051 7164 Resolved
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8 6 7 2 3 4 5 1 CK APPD 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. REV SCHEMATIC,MACBOOK PRO 17" ZONE ECN ENG APPD DESCRIPTION OF CHANGE DATE ? ? ? ? DATE ? 9/26/2006 D D (.CSA) DATE PAGE TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM CONTENTS SYNC 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 (.CSA) PAGE TABLE_TABLEOFCONTENTS_HEAD N/A Table of Contents N/A 2 System Block Diagram (MASTER) Power Block Diagram (MASTER) 3 4 BOM CONFIGURATION (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) 5 Functional / ICT Test (MASTER) 6 Signal Aliases (MASTER) 7 CPU 1 OF 2-FSB M59_MLB CPU 2 OF 2-PWR/GND M59_MLB 8 9 CPU Decoupling & VID 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM M59_MLB 10 CPU MISC1-TEMP SENSOR M59_MLB 11 CPU ITP700FLEX DEBUG (MASTER) 12 NB CPU Interface M59_MLB 13 NB PEG / Video Interfaces M59_MLB 14 NB Misc Interfaces M59_MLB NB DDR2 Interfaces M59_MLB 15 16 NB Power 1 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 08/08/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM M59_MLB 17 NB Power 2 M59_MLB 18 NB Grounds M59_MLB 19 NB (GM) Decoupling M57_MLB_MG 20 NB Config Straps M59_MLB 21 SB: 1 OF 4 M59_MLB SB: 2 of 4 M59_MLB 22 23 SB: 3 OF 4 08/08/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM M57_MLB_MG 24 SB: 4 OF 4 M59_MLB 25 SB Decoupling M59_MLB 26 SB Misc (MASTER) 27 M57 SMBUS CONNECTIONS (MASTER) 28 DDR2 SO-DIMM Connector A M59_MLB DDR2 SO-DIMM Connector B M59_MLB 29 30 Memory Active Termination (MASTER) TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) 31 Memory Vtt Supply M59_MLB 32 DDR2 VRef M59_MLB 33 CLOCKS M59_MLB 34 Clock Termination M59_MLB 37 Mobile Clocking M59_MLB PATA Connector (MASTER) 38 39 FireWire Link (TSB83AA22) M59_MLB 40 FireWire PHY (TSB83AA22) M59_MLB 41 ETHERNET CONTROLLER M59_MLB 42 Ethernet Connector M59_MLB Yukon Power Control M59_MLB 43 44 FW PHY Power Supply 09/15/2006 TABLE_TABLEOFCONTENTS_ITEM (MASTER) TABLE_TABLEOFCONTENTS_ITEM M59_MLB 45 FireWire Port Power DATE (MASTER) TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 CONTENTS SYNC 46 06/27/2006 FireWire Ports M59_MLB Camera Connector M59_MLB Internal USB Hub (MASTER) External USB Connector M59_MLB Left I/O Board Connector (MASTER) Current & Thermal Sensors (MASTER) PCI-E Connections (MASTER) SMC M59_MLB SMC Support M59_MLB LPC+ Debug Connector (MASTER) Thermal Sensors M59_MLB Current & Voltage Sensing M59_MLB SPI BOOTROM M59_MLB ALS Support (MASTER) Fan Connectors (MASTER) Sudden Motion Sensor (SMS) M59_MLB TPM M59_MLB IMVP6 CPU VCore Regulator M59_MLB 5V / 1.5V Power Supply M59_MLB 2.5V & 1.2V Regulators M59_MLB 1.8V Supply (MASTER) 3.3V / 1.05V Power Supplies (MASTER) 3.3V G3Hot Supply & Power Control M59_MLB Power Aliases (MASTER) DC-In & Battery Connectors (MASTER) PBus Supply & Batt. Charger M59_LIO ATI M56 PCI-E (MASTER) GPU (M56) Core Supplies (MASTER) ATI M56 Core Power (MASTER) ATI M56 Frame Buffer I/F (MASTER) GPU Straps M57_MLB_MG GDDR3 Frame Buffer A (MASTER) GDDR3 Frame Buffer B (MASTER) ATI M56 GPIO/DVO/Misc (MASTER) 49 09/15/2006 50 (MASTER) 52 09/15/2006 55 (MASTER) 56 (MASTER) 57 (MASTER) 58 09/15/2006 59 09/15/2006 60 (MASTER) 61 09/15/2006 62 09/15/2006 63 09/15/2006 64 (MASTER) 65 (MASTER) 66 C 09/15/2006 67 09/15/2006 75 09/15/2006 76 09/15/2006 77 09/15/2006 78 (MASTER) 79 (MASTER) 80 09/15/2006 81 (MASTER) 82 (MASTER) 83 09/15/2006 84 (MASTER) 85 (MASTER) 86 (MASTER) 87 (MASTER) 88 08/08/2006 89 (MASTER) 90 (MASTER) 91 B (MASTER) 93 (MASTER) ATI M56 Video Interfaces (MASTER) Internal Display Connectors M57_MLB_MG External Display Connector M59_MLB M57 SPECIFIC CONNECTORS (MASTER) LVDS Interface Pull-downs M59_MLB Revision History (MASTER) Napa Platform Constraints (MASTER) More System Constraints (MASTER) M9 Spacing & Physical Constraints (MASTER) M57 NET PROPERTIES (MASTER) 94 08/08/2006 97 09/15/2006 98 (MASTER) 99 09/15/2006 100 (MASTER) 101 (MASTER) 102 (MASTER) 103 (MASTER) 104 (MASTER) TABLE_TABLEOFCONTENTS_ITEM ALIASES RESOLVED DIMENSIONS ARE IN MILLIMETERS A Apple Computer Inc. METRIC XX X.XX DRAFTER Schematic / PCB #’s PART NUMBER THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING QTY ENG APPD MFG APPD QA APPD DESIGNER RELEASE SCALE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART ANGLES DESCRIPTION REFERENCE DES CRITICAL 051-7164 1 SCHEM,TRUCKEE,M57 SCH CRITICAL 820-2059 1 PCBF,TRUCKEE,M57 PCB CRITICAL A NOTICE OF PROPRIETARY PROPERTY DESIGN CK X.XXX BOM OPTION TITLE DO NOT SCALE DRAWING SCHEMATIC,MACBOOK PRO 17 NONE DRAWING SIZE TITLE=TRUCKEE ABBREV=DRAWING THIRD ANGLE PROJECTION LAST_MODIFIED=Tue Sep 26 13:17:56 2006 8 7 6 5 4 3 MATERIAL/FINISH NOTED AS APPLICABLE D DRAWING NUMBER REV. 051-7164 06004 SHT 2 1 1 OF 87 8 6 7 GDDR3 Core Duo (Merom) CPU Frame Buffer THERMAL 128MB/256MB SENSOR 2 3 4 5 1 ITP700FLEX CPU Debug Connector 479 BGA INVERTER P.75-76 PWM P.10 P.11 CONNECTOR D P.7-9 D P.79 J2800 LCD Panel Dual-Channel LVDS FSB ATI M56P DDR2 SO-DIMM A Expansion/Lower Connector P.79,82 GPU S-Video/Composite DVI-I/DL Connector w/TV-Out Support PCIe x16 CH.A 945GM NB Dual-Channel TMDS P.80 P.70-74,77-78 LVDS Graphics MUX P.28 J2900 DDR2 SO-DIMM B CH.B DDR2 VTT Factory/Upper Connector P.78 & REGULATOR 1466UFCBGA P.29 RJ45 (Ethernet) ENET Yukon Gig-E Connector Yukon Power Controller P.41 BUFFER P.39 P.40 P.32 DMI x4 1394a/b (FireWire) FW TSB83AA22 FireWire Connectors C P.44 Controller P.37-38 Port Power P.43 Right USB 2.0 P.30-31 DDR2 VREF P.12-20 C PCIe x1 PCI PHY Power ICH7-M P.42 PCIe x1 USB Connector P.47 PCIe x1 USB 2.0 Hub/Sleep LED IR USB Left I/O & Connector SB P.46,81 HDD/BT Connectors SATA USB USB x2 Audio Board Connector USB P.81 Azalia (HD-Audio) P.48 Camera Connector 609 BGA USB P.45 P.21-26 B B Geyser KB / USB SMBus TP Connector Batt Chgr/ PBUS Supply P.45 ODD Connector PATA P.69 66MHZ 16BITS LPC 33MHZ P.36 BootROM Power SPI TPM P.56 CK410 Clock Controller SB SMBus H8S/2116 P.27 P.33-34 P.61-68,71 Connector P. 60 Temperature P.53 System Block Diagram RT ALS SMC SMBus Sensors A Supplies LPC Debug SMC SMBus x5 P.57 SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY P.27 P.48,54 SMS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING P.59 Battery SMBus Fan Connector PWM/Tach Connectors II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART Analog P.58 P.68 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE P.51-52 SIZE Sensors P.55 APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 2 1 87 A 8 6 7 5 3 4 2 1 U8000 ENABLE J8290 Q7610 3.425 MLB DC in PPDCIN_G3H PP5V_S3 PP3V42_G3H G3Hot Connector 18.5V - 9V 5.0V 3.425V (LT3470) Q3820 SMC_PM_G2_ENABLE D D PP5V_S0_IDE_ODD ENABLE 1.5V 5V U8300 Q8250 PM_SLP_S3_L PM_SLP_S4_LS5V 5.0V Q7615 U7600 ENABLES PP18V5_G3H_CHGR 5.0V PBUS PPBUS_G3H 5V/1.5V SUPPLY 12.6 - 9V PP5V_S5 PP5V_S0 5.0V 5.0V ODD_PWR_EN_L (SB GPIO14) S5S0 (ISL6255AHRZ) Q4300 (LTC3728) ACIN_ENABLE_DIV_L J8290 PPBUS_G3H LIO Power Connector 12.6V - 9V PP1V5_S0 1.5V PP3V3_S3AC PM_SLP_S3_LS5V PGOOD 3.3V Q7945 NC SMC_PM_G2_ENABLE PP3V3_S3 PM_SLP_S3BATT 3.3V U7900 IMVP_VR_ON Q7720 ENABLE IMVP_PWRGD_IN C 2.5V PM_SLP_S4_LS5V PP3V3_S5 ENABLES C PP2V5_S0 3.3V U7530 S5 3.3V CPU VCore S0 (ISL9504) PM_SLP_S3BATT U7700 ENABLE (ISL6269B) PPVCORE_S0_CPU PGOOD PM_SLP_S3_LS5V_L Q7721 1.25V - 0.8V RSMRST_PWRGD "IMVP6" 2.5V PM_SLP_S3_L PGOOD S3 PP2V5_D3C 2.5V 2.5V (TPS62510) U7950 VR_PWRGOOD_DELAY PP2V5_S3 ENABLE J9450 PGOOD 1.05V Inverter P1V2R2V5DC3_EN_LS5V NC PM_SLP_S3BATT U7750 PP1V05_S0 S0 Connector 1.05V (ISL6269B) PM_SLP_S4_L B ENABLE 1.2V ENABLE IMVP_PWRGD_IN/ALL_SYS_PWRGD U8500 1.8V PP1V2_D3C 1.2V 1.2V (LTC3412) PP1V8_S3 S3 PP1V2_S3 S3 =GPUVCORE_EN_L 1.8V PGOOD ENABLE (TPS5117RGY) B Q7770 PGOOD U7800 P1V2R2V5D3C_EN_LS5V NC GPU VCore PGOOD PPVCORE_S0_GPU Q7947 S0 NC 1.1V - 0.95V PP3V3_S0 (ISL6269B) 3.3V PGOOD PM_SLP_S3_L NC Power Block Diagram U3100 PM_SLP_S3_LS5V ENABLE A SYNC_MASTER=(MASTER) Q7845 0.9V (Vtt) PP0V9_S0 PP1V8_D3C 0.9V 1.8V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING PPBUS_S5_FWPORT S0 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT (TPS51100) 12.6V - 9V III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. PM_SLP_S3_LS5V_L 8 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY Q4565 7 6 4 SHT NONE 3 2 REV. 051-7164 SCALE FWPWR_EN 5 DRAWING NUMBER D 06004 OF 3 1 87 A 8 6 7 PART NUMBER QTY 338S0270 1 338S0274 341S1931 DESCRIPTION 2 3 4 5 REFERENCE DES CRITICAL 1 BOM OPTION IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO U4101 CRITICAL 1 IC,SMC,HS8/2116 U5800 CRITICAL SMC_BLANK 1 IC,PRGRM,SMC(NEW),M57 U5800 CRITICAL SMC_PRGRM 341S1797 1 IC,EEPROM,SERIAL IIC,8KBIT,SO8 U4102 CRITICAL TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS 630-7814 TRUCKEE,2.33GHZ,B2,256VRAM,SAM,M57 VRAM_256SAM,M57_COMMON,CPU_2_33GHZ_B2,EEE_WJK 335S0384 1 IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8 U6301 CRITICAL BOOTROM_BLANK 341S1924 1 IC, BOOTROM, DEVELOPMENT, UNLOCKED ,M57 U6301 CRITICAL BOOTROM_DEVEL 341S1925 1 IC, BOOTROM, FINAL, LOCKED, M57 U6301 CRITICAL BOOTROM_FINAL 353S1461 1 IC,ISL9504,SYNC REG CTL,QFN 48 U7530 CRITICAL 359S0109 1 IC,LOW POWER CLOCK SYNTHESIZER,68PIN U3301 CRITICAL TABLE_BOMGROUP_ITEM D PART NUMBER 341S1789 PART NUMBER TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS QTY 1 QTY DESCRIPTION REFERENCE DES IC, TPM, 28-PIN TSSOP U6700 CRITICAL BOM OPTION CRITICAL DESCRIPTION REFERENCE DES 337S3393 1 IC,MDC,B2,PRQ,2.33GHZ,34W,667M,4M,479 BGA U0700 CRITICAL 338S0269 1 IC,945GM,NORTHBRIDGE U1200 CRITICAL 343S0385 1 IC,ICH7M,BGA U2100 CRITICAL D TPM CRITICAL BOM OPTION CPU_2_33GHZ_B2 TABLE_BOMGROUP_ITEM VRAM_128SAM VRAM_128_SAMSUNG VRAM_256SAM GPU_MEM_256M,VRAM_256_SAMSUNG BOM GROUP BOM OPTIONS M57_COMMON ALTERNATE,COMMON,M57_COMMON1,M57_COMMON2,M57_COMMON3,M57_COMMON4,M57_DEBUG M57_COMMON1 ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3,ISL6255A,NO_3G M57_COMMON2 KBDLED_HAS,MEMVREF_S3,MEMVTT_EN_PU,RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM C C TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM M57_COMMON3 LVDS_PD,FW_PORT_FAULT_PU M57_COMMON4 BOOTROM_DEVEL,SMC_PRGRM M57_DEBUG ITP,LPCPLUS M57_TPM TPM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM Extra TPM options: SMC_TPM_GPIO2 SMC_TPM_GPIO1 SMC_TPM_PP BAR CODE LABELS / EEE #’S PART NUMBER 826-4393 QTY 1 DESCRIPTION REFERENCE DES CRITICAL LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:WJK] CRITICAL BOM OPTION EEE_WJK B B MODULE PARTS PART NUMBER QTY 338S0368 1 DESCRIPTION REFERENCE DES CRITICAL IC,ATI,M56P,GRPHSCTRL,880BGA,LF U8400 CRITICAL BOM OPTION 333S0354 4 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_128_SAMSUNG 333S0350 4 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_256_SAMSUNG 333S0358 4 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_128_HYNIX 333S0351 4 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_256_HYNIX 333S0376 4 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_128_INFINEON 333S0377 4 IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA U8900,U8950,U9000,U9050 CRITICAL VRAM_256_INFINEON ALTERNATE PARTS TABLE_ALT_HEAD IS PART NUMBER ALTERNATE FOR PART NUMBER 376S0448 128S0083 BOM OPTION REF DES COMMENTS: 376S0445 ALL Si7806ADN for FDM6296 128S0073 C2516 1.86 MAX ALT TO 1.9 MAX 128S0093 128S0092 ALL KEMET IS ALT TO SANYO 353S1465 353S1461 ALL Screened ISL6262 for ISL9504 152S0287 152S0435 ALL Alternates for Coilcraft MSS5131 TABLE_ALT_ITEM BOM CONFIGURATION TABLE_ALT_ITEM TABLE_ALT_ITEM A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) TABLE_ALT_ITEM NOTICE OF PROPRIETARY PROPERTY TABLE_ALT_ITEM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 4 1 87 A 8 6 7 2 3 4 5 1 Power Supply NO_TESTs NO_TEST Functional Test Points EXPOSED_VIA TRUE IMVP6_RBIAS TRUE TRUE P5VS5_RUNSS P1V5S0_RUNSS TRUE TRUE P2V5S3_MODE P2V5S3_SHDNRT 61C7 Power Nets 62C4 66C6 I179 D TRUE TRUE P1V2S3_RT P1V2S3_RUNSS TRUE TRUE P1V8S3_COMP P1V8S3_FSET TRUE TRUE P3V3S5_COMP P3V3S5_FSET TRUE TRUE P1V05S0_COMP P1V05S0_FSET TRUE P3V42G3H_FB I178 I182 I183 63B6 I184 41C4 63B7 I185 I186 I267 I187 65C6 I188 65D6 I189 65A7 I190 65B7 I191 I192 66C3 I193 TRUE TRUE GPUVCORE_COMP GPUVCORE_FSET TRUE GPUBBP_ADJ Fan Connectors 71C7 I194 71C7 I195 I197 FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE FUNC_TEST PP0V9_S0 PP1V05_S0 PP1V2_D3C PP1V2_S3 PP1V5_S0 PP1V5_S0_NB PP1V8_S3 PP1V8_D3C PP2V5_S0 PP2V5_D3C PP3V3_S0 PP3V3_S3 PP3V3_S5 PP5V_S0 PP5V_S3 PP5V_S5 PPBUS_G3H GND 5A4 39A8 39D7 63B3 67D6 67D8 63C1 67A6 67A8 77A8 77C6 78C8 82D7 I199 I201 I202 I203 I204 C I205 I206 I207 I208 I209 I210 I211 I212 I213 I215 I214 I216 I217 I219 I218 I221 I220 I222 I223 I224 I225 TRUE TRUE FAN_LT_PWM FAN_LT_TACH B TRUE TRUE TRUE 65D8 66C5 67C3 67D3 67D5 79D5 24C3 25B6 25C8 25D2 26C5 11B5 22C6 22D8 23A7 23B7 23D1 23D4 23D8 24A5 24B3 56D4 63D8 65C8 65D1 65D2 5B2 45C3 52B8 62A2 67B1 67B3 81C4 81C6 66B8 66D8 67B1 67C1 67C3 25C8 47C7 52B5 62A4 62B2 62B6 62C8 64C8 65B7 65D6 71D7 5A1 41C6 42B8 43D8 55D3 61D4 61D7 62D7 64A6 64D7 65B7 65D6 67C1 67C3 68D5 69C1 71D7 79B7 IMVP_VR_ON IMVP_DPRSLPVR PM_SLP_S3_L PM_SLP_S3BATT PM_SLP_S4_L PM_SLP_S5_L P1V5P1V05S0_PGOOD CPU_DPRSTP_L IMVP6_VID<6..0> FSB_CLK_CPU_N FSB_CLK_CPU_P PLT_RST_L PLT_RST_L PEG_RESET_L SMC_LRESET_L TPM_LRESET_L CPU_STPCLK_L FSB_CLK_NB_P FSB_CLK_NB_N CLK_NB_OE_L NB_CLK100M_GCLKIN_P NB_CLK100M_GCLKIN_N NB_CLK_DREFCLKIN_P NB_CLK_DREFCLKIN_N NB_CLK_DREFSSCLKIN_P NB_CLK_DREFSSCLKIN_N CPU_THERMTRIP_R TP_SB_SUS_CLK 51D7 61C7 61C7 87C6 66C8 23C3 32B3 39C8 42A8 43C8 51C5 55C3 65B8 66B6 66C6 41B5 66B8 5C1 6A1 6A2 23C3 41B6 47C7 48C3 51C5 64C8 66A6 23C3 51C5 52A2 61C7 65B8 66B2 66B3 66B5 7B3 21C4 61C7 9C1 61C7 7C6 33C4 34D3 34D5 7C6 33C4 34D3 34D5 82A4 5C4 6C6 6C7 14B7 22A6 26A4 26B1 26C1 26C3 79A8 5C4 6C6 6C7 14B7 22A6 26A4 26B1 26C1 26C3 79A8 82A4 26B1 70A5 7C8 7D8 12C4 12D4 87D6 12A6 33C4 34D3 34D5 I142 I141 14C4 33B4 34C4 34C5 14C4 34B2 34B4 I140 14C4 34B2 34B4 I139 14B4 33B4 34B4 34B5 I143 14C4 33B4 34B4 34B5 I164 PP3V42_G3H PP5V_S0 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE LPC_AD<0> LPC_AD<1> LPC_FRAME_L PM_CLKRUN_L BOOT_LPC_SPI_L SMC_TMS DEBUG_RST_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L FWH_INIT_L PCI_CLK_PORT80_LPC LPC_AD<2> LPC_AD<3> INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RST_L SMC_NMI SMC_RX_L SV_SET_UP 7C8 7D8 12C4 87C6 I227 7D6 12C4 87D6 I228 7D6 12C4 87D6 I229 7B3 7B4 7C3 7C4 12B6 12C6 12D6 87D6 I230 7D6 12B4 87D6 I231 7B3 7B4 7C3 7C4 12B4 87D6 I232 7D6 12B4 87D6 I233 7B3 7B4 7C3 7C4 12B4 87D6 I235 7B3 7B4 7C3 7C4 12B4 87D6 I234 7D6 12B4 87D6 I236 7D6 12B4 87D6 I237 7D6 12B4 87D6 I238 7D8 12A4 12B4 87D6 I239 I241 I242 I243 opening for use as engineering probe point. I244 I245 Misc EXPOSED_VIA Nets I246 I247 EXPOSED_VIA I280 I248 DMI_N2S_P<1..0> DMI_N2S_N<1..0> SB_CLK100M_SATA_P SB_CLK100M_SATA_N USB_BT_P USB_BT_N I250 14B4 22D2 I249 14B4 22D2 I251 21B6 33B4 34C3 34C5 I253 21B6 33B4 34C3 34C5 I252 6C1 6C2 6C3 22C2 81A4 I254 6C1 6C2 6C3 22C2 81A4 I256 I255 I257 I258 Misc NO_TESTs NO_TEST I259 I260 EXPOSED_VIA I261 I281 I282 I283 TRUE TRUE TRUE USB2_CAMERA_P_F USB2_CAMERA_N_F TP_FW_CTL<0> 45B5 I263 45B5 I262 37C3 I264 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I165 22B3 51C7 53B4 I166 51B5 52B2 53B4 26B1 53B4 51C1 53B4 51B5 52B2 53B4 51C1 53B4 47B5 51C7 52B2 52B3 53B4 21C4 51D5 52D3 52D5 53C5 I138 34D6 53C5 21D4 51C7 53C5 60C6 21D4 51C7 53C5 60C6 23C8 51C7 53C5 60C6 23C5 51C5 52A2 53B5 60C6 51B5 52B2 53B5 51C5 52B2 53B5 51C3 52D6 53B5 51C1 53B5 47B5 51C7 52B2 52B3 53B5 23B6 23C3 53B5 PP5V_S0_ISENSECAL PP1V8_S3 PP1V05_S0 PPVCORE_S0_CPU PPVCORE_D3C_GPU ISENSE_CAL_EN GND TRUE TRUE TRUE TRUE TRUE TRUE TRUE 67D8 34C8 55A4 65A2 67D6 25C4 25D3 34B8 34C6 19D7 21C1 24C3 24D3 19D1 19D2 19D5 19D6 16D3 17D3 17D6 19C8 12B7 12C2 13B5 16C8 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 8B5 8D7 9D7 55A6 55D7 61D1 67D1 67D3 55A5 55C7 67A6 67A8 71B7 71C1 72D8 77A7 51B7 55A8 FUNC_TEST I286 7B3 21C4 87C6 I169 21C4 I269 PP5V_S3 USB2_CAMERA_N USB2_CAMERA_P PP5V_S3_CAMERA_F TRUE TRUE TRUE TRUE 5D4 45C3 52B8 62A2 67B1 67B3 81C4 81C6 6D1 6D2 6D3 22C2 45C3 6D1 6D2 6D3 22C2 45B3 I285 45C5 14B7 23C3 61C8 87C6 7 6 5 4 62A8 62C1 66C5 25B6 25C2 25C6 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25C8 25D6 48B6 67C6 67C8 PP1V5_S0 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE ALS_GAIN LTALS_OUT ACZ_SDATAIN<0> ACZ_SDATAOUT ACZ_BITCLK ACZ_RST_L EXCARD_OC_L LTUSB_OC_L LT2USB_OC_L PM_SLP_S3_LS5V PM_SLP_S4_L SYS_ONEWIRE MINI_CLKREQ_L SMC_EXCARD_CP EXCARD_CLKREQ_L SMC_EXCARD_PWR_EN LIO_PLT_RESET_L ACZ_SYNC USB2_LT_N USB2_LT_P USB2_EXCARD_N USB2_EXCARD_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N USB2_LT2_N USB2_LT2_P PCIE_MINI_R2D_C_N PCIE_MINI_R2D_C_P PCIE_MINI_D2R_N PCIE_MINI_D2R_P PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N SMBUS_SB_SCL SMBUS_SB_SDA PCIE_WAKE_L SMC_BC_ACOK SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA 6D5 48C4 51B5 48C3 57C7 21C7 48B3 87B4 21C7 48B3 87B4 21C7 48B3 87B4 21C7 48B3 87B4 6C1 6C3 22C4 22D8 48C3 52B3 6D1 6D3 22C4 22D8 48C3 6C1 6C3 22C4 22D8 48C3 6A1 6A2 48C3 62B3 66C6 66C7 64C8 5C4 6A1 6A2 23C3 41B6 47C7 48C3 51C5 66A6 66B8 48C3 51B7 52B2 33B4 34A3 34A4 48C3 48C3 51B7 52A2 C 33B4 34A3 34A4 48C3 48C3 51B7 26C1 48C3 21C7 48B3 87B4 6D1 6D2 6D3 22C2 48C6 6D1 6D2 6D3 22C2 48C6 6C1 6C2 6C3 22C2 48C6 6C1 6C2 6C3 22C2 48C6 48B6 50C5 50C6 48B6 50C5 50C6 22D4 50B5 22D4 50C5 48B6 50B3 50B6 48B6 50C3 50C6 33B4 34C3 34C5 48B6 33B4 34B3 34B5 48B6 6C1 6C2 6C3 22C2 48C6 6C1 6C2 6C3 22C2 48C6 48C6 50C5 50C6 48C6 50C5 50C6 22D4 50C5 22D4 50C5 33B4 48C6 48C6 50C3 50C6 48C6 50C3 50C6 34D4 34D5 33B4 34D4 34D5 48C6 46B6 48B3 81C3 28A6 29A6 33B6 23D5 27B6 27C6 27D6 27D7 27D8 23C8 39C6 48C3 48C3 51C5 52A2 68A6 69A6 81C3 27C3 27C5 27C6 48B6 51B5 81C3 81C3 48B3 33B6 28A6 27D7 27C6 23D5 27B6 27D6 27D8 29A6 46B6 B 27B3 27C3 27C5 27C6 48B6 51B5 Inverter Connector 7B3 21C4 87C6 D 27C1 27C2 27C3 51B5 68B2 TRUE 23C3 51D7 22A6 37C2 I273 23C1 51D7 I275 23C3 26A6 I277 21D6 26D4 I276 23C8 33C4 I278 GND_CHASSIS_INVERTER PPBUS_S0_INVERTER PP5V_INVERTER_SW INVERTER_PWM GND_CHASSIS_INVERTER TRUE TRUE TRUE TRUE TRUE 5B2 6A6 6A8 45B5 45C5 79A5 79A6 Left I/O Power Connector 79B5 79B5 FUNC_TEST 79A5 5B2 6A6 6A8 45B5 45C5 79A5 79A6 23C8 33C4 TRUE TRUE PP18V5_DCIN PPBUS_G3H TRUE GND 68B8 68C5 61D7 62D7 64A6 5C4 41C6 42B8 43D8 55D3 61D4 64D7 65B7 65D6 67C1 67C3 68D5 69C1 71D7 79B7 23C5 26B8 14B6 26B5 61C7 7D6 11B5 12C4 87D6 7A3 12A4 Request for at least 10 GND test points 7B3 12B4 87D6 14B6 22A6 78C7 78C7 78C7 78B7 78B7 66B6 54D4 33C7 78B7 26B4 24B3 20A4 20B4 5D4 10C5 14C7 14D6 21C3 21D3 25B8 25C4 27D5 27D8 49B5 49C4 62A6 65B3 82A4 82B3 33C5 67A3 67B3 67C3 67C5 71D2 79A8 79D3 57B6 58C4 58C7 60C7 60D4 61A5 61D8 33D3 33D8 34A8 36D6 40B6 26B6 26B8 26D1 27C3 27D3 24B5 24C3 24D3 25A4 25B4 Thermal Sensors FUNC_TEST (=PP3V3_S0_CK410) 17C6 19C6 19C7 TRUE 22B5 23B3 23D5 I173 25C6 25D3 25D8 28A6 29A3 29A6 TRUE 49C7 52D3 54B5 I174 65D6 66B1 66B5 TRUE 82C6 82D5 I172 TRUE I175 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 38D5 HSTHMSNS_DX_P HSTHMSNS_DX_N RSFSTHMSNS_D_P RSFSTHMSNS_D_N Functional / ICT Test 54C5 SYNC_MASTER=(MASTER) 54D5 54C5 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING SMC TPs FUNC_TEST I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 38C6 6C3 6C5 6C6 38B2 38D5 42C1 I177 38D3 I176 PM_SYSRST_L SMC_ONOFF_L TRUE TRUE (=PP1V2_S3_ENET) (=PP3V3_S3_ENET) (=PP2V5_S3_ENET) II NOT TO REPRODUCE OR COPY IT 23C5 26C5 51B7 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 51C5 52B2 52C6 81C4 SIZE 5D4 39A8 39D7 63B3 67D6 67D8 39A5 39B4 39B5 39B8 39D6 39D8 41C4 67D1 67D3 39D3 63C3 63D3 63D4 67B6 67B8 APPLE COMPUTER INC. DRAWING NUMBER D SCALE 39D5 40D5 3 2 REV. 051-7164 SHT NONE 8 51C5 52B2 68B2 27C1 27C2 27C3 51B5 68B2 21C5 51C7 53C4 60C6 6C6 6C7 23C3 CPU_PWRGD TP_CPU_CPUSLP_L PM_DPRSLPVR CPU_DPSLP_L PM_LAN_ENABLE PCI_RST_L PM_RSMRST_L PM_SB_PWROK SB_RTC_RST_L PM_STPCPU_L PM_STPPCI_L VR_PWRGD_CK410 VR_PWRGOOD_DELAY FSB_CPURST_L FSB_SLPCPU_L FSB_DPWR_L NB_SB_SYNC_L PP2V5_S0_GPU_TPVDD PP2V5_S0_GPU_TXVDDR PP2V5_S0_GPU_AVDD PP2V5_S0_GPU_A2VDD PP2V5_S0_GPU_LPVDD PP2V5_S0_GPU_LVDDR PP3V3_S0 PP3V3_S0_CK410_VDD48 PP3V3_S0_CK410_VDD_PCI PP3V3_S0_CK410_VDD_REF PP3V3_S0_CK410_VDD_CPU_SRC PP3V3_S0_CK410_VDDA PP3V3_FWPHY PP3V3_FWPHY_AVDD PP3V3_FWPHY_PLLVDD PP1V95_FWPHY PP1V95_FWPHY_PLLVDD PP1V2_S3 PP3V3_S3AC PP2V5_S3 PP2V5_S3_ENET_AVDD 68B1 68B2 21D4 51D7 53C4 60C6 23C8 51C5 53C4 60C6 Request for at least 2 GND TPs per resistor I167 SMC_BS_ALRT_L SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA 21D4 51D7 53C4 60C6 21C2 I168 TRUE TRUE TRUE 68A1 68A2 69B1 FUNC_TEST TRUE TRUE FUNC_TEST 14C4 33B4 34C4 34C5 BATT_POS BATT_NEG Left I/O Data Connector 12A6 33C4 34D3 34D5 14B6 33B4 TRUE TRUE 66D2 67D3 67D5 68B8 69A8 69B8 69C8 81D4 26D6 27C3 35B7 47B5 51C2 51D3 51D4 52B1 52B5 52B7 52D7 53C4 66A8 66C8 67B3 71A6 79B8 80A1 80B5 81B3 5D2 5D4 25D8 31C5 36D6 53C4 55A8 57B5 58C4 58C7 61D7 62B1 66B5 67A1 67B1 Resistor Calibration 7C8 21C4 87C6 FUNC_TEST should have a via with 10-mil soldermask I279 58B3 26B1 60B7 7D6 12C4 87D6 I240 A 58B3 26B1 51C7 MAC-1 TPs FSB_A_L<31..3> FSB_ADS_L FSB_ADSTB_L<1..0> FSB_BNR_L FSB_BREQ0_L FSB_D_L<63..0> FSB_DBSY_L FSB_DINV_L<3..0> FSB_DRDY_L FSB_DSTBN_L<3..0> FSB_DSTBP_L<3..0> FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L<4..0> EXPOSED_VIA property indicates that the net TRUE TRUE TRUE TRUE TRUE TRUE 58B6 Camera Connector EXPOSED_VIA TRUE I135 58B6 LPC+ Debug Connector CPU FSB NO_TESTs TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE FAN_RT_PWM FAN_RT_TACH 71A6 79B8 80A1 80B5 81B3 58C4 58C7 61D7 62B1 5D2 5D4 25D8 31C5 I134 36D6 53C4 55A8 57B5 66B5 67A1 67B1 67B3 FUNC_TEST Characterization TPs I200 PP5V_S0 TRUE TRUE FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 19A5 19B5 19B8 19C1 19C4 13C5 13D2 16D1 17B6 17C6 31C5 32C6 37B2 64A6 64C1 5B2 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 67B6 67B8 64A4 67B6 67B8 72B8 73A5 73A8 73B5 73B8 75D5 75D8 76D5 76D8 82D7 17C6 17D6 19A4 19A6 19A8 19C5 19D7 63D1 66B5 67A6 67A8 67B6 82C5 82D3 71B7 I198 FUNC_TEST 25D3 34B8 34C6 34C8 55A4 65A2 67D6 67D8 13B5 16C8 16D3 17D3 17D6 5B2 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 19C8 19D1 19D2 19D5 19D6 19D7 21C1 24C3 24D3 25C4 Request for at least 10 GND TPs NO_TEST Battery Connector 62C5 66A6 06004 OF 5 1 87 A 8 6 7 2 3 4 5 1 USB Port "A" (Debug Port) = Right USB 2.0 Port R0600 51B5 48C4 5C1 ALS_GAIN 0 1 RTALS_GAIN 2 NC_CPU_A32_L NC_CPU_A32_L 6D7 7C8 MAKE_BASE=TRUE 6D8 7C8 28C3 NC_CPU_A33_L NC_CPU_A33_L 6D7 7B8 MAKE_BASE=TRUE 6D8 7B8 29C3 MEM_A_A<15..14> 39C8 6D4 NC_ENET_CTRL12 MEM_B_A<15..14> 39C8 6D4 NC_ENET_CTRL25 NC_MEM_B_A<15..14> NC_CPU_A34_L NC_CPU_A34_L 6D7 7B8 MAKE_BASE=TRUE 6D8 7B8 TP_NB_CFG<4..3> NO_TEST=TRUE NC_CPU_A35_L NC_CPU_A35_L 6D8 7B8 NO_TEST=TRUE 47C5 22D8 22C4 6D2 6D1 47C5 22D8 22C4 6D3 6D1 RTUSB_OC_L NC_CPU_A36_L 6D8 7B8 NC_CPU_A37_L 6D8 7B8 NC_ENET_CTRL12 6D5 39C8 NC_ENET_CTRL25 6D5 39C8 USB_TRACKPAD_P 81C4 22C2 6D3 6D1 81C4 22C2 6D2 6D1 USB_TRACKPAD_N 81C4 22C2 6D3 6D1 81C4 22C2 6D2 6D1 14C6 22D8 22C4 6D1 NB_CFG<6> 14C6 NC_CPU_A38_L 6D8 7B8 NB_CFG<8> 14C6 NC_CPU_A39_L 6D8 7B8 ENET_LOWPWR_EN UNUSED_USB_B_OC_L USB2_LT_P 48C6 22C2 6D3 6D1 5C1 48C6 22C2 6D2 6D1 5C1 USB2_LT_N 48C6 22C2 6D3 6D1 5C1 48C6 22C2 6D2 6D1 5C1 NB_CFG<11..10> 14C6 22D8 22C4 0 SB_GPIO30 1 TP_NB_CFG<15..14> NB_CFG<15..14> TP_NB_CFG<17> NO_TEST=TRUE NB_CFG<17> 14C6 39B8 NC_CPU_APM0_L 6D8 7B8 6D2 6D3 22C2 81C4 USB_TRACKPAD_N 6D2 6D3 22C2 81C4 UNUSED_USB_B_OC_L 6D3 22C4 22D8 USB2_LT_P USB2_LT_P NOTE: NB_CFG<13..12> require test access USB2_LT_N D 5C1 6D2 6D3 22C2 48C6 USB2_LT_N LTUSB_OC_L 5C1 6D2 6D3 22C2 48C6 LTUSB_OC_L 5C1 6D3 22C4 22D8 48C3 MAKE_BASE=TRUE USB Port "D" = Camera NOTE: BOM options "USB_G_OC_PU" and "ENET_LOWPWR_EN" are mutually-exclusive. MAKE_BASE=TRUE NC_CPU_APM0_L USB_TRACKPAD_P MAKE_BASE=TRUE ENET_LOWPWR_EN 5% 1/16W MF-LF 402 MAKE_BASE=TRUE 6D7 7B8 MAKE_BASE=TRUE 2 48C3 22D8 22C4 6D1 5C1 14C6 NC_CPU_A39_L USB_TRACKPAD_N MAKE_BASE=TRUE TP_NB_CFG<11..10> NO_TEST=TRUE 6D7 7B8 MAKE_BASE=TRUE USB_TRACKPAD_P USB Port "C" = Left USB 2.0 Port MAKE_BASE=TRUE NC_CPU_A38_L 6D2 6D3 22C4 22D8 47C5 MAKE_BASE=TRUE R0690 NO_TEST=TRUE 6D7 7B8 MAKE_BASE=TRUE 6D2 6D3 22C2 47B5 RTUSB_OC_L MAKE_BASE=TRUE MAKE_BASE=TRUE NC_CPU_A37_L RTUSB_OC_L USB Port "B" = Trackpad (Geyser) Ethernet Powr Management Support TP_NB_CFG<8> NO_TEST=TRUE 6D7 7B8 MAKE_BASE=TRUE 6D2 6D3 22C2 47B5 USB2_RT_N MAKE_BASE=TRUE MAKE_BASE=TRUE NC_CPU_A36_L 6D7 7B8 MAKE_BASE=TRUE USB2_RT_P USB2_RT_N MAKE_BASE=TRUE MAKE_BASE=TRUE NB_CFG<4..3> TP_NB_CFG<6> USB2_RT_P MAKE_BASE=TRUE 47B5 22C2 6D2 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE 6D7 7B8 MAKE_BASE=TRUE 47B5 22C2 6D3 6D1 47B5 22C2 6D3 6D1 6D4 57C4 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE D NC_MEM_A_A<15..14> MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE USB2_RT_P 6D1 USB2_RT_N 47B5 22C2 6D2 6D1 RTALS_GAIN MAKE_BASE=TRUE 5% 1/16W MF-LF 402 USB2_CAMERA_P 45B3 22C2 6D3 6D1 5B2 45B3 22C2 6D2 6D1 5B2 USB2_CAMERA_N 45C3 22C2 6D3 6D1 5B2 45C3 22C2 6D2 6D1 5B2 USB2_CAMERA_P USB2_CAMERA_P 5B2 6D2 6D3 22C2 45B3 USB2_CAMERA_N 5B2 6D2 6D3 22C2 45C3 UNUSED_USB_D_OC_L 6C3 22C4 22D8 USB2_EXCARD_P 5C1 6C2 6C3 22C2 48C6 MAKE_BASE=TRUE NO_TEST=TRUE USB2_CAMERA_N MAKE_BASE=TRUE NC_CPU_APM1_L 6C7 7B8 MAKE_BASE=TRUE NC_CPU_APM1_L 6C8 7B8 NC_CPU_EXTBREF 6C8 7B6 NC_CPU_HFPLL 6C8 7B8 TP_NB_CFG<13..12> NB_CFG<13..12> 22D8 22C4 6C1 14C6 MAKE_BASE=TRUE UNUSED_USB_D_OC_L MAKE_BASE=TRUE NO_TEST=TRUE NC_CPU_EXTBREF 6C7 7B6 MAKE_BASE=TRUE NO_TEST=TRUE FireWire Aliases 23C3 6C6 5B4 NC_CPU_HFPLL 6C7 7B8 MAKE_BASE=TRUE TP_SB_SUS_CLK TP_SB_SUS_CLK 5B4 6C7 23C3 MAKE_BASE=TRUE NC_CPU_SPARE0 44D3 43B2 6C3 NC_CPU_SPARE0 USB2_EXCARD_N 48C6 22C2 6C3 6C1 5C1 48C6 22C2 6C2 6C1 5C1 PPFW_PORTA_VP_UF USB2_EXCARD_P PPFW_PORTB_VP_UF 52B3 48C3 22D8 22C4 6C1 5C1 PPFW_PORTB_VP_UF USB2_EXCARD_N USB2_EXCARD_N 5C1 6C2 6C3 22C2 48C6 MAKE_BASE=TRUE 6C5 43B2 44D3 MAKE_BASE=TRUE 44B3 43A2 6C3 NC_CPU_SPARE1 PPFW_PORTA_VP_UF 6C8 7B6 NO_TEST=TRUE 6C7 7B6 MAKE_BASE=TRUE USB2_EXCARD_P 48C6 22C2 6C3 6C1 5C1 48C6 22C2 6C2 6C1 5C1 MAKE_BASE=TRUE NO_TEST=TRUE 6C7 7B6 MAKE_BASE=TRUE USB Port "E" = ExpressCard EXCARD_OC_L EXCARD_OC_L 5C1 6C3 22C4 22D8 48C3 52B3 MAKE_BASE=TRUE 6C5 43A2 44B3 MAKE_BASE=TRUE NC_CPU_SPARE1 6C8 7B6 NC_CPU_SPARE2 6C8 7B6 NC_CPU_SPARE4 6C8 7B6 USB Port "F" = USB 1.1 Hub NO_TEST=TRUE NC_CPU_SPARE2 6C7 7B6 MAKE_BASE=TRUE 44B8 44A8 43B8 42C4 38D7 38B5 6C5 6C3 5A4 44B8 44A8 43B8 42C4 38D7 38B5 6C6 6C3 5A4 PP3V3_FWPHY NO_TEST=TRUE NC_CPU_SPARE4 6C7 7B6 MAKE_BASE=TRUE Inverter PWM Reset Alias PP3V3_FWPHY PP3V3_FWPHY VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.20 mm MAKE_BASE=TRUE PP3V3_FWPHY 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 PP3V3_FWPHY NO_TEST=TRUE C 82A4 79A8 26C3 26C1 26B1 26A4 22A6 14B7 6C6 5C4 PLT_RST_L PLT_RST_L 5C4 6C7 14B7 22A6 26A4 26B1 26C1 26C3 79A8 82A4 USB_HUB_P 46B7 46B3 22C2 6C3 6C1 USB_HUB_N 46B3 46A7 22C2 6C3 6C1 USB_HUB_P USB_HUB_N 6C2 6C3 22C2 46B3 46B7 USB_HUB_N 6C2 6C3 22C2 46A7 46B3 MAKE_BASE=TRUE 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 PP3V3_FWPHY USB_HUB_P MAKE_BASE=TRUE USB Port "G" = Bluetooth (M13P) 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 81A4 22C2 6C2 6C1 5A7 USB_BT_P 81A4 22C2 6C3 6C1 5A7 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 81A4 22C2 6C2 6C1 5A7 USB_BT_N 81A4 22C2 6C3 6C1 5A7 USB_BT_P USB_BT_P 5A7 6C2 6C3 22C2 81A4 USB_BT_N 5A7 6C2 6C3 22C2 81A4 C MAKE_BASE=TRUE PP3V3_FWPHY USB_BT_N MAKE_BASE=TRUE 42C1 38D5 38B2 6C5 6C3 5A4 PP1V95_FWPHY 42C1 38D5 38B2 6C6 6C3 5A4 PP1V95_FWPHY PP1V95_FWPHY VOLTAGE=1.95V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE PP1V95_FWPHY 5A4 6C3 6C5 6C6 38B2 38D5 42C1 USB Port "H" = 2nd Left USB 2.0 Port 5A4 6C3 6C5 6C6 38B2 38D5 42C1 48C6 22C2 6C2 6C1 5B1 USB2_LT2_P 48C6 22C2 6C3 6C1 5B1 5B1 USB2_LT2_N 48C6 22C2 6C3 6C1 5B1 USB2_LT2_P USB2_LT2_P 5B1 6C2 6C3 22C2 48C6 MAKE_BASE=TRUE 48C6 22C2 6C2 6C1 51D7 37A8 6C3 SMC_RSTGATE_L SMC_RSTGATE_L 6C5 37A8 51D7 48C3 22D8 22C4 6C1 5C1 MAKE_BASE=TRUE 37C6 22A7 PCI_AD<19> USB2_LT2_N USB2_LT2_N 5B1 6C2 6C3 22C2 48C6 MAKE_BASE=TRUE LT2USB_OC_L LT2USB_OC_L 5C1 6C3 22C4 22D8 48C3 MAKE_BASE=TRUE =FW_PCI_IDSEL 37B7 PCI_GNT3_L 6B5 22B6 37D3 46C3 6B2 TP_USB2_3G_P PCI_REQ3_L 6B5 22B6 26D2 37D3 46C3 6B2 TP_USB2_3G_N MAKE_BASE=TRUE 37D3 22B6 6B3 PCI_GNT3_L TP_USB2_3G_P MAKE_BASE=TRUE 37D3 26D2 22B6 6B3 6B3 46C3 MAKE_BASE=TRUE PCI_REQ3_L TP_USB2_3G_N MAKE_BASE=TRUE 6B3 46C3 MAKE_BASE=TRUE LVDS Pull Down Aliases Chassis connection to be made at the fan cutout near the right ALS. NO STUFF NO STUFF R0601 GND_CHASSIS_FANFRAME SH0601 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V 1 EMI-SPRING 1 0 Thermal Module Holes Not stuffed at Proto. 82C8 =LVDS_PD_L_CLK_N 82C8 =LVDS_PD_L_CLK_P 78A3 79D7 82C3 LVDS_L_DATA_N<1> 78A3 79D7 82C3 MAKE_BASE=TRUE Top CPU TM Hole 2 LVDS_L_DATA_P<1> MAKE_BASE=TRUE Add one through via per hole to GND or 2 blind vias per side per hole to GND Top GPU Right TM Hole 82D8 82C3 79D7 78A3 6B1 LVDS_L_DATA_P<0> 82D8 82C3 79D7 78A3 6B1 LVDS_L_DATA_N<0> LVDS_L_DATA_P<0> 6B2 78A3 79D7 82C3 82D8 MAKE_BASE=TRUE 5% 1/16W MF-LF 402 0G-502620R LVDS_L_DATA_N<0> 6B2 78A3 79D7 82C3 82D8 MAKE_BASE=TRUE 82D8 82C3 79D7 78A3 6B1 LVDS_L_CLK_N 82C8 82C3 79D7 78A3 6B1 LVDS_L_CLK_P LVDS_L_CLK_N 6B2 78A3 79D7 82C3 82D8 MAKE_BASE=TRUE Chassis connection to be made at the mounting hole northwest of the DVI connector. Plated hole. B ZT0600 195R106 82C8 GND_CHASSIS_DVI_TOP MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 82C8 C0600 GND_CHASSIS_DVI_TOP GND_CHASSIS_DVI_TOP GND 1 0.01UF 10% 50V 2 Chassis connection to be made on FW shell X7R 402 6B6 6A6 0 6B6 6B8 80A3 80A5 Left CPU TM Hole 44C1 HOLE-VIA-P5RP25 44A1 40B2 6A6 GND_CHASSIS_DVI_BOT GND_CHASSIS_DVI_BOT ZT0612 6A6 6B8 80A2 80B5 GND_CHASSIS_ENET =LVDS_PD_U_CLK_N 82B8 =LVDS_PD_U_CLK_P C0612 10% 50V 2 X7R 402 6A6 6A8 40B2 44A1 44C1 6A6 6A8 40B2 44A1 44C1 LVDS_U_DATA_P<0> 1 =LVDS_PD_U_DATA_P<1> 1 C0613 C0610 0.01UF 0.01UF 10% 2 50V X7R 402 10% 50V 2 X7R 402 1 82B8 C0611 82C3 82B8 79D7 78B3 6A1 10% 2 50V X7R 402 LVDS_U_CLK_N 82C3 82B8 79D7 78B3 6A1 LVDS_U_CLK_P 2 SHLD-SM-LF 3 8 6A2 78B3 79D7 82B8 82C3 MAKE_BASE=TRUE Base net is PM_SLP_S3_LS5V PM_SLP_S4_L MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 1 GND_CHASSIS_BATTCONN_HOLE C0619 6A6 6A8 44A1 44A3 47B2 1 0.01UF 10% 50V 2 X7R 402 6A6 6A8 44A1 44A3 47B2 6A6 6A8 44A1 44A3 47B2 PM_SLP_S4_L 66A6 64C8 51C5 48C3 47C7 41B6 23C3 6A1 5C4 5C1 66B8 1GND_CHASSIS_BATTCONN_HOLE 6A6 69A1 5C1 5C4 6A2 23C3 41B6 47C7 48C3 51C5 64C8 66A6 66B8 Base net is PM_SLP_S4_L 66C7 66C6 62B3 48C3 6A1 5C1 C0614 PM_SLP_S3_LS5V PM_SLP_S3_LS5V 5C1 6A2 48C3 62B3 66C6 66C7 0.01UF 10% 50V 2 X7R 402 Signal Aliases SYNC_MASTER=(MASTER) C0602 1 GND_CHASSIS_LVDS GND_CHASSIS_LVDS GND_CHASSIS_LVDS GND_CHASSIS_LVDS 6A6 6A8 79B2 79C3 79D2 79D3 6A6 6A8 79B2 79C3 79D2 79D3 ZT0610 ZT0614 HOLE-VIA-P5RP25 SYNC_DATE=(MASTER) MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V 6A6 6A8 79B2 79C3 79D2 79D3 GND_CHASSIS_INVERTER GND_CHASSIS_INVERTER GND_CHASSIS_INVERTER GND_CHASSIS_INVERTER GND_CHASSIS_INVERTER 7 5B2 6A6 6A8 45B5 45C5 79A5 79A6 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING HOLE-VIA-P5RP25 1GND_CHASSIS_LNDACARD_HOLE 6A6 6A8 79B2 79C3 79D2 79D3 1 1GND_CHASSIS_LEFT_DIMM_HOLE C0615 0.01UF OG-503040 6A2 78B3 79D7 82B8 82C3 LVDS_U_CLK_P NOTICE OF PROPRIETARY PROPERTY 10% 50V 2 X7R 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 78B3 79D7 82C3 LVDS_U_CLK_N MAKE_BASE=TRUE GND_CHASSIS_LVDS 0.01UF 79A6 79A5 45C5 45B5 6A6 5B2 78B3 79D7 82B3 LVDS_U_DATA_N<2> MAKE_BASE=TRUE 0.01UF ZT0602 1 6B2 78B3 79D7 82C3 82C8 LVDS_U_DATA_P<2> =LVDS_PD_U_DATA_N<1> Chassis connection to be made at the mounting hole east of the LVDS connector SH0600 6B2 78B3 79D7 82C3 82C8 LVDS_U_DATA_P<0> MAKE_BASE=TRUE ZT0611 GND_CHASSIS_USB MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 78B3 79D7 82C3 LVDS_U_DATA_N<0> MAKE_BASE=TRUE 82B8 HOLE-VIA-P5RP25 69A1 6A4 79B2 6A6 78B3 79D7 82C3 LVDS_U_DATA_P<1> LVDS_U_DATA_N<0> 6A6 6A8 40B2 44A1 44C1 ZT0601 195R106 79D3 79D2 HOLE-VIA-P5RP25 79C3 LVDS_U_DATA_N<1> MAKE_BASE=TRUE 82C8 82C3 79D7 78B3 6B1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V 0.01UF GND_CHASSIS_USB GND_CHASSIS_USB GND_CHASSIS_USB 82C8 82C3 79D7 78B3 6B1 1GND_CHASSIS_ODD_HOLE 1 GND_CHASSIS_ENET GND_CHASSIS_ENET GND_CHASSIS_ENET MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 82B8 HOLE-VIA-P5RP25 1GND_CHASSIS_LIOFLEX_HOLE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V Chassis connection to be made at the mounting hole southwest of the USB connector. Plated hole. 47B2 44A3 44A1 6A6 B 78A3 79D7 82C3 Lower Left GPU TM Hole ZT0613 HOLE-VIA-P5RP25 6B6 6B8 80A2 80B5 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE Right CPU TM Hole 6B6 6B8 80A3 80A5 Frame holes 2 ZT0604 1 78A3 79D7 82C3 LVDS_L_DATA_P<2> MAKE_BASE=TRUE R0602 1 =LVDS_PD_L_DATA_N<2> MAKE_BASE=TRUE GND_CHASSIS_DVI_BOT NO STUFF MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE A 6B2 78A3 79D7 82C3 82C8 LVDS_L_DATA_N<2> MAKE_BASE=TRUE ZT0603 80B5 HOLE-VIA-P5RP25 80A2 1 =LVDS_PD_L_DATA_P<2> MAKE_BASE=TRUE 80A5 80A3 6B6 1 LVDS_L_CLK_P MAKE_BASE=TRUE 10% 50V 2 X7R 402 1 C0616 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V 0.01UF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 1 C0617 0.01UF 10% 50V 2 X7R 402 10% 50V 2 X7R 402 1 II NOT TO REPRODUCE OR COPY IT C0618 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 0.01UF 10% 50V 2 X7R 402 SIZE APPLE COMPUTER INC. 5B2 6A6 6A8 45B5 45C5 79A5 79A6 LEFT CLUTCH BARREL CABLING SHT NONE 5B2 6A6 6A8 45B5 45C5 79A5 79A6 5 4 3 2 REV. 051-7164 SCALE 5B2 6A6 6A8 45B5 45C5 79A5 79A6 6 DRAWING NUMBER D 06004 OF 6 1 87 A 8 6 7 2 3 4 5 1 OMIT U0700 IO 87D6 12D4 5B7 IO 87D6 12D4 5B7 IO 87D6 12D4 5B7 IO 87D6 12C4 5B7 IO 87C6 12C4 5B7 IO 87D6 12B4 5A7 87D6 12B4 5A7 IO IO 87D6 12A4 5A7 IO 87D6 12C4 5B7 IO 87D6 12C4 5B7 IO 87D6 12C4 5B7 IO 87D6 12C4 5B7 IO 87D6 12C4 5B7 IO 87D6 12C4 5B7 87D6 12C4 5B7 87D6 12C4 5B7 87D6 12C4 5B7 87D6 12C4 5B7 87D6 12C4 5B7 87D6 12C4 5B7 87D6 12C4 5B7 87D6 12C4 5B7 C IO 87D6 12A4 5A7 87D6 12C4 5B7 87C6 12C4 5B7 87C6 21C4 21C2 87C6 21C4 87C6 21C4 5C4 87C6 21C4 87C6 21C4 87C6 21C4 P1 A15* R1 A16* L2 ADSTB0* FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4> IO 87D6 12A4 5A7 P2 A12* L1 A13* P4 A14* IO IO IO IO IO IO IO IO IO IO OUT IN IN IN IN W6 A20* U4 A21* Y5 A22* U2 A23* R4 A24* T5 A25* T3 A26* W3 A27* W5 A28* Y4 A29* W2 A30* Y1 A31* V4 ADSTB1* 6D8 6D8 6D8 6D8 6D8 6D8 6D8 6C8 D5 STPCLK* C6 LINT0 B4 LINT1 A3 SMI* 87D6 12B4 F1 87D6 12C4 5B7 87D6 12B4 FSB_BREQ0_L 54.9 1% 1/16W MF-LF 2 402 IO IO IO FSB_IERR_L 21C4 CPU_INIT_L IN FSB_LOCK_L IO INIT* D20 B3 LOCK* H4 87D6 12B4 5A7 RESET* RS0* B1 87D6 12C4 11B5 5A4 IN F3 F4 87D6 12A4 IN 87D6 12A4 IN G3 87D6 IN TRDY* G2 87D6 HIT* G6 E4 IERR* R0702 IO PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY 87C6 87C6 FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> 12A4 FSB_RS_L<2> 12A4 FSB_TRDY_L FSB_HIT_L 5B7 FSB_HITM_L PP1V05_S0 IN 87D6 12B4 5B7 IO 87D6 12B4 IO D 19D7 21C1 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 65A2 67D6 67D8 BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 THERMDA D21 A24 THERMDC A25 PROCHOT* THERMTRIP* BCLK0 BCLK1 C7 A22 A21 XDP_BPM_L<0> 87C6 11B3 XDP_BPM_L<1> 87C6 11B3 XDP_BPM_L<2> 87C6 11B3 XDP_BPM_L<3> 87C6 11B3 XDP_BPM_L<4> 87C6 11B3 XDP_BPM_L<5> 11B3 7A8 XDP_TCK 11B3 7B8 XDP_TDI 11B5 XDP_TDO 11B3 7B8 XDP_TMS 11B3 XDP_TRST_L 26C6 11B4 XDP_DBRESET_L 87C6 11B3 R0703 CPU_PROCHOT_L 10B6 CPU_THERMD_P 10B6 CPU_THERMD_N IO IO IO 54.9 OMIT 1% 1/16W MF-LF 2 402 U0700 IO IO IO IN IN OUT IN IN 1 R0704 52C1 21C2 14B6 34D5 34D3 33C4 5C4 34D5 34D3 33C4 5C4 PM_THRMTRIP_L FSB_CLK_CPU_P FSB_CLK_CPU_N 5% 1/16W MF-LF 2 402 OUT OUT OUT CPU_PROCHOT_L TO SMC AND CPU VR TO INFORM CPU IS HOT AA1 RSVD1 AA4 RSVD2 AB2 RSVD3 AA3 RSVD4 M4 RSVD5 N5 RSVD6 T2 RSVD7 V3 RSVD8 B2 RSVD9 C3 RSVD10 NC_CPU_HFPLL OUT OUT PM_THRMTRIP# SHOULD CONNECT TO ICH7-M AND GMCH WITHOUT T-ING (NO STUB) IN IN 87D6 12D6 5B7 IO B25 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 NC_CPU_EXTBREF T22 NC_CPU_SPARE0 NC_CPU_SPARE1 NC_CPU_SPARE2 TP_CPU_SPARE3 NC_CPU_SPARE4 TP_CPU_SPARE5 TP_CPU_SPARE6 TP_CPU_SPARE7 D2 F6 D3 C1 AF1 D22 C23 C24 IO 87D6 12D6 5B7 IO 87D6 12D6 5B7 IO 87D6 12D6 5B7 IO 87D6 12D6 5B7 IO 87D6 12D6 5B7 IO PP1V05_S0 IO 87D6 12C6 5B7 IO 87D6 12C6 5B7 IO 87D6 12C6 5B7 IO 87D6 12B4 5B7 IO 87D6 12B4 5B7 IO IO IO IO IO 87D6 12C6 5B7 IO 87D6 12C6 5B7 IO 6C7 6C8 87D6 12C6 5B7 IO 6C7 6C8 6C7 6C8 87D6 12C6 5B7 IO 87D6 12C6 5B7 IO 87D6 12C6 5B7 IO 87D6 12C6 5B7 IO 87D6 12C6 5B7 IO 87D6 12C6 5B7 IO 87D6 12C6 5B7 IO SPARE[7-0],HFPLL: ROUTE TO TP VIA AND PLACE GND VIA W/IN 1000 MILS 6C7 6C8 87D6 12C6 5B7 87D6 12C6 5B7 1% 1/16W MF-LF 2 402 21C1 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 65A2 5B2 5D4 7B5 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 19D7 67D6 67D8 87C6 R0720 1 IO 87D6 12D6 5B7 6C7 6C8 1K B IO 87D6 12D6 5B7 87D6 12C6 5B7 R0705 1 54.9 2 2.0K 1% 1/16W MF-LF 2 402 34C6 R0721 OUT 34B6 OUT 1 34B6 54.9 2 OUT 87D6 12C6 5B7 IO IO IO 87D6 12B4 5B7 IO 87D6 12B4 5B7 IO 87D6 12B4 5B7 IO FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTBN_L<0> FSB_DSTBP_L<0> FSB_DINV_L<0> E22 D0* F24 D1* E26 D2* E25 D6* E23 D7* K24 D8* G24 D9* J24 D10* J23 D11* H26 D12* F26 D13* K22 D14* H25 D15* H23 DSTBN0* (2 OF 4) D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* N22 D16* K25 D17* P26 D18* R23 D19* L25 D20* L22 D21* L23 D22* M23 D23* P25 D24* P22 D25* P23 D26* T24 D27* R24 D28* D48* D49* D50* D51* D52* D53* L26 D29* T25 D30* N24 D31* M24 DSTBN1* N25 DSTBP1* C26 TEST1 CPU_TEST2 D25 TEST2 CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2> B22 BSEL0 B23 BSEL1 C21 BSEL2 D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* M26 DINV1* CPU_TEST1 1% 402 D32* D33* BGA G22 DSTBP0* J26 DINV0* AD26 GTLREF A2 NC LAYOUT NOTE: 0.5" MAX LENGTH YONAH CPU H22 D3* F23 D4* G25 D5* FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_DSTBN_L<1> FSB_DSTBP_L<1> FSB_DINV_L<1> CPU_GTLREF R0706 1% 402 XDP_TDI IO 87D6 12C6 5B7 1 11B3 7C6 87D6 12D6 5B7 87D6 12B4 5B7 PP1V05_S0 XDP_TMS IO 87D6 12D6 5B7 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7 12C2 12B7 12A7 11C5 11B3 9B7 8C7 7D5 7B6 5D4 5B2 19D6 19D5 19D2 19D1 19C8 17D6 17D3 16D3 16C8 13B5 67D8 67D6 65A2 55A4 11B3 7C6 IO 87D6 12D6 5B7 87D6 12D6 5B7 68 52D3 52C1 87D6 12D6 5B7 87D6 12C6 5B7 NC_CPU_A32_L 6D7 NC_CPU_A33_L 6D7 NC_CPU_A34_L 6D7 NC_CPU_A35_L 6D7 NC_CPU_A36_L 6D7 NC_CPU_A37_L 6D7 NC_CPU_A38_L 6D7 NC_CPU_A39_L 6D7 NC_CPU_APM0_L 6C7 NC_CPU_APM1_L 6C8 6C7 E1 BR0* F21 FSB_DEFER_L 5B7 FSB_DRDY_L 5B7 FSB_DBSY_L 1 A6 A20M* A5 FERR* C4 IGNNE* 6D8 6D7 6D8 DBSY* HITM* Y2 A17* U5 A18* R3 A19* CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L IN 87D6 12B4 L5 REQ4* CPU_A20M_L CPU_FERR_L CPU_IGNNE_L IN H5 RS1* RS2* K3 REQ0* H2 REQ1* K2 REQ2* J3 REQ3* FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_ADSTB_L<1> IO DEFER* DRDY* 1 IO DATA GRP2 IO 87D6 12D4 5B7 IO 87D6 19D7 21C1 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 65A2 67D6 67D8 DATA GRP3 87D6 12D4 5B7 J1 A9* N3 A10* P5 A11* IO 87D6 12C4 5B7 DATA GRP0 IO PP1V05_S0 87D6 12C4 5B7 DATA GRP1 IO 87D6 12D4 5B7 CONTROL IO 87D6 12D4 5B7 FSB_ADS_L FSB_BNR_L 12C4 FSB_BPRI_L H1 E2 G5 ADS* BNR* BPRI* BGA XDP/ITP SIGNALS 87D6 12D4 5B7 (1 OF 4) THERM D IO K5 A6* M1 A7* N2 A8* HCLK IO YONAH CPU ADDR GROUP0 IO 87D6 12D4 5B7 J4 A3* L4 A4* M3 A5* ADDR GROUP1 IO 87D6 12D4 5B7 87D6 12D4 5B7 FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_ADSTB_L<0> IO 87D6 12D4 5B7 RESERVED 87D6 12D4 5B7 MISC 1 R0722 11B3 7C6 XDP_TCK 1 0 54.9 2 402 1 R0712 1% 402 51 5% 1/16W MF-LF 2 402 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 SLP* PSI* 87D6 12C6 87D6 12C6 87D6 12C6 87D6 12C6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B4 V23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 U26 U1 PWRGOOD 87D6 12C6 5B7 87D6 12B4 AC22 AC23 V1 E5 B5 D24 D6 D7 AE6 FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> 5B7 FSB_D_L<35> 5B7 FSB_D_L<36> 5B7 FSB_D_L<37> 5B7 FSB_D_L<38> 5B7 FSB_D_L<39> 5B7 FSB_D_L<40> 5B7 FSB_D_L<41> 5B7 FSB_D_L<42> 5B7 FSB_D_L<43> 5B7 FSB_D_L<44> 5B7 FSB_D_L<45> 5B7 FSB_D_L<46> 5B7 FSB_D_L<47> 5B7 FSB_DSTBN_L<2> 5B7 FSB_DSTBP_L<2> 5B7 FSB_DINV_L<2> 87D6 12C6 5B7 87D6 12B4 COMP1 DPSLP* DPWR* 87D6 12C6 5B7 Y25 R26 DPRSTP* R0730 AB24 V24 COMP0 COMP2 COMP3 NOSTUFF AA23 87D6 12B6 5B7 FSB_D_L<48> FSB_D_L<49> 5B7 FSB_D_L<50> 5B7 FSB_D_L<51> 5B7 FSB_D_L<52> 5B7 FSB_D_L<53> 5B7 FSB_D_L<54> 5B7 FSB_D_L<55> 5B7 FSB_D_L<56> 5B7 FSB_D_L<57> 5B7 FSB_D_L<58> 5B7 FSB_D_L<59> 5B7 FSB_D_L<60> 5B7 FSB_D_L<61> 5B7 FSB_D_L<62> 5B7 FSB_D_L<63> 5B7 FSB_DSTBN_L<3> 5B7 FSB_DSTBP_L<3> 5B7 FSB_DINV_L<3> 87D6 12B6 5B7 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B6 87D6 12B4 87D6 12B4 87D6 12B4 IO IO IO IO IO IO IO IO IO IO IO C IO IO IO IO IO IO IO IO IO IO IO IO IO IO LAYOUT NOTE: COMP0,2 CONNECT WITH TRACE LENGTH SHORTER COMP1,3 CONNECT WITH TRACE LENGTH SHORTER IO IO IO IO IO IO R0716 IO 1 IO IO IO 1 IO 402 54.9 2 1% IO 402 B R0718 IO CPU_COMP<0> 87C6 CPU_COMP<1> 87C6 CPU_COMP<2> 87C6 CPU_COMP<3> CPU_DPRSTP_L 87C6 21C4 5B4 CPU_DPSLP_L 87D6 12B4 5A4 FSB_DPWR_L 87C6 21C4 5B4 CPU_PWRGD 12A4 5A4 FSB_SLPCPU_L 61C7 CPU_PSI_L 27.4 2 R0717 1 87C6 61C7 21C4 5C4 ZO=27.4OHM, MAKE THAN 0.5". ZO=55OHM, MAKE THAN 0.5". 27.4 2 R0719 1 54.9 2 1% 402 IN IN IN IN IN IN 2 NOSTUFF 1 R0707 1K 5% 1/16W MF-LF 2 402 CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9 CPU 1 OF 2-FSB WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50 SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE) A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 7 1 87 A 8 6 7 5 3 4 2 1 OMIT A4 VSS_1 A8 VSS_2 A11 VSS_3 PPVCORE_S0_CPU OMIT A7 VCC_1 A9 VCC_2 A10 VCC_3 D A12 VCC_4 A13 VCC_5 A15 VCC_6 BGA (3 OF 4) VCC_71 AC9 VCC_72 AC12 VCC_73 AC13 VCC_74 AC15 VCC_75 AC17 VCC_76 AC18 B7 VCC_10 B9 VCC_11 B10 VCC_12 VCC_77 AD7 VCC_78 AD9 VCC_79 AD10 B12 VCC_13 B14 VCC_14 B15 VCC_15 VCC_80 AD12 VCC_81 AD14 C9 VCC_19 C10 VCC_20 C12 VCC_21 C13 VCC_22 C15 VCC_23 C17 VCC_24 C18 VCC_25 D9 VCC_26 D10 VCC_27 D12 VCC_28 D14 VCC_29 VCC_82 AD15 VCC_83 AD17 VCC_84 AD18 VCC_85 AE9 VCC_86 AE10 VCC_87 AE12 VCC_88 AE13 VCC_89 AE15 VCC_90 AE17 VCC_91 AE18 VCC_92 AE20 VCC_93 AF9 VCC_94 AF10 VCC_95 AF12 VCC_96 AF14 VCC_97 AF15 VCC_98 AF17 D15 VCC_30 D17 VCC_31 D18 VCC_32 E7 VCC_33 VCC_99 AF18 VCC_100 AF20 E9 VCC_34 E10 VCC_35 E12 VCC_36 VCCP_1 V6 VCCP_2 G21 E13 VCC_37 E15 VCC_38 E17 VCC_39 VCCP_3 J6 VCCP_4 K6 VCCP_5 M6 E18 VCC_40 E20 VCC_41 F7 VCC_42 VCCP_6 J21 VCCP_7 K21 VCCP_8 M21 F9 VCC_43 F10 VCC_44 F12 VCC_45 VCCP_9 N21 VCCP_10 N6 VCCP_11 R21 F14 VCC_46 F15 VCC_47 F17 VCC_48 VCCP_12 R6 VCCP_13 T21 F18 VCC_49 F20 VCC_50 AA7 VCC_51 AA9 VCC_52 AA10 VCC_53 AA12 VCC_54 AA13 VCC_55 B YONAH CPU VCC_68 AB20 VCC_69 AB7 VCC_70 AC7 A17 VCC_7 A18 VCC_8 A20 VCC_9 B17 VCC_16 B18 VCC_17 B20 VCC_18 C U0700 AA15 VCC_56 AA17 VCC_57 AA18 VCC_58 AA20 VCC_59 AB9 VCC_60 AC10 VCC_61 A14 VSS_4 A16 VSS_5 A19 VSS_6 A23 VSS_7 A26 VSS_8 5B2 8B5 9D7 55A6 55D7 61D1 67D1 67D3 (CPU CORE POWER) PP1V05_S0 21C1 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 65A2 5B2 5D4 7B5 7B6 7D5 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 19D7 67D6 67D8 (CPU IO POWER 1.05V) VCCP_14 T6 VCCP_15 V21 VCCP_16 W21 VCCA=1.5 ONLY VCCA B26 67C6 67C8 62A8 62C1 66C5 25C8 25D6 48B6 5D1 5D4 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 PP1V5_S0 (CPU INTERNAL PLL POWER 1.5V) VID0 AD6 VID1 AF5 VID2 AE5 VID3 AF4 VID4 AE3 VID5 AF2 VID6 AE2 CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6> OUT 9C2 87B6 OUT 9C2 87B6 OUT 9C2 87B6 OUT 9C2 87B6 OUT 9C2 87B6 OUT 9C2 87B6 OUT 9C2 87B6 VID FOR CPU POWER SUPPLY IF NO USE, NEED PULL-UP OR PULL-DOWN 5B2 8D7 9D7 55A6 55D7 61D1 67D1 67D3 1 R0802 100 1% 1/16W MF-LF AB10 VCC_62 AB12 VCC_63 AB14 VCC_64 AB15 VCC_65 AB17 VCC_66 AB18 VCC_67 PPVCORE_S0_CPU 2 402 VCCSENSE AF7 CPU_VCCSENSE_P OUT 61B1 87B6 VSSSENSE AE7 CPU_VCCSENSE_N OUT 61A1 87B6 1 R0803 LAYOUT NOTE: CONNECT R0803 TO TP_VSSSENSE WITH NO STUB. 100 1% 1/16W MF-LF 2 402 LAYOUT NOTE: CPU_VCCSENSE_P/CPU_VCCSENSE_N USE ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING. LAYOUT NOTE: PROVIDE A TEST POINT (WITH NO STUB) TO CONNECT A DIFFERENCTIAL PROBE BETWEEN VCCSENSE AND VSSSENSE AT THE LOCATION WHERE THE TWO 54.9 OHM RESISTORS TERMINATE THE 55 OHM TRANSMISSION LINE LAYOUT NOTE: VCCSENSE AND VSSSENSE LINES SHOULD BE OF EQUAL LENGTH U0700 VSS_82 VSS_83 YONAH CPU BGA (4 OF 4) P6 P21 VSS_84 P24 VSS_85 R2 VSS_86 R5 VSS_87 R22 VSS_88 R25 VSS_89 T1 B6 VSS_9 B8 VSS_10 B11 VSS_11 VSS_90 T4 VSS_91 T23 VSS_92 T26 B13 VSS_12 B16 VSS_13 B19 VSS_14 VSS_93 U3 VSS_94 U6 VSS_95 U21 B21 VSS_15 B24 VSS_16 C5 VSS_17 C8 VSS_18 C11 VSS_19 VSS_96 U24 VSS_97 V2 VSS_98 V5 VSS_99 V22 VSS_100 V25 C14 VSS_20 C16 VSS_21 C19 VSS_22 VSS_101 W1 VSS_102 W4 VSS_103 W23 C2 VSS_23 C22 VSS_24 C25 VSS_25 D1 VSS_26 D4 VSS_27 VSS_104 W26 VSS_105 Y3 VSS_106 Y6 D8 VSS_28 D11 VSS_29 D13 VSS_30 VSS_109 AA2 VSS_110 AA5 VSS_111 AA8 D16 VSS_31 D19 VSS_32 D23 VSS_33 VSS_112 AA11 VSS_113 AA14 VSS_114 AA16 D26 VSS_34 E3 VSS_35 E6 VSS_36 VSS_115 AA19 VSS_116 AA22 VSS_117 AA25 E8 VSS_37 E11 VSS_38 E14 VSS_39 E16 VSS_40 E19 VSS_41 VSS_118 AB1 VSS_119 AB4 E21 VSS_42 E24 VSS_43 F5 VSS_44 VSS_123 AB16 VSS_124 AB19 VSS_125 AB23 F8 VSS_45 F11 VSS_46 F13 VSS_47 F16 VSS_48 F19 VSS_49 VSS_126 AB26 VSS_127 AC3 VSS_128 AC6 F2 VSS_50 F22 VSS_51 F25 VSS_52 VSS_131 AC14 VSS_132 AC16 VSS_133 AC19 G4 VSS_53 G1 VSS_54 G23 VSS_55 VSS_134 AC21 VSS_135 AC24 VSS_136 AD2 G26 VSS_56 H3 VSS_57 H6 VSS_58 VSS_137 AD5 VSS_138 AD8 VSS_139 AD11 H21 VSS_59 H24 VSS_60 J2 VSS_61 J5 VSS_62 J22 VSS_63 VSS_140 AD13 VSS_141 AD16 J25 VSS_64 K1 VSS_65 K4 VSS_66 VSS_145 AE1 VSS_146 AE4 VSS_147 AE8 K23 VSS_67 K26 VSS_68 L3 VSS_69 VSS_148 AE11 VSS_149 AE14 VSS_150 AE16 L6 VSS_70 L21 VSS_71 L24 VSS_72 M2 VSS_73 M5 VSS_74 VSS_151 AE19 VSS_152 AE23 M22 VSS_75 M25 VSS_76 N1 VSS_77 VSS_156 AF8 VSS_157 AF11 VSS_158 AF13 N4 VSS_78 N23 VSS_79 N26 VSS_80 P3 VSS_81 VSS_159 AF16 VSS_160 AF19 VSS_161 AF21 D VSS_107 Y21 VSS_108 Y24 C VSS_120 AB8 VSS_121 AB11 VSS_122 AB13 VSS_129 AC8 VSS_130 AC11 VSS_142 AD19 VSS_143 AD22 VSS_144 AD25 B VSS_153 AE26 VSS_154 AF3 VSS_155 AF6 VSS_162 AF24 CPU 2 OF 2-PWR/GND A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 8 1 87 A 8 6 7 4 5 2 3 1 D D CPU VCORE HF AND BULK DECOUPLING 67D3 67D1 61D1 55D7 55A6 8D7 8B5 5B2 PPVCORE_S0_CPU 4x 330uF. 20x 22uF 0805 1 2 C0900 1 C0901 1 C0902 C0903 1 1 C0904 1 C0905 1 C0906 1 C0907 1 C0908 1 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 2 2 2 2 2 2 2 2 2 CPU VCORE VID Connections C0909 22UF Resistors to allow for override of CPU VID Will probably be removed before production RP0990 0 5% 1 2 C0919 87B6 8B7 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 87B6 8B7 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 20% 6.3V CERM 805 C0910 1 2 C0911 1 2 C0912 C0913 1 2 1 2 C0914 1 C0915 2 1 2 C0916 1 2 C0917 1 2 C0918 1 2 87B6 8B7 87B6 8B7 CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> 1 8 2 7 3 6 4 5 IMVP6_VID<0> IMVP6_VID<1> IMVP6_VID<2> IMVP6_VID<3> 5C4 61C7 5C4 61C7 5C4 61C7 5C4 61C7 1/16W SM-LF CRITICAL 1 CRITICAL 1 C0950 330UF C 330UF 3 POLY D2T POLY D2T RP0991 0 20% 3 2 2.5V 3 2 2.5V POLY D2T C0954 330UF 20% 20% 2 2.5V CRITICAL 1 C0953 330UF 20% 3 CRITICAL 1 C0952 2 2.5V C 5% POLY D2T 87B6 8B7 87B6 8B7 87B6 8B7 CPU_VID<4> CPU_VID<5> CPU_VID<6> NC 1 8 2 7 3 6 5 4 IMVP6_VID<4> IMVP6_VID<5> IMVP6_VID<6> 5C4 61C7 5C4 61C7 5C4 61C7 NC 1/16W SM-LF VCCA (CPU AVdd) Decoupling PP1V5_S0 25C2 25B6 25B2 25A8 24B5 24A5 24A3 8B7 5D4 5D1 67C8 67C6 66C5 62C1 62A8 48B6 25D6 25C8 25C6 1x 10uF, 1x 0.01uF C0980 1 1 2 2 10uF C0981 0.01UF 20% 6.3V X5R 603 20% 16V CERM 402 B B VCCP (CPU I/O) Decoupling 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7 12C2 12B7 12A7 11C5 11B3 8C7 7D5 7B6 7B5 5D4 5B2 19D6 19D5 19D2 19D1 19C8 17D6 17D3 16D3 16C8 13B5 67D8 67D6 65A2 55A4 PP1V05_S0 1x 470uF, 6x 0.1uF 0402 C0935 1 1 470uF 20% 2.5V TANT D2T 2 3 2 C0936 1 C0937 1 C0938 1 C0939 1 C0940 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 20% 10V CERM 402 20% 10V CERM 402 20% 10V CERM 402 20% 10V CERM 402 20% 10V CERM 402 2 2 2 2 1 C0941 0.1UF 2 20% 10V CERM 402 CRITICAL NOTE: This cap is shared between CPU and NB CPU Decoupling & VID A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 9 1 87 A 8 6 7 2 3 4 5 1 D D CPU ZONE THERMAL SENSOR 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 21C3 20B4 20A4 19C7 19C6 17C6 14D6 14C7 5D4 5A4 PP3V3_S0 25B4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 C1002 C LAYOUT NOTE: LAYOUT NOTE: ADD GND GUARD TRACE ROUTE CPU_THERMD_P AND FOR CPU_THERMD_P AND CPU_THERMD_N ON SAME CPU_THERMD_N LAYER. 1 C 0.1UF 10% 16V X5R 402 2 R10061 10K 5% 1/16W MF-LF 402 2 10 MIL TRACE 10 MIL SPACING 1 R1005 10K 5% 1/16W MF-LF 2 402 1 VDD ALERT*/ 6 THRM_ALERT_L THM2* R1001 OUT 7C6 CPU_THERMD_P 1 499 1% 1/16W MF-LF 402 (TO CPU INTERNAL THERMAL DIODE) (TC0D) THRM_CPU_DX_P THRM_CPU_DX_N 2 1 C1001 2 D+ 3 D- U1001 TMP401 MSOP CRITICAL THM* 4 THRM_ALERT SCLK 8 SDATA 7 51B5 49B5 27D3 27D2 27D1 SMBUS_SMC_B_S0_SCL IO 51B5 49B5 27D3 27D2 27D1 SMBUS_SMC_B_S0_SDA IO 0.001UF R1002 IN 7C6 1 CPU_THERMD_N 499 2 2 10% 50V CERM 402 GND 5 1% 1/16W MF-LF 402 PLACE U1001 NEAR THE U1200 B B CPU MISC1-TEMP SENSOR A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 10 1 87 A 8 7 6 2 3 4 5 1 D D CPU ITP700FLEX DEBUG SUPPORT C C ITPCONN 55A4 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7 12C2 12B7 12A7 11B3 9B7 8C7 7D5 7B6 7B5 5D4 5B2 19D6 19D5 19D2 19D1 19C8 17D6 17D3 16D3 16C8 13B5 67D8 67D6 65A2 CRITICAL PP1V05_S0 J1101 ITP 52435-2872 1 R1101 1R1103 54.9 1% 1/16W MF-LF 2 402 F-RT-SM 29 54.9 1% 1/16W MF-LF 2 402 7C6 7B8 7C6 7B8 7C6 OUT OUT R1102 7C6 IN 1% 1/16W MF-LF 402 ITP OUT XDP_TCK IN FSB_CPURST_L 1 87C6 34D5 34D3 33C4 (FROM CK410M HOST 133/167MHZ) 87C6 34D5 34D3 33C4 IN IN 4 5 6 ITP_TDO 7 CPU_XDP_CLK_N CPU_XDP_CLK_P 8 9 10 11B3 7C6 7A8 22.6 2 OUT (FBO) XDP_TCK 11 ITPRESET_L 12 IO XDP_BPM_L<5> 13 87C6 7C6 IO XDP_BPM_L<4> 87C6 7C6 IO XDP_BPM_L<3> 87C6 7C6 IO XDP_BPM_L<2> 87C6 7C6 IO XDP_BPM_L<1> IO XDP_BPM_L<0> 87C6 1% 1/16W MF-LF 402 B 3 NC (TCK) NC R1100 87D6 12C4 7D6 5A4 2 XDP_TRST_L 22.6 2 1 XDP_TDO 1 OUT ITP 11B3 7C6 7A8 XDP_TDI XDP_TMS 87C6 7C6 14 15 16 PP3V3_S5 79D5 67D5 67D3 67C3 66C5 65D8 24B3 24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 5D4 65D2 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 B 17 18 1 R1104 240 19 20 5% 1/16W MF-LF 2 402 21 22 87C6 7C6 23 NC (AND WITH RESET BUTTON) OUT 26C6 7C6 XDP_DBRESET_L 55A4 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7 12C2 12B7 12A7 11C5 9B7 8C7 7D5 7B6 7B5 5D4 5B2 19D6 19D5 19D2 19D1 19C8 17D6 17D3 16D3 16C8 13B5 67D8 67D6 65A2 24 25 PP1V05_S0 26 (DBA#) INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM. (DEBUG PORT ACTIVE) (DBR#) TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC (DEBUG PORT RESET) 27 1 C1100 28 0.1UF 10% 2 16V X5R 402 30 518S0320 1 R1106 ITP TCK SIGNAL LAYOUT NOTE: ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX CONNECTOR’S FBO PIN. 680 5% 1/16W MF-LF 2 402 CPU ITP700FLEX DEBUG SYNC_MASTER=(MASTER) A SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 11 1 87 A 6 7 D 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO 87D6 7C4 5B7 IO IO 87D6 7B4 5B7 IO 87D6 7B4 5B7 IO IO 87D6 7B4 5B7 IO 87D6 7B4 5B7 IO 87D6 7B4 5B7 IO 87D6 7B4 5B7 IO 87D6 7B4 5B7 IO 87D6 7B4 5B7 IO 87D6 7B4 5B7 IO 87D6 7B4 5B7 IO 87D6 7B4 5B7 IO 87D6 7C3 5B7 IO 87D6 7C3 5B7 IO 87D6 7C3 5B7 IO 87D6 7C3 5B7 IO 87D6 7C3 5B7 IO 87D6 7C3 5B7 IO IO 87D6 7C3 5B7 IO IO 87D6 7C3 5B7 IO 87D6 7C3 5B7 IO 87D6 7C3 5B7 1% 1/16W MF-LF 402 B 2 2 R1221 1 24.9 1% 1/16W MF-LF 402 2 IO IO IO 87D6 7B3 5B7 IO 87D6 7B3 5B7 IO R1225 87D6 7B3 5B7 IO 221 87D6 7B3 5B7 IO 87D6 7B3 5B7 IO 87D6 7B3 5B7 IO 1% 1/16W MF-LF 402 R1226 1 100 2 IO 87D6 7C3 5B7 87D6 7B3 5B7 1 IO 87D6 7C3 5B7 87D6 7C3 5B7 54.9 IO 87D6 7C3 5B7 87D6 7C3 5B7 1 IO 87D6 7C3 5B7 87D6 7C3 5B7 R1220 1 IO 87D6 7B4 5B7 87D6 7C3 5B7 PP1V05_S0 IO 87D6 7B4 5B7 87D6 7B4 5B7 55A4 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7 12C2 12A7 11C5 11B3 9B7 8C7 7D5 7B6 7B5 5D4 5B2 19D6 19D5 19D2 19D1 19C8 17D6 17D3 16D3 16C8 13B5 67D8 67D6 65A2 IO 87D6 7C4 5B7 87D6 7C4 5B7 C IO 1% 1/16W MF-LF 402 2 IO 87D6 7B3 5B7 IO 87D6 7B3 5B7 IO 87D6 7B3 5B7 IO 87D6 7B3 5B7 IO C1226 87D6 7B3 5B7 IO 0.1uF 87D6 7B3 5B7 IO 10% 16V X5R 402 87D6 7B3 5B7 IO FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8 NB_FSB_XRCOMP NB_FSB_XSCOMP NB_FSB_XSWING 55A4 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7 12C2 12B7 11C5 11B3 9B7 8C7 7D5 7B6 7B5 5D4 5B2 19D6 19D5 19D2 19D1 19C8 17D6 17D3 16D3 16C8 13B5 67D8 67D6 65A2 E1 E2 E4 NB_FSB_YRCOMP NB_FSB_YSCOMP NB_FSB_YSWING PP1V05_S0 R1230 1 1 54.9 1% 1/16W MF-LF 402 R1235 221 2 2 34D3 33C4 5C4 34D5 IN 34D3 33C4 5B4 34D5 IN Y1 U1 W1 FSB_CLK_NB_P FSB_CLK_NB_N AG2 AG1 HD0* HD1* HD2* HD3* HD4* HD5* HD6* HD7* HD8* HD9* HD10* HD11* HD12* HD13* HD14* HD15* HD16* HD17* HD18* HD19* HD20* HD21* HD22* HD23* HD24* HD25* HD26* HD27* HD28* HD29* HD30* HD31* HD32* HD33* HD34* HD35* HD36* HD37* HD38* HD39* HD40* HD41* HD42* HD43* HD44* HD45* HD46* HD47* HD48* HD49* HD50* HD51* HD52* HD53* HD54* HD55* HD56* HD57* HD58* HD59* HD60* HD61* HD62* HD63* HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING HCLKIN HCLKIN* OMIT U1200 945GM NB BGA (1 OF 10) HA3* HA4* HA5* HA6* HA7* HA8* HA9* HA10* HA11* HA12* HA13* HA14* HA15* HA16* HA17* HA18* HA19* HA20* HA21* HA22* HA23* HA24* HA25* HA26* HA27* HA28* HA29* HA30* HA31* H9 87D6 7D8 5B7 C9 87D6 7D8 5B7 E11 87D6 7D8 5B7 87D6 G11 87D6 F11 87D6 G12 87D6 F9 87D6 H11 87D6 J12 87D6 G14 87D6 D9 87D6 J14 87D6 H13 87D6 J15 87D6 F14 87D6 D12 87D6 A11 87D6 C11 87D6 A12 87D6 A13 87D6 E13 87D6 G13 87D6 F12 87D6 B12 87D6 B14 87D6 C12 87D6 A14 87D6 C14 87D6 D14 FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> 7D8 5B7 FSB_A_L<6> 7D8 5B7 FSB_A_L<7> 7D8 5B7 FSB_A_L<8> 7D8 5B7 FSB_A_L<9> 7D8 5B7 FSB_A_L<10> 7D8 5B7 FSB_A_L<11> 7D8 5B7 FSB_A_L<12> 7D8 5B7 FSB_A_L<13> 7D8 5B7 FSB_A_L<14> 7D8 5B7 FSB_A_L<15> 7D8 5B7 FSB_A_L<16> 7C8 5B7 FSB_A_L<17> 7C8 5B7 FSB_A_L<18> 7C8 5B7 FSB_A_L<19> 7C8 5B7 FSB_A_L<20> 7C8 5B7 FSB_A_L<21> 7C8 5B7 FSB_A_L<22> 7C8 5B7 FSB_A_L<23> 7C8 5B7 FSB_A_L<24> 7C8 5B7 FSB_A_L<25> 7C8 5B7 FSB_A_L<26> 7C8 5B7 FSB_A_L<27> 7C8 5B7 FSB_A_L<28> 7C8 5B7 FSB_A_L<29> 7C8 5B7 FSB_A_L<30> 7C8 5B7 FSB_A_L<31> 2 3 4 5 HADS* HADSTB0* HADSTB1* HAVREF HBNR* HBPRI* HBREQ0* HCPURST* HDBSY* HDEFER* HDPWR* HDRDY* HDVREF E8 87D6 7D6 5B7 B9 87C6 7D8 5B7 C13 87C6 7C8 5B7 HDINV0* HDINV1* HDINV2* HDINV3* J7 87D6 7C4 5B7 W8 87D6 7B4 5B7 U3 87D6 7C3 5B7 J13 C6 F6 C7 B7 A7 C3 J9 H8 FSB_ADS_L FSB_ADSTB_L<0> FSB_ADSTB_L<1> NB_FSB_VREF FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_CPURST_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L 1 IO D IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PP1V05_S0 IO 21C1 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 65A2 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 19D7 67D6 67D8 C IO 1 HOST 8 R1210 100 IO IO 2 1% 1/16W MF-LF 402 IO IO 1 OUT IO OUT IO C1211 1 10% 16V X5R 402 R1211 200 0.1uF 2 2 1% 1/16W MF-LF 402 OUT IO IO K13 87D6 AB10 FSB_DINV_L<0> FSB_DINV_L<1> FSB_DINV_L<2> 7B3 5B7 FSB_DINV_L<3> 87D6 7C4 5B7 FSB_DSTBN_L<0> 7B4 5B7 FSB_DSTBN_L<1> 7C3 5B7 FSB_DSTBN_L<2> 7B3 5B7 FSB_DSTBN_L<3> HDSTBN0* HDSTBN1* HDSTBN2* HDSTBN3* K4 HDSTBP0* HDSTBP1* HDSTBP2* HDTSBP3* K3 87D6 7C4 5B7 T6 87D6 7B4 5B7 HHIT* HHITM* HLOCK* D3 HREQ0* HREQ1* HREQ2* HREQ3* HREQ4* D8 HRS0* HRS1* HRS2* B4 HSLPCPU* HTRDY* E3 87D6 T7 87D6 Y5 87D6 AC4 87D6 AA5 87D6 AC5 87D6 7D6 5B7 87D6 D4 87D6 B3 FSB_HIT_L 7D6 5B7 FSB_HITM_L 7D6 5A7 FSB_LOCK_L 87D6 7D8 5A7 87D6 G8 87D6 B8 87D6 F8 87D6 A8 FSB_DSTBP_L<0> FSB_DSTBP_L<1> 7C3 5B7 FSB_DSTBP_L<2> 7B3 5B7 FSB_DSTBP_L<3> FSB_REQ_L<0> 7D8 5A7 FSB_REQ_L<1> 7D8 5A7 FSB_REQ_L<2> 7D8 5A7 FSB_REQ_L<3> 7D8 5A7 FSB_REQ_L<4> FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> E6 D6 E7 7A3 5A4 FSB_SLPCPU_L FSB_TRDY_L IO IO IO IO IO IO IO IO B IO IO IO IO IO IO IO IO IO IO IO IO OUT OUT OUT OUT OUT 1% 1/16W MF-LF 402 NB CPU Interface A SYNC_MASTER=M59_MLB R1231 1 1 24.9 1% 1/16W MF-LF 402 R1236 1 100 2 2 1% 1/16W MF-LF 402 SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY C1236 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING 0.1uF 2 10% 16V X5R 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 12 1 87 A 8 7 6 2 3 4 5 PP1V5_S0_NB 1 U1200 OUT OUT 82A7 82A5 79C3 IO 82A7 82A5 79C3 IO 19D3 82A4 IO OUT IN IN 82D3 82D3 82C3 82C3 82D3 82D3 19C5 16D1 67C8 19D1 13D2 62A7 13D2 19C4 19C4 13D2 67C6 19C5 13C5 19D7 13C5 19C1 OUT OUT 82D3 OUT 82C3 19D1 17B6 62A7 19D2 16D1 67B6 16D1 19C5 OUT 82D3 82C3 19D2 17C6 67B6 19D5 17B6 67C6 17B6 19D1 OUT OUT 82D3 19D7 19D6 19D5 19B8 19B5 19A5 67C8 67C6 62A7 19D7 19D6 19B8 19B5 19A5 17C6 67B6 19C4 19C1 67C8 19B8 19B5 19A5 17C6 19D6 19D5 19D2 OUT 82D3 82D3 Composite: DACA only S-Video: DACB & DACC only Component: DACA, DACB & DACC OUT OUT 82C3 TV-Out Signal Usage: OUT 82D3 82D3 C OUT OUT OUT OUT OUT OUT 19C1 13C5 5D4 OUT 5D4 5D4 OUT OUT 67C8 67C6 67B6 62A7 19D7 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 OUT 19D6 19D5 19D2 19D1 19C5 19C4 19C1 Unused DAC outputs must remain powered, but can omit filtering components. Unused DAC outputs should connect to GND through 75-ohm resistors. 62A7 19D7 19D6 19D5 19D2 19B8 19B5 19A5 17C6 17B6 16D1 67B6 19C4 19C1 67C8 67C6 67B6 19B8 19B5 19A5 17C6 17B6 16D1 19D6 19D5 19D2 19D1 19C5 TV-Out Disable OUT 67C8 67C6 19D1 19C5 13D2 13C5 5D4 OUT 62A7 19D7 13D2 13C5 5D4 OUT 19C4 19C1 67D8 67D6 65A2 55A4 34C8 34C6 34B8 24D3 24C3 21C1 19D7 19D6 19D5 19D2 19D1 12A7 11C5 11B3 9B7 8C7 7D5 7B6 7B5 5D4 5B2 OUT 19C8 17D6 17D3 16D3 16C8 13B5 12C2 12B7 25D3 25C4 67D8 67D6 65A2 55A4 34C8 34B8 25D3 25C4 24D3 24C3 21C1 19D7 OUT 19D5 19D2 19D1 19C8 17D6 17D3 16D3 16C8 12A7 11C5 11B3 9B7 8C7 7D5 7B6 7B5 5D4 5B2 OUT 13B5 12C2 12B7 67D8 67D6 65A2 55A4 34C8 19D6 34B8 25D3 25C4 24D3 24C3 21C1 34C6 34C6 19D6 OUT 19D5 19D2 19D1 19C8 17D6 19D7 12B7 12A7 11C5 11B3 9B7 8C7 7D5 7B6 7B5 17D3 16D3 16C8 13B5 12C2 5B2 67D8 67D6 5D4 OUT 24D3 24C3 21C1 19D7 19D6 19D5 19D2 19D1 12A7 11C5 11B3 9B7 8C7 7D5 7B6 7B5 5D4 5B2 OUT 19C8 17D6 17D3 16D3 16C8 13B5 12C2 12B7 65A2 55A4 34C8 34C6 34B8 25D3 25C4 Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail. Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND. CRT Disable Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core rail, and tie VSSA_CRTDAC and VCC_SYNC to GND. 19D6 19D5 IO 19D6 19D5 IO OUT 67D8 67D6 24D3 24C3 21C1 19D7 19D6 19D5 19D2 19D1 12A7 11C5 11B3 9B7 8C7 7D5 7B6 7B5 5D4 5B2 OUT 19C8 17D6 17D3 16D3 16C8 13B5 12C2 12B7 65A2 55A4 34C8 34C6 34B8 25D3 25C4 OUT LVDS_BKLTCTL LVDS_BKLTEN TP_LVDS_CLKCTLA TP_LVDS_CLKCTLB LVDS_CONN_DDC_CLK LVDS_CONN_DDC_DATA LVDS_IBG TP_LVDS_VBG LVDS_VDDEN GND GND LVDS_A_CLK_N LVDS_A_CLK_P LVDS_B_CLK_N LVDS_B_CLK_P EXP_A_COMPI D40 BGA EXP_A_COMPO D38 EXP_A_RXN0 EXP_A_RXN1 F34 L_CLKCTLB L_DDC_CLK L_DDC_DATA EXP_A_RXN2 H34 EXP_A_RXN3 EXP_A_RXN4 J38 EXP_A_RXN5 EXP_A_RXN6 M38 EXP_A_RXN7 P38 EXP_A_RXN8 EXP_A_RXN9 R34 L_BKLTCTL J30 H30 L_BKLTEN L_CLKCTLA H29 G26 EXP_A_RXP0 D34 70D1 EXP_A_RXP1 EXP_A_RXP2 F38 EXP_A_RXP3 H38 EXP_A_RXP4 EXP_A_RXP5 J34 EXP_A_RXP6 M34 EXP_A_RXP7 EXP_A_RXP8 N38 EXP_A_RXP9 EXP_A_RXP10 R38 EXP_A_RXP11 V38 EXP_A_RXP12 EXP_A_RXP13 W34 EXP_A_RXP14 AA34 EXP_A_RXP15 AB38 PEG_D2R_P<0> 70D1 PEG_D2R_P<1> 70D1 PEG_D2R_P<2> 70D1 PEG_D2R_P<3> 70D1 PEG_D2R_P<4> 70C1 PEG_D2R_P<5> 70C1 PEG_D2R_P<6> 70C1 PEG_D2R_P<7> 70C1 PEG_D2R_P<8> 70C1 PEG_D2R_P<9> 70C1 PEG_D2R_P<10> 70B1 PEG_D2R_P<11> 70B1 PEG_D2R_P<12> 70B1 PEG_D2R_P<13> 70B1 PEG_D2R_P<14> 70B1 PEG_D2R_P<15> EXP_A_TXN0 EXP_A_TXN1 F36 70D5 EXP_A_TXN2 H36 EXP_A_TXN3 EXP_A_TXN4 J40 EXP_A_TXN5 EXP_A_TXN6 M40 EXP_A_TXN7 P40 EXP_A_TXN8 EXP_A_TXN9 R36 EXP_A_TXN10 V36 EXP_A_TXN11 EXP_A_TXN12 W40 C25 CRT_DDC_CLK CRT_DDC_DATA G23 HSYNC EXP_A_TXN13 AA40 J22 CRT_IREF CRT_VSYNC EXP_A_TXN14 EXP_A_TXN15 AB36 B38 C35 F32 C33 C32 L_IBG L_VBG L_VDDEN L_VREFH L_VREFL A32 LA_CLK EXP_A_RXN10 V34 E27 LB_CLK* LB_CLK EXP_A_RXN11 EXP_A_RXN12 W38 EXP_A_RXN13 AA38 EXP_A_RXN14 EXP_A_RXN15 AB34 E26 A37 LA_DATA1* LA_DATA2* LVDS_A_DATA_P<0> LVDS_A_DATA_P<1> LVDS_A_DATA_P<2> B37 LA_DATA0 B34 LA_DATA1 A36 LA_DATA2 LVDS_B_DATA_N<0> LVDS_B_DATA_N<1> LVDS_B_DATA_N<2> G30 D30 LB_DATA0* LB_DATA1* F29 LB_DATA2* TP_CRT_DDC_CLK TP_CRT_DDC_DATA GND PP1V05_S0 GND N34 LA_CLK* B35 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 L34 A33 LA_DATA0* PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB G38 F30 D29 F28 LB_DATA0 LB_DATA1 LB_DATA2 C18 TV_DACA_OUT TV_DACB_OUT A19 TV_DACC_OUT A16 J20 TV_IREF B16 B18 TV_IRTNA TV_IRTNB B19 TV_IRTNC E23 CRT_BLUE D23 CRT_BLUE* C22 CRT_GREEN CRT_GREEN* B22 A21 B21 C26 H23 CRT_RED CRT_RED* B T38 Y34 G34 L38 P34 T34 Y38 70D1 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN EXP_A_TXP0 D36 EXP_A_TXP1 EXP_A_TXP2 F40 EXP_A_TXP3 H40 EXP_A_TXP4 EXP_A_TXP5 J36 EXP_A_TXP6 M36 EXP_A_TXP7 EXP_A_TXP8 N40 EXP_A_TXP9 EXP_A_TXP10 R40 EXP_A_TXP11 V40 EXP_A_TXP12 EXP_A_TXP13 W36 EXP_A_TXP14 AA36 EXP_A_TXP15 AB40 T40 Y36 G36 L40 P36 T36 Y40 C IN 70D5 N36 SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL IN AC40 L36 D SDVO_TVCLKIN# SDVO_INT# SDVO_FLDSTALL# IN PEG_R2D_C_N<0> 70D5 PEG_R2D_C_N<1> 70D5 PEG_R2D_C_N<2> 70D5 PEG_R2D_C_N<3> 70C5 PEG_R2D_C_N<4> 70C5 PEG_R2D_C_N<5> 70C5 PEG_R2D_C_N<6> 70C5 PEG_R2D_C_N<7> 70C5 PEG_R2D_C_N<8> 70C5 PEG_R2D_C_N<9> 70B5 PEG_R2D_C_N<10> 70B5 PEG_R2D_C_N<11> 70B5 PEG_R2D_C_N<12> 70B5 PEG_R2D_C_N<13> 70B5 PEG_R2D_C_N<14> 70B5 PEG_R2D_C_N<15> G40 1% 1/16W MF-LF 402 SDVO Alternate Function AC38 G25 C37 PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB (3 OF 10) R1310 PEG_COMP PEG_D2R_N<0> 70D1 PEG_D2R_N<1> 70D1 PEG_D2R_N<2> 70D1 PEG_D2R_N<3> 70C1 PEG_D2R_N<4> 70C1 PEG_D2R_N<5> 70C1 PEG_D2R_N<6> 70C1 PEG_D2R_N<7> 70C1 PEG_D2R_N<8> 70C1 PEG_D2R_N<9> 70B1 PEG_D2R_N<10> 70B1 PEG_D2R_N<11> 70B1 PEG_D2R_N<12> 70B1 PEG_D2R_N<13> 70B1 PEG_D2R_N<14> 70B1 PEG_D2R_N<15> LVDS_A_DATA_N<0> LVDS_A_DATA_N<1> LVDS_A_DATA_N<2> LVDS_B_DATA_P<0> LVDS_B_DATA_P<1> LVDS_B_DATA_P<2> 2 945GM NB D32 PCI-EXPRESS GRAPHICS 19D4 19D3 OUT LVDS 19D4 19D3 OUT TV D 82A4 VGA 82A4 Can leave all signals NC if LVDS is not implemented Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used VCCD_LVDS must remain powered with proper decoupling. Otherwise, tie VCCD_LVDS to GND also. 5D4 13C5 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 24.9 OMIT LVDS Disable 1 PEG_R2D_C_P<0> 70D5 PEG_R2D_C_P<1> 70D5 PEG_R2D_C_P<2> 70D5 PEG_R2D_C_P<3> 70D5 PEG_R2D_C_P<4> 70C5 PEG_R2D_C_P<5> 70C5 PEG_R2D_C_P<6> 70C5 PEG_R2D_C_P<7> 70C5 PEG_R2D_C_P<8> 70C5 PEG_R2D_C_P<9> 70B5 PEG_R2D_C_P<10> 70B5 PEG_R2D_C_P<11> 70B5 PEG_R2D_C_P<12> 70B5 PEG_R2D_C_P<13> 70B5 PEG_R2D_C_P<14> 70B5 PEG_R2D_C_P<15> OUT OUT OUT OUT OUT OUT OUT OUT SDVOB_RED# SDVOB_GREEN# SDVOB_BLUE# SDVOB_CLKN SDVOC_RED# SDVOC_GREEN# SDVOC_BLUE# SDVOC_CLKN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT SDVOB_RED SDVOB_GREEN SDVOB_BLUE SDVOB_CLKP SDVOC_RED SDVOC_GREEN SDVOC_BLUE SDVOC_CLKP B OUT OUT OUT OUT OUT OUT OUT OUT NB PEG / Video Interfaces A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 13 1 87 A 6 7 R1440 1 1 10K 2 OMIT 5% 1/16W MF-LF 402 (D_PLLMON1#) (D_PLLMON1) (H_EDRDY#) (H_PCREQ#) (H_PLLMON1#) (H_PLLMON1) (H_PROCHOT#) (TESTIN#) (TV_DCONSEL0) (TV_DCONSEL1) (VSS_MCHDETECT) (LA_DATAN3) (LA_DATAP3) (LB_DATAN3) (LB_DATAP3) NC NC NC NC NC NC 19D3 19D4 19D3 19D4 19D3 19D4 34C7 IN 34B7 IN 34B7 IN 6D6 IN 6D6 IN 20C7 IN 6D6 IN 20C7 IN 6D6 IN 20B7 IN 6D6 IN 6D6 IN 6C6 IN 66B5 36D6 25B8 5A4 21D3 27D3 58C7 82A4 PP3V3_S0 R1420 1 10K 5% 1/16W MF-LF 402 2 52D5 52D3 51B7 29C3 28C3 IN 87C6 61C8 23C3 5B4 IN IN IN IN 6D7 IN 20C5 IN 6D6 IN 20B5 IN 20B5 IN 20A5 IN 23C5 OUT PLT_RST_L 1 100 52C1 21C2 7C6 OUT 61C7 26B5 5A4 IN 2 5% 1/16W MF-LF 402 19D4 19D3 19D4 19D3 IO IO 22A6 5A4 OUT 33B4 5B4 OUT SM_CK0 AY35 R32 RSVD2 RSVD3 BGA SM_CK1 SM_CK2 AR1 (2 OF 10) SM_CK3 AW40 MEM_CLK_P<0> 28A3 MEM_CLK_P<1> 29A3 MEM_CLK_P<2> 29D3 MEM_CLK_P<3> SM_CK0* SM_CK1* AW35 28D3 SM_CK2* AY7 SM_CK3* AY40 MEM_CLK_N<0> 28A3 MEM_CLK_N<1> 29A3 MEM_CLK_N<2> 29D3 MEM_CLK_N<3> SM_CKE0 SM_CKE1 AU20 30D6 28C6 AT20 30D6 28C3 SM_CKE2 BA29 SM_CKE3 AY29 RSVD4 RSVD5 AF11 RSVD6 H7 RSVD7 RSVD8 J19 K30 RSVD9 A41 RSVD10 RSVD11 NC_NB_XOR_LVDS_A35 NC_NB_XOR_LVDS_A34 NC_NB_XOR_LVDS_D28 NC_NB_XOR_LVDS_D27 A35 RSVD12 A34 RSVD13 RSVD14 D27 RSVD15 NB_BSEL<0> NB_BSEL<1> NB_BSEL<2> NB_CFG<3> NB_CFG<4> NB_CFG<5> NB_CFG<6> NB_CFG<7> NB_CFG<8> NB_CFG<9> NB_CFG<10> NB_CFG<11> NB_CFG<12> NB_CFG<13> TP_NB_CFG<14> TP_NB_CFG<15> NB_CFG<16> NB_CFG<17> NB_CFG<18> NB_CFG<19> NB_CFG<20> K16 K18 CFG0 CFG1 J18 CFG2 F18 CFG3 CFG4 PM_BMBUSY_L J29 D28 E15 F15 CFG5 E18 D19 CFG6 CFG7 D16 CFG8 G16 CFG9 CFG10 E16 PM_THRMTRIP_L VR_PWRGOOD_DELAY NB_RST_IN_L_R IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPD IPD IPD G15 CFG11 CFG12 K15 CFG13 C15 H16 CFG14 CFG15 G18 CFG16 H15 J25 CFG17 CFG18 K27 CFG19 J26 CFG20 G28 PM_BM_BUSY* F25 PM_EXTTS0* H26 PM_EXTTS1* PW_THRMTRIP* D15 G6 AW7 AT1 SM_CS0* SM_CS1* AW13 SM_CS2* SM_CS3* AY21 SMOCDCOMP0 AL20 SMOCDCOMP1 AF10 30D6 28B3 30D6 28B6 MEM_CS_L<0> MEM_CS_L<1> 30D6 29B3 MEM_CS_L<2> 30D6 29B6 MEM_CS_L<3> AW21 BA13 SM_ODT1 SM_ODT2 BA12 SM_ODT3 AU21 AV9 SMVREF0 AK1 SMVREF1 AK41 G_CLKIN D_REFCLKIN* A27 D_REFCLKIN A26 AG33 C40 D41 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT PP1V8_S3 30C6 28B3 MEM_ODT<0> 30C6 28B6 MEM_ODT<1> 30C6 29B3 MEM_ODT<2> 30C6 29B6 MEM_ODT<3> 1 OUT R1410 OUT 80.6 OUT OUT 32B4 32B3 29D6 28D6 14C2 NB_CLK100M_GCLKIN_N NB_CLK100M_GCLKIN_P NB_CLK_DREFCLKIN_N 5B4 NB_CLK_DREFCLKIN_P 5B4 NB_CLK_DREFSSCLKIN_N 5B4 NB_CLK_DREFSSCLKIN_P 34C5 34C4 33B4 5B4 34B4 34B2 5B4 34B4 34B2 34B5 34B4 33B4 34B5 34B4 33B4 DMI_RXN0 AE35 DMI_RXN1 DMI_RXN2 AF39 DMI_RXN3 AH39 DMI_S2N_N<0> 22D2 DMI_S2N_N<1> 22D2 DMI_S2N_N<2> 22D2 DMI_S2N_N<3> 22D2 AG35 DMI_S2N_P<0> DMI_S2N_P<1> 22D2 DMI_S2N_P<2> 22D2 DMI_S2N_P<3> IN C1415 IN 0.1uF IN IN AE39 IN DMI_RXP3 AG39 H32 CLK_REQ* D1 NC0 AE37 DMI_TXN1 DMI_TXN2 AF41 DMI_TXN3 AH41 AG37 C41 NC1 C1 DMI_TXP0 DMI_TXP1 AC37 BA41 NC2 NC3 BA40 NC4 DMI_TXP2 AF37 BA39 DMI_TXP3 BA3 NC5 NC6 AG41 BA2 NC7 BA1 NC8 NC9 B41 AY41 NC10 NC11 AY1 NC12 AW41 AW1 NC13 NC14 A40 NC15 A4 A39 NC16 NC17 A3 NC18 B2 DMI_N2S_P<0> DMI_N2S_P<1> 22D2 DMI_N2S_P<2> 22D2 DMI_N2S_P<3> AE41 0.1uF 20% 10V CERM 402 IN R1411 80.6 1% 1/16W MF-LF 2 402 IN DMI_RXP1 DMI_RXP2 DMI_TXN0 2 1 IN RSTIN* ICH_SYNC* 2 C1416 IN AH34 K28 1 IN IN 22D2 DMI_N2S_N<0> DMI_N2S_N<1> 22D2 DMI_N2S_N<2> 22D2 DMI_N2S_N<3> 1 MEMVREF_OUT MEMVREF_OUT IN 22D2 H27 C IN AC35 AF35 20% 10V CERM 402 IN DMI_RXP0 SDVO_CTRLCLK SDVO_CTRLDATA 1% 1/16W MF-LF 402 32B4 32B3 29D6 28D6 14C2 34C5 34C4 33B4 5B4 PWROK H28 2 5B2 5D4 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 31C5 32C6 37B2 64A6 64C1 67B6 67B8 MEM_RCOMP_L MEM_RCOMP AT9 AF33 OUT NC NC AY20 SMRCOMP* SMRCOMP D_REFSSCLKIN* D_REFSSCLKIN MEM_CKE<0> MEM_CKE<1> 30D6 29C6 MEM_CKE<2> 30D6 29C3 MEM_CKE<3> AW12 SM_ODT0 G_CLKIN* 28D3 AH33 TP_SDVO_CTRLCLK TP_SDVO_CTRLDATA NB_SB_SYNC_L CLK_NB_OE_L NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC B 945GM NB AG11 PM_EXTTS_L PM_DPRSLPVR R1430 79A8 26C3 26C1 26B1 26A4 22A6 6C7 6C6 5C4 82A4 6C6 6D7 RSVD1 F7 NC 19D3 19D4 T32 F3 TP_NB_XOR_FSB2_H7 TP_NB_TESTIN_L NB_TV_DCONSEL0 NB_TV_DCONSEL1 C D U1200 RSVD 2 DDR MUXING D R1441 CFG 5% 1/16W MF-LF 402 CLK 10K 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 21C3 20B4 20A4 19C7 19C6 17C6 14D6 10C5 5D4 25B4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 82D5 82C6 82B3 1 PP3V3_S0 PM 66B5 36D6 25B8 5A4 21D3 27D3 58C7 82A4 MISC DMI 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 21C3 20B4 20A4 19C7 19C6 17C6 14C7 10C5 5D4 25B4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 82D5 82C6 82B3 2 3 4 5 IN IN OUT OUT OUT OUT B OUT OUT OUT OUT NC 8 NB Misc Interfaces A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 14 1 87 A 8 6 7 D OMIT IO 28D3 IO 28D3 IO 28D6 IO 28D6 IO 28D6 28D6 28D3 28D3 28D6 28D6 IO IO IO IO IO 28D6 IO 28D6 IO 28D3 IO 28C3 28C6 28C6 28C6 28C3 28C3 28C3 28C3 IO IO IO IO IO IO IO IO IO 28C6 IO 28C3 IO 28C6 IO 28C6 28C3 28C6 IO IO IO 28C3 IO 28B3 IO 28B6 IO 28B3 IO 28B6 28B3 28B6 28B3 28B6 IO IO IO IO IO 28A3 IO 28A6 IO 28A3 28A6 B IO 28D3 28C6 C IO IO IO 28A3 IO 28A6 IO 28A6 IO 28A3 IO 28A6 IO 28A3 IO 28A6 IO 28A6 IO 28A3 IO 28A6 IO 28A3 IO 28A3 IO 28A3 IO 28B3 IO 28A6 IO 28B6 IO 28B6 IO 28A6 IO 28A3 28B3 IO IO AJ35 SA_DQ0 AJ34 SA_DQ1 SA_DQ2 AM31 AJ36 SA_DQ3 SA_DQ4 AK35 SA_DQ5 AM33 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AY13 30B6 28B6 SA_BS1 SA_BS2 AV14 SA_CAS* SA_DM2 AL26 AN22 SA_DQ8 SA_DM3 SA_DM4 AM14 SA_DM5 AL9 AR3 SA_DQ11 SA_DM6 SA_DM7 SA_DQ12 SA_DQ13 AH4 SA_DQS0 AK33 SA_DQ14 SA_DQ15 SA_DQS1 AT33 AN28 SA_DQ16 SA_DQS2 SA_DQS3 SA_DQS4 AN12 SA_DQS5 SA_DQS6 AN8 SA_DQS7 AG5 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 AN20 SA_DQ27 AP24 SA_DQ28 SA_DQ29 AP20 SA_DQ30 SA_DQS0* SA_DQS1* SA_DQS2* SA_DQS3* AK32 AU33 AN27 AM21 SA_DQS4* AM12 SA_DQS5* SA_DQS6* AL8 SA_DQS7* AH5 AN3 SA_MA0 AY16 SA_MA1 AU14 SA_MA2 SA_MA3 AW16 SA_MA4 SA_MA5 BA17 SA_DQ36 SA_DQ37 SA_MA6 AV17 AU17 SA_DQ38 SA_MA7 SA_MA8 SA_MA9 AT16 AK9 SA_DQ39 SA_DQ40 SA_DQ41 SA_MA10 SA_MA11 AU13 AN7 SA_MA12 AV20 SA_MA13 AV12 AT21 AR12 SA_DQ31 SA_DQ32 AR14 SA_DQ33 AP13 SA_DQ34 SA_DQ35 AP12 AT13 AT12 AL14 AL12 AK8 AK7 SA_DQ42 SA_DQ43 AP9 SA_DQ44 AN9 SA_DQ45 SA_DQ46 AT5 SA_RAS* SA_RCVENIN* AW17 AT17 30B6 28B3 AW14 AK23 29D6 IO OUT OUT OUT OUT OUT OUT IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MEM_A_A<0> 30C6 28B6 MEM_A_A<1> 30C6 28B3 MEM_A_A<2> 30C6 28B6 MEM_A_A<3> 30C6 28B3 MEM_A_A<4> 30C6 28B6 MEM_A_A<5> 30C6 28C3 MEM_A_A<6> 30C6 28C3 MEM_A_A<7> 30C6 28C6 MEM_A_A<8> 30C6 28C6 MEM_A_A<9> 30C6 28B6 MEM_A_A<10> 30C6 28C3 MEM_A_A<11> 30C6 28C6 MEM_A_A<12> 30C6 28B3 MEM_A_A<13> AU16 OUT OUT 30C6 28B3 BA16 IO OUT MEM_A_DQS_P<0> 28D6 MEM_A_DQS_P<1> 28C6 MEM_A_DQS_P<2> 28C3 MEM_A_DQS_P<3> 28B6 MEM_A_DQS_P<4> 28A6 MEM_A_DQS_P<5> 28A3 MEM_A_DQS_P<6> 28A3 MEM_A_DQS_P<7> 28D6 MEM_A_DQS_N<0> 28D6 MEM_A_DQS_N<1> 28C6 MEM_A_DQS_N<2> 28C3 MEM_A_DQS_N<3> 28B6 MEM_A_DQS_N<4> 28A6 MEM_A_DQS_N<5> 28A3 MEM_A_DQS_N<6> 28B3 MEM_A_DQS_N<7> AP3 29D3 OUT 28D6 AM22 OUT OUT MEM_A_CAS_L 28D3 MEM_A_DM<0> 28D3 MEM_A_DM<1> 28C3 MEM_A_DM<2> 28C6 MEM_A_DM<3> 28B3 MEM_A_DM<4> 28A3 MEM_A_DM<5> 28A6 MEM_A_DM<6> 28A6 MEM_A_DM<7> AM35 SA_DQ9 SA_DQ10 SA_DQ19 MEM_A_BS<0> MEM_A_BS<1> MEM_A_BS<2> (4 OF 10) SA_DQ6 SA_DQ7 AP21 AL23 BA20 AU12 AJ33 SA_DQ25 SA_DQ26 AL22 BGA 30B6 28B6 30B6 28B3 30B6 28C6 SA_BS0 SA_DM0 SA_DM1 SA_DQ17 SA_DQ18 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT MEM_A_RAS_L OUT NC NC 29D6 IO 29D3 IO 29D6 IO 29D3 IO 29D3 29D6 29D3 29D3 29D6 29D3 IO IO IO IO IO IO 29D3 IO 29D6 IO 29D6 IO 29D6 IO 29C3 29C3 29C3 29C6 29C6 29C6 29C3 29C6 29C6 IO IO IO IO IO IO IO IO IO 29C6 IO 29C3 IO 29C6 IO 29C3 IO 29C6 IO 29C3 IO 29C3 IO 29B3 IO 29B6 IO 29B6 IO 29B6 29B6 29B3 29B3 29B3 IO IO IO IO IO 29B6 IO 29B6 IO 29A6 29A6 IO IO 29B3 IO 29B3 IO 29A3 IO 29A3 IO 29A3 IO 29A6 IO AY2 SA_DQ47 SA_DQ48 AW2 SA_DQ49 AP1 29A3 IO AN2 SA_DQ50 SA_DQ51 29A6 IO AV2 SA_DQ52 29A6 IO AT3 29A3 IO AN1 SA_DQ53 SA_DQ54 29A6 IO AL2 SA_DQ55 29A3 IO AG7 SA_DQ56 SA_DQ57 29A3 IO 29A3 IO SA_DQ58 SA_DQ59 29A3 IO AF6 29A6 IO AG9 SA_DQ60 29A6 IO AH6 SA_DQ61 SA_DQ62 29A6 IO AF4 AF8 SA_DQ63 29A3 AL5 AF9 AG4 D U1200 945GM NB SA_RCVENOUT* AK24 SA_WE* AY14 30B6 28B6 MEM_A_WE_L OUT 29A6 IO IO MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63> AY28 30A6 29B6 30A6 29B3 30A6 29C6 SB_CAS* AR24 30A6 29B6 SB_DM0 SB_DM1 AK36 SB_DQ6 SB_DQ7 SB_DM2 AT36 BA31 SB_DQ8 SB_DM3 SB_DM4 SB_DQ9 SB_DQ10 SB_DM5 AH8 BA5 SB_DQ11 SB_DM6 SB_DM7 AK39 SB_DQ0 AJ37 SB_DQ1 SB_DQ2 AP39 AJ38 SB_DQ3 SB_DQ4 AK38 SB_DQ5 AR41 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 945GM NB BGA SB_BS0 AT24 SB_BS1 SB_BS2 AV23 MEM_B_BS<0> MEM_B_BS<1> MEM_B_BS<2> OUT OUT OUT (5 OF 10) AN4 MEM_B_CAS_L 29D3 MEM_B_DM<0> 29D3 MEM_B_DM<1> 29C3 MEM_B_DM<2> 29C6 MEM_B_DM<3> 29B3 MEM_B_DM<4> 29A6 MEM_B_DM<5> 29A6 MEM_B_DM<6> 29A3 MEM_B_DM<7> SB_DQS0 AM39 29D6 SB_DQ14 SB_DQ15 SB_DQS1 AT39 AU35 SB_DQ16 SB_DQS2 SB_DQS3 SB_DQS4 AR16 SB_DQS5 SB_DQS6 AR10 SB_DQS7 AN5 SB_DQ12 SB_DQ13 AR38 AL17 OUT OUT OUT OUT OUT OUT OUT OUT OUT SB_DQS0* SB_DQS1* AM40 SB_DQS2* SB_DQS3* AT35 SB_DQS4* AP16 SB_DQS5* SB_DQS6* AT10 SB_DQS7* AP5 MEM_B_DQS_P<0> 29D6 MEM_B_DQS_P<1> 29C6 MEM_B_DQS_P<2> 29C3 MEM_B_DQS_P<3> 29B6 MEM_B_DQS_P<4> 29A3 MEM_B_DQS_P<5> 29A3 MEM_B_DQS_P<6> 29A6 MEM_B_DQS_P<7> 29D6 MEM_B_DQS_N<0> 29D6 MEM_B_DQS_N<1> 29C6 MEM_B_DQS_N<2> 29C3 MEM_B_DQS_N<3> 29B6 MEM_B_DQS_N<4> 29B3 MEM_B_DQS_N<5> 29A3 MEM_B_DQS_N<6> 29A6 MEM_B_DQS_N<7> SB_MA0 AY23 30B6 29B3 SB_MA1 AW24 SB_MA2 SB_MA3 AY24 SB_MA4 SB_MA5 AT27 SB_DQ36 SB_DQ37 SB_MA6 AU27 AV28 SB_DQ38 SB_MA7 SB_MA8 SB_MA9 AW27 AJ11 SB_DQ39 SB_DQ40 SB_DQ41 SB_MA10 SB_MA11 AV24 AH10 SB_MA12 AY27 SB_MA13 AR23 MEM_B_A<0> 30B6 29B6 MEM_B_A<1> 30B6 29B3 MEM_B_A<2> 30B6 29B6 MEM_B_A<3> 30B6 29B3 MEM_B_A<4> 30B6 29B6 MEM_B_A<5> 30B6 29C3 MEM_B_A<6> 30B6 29C3 MEM_B_A<7> 30B6 29C6 MEM_B_A<8> 30B6 29C6 MEM_B_A<9> 30B6 29B6 MEM_B_A<10> 30B6 29C3 MEM_B_A<11> 30B6 29C6 MEM_B_A<12> 30B6 29B3 MEM_B_A<13> SB_RAS* SB_RCVENIN* AU23 30A6 29B3 MEM_B_RAS_L OUT SB_RCVENOUT* AK18 SB_WE* AR27 30A6 29B6 MEM_B_WE_L OUT AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 AT31 SB_DQ25 SB_DQ26 AU29 SB_DQ27 BA33 AW31 SB_DQ28 SB_DQ29 AV29 SB_DQ30 AU31 AW29 AM19 SB_DQ31 SB_DQ32 AL19 SB_DQ33 AP14 SB_DQ34 SB_DQ35 AN14 AN17 AM16 AP15 AL15 AJ9 AN10 SB_DQ42 SB_DQ43 AK13 SB_DQ44 AH11 SB_DQ45 SB_DQ46 AK10 BA10 SB_DQ47 SB_DQ48 AW10 SB_DQ49 BA4 AW4 SB_DQ50 SB_DQ51 AY10 SB_DQ52 AY9 AW5 SB_DQ53 SB_DQ54 AY5 SB_DQ55 AV4 SB_DQ56 SB_DQ57 AJ8 AR5 AK3 SB_DQ58 SB_DQ59 AT4 SB_DQ60 AK5 AJ5 SB_DQ61 SB_DQ62 AJ3 SB_DQ63 AK4 DDR SYSTEM MEMORY B 28D3 MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63> DDR SYSTEM MEMORY A IO 1 OMIT U1200 28D3 2 3 4 5 AR29 AR7 AU39 AP29 AT7 AR28 AT28 AV27 BA27 AK16 IO IO IO IO IO IO IO IO IO C IO IO IO IO IO IO IO OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT NC NC B NB DDR2 Interfaces A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 15 1 87 A 8 6 7 2 3 4 5 1 NCTF balls are Not Critical To Function PP1V05_S0 AD27 AC27 AB27 AA27 D VCC_NCTF4 W27 V27 VCC_NCTF5 VCC_NCTF6 U27 VCC_NCTF7 T27 VCC_NCTF8 VCC_NCTF9 AD26 VCC_NCTF10 AC26 VCC_NCTF11 VCC_NCTF12 AB26 AA26 L16 N16 M16 VCC_109 VCC_110 M17 VCC_SM64 VCC_SM65 VCC_SM66 VCC_SM67 VCC_SM68 VCC_SM69 VCC_SM70 VCC_SM71 VCC_SM72 VCC_SM73 VCC_SM74 VCC_SM75 VCC_SM76 VCC_SM77 VCC_SM78 VCC_SM79 VCC_SM80 VCC_SM81 VCC_SM82 VCC_SM83 VCC_SM84 VCC_SM85 VCC_SM86 VCC_SM87 VCC_SM88 VCC_SM89 VCC_SM90 VCC_SM91 VCC_SM92 VCC_SM93 VCC_SM94 VCC_SM95 VCC_SM96 VCC_SM97 VCC_SM98 VCC_SM99 VCC_SM100 VCC_SM101 VCC_SM102 VCC_SM103 VCC_SM104 VCC_SM105 VCC_SM106 VCC_SM107 AP19 AK19 AJ18 AH17 AJ16 BA15 AY15 AV15 AU15 AR15 AJ14 AJ13 AK12 AJ12 AG12 AK11 AY8 AV8 AT8 AP8 BA6 AW6 AV6 AR6 AN6 AL6 AJ6 AV1 AJ1 VCC_SM62 VCC_SM63 AT19 AK6 VCC_SM61 AU19 10% 6.3V CERM-X5R 402 AP6 VCC_SM59 VCC_SM60 AW19 PP1V8_S3 AT6 VCC_SM58 AY19 AY6 VCC_SM56 VCC_SM57 AK20 AR8 VCC_SM54 VCC_SM55 AJ22 AW8 VCC_SM53 AK22 BA8 VCC_SM51 VCC_SM52 AR22 AH12 VCC_SM50 AT22 AH13 VCC_SM48 VCC_SM49 AV22 AJ15 VCC_SM47 AW22 AT15 VCC_SM45 VCC_SM46 BA22 AW15 VCC_SM43 VCC_SM44 BA23 AH16 VCC_SM42 AH24 AJ17 VCC_SM40 VCC_SM41 AH25 AJ19 VCC_SM39 AJ25 2 AR19 VCC_SM37 VCC_SM38 AJ26 2 AV19 VCC_SM36 AR26 10% 6.3V CERM-X5R 402 BA19 VCC_SM34 VCC_SM35 AU26 0.47UF 10% 6.3V CERM-X5R 402 37B2 28D6 5B2 19D7 29D6 AK21 VCC_SM32 VCC_SM33 AW26 0.47UF AP22 VCC_SM31 AY26 C1613 AU22 VCC_SM29 VCC_SM30 AH27 1 AY22 VCC_SM28 AJ27 1 AJ23 VCC_SM26 VCC_SM27 AJ28 AJ24 VCC_SM25 AH29 AH26 VCC_SM23 VCC_SM24 AK29 AT26 VCC_SM21 VCC_SM22 AM29 AV26 VCC_SM20 AM30 BA26 VCC_SM18 VCC_SM19 AP30 AH28 VCC_SM17 AR30 AJ29 VCC_SM15 VCC_SM16 AU30 AL29 VCC_SM14 AV30 AN30 VCC_SM12 VCC_SM13 AY30 AT30 VCC_SM10 VCC_SM11 AR34 AW30 VCC_SM9 AT34 BA30 VCC_SM7 VCC_SM8 AV34 AU34 VCC_SM6 AW34 AY34 VCC_SM4 VCC_SM5 2 C1614 67B8 67B6 64C1 64A6 29D3 29B2 14C2 5D4 28D3 28B2 32C6 31C5 0.47UF C1615 VCC_108 P17 L18 N17 VCC_106 VCC_107 VCC_105 N18 L19 M18 VCC_103 VCC_104 VCC_102 N19 Y19 AA19 AB19 M19 VCC_100 VCC_101 VCC_98 VCC_99 VCC_97 M20 N20 L20 VCC_95 VCC_96 VCC_94 W20 Y20 P20 VCC_92 VCC_93 VCC_91 AC20 L21 M21 N21 AB20 VCC_89 VCC_90 VCC_87 VCC_88 VCC_86 AA21 AC21 W21 VCC_84 VCC_85 VCC_83 M22 N22 L22 VCC_81 VCC_82 VCC_80 W22 P22 VCC_78 VCC_79 AB22 AC22 L23 M23 N23 Y22 VCC_76 VCC_77 VCC_75 VCC_73 VCC_74 VCC_72 Y23 AA23 P23 VCC_70 VCC_71 VCC_69 M24 AB23 VCC_67 VCC_68 P24 L25 M25 N25 L26 N26 P26 L27 N24 VCC_65 VCC_66 VCC_64 VCC_62 VCC_63 VCC_61 VCC_59 VCC_60 VCC_58 N27 M27 VCC_56 VCC_57 L28 M28 P27 VCC_54 VCC_55 VCC_53 P28 R28 T28 U28 V28 N28 VCC_51 VCC_52 VCC_50 VCC_48 VCC_49 VCC_47 AA28 Y28 VCC_45 VCC_46 L29 M29 AB28 VCC_43 VCC_44 VCC_42 R29 U29 P29 VCC_40 VCC_41 VCC_39 W29 Y29 AA29 L30 V29 VCC_37 VCC_38 VCC_36 VCC_34 VCC_35 N30 P30 M30 VCC_32 VCC_33 VCC_31 T30 U30 R30 VCC_29 VCC_30 VCC_28 W30 Y30 AA30 M31 V30 VCC_26 VCC_27 VCC_25 VCC_23 VCC_24 P31 R31 N31 VCC_21 VCC_22 VCC_20 V31 W31 T31 VCC_18 VCC_19 VCC_17 J32 L32 AA31 VCC_15 VCC_16 VCC_14 M32 N32 VCC_12 VCC_13 V32 P32 VCC_10 Y32 W32 VCC_8 VCC_9 AA32 L33 J33 VCC_6 VCC_7 VCC_5 (6 OF 10) P33 N33 VCC_3 VCC_4 W33 VCC_SM3 AM41 BA34 BGA VCC_2 VCC_0 VCC_1 AU40 1 NB_VCCSM_LF2 NB_VCCSM_LF1 Layout Note: Place near pin BA23 1 1 10uF 20% 6.3V X5R 603 2 2 C1621 C1610 C1612 10uF 0.47UF 0.47UF 0.47UF 20% 6.3V X5R 603 10% 6.3V CERM-X5R 402 10% 6.3V CERM-X5R 402 10% 6.3V CERM-X5R 402 1 2 1 2 1 2 Layout Note: Place in cavity VSS_NCTF7 AE20 VSS_NCTF8 VSS_NCTF9 AE19 VSS_NCTF10 AC17 VSS_NCTF11 VSS_NCTF12 Y17 AE18 U17 VCCAUX_NCTF0 AG27 R26 VCCAUX_NCTF1 VCCAUX_NCTF2 AF27 VCC_NCTF18 VCCAUX_NCTF3 AF26 AD25 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 AB25 VCCAUX_NCTF4 VCCAUX_NCTF5 AG25 AC25 VCC_NCTF22 VCC_NCTF23 VCCAUX_NCTF6 VCCAUX_NCTF7 AG24 VCCAUX_NCTF8 AG23 W25 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 U25 VCCAUX_NCTF9 VCCAUX_NCTF10 AF23 V25 VCCAUX_NCTF11 AF22 T25 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 AD24 VCCAUX_NCTF12 VCCAUX_NCTF13 AG21 R25 VCCAUX_NCTF14 AG20 AC24 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 AA24 VCCAUX_NCTF15 VCCAUX_NCTF16 AF20 AB24 VCC_NCTF33 VCC_NCTF34 VCCAUX_NCTF17 VCCAUX_NCTF18 AF19 VCCAUX_NCTF19 AG18 V24 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 T24 VCCAUX_NCTF20 VCCAUX_NCTF21 AF18 U24 VCCAUX_NCTF22 AG17 R24 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 V23 VCCAUX_NCTF23 VCCAUX_NCTF24 AF17 AD23 VCCAUX_NCTF25 AD17 U23 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 R23 VCCAUX_NCTF26 VCCAUX_NCTF27 AB17 T23 VCC_NCTF44 VCC_NCTF45 VCCAUX_NCTF28 VCCAUX_NCTF29 W17 VCC_NCTF46 VCC_NCTF47 VCCAUX_NCTF30 T17 R17 T22 VCC_NCTF48 R22 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 AF16 AD21 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 U21 VCCAUX_NCTF34 VCCAUX_NCTF35 AE16 V21 VCCAUX_NCTF36 AC16 T21 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 AD20 VCCAUX_NCTF37 VCCAUX_NCTF38 AB16 R21 VCC_NCTF55 VCC_NCTF56 VCCAUX_NCTF39 VCCAUX_NCTF40 Y16 VCC_NCTF57 VCC_NCTF58 VCCAUX_NCTF41 V16 U16 R20 VCC_NCTF59 AD19 VCCAUX_NCTF42 VCCAUX_NCTF43 VCC_NCTF60 VCC_NCTF61 VCCAUX_NCTF44 R16 U19 VCC_NCTF62 T19 VCCAUX_NCTF45 VCCAUX_NCTF46 AG15 VCCAUX_NCTF47 AE15 AD18 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 AB18 VCCAUX_NCTF48 VCCAUX_NCTF49 AD15 AC18 VCC_NCTF66 VCC_NCTF67 VCCAUX_NCTF50 VCCAUX_NCTF51 AB15 VCC_NCTF68 VCC_NCTF69 VCCAUX_NCTF52 Y15 W15 V18 VCC_NCTF70 U18 VCCAUX_NCTF53 VCCAUX_NCTF54 VCC_NCTF71 VCC_NCTF72 VCCAUX_NCTF55 U15 VCCAUX_NCTF56 VCCAUX_NCTF57 T15 U20 T20 V19 AA18 Y18 W18 T18 D AE21 T26 V20 B AE22 AE24 U26 V22 Layout Note: Place near pin BA15 AE23 VSS_NCTF5 VSS_NCTF6 VCC_NCTF16 VCC_NCTF17 AD22 C1611 VSS_NCTF4 VCC_NCTF15 U22 C1620 AE25 AE26 V26 W24 VCC_SM1 VCC_SM2 NB_VCCSM_LF4 NB_VCCSM_LF5 (7 OF 10) AE27 VSS_NCTF2 VSS_NCTF3 W26 Y24 VCC_SM0 OMIT AT41 945GM NB Speed 400MTs 533MTs 667MTs AU41 U1200 C 1.8V Max Current 1 Channel 2 Channel 1300mA 2400mA 1500mA 2800mA 1700mA 3200mA BGA VSS_NCTF0 VSS_NCTF1 Y26 Y25 VCC AA33 1.05V or 1.5V VCC_11 PP1V05_S0 945GM NB VCC_NCTF13 VCC_NCTF14 AA25 24D3 25C4 25D3 34B8 19C8 19D1 19D2 19D5 5B2 5D4 7B5 7B6 7D5 13B5 16D3 17D3 17D6 19D6 19D7 21C1 24C3 34C6 34C8 55A4 65A2 67D6 67D8 U1200 VCC_NCTF2 VCC_NCTF3 Y27 R27 1.05V, Internal Graphics: 3500mA Max 1.05V, External Graphics: 1500mA Max 8C7 9B7 11B3 11C5 12A7 12B7 12C2 1.5V, Internal Graphics: 5500mA Max VCC_NCTF0 VCC_NCTF1 NCTF 55A4 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7 12B7 12A7 11C5 11B3 9B7 8C7 7D5 7B6 7B5 5D4 5B2 19D6 19D5 19D2 19D1 19C8 17D6 17D3 16C8 13B5 12C2 67D8 67D6 65A2 These connections can break without impacting part performance. OMIT 62A7 67B6 19D2 19D5 19C1 19C4 17C6 19A5 5D4 13C5 13D2 17B6 19B5 19B8 19C5 19D1 19D6 19D7 67C6 67C8 PP1V5_S0_NB AG26 AF25 AF24 AG22 AF21 C AG19 R19 R18 AE17 AA17 V17 AG16 AD16 AA16 W16 B T16 AF15 AC15 AA15 V15 R15 NB Power 1 A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 16 1 87 A 8 7 6 70mA Max VCCA_CRTDAC/VCCSYNC 66B5 63D1 19D7 19C5 19A8 19A6 19A4 17D6 17C6 5D4 82D3 82C5 67B6 67A8 67A6 OMIT GND H22 VCCSYNC PP2V5_S0 C30 VCC_TXLVDS0 VCC_TXLVDS1 B30 60mA Max A30 VTT0 AC14 945GM NB VTT1 VTT2 AB14 BGA VTT3 VTT4 V14 VCC_TXLVDS2 D 1500mA Max VCC3G/3GPLL VTT5 R14 VCC3G1 VCC3G2 VTT6 VTT7 P14 V41 VCC3G3 VTT8 M14 R41 VCC3G4 VCC3G5 VTT9 VTT10 L14 VTT11 AC13 VTT12 VTT13 AB13 VTT14 VTT15 Y13 N41 L41 19B3 66B5 63D1 19D7 19C5 19A8 19A6 19A4 17D6 17C6 5D4 82D3 82C5 67B6 67A8 67A6 55A4 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7 12B7 12A7 11C5 11B3 9B7 8C7 7D5 7B6 7B5 5D4 5B2 19D6 19D5 19D2 19D1 19C8 17D3 16D3 16C8 13B5 12C2 67D8 67D6 65A2 PP1V5_S0_NB_VCCA_3GPLL PP2V5_S0 GND G41 PP1V05_S0 VCC3G6 VCCA_3GPLL VCCA_3GBG 2mA Max AD13 AA13 H41 VSSA_3GBG F21 VCCA_CRTDAC0 See VCCSYNC VCCA_CRTDAC1 VTT16 V13 U13 E21 D N14 W13 GND G21 VSSA_CRTDAC VTT17 VTT18 PP1V5_S0_NB_VCCA_DPLLA PP1V5_S0_NB_VCCA_DPLLB PP1V5_S0_NB_VCCA_HPLL B26 VCCA_DPLLA 50mA Max VTT19 R13 C39 VCCA_DPLLB 50mA Max VCCA_HPLL 45mA Max VTT20 VTT21 N13 A38 VCCA_LVDS 10mA Max VTT22 L13 PP2V5_S0 GND B39 VTT23 VTT24 AB12 VSSA_LVDS PP1V5_S0_NB_VCCA_MPLL AF2 VCCA_MPLL 45mA Max Y12 PP1V5_S0_NB GND H20 VTT25 VTT26 VCCA_TVBG VSSA_TVBG VTT27 V12 PP1V5_S0_NB E20 VCCA_TVDACC0 VTT28 VTT29 U12 67C8 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 67C6 67B6 62A7 19D7 19D6 19D5 19D2 19D1 19C5 19C4 F20 VCCA_TVDACC1 VTT30 R12 67C8 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 67C6 67B6 62A7 19D7 19D6 19D5 19D2 19D1 19C5 19C4 PP1V5_S0_NB C20 VCCA_TVDACB0 VCCA_TVDACB1 VTT31 VTT32 P12 34B2 19A6 19A6 19B6 67A6 66B5 63D1 19D7 19C5 19A8 19A6 19A4 17D6 5D4 82D3 82C5 67B6 67A8 19B6 67C8 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 67C6 67B6 62A7 19D7 19D6 19D5 19D2 19D1 19C5 19C4 67C8 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 67C6 67B6 62A7 19D7 19D6 19D5 19D2 19D1 19C5 19C4 C AC33 AF1 G20 D20 PP1V5_S0_NB 67C8 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 67C6 67B6 62A7 19D7 19D6 19D5 19D2 19D1 19C5 19C4 PP1V5_S0_NB 67C8 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 67C6 67B6 62A7 19D7 19D6 19D5 19D2 19D1 19C5 19C4 T13 M13 AA12 W12 T12 N12 E19 VCCA_TVDACA0 VTT33 M12 F19 VCCA_TVDACA1 L12 AH1 VCCD_HMPLL0 VTT34 VTT35 VTT36 VTT37 P11 150mA Max VCCD_HMPLL1 PP1V5_S0_NB A28 VCCD_LVDS0 VTT38 M11 20mA Max B28 VCCD_LVDS1 VCCD_LVDS2 VTT39 VTT40 R10 VTT41 N10 VTT42 VTT43 M10 VTT44 N9 VTT45 VTT46 M9 P8 67C8 5D4 19C4 36D6 25B8 5A4 21D3 27D3 58C7 66B5 82A4 PP1V5_S0_NB 67C8 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 67C6 67B6 62A7 19D7 19D6 19D5 19D2 19D1 19C5 19C4 67C8 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 67C6 67B6 62A7 19D7 19D6 19D5 19D2 19D1 19C5 19C4 D21 VCCD_TVDAC C R11 AH2 C28 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 67C6 67B6 62A7 19D7 19D6 19D5 19D2 19D1 19C5 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 21C3 20B4 20A4 19C7 19C6 14D6 14C7 10C5 5D4 25B4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 82D5 82C6 82B3 120mA Max 800mA Max T14 VCC3G0 AB41 Y41 N11 P10 A23 VCC_HV0 B23 VCC_HV1 B25 VCC_HV2 PP1V5_S0_NB H19 VCCD_QTVDAC PP1V5_S0_NB AK31 VCCAUX0 VTT47 VTT48 AF31 VCCAUX1 VTT49 M8 AE31 VCCAUX2 VCCAUX3 VTT50 VTT51 P7 AC31 AL30 VCCAUX4 VTT52 M7 AK30 VTT53 VTT54 R6 AJ30 VCCAUX5 VCCAUX6 AH30 VCCAUX7 VTT55 M6 AG30 VCCAUX8 VCCAUX9 VTT56 VTT57 A6 VCCAUX10 VCCAUX11 VTT58 VTT59 P5 C1713 N5 0.47UF AC30 VCCAUX12 VTT60 M5 AG29 VTT61 VTT62 P4 AF29 VCCAUX13 VCCAUX14 10% 6.3V CERM-X5R 402 AE29 VCCAUX15 VTT63 M4 AD29 VCCAUX16 VCCAUX17 VTT64 VTT65 R3 AC29 AG28 VCCAUX18 VTT66 N3 AF28 VCCAUX19 VCCAUX20 VTT67 VTT68 M3 VCCAUX21 VCCAUX22 VTT69 VTT70 P2 AJ21 AH21 VCCAUX23 VTT71 D2 AJ20 VCCAUX24 VCCAUX25 VTT72 VTT73 AB1 AH20 AH19 VCCAUX26 VTT74 P1 C1711 P19 VCCAUX27 VCCAUX28 VTT75 VTT76 N1 0.47UF P16 M1 AH15 VCCAUX29 10% 6.3V CERM-X5R 402 P15 VCCAUX30 VCCAUX31 PP3V3_S0 40mA Max 1900mA Max AF30 AE30 AD30 B AE28 AH22 AH14 AG14 A AF14 VCCAUX32 VCCAUX33 AE14 VCCAUX34 Y14 AF13 VCCAUX35 VCCAUX36 AE13 VCCAUX37 AF12 AE12 VCCAUX38 VCCAUX39 AD12 VCCAUX40 24mA Max 1 W14 AJ41 POWER PP1V5_S0_NB_VCC3G 2 21C1 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 65A2 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D6 19C8 19D1 19D2 19D5 19D6 19D7 67D6 67D8 PP1V05_S0 U1200 (8 OF 10) 19B3 3 4 5 P9 R8 N8 N7 P6 NB_VTTLF_CAP3 R5 1 B 2 N4 P3 R2 M2 NB_VTTLF_CAP2 NB_VTTLF_CAP1 R1 1 1 2 2 C1712 0.22uF 20% 6.3V X5R 402 NB Power 2 SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 17 1 87 A 8 6 7 5 3 4 OMIT AC41 AA41 W41 VSS_3 P41 VSS_4 VSS_5 NB BGA (9 OF 10) AK34 VSS_98 VSS_99 AG34 VSS_100 AE34 VSS_101 VSS_102 AC34 VSS_105 AR33 VSS_106 VSS_107 AE33 AN40 VSS_9 VSS_10 AK40 VSS_11 VSS_108 Y33 VSS_109 VSS_110 V33 AH40 VSS_12 VSS_13 AG40 VSS_14 VSS_111 R33 AF40 VSS_15 VSS_16 VSS_112 VSS_113 M33 VSS_17 VSS_18 VSS_114 VSS_115 G33 VSS_19 VSS_116 D33 VSS_117 VSS_118 B33 AR39 VSS_20 VSS_21 AN39 VSS_22 VSS_119 AG32 VSS_120 VSS_121 AF32 AC39 VSS_23 VSS_24 AB39 VSS_25 VSS_122 AC32 VSS_26 VSS_27 VSS_123 VSS_124 AB32 VSS_28 VSS_29 VSS_125 VSS_126 B32 VSS_30 VSS_127 AV31 VSS_31 VSS_32 VSS_128 VSS_129 AN31 VSS_33 VSS_130 AG31 VSS_131 VSS_132 AB31 L39 VSS_34 VSS_35 J39 VSS_36 VSS_133 AB30 VSS_37 VSS_38 VSS_134 VSS_135 E30 VSS_136 VSS_137 AN29 D39 VSS_39 VSS_40 AT38 VSS_41 VSS_138 T29 VSS_42 VSS_43 VSS_139 VSS_140 N29 VSS_44 VSS_141 G29 VSS_142 VSS_143 E29 AE38 VSS_45 VSS_46 C38 VSS_47 VSS_144 B29 VSS_48 VSS_49 VSS_145 VSS_146 A29 VSS_50 VSS_51 VSS_147 VSS_148 AW28 AY39 AW39 AV39 AJ39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 H39 G39 F39 AM38 AH38 AG38 AF38 AK37 AH37 AB37 AA37 VSS_66 VSS_163 B27 AW36 VSS_67 VSS_68 VSS_164 VSS_165 AN26 VSS_69 VSS_166 K26 VSS_70 VSS_71 VSS_167 VSS_168 F26 VSS_72 VSS_73 VSS_169 VSS_170 AK25 H25 VSS_294 VSS_295 Y21 VSS_203 VSS_296 AA8 P21 VSS_204 VSS_205 VSS_297 VSS_298 U8 VSS_299 VSS_300 C8 H21 VSS_206 VSS_207 C21 VSS_208 VSS_301 AV7 AW20 VSS_209 VSS_210 VSS_302 VSS_303 AP7 AR20 AM20 VSS_211 VSS_304 AJ7 AA20 VSS_212 VSS_213 VSS_305 VSS_306 AH7 K20 B20 VSS_214 VSS_307 AC7 A20 VSS_215 VSS_216 VSS_308 VSS_309 R7 VSS_217 VSS_218 VSS_310 VSS_311 D7 VSS_77 VSS_174 D25 AR35 VSS_78 VSS_79 VSS_175 VSS_176 A25 BA24 VSS_80 VSS_177 AU24 VSS_81 VSS_82 VSS_178 VSS_179 AL24 VSS_92 VSS_93 AH9 Y9 E9 AD8 K8 BA7 AL7 AF7 AG6 VSS_312 VSS_220 VSS_221 VSS_313 VSS_314 AB6 AH18 VSS_222 VSS_315 U6 P18 VSS_223 VSS_224 VSS_316 VSS_317 N6 H18 D18 VSS_225 VSS_318 H6 A18 VSS_226 VSS_227 VSS_319 VSS_320 B6 VSS_321 VSS_322 AF5 AP17 VSS_228 VSS_229 AM17 VSS_230 VSS_323 AY4 AK17 VSS_324 VSS_325 AR4 AV16 VSS_231 VSS_232 AN16 VSS_233 VSS_326 AL4 AL16 VSS_234 VSS_235 VSS_327 VSS_328 AJ4 J16 F16 VSS_236 VSS_329 U4 C16 VSS_237 VSS_238 VSS_330 VSS_331 R4 VSS_332 VSS_333 F4 AK15 VSS_239 VSS_240 N15 VSS_241 VSS_334 AY3 M15 VSS_335 VSS_336 AW3 L15 VSS_242 VSS_243 B15 VSS_244 VSS_337 AL3 Y6 K6 AV5 AD5 AP4 Y4 J4 C4 BA14 VSS_245 VSS_246 VSS_338 VSS_339 AT14 VSS_247 VSS_340 AF3 AK14 VSS_248 VSS_249 VSS_341 VSS_342 AD3 VSS_343 VSS_344 AA3 U14 VSS_250 VSS_251 K14 VSS_252 VSS_345 AT2 H14 VSS_346 VSS_347 AR2 E14 VSS_253 VSS_254 AV13 VSS_255 VSS_348 AK2 AR13 VSS_349 VSS_350 AJ2 AN13 VSS_256 VSS_257 AM13 VSS_258 VSS_351 AB2 AL13 VSS_259 VSS_260 VSS_352 VSS_353 Y2 VSS_261 VSS_262 VSS_354 VSS_355 T2 F13 D13 VSS_263 VSS_356 J2 B13 VSS_357 VSS_358 H2 AY12 VSS_264 VSS_265 AC12 VSS_266 VSS_359 C2 K12 VSS_360 AL1 H12 VSS_267 VSS_268 E12 VSS_269 VSS_270 VSS_271 Y11 VSS_272 B AV3 AH3 AA11 C G7 VSS_219 AD11 D BA9 C19 P13 VSS_91 AC10 G19 AW23 VSS_89 VSS_90 VSS AL10 AD6 AG13 VSS_88 (10 OF 10) K19 E25 AV35 AN34 VSS_201 VSS_202 AG8 AB21 P25 VSS_172 VSS_173 D35 A9 AL21 AA14 VSS_75 VSS_76 F35 VSS_293 D26 B36 G35 VSS_200 AD14 K25 H35 AN21 M26 VSS_171 J35 G9 A15 VSS_74 L35 VSS_291 VSS_292 C27 C36 M35 VSS_198 VSS_199 J27 AY36 N35 R9 AR21 AM15 F27 P35 VSS_290 AM27 VSS_161 VSS_162 VSS_86 VSS_87 VSS_197 AV21 AN15 VSS_64 VSS_65 R35 BA21 J28 F37 VSS_85 VSS_288 VSS_289 AD28 G27 T35 VSS_195 VSS_196 AB9 A22 AU28 VSS_160 V35 AR9 BA28 VSS_63 VSS_83 VSS_84 VSS_286 VSS_287 AR17 G37 W35 VSS_193 VSS_194 AY17 AK27 Y35 F22 C29 VSS_158 VSS_159 AA35 AW9 K29 VSS_61 VSS_62 AB35 VSS_285 AB29 AP27 AH35 VSS_192 W19 VSS_156 VSS_157 BA35 G22 AT29 VSS_59 VSS_60 AC36 VSS_283 VSS_284 AC19 E28 AE36 VSS_190 VSS_191 U10 K22 AN19 VSS_155 AF36 W10 AA22 Y31 VSS_58 AG36 VSS_282 AJ31 W28 AH36 VSS_189 AY31 VSS_153 VSS_154 AN36 C23 G32 VSS_56 VSS_57 D37 VSS_280 VSS_281 J21 AC28 H37 VSS_187 VSS_188 AG10 F23 K21 VSS_152 J37 AJ10 J23 AE32 VSS_55 L37 VSS_279 AH32 AM28 M37 VSS_277 VSS_278 VSS_186 F33 VSS_150 VSS_151 N37 VSS_184 VSS_185 K23 H33 VSS_53 VSS_54 B11 W23 D22 W37 BGA AP10 E22 AP28 P37 AV10 T33 VSS_149 R37 D11 VSS_275 VSS_276 AB33 VSS_52 T37 945GM NB VSS_274 VSS_182 VSS_183 AV33 Y37 V37 J11 VSS_181 AM23 C34 VSS_8 B40 VSS_273 AN23 U1200 AC23 AV40 AE40 VSS_180 AH23 F41 VSS AT23 AF34 AW33 AJ40 A 945GM 1 OMIT VSS_97 VSS_103 VSS_104 AP40 B U1200 VSS_6 VSS_7 J41 C VSS_1 VSS_2 T41 M41 D VSS_0 2 AG3 AC3 G3 AP2 AD2 U2 N2 F2 NB Grounds SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE VSS_94 VSS_95 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART VSS_96 SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 18 1 87 A 8 6 7 34C8 34C6 34B8 25D3 25C4 24D3 24C3 21C1 19D7 12B7 12A7 11C5 11B3 9B7 8C7 7D5 7B6 7B5 5D4 5B2 19D5 19D2 19D1 19C8 17D6 17D3 16D3 16C8 13B5 12C2 67D8 67D6 65A2 55A4 55A4 65A2 67D6 67D8 25C4 25D3 34B8 34C6 34C8 19D5 19D6 19D7 21C1 24C3 24D3 17D3 17D6 19C8 19D1 19D2 13B5 16C8 16D3 12A7 12B7 12C2 19D3 13D5 MAKE_BASE=TRUE 5B2 5D4 7B5 7B6 7D5 8C7 55A4 65A2 67D6 67D8 9B7 11B3 11C5 19C8 19D1 19D2 19D5 19D6 19D7 21C1 24C3 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 19D3 13D5 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 MAKE_BASE=TRUE 65A2 67D6 67D8 24D3 25C4 25D3 34B8 34C6 34C8 21C1 24C3 24D3 25C4 25D3 34B8 34C6 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D3 14C6 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 MAKE_BASE=TRUE 7D5 19D6 19D7 7B5 34C6 34C8 55A4 65A2 67D6 67D8 34C8 55A4 5B2 21C1 24C3 24D3 25C4 25D3 34B8 19D3 14C6 5D4 19C8 19D1 19D2 19D5 19D6 19D7 MAKE_BASE=TRUE 7B6 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 67D8 19D5 19D6 19D7 21C1 24C3 24D3 25C4 19D3 14C6 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 MAKE_BASE=TRUE 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 67D6 65A2 55A4 25D3 34B8 34C6 34C8 19D3 14C6 PP1V05_S0 Power Interface These are the power signals that leave the NB "block" Rail Totals: 2310mA Max? IN IN IN IN IN PP1V8_S3 IN D IN IN IN IN IN 3200mA Max IN IN IN NC_NB_XOR_LVDS_A34 Max Max Max Max Max 13D5 19D4 NC_NB_XOR_LVDS_A34 14C6 19D4 NC_NB_XOR_LVDS_A35 14C6 19D4 (MCH H/V SYNC 2.5V PWR) NC_NB_XOR_LVDS_D27 14C6 19D4 GND NC_NB_XOR_LVDS_D28 14C6 19D4 GND NO_TEST=TRUE NC_NB_XOR_LVDS_D28 MAKE_BASE=TRUE NO_TEST=TRUE 19D3 14B6 TP_SDVO_CTRLCLK TP_SDVO_CTRLCLK 19D3 14B6 TP_SDVO_CTRLDATA 14B6 19D4 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 67C8 67C6 67B6 62A7 19D7 19D6 19D5 19D1 19C5 19C4 (MCH TVDAC DEDICATED PWR 1.5V) PP1V5_S0_NB 14B6 19D4 PP1V5_S0_NB LVDS_IBG 13D5 (MCH TVDAC DIGITAL QUIET 1.5V PWR) MAKE_BASE=TRUE 13B5 19D6 R1990 1.5K PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB ?mA Max 40mA Max (MCH TV OUT CHANNEL A 3.3V PWR) 1% 1/16W MF-LF 2 402 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 D 19D7 62A7 67B6 67C6 19B8 19C1 19C4 19C5 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19D1 19D2 19D5 19D6 67C8 PP1V5_S0_NB 1 70mA Max 60mA Max 2mA Max 19D7 62A7 67B6 67C6 19B8 19C1 19C4 19C5 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19D1 19D2 19D5 19D6 67C8 TP_SDVO_CTRLDATA 13B5 19D6 TP_CRT_DDC_DATA 3200mA Max 67D8 25C4 25D3 34B8 34C6 19C8 19D2 19D5 19D6 12A7 12B7 12C2 13B5 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 16C8 16D3 17D3 17D6 19D7 21C1 24C3 24D3 34C8 55A4 65A2 67D6 PP1V05_S0 NO_TEST=TRUE NC_NB_XOR_LVDS_D27 TP_CRT_DDC_CLK TP_CRT_DDC_DATA (MCH CRTDAC ANALOG 2.5V PWR) PP1V05_S0 TP_LVDS_CLKCTLB MAKE_BASE=TRUE TP_CRT_DDC_CLK 67D8 21C1 19D7 19D6 19D5 19D1 19C8 17D6 17D3 16D3 7B6 7B5 5D4 5B2 13D5 19D4 16C8 13B5 12C2 12B7 12A7 11C5 11B3 9B7 8C7 7D5 67D6 65A2 55A4 34C8 34C6 34B8 25D3 25C4 24D3 24C3 1 NO_TEST=TRUE NC_NB_XOR_LVDS_A35 1500mA Max ?mA 100mA 24mA 150mA 1900mA TP_LVDS_CLKCTLA TP_LVDS_CLKCTLB GND GND 19D6 19D7 62A7 67B6 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 62A7 67B6 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D2 19D5 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D5 13B5 19D6 19D7 19D5 MAKE_BASE=TRUE 67C6 67C8 19D2 19C1 67C8 5D4 19D5 13B5 19D6 19D7 62A7 67B6 62A7 67B6 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 67C6 MAKE_BASE=TRUE 19D2 19D5 19C4 19C5 19D1 67C6 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 62A7 19D6 19D6 19D7 19C1 19C4 19C5 19D1 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 67C8 67C6 19D2 19D5 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 13C5 5D4 19D7 67B6 62A7 19D7 19D5 19D2 19D1 19C5 19C4 67B6 82D3 67B6 82C5 67C8 67A6 67A8 82D3 63D1 66B5 19D7 63D1 66B5 67A6 67A8 67B6 82C5 19C5 19D7 19C5 19A6 19A8 19A8 17D6 19A4 19A6 5D4 17C6 19A4 82C6 82D5 17D6 66B5 66B6 17C6 57B6 58C4 5D4 26D1 27C3 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 24C3 24D3 25A4 25B4 25B8 25C4 25C6 25D3 25D8 26B4 23B3 23D5 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 24B3 24B5 26B6 26B8 33D8 34A8 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 PP3V3_S0 PP3V3_S0 IN 40mA Max? Max Max? Max Max ?mA Max GND PP2V5_S0 PP2V5_S0 IN 132mA Max 1500mA 10mA 800mA ?mA PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB IN 3674mA Max 25C4 25D3 34B8 34C6 34C8 55A4 65A2 67D6 17D3 17D6 19C8 19D1 19D2 19D5 19D6 19D7 67D8 12C2 21C1 24C3 24D3 19D7 21C1 5B2 67D8 19D1 19D2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 16D3 17D3 13B5 16C8 16D3 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 17D6 19C8 19D5 19D6 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 65A2 67D6 5B2 5D4 7B5 16D3 17D3 17D6 19C8 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 19D1 19D2 19D5 19D6 19D7 21C1 24C3 24D3 25C4 25D3 34B8 34C6 19C1 34C8 55A4 5D4 62A7 67B6 67C6 67C8 65A2 67D6 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 67D8 19C4 19C5 19D1 19D2 19D5 19D6 19D7 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 IN TP_LVDS_CLKCTLA PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 2 3 4 5 19D7 62A7 67B6 67C6 19B8 19C1 19C4 19C5 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19D1 19D2 19D5 19D6 67C8 PP1V5_S0_NB GND (MCH TV OUT CHANNEL B 3.3V PWR) 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 GND 19D7 62A7 67B6 67C6 19B8 19C1 19C4 19C5 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19D1 19D2 19D5 19D6 67C8 PP1V5_S0_NB (MCH TV OUT CHANNEL C 3.3V PWR) 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 19D7 62A7 67B6 67C6 19B8 19C1 19C4 19C5 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19D1 19D2 19D5 19D6 67C8 PP1V5_S0_NB (MCH TV DAC BAND GAP 3.3V PWR) 19D7 62A7 67B6 67C6 19B8 19C1 19C4 19C5 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19D1 19D2 19D5 19D6 67C8 PP1V5_S0_NB 55A4 25D3 21C1 19D2 17D3 12C2 11B3 7B5 5D4 8C7 7D5 12A7 16C8 19C8 19D6 24D3 34C6 67D6 67D8 34C8 25C4 19D7 19D1 16D3 12B7 9B7 5B2 7B6 11C5 13B5 17D6 19D5 24C3 34B8 65A2 GND PP1V05_S0 GMCH CORE PWR 1.05V BYPASS 1500mA Max CRITICAL 1 1 C1900 470uF C 3 67D8 34B8 25D3 25C4 19D5 19D2 19D1 13B5 12C2 12B7 7D5 7B6 7B5 5D4 11C5 11B3 9B7 17D6 17D3 16D3 24C3 21C1 19D7 65A2 55A4 34C8 67D6 24D3 19C8 12A7 5B2 8C7 16C8 19D6 34C6 20% 2 2.5V TANT D2T 2 C1902 1 C1903 1 1 C1905 0.22uF 0.22uF 10% 6.3V CERM 402 20% 6.3V X5R 402 20% 6.3V X5R 402 2 2 2 1 C1965 2 82D5 82C6 82B3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5 65B3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 49C4 49B5 40B6 36D6 34A8 33D8 33D3 33C7 29A6 27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 21C3 20B4 20A4 19C7 17C6 14D6 14C7 10C5 5D4 25B4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 28A6 27D8 27D5 54D4 54B5 52D3 66B1 82A4 (SHARE C0940 470UF) 2 C1906 1uF 20% 6.3V X5R 603 800mA Max 1 1 10uF 20% 6.3V X5R 603 MCH VTT BYPASS (MCH FSB 1.05V PWR) PP1V05_S0 C1904 10uF 1 C1966 1 C1907 0.22uF 2 20% 6.3V X5R 402 C MCH VCC_HV BYPASS (MCH HV BUFFER 3.3V PWR) 57B6 29A3 25B8 5A4 21D3 27D3 49C7 65D6 79D3 MCH VCCA_3GBG BYPASS (MCH PCIE/DMI BAND GAP 2.5V PWR) PP3V3_S0 40mA Max 19D7 19A8 19A6 19A4 17D6 17C6 5D4 82D3 82C5 67B6 67A8 67A6 66B5 63D1 C1967 C1914 2.2uF 0.22uF 10uF 20% 6.3V CERM 603 20% 6.3V CERM1 603 20% 6.3V X5R 402 2 Layout Note: Place in cavity 1 1 20% 6.3V X5R 603 2 2 B 1 0603 1 1 2 2 22UF 20% 6.3V CERM 805 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V 2 1 1 22UF 20% 6.3V CERM 805 C1950 1 2 2 1uF 10% 6.3V CERM 402 2 2 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V 1 0.01uF 10% 16V CERM 402 1 C1952 10uF 2 2 1 C1972 17D6 Layout Note: 10uF caps should be close to MCH on opposite side. 10uF 2 20% 6.3V X5R 603 B 1500mA Max GMCH VCCA_3GPLL FILTER (3GIO PLL 1.5V PWR) L1975 19D2 19D1 13C5 5D4 17C6 19C5 19C4 19C1 19B8 19B5 19A5 17C6 17B6 16D1 13D2 67C8 67C6 67B6 62A7 19D7 19D6 19D5 GMCH VCCA_DPLLA FILTER (CRT/TVOUT PLL 1.5V PWR) PP1V5_S0_NB_VCCA_DPLLA 17C6 0 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V 2 R1975 1.0UH-220MA-0.12-OHM PP1V5_S0_NB 1 2 2 20% 6.3V X5R 603 0 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V 2 5% 1/16W MF-LF NO STUFF 402 C1953 1 1 0.1uF 20% 10V CERM 402 MCH VCC_TXLVDS BYPASS (MCH LVDS TRANSMITTER 2.5V PWR) 82D3 82C5 67B6 67A8 17C6 17D6 17C6 5D4 67A6 66B5 63D1 19D7 19C5 19A8 19A4 50MA MAX PP2V5_S0 60MA MAX 20% 6.3V CERM 603 2 20% 10V CERM 402 MCH VCCD_LVDS BYPASS (MCH LVDS DIGITAL 1.5V PWR) 62A7 19D7 19D6 19D5 19D2 19D1 19C5 19C4 19C1 16D1 13D2 13C5 5D4 19B8 19B5 17C6 17B6 67C8 67C6 67B6 1 1 4.7UF C1954 0.1uF 2 17D6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V 2 1% 1/16W MF-LF 402 C1975 1 1 2 2 10uF 20% 6.3V X5R 603 C1976 0.1uF 20% 10V CERM 402 GND Layout Note: Route to caps, then GND 34B2 C1990 1 PP1V5_S0_NB_VCCA_3GPLL 0.51 PP1V5_S0_NB_3GPLL_F MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=1.5V 50MA MAX GMCH VCCA_DPLLB FILTER (LVDS PLL 1.5V PWR) PP1V5_S0_NB_VCCA_DPLLB R1954 PP1V5_S0_NB_DPLL TPS73115_NR C1951 20% 6.3V X5R 603 Layout Note: 3GPLL 10uF cap should be placed in cavity 5% 1/16W MF-LF 402 1 10uF 20% 2.5V POLY CASE-B2 1500mA Max 20% 10V CERM 402 1 5 4 C1971 220UF 0.1uF CRITICAL OUT NR/FB GND 1 C1970 C1937 NO STUFF 1 IN 3 EN 2 0805 R1953 SOT23-5 Layout Note: Place L and C close to MCH 45mA Max C1936 TPS73115 PP1V5_S0_NB_VCC3G MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V 2 20% 10V CERM 402 GMCH VCCA_MPLL FILTER (MCH MEMORY PLL 1.5V PWR) PP1V5_S0_NB_VCCA_MPLL 0603 PP2V5_S0 1 0.1uF FERR-120-OHM-0.2A A 2 GMCH VCC3G FILTER (PCI-E/DMI ANALOG 1.5V PWR) 1 C1935 L1936 U1900 2 91nH PP1V5_S0_NB 17C6 45mA Max C1934 82D3 67A8 63D1 19A6 17C6 5D4 19A4 17D6 19D7 19C5 67A6 66B5 82C5 67B6 20% 10V CERM 402 L1970 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V 2 1 0.1uF 20% 10V CERM 402 20% 10V CERM 402 1 C1918 0.1uF 1210 GMCH VCCA_HPLL FILTER (HOST PLL 1.5V PWR) PP1V5_S0_NB_VCCA_HPLL L1934 100mA Max C1916 1 Layout Note: Place on the edge FERR-120-OHM-0.2A PP1V5_S0_NB PP1V5_S0_NB 1900mA Max C1915 0.1uF 67C8 67C6 67B6 62A7 19D7 19D2 19D1 19C5 19C4 19C1 19B8 19B5 19A5 17C6 17B6 13C5 5D4 16D1 13D2 19D6 19D5 19D6 19D5 19D2 19D1 19C5 17B6 16D1 13D2 13C5 5D4 19C4 19C1 19B5 19A5 17C6 67C8 67C6 67B6 62A7 19D7 67C8 67C6 67B6 62A7 19D7 19D6 19A5 17C6 17B6 16D1 13D2 13C5 5D4 19D5 19D2 19D1 19C5 19C1 19B8 19B5 PP2V5_S0 2mA Max 4.7uF 2 GMCH VCCAUX FILTER (MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V) C1991 0.1uF 2 2 20% 10V CERM 402 PP1V5_S0_NB NB (GM) Decoupling MCH VCCA_LVDS BYPASS (MCH LVDS ANALOG 2.5V PWR) 82D3 82C5 67B6 67A8 67A6 66B5 63D1 19D7 17D6 17C6 5D4 19C5 19A8 19A6 SYNC_MASTER=M57_MLB_MG 20MA MAX SYNC_DATE=08/08/2006 NOTICE OF PROPRIETARY PROPERTY PP2V5_S0 10MA MAX C1992 1 1 10uF 20% 6.3V X5R 603 2 2 C1993 C1994 0.1uF 0.01UF 20% 10V CERM 402 20% 16V CERM 402 1 1 2 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING C1995 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 0.1uF 20% 10V CERM 402 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART GND SIZE Layout Note: Route to caps, then GND APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 19 1 87 A 8 6 7 3 4 5 2 1 Internal pull-ups 00 01 10 11 NB_CFG<13:12> NB_CFG<3> RESERVED NB_CFG<4> RESERVED D = = = = Partial Clock Gating Disable XOR Mode Enabled All-Z Mode Enabled Normal Operation NB_CFG<14> RESERVED NB_CFG<15> RESERVED D NB_CFG<5> 14C6 Internal pull-up NBCFG_DMI_X2 1 NB_CFG<5> High = DMIx4 DMI x2 Select Low R2075 2.2K = DMIx2 2 5% 1/16W MF-LF 402 PROBABLY NOT NEEDED NB_CFG<16> 14C6 C Internal pull-up NB_CFG<6> RESERVED FSB Dynamic ODT R2085 High = Enabled 2.2K Low 5% 1/16W MF-LF 402 = Disabled 2 NB_CFG<7> 14C6 Internal pull-up NO STUFF 1 NB_CFG<7> High = Mobile CPU CPU Strap Low R2077 2.2K = RESERVED 2 5% 1/16W MF-LF 402 NB_CFG<17> RESERVED PP3V3_S0 NBCFG_VCC_1V5 1 NB_CFG<18> NB_CFG<8> C NBCFG_DYN_ODT_DISABLE 1 NB_CFG<16> RESERVED VCC Select = 1.05V 2 5% 1/16W MF-LF 402 NB_CFG<18> 14C6 B R2058 2.2K High = 1.5V Low 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 82C6 82D5 B Internal pull-down NB_CFG<9> 14C6 Internal pull-up PP3V3_S0 NBCFG_PEG_REVERSE 1 NB_CFG<9> PCIE Graphics Lane Reversal NBCFG_DMI_REVERSE 1 R2079 High = Normal 2.2K NB_CFG<19> High = Reversed Low 5% 1/16W MF-LF 402 DMI Lane Reversal Low = Reversed 2 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 82C6 82D5 R2059 2.2K = Normal 2 5% 1/16W MF-LF 402 NB_CFG<19> 14C6 Internal pull-down PP3V3_S0 945 External Design Spec says reserved 1 NB_CFG<10> RESERVED NB_CFG<20> High = Both active PCIe Backward Interop. Mode Low 14B6 = Only SDVO or PCIe x1 66B5 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 27D3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 25B8 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 82B3 82C6 82D5 NBCFG_SDVO_AND_PCIE R2060 2.2K 2 5% 1/16W MF-LF 402 NB_CFG<20> Internal pull-down PROBABLY NOT NEEDED NB Config Straps A SYNC_MASTER=M59_MLB NB_CFG<11> RESERVED SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 20 1 87 A 6 7 PP3V3_G3C_SB_RTC_D 2 R2105 NOTE: ENABLE INTERNAL 1.05V SUSPEND REG 402 MF-LF 1/16W 1% 1 R2194 1 D 10K U2100 26D4 5B4 IN 26D4 SB_RTC_RST_L AA3 SB_SM_INTRUDER_L IN NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L RTCRST* Y5 INTRUDER* SB_INTVRMEN W4 INTVRMEN TP_SB_XOR_W1 TP_SB_XOR_Y1 TP_SB_XOR_Y2 TP_SB_XOR_W3 W1 EE_CS Y1 EE_SHCLK Y2 EE_DOUT W3 (INT PU) EE_DIN TP_SB_XOR_V3 V3 ICH7-M SB LAD0 LAD1 LAD2 LAD3 BGA (1 OF 6) LPC OUT AB1 RTCX1 AB2 RTCX2 RTC 26C8 SB_RTC_X1 SB_RTC_X2 LDRQ0* LDRQ1*/GPIO23 LFRAME* A20GATE A20M* AA6 AB5 AC4 Y6 53C5 AC3 AA5 AB3 60C6 53C4 51D7 5D2 60C6 51C7 LPC_AD<0> LPC_AD<1> LPC_AD<2> 5C2 LPC_AD<3> IO IO NOTE: LAD<0-3> HAVE INTERNAL 20K PU IO IO TP_SB_DRQ0_L LVDS_MUX_SEL_GPU IO 60C6 53C4 51C7 5C2 AE22 AH28 LPC_FRAME_L NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU NOSTUFF OUT SB_A20GATE CPU_A20M_L 87C6 7C8 C 87B4 48B3 5C1 OUT 87B4 48B3 5C1 OUT 87B4 48B3 5C1 OUT 87B4 48B3 5C1 IN ACZ_BITCLK ACZ_SYNC ACZ_RST_L ACZ_SDATAIN<0> R2195 R2198 1 1 R2197 1 U3 TP_SB_XOR_U5 TP_SB_XOR_V4 TP_SB_XOR_T5 U5 LAN_RXD0 V4 LAN_RXD1 (WEAK T5 LAN_RXD2 LAN_RSTSYNC 2 3987B4 SB_ACZ_BITCLK 3987B4 SB_ACZ_SYNC U1 ACZ_BIT_CLK R6 ACZ_SYNC 2 3987B4 SB_ACZ_RST_L R5 ACZ_RST* T2 ACZ_SDIN0 T3 20K PD ACZ_SDIN1 T1 20K PD ACZ_SDIN2 2 TP_SB_ACZ_SDIN1 TP_SB_ACZ_SDIN2 FERR* INT PU) GPIO49/CPUPWRGD U7 LAN_TXD0 V6 LAN_TXD1 V7 LAN_TXD2 TP_SB_XOR_U7 TP_SB_XOR_V6 TP_SB_XOR_V7 TP1/DPRSTP* TP2/DPSLP* CPU 5% 1/16W MF-LF 402 TP_SB_XOR_U3 IGNNE* INIT3_3V* INIT* INTR RCIN* AC-97/ AZALIA NOTE: POR IS SMC WILL PUT LAN INT’F INTO RESET STATE TO SAVE PWR. INTEL CONFIRMS OK TO LEAVE PINS AS NC CPUSPL* LAN (WEAK INT PD) NMI SMI* STPCLK* 20K PD 87B4 48B3 5C1 OUT ACZ_SDATAOUT R2196 1 3987B4 SB_ACZ_SDATAOUT 2 T4 THRMTRIP* ACZ_SDOUT 1 NOTE: PULLED UP PER INTEL OUT 36A5 36A4 OUT 36A5 36A4 OUT 81A7 IN 81A7 81B7 81B7 34C5 34C3 33B4 5A7 IN 34C5 34C3 33B4 5A7 IN IN OUT OUT IN 36A5 36A4 21B6 IN 36C5 OUT 36C4 OUT 36C4 NOTE: DDREQ HAS INTERNAL 11.5K PD SATA_C_D2R_N SATA_C_D2R_P SATA_C_R2D_C_N SATA_C_R2D_C_P AF7 SATA_2RXN AE7 SATA_2RXP AG6 SATA_2TXN AH6 SATA_2TXP SB_CLK100M_SATA_N SB_CLK100M_SATA_P 36A5 36A4 21B6 B AF3 SATA_0RXN AE3 SATA_0RXP AG2 SATA_0TXN AH2 SATA_0TXP OUT 36C4 IN 36C5 IN 36C5 IN DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 IDE IN TP_SATA_A_D2RN TP_SATA_A_D2RP TP_SATA_A_R2DN TP_SATA_A_R2DP SATA 36A5 36A4 IN AF1 SATA_CLKN AE1 SATA_CLKP SATA_RBIAS SATA_RBIAS AH10 SATARBIASN AG10 SATARBIASP IDE_PDIOR_L IDE_PDIOW_L IDE_PDDACK_L IDE_IRQ14 IDE_PDIORDY IDE_PDDREQ AF15 AH15 AF16 AH16 AG16 AE15 TP_CPU_CPUSLP_L 61C7 AF24 7B3 5C4 CPU_DPRSTP_L AH25 87C6 7B3 5B4 CPU_DPSLP_L 5B4 2.2K 2 5% 1/16W MF-LF 402 OUT 1 R2199 R2110 10K 54.9 5% 1/16W MF-LF 2 402 MF-LF 402 1/16W 1% AG22 AG21 AF22 AF25 7C8 87C6 7B3 5B4 CPU_IGNNE_L FWH_INIT_L 87C6 7D6 CPU_INIT_L 87C6 7C8 CPU_INTR 87C6 7C8 53C5 52D5 52D3 51D5 5C2 AG23 CPU_NMI CPU_SMI_L 87C6 7C8 87C6 7C8 87C6 7C8 5C4 CPU_STPCLK_L CPU_FERR_L IN OUT OUT OUT OUT NOSTUFF OUT R2100 NOTE: KEYBOARD CONTROLLER RESET CPU CPU_RCIN_L AH24 AF23 AH22 CPU_PWRGD NOTE: R2110=56 IN CV. CHANGED TO 54.9 FOR BOM CONSOLIDATION OUT AG26 AG24 19D2 19D5 19D6 19D7 21C1 24C3 24D3 25C4 25D3 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 34B8 34C6 34C8 55A4 65A2 67D6 67D8 PP1V05_S0 OUT NOTE: RISING-EDGE TRIGGERED AT CPU 1 0 2 19D2 19D5 19D6 19D7 21C1 24C3 24D3 25C4 25D3 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 34B8 34C6 34C8 55A4 65A2 67D6 67D8 PP1V05_S0 51C7 SMC_RCIN_L NOTE: R2108=56 IN CV. CHANGED TO 54.9 FOR 2 BOM CONSOLIDATION IN MF-LF 402 1/16W 5% R2108 54.9 OUT R2107 OUT AF26 5B4 CPU_THERMTRIP_R 1 24.9 2 1 MF-LF 402 1/16W 1% 52C1 14B6 7C6 C LAYOUT NOTE: R2108 TO BE < 2 IN OF R2107 W/O STUB PM_THRMTRIP_L IN MF-LF 402 1/16W 1% TP_SB_SATALED_L AF18 SATALED* 36A5 36A4 AG27 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 27D3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 25B8 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 82D5 PP3V3_S0 R2101 (INT PU) LAN_CLK D LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE 5% 1/16W MF-LF 2 402 OMIT IN 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 27D3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 25B8 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 82D5 PP3V3_S0 332K 26C8 1 2 26D4 26D3 25A4 24B3 2 3 4 5 1 8 DIOR* (HSTROBE) DIOW* (STOP) DDACK* IDEIRQ IORDY (DSTROBE) DA0 DA1 DA2 DCS1* DCS3* DDREQ AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15 AH17 AE17 AF17 AE16 AD16 IDE_PDD<0> IDE_PDD<1> IDE_PDD<2> 36C5 IDE_PDD<3> 36C5 IDE_PDD<4> 36C5 IDE_PDD<5> 36C5 IDE_PDD<6> 36C5 IDE_PDD<7> 36D4 IDE_PDD<8> 36C4 IDE_PDD<9> 36C4 IDE_PDD<10> 36C4 IDE_PDD<11> 36C4 IDE_PDD<12> 36C4 IDE_PDD<13> 36C4 IDE_PDD<14> 36C4 IDE_PDD<15> 36C5 IO 36C5 IO 36C5 IO IDE_PDA<0> 36C4 IDE_PDA<1> 36C5 IDE_PDA<2> 36C4 36C5 36C4 IDE_PDCS1_L IDE_PDCS3_L LAYOUT NOTE: R2107 TO BE < 2 IN OF SB IO IO IO IO IO NOTE: DD<7> HAS INTERNAL 11.5K PD IO IO IO IO IO IO IO IO B OUT OUT OUT OUT OUT NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S AC ’07 A ACZ_BIT_CLK SB: 1 OF 4 INTEL HIGH DEFINITION AUDIO SYNC_MASTER=M59_MLB INTERNAL 20K PD ENABLED WHEN ACZ_RST# SYNC_DATE=09/15/2006 INTERNAL 20K PD ONLY ENABLED IN S3COLD NOTICE OF PROPRIETARY PROPERTY - LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR NONE - BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED ACZ_SDIN[0-2] INTERNAL 20K PD INTERNAL 20K PD ACZ_SDOUT INTERNAL 20K PD ENABLED DURING RESET AND WHEN INTERNAL 20K PD ENABLED WHEN - LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR - LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART - BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED - BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED SIZE ACZ_SYNC INTERNAL 20K PD APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 21 1 87 A 8 6 7 2 3 4 5 1 79D5 67D5 67D3 67C3 66C5 65D8 24B3 24A5 23D8 23D4 23D1 23B7 23A7 22C6 11B5 5D4 65D2 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 PP3V3_S5 R2200 R2250 10K 10K 5% 1/16W MF-LF 2 402 5% 1/16W MF-LF 2 402 R2255 10K 5% 1/16W MF-LF 2 402 OMIT USB_G_OC_PU USB_E_OC_PU 1 R2223 1R2222 1R2226 1 R2251 10K 5% 1/16W MF-LF 2 402 10K 10K 10K 5% 1/16W MF-LF 2 402 5% 1/16W MF-LF 2 402 5% 1/16W MF-LF 2 402 U2100 39D5 IN 39D5 IN 39C5 39C5 47C5 22C4 6D3 6D2 6D1 22C4 6D3 6D1 D 48C3 22C4 6D3 6D1 5C1 22C4 6C3 6C1 52B3 48C3 22C4 6C3 6C1 5C1 22C4 22C4 6D5 48C3 22C4 6C3 6C1 5C1 RTUSB_OC_L UNUSED_USB_B_OC_L LTUSB_OC_L UNUSED_USB_D_OC_L EXCARD_OC_L OUT OUT 50C6 50C5 50C3 48C6 5B1 IN 50C6 50C5 50C3 48C6 5B1 IN 50C3 50C3 OUT OUT 50B6 50B5 50B3 48B6 5B1 IN 50C6 50C5 50C3 48B6 5B1 IN SB_GPIO29 SB_GPIO30 LT2USB_OC_L 50C3 OUT 50C3 OUT 50B6 50B3 IN 50B6 50B3 50B6 50B3 50B6 50B3 79D5 67D5 67D3 67C3 66C5 65D8 24B3 24A5 23D8 23D4 23D1 23B7 23A7 22D8 11B5 5D4 65D2 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 PP3V3_S5 2 IN IN 10K MF-LF 1/16W 402 5% C 56C7 51D5 IO 56C7 51B5 IO 51D5 IO 56C1 51D5 IO 56C1 51D5 IO 50B6 50B3 R2206 R2207 10K MF-LF 1/16W 402 5% 1 50A6 50A3 10K MF-LF 1/16W 402 5% 1 50B6 50B3 50B6 50B3 1 OUT 50B6 50B3 2 NOSTUFF R2205 OUT 50B6 50B3 50B6 50B3 2 IN 50B6 50B3 OUT OUT IN IN OUT OUT ICH7-M SB PCIE_A_D2R_N PCIE_A_D2R_P PCIE_A_R2D_C_N PCIE_A_R2D_C_P F26 PERN1 F25 PERP1 E28 PETN1 E27 PETP1 PCIE_MINI_D2R_N PCIE_MINI_D2R_P PCIE_B_R2D_C_N PCIE_B_R2D_C_P H26 PERN2 H25 PERP2 G28 PETN2 G27 PETP2 Y26 DMI1RXN Y25 DMI1RXP W28 DMI1TXN W27 DMI1TXP PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_C_R2D_C_N PCIE_C_R2D_C_P K26 PERN3 K25 PERP3 J28 PETN3 J27 PETP3 AB26 DMI2RXN AB25 DMI2RXP AA28 DMI2TXN AA27 DMI2TXP TP_PCIE_D_D2RN TP_PCIE_D_D2RP TP_PCIE_D_R2DN TP_PCIE_D_R2DP M26 PERN4 M25 PERP4 L28 PETN4 L27 PETP4 TP_PCIE_E_D2RN TP_PCIE_E_D2RP TP_PCIE_E_R2DN TP_PCIE_E_R2DP P26 PERN5 P25 PERP5 N28 PETN5 N27 PETP5 TP_PCIE_F_D2RN TP_PCIE_F_D2RP TP_PCIE_F_R2DN TP_PCIE_F_R2DP T25 PERN6 T24 PERP6 R28 PETN6 R27 PETP6 BGA (3 OF 6) SPI_SI SPI_SO P5 SPI_MOSI P2 SPI_MISO 48C3 52B3 48C3 D3 C4 D5 D4 E5 C3 A2 B3 RTUSB_OC_L 22D8 6D3 6D1 UNUSED_USB_B_OC_L 22D8 6D3 6D1 5C1 LTUSB_OC_L 22D8 6C3 6C1 UNUSED_USB_D_OC_L 22D8 6C3 6C1 5C1 EXCARD_OC_L 22D8 SB_GPIO29 22D8 6D5 SB_GPIO30 48C3 22D8 6C3 6C1 5C1 LT2USB_OC_L DMI_N2S_N<0> DMI_N2S_P<0> DMI_S2N_N<0> 14B4 DMI_S2N_P<0> 14B4 5A7 14B4 5A7 14B4 DMI_N2S_N<1> DMI_N2S_P<1> 14B4 DMI_S2N_N<1> 14B4 DMI_S2N_P<1> 14B4 5A7 14B4 5A7 DMI_N2S_N<2> DMI_N2S_P<2> DMI_S2N_N<2> 14B4 DMI_S2N_P<2> 14B4 AD25 DMI3RXN AD24 DMI3RXP AC28 DMI3TXN AC27 DMI3TXP PD) PD) OC0* OC1* OC2* OC3* OC4* OC5*/GPIO29 OC6*/GPIO30 OC7*/GPIO31 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3 D2 USBRBIAS* D1 USBRBIAS IN IN OUT OUT IN D IN OUT OUT IN 14B4 IN 14B4 OUT DMI_N2S_N<3> DMI_N2S_P<3> 14B4 DMI_S2N_N<3> 14B4 DMI_S2N_P<3> 14B4 14B4 34C5 34C3 33B4 34C5 34C3 33B4 OUT IN IN OUT OUT SB_CLK100M_DMI_N SB_CLK100M_DMI_P IN PP1V5_S0_SB_VCC1_5_B 1 DMI_IRCOMP_R PP3V3_S0 OMIT B E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6 37C6 IO 37C6 IO PCI_AD<0> PCI_AD<1> PCI_AD<2> PCI_AD<3> PCI_AD<4> PCI_AD<5> PCI_AD<6> PCI_AD<7> PCI_AD<8> PCI_AD<9> PCI_AD<10> PCI_AD<11> PCI_AD<12> PCI_AD<13> PCI_AD<14> PCI_AD<15> PCI_AD<16> PCI_AD<17> PCI_AD<18> PCI_AD<19> PCI_AD<20> PCI_AD<21> PCI_AD<22> PCI_AD<23> PCI_AD<24> PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29> PCI_AD<30> PCI_AD<31> 37D3 26D2 IO PCI_FRAME_L F16 FRAME* 26D2 IO 26D2 IO 26D2 IO 37D6 IO 37D6 IO 37D6 IO 37D6 IO 37D6 IO 37D6 IO 37D6 IO 37D6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 6C5 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO 37C6 IO AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 U2100 ICH7-M SB BGA (2 OF 6) REQ0* GNT0* REQ1* GNT1* REQ2* GNT2* REQ3* GNT3* REQ4*/GPIO22 GNT4*/GPIO48 GPIO1/REQ5* GPIO17/GNT5* D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8 1 26D2 PCI_REQ0_L TP_PCI_GNT0_L 26D2 PCI_REQ1_L TP_PCI_GNT1_L 26D2 PCI_REQ2_L TP_PCI_GNT2_L PCI_REQ3_L PCI_GNT3_L TP_PCI_GNT4_L R2298 IN OUT IN 24.9 2 USB2_RT_N IO EXTERNAL 0 USB2_RT_P IO USB_TRACKPAD_N IO TRACKPAD (GEYSER) 81C4 6D3 6D2 6D1 USB_TRACKPAD_P IO USB2_LT_N IO EXTERNAL 1 USB2_LT_P IO USB2_CAMERA_N IO CAMERA NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD USB2_CAMERA_P IO USB2_EXCARD_N IO EXTERNAL 2 USB2_EXCARD_P IO USB_HUB_N IO IR USB_HUB_P IO USB_BT_N IO BLUETOOTH USB_BT_P IO USB2_LT2_N IO USB2_LT2_P IO PCI IRDY* PAR PCICLK DEVSEL* PERR* PLOCK* SERR* STOP* TRDY* PLTRST* PCIRST* (INT 20K PU) PME* B15 C12 D12 C15 R2204 USB_RBIAS_PN 1 22.6 2 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 27D3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 25B8 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 82D5 R2299 10K 5% 1/16W MF-LF 2 402 5% 1/16W MF-LF 2 402 OUT IN OUT IN OUT SB_CRT_TVOUT_MUX IO PCI_PME_FW_L IN NOTE: FWH_WP_L NOT USED B OUT 53B4 51C7 5C2 A7 37D3 26D2 PCI_IRDY_L E10 37B6 PCI_PAR A9 34D6 PCI_CLK_SB A12 37D3 26D2 PCI_DEVSEL_L C9 37D3 26D2 PCI_PERR_L E11 26D2 PCI_LOCK_L 37C3 B10 26D2 PCI_SERR_L 37C3 F15 26D2 PCI_STOP_L 37C3 F14 26D2 PCI_TRDY_L 82A4 79A8 26C3 26C1 26B1 26A4 14B7 6C7 6C6 5C4 C26 B18 B19 PLT_RST_L PCI_RST_L TP_PCI_PME_L 37C2 5B4 1 IO IO R2211 5% 1/16W MF-LF 2 402 (STRAPPED TO TOP-BLOCK SWAP MODE IE SB INVERTS A16 FOR ALL CYCLES TARGETING FWH BIOS SPACE) IO OUT 1K NO STUFF - DEFAULT STUFF - A16 SWAP OVERRIDE IO BOOT_LPC_SPI_L IO IO IN SB BOOT BIOS SELECT IO IO IO STRAP GNT5# R2211 GNT4# R2210 IO LPC (DEFAULT) 11 UNSTUFF IO PCI 10 UNSTUFF STUFF OUT SPI 01 STUFF UNSTUFF IO UNSTUFF OUT NOTE: GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K) SB: 2 OF 4 NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L A 37D3 26D2 IO INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L TP_SB_XOR_AE5 TP_SB_XOR_AD5 TP_SB_XOR_AG4 TP_SB_XOR_AH4 TP_SB_XOR_AD9 A3 PIRQA* B4 PIRQB* C5 PIRQC* B5 PIRQD* AE5 AD5 AG4 AH4 AD9 RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 VOLTAGE=0V 1 10K 37D3 PCI_C_BE_L<0> PCI_C_BE_L<1> PCI_C_BE_L<2> PCI_C_BE_L<3> INT I/F GPIO2/PIRQE* GPIO3/PIRQF* GPIO4/PIRQG* GPIO5/PIRQH* MISC RSVD5 RSVD6 NOTE: CHANGE SYMBOL RSVD7 TO RSVD[1-9] RSVD8 MCH_SYNC* G8 F7 F8 G7 SB_GPIO2 IO 26C2 SB_GPIO3 IO 80A1 SB_DVI_HPD IO 36C7 ODD_PWR_EN_L IO AE9 TP_SB_XOR_AE9 AG8 TP_SB_XOR_AG8 AH8 TP_SB_XOR_AH8 F21 TP_SB_RSVD9 AH20 NB_SB_SYNC_L NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE (AKA TP3, INTERNAL 20K PU) IN DRAWING NUMBER D SHT NONE 6 5 4 3 2 REV. 051-7164 SCALE 7 A 26D2 APPLE COMPUTER INC. 8 C LAYOUT NOTE: PLACE R2204 < 1/2 IN FROM SB BOM NOTE FOR PD ON PCI_GNT3_L: 37C6 C/BE0* 37B6 C/BE1* 37B6 C/BE2* 37B6 C/BE3* LAYOUT NOTE: PLACE R2203 < 1/2 IN FROM SB 1/16W MF-LF 1% 402 47B5 6D3 6D2 6D1 47B5 6D3 6D2 6D1 81C4 6D3 6D2 6D1 1% 1/16W MF-LF 402 NOTE: GNT[0-3]# HAVE INT 20K PU ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H 24D5 25B6 IN R2203 C25 DMI_ZCOMP D25 DMI_IRCOMP R2 SPI_CLK (INT P6 SPI_CS* P1 SPI_ARB (INT IN V26 DMI0RXN V25 DMI0RXP U28 DMI0TXN U27 DMI0TXP AE28 DMI_CLKN AE27 DMI_CLKP SPI_SCLK SPI_CE_L SPI_ARB 47C5 22D8 6D3 6D2 6D1 DMI 5% 1/16W MF-LF 2 402 USB_D_OC_PU 1 USB 10K 1 PCI-EXP R2225 1 SPI USB_C_OC_PU 1 06004 OF 22 1 87 8 6 7 2 3 4 5 1 NOTE FOR R2323 (DEF=NOSTUFF) STRAPPING @ PWROK RISING: SB WILL DISABLE TCO TIMER SYSTEM REBOOT FEATURE 79D3 82A4 82B3 82C6 82D5 62A6 65B3 65D6 66B1 66B5 66B6 67A3 67B3 67C3 67C5 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 27D3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 24B3 24B5 24C3 24D3 25A4 25B4 25B8 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 60C7 60D4 61A5 61D8 66C5 67C3 67D3 67D5 79D5 71D2 79A8 5D4 11B5 22C6 22D8 23A7 23B7 23D1 23D8 24A5 24B3 24C3 25B6 25C8 25D2 26C5 56D4 63D8 65C8 65D1 65D2 65D8 PP3V3_S0 PP3V3_S5 8 1 1 R2318 D 67D3 25C8 11B5 5D4 23D4 23D1 65D1 65C8 PP3V3_S5 7 6 5 1 NOSTUFF 1 NOSTUFF 1 NO_REBOOT_MODE R2397 R2327 R2326 10K 8.2K 10K 8.2K 10K 10K 1/16W 2 402 MF-LF 5% 1/16W 2 402 MF-LF 5% 1/16W 2 402 MF-LF 5% 1/16W 2 402 MF-LF 5% 1/16W 2 402 MF-LF 5% 1/16W 2 MF-LF 402 5% RP2300 R2323 5% 1/16W SM-LF 1K 1/16W 2 402 MF-LF 5% 1 2 3 U2100 1 33B6 29A6 28A6 27D8 27D7 27D6 27C6 27B6 5B1 81C3 48B3 46B6 33B6 29A6 28A6 27D8 27D7 27D6 27C6 27B6 5B1 81C3 48B3 46B6 1 R2320 R2317 R2316 1K 10K 10K 10K 1/16W 2 402 MF-LF 5% 1/16W 2 402 MF-LF 5% 1/16W 2 402 MF-LF 5% IO IO C22 B22 SMB_LINK_ALERT_L A26 B25 SMLINK<0> A25 SMLINK<1> SMBUS_SB_SCL SMBUS_SB_SDA NOT USED PM_RI_L SB_SPKR 51B7 26C5 5A2 IN PM_SUS_STAT_L PM_SYSRST_L 14B6 IN PM_BMBUSY_L 60C6 53B5 52A2 51C5 5C2 OUT SMB_ALERT_L A28 AB18 B23 NOTE: RESERVED FOR FUTURE OUT 33C4 5B4 OUT A21 23A6 23A6 IO IN IO 51B7 IN GPU_D3COLD_RESET_L TP_AZ_DOCK_RST_L PCIE_WAKE_L INT_SERIRQ PM_THRM_L IN VR_PWRGD_CK410 IO IN 51B7 IN GPIO11/SMBALERT* GPIO26 SMC_RUNTIME_SCI_L SMC_EXTSMI_L TP_SB_GPIO6 SUSCLK PWROK GPIO16/DPRSLPVR TP0/BATLOW* (INT 20K PU) PWRBTN* LAN_RST* GPIO32/CLKRUN* RSMRST* AC19 GPIO33/AZ_DOCK_EN* U2 GPIO34/AZ_DOCK_RST* AD22 AC1 CLK14 B2 CLK48 VRMPWRGD AC21 GPIO6 AC18 GPIO7 E21 GPIO8 C20 GPIO 34A6 34C7 6C6 66C8 66B6 65B8 51C5 43C8 B24 SLP_S3* D23 SLP_S4* F22 SLP_S5* F20 WAKE* AH21 SERIRQ AF20 THRM* 26B8 5A4 51B7 AF19 SB_GPIO21 GPIO21/SATA0GP AH18 SB_GPIO19 GPIO19/SATA1GP AH19 GPIO36/SATA2GP AE19 SB_GPIO37 GPIO37/SATA3GP GPIO0/BM_BUSY* B21 GPIO27 E23 GPIO28 AG18 26A4 48C3 39C6 5B1 BIOS_REC FWH_MFG_MODE PM_CLKRUN_L C 60C6 53C5 51C7 5C2 PD) AC20 GPIO18/STPPCI* AF21 GPIO20/STPCPU* PM_STPPCI_L PM_STPCPU_L SB_GPIO26 60C6 53C4 51C5 5C2 RI* D 8.2K 10K SATA GPIO (4 OF 6) SMBCLK SMBDATA LINKALERT* SMLINK0 SMLINK1 A19 SPKR (INT WEAK A27 SUS_STAT* A22 SYS_RST* 1 R2319 R2343 CLKS 1 R2398 1/16W 2 402 MF-LF 5% 33C4 5B4 1 ICH7-M SB 4 BGA 1 65D8 66C5 67C3 67D3 67D5 24C3 25B6 25C8 25D2 26C5 5D4 11B5 22C6 22D8 23A7 23B7 23D4 23D8 24A5 24B3 56D4 63D8 65C8 65D1 65D2 79D5 PP3V3_S5 OMIT 10K SMB 67D5 25D2 22C6 24A5 65D2 R2396 1 SYS GPIO PWR MNGT 79D5 63D8 56D4 26C5 23B7 23A7 22D8 25B6 24C3 24B3 67C3 66C5 65D8 R2395 1 6C7 5B4 66C6 55C3 42A8 39C8 32B3 5C4 100 1 100 1 2 2 R2302 R2303 100 1 2 R2305 36B5 SB_CLK14P3M_TIMER SB_CLK48M_USBCTLR PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L AA4 26A6 5B4 PM_SB_PWROK IN AC22 87C6 61C8 14B7 5B4 PM_DPRSLPVR OUT C23 C19 SATA_C_DET_L 5% 2 1/16W MF-LF 402 IN IN IN TP_SB_SUS_CLK OUT 52A2 51C5 5C4 C21 1/16W 2 402 MF-LF 5% OUT OUT OUT NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN PM_PWRBTN_L IN PM_LAN_ENABLE IN 51D7 51D7 5B4 Y4 51B7 PM_BATLOW_L IN 51D7 5B4 PM_RSMRST_L IN NOTE: SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F IN RESET STATE TO SAVE PWR R2399 GPIO9 GPIO10 DEF=GPI GPIO12 GPIO13 DEF=GPI GPIO14 GPIO15 GPIO24 GPIO25 OD GPIO35 66B7 66B6 GPIO38 DEF=GPI GPIO39 E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20 SMS_INT_L SMC_SB_NMI 40A3 LAN_ENERGY_DET 52B2 51B5 51D7 1 IN 2 C 100K 5% 1/16W 402 MF-LF IN IN 51D5 SMC_WAKE_SCI_L IN IDE_RESET_L OUT SV_SET_UP 5C2 23B6 53B5 CRB_SV_DET 23B6 TP_SB_GPIO25_DO_NOT_USE 33B4 SB_CLK100M_SATA_OE_L OUT SB_GPUVCORE_DISABLE_L IO 23A3 SATA_C_PWR_EN_L OUT 36D5 NOTE FOR GPIO25: - HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS - CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP) 79D5 67D5 67D3 67C3 66C5 65D8 24B3 24A5 23D8 23D4 23D1 23A7 22D8 22C6 11B5 5D4 65D2 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 PP3V3_S5 B 1 NOSTUFF R2306 R2308 10K 10K 1/16W 2 402 MF-LF 5% 1/16W 2 402 MF-LF 5% B NOTE: SV_SET_UP IS LINDACARD DETECT HI = PRESENT LO = NOT PRESENT 1 SV_SET_UP CRB_SV_DET PP3V3_S0 5C2 23C3 53B5 23C3 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 27D3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23D5 24B3 24B5 24C3 24D3 25A4 25B4 25B8 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 82D5 1 R2388 10K 1 LAYOUT NOTE: R2307 R2309 PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE 79D5 67D5 67D3 67C3 66C5 65D8 24B3 24A5 23D8 23D4 23D1 23B7 22D8 22C6 11B5 5D4 65D2 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 5% 1/16W MF-LF 2 402 1 NOSTUFF 10K 1/16W 402 2 MF-LF 5% 0 1/16W 402 2 MF-LF 5% 23B3 SATA_C_PWR_EN_L PP3V3_S5 1 A SB: 3 OF 4 1 R2313 R2310 10K 10K 1/16W 402 2 MF-LF 5% 1/16W 402 2 MF-LF 5% 1 NOSTUFF 1 NOSTUFF SYNC_MASTER=M57_MLB_MG SYNC_DATE=08/08/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING FWH_MFG_MODE 23C5 BIOS_REC 23C5 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE R2314 0 1/16W 2 402 MF-LF 5% II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART R2311 10K SIZE 1/16W 2 402 MF-LF 5% D APPLE COMPUTER INC. DRAWING NUMBER SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 23 1 87 A 8 6 7 D C B A 1 OMIT OMIT A4 A23 N24 P24 R18 U14 V27 AA24 AB27 AD11 B1 D10 F4 G18 J1 L24 M17 N14 N17 N18 N25 N26 P3 P4 P12 P13 P14 P15 P16 P17 P27 P28 R1 R11 R12 R13 R14 R15 R16 R17 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB28 AC2 AC5 AC9 AC11 AD1 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 2 3 4 5 25D7 AD3 AD4 AD7 AD8 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 B8 B11 B14 B17 B20 B26 B28 C2 C6 C27 D13 D18 D21 D24 E1 E2 E4 E8 E15 F3 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J2 J5 J24 J25 J26 K24 K27 K28 L13 L15 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N15 N16 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27 U2100 ICH7-M SB BGA (6 OF 6) VSS 25C7 25B6 22C1 PP5V_S0_SB_V5REF PP5V_S5_SB_V5REF_SUS PP1V5_S0_SB_VCC1_5_B 82D5 82C6 82B3 82A4 66B6 66B5 66B1 65D6 65B3 62A6 61D8 61A5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 33D3 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 60D4 60C7 58C7 58C4 57B6 54D4 54B5 79D3 79A8 71D2 67C5 67C3 67B3 67A3 PP3V3_S0 PP1V5_S0_SB_VCCDMIPLL PP1V5_S0 25B6 25B2 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 67C8 67C6 66C5 62C1 62A8 48B6 25D6 25C8 25C6 25C2 G10 AD17 F6 AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28 D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 R25 R26 T22 T23 T26 T27 T28 U22 U23 V22 V23 W22 W23 Y22 Y23 B27 AG28 AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5 PP1V5_S0 AD2 PP3V3_S0 AH11 25B6 25B2 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 67C8 67C6 66C5 62C1 62A8 48B6 25D6 25C8 25C6 25C2 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 33D3 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 61A5 60D4 60C7 58C7 58C4 57B6 54D4 54B5 67A3 66B6 66B5 66B1 65D6 65B3 62A6 61D8 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 82D5 82C6 PP1V5_S0 AB10 AB9 AC10 AD10 AE10 AF10 AF9 AG9 AH9 V5REF V5REF_SUS BGA CORE VCC1_05 VCC PAUX VCCLAN_3_3 VCCA3GP V_CPU_IO IDE VCC3_3 PCI VCC3_3 VCCRTC D NOTE FOR VCCLAN_3_3: S3 IF INTERNAL LAN IS USED S0 OR S3 IF NOT PP3V3_S0 PP3V3_S5 AE23 AE26 AH26 PP1V05_S0 AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19 PP3V3_S0 W5 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 27D3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 25A4 25B4 25B8 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 82B3 82D5 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 40B6 49B5 25D3 25D8 26B4 26B6 26B8 26D1 27C3 27D3 27D5 25B4 25B8 24B5 24C3 22B5 23B3 20A4 20B4 14D6 17C6 5A4 5D4 10C5 14C7 19C6 19C7 21C3 21D3 19D2 19D5 19D6 23D5 24B3 16C8 16D3 17D3 24D3 25A4 11B3 11C5 12A7 25C4 25C6 5B2 5D4 7B5 7B6 27D8 28A6 7D5 8C7 9B7 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 60C7 12B7 12C2 13B5 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 17D6 19C8 19D1 82C6 82D5 67D6 67D8 19D7 21C1 24D3 25C4 25D3 34B8 34C6 34C8 55A4 65A2 PP3V3_S0 U6 R7 A5 B13 B16 B7 C10 D15 F9 G11 G12 G16 19D7 21C1 24C3 25C4 25D3 34B8 34C6 34C8 55A4 65A2 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 67D6 67D8 PP1V05_S0 NOTE: VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V DEPENDING ON VIO OF AZALIA INTERFACE CODEC IC’S CONSIDERED SO FAR ARE 3.3V 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 82C6 82D5 C PP3V3_S0 PP3V3_G3C_SB_RTC_D 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 27D3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B5 24C3 24D3 25A4 25B4 25B8 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 82D5 21D6 25A4 26D3 26D4 65D8 66C5 67C3 67D3 67D5 79D5 5D4 11B5 22C6 22D8 23A7 23B7 23D1 23D4 23D8 24A5 24B3 24C3 25B6 25C8 25D2 26C5 56D4 63D8 65C8 65D1 65D2 PP3V3_S5 A24 C24 D19 VCCSUS3_3 D22 G19 VCC3_3 VCCDMIPLL ARX VCC1_5_A USB VCCSUS3_3 VCCSATAPLL K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7 B 65D8 66C5 67C3 67D3 67D5 79D5 5D4 11B5 22C6 22D8 23A7 23B7 23D1 23D4 23D8 24A5 24B3 24C3 25B6 25C8 25D2 26C5 56D4 63D8 65C8 65D1 65D2 PP3V3_S5 VCC3_3 AB17 VCC1_5_A AC17 VCC1_5_A ATX VCC1_5_A T7 F17 G17 PP1V5_S0 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 62A8 62C1 66C5 67C6 67C8 AB8 VCC1_5_A AC8 K7 C1 VCCSAUS1_5 CHANGE SYMBOL TO 1.05 AA2 Y7 V5 V1 W2 W7 P7 PP1V5_S0 VOLTAGE GENERATED INTERNALLY SO NO CONNECT HERE VCC3_3/VCCHDA VCCSUS3_3/VCCSUSHDA VCC1_5_B E3 VCCSUS3_3 25B6 25B2 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 67C8 67C6 66C5 62C1 62A8 48B6 25D6 25C8 25C6 25C2 ICH7-M SB (5 OF 6) PP3V3_S5 79D5 67D5 67D3 67C3 66C5 65D8 24B3 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 65D2 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 U2100 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 C28 G20 VOLTAGE GENERATED INTERNALLY SO NO CONNECT HERE VCCUSBPLL VCCLAN1_5 CHANGE SYMBOL TO 1.05 USB CORE VCC1_5_A A1 H6 H7 J6 J7 SB: 4 OF 4 SYNC_MASTER=M59_MLB PP1V5_S0 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 62A8 62C1 66C5 67C6 67C8 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. 0 SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY 0 DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 24 1 87 A 8 81B3 80A1 71A6 67B1 66B5 61D7 58C4 55A8 36D6 5D4 5D2 31C5 53C4 57B5 58C7 62B1 67A1 67B3 79B8 80B5 79D3 79A8 71D2 67C5 67B3 67A3 66B6 66B5 65D6 65B3 62A6 61D8 60D4 60C7 58C7 58C4 54D4 54B5 52D3 49C7 49B5 40B6 36D6 34A8 33D3 33C7 29A6 29A3 27D8 27D5 27D3 27C3 26B8 26B6 26B4 25D3 25C4 25B8 25B4 25A4 23B3 22B5 21D3 21C3 14D6 14C7 10C5 5D4 5A4 20B4 20A4 19C7 19C6 17C6 24D3 24C3 24B5 24B3 23D5 26D1 25C6 28A6 33D8 49C4 57B6 61A5 2 66B1 67C3 82A4 82B3 82C6 82D5 6 7 ICH VCC1_5_A/ARX BYPASS (ICH LOGIC&IO[ARX] 1.5V PWR) 5D1 PP1V5_S0 PP3V3_S0 1 R2502 100 10% 2 16V X5R 402 BAT54DW SOT-363 ICH V5REF BYPASS (ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT) PP5V_S0_SB_V5REF 24D5 6 D 1 0.1UF D2502 NC 1/16W MF-LF 402 5% C2511 1 5 C2503 1 C2518 0.1UF 10% 16V 2 X5R 402 0 1 C2502 1 C2517 0.1UF PLACEMENT NOTE: PLACE CAP UNDER SB NEAR PINS V1, V5, W2, OR W7 PP5V_S5 2 1 D2502 BAT54DW NC 1 SOT-363 1 ICH V5REF_SUS BYPASS (ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC) PP5V_S5_SB_V5REF_SUS 24D5 10% 16V 2 X5R 402 PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AH11 0 0.1UF C C2513 0.1UF VOLTAGE=5V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM C2504 10% 16V 2 X5R 402 PLACEMENT NOTE: PLACE C2504 < 2.54MM OF PIN F6 OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY C2519 0.1UF C2514 1UF 10% 6.3V 2 CERM 402 PP1V5_S0 PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AG9 ICH VCC3_3/VCCHDA BYPASS (ICH INTEL HDA CORE 3.3V PWR) 25B4 5D4 5A4 PP3V3_S0 2 0.1UF 10% 2 16V X5R 402 20% 2 2.5V POLY CASE-B2 0.1UF 10% 2 16V X5R 402 1 C2521 0.1UF 10% 16V 2 X5R 402 C ICH VCC1_5A BYPASS (ICH LOGIC&IO 1.5V PWR) 1 PP3V3_S5 C2520 0.1UF PLACEMENT NOTE: PLACE C2500 & C2505-07 < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY NEAR PINS D28, T28, AD28 0.1UF 10% 2 16V X5R 402 C2510 1 PLACEMENT NOTE: PLACE CAPS NEAR PINS AB8 AND AC8 OF SB 1 C2522 0.1UF 0.1UF 10% 16V 2 X5R 402 1 C2524 4.7UF 10% 2 16V X5R 402 20% 2 6.3V CERM 603 ICH USB CORE/VCC1_5_A BYPASS (ICH USB CORE 1.5V PWR) 0 PP1V5_S0 25C2 25B6 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 67C8 67C6 66C5 62C1 62A8 48B6 25D6 25C8 25C6 ICH IDE/VCC3_3 BYPASS (ICH IDE I/O 3.3V PWR) PP3V3_S0 82D5 82C6 82B3 82A4 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5 65D6 65B3 62A6 61D8 61A5 60D4 60C7 58C7 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6 27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 58C4 66B1 79D3 PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PINS AA7 ... AG19 PP1V5_S0 1 C2515 10% 16V 2 X5R 402 PLACEMENT NOTE: PLACE C2509 NEAR PIN B27 OF SB PLACEMENT NOTE: PLACE C2520 NEAR PIN C1 OF SB 1 PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PINS A1 ... J7 1 C2512 0.1UF B 10% 16V 2 X5R 402 C2525 0.1UF 10% 16V 2 X5R 402 25C2 25B2 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 67C8 67C6 66C5 62C1 62A8 48B6 25D6 25C8 25C6 C2509 PP1V5_S0 0 0.1UF 1 10% 2 16V X5R 402 PLACEMENT NOTE: PLACE C2520 NEAR PIN E3 OF SB ICH VCCUSBPLL BYPASS (ICH USB PLL 1.5V PWR) ICH VCC3_3 BYPASS (ICH IO BUFFER 3.3V PWR) PP3V3_S0 C2523 0.1UF 1 B 79A8 71D2 67C5 65D6 65B3 62A6 57B6 54D4 54B5 34A8 33D8 33D3 27D3 27C3 26D1 25C4 25B4 25A4 22B5 21D3 21C3 14C7 10C5 5D4 5A4 20B4 20A4 19C7 19C6 24D3 24C3 24B5 24B3 26B8 26B6 26B4 25D8 33C7 29A6 29A3 28A6 52D3 49C7 49C4 49B5 61D8 61A5 60D4 60C7 67C3 67B3 67A3 66B6 82D5 82C6 82B3 25C6 25B6 25B2 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 67C8 67C6 66C5 62C1 62A8 48B6 25D6 25C8 ICH V_CPU_IO BYPASS (ICH CPU I/O 1.05V PWR) 24D3 24C3 21C1 19D7 19D6 8C7 7D5 7B6 7B5 5D4 5B2 PP1V05_S0 ICH VCCSUS3_3 BYPASS (ICH SUSPEND 3.3V PWR) 10% 16V 2 X5R 402 0 10% 16V 2 X5R 402 0 67D3 67C3 66C5 65D8 25D2 25C8 24C3 24B3 23A7 22D8 22C6 11B5 5D4 24A5 23D8 23D4 23D1 23B7 65D2 65D1 65C8 63D8 56D4 26C5 79D5 67D5 0.1UF 10% 2 16V X5R 402 C2532 0.1UF 10% 16V 2 X5R 402 22C1 24D5 C2500 1 C2505 1 C2506 1 C2507 220UF 79D3 66B1 58C4 36D6 27D5 25C6 23B3 14D6 D 0 PP1V5_S0_SB_VCC1_5_B 1 1 0.1UF 82D5 67A3 66B6 66B5 66B1 65D6 65B3 62A6 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25B8 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 54B5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 PLACEMENT NOTE: PLACE NEAR PINS AE23, AE26 & AH26 OF SB SM-3 C2533 1 55A4 34C8 34C6 34B8 25D3 12B7 12A7 11C5 11B3 9B7 19D5 19D2 19D1 19C8 17D6 17D3 16D3 16C8 13B5 12C2 67D8 67D6 65A2 ICH VCCA3GP(VCC1_5_B BYPASS (ICH IO,LOGIC 1.5V PWR) VOLTAGE=1.5V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM 82A4 66B5 58C7 40B6 27D8 25D3 23D5 17C6 10% 2 16V X5R 402 PP3V3_S5 0 0 1 0.1UF 10% 2 16V X5R 402 PLACEMENT NOTE: PLACE CAPS NEAR PINS K3 ... N7 OF SB PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN U6 1 L2500 C2534 1 0.1UF 79D5 67D5 67D3 67C3 66C5 65D8 65D2 24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 24B3 25B6 25B2 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 67C8 67C6 66C5 62C1 62A8 48B6 25D6 25C8 25C2 100-OHM-EMI C2531 ICH USB/VCCSUS3_3 BYPASS (ICH SUSPEND USB 3.3V PWR) 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 58C4 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 79D3 82A4 82B3 82C6 82D5 10% 16V 2 X5R 402 ICH VCC1_5_A/ATX BYPASS (ICH LOGIC&IO[ATX] 1.5V PWR) PP1V5_S0 0 67C8 66C5 62A8 25D6 25C2 25B2 24B5 24A3 8B7 5D1 5D4 9B7 24A5 25A8 25B6 25C6 48B6 62C1 67C6 1 0 ICH VCC3_3 BYPASS (ICH IO BUFFER 3.3V PWR) PP3V3_S0 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 26D1 26B8 26B6 26B4 25D8 25D3 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 4 3 PLACEMENT NOTE: PLACE CAPS NEAR PINS A24 ... G19 AND P7 OF SB PLACEHOLDER FOR 270UF ICH VCC_PAUX/VCCLAN3_3 BYPASS 66B6 67A3 67B3 67C3 67C5 71D2 79A8 (ICH LAN I/F BUFFER 3.3V PWR) 66B5 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 25B8 25C4 25C6 25D8 26B4 26B6 26B8 26D1 27C3 27D3 PP3V3_S0 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 1 PP3V3_S5 2 PP3V3_S5 0 PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AD2 0 1/16W MF-LF 402 5% C2516 20% 2 2.5V POLY CASE-C2 62C1 62A8 48B6 25B6 25B2 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 25D6 25C8 25C6 25C2 67C8 67C6 66C5 67C3 66C5 65D8 65D2 25D2 25B6 24C3 24B3 23A7 22D8 22C6 11B5 5D4 24A5 23D8 23D4 23D1 23B7 65D1 65C8 63D8 56D4 26C5 79D5 67D5 67D3 10 79D5 67D5 67D3 67C3 66C5 65D8 65D2 24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 24B3 0 10% 2 16V X5R 402 R2501 ICH VCCSUS3_3 BYPASS (ICH SUSPEND 3.3V PWR) 19D7 21C1 24C3 24D3 25C4 34B8 34C6 34C8 55A4 65A2 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 67D6 67D8 330UF 10% 6.3V 2 CERM 402 ICH VCCSATAPLL BYPASS (ICH SATA PLL 1.5V PWR) PP1V5_S0 PLACEMENT NOTE: PLACE C2503 < 2.54MM OF PIN AD17 OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY 0 5D4 47C7 52B5 62A4 62B2 62B6 62C8 64C8 65B7 65D6 66B8 66D8 67B1 67C1 67C3 71D7 1 1UF 1 VOLTAGE=5V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM 0.1UF 10% 16V 2 X5R 402 ICH CORE/VCC1_05 BYPASS (ICH CORE 1.05V PWR) PP1V05_S0 PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AG5 2 3 4 PLACEMENT NOTE: PLACE CAPS AT EDGE OF SB 25B6 25B2 25A8 24B5 24A5 24A3 9B7 8B7 5D4 67C8 67C6 66C5 62C1 62A8 48B6 25D6 25C8 25C6 25C2 PP5V_S0 1 5 0 0 0 ICH PCI/VCC3_3 BYPASS (ICH PCI I/O 3.3V PWR) 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25B4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 82D5 82C6 82B3 0 PLACEMENT NOTE: DISTRIBUTE IN PCI SECTION OF SB NEAR PINS A5 ... G16 66B5 36D6 25B8 5A4 21C3 27D3 58C7 82A4 PP3V3_S0 1 C2526 0.1UF 10% 16V 2 X5R 402 1 C2527 0.1UF 1 C2528 0.1UF 10% 16V 2 X5R 402 10% 16V 2 X5R 402 0 67C8 67C6 66C5 62C1 62A8 48B6 24B5 24A5 24A3 9B7 8B7 5D4 5D1 25D6 25C8 25C6 25C2 25B6 25B2 SB: 4 OF 4 PP1V5_S0 A L2507 R2500 1 1 2 1/10W 5% MF-LF 603 ICH VCCDMIPLL BYPASS (ICH DMI PLL 1.5V PWR) PP1V5_S0_SB_VCCDMIPLL 0.28-OHM PP1V5_S0_SB_VCCDMIPLL_F VOLTAGE=1.5V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM 1 2 24B5 VOLTAGE=1.5V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM 1206 1 C2501 1 0.01UF ICH VCCRTC BYPASS (ICH RTC 3.3V PWR) PP3V3_G3C_SB_RTC_D 1 20% 2 6.3V X5R 603 PLACEMENT NOTE: PLACE CAPS NEAR PIN W5 OF SB C2530 0.1UF 10% 16V 2 X5R 402 1 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE C2529 II NOT TO REPRODUCE OR COPY IT 0.1UF 10% 16V 2 X5R 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE 0 APPLE COMPUTER INC. 0 DRAWING NUMBER D SHT NONE 7 6 5 4 3 2 REV. 051-7164 SCALE 8 A NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING C2508 10UF 10% 2 16V CERM 402 PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY 26D4 26D3 24B3 21D6 06004 OF 25 1 87 8 6 7 2 3 4 5 1 82D5 82C6 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 27C3 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 RTC Battery Connector 26D3 25A4 24B3 21D6 D2600 CRITICAL J2600 2 D 4 21D6 24B3 25A4 26D4 37D3 22A7 IO 37D3 22A6 IO SOT-363 81D4 69C8 52B7 52B5 52B1 51D4 51D3 51C2 47B5 35B7 27C3 5D2 69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52D7 1 PP3V42_G3H 6 1 NC R2607 1 PP3V3_G3C_SB_RTC_D BAT54DW BM02B-ACHKS-A-GAN-TF-LF M-RT-SM 3 PP3V3_G3C_SB_RTC_D MAKE_BASE=TRUE VOLTAGE=3.3V PPVBATT_G3C_RTC 1K 2 1 VOLTAGE=3.3V 2 PPVBATT_G3C_RTC_R 3 4 C2610 37C3 22A6 IO 1UF 37C3 22A6 IO 37C3 22A6 IO 10% 6.3V CERM 402 37D3 22A6 VOLTAGE=3.3V 5% 1/16W MF-LF 402 5 NC NC 2 NC NC 20K 1 518S0452 SB_RTC_RST_L 2 5% 1/16W MF-LF 402 NOTE: R2607 and D2600 form the doublefault protection for RTC battery. IO 22A6 IO 22B6 IN 22B6 IN 22B6 IN R2600 NC 1 1 C2605 1UF R2606 2 1M 2 OUT 5% 1/16W MF-LF 402 21D6 10% 6.3V CERM 402 37D3 22B6 6B5 6B3 SB_SM_INTRUDER_L OUT IO 37D3 22A6 IN 22A7 IO 22A7 IO 22A7 IO 37D3 22A7 IO 22A6 IO 22A6 IO 82B3 66B5 36D6 25B4 5A4 21C3 27D3 58C7 82A4 PCI_FRAME_L PCI_IRDY_L PCI_TRDY_L PCI_STOP_L PCI_SERR_L PCI_DEVSEL_L PCI_PERR_L PCI_LOCK_L R2623 R2624 R2625 R2626 R2627 R2628 R2630 R2629 PCI_REQ0_L PCI_REQ1_L PCI_REQ2_L PCI_REQ3_L R2632 R2631 R2633 R2634 INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L SB_GPIO2 SB_GPIO3 R2637 R2636 R2638 R2639 R2640 R2642 PP3V3_S0 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K D 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K Pullup on SB_GPIO4 removed as it now defaults low for use as DVI_HPD in muxed graphics solution. Platform Reset Connections SB RTC Crystal Circuit C 1 21D6 5% 1/16W MF-LF 402 ITP 2 2 Y2600 NC NC 1 32.768K SM-2 5% 50V CERM 402 3 4 CRITICAL 2 IN 1 PM_SYSRST_L MAKE_BASE=TRUE 5% 50V CERM 402 1 PLT_RST_L 100K PLT_RST_L Silk: "SYS RST" 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 65D6 65B3 62A6 61D8 61A5 60D4 60C7 58C7 82D5 82C6 82B3 82A4 66B1 34A8 25B4 5A4 21C3 27C3 58C4 79D3 R2681 MC74VHC1G08 SC70 4 37A7 1 3 1 PLT_RST_BUF_L 1 2 1 1 0 100 2 1 66B5 36D6 25B4 5A4 21C3 27D3 58C7 82A4 2 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 65D6 65B3 62A6 61D8 61A5 60D4 60C7 58C7 82D5 82C6 82B3 82A4 1 1 0.1UF 20% 10V CERM 402 4 R2611 66B1 34A8 25B4 5A4 21C3 27C3 58C4 79D3 PP3V3_S0 1.8K 2 2 VR_PWRGD_CK410 MC74VHC1G08 5 1 SC70 MAKE_BASE=TRUE IN OUT PM_SB_PWROK 4 0 2 ENET_RST_L 39C6 B 3 VR_PWRGOOD_DELAY IN ALL_SYS_PWRGD IN 26A4 23C5 GPU_D3COLD_RESET_L 1 1 GPU_D3COLD_RESET_L SC70 2 VR_PWRGD_CK410_L 2 PLT_RST_L PLTRST_D3COLD_L 4 1 3 1 5% 1/16W MF-LF 402 PEG_RESET_L 5C4 70A5 C2685 20% 10V CERM 402 1K 2 GPU_SIGNAL_ENABLE 26A1 26A2 80B2 82A7 R2688 GPU_SIGNAL_ENABLE 26A1 26A2 80B2 82A7 GPU_SIGNAL_ENABLE 5% 1/16W MF-LF 402 100K 0.1UF 2 82A7 80B2 26A1 1 MAKE_BASE=TRUE 2 R2622 10K 2 R2689 MC74VHC1G08 MAKE_BASE=TRUE 82A4 79A8 26C3 26C1 26B1 22A6 14B7 6C7 6C6 5C4 0 2 U2685 3 10K 5% 1/16W MF-LF 402 66B1 51D7 R2687 1 5% 1/16W MF-LF 402 5 U2601 2 R2612 1 D3Cold Reset for GPU 10K 5% 1/16W MF-LF 402 1 2 33A4 61C7 26A8 VR_PWRGD_CK410_L 5C4 60B7 Initial resistor values are based on CRB, but may change after characterization. R2686 1 5% 1/16W MF-LF 402 5 U2603 TPM_LRESET_L R2682 PP3V3_S0 C2607 SC70-5 5C4 51C7 5% 1/16W MF-LF 402 2 MC74VHC1G00 SMC_LRESET_L 5% 1/16W MF-LF 402 R2684 1 20% 10V CERM 402 OUT 2 5C2 53B4 Linda Card represents 3 loads R2683 PP3V3_S0 0.1UF 61C7 33A4 26A7 5% 1/16W MF-LF 402 DEBUG_RST_L 2 5% 1/16W MF-LF 402 C2611 OUT 100K 0.1UF 0 5% 1/16W MF-LF 402 R2680 C2680 20% 10V CERM 402 5C4 6C6 6C7 14B7 22A6 26A4 26C1 26C3 79A8 82A4 Hook to inverter PWM AND gate (except M59) This RST is used to mask a glitch output from the NB PWM output during reset. Buffered U2680 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 27C3 26D1 26B8 26B4 25D8 25D3 25C6 25C4 25B8 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 82D5 82C6 82B3 5C4 6C6 6C7 14B7 22A6 26A4 26B1 26C1 26C3 79A8 82A4 PLT_RST_L PP3V3_S0 2 B 5C4 6C6 6C7 14B7 22A6 26A4 26B1 26C1 26C3 79A8 82A4 100-ohm on NB page 5 67C5 57B6 27D8 24B5 5A4 20A4 25D3 36D6 65B3 LIO represents X loads (2?) 5% 1/16W MF-LF 402 OUT OMIT 5% 1/16W MF-LF 402 2 C 5C1 26C1 48C3 MAKE_BASE=TRUE 1 82D5 82C6 82B3 82A4 79D3 79A8 71D2 62A6 61D8 61A5 60D4 60C7 58C7 58C4 34A8 33D8 33D3 33C7 29A6 29A3 28A6 25C6 25C4 25B8 25B4 25A4 24D3 24C3 19C7 19C6 17C6 14D6 14C7 10C5 5D4 24B3 23D5 23B3 22B5 21D3 21C3 20B4 27D5 27D3 27C3 26D1 26B6 26B4 25D8 54D4 54B5 52D3 49C7 49C4 49B5 40B6 67C3 67B3 67A3 66B6 66B5 66B1 65D6 LIO_PLT_RESET_L 2 R2698 1 This part is never stuffed, it provides a set of pads on the board to short or to solder a reset button. 2 PLT_RST_L 0 MAKE_BASE=TRUE 2 2 5% 1/16W MF-LF 402 12pF 79A8 26C1 26B1 26A4 22A6 14B7 6C7 6C6 5C4 IN 82A4 1K XDP_DBRESET_L C2609 1 SB_RTC_X2 LIO_PLT_RESET_L 5C1 26C1 48C3 On M59 this RST is used for layout reasons R2685 10K R2696 5% 1/16W MF-LF 402 10M 5% 1/16W MF-LF 402 1 SB_RTC_X1_R 2 R2609 1 Unbuffered R2697 1 12pF 0 SB_RTC_X1 PP3V3_S5 C2608 R2610 21D6 79D5 67D5 67D3 67C3 66C5 65D8 24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 65D2 65D1 65C8 63D8 56D4 25D2 25C8 25B6 24C3 24B3 2 5% 1/16W MF-LF 402 1 C2689 0.001UF 2 1G00 used as small & cheap inverter 10% 50V CERM 402 SB Misc A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 26 1 87 A 8 6 7 ICH7-M SMBus Connections SMC "0" SMBus Connections 82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 49B5 40B6 36D6 34A8 33D8 33D3 33C7 29A6 25D8 25D3 25C6 25C4 25B8 25B4 25A4 24D3 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 20B4 29A3 28A6 27D5 27D3 27C3 26D1 26B8 26B6 26B4 60C7 58C7 58C4 57B6 54D4 54B5 52D3 49C7 49C4 PP3V3_S0 D SMBUS_SB_SCL 81C3 48B3 29A6 27D6 23D5 5B1 27C6 27B6 28A6 27D7 46B6 33B6 R2700 81C3 48B3 46B6 33B6 29A6 28A6 27D8 27D6 27C6 27B6 23D5 5B1 1 1 R2701 4.7K 4.7K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 2 SMC CY28445-5: U3301 (Write: 0xD2 Read: 0xD3) U5800 (MASTER) SMBUS_SB_SCL SMBUS_SB_SCL SMBUS_SB_SDA SMBUS_SB_SDA MAKE_BASE=TRUE 81C3 29A6 33B6 27D6 27D7 5B1 23D5 27B6 27C6 27D8 28A6 46B6 48B3 54C2 27D5 27D3 54B3 51C7 54C2 27D5 27D3 54B3 51C5 PP3V3_S0 R2750 Clock Chip MAKE_BASE=TRUE SMBUS_SB_SDA 82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 49B5 40B6 36D6 34A8 33D8 33D3 33C7 29A6 25D8 25D3 25C6 25C4 25B8 25B4 25A4 24D3 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 20B4 29A3 28A6 27D8 27D5 27C3 26D1 26B8 26B6 26B4 60C7 58C7 58C4 57B6 54D4 54B5 52D3 49C7 49C4 PP3V3_S0 U2100 (MASTER) SMBUS_SMC_0_S0_SCL 54C2 54B3 51C7 27D6 27D3 1 1 R2751 4.7K 4.7K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 2 SMBUS_SMC_0_S0_SCL GPU Temp SMC TMP401: U6150 (Write: 0x98 Read: 0x99) U5800 (MASTER) SMBUS_SMC_0_S0_SCL MAKE_BASE=TRUE 54C2 54B3 51C5 27D6 27D3 SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA MAKE_BASE=TRUE 54C2 54B3 51C7 27D6 27D3 27D5 54B3 27D6 27D3 27D5 51C5 54C2 R2760 51B5 27D1 10B3 49B5 27D2 SMBUS_SMC_B_S0_SCL 51B5 27D1 10B3 49B5 27D2 SMBUS_SMC_B_S0_SDA SO-DIMM "A" C2701 15pF 2 1 5% 50V CERM 402 2 SMBUS_SMC_0_S0_SCL SMBUS_SB_SCL SMBUS_SB_SDA 81C3 29A6 33B6 27D6 27D7 5B1 23D5 27B6 27C6 27D8 28A6 46B6 48B3 SMBUS_SMC_0_S0_SDA 1 R2761 4.7K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 2 CPU Temp TMP401: U1001 (Write: 0x98 Read: 0x99) SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SCL 49B5 51B5 10B3 27D1 27D2 27D3 SMBUS_SMC_B_S0_SDA 49B5 51B5 10B3 27D1 27D2 27D3 MAKE_BASE=TRUE SMBUS_SMC_B_S0_SDA 1 C2761 2 D Battery Chgr 15pF MAX6695: U6100 (Write: 0x30 Read: 0x31) 5% 50V CERM 402 1 4.7K MAKE_BASE=TRUE Remote Temps C2751 15pF J2800 (Write: 0xA0 Read: 0xA1) 51B5 49B5 27D3 27D1 10B3 51B5 49B5 27D3 27D1 10B3 NO STUFF 1 1 SMC "B" SMBus Connections 82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 49B5 40B6 36D6 34A8 33D8 33D3 33C7 29A6 25D8 25D3 25C6 25C4 25B8 25B4 25A4 24D3 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 20B4 29A3 28A6 27D8 27D3 27C3 26D1 26B8 26B6 26B4 60C7 58C7 58C4 57B6 54D4 54B5 52D3 49C7 49C4 ICH7-M 2 3 4 5 5% 50V CERM 402 TMP106: U5650 (Write: 0x92 Read: 0x93) 54B3 27D6 27D3 27D5 51C7 54C2 51B5 49B5 27D3 27D2 10B3 27D1 49B5 27D2 10B3 27D1 27D3 51B5 SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SO-DIMM "B" SMC "A" SMBus Connections J2900 (Write: 0xA4 Read: 0xA5) SMBUS_SB_SCL SMBUS_SB_SDA 81D4 69C8 69B8 69A8 68B8 67D5 52B1 51D4 51D3 51C2 47B5 35B7 26D6 5D2 67D3 66D2 66C8 66A8 53C4 52D7 52B7 52B5 PP3V3_S3 81C3 29A6 33B6 27D6 27D7 5B1 23D5 27B6 27C6 27D8 28A6 46B6 48B3 PP3V42_G3H R2770 1 SMC C U5800 (MASTER) USB Hub Trackpad I2C Connections: U4900 (See Table) U1 - Trackpad Controller (Write: 0x70 Read: 0x71) SMBUS_SB_SCL U2 - Keyboard Controller SMBUS_SB_SDA (Write: 0x72 Read: 0x73) SMC "Battery A" SMBus Connections NOTE: SMC RMT bus remains powered and may be active in S3 state 81D4 81A5 67C5 46C3 46B3 41C5 37D7 37D5 37C3 37A7 32C5 5D4 67C3 66C6 65D1 63B7 60C2 59C6 57D4 52B1 46D6 51B5 27C3 5B1 48B6 27C5 81C3 48B6 27B3 5B1 27C5 27C3 81C3 51B5 SMBUS_SMC_A_S3_SCL 33B6 28A6 27D7 27C6 48B3 5B1 23D5 27B6 46B6 27D6 27D8 29A6 81C3 81C3 51B5 48B6 27C6 27C3 5B1 81C3 51B5 48B6 27C6 27C3 27B3 5B1 SMBUS_SMC_A_S3_SDA 1 R2771 4.7K 4.7K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 2 Top-Case TMP275: J4900 (WRITE: 0X98 READ: 0X99) SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SCL MAKE_BASE=TRUE SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SDA MAKE_BASE=TRUE R2780 1 SMC 81C3 51B5 48B6 27C6 27C5 27C3 5B1 81C3 48B6 27C5 5B1 27B3 27C6 51B5 U5800 (MASTER) 68B2 27C1 5D1 51B5 27C2 SMBUS_SMC_BSA_SCL 68B2 27C1 5D1 51B5 27C2 SMBUS_SMC_BSA_SDA 68B2 51B5 27C3 27C1 5D1 68B2 51B5 27C3 27C1 5D1 1 R2781 3.3K 3.3K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 2 Battery J8250 (Write: 0x16 Read: 0x17) SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL 68B2 5D1 27C2 27C3 51B5 SMBUS_SMC_BSA_SDA 68B2 5D1 27C2 27C3 51B5 MAKE_BASE=TRUE SMBUS_SMC_BSA_SDA MAKE_BASE=TRUE C LIO/ALS Temp J5500 (See Table) M35B - TMP106 (Write: 0x92 Read: 0x93) SMBUS_SB_SCL ExpressCard Slot SMBUS_SB_SDA (Address determined by ARP) SMC "Battery B" SMBus Connections TMP106: J5500 (WRITE: 0X92 READ: 0X93) Left I/O Board Left I/O SMBus Connections: SMBUS_SMC_A_S3_SCL 33B6 28A6 27D7 27C6 48B3 5B1 23D5 27B6 46B6 27D6 27D8 29A6 81C3 SMBUS_SMC_A_S3_SDA 82D5 82C6 82B3 82A4 79D3 71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65B3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 36D6 34A8 33D8 33D3 33C7 29A6 29A3 28A6 25D3 25C6 25C4 25B8 25B4 25A4 24D3 24C3 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 65D624B5 24B3 23D5 23B3 22B5 21D3 21C3 20B4 79A827D8 27D5 27D3 26D1 26B8 26B6 26B4 25D8 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 PP3V3_S0 81C3 48B6 27C5 5B1 27C3 27C6 51B5 R2790 SMC USB_HUB - U4900 (Write: 0x58 Read: 0x59) Trackpad J4900 (See Table) SMBUS_SB_SCL SMBUS_SB_SDA 1 100K U5800 (MASTER) 51C5 27B2 SMBUS_SMC_BSB_SCL 51C5 27B3 51C7 27B2 SMBUS_SMC_BSB_SDA 51C7 27B3 1 R2791 100K 5% 1/16W MF-LF 402 2 5% 1/16W MF-LF 2 402 SMBUS_SMC_BSB_SCL MAKE_BASE=TRUE SMBUS_SMC_BSB_SDA MAKE_BASE=TRUE 33B6 28A6 27D7 27C6 48B3 5B1 23D5 27B6 46B6 27D6 27D8 29A6 81C3 B B M57 SMBUS CONNECTIONS A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 27 1 87 A 6 7 Page Notes 32B4 32B3 29D6 14C2 C2801 1 1 2.2uF 20% 6.3V CERM1 603 Signal aliases required by this page: - =I2C_SODIMMA_SCL - =I2C_SODIMMA_SDA C2800 0.1uF 2 2 5A MEM_A_DQ<14> 15C7 MEM_A_DQ<13> 15C7 20% 10V CERM 402 7A 9A 11A MEM_A_DQS_N<1> 15C5 MEM_A_DQS_P<1> 15C5 13A 15A BOM options provided by this page: (NONE) 15C7 15C7 17A MEM_A_DQ<10> MEM_A_DQ<11> 19A 21A NOTE: This page does not supply VREF. The reference voltage must be provided by another page. MEM_A_DQ<5> 15D7 MEM_A_DQ<4> 23A MEM_A_DQS_N<0> 15C5 MEM_A_DQS_P<0> 29A 15D7 25A 27A 15C5 31A 33A 35A MEM_A_DQ<6> 15D7 MEM_A_DQ<7> 15D7 37A 39A 41A 43A MEM_A_DQ<19> 15C7 MEM_A_DQ<18> 15C7 45A 47A 49A MEM_A_DQS_N<2> 15C5 MEM_A_DQS_P<2> 15C5 51A 53A 55A MEM_A_DQ<20> 15C7 MEM_A_DQ<16> 15C7 57A 59A 15C7 15C7 61A MEM_A_DQ<28> MEM_A_DQ<25> 63A 65A 67A 15C5 MEM_A_DM<3> NC 69A 71A C 15C7 "Expansion" (surface-mount) slot 15C7 73A MEM_A_DQ<27> MEM_A_DQ<30> 75A 77A 30D6 14C4 79A MEM_CKE<0> 81A NC 30B6 15D5 83A 85A MEM_A_BS<2> 87A 89A MEM_A_A<12> 15B5 MEM_A_A<9> 15B5 MEM_A_A<8> 30C6 15B5 30C6 30C6 91A 93A 95A 97A MEM_A_A<5> MEM_A_A<3> 15C5 MEM_A_A<1> 30C6 15B5 99A 30C6 15B5 30C6 101A 103A 105A MEM_A_A<10> 15D5 MEM_A_BS<0> 15B5 MEM_A_WE_L 30C6 15B5 30B6 30B6 107A 109A 111A 113A MEM_A_CAS_L 14C4 MEM_CS_L<1> 30B6 15D5 30D6 115A 117A 30C6 14C4 119A MEM_ODT<1> 121A 15B7 15B7 B 123A MEM_A_DQ<35> MEM_A_DQ<39> 125A 127A 129A MEM_A_DQS_N<4> 15C5 MEM_A_DQS_P<4> 15C5 131A 133A 135A MEM_A_DQ<37> 15C7 MEM_A_DQ<33> 15B7 137A 139A 141A MEM_A_DQ<60> 15B7 MEM_A_DQ<59> 15A7 143A 145A 15C5 147A MEM_A_DM<7> 149A 15B7 15A7 151A MEM_A_DQ<58> MEM_A_DQ<61> 153A 155A 15B7 15B7 157A MEM_A_DQ<43> MEM_A_DQ<45> 159A 161A NC 163A 165A 167A MEM_A_DQS_N<5> 15C5 MEM_A_DQS_P<5> 15C5 169A 171A 173A 15B7 MEM_A_DQ<41> 15B7 MEM_A_DQ<46> 175A 177A A 179A MEM_A_DQ<51> 15B7 MEM_A_DQ<50> 15B7 181A 183A 15C5 185A MEM_A_DM<6> 187A 82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 15B7 67B3 67A3 66B6 66B5 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 15B7 33D3 33C7 29A6 29A3 27D8 27D5 27D3 27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 46B6 33B6 29A6 27D8 27D7 27D6 27C6 27B6 23D5 81C3 189A MEM_A_DQ<53> MEM_A_DQ<48> PP3V3_S0 5B1 SMBUS_SB_SDA 48B3 5B1 SMBUS_SB_SCL 191A 193A 195A 197A 46B6 33B6 29A6 27D8 27D7 27D6 27C6 27B6 23D5 81C3 48B3 199A VREF VSS1 CRITICAL DQ1 VSS4 VSS0 DQ4 J2800 DQ0 DQ5 F-RT-SM-M9 DQS0* DQS0 VSS6 DQ2 DQ3 VSS8 PP1V8_S3 NC 201 1A MEMVREF_OUT 3A Power aliases required by this page: - =PP1V8_S3_MEM - =PPSPD_S0_MEM (2.5V - 3.3V) D 203 VSS2 DM0 VSS5 DQ6 DQ7 VSS7 DQ12 DQ13 VSS9 DM1 DQ8 DQ9 VSS10 VSS11 DQS1* DQS1 CK0 CK0* VSS12 VSS13 DQ10 DQ11 DQ14 DQ15 VSS14 VSS15 KEY VSS16 DQ16 VSS17 DQ20 DQ17 DQ21 VSS18 DQS2* VSS19 NC0 DQS2 DM2 VSS21 DQ18 VSS22 DQ22 DQ19 VSS23 DQ23 VSS24 DQ24 DQ28 DQ25 VSS25 DQ29 VSS26 DM3 DQS3* NC1 VSS27 DQS3 VSS28 DQ30 DQ26 DQ27 VSS29 CKE0 VDD0 DQ31 VSS30 NC/CKE1 VDD1 NC2 NC/A15 BA2 VDD2 NC/A14 VDD3 A12 A11 A9 A8 A7 A6 VDD4 VDD5 A5 A3 A4 A2 A1 VDD6 A0 VDD7 A10/AP BA1 BA0 WE* RAS* S0* VDD8 VDD9 CAS* NC/S1* ODT0 NC/A13 VDD10 VDD11 NC/ODT1 VSS31 NC3 VSS32 DQ32 DQ33 DQ36 DQ37 VSS33 VSS34 DQS4* DQS4 DM4 VSS35 VSS36 DQ38 DQ39 VSS37 DQ34 DQ35 VSS38 DQ44 DQ45 VSS39 DQ40 DQ41 VSS40 DM5 DQS5* DQS5 VSS41 VSS42 DQ42 DQ43 DQ46 DQ47 VSS43 VSS44 DQ48 DQ49 DQ52 DQ53 VSS45 VSS46 NC_TEST VSS47 CK1 CK1* DQS6* DQS6 VSS48 DM6 VSS49 VSS50 DQ50 DQ51 DQ54 DQ55 VSS51 VSS52 DQ56 DQ57 DQ60 DQ61 VSS53 VSS54 DM7 VSS55 DQS7* DQS7 DQ58 DQ59 VSS56 DQ62 VSS57 DQ63 VSS58 SA0 SDA SCL VDDSPD SA1 2 3 4 5 PP1V8_S3 29D6 29D3 29B2 28D3 28B2 19D7 16B6 14C2 5D4 5B2 67B8 67B6 64C1 64A6 37B2 32C6 31C5 DDR2-SODIMM-DUAL 8 2A 4A 6A MEM_A_DQ<8> MEM_A_DQ<12> 15C7 MEM_A_DM<1> 15D5 15C7 8A 10A 12A 14A MEM_A_DQ<15> MEM_A_DQ<9> 16A 15C7 15C7 18A 20A MEM_A_DQ<2> MEM_A_DQ<3> 22A 15D7 D 15D7 24A 26A MEM_A_DM<0> 15D5 28A 30A MEM_CLK_P<0> MEM_CLK_N<0> 32A 14D4 14D4 34A 36A MEM_A_DQ<1> MEM_A_DQ<0> 38A 15D7 15D7 40A 42A 44A MEM_A_DQ<23> MEM_A_DQ<22> 46A 15C7 15C7 48A 50A PM_EXTTS_L MEM_A_DM<2> 52A 14B7 29C3 51B7 52D3 52D5 15D5 54A 56A MEM_A_DQ<21> MEM_A_DQ<17> 58A 15C7 15C7 60A 62A MEM_A_DQ<29> MEM_A_DQ<24> 64A 15C7 15C7 66A 68A MEM_A_DQS_N<3> MEM_A_DQS_P<3> 70A 15C5 15C5 72A 74A MEM_A_DQ<26> MEM_A_DQ<31> 76A C 15C7 15C7 78A 80A MEM_CKE<1> 14C4 30D6 82A 84A NC_MEM_A_A<15> NC_MEM_A_A<14> 86A 6D7 6D7 88A 90A MEM_A_A<11> MEM_A_A<7> MEM_A_A<6> 92A 94A DDR2 Bypass Caps 15B5 30C6 15B5 30C6 (For return current) 15B5 30C6 96A PP1V8_S3 29D6 29D3 29B2 28D6 28D3 19D7 16B6 14C2 5D4 5B2 67B8 67B6 64C1 64A6 37B2 32C6 31C5 98A MEM_A_A<4> MEM_A_A<2> MEM_A_A<0> 100A 102A 15B5 30C6 15C5 30C6 1 15C5 30C6 8 7 6 5 204 C2808 1 C2809 104A 10UF 106A 2 20% 6.3V X5R 603 2 20% 6.3V X5R 603 1 C2810 1 C2811 MEM_A_BS<1> MEM_A_RAS_L MEM_CS_L<0> 108A 110A 15D5 30B6 15B5 30B6 10UF 14C4 30D6 112A 114A MEM_ODT<0> MEM_A_A<13> 116A 14C4 30C6 15B5 30C6 1 1UF 1UF 1UF 120A 2 10% 6.3V CERM 402 2 10% 6.3V CERM 402 2 10% 6.3V CERM 402 1 C2814 1 C2815 1 NC 122A 124A MEM_A_DQ<38> MEM_A_DQ<34> 126A 1 C2812 118A C2813 1UF 2 10% 6.3V CERM 402 1 C2817 15B7 15B7 B 128A 130A MEM_A_DM<4> 15C5 134A MEM_A_DQ<32> MEM_A_DQ<36> 136A C2816 1UF 1UF 1UF 1UF 2 10% 6.3V CERM 402 2 10% 6.3V CERM 402 2 10% 6.3V CERM 402 2 10% 6.3V CERM 402 1 C2818 1 C2819 1 1 C2821 132A 15C7 15B7 138A 140A MEM_A_DQ<57> MEM_A_DQ<63> 142A 15B7 15A7 144A 146A MEM_A_DQS_N<7> MEM_A_DQS_P<7> 148A 2 15C5 15C5 C2820 1UF 1UF 1UF 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 2 2 1UF 2 10% 6.3V CERM 402 150A 152A MEM_A_DQ<56> MEM_A_DQ<62> 154A 15B7 15A7 156A 158A MEM_A_DQ<40> MEM_A_DQ<42> 160A 15B7 15B7 162A 164A 166A MEM_CLK_P<1> MEM_CLK_N<1> 14D4 MEM_A_DM<5> 15C5 14D4 168A 170A 172A 174A MEM_A_DQ<47> MEM_A_DQ<44> 176A DDR2 SO-DIMM Connector A 15B7 15B7 178A SYNC_MASTER=M59_MLB 180A MEM_A_DQ<54> MEM_A_DQ<55> 182A 15B7 184A 186A MEM_A_DQS_N<6> MEM_A_DQS_P<6> 188A SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY 15B7 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING 15C5 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 15C5 190A II NOT TO REPRODUCE OR COPY IT 192A MEM_A_DQ<52> MEM_A_DQ<49> 194A III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 15B7 15B7 SIZE 196A 198A 200A APPLE COMPUTER INC. ADDR=0xA0(WR)/0xA1(RD) DRAWING NUMBER D NC SHT NONE 4 3 2 REV. 051-7164 SCALE 202 516S0471 1 5B2 5D4 14C2 16B6 19D7 28B2 28D6 29B2 29D3 29D6 31C5 32C6 37B2 64A6 64C1 67B6 67B8 06004 OF 28 1 87 A 6 7 Page Notes 32B4 32B3 28D6 14C2 MEMVREF_OUT 1B 3B Power aliases required by this page: - =PP1V8_S3_MEM - =PPSPD_S0_MEM (2.5V - 3.3V) C2901 1 1 2.2uF 20% 6.3V CERM1 603 Signal aliases required by this page: - =I2C_SODIMMB_SCL - =I2C_SODIMMB_SDA C2900 MEM_B_DQ<15> 15C4 MEM_B_DQ<14> 0.1uF 2 2 5B 15C4 20% 10V CERM 402 7B 9B 15C2 15C2 MEM_B_DQS_N<1> MEM_B_DQS_P<1> 11B 13B 15B BOM options provided by this page: (NONE) D 201 15C4 15C4 MEM_B_DQ<10> MEM_B_DQ<13> 17B 19B 21B NOTE: This page does not supply VREF. The reference voltage must be provided by another page. MEM_B_DQ<7> 15D4 MEM_B_DQ<2> 23B MEM_B_DQS_N<0> 15C2 MEM_B_DQS_P<0> 29B 15D4 25B 27B 15C2 31B 33B 15D4 15D4 MEM_B_DQ<1> MEM_B_DQ<4> 35B 37B 39B 41B MEM_B_DQ<21> 15C4 MEM_B_DQ<19> 43B 15C4 45B 47B 15C2 15C2 49B MEM_B_DQS_N<2> MEM_B_DQS_P<2> 51B 53B 15C4 15C4 55B MEM_B_DQ<20> MEM_B_DQ<23> 57B 59B 61B MEM_B_DQ<29> 15C4 MEM_B_DQ<24> 15C4 63B 65B 15C2 MEM_B_DM<3> 67B NC 69B 71B C 15C4 "Factory" (thru-hole) slot 15C4 MEM_B_DQ<27> MEM_B_DQ<25> 73B 75B 77B 30D6 14C4 MEM_CKE<2> 79B 81B NC 30A6 15D2 MEM_B_BS<2> 83B 85B 87B MEM_B_A<12> 15B2 MEM_B_A<9> 15B2 MEM_B_A<8> 89B 30B6 15B2 30B6 30B6 91B 93B 95B MEM_B_A<5> MEM_B_A<3> 15C2 MEM_B_A<1> 97B 30B6 15B2 99B 30B6 15B2 30B6 101B 103B 105B MEM_B_A<10> 15D2 MEM_B_BS<0> 15B2 MEM_B_WE_L 30B6 15B2 30A6 30A6 107B 109B 111B MEM_B_CAS_L 14C4 MEM_CS_L<3> 113B 30A6 15D2 30D6 115B 117B 30C6 14C4 MEM_ODT<3> 119B 121B 15B4 MEM_B_DQ<36> 15C4 MEM_B_DQ<33> B 123B 125B 127B MEM_B_DQS_N<4> 15C2 MEM_B_DQS_P<4> 129B 15C2 131B 133B MEM_B_DQ<34> 15B4 MEM_B_DQ<35> 135B 15B4 137B 139B MEM_B_DQ<40> 15B4 MEM_B_DQ<41> 141B 15B4 143B 145B 15C2 MEM_B_DM<5> 147B 149B 15B4 15B4 MEM_B_DQ<42> MEM_B_DQ<43> 151B 153B 155B 15A4 15B4 MEM_B_DQ<62> MEM_B_DQ<59> 157B 159B 161B NC 163B 165B MEM_B_DQS_N<7> 15C2 MEM_B_DQS_P<7> 167B 15C2 169B 171B 15A4 MEM_B_DQ<60> 15A4 MEM_B_DQ<61> 173B 175B 177B A MEM_B_DQ<54> 15B4 MEM_B_DQ<51> 179B 15B4 181B 183B 15C2 MEM_B_DM<6> 185B 187B MEM_B_DQ<52> 71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6 15B4 MEM_B_DQ<49> 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 PP3V3_S0 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33D8 33D3 33C7 29A3 28A6 27D8 27D5 27D3 27C3 26D1 SMBUS_SB_SDA 65B3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 82D5 82C6 82B3 82A4 79D3 79A8 46B6 33B6 28A6 27D8 27D7 27D6 27C6 27B6 23D5 5B1 SMBUS_SB_SCL 189B 15B4 191B 193B 195B 197B 81C3 48B3 199B VREF VSS1 DQ0 CRITICAL J2900 DQ1 VSS4 DQS0* DQS0 VSS6 DQ2 DQ3 VSS8 F-RT-TH1 6 5 DQ5 VSS2 DM0 DQ6 DQ7 VSS7 DQ12 DQ13 VSS9 DM1 VSS10 VSS11 DQS1* DQS1 CK0 CK0* VSS12 VSS13 DQ10 DQ11 DQ14 DQ15 VSS14 VSS15 KEY VSS16 DQ16 VSS17 DQ20 DQ17 DQ21 VSS18 DQS2* VSS19 NC0 DQS2 DM2 VSS21 DQ18 VSS22 DQ22 DQ19 VSS23 DQ23 VSS24 DQ24 DQ28 DQ25 VSS25 DQ29 VSS26 DM3 DQS3* NC1 VSS27 DQS3 VSS28 DQ26 DQ30 DQ27 VSS29 CKE0 VDD0 DQ31 VSS30 NC/CKE1 VDD1 NC2 NC/A15 BA2 VDD2 NC/A14 VDD3 A12 A11 A9 A8 A7 A6 VDD4 VDD5 A5 A3 A4 A2 A1 VDD6 A0 VDD7 A10/AP BA1 BA0 WE* RAS* S0* VDD8 VDD9 CAS* NC/S1* ODT0 NC/A13 VDD10 VDD11 NC/ODT1 VSS31 NC3 VSS32 DQ32 DQ33 DQ36 DQ37 VSS33 VSS34 DQS4* DQS4 DM4 VSS35 VSS36 DQ38 DQ39 VSS37 DQ34 DQ35 VSS38 DQ44 DQ45 VSS39 DQ40 DQ41 VSS40 DM5 DQS5* DQS5 VSS41 VSS42 DQ46 DQ47 DQ42 DQ43 VSS43 VSS44 DQ48 DQ49 DQ52 DQ53 VSS45 VSS46 NC_TEST VSS47 CK1 CK1* DQS6* DQS6 VSS48 DM6 VSS49 VSS50 DQ50 DQ51 DQ54 DQ55 VSS51 VSS52 DQ56 DQ57 DQ60 DQ61 VSS53 VSS54 DM7 VSS55 DQS7* DQS7 DQ58 DQ59 VSS56 DQ62 DQ63 VSS57 SDA SCL VSS58 SA0 VDDSPD SA1 202 7 VSS0 DQ4 VSS5 DQ8 DQ9 516-0140 8 PP1V8_S3 NC 2 3 4 5 PP1V8_S3 29D3 29B2 28D6 28D3 28B2 19D7 16B6 14C2 5D4 5B2 67B8 67B6 64C1 64A6 37B2 32C6 31C5 DDR2-SODIMM-DUAL 8 1 5B2 5D4 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D6 31C5 32C6 37B2 64A6 64C1 67B6 67B8 2B 4B MEM_B_DQ<9> MEM_B_DQ<11> 6B 15C4 15C4 8B 10B MEM_B_DM<1> 15D2 12B MEM_B_DQ<12> MEM_B_DQ<8> 14B 16B 15C4 15C4 18B MEM_B_DQ<3> MEM_B_DQ<6> 20B 22B 15D4 D 15D4 24B 26B MEM_B_DM<0> 15D2 MEM_CLK_P<3> MEM_CLK_N<3> 14D4 28B 30B 32B 14D4 34B MEM_B_DQ<0> MEM_B_DQ<5> 36B 38B 15D4 15D4 40B 42B 44B 46B MEM_B_DQ<22> MEM_B_DQ<18> 15C4 PM_EXTTS_L MEM_B_DM<2> 15D2 15C4 48B 50B 52B 14B7 28C3 51B7 52D3 52D5 54B 56B MEM_B_DQ<17> MEM_B_DQ<16> 58B 15C4 15C4 60B 62B MEM_B_DQ<26> MEM_B_DQ<28> 64B 15C4 15C4 66B MEM_B_DQS_N<3> MEM_B_DQS_P<3> 68B 70B 15C2 15C2 72B MEM_B_DQ<31> MEM_B_DQ<30> 74B 76B C 15C4 15C4 78B MEM_CKE<3> 80B 14C4 30D6 82B 84B NC_MEM_B_A<15> NC_MEM_B_A<14> 86B 6D7 6D7 88B MEM_B_A<11> MEM_B_A<7> MEM_B_A<6> 90B 92B 94B DDR2 Bypass Caps 15B2 30B6 15B2 30B6 (For return current) 15B2 30B6 PP1V8_S3 96B 29D6 29D3 28D6 28D3 28B2 19D7 16B6 14C2 5D4 5B2 67B8 67B6 64C1 64A6 37B2 32C6 31C5 MEM_B_A<4> MEM_B_A<2> MEM_B_A<0> 98B 100B 102B 15B2 30B6 15C2 30B6 1 15C2 30B6 C2908 1 10UF 104B 106B MEM_B_BS<1> MEM_B_RAS_L MEM_CS_L<2> 108B 110B 2 15D2 30A6 15B2 30A6 C2909 10UF 20% 20% 6.3V X5R 603 2 C2910 1 6.3V X5R 603 14C4 30D6 112B MEM_ODT<2> MEM_B_A<13> 114B 116B 14C4 30C6 1 15B2 30B6 118B 120B NC 2 122B MEM_B_DQ<32> MEM_B_DQ<37> 124B 126B 1 C2911 0.1uF 1UF 10% 20% 10% 6.3V CERM 402 2 C2914 1 10V CERM 402 2 C2915 1 1 C2912 1UF C2913 1UF 10% 6.3V 2 CERM 402 6.3V CERM 402 15C4 15B4 B 128B 1 MEM_B_DM<4> 130B 15C2 132B MEM_B_DQ<38> MEM_B_DQ<39> 134B 136B 2 15B4 C2916 1 C2917 1UF 1UF 1UF 0.1uF 10% 10% 10% 20% 6.3V CERM 402 2 C2918 1 6.3V CERM 402 2 C2919 1 6.3V 2 CERM 402 10V CERM 402 15B4 138B MEM_B_DQ<44> MEM_B_DQ<45> 140B 142B 15B4 1 15B4 144B MEM_B_DQS_N<5> MEM_B_DQS_P<5> 146B 148B 0.1uF 0.1uF 20% 20% 20% 10V 2 CERM 15C2 10V 2 CERM 402 15C2 C2920 0.1uF 1 402 C2921 0.1uF 20% 10V 2 CERM 2 402 10V CERM 402 150B MEM_B_DQ<46> MEM_B_DQ<47> 152B 154B 15B4 15B4 156B MEM_B_DQ<58> MEM_B_DQ<63> 158B 160B 15B4 15A4 162B 164B 166B MEM_CLK_P<2> MEM_CLK_N<2> 14D4 MEM_B_DM<7> 15C2 14D4 168B 170B 172B MEM_B_DQ<56> MEM_B_DQ<57> 174B 176B DDR2 SO-DIMM Connector B 15B4 15B4 178B SYNC_MASTER=M59_MLB MEM_B_DQ<55> MEM_B_DQ<50> 180B 182B 15B4 15B4 184B MEM_B_DQS_N<6> MEM_B_DQS_P<6> 186B 188B 15C2 PP3V3_S0 15C2 1 MEM_B_DQ<53> MEM_B_DQ<48> 194B 196B 15B4 2 4 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 5% 1/16W MF-LF 402 SIZE DRAWING NUMBER D SHT NONE 3 2 REV. 051-7164 SCALE ADDR=0xA4(WR)/0xA5(RD) NC THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING APPLE COMPUTER INC. SODIMM_A_SA1 200B R2900 10K 15B4 Resistor prevents pwr-gnd short 198B 79D3 82A4 82B3 82C6 82D5 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 29A6 33C7 33D3 33D8 34A8 36D6 40B6 49B5 25A4 25B4 25B8 25C4 25C6 25D3 25D8 26B4 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 26B6 26B8 26D1 27C3 27D3 27D5 27D8 28A6 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 66B5 66B6 67A3 67B3 67C3 67C5 71D2 79A8 190B 192B SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY 06004 OF 29 1 87 A 8 7 6 3 4 5 2 1 One cap for each side of every RPAK, one cap for every two discrete resistors Ensure CS_L and ODT resistors are close to SO-DIMM connector 67D8 67D6 66B5 31C2 5D4 29B6 29B3 28B6 28B3 14C4 IN MEM_CS_L<3..0> RP3001 RP3004 RP3007 RP3010 0 D 1 2 3 29C6 29C3 28C6 28C3 14C4 IN MEM_CKE<3..0> RP3009 RP3009 RP3012 RP3012 0 1 2 3 29B6 29B3 28B6 28B3 14C4 IN MEM_ODT<3..0> RP3013 RP3004 RP3007 RP3010 0 1 2 3 28C6 28C3 28B6 28B3 15C5 15B5 IN MEM_A_A<13..0> RP3002 RP3005 RP3002 RP3001 RP3002 RP3002 RP3006 RP3003 RP3006 RP3003 RP3005 RP3006 RP3003 RP3013 0 1 2 3 4 5 6 C 7 8 9 10 11 12 13 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 PP0V9_S0 2 7 4 5 1 8 1 8 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 6 2 7 5% 1/16W SM-LF 2 7 5% 1/16W SM-LF 1 8 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 8 3 6 2 7 2 7 4 5 4 5 3 6 1 8 1 8 2 7 3 6 3 2 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 6 5% 1/16W SM-LF 7 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W 5 1 8 4 5 1 8 3 6 1 2 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 1 IN MEM_A_BS<2..0> RP3001 RP3005 RP3009 0 1 2 56 56 56 3 6 3 6 5% 1/16W SM-LF 4 5 5% 1/16W SM-LF 5% 1/16W SM-LF 2 1 IN 28B6 15D5 IN 28B6 15B5 IN RP3005 RP3004 RP3001 MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L 56 56 56 2 7 2 7 5% 1/16W SM-LF 4 5 5% 1/16W SM-LF 5% 1/16W SM-LF 1 29C6 29C3 29B6 29B3 15C2 15B2 IN MEM_B_A<13..0> RP3013 RP3012 RP3006 RP3009 RP3003 RP3011 RP3008 RP3008 RP3011 RP3012 RP3008 RP3008 RP3011 RP3007 0 1 2 3 4 5 6 7 8 9 10 11 12 13 56 56 56 56 56 56 56 56 56 56 56 56 56 56 2 7 4 5 1 8 1 1 8 2 4 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W SM-LF 7 5% 1/16W SM-LF 5 5% 1/16W SM-LF 3 6 5% 1/16W SM-LF 4 5 5% 1/16W SM-LF 3 6 5% 1/16W SM-LF 3 6 5% 1/16W SM-LF 1 8 5% 1/16W SM-LF 2 7 5% 1/16W SM-LF 2 7 5% 1/16W SM-LF 3 6 5% 1/16W SM-LF 5% 1/16W SM-LF IN MEM_B_BS<2..0> RP3007 RP3013 RP3011 0 1 2 56 56 56 4 5 4 5 1 8 2 5% 1/16W SM-LF 5% 1/16W SM-LF 5% 1/16W 1 A IN 29B6 15D2 IN 29B6 15B2 IN RP3004 RP3010 RP3010 MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L 56 56 56 C3030 20% 10V CERM 402 C3032 20% 10V CERM 402 C3034 20% 10V CERM 402 C3036 20% 10V CERM 402 C3038 20% 10V CERM 402 C3050 20% 10V CERM 402 C3052 2 1 20% 10V CERM 402 C3054 1 1 C3056 1 SM-LF C3011 20% 10V CERM 402 C3031 20% 10V CERM 402 C3033 C 0.1uF 2 1 20% 10V CERM 402 C3035 0.1uF 2 1 20% 10V CERM 402 C3037 0.1uF 2 1 20% 10V CERM 402 C3039 0.1uF 2 1 20% 10V CERM 402 C3051 B 0.1uF 2 1 20% 10V CERM 402 C3053 0.1uF 2 1 20% 10V CERM 402 C3055 0.1uF 2 1 0.1uF 20% 10V CERM 402 20% 10V CERM 402 0.1uF 2 0.1uF 20% 10V CERM 402 C3007 0.1uF 2 0.1uF 2 29B3 15B2 1 0.1uF 2 29C6 29B6 29B3 15D2 20% 10V CERM 402 0.1uF 1 5% C3010 20% 10V CERM 402 0.1uF 2 0.1uF 2 B 1 0.1uF 2 28B3 15B5 20% 10V CERM 402 0.1uF 2 28C6 28B6 28B3 15D5 C3005 D C3002 0.1uF 2 0.1uF SM-LF 5% 1 0.1uF 2 SM-LF 20% 10V CERM 402 0.1uF 1 1/16W 4 1 2 5% C3000 0.1uF 2 3 1 1 20% 10V CERM 402 C3057 0.1uF 2 20% 10V CERM 402 Memory Active Termination 1 8 4 5 5% 1/16W SM-LF 3 6 5% 1/16W SM-LF 5% 1/16W SM-LF 1 2 C3058 1 C3059 0.1uF 0.1uF 20% 10V CERM 402 20% 10V CERM 402 2 SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 30 1 87 A 8 Page Notes 7 6 2 3 4 5 1 Power aliases required by this page: - =PP5V_S0_MEMVTT - =PP1V8_S0_MEMVTT - =PP0V9_S0_MEMVTT_LDO Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE) D D DDR2 Vtt Regulator PP5V_S0 61D7 58C7 58C4 57B5 55A8 53C4 36D6 25D8 5D4 5D2 81B3 80B5 80A1 79B8 71A6 67B3 67B1 67A1 66B5 62B1 C3104 1 4.7UF 29D3 29B2 28D6 28D3 28B2 19D7 16B6 14C2 5D4 5B2 67B8 67B6 64C1 64A6 37B2 32C6 29D6 PP1V8_S3 C3101 C 20% 6.3V CERM 603 1 2 C 10UF If power inputs are not S0, MEMVTT_EN can be used to disable MEMVTT in sleep. 1 VDDQSNS MSOP PP0V9_S0 5D4 30D5 66B5 67D6 67D8 VTT 3 CRITICAL 2 7 S3 VTTSNS 5 9 S5 THRML PGND PAD VTTREF 6 MEMVTT_VREF GND 8 MEMVTT_EN VIN TPS51100 4 1K VLDOIN U3100 R31001 5% 1/16W MF-LF 402 10 MEMVTT_EN_PU 2 2 11 20% 6.3V X5R 603 1 1 C3102 0.1UF Okay to turn off 5V and leave 1.8V powered in S3. 2 20% 25V X5R 402 C3105 22UF 20% 6.3V 2 X5R 805 1 C3106 22UF 20% 6.3V 2 X5R 805 B B Memory Vtt Supply A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 31 1 87 A 8 7 6 2 3 4 5 1 D D C 81D4 46D6 46C3 46B3 41C5 37D7 37D5 37C3 37A7 27C5 5D4 81A5 67C5 67C3 66C6 65D1 63B7 60C2 59C6 57D4 52B1 C PP3V3_S3 MEMVREF_S3 C3200 1 R3202 1 0.1UF 20% 10V CERM 402 29D3 29B2 28D6 28D3 28B2 19D7 16B6 14C2 5D4 5B2 67B8 67B6 64C1 64A6 37B2 31C5 29D6 100K 5% 1/16W MF-LF 402 2 PP1V8_S3 R3205 1 U3200 10K 4 1% 1/16W MF-LF 402 2 V+ 3 MEMVREF_UNBUF R3206 1 10K 1% 1/16W MF-LF 402 2 2 CRITICAL MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAX4236EUTT SOT23-6-LF 1 5 V2 C3205 6 14C2 28D6 29D6 32B3 32B4 14C2 28D6 29D6 32B3 32B4 14C2 28D6 29D6 32B3 32B4 MEMVREF_S0 1 R3203 220pF 5% 25V CERM 402 MEMVREF_OUT MEMVREF_OUT MEMVREF_OUT MEMVREF_OUT MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.15 mm VOLTAGE=0.9V MAKE_BASE=TRUE 2 MEMVREF_SHDN_L 2 0 1 PM_SLP_S3_L IN 5% 1/16W MF-LF 402 B B DDR2 VRef A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 32 1 87 A 8 6 7 2 3 4 5 1 L3302 FERR-120-OHM-1.5A PP3V3_S0_CK410_VDD48_PCI VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm 1 1 C3308 1 C3309 0.1UF 82D5 79A8 71D2 67C5 66B5 66B1 65D6 60D4 60C7 58C7 52D3 49C7 49C4 33D3 33C7 29A6 27D3 27C3 26D1 25D3 25C6 25C4 24C3 24B5 24B3 21C3 20B4 20A4 14C7 10C5 5D4 5A4 19C7 19C6 17C6 14D6 23D5 23B3 22B5 21D3 25B8 25B4 25A4 24D3 26B8 26B6 26B4 25D8 29A3 28A6 27D8 27D5 49B5 40B6 36D6 34A8 58C4 57B6 54D4 54B5 65B3 62A6 61D8 61A5 67C3 67B3 67A3 66B6 82C6 82B3 82A4 79D3 PP3V3_S0 1 10UF 10% 2 16V X5R 402 D 2 0402-LF C3310 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D8 34A8 36D6 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 82D5 1UF 20% 2 6.3V X5R 603 10% 2 6.3V CERM 402 D L3301 FERR-120-OHM-1.5A 1 2 PP3V3_S0_CK410_VDD_CPU_SRC_A PP3V3_S0 VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm 0402-LF 1 C3314 1 1UF 1 10% 6.3V 2 CERM 402 10UF 20% 2 6.3V X5R 603 0.1UF 10% 16V 2 X5R 402 0.1UF 10% 16V 2 X5R 402 0.1UF 10% 16V 2 X5R 402 0.1UF 0.1UF 10% 10% 2 16V X5R 0.1UF 2 16V X5R 402 10% 16V 2 X5R 402 10% 16V 2 X5R 402 C3305 1 C3306 1 C3317 0.1UF C3316 1 C3315 1 C3301 1 C3302 1 C3303 1 C3304 402 10UF 20% 2 6.3V X5R 603 R3303 5A4 1 VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm C3312 C3311 1 10UF 20% 2 6.3V X5R 603 PP3V3_S0_CK410_VDD_REF 1 0.1UF 1 C3307 0.1UF 10% 1 2 5% 1/16W MF-LF 402 10% 2 16V X5R 2 16V X5R 402 402 C3389 12PF 5% 2 50V CERM 402 1 C3390 35 17 28 U3301 PP3V3_S0 34B8 IN SLG8LP436 R3301 (FW PCI 33MHZ) 34D8 10K (TPM LPC 33MHZ) 5% 1/16W MF-LF (SMC LPC 33MHZ) 2402 34D8 34D6 (NO USED) 34A8 CK410_PCI5_FCTSEL1 IO (PORT80 LPC 33MHZ) (ICH7M PCI 33MHZ) OUT OUT OUT OUT OUT (INT PD) PCI_1 PCI_2 23C8 CPU_1* CPU_1 41 34D5 34D3 12A6 5B4 42 34D5 34D3 12A6 CPU_ITP/SRC_11* 36 CPU_0 CPU_ITP/SRC_11 37 SRC_0/LCD_CLK* SRC_0/LCD_CLK 11 10 SRC_1* 14 SRC_1 13 9 PCI_3 PCI_4 65 PCI_5/FCT_SEL_1 (INT PU) CLKREQ_1* 34D5 34D3 7C6 5C4 87C6 34D5 34D3 11B3 PM_STPPCI_L 5B4 PM_STPCPU_L 23C8 5B4 34D5 34D3 7C6 5C4 68 PCIF_0/ITP_EN 1 PCIF_1 CK410_PCIF1_CLK 56 (INT PU) 55 (INT PU) 44 45 CPU_0* CRITICAL 8 FS_B_TEST_MODE 57 CK410_PCI1_CLK 58 CK410_PCI2_CLK CK410_PCI3_CLK 63 TP_CK410_PCI4_CLK64 CPU_STOP* QFN OMIT 51 XTAL_IN 50 XTAL_OUT CK410_FSB_TEST_MODE 1 CK410_PCIF0_CLK 12 PCI_STOP* 402 CK410_XTAL_IN CK410_XTAL_OUT OUT 49 5% VDD_A 39 VSS_A 34D8 C 12PF 2 50V CERM 38 71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33D8 33D3 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 65B3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 82D5 82C6 82B3 82A4 79D3 79A8 (EACH POWER PIN PLACED ONE 0.1UF) (PLACED 0.1UF NEAR THE RELATIVE POWER PIN) VDD_SRC 1 C VDD_REF 2 5X3.2-SM 61 VDD_PCI 67 VDD_48 1 NEED TO CHECK CAP VALUE VDD_CPU 3 Y3301 14.31818 43 CRITICAL FSB_CLK_CPU_N FSB_CLK_CPU_P FSB_CLK_NB_N 5C4 FSB_CLK_NB_P CPU_XDP_CLK_N CPU_XDP_CLK_P 34B5 34B4 14C4 5B4 34B5 34B4 14B4 5B4 IN PEG_CLK100M_GPU_N 34B5 34B4 PEG_CLK100M_GPU_P 34A4 CK410_SRC_CLKREQ1_L SRC_2* SRC_2 16 34C5 34C3 22C2 15 34C5 34C3 22C2 SRC_3* 19 18 48B6 34B5 34B3 5B1 SB_CLK100M_DMI_N SB_CLK100M_DMI_P (FROM ICH7 GPIO18 STPPCI* ) (FROM ICH7 GPIO20 STPCPU* ) OUT OUT (CPU HOST 133/167MHZ) OUT OUT (GMCH HOST 133/167MHZ) OUT OUT NB_CLK_DREFSSCLKIN_NOUT NB_CLK_DREFSSCLKIN_POUT 70A5 34B5 34B4 70A5 IN OUT (ITP HOST 133/167MHZ) (GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ) (GPU PCI-E 100 MHZ ) OUT IN NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO? OUT OUT (ICH7M DMI 100 MHZ ) (PULL UP PIN 68 TO ENABLE ITP HOST CLK) 81C3 29A6 28A6 27D8 27D7 27D6 27C6 27B6 23D5 5B1 IN 48B3 46B6 29A6 28A6 27D8 27D7 27D6 27C6 27B6 23D5 5B1 IO 81C3 48B3 46B6 (ICH SM BUS) SMBUS_SB_SCL SMBUS_SB_SDA 47 SCL 48 SDA CK410_IREF SRC_3 (INT PU) CLKREQ_3* 40 NC SRC_4* B 5 NO STUFF 1 R3300 SRC_4 (INT PU) CLKREQ_4* VSS_48 46 VSS_CPU 475 1% 1/16W MF-LF 2 402 62 59 SB_CLK100M_SATA_N SB_CLK100M_SATA_P 23C3 SB_CLK100M_SATA_OE_L 34C5 34C3 21B6 5A7 20 SRC_5* 24 SRC_5 23 60 (INT PU) CLKREQ_5* SRC_6* SRC_6 27 52 VSS_REF 31 VSS_SRC (INT PU) CLKREQ_6* 25 SRC_7* SRC_7 30 29 SRC_8* 32 SRC_8 33 34 (INT PU) CLKREQ_8* 34C5 34C3 21B6 5A7 22 21 66 VSS_PCI 69 THRML_PAD PCIE_CLK100M_EXCARD_N OUT PCIE_CLK100M_EXCARD_P OUT EXCARD_CLKREQ_L IN 48B6 34C5 34C3 5B1 IN 48C6 34D5 34D4 5B1 48C6 34D5 34D4 5B1 PCIE_CLK100M_MINI_NOUT PCIE_CLK100M_MINI_POUT MINI_CLKREQ_L IN 26 34B5 34B5 CK410_SRC7_N CK410_SRC7_P OUT (ICH SATA 100 MHZ) B (FROM ICH7 GPIO35) 39C6 CK410_27M_SPREAD CK410_27M_NONSPREAD 34B5 (INT PD) VTT_PWRGD*/PD 2 61C7 26A8 26A7 48M/FS_A 4 54 53 VR_PWRGD_CK410_L CK410_USB48_FSA CK410_CLK14P3M_TIMER 34A8 CK410_REF1_FCTSEL0 34C8 34B8 (GMCH G_CLKIN 100 MHZ ) (FROM GMCH CLK_REQ*) (WIRELESS PCI-E 100 MHZ ) (NB CRT/TV GRAPHICS DOTCLK 100MHZ) OUT ENET_CLK100M_PCIE_NOUT 34C5 34C3 ENET_CLK100M_PCIE_P OUT 34A4 CK410_SRC_CLKREQ8_L IN 39C6 34C5 34C3 34B5 REF_0/FS_C/TEST_SEL OUT NB_CLK100M_GCLKIN_NOUT 34C5 34C4 14C4 5B4 NB_CLK100M_GCLKIN_P OUT 14B6 5B4 CLK_NB_OE_L IN 6 (INT PD) REF_1/FCT_SEL_0 OUT 34C5 34C4 14C4 5B4 7 DOT_96*/27M_SS* DOT_96/27M (FOR PCI-E CARD) (GIGA LAN PCI-E 100 MHZ ) (GMCH D_REFCLKIN DISPLAY PLL A 96MHZ) OUT OUT IN OUT OUT (FROM CPU VCORE PWR GOOD) (ICH7M USB 48MHZ) (ICH7M,SIO,LPC REF. 14.318MHZ) IO CLOCKS A FCTSEL1 0 FCTSEL0 0 PIN 6 DOT96T PIN 7 DOT96C PIN 10 100MT_SST SYNC_MASTER=M59_MLB PIN 11 100MC_SST 0 1 DOT96T DOT96C SRCT0 SRCC0 1 0 27M NON SPREAD 27M SPREAD SRCT0 SRCC0 1 1 OFF LOW TBD SRCT0 SRCC0 SYNC_DATE=09/15/2006 A NOTICE OF PROPRIETARY PROPERTY * FOR INT. GRAPHIC SYSTEM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING * FOR EXT. GRAPHIC SYSTEM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 33 1 87 8 6 7 2 3 4 5 1 R3463 33B7 CK410_PCIF0_CLK IN 1 33 2 5% 1/16W MF-LF 402 33B6 CK410_PCIF1_CLK IN 33 1 CK410_PCI1_CLK IN 1 33 D CK410_PCI2_CLK 33B6 CK410_PCI3_CLK 34D6 33B6 IN TP_CK410_PCI4_CLK IN OUT 22A6 (TO ICH7M PCI 33MHZ) PCI_CLK_FW OUT 37B6 (TO FIREWIRE PCI 33MHZ) PCI_CLK_TPM OUT 60C6 (TO TPM PCI 33MHZ) IN 34D3 33C4 7C6 5C4 33 34D3 33C4 12A6 5C4 2 5% 1/16W MF-LF 402 PCI_CLK_SMC 5% 1/16W MF-LF 402 OUT 51C7 IN FSB_CLK_CPU_N IN FSB_CLK_NB_P 87C6 34D3 33C4 11B3 NOSTUFF 1 C3401 15PF PLACEMENT of these caps should be close as possible to the resistors NOSTUFF 1 C3402 15PF 5% 50V 2 CERM 402 5% 50V 2 CERM 402 FSB_CLK_CPU_N MAKE_BASE=TRUE FSB_CLK_NB_P MAKE_BASE=TRUE IN FSB_CLK_NB_N IN CPU_XDP_CLK_P 33B6 34D8 MAKE_BASE=TRUE C3400 FSB_CLK_NB_N MAKE_BASE=TRUE CPU_XDP_CLK_P MAKE_BASE=TRUE NOSTUFF 1 IN CPU_XDP_CLK_N IN PCIE_CLK100M_MINI_P CPU_XDP_CLK_N 15PF 15PF 15PF 5% 50V 2 CERM 402 5% 50V 2 CERM 402 5% 50V 2 CERM 402 48C6 34D4 33B4 5B1 CK410_USB48_FSA IN 23D3 SB_CLK48M_USBCTLR (TO ICH7M USB 48MHZ) OUT 19D7 21C1 24C3 24D3 25C4 25D3 34B8 34C8 55A4 65A2 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 67D6 67D8 PP1V05_S0 1 48C6 34D5 33B4 5B1 PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N IN NB_CLK100M_GCLKIN_P 34C5 33B4 14C4 5B4 IN NB_CLK100M_GCLKIN_N 34C5 33B4 14C4 5B4 IN SB_CLK100M_DMI_P 48C6 34D5 33B4 5B1 PCIE_CLK100M_MINI_N NOSTUFF 34C4 33B4 14C4 5B4 34C3 33B4 22C2 34C3 33B4 22C2 1K NB_BSEL<0> 2 NB_CLK100M_GCLKIN_P OUT MAKE_BASE=TRUE 1 OUT 39C6 34C3 33A4 (TO MCH FS_A) 39C6 34C3 33A4 R3450 CPU_BSEL_R<0> 2 NB_CLK100M_GCLKIN_N OUT MAKE_BASE=TRUE SB_CLK100M_DMI_P OUT MAKE_BASE=TRUE IN SB_CLK100M_DMI_N IN ENET_CLK100M_PCIE_P SB_CLK100M_DMI_N MAKE_BASE=TRUE ENET_CLK100M_PCIE_P MAKE_BASE=TRUE 0 1 2 7B4 CPU_BSEL<0> IN 5% 1/16W MF-LF 402 R3469 34C3 33B4 21B6 5A7 34C3 33B4 21B6 5A7 IN ENET_CLK100M_PCIE_N IN SB_CLK100M_SATA_P ENET_CLK100M_PCIE_N MAKE_BASE=TRUE SB_CLK100M_SATA_P MAKE_BASE=TRUE 48B6 34C3 33B4 5B1 1 48B6 34B3 33B4 5B1 R3470 5% 1/16W MF-LF 2 402 CK410_FSB_TEST_MODE 1K 1 2 1K 14C6 1 5% 1/16W MF-LF 402 1 IN PCIE_CLK100M_EXCARD_P 2 34B5 33A4 NB_BSEL<1> OUT SB_CLK100M_SATA_N MAKE_BASE=TRUE PCIE_CLK100M_EXCARD_P MAKE_BASE=TRUE PP1V05_S0 34B5 33A4 1 1K IN 34B5 33A4 R3451 0 1 2 7B4 CPU_BSEL<1> IN (FROM CPU FS_B) 5% 1/16W MF-LF 402 NOSTUFF R3452 PCIE_CLK100M_EXCARD_N 33A4 34C5 39C6 OUT 33A4 34C5 39C6 OUT 5A7 21B6 33B4 34C5 OUT 5A7 21B6 33B4 34C5 OUT 5B1 33B4 34C5 48B6 OUT MAKE_BASE=TRUE CK410_27M_NONSPREAD CK410_27M_NONSPREAD 121 1 C 1% 1/16W MF-LF 402 CK410_27M_SPREAD CK410_27M_SPREAD 77A5 74C2 74C1 34B2 34B4 33B4 70A5 IN GPU_CLK27M R3419 1 56 2 77C3 74C8 74C5 34B2 70A5 34B5 33B4 GPU_CLK27MSS_IN 77C3 74C8 74C5 34B4 OUT GPU_CLK27MSS_IN PEG_CLK100M_GPU_P 5% 1/16W MF-LF 402 CPU_BSEL_R<2> 1 NOSTUFF R3454 71.5 2 OUT 70A5 34B4 33B4 IN PEG_CLK100M_GPU_N IN NB_CLK_DREFSSCLKIN_P 70A5 34B5 33B4 PEG_CLK100M_GPU_N OUT MAKE_BASE=TRUE 19A6 17C6 PP1V5_S0_NB_VCCA_DPLLA 1NO STUFF 34B4 33B4 14B4 5B4 34B5 33B4 14B4 5B4 NB_CLK_DREFSSCLKIN_P R3426 OUT MAKE_BASE=TRUE 100K IN NB_CLK_DREFSSCLKIN_N 34B5 33B4 14C4 5B4 NB_CLK_DREFSSCLKIN_N MAKE_BASE=TRUE 2 R3424 R3443 NB_BSEL<2> 33B4 (TO MCH FS_C) OUT 33B4 R3453 0 1 2 7B4 CPU_BSEL<2> IN IN IN CK410_SRC7_P CK410_SRC7_N 0 1 5% 1/16W MF-LF 402 B 5% 1/16W MF-LF 2 402 OUT NO STUFF 5% 1/16W MF-LF 402 R3402 1 1% 1/16W MF-LF 402 MAKE_BASE=TRUE R3475 14C6 1 NO STUFF (GPU PCI-E Graphics 100MHz) 34B4 33B4 14C4 5B4 1K 2 1% 1/16W MF-LF 402 (NB LVDS GRAPHICS 100MHZ) 5% 1/16W MF-LF 2 402 71.5 1 GPU_CLK27M (GPU 27MHz Spread / Non-Spread) 5% 1/16W MF-LF 402 PEG_CLK100M_GPU_P 77A5 74C2 74C1 34B4 OUT R3473 2 5B1 33B4 34B5 48B6 R3405 2 MAKE_BASE=TRUE 1K R3474 PCIE_CLK100M_EXCARD_N MAKE_BASE=TRUE (TO MCH FS_B) 5% 1/16W MF-LF 2 402 1 IN 34B5 33A4 IN 1K CK410_CLK14P3M_TIMER OUT R3418 R3472 CPU_BSEL_R<1> 33A4 SB_CLK100M_SATA_N NEED TO CHECK THE BSEL PULLS 5% 1/16W MF-LF 402 IN 22C2 33B4 34C5 (ExpressCard Slot) R3471 B IN PP1V05_S0 1K 67D8 24D3 19C8 12A7 5B2 8C7 16C8 19D6 34C8 OUT (ICH7M SATA 100MHZ) 5% 1/16W MF-LF 2 402 34C6 25D3 25C4 19D5 19D2 19D1 13B5 12C2 12B7 7D5 7B6 7B5 5D4 11C5 11B3 9B7 17D6 17D3 16D3 24C3 21C1 19D7 67D6 65A2 55A4 22C2 33B4 34C5 (FROM CPU FS_A) 1K OUT 11B3 33C4 34D5 87C6 (Yukon PCI-E 100MHZ) 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 33C6 D R3468 R3401 67D8 24D3 19C8 12A7 5B2 8C7 16C8 19D6 34C6 OUT 11B3 33C4 34D5 87C6 (ICH7M DMI 100MHZ) 14C6 1 34B8 25D3 25C4 19D5 19D2 19D1 13B5 12C2 12B7 7D5 7B6 7B5 5D4 11C5 11B3 9B7 17D6 17D3 16D3 24C3 21C1 19D7 67D6 65A2 55A4 5B4 12A6 33C4 34D5 OUT MAKE_BASE=TRUE R3480 5% 1/16W MF-LF 2 402 2.2K OUT OUT MAKE_BASE=TRUE IN 1K 1 5C4 12A6 33C4 34D5 (GMCH G_CLKIN 100MHZ) 2 5% 1/16W MF-LF 402 C OUT (WIRELESS PCI-E MINI 100MHZ) 34C4 33B4 14C4 5B4 33A4 5C4 7C6 33C4 34D5 C3404 48C6 34D4 33B4 5B1 33 OUT OUT MAKE_BASE=TRUE NOSTUFF 1 C3403 R3417 1 5C4 7C6 33C4 34D5 (ITP HOST 133/167MHZ) TP_CK410_PCI4_CLK NOSTUFF OUT MAKE_BASE=TRUE (TO SMC PCI 33MHZ) 87C6 34D3 33C4 11B3 1 FSB_CLK_CPU_P (GMCH HOST 133/167MHZ) 34D3 33C4 12A6 5B4 2 FSB_CLK_CPU_P (CPU HOST 133/167MHZ) TPM R3433 33 PCI_CLK_SB R3430 1 1 5C2 53C5 34D3 33C4 7C6 5C4 2 2 5% 1/16W MF-LF 402 33B6 IN OUT 5% 1/16W MF-LF 402 R3429 33B6 (PORT80 LPC 33MHZ) PCI_CLK_PORT80_LPC R3432 2 34B2 14C4 5B4 34B4 14C4 5B4 NB_CLK_DREFCLKIN_P NO STUFF R3444 1 0 2 (NB CRT/TV GRAPHICS DOTCLK 100MHZ) 34B2 14C4 5B4 NB_CLK_DREFCLKIN_P 34B4 14C4 5B4 NB_CLK_DREFCLKIN_N 0 1 OUT 2 5% 1/16W MF-LF 402 NB_CLK_DREFCLKIN_N R3425 (FROM CPU FS_C) 2 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 0 1 OUT 1K 5% 1/16W MF-LF 2 402 R3476 33 1 71D2 67C5 67C3 67B3 67A3 61A5 60D4 60C7 58C7 58C4 40B6 36D6 33D8 33D3 33C7 26D1 26B8 26B6 26B4 25D8 24C3 24B5 24B3 23D5 23B3 17C6 14D6 14C7 10C5 5D4 21D3 21C3 20B4 20A4 19C7 25C6 25C4 25B8 25B4 25A4 29A3 28A6 27D8 27D5 27D3 54D4 54B5 52D3 49C7 49C4 66B5 66B1 65D6 65B3 62A6 82D5 82C6 82B3 82A4 79D3 66B6 57B6 29A6 25D3 22B5 5A4 19C6 24D3 27C3 49B5 61D8 79A8 2 SB_CLK14P3M_TIMER 5% 1/16W MF-LF 402 1 A 33A4 IO FS_C FS_B FS_A CPU 0 0 0 266M # 0 0 1 133M # 0 1 0 166M 0 1 1 200M 1 0 0 100M 1 0 1 333M 1 1 0 400M RESERVED 1 1 1 # NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED CK410_PCI5_FCTSEL1 CK410_REF1_FCTSEL0 1 R3466 10K 2 8 (ICH7M 14.318MHZ) NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY R3467 5% 1/16W MF-LF 2 402 IO 23D3 PP3V3_S0 10K 33B6 OUT 5% 1/16W MF-LF 402 7 6 5 Clock Termination 48C3 34A3 33B4 5C1 EXCARD_CLKREQ_L 48C3 34A3 33B4 5C1 MINI_CLKREQ_L EXCARD_CLKREQ_L SYNC_MASTER=M59_MLB 5C1 33B4 34A4 48C3 SYNC_DATE=09/15/2006 MAKE_BASE=TRUE MINI_CLKREQ_L NOTICE OF PROPRIETARY PROPERTY 5C1 33B4 34A4 48C3 MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING R3485 33B4 CK410_SRC_CLKREQ1_L GPU CLK OE* 33A4 1 1K 5% 1/16W MF-LF 402 CK410_SRC_CLKREQ8_L Yukon CLK OE* 2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT R3486 1 1K III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 2 SIZE 5% 1/16W MF-LF 402 APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 4 3 2 REV. 051-7164 06004 OF 34 1 87 A 8 6 7 2 3 4 5 1 D D TPM Crystal Circuit TPM TPM C3720 R3721 R3720 1 TPM CRITICAL Y3720 32.768K 10M 5% 1/16W MF-LF 402 2 60C6 SM-2 NC NC 2 5% 50V CERM 402 3 TPM_XTALO_R 2 5% 1/16W MF-LF 402 4 1 NO STUFF 2 TPM_XTALO 15pF 1 TPM C3721 1 60C6 0 15pF 1 TPM_XTALI 2 5% 50V CERM 402 C C SMC G3Hot Oscillator L3750 81D4 69C8 52B7 52B5 52B1 51D4 51D3 51C2 47B5 27C3 26D6 5D2 69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52D7 FERR-EMI-100-OHM PP3V42_G3H 1 2 SM PP3V42_G3H_SMC_CLK_F MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.425V 1 C3750 C3751 4.7uF 2 1 0.1uF 20% 6.3V CERM 603 20% 10V CERM 402 12 CRITICAL VDD 2 U3750 32.768KHZ-9-3.6V R3750 SG-3040LC-SM 1 VIO OUT 7 2 NC0 NC4 8 3 NC1 NC2 NC5 NC6 9 4 5 NC3 NC7 11 SMC_CLK32K_SUSCLK_R 22 1 51C5 2 35B2 SMC_CLK32K_SUSCLK SMC_CLK32K_SUSCLK 35B3 51C5 MAKE_BASE=TRUE NC NC NC NC B 10 5% 1/16W MF-LF 402 NC NC NC NC B GND 6 Mobile Clocking A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 35 1 87 A 8 6 7 3 4 5 2 1 IDE (ODD) Connector 71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 34A8 33D8 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 65B3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 82D5 82C6 82B3 82A4 79D3 79A8 PP3V3_S0 CRITICAL Q3820 PP5V_S0 61D7 58C7 58C4 57B5 55A8 53C4 31C5 25D8 5D4 5D2 81B3 80B5 80A1 79B8 71A6 67B3 67B1 67A1 66B5 62B1 FDZ293P BGA B3 C3 D B1 S B2 A3 A2 C1 PP5V_S0_IDE_ODD MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=5V D NO STUFF R3801 1 G D C2 4.7K R3820 1 5% 1/16W MF-LF 402 2 A1 10K 5% 1/16W MF-LF 402 2 1 10K 22A6 IN 5% 1/16W MF-LF 402 2 20% 6.3V X5R 402 R3821 1 5% 1/16W MF-LF 402 4.7K 0.22uF ODD_PWR_EN_L_RC 23C3 IN 21B5 21B5 2 ODD_PWR_EN_L (UATA_CS0*) IO IO 21B5 IO IO 21B5 IO 21B5 IO 21C5 IO 21B6 C IO 21B5 21B5 (UATA_HSTROBE) (UATA_DSTROBE) 1 R3802 1 C3821 21B6 21B6 OUT IN OUT 21B5 IN 21B5 IN J3800 M-ST-SM1-LF 2 IDE_RESET_L IDE_PDD<7> IDE_PDD<6> IDE_PDD<5> IDE_PDD<4> IDE_PDD<3> IDE_PDD<2> IDE_PDD<1> IDE_PDD<0> IDE_PDDREQ IDE_PDIOR_L IDE_PDIORDY IDE_PDA<2> IDE_PDCS1_L NC R3811 1 15K 5% 1/16W MF-LF 402 2 2 1 50 2 49 21B5 3 48 21B5 4 47 21B5 5 46 21B5 6 45 7 44 21B5 8 43 21B5 9 42 21B5 10 41 21B5 11 40 12 39 21B6 13 38 21B6 14 37 15 36 16 35 17 34 21B5 18 33 21B5 19 32 20 31 21 30 22 29 23 28 24 27 25 26 R3810 33K CRITICAL 5% 1/16W MF-LF 402 IDE_PDD<8> IDE_PDD<9> IDE_PDD<10> IDE_PDD<11> IDE_PDD<12> IDE_PDD<13> IDE_PDD<14> IDE_PDD<15> IDE_PDIOW_L IDE_PDDACK_L IDE_IRQ14 IDE_PDA<1> 21B6 21B5 IDE_PDA<0> IDE_PDCS3_L IO IO IO IO IO IO IO IO IN (UATA_STOP) IN OUT IN IN IN C (UATA_CS1*) Indicates disk presence SMC_ODD_DETECT OUT 51B7 1 R3803 6.2K 5% 1/16W MF-LF 2 402 516S0335 Counters 10K pull-up to 5V in ODD to keep SB GPIO <= 3.3V B B 23D2 SATA_C_DET_L 1 R3850 100 2 5% 1/16W MF-LF 402 36A4 21B6 TP_SATA_A_R2DP TP_SATA_A_R2DP 36A4 21B6 TP_SATA_A_R2DN TP_SATA_A_R2DN 21B6 36A5 MAKE_BASE=TRUE 21B6 36A5 MAKE_BASE=TRUE 36A4 21B6 TP_SATA_A_D2RP TP_SATA_A_D2RP 36A4 21B6 TP_SATA_A_D2RN TP_SATA_A_D2RN 21B6 36A5 MAKE_BASE=TRUE PATA Connector 21B6 36A5 MAKE_BASE=TRUE A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY 36A5 36A4 21B6 36A5 36A4 21B6 SATA_RBIAS SATA_RBIAS 36A5 21B6 SATA_RBIAS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING MAKE_BASE=TRUE 1 Place within 12.7mm from ball of SB R3860 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 24.9 Placement note 2 II NOT TO REPRODUCE OR COPY IT 1% 1/16W MF-LF 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 36 1 87 A 8 6 7 81D4 46D6 46C3 46B3 41C5 37D5 37C3 37A7 32C5 27C5 5D4 81A5 67C5 67C3 66C6 65D1 63B7 60C2 59C6 57D4 52B1 2 3 4 5 81D4 46D6 46C3 46B3 41C5 37D7 37C3 37A7 32C5 27C5 5D4 81A5 67C5 67C3 66C6 65D1 63B7 60C2 59C6 57D4 52B1 PP3V3_S3 PP3V3_S3 1 2 1 C3900 1 C3901 1 C3902 1 C3903 1 C3904 1uF 1uF 1uF 1uF 1uF 10% 10V X5R 402 10% 10V X5R 402 10% 10V X5R 402 10% 10V X5R 402 10% 10V X5R 402 10% 10V X5R 402 2 2 2 2 2 1 C3908 1uF C3909 1uF 10% 10V 2 X5R 402 R3901 1 1 VCC 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22B7 IO 22A7 6C5 IO 22A7 IO 22A7 IO 22A7 IO C 22A7 IO 22A7 IO 22A7 IO 22A7 IO 22A7 IO 22A7 IO 22A7 IO 22A7 IO 22A7 IO 22B6 IO 22B6 IO 22B6 IO 22B6 IO 5% 1/16W MF-LF 402 VCCP U3900 BGA (2 OF 2) PCI_REQ_L F3 PCI_REQ64_L J13 PCI_RST_L D1 PCI_ACK64_L N12 26D2 IO IN OUT IO IO OUT OUT 26D2 PCI_RST_FW_L 22A6 PCI_SERR_L 22A6 PCI_STOP_L 22A6 PCI_TRDY_L R3903 1 IO 34D6 22A6 R3900 PCI_C_BE0_L PCI_C_BE1_L PCI_C_BE2_L PCI_C_BE3_L TP_FW_CTL<0> TP_FW_CTL<1> IO IO 38B6 IO 38B6 IO C IO IO 81D4 46D6 46C3 46B3 41C5 37D7 37D5 37A7 32C5 27C5 5D4 81A5 67C5 67C3 66C6 65D1 63B7 60C2 59C6 57D4 52B1 PP3V3_S3 IO R3904 OUT 38C3 38A3 1K 1 2 FW_LKON IO 1% 1/16W MF-LF 402 IO OUT 1 R3910 10K IN IN 5% 1/16W MF-LF 402 FW_LLC_PP1V8LDO_EN_L PP1V8_S3 1 C3910 1 FW_SCL FW_SDA 10% 16V X5R 402 2 5B2 5D4 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 31C5 32C6 64A6 64C1 67B6 67B8 C3911 0.1uF 2 10% 16V X5R 402 G_RST_L E4 2 5% 1/16W MF-LF 402 MFUNC A1 FW_MFUNC K10 J8 J9 J10 H10 H8 H9 H6 H7 46C7 37A5 G10 F9 F7 F8 E9 E10 F6 E7 E8 E6 D6 D7 C8 C7 GND Might use MFUNC as a GPIO 1 B 2 81D4 46D6 46C3 46B3 41C5 37D7 37D5 37C3 32C5 27C5 5D4 81A5 67C5 67C3 66C6 65D1 63B7 60C2 59C6 57D4 52B1 IN 5A7 38B6 SCL C3 SDA C4 G8 G9 22 PCI_RST_L THIS IS FROM ICH-7M TP_FW_DATA<0> TP_FW_DATA<1> REG_EN_L C2 REG18_0 G11 REG18_1 G12 G7 1 22A6 5B4 2 F10 G6 =FW_PCI_IDSEL IN 2 IO 0.1uF From PCI clock generator via 33 Ohms 100 5% 1/16W MF-LF 402 IO PCI_ACK64_L FW_DATA<2> FW_DATA<3> FW_DATA<4> PHY_D5 C11 38B6 FW_DATA<5> PHY_D6 B12 38B6 FW_DATA<6> PHY_D7 A11 38B6 FW_DATA<7> PHY_LCLK B7 38C5 CLKFW_PHY_LCLK FW_PHY_LKON PHY_LINKON B4 PHY_LPS A2 38C5 FW_LPS D4 38C5 FW_LREQ PHY_LREQ PHY_PCLK B6 38C3 CLKFW_LINK_PCLK PHY_PINT A3 38C3 FW_PINT G3 PCI_AD27 H1 PCI_AD28 F1 PCI_AD29 F2 PCI_AD30 G4 PCI_AD31 D3 PCI_CLK L2 PCI_IDSEL N3 PCI_PAR 26D2 PHY_D2 C13 PHY_D3 B9 PHY_D4 B10 H4 PCI_AD24 J3 PCI_AD25 H2 PCI_AD26 IO PCI_REQ64_L PHY_D0-D0 E13 PHY_D1-D1 E12 L1 PCI_AD21 J4 PCI_AD22 H3 PCI_AD23 PCI_CLK_FW FW_PCI_IDSEL PCI_PAR 26D2 PHY_CTL0-CTL0 F13 PHY_CTL1-CTL1 F12 K3 PCI_AD16 N1 PCI_AD17 L4 PCI_AD18 M2 PCI_AD19 M1 PCI_AD20 PCI_DEVSEL_L PCI_FRAME_L PCI_GNT3_L 26D2 22A7 INT_PIRQD_L 26D2 22A6 PCI_IRDY_L 26D2 22A6 PCI_PERR_L 22B5 PCI_PME_FW_L 22B6 6B5 6B3 PCI_REQ3_L 26D2 22A7 K9 PCI_AD13 K8 PCI_AD14 M5 PCI_AD15 K2 5% 1/16W MF-LF 402 26D2 22A6 PCI_SERR_L L7 PCI_STOP_L L5 PCI_TRDY_L J5 K5 2 22B6 6B5 6B3 N6 PCI_AD10 M6 PCI_AD11 M7 PCI_AD12 PCI_C_BE_L<0> PCI_C_BE_L<1> PCI_C_BE_L<2> PCI_C_BE_L<3> 2 PCI_PERR_L L6 PCI_PME_L F4 TSB83AA22AZAJ D 4.7K PCI_GNT_L E3 PCI_INTA_L B3 PCI_IRDY_L K4 CRITICAL K12 PCI_AD5 M9 PCI_AD6 N9 PCI_AD7 L8 PCI_AD8 M8 PCI_AD9 N8 M3 R3902 PCI_DEVSEL_L N2 PCI_FRAME_L L3 L12 PCI_AD0 N11 PCI_AD1 M11 PCI_AD2 N10 PCI_AD3 M10 PCI_AD4 PCI_AD<0> PCI_AD<1> PCI_AD<2> PCI_AD<3> PCI_AD<4> PCI_AD<5> PCI_AD<6> PCI_AD<7> PCI_AD<8> PCI_AD<9> PCI_AD<10> PCI_AD<11> PCI_AD<12> PCI_AD<13> PCI_AD<14> PCI_AD<15> PCI_AD<16> PCI_AD<17> PCI_AD<18> PCI_AD<19> PCI_AD<20> PCI_AD<21> PCI_AD<22> PCI_AD<23> PCI_AD<24> PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29> PCI_AD<30> PCI_AD<31> F11 E11 J11 J7 H11 J6 F5 D5 D8 D D9 E5 4.7K 6C3 1 R3980 1 R3990 1K 220 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 1 R3991 220 2 5% 1/16W MF-LF 402 FW_G_RST_L IN G_RST* is clamped to VCCP It must not be taken high when there’s no power on VCCP (OK if VCCP and VCC are aliased to the same rail) G_RST* assertion min 2ms B PP3V3_S3 Gated Platform Reset Option RC Reset Option 1 R3977 10K Q3970 2N7002 SOT23-LF 26B3 2 PLT_RST_BUF_L 3 S 5% 1/16W MF-LF R3879 2 402 1 FW_G_RST_L_R D 0 5% 1/16W MF-LF 402 G 2 46C7 37B2 1 1 IN SMC_RSTGATE_L 1 10K 2 A 2 SMC_RSTGATE_RC_L 5% 1/16W MF-LF 402 1 OUT C3977 1UF R3979 51D7 6C5 6C3 FW_G_RST_L 10% 10V X5R 402 FireWire Link (TSB83AA22) C3979 SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 0.001uF 2 NOTICE OF PROPRIETARY PROPERTY 10% 50V CERM 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 37 1 87 A 8 6 7 PP3V3_FWPHY_AVDD 44B8 44A8 43B8 42C4 38B5 6C6 6C5 6C3 5A4 1 1 D 1 1 C4001 1 C4010 1 C4002 C4004 1uF 10% 10V 10% 10V 1 1uF 10% 10V 10% 10V X5R 402 2 X5R 2 X5R 2 X5R 402 402 402 402 1 C4011 C4012 1 C4013 1uF 1uF 1uF 20% 16V CERM 402 10% 10V X5R 402 10% 10V X5R 402 10% 10V X5R 402 2 2 1 C4030 1uF 2 X5R 0.01uF 2 1 C4003 1uF 10% 10V 2 R4035 PP1V95_FWPHY 1 1uF 1 42C1 38B2 6C6 6C5 6C3 5A4 2 5% 1/16W MF-LF 402 1 5A4 VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.22 mm R4000 PP3V3_FWPHY 2 3 4 5 1 C4031 2 5A4 1 1 1uF 10% 10V X5R 402 2 PP1V95_FWPHY_PLLVDD D VOLTAGE=1.95V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.22 mm 5% 1/16W MF-LF 402 C4035 2.2uF 10% 6.3V 2 2 CERM1 603 C4014 1uF 10% 10V 2 X5R 402 R4020 2 5A4 PP3V3_FWPHY_PLLVDD 37C4 IN FW_A_DS FW_B_DS CLKFW_PHY_LCLK A6 DS0 B8 G13 DS1 LCLK FW_LPS N13 LPS 1 1K 37C4 IN 37C4 R4056 10K 5% 1/16W MF-LF 2 402 FW_LREQ K13 LREQ 2 IN 44B8 44A8 43B8 42C4 38D7 6C6 6C5 6C3 5A4 1 5% 1/16W MF-LF 402 PP3V3_FWPHY 5% 1/16W MF-LF 402 2 PCLK H13 PINT M13 CNA M12 LKON_DS2 L13 1 1 R4091 1K R4061 470 5% 1/16W MF-LF 2 402 2 1% 1/16W MF-LF 402 37C4 C CLKFW_LINK_PCLK OUT C6 C5 K6 K7 J12 H12 U3900 TSB83AA22AZAJ 37C4 FW_PINT OUT 38A3 37C3 FW_LKON IO IO DUAL PORT DEVICES ARE POWER CLASS 4 (’100’) SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’) IMPLEMENT 1K PULLUP OR PULLDOWN ON PORT PAGE TPA0P 44C7 44C5 44B4 IO TPA0N E2 44C7 44C5 FW_PORT2_TPA_P 44B4 FW_PORT2_TPA_N IO TPA1P J2 44D7 44C5 44B7 44B5 IO PD TPA1N J1 44D7 44C5 44B7 FW_PORT1_TPA_P 44B5 FW_PORT1_TPA_N IO TPB0P C1 44C7 44C5 44B4 TPB0N B1 44C7 44C5 PC0 M4 PC1 PC2 N5 FW_BMODE L9 BMODE FW_CPS A5 CPS 1MA (MAX) BUS HOLDERS R4055 1 390K 2 5% 1/16W MF-LF 402 IO IO IO IO IO B IO FW_DATA<2> 37C4 FW_DATA<3> 37C4 FW_DATA<4> 37C4 FW_DATA<5> 37C4 FW_DATA<6> 37C4 FW_DATA<7> 37C4 FW_PHY_RESET_L 44D7 44C5 44B7 44B5 IO D2 D3 TPB1N G1 44D7 44C5 44B7 FW_PORT1_TPB_P 44B5 FW_PORT1_TPB_N IO D4 D5 TPBIAS0 TPBIAS1 D2 44D7 K1 44D7 FW_A_TPBIAS FW_B_TPBIAS OUT C12 B13 D6 B11 D7 L10 RESET D13 C9 C10 1 RESET PULSE WHEN PHY FIRST RECEIVES POWER C4050 2 R0 R1 XI L11 N7 A12 A13 FW_TESTM FW_TESTW 2 6.34K 20% 6.3V X5R 402 1 4.7 PP1V8_FWPHY_OSC 2 VOLTAGE=1.83V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.20 mm 5% 1/16W MF-LF 402 OUT FW_R0 FW_R1 1 CRITICAL CLK98P304_FW_XI A9 B 1 1% 1/16W MF-LF 402 4 VCC 22 G4080 2 CLK98P304M_FW_XI_R C4080 0.22uF R4080 1 2 20% 6.3V X5R 402 98P3040MHZ 5% 1/16W MF-LF 402 A10 0.22uF PP1V95_FWPHY R4062 TESTM TESTW SE SM R4086 IO G2 B5 INTERNAL PULLUP PROVIDES IO TPB1P A4 CAPACITOR IN CONJUCTION WITH FW_PORT2_TPB_P 44B4 FW_PORT2_TPB_N 42C1 38D5 6C6 6C5 6C3 5A4 PLLGND PPBUS_S5_FW_FET NC E1 N4 K11 67C3 67C1 43D3 43B5 42C8 1K (1 OF 2) 1K 5% 1/16W MF-LF 402 2 R4040 R4090 1 BGA R40451 FW_B is BILINGUAL CRITICAL A8 FW_A is DS_ONLY PLLVDD_CORE 5% 1/16W MF-LF 402 2 A7 C PLLVDD_3P3 1K DVDD_CORE AVDD_3P3 402 R4042 1 DVDD_3P3 10% D12 1uF 2 10V X5R H5 C4021 G5 VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm 1 D11 1 5% 1/16W MF-LF 402 D10 1 SM 3 1 OUT TRI-ST/NC NC GND 2 FW_LKON 37C3 38C3 NO STUFF R4063 1 1K 1% 1/16W MF-LF 402 2 FireWire PHY (TSB83AA22) A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 38 1 87 A 8 6 7 2 3 4 5 1 PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6. MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.22MM SCHEME MATCHES DOC MVL100258-01 40D5 5A4 L4100 FERR-120-OHM-1.5A VOLTAGE=2.5V PP2V5_S3_ENET_AVDD 1 2 PP2V5_S3 5A4 63C3 63D3 63D4 67B6 67B8 0402-LF 1 C4100 1 1 0.1UF 1UF 2 C4101 10% 6.3V CERM 402 2 C4102 C4103 1 0.1UF 10% 16V X5R 402 2 1 0.1UF 10% 16V X5R 402 C4105 1 0.1UF 10% 16V X5R 402 2 C4104 2 1 C4106 0.001UF 10% 16V X5R 402 10% 50V CERM 402 2 1 C4107 0.001UF 0.1UF 10% 50V CERM 402 2 D 2 10% 16V X5R 402 D PLACE C4107 NEAR U4101 AVDD PP3V3_S3AC PP1V2_S3 5A4 39A5 39B4 39B5 39B8 39D6 41C4 67D1 67D3 67D3 39B8 39D8 5A4 39A5 39B4 39B5 41C4 67D1 PP3V3_S3AC 67D6 67D8 5A4 5D4 39A8 63B3 PLACE C4110 AND C4111 WITHIN 12 MIL OF U4101 PIN 49 AND 50 C4110 66C8 66C6 66B6 42A8 32B3 23C3 5C4 65B8 55C3 51C5 43C8 PM_SLP_S3_L VAUX_AVLBL 47 NC 11 VMAIN_AVLBL SWITCH_VCC NC 9 SWITCH_VAUX CRITICAL U4101 OUT 25 NC_ENET_CTRL25 6D4 NC_ENET_CTRL12 6D5 6D4 6D5 CTRL25 3 CTRL12 NC 59 NC 60 NC 62 NC 63 PCI EXPRESS ANALOG 46 TESTMODE VDD25 2 1 49 TX_N 50 RX_P RX_N 54 2 22D4 PCIE_A_D2R_P OUT 22D4 PCIE_A_D2R_N OUT C4111 C4112 0.1UF 0.1UF 402 X5R 10% 16V 402 PCIE_A_R2D_P PCIE_A_R2D_N 53 REFCLKP 55 34C5 34C3 33A4 REFCLKN 56 34C5 34C3 33A4 ENET_CLK100M_PCIE_P ENET_CLK100M_PCIE_N PCIE_WAKE_L 26B1 ENET_RST_L 6 48C3 23C8 5B1 5 1 1 2 22D4 2 22D4 IN C4113 IN 0.1UF PCIE_A_R2D_C_P PCIE_A_R2D_C_N IN IN PLACE C4113 AND C4112 WITHIN 12 MIL OF U2100 E27 AND E28 402 X5R 16V 10% OUT IN ENET_MDI_P<0> ENET_MDI_N<0> IO ENET_MDI_P<1> 40A7 ENET_MDI_N<1> IO IO 27 ENET_MDI_P<2> 40C4 ENET_MDI_N<2> 30 40C4 ENET_MDI_P<3> 40B4 ENET_MDI_N<3> IO 17 40D4 18 40C4 40B7 MDIP1 20 40C4 MDIN1 21 MDIP2 MDIN2 26 MDIP3 MDIN3 31 40C4 MEDIA LED LED_LINK1000* LINK* TSTPT TX_P MDIP0 MDIN0 LED_ACT* LED_LINK10/100* 1 PCIE_A_D2R_C_N 10% 16V X5R WAKE* PERST* RSET 29 PCIE_A_D2R_C_P 88E8053 HSDACP HSDACN 4 16 NO PULL-UP NEEDED 2 1% 1/16W MF-LF 402 4.87K R4102 ENET_RSET 1 OPTIONAL EXTERNAL LDO C OUT 24 NC 10% 16V X5R 402 64 19 22 OMIT QFN NC AVDDL0 28 32 51 AVDDL2 AVDDL1 52 AVDDL4 AVDDL3 57 AVDDL5 AVDD AVDDL6 1 23 8 VDDO_TTL1 VDDO_TTL0 40 45 VDDO_TTL2 LOM_DISABLE* 12 VDDO_TTL4 VDDO_TTL3 2 7 61 VDD0 13 VDD2 VDD1 33 39 44 VDD3 48 VDD5 VDD4 VDD6 58 ENET_LOM_DIS_L 10 39B7 VDD7 0.1UF VPD_CLK TEST ENET_VPD_CLK ENET_VPD_DATA 38 VPD_DATA 41 TEST PU_VDDO_TTL0 PU_VDDO_TTL1 42 SPI_DI 35 NC SPI_DO SPI_CLK 34 NC 37 NC SPI_CS 36 NC XTALI 15 XTALO 14 MAIN CLK C IO 40C4 TWSI SPI IO IO IO 39A2 39A2 ENET_PU_VDD_TTL0 39A6 ENET_PU_VDD_TTL1 39A6 43 ASF IS UNAVAILABLE ON 8053 1 INTERNAL PULL-UP CRITICAL ENET_XTALI ENET_XTALO 3 1. KEEP ENET_XTALI AND ENET_XTALO 1 2 1 R4106 R4105 1 1 R4104 1 R4103 1 R4120 R4119 1 49.9 49.9 49.9 49.9 49.9 49.9 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 2 2 2 2 2 2 1 R4118 49.9 R4117 49.9 2 1% 1/16W MF-LF 402 TRACE LENGTH <12MIL 65 THRML_PAD 4 2 ENET_MDI0 2. DO NOT ROUTE UNDER CRYSTAL ENET_MDI1 VOLTAGE=1.234V Y4101 ENET_MDI2 VOLTAGE=1.234V VOLTAGE=1.234V ENET_MDI3 VOLTAGE=1.234V SM-3.2X2.5MM Setting attribute VOLTAGE to arbitrary value to help constraint manager find correct topolgy 25.0000M 1 67D3 67D1 41C4 39D8 39D6 39B5 39B4 39A5 5A4 PP3V3_S3AC 2 C4150 1 C4151 1 C4116 1 C4115 1 C4117 27pF 27pF 0.001UF 0.001UF 0.001UF 5% 50V CERM 402 5% 50V CERM 402 10% 50V CERM 402 10% 50V CERM 402 10% 50V CERM 402 2 2 2 2 1 C4118 0.001UF 2 10% 50V CERM 402 R41011 B B 4.7K 5% 1/16W MF-LF 402 2 PLACE RESISTORS CLOSE TO U4101 39C8 PP3V3_S3AC 67D3 67D1 41C4 39D8 39D6 39B8 39B5 39A5 5A4 2 5% 1/16W MF-LF 402 2 39C6 ENET_PU_VDD_TTL0 39B6 ENET_PU_VDD_TTL1 5% 1/16W MF-LF 402 2 PLACE C4140 NEAR U4102 VCC 1 PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101 SCHEME MATCHES DOC MVL100258-01 10% 16V X5R 402 OMIT CRITICAL 8 VCC 3 E2 2 NC1 U4102 SDA 1 NC0 M24C08 SCL 7 WC* SO8 PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101 SCHEME MATCHES DOC MVL100258-01 PP1V2_S3 C4140 0.1UF 2 5 ENET_VPD_DATA 39C6 6 ENET_VPD_CLK 39C6 VSS PP3V3_S3AC 63B3 39D7 5D4 5A4 67D8 67D6 2 4.7K 5% 1/16W MF-LF 402 10K 100K 4.7K 5% 1/16W MF-LF 402 R4132 2 R4123 S PP3V3_S3AC R4131 1 G 1 1 2 ENET_LOWPWR_EN SOT23-LF R4130 10K 6D4 1 5% 1/16W MF-LF 402 2N7002 1 5A4 39A5 39B4 39B8 39D6 39D8 41C4 67D1 67D3 Q4100 R4122 D 1 ENET_LOM_DIS_L 3 39D8 39D6 39B8 39B5 39B4 5A4 67D3 67D1 41C4 4 1 1 C4126 1 0.1UF A 2 10% 16V X5R 402 C4127 1 0.1UF 2 10% 16V X5R 402 C4128 1 0.1UF 2 10% 16V X5R 402 C4129 1 0.1UF 2 10% 16V X5R 402 C4130 1 0.1UF 2 10% 16V X5R 402 C4131 1 0.001UF 2 10% 50V CERM 402 C4132 1 0.001UF 2 10% 50V CERM 402 C4133 1 0.001UF 2 10% 50V CERM 402 C4134 1 0.001UF 2 C4135 1 0.1UF 10% 50V CERM 402 2 10% 16V X5R 402 C4136 1 0.1UF 2 10% 16V X5R 402 C4137 1 0.1UF 2 10% 16V X5R 402 C4138 10% 50V CERM 402 ETHERNET CONTROLLER 0.001UF 0.001UF 2 C4139 2 10% 50V CERM 402 SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 39 1 87 A 8 6 7 2 3 4 5 1 NET_TYPE ELECTRICAL_CONSTRAINT_SET PROVIDED BY ETHERNET PHY D SPACING PHYSICAL ENETCONN ENET_100D ENETCONN ENET_100D ENETCONN ENET_100D ENETCONN ENET_100D ENETCONN ENET_100D ENETCONN ENET_100D ENETCONN ENET_100D ENETCONN ENET_100D ENETCONN_P<0> ENETCONN_N<0> ENETCONN_P<1> ENETCONN_N<1> ENETCONN_P<2> ENETCONN_N<2> ENETCONN_P<3> ENETCONN_N<3> 40D3 40C3 40C3 40C3 40C3 40C3 40C3 39D5 5A4 40B3 IN PP2V5_S3_ENET_AVDD Place one cap at each pin of transformer D Page Notes 1 C4200 1 1uF Power aliases required by this page: - =PP2V5_ENET - =GND_CHASSIS_ENET 2 Signal aliases required by this page: (NONE) C4201 C4202 1 1uF 10% 6.3V CERM 402 2 1 1uF 10% 6.3V CERM 402 1uF 10% 6.3V CERM 402 2 C4203 2 10% 6.3V CERM 402 1000BT-824-00275 CRITICAL T4200 BOM options provided by this page: (NONE) 39C3 IO XFR-SM 1 ENET_MDI_P<0> 16 3 14 2 15 40D7 ENETCONN_P<0> ENET_CTAP0 IO ENET_MDI_N<0> 5 39C3 IO ENET_MDI_P<1> NC1 NC2 LINE SIDE 4 CHIP SIDE CRITICAL 40B7 39C3 40D7 J4200 ENETCONN_N<0> JM36113-P2054-7F 13 NC4 NC3 11 F-RT-TH-RJ45 12 9 7 10 6 11 8 9 40D7 ENETCONN_P<1> ENET_CTAP1 1 2 40A7 39C3 IO ENET_MDI_N<1> Transformers should be mirrored on opposite sides of the board ENETCONN_N<1> 3 4 SYM_VER2 1000BT-824-00275 5 6 CRITICAL T4201 C 40D7 39C3 IO XFR-SM 1 ENET_MDI_P<2> 16 3 40D7 14 7 ENETCONN_P<2> C 8 ENET_CTAP2 10 12 IO 2 ENET_MDI_N<2> 5 39C3 IO ENET_MDI_P<3> 15 NC1 NC2 LINE SIDE 4 CHIP SIDE 39C3 40D7 ENETCONN_N<2> 514-0277 13 NC4 NC3 12 7 10 6 11 8 9 40D7 Short shielded RJ-45 ENETCONN_P<3> NO STUFF ENET_CTAP3 R4210 39C3 IO ENET_MDI_N<3> 40D7 0 ENETCONN_N<3> 1 SYM_VER2 R4200 1 R4201 1 75 75 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 2 1 2 R4202 1 75 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 82D5 82C6 66B6 66B5 66B1 65D6 65B3 62A6 61D8 61A5 49C4 49B5 27D5 27D3 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 36D6 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 60D4 60C7 58C7 58C4 57B6 54D4 54B5 52D3 49C7 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3 C4220 R4220 68PF 1 2 ED_MDIN0_C 1 2.4K 1 1 R4223 392K 100K 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 2 2 2 2 2 2 EDET_MDIN_AMP EDET_ACT 2 ED_MDIN1_C 1 2.4K 6 ED_MDIN_R 2 LMC7211 MMDT3904XF SM-LF 5% 1/16W MF-LF 402 1 10K MMDT3904XF 5% 1/16W MF-LF SOT-363-LF 1 LAN_ENERGY_DET 23C3 V- R4226 Q4220 5 SOT-363-LF 3 5 3 Q4220 2 4 NO STUFF 1 C4222 100pF Setting attribute VOLTAGE to arbitrary value to help constraint manager find correct topolgy PLACE C4220 & C4221 U4200 1 VOLTAGE=1.234V 5% 50V CERM 402-1 4 V+ R4221 68PF 1 10% 16V X5R 402 2 5% 1/16W MF-LF 402 C4221 ENET_MDI_N<1> OUT 0.1uF R4224 3.3K 1% 1/16W MF-LF 402 EDET_REF 40C4 39C3 GND_CHASSIS_ENET C4223 1 R4228 470K VOLTAGE=1.234V 5% 50V CERM 402-1 2 44C1 6A8 6A6 10%44A1 3KV CERM 1808 B 1 R4227 ENET_MDI_N<0> 1 PP3V3_S0 1 40C4 39C3 C4204 100pF MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm LAN ENERGY DETECT Place close to connector R4203 75 ENET_CTAP_COMMON B 2 5% 1/16W MF-LF 402 2 5% 50V CERM 402 2 402 1 R4225 51.1K 1% 1/16W MF-LF 2 402 NEAR ENET_MDI_N<0/1> Ethernet Connector A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 40 1 87 A 8 6 7 2 3 4 5 1 D D Yukon Power Control Allows powering Yukon down during battery sleep to save power Q4300 FDG6332C_NL SC70-6 81D4 46D6 46C3 46B3 37D7 37D5 37C3 37A7 32C5 27C5 5D4 81A5 67C5 67C3 66C6 65D1 63B7 60C2 59C6 57D4 52B1 P-CHN PP3V3_S3 4 PP3V3_S3AC D S 5A4 39A5 39B4 39B5 39B8 39D6 39D8 67D1 67D3 3 G 5 PPVIN_S3_P2V5S3_SVIN 1 63D6 R4304 100K 2 5% 1/16W MF-LF 402 PM_SLP_S3BATT_L 41C4 63D8 PM_SLP_S3BATT_L 63D8 41C3 MAKE_BASE=TRUE 3 D C Q4304 C 2N7002 1 G SOT23-LF S 2 64D7 64A6 62D7 61D7 61D4 55D3 43D8 42B8 5C4 5A1 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 PPBUS_G3H 1 P1V2S3_RUNSS R4302 2 3 5% 1/16W MF-LF 402 D Q4302 2N7002 PM_SLP_S3BATT 5C4 5D7 63B7 1.2V enable has pull-up to 3.3V 470K 1 G SOT23-LF S 2 6 D PM_SLP_S4_L 2 G 1 0 2 FDG6332C_NL SC70-6 1 R4300 FWPWR_EN_L Q4300 S ENETPWR_S3AC 43C7 N-CHN 66B8 66A6 64C8 51C5 48C3 47C7 23C3 6A2 6A1 5C4 5C1 FWPWR_EN_L_OR_GND ENETPWR_S3 5% 1/16W MF-LF 402 1 R4301 0 B 2 5% 1/16W MF-LF 402 B When ENETPWR_S3AC BOMOPTION is active: State PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L S0 AC 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON) S0 Batt 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON) S3 AC 0V 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON) PBUS 3.3V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF) 0V 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF) S5 Batt PBUS 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF) G3H Batt PBUS 0V PBUS (3.3V OFF) 0V 0V (2.5V OFF) 0V (1.2V OFF) S3 Batt S5 AC FWPWR_EN_L P2V5S3_EN P1V2S3_RUNSS When ENETPWR_S3 BOMOPTION is active: State A PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN P1V2S3_RUNSS S0 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON) S3 3.3V 0V (3.3V ON) 3.3V 3.3V (2.5V ON) 3.3V (1.2V ON) S5 G3H PM_SLP_S4_L 0V 0V PBUS (3.3V OFF) PBUS (3.3V OFF) 0V 0V 0V (2.5V OFF) 0V 0V (2.5V OFF) 0V Yukon Power Control SYNC_MASTER=M59_MLB (1.2V OFF) SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY (1.2V OFF) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 41 1 87 A 8 6 7 2 3 4 5 1 D D 3.3V Supply for FWPHY 1.95V Supply for FW PHY D4400 SC-59 67C3 67C1 43D3 43B5 38B7 PPBUS_S5_FW_FET 1 PPBU_S0_FW 2 3 PP5VR33V_FWPHY3V3 42B6 SMD20E40C-X-F C 44B8 44A8 43B8 42C4 38D7 38B5 6C6 6C5 6C3 5A4 CRITICAL PP3V3_FWPHY C4400 3 VIN 1 4.7UF 10% 50V X7R-CERM 1206 C4405 6 BOOST U4400 2 LT3470 165MA MAX LOAD 1 NC 2 SW SHDN* CRITICAL BIAS NC FB SON 6 IN 4 EN CRITICAL 2 5 7 FWPHY3V3_SW MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE 33uH PP3V3_FWPHY 1 NC 5A4 6C3 6C5 6C6 38B5 38D7 42C4 43B8 44A8 44B8 2 Vout = 3.316 CDPH4D19F-SM 200mA max output 8R4410 (Switcher limit) 1 GND 4 OUT 1 NR 2 FWPHY_CORE_NR C L4400 TSOT23-8 1 5A4 6C3 6C5 6C6 38B2 38D5 TPS799195 0.22uF 20% 6.3V X5R 402 PP1V95_FWPHY U4420 FWPHY3V3_BOOST C4410 1 22pF 5% 50V CERM 402 1% 1/16W MF-LF 2 2 402 1 THRML GND PAD 3 7 1 C4420 1 C4421 2 10% 16V CERM 402 1 C4422 2.2uF 0.01uF 1uF 10% 6.3V CERM 402 324K 5 NC 2 2 20% 4V X5R 402 C4401 22UF FWPHY3V3_FB R4411 1 20% 6.3V 2 X5R 805 196K 1% 1/16W MF-LF 2 402 Vout = 1.25V * (1 + Ra / Rb) PBUS S0 FET Q4450 IRLML6302PBF B B R4450 C4450 470K 1 0.0022UF 5% 1/16W MF-LF 402 2 10% 50V CERM 2 402 PPBU_S0_FW 42C8 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V 1 1 G S PPBUS_G3H 3 79B7 71D7 69C1 68D5 67C3 61D4 55D3 43D8 41C6 5C4 5A1 67C1 65D6 65B7 64D7 64A6 62D7 61D7 D 2 SOT23 PPBU_S0_FW_EN_DIV 1 R4451 330K 5% 1/16W MF-LF 402 2 PPBU_S0_FW_EN 3 Q4451 D 2N7002 PM_SLP_S3_L 55C3 51C5 43C8 39C8 32B3 23C3 5C4 66C8 66C6 66B6 65B8 1 G SOT23-LF S 2 FW PHY Power Supply A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 42 1 87 A 8 6 7 2 3 4 5 1 Page Notes Power aliases required by this page: - =PPBUS_S0_FWPWRSW (system supply for bus power) - =PP3V3_S0_FWPORTPWRSW Signal aliases required by this page: - =FWPWR_PWRON (see related text note below) Port Power Switch BOM options provided by this page: (NONE) CRITICAL Q4565 CRITICAL D PPBUS_G3H CRITICAL NDS9407 F4565 SMB 1.5A-24V 64D7 64A6 62D7 61D7 61D4 55D3 42B8 41C6 5C4 5A1 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 1 1 8 2 470K 2 6 PPBUS_S5_FW_FET 2 38B7 42C8 43B5 67C1 67C3 B340XF 1 1 C4565 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V 7 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MINISMDC R4565 1 PPBUS_S5_FW_FET_D 3 PPBUS_S5_FWPWRSW_F D D4565 SOI-LF 5 0.01uF 5% 1/16W MF-LF 2 402 20% 16V CERM 402 4 2 FWPWR_EN_L_DIV MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm 1 R4566 330K 2 5% 1/16W MF-LF 402 FWPWR_EN_L 41B6 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm 3 Enables port power when machine is running or on AC. D Q4560 2N7002DW-X-F 68A6 52A2 51D5 5 SMC_ADAPTER_EN SOT-363 G 6 S D Q4560 4 66B6 65B8 55C3 51C5 42A8 39C8 32B3 23C3 5C4 66C8 66C6 2N7002DW-X-F 2 PM_SLP_S3_L G SOT-363 S 1 C C Current Limit/Active Late-VG Protection Late-VG Event Detection Q4520 SI2318DS CRITICAL 67C3 67C1 43D3 42C8 38B7 PPBUS_S5_FW_FET 44D5 44B5 44A5 SOT23-3 R4520 1 0.020 PPFW_PORTA_ISENSE 2 D S PPFW_PORTA_VP_UF 6C3 6C5 44D3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V G CRITICAL U4520 B 2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V 1% 0.25W MF 805 PP2V4_FWLATEVG 3 1 MAX5944 PP3V3_FWPHY B SOIC 42C4 38D7 38B5 6C6 6C5 6C3 5A4 44B8 44A8 FW_PORT_FAULT_PU 1 1 10K R4505 1 2 5% 1/16W MF-LF 402 PP2V4_FWLATEVG_RC 4 MIN_LINE_WIDTH=0.1 mm MIN_NECK_WIDTH=0.1 mm V+ SM-LF 1 3 5% 1/16W MF-LF 402 1 1% 1/16W MF-LF 402 LATEVG_EVENT_L V- 2 1 MBR0540XXG C4501 5% 50V CERM 402 INB 10 16 OUTA 13 GATE2A GATE1A 14 ONB SENSEB OUTB 3 FAULTA_L 6 11 GATE2B GATE1B FAULTB_L FW_PORT_FAULT_L 1% 1/16W MF-LF 402 2 FW_PORTA_PWRCTRL NC 5 7 FW_PORTB_PWRCTRL NC GND C4509 C4520 10% 10V CERM-X5R 603 1 1 2 2 1uF 10% 35V X7R 805 C4525 1uF 10% 35V X7R 805 1 CRITICAL G R4525 1 R4500 200K 15 8 FW_PORTPWR_EN 1 2 1 ONA 9 SENSEA 0.33uF 100pF 2 2 5% 1/16W MF-LF 402 SOD-123 1 80.6K ONQ1 2 D4500 5 R4506 2 4 R4529 100K R4509 2.0M 2 U4500 LMC7211 2 FWLATEGV_3V_REF 1 1 20% 10V CERM 402 INA 12 1% 1/16W MF-LF 402 2 2 10K C4500 0.1UF R4501 1 FWLATEVG_3V_REF: 2.95V when port power is on 2.81V when port power is off 0.020 2 1% 0.25W MF 805 PPFW_PORTB_ISENSE 3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V D S 2 PPFW_PORTB_VP_UF 6C3 6C5 44B3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V SOT23-3 SI2318DS Q4525 Current Limits 0.020 0.025 0.030 0.033 A ohm ohm ohm ohm => => => => 2.4A 2A 1.66A (Ideal) 1.5A FireWire Port Power SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY MAX5944 current limiter trips if integrator (counter) reaches 16. A new sample (taken every 125 us) is weighted as +1 if over the limit (at any point during the period) and -1/128 if under the limit. As a result, the device tends to trip easily on devices that produce periodic current spikes. Current limit has been set higher to compensate. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 43 1 87 A 8 6 7 2 3 4 5 1 NET_TYPE ELECTRICAL_CONSTRAINT_SET PROVIDED BY PHY PAGE D SPACING PHYSICAL FW FW_110D FW FW_110D FW FW_110D FW FW_110D FW FW_110D FW FW_110D FW FW_110D FW FW_110D FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N FW_PORT2_TPA_FL_P FW_PORT2_TPA_FL_N FW_PORT2_TPB_FL_P FW_PORT2_TPB_FL_N AREF needs to be isolated from all local grounds per 1394b spec 38B3 44B5 44B7 44C5 38B3 44B5 44B7 44C5 Cable Power 38B3 44B5 44B7 44C5 When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue) 38B3 44B5 44B7 44C5 44B2 44B2 44B2 FERR-250-OHM 1 1 44B2 Page Notes Power aliases required by this page: - =PPFW_PORT1 - =PP3V3_S5_FWLATEVG - =GND_CHASSIS_FW_PORT1 44B5 44A5 43B8 PPFW_PORT1_VP MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V C4624 0.001uF PP2V4_FWLATEVG DP4620 2 BAV99DW-X-F C4621 10% 50V X7R 402 Termination 20% 50V CERM 402 D SOT-363 1 5 0.01uF PORT 1 BILINGUAL Note:Trace PPFW_PORT1_VP should handle up to 5A 3 2 4 DP4620 BAV99DW-X-F Place close to FireWire PHY C4620 CRITICAL SOT-363 1 2 J4620 0.01uF TI PHYs require 1uF even though 38B3 FW_B_TPBIAS 38B3 FW_A_TPBIAS 2 SM "Snapback" & "Late VG" Protection BREF should be hard-connected to logic ground for speed signaling and connection detection currents per 1394b V1.33 Signal aliases required by this page: (NONE) NOTE: This page is expected to contain the necessary aliases to map the FireWire TPA/TPB pairs to their appropriate connectors and/or to properly terminate unused signals. L4620 43B2 6C5 6C3 PPFW_PORTA_VP_UF 10% 50V X7R 402 FW spec calls out 0.33uF 1394B-UG31903 6 2 F-RT-SM1 10 1 1 C4650 1 C4660 1uF BOM options provided by this page: (NONE) 44D7 44B7 44B5 38B3 FW_PORT1_TPB_N 1uF 10% 6.3V CERM 402 2 10% 6.3V CERM 402 2 (FW_PORT1_BREF) (PPFW_PORT1_VP) NC (GND_FW_PORT1_VG) VOLTAGE=1.234V VOLTAGE=1.234V 44D7 44B7 44B5 38B3 FW_PORT1_TPA_N FW_PORT1_AREF 1OMIT 1OMIT L4660 L4661 0 44D7 44B7 44B5 38B3 FW_PORT1_TPA_P 0 5% 1/16W MF-LF 1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03) DP4621 5% 1/16W MF-LF 2 402 C4629 56.2 1 56.2 1% 1/16W MF-LF 2 402 R4660 10% 50V X7R 402 56.2 1% 1/16W MF-LF 2 402 1% 1/16W MF-LF 402 2 SOT-363 1 VP 7 NC 6 VG 3 TPA- 5 TPA 4 TPA+ INPUT FW_PORT2_TPA_P FW_PORT2_TPA_P 44C5 44B4 38B3 FW_PORT2_TPA_N FW_PORT2_TPA_N 44C5 44B4 38B3 FW_PORT2_TPB_P FW_PORT2_TPB_P 1 514S0133 0.01uF 2 20% 50V CERM 603 Place C4629 close to pin 5 of connector 2 C 5 1 2 3 C4623 1 10% 50V X7R 402 38B3 44B4 44C7 MAKE_BASE=TRUE NO STUFF R4629 1 1M 0.01uF 44C5 44B4 38B3 10% 50V X7R 603-1 BAV99DW-X-F 1 0.01uF R4661 1 56.2 1% 1/16W MF-LF 402 2 C4622 VOLTAGE=1.234V VOLTAGE=1.234V R4651 1 R4650 6 FW_B_TPA_L_N C4625 1 0.1uF DP4621 1 OUTPUT TPB+ 11 SOT-363 2 C TPB 8 BAV99DW-X-F 2 402 FW_B_TPA_L_P TPB- 9 2 44D7 44B7 44B5 38B3 FW_PORT1_TPB_P Setting attribute VOLTAGE to arbitrary value to help constraint manager find correct topolgy NOTE: FireWire TPA/TPB pairs are NOT constrained on this page. It is assumed that FireWire PHY page will provide the appropriate constraints to apply to entire TPA/TPB XNets. 1 4 2 2 C4627 C4626 1 0.01uF 0.01uF 5% 1/16W MF-LF 402 2 20% 16V CERM 402 20% 16V CERM 402 2 GND_CHASSIS_ENET 38B3 44B4 44C7 6A6 6A8 40B2 44A1 MAKE_BASE=TRUE 38B3 44B4 44C7 MAKE_BASE=TRUE 44C5 44B4 38B3 FW_PORT2_TPB_N FW_PORT2_TPB_N 44D7 44C5 44B5 38B3 FW_PORT1_TPA_P FW_PORT1_TPA_P 44D7 44C5 44B5 38B3 FW_PORT1_TPA_N FW_PORT1_TPA_N 44D7 44C5 44B5 38B3 FW_PORT1_TPB_P FW_PORT1_TPB_P 38B3 44B4 44C7 MAKE_BASE=TRUE 38B3 44B7 44C5 44D7 MAKE_BASE=TRUE 38B3 44B7 44C5 44D7 Cable Power MAKE_BASE=TRUE 43A2 6C5 6C3 PPFW_PORTB_VP_UF "Snapback" & "Late VG" Protection 38B3 44B7 44C5 44D7 L4630 MAKE_BASE=TRUE 44D7 44C5 44B5 38B3 FW_PORT1_TPB_N FW_PORT1_TPB_N 38B3 44B7 44C5 44D7 43B8 44D5 44A5 MAKE_BASE=TRUE 44B8 44A8 43B8 42C4 38D7 38B5 6C6 6C5 6C3 5A4 PP3V3_FWPHY FERR-250-OHM PP2V4_FWLATEVG 1 R4652 R4653 56.2 1 1 56.2 1% 1/16W MF-LF 2 402 R4662 R4663 56.2 1% 1/16W MF-LF 402 2 1 DP4630 BAV99DW-X-F 56.2 1% 1/16W MF-LF 2 402 DP4630 1% 1/16W MF-LF 402 2 C4630 FW_B_TPB_L_N FW_B_TPB_L_P VOLTAGE=1.234V VOLTAGE=1.234V 10% 50V X7R 402 38D7 38B5 6C6 6C5 6C3 44B8 44A8 43B8 42C4 PP3V3_FWPHY C4631 2 10% 50V X7R 402 6 1OMIT L4663 0 0 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 0.001uF 5 20% 50V CERM 402 2 PORT 2 1394A 3 2 4 1OMIT L4662 B 2 FW_PORT2_TPA_P 1 38B3 FW_PORT2_TPA_N 2 44C7 44C5 38B3 SYM_VER-2 FW_PORT1_TPB_C VOLTAGE=1.234V VOLTAGE=1.234V J4630 44C7 44C5 44C7 44C5 R4654 1 C4654 4.99K 220pF Note: The peaking inductors were changed to resistors to allow placement in an area restricted by DFM rules for only Rs and Cs 2 1 1% 1/16W MF-LF 402 5% 25V CERM 402 C4664 2 2 1394A 1210-4SM1 90-OHM-100MA 1 38B3 FW_PORT2_TPB_P SYM_VER-2 4 F-RT-TH-LF 44D7 44D7 R4664 1 1% 1/16W MF-LF 402 5% 25V CERM 402 FW_PORT2_TPA_FL_P 6 FW_PORT2_TPA_FL_N 5 44D7 4.99K 220pF 44C7 44C5 38B3 2 FW_PORT2_TPB_N 3 44D7 1210-4SM1 90-OHM-100MA 2 DP4631 DP4631 BAV99DW-X-F BAV99DW-X-F SOT-363 FL4631 CRITICAL 4 FW_PORT2_TPB_FL_P 3 FW_PORT2_TPB_FL_N 1 (PPFW_PORT2_VP) 5 QTY 152S0414 4 DESCRIPTION REFERENCE DES IND,18nH-15mA,0402 L4660,L4661,L4662,L4663 CRITICAL BOM OPTION 10% 50V X7R 402 (TPA-) TPI (TPB+) TPI# (TPB-) VGND 514-0255 8 9 10 3 C4633 1 0.01uF CRITICAL (TPA+) TPO# (GND_FW_PORT2_VG) 7 C4632 TPO VP 2 SOT-363 2 6 PART NUMBER B CRITICAL FL4630 FW_PORT2_TPB_C 4 3 CRITICAL 1 PPFW_PORT2_VP MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V C4634 SOT-363 1 0.01uF 2 1 BAV99DW-X-F SOT-363 1 0.01uF 1 5A4 PP3V3_FWPHY 2 SM 1 1 0.01uF 1 10% 50V X7R 402 2 1 4 2 2 C4635 C4636 0.01uF 0.01uF 20% 50V CERM 603 20% 16V CERM 402 1 2 GND_CHASSIS_USB 47B2 6A6 6A8 44A3 GND_CHASSIS_ENET 44C1 6A6 6A8 40B2 Late-VG Protection Power FireWire Ports R4699 A 44B8 43B8 42C4 38D7 38B5 6C6 6C5 6C3 5A4 PP3V3_FWPHY R4690 1 332 PP2V4_FWLATEVG 1% 1/16W MF-LF 402 PP2V4_FWLATEVG needs to be biased to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin R4690 should be 390 Ohms max for a 3.3V rail 1 43B8 44B5 44D5 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.4V 2 CRITICAL 3 C4691 1 D4690 0.01UF 10% 50V X7R 402 0 5% 1/16W MF-LF 402 ESD and late-VG rail for snap-back diodes (Common to all ports) SYNC_MASTER=M59_MLB 2 GND_CHASSIS_USB THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE MMBZ5227B 2 SYNC_DATE=06/27/2006 NOTICE OF PROPRIETARY PROPERTY 6A6 6A8 44A1 47B2 II NOT TO REPRODUCE OR COPY IT SOT23 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 1 SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 44 1 87 A 8 7 6 2 3 4 5 1 D D Camera Connector C PP5V_S3 L4930 C 5B2 5D4 52B8 62A2 67B1 67B3 81C4 81C6 FERR-220-OHM 1 5B2 79A6 79A5 45B5 6A8 6A6 5B2 1 PP5V_S3_CAMERA_F VOLTAGE=5V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm GND_CHASSIS_INVERTER 2 0.01UF 10% 50V 2 X7R 402 0402 NO STUFF C4931 CRITICAL 20% 50V CERM 402 CAMERA-M1-CUS Connector shield F-RT-SM 7 1 Twin-Ax Pair 1 (40 AWG) Twin-Ax Pair 2 (40 AWG) Standard wires (28 AWG) Connector shield 2 3 4 1 CRITICAL 0.001uF J4931 C4932 FL4935 90-OHM-100MA 1210-4SM1 2 SYM_VER-1 USB2_CAMERA_N_F 5A7 USB2_CAMERA_P_F 1 22C2 6D3 6D2 6D1 4 5B2 USB2_CAMERA_N IO 2 22C2 6D3 6D2 6D1 3 5B2 USB2_CAMERA_P IO 5A7 NC NC 5 CRITICAL L4931 6 FERR-220-OHM-2A 79A6 79A5 45C5 45B5 6A8 6A6 5B2 8 GND_CHASSIS_INVERTER 1 2 0603 518S0371 CRITICAL B B L4950 FERR-220-OHM-2A 79A6 79A5 45C5 45B5 6A8 6A6 5B2 GND_CHASSIS_INVERTER 1 2 0603 Camera Connector A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 45 1 87 A 8 6 7 PP1V8_USB_HUB_INTERNAL_VDD18 3G 81D4 46C3 46B3 41C5 37D7 37D5 37C3 37A7 32C5 27C5 5D4 81A5 67C5 67C3 66C6 65D1 63B7 60C2 59C6 57D4 52B1 1 C5005 0.1UF 0.1UF 20% 10V CERM 402 20% 10V CERM 402 2 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V 3G 3G 3G C5000 1 1 C5012 2 1 1 2 2 0.1UF 20% 6.3V CERM 603 D 3G C5008 4.7UF 2 20% 10V CERM 402 C5010 4.7UF 20% 6.3V CERM 603 PP3V3_S3 3G 3G C5004 0.1UF 20% 10V CERM 402 20% 10V CERM 402 2 1 1 C5011 2 2 20% 10V CERM 402 2 5% 1/16W MF-LF 402 3G ATEST/REG_EN MISC SELF_PWR 3G R5001 1M USB_HUB_G_RST_L 3G 1 USB_HUB_XTAL_OUT_R Y5000 SM-2 24.000MHZ-12PF-60PPM 197S0162 CLKIN_EN R5006 3G CRITICAL 1 RESET* 2 1% 1/16W MF-LF 402 3 0 USB_HUB_XTAL_IN USB_HUB_XTAL_OUT 2 5% 1/16W 27D7 MF-LF 23D5 40227C6 27D6 5B1 27B6 81C3 48B3 33B6 29A6 28A6 27D8 U5000 QFN XTAL1/CLKIN XTAL2 SMBUS_SB_SDA SMBUS_SB_SCL SDA/SMBDATA SCL/SMBCLK/CFG_SEL0 2 4 3G 1 2 CFG_SEL1 SERIAL PORT 3G C5001 1 C5002 12PF 12PF 5% 50V CERM 402 5% 50V CERM 402 2 1 VSS C5013 4.7UF 2 2 1 20% 10V CERM 402 C5014 4.7UF 2 2 20% 6.3V CERM 603 20% 6.3V CERM 603 USB_IR_P USB_IR_N USBDP1 USBDN1 TP_USB2_3G_P TP_USB2_3G_N USBDP2 USBDN2 C 46B5 81C6 46A5 81C6 6B2 6B3 6B2 6B3 TP_USB_HUB_ENUM PP3V3_S3 5D4 PRTPWR PRTPWR_POL Test point should be on TOP side. 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81A5 81D4 PRTPWR_POL High = PRTPWR goes high whenever USB HUB is enumerated GR1/NON_REM0 GR2/NON_REM1 NC NC OCS* RBIAS NC UPS USB2.0 REG_EN High = internal 1.8V TEST USB2502 NC 2-PORT USB2.0 CRITICAL C 1 VDD33CR VDDA33 0 VDDA33PLL 28 3G FW_G_RST_L 1 0.1UF 20% 6.3V CERM 603 R5005 1 3G C5006 4.7UF 1 0.1UF VDD18PLL 1 0.1UF 3G C5007 3G 18 C5003 3G VDD18 3G 37B2 37A5 1 PP1V8_USB_HUB_INTERNAL_VDD18PLL MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V D 2 3 4 5 R4912 should be placed as close as possible to U4900.36 and isolated by 0.9mm from other signals. 3G USB_HUB_RBIAS 1 PP3V3_S3 VBUS_DET USB_HUB_P USB_HUB_N USBDP0 USBDN0 R5012 52B1 57D4 59C6 60C2 63B7 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46C3 46D6 65D1 66C6 67C3 67C5 81A5 81D4 12K 2 5% 1/16W MF-LF 402 6C1 6C2 6C3 22C2 46B7 6C1 6C2 6C3 22C2 46A7 THRML PAD 311S0279 B B NO_3G R5004 1 46B3 22C2 6C3 6C2 6C1 46B3 22C2 6C3 6C2 6C1 0 2 5% 1/16W MF-LF 402 USB_HUB_P USB_HUB_N USB_IR_P USB_IR_N NO_3G 46C3 81C6 46C3 81C6 R5003 1 0 2 5% 1/16W MF-LF 402 Internal USB Hub A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 46 1 87 A 8 6 7 2 3 4 5 1 D D Port Power Switch Right USB Port CRITICAL CRITICAL U5290 65D6 65B7 64C8 62C8 62B6 62B2 62A4 52B5 25C8 5D4 71D7 67C3 67C1 67B1 66D8 66B8 C L5205 TPS2051 PP5V_S5 PP5V_S3_RTUSB_ILIM MSOP 2 IN OUT 3 IN OUT 7 OUT 66B8 66A6 64C8 51C5 48C3 41B6 23C3 6A2 6A1 5C4 5C1 PM_SLP_S4_L 4 EN GND 1 C5290 1 1 10uF 20% 6.3V CERM 805-1 2 2 C5291 FERR-220-OHM-2A OC* THRML MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V 8 1 2 C PP5V_S3_RTUSB_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V 0603 C5205 1 0.01uF 6 5 22D8 22C4 6D3 6D2 6D1 20% 16V CERM 402 CRITICAL RTUSB_OC_L L5200 OUT J5200 UAR2X 2 F-RT-SM-USB-RGT1 5 6 90-OHM-100MA 1210-4SM1 PAD CRITICAL SYM_VER-1 USB2_RT_MUXED_N 9 C5295 0.1UF 10uF 20% 10V CERM 402 20% 6.3V CERM 805-1 1 1 4 1 USB2_RT_MUXED_P 20% 2 6.3V POLY B2 2 3 VBUS 2 D- USB2_RT_F_N USB2_RT_F_P C5296 100UF 2 1 3 D+ 4 GND RTUSB_ESD D5200 2 1 7 C5206 RCLAMP0502B 1 8 0.01uF 20% 16V CERM 402 SC-75 CRITICAL CRITICAL 3 2 514S0115 L5206 FERR-220-OHM-2A 1 USB/SMC Debug Mux 81D4 69C8 52B7 52B5 52B1 51D4 51D3 51C2 35B7 27C3 26D6 5D2 69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52D7 GND_CHASSIS_USB 6A6 6A8 44A1 44A3 GND_RTUSB MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=0V Place L5200, L5205 and L5206 across moat PP3V42_G3H C5250 B 2 0603 1 1 R5250 0.1UF 20% 10V CERM 2 402 B 8 2 10K 5% 1/16W MF-LF 2 402 VDD IO IO IO IO 22C2 6D3 6D2 6D1 22C2 6D3 6D2 6D1 SMC_TX_L SMC_RX_L 12 11 0I0 1I0 USB2_RT_N USB2_RT_P 10 9 0I1 1I1 U5250 Y0 Y1 TDFN SEL CRITICAL PI3USB10 13 THRM_PAD GND 3 4 USB_DEBUGPRT_EN_L 6 52B3 SEL=0 Choose SMC SEL=1 Choose USB 7 5 1 53B4 52B3 52B2 51C7 5C2 External USB Connector A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 47 1 87 A 8 7 6 3 4 5 2 1 Left I/O Board Connector D D CRITICAL J5500 QT510806-L111-7F F-ST-SM NC 22C2 6C3 6C2 6C1 5B1 22C2 6C3 6C2 6C1 5B1 22C2 6D3 6D2 6D1 5C1 22C2 6D3 6D2 6D1 5C1 C 22C2 6C3 6C2 6C1 5C1 22C2 6C3 6C2 6C1 5C1 34D5 34D4 33B4 5B1 34D5 34D4 33B4 5B1 50C6 50C5 50C3 22D4 5B1 50C6 50C5 50C3 22D4 5B1 50C6 50C5 5B1 50C6 50C5 5B1 34B5 34B3 33B4 5B1 34C5 34C3 33B4 5B1 50B6 50B5 50B3 22D4 5B1 50C6 50C5 50C3 22D4 5B1 50C6 50C5 5C1 50C6 50C5 5C1 USB2_LT2_N USB2_LT2_P USB2_LT_N USB2_LT_P USB2_EXCARD_N USB2_EXCARD_P PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_P PCIE_MINI_D2R_N PCIE_MINI_D2R_P PCIE_MINI_R2D_C_N PCIE_MINI_R2D_C_P PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P NC NC B SMBUS_SMC_A_S3_SCL 5B1 SMBUS_SMC_A_S3_SDA 81C3 51B5 27C6 27C5 27C3 5B1 81C3 51B5 27C6 27C5 27C3 27B3 25C2 25B6 25B2 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 67C8 67C6 66C5 62C1 62A8 25D6 25C8 25C6 PP1V5_S0 NC 84 81 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 54 53 56 55 58 57 60 59 62 61 64 63 66 65 68 67 70 69 72 71 74 73 76 75 78 77 80 79 83 82 NC SMC_BC_ACOK LT2USB_OC_L LTUSB_OC_L 51B5 6D5 SYS_ONEWIRE 5C1 ALS_GAIN LTALS_OUT LIO_PLT_RESET_L EXCARD_CLKREQ_L MINI_CLKREQ_L EXCARD_OC_L SMC_EXCARD_CP PM_SLP_S3_LS5V SMC_EXCARD_PWR_EN PM_SLP_S4_L PCIE_WAKE_L 5B1 51C5 52A2 68A6 69A6 5C1 6C1 6C3 22C4 22D8 5C1 6D1 6D3 22C4 22D8 5C1 51B7 52B2 IN C 5C1 57C7 5C1 26C1 5C1 33B4 34A3 34A4 5C1 33B4 34A3 34A4 5C1 6C1 6C3 22C4 22D8 52B3 5C1 51B7 52A2 5C1 6A1 6A2 62B3 66C6 66C7 5C1 51B7 5C1 5C4 6A1 6A2 23C3 41B6 47C7 51C5 64C8 66A6 66B8 5B1 23C8 39C6 NC SMBUS_SB_SCL SMBUS_SB_SDA 5B1 23D5 27B6 27C6 27D6 27D7 27D8 28A6 29A6 33B6 46B6 81C3 5B1 23D5 27B6 27C6 27D6 27D7 27D8 28A6 29A6 33B6 46B6 81C3 ACZ_SDATAOUT 5C1 21C7 87B4 ACZ_BITCLK 5C1 21C7 87B4 ACZ_SDATAIN<0> 5C1 21C7 87B4 ACZ_SYNC 5C1 21C7 87B4 ACZ_RST_L 5C1 21C7 87B4 B NC 516S0361 Left I/O Board Connector A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 48 1 87 A 8 6 7 2 3 4 5 1 D D Battery Current Sense 69B2 DCIn Current Sense CHGR_CSO_R_P 69D6 69C2 CHGR_CSO_R_N Placement Note: 3 Place near R8308 V+ 69D4 CHGR_CSI_P Placement Note: SOT23-5 3 Place near R8307 OUT 1 LIO_BATT_ISENSE 55C3 INA193 5 CRITICAL 1 1uF 2 1 C5615 10% 6.3V CERM 402 2 V+ SOT23-5 OUT 1 LIO_DCIN_ISENSE 55C5 CRITICAL C5605 1uF GND 2 4 VIN+ VINU5605 71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6 54D4 54B5 52D3 49C7 49B5 40B6 36D6 34A8 33D8 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 PP3V3_S0 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 65B3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 82D5 82C6 82B3 82A4 79D3 79A8 INA193 5 CHGR_CSI_R_N 4 VIN+ VINU5615 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3 54B5 52D3 49C4 49B5 40B6 36D6 34A8 33D8 33D3 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 PP3V3_S0 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 69D3 GND 10% 6.3V CERM 402 2 C C TMP106 Thermal Sensor 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 58C4 57B6 54D4 54B5 52D3 49C7 49C4 40B6 36D6 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 82D5 82C6 82B3 66B5 34A8 25B4 5A4 PP3V3_S0 21C3 27C3 58C7 82A4 C1 1 V+ TMP106 WCSP-6 51B5 27D3 27D2 27D1 10B3 SMBUS_SMC_B_S0_SDA A1 SDA 51B5 27D3 27D2 27D1 10B3 SMBUS_SMC_B_S0_SCL B1 SCL 2 A0 ALERT 5% 1/16W MF-LF 402 C2 TMPSNSR_A0 CRITICAL B R5651 0 U5650 1 B2 Temp Sensor has address x92,x93 NO STUFF R5650 B 0 GNDS 1 A2 0.1uF 2 Place sensor on bottom side C5650 2 5% 1/16W MF-LF 402 20% 10V CERM 402 near L8300 and Q8301 and Q8302 Current & Thermal Sensors A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 49 1 87 A 8 7 6 3 4 5 2 1 D D PCI-E x1 Port "A" = Ethernet (Yukon) PCI-E x1 Port "B" = PCI-E Mini Card C5710 0.1uF 50C5 48C6 5B1 PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_P 1 PCIE_B_R2D_C_P 2 22D4 MAKE_BASE=TRUE 10% 16V X5R 402 50C5 48C6 5B1 PCIE_MINI_R2D_C_N C5711 0.1uF PCIE_MINI_R2D_C_N 1 2 Place caps close to SB PCIE_B_R2D_C_N 22D4 MAKE_BASE=TRUE PCIE_MINI_D2R_P 50C6 50C3 48C6 22D4 5B1 5B1 PCIE_MINI_D2R_N 50C6 50C3 48C6 22D4 5B1 50C5 50C3 48C6 22D4 5B1 10% 16V X5R 402 PCIE_MINI_D2R_P PCIE_MINI_D2R_P 5B1 22D4 48C6 50C5 50C6 PCIE_MINI_D2R_N 5B1 22D4 48C6 50C5 50C6 MAKE_BASE=TRUE 50C5 50C3 48C6 22D4 PCIE_MINI_D2R_N MAKE_BASE=TRUE PCI-E x1 Port "C" = ExpressCard C C C5720 0.1uF 50C5 48B6 5C1 PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_P 1 PCIE_C_R2D_C_P 2 22D4 MAKE_BASE=TRUE 10% 16V X5R 402 50C5 48B6 5C1 PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_N C5721 0.1uF 1 2 Place caps close to SB PCIE_C_R2D_C_N 22D4 PCIE_EXCARD_D2R_P 5B1 22D4 48B6 50C5 50C6 PCIE_EXCARD_D2R_N 5B1 22D4 48B6 50B5 50B6 TP_PCIE_D_R2DP 22D4 50B6 TP_PCIE_D_R2DN 22D4 50B6 TP_PCIE_D_D2RP 22D4 50B6 TP_PCIE_D_D2RN 22D4 50B6 TP_PCIE_E_R2DP 22C4 50B6 TP_PCIE_E_R2DN 22C4 50B6 TP_PCIE_E_D2RP 22C4 50B6 TP_PCIE_E_D2RN 22C4 50B6 MAKE_BASE=TRUE PCIE_EXCARD_D2R_P 50C6 50C3 48B6 22D4 5B1 50C5 50C3 48B6 22D4 5B1 PCIE_EXCARD_D2R_N 50B6 50B3 48B6 22D4 5B1 50B5 50B3 48B6 22D4 5B1 10% 16V X5R 402 PCIE_EXCARD_D2R_P MAKE_BASE=TRUE PCIE_EXCARD_D2R_N MAKE_BASE=TRUE PCI-E x1 Port "D" = Unused 50B3 22D4 TP_PCIE_D_R2DP MAKE_BASE=TRUE 50B3 22D4 TP_PCIE_D_R2DN 50B3 22D4 TP_PCIE_D_D2RP MAKE_BASE=TRUE MAKE_BASE=TRUE 50B3 22D4 TP_PCIE_D_D2RN MAKE_BASE=TRUE PCI-E x1 Port "E" = Unused 50B3 22C4 TP_PCIE_E_R2DP 50B3 22C4 TP_PCIE_E_R2DN MAKE_BASE=TRUE MAKE_BASE=TRUE B 50B3 22C4 TP_PCIE_E_D2RP 50B3 22C4 TP_PCIE_E_D2RN B MAKE_BASE=TRUE MAKE_BASE=TRUE PCI-E x1 Port "F" = Unused 50B3 22C4 TP_PCIE_F_R2DP TP_PCIE_F_R2DP 22C4 50B6 TP_PCIE_F_R2DN 22C4 50B6 TP_PCIE_F_D2RP 22C4 50B6 TP_PCIE_F_D2RN 22C4 50A6 MAKE_BASE=TRUE 50B3 22C4 TP_PCIE_F_R2DN MAKE_BASE=TRUE 50B3 22C4 TP_PCIE_F_D2RP 50A3 22C4 TP_PCIE_F_D2RN MAKE_BASE=TRUE MAKE_BASE=TRUE PCI-E Connections A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 50 1 87 A 8 6 7 2 3 4 5 UNUSED PINS HAVE THE FORMAT SMC_XXX WHERE XXX IS THE PORT NUMBER. THEY ARE SET BY SOFTWARE TO BE DRIVEN OUTPUTS ALWAYS SO THEY CAN BE LEFT NO-CONNECTED. 81D4 69C8 52B7 52B5 52B1 51D4 51C2 47B5 35B7 27C3 26D6 5D2 69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52D7 PP3V42_G3H OMIT OUT TP_SMC_P20 52C5 52C3 TP_SMC_P21 52C5 52C3 TP_SMC_P22 52C5 52C3 TP_SMC_P23 SMC_BATT_TRICKLE_EN_L 52A2 OUT SMC_BATT_CHG_EN 52A2 OUT 52C5 52C3 TP_SMC_P26 52C5 52C3 TP_SMC_P27 52C5 52C3 69A3 69A6 60C6 53C4 21D4 5D2 IO 60C6 53C4 21D4 5C2 IO 60C6 53C5 21D4 5C2 IO 60C6 53C5 21D4 5C2 IO 60C6 53C4 21C5 5C2 IN 26B1 5C4 IN 34D6 IN 60C6 53C5 23C8 5C2 52C5 52C3 52A8 OUT OUT OUT 27B3 27B2 52B5 52C5 52C3 52D5 52D3 52D5 52D3 IO OUT OUT OUT OUT 57A6 OUT 53B4 52B3 52B2 47B5 5C2 OUT 53B5 52B3 52B2 47B5 5C2 IO A15 B14 B15 C14 D12 BGA (1 OF 4) P13 P14 P63/KIN3* P64/KIN4* L15 K12 K13 K14 J12 P15 P65/KIN5* C15 P16 P17 P66/IRQ6*/KIN6* P67/IRQ7*/KIN7* D13 P20 P70/AN0 N12 D14 D15 P21 P71/AN1 P22 P23 P72/AN2 P73/AN3 R13 P13 P24 P25 P74/AN4 P75/AN5 P26 P76/AN6 P27 P77/AN7 E12 E14 E15 E13 F14 D9 C9 A9 B9 D8 C8 A8 D7 P32/LAD2 P82/CLKRUN* B7 D6 P83/LPCPD* P84/IRQ3*/TXD1 P35/LRESET* P85/IRQ4*/RXD1 C6 A6 P86/IRQ5*/SCK1/SCL1 B6 P90/IRQ2* K4 P40/TMIO P91/IRQ1* P41/TMO0 P42/SDA1 P92/IRQ0* P93/IRQ12* J2 J1 P43/TMI1/EXSCK1 P94/IRQ13* P44/TMO1 P45 P95/IRQ14* P96/EXCL P36/LCLK P37/SERIRQ P46/PWX0/PWM0 SMC_TX_L SMC_RX_L SMBUS_SMC_0_S0_SCL G1 P50 P51 G4 F2 A7 P33/LAD3 P34/LFRAME* D3 C1 C2 N13 P15 C7 A5 B5 C3 B1 R15 P80/PME* P81/GA20 P97/IRQ15*/SDA0 J3 J4 H2 H1 G2 22UF OUT 20% 6.3V 2 CERM 805 OUT IN 1 C5803 1 0.1UF C5804 0.1UF 20% 10V 2 CERM 402 20% 10V 2 CERM 402 1 C5805 1 0.1UF C5806 0.1UF 20% 10V 2 CERM 402 20% 10V 2 CERM 402 IN OUT LAYOUT NOTE: PLACE C5807 NEAR PIN F1 IN IN D IN SMC_CPU_ISENSE IN 55D6 SMC_CPU_VSENSE IN 55B6 SMC_GPU_ISENSE IN 55C6 SMC_GPU_VSENSE IN 55C4 SMC_DCIN_ISENSE IN 55D2 SMC_PBUS_VSENSE IN 55C2 SMC_BATT_ISENSE IN 55B4 52D3 SMC_P1V5S0_NB_ISENSE IN SMC_VCL 55B7 R14 P14 P30/LAD0 P31/LAD1 TP_SMC_XDP_TMS SMC_SYS_LED_16B SMBUS_SMC_BSB_SDA SMC_TPM_PP TP_SMC_XDP_TRST_L TP_SMC_XDP_TCK TP_SMC_SYS_LED SMC_SYS_KBDLED D5 J13 SMC_PM_G2_EN SMC_ADAPTER_EN 22C6 SPI_ARB 56C7 22C6 SPI_SCLK 56C1 22C6 SPI_SI 56C1 22C6 SPI_SO 52D1 SMC_PROCHOT_3_3_L 53C5 52D5 52D3 21C4 5C2 FWH_INIT_L 66A8 68A6 52A2 43C8 52D5 SMC_WAKE_SCI_L 52C5 SMC_TPM_GPIO 60C6 53C4 23C8 5C2 PM_CLKRUN_L 60C6 53B5 52A2 23C5 5C2 PM_SUS_STAT_L 52B5 SC_TX_L 52B5 SC_RX_L 27B3 27B2 SMBUS_SMC_BSB_SCL 23C1 81C4 52C6 52B2 5A2 69A6 68A6 52A2 48C3 5B1 SMC_ONOFF_L SMC_BC_ACOK 68B2 52B2 5D1 SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L 52A2 23C3 5C4 PM_SLP_S5_L 35B3 35B2 SMC_CLK32K_SUSCLK 54C2 54B3 27D6 27D5 27D3 SMBUS_SMC_0_S0_SDA 1 LAYOUT NOTE: PLACE R5899 AND C5820 NEAR SMC PIN N14,N15 10% 6.3V 2 CERM-X5R 402 81D4 69C8 69B8 69A8 68B8 67D5 52B1 51D3 51C2 47B5 35B7 27C3 26D6 5D2 67D3 66D2 66C8 66A8 53C4 52D7 52B7 52B5 PP3V42_G3H PP3V3_AVREF_SMC R5899 IN 1 OUT 4.7 2 5% 1/16W MF-LF 402 IO IN OUT 1 C5820 0.1UF 69C8 52D7 52B1 47B5 26D6 5D2 35B7 27C3 51D4 51D3 52B7 52B5 69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 81D4 OMIT BGA (3 OF 4) IN MD1 E2 MD2 K1 NMI F4 ETRST* L1 IN IN IN 52C8 IN 52C8 R5809 10K SMC_H8S2116 GND_SMC_AVSS 53B5 52D6 5C2 IN PP3V42_G3H U5800 IO 57C2 55D6 55C6 55C1 55B7 55B5 55B3 55B1 52B6 51B2 57C6 52B6 PP3V3_AVCC_SMC MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM 20% 10V 2 CERM 402 IN IN C5807 0.47UF VCL IS INTERNAL RAIL SMC_RST_L E3 RES* SMC_XTAL SMC_EXTAL A2 XTAL B2 EXTAL R5801 10K 1 1 5% 1/16W MF-LF 2402 5% 1/16W MF-LF 2402 SMC_MD1 5C2 53B4 KBC_MDE 53B5 5C2 SMC_NMI IN 53B4 5C2 SMC_TRST_L IN IN IO P47/PWX1/PWM1 AVSS P52/SCL0 VSS D1 P4 54C2 54B3 27D6 27D5 27D3 IN LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L PCI_CLK_SMC INT_SERIRQ L14 VCL F1 23C3 D OUT P61/KIN1* P62/KIN2* AVREF M14 AVREF M15 61C7 5C4 OUT SMC_H8S2116 B4 D2 23C1 5B4 IN OUT L13 P11 P12 A4 23C3 P60/KIN0* C13 VCC J15 VCC A1 65C7 52A5 52A4 U5800 B13 A13 IN C5802 1 P10 VCC P2 VCC P1 OUT B12 R4 37A8 6C5 6C3 PM_LAN_ENABLE SMC_RSTGATE_L ALL_SYS_PWRGD RSMRST_PWRGD SMC_SB_NMI PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L F12 F13 OUT AVCC N14 AVCC N15 23C3 5B4 66B1 26A5 C 1 P12 R12 C NOSTUFF 1 1 R5898 R5803 R5802 10K 0 10K 1 5% 1/16W MF-LF 2402 5% 1/16W MF-LF 2402 5% 1/16W MF-LF 2402 OMIT 21C3 53B4 22B3 5C2 26C5 23C5 5A2 52B5 52D5 52D3 29C3 28C3 14B7 23C8 IN IN OUT IN IO 52B2 48C3 5C1 IO 23C1 OUT 23B8 23C8 36C4 55A8 5B2 52A2 48C3 5C1 48C3 5C1 52B5 52B2 B OUT 58B7 58B4 52D5 52D3 52D5 52D3 IN OUT IN OUT IN OUT IN OUT OUT OUT OUT OUT 58B7 IN 58B4 IN 52D5 52D3 IN 52D5 52D3 IN 59C3 IN 59C3 IN 59C3 IN 52D5 52D3 IN 55B2 52D5 52D3 IN 52A2 IN 57C7 IN 57D2 IN U5800 SMC_RCIN_L BOOT_LPC_SPI_L PM_SYSRST_L SMC_USB_DEBUG_MUX PM_EXTTS_L PM_THRM_L SYS_ONEWIRE PM_BATLOW_L R3 P3 PA0/KIN8*/PA2DC R2 PA2/KIN10*/PS2AC PA3/KIN11*/PS2AD SMC_EXTSMI_L SMC_RUNTIME_SCI_L SMC_ODD_DETECT ISENSE_CAL_EN SMC_EXCARD_CP SMC_EXCARD_PWR_EN SMC_EXCARD_OC_L SMC_XDP_TDO_3_3 B10 SMC_FAN_0_CTL SMC_FAN_1_CTL TP_SMC_FAN_2_CTL TP_SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH TP_SMC_FAN_2_TACH TP_SMC_FAN_3_TACH SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS TP_SMC_ANALOG_ID SMC_P1V05S0_ISENSE SMC_MEM_ISENSE ALS_LEFT ALS_RIGHT N3 R1 N2 M4 N1 A10 D10 A11 PA1/KIN9*/PA2DD SMC_H8S2116 BGA (2 OF 4) PA4/KIN12*/PS2BC PA5/KIN13*/PS2BD PA6/KIN14*/PS2CC PA7/KIN15*/PS2CD PB0/LSMI* PB1/LSCI PE0 PE1*/ETCK PE2*/ETDI PE3*/ETDO PE4*/ETMS PF6/PWM6 PF7/PWM7 A12 PB5 PB6 PG0/EXIRQ8*/TMIX D11 PB7 PG1/EXIRQ9*/TMIY PG2/EXIRQ10*/SDA2 G14 G15 PC0/TIOCA0/WUE8* PG3/EXIRQ11*/SCL2 H15 H13 H12 M11 P11 R11 N11 P10 R10 PC1/TIOCB0/WUE9* PC2/TIOCC0/TCLKA/WUE10* PG4/EXIRQ12*/EXSDAA PG5/EXIRQ13*/EXSCLA PC3/TIOCD0/TCLKB/WUE11* PG6/EXIRQ14*/EXSDAB PC4/TIOCA1/WUE12* PC5/TIOCB1/TCLKC/WUE13* PG7/EXIRQ15*/EXSCLB PC6/TIOCA2/WUE14* PC7/TIOCB2/TCLKD/WUE15* PD0/AN8 53B4 52B2 R6 N6 PF5/PWM5 G12 H14 L4 L2 PF2/IRQ10*/TMOY PB3 PB4 G13 53B5 52B2 5C2 M7 PB2 B11 C11 53B5 52B2 5C2 M1 PF0/IRQ8*/PWM2 PF1/IRQ9*/PWM3 PF3/IRQ11*/TMOX PF4/PWM4 PH0/EXIRQ6* PH1/EXIRQ7* PH2/FWE PH3/EXEXCL PD1/AN9 PH4 PD2/AN10 PD3/AN11 PH5 SMC_CASE_OPEN SMC_TCK SMC_TDI 5C2 SMC_TDO 5C2 SMC_TMS M3 M2 52A2 53B4 52B2 P6 81C4 M6 R5 P5 52D5 N5 52D5 P9 R9 N9 P8 R8 56C7 22C6 52B2 68B2 27C3 27C2 27C1 5D1 68B2 27C3 27C2 27C1 5D1 P7 R7 F3 K2 C4 D4 B3 XW5800 SM IN IN 1 OUT 2 GND_SMC_AVSS 51C4 52B6 55B1 55B3 55B5 55B7 55C1 55C6 55D6 57C2 57C6 IN TP_SMC_PF0 52C3 52C5 TP_SMC_PF1 52C3 52C5 52B2 SMC_LID IN 52B2 SMC_CPU_RESET_3_3_L IN 69A8 SMC_BATT_ISET OUT 52D3 TP_SMC_BATT_VSET OUT 69A8 SMC_SYS_ISET OUT 52D3 TP_SMC_SYS_VSET OUT M8 E1 IN SPI_CE_L SMC_XDP_TCK_3_3 SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SCL SMC_PROCHOT 52C2 SMC_THRMTRIP 52B2 SMC_FWE 48C4 6D5 5C1 ALS_GAIN 52B2 23C3 SMS_INT_L 59C6 SMS_ONOFF_L 52C2 IO IN IO B IO IO IO IO IO OUT OUT IN OUT OUT OUT PD4/AN12 N10 PD5/AN13 PD6/AN14 M10 PD7/AN15 OMIT U5800 SMC_H8S2116 BGA SMC (4 OF 4) A G3 H3 K3 L3 N4 M5 N7 M12 M13 L12 NC0 NC12 NC1 NC2 NC13 NC14 NC3 NC15 NC4 NC5 NC16 NC17 NC6 NC7 NC18 NC19 NC8 NC20 K15 NC9 NC10 NC21 NC22 J14 NC11 F15 A14 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING C5 A3 B8 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT E4 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART H4 M9 SIZE N8 APPLE COMPUTER INC. DRAWING NUMBER D SHT NONE 7 6 5 4 3 2 REV. 051-7164 SCALE 8 A NOTICE OF PROPRIETARY PROPERTY C12 C10 06004 OF 51 1 87 8 6 7 FWH_INIT_L FWH_INIT_L MAKE_BASE=TRUE SMC Reset Button / Brownout Detect 55B2 52D3 51A7 SMC_P1V05S0_ISENSE PP3V42_G3H 55B4 52D3 51D5 C5900 1 1 2 0.1uF 20% 10V CERM 402 RN5VD30A-F 5 OMIT 4 NC 2 OUT CD NC 53B5 51C3 5C2 C5901 0 1 3 0.01UF 5% 1/10W MF-LF 603 10% 16V CERM 402 PM_EXTTS_L PM_EXTTS_L 14B7 28C3 29C3 51B7 52D5 5% 1/16W MF-LF 402 TP_SMC_SYS_LED TP_SMC_SYS_LED 51C7 52D5 5% 1/16W MF-LF 402 2 52D3 51A7 TP_SMC_ANALOG_ID 20% 10V CERM 402 52D3 51B5 TP_SMC_BATT_VSET TP_SMC_BATT_VSET 51B5 52D5 MAKE_BASE=TRUE CRITICAL 52D3 51B5 TP_SMC_SYS_VSET 52D3 51B7 TP_SMC_FAN_2_CTL 52C1 7C6 TP_SMC_SYS_VSET TP_SMC_FAN_3_CTL 52D3 51B7 TP_SMC_FAN_3_TACH 52D3 51C7 TP_SMC_XDP_TCK D 51D5 1K 51B7 52D5 TP_SMC_FAN_2_TACH 5% 1/16W MF-LF 402 51B7 52D5 MAKE_BASE=TRUE 52D3 51B7 SMC_PROCHOT_3_3_L V- R5971 1 TP_SMC_FAN_2_CTL TP_SMC_FAN_2_TACH SM-LF 1 5 MAKE_BASE=TRUE 52D3 51B7 CPU_PROCHOT_L 3 51B5 52D5 MAKE_BASE=TRUE 2 LMC7211 V+ MAKE_BASE=TRUE OUT U5977 2 4 VOLTAGE=0.46V 51A7 52D5 2 1.05V Mid-Reference P0V46_SMC_LSREF TP_SMC_ANALOG_ID 1 0.1uF 6.2K MAKE_BASE=TRUE SMC_RST_L 1 52D3 51C7 C5977 R5970 1 R5900 GND R5901 2 SMC_P1V5S0_NB_ISENSE MAKE_BASE=TRUE SOT23-5 Silk: "SMC RST" SMC 1.05V to 3.3V Level Shifting PP3V3_S0 1K VDD U5900 2 SMC_MANUAL_RST_L 1 SMC_P1V5S0_NB_ISENSE 1 MAKE_BASE=TRUE 52D3 51B7 29C3 28C3 14B7 D 21C4 51D5 52D5 53C5 5C2 67C5 67C3 67B3 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 54B5 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 26B8 26B6 25C6 25C4 25B8 25B4 25A4 24D3 24C3 24B5 24B3 23D5 19C6 17C6 14D6 14C7 10C5 5D4 5A4 23B3 22B5 21D3 21C3 20B4 20A4 19C7 51A7 52D5 55B2 26B4 25D8 25D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 33D3 33C7 67A3 66B6 66B5 66B1 65D6 65B3 62A6 82D5 82C6 82B3 82A4 79D3 79A8 71D2 51D5 52D5 55B4 SMC_P1V05S0_ISENSE MAKE_BASE=TRUE 81D4 69C8 52B5 52B1 51D4 51D3 51C2 47B5 35B7 27C3 26D6 5D2 69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52B7 2 3 4 5 53C5 52D3 51D5 21C4 5C2 TP_SMC_FAN_3_CTL 2 51B7 52D5 MAKE_BASE=TRUE TP_SMC_FAN_3_TACH 51B7 52D5 MAKE_BASE=TRUE TP_SMC_XDP_TCK 51C7 52D5 MAKE_BASE=TRUE SMC Crystal Circuit Debug Power Button 51C7 52C3 TP_SMC_XDP_TMS 52C3 51C7 TP_SMC_XDP_TRST_L 52C3 51D7 TP_SMC_P20 1 2 SMC_ONOFF_L OUT 1 20.00MHZ 5X3.2-SM 1 C5921 2 2 15pF 1 SMC_EXTAL CPU_PROCHOT_L 51D7 52C5 TP_SMC_P21 52C3 51D7 TP_SMC_P22 TP_SMC_P21 D 51D7 52C5 Q5995 2N7002DW-X-F TP_SMC_P22 51D7 52C5 MAKE_BASE=TRUE 52C3 51D7 TP_SMC_P23 52C3 51D7 TP_SMC_P26 51B5 TP_SMC_P23 5 SMC_PROCHOT G SOT-363 S 51D7 52C5 4 MAKE_BASE=TRUE 2 TP_SMC_P26 51D7 52C5 MAKE_BASE=TRUE 52C3 51D7 TP_SMC_P27 52C3 51B5 TP_SMC_PF0 52C3 51B5 TP_SMC_PF1 TP_SMC_P27 51D7 52C5 MAKE_BASE=TRUE TP_SMC_PF0 PM_THRMTRIP_L 51B5 52C5 TP_SMC_PF1 51B5 52C5 6 D Q5995 SMC_TPM_GPIO1 2N7002DW-X-F R5990 51D5 51B5 0 SMC_TPM_GPIO 1 TPM_GPIO1 2 0 1 PP3V3_AVREF_SMC SOT23-3 1 IN OUT SMC_TPM_PP R5995 51C7 GND 3 1 2 2 C5965 C5966 0.47UF 10uF 10% 6.3V CERM-X5R 402 20% 6.3V X5R 603 1 2 0 SMC_TPM_PP 1 60C6 TPM_GPIO2 60C6 2 TPM_PP 60C6 81D4 69C8 52B7 52B5 51D4 51D3 51C2 47B5 35B7 27C3 26D6 5D2 69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52D7 5% 1/16W MF-LF 402 C5967 0.01uF 1 20% 16V CERM 402 46C3 46B3 41C5 37D7 37D5 37C3 37A7 32C5 27C5 5D4 67C5 67C3 66C6 65D1 63B7 60C2 59C6 57D4 52B1 46D6 81D4 81A5 41C5 37D7 37D5 37C3 37A7 32C5 27C5 5D4 63B7 60C2 59C6 57D4 52B1 46D6 46C3 46B3 81D4 81A5 67C5 67C3 66C6 65D1 R5992 51C5 0 SC_RX_L 1 2 SMC_RX_L 51B5 23C3 5C2 47B5 51C7 52B2 53B5 60B7 5% 1/16W MF-LF 402 2 R5993 GND_SMC_AVSS MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V 51C5 0 SC_TX_L 1 SMC_TX_L 2 51B2 51C4 55B1 55B3 55B5 55B7 55C1 55C6 55D6 57C2 57C6 81C4 52C6 51C5 5A2 5C2 47B5 51C7 52B2 53B4 81C4 51B5 51B7 5% 1/16W MF-LF 402 SMC_EXCARD_OC_L R5994 0 1 2 51B5 EXCARD_OC_L 53B4 52B3 51C7 47B5 5C2 5C1 6C1 6C3 22C4 22D8 48C3 53B5 52B3 51C7 47B5 5C2 B R5996 51B7 SMC_USB_DEBUG_MUX 0 1 5% 1/16W MF-LF 402 USB_DEBUGPRT_EN_L 2 47B3 51B7 48C3 5C1 5% 1/16W MF-LF 402 68B2 51C5 5D1 53B4 51B5 5C2 53B4 51B5 5C2 SMC PWRGD Circuit 53B5 51B5 5C2 53B5 51C5 5C2 Reports when 5V S5 and 3.3V S5 are in regulation System (Sleep) LED Circuit 51B5 65D6 65B7 64C8 62C8 62B6 62B2 62A4 47C7 25C8 5D4 71D7 67C3 67C1 67B1 66D8 66B8 81D4 69C8 52B7 52B1 51D4 51D3 51C2 47B5 35B7 27C3 26D6 5D2 69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52D7 PP5V_S3 PP5V_S5 PP3V42_G3H 51B5 51B7 69A3 51D7 R5951 1 1 100 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 2 C5960 R5950 2.2K R5961 1 1 10K 1% 1/16W MF-LF 402 2 R5963 1 69A6 51D7 0.1uF 16.2K 1% 1/16W MF-LF 2 402 SYS_LED_ILIM 20% 10V CERM 402 68A6 51D5 43C8 2 51C5 69A6 68A6 51C5 48C3 5B1 51B7 48C3 5C1 2 P1V71_SMC_REF 1.71V Reference 4 Q5950 1 P5VS5_COMP_POS 2N3906 3 81C6 5% 1/16W MF-LF 402 2 A R5962 1 SYS_LED_ANODE OUT 1 R5964 10K 10K 1% 1/16W MF-LF 402 2 1% 1/16W MF-LF 2 402 60C6 53B5 51C5 23C5 5C2 66A8 66A6 65D7 1 5 3 10K SM-LF 1 V- SOT23-LF R5952 1 U5960 LMC7211 V+ 2 SYS_LED_L_VDIV 51C5 23C3 5C4 P5VS5_PGOOD 51A7 OUT R5930 R5931 SMS_INT_L SMC_TPM_RESET_L R5932 R5933 R5934 R5935 R5936 SMC_ONOFF_L SMC_LID SMC_FWE SMC_TX_L SMC_RX_L R5937 R5938 R5939 R5940 R5941 R5942 R5980 R5981 R5982 SYS_ONEWIRE SMC_BS_ALRT_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_CPU_RESET_3_3_L SMC_XDP_TCK_3_3 SMC_XDP_TDO_3_3 SMC_BATT_TRICKLE_EN_L SMC_BATT_CHG_EN SMC_ADAPTER_EN SMC_CASE_OPEN SMC_BC_ACOK SMC_EXCARD_CP PM_SUS_STAT_L PM_SLP_S5_L SMC_MEM_ISENSE 10K 10K 10K 10K 470K 10K 100K 100K 100K 5% 1/16W MF-LF 2 402 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 Q5952 65C7 52A4 51D7 2N7002 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 B SMC Support SYNC_DATE=09/15/2006 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING G IN 65C7 52A5 51D7 RSMRST_PWRGD S RSMRST_PWRGD MAKE_BASE=TRUE ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V) NOTE: R5965 acts as 10K pull-up for PGOOD signal SOT23-LF 1 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE OUT II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART C5969 0.0022uF 2 2 SIZE 10% 50V CERM 402 APPLE COMPUTER INC. DRAWING NUMBER D SHT NONE 7 6 5 4 3 2 REV. 051-7164 SCALE 8 2 5% SYNC_MASTER=M59_MLB 3 1 2.0K 100K 10K 10K 10K 10K 10K 10K 10K 2 1 NOTICE OF PROPRIETARY PROPERTY D SMC_SYS_LED_16B 10K 100K 10K 10K 100K 1 10K 5V Comp threshold set to 4.480V (89.6%) IN R5943 R5944 R5945 R5946 R5947 R5948 R5983 R5984 R5985 10K 10K PP3V42_G3H PP3V3_S3 PP3V3_S3 R5965 SYS_LED_L 51C7 SOT-363 S 5% 1/16W MF-LF 402 51D2 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 2 G R5991 VR5965 REF3133 2 SMC_TPM_GPIO2 5% 1/16W MF-LF 402 CRITICAL PP3V42_G3H SMC_THRMTRIP 1 SMC AVREF Supply 81C6 45C3 5D4 5B2 81C4 67B3 67B1 62A2 C 7C6 14B6 21C2 MAKE_BASE=TRUE MAKE_BASE=TRUE 81D4 69C8 52B5 52B1 51D4 51D3 51C2 47B5 35B7 27C3 26D6 5D2 69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52D7 7C6 52D3 3 MAKE_BASE=TRUE 5% 1/10W MF-LF 603 5% 50V CERM 402 C 52C3 51D7 R5910 0 Silk: "PWR BTN" TP_SMC_P20 MAKE_BASE=TRUE OMIT Y5920 51C3 81C4 52B2 51C5 5A2 5% 50V CERM 402 CRITICAL 51C7 52C5 MAKE_BASE=TRUE 15pF SMC_XTAL 51C7 52C5 TP_SMC_XDP_TRST_L C5920 51C3 SMC 3.3V to 1.05V Level Shifting TP_SMC_XDP_TMS MAKE_BASE=TRUE 06004 OF 52 1 87 A 8 7 6 3 4 5 2 1 D D CRITICAL LPCPLUS C C J6000 QT500306-L021-9F M-ST-SM NC 52D5 52D3 51D5 21C4 5C2 34D6 5C2 60C6 51C7 21D4 5C2 60C6 51C7 21D4 5C2 60C6 51C7 23C8 5C2 60C6 52A2 51C5 23C5 5C2 52B2 51B5 5C2 52B2 51C5 5C2 52D6 51C3 5C2 51C1 5C2 52B3 52B2 51C7 47B5 5C2 23C3 23B6 5C2 FWH_INIT_L PCI_CLK_PORT80_LPC 2 LPC_AD<2> LPC_AD<3> INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RST_L SMC_NMI SMC_RX_L SV_SET_UP 32 (GPIO15) NC 31 NC PP3V42_G3H PP5V_S0 81D4 5D2 26D6 27C3 35B7 47B5 51C2 51D3 51D4 52B1 52B5 52B7 52D7 66A8 66C8 66D2 67D3 67D5 68B8 69A8 69B8 69C8 5D2 5D4 25D8 31C5 36D6 55A8 57B5 58C4 58C7 61D7 62B1 66B5 67A1 67B1 67B3 71A6 79B8 80A1 80B5 81B3 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 34 33 LPC_AD<0> LPC_AD<1> LPC_FRAME_L PM_CLKRUN_L BOOT_LPC_SPI_L SMC_TMS DEBUG_RST_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L 5D2 21D4 51D7 60C6 5C2 21D4 51D7 60C6 5C2 21C5 51C7 60C6 5C2 23C8 51C5 60C6 5C2 22B3 51C7 5C2 51B5 52B2 5C2 26B1 5C2 51C1 5C2 51B5 52B2 5C2 51C1 5C2 47B5 51C7 52B2 52B3 NC 516S0384 B B LPC+ Debug Connector A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 53 1 87 A 8 6 7 2 3 4 5 1 GPU/Heat Pipe & Bottom Case Skin Thermal Sensor D 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 58C4 57B6 54B5 52D3 49C7 49C4 49B5 40B6 36D6 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 82D5 82C6 82B3 M-RT-SM 3 66B5 34A8 25B4 5A4 21C3 27C3 58C7 82A4 R6100 PP3V3_S0 1 NC XW6110 SM 1 Placement note: 5A2 RSFSTHMSNS_D_P 1 47 PP3V3_S0_GPUTHMSNS_R 2 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE 5% 1/16W MF-LF 402 Place on left side of fan cutout C6110 4 NC 10% 50V CERM 402 5A2 VCC U6100 XW6111 2 1 UMAX REMTHMSNS_DXP1 REMTHMSNS_DXN REMTHMSNS_DXP2 2 XW6120 CRITICAL SM J6120 5A2 HSTHMSNS_DX_P 1 Placement note: 1 Place in between VRAM 2 4 2 4 DXP2 ALERT* 8 NC OT1* 5 OT2* 10 NC NC CRITICAL C6120 NC 1 27D3 27D5 27D6 51C5 54B3 27D3 27D5 27D6 51C7 54B3 XW6121 2 6 10% 50V CERM 402 SM HSTHMSNS_DX_N NC 7 GND 0.0022uF 5A2 SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SCL SMBDATA SMBCLK 9 3 DXP1 DXN 2 BM02B-ACHKS-A-GAN-TF-LF M-RT-SM 3 20% 10V CERM 402 MAX6695AUB SM RSFSTHMSNS_D_N C6100 0.1uF 2 1 0.0022uF 518S0452 (TG0H) 1 2 2 1 (Th1H) D (Th0H) CRITICAL J6160 BM02B-ACHKS-A-GAN-TF-LF 1 2 Placement note: Keep all 4 XWs as close to U6100 as possible 518S0452 C C GPU Die Thermal Sensor 82D5 67A3 66B6 66B5 66B1 65D6 65B3 62A6 61D8 49C4 49B5 40B6 36D6 34A8 33D8 33D3 33C7 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 25A4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 26B8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 52D3 49C7 82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 PP3V3_S0 C6150 1 0.1UF 10% 16V X5R 402 R61511 10K 2 5% 1/16W MF-LF 402 2 1 R6152 10K 5% 1/16W MF-LF 2 402 R6160 77A3 ATI_TDIODE_P 1 499 1 GPUTHMSNS_DXP 2 1% 1/16W MF-LF 402 (TG0T) 1 2 77A3 B 1 ATI_TDIODE_N 499 2 ALERT*/ 6 RSTHMSNS_ALERT_L THM2* C6160 0.001UF R6161 VDD 10% 50V CERM 402 2 D+ 3 D- U6150 TMP401 MSOP GPUTHMSNS_DXN 1% 1/16W MF-LF 402 THM* 4 RSTHMSNS_THM_L SCLK 8 SDATA 7 54C2 51C7 27D6 27D5 27D3 54C2 51C5 27D6 27D5 27D3 SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA IO B IO GND 5 Placement note: Place U6150 near GPU Thermal Sensors A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 54 1 87 A 8 6 7 CPU Voltage Sense / Filter 67D3 67D1 61D1 55A6 9D7 8D7 8B5 5B2 XW6209 PPVCORE_S0_CPU D CPUVSENSE_IN 2 4.53K 1 2 51D5 1% 1/16W MF-LF 402 Place short near U0700 center PBUS Voltage Sense Enable & Filter SMC_CPU_VSENSE Q6215 OUT FDG6332C_NL D SC70-6 C6209 1 P-CHN 0.22UF 20% 6.3V X5R 402 2 64D7 64A6 62D7 61D7 61D4 43D8 42B8 41C6 5C4 5A1 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 PPBUS_G3H 4 D S 3 PPBUS_G3H_VSENSE VOLTAGE=12.6V R6285 1 G GND_SMC_AVSS 51B2 51C4 52B6 55B1 55B3 55B5 55B7 55C1 55C6 57C2 57C6 27.4K 5 Place RC close to SMC 1% 1/16W MF-LF 402 PBUSVSENS_EN_L 6 Rthevanin = 4573 ohms 2 51D5 D 66C6 66B6 65B8 51C5 43C8 42A8 39C8 32B3 23C3 5C4 66C8 XW6259 PPVCORE_D3C_GPU R6259 SM 1 GPUVSENSE_IN 2 4.53K 1 2 2 51D5 SMC_GPU_VSENSE G SMC_PBUS_VSENSE R6286 1 FDG6332C_NL SC70-6 C6285 1 5.49K 1% 1/16W MF-LF 402 1 0.22UF 20% 6.3V X5R 402 2 2 OUT GND_SMC_AVSS 1 C6259 51B2 51C4 52B6 55B1 55B3 55B5 55B7 55C6 55D6 57C2 57C6 Place RC close to SMC 0.22UF 2 OUT Q6215 S Enables PBUS VSense divider when high. 1% 1/16W MF-LF 402 Place short near U8400 center PM_SLP_S3_L N-CHN GPU Voltage Sense / Filter 77A7 72D8 71C1 71B7 67A8 67A6 55A5 5B2 1 R6209 SM 1 2 3 4 5 20% 6.3V X5R 402 GND_SMC_AVSS 51B2 51C4 52B6 55B1 55B3 55B5 55B7 55C1 55D6 57C2 57C6 Place RC close to SMC C C DCIN Current Sense Filter Battery Current Sense Filter R6280 49C2 LIO_DCIN_ISENSE IN 1 4.53K R6290 2 51D5 1% 1/16W MF-LF 402 SMC_DCIN_ISENSE 49C6 OUT IN LIO_BATT_ISENSE 0.22UF R6270 1 2 1% 1/16W MF-LF 402 51D5 1 SMC_CPU_ISENSE 71D1 OUT IN 1 1% 1/16W MF-LF 402 C6270 0.22UF B 2 2 51D5 SMC_GPU_ISENSE 1 SMC_P1V5S0_NB_ISENSE 20% 6.3V X5R 402 GND_SMC_AVSS 65B1 OUT P1V05S0_IOUT 4.53K 1 2 20% 6.3V X5R 402 52D5 52D3 51A7 1 51B2 51C4 52B6 55B1 55B3 55B5 55B7 55C1 55C6 55D6 57C2 57C6 OUT C6240 B 20% 6.3V X5R 402 GND_SMC_AVSS 51B2 51C4 52B6 55B1 55B3 55B5 55B7 55C1 55C6 55D6 57C2 57C6 Place RC close to SMC SMC_P1V05S0_ISENSE 0.22UF 2 GND_SMC_AVSS 51B2 51C4 52B6 55B1 55B3 55B7 55C1 55C6 55D6 57C2 57C6 IN 1% 1/16W MF-LF 402 C6235 2 Place RC close to SMC 0.22UF 1.05V S0 (NB) Current Sense Filter 0.22UF 20% 6.3V X5R 402 GND_SMC_AVSS 51B2 51C4 52B6 55B1 55B3 55B5 55C1 55C6 55D6 57C2 57C6 2 1% 1/16W MF-LF 402 0.22UF 2 Place RC close to SMC 1 OUT C6290 R6240 52D5 52D3 51D5 4.53K P1V5S0_NB_IOUT IN C6275 1 20% 6.3V X5R 402 GND_SMC_AVSS 62A6 OUT SMC_BATT_ISENSE Place RC close to SMC R6235 4.53K GPUVCORE_IOUT 1 51B2 51C4 52B6 55B1 55B3 55B5 55B7 55C1 55C6 55D6 57C2 57C6 1.5V S0 (NB) Current Sense Filter R6275 4.53K CPUVCORE_IOUT IN 51D5 2 GND_SMC_AVSS 61A5 2 20% 6.3V X5R 402 Place RC close to SMC GPU Current Sense Filter 4.53K 1% 1/16W MF-LF 402 C6280 1 2 CPU Current Sense Filter 1 51B2 51C4 52B6 55B1 55B3 55B5 55B7 55C1 55C6 55D6 57C2 57C6 Place RC close to SMC Current Sense Calibration Circuit Switches in fixed load on power supplies to calibrate current sense circuits Q6229 FDG6332C_NL SC70-6 67D3 67D1 61D1 55D7 9D7 8D7 8B5 5B2 79B8 71A6 67B3 67B1 67A1 66B5 36D6 31C5 25D8 5D4 5D2 62B1 61D7 58C7 58C4 57B5 53C4 81B3 80B5 80A1 4 R6229 1 5% 1/16W MF-LF 402 D S G 470K ISENSE_CAL_EN_LS5V 3 1 470K 5 2 R6228 2 5% 1/16W MF-LF 402 ISENSE_CAL_EN 2 G 4 1% 1/4W MF-LF 1206 2 FDM6296 G FDM6296 G 2 1.05A / 1.1W 5 D CRITICAL SYNC_MASTER=M59_MLB FDM6296 G MICROFET3X3 3 Current & Voltage Sensing Q6223 4 NOTICE OF PROPRIETARY PROPERTY S 1 2 3 1 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING 3 100K 5% 1/16W MF-LF 402 SYNC_DATE=09/15/2006 MICROFET3X3 S 1 2 P1V05S0_ISENSE_CAL MIN_LINE_WIDTH=0.50 mm MIN_NECK_WIDTH=0.20 mm CRITICAL MICROFET3X3 1 1% 1/4W MF-LF 1206 2 Q6221 4 S SC70-6 1.00 1.2A / 1.44W 5 PP1V05_S0 R6223 1 GPUVCORE_ISENSE_CAL D 65A2 17D3 5B2 11C5 24C3 1 MIN_LINE_WIDTH=0.50 mm MIN_NECK_WIDTH=0.20 mm CRITICAL FDG6332C_NL S R6227 1 1.00 Q6220 N-CHN IN R6221 1% 1/4W MF-LF 1206 5 D 67D8 67D6 21C1 19D7 19D6 19D5 19D2 19D1 19C8 17D6 11B3 9B7 8C7 7D5 7B6 7B5 5D4 16D3 16C8 13B5 12C2 12B7 12A7 34C8 34C6 34B8 25D3 25C4 24D3 1.00 CPUVCORE_ISENSE_CAL D Q6229 PPVCORE_D3C_GPU 1 MIN_LINE_WIDTH=0.50 mm MIN_NECK_WIDTH=0.20 mm 6 51B7 5B2 71C1 71B7 67A8 67A6 55C7 5B2 77A7 72D8 R6220 ISENSE_CAL_EN_L A PPVCORE_S0_CPU P-CHN PP5V_S0 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 55 1 87 A 8 6 7 2 3 4 5 1 D PP3V3_S5 79D5 67D5 67D3 67C3 66C5 65D8 24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 65D2 65D1 65C8 63D8 26C5 25D2 25C8 25B6 24C3 24B3 D 1 0.1UF R63021 R63011 3.3K 20% 2 10V CERM 3.3K 5% 1/16W MF-LF 402 2 402 2 5% 1/16W MF-LF 402 2 C6312 R6308 CRITICAL 8 10K OMIT 5% 1/16W MF-LF 402 1 VDD U6301 16MBIT R6307 1 SPI_CE_L 6 22pF 5% 50V 402 1 NOSTUFF 1 C6308 R6309 22pF 10K 5% 2 50V CERM 402 SI SCK 5 SPI_SI_R SST25VF016B SPI_WP_L SPI_HOLD_L C6309 2 CERM R6306 SOI SPI_SCLK_R 5% 1/16W MF-LF 402 1 C 2 2 51B5 22C6 SPI_SCLK 3 7 CE* WP* HOLD* 1 47 2 SPI_SI 22C6 51D5 SPI_SO 22C6 51D5 5% R6303 1/16W MF-LF SO 2 SPI_SO_R 1 47 5% 1/16W MF-LF 402 VSS 2 402 1 C6301 22pF 5% 1 2 50V CERM 4 C6311 22pF 402 5% 1/16W MF-LF 402 5% 2 50V CERM 402 1 51D5 22C6 47 C R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH ICH7M AND TEKOA(LAN CHIP) R6307 AND R6306 SHOULD BE PLACED LESS THAN 100 MILS FORM ICH7M R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM B B SPI BOOTROM SYNC_MASTER=M59_MLB A SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 56 1 87 A 8 6 7 2 3 4 5 1 Right ALS Circuit 81D4 46C3 46B3 41C5 37D7 37D5 37C3 37A7 32C5 27C5 5D4 81A5 67C5 67C3 66C6 65D1 63B7 60C2 59C6 52B1 46D6 PP3V3_S3 D C6405 D 1 0.1UF 20% 10V CERM 402 2 Left ALS Filter CRITICAL U6405 RTALS_OP_IN and RTALS_OP_COMP need to be matched 4 6 V+ RTALS_PHOTODIODE R6430 48C3 5C1 LTALS_OUT 1 3.48K 1% 1/16W MF-LF 402 2 51A7 1 ALS_LEFT OUT 1 20% 6.3V X5R 402 GND_SMC_AVSS R6400 1 BS520EOF 0.22UF 2 3 RTALS_OP_IN 2 1 5.1M TH 5% 1/16W MF-LF 402 2 R6410 ALS_RT_OUT 2 4.53K 2 51A7 1 C6400 ALS_RIGHT OUT C6410 0.22UF 2 20% 6.3V X5R 402 GND_SMC_AVSS 0.01UF 2 1 1% 1/16W MF-LF 402 5 V2 1% 1/16W MF-LF 402 CRITICAL PD6400 C6430 1K 1 MAX4236EUTT SOT23-6-LF 1 R6401 Left ALS circuit has 1K series-R 20% 16V CERM 402 1 C6406 1 120K 0.22UF 20% 6.3V X5R 402 51B2 51C4 52B6 55B1 55B3 55B5 55B7 55C1 55C6 55D6 57C2 51B2 51C4 52B6 55B1 55B3 55B5 55B7 55C1 55C6 55D6 57C6 R6406 2 2 5% 1/16W MF-LF 402 RTALS_OP_COMP R6408 1 1 1K 1% 1/16W MF-LF 402 C R6407 15.0K 2 2 1% 1/16W MF-LF 402 C RTALS_GAIN_L 3 D Q6408 2N7002 6D4 IN RTALS_GAIN 1 G SOT23-LF S 2 Keyboard LED Driver B B CRITICAL L6450 61D7 58C7 58C4 55A8 53C4 36D6 31C5 25D8 5D4 5D2 81B3 80B5 80A1 79B8 71A6 67B3 67B1 67A1 66B5 62B1 22uH PP5V_S0 1 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 58C4 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 82D5 82C6 82B3 66B5 34A8 25B4 5A4 21C3 27C3 58C7 82A4 KBDLED_NOT R6451 1 C6450 1 1 1uF 10% 6.3V CERM 402 5% 1/16W MF-LF 402 2 IN KBDLED_SW PP3V3_S0 10K 51C7 2 3.8x3.8x1.5MM 7 VDD 2 CRITICAL SW U6450 MM3120 LLP VOUT 8 81C3 KBDLED_ANODE FB 4 81C3 KBDLED_RETURN THRML_PAD 9 3 CNTRL 6 NC SMC_SYS_KBDLED NC KBDLED_HAS R6452 1 1 1 10K 5% 1/16W MF-LF 402 NC PGND 5 AGND 2 2 C6455 0.22uF 2 20% 25V X5R 603 OUT IN R6455 25.5 1% 1/8W MF-LF 2 805 ALS Support A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 57 1 87 A 8 6 7 5 2 3 4 1 D D C Left Fan PP5V_S0 PP3V3_S0 CRITICAL 61D7 58C4 57B5 55A8 53C4 36D6 31C5 25D8 5D4 5D2 81B3 80B5 80A1 79B8 71A6 67B3 67B1 67A1 66B5 62B1 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 65B3 62A6 61D8 61A5 60D4 60C7 58C4 57B6 71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 82D5 82C6 82B3 82A4 79D3 5A4 21C3 25B4 27C3 33D8 54D4 65D6 79A8 J6550 SM04B-ACH R6550 1 47K 5% 1/16W MF-LF 402 R6555 51B7 SMC_FAN_0_TACH 1 47K 2 5D2 NC SMC_FAN_0_CTL 2N7002DW-X-F G SOT-363 D 3 5D2 5% 1/16W MF-LF 402 R6565 51B7 SMC_FAN_1_TACH 1 47K 2 5D2 NC 2 3 4 R6561 1 6 NC 100K 5% 1/16W MF-LF 402 518S0369 FAN_LT_PWM 51B7 SMC_FAN_1_CTL 2 2N7002DW-X-F G SOT-363 S 6 Q6560 2 1 M-RT-SM 5 1 2 FAN_RT_TACH 5% 1/16W MF-LF 402 Q6560 2 S 47K 2 NC 4 J6560 SM04B-ACH R6560 1 M-RT-SM 5 4 100K 51B7 CRITICAL 5A4 21C3 25B4 27C3 33D8 54D4 65D6 79A8 3 R6551 1 5 PP5V_S0 PP3V3_S0 61D7 58C7 57B5 55A8 53C4 36D6 31C5 25D8 5D4 5D2 81B3 80B5 80A1 79B8 71A6 67B3 67B1 67A1 66B5 62B1 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 65B3 62A6 61D8 61A5 60D4 60C7 58C7 57B6 71D2 67C5 67C3 67B3 67A3 66B6 66B5 66B1 82D5 82C6 82B3 82A4 79D3 1 2 FAN_LT_TACH 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 C Right Fan D 6 5D2 518S0369 FAN_RT_PWM B B Fan Connectors A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 58 1 87 A 8 6 7 3 4 5 2 1 D D 81D4 46C3 46B3 41C5 37D7 37D5 37C3 37A7 32C5 27C5 5D4 81A5 67C5 67C3 66C6 65D1 63B7 60C2 57D4 52B1 46D6 APN:338S0354 PP3V3_S3 1 1 13 14 R66201 C 10K 5% 1/16W MF-LF 402 C6620 C 0.1uF 2 VDD 20% 10V CERM 402 U6620 2 KXPS5-2050 51A5 2 3 5 6 12 SMS_ONOFF_L LGA X CRITICAL Y CS* Z ADDR/SDI SCL/SCLK FF/MOT ENABLE SDA/SDO MOT_ENABLE 7 8 9 SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS 11 4 51B7 51B7 51A7 TP_SMS_FF 10 GND 1 2 1 C6605 0.033UF 0.033UF 20% 10V X7R 402 20% 10V X7R 402 2 Desired orientation when Desired orientation when placed on board bottom-side: 1 +Y +Z (up) C6606 0.033UF 20% 10V X7R 402 Top-through View +Y +X 1 2 placed on board top-side: Package Top B C6604 B 1 +X +Z (dn) M59 placement: Bottom-side Sudden Motion Sensor (SMS) A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 59 1 87 A 8 6 7 2 3 4 5 1 D D 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 33D3 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 62A6 61D8 61A5 60C7 58C7 58C4 57B6 54D4 54B5 82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 PP3V3_S0 TPM 1 TPM C6700 0.1UF 10% 16V 2 X5R 402 1 C6701 0.1UF 10% 16V 2 X5R 402 TPM 1 NOSTUFF C6702 R6705 10% 16V 2 X5R 402 0 5% 1/8W MF-LF 2 805 OMIT 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 33D3 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 62A6 61D8 61A5 60D4 58C7 58C4 57B6 54D4 54B5 82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 IO 53C4 51D7 21D4 5C2 IO 53C5 51C7 21D4 5C2 PP3V3_S0 53C5 51C7 21D4 5C2 NOSTUFF 34D6 1 R6700 LAYOUT NOTE: PLACE WHERE ACCESSIBLE C 53C4 51D7 21D4 5D2 52B3 IO IO IN 53C4 51C7 21C5 5C2 IN 53B5 52A2 51C5 23C5 5C2 IN 26 LAD0 23 20 LAD1 TPM VDD TSSOP VDD 17 LAD2 LAD3 PCI_CLK_TPM LPC_FRAME_L 21 LCLK PM_SUS_STAT_L INT_SERIRQ PM_CLKRUN_L 28 27 53C5 51C7 23C8 5C2 IO 53C4 51C5 23C8 5C2 IO 22 16 15 TPM_GPIO1 NC 52C3 10 19 24 TPM R6704 VNC LFRAME* TPM_GPIO2 3 NC 12 NC TPM_XTALI TPM_XTALO TPM VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM 1 NC VBAT LRESET* LPCPD* 0.1UF 1 SERRIRQ CLKRUN/GPIO* R6702 PP/GPIO GPIO_EXPRESS_00 5% 1/16W MF-LF 2 402 (INT PD) PP XTALI/32K_IN 14 XTALO 2 PP3V3_S3 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 63B7 65D1 66C6 67C3 67C5 81A5 81D4 C BASE ADDR = 0X4E/4F GPIO 13 0 5% 1/8W MF-LF 805 10K 6 1 GPIO/SM_DAT NC GPIO/SM_CLK C6703 10% 16V 2 X5R 402 TPM NC 7 2 1 PP3V3_TPM_3VSB 5 VSB TESTBI/BADD/GPIO TESTBI/BADD TESTI 9 8 LAYOUT NOTE: PLACE R6702-03 WHERE ACCESSIBLE TPM_BADD NOSTUFF 1 GND 4 GND0 11 GND1 18 GND2 25 GND3 35D5 3V2 VDD GPIO2 35C5 3V1 CLKRUN* TPM_PP 52C3 3V0 3VSB 0 5% 1/16W MF-LF 2 402 U6700 LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> NOTE: SINCE CURRENT OF VSB IS NOT YET ON SPEC, 1/8W (R6704/R6705) IS USED FOR NOW 1 0.1UF R6703 10K 5% 1/16W MF-LF 2 402 BASE ADDR = 0X2E/2F TPM R6798 26B1 5C4 IN TPM_LRESET_L 1 0 2 5% 1/16W MF-LF 402 TPM_RST_L NOSTUFF B B R6799 52B2 IN SMC_TPM_RESET_L 1 0 2 5% 1/16W MF-LF 402 TPM A SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 60 1 87 A 8 6 7 PPBUS_G3H 64D7 64A6 62D7 61D7 55D3 43D8 42B8 41C6 5C4 5A1 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 58C7 58C4 57B5 55A8 53C4 36D6 31C5 25D8 5D4 5D2 81B3 80B5 80A1 79B8 71A6 67B3 67B1 67A1 66B5 62B1 2 3 4 5 These caps for Q7500 R7530 1 10 1 CRITICAL MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V 10 1 10 1 C7530 499 1 10% 16V X5R 402 C7528 10% 16V X5R 603 9C1 42 41 40 39 38 37 CRITICAL C7546 R7546 0.01uF 470K 10% 16V CERM 402 402 2 2 66B5 66B3 66B2 65B8 IMVP6_NTC_R C 33A4 26A8 26A7 1 51D7 5C4 4.02K 1 C7532 1 26B5 14B6 5A4 OUT VR_PWRGD_CK410_L IN IMVP_VR_ON OUT VR_PWRGOOD_DELAY IMVP6_VR_TT IMVP6_NTC 147K 0.015uF 10% 16V X7R 402 1% 1/16W MF-LF 402 2 R7532 1% 1/16W MF-LF 2 402 2 45 2 3 48 R7547 22 VDD VID6 VID4 BOOT1 OMIT VID5 U7530 47 44 1 5 6 (GND_IMVP6_SGND) IMVP6_SOFT 7 IMVP6_RBIAS 4 BOOT2 26 ISL9504CRZ QFN VID3 UGATE1 VID2 (GND_IMVP6_SGND) IMVP6_VDIFF PHASE1 34 VID0 1 820pF LGATE1 2 2 32 R7536 DPRSLPVR 1.82K 0 1 0 1-Phase CCM 1 0 1 1-Phase DCM 1 1 0 1-Phase DCM 1% 1/16W MF-LF 402 2 20% 25V X5R 603 1 2 2 B 2 RJK0301DPB IMVP6_LGATE1 1 NO STUFF C7501 1 0.0022UF 2 1 2 3 1 2 20% 6.3V X5R 402 R7506 C7502 0.0022UF 10% 50V CERM 402 2 2 1% 1/10W MF-LF 603 10% 50V CERM 402 (IMVP6_ISEN1) IMVP6_UGATE2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm 28 IMVP6_PHASE2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm 30 IMVP6_LGATE2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm 27 CLK_EN* LGATE2 5 VR_ON PGND2 29 VR_TT* ISEN2 C CRITICAL (GND) Q7550 4 PGOOD RJK0305DPB LFPAK 23 IMVP6_ISEN2 19 IMVP6_VSUM IMVP6_OCSET IMVP6_VO 61A2 IMVP6_DROOP NTC CRITICAL VSUM SOFT 8 VO 18 RBIAS 16 C7542 R7540 IMVP6_DFB VSEN 14 C7580 10% 25V CERM 402 NC 1 1 R7541 5 R7557 1 1 CRITICAL 2 1 5% 50V CERM 402 5% 1/16W MF-LF 402 2 Q7551 RJK0301DPB LFPAK R7542 5 2 2 C7555 R7555 13.7K 180pF 1% 1/16W MF-LF 2 402 2 2 SM-IHLP 1 4 1 C7540 1K TPAD 21 10% 50V CERM 402 2 1% 1/16W MF-LF 402 RTN 15 VW 1 0.001uF 3.01K 1 FB2 COMP 0.36UH-30A-1.2M-OHM (IMVP6_PHASE2) NO STUFF VDIFF 10 L7555 1 2 3 CRITICAL 1% 1/16W MF-LF 402 Q7552 4 10K 1 0.22UF 1 2 1% 1/16W MF-LF 402 RJK0301DPB 1 2 3 LFPAK (IMVP6_VO) 1 1 C7543 1 2 470pF R7543 R7548 11K R7556 3.65K 1 NO STUFF 1 5.23K 1% 1/16W MF-LF 402 2 10% 16V CERM 402 2 20% 6.3V X5R 402 49 GND_IMVP6_SGND 10% 50V CERM 402 0.22UF 2 1% 1/16W MF-LF 402 1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm IMVP6_ISEN1 PHASE2 GND C7535 C7505 10K 1 Q7502 3.65K 0.01uF 10% 50V CERM 402 5 LFPAK NO STUFF MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm (IMVP6_FB) 820pF RJK0301DPB 3V3 R7533 C7534 Q7501 LFPAK IMVP6_PHASE1 (GND) 1 1 0.22uF 20% 25V X5R 603 1% 1/16W MF-LF 402 2 NO STUFF C7551 1 0.0022UF 2 1 2 3 C7552 0.0022UF 10% 50V CERM 402 2 2 1% 1/10W MF-LF 603 10% 50V CERM 402 B IMVP6_VO_R 2 IMVP6_COMP_RC D 5% 1/16W MF-LF 402 2 C7500 1 1 R7507 CRITICAL IMVP6_UGATE1 0.0068uF 1% 1/16W MF-LF 402 1 0.22uF 301 1% 1/16W MF-LF 402 2 5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm ISEN1 24 UGATE2 PGD_IN FB 9 C7550 67D1 67D3 5B2 8B5 8D7 9D7 55A6 55D7 PPVCORE_S0_CPU 2 1 PSI* 11 25 1 CCM IMVP6_BOOT1 IMVP6_BOOT2 IMVP6_VDIFF_RC R7535 1 2-Phase PGND1 33 DFB 17 12 IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW 2.0K 10% 50V CERM 402 1 L7505 (Inductors limit) DPRSTP* NO STUFF 1 1 VID1 DROOP 13 35 10% 16V X5R 603 CRITICAL PVCC 36 2 0.36uH-30A-1.2M-OHM 1 2 3 OCSET 5D7 C7533 0 31 1 7B3 5C4 21C4 20% 16V POLY CASED2E-SM R7505 46 9C1 20% 16V POLY CASED2E-SM 2 C7561 1uF 33uF CRITICAL IN CPU_DPRSTP_L 87C6 5C4 IMVP_DPRSLPVR 7A3 IN CPU_PSI_L 5C4 IN P1V5P1V05S0_PGOOD 9C1 2 1 C7560 33uF 36A max output 2 VIN 9C1 CRITICAL 1 C7515 SM-IHLP 4 43 9C1 2 10% 16V X5R 603 (IMVP6_PHASE2) 2 20 9C1 20% 16V POLY CASED2E-SM 1 2 3 4 9C1 1 1uF 2 1 5C4 IMVP6_VID<6> 5C4 IMVP6_VID<5> 5C4 IMVP6_VID<4> 5C4 IMVP6_VID<3> 5C4 IMVP6_VID<2> 5C4 IMVP6_VID<1> 5C4 IMVP6_VID<0> (IMVP6_NTC) RJK0305DPB 1uF 2 1 2 C7511 LFPAK 0.1uF R7544 1% 1/16W MF-LF 402 Q7500 4 20% 6.3V CERM 603 1 R7545 PM_DPRSLPVR CRITICAL DPRSLPVR DPRSTP* PSI* Operation Mode C7531 1% 1/16W MF-LF 402 2 IN C7529 PPVIN_S0_IMVP6_R 499 87C6 23C3 14B7 5B4 1 33uF Vout = Variable 10% 6.3V CERM 402 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 1 1 C7510 CRITICAL 1uF PP3V3_S0_IMVP6_R 2 5% 1/16W MF-LF 402 2 5% 1/16W MF-LF 402 R7528 PP3V3_S0 2 R7531 PPBUS_G3H 64D7 64A6 62D7 61D4 55D3 43D8 42B8 41C6 5C4 5A1 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 1 4.7uF PP5V_S0_IMVP6_VDD 2 5% 1/16W MF-LF 402 82D5 82C6 82B3 82A4 79D3 66B6 66B5 66B1 65D6 65B3 57B6 54D4 54B5 52D3 49C7 33D3 33C7 29A6 29A3 28A6 26B6 26B4 25D8 25D3 25C6 24B5 24B3 23D5 23B3 22B5 17C6 14D6 14C7 10C5 5D4 5A4 21D3 21C3 20B4 20A4 19C7 19C6 25C4 25B8 25B4 25A4 24D3 24C3 27D8 27D5 27D3 27C3 26D1 26B8 49C4 49B5 40B6 36D6 34A8 33D8 62A6 61A5 60D4 60C7 58C7 58C4 79A8 71D2 67C5 67C3 67B3 67A3 These caps for Q7550 PP5V_S0 5 D 1 (IMVP6_VW) 1 CRITICAL R7534 1 1 C7537 107K 1% 1/16W MF-LF 402 1 47pF 5% 50V CERM 402 2 2 2 R7537 R7549 4.42K C7544 1% 1/16W MF-LF 402 0.22uF 20% 6.3V X5R 402 1 10KOHM-5% R7581 0603-LF 2 2 1 (IMVP6_ISEN2) (IMVP6_COMP) 0 CPU_VCCSENSE_P 2 8B6 87B6 5% 1/16W MF-LF 402 (IMVP6_VSUM) (IMVP6_VO) 87B6 R7582 IMVP6_VSEN_P 87B6 IMVP6_VSEN_N 0 1 NO STUFF C7541 1 0.22UF XW7530 SM 2 20% 6.3V X5R 402 C7582 C7581 1 0.01uF 2 10% 16V CERM 402 28A6 49C4 60D4 67A3 82B3 27D8 49B5 60C7 66B6 82A4 C7598 PP3V3_S0 2 1 29A6 29A3 49C7 61D8 67B3 82C6 CPU VCore Current Sense 52D3 1 33C7 26B6 25C4 0.01uF 24C3 10% 22B5 21D3 19C7 19C6 16V 10C5 5D4 5A4 2 CERM 17C6 14D6 14C7 402 21C3 20B4 20A4 24B5 24B3 23D5 23B3 25B8 25B4 25A4 24D3 26B4 25D8 25D3 25C6 27D5 27D3 27C3 26D1 26B8 40B6 36D6 34A8 33D8 33D3 58C7 58C4 57B6 54D4 54B5 66B5 66B1 65D6 65B3 62A6 79D3 79A8 71D2 67C5 67C3 82D5 1 C7595 1uF 10% 6.3V CERM 402 1 R7598 1 1M CPUISENS_NEG_RC 2 1% 1/16W MF-LF 402 NO STUFF 1 2 1% 1/16W MF-LF 402 CRITICAL 0 1 2 C7594 20% 10V CERM 402 IMVP6 CPU VCore Regulator U7595 HPA00141AIDCKR A SC70-5 55B8 Vout OUT 4 CPUVCORE_IOUT 5 + 1 SYNC_MASTER=M59_MLB V+ SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY V- = Gain * ((2.1 mV/A * Iload) + Voffset) 8B6 87B6 5% 1/16W MF-LF 402 0.1uF 2 2 CPU_VCCSENSE_N R7594 30.1K CPUISENS_NEG 2 10% 50V CERM 402 1 R7593 470pF 2 5% 1/16W MF-LF 402 - 2 3 Voffset = (Vdrp_offset * Kdroop) + Vamp_offset THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE Gain R7592 = Rc / (Ra + Rb) 1 1M 2 R7591 CPUISENS_POS 1 30.1K Voffset worst-case ~2.3mV (+/- ~1A offset) C7592 Vout @ 36A = 2.44V-2.60V 470pF 1 2 II NOT TO REPRODUCE OR COPY IT IMVP6_DROOP III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 61C6 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 SIZE 2 APPLE COMPUTER INC. 10% 50V CERM 402 8 7 6 5 4 DRAWING NUMBER D SCALE SHT NONE 3 2 REV. 051-7164 06004 OF 61 1 87 A 8 6 7 2 3 4 5 1 PPBUS_G3H 64D7 64A6 61D7 61D4 55D3 43D8 42B8 41C6 5C4 5A1 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 CRITICAL 1 CRITICAL 1 C7640 1uF 20% 16V POLY CASED2E-SM 2 1 C7641 33uF 20% 16V POLY CASED2E-SM 5% 1/16W MF-LF 402 2 C7681 1 1 1uF 33uF 10 10% 16V X5R 603 2 C7680 R7600 10% 16V X5R 603 2 2 D D MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 1 1 C7623 0.1uF 2 62B3 62D3 PP5V_S5_P5VP1V5_INTVCC 1 C7620 10% 16V X5R 402 1 2 R7629 D CRITICAL 1% 1/16W MF-LF 402 2 PP5V_S5 G 5% 1/16W MF-LF 402 4 S C7624 1 CRITICAL 3 2 1 0.1uF L7620 2.0UH (Q7621 limit) 1 20% 10V CERM 402 2 2 C7650 1 1 150UF 20% 6.3V CERM 805 20% 6.3V 2 POLY CASE-C3 P5VS5_BOOST BOOST1 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm P5VS5_SW SW1 26 TG1 P5VS5_BG NC 2 Q7621 C7622 G MICROFET3X3 C7651 2 C7621 1 30 1 LTC3728LXC P5VS5_VOSNS 1 P5VS5_ITH 5 P5VS5_RUNSS 1 C7627 47PF C7626 BG2 PLLIN PLLFLTR SENSE1+ SENSE2+ SENSE2- VOSENSE1 VOSENSE2 ITH2 ITH1 28 2 402 470pF 21 10% 50V CERM 402 5% 50V CERM 402 RUN_SS1 15 P1V5S0_SW MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm P1V5S0_BG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm P5VP1V5_FSEL 2 11 9 P1V5S0_VOSNS 8 P1V5S0_ITH SGND 1 33K 0.1uF 5% 1/16W MF-LF 2 402 10% 25V X7R 402 C7630 2 33 R7625 C7628 20% 10V CERM 402 27 INTVCC 20 NC1 10 NC2 16 NC3 NC4 29 2 C7664 Vout = 1.49V 1 0.1uF 2 CRITICAL 3 8A max output L7660 20% 10V CERM 402 62A8 66C5 67C6 67C8 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 PP1V5_S0 MICROFET3X3 1 2.2uH-14A 2 (L7660 & Q7660 limit) 1 2 IHLP2525CZ-SM CRITICAL 1 6 7 8 C7690 62B3 CRITICAL 1 C7662 2 2 Q7661 0.001uF 10% 50V CERM 402 1 P1V5S0_RUNSS 20% 6.3V CERM 805 1 1 2 3 C7666 470pF 2 NC NC NC NC 1 C7667 100pF 10% 50V CERM 402 5% 50V CERM 402 2 2 1 C7665 1 22UF NO STUFF 10% 25V X7R 402 C 20% 2 2.5V POLY CASE-D2E-LF C7691 SO-8 C7692 330UF 20% 6.3V CERM 805 IRF7832Z 4 C7661 1 32 1% 1/16W MF-LF 402 FDM6296 G 4 NC PGOOD 1.21K CRITICAL 22UF P1V5S0_SNS_R_P P1V5S0_SNS_R_N 12 7 EXTVCC 1 1000pF 2 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 3_3VOUT 2 6 10K MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm P1V5S0_BOOST 13 FCB P5VS5_ITH_RC NO STUFF 1% 1/16W MF-LF 402 2 P1V5S0_TG 17 18 10% 16V X5R 402 S 14 RUN_SS2 1 C7625 47pF 5% 50V 1 SW2 0.1uF 2 2 Q7660 5% 1/16W MF-LF 402 1000pF 10% 25V X7R 402 2 CERM 1 R7628 BOOST2 U7600 SENSE1- 4 52.3K 1% 1/16W MF-LF 402 2 2 1000pF 2 R7627 1 10% 50V CERM 402 NO STUFF 1 3 P5VS5_SNS_P P5VS5_SNS_N 1 0.001uF 4 S 20% 6.3V CERM 805 TG2 CRITICAL BG1 D 22UF 2 P5VS5_TG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 1% 1/16W MF-LF 402 R7669 1 D R7664 0 2 2 C7660 5 5 FDM6296 1 5% 1/16W MF-LF 402 2 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 5 CRITICAL 1 1M VIN MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 22UF MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm R7670 1 5% 1/16W MF-LF 2 402 QFN SM-IHLP CRITICAL P1V5S0_BOOST_RC R7630 2 1% 1/16W MF-LF 402 2 1M 0 Q7620 MICROFET3X3 11.5A max output C 1 R7624 1 FDM6296 Vout = 4.98V C7652 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 5 23.7K 67C1 67B1 66D8 66B8 62A4 52B5 47C7 25C8 5D4 65D6 65B7 64C8 62B6 62B2 71D7 67C3 2 1 3.65K CMDSH-3 10% 16V X5R 603 P5VS5_BOOST_RC R7660 1 SOD-323 1uF 2 909 2 62B3 62D6 D7664 C7600 CMDSH-3 1% 1/16W MF-LF 402 R7663 CRITICAL 1 1 SOD-323 4.53K 2 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12V 1 D7624 R7620 1 0.1uF PP5V_S5_P5VP1V5_INTVCC PPVIN_S5_P5VP1V5_R CRITICAL 1 0.1uF 10% 16V X5R 402 PGND 2 C7663 10% 16V X5R 402 THRML_PAD 1 4.02K 1% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 1 34.0K 470pF 10% 50V CERM 402 2 R7667 1% 1/16W MF-LF 2 402 2 P1V5S0_ITH_RC C7670 R7665 1 20% 10V CERM 402 NO STUFF 1 C7668 10K 0.1uF 19 R7623 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm R7668 39.2K 1000pF 5% 1/16W MF-LF 402 2 2 1 1 10% 25V X7R 402 1% 1/16W MF-LF 2 402 2 GND_P5VP1V5_SGND VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 1 XW7600 C7607 Connect to RUNSS pins to control outputs. If unconnected, powers up with VIN. NOTE: Be aware of pull-ups to VIN on these signals. B 2 1 Vout = 0.8V * (1 + Ra / Rb) TP_P5V_P1V5_PGOOD SM 0.01uF 66C1 66C2 2 10% 16V CERM 402 PP5V_S5_P5VP1V5_INTVCC 62D3 62D6 VOLTAGE=5V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 5V S0 FET P5VP1V5_SKIP 1 C7601 0 5% 1/16W MF-LF 2 402 1 1 4.7uF 20% 6.3V CERM 603 P5VP1V5_FCB R7603 65D6 65B7 64C8 62C8 62B6 62A4 52B5 47C7 25C8 5D4 71D7 67C3 67C1 67B1 66D8 66B8 2 5% 1/16W MF-LF 402 2 P5VP1V5_FSEL PP5V_S5 1 C7605 1uF 10% 6.3V CERM 402 2 5% 1/16W MF-LF 2 402 6 7 CRITICAL Q7615 R7615 1 R7607 0 3 62C4 P5VP1V5_CONT 1 PP5V_S5 30K 2 65D6 65B7 64C8 62C8 62B2 62A4 52B5 47C7 25C8 5D4 71D7 67C3 67C1 67B1 66D8 66B8 1 C7602 1uF 2 10% 6.3V CERM 402 R7604 1 10K C7604 66C7 66C6 48C3 6A2 6A1 5C1 PM_SLP_S3_LS5V 2 1 2 IRF7707PBF 4 P5VS0_EN_L_RC TSSOP 5% 1/16W MF-LF 402 0.01uF 5% 1/16W MF-LF 2 402 100K 10% 16V CERM 402 PP1V5_S0 1 2 1 8 C7615 C7616 R7675 0.002 1% 1/4W MF-LF 1206 1 C7672 22UF 20% 2 6.3V CERM 805 1 C7671 C7675 22UF 0.1UF 20% 2 6.3V CERM 805 1 R7671 NB1V5_ISENSE_R1_N 1 R1- V+ R7672 2.0K A 1% 1/16W MF-LF 2 402 NB1V5_ISENSE_R1_P 8 R1+ 3 V- + 2 65D6 65B7 64C8 62C8 62B6 62B2 52B5 47C7 25C8 5D4 71D7 67C3 67C1 67B1 66D8 66B8 SM-LF PP5V_S5 PP5V_S3 5B2 5D4 45C3 52B8 67B1 67B3 81C4 81C6 6 5 P1V5S0_NB_IOUT 6 4 55B5 5V / 1.5V Power Supply 2 CRITICAL 1 U7670 5 SYNC_MASTER=M59_MLB MSOP 3 R7674 2 NOTICE OF PROPRIETARY PROPERTY C7610 0.0022uF 1 100K 1% 1/16W MF-LF 402 SYNC_DATE=09/15/2006 INA326EA-250 NB1V5_ISENSE_R2 1 R7610 C7674 0.001UF 2 66B7 66B6 65D3 PM_SLP_S4_LS5V 10% 50V CERM 402 1 100K 5% 1/16W MF-LF 402 2 1 P5VS3_EN_L_RC THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING 2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 10% 50V CERM 402 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SHT NONE 7 6 5 4 3 2 REV. 051-7164 SCALE 8 20% 6.3V CERM 805 CRITICAL PLACE C7675 NEAR U7670 PIN 7 R2 C7617 FDC638P 4 1 1 Q7610 Placement Note: 7 2 2 22UF 1% 1/16W MF-LF 402 2 20% 6.3V CERM 805 5V S3 FET 10 10% 16V X5R 402 1 22UF 10% 50V 2 CERM 402 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 65B3 65D6 66B1 66B5 66B6 82D5 19D7 67B6 67C6 67C8 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 16D1 1 2 PP3V3_S0 5D4 13C5 NB1V5_ISENSE_VCC 13D2 19D6 17B6 PP1V5_S0_NB 80B5 81B3 67A1 67B1 67B3 55A8 57B5 58C4 5D2 5D4 25D8 31C5 36D6 53C4 58C7 61D7 66B5 71A6 79B8 80A1 PP5V_S0 1 5 0.0022uF 67C8 67C6 66C5 62C1 48B6 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 25D6 25C8 25C6 25C2 25B6 25B2 B R7606 06004 OF 62 1 87 A 8 6 7 2 3 4 5 1 2.5V S0 FET Q7720 2.5V S3 Regulator 67B8 67B6 63D4 63C3 39D3 5A4 FDC637AN PP2V5_S3 PP2V5_S0 5D4 17C6 17D6 19A4 19A6 19A8 19C5 19D7 66B5 67A6 67A8 67B6 82C5 82D3 SOT23 1 D 2 79D5 67D5 67D3 67C3 66C5 65D8 24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 65D2 65D1 65C8 56D4 26C5 25D2 25C8 25B6 24C3 24B3 C7720 PP3V3_S5 1 1 22uF 20% 6.3V CERM 805 2 41C3 PPVIN_S3_P2V5S3_SVIN VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm 5% 1/16W MF-LF 402 2 10% 50V CERM 402 C7701 0.1uF 2 41C4 41C3 PM_SLP_S3_LS5V_L 1 D 3 S 4 AVINPVIN 6 5 EN U7700 TPS62510 BQA P2V5S3_SW 1 SW 1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm MODE 1 1 R7707 10pF 5% 50V CERM 402 2 (U7700 limit) 1% 1/16W MF-LF 2 402 1 1 C7709 22UF 1 R7708 2 C7711 Q7721 22UF 20% 6.3V CERM 805 67B8 67B6 63D4 63D3 39D3 5A4 20% FDC637AN PP2V5_S3 805 1 2 5D4 67A6 67A8 77A8 77C6 78C8 82D7 D 2 1 C7710 C7721 22UF 1% 1/16W MF-LF 2 402 PP2V5_D3C SOT23 1 2 6.3V CERM 200K TP_P2V5S3_P1V2S3_PGOOD 2.5V D3Cold FET 1.5A max output 634K 2 11 AGND PGND THRM_PAD 3 5A4 39D3 63C3 63D3 67B6 67B8 Vout = 2.50V 8 PG PP2V5_S3 P2V5S3_VFB 4 FB 2 SM-MSS5131 C7706 7 P2V5S0_EN_RC 2 2.2uH-1.9A-23M-OHM CRITICAL OVT 100K 5% 1/16W MF-LF 402 CRITICAL L7700 10% 16V X5R 402 PM_SLP_S3BATT_L 66B8 66B7 63B5 G 6 2 R7720 66D5 66D4 1 10 C7700 5 1 0.0022uF R7700 1 9 D 5 1 0.0022uF 20% 6.3V CERM 805 10% 50V CERM 402 C7722 0.01UF 6 G 3 10% 50V X7R 402 2 S 2 4 R7721 160K 71C8 66D8 66D7 66D4 63B3 C 1 P1V2R2V5D3C_EN_LS5V 2 P2V5D3C_EN_RC C 5% 1/16W MF-LF 402 Vout = 0.6V * (1 + Ra / Rb) 1.2V S3 Regulator 81D4 46C3 46B3 41C5 37D7 37D5 37C3 37A7 32C5 27C5 5D4 81A5 67C5 67C3 66C6 65D1 60C2 59C6 57D4 52B1 46D6 PP3V3_S3 5% 1/16W MF-LF 402 2 41C4 5D7 P1V2S3_RUNSS 0 C7751 LTC3412 P1V2S3_RT 5 7 P1V2S3_ITH P1V2S3_MODE 3 6 PGOOD 2 P1V2S3_ITH_RC 1 C7753 C7754 0.0022uF 2 10% 50V CERM 402 1 C7757 2 10% 50V CERM 402 22pF 5% 50V CERM 402 1 2 1.2V D3Cold FET L7750 14 1.0UH-3.48A P1V2S3_SW MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 1 1 PP1V2_S3 GND_P1V2S3_SGND C7755 1 C7750 22pF 2 5% 50V CERM 402 XW7750 B D 5 1 C7758 1 2.5A max output C7770 22UF 22UF 0.0022uF 20% 6.3V CERM 805 20% 6.3V CERM 805 10% 50V CERM 402 2 1 C7756 22UF 2 SM 20% 6.3V CERM 805 (Switcher limit) 2 1 C7759 20% G 3 1 S 4 2 R7770 22UF 2 6.3V CERM 100K 71C8 66D8 66D7 66D4 63C3 1 P1V2R2V5D3C_EN_LS5V 2 P1V2D3C_EN_RC 5% 1/16W MF-LF 402 805 2 VOLTAGE=0V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 5D4 67C6 67D6 67D8 70A1 70C7 77B8 82D7 2 6 1% 1/16W MF-LF 402 2 1 5A4 5D4 39A8 39D7 63B3 67D6 67D8 Vout = 1.205V SM-LF 47.0K 1% 1/16W MF-LF 2 402 PP1V2_D3C SOT23 2 R7750 1 R7754 Q7770 PP1V2_S3 FDC637AN 11 17 13 67D8 67D6 63B3 39D7 39A8 5D4 5A4 CRITICAL 309K 470pF 20% 6.3V CERM 805 66B7 15 12 5% 1/16W MF-LF 2 402 22UF TP_P2V5S3_P1V2S3_PGOOD 66B8 63C8 THERM SGND PGND PAD 0 2 10 VFB 8 Burst 1% 1/16W MF-LF 402 2 4 R7756 2 C7752 CRITICAL ITH SYNC/MODE SW 1 8.25K 1 TSSOP-LF RT RUN/SS R7753 1 1 20% 6.3V CERM 805 U7750 5D7 1 22UF SVIN PVIN 5% 1/16W MF-LF 2 402 Connect RUNSS off-page to control If unconnected, powers up with PVIN. NOTE: Be aware of pull-up on this signal. B 9 CRITICAL R7755 1 Continuous 1M 16 NO STUFF 1 R7757 1 P1V2S3_VFB R7751 1 61.9K 1% 1/16W MF-LF 402 2 P1V2S3_VFB_DIV R7752 1 30.9K 1% 1/16W MF-LF 402 A 2.5V & 1.2V Regulators 2 SYNC_MASTER=M59_MLB Vout = 0.8V * (1 + Ra / (Rb + Rc)) SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 63 1 87 A 8 6 7 2 3 4 5 1 D D PPBUS_G3H 64A6 62D7 61D7 61D4 55D3 43D8 42B8 41C6 5C4 5A1 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 PP5V_S5 62C8 62B6 62B2 62A4 52B5 47C7 25C8 5D4 71D7 67C3 67C1 67B1 66D8 66B8 65D6 65B7 C7800 C7802 1 10% 6.3V CERM 402 1 1 1uF 1UF 10% 16V X5R 603 2 C7830 1 20% 16V POLY CASED2E-SM 2 C7831 1 C7832 1uF 33uF 2 2 1uF 10% 16V X5R 603 2 10% 16V X5R 603 R7801 10 1 1% 1/16W MF-LF 402 P1V8S3_V5FILT 2 C7801 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V 1 5 4.7UF 20% 6.3V CERM 603 2 CRITICAL U7800 R78031 182K 1% 1/16W MF-LF 402 2 C7803 1 THRM_PAD 0.1UF 10% 16V X5R 402 2 GND DRVH 13 DRVL 9 Q7820 4 P1V8S3_DRVH RJK0305DPB MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm LFPAK C LL 12 CRITICAL VOUT 3 L7820 1 2 3 1.2UH 1 P1V8S3_LL PGOOD 6 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE PGND 2 FDA1055 5 29D6 31C5 32C6 37B2 64A6 5B2 5D4 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 67B6 67B8 PP1V8_S3 8 PM_SLP_S4_L 7 51C5 23C3 5C4 5C1 6A2 6A1 48C3 47C7 41B6 66B8 66A6 15 C 4 V5FILT 10 V5DRV TPS51117RGY_QFN14 QFN 1 EN_PSV P1V8S3_TON 2 TON CRITICAL P1V8S3_TRIP 11 TRIP P1V8S3_VBST14 VBST 5 VFB CRITICAL R7821 1 Q7821 4 P1V8S3_DRVL RJK0303DPB MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm LFPAK 1% 1/16W MF-LF 402 2 CRITICAL Q7822 4 R7804 1 2 3 RJK0303DPB R7822 1 LFPAK 12.1K C7842 1% 1/16W MF-LF 2 402 C7820 1 2 3 P1V8S3_FB (L7820 limit) 20% 2.5V 2 POLY CASE-D2E-LF 1 47PF 5% 50V CERM 402 2 1 15K 5% 1/16W MF-LF 402 2 18A max output 1 330UF 21K 5 1 Vout = 1.825V C7841 1 22UF 2 (P1V8S3_FB) C7843 330UF 20% 6.3V CERM 805 20% 2 2.5V POLY CASE-D2E-LF Vout = 0.75V * (1 + Ra / Rb) B B TP_P1V8S3_PGOOD 66C1 66C2 1.8V D3Cold FET CRITICAL Q7845 PP1V8_D3C FDM6296 MICROFET3X3 29D3 29B2 28D6 28D3 28B2 19D7 16B6 14C2 5D4 5B2 67B8 67B6 64C1 37B2 32C6 31C5 29D6 64D7 62D7 61D7 61D4 55D3 43D8 42B8 41C6 5C4 5A1 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 PP1V8_S3 PPBUS_G3H 2 5 R7846 1 1 5% 1/16W MF-LF 402 P1V8D3C_EN C7845 0.0047UF 470K A 1 D 66D6 66D5 5D4 67B6 67B8 72B8 73A5 73A8 73B5 73B8 75D5 75D8 76D5 76D8 82D7 3 2 2 R7845 1 150K 2 10% 25V CERM 402 P1V8D3C_EN_RC S G 4 C7846 1 1 2 2 22UF 20% 6.3V CERM 805 C7847 22UF 20% 6.3V CERM 805 1.8V Supply SYNC_MASTER=(MASTER) 5% 1/16W MF-LF 402 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 64 1 87 A 8 6 7 2 3 4 5 1 Q7947 3.3V S0 FET 3.3V S5 Regulator PP5V_S5 PPBUS_G3H FDC638P 65B7 64C8 62C8 62B6 62B2 62A4 52B5 47C7 25C8 5D4 71D7 67C3 67C1 67B1 66D8 66B8 SM-LF PP3V3_S0 61D7 61D4 55D3 43D8 42B8 41C6 5C4 5A1 79B7 71D7 69C1 68D5 67C3 67C1 65B7 64D7 64A6 62D7 3.3V S3 FET 6 67D3 67C3 66C5 65D2 65D1 65C8 63D8 56D4 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 26C5 25D2 25C8 25B6 24C3 24B3 24A5 23D8 79D5 67D5 PP3V3_S5 Q7945 5 4 2 C7901 1 1uF 10% 16V X5R 603 1 C7900 1 CRITICAL 2 20% 2 16V POLY CASED2E-SM D 66D5 1 P3V3S0_EN_L 1 P3V3S0_EN_L_RC 2 2 C7902 NO STUFF 2 R7949 66A8 66A6 20% 6.3V CERM1 603 5% 1/16W MF-LF 402 0 5D7 P3V3S5_FSET 7 P3V3S5_EN_RC P3V3S5_FCCM 4 3 16 1 10% 16V CERM 402 3.3V D3Cold FET Q7948 2 2 1% 1/16W MF-LF 402 PP3V3_D3C 6 5 4 2 C R7908 P3V3S5_COMP 5 P3V3S5_FB 1 C7907 51.1K 470pF 1% 1/16W MF-LF 402 10% 50V CERM 402 150K P3V3D3C_EN_L 66D5 66D7 1 2 UG C7909 2 2 FSET R7945 5 0.22uF 66B7 66B6 62A4 D 20% 6.3V X5R 402 EN FCCM PGOOD COMP BOOT PHASE ISEN 6 FB 8 VO CRITICAL L7920 1 R7905 0 2 C7948 C7908 0.022uF 1 5% 1/16W MF-LF 402 2 2 5.62K PP3V3_S5 2 2 D CRITICAL 4 2 10% 25V X7R 402 1 1 2 2 1 R7922 2 C7942 150UF 20% 2 6.3V POLY CASE-C3 1 5% 1/16W MF-LF 402 C7941 1 22UF 732 20% 6.3V CERM 805 0.1% 1/16W MF-LF 402 2 SM 1 20% 6.3V CERM 805 0 3 XW7900 GND_P3V3S5_SGND 2 1 1000pF 20% 16V CERM 402 (L7920 limit) 22UF R7920 NO STUFF C7949 C7940 MICROFET3X3 S C7921 1 10% 25V CERM 402 P3V3S5_FB_RC FDM6296 G MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 67D5 79D5 65C8 65D2 65D8 25B6 25C8 25D2 23D1 23D4 23D8 5D4 11B5 22C6 22D8 23A7 23B7 24A5 24B3 24C3 26C5 56D4 63D8 66C5 67C3 67D3 4.5A max output C7920 0.0047uF 0.1% 1/16W MF-LF 402 2 Q7921 P3V3S5_LG 1 3.32K 5 10 Vout = 3.32V R7921 1 IHLP 1% 1/16W MF-LF 402 0.01uF 10% 16V CERM-X5R 402 4.7uH 3 R7910 11 17 1 2 1 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE THRML PAD 1 1 P3V3S5_ISEN PGND 2 10% 50V CERM 402 MICROFET3X3 P3V3S5_PHASE 15 9 P3V3S3_EN_L_RC 2 5% 1/16W MF-LF 402 S MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 13 1 FDM6296 G 4 1 100K PM_SLP_S4_LS5V CRITICAL Q7920 P3V3S5_UG 14 NO STUFF 10% 2 25V CERM 402 3 1 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 2 0.0047uF R7948 CRITICAL P3V3S5_COMP_R 82A7 80B2 77C6 74D6 71C4 71A4 67A3 67A5 71B8 74B2 77B7 77D2 80D5 82D7 FDC638P 1 QFN VIN 1 0 5% 1/16W MF-LF 402 LG 1 2 1 R7909 R7906 57.6K 0.01UF PP3V3_S5 D C7945 0.0022uF P3V3S5_BOOT 1 65D8 25D2 23D8 22C6 23B7 24C3 63D8 67D3 VCC ISL6269BCRZ 2 C7906 67D5 65D1 25B6 23D1 5D4 22D8 24A5 26C5 66C5 2 PVCC U7900 RSMRST_PWRGD SM-LF 12 2 1 5D7 79D5 65D2 25C8 23D4 11B5 23A7 24B3 56D4 67C3 1 2.2UF R7904 5% 1/16W MF-LF 402 52A5 52A4 51D7 2 3 0 1 5 4 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1 52A4 P5VS5_PGOOD PP3V3_S5 P3V3S5_BOOT_R 10% 25V CERM 402 5% 1/16W MF-LF 402 79D5 67D5 67D3 67C3 66C5 65D8 24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 24B3 1 0.0047uF 100K PP3V3_S3 6 33UF 20% 6.3V CERM1 603 C7947 SM-LF C7930 2.2UF 2 3 R7947 81D4 66C6 67C3 57D4 59C6 46B3 46C3 37C3 37D5 5D4 27C5 32C5 37A7 37D7 41C5 46D6 52B1 60C2 63B7 67C5 81A5 FDC638P 1 2 C 2 P3V3D3C_EN_L_RC 5% 1/16W MF-LF 402 Vout = 0.6V * (1 + Ra / Rb) 1.05V Current Sense CRITICAL C7980 P1V05ISENS_NTC 1 33uF 20% 16V POLY CASED2E-SM 1.05V S0 Regulator PP5V_S5 5A1 PPBUS_G3H 65D6 64C8 62C8 62B6 62B2 62A4 52B5 47C7 25C8 5D4 71D7 67C3 67C1 67B1 66D8 66B8 64A6 62D7 61D7 61D4 55D3 43D8 42B8 41C6 5C4 79B7 71D7 69C1 68D5 67C3 67C1 65D6 64D7 1 2 R7996 CRITICAL 1 R7997 0 5% 1/16W MF-LF 402 82D5 82C6 82B3 66B5 66B1 65D6 62A6 61D8 61A5 60D4 60C7 40B6 36D6 34A8 33D8 33D3 33C7 29A6 29A3 25D8 25D3 25C6 25C4 25B8 25B4 25A4 24D3 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 20B4 28A6 27D8 27D5 27D3 27C3 26D1 26B8 26B6 26B4 58C7 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 PP3V3_S0 0603-LF 2 C7951 1uF 10% 16V X5R 603 R7994 C7950 2 1 1 2.2UF 20% 6.3V CERM1 603 2 C7990 2 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm C7952 NO STUFF 1 20% 6.3V CERM1 603 5% 1/16W MF-LF 402 P1V05S0_FSET VCC PVCC 2 5% 1/16W MF-LF 402 ISL6269BCRZ 7 QFN VIN CRITICAL FSET 1 4.7 U7950 1 5D7 R79591 2 12 2.2UF R7954 0 2 1 UG 14 C7959 2 D 20% 6.3V X5R 402 CRITICAL P1V05S0_UG FDM6296 PM_SLP_S3_L 4 P1V05S0_FCCM P1V5P1V05S0_PGOOD 16 66B2 61C7 5C4 66B5 66B3 5D7 1 C7956 1 MICROFET3X3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 2 2 P1V05S0_COMP 5 BOOT PHASE ISEN R7956 1 57.6K 0.01UF 10% 16V CERM 402 3 EN FCCM PGOOD COMP 1% 1/16W MF-LF 402 R7958 C7957 30.9K 2 1 15PF 1% 1/16W MF-LF 402 5% 50V CERM 402 P1V05S0_FB 6 FB 8 VO THRML PAD 2 17 13 15 9 LG 11 PGND 10 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1 2.8K 0 2 7 CRITICAL 20% 16V CERM 402 P1V05S0_LG R7991 1 20.0K 10% 25V X7R 402 2 4 1 1 2 P1V05S0_IOUT OUT CRITICAL L7970 3 - B 2 1M 2 C7992 470pF 2 1.8UH 2 1 10% 50V CERM 402 19D7 21C1 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 67D6 67D8 Vout = 1.05V NO STUFF 1 R7970 1 0 10A max output C7985 22UF 5% 1/16W MF-LF 2 402 2 (L7970 limit) 20% 6.3V CERM 805 1 1% 1/16W MF-LF 402 20% 2 2.5V POLY CASE-D2E-LF NO STUFF C7970 1 C7986 0.0022uF 10% 50V CERM 402 2 (P1V05S0_FB) C7989 330UF P1V05S0_FB_RC R7972 1 2 55B3 V- 1% 1/16W MF-LF 402 4.42K 1 SC70-5 R7992 P1V05ISENS_POS 2 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 2 SM A 3 1000pF 1 + V+ 1 3.32K SO-8 XW7950 GND_P1V05S0_SGND 2 R7971 1 IRF7832Z MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm 0.01uF 1 0.22UF PP1V05_S0 Q7971 4 10% 6.3V CERM 402 CRITICAL 8 NO STUFF C7958 5% 1/16W MF-LF 402 6 1uF HPA00141AIDCKR SM-IHLP 5 2 1% 1/16W MF-LF 402 C7971 R7955 3 R7960 P1V05S0_COMP_R 1 2 C7995 U7995 5 C7991 1 1 P1V05ISENS_NEG 2 1% 1/16W MF-LF 402 1 1% 1/16W MF-LF 402 2 P1V05S0_PHASE P1V05S0_ISEN 20.0K 1 649 S MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE 1% 1/16W MF-LF 402 R7993 P1V05ISENS_RC R7990 1 P1V05S0_BOOT 55C3 51C5 32B3 23C3 5C4 43C8 42A8 39C8 66C8 66C6 66B6 1% 1/16W MF-LF 402 10% 6.3V CERM-X5R 402 Q7970 G 4 1 2 2 5 0.22uF 2 1M 1 10% 50V CERM 402 R7998 1 1 10% 6.3V CERM-X5R 402 2 2 0.47UF P1V05S0_BOOT_R B 10K 470pF Keep C7990, C7991, R7990, R7994 and R7997 close to inductor 2 1 C7998 Placement Note: 10KOHM-5% 1 22UF 2 20% 6.3V CERM 805 2 3.3V / 1.05V Power Supplies SYNC_MASTER=(MASTER) 2 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING Vout = 0.6V * (1 + Ra / Rb) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 65 1 87 A 8 6 7 2 3 4 5 Power Control Signals 67C3 67C1 67B1 66B8 65D6 62A4 52B5 47C7 25C8 5D4 65B7 64C8 62C8 62B6 62B2 71D7 71C8 63C3 63B3 66D7 66D4 IN SMC_PM_G2_ENABLE PM_SLP_S4_L PM_SLP_S3_L Run (S0) 1 1 1 Sleep (S3) 1 1 0 Soft-Off (S5) 1 0 0 Battery Off (G3Hot) 0 0 0 3.425V "G3Hot" Supply Supply needs to guarantee 3.31V delivered to SMC VRef generator R8051 1 10K 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 1 R8068 1 R8052 10K 2 2 1 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 GPU requires 1.2V, 1.8V, 2.5V and 3.3V rise after VCore is up. R8069 10K 2 2 69B2 68C4 67A8 67A6 PPDCIN_G3H 5% 1/16W MF-LF 402 P3V42G3H5_BOOST C8000 P1V2R2V5D3C_EN_LS5V 71C8 66D8 66D4 63C3 63B3 D State PP5V_S5 R8050 1 Need to ensure that ISL6269 PGOOD does not deassert while GPU PowerPlay is changing GPU core voltage. P1V2R2V5D3C_EN_LS5V P1V2R2V5D3C_EN_LS5V P1V2R2V5D3C_EN_LS5V MAKE_BASE=TRUE 66D5 65C8 P3V3D3C_EN_L 63B3 63C3 66D4 66D7 66D8 71C8 63B3 63C3 66D4 66D7 66D8 71C8 VIN 10% 25V X5R 1206-1 P1V8D3C_EN 20% 6.3V X5R 402 LT3470 65C8 66D7 P1V8D3C_EN 64A6 66D6 1.8V Enable has pull-up to PBUS SHDN* SW 5 BIAS 7 Q8055 5 S G L8010 33uH FB 8 1 P3V42G3H_SW 2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE SOT-363 200mA max output CRITICAL PM_SLP_S3_LS5V_L PM_SLP_S3_LS5V_L 63D3 66D5 66D5 65D8 P3V3S0_EN_L P3V3S0_EN_L C8010 5% 50V CERM 402 65D8 66D5 MAKE_BASE=TRUE 6 4 3 D Q8050 D 2N7002DW-X-F 2 G 1 (Switcher limit) 348K 5D7 1% 1/16W MF-LF 2 402 2 G SOT-363 D 2 20% 6.3V CERM 805 200K S 1% 1/16W MF-LF 2 402 1 4 6 C8015 22UF R8011 1 2N7002DW-X-F 5 1 P3V42G3H_FB Q8058 SOT-363 S R8010 22pF 4 MAKE_BASE=TRUE S 1 Vout = 3.425 CDPH4D19F-SM GND 66D4 63D3 81D4 5D2 26D6 27C3 35B7 47B5 51C2 51D3 51D4 52B1 52B5 52B7 52D7 53C4 66A8 66C8 67D3 67D5 68B8 69A8 69B8 69C8 PP3V42_G3H 1 2N7002DW-X-F SOT-363 G NC 2 Q8056 2N7002DW-X-F 2 NC 3 D D CRITICAL 2 TSOT23-8 P3V3D3C_EN_L MAKE_BASE=TRUE 6 1 0.22uF BOOST U8000 2 1 66D5 64A6 C8005 6 3 1 10UF MAKE_BASE=TRUE D 1 Q8058 2N7002DW-X-F 66C6 62B3 48C3 6A2 6A1 5C1 81D4 66D2 66A8 53C4 52D7 47B5 35B7 27C3 26D6 52B5 52B1 51D4 51D3 69B8 69A8 68B8 67D5 69C8 52B7 5D2 51C2 67D3 2 PM_SLP_S3_LS5V MAKE_BASE=TRUE PP3V42_G3H PM_SLP_S3_LS5V PM_SLP_S3_LS5V P1V5S0_RUNSS 3 1 D Q8050 5 G SOT-363 S 2 C R8054 4 D IN G 79D5 67D5 67D3 67C3 65D8 65D2 24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 24B3 MAKE_BASE=TRUE 1 TP_P2V5S3_P1V2S3_PGOOD R8081 10% 16V CERM 402 1 MC74VHC1G08 U8081 2 SC70 4 71C8 66B5 GPUVCORE_EN PM_SLP_S4_LS5V D PM_SLP_S4_LS5V PM_SLP_S4_LS5V Q8055 2N7002DW-X-F SOT-363 S GPUVCORE_EN 1 1 10K 10K 1% 1/16W MF-LF 402 2 1% 1/16W MF-LF 2 402 R8065 10K R8064 5% 1/16W MF-LF 2 402 P1V5P1V05S0_PGOOD P1V5P1V05S0_PGOOD IN OUT 5C4 61C7 65B8 66B3 66B5 82C6 82D5 66B6 67A3 67B3 67C3 67C5 58C4 58C7 60C7 60D4 61A5 34A8 36D6 40B6 49B5 49C4 27C3 27D3 27D5 27D8 28A6 25B4 25B8 25C4 25C6 25D3 21C3 21D3 22B5 23B3 23D5 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 24B3 24B5 24C3 24D3 25A4 25D8 26B4 26B6 26B8 26D1 29A3 29A6 33C7 33D3 33D8 49C7 52D3 54B5 54D4 57B6 61D8 62A6 65B3 65D6 66B5 71D2 79A8 79D3 82A4 82B3 P1V5P1V05S0_PGOOD 66B5 66B2 65B8 61C7 5C4 MAKE_BASE=TRUE ISL6269 undervoltage threshold 81-87% (0.85 - 0.91V) NOTE: R8065 acts as 10K pull-up for PGOOD signal 62A4 65D3 66B6 66B7 PP3V3_S0 C8080 (P5VS5_PGOOD) ALL_SYS_PWRGD OUT 26A5 51D7 1 0.1UF C8070 20% 10V CERM 402 1 2 0.1uF 1 R8074 1% 1/16W MF-LF 2 402 5C1 5C4 6A1 6A2 23C3 41B6 47C7 48C3 51C5 64C8 66A6 66B8 5C1 5C4 6A1 6A2 23C3 41B6 47C7 48C3 51C5 64C8 66A6 66B8 1 R8072 845K 1% 1/16W MF-LF 2 402 1% 1/16W MF-LF 2 402 5C1 5C4 6A1 6A2 23C3 41B6 47C7 48C3 51C5 64C8 66A6 66B8 P5VS5_PGOOD 52A4 65D7 66A8 P5VS5_RUNSS 5D7 62C5 R8070 365K PP3V42_G3H P5VS5_PGOOD 4 3 PP3V3_S0 PP5V_S0 PP2V5_S0 PP0V9_S0 68.1K (PM_SLP_S4_L) SC70 2 PGOOD_MUXED_S0_OR_S0D3C 5D2 61D7 5D4 67A8 67D8 67D6 31C2 30D5 5D4 B MC74VHC1G08 U8080 82A2 1 MAKE_BASE=TRUE 1 Does not include D3C rails for GPU!! 5% 1/16W MF-LF 402 2 PM_SLP_S4_L PM_SLP_S4_L PM_SLP_S4_L 5 Other S0 Rails PWRGD Circuit 62A4 65D3 66B6 66B7 82D5 82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B1 65D6 65B3 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 2.5V S3 and 1.2V S3 supplies are controlled by ethernet power control circuit. 100K IN 66B5 71C8 1 1.5V Comp threshold set to 1.32V (88%) 66B3 66B2 65B8 61C7 5C4 58C7 58C4 57B5 55A8 53C4 36D6 31C5 25D8 5D4 81B3 80B5 80A1 79B8 71A6 67B3 67B1 67A1 62B1 67A6 63D1 19D7 19C5 19A8 19A6 19A4 17D6 17C6 82D3 82C5 67B6 4 R8057 1 65D7 52A4 66A6 P1V5S0_PGOOD V- 2 MAKE_BASE=TRUE 81D4 69C8 52B5 52B1 51D4 51D3 51C2 47B5 35B7 27C3 26D6 5D2 69B8 69A8 68B8 67D5 67D3 66D2 66C8 53C4 52D7 52B7 SM-LF 1 MAKE_BASE=TRUE 3 3 G 3 P1V5S0_COMP_POS The SB can turn off the GPUVcore (and by extension all D3Cold rails) by driving GPIO38 low. 66B6 65D3 62A4 5 20% 10V CERM 402 R8062 2 10K B LMC7211 0.1uF 5 64B4 66C2 U8060 V+ 5 5% 1/16W MF-LF 402 2 TP_P1V8S3_PGOOD 2 MAKE_BASE=TRUE R8055 1 5% 1/16W MF-LF 402 4 P1V0_P1V5PG_REF 10K SB_GPUVCORE_DISABLE_L SB_GPUVCORE_DISABLE_L 20% 10V CERM 402 1% 1/16W MF-LF 2 402 0.89V Reference C8081 TP_P1V8S3_PGOOD 1 0.1uF R8063 2 43C8 51C5 55C3 65B8 66B6 66C6 66C8 5C4 23C3 32B3 39C8 42A8 1 1 PM_SLP_S3_L_GPUVCORE_EN PP5V_S5 PM_SLP_S4_L 51C5 55C3 65B8 5C4 23C3 32B3 39C8 42A8 43C8 66C6 66C8 1 0.047UF 65B7 64C8 62C8 62B6 62B2 62A4 52B5 47C7 25C8 5D4 71D7 67C3 67C1 67B1 66D8 65D6 R8053 5% 1/16W MF-LF 2 402 C8053 IN 1 4.99K 1% 1/16W MF-LF 402 2 2 10K 63B5 63C8 66B8 MAKE_BASE=TRUE This signal was used as an option previously to test for 2v5 and 1v2 S3 valid for GPUVCORE_EN. But was disconnected for C8053 placement. 66A6 48C3 47C7 41B6 6A1 5C4 5C1 23C3 6A2 64C8 51C5 R8061 1 27.4K (PM_SLP_S3_L) 62B3 66C2 MAKE_BASE=TRUE C8060 66B6 66C6 66C8 51C5 55C3 65B8 39C8 42A8 43C8 5C4 23C3 32B3 51C5 55C3 65B8 5C4 23C3 32B3 39C8 42A8 43C8 66B6 66C6 66C8 C TP_P5V_P1V5_PGOOD PP1V5_S0 PP3V3_S3 PM_SLP_S3_L PM_SLP_S3_L PM_SLP_S3_L PM_SLP_S3_L PP3V3_S0 TP_P5V_P1V5_PGOOD MAKE_BASE=TRUE 81D4 46C3 46B3 41C5 37D7 37D5 37C3 37A7 32C5 27C5 5D4 81A5 67C5 67C3 65D1 63B7 60C2 59C6 57D4 52B1 46D6 S 4 TP_P2V5S3_P1V2S3_PGOOD TP_P2V5S3_P1V2S3_PGOOD Unused PGOOD Signals 66C1 62B3 PP3V3_S5 66C1 64B4 25C2 25B6 25B2 25A8 24B5 24A5 24A3 9B7 8B7 5D4 5D1 67C8 67C6 62C1 62A8 48B6 25D6 25C8 25C6 5% 1/16W MF-LF 402 2 IN Reports when 1.5V S0 and 1.05V S0 are in regulation SOT-363 S 1 SOT-363 G 100K IN 1.5V / 1.05V PWRGD Circuit Q8057 2N7002DW-X-F 5 63C8 63B5 66B8 66B7 5D7 62C4 Q8057 PM_SLP_S3_L R8056 1 63C8 63B5 66B8 66B7 Vout = 1.25V * (1 + Ra / Rb) 1 2N7002DW-X-F 2 PM_SLP_S3 D 5C1 6A1 6A2 48C3 62B3 66C6 66C7 5C1 6A1 6A2 48C3 62B3 66C6 66C7 6 5% 1/16W MF-LF 402 3 66B6 55C3 43C8 39C8 23C3 5C4 32B3 42A8 51C5 65B8 66C6 S 1.5V Enable has pull-up to PBUS 100K 2N7002DW-X-F SOT-363 G 20% 10V CERM 402 2 1 1 V1 S0PGOOD_5V_DIV 3 V2 S0PGOOD_2V5_DIV 4 V3 S0PGOOD_0V9_DIV 5 V4 MAKE_BASE=TRUE U8070 R8076 10K CRITICAL 2 5% 1/16W MF-LF 402 LTC2903 TSOT-23 RST* 6 S0PGOOD_PWROK 82A4 82D5 GND 1 R8059 470K 2 SMC_PM_G2_EN_L A 100K Q8059 1% 1/16W MF-LF 402 2 IN 2 SMC_PM_G2_EN G C8075 0.1UF 20% 10V 2 CERM 402 R8073 100K 1% 1/16W MF-LF 402 2 1 C8073 R8071 1 100K 0.1UF 1% 1/16W MF-LF 402 2 20% 10V 2 CERM 402 1 C8071 2 0.1UF 20% 10V 2 CERM 402 3.3V G3Hot Supply & Power Control 2N7002DW-X-F 5 G SOT-363 S SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY Q8059 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING LTC2903 guaranteed threshold is 93.5% (3.055V, 4.725V, 2.325V, 0.840V) 2N7002DW-X-F 51D5 1 1 4 6 D D R8075 5V Enable has pull-up to PBUS 3 5% 1/16W MF-LF 402 1 SOT-363 S I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 1 R8058 1 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 100K SIZE 5% 1/16W MF-LF 402 2 APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 66 1 87 A 8 6 7 PP0V9_S0 5 67D6 30D5 5D4 66B5 31C2 55A4 25D3 21C1 19D2 17D3 12C2 11B3 7B5 5D4 8C7 7D5 12A7 16C8 19C8 19D6 24D3 34C6 67D6 34C8 25C4 19D7 19D1 16D3 12B7 9B7 5B2 7B6 11C5 13B5 17D6 19D5 24C3 34B8 65A2 PP0V9_S0 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.425V MAKE_BASE=TRUE 66A8 53C4 52D7 52B7 52B5 52B1 51D4 51D3 51C2 47B5 5D4 30D5 31C2 66B5 5D2 67D6 67D8 35B7 27C3 26D6 81D4 69C8 69B8 69A8 68B8 67D3 66D2 66C8 13B5 16C8 16D3 17D3 5B2 5D4 7B5 7B6 7D5 11B3 11C5 12A7 12B7 19C8 19D1 19D2 19D5 21C1 24C3 24D3 25C4 34B8 34C6 34C8 55A4 67D6 67D8 PP0V9_S0 PP1V05_S0 PP3V42_G3H MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.05V MAKE_BASE=TRUE PP1V05_S0 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.22 mm VOLTAGE=1.2V MAKE_BASE=TRUE 67D6 63B3 5D4 5A4 39D7 39A8 PP1V2_S3 PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V3_S5 17D6 19D7 8C7 9B7 12C2 19D6 25D3 65A2 19D7 21C1 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 65A2 67D6 67D8 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 13B5 16C8 16D3 12A7 12B7 12C2 13B5 16C8 16D3 17D3 9B7 11B3 11C5 17D6 19C8 19D1 19D2 19D5 19D6 19D7 5B2 5D4 7B5 21C1 24C3 24D3 25C4 25D3 34B8 34C6 7B6 7D5 8C7 34C8 55A4 65A2 67D6 67D8 12A7 12B7 12C2 24D3 25C4 17D3 17D6 19C8 19D1 19D2 19D5 19D6 19D7 21C1 24C3 25D3 34B8 34C6 34C8 55A4 65A2 67D6 67D8 19D7 21C1 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 65A2 67D6 67D8 19D7 21C1 24C3 24D3 25C4 25D3 34B8 34C6 34C8 55A4 5B2 5D4 7B5 7B6 7D5 8C7 9B7 11B3 11C5 12A7 12B7 12C2 13B5 16C8 16D3 17D3 17D6 19C8 19D1 19D2 19D5 19D6 65A2 67D6 67D8 5A4 5D4 39A8 39D7 63B3 67D6 67D8 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V2_S3 D 79D5 67D3 67C3 66C5 65D8 65D2 24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 24B3 PP1V2_S3 PP1V2_S3 PP1V2_D3C MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S3 PP3V3_S5 5A4 5D4 39A8 39D7 63B3 67D6 67D8 5A4 5D4 39A8 39D7 63B3 67D6 67D8 5D4 63B1 67C6 67D6 67D8 70A1 70C7 77B8 82D7 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.2V MAKE_BASE=TRUE 70C7 70A1 63B1 5D4 67D6 67C6 82D7 77B8 67C6 48B6 25C2 24B5 8B7 5D4 24A3 25B2 25C8 62C1 66C5 25D6 25B6 24A5 5D1 9B7 25A8 25C6 62A8 PP1V2_D3C PP1V2_D3C PP1V2_D3C PP1V2_D3C PP1V2_D3C PP1V5_S0 5D4 63B1 67C6 67D6 67D8 70A1 70C7 77B8 82D7 5D4 63B1 67C6 67D6 67D8 70A1 70C7 77B8 82D7 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 62A8 62C1 66C5 67C6 67C8 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 C 67C6 19C5 16D1 19B5 19D6 5D4 63B1 67C6 67D6 67D8 70A1 70C7 77B8 82D7 5D4 63B1 67C6 67D6 67D8 70A1 70C7 77B8 82D7 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V MAKE_BASE=TRUE PP1V5_S0 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 62A8 62C1 66C5 67C6 67C8 62A7 19C1 13C5 17C6 19D2 19D7 19B8 5D4 17B6 19D1 PP3V3_S3 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 62A8 62C1 66C5 67C6 67C8 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 62A8 62C1 66C5 67C6 67C8 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 62A8 62C1 66C5 67C6 67C8 67B6 64C1 29D6 29D3 29B2 28D6 14C2 5D4 5B2 28D3 28B2 19D7 16B6 64A6 37B2 32C6 31C5 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V MAKE_BASE=TRUE PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V5_S0_NB PP1V8_S3 PP1V5_S0_NB 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 PP3V3_S0 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 5B2 5D4 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 31C5 32C6 37B2 64A6 64C1 67B6 67B8 PP1V8_S3 PP1V8_S3 PP1V8_S3 PP1V8_S3 PP1V8_S3 PP1V8_S3 5B2 5D4 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 31C5 32C6 37B2 64A6 64C1 67B6 67B8 5B2 5D4 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 31C5 32C6 37B2 64A6 64C1 67B6 67B8 5B2 5D4 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 31C5 32C6 37B2 64A6 64C1 67B6 67B8 5B2 5D4 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 31C5 32C6 37B2 64A6 64C1 67B6 67B8 5B2 5D4 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 31C5 32C6 37B2 64A6 64C1 67B6 67B8 5B2 5D4 14C2 16B6 19D7 28B2 28D3 28D6 29B2 29D3 29D6 31C5 32C6 37B2 64A6 64C1 67B6 67B8 PP1V8_D3C B 75D8 73A8 64A4 72B8 73B8 76D8 82D7 75D5 73A5 5D4 67B6 73B5 76D5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V PP1V8_D3C 5D4 64A4 67B6 67B8 72B8 73A5 73A8 73B5 73B8 75D5 75D8 76D5 76D8 82D7 MAKE_BASE=TRUE PP1V8_D3C PP1V8_D3C PP1V8_D3C PP2V5_S3 5D4 64A4 67B6 67B8 72B8 73A5 73A8 73B5 73B8 75D5 75D8 76D5 76D8 82D7 5D4 64A4 67B6 67B8 72B8 73A5 73A8 73B5 73B8 75D5 75D8 76D5 76D8 82D7 5D4 64A4 67B6 67B8 72B8 73A5 73A8 73B5 73B8 75D5 75D8 76D5 76D8 82D7 5A4 39D3 63C3 63D3 63D4 67B6 67B8 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.5V MAKE_BASE=TRUE 67B6 63D4 39D3 5A4 63D3 63C3 PP2V5_S3 PP2V5_S3 PP2V5_S3 5A4 39D3 63C3 63D3 63D4 67B6 67B8 5A4 39D3 63C3 63D3 63D4 67B6 67B8 PP2V5_S0 5D4 17C6 17D6 19A4 19A6 19A8 19C5 19D7 63D1 66B5 67A6 67A8 82C5 82D3 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.5V MAKE_BASE=TRUE 67B6 67A6 66B5 63D1 19A4 17D6 17C6 5D4 19D7 19C5 19A8 19A6 82D3 82C5 PP2V5_S0 PP2V5_S0 PP2V5_S0 PP2V5_S0 PP2V5_S0 PP2V5_S0 5D4 17C6 17D6 19A4 19A6 19A8 19C5 19D7 63D1 66B5 67A6 67A8 67B6 82C5 82D3 5D4 17C6 17D6 19A4 19A6 19A8 19C5 19D7 63D1 66B5 67A6 67A8 67B6 82C5 82D3 5D4 17C6 17D6 19A4 19A6 19A8 19C5 19D7 63D1 66B5 67A6 67A8 67B6 82C5 82D3 5D4 17C6 17D6 19A4 19A6 19A8 19C5 19D7 63D1 66B5 67A6 67A8 67B6 82C5 82D3 5D4 17C6 17D6 19A4 19A6 19A8 19C5 19D7 63D1 66B5 67A6 67A8 67B6 82C5 82D3 PP2V5_D3C 5D4 63C1 67A6 67A8 77A8 77C6 78C8 82D7 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.5V MAKE_BASE=TRUE 77A8 67A6 63C1 5D4 82D7 78C8 77C6 PP2V5_D3C PP2V5_D3C PP2V5_D3C PP2V5_D3C PP2V5_D3C A PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S0 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE 5D4 13C5 13D2 16D1 17B6 17C6 19A5 19B5 19B8 19C1 19C4 19C5 19D1 19D2 19D5 19D6 19D7 62A7 67B6 67C6 67C8 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S3 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE 66C5 67C6 67C8 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 62A8 62C1 62A8 62C1 66C5 67C6 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 67C8 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25D6 25C2 25C6 25C8 25D6 48B6 62A8 62C1 66C5 67C6 25C8 67C8 5D1 48B6 62A8 62C1 66C5 67C6 67C8 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 5D1 5D4 8B7 9B7 24A3 24A5 24B5 25A8 25B2 25B6 25C2 25C6 25C8 25D6 48B6 62A8 62C1 66C5 67C6 67C8 PP1V5_S0_NB 67B6 19C4 13D2 19A5 19D5 4 PP3V42_G3H 5D4 30D5 31C2 66B5 67D6 67D8 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0.9V MAKE_BASE=TRUE 5D4 63C1 67A6 67A8 77A8 77C6 78C8 82D7 5D4 63C1 67A6 67A8 77A8 77C6 78C8 82D7 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 5D4 63C1 67A6 67A8 77A8 77C6 78C8 82D7 PP3V3_D3C 77A7 72D8 55C7 55A5 5B2 71C1 71B7 67A6 PPVCORE_D3C_GPU MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE 5B2 55A5 55C7 67A6 67A8 71B7 71C1 72D8 77A7 77D2 77C6 77B7 74D6 74B2 71C4 71B8 71A4 67A3 65C7 82D7 82A7 80D5 80B2 PPVCORE_D3C_GPU PPVCORE_D3C_GPU PP3V3_D3C PP3V3_D3C PP3V3_D3C PP3V3_D3C PP3V3_D3C PP3V3_D3C PP3V3_D3C PP3V3_D3C PP3V3_D3C PP3V3_D3C PP3V3_D3C PP3V3_D3C 5B2 55A5 55C7 67A6 67A8 71B7 71C1 72D8 77A7 5B2 55A5 55C7 67A6 67A8 71B7 71C1 72D8 77A7 PPDCIN_G3H 66D5 67A6 67A8 68C4 69B2 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V MAKE_BASE=TRUE 67A8 67A6 66D5 69B2 68C4 67A8 67A6 66D5 69B2 68C4 PPDCIN_G3H PPDCIN_G3H PPDCIN_G3H GND 66D5 67A6 67A8 68C4 69B2 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V 8 7 6 5 4 1 "S3AC" rail is ON in S3 on AC, OFF in S3 on battery PP3V3_S3AC 69C8 81D4 5D2 26D6 27C3 35B7 47B5 51C2 51D3 51D4 52B1 52B5 52B7 52D7 53C4 66A8 66C8 66D2 67D3 67D5 68B8 69A8 69B8 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.22 mm VOLTAGE=3.3V MAKE_BASE=TRUE 52B5 52B7 52D7 53C4 66A8 66C8 66D2 67D3 67D5 68B8 5D2 26D6 27C3 35B7 47B5 51C2 51D3 51D4 52B1 5A4 69A8 69B8 69C8 81D4 39A5 5D2 26D6 35B7 47B5 51C2 39D6 39B8 39B5 39B4 51D3 51D427C3 52B1 52B5 52B7 67D1 41C4 39D8 52D7 53C4 66A8 66C8 66D2 67D3 67D5 68B8 69A8 69B8 69C8 81D4 69C8 81D4 5D2 26D6 27C3 35B7 47B5 51C2 51D3 51D4 52B1 52B5 52B7 52D7 53C4 66A8 66C8 66D2 67D3 67D5 68B8 69A8 69B8 PP3V3_S3AC 67D1 39D8 39B8 39B4 5A4 39A5 39B5 39D6 41C4 67D3 71A2 67D1 67D3 72D2 PP3V3_S3AC PNBB_S0_GPU MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=-0.7V MAKE_BASE=TRUE 69C8 81D4 5D2 26D6 27C3 35B7 47B5 51C2 51D3 51D4 52B1 52B5 52B7 52D7 53C4 66A8 66C8 66D2 67D3 67D5 68B8 69A8 69B8 PNBB_S0_GPU 5D2 26D6 72D2 71A2 67D1 27C3 35B7 47B5 51C2 51D3 51D4 52B1 52B5 52B7 52D7 53C4 66A8 66C8 66D2 67D3 67D5 68B8 69A8 69B8 69C8 81D4 65D8 66C5 67C3 67D3 67D5 79D5 5D4 11B5 22C6 22D8 23A7 23B7 23D1 23D4 23D8 24A5 24B3 24C3 25B6 25C8 25D2 26C5 56D4 63D8 65C8 65D1 65D2 PNBB_S0_GPU 71A2 67D1 67D3 72D2 PPBB_S0_GPU 71B5 67D1 67D3 72D6 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.9V MAKE_BASE=TRUE 63D8 65C8 65D1 65D2 65D8 66C5 67C3 67D3 67D5 79D5 23D1 23D4 23D8 24A5 24B3 24C3 25B6 25C8 25D2 26C5 5D4 11B5 22C6 22D8 23A7 23B7 72D6 71B5 67D1 56D4 PPBB_S0_GPU 71B5 67D1 67D3 72D6 67D3 61D1 55A6 8D7 5B2 8B5 9D7 55D7 67D1 61D1 55A6 8D7 5B2 8B5 9D7 55D7 67D1 67D3 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 64D7 64A6 62D7 61D7 61D4 55D3 43D8 41C6 5A1 5C4 42B8 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 64D7 64A6 62D7 61D7 61D4 55D3 43D8 41C6 5A1 5C4 42B8 67C1 43B5 38B7 42C8 43D3 67C3 PPBB_S0_GPU 65D8 66C5 67C3 67D3 67D5 79D5 5D4 11B5 22C6 22D8 23A7 23B7 23D1 23D4 23D8 24A5 24B3 24C3 25B6 25C8 25D2 26C5 56D4 63D8 65C8 65D1 65D2 65D8 5D4 11B5 22C6 22D8 23A7 23B7 23D1 23D4 23D8 24A5 24B3 24C3 25B6 25C8 25D2 26C5 56D4 63D8 65C8 65D1 65D2 66C5 67C3 67D3 67D5 79D5 67C3 67D3 67D5 79D5 63D8 65C8 65D1 65D2 65D8 24C3 25B6 25C8 25D2 26C5 67D1 5D4 11B5 22C6 22D8 23A7 23B7 61D1 55D7 55A6 9D7 8D7 23D1 23D4 23D8 24A5 24B3 56D4 25D2 26C5 56D4 63D8 8B5 66C5 5D4 11B5 22C6 22D8 5B2 23A7 23B7 23D1 23D4 23D8 24A5 24B3 24C3 25B6 25C8 65C8 65D1 65D2 65D8 66C5 67C3 67D3 67D5 79D5 PPVCORE_S0_CPU MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.1V MAKE_BASE=TRUE PPVCORE_S0_CPU PPVCORE_S0_CPU 65D8 66C5 67C3 67D3 67D5 79D5 5D4 11B5 22C6 22D8 23A7 23B7 23D1 23D4 23D8 24A5 24B3 24C3 25B6 25C8 25D2 26C5 56D4 63D8 65C8 65D1 65D2 PPBUS_G3H MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE 65D8 66C5 67C3 67D3 67D5 79D5 5D4 11B5 22C6 22D8 23A7 23B7 23D1 23D4 23D8 24A5 24B3 79B7 71D7 69C1 68D5 24C3 25B6 25C8 25D2 26C5 56D4 63D8 65C8 65D1 65D2 64A6 62D7 61D7 61D4 55D3 43D8 42B8 41C6 5C4 5A1 67C1 65D6 65B7 64D7 65D8 66C5 67C3 67D3 67D5 79D5 5D4 11B5 22C6 22D8 23A7 23B7 23D1 23D4 23D8 24A5 24B3 24C3 25B6 25C8 25D2 26C5 56D4 63D8 65C8 65D1 65D2 81D4 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81A5 PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_S5_FW_FET PPBUS_G3H 81A5 81D4 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81D4 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81A5 67C5 81A5 81D4 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 81A5 81D4 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81D4 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81A5 81A5 81D4 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81D4 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81A5 81D4 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81A5 5D4 43D3 43B5 42C8 38B7 27C5 32C5 37A7 67C1 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81A5 81D4 81D4 5D4 27C5 32C5 37A7 37C3 37D5 37D7 41C5 46B3 46C3 46D6 52B1 57D4 59C6 60C2 63B7 65D1 66C6 67C3 67C5 81A5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=33V MAKE_BASE=TRUE PPBUS_S5_FW_FET 67C3 67C1 43B5 38B7 42C8 43D3 71D7 67C1 66D8 65D6 64C8 62B6 62A4 47C7 5D4 25C8 52B5 62B2 62C8 65B7 66B8 67B1 67C3 PPBUS_S5_FW_FET PPBUS_S5_FW_FET PPBUS_S5_FW_FET PP5V_S5 82D5 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 34A8 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 25D8 26B4 26B6 26B8 26D1 27C3 27D3 27D5 27D8 28A6 23D5 24B3 24B5 24C3 24D3 25A4 25B4 25B8 25C4 25C6 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 29A3 29A6 33C7 33D3 33D8 71D7 67C1 58C4 58C7 67A3 25D3 52B5 47C7 25C8 5D4 67B1 66D8 66B8 65D6 65B7 64C8 62C8 62B6 62B2 62A4 25B8 25C4 25C6 25D3 25D8 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 26B4 26B6 26B8 26D1 27C3 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 67A3 67B3 67C3 60D4 67C5 71D2 79A8 79D3 82A4 82B3 82C6 82D5 36D6 40B6 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 60C7 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 82D5 66B6 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 82D5 82D5 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 82A4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 67C3 25A4 25B4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 61A5 26B8 26D1 27C3 27D3 27D5 27D8 28A6 29A3 29A6 49C4 33C7 33D3 33D8 34A8 36D6 40B6 49B5 49C4 49C7 54B5 54D4 57B6 58C4 58C7 60C7 60D4 27D8 52D3 25C4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 21D3 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 5A4 82B3 82C6 82D5 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 25B8 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 27D3 27D5 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 40B6 49B5 49C7 52D3 54B5 54D4 57B6 58C4 58C7 60C7 60D4 61D8 62A6 65B3 65D6 66B1 66B5 66B6 67A3 67B3 67C5 71D2 79A8 79D3 82B3 82C6 62A2 52B8 45C3 5D4 5B2 81C6 81C4 67B1 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 82C6 82D5 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 82C6 82D5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5 71D7 67C1 66D8 65D6 64C8 62B6 62A4 47C7 5D4 25C8 52B5 62B2 62C8 65B7 66B8 67B1 67C3 PP5V_S3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE 81C6 81C4 67B3 67B1 62A2 52B8 45C3 5D4 5B2 81B3 80A1 71A6 67B1 66B5 61D7 58C4 55A8 36D6 25D8 5D2 5D4 31C5 53C4 57B5 58C7 62B1 67A1 67B3 79B8 80B5 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S0 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE 81B3 80B5 80A1 79B8 71A6 36D6 31C5 25D8 5D4 5D2 67B1 67A1 66B5 62B1 61D7 58C7 58C4 57B5 55A8 53C4 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 82C6 82D5 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 82C6 82D5 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 26D1 27C3 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 66B6 67A3 67B3 67C3 67C5 71D2 79A8 62A6 79D3 82A4 82B3 82C6 82D5 36D6 40B6 49B5 49C4 49C7 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 52D3 54B5 54D4 57B6 58C4 58C7 60C7 60D4 61A5 61D8 65B3 65D6 66B1 66B5 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 82C6 82D5 82B3 82C6 82D5 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 66B6 67A3 67B3 67C3 67C5 71D2 79A8 79D3 82A4 82B3 36D6 40B6 49B5 49C4 49C7 52D3 54B5 54D4 57B6 58C4 25B8 25C4 25C6 25D3 25D8 26B4 26B6 26B8 26D1 27C3 5A4 5D4 10C5 14C7 14D6 17C6 19C6 19C7 20A4 20B4 21C3 21D3 22B5 23B3 23D5 24B3 24B5 24C3 24D3 25A4 25B4 27D3 27D5 27D8 28A6 29A3 29A6 33C7 33D3 33D8 34A8 58C7 60C7 60D4 61A5 61D8 62A6 65B3 65D6 66B1 66B5 82C6 82D5 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 81B3 80B5 80A1 79B8 71A6 67B3 67B1 67A1 66B5 61D7 58C4 55A8 36D6 25D8 5D2 5D4 31C5 53C4 57B5 58C7 62B1 SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77B7 77C6 77D2 80B2 80D5 82A7 82D7 NOTICE OF PROPRIETARY PROPERTY 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77D2 80B2 80D5 82A7 82D7 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77D2 80B2 80D5 82A7 82D7 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77D2 80B2 80D5 82A7 82D7 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77D2 80B2 80D5 82A7 82D7 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING 77B7 77C6 77B7 77C6 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 77B7 77C6 II NOT TO REPRODUCE OR COPY IT 77B7 77C6 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77B7 77C6 77D2 80B2 80D5 82A7 82D7 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77B7 77C6 77D2 80B2 80D5 82A7 82D7 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77B7 77C6 77D2 80B2 80D5 82A7 82D7 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77B7 77C6 77D2 80B2 80D5 82A7 82D7 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77B7 77C6 77D2 80B2 80D5 82A7 82D7 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77B7 77C6 77D2 80B2 80D5 82A7 82D7 SIZE APPLE COMPUTER INC. DRAWING NUMBER D REV. 051-7164 SCALE SHT NONE 2 06004 OF 67 65C7 67A3 67A5 71A4 71B8 71C4 74B2 74D6 77B7 77C6 77D2 80B2 80D5 82A7 82D7 3 D 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 64D7 64A6 62D7 61D7 61D4 43D8 41C6 5A1 5C4 42B8 55D3 79B7 71D7 69C1 68D5 67C3 67C1 65D6 65B7 64D7 62D7 61D4 43D8 41C6 5A1 5C4 42B8 55D3 61D7 64A6 C 67C1 43B5 38B7 42C8 43D3 67C3 71D7 67C3 67C1 66D8 65D6 64C8 62B6 62A4 47C7 5D4 25C8 52B5 62B2 62C8 65B7 66B8 67B1 71D7 67C1 66D8 65D6 64C8 62B6 62A4 47C7 5D4 25C8 52B5 62B2 62C8 65B7 66B8 67B1 67C3 B 81B3 80A1 71A6 67B1 66B5 61D7 58C4 55A8 36D6 25D8 5D2 5D4 31C5 53C4 57B5 58C7 62B1 67A1 67B3 79B8 80B5 81B3 80A1 71A6 67B1 66B5 61D7 58C4 55A8 36D6 25D8 5D2 5D4 31C5 53C4 57B5 58C7 62B1 67A1 67B3 79B8 80B5 Power Aliases 5D4 63C1 67A6 67A8 77A8 77C6 78C8 82D7 PPVCORE_D3C_GPU MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.2V MAKE_BASE=TRUE 2 3 69C8 81D4 5D2 26D6 27C3 35B7 47B5 51C2 51D3 51D4 52B1 52B5 52B7 52D7 53C4 66A8 66C8 66D2 67D3 67D5 68B8 69A8 69B8 1 87 A 8 6 7 2 3 4 5 1 DC-In Connector D D CRITICAL J8290 87438-0832-BLK M-RT-SM PPBUS_G3H 1 5A1 5C4 41C6 42B8 43D8 55D3 61D4 61D7 62D7 64A6 64D7 65B7 65D6 67C1 67C3 69C1 71D7 79B7 2 3 4 5 6 7 PP18V5_DCIN 8 5B1 68B8 VOLTAGE=18.5V MIN_LINE_WIDTH=0.60mm MIN_NECK_WIDTH=0.20mm D8201 518S0456 R8207 1SS355 1 2 PPDCIN_G3H_R VOLTAGE=18.5V MIN_LINE_WIDTH=0.50mm MIN_NECK_WIDTH=0.20mm SOD-323 1 47 PPDCIN_G3H 2 66D5 67A6 67A8 69B2 5% 1/8W MF-LF 805 C C Inrush Limiter Battery Connector CRITICAL Q8250 SI4405DY-E3 B SO-8 68C5 2 R8221 1 1 1 470K 81D4 69C8 69B8 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52D7 52B7 52B5 52B1 51D4 51D3 51C2 47B5 35B7 27C3 26D6 5D2 0.22uF 1% 1/16W MF-LF 402 2 ACIN Detection PP3V42_G3H C8250 2 S3 S2 D4 D3 D2 D1 S1 87438-1043-BLK M-RT-SM 6 PP18V5_G3H_CHGR 68B3 69D8 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm GATE 20% 25V X5R 603 J8250 7 5 PP18V5_G3H_CHGR 3 68B3 69D8 ACIN_ENABLE_DIV_L R8212 1 R8214 1 102K 1% 1/16W MF-LF 402 2 5% 1/16W MF-LF 402 20% 10V CERM 402 52A2 51D5 43C8 102K 1% 1/16W MF-LF 2 402 ACIN_1V20_REF 4 8 69B1 68A1 5D1 BATT_NEG 5D1 68B2 OUT MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm IO GND IO (HOST_DETECT_L) BATT_POS BATT_POS 5D1 68A1 68A2 69B1 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm 9 10 2 BATT_POS 5D1 68A1 68A2 69B1 3 5 U8200 1 D U8250 SM-LF 1 2N7002 SC70 4 518S0457 Q8210 MC74VHC1G08 LMC7211 V+ 7 BATT_NEG SMC_BS_ALRT_L SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL ACIN_ENABLE_DIV2_L SMC_ADAPTER_EN CRITICAL 2 1 330K 0.1uF 2 6 R8250 C8210 4 5 MIN_LINE_WIDTH=0.2mm MIN_NECK_WIDTH=0.2mm 1 1 2 VOLTAGE=18.5V 4 B CRITICAL 68B3 69D8 8 3 PP3V42_G3H PP18V5_G3H_CHGR PP18V5_DCIN 5B1 1 ACOK_AND_PS_ON G SOT23-LF S 2 2 3 ACIN_DIV R8213 1 10.7K A 1% 1/16W MF-LF 402 2 R8215 DC-In & Battery Connectors 5 1 R8216 57.6K 2 1% 1/16W MF-LF 2 402 1M 1 SMC_BC_ACOK SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) 5B1 48C3 51C5 52A2 69A6 NOTICE OF PROPRIETARY PROPERTY 5% 1/16W MF-LF 402 NOTE: R8210 is on M57 LIO! System must provide 10K-70K impedance to A52 adapter for system load detection. REQ of R8210 (on M57 LIO), R8212, & R8213 is 36.9K. 3 V- THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING Vref = 3.42V * (R2a / (R1a + R2a)) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT Vth = (Vref / (R2b / (R1b + R2b)) III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART Vref = 1.23V SIZE Vth = 13.0V APPLE COMPUTER INC. Assuming 1% variance for R8210-R8215 and 3.42V: Worst case Vth: min:12.47V, max: 13.54V DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 68 1 87 A 8 6 7 PBus Supply & Battery Charger 2 3 4 5 1 CRITICAL Q8300 SI4413ADY-E3 68B3 SO-8 PP18V5_G3H_CHGR R8307 C8311 CHGR_SGND 69C7 69C6 69B7 69A7 R8393 34.8K IRLML5203-2.6A C8301 0.022uF S 2 1ISL6257H 20% 25V CERM 603 1% 1/16W MF-LF 402 D8340 SOT23 CHGR_CSO_R_N 3 CHGR_ICOMP CHGR_VCOMP NO STUFF 49D7 69C2 CHGR_ACSET_D R8344 8 ACLIM 3 ICOMP 4 VCOMP 9 VADJ TP_CHGR_VADJ 2 CELLS 0.1uF 69D5 69C6 69B7 69A7 2 2 10% 50V CERM 402 10% 16V X5R 402 10% 16V X5R 402 CHGR_SGND C8302 10% 25V X7R 402 PP3V42_G3H CHGR_VDD 23 ACPRN 27 ACSET 1 ISL6255A 1 C8390 0.0033uF 0.0033uF 10% CHGR_SGATE CHGR_CSI_P CHGR_CSI_N 1% 1/16W MF-LF 402 2 69D5 69C7 69B7 69A7 2 CHGR_SGND 1% 1/16W MF-LF 2 402 69C6 69A6 CHGR_ACPRN 20% 10V CERM 402 18 1 22UF 10% 2 25V X5R-CERM 805 C8306 22UF 20% 2 25V POLY CASE-D2-LF 20% 2 25V POLY CASE-D2-LF D8300 R8303 2.2 1 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm 2 SOD-123 2 CHGR_BOOT_R 5% 1/16W MF-LF 402 C8303 CHGR_VDDP 1 69D5 B0530WXF 2 5 20% 25V CERM 603 69C7 Q8301 4 RJK0305DPB MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm LFPAK CRITICAL 1 2 3 49.9 3 10A MAX, LIMITED BY L8300, Q8301 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm SM PPBUS_G3H 5 SWITCH_NODE=TRUE R8308 1 C8370 1 Q8302 0.0022uF 4 10% 50V CERM 603 CRITICAL CRITICAL RJK0305DPB MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION U8300 CRITICAL ISL6257H C8309 1 LFPAK CRITICAL 1 100UF 33UF 20% 16V 2 ELEC 6.3X5.5SM1 20% 2 16V POLY CASED2E-SM 0.01 PPVBAT_G3H_CHGR_OUT 2 1 2 2 XW8304 XW8303 SM 1UF 10% 2 16V X5R 603 SM 1 C8310 1 ISL6255A R8304 TABLE_5_ITEM 353S1510 1 ISL6257H,BATT CHGR,28P,QFN,LF S TABLE_5_ITEM 1 0 OHM,5%,1/16W,0402,SMD,LF R8304 C 69B7 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm 0.5% 1W MF 0612 C8308 1 2 3 Q8350 79B7 67C1 67C3 64A6 64D7 55D3 61D4 5A1 5C4 41C6 42B8 43D8 61D7 62D7 65B7 65D6 68D5 71D7 2 CHGR_PHASE 2 0.5% 1/16W MF-LF 603 1 4.7UH TABLE_5_HEAD 116S0004 69D6 49D7 ISL6257H 270 CHGR_CSO_R_N NO_TEST=TRUE 1 CHGR_SGND 49D7 CHGR_CSO_R_P 2.2 1 2 5% 1/16W MF-LF 402 R8306 2 69D5 69C7 69C6 69B7 69A7 D NO_TEST=TRUE SOT23-LF G 1 2 49D4 CHGR_CSI_R_N 5% 1/16W MF-LF 402 69C4 2N7002 1 CRITICAL C8305 R8305 NO_TEST=TRUE 3 D 1 CRITICAL 2 CHGR_EN CRITICAL C8317 L8300 1 100K 1 2.2UF 10% 2 25V X5R-CERM 805 1 R8370 XW8300 R8350 2.2UF 353S1244 1 402 2 TP_CHGR_DCPRN TP_CHGR_DCSET DCPRN 24 DCSET 28 SM 1 100K 1 C8304 1 2 50V CERM 402 R8324 1 1% 1/16W MF-LF 402 CRITICAL C8316 0.1UF CHGR_LGATE CHGR_EN 10% 50V 2 CERM C C8391 1 SM NO_TEST=TRUE CHGR_BOOT CHGR_UGATE BOOT 14 UGATE 15 CHGR_ACPRN CHGR_ACSET ISL6257H 2 2 NC_CHGR_BGATE CHGR_DCIN 69D7 BGATE 17 DCIN 25 69A6 69C8 1 49D4 CSIN 20 CHGR_VREF 0.0082uF 69B8 69A8 68B8 67D5 67D3 66D2 66C8 51D3 51C2 47B5 35B7 27C3 26D6 5D2 66A8 53C4 52D7 52B7 52B5 52B1 51D4 81D4 69D7 69D5 SGATE 18 CSIP 19 69B8 69D7 CRITICAL 2 XW8302 SM MIN_LINE_WIDTH=0.2mm MIN_NECK_WIDTH=0.2mm 2 1 21 CSOP 22 CSON PHASE 16 CRITICAL 7 CHLIM LGATE 12 BOMOPTION=ISL6255A 1 6 VREF EN 69B1 1 1% 1/16W MF-LF 2 402 CHGR_CSO_P 69C1 CHGR_CSO_N 69A6 CHGR_CHLIM 2 C8341 1 100K 1% 1/16W MF-LF 402 2 C8300 11.3K 1 XW8301 R8310 0.1UF QFN C8315 0.033uF R8341 1 1 VDDP U8300 5 ICM CHGR_ICM 680pF 1 1 1uF 10% 6.3V CERM 402 13 VDD CHGR_ACLIM 69A6 MMBD914XXG 2 402 ISL6255AHRZ 2 2 GND 20% 25V CERM 603 2 1% 1/16W MF-LF 100 1 0.1UF 0.1UF 1 R8302 C8307 0.5% 1W MF 0612 2 100K 11 69C6 C8312 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm 2 NO STUFF CHGR_VDDP 34.8K 10 1 C8340 1 69C2 R8392 26 NO STUFF 2 CHGR_ACSET 2 CHGR_VCOMP_C 10% 16V CERM-X5R 402 CHGR_DCIN 69D4 CHGR_ICM_R 1% 1/16W MF-LF 402 1 2 118K THRML_PAD R8340 1 2 5% 1/16W MF-LF 402 29 D 4.7 1 1 S1 GATE 1% 1/16W MF-LF 402 PPVDCIN_G3H_R 0.02 PPVDCIN_G3H_PRE MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm R8300 CHGR_PHASE_R SM CHGR_VDD PGND G 1 CHGR_VDD 2 10% 6.3V CERM 402 1ISL6255A Q8340 69C8 69D5 1uF 1 69D7 69C8 3 D S3 S2 D4 D3 D2 D1 2 CHGR_CSO_N 69C6 CHGR_CSO_P 69C6 5% 1/16W MF-LF 402 VOLTAGE FOLLOWER GUARANTEES CURRENT LIMIT CIRCUITS ARE PROVIDED WITH SUFFICIENT CURRENT WITHOUT SINKING CURRENT FROM VREF. 81D4 69C8 69B8 69A8 68B8 67D5 67D3 66D2 52B5 52B1 51D4 51D3 51C2 47B5 35B7 27C3 26D6 5D2 PP3V42_G3H 66C8 66A8 53C4 52D7 52B7 C8380 CRITICAL U8301 CHGR_VREF 69C6 1 V+ B 3 20% 10V CERM 402 HPA00141AIDCKR 5 + SC70-5 4 R8320 1 0.1UF CHGR_VREF_VF Battery Charge FET 2 2 69A7 69B7 69D5 69C7 69C6 69B7 69A7 CRITICAL CHGR_SGND 69C1 2 67D5 52B7 35B7 51D4 66C8 69C8 67D3 52B5 27C3 51D3 66A8 69B8 10% 16V CERM 402 1 PP3V42_G3H 1% 1/16W MF-LF 2 402 R8369 2 5% 1/16W MF-LF 402 CHGR_ACLIM_R 6 D 2 1 C8320 0.1uF 10% 16V X5R 402 2 1 0.01uF 10% 16V CERM 402 2 G 3.01K CHGR_ACLIM 2 1 Q8360 470K 1% 1/16W MF-LF 402 2 5 G R8363 1 0.22uF 2 2 SOT-363 S 2 5 SMC_BATT_CHG_EN G C8324 A As shown, Ichg = 3.3A max PP3V42_G3H 1 1 20% 16V CERM 402 5% 1/16W MF-LF 2 402 R8362 CHGR_CHLIM_R 6 3 D Q8361 Q8361 2N7002DW-X-F 51B5 SMC_BATT_ISET 2 G SOT-363 G SOT-363 2 S SMC_BATT_ISET_L 1 4 69D5 69C7 69C6 69B7 69A7 CRITICAL 7 F8302 6 5 8AMP-24V PPVBATT_G3H_FET 1 2 BATT_POS MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm 68A6 52A2 51C5 48C3 5B1 R8322 4 1 10K 2 GND_CHASSIS_BATTCONN_HOLE 1 2 10% 50V CERM 402 GND 2N7002DW-X-F Q8322 SOT-363 2N7002DW-X-F G D Q8324 S G 2 SMC_BATT_TRICKLE_EN_L PBus Supply & Batt. Charger 51D7 52A2 SOT-363 S SYNC_MASTER=M59_LIO 1 5 G SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY Q8322 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING SOT-363 S I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 1 C8362 0.01UF 2 C8323 1 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 0.1UF 20% 10V CERM 402 10% 16V CERM 402 II NOT TO REPRODUCE OR COPY IT 4 SIZE 2 APPLE COMPUTER INC. CHGR_SGND DRAWING NUMBER D SHT NONE 7 6 5 4 3 2 REV. 051-7164 SCALE 8 6A4 6A6 C8330 0.001UF 35.7K 2N7002DW-X-F SMC_BC_ACOK_R 10% 50V CERM 402 6 2 1 C8327 0.001UF 2 R8323 6 CHGR_ACPRN SMC_BC_ACOK 5D1 68A1 68A2 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm 1% 1/16W MF-LF 2 402 SOT-363 R8325 69C6 R8366 59.0K 2N7002DW-X-F 5 S B Q8324 D CHGR_CHLIM 1 66D5 67A6 67A8 68C4 MIN_LINE_WIDTH=0.2mm MIN_NECK_WIDTH=0.2mm 1 2 S 3 2 1% 1/16W MF-LF 402 PPDCIN_G3H 1 24.3K 1 2 5% 1/8W MF-LF 805 1206 R8367 1% 1/16W MF-LF 402 2 10K 47 1 TCHG_EN_DIV2_L 88.7K R8379 D 69C8 69C6 SOD-323 PPVBATT_G3H_DIO VOLTAGE=12.6V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.25mm TCHG_EN_DIV_L 1 0.01UF D 27C3 5D2 26D6 35B7 47B5 51C2 51D3 51D4 52B1 52B5 52B7 52D7 53C4 66A8 66C8 66D2 67D3 67D5 68B8 69B8 69C8 81D4 2 1% 1/16W MF-LF 2 402 4 CHGR_VREF_VF D4 D3 D2 D1 S1 2N7002DW-X-F CHGR_SGND 1 39.2K 3 52A2 51D7 Battery Charge Current Limit 1 CHG_EN_DIV2_L 10% 16V CERM 402 S3 S2 GATE NO STUFF C8361 4 69B7 1 5 4 330K D 69D5 69C7 69C6 69B7 69A7 2 6 GATE 10% 10V CERM 402 R8331 1 69D6 0.047UF 1% 1/16W MF-LF 2 402 SMC_SYS_ISET_L 1 S1 C8325 5% 1/16W MF-LF 402 2 20.0K 2N7002DW-X-F SOT-363 1 R8360 3 S 1 R8330 1 R8321 1SS355 8 3 7 CHG_EN_DIV_L 1% 1/16W MF-LF 402 D Q8360 SO-8 MIN_LINE_WIDTH=0.2mm MIN_NECK_WIDTH=0.2mm 1 2N7002DW-X-F SMC_SYS_ISET C8321 3.48K 1 10K 51B5 1 0.01UF 69A7 69B7 R8368 81D4 66D2 52B1 26D6 5D2 51C2 47B5 53C4 52D7 69A8 68B8 Q8321 SI4405DY-E3 SO-8 D4 D3 D2 D1 D8321 CRITICAL 8 C8322 CHGR_VREF_VF 5% 3W MF 2525 SI4405DY-E3 S3 S2 3 As shown, Isys =~4.6A max 2 Q8320 PPVBAT_G3H_CHGR_OUT NO STUFF Adapter Input Current Limit 1 MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm V- - 27 PPVBATT_G3H_PRE 06004 OF 69 1 87 A 8 6 7 2 3 4 5 1 OMIT U8400 M56P BGA (1 OF 7) 13C3 13B3 13C3 D 13B3 13C3 13B3 13B3 13B3 13B3 13B3 13B3 13B3 13B3 82D7 77B8 70C7 70A1 67D8 67D6 67C6 63B1 5D4 82D7 77B8 70C7 70A1 67D8 67D6 67C6 63B1 5D4 PP1V2_D3C PP1V2_D3C 13B3 C 13B3 IN IN IN IN PEG_R2D_C_N<2> IN IN IN IN IN IN IN C8423 PEG_R2D_C_N<1> IN IN C8422 PEG_R2D_C_P<1> PEG_R2D_C_P<2> IN C8421 PEG_R2D_C_N<0> IN IN C8420 PEG_R2D_C_P<0> C8424 C8425 C8426 PEG_R2D_C_P<3> C8427 PEG_R2D_C_N<3> C8428 PEG_R2D_C_P<4> C8429 PEG_R2D_C_N<4> C8430 PEG_R2D_C_P<5> C8431 PEG_R2D_C_N<5> C8432 PEG_R2D_C_P<6> C8433 PEG_R2D_C_N<6> C8434 PEG_R2D_C_P<7> C8435 PEG_R2D_C_N<7> L8400 0402 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF IN PEG_R2D_C_P<8> C8436 0.1uF 13B3 IN PEG_R2D_C_N<8> C8437 0.1uF 13B3 U8400 2 M56P 13B3 BGA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 (2 OF 7) OMIT N23 W29 P23 PCIE_PVDD_12 (1.2V) Y24 Y26 C8402 1 1uF 10% 6.3V CERM 402 U23 V23 C8401 1 1 1uF 2 10% 6.3V CERM 402 C8400 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.2V 13B3 2 20% 6.3V CERM 805 13B3 13B3 N25 Y30 N26 N27 C8407 AA25 N28 1uF AA26 N29 AL29 10% 6.3V CERM 402 1 C8406 1 1 1uF 2 10% 6.3V CERM 402 13B3 C8405 AB23 2 2 20% 6.3V CERM 805 13B3 C8414 20% 6.3V CERM 805 AL31 AL32 AB27 AM27 1uF AB29 AM28 AC23 AM29 10% 6.3V CERM 402 AM30 AC26 AM31 PCI EXPRESS POWER & GROUND AC29 AC30 AD25 AD26 AD29 AD31 AE26 PCIE_VSS AE27 AE29 AF26 AF28 AF29 AF30 AG25 PCIE_PVSS IN C8440 PEG_R2D_C_P<10> C8441 PEG_R2D_C_N<10> 0.1uF 0.1uF IN C8442 PEG_R2D_C_P<11> IN C8443 PEG_R2D_C_N<11> C8413 1 C8412 1 1uF 2 10% 6.3V CERM 402 C8411 1 1 1uF 2 10% 6.3V CERM 402 0.1uF 0.1uF 1 1 13A3 IN C8444 PEG_R2D_C_P<12> 0.1uF 1 13B3 C8410 IN C8445 PEG_R2D_C_N<12> 0.1uF 1 402 10% 16V X5R 402 10% 16V X5R 402 AK27 AJ27 PEG_D2R_C_P<0> PEG_D2R_C_N<0> 2 20% 6.3V CERM 805 13A3 13A3 W23 IN IN IN C8446 PEG_R2D_C_P<13> C8447 PEG_R2D_C_N<13> 0.1uF 0.1uF 1 1 13B3 IN PEG_R2D_P<1> PEG_R2D_N<1> AH30 AG30 PCIE_TX1P PCIE_TX1N PCIE_RX1P PCIE_RX1N 10% 16V X5R 402 10% 16V X5R 402 PEG_R2D_P<2> PEG_R2D_N<2> AG32 AF32 PCIE_TX2P PCIE_TX2N PCIE_RX2P PCIE_RX2N 13A3 P25 IN 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 PEG_R2D_P<3> PEG_R2D_N<3> AF31 AE31 PCIE_RX3P PCIE_RX3N PEG_R2D_P<4> PEG_R2D_N<4> AE30 AD30 PCIE_RX4P PCIE_RX4N PEG_R2D_P<5> PEG_R2D_N<5> AD32 AC32 PCIE_RX5P PCIE_RX5N 2 2 10% 16V X5R 402 10% 16V X5R 402 AJ25 AH25 PEG_D2R_C_P<1> PEG_D2R_C_N<1> 10% 16V X5R 402 10% 16V X5R 402 P26 13B3 P28 IN 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 0.1uF 1 2 AH28 C8460 0.1uF AG28 10% PEG_D2R_C_P<2> PEG_D2R_C_N<2> PEG_R2D_P<6> PEG_R2D_N<6> AC31 AB31 PCIE_RX6P PCIE_RX6N PCIE_TX3P PCIE_TX3N AG27 AF27 0.1uF C8462 0.1uF C8463 0.1uF C8464 0.1uF C8465 0.1uF 1 2 C8466 0.1uF 1 2 C8467 0.1uF 1 2 C8468 0.1uF 1 2 C8469 0.1uF 1 2 C8470 0.1uF 1 2 C8471 0.1uF 34B5 34B4 33B4 R23 34B5 34B4 33B4 PCIE_TX4P PCIE_TX4N AF25 AE25 PEG_D2R_C_P<4> PEG_D2R_C_N<4> IN IN T24 PCIE_VSS 1 2 1 2 10% PCIE_TX5P PCIE_TX5N AE28 AD28 PEG_D2R_C_P<5> PEG_D2R_C_N<5> 10% 10% PCIE_TX6P PCIE_TX6N AD27 AC27 PEG_D2R_C_P<6> PEG_D2R_C_N<6> PEG_R2D_P<7> PEG_R2D_N<7> AB30 AA30 PCIE_RX7P PCIE_RX7N PCIE_TX7P PCIE_TX7N AC25 AB25 10% PEG_D2R_C_P<7> PEG_D2R_C_N<7> PEG_R2D_P<8> PEG_R2D_N<8> AA32 Y32 PCIE_RX8P PCIE_RX8N PCIE_TX8P PCIE_TX8N AB28 10% AA28 PEG_D2R_C_P<8> PEG_D2R_C_N<8> 1 PEG_R2D_P<9> PEG_R2D_N<9> Y31 W31 PCIE_RX9P PCIE_RX9N PCIE_TX9P PCIE_TX9N AA27 Y27 PEG_D2R_C_P<9> PEG_D2R_C_N<9> 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 PEG_R2D_P<10> PEG_R2D_N<10> W30 V30 PCIE_RX10P PCIE_RX10N PCIE_TX10P PCIE_TX10N Y25 W25 C8472 0.1uF C8473 0.1uF 1 2 C8474 0.1uF 1 2 C8475 0.1uF 1 2 C8476 0.1uF 1 2 10% 10% PEG_R2D_P<11> PEG_R2D_N<11> V32 U32 PCIE_RX11P PCIE_RX11N PCIE_TX11P PCIE_TX11N W28 V28 C8477 0.1uF C8478 0.1uF C8479 0.1uF 1 2 C8480 0.1uF 1 2 C8481 0.1uF 1 2 C8482 0.1uF 1 2 C8483 0.1uF 1 2 C8484 0.1uF 1 2 1 2 10% PEG_D2R_C_P<11> PEG_D2R_C_N<11> 2 10% 2 PEG_R2D_P<12> PEG_R2D_N<12> U31 T31 PCIE_RX12P PCIE_RX12N PCIE_TX12P PCIE_TX12N V27 U27 PEG_D2R_C_P<12> PEG_D2R_C_N<12> 10% 2 10% 2 10% 16V X5R 402 10% 16V X5R 402 PEG_R2D_P<13> PEG_R2D_N<13> T30 R30 PCIE_RX13P PCIE_RX13N PCIE_TX13P PCIE_TX13N U25 T25 PEG_D2R_C_P<13> PEG_D2R_C_N<13> 10% 2 PEG_R2D_C_N<14> 2 10% 16V X5R 402 PEG_R2D_P<14> PEG_R2D_N<14> R32 P32 PCIE_RX14P PCIE_RX14N PCIE_TX14P PCIE_TX14N T28 R28 PEG_D2R_C_P<14> PEG_D2R_C_N<14> 10% 1 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 PEG_R2D_P<15> PEG_R2D_N<15> P31 N31 PCIE_RX15P PCIE_RX15N PCIE_TX15P PCIE_TX15N R27 P27 PEG_D2R_C_P<15> PEG_D2R_C_N<15> C8485 0.1uF 1 2 C8486 0.1uF 1 2 10% 2 10% PEG_CLK100M_GPU_P PEG_CLK100M_GPU_N AL28 AK28 PCIE_REFCLKP PCIE_REFCLKN 1 X5R 402 16V X5R 402 13C3 13D3 16V X5R 402 16V X5R 402 16V X5R 402 13C3 13D3 13C3 X5R 13D3 16V X5R 402 16V X5R 402 13C3 13D3 16V X5R 402 16V X5R 402 13C3 13D3 16V X5R 402 16V X5R 402 13C3 13D3 16V X5R X5R 16V X5R 402 16V X5R 402 OUT PEG_D2R_N<1> OUT D PEG_D2R_P<2> OUT PEG_D2R_N<2> OUT PEG_D2R_P<3> OUT PEG_D2R_N<3> OUT PEG_D2R_P<4> OUT PEG_D2R_N<4> OUT PEG_D2R_P<5> OUT PEG_D2R_N<5> OUT PEG_D2R_P<6> OUT PEG_D2R_N<6> OUT PEG_D2R_P<7> OUT 16V X5R 402 16V X5R 402 13D3 13C3 13D3 16V X5R 402 16V X5R 402 13C3 13C3 16V X5R 402 16V X5R 402 13C3 13C3 16V X5R 402 16V X5R 402 13C3 13C3 16V X5R 402 16V X5R 402 13C3 13C3 X5R PEG_D2R_N<7> OUT C 13C3 PEG_D2R_P<8> OUT PEG_D2R_N<8> OUT PEG_D2R_P<9> OUT PEG_D2R_N<9> OUT PEG_D2R_P<10> OUT PEG_D2R_N<10> OUT PEG_D2R_P<11> OUT PEG_D2R_N<11> OUT PEG_D2R_P<12> OUT PEG_D2R_N<12> OUT PEG_D2R_P<13> OUT PEG_D2R_N<13> OUT B 402 13C3 16V X5R 402 16V X5R 402 16V X5R 402 13C3 13C3 13C3 16V PEG_D2R_P<1> 402 13D3 16V OUT 402 13C3 16V OUT PEG_D2R_N<0> 402 2 10% 10% 16V 2 10% PEG_D2R_C_P<10> PEG_D2R_C_N<10> 13D3 16V PEG_D2R_P<0> 402 2 10% 1 X5R X5R PEG_D2R_P<14> OUT PEG_D2R_N<14> OUT PEG_D2R_P<15> OUT PEG_D2R_N<15> OUT 402 5D4 63B1 67C6 67D6 67D8 70C7 77B8 82D7 R8495 2.0K R26 AG31 2 10% R25 R31 1 10% R24 R29 2 PP1V2_D3C P30 AG29 1 10% PEG_D2R_C_P<3> PEG_D2R_C_N<3> 13C3 16V 2 C8461 P29 AG26 1 10% 2 2 1 C8459 10% 2 1 0.1uF 2 10% 2 1 C8451 1 2 0.1uF PEG_R2D_C_N<15> 2 0.1uF 10% 2 0.1uF 1 1 C8458 2 C8449 0.1uF C8457 0.1uF 10% 2 C8448 C8450 2 2 PEG_R2D_C_P<14> PEG_R2D_C_P<15> 2 1 10% 2 N30 P24 1 0.1uF 10% 10% N24 0.1uF C8456 10% 22UF 2 C8455 10% 2 2 1 X5R 2 1 1 16V 2 2 1 10% AH31 PCIE_TX0P PCIE_TX0N PCIE_RX0P PCIE_RX0N 2 2 26B1 5C4 AH24 IN 0.1uF 402 2 1 1 X5R AJ31 2 1 13B3 AC28 C8439 PEG_R2D_C_N<9> 22UF AB26 AC24 IN 22UF AL30 PCIE_VDDR_12 (1.2V) 0.1uF 16V 2 2000mA Y29 AA23 AA31 C8438 PEG_R2D_C_P<9> 22UF 2 Y28 AA29 IN 10% PEG_R2D_P<0> PEG_R2D_N<0> 2 PP1V2_S0_PCIE_GPU_PVDD_F 100mA W27 A 0.1uF 1 1 200-OHM-EMI B 0.1uF PCI-EXPRESS BUS INTERFACE 13B3 IN PEG_RESET_L AF24 PERST* PERST*_MASK AA24 PCIE_TEST AG24 NC PCIE_CALRP PCIE_CALRN AD24 AE24 GPU_PCIE_CALRP GPU_PCIE_CALRN PCIE_CALI AB24 GPU_PCIE_CALI 2 1% 1/16W MF-LF 402 T26 AH26 T27 AH27 T29 AH29 U24 AJ26 U26 AJ28 U28 R8497 1 1 1.47K 1% 1/16W MF-LF 402 R8496 562 2 2 1% 1/16W MF-LF 402 ATI M56 PCI-E SYNC_MASTER=(MASTER) AJ29 U29 AJ30 U30 AJ32 V24 AK26 V25 AK29 V26 AK30 V29 AK31 V31 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART AK32 W24 AL27 W26 SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 70 1 87 A 8 6 7 2 3 GPU VCore Current Sense 4 5 1 GPUISENS_NTC 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 82D5 82C6 82B3 82A4 79D3 79A8 1 R8596 GPU VCore Supply PP5V_S5 PPBUS_G3H 65B7 64C8 62C8 62B6 62B2 62A4 52B5 47C7 25C8 5D4 67C3 67C1 67B1 66D8 66B8 65D6 64A6 62D7 61D7 61D4 55D3 43D8 42B8 41C6 5C4 5A1 79B7 69C1 68D5 67C3 67C1 65D6 65B7 64D7 C8501 D 2.2UF 2 20% 6.3V CERM1 603 2 5% 1/16W MF-LF 402 20% 6.3V CERM1 603 2 GPUVCORE_BOOT_R C8590 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1 5C7 Stuff 4.7ohm for decreased slew rate 12 2 PVCC VCC U8500 2 GPUVCORE_FSET 7 UG GPUVCORE_EN 4 GPUVCORE_FCCM 66D8 66D4 63B3 63C3 66D7 3 P1V2R2V5D3C_EN_LS5V 16 5D7 1 R8508 C8507 150K 2 1 C8506 1 C 5 GPUVCORE_FB 1 6 15pF 1% 1/16W MF-LF 402 8 5% 50V CERM 402 0.22UF 2 2 20% 6.3V X5R 402 2 2 2 C8530 EN NO STUFF C8508 R8505 FCCM PGOOD COMP FB 1 2 3 13 LG 11 PGND 10 2 10% 50V CERM 402 2 5% 1/16W MF-LF 402 RJK0301DPB XW8501 C8522 SM 1000pF 1 GND_GPUVCORE_SGND 2 XW8500 XW8502 SM SM 1 1 2 10% 25V X7R 402 1M 2 C8592 470pF 2 1 1 2 1 2 3 C8521 18A max output 1 330UF (L8520 limit) 20% 2.5V 2 POLY CASE-D2E-LF 2 C8520 10% 50V CERM 402 1% 1/16W MF-LF 402 2 10% 25V X7R 402 C NO STUFF 1 0.0022uF 5.11K 2 C8542 GPUVCORE_FB_RC 1000pF 2 20% 6.3V CERM 805 R8522 1 NO STUFF 1 1 22UF 5% 1/16W MF-LF 2 402 1 2 3 RJK0301DPB LFPAK C8540 R8520 0 1% 1/16W MF-LF 402 2 Q8522 72D8 77A7 5B2 55A5 55C7 67A6 67A8 71B7 Vout = 1.10V / 0.95V NO STUFF 1 3.01K 17 4 55B6 R8592 GPUISENS_POS 1% 1/16W MF-LF 402 R8521 1 Q8521 4 NO STUFF OUT 2 PPVCORE_D3C_GPU 5 2 GPUVCORE_IOUT 10% 50V CERM 402 LFPAK 1 - 2 CRITICAL MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm THRML PAD 4 V- 5 2 1% 1/16W MF-LF 402 GPUVCORE_LG VO 2 SC70-5 FDA1055 5.11K 1 D HPA00141AIDCKR 5 + 1.2UH R8510 GPUVCORE_ISEN 20.0K 1% 1/16W MF-LF 402 1 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE 9 R8591 L8520 2 10% 6.3V CERM 402 CRITICAL V+ 1 CRITICAL GPUVCORE_PHASE 15 470pF 0 1uF U8595 1 1 649 1% 1/16W MF-LF 402 GPUISENS_NEG 3 GPUISENS_RC R8590 1 2 1 10% 6.3V CERM-X5R 402 RJK0305DPB MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm BOOT PHASE ISEN 2 Q8520 LFPAK 1% 1/16W MF-LF 402 C8595 0.22UF CRITICAL 1 1 2 C8591 GPUVCORE_COMP_R 1% 1/16W MF-LF 2 402 1M 1% 1/16W MF-LF 402 1 10% 6.3V CERM-X5R 402 20% 16V POLY CASED2E-SM GPUVCORE_BOOT FSET 20.0K 1 CRITICAL 4 57.6K 0.01UF 10% 16V CERM 402 R8506 GPUVCORE_COMP R8598 1 R8593 0.47UF CRITICAL 14 CRITICAL 66B5 5% 1/16W MF-LF 402 5 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm QFN VIN 4.7 1% 1/16W MF-LF 402 33uF C8509 1 GPUVCORE_UG ISL6269BCRZ 1 2 1 10% 50V CERM 402 2 2.2UF 0 2 Keep C8590, C8591 R8590, R8594 and R8597 close to inductor 2 1K 1 R8509 R8504 0603-LF 2 1 1 1 470pF Placement Note: R8594 C8500 C8598 10KOHM-5% NO STUFF 1 C8502 R8597 1 1uF 10% 16V X5R 603 1 1K 1% 1/16W MF-LF 402 PP3V3_S0 CRITICAL 1 C8541 1 22UF 2 2 (GPUVCORE_FB) C8543 330UF 20% 6.3V CERM 805 20% 2 2.5V POLY CASE-D2E-LF GND_GPUVCORE_PGND R8523 7.32K 1 Vout(low) Back-Bias Positive Supply = 0.6V * (1 + Ra / Rb) Vout(high) = 0.6V * (1 + Ra / Req) Back-bias positive supply provides VDDC + 0.5V when active. When inactive, provides VDDC to BBP pins. NOTE: BBP tracks VDDC based on GPU voltage GPIO. R8526 Req = Rb || Rc Q8575 5% 1/16W MF-LF 402 1 2 77A7 72D8 71C1 67A8 67A6 55C7 55A5 5B2 PPVCORE_D3C_GPU 71A5 71A8 3 10K D 4 71A6 71A4 3 GPUBB_EN B VIN PG EN 6 ADJ 5 20% 6.3V CERM1 603 1 10% 16V CERM 402 2 5C7 C8556 24.9K 0.01UF 2 77C3 74C8 74C5 20% 6.3V CERM 805 5% 1/16W MF-LF 402 1 2 2N7002 1 G SOT23-LF S 2 SOT-363 S 2 4 B 2 Back-bias negative supply provides VSS - 0.55V when active. When inactive, provides VSS to BBN pins. 77D2 77C6 77B7 74D6 74B2 71C4 71B8 67A5 67A3 65C7 82D7 82A7 80D5 80B2 Vout(low) PP3V3_D3C = 0.59V * (1 + Ra/Rb) C8580 Vout(high) = 0.59V * (1 + Ra/Req) 20% 6.3V X5R 603 58C7 58C4 57B5 55A8 53C4 36D6 31C5 25D8 5D4 5D2 81B3 80B5 80A1 79B8 67B3 67B1 67A1 66B5 62B1 61D7 71B8 71A6 PP5V_S0 1% 1/16W MF-LF 402 A D GPUBB_EN 0 1 1 2 5% 1/16W MF-LF 402 Q8570 G SOT23-LF S 2 2 SHDN_L IN 6 Vout = -Vin * Rb / Ra 1 R8588 CAP+ U8580 11.3K 2.2uF MAX1673 1% 1/16W MF-LF 402 20% 6.3V CERM1 603 SOI CRITICAL GPUBBN_CAPN 3 2 GPUBBN_FB C8581 CAP- OUT Recommended values: Ra = Vin / 50 uA Rb = -Vout / 50 uA GPU (M56) Core Supplies 2 5 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm PNBB_S0_GPU 1 C8570 0.0022uF 2N7002 71A4 71B8 71B7 NO STUFF 1 4 GPUBBN_CAPP 2 3 GPU_BB_CTL 1% 1/16W MF-LF 402 8 FB 1 2 GPUBB_EN_L 68.1K 2 MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm SI3446DV max Vgs is 1.6V Vin must be > 2.8V 4.7K For proper M56 power sequence, this pull-up must be powered before VCore GPU_GENERICD GPUBB_EN Pull-up voltage must be high enough to satisfy BBP FET Vgs (where Vs = 1.2V) R8570 1 R8561 R8587 1 1 10uF Req = Rb || Rc 77C3 1 Back-Bias Negative Supply 20% 6.3V CERM 805 GPUBBP_ADJ_LOW GPU_VCORE_HIGH 10% 16V CERM-X5R 402 C8557 22UF 1% 1/16W MF-LF 2 402 71B4 1 10K (LDO limit) 16.2K 1% 1/16W MF-LF 2 402 NO STUFF SOT-363 S 1 R8554 174K Q8554 G R8524 1 2 R8556 NO STUFF 3 5 G GPUBBP_ADJ 1 D GPU_VCORE_LOW 180mA max output 1 22UF 1% 1/16W MF-LF 2 402 2 67D1 67D3 72D6 Vout = (1.58V /) 1.50V R8555 1 C8555 1 2.2uF C8523 2 0.022uF 2N7002DW-X-F PPBB_S0_GPU VOUT GND C8551 2N7002DW-X-F GPU_VCORE_HIGH_RC Q8523 U8550 FAN2558 SOT23-6-LF 1 2 5% 1/16W MF-LF 402 3 6 Q8523 R8525 2 1 4 PP3V3_D3C 6 D GPU_VCORE_HIGH CRITICAL 80D5 80B2 77D2 77C6 71A4 67A5 67A3 65C7 77B7 74D6 74B2 71C4 82D7 82A7 1 5 GPUBB_EN_L GPUVCORE_FB_LOW 10K SI3446DV TSOP-LF 2 1% 1/16W MF-LF 402 PP3V3_D3C 77C6 77B7 74D6 74B2 71B8 71A4 67A5 67A3 65C7 82D7 82A7 80D5 80B2 77D2 LIN/SKIP_L GND 7 10% 50V CERM 402 1 C8589 20% 6.3V CERM 805 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING 125mA max output (Regulator limit) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 2 R8560 1 II NOT TO REPRODUCE OR COPY IT 10K 5% 1/16W MF-LF 402 SYNC_DATE=(MASTER) 67D1 67D3 72D2 Vout = -0.55V 22UF 2 SYNC_MASTER=(MASTER) III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE 2 APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 71 1 87 A 8 Page Notes 6 7 2 3 4 5 1 Power aliases required by this page: - =PP1V5_GPU_VDD15 - =PP1VR1V3_GPU_VCORE Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE) U8400 M56P BGA (7 OF 7) OMIT PPBB_S0_GPU 100mA (Preliminary) C8690 1 1 C8691 1 C8692 22UF 1uF 0.1uF 20% 6.3V CERM 805 10% 6.3V CERM 402 10% 16V X5R 402 2 2 2 1 C8601 1 1 C8604 1 20% 6.3V CERM 805 V10 BBP BBN AC14 1 C8606 1 C8607 1 C8608 1 C8609 1 C8610 100mA (Preliminary) R19 22UF 1uF 1uF 1uF 1uF 1uF 1uF 1uF T16 20% 6.3V CERM 805 20% 6.3V CERM 805 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 T17 2 2 2 2 2 2 2 2 T18 U15 U16 U17 1 C8611 1 1uF 2 R8630 10% 6.3V CERM 402 C8612 1 1uF 2 C8613 1 1uF 10% 6.3V CERM 402 2 C8614 1 1uF 10% 6.3V CERM 402 2 10% 6.3V CERM 402 C8615 1 1uF 2 10% 6.3V CERM 402 2 C8616 V14 1uF V15 10% 6.3V CERM 402 0 C 5% 1/10W MF-LF 603 VDDC (1.0V/1.2V) V16 1 2 82D7 73A8 73A5 67B8 67B6 64A4 5D4 76D8 76D5 75D8 75D5 73B8 73B5 2 2 PNBB_S0_GPU 67D1 67D3 71A2 M6 M7 M8 M9 M24 M28 M32 N3 N7 N8 P1 P5 P6 P7 P15 V18 P17 W14 R3 W15 R6 W19 R14 AC11 R16 AC12 T10 AD11 T15 PPVCORE_S0_GPU_VDDCI VOLTAGE=1.2V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm 2 AC17 P14 22UF 2 Y23 D C8695 22UF R17 C8605 1 10% 6.3V CERM 402 R18 C8600 1 1uF 10% 16V X5R 402 R15 14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI C8696 0.1uF R10 P19 PPVCORE_D3C_GPU 1 K15 M23 P18 77A7 71C1 71B7 67A8 67A6 55C7 55A5 5B2 C8697 K18 MEMORY & CORE POWER / GROUND D 71B5 67D3 67D1 C T19 C8630 1 1 C8631 1 C8632 1 C8633 1 K14 U1 C8634 P16 U5 T14 22UF 1uF 1uF 1uF 1uF 20% 6.3V CERM 805 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 2 2 2 2 2 T23 U19 U6 U7 VDDCI (1.0V/1.2V) U8 W10 U9 W17 U10 PP1V8_D3C U14 2.0A @ 500MHz 1.8V GDDR3 U18 A3 V3 A9 C8650 1 22UF 20% 6.3V CERM 805 C8651 1 22UF 2 20% 6.3V CERM 805 C8652 1 22UF 2 20% 6.3V CERM 805 C8653 1 1 22UF 2 20% 6.3V CERM 805 C8655 1 1uF 2 2 1 2 C8656 1 1uF 10% 6.3V CERM 402 2 C8661 1 10% 6.3V CERM 402 C8662 C8657 1 1uF 2 1 10% 6.3V CERM 402 C8663 C8658 1 1uF 2 1 10% 6.3V CERM 402 C8664 C8659 1 1uF 2 1 10% 6.3V CERM 402 C8665 2 1 C8660 A12 K23 F18 V6 1uF A15 A2 F19 V17 A18 A8 F21 V19 A21 A11 F22 A24 A13 F24 A30 A16 F27 Y1 C1 A19 F30 Y5 10% 6.3V CERM 402 C8666 1 2 1uF 1uF 1uF 1uF 1uF C32 A22 G13 Y6 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 F32 A25 G16 Y7 H13 A31 G19 AA4 H19 B1 G20 AA6 2 2 2 2 2 C8667 1 C8668 1 C8669 1 C8670 1 C8671 1 B32 G21 AC9 J10 C4 G22 AC10 C8672 J11 C5 G25 AD6 J13 C6 H1 AD7 J18 C9 H5 AD8 J19 C10 H7 AD9 J20 C15 H16 AD10 C18 H20 AD13 C20 H21 C21 H28 1uF 1uF 1uF 1uF 1uF 1uF 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 2 2 2 2 2 J32 1 2 1 2 W18 1uF J1 B W16 VSS C8673 1 C8674 1 C8675 1 C8676 1 C8677 1 C8678 K11 VSS VDDR1 (1.8V/2.0V) AD14 AD15 1uF 1uF 1uF 1uF 1uF 1uF K13 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 K19 C24 H32 K20 C27 J3 AD17 K21 D11 J6 AE8 K24 D30 J9 AE14 2 C8679 1 C8680 2 1 C8681 2 1 C8682 2 1 E5 J12 AE15 L24 E8 J16 AE16 L32 E9 J21 AE17 1uF 1uF 1uF 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 2 2 AD16 L23 1uF 2 VSS C8683 1uF 2 2 A M1 E12 J24 AF14 M10 E13 J28 AF16 N9 E16 J30 AG11 N10 E19 K10 AG16 P8 E25 K12 AG23 P9 E28 K16 AH10 P10 E30 K17 AH11 R1 E32 K27 AH16 R9 F3 K30 AJ10 V1 F6 L1 AK16 Y8 F10 L6 AL1 AL13 Y9 F13 L7 Y10 F15 L29 AA1 F16 M3 B ATI M56 Core Power SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY AM2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING AM13 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 72 1 87 A 6 IO IO 75B6 IO 75B6 IO 75B6 IO 75B6 IO 75B6 IO 75B6 IO 75B6 IO 75B6 IO 75B6 IO 75B6 75A6 IO 75A6 IO 75A6 IO 75A6 C IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75A6 IO 75B3 IO 1 1 40.2 1% 1/16W MF-LF 402 R8712 IO 75B3 IO 75B3 IO 75B3 IO 75B3 IO 75B3 IO 2 1% 1/16W MF-LF 402 IO 75B3 IO 75B3 IO 75B3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 75A3 IO 40.2 2 IO 75B3 75B3 B IO 75A6 75B3 PP1V8_D3C IO 75A3 IO 75A3 IO FB_A_DQ<0> FB_A_DQ<1> FB_A_DQ<2> FB_A_DQ<3> FB_A_DQ<4> FB_A_DQ<5> FB_A_DQ<6> FB_A_DQ<7> FB_A_DQ<8> FB_A_DQ<9> FB_A_DQ<10> FB_A_DQ<11> FB_A_DQ<12> FB_A_DQ<13> FB_A_DQ<14> FB_A_DQ<15> FB_A_DQ<16> FB_A_DQ<17> FB_A_DQ<18> FB_A_DQ<19> FB_A_DQ<20> FB_A_DQ<21> FB_A_DQ<22> FB_A_DQ<23> FB_A_DQ<24> FB_A_DQ<25> FB_A_DQ<26> FB_A_DQ<27> FB_A_DQ<28> FB_A_DQ<29> FB_A_DQ<30> FB_A_DQ<31> FB_A_DQ<32> FB_A_DQ<33> FB_A_DQ<34> FB_A_DQ<35> FB_A_DQ<36> FB_A_DQ<37> FB_A_DQ<38> FB_A_DQ<39> FB_A_DQ<40> FB_A_DQ<41> FB_A_DQ<42> FB_A_DQ<43> FB_A_DQ<44> FB_A_DQ<45> FB_A_DQ<46> FB_A_DQ<47> FB_A_DQ<48> FB_A_DQ<49> FB_A_DQ<50> FB_A_DQ<51> FB_A_DQ<52> FB_A_DQ<53> FB_A_DQ<54> FB_A_DQ<55> FB_A_DQ<56> FB_A_DQ<57> FB_A_DQ<58> FB_A_DQ<59> FB_A_DQ<60> FB_A_DQ<61> FB_A_DQ<62> FB_A_DQ<63> GPU_MVREFD0 GPU_MVREFS0 R8711 1 1 C8711 100 1% 1/16W MF-LF 402 1 2 1 100 0.1uF 10% 16V X5R 402 R8713 2 2 2 M30 L31 L30 H30 G31 G30 F31 M27 M29 L28 L27 J27 H29 G29 G27 M26 L26 M25 L25 J25 G28 H27 H26 F26 G26 H25 H24 H23 H22 J23 J22 E23 D22 D23 E22 E20 F20 D19 D18 B19 B18 C17 B17 C14 B14 C13 B13 D17 E18 E17 F17 E15 E14 F14 D13 H18 H17 G18 G17 G15 G14 H14 J14 C31 C30 A27 C8713 A28 0.1uF 1% 1/16W MF-LF 402 M31 BGA (4 OF 7) DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63 MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9 MAA_10 MAA_11 MAA_12 MAA_13 MAA_14 MAA_15 MEMORY INTERFACE A 75B6 75B6 M56P BGA (3 OF 7) MVREFD_0 MVREFS_0 (1.8V/ VDDRH0 2.0V) VSSRH0 75B6 DQMA_0* 75B6 DQMA_1* 75B6 DQMA_2* 75B6 DQMA_3* 75B3 DQMA_4* 75B3 DQMA_5* 75B3 DQMA_6* 75B3 DQMA_7* READ STROBE D R8710 OMIT U8400 WRITE STROBE BOM options provided by this page: (NONE) 76D8 76D5 75D8 75D5 67B8 67B6 64A4 5D4 73B5 73A8 73A5 72B8 82D7 OMIT U8400 M56P Signal aliases required by this page: (NONE) QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7 QSA_0* QSA_1* QSA_2* QSA_3* QSA_4* QSA_5* QSA_6* QSA_7* CLKA0 CLKA0* CSA0_0* CSA0_1* D26 75B8 75B5 F28 75B8 75B5 D25 75B8 75B5 75B8 75B5 E24 75B8 75B5 E26 75B8 75B5 D27 75B8 75B5 F25 75B8 75B5 C26 75B8 75B5 B26 75B8 75B5 D29 75B8 75B5 B27 75B8 75B5 E27 74C2 74C1 E29 75A8 75A5 B25 75A8 75A5 C25 75A8 75A5 D28 FB_A_MA<0> FB_A_MA<1> FB_A_MA<2> FB_A_MA<3> FB_A_MA<4> FB_A_MA<5> FB_A_MA<6> FB_A_MA<7> FB_A_MA<8> FB_A_MA<9> FB_A_MA<10> FB_A_MA<11> NC_FB_A_MA12 FB_A_BA<2> FB_A_BA<0> FB_A_BA<1> FB_A_DQM_L<0> FB_A_DQM_L<1> FB_A_DQM_L<2> FB_A_DQM_L<3> FB_A_DQM_L<4> FB_A_DQM_L<5> FB_A_DQM_L<6> FB_A_DQM_L<7> H31 J29 J26 G23 E21 B15 D14 J17 K25 F23 D20 B16 D16 H15 K31 75A8 K28 75A8 K26 75A8 G24 75A8 D21 75A5 C16 75A5 D15 75A5 J15 75A5 D31 75B8 E31 75B8 75B8 FB_A_WDQS<0> FB_A_WDQS<1> FB_A_WDQS<2> FB_A_WDQS<3> FB_A_WDQS<4> FB_A_WDQS<5> FB_A_WDQS<6> FB_A_WDQS<7> FB_A_CLK_P<0> FB_A_CLK_N<0> FB_A_CS_L<0> IO 76A6 IO 76A6 IO OUT OUT OUT OUT OUT 76A6 IO 76A6 IO 76A6 IO 76B6 IO 76B6 IO OUT 76B6 IO OUT 76B6 IO OUT 76B6 IO OUT 76B6 IO OUT 76B6 IO 76B6 IO OUT OUT 76B6 IO 76B6 IO IO 76B6 IO IO 76B6 IO IO 76A6 IO IO 76A6 IO IO 76A6 IO IO 76A6 IO IO 76A6 IO 76A6 IO IO IN 76A6 IO IN 76A6 IO IN 76A6 IO IN 76A6 IO IN 76A6 IO IN 76A6 IO IN 76A3 IO IN 76A3 IO OUT 76A3 IO OUT 76A3 IO 76A3 IO 76A3 IO 76A3 IO 76A3 IO OUT OUT OUT OUT OUT OUT OUT OUT OUT 76A3 IO 76A3 IO 76A3 IO 76B3 IO 76B3 IO 76B3 IO 76B3 IO 76B3 IO 76B3 IO 76B3 IO NC 75B8 FB_A_CKE<0> OUT B28 75A8 FB_A_RAS_L<0> OUT CASA0* C29 75A8 FB_A_CAS_L<0> OUT WEA0* B31 75A8 FB_A_WE_L<0> OUT TP_FB_A_ODT<0> ODTA0 F29 CLKA1 CLKA1* B20 75B5 C19 75B5 75B5 FB_A_CLK_P<1> FB_A_CLK_N<1> FB_A_CS_L<1> OUT OUT OUT 82D7 76D8 76D5 72B8 67B8 67B6 64A4 5D4 75D8 75D5 73B8 73A8 73A5 PP1V8_D3C OUT NC R8720 1 1 40.2 CKEA1 C22 75B5 FB_A_CKE<1> RASA1* B24 75A5 FB_A_RAS_L<1> CASA1* B22 75A5 FB_A_CAS_L<1> OUT WEA1* B21 75A5 FB_A_WE_L<1> OUT ODTA1 D24 TP_FB_A_ODT<1> OUT OUT OUT 1% 1/16W MF-LF 402 76B3 IO 76B3 IO 76B3 IO 76B3 IO 76B3 IO 76A3 IO 76A3 IO 76A3 IO 76A3 IO 76A3 IO 76A3 IO 76A3 IO 76A3 IO 40.2 2 2 1% 1/16W MF-LF 402 GPU_MVREFD1 GPU_MVREFS1 R8721 1 100 1% 1/16W MF-LF 402 10% 16V X5R 402 R8722 L8715 FERR-220-OHM PP1V8_D3C 1 C8721 1 2 1 100 0.1uF 10% 16V X5R 402 R8723 2 2 PP1V8R2V0_S0_GPU_VDDRH1 C8723 2 1 2 75D8 75D5 73B8 73B5 73A8 72B8 67B8 67B6 64A4 5D4 82D7 76D8 76D5 PP1V8_D3C PP1V8R2V0_S0_GPU_VDDRH0 0402 10% 16V X5R 402 GPU_TEST_MCLK GPU_TEST_YCLK GPU_MEMTEST 2 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 1 0402 C8715 1 C8716 C8725 1 1 C8726 1uF 1uF 1uF 1uF 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 10% 6.3V CERM 402 2 2 C12 B11 C11 C8 B7 C7 B6 F12 D12 E11 F11 F9 D8 D7 F7 G12 G11 H12 H11 H9 E7 F8 G8 G6 G7 H8 J8 K8 L8 K9 L9 K5 L4 K4 L5 N5 N6 P4 R4 P2 R2 T3 T2 W3 W2 Y3 Y2 T4 R5 T5 T6 V5 W5 W6 Y4 R8 T8 R7 T7 V7 W7 W8 W9 B3 C3 F1 AA5 AA2 AA7 DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63 MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8 MAB_9 MAB_10 MAB_11 MAB_12 MAB_13 MAB_14 MAB_15 G4 76B8 76B5 E6 76B8 76B5 76B6 DQMB_0* 76B6 DQMB_1* 76B6 DQMB_2* 76B6 DQMB_3* 76B3 DQMB_4* 76B3 DQMB_5* 76B3 DQMB_6* 76B3 DQMB_7* B8 QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7 B9 MVREFD_1 MVREFS_1 (1.8V/ VDDRH1 2.0V) VSSRH1 TEST_MCLK TEST_YCLK MEMTEST FB_B_MA<0> FB_B_MA<1> FB_B_MA<2> FB_B_MA<3> FB_B_MA<4> 76B8 76B5 FB_B_MA<5> 76B8 76B5 FB_B_MA<6> 76B8 76B5 FB_B_MA<7> 76B8 76B5 FB_B_MA<8> 76B8 76B5 FB_B_MA<9> 76B8 76B5 FB_B_MA<10> 76B8 76B5 FB_B_MA<11> 74C2 74C1 NC_FB_B_MA12 76A8 76A5 FB_B_BA<2> 76A8 76A5 FB_B_BA<0> 76A8 76A5 FB_B_BA<1> H4 J5 G5 F4 H6 G3 G2 D4 F2 F5 D5 H2 H3 2 4.7K 2 5% 1/16W MF-LF 402 2 OUT OUT OUT OUT OUT D9 G9 K7 M5 V2 W4 T9 OUT OUT OUT OUT OUT OUT OUT OUT OUT V8 FB_B_RDQS<0> 76A8 FB_B_RDQS<1> 76A8 FB_B_RDQS<2> 76A8 FB_B_RDQS<3> 76A5 FB_B_RDQS<4> 76A5 FB_B_RDQS<5> 76A5 FB_B_RDQS<6> 76A5 FB_B_RDQS<7> QSB_0* QSB_1* QSB_2* QSB_3* QSB_4* QSB_5* QSB_6* QSB_7* B10 76A8 V9 FB_B_WDQS<0> 76A8 FB_B_WDQS<1> 76A8 FB_B_WDQS<2> 76A8 FB_B_WDQS<3> 76A5 FB_B_WDQS<4> 76A5 FB_B_WDQS<5> 76A5 FB_B_WDQS<6> 76A5 FB_B_WDQS<7> CLKB0 CLKB0* B4 76B8 B5 FB_B_CLK_P<0> 76B8 FB_B_CLK_N<0> CSB0_0* CSB0_1* D2 76B8 FB_B_CS_L<0> 76A8 D10 H10 K6 N4 U2 U4 E10 G10 J7 M4 U3 V4 IO IO IO IO IO IO IO IO OUT OUT OUT OUT OUT OUT OUT C OUT IN IN IN IN IN IN IN IN OUT OUT OUT NC E3 CKEB0 C2 76B8 FB_B_CKE<0> OUT RASB0* E2 76A8 FB_B_RAS_L<0> OUT CASB0* D3 76A8 FB_B_CAS_L<0> OUT WEB0* B2 76A8 FB_B_WE_L<0> OUT ODTB0 D6 TP_FB_B_ODT<0> OUT CLKB1 CLKB1* N2 P3 FB_B_CLK_P<1> 76B5 FB_B_CLK_N<1> CSB1_0* CSB1_1* K2 76B5 FB_B_CS_L<1> 76B5 OUT OUT B OUT NC K3 CKEB1 L3 76B5 FB_B_CKE<1> RASB1* J2 76A5 FB_B_RAS_L<1> CASB1* L2 76A5 FB_B_CAS_L<1> OUT WEB1* M2 76A5 FB_B_WE_L<1> OUT ODTB1 J4 TP_FB_B_ODT<1> OUT DRAM_RST D OUT FB_B_DQM_L<0> FB_B_DQM_L<1> FB_B_DQM_L<2> FB_B_DQM_L<3> FB_B_DQM_L<4> FB_B_DQM_L<5> FB_B_DQM_L<6> FB_B_DQM_L<7> AA3 1 76A8 76A5 75A8 75A5 1 OUT FB_DRAM_RST OUT OUT R8733 4.7K 2 2 1 R8730 1 OUT 76B8 76B5 76B8 76B5 76B8 76B5 E4 4.7K FERR-220-OHM 1 B12 E1 0.1uF 1% 1/16W MF-LF 402 L8725 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V FB_B_DQ<0> FB_B_DQ<1> FB_B_DQ<2> FB_B_DQ<3> FB_B_DQ<4> FB_B_DQ<5> FB_B_DQ<6> FB_B_DQ<7> FB_B_DQ<8> FB_B_DQ<9> FB_B_DQ<10> FB_B_DQ<11> FB_B_DQ<12> FB_B_DQ<13> FB_B_DQ<14> FB_B_DQ<15> FB_B_DQ<16> FB_B_DQ<17> FB_B_DQ<18> FB_B_DQ<19> FB_B_DQ<20> FB_B_DQ<21> FB_B_DQ<22> FB_B_DQ<23> FB_B_DQ<24> FB_B_DQ<25> FB_B_DQ<26> FB_B_DQ<27> FB_B_DQ<28> FB_B_DQ<29> FB_B_DQ<30> FB_B_DQ<31> FB_B_DQ<32> FB_B_DQ<33> FB_B_DQ<34> FB_B_DQ<35> FB_B_DQ<36> FB_B_DQ<37> FB_B_DQ<38> FB_B_DQ<39> FB_B_DQ<40> FB_B_DQ<41> FB_B_DQ<42> FB_B_DQ<43> FB_B_DQ<44> FB_B_DQ<45> FB_B_DQ<46> FB_B_DQ<47> FB_B_DQ<48> FB_B_DQ<49> FB_B_DQ<50> FB_B_DQ<51> FB_B_DQ<52> FB_B_DQ<53> FB_B_DQ<54> FB_B_DQ<55> FB_B_DQ<56> FB_B_DQ<57> FB_B_DQ<58> FB_B_DQ<59> FB_B_DQ<60> FB_B_DQ<61> FB_B_DQ<62> FB_B_DQ<63> IO 76A3 B30 C23 IO OUT CKEA0 B23 IO 76A6 OUT RASA0* CSA1_0* CSA1_1* 76A6 76A6 FB_A_RDQS<0> 75A8 FB_A_RDQS<1> 75A8 FB_A_RDQS<2> 75A8 FB_A_RDQS<3> 75A5 FB_A_RDQS<4> 75A5 FB_A_RDQS<5> 75A5 FB_A_RDQS<6> 75A5 FB_A_RDQS<7> K29 C28 OUT 75A8 J31 B29 OUT R8731 82D7 75D5 73B8 73B5 67B6 64A4 5D4 73A5 72B8 67B8 76D8 76D5 75D8 1 MEMORY INTERFACE B Power aliases required by this page: - =PP1V8R2V0_S0_FB_GPU 2 3 4 5 READ STROBE 7 WRITE STROBE 8 Page Notes 5% 1/16W MF-LF 402 R8732 243 2 1% 1/16W MF-LF 402 ATI M56 Frame Buffer I/F A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 73 1 87 A 8 6 7 2 3 4 5 1 ROMCFGID[3..0] 77D2 77C6 77B7 74B2 71C4 71B8 71A4 67A5 67A3 65C7 82D7 82A7 80D5 80B2 0000 0010 0100 0110 PP3V3_D3C NO STUFF R8800 1 D Misc 77D3 GPU_GPIO_1 77D3 GPU_GPIO_2 77D3 GPU_GPIO_3 77D3 GPU_GPIO_4 77D3 GPU_GPIO_5 77D3 GPU_GPIO_6 82A4 77D3 74C5 77D3 77C3 77C3 74C5 C GPU_GPIO_0 TESTIN[0] TX_PWRS_ENb IPD TESTIN[1] TX_DEEMPH_EN TESTIN[2] Reserved TESTIN[3] Reserved TESTIN[4] DEBUG_ACCESS TESTIN[5] Reserved 10K 10K 10K 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 IPD TESTIN[6] IPD GPU_GPIO_11 GPU_GPIO_12 ENA_BL TESTIN[7] ROMSO TESTWR R8803 2 NO STUFF 1 R8805 1 10K 10K 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 2 GPU_MEM_64M 1 R8808 10K 2 2 2 R8813 2 NO STUFF 1 10K 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 2 2 GPU_MEM_NOT_SAM R8811 1 R8827 10K 2 5% 1/16W MF-LF 402 Renamed signals GPU_CLK27M GPU_CLK27M Unused signals 77A5 74C1 NC_GPU_XTALOUT 77A3 74C1 NC_ATI_ROMCS_L GPU_BLON 74C1 73D5 NC_FB_A_MA12 74C1 73D1 NC_FB_B_MA12 ROMIDCFG[3] TESTOUT[9] ROMIDCFG[0] IPD TESTOUT[10] ROMIDCFG[1] 74C8 77C3 Required for debug access 77C3 74C1 NC_GPU_GENERICA 77C3 74C1 NC_GPU_GENERICB Required for debug access 77C3 74C1 NC_GPU_GENERICC 78C3 74C1 NC_GPU_VGA_R 77C3 GPU_GPIO_13 TESTOUT[11] ROMIDCFG[2] Required for debug access TESTIN[8] NC_GPU_GPIO_14 NC_GPU_GPIO_14 NO_TEST=TRUE 74C8 77C3 78C3 74C1 NC_GPU_VGA_G 78C3 74C1 NC_GPU_VGA_B MAKE_BASE=TRUE 77C3 74C5 71B4 TESTIN[9] GPU_VCORE_LOW PWRCNTL GPU_VCORE_LOW SS_IN GPU_CLK27MSS_IN GPU_CLK27MSS_IN Thm Mon Int NC_GPU_GPIO_17 NC_GPU_GPIO_17 78B3 74C1 TP_GPU_VGA_HSYNC 34B2 34B4 74C8 77C3 78B3 74C1 TP_GPU_VGA_VSYNC 77D5 74B7 NC_GPU_GPIO_19 77D5 74B7 NC_GPU_GPIO_20 77D5 74B7 NC_GPU_GPIO_21 77D5 74B7 NC_GPU_GPIO_22 77D5 74B7 NC_GPU_GPIO_23 77D5 74B6 GPU_MEM_256M 77D5 74B7 NC_GPU_GPIO_25 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_GPIO_18 74B8 77D5 NC_GPU_GPIO_19 74B8 77D5 NO_TEST=TRUE 74C8 77C3 78B3 74C1 NC_GPU_TV_Y 78B3 74B1 NC_GPU_TV_C 78B3 74B1 NC_GPU_GPIO_20 74B8 77D5 78B3 NC_GPU_GPIO_21 74B8 77D5 78B3 74B1 77D5 74B7 NC_GPU_GPIO_26 GPU_MEMID 74B1 NC_LVDS_U_DATAP<3> 78A3 74B1 NC_LVDS_L_DATAP<3> NC_GPU_GPIO_23 74B8 77D5 78A3 74B1 NC_LVDS_L_DATAN<3> MAKE_BASE=TRUE 74B2 78B3 NC_GPU_TV_COMP 74B2 78B3 NC_LVDS_U_DATAP<3> 74B2 78B3 NC_LVDS_U_DATAN<3> 74B2 78B3 NC_LVDS_L_DATAP<3> 74B2 78A3 NC_LVDS_L_DATAN<3> 74B2 78A3 NC_ATI_DVPCLK 74B2 77C3 NO_TEST=TRUE MAKE_BASE=TRUE GPU_MEM_256M NO_TEST=TRUE 77C3 74B1 NC_ATI_DVPCLK 77C3 77B3 NC_ATI_DVPCNTL<2..0> MAKE_BASE=TRUE 74B8 77D5 NO_TEST=TRUE ATI_DVPCNTL<2..0> MAKE_BASE=TRUE 74B8 77D5 77B3 77D5 74B8 74C2 78B3 NC_GPU_TV_C NO_TEST=TRUE 74B8 77D5 NC_GPU_GPIO_26 74C2 78B3 NC_GPU_TV_Y NO_TEST=TRUE NC_LVDS_U_DATAN<3> NC_GPU_GPIO_22 MAKE_BASE=TRUE NO_TEST=TRUE 74C2 78B3 TP_GPU_VGA_VSYNC NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 77D5 74B6 NC_GPU_TV_COMP MAKE_BASE=TRUE NC_GPU_GPIO_25 MAKE_BASE=TRUE NO_TEST=TRUE 74C2 78C3 TP_GPU_VGA_HSYNC NO_TEST=TRUE MAKE_BASE=TRUE 77D5 74B8 74C2 78C3 NC_GPU_VGA_B NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_VGA_G C MAKE_BASE=TRUE MAKE_BASE=TRUE NC_GPU_GPIO_18 74C2 78C3 MAKE_BASE=TRUE MAKE_BASE=TRUE 77D5 74B7 74C2 77C3 NC_GPU_VGA_R NO_TEST=TRUE 71B4 74C8 77C3 MAKE_BASE=TRUE 77C3 74C5 74C2 77C3 NC_GPU_GENERICC NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 77C3 74C5 34B4 34B2 74C2 77C3 NC_GPU_GENERICB NO_TEST=TRUE MAKE_BASE=TRUE 77C3 74C5 NC_GPU_GENERICA NO_TEST=TRUE MAKE_BASE=TRUE IPD 73D1 74C2 NO_TEST=TRUE MAKE_BASE=TRUE Required for debug access 73D5 74C2 NC_FB_B_MA12 NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NC_FB_A_MA12 NO_TEST=TRUE MAKE_BASE=TRUE TP_GPU_GPIO_10 74C2 77A3 NO_TEST=TRUE MAKE_BASE=TRUE TESTOUT[8] 74C2 77A5 NC_ATI_ROMCS_L NO_TEST=TRUE MAKE_BASE=TRUE 74C8 77D3 82A4 MAKE_BASE=TRUE NC_GPU_XTALOUT NO_TEST=TRUE MAKE_BASE=TRUE Reserved IPD 34B2 34B4 74C2 77A5 MAKE_BASE=TRUE Reserved ROMSI ROMSCK TP_GPU_GPIO_10 77C3 R8801 2 NO STUFF 1 MAKE_BASE=TRUE GPU_GPIO_8 77C3 2 D R8824 1 10K 77A5 74C1 34B4 34B2 VDD_VCL GPU_BLON GPU_GPIO_9 GPU_MEM_256M R8812 1 5% 1/16W MF-LF 402 Straps IPD GPU_MEM_256M R8809 1 10K 2 77D3 NO STUFF R8806 1 5% 1/16W MF-LF 402 GPU_DEEPMH_EN TestBus NO STUFF R8804 1 128MB 256MB 64MB Reserved 10K 1 Serial ROM NO STUFF R8802 1 = = = = NO_TEST=TRUE NC_ATI_DVPDATA<15..0> ATI_DVPDATA<15..0> MAKE_BASE=TRUE GPU_MEMID NO_TEST=TRUE MAKE_BASE=TRUE B 77D5 74B7 NC_GPU_GPIO_28 77C5 74B7 NC_GPU_GPIO_29 77C5 74B7 NC_GPU_GPIO_30 77C5 74B7 NC_GPU_GPIO_31 77C5 74B7 NC_GPU_GPIO_32 77C5 74B7 NC_GPU_GPIO_33 77C5 74B7 NC_GPU_GPIO_34 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE NC_GPU_GPIO_28 74B8 77D5 NC_GPU_GPIO_29 74B8 77C5 NC_GPU_GPIO_30 74B8 77C5 NC_GPU_GPIO_31 74B8 77C5 NC_GPU_GPIO_32 74B8 77C5 NC_GPU_GPIO_33 74B8 77C5 NC_GPU_GPIO_34 74B8 77C5 B Required for debug access 77B3 77A3 TP_ATI_DVPDATA<23..16> ATI_DVPDATA<23..16> MAKE_BASE=TRUE Also required: GPIO10 - GPIO13 77D2 77C6 77B7 74D6 71C4 71B8 71A4 67A5 67A3 65C7 82D7 82A7 80D5 80B2 PP3V3_D3C MAKE_BASE=TRUE NO_TEST=TRUE R8890 1 78A3 78A3 R8891 1 4.7K 4.7K 5% 1/16W MF-LF 402 2 5% 1/16W MF-LF 402 2 GPU_DDC_B_CLK GPU_DDC_B_DATA GPU Straps A SYNC_MASTER=M57_MLB_MG SYNC_DATE=08/08/2006 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 74 1 87 A 73B8 73B5 73A8 73A5 72B8 67B8 67B6 64A4 5D4 IN 82D7 76D8 76D5 75D8 75D5 1 1 22UF 20% 6.3V CERM 805 2 2 C8901 1 C8902 1 C8903 C8904 1 0.1uF 0.1uF 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 2 2 F1 PP1V8_S0_FB_A0_VDDA0 2 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 L8915 1 FERR-220-OHM 1 PP1V8_S0_FB_A0_VDDA1 2 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 2 C8910 C8915 1 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 2 U8900.J1 M12 VDD5 V2 VDD6 VDD7 22UF 20% 6.3V CERM 805 2 2 C8921 1 C8922 1 1 C8924 1 C8925 1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 2 2 2 2 R8932 2.37K 2.37K 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 2 C 1 VSSA1 J12 R8931 R8933 5.49K 1 FERR-220-OHM 1 VDDQ3 VDDQ4 VSSQ3 VSSQ4 B12 VDDQ5 VSSQ5 D4 VDDQ6 VDDQ7 VSSQ6 VSSQ7 D9 E9 VDDQ8 VSSQ8 G2 0.1uF 10% 16V X5R 402 10% 16V X5R 402 2 2 VDDQ9 VDDQ10 VSSQ9 VSSQ10 G11 J9 VDDQ11 VSSQ11 L11 2 F1 PP1V8_S0_FB_A1_VDDA0 L8965 1 C8960 C8965 1 0.1uF PP1V8_S0_FB_A1_VDDA1 2 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 2 0.1uF 10% 16V X5R 402 10% 16V X5R 402 2 U8900.J1 M1 VDD3 VDD4 M12 VDD5 V2 VDD6 VDD7 22UF 20% 6.3V CERM 805 2 2 C8971 1 C8972 1 C8973 1 C8974 1 C8975 1 C8976 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 2 2 2 2 VDDQ3 VDDQ4 VSSQ3 VSSQ4 B12 C9 C12 VDDQ5 VSSQ5 D4 E1 VDDQ6 VDDQ7 VSSQ6 VSSQ7 D9 E4 E9 VDDQ8 VSSQ8 G2 G11 J9 VDDQ11 VSSQ11 L11 N1 VDDQ12 VDDQ13 VSSQ12 VSSQ13 P1 VDDQ14 VDDQ15 VSSQ14 VSSQ15 P9 N12 R1 VDDQ16 VSSQ16 T1 R4 VDDQ17 VDDQ18 VSSQ17 VSSQ18 T4 R9 R12 VDDQ19 VSSQ19 T12 V1 VDDQ20 VDDQ21 VDDQ16 VSSQ16 T1 2.37K R12 VDDQ19 VSSQ19 T12 V1 VDDQ20 VDDQ21 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 H1 VREF0 H12 VREF1 R8982 2 2 FB_A1_VREF0 V12 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm FB_A1_VREF1 D12 VSSQ9 VSSQ10 R1 2.37K D1 VDDQ9 VDDQ10 VSSQ14 VSSQ15 H1 VREF0 H12 VREF1 D B9 J4 VDDQ14 VDDQ15 R8980 J12 B4 N12 T9 J1 VSSA1 VSSQ1 VSSQ2 N9 T4 VSSA0 BOM options provided by this page: (NONE) V10 VDDQ1 VDDQ2 N4 VSSQ17 VSSQ18 V3 A12 P9 VDDQ17 VDDQ18 L12 VSS6 VSS7 B1 P4 R9 VSS5 Signal aliases required by this page: (NONE) L1 VSSQ0 P1 1 G12 Power aliases required by this page: - =PP1V8_S0_FB_VDD - =PP1V8_S0_FB_VDDQ G1 VDDQ0 VSSQ12 VSSQ13 1 VSS3 VSS4 A1 VDDQ12 VDDQ13 P12 A10 VDDA0 E12 1 1 A3 VSS1 VSS2 VDDA1 PP1V8_D3C C8970 L2 FBGA (2 OF 2) VSS0 K1 C4 U8900.J12 U8950 K12 C1 Connect to designated pin, then GND 75D8 75D5 73B8 73B5 67B8 67B6 64A4 5D4 IN 73A8 73A5 72B8 82D7 76D8 76D5 VDD1 VDD2 F12 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 D12 J4 C8954 1 0.1uF 10% 16V X5R 402 D1 E4 C8953 0.1uF VDD0 1 Page Notes L2 P4 P12 T9 C MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1 1 5.49K 1% 1/16W MF-LF 402 2 C8952 10% 16V X5R 402 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1 1 0.1uF A2 A11 V11 2 B9 V12 FB_A0_VREF1 J1 B4 2 FB_A0_VREF0 FERR-220-OHM VSSA0 2 2 C8951 L8960 VSSQ1 VSSQ2 R4 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm V10 L1 VDDQ1 VDDQ2 N9 R8930 V3 20% 6.3V CERM 805 A12 N1 1 L12 VSS6 VSS7 1 1 22UF B1 N4 1 VSS5 C8950 VSSQ0 C9 C8926 G12 G1 VDDQ0 C12 C8923 VSS3 VSS4 A1 E12 1 A10 VDDA1 PP1V8_D3C 1 A3 VSS1 VSS2 K12 E1 C8920 FBGA (2 OF 2) VSS0 VDDA0 C4 U8900.J12 U8900 K1 C1 Connect to designated pin, then GND 75D8 75D5 73B8 73B5 67B8 67B6 64A4 5D4 IN 73A8 73A5 72B8 82D7 76D8 76D5 M1 VDD3 VDD4 V11 FERR-220-OHM D VDD1 VDD2 F12 L8910 1 VDD0 K4J52324QC-BC20 C8900 A2 A11 CRITICAL OMIT PP1V8_D3C K4J52324QC-BC20 CRITICAL OMIT PP1V8_D3C 2 3 4 5 16MX32-GDDR3-500MHZ 75D8 75D5 73B8 73B5 67B8 67B6 64A4 5D4 IN 73A8 73A5 72B8 82D7 76D8 76D5 6 7 16MX32-GDDR3-500MHZ 8 1% 1/16W MF-LF 402 2 C8931 1 C8933 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 2 2 R8981 1 R8983 5.49K 1 1 5.49K 1% 1/16W MF-LF 402 2 1% 1/16W MF-LF 402 2 C8981 1 C8983 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 2 2 NOTE: U8900 DQ0-7 MUST connect to GPU IN 75B5 73D5 IN 75B5 73D5 IN 75B5 73D5 IN 75B5 73D5 IN 75B5 73D5 IN B 75B5 73D5 IN 75B5 73D5 IN 75B5 73D5 IN 75B5 73D5 IN 75B5 73D5 IN 75B5 73D5 IN 73B5 IN 73B5 IN 73B5 IN 73B5 73B5 IN IN 73B5 IN 73B5 IN 121 R8945 60.4 1% 1/16W MF-LF 402 2 1% 1/16W MF-LF 402 2 1 121 75A5 73A1 76A8 76A5 IN 73C5 73C5 73C5 73C5 73C5 73C5 A OUT OUT OUT OUT IN IN 73C5 IN 73C5 IN 75A5 73D5 IN 75A5 73D5 75A5 73D5 IN IN K9 A0 U8900 DM0 E3 A1 FBGA DM1 E10 K10 A2 A3 (1 OF 2) DM2 DM3 N10 DQ0 B2 73D7 H2 A4 A5 K3 A6 L4 A7 A8/AP K4 K2 M4 B11 J11 CK CK* 73D7 DQ9 B10 73D7 DQ10 C11 F4 CS* 73D7 DQ11 C10 H4 73D7 DQ12 73D7 DQ13 E11 F9 WE* CAS* H10 RAS* 73D7 DQ14 F11 73D7 DQ15 73C7 DQ16 G10 A9 ZQ MF V4 SEN 73D7 DQ17 L10 RESET 73C7 DQ18 N11 73D7 DQ19 M10 73C7 DQ20 73C7 DQ21 R11 P3 R8948 243 1% 1/16W MF-LF 402 R8949 100 2 2 RDQS0 RDQS1 RDQS2 RDQS3 F10 M11 R10 73C7 DQ22 T11 T10 D2 WDQS0 73C7 DQ23 DQ24 D11 WDQS1 DQ25 L3 73C7 P11 DQ26 DQ27 N2 73C7 P2 WDQS2 WDQS3 R2 73C7 BA0 DQ28 G9 DQ29 DQ30 R3 73C7 DQ31 T3 73C7 G4 NC NC F2 73D7 F3 73D7 G3 73D7 P10 1 DQ6 DQ7 D10 1 DQ4 DQ5 E2 73D7 73D7 DQ8 D3 FB_A_BA<0> FB_A_BA<1> FB_A_BA<2> C3 73D7 CKE V9 FB_A_WDQS<0> FB_A_WDQS<1> FB_A_WDQS<2> FB_A_WDQS<3> C2 73D7 H9 A4 FB_A_RDQS<0> FB_A_RDQS<1> FB_A_RDQS<2> FB_A_RDQS<3> DQ3 B3 73D7 L9 J10 FB_DRAM_RST A9 DQ1 DQ2 N3 A10 A11 K11 FB_A0_ZQ FB_A0_MF FB_A0_SEN 5% 1/16W MF-LF 402 2 H11 M9 BA1 H3 BA2 J2 RFU1 J3 RFU2 R8991 1K CRITICAL OMIT 1% 1/16W MF-LF 402 2 FB_A_CKE<0> FB_A_CLK_P<0> FB_A_CLK_N<0> FB_A_CS_L<0> FB_A_WE_L<0> FB_A_CAS_L<0> FB_A_RAS_L<0> 2 1 R8947 FB_A_MA<0> FB_A_MA<1> FB_A_MA<2> FB_A_MA<3> FB_A_MA<4> FB_A_MA<5> FB_A_MA<6> FB_A_MA<7> FB_A_MA<8> FB_A_MA<9> FB_A_MA<10> FB_A_MA<11> 1% 1/16W MF-LF 402 M2 73C7 M3 73C7 T2 73C7 FB_A_DQM_L<0> FB_A_DQM_L<1> FB_A_DQM_L<2> 73C5 FB_A_DQM_L<3> 73D5 IN 75B8 73D5 IN 73C5 IN 75B8 73D5 IN IN 75B8 73D5 IN IN 75B8 73D5 IN 75B8 73D5 IN 73C5 FB_A_DQ<0> FB_A_DQ<1> FB_A_DQ<2> FB_A_DQ<3> FB_A_DQ<4> FB_A_DQ<5> FB_A_DQ<6> FB_A_DQ<7> FB_A_DQ<8> FB_A_DQ<9> FB_A_DQ<10> FB_A_DQ<11> FB_A_DQ<15> FB_A_DQ<14> FB_A_DQ<12> FB_A_DQ<13> FB_A_DQ<19> FB_A_DQ<16> FB_A_DQ<18> FB_A_DQ<17> FB_A_DQ<23> FB_A_DQ<21> FB_A_DQ<20> FB_A_DQ<22> FB_A_DQ<24> FB_A_DQ<25> FB_A_DQ<26> FB_A_DQ<27> FB_A_DQ<29> FB_A_DQ<30> FB_A_DQ<28> FB_A_DQ<31> IO IO IO IO IO IO IO 75B8 73D5 IN 75B8 73D5 IN 75B8 73D5 IN 75B8 73D5 IN 75B8 73D5 IN 75B8 73D5 IN 75B8 73D5 IN 2 1 R8996 1 60.4 1% 1/16W MF-LF 402 2 1 R8993 121 2 R8995 1 60.4 1% 1/16W MF-LF 402 2 1% 1/16W MF-LF 402 2 R8997 121 2 CRITICAL OMIT 1% 1/16W MF-LF 402 FB_A_MA<0> FB_A_MA<1> FB_A_MA<2> FB_A_MA<3> FB_A_MA<4> FB_A_MA<5> FB_A_MA<6> FB_A_MA<7> FB_A_MA<8> FB_A_MA<9> FB_A_MA<10> FB_A_MA<11> A0 U8950 DM0 E3 73C5 IN A1 FBGA DM1 E10 73C5 IN K10 A2 A3 (1 OF 2) DM2 DM3 N10 73C5 DQ0 B2 73C7 DQ1 DQ2 B3 73C7 DQ3 C3 73C7 DQ4 DQ5 E2 73C7 DQ6 F2 73C7 M9 H2 A4 A5 K3 A6 L4 A7 A8/AP K4 K2 M4 A9 IO IN IO 73B5 IN IO 73B5 IN IO 73B5 IO 73B5 IN IO 73B5 IN IO 73B5 IN IN FB_A_CKE<1> FB_A_CLK_P<1> FB_A_CLK_N<1> FB_A_CS_L<1> FB_A_WE_L<1> FB_A_CAS_L<1> FB_A_RAS_L<1> IO IO IO IO IO IO IO IO 76A5 75A8 73A1 76A8 IN 73C5 73C5 73C5 73C5 OUT DQ7 G3 73C7 CKE 73C7 DQ8 B11 J11 CK CK* 73C7 DQ9 B10 73C7 DQ10 C11 F4 CS* 73C7 DQ11 C10 H4 73B7 DQ12 73B7 DQ13 E11 F9 WE* CAS* H10 RAS* 73B7 DQ14 F11 73B7 DQ15 73B7 DQ16 G10 A9 ZQ MF V4 SEN 73B7 DQ17 L10 RESET 73B7 DQ18 N11 73B7 DQ19 M10 73B7 DQ20 73B7 DQ21 R11 OUT OUT 73B7 DQ22 T11 OUT T10 V9 FB_A_RDQS<4> FB_A_RDQS<5> FB_A_RDQS<6> FB_A_RDQS<7> D3 D10 P10 P3 RDQS0 RDQS1 RDQS2 RDQS3 73C5 IO 73C5 IO 73C5 IN IO 73C5 IN 75A8 73D5 IN IO IO IO 75A8 73D5 75A8 73D5 IN IN IN IN FB_A_WDQS<4> FB_A_WDQS<5> FB_A_WDQS<6> FB_A_WDQS<7> FB_A_BA<0> FB_A_BA<1> FB_A_BA<2> R8998 243 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R8999 100 2 2 NC NC R10 WDQS0 D11 WDQS1 DQ25 L3 73B7 P11 DQ26 DQ27 N2 73B7 P2 WDQS2 WDQS3 R2 73B7 BA0 DQ28 G9 DQ29 DQ30 R3 73B7 DQ31 T3 73B7 BA1 H3 BA2 J2 RFU1 J3 RFU2 IO 1 M11 D2 G4 1 F10 73B7 DQ23 DQ24 IO IO F3 73C7 H9 A4 FB_DRAM_RST C2 73C7 L9 J10 FB_A1_ZQ FB_A1_MF FB_A1_SEN N3 A10 A11 K11 IO 73B5 FB_A_DQM_L<4> FB_A_DQM_L<5> FB_A_DQM_L<6> 73C5 FB_A_DQM_L<7> K9 H11 K4J52324QC-BC20 5% 1/16W MF-LF 402 2 1 R8943 GDDR3 vendor/device identification scheme. 2 121 1% 1/16W MF-LF 402 MFHIGH 1K 1 2 R8994 1 121 1% 1/16W MF-LF 402 16MX32-GDDR3-500MHZ R8941 2 R8992 1 121 MFHIGH 2 R8990 1 how these bits are mapped for GPU to support K4J52324QC-BC20 1% 1/16W MF-LF 402 MFHIGH 60.4 1% 1/16W MF-LF 402 16MX32-GDDR3-500MHZ 121 1% 1/16W MF-LF 402 MFHIGH 121 1% 1/16W MF-LF 402 Bits can be swapped within byte-lane, but software must know R8946 1 121 1 75B5 73D5 R8944 1 MFHIGH R8942 1 MFHIGH DQA0-7 or DQA8-15. R8940 1 M2 73B7 M3 73B7 T2 73B7 FB_A_DQ<32> FB_A_DQ<34> FB_A_DQ<33> FB_A_DQ<35> FB_A_DQ<36> FB_A_DQ<37> FB_A_DQ<38> FB_A_DQ<39> FB_A_DQ<40> FB_A_DQ<41> FB_A_DQ<42> FB_A_DQ<43> FB_A_DQ<46> FB_A_DQ<44> FB_A_DQ<47> FB_A_DQ<45> FB_A_DQ<48> FB_A_DQ<49> FB_A_DQ<50> FB_A_DQ<51> FB_A_DQ<52> FB_A_DQ<55> FB_A_DQ<54> FB_A_DQ<53> FB_A_DQ<60> FB_A_DQ<59> FB_A_DQ<61> FB_A_DQ<57> FB_A_DQ<62> FB_A_DQ<56> FB_A_DQ<63> FB_A_DQ<58> IN IN IO B IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GDDR3 Frame Buffer A IO IO SYNC_MASTER=(MASTER) IO IO SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY IO THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING IO IO I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 5% 1/16W MF-LF 402 SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 75 1 87 A C9002 1 C9003 C9004 1 0.1uF 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 2 2 F1 F12 L9010 D PP1V8_S0_FB_B0_VDDA0 2 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 L9015 1 FERR-220-OHM 1 PP1V8_S0_FB_B0_VDDA1 2 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 2 C9010 C9015 1 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 2 U9000.J1 VDD5 V2 VDD6 VDD7 22UF 20% 6.3V CERM 805 2 2 C9021 1 C9022 1 1 C9024 1 C9025 1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 2 2 2 2 R9032 2.37K 2.37K 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 2 C R9031 R9033 5.49K R9040 1 FERR-220-OHM 1 VDDQ3 VDDQ4 VSSQ3 VSSQ4 B12 VDDQ5 VSSQ5 D4 VDDQ6 VDDQ7 VSSQ6 VSSQ7 D9 E9 VDDQ8 VSSQ8 G2 10% 16V X5R 402 VDDQ9 VDDQ10 VSSQ9 VSSQ10 G11 J4 J9 VDDQ11 VSSQ11 L11 1 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 75D8 75D5 73B8 73B5 67B8 67B6 64A4 5D4 IN 73A8 73A5 72B8 82D7 76D8 76D5 1 1 22UF 20% 6.3V CERM 805 2 2 C9071 1 C9072 1 IN 76B5 73D1 IN 76B5 73D1 IN 76B5 73D1 IN 76B5 73D1 IN 76B5 73D1 IN 76B5 73D1 IN 76B5 73D1 IN 73B1 IN 73B1 IN 73B1 IN 73B1 73B1 IN IN 73B1 IN 73B1 IN 73C1 73C1 73C1 73C1 73C1 73C1 OUT OUT OUT OUT IN IN 73C1 IN 73C1 IN 76A5 73D1 IN 76A5 73D1 76A5 73D1 IN IN 10% 16V X5R 402 1 2 121 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 10% 16V X5R 402 2 2 FB_B_CKE<0> FB_B_CLK_P<0> FB_B_CLK_N<0> FB_B_CS_L<0> FB_B_WE_L<0> FB_B_CAS_L<0> FB_B_RAS_L<0> 2 VDDQ3 VDDQ4 VSSQ3 VSSQ4 B12 C9 C12 VDDQ5 VSSQ5 D4 E1 VDDQ6 VDDQ7 VSSQ6 VSSQ7 D9 E4 E9 VDDQ8 VSSQ8 G2 VDDQ17 VDDQ18 VSSQ17 VSSQ18 T4 R9080 T9 2.37K 2.37K R12 VDDQ19 VSSQ19 T12 V1 VDDQ20 VDDQ21 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 H1 VREF0 H12 VREF1 R9082 2 FB_B1_VREF0 FB_B1_VREF1 D12 VSSQ9 VSSQ10 G11 J9 VDDQ11 VSSQ11 L11 N1 VDDQ12 VDDQ13 VSSQ12 VSSQ13 P1 VDDQ14 VDDQ15 VSSQ14 VSSQ15 P9 N12 R1 VDDQ16 VSSQ16 T1 R4 VDDQ17 VDDQ18 VSSQ17 VSSQ18 T4 R9 R12 VDDQ19 VSSQ19 T12 V1 VDDQ20 VDDQ21 V12 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm D1 VDDQ9 VDDQ10 2 H1 VREF0 H12 VREF1 D B9 J4 T1 R9 J12 B4 VSSQ16 1 J1 VSSA1 VSSQ1 VSSQ2 VDDQ16 1 VSSA0 BOM options provided by this page: (NONE) V10 VDDQ1 VDDQ2 R1 P12 R9081 1 R9083 5.49K 1 1% 1/16W MF-LF 402 2 R9092 1 DM0 E3 73C1 IN 76B8 73D1 IN FBGA DM1 E10 73C1 IN 76B8 73D1 IN DM2 DM3 N10 73C1 IN 76B8 73D1 IN IN 76B8 73D1 IN 76B8 73D1 DQ0 B2 73D3 IN H2 K3 A6 L4 A7 A8/AP DQ3 B3 73D3 C2 73D3 C3 73D3 DQ4 DQ5 E2 73D3 DQ6 F2 73D3 F3 73D3 L9 DQ7 G3 73D3 H9 CKE 73C3 DQ8 B11 J11 CK CK* 73D3 DQ9 B10 73C3 DQ10 C11 F4 CS* 73D3 DQ11 C10 H4 73C3 DQ12 73C3 DQ13 E11 F9 WE* CAS* H10 RAS* 73C3 DQ14 F11 73C3 DQ15 73C3 DQ16 G10 A9 ZQ MF V4 SEN 73C3 DQ17 L10 RESET 73C3 DQ18 N11 73C3 DQ19 M10 73C3 DQ20 73C3 DQ21 R11 P10 P3 RDQS0 RDQS1 RDQS2 RDQS3 F10 M11 R10 73C3 DQ22 T11 T10 D2 WDQS0 73C3 DQ23 DQ24 D11 WDQS1 DQ25 L3 73D3 P11 DQ26 DQ27 N2 73D3 P2 WDQS2 WDQS3 R2 73D3 BA0 DQ28 G9 DQ29 DQ30 R3 73D3 DQ31 T3 73D3 G4 NC NC A9 DQ1 DQ2 N3 A10 A11 D10 FB_B_BA<0> FB_B_BA<1> FB_B_BA<2> FB_B_DQM_L<1> FB_B_DQM_L<2> FB_B_DQM_L<3> 73D1 FB_B_DQM_L<0> U9000 (1 OF 2) D3 FB_B_WDQS<1> FB_B_WDQS<2> FB_B_WDQS<3> FB_B_WDQS<0> 5% 1/16W MF-LF 402 2 A2 A3 A4 A5 BA1 H3 BA2 J2 RFU1 J3 RFU2 R9091 1K A1 V9 FB_B_RDQS<1> FB_B_RDQS<2> FB_B_RDQS<3> FB_B_RDQS<0> 2 M2 73D3 M3 73D3 T2 73D3 FB_B_DQ<15> FB_B_DQ<12> FB_B_DQ<14> FB_B_DQ<13> FB_B_DQ<8> FB_B_DQ<9> FB_B_DQ<11> FB_B_DQ<10> FB_B_DQ<18> FB_B_DQ<17> FB_B_DQ<19> FB_B_DQ<16> FB_B_DQ<20> FB_B_DQ<22> FB_B_DQ<23> FB_B_DQ<21> FB_B_DQ<29> FB_B_DQ<30> FB_B_DQ<28> FB_B_DQ<31> FB_B_DQ<27> FB_B_DQ<24> FB_B_DQ<26> FB_B_DQ<25> FB_B_DQ<1> FB_B_DQ<6> FB_B_DQ<0> FB_B_DQ<5> FB_B_DQ<3> FB_B_DQ<7> FB_B_DQ<2> FB_B_DQ<4> IO IO IO IO IO IO IO 76B8 73D1 IN 76B8 73D1 IN 76B8 73D1 IN 76B8 73D1 IN 76B8 73D1 IN 76B8 73D1 IN 76B8 73D1 IN 1 5.49K 1% 1/16W MF-LF 402 2 A0 A4 FB_DRAM_RST 2 2 V3 A12 VSSQ14 VSSQ15 K9 J10 2 2 L12 VSS6 VSS7 B1 VDDQ14 VDDQ15 K10 M4 100 C9076 VSS5 Signal aliases required by this page: (NONE) L1 VSSQ0 N12 H11 K11 1% 1/16W MF-LF 402 1 G12 Power aliases required by this page: - =PP1V8_S0_FB_VDD - =PP1V8_S0_FB_VDDQ G1 VDDQ0 N9 CRITICAL OMIT 1% 1/16W MF-LF 402 2 K2 243 C9075 VSS3 VSS4 A1 N4 1 K4 R9049 1 A10 VDDA0 P9 R9047 M9 R9048 C9074 A3 VSS1 VSS2 VDDA1 P4 2 FB_B_MA<0> FB_B_MA<1> FB_B_MA<2> FB_B_MA<3> FB_B_MA<4> FB_B_MA<5> FB_B_MA<6> FB_B_MA<7> FB_B_MA<8> FB_B_MA<9> FB_B_MA<10> FB_B_MA<11> 1 1 0.1uF 2 1 C9081 1 L2 P4 P12 T9 C C9083 0.1uF 0.1uF 10% 16V X5R 402 10% 16V X5R 402 2 R9094 1 1% 1/16W MF-LF 402 1 C9073 FBGA (2 OF 2) VSS0 K1 P1 R9090 1 FB_B0_ZQ FB_B0_MF FB_B0_SEN 75A5 73A1 76A5 75A8 IN 0.1uF 10% 16V X5R 402 K4J52324QC-BC20 76B5 73D1 0.1uF MFHIGH IN U9000.J12 U9050 K12 C4 10% 16V X5R 402 121 1% 1/16W MF-LF 402 2 VDD6 VDD7 C1 0.1uF 1% 1/16W MF-LF 402 60.4 10% 16V X5R 402 10% 16V X5R 402 121 1% 1/16W MF-LF 402 2 0.1uF 2 0.1uF 1% 1/16W MF-LF 402 121 2 10% 16V X5R 402 121 R9045 VDD5 V2 VSSQ12 VSSQ13 R9046 1 1 C9065 1 10% 16V X5R 402 0.1uF 1% 1/16W MF-LF 402 R9043 M12 E12 C9070 L2 60.4 1 M1 VDD3 VDD4 PP1V8_D3C 1% 1/16W MF-LF 402 R9041 F1 F12 Connect to designated pin, then GND C9033 16MX32-GDDR3-500MHZ IN 76B5 73D1 1 MFHIGH IN 76B5 73D1 C9031 2 2 C9060 U9000.J1 121 2 2 0.1uF PP1V8_S0_FB_B1_VDDA1 2 1% 1/16W MF-LF 402 2 2 VDD1 VDD2 VDDQ12 VDDQ13 MFHIGH IN 76B5 73D1 1 R9044 1 2 L9065 121 5% 1/16W MF-LF 402 2 A 0.1uF 10% 16V X5R 402 PP1V8_S0_FB_B1_VDDA0 1% 1/16W MF-LF 402 1K B D12 C9054 1 0.1uF D1 E4 C9053 10% 16V X5R 402 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.8V 0402 121 1 76B5 73D1 1 1% 1/16W MF-LF 402 2 R9042 1 1 0.1uF VDD0 1 Page Notes MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 5.49K 1% 1/16W MF-LF 402 2 C9052 10% 16V X5R 402 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1 1 0.1uF A2 A11 V11 2 B9 V12 FB_B0_VREF1 J12 B4 2 FB_B0_VREF0 VSSA1 VSSQ1 VSSQ2 R4 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1 VDDQ1 VDDQ2 N9 R9030 J1 A12 N1 1 FERR-220-OHM VSSA0 2 2 C9051 L9060 B1 N4 1 V10 L1 VSSQ0 C9 C9026 V3 20% 6.3V CERM 805 VDDQ0 C12 C9023 L12 VSS6 VSS7 1 1 22UF A1 E12 1 VSS5 C9050 VDDA1 PP1V8_D3C 1 G12 G1 K12 E1 C9020 VSS3 VSS4 VDDA0 C4 U9000.J12 FBGA (2 OF 2) A10 K1 C1 Connect to designated pin, then GND 75D8 75D5 73B8 73B5 67B8 67B6 64A4 5D4 IN 73A8 73A5 72B8 82D7 76D8 76D5 M12 V11 FERR-220-OHM 1 M1 VDD3 VDD4 A3 VSS1 VSS2 2 R9096 1 60.4 1% 1/16W MF-LF 402 2 1 R9093 121 2 R9095 1 60.4 1% 1/16W MF-LF 402 2 1% 1/16W MF-LF 402 2 R9097 121 2 CRITICAL OMIT 1% 1/16W MF-LF 402 FB_B_MA<0> FB_B_MA<1> FB_B_MA<2> FB_B_MA<3> FB_B_MA<4> FB_B_MA<5> FB_B_MA<6> FB_B_MA<7> FB_B_MA<8> FB_B_MA<9> FB_B_MA<10> FB_B_MA<11> A0 U9050 DM0 E3 73C1 IN A1 FBGA DM1 E10 73C1 IN K10 A2 A3 (1 OF 2) DM2 DM3 N10 73C1 DQ0 B2 73B3 DQ1 DQ2 B3 73B3 DQ3 C3 73B3 DQ4 DQ5 E2 73B3 DQ6 F2 73B3 M9 H2 A4 A5 K3 A6 L4 A7 A8/AP K4 K2 M4 A9 IO IN IO 73B1 IN IO 73B1 IN IO 73B1 IO 73B1 IN IO 73B1 IN IO 73B1 IN IN FB_B_CKE<1> FB_B_CLK_P<1> FB_B_CLK_N<1> FB_B_CS_L<1> FB_B_WE_L<1> FB_B_CAS_L<1> FB_B_RAS_L<1> IO IO IO IO IO IO IO IO 75A8 75A5 73A1 76A8 IN 73C1 73C1 73C1 73C1 OUT DQ7 G3 73B3 CKE 73B3 DQ8 B11 J11 CK CK* 73B3 DQ9 B10 73B3 DQ10 C11 F4 CS* 73B3 DQ11 C10 H4 73C3 DQ12 73C3 DQ13 E11 F9 WE* CAS* H10 RAS* 73C3 DQ14 F11 73C3 DQ15 73C3 DQ16 G10 A9 ZQ MF V4 SEN 73C3 DQ17 L10 RESET 73C3 DQ18 N11 73C3 DQ19 M10 73C3 DQ20 73C3 DQ21 R11 OUT OUT 73C3 DQ22 T11 OUT T10 V9 FB_B_RDQS<6> FB_B_RDQS<5> FB_B_RDQS<4> FB_B_RDQS<7> D3 D10 P10 P3 RDQS0 RDQS1 RDQS2 RDQS3 73C1 IO 73C1 IO 73C1 IN IO 73C1 IN 76A8 73D1 IN IO IO IO 76A8 73D1 76A8 73D1 IN IN IN IN FB_B_WDQS<6> FB_B_WDQS<5> FB_B_WDQS<4> FB_B_WDQS<7> FB_B_BA<0> FB_B_BA<1> FB_B_BA<2> R9098 243 5% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R9099 100 2 2 NC NC R10 WDQS0 D11 WDQS1 DQ25 L3 73B3 P11 DQ26 DQ27 N2 73B3 P2 WDQS2 WDQS3 R2 73B3 BA0 DQ28 G9 DQ29 DQ30 R3 73B3 DQ31 T3 73B3 BA1 H3 BA2 J2 RFU1 J3 RFU2 IO 1 M11 D2 G4 1 F10 73C3 DQ23 DQ24 IO IO F3 73B3 H9 A4 FB_DRAM_RST C2 73B3 L9 J10 FB_B1_ZQ FB_B1_MF FB_B1_SEN N3 A10 A11 K11 IO 73B1 FB_B_DQM_L<6> FB_B_DQM_L<5> FB_B_DQM_L<4> 73C1 FB_B_DQM_L<7> K9 H11 K4J52324QC-BC20 1 0.1uF VSS0 MFHIGH 2 2 C9001 U9000 16MX32-GDDR3-500MHZ 20% 6.3V CERM 805 VDD1 VDD2 MFHIGH 1 1 22UF VDD0 K4J52324QC-BC20 C9000 A2 A11 CRITICAL OMIT PP1V8_D3C K4J52324QC-BC20 73B8 73B5 73A8 73A5 72B8 67B8 67B6 64A4 5D4 IN 82D7 76D8 76D5 75D8 75D5 16MX32-GDDR3-500MHZ CRITICAL OMIT PP1V8_D3C 2 3 4 5 16MX32-GDDR3-500MHZ 75D8 75D5 73B8 73B5 67B8 67B6 64A4 5D4 IN 73A8 73A5 72B8 82D7 76D8 76D5 6 7 MFHIGH 8 M2 73B3 M3 73B3 T2 73B3 FB_B_DQ<54> FB_B_DQ<53> FB_B_DQ<52> FB_B_DQ<55> FB_B_DQ<50> FB_B_DQ<48> FB_B_DQ<49> FB_B_DQ<51> FB_B_DQ<44> FB_B_DQ<47> FB_B_DQ<45> FB_B_DQ<46> FB_B_DQ<43> FB_B_DQ<41> FB_B_DQ<42> FB_B_DQ<40> FB_B_DQ<37> FB_B_DQ<32> FB_B_DQ<39> FB_B_DQ<34> FB_B_DQ<36> FB_B_DQ<35> FB_B_DQ<38> FB_B_DQ<33> FB_B_DQ<63> FB_B_DQ<61> FB_B_DQ<62> FB_B_DQ<60> FB_B_DQ<56> FB_B_DQ<59> FB_B_DQ<58> FB_B_DQ<57> IN IN IO B IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GDDR3 Frame Buffer B IO IO SYNC_MASTER=(MASTER) IO IO SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY IO THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING IO IO I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 5% 1/16W MF-LF 402 SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 76 1 87 A 8 Page Notes 6 7 2 3 4 5 Power aliases required by this page: - =PP3V3_GPU_GPIOS - =PP2V5_PVDD - =PP1V8_GPU_LVDS_PLL 77C6 77B7 74D6 74B2 71C4 71B8 71A4 67A5 67A3 65C7 82D7 82A7 80D5 80B2 Signal aliases required by this page: - =I2C_GPU_TMDS_SDA - I2C data line for external TMDS transmitters - =I2C_GPU_TMDS_SCL - I2C clock line for external TMDS transmitters PP3V3_D3C OMIT 1 U8400 BGA (6 OF 7) BOM options provided by this page: (NONE) 74B8 74B7 74B8 74B7 74B8 74B7 74B8 74B7 74B8 74B7 74B8 74B7 74B8 74B6 74B8 74B7 74B8 74B7 74B8 74B6 74B8 74B7 74B8 74B7 74B8 74B7 74B8 74B7 74B8 74B7 74B8 74B7 74B8 74B7 77D2 77B7 74D6 74B2 71C4 71B8 71A4 67A5 67A3 65C7 82D7 82A7 80D5 80B2 NC_GPU_GPIO_18 NC_GPU_GPIO_19 NC_GPU_GPIO_20 NC_GPU_GPIO_21 NC_GPU_GPIO_22 NC_GPU_GPIO_23 GPU_MEM_256M NC_GPU_GPIO_25 NC_GPU_GPIO_26 GPU_MEMID NC_GPU_GPIO_28 NC_GPU_GPIO_29 NC_GPU_GPIO_30 NC_GPU_GPIO_31 NC_GPU_GPIO_32 NC_GPU_GPIO_33 NC_GPU_GPIO_34 AE13 AF13 AF9 AG7 AE10 AE9 AF7 AF8 AH6 AF10 AG10 AH9 AJ8 AH8 AG9 AH7 AG8 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 GPIO_32 GPIO_33 GPIO_34 PP3V3_D3C Typically <50mA AA9 AB9 C9100 1 1 22UF 20% 6.3V CERM 805 C9101 1 1uF 2 2 C9102 1 1uF 10% 6.3V CERM 402 2 10% 6.3V CERM 402 2 C9103 AB10 1uF AC19 10% 6.3V CERM 402 AC20 R9190 499 M56P GENERAL PURPOSE I/O D 1 2 VREFG AC8 ATI_VREFG GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7_BLON GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 AD4 GPU_GPIO_0 GPU_GPIO_1 GPU_GPIO_2 GPU_GPIO_3 GPU_GPIO_4 GPU_GPIO_5 GPU_GPIO_6 GPU_BLON GPU_GPIO_8 GPU_GPIO_9 TP_GPU_GPIO_10 GPU_GPIO_11 GPU_GPIO_12 GPU_GPIO_13 NC_GPU_GPIO_14 GPU_VCORE_LOW GPU_CLK27MSS_IN NC_GPU_GPIO_17 AD2 AD1 AD3 AC1 AC2 AC3 AB2 AC6 AC5 AC4 AB3 AB4 AB5 AD5 AB8 AA8 AB7 GENERICA GENERICB GENERICC GENERICD AK22 PANEL DIGON CONTROL VARY_BL AE11 VDDR3 (3.3V) AD18 AD19 NC_GPU_GENERICA NC_GPU_GENERICB NC_GPU_GENERICC GPU_GENERICD AF23 AE23 AD23 1 74D8 C9191 74C8 0.1uF 74C8 74C8 10% 16V X5R 402 1 1% 1/16W MF-LF 402 D R9191 499 2 2 1% 1/16W MF-LF 402 74C8 74C8 74C8 74C5 74C8 82A4 74C8 74C8 74C5 74C8 74C8 74C8 74C8 74C5 74C8 71B4 74C5 74C8 34B2 34B4 74C5 74C8 74C5 74C8 74C1 74C2 74C1 74C2 74C1 74C2 71A7 AD20 C 82D7 78C8 77C6 77A8 67A8 67A6 63C1 5D4 PP2V5_D3C 70mA total for VDD25 K22 GPU_DIGON GPU_VARY_BL AD12 C 82A4 82B6 82A4 L10 C9110 1 1 2 2 22UF 1uF 20% 6.3V CERM 805 1 1 22UF L9120 2 2 MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V C9120 1 1 22UF L9125 AC18 2 NC0 AB6 NC NC_DVOVMODE_0 NC_DVOVMODE_1 AK4 NC NC DVPCLK AG1 NC_ATI_DVPCLK DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 AF2 NC_ATI_DVPCNTL<0> NC_ATI_DVPCNTL<1> NC_ATI_DVPCNTL<2> 10% 6.3V CERM 402 DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 AG2 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 AE6 C9117 1uF 2 10% 6.3V CERM 402 C9121 1 2 2 10% 6.3V CERM 402 C9122 0.1uF 2 AJ5 10% 16V X5R 402 AK5 AL5 VDDR4 (1.8V/3.3V) AM5 PP1V8R3V3_S0_GPU_VDDR5_F MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 0402 AE2 AE3 C9125 1 1 2 2 22UF 20% 6.3V CERM 805 L9130 C9126 1 1uF 10% 6.3V CERM 402 2 C9127 AE4 0.1uF AE5 10% 16V X5R 402 VDDR5 (1.8V/3.3V) 200-OHM-EMI PP1V2_D3C 1 2 PP1V2_S0_GPU_VDDPLL MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V 0402 20mA C9130 1 1 22UF 20% 6.3V CERM 805 C9131 1 1uF 2 2 10% 6.3V CERM 402 C9132 (PP2V5_S0_GPU_PVDD_F) 1uF 2 AC15 VDDPLL (1.2V) AJ14 PVDD PVSS AH14 10% 6.3V CERM 402 (PP1V0R1V2_S0_GPU_MPVDD) A6 A5 L9135 82D7 78C8 77C6 67A8 67A6 63C1 5D4 VDD25 (2.5V) AC16 Typically <50mA FERR-220-OHM 1 82D7 70C7 70A1 67D8 67D6 67C6 63B1 5D4 AC13 10% 16V X5R 402 MPVDD MPVSS (2.5V) (2.5V) FERR-220-OHM PP2V5_D3C 1 2 PP2V5_S0_GPU_PVDD_F MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.5V 0402 74C1 34B4 34B2 74C2 100mA 74C2 74C1 C9135 1 1 22UF 20% 6.3V CERM 805 C9136 1 1uF 2 2 10% 6.3V CERM 402 C9137 AM26 XTALIN XTALOUT AG14 PLLTEST AL26 NC 0.1uF 2 GPU_CLK27M NC_GPU_XTALOUT 10% 16V X5R 402 PLL & XTAL B 1 1uF 20% 6.3V CERM 805 PP3V3_D3C AA10 0.1uF PP1V8R3V3_S0_GPU_VDDR4_F 2 0402 77C6 77B7 74D6 74B2 71C4 71B8 71A4 67A5 67A3 65C7 82D7 82A7 80D5 80B2 77D2 C9112 Typically <50mA FERR-220-OHM 1 C9116 1uF 20% 6.3V CERM 805 PP3V3_D3C 2 PP2V5_D3C C9115 77C6 77B7 74D6 74B2 71C4 71B8 71A4 67A5 67A3 65C7 82D7 82A7 80D5 80B2 77D2 10% 6.3V CERM 402 VIP HOST / EXTERNAL TMDS 82D7 78C8 77C6 77A8 67A8 67A6 63C1 5D4 C9111 1 AL4 AF1 AF3 NC_ATI_DVPDATA<0> NC_ATI_DVPDATA<1> NC_ATI_DVPDATA<2> NC_ATI_DVPDATA<3> NC_ATI_DVPDATA<4> NC_ATI_DVPDATA<5> NC_ATI_DVPDATA<6> NC_ATI_DVPDATA<7> NC_ATI_DVPDATA<8> NC_ATI_DVPDATA<9> NC_ATI_DVPDATA<10> NC_ATI_DVPDATA<11> AG3 AH2 AH3 AJ2 AJ1 AK2 AK1 AK3 AL2 AL3 AM3 NC_ATI_DVPDATA<12> NC_ATI_DVPDATA<13> NC_ATI_DVPDATA<14> NC_ATI_DVPDATA<15> TP_ATI_DVPDATA<16> TP_ATI_DVPDATA<17> TP_ATI_DVPDATA<18> TP_ATI_DVPDATA<19> TP_ATI_DVPDATA<20> TP_ATI_DVPDATA<21> TP_ATI_DVPDATA<22> TP_ATI_DVPDATA<23> AF4 AF5 AG4 AJ3 AH4 AJ4 AG5 AH5 AF6 AE7 AG6 THERMAL DIODE DPLUS DMINUS AG12 AH12 ATI_TDIODE_P ATI_TDIODE_N ROM ROMCS* AC7 NC_ATI_ROMCS_L TEST TESTEN AG22 ATI_TESTEN 1 74B1 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 B 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 74B2 54B6 54B6 74C1 74C2 R9195 1K L9140 72D8 71C1 71B7 67A8 67A6 55C7 55A5 5B2 FERR-220-OHM PPVCORE_D3C_GPU 2 1 A 2 0402 PPVCORE_S0_GPU_MPVDD MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V 5% 1/16W MF-LF 402 ATI M56 GPIO/DVO/Misc 20mA SYNC_MASTER=(MASTER) C9140 1 1 22UF 20% 6.3V CERM 805 C9141 1 1uF 2 2 10% 6.3V CERM 402 C9142 2 SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY 0.1uF 10% 16V X5R 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 77 1 87 A 8 6 7 2 3 4 5 1 Page Notes Power aliases required by this page: - =PP2V5_S0_GPU - =PP1V8R2V5_S0_GPU_LVDDR Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE) D D L9300 FERR-220-OHM 2 5A4 PP2V5_S0_GPU_TPVDD 1 OMIT 20mA peak MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=2.5V 0402 U8400 C9300 L9305 1 1 C9301 1 1uF 1uF 20% 6.3V CERM 805 10% 6.3V CERM 402 10% 6.3V CERM 402 2 2 2 M56P C9302 22UF BGA (5 OF 7) AM8 AL8 FERR-220-OHM 1 2 5A4 PP2V5_S0_GPU_TXVDDR 150mA peak MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.5V 0402 AJ6 AK6 C9305 1 1 20% 6.3V CERM 805 L9310 C9306 1 1uF 22UF 2 2 10% 6.3V CERM 402 2 C9307 AL6 0.1uF AM6 10% 16V X5R 402 AK7 AK8 2 5A4 PP2V5_S0_GPU_AVDD 1 65mA peak MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.5V 0402 C9310 1 1 2 2 C9311 1 1uF 10% 6.3V CERM 402 C9312 0.1uF 2 AL25 10% 16V X5R 402 AM25 L9315 1 20mA peak C9316 1 C9317 22UF 1uF 0.1uF 20% 6.3V CERM 805 10% 6.3V CERM 402 10% 16V X5R 402 2 2 2 AK23 AVSSQ AM23 AL23 VDD1DI (2.5V) VSS1DI AL22 RSET 2 0402 1 AK25 AVSS L9320 130mA peak 78A8 ATI_RSET C9320 2 5A4 PP2V5_S0_GPU_A2VDD 1 MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.5V C9322 AL16 22UF 1uF 0.1uF 20% 6.3V CERM 805 10% 6.3V CERM 402 10% 16V X5R 402 AM16 1 2 1 2 C9321 1 2 A2VDD (2.5V) AL17 L9325 AM17 A2VSS FERR-220-OHM NC 2 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=2.5V AK13 0402 20mA peak C9325 1 1 20% 6.3V CERM 805 B C9326 1 1uF 22UF 2 2 10% 6.3V CERM 402 C9327 78A8 ATI_R2SET NC_A2VDDQ A2VSSQ AJ17 VDD2DI (2.5V) VSS2DI AK14 R2SET AE19 LPVDD (2.5V) LPVSS AJ16 L9330 0.1uF 2 AL14 87A4 80D8 AL10 79C7 AK10 AM11 AL11 AM12 AL12 1 2 5A4 PP2V5_S0_GPU_LPVDD 20mA peak MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=2.5V 0402 AE18 C9330 1 1 2 2 20% 6.3V CERM 805 C9331 1 1uF 22UF 10% 6.3V CERM 402 2 AK12 R G B 74C2 AK24 74C1 74C2 AM24 74C1 74C2 AL24 74C1 NC_GPU_VGA_R NC_GPU_VGA_G NC_GPU_VGA_B HSYNC VSYNC 74C2 AJ23 74C1 74C2 AJ22 74C1 TP_GPU_VGA_HSYNC TP_GPU_VGA_VSYNC AJ9 AK9 AJ11 AK11 AJ12 1uF AC21 10% 6.3V CERM 402 AC22 AD21 AD22 FERR-220-OHM AE20 2 5A4 PP2V5_S0_GPU_LVDDR 1 0402 MIN_LINE_WIDTH=0.35 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.5V 200mA peak AE21 LVDDR (2.5V) AE22 C9340 1 22UF 20% 6.3V CERM 805 80C3 R2 G2 B2 AK15 79D7 H2SYNC V2SYNC AF15 80C5 80C3 AM15 79D7 80C3 AL15 79D7 C9345 1 1 20% 6.3V CERM 805 1 1uF 22UF 2 C9341 2 2 10% 6.3V CERM 402 C9342 1 0.1uF 2 10% 16V X5R 402 C9346 1 0.1uF 2 10% 16V X5R 402 2 C9347 AF19 0.1uF AF20 10% 16V X5R 402 AF17 AF18 AG17 AG19 LVSSR AH17 AH19 AJ19 2 1 78B5 R9351 499 715 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 2 78B5 80A1 IN GPU_HPD AF11 HPD1 MONITOR IDENTIFICATION AK17 R9350 OUT OUT OUT OUT OUT OUT C OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT GPU_R2 GPU_G2 GPU_B2 OUT OUT OUT OUT AG15 80D5 Y C 74C2 AJ15 74C1 74B2 AJ13 74B1 NC_GPU_TV_Y NC_GPU_TV_C OUT COMP 74B2 AH15 74B1 NC_GPU_TV_COMP TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N TXCLK_LP TXCLK_LN TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N AF22 1 OUT GPU_H2SYNC GPU_V2SYNC AJ21 OUT DDC1CLK 80B1 DDC1DATA 80B1 82C3 82B8 79D7 6A2 6A1 LVDS_U_CLK_P LVDS_U_CLK_N AK21 AG18 Composite/S-Video VGA Component OUT Y C G R Y Pr OUT Comp B Pb AK20 AJ20 AG20 AH20 74B2 AH21 74B1 74B2 AG21 74B1 AM18 AL19 AL20 AM21 AL21 74B2 AJ18 74B1 74B2 AK18 74B1 74A2 DDC2CLK 74A2 DDC2DATA AG13 82A7 DDC3CLK 82A7 DDC3DATA AF12 AH13 AE12 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 82D8 82C3 79D7 6B2 6B1 AM20 AH22 LVDS_U_DATA_P<0> LVDS_U_DATA_N<0> LVDS_U_DATA_P<1> LVDS_U_DATA_N<1> LVDS_U_DATA_P<2> LVDS_U_DATA_N<2> NC_LVDS_U_DATAP<3> NC_LVDS_U_DATAN<3> LVDS_L_CLK_P LVDS_L_CLK_N AK19 AH23 OUT 82C8 82C3 79D7 6B2 6B1 AL18 B OUT 82C8 82C3 79D7 6B2 6B1 AH18 AF21 ATI_RSET ATI_R2SET OUT TMDS_DATA_P<0> TMDS_DATA_N<0> TMDS_DATA_P<1> TMDS_DATA_N<1> TMDS_DATA_P<2> TMDS_DATA_N<2> TMDS_DATA_P<3> TMDS_DATA_N<3> TMDS_DATA_P<4> TMDS_DATA_N<4> TMDS_DATA_P<5> TMDS_DATA_N<5> TXCLK_UP TXCLK_UN C9332 L9345 A 87A4 80B8 79C7 TMDS_CLK_P TMDS_CLK_N FERR-220-OHM 10% 16V X5R 402 LVDS 1 87B4 80B8 79C7 AL9 FERR-220-OHM 0402 PP2V5_S0_GPU_VDD2DI DAC (CRT) C9315 AVDD (2.5V) AM9 AJ24 FERR-220-OHM MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=2.5V TX0P TX0M TX1P TX1M TX2P TX2M TX3P TX3M TX4P TX4M TX5P TX5M AM7 20% 6.3V CERM 805 1 TXVSSR TXCP TXCM AL7 22UF PP2V5_S0_GPU_VDD1DI TXVDDR (2.5V) AJ7 FERR-220-OHM C TPVDD (2.5V) TPVSS INTEGRATED TMDS PP2V5_D3C DAC2 (TV/CRT2) 82D7 77C6 77A8 67A8 67A6 63C1 5D4 Sum of peak currents on this page: 605mA LVDS_L_DATA_P<0> LVDS_L_DATA_N<0> LVDS_L_DATA_P<1> LVDS_L_DATA_N<1> LVDS_L_DATA_P<2> LVDS_L_DATA_N<2> NC_LVDS_L_DATAP<3> NC_LVDS_L_DATAN<3> GPU_DDC_A_CLK GPU_DDC_A_DATA OUT OUT OUT OUT OUT OUT OUT OUT ATI M56 Video Interfaces IO IO SYNC_MASTER=(MASTER) GPU_DDC_B_CLK GPU_DDC_B_DATA IO GPU_DDC_C_CLK GPU_DDC_C_DATA IO SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY IO THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING IO I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 78 1 87 A 8 6 7 ELECTRICAL_CONSTRAINT_SET SPACING VGA VGA VGA VGA VGA LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS 1 LCD (LVDS) INTERFACE PHYSICAL VGA 2 3 4 5 NET_TYPE GPU_R2 GPU_G2 GPU_B2 78B3 80C3 67D5 67D3 67C3 66C5 65D8 65D2 24A5 23D8 23D4 23D1 23B7 23A7 22D8 22C6 11B5 5D4 65D1 65C8 63D8 56D4 26C5 25D2 25C8 25B6 24C3 24B3 PP3V3_S5 78B3 80C3 78B3 80C3 C9400 D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS TMDS TMDS TMDS TMDS TMDS TMDS TMDS TMDS TMDS TMDS TMDS TMDS LVDS_U_CLK_P LVDS_U_CLK_N LVDS_U_DATA_P<2..0> LVDS_U_DATA_N<2..0> 6A1 6A2 78B3 82B8 82C3 1 5% 1/16W MF-LF 402 6A1 6B1 6B2 78B3 82C3 82C8 10% 50V CERM 402 4 LCD_PWREN_L_RC 3 R9401 2 100K 6B1 6B2 78A3 82C3 82C8 5% 1/16W MF-LF 402 6B1 6B2 78A3 82C3 82D8 6B1 6B2 78A3 82C3 82D8 82B6 PP3V3_LCD_SW MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 5 LCD_PWREN_L C9401 79B2 79C2 82C1 82D1 D 79C2 82C1 82D1 20% 50V CERM 402 Q9400 Q9401 1 0.001uF TSOP-LF D SI3443DV 3 D SM 1 79B2 82C1 79D2 79C3 79B2 6A8 6A6 GND_CHASSIS_LVDS 2 79D3 6A8 6A6 79C3 79B2 GND_CHASSIS_LVDS CRITICAL 2N7002 82A2 79C2 82C1 LVDS_PANEL_EN 1 G SOT23-LF S C9420 67B3 67A3 66B6 66B5 66B1 65D6 65B3 62A6 61D8 49C7 49C4 49B5 40B6 36D6 34A8 33D8 33D3 33C7 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 25A4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 2 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 26B8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 54B5 52D3 82D5 82C6 82B3 82A4 79A8 71D2 67C5 67C3 R9494 1 79C2 82C1 20% 50V CERM 402 100K 79C2 82C1 5% 1/16W MF-LF 402 78C3 80B8 87B4 78C3 80C8 87B4 100K pull-ups are for no-panel case (development). Panel has 2K pull-ups 2 78C3 80A8 80B8 87A4 78C3 80A8 80B8 87A4 78C3 80C8 80D8 87A4 82A7 82A5 78C3 80C8 80D8 87A4 82A7 82A5 J9400 1 MSC-RB30-5-FA 0.001uF PP3V3_S0 79C2 82C1 TMDS_CLK_P TMDS_CLK_N TMDS_DATA_P<5..3> TMDS_DATA_N<5..3> TMDS_DATA_P<2..0> TMDS_DATA_N<2..0> 6 2 79B2 82C1 LVDS_L_CLK_CONN_P LVDS_L_CLK_CONN_N LVDS_L_DATA_CONN_P<2..0> LVDS_L_DATA_CONN_N<2..0> L9400 FERR-250-OHM S G 6B1 6B2 78A3 82C3 82D8 LVDS_U_CLK_CONN_P LVDS_U_CLK_CONN_N LVDS_U_DATA_CONN_P<2..0> LVDS_U_DATA_CONN_N<2..0> 2 100K 6A1 6B1 6B2 78B3 82B3 82C3 82C8 LVDS_L_CLK_P LVDS_L_CLK_N LVDS_L_DATA_P<2..0> LVDS_L_DATA_N<2..0> 0.0022uF R9400 1 6A1 6A2 78B3 82B8 82C3 F-RT-SM 34 2 1 R94101 100K 5% 1/16W MF-LF 402 2 1 R9411 100K 5% 1/16W MF-LF 2 402 PP3V3_LCD_CONN 2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 3 4 5 NC 6 13D5 LVDS_CONN_DDC_CLK 13D5 LVDS_CONN_DDC_DATA 7 8 LVDS_L_DATA_CONN_N<0> 79D7 LVDS_L_DATA_CONN_P<0> 82C1 79D7 C9410 1 82C1 9 0.001uF 20% 50V CERM 402 79D3 79D2 79B2 6A8 6A6 GND_CHASSIS_LVDS 10 2 82C1 79D7 82C1 79D7 11 LVDS_L_DATA_CONN_N<1> LVDS_L_DATA_CONN_P<1> 12 13 14 LVDS_L_DATA_CONN_N<2> 79D7 LVDS_L_DATA_CONN_P<2> 82C1 79D7 82C1 15 C 16 C 17 LVDS_L_CLK_CONN_N 79D7 LVDS_L_CLK_CONN_P 82C1 79D7 82C1 18 19 82D1 79D7 82D1 79D7 20 LVDS_U_DATA_CONN_N<0> LVDS_U_DATA_CONN_P<0> 21 22 82C1 79D7 82C1 79D7 23 LVDS_U_DATA_CONN_N<1> LVDS_U_DATA_CONN_P<1> 24 25 26 LVDS_U_DATA_CONN_N<2> 79D7 LVDS_U_DATA_CONN_P<2> 82D1 79D7 82C1 27 28 29 LVDS_U_CLK_CONN_N 79D7 LVDS_U_CLK_CONN_P 82C1 79D7 INVERTER INTERFACE 82C1 0.001uF 2 FERR-220-OHM-2A PPBUS_G3H 64A6 62D7 61D7 61D4 55D3 43D8 42B8 41C6 5C4 5A1 71D7 69C1 68D5 67C3 67C1 65D6 65B7 64D7 1 2 5B2 0603 1 FDG6332C_NL R9450 1 4 SC70-6 L9452 P-CHN 400-OHM-EMI D S 5% 1/16W MF-LF 402 B MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V G 2 C9450 2 2 J9450 SM04B-ACH 20% 6.3V X5R 603 1 NC 2 N-CHN 2 G Q9450 1 FDG6332C_NL SC70-6 4 C9452 NC 0.001uF L9454 2 400-OHM-EMI 1 1 100K 5% 1/16W MF-LF 402 3 PP5V_INVERTER_SW MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V S R9489 B 2 5B2 D 1 M-RT-SM 5 1 6 INVERTER_BKLTON GND_CHASSIS_LVDS CRITICAL 10UF 5 FP_PWR_EN_L 82A2 79D3 79D2 79C3 6A8 6A6 20% 50V CERM 402 SM-1 C9451 518S0289 0.001uF 1 PP5V_INVERTER_SW_F 3 100K 1 20% 50V CERM 402 PPBUS_S0_INVERTER MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V Q9450 PP5V_S0 33 C9421 CRITICAL L9450 81B3 58C4 57B5 55A8 53C4 36D6 31C5 25D8 5D4 5D2 80B5 80A1 71A6 67B3 67B1 67A1 66B5 62B1 61D7 58C7 30 2 20% 50V CERM 402 5B2 SM-1 6 518S0369 INVERTER_PWM GND_CHASSIS_INVERTER 2 1 C9454 1 CRITICAL 0.001uF 20% 50V CERM 402 67C5 67C3 67B3 67A3 66B6 66B5 66B1 65D6 65B3 54B5 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 62A6 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 82D5 82C6 82B3 82A4 79D3 71D2 PP3V3_S0 0603 GND_CHASSIS_INVERTER 5 1 PLT_RST_L INVERTER_PWM_UNBUF 2 MC74VHC1G08 SC70 U9453 A FERR-220-OHM-2A 45C5 6A6 5B2 45B5 6A8 79A5 26C1 26B1 26A4 22A6 14B7 6C7 6C6 5C4 82A4 26C3 82A2 L9455 2 4 INVERTER_PWM_F INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL Internal Display Connectors 2 SYNC_MASTER=M57_MLB_MG 3 C9453 20% 10V CERM 402 SYNC_DATE=08/08/2006 1 NOTICE OF PROPRIETARY PROPERTY 0.1uF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING 2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 79 1 87 A 8 6 7 2 3 4 5 1 NET_TYPE ELECTRICAL_CONSTRAINT_SET TMDS Filtering VGA SYNC BUFFERS Place termination components close to GPU, common mode chokes near connector. 77C6 77B7 74D6 74B2 71C4 71B8 71A4 67A5 67A3 65C7 82D7 82A7 80D5 80B2 77D2 87A4 79C7 78C3 PP3V3_D3C TMDS_DATA_N<0> CRITICAL TMDS_DATA_RL<0> R9762 1 VOLTAGE=0V 1 1% 1/16W MF-LF 402 L9743 D 5 L9700 182 NO_TEST=TRUE 1 SC70 90-OHM-100MA 1210-4SM1 U9750 SYM_VER-1 1 2 4 TMDS_DATA_F_N<0> 78B3 GPU_V2SYNC 3 TMDS_DATA_F_P<0> PHYSICAL TMDS TMDS TMDS TMDS TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDS_CLK_R_P TMDS_CLK_R_N 80B7 80C7 TMDS_CLK_F_P TMDS_CLK_F_N 80B5 80B6 87A4 80A5 80C6 87A4 TMDS_DATA_F_P<5..0> TMDS_DATA_F_N<5..0> 80A6 80B3 80B5 80B6 80C6 80D6 87A4 80A6 80B3 80B5 80B6 80C6 80D6 87A4 80A3 5% 1/16W MF-LF 402 1 D 0.1uF 80B5 80D1 87A4 20% 10V CERM 402 2 TMDS_DATA_N<1> VGA_VSYNC 2 2 C9750 2 87A4 79C7 78C3 1 3 0402 TMDS_DATA_P<0> 33 VGA_VSYNC_R 4 80B5 80D1 87A4 47nH 87A4 79C7 78C3 R9750 MC74VHC1G08 SPACING 2 ANALOG FILTERING TMDS_DATA_RL<1> VOLTAGE=0V 1 NO_TEST=TRUE CRITICAL R9766 1 L9701 182 1% 1/16W MF-LF 402 L9744 PLACE CLOSE TO CONNECTOR PLACE U9750 & U9751 CLOSE TO DVI CONNECTOR 90-OHM-100MA 1210-4SM1 77C6 77B7 74D6 74B2 71C4 71B8 71A4 67A5 67A3 65C7 82D7 82A7 80D5 80B2 77D2 SYM_VER-1 1 4 2 TMDS_DATA_F_N<1> CRITICAL PP3V3_D3C SM-220MHZ-LF 47nH 79D7 78B3 0402 5 2 3 TMDS_DATA_F_P<1> 1 80B3 80D1 87A4 U9751 78B3 1 VGA_HSYNC 2 80A5 1% 1/16W MF-LF 402 TMDS_DATA_RL<2> R9770 VOLTAGE=0V NO_TEST=TRUE L9702 1 L9745 TMDS_DATA_F_N<2> 2 3 TMDS_DATA_F_P<2> C R9741 80B3 80D1 87A4 79D7 78B3 80B3 80D1 87A4 R9772 1 2 0 2 80D1 SM-220MHZ-LF R9774 370-OHM SM 2 3 1 4 TMDS_CLK_F_N 1% 1/16W MF-LF 402 2 3 TMDS_CLK_F_P 1 2 81B3 80A1 79B8 71A6 53C4 36D6 31C5 25D8 5D4 5D2 67B3 67B1 67A1 66B5 62B1 61D7 58C7 58C4 57B5 55A8 PP5V_S0 1 80D1 TMDS_CLK_R_P 1 PP5V_S0_DDC_F VOLTAGE=5V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm 2 VOLTAGE=5V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm Isolation required for DVI power switch 3V LEVEL SHIFTERS D9710 33 80A2 6B8 6B6 6A6 TMDS_DATA_N<3> VOLTAGE=0V R9778 L9746 87A4 80D6 80D1 CRITICAL 1 SOD-123 1 2 PP5V_S0_DDC_PULLUPS R9710 1 31 87A4 80D6 80D1 90-OHM-100MA 1210-4SM1 17 TMDS_DATA_F_N<0> 1 TMDS_DATA_F_N<2> TMDS_DATA_F_N<1> TMDS_DATA_F_P<2> TMDS_DATA_F_P<1> 18 TMDS_DATA_F_P<0> 2 10 SYM_VER-1 19 1 2 4 TMDS_DATA_F_N<3> 80C6 80D1 87A4 80C6 80D1 87A4 3 TMDS_DATA_F_P<3> 1 TMDS_DATA_F_N<5> 20 TMDS_DATA_F_P<5> 21 4 TMDS_DATA_F_N<4> TMDS_DATA_F_N<3> TMDS_DATA_F_P<4> TMDS_DATA_F_P<3> DVI_DDC_CLK_R 12 80B3 80D1 87A4 2 87A4 80D1 80A6 5 13 TMDS_DATA_N<4> 6 22 14 87A4 80D1 80B6 TMDS_DATA_RL<4> VOLTAGE=0V NO_TEST=TRUE L9747 1 23 TMDS_CLK_F_P 80A6 80D1 87A4 2 80B6 80D1 87A4 80A6 80D1 87A4 2N7002DW-X-F 100 2 C9711 2 87A4 80D1 80C6 R9782 1 24 TMDS_CLK_F_N 1 2 C9713 16 C1 VGA_R 80C1 VGA_G 80C1 80D3 5% 50V CERM 402 CRITICAL 2 80C1 VGA_B 80C3 VGA_HSYNC C3 C5B L9704 90-OHM-100MA 1210-4SM1 0402 4 1 D 6 Q9714 S 1 GPU_DDC_A_DATA 1 2 5 100 2 G SOT-363 R9714 1 C2 3 DVI_HPD D S 4 1 S D 2 TMDS_DATA_P<4> TMDS_DATA_F_N<4> 34 80B3 80D1 87A4 32 3 TMDS_DATA_F_P<4> 80B3 80D1 87A4 80A3 6B8 6B6 GND_CHASSIS_DVI_TOP 514-0278 R9730 2 1 GPU_HPD GND_CHASSIS_DVI_TOP C9714 2 2 2 6 GND_CHASSIS_DVI_BOT GND 6A6 6B6 6B8 80B5 R9723 2 D S 1 80A1 22A6 5% 1/16W MF-LF 402 SB_DVI_HPD MAKE_BASE=TRUE 22A6 80A1 External Display Connector 2 SYNC_MASTER=M59_MLB SYNC_DATE=09/15/2006 6B6 6B8 80A5 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT SYM_VER-1 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 1 4 TMDS_DATA_F_N<5> 80B5 80D1 87A4 2 3 TMDS_DATA_F_P<5> 80B5 80D1 87A4 SIZE 2 APPLE COMPUTER INC. DRAWING NUMBER D SHT NONE 6 5 4 3 2 REV. 051-7164 SCALE 7 SB_DVI_HPD 20K 5% 1/16W MF-LF 402 CRITICAL TMDS_DATA_P<5> 78A5 81B3 67A1 67B1 67B3 57B5 58C4 58C7 5D2 5D4 25D8 31C5 36D6 53C4 55A8 61D7 62B1 66B5 71A6 79B8 80B5 R9715 1 1 90-OHM-100MA 1210-4SM1 0402 G SOT-363 5% 50V CERM 402 L9705 47nH 2 2N7002DW-X-F PLACE NEAR 3, 11 & 19 L9748 PP5V_S0 270K Q9715 100pF 1 5% 1/16W MF-LF 402 182 20% 50V CERM 603 5% 1/16W MF-LF 402 0 2 1% 1/16W MF-LF 402 1 0 R9731 R9786 1 0.01uF TMDS_DATA_N<5> 8 R9722 5% 1/16W MF-LF 2 402 6 GPU_HPD_BILAT 1 C9710 PLACE NEAR C5A & C5B 87A4 79C7 78C3 2N7002DW-X-F G 78A3 270K Q9714 SOT-363 5% 1/16W MF-LF 402 C5A C4 2 NO_TEST=TRUE 5% 1/16W MF-LF 2 402 G 2N7002DW-X-F SYM_VER-1 VOLTAGE=0V 2 182 1% 1/16W MF-LF 402 47nH TMDS_DATA_RL<5> B 10K SOT-363 DVI_DDC_DATA 78A3 R9721 5% 1/16W 26A2 26A1 GPU_SIGNAL_ENABLE 82A7 MF-LF 402 100pF VGA_VSYNC DVI_HPD_R GPU_DDC_A_CLK 1 Q9711 100 5% 1/16W MF-LF 402 S 4 2N7002DW-X-F 2 8 D 3 DVI_DDC_CLK R9713 1 15 G SOT-363 R9711 80B6 80D1 87A4 (PP5V_S0_DDC) DVI_DDC_DATA_R 7 5 5% 1/16W MF-LF 402 5% 50V CERM 402 R9720 10K Q9711 1 80C6 80D1 87A4 80C6 80D1 87A4 11 87A4 80D1 80A6 2 87A4 79C7 78C3 5% 1/16W MF-LF 2 402 100pF 0402 TMDS_DATA_P<3> R9712 3 80B3 80D1 87A4 PP3V3_D3C 4.7K 5% 1/16W MF-LF 402 2 47nH 87A4 79C7 78C3 1 4.7K GND_CHASSIS_DVI_BOT 74B2 71C4 71B8 71A4 67A5 67A3 65C7 82D7 82A7 80D5 77D2 77C6 77B7 74D6 VOLTAGE=5V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm B0530WXF 9 L9703 182 1% 1/16W MF-LF 402 2 0.25% 50V CERM 402 PP5V_S0_DDC SM-1 J9700 NO_TEST=TRUE 3.3pF L9710 2 F-RT-TH-DVI TMDS_DATA_RL<3> C9742 400-OHM-EMI 0.5AMP-13.2V QH11121-RIG02-4F 1 C 1 CRITICAL F9710 R9773 0 TMDS_CLK_P 80A3 (55mA requirement per DVI spec) 80A5 80D1 87A4 CRITICAL A VGA_R 4 DVI DDC CURRENT LIMIT SYM_VER-1 1 SM-LF 87A4 79C7 78C3 0.25% 50V CERM 402 L9706 TMDS_CLK_R_N 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 87A4 79C7 78C3 2 1% 1/16W MF-LF 402 2 DVI INTERFACE 182 1 C9741 75 1 80A3 3.3pF FL9742 LCFILTER 1 R9742 TMDS_CLK_N B VGA_G 1 CRITICAL GPU_R2 TMDS_DATA_P<2> 1 1 4 (DAC2 C) CRITICAL 87A4 79C7 78C3 2 3 1% 1/16W MF-LF 402 2 2 87B4 79C7 78C3 0.25% 50V CERM 402 2 0402 87B4 79C7 78C3 2 SM-220MHZ-LF 2 C9740 3.3pF FL9741 LCFILTER 75 4 47nH 87A4 79C7 78C3 1 CRITICAL 1 GPU_G2 SYM_VER-1 1 80A5 (DAC2 Y) 2 90-OHM-100MA 1210-4SM1 182 1% 1/16W MF-LF 402 79D7 78B3 20% 10V CERM 402 CRITICAL VGA_B 4 75 5% 1/16W MF-LF 402 1 2 3 R9740 1 0.1uF TMDS_DATA_N<2> 1 VGA_HSYNC_R 4 3 C9751 87A4 79C7 78C3 33 2 GPU_H2SYNC TMDS_DATA_P<1> 1 GPU_B2 (DAC2 Comp) R9751 MC74VHC1G08 SC70 2 87A4 79C7 78C3 FL9740 LCFILTER 80B3 80D1 87A4 06004 OF 80 1 87 A 8 6 7 2 3 4 5 1 D D Top-Case Connector IR & Sleep LED Connector 81A5 67C5 46C3 46B3 41C5 37D7 37D5 37C3 37A7 32C5 27C5 66C6 65D1 63B7 60C2 59C6 57D4 52B1 46D6 69C8 52B5 52B1 51D4 51D3 51C2 47B5 35B7 27C3 26D6 69A8 68B8 67D5 67D3 66D2 66C8 66A8 53C4 52D7 81C6 67B3 67B1 62A2 52B8 45C3 5D4 CRITICAL J9800 67C3 5D4 69B8 5D2 52B7 5B2 PP3V3_S3 PP3V42_G3H PP5V_S3 CRITICAL 88231-06001-01 J4900 M-RT-SM 7 NC QT500166-L020 PP5V_S3 M-ST-SM 5B2 5D4 45C3 52B8 62A2 67B1 67B3 81C4 1 52B2 51B5 USB_IR_N 46B5 USB_IR_P 2 46C3 46A5 IO 3 46C3 IO 52C6 52B2 51C5 5A2 OUT OUT SMC_LID SMC_ONOFF_L 4 5 52A7 SYS_LED_ANODE IN 6 8 22C2 6D3 6D2 6D1 IO 22C2 6D3 6D2 6D1 IO USB_TRACKPAD_P USB_TRACKPAD_N NC CRITICAL 1 2 3 4 57A4 5 6 57A4 7 8 9 10 11 12 13 14 15 16 KBDLED_RETURN KBDLED_ANODE SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL SMBUS_SB_SCL SMBUS_SB_SDA OUT IN IO IO IO IO D4900 SC-75 1 C C 3 518S0474 2 516S0350 RCLAMP0502B Bluetooth (M13P) & SATA HDD Flex Connector B B PLACEMENT_NOTE=Place C4960 close to southbridge PLACEMENT_NOTE=Place C4961 next to C4960 PLACEMENT_NOTE=Place FL4965 close to J4960 FL4965 C4960 90-OHM-100MA 1210-4SM1 0.0047uF 21B6 IN SATA_C_R2D_C_P 2 1 CRITICAL J4960 SYM_VER-1 SATA_C_R2D_UF_P QT500166-L020 M-ST-SM C4961 0.0047uF 21B6 IN SATA_C_R2D_C_N 2 1 10% 25V CERM 402 21B6 OUT 10% 25V CERM 402 SATA_C_R2D_P SATA_C_R2D_N SATA_C_R2D_UF_N FL4960 C4966 90-OHM-100MA 1210-4SM1 0.0047uF SYM_VER-1 SATA_C_D2R_N SATA_C_D2R_UF_N 2 C4965 0.0047uF 21B6 OUT SATA_C_D2R_P SATA_C_D2R_UF_P PLACEMENT_NOTE=Place FL4960 close to southbridge 2 1 1 10% 25V CERM 402 59C6 46D6 41C5 37C3 27C5 37A7 37D7 46C3 57D4 63B7 81D4 67C5 67C3 66C6 SATA_C_D2R_C_N SATA_C_D2R_C_P PP3V3_S3 5D4 32C5 37D5 46B3 52B1 60C2 65D1 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 PP5V_S0 5D2 5D4 25D8 31C5 36D6 53C4 55A8 57B5 58C4 58C7 61D7 62B1 66B5 67A1 67B1 67B3 71A6 79B8 80A1 80B5 NC 22C2 6C3 6C2 6C1 5A7 USB_BT_N USB_BT_P IO IO 10% 25V CERM 402 PLACEMENT_NOTE=Place C4966 next to C4965 PLACEMENT_NOTE=Place C4965 close to J4960 516S0350 M57 SPECIFIC CONNECTORS A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 81 1 87 A 8 6 7 2 3 4 5 1 LVDS Interface Pull-downs LVDS I/F Mux D3CPGOOD_ALL BOM option stuffs LTC2903 circuit to monitor all D3C rails to qualify D3CPGOOD. D3CPGOOD_3V3 BOM option uses only PP3V3_D3C to qualify D3CPGOOD. 13C5 LVDS_PD 13C5 LVDS_L_DATA_P<0> 1 8 LVDS_PD 5% 1/16W SM-LF D3CPGOOD_ALL 1 C9990 67D6 67C6 63B1 5D4 70C7 70A1 67D8 77B8 RP9900 0.1uF 8.2K 82C3 79D7 78A3 6B2 6B1 2 LVDS_L_DATA_N<0> LVDS_PD D3CPGOOD_ALL 1 7 R9994 8.2K 82C3 79D7 78A3 6B2 6B1 LVDS_L_CLK_N 4 2 5 2 1% 1/16W MF-LF 402 RP9900 LVDS_L_CLK_P 3 LVDS_PD 2 20% 10V CERM 402 10K 5% 1/16W MF-LF 2 402 1 CRITICAL V1 D3CPGOOD_ALL 3 4 V2 V3 U9990 LTC2903 66A2 82A4 TSOT-23 5 R9995 1% 1/16W MF-LF 402 LVDS_PD RP9901 D3CPGOOD_ALL D3CPGOOD_ALL 1 R9993 1 C9995 100K 0.1UF 1% 1/16W MF-LF 402 20% 2 10V CERM 402 2 8.2K 1 RST* 6 V4 13C5 2 13C5 NB LVDS I/F 13C5 13C5 5 1 S0PGOOD_PWROK MC74VHC1G08 4 D3CPGOOD_ALL 1 R9991 C9993 100K 0.1UF 1% 1/16W MF-LF 402 20% 2 10V CERM 402 2 GND D3CPGOOD_ALL 1 D3CPGOOD_ALL 1 C9992 470K 0.1UF 2 1 20% 2 10V CERM 402 2 13C5 S0D3CPGOOD_PWROK 82A4 13C5 C9996 13C5 1UF 5% 1/16W MF-LF 402 13C5 10% 2 6.3V CERM 402 13C5 8 78B3 6A1 79D7 78B3 6B2 6B1 82C8 79D7 5% 1/16W SM-LF LTC2903 guaranteed threshold is 93.5% (3.055V, 2.325V, 1.685V, 1.120V) 78B3 6B2 6B1 82C8 79D7 8.2K =LVDS_PD_L_CLK_P 4 78A3 6B2 6B1 82C8 79D7 5 78A3 6B2 6B1 82D8 79D7 LVDS_PD 5% 1/16W SM-LF RP9901 LVDS Mux Selection Qualification 8.2K C 6B2 3 =LVDS_PD_L_CLK_N 6 5% 1/16W SM-LF LVDS_PD 8.2K LVDS_U_DATA_N<0> 2 7 LVDS_PD 5% 1/16W SM-LF RP9902 8.2K 82C3 79D7 78B3 6B2 6B1 1 LVDS_U_DATA_P<0> LVDS_PD 8 5% 1/16W SM-LF RP9902 67C5 67C3 67B3 67A3 66B6 60D4 60C7 58C7 58C4 57B6 36D6 34A8 33D8 33D3 33C7 26D1 26B8 26B6 26B4 25D8 24C3 24B5 24B3 23D5 23B3 17C6 14D6 14C7 10C5 5D4 21D3 21C3 20B4 20A4 19C7 25C6 25C4 25B8 25B4 25A4 29A3 28A6 27D8 27D5 27D3 54B5 52D3 49C7 49C4 49B5 66B1 65D6 65B3 62A6 61D8 82D5 82B3 82A4 79D3 79A8 66B5 54D4 29A6 25D3 22B5 5A4 19C6 24D3 27C3 40B6 61A5 71D2 LVDS_B_DATA_P<1> LVDS_B_DATA_N<1> LVDS_B_CLK_N LVDS_B_CLK_P LVDS_B_DATA_P<2> A2 DA17 B1 DA18 D1 DA19 LVDS_U_DATA_N<2> LVDS_U_DATA_N<0> LVDS_U_DATA_P<0> G1 DB0* J1 DB1* 4 PP3V3_S0 66B5 63D1 19D7 19C5 19A8 19A6 19A4 17D6 17C6 5D4 82D3 67B6 67A8 67A6 C9985 79D7 78A3 6B1 PP2V5_S0 78B3 6A2 6A1 82B8 79D7 78B3 6A2 6A1 82B8 79D7 1 0.1UF 20% 10V CERM 2 402 LVDS_PD 79D7 78B3 6B1 C9980 1 0.1UF 5 5% 1/16W SM-LF 79D7 78A3 6B1 20% 10V CERM 2 402 78B3 6A1 79D7 LVDS_L_CLK_P LVDS_L_CLK_N LVDS_L_DATA_N<0> LVDS_L_DATA_P<0> LVDS_L_DATA_P<2> LVDS_L_DATA_N<2> LVDS_L_DATA_N<1> LVDS_L_DATA_P<1> LVDS_U_DATA_P<1> LVDS_U_DATA_N<1> LVDS_U_CLK_N LVDS_U_CLK_P LVDS_U_DATA_P<2> C10 DA11 A10 DA12 A8 DA13 DH0 F2 DH1 H2 DH2 J2 DH3 J3 LVDS_U_DATA_CONN_N<2> LVDS_U_DATA_CONN_N<0> LVDS_U_DATA_CONN_P<0> NC LVDS_L_CLK_CONN_P LVDS_L_CLK_CONN_N DH4 J5 DH5 J6 DH6 J8 DH10 E9 DH11 C9 DH12 B9 K2 DB2* J4 DB3* K5 DB4* K7 DB5* DH13 B8 DH14 B6 NC LVDS_U_CLK_CONN_N LVDS_U_CLK_CONN_P LVDS_U_DATA_CONN_P<2> DH18 C2 DH19 E2 F10 DB9* D10 DB10* B10 DB11* SEL E3 79C2 79D7 79C2 79D7 79C2 79D7 NC LVDS_U_DATA_CONN_P<1> LVDS_U_DATA_CONN_N<1> DH15 B5 DH16 B3 DH17 B2 K8 DB6* K10 DB7* H10 DB8* 79C2 79D7 79C2 79D7 NC LVDS_L_DATA_CONN_N<0> LVDS_L_DATA_CONN_P<0> LVDS_L_DATA_CONN_P<2> LVDS_L_DATA_CONN_N<2> LVDS_L_DATA_CONN_N<1> LVDS_L_DATA_CONN_P<1> DH7 J9 DH8 H9 DH9 F9 79C2 79D7 79C2 79D7 79C2 79D7 79C2 79D7 79C2 79D7 79C2 79D7 79C2 79D7 79C2 79D7 79B2 79D7 C 79B2 79D7 79B2 79D7 LVDS_MUX_SEL_GPU_L A9 DB12* B7 DB13* A6 DB14* NOTE: SEL = LOW selects port B A4 DB15* A3 DB16* A1 DB17* C1 DB18* E1 DB19* GND H6 H5 =LVDS_PD_U_DATA_P<1> GPU LVDS I/F 79D7 78B3 6B1 8.2K 6A2 79D7 78A3 6B1 Enables the GPU LVDS path in the mux with the qualification that the GPU has turned on panel power and that the panel power has risen to (near) 3.3V. This should eliminate need for LVDS pulldowns RP9902 82C3 79D7 78B3 6B2 6B1 SYM_VER-3 A7 DA14 A5 DA15 B4 DA16 RP9901 6B2 BGA-LF K9 DA7 J10 DA8 G10 DA9 E10 DA10 3 D3CPGOOD_3V3 R9996 D3CPGOOD_ALL 2 1 D U9950 CBTV4020 LVDS_A_DATA_N<0> LVDS_A_DATA_P<0> LVDS_A_DATA_P<2> LVDS_A_DATA_N<2> LVDS_A_DATA_N<1> LVDS_A_DATA_P<1> SC70 2 D3CPGOOD_PWROK K3 DA3 K4 DA4 K6 DA5 20% 10V CERM 2 402 J7 DA6 13C5 0.1uF R9997 LVDS_A_CLK_P LVDS_A_CLK_N 1 13C5 D3CPGOOD_ALL 1 100K LVDS_PD 13D5 U9991 5% 1/16W SM-LF =LVDS_PD_L_DATA_N<2> 13C5 6 7 5% 1/16W SM-LF 1 1% 1/16W MF-LF 402 D3CPGOOD_1V8_DIV 8.2K 6B2 2 D3CPGOOD_1V2_DIV RP9901 =LVDS_PD_L_DATA_P<2> 2 13C5 PP3V3_S0 C9991 D3CPGOOD_2V5_DIV 8.2K 6B2 365K LVDS_PD 5% 1/16W SM-LF 82C3 79D7 78A3 6B2 6B1 R9990 237K 1% 1/16W MF-LF 402 20% 10V CERM 402 D3CPGOOD_ALL 1 R9992 124K 5% 1/16W SM-LF RP9900 D3CPGOOD_ALL 1 67A3 66B6 66B5 66B1 65D6 65B3 62A6 61D8 49C7 49C4 49B5 40B6 36D6 34A8 33D8 33D3 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 21D3 5D4 5A4 21C3 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 25B4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 61A5 60D4 60C7 58C7 58C4 57B6 54D4 54B5 52D3 82C6 82B3 82A4 79D3 79A8 71D2 67C5 67C3 67B3 1 0.1UF RP9902 C6 C5 8.2K 82C3 79D7 78A3 6B2 6B1 PP3V3_D3C PP2V5_D3C PP1V8_D3C PP1V2_D3C VDD F1 DA0 H1 DA1 CRITICAL K1 DA2 D2 D 71C4 71B8 71A4 67A5 67A3 65C7 82A7 80D5 80B2 77D2 77C6 77B7 78C8 77C6 77A8 67A8 67A6 63C1 5D4 LVDS_B_DATA_N<2> LVDS_B_DATA_N<0> LVDS_B_DATA_P<0> G2 D9 74D6 74B2 RP9900 C9950 E8 F8 PGOOD Monitor for GPU Rails PP2V5_S0 F3 66B5 63D1 19D7 19C5 19A8 19A6 19A4 17D6 17C6 5D4 82C5 67B6 67A8 67A6 G9 NOTE: These parts are to counter an invalid state caused by the M56 part. Bias voltage is present on LVDS interface pins even when they should be tri-stated to meet panel power sequence requirements. Resulting pump-up in LCD panel can cause startup and long-term reliability issues. Pull-down resistors reduce the pump-up in the panel, though some voltage will still be seen on LVDS signals when they should be 0V. 8.2K 6A2 =LVDS_PD_U_DATA_N<1> 3 6 5 LVDS_PD 5% 1/16W SM-LF RP9903 82A4 77C3 LVDS_U_CLK_N 2 82A4 82A3 21D5 7 SC70 4 3 1 79D3 PP3V3_LCD_SW 8 2 10K 5% 1/16W MF-LF 402 5% 1/16W SM-LF LVDS_PD 8.2K 6B2 =LVDS_PD_U_CLK_P 4 5 SC70-5 2 U9980 PANEL_PWR_ON 4 3 1 R9981 13.3K Panel/Backlight Control Mux LVDS_PD 5% 1/16W SM-LF 79A8 71D2 67C5 67C3 67B3 67A3 66B6 66B5 57B6 54D4 54B5 52D3 49C7 49C4 49B5 40B6 36D6 26D1 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 33D8 33D3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 65D6 65B3 62A6 61D8 61A5 60D4 60C7 58C7 82D5 82C6 82A4 RP9903 8.2K 6B2 1 1% 1/16W MF-LF 2 402 RP9903 B SN74LVC1G132 R9980 RP9903 LVDS_U_CLK_P 5 1 8.2K 82C3 79D7 78B3 6A2 6A1 CRITICAL GPU_DIGON_AND_SELECTED 2 LVDS_MUX_SEL_GPU LVDS_PD 5% 1/16W SM-LF MC74VHC1G08 U9985 8.2K 82C3 79D7 78B3 6A2 6A1 1 GPU_DIGON 3 =LVDS_PD_U_CLK_N Divider set to rise to 1.88V nom/1.74V min when panel power is at 3.3V/3.315V. Schmitt trigger voltage max is 1.70V (@2.625V Vcc). R9981 can also be used as pad for cap, creating an RC filter. 6 5% 1/16W SM-LF 66B1 34A8 25B4 5A4 21C3 27C3 58C4 79D3 B PP3V3_S0 C9960 1 0.1UF 20% 10V CERM 2 402 GPU DDC Pass FETs 80B2 26A2 26A1 77C6 77B7 74D6 74B2 71C4 71B8 71A4 67A5 67A3 65C7 82D7 80D5 80B2 77D2 CRITICAL U9960 PP3V3_D3C 13D5 82B6 77C3 1 R9970 13D5 15.8K 1% 1/16W MF-LF 402 2 2 67B3 67A3 66B6 66B5 66B1 65D6 65B3 62A6 52D3 49C7 49C4 49B5 40B6 36D6 34A8 33D8 33D3 26B8 26B6 26B4 25D8 25D3 25C6 25C4 25B8 25B4 20B4 20A4 19C7 19C6 17C6 14D6 14C7 10C5 5D4 5A4 25A4 24D3 24C3 24B5 24B3 23D5 23B3 22B5 21D3 21C3 33C7 29A6 29A3 28A6 27D8 27D5 27D3 27C3 26D1 61D8 61A5 60D4 60C7 58C7 58C4 57B6 54D4 54B5 82D5 82C6 82B3 79D3 79A8 71D2 67C5 67C3 Q9970 2N7002DW-X-F G 82A5 79C3 13D5 1 S GPU_DDC_C_CLK D 6 77D3 74C8 74C5 PP3V3_S0 SOT-363 78A3 13D5 C9961 77C3 1 0.1UF LVDS_CONN_DDC_CLK MAKE_BASE=TRUE 82D5 66A2 20% 10V CERM 2 402 13D5 79C3 82A7 82C4 PLT_RST_L R99711 15.8K 82B6 82A4 82A3 21D5 1% 1/16W MF-LF 402 2 GPU_DDC_C_DATA 3 5 6 11 10 14 13 1 LVDS_MUX_SEL_GPU_MUXED 5 A 2 LVDS_VDDEN GPU_DIGON LVDS_BKLTEN GPU_BLON LVDS_BKLTCTL GPU_VARY_BL S0PGOOD_PWROK S0D3CPGOOD_PWROK 15 NOTE: S = HIGH selects xB2 LVDS_CONN_DDC_CLK 79A8 26C3 26C1 26B1 26A4 22A6 14B7 6C7 6C6 5C4 78A3 16 VCC GPU_SIGNAL_ENABLE 5 LVDS_MUX_SEL_GPU 1 2 U9961 4 NO STUFF 3 GND 1 R9960 10K 8 LVDS_PANEL_EN 7 INVERTER_BKLTON 79B8 9 INVERTER_PWM_UNBUF 79A8 12 LVDS_CONN_DDC_DATA MAKE_BASE=TRUE THRML PAD LVDS Interface Pull-downs 17 SYNC_MASTER=M59_MLB 5% 1/16W MF-LF 2 402 SYNC_DATE=09/15/2006 NOTICE OF PROPRIETARY PROPERTY R9962 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING 5% 1/16W MF-LF 2 402 13D5 79C3 82A7 79D4 PGOOD_MUXED_S0_OR_S0D3C 66B2 0 SOT-363 3 5% 1/16W MF-LF 402 2 S OE* 4 1 2N7002DW-X-F D 100K SC70 Q9970 G 4 S R99611 MC74VHC1G08 74CBTLV3257 QFN 1B1 SYM_VER-2 1A 1B2 2B1 2A 2B2 3A 3B1 3B2 4A 4B1 4B2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 82A5 79C3 13D5 SIZE LVDS_CONN_DDC_DATA 82B6 82A4 82A3 21D5 LVDS_MUX_SEL_GPU LVDS_MUX_SEL_GPU LVDS_MUX_SEL_GPU 21D5 82A4 MAKE_BASE=TRUE NOTE: SB_GPIO23 has internal 20K PU to default selection to GPU 82B6 APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 82 1 87 A 8 7 6 5 4 3 2 1 Revision History D D C C B B Revision History A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 83 1 87 A 8 6 7 FSB (Front-Side Bus) Constraints 2 3 4 5 1 PCI-Express / DMI Bus Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FSB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF DMI_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =3:1_SPACING ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3:1_SPACING ? TABLE_SPACING_RULE_ITEM * FSB_ADDR TABLE_SPACING_RULE_ITEM FSB_DATA * TABLE_SPACING_RULE_ITEM FSB_ADDR2ADDR * =2:1_SPACING ? FSB_ADSTB * =3:1_SPACING ? FSB_DATA2DATA * =2:1_SPACING ? FSB_DSTB * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM D * =3:1_SPACING WEIGHT TABLE_SPACING_RULE_ITEM PCIE * 20 MIL ? DMI * 20 MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FSB_ADDR2ADSTB TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM D TABLE_SPACING_RULE_ITEM ? FSB_DATA2DSTB * =3:1_SPACING ? SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 7.2, 9.2 & 10.5.2 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2:1_SPACING ? Disk Interface Constraints TABLE_SPACING_RULE_ITEM FSB_COMMON * TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP IDE_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SATA_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF SPACING_RULE_SET LAYER TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_PHYSICAL_RULE_ITEM SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM FSB_ADDR FSB_ADDR * TABLE_PHYSICAL_RULE_ITEM FSB_ADDR2ADDR TABLE_SPACING_ASSIGNMENT_ITEM FSB_ADDR FSB_ADSTB * FSB_ADDR2ADSTB FSB_DATA FSB_DATA * FSB_DATA2DATA TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM FSB_DATA FSB_DSTB * IDE * =1.8:1_SPACING ? SATA * 20 MIL ? FSB_DATA2DSTB TABLE_SPACING_RULE_ITEM All FSB signals with impedance requirements are 55-ohm single-ended. Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs. Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs. DSTB complementary pairs are spaced 3:1, even in constraint areas. SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 10.6 & 10.7.2 Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD Design Guide recommends each strobe/signal group is routed on the same layer. Design Guide recommends FSB signals be routed only on internal layers. PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP AUDIO_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1. NOTE: Design Guide allows closer spacing if signal lengths can be shortened. TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =1.8:1_SPACING ? SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.2 & 4.3 TABLE_SPACING_RULE_ITEM AUDIO C CPU Signal Constraints * C SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * Y =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =STANDARD =STANDARD CPU_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB2_90D * Y =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2:1_SPACING ? TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_ITEM CPU_2TO1 * LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CPU_COMP * 25 MIL DG recommends at least 25 mils, >50 mils preferred ? USB2 * =4:1_SPACING USB2_2CLK * 25 MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM CPU_GTLREF * 25 MIL ? CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? DG says ? minimum spacing 50 mils to clocks TABLE_SPACING_RULE_ITEM SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.10.1.2 TABLE_SPACING_RULE_ITEM Internal Interface Constraints Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance. TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SMB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPI_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.4, 4.6.2, & 5.8.2.4 TABLE_PHYSICAL_RULE_ITEM DDR2 Memory Bus Constraints TABLE_SPACING_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP LINE-TO-LINE SPACING WEIGHT * =3:1_SPACING ? * =1.8:1_SPACING ? DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM SMB TABLE_PHYSICAL_RULE_ITEM SPI MEM_45S * Y =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD MEM_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MEM_70D * Y =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF TABLE_SPACING_RULE_ITEM B B TABLE_PHYSICAL_RULE_ITEM SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.17.1.1 TABLE_PHYSICAL_RULE_ITEM MEM_85D * Y =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF Clock Signal Constraints TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_ASSIGNMENT_HEAD WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * =4:1_SPACING MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM * =2:1_SPACING ? MEM_CTRL2MEM * =3:1_SPACING ? MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_CLK MEM_CMD * MEM_CLK2MEM =1.5:1_SPACING MEM_CLK MEM_DATA * MEM_CLK2MEM TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * =3:1_SPACING ? * =1.5:1_SPACING ? MEM_CTRL MEM_CLK * MEM_DQS * MEM_CLK2MEM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLK_FSB_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF CLK_PCIE_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF CLK_MED_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLK_SLOW_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK TABLE_PHYSICAL_RULE_HEAD SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM ? MEM_DATA2DATA AREA_TYPE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM * NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM MEM_CMD2CMD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_ASSIGNMENT_ITEM ? MEM_CTRL2CTRL SPACING_RULE_SET TABLE_PHYSICAL_RULE_ITEM MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DQS * MEM_CTRL2MEM TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_RULE_ITEM MEM_DATA2MEM * =3:1_SPACING NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CMD MEM_CLK * MEM_CMD2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DATA MEM_CLK * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM * =3:1_SPACING 25 MIL 25 MIL ? * 20 MIL ? CLK_MED * 20 MIL ? CLK_SLOW * 10 MIL ? TABLE_SPACING_RULE_ITEM MEM_CMD MEM_CTRL * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CTRL * TABLE_SPACING_RULE_ITEM MEM_DATA2MEM ? TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CMD * MEM_CMD2CMD TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CMD * TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DATA * MEM_CMD2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_DQS MEM_DATA * MEM_DQS2MEM Need to support MEM_*-style wildcards! NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK * * MEM_2OTHER MEM_CTRL * * MEM_2OTHER MEM_CMD * * MEM_2OTHER MEM_DATA * * MEM_2OTHER TABLE_SPACING_RULE_ITEM MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA MEM_DATA MEM_DQS * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD A * ? TABLE_SPACING_RULE_ITEM * TABLE_SPACING_RULE_ITEM CLK_FSB CLK_PCIE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_2OTHER WEIGHT ? TABLE_SPACING_RULE_ITEM MEM_DQS2MEM LINE-TO-LINE SPACING TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM Napa Platform Constraints TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM NOTICE OF PROPRIETARY PROPERTY TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING TABLE_SPACING_ASSIGNMENT_ITEM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * * MEM_2OTHER II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DQS * MEM_DQS2MEM SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE 8 SHT NONE SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 6.2 7 6 5 4 3 2 REV. 051-7164 06004 OF 84 1 87 A 8 6 7 2 3 4 5 GDDR3 (Frame Buffer) Memory Bus Constraints 1 High-Speed I/O Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_PHYSICAL_RULE_HEAD DIFFPAIR NECK GAP PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF FW_110D * Y =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM FB_35S_TO_55S * Y =35_OHM_SE =55_OHM_SE =35_55_OHM_SE =STANDARD TABLE_PHYSICAL_RULE_ITEM =STANDARD TABLE_PHYSICAL_RULE_ITEM FB_40S * Y =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD TABLE_PHYSICAL_RULE_ITEM =STANDARD TABLE_PHYSICAL_RULE_ITEM FB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD FB_75D * Y =75_OHM_DIFF =75_OHM_DIFF =75_OHM_DIFF =75_OHM_DIFF =75_OHM_DIFF TABLE_SPACING_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM ENET * =3:1_SPACING ? FW * =3:1_SPACING ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_ITEM WEIGHT TABLE_SPACING_RULE_ITEM D FB_ADCTRL * =2.5:1_SPACING ? FB_CLK * =2.5:1_SPACING ? D note TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM FB_DATA * =2.5:1_SPACING ? PCI Bus Constraints ADDR/CTRL lines should route 35-ohms to T, then 55-ohms to each VRAM device. CTRL lines are 55-ohm single-ended impedence. DQ/DQM/DQS lines are 40-ohm single-ended impedence. TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM NOTE: CLK lines are specified in Layout Guide as 40-ohm single-ended. We treat as 75-ohm differential. NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close" TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT =2:1_SPACING ? TABLE_SPACING_RULE_ITEM SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2. PCI * Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LVDS_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TMDS_100D * Y =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF VGA_75S * Y =75_OHM_SE =75_OHM_SE =75_OHM_SE =STANDARD =STANDARD SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM LVDS * =3:1_SPACING TABLE_SPACING_RULE_ITEM ? LVDS_PAIR2PAIR * 25 MIL ? TMDS_PAIR2PAIR * 25 MIL ? TABLE_SPACING_RULE_ITEM TMDS * =3:1_SPACING TABLE_SPACING_RULE_ITEM ? TABLE_SPACING_RULE_ITEM C VGA * 15 MIL ? C TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM LVDS LVDS * LVDS_PAIR2PAIR TMDS TMDS * TMDS_PAIR2PAIR TABLE_SPACING_ASSIGNMENT_ITEM LVDS and TMDS signals are 100-ohm +/- 10% differential impedence. LVDS and TMDS pairs should be kept at least 25 mils apart. Ground shields can be used around each pair if spacing cannot be met. VGA should be routed as close to 75-ohms single-ended impedence as possible. VGA signals should be kept at least 15 mils from other traces. Ground shields recommended around VGA signals. NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close" SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2. B B More System Constraints A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 85 1 87 A 8 6 7 2 3 4 5 1 M9 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO TABLE_SPACING_RULE_HEAD BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION SPACING_RULE_SET TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.2 DEFAULT LAYER LINE-TO-LINE SPACING WEIGHT 0.1 MM ? TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM MEM_CLK * BGA BGA_P2MM CLK_FSB * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_MED * BGA BGA_P2MM CLK_SLOW * BGA BGA_P2MM TABLE_SPACING_RULE_ITEM * TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM STANDARD * =DEFAULT TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DEFAULT * Y =55_OHM_SE =55_OHM_SE 30 MM 0 MM 0 MM STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT TABLE_SPACING_RULE_ITEM BGA_P1MM * =DEFAULT TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM BGA_P2MM * =DEFAULT TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM BGA_P3MM * =DEFAULT TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD D PHYSICAL_RULE_SET 55_OHM_SE LAYER TOP,BOTTOM ALLOW ROUTE ON LAYER? Y MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP D DIFFPAIR NECK GAP TABLE_SPACING_ASSIGNMENT_ITEM 0.100 MM TABLE_PHYSICAL_RULE_ITEM FB_CLK * BGA BGA_P2MM TABLE_PHYSICAL_RULE_ITEM FSB_DSTB FSB_DSTB BGA BGA_P3MM 0.100 MM TABLE_SPACING_ASSIGNMENT_ITEM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 50_OHM_SE TOP,BOTTOM Y 0.124 MM 0.124 MM TABLE_PHYSICAL_RULE_HEAD Allow 0.1 MM on blind-to-buried via dogbones (layers 2 & 11) TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE * Y 0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM 1.5:1_SPACING * 0.15 MM ? TABLE_SPACING_RULE_ITEM 1.5:1_SPACING ISL2,ISL11 0.1 MM 1.8:1_SPACING TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET 45_OHM_SE LAYER TOP,BOTTOM ALLOW ROUTE ON LAYER? Y MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP * 0.18 MM ? * Y TABLE_PHYSICAL_RULE_ITEM 1.8:1_SPACING ISL2,ISL11 0.1 MM 2:1_SPACING * 0.2 MM ? TABLE_PHYSICAL_RULE_ITEM 2.5:1_SPACING * 0.25 MM ? 0.105 MM 0.105 MM =STANDARD =STANDARD MINIMUM LINE WIDTH CLK_PCIE ISL2,ISL11 0.1 MM ? TABLE_SPACING_RULE_ITEM 2:1_SPACING ISL2,ISL11 0.1 MM ? 2.5:1_SPACING ISL2,ISL11 0.1 MM ? TABLE_SPACING_RULE_ITEM CLK_MED ISL2,ISL11 0.1 MM ? CLK_SLOW ISL2,ISL11 0.1 MM ? CPU_COMP ISL2,ISL11 0.1 MM ? CPU_GTLREF ISL2,ISL11 0.1 MM ? CPU_VCCSENSE ISL2,ISL11 0.1 MM ? DMI ISL2,ISL11 0.1 MM ? LVDS_PAIR2PAIR ISL2,ISL11 0.1 MM ? MEM_2OTHER ISL2,ISL11 0.1 MM ? PCIE ISL2,ISL11 0.1 MM ? SATA ISL2,ISL11 0.1 MM ? TMDS_PAIR2PAIR ISL2,ISL11 0.1 MM ? VGA ISL2,ISL11 0.1 MM ? TABLE_SPACING_RULE_ITEM MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_RULE_ITEM =STANDARD 3:1_SPACING LAYER ? 0.150 MM * 0.3 MM ? TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET 0.1 MM TABLE_SPACING_RULE_ITEM ? TABLE_SPACING_RULE_ITEM ALLOW ROUTE ON LAYER? ISL2,ISL11 DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM 45_OHM_SE CLK_FSB TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 0.150 MM TABLE_SPACING_RULE_ITEM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 3:1_SPACING ISL2,ISL11 0.1 MM DIFFPAIR NECK GAP 4:1_SPACING * 0.4 MM ? TABLE_SPACING_RULE_ITEM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM 4:1_SPACING 0.1 MM ISL2,ISL11 TABLE_SPACING_RULE_ITEM ? TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y 0.185 MM TABLE_SPACING_RULE_ITEM 0.185 MM TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE * Y 0.131 MM 0.100 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 35_OHM_SE TOP,BOTTOM Y 0.230 MM 0.230 MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 35_OHM_SE C * Y 0.165 MM 0.165 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 27P4_OHM_SE TOP,BOTTOM Y 0.335 MM 0.335 MM 27P4_OHM_SE * Y 0.240 MM 0.240 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP C TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM Rules for "Topology #3" for FSB signals, Napa DG tables 4-7 & 4-12. TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET =STANDARD LAYER LINE-TO-LINE SPACING TABLE_SPACING_RULE_HEAD WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_OVERRIDE FSB_ADDR * TABLE_SPACING_RULE_OVERRIDE =2:1_SPACING ? FSB_DATA OVERRIDE OVERRIDE OVERRIDE * =2:1_SPACING ? OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP OVERRIDE DIFFPAIR NECK GAP OVERRIDE OVERRIDE TABLE_SPACING_RULE_OVERRIDE FSB_ADDR2ADDR TABLE_PHYSICAL_RULE_ITEM 35_55_OHM_SE TOP,BOTTOM Y 0.230 MM 0.100 MM 35_55_OHM_SE * Y 0.165 MM 0.076 MM * OVERRIDE OVERRIDE ? FSB_DATA2DATA OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD TABLE_SPACING_RULE_OVERRIDE =STANDARD * OVERRIDE =STANDARD ? OVERRIDE OVERRIDE TABLE_SPACING_RULE_OVERRIDE =STANDARD FSB_ADSTB * OVERRIDE OVERRIDE TABLE_SPACING_RULE_OVERRIDE =2:1_SPACING ? FSB_DSTB OVERRIDE OVERRIDE OVERRIDE * OVERRIDE =2:1_SPACING ? OVERRIDE OVERRIDE TABLE_SPACING_RULE_OVERRIDE Unsupported rule FSB_ADDR2ADSTB PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 75_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD * OVERRIDE TABLE_PHYSICAL_RULE_HEAD OVERRIDE TABLE_SPACING_RULE_OVERRIDE =2:1_SPACING ? FSB_DATA2DSTB OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM * OVERRIDE =2:1_SPACING ? OVERRIDE OVERRIDE TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_ASSIGNMENT_ITEM LVDS * LVDS_100D TMDS * TMDS_100D TMDSCONN * TMDS_100D MEM_2OTHER TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_OVERRIDE OVERRIDE * OVERRIDE TABLE_SPACING_RULE_OVERRIDE 0.5 MM ? PCI_2PCI OVERRIDE OVERRIDE OVERRIDE * OVERRIDE 0.1 MM ? OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 70_OHM_DIFF * Y 0.149 MM 0.149 MM =STANDARD 0.125 MM 0.125 MM 70_OHM_DIFF TOP,BOTTOM Y 0.185 MM 0.185 MM 0.125 MM 0.125 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 75_OHM_DIFF * Y 0.131 MM 0.131 MM =STANDARD 0.125 MM 0.125 MM 75_OHM_DIFF TOP,BOTTOM Y 0.161 MM 0.161 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET PCI PCI * PCI_2PCI TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM VGA * TABLE_SPACING_ASSIGNMENT_ITEM VGA_75S TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET ENETCONN * * ENET TMDSCONN * * TMDS TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM B TABLE_SPACING_ASSIGNMENT_ITEM B TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 80_OHM_DIFF * Y 0.115 MM 0.111 MM =STANDARD 0.125 MM 0.125 MM "Stale" physical / spacing types TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET FSB_ANALOG * * FSB_COMMON TABLE_PHYSICAL_RULE_ITEM 80_OHM_DIFF TOP,BOTTOM Y 0.140 MM 0.140 MM 0.125 MM 0.125 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM FSB_P2MM * * FSB_COMMON TABLE_PHYSICAL_RULE_ITEM I2C * * SMB TABLE_PHYSICAL_RULE_ITEM GND * * STANDARD MEM_PP1V8_S3 * * STANDARD FB_PP1V8 * * STANDARD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_ASSIGNMENT_ITEM 85_OHM_DIFF * Y 0.101 MM 0.101 MM 85_OHM_DIFF TOP,BOTTOM Y 0.125 MM 0.125 MM =STANDARD 0.125 MM 0.125 MM 0.125 MM 0.125 MM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP TABLE_SPACING_ASSIGNMENT_ITEM DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 90_OHM_DIFF * Y 0.102 MM 0.102 MM 90_OHM_DIFF TOP,BOTTOM Y 0.130 MM 0.130 MM =STANDARD 0.220 MM 0.220 MM 0.220 MM 0.220 MM FSB_ANALOG TABLE_PHYSICAL_RULE_ITEM FSB_P2MM I2C TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_OHM_DIFF * Y 0.080 MM 0.080 MM =STANDARD 0.200 MM 0.200 MM GND MEM_PP1V8_S3 TABLE_PHYSICAL_RULE_ITEM FB_PP1V8 TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF TOP,BOTTOM Y 0.099 MM 0.099 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 0.200 MM 0.200 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI PCI_55S M9 Spacing & Physical Constraints TABLE_PHYSICAL_RULE_HEAD A MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_ITEM 110_OHM_DIFF * Y 0.077 MM 0.077 MM =STANDARD 0.330 MM LAYER 0.330 MM ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP 110_OHM_DIFF TOP,BOTTOM Y 0.089 MM 0.089 MM 0.330 MM 0.330 MM MEM_45S * OVERRIDE OVERRIDE * OVERRIDE NOTICE OF PROPRIETARY PROPERTY 0.100 MM OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE TABLE_PHYSICAL_RULE_ITEM MEM_70D OVERRIDE SYNC_DATE=(MASTER) DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM SYNC_MASTER=(MASTER) 0.100 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE TABLE_PHYSICAL_RULE_ITEM MEM_85D * OVERRIDE OVERRIDE II NOT TO REPRODUCE OR COPY IT 0.100 MM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 86 1 87 A 8 6 7 3 4 5 2 1 NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING MEM_CLK D FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_COMMON FSB_55S FSB_DATA FSB_55S FSB_DATA FSB_55S FSB_DSTB FSB_55S FSB_DSTB FSB_55S FSB_ADDR FSB_55S FSB_ADDR FSB_55S FSB_ADSTB CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S CPU_55S C CPU_55S CPU_2TO1 CPU_55S CPU_2TO1 CPU_55S CPU_2TO1 CPU_55S CPU_GTLREF CPU_55S CPU_COMP CPU_27P4S CPU_COMP CPU_55S CPU_COMP CPU_27P4S CPU_COMP CPU_55S CPU_ITP CLK_FSB_100D CPU_ITP CLK_FSB_100D CPU_ITP CPU_55S CPU_ITP CPU_55S CPU_2TO1 CPU_55S CPU_2TO1 THERM CPU_27P4S CPU_VCCSENSE THERM CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_RS_L<2..0> FSB_TRDY_L FSB_CPURST_L FSB_D_L<63..0> FSB_DINV_L<3..0> FSB_DSTBP_L<3..0> FSB_DSTBN_L<3..0> FSB_A_L<31..3> FSB_REQ_L<4..0> FSB_ADSTB_L<3..0> FSB_IERR_L FSB_FERR_L CPU_PWRGD CPU_INTR CPU_NMI CPU_A20M_L CPU_DPSLP_L CPU_IGNNE_L CPU_INIT_L CPU_SMI_L CPU_STPCLK_L CPU_THERMTRIP_L PM_DPRSLPVR IMVP_DPRSLPVR CPU_GTLREF CPU_COMP<3> CPU_COMP<2> CPU_COMP<1> CPU_COMP<0> XDP_BPM_L<5..0> CPU_XDP_CLK_P CPU_XDP_CLK_N ITPRESET_L CPU_VID<6..0> CPU_VID<6..0> CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N MEM_70D 5B7 7D6 12C4 MEM_CTRL MEM_45S 5B7 7D6 12C4 MEM_CMD MEM_55S 7D6 12C4 MEM_DATA MEM_55S 5B7 7D6 12C4 MEM_DQS MEM_85D FB_CLK FB_75D FB_ADCTRL FB_35S_TO_55S FB_ADCTRL FB_55S FB_DATA FB_40S 5B7 7D6 12B4 LVDS LVDS_100D 5A7 7D6 12B4 TMDS TMDS_100D 7D6 12A4 VGA VGA_75S PCIE PCIE_100D DMI DMI_100D SATA SATA_100D IDE IDE_55S USB2 USB2_90D ENET ENET_100D FW FW_110D SMB SMB_55S SPI SPI_55S CLK_FSB CLK_FSB_100D 5B4 7B3 21C4 CLK_PCIE CLK_PCIE_100D 7C8 21C4 CLK_MED CLK_MED_55S 7C8 21C4 CLK_SLOW CLK_SLOW_55S 5B7 7D6 12B4 7D6 12B4 5A4 7B3 12B4 5B7 7D6 12B4 5B7 7D6 12B4 D 7D6 12A4 5A4 7D6 11B5 12C4 5B7 7B3 7B4 7C3 7C4 12B6 12C6 12D6 5B7 7B3 7B4 7C3 7C4 12B4 5B7 7B3 7B4 7C3 7C4 12B4 5B7 7B3 7B4 7C3 7C4 12B4 5B7 7C8 7D8 12C4 12D4 5A7 7D8 12A4 12B4 5B7 7C8 7D8 12C4 7D6 7C8 21C4 5B4 7B3 21C4 7C8 21C4 7D6 21C4 7C8 21C4 5C4 7C8 21C4 5B4 14B7 23C3 61C8 C 5C4 61C7 7B4 7B3 7B3 7B3 7B3 7C6 11B3 11B3 33C4 34D3 34D5 11B3 33C4 34D3 34D5 11B3 8B7 9C2 87B6 8B7 9C2 87B6 8B6 61B1 8B6 61A1 61A3 61A3 AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO AUDIO_55S AUDIO TMDS TMDS TMDS TMDS TMDS TMDS TMDS TMDS I70 TMDS TMDS I71 TMDS TMDS TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN TMDSCONN I72 TMDSCONN TMDSCONN I73 TMDSCONN TMDSCONN B SB_ACZ_BITCLK ACZ_BITCLK SB_ACZ_SYNC ACZ_SYNC SB_ACZ_RST_L ACZ_RST_L ACZ_SDATAIN<0> SB_ACZ_SDATAOUT ACZ_SDATAOUT 21C6 5C1 21C7 48B3 21C6 5C1 21C7 48B3 B 21C6 5C1 21C7 48B3 5C1 21C7 48B3 21C6 5C1 21C7 48B3 TMDS_CLK_P TMDS_CLK_N TMDS_DATA_P<5..3> TMDS_DATA_N<5..3> TMDS_DATA_P<2..0> TMDS_DATA_N<2..0> TMDS_CLK_F_P TMDS_CLK_F_N TMDS_DATA_F_P<5..3> TMDS_DATA_F_N<5..3> TMDS_DATA_F_P<2..0> TMDS_DATA_F_N<2..0> 78C3 79C7 80B8 78C3 79C7 80C8 78C3 79C7 80A8 80B8 78C3 79C7 80A8 80B8 78C3 79C7 80C8 80D8 78C3 79C7 80C8 80D8 80B5 80B6 80D1 80A5 80C6 80D1 80A6 80B3 80B5 80B6 80D1 80A6 80B3 80B5 80B6 80D1 80B3 80B5 80C6 80D1 80D6 80B3 80B5 80C6 80D1 80D6 M57 NET PROPERTIES A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE APPLE COMPUTER INC. DRAWING NUMBER D SCALE SHT NONE 8 7 6 5 4 3 2 REV. 051-7164 06004 OF 87 1 87 A
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