Product Detail Manual 07

User Manual: 07

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54/74 Family
MSI/LSI Circuits

•

7-1

•

7·2

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

The following pages contain functional indexes and selection guides designed to simplify the choice of a particular
function to fit a specific application. Essential characteristics of similar or like functions are grouped for comparative
analysis, and the electrical specifications are referenced by page number. The following categories of functions are
covered:
Page
Adders
..................... .
Accumulators, arithmetic logic units, look·ahead carry generators
Multipliers . . . . . .
Comparators . . . . . .
Parity generators/checkers .
Other arithmetic operators
Quad,hex, and octal flip-flops
Register files
..
Shift registers . . . .
Other registers
Latches . . . . . .
Clock generator circuits
Code converters . . .
Priority encoders/registers
Data selectors/multiplexers
Decoders/demuitipiexers
............ .
Open-collector display decoders/drivers with counters/latches
Open-collector display decoders/drivers . . . . . . . . .
Bus transceivers and drivers
............ .
Asynchronous counters (ripple clock)-negative-ooge triggered
Synchronous counters-Positive-ooge triggered
Bipolar bit-slice processor elements
First-in first-out memories (FI Fa's) . . . .
Random-access read/write memories (RAM's)
Read-only memories (ROM's)
..... .
Programmable-read-only memories (PROM's)
Microprocessor controllers and support functions

7-4
7-4
7-4
7-4
7-5
7-5
7-5
7-5
7-6
7-6
7-7
7-7

7-7
7-8
7-8
7-9
7-9
7-10
7-11
7-11
7-12
7-12
7-12
7-13
7-13
7-14
7-14

•

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE sOX 5012

•

DALLAS. TEXAS 75222

7-3

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
ADDERS

DESCRIPTION

TYPICAL

TYPICAL

TYP POWER

DEVICE TYPE

CARRY

ADD

DISSIPATION

AND PACKAGE

TIME

TIME

PER BIT

-55°C to 125°C

PAGE
NO.

O°C to 70°C

SINGLE l·BIT GATED FULL ADDERS

10.5 ns

52 ns

105mW

SN5480

J,W

SN7480

J, N

7-41

SINGLE 2-BIT FULL ADDERS

14.5 ns

25 ns

87 mW

SN5482

J,W

SN7482

J, N

7-49

10 ns

15 ns

24mW

SN54LS83A

J,W

SN74LS83A

J, N

7-53

10 ns

15 ns

24mW

SN54LS283

J,W

SN74LS283

J, N

7-415
7-415

SINGLE 4-BIT FULL ADDERS

DUAL l-BIT CARRY-SAVE FULL ADDERS

11 ns

7 ns

124mW

SN54S283

J

SN74S283

J, N

10 ns

16 ns

76mW

SN5483A

J,W

SN7483A

J, N

7-53

10 ns

16 ns

76mW

SN54283

J,W

SN74283

J, N

7-415

11 ns

11 ns

110mW

SN54H183

J,W

SN74H183

J, N

7-287

15 ns

15 ns

23mW

SN74LS183 * J, N

7-287

SN54LS183* J,W

ACCUMULATORS, ARITHMETIC LOGIC UNITS, LOOK-AHEAD CARRY GENERATORS
TYPTOTAL

DEVICE TYPE

CARRY

ADD

POWER

AND PACKAGE

TIME

TIME

DISSIPATION

TYPICAL TYPICAL
DESCRIPTION
4-BIT PARALLEL
BINARY ACCUMULATORS
4-BIT ARITHMETIC LOGIC UNITSI
FUNCTION GENERATORS

LOOK-AHEAD CARRY GENERATORS

•

-55°C to 125°C

10 ns

20 ns

720mW

11 ns

20 ns

525mW

SN54S281

7 ns

11 ns

600mW

SN54S181

12.5 ns

24 ns

455mW

16 ns

24 ns

102mW

7 ns
13ns

PAGE
NO.

O°C to 70°C
SN74S281

J, N

SN74S381

N

7-484

J,W

SN74S181

J, N

7-271

SN54181

J,W

SN74181

J, N

7·271

SN54LS181

J,W

SN74LS181

J, N

260mW

SN54S182

J,W

SN74S182

J, N

180mW

SN54182

J,W

SN74182

J, N

J,W

7-410

7-271
7-282

MUL TlPLlERS
DEVICE TYPE AND PACKAGE

DESCRIPTION

!

_55°C to 125°C

PAGE

O°C to 70°C

NO.

J, N

2-BIT-BY-4-B!T PARALLEL BINARY MULTIPLIERS

SN54LS261

J,W

SN74LS261

4-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS

SN54284, SN54285
SN54S274

J, W
J

SN74284, SN74285I J, N
I J, N
SN74S274

7-BIT-SLICE WALLACE TREES

SN54LS275

J

SN74LS275

J, N

SN54S275

J

SN74S275

J, N

I

7-380
7-420

i
I

7-391
7-391

25-MHz 6-BIT-BINARY RATE MULTIPLIERS

SN5497

J,W

SN7497

J, N

7-102

25-MHz DECADE RATE MULTIPLIERS

SN54167

J, W

SN74167

J, N

7-222

COMPARATORS

DESCRIPTION

4-BIT MAGNITUDE COMPARATORS

TYPICAL

TYPTOTAL

DEVICE TYPE

COMPARE

POWER

AND PACKAGE

TIME

DISSIPATION

_55°C to 125°C

PAGE
NO.

O°C to 70°C

11.5 ns

365mW

SN54S85

J,W

SN74S85

J, N

21 ns

275mW

SN5485

J,W

SN7485

J, N

23.5 ns

52mW

SN54LS85

J,W

SN74LS85

J, N

82 ns

20mW

SN54L85

SN74L85

J, N

J

7-57

'New product in development as of October 1976.

1076

7-4

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
PARITY GENERATORS/CHECKERS

DESCRIPTION

9·BIT ODD/EVEN PARITY GENERATORS/CHECKERS
8-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

TYPICAL

TYP TOTAL

DELAY

POWER

DEVICE TYPE

TIME

DISSIPATION

31 ns

80mW

13 ns

335mW

SN54S280

35 ns

170mW

SN54180

PAGE
-55°C to 125°C

I

SN54LS280

J, W
J, W

I J,W

NO.

O°C to 70°C
SN74LS280
SN74S280
SN74180

I

J, N
J, N

7-406

I J, N

7·269

OTHER ARITHMETIC OPERATORS
TYPICAL

TYPTOTAL

DEVICE TYPE

DELAY

POWER

AND PACKAGE

TIME

DISSIPATION

DESCRIPTION

7 ns
QUADRUPLE 2·INPUT EXCLUSIVE-OR
GATES WITH TOTEM·POLE OUTPUTS

PAGE
NO.

250mW

SN54S86

J, W

SN74S86

J, N
J, N

7-65
7·65

10 ns

30mW

SN54LS86

J, W

SN74LS86

10 ns

30mW

SN54LS386

J, W

SN74LS386

14 ns

i50mW

J, W
J, T

SN7486
SN74L86

J, W

SN74LS136! J, N ! 7.131

I

J, N

7-487

55 ns

15mW

QUADRUPLE 2·INPUT EXCLUSIVE-OR GATES

18 ns

30mW

SN54LS136

WITH OPEN·COLLECTOR OUTPUTS

27 ns

150mW

nUADRupl 1= 2·!NPUT EXCLUS!VE·NOR GATES

18 ns

40mW

8 ns

325mW

SN54S135

J, W

SN74S135

J, N

7·129

14 ns

270mW

SN54H87

J, W

SN74H87

J, N

7·70

QUADRUPLE EXCLUSIVE OR/NOR GATES
4-BIT TRUE/COMPLEMENT, ZERO/ONE ELEMENT

N
J, N

I 7·65

SN5486
SN54L86

j,

7-65

~~:~~~66 ~: ~ !:~~:~~~66 !~: ~ !
'

7·386

!

QUAD, HEX, AND OCTAL FLlP·FLOPS
POWER

F·F
DESCRIPTION

FREQ

PER

FLlp·FLOP

PKG
50 MHz
I D TYPE 3·STATE WITH ENABLE

I

D TYPE WITH ENABLE

DEVICE TYPE

SETUP

HOLD

ns

ns

26mW

20t

Ot

PAGE

AND PACKAGE
-55°C to 125°C

NO.

O°C to 70°C

SN54LS364'

J

SN74LS364' J, N

7-467

50 MHz

17mW

20t

Ot

I SN54LS374'

J

SN74LS374' J. N I 7-471 I

100 MHz

56mW

51

21

I SN54S374

J

SN74S374

J: N

8

40 MHz

10.6mW

20t

51

! SN54LS377

J

SN74LS377

J, N

7-481

6

40 MHz

10.6mW

201

51

SN54LS378

J,W

SN74LS378

J, N

7-481

4

40 MHz

10.6mW

201

51

SN54LS379

J

SN74LS379

J, N

7-481

40 MHz

39mW

201

51

SN54273

J

SN74273

J, N,

40 MHz

10.6mW

201

51

SN54LS273

J

SN74LS273

J, N
J, N

8

8

D TYPE WITH CLEAR

DATA TIMES

PER

35 MHz

38mW

201

51

SN54174

J,W

SN74174

40 MHz

10.6mW

20t

51

SN54LS174

J,W

SN74LS174

J, N

110MHz

75mW

51

31

SN54S174

J,W

SN74S174

J, N

6

35 MHz

38mW

201

51

SN54175

J,W

SN74175

J, N

40 MHz

10.6mW

201

51

SN54LS175

J,W

SN74LS175

J, N

110MHz

75mW

5t

31

SN54S175

J, W

SN74S175

J, N

4

I

7-471

I

I

7·388

7·253

7·253

J·K TYPE WITH SEPARATE CLOCK

4

50 MHz

75mW

31

101

SN54276

J

SN74276

J, N

7-401

J·K TYPE WITH COMMON CLOCK

4

45 MHz

65mW

Ot

20t

SN54376

J,W

SN74376

J, N

7-479

REGISTER FILES

DESCRIPTION
EIGHT WORDS OF TWO BITS
FOUR WORDS OF FOUR BITS
FOUR WORDS OF FOUR BITS
(3-STATE OUTPUTS)

TYPICAL

TYP READ

DATA

TYPTOTAL

DEVICE TYPE

ADDRESS

ENABLE

INPUT

POWER

AND PACKAGE

TIME

TIME

RATE

DISSIPATION

33 ns

15 ns

20 MHz

560mW

SN74172

J, N

27 ns

15 ns

125mW

SN54LS170

J,W

SN74LS170

J, N

30 ns

15 ns

20 MHz
20 MHz

635mW

SN54170

J,W

SN74170

J, N

24 ns

19 ns

20 MHz

135mW

SN54LS670

J,W

SN74LS670

J, N

-55°C to 125°C

PAGE

O°C to 70°C

NO.
7·245
7·237
7·526

• New product in development as of October 1976.

1076

TEXAS INSTRUMENTS
Ir-.CORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-5

MSI/LSIFUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
SHIFT REGISTERS
NO.
OF

DESCRIPTION

BITS

SHIFT
FREO

SERIAL
INPUT

50 MHz
8

PARALLEL·IN,
PARALLEL·OUT
(BIDIRECTIONAL)

4
8
5

PARALLEL-IN,
PARALLEL-OUT
4

SERIAL-IN,

8

PARALLEL-IN,

8

SERIAL-OUT
4

I

8

DEVICE TYPE

Low

X X X

PAGE

AND PACKAGE
_55°C to 125°C

X

750mW

SN54S299

J,W

NO.

O°C to 70°C
SN74S299

J, N

7-437
7-437

35 MHz

D

Low

X X X

X

175mW

SN54LS299*

J

SN74LS299*

J, N

35 MHz

D

Sync L

X X X

X

175mW

SN54LS323*

J

SN74LS323*

J, N

7-443

25 MHz

D

Low

X

X X X

360mW

SN54198

J,W

SN74198

J N

7·338

70 MHz

D

Low

X X X X

450mW

SN54S194

J,W

SN74S194

J, N

25 MHz

D

Low

X

X

X

X

75mW

SN54LSl94A

J,W

SN74LSl94A

J, N

25 MHz

D

Low

X

X

X

X

195mW

SN54194

J,W

SN74194

J, N

25 MHz

J-K

Low

X

X

X

360mW

SN54199

J,W

SN74199

J, N

10MHz

D

Low

X

X

60mW

SN54LS96

J,W

SN74LS96

J, N

10MHz

D

Low

X

X

240mW

SN5496

J,W

5MHz

D

Low

X

X

120mW

SN54L96

SN7496

J, N

J

SN74L96

J N

7-316
7-338
7-95

70 MHz

J-K

Low

X

X

375mW

SN54S195

J,W

SN74S195

J, N

7-324

30 MHz

J-K

Low

X

X

195mW

SN54195

J,W

SN74195

J, N

7-324

SN54LS395A * J,W SN74LS395A * J, N

7-496

25 MHz

D

Low

X

X

75mW

25 MHz

D

None

X

X

195mW

SN5495A

J,W

SN7495A

J, N

7-89

25 MHz

D

Low

X

X

X

230mW

SN54179

J,W

SN74179

J, N

7-265

25 MHz

D

None

X

X

X

230mW

SN54178

J,W

SN74178

J, N

7-265

30 MHz

J-K

Low

X

X

70mW

SN54LS195A

J,W

SN74LS195A

J, N

7-324

25 MHz

D

None

X

X

65mW

SN54LS95B

J,W

SN74LS95B

J, N

25 MHz

D

None

X

X

70mW

SN54LS295B* J,W

SN74LS295B* J, N

7-429

7-89

3 MHz

J-K

None

X

X

19mW

SN54L99

J

SN74L99

J, N

7-109

3MHz

D

None

X

X

19mW

SN54L95

J,T

SN74L95

J, N

7-89

Low

X

80mW

SN54LSl64

J,W

SN74LSl64

J, N

25 MHz Gated D

Low

X

167mW

SN74164

Low

X

84mW

SN74Ll64

J, N
J, N

7-206

12MHz Gated D

SN54164
SN54L164

J,W
.J, T

25 MHz

D

None

X

X

X

210mW

SN54165

J,W

SN74165

J, N

7-212

35 MHz

D

None

X

X X

105mW

SN54LS165

J,W

SN74LS165

J, N

7-212

20 MHz

D

Low

X

X X

360mW

SN54166

J,W

SN74166

J, N

7-217

35 MHz

D

Low

X

X X

110mW

SN54LSl66

J,W

SN74LSl66

J, N

7-217

10MHz

D

High

X

X

175mW

SN5494

J,W

SN7494

J, N

7-86

None

X

SN54LS91

J,W

SN74LS91

J, N

25M

SERIAL-IN,
SERIAL-OUT

0

25MHz Gated D

PARALLEL-OUT

I

MODES
TYP TOTAL
++ ++ ~9
POWER
a:
..J
CLEAR
o :I:0 DISSIPATION
th th ..J
ASYNC

DATA

Gated D

110MHz
"'

Gated D
3MHz Gated D

I

I

~S-R '" shift right, SoL '" shift left

None
None

60mW

I~ III

175mW

I

17.5mW

I

SN5491 A
SN54L91

I

J, W ISN7491A
J, T SN74L91

J, N 17-81
J, N

I

OTHER REGISTERS

DESCRIPTION

FREO

ASYNC
CLEAR

TYP TOTAL

I

T

DEVICE TYPE

POWER

_55°C to 125°C

DISSIPATION

O°C to 70°C

None

36.5 mW

SN54LS398

J

SN74LS398

J, N

7-499

30 MHz

None

36.5 mW

SN54LS399

J,W

SN74LS399

J, N

7-499

SN54LS298

J,W

SN74LS298

J, N

7-432

SN54298
SN54L98

J,W

SN74298

J, N

7-432

J

SN74L98

J, N

7-107

J

SN74LS299*

J, N

25 MHz

None

65mW

125 MHz
3 MHz

None

195mW

None

25mW

8-BIT UNIVERSAL SHIFT/STORAGE

35 MHz

Low

175mW

SN54LS299*

REGISTERS

50 MHz

Low

750mW

SN54S299

J,W

SN74S299

J, N

25 MHz

High

250mW

J,W

SN74173

J, N

50 MHz

High

85mW

SN54173
SN54LS173*

J,W

SN74LS173*

J, N

QUADRUPLE BUS-BUFFER REGISTERS

NO.

30MHz
QUADRUPLE MULTIPLEXERS
WITH STORAGE

1

I PAGE I

AND PACKAGE

I

7-437
7-249

·New product in development as of October 1976.
1076

7-6

TEXAS I,,"CORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
LATCHES
NO.
DESCRIPTION

OF

CLEAR

TYPICAL

TYPTOTAL

DEVICE TYPE

DELAY

POWER

AND PACKAGE

TIME

DISSIPATION

OUTPUTS

BITS
MULTI-MODE BUFFERED

8

ADDRESSABLE

8

8

TRANSPARENT
DUAL 4-BIT WITH

8

INDEPENDENT ENABLE

I

DUAL 2-BIT WITH
INDEPENDENT ENABLE

4

Q

11 ns

410mW

SN54S412

J

SN74S412

J, N

Low

Q

12 ns

300mW

SN54259

J,W

SN74259

J, N

S-R

4

(SSI)

NO.

SN54LS259

J,W

SN74LS259

J, N

7-502
7-376

Low

Q

17 ns

110mW

None

Q

17 ns

210mW

None

Q

19 ns

120mW

SN54LS363*
SN54LS373*

J
J

SN74LS363* J, N
SN74LS373* J, N

None

Q

7 ns

525mW

SN54S373

J

SN74S373

J, N

7-471

Low

Q

11 ns

250mW

SN54116

J,W

SN74116

J, N

7-115

None

Q

15 ns

320mW

SN541 00

J,W

SN74100

J, N

7-113

None

Q,Q

15 ns

160mW

SN5475

J,W

SN7475

J, N

7-35

None

Q,a

30 ns

80mW

SN74L75

J, N

None

Q,a

11 ns

32mW

None

I

Q

I

Q
Q

None

QUAD

PAGE

O°C to 70°C

Low

None

I

-55°C to 125°C

15 ns

160mW

30 ns

80mW

10 ns

35mW

SN54L75

J

SN54LS75
SN5477

IJ~W

I

SN74LS75

J, N

SN54L77

I:~~~:~~51 j~W

7-467
7-471

7-35

I

7-35
7-35
7-35

I

I 7-35 I

None

! a,a !

12 ns

32mW

SN74LS375

j, N

None

Q

12 ns

90mW

SN54279

J,W

SN74279

J, N

None

Q

12 ns

19mW

SN54LS279

J,W

SN74LS279

J, N

i 7-478 i
6-60

CLOCK GENERATOR CIRCUITS

I
DESCRIPTION

DEVICE TYPE

TYP TOTAL
POWER

-55°C to 125°C

I DISSIPATION
CLOCK GENERATOR/DRIVERS

(FOR TMS 9900)

669mW

(FOR TMS 8080A)

719mW
90mW

DUAL VOLTAGE-CONTROLLED OSCILLATOR WITH ENABLE

525mW

DUAL VOLTAGE-CONTROLLED OSCILLATOR

PAGE

AND PACKAGE
O°C to 70°C
SN74LS362* J, N

NO.
7-460

SN74LS424

J, N

7-507

SN54LS124

J,W

SN74LS124

J, N

7-123

SN54S124

J, W

SN74S12L'

J, N

7-123

90mW

SN54LS326

J,W

SN74 LS326

J, N

7-445

150mW

SN54LS325

J,W

SN74LS325

J, N

150mW

SN54LS327

J,W

SN74LS327

J, N

90mW

7-445

SN54LS324

J,W

SN74 LS324

J, N

7-445

DUAL 30-MHz PULSE SYNCHRONIZERS/DRIVERS

255 mW

SN54120

J, W

SN74120

J, N

7-118

QUAD COMPLIMENTARY GATES (CLOCK/CLOCK) [SSI]

125mW

SN54265

J, W

SN74265

J, N

6-89

VOLTAGE-CONTROLLED OSCILLATOR WITH ENABLE

I

CODE CONVERTERS
TYPICAL
DELAY TIME

DESCRIPTION

PER PACKAGE

TYPICAL

DEVICE TYPE

TOTAL POWER

AND PACKAGE

DISSIPA TION

LEVEL

-55°C to 125°C

PAGE
NO.

O°C to 70°C

S-LiNE-BCD TO S-LiNE
BINARY, OR 4-LlNE TO 4-LlNE

25 ns

280 mW

SN54184

J,W

SN74184

J, N

7-290

25 ns

280mW

SN54185A

J,W

SN74185A

J, N

7-290

BCD 9's/BCD 10'5 CONVERTERS
S-BIT-BINARY TO S-BIT-BCD CONVERTERS

"New product in development as of October 1976.
1076

TEXAS li'ooCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-7

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
PRIORITY ENCODERS/REGISTERS

DESCRIPTION

FULL BCD PRIORITY ENCODERS
CASCADABLE OCTAL PRIORITY ENCODERS
CASCADABLE OCTAL PRIORITY ENCODERS
WITH 3-STATE OUTPUTS
4-BIT CASCADABLE PRIORITY REGISTERS

TYPICAL

TYPTOTAL

DEVICE TYPE

DELAY

POWER

AND PACKAGE

TIME

DISSIPATION

10 ns

225mW

15 ns

60mW

_55°C to 125°C

PAGE
NO.

O°C to 70°C

SN54147

J,W

SN74147

J, N

SN54LS147*

J,W

SN74LS147*

J, N

7-151

12 ns

190mW

SN54148

J,W

SN74148

J, N

15 ns

60mW

SN54LS148*

J,W

SN74LS148*

J, N

16 ns

63mW

SN54LS348*

J,W SN74LS348*

J, N

7448

35 ns

275mW

SN54278

J,W

J, N

7403

SN74278

7-151

DATA SELECTORS/MULTIPLEXERS
TYPICAL DELAY TIMES

TYPE
DESCRIPTION

OF
OUTPUT

16-LlNE-TO-l-LiNE
DUAL
8-LlNE-TO-l-LiNE

8-LlNE-TO-l-LiNE

DATA TO

DATA TO

INV

NON-INV

OUTPUT

OUTPUT

DUAL
4-LlNE-TO-l-LiNE

DEVICE TYPE

POWER

AND PACKAGE

ENABLE

DISSIPATION

11 ns

18 ns

200mW

3-State

10 ns

17 ns

220mW

3-State

4.5 ns

8 ns

14 ns

275mW

SN54S251

3-State

17 ns

21 ns

21 ns

250mW

SN54251

3-State

17 ns

21 ns

21 ns

35mW

SN54LS251

2-State

4.5 ns

8 ns

9 ns

225mW

2-State

8 ns

16 ns

22 ns

145mW
130mW

SN54152A

W

18 ns

27 ns

30mW

SN54LS151

J,W

18 ns

28mW

SN54LS152

W

16 ns

35mW

SN54LS253

J,W

2-State

8 ns

2-State

11 ns

2-State

11 ns
12 ns

SN54150

PAGE
NO.

oOe to 70°C

_55°C to 125°C

2-State

3-State

I

TYP TOTAL

FROM

J,W

SN74150

J, N

7-157

SN74351

N

7451

J,W

SN74S251

J, N

7-362

J,W

SN74251

J, N

7-362

J,W

SN74LS251

J, N

7-362

SN54S151

J,W

SN74S151

J, N

7-157

SN54151A

J,W

SN74151A

J, N

7-157

SN74LS151

J, N

7-157

SN74LS253

J, N

7-369

7-157
7-157

2-State

15 ns

22 ns

31 mW

SN54LS352

J,W

SN74LS352

J, N

7454

3-State

12 ns

21 ns

43mW

SN54LS353

J,W

SN74LS353

J, N

7457

9.5 ns

225mW

SN54S153

J,W

SN74S153

17 ns

180mW

SN54153

J,W

SN74153

J,W

2-State
2-State

I

6 ns

!

14 ns

!

2-State

14 ns

17 ns

31 mW

SN54LS153

2-State

27 ns

34 ns

90mW

SN541153

2-State

20 nst
20 nst
20 nst

195mW
32mW

SN54LS398

20 nst

37mW

QUADRUPLE

2-State

2-LlNE-TO-l-UNE

2-State

WITH STORAGE

2-State

20 nst
4 ns

5 ns

3-State
2-State

4 ns
5 ns

2-State
QUADRUPLE

3-State

2-LlNE-TO-l-UNE

3-State
2-State

12 ns
12 ns
7 ns
9 ns

2-State

SN74LS298

J, N

7432

SN74298

J, N

7432

SN74 LS398

J, N

7499

J, W SN74LS399
J I SN74L98
J,W SN74S258

J, N
J, N
J, N

7499
7-107
7-372

J,W

SN74S257

J, N

7-372

J,W

SN74S158

J, N

7-181

J,W

SN74S157

J, N

7-181

J, W SN74LS258A' J, N
J,W SN74LS257A' J, N

7-372

320mW

SN54S257

7 ns

195mW

8 ns

250mW

20 ns

60mW

SN54LS258A *

20 ns

60mW

12 ns

24mW

SN54LS257A'
SN54LSl58

14 ns

49mW

9 ns

14 ns

150mW

18 ns

27 ns

75mW

7-165
7-165

J,W

14 ns

2-State

J, N
J, N

J,W

25mW
280mW

2-State

SN74LS153
SN74L 153

SN54LS298

14 ns

I

7-165
7- 1 65

SN54298
SN54LS399
SN54L98
SN54S258

120 nst

2-State
3-State

65mW

J, N
I J, N

SN545158
SN54S157

J

I

7-372

J,W

SN74LS158

J, N

7-181

SN54LS157

J,W

SN74LS157

J, N

7-181

SN54157

J,W

SN74157

J, N

7-181

SN74L 157

J, N

7-181

SN54L 157

J

tFrom clock .
• N!"w product in development as of October 1976.
1076

7-8

TEXAS INSTRUMENTS
I .... CORPORATED

!=JOST OFFICE BOX 5012

•

CALLAS. TEXAS 75222

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

DECODERS/DEMUL TlPLEXERS

DESCR IPTION

4-lINE·TO-l6-lINE

4-lINE·TO·l (}'lINE,
BCD-TO-DECIMAL

TYPICAL TYPICAL

TYPE OF
OUTPUT

TYPTOTAL

DEVICE TYPE

SELECT

ENABLE

POWER

AND PACKAGE

TIME

TIME

DISSIPATION

Totem·Pole

23 ns

19 ns

170mW

Totem·Pole

46 ns

38 ns

85mW

Open·Coliector

24 ns

19 ns

170mW

-SSoC to 12SoC
SN54154
SN54L154
SN54159

J,W

J

PAGE
NO.

O°C to 70°C
SN74154

J, N

7·171

SN74L 154

J, N

7·171
7·188

J,W SN74159

J, N

Totem·Pole

17 ns

35mW

SN54LS42

J,W

SN54LS42

J, N

Totem-Pole

17 ns

140mW

SN5442A

J,W

SN7442A

J, N

Totem·Pole

34 ns

70mW

SN54L42

J

SN74L42

J, N

4-lINE·TO-l(}.lINE,

Totem-Pole

17 ns

140mW

SN5443A

J,W

SN7443A

J, N

EXCESS-3-TO-DECI MAL

Totem-Pole

34 ns

70mW

SN54L43

J

SN74L43

J, N

Totem-Pole

17 ns

140mW

SN5444A

J.W

SN7444A

Totem-Pole

34 ns

70mW

SN54L44

J

SN74L44

I J, N
J, N

4-lINE-TO-l (}'lINE
EXCESS-3-GRA yTO-DECIMAL
3-lINE-TO-8-lINE

DUAL 2-lINE-TO-4-lINE

Totem-Pole

8 ns

7 ns

245mW

Totem-Pole

22 ns

21 ns

31 mW

Totem-Pole

7.5 ns

6 ns

300mW

7-15

7-15

7-15

SN54S138

J, W

SN74S138

J, N

SN54LS138

J,W

SN74LS138

J, N

7-134

SN54S139

.J,vv

I j, N

7-134

J, N

7-134

7-134

Totem-Pole

22 ns

19 ns

34mW

SN54LSl39

J,W

SN74Si39
SN74LS139

Totem-Pole

18 ns

15 ns

30mW

SN54LS155

J,W

SN74LS155

J, N

7-175

Totem-Pole

21 ns

16 ns

125mW

SN54155

J,W

SN74155

J, N

7-175

SN54156

J,W

SN74156

J, N

7-175

SN54LS156

J,W

SN74LS156

J, N

7-175

Open-COllector

23 ns

18 ns

125mW

Open-Collector

33 ns

26ns

31 mW

OPEN-COLLECTOR DISPLAY DECODERS/DRIVERS WITH COUNTERS/LATCHES

DESCRIPTION

OUTPUT

OFF-STATE

TYPTOTAL

SINK

OUTPUT

POWER

DEVICE TYPE

CURRENT

VOLTAGE

DISSIPATION

55 V

340mW

7V

280mW

Ripple

SN54143

J,W

SN54144

J,W

BLANKING

PAGE

AND PACKAGE
-55°C to 125"C

OU C to 70°C

NO.

BCD COUNTER!
4-BIT LATCH!
BCD-TO-DECIMAL

7mA

I

SN74142

J, N

7-140

SN74143

J, N

7-143

SN74144

J, N

DECODER/DRIVER
BCD COUNTER!
4-BIT LATCH/
BCD-TO-SEVENSEGMENT DECODER/

Constant
Current

•

15mA

LED DRIVER
BCD COUNTER/
4-BIT LATCH/
BCD-TO-SEVENSEGMENT DECODER!

20mA

15V

280 mW

Ripple

25mA

15V

280mW

Ripple

7-143

LAMP DRIVER

RESUL TANT DISPLAYS USING '143, '144

6

1076

TEXAS)NSTRUMENTS
I~CORI'ORArED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-9

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE

OPEN-COLLECTOR DISPLAY DECODERS/DRIVERS

DESCRIPTION

BCD-TO-DECIMAL
DECODERS/DR IVERS

•

OFF-STATE

TYPTOTAL

SINK

OUTPUT

POWER

CURRENT

VOLTAGE

DISSIPATION

SOmA

30V

215mW

SOmA

15V

35mW

Invalid Codes
Invalid Codes SN54LS145

J,W

Invlaid Codes SN54145

12mA

15V

35mW

SOmA

15V

215mW

DEVICE TYPE
BLANKING

PAGE

AND PACKAGE
-55°C to 125°C

Invalid Codes SN5445

J,W

O°C to 70°C

NO.

SN7445

J, N

SN74LS145

J, N

7-20
7-148

J,W

SN74145

J, N

7-148
7-138

7-148

7 mA

60V

80mW

Invalid Codes

SN74141

J, N

40mA

30V

320mW

Ripple

SN5446A

J,W

SN7446A

J, N

7-22

40mA

30V

320mW

Ripple

SN54246

J,W

SN74246

J, N

7-22

40mA

15V

320mW

Ripple

SN5447A

J,W

SN7447A

J, N

7-22

40mA

15V

320mW

Ripple

SN54247

J,W

SN74247

J, N

7-351

24mA

15V

35mW

Ripple

SN74LS47

J, N

7-22

24mA

15V

35mW

Ripple

SN74LS247

J, N

7-351

12mA

15V

35mW

Ripple

SN54LS47

J,W

7-22

12mA

15V

35mW

Ripple

SN54LS247

J,W

7-351

20mA

30V

133mW

Ripple

SN54L46

J

SN74L46

J, N

7-22

20 mA

15V

133mW

Ripple

SN54L47

J

SN74L47

J, N

7-22

SEVEN·SEGMENT

6.4 mA

5.5V

265mW

Ripple

SN5448

J,W

SN7448

J, N

7-22

DECODERS/DR IVERS

6.4 mA

5.5V

265mW

Ripple

SN54248

J,W

SN74248

J, N

7-351

6mA

5.5 V

125mW

Ripple

SN74LS48

J, N

7-22

6mA

5.5V

125mW

Ripple

SN74LS248

J, N

7-351

2mA

5.5V

125mW

Ripple

SN54LS48

J,W

7·22

2mA

5.5 V

125mW

Ripple

SN54LS248

J,W

7-351

lamA

5.5V

165mW

Direct

SN5449

lamA

5.5V

265mW

Direct

SN54249

8mA

5.5V

40mW

8mA

5.5 V

40mW

4mA

5.5 V

40mW

Direct

SN54LS49

J,W

7-22

4mA

5.5 V

40mW

Direct

SN54LS249

J,W

7-351

BCD-TO-

I
I

OUTPUT

7-22

W
SN74249

J, N

7-351

Direct

SN74LS249

J, N

7-351

Direct

SN74LS49

J, N

J,W

7-22

RESULTANT DISPLAYS USING '46A, '47A, '48, '49, 'L46, 'L47, 'LS47, 'LS48, 'LS49

RESULTANT DISPLAYS USING '246, '247, '248, '249, 'LS247, 'LS248, 'LS249

1076

7-10

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
BUS TRANSCEIVERS AND DRIVERS
TYPICAL
DESCRIPTION

MAXIMUM MAXIMUM

PROPAGATION

SOURCE

SINK

DELAY TIMES

CURRENT

CURRENT

-lmA

CONTROLLER AND BUS DRIVER

4-BIT BUS TRANSCEIVERS
WITH STORAGE

-55°C to 125°C

10mA

-lmA

10mA

12 ns

-12mA

12mA

SN54LS245*

10 ns

-6.5mA

20mA

SN54S226*

FOR 8080A SYSTEMS
OCTAL BUS TRANSCEIVERS

DEVICE TYPE

PAGE

AND PACKAGE

J
J,W

NO.

O°C to 70°C
SN74S428

N

SN74S438

N

7·514

SN74LS245* J, N

7-349

SN74S226*

7-345

J, N

ASYNCHRONOUS COUNTERS (RIPPLE CLOCK)-NEGATIVE-EDGE TRIGGERED

DESCRiPTiON

COUNT

PARALLEL

FREQ

LOAD

50 MHz

TYP TOTAL

DEVICE TYPE

POWER

AND PACKAGE

DISSIPATION

PAGE

I O°C to 70°C
I J, W I SN74196 I J, N

_55°C to 125°C

Yes

Low

240mW

SN54196

Yes

375 mW

NO.
7-331

Yoo

Low
_"
... w
I

15n
... mIN
... -

SN54S196
1 SN54
176
.- ...

32 MHz

Set-to-9

High

40mW

SN54LS90

J,W

SN74LS90

N

7-72

32 MHz

Set-to-9

High

40mW

SN54LS290

J,W

SN74LS290

J, N

7-423

32 MHz

Set-to-9

High

160mW

SN5490A

J,W

SN7490A

J, N

7-72

32 MHz

Set-to-9

High

160mW

SN54290

J,W

SN74290

J, N

7-423
7-331

100MHZ
1 ""
,:!O:;!IJI~
....... z

DECADE

CLEAR

1

.

~.

J, W 1 SN74S196
1 -,I W
. _- ...
-- SN7417R

-

1 J,
",I
J,

N 1 7-331 1
7. ?59
.N

Yes

Low

60mW

SN54LS196

J,W

SN74LSl96

J, N

3 MHz

Set-to,9

High

20mW

SN54L90

J, T

SN74L90

J, N

7-72

50 MHz

Yes

Low

240mW

SN54197

J,W

SN74197

J, N

7-331

J,W

SN74S197

J, N

7-331

~N74177

J, N I 7-259

30 MHz

100 MHz

Yes

Low

375mW

SN54S197

I

I

I

35 MHz

Yes

Low

I

150 mIN

SN54177

I

32 MHz

None

High

SN54LS93

J,W

~~;~~S~3 I J, N

7-72

32 MHz

None

High

I

39mW

I 4-BiT BINARY

39mW

SN54LS293

J,W

SN74LS293

J, N

7-423

32 MHz

None

High

160mW

SN5493A

J,W

SN7493A

J, N

7-72

32 MHz

None

High

160mW

SN54293

J,W

SN74293

J, N

7-423

I

Yes

Low

60mW

SN54LS197

J,W

SN74LS197

J, N

7-331

3 MHz

None

High

20mW

SN54L93

J, T

SN74L93

J, N

7-72

32 MHz

None

High

39mW

SN54LS92

J,W

SN74LS92

J, N

32 MHz

None

High

160mW

SN5492A

J,W

SN7492A

J, N

SN54390

J,W

SN74390

J, N

SN54LS390

J,W

SN74LS390

J, N

7-489

SN54490

J,W

SN74490

J, N

7-520

SN54LS490

J,W

SN74LS490

J, N

7-520

SN54393

J,W

SN74393

J, N

7-489

SN54LS393

J,W

SN74LS393

J, N

7-489

30 MHz

DIVIDE-BY-12

DUAL DECADE

DUAL 4-BIT BINARY

I J, IN

25 MHz

None

High

210mW

35 MHz

None

High

75mW

25 MHz

Set-to-9

High

225mW

35 MHz

Set-to-9

High

75mW

25 MHz

None

High

190mW

35 MHz

None

High

75mW

II

7-72
7-489

1076

TEXAS I"ICORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-11

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
SYNCHRONOUS COUNTERS-POSITIVE-EDGE TRIGGERED

DESCRIPTION

COUNT

PARALLEL

FREQ

LOAD

40 MHz
DECADE

DECADE
UP/DOWN

DECADE
_1_
RATE MULTIPLIER, N10

4-BIT BINARY

4-BIT BINARY
UP/DOWN

•

6-BIT BINARY

--1-

RATE MULTIPLIER, N2

CLEAR

TYP TOTAL

DEVICE TYPE

POWER

AND PACKAGE

DISSIPATION

Sync

Sync-L

475mW

-SSoC to 12SoC

PAGE
NO_

O°C to 70°C

SN54S162

J,W

SN74S162

J, N
J, N

25 MHz

Sync

Sync-L

93mW

SN54LS162A

J,W

SN74LS162A

25 MHz

Sync

Async-L

93mW

SN54LS160A

J, W

SN74LS160A

J, N

25 MHz

Sync

Sync-L

305mW

SN54162

J,W

SN74162

J, N
J N

7-190

25 MHz

Sync

Async-L

305mW

SN54160

J,W

SN74160

40 MHz

Sync

None

500mW

SN54S168

J,W

SN74S168

J, N

7-226

25 MHz

Sync

None

100mW

SN54LS168A

J,W

SN74LS168A

J, N

7-226

25 MHz

Async

Async-H

85mW

SN54LS192

J,W

SN74LS192

J, N

7-306

25 MHz

Async

Async-H

325mW

SN54192

J,W

SN74192

J, N

7-306

20 MHz

Async

None

100mW

SN54LS190

J,W

SN74LS190

J, N

7-296

20 MHz

Async

None

325mW

SN54190

J,W

SN74190

J, N

7-296

3 MHz

Async

Async-H

42mW

SN74L 192

J, N

7-306

25 MHz

Set-to-9

Async-H

270mW

SN54167

SN74167

J, N

7-222

40 MHz

Sync

Sync-L

475mW

SN54S163

J, W

SN74S163

J, N

25 MHz

Sync

Sync-L

93mW

SN54LS163A

J,W

SN74LS163A

J, N

25 MHz

Sync

Async-L

93mW

SN54LS161A

J,W

SN74LS161A

J,N

25 MHz

Sync

Sync-L

305mW

SN54163

J,W

SN74163

J, N

SN54l192

J
J,W

7-190

25 MHz

Sync

Async-L

305 mW

SN54161

J,W

SN74161

J, N

40 MHz

Sync

None

500mW

SN54S169

J,W

SN74S169

J, N

7-226

25 MHz

Sync

None

100mW

SN54LS169A

J,W

SN74LS169A

J, N

7-226

SN54LS193

J,W

SN74LS193

J, N

7-306

SN54193

J,W

SN74193

J, N

7-306

SN54LS191

J,W

SN74LS191

J, N

7-296

SN54191

J, W

25 MHz

Async

Async-H

85mW

25 MHz

Async

Async-H

325 mW

20 MHz

Async

None

90mW

20 MHz

Async

None

325mW

3 MHz

Async

Async-H

42mW

Async-H

345mW

25 MHz

SN54l193

J

SN5497

J,W

SN74191

J, N

7-296

SN74l193

J, N

7-306

SN7497

J, N

7-102

BiPOLAR 8IT-SLICE PROCESSOR ElEMENTSt

DESCRIPTION

4-BIT SLICE

CASCADABLE

TYPICAL

TO

wOPERATION

DEVICE TYPE
TECHNOLOGY

N-BITS

TIME

Yes

100 ns

STTL

Yes

230 ns

Yes

230 ns

AND PACKAGE

1

-SSoC to 12SOC

O°C to 70°C

12L

SN545481
SBP0400AM

J
J

SN74S481
SBP0400AC

12L

SBP0401AM

J

SBP0401AC

I

J, N
J, N

J, N

FIRST-IN FIRST-OUT MEMORIES (FIFO'S)t
TYPE

DELAY TIME

TYP TOTAL

DEVICE TYPE

OF

FROM

POWER

AND PACKAGE

OUTPUT

CLOCK

DISSIPATION

-SSoC to 12 SoC , O°C to 70°C

3-State

50 ns

400mW

DESCRIPTION
ASYNCHRONOUS 16 X 5

1 I

SN74S225

I

J

tSee Bipolar Microcomputer Components Data Book, LCC4270.

1076

7-12

TEXAS I'oCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

MSI/LSI FUNCTIONS
FUNCTIONAL INDEX/SELECTION GUIDE
RANDOM-ACCESS READ-WRITE MEMORIES (RAM'SI

DESCRIPTION

ORGANIZATION

TYPE

TYPICAL TYPICAL

TYP POWER

DEVICE TYPE

OF

ADDRESS ENABLE

DISSIPATION

AND PACKAGE

OUTPUT

TIME

TIME

PER BIT

PAGE
NO.

aOc to 7aoC

-55°C to 125°C

1024-BIT ARRAYS

1024 X 1

3-State

65 ns

20 ns

0.2/0.07 mW

SN54LS215

JD

SN74LS215

JD,N

WITH POWER-DOWN

1024 X 1

O-C

65 ns

20 ns

0.2/0.07 mW

SN54LS315

JD

SN74LS315

JD,N

t

1024 X 1

3-State

65 ns

20 ns

0.2mW

SN54LS214

JD

SN74LS214

JD,N

t

1024 X 1

3-State

30 ns

15 ns

0.51 mW

1024 X 1

O-C

65 ns

20 ns

0.2mW

1024 X 1

O-C

30 ns

15 ns

0.51 mW

256 X4

3-State

60 ns

20 ns

0.3mW

256 X 4

3-State

40 ns

15 ns

0.59 mW

256 X4

3-State

60 ns

20 ns

0.3mW

256 X4

3-State

40 ns

15 ns

0.59 mW

256-BIT ARRAYS

256 Xl

3-State

35 ns

15 ns

1.1/0.39 mW

SN54LS202

WITH POWER-DOWN

256 Xl

O-C

35 ns

15 ns

1.1/0.39 mW

SN54LS302

~~

.~

1024-BIT ARRAYS

256-BIT ARRAYS

':>""'",, I

t

SN54S214

JD

SN74S214

JD,N

t

SN54LS314

JD

SN74LS314

JD,N

t

SN54S314

JD

SN74S314

JD,N

t

J, N

t
t

SN54LS207

J

SN74LS207

SN54S207

J

SN74S207

J, N

SN54LS208

J

SN74LS208

J, N

t

SN54S208

J

SN74S208

J, N

t

J,W

SN74LS202

J, N

t

J, W

SN74LS302
....... ....... ....

J, N

t

. ..
.. ... "'..................................
' o
~

H

L

ALL TYPES

'44A, 'L44
EXCESS-3-GRAY INPUT

= hIgh

level, L

I

: I:

j

I

:I

H

H

H

H

H

H

L

I-.

H

H

H

H

H

H

H

H

L

H

L

H

H

H

H

H

H

H

H

H

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

H

H

H

H

H

H

H

H

H

H

L

L

L

L

L

H

H

H

H

H

H

H

H

H

H

L

H

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

)76

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-15

I

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lit
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r+

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~ [TI
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'42A, 'L42, 'LS42
BCD-TO-DECIMAL DECODERS

"43A, 'L43
EXCESS-3-TO·DECIMAL DECODERS

'44A, 'L44
EXCESS-3-GRAY-TO-DECIMAL DECODERS

):II

II>

5.

o

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~~(IJ

zm t

3

3

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=
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en
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Z ~
a. tOr- ...... N
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::a

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m

en!i ~

~ ):II
I~ ..

~

""):lien
.!... .. Z

Cen~
-Z~

~~

~N

~-4

N::c
-4::a

::Cc

::a

~
(IJ

'42A THRU '44A
'L42 THRU 'L44
EQUIVALENT OF
EACH INPUT

vee3--

'LS42
EQUIVALENT OF
EACH INPUT

--

TYPICAL OF
ALL OUTPUTS

Vee

'LS42
TYPICAL OF
ALL OUTPUTS

Vee

17 kn. NOM

Req

INPUT

'42A THRU '44A
'L42 THRU 'L44

Cen
Z
en
Z~
...... ~
~~

t~
en
Z

INPUT
-OUTPUT

OUTPUT

~

i

N

'42A THRU '44A: Req
'L42 THRU 'L44: Req

s

~
~

4 kn. NOM
8 kn. NOM

'42A THRU '44A: R = 130 n. NOM
'L42 TH RU 'L44: R ~ 260 n. NOM

TYPES SN5442A, SN5443A, SN5444A, SN7442A, SN7443A, SN7444A
4-LlNE-TO-10-LlNE DECODERS (1-0F-10)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
...... .
I nput voltage . . . . . . .
...... .
Operating free·air temperature range: SN54' Circuits
SN74' Circuits
Storage temperature range

7V

5.5 V
-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

NOTE 1: Voltage values are with respect to netyvork ground terminal.

recommended operating conditions
SN7442A

SN5442A

MIN

SN5443A

SN7443A

SN5444A

SN7444A

NOM

4.5

Supply voltage, Vee
I

____ 1_. __ 1

_ ..... _ . • •

___

_ _.

UUlfJUlt,;urrt~lll,

MIN

5.5

4.75

NOM

MAX

5

-800

High-level output current, 10H
L.UVV-It;:Vt::1

MAX

5

UNIT

I

io

tOl

Operating free-air temperature, T A

-55

125

5.25

V

800

}.LA

16

mA
De

70

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

TEST CONDITIONSt

PARAMETER

SN5442A

SN7442A

SN5443A

SN7443A

MIN

UNIT

SN7444A

SN5444A
TYP:j: MAX

MIN

TYP:j: MAX

VIH

High-level input voltage

VIL

Low-level input voltage

ViK

!nput clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

Input current at maximum input voltage

Vee = MAX, VI = 5.5V

IIH

High-level input current

Vee= MAX, VI=2.4V

40

40

}.LA

IlL

Low level input current

Vee = MAX,

VI = 0.4 V

-1.6

-1.6

mA

lOS

Short-circuit output current §

Vee= MAX

-55

mA

lee

Supply current

Vee= MAX, See Note 2

56

mA

2

Vee = ~v~IN,

Ij=-12mA

Vee= MIN,

VIH = 2 V,

VIL = 0.8 V,

10H = -800}.LA

Vee = MIN,

VIH=2V,

VIL = 0.8V,

IOL=16mA

V

2
0.8

0.8

V

-1.5

-i.5

V

3.4

2.4

0.2

2.4
0.4

V

3.4
0.2

0.4
1

1

-55

-20
28

-18

41

28

V
mA

•

: For conditions shown as M IN or MAX, use t~e appropriate values specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25 e.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open and all inputs grounded.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

Propagation delay time, high-to-Iow-Ievel
tpHL

MIN

TYP

25

ns

17

30

ns

10

25

ns

17

30

ns

output from A, B, e, or D through 2 levels of logic
Propagation delay time, high-to-Iow-Ievel

tpHL

output from A, B, e, or D through 3 levels of logic
Propagation delay time, low-to-high-Ievel

tpLH

output from A,

B,

e, and D through 2 levels of logic

eL=15pF,
RL=400

NOTE 3:

output from A, B, e, and D through 3 levels of logic
Load

CirCUits

n,

See Note 3

Propagation delay time, low-to-high-Ievel
tPLH

MAX UNIT

14

and waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-17

TYPES SN54L42, SN54L43, SN54L44, SN74L42, SN74L43, SN74L44
4-LlNE-TO-10-LlNE DECODERS (1-0F-10)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V CC (see Note 1)
Input voltage . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54L' Circuits.
SN74L' Circuits
Storage temperature range

7V

5.5 V
-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54L42

SN74L42

SN54L43

SN74L43

SN54L44
MIN

NOM

4.5

Supply voltage, Vee

5

MIN

5.5

4.75

NOM
5

-400

High-level output current, 10H

8

Low-level output current, 10L
-55

Operating free-air temperature, T A

UNIT

SN74L44
MAX

125

0

MAX
5.25

V

-400

/lA

8

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER

•

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

MIN

TYPt

MAX UNIT
V

2
Vee = MIN,

II = -12 mA

Vee= MIN,

VIH = 2 V,

VIL = 0.8 V,

10H = -400JJA

Vce= MIN,

VIH = 2 V,

VIL = 0_8 V,

10L = 8mA

Input current at maximum input voltage

Vee= MAX,

VI=5.5V

2.4

0.8

V

-1.5

V

3.4
0.2

V
0.4
1

V
mA

IIH

High-level input current

Vec = MAX,

VI = 2.4 V

20

/lA

IlL

Low-level input current

Vec

= MAX,

VI = 0.4 V

-0.8

mA

lOS

Short-circuit output current §

Vee= MAX

-28

mA

lee

Supply Current

-9

I SN54L'

Vec - MAX,

14
14

I SN74L'

See Note 2

22
28

mA

tFor conditions shown as rv1:N or ~1AX, use the appropriate values specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°e.
§Not more than one output should beshorted at a time.
NOTE 2: Ice is measured with all outputs open and inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER

TEST CONDITIONS

I

Propagation delay time, high-to-Iow-Ievel
tpHL

output from A, B, e, or D through 2 levels of logic

MIN

TYP

10

44

60

ns

46

70

ns

J4

50

ns

52

70

ns

Propagation delay time, high-to-Iow-Ievel
tpHL

eL=15pF,

output from A, B, C, or D through 3 levels of logic

RL = 800

Propagation delay time, low-to-high-Ievel
tpLH

Propagation delay time, low-to-high-Ievel
tpLH

n,

See Note 3

output from A, B, e, and D through 2 levels of logic
output from A, B, e, and D through 3 levels of logic

MAX UNIT

10

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-18

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS42, SN74LS42
4-UNE-TO-l0-UNE DECODERS (1-0F-1O)
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS42
SN74LS42
Storage temperature range

7V
7V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS42
Supply voltage, Vee

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

-400

p.A

8

mA

-400

Low-level output current, 10L

4

Operating free-air temperature, T A

UNIT

NOM

High-level output current, 10H

I

SN74LS42

MIN

,-55

I":::'''''

C

70 I

o~

v

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL
VIK

Low-level input voltage

SN54LS42
MIN

TYP+

SN74LS42

MAX

2

Input clamp voltage

VOH High-level output voltage
VOL Lo\'\'!-!eve! output voltage
Input current at

Vee= MIN,

II = -18mA

Vee= MIN,

VIH=2V,

VIL=VILmax,IOH=-400p.A
Vec= MIN,

VIH=2V,

VIL = VIL max

2.5

TYP+

MAX

2

UNIT
V

0.7

0.8

V

-1.5

-1.5

V

3.5

2.7

0.25

\IOL=4mA

MIN

0.4

jlOL = 8 mA

3.5

V

0.25

0.4

0.35

0.5

V

Vee= MAX,

VI = 7 V

0.1

0.1

IIH

High-level input current

Vec= MAX,

VI = 2.7 V

20

20

p.A

IlL

Low-level input current

Vee= MAX,

VI = 0.4 V

-0.4

-0.4

mA

lOS

Short-circuit output current§

Vee = MAX

ICC

Supply current

Vee= MAX,

II

maximum input voltage

-100

-20
See Note 2

7

-20

13

I

I

mA

-100

mA

7

13

mA

TYP

MAX

15

25

ns

20

30

ns

15

25

ns

20

30

ns

II

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
0

tAli typical vah./es are at V C:C: = 5 V, T A = 25 C.
§ Not mOre than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2. ICC is measured with all outputs open and inputs grounded.

switching characteristics, Vee

= 5 V, T A = 25° C

PARAMETER

TEST CONDITIONS

MIN

Propagation delay time, high-to-Iow-Ievel
tPHL

output from A, B, e, or 0 through 2 levels of logic
Propagation delay time, high-to-Iow-Ievel

tPHL

eL = 15 pF,

output from A, B, e, or 0 through 3 levels of logic

RL = 2 kn,

Propagation delay time, low-to-high-Ievel
tPLH

See Note 4

output from A, B, e, and 0 through 2 levels of logic
Propagation delay time, low-to-high-Ievel

tpLH

UNIT

output from A, B, e, and 0 through 3 levels of logic

NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

TEXAS INSTRUMENTS
II'
:!::

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

A RAM
... _._.ET_
..

VIH
VIL

Low-level input voltage

VIK

Input clamp voltage

Va (on)
I a (off)

.reT

(

r-nMruT.,"U\U:.. t

....... """"n""""VI ... ,,-

I •.

no

IVIII~

._+

_

11'1"'+

u
t Ui\iiliviAA

2

High-level input voltage

On-state output voltage

Vee = MIN,

11=-12mA

Vce= MIN,

VIH = 2 V,

VIL=0.8V
Vee = MIN, VIH=2V,

Off-5tate output current

I

0.5

IO(on) = 80 mA

1

0.8

V

-1.5

V

0.9

V

0.4

IO(on) = 20 mA

VIL = 0.8 V, Va (off) = 30 V

250

IlA

II

Input current at maximum input voltage

Vce= MAX,

VI=5.5V

1

mA

IIH

High-level input current

Vee = MAX, VI = 2.4 V

40

IlA

IlL

Low-level input current

IVee= MAX, VI-OAV

lee

Supply current

Vee = MAX, See Note 2

-1.6 I mA

I

I
I

i

V

SN5445

43

SN7445

43

62
70

I

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type .
:j:AII typical values are at V CC = 5 V, T A = 25°C.
NOTE 2: ICC is measured with all inputs grounded and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

I

I tpLH
I tpHL

TEST CONDITIONS

PARAMETER
Propagation delay time, low-to-high-Ievel output

eL=15pF,

Propagation delay time, high-to-Iow-Ievel output

See Note 3

RL=100n,

I MIN

TYP

I
I

I

MAX UNIT
50
50

I
I

•

ns
ns

NOTE 3: Load circuit and waveforms are shown on page 3-10.

schematics of inputs and outputs
EQUIVALENT OF ALL INPUTS

TYPICAL OF ALL OUTPUTS

Vcc--____- .______

INPUT

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-21

TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74 LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
BULLETIN NO. DL-S 7611811. MARCH 1974-REVISED OCTOBER 1976

'46A, '47A, 'L46, 'L47, 'LS47
feature

'48, 'LS48
feature

'49, 'LS49
feature

•

Open-Collector Outputs
Drive Indicators Directly

•

Internal Pull-Ups Eliminate
Need for External Resistors

•

Lamp-Test Provision

•

Lamp-Test Provision

•

Leading/Trailing Zero
Suppression

•

Leading/Trailing Zero
Suppression

•

Open-Collector Outputs

•

Blanking Input

All Circuit Types Feature Lamp Intensity Modulation Capability
DRIVER OUTPUTS

TYPICAL

ACTIVE

OUTPUT

SINK

MAX

POWER

LEVEL

CONFIGURATION

CURRENT

VOLTAGE

DISSIPATION

SN5446A

low

open-collector

40mA

30V

320mW

SN5447A

low

open-collector

40mA

l5V

320mW

J,W

SN5448

high

2-k!"! pull·up

6.4mA

5.5 V

265mW

J,W
W

TYPE

•

•

PACKAGES
J,W

SN5449

high

open-collector

10mA

5.5 V

l65mW

SN54L46

low

open-collector

20mA

30V

160mW

J

SN54L47

low

open-collector

20mA

l5V

l60mW

J

l2mA

l5V

35mW

J,W

2mA

5.5 V

l25mW

J,W
J,W

SN54LS47

low

open-collector

SN54LS48

high

2-kn pull-up

SN54LS49

high

open-collector

4mA

5.5 V

40mW

SN7446A

low

open-collector

40mA

30V

320mW

J, N

SN7447A

low

open-collector

40mA

l5V

320mW

J, N

SN7448

high

2-k!"! pull-up

6.4mA

5.5V

265mW

J, N

SN74L46

low

open-collector

20mA

30V

l60mW

J, N

SN74L47

low

open-collector

20 mA

l5V

l60mW

J, N

SN74LS47

low

open-collector

24mA

15V

35mW

J,N

SN74LS48

high

2-k!"! pull-up

6mA

5.5 V

l25mW

J, N

SN74LS49

high

open-collector

SmA

5.5V

40mW

J, N

'46A, '47 A, 'L46, 'L47, 'LS47
(TOP VIEW)

'48, 'LS48
(TOP VIEW)

'49, 'LS49
(TOP VIEW)

O<.rTPtJTS
r -_ _ _ _ _ _~A~________,

~BT.
PUT

:~
PUT

INPUTS

positive logic: see function tables

1076

7-22

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74LS47, 'LS4~, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
description
The '46A, 'L46, '47A, 'L47, and 'LS47 feature active-low outputs designed for driving common-anode VLEDs or
incandescent indicators directly, and the '48, '49, 'LS48, 'LS49 feature active-high outputs for driving lamp buffers or
common-cathode VLEDs. All of the circuits except '49 and 'LS49 have full ripple-blanking input/output controls and a
lamp test input. The '49 and 'LS49 circuits incorporate a direct blanking input. Segment identification and resultant
displays are shown below. Display patterns for BCD input counts above 9 are unique symbols to authenticate input
conditions.
The '46A, '47A, '48, 'L46, 'L47, 'LS47, and 'LS48 circuits incorporate automatic leading and/or trailing-edge
zero-blanking control (RBI and RBO). Lamp test (LT) of these types may be performed at any time when the BI/RBO
node is at a high level. All types (including the '49 and 'LS49) contain an overriding blanking input (BI) which can be
used to control the lamp intensity by pulsing or to inhibit the outputs. Inputs and outputs are entirely compatible for
use with TTL or DTL logic outputs.
The SN54246/SN74246 through '249 and the SN54LS247/SN74LS247 through 'LS249 compose the 5 and
the 9 with tails and have been designed to offer the designer a choice between two indicator fonts. The
SN54249/SN74249 and SN54LS249/SN74LS249 are 16-pin versions of the 14-pin SN5449 and 'LS49. Included in the
'249 circuit and 'LS249 circuits are the full functional capability for lamp test and ripple blanking, which is
not available in the '49 or 'LS49 circuit.
a

II .J

I-I

tl 9 Ib
1--1
el IC

Ii il
3

-d-

4

5

6

8

9

iO

11

i2

13

14

15

NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS

SEGMENT
IDENTIFICATION
'46A, '47A, 'L46, 'L47, 'LS47 FUNCTION TABLE
DECIMAL

INPUTS

OR
FUNCTION

LT

RBI

0

H

1

H

2

C

B

H

L

L

L

L

H

X

L

L

L

H

H

H

X

L

L

H

L

H

3

H

X

L

L

H

H

4

H

X

L

H

L

5

H

X

L

H

6

H

X

L

= pigh

NOTi=S:

A

a

b

c

d

NOTE

e

f

ON

ON

ON

ON

ON

9
OFF

ON

ON

OFF

OFF

.oFF

OFF

ON

ON

OFF

ON

ON

OFF

ON

H

ON

ON

ON

ON

OFF

OFF

ON

L

H

OFF

ON

ON

OFF

OFF

ON

ON

L

H

H

ON

OFF

ON

ON

OFF

ON

ON

H

H

L

H

OFF

OFF

ON

ON

ON

ON

ON

ION
OFF

7

H

X

L

H

H

H

H

ON

ON

ON

OFF

OFF

OFF

OFF

8
9

H

X

H

L

L

L

H

ON

ON

ON

ON

ON

ON

ON

H

X

H

L

L

H

H

ON

ON

ON

OFF

OFF

ON

ON

10

H

X

H

L

H

L

H

OFF

OFF

OFF

ON

ON

OFF

ON

11

H

X

H

L

H

H

H

OFF

OFF

ON

ON

OFF

OFF

ON

12

H

X

H

H

L

L

H

OFF

ON

OFF

OFF

OFF

ON

ON

13

H

X

H

H

L

H

H

ON

OFF

OFF

ON

OFF

ON

ON

14

H

X

H

H

H

L

H

OFF

OFF

OFF

ON

ON

ON

ON

15

H

X

H

H

H

H

H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

BI

X

X

X

X

X

X

L

OFF

OFF

OFF

OFF

OFF

OFF

OFF

2

RBI

H

L

L

L

L

L

L

OFF

OFF

OFF

OFF

OFF

OFF

OFF

3

X

X

X

X

X

H

ON

ON

ON

ON

ON

ON

ON

4

L

LT
H

OUTPUTS

BI/RBOt

D

level, L

= low

level, X

1

•

= irrelevant

1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired.

2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are off regardless of the level of any
other input.

3. When ripple·blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp test input high, ali segment outputs
go off and the ripple·blanking output (RBO) goes to a low level (response condition)'
4. When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, ali
segment outputs are on.
tBI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-23

TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
'48, 'LS48
FUNCTION TABLE
DECIMAL
OR
FUNCTION
0
1
2
3

4
5
6
7

8
9
10
11
12
13
14
15
BI
RBI
LT

INPUTS
LT
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
L

RBI
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X

OUTPUTS

BI/RBOt

D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
L

C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
L

B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
L

X

X

X

A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
L
X

a
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H

c

b
H
H
H
H
H
L
L
H
H
H
L
L
H
L
L
L
L
L
H

H
L
H
H
L
H
L
H
H
H
L
L
L
H
L
L
L
L
H

H
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
H

NOTE

e

d
H
L
H
H
L
H
H
L
H
L
H
H
L
H
H
L
L
L
H

f
H
L
L
L
H
H
H
L
H
H
L
L
H
H
H
L
L
L
H

H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
L
L
L
H

9
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
H

1

2
3
4

H = high level, L = low level, X = irrelevant
NOTES: 1. The blanking input (61) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (R61) must be open or high, if blanking of a decimal zero is not desired,
2. When a low logic level is applied directly to the blanking input (61). all segment outputs are low regardless of the level of any
other input.

3. When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp-test input high, all segment outputs
go low and the ripple-blanking output (RBO) goes to a low level (response condition!'
4. When the blanking input/ripple-blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, all
segment outputs are high.

t 61/RBO is wire-AN D logic serving as blanking input (61) and/or ripple·blanking output (R60).

•

'49, 'LS49
FUNCTION TABLE
DECIMAL
OR
FUNCTION

C

0

L

L

1
2
3
4
5
6

9
10
11
12
13
14
15

L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

BI

X

L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X

7

8

OUTPUTS

INPUTS
D

B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X

NOTE
A
BI
L ' H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
X

a

'H
L
H
H
L
H
L
H
H
H
L
L
L

H
L
L
L

b
H
H
H
H
H
L
L
H

H
H
L
L
H
L
L
L
L

c
H

H
L
H
H
H
H

H
H
H
L
H
L
L
L
L
L

d
H
L
H
H
L
H
H
L
H
L
H
H
L
H
H
L
L

e

f

H
L

H

L

L
L
L
H
H
H
L
H
H
L
L

L
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L

H
L
L
L
H
L
H
L
H
L
L
L
H
L
L

H
H
H
L
L

9

1

2

H = high level, L = low level, X = irrelevant
NOTES: 1. The blanking input (61) must be open or held at a high logic level when output functions 0 through 15 are desired.
2. When a low logic level is applied directly to the blanking input (61), all segment outputs are low regardless of the level of any
other input.

374

7-24

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, 'LS49,
SN7446A, '47A, '48, SN74L46, 'L47, SN74LS47, 'LS48, 'LS49
BCD-TO -SEVEN -SEGM ENT DECO DERS/D RIVE RS
functional block diagrams
'46A, '47A, 'L46, 'L47, 'LS47

'48, 'LS48

BLANKING

RIPP~P!~~ING

RIPPLEi~~KING ..>:(5"-}--Lf-_-_-_-_~

_____

__l._./

'49, 'LS49

•

374

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-25

TYPES SN5446A, '47A, '48, '49, SN54L46, 'L47,
SN7446A, '47A, '48, SN74L46, 'L47
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
schematics of inputs and outputs
'46A, '47A, '48, '49, 'L46, 'L47

Q

EQUIVALENT OF EACH INPUT
EXCEPT BI/RBO

vee

'46A, '47A, '48

'L46, 'L47

EQUIVALENT OF BI/RBO

EQUIVALENT OF BI/RBO

Req

INPUT

Vee

Vee
2.4 kn

6 kn

NOM

NOM

--

SN54'/SN74': Req
SN54L'/SN74L':

Req

=6

kn NOM

=8

kn NOM

'46A, '47A

'L46, 'L47

TYPICAL OF OUTPUTS
aTHRU 9

TYPICAL OF OUTPUTS
a THRU 9

----------~~~~---vee

----------~~-------Vee

OUTPUT

OUTPUT

•
'48

'49
TYPICAL OF ALL OUTPUTS

TYPICAL OF OUTPUTS
a THRU 9

----------~~----vec

----------~.---~~vee

2kn
NOM
OUTPUT

OUTPUT

374

7-26

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES .SN54LS47, 'LS48, 'LS49, SN74LS47, 'LS48, 'LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
schematics of inputs and outputs
'LS47, 'LS48, 'LS49

'LS47, 'LS48, 'LS49

_-

EQUIVALENT OF BI/RBO

EQUIVALENT OF EACH INPUT
EXCEPT BI/RBO

vee

q

Req

INPUT

Vee

--

L T and RBI ('LS47, 'LS48): Req = 20 kn NOM
0

,....

_ _ .....

r""I......
_ .....
L.,.I.
neq - "::::0
r-

I.r">.

r;,..),{,

10 kn

NOM

NOM

BI/RBO----'

BI ('LS49): Req = 20 kn NOM
1\

_. c, v, allU

20 kn

&,_ ...
I"IIUIVI

'LS47

'LS48

TYPICAL OF OUTPUTS
a THRU 9

TYPICAL OF OUTPUTS
a THRU 9

-------.--~--vee

OUTPUT

•
'LS49
TYPICAL OF OUTPUTS
a THRU 9

-------.----vee

OUTPUT

374

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-27

TYPES SN5446A. SN5447A. SN7446A. SN7447A
BCD-TO-SEVEN-SEGM ENT 0 ECODERS/DR IVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . .
Input voltage . . . . . . .
.... .
Current forced into any output in the off state
Operating free-air temperature range: SN5446A, SN5447A
SN7446A, SN7447A
Storage temperature range

7V
5.5V
1 mA
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

4.5

Supply voltage, Vee

NOM MAX
5

SN7446A

SN5447A

SN5446A
MIN

MIN
4.5

5.5
30

NOM MAX
5

MIN

SN7447A

NOM MAX

5.5 4.75

MIN

5.25 4.75

5

NOM MAX
5

30

15

UNIT

5.25

V

15

V
rnA

Off-state output voltage, VO(off)

a thru g

On-state output current, 10(on)

a thru g

40

40

40

40

High-level output current, 10H

BI/RBO

-200

-200

-200

-200

!LA

Low-level output current, 10L

BI/RBO

8

8

8

8

rnA

70

°e

Operating free-air temperature, T A

125

-55

-55

125

70

0

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER

•

MIN

TYP+ MAX UNIT
V

2

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

BI/RBO

VOL

Low-level output voltage

BI/RBO

10 (oft) Off-state output current

a thru g

VO(on) On-state output voltage

a thru g

II

Input current at maximum input voltage

IIH

High-level input current

Vee = MIN,

II =-12mA

Vee= MIN,

VIH = 2V,

VIL = 0.8 V,

10H = -200 !LA

Vee=MIN,

VIH=2V,

VIL = 0.8 V,

10L = 8mA

2.4

v.

0.27

VO(off) = MAX

Vee = MAX. VIH=2V,
VIL = 0.8 V,

Any input
except B I/R BO
Any input

except B I/R BO

0.3

10(on) = 40 rnA

Low-level input current

ICC

Short-circuit output current

V
0.4

V

250

!LA

0.4

V

1

rnA

= 2.4 V

40

!LA

VCC= MAX, VI

-1.6

except BI/RBO

rnA

Vee= MAX. VI = 0.4 V
--4

BI/RBO
lOS

V

Vee = MAX. VI=5.5V

Any input
IlL

V

-1.5
3.7

Vee = MAX, VIH = 2V,
VIL = 0.8

0.8

BI/RBO

--4

Vee= MAX
Vee = MAX,

Supply current

See Note 2

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended
+AII typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

l

l

SN54'

64

85

SN74'

64

103

rnA
rnA

operatin~ conditions.

switching characteristics, Vee = 5 V, T A = 25°e
TEST CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT
100

toff

Turn-off time from A input

ton

Turn-on time from A input

eL = 15pF.

toft

Turn-off time from RBI input

See Note 3

ton

Turn-on time from RBI input

RL = 120

n.

100
100
100

ns
ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10; toff corresponds to tpLH and ton ·corresponds to tpH L'

1076

7·28

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54L46, SN54L47, SN74L46, SN74L47
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage . . . . . . . . . . . . . . .
Peak output current (tw ~ 1 ms, duty cycle ~ 10%)
Current forced into any output in the off state
Operating free-air temperature range: SN54L46, SN54L47
SN74L46, SN74L47
Storage temperature range

7V

5.5 V
200 rnA
.

1 rnA

-55°C to 125°C
0
O°C to 70 e
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54L47

SN54L46
MIN
4.5

Supply voltage, Vee

NOM MAX
5

MIN

5.5

SN74L46

NOM MAX

4.5

5

5.5

MIN
4.75

SN74L47

NOM MAX
5

MIN
4.75

5.25

NOM MAX
5

5.25

UNIT
V

Off-state output voitage, VO(off)

a thru g

30

i5

30

15

V

On-state output current, 10(on)

a thru g

20

20

20

20

rnA

High-level output current, 10H

BI/RBO

-100

-100

-100

-100

J.LA

Low-level output current, 10L

BI/RBO

4

4

4
'7n
.....

1"\ ...............+: ...... -'=_............. : ...
I '"'
.... c:laull~ l i c e - a i l

+ ......................... + .........

LCllltJCIQLII.oIIt;;,

T_

'A

I

....~
-"'"

1

" I -""

.2",

oJoJ

1

"!

.2....

n

4 rnA
or
'7n
...... ,

n

I

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

VOH

TYP+ MAX UNIT

2
Any input
except BI/RBO
BI/RBO

High-level output voltage

VOL

Low-level output voltage

BI/RBO

10(off)

Off-state output current

a thru g

VO(on)

MIN

On-state output voltage
Input current at maximum input voltage

IIH

High-level input current

11= -12 rnA

Vee - MIN,

VIH - 2 V,

VIL = 0.8 V,

10H = -100 iJ.A

Vee = MIN,

VIH=2V,

V!L=0.8V,

10L =4 rnA

2.4

VIL = 0.8 V,
VIL = 0.8 V,

except BI/RBO
Any input
except BI/RBO

Low-level input current

0.3

10(on) = 20 rnA

lee

Short-circuit output cu rrent

0.4

V

250

iJ.A

0.4

V

Vee = MAX, VI = 5.5 V

1

rnA

Vee = MAX, VI = 2.4 V

20

iJ.A

-0.8

except BI/RBO Vee = MAX, VI = 0.4 V

•

rnA

-2

BI/RBO
lOS

V

VO(off) = MAX

Any input
IlL

V

3.4
0.2

Vee - MAX, VIH-2V,

Any input

V

-1.5

I

Vee - MAX, VIH-2V,

a thru g

II

Vee = MIN,

V
0.8

BI/RBO

-2

Vee = MAX

Supply current

Vee - MAX,

ISN54L'

32

43

See Note 2

ISN74L'

32

52

rnA
rnA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, TA = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5

switching characteristics,

v.

Vee = 5 V, T A = 25° C
TEST CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT
200

toff

Turn-off time from A input

ton

Turn·on time from A input

CL=15pF,

toff

Turn-off time from RBI input

See Note 3

ton

Turn-on time from RBI input

RL = 280

n,

200
200
200

ns
ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10; toft corresponds to tpLH and ton corresponds to tpHL'

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-29

TYPES SN54LS47, SN74LS47
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
...... .
Input voltage . . . . . . . . . . . . . . .
Peak output current (tw <; 1 ms, duty cycle <; 10%)
Current forced into any output in the off state
Operating free-air temperature range: SN54LS4 7
SN74LS47
Storage temperature range

7V
7V

200mA
. . . . 1 mA
-55°C to 125°C
. O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS47
MIN
Supply voltage, Vee

4.5

NOM

SN74LS47

MAX

MIN

NOM

5.5

4.75

5

5

V

15

V

12

24

mA

-50

-50

p.A

3.2

mA

70

°e

a thru g

On-state output current, 10(on)

a thru g

High-level output current, 10H

BI/RBO

Low-level output current, 10L

BI/RBO

1.6

15

-55

UNIT

5.25

Off-state output voltage, VO(off)

Operating free-air temperature, T A

MAX

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

SN54LS47

TEST eONDITIONSt

MIN

High-level input voltage

•

TVP:\:

MIN

MAX

SN74LS47
TV!>:\: MAX UNIT

2

VIL

Low-level input voltage

VIK

Input clamp VOltage

VOH

High-level output voltage BI/RBO

VOL

Low-Ieveloutputvoltage BI/RBO

10(off)

Off-state output current

a thru 9

Va (on)

On-state output voltage

a thru 9

V

II =-18mA

Vee= MIN,

2.4

0.7

0.8

-1.5

-1.5

4.2

2.4

4.2

VIH = 2 V,

250

VIL = VIL max, VO(off) = 15 V

V

V

Vee = MIN,
\IOL = 1.6 mA
0.25
0.25
0.4
0.4
VIH = 2 V,
1------+-------+--------1
0.5
VIL = VIL max IIOL = 3.2 mA
0.35
Vee = MAX,

V

250

V

p.A

l

, I,

Input current

at maxim m inout

Vee- MAX '
0.25
10(on) = 12 mA
0.4
0.25
0.4
VIH = 2 V,
1------+-------+--------1
0.5
VIL = VIL max 110(on) = 24 mA
I
0.35

voltage

High-level input current

V f'f'

= MAX

V = 7V

Vee = MAX,

VI = 2.7 V

Any input
Low-level input current

except BI/RBO Vee

= MAX,

VI = 0.4 V

BI/RBO
Short-circuit
lOS
lee

output current

BI/RBO

-0.3

Vee = MAX

Supply current

Vee

= MAX,

See Note 2

V

0 1

I

01

mA

20

I

20

p.A

-0.4

-0.4

-1.2

-1.2

-2

-0.3

13

mA

-2

mA

13

rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:\: All typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER

TEST eONDITIONS

MIN

TVP

MAX UNIT

toff

Turn-off time from A input

ton

Turn-on time from A input

eL=15pF, RL=665n,

100

toft

Turn-off time from RBI input

See Note 4

100

ton

Turn-on time from RBI input

NOTE 4:

100

100

ns
ns

Load circuit and voltage waveforms are shown on page 3-11; toft corresponds to tpLH and ton corresponds to tpHL'

107

7-30

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN5448, SN7448
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
.... .
Operating free-air temperature range: SN5448
SN7448
Storage temperature range

7V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN5448
MIN
4.5

Supply voltage, Vee
High-!eve! output current, tOH

Low-level output current, 10L

SN7448

NOM MAX
5

MIN

5.5 4.75

NOM MAX
5

5.25

a thru g

-400

-400

BI/RBO

-200

-200

a thru g

6.4

6.4

R!/RRO

8
-55

Operating free-air temperature, T A

8

125

0

70

UNIT
V

j.i.,A
rnA
°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

10

Output current

VOL

Low-level output voltage

TEST eONDITIONSt

MIN

TYP+ MAX UNIT
V

2
Vee = MIN,

11=-12mA

a thru g

Vee = MIN,

VIH=2V,

2.4

4.2

BI/RBO

VIL = 0.8 V,

10H = MAX

2.4

3.7

Vee = MIN,

Vo = 0.85 V,

-1.3

-2

a thru g

II

Input current at maximum input voltage

IIH

High-level input current

Input conditions as for VOH

Any input
except BI/RBO
Any input
except BI/RBO

Vee = MIN,

VIH=2V,

VIL=0.8V,

10L = MAX

0.27

Low-level input current

ICC

Short-circuit output current

V
V
rnA

0.4

V

1

rnA

Vee = MAX, VI = 2.4 V

40

Il A

-1.6

except BI/RBO Vee = MAX, VI = 0.4 V
BI/RBO

lOS

V

-1.5

Vee = MAX, VI = 5.5 V

Any input
IlL

0.8

I

•

mA

-4

BI/RBO

-4

Vee = MAX
Vee - MIN,

Supply current

See Note 2

LSN5448

I SN7448

53

76

53

90

rnA
rnA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operatrng conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
NOTE 2: lee is measured with all outputs open and all inputs at 4.5 V"

switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER

TEST CONDITIONS

tPHL

Propagation delay time, high-to-Iow-Ievel output from A input

tPLH

Propagation delay time, low-to-high-Ievel output from A"input

eL=15pF,

tPHL

Propagation delay time, high-to-Iow-Ievel output from RBI input

See Note 5

tpLH

Propagation delay time, low-to-high-Ievel output from RBI input

MIN

TYP

MAX UNIT
100

RL = 1 kn,

100
100
100

ns
ns

NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-31

TYPES SN54lS48, SN74lS48
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . . . . . . . . .
Operating free·air temperature range: SN54LS48
SN74LS48
Storage temperature range

7V
7V

... ,

-55°C to 125°C
. oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74LS48

SN54LS48
MIN

NOM

4.5

Supply voltage, Vee
High-level output current, 10H
Low-level output current, 10L

MAX

MIN

NOM

5.5

4.75

5

5

5.25

a thru 9

-100

-100

BI/RBO

-50

-50

a thru 9

2

6

BI/RBO

1.6
-55

Operating free-air temperature, T A

125

UNIT

MAX

V
IlA
mA

3.2
0

°e

70

electrical characteristiCS over recommended operatmg free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

10

•

Output current

Vee= MIN,

11=-18mA

a thru g and

Vee= MIN,

VIH=2V,

BI/RBO

VIL = VIL max, 10H = MAX
Vee = MIN,

a thru 9

Vo = 0.85 V,

Input conditions as for VOH

SN74LS48

MAX

MIN

TYP+

V

-1.5

V

-1.3

-2

-1.3

-2

rnA

0.25

0.4

0.25

0.4

0.35

0.5

0.25

10L = 1.6 mA

0.4

0.25

0.4

0.35

0.5

V

VIH = 2 V,

Any input

maximum input voltage

except BI/BRO

High-ieve; input current ' Any input

except BI/RBO

10L = 3.2mA

Vee = MAX,

'''~ ~ ~'A Y!
Yl,;C

••

",

VI = 7 V
VI=2.7V

except BI/RBO Vee= MAX,

VI = 0.4 V

BI/RBO

lee

output current

V

4.2

V

Vec- MIN,

Input current at

Short-circuit

-1.5
2.4

0.1

0.1

20

20

-0.4

-0.4

-1.2

-1.2

Any input

lOS

V

4.2

10L = 6 mA

VIL = VIL max

Low-level output voltage

Low-level input current

0.8

2.4

10L = 2mA

VIL = VIL max

IlL

UNIT

MAX

2

VIH=2V,

BI/RBO

ilH

TYP+

0.7

Vee= MIN,

II

MIN
2

a thru 9
VOL

SN54LS48

TEST CONDITIONSt

BI/RBO

-0.3

Vee= MAX

Supply current

Vee= MAX,

See Note 2

-2
25

-0.3

38

25

mA

i

jlA

mA

-2

mA

38

rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V. T A 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee

= 5 V, T A = 25° C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

tpHL

Propagation delay time, high-to-Iow-Ievel output from A input

eL=15pF,

tPLH

Propagation delay time, low-to-high-Ievel output from A input

See Note 6

100

tpHL

Propagation delay time, high-to-Iow-Ievel output from RBI input

eL-15pF, RL-6kn,

100

tpLH

Propagation delay time, low-to-high-Ievel output from RBI input

See Note 6

100

RL = 4 kn,

100

ns
ns

NOTE 6: Load circuit and voltage waveforms are shown on page 3-11.

1071

7-32

TEXAS I!,;COHPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

D,4.LLAS. TEXAS 75222

TYPE SN5449
BCD-TO-SEVEN-SEGMENT DECODER/DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage . . . . . . . .
Current forced into any output in the off state
Operating free-air temperature range
Storage temperature range

7V

5.5 V
1 mA

-55°C to 125°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN5449
Supply voltage, Vee

NOM

MAX

4.5

5

5.5

V

5.5

V

10

mA

125

°e

High-level output voltage, VOH
Low-level output current, IOL
Operating free-air temperature, T A

UNIT

MIN

-55

------- --------

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

TEST CONDITIONSt

SN5449
MIN

TYP:j:

MAX

UNIT
V

2

V

0.6

VIK

Input clamp voltage

IOH

High-level output current

I VOL

Low-level output voltage

Vee - MIN,

11--10mA

Vee- MIN,

VIH - 2 V,

VIL=0.8V,

VOH = 5.5 V

Vee= MIN,

VIH=2V,

ViL = 0.8 V,

!OL

0.27

= 10 mA

II

Input current at maximum input voltage

Vee = MAX, VI = 5.5 V

-1.5

V

250

p.A

0.4
1

1

V

IIH

High-level input current

Vee - MAX, VI - 2.4 V

40

p.A

IlL

Low-level input current

Vee - MAX,

VI-O.4V

-1.6

mA

lee

Supply current

Vee = MAX, See Note 2

33

47

mA

TYP

MAX

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
fAil typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee

=

5 V, T A = 25°e

PARAMETER

TEST eONDITIONS

tPHL

Propagation delay time, high-to-Iow-Ievel output from A input

tpLH

Propagation delay time, low-to-high-Ievel output from A input

eL=15pF,

tPHL

Propagation delay time, high-to-Iow-Ievel output from RBI input

See Note 5

tPLH

Propagation delay time, low-to-high-Ievel output from RBI input

MIN

100
RL=667n,

100
100
100

I

mA

•

UNIT
ns
ns

NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS
I~CORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-33

TYPES SN54LS49, SN74LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SUl?ply voltage, V cc (see Note 1) . . . . .
Input voltage . . . . . . . . . . . . . . .
Curr.!'lnt forced into any output in the off state
Operating free-air temperature range: SN54LS49
SN74LS49
Storage temperature range

7V
7V
. . . . 1mA
-55°C to 125°C
. O°C to 70°C
_65° C to 150° C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS49
MIN
Supply voltage, Vee

4.5

NOM

SN74LS49

MAX

MIN

NOM

5.5

4.75

5

5

High-level output voltage, VOH

MAX

5.5

Low-level output current, IOL

4
-55

Operating free-air temperature, T A

125

0

UNIT

5.25

V

5.5

V

8

rnA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

,

SN54LS49

TEST CONDITIONSt

PARAMETER

MIN

TYP:!:

Input clamp voltage

•

11= -18mA

Vee = MIN,
Vee = MIN,

High-level output current

MIN

TYP:!:

MAX UNIT

2

Low-level input voltage

ICC

MAX

2

High-level input voltage

IOH

SN74LS49

VIL = VIL max, VOH = 5.5 V

V

0.7

0.8

V

-1.5

-1.5

V

250

250

IJ.A

Low-level output voltage

Vee = MIN,
IIOL = 4 rnA
0.25
0.4
0.25
0.4
VIH = 2 V,
If------+--------+---------l
VIL = VIL max
IOL = 8 rnA
0.35
0.5

Input current at maximum input voltage

Vee = MAX,

VI = 7 V

0.1

High-level input current

Vee = MAX,

VI = 2.7 V

20

Low-level input current

Vee = MAX,

VI = 0.4 V

Supply current

Vec = MAX,

See Note 2

-0.4

8

8

15

V

0.1

rnA

-0.4

rnA

15

rnA

tFor conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is meastJred with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee = 5 V T A = 25° C
1

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

tpHL

Propagation delay time, high-to-Iow-Ievel output from A input

CL = 15pF, RL=2kn,

100

tpLH

Propagation delay time,low-to-high-level output from A input

See Note 6

100

tpHL

Propagation delay time, high-to-Iow-Ievel output from RBI input

CL = 15 pF"

tPLH

Propagation delay time, low-to-high-Ievel output from RBI input

See Note 6

RL=6kn,

100
100

ns
ns

NOTE 6: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-34

TEXAS

INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN5475. SN5477. SN54L75. SN54Ln. SN54LS75. SN54LS77.
SN7475. SN74L75. SN74L77. -SN74LS75
4-BIT BISTABLE LATCHES
BULLETIN NO. DL-S 7611851, MARCH 1974-REVISED OCTOBER 1976

TTL
MSI

SN5475, SN54LS75 ••• J OR W PACKAGE
SN54L75. _ . J PACKAGE
SN7475, SN74L75, SN74LS75 •.. J OR N PACKAGE
(TOP VIEW)

logic
FUNCTION TABLE

(Each Latch)
INPUTS

OUTPUTS

D

G

a

a
H

L

H

L

H

H

H

L

X

L

00

00

10

H = high level, L = low level, X = irrelevant
00 = the level of 0 before the high-to-Iow transition of G

20

20

ENABLE
1·2

30

GNO

30

40

G

Q

description

Q

~I
I ~I~Hz~H~~

These latches are ideally suited for use as temporary
storage for binary information beiween processing
units and input/output or indicator units. Information present at a data (0) input is transferred to the Q
output when the enable (G) is high and the Q output
will follow the data input as long as the enable
remains high. When the enable goes low, the information (that was present at the data input at the time
the transition occurred) is retained at the Q output
until the enable is permitted to go high.

I

10

10

20

ENABLE

vee

3-4

logic: see function table
SN54ii, SN54LS77 ... W PACKAGE
SN54L77, SN74L77 ... T PACKAGE
10

ENABLE
1-2

20

GND

NC

30

40

~

The '75, 'L75, and 'LS75 feature complementary Q
and Q outputs from a 4-bit latch, and are available in
various 16-pin packages. For higher component
density applications, the '77, 'L77, and 'LS77 4-bit
latches are available in 14-pin flat packages.

I

•

These circuits are completely compatible with all
popular TTL or DTL families. All inputs are diodeclamped to minimize transmission-line effects and
simplify system design. Series 54, 54L, and 54LS
devices are characterized for operation over the full
military temperature range of -55°C to 125°C;
Series 74, 74L, and 74LS devices are characterized
for operation from O°C to 70°C.

1D

2D

ENABLE
3·4

Vcc

3D

4D

NC

logic: see function table
NC-No internal connection

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage: '75, 'L75, '77, 'L77
'LS75, 'LS77
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54', SN54L', SN54LS' Circuits
SN74', SN74L', SN74LS' Circuits
Storage temperature range
NOTES:

7V
5.5 V
7V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter input transistor and is not applicable to the 'LS75 and 'LS77.

076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DAL.LAS. TEXAS 75222

7-35

TYPES SN5475, SN5477, SN54L75, SN54Ln, SN54LS75, SN54LS77,
SN7475, SN74L75, SN74Ln, SN74LS75
.
4-BI1 BISTABLE LATCHES·
REVISED OCTOBER 1976

functional block diagrams (each latch)
'75,77, 'L75, 'L77

----~

(12}[21

B1

(13)[3)

B2

(1) [5)

B*

(2)[6]

BC

(3)[7)

en

~

schematic
(3) [7]
n

e _
Vee (14) [4]

(4)[8]
JO-.....- - - ' - - - - Cn+1

_
_

A1 (8)[12]

W1
I

~~lk
_

~
'V'

~~ ~

I

I

1

130

1

A2 (9)[13] I0Il

(4)[8] _
~-_-------en+1

(10)[14]
A*

(11)[1]

Ae -'---'-'---14--'
4k

•

B1 (12)[2]

B2 (13)[3]

B* (1)[5]

Be

(2)[6]

(7)[11]

GND------~

9- ..

Vee bus

Resistor values shown are nominal and in ohms.

1272

TEXAS)NSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-43

TTL
MSI

TYPES SN5481A. SN5484A. SN1481A. SN1484A
16-81T RANDOM-ACCESS MEMORIES
BULLETIN NO. DL-S 7211581, DECEMBER 1972

description
Each of these 16-bit active-element memories is a
high-speed, monolithic, transistor-transistor-Iogic
(TTL) array of 16 flip-flops and two write amplifiers
interconnected to form a scratch-pad memory with
direct-address and nondestructive read-out. These
devices are interchangeable with and replace SN5481,
SN7481, SN5484, and SN7484, but feature
diode-clamped inputs, improved switching speeds,
and lower supply current requirements.

•

SN5481A •• , J OR W PACKAGE
SN7481A .,. J OR N PACKAGE
(TOP VIEW)
WRITE ADDRESS

ADDRESS WRITE
X4

The flip-flops are arranged in a four-by-four matrix
with each flip-flop representing one bit of 16 words.
Four X·address lines and four Y-address lines permit
the address of one bit at a time. Each flip·flop,
composed of two cross-coupled three-emitter transistors, is used to store one bit. To determine if a
logic 1 or logic 0 has been stored, it is necessary to
know which one of the two flip-flop transistors is
conducting. One emitter of each of these transistors
serves as the sensing output. All 16 of the logic 1
sensing outputs are connected to the sense 1 (S1)
amplifier input and all 16 of the logic 0 sensing
outputs are connected to the sense 0 (SO) amplifier
input. The two remaining emitters of each transistor
are used to complete the matrix connections necessary for the X- and V-address lines. Address line
inputs are normally held low and currents from all
conducting flip-flop transistors flow out of these
address lines .

1

GND

0

Y4

~vcc~
ADDRESS

ADDRESS

logic: See logic diagram

SN5484A ••• J OR W PACKAGE
SN7484A ••• J OR N PACKAGE
(TOP VIEW)
WRITE

SENSE

WRITE

ADDRESS

~~GND~Y4

To address a flip-flop both the X- and V-address lines
associated with that flip-flop are taken to a high level.
Due to the matrix nature of the circuit, at least one
address iine of aii fiip-fiops except the one being
addressed will continue to remain at a low level and
no change will occur in those flip-flops. But, in the
addressed flip-flop, the current in the conducting
transistor diverts from the address lines to the
appropriate sense line and then to one of the sense
amplifiers. Thus, either the sense 1 amplifier or the
sense 0 amplifier is activated. When this occurs, the
output of the activated sense amplifier drops from a
high logic level to a low logic level. The memory is
nondestructive as the states of the flip-flops are not
disturbed during sensing. The memory is volatile and
information will be lost if the supply voltage is
removed.

~Vcc

y,~

ADDRESS

ADDRESS

logic: See logic diagram

To store new information in a flip-flop, it is necessary to address it and apply a high-level voltage to the appropriate
write amplifier. (The SN5484A and SN7484A have gated write-amplifier inputs). The output of the write amplifier
responds by dropping to a low logic level. Since all Sense 0 lines are connected to the output of the write 0 amplifier
and all sense 1 lines are connected to the output of the write 1 amplifier, a low level at the output of a write amplifier
076

7-44

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

CALLAS. TEXAS 75222

TYPES SN5481A, SN5484A, SN7481A, SN7484A
16-81T RANDOM-ACCESS MEMORIES
description (continued)
will cause the emitters of all flip-flop transistors connected to that amplifier to go low. In all the flip·flops except the
one being addressed, this low voltage has no effect since at least one other emitter on each of the flip-flop transistors is
held low by the address lines. Two possibilities exist with the flip·flop that is addressed. The flip·flop may already be in
the desired state, in which case no change occurs. If the flip-flop must be changed from one state to the other, the low
voltage applied to the emitter of the transistor which is not conducting turns that transistor on causing the other
transistor to turn off.
Since' the connection between the output of the write amplifier and the sense line is common to the input of the sense
amplifier, the memory cannot be used to provide information on the state of a bit while the write amplifiers are
activated.
A number of active-element memories may be paralleled to form the desired matrix size (number of words) and to form
the desired word length (number of bits). All inputs and outputs are compatible with most DTL and TTL circuits.
Average power dissipation is typically 225 milliwatts, and the open-collector outputs may be wire·AND connected to
similar outputs. Internal circuitry of the write and sense amplifiers are operated within their linear range to improve
speed. Sensing propagation delay tirnes are typically 12 Ili:mu~t:!(;uf1(js when operated at fuii fan-out and 30 picofarads of
circuit capacitance. The SN5481 A and SN5484A circuits are designed for operation over the full military temperature
range of -55°C to 125°C; the SN7481A circuits are designed for operation from O°C to 70°C.

logic diagram

•
Y1

Y2

Y3

Y4

1272

TEXAS INSTRUMENTS
Il'oICORPORATED

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•

DALLAS. TEXAS 75222

7-45

TYPES SN5481A, SN5484A, SN7481A, SN7484A
16-81T RANDOM-ACCESS MEMORIES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage . . . . . . .
Interemitter voltage (see Note 2)
High·level output voltage . . .
Operating free·air temperature range: SN5481A, SN5484A Circuits
SN7481A, SN7484A Circuits
Storage temperature range

7V

5.5 V
5.5 V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple·emitter transistor. For this circuit, this rating applies to any X input in
conjunction with any Y input.

recommended operating conditions
SN5481A, SN5484A SN7481A, SN7484A

Supply voltage, Vee

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

UNIT
V

High-level output voltage, VOH

5.5

5.5

V

Low-level output current, IOL

20

40

rnA

Width of write pulse, tw(write) (see Figure 1)

20

20

ns

0

0

ns

Address input setup time, tsu (see Figure 1)

125

-55

Operating free-air temperature, T A

70

0

e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

•

VIL

SN5481A, SN5484A SN7481A,SN7484A
MIN

TYP:j:

MAX

2

High-level voltage at any input
Low-level voltage

I

to prevent writing

at address inputs

I

to prevent sensing

MIN

MAX

2

UNIT
V

0.8

0.8
1

1

0.8

1

V
V

VIL

Low-level voltage at write inputs

VIK

I nput clamp voltage

Vee = MIN, 11= -12 rnA

-1.5

-1.5

V

IOH

High-level output current

Vee = MIN, VOH = 5.5 V

250

250

IJA

Vee = MIN, IOL = MAX

0.4

0.4

VOL

Low-!evel output voltage
I nput current at

II

IIH

maximum input voltage
High-level input current

IlL

Low-level input current

ICC

Supply current

Write
Address

1 '
Vee = MAX,VI = 5.5 V

Write

Vee = MAX,VI = 2.4 V

Address

Vee

= MAX,VI = 4.5 V

Write
Address

VI

Vee MAX,

= 0.4 V

= 5 V,

All inputs at 0 V

3

3
40

400

400

-1.6

-1.6

-11

-11

70

Vee = MAX,AII inputs at 0 V
Vee

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

i

40

45

60

t For conditions shown as MIN or M AX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.

7-46

TYP:j:

65
45

60

V
rnA

IJA
rnA

rnA

TYPES SN5481A. SN5484A. SN7481A. SN7484A
16-81T RANDOM-ACCESS MEMORIES
switching characteristics, Vee = 5 V, IOL = MAxt, TA = 25°e, see figure 1
PARAMETER§

LOCATION

MIN

= 30 pF
= 200 pF
CL = 30 pF
CL = 200 pF
CL = 30 pF
CL = 200 pF
CL = 30 pF
CL = 200pF
CL = 30 pF
CL = 200pF

X1-Y1

tSR

SN5481A. SN5484A SN7481A. SN7484A

TEST CONDITIONS

ADDRESSED

tpHL
X1-Y1
tPLH
tPHL
X1 thru X4 and Y1
tPLH

TYP

MAX

MIN

TYP

MAX

CL

13

CL

18

30

18

13
30

11

19

12

20

17

26

18

27

13

20

12

19

27

40

18

27

10

18

11

19

16

25

17

26

13

20

13

20

27

40

19

28

UNIT
ns

ns

ns

TFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
§tSR

== Sense recovery time after writing
== Propagation delay time, high-to-Iow-Ievel
== Propagation delay time, low-to-high-Ievel

tpH L

output

tpLH

output

schematic
r-------~~~~-------l
11 OF 161

rlI

---'wv

ADDRE:.-----_t
~7k

7k~

m

}

•

TOALL
OTHER CELLS

OTHER CELLS
L ________
___________

~

r - - - - - - - - - - - WRiTEANDSENse AMPURERS - - - - - - - - - - - - ,
I
110F21
I
I
I

r--.-------.-~~v~

I

I

So OTS 1

I
I

I
I
I

IL

~
_____________________________

~

tWO(B) and W1 (B) inputs (indicated with dashed lines) are applicable for the SN5484A, SN7484A only.

W...

Vee bus
Resistor values shown are nominal and in ohms.

1272

TEXAS INSTRUMENTS
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POST'OFFICE BOX 5012 •

DALLAS, TeXAS 75222

7-47

TYPES SN5481A, SN5484A, SN7481A, SN7484A
16-BIT RANDOM-ACCESS MEMORIES
PARAMETER MEASUREMENT INFORMATION
So°UTPUT

VCC=5V

CIl

:2

a:

~

w

Y4

~:3

Sor---~--------~----i

3:5
wZ

X2

(!)o

z
j

w

w

r - LOAD c;- RCUlT2 - -,

CIl

(Same as load circuit 1)
L _________
JI

(SeeNoteC)

TEST CIRCUIT
t4--100ns~

~

I ~<;;10ns

~: ~<;;10ns

9O%~ i

! 1t,90%
~

ADDRESS

INPUT

1.5V

tsu~
<;;10

ns~
10%

Wo INPUT

/

1.5V -{10%

:

i4- ~ 14-<;;10 n,
9Cn~tl:------------------------------3V

~'.'

v~

OV

I

l

OOo,

! K.~%

~1.~
--.;
<;;10 ns~

OUTPUT
(SoorS l)

ov

~------------l--------- ::~
~

~tsR
I

(See NoteD)

r

,'-,1

'\.
,/
't~.5 V
SENSE-RECOVERY TIME VOLTAGE WAVEFORMS "--...;..--...;..---~

f"!!--

INPUT
(Woo rW l'

1.5V~10%
~20 n'~

(See Note D)

'\.

<;;10n'~ I ~

WRITE

~tSR

o

schematics of inputs and outputs
'S3A

'S3A

EQUIVALENT OF

TYPICAL OF ALL
OUTPUTS

EACH INPUT

VCC3--

'LSS3A

'LS83A

EQUIVALENT OF

TYPICAL OF
ALL OUTPUTS

EACH INPUT

-----.. . .--VCC

VCC
VCC----

120

n

NOM

Req

INPUT

INPUT_...._ _ _

~

-OUTPUT

CO input: Req = 4 k!1 NOM
Any A or B: Req = 3.5 k!1 NOM

OUTPUT

C4 output: R = 100!1 NOM

CO input: Req = 17 k!1 NOM
Any A or B: Req = 8.5 kfi NOM

Anyr::R=120nNOM

1076

7·54

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN5483A, SN7483A
4-BIT BINARY FULL ADDERS WITH FAST CARRY
recommended operating conditions
SN5483A
NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

Supply Voltage, VCC
High-level output current, 10H

SN7483A

MIN
Any output except C4

-800

-800

Output C4

-400

-400

16

16

8

8

Any output except C4

Low-level output current, 10L

Output C4

Operating free-air temperature, T A

-55

125

0

70

UNIT
V
p.A
rnA

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

I

VIH

High-level input voltage

VIL

Low-level input voltage

V 11<

Input clamp voltage

VOH

VOL

MIN

TYP:j:

SN7483A
MAX

MIN

2

VCC= MIN,

II = -12mA

VCC = MIN,

VIH = 2 V,

I ·,L

High-level output voltage

\I

Low-level output voltage
Input current at maximum

II

SN5483A

TEST CONDITIONSt

PARAMETER

-

nA\I
...... '""

·un

I

IlJiAY
... '"

2.4

MAX

V

0.8

V

-1.5

-1.5

V

I

3.4

2.4

I I

3.4

V

'';

VCC= MIN,

VIH =2V,

VIL = 0.8 V,

10L = MAX

UNIT

0.8

0.2

0.4

VCC = MAX, VI = 5.5V

input voltage

TYp:j:

2

0.2

0.4

1

1

V
mA

IIH

High-level input current

VCC = MAX, VI = 2.4 V

40

40

p.A

IlL

Low-level input current

VCC = MAX, VI = 0.4 V

-1.6

-1.6

mA

Short-circuit
lOS

ICC

output current§

I Any output except C4

VCC = MAX

I Output C4

Aii B iow, other

II VCC = MAX,

inputs at 4.5 V

I

Supply current

-20

-55

-18

-55

-20

-70

-18

-70

I

I

Outputs open All jnputs at

66

4.5V

I

56

99

mA

56
mA
66

1

110

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
§ Only one output should be shorted at a time.

switching characteristics, Vee
PARAMETERlI
tPLH

= 5 V, TA = 25°e

FROM (INPUT)

TO (OUTPUT)

CO

Any 2:

Ai or Bi

2:i

CO

C4

TEST CONDITIONS

CL=15pF,

tpHL
tpLH

RL =400 n,

See Note 3

CL=15pF,

tPHL

See Note 3

tpLH
tpHL

AiorBj

MIN

TYP

MAX

14

21

12

21

16

24

16

24

UNIT
ns

ns

tpHL
tPLH

•

C4

RL=780n,

9

14

11

16

9

14

11

16

ns

ns

11 tpLH == Propagation delay time, low-to·high·level output
tpH L == Propagation delay time, high-to·low·level output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-55

TYPES SN54LS83A, SN74LS83A
4-BIT BINARY FULL ADDERS WITH FAST CARRY
REVISED OCTOBER 1976

recommended operating conditions
SN54LS83A
Supply voltage, Vee

MIN

NOM

4.5

5

SN74LS83A

MAX

MIN

5.5

4.75

MAX

5

5.25

V

-400

!J.A

S

mA

70

°e

-400

High-level output current, 10H

4

Low-level output current, 10L
-55

Operating free-air temperature, T A

125

UNIT

NOM

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

IIH
IlL
lOS

11=-lSmA

Vee- MIN,

VIH - 2V,

VIL - VIL max,

VIH-2V,

10L -4mA

Vee- MIN,

2.5

Vee = MAX,
Any A or B

input current

eo

Low-level

Any A or B

input current

eo

Short-circuit output current§

Vee = MAX,
Vee= MAX,

MAX

UNIT
V

O.S

V

-1.5

-1.5

V

3.4

2.7
0.4

3.4

V

0.25

0.4

0.35

0.5

0.2

0.2

0.1

0.1

40

40

V

mA

VI = 7V

VI=2.7V
VI = 0.4 V

All B low, other

Outputs open

inputs at4.5 V
All inputs at
4.5V

20

20

-0.8

-0.8

-0.4

-0.4

-100

-20

Vee= MAX

Vee= MAX,

Supply current

TYP:j:

0.7

eo

High-level

MIN
2

Any A or B

grounded

•

SN74LS83A

MAX

0.25

All inputs

lee

TYP:j:

10L = SmA

VIL = VIL max

at maximum
input voltage

Vec= MIN,
10H = -400!J. A

VOL Low-level output voltage

II

MIN
2

VOH High-level output voltage

Input current

SN54LS83A

TEST CONDITIONSt

PARAMETER

-100

-20

22

39

22

39

19

34

19

34

19

34

19

34

!J. A
mA
mA

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC = 5 V, T A = 25° C.
~ Only one output should be shorted at a time, and duration of the short-cirCuit should not exceed one second.

switching characteristics, Vee
PARAMETER~

tpLH
tpHL
tpLH
tpHL
tPLH

tpHL

0

C

FROM (INPUT)

TO (OUTPUT)

eo

Any:E

AiorBi

:l:i

eo

C4

tpHL
tPLH

= 5 V, TA = 25

Ai orBi

TEST CONDITIONS

MIN

TYP
16

eL=15pF,
See Note 4

C4

RL = 2 kn,

MAX UNIT
24

15

24

15

24

15

24

11

17

1.5

22

11

17

12

17

ns
ns

I

ns
ns

~tpLH == Propagation delay time, low-to-high-Ievel output
tpH L == Propagation delay time, high-to-Iow-Ievel output
Note 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

7·56

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

OALLAS. TEXAS 75222

TYPES SN5485, SN54L85, SN54LS85, SN54S85,
SN7485, SN74L85, SN74LS85, SN74S85
4-81T MAGNITUDE COMPARATORS

TTL
MSI

BULLETIN NO. DL-S 7611810, MARCH 1974-REVISED OCTOBER 1976

SN5485, SN54LS85, SN54S85 ••• J OR W PACKAGE
SN7485, SN74LS85, SN74S85 ••• J OR N PACKAGE
(TOP VIEW)

SN54L85 .•• J PACKAGE
SN74L85 ••• J OR N PACKAGE
(TOP VIEW)

DATA INPUTS

INPUTS

A

TYPE

'85

TYPICAL

TYPICAL

POWER

DELAY

DISSI·

(4·BIT

PATION

WORDS)

275mW

23 ns

'L85

20mW

'LS85

52mW
365mW

90 ns
24 ns

'585

11 ns

OUTPUTS

INPUTS

vCC~~~

D.frA,A B"A> B A:B A B, A < B, and A = B outputs of a stage handling less-significant bits are
connected to the corresponding A> B, A < B, and A = B inputs of the next stage handling more-significant bits. The
stage handling the least-significant bits must have a high-level voltage applied to the A = B input and in addition for the
'L85, low-level voltages applied to the A> B and A < B inputs. The cascading paths of the '85, 'LS85, and 'S85 are
impiemented with only a two-gate-Ievel delay to reduce overall comparison times for long words. An alternate method
of cascading which further reduces the comparison time is shown in the typical application data.
FUNCTION TABLES
COMPARING

CASCADING

INPUTS

OUTPUTS

INPUTS

A3,B3

A2, B2

Al.Bl

AO.BO

A>B

AB

A B3

X

X

X

X

X

X

H

L

L

A3< B3

x

X

X

X

X

X

L

H

L

A3= B3

A2 > B2

x

X

x

x

X

H

L

L

A3= B3

A2 < B2

X

X

X

X

X

L

H

L

A3= 82

A2= 82

A1 >81

x

x

x

X

H

L

L

A3= 83

A2= 82

A1 < 81

X

X

X

X

L

H

L

A3= 83

A2= 82

A1 = 81

AD> 80

X

X

X

H

L

L

A3= 83

A2= 82

A1 = 81

AO< 80

x

X

X

L

H

L

A3= 83

A2 = 82

A1 = 81

AO= 80

H

L

L

H

L

L

A3= 83

A2= 82

A1 = 81

AO= 80

L

H

L

L

H

L

A3= 83

A2= 82

A1 = 81

AO= 80

L

L

H

L

L

H

X

X

H

H

H

•

'85, 'LS85, 'S85
H

L

H

H

'L85
A3= 83

A2= 82

A1 = 81

AO= 80

L

H

H

L

H

A3= 83

A2= 82

A1 = 81

AO= 80

H

L

H

H

L

H
H

H

A3 = 83

A2= 82

A1 = 81

AO= 80

H

H

H

H

H

A3= 83

A2= 82

A1 = 81

AO= 80

H

H

L

H

H

L

A3= 83

A2= 82

A1 = 81

AO= 80

L

L

L

L

L

L

H

=

high level. L

= low

level. X

= irrelevant

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-57

TYPES SN5485, SN54L85, SN54LS85, SN54S85,
SN7485, SN74L85, SN74LS85, SN74S85
4-81T MAGNITUDE COMPARATORS
functional block diagrams

.

•

o

•• ; ;

~,

(,r-';;

i'L

t ~,

I

"''''


374

7-58

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN5485, SN54L85, SN54LS85, SN54S85,
SN7485, SN74L85, SN74LS85, SN74S85
4-81T MAGNITUDE COMPARATORS
schematics of inputs and outputs
EQUIVALENT OF EACH
INPUT FOR '85

VCC------.-----

~----------------~
EQUIVALENT OF EACH
INPUT FOR 'L85

= B, Any A or B:
Req = 1.67 k.l1 NOM
A> B,A < B:
Req = 4 k.l1 N'l.~.
A

EQUIVALENT OF EACH
INPUT FOR 'S85

VCC---~---

v CC - - - - 1 . . - - - -

v CC----1..----

INPUT--~~-e---.-

INPUT

INPUT

EQUIVALENT OF EACH
INPUT FOR 'LS85

Any A or B:
Rea = 16.7 k.l1 NOM
A=B,A>B,AS:A B inputs

all other inputs
A < B, A > B inputs
all other inputs

Vee = MIN,

11=-12mA

Vee = MIN,

VIH = 2 V,

VIL = 0.8 V,

IOH = - 4OO !J.A

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

IOL = 16 mA

Vee = MAX,

VI = 5.5 V

Vee = MAX,

VI = 2.4 V

Vee = MAX,

VI = 0.4 V

Short·circuit output current§

Vee = MAX,

Vo =0

ICC

Supply current

Vee = MAX,

See Note 4

V

-1.5

V

3.4
0.2

V
0.4
1

V
mA

40
120
-1.6
-4.8

I SN5485
I SN7485

lOS

2.4

V
0.8

-20

-55

-18

-55
55

88

!J.A
mA
mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 4: ICC is measured with outputs open, A = B grounded, and all other inputs at 4.5 V.

I

switching characteristics, Vee
PARAMETER~

= 5 V, TA = 25°e

FROM

TO

NUMBER OF

INPUT

OUTPUT

GATE LEVELS

TEST CONDITIONS

1
tpLH

Any A or B data input

A < B, A>B
A=B

i Any A or B data input I

A < B,

A>B

TYP MAX

2

12

3

17

26

4

23

35

3
4

ns

11

2

A=B

UNIT!

7

1
tPHL

MIN

eL = 15 pF,
I

RL = 400
See Note 5

st,

15
20

30

20

30

ns

tPLH

A < B or A = B

A>B

1

7

11

ns

tPHL

A < B or A = B

A>B

1

11

17

ns

tpLH

A=B

A=B

2

13

20

ns

tpHL

A=B

A=B

2

11

17

ns

tpLH

A> B or A = B

A B or A = B

A B, or A = B

A or B inputs
A

High-level input current

< B, A < B, or A

=B

A or B inputs
A

< B, A>

it-S_N_·5_4_L_8_5_+-_2_.4_ _3_._3_ _--i

VIL = 0.7 V,

output voltage

input current at

V I H ~ 2 V,

B, or A = B

3.2

ISN74L85

0.2

lOS

Short-circuit output current§

Vee= MAX

ICC

Supply current

Vee = MAX,

0.41

100
300
10

Vee = MAX, VI = 2.4 V

Low-level input current

30
-0.18

Vee= MAX, VI = 0.3 V

-0.54
-3

See Note 6

V

I;-S_N_54_L_85_+-_ _ _0_.1_5_ _0_.3--i

Vee = MAX, VI = 5.5 V

IlL

A or B inputs

2.4

V

I Condition A

1Condition B

-15
4.0

7.7

3.2

7.2

v

JlA
JlA
mA
mA
mA

tfor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

= 25

+AII typical values are at V CC = 5 V, T A

0

C.

§ Not more than one output should be shorted at a time.
NOTE 6: With all outputs open, ICC is measured for Condition A with all inputs at 4.5 V, and for Condition B with all inputs grounded.

switching characteristics, Vee
PARAMETER~

tpLH

II

= 5 V, TA = 25°e

FROM

TO

(INPUT)

(OUTPUT)

Any A or B

TEST CONDITIONS

Any

eL = 50 pF,

tpHL
tpLH
tpHL

A> B, A

< B,

orA = B

See Note 7

Any

RL = 4 kS1,

MIN

TYP

MAX UNIT

90

150

75

150

75

150

55

100

ns
ns

~ tpLH == propagation delay time, low-to·high-Ievel output
tpH L == propagation delay time, high·to-Iow-Ievel output
NOTE 7: Load circuit and voltage waveforms are shown on page 3-11.

374

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-61

TYPES SN54LS85, SN74LS85
4-81T MAGNITUDE COMPARATORS
REVISED OCTOBER 1976

recommended operating conditions
SN54LS85
Supply voltage, Vee

MIN

NOM

4.5

5

High-level output current, 10H

SN74LS85

MAX

MIN

NOM

5.5

4.75

5

-400

Low-level output current, 10L

5.25

V

-400

/lA

8

mA

70

°e

4

Operating free-air temperature, T A

-55

125

UNIT

MAX

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

SN54LS85

TEST eONDITIONSt

PARAMETER

MIN

Vee: MIN,

II: -18mA

Vee: MIN,

VIH: 2 V,

VIL: VIL max, 10H: -400/lA

2.5

Vee: MIN,

IIH
IlL

High·level

A < B, A > B inputs
all other inputs

Low-level

A < B, A > B inputs

input current

all other inputs

V

-1.5

V

3.4

2.7
0.4

lOS

Vee: MAX

Supply current

Vee: MAX,

3.4

V

0.25

0.4

0.35

0.5

V

0.1

0.1

0.3

0.3

mA

VI: 0.4 V

Vee: MAX,

lee

V

-1.5

20

20

60

60

-0.4

-0.4

VI :2.7V

Vee: MAX,

Short-circuit output current§

UNIT

VI: 7V

Vee: MAX,

input current

MAX
0.8

all other inputs

input voltage

TYP+

0.7

A < B, A > B inputs

at maximum

MIN
2

0.25

Il0L :4mA
VIH: 2V,
:1
VIL: VIL max 10L: 8 mA

VOL Low-level output voltage
I nput current

SN74LS85

MAX

2

VOH High-level output voltage

II

TYP+

-1.2
-20

See Note 4

-100
10.4

/lA
rnA

-1.2
-20
10.4

20

-100

mA

20

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC : 5 V, T A : 25°C.
§ Not more than One output should be shorted at a time, and duration of the short·circuit should not exceed one second.
NOTE 4: ICC is measured with outputs open, A : B grounded, and all other inputs at 4.5 V.

I

switching characteristics, Vee = 5 V, T A = 25° C
i

i

PARAMETER~

tPLH

i

FROM
INPUT

Any A or B data input

NUMBER Of
GATE LEVELS
1

14

A < B, A > B

2

19

3

24

36

A:B

4

27

45

I
tpHL

Any A or B data input

:

TO
OUTPUT

I

1

A < B, A> B

2

A:B

4

TEST CONDITIONS

I

3

MIN

TYP

MAX UNIT

:

ns

11
CL:15pF,
RL: 2 kn,
See Note 7

15
20

30

23

45

ns

tPLH

AB

1

14

22

tpHL

A < B or A - B

A>B

1

11

17

ns

tPLH

A:B

A:B

2

13

20

ns
ns

ns

tPHL

A-B

A-B

2

13

26

tpLH

A>BorA:B

A B or A: B

A B inputs
all other inputs
A < B, A > B inputs
all other inputs

Vce- MIN,

11--18mA

Vee= MIN,

V!H=2V,

VIL = 0.8 V,

10H = -1 mA

Vee = MIN,

VIH = 2V,

VIL - 0.8 V,

iOL=20mA

Vee- MAX,

VI- 5.5 V

Vee= MAX,

VI=2.7V

Vee = MAX,

VI = 0.5 V

!SN54S85

MAX UNIT

1SN74S85

3.4

2.7

3.4

V

-1.2

V
V

1
50
150
-2
-6
-100

--40

Vee = MAX, TA=125°e,
See Note 4

0.8

0.5

Vee = MAX

Supply current

V

2.5

Vee = MAX, See Note 4
ICC

TYp:j:

2

73

I

p.A
mA
mA

115
110

SN54S85W

V
mA

mA

TFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 4: ICC is measured with outputs open, A = B grounded, and all other inputs at 4.5 V.

switching characteristics, Vee
PARAMETER~

= 5 V, TA = 25°e

FROM

TO

NUMBER OF

INPUT

OUTPUT

GATE LEVELS

TEST CONDITIONS

1
A < B, A > B
tpLH

Any A or B data input
A=B

tpHL

Any A or B data input

TYP

MAX

2

7.5
10.5

16

4

12

18

1

5.5

3
A=B

4

UNIT

5

3

2

A < B, A> B

MIN

eL=15pF,
RL = 280

n,

See Note 5

7
11

16.5

11

16.5

ns

ns

tPLH

A < BorA = B

A>B

1

5

7.5

tpHL

A < BorA - B

A>B

1

5.5

8.5

ns

tPLH

A=B

A=B

2

7

10.5

ns
ns

ns

tpHL

A-B

A-B

2

5

7.5

tpLH

A> B or A - B

A B or A - B

AB

818
A18
817

A3

A17

816
A16
B15
A15
814
A14
B13
A13
B12
A12
Bl1
All
Bl0
AID

AB
'85, 'L85,
'L585. '585

83
B2
A2
Bl
AI

eo
AO
AB

AB
'85, 'L85,
'LS85. '585

830

83
A3

A3

B2

B2

A2
81
Al

eo

A8
'85, 'L85,
'L585, '585

AS

OUTPUTS
A<8
A~

A>B

Ail

AO

B9

A2
Bl
AI
SOA8

'85, 'L85,
'L585, '585

B8
AS
B7

A7
AB

B6
A6

B5
AS
B4

•

A4

A3
B2
A2
Bl
Al

B3
A3
B2
A2
Bl
A1

AO

AO

83

ILSB)

A=B
A>B

eo

eo

AB

'85, 'L85,
'LS85, '585

AB
'85, 'L85
'L585, '585

COMPARISON OF TWO 24-BIT WORDS

374

7-64

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

TYPES SN5486, SN54L86, SN 54LS86, SN54S86,
SN7486, SN74L86, SN74LS86, SN74S86
. QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

TTL
MSI

BULLETIN NO. DL-S 7611

••• J OR W PACKAG
SN74', SN74LS', SN74S' .•• J OR N PACKAGE
(TOP VIEW)

schematics of inputs and outputs
'86
TYPICAL OF
ALL OUTPUTS

EQUIVALENT OF
EACH INPUT

Vee

Vee

--~TI---

~ 4 k.l1 NOM

'N'UT-Cr

OUTPUT

positive logic: Y

'L86
TYPICAL OF
ALL OUTPUTS

EQUIVALENT OF
EACH INPUT

= A <±:l B = AB + As

SN54L86 ••• J PACKAGE
SN74L86 ••• J OR NPACKAGE
(TOPVIEWI

I

I I

VCC4B

4A

4Y

3Y

38

3A

~

II

ldJ II

[55J

~

positive logic: Y = A <±:l B = AB + AB

SN54L86 ••• T PACKAGE (TOP VIEW)
'LS86
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

•

Vee--......- 12.5 k.l1 NOM
I NPUT

_.,..-+-----

•

INPUT B . .).(.:. <)..c:[8~]
1
_ _--+-¢>

RO(l) (2)[1]
RO(2) (3)[2]

The J and K inputs shown without connection are for reference only and are functionally at a high level.

374

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-73

TYPES SN5490A, '92A, '93A, SN54L90, 'L93, SN54LS90, 'LS92, 'LS93,
SN7490A, '92A, '93A, SN74L90, 'L93, SN74LS90, 'LS92, 'LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
REVISED OCTOBER 1976
schematics of inputs and outputs
'90A, '92A, '93A
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT
vee3
Req - INPUT

--

INPUT
A
B ('90A, '92A)
B ('93A)
All resets

Req NOM
2.5 kH
1.25 kH
2.5 kH
6 kH

'L90, 'L93
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF A AND B
INPUTS OF 'L93

EQUIVALENT OF EACH INPUT
EXCEPT A AND B OF 'L93

vee~_-

Vee-----.----~~-------

Req

INPUT

--

INPUT

•

INPUT
A ('L90)
B ('L90)
All resets

Req NOM
13.3 kH
6.67 kH
40 kl1

'LS90, 'LS92, 'LS93
EQUIVALENT OF EACH RESET INPUT

Vee

U-T

~NOM

'N'"T

I

EQUIVALENT OF A AND B INPUTS

---_Vee
120 l1 NOM

ve~
R1 R2 R3

INPUT

TYPICAL OF ALL OUTPUTS

OUTPUT

NOMINAL VALUES
INPUT
R1
R2
R3
A
10kl1
10 kl1 10 kl1
B ('LS90, 'LS92) 6.7 kl1
6.7 kl1
5 kl1
B ('LS93)
15 kl1
15kl1 10kl1

107E

7·74

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN5490A, SN5492A, SN5493A, SN7490A, SN7492A, SN7493A
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN5490A, SN5492A, SN5493A
SN7490A,SN7492A,SN7493A
Storage temperature range
NOTES:

7V
5.5 V
5.5 V
-55°e to 125°e
0
O°C to 70 e
0
-65°e to 150 e

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between the two RO
inputs, and for the '90A circuit, it also applies between the two R9 inputs.

recommended operating conditions

I

I

SN5490A, SN5492A SN7490A, SN7492A
SN5493A
MIN
4.5

Supply voltage, Vee

NOM
5

MAX

MIN

5.5

4.75

NOM
5

-800

High-level output current, 1014
A input
Count frequency, fcount (see Figure 1)

Pulse width, tw

0

32
16

0

16

0
15

15

B input

30

30

Reset inputs

15

15

25
-55

V
/LA

32

B input

Operating free-air temperature, T A

5.25
-800

0

A input

Reset inactive-state setup time, tsu

UNIT
MAX

16

16

Low-level output current, 101

I I

SN7493A

mA
MHz

ns
ns

25
125

°e

70

0

electrical characteristics over recommended operating free-air temperature range (un!ess otherwise noted)
TEST eONDITIONst

PARAMETER
VIH

High-level input voltage

VIL
V IK

Low-level input voltage
Input clamp voltage

VOH High-level output voltage
VOL Low-level output voltage
Input current at
II

maximum input voltage
High-level

IIH

Vee= MIN,

II = -12 mA

Vee= MIN,

VIH = 2V,

VIL = 0.8 V, IOH = -800 /.LA
Vee= MIN,

VIH = 2 V,

VIL = 0.8 V,

10L = 16 mA1f

ICC

2.4

A input

0.2

Vee= MAX, VI = 5.5 V

Vee = MAX, VI = 2.4 V

Vee= MAX, VI = 0.4 V

B input

I SN54'

I SN74'

Vee= MAX

output current§
Supply current

TYP+

MAX

MIN

V

2
0.8

V

-1.5

-1.5

-1.5

V

2.4

3.4
0.2

0.4

2.4

3.4
0.2

0.4

V
V

0.4

1

1

1

40

40

40

80

80

80

120

120

80

-1.6

-1.6

-1.6

-3.2

-3.2

-3.2

-4.8

-4.8

-3.2 i

-57

-20

-57

-20

-18

-57

-18

-57

-18

29

UNIT

MAX

0.8

-20

Vee = MAX, See Note 3

TYP+

0.8

3.4

,Any reset
A input

MIN
2

B input

input current

'93A

'92A
MAX

2

Short-circuit
lOS

TYP+

Any reset

input current
Low-level

IlL

'90A
MIN

42

26

39

•

mA

/.LA

I

mA

-57
-57! mA
26

39: mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at

Vee = 5

V, T A

= 25° C.

§ Not more than one output should be shorted at a time.
~QA outputs are tested at IOL = 16 rnA plus the limit value for IlL for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-75

TYPES SN5490A, SN5492A, SN5493A, SN1490A, SN1492A, SN1493A
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
REVISED OCTOBER 1976

switching characteristics, Vee
PARAMETER~

f max

tpLH

TO

(INPUT)

(OUTPUT)

A

QA

32

B

QB

16

A

tpHL
tpLH
tpHL
tpLH
tpHL
tPLH

A
B

tpHL
tpLH
tpHL

CL:15pF,
QB

B

QD

Set-to-O
Set-to-9

MIN

'90A

'92A

'93A

TYP MAX MIN

TYP MAX MIN

TYP MAX

32

42

42

32

16
10

QD

Qc

tpHL

TEST CONDITIONS

QA

B

tpHL
tpLH

= 5 V, T A = 25° e

FROM

16

42

MHz

16
10

16

10

UNIT

16

12

18

12

18

12

18

32

48

32

48

46

70

34

50

34

50

46

70

10

16

10

16

10

16

RL:400n,

14

21

14

21

14

21

See Figure 1

21

32

10

16

21

32

23

35

14

21

23

35

21

32

21

32

35

23

35

34
34

51

23

Any

26

40

26

40

26

40

QA,QD

20

30

QB,QC

26

40

51

ns
ns
ns
ns
ns
ns
ns

~fmax == maximum count frequency
tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output

•

1076

7-76

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54L90, SN54L93, SN74L90, SN74L93
DECADE AND BINARY COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 4) . . . . . . . . . .
Input voltage (see Note 5)
. . . . . . . . .
Operating free-air temperature range: SN54L90, SN54L93 .
SN74L90, SN74L93
Storage temperature range
NOTES:

8V

5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

4. Voltage values are with respect to network ground terminal.
5. Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN54L90, SN54L93
MIN
Supply voltage, VCC

4.5

Count frequency, fcount

NOM
5

0

SN74L90, SN74L93

MAX

MIN

5.5

4.75

3

0

NOM
5

MAX
5.25
3

UNIT
V
MHz

High-level output current, 10H

-100

-200

!-LA

Low-level output current, 10L

2

3.6

mA

Width of input count pulse, tw(count)

200

200

Width of reset puise, 1w(reset)

zOu

zOO

Operating free-air temperature, T A

-55

125

ns
ns

0

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

VOL

maximum input voltage
High-level input

IIH

current

current

'L93
MAX

MIN

TYP+

SN54L'

SN74L'

-

Vee; MIN,

VIH; 2 V,

2.4

VIL; 0.7 V,

10H; MAX

2.4

Vee; MIN,

VIH;2V,

VIL; 0.7 V,

101 ; MAX~I

3.3
3.2

0.15

0.2

0.4

0.2

VCC; MAX, VI; 5.5V

Any reset input
Vee; MAX, VI; 2.4 V

Any reset input
Vce; MAX, VI; 0.3 V

A input
B input

Vce; MAX

ICC

Supply current

Vec; MAX, See Note 3

-3

0.4
100

300

200

600

200

10

10

30

20

60

20

-0.18

-0.18

-0.54

-0.36

-15
4

0.3

100

V

!-LA

!-LA

mA

•

-D.36

-1.08

lOS

Short-circuit output current§

V
V

3.2

0.3

B input
A input

3.3

0.15

Any reset input
A input

0.7
2.4
2.4

UNIT
V

0.7
SN54L'
-SN74L'

MAX

2

B input

Low-level input
IlL

TYP+

2

Low-level output voltage
input cu rrent at

II

'L90
MIN

-3
3.2

7.2

-15

mA

6.6

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC; 5 V, TA; 25°C.
§Not more than one output should be shorted at a time.
~QA outputs are tested at IOL; MAX plus the limit value for IlL for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

switching characteristics, Vee

= 5 V, TA = 25° e

PARAMETER

'L90

TEST CONDITIONS
MIN

f max
tpLH
tpHL

Maximum count frequency

3

Propagation delay time, low-to-high-Ievel QD
output from input A

CL; 50 pF,

Propagation delay time, high-to-Iow-Ievel QD

See Figure 1

RL;4kU,

output from input A

TYP

'L93
MAX

6

MIN
3

TYP

UNIT
MAX

6

MHz

230

340

280

450

ns

230

340

280

450

ns

374

TEXAS INCORPORATEO
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-77

TYPES SN54LS90, SN54LS92, SN54LS93,
SN74LS90, SN14LS92, SN14LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 4)
Input voltage: R inputs
A and B inputs
Operating free-air temperature range: SN54LS' Circuits
SN74LS' Circuits
Storage temperature range

7V
7V

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 4: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS90

SN74 LS90

SN54LS92

SN74 LS92

SN54LS93,
MIN
4,5

Supply voltage, VCC

NOM
5

High·level output current, 10H

MIN

5.5

4.75

NOM

Low·level output current, 10L

MAX

5

-400

5.25
,-400

4
A input

Count frequency. fcount (see Figure 11

Pulse width. tw

0

32
16

8
0

32

0

16

B input

0

A input

15

15

B input

30

30

Reset inputs

15

15

Reset inactive-state setup time, tsu

25

Operating free·air temperature. T A

-55

UNIT

SN74 LS93

MAX

mA
MHz

ns
ns

25
125

V
j.LA

0

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER

•

VI H

High-level input voltage

VI L

Low-level input voltage

VIK

Input clamp voltage

SN74LS90

SN54 LS92

SN74LS92

~M--IN---T-y-P-t--M-A--X~M--IN---T-y-P-t--M--A~X
2

Vcc

= MIN.

II

2

= -18 mA

Vcr. = MIN

V

0.8

V

-1.5

-1.5

V

3.4

V

1i-,1.,:,:0",L:...=_4
__
m_A_~::-+______
0_2_5____
0._4-+1______
0_2_5____
0_.4...;:

VIH = 2 V

IIOL=8mA~

iVI:=VILmax,

UNIT

0,7

2.5

VOH High-level output voltage
VOL Low-level output voltage

SN54LS90

I

0.350.51

v

0_.1-+1_ _ _ _ _ _ _ _ _ _ _ _0_,1---1

I nput current I-A_n....:v_r_e_se_t__+V....:C"-'C"--=_M_A_X....:.'--__V...,:I'-=__
7_V______________- t____________
II

at maximum
input voltage
High·level
input current

A input
B input

VCC = MAX.

ICC

0.2
0.4

0.2
0.4

20

20

VI = 2.7 V

40

40

80

80

-0.4

-0.4

Any reset
~A
__
in_p_u_t----i V CC = MAX.

B input

Any reset
Low·level
A input
VCC = MAX.
output current /---------j
B input
lOS

= 5.5 V

VI

VI = 0.4 V
-20

Short·circuit output current§ VCC = MAX
Supply current

Vcc = MAX,

See Note 3

-2.4

-2.4

-3.2

-3.2

-100

-100

-20

I 'LS90

9

15

9

15

I

9

15

9

15

'LS92

mA

j.LA

mA
mA
mA

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions,
tAil typical values are at V CC

=5

V. T A

= 25°C,

§ Not more than one output should be shorted at a time. and duration of the short-circuit should not exceed one second.
~ Outputs are tested at specified IOl plus the limit value of II l for the B input, This permits driving the B input while maintaining full fan·out
capability,
NOTE 3: ICC is measured with all outputs open. both RO inputs grounded following momentary connection to 4.5 V. and all other inputs
grounded.

107E

7-78

TEXAS I ....INSTRUMENTS
CORPORATED
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS90, SN54LS92, SN54LS93,
SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY
COUNTERS
REVISED OCTOBER 1976
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

SN54LS93

TEST CONDITIONSt
MIN

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOL low-level output voltage
Input current

2
Vee; MIN,

II ;-18mA

VCC; MIN,

VIH; 2 V,

VIL; VIL max,

IOH; -400 pA

Vee; MIN,

VIH;2V,

2.5

Vll; VIL max

2.7

3.4
0.25

!IOl;4mA'

MAX
0.8

V

-1.5

V
V

3.4

0.4

tlOl; 8 mA'

0.25

0.4

0.35

0.5

Any reset

Vee; MAX,

VI; 7V

0.1

0.1

Vee; MAX,

VI; 5.5 V

0.2

0.2

Vee; MAX,

V!;2.7V

V

mA

High-level

Any reset
A or

~

input

Any reset

Oui ~ut Curn3nt

UNIT
V

-1.5

A input

Vee; MAX,

VI; 0.4 V

20

20

40

80

-0.4

-0.4

-2.4

pA

-2.4

mA

15

mA

-1.61

-1.6

lIDS
lee

TYP:j:

2

A or B input

input current
Low-level

IlL

MIN

at maximum
input voltage

IIH

SN74LS93

MAX
0.7

VOH High-level output voltage

II

TYP:j:

iliA

Supply current

Vee; MAX,

9

See Note 3

9

15

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V, T A; 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
, QA outputs are tested at specified IOL plus the limit value for II L for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

switching characteristics, Vee
PARAMETER';

f max
tPLH

TO

(INPUT)

(OUTPUT)

A

QA

32

B

QB

16

A

tpHL
tpLH

QO

B

QB

B

Qe

tpHL
tPLH
tpHL
tPLH

tpLH

== maximum

RL; 2

kn

See Figure 1

'LS92

TYP MAX MIN
42

32

'LS93

TYP MAX MIN
42

32

16

TYP MAX
42

10

16

10

16

10

16

12

18

12

18

12

18

32

48

32

48

46

70

34

50

34

50

46

70

10

16

10

16

10

16

14

21

14

21

14

21

21

32

10

16

21

32

23

35

14

21

23

35

21

32

21

32

34

51

QO

23

35

23

35

34

51

Any

26

40

26

40

26

40

QA,QO

20

30

QB,QC

26

40

Set-to-9

UNIT

MHz

16

B

tpHL
41 f max

CL=15pF,

'LS90
MIN

Set-to-O

tpHL
tPHL

TEST CONDITIONS

QA

A

tpHL
tPLH

=5 V, TA = 25°C

FROM

ns
ns

•

ns
ns
ns
ns
ns

count frequency

tpLH == propagation delay time, low·to·high·level output
tpH L == propagation delay time, high·to·low·level output

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-79

TYPES SN5490A, SN5492A, SN5493A, SN54L90, SN54L93,
SN54LS90, SN54LS92, SN54LS93, SN7490A, SN7492A, SN7493A,
SN74L90, SN74L93, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE, AND BINARY COUNTERS
PARAMETER MEASUREMENT INFORMATION

TEST
POINT

FROM OUTPUT
UNDER TEST -

...---tI.-.-I.........,.;........,

eLI
-=-

(See Note B)

LOAD CIRCUIT

•
VOLTAGE WAVEFORMS

NOTES:

A. Input pulses are supplied by a generator having the following characteristics:
for '90A, '92A, '93A, tr';; 5 ns, tf .;; 5 ns, PRR = 1 MHz, duty cycle = 50%, Zout "" 50 ohms;
for 'L90, 'L93, tr';; 15 ns, tf';; 15 ns, PRR = 500 kHz, duty cycle = 50%, Zout "" 50 ohms;
for 'LS90, 'LS92, 'LS93, tr .;; 15 ns, tf .;; 5 ns, PRR = 1 MHz, duty cycle = 50%, Zout "" 50 ohms.
B. CL includes probe and jig capacitance.
C. C1 (30 pF) is applicable for testing 'L90 and 'L93.
D. All diodes are 1N916 or 1N3064.
E. Each reset input is tested separately with the other reset at 4.5 V.
F. Reference waveforms are shown with dashed lines.
G. For '90A, '92A, and '93A; Vref = 1.5 V. For 'L90, 'L93, 'LS90, 'LS92, and 'LS93; Vref = 1.3 V.

FIGURE 1

TEXAS INSTRUMENTS
7·80

INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

1076

TTL
MSI

TYPES SN5491A, SN54L91, SN54LS91, SN7491A, SN74L91, SN74LS91
8-BIT SHIFT REGISTERS
BULLETIN NO. DL-S 7611854, MARCH 1974-REVISED OCTOBER 1976

MSI TTL

1FT REGISTERS

for applications in
•

Digital Computer Systems

•

Data-Handling Systems

•

Control Systems

SN5491A, SN54LS91 •.. W PACKAGE
SN54L91, SN74L91 ..• T PACKAGE
FLAT PACKAGE (TOP VIEW)

SN5491A, SN54LS91 ... J PACKAGE
SN54L91, SN7491A,SN74L91, SN74LS91 ••• J OR N PACKAGE
DUAL·!N-LiNE PACKAGE (TOP VIEW)

FUNCTION TABLE
INPUTS
ATtn

OUTPUTS
AT tn+8

A

B

QH

H

H

H

L

L

X

L

H

X

L

L

H

OH

H = high, L = low,
X = irre!ev.::!!'1t

tn

NC

= Reference bit time,

clock low
t n +8 = Bit time after 8
low-to-high
clock transitions.

Vee

NC

NC

NC

positive logic: see function table

MAXIMUM
CLOCK
FREQUENCY

schematics of inputs and outputs

TYPICAL

'91A, 'L91

POWER

'LS91

EQUIVALENT OF EACH INPUT

EQUIVALENT OF EACH INPUT

DISSIPA TlON

'91A

18 MHz

175mW

'L91

6.5 MHz

17.5mW

18 MHz

60mW

'LS91

NC

NC-No internal connection

TYPICAL
TYPE

NC

vce~_Req

INPUT

__

description
These monolithic serial-in, serial-out, 8-bit shift registers utilize transistor-transistor logic (TTL) circuits
and are composed of eight R-S master-slave flip-flops,
input gating, and a clock driver. Single-rail data and
input control are gated through inputs A and Band
an internal inverter to form the complementary
inputs to the first bit of the shift register. Drive for
the internal common clock line is provided by an
inverting clock driver. This clock pulse inverter/driver
causes these circuits to sh"ift information one bit on
the positive edge of an input clock pulse.

•

'91AoReq = 4 kn NOM
'L91, Req = 40 kn NOM

'91A, 'L91

'LS91

TYPICAL OF BOTH OUTPUTS

TYPICAL OF BOTH OUTPUTS

Vee

Vee

OUTPUT

functional block diagram

'91A' R = 130

n

NOM

'L91,

n

NO.'VI

R = 500

(DUAL·IN·lINEI [FLAT PACKAGE]

A ......:..:11~21:....:[..:..:10:.;.1J
Q

1111 [121

(131 [131

QH

eK
Q 1141 [141 QH

CLOCK

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE B~X 5012

•

DALLAS, TEXAS 75222

7-81

TYPES SN5491A, SN7491A
8-BIT SH 1FT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage (see Note 2)
Operating free-air temperature range: SN5491A
SN7491A
Storage temperature range
NOTES:

7V
5.5V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
2. Input signals must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN5491A
MIN

NOM

4.5

Supply voltage, Vee

SN7491A
MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM

-400

Low-level output current, 10L

MAX

5

UNIT

5.25

V

-400

p.A

16

mA

16

Width of clock input pulse, tw

25

25

Setup time, tsu (see Figure 1)

25

25

ns

0

0

ns

Hold time, th (see Figure 1)

-55

Operating free-air temperature, T A

125

ns

0

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VOH

•

Low-level output voltage

MIN

NOM

SN7491A
MAX

2

MIN

NOM

Vee- MIN,

VIH-2V,

VIL = 0.8 V,

10H = -400p.A

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

10L = 16mA

2.4

MAX

3.5

0.8
2.4

0.2

3.5
0.2

0.4

UNIT
V

2
0.8

High-level output voltage

VOL

SN5491 A

TEST CONDITIONSt

PARAMETER

V
V

0.4

V

II

Input current at maximum input voltage

Vee= MAX, VI = 5.5 V

1

1

IIH

High-level input current

Vee - MAX, VI- 2.4 V

40

40

p.A

IlL

Low-level input current

Vee = MAX, VI = 0.4 V

-1.6

-1.6

mA

lOS

Short-circuit output currentS

Vee= MAX

-57

mA

lee

Supply current

Vee = MAX, See Note 3

58

mA

-20

-57
35

-18

50

35

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
V, T A = 25° C.
more than one output should be shorted at a time.

t All typical values are at V CC = 5
§ Not

NOTE 3:

ICC is measured after the eighth clock pulse with the output open and A and B inputs grounded.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER
f max

Maximum clock frequency

tpLH Propagation delay time, low-to-high-Ievel output
tpHL Propagation delay time, high-to-Iow-Ievel output

TEST CONDITIONS

MIN

TYP

CL = 15pF,

10

18

MAX UNIT
MHz

RL=4oon,

24

40

ns

See Figure 1

27

40

ns

1076

7-82

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54L91, SN74L91
8-BIT SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . .
Input voltage (see Note 2)
. . . . .
Operating free-air temperature range: SN54L91
SN74L91
Storage temperature range
NOTES:

8V

5.5V
G
-55°C to 125 e
oOe to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
2.

I nput signals must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN54L91
MIN
4.5

Supply voltage, Vee

NOM

SN74L91
MAX

MIN

5.5

4.75

5

NOM

Low-level output current, 10L

5.25

V
/.LA

3.6

mA

2

! High logic level
I Low logic level

Width of clock input pulse, tw(clock)
::;etup time, tsu (~ee Figure 1 j

ns

100

100

150

150

ns

120

120

ns

Hold time. th (see Figure 1)

0

0

-55

Operating free-air temperature, T A

UNIT

-200

5

-100

High-level output current, 10H

MAX

125

ns
70

0

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

SN54L91

TEST CONDITIONSt

PARAMETER

MIN

TYP:j:

SN74L91
MAX

2

MIN

TYP+ MAX

0.7
Vee- MIN,

VOL

Low-level output voltage

II

Input current at maximum input voltage

VIH-2V,

VIL = 0.7 V,

10H = MAX

Vee- MIN,

VIH - 2V

VIL = 0.7 V,

10L = MAX

Vee - MAX,

V,- 5.5 V

2.4

3.3

0.7
2.4

0.3

0.15

UNIT
V

2

0.2

100

V
V

3.2
0.4

V

100

/.LA

IIH

High-level input current

Vce = MAX,

VI = 2.4 V

10

10

/.LA

IlL

Low-level input current

Vee- MAX,

VI- 0.3 V

-0.18

-0.18

mA

lOS

Short-circuit output current

Vee = MAX

-15

mA

ICC

Supply current

Vce- MAX,

6.6

mA

-15

-3
See Note 3

3.5

-3

6.6

3.5

•

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V. TA = 25°C.
NOTE 3: ICC is measured after the eighth clock pulse with the outputs open and A and B inputs grounded.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER
f max

TEST CONDITIONS

Maximum clock frequency

MIN
3

TYP

Propagation delay time,
tpLH

eL=50pF,

low-to-high-Ievel output

MHz

55

100

ns

100

150

ns

See Figure 1

Propagation delay time,
tPHL

RL =4 kn,

MAX UNIT

6.5

high-to-Iow-Ievel output

076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-83

TYPES SN54LS91, SN74LS91
8-BIT SHIFT REGISTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Operating free-air temperature range: SN54LS91
SN74LS91
Storage temperature range
NOTES:

7V
7V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS91
MIN
Supply voltage, Vee

NOM

4.5

MIN

5.5

4.75

5

High-level output current, IOH

SN74LS91

MAX

NOM
5

-400

low-level output current. IOl

MAX

UNIT

5.25

V

-400

/J A
mA

4

8

Width of clock input pulse, tw

25

25

ns

Setup time, tsu (see Figure 1)

25

25

ns

0

0

Hold time, th (see Figure 1)
Operating free-air temperature. T A

-55

125

ns

0

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN74LS91

SN54LS91
TEST CONDITIONSt

PARAMETER

MIN

VIH High-level input voltage
Vil low-level input voltage

VOH High-level output voltage

Vee = MIN,

11=-18mA

Vee = MIN,

VIH = 2 V,

2.5

VI l = VI l max, IOH = -400 /JA
Vee = MIN,

VOL low-level output voltage

VIH - 2 V,

Vil = Vil max

Input current at

UNIT
V

0.7

0.8

V

-1.5

-1.5

V

3.5
0.25

IIOl - 4 mA

TYP:j: MAX

2

2.7
0.4

IIOl = 8mA

V

3.5
0.25

0.4

0.35

0.5

V

Vee = MAX,

VI = 7 V

0.1

0.1

mA

IIH

High-level input current

Vee = MAX,

VI=2.7V

20

20

III

low-level input current

Vee = MAX,

VI = 0.4 V

-0.4

-0.4

/J A
mA

lOS

Short·c:rcu:t output current §

ICC

Supply current

II

i

MIN

2

VIK I nput clamp voltage

•

TYP:j: MAX

maximum input voltage

1-20

, Vee= MAX
Vee = MAX,

See Note 3

-100, rnA

-100 1-20
12

20

12

20

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
= 5 V, T A = 25" C.

:j: All typical values are at V CC

§ Not more than one output should be shorted at a time, and du ration of the short-circuit should not exceed one second.
NOTE 3:

ICC is measured after the eighth clock pulse with the output open and A and B inputs grounded.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

7-84

TEST CONDITIONS

MIN

TYP

f max

Maximum clock frequency

el = 15pF,

10

18

tplH

Propagation delay time, low-to-high-Ievel output

Rl=2kn,

24

40

ns

tpHl

Propagation delay time, high-to-Iow-Ievel output

See Figure 1

27

40

ns

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

OALLAS, TEXAS 75222

MAX UNIT
MHz

107

TYPES SN5491A. SN54L91, SN54LS91, SN7491A. SN74L91, SN74LS91
8-BIT SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
VCC

=5

V OUTPUT

-

LOADCIRCuIT1 VCC

=5

-

-,

V

r---------,
I
I

PULSE

I

I

C

se;T
-=

GENERATOR r--------r-~~-~~
(See Note A)
INPUT A

IL _
Note B
~_Note
____
_D_ _ _ __

2.4 V

I
I
I
I
I
I
I
I

~

r-- --LO;:D~!;:U~;--- - - ,

~L

1
---- - ....JI

SAME AS LOAD CIRCUIT

--- -- -

TCC"T
I I'T
.lI-o.lIIl .....
_ IO
•• 1 .....
_I
_
.

1

CLOCK-PULSE
INPUT

INPUTA

2

thru

7

8

9

thru

15

16

17

18

19 thru 23

24

25

26

27

n
n---n n n----n n n n n---JlJlJlJlJl
I U L__ J U U L__ J U U U U L__

L____

OUTPUTQH _ _ _ _ _ _ _

____ ~ ____________
____ s - L

Sl____
TYPICAL INPUT/OUTPUT WAVEFORMS

J""'!'_ _--3V

CLOCK
INPUT
INPUT

I

-1-- I

-OV

I
I

~-------3V

I
I
I

tpH L
tp LH

INPUT
AOR B

1

•

1

---t--J

-I -

--t---I

-

- - : - th

-1- -

-

-

-

-- -

-

- -

0V

---3V

INPUT
AOR 13
~-------OV

PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS
NOTES:

SWITCHING TIMES VOLTAGE WAVEFORMS

n.

A. The generator has the following characteristics: tw(clock) = 500 ns, PRR ,,;; 1 MHz, Zout'" 50
For SN5491A/SN7491A,
tr";; 10 ns and tf ,,;; 10 ns; for SN54L91/SN74L91, tr";; 15 ns and tf ,,;; 15 ns; and for SN54LS91/SN74LS91, tr = 15 ns, and
B.
C.
D.
E.

CL includes probe and jig capacitance.
All diodes are 1N3064or 1N916.
C1 = 30 pF and is used for SN54L91/SN74L91 only.
For SN5491A/SN7491A, Vref = 1.5 V; for SN54L91/SN74L91 and SN54LS91/SN74LS91, Vref

= 1.3 V.

FIGURE l-SWITCHING TIMES

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-85

TYPES SN5494, SN7494
4-81T SHIFT REGISTERS

TTL
MSI

BULLETIN NO. DL-S 7211812, DECEMBER 1972

TTL MSI PARALLEL-IN SERIAL-OUT REGISTERS
for application as
Dual-Source, Parallel-To-Serial Converter
• Serial-In Serial-Out Register

•

description
SN5494 •.• J OR W PACKAGE
SN7494 •.• J OR N PACKAGE
(TOP VIEW)

These monolithic shift registers which utilize transistor-transistor logic (TTL) circuits in the familiar
Series 54/74 configuration, are composed of four R-S
master-slave flip-flops, four AND-DR-INVERT gates,
and four inverter-drivers. Internal interconnections of
these functions provide a versatile register which
performs right-shift operations as a serial-in, serial-out
register or as a dual-source, parallel-to-serial converter. A number of these registers may be connected in
series to form an n-bit register.

P2A

PE2

P2B

P2C

GND

P2D

P1A

P1B

P1C

P1D

VCC

PE1

CLEAR OUTPUT

All flip-flops are simultaneously set to a low output
level by applying a high-level voltage to the clear
input while the internal presets are inactive (high).
See the preset function table below. Clearing is
independent of the level of the clock input.
The register may be parallel loaded by using the clear
input in conjunction with the preset inputs. After
clearing all stages to low output levels, data to be
loaded is applied to either the P1 or P2 inputs of each
register stage (A, B, C, and D) with the corresponding
preset enable input, PE1 or PE2, high. Presetting,like
clearing, is independent of the level of the clock
input.

CLOCK

positive logic: see function tables

Transfer of information to the outputs occurs on the positive-going edge of the clock pulse. The proper information
must be setup at the R-S inputs of each flip-flop prior to the rising edge of the clock input waveform. The serial input
provides this information for the first flip-flop, while the outputs of the subsequent flip-flops provide information for
the remaining R-S inputs. The clear input must be at a low level and the internal presets must be inactive (high) when
clocking occurs.

•

PRESET FUNCTION TABLE

REGISTER FUNCTION TABLE

(BIT A, TYPICAL OF ALL)
PRESET iNPUTS

iNTERNAL

INTERNAL

!NPUTS

~RESETS

PE1 P1A PE2 P2A PRESET A

A

B

C

0

' INTERNAL OUTPUTS
QA

QB

QC

X
X

X
X

L

L

L

L

H

H

H

H

GAO
H

GBO
GBO

Geo
H

QOO

H

QAn

QBn

Qen

L

GAn

GBn

QCn

L

X

H (inactive)

H

H

H

H

H

L

X
X

X

L

H (inactive)

L

L

L

L

L

X
X

L

L

X

H (inactive)

H

H

H

H

L

L

L

L

H (inactive)

L

H

L

H

L

L

X
X

X

L (active)

H

H

H

H

L

t

H

H

L (active)

H

H

H

H

L

t

L

L

H

H

X
X

X

X

H

OUTPUT

CLEAR CLOCK SERIAL

I

Qo

GOO

level (steady state), L = low level (steady state), X = irrelevant, t = transition from low to high level
0AO, 0BO, 0CO, 0DO = the level of 0A, 0B, 0C, or 0D, respectively, before the indicated steadY'state input conditions were established.
0An, 0Bn' 0Cn = the level of 0A, 0B, or 0C, respectively, before the most-recent t transition of the clock.
H

= high

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
5.5 V
-55°C to 125°C
. O°C to 70°C
-65°C to 150°C

Supply voltage, VCC (see Note 1)
....... .
Input voltage (see Note 2)
. . . . . . . .
Operating free-air temperature range: SN5494 Circuits
SN7494 Circuits
Storage temperature range
NOTES:

1. Voltage values are with respect to network ground terminal.

2. Input voltage must be zero or positive with respect to network ground terminal.

1076

7·86

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN5494, SN7494
4-BIT SHIFT REGISTERS
functional block diagram
PRESETS

1\

/
P2A
(16)

P1A
(1)

P1B
(2)

P2B
(14)

\
P2C

P1D
(4)
(13)

P1C
(3)

P2D
(11)

PRESET {PE2 (15)
ENABLE
(6)
INPUTS
PE1~~----+__--~-+------+-~---+-+----~~~-+-+------~

...--------1 S

S

OB

S

CK

CK

----+--1 R
CLEAR

(9)

OUTPUT

CK

R

;0---.....

aD

S

R
CLEAR

CLEAR

CLEAR

(8)

CLOCK

-+ ...

•

I

dynamic input activated by transition from a high level to a low level

I

schematics of inputs and output
EQUIVALENT OF EACH INPUT

OUTPUT

Vee

------....------- Vee

INPUT

. . .- - - - - OUTPUT

kn
= 4 kn

PE1 and PE2: Req = 1

NOM

All others: Req

NOM

1272

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-87

TYPES SN5494, SN1494
4-811 SHIFT REGISTERS
recommended operating conditions
SN5494
MIN
4.5

Supply voltage, Vee

SN7494

NOM

MAX

MIN

5.5

4.75

5

NOM
5

-400

High-level output current, IOH

16

Low-level output current, IOL

MAX

UNIT

5.25

V

-400

folA

16

mA

Width of clock pulse, tw(clock)

35

35

ns

Width of clear pulse, tw(clearl

30

30

ns
ns

30

30

High-level data

35

35

Low-level data

25

25

0

0

Width of preset pulse, tw(preset)

I
I

Setup time, tsu
Hold time, th

-55

Operating free-air temperature, T A

125

ns
ns
70

0

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

•

VIH

High-level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

SN5494

TEST CONDITIONSt

PARAMETER

MIN

TYP:j:

MAX

MIN

2

SN7494
UNIT
TYp:j: MAX
V

2
0.8

Vee= MIN,

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH

High-level input current

Presets 1 and 2
Other inputs
Presets 1 and 2

IOH = -400folA

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

IOL = 16mA

2.4

3.5

2.4

0.2

0.4

Vee = MAX, VI = 5.5 V
Vee= MAX, VI = 2.4 V

IlL

Low-level input current

lOS

Short·circuit output current §

Vee = MAX

lee

Supply current

Vee = MAX,

Other inputs

VIH =2V,

VIL = 0.8 V,

Vee = MAX, VI = 0.4 V

3.5
0.2

0.4

1

1

160

160
40

-6.4

-6.4

-1.6

-1.6

-57
35

-18

50

35

V
V

40

-20
See Note 3

0.8

V
mA
folA
mA

-57

mA

58

mA

:For co~ditions shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions.
+AII tYPical values are at Vee = 5 V, T A = 25 e.
§Not more than one output should be shorted at a time.
NOTE 3: iCC is measured with the outputs ooero. clear grounded following momentary application of 4.5 V, both preset-enable inputs
grounded, and all other inputs at 4.5 V.

switching characteristics, Vee

= 5 V, TA = 25°e
TEST CONDITIONS

PARAMETER
f max

Propagation delay time, low-to-high-Ievel
tpLH

I

output from clock
Propgaation delay time, high-to-Iow-Ievel

tpHL

eL=15pF,

output.from clock

RL = 400

MAX UNIT
MHz

n,

25

40

ns

25

40

ns

35

ns

40

ns

I

output from preset
Propagation delay time, high-to-Iow-Ievel

tpHL

TYP

See Note 4

Propagation delay time, low-to-high-Ievel
tpLH

MIN
10

Maximum clock frequency

output from clear

NOTE 4:

Load circuit and voltage waveforms are shown on page 3-10.

1076

7-88

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN5495A, SN54L95, SN54LS95B,
SN7495A, SN74L95, SN74LS95B
4-BIT PARALLEL-ACCESS SHIFT REGISTERS

TTL
MSI

BULLETIN NO. DL-S 7611872. MARCH 1974-REVISEDOCTOBER 1976

TYPE
'95A
'L95
'LS95B

TYPICAL MAXIMUM

TYPICAL

SN5495A, SN54LS95B .•• J OR W PACKAGE
SN7495A, SN74LS95B .•. J OR N PACKAGE
(TOP VIEW)

CLOCK FREQUENCY POWER DISSIPATION
36 MHz
195mW
19mW
5MHz
36 MHz
65mW

OUTPUTS

Vee

description

CLOCK 2

~ ~;~~i ~~~~J
n

12

These 4-bit registers feature parallel and serial inputs,
parallel outputs, mode control, and two clock input.s.
The registers have three modes of operation:
Parallel (broadside) load
Shift right (the direction aA toward aD)
Shift left (the direction aD toward aA)
Parallel loading is accomplished by applying the four
bits of data and taking the mode control input high.
The data is loaded into the associated flip-flops and
appears at the outputs after the high-to-Iow transition
of the clock-2 input. During loading, the entry of
serial data is inhibited.

positive logic: see function table

SN54L95 ••• J OR T PACKAGE
SN74L95 ••• J OR N PACKAGE
(TOP VIEW)

Shift right is accomplished on the high-to-Iow transition of clock 1 when the mode control is low; shift
left is accomplished on the high-to-Iow transition of
clock 2 when the mode control is high by connecting
the output of each flip-flop to the parallel input of
the previous flip-flop (aD to input C, etc.) and serial
data is entered at input O. The clock input may be
applied commonly to clock 1 and clock 2 if both
modes can be clocked from the same source. Changes
at the mode control input shou Id normally be made
while both clock inputs are low; however, conditions
described in the last three lines of the function table
will also ensure that register contents are protected.

OUTPUTS

CLOCK 2

~7~H~~i

INPUT
A

•

positive logic: see function table

FUNCTION TABLE
INPUTS
MODE

CLOCKS

SERIAL

OUTPUTS
PARALLEL
B

C

D

QA

QB

Qc

H

H

X

X

X

X

X

X

QAO

H

~

X

X

a

b

c

d

a

QBO
b

Qeo QDO
c
d

CONTROL 21L) 1.IR)

A

QD

H

~

X

X

QBt

Qe t

Qot

d

QBn

L

L

H

X

X

X

X

X

L

X

-I-

H

X

X

X

X

QBn

Oen

L

X

-I-

L

X

X

X

X

QAO QBO
H
QAn
L
QAn

QBn

Qen

t

L

L

X

X

X

X

X

QAO

QBO

Qeo QOO

+

L

L

X

X

X

X

X

QAO

QBO Oeo QOO

Qen QO n

d

Qeo QOO

-I-

L

H

X

X

X

X

X

QAO

QBO

Qeo QOO

t

H

L

X

X

X

X

X

QAO

QBO

Qeo QOO

t

H

H

X

X

X

X

X

QAO

QBO

Qeo QOO

tShifting left requires external connection of QB to A, QC to B, and QD to C. Senal data

IS

entered at input D.

= high level (steady state), L = low level (steady state), X = irrelevant (any input, including transitions)
= transition from high to low level, t = transition from low to high level
a. b, c, d = the level of steady-state input at inputs A, B. C, or D, respectively.
QAO, QBO, QCO, QDO = the level of QA. QB. QC. or QD. respectively. before the indicated steady-state input conditions were
H
~

QAn. QBn. QCn. QDn = the level of QA •.Q B• QC. or QD. respectively. before the most-recent

~

established.

transition of the clock.

1076

TEXAS INSTRUMENTS
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POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-89

TYPES SN5495A, SN54L95, SN54LS95B, SN7495A, SN74L95, SN74LS95B
4-BI1 PARALLEL-ACCESS SHIFT REGISTERS
REVISED OCTOBER 1976

functional block diagram

(,95A,'LS95B) !'L95J

CLOCK 1 ,91[7]
RIGHT -5HI FT---r---;......./
ClOCK2

(8)[8!

LEFT-SH1FT-----L-./

(10119}

schematics of inputs and outputs
'95A

'L95

'95A, 'L95

EQUIVALENT OF EACH INPUT

EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

VCC~--

VCC1
3-Req
INPUT

--

Mode control: Req = 3 kn NOM
Clock inputs: Req = 4 kn NOM
All other inputs: Req = 6 kn NOM

•

Req

INPUT

--

Mode control: Req = 20 kn NOM
All other inputs: Req = 40 kn NOM

'95A: R = 100 n
'L95: R = 500 n

'LS95B

'LS95B

'LS95B

EQUIVALENT OF CLOCK
AND MODE CONTROL INPUTS

EQUIVALENT OF DATA
AND SERIAL INPUTS

TYPICAL OF ALL OUTPUTS
----'P--VCC

VCC~-­

VCC:E--

17
INPUT

n

NOM

u

~15

__
--

kn NOM

'N'UTO--

L------""---OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN54' SN54L' SN54LS' SN74' SN74L' SN74LS' UNIT
Supply voltage, V CC (see Note 1)

7

Input voltage (see Note 2)

5.5

I nteremitter voltage (see Note 3)

5.5

Operating free-air temperature range
Storage temperature range
NOTES:

8
5,5

7

7

8

7

V

7

5,5

5.5
5.5

7

V

5.5
-55 to 125
-65 to 150

5:5

o to 70
-65 to 150

V

°c
°c

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. For the 'L95, input voltages must be zero or positive with respect to network ground terminal.

3. This is the voltage between two emitters of a multiple-emitter input transistor. This rating applies between the clock-2 input and
the mode control input of the '95A and 'L95.

1076

7-90

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN5495A. SN7495A
4-81T PARALLEL-ACCESS SHIFT REGISTERS
REVISED MARCH 1974

recommended operating conditions
SN5495A
MIN
Supply voltage, VCC

4.5

NOM
5

High-level output current, IOH

SN7495A
MAX

MIN

5.5

4.75

Low-level output current, IOL

5.25

5

-800

V

-800

16

0

Clock frequency, fclock

UNIT

MAX

NOM

25

0

J.i.A

16

mA

25

MHz

Width of clock pulse, tw(clock) (see Figure 1)

20

20

Setup time, high-level or low-level data, tsu (see Figure 1)

15

15

ns

0

0

ns

Time to enable clock 1, tenable 1 (see Figure 2)

15

15

ns

Time to enable clock 2, tenable 2 (see Figure 2)

15

15

ns

Time to inhibit clock 1, tinhibit 1 (see Figure 2)

5

5

ns

Time to inhibit clock 2, tinhibit 2 (see Figure 2)

5

5

Hold time, high-level or .Iow-Ievel data, th (see Figure 1)

..

+i ........ -I= ..

..

~

.,.

I.

+ ......

."

- 55

ns

ns

n

~n

IV

I

0,..

'-'

I

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

VOL

II = -12 mA

VCC= MIN,

VIH=2V,

VIL = 0.8 V,

10H = -800J.i.A

VCC= MIN,

VIH = 2 V,

VIL = 0.8 V,

10L = 16mA

2.4

Low-level output voltage

TYP+

SN7495A
MAX

MIN

V
V

-1.5

-1.5

V

3.4

2.4

3.4

V

I

0.4

1

0.2

i

0.4

1

40

40

80

80

-1.6

-1.6

-3.2

-3.2

Vec = MAX, VI = 2.4 V

Serial, A, B, C, D,
Clock 1 or 2

Vee= MAX,

VI=0.4V

Mode control

lOS

Short-circuit output current§

VCC = MAX

ICC

Supply current

VCC - MAX, See Note 4

V

mA

I

J.i.A

Mode control

input current

UN!T

0.8

Vec= MAX, VI = 5.5V

Clock 1 or 2

MAX

2

Serial, A, B, C, D,

input current

TYP+

0.8

0.2

maximum input voltage

Low-level
IlL

VCC - MIN,

High-level output voltage

High-level
IIH

MIN
2

Input current at

II

SN5495A

TEST COND!T!ONSt

PARAMETER

-18

-57
39

-18

63

39

mA

-57

mA

63

mA

•

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC

=5

V, T A

= 25

0

C.

§ Not more than one output should be shorted at a time.
NOTE 4:

ICC is measured with all outputs and serial input open; A, B, C, and D inputs grounded; mode control at 4.5 V; and a momentary
3 V, then ground, applied to both clock inputs.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

f max

Maximum clock frequency

tpLH

Propagation delay time, low-to-high-Ievel output from clock

eL = 15 pF,
See Figure 1

tpHL Propagation delay time, high-to-Iow-Ievel output from clock

RL =400

n,

MIN
25

TYP

MAX

UNIT
MHz

36
18

27

ns

21

32

ns

1076

TEXAS INCORPORATED
INSTRUMENTS
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DALLAS, TEXAS 75222

7-91

TYPES SN54L95, SN74L95
4-81T PARALLEL-ACCESS SHIFT REGISTERS
recommended operating conditions
SN74L95

SN54L95
MIN
Supply voltage, V CC

NOM

4.5

MAX

MIN

5.5

4.75

5

NOM

5.25

V
IlA

2

Low-level output current, 10L
Clock frequency, fclock

3

0

UNIT

-200

5

-100

High-level output current, 10H

MAX

0

3.6

mA

3

MHz

Width of clock pulse, tw(clock) (see Figure 1)

200

200

Setup time, high-level data, tsu (see Figure 1)

100

100

ns
ns

Setup time, low-level data, tsu (see Figure 1)

120

120

ns

0

0

ns

Time to enable clock 1, tenable 1 (see Figure 2)

225

225

ns

Time to enable clock 2, tenable 2 (see Figure 2)

200

200

ns

Time to inhibit clock 1, tinhibit 1 (see Figure 2)

100

100

ns

Hold time, high-level or low-level data, th (see Figure 1 )

0

Time to inhibit clock 2, tinhibit 2 (see Figure 2)

ns

0
125

-55

Operating free-air temperature, T A

0

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VOH

•

VCC = MIN,

Low-level output voltage

II

at maximum

Clock lor 2

input voltage

Mode control

High-level
input current
Low-level
IlL

l

Input current

TYP+

SN74L95
MAX

MIN

TYP+

VIH = 2 V,

VIL = 0.7 V,

10H = MAX

VCC = MIN,

VIH=2V,

VIL = 0.7 V,

10L = MAX

2.4

3.3
0.3

0.15

VCC = MAX, VI = 5.5V

Serial, A, B, C, 0,

Serial, A, B, C, 0,
clock 1 or 2
Mode control

VCC

= MAX,

VI

= 0.3 V

i

i

Short-circuit output current §

VCC = MAX

ICC

Supply current

VCC = MAX, See Note 4

0.4

100

100

200

200

10

10
20

-0.18

-0.18

-0.36

-0.361

-15

-3

lOS

0.2

3.8

-3

9

3.8

V
V

3.2

20

VCC = MAX, VI = 2.4 V

Mode control

UNIT
V

0.7
2.4

Serial, A, B, C, 0,

Clock 1 or 2

MAX

2
0.7

VOL

IIH

MIN
2

High-level output voltage

I nput current

SN54L95

TEST CONDITIONSt

PARAMETER

V

IlA

IlA

mA

1

-15

mA

9

mA

I

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 4: Ice is measured with all outputs and serial input open; A, S, e,. and D inputs grounded; mode control at 4.5 V; and a momentary

3 V, then ground, applied to both clock inputs.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

f max

Maximum clock frequency

tpLH

Propagation delay time, low-to-high-Ievel output from clock

CL

= 5OpF,

See Figure 1

tpHL Propagation delay time, high-to-Iow-Ievel output from clock

RL =4 kil,

MIN
3

TYP

MAX UNIT
MHz

5
115

200

ns

125

200

ns

1076

7-92

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS95B, SN74LS95B
4-BIT PARALLEL-ACCESS SHIFT REGISTERS
REVISED OCTOBER 1976

recommended operating conditions
SN54LS95B
MIN
Supply voltage, Vee

4.5

NOM

MIN

5.5

4.75

5

High-level output current, 10H

SN74LS95B

MAX

NOM
5

-400

Low-level output current, 10L

4

Clock frequency, fclock

0

25

0

UNIT

MAX
5.25

V

-400

/LA

8

mA

25

MHz

Width of clock pulse, tw(clock) (see Figure 1)

25

25

Setup time, high-level or low-level data, tsu (see Figure 1)

20

20

ns

Hold time, high-level or low·level data, th (see Figure 1)

20

10

ns

Time to enable clock 1, tenable 1 (see Figure 2)

20

20

ns

Time to enable clock 2, tenable 2 (see Figure 2)

20

20

ns

Time to inhibit clock 1, tjnhibit 1 (see Figure 2)

20

20

ns

Time to inhibit clock 2, tinhibit 2 (see Figure 2)

20

20

ns

--,.., ...
- ..... - TA
! Op",,,ung
Ir"" air L"mp"ratur",
~

_.r:;

, .. 5

5 ...

o.

'''1

ns

..,,0

n

Or-

"

!

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VI H

High-level input voltage

VI L

Low-level input voltage

V IK

I nput clamp voltage

2

Vee= MIN,
VIL = VIL max,

0.8

V

-1.5

-1.5

V

2.7

0.25

0.4

3.4

V

0.25

0.4

0.35

0.5

11-------+----------1--------1

Input current at

Vee = MAX,

High-level
input cu rrent
input current

V

I

0.1

0.1

mA

Vee= MAX,

VI = 2.7 V

20

20

/LA

Vee = MAX,

VI = 0.4 V

-0.4

-0.4

mA

-100

mA

21

mA

Low-level
IlL

V

0.7

3.4

Vee = MIN,
IIOL = 4 mA
V;H = 2 V,
VIL = VIL max 10L = 8 mA

Lovl.J-!eve! output vo!tage

maximum input voltage
IIH

2.5

10H = -400/LA

SN74LS95B
MIN TYP:j: MAX UNIT

2

11'= -18 mA

Vee- MIN,

VOH High-level output voltage

I VOL

SN54LS95B
MIN TYP:j: MAX

TEST eONDITIONSt

lOS

Short-circuit output current§

Vee= MAX

ICC

Supply current

Vee - MAX,

-20

-100

See Note 4

13

-20

21

13

•

:For conditions shown as MIN or MAX, use othe appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25 C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 4: ICC is measured with all outputs and serial input open; A, B, C, and D inputs grounded; mode control at 4.5 V; and a momentary
3 V, then ground, applied to both clock inputs.

switch ing characteristics, Vee

= 5 V, TA = 25° C

PARAMETER

TEST CONDITIONS

f max

Maximum clock frequency

tpLH

Propagation delay time, low-to-high-Ievel output from clock

eL = 15 pF,
See Figure 1

tpHL Propagation delay time, high-to-Iow·level output from clock

1076

RL=2kn,

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

MIN
25

TYP

MAX UNIT

36

MHz

18

27

ns

21

32

ns

7-93

TYPES SN5495A, SN54L95, SN54LS95B, SN7495A, SN74L95, SN74LS95B
4-BIT PARALLEL-ACCESS SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
TEST
POINT

~~~~~~;:~T

____

(See Note CL
B)

VCC

RL

__

r

~~~~

T

~ C1
(See Note C)

;

':'

(See Note D)

-I~~"~

LOAD CIRCUIT

!tr - ,

DATA
INPUT

I--

--I I-- tf

I

l"V-re-f---""'f= - - --::
I- t i

J"10%-9O'J(,---~-r-ef"110%
I-

....eoJ

tw(data)

I

-I

tsu

tsu

thT

I

I

I

th

Vref
1---4---

CLOCK 1 OR 2
INPUT

I

I

OV

tw(clock)

I

! ~,-v_re_f_...:..!_.JI.~re~
tPHL

NOTES:

•

I----t-

~

VOH

n _ Voc

tPLH

n.

A. Input pulses are supplied by a generator having the following characteristics: tr <;;; 10 ns, tf <;;; 10 ns, and Zout '" 50
For the
data pulse generator, PRR = 500 kHz; for the clock pulse generator, PRR = 1 MHz. When testing f max , vary PRR. For '95A,
tw(data);;' 20 ns; tw(clock);;' 15 ns. For 'L95, tw(data);;' 150 ns; tw(clock) ;;'200 ns. For 'LS95B, tw(data);;' 20 ns,
tw(clock) ;;. 15 ns.
B. CL includes probe and jig capacitance.
C. C1 (30 pF) is applicable for testing' L95.
D. All diodes are 1N916 or 1N3064.
E. For '95A, V ref = 1.5 V; for 'L95 and 'LS95B, V ref = 1.3 V.

VOLTAGE WAVEFORMS
FIGURE 1-SWITCHING TIMES
- - - - - - - - - - VIH

SERIAL
INPUT

_ _ _ _ _- - - VIL
_--_

,._ _ _ _ _ VIH

\\.-_--J1

' -_ _ _ _ _ _ _ VIL

INPUT

'-------..j~ :::

CLOCK 2 tinhibit 2
INPUT
QA OUTPUT

_ _ _ _ _ _ _J

NOTES:

- - - VIL

1- - \

A. Input A is at a low level.
B. For '95A, Vref = 1.5 V; for 'L95 and 'LS95B, Vref

~

1

_ _ _ _J

L

VOH
VOL

= 1.3 V.

VOLTAGE WAVEFORMS
FIGURE 2-CLOCK ENABLE/INHIBIT TIMES

1076

7·94

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN5496. SN54L96. SN54LS96.
SN7496. SN74L96, SN74LS96
5-81T SHIFT REGISTERS

TTL
MSI

BULLETIN NO. DL-S 7611821, MARCH 1974-REVISED OCTOBER 1976

•

N-Bit Serial-To-Parallel Converter

•

N-Bit Parallel-To-Serial Converter

•

N-Bit Storage Register

SN5496, SN54LS96 ••. J OR W PACKAGE
SN54L96 .•• J PACKAGE
SN7496, SN74L96, SN74LS96 ... J OR N PACKAGE
(TOP VIEW)

TYPICAL
TYPE PROPAGATION

TYPICAL

DELAY TIME

POWER DISSIPAT!ON

'96

25 ns

240mW

'L96

50 ns

120mW

'LS96

25 ns

60mW

description
These shift registers consist of five R-S master-slave
flip-flops connected to perform parallel-to-serial or
serial-to-parallel conversion of binary data. Since both
inputs and outputs for all flip-flops are accessible,
parallel-in/parallel-out or serial-in/serial-out operation
may

CLOCK

b~ p~rformed.

• ABC

,

VCC

~

•

D E . !,_R~~EI

'--------y---J

PRESET

~NP,~L.t:

PRESET

All flip-flops are simultaneously set to a low output
positive logic: see function
level by applying a low-level voltage to the clear input
while the preset is inactive (low). Clearing is independent of the level of the clock input.

table

The register may be parallel loaded by using the clear input in conjunction with the preset inputs. After clearing all
stages to low output levels, data to be loaded is applied to the individual preset inputs (A, B, C, D, and E) and a
high-level load pulse is applied to the preset enable input. Presetting like clearing is independent of the level of the clock
input.
Transfer of information to the outputs occurs on the positive-going edge of the clock pulse. The proper information
must be set up at the R-S inputs of each flip-flop prior to the rising edge of the clock input waveform. The serial input
provides this information to the first flip-flop, while the outputs of the subsequent flip-flops provide information for
the remaining R-S inputs. The clear input must be high and the preset or preset enable inputs must be low when
clocking occurs.

FUNCTION TABLE
OUTPUTS

INPUTS
CLEAR

PRESET

PRESET
ENABLE

A

B

L

L

X

X

L

X

L

L

H

H

H

H

CLOCK SERIAL

D

E

QC

QD

QE

X

X

X

X

X

L

L

L

L

L

L

L

L

X

X

L

L

L

L

L

H

H

H

X

X

H

H

H

H

H

QAO
H

QBO

C

•

H

H

L

L

L

L

L

L

X

H

H

H

L

H

L

H

L

X

H

L

X

X

X

X

X

L

X

H

L

X

X

X

X

X

t

H

H

L

X

X

X

X

X

t

L

QA

QB

QBO

QAO QBO
H
QAn

L

QAn

QCO QOO
H
QOO

QEO
H

Oeo

QOO

QEO

QBn

QCn QDn

QBn

QCn QDn

H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
t = transition from low to high level
QAO, QBO, etc = the level of QA, QB, etc, respectively before the indicated steady-state input conditions were established.
QAn, QBn, etc = the level of QA, QB, etc, respectively before the most-recent t transition of the clocl<.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-9S

TYPES SN5496. SN54L96. SN54LS96.
SN7496. SN74L96. SN74LS96
5-81T SHIFT REGISTERS
typical clear, shift, preset, and shift sequences
CLOCK

CLEAR

-U
I

SERIAL
INPUT

1
1

I
rt--lL._________________________________________________________
_--+-1-----'. I
.

n 1.. ______________

PRESET:
1
ENABLE ---TI------+-------------------------~i

:

A

ri;l~___________________

1

PRESETS

1

~~--------------------

:

B

I

c

1

I

l

L

1

D

:

:

I

:

I
---,

OA __

__

:

~I

____

I

-- -1

00 ___ I

•

:

.----,IL.___________________________ I I11..__________________

~I

~,

~.----,

--~

Oc _

1 L

1

OB ___ I

OUTPUTS

~~-------------

I

; - 1_ _. . . . . ,

I

I
I

:I

.----,
I
I

I

.----,
I

--~

I

I----,L--..JI

r--1

I

OE ___ I

'--_________

I

1-------..
SHIFT

1

I

1

- - - - - - - - - - - -..

CLEAR

~.
J
H ~

I

LH

H

L

1 - SHIFT-

PRESET

functional block diagram

~.

dynamic input activated by transition from a high level to a low level.

1076

7·96

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN549S, SN54L9S, SN54LS9S,
SN749S, SN74L9S, SN74LS9S
5-81T SHIFT REGISTERS
REVISED OCTOBER 1976

schematics of inputs and outputs
'96

'96

TYPICAL OF
ALL OUTPUTS

EQUIVALENT OF
EACH INPUT

Vcc

-----4~--

INPUT

INPUT

Req NOM

800 n
4 kn

Preset enable
All others

'L96

'L96
TYPICAL OF
ALL OUTPUTS

EQUIVALENT OF
EACH INPUT

---s

--~VCC

V CC -----4~--

2600 NOM

_t(oUTeUT

iNPUT

INPUT

II

Req NOM

Preset enable
All others

1.6
8

kn
kn

'LS96

'LS96
TYPICAL OFALL OUTPUTS

EQUIVALENT OF
EACH INPUT

-----~~-VCC

V C C - - -....- -

Req

INPUT

---4H.... - - - . ' - - -....-

INPUT

Req NOM

Serial
Clock, Clear
Preset enable

25 kn
17 kn
3.4 kn

OUTPUT

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-97

TYPES SN5496. SN7496
5-BIT SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage (see Note 2). . . .'. . . . .
Operating free-air temper"ture range: SN5496
SN7496
Storage temperature range

7V
5.5 V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

NOTES: 1, Voltage values are with respect to network ground terminal.
2. Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN7496

SN5496

MIN
4.5

Supply voltage, Vee

NOM

MAX

MIN

NOM

5.5

4.75

5

5

-400

High-level output current, 10H

16

Low-level output current, 10L
0

Clock frequency, fclock

10

0

MAX

UNIT

5.25

V

-400

!J.A

16

mA

10

MHz

Width of clock input pulse, tw(clock)

35

35

ns

Width of preset and clear input pulse, tw

30

30

ns

Serial input setup time, tsu (see Figure 1)

30

30

ns

0

0

Serial input hold time, th (see Figure 1)
Operating free-air temperature, T A

-55

125

ns
70

0

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

II

TEST CONDITIONSt

VIH

High-level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

Input current at maximum input voltage

SN5496

MIN

TYPt

MAX

2

High-level input current

Vee - MIN,

VIH-2V,

VIL = 0.8 V,

10H = -4oo!J.A

Vee- MIN,

VIH - 2 V,

VIL = 0.8 V,

10L = 16mA

Vee = MAX,

VI = 5.5 V

Vee= MAX,

Vi = 2.4 V

2.4

3.4

preset enable

I

preset enable

Vee = MAX,

VI = 0.4 V

0.4

Short-circuit output current§

Vee = MAX

ICC

Supply current

Vee- MAX, See Note 3

0.2

0.4
1

40

40

200

200

-1.6

-1.6

-8

-8

-57

-20
48

-18
48

68

V
V

3.4

1

preset enable
lOS

0.8
2.4

0.2

any input except
Low-level input current

V

2

preset enable

IlL

SN7496
UNIT
TYP:j: MAX

0.8

any input except
, IIH

MIN

V
mA

!l.A.

mA

-57

mA

79

mA

tFor conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions.
0
tAli typical values are at V CC = 5 V, T A = 25 C.
§ Not more than one output should be shorted at a time.
NOTE 3: ICC is measured with the clear input grounded and all other inputs and outputs open.

switching characteristics, Vee

=

5 V, TA = 25°e

PARAMETER
tPLH

TEST CONDITIONS

Propagation delay time, low-to-high-Ievel output from clock

tpHL Propagation delay time, high-to-Iow-Ievel output from clock
tPLH Propagation delay time, low-to-high-Ievel output from preset or preset enable
tpHL Propagation delay time, high-to-Iow-Ievel output from clear

7-98

eL=15pF,
RL=4oon,
See Figure 1

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

MIN

TYP

MAX UNIT

25

40

ns

25

40

ns

28

35

ns

55

ns

I

TYPES SN54L96. SN74L96
5-811 SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . .
Input voltage (see Note 2)
. . . . .
Operating free·air temperature range: SN54L96
SN74L96
Storage temperature range
NOTES:

7V
5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

1. Voltage values are witR respect to net'l\Iork ground terminal.
2. Input voltage must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN54L96

SN74L96
1-------+----------1
UNIT
MIN
NOM

4.5

Supply voltage, V CC

MAX

MIN

5.5

4.75

5

High·level output current, 10H

NOM

-200

Low-level output current, 10L

o

Clock frequency, fclock
Width of clock, preset, or clear input pulse, tw

100

Serial input setup t!me, tsu (~ee Figure 1)

• tv.

V

/lA

o
100

ns
ns

125

ioa
o
o

o
-55

Operating free-air temperature, T A

5.25
-200

8
5

IVV

Serial input hold time, th (see Figure 1)

MAX

5

8

mA

5

MHz

ns

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High·level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

SN54L96
MIN

TYP:j:

SN74L96
MAX

2

Vee = MIN,

VOL
II

Input current at maximum input voltage

VIH = 2 V,

VIL = 0.8 V,

10H = -200 IJ.A

Vce= MIN,

VIH=2V,

VIL = 0.8 V,

10L = 8 mA

Vce = MAX,

VI = 5.5 V

2.4

3.2

preset enable

VCC= MAX,

0.2

VI = 2.4 V

any input except
Low-level input current

V

preset enable

Vec = MAX,

VI = 0.4 V

preset enable
lOS

Short-circuit output current§

Vee= MAX

lee

Supply current

Vce= MAX,

-10
See Note 3

0.4

1

1

20

20

100

100

-0.8

-0.8

-4

-4

-29

V
V
mA
IJ.A

-9

34

24

V
I

3.2
0.2

0.4

preset enable

IlL

UNIT

MAX
0.8

2.4

any input except
High-level input current

TYP:j:

2
0.8

Low-level output voltage

IIH

MIN

24

mA

-29

mA

40

mA

I

•

{For co~ditions shown at M IN or MAX, use t~e appropriate value specified under recommended operating conditions.
All typical values are at V CC = 5 V, T A = 25 C.
§Not more than one output should be shorted at a time.
NOTE 3: ICC is measured with the clear input grounded and all other inputs and outputs open.

switching characteristics, Vee = 5 V, TA

= 25°e

PARAMETER
tpLH

TEST CONDITIONS

Propagation delay time, low-to-high-Ievel output from clock

tpHL Propagation delay time, high-to-Iow-Ievel output from clock
tPLH Propagation delay time, low-to-high-Ievel output from preset or preset enable
tpHL Propagation delay time, high-to-Iow-Ievel output from clear

CL = 15pF,
RL = 800

n,

See Figure 1

MIN

TYP

MAX UNIT

50

80

ns

50

80

ns

56

70

ns

110

ns

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-99

TYPES SN54LS96. SN74LS96
5-81T SHIFT REGISTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Operating free-air temperature range: SN54LS96.
SN74LS96.
Storage temperature range

7V
7V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS96
MIN
Supply voltage. VCC

NOM

4.5

MIN

NOM

5.5

4.75

5

5

High·level output current, 10H

SN74LS96

MAX
-400

Low·level output current, 10L

MAX
5.25

V

-400

IJA

4

Clock frequency, fclock

0

25

UNIT

0

C

rnA

25

MHz

Width of clock input pulse, tw(clock)

35

35

ns

Width of preset and clear input pulse, tw

30

30

ns

Serial input setup time, tsetup (see Figure 1)

30

30

ns

0

0

Serial input hold time, thold (see Figure 1)
Operating free-air temperature, T A

-55

125

ns

0

°c

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS96

TEST CONDITIONSt

PARAMETER

MIN

VIK I nput clamp voltage
VOH High-level output voltage

Vee: MIN,

11:-18mA

Vee: MIN,

VIH: 2V,

2.5

VIL: VIL max, 10H: -400 IJA
Vee: MIN,

VOL Low-level output voltage

VIH:2V,

VIL: VIL max

at maximum
input voltage

Preset enable

I

Vee: MAX,

Preset enable

Low-level
IlL input cu rrent

Preset enable

Vee: MAX,

V

-1.5

-1.5

V

2.7
0.4

Vee

= MAX,

lOS

Short-circuit output current§

Vee: MAX

lee

Supply current

Vee: MAX,

0.25

0.4

0.35

0.5
0.5

0.1

0.1 :

I

rnA

100

100

20

20

VI =2.7 V

VI

V

0.5

All others

All others

V

3.5

VI :7V

All others

High-level
IIH input current

V
0.8

IIOL :8mA

I nput current
il

UNIT

TYP:!: MAX

0.7

3.5
0.25

IIOL :4mA

MIN
2

2

VIH High.level input voltage
VIL Low-level input voltage

•

SN74LS96

TYP:!: MAX

-2

= 0.4 V

-2.

-100 -20

-20
12

IJA

rnA

-0.4

-0.4

See Note 3

,

12

20

-100

mA

20

mA

IFor conditions shown at MIN or MAX. use t~e appropriate value specified under recommended operating conditions.
All typical values are at V CC : 5 V, T A: 25 C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 3: ICC is measured with the clear input grounded and all other inputs and outputs open.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

tpLH

Propagation delay time, low-to-high-Ievel output from clock

tpHL

Propagation delay time, high-to-Iow-Ievel output from clock

tPLH

Propagation delay time, low-to-high-Ievel output from preset or preset enable

tPHL

Propagation delay time, high·to-Iow-Ievel output from clear

eL: 15 pF,
i'lL

= 2 kn,

See Figure 1

MIN

TYP

MAX UNIT
ns

25

40

25

40

ns

28

35

ns

55

ns

1076

7-100

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN5496, SN54L96, SN54LS96,
SN7496, SN74L96, SN74LS96
5-81T SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
Vee

OUTPUT

(See Note

FROM OUTPUT
UNDER TEST

T

e)

eL~15PF

':'

(See Note B)

LOAD CIRCU!T

,I

f-- tw(dear) ---t
CLEARINPU~ V
r---------~S ~S-----------------------3V

1\

PRR';;; 1 MHz

ref

Vref

--------------------------OV

I

I

iI

I

I
I
---+I-----------------'i5

PRESET INPUT
PRR';;; 1 MHz
(See Note D)

!

\V10 ns

I

OUTPUT Y

\"'.- - - - - VOL

~ ....

"'wlcloCkr-l---tq>~
I
I

RATE INPUT

I

I

I---t-'PHL

I

I

I

I

~

I
OUTPUT Z

I~'h
t-- I

I

~N~~~L~~~

VOH

~3V

I

I

L

~~~~

PROPAGATION DELAY TIMES, CLOCK TO Z AND Y,
AND STROBE INPUT TO Z AND Y

I

',u ---..4

VOL

,.......-..rtPLH

Unity/cascade and rate inputs are high, other inputs are low,
and flip-flops are at any count other than maximum.

-DISABLED, ;--ENABLED~r--DISABLED-­

CLOCK

i

----VOL

VOH

ENABLING FROM POSITIVE-GOING
TRANSITION OF CLOCK PULSE

•

~'SV

~tPHL

1\---------

_ _ _ _ _ _ _ _---J.

I.....-tpHL

VOH

OUTPUT Z

1.SV

OUTPUT Y

3V

1.5 V

__ .

I

OV

~tPLH

r

VOH

~~.~~
---VOL

Flip-flops are at a count so that all other inputs to the gate
under test are high and all other inputs. including other rate
inputs, are low.

3V

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV

PROPAGATION DELAY TiMES,
RATE INPUT TO Z
OUTPUT Y

UNITY/CASCA::-\',5V

ENABLING FROM NEGATIVE-GOING
TRANSITION OF PREVIOUS CLOCK PULSE

INPUT

to--.,-

1. Unity/Cascade and pin 2 (rate input) are high, other inputs
are low. Clear the counter and apply clock and enable
pulse as illustrated.

OUTPUTY

2. Setup and hold times are illustrated for enabling a single
clock pulse (count). Continued application of the enable
function will enable subsequent clock pulse (counts) until
disabling occurs (enable goes high). The total number of
counts will be determined by the total number of
positive-going clock transition enabled.
NOTES:

';:::-3 V

~~'~~---OV

h

'PHL

-I---VO'"

~
'5V

'5V

VOL

Output Z is high.

PROPAGATION DELAY TIMES,
UNITY/CASCADE INPUT TO Y

A. The input pulse generator has the following characteristics: tw(clock)

=

20 ns, tTLH .;;; 10 ns. tTHL .;;; 10 ns. PRR

=1

MHz,

Zout '" 50 n.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064.

FIGURE 1-SWITCHING TIMES
1076

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TTL
MSI

TYPES SN54L98, SN14L98
4-81T DATA SELECTORS/STORAGE REGISTERS
BULLETIN NO. DL-S 72111322, DECEMBER 1972

SN54L98 ••• J PACKAGE
SN74L98 ••• J OR N PACKAGE
(TOP VIEW)

description
These monolithic data selectors/storage registers are
composed of four S-R master-slave flip-flops, four
AND-OR-!NVERT gates, one buffer, and six
inverter/drivers.

CLOCK

WORD
SELECT

When the word select input is low, word 1 (A 1 , 81,
C1, 01) is applied to the flip-flops. A high input to
word select will cause the selection of word 2
(A2, 82, C2, D2). The selected word is shifted to the
QutPl)t terminals on the negative-going edge of the
clock pulse.

, A2

Typical power dissipation is 25 mW. The SN54L98 is
characterized for operation over the full military
temperature range of -55°C to 125°C; the SN74L98
is characterized for operation from O°C to 70°C.

Ai

61

82

Ci

C2

02 I

GNIJ

positive logic: word select low for word 1,
word select high for word 2,
see descri ption

functional block diagram and schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

V C C - - -.....- - CK

I
INPUT
(14)

OB

OB

Dc

(131 Dc

CK

TYPICAL OF ALL OUTPUTS

CK

00

(111

00

CK

CLOCK~(~10~1------------------~C>~----------~

-- ... dynamic input activated by transition from a high level to a low level.
I

I

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TYPES SN54L98. SN74L98
4-81T DATA SELECTORS/STORAGE REGISTERS
absolute maximu m ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
.....
Input voltage (see Note 2)
. . . . .
Operating free-air temperature range: SN54L98
SN74L98
Storage temperature range
NOTES:

8V

5.5 V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

1. Voltage values are with respect to network ground terminal.
2_ Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN54L98
MIN
Supply voltage, Vee

4.5

NOM

SN74L98
MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM
5

-100

Low-level output current, 10L

MAX
5.25

V

-200

/l-A

3.6

mA

2
200

200

at A, B, e, or 0

100

100

at word select

150

150

at A, B, e, or 0

120

120

at word select

100

100

Width of clock pulse, tw(clock)
Setup time for high-level data, tsu(H)
Setup time for low-level data, tsu(L)
Operating free-air temperature, T A

-55

125

UNIT

ns
ns
ns
70

0

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

I

SN54L98

TEST eONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH
ilL

MIN

SN74L98

TVP+ MAX

2

MIN

TVP+ MAX

2

V

0.7
Vee
VIL
Vee
VIL

= MIN,
= 0.7 V,

VIH
10H

= 2V,
= MAX

= MIN,
= 0.7 V,

VIH

= 2V

2.4

3.3
0.3

0.15

10L = MAX

0.7
2.4

UNIT

3.2
0.2

100

V
V

0.4

V

100

/l-A

Vee - MAX,

VI- 5.5 V

High-level input current

Vee - MAX,

VI = 2.4 V

10

10

/l-A

Low-ievei input current

Vee -

~1AX,

Vi - 0.3 V

-0.18

-0.18

mA

lOS

Short-circuit output current§

Vee - MAX

-15

mA

lee

Supply current

Vee - MAX,

9

mA

-3
See Note 3

-15
5

-3

9

5

I

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, TA = 25°e.
§ Not more than one output should be shorted at a time.
NOTE 3: I ee is measured with all inputs grounded and all outputs open.

switching characteristics, Vee

=

5 V, T A = 25° C
TEST eONDITIONS

PARAMETER
f max

Maximum clock frequency

3

Propagation delay time, low-totPLH

CL=50pF,

high-level output from clock input
low-level output from clock input

NOTE 4:

RL = 4 k.l1.,

TVP

MAX UNIT
MHz

5
115

200

ns

125

200

ns

See Note 4

Propagation delay time, high-totpHL

MIN

Load circuit and voltage waveforms are shown on page 3-11.

PRINTED IN USA

1-108

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TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

TYPES SN54L99, SN74L99
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS

TTL
MSI

BULLETIN NO. DL-S 7211871. DECEMBER 1972

•

N-Bit Serial-to-Parallel Converter

•

N-Bit Parallel-to-Serial Converter

•

N-Bit Storage Register

•

J-K Serial Input

SN54L99 ••. J PACKAGE
SN74L99 ••• J OR N PACKAGE
(TOP VIEW)

description
These 4-bit registers feature parallel inputs, parallel
outputs, J-K serial inputs, mode control, and two
clock inputs. The registers have three modes of
operation:
Parallel (Broadside) load
Shift right (the direction GA toward GO)
Shift left (the direction GO toward GAl
Parallel loading is accomplished by applying the four
bits of data and taking the mode control input high.
The data is loaded into the associated flip-flop and
appears at the outputs after the high-to-Iow transition
of the clock-2 input. During loading, the entry of
serial data is inhibited.

e

vee

D

positive logic: see function table

Shift right is accomplished on a high-to-Iow transition of clock 1 when the mode control is low. Serial data for the
right-shift mode is entered at the J-R inputs. These inputs permit the first stage to perform as a J-R, a Ootype, or T -type
flip-flop as shown in the function table. Shift left is accomplished on the high-to-Iow transition of clock 2 when the
mode control is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop (GO to
input C, etc.). Serial data for this mode is entered at the 0 input. The clock input may be applied commonly to clock 1
and clock 2 if both modes can be clocked from the same source. Changes at the mode control input should normally be
made while both clock inputs are low; however, conditions described in the last three lines of the function table will
also ensure that register contents are protected.
FUNCTION TABLE
INPUTS
MODE

CLOCKS

OUTPUTS

SERIAL

PARALLEL
Oc

OD

OD

J

K

A

B

C

D

°A

°B

X

X

X

X

X

X

X

X

a

b

c

d

QSO
b

QCO QDO QDO

X

QAO
a

c

d

X

X

X

Qst

d

QS n

QCn

QDn

d

L

H

X

X

X

X

QAO

QSO

QCO QDO GOO

L

X

j,

L

H

L

X

j,

L

L

QS n
QS n

L

X

j,

H

H

X

X

X

X

QAO QAO
L
QAn
H
QAn

L

X

j,

H

L

X

X

X

X

t

L

L

X

X

X

X

X

X

j,

L

L

X

X

X

X

X

X

QS n QCn °Cn
°An QAn QS n QCn OCn
QAO QSO QCO QDO °DO
OAO QSO QCO QDO 000

j,

L

H

X

X

X

X

X

X

QAO

QSO

QCO QDO 000

t

H

L

X

X

X

X

X

X

QAO

QSO QCO QDO 000

t

H

H

X

X

X

X

X

X

QAO

QSO

CONTROL 2 (L) 1 (R)
H

H

X

H

j,

H

j,

L

Qct QDt
X

X

X

X

X

X

X

X

X

X

d
d

QCn

OCn

QCn

OCn

•

QCO QDO 000

tShifting left requires external connection of QB to A, QC to B, and QD to C. Serial data is
entered at input D.
H

= high

level (steady statel, L = low level (steady state)
X = irrelevant (any input, including transitions)
J, = transition from high to low level, t = transition from low to high level.
a. b. c. d = the level of steady·state input at inputs A. B. C. or D. respectively.
QAO. QBO. QCO. QDO = the level of QA' QB. QC. or QD. respectively. before the indicated steady-state input conditions were established.
QAn' QBn. QCn. QDn = the level of QA' QB. QC. or QD. respectively. before the most-recent .[ transition of the clock.

1076

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TYPES SN54L99, SN74L99
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS
functional block diagram
J 12)

SERIAL
INPUTS

{

CK

K 116)

114)

OB

B 13)
M
PARAllEL
INPUTS
112)

Oc

C (4)

o

M~OE

16)

(11) aD

17)

CONTROL

RI~~~S~:FT·...!(8"')_+""""F----\'

II

I

-<4>.

dynamic input activated by transition from a high level to a low level.

I

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

----+------v CC

vcc--------~--------

INPUT

OUTPUT

Input A and M· Req
All other:

Req

= 20

kn NOM

= 40 kn

NOM

i272

7-11.0

TEXAS INSTRUMENTS
INCORPORATED

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TYPES SN54L99. SN74L99
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
........ .
Input voltage (see Note 2)
. . . . . . . . .
Operating free-air temperature range: SN54L99 Circuits
SN74L99 Circuits
Storage temperature range
NOTES:

8V

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
2. Input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN54L99
MIN
Supply voltage, Vee

4.5

SN74L99

NOM

MAX

MIN

5.5

4.75

5

High-level output current, 10H

UNIT

5.25

V

-200

p.A

3.6

rnA

5

-100

Low-level output current, IOL

MAX

NOM

2

Width of clock pulse, tw(clock)

200

200

ns

Setup time for high-level data at J, K, A, 8, C, or D inputs, tsu(H)

100

100

ns

i20

-i20

ns

0

0

ns
ns

Seiup tirnt:: for

iuw~ievei

data at J, K, A, 8, C, or D inputs, tsu\Lj

Hold time at J, K, A, 8, C, or D inputs, th
Time to enable clock 1, tenable 1 (see Figure 1)

225

225

Time to enable clock 2, tenable 2 (see Figure 1)

200

200

ns

Time to inhibit clock 1, tinhibit 1 (see Figure 1)

100

100

I1S

Time to inhibit clock 2, tinhibit 2 (see Figure 1)

0

Operating free-air temperature, T A

0

-55

125

ns
70

0

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II
IIH
IlL

SN54L99
MIN

TYP:j:

SN74L99
MAX

2

MIN

TYP:j:

2

Input current at

J, K, 8, e, or D

maximum input voltage

MorA

High-level

J, K, 8, C, or D

input current

MorA

Low-level

J, K, B, e, or D

input current

MorA

VIH =2V,

VIL = 0.7 V,

10H = MAX

Vee= MIN,

VIH = 2V

VIL = 0.7 V,

10L =MAX

Vee = MAX,

VI = 5.5V

Vee = MAX,

VI = 2.4 V

Vee = MAX,

lOS

Short-circuit output current§

Vee = MAX

lee

Supply current

Vee = MAX,

2.4

3.3
0.15

VI = 0.3 V

0.3

0.2

0.4

100

100

200

200

10

10
20

-0.18

-0.18

-0.36

-0.36

-15
3.8

-3

9

3.8

•

V
V

3.2

20

-3
See Note 3

0.7
2.4

UNIT
V

0.7
Vce = MIN,

MAX

V
p.A
p.A
rnA

-15

rnA

9

rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be ~orted at a time_
NOTE 3: With all outputs and J and K inputs open, mode control at 4_5 V, inputs A through D grounded, ICC is measured after a momentary
3 V, then ground, is applied to both clock inputs_

switching characteristics, Vee

= 5 V, TA = 25° e

PARAMETER

TEST CONDITIONS

f max

Maximum clock frequency

tPLH

Propagation delay time, low-to-high-Ievel output from either clock

tpHL Propagation delay time, high-to-Iow-Ievel output from either clock

eL = 50 pF,
See Figure 2

RL =4 kn,

MIN
3

TYP

MAX

UNIT
MHz

5
115

200

ns

125

200

ns

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7-111

TYPES SN54L99, SN74L99
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
OUTPUT

VCC

FROM OUTPUT
UNDER TEST
CL

= 50 pF

(See Note B)

J

LOAD CIRCUIT

\-----

Jand K
INPUTS

----VIH

\ " . . - - - - - - - - V IL

MINPUT

~

fI

\,.3V

teMilie 1

I _______

1\

1.3V

.

I'--"""!""---i-----I
r-------I
j.

.

IH
VV

------

IL

-

CLOCK 1
INPUT

- -

-

n .-_-_-_- _

V

IH

- - - - - - - - - - V IL

tinhibit 2

CLOCK 2
INPUT

-+------

'---------'.

QA OUTPUT
_ _ _ _ _ _ _ _J

-

;'-------"\"--------11
---

\ -'----

V

IH

V IL
OH
V
VOL

NOTE: A input is at the low level.

VOLTAGE WAVEFORMS
FIGURE 1-CLOCK ENABLE/INHIBIT TIMES

•

';15 ns--+\
DATA
INPUT

I+-

~~
10%

:!l I- ~15 ns

00%\

1.3 V

\:V------

3V

I

~

f,1.3V
10%

~ Isu(L)

-t

I
-t
I

th

I
I.- Isu(H) ..I
I
...-t th
I

l-

OV

I
I

~

CLOCK
INPUT
~15

ns

I

t.-~15 ns

OUTPUT
(See Note 0)

I

I
I

/

I

I
I

--I

OV

~tW(clOCkl

I
I

t~'_n

I
\13V

j
tPHLI-

1

I
I
-I

tpLH

I-

__-

V OH

VOL

VOLTAGE WAVEFORMS
FIGURE 2-SWITCHING TIMES
NOTES:

n.

A. The input waveforms are supplied by pulse generators having the following characteristics: Zout '" 50
For data pulse
generator: tw ~ 150 ns, PRR';;; 500 kHz, lsetup(L) = 120 ns, and lsetup(H) = 100 ns. For clock pulse generator: tw ~ 200 ns and
PRR';;; 1 MHz. When testing f max ' vary PRR.
B. CL includes probe and jig capacitance.
C. All diodes are 1N916.
D. When data input is applied to J and K inputs, the output waveform applies only to output QA'

1076

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TYPES SN54100, SN74100
8-BIT BISTABLE LATCHES
BULLETIN NO. DL-S 7211830, DECEMBER 1972

SN54100 ••• J OR W PACKAGE
SN54100 ••• J OR N PACKAGE
(TOP VIEW)

logic
FUNCTION TABLE

ENABLE

Vee

(Each Latch)
INPUTS

lG

OUTPUTS

0

G

a

a

L

H

L

H

H

H

H

L

X

L

00

00

H = high level, X = irrelevant
level of Q before the
high-to-Iow transition of G

00 = the

description
These latches are ideally suited for use as temporary
storage for binary information between processing
units and input/output or indicator units. Information present at a data (D) input is transferred to the Q
output 'vvhen the enable (G) is high and the a"Output
will follow the data input as long as the enable
remains high. When the enable goes low, the information (that was setup at the data input at the time
the transition occurred) is retained at the Q output
until the enable is permitted to go high.
These circuits are completely compatible with all
popular TTL or DTL families. All inputs are diodeclamped to minimize transmission-line effects and
simplify system design. Typical power dissipation is
40 milliwatts per latch. The SN541 00 is characterized
for operation over the full military temperature range
0
0
of _55 to 125 e; the SN7 4100 is characterized for
0
operation from 0 e to 70° e.

positive logic: see function table
NC-No internal connection

functional block diagram (each latch)

ENABLE

DATA

schematic (each latch)

•
Resistor values shown are nominal and in ohms.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Intermitter voltage (see Note 2)
Operating free-air temperature range: SN54100
SN74100
Storage temperature range
NOTES:

7V
5.5 V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

1. Voltage values, except interemitter voltage. are with respect to network ground terminal.

2. This is the voltage between two emitters of a multiple-emitter input transistor. For this circuit, this rating applies between the
enable and D inputs of any latch.

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TYPES SN54100, SN74100
8-BIT BISTABLE LATCHES
REVISED OCTOBER 1976

recommended operating conditions
SN54100
MIN
Supply voltage, Vee

NOM

4.5

SN74100
MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM
5

-400

Low-level output current, 10L

16

MAX

UNIT

5.25

V

-400

/J A
rnA

16

Width of enabling pulse, tw

20

20

ns

Setup time, tsu

20

20

ns

5

5

Hold time, th

-55

Operating free-air temperature, T A

125

ns
70

0

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

•

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

TEST CONDITIONSt

TYP+

MAX UNIT
V

2

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH

High-level input current

Vee= MIN,

11=-12mA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10H = -400/JA

Vee= MIN,

VIH = 2 V,

VIL
D input
G input
D input

IlL

Low-level input current

lOS

Short-circuit output current§

ICC

MIN

G input

= 0.8 V,

VI = 5.5 V

Vee = MAX,

VI = 2.4 V

Vee= MAX,

V

-1.5

V

3.4
0.2

10L = 16mA

Vee = MAX,

V
0.4
1

80
320
-3.2

VI=O.4V

Vee = MAX

Supply current

2.4

0.8

-12.8

SN54100

-20

SN74100

-18

-57
-57

Vee = MAX,

SN541 00

64

92

See Note 3

SN74100

64

106

V
rnA
/J A
rnA
rnA
rnA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC

=5

V, T A

= 25

0

C.

§ Not more than one output should be shorted at a time.
NOTE 3: ICC is tested with all inputs grounded and all outputs open.

switching characteristics, Vee
PARAMETER~

tPLH
tpHL
tpLH
tpHL

= 5 V, TA = 25°e

FROM

TO

(INPUT)

(OUTPUT)

D

Q

TEST CONDITIONS

MIN

eL = 15 pF,
RL=400n,

G

Q

See Note 4

TYP
16

MAX UNIT
30

14

25

16

30

7

15

ns
ns

'\I tp LH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
NOTE 4: Test circuit and voltage waveforms are the same as those shown for the '75, '77, 'L 75, and' L 77 on page 7-40.

1076

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TYPES SN54116, SN74116
DUAL 4-81T LATCHES WITH CLEAR
BULLETIN NO. DL·S 7211849, DECEMBER 1972

•

Two Independent 4-Bit Latches in a
Single Package

SN54116 ••• J OR W PACKAGE
SN74116 ••• J OR N PACKAGE
(TOP VIEW)

•

Separate Clear Inputs Provide One-Step
Clearing Operation

•

Dual Gated Enable Inputs Simplify
Cascading and Register Implementations

•

Compatible for Use with TTL and DTL
Circuits

•

Input Clamping Diodes Simplify
System Design

description
These monolithic TTL circuits utilize O·type bistables
to implement two independent four·bit latches in a
singie package. Each four·bit iatch has an indepen·
dent asynchronous clear input and a gated two· input
enable circuit. When both enable inputs are low, the
output levels will follow the data input levels. When
either or both of the enable inputs are taken high, the
outputs remain at the last levels setup at the inputs
prior to the low·to-high-Ievel transition at the enable
input(s). After this, the data inputs are locked out.

positive logic: see function table

functional block diagram (each 4-bit latch)

The clear input is overriding and when taken low will
reset all four outputs low regardless of the levels of
the enable inputs.

•

The SN54116 is characterized for operation over the
full military temperature range of -55°C to 125°C;
the SN74116 is characterized for operation from O°C
to 70°C.
FUNCTION TABLE
(EACH LATCH)
INPUTS
CLEAR

ENABLE

OUTPUT
DATA

a

G1

G2

H

L

L

L

L

H

L

L

H

H

H

X

H

X

H

H

X

X

00
00

L

X

X

X

L

H = high level, L = low level, X = irrelevant

00 = the level of

°

before these input conditions were established.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Supply voltage, VCC (see Note 1)
....... .
I nput voltage "
. . . .,
....... .
Operating free-air temperature range: SN54116 Circuits
SN74116 Circuits
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.

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7-115

TYPES SN54116, SN74116
DUAL 4-BIT LATCHES WITH CLEAR
recommended operating conditions
SN54116
MIN
Supply voltage, Vee

4.5

NOM

SN74116
MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM
5

-800

Low-level output current, 10L

16

Input pulse width, tw
Data setup time, tSIJ

Enable

18

18

Clear

18

18

High logic level

8

8

Low logic level

14

14

8

8

Clear inactive-state setup time, tsu
Data hold time, low-level data, th

8

Operating free-air temperature, T A

V

-800

p.A

16

rnA

ns
ns
2

8

-55

125

UNIT

5.25

ns

2

Data release time, high-level data, trelease

MAX

70

0

ns

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

•

VIH

High-level input voltage

VIL
VIK

Low-level input voltage
Input clamp voltage

VOH

High-level output voltage

TEST CONDITIONSt

MIN

TYpt

VOL

Low-level output voltage

'I

Input current at maximum input voltage

IIH

High-level input current

IlL

Low-level input current

V

Gl, G2, or clear
Any D
Gl, G2, or clear
Any D, initial peak

Vee= MIN,

11=-12mA

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

10H = -SOOJJ.A

Vce= MIN,

VIH = 2V,

VIL = 0.8 V,

10L = 16mA

Vee = MAX,

VI = 5.5V

Vee = MAX,

VI=2.4V

Vee = MAX,

VI = 0.4 V

2.4

ICC

Short-circuit output current§

V

-1.5

V

0.2

V
0.4
1
40
60

V
rnA
JJ.A

-1.6
--2.4

rnA

-1.6
Vee= MAX
Vee

Supply current

0.8

3.4

Any D, steady-state
lOS

MAX UNIT

2

= MAX,

See Note 2

SN54116

-20

SN74116

-18

-57
-57

Condition A

60

100

Condition B

40

70

rnA
rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: With outputs open, ICC is measured for the following conditions:
A. All inputs grounded.
B. All 13 inputs are grounded and all other inputs are at 4.5 V.

switching characteristics, Vee =5 V, TA = 25°e
PARAMETER~

FROM

TO

(INPUT)

(OUTPUT)

Enable

AnyQ

TEST CONDITIONS

MIN

TYP

MAX UNIT

19

30

tpHL

eL = 15pF,

15

22

tpLH

RL=400n,

10

15

See Figure 1

12

18

15

22

tPLH

Data

Q

Clear

AnyQ

tpHL
tpHL

ns
ns
ns

~tpLH '" propagation delay time, low-to-high-Ievel output
tpHL'" propagation delay time, high-to-Iow-Ievel output

1076

7-116

TEXAS INSTRUMENTS
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TYPES SN54116, SN74116
4-811 LATCHES WITH CLEAR
schematics of inputs and outputs
TYPICAL OF
ALL OUTPUTS

EQUIVALENT OF
DATA INPUTS

EQUIVALENT OF CLEAR,
G1, AND G2 INPUTS

VCC
VCC1
4 3
kn NOM
INPUT

V C CReq
3--

--

'N'UT

.-OUTPUT

Initial Req = 3
Steady-state Req = 6

kn
kn

NOM
NOM

PARAMETER MEASUREMENT INFORMATION
FROM OUTPUT
UNOER TEST

LOAD CIRCUIT

CLEAR
INPUT

~
3V
15v
1.5 V
I'
.!.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

r--

ov
\L-__---Jlr---_-_-_-::

tw_

~tsu

I
OATA
INPUT

,..-_ _ _ 14--

,seeE~:.:~~ _ _...;...._ _ _ _. J11.5V

14-

l.-'PHL'"

_ _ _ _'""\ I

\1.5 V I

OUTPUT

~

-----t

tw

~1.5V

IPHL _

Iw

-!

3V

P}.1.._5_V__..JEov
\1.S V
F

•

14-- IPLH-+I

_----_ I

I

V

OH

.

VOL

SWITCHING TIMES FROM CLEAR AND ENABLE INPUTS
3V

OATA
INPUT

loS V

(See Note E)

I

ENABLE

I
I

I

I

~ ..... Ih

-.I!4-lrelease:
Isu ..... _ - - _

,see~~:.u~__...;!-----I=--------.J11.5V
IPLH ~

14-

Isu

~

3V

~ OV

I4-IPHL--l

1";-·S-V---\. .1_.S_V___

/

OUTPUT _ _ _--J

J

SWITCHING TIMES FROM DATA INPUTS

NOTES: A. Input pulses are supplied by generators having the following characteristics: tr';; 10 ns, tf';; 10 ns, PR R
B.
C.
D.
E.

=1

MHz, duty cycle';; 50%,

Zout "" 50 n.
CL includes probe and jig capacitance.
All diodes are 1 N3064.
The other enable input is low.
Clear input is high.

FIGURE 1

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7-117

TTL
MSI

TYPES SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
BULLETIN NO. DL-S 7211537, SEPTEMBER 1971-REVISED DECEMBER 1972

•

Generates Either a Single Pulse or Train of Pulses
Synchronized with Control Functions

•

Ideal for Implementing Sync-Control Circuits
Similar to those Used in Oscilloscopes

•

Latched Operation Ensures that Output Pulses
Are Not Clipped

•

High-Fan-Out Complementary Outputs Drive
System Clock Lines Directly

•

Internal Input Pull-Up Resistors Eliminate
Need for External Components

•

Diode-Clamped Inputs Simplify System Design

•

Typical Propagation Delays:

SN54120 ..• J OR W PACKAGE
SN74120 •.• J OR N PACKAGE
(TOP VIEW)
~

____

INPUTS
~A~

______

~

~----~v~----~
INPUTS

9 Nanoseconds through One Level
16 Nanoseconds through Two Levels

logic: see description and function table

description
These monolithic pulse synchronizers are designed to synchronize an asynchronous or manual signal with a system
clock. Reliable response is ensured as the input signals are latched up; therefore duration of logic input is not critical
and the adverse effects of contact-bounce of a manual input are eliminated. The ability to pass output pulses is started
and stopped by the levels or pulses applied to the latch inputs S1, S2, or R in accordance with the function table.
High-speed circuitry is utilized throughout the clock paths to minimize skew with respect to the system dock.

•

After initiation, the mode control (M) input determines whether a series of pulses or only one pulse is
passed. In the absence of a stop command, the clock
driver will continue to pass clock pulses as long as the
mode control input is low (see Figures 2 through 4).
If the mode control input is high only a single clock
pulse will be passed (see Figure 5).
When the mode control is set to pass a series of
pulses, the last pulse out is determined by two general
rules:
a. When pulses are terminated by the S or R
inputs, conditions meeting the setup times
(specified under recommended operating
conditions) will dominate.

FUNCTION TABLE

R
X

INPUTS
S1
S2
L

X

FUNCTION
Pass Output Pulses
Pass Output Pulses

X

X

L

L

H

H

Inhibit Output Pulses

H

~

H

Start Output Pulses

H

H

~

Start Output Pulses

I~

H

H

Stop Output Pulses

H

H

Continue t

H = high level (steady state)

= low level (steady state)
= transition from H to L
x = jrTe~evant
L

~

t Operation initiated by last ~ transition,continues.

b. Low-to-high-Ievel transitions at the mode control input should be avoided during the 20-nanosecond period
immediately following the negative transition of the input clock pulse as transitions during this time period
mayor may not allow the next pulse to pass (see Figures 4 and 5). When pulses are terminated by th~ mode
control input, a positive transition at the mode control input meeting the high·level setup time, tsu (H),
(specified under recommended operating conditions) will pass that positive clock pulse then inhibit remaining
clock pulses. The clock input (e) is latch-controlled ensuring that once initiated the output pulse will not be
terminated until the full pulse has been passed.

1076

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TYPES SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
desCription (continued)
This clock driver circuit is entirely compatible for use with either digital logic circuits or mechanical switches for input
controls since all inputs, except the clock, have internal pull-up resistors. This eliminates the requirement to supply an
external resistor to prevent the input from floating when the control switch is open. The internal resistor also means
that these inputs may be left disconnected if unused.
Typical propagation delay time is 9 nanoseconds to the Y output and 16 nanoseconds to the Y output from the clock
input. The outputs will drive 60 Series 54/74 loads at a high logic level and 30 loads at a low logic level. Typical power
dissipation is 127 milliwatts per driver. The SN54120 is characterized for operation from -55°C to 125°C; the
SN74120 is characterized for operation from O°C to 70°C.

functional block diagram (each driver)

INPUTS

l
:

0 - -....- - - - -......- - -

-~---Ir-I--:~J

-t_-_-_-_

_ _ _ _ _ _ _L_

JOU~~UTS

....

•

schematics of inputs and outputs
EQUIVALENT OF
EACH C INPUT

Vee

---+----

EQUIVALENT OF EACH
M. R. OR S INPUT
VeG~._-.....- -

TYPICAL OF
ALL OUTPUTS

- - - - - - - - Vee

NOM

INPUT

INPUT
I...--~-- OUTPUT

1272

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INSTRUMENTS

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•

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7·119

TYPES SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage . . . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54120 Circuits
SN74120 Circuits
Storage temperature range . . . .

7V
5.5 V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the S1 and S2
inputs.

recommended operating conditions
SN54120
MIN
4.5

Supply voltage, Vee

SN74120

NOM

MAX

MIN

NOM

5.5

4.75

5

5

High-level output current, 10H

tsu(H or

Setup time (see Figures 2 thru 5)

Mode control

II tsu(H)
tsu(Ll

mA

48

48

mA

0

12

12

3

3

20

20

th(H or Ll
Mode control, th(H or

Ll

12

0

Any input except mode control,
Hold time (see Figures 3 and 5)

-55

Operating free-air temperature, T A

V

-2.4

12

Ll

5.25

UNIT

-2.4

Low-level output current, 10L
Any input except mode control,

MAX

125

ns

ns

0

°e

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

•

VIH

High-level input voltage

VIL

Low·level input voltage

VIK

I nput clamp voltage

VOH

TEST eONDITIONSt

MIN

TYP:j:

MAX

2

H.igh-Ievel output voltage

VOL

Low-level output voltage

II

I nput current at max imum input voltage

IIH

High-level input current

Clock input
Other inputs
elock input

Vee- MIN,

11--12mA

Vee; MIN,

VIH; 2 V,

VIL; 0.8 V,

10H; -2.4 mA

Vee; MIN,

VIH; 2 V,

VIL;0.8V,

10L; 48 mA

Vee; MAX,

VI; 5.5 V

Vee; MAX,

VI;2.4V

Vee; MAX,

VI; 0.4 V

IlL

Low-level input current

lOS

Short-circuit output current§

Vee; MAX

lee

Supply current

Vee; MAX,

Other inputs

2.4

UNIT
V

0.8

V

-1.5

V

3.4
0.2

V

0.4
1

V
mA

80, J.!A
-0.12

-0.2

-0.36
-3.2
-2.1

-35
See Note 3

mA
mA

-90

mA

51

90

mA

TYP

MAX

14

22

17

25

10

16

8

13

t For conditions shown as M!N or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee; 5 V, T A; 25°e.
§ Not more than one output should be shorted at a time.
NOTE 3: lee is measured with ground applied to all inputs except R which is at 4.5 V and all outputs open.

switching charC!cteristies, Vee
PARAMETER~

tPLH

= 5 V, T A = 25°e
FROM

TO

(INPUT)

(OUTPUT)

TEST

y

e

tpHL
tpLH

eL ; 45 pF,
RL;133.!1,

y

e

See Figure 1

tpHL
~

eONDITION~

MIN

UNIT

ns

ns

tPLH "" Propagation delay time, low-to-high-Ievel output
tpH L "" Propagation delay time, high-to-Iow-Ievel output

1076

7-120

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TYPES SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
PARAMETER MEASUREMENT INFORMATION

Vcc

!

OUTPUT

NOTES:

clock

input

pulse

in figures 2

through 5

is

supplied by a generator having the following char-

1

acteristics:

FROM OUTPUT±
..._ il
l..IIIII.--4Il_-tIlll..l
....-tIlll..l
....-IIIIII..I
• ..,
UNDER TEST
,...,.
jiI'j
jiI'j jiI'j

l'

A. The

RL '133"

tw(clock);;;' 15 ns,

PRR';; 1 MHz,

and

Zout "" 50.n.
B. CL includes probe and jig capacitance.
C. All diodes are 1 N3064.

CL =45pF

FIGURE 1-LOAD CIRCUIT FOR SWITCHING TESTS

tw(clock)

~"lL~UCTK

ri

.,'..

;:::...L

S1 or S2
INPUT

I

~

I

tw(clock)

---

I~1.5V ~
1'---./
I

-----J

.

.1

I

tsu(L)

I

I'

I

~

'---Ii
!4----M- tsu(Hl
I

3 V

'- 0 V

.

/ , . - - - - 3V

1.5 VI
II
\.._~:_ _ _~:.-_ _ _ _ _ _ _~.

1.5 V
0V

(See Note)

tPHL--!

I
, - - - - - - - - - - - - - - VOH
YOUTPUT

Y OUTPUT
' -_ _ _ _ _ _ _ _ VOL
NOTE: Mode control and R inputs are low·unused S input is high.

FIGURE 2-INITIATING AND TERMINATING PULSE TRAIN FROM S INPUTS

•

CLOCK
INPUT

i----!I tsu(L)
I

I

~
-----------------*---'1-----r
II

S1orS2
INPUT

OV

,
,

......... tn(L)

1.5V

3V

I

1.5V

I

tsu(L)
_______________________________

~

I

.J

OV
th(L)

I

3V

RINPUT

_ - - - - - - - - - VOH
YOUTPUT

NOTE: Mode control input is low and unused S input is high.

FIGURE 3-INITIATING PULSE TRAIN FROM S AND TERMINATING WITH R INPUTS
1076

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TYPES SN54120, SN74120
DUAL PULSE SYNCHRONIZERS/DRIVERS
PARAMETER MEASUREMENT INFORMATION

.1

---I

CLOCK
INPUT

tw(clock)

I. . .~---+-

1
.....~-.01- tsu(L)

OV
tsu (H)

~~~ROL .~~.5__V_____________________~~1.-5-~----_-_-_--_-_--_-_-_--_-_--_-_-_--_-_-

3V

OV
VOH

YOUTPUT

'-_..J ___________ - - - - VOL

NOTE: At least one of the S inputs is low.

FIGURE 4-INITIATING AND TERMINATING PULSE TRAIN WITH MODE CONTROL INPUT

•

CLOCK
INPUT

I
I
I

OV

\4-

tsu{H)

th(L)~

fsv!

MODE CONTROL
INPUT

3V

-------+----t-h(-H-)---~ - - - ""t' -

- - - - -- -- -

- - - - - - - - - -

-

I~ __ ~_t~~) __________________ _

~~5_V________________________________

S1 or S2

INPUT

"'----~-----------

YOUTPUT

NOTE: Input R is low and the unused S input is high.

OV
3V

OV
VOH

VOL

FIGURE 5-ENABLING SINGLE PULSE
1076

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TYPES SN54LS124, SN54S124, SN74LS124, SN74S124
DUAL VOLTAGE-CONTROLLED OSCILLATORS

TTL
MSI

BULLETIN NO. DL-S 7612025, MARCH 1974-REVISED OCTOBER 1976

SN54LS124, SN54S124 ••• J OR W PACKAGE
SN74LS124, SN74S124 .•. J OR N PACKAGE
(TOP VIEW)

•

Two Independent VCO's in a 16-Pin
Package

•

Output Frequency Set by Single External
Component:
Crystal for High-Stability Fixed-Frequency
Operation
Capacitor for Fixed- or Variable-Frequency
Operation

•

Separate Supply Voltage Pins for Isolation
of Frequency Control Inputs and Oscillators
from Output Circuitry

•

Highly Stable Operation over Specified .
Temperature and/or Supply Voltage Ranges
GUARANTEED
TYPE

FREQUENCY
SPECTRUM

'LS124 1 Hz to 20 MHz
'S124

1 Hz to 60 MHz

TYPICAL

TYP!CAL
f max

POWER
DISSIPATION

30 MHz

150mW

85 MHz

525mW

logic: While the enable input is low, the
output is enabled. While the enable
input is high, the output is high.

description
The 'LS124 and 'S124 feature two independent voltage-controlled oscillators (VCOI in a single monolithic chip. The
output frequency of each VCO is established by a single external component, either a capacitor or a crystal, in
combination with two voltage-sensitive inputs, one for frequency range and one for frequency control. These inputs
can be used to vary the output frequency as shown under typical characteristics for the 'S124. The concept also applies
for the 'LS124. These highly stable oscillators can be set to operate at any frequency typically between 0.12 Hz and
30 MHz ('LS124) or 0.12 hertz and 85 megahertz (,S124). Under the conditions used in Figure 3, the output
frequency can be approximated as follows:
4
fo = 1 X 10- for 'LS124
Cext
'

4
fo = 5.X 10- for 'S124
Cext

where: fo = output frequency in hertz
Cext

=

external capacitance in farads.

•

These devices can operate from a single 5-volt supply. However, one set of supply-voltage and ground pins (VCC and
GND) is provided for the enable, synchronization-gating, and output sections, and a separate set eVCC and8GND)
is provided for the oscillator and associated frequency-control circuits so that effective isolation can be accomplished in
the system.
The enable input of these devices starts or stops the output pulses when it is low or high, respectively. The internal
oscillator of the 'LS124 runs continuously even while the output is disabled, whereas the internal oscillator of the
'S124 is itself started and stopped by the enable input. The enable input is one standard load in each series. The enable
input and the buffered output operate at standard Schottky-clamped TTL levels.
The pulse synchronization-gating section ensures that the first output pulse is neither clipped nor extended. Duty cycle
of the square-wave output is fixed at approximately 50 percent. Simultaneous operation of both VCO's in the same
package is not recommended.
The SN54LS124 and SN54S124 are characterized for operation over the full military temperature range of _55°C to
125°C; the SN74LS124 and SN74S124 are characterized for operation from O°C to 70°C.
1076

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7-123

TYPES SN54LS124, SN54S124, SN74LS124, SN74S124
DUAL VOLTAGE-CONTROLLED OSCILLATORS
schematics of inputs and outputs
'LS124
EQUIVALENT OF EACH
ENABLE INPUT

TYPICAL OF BOTH OUTPUTS

EQUIVALENT OF EACH FREQUENCY
CONTROL OR RANGE INPUT

--------------~-----Vee

vCC------~------

__~---~-

n

NOM

R3

17 kn NOM
INPUT~~

50

Vee----------_e--

R1
I NPUT--'''''''''....----I

'----.....- - - - OUTPUT

R2

NOMINAL VALUES
R1

R2

R3

79 kn 14 kn 27 kn
85 kn 6 kn 24 kn

Frequency control
Range

'S124
EQUIVALENT OF EACH
ENABLE INPUT

EQUIVALENT OF EACH FREQUENCY
CONTROL OR RANGE INPUT

TYPICAL OF BOTH OUTPUTS
- - - - -....- - Vee

Vee--------~----

114 n NOM

Vee---------.-------INPUT

•

INPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Notes 1 and 2)
Input voltage: 'LS124 Enable input
'LS124 Frequency control or range input
'S124 . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS124, SN54S124
SN74LS124,SN74S124
Storage temperature range

. 7V
. 7V

Vee
5.5V
-55°e to 125°e
oOe to 700e
0
-65°e to 150 e

NOTES: 1. Voltage values are with respect to the appropr'ate ground terminal.
2. Throughout this data sheet, the symbol Vee is used for the voltage applied to both the Vee and8vee terminals, unless otherwise noted.

1076

7-124

TEXAS INSTRUMENTS
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TYPES SN54LS124, SN74LS124
DUAL VOLTAGE-CONTROLLED OSCILLATORS
recommended operating conditions
SN54LS124

SN74LS124

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

5

0

5

V

Supply voltage, VCC

0

Input voltage at frequency control or range input, Vl(freq) or Vl(rng)
High-level output current, 10H

-1.2

-1.2

Low-level output current, 10L

12

24

mA
mA

20

MHz

70

°c

1

Output frequency (enabled),lo

Hz

1
20

-55

Operating free-air temperature, T A

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS124
MIN TYP:j: MAX

TEST CONDITIONSt

PARAMETER
High-ievei input

2

2

voltage at enable
Low-level input
VIL
VIK

0.7

0.8

V

-1.5

-1.5

V

voltage at enable
I nput clamp voltage at enable

VOH High-level output voltage
VOL Low-level output voltage
II

SN74LS124
MIN TYp:j: MAX UNIT

I nput current

Freq control
or range

VCC= MIN,

11- -18 mA

VCC- MIN,

VIH-2V,

2.5

2.7

3.4

V

3.4

IOH = -1.2 mA
VCC = MIN,

0.25

8vcc open IOL = 12mA

0.4

IOl = 24 mA

Vil = Vilmax
VCC= MAX

0.25

0.4

0.35

0.5

VI-5V

50

250

50

250

VI= 1 V

10

50

10

50

V
p.A
I

I nput current
II

at maximum

0.1

0.1

mA

VI = 2.7 V

20

20

p.A

VI = 0.4 V

-0.4

-0.4

mA

-225

mA

50

mA

Enable

VCC= MAX,

VI =7V

Enable

VCC= MAX,

Enable

VCC = MAX,

input voltage
High-level
IIH

input current
low-level

III
lOS

input current

Short-circuit output current§
Supply current, total into

ICC

pins 15 and 16

VCC= MAX,

-225

-40

VCC= MAX
See Note 2

30

-40
30

50

•

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with the outputs disabled and open.

switching characteristics, Vee = 5 V (unless otherwise noted), RL = 667 n, e L = 45 pF, T A = 25°e
PARAMETER

TYP

TEST CONDITIONS

MIN
20

30

11

20

fo

Output frequency (capacitor controlled)-

C
= 2 pF IVl(freq) = 4 V, Vl(rng) = 1 V
ext
IVl(freq) = 1 V, VI (rng) = 5 V

fo

Output frequency (crystal controlled)

8Vcc

Output duty cycle

Cext = 8.3 pF to 500 p.F

50%

fo'" 1 Hz

30+*

Propagation delay time,
tpHl

high-to-Iow-Ievel output from enable

= 3 V, VI(freq)

= Vl(rng)

=0 V

10

20

MAX UNIT
MHz
MHz

ns

9
'The delay will typically be 30 ns plus up to one period of one cycle (i.e. 30 ns to 30 ns + 1 X 10
ns) depending upon the timing of
the enable pulse with respect to the signal generated by the internal oscillator.
fo(Hz)

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-125

TYPES SN54S124, SN14S124
DUAL VOLTAGE-CONTROLLED OSCILLATORS
recommended operating conditions
SN54S124
MIN
Supply voltage, Vee (see Note 1)

SN74S124

NOM

MAX

MIN

NOM

MAX

5

5.5

4.75

5

5.25

5

1

4.5
1

Input voltage at frequency control or range input, Vl(freq) or Vl(rng)

5

-1

High-level output current, 10H
Low-level output current, 10L

20
1

Output frequency (enabled), f 0

-55

Operating free-air temperature, T A

125

V
V

-1

rnA

20

rnA

60

MHz

70

°e

Hz

1
60

NOTE 1: Throughout this data sheet, the symbol

UNIT

0

Vee is used for the vOltage applied to both pins 15 and 16.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage at enable

VIL

Low-level input voltage at enable

VIK

Input clamp voltage at enable

TEST CONDITlONSt

MAX UNIT
V

Vee; MIN,

VIH;2V,

I SN54S'

r SN74S'

2.5

3.4

2.7

3.4

V

-1.2

V
V

VIL;0.8V,
0.5

10L; 20 rnA
or range

0.8

I VI- 5V

Vee; MAX

10

50

1

15

I VI; 1 V

V

JlA

Enable

Vee; MAX, VI; 5.5 V

IIH

High-level input current

Enable

Vee; MAX, VI;2.7V

50

JlA

IlL

Low-level input current

Enable

Vee; MAX,

-2

rnA

lOS

Short-circuit output current §

-100

rnA

II

•

II; -18mA

Vee; MIN,
Freq control

Input current at

Vee; MIN,
10H; -1 rnA

VOL Low-level output voltage
Input current

TYP:j:

2

VOH High-level output voltage

II

MIN

maximum input voltage

VI; 0.5 V

Vee; MAX

-40

Vee; MAX, See Note 2

Supply current, total into
ICC

1

Vee; MAX, TA; 125°C,

pins 15 and 16

105

I

W package

150
110

only

See Note 2

rnA

rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee; 5 V, T A = 25°C.

~Not

more than O!1e output

~hou!d be shorted at a time ,a,nd duration of the short-circuit should not exceed one second.

NOTE 2: ICC is measured with the outputs disabled and open.

switching characteristics, Vee = 5 V, RL = 280 n, eL = 15 pF, TA = 25°e
PARAMETER
fo

tPHL

TEST CONDITIONS

I VI(freq) ; 4 V, Vl(rng) ;

Output frequency

eext; 2 pF

Output duty cycle

eext - 8.3 pF to 500 JlF

Propagation delay time,

fo; 1 Hz to 20 MHz

high-to-Iow-Ievel output from enable
fo

I

1V
Vl(freq); 1 V, Vl(rng); 5 V

> 20 MHz

MIN
60
25

TYP
85
40

MAX UNIT
MHz

50%
1.4
fo(Hz)
70

s
ns

1076

7-126

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS124, SN54S124, SN74LS124, SN74S124
DUAL VOLTAGE-CONTROLLED OSCILLATORS
TYPICAL APP.LlCATION DATA
free-running oscillator
Free-running oscillators can be implemented for most systems by setting the output frequency of the veo with either a
capacitor or a crystal. If excitation is provided with a capacitor the frequency control and/or range inputs can be used
to vary the output frequency.
When the 'S124 is excited with a crystal, low-frequency response (.;;;; 1 MHz) can be improved if a relatively small
capacitor (5 to 15 pF) is paralleled with the crystal. When operated at the fundamental frequency of a crystal, the
frequency control input should be high (~ 5 V) and the range input should be low (grounded) for maximum stability
over temperature and supply voltage variations.
When the 'LS124 is excited with a crystal, a small capacitor (2 to 10 pF) should be placed in series with the crystal
and the
Vee supply should be lowered to approximately 3 V. A series-resonant, fundamental-mode crystal with
series resistance less than 200 ohms should be used. The frequency control and range inputs should be grounded. The
maximum recommended frequency for crystal-excited operation is 10 MHz.

e

phase-locked loops
A basic crystal-controlled phase-locked loop is illustrated in Figure 1. This application can be used for implementation
of:
a. A highly stable fixed-frequency clock generator.
b. A highly stable fixed- or variable-frequency synthesizer.
c. A highly efficient "slave-clock" system for synchronizing off-card, remote, or data-interfacing clock systems
N
With fixed division rates for both M and N, the output frequency (fo) will be stable at fo = M fl. Obviously, either
ivi or N, or both, couid be programmable counters in which case the output frequency (fol wiil be a variable frequency
dependent on the instantaneous value of

ij-t,.

The crystal-controlled veo can be operated up to 60 MHz with an accuracy that is dependent on the crystal. At the
higher frequencies, response of the phase comparator can become a limiting factor and one of the following approaches
may be necessary to extend the operating frequency range.

k

can be divided equally by the same constant (K) also shown in Figure 1. The constant can
a. FreqUencies{tand
be any value greater than unity (K> 1), and should be selected to yield frequency ranges that can be handled
adequately by the phase-comparator and filter. The output frequency (fo) retains the same relationship as
previously explained because now:

•

KN
N
KM fl =
fl

M

it

b. In another method, the comparison of
and ~ can be performed with either an SN54LS85/SN74LS85 or
SN54S85/SN74S85. The resultant A> B and A < B outputs from the 'LS85 or 'S85 permit the detector to be
simplified to a charge-pump circuit. See Figure 2.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-127

TYPES SN54S124, SN74S124
DUAL VOLTAGE-CONTROLLED OSCILLATORS
TYPICAL APPLICATION DATA

FIGURE 2-HIGH-FREQUENCY PHASE-LOCKED LOOP

RGURE 1-PHASE-LOCKED LOOP

TYPICAL CHARACTERISTICS ('S124 only)
BASE OUTPUT FREQUENCY

•

vs

INPUT VOLTAGE

1G
N

:r:
I

>u
c:

Ql

:::J

100M
10M

I

~
i

1M

0-

U: 100 k

~i

e

10 k

0

~

co
a:l

I

I

~
..c

1k

i

-<

TA = 25 C

iii
I

I

>u
c:

i

0-

~

u..

:::J

!

:::J

'\

~

:

10

0

!

';", I

!

e

!
!

I

'\

"C

I
I

i

Ql

.!:::!

co

i

E
(5

z

I\.

I

..=

'\ '\.

:§
I

0.1

10- 12

10- 10

1.1

Q}

::J

......

i

100

I I :

1.2

I

~

!

:::J

1

",I

......

:::J

5
I Vee'
V
Vl(freq)o= VI (rng) = 2 V
i

i

Ql

NORMALIZED OUTPUT FREQUENCY

vs

EXTERNAL CAPACITANCE

10- 8

'\

I

10-6

10- 4

10- 2
VI (freq)-Input Voltage-V

Cext-External Capacitance-F
FIGURE 3
NOTE: fo

= fn

FIGURE 4

X fo(base).

1076

7-128

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54S135, SN14S135
QUADRUPLE EXCLUSIVE-OR/NOR GATES

TTL
MSI

BULLETIN NO. DL-S 7211826, DECEMBER 1972

SN54S135 •.. J OR W PACKAGE
SN74S135 .•• J OR N PACKAGE
(TOP VIEW)

•

Fully Compatible with Most TTL and
TTL MSI Circuits

•

Fully Schottky Clamping Reduces
Delay Times ... 8 ns Typical

•

Can Operate as Exclusive-OR Gate (C Input
Low) or as Exclusive-NOR Gate (C Input High)

Vcc

4B

4A

4Y

3C,4C

11;1

1Y

1C.2C

2A

3B

3A

3Y

FUNCTION TABLE
OUTPUT

INPUTS
B

C

L

L

L

L

L

H

L

H

L

L

H

H

I~

I~

IH
H

Y

A

= high

H
L

~I

L

~

H

H

H

level, L

= low

I
I

L
H
L

L

positive logic: Y;;; {A(±)B)(BC ==

ABC + ABC +-:ABC + A8C

H

level

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

--------VCC
VCC------~------

•

2.8 k.\1 NOM

INPUT

OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54S135
SI\I74S135
Storage temperature range . . . . . . . . .

7V
5.5 V
_55°C to 125°C
. . aOe to 7aoe
-65°C to 15aoe

NOTE1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

CALLAS. TEXAS 75222

7-129

TYPES SN54S135, SN74S135
QUADRUPLE EXCLUSIVE-OR/NOR GATES
recommended operating conditions
SN54S135
MIN
Supply voltage, V CC

NOM

4.5

SN74S135

MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM
5

-1

Low-level output current, 10L

20

Operating free-air temperature, T A

-55

125

0

UNIT

MAX
5.25

V

-1

rnA

20

rnA
DC

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONSt

MIN

TYP+

MAX UNIT

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

Input current at maximum input voltage

VCC= MAX, VI = 5.5 V

IIH

High-level input current

VCC= MAX, VI=2.7V

50

/.LA

IlL

Low-level input current

VCC= MAX, VI=0.5V

-2

rnA

lOS

Short-circuit output current§

VCC= MAX

-100

rnA

ICC

Supply current

VCC= MAX, See Note 2

99

rnA

2

V
0.8

VCC= MIN,

II = -18mA

VCC = MIN,

VIH=2V,

VIL = 0.8 V,

10H = -1 rnA

VCC= MIN,

VIH=2V,

VIL = 0.8 V,

10L = 20mA

V

-1.2

I SN54S'

I SN74S'

2.5

3.4

2.7

3.4

V
V

0.5

V

1

-40
65

rnA

t For conditions shown as MI N Or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
D
+AII typical values are at Vee = 5 V, TA = 25 e.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee

•

FROM

PARAMETER.

AorB

tpHL
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL

TEST CONDITIONS

(INPUT)

tpLH
tpLH

= 5 V, TA = 25°e

i

MIN

8.5

B or A = L, C = L
B or A

A orB
AorB

~

H. C = L

!

B or A = L, C= H

CL=15pF,
RL = 280

AorB

B or A = H, C = H

C

A=B

C

TYP

n,

See Note 3

I

A*B

MAX UNIT
13

11

15

8

12

9

13.5

10

15

6.5

10

8.5

12

7

11

8

12

9.5

14.5

7.5

11.5

8

12

ns
ns
I

ns
ns
ns
ns

• tpLH =' propagation delay time, low-to-high-Ievel output
tpH L =' propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7·130

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54136, SN54LS136, SN74136, SN74LS136
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
WITH OPEN-COLLECTOR OUTPUTS

TTL
MSI

BULLETIN NO, DL-S 7611827, DECEMBER 1972-REVISED OCTOBER 1976

SN54136, SN54LS136", J OR W PACKAGE
SN74136, SN74LS136 , , ,J OR N PACKAGE
(TOP VIEW)

Vce

4B

4A

4Y

3B

3A

3Y

1A

1B

1Y

2A

2B

2Y

GND

FUNCTION TABLE
INPUTS

H

OUTPUT

A

B

L

L

L

L

H

H

H

L

H

H

H

= high

Y

L
level, L

= low

level

positive logic: Y

= A<±)B = AB + AS

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
OF '136

EQUIVALENT OF EACH INPUT
OF '136
VCC----..--

__
INPUT

~OUTeUT

•

EQUIVALENT OF EACH INPUT
OF'LS136

TYPICAL OF ALL OUTPUTS
OF'LS136

VCC
12.5 kn NOM

INPUT

~~

_ _ ~OUTeUT

-

0.
..,....

~~
~,

,,'7

l076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

OALLAS, TEXAS 75222

7-131

TYPES SN54136, SN74136
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
WITH OPEN-COLLECTOR OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Operating free-air temperature range: SN54136
SN74136
Storage temperature range

7V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74136

SN54136
MIN

NOM

4.5

Supply voltage, Vee

MAX

MIN

5.5

4.75

5

NOM
5

MAX

UNIT
V

5.25

High-level output voltage, VOH

5.5

5.5

V

Low-level output current, IOL

16

16

mA

70

e

-55

Operating free-air temperature, T A

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

•

VIH

High-level input voltage

VIL

LOW-level input voltage

VIK

Input clamp voltage

IOH

High-level output current

VOL

Low-level output voltage

II

TEST CONDITlONS·t

MIN TVP+ MAX UNIT
V

2
Vee= MIN,

II =-8mA

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

VOH = 5.5 V

Vee = MIN,

VIH = 2V,

VIL = 0.8 V,

IOL = 16 mA

Input current at maximum input voltage

Vee= MAX,

VI=5.5V

0.2

0.8

V

-1.5

V

250

j.lA

0.4
1

V
mA

IIH

High-level input current

Vee = MAX,

VI = 2.4 V

40

j.lA

IlL

Low-level input current

Vee = MAX,

VI = 0.4 V

-1.6

mA

ICC

Supply current, high-level output

Vee = MAX, See Note 2

ISN54136

30

43

JSN74136

30

50

mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
= 5 V, T A = 25°C.
NOTE 2: ICC is measured with one input of each gate at 4.5 V, the other inputs grounded, and the outputs open.

+AII typical values are at Vee

switching characteristics, Vee
PARAMETER~

tpLH

= 5 V, TA = 25° C
FROM

TEST CONDITIONS

(INPUT)

Other input low

A or B

tpHL
tpLH

eL=15pF,
RL =400

AorB

Other input high

tpHL

MIN

n,

See Note 3

TVP

MAX

12

18

39

50

14

22

42

55

UNIT

ns
ns

11 tp LH == propagation delay time, low-to-h igh-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10•.

1076

7-132

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS136, SN74LS136
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
WITH OPEN-COLLECTOR OUTPUTS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS136
SN74LS136
Storage temperature range

7V
7V
-55°e to 125°e
aOe to 7aoe
-65°e to 15aoe

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS136
MIN
4.5

Supply voltage, Vee

NOM

SN74LS136

MAX

MIN

5.5

4.75

5

High-level output voltage, VOH
-55

5

MAX
5.25

UNIT
V

5.5

5.5

4

8

mA

70

°e

Low-level output current, IOL
Operating free-air temperature, T A

NOM

125

0

V

eiectricai characteristics over recommended operating free-air temperature range (uniess otherwise noted;

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

IOH

SN54LS136

TEST eONDITIONst

PARAMETER

MIN

TYP:j:

SN74LS136
MIN

MAX

High-level output current

11=-18mA

Vce- MIN,

VIH-2V,

MAX

2

2

Vee = MIN,

TYP:j:

V

0.7

0.8

V

-1.5

-1.5

V

100

100

VIL = VIL max, VOH = 5.5 V
Vee= MIN,
IIOL = 4 mA
VIH=2V,
VIL=VILmaxi IOL=8mA

VOL Low-level output voltage

UNIT

0.25

0.4

0.25

0.4

0.35

0.5

V

I

I

/LA

II

Input current at maximum input voltage

Vce= MAX,

VI = 7V

0.2

0.2

IIH

High-level input current

Vce = MAX,

VI=2.7V

40

40

/LA

IlL

Low-level input current

Vce- MAX,

VI- 0.4 V

-0.8

-0.8

mA

lee

Supply current

Vee- MAX,

See Note 2

10

mA

6.1

6.1

10

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j:AII typical values are at V CC = 5 V, T A = 25°C.
NOTE 2: ICC is measured with one input of each gate at 4.5 V, the other inputs grounded, and the outputs open.

switching characteristics, Vee
PARAMETER~
tPLH

•

=5 V, TA = 25° C
FROM

TEST CONDITIONS

(INPUT)
AorB

Other input low

tpHL
tpLH

I

I

eL=15pF,
RL=2kn,

A orB

Other input high

tpHL

See Note 4

MIN

TYP

MAX UNIT

18

30

18

30

18

30

18

30

ns

ns

~ tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-133

TYPES SN54LS138, SN54LS139. SN54S138, SN54S139,
SN74LS138. SN74LS139. SN74S138. SN74S139
DECODERS/DEMULTIPLEXERS

TIL
MSI

BULLETIN NO. DL-S 7611

•

Designed Specifically for High-Speed:
Memory Decoders
Data Transmission Systems

DECEMBER 1972-REVISED OCTOBER 1976

SN54LS138, SN54S138 ••• J OR W PACKAGE
SN74LS138, SN74S138 ••• J OR N PACKAGE
(TOP VIEW)

'S138 and 'LS138 3-to-8-Line Decoders
Incorporate 3 Enable Inputs to Simplify
Cascading and/or Data Reception

•

•

'S139 and 'LS139 Contain Two Fully
Independent 2-to-4-Line Decoders/
Demultiplexers

•

Schottky Clamped for High Performance
TYPICAL

TYPE

PROPAGATION DELAY
(3 LEVELS OF LOGIC)

'LS138
'S138

DATA OUTPUTS
r -________
________
~A~

~

TYPICAL
POWER DISSIPATION

22 ns

32mW

8 ns

245mW

'LS139

22 ns

34mW

'S139

7.5 ns

300mW

positive logic: see function table

description

•

These Schottky-clamped TTL MSI circuits are
designed to be used in high-performance memorydecoding or data-routing applications requiring very
short propagation delay times. In high-performance
memory systems these decoders can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a fastenable circuit the delay times of these decoders and
the enable time of the memory are usually less than
the typical access time of the memory. This means
that the effective system delay introduced by the
Schottky-clamped system decoder is negligible.

SN54LS139, SN54S139 •.• J OR W PACKAGE
SN74LS139, SN74S139 ••• J OR N PACKAGE
(TOP VIEW)

SELECT

Vee

DATA OUTPUTS

EN~~LE~~

~

The 'LS138 and 'S138 decode one-of-eight lines
dependent on the conditions at the three binary
select inputs and the three enable inputs. Two
active-low and one active-high enable inputs reduce
the need for external gates or inverters when
expanding. A 24-line decoder can be implemented
without external inverters and a 32-line decoder
requires only one inverter. An enable input can be
used as a data input for demultiplexing applications.

12345618

1G

1A

16

ENA6LE'-v--'
SELECT

lYO

lY1

1Y2

lY3

~

GND

DATA OUTPUTS

positive logic: see function table

The 'LS139 and 'S139 comprise two individual two-line-to-four-line decoders in a single package. The active-low enable
input can be used as a data line in demultiplexing applications.
All of these decoders/demultiplexers feature fully buffered inputs each of which represents only one normalized Series
54LS/74LS load ('LS138, 'LS139) or one normalized Series 54S/74S load ('S138, 'S139) to its driving circuit. All
inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design. Series
54LS and 54S devices are characterized for operation over the full military temperature range of -55°C to 125°C;
Series 74LS and 74S devices are characterized for oOe to 70°C industrial systems.
1076

7-134

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS138, SN54S138, SN54LS139, SN54S139
SN74LS138, SN74S138, SN74LS139, SN74S139
DECODERS/DEMULTIPLEXERS
functional block diagrams and logic
'LS138, 'S138
FUNCTION TABLE

'LS138, 'S138
INPUTS

DATA
OUTPUTS

jr

A

SELECT
INPUTS

8

_

131

"'-

.

"'-

.

l'-~

OUTPUTS

SELECT

ENABLE

B

A

YO Y1 Y2 Y3 Y4 Y5 Y6 Y7

X

X

X

H

H

H

H

H

H

H

H

X

X

X

H

H

H

H

H

H

H

H

L

L

L

I,

H

H

H

H

H

H

H

L

L

L

H

H

L

H

H

H

H

H

H

H

L

L

H

L

H

H

L

H

H

H

H

H

H

L

L

H

H

H

H

H

L

H

H

H

H

H

L

H

L

L

H

H

H

L

H

H

H

I I~

L

H

H

H

H

L

H

~I

G1

G2*

X

H

L

X

H

L

H

C

H

L

H

L

H

H
L

H

L

H

H

= G2A + G2B
= high level, L = low

I

H
H
H

H

H

H

H

H

L

H

H

H

H

H

H

H

'G2
H

level, X

=

irrelevant

'LS139, '5139
'LS139, '5139
(EACH DECODER/DEMUL TIPLEXER)
FUNCTION TABLE
INPUTS
ENABLE
DATA
OUTPUTS

B

A

YO Y1 Y2 Y3

H

X

X

H

,H

H

H

L

L

L

L

H

H

H

L

L

H

H

L

H

H

L

H
H

,L

H

H

L

H

H

H

H

H

L

level, L

= low

L
H

schematics of inputs and outputs
EQUIVALENT OF EACH
INPUT OF 'LS138, 'LS139

vcc--.......- -

v cc

c

---~~-vcc

level, X

=

irrelevant

•

TYPICAL OF OUTPUTS
OF 'S138, 'S139

-----vcc

2.8 kn NOM

20 kn NOM
INPUT_.,........~~

-

= high

TYPICAL OF OUTPUTS
OF 'LS138, 'LS139

EQUIVALENT OF EACH
INPUT OF 'S138, 'S139

OUTPUTS

SELECT

G

INPUT

--

L..--+__

OUTPUT

OUTPUT

1272

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-135

TYPES SN54LS138, SN54LS139, SN74LS138, SN74LS139,
DEC 0 DERS/ DEMU LTI PLEXERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage
Operating free-air temperature range: SN54LS138, SN54LS139 Circuits
SN74LS138, SN74LS139 Circuits
Storage temperature range

7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS138

SN74LSl38

SN54LSl39

SN74LSl39

MIN

NOM

4.5

Supply voltage, Vee

5

MAX

MIN

NOM

5.5

4.75

5

-400

High-level output current, IOH

5.25

V

-400

J.lA

8

rnA

70

°e

4

Low-level output current, IOL
-55

Operating free-air temperature, T A

125

UNIT

MAX

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LSl38
PARAMETER

TEST CONDITIONSt

MIN
VIH High-level input voltage
VIL Low-level input voltage
VIK

SN74LS139

TYP:j: MAX

MIN

2

I nput clamp voltage

VOH High-level output voltage

Vee; MIN,

II ;-18mA

Vee = MIN,

VIH = 2 V,

2.5

VIL = VIL max, IOH = -400 IlA
Vee= MIN,

VOL Low-level output voltage

VIH = 2 V,

Input current at

V

2
0.8

-1.5

-1.5

3.4

2.7

0.25

IIOL = 4 mA

UNIT

TYP:j: MAX

0.7

0.4

IIOL = 8mA

VIL = VIL max

•

SN74LS138

SN54LSl39

V
V
V

3.4
0.25

0.4

0.35

0.5

V

Vee= MAX,

VI = 7V

0.1

0.1

mA

IIH

High-level input current

Vee; MAX,

VI = 2.7 V

20

20

IlL

Low-level input current

Vee - MAX,

VI - 0.4 V

-0.4

-0.4

Il A
mA

Short-circuit output current ~

Vee; MAX

II

lOS
, lee

maximum input voltage

I'LS138

I Outputs en---..------ .

~

I I I

~

I

RIPPLE 8L4.NK!NG
BLANKING

I

I

D!;C!~..A.L

INPUT

I

I
--<:t>
... Dynamic input activated by a transition from a high level to a low level.
I

I

TYPICAL APPLICATION DATA
This application demonstrates how the drivers may be cascaded for N-bit display applications. It features:
Synchronous, look-ahead counting
Ripple blanking of leading zeros; blanking of trailing zeros (not illustrated) can also be implemented
Overriding blanking -for total suppression or intensity modulation of display
Direct parallel clear
Latch strobe permits counter to acquire next display while viewing current display

RIPPLE BLANK ING INPUT
CLOCK INPUT
LATCH STROBE
INPUT

1111

iii

CK

RBO

STROBE

p-----------<:

RBI

CK

RBO

STROBE

p----------c

RBI

CK

RBO

----< ~;~NT

SCEI

p-----------<: ~;~NT

SCEI

P----------< ~~NT

SCEI

CLEAR

PCEI

CLEAR

PCEI

CLEAR

PCEI

=if "' "'''''''''''''~ r"' "'' ' ' ' ' ' ~ r"' ",, , , , , ,",
I
{

OVERRIDING
BLANKING INPU T l
H
CLEAR INPUT
DECIMAL POINT
INPUTS

I

I II I II I I

I I I I I 11\

t~ ~~~~: :~,,~ U L ~~ 7;:~;~ U l ~~:;:7;~ U L ~~~" H~A
l........(: RBI

•

LEAST-SIGNI FICANT
DIGIT

1\

111111111

STROBE

TO NEXT
MORE
SIGNIFICANT
DIGIT

LED/LAMP DRIVER OUTPUTS

MOST-SIGNIFICANT
DIGIT

STROBE

CK

p-----------<:

RBI

RBO

h

~;~NT

SCEI

CLEAR

PCEI

J
p- 0 PEN

nr "' ""'"' ' ' -

ht

f>"i

J

v
LATCH LOGIC OUTPUTS

tThe serial count-enable input of the least-significant digit is normally grounded; however, it may be used as a count-enable control for the
entire counter (high to disable, low to count) provided the logic level on this pin is not changed while the clock line is low or false counting
may result.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-147

TTL

TYPES SN54145, SN54LS145, SN74145, SN74LS145

MSI

BCD-lO-DECIMAL DECODERS/DRIVERS
BULLETIN NO. DL-S 7611815. MARCH 1974-REVISED OCTOBER 1976

FOR USE AS LAMP, RELAY, OR MOS DRIVERS
•

Full Decoding of Input Logic

•

SN54145, SN74145, and SN74LS145 Have
SO-rnA Sink-Current Capability

•

All Outputs Are Off for Invalid
BCD Input Conditions

•

Low Power Dissipation of 'LS145 ...
35 mW Typical

SN54145, SN54LS145, . ,J OR W PACKAGE
SN74145, SN74LS145 . , ,J OR N PACKAGE
(TOP VIEW)

logic
FUNCTION TABLE
NO:
0

l'

2
3
4
5

6
7

D

C

B

A

0

1

L
L
L
L
L
L
L
L

L L
L L
L H
L H
H L
H L

L

L
H

H

H

H

L

H

H

H

H

H

H

H

H

L

H

H

H

L
L

L
H

H

H

L
H

H

H

H

H

L
H

H

H

H

H

L

H

H

H

H

H

Q

H

L

L
L
H
H

:J

H

H

L

>

H

H

H

H

L
H

H

H

H

8
9

H

«

~

I

H

= high

OUTPUTS

INPUTS

level (oft), L

H

L

L
H

H

H

H

H

L

H

H

H

H

H

= low level

3 4 5
H H H H
H H H H
L H H H
H L H H
H H L H
H H H L
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
H H H H
2

6

7

8

9

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L
H

H

H

H

L
H

H

H

L

H

H
H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

R

H

H

H

H

.

OuTPUTS

positive logic: see function table

functional block diagram

(on)

description
These monilithic BCD-to-decimal decoder/drivers
consist of eight inverters and ten four-input NAND
gates. The inverters are connected in pairs to make
BCD input data available for decoding by the NAND
gates. Full decoding of valid BCD input logic ensures
that all outputs remain off for all invalid binary input
conditions. These decoders feature high-performance,
n-p-n output transistors designed for use as indicator/
relay drivers or as open-collector logic-circuit drivers.
Each of the high-breakdown output transistors
(15 volts) of the SN54145, SN74145, or SN74LS145
will sink up to 80 milliamperes of current. Each input
is one Series 54/74 or Series 54LS/74LS standard
load, respectively. Inputs and outputs are entirely
compatible for use with TTL or DTL logic circuits,
and the outputs are compatible for interfacing with
most MOS integrated circuits. Power dissipation is
typically 215 milliwatts for the '145 and 35 milliwatts
for the 'LS145.

1076

7-148

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

lYPES SN54145, SN74145
BCD-lO-DECIMAL DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Maximum current into any output (off-state)
Operating free-air temperature range: SN54145
SN74145
Storage temperature range

7V
5.5 V
1 mA

-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54145
MIN
4.5

Supply voltage, Vee

SN74145

NOM

MAX

MIN

5

5.5

4.75

Off-state output voltage, VO(off)

NOM
5

15
-55

Operating free-air temperature, T A
_.-

125

0

UNIT

MAX
5.25

V

15

V

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

10(off)

Off-state output current

VO(on)

On-state output voltage

!;

Input current at maximum input voltage

Vee = MAX,

MIN

TYPt

MAX

UNIT

2

Vee= MIN,

II = -12 rnA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

VO(off) = 15 V

Vee= MIN,

VIH=2V,

V

-1.5

V

250
0.5

110(on) = 80 rnA

VIL = 0.8 V

V

0.8

/JA

0.9

V

0.4

110(on) = 20 rnA

rnA

i

Vi = 5.5 V

IIH

High-level input current

Vee = MAX, VI=2.4V

40

/JA

IlL

Low-level input current

Vee= MAX, VI=OAV

-1.6

rnA

lee

Supply current

Vee = MAX, See Note 2

ISN54145

43

62

ISN74145

43

70

rnA

II

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at VCC = 5 V. T A = 25°C.
NOTE 2: ICC is measured with all inputs grounded and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e

1

PARAMETER

TEST CONDITIONS

Propagation delay time, low-to-high-Ievel output 1
Propagation delay time, high-to-Iow-Ievel output I eL = 15 pF,
NOTE 3:

RL

= 100 n,

See Note 3

I MIN

MAX

1

50

I

50

I UNIT

I
I

ns
ns

Load circuit and waveforms are shown on page 3-10.

schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

Vcc _ _ _ _- OUTPUT

INPUT

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-149

TYPES SN54LS145, SN74LS145
BCD-lO-QECIMAL DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS145
SN74LS145
Storage temperature range

7V
7V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS145
MIN
Supply voltage, Vee
Off-state output voltage, VO(off)

4.5

SN74LS145

NOM

MAX

MIN

5

5.5

4.75

NOM
5

MAX

V

15

V

70

°e

15

Operating free-air temperature, T A

-55

125

UNIT

5.25

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low·level input voltage

VIK

Input clamp voltage

10(off)

Off-state output current

VO(on)

•

TEST CONDITIONSt

SN54LS145
TYP:j:

MIN

SN74LS145

MAX

2

On-state output voltage

Vee= MIN,

II = -18 mA

Vee = MIN,

VIH = 2 V,

VIL = VIL max,

VOH = 15 V

Vee = MIN,

IIOL = 12 mA

MIN

TYP:j:

MAX

2

V

0.7

0.8

V

-1.5

-1.5

V

250

p.A

250
0.25

UNIT

0.4

0.25

0.4

VIH = 2 V,

tlOL = 24 mA

0.35

0.5

Vil = Vil max

II0l = 80 mA

2.3

3

V

II

Input current at maximum input voltage

Vee = MAX,

VI = 7V

0.1

0.1

IIH

High-level input current

Vee= MAX,

VI=2.7V

20

20

p.A

III

low-level input current

Vee= MAX,

VI = 0.4 V

-0.4

-0.4

mA

lee

Supply current

Vee= MAX,

See Note 2

13

mA

7

13

7

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V. T A = 25°C.
NOTE 2: ICC is measurod with a!! inputs grounded and ovtputs

switching characteristics, Vee

ope~.

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

J--:tP...:;l::.;H..:......_P_r_op:...a...;;g_at_io_n_d_e_la_y_t_im_e,_I_ow..,--to_-_h...:;ig_h_-le_v_e_1o_u_t,;..pu_t-l el
tpHl
Propagation delay time, high-to-Iow.level output

= 45 pF,

MIN

See Note 4

MAX
50
50

NOTE 4: Load circuit and waveforms are shown on page 3-11.

schematic of inputs and outputs

q

EQUIVALENT OF EACH INPUT

VCC

TYPICAL OF ALL OUTPUTS

17 kfl NOM

INPUT

--

1076

7-150

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54147, SN54148, SN54LS147, SN54LS148,
TTL
SN74147, SN74148 {TIM9907),SN74LS147, SN74LS148
MSI 10-UNE-TO-4-UNE AND 8-UNE-TO-3-UNE PRIORITY ENCODERS
BULLETIN NO.

'147, 'LS147
•

Encodes 10-Line Decimal to 4-Line BCD

•

Applications Include:

o LoS

7611727, OCTOBER-1S-76

SN54147, SN54LS147 ••• J OR W PACKAGE
SN74147, SN74LS147 ••• J OR N PACKAGE
(TOP VIEW)
INPUTS
NC OU-g'UT~OU-ZUT

Keyboard Encoding
Range Selection
'148, 'LS148
•

Encodes 8 Data Lines to 3-Line Binary (Octal)

•

Applications Include:
N-Bit Encoding
Code Converters and Generators
TYPICAL
TYPE

TYPICAL

DATA

POWER

DElAY

DlSS!PAT!QN

'147

10 ns

225mW

'148

10 ns

190mW

'LS147

15 ns

60mW

'LS148

15 ns

60mW

positive logic: see function table
NC-No internal connection

SN54148, SN54LS148 • ,. J OR W PACKAGE
SN74148, SN74LS148 ••• J OR N PACKAGE
(TOP VIEW)

description
These TTL encoders feature priority decoding of the
inputs to ensure that only the highest-order data line
is encoded. The '147 and 'LS147 encode nine data
lines to four-line (8-4-2-1) BCD. The implied decimal
zero condition requires no input condition as zero is
encoded when all nine data lines are at a high logic
level. The '148 and 'LS148 encode eight data lines to
three-line (4-2-1) binary (octal). Cascading circuitry
(enable input EI and enable output EO) has been
provided to allow octal expansion without the need
for external circuitry. For all types, data inputs and
outputs are active at the low logic level. All inputs are
buffered to represent one normalized Series 54/74 or
54LS/74LS load, resp-ectively.

•
positive logic: see function table

'147, 'LS147

'148, 'LS148

FUNCTION TABLE

FUNCTION TABLE
OUTPUTS

INPUTS

H

INPUTS

OUTPUTS

1

2

3

4

5

6

7

8

9

0

C

B

A

EI

0

1

2

3

4

5

6

7

A2

Al

AO

H

H

H

H

H

H

H

H

H

H

H

H

H

H

X

X

X

X

X

X

X

X

H

H

H

H

X

X

X

X

X

X

X

X

L

L

H

H

L

L

H

H

H

H

H

H

H

H

H

H

H

H

L

X

X

X

X

X

X

X

L

H

L

H

H

H

L

X

X

X

X

X

X

X

L

L

L

L

L

H

X

X

X

X

X

X

L

H

H

H

L

L

L

L

X

X

X

X

X

X

L

H

L

L

H

L

H

X

X

X

X

X

L

H

H

H

H

L

L

H

L

X

X

X

X

X

L

H

H

L

H

L

L

H

X

X

X

X

L

H

H

H

H

H

L

H

L

L

X

X

X

X

L

H

H

H

L

H

H

L

H

X

X

X

L

H

H

H

H

H

H

L

H

H

L

X

X

X

L

H

H

H

H

H

L

L

L

H

X

X

L

H

H

H

H

H

H

H

H

L

L

L

X

X

L

H

H

H

H

H

H

L

H

L

H

GS EO
H

X

L

H

H

H

H

H

H

H

H

H

L

H

L

X

L

H

H

H

H

H

H

H

H

L

L

H

L

H

H

H

H

H

H

H

H

H

H

H

L

L

L

H

H

H

H

H

H

H

H

H

H

L

H

= ~igh

logic level, L

= low

logic level, X

= irrelevant

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-151

TYPES SN54147, SN54148, SN54LS147, S-N54LS148.
SN74141. _ SN74148 (TIM9907), S-N74L8141, SN74L8148
10-LlNE-TO-4-LlNE AND 8-LlNE-TO-3-LlNE PRIORITY ENCODERS
functional block, diagrams

•

1076

7-152

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES S~54147, S1\(54148, SN54LS147, SN54LS148,
SN74147, SN74148 (TIM9907) SN74LS147, SN14LS148
10-LlNE-TO-4-LlN~ AND 8-LlNE-TO-3-LlNE PRIORITY ENCODERS
schematics of inputs and outputs
'147, '148
EaUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

Vee ---~.....- - -

-----1.....- - V e e

INPUT

OUTPUT

o input ('148): Req
All other inputs: Req

=

2 kn NOM

= 4 kn NOM
'LS147, 'LS148

EaUiVALENT OF ALL iNPUTS

TYPICAL OF ALL OUTPUTS
----~~-Vee

Vee------1.....- -

INPUT-...,..........,.....-..-.

--tz}

OUTPUT

'LS148 inputs 1 thru 7: Req = 9 kn NOM
All other inputs: Req = 18 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage: '147, '148
'LS147, 'LS148
I nteremitter voltage: '148 only (see Note 2)
Operating free-air temperature range: SN54', SN54LS Circuits
SN74', SN74LS Circuits
Storage temperature range
NOTES:

. 7V
5.5 V

•

. 7V
5.5 V
-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

1. Voltage values, except intermitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For '148 circuits, this rating applies between any two of
the eight data lines, 0 through 7.

recommended operating conditions
MIN
Supply voltage, Vee

4.5

High-level output current, IOH

MIN

5.5

4.75

5

125

MIN

5.25

4.5

-800

16
-55

SN74'
NOM MAX
5

-800

Low-level output current, IOL
Operating free-air temperature, T A

SN54'
NOM MAX

70

MIN

NOM

MAX

5.5

4.75

5

5.25

V

-400

p.A

8
70

rnA
°e

5

-400

16
0

SN74LS'

SN54LS'
NOM MAX

4
-55

125

0

UNIT

1076

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-153

TYPES SN54147. SN54148. SN74147. SN74148(TIM9907)1
10-UNE-TO-4-UNE AND 8-UNE-TO-3-UNE PRIORITY ENCODERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

VOH

High-level output voltage

TEST CONDITIONSt

'147

'148

MIN TVP:j: MAX

MIN TVP:j: MAX

2

VOL

Low-level output voltage

II

I nput current at maximum input voltage

IIH

High-level input current

o input
Any input except 0

o input

IlL

Low-level input current

lOS

Short-circuit OUtput current §

ICC

Supply current

Vee= MIN,

II = -12 mA

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

10H = -SOOIlA

Vee- MIN,

VIH - 2 V,

VIL = 0.8 V,

10L = 16mA

Vee= MAX,

VI = 5.5 V

Vee = MAX,

VI = 2.4 V

Vee = MAX,

Any input except 0

2.4

UNIT
V

2
0.8

0.8

V

-1.5

-1.5

V

3.3

2.4

0.2

3.3
0.2

0.4

V
0.4

1

1

V
mA

40

80

40

-1.6

VI = 0.4 V

-1.6
-35

Vce= MAX

-85

-3.2
-35

IlA
mA

-85

mA

Vee = MAX, ICondition 1

50

70

40

60

mA

See Note 3

42

62

35

55

mA

ICondition 2

NOTE 3: For '147, ICC (condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (condition 2) is measured with
all inputs and outputs open. For '148, ICC (condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open;
ICC (condition 2) is measured with all inputs and outputs open.
t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V. T A = 25°c.
;iNot more than one output should be shorted at a time.

SN54147, SN74147 switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER~

•

tPLH

FROM

TO

(INPUT)

(OUTPUT)

Any

WAVEFORM

Any

tpHL

output

tpLH

Out-of-phase

Any

Any

PARAMETER~

tPLH
tpLH
tPHL

TO

(INPUT)

(OUTPUT)

o thru 7

tpHL

I

FROM

tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH

I

I

o thru 7
o thru 7
EI

!
i

EO

EI

EO

14

7

11

13

19

12

19

ns
ns

10
9

14

Out-of-phase

13

19

12

19

6

10

output
Out-of-phase

I

In-phase

tpHL

TVP MAX UNIT

output

output

tPHL
tPLH

TEST CONDITIONS MIN

output

AO, A1, or A2
GS

9

In-phase

In-phase

GS

EI

n,

See Note 4

WAVEFORM

AO, Al, or A2

I

I

RL = 400

TVP MAX UNIT

= 5 V, T A = 25°e

AO, Al, or A2

o thru 7
I

CL=15pF,

output

tPHL

SN54148, SN74148 switching characteristics, Vee

TEST CONDITIONS MIN

In-phase

eL = 15pF,
RL=400n,
See Note 4

15

14

25

18

30

14

25

10

15

output

10

15

In-phase

8

12

output

10

15

In-phase

10

15

output

17

30

ns
ns

I ns
ns
ns
ns
ns

~tPLH

== propagation delay tim·e. low·to·high·level output
tPH L == propagation delay time, high·tO·low·level output
NOTE 4: Load circuits and waveforms are shown on page 3-10.
1076

7-154

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS147, SN54LS148, SN74LS147, SN74LS148
10-UNE-TO-4-UNE AND 8-UNE-TO-3-UNE PRIORITY ENCODERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

2

VCC= MIN,

11- -18 mA

VCC = MIN,

VIH = 2 V

VIL = 0.8 V,

VOL Low-level output voltage

10H =-400!LA

Input current at

'LS148 inputs 1 thru 7
All other inputs

VCC = MAX,

'LS148 inputs 1 thru 7

High-level input current

All other inputs
'LS148 inputs 1 thru 7

-1.5

V

2.5

3.4

2.7

V

0.25

0.4

0.25

0.4

0.35

0.5

IlL

Low-level input current

lOS

Short-circuit output current§

ICC

Supply current

All other inputs

V

VI_=7V

VCC= MAX,

VI = 2.7 V
VI = Q,4V

Vee = MAX

V

3.4

VIH =2V,
VIL = VILmaxllOL =8 mA

maximum input voltage

0.8

-1.5

110L =4 mA

UNIT
V

0.7

VCC = MIN,

IIH

SN74LS'

MIN TYP:j: MAX MIN TYP:j: MAX
2

VOH High-level output voltage

II

SN54LS'

TEST CONDITIONSt

PARAMETER

0.2

0.2

0.1

0.1

40

40

20

20

-0.8

-0.8

-0.4
-20

Vcr. = MAX

-0.4

-100 -20

-100

mA
!LA
ml. .~

mA

VCC = MAX,

ICondition 1

12

20

12

20

mA

See Note 5

ICondition 2

10

17

10

17

mA

NOTE 5: For 'LS147, ICC (condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (condition 2) is measured
with all inputs and outputs open. For 'LS148, ICC (condition 1) is measured with inputs 7 and EI grounded, other inputs and
outputs open, ICC (condition 2) is measured with all inputs and outputS open.
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli tYpical values are at V CC = 5 V, T A = 25°C.
~ Not more than one output should be shorted at a time.

SN54LS147, SN74LS147 switching characteristics, Vee
PARAMETER'!
tPLH

FROM

TO

!INPUT)

(OUTPUT)

Any

=

WAVEFORM

Any

output

SN54LS148, SN74LS148 switching characteristics, Vee
FROM

TO

!INPUT)

(OUTPUT)

Othru 7

AO,A1,orA2

RL=2kn,
See Note 4

Out-of-phase

tPHL

PARAMETER~

CL=15pF,

output

Any

Any

TEST CONDITIONS MIN

In-phase

tpHL
tPLH

5 V, TA = 25°e

=

TYP MAX UNIT
12

18

17

25

24

36

19

29

TEST CONDITIONS MIN

12

18

output

25

tPLH

Out-of-phase

17
24

36

19

29

12

18

6

15
23

Othru 7

AO,A1,orA2

tPLH
tpHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH

Othru 7

output
Out-of-phase

EO

o thru 7
EI

AO, A1, or A2

EI

GS

EI

tPHL

output
In-phase

GS

I

j

output
In-phase

EO

II

TYP MAX UNIT

In-phase

tPHL

ns

5 V, TA = 25°e

WAVEFORM

tPHL

tPLH

ns

CL=15pF,
RL = 2 kn,
See Note 6

15
14
12

output

17

In-phase

11

ns
ns
ns
ns

21
18

ns

output

24

25
17
36

In-phase

14

21 '

output

17

25 I

I

ns
ns

'li tPLH == propagation delay time, low-to-high-Ievel output
tPHL:: propagation delay time, high-to-Iow-Ievel output
NOTE 6: Load circuits and waveforms are shown on page 3-11.
1076

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
I nstruments reserves the right to change or discontinue this product without notice.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

CALLAS. TEXAS 75222

7-155

TYPES SN54147, SN54148 (TIM9907)' SN54LS147, SN54LS148,
SN74147, SN74148, SN74LS147, SN74LS148
----10-LlNE-TO-4-LlNE AND
8-LI
NE-TO-3-LlNE
PRIORITY
ENCODERS
----TYPICAL APPLICATION DATA

~

16-LlNE DATA
________________________
______________________
--JA~

~

/

ENABLE

o

2

3

4

5

6

7

o

EI

SN54148/SN74148,
SN54LS148/SN74LS148

EO

2

3

4

5

6

7

EI

SN54148/SN74148,
SN54LS148/SN74LS148

EO

GS

GS

SN5400/SN7400
SN54LSOO/SN74LSOO

•

PRIORITY
FLAG
Full 4-bit binary 16-line-to-4-line encoding can be implemented as shown above. The enable input must be low to
enable the function. Decoding with 2·input NAND gates produces true (active-high) data for the 4-line binary outputs.
If active-low data is required, the SN5408/SN7408 or SN54LS08/SN74LS08 AND gate may be used, respectively.

1076

7-156

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54150, SN54151A, SN54152A. SN54LS151, SN54LS152, SN54S151,
.
SN74150, SN74151A, SN74LS151, SN74S151
DATA SELECTORS/MULTIPLEXERS
BULLETIN NO. DL-S 7611819, DECEMBER 1972-REVISED OCTOBER 1976

SN54150 _ •. J OR W PACKAGE
SN74150 •• _J OR N PACKAGE
(TOP VIEW)

•

'150 Selects One-of-Sixteen Data Sources

•

Others Select One-of-Eight Data SourCes

•

Performs Parallel-to-Serial Conversion

•

Permits Multiplexing from N Lines to
One Line

•

Also For Use as Boolean Function
Generator

•

Input-Clamping Diodes Simplify System
Design

•

Fully Compatible with Most TTL and DTL
Circuits
positive logic: see function table
TYPICAL AVERAGE
TYPE

TYPICAL

PROPAGATION DELAY TIME

POWER

DATA INPUT TO W OUTPUT

DISSIPATION

'150

11 ns

200mW

'151A

8 ns

145mW

'152A

8 ns

130mW

'L8151

11 nst

30mW

'L8152

11 nst

'8151

4.5ns

SN54151A,SNJ=.ALS151, S~':54S151 ••• J OR 'l'J PACKAGE
SN74151A SN74LS151,SN74S151 ••• J OR N PACKAGE
(TOP VIEW)

28mW
225mW

t Tentative data

description
STROBE

These monolithic data selectors/multiplexers contain
full on-chip binary decoding to select the desired data
source. The '150 selects one-of-sixteen data sources;
the '151A, '152A, 'LS151, 'LS152, and 'S151 select
one~9f~eight data sources. The '150, '151A,'LS151,
and" 'S151 have a strobe input which must be at a low
logic level to enable these devices. A high level at the
strobe forces the W output high, and the Y output (as
applicable) low.

DATA INPUTS

OUTPUTS

positive logic: see function table

II

SN54152A, SN54LS152 __ • W PACKAGE
(Top VIEW)

The '151A, 'LS151, and 'S151 feature complementary Wand Y outputs whereas the '150, '152A, imd
'LS152 have an inverted (W) output only.
The '151A and '152A incorporate address buffers
which have symmetrical propagation delay times
through the complementary paths. Th is reduces the
possibility of transients occurring at the output(s)
due to changes made at the select inputs, even
when the '151A outputs are enabled (i.e., strobe low).

~2~W

-v----

OUTPUT

positive logic: see function table

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-157

TYPES SN54150, SN54151A, SN54152A, SN54LS151, SN54LS152, SN54S151,
SN74150, SN74151A SN74LS151, SN74S151
DATA SELECTORS/MUtTIPLEXERS
REVISED OCTOBER 1976

logic

'150

'151A, 'LS151, 'S151

'152A, 'LS152

FUNCTION TABLE

FUNCTION TABLE

FUNCTION TABLE

INPUTS

SELECT

INPUTS

D

C

B

OUTPUT

SELECT

STROBE

SELECT

W
A

S

X

X

X

X

H

H

L

L

L

L

L

L

L

L

H

L

L

L

H

L

L

L

L

H

H

L

l

H

L

L

L

L

H

L

H

L

L

H

H

L

L

Eo
IT
E2
E3
E4
E5
Es
E7
Es
E9

L

H

H

H

L

H

L

L

L

L

H

L

L

H

L

H

L

H

L

L

El0

H

L

H

H

L

Ell

H

H

L

L

L

E12

H

H

L

H

L

E13

H

H

H

L

L

E14

H

H

H

H

L

E15

OUTPUTS

STROBE

Y

OUTPUT

INPUTS

W

W

C

B

A

S

X

X

X

H.

L

H

L

L

L

L

L

L

L

09

L

L

H

L

L

H

L

01

Do
51

L

H

L

52

L

H

L

L

02

52

L

H

H

53
54

C

B

A

L

H

H

L

03

53

H

L

L

H

L

L

L

04

54

H

L

H

H

L

H

L

05

H

H

L

H

H

L

L

06

Os
56

H

H

H

L

07

H

H

H

07

DO

01

05

00
i57

level, X = irrelevant
EO, E 1 ... E 15 = the complement of the level of the respective E input
DO, D1 ... D7 = the level of the D respective input

~= ~gh le~L

= low

-

'151A, 'LS151, 'S151
DO.!!!.I"_ _ _ _-==rq;;[)---,=~i

-

01

functional block diagrams

131

o,.£L"'------F=='===l~::rl
D3

'150

m

IN"'" "'=""----l=r=i=l=E=;:::fl

....
" I.
"

I

El

os.

not)

08(131

m

07(121

~I

'1S2A, 'L5152
00 ~I

0,(11)

",Ill

£'10

l

03Q1

(21.

_m

::~:
e1i1

1t7}

£15

(161

se~~i;{:~::::

oe{1!

osn31
08 112'1

D7(111

ADDRESS BUFFERS FOR '151A, '152A

ADDRESS BUFFERS FOR 'LS151, 'S151, 'LS152

'''''''',--''''-{''''~~
D~

1076

7-158

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54150, SN54151A, SN54152A, SN74150, SN74151A
DATA SELECTORS/MULTIPLEXERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage (see Note 2). . .
Operating free-air temperature range: SN54' Circuits
SN74' Circuits
Storage temperature range: . . . . . . . . . . .

7V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTES: 1. Voltage values a/with respect to network ground terminal.
2. For the '150, input voltages must be zero or positive with respect to network ground terminal.

recommended operating conditions
SN54'
MIN
4.5

Supply voltage, Vee

NOM
5

SN74'
MAX

MIN

5.5

4.75

NOM
5

-800

High-level output current, IOH

UNIT
MAX
5.25

V

-800

/.LA

16

rnA

70

°e

16

Low-level output current, 10L

125

-55

Operating free-air temperature, T A

0

---

electrical characteristics over recommended operating free-air temperature range (un!ess other.'Vise noted)
'151A, '152A

'150
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH
1VOL

TEST eONDITloNst

MIN

TYP:j: MAX MIN

2

TYP:j: MAX

V

2
0.8

High-level output volt~
Low-level output voltage

Vee = MIN,

11- -8 rnA

Vee = MIN,

VIH = 2 V,

VIL ~0.8V,

10H =-SOOJ,LA

Vee = MIN,

VIH =2V,

VIL = 0.8 V,

10L

II

Vee - MAX, VI- 5.5V

3.4
0.2

= 16mA

Input current at maximum input voltage

0.8
-1.5

2.4

2.4

3.4
0.2

0.4

UNIT

1

V
V
V

0.4
1

V

rnA

IIH

High-level input current

Vee - MAX,

VI- 2.4 V

40

40

/.LA

IlL

Low-level input current

Vee = MAX,

VI - 0.4 V

-1.6

-1.6

rnA

lOS

Short-circuit output current§

Vee= MAX

lee

Supply current

Vee

SN54'

-20

-55

-20

-55

SN74'

-18

-55

-18

-55

'150

= MAX,

See Note 3

40

rnA

68

'151A

29

48

'152A

26

43

rnA

•

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values at VCC = 5 V, T A = 25°C.
§ Not more than one output of the' 151 A should be shorted at a time.
NOTE 3: ICC is measured with the strobe and data select inputs at 4.5 V, all other inputs and outputs open.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-159

TYPES SN54150, SN54151A, SN54152A, SN74150, SN74151A
DATA SELECTORS/MULTIPLEXERS
switching characteristics, Vee
PARAMETER~

FROM

TO

TEST

(INPUT!

(OUTPUT!

CONDITIONS

tPLH

A, B,orC

tpHL

(4 levels!

tpLH

A, B,C, or D

tpHL

(3 levels!

tPLH

= 5 V, TA =25°e

W

Strobe

Y

CL = 15pF,

W

RL=400n,
See Note 4

Strobe

tpHL
tpLH

TYP

MAX

MIN

TYP

MAX

25

38

25

38

Y

tpHL
tpLH

. '151A, '152A

'150
MIN

23

35

17

26

22

33

19

30

21

33

22

33

15.5

24

14

21

21

30

15

23

13

20

18

27

Y

DO thru D7

tpHL
tpLH

EO thru E 15, or

tpHL

DO thru D7

W

13

20

8

14

8.5

14

8

14

UNIT
ns
ns
ns
ns
ns
ns

~tpLH '" propagation delay time, low·to·high·level output
tpH L '" propagation delay time, high·to·low·level output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-10.

schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
OF '150

EQUIVALENT OF EACH INPUT
OF '151A, '152A

Vee---~......- -

•

Vee - - - - 4......- -

INPUT

INPUT

~--------~I ~I______~
TYPICAL OF ALL OUTPUTS
OF '150, '151A, '152A

1076

7·160

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

CAL.LAS. TEXAS 75222

TYPES SN54LS151, SN54LS152, SN74LS151
DATA SELECTORS/MULTIPLEXERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . .
Input voltage . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS' Circuits
SN74LS' Circuits
Storage temperature range

7V
7V
-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

NOTE 1: Vo.ltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS'
I
IMIN NOM MAX

MIN

Supply voltage, Vee

!

4.75

High-level output current, 10H

I

Low-level output current, 10L
.'
I uperatlng
nee-air temperature,
~

I

-A

4.5

5

5.5

NOM

4

--

---

ILO

MAX
5.25

V
/-I A
rnA

8

-

I

UNIT

-400

5

-400

1-::>0

I

SN74LS'

-IU I

U

l.;

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

SN54LS'

TEST CONDITIONSt
MI!'I

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH High-Ieve: output voltage
VOL Low-level output voltage
Input current at

SN74LS'

TYP:j: MAX

MIN

2

Vee= MIN,

11=-18mA

Vee= MIN,

VIH = 2V,

2.5

VIL = VIL max, 10H = -400 /-IA
Vee= MIN,

VIH = 2V,

VIL = VIL max

MAX

2

UNIT
V

0.7

0.8

V

-1.5

-1.5

V

3.4
0.25

lIOL=4mA

TYP:j:

2.7
004

3.4
0.25
0.35

IIOL=8mA

V

004
0.5

V
rnA

Vee = MAX,

VJ =7 V

0.1

0.1

IIH

High-level input current

Vee= MAX,

VI = 2.7 V

20

20

/-IA

IlL

Low-level input current

Vee- MAX,

VI-OAV

-0.4

-004

rnA

lOS

Short-circuit output currentll

-100

rnA

II

lee

maximum input voltage

Supply current

Vee= MAX
Vee = MAX,

-100

-20
Outputs open, I

'LS151

6.0

10

I

'LS152

5.6

9

All inputs at 4.5 V

-20
6.0

10

rnA

•

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
0
:j:AII typical values are at V CC = 5 V, T A = 25 C.

§ Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-161

TYPES SN54LS151, SN54LS152, SN74LS151
DATA SELECTORS/MULTIPLEXERS
switching characteristics, Vee =5 V, TA = 25°e

I

PARAMETER~

FROM

TO

(INPUT)

(OUTPUT)

MIN

TVP

MAX

tPLH

A. B. orC

27

43

tPHL

(4 levels)

18

30

tpLH

A. B. orC

14

23

tPHL

(3 levels)

20

32

26

42

20

32

15

24

18

30

20

32

tPLH

y
W

y

Strobe

CL = 15pF.

tPHL

RL = 2 kn.

tPLH

Strobe

W

See Note 5

tPHL
tpLH

Any D

Y

tPHL

16

26

tPLH

13

21

12

20

Any D

W

tPHL

~ tPLH

SN54LS·. SN74LS'

TEST CONDITIONS

UNIT
ns
ns
ns
ns
ns
ns

:= Propagation delay time, low-to-high-Ievel output

tpHL:= Propagation delay time, high-to-Iow-Ievel output

NOTE 5: See load circuits and waveforms on page 3-11.

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
OF 'LS151. 'LS152

EQUIVALENT OF EACH INPUT
OF ·LS151. 'LS152

---'--VCC
VCC

•

------41.....---- ---

120

n NOM

Req

tNPUT-.~
Ll"1W
..
"""I---4I~_'-- OUTPUT

n'7
Data select and strobe:

Req

Data inputs:

Req

= 20 kn
= 17 kn

NOM
NOM

1076

1-162

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54S151, SN74S151
DATA SELECTORS/MULTIPLEXERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . .
........ .
Input voltage . . . . . . '
Operating free-air temperature range: SN54S151 Circuits
SN74S151 Circuits
Storage temperature range

7V
5.5V
-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54S151
MIN
Supply voltage, Vee

NOM

4.5

5

SN74S151

MAX

MIN

5.5

4.75

NOM
5

-1

High-level output current, IOH
low-level output current, 10l

20

Operating free-air temperature, T A

-55

125

0

UNIT

MAX
5.25

V

-1

rnA

20

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (uniess otherwise noted;
TEST eONDITloNst

PARAMETER
VIH

High-level input voltage

Vil

low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

V
0.8

low-level. output voltage

Vee = MIN,

II =-18mA

Vee= MIN,

VIH - 2 V,

Vil = 0.8 V,

IOH=-1 mA

Vee = MIN,

VIH - 2V,

VIL = 0.8 V,

iOl = 20 mA

II

Input current at maximum input voltage

Vee = MAX, VI = 5.5 V

High-level input current

Vee = MAX, VI-2.7V

III

low-level input current

Vee- MAX, VI = 0.5 V

lOS

Short-circuit output current!i

Vee - MAX

Supply current

TYP+ MAX UNIT

2

IIH

ICC

MIN

I

SN54S'

2.5

I SN74S'

2.7

All outputs open

V

3.4

V

3.4
0.5

V

11 mA
50
J.LA

45

I

I

I

I

-40

Vee= MAX, All inputs at 4.5 V,

V

-1.2

-2

mA

-100

mA

70

mA

•

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
+AII typical values are at V CC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-163

TYPES SN64S161, SN74S161
DATA SELECTORS/MULTIPLEXERS
switching characteristics, Vee = 5 V, TA
PARAMETER~

tpLH

A, B,orC
(4 levels)

tpLH
tpHL

A, B,orC
(3 levels)

tpLH

I

FROM
(INPUT)

tPHL

=25°e
TEST CONDITIONS

SN54S151, SN74S151
MIN

TYP

Y

W

Any 0

tpHL

TO
(OUTPUT)

= 15pF,

Y

CL

W

RL = 280
See Note 4

f!"

tpLH

Any D

tpHL
tPLH
tpHL

18
18

10

15

9

13.5

8

12

8

12

4.5

7
7
16.5
18
13
12

11
12

9

W

Strobe

12
12

4.5

Y

Strobe

tpLH

8.5

tPHL

MAX

UNIT

ns
ns
ns
ns
I'js
ns

~ tp LH == Propagation delay time, low-to·high·level output
tpH L == Propagation delay time, high·to·low·level output
NOTE 4: See load circuits and waveforms on page 3-10.

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
OF'S151

EQUIVALENT OF EACH INPUT
OF 'S151

- - - - -.....- - vee
50

v e e - - -....- - -

•

n

NOM

INPUT
OUTPUT

1272

7-164

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

TYPES SN54153, SN54L153, SN54LS153, SN54S153,
SN74153, SN74L153, SN74LS153, SN74S153
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

TTL
MSI

BULLETIN NO. DL-S 7611

DECEMBER 1972' -:- REVISE,?

ER 1976

SN54153, SN64LS153, SN54S153 ••• J OR W PACKAGE
SN64L 153 ••• J PACKAGE
SN74153, SN74L153,SN74LS153,SN74S153 ••• J OR N PACKAGE
,
(TOP VIEW)

•

Permits MultiplexiJ'lg from N lines to 1 line

•

Performs Parallel-to-Serial Conversion

•

Strobe (Enable) Line Provided for Cascading
(N lines to n lines)

•

High-Fan-Out, Low-Impedance, Totem-Pole
Outputs

•

Fully Compatible with most TTL and DTL
Circuits
positive logic: see function table
TYPICAL AVERAGE

TYPE

PROPAGATION DELAY TIMES
FROM
DATA

FROM
STROBE

TYPICAL
POWER

FROM
SELECT

DISSIPATION

'153

14 ns

17 ns

22 ns

180mW

'L153

27 ns

34 ns

44 ns

90mW

'LS153

14 ns

19 ns

22 ns

31 mW

6

'S153

ns

9.5 ns

12 ns

FUNCTION TABLE
SELECT

225mW

I

'-

description

,-

Each of these monolithic, data selectors/multiplexers
contains inverters and drivers to supply fully
complementary, on-chip, binary decoding data
selection to the AND-OR-invert gates. Separate strobe
inputs are provided for each of the two four-line
sections.

DATA INPUTS

INPUTS

STROBE OUTPUT

B

A

CO

C1

C2

C3

G

Y

X

X

X

X

X

X

H

L

L

L

1:-

X

X

X

L

L

L

L

H

X

X

X

L

H,

L

H

X

X

L

L

H

X

L
H

X

L

X

X

L

H

'I-i

L

X

X

L

X

L

L

H
H
H

L

X

X

H

X

L

H

H
H

X

X

X

L

L

L

X

X

X

H

L

H

•

Select inputs A and B are common to both sections,
H = high level. L = low level. X = irrelevant

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage: '153, 'L153, 'S153 . . . . . . . . . . . . . . . . . .
'LS153 . . . . . . . . . . . . . . . . . . . . . . .
O1>erating free-air temperature range: SN54', SN54L', SN54LS', SN54S' Circuits
SN74', SN74L', SN74LS', SN74S' Circuits
Storage temperature range . . . . . . . . . . . .

.

7V

5.5 V
7V

-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-165

TYPES SN54153, SN54L153, SN54LS153, SN54S153,
SN74153, SN74L15-3, SN74LS153, SN74S153
DU"AL 4-LlNE-TO-1-LlNE DATA SELECTORS/MULTIPLEXERS
REVISED OCTOBER 1976

functional block diagram
STROBE lG
(ENABLE)

(1)

ICO

--:-c-------++-+-1

lCl

------t-t-t--H..-.J

(5)

DATA 1
(4)

lC2 -----+-t-++-t-L..-/
lC3

(3)

2C0

(10)

2Cl

(11)

2C2

(12)

2C3

(13)

OATA2

STROBE 2G
(ENABLE) (15)

schematics of inputs and outputs
EQUIVALENT OF INPUTS OF '153, 'L 153

•

EQUIVALENT OF INPUTS OF 'LS153

V C CReq
3-INPUT

EQUIVALENT OF INPUTS OF 'S153

VCC?1-20 kn NOM

--

INPUT

m

VCCy
r)
- NOM'
2.8
kn

--

INPUT

~

--

~

'153: Req = 4 kn NOM
'L 153: Req = 8 kn NOM

TYPICAL OF OUTPUTS OF '153, 'L 153

TYPICAL OF OUTPUTS OF 'LS153, 'S153
------VCC

VCC

OUTPUT
OUTPUT

'153: R
'L 153: R

= 130 n
= 260 n

'LS153: R = 120
'5153: R = 50

NOM
NOM

n
n

NOM
NOM

1076

7-166

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54153, SN74153
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN54153
MIN
Supply voltage, Vee

4.5

NOM

SN74153
MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM
5

-800

Low-!evel output current, 10L

16

Operating free-air temperature, T A

-55

125

0

MAX

UNIT

5.25

V

-800

p.A

16

rnA

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

Vi L

Lo;,v-Ievel input voltage

VIK

Input clamp voltage

I VOH

SN54153

TEST CONDITIONSt

MIN

TYP:j:

MAX

MIN

2

High-"!eve! ct!tput voltage

Vee- MIN,

11- -12mA

Vee- MIN,

VIH -2V,

v- IH--?V

VIL = 0_8 V,

10L = 16mA

')

..

SN74153
UNiT
TYp:j: MAX
V

2
0.8

0.8

V

-1.5

-1.5

V

., A

')

..

., A

v

VOL

Low-Ieveloutput'voltage

VIL = 0.8 V,
V,..,..-MIN
.,," - ..... _,

II

Input current at maximum input voltage

Vee = MAX, VI=5.5V

IIH

High-level input current

Vee - MAX, VI = 2.4 V

40

40

p.A

I'lL

Low-level input current

Vee - MAX, VI- 0.4 V

-1.6

-1.6

rnA

Short-circuit output currentli
lOS
leel Supply current, output low

-57

rnA

Vee - MAX, See Note 2

60

rnA

10H = -800p.A

-

0.2

0.4

-20

Vee = MAX

0.2

1

-55
36

0.4
1

-18

52

36

V
rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V. T A = 25° C.
§Not more than one output should be shorted at a time.
NOTE 2: ICCl is measured with the outputs open and all inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETERlI
tPLH

FROM

TO

(INPUT)

(OUTPUT)

Data

Y

TEST CONDITIONS

MIN

TYP

MAX UNIT
18

ns

15

23

ns

22

ns

22

34
34

12

tpHL

Data

Y

tpLH

Select

Y

eL = 30pF,

tpHL

Select

Y

See Note 3

tpLH

Strobe

Y

19

30

ns

tpHL

Strobe

Y

15

23

ns

RL=400n,

•

ns

11 tp lH == propagation delay time, low-to-high-Ievel output
tpHl == propagation delay time, high-to-Iow-Ievel output
NOTE 3: load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. T.FXAS 75222

7-167

TYPES SN54L153. SN14L153
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN54L153
MIN
Supply voltage, VCC

4.5

NOM

MIN

5.5

4.75

5

High-level output current, 10H

SN74l153

MAX

NOM
5

-400

low-level output current, 10l

MAX
5.25

V

-400

/.IA

8

rnA

70

°c

8

Operating free-air temperature, T A

-55

125

UNIT

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

Vil

low-level input voltage

SN54'L153

TEST CONDITIONSt

MIN

SN74l153

TYP+ MAX

2

MIN

TYP+ MAX

2

V

0.8

VIK

Input clamp voltage

VOH

High-level output voltage

Vee= MIN,

11=-12mA

Vec- MIN,

VIH - 2V,

VOL

low-level output voltage

II

Input current at maximum input voltage

Vec= MAX, VI" 5.5V

-1.5

Vil = 0.8 V,

10H = -4oo/.lA

VCC= MIN,

VIH = 2V,

Vil = 0.8 V,

10l =8 rnA

2.4

3.4

2.4

0.2

0.4

UNIT

0.8

V

-1.5

V

3.4
0.2

V
0.4

1

1

V
rnA

IIH

High-level input current

VCC" MAX, VI = 2.4 V

20

20

/.IA

III

Low-level input current

Vec = MAX, VI = 0.4 V

-0.8

-0.8

rnA

lOS

Short-circuit output currentS

Vee - MAX

-30

rnA

30

rnA

'CCl Supply current, output low

-10

Vec=MAX, See Note 2

-28
18

-9

26

18

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

•

+AII typical values are at VCC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICCL is measured with the outputs open and all inputs grounded.

switching characteristics, Vee

= 5 V, TA = 25°e

FROM

TO

iNPUT

OUTPUT

tPlH

Data

Y

24

36

tpHL

Data

Y

30

46

ns

tPlH

Select

V

Cl = 30 pF,

44

68

n5

tpHl

Select

Y

See Note 3

44

68

n5

tpLH

Strobe

38

60

n5

tpHL

Strobe

Y
y

30 •

46

n5

PARAMETER~

TEST CONDITIONS

Rl =4000,

TVP

MAX IUNIT

I

n5

~tpLH == propagation delay time, low·to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-168

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS153, SN74LS153
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
REVISED OCTOBER 1976

recommended operating conditions
SN54LS153
MIN
Supply voltage, Vee

4.5

SN74LS153

NOM MAX
5

High-level output current, 10H
Low-level output current, 10L

MIN

5.5 4.75
-400

NOM MAX
5

5.25

V

-400
8

J.lA
mA

70

°e

4

Operating free-air temperature, T A

-55

125

0

UNIT

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER

SN54LS153
TYP; MAX

MIN

VIH High-level input voltage
VIL Low-level input voltage

2

VIK Input clamp voltage
VOH High-level output voltage
"-,_.

VOL

1

___ . 1 _ •• _1

SN74LS153
UNIT
MIN TYP; MAX

Vee = MIN,

11=-18mA

Vee = MiN,

VIH = 2V,

2.5

VIL = VIL max, 10H = -400 J.lA
Vee= MIN,

_ ...... _ ........ _1 .... ___

L..UVV'"ICVCI UULIJUL VU1Ld!::tt::

VIH = 2V,

I nput current at

V
0.8

V

-1.5

-1.5

V

3.4
0.25

IIOL -4 mA

VIL = VIL max

2
0.7

2.7
0.4

IIOL =8mA

V

3.4
0.25
0.35

0.4
0.5

v

Vee= MAX,

VI =7V

0.1

0.1

mA

IIH

High-level input current

Vee = MAX,

VI=2.7V

20

20

IlL

Low-level input current

Vee- MAX,

VI = 0.4 V

-0.4

-0,4

J.lA
mA

lOS Short-circuit output current §
leeL Supply current, output low

Vee-MAX

II

maximum input voltage

Vee-MAX,

-20.
See Note 2

6.2

-100 -20
10

6.2

-100 mA
10 mA

TYP

MAX UNIT

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
fAll typical Vah.ie5 are at Vee;:;; 5 V, T A;;;:;; 25°C.

§ Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second.
NOTE 2: ICCL is measured with the outputs open and all inputs grounded.

switching characteristics, Vee

=5 V, TA =25°e

PARAMETER~

FROM
(INPUT)

TO
(OUTPUT)

tpLH

Data

Y

tpHL

Data

Y

tpLH

Select

Y

tpHL

Select

Y

tPLH

Strobe
Strobe

Y
Y

tPHL

TEST CONDITIONS

eL=15pF,
RL = 2 kn,
See Note 4

MIN

10

15

ns

17

26

ns

19

29
38
24
32

ns

25
16
21

•

ns
ns
ns

~ tpLH

== propagation delay time, low-to·high-Ievel output
tpHL == propagation delay time, high·to-Iow-Ievel output
NOTE 4: Load circuits and voltage waveforms are shown on page 3-11.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

1-169

TYPES SN54S153, SN74S1_53
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN74S153

SN54S153
MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

Supply voltage, Vee

-1

High-level output current, 10H
Low-level output current, 10L

20

Operating free-air temperature, T A

-55

125

0

UNIT
V

-1

mA

20

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL
VIK

Low-level input voltage
Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

MIN

TYP+ MAX UNIT

2
Vee= MIN,

II =-18mA

Vee=MIN,

VIH=2V,

V

ISeries 545

2.5

3.4

VIL = 0.8 V,

10H = -1 mA Series 745

2.7

3.4

Vee = MIN,

VIH = 2 V,

VIL = 0.8 V,

10L = 20mA

I

0.8

V

-1.2

V
V

0.5

V

II

I nput current at maximum input voltage

Vee= MAX, VI = 5.5 V

1

IIH

High-level input current

Vee = MAX, VI = 2.7 V

50

/loA

IlL

Low-level input current

Vee = MAX, VI = 0.5V

-2

mA

lOS

Short-circuit output current§

Vee = MAX

-100

mA

70

mA

leeL Supply current, low-level output

-40

Vee = MAX, See Note 2

45

mA

T For conditions shown ~s MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC

=5

V, T A

= 25°C.

§Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second.

II

NOTE 2: ICCL is measured with the outputs open and all inputs grounded.

S'Nitching characteristics, Vee
PARAMETER.

=5 V, TA =25°C
FROM

TO

(INPUT)

(OUTPUT)

TEST CONDITIONS

MIN

TYP

MAX UNIT

tPLH

Data

Y

tPHL

Data

Y

tPLH

Select

y

eL=15pF,

tpHL

Select

y

See Note 3

tpLH

Strobe

y

10

15

ns

tpHL

Strobe

y

9

13.5

ns

RL = 280 0..,

6
6

9

ns

9

ns

11.5

18

ns

12

18

ns

~ tpLH ;;; propagation delay time, low-to-high-Ievel output
tpHL "" propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-170

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TTL
MSI

TYPES SN54154, SN54L154, SN74154, SN74L154
4-UN E-TO-16-UN E DECO DERS/ DEMU LTIPLEXERS
BULLETIN NO. DL-S 7211805, DECEMBER 1972

SN54154 ••• J OR W PACKAGE
SN54L154 .•• J PACKAGE
SN74154, SN74L154 ••• J OR N PACKAGE
(TOP VIEW)

•

'154 is Ideal for High-Performance
Memory Decoding

•

'L 154 is Designed for Power-Critical
Applications

•

Decodes 4 Binary-Coded Inputs into One of
16 Mutually Exclusive Outputs

•

Performs the Demultiplexing Function by
Distributing Data From One Input Line to
Any One of 16 Outputs

•

input Ciamping Diodes Simpiify System
Design

•

High Fan-Out, Low-Impedance, Totem-Pole
Outputs

•

Fully Compatible with Most TTL, DTL, and
MSI Circuits

INPUTS

':
3
4
5
6
7
8
9 ::,
III Y I I I I I I 1 1 1
ILl

'154
'L154

II
i

I

I I I I I I I I I I
JI
I I H2H3H4HsH6H7H8H9HJOHlIHI2~
\L.....-!

TYPE

OUTPUTS

'--I

'---..J

L......J

~

L-....J

'---..J

L..J

L.......J

L....J/G~Q

OUTPUTS

positive logic: see function table

TYPiCAL AVERAGE
PROPAGATION DELAY
3 LEVELS OF LOGIC
STROBE
23 ns
46 ns

L-...J

TYPICAL
POWER DISSIPATION

19 ns
38 ns

•

170mW
85mW

description
Each of these monolithic, 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one
of sixteen mutually exclusive outputs when both the strobe inputs, Gland G2, are low. The demultiplexing function is
performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the
other strobe input low. When either strobe input is high, all outputs are high. These demultiplexers are ideally suited for
implementing high-performance memory decoders. For ultra-high-speed systems, SN54S138/SN74S138 and SN54S139/
SN74S139 are recommended.
These circuits are fully compatible for use with most other TTL and DTL circuits. All inputs are buffered and input
clamping diodes are provided to minimize transmission-line effects and thereby simplify system design.
Series 54 and 54L devices are characterized for operation over the full military temperature range of -55°e to 125°e;
o
Series 74 and 74L devices are characterized for operation from oOe to 70 e.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-171

TYPES SN54154, SN54L154, SN74154, SN74L154
4-LlNE-TO-16-UNE DECODERS/DEMULTIPLEXERS
logic
FUNCTION TABLE
INPUTS

OUTPUTS

G1

G2

0

C

B

A

0

1

2

3

4

L

L

L

L

L

L

L

H

H

H

H

L

L

L

L

L

H

H

L

H

H

H

L

L

L

L

H

L

H

H

L

H

H

5
H
H
H

L

L

L

L

H

H

H

H

H

L

H

H

6
H
H
H
H

L

L

L

H

L

L

H

H

H

H

L

H

L

L

L

H

L

H

H

H

H

H

H

L

L

L

H

H

L

H

H

H

H

L

L

L

H

H

H

H

H

H

L

L

H

L

L

L

H

H

L

L

H

L

L

H

H

L

L

H

L

H

L

L

L

H

L

H

L

L

H

H

L

L

H

L

L

H

L

L

H

H

7

8

9

10

11

12

13

14

15

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

L

L

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

L

H

H
H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

·L

L

H

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H
H

H

H
H

H

H

H

H

L

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

~

high level, L

~

low level, X

~

irrelevant

functional block diagram and schematics of inputs and outputs

•

EQUIVALENT OF EACH INPUT

vcc:x-'NeuT

tj--

'154: R ~ 4 k.n NOM
'L154: R~8k.nNOM

INPUTS

TYPICAL OF ALL OUTPUTS

Vee

OUTPUT

'154: R
'L154: R

~
~

130.n NOM
260.n NOM

1272

7·172

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54154. SN74154
4-UNE-TO-16-UNE DECODERS/ DEMULTIPLEXERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . . .
I nput voltage. . . . . . .- . . . . . . . . . .
Operating free-air temperature range: SN54154 Circuits
SN74154 Circuits
Storage temperature range

7V

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54154
MIN
Supply voltage, Vee

4.5

NOM

SN74154
MAX

MIN

5.5

4.75

5

High·level output current, 10H

NOM
5

-800

Low-level output current, IOL

MAX
5.25

V

-800

J.LA

16

rnA

70

°c

16

Operating free-air temperature, T A

-55

125

UNIT

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PAnAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH
VOL

SN54154

TEST CONDiTiONS'

MIN

TYP

SN74154
MAX

High-level output voltage
Low-level output voltage

II = -12mA

Vec - MIN,

VIH - 2V,

VIL = 0.8 V,

10H = -800J.LA

Vee = MIN,

VIH = 2 V,

VIL = 0.8 V,

IOL=16mA

v! = 5.5 V

II

Input current at maximum input voltage

IIH

High-level input current

Vce = MAX, VI = 2.4 V

IlL

Low-level input current

Vee = MAX, Vi = 0.4 V

I Vee = MAX,

lOS

Short-circuit output current!i

Vee = MAX

Ice

Supply current

Vec = MAX, See Note 2

2.4

TYpt

MAX

2

2
Vee= MIN,

MIN

V

0.8

0.8

V

-1.5

-1.5

V

2.4

3.4
0.2

0.4

-20

V

3.4
0.2

0.4

V

11 mA

1 I

I

I

UNIT

40

40

J.LA

-1.6

-1.6

mA

-57

mA

56

mA

-55

34

-18

49

34

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
tAli typical values are at V CC = 5 V. T A = 25° C.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

Propagation delay time, low-to-high-Ievel output,
tpLH

from A, B, e, or D inputs through 3 levels of logic
Propagation delay time, high-to-Iow-Ievel output,

tpHL
tpLH

from A, B, e, or D inputs through 3 levels of logic

eL=15pF,

Propagation delay time. low-to-high-Ievel output,

See Note 3

RL = 400 .11,

from either strobe input
Propagation delay time, high-to-Iow·level output,

tpHL

from either strobe input

NOTE 3:

•

MIN

TYP

MAX UNIT

24

36

ns

22

33

ns

20

30

ns

18

27

ns

Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-173

TYPES SN54L154, SN74J154
4-UNE-TO-16-UNE DECODERS/ DEMULTIPLEXERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
........ .
Input voltage. . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54L 154 Circuits
SN74L 154 Circuits
Storage temperature range

7V
5.5V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54L 154
MIN
Supply voltage, Vee

4.5

NOM

SN74L154

MAX

MIN

5.5

4.75

5

NOM
5

-400

High-level output current, 10H
Low-level output current, IOL

8

Operating free-air temperature, T A

-55

125

0

UNIT

MAX
5.25

V

-400

j.LA

8

rnA

70

°e

electrical c.haracteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

•

VIH

High·level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

TEST CONDITIONSt

MIN

TYP:j: MAX UNIT

2

V
0.8

Vee = MIN,

II = -12mA

Vee- MIN,

VIH-2V,

VIL = 0.8 V,

10H = -4oo/LA

Vee - MIN,

VIH-2V,

VIL = 0.8 V,

10L = 8mA

Vee - MAX,

VI - 5.5 V

-1.5
2.4

3.4

V
V
V

VOL

Low·level output voltage

II

Input current at maximum input voltage

IIH

High·level input current

Vec = MAX,

VI = 2.4 V

20

/LA

IlL

Low·level input current

Vee ';"MAX,

VI = 0.4 V

-0.8

rnA

lOS

Short·circuit output current ~

Vec= MAX

ICC

Supply current

0.2

0.4
1

-9

-29

Vce = MAX,I SN54L 154

17

25

See Note 2

17

28

I SN74L 154

V
rnA

rnA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

:j: All typical values are at V CC = 5 V, T A = 25" C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.

switching characteristics, Vee = 5 V, TA = 25°e
TEST CONDITIONS

PARAMETER
Propagation delay time, low-to-high-Ievel output,
tpLH

tPLH

from A, B. e, or D inputs through 3 levels of logic

CL=15pF,

Propagation delay time, low·to-high·level output,

See Note 3

RL = 800

n,

MAX UNIT

48

72

ns

44

66

ns

40

60

ns

36

54

ns

from either strobe input
Propagation delay time, high-to-Iow-Ievel output,

tpHL

TYP

from A, B, C, or D inputs through 3 levels of logic
Propagation delay time, high·to-Iow-Ievel output,

tPHL

MIN

from either strobe input

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-174

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

OALLAS. TEXAS 75222

TYPES SN54155, SN54156, SN54LS155, SN54LS156,
SN74155, SN74156, SN74LS155, SN74LS156
DUAL 2-UNE-T0-4-UNE DECODERS/DEMULTIPLEXERS

TTL
MSI

BULLETIN NO. DL-S 7611850, MARCH 1974-REVISED OCTOBER 1976

•

Applications:
Dual 2-to-4-Line Decoder
DuaI1-to-4-Line Demultiplexer
3-to-S-Line Decoder
1-to-S-Line Demultiplexer

•

Individual Strobes Simplify Cascading for
Decoding or Demultiplexing Larger Words

•

Input Clamping Diodes Simplify System
Design

•

Choice of Outputs:
Totem Pole ('155, 'LS155)
Open-Collector ('156, 'LS156)
TYPES
'155, '156
'LS155

'LS156

TYPICAL AVERAGE
PROPAGATION DELAY
3 GATE LEVELS
21 ns
18 ns
32 ns

SN54155, SN54156, SN54LS155, SN54LS156 ••• J OR W PACKAGE
SN74155, SN74156, SN74LS155, SN74LS156 •.• J OR N PACKAGE
(TOP VIEW)

TYPICAL
POWER
DISSIFATION
125mW
31 mW
31 mVtJ

positive logic: see function table

descri ption
These monolithic transistor-transistor-Iogic (TTL) circuits feature dual 1-line·to-4·line demultiplexers with individual
strobes and common binary-address inputs in a single 16-pin package. When both,sections are enabled by the strobes,
the common binary-address inputs sequentially select and route associated input data to the appropriate output of each
section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input
1C is inverted at its outputs and data applied at 2C is not inverted through its outputs. The inverter following the 1C
data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping
diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.
Series 54 and 54LS are characterized for operation over the full military temperature range of -55°C to 125°C; Series
74 and 74LS are characterized for operation from O°C to 70°C.

schematics of inputs and outputs
'155, '156

'155

EaUIVALENT OF EACH INPUT

•

'156

TYPICAL OF ALL OUTPUTS

TYPICAL OF ALL OUTPUTS

VCC

Vcca--

4 kn NOM

INPUT

-OUTPUT

'LS155, 'LS156

'LS155

EaUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

'LS156

Vcc

V C C - -.......- 20 kn NOM

TYPICAL OF ALL OUTPUTS

_ _ ~OUTeUT

INPUT --e.-,lollf--+-_
l....-.......--OUTPUT

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-175

TYPES SN54155, SN54156, SN54LS155, SN54LS156,
SN74155, SN74156, SN74LS155, SN74LS156
DUAL 2-UNE-TO-4-UNE DECODERS/DEMULTIPLEXERS
functional block diagram and logic
FUNCTION TABLES
2-LlNE-T0-4-LlNE DECODER.
OR l-LiNE-TO-4-LINE DEMULTIPLEXER
OUTPUTS

INPUTS
SELECT

STROBE
lG - - - - - - ,

DATA
lC

STROBE

DATA

lYO

lYl

lC

lY3

A

lG

1Y2

B
X

X

H

X

H

H

H

H

L

L

L

H

L

H

H

H

L

t-i

L

H

H

L

H

H

H

L

L

H

H

H

L

H

H

H

L

H

H

H

H

L

X

X

X

L

H

H

H

H

2YO

2Yl

INPUTS
SELECT

SELECT
B

SELECT
A

STROBE

OUTPUTS
DATA

B

A

2G

2C

2Y2

2Y3

X

X

H

X

H

H

H

H

L

L

L

L

L

H

H

H

L

H

L

L

H

L

H

H

H

L

L

L

H

H

L

H

H

H

L

L

H

H

H

L

X

X

X

H

H

H

H

H

FUNCTION TABLE
3-LlNE-T0-8-LINE DECODER
OR l-LiNE-TO-8-LINE DEMULTIPLEXER
INPUTS

I

OUTPUTS
STROBE

SELECT

OR DATA

(01

(1\

(21

(31

(41

(51

(61

(71

ct

B

A

G+

X

X

X

H

H

H

H

H

H

H

H

H

L

L

L

L

L

H

H

H

H

H

H

H

L

L

H

L

H

L

H

H

H

H

H

H

L

H

L

L

H

H

L

H

H

H

H

H

L

H

H

L

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

2YO 2Yl 2Y2 2Y3 1YO lYl 1Y2 lY3

..

H

H

H

H
H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

,

= inputs 1 C and 2C connected together
= inputs 1 G and 2G connected together
H = high level, L = low level, X = irrelevant

tC

+G

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage: '155, '156
'LS155, 'LS156
Off-state output voltage: '155
'LS155
Operating free-air temperature range: SN54', SN54LS' Circuits
SN74', SN74LS' Circuits
Storage temperature range

7V
5_5V
7V
5.5V
7V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

NOTE 1: Voltage values are with respect to network ground terminal.

374

1-176

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54155, SN74155
DUAL 2-LlNE-TO-4-LlNE DECODERS/DEMULTIPLEXERS
recommended operating conditions
SN54155
MIN
Supply voltage, Vee

NOM

4.5

SN74155
MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM

-800

Low-level output current, 10L

MAX

5

V

-800

p.A

16

mA

70

°c

16

Operating free-air temperature, T A

-55

125

UNIT

5.25

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54155
PARAMETER·

SN74155

TEST CONDITIONSt
MIN

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

Vnl-l

TYP+

UNIT
MAX
V

2

High-level output voltage

VCc~

MIN,

II

VCC~

MIN,

VIH

~

2 V,

0.8 V,

10H

~

-800 p.A

MIN

V IH

~

2V

0.8 V,

10L

~

16mA

VIL
V CC

~

~

~

-12 mA
2.4

0.8

V

-1.5

V

3.4

V

VOL

Low-ievei output voitage

II

Input current at maximum input voltage

VCc~

MAX,

VI

~

5.5 V

1

IIH

High-level input current

VCC

~

MAX,

VI

~

2.4 V

40

p.A

IlL

Low-level input current

VCc~

MAX,

VI

~

0.4 V

-1.6

mA

lOS

Short-circuit output current§

VCC

~

MAX

VCC

~

MAX,

ICC

VIL

Supply current

~

See Note 2

0.2

SN54155

-20

SN74155

-18

0.4

-55
-57

SN54155

25

35

SN74155

25

40

V
mA

mA
mA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values ·are at V CC ~ 5 V, T A ~ 25°C.
§ Not more than one output should be shorted at ~ time.
NOTE 2:

ICC is measured with outputs open, A, B, and 1 C inputs at 4.5 V, and 2C, 1 G, and 2G inputs grounded.

switching characteristics, Vee
PARAMETERll

TO

LEVELS

(INPUT)

(OUTPUT)

OF LOGIC

Y

2

y

2

A, B, 2C,
tPLH

1G,or2G
A, B, 2C,

tpHL

= 5 V, TA = 25°e

FROM

1G,or2G

TEST CONDITIONS

CL~15pF,

RL~400n,

MIN

TYP

MAX UNIT

13

20

ns

18

27

ns

21

32

ns

21

32

ns

tPLH

AorB

y

tpHL

AorB

Y

3

tpLH

1C

y

3

16

24

ns

tpHL

1C

y

3

20

30

ns

3

See Note 3

•

ll tPLH == propagation delay time, low-to-high·level output
tpH L == propagation delay time, high·to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-117

TYPES SN54LS155, SN74LS155
DUAL 2-UNE-T0-4-UNE DECODERS/DEMULTIPLEXERS
REVISED OCTOBER 1976

recommended operating conditions
SN54LS155
MIN

NOM

4.5

Supply voltage, Vee

5

High-level output current, 10H

SN74LS155

MAX

MIN

5.5

4.75

NOM
5

-400

MAX

V

-400

IJA

8

mA

70

°e

4

Low-level output current, 10L
Operating free-air temperature, T A

-55

125

UNIT

5.25

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS155

TEST CONDITIONSt

PARAMETER

MIN

VIH High-level input voltage
VIL Low-level input voltage

MIN

2

VIK Input clamp voltage
VOH High-level output voltage

Vee= MIN,

II = -18mA

VCC- MIN,

VIH - 2V,

2.5

TYPt MAX

2

VCC- MIN,

VIH - 2V,

V
0.8

V

-1.5

-1.5

V

3.4

2.7

Input current at
maximum input voltage

IIOL -4mA

0.25

0.4

I'OL=8mA

VIL = VIL max
Vec=MAX,

VI =7V

UNIT

0.7

3.4

V

VIL = VIL max, 10H = -400 IJA

VOL Low-level output voltage
II

SN74LS155

TYPt MAX

0.25

0.4

0.35

0.5

0.1

0.1

V
mA

IIH

High-level input current

VCC= MAX,

VI = 2.7 V

20

20

IJA

IlL

Low-level input current

Vce = MAX,

VI = 0.4 V

-0.4

-0.4

mA

lOS Short-circuit output current S
ICC Supply current

VCC= MAX

-42

mA

Vee = MAX,

-6
See Note 2

-40
6.1

-5

10

6.1

10 mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at VCC = 5 V. T A = 25°C.
§ Not mOre than one output should be shorted at a time.
NOTE 2: ICC is measured with outputs open, A, B, and 1C inputs at 4.5 V, and 2C, 1G, and 2G inputs grounded .

•

switching characteristics, Vee

I
,

PARAMETER~

tpLH

I
,

II

FROM
(INPUT)
A, B,2C,
lG,or2G
A, B, 2C,

tpHL

=5 V, TA = 25° e

TO
(OUTPUT)

I,

LEVELS
OF LOGIC

Y

2

y

2

lG,or2G

I

SN54LS155
TEST CONDITIONS

MIN

CL = 15 pF,
RL =2 kn,

IUNITI

SN74LS155
TYP

MAX

10

15

ns

19

30

ns

17

26

ns

19

30

ns

tpLH

AorB

Y

3

tpHL

AorB

3

tpLH

le

Y
y

3

18

27

ns

tpHL

le

y

3

18

27

ns

See Note 4

~ tPLH "" propagation delay time, low-to-high-Ievel output
tpH L "" propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-178

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54156, SN74156
DUAL 2-LlNE-T0-4-LlNE DECODERS/DEMULTIPLEXERS
recommended operating conditions
SN54156
MIN
Supply voltage, Vee

NOM

4.5

SN74156
MAX

MIN

5.5

4.75

5

NOM
5

MAX
5.25

UNIT
V

High-level output voltage, VOH

5.5

5.5

V

Low-level output current, IOL

16

16

mA

70

°e

Operating free-air temperature, T A

-55

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54156
PARAMETER
ViH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

IIOH

TEST CONDITIONSt

SN74156
UNIT
MIN TYp:j: MAX

2

High-level output current

Vee= MIN,

II = -12 mA

Vee = MIN,

VIH = 2 V,

VII - 08 V

Vou = 5 5 V

Vee = MIN,

VIH =2 V,

.-

V

Low-level output voltage

VIL = 0.8 V,

IOL = 16mA

II

Input current at maximum input voltage

Vee = MAX,

VI = 5.5 V

V

-1.5

V

250

..

VOL

0.8

0.2

0.4
1

I !lA I
V
mA

IIH

High-level input current

Vee= MAX,

VI = 2.4 V

40

JJ.A

IlL

Low-level input current

Vee = MAX,

VI = 0.4 V

-1.6

mA

lee

Supply current

I SN54156
I SN74156

Vee = MAX,
See Note 2

25

35

25

40

mA

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with outputs open, A, S, and 1 C inputs at 4.5 V, and 2C, 1 G, and 2G inputs grounded.

switching characteristics, Vee
PARAMETER~

FROM

TO

LEVELS

!INPUT)

(OUTPUT)

OF LOGIC

Y

2

A, B,2e,
tPLH

=5 V, TA = 25°e

1G,or2G
A, B, 2e,

Y

2

tpLH

A or B

Y

3

tpHL

AorB

Y

3

tpLH

1e

Y

tpHL

1e

Y

tpHL

1G,or2G

TEST CONDITIONS

eL = 15 pF,

MIN

TYP

MAX

UNIT

15

23

ns

20

30

ns

23

34

ns

23

34

ns

3

18

27

ns

3

22

3~

ns

RL =400

n,

See Note 3

•

~ tp LH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-179

TYPES SN54LS156, SN74LS156
DUAL 2-UNE-T0-4-UNE DECODERS/DEMULTIPLEXERS
recommended operating conditions
SN54LSl56
Supply voltage, Vee

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

High-level output voltage, VOH
Low-level output current, IOL
Operating free-air temperature, T A

SI'J74LS156

MIN

-55

UNIT
V

5.5

5.5

4

8

rnA

70

°e

125

a

V

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

IOH

High-level output current

VOL

Low-level output voltage
I nput current at

II

SN54LSl56

TEST eONDITIONSt

PARAMETER

maximum input voltage

MIN

TYP:j:

SN74LSl56

MAX

2
Vee= MIN,

II = -18mA

Vee= MIN,

VIH=2V,

VIL = VIL max,

VOH = 5.5 V

Vee= MIN,

VIH=2V,

VIL = VIL max

IIOL = 4mA

MIN

VI =7V

MAX

0.25

UNIT
V

0.7

0.8

V

-1.5

-1.5

V

100

100

0.4

IIOL=8mA

Vee = MAX,

TYP:j:

2

0.25

0.4

0.35

0.5

0.1

0.1

p.A
V
rnA

IIH

High-level input current

Vee= MAX,

VI=2.7V

20

20

p.A

IlL

Low-level input current

Vee- MAX,

VI = 0.4 V

-0.4

-0.4

rnA

lee

Supply current

Vee= MAX,

See Note 2

10

rnA

6.1

10

6.1

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: ICC is measured with outputs open, A, S, and 1 C inputs at 4.5 V, and 2C, 1G, and 2G inputs grounded.

•

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~

FROM

TO

LEVELS

(INPUT)

(OUTPUT)

OF LOGie

A, B, 2e
tPLH

!

1G,o,2G
A, B,2e,

tpHL

Y

2

SN74LSl56
MIN

2

y

1G,or2G

SN54LSl56
TEST CONDITIONS

UNIT

TYP

MAX

25

40

ns

34

51

ns

31

46

ns

34

51

ns

3

32

48

ns

3

32

48

ns

tpLH

Aor B

Y

3

tpHL

AorB

3

tpLH

le

Y
y

tpHL

1e

y

eL = 15pF,
RL = 2 k.l1.,
See Note 4

~tpLH ;; propagation delay time, low-to-high-Ievel output
tpH L;; propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-180

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DAL.LAS, TEXAS 75222

TYPES SN54157, SN54L157, SN54LS157, SN54LS158, SN54S157, SN54S158,
SN74157. SN74L157, SN74LS157, SN74LS158. SN74S157. SN74S158
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
BULLETIN NO. DL-S 7611

features

•

Buffered Inputs and Outputs

•

Three Speed/Power Ranges Available

MARCH 1974-REVISED OCTOBER 1976

SN54157, SN54LS157, SN54S157 .•• J OR W PACKAGE
SN54L 157 ••. J PACKAGE
SN74157, SN74L157, SN74LS157, SN74S157 •.• J OR N PACKAGE
(TOP VIEW)
INPUTS

TYPICAL
TYPES

AVERAGE
PROPAGATION
TIME

'157

OUTPUT

VCC STROBE 4A

INPUTS OUTPUT

r--"-..

,.....-J'-..

TYPICAL

48

4Y

3A

38

3Y

POWER
DISSIPATION
150mW

9 ns

'L157

18 ns

75mW

'LS157

9 ns

49mW

'S157

5 ns

250mW

'LS158

7 ns

24mW

'S158

4 ns

195mW

3Y
1A

applications
•

Expand Any Data Input Point

SELECT 1A

18

1Y

2A

28

2Y

~~
INPUTS

•

Multiplex Dual Data Buses

•

Generate Four Functions of Two Variables
(One Variable Is Common)

•

Source Programmable Counters

OUTPUT

INPUTS

GND

OUTPUT

positive logic:
Low level at S selects A inputs
High level at S selects B inputs
SN54LS158, SN54S158 ... J OR W PACKAGE
SN74LS158, SN74S158 .•• J OR N PACKAGE
(TOPVIEW)

description
These monolithic data selectors/multiplexers contain
inverters and drivers to supply full on-chip data
selection to the four output gates. A separate strobe
input is provided. A 4-bit word is selected from one
of two sources and is routed to the four outputs. The
'157, 'L 157, 'LS157, and 'S157 present true data
whereas the 'LS 158 and'S 158 present inverted data
to minimize propagation delay time.

INPUTS

OUTPUT

INPUTS

OUTPUT

r--"-..

,.....-J'-..

•

FUNCTION TABLE
INPUTS
STROBE SELECT

'LS158

A

B

'LS157, '8157

'S158

H

X

X

X

L

H

L

L

L

X

L

H

L

L

H

X

H

L

L

H

X

L

L

H

X

H

H

L

level, X

= irrelevant

H

L
H

OUTPUTY
'157, 'L157,

= high

level, L

= low

SELECT~

INPUTS

1Y

~

OUTPUT

INPUTS

2Y

GND

OUTPUT

positive logic:
Low level at S selects A inputs
High level at S selects B inputs

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage: '157, 'L157, 'S158
'LS157, 'LS158
Operating free-air temperature range: SN54', SN54L', SN54LS', SN54S' Circuits
SN74', SN74L', SN74LS', SN74S' Circuits
Storage temperature range

7V
5.5V
7V
-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

NOTE1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-181

TYPES SN54157, SN54L157, SN74157, SN74L157,
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
functional block diagram
'157, 'L157

1A
1B
2A
2B
3A
3B
4A
4B
SELECT
STROBE

•

(15)

schematics of inputs and outputs

'157, 'L157

'157, 'L157

TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

-

.....--Vcc

Vcc---+--

INPUT
OUTPUT

'157: Req ~ 4 kn. NOM
'L157: Req~8kn.NOM

'157: R ~ 100 n. NOM
'L157: R~200nNOM

374

7·182

TEXAS

INSTRUMENTS

INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS157, SN54LS158, SN54S157, SN54S158,
SN74LS157, SN74LS158, SN74S157, SN74S158
QUADRUPLE 2-LlNE-TO-1-LlNE DATA SELECTORS/MULTIPLEXERS
functional block diagrams

schematics of inputs and outputs
'LS157, 'S157

'LS157, 'LS158

(2)

EQUIVALENT OF EACH INPUT

Vcc---.-..

1A
(3)
1B

I N PUT ~if-+----<~

(5)
2A

(6)

2B
S or G inputs: Req = 8.5

(11)

A or B inputs: Req = 17

3A

kn
kn

NOM
NOM

TYP!CAL OF ALL OUTPUTS
3B

4A

(10)

(14)

(13)
4B
STROBE G
SELECT S

(15)
(1)

'LS158, 'S158

'S157, 'S158

(2)
1A

1B

EQUIVALENT OF EACH INPUT

VCC3--

(3)

Req

(5)
2A

2B

INPUT.

II

--

(6)

(11)
3A

S or G inputs:

Req

A or B inputs:

Req

= 1.4 kn NOM
= 2.8 kn NOM

TYPICAL OF ALL OUTPUTS

(10)
3B

VCC /

(14)
4A
(13)

OUTPUT

4B
(15)
STROBE G

(1)

SELECT S

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-183

TYPES SN54157. SN74157
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN74157

SN54157
MIN
Supply voltage, Vee

NOM

4.5

MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM
5

-800

Low-level output current, 10L

UNIT
MAX
5.25

V

-800

!J.A

16

mA

70

°e

16
-55

Operating free-air temperature, T A

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54157

TEST CONOITIONSt

PARAMETER

MIN

TYP+

SN74157
MAX

2

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH
IlL

MIN

TYP+

MAX

UNIT
V

2
0.8
-1.5

0.8

V

-1.5

V

Vee = MIN,

11=-12mA

Vee = MIN,

VIH = 2 V,

VIL = 0.8 V.

10H = -800!J.A

Vee= MIN,

VIH = 2 V,

VIL = 0.8 V,

10L = 16 mA

Vee - MAX,

VI = 5.5 V

High-level input current

Vee = MAX,

VI=2.4V

40

40

!J.A

Low-level input current

Vee- MAX,

VI = 0.4 V

-1.6

-1.6

mA

lOS

Short-circuit output current~

Vee = MAX

lee

Supply current

Vee= MAX,

2.4

2.4

3.4
0.2

0.2

0.4

V

3.4
0.4
1

1

-20
See Note 2

-55
30

-18

48

30

V
mA

-55

mA

48

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time and duration of short-circuit should not exceed One second.
NOTE 2: ICC is measured with 4.5 V applied to all inputs and all outputs open.

•

switching characteristics, Vee::: 5 V, TA::: 25°e
PARAMETER~

tPLH

TEST CONDITIONS

FROM (INPUT)

tPHL
tPLH

CL=15pF,
Strobe

RL=400n,

tpHL
tPLH

MIN

TYP

9

Data

See Note 3
Select

tpHL

MAX UNIT
14

9

14

;3

20

14

21

15

23

18

27

ns
ns
ns

~ tpLH :; propagation delay time, low-to-high-Ievel output
tpHL:; propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-184

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

QUADRUPL~

TYPES SN54L157, SN74L157
2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

recommended operating conditions
SN54L157
MIN

NOM

4.5

Supply voltage, Vee

SN74L 157

MAX

MIN

NOM

5.5

4.75

5

5

High-level output current, 10H

-400

Low-level output current, 10L

8
-55

Operating free-air temperature, T A

125

0

UNIT

MAX
5.25

V

-400

p,A

8

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDlTlONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

Low-level output voltage

II

TYP+ MAX UNIT

2
Vee= MIN,

Vee;;;;

VOH High-level output voltage
VOL

MIN

~.4!!\!,

V

II = -12mA

ViH

=

2V,

VIL = 0.8 V,

10H = -400p,A

Vee= MIN,

VIH = 2V,

VIL = 0.8 V,

10L = 8mA

Input current at maximum input voltage

Vee = MAX,

VI=5.5V

2.4

0.8

V

-1.5

V
V

3.4
0.2

0.4
1

V
mA

IIH

High-level input current

Vee = MAX,

VI=2.4V

20

p,A

IlL

Low-level input current

Vee = MAX,

VI = 0.4 V

-0.8

mA

lOS

Short-circuit output current §

Vee = MAX

-28

mA

ICC

Supply current

Vee = MAX,

24

mA

-9
See Note 2

15

t For conditions shc\...... n as M! N or !\t1AX, use the appropriate value specified undar recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with 4.5 V applied to all inputs and all outputs open.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~
tpLH

FROM (INPUT)

TEST CONDITIONS

Data
eL = 15 pF,
Strobe

RL=800n,

tPHL
tPLH

See Note 3
Select

tpHL

~ tp LH
tpHL

TYP
18

tPHL
tPLH

MIN

MAX UNIT
28

18

28

26

40

28

42

30

46

36

54

ns

•

ns
ns

== propagation delay time, low-to-high·level output
== propagation delay time, high-to-Iow-Ievel output

NOTE 3:

Load circuit and voltage waveforms are-shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-185

TYPES SN54LS157, SN54LS158, SN74LS157, SN74LS158
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN54LS'

SN74LS'

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

-400

/J A

8

rnA

70

°e

Supply voltage, Vee

-400

High-level output current, 10H
Low-level output current, 10L

4
-55

Operating free-air temperature, T A

UNIT

MIN

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

at maximum

I nput current
input voltage
IIH
IlL

•

SN54LS'

TEST CONDITIONSt

PARAMETER

MIN

TVP:j:

SN74LS'
MAX

2
Vee= MIN,

11=-18mA

Vee= MIN,

VIH = 2 V,

VIL = MAX,

10H = -400/JA

Vee = MIN,

VIH = 2 V,

VIL = MAX

2.5

S or G input

input current

A or B input

Low-level

S or G input

input current

A or B input

Vee = MAX,
Vee= MAX,

lOS

Short-circuit output currend

Vee = MAX

ICC

Supply current

Vee= MAX,

V
V

-1.5

-1.5

V

2.7
0.4

V

3.4
0.25

0.4

0.35

0.5

0.2

0.2

0.1

0.1

40

40

V

rnA

VI = 7V

VI = 2.7 V
VI = 0.4 V

20

20

-0.8

-0.8

-0.4

-0.4

-100

-20
See Note 2

UNIT

0.8

Ii0L = 8mA

A or B input

High-level

MAX

0.7

3.4

S or G input
Vee= MAX,

TVP:j:

2

0.25

Ii0L = 4mA

MIN

-20

-100

l'LS157

9.7

16

9.7

16

I'LS158

4.8

8

4.8

8

/J A
rnA
rnA
rnA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25"e,
§ Not more than one output should be shorted at a time and duration of short-circuit should not exceed one second,
NOTE 2: ICC is measured with 4.5 V applied to all inputs and all outputs open.

switching characteristics, Vee
PARAMETER~
tPLH

= 5 V, T A = 25° C

FROM
(INPUT)

CL=15pF,
Strobe

tPHL
tPLH

'LS158

'LS157
MIN

Data

tpHL
tPLH

TEST CONDITIONS

RL=2kn,
See Note 4

Select

tPHL

TVP

MAX

MIN

TVP

MAX
12

9

14

7

9

14

7

12

13

20

11

17

14

21

12

18

15

23

13

20

18

27

16

24

UNIT
ns
ns
ns

~ tp LH "" propagation delay time, low-to-high-Ievel output
tpHL "" propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-186

TEXAS INSTRUMENTS
I~CORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54S157, SN54S158, SN74S157, SN74S158
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN54S157

SN74S1'57

SN54S158
MIN

NOM

4.5

Supply voltage, Vee

SN74S158

MAX

MIN

5.5

4.75

5

5

-1

High-level output current, 10H

20

Low-level output current, 10L
Operating free·air temperature, T A

-55

125

UNIT

MAX

NOM

0

5.25

V

-1

mA

20

mA

70

e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt

PARAMETER

SN54S157

SN54S158

SN74S157

SN74S158

UNIT

MIN TYP:j: MAX MIN TYP:j: MAX
VIH

High·level input voltage

VIL

Low-level input voltage

v~K

~np!..!t

2

damp vo!tage

VOH High·level output voltage
VOL Low-level output voltage
II

Input current at maximum input voltage

IIH

High·level input current

S or G input
A or B input
S or G input

Vee;::: MIN,

!i

= -18mA

V
0.8

V

_1')

1')

\I

Vee= MIN,

VIH = 2 V,

ISeries 54S

2.5

3.4

2.5

3.4

VIL = 0.8 V,

10H = -1 mA Series 74S

2.7

3.4

2.7

3.4

Vee= MIN,

VIH = 2 V,

VIL = 0.8 V,

10L = 20 mA

i

Vee = MAX, VI = 5.5 V
Vee= MAX, VI=2.7V

IlL

Low-level input current

lOS

Short·circuit output current§

Vee= MAX

ICC

Supply current

Vee= MAX, See Note 2

A or B input

2
0.8

Vee = MAX, VI=0.5V
-40

0.5

0.5

1

1

100

100

50

50

-4

-4

-2

-2

-100 -40
50

V

78

V
mA
!J.A
mA

-100

mA

61

mA

39

•

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
NOTE 2: lee is measured with 4.5 V applied to all inputs and outputs open.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~
tPLH
tPHL
tpLH

FROM

TEST CONDITIONS

!INPUT)

SN54S158

SN74S157

SN74S158

MIN

Data
eL = 15 pF,
RL = 280

Strobe

tPHL
tpLH

SN54S157

n,

See Note 3
Select

tPHL

TYP MAX MIN

UNIT

TYP MAX

5

7.5

4

4.5

6.5

4

6
6

8.5

12.5

6.5

11.5

7.5

12

7

12

9.5

15

8

12

9.5

15

8

12

ns
ns
ns

~tpLH == propagation delay time, low·to·high·level ~utPut
tpH L == propagation delay time, high·to·low·level output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

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•

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1-181

TTL
MSI

TYPES SN54159, SN74159
4-UNE-TO-16-UNE DECODERS/DEMULTIPLEXERS
WITH OPEN-COLLECTOR _OUTPUTS
BULLETIN NO. DL-S 7211800, DECEMBER 1972

•

Open-Collector Outputs for Interfacing with
MOS or Memory Decoders/Drivers

•

Decodes 4 Binary-Coded I nputs into One of
16 Mutually Exclusive Outputs

•

Performs the Demultiplexing Function by
Distributing Data from One Input Line to
Any One of 16 Outputs

•

Typical Average Propagation Delay Times:
24 ns through 3 Levels of Logic
19 ns from Strobe Input

•

Output Off-State Current is Less Than 50 p.A

•

Fully Compatible with Most TTL, DTL, and
MSI Circuits

SN54159 ••• J OR W PACKAGE
SN74159 ••• J OR N PACKAGE
(TOP VIEW)

~----------~vr-----------~

OUTPUTS

positive logic: see function table

description
Each of these monolithic, 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one
of sixteen mutually exclusive open-collector outputs when both the strobe inputs, G1 and G2, are low. The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe
inputs with the other strobe input low. When either strobe input is high, all outputs are high. These demultiplexers are
ideally suited for implementing MOS memory decoding or for interfacing with discrete memory address drivers. For
ultra-high-speed applications, the SN54S138/SNi4S138 or SN54S139/SN74S139 is recommended.

•

These circuits are fully compatible for use with most other TTL and DTL circuits. Input clamping diodes are provided
to minimize transmission-line effects and thereby simplify system design. Input buffers are used to lower the fan-in
requirement to only one normalized Series 54/74 load. A fan-out to 10 normalized Series 54/74 loads in the low-level
state is available from each of the sixteen outputs. Typical power dissipation is 170 mW .
The SN54159 is characterized for operation over the full military temperature range of -55°C to 125°C; the SN74159
is characterized for operation from O°C to 70°C.

function table
Same as SN54154, SN74154. See page 7-172.

functional block diagram
Same as SN54154, SN74154. See page 7-172.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage . . . . . . . .
Off-state output voltage
Operating free-air temperature range: SN54159 Circuits
SN74159 Circuits
Storage temperature range

7V
5.5 V
5.5V
-55°C to 125°C
aOc to 70°C
-65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminal

1076

7-188

TEXAS INSTRUMENTS
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•

DALLAS, TEXAS 75222

TYPES SN54159, SN74159
4-LlN E-TO-16-LlNE OECOOERS/OEMU LTIPLEXERS
WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN54159
MIN

NOM

4.5

Supply voltage, Vee

5

SN74159
MAX

MIN

5.5

4.75

NOM
5

16

Low-level output current, IOL
Operating free-air temperature, T A

125

55

0

MAX
5.25

UNIT
V

16

mA

70

°e

electrical characteristics over recommended operating free-air temperature range {unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

IOH

High-level output current

VOL

Low-level output voltage

!i

Input current 8t

IIH

High-level input current

IlL
lee

TEST CONDITIONSt

MIN

TYP:j:

MAX

2

UNIT
V

0.8
-1.5

V

Vec= MIN,

II = -12 mA

Vee = MIN,

VIH = 2 V,

V!L = 0.8 V,

VOH = 5.5V

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

IOL = 16mA

Vee == fv1AX,

VI- 5.5V

Vee = MAX,

VI = 2.4 V

40

J.LA

Low-level input current

Vee = MAX, VI = 0.4 V

-1.6

mA

Supply current

Vee = MAX,

56

mA

m~x:m:..:m

input vo~tage

V

50

J.LA

0.4

V
mA

All inputs grounded

34

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j: All typical values are at V CC = 5 V, T A = 25° C.

switching characteristics, Vee

= 5 V, TA = 25° C
TEST eONDITIONS

PARAMETER
Propagation delay time, low-to-high-Ievel output,

tPLH

from A, B, e, or D inputs through 3 levels of logic

I

Propagation delay time, high-to-Iow-Ievel output,
tpHL

from A, B, e, or D inputs through 3 levels of logic
Propagation delay time, low-to-high-Ievel output,

tPLH

eL=15pF,

RL=400n,

TYP

MAX

UNIT

23

36

oS

24

36

ns

15

25

ns

22

36

ns

See Note 2

from either strobe input
Propagation delay time, high-to-Iow-Ievel output,

tPHL

MIN

from either strobe input

NOTE 2: See load circuit and waveforms shown on page 3-10.

•

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

Vcc - - - -. .- - - -

INPUT

1076

TEXAS INCORPORATED
INSTRUMENTS
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CALLAS. TEXAS 75222

7-189

TTL
MSI

TYPES SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A,
SN54S162, SN54S163. SN74160 THRU SN74163,
SN74LS16-0A THR-U S-N74LS163A, SN74S162, SN74S163
SYNCHRONOUS
4-81T ~OUNTERS
BULLETIN NO. DL-5 7611385
ER 1976
'160, '161,'LS160A, 'LS161A ... SYNCHRONOUS COUNTERS WITH DIRECT CLEAR
'162, '163, 'LS162A, 'LS163A, 'S162, 'S163 ... FULLY SYNCHRONOUS COUNTERS

•

Internal Look-Ahead for Fast Counting

•

Carry Output for n-Bit Cascading

•

Synchronous Counting

•

Synchronously Programmable

•

Load Control Line

•

Diode-Clamped Inputs

TYPE

TYPICAL PROPAGATION
TIME, CLOCK TO
QOUTPUT

'160 thru '163
'LS160A thru 'LS163A
'5162 and 'S163

14 ns
14 ns
9 ns

SERIES 54', 54LS', 54S' .•. J OR W PACKAGE
SERIES 74', 74LS', 74S' ••• J OR N PACKAGE
(TOP VIEW)

TYPICAL
TYPICAL
MAXIMUM
POWER
CLOCK
DISSIPATION
FREQUENCY
32MHz
305mW
93mW
32MHz
70MHz
475mW

CLEAR CLOCK

ABC

D ENABLE GND

~p

DATA INPUTS

logic: see description

description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting
designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161 A, 'LS163A, and
'S163 are 4-bit binary counters". Synchronous operation is provided by having all flip-flops clocked simultaneously so
that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple
clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input
waveform.

•

These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after
the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160
thru '163 or 'S163A or 'S162 should be avoided when the clock is low if the enable inputs are high at or before the
transistion. This restriction is not applicable to the 'LS160A thru 'LS163A. The clear function for the '160, '161,
'LS160A, and 'LS161A is -asynchronous and a low level at the clear input~ets all four of the flip-flop outputs low
regardless of the levels of clock,load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162,
and'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock
pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily
as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is
connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear
input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before
the transition.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both
count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The
ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the
high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive
cascaded stages. High-to-Iow-Ievel transitions at the enable P or T inputs of the '160 thru '163 should occur only when
the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are
allowed regardless of the level of the clock input.
'LS160A toru 'LS163A, 'S162 and 'S163 feature a fully independent c!ock circuit. Changes at control inputs (enable
P or T, or clear) that will modify the operating mode have no effect until clocking occurs. The function of the
counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable
setup and hold times.
The 'LS160A thru 'LS163A are completely new designs. Compared to the original 'LS160 thru 'LS163, they feature
O-nanosecond minimum hold time and reduced input currents II H and II L.

1076

7-190

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

~
~

-n

I:

:::I

SN54160, SN74160 SYNCHRONOUS DECADE COUNTERS

~

SN54163, SN74163 SYNCHRONOUS BINARY COUNTERS

SN54162, SN74162 synchronous decade counters are similar;
however the clear is synchronous as shown for the SN54163,
SN74163 binary counters at right.

O·
:::I
~

SN54161, SN74f161 synchronous binary counters are similar;
however, the clear is asynchronous as shown for the SN54160,
SN74160 decade counters at left.

C"

g

"iii'
0-

ce

iil

LOAD

g

(91

LOAD (91
(141

D~TA

i

13)

(14)

DA

....

OA

DATA

~I

<
"'CI

(3)

A

m

en
en

£"oo-oi
[T]

. . ><
~

f,l

ID Z_

o

~8z
~~(J)
'0"""'1
g~~
E~c::

~03::
\:1

~
~
~

(13)

(131 DB

>

DB

2

-....=
U"I

(J)

DABTA

(41

I I

I r--"~I

-a::.

DATA (4J
B --

CLEAR I

CD

CLOCK

(2)

(12)

(121 Dc

:c

Dc

:::a

C
D~TA_15_1_.

I I I I

I

OATA~)

r--"~

en en

C

[T]

<2
2U"1

Z

-i

(J)

(11)

(11)

DO

DO

n-a::.
:cO:;
:::a W

0"

2 en
2

OATA~~

0
CLEAR

ENABLE
p

(71

T

(101
(15)

6::~e
OUTPUT

0

C

(1)

=========[~
"" ; :;.~:
~DUTPUT

.=

......

en:!::
-a::. CD

.=

!:!!! ....

.... :c

n:::a

OC

Cen

22
..........
m-a::.

';'-I

~

:::aen~

•

•

~

CD
N

-'...,

~

--t

~1~[­

~ o~-g

....

r::

::s

~

o·::s

8.. m
-i
~~ ~ ~ ~

SN54LS160A. SN74LS160A SYNCv~"''''f}US
DECADE COUNTERS

SN54LS163A. SN74LS163A SYNCHRONOUS
BINARY COUNTERS

g~ ~:

:(m

::J n::J

0

0

l>

SN54LS162A. SN74LS162A synchronous decade
counters are similar; however the clear is synchronous
as shown for the SN54LS163A. SN74LS163A binary
counters at right.

SN54LS161A. SN74LS161A synchronous binary
counters are similar; however, the clear is
asynchronous
as shown for the SN54LS160A.
SN74LS160A decade counters at left.

n
'fil
:> ::TC-o

Ql

§,: ;l g:

s ~_~Q;'
s0' ~.;t~,
!" a ~ 5'
C CD

~

~
CIl

!EO'"

0"

n

~

Co

Di·

ce
@

3

Q~Q ~
(ii' ~

:::!.
0

~

(J1

~

~

~,en

m=

c::a
ZC

~
men
enc.n

["l"I

><

m

e:e

,,-1
-<

n

:een
::a
een
ZZ
eel'
C~
enren

n~

8.~~
~~~

~

Z"'tJ

::::;>

5-;;; ~ ~
-0:2

en~

-<-<

::aZ

>

DATAA~

OATAA~

r,

z.......

~

.,.-

------~---~

r-

en

~8z
~~(J1

en
w

o~

~~

DATAB~f-+I-+I-+I---+---..J

DATABill~-+------l

~c:

en
Z

o~

......

~

["l"I

=
r-

Z

en

~
(J1

en

>

DATAC~

J I I I I I

r---

I L...J

DATAC~I-+I--III-+I-il~---+--

~

:e
::a
C

en
i2
......

DATAO~

OATAO~

--------(1-5Ig~mT

S
m

II

~

I t-t_----l
_______

---!

~

r-

en

1'5Ig~~~jT

en
w

>

'8
Cl'l

2'

JJ

~

iii
m

::::I

0

Q)

-0-

0

0"
0

0

'"c..iii"

JJ

::::I

SN54S163, SIN74S163 SYNCHRONOUS BINARY COUNTERS

SN54S162, SN74S162 SYNCHRONOUS DECADE COUNTERS

CLOCK

CLOCK

:::~"~

LOAD

CLEAR
DATAA

..

g
-I

~

~

I I'

'"I

~--------------

0"

~
Q)

m

<

0

-I
to

m

U;
-.J

Cl'l

a

----J
["l'1

-I

><

-<

>

(JJ

DATAB

\4,

I

"tJ

m
tn
en

III~

aIII -z _

~8Z
~~Cf)
.0'"""1
g~iC
~~C

~03:
~

~

;;l

~

2

U'I

~

DATAC

(51

tn
en

II

N

tT'J

tn-

'"""I

Zz
n U'I

------COUNT---__I-·- - - I N H I B I T - - - -

SYNC PRESET

ASYNCCLEAR
CLEAR

1076

7-194

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54161, SN54163, SN54LS161A, SN54LS163A, SN54S163,
SN74161, SN74163, SN74LS161A, SN74LS163A, SN74S163
SYNCHRONOUS 4-81T COUNTERS
'161, 'LS161A, '163, 'lS163A, 'S163 BINARY COUNTERS
typical clear, preset, count, and inhibit sequences
Illustrated below is the following sequence:
1. Clear outputs to zero ('161 and 'LS161A are asynchronous; '163, 'LS163A, and 'S163 are synchronous)
2. Preset to binary twelve
3. Count to thirteen, fourteen fifteen, zero, one, and two
4. Inhibit

CLEAR~

LJ

LOAD

,--

A
B

DATA
INPUTS

C

I

----~------~,

--

,--

----~------~I __
...J,...---i-------.,' -

'--

1,...--:-------."

D

L

---.J

-

__

CLOCK

•

ENABLE P
I

I

ENABLE T

I

I
OA - - - , --,

-

-

---!

-,----.;----.j

-,-,,_---.;_ _ _ _

OB _ _ _,

~

OUTPUTS

OD=-' ;~
I
I
I

RIPPLE-CARRY
OUTPUT

I

I

I
I

::

:12

I

I

.---,

I
SYNC PRESET
CLEAR

13

14

I

I~

15

0

_ _ _......:-_ _ _ _ _ _ _ _ __
2

..I·---COUNT---"'I~'- - - I N H I B I T - - -

ASYNC
CLEAR

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-195

TYPES SN54160 THRU SN54163. SN74160 THRU SN74163
SYNCHRONOUS 4-81T COUNTERS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

VCC--------~--------

INPUT

Clock:
Enable T:
Clear, Enable P:
A, B, C, D:

Req = 2.8 H2 NOM
Req = 2 kn NOM
Req = 4 kn NOM
Req = 6 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

•

Supply voltage, VCC (see Note 1)
Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54' Circuits
SN14' Circuits
Storage temperature range
NOTES:

1V
5.5 V
5.5V
-55°C to 125°C
O°C to 10°C
-65°C to 150°C

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple·emitter transistor. For these circuits, this rating applies between the count
enable inputs P and T.

recommended operating conditions
SN54160, SN54161

SN74160, SN74161 i

SN54162, SN54163

SN74162, SN74163i UNIT

I
Supply voltage, VCC

MIN

NOM

4.5

5

MAX
5.5

High-level output current, IOH

-800

Low-level output current, IOL

16

Clock frequency, fclock

0

25

MIN
4.75

NOM
5

MAX
5.25

V

-800 I J.lA
16

0

25

I

rnA
MHz

Width of clock pulse, tw(clock)

25

25

ns

Width of clear pulse, tw(clearl

20

20

ns

20

20

Enable P

20

20

Load

25

25

Clearo

20

20

Data inputs A, B, C, D
Setup time, tsu isee Figures 1 and 2)

Hold time at any input, th

0

Operating free-air temperature, T A

~his applies

.-

-55
...

ns

0
125

0

I

!

I

ns
70

°c

only for '162 and '163, which have synchronous clear inputs .

1076

7-196

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54160 THRU SN54163, SN74160 THRU SN74163
SYNCHRONOUS 4-811 COUNTERS

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONSt

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH
III
lOS

SN74160, SN74161

SN54162, SN54163

SN74162, SN74163 UNIT

MIN

MIN

TYP:j:

MAX

2

High-!eve!

Clock or enable T

input current

Other inputs

Low-level

Clock or enable T

input 'current

SN54160, SN54161

Other inputs

Short-circuit output current §

Vee= MIN,

II =-12mA

Vee = MIN,

VIH = 2 V,

VIL = 0_8 V,

10H = -800J.l.A

Vee = MIN,

VIH =2 V,

VIL=0.8V,

IOL=16mA

MAX

OB

V

-1-5

-1-5

V

3.4
0_2

V

0_8

2.4

3A
0.2

0.4

Vec = MAX, VI = 5.5 V

1

VCC = MAX, VI = 2.4 V

80 I
40

-57

0.4

V
rnA

80
40

J.l.A
I

-3.2

-1-6

-20

V

1

-3.2

Vee:= MAX, V; = 0.4 V

-1-6

-18

!

rnA

-57

rnA

VCC = MAX, See Note 3

59

85

59

94

rnA

VCC = MAX, See Note 4

63

91

63

101

rnA

Vee = MAX

ICCH Supply current, all outputs high
ICCL Supply current, all outputs low

2A

TYP:j:

2

~For conditions shown as MIN or MAX, use t~e appropriate value specified under recommended operating conditions.

+AII typical values are at VCC = 5 V, T A = 25 C.
§Not more than one output should be shorted at a time.
NOTES: 3. ICCH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open.
4. iCCL is measured with the clock ;'nput high, then again with the clock input low, with alt' other inputs low and all outputs open.

switching characteristics, Vee
PARAMETER~

=S V, TA = 2Soe

FROM

TO

(INPUT)

(OUTPUT)

TEST CONDITIONS

f max

MIN
25

tpLH

Ripple

Clock

carry

tpHL
tPLH

Clock

Any

tpHL

(load input highl

Q

tpLH

Clock

Any

tpHL

(load input lowl

Q

tPLH

Enable T

tPHL
tpHL

Clear

CL = 15 pF,
RL = 400

n,

TYP

MAX

32

UNIT
ns

23

35

23

35

13

20

15

23

See Figures 1 and 2

17

25

and Notes 5 and 6

19

29

Ripple

11

16

carry

11

16

AnyQ

26

38

ns
ns

•

ns
ns
ns

~fmax == Maximum clock frequency

tpLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
NOTES: 5. Load circuit is shown on page 3-10_
6. Propagation delay for clearing is measured from the clear input for the '160 and '161 or from the clock input transition for the
'162 and '163.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-197

TYPES SN54LS160A, THRU SN54LS163A, SN74LS160A, THRU SN74LS163A,
SYNCHRONOUS 4-811 COUNTERS

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

- - - - - -....VCC

-----11..----

I NPUT -

Vcc

120 n NOM

...-41"-4~"--

L...-----4.-- OUTPUT

Data:
Enable T, Load:
Clock, Enable P:
Clear ('LS160A. 'LS161A):
Clear ('LS162A. 'LS163A):

Req = 2.5 kn NOM
Req = 10 kn NOM
Req = 20 kn NOM
Req = 20 kn NOM
Req = 10 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Supply voltage, VCC (see Note 7)
.. - . . - . .
Input voltage . . . . . . . . . . - . . - . .
Operating free-air tempEirature range: SN54LS' Circuits
SN74LS' Circuits
Storage temperature range

•

NOTE 7: Voltage values are with respect to network ground terminal.

recommended operating

~nditions
SN54LS'

i
Supply voltage, VCC

NOM

MAX

4.5

5

5.5

MIN

4.75

-400
4

High-level output current, IOH
low-level output current, IOl
Clock frequency, fclock
Width of clock pulse, tw(clock)

0
25

Width of clear pulse, tw(clearl

20

25
20

Data inputs A, B, C, D

20

20

Enable P or T
load

20
20

Clear O

20

20
20
20

Setup time, tsu (see Figures 1 and 2)

Hold time at any input, th

0
-55

Operating free-air temperature, T A

o This applies only for

25

125

0

0
0

NOM

5

:

MAX

5.25
-400

/lA

8

mA

25

V

MHz
ns
ns

ns

ns

70

"c

'LS162 and 'LS1 63, which have synchronous clear inputs.

1076

TENTATIVE DATA

7-198

SN74LS'

MIN

This page provides tentative information on a
new product. Texas Instruments reserves the
right to change specifications for this product
in any manner without notice.

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DA.LLAS. TEXAS 75222

TYPES SN54LS160A THRU SN54LS163A, SN74LS160A THRU SN74LS163A
SYNCHRONOUS 4-81T COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

SN54LS'

TEST eONDITIONst

PARAMETER

MIN

TYP+

SN74LS'
MAX

MIN

2

VOH High-level output voltage

Vee= MIN,

II =-18mA

Vec= MIN,

VIH=2V,

2.5

VIL = VIL max, 10H = -400 p,A
VCC= MIN,

VOL Low-level output voltage

II

at maximum
input voltage

IIH

V

-1.5

-1.5

V

2.7
0.4

V

3.4
0.25

0.4

0.35

0.5

V

VIH = 2 V,

Data or enable P

0.1

0.1

Load, clock, or enable T

0.2

0.2

0.1

0.1

0.2

0.2

Clear ('LS160A, 'LS161A)

VI = 7V

VCC= MAX,

Clear ('LS 162A, 'LS 163A)
Data or enable P

20

20

High-level

Load, clock, or enable T

40

40

inpui Curreni

Cit:ar\ 'LS i oGA, 'LSi oi Ai

VI = 2.7V

VCC = MAX,

20

I

Clear('LS162A, 'LS163A)

40

Data or enable P
IlL

V
0.8

VIL=VILmax IIOL=8mA
Input current

UNIT

MAX

0.7

3.4
0.25

[IOL=4mA

TYP:j:

2

Low-level

Load, clock, or enable T

input current

Clear ('LS160A, 'LS161A)

VI = 0.4 V

VCC= MAX,

Clear('LS162A, 'LS163A)

20
40

I

-0.4

-0.4

-0.8

-0.8

-0.4

-0.4

-0.8

-0.8

-100

I

I
rnA

mA

VCC= MAX,

See Note 3

18

31

18

31

mA

ICCL Supply current, all outputs low

VCC- MAX,

See Note 4

19

32

19

32

rnA

-20

-100

!J.A

lOS Short-circuit output current§
ICCH Supply current, all outputs high

VCC= MAX

-20

rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time, and duration of the short-eircuit should not exceed one second.
NOTES: 3. ICCH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open.
4. ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open .

switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER~

FROM

TO

(INPUT)

(OUTPUT)

TEST CONDITIONS

f max
tPLH

Clock

tPHL

Ripple
carry

tPLH

Clock

Any

tpHL

(load input high)

Q

tPLH

Clock

Any

tPHL

(load input low)

Q

tPLH

Enable T

tPHL
tpHL

Clear

CL=15pF,
RL = 2 kn,
See Figures
1 and 2 and
Notes 8 and 9

Ripple
carry

MIN

TYP

25

32

UNIT
MHz

20

35

18

35

1:3

24

18

27

13

24

18

27

9

14

- - 209

AnyQ

MAX

14'
28

•

ns
ns
ns
ns
ns

~ f max == Maximum clock frequency
tpLH == propagation delay time, low-to-high-Ievel output.
tpHL == propagation delay time, high-to-Iow-Ievel output.
NOTES: 8, Load circuit is shown on page 3-11.
9. Propagation delay for clearing is measured from the clear input for the 'LS160A and 'LS161 A or from the clock transition
for the 'LS162A and 'LS163A.

1076

TENTATIVE DATA
This page provides tentative information on a
new product, Texas Instruments reserves the
right to change specifications for this product
in any manner without notice.

TEXAS

INSTRUMENTS

INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-199

TYPES SN54S162, SN54S163, SN74S162, SN74S163
SYNCHRONOUS 4-81T COUNTERS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS
-------------~-----VCC

50

VCc-------~e_-------

n

NOM

INPUT
OUTPUT

Enable P or T inputs:
Other inputs:

Req
Req

= 1.4
= 2.8

kn NOM
kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54S162, SN54S163 (see Note 10)
SN74S162,SN74S163
Storage temperature range

•

7V

5.5 V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

recommended operating conditions
SN74S162, SN74S163

SN54S162, SN54S163

Supply voltage, VCC

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

-1

High-level output current, IOH

20

Low·level output current, IOL
0

Clock frequency, fclock'

40

i

i

--

10

Width of clear pulse, twklearl

10

10

4

4

Enable P or T

12

12

Load
Clear

14

I

Setup time, tsu (see Figure 4)

I

14

Load inactive-state

12

Clear inactive-state

12

Enable P or T

Release time, trelease (see Figure 4)

i

ns
ns

i

i

ns

12
12
4

3

Load

0

0

Clear

0

0

-55

i MHz
1

14

3

Operating free-air temperature, T A .(see Note 10)
NOTES:

40

14

4

Data inputs A, B, C, 0
Hold time, th (see Figure 4)

I

mA

20 I mA
0

10

i

V

-1

Width of clock pulse, tw(clock) (high or low)
Dauinput~A,B,C,D

UNIT

125

0

ns
ns

"c

70

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.

2. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between

th~e

count

enable inputs P and T.
10, An SN54S162 or SN54S163 in the W package operating at free·air temperatures above 91°C requires a heat sink that provides a
thermal resistance from case to free-air, ReCA, of not more than 26°C/W.

1076

7-200

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN54S162, SN54S163, SN14S162, SN14S163
SYNCHRONOUS 4-811 COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S162
PARAMETER

TEST CONDITIONSt
MIN

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

TYP:j:

SN74S163

MAX

2

VOH High-level output voltage
VOL Low-level output voltage

,

SN74S162

SN54S163

II

Input current at maximum input voltage

IIH

High-level input current

Enable T

Othei inputs
Enable T

Vee; MIN,

II; -18mA

Vee; MIN,

VIH;2V,

VIL; 0.8 V,

10H; -1 mA

Vec; MIN,

VIH; 2 V,

VIL; 0.8 V,

10L; 20mA

Vee; MAX,

VI; 5.5 V

Vee; MAX,

VI; 2.7 V

Vee; MAX,

VI; 0.5 V

IlL

Low-level input current

lOS
I,..,..
VV'

Short-circuit output current§

Vee; MAX

Iv N:lrrAnt
Su pp,
--.. - .. -

V,..,..; MAX

Other inputs

2.5

MIN

TYP:j:

UNIT

MAX

2

V

0.8

0.8

V

-1.2

-1.2

V

3.4

2.7

3.4

0.5

0.5

1

1

100

100

50

50

-4

-4

-2
-40

-100

95

V

-2
-40

V
mA
}lA
mA

-100

mA

95

160

rnA

MIN

TYP

MAX

40

70

160

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC = 5 V, T A = 25"C.

§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

switching characteristics, Vee

= 5 V, T A = 25° C

PARAMETER~

FROM

TO

(INPUT)

(OUTPUT)

TEST CONDITIONS

f max

tPLH

Hippie

Clock

tpHL
tPLH

eL;15pF,

carry

RL; 280

Any Q

Clock

tpHL
tPLH

Ripple

Enable T

tPHL

n,

MHz

14

25

17

25

8

15

See Figures 1, 3, and 4 and

10

15

Note 5

10

15

10

15

carry

~fmax ==maximum clock frequency
tpLH ==propagation delay time, low·to·high·level output
tpH L == propagation delay time, high·to·low·level output

UNIT

ns
ns
ns

•

NOTE 5: Load circuit is shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-201

TYPES SN54160 THRU SN54163, SN54LS160A,THRU SN54LS163A
SN54S162, SN54S163, SN74160 THRU SN74163,
,
SN74LS160A THRU SN74LS163A, SN74S162, SN74S163
SYNCHRONOUS 4-81T COUNTERS
PARAMETER MEASUREMENT INFORMATION

...I

I-tW(CIOCk)

I

I

I

3V

CLOCK
INPUT

- - - I...-.....I-tPLH
I (measure at t n+1)

I

1
I

OUTPUT

°A ___

Vref

';"",J

I

,(measure at t n+2)

~5""'----.J/
I

~tPHL

I

I

(measure at t n +4)

~tPLH
I (measure at t n +2)

I
I

I

~,s. . __:........l~ref___ _

OUTPUT

Os

I....---..L- tpHL
I

: (measure at t n+8)

II

.1
I

(measure at t n +10
or t n+16)

-

-

-

VOL

-

-

VOL

___ _
-

I

1ooI1.f--_.....I-tPHL
I

VOH

tPLH
(measure at t n +4)

ou~uT-----------";"'--I.~s\-_ _.;...~lv~f

•

- ov

I.---..t- tpH L

Ajl---+-I-tPLH
(measure at t n +8)

I
I

'~"S____--JlV~f ______

'\.. v(::e Note S)

OUTPUT

°D

~tPLH

I
I
I

RIPPLE
CARRY_ _ _ _ _..J
OUTPUT
,

Vref

VOH
VOL

~11~--t_I-tPHL
I
I (measure at t n+10
I or t n+16) (See Note S)

\S-\os---------------------------- ~:~

VOLTAGE WAVEFORMS

NOTES:

n;

A. The input pulses are supplied by a generator having the following characteristics: PRR .;; 1 MHz, duty cycle';; 50%, Zout ,., 50
for '160 thru '163, tr .;; 10 ns, tf .;; 10 ns; for' LS160A thru', LS163A,t r .;; 15 ns, tf .;; 6 ns; and for 'S162, 'S163, tr " 2.5 ns,
tf .;; 2.5 ns. Vary PRR to measure f max .
B. Outputs QD and carry are tested at t n +10 for'160,'162,'LS160A.'LS162A,and'S162, and at t n +16 for '161, '163,'LS161/\
'LS163A, and 'S163, where tn is the bit time when all outputs are low.
C. For '160'thru '163, 'S162, and 'S163, Vref = 1.5 V; for 'LS160A thru 'LS163A, Vref = 1.3 V.

FIGURE 1-SWITCHING TIMES

1076

7·202

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54160 THRU_ SN54163, SN54LS16QA THRU SN54LS163A,
SN74160 THRU SN74163, SN74LS160A TH-RU SN74LS163A
SYNCHRONOUS 4-81T COUNTERS

f

PARAMETER MEASUREMENT INFORMATION

------------------------

CLOCK INPUT
'160, 'LS160A
'161, 'LS161A

\
1 V ref

~-------------------------------

1

,-tW(CIOCk)-I

-----------------

1

CLEAR
INPUT

~v: ______ j _____________ __
__________________________
4-tw (clear).,.J

I
1 1_

~I

-.I,

t su

~~re~ ____________ __

LOAD
INPUT

I I...-

tsu - :

~:---------------

DATA INPUTS
A, B, C, and D

-------~;-t-PH-L--~--------------~

~~i:~~VTPVTS [ ~~v_re_f
~
QB and QC OUTPUTS
'160, 'LS160A

tpHL

__________

~

3V

, Vref

_I tPLH

________

j..::-

OV
3V

~i~J~~v-r~-f--_--_--_---

VOH

--_--==
__

_--_---_-_
__
-__- -__

VOL
(measure at tn+2 or t n +4)

: ,~~~~~~~--~-----~~~

\vm

OV
3V

v v

~ tPLH

I...-

OV
3V

~~:----

ENABLE P or
ENABLE T

VOH

VOL
3V

OV
tPLH+---t
RIPPLE
CARRY
OUTPUT

.:--t--tPHL

~-\~~--

______~--------_--------....:.--------------------_----_T

Vref

1

1- tsu

-I

-l tPH L I+I

QOUTPUTS
'163, 'LS163A
QA and QD OUTPUTS
'162, 'LS162A

QB and QC OUTPUTS
'162, 'LS162A

NOTES:

I

~

1

~~~:~:f[\~_____Jf,vref \vm tl~': ___

VOH

3V

h

_ _ _ _ _ _ _ _ _

•

OV

'-- , tPLH : - _ - - - - - - - - - - - - - - - - - - - - - - - - - - -

1

i

nIT

' \V

lvref

-l tpHL :-'--------~::-.~.I -

t-;L~(;;a;;;re-;;t~+~r~+~

-

-

-

-

VOL

I~:-_-_-_-_-_ ~ ~ ===~ :::

\vnn

VOLTAGE WAVEFORMS
A. The input pulses are supplied by generators having the foik,~ing ch~racteristics: P R R .;; 1 M Hz, duty cycle';; 50%, Zout '" 50

n;

for '160 thru '163, tr';; 10 ns, tf';; 10 ns; and for 'LS160A thru 'LS163A, tr .;; 15 ns, tf .;; 6 ns.
B. Enable P and enable T setup times are meas~"'ed at tn+O'
C. For '160thru '163, Vref = 1.5 V; for 'LS160A thru 'LS163A, Vref = 1.3 V.

FIGURE 2-SWITCHING TIMES
1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-203

TYPES SN54S162, SN54S163, SN74S162, SN74S163
SYNCHRONOUS 4-81T COUNTERS
PARAMETER MEASUREMENT INFORMATION

ENABLE T
INPUT

-i

~~:---------::

SV

I

I

~

I--

CARRY

________________

OUTPUT

tpHL--I

t PLH ----:

I
I

\~---VOH

J~SV

\".---",;,,-VOL

VOL TAGE WAVEFORMS
NOTES:

A. The input pulse is supplied by a generator having the following characteristics: tr';;; 2.5 ns, tf';;; 2.5 ns, PRR ,;;; 1 MHz, duty
cycle';;; 50%, Zout '" 50

n.

B. tpLH and tpHL from enable T input to carry output assume that the counter is at the maximum count (QA and QD high for
'S162, all Q outputs high for 'S163).

FIGURE 3-PROPAGATION DELAY TIMES FROM ENABLE T INPUT TO CARRY OUTPUT

t-- tw(clock)

3V

I
I

CLOCK
INPUT

.....JI

'--_ _....J:

r--

I

INPUT

t---

-.!

(active state)

t.-

~,-1'_5V

CLEAR

•

tsu

'--_ _
th

_____

I--

tw(clear)

~

tsu

~

I

(inactive state)

..J,t~v____ ~ ________ ~ ___ ::

----+I

:-I

tsu

~

(active state)

t-----:-

th ..I

tsu

--:------l

(inactIve state)

I

I

I

l_....Jt~"- _____ J____

LOAD
INPUT

~

\'-.5_v___
t--

tsu

--I

I

-J~.SV
Dr'

_______

\SV

t---

I

tsu

1:

ENABLEPor
ENABLE T
____________________________________-J•

J ____ 3V

i

DATAINPUTS_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

A, B, C, and

ov

I
I

...
I.----I~th
I

3V

'.SV

ov

--1

~trelease

~5~--_3V
_._______ 0 V

VOLTAGE WAVEFORMS
NOTE A: The input pulses are supplied by generators having the following characteristics: tr';; 2.5 ns, tf';; 2.5 ns, PRR ,;;; 1 MHz, duty
cycle';;; 50%, Zout '" 50

n.

FIGURE 4-PULSE WIDTHS, SETUP TIMES, HOLD TIMES, AND RELEASE TIME

1076

7·204

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

o

-..I
Ol

N-BIT SYNCHRONOUS COUNTERS
This application demonstrates how the look-ahead carry circuit can be used to implement a hi£lh-speed n-bit counter. The '160, '162,
'LS160A, 'LS162A, or 'S162 will count in BCD and the '161, '163, 'LS161A, 'LS163A or 'S163 will count in binary. Virtually any count
mode (modulo-N, Nl-to-N2, Nl-to-maximum) can be used with this fast look-ahead circuit.

.....
-<

."

m

U)
U)
iii!

•
~
rr1

INPUTS

~

><

INPUTS

INPUTS

~

~

~en
0o-i
~;o
~c::

03:

n
»
»
""C

..... !!!2

-<

""'C

LD A
H = COUNT
L = DISABLE

H

B

C

D

LD A

B

C

D

LD A

RIPPLE
CARRY
OUTPUT

rr1

C

D

LD A

EN P

EN P

= COUNT

B

RIPPLE
CARRY
OUTPUT

EN T

B

C

EN F'

RIPPLE
CARRY
OUTPUT

EN T

""'C

r-

RIPPLE
CARRY
OUTPUT

Z

o-i

en

CK

CK

CK
CLR 0A 0B 0c 0D

CLR 0A 0B 0c 0D

CLEAR

'---v-----'

~

OUTPUTS

OUTPUTS

CLOCK

[

r-

D

__ CLR QA Qs Qc QD

J__ ~ 1

n
»
-I
eZ
0

~
_

~U)

::eenU'l
:::aN~

c ..

en

U)w
U)2,..
2 U'I'U)

U)~t;2

-U'I

-I

>

z_

~

en

~

INPUTS

r-~

(J)

8z

U'I

U)
2
.....

CLR 0A 0B 0c 0D

:::aW,"A':J> V" en

C!
2 ..

2c:::::t
.....
_
~­

C
c:2.....

'---v-----'
OUTPUTS

U) ..... en:c
~c:::::t
~,U)
:::a
I , _ I ..... C
caen:c
=i N::::a U)
n" C2
U) U'I
C2U)~
C ..... 2r2~""'U)

~!!!~'m

:::aen enw

.....

N

CI

U"I

U)W;~'l>

•

TTL TYPES SN54164. SN54L164. SN54LS164. SN74164. SN74L164. SN74LS164
MSI
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
BULLETIN NO. DL-S 7611835, MARCH 1974-REVISED OCTOBER 1976

•

Gated (Enable/Disable) Serial Inputs

•

Fully Buffered Clock and Serial Inputs

•

Asynchronous Clear

SN54164, SN54LS164 .•. J OR W PACKAGE
SN54L 164, SN74L 164 .•• J, N, OR T PACKAGE
SN74164, SN74LS164 .•• J OR N PACKAGE
(TOP VIEW)
OUTPUTS

TYPICAL
TYPE

VCC

TYPICAL

MAXIMUM
CLOCK FREQUENCY

~CLEARCLOCK

POWER DISSIPATION

'164

36MHz

21 mW per bit

'L164

18MHz

11 mW per bit

'LS164

36MHz

10 mW per bit

CLEAR
CK

A

description
These 8-bit shift registers feature gated serial. inputs
and an asynchronous clear. The gated serial inputs (A
and B) permit complete control over incoming data as
a low at either (or both) input(s) inhibits entry of the
new data and resets the first flip-flop to the low level
at the next clock pulse. A high-level input enables the
positive logic: see function table
other input which will then determine the state of the
first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the
setup requirements will be entered. Clocking occurs on the low-to-high-Ievel transition of the clock input. All inputs are
diode-clamped to minimize transmission-line effects.
Series 54, 54 L, and 54LS devices are characterized for operation over the full military temperature range of -55°C to
125°C; Series 74, 74L, and 74LS devices are characterized for operation from O°C to 70°C.
FUNCTION TABLE
INPUTS
CLEAR CLOCK

•

L

X

OUTPUTS
A

B

QA

X

X

L

QAO
H

H

L

X

X

H

t

H

H

H

t
t

H

QB '"
L

QH
L

QBO

QHO

QAn

DGn

L

X

L

QAn

DGn

X

L

L

QAn

DGn

H
X

= high

level (steady state). L

= low level

(steady state)

= irrelevant (any input, including transitions)
t = transition from low to high level.
0AO. 0BO. 0HO = the level of 0A, 0B. or 0H,

respectively, before the indicated
steady-state input conditions were established.
level of OA or 0G before the most-recent t transition of the
clock; indicates a one-bit shift.

= the

0An. 0Gn

schematics of inputs and outputs
'164, 'L 164
EQUIVALENT OF EACH INPUT

'LS164

TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

--+---Vcc

- - - -.......--VCC

Req.

Req
VCC1
3-INPUT

VCC-----

TYPICAL OF ALL OUTPUTS

I NPUT-..,....-+-_

--

"----<~-OUTPUT

OUTPUT

'164: Req = 4 kn NOM
'L 164: Req = 8 kn NOM
'164: R = 200 n NOM
'L 164: R = 400 n NOM

Clear. clock: 17 kn NOM
Serial In: 25 kn NOM

1076

7-206

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

TYPES SN54164, SN54L164, SN54LS164, SN74164, SN74L164, SN74LS164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
REVISED OCTOBER 1976

typical clear, shift, and clear sequences

~

CLEAR'l..J
I
I

SERIAL {
INPUTS

I

~~------------~:------------

A

__':------...J
I

I

CLOCK

~~------~--------~~----~---------

QA===i
---,

roc===-,-l

~,~-------------~

QB _

I

-------1

J

QD===.~J~

---,
---,

OUTPUTS ~

QE ___

H

~L...........:.._____________

___________________

I n _ _ _ _ _ _ _ _ _ __
L...-....I

~

______________________________

---,~I~
---~l

_ _~_ _ _- - - - -

~I

I

I~

QG __
Q

________________________~

~I

I

~'~

QF ____

r--l

~

I

I

~

_ _----------------------~

I

___________________________~r_l~'_________
I

CLEAR

CLEAR

•

functional block diagram

CLEAR~----~ ~--~----~~-----.------~------.-----~~-----e------~
CLOCK~____~

~~--~--~--+---e---~~~-4--~--~--~--+-~~~--,

(3)

OUTPUT

°A

15)

110)

111)

(12)

(13)

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

Os

Dc

°D

°E

OF

DG

(4)

(61

°H

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-207

TYPES SN54164, SN74164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
.... .
Input voltage . . . . . . . . . . . . .
Operating free-air temperature range: SN54164
SN74164
Storage temperature range

7V
5.5V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74164

SN54164
MIN
4.5

Supply voltage, VCC

NOM

MAX

MIN

NOM

5.5

4.75

5

5

MAX

-400

High·level output current, 10H

5.25

V

-400

JlA

8

mA

8

Low-level output current, 10L
0

Clock frequency, fclock

25

0

UNIT

25 MHz

Width of clock or clear input pulse, tw

20

20

ns

Data setup time, tsu (see Figure 1)

15

15

ns

5

5

Data hold time, th (see Figure 1)

-55

Operating free-air temperature, T A

125

ns
70

0

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High·level input voltage

VIL

Low·level input voltage

VIK

Input clamp voltage

TYP:f:

MAX

2

VOH High-level output voltage

•

SN74164

SN54164
MIN

VOL Low-level output voltage
II

Input current at maximum input voltage

VCC= MIN,

II = -12mA

VCC- MIN,

VIH=2V,

VIL = 0.8 V,

10H = -400JlA

VCC- MIN,

VIH - 2 V,

VIL = 0.8 V,

10L =8mA

2.4

MIN

TYP:f:

MAX

V

2
0.8

0.8

V

-1.5

-1.5

V

3.2

2.4

0.2

V

3.2
0.2

0.4

0.4
1

1

VCC - MAX, VI-5.5V,

UNIT

V
mA

IIH

High-level input current

VCC - MAX, VI = 2.4 V

40

40

JlA

IlL

Low-level input current

VCC - MAX, VI - 0.4 V

-1.6

-1.6

mA

lOS

Short-circuit output currentS

VCC = MAX

-21.5

mA

ICC

Supply current

VCC - MAX,
See Note 2

-10

I Vl{clock) = 0.4 V

IV I (clock) = 2.4 V

-21.5

-9
30

30
37

37

54

54

mA

t For conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than two outputs should be shorted at a time.
NOTE 2: lee is measured with outputs open, serial inp,uts grounded, and a momentary ground, then 4.5 V, applied to clear.

switching characteristics, Vee

= 5 V, TA = 25°e
TEST CONDITIONS

PARAMETER
f max Maximum clock frequency

CL = 15 pF

Propagation delay time, high-to-Iow-Ievel
tpHL

tPHL

TYP

25

36

CL= 15pF

MAX
36

28

42

8

11

21

CL = 50 pF

10

20

30

Propagation delay time, high-to-Iow-Ievel

CL= 15pF

10

21

32

Q outputs from the clock input

CL = 50 pF

10

25

37

Q outputs from clock input

RL=800n,
See Figure 1

CL = 50 pF

UNIT
MHz

24

CL=15pF

Q outputs from clear input

Propagation delay time, low-to-high-Ievel
tPLH

MIN

ns
ns
ns

1076

7-208

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54L164, SN74L164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54L 164
SN74L164
Storage temperature range

7V
5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74L164

SN54L164
MIN
4.5

Supply voltage, V CC

NOM

MAX

MIN

5.5

4.75

5

NOM

V

-200

ILA

4

rnA

4

Low-level output current, 10L
0

Clock frequency, fclock

12

UNIT

5.25

5

-200

Higi1-ievei output current, iOH

MAX

12 MHz

0

Width of clock or clear input pulse, tw

40

40

Data setup tim2, tsu {see Figure 1}

30

?n

iiS

10

ns

Data hold time, th (see Figure 1)

10
-55

Operating free-air temperature, T A

125

ns

70

0

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

V:K

lop!,!! clamp voltage

SN74L164

SN54L164
MIN

TYP:j:

MAX

2

VOH High-level output voltage
VOL Low-level output voltage

VCC- MIN,

Ii --12mA

VCC- MIN,

VIH=2V,

VIL = 0.8 V,

10H = -200 ILA,

VCC- MIN,

VIH = 2V,

VIL = 0.8 V,

10L =4 rnA

II

Input current at maximum input voltage

VCC = MAX, VI = 5.5 V

2.4

MIN

TYP:j:

MAX

2

V

0.8

0.8

V

-1.5

-1.5

V

3.2
0.2

UNIT

2.4
0.4

3.2
0.2

V
0.4
1

1

IIH

High-level input current

VCC- MAX, VI-2.4 V

20

20

ILA

IlL

Low-level input current

VCC= MAX, VI = 0.4 V

-0.8

-0.8

rnA

lOS

Short-circuit output current§

VCC= MAX

-20

rnA

ICC

Supply current

VCC- MAX, See Note 3

27

rnA

-5

-20
19

-4
19

27

•

V
rnA

tFor conditions shown at MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C
§Not more than two outputs should be shorted at a time.
NOTE 3: ICC is measured with outputs open, serial inputs grounded, the clock input at 2.4 V, and a momentary ground, then 4.5 V, applied to
clear.

switching characteristics, Vee = 5 V, T A = 25° C
TEST CONDITIONS

PARAMETER
f max Maximum clock frequency

CL = 15pF

Propagation delay time, high-to-Iow-Ievel
tpH L Q outputs fr~m clear input
Propagation delay time, low-to-high-Ievel
tPLH

Q outputs from clock input

MIN

TYP

12

18

CL=15pF
RL=800n,
See Figure 1

Propagation delay time, high-to-Iow-Ievel
tpHL Q outputs from the clock input

CL = 50 pF

MAX UNIT
MHz

48

72

56

84

34

54

CL = 15pF

8

CL - 50 pF

10

20

60

CL = 15 pF

10

42

64

CL = 50 pF

10

50

74

ns
ns
ns

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-209

TYPES SN54LS164, SN74LS164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS164
SN74LS164
Storag~ temperature range

7V
7V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74LS164

SN54LSl64

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

-400

p.A

S

mA

Supply voltage, VCC

-400

High-level output current, 10H

4

Low-level output current, 10L
0

Clock frequency, fclock

25

0

25 MHz

Width of clock or clear input pulse, tw

20

20

ns

Data setup time, tsu (see Figure 1)

15

15

ns

Data hold time, th (see Figure 1)

5

ns

5

-55

Operating free-air temperature, T A

125

70

0

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

•

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

MIN

TYP+

MAX

2

VOH

High-level output voltage

VOL

Low-level output voltage

VCC = MIN,

11=-lSmA

VCC- MIN,

VIH - 2 V,

VIL = VIL max,

10H = -400 p.A

VCC - MIN,

VIH = 2 V,

VCC = MAX,

maximum input voltage

2.5

I!H

High-level input current

Vee = MAX,

V!

Low-level input current

VCC - MAX,

VI- 0.4 V

lOS

Short-circuit output current §

VCC = MAX

V
V

-1.5

-1.5

V

3.5

2.7
0.4

3.5
0.4

0.35

0.5

ICC

Supply current

VCC= MAX,

0.1

16

See Note 3

V
mA

20, p.A

-0.4
-100

V

0.25

20,

V
-20

UNIT

O.S

0.1

IlL

MAX

2

VI = 7 V

= 2.7

TYP+

0.7

0.25

IIOL - 4mA

MIN

IIOL = SmA

VIL = VIL max
Input current at

II

SN74LS164

SN54LS164

TEST CONDITIONSt

PARAMETER

-20
16

27

-0.4

mA

-100

mA

27

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 3: ICC is measured with outputs open, serial inputs grounded, the clock input at 2.4 V, and a momentary ground, then 4.5 V applied

§ Not

to clear.

switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER

TEST CONDITIONS

f max

Maximum clock frequency

tpHL

Propagation delay time, high-to-Iow-Ievel Q outputs from clear input

CL=15pF,

tPLH

Propagation delay time, !ow-to-high-!evel Q outputs from clock input

See Figure 1

tpHL

Propagation delay time, high-to-Iow-Ievel Q outputs from clock input

RL=2k!1,

MIN

TYP

25

36

MAX

UNIT
MHz

24

36

ns

17

27

ns

21

32

ns

1076

7-210

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DAL.LAS. TEXAS 75222

TYPES SN54164, SN54L164, SN54LS164, SN74164, SN74L164, SN74LS164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
AANDB
PULSE
GENERATOR

OUTPUT

VCC

QA
QB

A
B
CLOCK
PULSE
GENERATOR

Dc
QD
QE
QF

CLOCK

DG
QH

CLEAR
PULSE
GENERATOR

TEST CIRCUIT

j..- tw(clear)

~

PULSE
mAR
GENERATOR

(PRR .;; 1 MHz)

V

I

ref

f

---I

V
ref

-------

----------oV
i.--lw(Clock)

I

CLOCK
PULSE
GENERATOR
(PRR.;; 1 MHz)

I

I
I

I
I
Vref

I

I

'--___"'·_1 ____ ov

I

~rth

--4 r- th

II
I

I I

---~II

SERIAL INPUTS
AAND BPULSE
GENERATOR
(PRR.;; MHz)

-.I

~I

Vref

'-___

1

--t
---eof

3V

I

•

.....,J~--_- 0 V

~tPHLI-­

tpLH

r--~i:Jf------""""'~ VOH
QA OUTPUT
(See Note D)

VOL

VOLTAGE WAVEFORMS
NOTES:

A. The pulse generators have the following characteristics: duty cycle';;; 50%, ZOtJt '" 50 n; for '164 and 'L164, tr';;; 10 ns,
tf .;;; 10 ns, and for' LS164, tr .;;; 15 ns, tf .;;; 6 ns.
B. CL includes probe and jig capacitance.
C. A"diodesare1N30640r1N916.
D. Q A output is illustrated. Relationship of serial input A and B data to other Q outputs is illustrated in the typical shift sequence.
E. Outputs are set to the high level prior to the measurement of tpH L from the clear input.
F. For '164 and 'L 164, Vref = 1.5 V; for 'LS164, Vref = 1.3 V.

FIGURE 1-SWITCHING TIMES

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE SOX 5012

•

DALLAS. TEXAS 75222

7-211

TYPES SN54165, SN54LS165, SN74165, SN74LS165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS

TTL
MSI

BULLETIN NO. DL-S

1375, OCTOBER 1976

SN54165, SN54LS165 .•. J OR W PACKAGE
SN74165, SN74LS165 ... J OR N PACKAGE
(TOP VIEW)

• Complementary Outputs
• Direct Overriding Load (Data) Inputs

CLOCK
Vcc INHIBIT

• Gated Clock Inputs

A ALLEL INPUTS

~

SERIALOUTPUT
INPUT
ClH

• Parallel-to-Serial Data Conversion
TYPICAL MAXIMUM

TYPICAL

CLOCK FREQUENCY

POWER DISSIPATION

'165

26 MHz

210mW

'LS165

35MHz

105mW

TYPE

description
The '165 and 'LS165 are 8-bit serial shift registers
that shift the data in the direction of QA toward
QH when clocked. Parallel-in access to each stage is
made available by eight individual direct data inputs
that are enabled by a low level at the shift/load
input. These registers also feature gated clock inputs
and complementary outputs from the eighth bit. All
inputs a re diode-clamped to minimize
transmission-line effects, thereby simplifying system
design.

positive logic: see description

Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit
function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the
shift/load input high enables the other clock input. The clock-inhibit input should be changed to the high revel only
while the clock input is high. Parallel loading is inhibited as long as the shift/load input is high. Data at the parallel
inputs are loaded directly iilto the register on a high-to-Iow transition of the shift/load input independently of the levels
of the clock, clock inhibit, or serial inputs.

II

FUNCTION TABLE
INPUTS
LOAD

INHIBIT

L

X

X

H

L

L

H

L

L
X

H

L

t
t

H

H

X

OUTPUT

I

GH

'

INTERNAL

I SHIFT! !CLOCK! CLOCK! SERIAL

PARALLEL

OUTPUTS

A ..• H

QA

QB

a ... h

a

b

X

X

QHO

X

GAO
H

QBO

H

QAn

QGn

X

L

QAn

QGn

X

GAO

QBO

QHO

X

h

See explanation of function tables on page 3-8.

schematic of inputs and output
'165

VCC

EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPl,ITS

VCC3-Req

INPUT

-}VCC
100 !l.
NOM

INPUT

-_

'Q

'LS165

EQUIVALENT OF EACH INPUT TYPICAL OF BOTH OUTPUTS

OUTPUT

Req

--

OUTPUT

Clock, clock inhibit: Req = 17 k!l. NOM

Shiftiload: Req = 3
Other inputs;

Req "" 6

kn
kn

Parallel inputs,
NOM
NOM

serial input: Req = 24 kS1 NOM
Shift/load: Req = 5.7 k!l. NOM

,J,

1076

7·212

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54165, SN54LS165, SN74165, SN74LS165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
________________________

~

~

INPUTS
A

________________________

~

~

functional block diagram

(9)

OUTPUT

(7)

OUTPUT

OH

C:IOCK

1151

INHIBIT

------L...-/

a..

typical shift, load, and inhibit sequences

SHIFT/LOAD

~

r -------.IT:l
A

I

L

~----+----------------------------------

:

c

-----K:l
I
~----~----------------------------------L

•

,I

E

----.If:l~----~----------------------------------I
I

L

I

G----.lf:l~

,

____~____________________________

H~~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _

I
OUTPUTO H

OUTPUTOH

Iabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, Vee (see Note 1)
Input voltage: SN54165, SN74165
SN54LS165, SN74LS165
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54165, SN54LS165
SN74165,SN74LS165
Storage temperature range
NOTES:

7V
5.5 V
. 7V

5.5 V
. -55°C to 125°e
aOe to 7aoe
. -65°e to 15aoe

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies tor the '165 to the shift/load inpu"[ ,n
conjunction with the clock-inhibit inputs.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-213

TYPES SN54165, SN74165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
recommended operating conditions
SN74165

SN54165
MIN

NOM

4.5

Supply voltage, VCC

MAX

MIN

5.5

4.75

5

NOM
5

-800

High-level output current, IOH

MAX

V

-800

!J.A

16

Low-level output current, IOL
0

Clock frequency, fclock

0

20

UNIT

5.25
16

mA

20

MHz

Width of clock input pulse, tw(clock)

25

25

Width of load input pulse, tw(load)

15

15

ns
ns

Clock-enable setup time, tsu (see Figure 1)

30

30

ns

Parallel input setup time, tsu (see Figure 1)

10

10

ns

Serial input setup time, tsu (see Figure 2)

20

20

ns

Shift setup time, tsu (see Figure 2)

45

45

ns

0

0

'ns

Hold time at any input, th

-55

Operating free-air temperature, T A

125

0

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

•

MIN

TYPj MAX

2

MIN

TYPt MAX

2

Low-level output voltage

II

Input current at maximum input voltage

IIH

High-level input current

Shift/load
Other inputs
Shift/load

VCC = MIN,

11=-12mA

VCC = MIN,

VIH - 2V,

VIL = 0.8 V,

10H = -800!J. A

VCC - MIN,

VIH - 2V,

VIL = 0.8 V,

10L = 16 mA

VCC - MAX,

VI- 5.5 V

VCC = MAX,

VI = 2.4 V

IlL

Low-level input current

lOS

Short-circuit output current ~

VCC = MAX

ICC

Supply current

VCC = MAX,

VCC = MAX,

Other inputs

0.8 I

-1.5
2.4

0.2

VI = 0.4 V
-20
See Note 3

-1.5
2.4

3.4

3.4

0.2

0.4

0.4

1

1

80

80

40

40
-3.2

-1.6

-1.6

-55

-18
42

63

V
V
V

-3.2

42

UNIT
V

0.8

VOH High-level output voltage
VOL

SN74165

SN54165

TEST CONDITIONSt

PARAMETER

V
mA
!J.A
mA

-55

mA

63

mA

NOTE 3: With the outputs open, clock inhibit and clock at 4.5 V, and a clock pulse applied to the shift/load input, ICC is measured first
with the parallel inputs at 4.5 V, then with the parallel inputs grounded.
t Fer conditions shewn as M!N or I\/IA X, use the appropnate value specified under recommended operating conditions.
+AJI typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.

switching characteristics, Vee
PARAMETER~

= 5 V, T A = 25°e

FROM
(INPUT)

I

TO
(OUTPUT)

i

TEST CONDITIONS

f max

MIN

TYP

20

26

MAX! UNIT

21

31

tPHL

27

40

tPLH

16

24

21

31

tPLH

Load

Any

Clock

Any

CL=15pF,RL=400n,

tpHL
tpLH

See figures 1 thru 3
H

QH

tPHL
tPLH

H

OH

tPHL

I

MHz

11

17

24

36

18

27

18

27

ns
ns

ns

ns

~fmax == maximum cioc"k frequency
tpLH "" propagation delay time, low-to-high-Ievel output
tp H L "" propagation delay time, h igh-to·low-Ievel output
1076

7-214

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS165, SN14LS165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
recommended operating conditions
SN74LS165

SN54LS165
MIN

NOM

4.5

Supply voltage, VCC

MAX

MIN

5.5

4.75

5

NOM
5

-400

High-level output current, 10H
Low-level output current, 10L

MAX

V

-400

J.LA

8

mA

25

MHz

4
0

Clock frequency, fclock

0

25

UNIT

5.25

Width of clock input pulse, tw(clock)

25

25

ns

Width of load input pulse, tw(ioad)

15

15

ns

Clock-enable setup time, tsu .(see Figure 1 )

30

30

ns

Parallel input setup time, tsu (see Figure 1)

10

10

ns

Serial input setup time, tsu (see Figure 2)

20

20

ns

Shift setup time, tsu (see Figure 2)

45

45

ns

0

0

Hold time at any input, th

125

-55

Operating free-air temperature, T A

ns

0

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

I

I

PARAMETER

I

TEST CONDITIONSt

V!H

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

SN74LS165

MAX MIN

TYP+

VCC: MIN,

II :-18 mA

VCC: MIN,

VIH: 2 V,

VIL : VI Lrnax,

10H :-400J.LA

VIH: 2 V,

Low-level output voltage

I

Input current at

Shift/load

maximum input voltage

Other inputs
Shift/load

Vee: MAX,
VCC: MAX,

IIH

Low-level input current

IlL

Low-level input current

lOS

Short-circuit output current§.

Vce= MAX

lee

Supply current

Vee: MAX,

Other inputs
Shift/load
Other inputs

VCC = MAX,

IOL:4mA

3.5

2.7

0.25

0.4

IOL:8 mA
VI =7 V
VI: 2.7 V
VI=O.4V
-20
See Note 3

0.8

V

-1.5

V

3.5

V

0.25

0.4

0.35

0.5

0.3

0.3

0.1

0.1

60

60

20

20

-1.2

-12

-0.4

-0.4

-100
21

II!,\!!T
V

-1.5
2.5

MAX

2
0.7

VIL : VILmax,1
II

TYPt

2

Vcc: MIN,
VOL

I

SN54LS165

MIN

-20
21

36

V

mA
J.LA
rnA

-100

rnA

36

rnA

NOTE 3: With the outputs open, clock inhibit and clock at 4.5 V, and a clock pulse applied to the shift/load input, lee is measured first
with the parallel inputs at 4.5 V, then with the parallel inputs grounded.
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

•

+AII typical values are at Vee = 5 V, T A: 25°C.

§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, Vee
PARAMETER~

= 5 V, T A = 25°e
FROM

TO

(INPUT)

(OUTPUT)

TEST CONDITIONS

f max

tPLH

Load

MIN

TYP

25

35
22

Any

MAX UNIT
MHz
35

tPHL

22

35

tPLH

27

40
40

Clock

Any

eL = 15 pF, RL : 2 kn,

tPHL
tPLH

See figures 1 thru 3
H

QH

tPHL
tPLH

H

OH

tPHL

28
14

25

21

30

21

30

16

25

ns

ns

ns

ns

~fmax == maximum clock frequency
tp LH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-215

II

.....

~

en

-a.-t

--------~

CLOCK INHIBIT
INPUT

:I>-C

=-a
:l>m

CLOCK
INPUT

SHIFT/
LOAD

I

OUTPUT
QH

[TI

><

"HL~

iJtH

:

- 1-

tPLH~

;l>

(J)

z_

~\1

OUTPUT

8z

GlH

~(J)

NOTES:

~;o

-I -

1
_ _ _ _ _..:.I_ _ _-.-J

1

1

I

0 V

r-U'I

"I - - - --

3 V

aen

I '--------'-I- -- -

I

V~

-

-

1

I

1

1

1

0

I

"LH~VOH
:

tPLH-I.....t

\Vref

r

Vref

/4-+l--;-p::-- VOL

1

~V

---VOH

lVref

A. The remaining six data inputs and the serial input are low.

OL

C. The input pulse generators have tho following characteristics; PRR';; 1 MHz, duty cycle';; 50% Zout "" 50 fl.; for "165, tr';; 10 ns, tf';; 10 ns;

03::

for 'LS165, tr';; 15 ns, tf';; 6 ns.
D. For '165, Vref

[TI

=

1.5 V; for 'LS165, Vref

=

~-----------------------.----------------------------

-

-

-.----

----

TEST
POINT

0~~~RO~;:-iJT

S

»
-i

o

•

III'

. . . . ..

\'----,
att n +7'
B. The input pulse generators have the following characteristics: PRR .;; 1 MHz, duty cycle';; 50%,
Zout '" 50 fl.; for '165, tr';; 10 ns, tf';; 10 ns; for 'LS165, tr';; 15 ns, tf';; 6 ns.
1.5 V; for 'LS165, Vref

=

1.3 V.

FIGURE 2-VOLTAGE WAVEFORMS

e
0\

S

m
Z

:::0

VCC

NOTES:

=

C
:::0

o

RL

C. For '165, Vref

m
»
en

"T1

-OV

SERIAL
INPUT

CLOCK
INPUT

:::0

S

Z

3V

SHIFT/
LOAD

(J)

m
-i
m

-i

FIGURE l-VOL TAGE WAVEFORMS

1.3 V.

i

z
...;

»
"
»
S
:::0

m

B. Prior to test, high-level data is load'~d into H input.

~c:

men

=iz

3V

1

,Vref

co.?"

v

t----OV

:-r:'HL

T Vref

I I

•

-

---1----

~tPHL

tPLH--l.--.!

-

C)~
:1> _

I

W (CIOCk)"'1

-

r;-"Z

I

"LHrJt

\Vref

~Jvref

- - - - . T V ref

0"';

I

R,"HL

Vref

~tpHL

,.t

---+I

I

..,..-_ _ _ _..J

"'""'i

--

Vref

Vref
' - - _ _ _ _ _ _ _ _-.J, I

tsu

en
men

3V

rr-

NOTES:

A. CL includes probe and jig capacitance.
B. All diodes are IN3064.

FIGURE 3-LOAD CIRCUIT FOR
SWITCHING TESTS

Z

enU'l

_ r=~

~~
en

=U'I

m ..

G')en
-z
en
.....
-t~
m_
=en
en'U'I
en

z
.....
~

r-

en
en
U'I

TYPES SN54166, SN54LS166, SN74166, SN74LS166
8-BIT SHIFT REGISTERS

TTL
MSI

BULLETIN NO. DL·S 7611808, OCTOBER 1976

SN54166, SN54LS166 ... J OR W PACKAGE
SN74166, SN74LS166 ... J OR N PACKAGE
(TOP VIEW)

• Synchronous Load
• Direct Overriding Clear
• Parallel to Serial Conversion
TYPICAL MAXIMUM

TYPICAL

CLOCK FREQUENCY

POWER DISSIPATION

'166

35 MHz

360mW

'LS166

35 MHz

110mW

TYPE

Vee

PARALLEL
PARALLEL INPUTS
SHIFT/ INPUT OUTPUT ~
LOAD
H
QH
G
F
E
CLEAR

functional block diagram

SERiAL-A- --B- --e- [)ClOCK CLOCK
INPUT - - . - . - - INHIBIT
?ARALLEL iNPUTS

'"G"N5'

positive logic: see description

description
The '166 and 'LS166 8-bit shift registers are
compatible with most other TTL and DTL logic
families. All '166 and 'LS166 inputs are buffered to
iower the drive requirements to one Series 54/74 or
Series 54LS/74LS standard load, respectively. Input
clamping diodes minimize switching transients and
simplify system design.

~ . . . dynamic input activated by transition from a high level to a low level.

I

These parallel-in or serial-in, serial-out shift registers
have a complexity of 77 equivalent gates on a
monolithic chip. They feature gated clock inputs and
an overriding clear input. The parallel·in or serial-in
modes are established by the shift/load input. When
high, this input enables the serial data input and
couples the eight flip-flops for serial shifting with
each clock pulse. When low, the parallel (broadside)
data inputs are enabled and synchronous loading
occurs on the next clock pulse. During parallel
loading, serial data flow is inhibited. Clocking is
accomplished on the low·to-high-Ievel edge of the
clock pulse through a two-input positive NOR gate
permitting one input to be used as a clock-enable or
clock-inhibit function. Holding either of the clock
inputs high inhibits clocking; holding either low
enables the other clock input. This, of course, allows
the system clock to be free-running and the register
can be stopped on command with the other clock
input. The clock·inhibit input should be changed to
the high level only while the clock input is high. A
buffered, direct clear input overrides all other inputs,
including the clock, and sets all flip-flops to zero.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-217

TYPES SN54166, SN54LS166, SN14166, SN14LS166
8-BIT SHIFT REGISTERS
typical clear, shift, load, inhibit, and shift sequences
CLOCK
CLOCKINHIBIT~~__~________________________~____~~L~__________________________

I

I

I

CLEAR~I
SERIAL INPUT

I
I
~L-____________________~______~____~~__________________________

I

I

I
SHIFT/LOAD--~I--~------------------------~---.~r----------------------------------

,

A __~~________________________~__~~L______-7__________________________

,

L,

I

C __~~________________________~__~~L____~-7__________________________

PARALLEL
INPUTS

D__ ________________________ ______ ,________ _________________________
____~________________________~__~~L----~~-------------------------~~

~

~L~:

~

I

L,

G____~________________________~__~~L----~~-------------------------H __

~~

________________________

~~

___

I

OUTPUT QH

==:::'."_~________________________---'
CLEAR

1 - - - - - - - SE RIAL SH I FT ----------------1
LOAD

FUNCTION TABLE
INTERNAL

INPUTS

I

PARALLEL

OUTPUT

OUTPUTS

SHIFTI

CLOCK

LOAD

INHIBIT

L

X

X

X

X

X

L

L

L

H

X

L

L

X

X

QAO

H

L

L

t

X

a ... h

a

QBO
b

QHO
h

H

H

L

t

H

X

H

QAn

QGn

H

H

L

t

L

X

L

QAn,

QGn

H

X

H

X

X

CLEAR

CLOCK SERIAL

A ••• H

QA

QH

QB

See explanation of function tables on page 3-8.

schematics of inputs and outputs
'LS166

'166

EQUIVALENT OF EACH INPUT

OUTPUT

EQUIVALENT OF EACH INPUT

OUTPUT

Vee -----.--Req

Parallel and
serial inputs:

Req

Others: Req

= 24 kn NOM

= 17 kn

NOM

1076

7-218

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54166, SN74166
8-BIT SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
5.5 V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

Supply voltage, Vee (see Note 1)
.....
Input voltage . .. . . . . . . . . . . .
Operating free-air temperature range: SN54166
SN74166
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74166

SN54166
MIN
Supply voltage, V CC

NOM MAX

4.5

5

UNIT

MIN

NOM MAX

4.75

5.5

5

-800

High-level output current, 10H
Low-level output current, IOL

5.25

V

-soo

JLA

16

Clock frequency, fclock

0

Width of clock or clear pulse, tw (see Figure 1)
uala sewp lime, ISU \see t"lgure II.

25

0

mA

25

MHz

20

20

ns

30

30

ns

20

20

o

Hold time at any input, th (see Figure 1)

o

-55

Operating free-air temperature, T A

16

o

125

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

SN54166

TEST CONDITIONSt

PARAMETER

MIN

SN74166

TYP:j: MAX

MIN

2

VOH High-level output voltage

VCC= MIN,

II =-12mA

VCC- MIN,

VIH - 2V,

VIL = O.BV,

10H = -BOOjLA

VCC- MIN,

VIH - 2V,

VIL = 0.8 V,

10L = 16mA

2.4

TYP:j: MAX

UNIT

I

2

V

O.B

O.B

V

-1.5

-1.5

V

3.4

2.4

V

3.4

VOL

Low-level output voltage

II

Input current at maximum input voltage

VCC- MAX, VI- 5.5V

IIH

High-level input current

Vcc = MAX, VI = 2.4 V

40

40

JLA

IlL

Low-level input current

VCC= MAX, VI = 0.4 V

-1.6

-1.6

mA

lOS

Short-circuit output current Ii

VCC - MAX

-57

mA

ICC

Supply current

VCC = MAX, See Note 2

116

mA

0.2

0.4

0.2

0.4

1

-20

-57

72

1

-18

72

104

II

V
mA

t For conditions shown as MI N or MAX. use the appropriate value specified under recommended operating conditions.

:j:AII typical values are at Vec = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: With all outputs open, 4.5 V applied to the serial input, all other inputs except the clock grounded, ICC is measured after a momentary
ground, then 4.5 V, is applied to clock.

switching characteristics, Vee

= S V, T A = 2S"e

PARAMETER

TEST CONDITIONS

f max Maximum clock frequency

MIN

TYP

25

35

MAX UNIT
MHz

Propagation delay time, high-totPHL

low-level output from clear
Propagation delay time, high-to-

tpHL

low-level output from clock

CL=15pF,
See Figure 1

Propagation delay time, low-totPLH

~igh-Ievel

23

35

ns

20

30

ns

17

26

ns

RL = 400 fl,

output from clock

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-219

TYPES SNS4LS166,SN74LS166
8·BIT SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS166
SN74LS166
Storage temperature range

. . . . . 7V
. . . . . 7V
_55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS166
MIN

NOM

4.5

Supply voltage, Vee

5

SN74LS166
MIN

NOM

MAX

5.5

4.75

5

5.25

V

-400

/.LA

-400

High-level output current, 10H

4

Low-level output current, 10L
0

Clock frequency, fclock

UNIT

MAX

25

0

8

mA

25

MHz

Width of clock or clear pulse, tw (see Figure 1)

20

20

ns

Mode-control setup time, tsu

30

30

ns

Data setup time, tsu (see Figure 1)

20

20

ns

0

0

ns

Hold time at any input, 1h (see Figure 1)

-55

Operating free-air temperature, T A

125

0

°e

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

•

SN74LS166

MIN TYP+ MAX MIN TYP+ MAX
2

VOH High-level output voltage

Vee= MIN,

11=-18mA

Vee = MIN,

VIH = 2 V,

i

VIL = VIL max, 10H = -400 /.LA
Vee = MIN,

VOL Low-level output voltage
II

SN54LS166

TEST CONDlTlONSt

VIH=2V,

VIL = VIL max

Input current at maximum

Vee = MAX,

VI = 7V

High-level input current

Vee = MAX,

VI = 2.7 V

I;L

Lc....v-Ieve! input current

Vee

lOS

Short-circuit output current§

Vee= MAX

ICC

Supply current

Vee= MAX,

= MAX,

0.8

V

-1.5

-1.5

V

3.4
0.25

Vi 0.4 V

i
-20

See Note 2

V

0.7

0.25

0.4

0.35

0.5

V
V

0.1

0.1

20

20

/.LA

-0.4

-0.4

mA

-100

mA

38

mA

-100 -20
22

I

3.4

2.7
0.4

IIOL =8 mA

IIH

input voltage

2.5

IIOL =4 mA

UNIT

2

38

22

mA

I

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
fAil typical values are at Vee = 5 V. T A

= 25°e.

§ Not more than one output should be shorted at a time, and duration of short-circuit should not exceed one second.
NOTE 2: With all outputs open. 4.5 V applied to the serial input and all other inputs except the clock grounded .. lee is measured a·fter a
momentary ground, then 4.5 V, is applied to clock.

switching characteristics, Vee = 5 V, TA = 25° C
TEST CONDITIONS

PARAMETER
f max

Maximum clock frequency

MIN

TYP

25

35

Propagation delay time, high-totPHL

low-level output from clear
Propagation delay time, high-to-

tPHL

eL=15pF,

RL

=2

UNIT
MHz

19

30

ns

8

23

35

ns

8

24

35

ns

kn,

See Figure 1

low-level output from clock
Propagation delay time, low-to-

tpLH

MAX

high-level output from clock

1076

7-220

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54166, SN54LS166, SN74166, SN74LS166
8-BIT SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
TEST
POINT
TEST TABLE FOR SYNCHRONOUS INPUTS

FROM

~~~~~T __~-M__~"~~__~-'
TEST

DATA INPUT

OUTPUT TESTED

SHIFT/LOAD

(See Note 0

(SEE NOTE F)

FOR TEST

/"f: CL = 15 pF

OV

H

....L(See Note C)

Serial

4.5

Input

QH att n +1

V

QH at tn+8

LOAD FOR OUTPUT UNDER TEST

~
Vref

CLEIl.R!NPUT

________ _

tw(clear) , , . . . . . - - - - - - - - - - - - - - - - - - - - - - 3 V

U~re~

tn+1

r--

tn

(See Note G)

I~--""

-

-

- - OV

tn+1

tn

~

-~---3V

CLOCK INPUT

~ -~th

Lov

9tsu~~3V

DATA
INPUT

Vref

(SEE TEST

~~ef_ _ _ _ ov

I

TABLE)

-.l

tpHL
(clear-Q)

I

--I tPHLj--

r-

(CLK-Q)
' \::ef- -

OUTPUT Q - - - - - " " " \ Vref

- - VOH

~----VOL

VOLTAGE WAVEFORMS
NOTE: A. All pulse generators have the following characteristics: Zout "" 50

n;

I

for '166, tr .;; 7 ns and tf';; 7 ns; for 'LS166, tr';; 15 ns and

tf';; 6 ns_
B. The clock pulse has the following characteristics: tw(clock) .;; 20 ns and PRR
characteristics: tw(clear) ;;, 20 ns and thold

=0

=

1 MHz. The clear pulse has the following

ns. When testing f max , vary the clock PRR.

C. CL includes probe and jig capacitance.
D. All diodes are 1 N3064 or 1 N916.
E. A clear pulse is applied prior to each test.
F. Propagation delay times (tpLH and tpH L) are measured at t n +1' Proper shifting of data is verified at t n +8 with a functional test.
G. tn

= bit time before clocking transition
= bit time after one clocking transition

tn+1

tn+8

= bit time

H. For '166 Vref

after eight clocking transitions

= 1.5 V;

for 'LS166 Vref

= 1.3

V.
FIGURE 1

7·221

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TTL
MSI

TYPES SN54161, SN14161
SYNCHRONOUS DECADE RATE MULTIPLIERS
BULLETIN NO DL-S 7211813, DECEMBER 1972

SN54167 ••• J OR W PACKAGE
SN74167 ••. J OR N PACKAGE
(TOP VIEW)

•

Perform Fixed-Rate or Variable-Rate
Frequency Division

•

For Applications in Arithmetic, Radar,
Digital-to-Analog (D/A), Analog-to-Digital
(AID), and other Conversion Operations

•

Typical Maximum Clock Frequency ... 32
Megahertz

RATE INPUTS

~

UNITY/ENABLE
CLEAR CASCADE INPUT STROBE

~

~

description
These monolithic, fully synchronous, programmable
counters utilize Series 54/74 TTL circuitry to achieve
32-megahertz
typical
maximum
operating
frequencies. These decade counters feature buffered
clock, clear, enable and set-to-nine inputs to control
the operation of the counter, and a strobe input to
enable or inhibit the rate input/decoding AND-ORINVERT gates. The outputs have additional gating
for cascading and transferring unity-count rates.

RATE INPUTS

OUTPUTS

positive logic: see description

NC-No internal connection

The counter is enabled when the clear, strobe set-to-nine, and enable inputs are low. With the counter enabled, the
output frequency is equal to the input frequency mUltiplied by the rate input M and divided by 10, ie.:
Mofin
fout = ---;0
where: M = D023 + e02 2 + 8 02 1 + A02 0 for decimal zero through nine.
When the rate input is binary 0 (all rate inputs low), Z remains high. In order to cascade devices to perform two-decade
rate multiplication (0-99), the enable output is connected to the enable and strobe inputs of the next stage, the Z
output of each stage is connected to the unity/cascade input of the other stage, and the SUb-multiple frequency is taken
from the Y output. For longer words, see typical application data, Figure 1.

I

The unity/cascade input, when connected to the clock input, may be utilized to pass the clock frequency (inverted) to
the Y output when the rate input/decoding gates are inhibited by the strobe. The unity/cascade input may also be used
as a control for the Y output.
All of the inputs of these counters are diode-clamped, and each input, except the clock input, represents one
normalized Series 54/74 load. The buffered clock input, used with the strobe gate, is only two Series 54/74 loads. Full
fan-out to 10 Series 54/74 loads is available from each of the output. These devices are completely compatible with
most TTL and DTL families. Typical dissipation is 270 milliwatts. The SN54167 is characterized for operation over the
full military temperature range ;f -55°C to 125°C, and the SN74167 is chara~terized for operation from oOe to 70°C.

1076

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TYPES SN54161, SN14161
SYNCHRONOUS DECADE RATE MULTIPLIERS
STATE AND/OR RATE FUNCTION TABLE (See Note AI
OUTPUTS

INPUTS

LOGIC LEVEL OR
NUMBER OF

BCD RATE

NOTES:

UNITY/

NUMBER OF PULSES
Y

Z

ENABLE

NOTES

H

X

H

X

X

X

X

X

H

L

H

H

B

L

L

L

L

L

L

L

10

H

L

H

1

L

L

L

L

L

L

H

10

H

1

1

1

C
C

L

L

L

L

L

H

L

10

H

2

2

1

C

L

L

L

L

L

H

H

10

H

3

3

1

C

L

L

L

L

H

L

L

10

H

4

4

1

C

L

L

L

L

H

L

H

10

H

5

5

1

C

L

L

L

L

H

H

L

10

H

6

6

1

C

L

L

L

L

H

H

H

10

H

7

7

1

C

L

L

L

H

L

L

L

10

H

C

L

L

H

L

L

H

10

H

1

C

L

L

L

H

L

H

L

10

H

8
9
8

1

L

8
9
8

1

C,D

L

L

L

10

H

9

9

C,D

'-

'-

'-

u

u

en

L

L

L

9

9

L

L

L

L

L

L

CLEAR ENABLE STROBE

0

C

B

A

CLOCK PULSES CASCADE

..

'-

'-

.u

H

10

H

,~

1

H

H

L

L

H

H

H

L

10

H

8

8

1

L

H

H

H

H

10

H

9

9

1

L

H

L

L

H

10

L

H

9

1

C,D
C,D

I C,D
I

E

A. H = high level, L = low level, X = irrelevant. All remaining entries are numeric counts.
B. This is a simplified illustration of the clear function. The states of clock and strobe' can affect the logic level of Y and Z. A low
unity/cascade will cause output Y to remain high.
C. Each rate illustrated assumes a constant value at rate inputs; however, these illustrations in no way prohibit variable-rate inputs.
D. These input conditions exceed the range of the decimal rate inputs.
E. Unity/cascade can be used to inhibit output Y.

functional block diagram and schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
V CC--___4I----

I

INPUT

Clock: Req = 2 kn NOM
All others: Req = 4 kn NOM

TYPICAL OF ALL OUTPUTS
VCC

OUTPUT

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TYPES SN54167, SN74167
SYNCHRONOUS DECADE RATE MULTIPLIERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . .
Input voltage . . . . . . . . . . . . .
Operating free·air temperature range: SN54167
SN74167
Storage temperature range

7V
5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54167
MIN NOM
4.5

Supply voltage, V CC

SN74167

MAX

MIN NOM

5

5.5 4.75

High-level output current, 10H

MAX

5

-400
16

low-level outpu~ current, 'Ol
0

Clock frequency, fclock

25

UNIT

5.25

V

-400

{LA

16 mA
25 MHz

0

Width of clock pulse, tw(clock)

20

20

ns

Width of clear pulse, tw(clearl

15

15

ns

Width of set-ta-nine pulse tw(set-ta-91

15

15

ns

(See Note 2)

Enable setup time, tsu:
From positive-going transition of clock pulse

25

From negative-going transition of previous clock pulse

t w (clock)-10

0

t w (clock)-10

ns
ns

(See Note 2)

Enable hold time, th:
From positive-going transition of clock pulse
From negative-going transition of previous clock pulse
Operating free-air temperature, T A
NOTE 2:

ns

25

0
0

tw(clock)-10

0

t w (clock)-10

20

tcp-10

20

tcp-10

ns

-55

125

0

70

°c

tw(clock) is the interval in which the clock is high. tcp is the total clock cycle starting with a negative transition. See Figure 1
SN5497, SN7497 data sheet,

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER

I

VIH

High-level input voltage

VI l

low-level input voltage

MIN

TYP:j:

MAX UNIT

2

Input clamp voltage
VOH

Hlgh-!evel o.Jtput voltage

Val

low-level output voltage

I,

Input current at maximum input voltage

IIH

High-level input current

clock input
other inputs
clock inputs

II l

low-level input current

lOS

Short circuit output current§

other inputs

Vee- MIN,

11- -12 mA

Vee = MIN,

V,H = 2 V,

Vil = 0.8 V,

10H = -400 /.LA

Vee= MIN,

VIH=2V,

Vil = 0.8 V,

10l = 16 mA

Vee = MAX,

VI = 5.5V

Vec= MAX,

VI=2.4V

Vec = MAX,

2.4

V
V

-1.5

V

34
0.2

i
0.4
1

V
V
mA

80
40
-3.2

VI = 0.4 V

-1.6
-18

Vee = MAX

0.8

leCH Supply current, output high

Vee- MAX,

See Note 3

43

ICCl Supply current, output low

Vee = MAX,·

See Note 4

65

JJ.A
mA

-55

mA

99

mA

mA

NOTES: 3. 'CCH is measured with outputs open and all inputs low.
4. ICCL is measured with outputs open and all inputs high except the set-to-nine input which is low.
tFor test conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.

:j: All typical values are at V CC

=5

V, T A

= 25° C.

§ Not more than one output should be shorted at a time.

1076

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TYPES SN54167, SN74167
SYNCHRONOUS DECADE RATE MULTIPLIERS
switching characteristics, VCC
PARAMETERS1f

= 5 V, TA = 25°C
FROM

TO

INPUT

OUTPUT

TEST CONDITIONS

MIN

TYP

25

32

f max

MAX UNIT
MHz

13

20

tpHL

14

21

tpLH

12

18

15

23

tPLH

Enable

Enable
Strobe

Z

Clock

y

tpHL

26

39

tpHL

20

30

tpLH

12

18

17

26

9

14

6

10

tPLH

Clock

Z

Rate

Z

tpHL
tPLH

CL = 15 pF,

tPHL

RL=400n,

TPLH

Unity/Cascade

Y

c+ ....... (..,. ....

y

Clock

Enable


----2::-:1~~=~~~1

tpHL
-r n

22

33
36

Z

15

23

Set-t0-9

Enable

18

27

Any Rate Input

y

15

23

15

23

tpHL
tpHL

--

24

Clear

tpLH

.-

Y

tpHL
tPLH

ns
ns
ns
ns

See Note 5

tpHL
tpLH

ns

tpHL

". I
ns
ns
ns
ns

1ff max is maximum clock frequency.
tpLH is propagation delay time, low·to·high-Ievel output.
tpH L is propagation delay time, high-to-Iow-Ievel output.
NOTE 5: Load circuit, voltage waveforms, and input conditions for measuring switching characteristics are the same as those for the SN5497
and SN7497, page 7-106.

TYPICAL APPLICATION DATA
This application demonstrates how the decimal-rate multipliers may be cascaded for longer words. Three decades are
illustrated (0.999 to 999) although longer words can be implemented by using the pattern shown. The output is
decoded either from output Y with a NOR gate or from output Z with a NAND gate. Either method of decoding
produces the complement of the output used.
~

II

______________________
~
RATE~A~
INPUT______________________
1M)

IL-------.--~+_+_+_----_+----~--+_+_+_r_----_+----~

NC

OUTPUT JL.

OUTPUT1J"

FIGURE 1

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7·225

TYPES SN54LS168A, SN54LS169A, SN54S168, SN54S169,
SN74LS168A, SN74LS169A, SN74S168, SN74S169SYNCHRONOUS 4-81T UP UP/DOWN COUNTERS

TTL
MSI

BULLETIN NO. DL-S 7612068, OCTOBER 1976

'LS168A, 'S168 ... SYNCHRONOUS UP/DOWN DECADE COUNTERS
'LS169A, 'S169 ... SYNCHRONOUS UP/DOWN BINARY COUNTERS
SERIES SN54LS', SN54S' ..• J OR W PACKAGE
SERIES SN74LS', SN74S' .•• J OR N PACKAGE
(TOP VIEW)

Programmable Look-Ahead Up/Down
Binary/Decade Counters
•

Fully Synchronous Operation for Counting
and Programming

•

Internal Look-Ahead for Fast Counting

•

Carry Output for n-Bit Cascading

•

Fully Independent Clock Circuit

TYPICAL MAXIMUM
TYPE

CLOCK FREQUENCY
COUNTING COUNTING

OUTPUTS
~

____-JA~____~

TYPICAL
POWER
DISSIPATION

UP

DOWN

'LSl68A. 'LSl69A

35MHz

35 MHz

100mW

'Sl68, 'S169

70 MHz

55 MHz

500mW

V
DATA INPUTS

positive logic: see description

description

•

These synchronous presettable counters feature an internal carry look-ahead for cascading in high-speed counting
applications_ The 'lS168A and 'Sl68 are decade counters and the 'lS169A and 'S169 are 4-bit binary counters.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation
helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A
buffered clock input triggers the four master-slave flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is, the outputs may each be preset to either level. The load input circuitry
allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at
the load input disables the counter and causes the outputs to agree with the data inputs after the next ciock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output. Both count enable
inputs (P and T) must be low to count. The direction of the count is determined by the level of the up/down input.
When the input is high, the counter counts up; when low, it counts down. Input'F is fed forward to enable the carry
output. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the
high portion of the QA output when counting up and approximately equal to the low portion of the QA output when
counting down. This low-level overflow carry pulse can be used to enable successive cascaded stages. Transitions at the
enable P or 'F inputs are allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. Changes at control inputs (enable P, enable T, load, up/down)
that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether
enabled, disabled,loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
The 'lS168A and 'LS169A are completely new designs. Compared to the original 'lS168 and 'lS169, they feature
O-nanosecond minimum hold time and reduced input currents IIH and Ill'

1076

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TYPES SN54LS168A, SN54LS169A, SN74LS168A, SN74LS169A
SYNCHRONOUS 4-81T UP/DOWN COUNTERS
functional block diagrams

•

en
a:
w

I-

2

:::>

oCJ

w

o


cc
c:(

z

iii
~

en

"3'
,...

Z

en

Pi
ij
III

Z

en

0

~ "~ g

......

y

~

i
~~~

~

•

if

8

/5

~~~

~~o

en

cc

W

IZ
::l

ot)

w

oc:(
t)

w

o

co

u:o

ij,...
Z

en

f8

ij
III

Z

en

-

12 §
0

~

~

-

" "
~ ..." "'3

10

:5

§:
u

~

374

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TYPES SN54LS168A, SN54S168, SN74LS168A, SN74S168
SYNCHRONOUS 4-81T UP/DOWN COUNTERS
'LS168A, 'S168 DECADE COUNTERS

typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1.
2.
3.
4.

Load (presetl to BCD seven
Count up to eight, nine (maximum). zero, one, and two
Inhibit
Count down to one, zero (minimum). nine, eight, and seven

I

L

DATA
INPUTS

j

s-.J

L.. _

c-.J

L_

j

,

rCLOCK

U"--W'--uLJ1J-U'--U-u'LJ-u'LJL.Jl.J-L
I

UfD

I

I

--

I I

__ J'

, I

:

7

I I
--,

PANDT

, I

I~-+__~I_I~________________~

I:
,I

Os

l
----n, !------------.....

___ -J

:!

I

,I

I

°c ----;--11
~ __ -J

1

!-i--------------------------~--~----------------~·

--,
I!
°D -____
L-.iJ

~:~~~ ----I

II

OUTPUT ___ ...J

I 1
"

LI

I

I

'---J

:7,,890

U I---..

2

',I

I

I

L-I

221109

COUNT UP --_II-INHIBIT

-I I---

8

7

COUNT DOWN - - - -

LOAD

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TYPES SN54LS169A. SN54S169.SN14LS169A. SN14S169
SYNCHRONOUS 4-81T UP UP/DOWN COUNTERS
'LS169A, 'S169 BINARY COUNTERS

typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1. Load (preset) to binary thirteen

2. Count up to fourteen, fifteen (maximum). zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum). fifteen, fourteen, and thirteen

LOAD

L---.J

A

,"----";-" -

---l

-

L..._

r-

B _ _ _~.....I _ -

DATA
INPUTS

C~

,r----..L---_

D

---.J
CLOCK

•

_--~i-+--~IHI~----------------------

I

UfO __ J

PANDT--'~~______________________--,
!
___ i

L
-

Q

D

RIPPLE -

CARRY

-

I

- --.I
-

OUTPUT- -

-r--...,;,..---u
•

~

I 13

I

14

15

I

I

0

2,

2

2

I·---COUNT
..
UP --_·.I·_INHIBIT-I
.

LJ
o

15

14

13

~COUNTOOWN-----

~

LOAD

1076

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TYPES SN54LS168A, SN54LS169A'ISN74LS168A, SN74LS169A
SYNCHRONOUS 4-81T UP/DOWN COUNTERS
schematics of inputs and outputs

EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

------'t--

Vcc

Reqf
VCC?
INPUT

'-~~-

~

OUTPUT

Load: Req = 10 k!2 NOM
Data: Req

= 25

k!2 NOM

Clock, Enable P, T, UfO: Req

= 20

k!2 NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
............ .
Input voltage . . . . . . .
............ .
Operating free-air temperature range: SN54LS168A, SN54LS169A.
SN74LS168A, SN74LS169A.
Storage temperature range

7V
7V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

•

recommended operating conditions
SN74LS168A
SN74LS169A

SN54LS168A
SN54LS169A
MIN
Supply voltage, VCC

4.5

NOM
5

High-level output current, IOH
Low-level output current, IOL

NOM

5.5

4.75

5

4
0

Width of clock pulse, tw(clock) (high or low) (see Figure 1)

25

0

25

25

Data inputs A, B, C, D

20

20

Enable PorT

20

20

Load

25

25

Up/Down

30

30

Hold time at any input with respect to clock, th (see Figure 1)
Operating free-air temperature, T A

1076

MIN

-400

Clock frequency, f clock

Setup time, tsu (see Figure 1)

MAX

0
-55

UNIT

MAX
5.25

V

-400

f.lA

8

rnA

25

MHz
ns

ns

0
125

0

ns
70

DC

TENTATIVE DATA
This page provides tentative information on a
new product. Texas Instruments reserves the
right to change specifications for th is product
in any manner without notice.

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7-231

TYPES SN54LS168A, SN54LS169A,SN74LS168A, SN74LS169A
SYNCHRONOUS 4-81T UP/DOWN COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS168A
PARAMETER

MIN
VIH

High-level input voltage

VIL
VIK

Low-level input voltage

TYP+

Input clamp voltage

VCC= MIN,

II = -18 rnA

VCC- MIN,

VIH-2V,

VIL = VIL max, 10H = -400 IJ.A

2.5

VCC = MIN,

In put cu rrent

A, B, C, D, P, U/D

at maximum

Clock, T

input current

-1.5

V

2.7
0.4

input current

VI =7 V

0.4

0.35

0.5

0.1

0.1

0.1

0.1 I rnA

0.2

0.2
20

20

20

40

40

-0.4

-0.4

-0.4

-0.4

-0.8

-0.8

VI=2.7V

Load
Clock, T

0.25

20
VCC = MAX,

Vce = MAX,

VI = 0.4 V

Load

lOS

Short-circuit output current§

VCC= MAX

ICC

Supply current

VCC= MAX,

V

3.4

V

A, B, C, D, P, U/D

Low·level
IlL

V

-1.5
3.4

I

V
0.8

Load
Clock, T

UNIT

TYP+ MAX

2

A,B,C,D,P,U/D

High-level
IIH

VCC= MAX,

MIN

0.7

0.25

IIOL =4 rnA
VIH=2V,
VIL=VILmax IIOL=8mA

VOL Low-level output voltage

input voltage

SN74LS169A

MAX

2

VOH High-level output voltage

II

SN74LS168A

SN54LS169A

TEST CONDlTlONSt

-20

-100

20

See Note 2

-20

34

20

I
IJ.A

rnA

-100

rnA

34

rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+ All typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured after applying a momentary 4.5 V, then ground, to the clock input with all other inputs grounded and the outputs
open.

•

switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER.

FROM

TO

!INPUT)

(OUTPUT)

TEST CONDITIONS

f max
tPLH
tPHL
tpLH
tPHL
tpLH

Clock
Clock

Enable T

Ripple
carry

See Figures 2 and 3

TYP

25

32

MAX

35

23
13

35
20

15

23

10

14
14

Ripple

17

25

carry

19

29

tPLHO

and Note 3

UNIT
MHz

23

10

carry

Up/Down

RL = 2 kn,

Q

Ripple

tPHL
tpHLO

CL=15pF,

Any

MIN

ns
ns
ns
ns

.f max =" Maximum clock frequency
tpLH =" propagation delay time, low-to-high-Ievel output.
tpHL =" propagation delay time, high-to-Iow-Ievel output.
°propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the
logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output
transition will be in phase. If the count is maximum (9 for 'LS168A or 15 for 'LS169A), the ripple carry output will be out of phase.
NOTE 3: Load circuit is shown on page 3-11.

TENTATIVE DATA

7-232

This page provides tentative information on a
new product. Texas Instruments reserves the
right to change specifications for th is product
in any manner without notice.

1076

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•

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TYPES SN54S168, SN54S169, SN74S168, SN74S169
SYNCHRONOUS 4-81T UP/DOWN COUNTERS
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

- - - - - -...--VCC
VCC--------~-------

50 Q NOM

OUTPUT

Enable P or T inputs: Req

~

= 1.4 kQ

O_t~_.e_r;~_.p_utS_:_Re_q_=2_.8_k_Q_N_O~_A

_______

I II

NOM

____

~1 ~I

J'-.:a.___..__.~

_________________

r.h
__________~

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 4)
Input voltage . . . . . . . .
Interemitter voltage (see Note 5)
Operating free-air temperature range: SN54Si68, SN54Si69 isee Note 6)
SN74S168,SN74S169
Storage temperature range

7V
5.5 V
5.5V

-55°C to 125°C
oOe to 700 e
0
-65°e to 150 e

recommended operating conditions
SN54S168

SN74S168

SN54S169

SN74S169

MIN
4.5

Supply voltage, VCC
Low-level output current, IOL

MIN

NOM

MAX

5

5.5

4.75

5

5.25

V

-1

rnA

20

Clock frequency, fclock

0

Width of clock pulse, tw(clock} (high or low} (see Figure 1)
Enable PorT

Setup time, tsu (see Figure 1)

10
4

14

14

6

6

20

20

Hold time at any input with respect to clock, th (see Figure 1)

1
-55

Operating free-air temperature, T A (see Note 6)

0

4

Load
Up/Down

40

10

Data inputs A, B, C, D

NOTES:

MAX
-1

High-level output current, IOH

UNIT

NOM

20

rnA

40

MHz
ns

ns

ns

1
125

0

•

70

°c

4. Voltage values, except interemitter voltage, are with respect to network ground terminal.
5. This is the voltage between two emitters of a multiple·emitter transistor. For these circuits, this rating applies between the count
enable inputs P and T . .
. .
0 . . .
6. An SN54S~68 or SN54S169 In the,,:, package operating at free-al~ temperatures above 91 C requires a heat sink that provIdes a
thermal resIstance from case to free-air, ReCA' of not more than 26 C/W.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-233

TYPES SN54S168, SN54S169, SN74S168, SN74S169
SYNCHRONOUS 4-81T UP/DOWN COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

I

PARAMETER

VIH

High-tevel input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

MIN

SN74S168
SN74S169

TYPt MAX

2

I

VOH High-level output voltage
VOL Low-level output voltage
II

Input current at maximum input voltage

IIH

High-level input current

IlL

SN54S168
SN54S169

TEST CONDITIONSt

Enable T
Other inputs
Enable T

Low-level input current

Other inputs

Vee = MIN,

II = -18mA

Vee = MIN,

VIH = 2 V,

VIL = 0.8 V,

10H = -1 mA

Vee= MIN,

VIH = 2 V,

VIL = 0.8 V,

10L = 20mA

Vee = MAX,

VI-5.5V

Vce = MAX,

VI=2.7V

2.5

lOS

Short-circuit output current§

VCC = MAX

Supply cureent

VCC- MAX,

TYPt

V

0.8

0.8

-1.2

-1.2

3.4

2.7

-40

V
V
V

0.51

V

1

1

mA

100

100

50

50

-4

-4

-2

-2

-100
100

!

3.4

0.5

See Note 2

UNIT\

MAX

2

Vec = MAX, VI = 0.5 V

Ice

MIN

-40

160

100

!1A

mA

-100

mA

160

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
fAil typical values are at V CC = 5 V, T A = 25°C.

§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2:

ICC is measured after applying a momentary 4.5 V, then ground, to the clock input with all other inputs grounded and the outputs
open.

switching characteristics, Vee
PARAMETER~

= 5 V, TA = 25°e

FROM

TO

(lNPUTI

(OUTPUT!

TEST CONDITIONS

f max

•

tpLH

carry

tPLH
tPLHO
tpHLO

Enable

40

70

T

Up/Down

UP /DOWN = LOW
MIN

TYP

40

55

MAX

21

14

21

20

28

20

28
15

15

8

15

11

15

7.5

11

6

12

15

22

15

25

Ripple

9

15

8

15

carry

10

15

16

22

carry

RL = 280

n,

See Figures 2 and 3

and Note 7

UNIT
MHz

14
8

Ripple

i

CL=15pF,

MAX

11

Any Q

Clock

tpHL
tpHL

TYP

Ripple

Clock

tPHL
tPLH

UP/DOWN = HIGH
MIN

ns
ns

ns

I

ns

~fmax '" maximum clock frequency
tpLH '" propagation delay time, low-to-high-Ievel output
tPHL '" propagation delay time, high-to-Iow-Ievel output
°Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the
logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output
transition will be in phase. If the count is maximum (9 for 'S168 or 15 for'S 169), the ripple carry output will be out of phase.
NOTE 7:

Load circuit is shown on page 3-10_

1076

7-234

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•

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TYPES SN54LS168A, SN54LS169A, SN54S168, SN54S169,
SN74LS168A, SN74LS169A, SN74S168, SN74S169
SYNCHRONOUS 4-81T UP UP/DOWN COUNTERS
PARAMETER MEASUREMENT INFORMATION

I-- tw(clock)

...-.j

I

(4...-- tw(clock) ~

I

I

I

I

CLOCK
INPUT

3V

I

Vref

I

I

T--- OV

I

--t

f4- tsu
I (active state)

LOAD
INPUT

\v~
f

j 4 - - tsu --.I
th -.!
(inactive state)
I

I.-

I

l~~~ ___ Ti - - -

i

~----~I-----'

~ tsu

I

DATA INPUTS
A, B, C, and D

--t--

th

-I

I

3V

!
------f---OV

I

I

I

____

J._

\.Vref

!
-------l---3V

Vref

----./

\

i

r-

tsu

I

-.I

th~

I

I

:C

\v~f
"-___+I ____________....j.:...IT

ENABLE P or
ENABLE f

I
I

I

'-

I
I

tsu

lv~

UP/DOWN
INPUT

OV

_V:f_ 3 V

I

I

~
I
\.
\

~th

th

I

3V

Fav

V ref

\...

VOLTAGE WAVEFORMS
NOTES:

OV

I

!

•

A. The input pulses are supplied by a generator having the following characteristics: PRR '" 1 MHz, duty cycle", 50%, Zout '" 50!2;
for 'LS168A and 'LS169A, tr '" 15 ns, tf '" 6 ns, and for 'S168 and 'S169. tr '" 2.5 ns, tf '" 2.5 ns.
B. For 'LS168A and 'LS169A, Vref ~ 1.3 V; for 'S168 and 'S169, Vref ~ 1.5 V.

FIGURE 1-PULSE WIDTHS, SETUP TIMES, HOLD TIMES

ENABLE
INPUT

f

,.,4

\. ,

f",V_re_f _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I
!+--tPHL

RIPPLE
CARRY
OUTPUT

NOTES:

3V

vref _______ av

----eo!

I

!.-- tPLH--II

I

I

\V~

VOLTAGE WAVEFORMS

VOL

lv~ ---VaH

A. The input 'Pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz, duty cycle", 50%, Zout '" 50 !2;
for 'LS168A and 'LS169A, tr '" 15 ns, tf '" 6 ns; and for 'S168 and 'S169, tr '" 2.5 ns. tf '" 2.5 ns.
B. tpLH and tpH L from enable T input to ripple carry output assume that the counter is at the maximum count (QA and QD high
for 'LS168A and 'S168, all Q outputs high for 'LS169A and 'S169).
C. For 'LS168A and 'LS169A, Vref ~ 1.3 V; for 'S168 and 'S169, Vref ~ 1.5 V.
D. Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum
count. As the logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0) the
ripple carry output transition will be in phase. If the count is maximum (9 for 'LS168A and 'S168, or 15 for 'LS169A and
'5169) the ripple carry output will be out of phase.

FIGURE 2-PROPAGATION DELAY TIMES TO CARRY OUTPUT
1076

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•

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7·235

TYPES SN54LS168A, SN54LS169A, SN54S168, SN54S169,
SN74LS168A, SN74LS169A, SN74S168, SN74S169
SYNCHRONOUS 4-81T UP/OOWNCOUNTERS
PARAMETER MEASUREMENT INFORMATION

I..tW!cIOCk)

..I

I

I

I

3V

CLOCK
INPUT

~tPLH
I

~tPHL

(measure at t n+1)

I

OUTPUT

0A

V

I

I

I

I

(measure at t n+2)

"tv",

/

Y~'r---~·
I

_ _ _ _..JrVref

~tPHL

I

I

(measure at t n +4)

~tPLH
I (measure at t n+2)

I
I

I

~~s----:~)I~,- ---

OUTPUT

°B

I...--...L- tpHL

I

:

.1
I

II

(measure at tn+Sl

I

•

I"
.......-

tPHL

-

-

-

:

(measure at t n +10
or tn+16l

I

(measure at tn+Sl

I

VOH

(measure at t n +10
or tn+16 1 (See Note B)

pf

"V",

VOL

I
...t--tpLH

I

I
RIPPLE
CARRY
OUTPUT

VOH

'~'Fs==_~lv: _____ _

°D

VOL

""1"--·""I-tPLH

~ v~::e Note B)

OUTPUT

r----r-

-

_

I

""11~-.....
I-tPHL

-

(measure at tn+4l

...

I

-

tPLH

OU6;UT-------------~s --......;.!-,..,lv~, ___
I

VOH

"".- - - - - - - . -

-

-

-

VOH

-

-

-

-

-

-

-

-

-

-

-

-

-

VOL

UP-COUNT VOLTAGE WAVEFORMS
NOTES:

A. The input pulses are supplied by a generator having the following characteristics: PRR .;; 1 MHz, duty cycle';; 50%. Zout '" 50 n;
for 'LS168A and 'LS169A, tr';; 15 ns, tf';; 6 ns; and for 'S168 and 'S169,t r ';; 2.5 ns,tf';; 2.5 ns. Vary PRR to measuref max •
B. Outputs Q D and carry are tested at tn+1 0 for the 'LS168A and 'S168, and at t n +16 for the 'LS169A and 'S169, where tn is the
bit-time when all outputs··are low.

C. For 'LS168A and 'LS169A, Vref

= 1.3

V; for 'S168 and 'S169, Vref

= 1.5

V.

FIGURE 3-PROPAGATION DELAY TIMES FROM CLOCK

1076

1-236

TEXAS '''ICORPORATED
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•

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TTL
MSI

TYPES SN54170, SN54LS170, SN74170, SN74LS170
4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
BULLETIN NO. DL-S 7611349, MARCH 1974-REVISED OCTOBER 1976

•

Separate Read/Write Addressing Permits
Simultaneous Reading and Writing

•

Fast Access Times ... Typically 20 ns

•

Organized as 4 Words of 4 Bits

•

Expandable to 1024 Words of n-Bits

•

For Use as:
Scratch-Pad Memory
Buffer Storage between Processors
Bit Storage in Fast Multiplication Designs

•

Open-Collector Outputs with Low
Maximum Off-State Current:
'170 ... 30 ~A
'LSi70 ... 20 p.A

•

SN54LS670 and SN74LS670 Are
C!':_:I __ D .... u_ .... _
~l1ll1lal CUL nave

.,

SN54170, SN54LS170 ... J OR W PACKAGE
SN74170, SN74LS170 ... J OR N PACKAGE
(TOP VIEW)
WRITE SELECT

Vcc

ENABLE

D~~A 'W';''W;'' WRITE

READ

OUTPUTS

"'Q'T"Ci2'

D2

Cl.. _ .._ r\ .... _ ...._
VULt-IUL:I

02

positive iogic: see description

~-~LaLe

description
The '170 and 'LS170 MSI 16-bit TTL register files incorporate the equivalent of 98 gates. The register file is organized
as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either
write-in or retrieve data. This permits simultaneous writing into one location and reading from another word location.
Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined
by the write-address inputs A and 8 in conjunction with a write-enable signal. Data applied at the inputs should be in its
true form. That is, if a high-level signal is desired from the output, a high level is applied at the data input for that
particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate
inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable
input, GW, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the
internal latches. When the read-enable input, GR, is high, the data outputs are inhibited and remain high.

•

The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding
gates are used to complete the address for reading a word. When the read address is made in conjunction with the
read-enable signal, the word appears at the four outputs.
This arrangeinent-data-entry addressing separate from data-read addressing and individual sense line-eliminates recovery
times, permits simultaneous reading and writing, and is limited in speed only by the write time (30 nanoseconds
typical) and the read time (25 nanoseconds typical). The register file has a nondestructive readout in that data is not
lost when addressed.
All '170 inputs and all inputs except the read enable and write enable of the 'LS170 are buffered to lower the drive
requirements to one Series 54/74 or Series 54LS/74LS standard load, respectively. Input-clamping diodes minimize
switching transients to simplify system design. High-speed, double-ended AND-OR-INVERT gates are employed for the
read-address function and drive high-sink-current, open-collector outputs. Up to 256 of these outputs may be wire-AND
connected for increasing the capacity up to 1024 words. Any number of these registers may be paralleled to provide
n-bit word length.
The SN54170 and SN54LS170 are characterized for operation over the full military temperature range of -55°C to
125°C; the SN74170 and SN74LS170 are characterized for operation from oOe to 70°C.

1076

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7-m

TYPES SN54170, SN54LS170, SN74170, SN74LS170
4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
logic
READ FUNCTION TABLE (SEE NOTES A AND DI

WRITE FUNCTION TABLE (SEE NOTES A, B, AND CI
WRITE INPUTS

READ INPUTS
01

02

Q3

04

L

GR
L

WOB1

WOB2

WOB3

WOB4
W1B4

0

1

2

3

RB

L

GW
L

0=0

00

00

L

H

L

00

00
O=D

H

L

L

00

00

00
O=D

H

H

L

00

00

X

X

H

00

00

OUTPUTS

RA
L

WA
L

WB

NOTES:

WORD

00

L

H

L

W1B1

W1B2

W1B3

H

L

L

W2B1

W2B2

W2B3

W2B4

00

00
0=0

H

H

L

W3B1

W3B2

W3B3

W3B4

00

00

X

X

H

H

H

H

H

A. H = high level, L = low level, X = irrelevant.
B. (Q = 0) = The four selected internal flip·flop outputs will assume the states applied to the four external data inputs.
C. Q O = the level of Q before the indicated input conditions were established.
O. WOB1 = The first bit of word 0, etc.

functional block diagram

'170

OUTPUTS

•

DATA
INPUTS

03

1",,,f

(4)

(5)

~
WRITE INPUT

374

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TYPES SN54170, SN54LS170, SN74170, SN74LS170
4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
REVISED OCTOBER 1976

functional block diagram
'LS170

DATA
INPUTS

JI

I
03

•
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage: '170
'LS170
Off-state output voltage: '170
'LS170
Operating free-air temperature range: SN54170, SN54LS170 (see Note 2)
SN74170,SN74LS170
Storage temperature range
NOTES:

7V

5.5V
7V

5.5 V
. . ..

7V

-55°C to 125°C
. oOe to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
2. An SN54170 in the W package operating at free-air temperatures above 105°C requires a heat sink that provides a thermal
resistance from case to free-air, ReCA' of not more than 38°C/W

1076

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7-239

TYPES SN54170, SN74170
4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN54170

SN74170

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

Supply voltage, Vee

UNIT

High-level output voltage, VOH

5.5

5.5

V

Low-level output current, IOL

16

16

mA

Width of write-enable or read-enable pulse, tw

25

25

ns

10

10

ns

15

15

ns

15

15

ns

5

5

ns

25

25

Data input with respect to
Setup times, high- or low·level data

write enable, tsu(O)

(see Figure 2)

Write select with respect to
write enable, tsu{W)
Data input with respect to

Hold times, high- or low-level data

write enable, th(D)

{see Note 3 and Figure 2}

Write select with respect to
write enable, th{W)

Latch time for new data, tlatch (see Note 4)
Operating free-air temperature range, T A (see Note 2)
NOTES:

-55

125

I

V

ns

0

°e

70

2. An SN54170 in the W package operating at free·air temperatures above 105°C requires a heat sink that provides a thermal
resistance from case to free-air, ReCA' of not more than 38° C/W.
3. Write select setup time will protect the data written into the previous address. If protection of data in the previous address is not
required, !su(w) can be ignored as any address selection sustained for the final 30 ns of the write-enable pulse and during th(W)
will result in data being written into that location. Depending on the duration of the input conditions, one or a number of
previous addresses may have been written into.
4. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is important
only when attempting to read from a location immediately after that location has received new data.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

•

VIH

High-level input voltage

VIL

Low·level input voltage

VIK

Input clamp voltage

IOH
VOL

TEST CONDITIONSt

MIN

TYP+

MAX

UNIT
V

2

High-level output current
Low-level output voltage

Vee= MIN,

II = -12 mA

Vee - MIN,

VOH - 5.5 V,

VIH=2V,

VIL=0.8V

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

IOL = 16mA

0.8

V

-1.5

V
}.LA

30
0.2

0.4

!

I

V

II

Input current at maximum input voltage

Vee - MAX, VI - 5.5 V

1

IIH

High-level input current

Vee = MAX, VI=2.4V

40

}.LA

IlL

Low-level input current

Vee = MAX,

-1.6

mA

lee

Supply current

VI = 0.4 V

Vee = MAX, LSN54170

127§

140

See Note 5

127§

150

ISN74170

mA

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
§Typical supply current shown is an average for 50% duty cycle.
NOTE 5: Maximum ICC is guaranteed for the following worst·case conditions: 4.5 V is applied to all data inputs and both enable inputs, all
address inputs are grounded, and all outputs are open.

1076

7-240

TEXAS INCORPORATED
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POST OFFICE BOX 5012

•

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TYPES SN54170, SN74170
4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
switching characteristics, Vee
PARAMETER~

tPLH

= 5 V, TA = 25°e

FROM

TO

(INPUT)

(OUTPUT)
AnyQ

Read enable

TEST CONDITIONS
CL=15pF,

tpHL

RL=400n,

MAX UNIT

10

15

20

30

23

35

30

40

tpLH

25

40

34

45

20

30

30

45

AnyQ

Read Select
Write enable

See Figures 1 and 2

AnyQ

CL=15pF,

tpHL

RL=400n,

tPLH

AnyQ

Data

See Figures 1 and 3

tpHL

tpH L

TYP

tpHL

tPLH

~tpLH

MIN

== propagation delay
== propagation delay

ns
ns
ns
ns

time, low-to-high-Ievel output
time, high-to-Iow-Ievel output

schematics of inputs and outputs

'170

'170
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

vcc------~

__------OUTPUT

•

INPUT

374

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TYPES SN54LS170, SN74LS170
4-BY-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
recommended operating conditions
SN54LS170
Supply voltage, Vee

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

High-level output voltage, VOH
Low-level output current, IOL
Width of write-enable or read-enable pulse, tw
Data input with respect to
Setup times, high- or low-level data

write enable, tsu(Q)

(see Figure 2)

Write select with respect to
write enable, tsu(W)
Data input with respect to

Hold times, high- or low-level data

write enable, th(D)

(see Note 3 and Figure 2)

Write select with respect to

Operating free-air temperature range, T A
NOTES:

5.5

5.5

4

8

UNIT
V
V
rnA

25

25

ns

10

10

ns

15

15

ns

15

15

ns

5

5

ns

25

25

write enable, th(W)
Latch time for new data, tlatch (see Note 4)

SN74LS170

MIN

-55

125

ns

0

70

°e

3. Write-select setup time will protect the data written into the previous address. If protection of data in the previous address is not
required, tsu(W) Can be ignored as any address selection sustained for the final 30 ns of the write·enable pulse and during th(W)

will result in data being written into that location. Depending on the duration of the input conditions, one or a number of
previous addresses may have been written into.
4. Latch time is the time allowed for the internal output of the latch to assume the state of new data. See Figure 2. This is important
only when attempting to read from a location immediately after that location has received new data.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt

PARAMETER

•

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

IOH

High-level output current

SN54LS170
TYP:j: MAX

MIN
2

Vee :MIN,

II: -18 mA

Vee: MIN,

VOH = 5.5 V,

1ioL = 4mA
VIH=2V,
VIL=VILmax IIOL=8mA

VOL Low-level output voltage

IIH

Input current at

Any D, R, or W,

maximum input voltage

GR orGw
Any D, R, orW

High-level input current

IlL

Low-level input current

lee

Supply current

V

2
0.7

0.8

V

-1.5

-1.5

V

20

20

/.IA

0.4

0.25

0.4

0.35

0.5

VIL = VIL max, VIH = 2 V
Vee = MIN,

II

SN74LS170
UNIT
TYP:j: MAX

MIN

GRorGw
AnyD,R,orW
GR or GW

Vee = MAX,

0.25

V

VI = 7V

Vee = MAX,

VI = 2.7 V

Vee = MAX,

VI = 0.4 V

Vee= MAX,

See Note 6

25

0.1

O·
.1 ,

0.2

0.2

20

20

40

40

-0.4

-0.4

-0.8

-0.8

40

25

40

rnA
/.IA
rnA
rnA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:tA" typical values are at VCC = 5 V, T A = 25°C.
NOTE 6: ICC is measured under the following worst-case conditions: 4.5 V is applied to a" data inputs and both enable inputs, all address
inputs are grounded, and a" outputs are open.

1076

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TYPES SN54LS170. SN74LS170
4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~

tpLH

FROM

TO

(INPUT)

(OUTPUT)

Read enable

AnyQ

tpHL

TEST CONDITIONS

Read select

AnyQ

Write enable

AnyQ

See Figures 1 and 2

tpHL
tPLH
tpHL

CL=15pF,
RL = 2 kn,

tpLH

AnyQ

Data

TYP
20

CL=15pF,
RL = 2 kn,

tPLH

MIN

See Figures 1 and 3

tpHL

MAX UNIT
30

20

30

25

40

24

40

30

45

26

40

30

45

22

35

ns
ns
ns
ns

~ tp LH "" propagation delay time, low-to-high-Ievel output
tpHL "" propagation delay time, high-to-Iow-Ievel output

schematics of inputs and outputs
'LS170

'LS170

EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

Vee

----+---

:NPUT -

.....~i-....-

..........
__

~OUTeuT

•

Any D, R, or W: Req = 20 kn NOM
GR or GW: Req =10 kn NOM

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TYPES SN54170, SN54LS170, SN74170, SN74LS170
4-8Y-4 REGISTER FILES WITH OPEN-COLLECTOR OUTPUTS
REVISED MARCH 1974

PARAMETER MEASUREMENT INFORMATION

Vee
FROM OUTPUT
UNDER TEST

~
l

TEST
POINT

Tel

CL includes probe and jig capacitance

LOAD CIRCUIT

FIGURE 1

~
___________

WFlITE.sELECT
INPUT WA or We

Vref

I

lSee Note A.)

DATAINPIJT

~~~2~t~!tD4

OV

''"'~ i.- "'WI

I

t----+- '1"I(0!

INPUTGw

I

~~'r;'-

---'1

f.-----1

_________

OUTPUT

3\1

•

ISft'NofeBI

READ·ENABLE

j'w----r-l
3V
~Vre'
i~

V rt ,

\ . V rel
:~

INPUTGR

!

g~T;'~';,';U,~ ~,-",_,___---'1_____________ ::

_ _ _ ov

~~¥=-

:

___

I

:~~~~:ABLE__ - ,-:___--JI

ov

~'PHL:~'PlH

11IVOH

OUTPUT

0'. 02. 00, o.(l'

~
1.----1-:.: - I

;.. 'PHl...i

V'I

"

r .. ;

V

vOL

OUTPUT

_

_

\~f- -----::
~'PLH

"'Hl

~v-.

al,Q2,03,O'C: _

NOTES:

VOH

VOLTAGE WAVEFORM 1

1

I

Vref

~

_ _ _ _ _ _ 3V

~

If
_ _ _ _ _ _...J

~tpHl

ref

----

~ [tatch----,
INPUT RA or Ae

\V"~ - - -- - -::

IPLH

----~IV
i-----

Q1, Q2, OJ Of 0lIl

ov

V

0'01

:~~:~ABl_E-.,;:___

0'01

~[,ufDl

WR'TE'EN.BLe~tw

I Vref

I
3v

~" .• I
~
I
~I
Vre! 1
..L~,,:,rere~~ ________________
I

\------------'3

DATAINPUTJ-

01,02.03 or 04

I

--I :-

3V

Vre!

~3V

~~ _ _ _ OV

_

VOL TAGE WAVEFORMS

VOLTAGE WAVEFORM 2

FIGURE 2

FIGURE 3

A. High-level input pulses at the select and data inputs are illustrated in Figure 2; however, times associated with low-level pulses are
measured from the same reference points.
B. When measuring delay times from a read-select input, the read-enable input is low. When measuring delay times from the
read-enable input, both read-select inputs have been established at steady states.
C. In Figure 3, each select address is tested. Prior to the start of each of the above tests, both write and read address inputs are
stablized with WA = RA and WB = RB. During the test GR is low.
D. Input waveforms arE; supplied by generators having the following characteristics: PRR .;;; 1 MHz, Zout "" 50 n, duty cycle';;; 50%,
tr .;;; 10 ns and tf .;;; 10 ns for' 170, and tr .;;; 15 ns and tf .;;; 6 ns for' LS 170.
D. For '170, Vref = 1.5 V; for 'LS170, Vref = 1.3 V.

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TTL
LSI

TYPE SN74172
16-81T MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS
BULLETIN NO. DL-S 7211744, MAY 1972 -

•

•

Independent Read/Write Addressing Permits
Simultaneous Reading and Writing

J OR N DUAL-IN-LiNE
PACKAGE (TOP VIEW)

Organized as Eight Words of Two Bits Each
WRITE

•

Fast Access Times:
From Read Enable ... 15 ns Typical
From Read Select ... 33 ns Typical

•

Three-State Outputs Simplify Use in
Bus-Organized Systems

•

Applications:
Stacked Data Registers
Scratch-Pad Memory
Buffer Storage Between Processors
Fast Multiplication Schemes

REVISED DECEMBER 1972

DATA
INPUTS

WRITE

WRITE/READ
ADDRESS

READ
ENABLE

OUTPUTS

ADDRE~ENABLE~~~

Vee

1W2

lOA

20A

2GW

2W!R2 2W/Al 2W/RO 2GR

1GR

lOA

2QA

~W';,~E~CLOCK~~GND
nniT~

t:NA~Lt::

ADDRESS

description

uATA
INPUTS

Ht-AU
ADDRESS

UUiPUTS

positive logic: see description

The SN74172, containing the equivalent of 201 gates
on a monolithic chip, is a high-performance 16-bit
register file organized as eight words of two bits each.
Multiple address decoding circuitry is used so that the
read and write operation can be performed independently on two word locations. This provides a true
simultaneous read/write capability. Basically, the file
consists of two distinct sections (see Figure A).
Section 1 permits the writing of data into any two-bit
word location while reading two bits of data from
another location simu Itaneously. To provide this
flexibility, independent decoding is incorporated.

I

I

I

'1 101

I

~-L----{=~=Hg-""~t""'-""-- --

SWORD

28IT
STORAGE

----------~

I
I

AEGISTE~

I
I
I
I

Section 2 of the register file is similar to section
with the exception that common read/write address
circuitry is employed. This means that section 2 can
be utilized in one of three modes:

•

I

I
1411

.

10

I

I

I

I

I

8UN~i~Ll

I

I

LINE

MULTIPLEXER

I
113) lOA

I
I

I
1111)20e

1) Writing new data into two bits
2) Reading from two bits
3) Writing into and simultaneously
reading from the same two bits.

~
ADDRESS

WRITE/READ
2W1"

Regardless of the mode, the operation of section 2 is
entirely independent of section 1.

FIGURE A

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TYPE SN74172
16-81T MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS
description (continued)
The three-state outputs of this register file permit connection of up to 129 compatible outputs and one Series 54/74
high-logic-level load to a common system bus. The outputs are controlled by the read-enable circuitry so that they
operate as standard TTL totem-pole outputs when the appropriate read-enable input is low or they are placed in a
high-impedance state when the associated read-enable input is at a high logic level. To minimize the possibility that two
outputs from separate register files will attempt to take a common bus to opposite logic levels, the read-enable circuitry
is designed such that disable times are shorter than enable times.
All inputs are buffered to lower the drive requirements of the clock, read/write address, and write-enable inputs to one
normalized Series 54/74 load, and of all other inputs to one-half of one normalized Series 54/74 load.
Functions of the inputs and outputs of the SN74172 are as shown in the following table.
SECTION 1

SECTION 2

DESCRIPTION

Write Address

FUNCTION

1WO, 1W1, 1W2

2W/RO, 2WIR1, 2W/R2

Binary write address selects one of eight two-bit
word locations.

Write Enable

1GW

2GW

When low, permits the writing of new data into
the selected word location on a positive transition
of the clock input.

lOA, lOB

2DA,2DB

Data at these inputs is entered on a positive
transition of the clock input into the location
selected by the write address inputs if the write
enable input is low. Since the two sections are
independent, it is possible for both write functions
to be activated with both write addresses selecting
the same word location. If this occurs and the
information at the data inputs is not the same for
both
sections
(i.e.,
lOA 01= 2DA
and/or
1DB 01= 2DB) the low-level data will predominate
in each bit and be stored.

Read Address

lRO, lRl, lR2

Common with
write address

Binary write address selects one of eight two-bit
word locations.

Read Enable

lGR

2GR

Data Outputs

lOA, lOB

20A,20B

Data Inputs

•

Clock

CK

When read enable is low, the outputs assume the
levels of the data stored in the location selected by
read address inputs. When read enable is high, the
associated outputs remain in the high-impedance
state and neither significantly load nor drive the
lines to which they are connected.
The positive-going transition of the clock input
will enter new data into the addressed location if
the write enable input is low_ The clock is
common to both sections.

572

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TYPE SN74172
16-81T MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (see Note 1)
Input voltage
.. . . .
Output voltage (see Note 2)
Operating free-air temperature range
Storage temperature
NOTES:

7V
5.5V
5.5V
O°C to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
2. This is the maximum voltage which should be applied to any output when it is in the high·impedance state.

recommended operating conditions
Supply voltage, Vee

MIN

NOM

4.75

5

High-level output current, 10H
Low-level output current, 10L
Clock frequency, f clock

0

Width of clock pulse, tw(clock)

MAX UNIT
5.25

V

-5.2

mA

16

mA

20

MHz

25

I Write select

ns

t w (dock)+10

~1~H~i9~h~-le~v~e~ld~a~ta~~____3~0~__________~1

I

Setup time, tsu(see Figure 1)

Hold time, th(see Figure 1)
Data release time, trelease (see Figure 1)

Low-ievei data

45

Write enable

35

Write select

0

Write enable

0

ns

High-level data

10

Low-level data

10

Operating free-air temperature, T A

I

ns

0

70

ns
°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

TEST eONDITIONSt

MIN

TYPt MAX UNIT
V

2

VOL

Low-level output voltage

10(off)

Off-state (high-impedance state) output current

II
IIH

Vee= MIN,

II = -12 mA

Vee - MIN,

VIH - 2 V,

VIL = 0.8 V,

10H = -5.2 mA

Vee - MIN,

VIH - 2 V,

VIL = 0.8 V,

10L = 16 mA

2.4

V

-1.5

V

3
0.2

V
0.4

Vee = MAX,

Va - 2.4 V

40

Vee = MAX,

Va = 0.4 V

-40

Input current at maximum input voltage

Vee - MAX,

VI- 5.5V

High-level input current

Vee = MAX,

VI = 2.4 V

\2W/RO, 2W/Rl, 2W/R2,
IlL

0.8

LOW-level input current

lOS

Short-circuit output current §

ICC

Supply current

lGW, 2GW, or clock

Vee = MAX,

I Any other input

•

Il A

1

mA

40

IlA

-1.6

VI = 0.4 V

V

mA

-0.8
-18

Vee = MAX
Vee - MAX,

All inputs at 4.5 V,

Outputs open

112

-55

mA

170

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at VCC = 5 V, TA

= 25°C.

§Not more than one output should be shorted at a time.

1076

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TYPE SN74172
16-BIT MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS
switching characteristics, Vee = 5 V, TA = 25°e, RL = 400

n
TEST

PARAMETER

MIN

CONDITIONS

f max

Maximum clock frequency

tpLH

Propagation delay time, low-to-high-Ievel output from read select

tpHL

Propagation delay time, high-to-Iow-Ievel output from read select

tpLH

Propagation delay time, low-to-high-Ievel output from clock

tpHL

Propagation delay time, high-to-Iow-Ievel output from clock

tZH

TYP

MAX UNIT

20

MHz
33

45

30

45

35

50

35

50

Output enable time to high level

14

30

tZL

Output enable time to low level

16

30

tHZ

Output disable time from high level

CL

6

20

tLZ

Output disable time from low level

See Figure 1

11

20

CL=50pF,
See Figure 1

= 5 pF,

ns
ns
ns
ns

PARAMETER MEASUREMENT INFORMATION
t---tw~

CLOCK~I 3V
INPUT

WRITE

1--.. ,0",-

____

SELECT
INPUTS

1.5 V

1.5 V

-I--------Ov

t.u

~ISeeNot.CI~----3V
'1.5
-V
__________

'

L
,

1.5 V

ov

i~'!!~----3V
Y. v
15 V'-i I
. ."'\. I
0V

DATA INPUT
(HIGH·LEVEL D A T A l - - . / ' 1.5

tsu --------..

It

~ ...-

I

DATA INPUT
(LOW·LEVEL DATAl

WRITE

~~~i:

~.5V

~

1.5~

INPUT

WAVEFORM'
(See

I----tsu-

Note BI

WAVEFORM 2
(See Note B)

~::

i---1ZL---I

t-ILZ"""1

I

1

t----~4.5V
~'.5V

: 51 closed.
,520oon
~
~ tZH------!
Slopen,
52 closed

:
F

:

~~:~

~"".5V
~==*--.VOL
:

~ tHZ-: 0.5 v 0.5 v

-----.1;.::';----

VOH

'~::::"1.5V

1.SV
:::;0 V

51 and

S2c1osed

3V

:
.l-------OV

ENABLE AND DISABLE TIMES FROM READ ENABLE

~th

tsu

1.5V

":
:

)<
-~:.::'---OV
3V

NOTES:

;

OUTPUT

1.5"x

such that the output is low except when disabled.
Waveform 2 is for an output with internal conditions
such that the output is high except when disabled.

I
""--VOL
I--~LH-t
:/:,,:"1

OUTPUT

VOH

/,.5V

------------------------~

A. Input waveforms are supplied by pulse generators
having the following
characteristics: tr';;; 7 ns,
tf';;; 7 ns, PRR = 1 MHz, Zout '" 50 f2.
B. Waveform 1 is for an output with internal conditions

____________________~r---~_LH~~--VOH

•

~.5V

READ
ENABLE

C. Write select setup time, as specified, will protect data
written into previous address.

-VOL

D, Load circuit is shown on page 3-10,

SWITCHING TIMES FROM CLOCK INPUT
VOLTAGE WAVEFORMS
FiGURE i

schematics of inputs and outputs
EaUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS
----41~-- V CC

OUTPUT

2W/RO, 2W/R1, 2W/R2,
1GW, 2GW, or Clock: Req
Other inputs: Req

=4
=8

kf2 NOM
kf2 NOM

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TYPES SN54173, SN54LS173, SN74173, SN74LS173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS

TTL
MSI

BULLETIN

•

Three-State Outputs Interface Directly
with System Bus

•

Gated Output-Control Lines for Enabling or
Disabling the Outputs

•

Fully Independent Clock Virtually
Eliminates Restrictions for Operating in One
of Two Modes:

DL-S 7611721 OCTOBER 1976

SN54173, SN54LS173 ••• J OR W PACKAGE
SN74173, SN74LS173 ••• J OR N PACKAGE
(TOP VIEW)
DATA INPUTS

DATA ENABLE
INPUTS

VCCCLEAR~~

Parallel Load
Do Nothing (Hold)
•

For Application as Bus Buffer Registers
TYPICAL

MAXIMUM

PROPAGATION

CLOCK

POWER

DELAY TIME

FREQUENCY

DISSIPATION

'173

23 ns

35 MHz

250mW

'LS173

18

50

~.l!Hz

85m\AJ

TYPE

!1S

TYPICAL

L.!.Jt..!JL!JLiJ~L!JL.?JL.!J
,10
20
30
40, CLOCK GND
~

description

OUTPUT CONTROL

The '173 and 'LS173 four-bit registers include D-type
flip-flops featuring totem-pole t~ree-state out-puts
capable of driving highly capacitive or relatively
low-impedance loads. The high-impedance third state
and increased high-logic-level drive provide these
flip-flops with the capability of being connected
directly to and driving the bus lines in a bus-organized
system without need for interface or pull-up components. Up to 128 of the SN74173 or SN74LS173
outputs may be connected to a common bus and still
drive two Series 54/74 or 54LS/74LS TTL normalized loads, respectively. Simi larly, up to 49 of the
SN54173 or SN54LS173 outputs can be connected
to a common bus and drive one additional Series
54/74 or 54LS/74LS TTL normalized load, respectively. To minimize the possibility that two outputs
will attempt to take a common bus to opposite logic
levels, the output control circuitry is designed so that
the average output disable times are shorter than the
average output enable times.

OUTPUTS

positive logic: see function table

FUNCTION TABLE

I

I~un
I-----r----.----=------.----I
OUTPUT
DATA ENABLE

DATA

CLEAR

CLOCK

G1

G2

H

X

X

X

X

L

L

L

X

X

X

00

D

I

Q

L

t

H

X

X

QO

L

t

X

H

X

L

t

L

L

L

QO
L

L

t

L

L

H

H

•

When either M or N (or both) is (are) high the output is
disabled to the high-impedance state; however sequential
operation of the flip-flops is not affected.

Gated enable inputs are provided on the '173 and 'LS173 for controlling the entry of data into the flip-flops. When
both data-enable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive
transition of the buffered clock input. Gate output control inputs are also provided. When both are low, the normal
logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are
disabled independently from the level of the clock by a high logic level at either output control input. The outputs then
present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table.
Higher density D-type registers, some with improved performance and including the new octal D-type registers,
are shown in the functional index/selection guide, see pages 1-11 and 1-12.

1076

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7-249

TYPES SN54173, SN54LS173, SN74173, SN74LS173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage: '173 . .
'LS173 . . . . .
Off·state output voltage
Operating free-air temperature range: SN54173, SN54LS173
SN74173,SN74LS173
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminals.

functional block diagram and schematics of inputs and outputs

. 7V
5.5 V
.7 V
5.5 V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

Q
'173

EaUIVALENT OF EACH INPUT
(11
OUTPUT

VCC

M

CONTROL

4 kfl NOM

N

{

INPUT

OATA

~

ENABLE

'

--

TYPICAL OF ALL OUTPUTS

G2

OAT A

20

.:.:..::::'-----+----+--1

•

'LS173
EaUIVALENT OF EACH INPUT

vee---T-~ 20 kfl NOM

IN'UTO--

TYPICAL OF ALL OUTPUTS

,Vee

1'51

OUTPUT

-....
1

dynamic input activated by a transition from a high level to a low level.

I

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POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54173, SN74173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS
recommended operating conditions
SN54173
MIN
Supply voltage, Vee

SN74173

NOM MAX MIN

4.5

5

5.5

High·level output current, 10H

4.75

NOM MAX
5

-2

Low-level output current, 10L

16

Input clock frequency, fclock

0

Width of clock or clear pulse, tw

Setup time, tsu

0

20

20

Data enable

17

17

Data

10

10

Clear inactive state

10

10

Data enable

Hold time, th

25

Data

Operating free-air temperature, T A

2

2

10

10

-55

125

UNIT

5.25

V

-5.2

mA

16

mA

25 MHz
ns

ns

ns

0

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONSt

Loy".-Ievel input voltage
V IK
VOH

VOL

10(off)

IH

I MIN TYP:j: MAX IUNITI

I

High-level input voltage

I nput clamp voltage
High-level output voltage

Low-Ievei output voltage

Vee = MIN,

11- -12 mA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10H = MAX

Vee= MIN,

VIH~2V,

VIL = 0.8 V,

10L = 16 mA

o.J ~ I

2

-1.5

V

2.4

0.4

Vee-MAX,

I VO-2.4V

40

VIH = 2 V

I V o=O.4V

-40

I nput current at maximum input voltage

I Vee = MAX,

V I = 5.5 V

H'19h -level input current

I V ee = MAX

V 1- 24 V

Off-state (high-impedance state) output current

IlL

Low-level input current

Vee - MAX,

lOS

Short-circuit output currend

Vee = MAX

ICC

Supply current

Vee= MAX,

V

V

JJ-A

1 I mA

VI - 0.4 V
-30
See Note 2

50

-1.6

mA

-70

mA

72

mA

tFor ~onditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
:j:AII tYpical values are at V CC = 5 V, T A = 25° C.

§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open; clear grounded following momentary connection to 4.5 V; N, G1, G2, and all data inputs
grounded; and the clock input and M at 4.5 V.
'

'switching characteristics, Vee = 5 V, TA = 25°e, RL = 400

•

Q

PARAMETER

TEST CONDITIONS

f max

Maximum clock frequency

tpHL

Propagation delay time, high-to-Iow-Ievel output from clear input

tPLH

Propagation delay time, low-to·high-Ievel output from clock input

eL = 50 pF,
See Note 3

MIN

TYP

25

35

MAX

UNIT
MHz

18

27

28

43

tpHL

'Propagation delay time, high-to-Iow-Ievel output from clock input

19

31

tPZH

Output enable time to high level

7

16

30

tPZL

Output enable time to low level

7

21

30

tPHZ

Output disable time from high level

eL=5pF,

3

5

14

tPLZ

Output disable time from low level

See Note 3

3

11

20

ns
ns

ns

ns

NOTE 3: Load circuits and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE B?X 5012

•

DALLAS. TEXAS 75222

7-251

TYPES SN54LSI73, SN74LS173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS
recommended operating conditions
SN54LS173

SN74LS173

MIN

NOM

MAX

MIN

NOM

4.5

5

5.5

4.75

5

Supply voltage, Vee
High-level output current, IOH

-1

Low-level output current, IOL

MAX
5.25

V

-2.6

mA

12
0

Input clock frequency, fclock
Width of clock or clear pulse, tw

Hold time, th

0
20

17

17

Data

17

17

Clear inactive state

10

10

Data enable

0

0

Data

0

mA
MHz

ns

ns

0

-55

Operating free-air temperature, T A

24

30

ns

20
Data enable

Setup time, tsu

30

125

UNIT

0

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

MIN TYPt

SN74LS173

MAX MIN TYPt

2

Low-level output voltage

10(off) Off-state (high-impedance state) output current

•

SN54LS173

TEST CONDITIONSt

Vee = MIN,

11=-18mA

Vee = MIN,

VIH - 2 V,

2.4

MAX

2

V

0.7

0.8

V

-1.5

-1.5

V

3.4

2.4

V

3.1

VIL = VILmax

10H = MAX

Vee = MIN,

10L = 12 mA

VIL=0.8V

10L - 24 mA

Vee = MAX,

VO=2.7V

20

20

VIH = 2 V

Va = 0.4 V

-20

-20

0.1

0.1

II

Input current at maximum input voltage

Vee = MAX,

VI =7 V

0.25

UNIT

0.4

0.25

0.4

0.35

0.5

V
IJA
mA

IIH

High-level input current

Vee = MAX,

VI=2.7V

20

20

IJA

IlL

Low-level input current

Vee = MAX,

VI = 0.4 V

-0.4

-0.4

mA

lOS

Short-circuit output current§

Vee = MAX

-130

mA

lee

Supply current

Vee = MAX,

30

mA

-30
See Note 2

-130
17

-30

30

17

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output shouid be shorted at a time.
NOTE 2: ICC is measured with all outputs open; clear grounded following momentary connection to 4.5 V; N, G 1. G2, and all data inputs
grounded; and the clock input and Mat 4.5 V.

switching characteristics, Vee

= 5 V, TA = 25°e, RL = 667 n

PARAMETER

TEST CONDITIONS

f max

Maximum clock frequency

tPHL

Propagation delay time, high-to-Iow-Ievel output from clear input

tPLH

Propagation delay time, low-to-high-Ievel output from clock input

tPHL

Propagation delay time, high-to-Iow-Ievel output from clock input

tpZH
tpZL
tPHZ

Output disable time from high level

tPLZ

Output disable time from low level

MIN TYP MAX UNIT
30

50

MHz

20

30

eL=45pF,

16

29

See Note 4

20

30

Output enable time to high level

13

21

Output enable time to low level

24

36

eL=5pF,

11

17

See Note 4

15

23

ns
ns
ns
ns

NOTE 4: Load circuits and voltage waveforms are shown on page 3-11.

1076
DESIGN GOAL

7-252

This page provides tentative information on a
product in the developmental stage. Texas
I nstruments

reserves

the right to change or dis-

continue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175,
SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175
H-EX/QUADRUP~~D-TYPE FLIP-FLOPS WITH CLEAR
DECEMBER 1972-REVISED OCTOBER 1976

BULLETIN NO. DL·S 7611

'174, 'LS174, 'S174 ... HEX D-TYPE FLIP-FLOPS
'175, 'LS175, 'S175 ... QUADRUPLE D-TYPE FLIP-FLOPS
•

'174, 'LS174, 'S174 Contain Six Flip-Flops
with Single-Rail Outputs

•

'175, 'LS175, 'S175 Contain Four Flip-Flops
with Double-Rail Outputs

•

Three Performance Ranges Offered: See
Table Lower Right

•

Buffered Clock and Direct Clear Inputs

•

Individual Data Input to Each Flip-Flop

•

Applications include:
Buffer/Storage Registers
Shift Registers
Pattern Generators

SN54174, SN54LS174, SN54S174 ... J OR W PACKAGE
SN74174, SN74LS174, SN74S174 ... J OR N PACKAGE
(TOP VIEW)

Vee

6Q

60

50

50

40

4Q

CLOCK

IUL~,..,n

IU

iQ

2D

2Q

3D

30

GNU

description
These monolithic, positive-edge-triggered flip-flops
utilize TTL circuitry to implement D-type flip-flop
logic. All have a direct clear input, and the '175,
'LS175, and 'S175 feature complementary outputs
from each flip-flops.

positive logic: see function table

SN54175, SN54LS175, SN54S175 •. , J OR W PACKAGE
SN74175, SN74LS175, SN74S175 ... J OR N PACKAGE
(TOP VIEW)

Information at the D inputs meeting the setup time
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and is
not directly related to the transition time of the
positive-going pulse. When the clock input is at either
the high or low level, the D;input signal has no effect
at the output.

Vce

40

40

40

30

30

30

CLOCK

•

These circuits are fully compatible for use with most
TTL or DTL circuits.
FUNCTION TABLE
CLEAR

(EACH FLIP-FLOP)
D

Q

Qt

L

X

X

L

H

H

H

H

L

H

t
t

L

L

H

H

L

X

Qo

00

CLEAR CLOCK

10

10

10

20

L
X

= irrelevant

t = transition
Q

O

= the

20

GNO

positive logic: see function table

TYPICAL

= high level (steady state)
= low level (steady state)

H

20

OUTPUTS

INPUTS

TYPES

TYPICAL

MAXIMUM

POWER

CLOCK

DISSIPATION

FREQUENCY PER FLIP-FLOP
from low to high level

level of Q before the indiCated steadY'state

input conditions were established.

t = '175, 'LS175, and 'S175 only

'174, '175

35MHz

'LS174, 'LS175

40MHz

14mW

110MHz

75mW

'S174, 'S175

38mW

1076 .

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-253

TYPES SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175,
SN74174, SN74175, SN74LS174, SN74LS175,SN74S174, SN74S175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
functional block diagrams
'174, 'LS174, 'S174

10..;.13;;;.l_ _ _ _ _ _-I

'175, 'LS175, 'S175

10

20

-+-+-I

...;,14.;;..l_ _ _ _

20

20

-+-+-I

30 ...;,16;.;..l_ _ _ _

14l

15l

20

30

(12)

(10)

3D

40

•

111l

30

40

(15)
40

50

..:..(1;;:;:3):..-._ _ _---+-I-~

40

50

(14)

40

CLEAR

60

...;,1,;.;,14;..,.l_ _ _ _+--1-1

60

I
I

--¢> ...

dynamic input activated by transition from a high level to a low level.

I

I
1272

7-254

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54174, SN54175, SN54LS174, SN54LS175, SN54S174, SN54S175,
SN74174, SN74175, SN74LS174, SN74LS175, SN74S174, SN74S175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
REVISED OCTOBER 1976

schematics of inputs and outputs

SN54174,SN54175,SN74174,SN74175
__----------------------------___

r---~--------------------------~
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF ALL INPUTS

---VCC
VCC--e__-

INPUT
OUTPUT

Clock, D: Req
Clear: Req

=8
=4

II

k.\1 NOM
k.\1 NOM

rh

------------"

~--~

SN54LS174,SN54LS175,SN74LS174,SN74LS175
__------------------------------_

r----~~----------------------__,
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF ALL INPUTS

VCC~--

--aVCC
120.\1

Req

INPUT

NOM
--

W

'---+--OUTPUT

II

Clock: Req = 17 k.\1 NOM
Clear, D: Req = 20 k.\1 NOM

SN54S174, SN54S175, SN74S174, SN74S175,.

~-------E-Q-UI-V-AL-E-N-T~b-FA-L-L-IN-P-U-TS---------

r-----~--T~Y~P~IC-AL-O~F~A-L-L-O~UT~P~U~TS~-------,

- - - - - - : : - + - - V CC
V cc-----4..---

INPUT
'---+--OUTPUT

1076

TEXAS INSTRUMENTS
INCORPORATED

POSi OFFICE BOX 5012

•

DAL.LAS. TEXAS 75222

1-255

TYPES SN54174, SN54175, SN74174, SN74175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage
Operating free-air temperature range: SN54174, SN54175 Circuits
SN74174, SN74175 Circuits
Storage temperature range

7V

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions

Supply voltage, Vee

SN54174, SN54175

SN74174, SN74175

MIN

MAX

MIN

NOM

5.5

4.75

5

NOM

4.5

5

'High-Ievel output current, 10H

-800

Low-level output current, 10L

16

Clock frequency, fclock

0

Width of clock or clear pulse, tw

I Data input
I Clear inactive-state

Setup time, tsu

0

UNIT

5.25

V

-SOO

IlA

16

mA

25

MHz

20

20

ns

20

20

ns

25

25

ns

5

5

ns

Data hold time, th
Operating free-air temperature, T A

25

MAX

-55

125

0

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

TEST CONDITIONSt

TYP:f:

MAX

2

VOH High-level output voltage

•

MIN

Vee= MIN,

11=-12mA

Vee= MIN,

VIH = 2V,

VIL = O.S V,

10H = -SOOIlA

Vee = MIN,

VIH = 2 V,

2.4

UNIT
V

O.S

V

-1.5

V

3.4

V

VOL

Low-level output voltage

VIL = O.S V,

10L = 16 mA

II

I nput current at maximum input voltage

Vee = MAX,

VI=5.5V

IIH

High-level input current

Vee = MAX,

VI = 2.4 V

40

Il A

IlL

Low-level input current

Vee = MAX,

VI = 0.4 V

-1.6

mA

lOS

Short-circuit output currentS

Vee = MAX

lee

Supply current

Vee = MAX,

See Note 2

0.2

0.4
1

I SN54'

-20

-57

I SN74'

, -18

-57

I1'174
'175

45

65

30

45

V
mA

rnA
rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values are at Vee

=5

V, T A

= 25° e.

§ Not more than one output should be shorted at a time.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, lec is measured after a momentary ground, then 4.5 V, is
applied to clock.

switching characteristics, Vee

= 5 V, TA = 25°e
PARAMETER

f max

TEST CONDITIONS

Maximum clock frequency
Propagation delay time, low-to-high-Ievei output from clear

tPLH

(SN54175, SN74175 only)

tpHL

Propagation delay time, high-to-Iow-Ievel output from clear

tpLH

Propagation delay time, low-to-high-Ievel output from clock

eL=15pF,
RL=400n,
See Note 3

tpHL Propagation delay time, high-to-Iow-Ievel output from clock

MIN

TYP

25

35

MAX UNIT
MHz

16

25

ns

23

35

ns

20

30

ns

24

35

ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-256

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS174. SN54LS175, SN74LS174, SN74LS175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
.............. .
Input voltage . . . . . . .
.............. .
Operating free-air temperature range: SN54LS174, SN54LS175 Circuits
SN74LS174, SN74LS175 Circuits
Storage temperature range

7V
7V

-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS174

SN74LS174

SN54LS175
Mll\I
Supply voltage, VCC

4.5

5

High-level output current, 10H

UNIT

SN74LS175

NOM MAX
5.5

MIN

NOM MAX

4.75

5

-400

Low-level output current, 10L

5.25

V

-400

jl.A

8

mA

4

Clock frequency, fclock

0

Width of clock or clear pulse, tw
Setup time, tsu

30

30 MHz

0

20

20

ns

I Data Input

")1'\

")1'\

...

I Clear inactive-state

25

25

ns

5

5

Data hold time, th

-55

Operating free-air temperature, T A

125

0

70

ns
DC

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LS174
SN54LS175

TEST eONDITIONSt

PARAMETER

MIN
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

VOL

High-level output voltage

Vee; MIN,

i l ; -18mA

Vee; MIN,

VIH;2V,

2.5

VIL;VILmax,IOH;-400!LA
Vec; MIN,

Low-level output voltage

VIH;2V,

VIL; VIL max
Vec; MAX,

VI;7 V

Vee; MAX,

VI; 2.7 V

IlL

Low-level input current

Vee; MAX,

VI; 0.4 V

lOS

Short-circuit output current§

Vce; MAX

lee

Supply current

Vee; MAX,

maximum input voltage

V

0.7

0.8

V

-1.5

-1.5

V

3.5

-20
See Note 2

UNIT

TYP:j: MAX

2

0.25

IIOL;4 mA

MIN

2.7
0.4

IIOL; 8mA

High-level input current

IIH

TYP:j: MAX

2

Input current at
II

SN74LS174
SN74LS175

V

3.5
0.25

0.4

0.35

0.5

V

0.1

0.1

mA

20

20

!LA

-0.4

-0.4

mA

-100 -20

-100

mA

I'LS174

16

26

16

26

I 'LS175

11

18

11

18

•

mA

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
D
:j:AII typical values are at Vce; 5 V, T A = 25 e.
§ Not more than one output should be shorted at a time, and duration of the short·circuit should not exceed one second.
NOTE 2: With all outp'uts open and 4.5 V applied to all data and dear inputs, lee is measured after a momentary ground, then 4.5 V, is
applied to clock.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

f max Maximum clock frequency
Propagation delay time, low-to-high-Ievel output from clear
tPLH (SN54LS175, SN74LS175 only)

CL = 15pF,
RL=2kn,

tPHL Propagation delay time, high-to-Iow-Ievel output from clear

See Note 4

tPLH Propagation delay time, low-to-high-Ievel output from clock
tpHL Propagation delay time, high-to-Iow-Ievel output from clock

MIN

TYP

30

40
16

MAX UNIT
MHz
25

ns

23

35

ns

20

30

ns

21

30

ns

NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-257

TYPES SN54S174, SN54S175, SN74S174, SN74S175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
absolute maximum ratings over operating free-air temperature_range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
............. .
Input voltage . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54S174, SN54S175 Circuits
SN74S174, SN74S175 Circuits
Storage temperature range

7V
5.5V
-55°C to 125°C
. aOc to 7aoC
-65°C to 15aoC

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54S174, SN54S175
I

Supply voltage, Vec

SN74S174, SN74S175

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

-1

mA

-1

High-level output current, 10H

20

Low-level output current, 10L

75

0

Clock frequency, fclock
Pulse width, tw
Setup time, tsu

0

Clock

7

7

Clear

10

10

Data input

5

5

Clear inactive-state

5

5

3

Data hold time, th

20

mA

75

MHz
ns
ns
ns

3

-55

Operating free-air temperature, T A

UNIT

MIN

125

°c

70

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER

•

VIH

High-level input voltage

V 11.,VIK

Low-level input voltage

VOH High-level output voltage
Low-level output voltage

TYP+

MAX

VCC; MIN,

II; -18mA

VCC; MIN,

VIH; 2 V,

I SN54S'

2.5

3.4

VIL; 0.8 V,

10H; -1 mA

ISN74S'

2.7

3.4

VCC; MIN,

VIH;2V,

VIL

= 0.8 V,

UNIT
V

2

Input clamp voltage

VOL

MIN

0.8

V

-1.2

V
V

0.5

10L; 20mA

V

II

Input current at maximum input voltage

VCC; MAX, VI; 5.5 V

1

IIH

High-level input current

Vce; MAX, VI;2.7V

50

IJ.A

IlL

Low-level input current

VCC

-2

mA

lOS

Short-circuit output current§

Vcc; MAX

-100

mA

lee

= MAX,

VI; 0.5 V
-40

Vec; MAX, See Note 2

Supply current

1'174

90

144

1'175

60

96

mA

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device

type.
+AII typical values are at Vee; 5 V, T A; 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is
applied to clock.

switching characteristics, Vee;:;:: 5 V, TA ;:;: 25°e
TEST CONDITIONS

PARAMETER
f max Maximum clock frequency
Propagation delay time, low-to-high-Ievel Q output from clear
tpLH

CL

(SN54S175, SN74S175 only)

See Note 3

tpHL Propagation time, high-to-Iow-Ievel output from clock
NOTE 3:

= 15pF,

RL;280n,

tpHL Propagation delay time, high-to-Iow-Ievel Q output from clear
tPLH Propagation delay time, low-to-high-Ievel output from clock

MIN

TYP

75

110

MAX UNIT
MHz

10

15

13

22

ns

8

12

ns

11.5

17

ns

ns

Load circuit and voltage waveforms are shown on page 3-10.

PR!NTED IN U.S A

7-258

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

1076

TYPES SN54176, SN54m, SN74176, SN74177
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES

TTL
MSI

BULLETIN NO. DL-S 7211478, MAY 1971-REVISED DECEMBER 1972

SN54176, SN54177 ••• J OR W PACKAGE
SN74176, SN74177 ••• J OR N PACKAGE
__ (TOP VI EW)

VCC CLEAR 0D

•

Reduced-Power Versions of SN54196, SN54197,
SN74196, and SN74197 50-MHz Counters

•

D-C Coupled Counters Designed to Replace Signetics
8280,8281,8290, and 8291 Counters in Most
Applications

•

Performs BCD, Bi-Quinary, or Binary Counting

•

Fully Programmable

•
•

Fully Independent Clear Input

•

Os

CLOCK
1

Guaranteed to Count at Input Frequencies
from 0 to 35 MHz
Input Clamping Diodes Simplify System Design
asynchronous input:

Low input to clear sets 0A,
OS, 0C, and 0D low.

description
These high-speed monolithic counters consist of four d-c coupled m"lster-slave flip-flops which are internally
interconnected to provide either a divide-by-two and a divide-by-five counter (SN54176, SN74176) or a divide-by-two
and a divide-by-eight counter (SN54177, SN74177). These counters are fully programmable; that is, the outputs may
be preset to any state by placing a low on the count/load input and entering the desired data at the data inputs. The
outputs will change to agree with the data inputs independent of the state of the clocks.
These counters may also be used as 4-bit latches by using the count/load input as the strobe and entering data at the
data inputs. The outputs will directly follow the data inputs when the count/load is low, but will remain unchanged
when the count/load is high and the clock inputs are inactive.

•

These high-speed counters will accept count frequencies of a to 35 megahertz at the clock-1 input and a to 17.5
megahertz at the clock-2 input. During the count' operation, transfer of information to the outputs occurs on the
negative-going edge of the clock pulse. The counters feature a direct clear which when taken low sets all outputs low
regardless of the states of the clocks.
All inputs are diode-clamped to minimize transmission-line effects and simplify system design. The circuits are
compatible with most TTL and DTL logic families. Typical power dissipation is 150 milliwatts. The SN54176 and
SN54177 circuits are characterized for operation over the full military temperature range of -55°C to 125°C; the
SN74176 and SN74177 circuits are characterized for operation from aOe to 70°C.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-259

TYPES SN54176. SN54ID. SN74176. SN741n
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
typical count configurations
SN54176 and SN74176

SN54176, SN74176
FUNCTION TABLES

The output of flip-flop A is not internally connected
to the succeeding flip-flops; therefore, the count may
be operated in three independent modes:

DECADE (BCD)

BI-aUINARY (5-2)

(See Note A)

1. When used as a binary·coded·decimal decade
counter, the clock-2 input must be externally
connected to the ~ output. The clock-1 input
receives the incoming count, and a count
sequence is obtained in accordance with the
BCD count sequence function table shown at
right.

(See Note B) .

OUTPUT

COUNT

2. If a symmetrical divide-by-ten count is desired
for frequency synthesizers (or other applications requiring division of a binary count by
a power of ten), the OD output must be
externally connected to the clock-1 input. The
input count is then applied at the clock-2 input
and a divide-by-ten square wave is obtained at
output OA in accordance with the bi-quinary
function· table.

aA aD ac aB
L
L
L
L

0

L

L

L

L

1

L

L

L

H

1

L

L

L

2

L

L

H

L

2

L

L

H

L

3

L

L

H

H

3

L

L

H

H

4

L

H

L

L

4

L

H

L

L

5

L

H

L

H

H

L

L

L

6

L

H

H

L

5
6

H

L

L

H

7

L

H

H

H

L

H

L

H

L

L

L

7
8

H

8

H

L

H

H

H

L

L

H

9

H

H

L

L

9
H

OUTPUT

COUNT

aD ac aB aA

= high

level, L

0

H

= low level

NOTES: A. Output QA connected to clock-2 input.
B. Output QO connected to clock-1 input.

3. For operation as a divide-by-two counter and a divide-by-five counter, no external interconnections are required.
Flip-flop A is used as a binary element for the divide-by-two function. The clock-2 input is used to obtain binary
divide-by-five operation at the OB, OC, and OD outputs. In this mode, the two counters operate independently;
however, all four flip-flops are loaded and cleared simultaneously.

•

SN54177, SN74177

SN54177 and SN74177

FUNCTION TABLE
(See Note A)

The output of flip-flop A is not internally connected to the succeeding flip-flops,
therefore the counter may be operated in two independent modes:

1. When used as a high-speed 4-bit ripple-through counter, output OA must be
externally connected to the clock-2 input. The input count pulses are applied to
the clock-1 input. Simu Itaneous divisions by 2, 4, 8, and 16 are performed at the
OA, OB, Qc, and OD outputs as shown in the function table at right.

COUNT
I

2. When used as a 3-bit ripple-through counter, the input count pulses are applied
to the clock-2 input. Simultaneous frequency divisions by 2, 4, and 8 are
available at the OB, OC, and OD outputs. Independent use of flip-flop A is
available if the load and clear functions coincide with those of the 3-bit
ripple-through counter.

H

OUTPUT

aoacas

aA

0

'L

L

L

L

1

L

L

L

H

2

L

L

H

L

3

L

L

H

H

4

L

H

L

L

5
6

L

H

L

H

L

H

H

L

7

L

H

H

H

8

H

L

L

L

9

H

L

L

H

10

H

L

H

L

11

H

L

H

H

12

H

H

L

L

13

H

H

L

H

14

H

H

H

L

15

H

H

H

H

= high

level, L

= low

level

NOTE A: Output QA connected
to clock-2 input.

1272

1-260

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DAL.L.AS, TEXAS 75222

TYPES SN54176, SN54m, SN74176, SN74177
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
functional block diagrams

.,

o

Q

"

o

o

§

§

~

.....
.....
.....
z
en

:;;:

~.
:;;:

I

~

1~I+I--,+I---4~--~---+~------~~------~

. oRf.l
.,

u

o
§

Q

o

o

§

§

1

~

~

E
CD

.,

«

rj

0

>-

""

m

~

rj

a:

M.

~

u

0

,

"'"

>-

J~

~~

/\

J

~~

~~

'"
m

1]

11

10

0

,

Q

J

(""

Q

Q

0

"'"

~

s

1
.r::

OJ

:c

•

CD

E

.g
c
0

";;

"!
>

.0

e
~

~
:J

C.
C

"~"
>

~

"0

~

§

-

--+--

1272

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-261

TYPES SN54176, SN54m, SN74176, SN741n
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
schematics of inputs and outputs
EQUIVALENT OF COUNT/LOAD,
CLEAR, AND DATA INPUTS

EQUIVALENT OF CLOCK INPUTS

TYPICAL OF ALL OUTPUTS

--+-_VCC

VCC----+------

OUTPUT

Data, Count/load: Req
Clear: Req

=4
=2

kn NOM
kn NOM

INPUT
Clock 1
Clock 2

NOMINAL VALUES OF
R1, R2, and R3
'176
'177
4 kn
4 kn
4 kn
6 kn

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

7V
5.5 V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Supply voltage, VCC (see Note 1)
Input voltage . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54176, SN54177 Circuits
SN74176, SN74177 Circuits
Storage temperature range
NOTES:

•

1. Voltage values are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the clear and
countlload inputs .

recommended operating conditions
MIN
, Supplv voltage.

SN54'

Vee
I

SN74'

NOM MAX

4.5
, 47r::.
.

-

5

-

UNIT

5.5

V

-.-

High-level output current, IOH

-800 I

/lA

low-level output current, IOl

16

mA

Count frequency (see Figure 1)

Pulse width, tw (see Figure 1)

Input hold time, th (see Figure 1)
Input setup time, tsu (see Figure 1)

Clock-1 input

0

35

Clock-2 input

0

17.5

Clock-1 input

14

Clock-2 input

28

Clear

20

load

25

High-level data

tw(load)

low-level data
High-level data

tw(load)
15

low-level data

20

I

Operating free-air temperature, T A

ns

ns
ns

25

Count enable time, tenable (see Note 3 and Figure 1)

MHz

ns

SN54'

-55

125

SN74'

0

70

°c

NOTE 3' Minimum count enable time is tl1e interval immediatelv preceding the negative-going edge of the clock oulse during which interval the
count/load and clear inputs must both be high to ensure counting,

1272

7-262

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 15222

TYPES SN54176, SN54ffl, SN74176, SN74177
35-MHz PRESETTABLE DECADE AND
BINARY COUNTERS/LATCHES
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

SN54176, SN74176 SN54117, SN74117

TEST CONDITIONSt

PARAMETER

MIN

TYP:j: MAX

VIK

I nput clamp voltage
High-level output voltage

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH

High-level input current Clear, clock 1

VCC- MIN,

11--12mA

VCC = MIN,

V!H=2V,

VIL = 0.8 V,

IOH = -800/lA

VCC= MIN,

VIH = 2 V,

VIL = 0.8 V,

IOL = 16 mA~

0.2

VI = 2.4 V

Clock 2

IlL

0.2

1

I Glock 2
~.

1

40

40

80

80

120

80

-4.~

I SN54,1-20

iOS

Short-circuit output currentS

VCC = iviAX

ICC

Supply current

VCC = MAX, See Note 4

SN74'

-18
30

0.4

1

V

V
rnA
/lA

-11>

~;
1
-4.8

VCC = MAX, VI = 0.4 V

Clock 1

0.4

V

V

3.4

-11>

Data, count!!oad
Clear

2.4

VCC- MAX, VI - 5.5 V
VCC= MAX,

-1.5

3.4

UNIT
V

0.8

-1.5
2.4

Data, count/load

1

TYP:j: MAX

2
0.8

VOH

Low-level input current

MIN

2

-;;1
-4.8

rnA

1

I

-57

-20

-57

-18

48

30

NOTE 4: I ee is measured with all inputs grounded and all outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°e.
~ QA outputs are tested at IOL

= 16 mA

plus the limit value of II L for the clock-2 input. This permits driving the clock-2 input while fanning

out to 10 Series 54/74 loads.

§ Not more than one output shou Id be shorted at a time.

switching characteristics, Vee

= 5 V, RL = 400 il, eL = 15 pF, TA = 25°e, see figure

PARAMETERO

FROM (INPUT)

TO (OUTPUT)

f max

Clock 1

QA

Clock 1

QA

Clock 2

QS

tPLH
tpHL
tPLH
tpHL
tpLH

Clock 2

QC

Clock 2

QD

tpHL

1

SN54176, SN74176 SN54117, SN54117
MIN

TYP

35

50

MAX

MIN

TYP

35

50

MAX

MHz

8

13

8

13

11

17

11

17

11

17

11

17

17

26

17

26

27

41

27

41

34

51

34

51
66

13

20

44

tPHL

17

26

50

75

tpLH

19

29

19

29

31

46

31

46

tpLH

A,S,C,D

QA, QS, QC, QD

Load

Any

Clear

Any

tpHL
tpLH
tpHL
tpHL

I

UNIT

29

43

29

43

32

48

32

32

48

32

48
48

ns
ns
ns
ns
ns
ns
ns

Of max "" maximum count frequency
tPLH
tpH L

== propagation
== propagation

delay time, low-to~high-Ievel output
delay time, high-to-Iow-Ievel output

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

OALLAS. TEXAS 75222

7-263

iii

......
N

...

C)

~ tW(CIOCkl..,

~~ ~, -

CLOCK-' OR

VCC

CI:IW~

-

-

-

3.5 V

I

I

t.-----.f- tPHL
LOAD CIRCUIT

---------\j.~

OUTPUT

0A, 0B. DC, or 00

I

INPUT

I

- - VOL

- - --

OUTPUT

"'ID

o

-

i

cm~

Zcn~

~mcn
m~ ..

OV

::D~cn

VOH

°A

,.5 V

cn;;Z

"tI

VOL

CLOCK ENABLE TIME VOLTAGE
WAVEFORMS

CLOCK-MODE VOLTAGE WAVEFORMS

['1'1

><

1

-I "0,,,,10--

VOH

- - - - - VOL

~

------3.5V

1,.5V

'.5 V

__________~I----~

::D:ccn
-
(J)

,----------------------------------------------------------------------3.5V
CLEAR

Z_

-- -- -

-

0"";

-

t-

tsu

:

DATA INPUTS
A, B, C, AND 0

-

--1

- - - - - - - - - - - - - - - - - - - ------OV
3.5 V

I
I
1

03:

I

I~-----OV

I

['1'1

I

_.J. I
I

-1- -

z
....;

I

COUNT/LOAD
INPUT

(J)

I"---J:~

I
-I tPHL"--

I
--.... tPLH
I

toe--

----"'\1
OUTPUTS
0A, 0B, DC, AND 00

"\L,.5
\

V

T.'.v

'.5 V .

.....

J--

tPHL
I

,

\L,.5 V

1

\

-

-

-

-

s:

-..j tPLH

FIGURE 1

<

5 ns, and unless

:J:It

Z ..cn

~

S

m
2

o

::xl

»
-I

o
Z

CLEAR AND LOAD VOLTAGE WAVEFORMS

m~
.~

acn

::xl

S

VOH

ncn
cn a .....

m

2

I '.5 V

:C m

m:J:lt'Z

c

-I

OV

~I.

NOTES: A. The input pulse is supplied by a genorator having the following characteristics: PRR .;; , MHz, duty cycle';; 50%, tr
specified, tf < 5 ns. When testing f max , vary PRR.
B. CL includes probe and jig capacitance.
C. All diodes are' N3064.
D. Unless otherwise specified, QA is connected to clock 2.

Cf)

3.5 V

t.--..j tpHL 14I

'.5 V I

»

"T1

I

I

r

-

- - - VOL

::lCI'>

::xl

m

~8Z
~~(J)

~;o
~c::

m

--,...U"I
;:m~
~a9
n
..

Z

9

TTL
MSI

TYPES SN54178, SN54179, SN74178, SN74179
4-81T PARALLEL-ACCESS SHIFT REGISTERS
BULLETIN NO. DL·S 7211846, DECEMBER 1972

•

Typical Maximum Clock Frequency ... 39 MHz

•

Three Operating Modes:
Synchronous Parallel Load
Right Shift
Hold (Do Nothing)

SN54178 ••• J OR W PACKAGE
SN74178 •.• J OR N PACKAGE
(TOP VIEW)
INPUTS

VCC

~

SHI FT

OUTPUT
OUTPUT
QD LOAD Oc

8

•

Negative-Edge-Triggered Clocking

•

D-C Coupling Symplifies System Designs

description
These shift registers utilize fully d·c coupled storage
elements and feature synchronous parallel inputs and
parallel outputs. The SN54179/SN74179 has a direct
clear line and complementary output from the D
flip-f!op, thereby differing from the SN54178/
SN74178.

~ SERIAL

QA CLOCK Qs
GND
IN OUTPUT
OUTPUT

INPUTS

positive logic: see fu nction table

Parallel loading is accomplished by taking the shift
input low, applying the four bits of data, and taking
the load input high. The data is loaded into the
associated flip·flop synchronously and appears at the
outputs after a high·to-Iow transition of the clock.
During loading, serial data flow is inhibited.

C'F\.II:.JI1 "7Q
o.I'.,...,roT1
I.J

~

I n
D lAI
'-".1
•• IDJ\""VA~~
__

• • 0.1

I'_~""

SN74179 •.• J OR N PACKAGE
INPUTS

~

VCC

OUTPUTS

~

SHIFT

LOAD

ou
:

UT

9

Shift right is also accomplished on the falling edge of
the clock pulse when the shift input is high regardless
of the level of the load input. Serial data for this
mode is entered at the serial data input.
When both the shift and load inputs are low, clocking
of the register can continue; however, data appearing
at each output is fed back to the flip·flop input
creating a mode in which the data is held unchanged.
Thus, the system clock may be left free·running
without changing the contents of the register.

positive logic: see function table

I

'178, '179 t
FUNCTION TABLE
OUTPUTS

INPUTS
PARALLEL
CLEARt SHIFT LOAO CLOCK SERIAL
L

H
H
H
H
H

X
X
IX-X-

I
I
I
I
I

-HX- -XX-

A

B

C

-X

X

X X
X X

0

°A

OB

Oc

00

L

L

X

L

L

X

QAO

QBO

QCO QDO



Denotes input activated by a transition from a high ;evs! to a

~o ...'V

fevel.

I

I

schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

---4___- - Vee

Vcc---......- - -

INPUT
OUTPUT

1272

7-266

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54178, SN54179, SN74178, SN74179
4-81T PARALLEL-ACCESS SHIFT REGISTERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
............ .
Input voltage . . . . . . .
............ .
Operating free-air temperature range: SN54178, SN54179 Circuits
SN74178, SN74179 Circuits
Storage temperature range

7V

5.5 V
-55°C to 125°C
. O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54178, SN54179

SN74178, SN74179

MIN
4.5

Supply voltage, Vee

MAX

M!N

NOM

MAX

5

5.5

4.75

5

5.25

V

-800

/LA

-800

High-level output current, 10H

io

Low-level output current, 10L
0

elock frequency. fc!ock
Width of clock or clear pulse, tw (see Figure 1)

Setup time, tsu (see Figure 1)

25

0

20

20

Shift (H or L) or load

35

35

Data

30

30

15

15

elear-inactive-state
(SN54179 and SN74179)

Hold time at any input, th

i6

rnA

25

MHz
ns

ns

ns

5

5
-55

Operating free-air temperature, T A

UNIT

NOM

125

0

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low·level input voltage

VIK

Input clamp voltage

VOH

H igh·level output voltage

VOL

SN54178. SN54179

SN74178. SN74179

MIN

MIN

TYP:j:

MAX

2

2
Vee; MIN,

Low-level output voltage

II; -12mA

Vee; MIN,

VIH; 2V,

VIL; 0.8 V,

10H; -800/LA

Vee- MIN,

VIH-2V,

VIL; 0.8 V,

10L; 16 rnA

2.4

TYP:j: MAX

V

0.8

0.8

V

-1.5

-1.5

V

2.4

3.4
0.2

UNIT

V

3.4
0.2

0.4

0.4

V

II

I nput current at maximum input voltage

Vee; MAX,

VI; 5.5 V

1

1

IIH

High-level input current

Vee; MAX,

VI; 2.4 V

40

40

/LA

IlL

Low-level input current

Vee; MAX,

VI; 0.4 V

-1.6

-1.6

rnA

lOS

Short-circu it output current §

Vee; MAX

lee

Supply current

Vee; MAX, See Note 2

-20

-57

46

70

-18

46

•

mA

-57

rnA

75

rnA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions for the applicable device

type.
tAli typical values are at Vee; 5 V, T A; 25°e.

§ Not more than one output should be shorted at a time.
NOTE 2: lee is measured as follows:
a) 4.5 V is applied to serial inputs, load, shift, and clear,
b) Parallel inputs A through Dare gounded,
c) 4.5 V is momentarily applied to clock which is then grounded.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-267

TYPES SN54178, SN54179, SN74178, SN74179
4-81T PARALLEL-ACCESS SHIFT REGISTERS
switching characteristics, Vee
PARAMETER~

=5 V, TA =25°e

FROM

TO

(lNPun

(OUTPUT)

TEST CONDITIONS

MIN

TYP

25

39

f max

tpLH

°D
0A, 0B, 0C, 0D

Clear

tpHL
tPLH

Clock

CL=15pF,

RL = 400

n,

See Figure 1

Any output

tpHL

MAX UNIT
MHz

15

23

24

36

17

26

23

35

ns
ns

~fmax'; Maximum clock frequency
tpHL'; Propagation delay time, high-to-Iow-Ievel output
tpLH ';Propagation delay time, low-to-high-Ievel output

PARAMETER MEASUREMENT INFORMATION
OUTPUT

VCC

FROMOUTPUT __~___-M__~__~~~~~~~
UNDER TEST
CL = 15pF
(See Note C)

l'
'::'

LOAD CI RCUIT

14- tw(clearl-J

j:'5 ~ _____________________

~ 1.5 V

CLEAR

I

~1.5V
I.--

SHIFT

I

I
:

LOAD

%1.5 V
tsu

I
:

CLOCK

I

t
SU

0V

4~~--------------:~
I

~ ~ ;-:-- -

I I -

-:::
/,1.5V

--"'1--" ~
I
I
I

!

tsu . .....;

--oooil~· 14--

DATA
(See Note B)

~tsu

3 V

-

-

-

-- -

-

-- -- -

I

'-t h

!

II

rI

3V

0V

:~ ~;:----- -- - - - - - - - 3 V

-::I

. . . th

I

I

t
su

1.5 V

0V

~

T-------

3V

I ----.---

0 V

1.5 V

____-+_J

----------:-t--1.5V~
!.-tPHL.....

° OUTPUT
(See Note B)

VOH

. " - - VOL

VOLTAGE WAVEFORMS

NOTES:

A. Input pulses are supplied by generators having the following characteristics: tTLH';;; 10 ns, tTHL';;; 10 ns, PRR';;; 1 MHz,
Zout '" 50

n.

B. Data input and

Q output are any related pair. Serial and other data inputs are at GND. Serial data input is tested in conjunction

with QA output in the shift mode.
C. CL includes probe and jig capacitance.
D. All diodes are 1 N3064.

FIGURE 1-SWITCHING TIMES

1076

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TEXAS INSTRUMENTS
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•

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TTL

TYPES SN54180, SN74180
9-81T ODD/EVEN PARITY GENERATORS/CHECKERS

MSI

BULLETIN NO. DL-S 7211814, DECEMBER 1972

SN54180 .•. J OR W PACKAGE
SN74180 .•• J OR N PACKAGE
(TOP VIEW)

logic
FUNCTION TABLE
OUTPUTS

INPUTS
Z;

OF H'sAT

A THRU H

= high

~

EVEN ODD

EVEN

H

L

H

L

ODD

H

L

L

H

EVEN

L

H

L

H

ODD

L

H

H

L

X

H

H

L

L

L

H

H

X
H

Z;

EVEN ODD

level, L

= low

L
level, X

= irrelevant

'----"---~EVEN
- . . r - INPUT
INPUTS

ODD

~·EveN

~·ODD

INPUT OUTPUT OUTPUT

positive logic: see function table

description
These universal, monolithic, 9-bit (8 data bits plus 1 parity bit) parity generators/checkers, utilize familiar Series 54/74
TTL circuitry and feature odd/even outputs and control inputs to facilitate operation in either odd- or even-parity
applications. Depending on whether even or odd parity is being generated or checked, the even or odd inputs can be
utilized as the parity or 9th-bit input. The word-length capability is easily expanded by cascading.
The SN54180/SN74180 are fully compatible with other TTL or DTL circuits. Input buffers are provided so that each
data input represents only one normalized series 54/74 load. A full fan-out to 10 normalized series 54/74 loads is
available from each of the outputs at a low logic level. A fan-out to 20 normalized loads is provided at a high logic level
to facilitate the connection of unused inputs to used inputs. Typical power dissipation is i70 mW.
The SN54180 is characterized for operation over the full military temperature range of -55°C to 125°C; and the
SN74180 is characterized for operation from O°C to 70°C.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V

Supply voltage, V CC (see Note 1)
....... .
Input voltage . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54180 Circuits
SN74180 Circuits
Storage temperature range

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74180

SN54180
MIN
4.5

Supply voltage, Vee

NOM
5

MAX

MIN

5.5

4.75

-800

High-level output current, IOH

16

Low-level output current, IOL
-55

Operating free-air temperature, T A

125

a

NOM
5

MAX

UNIT

5.25

V

-800

/lA

16

mA

70

°e

1076

TEXAS INSTRUMENTS
INCORPORATED

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•

DALLAS. TEXAS 75222

7·269

II

TYPES SN54180, SN74180
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONSt

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH

High-level input current

IlL

Low-level input current

SN54180
MIN

TYPt

SN74180
MAX

2

MIN

TYPt

II = -12mA

Vee - MIN,

VIH - 2 V,

VIL=0.8V,

10H = -800 IlA

Vee

MIN,

-1.5
2.4

VIH - 2 V,

VIL = 0.8 V,

3.3
0.2

10L = 16 rnA

2.4
0.4

Any data input

Vee=MAX, VI = 2.4 V

Even or odd input
Any data input

VI = 0.4 V

Vee = MAX,

Even or odd input

lOS

Short-circuit output current§

Vee = MAX

lee

Supply current

Vee = MAX, See Note 2

-1.5

V

0.2

V
0.4
1

40

40

80

80

-1.6

-1.6

-55
34

V

3.3

-3.2

-3.2
-20

0.8

1

Vee- MAX, VI- 5.5V

-18
34

49

UNIT
V

0.8
Vee= MIN,

MAX

2

V
rnA
IlA
rnA

-55

rnA

56

rnA

NOTE 2: ICC is measured with even and odd inputs at 4.5 V, all other inputs and outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
tAli typical values are at VCC

=5

V, T A

= 25°C.

§ Not more than one output should be shorted at a time.

switching characteristics, Vee = 5 V, TA =25° C
PARAMETER 11
tpLH

FROM

TO

(INPUT)

IOUTPUT)
~

Data

TEST CONDITIONS

Even

tpHL

eL = 15pF,

tpLH

Odd input grounded, See Note 3

Data

~Odd

Data

~

RL = 400 n,

tPHL
tPLH

II

Even

tpHL

eL = 15pF,

tPLH

Even input grounded, See Note 3

~

Data

tpHL
tpLH

~

Even or Odd

tpHL

NOTE 3: Load circuits and wavefonns are shown on

Odd

Even or

p~9a

~

Odd

CL = 15 pF,
See Note 3

RL=400n,

RL=4oon,

MIN

TYP

MAxi UNIT

40

60

45

68

32

48

25

38

32

48

25

38

40

60

45

68

13

20

7

10

ns
ns
ns
ns
ns

3-10.

11 tp LH == Propagation delay time, low-to-high-Ievel output
tPH'L== Propagation delay time, high-to-Iow-Ievel output

functional block diagram and schematics of inputs and outputs
TYPICAL OF BOTH
OUTPUTS

EQUIVALENT OF
EACH INPUT

vcc3-Req

INPUT

Data inputs:
Even and odd:

--

Req
Req

= 4 k.n
= 2 kn

1076

7-270

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54181, SN54LS181, SN54S181,
SN74181, SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

TTL
MSI

BULLETIN NO. DL-S 7611831, DECEMBER 1972 -

REVISED OCTOBER 1976

SN54181, SN54LS181, SN54S181 ..• J OR W PACKAGE
SN74181, SN74LS181, SN74S181 •.. J OR N PACKAGE
(TOP VIEW}

•

Full Look-Ahead for High-Speed
Operations on Long Words

•

Input Clamping Diodes Minimize
Transmission-Line Effects

•

Darlington Outputs Reduce 7urn-Off
Time

•

Arithmetic Operating Modes:
Addition
Subtraction
Shift Operand A One Position
Magnitude Comparison
Plus Twelve Other Arithmetic
Operations

•

Logic Function Modes:
Exclusive-OR
Comparator
AND, NAND, OR, NOR
Plus Ten Other Logic Operations

iogic: see tabies

"j

and 2

TYPICAL ADDITION TIMES
PACKAGE COUNT

ADDITION TIMES

NUMBER

CARRY METHOD

OF

USING '181

USING 'LS181

USING'S181

ARITHMETIC/

LOOK-AHEAD

BITS

AND '182

AND '182

AND'S182

LOGIC UNITS

CARRY GENERATORS

1 to4

24 ns

24 ns

11 ns

1

NONE

5to 8

36 ns

40ns

18 ns

2

RIPPLE

9 to 16

36 ns

44 ns

17 to 64

60 ns

68 ns

I

BETWEEN
ALU's

19 ns

30r4

1

FULL LOOK-AHEAD

28 ns

5 to 16

2 to 5

FULL LOOK-AHEAD

I

description
The '181, 'LS181, and 'S181 are arithmetic logic units (ALU)/function generators that have a complexity of 75
equivalent gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as
shown in Tables 1 and 2. These operations are selected by the four function-select lines (SO, S1, S2, S3) and include
addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries
must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead scheme is made
available in these devices for fast, simultaneous carry generation by means of two cascade-outputs (pins 15 and 17) for
the four bits in the package. When used in conjunction with the SN54182, SN54S182, SN74182, or SN74S182, full
carry look-ahead circuits, high-speed arithmetic operations can be performed. The typical addition times shown above
illustrate the little additional time required for addition of longer words when full carry look-ahead is employed. The
method of cascading '182 or 'S182 circuits with these ALU's to provide multi-level full carry look-ahead is illustrated
under typical applications data for the '182 and 'S182.
If high speed is not of importance, a ripple-carry input (C n ) and a ripple-carry output (C n+4) are available. However,
the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be
performed without external circuitry.

1076

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7-271

TYPES SN54181, SN54LS181, SN54S181,
SN74181, SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
description (continued)
The '181, 'LS181, and 'S181 will accommodate active-high or active-low data if the pin designations are interpreted as
follows:

PIN NUMBER
2
Active-low data (Table 1) AO
Active-high data (Table 2) AO

1

23

22

I 21 I 20 I 19

18

9

10

11

13

80
80

Al
A1

81 I A2 1 8 2 I A3
81 A2 82 A3

83
83

Fa
Fa

Fl
Fl

F2
F2

F3
F3

I

I

I

7

16

Cn Cn+4
Cn Cn +4

15

17

]5

G

X

y

Subtraction is accomplished by 1's complement addition where the 1's complement of the subtrahend is generated
internally_ The resultant output is A-8-1, which requires an end-around or forced carry to provide A-8.
The '181, 'LS181, or 'S181 can also be utilized as a comparator. The A = 8 output is internally decoded from the
function outputs (Fa, F 1, F2, F3) so that when two words of equal magnitude are applied at the A and 8 inputs, it will
assume a high level to indicate equality (A = 8)_ The ALU should be in the subtract mode with Cn = H when
performing this comparison. The A = 8 output is open-collector so that is can be wire-AND connected to give a
comparison for more than four bits. The carry output (C n+4) can also be used to supply relative magnitude
information. Again, the ALU should be placed in the subtract mode by placing the function select inputs S3, S2, Sl,
SO at L, H, H, L, respectively.

INPUT Cn OUTPUT Cn +4

ACTIVE-LOW DATA

ACTIVE-HIGH DATA

(FIGURE 1)

(FIGURE 2)

H

H

A;;'S

A<;;S

H

L

AS

L

H

A >S

A
n\./
v
V , u V - U u - V v,

Sl = S2 =,4.5 V (DIFF mode)

tPHL
AjorBj

tpHL
tPLH

I

tPLH

AjorBj

tpHL
tpLH

AnyAorB

I

Fj

AjorBj

tpHL

Fj

I

A=B

tpHL

12
12

10.5

15

10.5

15

7.5

12

7.5

12

IV.'"

15

10.5

15

11

16.5

11

16.5

14

20

Sl = S2 = 4.5 V (DIFF mode)

14

22

14

20

14

22

M = 4.5 V (logic mode)

Fj

8
7.5

a v, so = S3 = 4.5 v,
Sl = S2 = a v (SUM mode)
M = a v, so = S3 = a v,
M=

tPLH

10.5

12.5

Sl = S2 =

tpHL

10.5

7

18.5

M-

G

B

tpHL

MAX UNIT

12.5

-

Cn

tpHL

TYP

a v, so - S3 - 4.5 V,
Sl = S2 = a v (SUM mode)
M - a v, SO - S3 - a v,
M-

tpHL
tPLH

MIN

7

Cn

tpHL

TEST CONDITIONS

M=OV,SO=S3=OV,

15

23

Sl = S2 = 4.5 V (DIFF mode)

20

30

ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns

~tpLH == propagation delay time, low-to-high-!evel output
tpHL == propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-10.

•

schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

Vcc - - - - - - . - - - - -

TYPICAL OF ALL OUTPUTS
EXCEPT A = B

--~-------- VCC

I

ns

A =BOUTPUT

Vcc

OUTPUT

INPUT

1..---'-'--- 0 UTP UT

Mode control:
Any A or B:
Any S:
cn:

Req
Req
Req
Req

=
=
=
=

2.8 kDo NOM
940 Do NOM
700 Do NOM
560 Do NOM

1076

TEXAS INCORPORATED
INSTRUMENTS
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•

DALLAS. TEXAS 75222

7-279

TYPES SN54181, SN54LS181, SN54S181, SN74181, SN74LS181, SN74S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
functional block diagram
53
52
51
50

133 or B3

(3)
(4)
(5)
(6)

I
I

I

I
(17)

GorY

(18)

(16)

C n + 4 or

(;n+4

(15)
PorX
(19)
A3 or A3
(13) _
F3 or F3

(20)
132 or B2

(21)
A2 or A2

>---+--....:..:.(1.:..:...-1) F2 or F2

•

(22)

II ""

BlorBl

~A"

II

(23)

Al or Al---+-+-+-~-I

(10) _

>-+-+------'-- F 1 or F 1

(1)

BOor Bu

}----+-----.:(.:.;...9)

0 or FO

AO or AO_(2_)- - - " " " " * - - I

M _______________

.~

1076

7-280

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54181, SN54LS181, SN54S181, SN14181, SN14LS181, SN14S181
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
PARAMETER MEASUREMENT INFORMATION
SUM MODE TEST TABLE
FUNCTION INPUTS: SO =S3 =4.5 V. Sl =S2 = M
INPUT
PARAMETER

UNDER
TEST

Ai

OTHER DATA INPUTS

r-,.A-PP,.:~;:.;~:..::M.;:.E..::;~:.,:I~""L""y"---+-A-=-PP:-L-y:--r-A:--P-=-P-Ly---l
4.5 V

GND

Bi

None

Ai

Bi

None

4.5 V

None

None

None

None

A;

None

None

Ai

None

Bi

Bi

None

Ai

WAVEFORM
(See Note 41

GND

In-Phase

Fi

AandS

Ai

Bi

OUTPUT

UNDER
TEST

Remaining

Bi

None

OUTPUT

AandS

Bi

None

=0 V

Remaining

Ai

Ai

tPLH

OTHER INPUT

Remaining

In-Phase

A and B. Cn
Remaining

B

AandS,C n
Remaining
A,C n

Remaining

Remaining

Remaining

In-Phase
In-Phase
In-Phase

B

A,C n

All

All

Any F

A

B

or Cn +4

PARAMETER

OTHER DATA INPUTS

UNDER

APPLY

TEST

None

Ai
Ai

None

Si
None

B;
None

Ai

None

4.5V

GND
Remaining

tpLH

None

B;
B;

I

A
None

None

None

None

None

Remaining

Remaining

Out-ol-Phase

A andB, Cn
Remaining

In-Phase

AandS, Cn
Remaining

Out·ol·Phase

A andB,C n
Remaining

S,C n
Remaining

None

In·Phase

A andB, Cn

A

None

I Out.al-Phase

B,C n
Remaining

Remaining
Remaining

None

OUTPUT

In-Phase

B,C n
Remaining

Si

None

=0 V

OUTPUT

APPLY

Remaining

None

B;

In-Phase

I Out-ol-Phase
I Out-ol-Phase

DIFF MODE TEST TABLE
FUNCTION INPUTS: Sl =S2 =4.5 V. SO =S3 = M
INPUT

In-Phase

In-Phase

A=B

A
All

A andSNone

None

None

C n +4
or any F

Remaining

Out-ol Phase
In-Phase
Out-ol·Phase

A,B,C n
Remaining

In ·Phase

A,B,C n

LOGIC MODE TEST TABLE
FUNCTION INPUTS: Sl = S2 = M = 4.5 V. SO

•

= S3 = 0 V

OTHE'R INPUT
INPUT
PARAMETER

UNDER
TEST

tpHL

B;

OTHER DATA INPUTS OUTPUT
SAME BIT
f-A:-::P:::"P:-:Ly-'--':'-=A:-'P=P-:-Ly,,---'f--AP:-:::::"P"""Ly-'---'---AP--P"-L"-'y---1 UN DE R
4.5 V

GND

4.5 V

None

None

None

None

GND

TEST

OUTPUT
WAVE FORM
(See Note 41

Remaining

A andB, Cn
Remaining

A andB, Cn

Out-ol·Phase

NOTE 4: Load circuit and voltage waveforms are shown on pages 3-10 and 3-11.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-281

TTL

TYPES SN54182, SN54S182, SN74182, SN74S182
LOOK-AHEAD CARRY GENERATORS

MSI

BULLETIN NO. DL-S 7611823, DECEMBER 1972-REVISED OCTOBER 1976

•

Directly Compatible for Use With:

SN54182, SN54S182 ... J OR W PACKAGE
SN74182, SN74S182 ••• J OR N PACKAGE
(TOP VIEW)

SN54181/SN74181, SN54LS181/SN74LS181,
SN54S281/SN74S281, SN54S381, SN74S381,
SN54S481/SN74S481
PIN DESIGNATIONS
ALTERNATIVE

DESIGNA TlONSt

PIN NOS.

FUNCTION

GO, G1, G2, G3

GO, G1, G2, G3

3,1,14,5

CARRY GENERATE INPUTS

PO, P1, P2, P3

PO, P1, P2, P3

4,2,15,6

CARRY PROPAGATE INPUTS

Cn

Cn

13

CARRY INPUT

C n +x , C n +y ,

C n +x , C n +y ,

C n+ z

Cn+z

12,11,9

CARRY OUTPUTS

G

Y

10

CARRY GENERATE OUTPUT

P

X

7

CARRY PROPAGATE OUTPUT

VCC

16

SUPPLY VOLTAGE

GND

8

GROUND

logic: see description and function tables

t Interpretations are illustrated on page 7-273

description
The SN54182, SN54S182, SN74182, and SN74S182 are high·speed, look·ahead carry generators capable of anticipating
a carry across four binary adders or group of adders. They are cascadable to perform full look-ahead across n-bit adders.
Carry, generate-carry, and propagate-carry functions are provided as enumerated in the pin designation table above.
When used in conjunction with the '181, 'LS181, or 'S181 arithmetic logic unit (ALU), these generators provide
high-speed carry look-ahead capability for any word length. Each '182 or 'S182 generates the look-ahead (anticipated
carry) across a group of four ALU's and, in addition, other carry look-ahead circuits may be employed to anticipate
carry across sections of four look-ahead packages up to n-bits. The method of cascading '182 or 'S182 circuits to
perform multi-level look-ahead is illustrated under typical application data.

•

The carry functions (inputs, outputs, generate, and propagate) of the look-ahead generators are implemented in the
compatible forms for direct connection to the ALU. Reinterpretations of carry functions as explained on the '181,
'LS18l, and 'S181 data sheet are also applicable to and compatible with the look-ahead generator. Logic equations for
the '182 and 'S182 are:

Cn + x = GO + PO Cn
C n+y = Gl + Pl GO + Pl PO Cn
Cn+z = G2 + P2 Gl + P2 P1 GO + P2 Pl PO Cn
G = G3 + P3 G2 + P3 P2 Gl + P3 P2 Pl GO
15= P3 P2 Pl PO

or

Cn +x = YO (XO + Cnl
Cn+y = Yl [Xl + YO (XO + Cn )]
Cn +z = Y2 {X2 + Yl [Xl + YO (XO + Cn )]}
Y = Y3 (X3 + Y2) (X3 + X2 + Yll (X3 + X2 + Xl + YO)
X = X3 + X2 + Xl + XO

logic
FUNCTION TABLE FOR

G OUTPUT

INPUTS

= high

FORPOUTPUT

G3

G2

G1

GO

P3

P2

P1

G

L

X

X

X

X

X

X

L

X

L

X

X

L

X

X

L

X

X

L

X

L

L

X

L

All other

X

X

X

L

L

L

L

L

combinations

All other combinations
H

FUNCTION TABLE

OUTPUT

level, L

=

low level, X

=

INPUTS

OUTPUT

P3 P2 P1

PO

P

L

L

L

L

L

H

H

irrelevant

Any inputs not shown in a given table are irrelevant with respect to that output.

1076

7-282

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54182, SN54S182, SN14182, SN14S182
LOOK-AHEAD CARRY GENERATORS
logic

functional block diagram
FUNCTION TABLE
FOR C n+x OUTPUT
INPUTS

OUTPUT

GO

PO

Cn

L

X

X

C n+x
H

L

H

H

X

All other

L

combinations

(6)
~30r X3 (5)
G30rY3

FUNCTION TABLE
FOR Cn+y OUTPUT
INPUTS
Gl

GO Pl PO Cn

L

X

X

X

X

X

L

L

X

X

X

X

L

L

H

H
or

Cn+z

All other

P2 or X2 (15)
G2orY2 (14)

combinations

FUNCTION TABLE FOR Cn+z OUTPUT
INPUTS

OUTPUT

G2

Gl

GO

P2

Pl

PO

Cn

L

X

X

X

X

X

X

Cn+z
H

X

L

X

L

X

X

X

H

X

X

L

L

L

X

X

H

X

X

L

L

L

H

H

X

All other combinations

L

I

I

(2)
~1 orXl (1)
GlorYl

illOJ

•

I

H = high level, L = low level, X = irrelevant
Any inputs not shown in a given table are irrelevant with respect to
that output.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54', SN54S' Circuits.
SN74', SN74S' Circuits.
Storage temperature range
NOTES:

7V
5.5 V
. . . . 5.5 V
-55°C to 125°C
. aOc to 7aoC
-65°C to 15aoC

1. Voltage values. except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple·emitter input transistor. For these circuits, this rating applies to each
input in conjunction with any other G input or in conjunction with any P input.

IT

1076

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•

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7-283

TYPES SN54182. SN74182
LOOK-AHEAD CARRY GENERATORS
recommended operating conditions
SN74182

SN54182
MIN
Supply voltage, VCC

4.5

NOM

MAX

MIN

5.5

4.75

5

High-level output current, IOH

NOM

-BOO

low-level output current, 10l

MAX

V

-BOO

/lA

16

mA

70

°c

16
-55

Operating free-air temperature, T A

125

UNIT

5.25

5

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

Vil

low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage
low-level output voltage

II

Input current at maximum input voltage

VCC= MIN,

11--12mA

VCC= MIN,

VIH=2V,

Vil = O.S V,

10H =-SOO/lA

VCC= MIN,

VIH = 2 V,

Vll=O.SV,

IOl = 16mA

2.4

•

TYP+ MAX
O.S

-1.5

-1.5
2.4

0.2

1

0.4
1

Cn input

SO

SO

~3 input

120

120

High-level

P2 input

input current

15'0, P1, or G3 input

VCC= MAX, VI = 2.4 V

160

160

200

200

360

360

G1 input

400

400

Cn input

-3.2

-3.2

-4.S

-4.S

-6.4

-6.4

-S

-S

-14.4

-14.4

low-level

P2 input

input current

150, P1, or G3 input

Vec= MAX, VI = 0.4 V

GO or G2 input
G1 input

-16

Short-circuit output current§

-40

Vec= MAX

leCH Supply current, all outputs high
ICCl Supply current, all outputs low

-100

See Note 3

27

Vec - MAX, See Note 4

45

Vec=5V,

V
V
V

3.4
0.2

0.4

VCC = MAX, VI = 5.5V

UNIT
V

O.S

3.4

P3 input

lOS

MIN
2

GO or G2 input

III

SN74182

TYP+ MAX

2

VOL

IIH

SN54182
MIN

V
mA

IlA

mA

-16
-100

-40
27

65

45

mA
mA

72

mA

TFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time and duration of the short-circuit test should not exceed one second.
NOTES: 3. ICCH is measured with all outputs open, inputs P3 and G3 at 4.5 V, and all other inputs grounded.
4. I CCL is measured with all outputs open; inputs GO, <31, and <32 at 4.5 V; and all other inputs grounded.

switching characteristics, Vee

I

I
I

= 5 V, TA = 25°e.
i

PARAMETER
tplH

Propagation delay time, low-to-high-Ievel output

tpHl Propagation delay time, high-to-Iow-Ievel output

I

1

TEST CONDITIONS
Cl = 15 pF,

Rl =400

See Note 5

MIN

n,

TYP

MAX UNIT

11

17

ns

15

22

ns

NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-284

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN54S182, SN74S182
LOOK-AHEAD CARRY GENERATORS
recommended operating conditions
MIN
Supply voltage, VCC

4.5

SN54S182
NOM MAX
5

MIN

5.5
-1

High-level output current, IOH
Low-level output current, IOL

4.75

SN74S182
UNIT
NOM MAX
5

20

Operating free-air temperature, T A

-55

125

0

5.25
-1

V

20

mA
mA

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

..'I

TEST CONDITIONSt

MIN

SN54S182
TVP:j: MAX

2

Low-ievei ouipui voitage

Input CUiiSfit at maximum input VO:tage

VCC= MIN,

II = -1SmA

VCC - MIN,

VIH=2V,

V

2

VIL = O.S V,

IOH =-1 mA

VCC- MIN,

VIH-2V,

VIL = O.S V,

IOL =20mA

2.5

O.S
-1.2

3.4

2.7

Vee = MAX, VI=5.5V

3.4

f:ligh-Ievel

P2 input

input current

PO, P1, or G3 input

0.5

i

i

50

150

150
200

GO or G2 input

350

350

G1 input

400

C n input

-2

400
-2

Low-ievei

15"3 input
;>2 input

input current

PO, P1, or <33 input

-4
I

VCC = MAX, VI = 0.5 V

-6
-S
-14
-16
-100

I

GO or G2 input
G1 input
Short-circuit output current §
lOS
ICCH Supply current, all outputs high
ICCL Supply current, all outputs low

-40

VCC= MAX
See Note 3
VCC= 5V,
VCC - MAX, See Note 4

35
69

V
mA

100

200

VCC= MAX, VI = 2.7 V

V
V
V

0.5

50
100

P3 input

IlL

SN74S182
UNIT
TVP:j: MAX

O.S
-1.2

Cn input

IIH

MIN

J.LA

-4
I

-61
mA
-S
-14
-16
-40

-100

mA

109

mA
mA

35
99

69

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j: All typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time and duration of the short-circuit test should not exceed one second.
NOTES: 3. ICCH is measured with all outputs open, inputs 15"3 and 133 at 4.5 V, and all other inputs grounded.
.
4. ICCL is measured with 1111 outputs open; inputs GO, 131, and (32 at 4.5 V; and all other inputs grounded.

switching characteristics, Vee

TO
(OUTPUT)

tPLH
tpHL

GO, G1, G2, G3,
PO, P1, P2, or P3

tpLH

GO, G1, G2, G3,

tpHL

P1, P2, or P3

tpLH

Po, P1, P2, or 1>3

tpHL
tpLH
tpHL

Cn

•

= 5 V, TA = 25°e

FROM
(INPUT)

PARAMETER~

I

I

TEST CONDITIONS

MIN

TVP

MAX UNIT

Cn+x , Cn+y,

4.5

7

or C n+z

4.5

7

5

7.5

7

10.5

4.5
6.5

6.5
10

6.5

10

7

10.5

G

RL=2S0n, CL=15pF,
See Note 5

I>
Cn+x, Cn+y,
orC n+z

ns
ns
ns
ns

~tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
NOTE 5: Load circuit and voltage waveforms are shown on page 3-10.

1076

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•

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7-285

TYPES SN54182, SN54S182, SN74182, SN74S182
LOOK-AHEAD CARRY GENERATORS
schematics of inputs and outputs
'182
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

-------------~~-VCC

Vcc----------e--------

58
INPUT
Cn

1'3
1'2
PO, P1,G3
GO, 134
G1

INPUT

n

NOM

Req NOM

2.8 kn
1.4 kn
940 n
700 n
400 n
350 n

OUTPUT

'S182
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS
-------------~~-VCC

50

n

NOM

VCC---------.------

INPUT

•

INPUT

Req NOM

Cn
1'3
P2
PO,P1, <33
GO, (34
131

2.8 kn
1.4 kn
940 n
700 n
400 n
350 n

'-----......-OUTPUT

TYPICAL APPLICATION DATA

64·BIT ALU, FULL-CARRY LOOK-AHEAD IN THREE LEVELS
Remaining inputs and outputs at ·181, 'LS181, 'S181 'S281 , 'S381, and 'S481 are not shown.

1076

7-286

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DALLAS. TEXAS 75222

TYPES SN54H183, SN54LS183, SN74H183, SN74LS183
DUAL CARRY-SAVE FULL ADDERS

TTL
MSI

BULLETIN NO. DL-S 7611B4B, OCTOBER 1976

SN54H183, SN54LS183 ..• J OR W PACKAGE
SN74H183, SN74LS183 ... J OR N PACKAGE
(TOP VIEW)

•

For Use in High-Speed Wallace-Tree Summing
Networks

•

High-Speed, High-Fan-Out Darlington Outputs

•

Input Clamping Diodes Simplify System Design

TYPICAL AVERAGE
PROPAGATION
DELAY TIME

TYPICAL
POWER
DISSIPATION

'H183

11 ns

110 mW per bit

'LS183

15 ns

23 mW per bit

TYPES

~~GND

functional block diagram (each adder)

INPUTS

OUTPUTS

POS!ti\'2 logic: see function t:;:b!e
NC-No internai connection

FUNCTION TABLE
(EACH ADDER)
B (3,12)

INPUTS
Cn
L
A

(1,13)

H

A

I:

L

L

L

Cn +1
L

L

L

H

H

L

L

H

L

H

L

H

H

L

H

L

L

H

L

H

L

H

L

H

H

H

L

L

H

H

H

H

H

H

= high

schematics of inputs and outputs
'H183
EQUIVALENT OF
EACH INPUT

VCC

--

'NOM
INPUT

okn

TYPICAL OF ALL

VCC

58n
--~VCC
NOM

= low

L
I

H

I

•

level

o

'LS183
TYPICAL OF ALL
OUTPUTS

6 kn NOM

INPUT
__

level, L

EQUIVALENT OF
EACH INPUT

OUTPUTS

--

OUTPUTS

B

OUTPUT

--

description
These dual full adders feature an individual carry output from each bit for use in multiple·input, carry-save techniques
to produce the true sum and true carry outputs with no more than two gate delays. The circuits utilize high-speed,
high-fan-out, transistor-transistor logic (TTLI. but are compatible with both DTL and TTL families. Series 54H and
54LS devices are characterized for operation over the full military temperature range of -55°e to 125°e; Series 74H
o
and 74LS devices are characterized for operation from oOe to 70 e.
1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-287

TYPES SN54H183, SN74H183
DUAL CARRY-SAVE FUll ADDERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage VCC (see Note 1)
Input voltage. . . . . . . .
Interemitter voltage (see Note 2)
Operating free·air temperature range: SN54H 183 Circuits
SN74H183 Circuits
Storage temperature range
NOTES:

7V
5.5V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between any two
inputs to the same adder.

recommended operating conditions
SN54H183
MIN

NOM

4.5

Supply voltage, Vee

SN74H183

MAX

MIN

5.5

4.75

5

NOM
5

-1

High-level output current, 10H
low-level output current, 10l

20
-55

Operating free-air temperature, T A

125

0

UNIT

MAX
5.25

V

-1

mA

20

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High·level input voltage

Vil

low-level input voltage

VIK

Input damp voltage

VOH

High-level output voltage

VOL

•

TEST CONDITIONSt

MIN

TYP:j: MAX

UNIT

2

low-level output voltage

Vee= MIN,

II = -8 mA

Vee = MIN,

VIH = 2 V,

Vil = 0.8 V,

10H = -1 mA

Vee = MIN,

VIH =2 V,

Vil = 0.8 V,

10l = 20mA

2.4

V
0.8

V

-1.5

V

3.5
0.2

V
V

0.4

II

Input current at maximum input voltage

Vee = MAX,

VI = 5.5V

1

IIH

High-level input current

Vee = MAX,

VI = 2.4 V

150

/lA

III

low-level input current

Vee= MAX,

VI = 0.4 V

-6

mA

lOS

Short-circuit output current§

Vee = MAX

-100

mA

leCl Supply current, all outputs low

I leeH

ISN54H183

48

69

See Note 3

ISN74Hl83

48

75

See Note 4

40

I Vee = MAX,

Supply current, all outputs high

-40

Vce = MAX,

mA

mA

I

mA

I

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:\: All typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
NOTES: 3. leCL is measured with all outputs open and all inputs grounded.
4. ICCH is measured with all outputs open and all outputs at 4.5 V.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER
tplH

TEST CONDITIONS

Propagation delay time, low-to-high-Ievel output

el=25pF,

tPHl Propagation delay time, high-to-Iow-Ievel output

See Note 5

Rl=280n,

MIN

TYP

MAX

10

15

12

18

NOTE 5: Load circuit and waveforms are shown on page 3-10.

1076

7·288

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS183. SN74LS183
DUAL CARRY-SAVE FULL ADDERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage Vcc (see Note 1)
Input voltage .
Operating free-air temperature range: SN54LS183 Circuits
SN74LS183 Circuits
Storage temperature range

. 7V
. 7V
-55°C to 125°C
. . O°C to 70°C
-65°C to 150°C

NOTE1: Voltage values, except interemitter voltage, are with respect to network ground terminal.

recommended operating conditions
SN74LS183

SN54LS183
MIN
4.5

Supply voltage, VCC

NOM

MAX

MIN

5.5

4.75

5

NOM
5

--400

High·level output current, 10H

4

Low-I eve! Qt.!tput current, IOL

-55

Operating free-air temperature, T A

125

0

MAX

UNIT

5.25

V

-400

p,A

15

rnA

70

°c

electrical characteristics over recommended operation free-air temperature range (unless otherwise noted)
High-level input voltage

V, L

Low-level input voltage

TYP+

MAX

2

MIN

TYP+

Vcc = MIN,

" = -18

V,L = V,Lmax,

I

Vee - MIN,

I V,H = 2 V,

Low-level output voltage

10H = -400 p,A

2.5

3.4

2.7

0.25

\'OL =4 rnA

0.4

0.8

V

-1.5

V

3.4
0.25

V

0.4

rf-.----+-------+--------I

V,L = V,Lmax,

10L = 8 rnA

UNIT

V

-1.5

mA

Vcc - MIN,

High-level output voltage

MAX

2
0.7

Input clamp voltage

"

MIN

TEST CONDITIONSt

PARAMETER
V,H

0.35

V

0.5
rnA

Input current at maximum input voltage

Vcc = MAX,

V, = 7 V

0.3

0.3

High-level input current

Vcc = MAX,

V,

V

60

60

p,A

Low-level input current

Vcc = MAX,

V, =0.4 V

-1.2

-1.2

rnA

= 2.7

lOS
ICCL

Short-circuit output current §

Vcc = MAX

-100

rnA

Supply current, all outputs low

Vcc - MAX,

See Note 3

10

17

10

17

rnA

ICCH

Supply current, all outputs high

Vcc - MAX,

See Note 4

8

14

8

14

mA

-20

-100

-20

•

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:tAli typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.

3. ICCL is measured with all outputs open and all inputs grounded.
4. ICCH is measured with all outputs open and all outputs at 4.5 V.

NOTES:

switching characteristics, Vee

=5 V, TA =25°e
TEST CONDITIONS

PARAMETER
tpLH

Propagation delay time, low-to-high-Ievel output

CL=15pF,
See Note 6

tPHL Propagation delay time, high-to-Iow-Ievel output
NOTE 6:

)76

Load circuit and waveforms are shown on

RL=2kn,

MIN

TYP

MAX

15

23

15

23

page 3-11.

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas

I nstruments reserves the right to change or discontinue this product without notice.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE B~X 5012

•

DALLAS. TEXAS 75222

7-289

TTL
MSI

TYPES SN54184. SN54185A. SN74184. SN74185A
BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS
BULLETIN NO. DL·S 7211392, FEBRUARY 1971 -

REVISED DECEMBER 1972

SN54184, SN74184 BCD-TO-BINARY CONVERTERS
SN54185A, SN74185A BINARY-TO-BCDCONVERTERS

SN54184. SN54185A ... J OR W PACKAGE
SN74184.SN74185A ... J OR N PACKAGE
(TOP VIEW)

description
These monolithic converters are derived from the
custom MSI 256·bit read-only memories SN5488 and
SN7488. Emitter connections are made to provide
direct read·out of converted codes at outputs Y8
through Yl as shown in the function tables. These
converters demonstrate the versatility of a read-only
memory in that an unlimited number of reference
tables or conversion tables may be built into a system
using economical, customized read-only memories.
Both of these converters comprehend that the least
significant bits (LSB) of the binary and BCD codes
are logically equal, and in each case the LSB bypasses
the converter as illustrated in the typical applications.
This means that a 6-bit converter is produced in each
case. Both devices are cascadable to N bits.

positive logic: see function table

An overriding enable input is provided on each converter which, when taken high, inhibits the function, causing all
outputs to go high. For this reason, and to minimize power consumption, unused outputs Y7 and Y8 of the '185A
and all "don't care" conditions of the '184 are programmed high. The outputs are of the open-collector type.

•

The SN54184 and SN54185A are characterized for operation over the full military temperature range of -55°C to
125°C; the SN74184 and SN74185A are characterized for operation from O°C to 70°C.

SN54184 and SN74184 BCD-to-binary converters
TABLE I
SN54184, SN74184

The 6·bit BCD-to·binary function of the SN54184
and SN74184 is analogous to the algorithm:

PACKAGE COUNT AND DELAY TIMES
FOR BCD·TO-BINARY CONVERSION

a. Shift BCD number right one bit and examine
each decade. Subtract thre.e from each 4-bit
decade containing a binary value greater than
seven.
b. Shift right, examine, and correct after each
shift until the least significant decade contains
a number smaller than eight and all other con·
verted decades contain zeros.

INPUT

PACKAGES

(DECADESI

REQUIRED

TOTAL DELAY TIMES (nsl
TVP

MAX

2

2

56

80

3

6

140

200

4

11

196

280

5

19

280

400

6

28

364

520

1076

7-290

TEXAS INSTRUMENTS
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•

DALLAS. TEXAS 75222

TYPES SN54184, SN54185A, SN74184, SN74185A
BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS
SN54184 and SN74184 BCD-to-binary converters (continued)
BCD 10'S
COMPLEMENT CONVERTER

BCDS'S
COMPLEMENT CONVERTER

6-BIT CONVERTER
MOO

~
BADes
A

sv

r--"---..
0

C

B

A

I

~

~

&oBIT BINARY OUTPUT

BCD 10'S COMPLEMENT

FUNCTION TABLE
BCD-TO-BINARY
CONVERTER
iNI'UI:;

BCD

FUNCTION TABLE
BCD 9'S OR BCD 10'S
COMPLEMENT CONVERTER
OUTPUTS

e

'See Note AI
D
C
BAG

0- 1

L

L

!:~

~ ~ ~ ~

&7

L

L

L

~

L

L

H

,See

I

L

L

o

:

~ ~ ~ ~ ~

:

1

LLLLHLHLL

2

LLLHLLLHH

H

H

L

L

L

L

H

H

3

LLLHHLLHL

L

L iL

L

L

H

L

L

4

LLHLLLLHH

10-11

5

L

~!:~~

6

L

7

L

L

L

L ILL

L

L

I LLL

16-17

I

I'See

INPUTS
OUTPUTS
BCD
Note CI
Note DI
RD re=

ns

27

40

ns

tpHL Propagation delay time, high-to-Iow-Ievel output from binary select

See Figure 1 and Note 2

23

40

ns

schematics of inputs and outputs

PARAMETER MEASUREMENT
INFORMATION

EQUIVALENT OF
ALL INPUTS

VCC

------I1

TYPICAL OF
ALL OUTPUTS

•

Vcc ________._-------

30 pF

FROM OUTPUT-----...
UNDER
TEST
RL2

600

n

INPUT

-=

CL

CL includes probe and jig capacitance.

LOAD CIRCUIT
FIGURE 1

NOTE 2: Voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-293

TYPES SN54184, SN54185A, SN74184, SN74185A
BCD-TO-BINARY AND BINARY-TO-BCD CONVERTERS
TYPICAL APPLICATION DATA
SN54184, SN74184

~r-"-..r-"-..~,----"--..~
os CS

85 AS

04 C4

B4 A4 03

C3 83 A3 02 C2

82 A2 01 C1

a1

Al DO CO 80

AD

FIGURE 1-BCD-TO-BINARY CONVERTER
FOR TWO BCD DECADES

.

BCD

•

II

1j j
FIGURE 2-BCD-TO-BINARY CONVERTER
FOR THREE BCD DECADES

FIGURE 3-BCD-TO-BINARY CONVERTER
FOR SIX BCD DECADES

MSD-most significant decade
LSD-least significant decade
Each rectangle represents an SN54184 or SN74184.

127:

7·294

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN54184, SN54185A, SN74184, SN74185A
BCD-lO-BINARY AND BINARY-lO-BCD CONVERlERS
TYPICAL APPLICATION DATA
SN54185A,SN74185A

IIINARV

~

FIGURE 4-6-BIT BINARV-TO-BCD
CONVERTER

........ y

~
I I I I I I I

FIGURE 7-12-BIT BINARV-TO-BCD
CONVERTER (SEE NOTE B)

\

MSD

..

BCD

•

FIGURE 5-8-BIT BINARV-TO-BCD
CONVERTER

~'--..r-----'
\

MSD

V

LSD

I

BCD

FIGURE 6-9-BIT BINARV-TO-BCD
CONVERTER

V

BCD

FIGURE 8-16-BIT BINARV-TO-BCD
CONVERTER (SEE NOTE B)

MSD-Most significant decade
LSD-Least significant decade
NOTES: A. Each rectangle represents an SN54185A or an SN74185A.
B. All unused E inputs are grounded.

02

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-295

TYPES SN54190, SN54191, SN54LS190, SN54LS191,
SN14190, SN14191, SN14LS190, SN14LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
BULLETIN NO. DL-S 7611865, DECEMBER 1972-REVISED OCTOBER 1976

•

SN54', SN54LS' ••. J OR W PACKAGE
SN74', SN74LS' •.• J OR N PACKAGE
(TOP VIEW)

Counts 8-4-2-1 BCD or Binary

•

Single Down/Up Count Control Line

•

Count Enable Control Input

•

Ripple Clock Output for Cascading

INPUTS

DATA
A

•

Asynchronously Presettable with Load Control

•

Parallel Outputs

•

Cascadable for n-Bit Applications
AVERAGE
TYPE

PROPAGATION
DELAY

TYPICAL

INPUTS

DATA

DATA

C

0

CLOCK CLOCK

MIN· LOAD

TYPICAL

MAXIMUM
CLOCK

POWER
DISSIPATION

0B

20 ns

25 MHz

325 mW

20 ns

25 MHz

100 mW

0A

B

FREQUENCY

'190, '191
'LS190, 'LS191

OUTPUTS

RIPPLE MAXI

r--'--,..-;;.r--. ,,..--'--__

ENABLE flOWNI

G

Oc

0D

UP

' - - ' '--v--' ' - . . - - ' '-v----'
INPUT

OUTPUTS

...INPUTS

OUTPUTS

asynchronous inputs: Low input to load sets 0A=A,
Os = S, 0c = C, and 00 = 0

description

The '190, 'LS190, '191, and 'LS191 are synchronous, reversible up/down counters having a complexity of 58
equivalent gates. The '191 and 'LS191 are 4-bit binary counters and the '190 and 'LS190 are BCD counters.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change
coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output
counting spikes normally associated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered on a low-to-high-Ievel transition of the clock input if the
enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made only
when the clock input is high. The direction of the count is determined by the level of the down/up input. When low,
the counter counts up and when high, it counts down. Level changes at the down/up input of the 'LS198 and 'LS191
should be made only when the clock input is high.

•

These coooters are fully programmable; that is, the outputs may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply
modifying the count length with the preset inputs.
The clock, down/up, and load inputs aie buffered to !ovver the drive requirement which significantly ieduces the

number of clock drivers, etc., required for long parallel words.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish
look-ahead for high-speed operation.
Series 54' and 54LS' are characterized for operation over the full military temperature range of -55°C to 125°C; Series
14' and 14LS' are characterized for operation from.O°C to 10°C.

1076

7-296

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX

501~

•

DALLAS. TEXAS 75222

TYPES SN54190, SN54191, SN54LS190, SN54LS191,
SN74190, SN74191, SN74LS190, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
functional block diagrams

en
w

"

I2:

::>

o(.)

>

"

o(.)
w

C

--t+---l----+-+++-+__++__++__' II

!

~

::l

.S

o·

u

0')

.~

~

>

Cl

1272

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-297

TYPES SN54190, SN54LS190, SN74190, SN74LS190
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
'190, 'LS190 DECADE COUNTERS

typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1.
2.
3.
4.

Load (preset) to BCD seven.
Count up to eight, nine (maximum), zero, one, and two.
Inhibit.
Count down to one, zero (minimum), nine, eight, and seven.

LOAD~
I
A

DATA
INPUTS

I

Ij""---r1 ---.-.J i l L . I

I

I

I

S.s:Tla... -I

C

I

Ij"""'""""'j1 -

--1:

;L_
Ir-

D

I ,

CLOCK

DOWNlUP--'L...~---i"-'_ _ _ _ _ _ _ _ _""'"

•

ENABLEIL..~---":~_ _ _ _ _ _ _.......I

I

QB::::IIlL..I _____---II,
I

I
r___

I

QC----r-jia...
__________________~_________~~__________________.......
___ ..J
I 1I
___ ,

QD ____

I

I

L-JJ

~

II

MAX/MIN

=::J ::
II

RIPPLE CLOCK

I I

==~J

I I

:

7::

U
B

I II---....::.....,..;

U

I

9

2

COUNT UP _ ! - , N H , B , T

2:

1

--I I---

0

9

~

COUNT DOWN - - -....

LOAD

1272

7-298

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54191, SN54LS191, SN74191, SN74LS191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
'191, 'LS191 BINARY COUNTERS
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1.
2.
3.
4.

Load (preset) to binary thirteen.
Count up to fourteen, fifteen (maximum), zero, one, and two.
Inhibit.
Count down to one, zero (minimum), fifteen, fourteen, and thirteen.

ENABLE

IL..-:----7-:-______-!r----l!---:--_ _ _ _ _ _ __
I

II
II
II

Go::] :;

II

n

MAX/MIN=-=~~----~------7-~--~
II

II

RIPPLE CLOCK

==J ::
: 13 I I

I

U
14

15

1

2.

2

I 2

II----COUNTUP--+INHIBIT--!

•

U

I
0

L.._________

1

0

15

14

I----COUNTDOWN---!

~
LOAD

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . .
Input voltage: SN54', SN74' Circuits. . .
SN54LS', SN74LS' Circuits.
Operating free-air temperature range: SN54', SN54LS' Circuits.
SN74', SN74LS' Circuits.
Storage temperature range

7V
5.5 V
7V
· -55°C to 125°C
· . O°C to 70°C
· -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

1272

TEXAS INSTRUMENTS
I1'-.CORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-299

TYPES SN54190, SN54191, SN74190, SN74191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL

recommended operating conditions
SN54190, SN54191
MIN
Supply voltage, Vee

4.5

SN74190, SN74191

NOM MAX
5

High-level output current, 10H

5.5

MIN
4.75

NOM MAX
5

-SOO

Low-level output current, 10L

16

Input clock frequency, fclock

20

0

0

UNIT

5.25

V

-SOO

fJ.A

16

mA

20

MHz

Width of clock input pulse, tw(clock)

25

25

Width of load input pulse, twOoad)

35

35

ns

Data setup time, t setup (See Figures 1 and 2)

20

20

ns

Data hold time, thold

0

Operating free-air temperature, T A

ns

ns

0

-55

125

0

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

Vee = MIN

VIL

Low-level input voltage

Vee= MIN

VIK

Input clamp voltage

Vee = MIN,

11=-12mA

VOH

High-Isvel output voltage

Vee= MIN,

VIH=2V,

VOL

•

TEST CONDITIONSt

II

Low-level output voltage
High-level input current at
maximum input voltage

SN54190, SN54191 SN74190, SN74191
MIN

TYP:j: MAX

VIL = O.S V,

10H = -SOOfJ.A

Vee= MIN,

VIH = 2V,

VIL = O.S V,

10L = 16mA

Vee = MAX,

VI = 5.5V

Vee= MAX,

VI=2.4V

2.4

at any input except enable
High-level input current

IIH

9. 2

input current

V
O.S

V

-1.5

-1.5

V

2.4

3.4
0.2

0.4

at enable input
Short-circuit output current§

Vee= MAX

ICC

Supply current

Vee = MAX,

0.4

V

1

40

40

fJ. A

120

120

fJ. A

-1.6

mA

-4.S

mA

I

mA

VI = 0.4 V
-4.S

IlL
lOS

V

1

-1.6

IlL
i
at any mput except enable
t-----L-ow--'--Iev-e'-Ii-n-pu-t-c-'-u-rr-e-nt------i Vee = MAX,

UNIT

O.S

3.4

at enable input
Low~level

TYP:j: MAX

2

High-level input current
IIH

MIN

2

-20
See Note 2

-65
65

99

-1S
65

-65

mA

105

mA

tFor conditions shown as MAX or MIN, use appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.

1076

7-300

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54190, SN54191, SN74190, SN74191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL

switching characteristics,
PARAMETER~

vee = 5 V, TA = 25° C
FROM

TO

(INPUT)

(OUTPUT)

'190, '191
TEST CONDITIONS

f max

tpLH

Load

tpHL
tpLH

Data A. B. C. D

QA. QB. QC. QD

Clock

Ripple Clock

CL=15pF,

tpHL
tPLH

25

RL = 400

n,

See Figures 1 and 3 thru 7
Clock

QA, QB, QC, QD

tPHL
tpLH

TYP

20
QA, QB, QC. QD

tpHL
tpLH

MIN

I

Clock

Max/Min

MAX

MHz

22

33

33

50

14

22

35

50

13

20

16

24

16

24

24

36

28

42

tPHL

37

52

"t'Ln

.)u

45

30

45

tPHL
, tPLH

Down/Up

Ripple Clock

Down/Up

Max/Min

tpHL

UNIT

21

33

22

33

ns
ns

ns
ns

i
I
I

ns

I

ns

1

ns

I

~fmax

== maximum clock frequency
== propagation delay time, low-to-high-Ievel
tpHL == propagation delay time, high-to-Iow-Ievel
tpLH

output
output

schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

vcc--------e-------

----+------v cc

•

INPUT

OUTPUT

Enable input:

Req

All other inputs:

Req

= 1.3 kn NOM
= 4 kn NOM

1272

TEXAS Il'

D

I
:J

.~
t)

~

«
....

Cl

0

«

g

::J
2

-*-

1272

TEXAS Ir-CORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7·307

TYPES SN54192, SN54193, SN54L192, SN54L193, SN54LS192, SN54LS193,
SN74192, SN74193, SN74L192, SN74L193, SN74LS192, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
REVISED OCTOBER 1976

schematics of inputs and outputs

EQUIVALENT OF INPUTS
OF '192, '193, 'L 192, 'L 193

TYPICAL OF OUTPUTS
OF '192, '193, "L 192, 'L 193

----4..--VCC--~

VCC

__- -

INPUT
.....--OUTPUT

'192, '193: Req = 4 kn NOM
'L 192, 'L 193: Req = 40 kn NOM

•

'192, '193: R=130
'L 192, 'L 193: R = 5:;0

n

n

NOM
NOM

TYPICAL OF OUTPUTS
OF 'LS192, 'LS193

EQUIVALENT OF INPUTS
OF 'LS192, 'LS193

- - - - -....- - V C C

V

CC

INPUT

120

n

NOM

---.'---

--t~~

__-

__

'---__.--OUTPUT

Load input: Req
All other inputs: Req

= 25 kn NOM
= 17

kn NOM

1076

7·308

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54192, SN54L192, SN54LS192, SN74192, SN74L192, SN74LS192
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
'192,'L 192, 'LS192 DECADE COUNTERS

typical clear, load, and count sequences
Illustrated below is the following sequence:
1.
2.
3.
4.

CLEAR

Clear outputs to zero.
Load (preset) to BCD seven.
Count up to eight, nine, carry, zero, one, and two.
Count down to one, zero, borrow, nine, eight, and seven.

n

--.J

I

I

LJ

LOAD

A

---_-L
- -__
_ -_ -__

i~--------~!

--1

I

-- __________
-- -- -- -L
_

~------~I

.J
DATA
C

I

~-----~I--

-.J

LI

r-

D

u'"LJ"'UL.Jl.J

COUNT
UP
COUNT
DOWN

°A

I

°B

I

=:1

~

____---,II
I

I

OUTPUTS
°c

=--,

~--------_____----,II

=:1

~

I

°D

CARRY

I
I

u
U

BORROW

r---

1

SEQUENCE
iLLUSTRATED

NOTES:

•

1

0

I
9

COUNT DOWN

8

71

~

A. Clear overrides load, data, and count inputs.
B. When counting up, count-down input must be high; when counting down, count-up input must be high.

1272

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7·309

TYPES SN54193, SN54L193, SN54LS193, SN74193, SN74L193, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
'193, 'L 193, 'LS193 BINARY COUNTERS

typical clear, load, and count sequences
Illustrated below is the following sequence:
1.
2.
3.
4.

CLEAR

Clear outputs to zero.
Load (preset) to binary thirteen.
Count up to fourteen, fifteen, carry, zero, one, and two.
Count down to one, zero, borrow, fifteen, fourteen, and thirteen.

~________________________________________________________________

LOAD

U
IC
I

A-.J

I
_ _ _ _ _ _ _.......1 _

r-

. . ------.L

DATA

~

I

COUNT
UP

•

COUNT
DOWN

u

CARRY

BORROW
SEQUENCE
ILLUSTRATED

NOTES:

I

r--14

15

0

1

COUNT UP

21

~

I

r--1

U
0

I

15

COUNT DOWN

14

13

1

~

A. Clear overrides load, data, and count inputs.
B. When counting up, count-down input must be high; when counting down, count-up input must be high.

1272

7-310

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

TYPES SN54192, SN54193, SN74192, SN74193
SYNCHRONOUS 4-811 UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
recommended operating conditions

MIN
Supply voltage, VCC

SN54192

SN74192

SN54193

SN74193

NOM

4.5

MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM

Low-level output current, 10L

5.25

V

-400

;LA

5

-400
16

Clock frequency, f clock

0

25

UNIT
MAX

0

16

mA

25

MHz

Width of any input pulse, tw

20

20

ns

Data setup time, tsu (see Figure 1)

20

20

ns

0

0

Data hold time, th
Operating free-air temperature, T A

-55

125

ns

0

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

I
I

TEST CONDITIONSt

PARAMETER

MIN
VIH

High-level input voltage

VIL

Low-ievei input voitage

V!K

Input clamp voltage

VOH
VOL

SN54192

SN74192

SN54193

SN74193

TYP+

MAX

I
u.8

2

High-level output voltage
Low-level output voltage

VCC= MIN,

II = -12mA

VCC = MIN,

VIH=2V,

MIN

TYP+

2

-1.5

VIL = 0.8 V,

10H = -400;LA

VCC= MIN,

VIH = 2 V

VIL = 0.8 V,

10L = 16mA

2.4

3.4

2.4

0.2

0.4

0.8

V

-1.5

V
V

3.4
0.2

0.4

V

II

I nput current at maximum input voltage

VCC = MAX, VI = 5.5 V

1

1

IIH

High-level input current

VCC = MAX, VI = 2.4 V

40

40

;LA

IlL

Low-level input current

VCC = MAX, VI=O.4V

-1.6

-1.6

mA

lOS

Short-circuit output current§

VCC = MAX

-65

mA

ICC

Supply current

VCC = MAX, See Note 2

102

mA

-20

-65
65

1-18

89

65

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at V CC = 5 V, T A = 25°C.
than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V.

§ Not more

switching characteristics, Vee
PARAMETER~

= 5 V, TA = 25°e

FROM

TO

INPUT

OUTPUT

TEST CONDITIONS

f max

tpLH

Count-up

Carry

Count-down

Borrow

tPHL
tPLH
tpHL
tpLH

CL

= 15 pF,
n,

RL = 400
Either Count

Q

Load

Q

Clear

Q

See Figures 1 and 2

tpHL
tpLH
tpHL
tpHL

II

MIN

TYP

25

32

MAX UNIT
MHz

17

26

16

24

16

24

16

24

25

38

31

47

27

40

29

40

22

35

ns
ns
ns
ns
ns

~fmax "" maximum clock frequency
tpLH "" propagation delay time, low-to-high-Ievel output
tpH L "" propagation delay time, high-to-Iow-Ievel output

1076

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-311

TYPES SN54L192. SN54L19J. SN74L192. SN74L19J
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
recommended operating conditions
SN54L192
MIN
Supply voltage, V CC

NOM

4.5

SN74L193

MAX

MIN

5.5

4.75

5

High-level output current, 10H

SN74L192

I

SN54L 193

NOM
5

-100

Low-level output current, 10L

5.25

V

-200

p.A

2

Clock frequency, fclock

3

0

UNIT

MAX

0

3.6

mA

3

MHz

Width of any input pulse, tw

200

200

Data setup time, tsu (see Figure 1)

100

100

ns

0

0

ns

Data hold time, th
Operating free-air temperature range, T A

-55

125

ns

0

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER

I

SN54L192
MIN

•

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

SN74L192

SN54L193
TYP:j:

SN74L193

MAX

MIN

2

TYP:j:

2

V

0.7
VCC = MIN,

II = -12mA

VCC = MIN,

VIH = 2 V,

VIL = 0.7 V,

10H = MAX

VCC = MIN,

VIH = 2 V

VIL = 0.7 V,

10L = MAX

0.7

-1.5 i
2.4

UNIT

MAX

I

3.3

-1.5
2.4

0.3

0.15

V
V

3.2
0.2

V

0.4

V
p.A

II

Input current at maximum input voltage

VCC = MAX, VI = 5.5 V

100

100

IIH

High-level input current

VCC= MAX,

VI = 2.4 V

10

10

p.A

IlL

Low-level input current

VCC = MAX, VI = 0.3 V

-0.18

-0.18

mA

lOS

Short-circuit output current§

VCC = MAX

-15

mA

ICC

Supply current

VCC= MAX, See Note 2

15

mA

-3

-15
8.5

-3

15

8.5

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type .
~AII typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V.

switching characteristics, Vee
PARAMETER'

= 5 V, TA = 25°C

FROM

TO

INPUT

OUTPUT

TEST CONDITIONS

f max

3

tPLH
tpHL
tpLH

Count-up
I

Count-down

Borrow

CL=50pF,
RL = 4 kn,

Q

Either Count

See Figures 1 and 2

tpHL
tPLH

Load

Q

Clear

Q

tpHL
tPHL

TYP

MAX UNIT

7
65

Carry

tpHL
tPLH

MIN

MHz
130

65

130

65

130

65

130

104

200

135

240

130

240

105

200

110

200

ns
ns
ns

ns
ns

~fmax

"" maximum clock frequency
tpLH "" propagation delay time, low-to-high-Ievel output
tpH L =' propagation delay time. high-to-Iow-Ievel output

1076

7-312

TEXAS I"iCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 7524:2

TYPES SN54LS192, SN54LS193, SN74LS192, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
REVISED OCTOBER 1976

recommended operating conditions
SN54LS192

SN74LS192

SN54LS193
MIN
Supply voltage, VCC

NOM

4.5

MIN

5.5

4.75

5

High·level output current, 10H

SN74LS193

MAX

NOM
5

-400

Low-level output current, 10L

5.25

V

-400

JlA

4

Clock frequency, fclock

0

25

UNIT

MAX

0

8

rnA

25

MHz

Width of any input pulse, tw

20

20

ns

Data setup time, tsu (see Figure 1)

20

20

ns

0

0

Data hold time, th
Operating free-air temperature range, T A

-55

125

ns
70

0

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER

SN54LS192

SN74LS192

SN54LS193

SN74LS193

iviii~

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VCC= MIN,

11=-18mA

VCC= MIN,

VIH = 2 V,

VCC = MIN,

VIH=2V,

Input current at maximum

VCC = MAX,

input voltage

VI =2.7V
VI = 0.4 V

IlL

Low-level input current

VCC = MAX,

lOS

Short-circuit output current§

VCC= MAX

ICC

Supply current

VCC = MAX,

UNIT

MAX
V
V

-1.5

-1.5

V

3.4

2.7
0.4

VI =7V

I Vee = MAX,

ITt"'+

0.8

IIOL = 8mA

High-level input current

_ ... , ..... +

0.7

0.25

IIOL =4 rnA

VIL = VIL max

iviiN

2

2.5

VIL = VIL max, 10H = -400 JlA

VOL Low-level output voltage

IIH

iviAX

2

VOH High-level output voltage

II

.,,...+

......... roo+

0.15

0.4

0.35

0.5
0.1

0.1
20 I

I

See Note 2

19

V
rnA

20 I J.!A

-0.4
-100

-20

V

3.4

- 20

34

19

-0.4

rnA

-100

rnA

34

rnA

: For conditions shown as MI N or MAX, use othe appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at V CC = 5 V, T A = 25 C.
§Not more than one output should be shorted at a time. ,and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V.

switching characteristics, Vee
PARAMETER~

= 5 V, TA = 25°e

FROM

TO

INPUT

OUTPUT

Count-up

Carry

TEST CONDITIONS

f max
tPLH
tpHL
tPLH

Count-down

CL=15pF,

Borrow

tPHL
tPLH

RL=2k.ll.,
Either Count

Q

Load

Q

Clear

Q

See Figures 1 and 2

tpHL
tPLH
tpHL
tpHL

~fmax
tpLH
tpH L

II

== maximum clock frequency
== propagation delay time, low·to-high-Ievel
== propagation delay time, high-to·low-Ievel

MIN

TYP

25

32

MAX UNIT
MHz

17

26

21

23

16

24

21

33

25

38

31

47

27

40

29

40

22

35

ns
ns
ns
ns
ns

output
output

1076

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-313

TYPES SN54192, SN54193, SN54L192, SN54L193, SN54LS192, SN54LS193,
SN74192, SN74193, SN74L192, SN74L193, SN74LS192, SN74LS193
SYNCHRONOUS 4-BIT UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
PARAMETER MEASUREMENT INFORMATION

,---------- --------.,

DATA
PULSE
GENERATOR
(See Note A)

BORROW

OPEN

I

CARRY

OPEN

I

Q

CLEAR
PULSE
GENERATOR
(See Note A)

I

A

I
I

(See

I

Os

T-=-

Dc
00

LOAD
PULSE
GENERATOR
(See Note A)

I
I
I

RL

;~-:

CL
(See

Note B)

IL _____

LOAD

;

"".:?-

Note C)

I

I
I
I

JOpF
(used with
'54L/74L
only)

~~~~~~:~

I

_____ J

r-----~;~;.~~~------1
L _____ ~=:~~;:~~
J

.---

_____

r------------------~
LOAD CIRCUIT 2
I

L _____ '~'::,~"!<::C.::2)_____ ~

------------.,
LOAD CIRCUIT 4

I

L ____ ~': :,L.::.,lId":i::,u!!..l':"' ____ ~

TEST CIRCUIT

tr

CLEAR

I

I+I
1
1 I

-.I

--+I '-- tf
1 I

I

~r:% 90%~:------------------------------::

I
DATA
INPUT

LOAD
INPUT

--I

~ VI
I-I

!
II
I

--I

tpHL

I-

I4-tf

of~

t-tf

t",

9O%~i

1

V re f Z

1

--I

OV

I.

-:

10% Fj

.,,10%

---- ---------"
t..,

~

90i

1

t-tr

I

~I ~~_ _ _ __

V'ef~9M.
3V
1cr:]jll~ _______ 0V
+I

~tr

_----..!I.==!tp:!!H,!;;L====:~:d.---- VOH
~...vr_ef_ _ _ _ _ _ _ _ _ _ _ _/Vref
~Vref
, " , - - _ VOL
1

Q

--I

l-tr

10%J.Liol!:r--~~----------~~~ref""'"\Lt:'1~I-~:

i

I

OUTPUT

.

I

I.--tPLH

-I

VOLTAGE WAVEFORMS

NOTES:

A. The pulse generators have the following characteristics: Zout '" 50 n and for the data pulse generator PRR";; 500 kHz, duty
cycle = 50%; for the load pulse generator PR R is two times data PRR, duty cycle = 50%.
B. CL includes probe and jig capacitance.
C. Diodes are 1 N3064 for '192, '193, 'LS192, and 'LS193; 1 N916 for 'L 192 and 'L 193.
D. tr and tf ,,;; 7 ns for '192, '193, 'LS192, and 'LS193;";; 25 ns for 'L 192 and 'L 193.
E. Vref is 1.5 volts for '192 and '193; 1.3 volts for 'L192, 'L193; 'LS192, and 'LS193,

FIGURE 1-CLEAR, SETUP, AND LOAD TIMES
1076

7-314

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54192, SN54193, SN54L192, SN54L193, SN54LS192, SN54LS193,
SN74192, SN74193, SN74L192, SN74L193, SN74LS192, SN74LS193
SYNCHRONOUS 4-81T UP/DOWN COUNTERS (DUAL CLOCK WITH CLEAR)
PARAMETER MEASUREMENT INFORMATION
OUTPUTS

r----"----..
Co Oc OsQ

A CARRY BORROW

4V

r------- ----- -I

PULSE
GENERATOR
(See Note AI

I

BORROW

I

CARRY H-+-+-+-~
Q

I
I
I
I

A

Os

Oc

I
:

T

...L

CL
(See Note BI

-=

I
I
I

(See Note CI

:'T"~ 30 pF

i

(used WIth

I
I

"7..7 '54LI'74L
only I

_
IL ______________
LOAD CIRCUIT 1

'
"
.
III w

Co

CLEAR

~

RL

.J'

r~----~=~:~;----,

' - - - - - + - 0 LOAD

_.!~:!O~~:;,'.: ____ j
,..- --- -70::C:~,;3- - - - -,

II

-------------.-----I
r------------------.
L ___________. _____

I

L _

_

_

G

~

(Same as load Circuit 1)

iSa~:O~C~::~lJ

:

~

I~----------------~
L
____ ~::=~~~c:\!.! ____ J
LOAD CI RCUIT 5

•

r-------~--------~
LOAD CIRCUIT 6
I

I

tl

COUNT
UP
INPUT
(See Note OJ
OUTPUT
(See Note EI

-l r-~

r-tr

~

90% li_yJI ~vrel ~5
10%

9

--

Vrel

16

-l'PLHiI

---------------1t

V OH

:~'PHL~
:

-\:::.

'.!~'PLH~

I

VOL
V OH

Vref~~e~
- - - VOL

tl::l:~\...:....7t
~
-------------.......,.1
1

90%

10%

-2-'
--

,

r-\

i

Vret

,{h .

~

"

r---3V

r--\,

~

Vrel

-x...:.Jt
, + -,- v:t

1

-+j tpHL

0 V

-!'PLHI4-

I

I

__________________________

A.
B.
C.
D.

OV

--+t 'PHL ~

(See Note EJ

NOTES:

!

I

'Vret

BORROW
OUTPUT

-t----

Vrel

--''PHLf--

OUTPUT

V -;---3V
re

I
I

I

CARRY
OUTPUT

COUNT
OOWN
INPUT
(See Note 01

I

(Same as Load CirCUit 1)

L _________ - - - - - - - J

TEST CIRCUIT

i

::l

~~

t

~

~::::e~
-1-

,PLH~

VOH
VOL
V
OH

Vref~V~f_

VOLTAGE WAVEFORMS

---

VOL

The pulse generator has the following characteristics: PRR"';; 1 MHz, Zout '" 50 n, duty cycle = 50%.
CL includes probe and jig capacitance.
Diodes are 1 N3064 for '192, '193, 'LS192, and 'LS193; 1 N916 for 'L192 and 'L 193.
Count-up and count-down pulse shown are for the '193, 'L193, and 'LS193 binary counters. Count cycle for '192, 'L192,
and 'LS192 decade counters is 1 through 10.

E. Waveforms for outputs 0A, 0B, and 0c are omitted to simplify the drawing.
F. trand tf"';; 7 nsfor '192, '193, 'LS192, and 'LS193;"';; 25 nsfor'L192 and 'L193.
G. Vrsf is 1.5 volts for '192 and '193; 1.3 volts for'L 192, 'L193, LS192, and 'LS193.

FIGURE 2-PROPAGATION DELAY TIMES

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-315

TYPES SN54194, SN54LS194A, SN54S194,
SN74194, SN74LS194A, SN74S194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

TTL
MSI

BULLETIN NO. DL-S 7611866. MARCH 1974-REVISED OCTOBER 1976

•

Parallel Inputs and Outputs

•

Four Operating Modes:

SN54194, SN54LSl94A, SN54S194 .•. J OR W PACKAGE
SN74194, SN74LSl94A, SN74S194 " . J OR N PACKAGE
(TOP VIEW)

Vcc

Synchronous Parallel Load

OA

Os

0c

OD

CLOCK

S1

so

Right Shift
Left Shift
Do Nothing
•

Positive Edge-Triggered Clocking

•

Direct Overriding Clear
TYPICAL
TYPE

TYPICAL

MAXIMUM

POWER

CLOCK

OISSIPATION

FREQUENCY
36 MHz

'194
'L5194A
'5194

CLEAR ~~~~~ \ A

195mW

36 MHz

75mW

105 MHz

425mW

SERIAL
INPUT

DI
PARALLEL INPUTS

SL~I;;
SERIAL
INPUT

positive logic: see function table
description

These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in
a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and
left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct
modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction GA toward GO)
Shift left (in the direction GO toward GA)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, SO
and Sl, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transistion
of the clock input. During loading, serial data flow is inhibited.

I

Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and Sl is low. Serial
data for this mode is entered at the shift-right data input. When SO is low and Sl is high, data shifts left synchronously
o)-----+I-+---.--f+-\-+-----.--++-i-~t_-r__+-_r__-___,

CLEAR 1 1 1 .

1131

(14)

Os

OA

Oc

\~--------------~v~-----------------~
PARALLEL OUTPUTS

tThis connection is made on '195 only.

typical clear, shift, and load sequences

CLOCK

I

CLEAR

I

J
SERIAL

____~____~r--r-1~______________________~_____+---------------------I

INPUTS {

R

SHIFT LOAD

•

I

-----~----~~~----------------------~'----~---------------------I
-----~------~-------------------------,Ll_J
I

----~------~----------------------~~~~~-------------------I
PARALLEL{ :
DATA
INPUTS

C

o

OUTPUTS

~

A

L

I
I

----~------~----------------------~~~~~-------------------I
L
I

I
I

---"""~~______~r----1,_--------------------~r----1
...--------------------I
I

--- :

08

---~

I

Oc

---,

I

00

---~

I

---~:--------~I----~
---~:--------~I--------~
I

,

I

14'
..- - - - - SE R IA L SH I FT
CLEAR

--------t

~ SERIAL S H I F T _

LOAD

374

TEXAS I ....INSTRUMENTS
CORPORATED
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-325

TYPES SN54195, SN54LS195A, SN54S195, SN74195, SN74LS195A, SN74S195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
REVISED OCTOBER 1976

schematics of inputs and outputs
'195
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

-----4.------

VCC--------~-------

V cc

INPUT

OUTPUT

Clock input: Req

All other inputs: Req

=4
=6

kf!. NOM
kf!. NOM

'LS195A
EQUIVALENT OF J, K,
A, B, C, AND D INPUTS

EQUIVALENT OF CLEAR, CLOCK,

TYPICAL OF ALL OUTPUTS

ANDSHIFT/LOAD INPUTS
--------------....- - - - V CC

120 f!. NOM
VCC---------~-------

VCC--------~-------

17 kf!.

15 kf!. NOM

INPUT--~~~----e-

INPUT----~~------

' - - -......- - OUTPUT

•
'S195
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

-------------....- - - - V CC

50 f!. NOM

VCC------~-------

INPUT
L-.___....____ OUTPUT

Clear, shift/load: Req

All other inputs: Req

= 4 kf!. NOM
= 2.8 kf!. NOM

1076<

7-326

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54195, SN74195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Operating free-air temperature range: SN54195
SN74195
Storage temperature range

7V

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54195
MIN
4.5

Supply voltage, Vee

NOM

SN74195
MAX

MIN

NOM

5.5

4.75

5

5

-800

High-level output current, 10H

16

Low-level output current, 10L
0

Clock frequency, fclock

Width of dock !nput pu!se, tw(ciock)
Width of clear input pulse, tw(clear)

I Shift/load

I Serial and parallel data
1 Clear inactive-state

Setup time, tsu (see Figure 1)

30

0

5.25

V

-800

!LA

16

mA

30

MHz

'u
12

i6

ns

12

ns

25

25

20

20

25

25

ns

10

Shift/load release time, trelease (see Figure 1)
0

Serial and parallel data hold time, th (see Figure 1)

10

ns

70

°e

ns

0

-55

Operating free-air temperature, T A

UNIT

MAX

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High·level input voltage

VIL

LO)l\l·level input voltage

VIK

Input clamp voltage

TEST eONDITIONSt

MIN

TYP+ MAX UNIT

2

VOH High·level output voltage

Vee = MIN,

11= -12 mA

Vee = MIN.

VIH = 2 V,

VIL = 0.8 V,

10H = -800}.LA

Vee = MIN,

VIH = 2 V,

VIL = 0.8 V,

10L = 16 mA

2.4

V
0.8

V

-1.5

V

3.4

VOL

Low-level output voltage

II

Input current at maximum input voltage

Vee = MAX.

VI = 5.5 V

1

IIH

High·level input current

Vee= MAX.

VI=2.4V

40

}.LA

IlL

Low-level input current

Vee

= MAX,

VI = 0.4 V

-1.6

mA

lOS

Short·circuit output current§

Vee = MAX

ICC

Supply current

Vee= MAX,

I SN54195

I SN74195

0.2

-20

See Note 2

0.4

-57

-18

-57
39

•

V

63

V
mA

mA
mA

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee

=

5 V, T A

=

25°e.

§ Not more than one output should be shorted at a time.
NOTE 2:

With all outputs open, shift/load grounded, and 4.5 V applied to the J, K, and data inputs, lee is measured by applying a
momentary ground, followed by 4.5 V, to clear and then applying a momentary ground. followed by 4.5 V, to clock.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER

TEST CONDITIONS

f max Maximum clock frequency

eL = 15 pF,

tPHL Propagation delay time, high-to-Iow-Ievel output from clear

RL=400n,

tPLH Propagation delay time, low-to-high-Ievel output from clock

See Figure 1

tpHL Propagation delay time, high-to-Iow-Ievel output from clock

MIN
30

TYP

MAX

UNIT
MHz

39

ns

19

30

14

22

ns

17

26

ns

·076

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-327

TYPES SN54LS195A, SN14LS195A
4-81T PARALLEL-ACCESS SHIFT REGISTERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply Voltage, Vee (see Note 1)
Input voltage
Operating free-air temperature range: SN54LS195A
SN74LS195A
Storage temperature range

7V
7V
-55°e to 125°e
oOe to 700e
0
-65°e to 150 e

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74LS195A

SN54LS195A
MIN
Supply VOltage, Vee

NOM

4.5

MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM
5

-400

Low-level output current, 10L

MAX

V

-400

/-LA

4
0

Clock frequency, fclock

30

UNIT

5.25

0

8

mA

30

MHz

Width of clock or clear pulse, tw(clock)

16

16

ns

Width of clear input pulse, tw(clear)

12

12

ns

25

25

I

I
I

Setup time, tsu (see Figure 1)

Shift/load
Serial and parallel data

15

15

Clear inactive-state

25

25

Shift/load release time, trelease (see Figure 1)

ns

10

Serial and parallel data hold time, th (see Figure 1)

0

Operating free-air temperature, T A

10

ns

70

°e

0

-55

125

ns

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

•

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

SN54LS195A

TEST eONDlTlONSt

MIN

TYP+

SN74LS195A

MAX

2

VOH High-level output voltage

Vee = MIN,

II = -18 mA

Vee - MIN,

VIH - 2 V,

MIN

Vee - MIN,

2.5

i I OL=8mA

Input current at

UNIT
V

0.8

V

-1.5

-1.5

V

3.4

2.7

0.25

VIH-2V,IIOL=4mA

VIL = Vil. max

MAX

0.7

VIL = VIL max, 10H = -400 /-LA

, VOL Low-!evel output voltage

TYP+

2

0.4

iI

V

3.4
0.25

0.4

0.35

0.5'

V

Vee= MAX,

VI = 7 V

0.1

0.1

IIH

High-level input current

Vee= MAX,

VI=2.7V

20

20

/-LA

IlL

Low-level input current

Vee = MAX,

VI = 0.4 V

-0.4

-0.4

mA

lOS

Short-circuit output current§

Vee= MAX

-100

mA

ICC

Supply current

Vee= MAX,

21

mA

II

maximum input voltage

-20

-100

See Note 2

14

-20

21

14

!

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

:~AII typical values are at V CC = 5 V, T A = 25' C.
~Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second,

NOTE 2: With all outputs open, shift/load grounded, and 4.5 V appl,ed to the J, K, and data inputs, ICC IS measured by applYing a momentary
ground, followed by 4.5 V, to clear and then applying a momentary ground, followed by 4.5 V, to clock.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

f max Maximum clock frequency

eL=15pF,

tpHL Propagation delay time, high-to-Iow·level output from clear

RL = 2 kl2,

tpLH Propagation delay time, low·!o-high·level output from clock

See Figure 1

tpHL Propagation delay time, high·to-Iow-Ievel output from clock

MIN

TYP

30

39

MAX UNIT
MHz

19

30

ns

14

22

ns

17

26

ns

1076

7-328

TEXAS I"'CORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54S195, SN74S195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
REVISED MARCH 1974

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Operating free-air temperature range:

7V
5.5 V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

SN54S195
SN74S195

Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54S195
MIN
4.5

Supply voltage, Vee

NOM

SN74S195

MAX

MIN

5.5

4.75

5

NOM
5

-1

High-level output current, 10H
Low-jevei output current, iOL

20
0

Clock frequency, fclock

0

70

UNIT

MAX
5.25

V

-1

rnA

20

rnA

70

MHz

Width of clock input pulse, tw(clockl

7

7

n~

Width of clear input pulse, w(clearl

12

12

ns

11

11

i

Shift!ioaci

I Serial and parallel data

Setup time, tsu (see Figure 11

I Clear inactive-state

5

5

9

9

ns

6

Shift/load release time, trelease (see Figure 11

3

Serial and parallel data hold time, th (see Figure 11

-55

Operating free-air temperature, T A

6

ns

70

°e

3
125

ns

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
I

TEST CONDITIONSt

MIN

High-level input voltage

TYPt

MAX

Low-level inpUt voltage

V,K

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

I,
"H
I,L
lOS

Short-circuit output current§

Vee = MAX

ICC

Supply current

Vee = MAX,

0.8
Vee = MIN,

II = -18mA

Vee = MIN,

V,H = 2V,

-1.2
ISN54S195

I SN74S195

UNIT
V

2

V,L

i

i

i

I

PARAMETER
V,H

2.5

3.4

2.7

3.4

V
V

V,L = 0.8 V,

10H=-lmA

Vee= MIN,

V,H = 2 V,

V,L = 0.8 Y,

10L = 20 rnA

Input current at maximum input voltage

Vee = MAX,

V,=5.5V

1

High-level input current

Vee = MAX,

V, = 2.7 V

50

IJA

Low-level input current

Vee= MAX,

V, =0.5V

-2

rnA

0.5

-100

-40
See Note 2

I SN54S195

I SN74S195

•

V

70

99

70

109

V
rnA

rnA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC = 5 V, T A = 25° C.
than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open, shift/load grounded, and 4.5 V applied to the J, K, and data inputs, ICC is measured by applying a momentary
ground, followed by 4.5 V, to clear, and then applying a momentary ground, followed by 4.5 V, to clock.

§ Not more

switching characteristics, Vee

= 5 V, T A = 25° C

PARAMETER

TEST CONDITIONS

f max Maximum clock frequency

eL=15pF,

tPHL Propagation delay time, high-to-Iow-Ievel output from clear
tPLH Propagation delay time, low-to-high-Ievel output from clock

RL = 280

n,

See Figure 1

tpHL Propagation delay time, high-to-Iow-Ievel output from clock

MIN

TYP

70

105

MAX UNIT
MHz

12.5

18.5

ns

8

12

ns

11

16.5

ns

'076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-329

TYPES SN54195. SN54LS195A, SN54S195.
SN74195, SN74LS195A, SN74S195
4-81T PARALLEL-ACCESS SHIFT REGISTERS
PARAMETER MEASUREMENT INFORMATION
OUTPUT

VCC

FROM OUTPUT

---e~~-4~~

UNDER TEST

__

M-~~

CL; 15 pF
(See Note B)

LOAD FOR OUTPUT UNDER TEST

I-

----... l

_;

tw(clearl

~.::

CLEAR

3V~'

1

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV

--I

tsu

r+ t n+l

tn....,
CLOCK

tn

Vref

1~--~~~~:7~~----'1
tw(clock)
~ th

DATA

,rtsetup:

(See Note Gl ______.....;_________.J
~

•

v __ <

----.t
,_

-1'

~

~tPHL ---.-.I
ASSOCIATED
OUTPUT Q

p~

..,

I

Vref

trelease

I

\

r1

tsu

____

I th
...r-t-

3V

tsu
Vref

11
I

OV

1, . - - - - - 3V
Vref

OV

--.j

rr-I-

-,

trelease

2~ ..
~~~i-------

...... tPLw---i

t

Vref

3V

OV

\4--tPHL-.I

Ir2t---

I

\

~..

1"\:.:::.J

Vref

tsu

I

-----+----'\'{

tn+l

Vref

fool

SHIFT/LOAD

r+

+-;

Vref

~

VOH
VOL

VOLTAGE WAVEFORMS

NOTES:

A. The clock pulse generator has the following characteristics: Zout '" 50 nand PRR .;; 1 MHz. For '195, tr .;; 7 ns and tf .;; 7 ns.
For 'LS195A, tr';; 15 ns and tf';; 6 ns. For 'S195, tr; 2.5 ns and tf = 2.5 ns. When testing f max , vary the clock PRR.
B. CL includes probe and jig capacitance.
C. ,1>.11 diodes are 1 N3064.
D. A clear pulse is applied prior to each test.
E. For '195 and 'S195, Vref = 1.5 V; for 'LS195A, Vref; 1.3 V.
F. Propagation delay times ItPLH and tPH L) are measured at t n +l' Proper shifting of data is verified at tn+4 with a functional test.
G. J and K inputs are tested the same as data A, B, C, and 0 inputs except that shift/load input remains high.
H. tn = bit time before clocking transition.
tn+l ; bit time after one clocking transition.
t n +4; bit time after four clocking transitions.

FIGURE 1-SWITCHING TIMES

107

7-330

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

TYPES SN54196, SN54197, SN54LS196, SN54LS197,SN54S196, SN54S197,
SN74196, SN74197, SN74LS196, SN74LS197, SN74S196, SN74S197
50/30/100 -MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
BULLETIN NO. DL-S 7611806, OCTOBER 1976

•

Performs BCD, Bi-Quinary, or Binary
Counting

•

Fully Programmable

•

Fully Independent Clear Input

•

Input Clamping Diodes Simplify
System Design

•

Output QA Maintains Full Fan-out
Capability In Addition to Driving
Clock-2 Input

VCC CLEAR aD

GUARANTEED
- TYPES

COUNT FREQUENCY
CLOCK 1

'1nc '1n'"7
IvV,

'ui

n

1":"1"1. • •

v-~u

,1

IVln£

'LS196, 'LS197 0-30 MHz
'S196, 'S197

CLOCK 2
,..", .......

u-.:::::o IVlnz

TYPICAL
POWER DISSIPATION
240mW

0-15 MHz

80mW

0-100 MHz 0-50 MHz

375mW

asynchronous input:

LO\AJ !nput to dear sets QA.
0B, QC, and aD low.

description
These high-speed monolithic counters consist of four doc coupled, master-slave flip-flops, which are internally
interconnected to provide either a divide-by-two and a divide-by-five counter ('196, 'LS196, 'S196) or a divide-by-two
and a divide-by-eight counter ('197, 'LS197, 'S197). These four counters are fully programmable; that is, the outputs
may be preset to any state by placing a Iowan the count/load input and entering the desired data at the data inputs.
The outputs will change to agree with the data inputs independent of the state of the clocks,
During the count operation, transfer of information to the outputs occurs on the negative-going edge of the clock pulse.
These counters feature a direct clear which when taken low sets all outputs low regardless of the states of the clocks .

•

These counters may also be used as 4-bit latches by using the count/load input as the strobe and entering data at the
data inputs. The outputs will directly follow the data inputs when the count/load is low, but will remain unchanged
when the count/load is high and the clock inputs are inactive.
All inputs are diode-clamped to minimize transmission-line effects and simplify system design. These circuits are
compatible with most TTL and DTL logic families. Series 54, 54LS, and 54S circuits are characterized for operation
over the full military temperature range of -550 C to 1250 C; Series 74, 74LS, and 74S circu its are characterized for
operation from 0 0 C to 70 0 C.

typical count configurations
'196, 'LS196, and 'S196 typical count configurations and function tables are the same as those for '176.
See page 7-260_
'197, 'LS197, and 'S197 typical count configurations and function tables are the same as those for '177.
See page 7-260.

functional block diagrams
'196, 'LS196, and 'S196 functional block diagram is the same as that for '176. See page 7-261.
'197, 'LS197, and 'S197 functional block diagram is the same as that for '177. See page 7-261.

076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX S012

•

DAL.L.AS. TEXAS 75222

7-331

TYPES SN54196, SN54197, SN74196, SN74197
50-MHz PRESETIABLE DECADE OR BINARY COUNTERS/LATCHES
schematics of inputs and outputs
EQUIVALENT OF COUNT/LOAD.
CLEAR. AND DATA INPUTS

EQUIVALENT OF CLOCK INPUTS

TYPICAL OF ALL OUTPUTS

VCC-----------~--------

INPUT

NOMINAL VALUES OF
R1. R2, and R3
Countlload, Data: Req; 4 k.l1 NOM
Clear: Req; 2 k.l1 NOM

INPUT
Clock 1
Clock 2

'196

'197

4 k.l1
3 k.l1

6 k.l1

4 k.l1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage . , . . . . . .
Interemitter voltage (see Note 2)
Operating free·air temperature range: SN54196, SN54197 Circuits
SN74196, SN74197 Circuits
Storage temperature range
NOTES:

•

7V

5.5 V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple·emitter transistor. For this circuit, this rating applies between the clear and
count/load inputs.

recommended operating conditions
SN54196, SN54197

SN74196. SN74197

I I

1----'-.....:..-....:....:......---+------'....:....:......-..;;..;..---1. UNIT
MIN
NOM
MAX
MIN
NOM
MAX
Supply voltage, V CC
High·level output current, IOH

4.5

5

Low-level output current, IOL
Count frequency

Pulse width, tw

Input setup time, tsu

4.75

16
Clock·1 input

0

50

Clock·2 input

0

25

Clock·1 input

20

16

mA

0

25

30

30

15

20

MHz

I
ns

20

H igh·level data

tw(ioad)

tw(ioad)

Low·level data

tw(ioad)

tw(ioad)

High-level data

10

Low-level data

15

15

20

20

-55

V

/lA

20

15

Operating free-air temperature, T A

5.25
-800
50

Clear

Count enable time, tenable (See Note 3)

5

0

Clock·2 input
Load

Input hold time, th

5.5
-800

ns

10

125

0

ns
ns
70

°c

NOTE 3: Minimum count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which interval the
count/load and clear inputs must both be high to ensure counting.

107

7-332

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54196, SN54191, SN14196, SN14191
50-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

SN54196. SN74196 SN54197. SN74197
UNIT
MIN TYP:j: MAX MIN TYp:j: MAX

TEST CONDITIONSt

2

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH

High-level input current

Vee- MIN,

11=-12mA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10H = -800J.LA

Vee - MIN,

VIH=2V,

VIL = 0.8 V,

10L = 16mA~

2.4

2
-1.5

V

0.4

Vee = MAX, VI = 2.4 V

clock 2
data, countlload
clear

I

IlL

I

lOS

Short-circuit output current §

I

ICC

Supply current

I Vee = MAX,

I

-1.5

I

Vee = MAX, VI = 0.4V

clock 1

Vee = MAX

V
0.4

0.2

1

40

40

80

80

120

80

-'.61
-3.2

-1.61
-3.2

i -20

-57

1 -18

-57 1-18

I

59

J.LA

rnA

-3.21

j -20

ISN54'

48

V
rnA

-4.8

-4.8

1 SN74'
See Note 4

3.4

1

Vee = MAX, VI = 5.5V

clear, clock 1

I clock 2

V

2.4

data, count/load

Low-level input current

0.8

3.4
0.2

V

0.8

J

-57

rnA

-57
48

I

59

rnA

NOTE 4: ICC is measured with all inputs grounded and all outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C.
~ QA outputs are tested at 10 L = 16 mA plus the limit value of II L for the clock-2 input. This permits driving the clock-2 input while fanning
out to 10 Series 54174 loads.

§ Not more than one output should be shorted at a time.

switching characteristics, Vee
PARAMETERO
f max
tpLH

TO
(OUTPUT)

Clock 1

QA

Clock 1

QA

Clock 2

QB

tpHL
tpLH
tpHL
tpLH

Clock 2
Clock 2
A,B,C,O

tpHL
tpLH

MIN

TYP

50

70

See Note 5

QA, QB, Qe, QO

Load

Any
Any

SN54197

SN74196

CL = 15 pF,

QD

Clear

tpHL
tpHL

QC

TEST CONDITIONS

RL =400n,

tpHL
tpLH

SN54196

FROM
(INPUT)

tpHL
tpLH

= 5 V, TA = 25°e
SN74197

MAX

MIN

TYP

50

70

UNIT

MAX
MHz

7

12

7

12

10

15

10

15

12

18

12

18

14

21

14

21

24

36

24

36

28

42

28

42

14

21

36

54

12

18

42

63

16

24

16

24

25

38

25

38

22

33

22

33

24

36

24

36

25

37

25

37

ns

•

ns
ns
ns
ns
ns
ns

Ofmax == maximum count frequency.
tpLH == propagation delay time, low-to-high-Ievel output.
tpH L == propagation delay time, high-to-Iow-Ievel output.
NOTE 5: Load circuit, input conditions, and voltage waveforms are the same as those shown for the '176, '177 (page 7-264) except that
testing f max , VI L = 0.3 V.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7·333

TYPES SN54LS196, SN54LS197, SN74LS196, SN74LS197
30-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
REVISED OCTOBER 1976

schematics of inputs and outputs

r-------------------------__

EQUIVALENT OF
COUNT/LOAD AND
CLEAR INPUTS

EQUIVALENT OF
CLOCK INPUTS

EQUIVALENT OF
DATA INPUTS

TYPICAL OF ALL
OUTPUTS

VCC

VCC---'---

25 kn
NOM
INPUT
INPUT

......
IW

"

~~

Count/Load: Req = 17 kn NOM
Clear: Req = 9.2 kn NOM

INPUT
Clock 1
Clock 2

"

NOMINAL
VALUES OF
R1, R2, and R3
'LS196
'LS197
8 kn
8 kn
6 kn
15 kn

r.7

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage . . . . . . .
Interemitter voltage (see Note 2).
Operating free·air temperature range: SN54LS196, SN54LS197 Circuits
SN74LS196, SN74LS197 Circuits
Storage temperature range
NOTES:

•

7V
5.5 V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies between the clear and

count/load inputs .

recommended operating conditions
SN54LSl96, SN54LS197
;

MIN
4.5

Supply voltage, VCC
High-level output current, IOH

MAX

MIN

NOM

MAX

5

5.5
-400

4.75

5

5.25
-400

/lA

8

mA

4

Low-level output current, IOL
Count frequency

Clock-1 input
Clock-2 input
Clock-1 input

Pulse width, tw

Input setup time, tsu

I

0

30

0

15

20

I

0

30

0

15

30

30

Clear

15

15

twOoad)

twOoad)

Low-level data

tw(load)
10

twOoad)
10

Low-level data

Count enable time, tenable (See Note 3)

15

15

20

20

-55

Operating free·air temperature, T A

MHz

I
ns

20

20

High-level data
High-level data

V

20

Clock-2 input
Load

Input hold time, th

SN74LS196, SN74LS197 UNIT

NOM

125

0

ns
ns
ns
70

°c

NOTE 3: Minimum count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which interval the
count/load and clear inputs must both be high to ensure counting.

1076

7-334

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS196, SN54LS197, SN74LS196, SN74LS197
30-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
REVISED OCTOBER 1976

electrical characteristics over recommended operating free-air temperature range (urness otherwise noted)
SN54LSl96
PARAMETER

TEST CONDITIONSt

SN74LS196

SN54LS197
MIN

VIH High-level input voltage
VIL Low-level input voltage

SN74LS197

TYP:j: MAX

2

VIK Input clamp voltage
VOH High-level output voltage

VCC= MIN,

II = -18mA

VCC= MIN,

VIH = 2V,

2.5

VOL Low-level output voltage

VIH=2V,

Input current
at maximum
input voltage

0.8

V

-1.5

-1.5

V

3.4

2.7

I

I •••

1M

High-level
mput current

0.25

0.4

Data, count/load
Clear, clock 1
Clock 2 of 'LS196

VCC= MAX,

VI = 5.5 V

Clock 2 of 'LSi97

Low-level
I nput current

V

3.4
0.25

0.4

0.35

0.5

0.1

0.1

0.2
0.4

0.2
0.4

0.2

0.2

Data, count/load

20

20

Clear, clock 1

40

40

40

40

Data, count/load

-0.4

-0,4

Clear

-0.8

-0.8

I

V-.. -..
Clock 2 of 'LS1961 CC

=.

iviAX,

v

=

2.7 V

C!cck 2 of 'LS197

IlL

V

2

IIOL =8mA~

VIL = VIL max

II

[IOL =4mA~

UNIT

TYP:j: MAX

0.7

VIL = VIL max' 10H = -400 IlA
VCC= MIN,

MIN

Clock 1

VCC = MAX,

VI

= 0.4 V

Clock 2 of 'LS196
Clock 2 of 'LS197

lOS Short-circuit output current§
ICC Supply current

VCC= MAX,

See Note 4

IlA

-2.4 rnA

-2.8

-2.8
-1.3
-100

-100 -20

-20

rnA

-2.4
-1.3

VCC= MAX

V

16

rnA
27 rnA

16

27

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+Aii typicai values are at Vce = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-<:ircuit should not exceed one second.
~ QA outputs are tested at specified IOL plus the limit value of II L for the clock-2 input. This permits driving the clock-2 input while maintaining full fan-out capability.
NOTE 4: ICC is measured with all inputs grounded and all outputs open.

switching characteristics, Vee
PARAMETERO
f max
tpLH

TO

(INPUT)

(OUTPUT)

Clock 1

QA

Clock 1
Clock 2

QB

Clock 2

QC

MIN
30

CL = 15pF,
RL = 2 kn,

Clock 2

See Note 6

QD

tPHL
tpLH

A,B,C,D

QA,QB, QCQD

Load

Any

Clear

Any

tpHL
tPLH
tpHL
tpHL

SN54LS197

SN74LS196

QA

tpHL
tpLH

TEST CONDITIONS

TYP

SN74LS197

MAX

40

MIN
30

TYP

UNIT

MAX

•

MHz

40

15

8

15

13

20

14

21

16

24

12

19

22

33

23

35

38

57
'62

34

51

41

42

63

12

18

55

78

30

45

63

95

20

30

18

27

29

44

29

44

8

tPHL
tPLH

SN54LS196

FROM

tpHL
tpLH

= 5 V, TA = 25°e

ns
ns
ns
ns

27

41

26

39

30

45

30

45

34

51

34

51

ns
ns
ns

Of max ;; maximum count frequency
tPLH ;; propagation delay time, low-to-high-Ievel output, tPH L ;; propagation delay time, high-to-Iow-Ievel output
NOTE 6: Load circuit, input conditions, and voltage waveforms are the same as those shown for the '176, '177 (page 7-264) except that
tr';;; 15 ns, tf';;; 6 ns, and Vref = 1.3 V (as opposed to 1.5 V)

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-335

TYPES SN54S196, SN54S197, SN74S196, SN74S197
100-MHZ PRESEnABLE DECADE AND BINARY COUNTERS/LATCHES
schematics of inputs and outputs
EQUIVALENT OF COUNT/LOAD,

EQUIVALENT OF CLOCK INPUT

CLEAR, AND DATA INPUTS

TYPICAL OF ALL OUTPUTS
----------~---VCC

VCC - - 1......-

VCC - - - . - -

50n

Req

.---------e NOM

INPUT
-

.......>-.--'

Clock 1 Req
Count/Load, Clear: Req = 2.3 kn NOM
Data: Req

= 2.8 kn NOM

= 1.2 kn NOM
= 700 n NOM

Clock 2 'S196 Req

Clock 2 'S197 Req = 1.4 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V

Supply voltage, VCC (see Note 1)
Input voltage
Operating free-air temperature range: SN54S196, SN54S197 Circuits
SN74S196, SN74S197 Circuits
Storage temperature range

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

•

recommended operating conditions
SN54S196, SN54S197
NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

Supply voltage, VCC
:

High-level output current, IOH
Low-level output current, IOL
Clock frequency

I Pulse width, tw
Input hold time, th
Input setup time, tsu

SN74S196, SN74S197

i MIN

i

-1

i

rnA

20

I

20

I

mA

Clock-1 input

0

100

0

100

0

50

0

50

Clock-1 input

5
10

Clear

30

Load

5

5

High-level data

3t
3t
at
at

3t
at
at

Low-level data

10
I

-55

Operating free-air temperature, T A

MHz

ns

30

3t

12

Count enable time, tenable (see Note 3)

I

5

Clock-2 input

High-level data

V

-1

Clock-2 input

Low-level data

UNIT

ns
ns
ns

12
125

0

i

70

°c

NOTE 3: Minimum count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which interval the
count/load and clear inputs are both high to permit counting.

,

7-336

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

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07~

TYPES SN54S196, SN54S197, SN74S196, SN74S197
100-MHZ PRESETTABLE DECADE AND BINARY COUNTERS/LATCHES

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54S196,
PARAMETER

TEST CONDITIONSt

MIN
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

input voltage

ilH

IlL
i

TYP+

SN74S197

MAX

2

Input current at maximum
II

SN54S197,

SN74S196

MIN TYP+

UNIT

MAX

2

V

0.8

0.8

V

-1.2

-1.2

V

VCC= MIN,

II = -18mA

VCC= MIN,

VIH = 2V,

l54S

2.5

3.4

2.5

3.4

VIL = 0.8 V,

10H = -1 mA 174S

2.7

3.4

2.7

3.4

VCC= MIN,

VIH=2V,

VIL = 0.8 V,

10L = 20 mA~

VCC= MAX,

VI = 5.5 V

V

0.5

0.5

1

1

I

50

50

Il A

!

0.75

0.75

mA

V
mA

I

High-level input current
Low-level input
current

I
I
i

VI=2.7V

VCC= MAX,

data, count/load
clear

V cc = MAX,

clock 1
ciock 2

V = 0.5 V

~I
-10

lOS

Short-circuit output current §

VCC= MAX

ICC

Supply current

Vec= MAX,

-30
See Note 4

-110

mA

-61
-30

-110

I

I54S

75

110

75

110

i

174s

75

120

75

120

I

mA
mA

I

I
I
I

NOTE 4: ICC is measured with all inputs grounded and all outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

+All typical values are at V CC = 5 V, T A

= 25°C.
, QA outputs are tested at IOL = 20 mA plus the limit value of II L for the clock-2 input. This permits driving the ciock-2 input while fanning
out to 10 Series 54S/74S loads.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

switching characteristics, Vee
PARAMETERO
f max

tpLH
tpHL
tPHL
tpLH

FROM

TO

(INPUT)

(OUTPUT)

Clock 1

QA

Clock 1

QA

Clock 2

QS

Clock 2

QC

I
i

tPHL

I

tpLH

I

tPLH
tPLH

I

CL=15pF,
I

Clock 2

tpHL
tpHL

TEST CONDITIONS

I

tpLH

A,S,C,D

RL =280

QA, QS, QC, QO

Load

Any

Clear

Any

n,

See Note 7

QO

tPHL
tPHL

•

= 5 V, TA = 25° C
SN54S196,

S1\!54S197,

SN74S196

SN74S197

MIN

TYP

100

140

MAX

MIN

TYP

100

140

UNIT
MAX
MHz

5

10

5

10

6

10

6

10

5

10

5

10

8

8

12

12

12 I
18 !

12

18

16

24

15

22

5

10

18

27

8

12

22

33

7

12

7

12

18

12

18

10

18

10

18

ns
ns
I

12 I

12

18

12

18

26

37

26

37

ns

1

ns
ns
ns
ns

I
I

°f max == maximum input countY frequency.
tpLH == propagation delay time, low-to-high-Ievel output.
tpHL == propagation delay time, high-to-Iow-Ievel output.
NOTE 7: Load circuit, input conditions, and voltage waveforms are the same as those shown for the '176, '177 on page 7-264.

)76

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

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7-337

TTL
MSI

TYPES SN64198, SN64199, SN74198, SN74199
8-BIT SHIFT REGISTERS
BULLETIN NO. DL-S 7611841, DECEMBER 1972-REVISED OCTOBER 1976

description

SN54198 ..• J OR W PACKAGE
SN74198 •.. J OR N PACKAGE
(TOP VIEW)

These 8-bit shift registers are compatible with most
other TTL, DTL, and MSI logic families. All inputs
are buffered to lower the drive requirements to one
normalized Series 54/74 load, and input clamping
diodes minimize switching transients to simplify
system design. Maximum input clock frequency is
typically 35 megahertz and power dissipation is
typically 360 mW.

SHIFT

LEFT
SERIAL INPUT
51

INPUT

INPUT
F

INPUT
G

H

INPUT

E

Series 54 devices are characterized for operation over
the full military temperature range of -55°C to
125°C; Series 74 devices are characterized for
operation from O°C to 70°C.

SN5419S and SN7419S
These bidirectional registers are designed to incorpopositive logic: see function table
rate virtually all of the features a system designer may
want in a shift register. These circuits contain 87
equivalent gates and feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-modecontrol inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:
Parallel (Broadside) Load
Shift Right (In the direction OA toward 0H)
Shift Left (In the direction OH toward 0A)
Inhibit Clock (Do nothing)
Synchronous parallel loading is accomplished by applying the eight bits of data and taking both mode control inputs,
SO and Sl, high. The data is loaded into the associated flip-flop and appears at the outpuLS after the positive transition
of the clock input. During loading, serial data flow is inhibited.

•

Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and Sl is low. Serial
data for this mode is entered at the shift-right data input. Wh~n SO is low and Sl is high, data shifts left synchronously
and new data is entered at the shift· left serial input.
Clocking of the flip-flop is inhibited when both mode cont
only while the clock input is high.

inputs are low. The mode controls should be changed

'198
FUNCTION TABLE
OUTPUTS

INPUTS
MODE

CLEAR

I----

S1

CLOCK

SERIAL

PARALLEL

LEFT RIGHT

A ... H

°A

°B

L

L

...

~

°H

L

L

L

X

So
X

H

X

X

L

X

H

H

H

t

X

X

a ... h

H

L

H

t

X

H

X

H

QAn

QFn ....,

'199

CLOCK (13)

CLOCKINHIBIT~
SERIAL INPUTS

{~ ~)

i

SHIFT/LOAO-'='(23"'-'I"".-d ..........~

B

(5)

(6)

C

B

(5)

C

(7)

o

(9)

Os

(7)

(B)

o

(9)

(10) 00

E (15)

E (16)

I t------++--+-~ Oe
F (17)
F(18)

•

t+-:=-_ _ _++_

_+_..!.2(1~6) OF

G (191
G (20)

(18)

OG

H (21)
H (22)

SE~~!~;~;0i ..:.:(2;=:2)_ _ _ _ _+--1_ ~

+ ____...J

CLEAR .-'-'('-"'3)_o_--'

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT
VCC---_--

INPUT

Clear, A thru H: Req
All others: Req

= 6 kn
= 4 kn

NOM
NOM

1 07E

7·340

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

CALLAS. TEXAS 75222

TYPES SN54198. SN74198
8-BIT SHIFT REGISTERS
SN54198, SN74198

typical clear, load, right-shift, left-shift, inhibit, and clear sequences

IIII III III

IIII

~

•
--I

,,:

u

3u

I
0

til

iii

a:

;
u

'" _u_
C
(!l:r:
'-v-' \...«_
-..J_ _ _

a:

oJ

oJ

~I\

«

0

o'"

u

0

C
0

w

0

til

~~~
~Cl~

076

TEXAS

INSTRUMENTS

INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-341

TYPES SN54199, SN74199
8-BIT SHIFT REGISTERS
SN54199, SN74199

typical clear, shift, load, and inhibit sequences

•
~

u

g
u

~

u

a

..J

u

cc

~

...,

I~

U

1272'

7·342

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54198, SN54199, SN74198, SN74199
8-BIT SHIFT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
5.5V
-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

Supply voltage, Vcc (see Note 1) . . . . . . .
Input voltage . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54' Circuits
SN74' Circuits
Storage temperature range
NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54198

I I

SN74198

t--_S_N_5:...4_1..:.99.:....-_-+-__S=:,;N..:.7:...4:....:1..::.99=--_--1 UNIT
MIN NOM MAX
MIN NOM MAX
Supply voltage, V CC

4.5

5

High-level output current, 10H

5.5

4.75

5

-BOO

Low·level output current, 10L

5.25

V

-BOO

Jl.A

16

C

25

16

mA

25

MHz

Clock frequency, fctock
Width of clock or clear pulse, tw (see Figure 1)

20

20

Mode·control setup time, tsu

30

30

ns

Data setup time, tsu (see Figure 1)

20

20

ns

Hold time at any input, th (see Figure 1)

0

0

Operating free-air temperature, T A

ns

0

-55

125

ns

0

I °c I

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST

I

COi~DiTiOi~S'

MIN
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

I

SN54198

SN74198

SN54199

SN74199

TYP:j: MAX

2

MIN
2

V

O.B

VOH High-level output voltage

VCC = MIN,

II =-12mA

VCC= MIN,

VIH=2V,

-1.5

VIL = O.B V,

10H =-BOOJl.A

VCC- MIN,

VIH-2V,

VIL = O.B V,

IOL=16mA

2.4

UNITl

TYP:j: MAX

2.4

3.4

O.B

V

-1.5

V
V

3.4

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH

High-level input current

VCC = MAX, VI = 2.4 V

40

40

Jl.A

IlL

Low-level input current

' VCC - MAX, VI- 0.4 V

-1.6

-1.6

mA

-57

mA

116

mA

0.2

0.4

VCC - MAX, VI- 5.5 V

0.2

1

lOS

Short-circuit output current ~

VCC - MAX

ICC

Supply current

VCC= MAX, See Table Below

-20

-57

72

0.4
1

-lB

104

72

V

•

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time.
TEST CONDITIONS FOR ICC
(ALL OUTPUTS ARE OPEN)
TYPE

APPLY 4.5 V

FIRST GROUND,

GROUND

THEN APPLY 4.5 V

SN5419B, SN7419B Serial Input, So, Sl

Clock

Clear, Inputs A thru H

SN54199, SN74199 J, K, Inputs A thru H

Clock

Clock inhibit, Clear, Shift/Load

076

TEXAS INCORPORATED
INSTRUMENTS
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DALLAS. TEXAS 75222

7·343

TYPES SN54198, SN54199, SN74198, SN74199
8-BIT SHIFT REGISTERS
switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER

TEST CONDITIONS

f rnax Maximum clock frequency
Propagation delay time, high-tatpHL

TYP

25

35

I

low-level output from clear

CL=15pF,

Propagation delay time, high-totpHL

MIN

RL = 400

Propagation delay time, low-totpLH

MHz

23

35

ns

20

30

ns

17

26

ns

n,

See Figure 1

low-level output from clock

MAX UNIT

high-level output from clock

PARAMETER MEASUREMENT INFORMATION
SN54198, SN74198

SN54199, SN74199

TEST TABLE FOR SYNCHRONOUS INPUTS

TEST TABLE FOR SYNCHRONOUS INPUTS

DATA INPUT

•

OUTPUT TESTED

DATA INPUT

(SEE NOTE E)

FOR TEST

4.5V

0A at tn+1

A

OV

0A at tn+1

4.5V

4.5V

0B at tn+1

B

OV

Os at tn+1

Sl

SO

A

4.5V

B

FOR TEST

OUTPUT TESTED

SHIFT/LOAD

(SEE NOTE E)

C

4.5V

4.5V

0c at tn+1

C

OV

0c at tn+1

D

4.5 V

4.5 V

0D at tn+1

D

OV

0D attn+1

E

4.5V

4.5V

0E at tn+1

E

OV

0E at tn+1

F

4.5 V

4.5 V

OF at tn+1

F

OV

OF at tn+1

G

4.5V

4.5V

0G at tn+1

G

OV

0G at tn+1

H

4.5 V

4.5V

0H at tn+1

H

OV

0H at tn+1

L Serial Input

4.5 V

OV

0A at tn+8

J and

4.5V

QH at tn+8

R Serial Input

OV

4.5V

0H at tn+8

.-.oj tw(ele.r)

CLEAR INPUT

OUTPUT

1

TEST

I~------------------

~~5~

___

(See Note F)

I

fVCC

RL

~

=4oon

14

~ ~ ~

(5 . . Note CI

DATA

"*(588

Note BI

TABLE)

-.l r-

tpHL
(clear·O)
OUTPUT

a

~---3V

1.5V~1~V_ _ _ _ ov

INPUT
(SEE TEST _ _ _--i. _ _ _ _ _J

LOAD FOR OUTPUT UNDER TEST

~

~"~th
Lov
~tSU'~3V

1_1

/f':'CL = 15 pF

tn

-

CLOCK INPUT

~

3 V

_
---OV

tn

FROM

~~6~~T

R

I

-I tPHLt--

I

--1

I.(CLK·O)
(CLK'O)~t--------v--=--tpLH

1

----""'""\15 V

1 SV
.

-

L-

VOH

VOL

VOLTAGE WAVEFORMS

NOTES:

A. The clock pulse has the following characteristics: tw(clock) ;. 20 ns and PRR = 1 MHz. The clear pulse has the following
characteristics: tw(clear);' 20 ns and thold = 0 ns. When testing f max , vary the clock PRR.
B. CL includes probe and jig capacitance.

C. All diodes are 1 N3064.
D. A clear pulse is applied prior to each test.
E. Propagation delay times (tPLH and tpHL) are measured at t n +1' Proper shifting of data is verified at tn+8 with a functional test.
F. tn = bit time before clocking transition
tn+1 = bit time after one clocking transition
t n +8 = bit time after eight clocking transitions

FIGURE 1
1076

7-344

TEXAS INSTRUMENTS
INCORPORATED

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•

DALLAS, TEXAS 75222

TTL
MSI

TYPES SN54S226, SN74S226
4-BIT PARALLEL LATCHED BUS TRANSCEIVERS
BULLETIN NO. DL-S 7612477, OCTOBER 1976

• Universal Transceivers for Implementing
System Bus Controllers

SN54S226 ... J PACKAGE
SN74S226 ... J OR N PACKAGE

• Dual-Rank 4-Bit Transparent Latches
Provide
- Exchange of Data Between 2 Buses In One
Clock Pulse
- Bus-to-Bus Isolation
- Rapid Data Transfer
- Full Storage Capability

(TOP VIEW)
BUS B INPUTS/OUTPUTS
STB SEL,~-------A------_
VCC GAB S2
B1
B2 B3
B4
13

• Hysteresis at Data Inputs Enhances Noise
Rejection
• Separate Output Control Inputs Provide
Independent Enable/Disable for Either
Bus Output

:::r

II
II I I I I I I I
Al

A2

A3

A4

III
I I

~
STB Sl
A1
A2
A3
A4 OCBA GND

• 3-State Outputs Drive Bus Lines Directly

GBA SEL l
I
BUS A INPUTS/OUTPUTS

description
SEE FUNCTION TABLES

These high'performance Schottky TTL quadruple bus
transceivers employ dual-rank bidirectional four-bit
transparent latches and feature three-state outputs
designed specifically for driving highly-capacitive or
relatively low-impedance loads. The bus-management
functions implemented and the high-impedance controls offered provide the designer with a controller/
transceiver that interfaces and drives system busorganized lines directly. They are particularly attractive for implementing:
Bidirectional bus transceivers
Data-bus controllers

DUAL-RANK
LATCHES

The bus-management functions, under control of the
function-select (S1, S2) inputs, provide complete data
integrity for each of the four modes described in the
function table. Directional transparency provides for
routing data from or to either bus, and the dual store
and dual readout capabilities can be used to perform
the exchange of data between the two bus lines in the
equivalent of a single clock pulse. Storage of data is
accomplished by selecting the latch function, setting
up the data, and taking the appropriate strobe input
low. As long as the strobe is held low, the data is
latched for the selected function. Further control is
offered through
the availability of independent
output controls that can be used to enable or

1076

•

functional block diagram

DUAL-RANK
LATCHES

DCAB
SELECT

STROBE OUTPUT
GAB CONTROL

DESIGN GOAL

This page. provides tentative information on a

i~~~~~en'~ r!::rv=:~~:~;~~~~ c~:~~ :e;:~

continue this product without notice.

TEXA sIN S T RUM EN T S
INCORPORATED
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-345

TYPES SN54S226, SN74S226
4-BIT PARALLEL LATCHED BUS TRANSCEIVERS

BUS-MANAGEMENT FUNCTION TABLE

OUTPUT-CONTROL FUNCTION TABLE

OPERATION

S2

Sl

LATCH FUNCTIONS

OCAB

OCBA

DRIVE BUS B

L

L

Pass Bus A Data to Bus B

L

X

DRIVE BUSA

H

L

Pass Bus B Data to Bus A

H

X

Enable Bus B Outputs

EXCHANGE

H

H

Store Bus A and Bus B Data

X

L

Disable Bus A Outputs (Hi-Z)

BUS A AND B

L

H

Readout Stored Data

X

H

Enable Bus A Outputs

OUTPUT FUNCTION
Disable Bus B Outputs (Hi-Z)

disable the outputs as shown in the output-control function table, regardless of the latch function in process. Store
operations can be performed with the outputs disabled to a high impedance (Hi-Z). In the Hi-Z state the inputs/outputs
neither load nor drive the bus lines significantly. The p-n-p inputs feature typically 400 millivolts of hysteresis to
enhance noise rejection.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

•

Supply voltage, Vee (see Note 1)
Input voltage
Off-state output voltage
Operating free-air temperature range: SN54S226
SN74S226
Storage temperature range

7V

.5.5 V
.5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminaL

1076

DESIGN GOAL

7-346 :~~~';C~gei~r~~i:e~::;I:~~:ni;aflor;::!~n T~:a:TEXAS
Instruments reserves the right to change or dis·
continue this product without notice.

IN STRU M ENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54S226, SN74S226
4-BIT PARALLEL LATCHED BUS TRANSCEIVERS

recommended operating conditions
SN54S226
Supply voltage, Vee

MIN

NOM

4.5

5

SN74S226

MAX

MIN

NOM

5.5

4.75

5

MAX
5.25

High-level output voltage, VOH

5.5

5.5

High-level output current, 10H

-6.5

-10.3

Data setup time, tsu
Data hold time, th

Data (A or B)

5.

3.

Select

5.

3.

Data (A or B)

5.

3.J.

Select

5.

Operating free-air temperature, T A
~ The

125

V
V
rnA
ns
ns

3.

-55

UNIT

a

70

°e

arro"..... indicates that the high-to-:ovv transition of the enable input is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDlTlONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH
VOL

MIN

TYP:j:

MAX

I SN54S226
I SN74S226

High-level output voltage

I

Low-level output voltage

Vee= MIN,

II = -18 rnA

Vee= MIN,

VIH = 2 V,

ISN54S226

2.4

3.3

2.4

2.9

I

VIL = 0.8 V,

IOH = MAX SN74S226

Vee = MIN,

VIH = 2 V,

VIL = 0.8 V,

IOL = 20mA
VIH = 2 V,

UNIT
V

2
0.8

V

-1.2

V
V

0.5

V

100

IlA

-100

IlA

Off-state output current,

Vee = MAX,

high-level voltage applied

Va = 2.4 V

Off-state output current,

Vee = MAX,

low-level voltage applied

VO= 0.5 V

II

Input current at maximum input voltage

Vee= MAX,

VI = 5.5 V

1

rnA

IIH

High-level input current

Vee = MAX,

VI = 2.7 V

100

IlA

IlL

Low-level input current

Vee - MAX,

VI- 0.5 V

lOS

Short-circuit output current§

Vee = MAX

lee

Supply current

Vee- MAX, See Note 2

IOZH
IOZL

VIH = 2 V,

-50
125

-300

IlA

-180

rnA

•

rnA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: I CC is measured with all inputs (and outputs) grounded.

076

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
Instruments reserves the right to change or discontinue this product without notice.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-347

TYPES SN54S226, SN74S226
4-BIT PARALLEL LATCHED BUS TRANSCEIVERS

switching characteristics, Vee
PARAMETER
tPLH

= 5 V, TA = 25°e

FROM

TO

(INPUT)

(OUTPUT)

A orB

tPHL
tpLH

Select

tpHL
tPLH

Strobe GBA

tPHL

or GAB

tpZH

Output Control

tPZL

OCBA orOCAB

tpHZ

Output Control

tPLZ

OCBAor OCAB

TEST CONDITIONS

MIN

TYP

MAX UNIT

14

BorA

ns

14
12

Any

CL

= 50 pF,

= 280 n,

RL

AorB

ns

12

See Note 2

12

ns

12

9
9
7

AorB
CL

AorB

= 5 pF,

RL

= 280 n,

ns
ns

7

See Note 2

== pro~~~ion del~_.!ime, low-to-nigh-Ie:-el output
== propagation delay time, low-to-nigh-Ievel output
tZH == output enable time to high level
tZL == output enable time to low level
tHZ == output disable time from high level
tLZ == output disable time from low level
tPLH

tPH L

NOTE 2: Load circuits and voltage waveforms are shown on page 3-10,

applications
The following examples demonstrate four fundamental bus-management functions that can be performed with the
'S226_ Exchange of data on the two bus lines can be accomplished with a single high-to-Iow transition at S2 when S1 is
high,

•

'S226

~

CONTROL
BUS B .....BUS A

'S226

'S226

'S226

L.....,--J

~
CONTROL
BUSA..-BUSB

CONTROL
READOUT A AND B

CONTROL
STORE A AND/OR B

-- -

-

- - - VIH
Vll

CONTROL {S2

VIH

S1------------------------------------~--~

-

-

-

DESIGN GOAL

7-348

This page. provides tentative information on a
product on the develop~ental stage. Tex~s
Instruments reserves the roght to change or d.s-

continue this product without notice.

TEXAS

I N STRUM ENTS

INCORPORATED
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

VIL

TYPES SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS WITH 3·ST ATE OUTPUTS

TTL
MSI

BULLETIN NO. DL-S 7612471, OCTOBER 1976

•

Bi-clirectional Bus Transceiver in a
High-Density 20-Pin Package

•

3-State Outputs Drive Bus Lines Directly

•

P-N-P Inputs Reduce D-C Loading on
Bus Lines

SN54LS245 ••• J PACKAGE
SN74LS245 ... J OR N PACKAGE
(TOP VIEW)

ENABLE
Vee

•

Hysteresis at Bus Inputs Improve Noise
Margins

•

Typical Propagation Delay Times,
Port-to-Port ... 12 ns

•

Typical Enable/Disable Times ... 17 ns
IOL
(SINK

IOH
(SOURCE

CURRENT)

CURRENT)

TYPE

ill'll OIT L.;;)L"+O

140 rnM

-1.£ (11M.

SN74LS245

24mA

-15mA

G

B1

62

63

64

B5

66

67

B8

positive logic: see function table

description
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control
function implementation minimizes external timing requirements.
The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the
logic level at the direction control (DI R) input. The enable input (<3) can be used to disable the device so that the buses
are effectively isolated.
The SN54LS245 is characterized for operation over the full military t~mperature range of -55°C to 125°C. The
SN74LS245 is characterized for operation from aOe to 7aoe.

schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

FUNCTION TABLE

TYPICAL OF ALL OUTPUTS

Vec

DIRECTION

ENABLE

Q(IO'
. 1)

OUTPUT
H

CONTROL
DIR

OPERATION

(t)

L

L

Etdata to A bus

L

H.•

~ da~a

H

X

= high

level. L

= low

to B bus

Isolation" level, X

= irrelevant

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Operating free-air temperature range: SN54LS245
SN74 LS245
Storage temperature range

..... 7 V
..... 7 V

-55"e to 125°C
aOe to 7aoe
-65°C to 15aoe

NOTE 1: Voltage values are with respect to network ground terminal.

'1076

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
Instruments reserves the right to change or dis-

continue this product without notice.

TEXAS IN ST RUM ENTS
INCORPORATED
POST OFFICE BOX 5012 • DALLAS. TEXAS 75222

7-349

•

TYPE~ SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
recommended operating conditions
SN54LS245

PARAMETER
Supply voltage, Vee

SN74LS245

MIN

NOM

MAX

MIN

4.5

5

5.5

4.75

High·level output current, 10H

MAX

5

5.25

V

-15

rnA

24

rnA

70

°e

-12

Low·level output current, 10L

12

Operating free-air temperature, T A

-55

125

UNIT

NOM

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

VOL

Input clamp voltage

Vee = MIN,

Hysteresis (VT+ - VT_)A or B input

Vee= MIN

High-level output voltage

II

•

SN74LS245

MAX

MIN

TYPt

II = -18mA

10H =-3 rnA

MAX

2

Low-level output voltage

-1.5
0.2

0.4

0.2

0.4

2.4

3.4

2.4

3.4

10H = MAX

Vee = MIN,

10L = 12mA

Off-state output current,

G at2

V

low-level voltage applied
Input current at maximum
input voltage

V
V

2

2
0.4

0.4

VIH = 2 V,

Vce= MAX,

V

V

VIL = VIL max

high-level voltage applied

UNIT
V

0.8
-1.5 ;

VIH=2V,

Off-state ou tpu t cu rrent,

10ZL

TYPt

0.7

VIL = VIL max
10ZH

MIN
2

Vee = MIN,
VOH

SN54LS245

TEST CONDITIONSt

V
10L = 24 rnA

0.5
20 !

VO=2.7V

20
jJ.A

Va = 0.4 V

Vee = MAX,

VI =7V

-20

-20

0.1

0.1

rnA

IIH

High-level input current

Vee = MAX,

VIH = 2.7 V

20

20

jJ.A

IlL

Low-level input current

Vee = MAX,

VIL=OAV

-0.2

rnA

lOS

Short-circuit output current~

Vee = MAX

-0.2
-225

-225

-40

I Total, outputs high
lee

Supply current

25

I Total, outputs low

Vee = MAX,

IOutputs at Hi-Z

-40

46

25

46

58

100

64

105

58
64

105

Outputs open

100

rnA
rnA

t For conditi'ons shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical-values are at Vee = 5 V, TA = 25°e.
~ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

1

Propagation delay time,
tpLH

TYP
12

low-to-high-level output
Propagation delay time,

MIN

eL=45pF,

RL = 667

n,

See Note 2

MAX I UNIT
18

ns

12

18

ns

tpZL

Output enable time to low level

20

30

ns

tpZH

Output enable time to high leve!

15

25

ns

tpLZ

Output disable time from low level

15

25

ns

tpHZ

Output disable time from high level

10

18

ns

tPHL

hiltJ-to-low-leveloutput

eL=5pF,

RL = 667

n,

See Note 2

NOTE 2: Load circu it and waveforms are, shown on page 3-11.

DESIGN GOAL

7-350

This page provides tentative information on a

product in the developmental stage. Texas
InstrUments reserves the right to change or discontinue this product without notice.

1076

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

TYPES SN54246 THRU SN54249, SN54LS247 THRU SN54LS249,
SN74246 THRU SN74249, SN74LS247 THRU SN74LS249
BCO-TO- SEVEN-SEGM ~NT OECOOJRS/OIUVEBS

TTL
MSI

BULLETIN NO. DL-S 7612078, MARCH 1974- REVISED OCTOBER 1976

'246, '247, 'LS247
feature

'248, 'LS248
feature

'249, 'LS249
feature

•

Open-Collector Outputs
Drive Indicators Directly

•

Internal Pull-Ups Eliminate
Need for External Resistors

•
•

Lamp-Test Provision

•

Lamp-Test Provision

Leading/Trailing Zero
Suppression

•

Leading!Trailing Zero
Suppression

•

•

Open-Collector Outputs

•
•

Lamp-Test Provision
Leading/Trailing Zero
Suppression

All Circuit Types Feature Lamp Intensity Modulation Capability
DRIVER OUTPUTS

TYPICAL

ACTIVE

OUTPUT

SINK

MAX

POWER

LEVEL

CONFIGURATION

CURRENT

VOLTAGE

DISSIPATION

SN54246

low

open-collector

40mA

30V

320mW

J,W

SN54247

low

open-collector

40mA

15V

320mW

J,W

ISi~54248

high

2-kn puii-up

6.4mA

5.5 V

265 rn\N

J, 'v·v

5.5V

265mW

J,W

TYPE

SN54249

I

high

I

open-collector

I

10mA

I

PACKAGES

SN54LS247

low

open-collector

12mA

15V

35mW

J,W

SN54LS248

high

2-krl pull-up

2mA

5.5 V

125mW

J,W

SN54LS249

high

open-collector

4mA

5.5V

40mW

J,W

SN74246

low

open-collector

40mA

30V

320mW

J, N

SN74247

low

open-collector

40mA

15V

320mW

J, N

SN74248

high

2-krl pull-up

6.4 mA

5.5 V

265mW

J, N

SN74249

high

open-collector

10mA

5.5V

265mW

J, N

ISN74LS247

low

open-collector

24mA

15V

35mW

I SN74LS248

high

6mA

5.5V

125mW

ISN74LS249

high

8mA

5.5V

40mW

I

2-krl pull-up

I

open-collector
'246, '247, 'LS247

'248, '249, 'LS248, 'LS249

(TOP VIEW)

(TOP VIEW)

I
I

J, N

J, N
J, N

•

OUTPUTS

r-------~A~------~

positive logic: see function tables

description
The '246 through '248 are electrically and functionally identical to the SN5446A/SN7446A, SN5447A/SN7447A, and
SN5448/SN7448, respectively, and have the same pin assignments as their equivalents. Also the 'LS247 and 'LS248 are
electrically and functionally identical to the SN54LS47/SN74LS47 and SN54LS48/SN74LS48, respectively, and have
the same pin assignments as their equivalents. They can be used interchangeably in present or future designs to offer
designers a choice between two indicator fonts. The '249 and 'LS249 are 16-pin versions of the 14-pin SN5449 and
SN54LS49/SN74LS49, respectively. Included in the '249 and 'LS249 circuits is the full functional capability for lamp
test and ripple blanking, which is not available in the '49 and 'LS49 circuits. The '46A, '47A, '4£, '49, 'LS47, 'LS48,
and 'LS49 compose the b and the g without tails and the '246 through '249 and 'LS247, 'LS248, and 'LS249
1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-351

TYPES SN54246 THRU SN54249, SN54LS247 THRU SN54LS249,
SN74246 THRU SN74249, SN74LS247 THRU SN74LS249
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
description (continued)
compose the 5 and the S with tails. Composition of all other characters, including display patterns for BCD inputs
above nine, is identical. The '246, '247, and 'LS247 feature active·low outputs designed for driving indicators directly,
and the '248, '249, 'LS248, and 'LS249 feature active-high outputs for driving lamp buffers. All of the circuits have full
ripple-blanking input/output controls and a lamp test input. Segment identification and resultant displays are shown
below. Display patterns for BCD input counts above 9 are unique symbols to authenticate input conditions.
All of these circuits incorporate automatic leading and/or trailing-edge zero-blanking control (RBI and RBO). Lamp test
(LT) of these types may be performed at any time when the BI/RBO node is at a high level. All types contain an
overriding blanking input (BI) which can be used to control the lamp intensity by pl,llsing or to inhibit the outputs.
Inputs and outputs are entirely compatible for use with TTL or DTL logic outputs.
Series 54 and Series 54LS devices are characterized for operation over the full military temperature range of _55°C to
125°C; Series 74 and Series 74LS devices are characterized for operation from O°C to 70°C.

r:-Ib
el-Ie
-d-

NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS

SEGMENT
IDENTIFICATION

'246, '247, 'LS247
FUNCTION TABLE
DECIMAL

INPUTS

OR

NOTE

FUNCTION

LT

RBI

D

C

0

H

H

L

L

L

L

H

1

H

X

L

L

L

H

H

2

H

X

L

L

H

L

H

H

X

L

L

H

H

H

X

L

H

L

L

5

H

X

L

H

L

6
7
8

H

X

L

H

H

X

L

H

H

X

H

L

L

9

H

X

H

L

L

X

H

L

H

L

H

ON

OFF, ON I

X

H

L

H

H

H

OFF

OFF

ON

ON

OFF

OFF

ON

3
4

•

OUTPUTS

BI/RBOt

I
/

I

e

b

c

ON

ON

ON

ON

ON

ON

9
OFF

OFF

ON

ON

OFF

OFF

OFF

OFF

ON

ON

OFF

ON

ON

OFF

ON

H

ON

ON

ON

ON

OFF

OFF

ON

H

OFF

ON

ON

OFF

OFF

ON

ON

H

H

ON

OFF

ON

ON

OFF

ON

ON

H

L

H

ON

OFF

ON

ON

ON

ON

ON

H

H

H

ON

ON

ON

OFF

OFF

OFF

OFF

L

H

ON

ON

ON

ON

ON

ON

ON

H

H

ON

ON

ON

ON

OFF

ON

ON

B

a

A

1

d

!

f

10

H

11

H

12

H

X

H

H

L

L

H

OFF

ON

OFF

OFF

OFF

ON

ON

13
14

H

X

H

H

L

H

H

ON

OFF

OFF

ON

OFF

ON

ON

H

X

H

H

H

L

H

OFF

OFF

OFF

ON

ON

ON

ON

15

H

X

H

H

H

H

H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

BI

X

RBI

H

LT

L

i

1

I

, OFr ,OFr IOFF I ON

X

X

X

X

X

L

OFF

OFF

OFF

OFF

OFF

OFF

OFFI

L

L

L

L

L

L

OFF

OFF

OFF

OFF

OFF

OFF

X

X

X

X

X

H

ON

ON

ON

ON

ON

ON

OFFI
ON

1

2

3
4

I

H = high level, L = low level, X = irrelevant
NOTES: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are off regardless of the level of any other
input.
3. When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp test input high, all segment outputs
go off and the ripple·blanking output (RBO) goes to a low level (response condition).

4. When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, all
segment outputs are on.
tBI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).

374

7-352

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54246 THRU SN54249, SN54LS247 THRU SN54LS249,
SN74246 THRU SN74249, SN74LS247 THRU SN74LS249
BCD-TO- SEVEN-SEGM ENT DECODERS/DRIVERS
'248, '249, 'LS248, 'LS249
FUNCTION TABLE
DECIMAL
OR
FUNCTION
0
1
2
3
4

5
6
7
8

9
10
11
12
13
14

INPUTS
LT
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

RBI
H

X
X
X
X
X
X
X
X
X
X
X

X
X
X

D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

OUTPUTS

BI/RBOt

C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

x

X

X

X

L

L

L

L

X

X

X

X

a
H
L
H
H
L
H
H
H
H
H
L
L
L
H
L
L
L
L
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

b
H
H
H
H
H
L
L
H
H
H
L
L
H
L
L
L
L
L
H

c

d
H
L
H
H
L
H
H
L
H
H
H
H
L
H

H
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
H

H
L
L
L
H

e
H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
L
L
L
H

NOTE
f
H
L
L
L
H
H
H
L
H
H
L
L
H
H
H
L
L
H

g

L
L
H
H
H
H
H
L
H
H
H
H
H
H

1
1

1

H

L
L
L
H

H = high level, L = low level, X = irrelevant
NOTES: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are low regardless of the level of any
other input.
3. When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp test input high, all segment outputs
go low and the ripple-blanking output (RBO) goes to a low level (response condition).
4. When the blanking input/ripple-blanking output (BIIRBO) is open or held high and a low is applied to the lamp-test input, all
segment outputs are high.
tBI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO)_

'248, '249, 'LS248, 'LS249

'246, '247, 'LS247

BURBO

•

BLANKING

RI,.t~k~:'NG-,=I",---+__~

RtPP~!1~~~~ING-""4I'---t_ _-!

INPUT

LAMP-TEST !'3)

--t==--____.::::EU

RIPPLEi~~~KING-"I5,,---1

374

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-353

TYPES SN54246 THRU SN54249, SN74246 THRU SN74249
BCD-TO- SEVEN-SEGM ENT DECODERS/DRIVERS
schematics of inputs and outputs
'246, '247, '248, '249

'246, '247, '248, '249

Q

EaUIVALENT OF BI/RBO

EaUIVALENT OF EACH INPUT
EXCEPT BI/RBO

v ee

Vee

6 kil NOM

INPUT

--

'246, '247

'248

TYPICAL OF OUTPUTS
a THRU 9

TYPICAL OF OUTPUTS
a THRU 9

-----------.--.------vee
------------1Ir-----.-

OUTPUT

vee

2kil
NOM

•

OUTPUT

'249
TYPICAL OF ALL OUTPUTS

------------1Ir----- v ee

OUTPUT

37,

7-354

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS247 THRU SN54LS249, SN74LS247 THRU SN74LS249
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
schematics of inputs and outputs
'LS24 7, 'LS248, 'LS249

'LS247, 'LS248, 'LS249

-

EQUIVALENT OF BI/RBO

EQUIVALENT OF EACH INPUT
EXCEPT BI/RBO

q

vee

Req

INPUT

--

L T and RBI:

Req

= 20

e, and

Req

= 25 kO

A, B,

D:

Vee

kO NOM
NOM

'LS247

'LS248

TYPICAL OF OUTPUTS
a THRU 9

TYPICAL OF OUTPUTS
a THRU 9

----------.----.-----vee

----------~--~~vee

2kO
NOM
OUTPUT
OUTPUT

•

'LS249

TYPICAL OF OUTPUTS
a THRU 9

----------~----vee

OUTPUT

374

TEXAS

INSTRUMENTS

Il'OCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-355

TYPES SN54246, SN54247, SN74246, SN74247
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED MARCH 1974

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . .
Input voltage . . . . . . . . . . . . .
Current forced into any output in the off state
Operating free-air temperature range: SN54246, SN54247
SN74246, SN74247
Storage temperature range

7V
5.5 V
1 rnA
-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54246
MIN
Supply voltage, Vee

4.5

SN54247

NOM MAX
5

MIN

5.5

SN74246

NOM MAX

MIN

5.5

4.75

4.5

5

SN74247

NOM MAX
5

MIN

5.25 4.75

NOM MAX
5

5.25

UNIT
V

Off-state output voltage, VO(off)

a thru g

30

15

30

15

V

On-state output current, 10(on)

a thru g

40

40

40

40

mA

High·level output current, 10H

BI/RBO

-200

-200

-200

-200

IJ.A

Low-level output current, 10L

BI/RBO

S

S

S

S

mA

70

°e

Operating free-air temperature, T A

-55

125

-55

125

70

0

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

•

TEST CONDITIONSt

High-level output voltage

BI/RBO

Low-level output voltage

BI/RBO

10(offl

Off-state output current

a thru g

II
,1!H

TYP+ MAX UNIT
V

2

VOL

VO(on)

MIN

On-state output voltage

II; -12 mA
VIH - 2 V,

VIL; O.S V,

10H; -2oo1J.A

Vee- MIN,

VIH-2V,

VIL; O.S V,

10L; SmA

2.4

VIL = O.S V,

0.27

VO(off) ; MAX

Vee; MAX, VIH;2V,
VIL = O.S V,

Any input

0.3

10(on) = 40 mA

Low-level input current

lOS

Short-circuit output current
Supply current

V
0.4

V

250

IJ.A

0.4

V
mA

,..,Vee=MAX, VI; 2.4 V
except BI/RBv
"

40

jJ.A

-1.6

except BI/RBO Vee; MAX, VI; 0.4 V
BI/RBO

lee

V

1

Any input
IlL

1.5V

Vee = MAX, VI = 5.5V

except BI/RBO
Any input

High-level input current

V

3.7

Vee- MAX, VIH - 2 V,

a thru g

Input current at maximum input voltage

Vee; MIN,
Vee- MIN,

O.S

mA

-4

BI/RBO

Vee; MAX
Vee= MAX, See Note 2

64

-4

mA

103

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A; 25°C.
'
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee

=5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

toff

Turn-off time from A input

ton

Turn-on time from A input

eL=15pF.

toff

Turn-off time from RBI input

See Note 3

ton

Turn-on time from RBI input

MIN

TYP

MAX UNIT
100

RL = 120

n,

100
100
100

ns
ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3·10; toft corresponds to tpLH and ton corresponds to tpH L·

1076

7-356

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS247, SN74LS247
BCD-TO- SEVEN-SEGM ENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
...... .
Input voltage . . . . . . . . . . . . . . .
Peak output current (tw::;;; 1 ms, duty cycle::;;; 10%)
Current forced into any output in the off state
Operating free-air temperature range: SN54LS247
SN74LS247
Storage temperature range

7V
7V
200mA
. . 1mA
-55°C to 125°C
. O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS247
MIN
4.5

Supply voltage, Vee

NOM

SN74LS247

MAX

MIN

NOM

5.5

4.75

5

5

UNIT

MAX

V

5.25

Off-state output voltage, VO(off)

a thru g

15

15

V

On-state output current, IO(on)

a thru g

12

24

rnA

High-level output current, 10H

BI/RBO

-50

-50

}.LA

Low-level output current, 10L

BI/RBO

1.6

3.2

rnA

I Uperatlng tree-air temperature,

--

IV I
I
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

I

-

A

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

MIN

High-level output voltage BI/RBO

II - -18 rnA

Vec - MIN,

VIH-2V,

1

2.4

VIL = VIL max, 10H = -50}.LA
Vee= MIN,

I VOL

I o(off)

TYP+

Off-state output current

I

llOL = 1.6 rnA
IVIH=2V,
VIL = VIL max /IOL = 3.2 mA

Low-ievei output voltage 8i/R8G

Vee - MAX,

a thru g

II

Input current at maximum input voltage

Vee - MAX,

VI = 7 V

IIH

High-level input current

Vee- MAX,

VI - 2.7 V

IlL

Low-level input current

except BI/RBO Vee= MAX,

VI = 0.4 V

0.25

lee

BI/RBO

Supply current

See Note 2

Vee = MAX,

V

2.4
0.4 I

V

4.2
0.25

0.4

0.35

0.51
250

0.4

1 V

0.25

0.4

0.35

0.5

}.LA

0.1

0.1

rnA

20

20

}.LA

-0.4

-0.4

-1.2

-1.2

-2

-0.3

Vee = MAX

-1.5

V

BI/RBO
output current

V

-1.5

I

Any input

Short-circuit

V

250

lIO(on) = 12 rnA
VIH =2 V,
VIL = VIL max 110(on) = 24 rnA

a thru g

UNIT

MAX
0.8

I

VIH-2V,

On-state output voltage

TYP+

0.7

4.2
0.25

Vee- MAX,

lOS

MIN
2

VIL = VIL max, VO(off) = 15 V

VO(on)

~

SN74 LS247

MAX

2
Vee - MIN,

~~

~

I"::"

SN54LS247

TEST CONDITIONSt

PARAMETER

.~-

7

I

-0.3
7

13

•

mA

-2

rnA

13

rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at VCC = 5 V, T A = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.

switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

toff

Turn·off time from A input

ton

Turn-on time from A input

eL=15pF, RL=665n,

100

toff

Turn-off time from RBI input

See Note 4

100

ton

Turn-on time from RBI input

100

100

ns
ns

NOTE 4: Load cIrcuIt and voltage waveforms are shown on page 3-11; toff corresponds to tpLH and ton corresponds to tpH L.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-357

TYPES SN54248. SN14248
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED MARCH 1974

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . .
Input voltage . . . . . . . . . . . . .
Operating free-air temperature range: SN54248
SN74248
Storage temperature range

7V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminals.

recommended operating conditions
SN54248
MIN
Supply voltage, Vee

4.5

High-level output current, 10H
Low-level output current, 10L

SN74248

NOM MAX
5

5.5

MIN
4.75

NOM MAX
5

5.25

a thru g

-400

-400

BI/RBO

-200

-200

a thru g

6.4

6.4

BI/RBO

8

8

Operating free-air temperature, T A

-55

125

0

70

UNIT
V

/lA.
mA
°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

•

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

10

Output current

TEST CONDITIONSt

MIN

TYP+ MAX UNIT
V

2
Vee= MIN,

II = :-12 mA

a thru g

Vee = MIN,

VIH = 2V,

2.4

4.2

BI/RBO

VIL = 0.8 V,

10H = MAX

2.4

3.7

Vee = MIN,

Va = 0.85 V,

-1.3

-2

a thru g

Input conditions as for VOH
Vee- MIN,

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH

High-level input current

I!L

Low-leve~

Any input
except BI/RBO

0.27

I

Short-circuit output current

lee

Supply current
. .

V
mA
0.4

V

10L = MAX

Vee

= MAX,

VI = 5.5 V

1

mA

Vee = MAX, VI=2.4V

40

p,A

except B!/RBO Vee= M.A.X. VI

-1.6

= OAV

BI/RBO
lOS

V

= 0.8 V,

Any input
input current

V

-1.5

VIL
Any input
except SI/RBO

VIH-2V,

0.8

mA

-4

SI/RBO

Vee

..

= MAX

Vee - MAX. See Note 2

53

..

-4

mA

90

mA

I

i

tFor condItIons shown as MIN or MAX. use the approproate value specIfIed under recommended operatmg cond,t,ons .
+AII typical values are at VCC = 5 V. T A = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

switching characteristics, Vee = 5 V, TA = 25° C
PARAMETER

TEST CONDITIONS

tpHL

Propagation delay time. high-to-Iow-Ievel output from A input

tPLH

Propagation delay time, low-to-high-Ievel output from A input

CL= 15pF.

tpHL

Propagation delay time. high-to-Iow-Ievel output from RSI input

See Note 5

tPLH

Propagation delay time, low-to-high-Ievel output from RBI input

MIN

TYP

MAX UNIT
100

RL = 1 kil.

100
100
100

ns
ns

NOTE 5: Load CirCUIt and voltage waveforms are shown on page 3·10.

1076

7-358

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54lS248. SN74lS248
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS248
SN74LS248
Storage temperature range

7V
7V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS248
MIN
Supply voltage, Vee

4.5

High-level output current, IOH
Low-level output current, IOL

NOM

SN74LS248

MAX

MIN

NOM

5.5

4.75

5

5

5.25

a thru g

-100

-100
-50

BI/RBO

-50

a thru g

2

6

BI/RBO

1.6

3.2

-55

Operating free-air temperature, T A

a

125

UNIT

MAX

V
p,A
mA
°e

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

10

Output current

Vee= MIN,

11=-18mA

a thru g and

Vee - MIN,

VIH-2V,

BI/RBO

VIL = VIL max, IOH = MAX
Vo = 0.85 V,

Vee = MIN,

a thru g

I

Input conditions as for VOH

a thru g

I

VOL

UNIT

IYP+ MAX

2

V

0.7

0.8

-1.5

-1.5

4.2

2.4

4.2

-1.3

-2

-1.3

-2

0.25

0.4

V
V
V

Vee- MIN,

0.25

0.4

0.35

0.5

10L = 1.6 rnA

0.25

0.4

0.25

0.4

0.35

0.5

!

10L = 3.2 rnA

I nput current at

Any input
except BilBRO

Vee = MAX,

VI =7 V

Vee = MAX,

VI = 2.7 V

Any input
except BI/RBO

0.1
20

I

i
V

VIH=2V,

maximum input voltage

mA

I

V
10L =6 rnA

VIL = VIL max

Low-level output voltage

High-level input current

MiN

MAX

2.4

10L = 2 rnA

VIL = VIL max

IIH

TYP+

VIH=2V,

BI/RBO

II

iViii~

2

Vee = MIN,

I

SN74LS248

SN54LS248

TEST CONDITIONSt

0.1

mA

20

p,A

II

i

Any input
IlL

Low-level input current

except B I/RBO Vee = MAX,

VI = 0.4 V

Short-circu it
lOS
lee

output current

BI/RBO

-0.3

Vee = MAX

Supply current

See Note 2

Vee = MAX,

-0.4 I

-0.4

-1.2

-1.2

i

BI/RBO

-2 :-0.3
25

25

38

mA

-2

rnA

38

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V. T A 25° C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 v.

switching characteristics, Vee

= 5 V, T A = 25°e

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

tpHL

Propagation delay time. high-to-Iow-Ievel output from A input

eL=15pF,

tPLH

Propagation delay time, low-to-high-Ievel output from A input

See Note 6

100

tPHL

Propagation delay time, high-to-Iow-Ievel output from RBI input

eL=15pF, RL =6 k!1,

100

tpLH

Propagation delay time, low-to-high-Ievel output from RBI input

See Note 6

100

RL =4 k!1,

100

UNIT
ns
ns

NOTE 6: Load circuit and voltage waveforms are shown on page 3-11.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-359

TYPES SN54249, SN74249
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
.... .
Input voltage . . . . . . . . . . . . .
Current forced into any output in the off state
Operating free-air temperature range: SN54249
SN74249
Storage temperature range

7V
5.5V
1 rnA

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54249
MIN
Supply voltage, Vee

4.5

5

Low-level output current, 10L

MIN

UNIT

5.25

V
V

IBI/RBO

5.5

-200

-200

I a thru g

10

10

5.5

IBI/RBO

5

8
-55

Operating free-air temperature, T A

4.75

NOM MAX

5.5

High-level output voltage, VOH
High-level output current, 10H

SN74249

NOM MAX

125

8
0

70

j.lA
mA
°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High·level input voltage

VIL

LOW-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

BI/RBO
a thru g

Low-level output voltage
Input current at maximum input voltage

II
IIH

High-level input current

IlL

Low-level input current

MIN

TVP:j: MAX UNIT
V

2

High-level output current

10H

•

TEST CONDITIONSt

Any input
except BI/RBO
Any input
except BI/RBO

Vee= MIN,

11=-12mA

Vee= MIN,

VIH = 2V,

VIL = 0.8 V,

10H = MAX

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

VOH = 5.5 V

Vee= MIN,

VIH = 2 V,

VIL = 0.8 V,

10L = MAX

Vce= MAX,

VI = 7V

2.4

0.27

Vee = MAX, VI = 2.4 V

lOS

Short-circuit output current
Supply current

tFor

..
conditions

V
V

250

j.lA

0.4

V

1

mA

40

j.lA

-1.6

Vce = MAX, VI = 0.4 V

I

mA

-4

BI/RBO
ICC

V

-1.5
3.7

Any input
except BI/RBO

0.8

BI/RBO

Vce = MAX

..
approproate value specified

shown as MIN or MAX, use the
tAli typical values are at Vee = 5 V, TA = 25°C.
NOTE 2: ICC is measured with all outputs open and all inputs at 4.5 V.

Vce = MAX, See Note 2
under recommended

..
operatong conditions .

53

-4

mA

90

mA

switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER

TEST CONDITIONS

tPHL

Propagation delay time, high·to-Iow-Ievel output from A input

tPLH

Propagation delay time, low-to-high-Ievel output from A input

CL=15pF,

tPHL

Propagation delay time, high-to-Iow-Ievel output from RBI input

See Note 5

tpLH

Propagation delay time, low-to-high-Ievel output from RBI input

MIN

TVP MAX UNIT
100

RL=667n,

100
100
100

ns

ns

NOTE 5: Load CirCUit and voltage waveforms are shown on page 3-10.

1076

7-360

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

CALLAS, TEXAS 75222

TYPES SN54LS249, SN74LS249
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage . . . . . . . . . . . . . .
Current forced into any output in the offstate
Operating free-air temperature range: SN54LS249
SN74LS249
Storage temperature range

7V
7V
. . . . 1 rnA
-55°C to 125°C
. O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS249
MIN
4.5

Supply voltage, Vee

NOM

SN74LS249

MAX

MIN

NOM

5.5

4.75

5

5

UNIT

MAX
5.25

V

High-level output voltage, VOH

a thru g

5.5

5.5

V

Hi!tl-Ievel output current, 10H

BI/RBO

-50

-50

J1.A

Low-level output current, 10L

a thru g

4

8

Bl/RBO

1.6

3.2

Operating free-air temperature, T A

-55

125

mA
°e

70

0

electrical characteristics over recommended operating free-air temperature range (m'!!ess otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage BI/RBO

10H

Vee = MIN,

11=-18mA

Vee= MIN,

VIH=2V,

VIL = VIL max, 10H = -50 J1.A
Vee= MIN,

High-level output current a thru g

I BI/RBO

2.4

Vee = MIN,

TYP:j:

V
V

-1.5

-1.5

V

4.2

0.25

2.4

4.2

V
250

0.4

0.25

I
0.25

0.4

Any input

maximum input voltage

except BI/RBO

J1.A
I

0.4
V

0.35

0.5

0.25

0.4

0.35

0.5

VIH=2V,

I

I

V
10L = 8 mA

VIL = VIL max
I n put current at

Ur-~IT

0.8

250

10L = 4 mA

MAX

0.7

10L = 3.2 mA

VIL = VIL max

Low-level output voltage

High-level input current

MIN
2

VIH=2V,

10L = 1.6mA

I

SN74 LS249

MAX

VIH=2V,

a thru g

IIH

TYP:j:

VIL = VIL max, VOH = 5.5 V

I

II

MIN
2

Vee = MIN,

VOL

SN54LS249

TEST COND!T!ONS

Vee = MAX,

VI = 7V

0.1

0.1

mA

Vee= MAX,

VI = 2.7 V

20

20

J1.A

except BI/RBO Vee= MAX,

VI = 0.4 V

II

Any input
except BI/RBO
Any input

IlL

Low-level input current

BI/RBO
Short-circuit
lOS
ICC

output current

BI/RBO

Vee = MAX

Supply current

Vee = MAX,

-0.3
See Note 2

-0.4

-0.4

-1.2

-1.2

-2
8

-0.3
8

15

mA

-2

mA

15

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
NOTE 2: ICC is measured with all outputs open and inputs at 4.5 V.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER

TEST CONDITIONS

tPHL

Propagation delay time, high-to-Iow-Ievel output from A input

eL=15pF,

MIN

TYP

MAX

RL=2kn,

100

tpLH

Propagation delay time, low-to-high-Ievel output from A input

See Note 6

100

tpHL

Propagation delay time, high-to·low-Ievel output from RBI input

eL-15pF, RL = 6 kn,

100

tPLH

Propagation delay time, low-to-high-Ievel output from RBI input

See Note 6

100

UNIT
ns
ns

NOTE 6: Load circu it and voltage waveforms are shown on page 3·11.

U.S.A

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-361

TYPES SN64261, SN64LS261. SN64S261,
SN74261, SN74LS261 (TIM99061. SN74S261
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

TTL
MSI

DECEMBER 1972-REVISED

BULLETIN NO. DL-S 7611

•
•

Three-State Versions of '151, 'LS151, 'S151
Three-State Outputs Interface Directly with
System Bus

•
•
•

Perform Parallel-to-Serial Conversion
Permit Multiplexing from N-lines to One Line
Complementary Outputs Provide True and
Inverted Data

•

Fully Compatible with Most TTL and DTL
Circuits

TYPE

MAX NO.

TYPICAL AVG PROP

TYPICAL

OF COMMON

DELAY TIME

POWER

OUTPUTS

(DTOY)

DISSIPATION

SN54251

49

17 ns

250mW

SN74251

129

17 ns

250mW

SN54LS251

49

17 ns

35mW

SN74LS251

129

17 ns

35mW

SN54S251

39
129

8 ns
8 ns

275mW

SN74S251

positive logiC: see function table

functional block diagram
---------r-----.------.

IE~:~~-,,,,,-I

01

275mW

description

•

These monolithic data selectors/multiplexers contain
full on-chip binary decoding to select one-of-eight
data sources and feature a strobe-controlled threestate output. The strobe must be at a low logic level
to enable these devices. The three-state outputs permit a number of outputs to be connected to a common bus. When the strobe input is high, both outputs
are in a high-impedance state in which both the upper
and iower transistors of each totem-pole output are
off, and the output neither drives nor loads the bus
significantly. When the strobe is low, the outputs are
activated and operate as standard TTL totem-pole
outputs.

ER 1976

SN54251, SN54LS251, SN54S251 .•• J OR W PACKAGE
SN74251, SN74LS251, SN54S251 ••. J OR N PACKAGE
(TOP VIEW)

III

02

~21

03

(1)

04

115]

06

il).

01

(12'

i

~

'e':.~~~{: : :

tSTNlI.RV,

c

A, , e

191

C

FUNCTION TABLE
INPUTS
SELECT

To minimize the possibility that two outputs will
attempt to take a common bus to opposite logic
levels, the output control circuitry is designed so that
the 'average output disable time is shorter than the
average output enable time. The SN54251 and
SN74251 have output clamp diodes to attenuate
reflections on the bus line.

OUTPUTS

STROBE

Y

W

C

B

A

S

X

x

X

H

Z

Z

L

L

L

L

DO

00
01

L

L

H

L

01

L

H

L

L

02

L

H

H

L

03

52
OJ

H

L

L

L

04

54

H

L

H

L

05

H

H

L

L

06

H

H

H

L

07

Os
66
OJ

H = high logic level, L = low logic level
X = irrelevant, Z = high impedance (off)
DO, 01 ... 07 = the level of the respective 0 input

1076

7-362

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALL.AS. TEXAS 75222

TYPES SN54251, SN74251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
Off-state output voltage
Operating free-air temperature range: SN54251
SN74251
Storage temperature range

7V
5.5V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54251
MIN
Supply voltage, Vee

4.5

NOM
5

SN74251
MAX

MIN

5.5

4.75

NOM
5

-2

High-level output current, 10H

16

Low-level output current, 10L
-55

Operating free-air temperature, T A

125

0

MAX

UNIT

5.25

V

-5.2

rnA

16

rnA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDlTlONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH
VOL

I

TYP+

MAX UNIT

2

High-level output voltage
Low-level output voltage

I o (oft) Off-state (high-impedance-state) output current
Vo

MIN

I

Output clamp voltage

Vee = MIN,

11= -12mA

Vee- MIN,

VIH - 2 V,

VIL = 0.8 V,

10H = MAX

Vee- MIN,

VIH-2V,

VIL = 0.8 V,

10L = 16mA

2.4

V
0.8

V

-1.5

V
V

3.2
0.2

0.4

Vee = MAX,

Vo = 2.4 V

40

VIH = 2 V

Vo = 0.4 V

-40

Vee = MAX,

10=-12mA

-1.5

VIH = 4.5 V

IO=12mA

Vee+ 1. 5

V

JJA
V

II

Input current at maximum input voltage

Vee= MAX,

VI = 5.5 V

1

IIH

High-level input current

Vee = MAX,

VI = 2.4 V

40

/lA

IlL

Low-level input current

Vee - MAX,

VI - 0.4 V

-1.6

rnA

lOS

Short-circuit output current!l

Vee= MAX

ICC

Supply current

Vee = MAX,

-18
All inputs at4.5 V,

All outputs open

38

rnA

-55

rnA

62

rnA

II

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-363

TYPES SN54251, SN74251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
switching characteristics, Vee
PARAMETER~

= 5 V, TA = 25°e

FROM

TO

(INPUT)

(OUTPUT)

TEST CONDITIONS

MIN

TYP

MAX UNIT

tPLH

A, B, or C

tPHL

(4 levels)

28

45

tpLH

A, B,orC

20

33

tpHL

(3 levels)

21

33

17

28

18

28

10

15

9

15

tPLH

y
W

y

Any 0

CL; 50 pF,

tpHL

RL ;400

tPLH

Any D

W

Strobe

y

tpHL

n,

See Note 2

29

45

17

27

tZL

26

40

tZH

17

27

24

40

tZH

Strobe

W

Strobe

y

tZL
tHZ

CL; 5 pF,

tLZ

RL; 400

tHZ

W

Strobe

n,

See Note 2

tLZ

5

8

15

23

5

8

15

23

ns
ns
ns
ns

ns
ns
ns
ns

~ tpLH '" Propagation delay time, low-to-high-Ievel output
tpH L == Propagation delay time, high-to-Iow-Ievel output
tZH '" Output enable time to high level
tZL '" Output enable time to low level
tHZ == Output disable time from high level
tLZ '" Output disable time from low level
NOTE 2: See load circuits and waveforms on page 3-10.

schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

II

TYPICAL OF BOTH OUTPUTS

--~vcc

vcc-------.------

--Uf

INPUT

OUTPUT

Select: Req; 6 kn NOM
Other inputs: Req; 4 kn NOM

1272

7·364

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

bALLAS, TEXAS 75222

TYPES SN54LS251, SN74LS251 (TIM9905)
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Off-state output voltage
Operating free-air temperature range: SN54LS251
SN74LS251
Storage temperature range

7V
7V

5.5V
55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74 LS251

SN54LS251
MIN
4.5

Supply voltage, Vee

NOM

MAX

MIN

5.5

4.75

5

NOM
5

-1

High-level output current, 10H

MAX

V

-2.6

mA

8

mA

70

°e

4

Low-Ieve! output current, 'OL
Operating free-air temperature, T A

-55

125

UNIT

5.25

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High·level output voltage

VOL

Low-level voltage

TYP:j:

SN74 LS251

MAX

2

MIN

TYp:j:

Vee= MIN,

II = -18 mA

Vee = MIN,

V!H = 2 V,

VIL = MAX,

10H = MAX
IOL=4mA

3.4

0.25

2.4

0.4

UNIT
V

-1.5
2.4

MAX

2
0.7

Vee = MIN,

0.8

V

-1.5

V

3.1

V

0.25

0.4

0.35

0.5

VIH = 2 V,

V
IOL =8 mA

VIL = VIL max
10(oft)

SN54LS251
MIN

Off-state (high-impedance-state)

Vee= MAX,

VO=2.7V

20

20

output current

VIH = 2V

Va = 0.4 V

-20

-20

!LA

II

Input current at maximum input voltage

Vee= MAX,

VI- 7 V

0.1

0.1

IIH

High-level input current

Vee= MAX,

VI = 2.7 V

20

20

!LA

IlL

Low-level input current

Vee = MAX,

VI - 0.4 V

-0.4

-0.4

mA

lOS

Short-circuit output current§

Vee = MAX

-130

mA

ICC

Supply current

-130

-30

-30

Vee= MAX,

Condition A

6.1

10

6.1

10

See Note 3

Condition 8

7.1

12

7.1

12

I

mA

mA

tFor conditions shown as II(1IN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
:j:AII typical values are at VCC = 5 V.:J A = 25°C.
§Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 3: ICC is measured with the outputs open and all data and select inputs at 4.5 V under the following conditions:
A. Strobe grounded.
B. Strobe at 4.5 V.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

CALLAS. TEXAS 75222

7-365

TYPES SN54LS25_1. SN74LS251 (TIM9905)
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER~

FROM
(INPUT)

tPLH

A, B,orC

tpHL

(4 levels)

tPLH
tpHL

A, B,orC

TO
(OUTPUT)

TEST CONDITIONS

MIN

TYP

MAX UNIT

29

45

28
20

33

21

33

17
18

28

10

15

9

15

30
26

45

tZL
tZH

17

27

24

40

30

45
25

ns

55
25

ns

Y
W

(3 levels)

tpLH

Any D

Y

CL=15pF,

W

RL=2kn,
See Note 4

tpHL
tpLH

Any D

tpHL
tZH

Y

Strobe

W

Strobe

tZL
tHZ

Y

Strobe

CL = 5 pF,

tLZ

RL = 2 kn,

tHZ

Strobe

W

See Note 4

tLZ

15
37
15

45

28

ns
ns
ns
ns
ns

40
ns

~ tpLH "" Propagation delay time, low-to-high-Ievel output

tpH L "" Propagation delay time, high-to-Iow-Ievel output
tZH "" Output enable time to high level
tZL"" Output enable time to low level
tHZ"" Output disable time from high level
tLZ "" Output disable time from low level
NOTE 4: See load circuits and waveforms on page 3-11.

schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

TYPICAL OF BOTH OUTPUTS

Vee

I

Req

INPUT

~

~

~~

,

.. r-

.. ~

r.7
A, B, e, S: Req = 20 kn NOM
thru 07: Req = 17 kn NOM

DO

1076

7-366

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54S251. SN74S251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Off-state output voltage
Operating free-air temperature range: SN54S251
SN74S251
Storage temperature range

7V
5.5 V
5.5 V
-55°e to 125°e
oOe to 700e
0
-65°e to 150 e

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74S251

SN54S251
MiN

NOM

4.5

Supply voltage, Vee

5

MAX

MIN

5.5

4.75

i-.lOM
5

-2

High-level output current, 10H

20

Low-level output current, 10L

125

I- 55

I Operating free-air temperature, T A

MAX

UNIT

5.25

V

-6.5

rnA

20
rnA
7n
.- I °c

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST eONDlTlONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

I VOH
VOL

MIN

TYP+

MAX UNIT

2

High-level output voltage
Low-level output voltage

I o (oft) Off·state (high-impedance-state) output current

Vee= MIN,

11=-18mA

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

10H = MAX

Vee = MIN,

VIH=2V.

VIL = 0.8 V,

10L = 20 rnA

Vee = MAX,
VIH = 2 V

I

i

V

SN54S'

2.4

3.4

SN74S'

2.4

3.2

0.8

V

-1.2

V
V

0.5

I

Vo = 2.4 V

50

I

Vo = 0.5 V

-50

V
p.A

II

Input current at maximum input voltage

Vee= MAX,

VI = 5.5V

1

rnA

IIH

High-level input current

Vee - MAX,

VI-2.7V

50

p.A

IlL

Low-level input current

Vee = MAX,

VI = 0.5 V

lOS

Short-circuit output current!<

Vee - MAX

ICC

Supply current

-40
All inputs at 4.5 V,

Vee = MAX,
All outputs open

55

I

-2

rnA

-100

rnA

85

rnA

I

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at Vee = 5 V, T A = 25°C.

§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-367

TYPES SN54S251, SN74S251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~

FROM

TO

(INPUT)

(OUTPUT)

tpLH

A, B,orC

tpHL

(4 levels)

tpLH

A, B, or C

tpHL

(3 levels)

TEST CONDITIONS

MIN

TYP

MAX UNIT

12

18

13

19.5

CL=15pF,

10

15

RL = 280 n,

9

13.5

See Note 2

8

12

tpHL

8

12

tpLH

4.5

7

tpLH

Y

W

Any 0

Y

Any 0

W

tpHL
tZH

Strobe

Y

4.5

7

13

19.5

14

21

13

19.5

CL = 50pF,

tZL

RL=280n,

tZH

See Note 2

W

Strobe

tZL

14

21

tHZ

5.5

8.5

9

14

5.5

8.5

9

14

Y

Strobe

CL = 5 pF,

tLZ

RL = 280 n,

tHZ

W

Strobe

See Note 2

tLZ

ns
ns
ns
ns
ns
ns
ns
ns

~tpLH := Propagation delay time, low-to-high-Ievel output
tpH L:= Propagation delay time, high-to-Iow-Ievel output
tZH := Output enable time to high level
tZL := Output enable time to low level
tHZ := Output disable time from high level
tLZ:= Output disable time from low level
NOTE 2: See load circuits and waveforms on page 3-10.

xW

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT

vcc

I

TYPICAL OF BOTH OUTPUTS
----------~----vcc

2.8 kn NOM

INPUT

-OUTPUT

1272

7·368

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS253, SN74LS253
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS

TTL
MSI

BULLETIN NO. DL-S 7611790, SEPTEMBER 1972-REVISED OCTOBER 1976

•

Three-State Version of SN54LS153/SN74LS153

•

Schottky-Diode-Clamped Transistors

•

Permits Multiplexing from N Lines to 1 Line

SN54LS253 ••• J OR W PACKAGE
SN74LS253 .•. J OR N PACKAGE
(TOP VIEW)
DATA INPUTS

r -____

•

Performs Parallel-to-Serial Conversion

•

Typical Average Propagation Delay Times:
Data Input to Output ... 12 ns
Control Input to Output ... 16 ns
Select I nput to Output ... 21 ns

•

Fully Compatible with Most TTL and DTL
Circuits

•

Low Power Dissipation ... 35 mW Typical
(Enabled)

~A~

______

~

~----~v~------~
DATA INPUTS

logic: see function table

description
Each of these Schottky-clamped data selectors/multiplexers contains inverters and drivers to supply fully
complementary, on-chip, binary decoding data selection to the AND-OR gates. Separate output control inputs are
provided for each of the two four-line sections.
The three-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high-impedance state) the low-impedance of the single enabled output will drive the bus
line to a high or low logic level.

logic

functional block diagram
FUNCTION TABLE
SELECT
INPUTS
A
B

OUTPUT
OUTPUT
CONTROL

DATA INPUTS
CO

Cl

C2

C3

X

X

X

X

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H

X
X

X
X
X
X
X
X

L
H

X
X
X
X
X

L
H

X
X
X
X
X
X
X

X
X

L
H

X
X
X
X

G
H
L
L
L
L
L
L
L
L

DATA'{:::~:::

Y

z

'C2.",{4,-'
1C3\31

DATA2{2::~::::

Address inputs A and B are common to both sections.
H

= high

level, L

= low

level, X

= irrelevant,

Z

=

I

----++-+-ffL.J

L
H
L
H
L
H
L
H

ZC2(12)

high impedance (off)
2C3

1131

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . . .
Off-state output voltage . . . . .
Operating free-air temperature range: SN54LS253
SN74LS253
Storage temperature range . . . .
NOTE

7V
7V
5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TeXAS 75222

7-369

TY~ES_~N54LS253, SN74~S253

DUAL 4:LlNE-TO-1-LlNE DATA S_ELECTOIJS/
MULTIPLEXERS WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

recommended operating conditions
SN54lS253
MIN
4.5

Supply voltage, VCC

SN74lS253

NOM MAX
5

5.5

MIN
4.75

5

-1

High-level output current, 10H
low-level output current, 10l

5.25

V

-2.6

mA

8

mA

70

°c

4
-55

Operating free-air temperature, T A

0

125

UNIT

NOM MAX

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

Vil
VIK

low-level input voltage
I nput clamp voltage

VOH

High-level output voltage

11=-18mA

VCC= MIN,

VIH = 2V,

VCC= MIN,

VIH=2V,

2.4

TYP+ MAX

MIN

I nput current at
maximum input voltage

VIH = 2 V

0.8

V

-1.5

-1.5

V

2.4

3.4

Vec = MAX,

VI = 7V

Vo = 2.7 V
Va = 0.4 V

V

0.7

0.4

10L =8mA

Vec = MAX,

UNIT

TYP+ MAX

2

0.25

IOl = 4mA

VI'L = VIL max

state) output current

II

VCC= MIN,

Vil = VILmax, 10H = MAX

Off-State (high-impedance
10Z

MIN
2

Low-level output voltage

Val

SN74lS253

SN54lS253

TEST CONDITIONSt

PARAMETER

i

3.1

I

0.25

0.4

0.25

0.5

20
-20

-20

0.1

0.1

20

V
V
,.,.A
mA

IIH

High-level input current

VCC = MAX,

VI = 2.7 V

20

20

,.,.A

IlL

low-level input current

VCC = MAX,

VI = 0.4 V

-0.4

mA

lOS

Short-circu it output current §

VCC = MAX'

-0.4
-130

ICC

Supply current

VCC= MAX,

-130

-30
See Note 2

-30

Condition A

7

12

7

12

Condition B

8.5

14

8.5

14

mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.,

•

+AII typical values are at VCC

=5

= 25°C.

V, T A

§ Not more than one output should be shorted at a time, and duration for the.short-circuit should exceed one second .
NOTE 2:

ICC is measured with the outputs open under the following conditions:
A. All inputs grounded.
B. Output control at 4.5 V, all inputs grounded.

switching characteristics, Vee
PARAMETERlI
tpLH
tpHL
tplH

=5 V, TA = 25°C

FROM

TO

(INPUT)

(OUTPUT)

Data

Y

Select

TEST CONDITIONS

CL=15pF,

y

See Note 3

tpHL
tZH

Output

tZl

Control

tHZ

Output

tlZ

Control

RL = 2 kn,

Y
~

Y

= 5 pF,

RL

= 2 kn,

See Note 3

MIN

TYP

MAX UNIT

17

25

13

20

30

45

21

32

15
15

28
23

27

41

18

27

ns
ns ns
ns

== Propagation delay time, low-to-high-Ievel output
tPHL == Propagation delay time, high-to-Iow-Ievel output
tZH == Output enable time to high level
tZL == Output enable time to low level
tHZ == Output disable time from high level
tLZ == Output disable time from low level

11 tpLH

NOTE 3: Load circuit and waveforms are shown on page 3-11.

1076

7-370

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

OALLAS, TEXAS 75222

TYPES SN54LS253. SN74LS253
DUAL 4-LlNE~TO-1-LlNE DATA SELECTORS/
MULTIPLEXERS WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

schematic (each selector/multiplexer, and the common select section)

CO

(6.10)

Cl

(5. II)

-+-+-+-+-+:ij.....

C3 --'(....:.3._13""")_ _

I

~VCC
TO OTHER SELECTOR/MUL TlPLEXER
(SEE FUNCTIONAL BLOCK DIAGRAM)

w ...

M

1

[JGND

VCC bus

Resistor values shown are nominal and in ohms.

PRINTED IN USA

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-371

TYPES SN54LS257A, SN54LS258A, SN54S257, SN54S258,
SN74LS257A, SN74LS258A, SN74S257, SN74S258
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS

TIL
MSI

BULLETIN NO. DL-S 7611734. OCTOBER 1976

SN54LS257A, SN54S257 •• , J OR W PACKAGE
SN74LS257A, SN74S257 ••• J OR N PACKAGE
(TOP VIEW)

•

Three-State Outputs Interface Directly
with System Bus

•

'LS257 A and 'LS258A Offer Three
Times the Sink-Current Capability
of the Original 'LS257 and 'LS258

•

Same Pin Assignments as SN54LS157,
SN74LS157,SN54S157,SN74S157,and
SN54LS158, SN74LS158, SN54S158,
SN74S158

•

Provides Bus Interface from Multiple
Sources in High-Performance Systems
AVERAGE PROPAGATION

'LS257A

s

3Y

1A

18

lY

2A

28

2Y

TYPICAL

DELAY FROM

POWER

DATA INPUT

DISSIPA TIONO

12 ns
12 ns

60mW
60mW

'S257

4.8 ns

320mW

'S258

4 ns

280mW

'LS258A

INPUTS
INPUTS
OUTPUT ~OUTPUT ~ OUTPUT
VCCCONTROL4A
4B
4Y
3A
38
3Y

SELECT ~
lY
~
2Y
GND
INPUTS OUTPUT INPUTS OUTPUT

positive logic: see function table

SN54LS258A, SN54S258 ••• J OR W PACKAGE
00ff state (worst case)

SN74LS258A, SN74S258 ••• J OR N PACKAGE
!TOPVIEW.)

description

INPUTS
INPUTS
OUTPUT
OUTPUT ~ OUTPUT
VCCCONTROL4A
48
4Y
3A
38
3Y

r--"-..

These Schottky·clamped high-performance multiplexers feature three-state outputs that can interface
directly with and drive data lines of bus-organized
systems. With all but one of the common outputs
disabled (at a high-impedance state) the low impedance of the single enabled output will drive the bus
line to a high or low logic level. To minimize the
possibility that two outputs will attempt to take a
common bus to opposite logic levels, the outputepable circuitry is designed such that the output
disable times are shorter than the output enable
times.

I

SELECT ~
lY
~
2Y
GND
INPUTS OUTPUT INPUTS OUTPUT

This three-state output feature means that n-bit
(paralleled) data selectors with up to 258 sources can
be implemented for data buses. It also permits the use
of standard TTL registers for data retention
throughout the system.

positive logic: see function table

FUNCTION TABLE
OUTPUTY

INPUTS

Series 54LS and 54S are characterized for operation
over the full military temperature range of -55°e to
125°e; Series 74LS and 74S are characterized for
o
operation from oOe to 70 e.

OUTPUT

'LS257A

'LS258A

'S257

'8258

SELECT

A

B

H

X

X

X

Z

Z

L

L

L

X

L

H

L

L

H

X

H

L

L

H

X

L

L

H

L

H

X

H

L

CONTROL

H ~ high level, L ~ low level, X

H
~

irrelevant, Z

~

high impedance (off)

1076

7-372

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

TYPES SN54lS257A, SN54lS258A, SN54S257, SN54S258,
SN74lS257A, SN74lS258A, SN74S257, SN74S258
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MUlTIPLEXERS
functional block diagrams
'LS257A, 'S257

'LS258A, 'S258

CONTROL

CONTROL

lA

lA
lY

(3)

18

(5)

2A

2Y

( 111

3A

2Y

(11)
(10)

3Y

3B

4Y

4B~

3Y

,~ ~"41
I ti--r L;

(14)

4A

(6)

28
3A

(10)

38

(5)

2A

(6)

28

lY

(3)

18

<121

4B

SELECT

SELECT

4Y

(1)

schematics of inputs and outputs

q

'LS257A, 'LS258A

EQUIVALENT OF EACH INPUT

VCC

TYPICAL OF ALL OUTPUTS

V CC

---.---VCC

Req

INPUT

Select:
All other inputs:

c
Req

--

INPUT
OUTPUT

Select:

Req ~ 9.5 kU NOM
Req = 19 kn NOM

-

'S257, 'S258

EQUIVALENT OF EACH INPUT

All other inputs:

Req

~

TYPICAL OF ALL OUTPUTS

---.---VCC

-OUTPUT

•

1.4 kU NOM

Req = 2.8

kn

NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage: 'LS257A, 'LS258A Circuits
'S257, 'S258 Circuits
Off-state output voltage . . . . . . .
Operating free-air temperature range: SN54LS', SN54S' Circuits
SN74LS', SN74S' Circuits
Storage temperature range

7V
7V

5.5V
5.5 V
-55°C to 125°C
aOc to 7aoC
-65°C to 15aoC

NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-373

TYPES SN54LS257A, SN54LS258A, SN74LS257A, SN74LS258A
QUADRUPLE 2-LlNE-TO-1-LlNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN74LS'

SN54LS'
Supply voltage, Vce

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

-2.6

mA

24
70

mA
°c

-1

High-level output current, 10H
Low-level output current, 10L

12
125

-55

Operating free-air temperature, T A

UNIT

MIN

0

electrical characteristics over recommended operating free-air
temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

TEST CONDITIONSt

Vee= MIN,

11=-18mA

Vce = MIN,

VIH=2V,

VIL = VIL max, 10H = MAX

lOS

IOL=24mA

Vee = MAX,

VIH=2V,

low-level voltage applied

Vo
S input

maximum input voltage

Any other

High-level

S input

input current

Any other

Low-level

S input

input current

Any other

= 0.4 V

Vec = MAX,
Vce= MAX,
VCC= MAX,

Short-circuit output current§

VIH=2V,

VI = 7V
VI = 2.7 V
VI = 0.4 V

Vec= MAX

•

V

-1.5

-1.5

V

2.4
0.4

3.1

V

0.25

0.4

0.35

0.5

All outputs low
All outputs off

Supply current

All outputs high

'LS257A
Vce= MAX,
See Note 2

All outputs low

20

20

p,A

-20

-20

p,A

0.2

0.2

0.1

0.1

40

40

20

20

-0.8

-0.8

-0.4

-30

All outputs high

ICC

0.8

V

VIL = VIL max

Vee = MAX,

Input current at

IlL

V

0.7

3.4
0.25

IOL=12 mA

SN74LS'
UNIT
TYp:j: MAX

2

Vo =2.4 V

Off-state output current,

IIH

2.4

MIN

VIH = 2 V,

Off-state output current,
10ZH high-level voltage applied

II

SN54LS'
TYP:j: MAX

2

Vce= MIN,

10ZL

MIN

'LS258A

1 Ai! outputs off

-0.4
-130

-30

6.2

-130
10

6.2

10

10
12

16
19

10
12

16

4.
8.8

7
14

4.5

19
7

8.8

14

12

19 ,

12

19,

mA
p,A
mA
mA

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°e.
§N.ot more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: lee is measured with all outputs open and all possible inputs grounded while achieving the stated output conditions.

kU

switching characteristics, Vee = 5 V, T A = 25°e, RL ';·667
PARAMETER~

tpLH
tpHL
tpLH

FROM
(INPUT)
Data
Select

TO
(OUTPUT)

tpZH

Output

tpZL

Control

tpHZ

Outout

tpLZ

Control

CONDITIONS

Any
Any

tpHL

CL =45 pF,
See Note 3

Any
Any

~tpLH

== propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
tpZH == output enable time to high level
NOTE 3: Load circuit and waveforms are shown on page 3-11.

'LS257A

TEST
MIN

'LS258A

TYP

MAX

12

18

1-314

TYP

MAX

12

18

12

18

12

18

14

21

14

21

14

21

14

21

20

30

20

30

20

30

20

30

CL=5pF,

18

30

18

30

See Note 3

16

25

16

25

tpZL
tpHZ
tpLZ

UNIT

I

ns
ns
ns
ns

== output enable time to low level
== output disable time from high level
== output disable time from low level

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
Instruments reserves the right to change or discontinue this product without notice.

MIN

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN54S257, SN54S258, SN74S257, SN74S258
QUADRUPLE 2-UNE-TO-1-UNE DATA SELECTORS/MULTIPLEXERS
recommended operating conditions
SN54S257, SN54S258
MIN
Supply voltage, Vee

4.5

SN74S257, SN74S258

MAX

MIN

NOM

MAX

5

5.5

4.75

5

5.25

V

-6.5

rnA

20

rnA

70

°e

-2

High-level output current, 10H
Low-leI(el output current, 10L

20
-55

Operating free-air temperature, T A

UNIT

NOM

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH
VIL

LoW'level input voltage

ViK

Input clamp voltage

VOH

High-level output voltage

'VOL

Low-level output voltage

Vee= MIN,

Ij=-18mA

Vee- MIN,

VIH = 2V,

V-'L.

Off-state output current,
'

lOS

OAV
.- -,

I SN74S'

V

-i.2

-1.2

V

2.4

3.4

2.4

3.2

d

Vee= MAX, VI = 5.5V

High-level

S input
Any other

LO'J"J-!s'..'e!

S input

input current

Any other

Vee = MAX, VI = 2.7 V
I

Short-circuit output current§
Supply current

V

3.2

-?O .....

Vee = MAX, VI = 0.5 V

44

V

0.51

0.51

V

50 "

50

IJ.A

-50

-50

IJ.A

1

1

rnA

100

100

50

50

-4

-4

-2

-2

-100

-40

Vee= MAX

UNIT

0.8

3.4

VO=0.5V

input current

MAX

0.8

2.4

VIH = 2 V,
·UL.

TYp:j:

2.4

All outputs high
ICC

MIN
2

Vee = MAX, VIH = 2 V,

low-level voltage applied
input voltage

IlL

MAX

VO=2.4V

high-level voltage applied

I nput current at maximum

IIH

TYp:j:

Vee = MAX, VIH= 2V,

Off-state output current,

II

I SN54S'

VIL = 0.8 V, 10H = MAX
Vee = MIN,

10ZL

MIN
2

High-level input voltage

10ZH

SN545257, SN74S257 SN54S258, SN74S258

-100

-40

68

36

56

All outputs low Vee = MAX, See Note 2

60

93

52

81

All outputs off

64

99

56

87

,

p.A
rnA
rnA
rnA

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with all outputs open and all possible inputs grounded while achieving the stated output conditions.

switching characteristics, Vee
PARAMETER~

tpLH

= 5 V, TA = 25°e, RL = 280 Q

FROM

TO

TEST

(INPUT)

(OUTPUT)

CONDITIONS

Data

Any

SN54S257, SN74S257
MIN

Select

tpHL
tpZH

Output

tpZL

Control

tpHZ

Output

tpLZ

Control

Any

~ tp LH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
tpZH '= output enable time to high level
NOTE 4: Load circuit and waveforms are shown "on pages 3-10_

SN54S258, SN74S258

MAX

MIN

TYP

MAX

5

7.5

4

6.5

4

6

eL=15pF,

8.5

15

8

12

See Note 4

8.5

15

7.5

12
19.5

6

13

19.5

13

14

21

14

21

eL - 5 pF,

5.5

8.5

5.5

8.5

See Note 4

9

14

9

14

Any
Any

TYP
4.5

tpHL
tpLH

•

UNIT
"ns
ns
ns
ns

tpZL'= output enable time to low level
tPHZ '= output disable time from high level
tpLZ'= output disable time from low level

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

1-315

TTL
MSI

TYPES SN54259. SN54LS259. SN74259. SN74LS259 (TIM9906)
8~BIT ADDRESSABLE LATCHES
BULLETIN NO. DL-S 7612347, OCTOBER 1976

•

•
•
•
•
•
•
•

•

•

8-Bit Parallel-Out Storage Register
Performs Serial-to-Parallel Conversion With
Storage
Asynchronous Parallel Clear
Active High Decoder
Enable/Disable Input Simplifies Expansion
Direct Replacement for Fairchild 9334
Expandable for N-Bit Applications
Four Distinct Functional Modes
Typical Propagation Delay Times:

SN54259, SN54LS259 •. , J OR W PACKAGE
SN74259, SN74LS259 ... J OR N PACKAGE
(TOP VIEW)
EN·
CLEAR ABLE

~

Q7

os

05

04

Q1

02

Q3

GND

D
B

'LS259
'259
Enable-to-Output. .. 12
17
Data-to-Output .... 12
18
20
Address-to-Output .. 16
16
20
Clear-to-Output
Fan-Out
IOL (Sink Current)
'259 ............. 16 mA
SN54LS259 ....... 4 mA
SN74LS259 ....... 8 mA
IOH (Source Current)
'259 ............. -0.8 mA
'LS259 ........... -0.4 mA
Typical ICC
'259 ............. 60mA
'LS259 ........... 22 mA

C

ABC

QO

~

~

LATCH SEL

OUTPUTS

logic: see function table

description

FUNCTION TABLE

These 8-bit addressable latches are designed for
general purpose storage applications in digital systems. Specific uses include working registers, serialholding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of
storing single-line data in eight addressable latches,
and being a 1-of-8 decoder or demultiplexer with
active-high outputs.

•

OUTPUTS

DATA
IN

INPUTS
CLEAR

Four distinct modes of operation are selectable by
controlling the clear and enable inputs as enumerated
in the function table. In the addressable-latch mode,
data at the data-in terminal is written into the
addressed latch. The addressed latch will follow the
data input with all unaddressed latches remaining in
their previous states. In the memory mode, all latches
remain in their previous states and are unaffected by
the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, the
enable should be held high (inactive) while the
address lines are changing. In the 1-of-8 decoding or
demultiplexing mode, the addressed output will
follow the level of the D input with all other outputs
low. In the clear mode, all outputs are low and
unaffected by the address and data inputs.

G

OUTPUT OF

EACH

ADDRESSED

OTHER

FUNCTION

OUTPUT

LATCH

Addressable Latch

H

L

D

GiO

H

H

GiO

GiO

L

L

D

L

8-Line Demultiplexer

L

H

L

L

Clear

Memory

LATCH SELECTION TABLE
SELECT INPUTS
C

B

LATCH
ADDRESSED

A

L

L

L

L

L

H

L

H

L

I

0
1

2

L

H

H

3

H

L

L

4

H

L

H

5

H

H

L

6

H

H

H

7

H"" high level, L "" low level
D;; the level at the data input
0iO =' the level of 0i (i = 0, 1, ... 7, as appropriate) before the indio
cated steady·state input conditions were established.

1076

7-376

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54259, SN54LS259, SN74259, SN74LS259 CTIM99061
8-BIT ADDR~SSABLE LATCHES
schematic of inputs and outputs
-'259

EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS
- - - - - - - - - -......- - - VCC
100

Vcc------~-----

n

NOM

INPUT
'----.....- - - OUTPUT

Latch select, data in, or clear: Req

=4

kn NOM

Enable:
=
kn
_______________________________________
Rcq

2_2

NOM

I I_______________________________________________________

~I

~I

'LS259

'LS259

EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

~

--~VCC
__

VCC
Req

INPUT

= 17

~~

kn NOM

-

Dol
..,-..

~120nNOM

L...-_ _....._ _ _

OUTPUT

•

~,
....

~~

n7

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (see Note 1)
Input voltage: SN54259, SN74259 . .
SN54LS259,SN74LS259
Operating free-air temperature range: SN54259, SN54LS259
SN74259,SN74LS259
Storage temperature range

. 7V

5.5 V
. 7V

-55°C to 125°C
oOe to 70°C
. -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-377

TYPES SN54259,SN74259
8-BIT ADDRESSABLE LATCHES

recommended operating conditions
SN54259

SN74259

MIN NOM MAX

MIN NOM MAX

Supply voltage, Vee

4.5

5

High-level output current, 10H

4.75

5.5
-800

Low-level output current, 10L

V

-800

JlA

16

mA
ns

16
15

15

15i

15t

5t

5t

Width of clear or enable pulse, tw
Data

Setup time, tsu

Address
Data

Hold time, th

Address

Operating free-air temperature, T A

ot

ot

20t

20t

-55

125

UNIT

5.25

5

ns
ns
70

0

°e

tThe arrow indicates that the rising edge of the enable pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
MIN
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

I

High-level output voltage
Low-level output voltage

II

Input current at maximum input voltage

IlL

2

V

0.8

High-level input

Enable

current

Other inputs

Low-level input

Enable

current

Other inputs

Vee = MIN,

II = 12 mA

Vee = MIN,

VIH = 2 V,

VIL = 0.8 V,

IOH = --800 JlA

Vee = MIN,

VIH = 2 V,

VIL = 0.8 V,

IOL = 16mA

Vee = MAX,

VI = 5.5 V

Vee = MAX,

VI = 2.4 V

Vee = MAX,

VI = 0.4 V

lOS

Short-circuit output current§

Vee= MAX

ICC

Supply current

Vee = MAX,

-1.5
I

UNIT

MIN TYP:j: MAX

TYP:j: MAX

2

VOL

IIH

SN74259

SN54259

TEST CONDITlONSt

PARAMETER

2.4

3.4

0.8
-1.5

I

!

0.2

2.4

3.4

1

80

80

40

40

-3.2

-3.2

See Note 2

60

-18

V
V

JlA
mA

-57

mA

90

mA

60

90

!

mA

-1.6

-1.6
-57

I

0.4

1

V
V

i

0.2

0.4

-18

:

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC ~ 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time,
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee = 5 V, TA = 25° C

I

PARAMETER

I
I

tPHL
tpLH

Clear

Any Q

Data

I

TEST CONDITIONS

Any Q

I

MIN

TYP

MAX

16

25

14

24

eL=15pF,

11

20

RL = 400n,

15

28

See Note 3

17

28

12

20

11

20

tPLH

== propagation delay time.
== propagation delay time,

Address
Enable

Any Q

Any Q

I UNIT
I

tPLH

tPHL

tPH L

TO
(OUTPUT)

tpHL
tPHL

tpLH

FROM
(INPUT)

ns
ns
ns
ns

low-to-high-Ievel output
high-to-Iow-Ievel output

NOTE 3: Load circuit is shown on page 3-10.

1076

7-378

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS259, SN74LS259 ITIM9906)
8-BIT ADDRESSABLE LATCHES
recommended operating conditions
SN54LS259

SN74 LS259

MIN NOM MAX

MIN NOM MAX

Supply voltage, Vee

4.5

5.5

5

High-level output current, IOH

4.75

5

-400

Low-level output current, IOl
Width of clear or enable pulse, tw

Hold time, th

J.lA

8

mA
ns

15

Data

15T

15t

Address

15t

15t

Data

ot

ot

Address

ot

ot

Operating free-air temperature, T A

V

-400

4
15

Setup time, tsu

UNIT

5.25

125

-55

ns
ns

0

°e

70

tThe arrow indicates that the rising edge of the enable pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

I

PARAMETER
VIH

IM!~

High level input voltage

VIL

Low level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

Vee= MIN,

II = -18 mA

Vee = MIN,

VIH = 2 V

VIL = VIL max,

IOH = -0.4 mA

Vee = MIN,

VIH = 2 V,

VIL = VIL max.
Input current at maximum

II

f---=SN:.:.54:....:..::L==S:::2=59=---t_-'S:::.N::.:7c.::4:.=L=S2:::5::::9~-I UNIT

TEST eONDITIONSt

input voltage

2.5

TYP+

IM!~

VI =7V

MAX
0.8

V
V

2.7
0.4

IIH

High-level input current

Vee = MAX,

VI=2.7V

20

IlL

Low-level input current

I Vee= MAX.

VI=0.4V

-0.4

lOS

Short-circuit output current§

Vee = MAX

ICC

Supply current

Vee = MAX.

-20

-100
22

V

-1.5
3.4
0.25

0.4

0.35

0.5
0.1

V
mA

20 1 ;.tA
-20

36

-0.4

mA

-100

mA

36

mA

22

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time, and duration short-circuit should not exceed one second.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
tpHL
tPLH

FROM

TO

(INPUT)

(OUTPUT)

Clear

Any Q

Data

Any Q

TEST CONDITIONS

tPHL
tPLH

RL = 2 kU,
Address

Any Q

tpHL
tpLH

eL=15pF,

Enable

See Note 3

Any Q

tPHL

MIN

TYP

I

V

0.1

See Note 2

I

0.7

iloL =8 mA

Vee = MAX.

TYpt

-1.5
3.4
0.25

llOL =4 mA

MAX

MAX

17

27

20

32

13

21

24

38

18

29

22

35

15

24

I
J

•

UNIT
ns
ns
ns
ns

tpLH == propagation delay time. low-to-high-Ievel output
tpHL == propagatiOn delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit is shown on pa!!e 3-11.
•

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-379

TIL

TYPES SN54LS261, SN74LS261
2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS

MSI

BULLETIN NO. DL·S 7612123. MARCH 1974-REVISED OCTOBER 1976

•

Fast Multiplication ... 5-Bit Product in 26 ns Typ

•

Power Dissipation ... 110 mW Typical

•

Latch Outputs for Synchronous Operation

•

Expandable for m-Bit-by-n-Bit Applications

•

Fully Compatible with Most TTL and Other
Saturated Low-Level Logic Families

•

Diode-Clamped Inputs Simplify System
Design

SN54LS261 ••• J OR W PACKAGE
SN74LS261 ..• J OR N PACKAGE
(TOP VIEW)
OUTPUTS

62

VCC

61

60

~

MO

M1

00

G

01

01

description
These low-power Schottky circuits are designed to be
used in parallel mUltiplication applications. They
perform binary multiplication in two's-complement
form, two bits at a time.

63

M2~

FUNCTION TABLE
INPUTS
LATCH
CONTROL

The SNS4LS261 is characterized for operation over
the full military temperature range of -ssoe to
o
12S e; the SN74LS261 for operation from oOe to
o
70 e.

OUTPUTS

MULTIPLIER
M2

M1

MO

L

X

X

X

H

L

L

L

G

The leading (most-significant) bit of the product is
inverted for ease in extending the sign to square (left
justify) the partial-product bits.

04

Q3

Q2

Q1

QO

040 030 02 0 01 0 000
H
L
L
L
L
B4

B3

B2

Bl

B4

B3

B2

Bl

H

B4
B4
B4

B3

B2

Bl

BO

L

L

B4

83

82

81

80

H

L

L

H

H

L

H

L

H

L

H

H

H

-

H

H

L

H

B4

82

81

H

H

L

84

B4
B4

B3

H

83

82

181

H

H

H

L

L

L

L

H

IH

H ; high level. L; low level. X ; irrelevant
040 ..• aoo ; The logic level of the same output before the
high-to-Iow transition of G.
B4 •.. BO; The logic level of the indicated multiplicand (B) input.

schematics of inputs and outputs

TYPICAL OF QQ. Q1. Q2. Q3 OUTPUTS

TYPICAL OF

---~t--Vcc

VCC--'---

GND

OUTPUTS

positive logic: see description

The outputs represent partial products in one'scomplement form generated as a result of mUltiplication. A simple rounding scheme using two additional
gates is needed for each partial product to generate
two's complement.

EQUIVALENT OF EACH INPUT

LATCH
CONTROL

G

The M inputs are for the multiplier bits and theB inputs
are for the multiplicand. The Q outputs represent the
partial product as a recoded base-4 number. This
recoding effectively reduces the Wallace-tree
hardware requirements by a factor of two.

•

B4

04 OUTPUT
-----+-VCC

17 kn NOM
INPUT.....,.~

_ _....
OUTPUT

OUTPUT

G: R eq ;17knNOM
B or M2: Req; 20 kn NOM

MO or MI:Re

= 10 kn

NOM

1076

7·380

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE

sox

5012

•

DALLAS, TEXAS 75222

TYPES SN54LS261, SN14LS261
2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS
functional block diagram
BO (13)

•

MO

M1--.......~

374

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-381

TYPES SN54LS261, SN74LS261
2-BIT-BY-4-BIT PARALLEL BINARY MULTIPLIERS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . . . . . . . . .
Operating free·air temperature range: SN54LS261
SN74LS261
Storage temperature range

7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS261
Supply voltage, Vee

SN74LS261

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

-400

jJ.A

8

mA

High-level output current, 10H

-400

Low-level output current, 10L

4

Setup time, tsu
Hold time, th

ns

25

25

Any M input

17.[

17.[

Any B input

15.[

15.[

Any M input

0.[

OJ,

Any B input

OJ,

Width of enable pulse, tw

ns
ns

0,[

-55

Operating free-air temperature, T A

UNIT

MIN

125

°e

70

0

.[ The arrow indicates that the falling edge of the enable pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

•

MIN

TYPt

SN74LS261

MAX

MIN

VOL Low-level output voltage
Input current at
maximum input voltage

Vee - MIN,

11--18mA

Vee = MIN,

VIH=2V,

VIL = VIL max,

10H =-400jJ.A

Vee= MIN,

VIH = 2 V,

2.5
10L = 4 mA

TYPt

0.8

V

-1.5

-1.5

V

2.7

3.4
,0.25

V

0.7

0.4

3.4

V

0.25

0.4

,0.35

'0.5

VIL = VIL max

10L - 8 mA

Vee= MAX,

MOorMI
All others

0.2

0.2

0.1

0.1

MOorMI

40

40

All others

20

20

MOorM!

-0,8

All others

-0.4

-0.8
-0.4

VI = 7 V

IIH

High-level input current

Vee = MAX,

VI = 2.7 V

IlL

Low-level input current

Vee = MAX,

VI = O.4'V

lOS

Short-circuit output current~

Vee = MAX

ICC

Supply current

Vee - MAX,
OUtputsopen ,

,

All inputs at 0 V,

UNIT

MAX

2

2

VOH High-level output voltage

II

SN54LS261

TEST CONDITIONSt

PARAMETER

-20

-100

22

38

-20
20

V
mA
jJ.A
I

rnA

-100

mA

40

mA

tAli typical values UT

"l-I!f.!--t-- OUTPUT
OUTPUT

G:

Enable
Req = 18 k!1 NOM
Others: Req = 6 k!1 NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage: 'LS275 . . . .
'S274, 'S275
Off·state output voltage: 'LS275
'S274, 'S275
Operating free-air temperature range: SN54LS, SN54S Circuits
SN74LS, SN74S Circuits
Storage temperature range

· 7V
· 7V

5.5 V
· 7V

5.5V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

10j

7-392

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS215, SN14LS215
1-BIT-SLICE WALLACE TREES WITH ~-STATE OUTPUTS
recommended operating conditions
SN54LS275

SN74LS275

MIN

NOM

MAX

MIN

NOM

4.5

5

5.5

4.75

5

Supply voltage, Vee
High-level output current, 10H

-1

Low-level output current, IOL

12

Operating free-air temperature, T A

-55

125

0

UNIT

MAX
5.25

V

-2.6

mA

24

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

Vee= MIN,

11=-18mA

Vee = MIN,

VIH = 2 V,

VIL = VILrnax

V,...,... VOL

~.~IN

Low-level output voltage
VIL = VILrnax

IOZH
10ZL
II
IIH
IlL

MIN

TYP:j:

MAX

MIN

2

High-level output voltage

VOH

SN54LS275

TEST eONDITIONSt

Off-state output current,

Vee = MAX,

high-level voltage applied

Vo

Off-state output current,

Vee= MAX,

low-level voltage applied

Va = 0.4 V

Input current at

Enable G

maximum input voltage

All others

High-level

Enable G

input current

All others

Low-level

Enable G

input current

All others

= 2.7

Vee
Vee
Vee

= MAX,
= MAX,

Short-circuit output current§

Vee = MAX

lee

Supply current

Vee

V

0.7

0.8

V

-1.5

-1.5

V

2.4
3.2
2.4
3.1
IOH = MAX
I.
..
- .
- ~1_IO_L__
=_I_~_m_A-+I______U_.~_b____U_._441_______
U_.l_b____u_.4~1

I iOL = 24 rnA

0.35

VIH = 2 V,
VIH = 2 V,

VI =7V
VI
VI

= 2.7 V
= 0.4 V

J.l.A

-20

-20

J.l.A

0.1

0.1

0.3

0.3

20

20

-130
25

mA
J.l.A

60

I

-0.4

-1.21

= MAX

V

0.5
20

-0.4
-30

V

20

60

I
1

lOS

UNIT

2

V

= MAX,

SN74LS275
TYp:j: MAX

I

-1.21
-30

40

25

mA

-130

mA

40

mA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC

=5

V, T A

= 25°C.

§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

switching characteristics, Vee = 5 V, TA
PARAMETER~

tpLH
tpHL

= 25°e

FROM

TO

(INPUT)

(OUTPUT)

Any Slice or earry

Any

Any Enable

Any

TEST CONDITIONS
eL =45 pF,

RL = 667 .n,

See Note 2

tpZH
tpZL
tpHZ

eL=5pF,
See Note 2

tpLZ
~

RL

= 667.n,

MIN

TYP

•

MAX UNIT

41

62

44

66

15

23

15

23

10

15

10

15

ns
ns
ns

tpLH == Propagation delay time, low-to-high-Ievel output
tpHL == Propagation delay time, high-to-Iow-Ievel output
tpZH == Output enable time to high level
tpZL == Output enable time to low level
tpHZ == Output disable time from high level
tpLZ == Output disable time from low level

NOTE 2: Load circuit and voltage waveforms are shown on page 3-11.

1076

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
I nstruments

reserves the right to change
continue this product without notice.

or dis-

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-393

TYPES SN54S274, SN54S275, SN74S274, SN74S275
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
recommended operating conditions
SN74S274

SN54S274

Supply voltage, Vee

MIN

NOM

MAX

MIN

NOM

4.5

5

5.5

4.75

5

High-level output current, 10H

MAX

-2

Low-level output current, 10L

12

Operating free-air temperature, T A

-55

UNIT

SN74S275

SN54S275

125

0

5.25

V

-6.5

rnA

12

rnA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN74S274

SN54S274
PARAMETER

TEST CONDITIONSt
MIN

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

TYP:!:

MAX

VOL Low-level output voltage
Off-state output current,

Vee= MIN,

II = -18mA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10H = MAX

Vee= MIN,

VIH = 2V,

VIL = 0.8 V,

IOL=12mA

Vee= MAX,

VIH=2V,

10ZH high-level voltage applied

Vo = 2.4 V

Off-state output current,
10ZL
.
low-level voltage applied

Vee= MAX,

2.4

Vee= MAX,

VI - 5.5 V

V

0.8

0.8

V

-1.2

-1.2

V

3.4

2.4

Vo =0.5 V

Input current at maximum input voltage

UNIT

MAX

2

VIH=2V,

II

TYP:!:

MIN

2

VOH High-level output voltage

•

SN74S275

SN54S275

V

3.2

0.5

0.5

V

50

50

J.IA

-50

-50

J.IA

1

1

rnA

IIH

High·level input current

Vee= MAX,

VI = 2.7V

25

25

J.IA

IlL

Low-level input current

Vee = MAX,

VI = 0.5 V

-0.25

-0.25

rnA

lOS

Short-circuit output current§

Vee = MAX

-100

rnA

lee

Supply current

Vee = MAX

155

rnA

-30

switching characteristics over recommended ranges of T A and
PARAMETERl1

FROM

TO

(INPUT)

(OUTPUT)

Vee

tpLH

Any A or B ('5274), or
Any Slice or Carry ('5275)

TEST CONDITIONS
CL=30pF,

Any

tPZL
tpHZ

eL=5pF,
Any Enable

Any

RL = 400 n,
See Note 3

tPLZ
1 For

105

SN54S274

SN74S274

SN54S275

SN74S275

TYP:!:

MAX

50

95

50

MIN

UNIT

TYP:!:

MAX

50

70

95

50

70

15

45

15

30

15

45

15

30

10

40

10

25

10

40

10

25

RL=400n,
See Note 3

tpZH

155

(unless otherwise noted)

MIN
tPHL

-30

-100
105

i

I

ns

ns
ns

conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

:!:AII typical values are at VCC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
11 tPLH ;: Propagation delay time, low-to-high-Ievel output
tPH L;: Propagation delay time, high-to-Iow-Ievel output
tPZH ;: Output enable time to high level
tPZL;: Output enable time to low level
tPHZ ;: Output disable time from high level
tpLZ ;: Output disable time from low level
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-394

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS275, SN54S274,SN54S275, SN74LS275, SN74S274, SN74S275
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
TYPICAL APPLICATION DATA

~sub-mult:iplepartial~uctbi1s

~sub-multiplepartialprQductbits

that tontribute to1he

thatcontributa to the;i"+O product
(See Note AI

2"+0 product

{See Note A)

~

~
....--4-..j....4-l--t-iI-+--..., :07~n==ondelaytime

';;7inputsperbit·s1ice

- --, ~;=::~!s~~deJaytime
I

,..-I,-~""""',....J:-iL.:-t

1 package per bit-slice

I

I
: -r2 -r'
2""':
2"+~ carrybittOthe2"~~ tree _ • • • • oJ"" ... ']"'
0
2"''''''Yb;'1o",e2".'''''''1=
.. 1. I.
'LS275/'S275

_, I.

......

tothe2"""' product.UsuaJly

IT.." '''''''''OIBA'

•

3-INPUT

•

:

ADDER

:

:~r··v

. ""."'~'''''_t''DU'''y
this carry bi1: andthe:z"l+l
productoutput(from'then+l
Wallace tree) are fed intDa

I
_">~ ca~bi~

I

c-r'

I

I
I

_. L---~ti~

I

2' ..... car::rbitthatcontnbtltesy2""""Pfoductoutput

to1he:zn product.Usuaily
'
thiscanybitandthe2"+1

2""'",oductoutput

proouctoutput(from%hen+l

Wallace tree} are fed into a
summing adder.

summmgackier.

FIGURE 1-BASIC BIT -SLICE WALLACE TREE

~

FIGURE 2-HIGH-SPEED BIT-SLiCE WALLACE TREE

7 inputs per bit-slice

61 ns typical propagation delay time
1 1/4 packages per bit-slice
BIT SLICE

BIT SLICE

BIT SLICE

See
Note A

To next CO

To n+2
tree

•

BIT SLICE

~------------------------~vr-----------------------J
To final summing adder

FIGURE 3-MODERATE-SPEED BIT -SLICE WALLACE TREE

NOTE A:

All unused inputs must be grounded.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-395

TYPES SN54LS215,SN54S214, SN54S215, SN14LS215, SN14S214·, SN14S215
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
1-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
TYPICAL APPLICATION DATA
'" 15 inputs per bit·slice
101 nstypicalpropagationdelaytime

31/2,-"

~+-------~--+-~-------... }romn-1
}::~....
See
Note
A

. - - - - - , .... From n-2 Tree
Fromn-1 Tree

I
I

SeeN01IIC

L ________ _
~
To Final Summing Adder

NOTES:

A. Ground unused inputs.
B. These outputs from preceeding trees may go to any of the inputs of the 'LS275";'S275.
C. The circuit within the dotted lines may be either the basic bit-slice Wallace tree or the high-speed Wallace tree. I n the latter case
both carry inputs of the 'LS2751'S275 must be grounded.

FIGURE 4-15-BIT-SLICE WALLACE TREE FOR 32-BIT X 32-BIT MULTIPLIER

•

See Note A

'LS275/

!"' -'5275 .,

I

i
i
i
i

(27 Bits)

i

DETAIL A

L.

r~

________________

~

'-----------'j1

iL._._._._._._._. __
DETAIL A

2"+2 bit from 2"-2 tree
2"+1 bit from 2"-1 tree
"2'+2 bit to 2"'+2 tree
:z"+1 bit to 2"+1 tree

2"

~
To final summing adder

NOTES:

A. Ground unused inputs.
B. The number of bits in parentheses is the maximum number of bits this tree can combine if the remaining 'LS2751'S275 (all having
a higher number in the parentheses) were not connected.

FIGURE 5-7-TO-31-BIT-SLICE WALLACE TREE FOR UP TO 64-BIT X 64-BIT MULTIPLIERS

107'

7·396

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS275, SN54S274,SN54S275, SN74LS275, SN74S274, SN74S275
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
TYPICAL APPLICATION DATA

'·_·_·_·_·_·_·_·-1
. 2 upper half of n X iower half of

11

•

,·_·_·_·....l·_·_·_·,·_·_·_·_·-1.·_·_·_·_·

1.
i.1 upper
half of n X 2upper half of n . 210wer half of n X 210wer half of n
. _._._.,._._._.-1.._._._._.,._._._._)
. 210wer half of n X 2upper half of n

.

L.!._._._._._._._._I
NOTE A: The left·hand half of each rectangle is the portion of
word one used to obtain the product shown within the
rectangle. Similarly, the right-hand half of each rectangle
is the portion of word two used.

FIGURE 6-UNIVERSAL METHOD OF

I
1I
I I I

%

ADDING
-BIT PRODUCTS TO
OBTAIN AN n-BIT PRODUCT

I

~I I~I i i i I

I~H

•

1(/)1 1

I~I t

I I I

1

I~I I I I I I~I~I~I~I I I I I I~I
1;1 I I I 1 I~I~I~I~I I I I I I~I
It-I I I I 1 I~I~I~I~I 1 I I I I~I
CO

:-·(21S-;;;231·;x·(20·-;21s·)-!
L(~~~·~!4!~~~·~)_·~·.E°~·~~~·~·~2~._j

r-·_·_·_·-L.·_·_·_·_·_·_-_·_·-1.·_·_·_·_· 1

L.E~~.~~)~_~6...!?~1.~i

I~J 1 I I I I~ I~ I~ I~ I I I I I e~1
N
I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~I~-I

FIGURE 7-METHOD OF ADDING
32-BIT PRODUCTS TO OBTAIN A
64-BIT PRODUCT

~

~&4

It.

64 MULTIPLIER ARRAY

~

~

~

~

~

~

~

~

~

~

~

~

~

FIGURE a-FINAL PRODUCTS AND
ARRAY SUBPRODUCT ADDITIONS FOR
32-BIT X 32-BIT MULTIPLIER

•
I I
I II
I II I I
I I I II I
II III I
I I I II I
I I I I I I
I II II I
I ~I I I I I
I~I I I I I
I~I I I I I
I{I 1 I 1 I
I~I 1 I I I
[if I I 1 I I
[!U:I:I~I:I

I I
I I
I I I
II I
I I I
I I I
I I I
I I I
I I ~I
I I ~I
l::ll ~I

I

I I
I I I
I I I I
I I I I I I
I I I I I I
I I I I I I
I I l::ll::ll::ll
I I I~I~I~I
I I I~I~I~I
I 1 I~I~INI
1 1 1:1:1:1

I

I
I I I
I! I I
I I I I
i I I I
I l::ll::ll
1 I~I~I
1 I~I~I
I I~I~I
1 1:1:1
I

I

I

I I
I I I
I
l::ll::ll::ll l::ll I
I~I~I~I I~I I
I~I~I~I I~I I
1:<:1~11l1 1;:;1 I
I:I:I~I 1:1 I

I I I
l::ll::ll

I~I~I
I~I~I

I:<:I~I

I~I:I

I
I I I
I I I I
I I I I
I I II
I I I I
I I I I
I I I I
I I l::ll
1 I I~I 1~lil
I I I~I I~I':I
I 1 I~I 1;;17-..1
I I~I~I~I~I~I

NOTE A: See Note B of Figure 6 for designing trees with any number of inputs up to 31.

AGURE 9-ARRAY ARRANGEMENT FOR VARIOUS MULTIPLIERS
INCLUDING ARRAYSUBPRODUCT ADDITIONS FOR 64-BIT X 64-BIT
MULTIPLIER
1076

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INSTRUMENTS
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•

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7-397

TYPES SN54LS215.SN54S214. SN54S215. SN14LS215. SN14S214. SN14S215
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
1-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
TYPICAL APPLICATION DATA

. ~.

L.....----J~ &.

~

0

a.c:
0

'+'

E

~

b

i

:0

2
M

~
N
.,.,

.r:

en
~

~
:J
C>

u::

.,
OJ

en

~
"0

•

0

a.

iii

z

0

i=

u
w

Z

z

0

u
~
::>

Q.
~

::>
0
I
CO)

II..

...0
~

W
W

J:

~
II:
W

:i
Q.

i=

..J

iii

::>
:E

"5
0.

iii

.-'"

X

.,

.c

~

~
~

iii

~ I
~ ::!
:c w
cD

:c
.;.

:c
I-

II:

::>

CI

u::

*

1076

7-398

TEXAS INSTRUMENTS
INCORPORATED

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•

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o-J

c:=
]
=-r";;-

Ol

1:1
~

/

4

'I,

/~:F-

4

22722622522

.

J

'/

r----

,),~:~r::l,

J--

m

(I)
(I)

4

8,
I

Z
U"I

~

....
,f:IiI

(I)

~
I

C:.:":",,,4
J. L':r=:n,,,J
r

12

J

"'a

'S274

~·f
217~

223222221220

8,

....
-<

_~ _ _

16.

~ 4/

}

N

.....
U"I

=(I)

~z
U"I
..... -<,f:IiI

=

~

."

n
»
r

g,~(I)

....
=I N
.....
1_,f:IiI
(I)
.... _

n

!::=(I)
n_Z
mZU"l
:el>,f:IiI
_::xli(/)
--l> .....

7
217

7
2 16

-I-I,f:IiI
mm'(n

OOZ

CC .....
-I-I,f:IiI

-a-acn

CCN
-1-1 .....

en en

U"I

TYPES SN54LS275,SN54S274,SN54S275, SN74LS275, SN74S274, SN74S275
4-BIT-BY-4-BIT BINARY MULTIPLIER WITH 3-STATE OUTPUTS
7-BIT-SLICE WALLACE TREES WITH 3-STATE OUTPUTS
TYPICAL APPLICATION DATA

•

*Each starred block may be either a basic bit-5lice Wallace tree('LS275 or 'S275 only) or a high-5peed bit-slice Wallace tree ('LS275 plus 1/2
'LS183 or 'S275 plus 1/2 'Hl83). In either case the function of the terminal is the same as the similarly located terminal of the basic biHlice
(Figure 1) or high-speed biHlice Wallace tree (Figure 2). Also for either tree, when only five inputs of the seven-input adder of the
'LS275/'S275 are used, the remaining two inputs must be grounded. When the high-5peed adder is used, the C2 n inputs of the 'LS275/'S275
must be grounded.

t For

improved performance SN74LS181/SN74S181 ALUs with SN74S182 look-ahead generators can be substituted
SN74283/SN74LS283/SN74S283 adders. Typically, the multiplication time will be reduced by 18 to 32 nanoseconds.

for

the

FIGURE 10-16-BIT X 16-BIT MULTIPLIER
(SHEET 3 OF 3-SUMMING PARTIAL PRODUCTS)

1076

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TTL

TYPES SN54276, SN74276
QUADRUPLE J-K FLIP-FLOPS

MSI

BULLETIN NO. DL-S 7612460, OCTOBER 1976

SN54276 . , . J PACKAGE
SN74276 .•. J OR N PACKAGE
(TOP VIEW)

features
•

Four J-K Flip-Flops in a Single Package ...
Can Reduce FF Package Count by 500..b

•

Separate Negative-Edge-Triggered Clocks with
Hysteresis ... Typically 200 mV

•

Typical Clock Input Frequency ... 50 MHz

•

Fully Buffered Outputs

VCC

4J

4CK

4;(

40

30

3;(

3CK

3J

PRESET

CLEAR

lJ

lCK

1;(

10

2Q

2;(

2CK

2J

GND

description
These quadruple TTL J-K flip-flops incorporate a
number of third-generation Ie features that can
simplify system design and r~duce flip-flop package
count by up to 50%. They feature hysteresis at each
clock input, fully buffered outputs, and direct clear
capabil itv, and arc prcscttab!c through a buffer that
also features an input hysteresis loop. The negativeedge-triggering clocks are directly compatible with
earlier Series 54/74 single and dual pulse-triggered
flip-flops. These circuits can be used to emulate
D- or T-type flip-flops by hard-wiring the inputs, or
to implement asychronous sequential functions.

schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

Vcc---.---

INPUT

The SN54276 is characterized for operation over the
full military temperature range of -55°C to 125°C;
the SN74726 is characterized for operation from oOe
to 70°C.
Clear, J, K: Req = 4 kU NOM
Clock: Req = 10.2 kU NOM

FUNCTION TABLE (EACH FLIP-FLOP)
PRESET

CLEAR

CLOCK

J

K

Q

•

Preset: Req = 11.6 kU NOM

OUTPUT

INPUTS

COMMON INPUTS

TYPICAL OF ALL OUTPUTS
-------~---vcc

L

H

X

X

X

H

H

L

X

X

X

L

L

X

X

X

L
Ht

H

H

+

L

H

Qo

H

H

t

H

H

H

H

H

+

L

L

L

H

H

t

H

L

TOGGLE

H

H

H

X

X

Qo

Q

tThis configuration is nonstable; that is, it may not
persist when preset and clear return to their inactive
(high) level.
See explanation of function tables on page 3·8.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
..... 7 V
. . . . 5.5 V
_55°C to 125°C
oOe to 70°C
-65°C to 150°C

Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Operating free-air temperature range: SN54276
SN74276
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.

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TYPES SN54276, SN74276
QUADRUPLE J-K FLIP-FLOPS
recommended operating conditions
SN74276

SN54276
MIN

NOM

4.5

5

Supply voltage, VCC

MAX

MIN

NOM

5.5

4.75

5

-800

High·level output current, 10H

35

0

Pulse width, tw

V
J.l.A

0

Clock high

13.5

13.5

Clock low

15

15

Preset or clear low

12

12

J, K inputs
Setup time, tsu

5.25
-800

16

Low·level output current, 10L
Clock frequency

Clear and preset inactive state

Input hold time, th

3.

3./.

10.

10.

10.

10./.

-55

Operating free-air temperature, T A

125

UNIT

MAX

16

mA

35

MHz

ns

ns
ns

0

°c

70

./. The arrow indicates that the falling edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH
VOL

•

MIN

TYP:j:

UNIT

MAX

V

2

High-level output voltage
Low-level output voltage

VCC - MIN,

11--12mA

VCC = MIN,

VIH -2 V,

VIL = 0.8 V,

10H = -8ooJ.l.A

VCC = MIN,

VIH =2 V,

VIL = 0.8 V,

IOL=16mA

2.4

0.8

V

-1.5

V
V

3.4
0.2

V

0.4
1

mA

II

Input current at maximum input voltage

Vee = MAX,

VI = 5.5 V

IIH

High-level input current

Vce = MAX,

VI = 2.4 V

40

J.l.A

IlL

Low·level input current

VCC - MAX,

VI - 0.4 V

-1.6

mA

-85

mA

81

mA

lOS

Short-circuit output current§

Vce = MAX

ICC

Supply current

Vec = MAX

-30

60

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
§Not more than one output should be shorted at a time.

switching characteristics, Vee

= 5 V, T A = 25° C

PARAMETER

TEST CONDITIONS

MIN

TYP

35

50

MAX UNIT

f max

Maximum clock frequency

tPLH

Propagation delay time, low-to-hi!tl-level output from preset

CL=15pF,

15

25

tPHL

Propagation delay time, high-to-low-Ievel output from clear

RL = 400.11,

18

30

ns

tPLH

Propagation delay time, Iow-to-high-Ievel output from clock

See Note 2

17

30

ns

tPHL

Propagation delay time, high-to-Iow-level output from clock

20

30

ns

MHz
ns

NOTE 2: Load circuit and voltage waveforms are shown on page 3-10.

1076

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•

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TIL

TYPES SN54278, SN74278
4-BIT CASCADABLE PRIORITY REGISTERS

MSI

BULLETIN NO. DL-S 7211729, MAY 1972-REVISED DECEMBER 1972

•

SN54278 ••• J OR W PACKAGE
SN74278 .•. J OR N PACKAGE
___ ~VIEW)

Latched Data Inputs Serve as Buffer Register
and Can also:
Synchronize Data Acquisition
"Debounce" Mechanical Switch Input

•

Cascading Input PO and Output P1
Provides "Busy"Signal Inhibiting All
Lower-Order Bits

•

Full TTL Compatibility

•

Use for:
Priority Interrupt
Synchronous Priority Line Selection

OUTPUTS

INPUTS

vcc~ NC~

~~GNO
INPUTS

description

OUTPUTS

positive logic: see function table

The SN54278 and SN74278 each consist of four data
latches. full priority output gating, and a cascading
gate. The highest-order data applied at a D latch input
is transferred to the appropriate Y output while the
strobe input is high. and when the strobe goes low all
data is latched. The cascading input PO is fully
overriding and on the highest-order package this input
must be held at a low logic level. The P1 output is
intended for connection to the PO input of the next
lower-order package and will provide a "busy"
(high-level) signal to inhibit all subsequent Iowerorder packages.
After the overriding PO input, the order of priority is
D1, D2, D3, and D4, respectively, within the package.

NC-No internal connection

FUNCT;CN TABL.E
INTERNAL

INPUTS

OUTPUTS

LATCH NODES

PO

G

01 02 03 D4 01 02 Q3 04 V1 V2 V3 V4 P1

L

H

H

X

X

X

L

X

X

X

H

L

L

L

L

H

L

H

X

X

H

L

X

X

L

H

L

L

H

L

H

L

L

H

X

H

H

L

X

L

L

H

L

H

L

H

L

L

L

H

H

H

H

L

L

L

L

H

H

L

H

L

L

L

L

H

H

H

H

L

L

L

L

L

Same function of Q
L
H
H

functional block diagram

L
L
H

X
X

X

X

X

Latched when

nodes as on 1st

G goes low

5 lines

X

L

L

L

L

H

Internal Q levels are same
function of 0 inputs as on
first 5 lines

L

L

L

L

H

X

X

H = high level, L = low level, X = irrelevant

INPUT
PO

STROBE

INPUT

INPUT

INPUT

INPUT

D4

03

02

01

G

OUTPUT

OUTPUT

P1

Y4

H

OUTPUT
V3

OUTPUT
Y2

•

OUTPUT
Y1

1272

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TYPES SN54278, SN74278
4-81T CASCADABLE PRIORITY REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Input voltage . . . . . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54278 Circuits
SN74278 Circuits
Storage temperature range
NOTES:

7V
5.5V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple·emitter transistor. For this circuit, this rating applies between the strobe
input and any of the four data inputs.

recommended operating conditions
SN54278

SN74278

MIN NOM MAX MIN NOM MAX
Supply voltage, Vee

4.5

5.5

5

High·level output current, 10H
Low·level output current, 10L
Data setup time, tsu

4.75

5

-800
16

(see Figure 1)

Operating free·air temperature, T A

V

-800

~A

16

mA

20

20

ns

5

5

ns

20

20

Data hold time, th (see Figure 1)
Strobe pulse width, tw (see Figure 1)

5.25

UNIT

-55

125

ns

0

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High·level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

•

TEST CONDITIONSt

H igh·level output voltage
Low-level output voltage

II

Input current at maximum input voltage

IlL

High·level input current

Low-level input current

I

Any D input

!

G mout

I

Any D input

I

I
I

lOS

Short·circuit output current§

ICC

Supply current

TYP MAX UNIT

2

VOL

IIH

MIN

Vee= MAX,

II = -12 mA

Vee= MIN,

VIH = 2 V,

VIL = 0.8 V,

10H = -800~A

Vee= MIN,

VIH = 2V,

VIL = 0.8 V,

10L = 16 mA

Vee = MAX,

VI = 5.5 V

I

2.4

V
0.8

V

-1.5

V

3.4
0.2

V
0.4

V

1 mA
80

PO input

200 ~A

VI = 2.4 V

Vee= MAX,

,

320

i

-3.2

PO input

Vee= MAX,

G input
Vee = MAX

-8 mA

VI=O.4V

I SN54278
rSN74278

Vee= MAX,

See Note 3

-12.8
-18

-55

-18

-57

55

mA

80 mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
+AII typical values are at Vee = S V, T A = 2Soe.
§ Not more than one output should be shorted at a time.
NOTE 3: lee is measured with the PO input grounded, all other inputs at 4.S V, and outputs open.

1076

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•

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TYPES SN54278. SN74278
4-BIT CASCADABLE PRIORITY REGISTERS
switching characteristics, Vee
PARAMETER~

=5 V, TA =25°e

FROM

TO

(INPUT)

(OUTPUT)

Data

Y

tPLH
tpHL
tpLH

Data

Y

Data

P1

tPHL
tpLH

30
39

Aand D

38

(with strobe highl

31

A and E
Band C

t ... LH

Strobe

P1

See Figure 1

38

tPLH

23

== propagation delay
== propagation delay

ns

31

Band E

P1

ns

30

42

PO

ns

39

RL=400n,

or Band D

ns

46

CL=15pF,

tpHL

.'PHL
tpHL

AandC

tpLH

AnyY

TYP MAX UNIT

(with strobe high)

(with strobe highl

Strobe

MIN

CONDITIONS

tpHL
tpHL

~tpLH

TEST

WAVEFORMS

F and G

ns
ns

30

time, low-to-high-Ievel output
time, high-to-Iow-Ievel output

schematics of inputs and outputs

PARAMETER MEASUREMENT INFORMATION
Vcc

EQUIVALENT OF EACH INPUT
V CC---tl---1 ' CL =15 P F

C L includes probe and jig capacitance_

INPUT

An diodes are 1 N3064.

LOAD CIRCUIT

•

~:;~I~~~~ ~I ~.5 V

:

Any D: Req = 2_5 kn NOM
PO: Req

G: Req

= 1 kn NOM
= 0_6 kn NOM

STROBE INPUT G

(WAVEFORM Bl

i

t
-

I

I

I

r---tw~

~~~~~iERTING
(WAVEFORM C)

rtprL_H

I

~lw---tlo4

_-:-_+-'.----..~. ~~l_ _

_ _ _

_ - - ; - _ - : - '_ _ I

VOL

:tpLH~

TYPICAL OF ALL OUTPUTS

VOH

~tl»HL
INVERTING
OUTPUT
(WAVEFORM DJ

--"--VCC

I

1
OUTPUTPl
(WAVEFORM E)

I

,----

I l.5V

~q>HL~II''---""~-q>-L-"H;--C--./..'-1-- - - !.-tpLH...-.j

[

I

l'sv

I4---tPLH~

::'~TE~~RMFI~SV

VOH
VOL

~tpHL"""

~::~

~tPHL~

~~~--------

~tPlH-eoj

OUTPUT

i

- - -

OUTPUTP'

r+-tpHL.....,

!,r.,------"""\l.1.S V

(WAVEFORM GI _ _ _ _ _ /

J

1.5

v

-

~

VOH
VOL

VOLTAGE WAVEFORMS
NOTE: Input pulses are supplied by a generator having the following
characteristics: tr';;; 7 ns, tf';;; 7 ns, PRR .;;; 1 MHz, Zout "" 50

n.

FIGURE l-SWITCHING TIMES

1076

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7-405

TYPES SN54LS280, SN54S280, SN74LS280, SN74S280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

TTL
MSI

BULLETIN NO. DL-S 7611829, DECEMBER 1972-REVISED OCTOBER 1976

SN54LS280, SN54S280 ..• J OR W PACKAGE
SN74LS280, SN74S280 •.. J OR N PACKAGE
(TOP VIEW)

•

Generates Either Odd or Even Parity
for Nine Data Lines

•

Cascadable for n-Bits

•

Can Be Used to Upgrade Existing
Systems using MSI Parity Circuits

•

Typical Data-to-Output Delay of Only 14 ns
for 'S280 and 33 ns for 'LS280

•

Typical Power Dissipation:
'LS280 ... 80 mW
'S280 ... 335 mW
FUNCTION TABLE

~

OUTPUTS

NUMBER OF INPUTS A
THRU I THAT ARE HIGH

k EVEN

0,2,4,6,8

H

L

1,3,5,7,9

L

H

H

= high

level, L

NC

I
~
~
;NPUT~

GNO

INPUTS

kODD

OUTPUTS

logic: see function table

= low level

NC-No internal connection

description
These universal, monolithic, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance
circuitry and feature odd/even outputs to facilitate operation of either odd or even parity application. The word-length
capability is easily expanded by cascading as shown under typical application data.
Series 54LS/74LS and Series 54S/74S parity generators/checkers offer the designer a trade-off between reduced power
consumption and high performance. These devices can be used to upgrade the performance of most systems utilizing
the '180 parity generator/checker. Although the 'LS280 and 'S280 are implemented without expander inputs, the
corresponding function is provided by the availability of an input at pin 4 and the absence of any internal connection
at pin 3. This permits the 'LS280 and 'S280 to be substituted for the '180 in existing designs to produce an identical
function even if 'LS280's and 'S280's are mixed with existing '180's.

•

These devices are fuliy compatible with most other TTL and DTL circuits. A!! 'LS280 and 'S280 inputs are buffered to
lower the drive requirements to one Series 54LS/74LS or Series 54S/74S standard load, respectively.

schematics of inputs and outputs

o

'LS280

EQUIVALENT OF INPUTS

VCC
INPUT

TYPICAL OF OUTPUTS

---~-Vcc

o

EQUIVALENT OF INPUTS

vcc

'S280
TYPICAL OF OUTPUTS

~~~VCC

2.8 kn NOM

20 kn NOM
__

INPUT
OUTPUT

--

u~OUTPUT

1lIJ
1076

7-406

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INSTRUMENTS
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TYPES SN54LS280, SN74LS280
9-BIT ODD/EVENi PARITY GENERATORS/CHECKERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (see Note 1)
Input voltage
Operating free-air temperature range: SN54 LS280
SN74LS280
Storage temperature range

7V
7V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54lS280
MIN
Supply voltage, Vee

4.5

NOM

MIN

b.5

4.15

b

High-level output current, 10H

SN74lS280

MAX

NOM
5

MAX
5.25

-0.4

low-level output current, 10L

mA

8

mA

70

°c

4

-55

125

0

V

.4

----

Operating free-air temperature, T A

UNIT

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54lS280
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

TEST CONDITIONSt

MIN

TYP+

SN74lS280

MAX

MIN

2
Vee = MIN,

II =-18mA

Vee - MIN,

VIH = 2 V,

VIL=MAX,

10H = -0.4 mA

Vee - MIN,

VIH = 2 V,

VOL

Low-level output voltage

II

Input current at maximum input voltage

Vee = MAX,

VI =7V

IIH

High-level input current

Vee = MAX,

VI = 2.7 V
VI = 0.4 V

2.5

IlL

Low-level input current

Vee = MAX,

Short-circuit output current§

Vee - MAX

lee

Supply current

Vee = MAX, See Note 2

UNIT

MAX

2
0.8

V

-1.5

-1.5

V

3.4
0.25

V

0.7

2.7
0.4

VIL = MAX

lOS

TYP+

3.4

V

0.25

0.4

0.35

0.5

V

0.1

0.1

mA

20
-0.4

20

/lA

-20

-100

16

27

-0.4

mA

-100

mA

16

27

mA

TYP

MAX

33

50

29

45

23

35

31

50

-20

II

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with all inputs grounded and all outputs open.

switching characteristics, Vee
PARAMETER~

tPLH

= 5 V, TA = 25° C

FROM

TO

(INPUT)

(OUTPUT)

Data

TEST CONDITIONS

LEven

tpHL
tPLH

MIN

eL=15pF,RL=2kn,
See Note 3
Data

L Odd

tPHL
~tPLH

==

NOTE 3:

UNIT
ns
ns

propagation delay time, low-to-high-Ievel output; tpHL == propagation delay time, high-to-Iow-Ievel output
Load circuit and VOltage waveforms are shown on page 3-11.

1076

TEXAS INCORPORATED
INSTRUMENTS
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•

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7-407

TYPES SN54S280, SN14S280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (see Note 1)
Input voltage
Operating free-air temperature range: SN54S280
SN74S280
Storage temperature range

7V

5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54S280
MIN
Supply voltage, Vee

NOM

4.5

SN74S280

MAX

MIN

5.5

4.75

5

High-level output current, 10H

NOM
5

-1

Low-level output current, 10L

20

Operating free-air temperature, T A

-55

125

0

MAX

UNIT

5.25

V

-1

mA

20

mA

70

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

I

TEST CONDITIONSt

MIN

TYPt

MAX UNIT

2

Low-level output voltage

Vee= MIN,

II = -18mA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10H = -1 mA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10L = 20mA

V

TSN54S'

2.5

3.4

I SN74S'

2.7

3.4

0.8

V

-1.2

V
V

0.5

V

II

Input current at maximum input voltage

Vee= MAX,

VI = 5.5V

IIH

High-level input current

Vee = MAX,

VI=2.7V

50

JlA

IlL

Low-level input current

Vee = MAX,

VI=0.5V

-2

mA

lOS

Short-circuit output current§

1

Vee= MAX

-40

Vee = MAX, See Note 2
ICC

Supply current

Vee = MAX, TA=125°C,
See Note 2

-100

SN54S280

67

99

SN74S280

67

105
94

SN54S280N

mA

mA
mA
mA

t F or conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
~AII typical values are at Vee = 5 V. T A = 25°C.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
NOTE 2:

ICC is measured with all inputs grounded and all outputs open.

switching characteristics, Vee
PARAMETER~

tPLH

= 5 V, TA = 25° C

FROM

TO

(INPUT)

(OUTPUT)

Data

~

TEST CONDITIONS

Even

tpHL

eL=15pF,

tpLH

See Note 4

Data

~

Odd

MIN

RL = 180n,

tpHL

TYP

MAX

14

21

11.5

18

14

21

11.5

18

UNIT
ns
ns

~ tpLH "" propagation delay time, low-to-high-Ievel output; tpH L '" propagation delay time, high-to-Iow-Ievel output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-10.

1076

7-408

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS280. SN54S280. SN74LS280. SN74S280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
functional block diagram

TYPICAL APPLICATION DATA
81-LINE PARITY/GENERATOR CHECKER

2S-LINE PARITY/GENERATOR CHECKER
Three

'LS280's

or 'S280's can

be

Longer word lengths can be imple-

used to implement a 25-line parity

mented

generator/checker. This arrangement

'S280's. As shown here, parity can be

will provide parity in typically 75 or

A
B

25 nanoseconds respectively.

bits

EVEN

E
F
G

o

'LS280/
'S280

A
B
~

o
EVEN
E
F
l:
GOOD
H 'LS280/
'S280

H = EVEN
l=ODO

C

or

I

in typically 75 or 25 nano-

seconds respectively.

'LS280/
'S280
A
:!: I-----"'--IB
EVEN

H =000
l = EVEN

H

'LS280/
'8280

:!:
.....----10
EVEN
E
F
l:
GOOD
H 'LS280/
'S280

H = EVEN
l=OOD
H = EVEN
l=OOO

A
~

EVEN

F

C

As an alternative, the outputs of two
or

G

:!:
EVEN

o

A

C
0

'LS280's

E
F

G
H

A
B
C

cascading

generated for word lengths up to 81

A

~

C

by

o

three parity generators/checkers

E
F
G
H

can be decoded with a 2-input ('S86
'LS280/
'S280

'LS86)

or

3-input

('S135)

exclusive-OR gate for 18- or 27-line

l:
EVEN

~
'LS280/
'S280

TO OTHER
'LS280/
'S280

parity applications.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

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7-409

TYPES SN54S281, SN74S281
4-BIT PARALLEL BINARY ACCUMULATORS

TTL
LSI

BULLETIN NO. DL-S 7612065, FEBRUARY 1974 - REVISED OCTOBER 1976

•

Full 4-Bit Binary Accumulator in
a Single Package

•

15 Arithmetic/Logic-Type Operations:
Add
Subtract (B-A or A-B)
Complement
Increment
Transfer
Plus 10 Other Functions

•

Full Shifting Capabilities:
Logic Shift (Left or Right)
Arithmetic Shift (Left or Right)
for Sign Bit Protection
Hold
Parallel Load

•

Expandable to Handle n-Bit Words
with Full Carry Look-Ahead

•

SN54S281 ... J OR W PACKAGE
SN74S281 ... J OR N PACKAGE
(TOP VIEW)

logic: see description and function tables

Logic Mode Operation Provides Seven
Boolean Functions of the Two Variables

description
These Schottky-clamped four-bit accumulators integrate high-performance versions of an arithmetic logic unitlfunction
generator and a shift/storage matrix on a single monolithic circuit bar. The arithmetic logic unit (ALU) portion, similar
to the SN54S181/SN74S181 circuit, incorporates the capability to perform 16 arithmetic/logic·type operations as
detailed in Table 1. The accumulator includes an exchange of subtract operands by which either A-8 or 8-A can be
accomplished directly. The ALU is controlled by three function-select inputs (ASO, AS1, AS2) and a mode-control
input (M). When the mode-control input is hi9h, the ALU is placed in a logic mode that performs any of seven logic
functions on two binary variables as detailed in Table 2. Full carry look-ahead is provided for fast, simultaneous carry
generation for the full four binary bits. The carry input (C n ) and propagate and generate outputs (p, G) are
implemented for direct use with the SN54S182/SN74S182 look-ahead carry generators. This permits systems to be
Implemented with the added advantage of full look-ahead across any word length to minimize the accumulator delay
times. Once data is loaded ir!to the accumulator, the typical add time with full look-ahead is 29 nanoseconds for 16-bit
words.

I

The shift/storage matrix is analogous in its capabilities to the SN54S194/SN74S194 universal bidirectional shift register
with the added advantages of multiplexed input/output (I/O) cascading lines that comprehend arithmetic shift
functions having a sign bit, such as 2's complements. The matrix can be used to perform either logic or arithmetic shifts
in either direction (left or right), parallel load, or hold. Control of the register is accomplished with three inputs:
register control (RC) and register selection (RSO, RS1). The cascading input/output lines incorporate three-state
outputs multiplexed with an input. The least-significant cascading bit is combined with the AO, FO circuitry to provide
the shift-right input and the shift-left output (RI/LO)' and the most significant bit is coupled with the A3, F3 circuitry
to provide the shift-left input and the shift-right output (L1/RO).
Series 54S circuits are characterized for operation over the full mil itary temperature range of _55° C to 125° C; Series
74S circuits are characterized for operation from O°C to 70°C.

1076

7-410

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOx 5012

•

DALLAS. TEXAS 75222

TYPES SN54S281, SN74S281
4-BIT PARALLEL BINARY ACCUMULATORS
FUNCTION TABLES
TABLE 1-ARITHMETIC FUNCTIONS

TABLE 2-LOGIC FUNCTIONS

Mode Control (M) = Low

Mode Control (M) = High
Carry Input (C n ) = X (Irrelevant!

ACTIVE-HIGH DATA

ALU
SELECTION

Cn=H

AS2 AS1 ASO

(with carry)

= L.

= F2 =

Cn = L
(no carry)

ALU

ACTIVE-HIGH

SELECTION

L

L

L

FO

L

L

H

F = B MINUS A

F = B MINUS A MINUS 1

L

L

L

Fn = L

L

H

L

F =A MINUS B

F = A MINUS B MINUS 1

L

X

H

Fn=An

L

H

H

F = A PLUS B PLUS 1

F = A PLUS B

L

H

L

Fn = An

H

L

L

F = B PLUS 1

Fn = Bn

H

L

L

Fn = AnBn

F1

AS2 AS1 ASO

DATA FUNCTION

Fn = H

F3 = H

-

0
0

Bn
Bn

H

L

H

F = B PLUS 1

-

Fn = Bn

H

L

H

Fn=An+Bn

H

H

L

F = A PLUS 1

Fn = An

H

H

L

Fn = AnBn

H

H

H

F=

F n =A

H

H

H

F =A

-

A PLUS 1

I

+B

TABLE 3 - SHIFT-MODE FUNCTIONS

Cn

= M = ASO = AS1

INPUTS BEFORE

REGISTER

FUNCTION

REGISTER

INPUT!

CONTROL

OUTPUT

INPUT

RI/LO

SELECTION
RSO RS1

~

Sn)

INPUT!
OUTPUT

INPUTS
F1

F2

F3

LI/RO

SHIFT-MATRIX

INPUT/

CLOCK

INPUT/

OUTPUTS

OUTPUT

INPUT

OUTPUT

(ALU B INPUTS)

RI/LO

LI/RO

L

L

X

Z

to

f1

f2

f3

Z

t

Z

to

LSL

L

H

L

QA

QA

QB

QC QD

Ii

t

QBn

QBn

QCn

QDn

Ii

L

H

I

H

QA

QA QB

QC QD

Ii

t

QS n

QCn

Ii

QDO

Ii

RSL

H

L

ri

QA

QB

QC QD

QD

t

ri

QAn

QBn

QCn

QCn

RSA

H

L

Ii

L

QBn
ri

H

ri

QA QB

QC QD

QC

t

ri

ri

QAn

QBn

QDO

QBn

H

H

X

X

QA

QB

QC

QD

X

t

Z

QAO

QBO

QCO QDO

Z

X

X

X

X

QA

QB

QC

QD

X

L

QAO QBO

QCO QDO

LltRO

I

°A

t

LOAD

HOLD

t

H (F n

OUTPUTS AFTER

SHIFT-MATRIX
FO

='

°B
f1

LSA

H
L
X
Z

= L, and AS2

t

I

RilLa

°c
f2

°D
f3

Z
Ii

= high level (steady state)
= low level (steady state)
= irrelevant (any input, including transitions)
= high impedance (output off)

•

= transition from low to high level

fO, f1, f2, f3, ri, Ii = the level of steady-state conditions at FO, F 1. F2. F3. R liLa. or U/RO respectively
QAO, QBO. QCO, QDO = the level of QA, QB, QC. or QD, respectively, before the indicated steady-state input conditions were established
QAn. QBn' QCn' QDn = the level of QA. QB, QC, or QD. respectively, before the most recent transition of the clock
See explanation of function tables on page 3-8.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1)
.......... .
Input voltage . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54S281 (see Note 2)
SN74S281
Storage temperature range

NOTES:

7V

5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
2. An SN54S281 in the W package operating at free-air temperatures above 110°C requires a heat sink that provides thermal
o

resistance from case to free-air, ROCA. of nOt more than 20 C/W.

1076

TEXAS INCORPORATED
INSTRUMENTS
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•

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7-411

TYPES SN54S281, SN74S281
4-BIT PARALLEL BINARY ACCUMULATORS
recommended operating conditions
SN54S281

I

Supply voltage, Vee

NOM

MAX

MIN

NOM

MAX

4.5

5

5.S

4.75

5

5.25

Any output except Ll/RO and RI/LO

High-level output current, 10H
Low-level output current, 10L

SN74S281

MIN

-1

-1

Ll/RO and RI/LO

-2

-2

Any output except Ll/RO and RI/LO

20

20

Ll/RO and RI/LO

10

UNIT
V
mA
mA

10

elock frequency, fclock (for shifting)

0

Width of clock pulse, tw(clock)

8

8

Data setup time with respect to clock, tsu

ot

ot

ns

18t

18t

ns
°e

Data hold time with respect to clock, th
Operating free-air temperature, T A (see Note 2)

50

-55

125

0

MHz

50

ns

0

70

tThe arrow indicates that the rising edge of the clock pulse is used for reference.
NOTE 2: An SN54S281 in the W package operating at free-air temperatures above 110°C requires a heat sink that provides thermal resistance
from case to free-air, ReCA, of not more than 20°C/W.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage
High-level

VOH

output voltage

TEST CONDITIONSt

Any input except
Ll/RO and RI/LO
Any output except

•

IIH

input current

IlL

input current

lee

-1.2

-1.2

V

Vee = MIN,

VIH=2V,

2.5

3.4

2.7

3.4

VIL = 0.8 V,

10H = MAX

2.4

3.4

2.4

3.4

Vee = MIN,

VIH = 2V,

VIL = 0.8 V,

10L = MAX

See Note 3

I

ASO,AS1

Vee = MAX,

VI =0.5V

See Note 3

All others
lOS

V

II = -18mA

Vee = MAX, VI = 2.7 V,

LI/RO, RI/LO

M, elock

V

0.8

Vee = MIN,

Vee = MAX, VI = S.5 V

RSO, RS1
M, elock

RI/LO

!

2

RSO, RS1, Ll/RO
Low-level

SN74S281
UNIT
TYP:j: MAX

V

Ll/RO, RI/LO

AS2
All others

MIN

0.8

L1/RO and RI/LO

Input current at maximum input voltage

High-level

SNS4S281
TYP:j: MAX

2

VOL Low-level output voltage
II

MIN

0.5

0.5

1

1

SO

50

150 i

150

200

200

300

300

250

250

-2

-2

-3

-3

-4

-4

-6

-6

-8

Short-circuit output current§

Vee = MAX

Supply current

Vee = MAX'l W package
TA = 12Soe only
Vee = MAX

-40

I All packages

-110

230

IlA

mA

-8
-40

-110

190
144

V
mA

mA
mA

144

230

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 3. When testing input current at the R lILa or Ll/RO terminals, the output under test must be in the high-impedance (off) state.

1076

7-412

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

CALLAS, TEXAS 75222

TYPES SN54S281, SN74S281
4-BI1 PARALLEL BINARY ACCUMULATORS
switching characteristics, Vee
PARAMETER~
tPLH

=5 V, TA = 25°e
FROM

TO

(INPUT)

(OUTPUT)

Cn

tpHL
tpLH

Any A

tPLH

TYP

MAX

10

20

Cn+4

Cn

tpHL

MIN

C n+4

tpHL
tpLH

TEST CONDITIONS

Any F

-

Any A

G

20
30

18

30

10

20

10

20

14

24

tpHL

14

24

tPLH

12

20

12

20

20

35

P

Any A

tpHL
tpLH

Ai

tD
I
,H~

tpLH
tpHL
tPLH
tpHL
tpLH

Fi

AO

RI/LO

A3

LI/RO

FO

RI/LO

F3

LI/RO

Any AS

tpHL
tpLH

Any AS

20

35

CL=15pF,

30

45

I/O outputs: RL = 560 fl,

30

45

Other outputs: HL = 280

n,

See Figure 1

tpLH

I

Clock

== Propagation delay time, low-to-high-Ievel
== Propagation delay time, high-to-Iow-Ievel

7

11

7

11

7

11
11
45

C n+4

28

45

ns
ns
ns
ns
ns
ns

I
I

I
I

ns

33
33

30

45 I

30

45

RI/LOor

35

55

LI/RO

35

55

I

ns

ns

20

I

ns

ns

20
Any F

tpHL

45

28

tpHL
tpLH

45

30

Any F or

PorG

Ciock

30

7

tpHL

~ tpLH
tpHL

10
18

UNIT

ns

I

ns
ns

output
output

I

I

I

II

PARAMETER MEASUREMENT INFORMATION

~~.;V--

INPUT

Jl"~v

-3V

~OV

l-tPLH.....

I-tPHL--t

IN.PHAS~I
I
: -:--VOH
OUTPUT

~

1.5 V

I
I

1.5 V
VOL

I

I

r-tPHL -I

t-tPLH-oi

:

~

OUT·OF·PHASE
OUTPUT

LOAD CIRCUIT

iVOH
1.5 V

1.5 V

- - -VOL

VOLTAGE WAVEFORMS

NOTES:

A. Input pulse is supplied by a generator having the following characteristics: t r " 2.5 ns, tf" 2.5 ns, PRR " 1 MHz, Zout "" 50 fl.
B. C L inlcudes probe and jig capacitance.
C. All diodes are 1 N916 or 1 N3064.
FIGURE 1

1076

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DALLAS. TEXAS 75222

7-413

TYPES SN54S281, SN74S281
4-BIT PARALLEL BINARY ACCUMULATORS
TYPICAL APPLICATION OAT A
RIGHT
DATA IN
CARRY
INPUT

RI/LO

LI/RO

RI/LO

LI/RO

RI/LO

Cn

Cn+4

Cn

'S281

RI/LO

LI/RO

Cn +4

Cn

Cn+4

'S281

'S281

'S281

Ll/RO

LEFT
DATA IN
CARRY
OUTPUT

ENTER AND STORE TIME:
38 ns typical
EACH SUCCESSIVE ADDITION TO STORED DATA: 44 ns typical
FIGURE A-16-BIT BINARY ACCUMULATOR USING FOUR SN54S281/SN74S281 CIRCUITS
IN RIPPLE-CARRY MODE

RIGHT
DATA IN
CARRY
INPUT

Ll/RO

RI/LO

RI/LO
Cn

Ll/RO

RI/LO

'S281

Cn

G P

RI/LO

LI/RO

Cn

'S281

Ll/RO
'S281 Cn+4

LEFT
DATA IN
CARRY
OUT

G P

C n+ x

'S182
ENTER AND STORE TIME:
37 ns typical
EACH SUCCESSIVE ADDITION TO STORED DATA: 29 ns typical
FIGURE B-16-BIT BINARY ACCUMULATOR USING FOUR SN54S281/SN74S281 CIRCUITS
AND ONE SN54S182/SN74S182 IN FULL LOOK-AHEAD CARRY MODE

I

RIGHT
DATA IN
CARRY
INPUT

RI/LO

4

LI/RO

G

P

GO

PO

RI/LO

Cn+ x

Cn

4

RI/LO

LI/RO

G

P

G1

P1

Cn+y

4

Ll/RO

G

P

G2

P2

·RI/LO

Cn+ z

4

Ll/RO

G

P

G3

P3

LEFT
DATA IN
CARRY
OUT

'S182

ENTER AND STORE TIME:
42 ns typical
EACH SUCCESSIVE ADDITION TO STORED DATA: 34 ns typical
FIGURE C-64-BIT BINARY ACCUMULATOR USING 16 SN54S281/SN74S281 CIRCUITS AND
FIVE SN54S182/SN74S182 CIRCUITS FOR FULL CARRY LOOK-AHEAD

A inputs and F outputs of 'S281 are not shown.
1076

7-414

TYPES SN54283, SN54LS283, SN54S283,
SN74283, SN74LS283, SN74S283
4-BIT BINARY FULL ADDERS WITH FAST CARRY

TTL
MSI

BULLETIN NO. DL-S 7611832, OCTOBER 1976

•

Full-Carry Look-Ahead Across the Four
Bits

•

Systems Achieve Partial Look-Ahead
Performance with the Economy of Ripple
Carry

•

Supply Voltage and Ground on Corner
Pins to Simplify P-C Board Layout

SN54283, SN54LS283 ... J OR W PACKAGE
SN54S283 ..• J PACKAGE
SN74283, SN74LS283, SN74S283 .•• J OR N PACKAGE
(TOP VIEW)

vcc

B3

A3

~3

A4

C4

TYPICAL ADD TIMES
~2

TWO

TWO

TYPICAL POWER

8-BIT

16-BIT

DISSIPATION

TYPE

WORDS

WORDS

PER ADDER
310 mW

'283

23ns

43ns

'LS283

25ns

45ns

95 mW

'S283

15ns

30ns

510 mW

C4

positive logic: S€'e' function table

description
The '283 and 'LS283 adders are electrically and
functionally identical to the '83A and 'LS283,
respectively; only the arrangement of the terminals
has been changed. The 'S283 high performance
versions are also functionally identical.

FUNCTION TABLE

These improved full adders perform the addition of
two 4-bit binary words. The sum (L) outputs are
provided for each bit and the resultant carry (e4) is
obtained from the fourth bit. These adders feature
full internal look-ahead across all four bits generating
the carry term in ten nanoseconds, typically, for the
'283 and 'LS283, and 7.5 nanoseconds for the 'S283.
This capability provides the system designer with
partial look-ahead performance at the economy and
reduced
package
count of
ripple-carry
implementation.

H
H

H
H

H

H

H

H
H

L

I

H
H

H

H

H

H

H

H
H

H

H

H

H

L

L

L

H
H

The adder logic, including the carry, is implemented
in its true form. End around carry can be accomplished without the need for logic or level inversion.

H

H

H

H

H

H

H

H

H

H

H

H

H

H

Series 54, Series 54LS, and Series 54S circuits are
characterized for operation over the full temperature
range of -55°C to 125°C. Series 74, Series 74LS, and
Series 74S circuits are characterized for oOe to 70°C
operation.

H

H
H

H

H

= high

H
H

H

H

H

H
H

level, L

L

L

H

H

H

H

= low

H
H

H

H
H
H

H

H

H

H

H

H

H

H

H

level

NOTE: Input conditions at A 1, B1, A2, B2, and CO are used to
determine outputs ~1 and ~2 and the value of the internal
carry C2. The values at C2, A3, B3, A4, and B4 are then
used to determine outputs 2:3, 2:4, and C4.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7415

TYPES SN54283, SN54LS283, SN54S283,
SN74283, SN74LS283, SN74S283
4-BIT BINARY FULL ADDERS WITH FAST CARRY
functional block diagram and schematics of inputs and outputs
'283
TYPICAL OF ALL
OUTPUTS

EQUIVALENT OF
EACH INPUT

vce3--

----..--Vee

Req

INPUT

--

OUTPUT

CO input: Req = 4 kn NOM
Any A or B: Req = 3.5 kn NOM

e4 output: R = 100 n NOM
Any E: R = 120 n NOM

'LS283
EQUIVALENT OF
EACH INPUT

TYPICAL OF ALL OUTPUTS

Vee--..._--

-----+--Vee

Req
INPUT-+....

~

__
OUTPUT

CO input: Req = 17 kn NOM
Any A or B: Req = 8.5 kn NOM

--a

'8283
EQUIVALENT OF
EACH INPUT

I

Vee

INPUT

TYPICAL OF ALL OUTPUTS

_
w
T

~2.8knN-OM

on NOM

Vee

--

~OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage: '283, 'S283
'LS283 . . . .
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54283, SN54LS283, SN54S283 .
SN74283, SN74LS283, SN74S283 .
Storage temperature range
NOTES:

7V
5.5V
7V
5.5V
. -55°C to 125°C
oOe to 70°C
. -65°eto 150°C

1. Voltage values, except interemitter voltage,. are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the '283 and 'S283 only between
the following pairs: A 1 and B1, A2 and 82, A3 and 83, A4 and B4.

1076

7-416

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54283, SN74283
4-BIT BINARY FULL ADDERS WITH FAST CARRY
recommended operating conditions
SN54283
NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

Supply Voltage, VCC
High·level output current, 10H

SN74283

MIN
Any output except C4

-800

-800

Output C4

--400

-400

16

16

8

8

Any output except C4
Low-level output current, 10L

Output C4
-55

Operating free-air temperature, T A

125

0

70

UNIT
V
/J. A

rnA

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

ViH

High-Ieve! input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

, VOH

VOL

MIN

TYP:j:

SN74283
MAX

VCC = MIN,

II = -12 mA

VIL = 0.8 V,

IOH

VCC= MIN,

VIH=2V,

VIL = 0.8 V,

10L = MAX

-.. -'-'ptcc"= MIN~~

High-level output voltage

Low-level output voltage

input voltage

V

-1.5

-1.5

V

H-------2-V-,--l-'-2-.-4--3-.6-----+-'-2.-4--3-.6----+--V----1

= MAX
0.2

1

V

1

40

/J.A

-1.6

mA

VCC = MAX, VI = 2.4 V
VCC= MAX,

VI = 0.4 V

-1.6

VCC = MAX

I

-20

-55

-18

-55

-20

-70

-18

-70

All B low, other
VCC = MAX,

Supply current

0.4

VCC = MAX, VI = 5.5 V

Low-level input current

I ICC

0.2

0.4

High-level input current

I Any output except C4
I Output C4

UNIT
V

IIH

output current §

MAX

0.8

IlL

Short-circuit

TYp:j:

0.8

40

lOS

MIN

2

Input current at maximum
II

SN54283

TEST CONDITIONst

PARAMETER

inputs at 4.5 V

Outputs open All inputs at

56

mA

56
mA

99

66

4.5 V

mA

66

I

110

t For conditions shown as MIN or MAX, use the :::ppropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5. V, T A = 25°C.
§Only one output should be shorted at a time.

switching characteristics, Vee
PARAMETER~

tPLH

=

5 V, T A = 25°e
TO (OUTPUT)

FROM (INPUT)

Any:E

CO

TEST CONDITIONS

tpHL

CL=15pF,

tpLH

See Note 3
AiorBi

:Ei

CO

C4

RL = 400

n,

tpHL

CL=15pF,

tpLH

See Note 3
C4

Ai orBi

tpHL
~ tp LH
tpH L

== Propagation
== Propagation

NOTE 3:

MIN

TYP

MAX

14

21

12

21

16

24

16

24

UNIT
ns

ns

tpHL
tpLH

•

RL = 780

n,

9

14

11

16

9

14

11

16

ns

ns

delay time, low·to·high·level output
delay time, high·to·low·level output

Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-417

TYPES SN54LS283, SN74LS283
4-BIT BINARY FULL ADDERS WITH FAST CARRY
recommended operating conditions
SN54LS283
Supply voltage, Vee

MIN

NOM

4.5

5

High-level output current, 10H

SN74LS283

MAX

MIN

NOM

5.5

4.75

5

-400

Low-level output current, 10l

MAX
5.25

V

-400

IJ.A

S

mA
De

4

Operating free-air temperature, T A

-55

125

UNIT

0

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

Vil

low-level input voltage

VIK

Input clamp voltage

IIH
III
lOS

II = -1SmA

Vee= MIN,

VIH = 2V,

Vil = Vil max,

VIH = 2V,

10l = 4mA

Vee= MIN,
Vil = Vil max

2.5

SN74LS283

MAX

MIN

Vee= MAX,
Any A or B

input current

eo

low-level

Any A or B

input current

eo

Short-circuit output current§

Vee= MAX,

VI = 2.7 V

Vee= MAX,

VI = 0.4 V

UNIT
V

O.S

V

-1.5

-1.5

V

I

3.4
0.25

2.7

0.4

3.4

V

0.25

0.4

0.35

0.5

0.2

0.2

0.1

0.1

40

40

20

20

VI = 7V

V

mA

Vee= MAX
grounded
All B low, other

Outputs open

inputs at 4.5 V
All inputs at

I

4.5V

-O.S

-O.S

-0.4

-0.4

-100

-20

Vee= MAX,

Supply current

MAX

2

eo

High-level

TYP+

0.7

10l - SmA

All inputs

lee

TYP+

Any A or B

at maximum
input voltage

Vee= MIN,
10H =-400IJ.A

Val low-level output voltage

II

MIN
2

VOH High-level output voltage

I nput current

SN54lS283

TEST CONDITIONSt

-100

-20

22

39

22

39

19

34

19

34

19

34

19

34

IJ.A
mA
mA

mA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
!AII typical values are at V CC

=5

V, T A

= 25

D

C.

§Oniy One output shouid be shorted at a tin,.:! and duration of the short-circuit should not exceed ona second.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER.
tPlH
tpHl
tplH
tpHl

FROM (INPUT)
eo

TO (OUTPUT)
Any

Aior Bj

~j

eo

C4

TEST CONDITIONS

~

el = 15pF,

TYP

MAX UNIT

16

24

15

24

15

24

15

24

11

17

tPHl

11

22

tPlH

11

17

12

17

tPlH

Ai or Bj

See Note 4

Rl=2kn,

MIN

C4

tPHl

ns

ns
ns
ns

.tPLH == Propagation delay time, low·to·high·level output
tPHL == Propagation delay time, high-to-Iow·level output
NOTE 4: Load circuit and voltage waveforms are shown on page 3-11.

1076

7-418

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

OALLAS. TEXAS 75222

TYPES SN54S283, SN74S283
4-BIT BINARY FULL ADDERS WITH FAST CARRY
recommended operating conditions
SN54S283

Low-level output current, IOL

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

-1

-1

mA

-500

-500

20

20

Any output except C4
Output e4
Any output except e4
Output C4

10
-55

Operating free-air temperature, T A

UNIT

NOM

Supply voltage, Vee
High-level output current, IOH

SN74S283

MIN

0

125

0

70

/LA
mA
°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONSt

VIH

High-level input voltage

V;L

L~~!-~e'!e!

VIK

I nput clamp voltage

VOH
VOL

MIN

TYpf

MAX

!!"!p!.!t vc~t~e

High-level output voltage

Vee = MIN,

II =-18mA

ISN54S283

VCC= MIN,

VIH = 2 V,

2.5

3.4

ISN74S283

VIL = 0.8 V,

IOH = MAX

2.7

3.4

VCC = MIN,

VIH = 2V,

VIL = 0.8 V,

IOL = MAX

Low-level output voltage
Input current at maximum

UNIT
V

2
no

\I

-1.2

V
V

0.5

V

Vee = MAX,

VI = 5.5 V

1

IIH

High-level input current

Vce = MAX,

VI = 2.7 V

50

/LA

IlL

Low-level input current

VCC - MAX,

VI- 0.5 V

-2

mA

II

I !OS

input voltage

Short-circuit
output current§

I
I

Any output except C4

Vee

Output C4

= ~.,1AX

-40

-100

-20

-100

mA

rnA

I

I

All B low, other
lec

Supply current

VCC = MAX,

inputs at 4.5 V

Outputs open

All inputs at

SO
mA
95

4.5 V

160

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
tAli typical values are at VCC

=5

V, T A

=

25°C.

§ Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

I
I

•

switching characteristics, Vee = 5 V, T A = 25°e
PARAMETER~

tPLH

FROM (INPUT)

TO (OUTPUT)

CO

Any

Ai or Bi

~i

~

CL

tpHL
tpLH
tpHL
tPLH

CO

C4

Ai or Bi

C4

tpHL
tpLH
tpHL
~ tp LH
tpHL

MIN

TEST CONDITIONS

= 15 pF,

RL

= 280

fl,

See Note 3

TYP
11

MAX
18

12

18

12

18

11.5

18

6

11

CL=15pF, RL = 560 fl,

7.5

11

See Note 3

7.5

12

8.5

12

UNIT
ns
ns
ns
ns

= Propagation delay time, low-to-h igh-Ievel output
= Propagation delay time, high-to-Iow-Ievel output

NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-419

nL

TYPES SN54284, SN54285, SN74284, SN74285
4-BI1 -BY-4-BIT PARALLEL BINARY MULTIPLIERS

LSI

BULLETIN NO. DL-S 7211741, MAY 1972-REVISED DECEMBER 1972

•

Fast Multiplication of Two Binary Numbers
8-Bit Product in 40 ns Typical

•

Expandable for N-Bit-by-n-Bit Applications:
16-Bit Product in 70 ns Typical
32-Bit Product in 103 ns Typical

•

Fully Compatible with Most OTL and
TTL Circuits

•

Diode-Clamped Inputs Simplify System
Design

SN54284 .•• J OR W PACKAGE
SN74284 .•• J OR N PACKAGE
(TOP VIEW)
OUTPUTS

,....----"\..._---.

description
These high-speed TTL circuits are designed to be used
in high-performance parallel mUltiplication applications. When connected as shown in Figure A, these
circuits perform the positive-logic multiplication of
two 4-bit binary words. The eight-bit binary product
is generated with typically only 40 nanoseconds
delay.

~~GND
WORD INPUTS

positive logic: see description

SN54285 ..• J OR W PACKAGE
SN74285 •.. J OR N PACKAGE
rrQPVIEW)

This basic four-by-four multiplier can be utilized as a
fundamental building block for implementing larger
multipliers. For example, the four-by-four building
blocks can be connected as shown in Figure B to
generate submultiple partial products. These results
can then be summed in a Wallace tree, and, as
illustrated, will produce a 16-bit product for the two
eight-bit words typically in 70 nanoseconds.
SN54H 183/SN74H 183
carry-save
adders
and
SN54S181/SN74S181 arithmetic logic units with the
SN54S182/SN74S182 look-ahead generator are used
to achieve this high performance. The scheme is
expandable for implementing N X M bit multipliers.

II

WORD INPUTS

WORD

ENABLE

OUTPUTS

IN:~T 'GA"GB'~

schematics of inputs and o,..u_t;...pu_t_s_ _ _ _ _ __
~~GND

TYPICAL OF
ALL OUTPUTS

EQUIVALENT OF
EACH INPUT

WORD INPUTS

positive logic: see description

V C C63
k!1NOM
INPUT

WORD INPUTS

--

The SN54284 and SN54285 are characterized for
operation over the full military temperature range of
-55°C to 125°C; the SN74284 and SN74285 are
characterized for operation from aOc to 70°C.

1076

7·420

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DAL.LAS, TEXAS 75222

TYPES SN54284, SN54285, SN14284, SN14285
4-8IT-8Y-4-8IT PARALLEL 81NARY MULTIPLIERS

'"

N

g

'l-.

0-

III
II

~N

<{

-:..

:;J

;

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0

...i
II

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:£
0

(/)

_J

~I

II

00
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N
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a:

w

::i

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(/)

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:e

..J

co
X

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lil

a:

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u::

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co
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til
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M

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:£

:::I
C!J

8

:,
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<{

N

co

00
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~

Z

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a:

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w
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:::I

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if
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1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-421

TYPES SN54284. SN54285. SN74284. SN74285
4-BIT -BY-4-BIT PARALLEL BINARY MULTIPLIERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
...... .
Input voltage . . . . . . . . . . . . . . .
Operating free·air temperature range: SN54' Circuits
SN74' Circuits
Storage temperature range

7V
5.5V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54284

SN74284

SN54285

SN74285

MIN
Supply voltage, Vee

NOM

4.5

MAX

MIN

5.5

4.75

5

High-level output voltage, VOH
Low-level output current, IOL
Operating free·air temperature, T A

-55

NOM
5

UNIT
MAX
5.25

V

5.5

5.5

V

16

16

mA

70

°e

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

TYP:j: MAX UNIT

2

VI

Input clamp voltage

IOH

High-level output current

Vee- MIN,

11- -12mA

Vee= MIN,

VIH = 2V,

VIL = 0.8 V,

VOH = 5.5V

Vee = MIN,
VOL Low-level output voltage

•

MIN

V
0.8

V

-1.5

V

40

IOL = 12mA

0.4

IOL = 16mA

0.45

V

VIH = 2 V,
VIL =0.8V

/J A

II

Input current at maximum input voltage

Vee = MAX, VI = 5.5 V

1

IIH

High-level input current

Vee - MAX, VI = 2.4 V

40

/JA

IlL

Low-level input current

Vee - MAX, VI- 0.4 V

-1

mA

Vee - MAX,
TA = 125°e,

I'cc

i See Note 2

Supply current

SN54284, SN54285
N package only

mA

99

i

Vee = MAX, SN54284, SN54285

92

110

See Note 2

92

130

SN74284, SN74285

'rnA

I

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device
type.
:j:AII typical values are at V CC = 5 V, T A = 25° C.
NOTE 2: With outputs open and both enable inputs grounded, ICC is measured first by selecting an output product which contains three or
more high-level bits, then by selecting an output product which contains four low-level bits.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

tpLH Propagation delay time, low-to-high-Ievel output from enable

eL = 30 pF to GND,

20

30

tpH L Propagation delay time, high-to-Iow-Ievel output from enable

to Vee,

20

30

tPLH Propagation delay time, low-to-high-Ievel output from word inputs

n
RL2 = 600 n

to GND,

40

60

tPH L Propagation delay time, high-to-Iow-Ievel output from word inputs

See Note 3

40

60

RL1 = 300

ns
ns

NOTE 3: Load circuit is as described above; waveforms are shown on page 3-10.

1076

7-422

TEXAS INSTRUM ENTS
1 .... ( OIU'OH!\11

POST OFFICE BOX 5012

•

J)

DALLAS. TEXAS 75222

TYPES SN54290. SN54293. SN54LS290. SN54LS293
SN74290. SN74293. SN74LS290. SN74LS293
DECADE AND 4-BIT BINARY COUNTERS

TTL
MSI

BULLETIN NO. DL-S 7611833, MARCH 1974-REVISED OCTOBER 1976

SN54290, SN54LS290 ... J OR W PACKAGE
SN74290, SN74LS290 ... J OR N PACKAGE
(TOP VIEW)

'290, 'LS290 ... DECADE COUNTERS
'293, 'LS293 ... 4-BIT BINARY COUNTERS

OUTPUTS

•

GND and Vec on Corner Pins
(Pins 7 and 14 Respectively)

Vee

RO(2)

IN~UT IN~UT ~

description
R9(1)

The SN54290/SN74290, SN54LS290/SN74LS290,
SN54293/SN74293, and SN54LS293/SN74LS293
counters are electrically and functionally identical to
the SN5490A/SN7490A, SN54LS90/SN74LS90,
SN5493A/SN7493A, and SN54LS93/SN74LS93,
respectively. Only the arrangement of the terminals
has been changed for the '290, , LS290, '293, and
'LS293.

Qo

positive logic: see function tables

SN54293, SN54LS293 ..• J OR W PACKAGE
SN74293, SN74LS293 •• _J OR N PACKAGE
(TOP VIEW)

Each of these monolithic counters contains four
master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary
counter for which the count cycle length is divideby-five for the '290 and 'LS290 and divide-by-eight
for the '293 and 'LS293.
All of these counters have a gated zero reset and the
'290 and 'LS290 also have gated set-to-nine inputs for
use in BCD nine's complement applications.
To use the maximum count length (decade or four-bit
binary) of these counters, the B input is connected to
the QA output. The input count pulses are applied to
input A and the outputs are as described in the
appropriate function table. A symmetrical divide-byten count can be obtained from the '290 and 'LS290
counters by connecting the QD output to the A input
and applying the input count to the B input which
gives a divide-by-ten square wave at output QA.

•
positive logic: see function tables
NC-No internal connection

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

1-423

TYPES SN54290, SN54293, SN54LS290, SN54LS293,
SN74290, SN74293, SN74LS290. SN74LS293
DECADE AND 4-BIT BINARY COUNTERS
'290, 'LS290
BI-QUINARY (5-21
(See Note BI

'290, 'LS290
BCD COUNT SEQUENCE
(See Note AI
OUTPUT

COUNT

0

OUTPUT

COUNT

00 0c 0B 0A
L
L
L
L

0

'293, 'LS293
COUNT SEQUENCE
(See Note CI

'290, 'LS290
RESET/COUNT FUNCTION TABLE
OUTPUT

RESET INPUTS

0A 00 0c 0B
L
L
L
L

ROOI
H

RO(2)
H

R9(11
L

R9(2) 00
X
L

Dc
L

OUTPUT

COUNT

OB OA
L
L

00

Dc °B °A

0

L

L

L

L

1

L

L

L

H

1

L

L

L

H

H

H

X

L

L

L

L

L

1

L

L

L

H

2

L

L

H

L

L

L

H

L

X

X

H

H

H

L

L

H

2

L

L

H

L

3

L

L

H

H

2
3

L

L

H

H

X

L

X

L

COUNT

3

L

L

H

H

4

L

H

L

L

4

L

H

L

L

L

X

L

X

COUNT

4

L

H

L

L

5

L

H

L

H

5

H

L

L

L

L

X

X

L

COUNT

5

L

H

L

H

6

L

H

H

L

6

H

L

L

H

X

L

L

X

COUNT

L

H

H

L

7

L

H

H

H

7

H

L

H

L

6
7

L

H

H

H

8

H

L

L

L

8

H

L

H

H

8

H

L

L

L

9

H

L

L

H

9

H

H

L

L

9

H

L

L

H

'293, 'LS293
RESET/COUNT FUNCTION TABLE
RESET INPUTS

NOTES:

A. Output QA is connected to input B for BCD count.
B. Output QD is connected to input A for bi·quinary

Roell
H

count.
C. Output QA is connected to input B.
D. H = high level, L = low level, X = irrelevant

Roe21
H

OUTPUT

00

Dc °B °A

L

L

L

L

10

H

L

H

L

11

H

L

H

H

12

H

H

L

L

13

H

H

L

H

L

X

COUNT

14

H

H

H

L

X

L

COUNT

15

H

H

H

H

functional block diagrams
'290, 'LS290

'293, 'LS293

INPUT A . ;. (1_0..;..)_ _ _+-__--<11>

INPUT A . .:.(. ;. ;10"-')_ _ _ _-01>

(5)

(5) OB

II

INPUT B

OB

INPUT B .:. .(1:. . ;1. :. )_ _ _ _t-

(11)

---_.++----(1)

(4)

(8)

(8)

Oc

00

00

The J and K inputs shown without connection are for reference only and are functionally at a high level.

1076

7-424

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54290, SN54293, SN74290, SN74293
DECADE AND 4-81T BINARY COUNTERS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

Vee

vee3-Req

INPUT

--

OUTPUT
INPUT
A
B ('290)
B ('293)
All resets

Req NOM
2.5 kU
1.25 kU
2.5 kU
6kU

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1)
Input voltage . . . . . . . .
!nteremitter vo!tage (see Note 2)
Operating free·air temperature range: SN54' Circuits
SN74' Circuits
Storage temperature range
NOTES:

7V
5.5 V
5.5 V
-55°C to 125°C
DoC to 70°C
-65°C to 150°C

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For these circuits, this rating applies between the two
RO inputs, and for the '290 circuit, it also applies between the two R9 inputs.

•

recommended operating conditions
-----

SN54'

MIN
Supply voltage, VCC

4.5

High·level output current, IOH

NOM
5

SN74'

MAX

MIN

5.5

4.75

-800

Low-level output current, IOL

Pulse width, tw

0

32
16

B input

30

30

Reset inpu ts

15

15

25

!J.A

16

15

-55

V

-800

0

0
15

0

mA
MHz

ns

25
125

UNIT

5.25

32

B input

Reset inactive-state setup time, tsu

MAX

0

A input

Operating free-air temperature, T A

5

16

16
A input

Count frequency, fcount

NOM

ns

70

°c

10i6

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-425

TYPES SN54290, SN54293, SN74290, SN74293
DECADE AND 4-BI1 BINARY COUNTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

'290

TEST CONDITIONSt

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

Input current at maximum input voltage

IIH

High-level input current

MIN

TVP:j:

2

MIN

TVP:j:

Vee= MIN,

11=-12mA
VIH = 2 V,

VIL = 0.8 V,

10H = -800p.A

Vee - MIN,

VIH=2V,

VIL = 0.8 V,

10L = 16 mA~

3.4
0.2

Vee = MAX, VI = 2.4 V

B input
Any reset
High-level input current

A input

Vee = MAX,

VI = 0.4 V

B input

-1.5
2.4

3.4
0.2

0.4

Vee - MAX, VI- 5.5V

A input

0.8

-1.5
2.4

0.4

1

1

40

40

80

80

120

80

-1.6

-1.6

-3.2

-3.2

-4.8

-3.2

-20

-57

-20

-57

SN74'

-18

-57

-18

-57

Short-circuit output current §

Vee = MAX

lee

Supply current

Vee = MAX, See Note 3

l

29

42

26

V
V
V

I SN54'

lOS

UNIT
V

0.8
Vee = MIN,

MAX

2

Any reset

IlL

'293
MAX

39

V
mA
p.A

mA

mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C.

§ Not more than one output should be shorted at a time.
~QA outputs are tested at IOL = 16 mA plus the limit value of IlL for the B input. This permits driving the B input while maintaining full
fan-out capability.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

•

switching characteristics, Vee
PARAMETERO

f max
tpLH

FROM

TO

(INPUT)

(OUTPUT)

A
B

A

QA

tpHL
tPLH

A

tPHL
tpLH

B
B

tpLH
tpHL

TVP

°A

32

42

°B

16

,

00
°B

'293

RL = 400

n,

°e

MAX

UNIT

MIN

TVP

32

42

MAX
MHz

16
10

16

10

12

18

12

18

32

48

46

70

34

50

46

70

10

16

10

16

14

21

14

21

21

32

21

32

23

35

23

35

21

32

34

51

16

B

00

23

35

34

51

Set-to-O

Any

26

40

26

40

°A,OO

20

30

°B,Oe

26

24

tpHL
tPHL

MIN

See Note 4

tpHL
tpLH

'290
TEST CONDITIONS

eL=15pF,

tpHL
tPLH

= 5 V, TA = 25°e

Set-to-9

ns
ns
ns
ns

I

ns
ns
ns

Of max == maximum count frequency
tpLH '" propagation delay time, low·to-high·level output
tpH L '" propagation delay time, h igh-to·low·level output
NOTE 4: Load circuit and voltage waveforms are the same as those shown for the '90A and '93A, page 3-10.

1076

7-426

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS290, SN54LS293, SN74LS290, SN74LS293
DECADE AND 4-BIT BINARY COUNTERS
REVISED OCTOBER 1976

schematics of inputs and outputs
EQUIVALENT OF EACH RESET INPUT

Vcc - - - + - - 20 kn NOM
I NP UT

_-Wl-+-_~

TYPICAL OF ALL OUTPUTS

EQUIVALENT OF A AND B INPUTS

----+--VCC
120 n NOM

VC~
R1 R2 R3

INPUT

OUTPUT

NOMINAL VALUES
iNPUT
R1
R2
R3
A
10 kn 10 kn 10 kn
B ('LS290) 6.7 kn 6.7 kn
5 kn
!3 ('LS293)

~5

kn

15 k!1

1Q kn

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 5)
Input voltage: R inputs
A and B inputs
Operating free-air temperature range: SN54LS290, SN54LS293

7V

7V
5.5 V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

SN74LS290,SN74LS293
Storage temperature range

•

NOTE 5: Voltage values are with respect to network ground terminal.

recommended operating. cond itions
SN74LS'

SN54LS'
MIN
Supply VOltage, VCC

4.5

High-level output current, IOH

NOM
5

MAX

MIN

5.5

4.75

Count frequency, fcount

Pulse width, tw

0

32
16

0

32

0

16

B input

0

A input

15

15

B input

30

30

Reset inputs

15

15

Reset inactive-state setup time, tsu

25

Operating free-air temperature, T A

-55

5.25

8

4
A input

5

MAX

-400

-400

Low-level output current, IOL

NOM

0

V
p.A

mA
MHz

ns
ns

25
125

UNIT

70

°c

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-427

TYPES SN54LS290, SN54LS293, SN74LS290, SN74LS293
DECADE AND 4-BI1 BINARY COUNTERS
REVISED OCTOBER 1976

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOL Low-level output voltage
Input current
at maximum

Vee = MIN,

11=-18mA

Vee= MIN,

VIH = 2 V,

VIL = VIL max,

10H =-400IJA

Vee= MIN,

VIH = 2 V,

Any reset

Vee= MAX,

2.5
IIOL = 4

mA~

VI = 7 V

A input

input current

B of 'LS290

Vee = MAX,

VI=5.5V

VI = 2.7 V

B of'LS293
Any reset
Low-level
IlL

A input

output current B of 'LS290

Vee= MAX,

VI = 0.4 V

B of 'LS293
lOS
ICC

-20

Short-circuit output current§ Vee = MAX
Supply current

Vee = MAX,

V
0.8

V

-1.5

-1.5

V

2.7
0.4

See Note 3

V

3.4
0.25

0.4

0.35

0.5

0.1

B of'LS293

High-level

UNIT

TYP:j: MAX

0.7

3.4
0.25

A input
Vee= MAX,

MIN
2

Any reset
IIH

SN74LS'

TYP:j: MAX

IIOL=8mA~

VIL = VIL max

B of 'LS290

input voltage

MIN
2

VOH High-level output voltage

II

SN54LS'

TEST eONDITIONst

V

0.1

0.2

0.2

0.4

0.4

0.2

0.2

20

20

40

40

80

80

40

40

-0.4

-0.4

-2.4

-2.4

-3.2

-3.2

-1.6
-100

-1.6
-20

mA

IJA

mA

-100

I'Ls290

9

15

9

15

J'LS293

9

15

9

15

mA
mA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
tAli tvpical values are at VCC

=5

V, T A

= 25°C.

§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
~QA outputs are tested at specified IOL plus the limit value of IlL for the B input. This permits driving the B input while maintaining full
fan-out capability.
.
NOTE 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

•

switching characteristics,
PA-RAMETERO

f max

tpLH

J_

Vee = 5 V, TA = 25° e

FROM

TO

(INPUT)

(OUTPUT)

tPLH

32

°B

16

A

°A

A
B

tpLH

B
B
5et-to-0
Set-to-9

tpHL
¢f max

== maximum

°B

RL=2kn.,
See Note 6

tPHL
tpHL

°D
CL=15pF,

tPHL
tpLH

42

°A

tpHL
tpLH

TYP

A

tPHL
tPLH

MIN

B

tpHL

'LS293

'LS290

TEST CONDITIONS

°c

MAX

MIN

TYP

32

42

MHz

16
10

16

10

12

18

12

18

32

48

46

70

34

50

46

70

16

10

16

10

16

14

21

14

21

21

32

21

32

23

35

23

35

21

32

34

51

23

35

34

51

Any

26

40

26

40

°A,OD

20

30

°B,Oe

26

40

°D

UNIT

MAX

ns
ns
I

ns
ns
ns
ns
ns

count frequency

tPLH'" propagation delay time, low-to-high-Ievel output
tpH L '" propagation delay time, high-to-Iow-Ievel output
NOTE 6: Load circuit and voltage waveforms are the same as those shown for the 'LS90 and 'LS93, pages 7-80.

107~
7-428

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS295B, SN74LS295 B
4-BIT RIGHT-SHIFT LEFT-SHIFT REGISTERS
WITH 3-STATE OUTPUTS

TTL
MSI

BULLETIN NO. DL-S 7611780, OCTOBER 1976

•

'LS295B Offers Three Times the
Sink-Current Capability of 'LS295A

•

Schottky-Diode-Clamped Transistors

•

Low Power Dissipation ... 80 mW Typical
(Enabled)

•

Applications:
N-Bit Serial-To-Parallel Converter
N-Bit Parallel-To-Serial Converter
N-Bit Storage Register

SN54LS295B .•. J OR W PACKAGE
SN74LS295B •.. J OR N PACKAGE
(TOP VIEW)

description
These 4-bit registers feature parallel inputs, parallel
outputs, and clock, serial, mode, and output control
inputs. The registers have three modes of operation:

SI~~TL ~c~~f.C!EO!"

GND

INPUTS

Parallel (broadside) load
Shift right ithe direction QA toward GD)
Shift left (the direction GD toward GAl

iogic:

see function tabie

Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs after the high-to-Iow transition of the clock input.
During parallel loading, the entry of serial data is inhibited.
Shift right is accomplished when the mode control is low; shift left is accomplished when the mode control is high by
connecting the output of each flip-flop to the parallel input of the previous flip-flop (GD to input C,etc.) and serial data
is entered at input D.
When the output control is high, the normal logic levels of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a low logic level at the output control
input. The outputs then present a high impedance and neither load nor drive the bus line; however, sequential operation
of the registers is not affected.
The SN54LS2958 is characterized for operation over the full military temperature range of -55°C to 125°C; the
SN74LS2958 is characterized for operation from O°C to 70°C.
FUNCTION TABLE
INPUTS
MODE

CLOCK

SERIAL

H

H

H

CONTROL

OUTPUTS
PARALLEL
OA

OB

Oc

°AO

a

QSO
b

QCO QDO
c
d

QS n

QCn

Oon

°D

A

B

C

D

X

X

X

X

X

.j,

X

a

b

c

·d

H

.j,

X

QBt

d

L

H

X

X

X

L

.j,

H

X

X

X

X

L

.j,

L

X

X

X

X

QAO QSO QCO QDO
H
QAn QS n QCn
L
QAn °Sn QCn

Qct QDt
X

X

•

d

When the output control is low, the outputs are disabled to the high-impedance state;
however, sequential operation of the registers is not affected.
tShifting left requires external connection of QS to A, QC to B, and Q D to e. Serial data is
entered at input D.

H = high level (steady state), L = low level (steady state), X = irrelevant (any input, including transitions)
.j, = transition from high to low level.
a, b, c, d = the level of steady·state input at inputs A, B, e, or D, respectively.
QAO, QBO, Qeo, QDO = the level of QA' QS, Qe, or QD, respectively, before the indicated steady-state input conditions were established_
QAn, QSn' Qen, QDn = the level of QA' QB, Qe, or QD, respectively, before the most-recent .j, transition of the clock_

See explanation of function tables on page 3-8.

1076

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
I nstruments reserves the right to change or d iscontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED

F"OST OFFICE BOX 5012

•

DALL.AS. TEXAS 75222

7-429

TYPES SN54LS2958. SN74LS2958
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS
WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . . .
Input voltage . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS295B
SN74LS295B
Storage temperature range

7V
7V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74LS295B

SN54LS295B
MIN
Supply voltage, Vee

4.5

NOM
5

MAX

MIN

5.5

4.75

High-level output current, IOH

NOM
5

-1

Low-level output current, IOL

5.25

V

-2.6

mA

12

Clock frequency, fclock

0

20

UNIT

MAX

0

24

mA

20

MHz

Width of clock pulse, tw(clock)

25

25

Setup time, high-level or low-level data, tsu

20

20

ns

Hold time, high-level or low-level data, th

20

20

ns

Operating free-air temperature, T A

-55

125

ns

0

°e

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH High-level output voltage

•

VOL Low-level output voltage
Off-state output current,
IOZH high-level voltage applied
IOZL

SN54LS295B

TEST CONDITIONSt

MIN

TYP:j:

SN74LS295B

MAX

2
Vee = MIN,

II = -18 mA

Vee = MIN,

VIH=2V,

VIL = VIL max,

IOH = MAX

Vee - MIN,

VIH-2V,

VIL = VIL max
Vee= MAX,

2.4

Vee- MAX,

low-level voltage applied

VO=O.4 V

UNIT

MAX

V

0.7

0.8

V

-1.5

-1.5

V

3.4

2.4
0.4

IIOL = 24 mA
VIL - VIL max,

Vo = 2.7 V

Off-state output current,

TYP:j:

2

0.25

IIOL = 12 mA

MIN

VIH-2V,

V

3.1
0.25

0.4

0.35

0.5

20

20

-20

-20

V
p.A
p.A

,

Input current at
Vee = MAX,

VI =7 V

0.1

0.1

IIH

High-level input current

Vee = MAX,

VI=2.7V

20

20

p.A

IlL

Low-level input current

Vee - MAX,

VI = 0.4 V

-0.4

-0.4

mA

lOS

Short-circuit output current§

Vee = MAX

-130

mA

ICC

Supply current

Vee = MAX,

II

maximum input voltage

-30
See Note 2

-130

-30

lCondition A

16

27

16

27

I Condition B

17

29

17

29

mA

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time,and duration of the short·circuit should not exceed one second.
NOTE 2: ICC is measured with the outputs open, the serial input and mode control at 4.5 V, and the data inputs grounded under the following
conditions:
A. Output control at 4.5 V and a momentary 3 V, then ground, applied to clock input.
B. Output control and clock input grounded.

DESIGN GOAL

1076

7-430 ~;~~:c~gei~r~~i:e~:~~I~~~:nitnaflor;:;!~nT~:a: TEXAS INSTRUMENTS
Instruments reserves the right to change or dis·
continue this product without notice.

INCORPORATED
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN54LS2958 SN74LS2958
4-81T RIGHT-SHIFT LEFT-SHIFT REGISTERS
WITH 3-STATE OUTPUTS
switching characteristics,

Vee =5 V, T A = 25 e, RL = 667 n
PARAMETER

TEST CONDITIONS

f max Maximum clock frequency
tpLH Propagation delay time, low-to-high-Ievel output

CL = 45 pF,

tpHL Propagation delay time, high-to-Iow-Ievel output

See Note 3

tpZH Output enable time to high level
tpZL Output enable time to low level

MIN

TYP

25

35

MAX UNIT
MHz

20

30

ns

23

35

ns

17

26

ns

28

42

ns

tpHZ Output disable time from high level

CL=5pF,

13

20

ns

tPLZ Output disable time from low level

See Note 3

17

26

ns

NOTE 3: Load circuit and voltage waveforms are shown on page 3-11.

functional block diagram
~

OUTPUT
CONTROL

___________________________DATA INPUTS
______________________________
~i'~

~

(8)

•

~~-------------~~---~v~--~------~
OUTPUTS

schematics of inputs and outputs
EQUIVALENT OF SERIAL
AND DATA INPUTS

EQUIVALENT OF CLOCK,

TYPICAL OF ALL OUTPUTS

MODE CONTROL, AND
OUTPUT CONTROL INPUTS

- - - - _ - Vee
vee
Req
INPUT

......

-~

~~

OUTPUT

"
~~

~t
r.

Serial: Req = 30 k.l1 NOM
A,B,C, D: Req = 20 k.l1 NOM

1076

DESIGN GOAL
This page provides tentative information on a

product in the developmental stage. Texas
Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-431

TTL
MSI

TYPES SN54298. SN54LS298. SN74298. SN74LS298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
BULLETIN NO. DL-S 7611747, MARCH 1974-REVISED OCTOBER 1976

•

Selects One of Two 4-Bit Data Sources
and Stores Data Synchronously with
System Clock

•

Applications:
Dual Source for Operands and Constants
in Arithmetic Processor; Can Release
Processor Register Files for Acquiring New
Data

SN54298, SN54LS298 ... J OR W PACKAGE
SN74298, SN74LS298 .• , J OR N PACKAGE
(TOP VIEW)
OUTPUTS

DATA
WORD INPUT

~
VCC

OA

OB

Oc

00 ClOCKSElECT

13

Implement Separate Registers Capable of
Parallel Exchange of Contents Yet Retain
External Load Capability

CK
B2

Universal Type Register for Implementing
Various Shift Patterns; Even Has Compound
Left-Right Capabilities

C1

A2

description
These monolithic quadruple two-input multiplexers
with storage provide essentially the equivalent
functional capabilities of two separate MSI functions
(SN54157/SN74157 or SN54LS157 /SN74LS157 and
SN54175/SN74175 or SN54LS175/SN74LS175) in a
single 16-pin package.

•

V

DATA INPUTS

logic: see function table

functional block diagram

When the word-select input is low, word 1 (A 1, B1,
C1, 01) is applies to the flip-flops. A high input to
word select will cause the selection of word 2 (A2,
B2, C2, 02). The selected word is clocked to the
output terminals on the negative-going edge of the
clock pulse.
Typical power dissipation is 195 milliwatts for the
'298 and 65 milliwatts for the 'LS298. SN54298
and SN54LS298 are characterized for operation over
the full military temperature range of -55°C to
125°C; SN74298 and SN74LS298 are characterized
for operation from O°C to 70°C.
FUNCTION TABLE
lNPUTS
WORD

OUTPUTS
aA

aB

ac

aD

L

~

a1

b1

c1

d1

H

~

a2

b2

c2

d2

X

H

SELECT

CLOCK

QAO QBO QCO QDO

CLOCK ...!I.:.:",-I- - - - - - - - 1

H = high level (steady state)
L = low level (steady state)
X = irrelevant (any input, including transitions)
• = transition from high to low level
a1, a2, etc. = the level of steady-state input at A 1, A2, etc.
0AO, 0BO, etc. = the level of 0A, 0B, etc. entered on the
most~recent ~ transition of the clock input.

:>_ _ _ _---'

-J:. ... Dynamic input activated by a transition from a high level
I

to a low level

1076

7-432

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

TYPES SN54298, SN54LS298, SN74298, SN74LS298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
REVISED OCTOBER 1976

schematics of inputs and outputs

'298

'298

EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

-----VCC

V C C - -.....- -

INPUT

~~
Clock:
All other inputs:

'LS298

Req
Req

=4
=6

I-~

I

kn NOM
kn NOM

L._ _ _ _ _ _ _ _ _ _~

'LS298

'LS29S

EQUIVALENT OF DATA INPUTS

OUTPUT

EQUIVALENT OF OTHER INPUTS

TYPICAL OF ALL OUTPUTS
- - - -........-VCC

V C C - -......- VCC---+---

15 kn NOM
17 kn NOM
INPUT-...,...........-

.......
INPUT -...,...........-

.......

'L----4t-- 0

UTP UT

•

76

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-433

TYPES SN54298, SN74298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . .
Input voltage . . . . . . . . . . . . .
Operating free-air temperature range: SN54298
SN74298
Storage temperature

7V

5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54298
MIN

NOM

4.5

5

Supply voltage, Vee

SN74298
MAX

MIN

NOM

5.5

4.75

5

-800

High-level output current, 10H
Low-level output current, 10L

16

Width of clock pulse, high or low level, tw
Setup time, tsu
Hold time, th

20

20

Data

15

15

Word select

25

25

Data

5

5

Word select

0

0

Operating free-air temperature, T A

-55

125

MAX

UNIT

5.25

V

-800

IJ.A

16

mA
ns
ns
ns

70

0

°e

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

TEST CONDITIONSt

VOL Low-level output voltage

I

TYP:j:

MAX

Vee = MIN,

11= -12 mA

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10H = -8001J.A

Vee = MIN,

VIH=2V,

VIL = 0.8 V,

10L = 16 mA

II

Input current at maximum input voltage

Vee = MAX, VI = 5.5 V

2.4

UNIT
V

2

VOH High-level output voltage

•

MIN

0.8

V

-1.5

V
V

3.2
0.4
1

V
mA

IIH

High-level input current

Vee = MAX, VI = 2.4 V

40

IJ.A

IlL

Low-level input current

Vee = MAX, VI = 0.4 V

-1.6

mA

lOS

Short-circuit output current§

Vee = MAX

ICC

Supply current

Vee =MAX, See Note 2

I SN54298

! SN74298

-20

-57

-18

-57
39

65

mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time.
NOTE 2: With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5 V, followed by ground, to
the clock input.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

r-:tP...:L::.:.H-,--P_ro....:pa---=:.ga_t_io_n_d_e_la..;.y_t_im_e..;.,_lo_w_-_to_-_h·.::lg_h-_le_v_el_o_u_tP;...u_t_ _ _ _ _ _ _-I CL = 15 pF,
tPHL Propagation delay time, high-to-Iow-Ievel output
NOTE 3:

See Note 3

RL = 400.11,

MIN

TYP

MAX

18

27

21

32

Load circuit and waveforms are shown on page 3·10.

10

7-434

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS298,SN74LS298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS298
SN74LS298
Storage temperature range

7V
7V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS298
MIN

NOM

4.5

5

Supply voltage, Vee

SN74LS298

MAX

MIN

NOM

5.5

4.75

5

-400-

High-level output current, 10H
Low-level output current, 10L

MAX
5.25

V

-400

/LA

8

mA

4

Width of clock pulse, high or low level, tw
Setup time, tsu

20

20

I Data

15

15

I Word select

25

25

5

5

Hold time, th

o
-55

Operating free-air temperature, T A

125

UNIT

ns
ns

o
o

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

V,L

Low-level input voltage

VIK

Input clamp voltage

MIN

TYP:j:

SN74LS298

MAX

2

VOH High-level output voltage
VOL Low-level output voltage

Vee= MIN,

I, =-18mA

Vee= MIN,

V'H=2V,

VIL = VIL max,

10H = -400/LA

Vee = MIN,

VIH=2V,

maximum input voltage

2.5

MIN

VI = 7V

MAX

UNIT
V

0.7

0.8

V

-1.5

-1.5

V

2.7

3.4
0.4

I'OL =8mA

Vee = MAX,

TYP:j:

2

0.25

IIOL = 4 mA

V,L = VIL max

Input current at
II

SN54 LS298

TEST eONDITIONSt

PARAMETER

V

3.4
0.25

0.4

0.35

0.5

0.1

0.1

V
mA

IIH

High-level input current

Vee = MAX,

V, = 2.7 V

20

20

/LA

I,L

Low-level input current

.Vee= MAX,

VI = 0.4 V

-0.4

-0.4

mA

lOS

Short-circuit output current§

Vee = MAX

-100

mA

lee

Supply current

Vee = MAX,

21

mA

-20
See Note 2

-100
13

-20
13

21

•

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are.at V CC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5 V, followed by ground, to
the clock input.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER

TEST CONDITIONS

tpLH Propagation delay time, low-to-high-Ievel output

eL=15pF,

tpHL Propagation delay time, high-to-Iow-Ievel output

See Note 4

RL=2kn,

MIN

TYP

MAX

18

27

21

32

NOTE 4: Load circuit and waveforms are shown on page 3-11.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-435

TYPES SN54298, SN54LS298, SN14298, SN14LS298
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
TYPICAL APPLICATION DATA
This versatile multiplexer/register can be connected to operate as a shift register that can shift N-places in a single
clock pulse.
The following figure illustrates a BCD shift register that will shift an entire 4-bit BCD digit in one clock pulse.
PARALLEL LOAD

Ir------------------~A~

A1

I
WS

l A1

QA~

A2
B2 'L~;98
"-- C1 REG
1
C2
"--- D1

CLOCK

I

T

<;,t<

-

QB~

--

ac:-::

l A1

-

WS QA

A2

..... B1 '298

D2

________________~\

I

B1 '298
or QB
B2 'LS298
C1 REG
2 Dc
C2

A2

~

D2

-

~

C~

QD

QA

ac

D1
D2

CK QD

A

y

£

-

-

WORD SELECT

..... B1 '298
or QB
B2 'LS298
Cl REG
3
C2

--

~

'---- D1

QD

T
WS

c..r

~

~
DIGIT 1

DIGIT 2

DIGIT 3

When the word-select input is high and the registers are clocked, the contents of register 1 is transferred (shifted) to
register 2 and etc. In effect, the BCD digits are shifted one position. In addition, this application retains a parallel-load
capability which means that new BCD data can be entered in the entire register with one clock pulse. This arrangement
can be modified to perform the Shifting of binary data for any number of bit locations.

•

Another function that can be implemented with the '298 or 'LS298 is a register that can be designed specifically for
supporting multiplier or division operations_ The example below is a one place/two-place shift register.

---------1
I
'181, 'LS181, or 'S181

(ALU)

FO

F1

F2

F3

A 1 A2 B1 B2 C1 C2 D1 D2

T-------T
'181, 'LS181, or 'S181
(ALUI
FO
F1
F2
F3

A1 A2 B1 B2 C1 C2 D1 D2
WS

WORD

'-----~-~-~~-~--~SELECT

When word select is low and the register is clocked, the outputs of the arithmetic/logic units (ALU's) are shifted one
place. \Nhen word select is high and the registers are clocked, the data is shifted two places.

37~

7·436

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS299, SN54S299, SN74LS299, SN74S299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

TTL
LSI

BULLETIN NO. DL.S 7612115. MARCH 1974-REVISED OCTOBER 1976

•

Multiplexed Inputs/Outputs Provide
Improved Bit Density

SN54LS299, SN54S299 ..• J PACKAGE
SN74LS299, SN74S299 •.. J OR N PACKAGE
(TOP VIEW)

•

Four Modes of Operation:
Shift Left
Hold (Store)
Shift Right
Load Data

•

Operates with Outputs Enabled or at High Z

•

3-State Outputs Drive Bus Lines Directly

•

Can Be Cascaded for N-Bit Word Lengths

•

SN54LS323 and SN74LS323 Are Similar
But Have Synchronous Clear

•

Applications:
Stacked or Push-Dow!"! Registers.

TyPE

so

SHiFT iCLOCK;

POWER

FREQUENCY

DISSIPATION

35 MHz

175mW

'S299

50 MHz

700mW

H/QH

D/QD

BiOs

CLOCK

SR

L..:J L.:J L.:.J LJ L..J L:.J L..:.J L:.J L..J L.:J

TYPICAL

'LS299

SHIFT

RIGHT
CHI

~jRgRLLLL1,L"J II

Buffer Storage, and
Accumulator Registers
GUARANTEED

SHIFT
LEFT
SL

VCC

~ GIQG

C/Oc

EIQE

AIQA

QA'

CLEAR

GNO

OUTPUT
CONTROLS

logic: see

~escription

and function table

description
These Schottky TTL eight-bit universal registers feature multiprexed inputs/outputs to achieve full eight bit data
handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose
the modes of operation listed in the function table.
Synchronous parallel loading is accomplished by taking both function-select lines, SO and S1, high. This places the
three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked
into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct
overriding input is provided to clear the register whether the outputs are enabled or off.

•

FUNCTION TABLE
INPUTS
MODE

FUNCTION
CLEAR

SELECT
S1

Clear
Hold
Shift Right
Shift Left
Load

SO

INPUTS/OUTPUTS

OUTPUTS

OUTPUT
SERIAL
CONTROL CLOCK
A/QA B/QB C/Qc D/QD E/QE F/QF
G1 t
G2t
SL SR

GIDG

H/QH QA'

QH'

L

X

L

L

L

X

X

X

L

L

L

L

L

L

L

L

L

L

L

X

L

L

X

X

X

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

X

X

X

QAO

QBO

QCO

QOO

QEO

QFO

QGO

QHO

QAO

QHO

H

X

X

L

L

L

X

X

QCO

QOO

QEO

QFO

QGO

QHO

L

H

L

L

t

X

H

QAO
H

QBO

H

QAn

QBn

Ocn

QO n

QEn

QFn

QGn

QAO QHO
H
QGn

H

L

H

L

L

L

L

QAn

QBn

QCn

QO n

QEn

QFn

H

L

L

L

t
t

X

H

H

X

QBn

QCn

QO n

QEn

QFn

DGn

QHn

QGn
H

QBn

H

H

L

L

L

L

X

QO n

QEn

QFn

L

QBn

L

H

X

X

X

X

b

c

d

e

QGn
f

QHn

H

QBn
a

QCn

H

g

h

a

h

t
t

L

L

DGn
H

tWhen one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however,
sequential operation or clearing of the register is not affected.

a ... h

= the

level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip-flop

outputs are isolated from the input/output terminals. See explanation of function tables on page 3-8.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-437

TYPES SN64LS299, SN64S299, SN74LS299, SN74S299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
functional block diagram

1£

w

>-+---g

•

M

= '"

>-+---~

37'

7438

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS299, SN74LS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

TYPICAL OF OUTPUTS

TYPICAL OF OUTPUTS

QA'THRUQH'

QA THRUQH

----+--VCC

-----VCC

OUTPUT

OUTPUT

SO, S1: Req= 9 kU NOM
All other inputs: Req= 18 kU NOM

3b~cluta

mIDtimum ratings uvCii opaiatiiig fies-air tempSra'Lufe fBilge (unless otherwise nomoj

Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Off-state output voltage
Operating free-air temperature range: SN54LS299
SN74LS299
Storage temperature

7V
7V
7V
-55°C to 125°C
aOe to 7aoe
-65°C to 15aoe

NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS299
NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

Supply voltage, VCC
High-level output current, IOH

QA thru QH

Width of clear pulse, tw(clear)

Setup time, tsu

Hold time, th

-2.6

-0.4

-0.4

12

24

QA' orQH'

4

8

Clock .frequency, f clock
Width of ciock pulse, tw(clock)

-1

QA thru QH

QA' or QH'
Low-level output current, IOL

SN74LS299

MIN

0
Clock high

35

0

20

20

Clock low

20

20

Clear low

20

20

Select

10t

10t

High-level data O

20t

20t

Low-level data O

20t

20t

Clear inactive-state

20t

20t

Select

10t

10t

Data O

ot

Operating free-air temperature, T A

-55

35

0

V
rnA
rnA
MHz

•

ns
ns

ns

ns

ot
125

UNIT

70

°c

0Data includes the two serial inputs and the eight input/output data lines.

76

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
Instruments reserves the right to change or dis·
continue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-439

TYPES SN54LS299, SN74LS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

Vil

low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

TEST CONDITIONSt

VCC =MIN,

II =-18mA

QA thru QH

VCC = MIN,

VIH = 2 V,

QA' or QH'

Vil = Vilmax, 10H = MAX

QA thru QH

VCC= MIN,
VIH=2V,

QA' or QH'

VIL = VILmax

Off-state output current,
10ZH

II
IIH
IlL

VCC - MAX,

QA thru QH

high-level voltage applied
Off-state output current,

10ZL

SN74lS299
UNIT
MAX MIN TYp:j: MAX

2

Low-level output voltage

VOL

SN54lS299
MIN TYP:j:

Input current at maximum

SO, S1

input voltage

Any other

VCC = MAX,

Any other
SO,S1

Low-level input current

Any other

lOS

Short-circuit output current§

ICC

Supply current

QA thru QH
QA' or QH'

2.4

VCC = MAX,
VCC = MAX,
VCC = MAX,

3.1

2.7

0.25

10L = 24 mA
10L =4mA

0.4

0.25

10L =8 mA
VIH-2V,
VIH=2V,

VCC = MAX

0.5

0.25

0.4

0.35

0.5

-20

V

/JA

-400

-400

/JA

0.2

0.2

0.1

0.1

40

40

30

30

-0.8

-0.8

-0.4

VCC - MAX

0.4

0.35

40

VI = 2.7 V

-30

V

40

VI = 7V

VI = 0.5 V

V

V

3.4

0.4

0.25

VO=O.4V

A thru H, SO, S1

High-level input current

-1.5

3.4

2.7

10l = 12 mA

-1.5
3.2

2.4

V
0.8

VO=2.7V

QA thru QH

low-level voltage applied

2
0.7

-0.4

-130

-30

-100

-20

-130
-100

66

35

35

60

mA
/J A
mA
mA
mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

•

switching characteristics, Vee
PARAMETER'

= 5 V, TA = 25°e

FROM

TO

(INPUT)

(OUTPUT)

TEST CONDITIONS

f max

See Note 2

tPLH

Clock

tPHL
tPHL
tPLH

!

tpHL
tpZH

Clear

QA'or QH'
QA thru QH

Clear

QA thru QH

<3\<32

tPZL
tpHZ

<31,<32

RL=2k!1,

See Note 2

Clock

tpHL

CL=15pF.

QA' or QH'

CL=45pF,

RL = 665

n,

See Note 2

QA thru QH
CL =5pF,

QA thru QH

RL = 665

See Note 2

tPLZ

n,

MIN

TYP

35

50

MAX

UNIT
MHz

15

25

15

25

20

35

15

25

15

25

20

35

20

35

20

35

15

25

15

25

ns
ns
ns
ns
ns
ns

, f max "" maximum clock frequency
tpLH "" propagation delay time, low-to-high-Ievel output.
tpHL "" propagation delay time, high-to-Iow-Ievel output
tpZH "" output enable time to high level
tpZL "" output enable time to low level
tpHZ "" output disable time from high level
tpLZ "" output disable time from low level
NOTE 2: For testing f max , all outputs are loaded simultaneously, each with CL and RL as spacified for the propagation times. See lOad
circuits and waveforms on page 3-11.

DESIGN GOAL

7-440

This page provides tentative information on a

product in the developmental stage. Texas
Instruments reserves the right to change or dis·
continue this product without notice.

10,

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TYPES SN54S299, SN74S299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
schematics of inputs and outputs
EQUIVALENT OF CLOCK AND
CLEAR INPUTS

EQUIVALENT OF G1
AND G21NPUTS

VCC~--

Req
VCC13-INPUT

EQUIVALENT OF A THRU Ht,SO, S1,
SHIFT RIGHT, AND SHIFT LEFT INPUTS

2.8 kn
NOM

--

VCC~5;n
NOM

--

INPUT

INPUT

Clock: Req = 2.8 kn NOM
Clear: Req = 3.5 kn NOM

--

tWhen 3-state outputs are disabled.

TYPICAL OF OUTPUTS

;;:;;;,;:t

50~

_

V CC

~OUT'Ul

absolute maximum ratings over operatinQ free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
!nput voltage . . . . . . . .
Off-state output voltage
Operating free-air temperature range: SN54S299 (see Note 2)
SN74S299
Storage temperature

. 7V
5.5 V

5.5 V
-55°e to 125°C
aOe to 7aoe
-65°e to 15aoC

NOTES 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54S299
Supply voltage, VCC
High-level output current, IOH

MIN

NOM

MAX

MIN

NOM

4.5

5

5.5

4.75

5

QA thru QH

Width of clear pulse, tw(clear)

Setup time, tsu

-6.5

-D.5

20

20

QA' or QH'

6
0

50

6
0

Clock high

10

10

Clo~k

10

10

low

Clear low

10

10

Select

15t

15t

7t

7t

5t

5t

10t

10t

High-level data O
Low-level data O
CI ear i nactive-state

Hold time, th

5.25

-2
-0.5

Clock frequency, fclock
Width of clock pulse, tw(clock}

MAX

QA thru QH

QN or QH'
Low-level output current, IOL

SN74S299

Select

5t

5t

DataO

5t

5t

Operating free-air temperature, T A

-55

125

0

50

UNIT

•

V
mA
mA
MHz
ns
ns

ns

ns
70

°c

°Data includes the two serial inputs and the eight input/output data lines.
1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-441

TYPES SN54S299. SN74S299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

TEST CONDITIONSt

MAX

QA thru QH

QA thru QH

high-level voltage applied

Input current at maximum input voltage

IIH

High-level input current

Vec = MIN,

VIH =2 V,

2.4

3.2

VIL = 0.8 V,

10H = MAX

2.7

3.4

VCC = MIN,

VIH - 2 V,
10L = MAX

VCC = MAX,

VIH -2 V,

VCC = MAX,

QA thru QH

II

II =-18mA

Any other

VCC = MAX,

VI = 5.5 V

VCC= MAX,

VI = 2.7 V

Vec = MAX,

VI=0.5V

Clock or clear

Low-level input current

lOS

Short-circuit output current§

ICC

Supply current

Any other
QA thru QH

VIH = 2 V,

Va = 0.5 V

A thru H, SO, Sl

IlL

-1.2

Va = 2.4 V

Off-state output current,
low-level voltage applied

Vee = MIN,

VIL = 0.8 V,

QA' or QH'

V

100

/J A

-250

/J A

1
100

rnA

-2
-100

-20

V

0.5

-250
-100

VCC= MAX

V

V

50

-40

Vee = MAX

UNIT
V

0.8

Off-state output current,

10ZL

TYP:j:

2

QA' orQH'

10ZH

MIN

140

225

MIN

TYP

MAX

50

70

/JA
rnA
/JA
rnA
rnA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
o

:j:AII typical values are at Vee = 5 V, T A = 2S e.
§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

•

switching characteristics, Vee
PARAMETER.

=5 V, TA =25°e

FROM

TO

(INPUT)

(OUTPUT)

TEST CONDITIONS

f max

tPLH

See Note 2
Clock

QA'orQH'

Clear

QA' or QH'

Clock

QA thru QH

Clear

QA thru QH

<31, <32

QA thru QH

tPHL
tpHL
tPLH
tpHL
tPHL
tpZH
tPZL
tPHZ
tPLZ

G1,G2

CL = 15 pF,

RL = 1 kn,

See Note 2

CL =45 pF,

RL = 280n,

See Note 2

eL-5pF,

QA thru QH

See Note 3

RL -280n,

UNIT
MHz

12

20

13

20

14

21

ns

15
15

21
21

ns

16

24

ns

10

18

12

18

7

12

7

12

ns

ns
ns

1 f max == maximum clock frequency
tpLH == propagation delay time, low-to-hi9h-level output.
tpHL == propagation delay time, high-to-Iow-Ievel output
tpZH == output enable time to high level
tpZL == output enable time to low level
tpHZ == output disable time from high level
tpLZ == output disable time from low level
NOTE 3: For

testing f max , all outputs are loaded simultaneously, each with eL and RL as specified for the propagation times. See load
circuits and waveforms on page 3-10.

1076

7-442

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TTL
LSI

TYPES SN54LS323, SN74LS323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
BULLETIN NO. DL·S 7612462, OCTOBER 1976

•

Multiplexed Inputs/Outputs Provide
Improved Bit Density

•

Four Modes of Operation:
Hold (Store)
Shift Left
Shift Right
Load Data

SN54LS323 .•. J PACKAGE
SN74LS323 •.• J OR N PACKAGE
(TOP VIEW)

SHIFT

•

Operates with Outputs Enabled or at High Z

•

3-State Outputs Drive Bus Lines Directly

•

Can Be Cascaded for N-Bit Word Lengths

•

Typical Power Dissipation ... 175 mW

•

Guaranteed Shift (Clock) Frequency ... 35 MHz

•

Applications:
Stacked or Push-Down Registers,
Buffer Storage, and
A. __ •• _

LEFT
SL

OH'

HIOH

F/oF

D/oD

BlOB

so

~ G/QG

E/QE

clDc

AlGA

QA'

RIGHT
SR

•• 1...,. .. __ D __ : .. . , . _

I""\."","UIIIUIQLUI

e

SHIFT

Vee

I";;;:!::II"'''GI~

SN54LS299 and SN74LS299 Are Similar

CLEAR

GND

OUTPUT
CONTROLS

But Have Direct Overriding Clear
logic: see description and function table

description
These Low-Power Schottky eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data
handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose
the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both
function-select lines, SO and S1, high. This places the three-state outputs in a high-impedance state, which permits data
that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished
while the outputs are enabled in any mode. The clear function is synchronous and a low level at the clear input clears
the register on the next low-to-high transition of the clock.
FUNCTION TABLE
INPUTS
MODE

FUNCTION
CLEAR

SELECT
S1

Clear
Hold
Shift Right
Shift Left
Load

SO~

INPUTS/OUTPUTS

OUTPUTS

OUTPUT

SERIAL
CONTROL CLOCK
A/QA B/QB C/Qc D/QD E/QE F/QF G/O(; H/QH QA'
G1 t G2 t
SL SR

QH'

L

L

X

L

L

t
t

X

X

L

L

L

L

L

L

L

L

H

L

L

L

L

X

X

X

QAO

QBO

QCO

QDO

QEO

QFO

QGO

QHO

QAO QHO

H

X

X

L

L

L

X

X

QCO

QDO

QEO

QFO

QGO

QHO

L

H

L

L

t

X

H

QAO
H

QBO

H

QAn

QBn

Den

QDn

QEn

QFn

QGn

QAO QHO
H
QGn

H

L

H

L

L

t

X

L

L

QAn

QBn

QCn

QDn

QEn

QFn

H

H

L

L

L

t

H

X

QBn

QCn

QDn

QEn

QFn

QGn

QHn

QGn
H

QBn

H

H

L

L

L

t

L

X

QBn

QCn

QDn

QEn

QFn

QGn

QHn

L

QBn

L

H

H

H

X

X

t

X

X

a

b

c

d

e

f

g

h

a

h

L

X

L

L

L

X

L

X

L

L

L

L

L

L

L

L

L

L

L

L

•

DGn
H

tWhen one or both output controls are high the eight input/output terminals are disabled to the high-impedance state; however,
sequential operation or clearing of the register is not affected.
a . . . h = the level of the steady·state input at inputs A through H, respectively. These data are loaded into the flip·flops while the flip-flop
outputs are isolated from the input/output terminals. See explanation of function tables on page 3-8.

schematics of inputs and outputs, absolute maximum ratings, recommended operating conditions, and
electrical characteristics
Same as SN54LS299 and SN74LS299, see page 7-439.
1076

DESIGN GOAL
This page provides tentative information on

d

product in the developmental stage. Texas
I nstruments reserves the right to change or discontinue this, product.without notice.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-443

TYPES SN54LS323, SN74LS323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
functional block diagram
Sl
(19)

so
(1)

CLEAR ----''''--t-."

".'"

10H = -1.2 mA,See Note 3

VOL low-level output voltage
II

MIN

voitage at enable·
low-level input

Vil

SN74lS'

TYP:t: MAX

0.25

0.4

IOl = 24mA

Vee = MAX

3.4

V

0.25

0.4

0.35

0.5

VI =5V

50

250

50

250

VI= 1 V

10

50

10

50

V
IlA

Input current
at maximum

II

Enable+

Vee= MAX,

VI =7V

Enable+

Vee= MAX,

VI = 2.7 V

Enable.

Vee = MAX,

VI =0.4V

0.1

0.1

mA

input voltage

High-Iavel
IIH

input current
low-level

III
lOS
ICC

input current

I

20 1

20

-0.4

-0.4

mA

Short·circuit output current!!

Vee= MAX

-225

mA

Supply current, total into

Vee - Max

I 'LS324, 'lS326

18

30

18

30

See Note 4

I

mA

VCC and9v'cc pins

30

50

30

50

-40

-225

'LS325, 'LS327

-40

1''"'

II

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
= 5 V, T A = 25° e.

:j: All typical values are at Vee

§ Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second •
• The characteristics involving an enable input are applicable to 'LS324 and 'LS326 only.
NOTES: 3. VOH is measured for Y outputs by connecting a 1-kn resistor from eX1 to Vee and another 1-kn resistor from eX2 to GND.
This procedure is reversed for testing VOH of

Y outputs

(not applicable to 'LS327). That is, a 1-kn resistor is connected from

eX2 to Vee and another 1-kn resistor from eX1 to GND. During the VOH tests of 'LS324 and 'LS326, the enable pin should
be at VIL max.
4. For 'LS324 and 'LS326, ICC is measured with the outputs disabled and open, and
measured with one

e

Vee = MAX, and with the other

e

e

Vee = MAX. For 'LS325 and 'LS327, ICC is

Vee and outputs open.

switching characteristics, Vee = 5 V (unless otherwise noted), RL
PARAMETER

= 667 il, eL = 45 pF, TA = 25°e

TEST CONDITIONS

= 5 v,
IVI(freq) = 0 V,

lVI(freq)

MIN

TYP

VI(rnQ) = 0 V

20

30

VI(rng) = 5 V

11

20

10

20

fo

Output frequency

Cext = 2 pF

to

Output frequency (crystal controlled)

eVCC=3V, VI(freq) = Vl(rng) = 0 V
Cext = 8.3 pF to 500 IlF

Output duty cycle
Propagation delay time,
tpHL

to;;' 1 Hz

high·to·low·level output from enable

"'The range input is provided only on the 'LS324.
'The delay will typically be 30 ns pulse up to one

MAX

UNIT
MHz
MHz

50%
30+*

ns

1 X 109
period of one cycle (I.e. 30 ns + - - - ns I depending upon the timing of the enable

pulse with respect to the signal generated by the internal oscillator.

fo(Hz)

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-447

TYPES SN54LS348, SN74LS348 (TIM9908)
8-UNE-TO-3-UNE PRIORITY ENCODERS
WITH 3-STATE OUTPUTS

TTL
MSI

BULLETIN NO. D

•

SN54LS348 •.. J OR W PACKAGE
SN74LS348 •.• J OR N PACKAGE
(TOP VIEW)

3-State Outputs Drive Bus Lines Directly

•

Encodes 8 Data Lines to 3-Line Binary (Octal)

•

Applications Include:
N-Bit Encoding
Code Converters and Generators

•

Typical Data Delay ... 15 ns

•

Typical Power Dissipation ... 60 mW

OCTOBER 1976

description
These TTL encoders feature priority decoding of the
inputs to ensure that only the highest-order data line
is encoded. The 'LS348 circuits encode eight data
lines to three-line (4-2-1) binary (octal). Cascading
circuitry (enable input EI and enable output EO) has
been provided to allow octal expansion. Outputs AD,
A1, and A2 are implemented in three-state logic for
easy expansion up to 64 lines without the need for
external circuitry. See Typical Application Data.

positive logic: see function table

functional block diagram
EI

{51

0 1101

,(111

FUNCTION TABLE
INPUTS

•

OUTPUTS

21121

EI

0

1

2

3

4

5

6

7

A2

Al

AO

GS

EO

H

X

X

X

X

X

X

X

X

Z

Z

Z

H

H

L

H

H

H

H

H

H

H

H

Z

Z

Z

H

L

L

X

X

X

X

X

X

X

L

L

L

L

L

H

L

X

X

X

X

X

X

L

H

L

L

H

L

H

L

X

X

X

X

X

L

H

H

L

H

L

L

H

L

X

X

X

X

L

H

H

H

L

H

H

L

H

L

X

X

X

L

H

H

H

H

H

L

L

L

H

L

X

X

L

H

H

H

H

H

H

L

H

L

H

L

X

L

H

H

H

H

H

L

L

H

H

H

H

H

H

~ i~

H

L

L

H

H

H

L

H

3

1131

4{1'

5

121

H = high logic level. L = low logic level. X = irrelevant
Z = high-impedance state

schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC-----

TYPICAL OF OUTPUTS
------.--VCC

TYPICAL OF OUTPUTS
EO,ES
----.--VCC

Req
I NPUT_~f-+-__
OUTPUT

L.-----""'--OUTPUT

Inputs 1 thru 7: Req = 9 k.!1 NOM
All others: Req = 18 k.!1 NOM

1076
DESIGN GOAL

7-448

This page provides tentative information on a
product in the developmental stage. Texas

TEXAS INSTRUMENTS
INCORPORATED

Instruments reserves the right to change or dis· POST OFFICE BOX 5012 • DALLAS, TEXAS 75222

continue this product without notice.

TYPES SN64LS348, SN14LS348 (TIM9908)
8-LlNE-TO-3-LlNE PRIORITY ENCODERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . . .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS348
SN74 LS348
Storage temperature range

. . . . . 7V
. . . . . 7V
_55°C to 125°C
O°C to 70°C
-65°C to 150°C

NQTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS348
MIN
4.5

Supply voltage, Vee

5

AO, A1,A2

High-level output current, IOH

EO,GS
AO, A1,A2

Low-level output current, IOL

EO,GS

5.5 4.75

NOM MAX
5

UNIT

5.25

V

-1

-2.6

mA

-400

-400

iJA

12

24

mA

l3

rnA

70

°e

4

-55

Operating free-air temperature, T A

SN74LS348

NOM MAX MIN

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage
High-level

VOH

output voltage

Low-level
VOL

II
IIH

output voltage

AO, A1, A2

Short-circuit output current§

IOH =-1 rnA

VIH =2 V,

IOH = -2.6 mA

AO, A1, A2

Vee = MIN,

EO,GS

VIL = VILmax

Inputs 1 thru 7
All other inputs
Inputs 1 thru 7
All other inputs
Outputs AO, A1, A2
Outputs EO, GS

Supply current

2.4

3.1

2.5

3.4
0.25

IOL = 12mA

0.8

V

-1.5

-1.5

V

2.4

3.1

2.7

3.4

0.4
0.4

IOL =8mA

Vee= MAX,

VI =7V

Vee =MAX,

VI = 2.7 V

Vee = MAX,

0.25

IOL=4mA

VI =0.4V

Vee = MAX

V

2
0.7

IOL=24mA

VIH = 2V,

All other inputs

lOS

II = -18mA

VIL = VIL max IOH = -400jJ,A

input voltage

Low-level input current

Vee = MIN,
Vee= MIN,

EO,GS

Inputs 1 thru 7

IlL

ICC

2

Input current at maximum

High-level input cu rrent

SN54LS348
SN74LS348
UNIT
MIN TYp:j: MAX MIN TYp:j: MAX

0.25

V
0.4

0.35

0.5

0.25

0.4

0.35

0.5

0.2

0.2

0.1

0.1

40

40

20

20

-0.8

-0.8

-0.4

-0.4

-30

-130 -30

-20

-100 -20

-130
-100

Vee = MAX,

Condition 1

13

25

13

25

See Note 2

Condition 2

12

23

12

23

V

mA

•

iJ A
mA
mA
mA

NOTE 2: IcC (condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open. ICC (condition 2) is measured with all
inputs and outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
0

:j: All typical values are at V CC = 5 V, T A = 25 C.
§ Not more than one output should be shorted at a time.

1076

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
Instruments reserves the right to change or discontinue this product without notice.

TEXAS IN ST RUM ENTS
I NCORPORAT ED
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7449

TYPES SN54LS348, SN74LS348 (TIM9908)
8-UNE-TO-3-UNE PRIORITY ENCODERS WITH 3-STATE OUTPUTS
switching characteristics, VCC = 5 V, T A = 25 C
0

PARAMETER'
tpLH
tpHL
tPLH
tpHL
tPLH

FROM

TO

(INPUT)

(OUTPUT)

o thru 7

AO, A1, or A2

o thru 7

AO,A1,or A2

Othru7

WAVEFORM

EO

11

17
30

Out-of-phase

23

35

output

23

35

Out-of-phase

12

18

output
In-phase

tpHL

output

tpLH

In-phase

EI

GS

TYP MAX UNIT

20

tpLH

GS

MIN

output

tPHL
Othru7

TEST CONDITIONS

In-phase

CL = 45pF,
RL = 667

n,

See Note 3

6

15

15

23

14

21

11

17

tPHL

output

24

36

tpLH

In-phase

14

21

EI

EO

output

tPHL
tPZH

EI

AO, A1, orA2

EI

AO, Al,or A2

27

41

18

27

n

23

35

RL =667

tpLZ

25
39

CL - 5 pF,

tPZL
tpHZ

17
26

ns
ns
ns
ns
ns
ns
ns
ns

= propagation delay time, low-to-high-Ievel output
= propagation delay time, high-to-Iow-Ievel output
= output enable time to high level
tpZL = output enable time to low level
tpHZ = output disable time from high level
tpLZ = output disable time from low level

'tPLH
tpHL
tpZH

NOTE 3: Load circuits and waveforms are shown on page 3-11_

TYPICAL APPLICATION DATA

•

EO

'lS348

EI

EO

'LS348

EI

lSB

ENABLE
INPUT

STROBE
OUTPUT

FIGURE l-PRIORITV ENCODER WITH UP TO 64 INPUTS.

1076

DESIGN GOAL

7-450 This

page provides tentative information on a
product in the developmental stage, Texas
Instruments reserves the right to change or dis-

continue this product without notice.

TEXAS IN ST RU M ENTS
IN (

Of{ POR ArE D

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TTL
MSI

TYPE SN74351
DUAL DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS
BULLETIN NO. DL-S 761211

MARCH 1974 -

REVISED OCTOBER 1976

N

•

DUAL-IN-LINE PACKAGE (TOP VIEW)

DuaI8-Line-to-1-Line Multiplexer That
Can Replace Two SN54151, SN74151
Multiplexers in Some Applications

DATA INPUTS
A

•

Four Common Data Lines Permit Simultaneous
Interdigitation with Parallel-to-Serial Conversion

•

4-Bit Organization Is Easily Adapted to
Handle Binary or BCD

•

Three-State Outputs Can Be Connected
Directly to System Bus Lines

•

Enable Input Controls Impedance Levels of the
12 Data Inputs and Two Outputs
GND

ABC

'-y---/

description

SELECT INPUTS

DATA INPUTS

logic: see function table

The SN74351 comprises two 8-line-to-l-line data
selectors/multiplexers with full decoding on one
monolithic chip. Symmetiically sVvitching, complementary decode generators minimize decoder skew
during changes at the select inputs and ensure that
potentially erroneous effects are minimized at the
data outputs. Four data inputs are exclusive to each
multiplexer and four are common to both_ A
common enable input is provided which, when high,
causes both outputs to assume the high-impedance
(off) state and simultaneously diverts the majority of
the input current, which reduces the load significantly on the data input drivers. A low logic level at
the enable input activates both outputs so that each
will assume the complement of the level of the
selected input.

functional block diagram

j

::-=-:---H±±±--r--..

103 (9 )

DATA

INPUTS

:l: :

--.,.----;!;±±±:!::±::r-.....

0""",',4,,-'

07(11)

~~G~~ {: , : , :
c

t--Vee

Vee
20 kn NOM
INPUT

--

......
_IW

~~

OUTPUT

.... '

~,

n'T

1076

7-458

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS353, SN14LS353
DUAL 4-UNE-TO-1-UNE DATA SELECTORS/
MULTIPLEXERS WITH 3-STATE OUTPUTS
recommended operating conditions
SN54LS353
MIN
4.5

Supply voltage, VCC

SN74LS353

NOM MAX
5

MIN

5.5 4.75
-1

High-level output current, 10H
Low-level output current, 10L

NOM MAX
5

V

-2.6

mA

4
-55

Operating free-air temperature, T A

125

UNIT

5.25

0

8

mA

70

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL
VIK

Low-level input voltage
I nput clamp voltage

VOH

High-ievei output voitage

VOL

Low-level output voltage

I~·u£.

SN54LS353

TEST CONDITIONSt

PARAMETER

MIN

SN74LS353

TYP+ MAX

2
VCC= MIN,

II = -18 mA

VCC = MIN,

VIH=2V,

2.4

VIL = VIL max, 10H = MAX
VCC= MIN,
\ / .•

_

\ / ••

VIH=2V,

10L = 4 mA
'UL.- v

Vee

state) output current
Input current at

= ~.4.6,X,

VIH

=2 V

TYP+ MAX

2

V

0.8

V

-1.5

-1.5

V

3.4
0.25

UNIT

0.7

2.4
0.4

V

3.1
0.25

1 ___ 0_1\

'-""1

VIL- VIL"'Oro.

Off-State (high-impedance

MIN

n ':Ie:

III'"

0.4

V

V.V

Vo = 2.7 V

20

20

Vo = 0.4 V

-20

-20

;.:.A

Vee= MAX,

VI = 7 V

0.1

0.1

IIH

High-level input current

VCC = MAX,

VI=2.7V

20

20

!J.A

IlL

Low-level input current

VCC = MAX,

VI = 0.4 V

-0.4

-0.4

mA

lOS

Short-circuit output current §

Vce = MAX

-130

mA

lec

Supply current

VCC = MAX,

II

maximum input voltage

-130 -30

-30
See Note 2

Condition A

7

12

7

12

Condition B

8.5

14

8.5

14

mA

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli tvpical values are at V CC = 5 V, T A = 25° C.
§Not more than one output should be shorted at a time, and duration of the short-<:ircuit should not exceed one second.
NOTE 2: ICC is measured with the outputs open under the following conditions:

I

A. All inputs grounded.
B. Output control at 4.5 V, all inputs grounded.

switching characteristics, Vee
PARAMETER~

tpLH

= 5 V, TA = 25°e

FROM

TO

(INPUT)

(OUTPUT)

Data

Y

TEST CONDITIONS

tpHL
tPLH

Select

tpHL
tpZH

Output

tpZL

Control

tpHZ

Output

tpLZ

Control

CL=15pF,

y

RL=2kSl,

See Note 3

y
CL=5pF,

Y

RL = 2 kn,

See Note 3

MIN

TYP

MAX UNIT

11

25

13

20

20

45

21

32

11

23

15

23

27

41

12

27

ns
ns
ns
ns

~ tp LH == Propagation delay time, low-to-high-Ievel output
tpHL == Propagation delay time, high-to-Iow-Ievel output
tPZH== Output enable time to high level
tpZL == Output enable time to low level
tpHZ == Output disable time from high level
tpLZ == Output disable time from low level
NOTE 3: Load circuit and waveforms are shown on page 3-11.

1076

TEXAS I'CORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXA.S 75222

7-459

TTL
MSI

TYPE SN74LS362 (TIM9904)
FOUR-PHASE CLOCK GENERATOR/DRIVER
BULLETIN NO. DL-S 7612476, OCTOBER 1976

•

Clock Generator/Driver for The
TMS 9900 or Other Microprocessors

•

High-Level 4-Phase Outputs

•

Complementary TTL 4-Phase Outputs

•

Self-Contained Oscillator Can be
Crystal or Capacitor Controlled

SN74LS362 •.• J OR N PACKAGE
(TOP VIEW)

osc osc

•

External Oscillator Can Be Used

•

Clocked D-Type Flip-Flop With
Schmitt-Trigger Input For Reset
Signal Synchronization

IN

OUT

IN

OUT

;P2

;\1

TTL

TTL

Voo

,,1

<1>2

TANK 1

description

TANK TANK GNO

2

<1>2

1

FFQ

FFO

1>3

TTL

TTL

<1>4

GNO

2

The 'LS362 consists of an oscillator, divide-by-four counter, a second divide-by·four counter with gating to generate
four clock phases, high-level (12-volt) output drivers, low-level (5-volt) complementary output drivers, and a Ootype
flip-flop controlled by an external signal and the cp3 clock. The four high-level clock phases provide clock inputs to a
TMS 9900 microprocessor. The four complementary TTL-level clocks can be used to time memory or other logic
functions in a TMS 9900 computer system. The Ootype flip-flop can be used to provide (for example) a reset signal to a
TMS 9900, timed by cp3, on receipt of an input to the FFO input from power turn-on or a manual switch closure. Other
applications are possible. A safety feature has been incorporated in the cp outputs such that if an open occurs in the
VCC supply common to 'LS362 and TMS 9900, the cp outputs will go low thus protecting the TMS 9900.
The frequency of the internal oscillator can be established by a quartz crystal or capacitor and LC circuit. Either a
fundamental or overtone crystal may be used. The LC circuit connected to the tank inputs selects the desired crystal
overtone or establishes the internal oscillator frequency when a capacitor is used instead of a crystal. An LC circuit
must always be used at the tank inputs when using the internal oscillator. An external oscillator can be used, if desired,
see "Applications Information" for details.

typical phase relationships of inputs and outputs (OSC is internal)

OSCIN

.-J

osc
OSCOUT~______~r-l~
¢1-'~

______~r-l~_________~r-l~______~r-l~______~r-l~______~r-l~__________~

______________________________~

¢2---.J
¢3 ______________~

~---------------------------------~

q;1 .-J

"¢2 ----,~_______J
q;3-------------------,~

______~

q;4
FFD
FFO- -

-

-

-

-

-

-

-

-

-

-I

DESIGN GOAL

7-460

This page provides tentative information on a
product in the developmental stage. Texas
Instruments reserves the right to change or discontinue thjs product without notice.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPE SN74LS362 (TIM9904)
FOUR-PHASE CLOCK GENERATOR/DRIVER
functional block diagram

TANK 1
TANK 2
XTAL1
XTAL2

(1)
(2)
(1S)

OSCILLATOR

(19)

I~

1·

OSC!N--'("-17::...:.)----~~~-----__=------y--'

(16)

~
- - - - OSCOUT
V

L-II
r

12..VSECTiON--,

n-_~....:-I----t1

I

I

I

(12) ¢1

I
(11)
¢2

IS)

¢3

(9) ct>4

I

(14) _
¢1TTL

(15) ~2TTL

(7)

~3TTL

(6) ~TTL
(4)

FFD

1076

FFQ

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
I nstruments reserves the right to change or dis·
continue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-461

TYPE SN14LS362 (TIM9904)
FOUR-PHASE CLOCK GENERATOR/DRIVER
schematics of inputs and outputs
EQUIVALENT OF D INPUT

EQUIVALENT OF XTAL 1 AND
XTAL 2 INPUTS

EQUIVALENT OF OSCIN INPUT

Vee

Vee---.--20 kn NOM

Vee---.---

I NPUT ---1f-:"11e-~-.INPUT

INPUT

GND 1

GNDl

EQUIVALENT OF
TANK INPUTS

GND 1

TYPICAL OF OSCOUT. Q. AND

TYPICAL OF

ALL ;-TTL OUTPUTS

q,1. 2. 3 AND c/>4 OUTPUTS

-----.--Vee
V e e - - -.....-

-4~---~-e--VDD

L-.~'--OUTPUT

----e-~~~~OUTPUT

I NPUT-.....- -..

GND1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

I

Supply voltage: Vee (see Note 1)
VDD (see Note 1)
Input voltage: OSelN . . . . .
FFO . . . . . ,
Operating free-air temperature range
Storage temperature range

. 7V
13V
5.5 V
-0.5 V to 7 V
aOe to 7aoe
-65°e to 15aoC

NOTE1: Voltage values are with respect to the network ground terminals connected together.

recommended operating conditions
I
Supply voltages
High-level output current, IOH

NOM

MAX

4.75

5

5.25

VDD
1,2,3, 4

11.4

12

12.6

V

-100
-400

1,2,3,4

4

rnA

All others

8

rnA

54

MHz

48

I nternal oscillator frequency, f osc
External oscillator pulse width, tw(oscl

25

ns

Setup time, FFD input (with respect to falling edge of 3), tsu

50

ns

0

Operating free-air temperature, T A

DESIGN GOAL

Instruments reserves the right to change or dis·

70

°e

1076

;~~~:C~gei~r~~i:e~;~~I::~~:ni;aflor:aa~!~\~~a: TEXAS IN ST RUM ENTS
continue this product without notice.

ns

-30

Hold time, F F D input (with respect to falling edge of 3), th

7-462

V

iJA
iJA

All others

Low-level output current, IOL

I UNIT

MIN

Vee

INCORPORATED
POST OFFICE BOX"S012 •

DALLAS. TEXAS 75222

TYPE SN74LS362 (TIM9904)
FOUR-PHASE CLOCK GENERATOR/DRIVER
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS

PARAMETER

MIN

High-level input voltage

VIH
Vil

low-level

FFD

input voltage

OSelN

VT+-VT-

Hysteresis

FFD

VIK

Input clamp voltage

VOH

II

'IL

lOS

Vee

ct>1, ct>2,i/>3, ct>4 Vee

~

Other outputs VDD

~

V,

output voltage

Other outputs

I nput current at

FFD

t-FD

input current

oselN

0.8

VDD -11.4 V, 11--18mA
10H

11.4 Vto 12.6 V

10H - -400~A

Vee =4.75 V,

Vee = 5.25 V,

low-level

FFD
OSelN

Short~circuit

All except

output current+

ct>1, ct>2,ct>3,ct>4

VCC

~

5.25 V,

Vee

~

5.25 V

VDD-2 VDD-1.5
2.7

VDD = 11.4 V 10l -4 mA

0.25

0.4

10l =8 mA

0.35

0.5

VDD

~

~

5.5 V

mA

mA

0.3
20

~A

60
-0.4

i2.6 V, VI = 0.4 V

mA

-3.2
-20

-100

FFD and OSelN at GND,

Outputs open

I

mA

105

175

mA

12

20

mA

VDD = 12.6 V,

FFD and OSCIN at GND,

V

0.4

0.1

VI =7 V

I

Vee = 5.25 V,

VDD

0.25

VI

V

3.4

VDD = 12.6 V, VI = 2.7 V

Vec = 5.25 V,

V
-1.5

10l =4 mA

VDD = 12.6 V

Vee = 5.25 V,

input current

~-100~A

4.75 V,

ct>1,ct>2,ct>3,ct>4

Supply current from VDD

IDD

~4.75

High-level

High-level

V

0.8

Supply current from Vce

ICC

UNIT
V

0.4

maximum input voltage OSelN

IIH

MAX
0.5

output voltage
low-level

VOL

TYP+
2

Outputs open

t All typical values are at VCC = 5 V, VDD ~ 12 V, T A = 25°C.
+ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. Outputs ct>1, ct>2, ct>3,
and ct>4 do not have short-circuit protection.

switching characteristics, TA

= 25°C, VCC1 = 5 V, VCC2 = 12 V, fosc = 48 MHz, see figure

PARAMETER

TEST CONDITIONS

MIN

1

TYP

MAX

UNIT

3

MHz

12

MHz

f out

Output frequency, any ct> or ct> TTL

f out

Output frequency, OSeOUT

tc{ct>l

eycle time, any  output

tr{ct>l

Rise time, any ct> output

10

20

ns

tf{ct>l

Fall time, any ct> output

10

20

ns

tw{ct>l

Pulse width, any ct> output high

40

1ll,ct>2H

Delay time, ct>1 low to ct>2 high

0

5

15

12l,ct>3H

Delay time, ct>2 low to ct>3 high

0

5

15

ns

13l ct>4H

Delay time, ct>3 low to ct>4 high

0

5

15

ns

tct>4l,lH

Delay time, ct>410w to ct>1 high

15

ns

tct>lH,ct>2H

Delay time, <1>1 high to <1>2 high

tct>2H, ct>3H

ns

333

Output loads:

I

ns
ns

0

5

70

83

ns

Delay time, <1>2 high to ct>3 high

ct>1,3,ct>4: 100pF toGND
ct>2: 200 pF to GND

70

83

ns

13H,ct>4H

Delay time, ct>3 high to ct>4 high

Others: Rl = 2 kU,

70

83

ns

tct>4H, ct>lH

Delay time, ct>4 high to ct>1 high

Cl = 15 pF

70

83

ns

1H,ct>Tl

Delay time, n high to ct>n TTL low

See Note 2

1l,TH

Delay time, ct>n low to ct>n TTL high

--8

ns

-19

ns

tct>3l,QH

Delay time, <1>3 low to FFQ output high

-7

ns

13l,Ql

Delay time"ct>3 low to FFQ output low

-12

ns

1l,OSOH

Delay time, ct> low to OSeOUT high

-5

ns

1H,OSOl

Delay time, FFQ high to OSeOUT low

-13

ns

NOTE 2: Use load circuit for bi-state totem-pole outputs, page 3-11.

DESIGN GOAL

1076

This page provides tentative information on a

product

in the developmental stage, Texas

Instruments reserves the right to change or dis-

continue this product without notice.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-463

-

.....

J::,.

CD

-'='"
~

t~

I"- t l/>1H,1/>2H--IIi
1/>1

9.4V

9.4 V

~

~
9.4 V

1

1/>3

1

1\.4
V

1

I

I.I

II

1

trp3L,4H

I

~

[TI

><

);(J)

q>1

z_

I
I

U

trpH,I/>TL~

8z
~C/J

.2

0-1

~iC

,.

3V

J

~

q>3

[TI

z

Q>4

\

I~

I

I

II

I1

II

J

I

:.

I

1

I

II

II

I

I

I

II

I

1

YDC

;0.7 V

1

U

~tl/>L,I/>TH:

:I
I

t,/,L
'I'

IL

."

»
JJ
»
s:
m
-I
m

I

I

I

I

I

II

FIGUFtE 1-SWITCHING CHARACTERISTICS. VOLTAGE WAVEFORMS

\

r

L-.J

meD
zeD

mc::::t
::a~

m

JJ

........

2:
-I

-<

Z

::a

."

I

=-=~

C')i:

~

s:m

UJi

I

n-

:......
e

c:

{\~

FFQ
OUTPUT

oo,J

-\:l=-.;;.;0.~7..:.V_ _ _ __

trpH,~SOL-.I!.-:

OSOH~
"1

,T"

FFD
INPUT

m

I

W

\.--+1I

{\

m~

s:
m

:

{\

cn~

JJ

UUV i

U·

:. .....

nW
r-crt
eN

I,--_ _•...-llf--_ _ _ _ _ _ _ _ _ _ _ _ _......,

\

-acn

=z

_____________

I 0.7 V

~94V
I1
.

I

-I
C/J

I

I

~c:

03::

0.7 V

J

II

I+- t I/>3H,1/>4H--+I

I
I
tI/>2L.1/>3H~
_ _ _ _ _ _ _.:..1_ _ _1:-,;;0.,;.;.7_V;..."

1/>4

C~

::am

~---------------~-:-trp4L,1/>1H
!K9.4V

I
II

:

1I

trp1L,1/>2H
I
____~~J

-

0.7 V

I

.....

e-<

:..pr:4V\

:

0.7 V I4-twl/>
0.7 V i i
trl/>-tojt+
-a./l4-tfl/> r4-trp2H,1/>3H-II>I
I

1/>2

."
~

I4-- t I/>4H,1/>1H4t

o
JJ
s:
~

o2:

::a
c.
::a

m

TYPE SN74LS362 (TIM9904)
FOUR-PHASE CLOCK GENERATOR/DRIVER
APPLICATION INFORMATION
Figure 2 shows the 'LS362 connected to a TMS9900. The oscillator is shown operating with a quartz crystal and an
LC circuit connected to the tank terminals.
For operation of the TMS 9900 microprocessor at 3 MHz, the frequency reference will need a resonant frequency of
48 MHz (16 x 3 MHz). A quartz crystal used as a frequency reference should be made for series-mode operation with a
resistance in the 20~ to 75-ohm range and be capable of a minimum of 2 mW power dissipation. Typical frequency
tolerance is ±O.005%. For 48·MHz o"peration a third-overtone crystal is used. The inductance L connected across the
tank terminals should be 0.47 pH ± 10%, and the capacitance C (including board capacity) should be 22 pF ± 5%. The
LC circuit should be tuned to the third·overtone crystal frequency for best results. A 0.1-pF capacitor can be substituted for the quartz crystal. With a capacitor rather than a crystal, the LC tuned circuit establishes the operating
frequenCies. LC component values for operation at any frequency can be computed from fosc = 1/(2tryLC) where
fosc is the oscillator frequency, L is the inductance value in henries, and C is the capacitance value in farads.
When the internal oscillator is being used, OSCIN should be connected to VCC through a resistor (1 kSl nominal) and
an LC tank circuit must be connected to the tank inputs. An external oscillator can be uSed by connecting it to OSCIN

and disabling the internal oscillator by connecting the crystal terminals to VCC and leaving the tank inputs open. An
external oscillator must have a frequency four times the desired output clock frequency and a 25% duty cycle. See
Figure 3.
The first iow-ievei externai dock puise wiii preset the divide-by-four counter, allowing the external oscillator signal to
directly drive the phase generator. Figure 3 is a timing diagram illustrating operation with an external oscillator.
Resistors between <1>1, <1>2, <1>3, and <1>4 outputs of the 'LS362 and the corresponding clock input terminals of the TMS
9900 should be in the 10- to 20-ohm range (See Figure 2). Their purpose is to minimize overshoot and undershoot.
The required resistance value"is dependent on circuit layout. Clock signal interconnectionsshould be as short as possible.
The D-type flip-flop associated with pins FFD and FFQ can be used to provide a power-on reset and a manual reset to
the TMS 9900 as shown in Figure 4. A Schmitt-trigger circuit" driving the D input generates a fast-rising waveform when
the input voltage rises to a specific value. At power turn-on, voltage across the 0.1 pF capacitor in Figure 4 will rise
towards VCC. This circuit provides a delay that resets the TMS 9900 after VCC has stabilized. An optional manual
reset switch can be connected to the delay circuit for resetting the TMS 9900 at any time. The TMS 9900 HOLD
signal could alternately be actuated by FFD.
The ground terminals GND1 and GND2 shoulq be connected together and to system ground.

XTAL1
QUARTZ
CRYST AL

c:::J

XT AL 2
TANK 1

TANK2

'LS362
(TIM9904)
CLOCK
DRIVER

¢1

R

<1>2

R

¢2

q,3

R

q,3

4

R

q,4

I

<1>1

TMS 9900
MICROPROCESSOR

+5 V +12 V
FIGURE 2-'LS362 CRYSTAL-CONTROLLED OPERATION

1076

TEXAS II'oCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

1-465

TYPE SN14LS362 (TIM9904)
FOUR-PHASE CLOCK GEN'ERATOR/ORIVER
APPLICATION INFORMATION

OSCIN

q,2 _ _ _ _..J~

......_ _ _ _ _ _ _ _

~r

q,3-------------------------------------------J~~_________________________

q,4----------------------------------J~~____________________________
FIGURE 3-EXTERNAL OSCILLATOR TIMING

I
VCC

'LS362
(TIM9904)
TMS 9900
MICROPROCESSOR

10kn
100.n

D

Q

FFQ

1----+---=-1
RESET

OPTIONAL
MANUAL RESET
SWITCH
FIGURE 4-POWER-ON RESET

1076

7-466

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS363, SN54LS364, SN74LS363, SN74LS364
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS

TTL
MSI

BULLETI N NO. DL-S 7612466, OCTOBER 1976

•

High VOH ... 3.65 V Min ( 74LS')

•

Choice of 8 Latches or 8 D-Type Flip-Flops
I n a Single Package

•

3-State Bus-Driving Outputs

•

Full Parallel-Access for Loading and Reloading

•

Buffered Control Inputs

•

Clock/Enable Input Has Hysteresis to Improve
Noise Rejection and P-N-P Inputs To Reduce
D-C Loading

•

SN54LS373/SN74LS373 and SN54LS374/
SN74LS374 Are Similar But Have Standard
V OH of 2.4 V Min

SN54LS363 ... J PACKAGE
SN74LS363 ..• J OR N PACKAGE
(TOP VIEW)

OUTPUT
CONTROL

logic: see function table
'LS363
FUNCTION TABLE

I

OUTPUT

ENABL.E

CONTROL

G

L
L

D

OUTPUT

H

H

H

H

L

L

L

L

X

00

H

X

X

Z

. _.

SN54LS364 •.• J PACKAGE
SN74LS364 .•• J OR N PACKAGE
(TOP VIEW)
Vee

'LS364
FUNCTION TABLE

I

I
CLOCK

D

OUTPUT

L

t

H

H

L

t

L

L

L

L

X

00

H

X

X

Z

CONTROL

I

See explanation of function tables on page 3--8.

logic: see function table

description
These 8-bit registers feature totem-pole three-state outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these
registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without
need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the 'LS363 are transparent D-type latches meaning that while the enable (G) is high the Q outputs
will follow the data (D) inputs. When the enable is taken low the outputs will be latched at the level of the data that
was setup.
The eight flip-flops of the 'LS364 are edge-triggered D-type flip-flops. On the positive transition of the clock the Q
output will be set to the logic state that was setup at the D input. The 'LS363 is particularly useful for interfacing to
MaS logic where a higher than normal VOH level is desirable such as that required by the TMS 8080A microprocessor.
Schmitt-trigger buffered inputs at the enable (,LS363) and clock (,LS364) lines simplify system design as ac and dc
noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output control input can be
used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the
high-impedance state the outputs neither load nor drive the bus line significantly.

1076

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
I nstruments reserves the right to change or d iscontinue this product without notice.

TEXAS INS T RUM EN T S
INCORPORATED
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-467

TYPES SN54LS363, SN54LS364, SN74LS363, SN74LS364
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
functional block diagram
Same as SN54LS373/SN74LS373 and SN54LS374/SN74LS374

o
- a o

schematics of inputs and outputs
EQUIVALENT OF DATA AND
OUTPUT CONTROL INPUTS

'LS363
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF ENABLE INPUT

VCC

V C C - - -......- -

Req

INPUT

--

INPUT

Data: Req = 20 k!1 NOM
Output control: Req = 18 k!1 NOM

EQUIVALENT OF
DATA INPUTS
VCC

--

EQUIVALENT OF
CLOCK INPUT

TYPICAL OF ALL OUTPUTS

V C C - - -......- -

vcc

30 k!1 NOM

INPUT

'LS364

EQUIVALENT OF OUTPUT
CONTROL INPUT

18 k!1 NOM
--

INPUT

INPUT

OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

I

Supply voltage, Vee (see Note 1)
Input voltage
Off-state output voltage
Operating free-air temperature range: SN54LS'
SN74LS'
Storage temperature range

7V
7V
7V

_55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground tarminal.

recommended operating conditions
: -_ _ _S_N_5_4L_S_'_ _ _t -_ _ _S_N_7_4_LS_'_ _ _--1' UNIT
Supply voltage, VCC

MIN

NOM

MAX

4.5

5

5.5

I

MIN

NOM

MAX

4.75

5

5.25

High-lell9l output voltage, VOH

5.5

5.5

High·level output current, IOH

-1

-2.6

Width of clock/enable pulse, tw
Data setup time,

tsu

Data hold time, th

High

15

15

Low

15

15

'LS363

O.j,

O.j,

'LS364

20t

20t

'LS363
'LS364

10.j,

10.j,

Operating free-air temperature, T A

t.j,

Ot

The arrow indicates the transition of the clock/enable input used for reference:
tion.

t

DESIGN GOAL

7-468

This page provides tentative information on a
product in the developmental stage. Texas
Instruments reserves the right to change or discontinue this product without notice.

V
V
mA

ns
ns

0

for the low-to-high transition,

I

I

ns

Ot
125

-55

I

70

.j, for

°c

the high-to-Iow transi

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX !5012

•

DALLAS, TEXAS 75222

TYPES SN54LS363, SN54LS364, SN74LS363, SN74LS364
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITlONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

IOZH

IOZL

SN74LS'
MAX

TYP:j:

MIN

Vee = MIN,

11=-18mA

VCC = MIN,

VIH=2V,

Vee = MIN,

Off-state output current,

Vee = MAX,

high-level voltage applied

Vo = 3.65 V

Off-state output current,

Vee = MAX,

low-level voltage applied

Vo = 0.4 V
Vee = MAX,

0.25

IIOL = 12 rnA

0.8

V

-1.5

V

3.65
0.4

1ioL = 24 rnA
VIH = 2 V,

VIH=2V,

VI =7 V

UNIT
V

-1.5
3-45

VIH = 2 V,

VIL = VILmax

MAX

2
0.7

VIL = VI Lmax, IOH = MAX

maximum input voltage

TYP:j:

2

input current at
II

SN54LS'
MIN

V
0.25

0.4

0.35

0.5

V

20

20

p.A

-20

-20

p.A

0.1

0.1

rnA

IIH

High-level input current

Vee = MAX,

VI=2.7V

20

20

p.A

ilL

Low-level input current

Vee = MAX,

VI = 0.4 V

-400

-400

p.A

-i30

rfiA

70

rnA

lOS

Short·circuit output current§

Vee = MAX

lee

Supply current

Vee= MAX,

-30

-130

Output control at 4.5 V

-30

70

42

42

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, T A = 25°C_
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

TEST CONDITIONS

'LS363
MIN

'LS364

TYP MAX

f max
tPLH

35
Data

tpLH

Clock or

tpHL

enable

tPZH

Output

tPZL

Control

tPHZ

Output

tPLZ

Control

15

Any Q

tpHL

NOTES:

MIN

eL=45pF, RL=667n,
Any Q

See Notes 2 and 3

Any Q

Any Q

eL=5pF,

RL = 667 n,

See Note 3

TYP MAX

UNIT
MHz

50

23
ns

18

27

19

30

21

33

24

36

22

34

16

28

16

28

22

36

22

36

12

20

10

18

16

25

14

24

ns

•

ns

ns

2. Maximum clock frequency is tested with all outputs loaded.
3. See load circuits and waveforms on page 3-11.

f max == maximum clock frequency
tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
tpZH == output enable time to high level
tpZL == output enable time to low level
tpHZ == output disable time from high level
tpLZ == output disable time from low level

DESIGN GOAL
1076

This page provides tentative information on a
product in the developmental stage. Texas
Instruments reserves the right to change or discontinue this product without notice.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE SOX 5012 •

DALLAS. TEXAS 75222

7-469

TYPES SN54LS363, SN54LS364, SN74LS363,
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS

SN74LS3~~

TYPICAL APPLICATION DATA
IIIDIRECTIONAL BUI DflIVER
OUTPUT
CONTROL 1

~
A

10

10
20

2D

30

3D

0

BIDIRECTIONAL
DATA BUS 1

40

'LS364

I-

SO

I-

SO

70

70

~

0

BIDIRECTIONAL
DATA BUS 2

80

)

CLOCK 1

CLOCK 2

(
'--10

V

_20

CK

10 t-20 t--

-30
'---40

'LS364

30

t--

40

r----

50 t - - - - -

-SO
SO

60

70

70

80

A

80

Y

OUTPUT
CONTROL 2

CLOCK1H5Lr
::HANGEL-j
CLOCK

CLOCK 2 H

Lr

CLOCK CIRCUIT FORBUS EXCHANGE

II

EXPANDABLE

~RD4Y~IT

GENERAL REGIITER FILE

SN74LS364

G

YO

SN74LS364

Y1
ENABLE SELECT {

A

Y2

B

Y3

SN74LS364

SN74LS364

1/2 SN74LS139

Cusci
SELECT

LS

CLOCK

1076

7470

TEXAS INCORPORAfED
INSTRUMENTS
POST OFF1CE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED
FLIP-FLOPS
BULLETIN NO. DL-S 7612350, OCTOBER 1976

TTL
MSI

• Choice of 8 Latches or 8 D-Type Flip-Flops
In a Single Package
• 3-State Bus-Driving Outputs
• Full Parallel-Access for Loading
• Buffered Control Inputs '
• Clock/Enable Input Has Hysteresis to Improve
Noise Rejection
• P-N-P Inputs Reduce D-C Loading on
Data Lines ('S373 and 'S374)

SN54LS373, SN54S373 ... J PACKAGE
SN74LS373, SN74S373 ••. J OR N PACKAGE
(TOP VIEW)

• SN54LS363 and SN74LS364 Are Similar But
Have Higher V OH For MOS Interface

'LS373, 'S373
FUNCTION TABLE

logic: see function table

OUTPUT

ENABLE

CONTROL

G

L

H

L

H

L

L

L

L

X

00

H

X

X

Z

D

OUTPUT

H

H

SN54LS374, SN54S374 .•. J PACKAGE
SN74LS374, SN74S374 ••• J OR N PACKAGE
(TOP VIEW)
Vee

'LS374, 'S374
FUNCTION TABLE
OUTPUT

CLOCK

D

OUTPUT

t
t

H

H

L

L

L

L

L

X

00

H

X

X

Z

CONTROL

L

OUTPUT

•

10

CONTROL

logic: see function table

See explanation of function tables on page 3-8.

description
These 8-bit registers feature totem-pole three-state outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these
registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without
need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the 'L8373 and '8373 are transparent O-type latches meaning that while the enable (G) is high the
Q outputs will follow the data (0) inputs. When the enable is taken low the output will be latched at the level of the
data that was setup.

1076

TENTATIVE DATA SHEET
This document provides tentative information
on a new product, Texas Instruments reserves
the righ.t to change ~ecificatio.ns for this
product'" any manner Without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-471

TYPES SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
description (continued)
The eight flip-flops of the 'LS374 and '5374 are edge-triggered D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the logic states that were setup at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines simplify system design as ac and dc noise rejection is improved
by typically 400 mV due to the input hysteresis. A buffered output control input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state
the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be
retained or new data can be entered even while the outputs are off.

'LS374, 'S374
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

'LS373, 'S373
TRANSPARENT LATCHES

OUTPUT _(_1_)______~~
CONTROL

10

(3)

20

(4)

(1_)______~n
OUTPUT __
CONTROL

(7)

3D ---'-----1----1

•

3D

(8)

40

-------+----4

50

-------+----4

-------+----4

40 - - - - - 1 - - - 1

(13)

50

-----I--~

50
(14)

60 --------1---1

60

-----I--~

60

60

(17)

70

--------1----4

70

-------~-

70
80

70

(18)

CLOCK

1076

7-472

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS373, SN54LS374, SN74LS373, SN74LS374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS

o

schematic of inputs and outputs
EQUIVALENT OF DATA AND
OUTPUT CONTROL INPUTS

vcc

'LS373
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF ENABLE INPUT

- - - -......--Vcc
Vcc---......- -

Req

INPUT

-INPUT

Data: Req = 20 kn NOM
Output control: Req = 18 kn NOM
'LS374
EQUIVALENT OF
CLOCK INPUT

EQUIVALENT OF OUTPUT
CONTROL INPUT

EQUIVALENT OF
DATA INPUTS

TYPICAL OF ALL OUTPUTS
- - - -......--VCC

w--

VCC~NOM
,NPUT

absoiute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, vee (see Note 1)
Input voltage
Off-state output voltage
Operating free-air temperature range: SN54LS'
SN74LS'
Storage temperature range

7V
7V

.7V
_55°C to 125°C
aOe to 7aoe
_65°C to 15aoe

NOTE 1: Voltage values are with raspect to network ground terminal.

•

recommended operating conditions
SN74LS'

SN54LS'
Supply voltage, VCC

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

High-level output voltage, VOH

5.5

5.5

High-level output current, IOH

-1

-2.6

Width of clock/enable pulse,
Data setup time,

tw

tsu

Data hold time, th

High

15

15

Low
'LS373

1.5
O.j.

15

'LS374

20t
10.j.

20t
10.j.

'LS373
'LS374

Operating free-air temperature, T A

I

Ot
--55

Ot
0

V
V
rnA
ns

O.j.

125

UNIT

ns
ns
70

°c

t.j. The arrow indicates the transition of the clock/enable input used for reference: t for the low-to-high transition, .j. for the high-to-Iow transition.
1076

DESIGN GOAL
This page provides tentative information on a
product in the developmental stage. Texas
Instruments reserves the right to change or discontinue this product without notice.

TEXAS ',",CORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-473

TYPES SN54LS373. SN54LS374. SN74LS373. SN74LS374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

10ZH
10ZL

SN54LS'

TEST CONDITIONSt

MIN

TYP:j:

SN74LS'
MAX

MIN

2

I

Vee; MIN,

11;-18mA

Vce - MIN,

VIH - 2 V,

Vil ;VILmax,IOH; MAX
Vce; MIN,

VIH;2V,

VIL; VILmax

Off-state output current,

Vee; MAX,

high-level voltage applied

VO;2.7V

Off-state output current,

Vee; MAX,

low-level voltage applied

Va; 0.4 V

Input current at

I

2.4

MAX
0.8

-1.5

-1.5
2.4

3.4

0.4

I10l; 24 mA
VIH;2V,

V
V
V

3.1

0.25

0.4

0.35

0.5

V

20

20

p.A

-20

-20

p.A
mA

I

VIH; 2 V,

UNIT
V

0_7

0.25

I10l; 12 mA

TYP:j:

2

Vee; MAX,

VI; 7 V

0.1

0.1

IIH

High-level input current

Vee ;MAX,

VI; 2.7 V

20

20

p.A

IlL

Low-level input current

Vce; MAX,

VI; 0.4 V

-0.4

-0.4

lOS

Short-circuit output current§

Vee; MAX

mA
mA

ICC

Supply current

II

maximum input voltage

-30

-130

-30

-130

Vec; MAX,

!'lS373

24

40

24

40

Output control at 4.5 V

I'LS374

27

45

27

45

mA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC ; 5 V, T A; 25°C.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, Vee

•

PARAMETER

= 5 V, TA = 25° C

FROM
ItNPUT)

TO
(OUTPUT)

TEST CONDITIONS

'LS373

'LS374

MIN TYP MAX

MIN TYP MAX
35
50

f max

tpLH
tpHl

I

Data

tPlH

Clock or

lPHL

enable

tpZH

Output

tPZL

Control

tpHZ

Output

tPLZ

Control

NOTES:

10

Any Q
el ;45 pF, RL; 667
Any Q

n,

See Notes 2 and 3

Any Q
Any Q

el;5pF,

RL; 667

See Note 3

n,

18

UNIT
MHz
ns

18

27

14

25

16

28

24

36

22

34

16

28[

16

28

22

36

22

12

20

10

18

16

25

14

24

36

ns

!

ns
ns

2. Maximum clock frequency is tested with all outputs loaded.
3. See load circuits and waveforms on page 3-11.

f max == maximum clock frequency
tpLH == propagation delay time, low-to-high-Ievel output
tpH L == propagation delay time, high-to-Iow-Ievel output
tpZH == output enable time to high level
tpZL == output enable time to low level
tpHZ == output disable time from high level
tpLZ == output disable time from low level

1076

DESIGN GOAL

7-474

This page provides tentative information on a
product in the developmental stage. Texas
I nstruments reserves the right to change or discontinue this product without notice.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54S373, SN54S374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED fLIP-fLOPS
schematic of inputs and outputs

EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

------------~-----Vee

50n
NOM

Vee--------------~------

2.8 kn
NOM

INPUT

---41-....- . .

OUTPUT

II

m

f V

~- - - - - - - - - - - - - - - ~I ~ ~ ~ ~
_________-___ __

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
5.5 V
5.5 V
-55°e to 125°e
aOe to 7aoe
-65°e to 15aoe

Supply voltage, Vee (see Note 1)
Input voltage
Off-state output voltage
Operating free-air temperature range: SN54S'
SN74S'
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.

•

recommended operating conditions
SN74S'

SN54S'
Supply voltage, Vee

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

High-level output voltage, VOH

5.5

5.5

High-level output current, IOH

-2

-6.5

Width of clock/enable pulse, tw
Data setup time,

tsu

Data hold time, th

High
Low
'S373
'S374
'S373
'S374

Operating free-air temperature, T A

6
7.3
O.j,

O.j,

5t
10.j,

51'
10.j,

21'
-55

2t
0

1'.j, The arrow indicates the transition of the clock/enable input used for reference:
tion.

1076

TENTATIVE DATA
This page provides tentative information on a
new product. Texas Instruments reserves the
right to change specifications for this product
in any manner without notice.

6
7.3

125

l' for

V
V
rnA
ns
ns
ns

70

°e

the low-to-high transition, .j, for the high-to-Iow transi-

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

UNIT

DALLAS, TEXAS 75222

7-475

TYPES SN54S373, SN54S374, SN74S373, SN74S374
O-C-TAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED fLIP-fLOPS
electrical

character~stics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

IOZH

TEST CONDITIONSt

TYpt

MIN

MAX

UNIT

2

I SN54S'
I SN74S'

V

VCC= MIN,

1,=-18mA

VCC= MIN,

VIH=2V,

2.4

3.4

VIL = 0.8 V,

IOH = MAX

2.4

3.1

VCC= MIN,

VIH=2V,

VIL = 0.8 V,

IOL = 20mA

Off-state output current,

VCC = MAX,

VIH=2V,

high-level voltage applied

VO= 2.4 V

0.8

V

-1.2

V
V

0.5

V

50

IlA

Off-state output current,

VCC= MAX,

low-level voltage applied

Vo =0.5 V

II

Input current at maximum input voltage

VCC= MAX,

VI=5.5V

IIH

High-level input current

VCC = MAX,

VI = 2.7 V

50

IlA

IlL

Low-level input current

VCC= MAX,

VI =0.5V

-250

IlA

-100

mA

IOZL

lOS

Short-circuit output current!l

VCC= MAX

ICC

Supply current

VCC= MAX

VIH=2V,

-40

I
I

-50

IlA

1

mA

'S373

105

160

'S374

90

140

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, Vee == 5 V, T A = 25°e
FROM

PARAMETER

(INPUT)

TO
(OUTPUT)

I

'5373

TEST CONDITIONS

I

f max

•

tpLH

Data

tpHL
tpLH

Clock or

tpHL

enable

tpZH

Output

tP2;L-

Control

tpHZ

Output

tpLZ

Control

NOTES:

AnyQ
CL=15pF, RL=280n,
Any Q

See Notes 2 and 4

Any Q
Any Q

CL = 5 pF,

'5374

MIN TYP MAX IMIN TYP MAX

RL = 280 n,

See Note 3

75

100

MHz

5

9;

9

13 i

7

14 i

8
11
8

15 ,

11

18 I

12

18

8

15

i
I

11

18

I

6
8

91
12

1

UNIT

ns
15
17

5

9

7

12

ns
ns
ns

2. Maximum clock frequency is tested with all outputs loaded.
4. See load circuits and waveforms on page 3·10.

f max "" maximum clock frequency
tpLH "'" propagation delay time, low-to-high-Ievel output
tpHL

== propagation delay

time, high-to-Iow-Ievel output

tpZH "'" output enable time to high level
tpZL == output enable time to low level
tpHZ == output disable time from high level
tpLZ "'" output disable time from low level

TENTATIVE DATA

7-476

This page provides tentative information on a
new product. Texas Instruments reserves the
right to change specifications for this product
. in any manner without notice.

1076

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TYPES SN54LS374, SN54S374, SN74LS374, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND
EDGE-TRIGGERED FLIP-FLOPS
TYPICAL APPLICATION DATA
BIDIRECTIONAL lUI DRIVER

OUTPUT
CONTROL 1

A
A

1D

10
2Q

2D

3Q

3D

-

BIDIRECTIONAL
DATA flUS 1

'LS374
OR

r-

'S374

70

7D

5'{

i

(

\(

10

H

80

)

CLOCK 1

CLOCK 1

=c?-

BIOI RECTIONAL
OATABUS2

ISO

10

1-

lUI

40

10

CLOCK 2

1

'----J

EXCHANGELr

CLOCK
CLOCK 2

H

--L-,J-

I
L-...J

--,

CLOCK CIRCUIT FOR lUI EXCHANGE

EXPANDABLE

~RD"Y""IT

GENERAL REGIITER FILE

•

1/2 SN74LSl39
OR SN74S139

G

YO

A

Y2

B

Y3

Y1

ENABLE SELECT {

1/2 SN74LSl39
OR SN74S139

~
SELECT

L..S

CLOCK

1076

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INSTRUMENTS
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•

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7477

TTL
MSI

TYPES SN54LS375, SN74LS375
4-BIT BISTABLE LATCHES
BULLETIN NO. DL-S 7612131, OCTOBER 1976

•

Supply Voltage and Ground on Corner
Pins To Simplify P-C Board Layout
logic

SN54LS375 ••• J OR W PACKAGE
SN74LS375 •.. J OR N PACKAGE
(TOP VIEW)

FUNCTION TABLE
(EACH LATCH)
INPUTS OUTPUTS
0
G
Q
Q

L
H

X

H
H
L

L
H

H

Co

00

vce

40

10

10

40

ENABLE
3-4

30

ENABLE
1·2

20

2Q

3D

L

H = high level, L = low level, X = irrelevant
00 = the level of a before the high-to-Iow transition of G.

functional block diagram (each latch)

Dm~ ~

mo,","
LATCH

10

ENABLE

20

GNO

logic: see function table

description
The SN54lS375 and SN74LS375 bistable latches are
electrically and functionally identical to the
SN54lS75 and SN74lS75, respectively. Only the schematics of inputs and outputs
arrangement of the terminals has been changed in the
EQUIVALENT OF
SN54lS375 and SN74lS375.
EACH INPUT
TYPICAL OF ALL OUTPUTS

r------------.

•

These latches are ideally suited for use as temporary
storage for binary information between processing
units and input/output or indicator units. Information present at a data (D) input is transferred to the Q
output when the enable (G) is high and the Q output
will follow the data input as long as the enable
remains high. When the enable goes low, the information (that was present at the data input at the time
the transition occurred) is retained at the Q output
until the enable goes high.

Vee

INPUT

~

q
IRe

--

"

~~

~

U

111

These circu,its are completely compatible with all
popular TIL or DTl families. All inputs are diode·
clamped to minimize transmission-line effects and
simplify system design. The SN54lS375 is character·
ized for operation over the full military temperature
range of -55°C to 125°C; SN74LS375 is characterized for operation from 0° C to 70° C.

Data: Req
Enable: Req

= 17 kn
= 4.2 kn

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1) . . . . . . .
Input voltage . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS375
SN74lS375
Storage temperature range

7V
7V

-55°C to 125°C
. O°C to 70°C
-65°C to 150°C

NOTE1: Voltage values are with respect to network ground terminal.

recommended operating conditions, electrical characteristics, and switching characteristics
Same as SN54LS75 and SN74LS75, see page 7-39.
1076

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TTL

TYPES SN54376. SN74376
QUADRUPLE J-K FLIP-FLOPS

MSI

BULLETIN NO. DL-S 7612461, OCTOBER 1976

•

Four J-j( Flip-Flops in a Single Package ...
Can Reduce FF Package Count by 50%

•

Common Positive-Edge-Triggered Clocks
with Hysteresis ... Typically 200 mV

•

Fully Buffered Outputs

•

Typical Clock Input Frequency ... 45 MHz

SN54376 .•. J OR W PACKAGE
SN74376 ... J OR N PACKAGE
(TOP VIEW)

Vcc

4J

4K

4Q

3Q

CLEAR

1J

11<:

1Q

2Q

3K

3J

CLOCK

2J

GND

description
These quadrup!e TTL J-j( flip-f!ops incorporate a
. '~umber of third-generation IC features that can
simpltfy system design and reduce flip-flop package
count by as much as 50"k. They feature hysteresis at
the clock input, fully buffered outputs, and direct
clear capability. The positive-edge-triggered SN54376
and SN74376 are directly compatible with most
Series 54/74 MSI registers.

logic: see function table

schematics of inputs and outputs

The SN54376 is characterized for operation over the
full military temperature range of -55°C to 125°C;
the SN74376 is characterized for operation from O°C
to 70°C.

EQUIVALENT OF
EACH INPUT

TYPICAL OF ALL
OUTPUTS

VCC--....- - -

FUNCTION TABLE (EACH FLIP-FLOP)
COMMON INPUTS

INPUTS

CLEAR

CLOCK

J

K

•

Q

OUTPUT
Q

L

X

X

X

L

H

t

L

H

H

t

H

H

Qo
H

H

L

L

L

H

t
t

H

L

TOGGLE

H

L

X

X

QO

Clear, J, K: Req: 4 kn NOM
Clock: Req: 11.6 kn NOM

See explanation of function tables on page 3-8.

Resistor values shown are nominal and in ohms

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vec (see Note 1)
.... .
Input voltage . . . . . . . . . . . . .
Operating free-air temperature range: . SN54376
SN74376
Storage temperature range

. .... 7 V

. . . . 5.5 V
-55°C to 125°e
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

1076

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•

DALLAS. TEXAS 75222

7-479

TYPES SN54376, SN74376
QUADRUPLE J-K FLIP-FLOPS
recommended operating conditions
SN54376
NOM

MIN
4.5

Supply voltage, Vee

5

High-level output current, 10H
Low-level output current, 10L
Clock frequency
Pulse width, tw

0
22
12
12

Clock high
Clock low
Preset or clear low
J, K inputs

Input hold time, lh

Ot
lOt
20t

Operating free-air temperature, T A

55

Setup time, 1:su

Clear inactive state

SN74376
MAX
5.5
-SOO
16
30

MIN
4.75

NOM

UNIT

MAX
5.25
-SOO
16
30

5

0

V
p.A
mA
MHz

22
12
12

ns

Ot
lOt
125

t.j, The arrow indicates the edge of the clock pulse used for reference: t for the rising edge,

.j.

ns

20t
0

I

ns
°e

70

for the falling edge.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

•

VIH
VIL
VIK

PARAMETER
High-level input voltage
Low-level input voltage
Input clamp voltage

VOH

High-level output voltage

TEST CONDITIONSt

TYP;

MAX

UNIT
V
V
V

2

VOL

Low-level output voltage

II

Input current at maximum input voltage
High-level input current
Low-level input current
Short-i:ircuit output current!?
Supply current

IIH
IlL
lOS
ICC

MIN

Vee; MIN,
Vee; MIN,
VIL; O.S V,
Vee; MIN,
VIL; O.S V,
Vee; MAX,
Vee = MAX,
Vee - MAX,
Vee = MAX
Vee = MAX

11;-12mA
VIH;2 V,
10H ;-Soop.A
VIH; 2 V,

O.S
-1.5
2.4

V

3.4
0.2

IOL=16mA
VI; 5.5 V

V

0.4

mA
p.A

1

VI = 2.4 V
VI; 0.4 V

40
-1.6
-S5
74

-30
52

mA
mA
mA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
;AII typical values are at Vee = 5 V, T A = 25°e.

§Not more than one output should be shorted at

switching characteristics, Vee

8

time.

= 5 V, TA = 25°e

PARAMETER
fmax
tpHL
tpLH
tpHL

TEST CONDITIONS

Maximum clock frequency
Propagation delay time, high-to-Iow-Ievel output from clear·
Propagation delay time, low-to-hi!tl-Ievel output from clock
Propagation delay time, high-to-low-level output from clock

eL;15pF,
RL = 400n,
See Note 2

MIN

TVP

30

45
17
22
24

MAX
30
35
35

UNIT
MHz
ns
ns
ns

NOTE 2: Load circuit and voltage waveforms are sh own on page 3'10.

1076

7-480

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS377, SN54LS378, SN54LS379,
SN74LS377, SN74LS378, SN74LS379
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE
BULLETIN NO. DL-S 7612474, OCTOBER 1976

•

'LS377 and 'LS378 Contain Eight and
Six Flip-Flops, Respectively, with SingleRail Outputs

•

'LS379 Contains Four Flip-Flops with
Double-Rail Outputs

•

Individual Data Input to Each Flip-Flop

•

Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators

description

SN54LS377 •.• J PACKAGE
SN74LS377 ... J OR N PACKAGE
(TOP VIEW)
80

8D

7D

70

6Q

6D

SD

sa

CLDCK

ENABLE 10

1D

2D

20

30

3D

4D

40

GND

G

These monolithic, positive-edge-triggered flip-flops
utilize TTL circuitry to implement D-type flip-flop
logic with an enable input. The 'LS377, 'LS378, and
'LS379 devices are similar to 'LS273, 'LS174, and
'LS175, respectively, but feature a common enable
instead of a common clear.

logic: see function table
SN54LS378 ... J OR W PACKAGE
SN74LS378 ... J OR N PACKAGE
(TOP VIEW)
Vee

6Q

6D

50

sa

4D

40

CLOCK

ENABLE

10

1D

2D

20

3D

30

GND

Information at the D inputs meeting the setup time
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse if the enable
input G is low. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When the
clock input is at either the high or low level, the D
input signal has no effect at the output. The circuits
are designed to prevent false clocking by transitions
at the G input.
These flip-flops are guaranteed to respond to clock
frequencies ranging from 0 to 30 MHz while
maximum clock frequency is typically 40 megahertz.
Typical power dissipation is 10 milliwatts per
flip-flop.

•

G

logic: see function table
SN54LS379 •.• J OR W PACKAGE
SN74LS379 ... J OR N PACKAGE
(TOP VIEW)
vce

40

40-

4D

ENABLE

10

115

10

3D

35

30

CLOCK

FUNCTION TABLE
(EACH FLIP-FLOP)
INPUlS

OUTPUTS

a

a

G

CLOCK

DATA

H

x

X

00

00

L

H

H

L

L

t
t

L

L

H

X

L

X

00

DD

See explanation of function tables on page 3-8.

G

logic: see function table

076

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7-481

TYPES SN54LS311, SN54LS318, SN54LS319,
SN14LS311, SN14LS318, SN14LS319
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE
functional block diagram
D
CLOCK - - - - - t

D

CK

ENABLE

G

a.

Q

a.

Q

TO

7
5
3
OTHER

('LS377J
('LS378)
('LS379)
FLIP-FLOPS

--~L_~_""

('LS379
ONLY)

schematics of inputs and outputs
EQUIVALENT OF DATA
INPUT

EQUIVALENT OF CLOCK OR
ENABLE INPUT

TYPICAL OF ALL OUTPUTS
------4I~-VCC

vcc-----.....25 kO

INPUT_~---,tI....-

vcc--......- 20 kO NOM

.... NOM

I NPUT-..,........-

.......

•

' - - - + - OUTPUT

absolute maximum rating over operating free-ai-r temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
.... .
Input voltage . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS'
SN74LS'
Storage temperature range

. . . . . 7V
. . . . . 7V
· _55°C to 125°C
· . oOe to 70°C
· -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

10

7-482

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS377, SN54LS378, SN54LS379,
SN74LS377, SN74LS378, SN74LS379
OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE
recommended operating conditions
SN54LS'
Supply voltage, Vee

SN74LS'

MIN

NOM

MAX MIN

4.5

5

5.5 4.75

NOM MAX
5

-400

High-level output current, IOH

V

-400

/LA

4

Low-level output current, IOH
0

Clock frequency, fclock

Hold time, "th

0

8

mA

30

MHz

20

20

ns

Data input

20t

Enable active-state

25t

20t
25t

ns

Enable inactive-state

10t

10t

Width of clock or clear pulse, tw
Setup time, tsu

30

UNIT

5.25

5t

Data and enable

5t

-55

Operating free-air temperature, T A

125

ns

0

70

°c

t The arrow indicates that the rising edge of the clock pu Ise is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

V,H

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

f;

SN54LS'
SN74LS'
UNIT
MIN TYp:j: MAX MIN TYp:j: MAX

TEST COND!T!ONSt

PARAMETER

2

/I =-18mA

Vee = MIN
Vec- MIN,

VIH - 2 V,

VIL = VIL max,

IOH =-400/LA

Vee = MIN,

VIH = 2 V,

Vil =Vll max

Input current at
maximum input voltage

2

2.5

3.5

2.7

0.25

1I0L=4mA

0.4

Vi =7V

~

I

High-level input current

VCC= MAX,

VI = 2.7 V

20

IlL

low-level input current

VI = 0.4 V

lOS

Short·circuit output current§

VCC = MAX,
Vec= MAX

-0.4
-100

Supply current

VCC = MAX,

-20
See Note 2

0.25

0.4

0.35

0.5
~

.1

.1

U.I

)

-20

V
V
V

3.5

U.I

I

IIH

Ice

-1.5

tlOl =8 mA

Vee = MAX,

V
0.8

0,7
-1.5

V
mA

20

p,A

-0.4
-100

mA
mA

l'lS377
l'lS378

17
13

28
22

17
13

28
22

mA
mA

l'lS379

9

15

9

15

mA

I

I

•

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All typical values are at V CC = 5 V, T A = 25° C.
§ Note more than one input should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: With all outputs open and ground applied to all data and enable inputs, ICC is measured after a momentary ground,
then 4.5 V, is applied to clock.

switching characteristics, Vee

=5 V, TA = 25°e

PARAMETER

TEST CONDITIONS MIN

Maximum clock freq'uency

tPlH

Propagation delay time, low-to-high-level output from clock

RL = 2 kU

17

27

ns

tpHl Propagation delay time, high-to-low-Ievel output from clock

See Note 3

18

27

ns

CL = 15 pF,

30

TVP MAX UNIT

f max

40

MHz

NOTE 3: Load circuit and voltage waveforms are shown on page 3-11.

1076

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7-483

TTL
MSI

TYPES SN 54S381, SN74$381
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
BULLETIN NO. DL-S 7612124, MARCH 1974 -

REVISED OCTOBER 1976

SN54S381 ..• J PACKAGE
SN74S381 .•• J OR N PACKAGE

PIN DESIGNATIONS

{TOP VIEW)
PIN NOS.

DESIGNATION

A3, A2, Al, AO 17,19,1,3
B3, B2, B1, BO 16,18,2,4
7,6,5

S2, Sl, SO

FUNCTION
WORD A INPUTS
WORD B INPUTS
FUNCTION-SELECT
INPUTS
CARRY INPUT FOR

Cn

15
\

ADDITION,INVERTED\
CARRY INPUT FOR
SUBTRACTION

F3, F2, Fl, FO 12,11,9,8 FUNCTION OUTPUTS
INVERTED CARRY

P

14

G

13

VCC
GND

20

SUPPLY VOLTAGE

10

GROUND

PROPAGATE OUTPUT
INVERTED CARRY
GENERATE OUTPUT

•

A Fully Parallel 4-Bit ALU in 20-Pin
Package for 0.300-1 nch Row Spacing

•

Ideally Suited for High-Density
Economical Processors

•

Parallel Inputs and Outputs and Full
Look-Ahead Provide System Flexibility

•

I
•

logic: see function table

FUNCTION TABLE
SELECTION ARITHMETIC/LOGIC

Arithmetic and Logic Operations
Selected Specifically to Simplify System
Implementation:
A MinusB
B Minus A
A Plus B
and Five Other Functions
Schottky-Clamped for Hi~ Performance
i 6-Bit Add Time ... 26 ns Typ Using
Look-Ahead
32-Bit Add Time ... 34 ns Typ Using
Look-Ahead

S2

S1

SO

L

L

L

OPERATION

L

L

H

B MINUSA

L

H

L

A MINUSB
A PLUS B

CLEAR

L

H

H

H

L

L

AGB

H

L

H

A + B

H

H

L

AB

H

H

H

H

~

high level.

PRESET
L ; low level

description
The 'S381 is a Schottky TTL arithmetic logic unit (ALU)/function generator that performs eight binary arithmetic/
logic operations on two 4·bit words as shown in the function table. These operations are selected by the three
function-select lines (SO, S1, S2). A full carry look·ahead circuit is provided for fast, simultaneous carry generation
by means of two cascade outputs (p and G) for the four bits in the package. The method of cascading SN54182/
SN74182 or SN54S182/SN74S182 look·ahead carry generators with these ALU's to provide multi-level full carry
look·ahead is illustrated under typical applications data for the '182 and 'S182. The typical addition times shown
above illustrate the short delay time required for addition of longer words when full look-ahead is employed. The
exciusive·OR, AND, or OR function of two Boolean variables is provided without the use of external circuitry. Also,
the outputs can be either cleared (low) or preset (high) as desired.

1076

7-484

TEXAS INCORPORATED
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POST OFFICE BOX 5012

•

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TYPES SN 54S381, SN74S381
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
REVISED OCTOBER 1976

functional block diagram and schematics of inputs and outputs
EQUIVALENT OF EACH INPUT

VCC-----4I--_ _

INPUT

Any A or B: Req = 1
Cn: Req
Any S:

Req

kn

= 800 n
= 6 kn

TYPICAL OF ALL OUTPUTS
- - - -.......-VCC

~---41---

OUTPUT

•

1076

TEXAS INCORPORATED
INSTRUMENTS
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•

DALLAS. TEXAS 75222

7-485

TYPES SN54S381, SN74S381
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see !\I0te 1)
Input voltage . . . . . . . . . . . . . .
.••..•
Interemitter voltage (see Note 2)
Operating free-air temperature range: SN54S381
SN74S381
Storage free-air temperature range
NOTES:

. 7V
5.5 V
5.5 V
-55°C to 125°C
oOe to 70°C
_65°C to 150°C

1. Voltage values, except interemitter voltage, are with respect to network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For this circuit, this rating applies to each A input in
conjunction with its respective B input; for example AO with BO, etc.

recommended operating conditions
SN74S381

SN54S381

Supply voltage, Vee

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

-1

mA

20

mA

70

°e

-1

High·level output current, 10H

20

Low-level output current, 10L
-55

Operating free-air temperature, T A

UNIT

MIN

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High·level input voltage

VIL

Low·level input voltage

VIK

Input clamp voltage

VOH

High·level output voltage

TEST CONDITIONSt

MIN

TYPt

VOL

Low-level output voltage

II

Input current at maximum input voltage

•

High-level input current

Vee= MIN,

II = -18mA

SN54S381

Vee - MIN,

VIH - 2 V,

2.4

3.4

SN74S381

VIL = 0.8 V,

10H = -1 mA

2.7

3.4

Vee = MIN,

VIH =2V,

VIL = 0.8 V,

10L =20mA

Vee = MAX,

VI = 5.5 V

en
All others

Low-level input current

en
All others

0.8

V

-1.2

V
V

0.5
1

V
mA

50
Vee = MAX,

VI = 2.7 V

250

~A

200

Any S inpu
IlL

UNIT
V

Any S input
IIH

MAX

2

-2
Vee = MAX,

-8

VI = 0.5 V

mA

-6

lOS

Short-circuit output current§

Vee = MAX

lec

Supply current

Vee= MAX

-40
105

-100

mA

160

mA

MAX

UNIT

--

tFor conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER.
tPLH
tpHL
tpLH

FROM

TO

(INPUT)

(OUTPUT)

Cn

Any F

Any A or B

TEST CONDITIONS

MIN

10

-

G

tpHL
tPLH

Any A or B

CL=15pF,

P

See Note 3

tPHL
tpLH
tpHL
tpLH

AiorBi

Fi

Any S

Any

TYP

tpHL

RL = 280

n,

17

10

17

12

20

12

20

11

18

11

18

18
16

27
25

18

30

18

30

ns
ns
ns
ns
ns

.tPLH == propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.
1076

1-486

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TIL

TYPES SN54LS386, SN74LS386
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

MSI

BULLETIN NO. DL-S 7612118, MARCH 1974-REVISED OCTOBER 1976

SN54LS386 ••. J OR W PACKAGE
SN74LS386 .•• J OR N PACKAGE
(TOP VIEW)

•

Vee

4B

4A

4Y

3Y

3B

3A

lA

lB

lY

2Y

2A

2B

GND

Electrically Identical to

SN54LS86/SN74 LS86
•

Mechanically Identical to

SN54L86/SN74L86
•

Total Average Propagation Delay
Times ... 10 ns

•

Typical Total Power
Dissipation ... 30.5 mW

positive logic: Y = A <±> B

= AB

+ AS

FUNCTION TABLE
(EACH GATE)
INPUTS
A

OUTPUT

L

L

L

L

H

H

H

L

H

H

H

L

H
L

schematics of inputs and outputs

B

= high level
= low level

EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

•

-----------4~---Vcc

vcc-------e-----12.5

kn NOM

I NPUT·--. . . . . .--4II---__
......-

......--OUTPUT

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-487

TYPES SN54LS386, SN74LS386
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
REVISED OCTOBER 1976

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
..... .
Input voltage . . . . . . .
..... .
Operating free-air temperature range: SN54LS386
SN74LS386
Storage temperature range

7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54 LS386
MIN
Supply voltage, Vee

4.5

NOM

MIN

NOM

5.5

4.75

5

5

High-level output current, 10H

SN74LS386

MAX
-400

Low-level output current, 10L

MAX
5.25

V

-400

/loA

8

mA

70

°e

4
-55

Operating free-air temperature, T A

125

UNIT

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

MIN

TVPt

SN74 LS386

MAX

2

VOH High-level output voltage

Vee= MIN,

II = -18 mA

Vec= MIN,

VIH=2V,

VIL = VIL max, 10H = -400/loA
Vee

= MIN.

VIH=2V,

VOL Low-level output voltage

•

SN54LS386

TEST CONDITIONSt

PARAMETER

I

2.5

TVPt

MAX

2

UNIT
V

0.7

0.8

V

-1.5

-1.5

V

2.7

3.4
0.25

10L = 4 mA

MIN

0.4

3.4

V

0.25

0.4

0.35

0.5

V

VIL = VIL mad 10L = 8 mA

mA

II

Input current at maximum input voltage

Vee - MAX,

VI-7 V

0.2

0.2

IIH

High-level input current

Vee = MAX,

VI - 2.7 V

40

40

/loA

IlL

Low-level input current

Vee = MAX,

VI = 0.4 V

-0.8

-0.8

mA

lOS

Short-circuit output current§

Vee = MAX

-42

mA

lee

Supplv current

Vee- MAX,

10

mA

-40

-6
See Note 2

6.1

-5

10

6.1

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t All typical values are at V CC = 5 V, T A = 25° C.
§ Not more than 0 ne output shou Id be shorted at a time.
NOTE 2: ICC is measured with the inputs grounded and the outputs open.

switching characteristics, Vee
PARAMETERlI
tpLH

=5 V, TA = 25°C
FROM

TEST CONDITIONS

(INPUT)
AorB

Other input low eL = 15 pF,

tpHL
tpLH

RL = 2 kn,
AorB

Other input high See Note 3

tpHL

MIN

TVP

MAX UNIT

12

23

10

17

20

30

13

22

ns
ns

lItPLH '" propagation delay time, low-to-high-Ievel output
tpHL '" propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit and VOltage waveforms are shown on page 3-11.

1071

7-488

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TTL

TYPES SN54390, SN54LS390,. SN54393, SN54LS393,
SN14390, SN14LS390, SN14393, SN14LS393
DUAL 4-BIT DECADE, AND BINA.RY COUNTERS
BUL

OCTOBER 1976

SN54390, SN54LS390 .•. J OR W PACKAGE

•

Dual Versions of the Popular '90A, 'LS90
and '93A, 'LS93

•

'390, 'LS390 .. .Individual Clocks for A and B
Flip-Flops Provide Dual +2 and +5 Counters

SN74390, SN74LS390 .•• J OR N PACKAGE
(TOP VIEW)

•

'393, 'LS393 ...Dual 4-Bit Binary Counter
with Individual Clocks

•

All Have Direct Clear for Each
4-Bit Counter

•

Dual4-Bit Versions Can Significantly Improve
System Densities by Reducing Counter Package
Count by 50%

e

Typical Maximum Count Fiequency ... 35 MHz

•

Buffered Outputs Reduce Possibility of Collector
Commutation

OUTPUTS

VCC

2A

2

OUTPUT

CLEAR

2QA

r-l~~"

I

I I¥

1A

CL~AR OJ~~UT

e
1B

2B~

~ ~
I

I

Qo

I

~

GND

OUTPUTS

positive logic: High input to clear resets all four
outputs low

description
SN54393, SN54LS393 •.. J OR W PACKAGE

Each of these monolithic circuits contains eight
master-slave flip-flops and additional gating to imple·
ment two individual four-bit counters in a single
package. The '390 and 'LS390 incorporate dual
divide-by-two and divide-by-five counters, which can
be used to implement cycle lengths equal to any
whole and/or cumulative multiples of 2 and/or 5 up
to divide-by-100. When connected as a bi-quinary
counter, the separate divide-by-two circuit can be
used to provide symmetry (a square wave) at the final

SN74393, SN54LS393 ... J OR N PACKAGE
(TOP VIEW)
OUTPUTS

•

output stage. The '393 and 'LS393 each comprise
two independent four-bit binary counters each having
a clear and a clock input. N-bit binary counters can
be implemented with each package providing the
capability of divide-by-256. The '390, 'LS390, '393,
and 'LS393 have parallel outputs from each counter
stage so that any submultiple of the input count
frequency is available for system-timing signals.
Series 54 and Series 54LS circuits are characterized
for operation over the full military temperature range
of -55°C to 125°C; Series 74 and Series 74LS
circuits are characterized for operation from O°C
to 70°C.

positive logic: High input to clear resets all four
outputs low

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-489

TYPES SN64390, SN64LS390. SN64393, SN54LS393.
SN74390. SN74LS390. SN74393. SN74LS393
DUAL 4-BIT DECADE AND BINARY COUNTERS
FUNCTION TABLES
'390, 'LS390
BCO COUNT SEQUENCE
(EACH COUNTER)
(See Note A)

'390, 'LS390
BI·QUINARY (5·2)
(EACH COUNTER)
(See Note B)

OUTPUT

COUNT

0
1

L

L

L

OUTPUT

COUNT

QO QC QB QA
L
L
L
L

'393, 'LS393
COUNT SEQUENCE
(EACH COUNTER)

QA QO QC QB

H

OUTPUT

COUNT
QO

Oc

QB QA

0

L

L

L

L

0

L

L

L

L

1

L

L

L

H

1

L

L

L

H

2

L

L

H

L

2

L

L

H

L

2

L

L

H

L

3

L

L

H

H

3

L

L

H

H

3

L

L

H

H

4
5
6

L

H

L

L

4

L

H

L

L

4

L

H

L

L

L

H

L

H

5

H

L

L

L

5

L

H

L

H

L

H

H

L

H

L

L

H

H

H

L

L

H

H

H

H

L

H

L

6
7

L

7

L

H

H

H

H

L

H

H

8

H

L

L

L

H

H

L

L

9

H

L

L

H

10

H

L

H

L

11

H

L

H

H

12

H

H

L

L

13

H

H

L

H

8

H

L

L

L

6
7
8

9

H

L

L

H

9

NOTES:

A. Output QA is connected to Input B for BCD count.
B. Output QD is connected to input A for bi-quinary
count.
C. H = high level. L = low level.

14

H

H

H

L

15

H

H

H

H

functional block diagrams
OUTPUT

•

aA

(1,151

INPUT A

aA

OUTPUT
(4,12)

Os

!NPUTlJ

OUTPUT

Oc

OUTPUT

aD

(2,

CLEAR 14)

INPUT

'390, 'LS390

'393, 'LS393

1076

7-490

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54390. SN54LS390. SN54393, SN54LS393.
SN14390, SN14LS390. SN14393. SN14LS393
DUAL 4-BIT DECADE AND BINARY COUNTERS
schematics of inputs and outputs

'390, '393
EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

VCC3-Req

INPUT

--

INPUT

Req NOM

A ('390)...... 3 kn
B ('390) ...... 1.5 kn
A ('393)...... 3 kn
Any clear . . . . .. 8 kn

-

'LS390, 'LS393

EQUIVALENT OF EACH
AAND B INPUT

EQUIVALENT OF EACH
CLEAR INPUT

VCC

VCC~-18 kn NOM

A

Req

INPUT

INPUT

INPUT

--

~

Req NOM

TYPICAL OF ALL OUTPUTS

--

~

A ('LS390l. ........ 4.3 kn
B ('LS390). ........ 2.7 kn
A ('LS393l. ....... .4.3 kn

•

076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-491

TYPES SN54390. SN54393. SN74390. SN74393
DUAL 4-BI1 DECADE AND BINARY COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) . . . . .
Input voltage . . . . . . . . . . . . .
Operating free·air temperature range: SN54390, SN54393
SN74390, SN74393
Storage temperature range

7V
5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54390

SN74390

SN54393

SN74393

MIN
4.5

Supply voltage, V CC

NOM
5

MIN

NOM

5.5

4.75

5

-800

High-level output current, 10H
Low-level output current, 10L

16
A input

Count frequency, fcount

B input

Pulse width, tw

0

25

0

20

V
J.l.A

16

mA

0

20

20

B input high or low

25

25

Clear high

20

20

25-1-

5.25
-800
25

20

Clear" inactive-state setup time, tsu

UNIT
MAX

0

A input high or low

MHz

ns
ns

25+

-55

Operating free-air temperature, T A

+The

MAX

125

°c

70

0

arrow indicates that the falling edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

•

VIH

High·level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

II

'390

TEST CONDITIONSt

PARAMETER

MIN

TYP+

VCC = MIN,

11=-12mA

VCC= MIN,

VIH=2V,

VIL = 0.8 V,

10H = -800J.l.A

VCC = MIN,

VIH=2V,

,VIL =0.8V,

Input current at

Low-level input current

V

-1.5
2.4

3.4
0.2

10L = 16mA'

VCC = MAX, VI = 5.5 V

'Input A

r--Clear
'Input A

VCC = MAX, VI = 2.4 V

2.4
0.4

0.8

V

-1.5

V

3.4
0.2

V

1

1

40

40

80

80

-1

i

-3.2

'Input B

-1
-3.2

I

V

0.4

120
VCC = MAX, VI = 0.4 V

UNIT

2

Input B

IlL

TYP+ MAX

0.8

maximum input voltage
High-level input current

MIN

2

Clear
IIH

'393
MAX

mA

J.l.A

i
mA

I

-4.8
ISN54'

-20

-57

-20

ISN74'

-18

-57

-18

lOS

Short-circuit output current §

VCC = MAX

ICC

Supply current

VCC = MAX, See Note 2

42

69

-57
-57
38

64

mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at V CC = 5 V, T A = 25°C.
, The QA outputs of the '390 are tested at IOL = 16 mA plus the limit value for IlL for the B input. This permits driving the B input while
maintaining full fan·out capability.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

107€

7-492

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54390, SN54393, SN74390, SN74393
DUAL 4-BI1 DECADE AND BINARY COUNTERS
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~

f max
tPLH

FROM

TO

(INPUT)

(OUTPUT)
QA

25

35

QB

20

30

QA

A

TYP

25

35

MAX

20

12

20

13

20

13

20

37

60

40

60

RL=400n,

39

60

40

60

See Note 3

13

21

and

14

21

24

39

26

39

13

21

14

21

B

QB

B

QC

Figure 1

B

QD

Clear

Any

tpHL

ns
ns
ns
ns
ns

24

39

24

UNIT
MHz

12
CL = 15 pF,

tpHL
tpLH

MIN

QD of '393

tPHL
tPLH

MAX

QC of '390

tpHL
tPLH

TYP

B
A

tPLH

MIN

A

tpHL

'393

'390

TEST CONDITIONS

39

ns

~fmax = maximum count frequency
tpLH = propagation delay time, low-to-high-Ievel output
tpH L = propagation delay time, high-to-Iow-Ievel output
NOTE 3: Load circuit is shown on page 3-10.

PARAMETER MEASUREMENT INFORMATION

\~~

r"

~::----~,-----------~,---------::

i

~

tsu

I-

~

~

-,

IN~UT:

~----3V

.1_SV

'l.SV

1.SV

~tPHL

OUTPUTQA~I~.
.==~

I

,1.5V

INPUT

:

-

--

I

t~rf

at tn+l

I

1.SV

I ~l.SV
htpHL

,I

+\l.SV

~.

at tn+2

/

I -

tpLH-Measure at tn+2

I
:

,

- - - "\,

OUTPUT QD

I

I

I

r------rtpHL -Measure at tn+4

,_

!1.5V

I

/1

I

,I _

b

1 .5V
\:.VOL

:_

RtPHL-Measureat tn+8

{f-I--voH

lSV

----tf

-\-l.S V

•

X-

:

~} tpLH-Measureat tn+4

I

VOL

f f - I - -VOH

H ·

--...:...-.....Ji-----------4rS-s--..:I--;.I-J
~tpHL

ov

r~----VOH
I
1.SV

-

M

- - --,,\,
OUTPUTQc

'I

l\1.5V

-

~I

,\

I
I
I

~LH-Measure ~ Ii>HL-Measure

r-----:-tpHL

OUTPUTQB

1.SV

, I

I

-

tw(clock)

I

.
tpLH-Measure at tn+8

I
I
I

,-

I ~l.SV

I

\:.VOL

\4-=-=t\.
tpHL -Measure at t n +l0 for '390
~
ortn+lsfor'393

l'----oIHlf--.....;.....;--"""'\:i
1.S V

VOH
1.5 V

----------~\~------------~J,~S-------------'·

VOL

VOLTAGE WAVEFORMS
NOTE A: Input pulses are supplied by a generator having the following characteristics tr';; 5 ns, tf';; 5 ns, PRR
Zout '" 50 ohms_

=1

MHz, duty cycle = 50%,

FIGURE 1

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-493

TYPES SN54LS390, SN54LS393, SN74LS390, SN74LS393
DUAL 4-BIT DECADE AND BINARY COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Clear input voltage . . . . . .
Any A or B clock input voltage
Operating free-air temperature range: SN54LS390, SN54LS393
SN74LS390,SN74LS393
Storage temperature range

. 7V

. 7V
5.5V
_55°C to 125°C
O°C to 70°C
_65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS390
SN54LS393
MIN
Supply voltage, V CC

NOM

4.5

MAX

MIN

NOM

5.5

4.75

5

5

High-level output current, 10H

SN74LS390
SN74LS393

Low-level output current, 10L

-400

4
A input
B input

Pulse width, tw

0

25

0

20

S
0

25

0

20

A input high or low

20

20

B input high or low

25

25

Clear high

20

20

Clear"inactive·state setup time, tsu

25.

Operating free-air temperature, T A
.j.

5.25

-400

Count frequency, fcount

UNIT

MAX

125

rnA
MHz

ns
ns

25.

-55

V
p,A

70

0

°c

The arrow indicates that the falling edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

•

VIH

High·level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

IIH

maximum input voltage

VCC= MIN,

II = -lS rnA

VCC= MIN,

VIH=2V,

2.5

VIL = VI Lrnax, VOH = -400p,A
VCC= MIN,

Low-level output voltage
Input current at

II

VIH=2V,

MAX

VI=5.5V

Input B

Clear
r-High-level input current [Input A VCC = MAX,
Clear
f--Low-level input current Input A Vce= MAX,

,.......--

VI = 2.7 V

VI=0.4V

Input B

lOS

Short-circuit output current§

ICC

Supply current

-1.5

0.4

-20

Vec = MAX

0.25

0.4

0.35

0.5

V

V

0.1 ,

0.2

0.2

0.4

0.4

20

20

40

40

SO

SO

-0.4

-0.4 .

-1.6

-1.6

-2.4

-2.4

-100

V

V

3.4

0.1,

VI =7 V

~ VCC=

-1.5

10L=SmA~

Clear

I---

O.S

2.7

UNIT
V

0.7

3.4
0.25

IOL=4mA.

VIL = O.S V,

MAX

2

Input B

IlL

SN74LS'

MIN TYP:!: MAX MIN TYP:!:
2

VOH High-level output voltage
VOL

SN54LS'

TEST CONDITIONSt

PARAMETER

-20

-100

Vee = MAX,

'LS390

15

26

15

26

See Note 2

'LS393

15

26

15

26

rnA

p,A

rnA

I

rnA
rnA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:!:AII typical values are at Vee = 5 V, T A = 25°e .
• The QA outputs of the 'LS390 are tested at 10L = MAX plus the limit value for IlL for the clock B input. This permits driving the clock B
input while maintaining full fan-out capability.
§ Not more than one output should be shorted at a time,and duration of the short-circuit should not exceed one second.
NOTE 2: lee is measured with a!l outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.
1076

TENTATIVE DATA

7-494

This page provides tentative information on a
new product. Texas Instruments reserves the
right to change specifications for this product
in any manner without notice.

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS390, SN54LS393, SN74LS390, SN74LS393
DUAL 4-BIT DECADE AND BINARY COUNTERS
= 5 V, T A = 25' C

switch ing characteristics, Vee
PARAMETER'

FROM

TO

(INPUT)

(OUTPUT)

A
B

f max
tPLH

A

B
B

== max imu m

QB

20

30

'L.s393
MAX

B

QD

Clear

Any

MIN

TYP

25

35
12

20

MAX

MHz

13

20

13

20

37

60

40

60

RL = 2 kn,

39

60

40

60

See Note 4 and Figure 2

13

21

14

21

24

39

26

39

13

21

14

21

24

39

UNIT

20

CL = 15 pF,

QC

tPHL

, f max
tpLH
tpH L

35

QB

tPHL

tpHL

25

QD of 'LS393

tPHL

tPLH

QA

QA

A

tPLH

TYP

Oc of 'LS390

tPHL
tPLH

MIN

12

tpHL
tPLH

'LS390

TEST CONDITIONS

ns
ns
ns
ns
ns

24

39

ns

cou nt freq uency

== propagation delay time, low-to-high-Ievel output
== propagation delay time, high-to-Iow-Ievel·output

NOTE 4: Load circuit is shown on page 3-11.

PARAMETER MEASUREMENT INFORMATION

("

~~~

~~;;----~,-----------~,---------

!• •I
IN~UT:
~1.3V ~1.3V
~
r\:,;....1 . -- ~
I

I+-

tsu

~

tw(clock)

/ \

~

1-

-I

l

'i.~

I

attn+1

~rf

,1.3 V

I
~tPHL
- -- ~

t

I

1 3V
.

!

\1.3

H

I
:

-

-

-

+

I

1.3 V

\

~tPHL
~ 1.3 V
\

rs

I
,_

I
I

r~-

I

II (I

I

I_

•

-VOH

VOL

r----rtpHL-Measureat tn+4

I

-VOH

'\::V

I

VOL
R}'PHL-Measureat tn+8

ff-'--v

13V

~tPLH-Measureattn+8

/1.3

ov

~

ff-I-

_I} tpLH-Measureattn+4

~

--

3V

I'

!1.3V

I~
,_

----"'\1
OUTPUTOc

I
I

:

~::-I

attn+2

1
~tPLH-MeaSUreattn+2

V

I
r----r-tPHL

\_

I

l\13V

B INPUT

OUTPUTQB

J

~PLH-Measure ~tPLH-Measure

tPHL

OUTPUT QA -..;........,.,
'L::!

~

V

If

IS·

~1.3V OH

I

I

I
~_

I
L.VOL
~} tpHL-Measureattn+10for'LS390
~ l~:OH
or 'n+16 for 'LS393
\:.VOL

VOLTAGE WAVEFORMS
NOTE A:

Input pulses are supplied by a generator having the following characteristics tr';; 15 ns, tf .;; 6 ns, PR R

=1

MHz, duty cycle

= 50%,

Zout "" 50 ohms_

1076

TENTATIVE DATA
This page provides tentative information on a
new product. Texas Instruments reserves the
right to change specifications for th is product
in any manner without notice.

TEXAS INSTRUM ENTS
INCORPORATED
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

1-495

TTL
MSI

TYPES SN54LS395A. SN74LS395A
4-BI1 CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS
BULLETIN NO. OL-S 7612114, OCTOBER 1976

SN54LS395A ..• J OR W PACKAGE
SN74LS395A ••• J OR N PACKAGE
(TOP VIEW)

•

Three-State, 4 Bit, Cascadable,
Parallel-In, Parallel-Out Registers

•

'LS395A Offers Three Times the
Sink-Current Capability of 'LS395

•

Low Power Dissipation ... 75 mW Typical
(Enabled)

•

Applications:
N-Bit Serial-To-Parallel Converter
N-B it Parallel-To-Serial Converter
N-Bit Storage Register

.

OUTPUTS

description
These 4-bit registers feature parallel inputs, parallel
outputs, and clock, serial, load/shift, output control
and direct overriding clear inputs.
PARALLh INPUTS

Shifting is accomplished when the load/shift control
is low. Parallel loading is accomplished by applying
logic; see functional table
the four bits of data and taking the load/shift control
input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-Iow transition
of the clock input. During parallel loading, the entry of serial data is inhibited.
When the output control is low, the normal logic levels of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a high logic level at the output control
input. The outputs then present a high impedance and neither load nor drive the bus line; however, sequential operation
of the registers is not affected. During the high-impedance mode, the output at GO' is still available for cascading.

•

FUNCTION TABLE
3-STA TE OUTPUTS

INPUTS
CLEAR

,

LOAD/SHIFT
CONTROL

CLOCK SERIAL

L

X

X

H

H

H

H

H

~

X
X
X

H

L

H

X

H

L

~

H

H

L

~

I.,.

PARALLEL
A B C 0

°A

°B

Oc 00

L
L
X X X X L
L
,X X X X OAO 0BO OCO 0DO
d
b
c
a b c d a
X X X X 0AO 0BO 0CO 0DO
X X X X H 0An 0Bn 0Cn
X X X X L 0An 0Bn 0Cn

CASCADE
OUTPUT
aD'
L
°DO

d
°DO
°Cn
OCn

When the output control is high, the 3-state outputs are disabled to the high-impedance state;
however, sequential operation of the registers and the output at QO' .are not affected_
See explanation of function tables on page 3-8.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
...... .
Input voltage . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54LS395A
SN74LS395A
Storage temperature range

7V
7V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

DESIGN GOAL

7·496

This page provides tentative information on a

product in the developmental stage. Texas
Instruments reserves the right to change or discontinue this product without notice.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TYPES SN54LS395A. SN74LS395A
4-BIT CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS
recommended operating conditions
SN54LS395A
Supply voltage, VCC

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

V

-1

-2.6

mA

-400

-400

J.lA

12

24

mA

QD'
QA,QB, Qc,QD

Low-level output current, IOL

UNIT

NOM

QA,QB,Qc,QD

High-level output current, IOH

SN74LS395A

MIN

QD'

4
0

Clock frequency, fclock

25

0

8

mA

25

MHz

Width of clock pulse, tw(clock)

25

25

Setup time, high-level or low-level data, tsu

20

20

ns

Hold time, high-level or low-level data, th

10

10

ns

-55

Operating free-air temperature, T A

125

ns

70

0

°c

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
iESi COr~DiTioNst

FARAiv1EiER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

IOZH
IOZL

Low-ievei output voitage

II

VCC= MIN,

II =-18mA

VCC = MIN,

VIH = 2 V,

VIL = VIL max,

IOH = MAX

MIN

TYpt

VIL = VIL max,

QD'

Qc,QD

IOL - 24 mA I

QD
VIH=2V,

high-level voltage applied

VO=2.7V

Off-state output current,

VCC = MAX,

low-level voltage applied

VO=0.4 V

3.4

2.5

V
0.8

V

-1.5

V

3.1

V

IOL -4 mA

2.7

3.4

V

3.4

0.25

0.4

0.25

0.4

0.35

0.5 I

0.25

0.4

0.25

0.4

0.35

0.5

IOL=8mA
QA,QB,
Qc,QD

VIH-2V,

2.4

QA,QB,

VI =7V

V
I
V

20

20

J.lA

-20

-20

J.lA

0.1

0.1

mA

Qc,QD

VCC = MAX,

Ui~ii

Qc,QD
IOL = 12mA

VCC= MAX,

2.4

MAX

2
-1.5

QA,QB,

QA,QB,

VIH = 2 V

maximum input voltage

SN74LS395A

MAX
0.7

Off-state output current,

Input current at

TYPt

2

VCC= MIN,
VOL

SN54LS395A
MIN

IIH

High-level input current

VCC= MAX,

VI = 2.7 V

20

20

J.lA

IlL

Low-level input current

VCC = MAX,

VI = 0.4 V

-0.4

-0.4

mA

lOS

Short-circuit output current§

VCC= MAX

QA,QB,
Qc,QD
QD
ICC

Supply current

VCC= MAX,

See Note 2

-30

-130

-30

-130

mA

-20

-100

-20

-100

mA

Condition A

18

29

18

29

Condition B

15

25

15

25

•

mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V. T A = 25°e.
§ Not more than one output should be shorted at a time,and duration of the short-circuit should not exceed one second.
NOTE 2: lee is measured with the outputs open, the serial input and mode control at 4.5 V, and the data inputs grounded under the following
conditions:
A. Output control at 4.5 V and a momentary 3 V, then ground, applied to clock input.
. B. Output control and clock input grounded.

1076

DESIGN GOAL
This page provides tentative information on a

product

in

the developmental stage. Texas

1nstruments reserves the right to change or d iscontinue this product without notice.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-497

TYPES SN54LS395A, SN74LS395A
4-BIT CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER

TEST CONDITIONS

f max

Maximum clock frequency

tPHL

Propagation delay time, high-to-Iow-Ievel output from clear

tpLH

Propagation delay time, low-to-high-Ievel output

MIN

See Note 3,
QA, QB,

TYP

25

MAX

Oc, QD outputs:

RL = 667 n, CL = 45 pF

UNIT
MHz

35
23

35

ns

23

35

ns

20

30

ns

13

20

ns

24

36

ns

tPHL

Propagation delay time, high-to-low-Ievel output

tpZH

Output enable time to high level

tpZL

Output enable time to low level

tpHZ

Output disable time from high level

CL =5 pF,

11

17

ns

tpLZ

Output disable time from low level

See Note 3

15

23

ns

QD' output:
RL =2 kn,CL = 15pF

NOTE 3: Load circuit and voltage waveforms are shown on page 3-11.

functional block diagram
DATA INPUTS

•

(4)

(6)

(5)

(14)

(13)

Os

v

ac

(12)

(11)

aD

I

00'

3-STATE OUTPUTS

CASCADE
OUTPUT

schematics of inputs and outputs
EQUIVALENT OF SERIAL
AND DATA INPUTS

Vee --~fr--Req-

Serial: Req
A, B, C, D: Req

= 30 kn

NOM

o

EQUIVALENT OF
OTHER INPUTS

vee

"PUT_q--

INPUT-

------vee

TYPICAL OF QD' OUTPUTS

- - -......--vee

-OUTPUT

OUTPUT

= 20 kn NOM

This page provides tentative information on a
product in the developmental stage. Texas
I nstruments

TYPICAL OF QA, QS. Oc. QD
OUTPUTS

20k r1 NOM

DESIGN GOAL

7-498

o

C

B

A
(3)

reserves

the right to change or dis~

continue this product without notice.

TEXAS

I N STRUM ENTS

INCORPORATED
POST OFFICE BOX 5012 •

CALLAS, TEXAS 75222

1076

TYPES SN54LS398, SN54LS399
SN74LS398, SN74LS399
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE

TTL
MSI

BULLETIN NO. DL-S 7612465, OCTOBER 1976

•
•
•

SN54LS398 ••• J OR W PACKAGE
SN74LS398 ••• J OR N PACKAGE
(TOP VIEW)

Double-Rail Outputs on 'LS398
Single-Rail Outputs on 'LS399
'LS398 is Similar to 'LS298,
Which Has Inverted Clock

•

Selects One of Two 4-Bit Data Sources
and Stores Data Synchronously with System Clock

•

Applications:
Dual Source for Operands and Constants
in Arithmetic Processor; Can Release
Processor Register Files for Acquiring
New Data
Implement Separate Registers Capable of
Parallel Exchange of Contents Yet Retain
External Load Capability

logic: see function table

Universal Type Register for Implementing
Various Shift Patterns; Even Has Compound
Left-Right Capabilities

SN54LS399 •.. J OR W PACKAGE
SN74LS399 .•• J OR N PACKAGE
(TOP VIEW)

Co

Vcc

01

02

C2

Cl

Clc

CLOCK

~

description
These mono!!thic quadruple t'No-input multiplexers

with storage provide essentially the equivalent functional capabilities of two separate MSI functions
(SN54LS157/SN74LS157
and
SN54LS175/
SN74LS175) in a single 16-pin or 20-pin package.

ws

II

When the word-select input is low, word 1 (A1, 81,
C1, 01) is applied to the flip-flops. A high input to
word select will cause the selection of word 2 (A2,
82, C2, 02). The selected word is clocked to the
output terminals on the positive-going edge of the
clock pulse.

logic: see function table

Typical power dissipation is 37 milliwatts.
SN54LS398 and SN54LS399 are characterized for
operation over the full military range of -55°C to
125°C, SN74LS398 and SN74LS399 are characterizea for operation from O°C to 70°C.

FUNCTION TABLE
INPUTS
WORD

OUTPUTS

CLOCK

aA

t
t

a1

b1

c1

d1

H

a2

b2

c2

d2

X

L

QAO

QBO

Qeo

QDO

SELECT
L

aB

Dc

aD

See explanation of function tables on page 3-8.

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

7-499

TYPES SN54LS398, SN54LS399, SN74LS398, SN74LS399
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
functional block diagram
A1-------,-........,
WORD
SELECT

A2---+--+-+-L-"';

B1-----+-~r-........,

B2-----f--+-IL-.../

C1-----+-+-r--........,

C2-----f--f--L-J

D1-----r--t---i,--.......
QD

'00

•

CLOCK

-----------1

~D_--------'

I

-- . . . .

Dynam ic input activated by a transition from a high level to a low level

I

. . . . 'LS398 Only

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF
OTHER INPUTS

EQUIVALENT OF
EACH DATA INPUT

------411..... Vee

VCC

Vee

,
Req

30kn
NOM
INPUT
INPUT .............- + -

-

C.

...s--.

OUTPUT
~,

~~

~~
/)7

Clock: Req
Word select: Req

= 17 kn
= 25 kn

NOM
NOM

1076

7·500

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54LS398, SN54LS399, SN74LS398, SN14LS399
QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . .
.... .
Operating free·air temperature range: SN54LS'
SN74LS'
Storage temperature range

..... 7 V
. . . . . 7V

-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54lS'
Supply voltage, Vee

SN74lS'

MIN

NOM

MAX

MIN

NOM

4.5

5

5.5

4.75

5

High-level output current, 10H

MAX

-400

Low-ievei output current, 10l

5.25

V

-400

/.LA

8

mA

4

Width of clock pulse, high or low level, tw

I

C" ....... _ .... : _ _
....
uCl.u ..... 1..IIIn::;,

"'su

Data

Hold time, th
Operating free-air temperature, T A

20

20

20

20

25

25

o
o

o
o
o

-55

125

UNIT

ns
ns

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIH

High·level input voltage

ViL

Lovv-Iavel input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

SN54lS'

TEST CONDITIONSt

MIN TYP+

SN74lS'
MAX MIN

2'

Vee - MIN,

II - -18 mA

Vee= MIN,

VIH = 2 V,

Vil = VILmax

10H = -400 /.LA

Vee - MIN,

VIH - 2 V,

2.5

I

Vil = VILmax

UNIT
V

0.7

0.8

V

-1.5

-1.5

V

304
0.25

llOL - 4 mA

MAX

TYP+

2

2.7

004

10L -8 mA

304

V

0.25

004

0.35

0.5

V

II

Input current at
II

Vee = MAX,

VI =7 V

0.1

0.1

IIH

High-level input current

Vee = MAX,

VI - 2.7 V

20

20

/.LA

IlL

low-level input current

Vee - MAX,

VI-OAV

-004

-004

mA

lOS

Short-circuit output current§

Vee = MAX

-100

mA

lee

Supply current

Vee = MAX,

13

mA

maximum input voltage

-20
See Note 2

-100
7.3

-20

13

7.3

mA

t For conditions shown as MI N or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee = 5 V, T A = 25°C.
§ Not more than one output should be shorted at a time, duration of the short-circuit should not exceed one second
NOTE 2: With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5 V, followed by ground, to
the clock input.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

TEST CONDITIONS

tpLH

Propagation delay time, low·to-high·level output eL = 15pF,

tPHL

Propagation delay time, high-to-Iow-Ievel output See Note 3

RL = 2 kn,

MIN

TYP

MAX

18

27

21

32

UNIT
ns

NOTE 3: Load circuit and waveforms are shown on page 3-11.

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS, TEXAS 75222

7-501

TYPES SN54S412, SN74S412 (TIM8212)
MULTI-MODE BUFFERED LATCHES

TTL
MSI

BULLETIN NO. DL-S 7512351, OCTOBER 1975

• P-N-P Inputs and 3-State Outputs Maximize
I/O and Data Bus Capabilities

SN54S412 _•• J PACKAGE
SN74S412 ••• J OR N PACKAGE
(TOP VIEW)

• Data Latch Transparency Permits
Asynchronous or Latched Receiver Modes

OAT A INPUTS AND OUTPUTS

• Mode and Select Inputs Permit Storing
With Outputs Enabled or Disabled
• Strobe-Controlled Flag Flip-Flop Indicates
Status or Interrupt
• Asynchronous Clear Sets All Eight Data
Lines Low and Initializes Status Flag
• High-Level Output Voltage, Typically 4 V,
Drives Most MOS Functions Directly
• Direct Replacement for Intel 3212
or 8212

logic: see function table

description
This high-performance eight-bit parallel expandable buffer register incorporates package and mode selection inputs and
an edge-triggered status flip-flop designed specifically for implementing bus-organized input/output ports. The
three-state data outputs can be connected to a common data bus and controlled from the appropriate select inputs to
receive or transmit data. An integral status fl ip-flop provides package busy or request interrupt commands. The outputs,
with a 4-volt typical high-level Voltage, are compatible for driving low-threshold MOS directly.
DATA LATCHES

II

The eight data latches are fully transparent when the internal gate enable, G, input is high and the outputs are enabled
(OE = H). Latch transparency is selected by the mode control (M), select (Sl and S2), and the strobe (STB) inputs and
during transparency each data output (DOi) follows its respective data input (Dli)' This mode of operation can be
terminated by clearing, de-selecting, or holding the data latches. See data latches function table.
MODE SELECTION

An input mode or an output mode is selectable from this single input line. In the input mode, MD = L, the eight data
latch inputs are enabled when the strobe is high regardless of device selection. If selected during an input mode, the
outputs will follow the data inputs. When the strobe input is taken low, the latches will store the most-recently setup
data.
In the output mode, M = H, the output buffers are enabled regardless of any other control input. During the output
mode the content of the register is under control of the select ($1 and S2) inputs. See data latches function table.
STATUS FLIP-FLOP

The status flip-flop provides a low-level output Signal when:
a.

the packagj is selected

b.

a strobe input is received.

This status signal can be used to indicate that the register is busy or to initiate an interrupt type command.

TENTATIVE DATA SHEET

7-502

This document provides tentative information
n arr:-w product. Texas 1~~tlfrO-r ~
0tha
itht to change specifications
thiS
product in any manner without 1'IOtic:e.

1076

TEXAS IN ST RU M ENTS
INCORPORATED
POST OFFICE BOX 5012

•

DALLAS

TEXAS 75222

.

TYPES SN54S412_. SN74S412 (TIM8212)
MULTI-MODE BUFFERED LATCHES
functional block diagram
r---- - - -- ----- - - ---- -----,
I

I
I

PRESET
Q

o

STB

M

51

(11)
(2)

"""-~~.........

7<>-+-- iNT

I----~~=O"'-_+_......._L - j

S2

L-------~--~-L_/

011

(3)

012

(5)

013

(7)

014

19)

DIS

118)

J:---+--+-~D02
I

1101
I-+--+~ >--+-....:..:..::.~ DO 4

115)

016

DOS

lIS)
,>-...!...-..:..:ll.:.,:.7)_ DO 6

017

120)

DIS

122)

CUi

114)

I

119)

007

121)

DOS

I
I
I

L ________________________ --.J
schematics of inputs and outputs
EQUIVALENT OF CLEAR, STROBE,
MODE, S1, AND S21NPUTS

EQUIVALENT OF EACH 01 INPUT
vcc-------------.--------~

vcc----__.-__4 -

TYPICAL OF ALL OUTPUTS

------....---vcc

OUTPUT

INPUT
I NPUT---.-:IiI.....--I

1076

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

7-503

TYPES SN54S412, SN~4S412 (TIM8212)
MULTI-MODE BUFFERED LATCHES
DATA LATCHES FUNCTION TABLE
FUNCTION

CLEAR

M

S1

S2

STB

DATA IN

DATA OUT

L

H

H

X

X

X

L

L

L

L

H

L

X

L

X

L

X

L

X

X

Clear
De-select
Hold
Data Bus
Data Bus

X

L

H

X

X

X

Z
Z

H

H

H

L

X

X

00

H

L

L

H

L

X

0.0

H

H

L

H

X

L

L

H

H

L

H

X

H

H

H

L

L

H

H

L

L

H

L

L

H

H

H

H

STATUS FLIP-FLOP FUNCTION TABLE

-INT

CLEAR

S1

S2

STB

L

H

X

X

H

L

X

L

X

H

H

X

X

-l-

L

H

L

H

X

L

H == high level (steady state)
L == low level (steady state)
X ==irrelevant (any input, including transitions)
Z == high impedance (off)
-l- ==transition from low to high level

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage .
Operating free-air temperature range: SN54S412
SN74S412
Storage temperature range. .

I

.... 7 V

5.5 V
· -55°C to 125°C
· . oOe to 70°C
· -65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN74S412

SN54S412
MIN
4.5

Supply voltage, VCC
Pulse width, tw
(see Figures 1,2, and 41

I

I

NOM MAX

MIN

5.5

4.75

5

STB or S"1 • S2

25

25

Clear low

25

25

15-l-

15-l-

Setup time, tsu (see Figure 3)
Hold time, th (see Figures 1 and 3)

20-l-55

Operating free-air temperature, T A

NOM MAX
5

5.25

0

V
ns

I

ns
ns

20-l125

UNIT

70

°c

-l- The arrow indicates that the falling edge of the clock pulse is used for reference.

1075

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TYPES SN54S412, SN74S412 (TIM8212)
MULTI-MODE BUFFERED LATCHES
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

10ZL

Vee = MIN;

II = -18mA

Vee=MIN,

VIH = 2 V,

VIL = 0.8 V,

10H= -1 rnA

Vee=MIN,
VIH=2V,

Off-state output current,

DO 1 thru

high-level voltage applied

008

Off-state ou tput cu rrent,

DO 1 thru

low-level voltage applied

008

Input current at
II

maximum input voitage

IIH

Typf

High-level input current
Low-level input current

M

MIN

Typf

MAX

2

I

UNIT
V

0.85

0.85

V

-1.2

-1.2

V

4

3.65

3.65

4

V

10L = 15mA

0.45

0.45

IIOL -20mA

0.5

0.5

Vee = MAX,

Vo =2.4 V

50

50

IJ.A

Vee = MAX,

Vo =0.5 V

-50

-50

IJ.A

Vee = MAX,

V! = 5.5 V

1

1

~I\

Vr.C=MAX,

V! =5.25 V

20

10

p..A

-1

-1

81
IlL

SN74S412
MAX

2

VIL = 0.8 V
10ZH

SN54S412
MIN

Vee= MAX,

VI =0.4 V

All others
lOS

Short-circuit output current §

Vee = MAX

ICC

Supply current

Vee = MAX,

-20
see Note 2

-0.75

-0.75

-0.25

-0.25

-65

-20

82

82

V

rnA

-65

rnA

130

rnA

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

TAli tYpical values are at Vee = 5 V, T A = 25°e.
§Not more than one output should be shorted at a time.
NOTE 2: iee is measured with ail outputs open, ciear input at 4.5 V. and all other inputs grounded.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
tpLH
tpHL
tpHL
tpLH

FROM
STB, 51, or S2
eLR

TO
Any

FIGURE

TEST CONDITIONS

1

DO
Any DO

eL =30pF,

2

See Note 3

MIN

TYP

MAX

18

27

15

25

18

27

12

20

Dli

DOi

3

10

20

tPLH

S10rS2

INT

4

eL =30pF,

12

20

tPHL

STB

INT

4

See Note 3

16

25

Any DO

5

eL=30pF,

21

35

See Note 3

25

40

eL = 5 pF,

9

20

See Note 3

12

20

tpHL

tZH

51,S2,orM

tZL
tHZ
tLZ

51,S2,orM

Any DO

5

UNIT

I

ns
ns
ns
ns
ns
ns

tpLH ==propagation delay time, low-to-high-Ievel output
tpHL == propagation delay time, high-to-Iow-Ievel output
tZH ==output enable time to high levlli
tZL ==output enable time to low level
tHZ ==output disable time from high level
tLZ == output disable time from low level
NOTE 3: Load circuit and voltage waveforms are shown on page 3-10.

1076

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7-505

TYPE5 5N545412. 5N145412 (TIM8212)
MULTI-MODE BUFFERED LATCHE5
PARAMETER MEASUREMENT INFORMATION

___ ~.~V)(------- -

DATA INPUT

~
STB OR 5'·S2

tw

,~.~ __

::V

-:r---~~---

2.5 V

\,.5 V
'-------

OV

,.5V!
_ _ _ _ _ _. J !+tPHL ~

- - - - - - - --I~;------

DATA OUTPUT

VOH
VOL

FIGURE' - S"rROBE OR SELECT TO DATA OUTPUT
-

k

_ _ _ _ _ _...... ~ !wIeld

CLEAR INPUT

,.

5V

...j

~______

t..5~

2.5 V

_____

OV

_ _ _ _ _ _ _..:........_---.:..tp.:..:.H;;:...L~ _ _ _ _ _ _
VOH
DATA OUTPUT

\,.5V
FIGURE 2 - CLEAR INPUT TO DATA OUTPUT
'.5V

DATA INPUT

X- - ---- - -

2.5 V

~.5V
th~'- - - - -

- - - -..../ I4-- t SU"
I
. {,~ ;- - - - - - - -

STBOR 8'·S2

ov
2.5 V

L--I
~tPHL

OV

-----....:......-~;---------

VOH

-------/

VOL

DATA OUTPUT
.

FIGURE 3 - DATA INPUT TO DATA OUTPUT
2.5 V
STROBE
OV

I

_______....!I__
INTERRUPT OUTPUT

2.5 V

~
I.. .'J:;;I -;P~H

I

!w(sell

0V
VOH

V-

I

\
j-,_.5.5_'V
~~tp-H-L-------~

VOL

FIGURE 4 - STROBE OR SELECT TO INTERRUPT OUTPUT

/'V

_ _---J

---I

tZH

I

---!

I--

-----=-:_-.J - ' : : V

IHIGHSTORED) _ _ _

--t

r

C

0.5 V

tZL

t

:

--l

I.I

DATA OUTPUT
(LOW STORED)

tHZ

--- ::v

l,------~,--""'~

!

DATA OUTPUT

\~,~

I

- - - - - - - - . , , - - - - • 45 V
.,.5V

F

~-----------~

CO.

5V

+

FIGURE 5 - SELECT TO DATA OUTPUT

1075

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TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER

TTL
MSI

BULLETIN NO. DL-S 7612475, OCTOBER 1976

•

Designed to be Interchangeable With Intel 8224

•

Single-Chip Clock Driver With
Self-Contained Oscillator

•

J OR N PACKAGE
(TOP VIEW)

Specifically Designed to Drive
All 8080A Microprocessors
XTAL

XTAL

TANK

QSC

61

02

description
This clock generator is capable of driving 12-volt
lines. It contains a crystal-controlled oscillator, a
divide-by-nine clock phase generator, two high-level
drivers, and auxiliary circuitry.

RESET

The internal oscillator is designed to operate with
fundamental-mode crystals, or with overtone-mode
crystals when using a parallel-tuned circuit connected
..1.. . . . . . . . . L._

I.U

Lilt:

1...
lalll'-

.&. _ _

1
LeIIIIlIIOI,

..... :_
1-1111

.&. _ _ _ : _ _

1')
Iv.

T ..... _
Ille

..... __ :11 ... + __
V;, .... IIIQlVI

...... + ........ +
VUq.JUl

appears on pin 12 and drives the divide-by-nine
counter. The 79 clock phase generator output
consists of phases cf>2 for driving MOS inputs and
cf>2 TTL for driving TTL. Three other TTL outputs,
status strobe, reset, and ready, are coupled to the
divide-by-nine counter. A sync input from the SOSOA
is AND'ed with cf>1A to produce the status strobe.
The power-on reset also generates the status strobe
signal through an output NOR gate. The reset input
works on a voltage-level basis by use of a Schmitt

RESET RESIN

RDYIN

READY SYNC

OUT

iNPUT

62

STSTS

TTL

OUT

GND

trigger. A rising voltage waveform is triggered at a
particular voltage. A synchronized ready output is
obtained by clocking with a cf>2 signal.
The SN74LS424 is characterized for operation over
the temperature range of DoC to 70°C.

functional block diagram
XTAL 1

•

(15)

(12)

OSC

(11)

qil

(10)

-___....:.(6;:.:.)_qi2TTL
qi2D qilA

STATUS
STROBE
STSTB

~~~JT-(~5~)-----+------~__~
RESET
INPUT
RESIN

>-__----(;...1.;...) RESET
READY
INPUT
RDYIN

~---~(~4)~READY

1076

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7-507

TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER
schematics of inputs and outputs
EQUIVALENT OF RESET
AND SYNC INPUTS

EQUIVALENT OF XTAL 1 AND
XTAL 2 NODES

TYPICAL OF 1, t/>2

3.1
0.45

VOO = 12.6 V. VI = 5.25 V
VOO=12.6V. VI:O.4V

ci rcu it cu rrent §

3.9

0.2

VOO = 12.6V, VI = 7V

Short-circuit

3.6
2.4

025

Vee: 5.25 V,

lOS

10.4

10l: 15mA
Vee: 5.25 V,

maximum input voltage

-1.5
9.4

10l :2.5mA

High-level input current

II

-1

li--1SmA

IOH--1mA

t/>1, t/>2, reset,
low-level output voltage

11- -5 mA

10H: -100.uA

V
V

0.25
Vee: 4.75 V,

t/>1,t/>2
Ready, reset

UNIT

V

2

Others

Val

TYP* MAX

2.6

Ali others

Input clamp voltage

High-level output voltage

MIN

I

*AII typical values are at Vee: 5 V. Voo = 12 V. T A: 25°C.
§ Not more than one output should be shorted at a time. t/>1 and t/>2 do not have short-circuit protection.
NOTE 2: ICC and 100 are measured with outputs disabled and open.

1076

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7-509

TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER
switching characteristics, Vee

= 5 V, V DD = 12 V, T A = 25°e, see figure 1

PARAMETER

TEST CONDITIONS

TYP

MIN

MAX

f max

Maximum oscillator frequency

tc(osc)

Oscillator cycle time

tw(cp1)

Pulse width, cp1 high

t w (cp2)

Pulse width, cp2 high

tw(SS)

Pulse width, status strobe low

tr(cp)

Rise time, clock outputs

CL = 30 pF,

R1 = 300 n,

20

tf(cp)

Fall time, clock outputs

R2 = 600 n,

See Figure 3

20

tcp1L,cp2H

Delay time, cp1 low to cp2 high

tcp2L,cp1H

Delay time, cp2 low to cp1 high

t¢lH,q,2H

27

MHz
ns

.!2:
9
cp1 and cp2:
CL = 20 pF to 110 pF,

Delay time, q,1 high to q,2 high

2tc _ 20
9

ns

~-35

ns

.!£.- 15

ns

9

See Figure 2

9

cp2TTL:

R1=2kn,

ns
ns

0

ns

2tc _ 14
9

ns

Status Strobe:
CL=15pF,
R2=4kn,

UNIT

See Figure 3

~
9

2tc + 20

9

ns

OSC, Ready, Reset:
tq,2,cp2T
tq,2H,SSL
tRV, q,2L

R1 = 2 kn,

R2=4kn,

See Figure 3

-5

15

ns

~-30

6t c

ns

Delay time, ready or reset

~-25

S-

9

ns

9

output valid to phase 2 low

EXAMPLE: switching times for fosc

= 20 MHz (tc(¢1) = tc(¢2} = 450 ns)

PARAMETER

I

CL=10pF,

Delay time, q,2 high to
status strobe low

Delay time, cp2 to cp2 TTL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fosc

Oscillator frequency

20

MHz

tc(osc)

Oscillator cycle time

50

ns

tw(¢l)

Pulse width, q,1 high

80

ns

t w (q,2)

Pulse width, cp2 high

215

ns

tw(SS)

Pulse width, status strobe

35

ns

t<1>lL,cp2H

Delay time, <1>1 low to <1>2 high

tq,2L,q,lH

Delay time, q,2 low to q,1 high

tcp1H,q,2H

Delay time, q,1 high to q,2 high

Same as above

Delay time, q,2 high to
tcp2H,SSL
tRV,cp2L

status strobe low
Delay time, ready or reset

I

0

ns

86

ns

100

120

ns

270

300

ns

175

output valid to cp2 low

ns

1076

7-510

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TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER
PARAMETER MEASUREMENT INFORMATION
tc(OSCl-r----1
OSC

if
!

ct>2TTL _ _ _ _ _ _ _ _ _ _-+l

\

SYNC
(FROM 8080A)

READY

I

\"'_1.5_V
_ _ _ _ _ _ _ _ _ __

I

i /

\

1I

I'
I_

~tw(SS)
STATUS
STROBE

I

1.5 V

tct>2H,SSL

I

1

I

~'.5V
--.ll.-tsu(RDYINl
I
th(RDYINl

t-

~~~~
-,
I

I

1,_----

'.5V~'.5V

I

-I

-~5~±- _ _ _ _ _ _ _ _ _ 1l.;V--- _
-r
- -- - ---- ------_
..:J!,;;._ _ _ _ _
-+I______________
~

RESET
INPUT

r

tRV ,ct>2L----1

- - - -- - - - - - - -- - ~~------+I--------------READY OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _'_.5_V....'l.. _____ +-____________ _
I'---tRV, ct>2L---!
RESET OUTPUT ---------------~~~I_,~.5_V_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

I

NOTE: Transistion times, pulse widths, and interpulse relationships are distorted in this diagram in order to define various intervals, See Figure 5
for correct relative relationships,

VOLTAGE WAVEFORMS
FIGURE 1

Vcc
OUTPUT
UNDER
TEST

Rl

~
CL

R2

LOAD CIRCUIT

LOAD CIRCUIT

FIGURE 2

FIGURE 3

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7-511

TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER
TYPICAL APPLICATION DATA
The 'LS424 is a single-chip clock generator/driver for 8080A CPU's, furnishing three clocks (1, 2 and 2 TTLl. status
strobe, reset, and ready signals. The 'LS424 contains a crystal-controlled oscillator, a divide-by-nine counter, two
high-level drivers, and several auxiliary logic functions. Figure 4 is a functional block diagram of the SN74LS424.
Figure 5 shows the relationship between 1, 2, and the oscillator frequency period.

oscillator
A high order of clock frequency stability is provided by use of an external quartz crystal to set the oscillator frequency
which is nine times the operating frequency of the 8080A. The quartz crystal is operated in a series·resonant mode. A
fundamental-mode crystal requires no auxiliary circuitry, but an overtone-mode crystal requires an ac-coupled
parallel-resonant circuit to be connected to the tank connection (pin 13). The "parallel-resonant circuit, tuned to the
oscillator frequency, compensates for the lower Q of the overtone"-mode crystal. The required size of the circuit
components can be calculated from f = 1/2rrv'LC where f is the oscillator frequency, L is inductance value, and C is
capacitance value. Figure 6 shows an ac-coupled parallel-tuned circuit used with the SN74 LS424.

clock phase generator
The divide-by-nine clock phase generator contains a divide-by-nine counter, logic required to shape the clock pulses as
shown under parameter measurement information, gates and flip-flops to generate auxiliary signals, and output drivers.
The divide-by-nine counter waveforms are combined with gates to form a 1 pulse with a width of two periods of the
oscillator frequency, repeating at intervals of nine oscillator periods. Similarly, the 2 pulse, having a width of five
oscillator frequency periods, is formed lagging the 1 pulse by two oscillator periods.
1 and 2 outputs are provided by high-level drivers for direct connection to the 8080A CPU. 2 TTL is derived in a
manner similar to 1 and 2, but the output driver output is at TTL voltage levels. The 2 TTL pulse width is the same
as 2. A 2 TTL application is clocking in direct memory access activities. Figure shows the 'LS424 connected to an
8080A, quartz crystal, and LC circuits.

status strobe
The 8080A CPU puts status information on its data bus at the beginning of each machine cycle that defines the nature
of the machine operation for that cycle. A sync signal from the 8080A is gated by an internal timing signal (lA) and
becomes a status strobe to notify system components that the status data is present on 8080A status output lines. The
status strobe signal connects directly to the 'S428 system controller.

I

The status strobe signal is alternatively generated by the reset input. An external RC series network connected to VCC
and the reset input will provide a rising voltage waveform when VCC is turned on. An internal Schmitt trigger circuit
generates a sharp, fast-rising waveform when the reset input reaches a particular voltage value. The Schmitt trigger is
connected to the D input of a flip-flop clocked by 2D. When power is turned on, the combination of internal and
external circuitry will produce a status strobe signal. A manual reset switch can be connected as in figure 6 to the RC
network to produce reset and status strobe signals for the 8080A.
The ready signal indicates to the 8080A that an external device has completed transfer of data to or from the data bus.
A ready signal input to the 'LS424 drives the D input of a flip-flop clocked by an internal 2D signal. Timing
requirements of the 8080A machine cycle are met by the synchronization with the system clocks provided by the
flip-flop. This implementation saves about 200 ns of system time during memory cycles (as contrasted with generating a
"wait request" within the 8080A's MOS logic) since the bipolar logic of the 'LS424 has much less delay,

1076

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TYPE SN74LS424 (TIM8224)
TWO-PHASE CLOCK GENERATOR/DRIVER
TYPICAL APPLICATION DATA

Qil
Qi2

1

qi2TTL

1 UNIT=fosc

cp1

STATUS
STROBE
STSTB

cp2
Example: 8080A cycle

(1)

RESET

ns)

FIGURE 5

QUARTZ
CRYSTAL

0

r-- -- --,
I

ns)

= 250 ns (5 X 50 ns)
= 100 ns (2 X 50

tcp2L,cp1 H

READY

FIGURE 4

I

ns

= 50

tw\qjij = 100~:; (2 X 50 :--::;)
t w (cp2)

(4)

= 450

fosc: 20 MHz (unit

L:
C

I

I

XTAL2 XTAL 1
(14)
(15)

I
IL C~C
_ _ _ _ _ _ ..JI

ICs'X'

(11)

¢1

(12)
OSC
¢2TTL

(10) ¢2

(15)

(6)

READY (3)
(RDYIN)

(4) READY
(23)

'LS424

8080A
CPU

VCC

r

MANUAL::::r::;
SWITCH

(1) RESET(12)

R
RESET (2)

(5) SYNC (19)

(RESIN)

l'

(7)

STATUS
STROBE
(STSTB)

FIGURE 6

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7-513

TYPES SN74S42B(TIMB22B). SN74S43B(TIMB23B)
CONTROLLER AND BUS DRIVER FOR BOBOA SYSTEMS

TTL
LSI

BULLETIN NO. DL-S 7612468, OCTOBER 1976

•

N PACKAGE

Designed to Be Interchangeable with Intel 8228
and 8238

(TOP VIEW)

PIN DESIGNATIONS
DESIGNATION
DO thru D7
DBO thru DB7

PIN NOS.

FUNCTION

15, 17, 12, 10, BIDIRECTIONAL DATA PORT
6, 19.21,8

(TO TMS 8080A)

13. 16. 11.9. BIDIRECTIONAL DATA PORT
5, 18. 20, 7 (TO SYSTEM BUS)

I/OR

25

10/w

27

MEMR

24

MEMW

26

DBIN

4

READ OUTPUT TO I/O
(ACTIVE LOW)
WRITE OUTPUT TO I/O

V

BIDIRECTlONA.L DATA PORTS

(ACTIVE LOW)

logic: see description

READ OUTPUT TO MEMORY
(ACTIVE LOW)
WRITE OUTPUT TO MEMORY

functional block diagram

(ACTIVE LOW)
INPUT TO INDICATE
TMS 8080A IS IN INPUT

INTA

23

2

OUTPUT (ACTIVE LOW)

i

TM~/~080A

INPUT (ACTIVE HIGH)
INPUT TO INDICATE

3

TMS 8080A IS IN WRITE
SYSTEM DATA PORT

22

DB2

DB3 SY~JoEM
DB4 DATA PORT

D5

DB5

D6
D7

DB6
DB7

STATUS (1)
STROBE
INPUT

MODE (ACTIVE LOW)
BUS EN

DBl

D2

D3
DATA PORT D4

FROM TMS 8080A
WR

DB~

Dl

INTERRUPT ACKNOWLEDGE
HOLD ACKNOWLEDGE

HLDA

~

DO

MODE (ACTIVE HIGH)

ENABLE INPUT (ACTIVE
LOW)

I

SYNCHRONIZING STATUS

STsTB

1

STROBE INPUT FROM
SN74LS424 (TIM8224)

I

VCC

28

GND

14

SUPPLY VOLTAGE (5 V)

vcc = PIN (281. GND = PIN (14)

IGROUND

description
These monolithic Schottky-clamped TTL system controllers are designed specifically to provide bus-driving and
peripheral-control capabilities for interfacing memory and I/O devices with the 8080A in small to medium-large microcomputer systems.
A bidirectional eight-bit parallel bus driver is provided that isolates the 8080A bus from the memory and I/O data bus
allowing the system designed to utilize cost-effective memory and peripheral devices while obtaining the maximum
efficiency from the microprocessor. The TTL system drivers also provide increased fan-out with a lower impedance
that enhances noise margins on the system bus.
Implementation of the status latches and control decoding array of the SN74S428/SN74S438 provides for using
either a single-level interrupt vector RST7 for small systems, or multiple-byte call instructions for systems needing
unlimited interrupt levels.

TENTATIVE DATA SHEET

7·514

This document provides tentative information
on a new product. Texas Instruments reserves
the right to change specifications for this
product in any manner without notice.

T

EXAS

I

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TYPES SN74S428(TIM8228), SN74S438(TIM8238)
CONTROLLER AND BUS DRIVER FOR 8D8DA SYSTEMS
description (continued)
With respect to the system clocks, the SN74S438 is configured to generate an advanced response for I/O or memory
write output signals to further simplify peripheral control implementation of complex systems. See Figure 3.
8-bit parrallel bus transceiver
The 8-bit parallel bus transceiver buffers the 8080A data bus from the memory and I/O system bus by providing
one port (DO through 07) to interface with the 8080A and another port (DBO through DB7) to interface with the
system devices. The 8080A side of the transceiver is designed specifically to interface with the microprocessor data
bus ensuring not only that the processor output drive capabilities are adequate, but also that the inputs are driven
with enhanced noise margins. The system bus side features high fan-out buffers designed to drive a number of system
devices simultaneously and directly. The system port is rated to sink ten milliamperes of current and to source one
milliampere of current at standard low-threshold voltage levels.
Status lines from the 8080A instruction-status decoder and the system bus enable input (BUSEN) provide complete
transceiver directional and enable control to ensure integrity of both the processor data and the system bus data.
status latches
During the beginning of each machine cycle, the six status latches receive status information from the 8080A data
bus indicating the type of operation that will be performed. When the STsTB input goes low, the latches store the
status data and generate the signals needed to enable and sequence the memory and I/O control outputs. The status
words and types of machine cycles are enumerated in Table A.
TABLE A - STATUS WORDS
80SOA

STATUS
WORD

TV!>E OF

STATUS OUTPUT

MACHINE CYCLE

'S4281'S438
COMMAND

DO

01

02

03

D4

05

D6

07

1

L

H

L

L

L

H

L

H

I nstruction fetch

MEMR

2
3

L

H

L

L

L

L

L

H

Memory read

MEMR

L

L

L

L

L

L

L

L

Memory write

MEMW

4

L

H

H

L

L

L

L

H

Stack read

MEMR

5

L

L

H

L

L

L

L

L

Stack write

riiiEii.1W

6

L

H

L

L

L

L

H

L

Input read

IIOR

7

L

L

L

L

H

L

L

L

Output write

I/OW

8
9

H

H

L

L

L

H

L

L

Interrupt acknowledge

iNTA

L

H

L

H

L

L

L

H

Halt acknowledge

NONE

H

H

L

H

L

H

L

L

Interrupt acknowledge at halt

INTA

~

::.:

«
f-

f-

0..

c:
:2
W
:2

10

«
f~

U

~

CIl

-l

J:

:;)

0

i

~

GENERATED

I

STATUS INFORMATION

decoding array
The decoding array receives enabling commands from the status latches and sequencing commands from the 8080A
and generates memory and I/O read/write commands and an interrupt acknowledgement.

1076

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TYPES SN74S428(TIM8228), SN74S438(TIM8238)
CONTROLLER AND BUS DRIVER FOR 8080A SYSTEMS
description (continued)
The read commands (MEM"R, I/OR) and the interrupt acknowledgement (lNTA) are derived from the status bit(s)

and the data bus input mode (DBIN) signal. The write commands (M"EMW, i/OW) are derived from the status bit(s)
and the write mode (WR) signal. (See Table A.) All control commands are active low to simplify interfacing with
memory and I/O controllers.

The interrupt acknowledgement (lNTA) command output is actually a dual function pin. As an output, its function
is to provide the ii\i'TA command to the memory and I/O peripherals as decoded from the status inputs and latches.
When CALL is used as an interrupt instruction, the SN74S428/SN74S428 generates the proper sequence of control
signals. Additionally, the terminal includes high·threshold decoding logic that permits it to be biased through a onekilohm series resistor to the 12-volt supply to implement an interrupt structure that automatically inserts an RST7
instruction on the bus when the DBIN input is active and an interrupt is acknowledged. This capability provides a
single·level interrupt vector with minimal hardware.
The asynchronous bus enable (BUSEN) input to the decoding array is a control signal that protects the system bus.
The system bus can be accessed and driven·from the SN74S428/SN74S428 controller only when the BOSEN'input
is at a low voltage level.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
... 7 V
7V
O°C to 70°C
-65°C to 150°C

Supply voltage, VCC (see Note 1)
Input voltage . . . . . . . .
Operating free·air temperature range
Storage temperature range
NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
Supply voltage,

I

Vee

MIN

NOM

MAX

4.75

5

5.25

V

-10
-1

jlA

DO thru 07

High·level output current, IOH

All othel1i
DO thru 07

Low-level output current, IOL

All othel1i

Status strobe pulse width, tw(STSTBi (see Figure 3;
Status inputs DO thru 07

Setup time, tsu (see Figure 3)

22

Status inputs DO thru 07

8
10
5

System bus inputs to HLOA

20

System bus inputs to HLOA

Hold time, th (see Figure 3)

,

2
10

Operating free-air temperature, T A

0

UNIT

rnA
rnA
ns
ns
ns

70

°e

1076

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TEXAS INCORPORATED
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•

DALLAS, TEXAS 75222

TYPES SN74S428(TIM8228), SN74S438(TIM8238)
CONTROLLER AND BUS DRIVER FOR 8080A SYSTEMS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

00 thru 07

10ZL

high-level voltage applied
output current,

low-level voltage applied
INTA
00 thru 07

High-level input current

IIH

All other inputs

I u2 or u6

I

Low-level input current

IlL

VCC =MIN,

II = -5 rnA

VCC =MIN,

VIH-2V,

3.6

10H = MAX

2.4

All other outputs VIL = 0.8 V,

Low-level output voltage

Off~te

TYP:j:

MAX

2

Off-51:ate output current,
10ZH

MIN

STSTB

VCC = MIN,

VIH=2V,

VIL = 0.8 V,

10L = MAX

VCC =MAX,

UNIT
V

0.8

V

-1

V

4

V
0.45

V

Vo =5.25 V

100

IJA

VCC =MAX,

Vo = 0.45 V

-100

JJA

Vee= MIN,

See Figure 1

5

rnA

VCC = MAX,

VI =5.25 V

IVCC = MAX,

VI =0.45 V

20
100

JJA

-/bU

-500

All other inputs

JJA

I

-250

lOS

Short·drcuit output current§

VCC = MAX

ICC

Supply current

VCC =MAX

-15
140

-90

rnA

190

rnA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
+AII typical values are at Vee = 5 V, T A = 25°e.
§ Not more than one output should be shorted at a time.

switching characteristics, Vee

=5 V, TA =25°e, see figure 3

FROM

TO

(INPUT)

(OUTPUT)

tpo

DO thru 07

DBO thru OB7

tPD

DBO thru DB7

DO thru D7

PARAMETER1I

STSTB

tPHL

TEST CONDITIONS
CL = 100 pF,

See Figure 2

CL = 25pF,

See Figure 2

MIN
5

TYP

MAX

UNIT

40

ns

30

ns

INTA, '"i7(5R, MEMR,

mJiJ, MEiiiiW
CL = 100pF,

See Figure 2

20

60

ns

5

45

ns

WR

1f(YoN,MEMW

tpLH

DBIN

INTA, i70R, MEMR

30

ns

tpLH

HLDA

INTA, i7QR, MEMR

25

ns

45

ns

tpo

tpZX

DBIN

DO thru D7

tpxz

DBIN

DO thru D7

tpZX

STSTB, BOSEfij

DBO thru DB7

tpXZ

i3Om'l

DBO thru DB7

CL=25pF,
CL = 100pF,

See Figure 2
See Figure 2

45

ns

30

ns

30

ns

•

11 tp 0 == propagation delay time
tpH L
tpLH
tpZX
tpXZ

== propagation delay time, hiltJ-to-low-level output
== propagation delay time, low-to-high-Ievel output
== output enable time from hiltJ-impedance state
== output disable time to high-impedance state

1076

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TYPES SN74S428(TIM8228), SN74S438{TIM8238)
CONTROLLER AND BUS DRIVER FOR 8080A SYSTEMS
PARAMETER MEASUREMENT INFORMATION

Vee

!::

OUTPUT

'iV'kn

11

UNDER TEST

TO INTA--.J
OUTPUT . - II

Tel

i

-=-

FIGURE 1-iN"i'A INPUT CURRENT
TEST CIRCUIT

R2

S2

FIGURE 2-SWITCHING CHARACTERISTICS
LOAD CI RCUIT

C~::e~I{¢'
¢2

-_
' _----,.Je-tw--lr-_ _ _ _ _ _ _ _ _ _ _ _ _
- _-_-_

'i

STsTa
INPUT

....

ST~~,~~TS

~'.5 ~

TMS8080A

I

DO'h", 07

:

I

I

~------------------

'1..u.

V
'--------------------

ill

.1r-----"""'~

! I

OBIN
INPUT

I

I

r.,.5V

1\1.5 V

mTA,mlR,~--------~I~-~I----J:
OUTPUTS

•

:

~.5Y

I

'PHL...l

1.-1

I

f1.5V
t--------------

t!~~LH

I

:

I T,·5V

I
l'

I

I

I

:
1
mTA,mlR,MEMR--------~lh\ I
I

OURINGHLOA

i~~-l-H~-,------------

I
1

:
I

:

HLDA INPUT

~

vJ{

H

..J.--..t6~t~-t

,.

r1

5v

, I ...1r=~----------

i

I - - I - - j - - =I I ]SVSTEMBUS I N P U T - - - - - - - ' '... -=iiI4'I'h
I ....
~-------------

DU~'NG~EAD
D80tb",OB1

O~':~u':,;AD

iVA INPUT

3V

I

'O.8V

'.5V

I

------------

l V
0.8

vi

------------

:I
~~O
1.5~-I~-=Y~~~--- , ....

,:svt

('S428onlYl

OUTPUT

~ ..-::,'' ' PO''--_ __

'5_V_ _ _ _....Jf'·5V

I
TMS 8080A BUS INPUT

V

I

__________

-1.

~'.5V

--'*. .

,pzx~ ; ; V

SYSTEM BUS OUTPUT

Dg~~:~~~E

~

i.=::=::ii~0:·

I

I/C1#/ORMEMW

DU:::';r:~~TE

!

1.5 V

---------t--+.
I
I
--------t--r----I
! I
~zx~HL--4--.t l

TMS BOBOA BUS OUTPUT

-

-

_ _ _ -,''"''PO::....-_ _ _ _ _ _ _ _ _ __

- - - - - - - - - ' ' . j . . - ' ' 0..:...8V'--_ _ _ _

iiUsEN

'.5_V_ _ _ _ _ _ _ _ _ _ __

1.,.5 V
I ....

.J,.5V

-----J~

INPUT

SYSTEM BUS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L _ ; t l V
OUTPUTS
OBO 'hno OB7

I

~0.8

I--tpzx-,

v

I

3Vt,_ _ _ _ _ _ _ _ _ _ _ _ _

I 0.8

v-JL

F=t!--tpxz

NOTE A: Advanced response of I/OW or MEMW for the SN74S438 is indicated by the dashed line.

FIGURE 3-VOL TAGE WAVEFORMS

1076

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POST OFFICE BOX 5012

•

DALL.AS. TEXAS 75222

TYPES SN74S428(TIM8228), SN74S438(TIM8238)
CONTROLLER AND BUS DRIVER FOR 8080A SYSTEMS
TYPICAL APPLICATION DATA

VOO (12V)
VCC

-

(5V)

V BB (-5 V)
(16)

(9)

~

%)

SN74LS424

4;1

(11)

XT AL (TIM8224)
4>2

, .......
TANK-----..9 TANK

USC

1(11)

VOO

VCC

V BB

.

L

VCC

(22) ;;1

4>2

~

q,2TTL

SYNC

RESIN

--A

RESIN

RESET

ROYIN

~

ROYIN

READY

01
02
03

~

(9)
(8)
(7)

041'~':

CLOCK

,?

05 (4)

~IOSC GE~i;~~~OR

oi>2TTL

VCC

DO (10)
8080A
CPU

(15)

(10)

I,~,

(28)

VOO
(15)
DO
.. (17)
01
(12)
02
(10)
03
r

(19)

(5)

~

07 (6)

....-

I~\

(19)05

OB5

(18)

(21) 06

DB';

(20)....

(8)

BIDIRECTIONAL

07

.

~

~:J

... --.. OB~l
OB4r'u,-r--:-~~lf3 0:.1:
(:~)

OBl

(7)

~

OB5

....

~

~

DB6
OB7

f.--------

SYNC

~

(13)

OBl (16)
OB2

: .u, 104
:

(TlM82281
TIM8238)

DB3

'e'

D6 (5) .....

DBO

'54281'5438

CONTROL

STSTB
GNO

(12)

(1)
(4)

..

(23)

~

~,

RESET

OBIN (17)
(18)

READY

HL:: i"'(21)

«43:»_ OBIN

~

r

(2)-

:~OA

D~~':~G MEMR
INTA
(23)
IV (24)

22) BUSEN
:---v STSTB

~

M~ '""(25)

J!lr, __

WAIT

BUSEN

}
INTA

~(~26~).....- - :~::

I/OR U'"(27)-r
I/OW ""

I/OR

CONTROL
BUS

I/OR

GNO

J¥)

~4)
AO
Al
A2

(13)
SYSTEM OMA REQUEST---+--+"":':'::, HOLD

A3

..

A4

(14)
SYSTEM INTERRUPT REQUEST---+-....-'-'-"I INT

AS
A6

(16)
INTERRUPT ENABLE---+-. . ....!.!.::!.f INTE

(25)

(29) ::
(30)

..

(31)
(32) ::
(33)

::

(35)

..

(1)

..

(40)
(37)

..

(38)
A13
(39)
A14
(38)
A15

..

A7
(34)
A8

~

AO

(26) ..
(27) ::

A9
Al0
All
A12

Al
A2
A3
A4
AS
A6
A7
A8

A9
Al0
All
A12

ADDRESS
BUS

•

A13
A14
A15

Vss

~)

FIGURE 4-SYSTEM tNTERFACING WITH CENTRAL PROCESSING UNIT

1076

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7-519

TYPES SN54490, SN54LS490, SN14490, SN14LS490
DUAL 4-81T DECADE COUNTERS

TTL
MSI

BULLETIN NO. DL-S 7612089, OCTOBER 1976

•

Dual Versions of Popular SN5490A, SN54LS90,
SN7490A, and SN74LS90 Counters

•

Individual Clock, Direct Clear, and Set-to-9
I nputs for Each Decade Counter

SN54490 ... J OR W PACKAGE
SN74490 •.. J OR N PACKAGE
(TOP VIEW)

20A

2

2

CLOCK CLEAR

•

Dual Counters Can Significantly Improve
System Densities as Package Count Can
Be Reduced by 50%

•

Maximum Count Frequency •.. 35 MHz
Typical

•

Buffered Outputs Reduce Possibility of
Collector Commutation
1

1

2

OUTPUTS

~~~9~

10A

CLOCK CLEAR

description

OUT·
PUT

OUT·
PUT

positive logic: High input to clear resets all fqur outputs low;

Each of these monolithic circuits contains eight
high input to set-to-9 sets 0A and 00 high, Os
master-slave flip-flops and additional gating to impleand 0c low.
ment two individual 4-bit decade counters in a single
package. Each decade counter has individual clock,
clear, and set-to-9 inputs. BCD count sequences of any length up to divide-by-l00 may be implemented with a single
'490 or 'LS490. Buffering on each output is provided to ensure that susceptibility to collector cummutation is
reduced significantly. All inputs are diode-clamped to reduce the effects of line ringing. The counters have
parallel outputs from each counter stage so that submultiples of the input count frequency are available for system
timing signals.

•

The SN54490 and SN54LS490 are characterized for operation over the full military temperature range of _55°C to
125°C; the SN74490 and SN74LS490 are characterized for use in industrial systems operating from O°C to 70°C .

BCD COUNT SEQUENCE
(EACH COUNTER)
OUTPUT

CLEARISET-TO·9

Qo Qc Qs QA

FUNCTION TABLE

COUNT

0

L

L

L

L

1

L

L

H

2

L
I L

L

H

LI

3

L

L

H

H

4

L .H

L

L

5

L

H

L

H

6

L

H

H

L
H

7

L

H

H

8

H

L

L

L

9

H

L

L

H

(EACH COUNTER)
INPUTS

OUTPUTS

CLEAR SET-TQ-9 QA QB
H
L
L
L

L

H

L
H

= high

H

L

= low

level

L
level,

Oc

QD

L

L

L

H

COUNT
L

1076

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TYPES SN54490, SN54LS490, SN74490, SN74LS90
DUAL 4-81T DECADE COUNTERS
schematics of inputs and outputs

-

'490

EQUIVALENT OF EACH INPUT
vee

o
Req

INPUT

TYPICAL OF ALL OUTPUTS
--_-vee

-OUTPUT

INPUT

Req NOM

CLOCK
CLEAR, SET -TO-S

3 kH
8 k1!

'LS490
EQUIVALENT OF EACH
CLOCK INPUT

EQUIVALENT OF EACH
CLEAR AND SET-TO-NINE INPUT

TYPICAL OF ALL OUTPUTS
----_vee

t--

v e e - -......

18kHNOM

functional block diagram (each counter)

I
(5,11)

OUTPUT

DB

(6,10)

OUTPUT

Oc

OUTPUT

DD

1076

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TYPES SN54490, SN74490
DUAL 4-81T DECADE COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
.....
Input voltage . . . . . . . . . . . . .
Operating free-air temperature range: SN54490
SN74490
Storage temperature range

. . . . . 7V
. . . . 5.5V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54490
Supply voltage, VCC

MIN

NOM

4.5

5

High-level output current, 10H

SN74490
MAX

MIN

NOM

5.5

4.75

5

-800

Low-level output current, 10L

16

Count frequency, f count

0

25

Pulse width, tw (any input)

20

Operating free-air temperature, T A

5.25

V
J1.A

16

mA

25

MHz
ns

25~

-55

125

0

UNIT

-800

20

25~

Clear or set-to-9 inactive-state setup time, tsu

~ The

0

MAX

70

ns
°c

arrow indicates that the falling edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONSt

PARAMETER

I

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

II

Input current at maximum input voltage

IIH

High-level input current

lOS

Short-circuit output current§

ICC

Supply current

Vee; MIN,

II; -12mA

VCC - MIN,

VIH - 2V,

,VIL;0.8V, 10H ; -800 J.lA

VOL Low-level output voltage

Low-level input current

TYP:j: MAX

Vee; MIN,

VIH; 2 V,

VIL;0.8V

IOL; 16mA

!

2.4

I

Clock
Clear, set-to-9
Clock

Vce; MAX, VI
Vce; MAX, VI

0.2

V
V

0.4

40

80
-1

= 0.4 V

ISN54490

V

-1.5

1

= 2.4 V

= MAX ISN74490
Vee = MAX. See Note 2

Vee

0.8

3.4

Vce; MAX, VI; 5.5 V
Clear, set-to-9

UNIT
V

2

VOH High-level output voltage

IlL

MIN

-3.2
-20

-57

-18

-57
45

70

V
mA
J1.A
mA
mA
mA

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at Vee; 5 V, T A ; 25°C.
§Not more than one output should be shorted at a time.
NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.

1076

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POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TYPES SN54490, SN74490
DUAL 4-81T DECADE COUNTERS
switching characteristics, Vee = 5 V, TA
PARAMETER~
f max

tpLH

TO

(INPUT)

(OUTPUT)

Clock

°A

Clock

°A

Clock

°8,°0

tpHL
tpLH

tpLH
tpHL

25

35

CL=15pF,

RL = 400

n,

MAX UNIT
MHz

13

20

24

39
39

54

36

54

24

39

°A,OO

24

39

°8,OC

20

36

Any

Set-to-9

20

26

°c

Clear

tpHL
~fmax

TYP

32

Clock

tpLH

MIN

See Figure 1 and Note 3

tPHL
tpHL

TEST CONDITIONS

12

tpHL
tPLH

=25°e

FROM

ns
ns
ns
ns
ns

== maximum count frequency
== propagation delay time, low-to-high-Ievel output
== propagation delay time, high-to-Iow-Ievel output

NOTE 3: Load circuit is shown on page 3-10.

S~~~~~9 ~~;---------~s---- - - ~S- - - - - - - - - : :
~

INPUT

I

_..;...____....J:

I+-

I

i

CLOCK
INPUT

I

I
l

I 1.5V

I

~tPHL

--:-':
I

\

: . . - - . : - tPHL

I
1
--1-' 1

~

1.5V

I

\1.5V

~ tPHL

I

I

H

\1.5V

tPLH-Meosure
attn+4

-1"---'1
*-1.5V

:

~tPLH

I

I

:

\i.I

if

\

4

t PHL

i

11.5v

J.ri

---1'

-

/1.SV

--J...-....,
I

r'

1

(1.5V

! ~
~I
I
I

r

II

:

--

~

VOH

tpHL-Measureatt n +10

~---

\..--------~5t-f---------'

VOL

VOL

~

/ ' 1.5V

VOH

tpHL -Measure at tn+8

I

~

l

' \ 1.5V

VvOoHL

~ tpHL -Measure
I
I
ottn+4

I

tpLH-Measureatt n +8

Ir -

1.5V

~"'f----..;..--1

1"'------'
OUTPUTQO

tpHL -Measure
attn+2

tPLH-Meosure~
ottn+2
I

I~tPHL
I

~

I

-,-, I

\- 1.5V

I

OUTPUTOc

pi
I
,

' \ 1.5V

tPLH-Meosure
r
attn+l

ov

1

I

~tPHL

:

ov

~I
~----3\1
1.5V
1.5V
1.5V

~

:

,.-_......:_-"

jJ

H
~twlcIOCkl.,

-+J

:

I

1

OUTPUTQB

S\

I

tsu

__~_ _ _ _ _~I_ _ __ J

I+-+t- tPLH
OUTPUTQA

_I

tsu

F\l-:V---!-------------------- 3V

CLEAR

VOH

1.5V
VOL

VOLTAGE WAVEFORMS
NOTES:

A. Input pulses are supplied by a generator having the following characteristics: tr .;;; 5 ns, tf .;;; 5 ns, PRR
= 50%, Zout "" 50 ohms.

=

1 MHz, duty cycle

FIGURE 1

1076

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-523

TYPES SN54LS490 SN74LS490
DUAL 4-81T DECADE COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc (see Note 1)
Clear and set-to-9 input voltage
Clock input voltage . . . . . .
Operating free-air temperature range: SN54LS490
SN74LS490
Storage temperature range

. 7V
. 7V

5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

recommended operating conditions
SN54LS490
MIN

NOM

4.5

Supply voltage, V CC

MIN

NOM

5.5

4.75

5

5

High-Ie\lel output current, 10H

SN74LS490

MAX

5.25

-400

-400

low-Ie\lel output current, 10l

MAX

4
0

Count frequency, fcount

25

0

Pulse width, tw (any input I

20

20

Clear or set-t0-9 inactive-state setup time, tsu

25.

25.

Operating free-air temperature, T A

-55

125

UNIT
V
IJA

8

mA

25

MHz
ns
ns

0

70

°c

• The arrow indicates that the falling edge of the clock pulse is used for reference.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

II

VIH

High-level input voltage

Vil

low-level input voltage

VIK

Input clamp voltage

VOH

TEST CONDITIONSt

High-level output voltage

VCC =MIN,

II =-1 mA

VCC = MIN,

VIH = 2 V,

2.5

Vil = Vilmax
Low-level output vOltage

0.25

1101.>4 mA

TYPt

MAX

UNIT
V

0.7

0.8

V

-1.5

-1.5

V

3.4

2.7
0.4

I

V

3.4
0.25

OA

0.35

0.5

V

Clear,
I nput current at
set-to-9 VCC = MAX,
maximum input voltage I - - Clock

IQ1. =8 mA
VI =7 V

0.1

0.1

VI = 5.5 V

0.2

0.2

High-level input current set-to-9 VCC = MAX,
I Clock

VI=2.7V

Clear,
IlL

MIN
2

Clear,
IIH

SN74LS490
MAX

VIH = 2 V,
VIL = VILmax

II

TYPt

2

VCC = MIN,
VOL

SN54lS490
MIN

Low-level input current set-to-9 VCC =MAX,

I---

VI=O.4V

Clock

lOS

Short-circuit output current§

VCC = MAX

ICC

Supply current

VCC = MAX,

-20
See Note 2

20

20

40

40

-0.4

-0.4

-1.6

-1.6

-100
15

26

-20
15

mA

IJA

I

mA

-100

rnA

26

rnA

tFor conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
fAil typical values are at Vee = 5 V, T A = 25°C.
one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 2: ICC is measured with all outputs open, both clear inputs grounded following momentary connection to 4.5 V. and all other inputs

§ Not more than

grounded.

1076

TENTATIVE DATA

7-524

This page provides tentative information on a
new product. Texas Instruments reserves the
right to change specifications for this product
in any manner without notice.

TEXAS INSTRUMENTS
INCORPORATED
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•

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TYPES SN54LS490, SN74LS490
DUAL 4-81T DECADE COUNTERS
switching characteristics, Vee
PARAMETER~

f max
tPLH

=5 V, TA =25°e

FROM

TO

(INPUT)

(OUTPUT)

Clock

QA

Clock
Clock
Clock
Clear

tPLH

Set-to-9

tpHL
~ f max
tpLH
tpH L

35

== maximum count frequency
== propagation delay time, low-to-high-Ievel
== propagation delay time, high-to-Iow-Ievel

RL = 2 kn

CL=15pF,

See Figure 2 and Note 4

QC

tpHL
tPHL

TYP

25

MAX UNIT

12

QS,QD

tpHL
tpLH

MIN

QA

tpHL
tPLH

TEST CONDITIONS

MHz
20

13

20

24

39

26

39

32

54

36

54

Any

24

39

QA,QD

24

39

QS,QC

20

36

ns
ns
ns
ns
ns

output
output

NOTE 4: Load circuit is shown on page 3-11.

SET-TO-9
INPUT

~~3~-------- -~\~

:

CLEAR
INPUT

CLOCK
INPUT

!

tPLH

I

I

I

~

IS

--:-':
I

\-- 1.3 V

I

0v

n+1

~

I

tPHL

I

\

\.----.t--

t"\
~tPLH

I

+

:

\

4

1.3V

i f .
I

I

1

attn+4
1.3 V

If
t

PHL

I

FI l'

1

1.3 V

I

tpLH-Measureatt n +8

VOH

II

~ tn+4

I
'{ ::-

OH

L-

VOL

~

tPHL-Measure attn+8

--

:

I

~

~1.3V
~

~

' \ . 1.3 V

/ ' 1.3 V

~-----------------~§rf------------J

VOH

VOL

tpHL-Measureatt n +10

~I ~---

1,--------,.
V

I
:

I

tPLH-Measure~

tPHL

-.-'1

4-1.3V-

~

at tn+2

tPLH-:~:s~;e ~~1

I

11.3

tpHL -Measure

I

VOL

: - ' \ 1.3 V

I

I

--1-'1

!

a

tPH L -Measure

...J~ tPHL

-

\

r-----rI

f

tPHL

I

~tPHL

OUTPUTQO

3V

~tWICIOCkl"

-,

1.3V

I

OUTPUTOc

5\

I

tsu

~ tPLH-M:~sure

:

I ,--_ _...;1'• .....,.1

JJ1.3V

OUTPUTQS

.1

tsu

F\1~V---!--------------------

_..;I.--..r,-____~!:__---J/~J~~~v~- - ::
i '\
Pv
\.;v :I.----.t-C
I

OUTPUTQA

~s - - - - - - - --::

-- - - -

VOH

1.3 V
VOL

VOLTAGE WAVEFORMS
NOTES:

A. Input pulses are supplied by a generator having the following characteristics: tr .;; 15 ns, tf';;; 6 ns, PRR = 1 MHz, duty cycle
= 50%, Zout '" 50 ohms.

FIGURE 2

1076

TENTATIVE DATA
This page provides tentative information on a
new product_ Texas Instruments reserves the
right to change specifications for this product
in any manner without notice_

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

7-525

TTL
MSI

TYPES SN54LS670, SN74LS670
4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS
BULLETIN NO. DL-S 7612122, MARCH 1974-:-REVISED OCTOBER 1976

SN54LS670 ••. J OR W PACKAGE
SN74LS670 •.• J OR N PACKAGE
(TOP VIEW)

•

Separate Read/Write Addressing Permits
Simultaneous Reading and Writing

•

Fast Access Times ... Typically 20 ns

•

Organized as 4 Words of 4 Bits

•

Expandable to 512 Words of n-Bits

•

For Use as:
Scratch-Pad Memory
Buffer Storage between Processors
Bit Storage in Fast Multiplication Designs

Vcc

D~~A

D1

•

3-State Outputs

•

SN54LS170 and SN74LS170 Are Similar
But Have Open-Collector Outputs

WRITE SELECT

'W";"'W';"

ENABLE

WRITE READ

OUTPUTS

"Ci'i"'Cii'

01

D2

02

positive logic: see description

description
The SN54LS670 and SN74LS670 MSI 16-bit TTL register files incorporate the equivalent of 98 gates. The register file
is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations
to either write-in or retrieve data. This permits simultaneous writing into one location and reading from another word
location.
Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined
by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its
true form. That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that
particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate
inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable
input, GW, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the
internal latches. When the read-enable input, GR, is high, the data outputs are inhibited and go into the high-impedance
state,

I

The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding
gates are used to complete the address for reading a word. When the read address is made in conjunction with the
read-enable signal, the word appears at the four outputs.
This arrangement-data-entry addressing separate from data-read addressing and individual sense line-eliminates
recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time
(27 nanoseconds typical) and the read time (24 nanoseconds typical). The register file has a nondestructive readout in
that data is not lost when addressed.
All inputs except read enable and write enable are buffered to lower the drive requirements to one Series 54LS/74LS
standard load, and input-clamping diodes minimize switching transients to simplify system design. High-speed,
double-ended AND-OR-INVERT gates are employed for the read-address function and have high-sink-current,
three-state outputs. Up to 12L of these outputs may be wire-AND connected for increasing the capacity up to 512
words. Any number of these registers may be paralleled to provide n-bit word length.
The SN54LS670 characterized for operation over the full military temperature range of -55°C to 125°C; the
SN74LS670 is characterized for operation from O°C to 70°C.

1076

7-526

TEXAS INSTRUMENTS
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•

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TYPES SN54LS670, SN74LS670
4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

logic
READ FUNCTION TABLE (SEE NOTES A AND DI

WRITE FUNCTION TABLE (SEE NOTES A, B, AND CI
WRITE INPUTS

OUTPUTS

WB

WA

GW

0

1

2

3

RB

RA

GR

Q1

Q2

Q3

Q4

L
L

L

Q=D

QO

QO

L

WOB2

WOB3

WOB4

H

L
L

WOB1

H

L
L

W1B1

W1B2

W1B3

W1B4

H

L

H

L

L

W2B1

W2B2

W2B3

W2B4

H

H

L
L
L
L

H

H

L

W3B1

W3B2

W3B3

W3B4

X

H

X

X

H

Z

Z

Z

Z

X
NOTES:

READ INPUTS

WORD

A.
B.
C.
D.

QO

QO
Q=O

QO

QO

QO
Q=O

QO

QO

QO

QO
Q=O

QO

QO

QO

QO

QO

H = high level, L = low level, X = irrelevant, Z = high impedance (off)
(a = D) = The four selected internal flip·flop outputs will assume the states applied to the four external data inputs.
aO = the level of a before the indicated input conditions were established.
WOB1 = The first bit of word 0, etc.

functional block diagram

DATA
INPUTS

OUTPUTS

•

1076

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•

DALLAS, TEXAS 75222

7-527

TYPES SN54LS670, SN74LS670
4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

-------4. . . -- vee

Vee - - - -....- - - -

INPUT -

. .-W......- -. .-

'----4......- -

OUTPUT

Any D, R, or W: Req = 20 kn NOM
GR: Req = 6.67 kn NOM
GW: Req = 10 kn NOM

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1)
Input voltage . . . . . . . .
Off-state output voltage
Operating free-air temperature range: SN54LS670
SN74LS670
Storage temperature range

•

7V
7V

5.5 V
-55°C to 125°C
oOe to 70°C
-65°C to 150°C

recommended operating conditions
SN54LS670
MIN
4.5

Supply voltage, Vee
High-level output current, IOH

5

SN74LS670

MAX

MIN

NOM

5.5

4.75

5

-1

Low-level output current, IOL

i

Data input with respect to
write enable, tsu(D)

Setup times, high- or low-level data

Write select with respect to

(see Figure 2)

write enable, tsu(W)
Data input with respect to
write enable, th(W)

Hold times, high- or low-level data

25
10

15

15

rnA

i

I

i

ns
ns
ns

I
I

15

15

ns

5

5

ns

25

25

ns

-55

Operating free-air temperature range, T A

V

!
I

10

write enable, th(O)
Latch time for new data, tlatch (see Note 3)

5.25

81 rnA

25

Write select with respect to

(see Note 2 and Figure 2)

UNIT

MAX
-2.6

41

Width of write-enable or read-enable pulse, tw

NOTES:

NOM

125

0

70

°c

1. Voltage values are with respect to network ground terminal.
2. Write-select setup time will protect the data written into the previous address. If protection of data in the previous address is not
required, tsu(W) can be ignored as any address selection sustained for the final 30 ns of the write-enable pulse and during th(W)
will result in data being written into that location. Depending on the duration of the input conditions. one or a number of
previous addresses may have been written into.
3. Latch time is the time allowed for tl'le internal output of the latch to assume the state of new data. See Figure 2. This is important

only when attempting to read from a location immediately after that location has received new data.

1076

7-528

TEXAS INSTRUMENTS
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•

OALLAS, TEXAS 75222

TYPES SN54LS670. SN74LS670
4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS
REVISED OCTOBER 1976

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH High-level output voltage
VOL Low-level output voltage

SN54LS670
TYP:j: MAX

TEST CONDITIONSt

PARAMETER

MIN
2

Vee= MIN,

II = -18 mA

Vee- MIN,

VIH-2V,

VIL = VIL max
Vee- MIN,

VIH - 2V,

VIH = 2V,

Vo = 2.7 V

Off-state output current,
10ZL low-level voltage applied

Vee = MAX,

VIH=2V,

Vo = 0.4 V

VI = 7V

I"
input current
... Hioh-Ievel
--

Low-level input current

IlL

I Vee= MAX,
VI =2.7V

Vee= MAX

Short-circuit output current§ Vee= MAX
Supply current
Vee= MAX,

lOS
ICC

-1.5

V

3.4
0.25

Vee = MAX,

Vee = MAX,

V

-1.5
2.4

10L -4mA

V
0.8

0.4

10L =8 mA

Off-state output current,
10ZH high-level voltage applied

Input current at

2
0.7

10H =-2.6mA

VIL = VIL max

maximum input voltage

2.4

10H =-1 mA

SN74LS670
UNIT
TYP:j: MAX

MIN

I

I Any D, R, crW
I GW
I GR

I ..

Any D, R, or W

V

3.1
0.25

0.4

0.35

0.5

V

20

20

p.A

-20

-20

p.A

0.1
0.2

0.1

0.3

0.3

20

20

mA

0.2

I I

~G-,.~'~~--------------~-----------4-0~------------4-0~

GR
Any D, R,orW

60

60

-0.4

-0.4

GW

-0.8

-0.8

GR

-1.2

-1.2

-130

-30
See Note 4

30

-30

50

30

-130
50

uA

mA
mA
mA

tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j:AII typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
NOTE 4: Maximum ICC is guaranteed for the following worst·case conditions: 4.5 V is applied to all data inputs and both enable inputs, all
address inputs are grounded and all outputs are open.

switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER~

tPLH

FROM
(INPUT)

TO
(OUTPUT)

TEST CONDITIONS

Read select

AnyQ

eL = 15 pF, RL=2kn.
See Figures 1 and 2

Write enable

AnyQ

tpHL
tpLH

MIN

TYP

MAX UNIT

23

40

25

45

26

45

tpHL

eL = 15 pF, RL = 2 kn,

28

50

tpLH

See Figures 1 and 3

25

45

23

40

Data

AnyQ

Read enable

AnyQ

tPHL
tZH
tZL
tHZ

eL=5pF,

RL = 2 kn,

See Figures 1 and 4

15

35

22

40

30

50 i
35

16

tLZ

ns

•

ns
ns
ns
ns

= propagation delay time, low·to-high·level output
tpHL propagation delay time, high-to·low·level output
tZH = output enable time to high level
tZL = output enable time to low level
tHZ output disable time from high level
tLZ = output disable time from low level

~tpLH

=

=

)76

TEXAS INCORPORATED
INSTRUMENTS
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DALLAS. TEXAS 75222

1-529

TYPES SN54LS670, SN74LS670
4-8Y-4 REGISTER FILES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
TEST
POINT

Sl
FROM OUTPUT
UNDER TEST
-

......- - - - 4................
(See Note B)

NOTES:

A. CL includes probe and jig capacitance.
B. All diodes are 1N916 or 1N3064.

LOAD CI RCUIT
FIGURE 1

WRITE-SELECT
INPUTWAorWB
(See Note A)

\-----------3V

~
I
-.j

1.3V

~

11.3V

\.._______________ 0 V

-----il-""\ .

--I

\.3V

OATt' INPUT
01,02,03, or 04
(See Note A)

•

I

tsu(W)

I

I

t-- th{W)

3V

/.~"-

1
________ ov
1---1- tsu(D)

~th(O)

- - -.. . t-- tw ---I
~~~:~~ABLE
11.3v

I ~~ _________ -ov
______--J,)'..3 V \l~V -3V

\ . - - tlatch - - ,

-

READ-SELECT
INPUT RA or RS
(See Note S)

_ _ 3V

I \..._ _ _ _ _ _ 0 V
I

!+tPLH ,

I
!+-tPHL-!

\1."-___
3V -It":. _-

OUTPUT
01,02,03, or 04

I

VOH

VOL

VOLTAGE WAVEFORMS (S1 AND S2 ARE CLOSED)

NOTES:

A. High-level input pulses at the select and data inputs are illustrated; however, times associated with low-level pulses are measured
from the same reference points.
B. When measuring delay times from a read-select input, the read-enable input is low.
C. Input waveforms are supplied by generators having the following characteristics: PRR .;; 2 MHz, Zout '" 50 51, duty cycle';; 50%,
tr .;; 15 ns, tr .;; 6 ns.

FIGURE 2

107;

7-530

TEXAS INCORPORATED
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•

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TYPES SN54LS670, SN74LS670
4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
\ - - - - - - - - - - - - 3V

,DATA INPUT
D1, D2, D3, or D4

.

OV

WRITE-ENABLE
INPUTGW

OUTPUT
01,02,03, or 04

VOLTAGE WAVEFORM 1 (S1 AND S2 ARE CLOSED)

DATA INPUT
D1, D2, D3, or D4

1

~.3V-----....J
I ........

WRITE-ENABLE
INPUTGW

3v

- - - - - - - - - - - - ov

\;~ ~ ----- ::

---'1

_ _--:1_ _ _ _

I------i-tpH L

r - - - + I

----\1I
OUTPUT
01,02,03, or 04
_____\\..._3_V____________

tpLH

3V

---Jl,·: ___

ov

VOLTAGE WAVEFORM 2 (S1 AND S2 ARE CLOSED)
NOTES:

A. Each select address is tested. Prior to the start of each of the above tests both write and read address inputs are stabilized with
WA = RA and WB = RB' During the test GR is low.
B. Input waveforms are supplied by generators having the following characteristics: PRR .;; 1 MHz, Zout '" 50 n, duty cycle';; 50%,
tr .;; 15 ns, tr .;; 6 ns.

FIGURE 3

READ~
ENABLE

~3V

1.3V

l\:
I '-------------- ----li=~.>-.:'-------- 0 V

I---tZL----.,

WAVEFORM 1
(See Note A)

:
I
:

I--tLZ--j

-t----""4.5V
Sl closed,
1.3 V
S2 open

I----tZH

-----l

Sl open,
S2 closed

I

I

:

I

I

:

Sl and
S2 closed

1---1..

'"

1.5 V

,----VOL

r-tHZ-\ 0.5 VO.5 V

I
WAVEFORM 2
(See Note A)

•

lr--

/ " 1.3 V

- - - - - . . . : ' -*-----VOH
,...
"'1.5V
S1 and
"" 0 V
S2 closed

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS
NOTES:

A. Waveforms 1 is for an output with internal conditions such that the output is low except when disabled by the read-enable input.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the read-enable input.
B. When measuring delay times from the read-enable input, both read-select inputs have been established at steady states.
C. Input waveforms are supplied by generators having the following characteristics: PRR .;; 1 MHz, Zout '" 50 n, duty cycle';; 50%,
tr .;; 15 ns, tr .;; 6 ns.

FIGURE 4

374

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7-531

•

7-532



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