070 5397 00 91S16 91S32 Service Manual Oct85 070-5397-00_91S16_91S32_Service_Manual_Oct85 070-5397-00_91S16_91S32_Service_Manual_Oct85
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COMMITTED TO EXCEllENCE
91S16 AND 91S32
SERVICE MANUAL ADDENDUM
TO THE DAS 9100 SERIES SERVICE MANUAL
(PART NUMBER 062-5848-00, -01, AND UP)
This Tektronix Manual Addendum supports the 91S16 and 91S32
Programmable Pattern Generator Modules. This addendum contains
the general information, specifications, operating instructions,
theory of operation, test and adjustment procedures, and
troubleshooting information for the modules.
Parts location
drawings and schematics are also included.
The 062-5848-00 manual set is a package consisting of loose leaf
binders with manuals and addenda.
Each manual and addendum in
the set has its own part number starting with prefix 070.
This addendum contains service information for the 91S16 and
91S32 Programmable Pattern Generator Modules.
Refer to the DAS 9100 Series Service Manual for information on
other DAS products, including mainframes, instrument modules,
probes, and options.
How to Use This Addendum. This addendum is organized similarly
to the DAS 9100 Series Service Manual: sections in the addendum
correspond to the sections in the service manual. You can either
leave the addendum whole and place it in one of the service
manual binders, or you can separate the sections and insert them
after the corresponding section in the main manual.
NOTE:
You can order an extra service manual binder
(Vol. III) by using PIN 016-0769-00.
PLEASE CHECK FOR CHANGE INFORMATION
AT THE REAR OF THIS MANUAL
070-5397-00
Product Group 57
FIRST PRINTING OCTOBER 1985
THE FOLLOWING SERVICING INSTRUCTIONS
AR6 ·J;QR. USE ·BY . QUALIHED p.eBS01@dtit~
ONLY. TO AVOID PERSONAL INJURY, DO NOT
PERFORM :t~WN'f -S1t~V4GlNS ~H£mc;!'ItH,4;~
THAT CONTAtNEE)~ tN {)PERAT.NG'~JNS1'R~
T10NS' UNLESS -vet)' ARE €lUfttElftEO:,W GO·
SO:
.
Copyright@, ·1985.,. Tektr8OiiP,mcr::,m:~'ri.gh.tS'~r(e~.
Contents -of this pu~iGa.ti"A may ~t'Ybe:'. rnpl!Ddooedi~in arw.:
form· without> Mle Wrtttefl pel'!iT.tisSfOR·'of 'jfektronfXi;, Hfc.
.
-
-
-
Products of Tektronix, Inc. and its subsidiaries are covered
'by U.S. and foreign 'patents'and/or pending- patents.
iEKTRO~IX"TEK j:,S'CdPE~MOBiLE
~
.' and,'" . ,i f " a f e
registered tr~dema;ksof Tet<:tronix,:lnc: TE[EQUIPMENT:is
.~. registet'e9 Jrc:id~l!Iark.:'()rTe~tronfxO.K. limited.:
Printedjri J{s.,!=§~ifii~~~ lin~
are rese,rveq..
Tektronix, Inc.
P.O. BOX 4600
Beaverton, Oregon 97075
~ti~·~c~~~~~P.r~~~s
.
DAS 9100 Series 91S16-91S32 Service
TABLE OF CONTEr.rS
Section 1 -- INTRODUCTION AND SPECIFICATIONS
Page
DESCRIPTION. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • .. • • • • • • • .. •• 1-1
91516 Algorithmic Pattern Generator ••••••••••••••••••..•••• 1-1
91532 Stored-Pattern Pattern Generator ••••••••••••••..•••.• 1-2
91516 as Controller for 91S32s ••.••.•••••••••••••••.•••••.• 1-2
SIGN.AL- CBA.RAC'.rERISTICS •••••••••••••
1-4
Clock ing. • • • • • • • • .. • • • • . • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 1-5
Co
••
'"
•
•
•
•
•
•
•
•
•
•
•
•
•
..
•
•
•
•
•
•
••
Data Output •••
1-5
Strobes. . . • . • • . .. . . . • • • . . • . . • . . • • . • • . . • • . .. • • . • . . • • . . . . . • . • .• 1-5
Interrupt Request ••••••••..•••••••••••.••••••••.••••••••..• 1-6
0
••••••••••••••••••••••••••••••••••••••••••••
Pause ......................
e.o • • • • • •
IIa
......................
III
....
1-6
External Start ••••••••••••••••••.•••••.•••••••••.•.•••••••• 1-6
KEYBO.ARD COftROI.S............... ~ • • • • • • • • • • •
4;
•
•
•
•
•
•
•
•
•
•
•
•
..
•
•
it.
1-7
INTRODUCTION TO 91S16 AND 91S32 SUB-MENUS ••.•••.•••••••••..•• 1-8
Major Sub-Menu Types ••••••••••••••••••••••••.••••..•••••••• 1-9
Configuration Sub-Menus ••••••••••••.•••••••••••.••.......•• l-10
Setup Sub-Menus •••••••••••.•••••••••••••••••••••••.•••.•••. l-11
Programming Sub-Menus ••••••••••••.••••••••••••••.•.••••.••• l-ll
STANDARD AND OPTIONAL ACCESSORIES ••.••••••.••••••••••••••••.• 1-13
91516 Pattern Generator Module ••••••••.•••••••••••••••.•.•. 1-13
91532 Pattern Generator Module •••••••••••••••••••••••••••.. 1-14
P6464 TTL/ECL Pattern Generator Probe •••••••••••••••••.•.•. 1-14
SPEC IF lCA.TI.ONS •
Electrical
Electrical
Electrical
Electrical
Electrical
Electrical
Electrical
Electrical
Q
•
,.
•••••••••••••••••••••••••••••••••••••••••••
Specifications:
Specifications:
Specifications:
Specifications:
Specifications:
Specifications:
Specifications:
Specifications:
1-15
Power Requirements ••.••..••••••• 1-15
91516 Pattern Processor ••••...•• 1-16
91532 Control •...•••••••...••••• 1-17
Pattern Data ••.••••••••••.•.•.•. 1-18
Strobe and Clock Outputs ...•.••• 1-20
Clock Rate ••••••••••••••••.••••• 1-24
91516 External Control Signals •• 1-15
91S16 External Start Input and
Trigger Output •••.••.•..••.•••.• 1-29
Electrical Specifications: 91532 External Control Signals •. 1-30
P6464 Electrical Specifications •••••••••••••••••••••••••••• 1-32
P6464 Environmental Specifications •.••••••.•••••••••••••••. 1-33
P6460 Electrical Specifications •••.••••.••••••••••••••••••. 1-33
P6460 Environmental Specifications ••••••••••••••••••.•••.•• 1-34
i
Sietion 2 --
OPTIONS
Page
~~R!-IGtDATION AND "UPDA"l.'E'RBQtJIREMENTS •• ~; ~;;. ~;;. ~"~.........
f<.
r
...
:
3-1
!"l?~~ I~~~~TI~,!,: : ~ : • : : : ~ • : : ~ : : • " • • • • ~, : : ~. ,~ ~, ~ " ... •••••••••
3- 3
~~IN~ ~,P~~~, ~~R\ PROBES.:;~
3-6
0,. .: ~):,!f~ !t,""'~
.
".'
':~}
• • • • • • •
,
OPiRA"l.'OR"'SCBECKOtrr~~~J?~~::: ~",;::! ~.' ~ •• ~'7·~~.~;'f~ ~ ......... 3-11
91516 CONPIGORA"l.'ION SUB.:.JdltO'ptELDS'AiifI) VALUES~~;:;~
........
: PATTERN GENERATOR CONFIGUAATIOl-l' Field. : : ~ ~ ;: ; e',; ~;. • • • • • • ••
~REGISTER ~ Field; •• ~ ~. ~ ~ .~
~ ~
~
e ~ ;' • • • • • • • s .
POD Heading •• c ."~~'1'~, ~:~y. t;"/'t'~ • •
'fr~;· 'ie,
,~ ,; f::,~fLI~ • •-, r~~~?
• ~ l".'.~ • • • e o . .
P6464 'OUTPUT t:.EVEL' 'Fi~fa ••••• -:~'. ~ •• '.,,: ~; •.• '.-;'. ,...
.. • • • • ••
CLOCK POLARITY Field~' ~ ~'~ : • : • :: : ; ~ • ;; .... :" ~ ~ ;; •• ~ ~.,~ •••• ~ • • • • ••
"',
CLOCK INHIBIT 'MASK 'Field.:~'::. ~: ~ ~:; ~;~'.:.:~'::::";:;~'
••••••
...... '
,. .
STROBE INHIBIT 'MASK 'Field: ~. ~.:::.:; ::~': ~ ~:~':. : :'. ; •••••••••
POD CLOCK Field ..... ~: ••~·~.s·:.~.~.~.:."'~:.rc: ...... ~.:~ •... ~~; .•~0:.$ •..•.
"
,
,I
l
•
:
:
.'
;
;
;
;'
•
;
..
:
•
;
;"
•
•. ~., •
:-;;.;
'
••"
c~
3-12
3-13
3-13
3-13
3-14
3-14
3-14
3-15
3-15
"
91S32 STAND ALORB'CORPIGURATIOH'SOB-MENU·PIELDS AND'VALUES •• 3-16
PATTERN ,GENERATOR cq~~~GtP~~~~ ~> ~
91S32 MODE Field .....· ••".~."'.:· .. ~'.".~ ~ .t-'.~.J..t.~. ~
~ .J.~".'If.{." !::'~"::~.~i ••••••••
POD Head ing ........... ~.' .'" ••~ ~ .•' .1 ....~ •.•"".' ~t .~ ~' ~ ~ * .' ~'> .t .~ .<' .'> .f .'" . "
."
. •#. ."
.-.
. " .--
3-17
3-17
3-18
3-18
3-18
3-19
3-19
3-20
3-20
3-22
3-22
3-23
3-26
3-26
3-27
3-27
3-28
3-28
nAS
9100 Series 91s1~~91S32-Service
·'1 "·c,
~';-;
~:' '"':"r. 15 "~.'
TABLE OF CONTEN'l'S -1cont:j
i'
91516 PROBE SUB-MENU FIELDS AND VALUES •••••••••
3-29
3~J.~
PATTERN GENERATOR SETUP Field. ·~~·~il'~'f~F!"! .~,;~l)!\t.·...$!!~) ...
..;.. ............. '
P6460 INPUT THRESHOLD Field .••••
3-30
IRQ Field AND QUALIFIER Field..
• •••••••
3-30
EXT JUMP Fie ld ••••••••••••••••.,~•.. ""~~.~' ,::~";~~,,~ • ~!"ff.: ,~i t~~'~:e: • J~' ,;.~ l:. • :;.- ~~~:,!~~__~~~.~',."~~:7~~~! "~'. ~r:J?;-~
PAUSE Field.;~~~;.~~ •• ~ ••••••••••••••••••••••••••••••••••• 3-33
INHIBIT (91516 & 91532) Field ••••••.•..••••• 'i'!".~"""'''., ~"".:!;..!\" .... T:~'i~~
EXTERNAL START· Field; ••••••••• ~ ~- ~ ~ ~ ; ~; ;~': ~ ~;' ."~": :_'''H~~/'~"'.':' :N~~ -: •~*W'~~35
ABo VALUES~~:'~~:" • ;::~':;';'.,,] • ::r:'~ "'. :'~:1~1\l~3 6
~~~§~~N~:E::~H~~~~~i!i~7~: •. : ; ~jA,~:~.~)Y' ~ '1 Cy;:j~~:'.J;,~::.: : '?"!
91532 PROBE SUB.:..MENU· FIELDS
PAUSE Fie1d •••••• k~~ • • ,., ••••;~~
INHIBIT Field:::. ~ ;.... ":J.'.'. ~
EXTERNAL START'Field:~:~
. . . . . . . ..
--.•. ~ .•, ." "1'-"
eM'
•• .: ••••
&-
e," • •
...... e.,.- •• ' -:"_/ .-.-.
).~.
,'"
",
.
~.r".-~.
~.,
.• -,!}.
91Sl6 AND 91S32 TIM1NG SuB-MEHUFIELDS A.N1? 'VALUES.,,' • "'~." • ~ • ~ •
PATTERN GENERATOR SETUP Field •• : •• ~ •• ~: • ; ~ •• '~ _~.': •• 1f • • • • • • •
CLOCK Field.~~;: ••
• , ~,~:,:- :. • !.\ ~~~}. • It • .' .- •. "... •
REFERENCE Field~
••••••••••••••", !. :-. ... ••
." • ••
POD Field.~.;~:;~
• • • .•' ! •
POD CLOCK
~
~
~_£r'
.,~
"~
, ,r
'~'-
~I'"
r:
!""" 1 "0"',. ":
,...".
91Sl6 PROGRAM: 'RON MODESuB":'MEMu~'/~: .'~ •• ;}~
PATTERN GENERATOR PROGRAM Fie1d.'~·",'~"""",
,
MODE Fie1d~~ .. ~~ .. : ••
START Seq Field~;.~
INHIBIT MASK 'Field.
SEQ (Sequencet Field.
• • • • e:".
LABEL Field •.••••••.••.
#A and #B Pattern Fields ••
S (Strobe) Field •••.••••.
.. .
..
",
"
• • •0
~ g~~!~~~bt~~~;~,.~'Fi;i~: ';;',::: :,~;"~;:ts"rr~:~:· ::r;:··
SEQ FLOW, CO~T~OL 'Fields~' •••••••••.••
REG, OUT Fields.".~.~.~.~.", ... :.,>:.",.' ...".,,-.~ .....
EDIT Fields:::::::::: •••••
> Field .• :::: ••• : •••.••
WIDTH Field~~:;: •• ::;:.
t
••••
....... .. .
~-)
DATA Column ..~ e·.1-. ~~ • •S.G.<.'" ~~ • • • • • • •fI: ." ••" .....~. -I'CODE Column."".: •••
t.~.~."
~
~.'"
~
CONVERSION "'F±fi!ld. ~'."~~.~.1~.
~.~ ~ ~ ~r,~'S·
J..I;,., . ,. •
fc
l\-
"
iii
."."" • •
. . . . . ._
.......,..
., .
t '.
3-40
3-40
·3-41
3-42
3-43
3-43
3-44
3-45
3-46
3-46
3-46
3-46
3-47
3-49
3-50
3-51
3-51
3-52
3-52
3-60
3-65
3-68
3-68
3-69
3-70
3-71
DAB ?9100 ::Sei:ies- 91S16-91S32 Service
Page
3-84
3-85
3-85
3-85
3-86
3-87
3-87
3-89
3-90
3-90
3-92
3-94
3-95
3-95
91532 PROGRAM: RUN MODE SUB-MENU FIELDS AND VALUES;
PATTERN GENERATOR PROGRAM Field ••••
!cWMODE Field ••••••••••
PAGE Field ••••••••••
START;SEG·Field~:: ••••••• ~: ••••••
INHIBIT MASK Field ••••••••••
-SEI3 - {SequeAce) -Pield. Ii; ~ ••• ~.
tDe and tBA Pattern Field ••••
S (Strobe}·Field,,~~
- I (Inhibit) ·Pield ••• i • • • • • • i.~ • • •
-'DIT·Fie1ds.;.~~ •••
> Field;.~~ •• i • • ~~ • • • • • • •
WIDTHFields~.~;~ •••••••••
DATA"Column •••
CODE Field ••.•
....
•
•
0
•
•
·.....
•
.......... .................
.. . . .. ..
... ..
91516 PROGRAM:
.
...
,~,
'l'RAa
AND
....
.,
;" iF"
~
-"
~
·
......
·
.
............ .. .. ..
• '~'i ~ • • • •
• i
·..
3-97
S'rEif~' •..~·~~._~_.L. ~':
................................... 5 -18
Transmission Test of the EXT CLK Signal •••••••••••.••••.... 5-l9
TRIGGER OUT Signal ·CGrittol Test ••••••••••••.•.•••••.••.••.• 5-21
External Pause Signal Control Test •••.••.•••••••••.••.••••• 5-23
.External Start ' Control 'Test •••••••.••••••••••••••••..•.•••• 5-25
POD Clock Delay Control Test ••••••••••••••••••••••••••••••• 5-26
91832 PATTERN GENERATOR MODULE FUNCTIONAL CHECK •••••..•.•.... 5-28
Mainframe Setup for the Functional Check •••.••••••.•••....• 5-28
Executing the Diagnostic Se1f-Test ••••••••••••••••.•..•..•• 5-29
Probe Setup for the Functional Check ••••••••••••••.•.••..•• 5-29
Initial Menu Setup for the Functional Check ••••••••••••.••• 5-30
Verifying POD Connector 0 .•.••••••.••.••....•...•...••..... 5-32
Verifying POD Connector C•..•.......•...•.....•.•.......... 5-33
Verifying POD Connector B••••••.•••.•••••••••••.•••.••..•.. 5-35
Verifying POD Connector A.~ •••••••••••••••••••••••.•••..••• 5-36
Verifying the PG INHIBIT line~ •••••••••••••••••••••••..•..• 5-38
Verifying the EXTERNAL START line •••••••••••••••••••••••••• 5-42
Verifying the PG CLK Line •••••••••••••••••••••••••.••••••.• 5-43
Verifying the PG PAUSE Line.~ ••..•••••••••••••••••••.•••.•• 5-44
91S32 PATTERN GENERATOR FUNCTIONAL CHECK WITH 91816 ••••.•.••. 5-47
Mainframe Setup for the Functional Check
of 91S32 with 91S16 ••••••••••..••••••••••••••••••••••...•.. 5-47
Executing the Diagnostic Self-Test •••••••••.••••••••••.••.. 5-48
Probe Setup for the Functional Check ••••••.••••••••••••••.. 5-48
Initial Menu Setup for the Functional Check ••••••••••.••.•. 5-49
Verifying POD Connector A of 91S32 ••.•••••••.•..••••.•..... 5-51
Verifying Clock Divider ••..•..••.•••••••••••••••.•.•...•.•• 5-52
Verifying the PG INHIBIT Line from 91516 to 91S32 ••••.•...• 5-56
Ver ifying the POD Delay .•••••••••••••••••••••••••••••.•.••• 5-60
Verifying the Data Delay .•••.•.•.•••.••••••.•••..••••••.••. 5-64
AOO'USTMENT PROC.EDtJRBS -. • • • .- .. • • • • • • • • • .. • •
e
•
•
•
•
•
.'. •
•
•
•
•
•
•
•
•
•
•
•
•
•
5- 6 6
91816 ADJUSTMENT PROCEDURBS •••••••••••••••••••••••••••••••••• S-66
DAC Adjustment for the P6460 Probe •••••••••••.••••.••.•.•.• 5-66
Equipment Required for Threshold Fixture Construction ••.•.• 5-67
Adjusting Delay Lines in ClockControl ••••••••••••••••...•. 5-69
Delay Line Adjustment for the First Latch#s
Clock in the Clock Line ••••.••••••••••••••.•••••••••••.•• 5-70
Adjusting Delay Lines for the Clock Line
in the P6464 Probe ••••••••••••••••••••••••••••••••.••..•• 5-72
Adjusting Delay Lines for the POD Clock
in Clock Positioning •••••••••••.••••••••••••••••••••••.•• 5-73
Delay Line Adjustment for the Last Latch Clock •••••••...• 5-75
viii
DAS 9100 5eries 91516-91532 Service
TABLE OF CONTENTS (Cont.)
Paqe
91532 ADJUSTMENT PROCEDURE ••.•.•...••••••••••••••••••.•••.••• 5-77
Delay Timing Adjustment ••••.•.••••••.•.•••••••••••••••••.•• 5-77
Adjusting 5 ns POD-to-POD Delay •.••.••••••••••••••••••••••• 5-8l
91532 Board Skew Adjustment Without a 9,1516, ••• ,••••••••••••• 5-85
P6464 'l"1'L/ECL PATTERN GENERATOR PROBE
CBECK~
••:••••••••.•••••• 5-88
VERIFYING INSTALLATION OF THE UPGRADED +5 V POWER SUPPLy ••••• 5-93
Section 6 -- MAIftERARCE: GENERAL INFORMATION
Paqe
MArRTERARCB PRECAUTIONS •••••••••••••••••••••••••••••••••••••• 6-1
INSTALLING AND RBMOVI.RG INSTROMENT MODULES ••.•••••.•••••••••• 6-2
Installation Slot Restrictions •••.•••••••••••••.••••••••••• 6-2
PREVEliITIVE AND CORRECTIVE MAIRTBlIARCE ............... e • • • • • • • • • 6- 2
Repairing 91516 and 91532 Modules •••••••••••••••••••••••••• 6-3
Extending the Modules for Maintenance •••••••••••••••••••••• 6-3
REPACKAGING IRPORMATION...................................... 6- 3
DISASSEMBLY 01' THE P6464 PROBB •••••••,........................ 6-4
Section 7
MAIl'I'rl5l!lARCE: TROUBLESHOOTING
Section 8 -- DIAGNOSTIC TEST DESCRIPTIONS
Page
91S16 PATTERN GENERATOR DIAGNOSTICS •••••••••••••••••••••••••• 8-1
The Diagnostics Menu ••.••••••••••••••••••••••••••••••.••••• 8-1
Diagnostics Control Summary •••••••••••••••••••••••••••••••• 8-2
Organization of Diagnostic Function
and Subtest Descriptions ••••••••••••••••••••••••••••••••••• 8-2
Quick Reference Function Descriptions •••••••••••••••••••••• 8-3
91Sl6 Function 0 CLK Path •••••••••••••••••••••••••••••••••• 8-4
91S16 Function 1 MEM ADDR •••••••••••••••••••••••••••••••••• 8-7
91Sl6 Function 2 VECTOR RAM •••••••••••••••••••••••••••••••• 8-15
91S16 Function 3 REGISTER ••••••••••••••••••.••••••••••.•••• 8-27
91S16 Function 4 INSTR ••••••••••••••••••••••••••••••••••••• 8-44
91Sl6 Function 5 Interrupt ••••••••.•••••••••••••••••.•••••• 8-57
91516 Function 6 THRSH ••••••••••••••••••••••••••••••••••••• 8-64
," ix
TABLEOP CONTENTS (cont.)
Page
91S32 PATTERN GENBRA~R DIAGNOSTICS •.•..•••..••••••.••...•..• 8-66
Organization of Diagnostic Function
and Subset Description·.· .•••.••..•••••••••••..••••..•.••••.. 8-66
Quick Reference Function Descriptions •.•••••••••••••.••••.• 8-67
91S32 Function 0 VECTIR GEN •••••••••••••••••.•••••••.•••..• 8-68
91832 Function 1 LOOP COUNT ••••••••••••.••••.....•.•..••.•• 8-73
91532 Function 2 VECTOR RAM ••..••••••••••.•.••...•••••.•.•• 8-81
91532 Function 3 eLK SEL •.••••••.••••••••.•••.••••••••.••.. 8-87
91S32 Function 4 5TART FF •••••••••••••••.•••••.••.••.•••..• 8-92
91532 Function 5 INHIBIT •••.••••.•••••••••••.•••••••...•... 8-93
91532 Function 6 PROBE IF ••.•.•.•••••••..•••••••.•••••.•.•. 8-95
91532 Function 7 BUFFER •••..•••••••..•••.••••••••••••••••.. 8-96
Section 9 -- REFERENCE IBPORMATION
SYSTEM COlIRBCTIONS •••
e
$
•
••••
f/:I
••••••••••••••••
Page
,.
••••••••••
"
,.
•
••
9-1
TEST POINT, JUMPER, AND ADJUSTMENT LOCATIONS ••.••••••••••..•• 9-4
SIGN.AL GLOSSARy ••••••••••••••••••••••••••••••••••••••
Section 10
REPLACEABLE ELECTRIC.AL PARTS
Section 11
DIAGRAMS
Section 12
REPLACEABLE MECBARIC.AL PARTS
x
CI
•
ill
•••••
9-12
DAS 9100 Series 91S16-91S32 Service
LIST OF ILLUSTRATIONS
Figure
1-1
1-2.
1-3
1-4
1-5
1-6
1-7
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
Page
91S16/32 block diagram •....•...••...•••.......•..•....
91S16/32 keyboard overlay .•..•.•.•••.•....•.••..••.•.
91S16/32 sub-menu structure •.••••••••••..•.•..••....•.
How to move between 91S16/32
Pattern Generator sub-menus •.•••••.••••••...••.....•..
Pod Clock/Data Output Delay from External Clock Input.
Interrupt/Qualifier and Mask timing diagram ••••.......
Internal and External inhibit timing diagram •.•.••....
0
1-4
1-7
1-9
1-10
1-21
1-28
1-28
Terminator configuration for 91S32s with 91516 .••..••.
3-2
Terminator configuration for stand alone 91S32s .••....
3-3
Installing an instrument module in the mainframe •••...
3-5
P6464 Pattern Generator Probe •..•...••.••.•.•.•.•.•...
3-7
P6460 External Control Probe .•..••••••..•.•••.••..•...
3-8
Installing a probe to a pod connector •.••••.•.••••.••• 3-10
91S16 Configuration sub-menu ••..•.••••.•.•••....••..•• 3-12
91S32 Stand Alone Configuration sub-menu ••••..•....... 3-16
91S32 Configuration sub-menu when used with 91S16 •••.• 3-21
91S16 Setup: Probe sub-menu ••••.•••••••.•.••.•••..•..• 3-29
91S32 Setup: Probe sub-menu ••••••••.•••.•.••.••••.•..• 3-36
91S16 and 91S32 Setup: Timing sub-menu •••••••.•.....•• 3-40
91S16 Program: Run sub-menu ••••••••...••••.••••..•.•.• 3-45
Table Build sub-menu ••••••••••.•..•••••••••••..•••.••. 3-67
91S32 Program: Run sub-menu ••.••.••••.•••••••.••..•.•. 3-84
Table Build sub-menu •••.•••••••••.•••••••••••••••.•••. 3-94
91S16 Program: Trace sub-menu ••••.•.•.••••.•.•..•••.•• 3-113
91S16 Program: Step sub-menu •.•.•••••.•••..•....•••..• 3-113
91S32 Trace sub-menu ......••.•.•..•....•...•.....•.•.. 3-118
91S32 Step sub-menu •.•••••••.•••••••••••••.•••••.•••.• 3-118
91S16 Program: Run sub-menu display
after binary down1oad ....••••••••.•••.•••••••..•••.... 3-131
91S16 Program: Run sub-menu display
after binary download ••.••.•.•.••.••••••••••.•.•.••••. 3-133
Trigger Specification menu organization •.•.•..••...•••
Timing Diagram menu, POD A transmission test .....•.•.•
Test data, inhibit control test •••.••....•••..••.••...
Test data, external jump line test ••••..••..•.....•••.
Test data, interruot test 1 .•.••..•••.•.•...•.••..••..
Test data, qualify-line test ••..•.•••...•.•••.••..•.••
Test data, EXT CLK transmission test •...••.•.....•••••
5-9
5-10
5-12
5-14
5-16
5-17
5-21
TRIGGER OUT pulse •••••••••••••••••••..•.•••.••••••.••. 5-22
External pause pulse, PAUSE = 0 ...•................... 5-24
External pause pulse, PAUSE
1 ••••••.•.•••••••..•.••• 5-25
=
xi
Introduction and Specifications
CAS 9100 Series 91S16-91S32 Service
GENERAL INFORMATION
DESCRIPTION
The 91 516 and 91532 Pattern Generator modules are second generation pattern generator cards.
Each module can be used alone. and each has specialized features that make it particularly suited
to a field of applications. However. the 91 516 can also be used to control the operation of up to five
91532s, giving you the advantage of both cards' feature sets.
NOTE
The 91516 and 91532 replace the first generation 91P16132 pattern generator modules. You cannot operate a 91516 or 915325 if a 91P16 is installed in
the DA5.
91S16 ALGORITHMIC PATTERN GENERATOR
The 91516 is an algorithmic pattern generator. The 91516 differs from stored-pattern (all vectors
stored in RAM) pattern generators in that loops, conditional branches, and a wide variety of
interactions with the circuit under test are allowed. A large pattern generator memory is not
necessary with algorithmic pattern generators since the capability to branch and loop within the
program allows you to keep the system under test stimulated without writing lengthy programs.
The 91 516 also allows you to have a great deal of real-time interaction with the circuit under test via
the 91516's optional P6460 External Control probe (Data Acquisition probe). This probe can be
used to acquire the following external signals: External Jump, Interrupt Request. Interrupt Request
Qualifier, Pause, and External Inhibit signals. You can also use this probe to acquire an external
clock signal.
There are two phono connectors on the back of the 91 516 module; one accepts an external start
Signal, and the other provides an external trigger signal.
The 91 516 provides two 8-bit data registers (or one internal 16-bit data register) which can be used
as counters or as an alternate source for pattern output. The 91 516 instruction set includes nine instructions ranging from simple JUMP to label commands to IF Register = 0 JUMP to label. Fifteen
different labels can be programmed. You can also program a special interrupt service routine.
The 91516 Pattern Generator module provides 16 data output channels. 2 clock. and 2 strobe
lines. 5trobes can be used as additional data channels. The master clock can be supplied either
from the DA5 internal clock or from an external device. Maximum clock speed is 50 MHz. Data output is normally synchronous with the master clock, but individual data and strobe lines can be
programmed :t 10 ns relative to the master clock (± 5 ns relative to pod clock). Pattern memory is
1024 sequence lines (vectors) deep.
Only one 91516 can be installed in the DA5, however the 91516 can be used as a controller for up
to five 91532s.
1-1
Introduction and Specifications
OAS 9100 Series 91S16-91S32 Service
91S32 STORED-PATTERN PATTERN GENERATOR
The 91 S32 is a stored-pattern (all vectors stored in RAM) pattern generator. Not all pattern
generator applications require as much interaction with the system under test as is provided by the
91 S16. Instead, many applications require straightforward test patterns that are often quite
lengthy, and frequently require wide data patterns. The 91 S32 is designed to serve these" wide and
deep" applications.
The 91 S32 is traditionally programmed to execute its program in a sequential beginning-to-end
fashion. However, if you use the 91532 in conjunction with a P6452 probe attached to the DA5
Trigger/Time Sase module, you can use inputs from that module to supply External Clock, External
Start, External Inhibit, and Pause signals. Data output is normally synchronous with the master
clock's rising edge, but individual pods can be adjusted ± 5 ns and individual channels have an additional ± 5 ns range.
Each 91 S32 provides 32 channels of data, four strobes, and four clock lines. You can install up to
six 91 S32s in a single CAS for a total of 192 data channels, 24 strobes, and 24 clock lines. In addition, the strobe lines can be used as extra data channels. Maximum clock speed is 50 MHz. Pattern
depth for all channels is 2048 sequence lines (vectors). however there are features available that allow you to split the memory into two 1024-line pages and reload alternate pages of memory while
the pattern generator is outputting data (this requires a 91 S16). The 91532 can also be
programmed to execute its program repeatedly.
91S16 AS CONTROLLER FOR 91S325
One 91 S16 can serve as a controller for up to five 91 S32s. In this configuration, you can supply up
to 16 data channels with a memory depth of 1024 lines, plus 160 data channels with a memory
depth of 2048 lines (two 1024-line pages). There are also 22 clock lines and 22 strobe lines
available.
In addition, this configuration provides all the branching instructions and interactive features
available with the 91516 along with the large numbers of data channels and pattern depth afforded
by the 91 S32s.
There are two different operating modes available when the 91 S 16 and 91 S32 are used together:
Sequential mode and Follows 91 S 16 mode.
Sequential Mode. This operating mode allows the 91 S 16 and 91832 to operate simultaneously.
The 91 S 16 will supply the clock signal to the 91 S32, however each card will execute its program
independently. In other words, the 91516 can perform branching operations while the 91S32s
execute their program in a sequentialline-by-line manner. When the 91832 reaches the end of its
memory, it can be set to automatically restart from the beginning. This will keep all data channels
active for as long as is desired.
In this mode. the 91 S32's memory is configured as a single 2048-line program.
Follows 91S16 Mode. This operating mode allows the 91 S16 to have much more active control
over the output of the 91 S32s. The 91532 will follow instructions governing sequence line
execution programmed in the 91S16.
1-2
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
In Follows 91 S 16 mode, the vector memory address register of the 91 S 16 becomes the vector address register for the 91 S32s via an interconnect cable. This means that if the 91 S 16 executes a
loop, the 91 S32s will also loop. For example, if 91 S 16 SEQ 10 (sequence line 10) contained an instruction transferring pattern execution to SEQ 5, the 91 S32s would also jump to SEQ 5 and
continue outputting data sequentially from that line.
The 91 S16 also supplies the master clock to the 91 S32 modules. Usually. you would want the
91 S 16 and 91 S32 to output data according to the same clock, but you can program the 91 S32 to
execute its program at one-half or one-fourth the clock rate supplied by the 91 S16 module.
In Follows 91 S 16 mode, the memory of the 91 S32 is divided into two 1024-line pages called Page A
and Page B. The size of these pages matches the memory depth of the 91 S16. The 91 S16 has control over which memory page the 91 S32 will execute. As an example, you can program two
different programs in the 91S32 (one in each page) and use the 91S16 to switch between the programs based on some signal sensed by the 91 S16's optional P6460 External Control probe.
Pattern Download From Host
One major feature provided by Follows 91 S 16 mode is the automatic Pattern Download From Host
feature. There are two versions of Pattern Download From Host. The Pattern Download For Static
Devices version can be used with or without a 91 S 16 installed. It can be implemented using either
Option 02 or Option 06 GPIB interface commands. The Pattern Download For Dynamic Devices
version uses the Keep-Alive feature programmed into the 91 S16. This version is only available
when you have a 91 S16 and at least one 91 S32 installed; you must use the Option 06 GPIB interface commands.
Pattern Download For Static Devices. If your pattern generator program is very large. or if you
have developed the program on a host computer. the entire program may be too large to fit into the
91S32's memory. Follows 91S16 mode allows you to output 2047-lines of vectors. reload the
pattern generator's memory from a host computer. output the new block Of vectors. and continue
this process until the entire program has been executed. Instructions for communicating with the
host computer or external storage device are programmed into the 91 S16. The Pattern Download
From Host feature uses either DAS Option 02 GPIB, the RS-232 master/slave interface using GPIB
commands, or DAS Option 06 GPIB (high speed GPIB).
Pattern Download For Dynamic Devices (Keep-Alive) When using the Pattern Download For
Static Devices feature. the pattern generator alternates between outputting patterns and sitting
idle while the next block of vectors is downloaded from the host computer. This can cause a
problem with dynamic circuit elements that require constant clock and vector inputs. The 91 S16/32
combination provides a Keep-Alive function to supply clock and a few vectors to keep the circuit under test active until the 91 S32 memory has been reloaded. Keep-Alive is essentially a subroutine
you program into the 91S16; static devices being tested won't require this feature. Keep-Alive is
only available when you are using DAS 9100 Option 06: I/O Communication Interface (with HSPAT
GPIB command).
1-3
Introduction and Specifications
OAS 9100 Series 91516·91532 Service
SIGNAL CHARACTERISTICS
The purpose of the pattern generator is to exercise a system under test. The pattern generator outputs clock and data signals which can be used to simulate circuit bus activity, or to directly
stimulate circuit elements. At the same time, it interacts with the system under test by responding
to a variety of external signals. The external signals available depend on whether you are using a
91516 module, a 91532 module, or a combination of the two modules.
Figure 1-1 illustrates the basic functions of the pattern generator and its input and output signals.
The characteristics of these signals are set up and enabled via the Pattern Generator menus.
..
EXTERNAL CLOCK
EXTERNAL START
PAUSEEXTERNAL INHIBIT
EXTERNAL CLOCK
INTERRUPT REQUEST
INTERRUPT REQUEST QUALIFIER
EXTERNAL JUMP
PAUSE
EXTERNAL INHIBIT
•
..
..-
---
POD CLOCK
~A&STROBE
....
P6464
EXTERNAL
CLOCK
PROBE
(91532'8 Only)
P6460
EXTERNAL
CONTROL
PROBE
(91516 Option)
P6464
PATTERN
GENERATOR
PROBE
TRIGGER/TIME BASE
MODULE
P
(Internal Clock)
=>
Cr---
PATTERN
GENERATOR
MODULE
r-
EXTERNAL START
TRIGGER OUT
5397-01
Figure 1·1. 91516/32 block diagram.
Refer to the specification tables later in this section for technical parameters related to these
signals.
1-4
Introduction and Specifications
DAS 9100 Series 91516-91S32 Service
CLOCKING
The pattern generator is associated with two types of clocks: the master input clock and the output
clocks.
The pattern generator's master input clock controls the rate of the output clock and data. The master clock may be the DA8 internal clock or the rising or falling edge of an external clock source. The
external clock is supplied via the optional P6460 probe for the 91816, or via the P6452 external
control probe attached to the DA8 Trigger/Time Base module for stand-alone 91832s. The
maximum clock rate is 50 MHz for the 91 S16 with either internal or external clock source. 91 S32s
operating without a 91816 controller can run at 50 MHz. using an internal clock source, or at 25
MHz. using an external clock source. A 91816 operating with 91832s can operate at up to 50
MHz., but there are some restrictions on the pod clock delay settings.
Here is a summary of the timing restrictions:
91816
Up to 50 MHz with internal or external clock; no pod clock restrictions.
91 S32 Stand-Alone
Up to 50 MHz. with internal clock if all pod clocks are set to 0 ns delay.
Up to 25 MHz. with either an internal or external clock with no pod clock
restrictions.
91 S16 with 91 S32s
Up to 50 MHz. with internal clock if all pod clock delays are set to
-5 ns.
The output clock (pod clock) signals are derived from the master input clock. The output clock's rising edge is synchronized with the selected master clock edge, whether rising or falling.
Each P6464 Pattern Generator probe supplies one output clock line, labeled ClK. Each P6464
probe also supplies eight data channels and one strobe line. Each probe connects to a specific pod
connector on the back of the pattern genrator module. Pod connectors are assigned letters to help
with identification. The 91 S16 accepts two P6464 probes and one optional P6460 External Control
Probe; the P6464s attach to pods A and B, and the P6460 probe attaches to Pod C. Each 91832
has four P6464 probes and which attach to pods labeled Pod A through Pod D.
In addition to the simple relationship of the pattern generator master clock to the rising or falling
edge of the input clock, each pod has a clock line that can be adjusted relative to the master clock.
Pod clocks can be skewed ± 5 ns relative to the master clock, and data and strobe outputs can be
skewed an additional ± 5 ns, allowing a maximum skew between data outputs (from two differnt
pods) of 20 ns. All pod timing adjustments are made relative to the master clock. Data and strobe
timing adjustments are made relative to the pod clocks.
When a 91S16 contrails one or more 91S32s in Follows 91816 mode, the 91S16 supplies the
master clock to the 91 S32s. You can program the 91 S32's clock rate to be one-half, one-fourth, or
the same as the 91816'5 clock.
DATA OUTPUT
Data output from the pattern generator is normally parallel on all channels. Each channel's timing is
adjustable up to ± 5 ns relative to its pod clock via the. 8etup: Timing sub-menu. Each pod clock is
adjustable an additional ± 5 ns relative to the master clock.
Each pattern generator probe provides eight data channels labeled 0 through 7. Each probe also
provides one strobe line which can be used as an additional data channel.
1-5
Introduction and Specifications
CAS 9100 Series 91S16·91S32 Service
INTERRUPT REQUEST
The 91S16 provides an Interrupt Request (IRQ) line via its optional P6460 External Control (Data
Acquisition) probe. The 91 S16 can be programmed to perform a special interrupt service routine
every time the IRQ line is asserted. The 91 S16 can also be programmed to ignore an interrupt call
during certain segments of program memory.
There is also an interrupt request qualifier line provided by the 91 S16's optional P6460 probe. This
line allows you to qualify when the IRQ line is valid.
PAUSE
Both the 91S16 and the 91S32 have the capability to respond to an external pause signal. Pause
causes the pattern generator to stop executing program lines but still hold the P6464 outputs at
their current levels. The 91 S16 PAUSE signal is supplied via its optional P6460 External Control
probe. The stand-alone 91 S32 PAUSE signal must be supplied via the P6452 External Clock Probe
attached to the DAS Trigger/Time Base module.
INHIBIT
There are two kinds of inhibit signals used by the 91 S16 and the 91 S32: internally programmed inhibits and external inhibits. Either kind of inhibit signal causes some or all of the P6464 data lines to
be tri-stated.
The 91 S 16 can have internal inhibits programmed in its Program: Run sub-menu. External inhibit
signals are provided via its optional P6460 External Control probe. The 91 S32 can also have
internal inhibits programmed in its Program: Run sub-menu, and external inhibit signals are
provided either by the 91 S16's P6460 probe, or, if no 91 S16 is installed, via a P6452 External Clock
probe attached to the DAS Trigger/Time Base module.
The 91 S 16 and 91 S32 Configuration sub-menus provide fields that allow you to select the polarity
of the internal and external inhibit signals. They also allow you to use logical operators to combine
these inhibit signals.
Both 91 S16 and 91 S32 modules provide bit-selectable inhibit masks for data channels in their
program sub-menus. Inhibit masks for clock and strobes lines appear in the Configuration submenus.
EXTERNAL START
Both the 91 S 16 and the 91 S32 can respond to External Start signals. These signals are supplied
via a phono connector for the 91 S16, and via the P6452 probe (attached to the DAS Trigger/Time
Base module) for stand-alone 91 S32s.
1-6
Introduction and Specifications
CAS 9100 Series 91S16-91S32 Service
KEYBOARD CONTROLS
Figure 1-2 illustrates the keyboard overlay supplied with each 91 S16 and 91 S32. Apply this overlay
over the existing Pattern Generator keys in the lower left corner of the DAS keyboard.
SEa FLOW
CONTROL
REG
080B08
08
OUT
SONY~!
......
9tS~ JIIW't PATTERN
...., . . GENERATOR
5397.02
Figure 1-2. 91516/32 keyboard overlay.
The 91 S16/32 Pattern Generator keys are arranged in three major groups. Group one consists of
keys used to call up the various sub-menus on the display. This group includes the PATTERN
GENERATOR key, the SETUP key. and the CONFIG key. Group two contains only the EXECUTE
key. The third group consists of the SEa FLOW, CONTROL, REG. and OUT keys. Key groups are
outlined on the 91 S 16/32 keyboard overlay.
NOTE
The SETUP and CONFIG keys will not operate unless you have already
entered the patten generator Program Run sub-menu. To enter the Setup
and Configuration sub-menus, press the PATTERN GENERATOR key first,
and then press either the SETUP or CONFIG key.
PATTERN GENERATOR This is the first key you will press when you want to call up any pattern
generator sub-menu from the DAS power-up menu. After pressing the PATTERN GENERATOR
key, the DAS will display the 91S16 Run sub-menu if a 91S16 is installed, otherwise it will display
the 91 S32 Run sub-menu.
SETUP This key causes the SETUP sub-menu to be displayed. There are two different setup submenus for each pattern generator module: PROBE and TIMING. See the Introduction to 91516
and 91532 Sub-menus section later in this manual for a description of these sub-menus. The
91 S 16 SETUP sub-menu will be displayed if a 91 S 16 is installed, otherwise the 91 S32 SETUP submenu will be displayed.
1-7
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
CONFIG This key causes the Configuration sub-menu to be displayed. See the Introduction to
91S16 and 91S32 Sub-menus section for a description of this sub-menu. The 91 S16 Configuration
sub-menu will be displayed first whenever a 91 S 16 is installed in the DAS.
EXECUTE This key marks the end of data entry during an edit operation. Pressing this key tells
the DAS you have finished making entries in an edit command and starts the operation.
SEa FLOW This key is only used when programming branch instructions for the 91 S 16. SEQ
FLOW stands for Sequence Flow. the order in which sequence lines are executed. See the 91 S 16
Program Run sub-menu for details.
CONTROL This key is used when programming the 91 S 16 to control the operation of one or more
91 S32s operating in FOLLOWS 91 S 16 mode. This key also selects the TRIGGER instructions
which issues a trigger signal via a phono connector on the back of the 91 S 16.
REG This is another 91 S 16 programming key used to control the function of the 91 S 16 internal
register. REG instructions can include load, increment. or decrement the contents of the internal
register.
OUT This key instructs the 91 S 16 to output the contents of its internal data register as data in
place of the regular vector programmed for that sequence line. This key also provides an instruction
that causes the pattern generator to ignore both the current Pod A pattern and register values and
instead output the previous Pod A vector again.
INTRODUCTION TO 91516 AND 91532 SUB-MENUS
The 91 S 16 and 91 S32 Pattern Generator modules provide a number of different sub-menus
tailored to particular tasks. Because the 91 S16 and 91 S32 can each operate independently. or with
the 91 S 16 as a controller for up to five 91 S32s. the two types of pattern generator modules have
similar sub-menus. In other words. the 91 S 16 and the 91 S32 both have Run. Trace, and Step submenus. However, because the 91 S 16 and the 91 S32 have different features. sub-menus with the
same name for each card may not operate in exactly the same way. Also. when the 91 S 16 is used
to control one or more 91 S32s. the function of both cards' sub-menus changes slightly.
This section of the manual is designed to familiarize you with the names and functions of each type
of sub-menu, let you know what other sub-menus are available, and help you move from one submenu to another easily. Detailed descriptions for each sub-menu are provided later in this
addendum.
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
MAJOR SUB-MENU TYPES
Both the 91 S 16 and the 91 S32 provide three basic types of sub-menus. These sub-menus are the
Configuration, Setup, and Programming sub-menus. Figure 1-3 illustrates the grouping of the submenus within their major headings.
To Enter PAT GEN Sub-Menus
Press PAT GEN Key
PROGRAM SUB-MENUS
1
STEP
I
TRACE
RUN
'-
(
SET-UP SUB-MENUS
-
**
TABLE
BUILD
*
~~
~
CONFIGURA nON SUB-MENU
TIMING
PROBE
I
**
CONFIGURATION
I
*TASLE BUILD sub-menu is part of CONVERSION edit command.
**
Denotes Default
5397-03
Figure 1-3. 91S16/32 sub-menu structure.
1-9
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
In order to access most of the pattern generator sub-menus, you must first press the PATTERN
GENERATOR key. Once you have displayed a pattern generator sub-menu, you can easily move to
and from the other sub-menus by pressing the appropriate key. Figure 1-4 illustrates how to use the
DAS pattern generator keys to move between the various sub-menus.
For
ProKram Suh-Mellus
Or For
Set-L!p Sub-Mel/US
Or For
Configuration Sub-Menu
Press
Move Cursor to
Mode Field
I
Press
*
CONFIGURATION
Press
TRACE
TIMING
Mode
Press
STEP
Mode
* Default
5397.04
Figure 1-4. How to move between 9181./32 Pattem Generator sub-menus.
CONFIGURATION SUB-MENUS
The 91 S16 and 91 S32 Configuration sub-menus are primarily used to set signal levels. signal
polarities, pod delays, and various inhibit masks-the kinds of things you do once per test
environment. They are also used to select major operating modes when 91S16 and 91S32 cards
are used together.
Press the CON FIG key on the DAS keyboard to display the Configuration sub-menu. If you have a
91S16 installed in the DAS, the 91516 Configuration sub-menu will be displayed first. Press the
SELECT key to display the 91 S32 sub-menu if you have both types of pattern generators installed.
NOTE
Some additional 91 S32 Configuration sub-menu fields are available when the
91832 is used in conjunction with a 91S16 mOdule.
1-10
Introduction and Specifications
DAS 9100 Series 91516-91532 Service
SETUP SUB-MENUS
There are two different Setup sub-menus: Probe. and Timing. Press the SETUP key to display the
Probe sub-menu. If an 91 S16 is installed in the DAS, the 91 S 16 Probe sub-menu will be displayed.
If only 91 S32s are installed, the 91 S32 Probe sub-menu will be displayed. You cannot display the
91S32 Probe sub-menu if a 91S16 is installed in the DAS.
The Probe sub-menu allows you to enter parameters for external control signals. The 91 S 16
accepts external control signals through its optional P6460 External Control (Data Acquisition)
Probe. The 91 S16 also has two phono connectors on the back of the module; the top phono
connector provides a trigger out signal (for an oscilloscope), and the bottom phono connector
accepts an external start signal. The external start signal is enabled in this sub-menu. The 91 S32.
in stand-alone configuration, uses the P6452 External Clock (Data Acquisition) Probe connected to
the DAS Trigger/Time Base module for its external control probe.
Because of the differences in these probes. the 91 S 16 and the 91 S32 Probe sub-menus are quite
different. The 91 S 16 Probe sub-menu will be the only Probe sub-menu available any time a 91 S 16
is installed in the DAS. If you are not using any extenal control signals with your pattern generator
modules, you do not need to enter anything into these sub-menus.
The Timing sub-menu is exactly the same for both the 91 S 16 and the 91 S32. To view the Timing
sub-menu, move the screen cursor to the top-most field in the Probe sub-menu and press the
SELECT key.
The Timing sub-menu adjusts the timing relationships between the clock. data. and strobe lines of a
single P6464 Probe. You will use this sub-menu to select the master clock and adjust the timing relationships between various data and strobe lines.
This sub-menu allows you to adjust the time when each data channel outputs its signal relative to
the master clock. You can use the fields in this sub-menu to move the clock (pod clock) supplied by
a particular probe ± 5 ns relative to the master pattern generator clock. You can also individually
program each of the data and strobe lines associated with that probe up to an additional ± 5 ns in
1 ns increments.
The Timing sub-menu also allows you to select the master pattern generator clock, either as a-function of the clock supplied by the DAS. or in the case of the 91 S 16. as an external clock supplied by
the P6460 External Control probe. 91 S32s in stand-alone configuration can receive an external
clock via a P6452 External Clock Probe attached to the DAS Trigger/Time Base module.
PROGRAMMING SUB-MENUS
The 91 S16 and 91 S32 Pattern Generator modules have three types of Programming sub-menus:
Run, Trace, and Step. These sub-menu names reflect the three major pattern generator operating
modes: Run mode, Trace mode. and Step mode. The Run sub-menu is the default sub-menu
displayed when the PATIERN GENERATOR key pressed. It is also the most frequently used submenu. In addition, the Run sub-menu has a special sub-menu called TABLE BUILD used for editing
existing data patterns.
You will use the Run sub-menu to enter the pattern used to stimulate your circuit under test. along
with a/l associated programming instructions. Trace and Step sub-menus control features that help
you monitor the pattern generator as it interacts with the system under test.
1-11
Introduction and Specifications
CAS 9100 Series 91S16·91S32 Service
The Run sub·menu displays sequence lines that indicate the order of program execution. In the
case of the 91 S32. pattern generation will start with the lowest-numbered sequence line and
progress sequentially until it reaches the highest.numbered sequence line. The 91 S16 Run submenu allows loops and conditional branch instructions, but the same general order of execution
holds true.
Each sequence line contains one or more fields in which you enter the data you want output via the
P6464 pattern generation probes. Additional fields are provided for strobe and inhibit bits. The
91 S 16 provides additional fields for its specialized instructions.
Both the 91 S16 and 91 S32 Run sub-menus provide nine pattern editing instructions: CONVERT,
COPY, DELETE, DISPLAY, FILL, INSERT, MODIFY, MOVE, and SEARCH. The CONVERT
editing instruction displays the Table Build sub-menu. The Table Build sub-menu is used to convert
an existing pattern generator program's data from one coding system to another (for example.
from normal binary to the Gray code).
Trace and Step sub-menus simply display the number of clocks, sequence line being executed, and
data vectors output so you can monitor program flow. Trace mode allows the pattern generator to
execute its program automatically. but at a rate slow enough for you to see sequence jumps, loops,
interrupt subroutines, and other structural demands on your pattern generator program. Step
mode allows you to do exactly the same thing, but requires you to press the START PAT GEN key
for each sequence line you want executed.
1-12
Introduction and Specifications
CAS 9100 Series 91S16-91S32 Service
STANDARD AND OPTIONAL ACCESSORIES
91516 PATTERN GENERATOR MODULE
The following lists include the standard and optional accessories for the 91 S 16 Pattern Generator
Module.
Standard Accessories
2
010-6464-01
P6464 TTUECL Pattern Generator Probes
334-6094-00 91 S16/32 Keyboard Overlay
1
070-5396-00
91 S 16, 91 S32, and P6464 Operator's Addendum (English)
1
070-5398-00 91 S16, 91 S32 Operator's Reference Guide
1
334-6230-00
"EXTERNAL CONTROL PROBE" Label for optional P6460 Probe
Optional Accessories
010-6460-00
P6460 Data Acquisition Probe (External Control Probe)
020-1392-00 Controlled-Width Podlet
175-9676-00 Phono-to-Phono Cable (9-inch) For external start signal.
175-8165-00 Phono-to-BNC Cable (2-meters) For Trig Out signal.
070-5397 -00 91 S 16, 91 S32, and P6464 Service Addendum
003-1134-00
Delay Line Adjustment Tool
1-13
Introduction and Specifications
CAS 9100 Series 91S16·91S32 Service
91532 PATTERN GENERATOR MODULE
The following lists include the standard and optional accessories for the 91 S32 Pattern Generator
Module.
Standard Accessories
4
010·6464-01
P6464 TIL/ECl Pattern Generator Probes
1
175-9700·00 Interconnect Cable (six connector)
334-6094-00 91 S16/32 Keyboard Overlay
070·5396-00 91 SS16, 91 S32, and P6464 Operator's Addendum (English)
070·5398-00 91S16. 91S32 Operator's Reference Guide
Optional Accessories
020-1392·00 ContrOlled-Width Podlet
003-1134-00 Delay Line Adjustment Tool
070-5397 -00 91 S16, 91 S32, and P6464 Service Addendum
175-9782-00 Extender Interconnect Cable
P6464 TTL/Eel PATTERN GENERATOR PROBE
The following lists include the standard and optional accessories for the P6464 TIL/ECl Pattern
Generator Probe.
Standard Accessories
070-5475-00 P6464 TIL/ECl Pattern Generator Probe Instruction Sheet
013-0217-00 Package of Grabber Tips (23 per probe)
334-6093-00 Package of Podlet Identification labels
196-2963-00 Package of lead-Sets (10 per probe)
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
SPECIFICATIONS
Table 1-1
ELECTRICAL SPECIFICATIONS: POWER REQUIREMENTS
Characteristic
Performance
Requirement
Supplemental
Information
Input Power Used by 91 816
+5 V ± 3% at 8 A maximum
+ 6 V ± 5% at 43 mA maximum
+ 12 V ± 1.5% at 30 mA maximum
-12 V ± 10% at 30 mA maximum
Input Power Used by 91832
+5V ± 3% at 8 A maximum
+6 V ± 5% at 36 mA maximum
Output Power from Mainframe
to Each P6464
+5 V ± 5% at 700 mA maximum
Output Power from Mainframe
to P6460
+5V ± 3%, at 600 mA maximum
-5V ± 3% at 100 mA maximum
1-15
Introduction and Specifications
CAS 9100 Series 91S16-91S32 Service
Table 1-2
ELECTRICAL SPECIFICATIONS: 91S16 PATTERN PROCESSOR
Characteristic
Performance
Requirement
Supplemental
Information
o to
Sequence Number
1023. 1024 lines
Multiple micro instructions can be programmed in the same sequence as long
as instruction is different.
2 S-bit registers: RA and RB
Internal Registers
RA and RB can be configured into one
16-bit register named R.
Program flow control:
Sequence Flow Instructions
'(Advance to next line)
IF RA=O JUMP to label
IF RB=O JUMP to label
IF R=O JUMP to label
IF EXT JUMP to label
IF IRQ JUMP to label
IF FULL JUMP to label
IF END JUMP to label
JUMP to label
RETURN
CALL RMT
HALT
Register Operation:
'(Hold register value)
INCR register value
DECR register value
LOAD register value
Output Control:
'Out data pattern
OUT register value
OUT REPeat
Note:
• : Default Operation
() : Displayed as Blank
1-16
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
Table 1-3
ELECTRICAL SPECIFICATIONS: 91S32 CONTROL
Characteristic
Performance
Requirement
Supplemental
Information
Operating Mode
91S32 with 91S16
Follows 91S16
91 S32 receives the clock and high
speed address (up to 1K range) from
91 S 16. 91 S32 memory divided into two
1K pages, arid changes between pages
when 91S16 executes INCR PAGE.
Sequential
91 S32 receives only the clock from
91S16. The 91S32 address and page
counter are incremented automatically
by the clock.
91 S32 Stand-alone
Sequential operation only
Repeat
1 to 65535
Free Run
This field specifies the number of times
the 91 S32s will loop through their
programs.
o to 2047
End Sequence
This number specifies the last sequence line in the program; after executing the sequence line specified. the
91 S32 restarts.
The END SEa field can be used when
91S32s are operating with a 91S16 in
sequential mode or in 91 S32 standalone mode.
1-17
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
Table 1-4
ELECTRICAL SPECIFICATIONS: PATTERN DATA
Characteristic
Performance
Requirement
Supplemental
Information
Number of Pattern Vectors
91S16
1024 maximum
91S32
2048 maximum
Pattern Width
91S16
16 parallel channels
(2 strobes/91S16)
91S32
32 parallel channels
(4 strobes/91 S32)
Expandable up to 176 channels with
one 91S16 and five 91S32's.
16+ (32 x 5)
Expandable up to 192 channels with six
91 S32's, (32 x 6)
Data Channel Maximum Skew
within Pod
1 ns at P6464 connector
(no edge positioning)
Any data channels within a pod will be
valid at P6464 connector within 1 ns of
each other when Edge Positioning is
not programmed.
Data Channel Maximum Relative
Error within Pod
2 ns at P6464 connector
(edge positioned)
Any data channels within a pod will be
valid at P6464 connector within
2 ns + Edge Position of each other
when Edge POSitioning is programmed.
Data Channel Edge Positioning
Any data channel can be placed :t 5 ns
in 1 ns steps at P6464 probe tip centered on the Pod Clock, This is a function of the P6464 programmed via the
Timing sub-menu.
Tri-State
Each data channel may be individually
tri-stated (inhibited) by the pattern generator inhibit signal.
The pattern generator inhibit Signal
sent to the P6464 is derived from microcode (Run sub-menu) and/or P6460
External Control Probe if 91 S 16 exists,
or from P6452 External Clock Probe
through Trigger/Timebase Module if
only 91 S32s installed.
1-18
Introduction and Specifications
OAS 9100 Series 91S16-91S32 Service
Table 1-4 (cont.)
ELECTRICAL SPECIFICATIONS: PATTERN DATA
Characteristic
Performance
Requirement
Supplemental
Information
Vector Source for Pod A
(91 S 16 only)
Data pattern, RA, RS, R (Low byte
only) or Repeat previous Pod A value
(OUT REP)
Vector Source for Pod B
(91 S 16 only)
Data pattern or R (High byte only)
NOTE: Not RB, and not high byte of
OUT REP
1-19
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
Table 1-5
ELECTRICAL SPECIFICATIONS: STROBE AND CLOCK OUTPUTS
Characteristic
Performance
Requirement
Supplemental
Information
strobe line per P6464
Strobe Output
Number of Strobes
91S16
2 strobes
91S32
4 strobes
Strobe Polarity
Strobe polarity can be programmed the
same as pattern data.
Strobe Maximum Skew Relative
to Data Channels Within Pod
ECl
1 ns at P6464 connector
(no edge positioning)
Strobe will be valid at P6464 connector
within 1 ns (ECl) or 1.5 ns (TTL) with
TTL
1.5 ns at P6464 connector
(one TTL load)
respect to other data channels in the
same pod when Edge Positioning is not
programmed.
(no edge positioning)
Strobe Maximum Relative Error
Within Pod
2 ns at P6464 connector
(edge positioned)
Strobe will be valid at P6464 connector
within 2 ns + Edge Position with reo
spect to other data channels in the
same pod when Edge Positioning is
programmed.
Strobe Edge Positioning
Strobe can be positioned::: 5 ns in 1 ns
steps at P6464 probe tip centered on
the Pod Clock. This function is controlled in the Timing sub-menu.
Tri-State
Strobe may be tri-stated (inhibited) by
the inhibit signal.
The pattern generator inhibit signal
sent to the P6464 is derived from microcode (Run-sub menu) and/or P6460
External Control Probe if 91S16 exists.
or from P6452 External Clock Probe
through Trigger/Time Base Module if
only 91832's used.
Pod Clock Output
1 clock line per P6464 probe can be
used as a Pod Clock.
Number of Pod Clocks
91S16
2 Pod Clocks
91S32
4 Pod Clocks
Pod Clock Polarity
Rising or Falling Edge. menu-selectable
1-20
Introduction and Specifications
DAS 9100 Series 91516-91532 Service
Table 1-5 (cant.)
ELECTRICAL SPECFICATIONS: STROBE AND CLOCK OUTPUTS
Characteristic
Performance
Requirement
Supplemental
Information
Pod Clock Pulse Width
(at P6464 Connector)
Internal Clock
~
External Clock
Input pulse width ± 6 ns
8ns
Clock pulse comes from P6460 Externa Control Probe if 91516 exists, or
from P6452 External Clock Probe
through Trigger/Time Base Module if
only 91532's used.
Pod Clock Delay from External
Clock Input
102 ns typical. Refer to Figure 1-5.
i
102 nS T Y P . i
EXTERNAL CLOCK INPUT ~I,..----:.___
AT P6460 PROBE TIP
POD CLOCK OUTPUT
AT P6464 PROBE TIP
(NO DELAY PROGRAMMED)
DATA OUTPUT
AT P6464 PROBE TIP
(NO DELAY PROGRAMMED)
LI
1
I
X
I
1
I
X
5397-05
Figure 1·5. Pod Clock/Data Output Delay from External Clock Input.
1-21
Introduction and Specifications
CAS 9100 Series 91S16·91S32 Service
Table 1-5 (cont.)
ELECTRICAL SPECFICATIONS: STROBE AND CLOCK OUTPUTS
Characteristic
Performance
Requirement
Pod Clock Maximum 8kew
Between Pods
Within 91816 or 91832
Supplemental
Information
Add 3 ns for maximum skew at P6464
probe tip if adjusted without probe,
2 ns at P6464 connector
(no edge positioning)
Edge of any Pod Clock within 91816 or
within 91832 will occur at P6464 connector within 2 ns of each other when
Edge Positioning is not programmed,
Between 91816 and First
91832
3 ns (adjusted as a set)
7ns (adjusted as a module)
at P6464 connector
(no edge positioning)
Edge of any Pod Clock within 91 S 16
and first 91 S32 will occur at P6464
connector within 3 ns (adjusted as a
set) or 7 ns (adjusted as a module) of
each other when Edge Positioning ia
not programmed.
Between 91 832' s
4 ns (adjusted as a set)
8 ns (adjusted as a module)
at P6464 connector
(no edge positioning)
Edge of any of 91 S32 Pod Clock will
occur at P6464 connector within 4 ns
(adjusted as a set) or 8 ns (adjusted as
a module) of each other when Edge
Positioning is not programmed.
Add 3 ns for maximum relative error at
P6464 probe tip if adjusted without
probe.
Pod Clock Maximum Relative
Error between Pods
Within 91816 or 91832
4 ns at P6464 connector
(edge positioned)
Edge of any Pod Clock within 91 S 16 or
within 91832 will occur at P6464 connector within 4 ns + Edge Position of
each other when Edge Positioning is
programmed.
Between 91 816 and First
91832
5 ns (adjusted as a set)
9 ns (adjusted as a module)
at P6464 connector
(edge positioned)
Edge of any Pod Clock and first 91 S32
will occur at P6464 connector within
5 ns + Edge Position (adjusted as a set)
or 9 ns + Edge Position (adjusted as a
module) of each other when Edge Positioning is programmed.
Between 91 832' s
6 ns (adjusted as a set)
10 ns (adjusted as a module)
at P6464 connector
(edge positioned)
Edge of any 91 S32 Pod Clock will occur
at P6464 connector within 6 ns.,... Edge
Position (adjusted as a set) or 10 ns.,...
Edge Position (adjusted as a module) of
each other when Edge Positioning is
programmed.
1·22
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
TABLE 1-5 (cont.)
ELECTRICAL SPECFICATIONS: STROBE AND CLOCK OUTPUTS
Characteristic
Pod Clock Edge Positioning
Performance
Requirement
Supplemental
Information
:t: 5 ns in 5 ns steps
Pod Clock can be positioned in - 5 ns
to + 5 ns range in 5 ns steps. Programmable.
Pod Clock may be tri-stated (inhibited)
by the inhibit signal.
Tri-State
The pattern generator inhibit signal
sent to the P6464 is derived from microcode (Run sub-menu) and/or P6460
External Control Probe if 91 S16 exists.
or from P6452 External Clock Probe
through Trigger/Time Base Module If
only 91 S32's used.
1-23
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
Table 1-6
ELECTRICAL SPECIFICATIONS: CLOCK RATE
Characteristic
Performance
Requirement
Supplemental
Information
Operating Rate, Run Mode
Up to 50 MHz (20 ns cycle time) Internal clock or external clock
91S16
91S32
With 91S16
Up to 50 MHz (20 ns cycle time) internal clock (Pod clock delay set to -5 ns)
or 25 MHz (40 ns cycle time) external
clock
Stand-Alone
Up to 50 MHz (20 ns cycle time) internal clock (Pod clock delay set to 0 ns)
Up to 25 MHz (40 ns cycle time) external clock
Clock
Internal or external, selectable
Source
Internal
From Trigger/Time Base Module of the
Mainframe
External
From P6460 External Control Probe if
91 S 16 exists. or from P6452 External
Clock Probe through Trigger/Timebase
Module if only 91 S32' s used.
Rising or falling edge. selectable
Polarity
91S16
91S32
(Stand-Alone)
Period
20 ns min
20 ns int. ck.
40 ns ext. ck.
Pulse High
9 ns min
19 ns min
Pulse Low
9 ns min
19 ns min
1-24
Introduction and Specifications
CAS 9100 Series 91S16-91S32 Service
Table 1-7
ELECTRICAL SPECIFICATIONS: 91S16 EXTERNAL CONTROL SIGNALS
Characteristic
Performance
Requirement
Using P6460 Probe
Input Threshold Range
Supplemental
Information
External control signals for 91 S16 are
obtained from P6460 External ContrOl
Probe.
-6.40 V to +6.35 V
in 50 mV steps
Threshold Accuracy
Indicated value ± .5% ± 6.5 mV
Minimum Logic Swing
0.5 V peak-to-peak, centered on the
threshold
External Clock Input
1 external clock line (edge selectable)
9 ns minimum pulse width
Interrupt Input
1 interrupt line (edge selectable)
Interrupt Processing Cycle Delay
1 cycle
When a valid interrupt request is logged
in, the first interrupt vector appears at
P6464 probe tip in the cycle where the
interrupt has been sampled.
Interrupt Minimum Pulse Width
15 ns
Interrupt Input Timing Window
Prior to External Clock Input
10 ns typical
To be recognized in a certain cycle.
assert the interrupt request in a range
of 10 ns prior to the selected edge of
the external clock, otherwise it will be
recognized in the next cycle.
Interrupt Input Timing Window
Prior to Pod Clock Output
104 ns typical
To be recognized in a certain cycle.
assert the interrupt request in a range
of 104 ns prior to Pod clock selected
edge output, otherwise recognized in
the next cycle.
Interrupt Latency
1 cycle time
Second interrupt can be latched in the
next cycle after the first interrupt has
been started.
1 level
Interrupt Service Call
The stack used to save the return address for the interrupt service call has 1
level.
1-25
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
Table 1-7 (cont.)
ELECTRICAL SPECIFICATIONS: 91S16 EXTERNAL CONTROL SIGNALS
Characteristic
Performance
Requirement
Supplemental
Information
Interrupt Mask
Mask bit in microcode disables receipt
of an interrupt as long as it is "1"
Interrupt Mask Timing Window
11 ns typical. Refer to Figure 1-6. 11 ns
typical after the rise/fall edge selected
to 11 ns typical to the next rise/fall edge
selected the external clock
Interrupt Qualifier Input
1 qualifier line (level selectable)
An interrupt is recognized if the selected edge is detected on the interrupt line
only when the qualifier line stays high or
low as specified.
Interrupt Qualifier Input Minimum
Pulse Width
15 ns
Interrupt Qualifier Input Setup
Time Relative to Interrupt
15 ns minimum
Maintain qualifier line high or low for
15 ns prior to the selected edge of the
interrupt.
Interrupt Qualifier Input Hold
Time Relative to Interrupt
o ns maximum
External Jump Input
1 external jump (level selectable)
Maintain qualifier line high or low after
the selected edge of the interrupt.
Pattern will branch on "IF EXT JUMP"
instruction if the EXT JUMP line is activated when the instruction is tested.
External Jump Minimum Pulse
Width
15 ns
External Jump Input Setup Time
Relative to External Clock Input
15 ns minimum
10 ns typical
Assert the external jump request 15 ns
prior to the selected edge of the external clock.
External Jump Input Hold Time
Relative to External Clock Input
o ns maximum
External Jump Input Setup Time
Relative to Pod Clock Output
105 ns
Assert the external jump request 0 ns
after the selected edge of the external
clock.
+
1 clock cycle typical
Assert the external jump request
105 ns + 1 clock cycle prior to the Pod
Clock selected edge output.
1-26
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
Table 1-7 (cant.)
ELECTRICAL SPECIFICATIONS: 91S16 EXTERNAL CONTROL SIGNALS
Characteristic
Performance
Requirement
External Inhibit Input
Supplemental
Information
external inhibit line (level selectable)
External inhibit is ANDed/ORed with
internal inhibit according to selection In
Probe sub-menu.
External Inhibit Minimum Pulse
Width
15 ns
External Inhibit Delay
40 ns typical. Refer to Figure 1-7.
Pause Input
1 pause line (level selectable)
Freezes the current data outputs while
pause line remains true.
15 ns
Pause Input Minimum Pulse
Width
15 ns minimum
Pause Input Setup Time Relative
to External Clock Input
10 ns typical
Assert the pause request 15 ns prior to
the selected edge of the external clock.
Pause Input Hold Time Relative
to External Clock Input
o ns
Pause Input Setup Time Relative
to Pod Clock Output
59 ns typical
Assert the pause request 59 ns prior to
the selected edge of the Pod Clock
output.
1-27
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
EXTERNAL CLOCK INPUT - '
AT P6460 PROBE TIP
i
Masked
I!-.- orSeqTopn -'-of1 Sub-Routine
QUALIFIER INPUT - ' I'-___
I'"
Seq rr
I
..
1..--_ _ _ _ _ __
I
r-- 15 nS--,
AT P6460 PROBE TIP
I
I
I
~10 nS_
I Typ. ,
Min.
I
INTERRUPT INPUT
AT P6460 PROBE TIP
If
I
1
I
\.1_ _ _ _ __
r--- 15 nS~
Min.
I
,
I
I
~11 nS~
L.11 nS.J
Typ.
I
Typ.
I
EFFECTIVE MASK WINDOW
(IF PROGRAMMED IN SEa n-1)
I
,...1_ _ _ _
~One
Clock Cycle...-..j
5397.06
Figure 1-6. Interrupt/qualifier and mask timing.
1-t--102 nS Typ.--...
~I
I
EXTERNAL CLOCK INPUT
AT P6460 PROBE TIP
POD CLOCK OUTPUT
AT P6464 PROBE TIP
(NO DELAY PROGRAMMED)
....J
I
'----...,j!
n-th Clock '--_ _---01
---..J
I
I
I
I
I
10 nS Typ.
"'1
!...
L-
INTERNAL INHIBIT ___I~_ _ _ _ _....I
I
AT P6464 PROBE TIP
I
r--0ne Clock Cycle-..,
(IF PROGRAMMED IN SEa n)
I
I
I~_ _.~_~:;;II----_--_
...,
I'" I
I
15nSMin.
I
EXTERNAL INHIBIT INPUT _ _ _
AT P6460 PROBE TIP
I
L--40nS~
I
Typ. T IIi-_ _......
I
I
EXTERNAL INHIBIT _ _ _ _ _ _ _ _ _ _......:1:....11
AT P6464 PROBE TIP
'-----
DATA OUTPUT
, _ _ _ _ __
AT P6464 PROBE TIP::::::::):
----------(NO DELAY PROGRAMMED)
5397·07
Figure 1-7. Internal and external inhibit timing diagram.
1-28
Introduction and Specifications
CAS 9100 Series 91516-91532 Service
Table 1-8
ELECTRICAL SPECIFICATIONS: EXTERNAL START INPUT AND TRIGGER OUTPUT
Characteristic
Performance
Requirement
Supplemental
Information
TIL-level input (edge selectable); phono connector; 2 LS TTL fan-in
External Start Input
The pattern generator automatically
starts when the external start signal is
asserted after once pressing the
START PAT GEN or START SYSTEM
key on the keyboard.
External Start Input Minimum
Pulse Width
15 ns minimum
Trigger Output
TIL-level output; phono connector: 5
STO TIL fan-out
A TIL high-level signal occurs on the
trigger output for 1 clock cycle when
the 91516 executes the TRIGGER
instruction.
Trigger Output Timing
-46 ns
Relative to Pod Clock Output
Trigger signal occurs 46 ns prior to the
selected edge of the pod clock output
when no delay is programmed.
56 ns
Relative to External Clock
Input
Trigger signal occurs 56 ns after the
selected edge of the external clock.
1-29
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
Table 1-9
ELECTRICAL SPECIFICATIONS: 91S32 EXTERNAL CONTROL
SIGNALS
Characteristic
Performance
Requirement
Supplemental
Information
Using P6452 Probe
External control signals for 91 S32 in
stand-alone configuration are obtained
from P6452 External Clock Probe attached to DAS Trigger/Time Base
Module.
Input Threshold Range
-2.5 V to +5.00 V in 50 mV steps
Input Threshold Accuracy
Menu-selected value :t 2% :t 100 mV
Minimum Logic Swing
0.5 V peak to peak centered on the
threshold.
1 external clock line (edge selectable)
External. Clock Input
19 ns minimum pulse width
1 external inhibit line (level selectable)
External Inhibit Input
External inhibit is ANDedJORed with
internal inhibit according to menu selections in the Probe sub-menu.
External Inhibit Minimum Pulse
Width
19 ns
External Inhibit Delay
76 ns minimum.
When external inhibit line is asserted.
the data outputs will be inhibited or tristated 76 ns after the external inhibit
signal is asserted.
1-30
Introduction and Specifications
CAS 9100 Series 91S16·91S32 Service
Table 1·9 (cant.)
ELECTRICAL SPECIFICATION: 91S32 EXTERNAL CONTROL SIGNALS
Characteristic
Performance
Requirement
Pause Input
Supplemental
Information
1 pause line (level selectable)
Freezes the current data outputs while
pause line remains true.
Pause Input Minimum Pulse
Width
19 ns
Pause Input Setup Time Relative
to External Clock Input
19 ns minimum
Assert the pause request 19 ns prior to
the selected edge of the external clock.
Pause Input Hold Time Relative
to External Clock Input
ons max
Pause Input Setup Time Relative
to Pod Clock Output
120 ns minimum
108 ns typical
Assert the pause request 0 ns after the
selected edge of the external clock.
Assert the pause request 120 ns prior
to Pod Clock selected edge output.
External Start Input
The pattern generator automatically
starts when the external start signal is
asserted after once pressing the
START PAT GEN or START SYSTEM
key on the keyboard.
External Start Input Minimum
Pulse Width
19 ns minimum
External Start Input Setup Time
Relative to External Clock Input
14 ns minimum
5 ns typical
External Start Input Hold Time
Relative to External Clock Input
ons typical
5ns minimum
1·31
Introduction and Specifications
DAS 9100 Series 91S16·91S32 Service
Table 1-10
P6464 ELECTRICAL SPECIFICATIONS
Characteristic
Clock In. Maximum Frequency
Performance
Requirement
Supplemental
Information
50 MHz (20 ns)
Power Required
Power required per channel from user s
circuit. Voltages referenced to instrument ground.
-.5 V to +5.5 V
at 55 mA + I load (user's more positive
supply voltage)
+.3 V to -5.5 V
at 63 mA + I load (user's more negative supply voltage)
4.8 V to 5.2 V
(within individual probes)
Pin Driver Outputs: Data. Clock.
Strobe
TTL Mode
Drive Capability
V LOUT = V L + .75 V
VH OUT = VH -1 V
sink or source > 20 mA
3.5 ns maximum (20% to 80% of logic
Transition Time
level). resistive load
ECl Mode
Drive Capability
VL OUT = VH -1.65 V
VH OUT = VH -1 V
20 mA (50!! to VH -2 V)
Nominal open emitters
50 pF maximum
2.5 ns maximum (20% to 80% of logic
level). resistive load
Transition Time
1-32
Introduction and Specifications
DAS 9100 Series 91S16·91S32 Service
Table 1·11
P6464 ENVIRONMENTAL SPECIFICATIONS
Characteristic
Description
Temperature
Operating
O°C to +50°C
Storage
-55°C to + 75°C
90% to 95% relative humidity
Humidity
Altitude
Operating
" maximum
4.5 km (15,000 ft.)
Storage
15 km (50,000 ft.) maximum
Table 1-12
P6460 ELECTRICAL SPECIFICATIONS
Characteristic
Description
User's Ground Sense
< 100 n to user's ground
Input Impedance
1 M!l ± 1%, 5 pF nominal; lead set adds approx. 5 pF
Max. Non-Destructive Input Voltage Range
± 40 V (DC + peak AC)
Max. Voltage Between Any Two
Inputs
± 60 V (DC + peak AC)
Operating Input Voltage Range
From -40 V to input threshold's voltage + 10 V
( + 30 V for RS-232 only)
Threshold Offset and Accuracy
± 0.25% of threshold ± 50 mV
Minimum Input Swing
0.5 V peak-to-peak, centered on the threshold
Minimum Pulse Width (with input
250 mV over the threshold from
+0.5 V and -0.5 V)
4 ns at threshold
1-33
Introduction and Specifications
DAS 9100 Series 91S16-91S32 Service
Table 1-13
P6460 ENVIRONMENTAL SPECIFICATIONS
Characteristic
Description
Temperature
Operating
Storage
Humidity
95% to 97% relative humidity
Altitude
Operating
4.5 km (15,000 ft.) maximum
Non-operating
15 km (50,000 ft.) maximum
1-34
DaD
Figure
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
~~UU
~eries
9~S16-91S32
Service
LIST OF ILLUSTRATIONS (cont.)
Page
Pattern Generator Program sub-menu
to start 9lS32 functional test •••••••.••••••••••••••••• 5-3l
Timing Diagram menu for POD connector 0 •••••••••••••••• 5-32
Pattern generator setup for POD D check •••••••••••••••• 5-33
Pattern generator setup for POD C check ••.••••••••••••• 5-34
Pattern generator setup for POD B check •••••••••••••••• 5-36
Pattern generator setup for POD A check •••••••••.•••••• 5-37
Pattern Generator Configuration sub-menu,
PG inhibit line test ••••••••.••••.••••••••••.•••••••••• 5-39
Pattern Generator Program menu
for PG inhibit line test ••••••••••••••••••••••••••••••• 5-39
Timing Diagram menu, PG inhibit line test •••••••••••••• 5-40
Pattern Generator Program Submenu modified,
PG inhibit line test •••••••••••••••••••••••••••••••.••• 5-4l
PG PAUSE line response, PAUSE = 0 •••••••••••••••••••••• 5-45
PG PAUSE line response, PAUSE = 1 •••••••••••••••••••••• 5-46
9lSl6 Program sub-menu setup, 9lS32 with 9lSl6 ••••••••• 5-50
9lS32 Program sub-menu setup, 9lS32 with 91516 ••••••••• 5-50
Timing Diagram menu, POD connector A••••••••••••••••••• 5-5l
9lS32 Program sub-menu for clock divider test •••••••••• 5-52
Timing Diagram menu for clock divided by 1 ••••••••••••• 5-53
Timing Diagram menu for clock divided by 2 ••••••••••••• 5-54
Timing Diagram menu for clock divided by 4 ••••••••••••• 5-55
9lSl6 configuration clock setup
for PG inhibittest •••••••••••••••••••••••••••••••••••• 5-57
9lS32 configuration clock setukp
for PG inhibit test •••••••••••••••••••••••••••••••••••• 5-57
91516 Program sub-menu for PG inhibit test ••••••••••••• 5-58
91532 Program sub-menu for PG inhibit test ••••••••••••• 5-58
Timing Diagram menu for the PG inhibit test •••••••••••• 5-59
+5 ns POD delay ••••••••••.••••••••••••••••••••••••••••• 5-6l
5-36
-5 ns POD delay_ . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
5-37
5-38
5-39
5-40
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
Threshold Fixture •••••••••••••••••••••••••••••••••••••• 5-67
First-latch clock line delay ••••••••••••••••••••••••••• 5-7l
P6464 clock line de1ay ••••••••••••••••••••••••••••••••• 5-72
POD clock line delay line setup •••••••••••••••••••••••• 5-73
Clock line delay for delay line DL760 •••••••••••••••••• 5-74
Clock line delay for delay line DL780 •••••••••••••••••• 5-75
Clock line delay for DL700 ••••••••••••••••••••••••••••• 5-76
91532 pre-adjustment setup ••••••••••••••••••••••••••.•• 5-79
91532 timing delay for DL260 ••••••••••••••••••••••••••• 5-80
Setup for -5 ns POD-to-POO delay adjustment •••••••••••• 5-8l
Setup for +5 ns POD-to-POD delay ••••••••••••••••••••••• 5-82
Oscilloscope display for DL140 adjustment •••••••••••••• 5-83
Oscilloscope display for DL160 adjustment •••••••••••••• 5-84
Removing the top panel and
the module compartment cover ••••••••••••••••••••••••••• 5-94
Identifying "the +5 V power supply •••••••••••••••••••••• 5-95
9-1
9-2
91516 cable connections •••••••••••••••••••••••••••••••• 9-1
9lS32 cable connections •••••••••••••••••••••••••••••••• 9-2
xii
DAS 9100 Series 91S16-91S32 Service
LIST OF TABLES
Table
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
Page
El~ctrical Specifications: Power Requirements .......•.
Electrical Specifications: 9lS16 Pattern Processor ...•
Electrical Specifications: 9lS32 Control •..•••...•...•
Electrical Specifications: Pattern Data •••••.•........
Electrical Specifications: Strobe and Clock Outputs ...
Electrical Specifications: Clock Rate •..•••..•.••....•
Electrical Specifications: 9lSl6
External Control Signals ..•......•.•••..••.•.••.•.....
Electrical Specifications: 9lSl6
External Start Input and Trigger Output ••..•.•.••.•.•.
Electrical Specifications: 9lS32
External Control Signals..............................
P6464 Electrical Specifications •.•.•.•••.•.•••••..••••
P6464 Environmental Specifications ...•••••.••••....••.
P6460 Electrical Specifications •.••••.••••.•.•.•..•...
P6460 Environmental Specifications •••.••••..••.•••...•
1-15
1-16
1-17
1-18
1-20
1-24
1-25
1-29
1-30
1-32
1-33
1-33
1-34
Power-Up Error Conditions ..•....•..........•........•. 3-11
Menu Sequence and Hardware Location for 9lSl6 •••..•••. 3-l26
Menu Sequence and Hardware Location for 9lS32 •••.••.•• 3-l26
9lS32s in Sequential and Stand-Alone Modes
Menu Sequence to Hardware Location Map •....•...•••..•. 3-l27
9lSl6 Microcode Bit Assignment •••..••.•••..•.•.•....•. 3-l29
9lS32 Strobe/Inhibit Code Bit Assignment •••.•••.••••.. 3-l30
Binary File for Pattern Download
for Static Devices .................................... 3-131
Binary File for Pattern Download
for Dynamic Devices •..•.•••••••••••••••.•..••.•••••.•. 3-l33
Sample Pattern Download from Host
Controller Program for Static Devices •••••••......•••• 3-l36
Sample Pattern Download for Dynamic
Devices Controller Program (Keep-Alive) •••...••.•.•.•• 3-l39
5-1
Equipment Needed for the P6464 Check ••..•••••••.•••.•• 5-88
9-1
9-2
9lSl6/9lS32 P2 Signal Detail •.•••••••••••••..•••.••.•. 9-3
9lSl6 Test Points, Jumpers, and Adjustments
(Component Listing)................................... 9-4
9lSl6 Test Points, Jumpers, and Adjustments
(Signal Listing) ••••••.•••.•••.•.•.•••.•••••••••.••••. 9-6
91S32 Test Points, Jumpers, and Adjustments
(Component Listing)................................... 9-8
9lS32 Test Points, Jumpers, and Adjustments
(Signal Listing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
91Sl6 Signal Glossary ••••••••••••••••••••.•••••..•.•.. 9-12
9lS32 Signal Glossary .•.•.•••..•••••..•••••.••.•.••..• 9-23
9-3
9-4
9-5
9-6
9-7
xiii
DAS 9100 Series 91S16-91S32 Service
OPERATOR-- S SAFETY SUMMARY
The general safety information in this summary is for both
operator and service personnel. Specific cautions and warnings
are found throughout the addendum where they apply but may not
appear in this summary.
TERMS
IN THIS ADDENDUM
CAUTION statements identify conditions or practices that could
result in damage to the equipment or other property.
WARNING statements identify conditions or practices that could
result in personal injury or loss of life.
TERMS AS MARKED ON EQUIPMENT
CAUTION indicates a personal lnJury hazard not immediately
accessible as one reads the marking, or a hazard to property,
including the equipment itself.
DANGER indicates a personal injury hazard immediately accessible
as one reads the marking.
SYMBOLS AS MARKED ON EQUIPMENT
DANGER - High voltage.
Protective ground (earth) terminal.
ATTENTION - refer to manual.
GROUNDING THE PRODUCT
The mainframe in which this product is installed is intended to
operate from a power source that does not apply more than 250 V
rms between the supply conductors or between either supply
conductor and ground.
This product is grounded through the mainframe in which it is
operating. To avoid electrical shock, plug the power cord of the
mainframe into a properly wired receptacle before connecting to
the product. A protective-ground connection by way of the
grounding conductor in the power cord is essential for safe
operation.
xiv
DAS 9100 Series 91516-91532 Service
OPERATOR--S SAFETY SUMMARY (cont.)
DANGER ARISING FROM LOSS OF GROUND
Upon loss of the protective ground connection, all accessible
conductive parts (including keys and ~ontrols that may appear to
be insulated) can render an electric shock.
DO NOT OPERATE WI'rIIOUT COVERS
To avoid personal injury, do not operate this product without
mainframe covers or panels installed. Circuit boards and
components can become very hot during operation.
DO NOT OPERATE IN EXPLOSIVE ATMOSPHERES
To avoid explosion, do not operate this product in an explosive
atmosphere unless it has been spefically certified for such
operation.
xv
DAS 9100 Series 91S16-91S32 Service
SERVICE SAFETY SUMMARY
POR QUALIPIED SERVICE PERSONNEL ONLY
Refer also to the preceding
Operator~s
Safety Summary.
DO NOT SERVICE ALONE
Do not perform service or adjustment of this product unless
another person capable of rendering first aid and resuscitation
is present.
USE CARE WBE!f SERVICING WITH POWER ON
Dangerous voltages exist at several points in this product.
avoid personal injury, do not touch exposed connections and
components while power is on.
To
Disconnect power before soldering or replacing components.
DO NOT WEAR JEWELRY WBE!f SERVICING
Remove jewelry prior to servicing. Rings, necklaces, and other
metallic objects could come into contact with dangerous voltages.
NOTE
Observe safety precautions stated in the DAS 9100
Series Service Manual concerning CRT safety, X-ray
emission, and loose objects.
xvi
Options
DAS 9100 Series 91516-91532 Service
OPTIONS
There are no options to the 91516 or 91532 Pattern Generator modules.
2-1
Operating Instructions
CAS 9100 Series 91S16·91S32 Service
SECTION 3
OPERATING INSTRUCTIONS
This section describes installation requirements for the 91 S 16 and 91 S32 Pattern Generator
modules and their probes. It also provides a description of operator's checkout procedures for the
modules and probes. If your instrument has a lower serial number, have a qualified service
technician verify that you have the 22 ampere supply installed. Refer the technician to Service
Information: Verifying Installation of the Upgraded + 5 V Power Supply in the Test and Verification
section of this addendum.
Repackaging Information. All 9100 Series products are shipped in specially designed transportation packaging. Keep this packaging for use whenever you ship DAS products. If the original
packaging is no longer fit for use, contact your nearest Tektronix Field Office and obtain new DAS
packaging.
If you need to ship any part of your 91 S16 or 91 S32 system to a Tektronix Service Center, please
send in all parts of your system: the 91S16 andlor 91S32s and all of their probes.
When you ship a product to a Tektronix Service Center, be sure to attach an identifying tag to the
product (inside the-packaging). On this tag include your name, the name of your company, the name
and serial number of the enclosed product, and a description of the service requested.
CONFIGURATION AND UPDATE REQUIREMENTS
CONFIGURATION REQUIREMENTS
The 91 S 16 module can be installed in any DAS slot supplied by the upgraded 22 ampere 5 volt
power supply (pin 620-0296-01). DAS 9100 instruments with the following serial numbers and
greater will automatically have the upgraded power supply installed:
•
Monochrome DAS 9109, serial numbers 8050326 and higher
• Color DAS 9129. serial numbers 8060100 and higher
• DAS 9119, serial numbers 8010102 and higher
If your instrument has a lower serial number, have a qualified service technician verify that you have
the 22 ampere supply installed. Refer the technician to the section at the back of this addendum
(behind the goldenrod page) titled Service Information: Verifying Installation of the Upgraded + 5 V
Power Supply.
Only one 91 S 16 module may be installed in the DAS system. If first generation 91 P16/P32 Pattern
Generator modules are installed in the DAS. you must remove them; you cannot have both
91 S16/S32 and 91 P16/P32 modules installed at the same time.
The 91 S32 module can be used as a channel expander for the 91 S16 or as discrete pattern
generator. A maximum of five 91S32 modules can be installed with one 91S16 module, or a
maximum of six 91 S32s can be installed without a 91 S 16. 91 S32s can be installed in any DAS slot
supplied by the upgraded 22 ampere 5 volt power supply.
When more than one pattern generator module is installed in the DAS, the modules are connected
by a ribbon cable which attaches to the top of each circuit board. This ribbon cable distributes clock
signal to each module, and provides addresses and control signals to the 91 S32s when used in
FOLLOWS 91S16 mode.
As an expander, the first 91 S32 module must be in the slot next to the 91 S 16. Additional 91 S32
mpdules need to be in adjacent slots.
3-1
Operating Instructions
DA5 9100 5eries 91516-91532 Service
NOTE
91A04A and 91AE04A Data Acquisition Modules must be installed in slot
numbers higher than the 91516 and 91532 modules.
91S32 TERMINATOR CONNECTORS. 91 S32 modules contain a series of terminator connectors immediately below the interconnect cable card-edge connectors. These connectors are used
to terminate the clock, address, and control signals passed over the interconnect cable. Only the
91 S32s at the end of the signal path should have these terminators in place; you should remove the
terminators from all intermediary boards.
When a 91 S16 is used to control 91 S32s, the 91 S16 provides the clock and address signals.
Hence. only the 91S32 farthest from the 91S16 should have its terminators installed (15
terminators). The following pin numbers should have terminators in place: J202, J204, J302. J304.
J306. J308, J310, J312, J314, J316, J318, J320, J322, J324, and J102. J102 is located below and
to the right of the other terminator connectors. The only pins that should not have terminators installed are J206 and J208. Refer to Figure 3·1.
91S16 - - - - ,
91 S32 - - - - - ,
JUMPERS REMOVED
"0
--...I.. •••... •••... •••... ..'1 ..
D~O~OW 0:
91 S32 - - - - - ,
JUMPERS REMOVED -_........
•••
......
•••
•••
•••
•••
DJDWJU
91 S32 ------.,
THESE JUMPERS IN PLACE
••
II
0
0:.
..
'1
~------------------~
::e
0 0 0 D·
-8 iill GEJ []
O~\
~ ~
NO JUMPER
J206 J208
g-JUMPER
J102
5397·08
Figure 3·1. Terminator configuration for 915328 with 91516.
3-2
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
When 91832s are used without a 91816 module, the outermost 91832 modules should have the
following terminators in place: J206 and J208. Remove the rest of the terminators. Any intermediate 91 832 modules should have all their card-edge connector terminators removed. (No terminator
on J102.) Refer to Figure 3·2.
91S32
THESEJUM~
IN PLACE
91 S32
J1J~ J J:--~~2JUMPER
LJr-------.:.;;;...:..:::....;....~-1
···············. 0
JJJ]JJJ J:
:: :: :: :: : : 0
J]J]J]J J:
•••
91S32-----~LJ
91S32--~
OJ
-----,U
JUMPERS REMOVED
JUMPERS REMOVED
.....,
.1.
•••
•••
II
LJr----------------------1
~---------------------------~
5397·09
Figure 3-2. Terminator configuration for stand alone 91S32s.
MODULE INSTALLATION
The following paragraphs assume you are already familiar with the procedures for removing the
mainframe top panel and cover, and with the procedures for installing modules into the mainframe
bus slots. If you are not familiar with these procedures, refer to the Operating Instructions section
of the DAS 9100 Series Operator's Manual.
Do not remove or install a 91816 or 91 832 module until you have read the following warnings, cautions. and configuration requirements.
3-3
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
WARNING
I
When installing or removing instrument modules, the operator may gain
access to the mainframe's module compartment only. Unless you are a
qualified service technician, do not open any other compartments within the
mainframe. Other compartments contain hazardous voltages.
~
When modules are being installed, the mainframe should be turned off and
unplugged from its power source. Damage to the module's circuitry may
occur if the module is installed while the mainframe is receiving power.
Installing a Module into the DAS
Figure 3-3 illustrates the location of a module in the mainframe. Refer to the figure while reading the
following instructions.
~
If a 91 S 16 or 91 S32 module is installed in a slot that is not supplied by the 22
amp 5 volt power supply, the module may not function correctly due to
current overload.
As long as all DAS bus slots are supplied by the 22 amp +5 V power supply. there are no power-related slot restrictions.
• Be sure power is off and the power cord is unplugged before attempting to install a module.
• Refer to Section 2: Operating Instructions in the DAS 9100 Series Service Manual (pin 0625848-00) for instructions on removing the mainframe top panel and module compartment
cover.
The module may be damaged if it is installed or removed while the mainframe
is receiving power.
1. Remove the mainframe top panel and module compartment cover. Do not remove the power
supply cover.
2.
Position the module over the selected bus slot. with the yellow rejector tab toward the front of
the mainframe. Make sure this tab is parallel to the module.
3.
Insert the module between the guide slots at the top of the mainframe. This procedure is
easiest if you align the module with the rear guide first.
4.
Slide the module down through the slots until its connectors rest on top of the bus slot
connectors on the interconnect board.
5.
Push the module down into the bus slot connectors. Press firmly on the board but do not press
on components.
3-4
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
EJECTOR TAB (down)
5397-10
Figure 3-3. Installing an instrument modute in the mainframe.
Installing the Interconnect Cable
Each 91 S32 is shipped with a six-connector interconnect cable. This cable distributes the clock
signal from the 91 S16, or from the 91 S32 nearest the Trigger/Time Base module, to the rest of the
91 S32s installed in the oAS. It also distributes the vector RAM address to the 91 S32s when
operating in Follows 91S16 mode.
You must cut any unnecessary connector blocks off of your interconnect cable or system
performance will be degraded. Use a sharp razor blade to trim the unneeded cable and connector
-blocks off. Make your cut as close to the last needed connector block as possible. Do not leave any
frayed ends.
To install the interconnect cable, simply align the connector blocks with the card edge connectors
on top of each 91S16 and 91S32 module, and press the connector blocks firmly in place. When
seated, the top of the connector blocks should be roughly level with the top of the circuit boards.
The red line on the interconnect cable should face toward the back of the oAS mainframe.
3-5
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
CONNECTING THE PATTERN GENERATOR PROBES
The 91 S 16 and 91 S32 Pattern Generator modules use both pattern generator probes (to output
singals) and an external control probe (to acquire external clock, inhibit, pause, etc.). The P6464
Pattern Generator probe supplies the pattern to the system under test for both 91 S16 and 91 S32
modules. The external control probe acquires external clock, interrupt, pause, (etc.) signals from an
external device and provides them to the pattern generator. There are two different external control
probes; one used when a 91 S 16 is installed in the DAS, and a different probe for when only 91 S32s
are present.
The 91 S 16 uses a P6460 Data Acquisition probe as an external control probe. This optional probe
is refered to as the P6460 External Control Probe in this addendum. Any time a 91 S 16 module is in·
stalled in the DAS, the P6460 serves as the external control probe. The 91 S16 also has two
miniature phono connectors on the back of the module for EXT START (external start) and TRIG
OUT (trigger·out) signals.
If only 91 S32s are installed in the DAS, the P6452 Data Acquisition Probe attached to the DAS
Trigger/Time 8ase module serves as the external control probe. This DAS standard accessory
probe is referred to as the P6452 External Clock Probe in this addendum.
Specifictions for the P6464 and P6460 probes can be found in the Specifications section of this ad·
dendum. Specifications for the P6452 probe can be found in the DAS 9100 Series Operator's
Manual.
Connecting P6464 Pattern Generator Probes
The P6464 can be used with either 91S16 or 91S32 Pattern Generator modules. The 91S16 has
three pod connector locations (from top to bottom: A, 8, and C). The first two locations can
accommodate one P6464 TTUECL Pattern Generator Probe each. The bottom connector is for the
optional P6460 Data Acquisition Probe. The 91 S32 has four pod connector locations (from top to
bottom: A, 8, C, and D). All four locations accommodate one P6464 each.
When connecting a probe to a module, first find the bus slot where that module is installed. Once
you have identified the correct bus slot, look through the back.panel opening and locate the pod
connectors.
WARNING
I
Stop the pattern generator before connecting or disconnecting a probe.
Failure to stop the pattern generator may result in damage to the pattern
generator module.
NOT£
When connecting probes to a module with more than one pod connector, it is
easiest to connect the first probe to the bottom connector and then work up.
3-6
Operating Instructions
CAS 9100 Series 91516-91532 Service
NOTE
If you inadvertently connect an acquisition probe to a pattern generator pod
(or vice versa) on the 91S16 or 91S32, the DAS will not notify you of this error. Damage will not occur to the probe.
Refer to Figure 3-4. when reading the following paragraphs.
PODLET
DATA CLOCK
AND STROBE CHANNELS
:::::::;;;;~~
::J- SENSE LEADS
5397-11
Figure 3-4. P6464 Pattern Generator Probe.
The stimulus output of the P6464 probe consists of eight data channels, one clock line, and one
strobe line. Each output consists of an active pin driver (podlet) at the end of an individual flex cable.
The pod lets are designed to slip over .025 inch square pins on your circuit. The square pins should
be on 0.1 inch centers (0.125 inch centers between pairs of square pins). Use gold-plated pins to
prevent corrosion within the podlet connectors.
If your circut does not have square pins, use the grapper tips and lead sets that are provided. One
end of each lead set plugs into the podlet and the other ends slip inside the grapper tips.
The P6464 recieves power from your circuit through three sense leads conncted to the front on the
probe. The red lead (VH) is connected to the higher voltage, the black (VL) lead is connected to the
lower voltage, and the green lead is connected to ground. VH must be connected to a power
source of - 0.5 V to + 5.5 V. VL must be connected to a power source of + 0.3 V to - 5.5 V. However, the difference between VH and VL must be 4.8 to 5.2 V.
Connecting the P6460 External Control Probe to the 91516
The P6460 External Control Probe should be connected to Pod C of the 91 S 16 Pattern Generator
module. If you connect this probe to the wrong pod connector, the DAS will not indicate an error;
however, no damage will occur.
3-7
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
The optional P6460 External Control Probe used with the 91516 Pattern Generator module is the
same probe la~led P6460 Data Acquisition Probe used with the 91 A24 and 91 Ae24 Data
Acquisition Modules. For our purposes, attach the self-adhesive ·P6460 EXTERNAL CONTROL
PROBEw label supplied with the 91516 module. This label should be applied directly over the
existing label on the top of the probe.
Figure 3-5 illustrates the various elements and features of the P6460 probe. Refer to this figure
when reading the following paragraphs.
TOP OF PROBE
P6460 EXTERNAL CONTROL
PROBE LABEL
GRABBER TIP
(12 provided)
BOTTOM OF PROBE
GROUND LEAD
POMONA-----,
HOOK TIP
BACK OF PROBE
5397-12
F'tgure 3-5. P6460 External Control Probe.
3-8
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
Probe Leads and Tips. Each P6460 probe is supplied with a 1a-inch lead set and a package of
12 probe tips (grabber type). Figure 12 shows the connection of leads and tips.
Connect the lead set to the probe, making sure that the set's white lead is on the side of the probe
housing labeled CK (clock). Push the lead set's connector into the probe housing. To disconnect the
lead set, pull on its connector; do not pull on the leads.
Ground Lead Connections. Also provided with each P6460 are two 5-inch ground sense
leads with Pomona Hook tips, and two alligator-clip lead tips. Plug both sets of ground
leads into the probe housing's connectors labeled USERS GND as shown in Figure 3-5.
The middle GND connector, labeled 8, should only be used when the diagnostic lead set is
connected to the probe.
Maximum Non-Destructive Input Voltage.
the P6460 probe is ± 40 V peak.
The maximum input voltage which may be used with
~
Probe circuitry may be damaged if the P6460 is connected to a voltage
source greater than :1:40 V peak.
Connecting the EXT START and TRIG OUT Phono Connectors to the 91516
The 91 S 16 has two minature phono connectors below the probe connectors on the back of the
module. The top phono jack (J180) outputs the external trigger (TRIG OUT) signal to some external
device (typically an oscilloscope). Use the optional 2-meter phono-to-BNC connector cable for this
purpose.
The bottom minature phono jack (J160) receives the external start signal. Typically, you will use the
9·jnch phono-to-phono cable to connect the output of an acquisition module to this external start
input jack.
Connecting the P6452 External Clock Probe to the Trigger/Time Base Module
(91S32 Stand Alone)
Instructions for connecting the P6452 External Clock Probe to the OAS Trigger/Time Base module
can be found in the Operating Instructions section of the DAS 9100 Series Operator's Manual. The
P6452 probe can be used as the external signal source for the 91 S32 Pattern Generator modules in
stand alone configuration; the optional P6460 probe serves as the external control probe whenever
a 91 S16 is installed in the DAS.
To connect a probe to any DAS module:
1.
Once you have identified the correct pod connector, grasp the probe's cable holder.
2.
Align the cable connector with a square-pin pod connector. Be sure the raised tab on the cable holder is facing towards bus slot 0, and is aligned with the opening on the pod connector.
3.
Gently push the cable connector onto the pod connector. Do not force the connection.
3-9
Operating Instructions
CAS 9100 Series 91S16·91S32 Service
Figure 3·6 demonstrates probe connection procedures.
Figure 3·6. Instatling a probe to a pod connector.
To remove a probe from a pod connector, firmly grasp the cable connector and gently pull straight
out; do not pull on the cable itself.
3-10
Operating Instructions
CAS 9100 Series 91516-91532 Service
OPERATOR'S CHECKOUT PROCEDURE
When the DAS mainframe is powered up, all installed 91 S16 and 91 S32 modules will appear on the
power-up configuration display. PASS or FAIL notations appear next to each module to show the
results of that module's power-up testing. Table 3-1 lists and defines the power-up error conditions
for 91 S16 and 91 S32 modules.
Table 3-1
POWER-UP ERROR CONDITIONS
Error Condition
Definition
91 S16 Pattern Generator Module
FAIL
The 91 S16 module has failed the power-up test. The module will not
operate properly. Refer the 91 S16 module with probes to qualified
service personnel.
This failure does not affect the operation of any installed data
acquisition module. If the 91 S16 is being used to control 91 S32s, the
91 S32s may also be disabled by a failure in the 91 S16.
91 S32 Pattern Generator Module
FAIL
The 91 S32 module has failed the power-up test. The module will not
operate properly. Refer the 91 S32 module and its probes to qualified
service personnel.
Make sure the interconnect cable is attached before the DAS is
turned on, otherwise the 91 S32s will fail diagnostics.
If multiple 91 S32's fail on power-up, it is probably because:
1. The interconnect cable is not properly attached.
2. There may be a broken line in the interconnect cable.
3. The terminating jumpers on the 91 S32s have not been properly
set.
If there is only one 91 S32 failure when multiple 91 S32s are installed,
refer that 91 S32 for service. Adjust the remaining modules so that
there are no empty slots between modules.
3-11
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
91S16 CONFIGURATION SUB-MENU FIELDS AND VALUES
NOTE
The 91516 Configuration sub-menu appears only when
installed in the DA5.
a 91516 module is
The following paragraphs explain how to use the 91 816 Configuration sub-menu to set up the
91816 Pattern Generator module. They discuss each menu field and explain the optional values.
Figure 3-7 illustrates the 91816 Configuration sub-menu and its fields. The field names, which
appear in reverse video on the screen, are bracketed [ ] throughout the text. Use the four
directional cursor keys and the NEXT key to move the blinking screen cursor from one field to
another.
Refer to the numbered callouts in Figure 3-7 when reading the following paragraphs. These
numbers serve as visual references and do not imply sequence of use.
1
2
5
4
3
6
7
8
5397-14
Figure 3-7. 91S16 Configuration sub-menu.
Pattern Download From Host Feature. For information about downloading programs and
vectors from a host computer to the 91816 module, see the section of this addendum titled GPIB
Programming. If you are using 91816 and 91832 modules together, also see the paragraphs titled
Pattern Download From Host in the 91532 Configuration 5ub-Menu When Used With 91516
section of this addendum.
3-12
Operating Instructions
CAS 9100 Series 91516-91532 Service
1 PATTERN GENERATOR CONFIGURATION Field
The field directly to the r.ight of the menu title is used to select either the 91 S16 Configuration submenu or the 91 S32 Configuration sub-menu.
NOTE
When a 91516 is installed with one or more 91532s, the 91532 Configuration menu has some fields that are not displayed when only 91532s are
installed in the DA5. If you are using both 91516 and 91532 Pattern
Generator modules, you will need to enter parameters in both the 91516
Configuration sub-menu and the 91532 Configuration sub-menu.
When a 91 S16 is installed in the DAS, the 91 S16 Configuration sub-menu will be displayed as the
default menu. Press the SELECT key when the screen cursor is in this field in order to view the
91 S32 Configuration sub-menu. (The 91 S32 Configuration sub-menu is only available if there is at
least one 91 S32 installed in the DAS.)
2 REGISTER Field
The REGISTER field is used to select the configuration of the 91S16's internal register. This
register can be used as an incrementing or decrementing counter for program loops or to supply an
alternate source of pattern for some program line.
The 91 S16 internal register at power-up is configured to be two 8-bit registers named RA and RS,
however you can use the REGISTER field to select a single 16-bit register named R. When RA and
RS are concatenated into register R, RS bits become the high-order bits of R, and RA bits become
the low-order bits of R.
NOTE
If you have selected the register to be two B-bit registers, only instructions
relating to RB and RA wl1l be displayed. If you have selected the internal
register to be "R, " a single 16-bit register, only instructions relating to R will
be displayed in any of the 91516 menus; no instructions relating to RB or RA
will be displayed. If you have programmed any instructions that use the
register in one configuration, you cannot select the other register configuration untJI you have deleted those instructions from the program.
To select the 91516 internal register's configuration:
1.
Move the screen cursor to the REGISTER field.
2.
Press the SELECT key until the desired value appears in the field.
3 POD Heading
The POD heading is used to display the name of the pods associated with the 91 S16's data probes.
The DAS employs a numbering scheme using bus slot numbers to identify specific circuit boards
and letters to identify specific probes attached to each circuit board.
Each P6464 Pattern Generator probe and P6460 External Control Probe is connected to a specific
socket on the back of the 91 S16 card referred to as a pod connector. The name of each pod connector is called the pod I.D. (pod identification).
3-13
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
A pod 1.0. consists of a number and a letter. The number corresponds to the DAS slot number
where the 91 S16 card resides. The letter refers to the pod on that particular 91 S16. For instance, a
pod labeled 6B would correspond to the second pod on the 91S16 installed in DAS slot 6.
In the case of the 91 S16, Pod A and Pod B are reserved for P6464 Pattern Generator Probes; Pod
C is reserved for the optional P6460 External ContrOl Probe.
4 P6464 OUTPUT LEVEL Field
The P6464 OUTPUT LEVEL field is used to select the output level for the P6464 Pattern Generator
Probe. This probe outputs the data, strobe, and clock to a circuit/device under test. The P6464
Probe has two output levels, TTL and ECL. You can select the output levels for each pod
independently.
To select the output level for the P6464 probe:
1.
Move the screen cursor to the P6464 OUTPUT LEVEL field.
P6464
OUTPUT LEVEL
[TIL]
2.
Press the SELECT key until the desired output level appears in the field.
[ECL]
5 CLOCK POLARITY Field
The CLOCK POLARITY field is used to specify whether the clock supplied to the device under test
is a rising edge signal or a falling edge signal at the start of each cycle. Each pod has its own clock
line, and you can set the clock edge for each pod independently. At power-up, all the clocks are set
to rising edge Signals.
To specify the clock's edge:
1.
Move the screen cursor to the CLOCK POLARITY field.
CLOCK
POLARITY
[5 ]
2.
Press the SELECT key until the desired value appears in the field.
The DAS displays optional values in this order:
(5 ]
[L 1
6 CLOCK INHIBIT MASK Field
The CLOCK INHIBIT MASK field is used to specify whether or not the clock output responds to the
inhibit signal. If the CLOCK INHIBIT MASK field is set to 0 (unmasked), the clock signal for that data
pod will be tri-stated whenever the inhibit signal is asserted. If the CLOCK INHIBIT MASK field is
set to 1 (masked), the clock signal for that particular pod will continue to be output even if the inhibit
signal is asserted. The default value for this field is 0 (unmasked).
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
To set the CLOCK INHIBIT MASK Field:
1.
Move the screen cursor to the CLOCK INHIBIT MASK field:
CLOCK
INHIBIT MASK
[0]
2.
Use the data entry keys to enter a 1 (masked).
CLOCK
INHIBIT MASK
[1 ]
7 STROBE INHIBIT MASK Field
The STROBE INHIBIT MASK field is used to specify whether or not the strobe output responds to
the inhibit signal. If the STROBE INHIBIT MASK field is set to 0 (unmasked), that particular pod's
strobe line will be tri-stated whenever the inhibit signal is asserted. If the STROBE INHIBIT MASK
field is set to 1 (masked), that pod's strobe line will not be tri-stated, even if the inhibit signal is asserted. The default value for this field is 0 (unmasked).
To specify the strobe inhibit mask:
1. Move the screen cursor to the STROBE INHIBIT MASK field.
STROBE
INHIBIT MASK
[0]
2.
Use the data entry keys to enter a 1
[1 ]
8 POD CLOCK Field
The POD CLOCK field is used to select the pod clock delay relative to the start of the pattern generator cycle. This feature allows you to adjust the timing of one pod relative to another. You could set
one pod to output its data and clock signal 5 ns before the main clock edge, and set another pod to
output data 5 ns after the main clock edge. The timing difference between the two pods would then
be 10 ns.
Use the INCR or DECR keys to select a pod clock delay value. You can set each pod individually to
output its data, strobe, and clock signals up to 5 ns before or 5 ns after the pattern generator clock
edge. This field adjusts timing in 5 ns increments. The default value for this field is 0 ns.
Note: If you are running the 91 S 16 with 91 S32s at 50 MHz. there are some restrictions on the pod
clock delay value. Refer to the Timing sub-menu description for details.
To increase or decrease the POD CLOCK delay:
1. Move the screen cursor to the POD CLOCK field.
POD CLOCK
[ OnS]
2.
Use the INCR key to increase the delay value, or the DECR key to decrease it. The DAS displays the delay values in this order:
[ -5nS]
[
OnS]
[ +5nS]
3-15
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
91S32 STAND ALONE CONFIGURATION SUB-MENU FIELDS AND
VALUES
NOTE
The 91532 Configuration menu is available only when 91532 Modules are
installed in the DA5. A slightly different version of the 91532 Configuration
sub-menu is displayed if both 91516 and 91532 Pattern Generator modules
are installed in the DA5 at the same time. 5ee the section of this addendum
titled 91S32 Configuration Sub-Menu When Used With 91S16 if you are
using both types of pattern generator modules together.
The following paragraphs explain how you can use the 91 S32 Configuration sub-menu to set up
the pattern generator. Each sub-menu field is described and its optional values explained.
Figure 3-8 illustrates the 91 S32 Configuration sub-menu and its fields. The fields, which appear in
reverse video on the screen, are bracketed [ ] throughout the text. The four directional cursor keys
and the NEXT key can be used to move the blinking screen cursor from one field to another.
Refer to the numbered callouts in Figure 3-8 when reading the following paragraphs. These
numbers serve as visual references and do not imply sequence of use.
'1
2
6
5
4
PATTERN GENERATOR CONFIGURATION: 91S32
c-------------------------
- END SEQ:
KIi
I
iii:E.!ii
iiiI.I~
-~=-.:-----.::=-~-=-::==::1----------=t~==--==-:=--~:~=---~----===~-~----;:::I~
'-P6464'
POD
1 50
OUTPUT LP)EL
25C
IIiJ
358
4 5A
5 40
6 4C
7 48
IIiJ
--_
3
'--STR-Off'
___ ---L---
IttlIBIT MASK INHIBIT IliSK
'poo CLIXK
CLOCK''- CLOCi(--1
PClARITY
DOD
DOli
DOli
11m
IGI
11m
..
D
D
0
0
0
0
D
D
0
11m
D
0
D
11m
11m
5397-15
Figure 3-8. 91S32 Stand Alone Configuration sub-menu.
3-16
7
8
9
Operating Instructions
CAS 9100 Series 91516·91532 Service
Pattern Download From Host Feature. 91 S32 modules can use the static device version of the
Pattern Download From Host feature (91 S 16 optional). This feature allows you to download
extensive programs into the pattern generator from a GPIS controller. Refer to the GPIB
Programming section of this manual for details. You should also read the paragraphs titled Pattern
Download From Host in the 91S32 Configuration Sub-Menu When Used With 91S 16 section of this
addendum.
1 PATTERN GENERATOR CONFIGURATION Field
This field (directly to the right of the menu title) indicates the title of the 91 S32 Configuration sub·
menu. The 91 S32 Configuration sub-menu is the only option available when 91 S32s are the only
pattern generator modules installed in the DAS.
NOTE
If you are using a 91$16 with 91S32s, this field will default to the 91S16
Configuration sub-menu. See the section of this addendum titled 91 S32
Configuration Sub-Menu When Used With 91 S16.
2 END SEa Field
The 91 S32 pattern generator normally executes all the sequence lines in memory and then
automatically restarts from the beginning. However, not all patterns require the full 2047 lines of
available memory. This field allows you to specify some smaller number to reset pattern execution
to the first sequence. This number can be any value between 0 and 2047 (ASEQ) or A 0 and S 1023
(RSEQ).
The 91 S32 modules will repeatedly execute the program entered between the number in the
START SEQ: field of the 91 S32 Program: Run sub-menu (usually SEQ O) and the sequence
number specified in the END SEQ field.
The default value for the END SEQ field is END SEQ 2047. Note that this field will display END SEQ
2047 if you have set the SEQ field to ASEQ (absolute sequence) in the 91 S32 Run sub-menu. If you
have set the SEQ field to RSEQ (relative sequence), the allowable range will be Page A, 0 through
1023, and Page S, 0 through 1023. See the 91 S32 Program: Run sub-menu section SEQ field description for details about the ASEQ and RSEQ options.
To specify the END SEQ:
1.
Move the screen cursor to the END SEQ field.
END SEQ [2047]
2.
Use the data entry keys to enter the END SEQ number. For example, to enter sequence
number 500:
END SEQ [ 500]
3-17
Operating Instructions
DAS 9100 Series 91516-91532 Service
3 LOOP Field
This field is used to specify the 91 S32 operating mode. There are two possible selections for this
field: LOOP and FREE RUN. The 91 S32 normally executes all the sequence lines entered into
memory starting with sequence 0 and ru~ning through to the sequence number specified in the
END SEa field, or until the end of memory if no END SEa value has been specified. The pattern
generator will execute this program repeatedly until you press the STOP key. This is called FREE
RUN mode.
If you only want the pattern generator to loop through its program a certain number of times and
then stop. select LOOP. Loop mode displays a special LOOP field where you can enter the number
of times you want the pattern generator to execute its program. Maximum value for this field is
65535.
To select FREE RUN or LOOP mode:
1.
Move the screen cursor to the field immediately to the right of the END SEa field:
END SEa [2047] [ LOOP] [
2.
1]
Press the SELECT key until the desired value appears in the field.
END SEa [2047] [ LOOP] {
1]
[FREE RUN]
To enter a value for the [LOOP] field:
1.
Move the screen cursor to the field immediately to the right of the LOOP field.
2.
Use the data entry keys to enter the number of times you want the pattern generator to execute
its program. For example, to run through the lOOp 1000 times, and then stop. enter 1000:
END SEa [2047] [ LOOP] [1000]
4 POD Heading
The POD heading is used to display the number of 91 S32 boards installed in the DAS and the name
of each data pod available. A POD refers to the specific connector on the back of the 91 S32 where
a P6464 probe is connected.
The name of each pod is referred to as pod 1.0. (pod identification). A pod 1.0. consists of a number
and a letter. The number corresponds to the DAS slot number where that particular 91 S32 card resides. The letter refers to the pod on that particular 91 S32. For instance, a pod labeled 6C would
correspond to the third pod on the 91 S32 installed in DAS slot 6.
5 P6464 OUTPUT LEVEL Field
The P6464 OUTPUT LEVEL field is used to select the output level for the P6464 Pattern Generator
Probe. This probe outputs the data, strobe, and clock to a circuit/device under test. The P6464
Probe has two output le,vels. TTL and ECL. You can select the output levels for each pod
independently.
3-18
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
To select the output level for the P6464 Probe:
1.
Move the screen cursor to the P6464 OUTPUT LEVEL field.
P6464
OUTPUT LEVEL
[TTL]
2.
Press the SELECT key until the desired output level appears in the field.
[ECL]
6 CLOCK POLARITY Field
The CLOCK POLARITY field is used to specify whether the clock supplied to the device under test
is a rising edge signal or a falling edge signal at the start of each cycle. Each pod has its own clock
line. and you can set the clock edge for each pod individually. In default, all the clocks are set to rising edge signals.
To specify the clock's edge:
1.
Move the screen cursor to the CLOCK POLARITY field.
CLOCK
POLARITY
[S ]
2.
Press the SELECT key until the desired value appears in the field.
The DAS displays optional values in this order:
[S ]
[1.. ]
7 CLOCK INHIBIT MASK Field
The CLOCK INHIBIT MASK field is used to specify whether or not the clock output responds to the
inhibit signal. If the CLOCK INHIBIT MASK field is set to 0 (unmasked), the clock signal for that data
pod will be tri-stated whenever the inhibit signal is asserted. If the CLOCK INHIBIT MASK field is
set to 1 (masked), the clock signal for that particular pod continues to be output even if the inhibit
signal is asserted. The default value for this field is 0 (unmasked).
To set the CLOCK INHIBIT MASK Field:
1.
Move the screen cursor to the CLOCK INHIBIT MASK field.
CLOCK
INHIBIT MASK
[0]
2.
Use the data entry keys to enter a 1 (masked).
[ 1]
3-19
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
8 STROBE INHIBIT MASK Field
The STROBE INHIBIT MASK field is used to specify whether or not the strobe output responds to
the inhibit signal. If the STROBE INHIBIT MASK field is set to 0 (unmasked). that particular pod's
strobe line will be tri-stated whenever the inhibit signal is asserted. If the STROBE INHIBIT MASK
field is set to 1 (masked), that pod's strobe line will never be tri-stated, even if the inhibit signal is asserted. The default value for this field is 0 (unmasked).
To specify the strobe inhibit mask:
1.
Move the screen cursor to the STROBE INHIBIT MASK field.
STROBE
INHIBIT MASK
[0]
2.
Use the data entry keys to enter a 1 (masked).
[1 ]
9 POD CLOCK Field
The POD CLOCK field selects the pod clock delay value relative to the start of the pattern generator
cycle. This feature allows you to adjust the timing of one pod relative to another. You could set one
pod to output its data and clock signal 5 ns before the main clock edge, and set another pod to out·
put data 5 ns after the main clock edge. The timing difference between the two pods would then be
10 ns.
Use the INCR or DECR keys to select a pod clock delay value. You can set each pod individually to
output its data, strobe, and clock signals up to 5 ns before or 5 ns after the pattern generator clock
edge. This field adjusts timing only in 5 ns increments. The default value for this field is 0 ns.
Note: If you have selected a clock rate of 50 MHz., all pod clock values must be set to 0 ns.
To increase or decrease the POD CLOCK delay:
1.
Move the screen cursor to the POD CLOCK field.
POD CLOCK
[ 0 nS]
2. Use the INCR key to increase the delay value, or the DECR key to decrease it. The DAS will dis·
play the delay values in the following order:
[-5 nS]
[ 0 nS]
[+5 nS]
3·20
Operating Instructions
CAS 9100 Series 91516-91532 Service
91S32 CONFIGURATION SUB-MENU WHEN USED WITH 91S16
NOTE
This version of the 91532 Configuration sub-menu only appears when both
91516 and 91532 modules are installed in the DAS at the same time.
The following paragraphs explain how to use the 91532 Configuration sub-menu when both 91516
and 91 S32 pattern generator modules are installed in the DAS. Refer to the preceding sub-section
titled 91532 Stand-Alone Configuration Sub-Menu if you do not have a 91516 installed.
Figure 3-9 illustrates the 91532 Configuration sub-menu as it appears when both 91516 and
91 S32 modules are installed. There are several small differences between this sub-menu and the
91532 Configuration sub-menu that appears when only 91 S32s are installed; most of these
differences are concerned with Follows 91 S16 mode and the keep-alive feature.
Fields that appear in reverse video on the DA5 screen are bracketed [ ] throughout the text. Use
the four directional cursor keys and the NEXT key to move the blinking cursor from one field to
another.
Refer to the numbered callouts in Figure 3-9 when reading the following paragraphs. These
numbers are visual references only and do not imply sequence of use.
1
2
3
6
5
4
5397.16
Figure 3-9. 91532 Configuration sub-menu when used with 91516.
3-21
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
1 PATTERN GENERATOR CONFIGURATION Field
This field (directly to the right of the menu title) is used to select either the 91 S 16 or the 91 S32 Configuration sub-menu display. If only 91 S32s are installed, a slightly different version of the 91 S32
Configuration sUb-menu will be displayed; this version of the sub-menu is described in a separate
section titled 91S32 Stand-Alone Configuration Sub-Menu.
If both 91S16 and 91S32 modules are installed, the 91S16 Configuration sub-menu will be
displayed first; the 91 S32 Configuration sub-menu will only be displayed if you press the SELECT
key when the screen cursor is in this field. Pressing SELECT repeatedly causes the DAS to
alternately display the 91S16 and 91S32 Configuration sub-menus.
To alternately display the 91S16 or 91S32 Configuration sUb-menus:
1.
Move the screen cursor to the field directly to the right of the menu title.
PATTERN GENERATOR CONFIGURATION: [91S16]
2.
Press the SELECT key until the 91 S32 Configuration sub-menu appears in the field.
PATTERN GENERATOR CONFIGURATION: [91 S32]
3.
Press SELECT again if you want to return to the 91S16 Configuration sub-menu.
2 91532 CLOCK Field
NOTE
The 91S32 CLOCK field will only appear if a 91S16 is installed in the DAS. If
no 91S16 is installed, the 91S32's clock rate is set in the Timing sub-menu.
When 91 S32 modules are used with a 91 S16 module, the 91 S32 modules receive their system
clock from the 91S16 module. The 91S32 modules usually operate at the same clock rate as the
91S16 module, but they can be operated at one-half or one-fourth the clock rate of the 91S16.
For example, if you enter a 2 in the 91 S32 CLOCK field, you can then program the 91 S16 clock to
run at 50 MHz (programmed in the Timing sub-menu) and the 91532 modules will run at 25 MHz.
Even at slower clock rates, you may find it convenient to run the 91 S16 faster than the 91 S32s. The
default divisor is 1.
Note: There are some pod clock delay restrictions when operating 91 S16 and 91 S32 modules at 50
MHz. Refer to the Timing sub-menu.
3-22
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
To change the clock divisor for the 91S32 modules:
1.
Move the screen cursor to the 91832 CLOCK field.
91832 CLOCK: 91816 CLOCK DIVIDED BY [1]
2.
Press the INCR key to increase the divisor value or the DECR key to decrease the value. The
DA8 will display increasing divisor values in a 1-2-4 sequence. For example, to change the
divisor to 2, press the INCR key once.
91832 CLOCK: 91S16 CLOCK DIVIDED BY [2]
NOTE
The 91516 and 91532 combination can not run faster than 25 MHz (40 ns). If
you program the 91516 to run at 50 MHz and set the 91532 CLOCK field to
91516 DIVIDED BY 1, the 91532 modules may not work properly.
3 91S32 MODE Field
The 91S32 module has two operating modes when used with a 91S16 module: Follows 91S16
mode and Sequential mode. Follows 91 S 16 mode is the default mode.
FOLLOWS 91S16 Mode and the MEMORY RELOAD FROM HOST Field
In Follows 91 S 16 mode, the 91 S32s receive both its clock and vector-memory addresses from the
91 S 16 module via the interconnect cable. In this mode, when the 91 S 16 program executes a jump
from SEa 100 to SEa 50, the 91 S32s will also jump from SEa 100 to SEa 50. The 91 S32s follow
the sequence flow instructions programmed in the 91 S 16.
In Follows 91S16 mode the 91S32's memory is divided into two 1024-vector pages called Page A
and Page B. Each memory page matches the 1024-vector depth of the 91 S16's memory. When the
pattern generator is started, the 91 S 16 outputs its 1024-vector pattern while the 91 S32s output
the pattern in Page A. When the 91 S 16 reaches an INCR PAGE (Increment Page) command, it instructs the 91 S32s to switch to Page B. (Note: Pattern Download From Host does not use the
INCR PAGE command to switch between Page A and Page B.)
Pattern Download From Host
Follows 91 S 16 mode also provides a Pattern Download From Host feature that allows you to
reload the 91 832's vector memory from a host computer or mass storage device while the pattern
generator is running. The Pattern Reload From Host feature allows you to use a pattern longer than
2047 lines. It also enables you to develop a pattern generator program on a host computer and enter it into the DA8 remotely.
NOTE
In order to use the Pattern Download From Host feature, the DAS must be
connected to a host computer using General Purpose Interface Bus (GPIB)
connections and protocols. Instructions for making these connections and
formating the data to be downloaded to the pattern generator cards can be
found in the section of this addendum titled GPIB Programming, the DAS
Option 06: I/O Communication Interface Operator's Manual Addendum, and
in Section 12: GPIB Programming in the DAS 9100 Series Operator's
Manual.
3-23
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
There are two versions of Pattern Download From Host. Pattern Download For Static Devices can
be used with either a 91 S16, 91 S32s, or a combination of the two. Pattern Download For Dynamic
Devices (Keep-Alive) requires a 91 S 16 and at least one 91 S32 module.
Pattern Download For Static Devices.
This version of the Pattern Download feature can be
implemented using DAS Option 02 or DAS Option 06 (GPIB commands via the GPIB or RS-232 interfaces). Using Pattern Download For Static Devices, the pattern generator outputs all its vectors,
maintains the last vector at the probe tips while the next block of vectors is downloaded from the
host computer, and then resumes outputting vectors. This process can be repeated until the entire
program has been executed.
Pattern Download For Dynamic Devices (Keep-Alive). This version of the Pattern Download
feature provides some clock and vector output during the interval when the 91 S32's memory is be·
ing reloaded. Pattern Download For Dynamic Devices is only available when using the Option 06
HSPAT command over the GPIB interface. You must have a 91 S16 and at least one 91 S32
installed, and the pattern generator clock rate is limited to 25 MHz.
Some types of circuitry require constant clock and data inputs. Pattern Download For Static
Devices, described above, does not provide any circuit stimulation while the host computer is
downloading the next block of vectors. For static circuit elements this is not a problem; the device
under test can just wait for the next block of vectors to finish being reloaded. But for dynamic circuit
elements (such as dynamic RAMs), some clock and vector input is necessary to keep the device
active while the reload process is being completed. The 91S16/32 Pattern Generator modules
provide a feature called Keep-Alive to stimulate the circuit until the other page of memory is ready.
In order to use the Keep-Alive feature, you must set the MEMORY RELOAD FROM HOST (FOR
KEEP-ALIVE) Field to ON.
NOTE
Selecting ON in the MEMORY RELOAD FROM HOST (FOR KEEP-ALIVE)
field is only valid if you are using DAS 9100 Option 6: Fast GPIB Programming to perform memory reload. This field enables some instructions in the
91 S 16 Program: Run sub-menu that are only valid using Option 6 GPIB. See
the GPIB of this addendum for detailed instructions about using Keep-Alive.
Reloading the 91S32 memory from a host is possible via RS-232 or slow
GPIB when this field is set to OFF, but the Keep-Alive feature will not be
available.
Keep-Alive is basically a subroutine programmed into the 91 S16 that outputs a limited number of
vectors to the device under test while frequently testing to see if the memory reload operation has
been completed.
Following 91 S 16 control, the 91 S32s execute one 1024-line page of vectors while reloading the
other page. However, it takes longer to reload a page of vectors than it does to execute a page of
vectors. The Keep-Alive sub-routine programmed into the 91 S 16 provides some circuit stimulation
while the 91 S32 reload process is being completed. The 91 S16 is programmed with instructions
that test if the other page of memory has been reloaded. If the other page has been reloaded, the
91S16 instructs the 91532s to switch execution to the newly refilled memory page; if the other
page has not been reloaded, the 91 S 16 loops back through its sub-routine and the pattern
generator continues to output some vectors.
An example of a Keep-Alive routine is provided in the GPIB section of this addendum.
3-24
Operating Instructions
CAS 9100 Series 91516-91532 Service
SEQUENTIAL Mode and the END SEQ Field
When 91 S32s are in Sequential mode with a 91 S16. the two types of modules are clocked together
but execute their programs independently. Pattern generation begins with the lowest numbered
sequence line specified in the 91 S32 Program: Run sub-menu (usually SEa 0) and progresses
sequentially until reaching the sequence number specified in the END SEa field. Program execution
in the 91S32 modules is not affected by branching instructions executed by the 91S16 program.
For example, if the 91 S16 is programmed to jump from SEa 100 to SEa 50. the 91 S32s will not
jump. but continue to execute their program sequentially at SEa 101.
While 91 S32s in Sequential mode are not affected by 91 S16 branch instructions. they are affected
by 91 S 16 halt and pause conditions since the 91 S 16 provides the clock to the 91 S32 modules.
The END SEa field allows you to specify a sequence line number smaller than Page B SEa 1023 as
the last line in your pattern generator program. The END SEa field only appears when Sequential
mode has been selected.
The advantage of Sequential mode is that you can program the 91 S16 to perform conditional
branching and loops while allowing the 91 S32s to supply the usual sequential patterns. One
example of this kind of application occurs when you are using the 91 S 16 to provide addresses to
some memory device while the 91 S32s supply the test vectors.
The default value for the END SEa field is 2047. The numbering scheme for END SEa field is dependent on whether you have selected ASEa (absolute sequence) numbers or RSEa (relative
sequence) numbers in the 91 S32 Program: Run sub-menu. If you have selected ASEa in that submenu, the maximum allowable END SEa field value is 2047. If you have selected RSEa, the
maximum allowable END SEa field value is Page B 1023. The END SEa field format will indicate
which numbering scheme is being used.
To select either FOLLOWS 91516 or SEQUENTIAL mode:
,.
Move the screen cursor to the 91 S32 MODE field.
91 S32 MODE: [FOLLOWS 91 S16] MEMORY RELOAD FROM HOST: [OFF]
(FOR KEEP-ALIVE)
2.
Press the SELECT key until the desired mode appears in the field. The DAS will display the
modes in this order:
[FOLLOWS 91S16]
[SEaUENTIAL
)
NOTE
You cannot switch from FOLLOWS 91S16 mode to SEQUENTIAL mode if
CALL RMT, IF FULL, or IF END instructions are programmed in the 91S16
Program: Run sub-menu. or if the MEMORY RELOAD FROM HOST (FOR
KEEP-ALIVE) Field is set to ON.
3·25
Operating Instructions
CA5 9100 Series 91516-91532 Service
To enable or disable the KEEP-ALIVE feature in FOLLOWS 91516 mode:
1.
Move the screen cursor to the 91S32 MODE field and select FOLLOWS 91S16 mode. Then
move the cursor to the MEMORY RELOAD FROM HOST sub-field.
91S32 MODE: [FOLLOWS 91516] MEMORY RELOAD FROM HOST: [OFF]
(FOR KEEP-ALIVE)
2.
Press the SELECT key until the desired value appears in the field.
91S32 MODE: [FOLLOWS 91S16] MEMORY RELOAD FROM HOST: [ ON]
(FOR KEEP-ALIVE)
To enter a value in the SEQUENTIAL mode END SEQ: sub-field:
1.
Move the screen cursor to the 91 S32 MODE field and select SEQUENTIAL mode. Then move
the cursor to the END SEQ SUb-field.
91 S32 MODE: [SEQUENTIAL] END SEQ [2047]
2.
Use the data entry keys to enter the END SEQ number. For example, enter 500:
91 S32 MODE: [SEQUENTIAL] END SEQ [500]
4 POD Heading
The POD heading is used to display the number of 91 S32 boards installed in the DAS and the
names of each data pod available. A POD refers to the specific connector on the back of the 91832
where a P6464 probe is connected.
The name of each pod is referred to as pod 1.0. (pod identification). A pod 1.0. consists of a number
and a letter. The number corresponds to the DAS slot number where that particular 91 S32 card resides. The letter refers to the pod on that particular 91 S32. For instance, a pod labeled 6C would
correspond to the third pod on the 91 S32 installed in DA5 slot 6.
5 P6464 OUTPUT LEVEL Field
The P6464 OUTPUT LEVEL Field is used to select the output level for the P6464 Pattern Generator
Probe. This probe outputs the data, strobe, and clock to a circuit/device under test. The P6464
Probe has two output levels, TTL and ECL. You can select the output levels for each pod
individually.
To select the output level for the P6464 Probe:
1.
Move the screen cursor to the P6464 OUTPUT LEVEL field.
P6464
OUTPUT LEVEL
[TTL]
2.
Press the SELECT key until the desired output level appears in the field.
[ECL]
3-26
Operating Instructions
DAS 9100 Series 91S16·91S32 Service
6 CLOCK POLARITY Field
The CLOCK POLARITY field is used to specify whether the clock supplied to the device under test
is a rising edge signal or a falling edge signal at the start of each cycle. Each pod has its own clock
line, and you can set the clock edge for each pod individually. In default, all the clocks are set to rising edge signals.
To specify the clock's edge:
1.
Move the screen cursor to the CLOCK POLARITY field.
CLOCK
POLARITY
[5 ]
2.
Press the SELECT key until the desired value appears in the field.
The DAS displays optional values in this order:
[5 ]
[1.. ]
7 CLOCK INHIBIT MASK Field
The CLOCK INHIBIT MASK field is used to specify whether or not the clock output responds to the
inhibit signal. If the CLOCK INHIBIT MASK field is set to 0 (unmasked), the clock signal for that data
pod will be tri·stated whenever the inhibit signal is asserted. If the CLOCK INHIBIT MASK field is
set to 1 (masked), the clock signal for that particular pod will continue to be output even if the inhibit
signal is asserted. The default value for this field is 0 (unmasked).
To set the CLOCK INHIBIT MASK Field:
1.
Move the screen cursor to the CLOCK INHIBIT MASK field:
CLOCK
INHIBIT MASK
[0]
2.
Use the data entry keys to enter a 1 (masked).
CLOCK
INHIBIT MASK
[1 ]
3·27
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
8 STROBE INHIBIT MASK Field
The STROBE INHIBIT MASK field is used to specify whether or not the strobe output responds to
the inhibit signal. If the STROBE INHIBIT MASK field is set to 0 (unmasked). that particular pod's
strobe line will be tri-stated whenever the inhibit signal is asserted. If the STROBE INHIBIT MASK
field is set to 1 (masked). that pod's strobe line will never be tri-stated. even if the inhibit signal is asserted. The default value for this field is 0 (unmasked).
To specify the strobe inhibit mask:
1. Move the screen cursor to the STROBE INHIBIT MASK field.
STROBE
INHIBIT MASK
[0]
2.
Use the data entry keys to enter a 1 (masked).
STROBE
INHIBIT MASK
[1 ]
9 POD CLOCK Field
The POD CLOCK field is used to select the pod clock delay relative to the start of the pattern generator cycle. This feature allows you to adjust the timing of one pod relative to another. You could set
one pod to output its data and clock signalS ns before the master clock edge, and set another pod
to output data 5 ns after the master clock edge. The timing difference between the two pods would
then be 10 ns.
Use the INCR or DECR keys to select a pod clock delay value. You can set each pod individually to
output its data. strobe. and pod clock signals up to 5 ns before or 5 ns after the pattern generator
master clock's selected edge. This field adjusts timing only in 5 ns increments. The default value for
this field is 0 ns.
Note: When operating 91 S16 and 91 S32 modules together at 50 MHz. you must set all pod clock
delay values to - 5 ns.
To increase or decrease the POD CLOCK delay:
1.
Move the screen cursor to the POD CLOCK field.
POD CLOCK
[ OnS]
2.
Use the INCR key to increase the delay value. or the CECR key to decrease it. The CAS displays the delay values in this order:
[ -5nS]
[ OnS]
[ +5nS]
3-28
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
91S16 PROBE SUB-MENU FIELDS AND VALUES
NOTE
The 91 S 16 Setup: Probe sub-menu appears only when the 91 S 16 Module is
installed in the DAS.
The following paragraphs show how to use the 91 S 16 Setup: Probe sub-menu to set up the
91 S16's P6460 External Control Probe. They discuss each menu field and explain all the optional
values.
Figure 3-10 illustrates the 91 S16 Setup: PROBE sub-menu and its fields. The fields, which appear
in reverse video on the screen, are bracked [ ] throughout the text. The four directional cursor keys
and the NEXT key can be used to move the blinking screen cursor from one field to another.
Refer to the numbered callouts in Figure 3-10 when reading the following paragraphs. These
numbers are intended to be a visual reference and do not imply sequence of use.
1
2
3
4
5
6
7
5397·17
Figure 3-10. 91S16 Setup: Probe sub-menu.
3-29
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
1 PATTERN GENERATOR SETUP Field
The field directly to the right of the menu title is used to select either the 91 S 16 Setup: PROBE or
the 91 S16 Setup: TIMING sub-menu display. In default, the 91 S16 PROBE sub-menu is displayed
whenever a 91S16 is installed in the DAS.
2 P6460 INPUT THRESHOLD Field
The P6460 INPUT THRESHOLD field is used to set the threshold level for the P6460 External Control Probe. This probe supplies the 91S16 pattern generator's external clock, interrupt request,
interrupt request qualifier, external jump, pause, and external inhibit lines. In default, the INPUT
THRESHOLD field is set to TTL + 1.40 V.
To change the INPUT THRESHOLD field from TTL to ECl or VAR (variable):
1.
Move the screen cursor to the INPUT THRESHOLD field.
2.
Press the SELECT key until the desired threshold level appears in the field. The DAS will
display the optional values in this order:
[TTL] + 1.40 V
[VAR] [ + 3.70 V]
[ECL]
- 1.30 V
When VAR has been selected, a new field appears to allow you to set the variable voltage level. The
range for this field is between - 6.40 V and + 6.35 V in 50 mV increments. Use the INCR and
DECR keys to set the value for this field.
3 IRQ Field AND QUALIFIER Field
The interrupt signal is supplied to the 91 S16 module via the optional P6460 External Control Probe.
This signal line mus.t be connected to an external source. In order to use the interrupt signal to control the 91 S16, you must abide by the following three rules:
1.
For the internal interrupt to be true for a given clock cycle, the external interrupt signal must
have a 15 ns set-up time relative to the selected edge of the external input clock. In other
words, if you are running the 91 S16 at 50 Mhz (20 ns clock cycles) the external interrupt signal
must occur during the first 5 ns of the current clock cycle or else the interrupt will not be recognized until the next clock cycle.
2.
The interrupt qualifier signal must stay true for 15 ns prior to the interrupt signal becoming
active.
3.
The interrupt mask must be set to 0 (unmasked).
The IRQ (Interrupt Request) field is divided into two parts. The first part specifies whether the
interrupt is disabled or enabled. If it is enabled, another field appears which allows you to specify
whether the interrupt will occur on the rising or falling edge of the external interrupt signal. The second part of the IRQ field specifies the mode the 91 S16 uses to handle interrupts.
IRQ enabled, CAll Mode and IF IRQ Mode
The 91 S16 provides two modes for handling external interrupts. The options are CALL and IF IRQ.
The first method uses a special interrupt servicing routine that suspends program execution when
an interrupt is detected, executes a small subroutine, and then resumes program execution on the
sequence line following the one where the interrupt was received. To use this method you will select
CALL mode in the IRQ field.
3-30
Operating Instructions
OAS 9100 Series 91516-91532 Service
The second method of handling interrupts allows you to program IF IRQ JUMP commands into
specific program lines and transfer program flow without saving a return address. To use this
method you will select IF IRQ mode in the IRQ field.
If you select CALL mode, you must enter the label for an interrupt service routine in the field next to
CALL. You will then enter the same label name in a routine in the 91816 Program: Run sub-menu.
The last line of your servicing routine must contain the RETURN instruction to return program flow
to the line following the one where the interrupt was detected.
The first sequence line of this routine must not contain a sequence flow instruction like JUMP or
RETURN. If the first line does contain a sequence flow instruction, that instruction will be ignored.
If a second interrupt is detected while the pattern generator is performing an interrupt service
routine, the second interrupt will be serviced after the first routine has been completed.
If you select IF IRQ mode, the IRQ line can be tested at convenient points in the pattern generator
program by programming IF IRQ JUMP instructions in the 91816 Program: Run sub-menu. In this
mode, when an interrupt is detected, the pattern generator will automatically jump to another place
in the program and continue executing sequence lines from that point. Different JUMP destinations
can be programmed for each IF IRQ JUMP instruction programmed.
One advantage of the IF IRQ mode is that interrupts will only be serviced at convenient times. (Interrupt masking is possible with CALL mode too, by using the M column in the 91816 Program:
Run sub-menu. The disadvantage is that this method takes longer to program.)
NOTE
If you select CALL in the IRQ mode field, IF IRQ JUMP commands will not be
available in the 91516 Program: Run sub-menu. When in IF IRQ mode, the
RETURN instruction will not be available in the Run sub-menu. If you have already programmed IF IRQ JUMP commands in the Run sub-menu. you can
not change from IF IRQ to CALL mode in this menu. Similarly, if you have
programmed the RETURN instruction in the Run sub-menu, you will not be
able to change from CALL to IF IRQ mode in this menu. To change from one
mode to the other, you will have to remove the mode-specific instructions
from the 91516 Program: Run sub-menu and then return to the Probe submenu to select the other mode.
NOTE
The 91516 Pattern Generator Module automatically resets the interrupt line
before beginning pattern execution. Therefore, if the IF IRQ instruction is
programmed on the first line executed (usually SEQ 0) the interrupt signal
may not meet the required set-up and hold times necessary for the interrupt
to be recognized for this clock cycle; the pattern generator may not jump
from this sequence line.
NOTE
GPIB commands use hardware memory address, not labels. to control the
pattern generator program flow. IRQ ENABLED CALL mode
reserves the first hardware memory location for the interrupt routine address,
thereby shifting all program lines down one memory location. IRQ 018ABLED and IRQ ENABLED IF IRQ mode do not reserve the first memory
location. You must remember which IRQ mode is selected when programming jump addresses via GPIB. See the section of this addendum titled GPI B
Programming for detailed information.
3-31
Operating Instructions
CAS 9100 Series 91516-91532 Service
To enable an interrupt and select either the rising or falling edge:
1.
Move the screen cursor to the IRQ field
IRQ
2.
[DISABLED]
Press the select key. The IRQ field will display a rising edge symbol.
[
3.
ON S
]
Press the SELECT key again to rotate through the list of optional values.
[DISABLED]
[ ON S ]
[ ON L ]
To specify either CALL or IF IRQ mode:
1.
When the IRQ feature has been turned on, a new field appears to the right of the IRQ field.
Move the screen cursor to this new field. The default value for this field is "IF IRQ" ENABLED".
IRQ
2.
[
ON S
]
["IF IRQ" ENABLED]
Press the SELECT key until the desired mode appears in the field.
[
ON S
]
["IF IRQ" ENABLED]
[
CALL
] [
CALL mode requires you to enter the label of the interrupt service routine in the new field to the right
of CALL.
To enter the label value for CALL mode:
1.
Move the screen cursor to the new field that appears to the right of CALL.
2.
Use the data entry keys to enter the LABEL name. You must enter this same LABEL name in
the 91 S 16 Program: Run sub-menu on the first line of the interrupt service routine. For
example, you could call the interrupt service routine INTR.
IRQ
[
ON S
]
CALL
]
[INTR]
Interrupt Qualifier Field
When the IRQ field has been enabled, a new QUALIFIER field appears on the screen immediately
below the IRQ field. This QUALIFIER field can be used to qualify whether or not the 91S16
responds to the interrupt request line.
The QUALIFIER signal is supplied via the P6460 External Control Probe. The interrupt qualifier
signal must be connected to an external source for this feature to be available. You are not required
to use the qualifier line in order to use the IRQ line. The QUALIFIER field defaults to DON'T CARE.
You can set the qualifier signal to be asserted for either high or low logic states. The QUALIFIER
signal must have a 15 ns setup time relative to the selected edge of the IRQ signal. Hold time is
o ns.
3·32
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
To set the QUALIFIER field's active state:
1.
Move the screen cursor to the QUALIFIER field.
[X]
QUALIFIER
2.
Use the data entry keys to enter either a 1 (positive-true) or a 0 (negative-true) value into the
field.
[1 ]
4 EXT JUMP Field
The EXT JUMP (External Jump) signal is tested by the IF EXT JUMP instruction which can be programmed in the 91S16 Program: Run sub-menu. The EXT JUMP field is used to select either
positive-true (IF 1) or negative-true (IF 0) logic states for the external jump signal.
This signal is supplied via the optional P6460 External Control Probe. The EXT JUMP line must be
connected to an external source. For the EXT JUMP signal to be asserted, it must have a 15 ns setup time relative to the selected edge of the pattern generator clock. Hold time is 0 ns.
NOTE
The EXT JUMP field can not be disabled if you have programmed an IF EXT
JUMP instruction in the 91516 Program: Run sub-menu. To disable this field,
you must first remove al/ IF EXT JUMP instructions.
To set the EXT JUMP active state:
1.
Move the screen cursor to the EXT JUMP field.
EXT JUMP
[DISABLED]
2. Press the SELECT key until the desired value appears in the field:
IF 0 ]
IF 1 ]
5 PAUSE Field
The PAUSE signal is used to freeze the output of the pattern generator in its present state. While
the pause signal is active, all pattern generator data, clock and strobe lines maintain their current
levels. The PAUSE field is used to specify whether a pause condition is asserted as either a
positive-true or a negative-true input signal. In default, the PAUSE field is disabled.
The pause signal is supplied via the optional P6460 External Control Probe. This signal line must be
connected to an external source. To be asserted, the pause signal must have a 15 ns setup time relative to the selected edge of the pattern generator clock. Hold time is 0 ns.
10 set the PAUSE field to be either positive-true or negative-true:
1.
Move the screen cursor to the PAUSE field.
PAUSE
2.
[DISABLED]
Press the SELECT key until the desired condition appears in the field:
[
[
ON 0 ]
ON 1 ]
3-33
Operating Instructions
CAS 9100 Series 91516-91532 Service
6 INHIBIT (91S16 & 91S32) Field
The inhibit signal is used by both the 91 S16 and 91 S32 to selectively tri-state the outputs of the
P6464 Pattern Generator probes. When the inhibit signal is asserted, any data line not masked by
the INHIBIT MASK in the Program: Run sub-menu will be tri-stated.
The inhibit signal can be determined by logically combining the external inhibit line and the internal
inhibit bit programmed in the Run sub-menu. You can choose to assert the inhibit signal as a simple
reaction to either the internal inhibit bit, the external inhibit signal, or a combination of the two either
ANDed or ORed together.
NOTE
The pattern generator will continue to execute its program even though an
inhibit signal has been asserted. Some data may be output by the P6464
probes while an inhibit is asserted if those bits have been protected by the INHIBIT MASK in the Program: Run sub-menu.
The INHIBIT field is used to specify whether the internal and external inhibit signals are enabled on
a positive-true (1) or negative-true (0) condition. Additional fields will appear when the INHIBIT field
is enabled to allow you to combine the two inhibits using logical operators. In default, the INHIBIT
field is disabled.
To set the asserted state for the internal and external inhibit signals:
1.
Move the screen cursor to the INHIBIT field.
INHIBIT
2.
[DISABLED]
Press the SELECT key until the desired condition appears in the field:
[EXTERNAL
[EXTERNAL
[INTERNAL
[INTERNAL
0]
[ONLY]
1] [ONLY]
0]
1 ]
[ONLY]
(ONLY]
To select a logical relationship between the internal and external inhibits:
1.
Move the screen cursor to the new field immediately to the right of the first condition field.
2.
Press the SELECT key until the desired logical operator appears in the field.
INHIBIT
3.
{EXTERNAL 0]
[ONLY]
[ AND]
[ OR]
]
]
A new field appears to the right of the logical operator field. This field allows you to set the asserted state for the other inhibit signal. Move the screen cursor to this new field and press select until the desired value you want appears in the field. For example:
[ INTERNAL 0
1[OR]
[EXTERNAL 0]
[EXTERNAL 1]
3-34
Operating Instructions
CAS 9100 Series 91516-91532 Service
7 EXTERNAL START Field
The external start signal works like an external trigger. If the EXTERNAL START field has been set
to ON and the START SYSTEM or START PAT GEN key has been pressed, the pattern generator
will begin program execution when the external start signal is received.
The external start signal is supplied via the External Start Input phono connector located on the
back of the 91 S16 module. This is the bottom phono connector on the back of the circuit board.
This connector must be connected to an external TTL-level signal source. To be asserted, the
external start signal must have a minimum 15 ns pulse width.
The EXTERNAL START field is used to enable the external start feature on either the rising or failing edge of the input signal. In default, the EXTERNAL START field is disabled.
To select either the rising or falling edge to enable the external start signal:
1.
Move the screen cursor to the EXTERNAL START field.
EXTERNAL START
2.
[DISABLED]
Press the SELECT key until the desired value appears in the field.
ONS]
ONL]
3-35
Operating Instructions
CAS 9100 Series 91S16·91S32 Service
91S32 PROBE SUB-MENU FIELDS AND VALUES
NOTE
The 91 S32 Setup: Probe sub-menu will appear when 91 S32 Modules are the
only pattern generator cards installed. This menu will not appear if a 91 S16 is
installed.
The following paragraphs explain how you can use the Setup: Probe sub-menu to set up the P6452
External Clock (Data Acquisition) Probe when 91 S32 modules are used without a 91 S16 controller.
(The P6452 probe connects to the DAS Trigger/Time Base module.) Each menu field is described
and its optional values are explained.
Figure 3-11 illustrates the Probe sub-menu and its fields. The fields, which appear in reverse video
on the screen, are bracketed [ ] throughout the text. The four directional cursor keys and the NEXT
key can be used to move the blinking screen cursor from one field to another.
Refer to the numbered callouts in Figure 3-11 when reading the following paragraphs. These
numbers serve as visual references and do not imply sequence of use.
1
2
3
4
5
5397·18
Figure 3·11. 91S32 Setup: Probe sub-menu.
3-36
Operating Instructions
CAS 9100 Series 91516-91532 Service
1 PATTERN GENERATOR SETUP Field
Use this field (directly to the right of the menu title) to select either the Probe or the Timing submenu display. Refer to the description of sub-menu selections in the Introduction to 91516 and
91532 Sub-Menus section earlier in this addendum. The Probe sub-menu is the default display.
2 P6452 INPUT THRESHOLD Field
Use the P6452 INPUT THRESHOLD field to set the threshold level for the P6452 External Clock
Probe. This probe supplies the pattern generator's external clock, pause, external inhibit, and
external start signals.
NOTE
The P6452 External Clock Probe also supplies the external clock signal to
the 91A32 Data Acquisition Modules. Therefore, any changes made to the
probe's threshold in this menu will also affect the 91A32 external clock
threshold. (Refer to the Trigger Specification Menu section of this manual.)
The P6452 External Clock Probe has a threshold-range switch. If this switch is set to NORM, the
probe operates with a TTL/VAR threshold. If the switch is set to AUX, the probe operates with a
MOS threshold. Once the probe switch has been set, the threshold field can be used to select the
lIarying voltage lellels for these thresholds.
If the probe is set to NORM, the threshold field defaults to TTL + 1.40 V. This threshold can be
changed to VAR (variable).
To change the P6452 INPUT THRESHOLD level field:
1.
Move the screen cursor to the threshold field.
[TTL] +1.4 V
2.
Press the SELECT key until the desired threshold level appears in the field.
The DAS displays optional threshold values in this order:
[TTL] + 1.40 V
[VAR] [-1.30 Vj
When VAR threshold is selected, a new field appears for setting the variable voltage level. The settings for this field range between +5.00 V and -2.50 V in 0.5 V increments. The voltage level may
be changed by using the INCR and DECR keys.
If the P6452's threshold range switch has been set to AUX, the threshold field will show the MOS
lIoltage range. This field may be set to a voltage level ranging between +20.00 V and -10.00 V in
0.20 V increments. Use the INCR and DECR keys to change the lIoltage level.
3-37
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
3 PAUSE Field
The pause signal is supplied via the P6452 External Clock Probe. This signal line must be
connected to an external source. To be asserted, the pause signal must have a 19 ns set-up time
and a 0 ns hold time (19 ns pulse width) relative to the selected edge of the clock.
The pause signal keeps the pattern generator outputs fixed at their last voltage states. While the
pause line is enabled, aU the pattern generator data and clock signals are held at their current levels.
The PAUSE field is used to specify whether a pause is enabled on a positive-true (1) or negativetrue (0) condition. In default, the pause feature is disabled.
To set the PAUSE signal to be active-high (1) or active-low (0):
1. Move the screen cursor to the PAUSE field.
PAUSE [DISABLED]
2.
Press the SELECT key until the desired condition appears in this field.
[DISABLED]
[ ON 0 ]
[ ON 1 ]
4 INHIBIT Field
The inhibit signal is generated by a logical operation of the internal and external inhibit signals. The
internal inhibit signal can be programmed in the 91 S32 Program Run sub-menu. The external inhibit
signal line must be connected to an external source. Either inhibit signal can cause the pattern generator probes to be tri-stated.
NOTE
The pattern generator will continue to execute its program even though an
inhibit signal has been asserted. Some data may be output by the P6464
probes while an inhibit is asserted if those bits have been protected by the INHIBIT MASK in the Program: Run sub-menu.
The INHIBIT field is used to specify whether the inhibit signals (internal and external) are enabled on
a positive-true (1) or negative-true (0) transition. This field also allows you to select the logical
operator combining the two inhibit signals. In default, the INHIBIT signal is disabled.
To set the INHIBIT field condition:
1.
Move the screen cursor to the INHIBIT field.
INHIBIT [ DISABLED]
2.
Press the SELECT key until the desired condition appears in the field.
[
[
[
[
EXTERNAL
EXTERNAL
INTERNAL
INTERNAL
0 1 [ONLYj
1 1 [ONLY]
0 ] [ONLY}
1 j [ONLYj
3-38
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
To select the logical operator:
1.
Move the screen cursor to the field following the first inhibit selection.
[ EXTERNAL 0 ] [ONLY]
[AND] [
[ OR ] [
2.
Press the SELECT key until the desired logical operator appears in the field. For example,
select OR:
[ INTERNAL 0 ] [OR] [EXTERNAL 0]
3. A new field appears to the right of the logical operator field. This field allows you to set the asserted state for the other inhibit signal. Move the screen cursor to this new field and press select until the desired value you want appears in the field. For example:
[ INTERNAL 0 ] [OR] [EXTERNAL 0]
[EXTERNAL 1]
5 EXTERNAL START Field
The external start signal is supplied by the P6452 External Clock Probe. This external start line
must be connected to an external source. To be asserted, the external start signal must have a
19 ns minimum pulse width.
The external start signal works line an external trigger. If the EXTERNAL START field is set to enabled and the DAS START SYSTEM or START PAT GEN key has been pressed, the pattern
generator will begin pattern execution when the external start signal is received.
The EXTERNAL START field is used to enable the external start on either the rising or falling edge
of the input signal. In default, the EXTERNAL START feature is disabled.
To select either the rising of falling edge to enable the external start feature:
1.
Move the screen cursor to the EXTERNAL START field.
EXTERNAL START: [DISABLED]
2.
Press the SELECT key until the desired value appears in the field.
[ ON S ]
[ ON 1. ]
3-39
Operating Instructions
CAS 9100 Series 91516-91532 Service
91S16 AND 91S32 TIMING SUB-MENU FIELDS AND VALUES
The following paragraphs explain how to use the Timing sub-menu to set up and adjust the 91 S16
and 91 S32 pattern generator pod and data channel timing relationships relative to the pattern
generator master clock. Each menu field is described and all optional values are discussed.
Figure 3-12 illustrates the Timing sub-menu and its fields. The fields, which appear in reverse video
on the screen, are bracketed [ ] throughout the text. The four directional cursor keys and the
NEXT key can be used to move the blinking screen cursor from one field to another.
Refer to the numbered callouts in Figure 3-12 when reading the following paragraphs. These
numbers serve as visual references and do not imply sequence of use.
1
2
3
6
4
5
5397-19
Figure 3-12. 91516 and 91532 Setup: Timing sub-menu.
1 PATTERN GENERATOR SETUP Field
The field directly to the right of the menu title is used to select either the Probe or the Timing submenu display. Refer to the Introduction to 91S16 and 91S32 Sub-Menus section earlier in this
addendum. In default, the Probe sub-menu will be displayed.
To change the sub-menu to the TIMING sub-menu:
1.
Move the screen cursor to the field directly to the right of the menu title.
PATTERN GENERATOR SETUP: [PROBE]
2.
Press the SELECT key until the Timing sub-menu appears in the field:
[TIMING ].
3-40
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
2 CLOCK Field
Use the CLOCK field to select the master input clock for the pattern generator. This clock is fed into
the pattern generator (usually from the DAS Trigger/Time Base board) and is used to control the
rate at which the pattern generator outputs clock and data signals to the circuit under test. The
master clock can be supplied by an external clock source. In this case, the 91 S16 External Clock
signal is supplied via an optional P6460 External Control Probe. The External Clock signal, when
only 91 S32s are installed. is supplied via a P6452 External Clock Probe connected to the DAS Trigger/Time Base Module.
The CLOCK field optional settings depend on whether you are using just a 91 S16. just 91 S32s. or a
combination of both. The optional values are as follows:
91S16 only
DAS internal clock, selections ranging from 5 ms through 20 ns
An external clock source: 50 MHz maximum (20 ns)
91S16 with 91S32s
DAS internal clock. selections ranging from 5 ms through 20 ns
at 50 MHz. all pod clock delays must be set to -5 ns
An external clock source: 50 MHz. (20 ns)
•
91 S32s only
DAS internal clock. selections ranging from 5 ms through 20 ns.
at 50 MHz. all pod clock delays must be set to 0 ns
An external clock source can supply clocking signals between 5 ms and 40 ns.
NOTE
The DAS provides two internal clocks. These clocks are shared by the 91 A32
and 91AOB data acquisition modules and the 91516/32 pattern generator
modules. Since it is possible to specify a different clock for each of these
modules while only two are available, you must make sure that no more than
two different clocks have been specified. Refer to the Start and Stop section
of the DAS 9100 Series Operator's Manual for details.
The default CLOCK setting is the DAS internal clock, with an interval of 1 /-lS. Use the INCR and
DECR keys to increase or decrease the clock interval as needed.
To increase or decrease the internal clock rate:
1.
Move the screen cursor to the CLOCK field.
CLOCK [1 /-lS ]
2.
Press the INCR key to increase the value or the DECR key to decrease the value.
The DAS will display increasing or decreasing clock values in a 1-2-5 sequence.
3-41
Operating Instructions
CAS 9100 Series 91516-91532 Service
An external clock source can also be selected using this field. You can also specify either the rising
or falling edge of the external clock signal. The external clock for the 91 S 16 is supplied via an optional P6460 External Control Probe connected to Pod C on the back of the 91 S16module. The external clock for 91 S32s used without a 91 S 16 is supplied via the PG452 External Clock Probe
attached to the DAS Trigger/Time 8ase Module.
When an external clock source is selected for the 91 S16, the P6460 INPUT THRESHOLD level is
displayed in the field following the CLOCK field for reference purposes.
To select an external clock source:
1.
Move the screen cursor to the CLOCK field.
CLOCK [1
2.
j.l.S ]
Press the SELECT key until the desired clock value appears in the field.
The DAS will display the available clock values in this order:
[1 j.l.S ]
[EXTERNAL I]
[EXTERNAL 1.]
3 REFERENCE Field
The REFERENCE field is used to select any data channel, strobe, or pod clock line you choose to
use as a timing reference when programming the edge position of a particular pod's data and
strobe channels.
The REFERENCE field is divided into two parts: POD, which specifies the pod 1.0. for your
reference channel; and the field following POD, which specifies a data channel, strobe. or pod clock
line. The delay value of the reference signal relative to the pattern generator master clock is
displayed in the DELAY field for your information; the value cannot be changed in this field. The delay value is also graphically represented as a positive-true signal for ease of comparison.
The default channel for the REFERENCE field is CH 0 of pod A anytime a 91 S 1G is installed. When
only 91 S32s are installed, the REFERENCE field default channel will be Channel 0 of pod A from
the 91 S32 installed in the highest-numbered DAS slot; for instance: CH 0, POD GA.
To specify a different reference channel:
1.
Move the screen cursor to the POD field.
POD
REFERENCE [GA] [CH 0]
2.
Use the data entry keys to enter any available pod 1.0. For example, 58.
[58J [CH 0]
To select the data channel, strobe, or pod clock:
1.
Move the screen cursor to the field following the POD field.
POD
REFERENCE [6A] [ CH 0]
3-42
Operating Instructions
CA5 9100 Series 91516-91532 5ervice
2.
Press the SELECT key until the desired reference channel appears in the field.
The DAS displays the data channels. strobe. and clock lines in this order:
[ CH 0 ]
[ CH 1 ]
[ CH 2 ]
[ CH 3 ]
[ CH 4 ]
[ CH 5 ]
[ CH 6 ]
[ CH 7 ]
[STROBE]
[POD CLOCK]
4 POD Field
-
The POD field is used to specify the name of the pod you want displayed. Any available pod 1.0. can
be entered. The POD field defaults to either the 91516 Pod A when a 91 S16 is installed, or Pod A
for the 91 S32 in the highest-numbered DAS slot when only 91 S32s are installed.
To select a pod for timing adjustment:
1.
Move the screen cursor to the POD field.
POD
[6A]
2.
Use the data entry keys to enter any available pod 1.0. For example, enter 5B:
[58]
5 POD CLOCK Field
The POD CLOCK field is used to adjust the timing of all the signals associated with this pod at one
time. The adjustment is made in relation to the pattern generator's master clock. The master clock
determines the start of each cycle.
Use the INCR or DECR keys to set the POD CLOCK delay value. The POD CLOCK delay value can
be set :t 5 ns relative to the master clock. Each pod may have a different POD CLOCK delay value.
In default. all the pod clocks have a delay value of 0 ns. The POD CLOCK delay values may also be
changed in the Configuration sub-menu.
Remember that 91 S32s operating at 50 MHz. with a 91 S16 must have their pod clock delays set to
- 5 ns. 91 S32s operating at 50 MHz. without a 91 516 must have thier pod clock delays set to 0 ns.
To increase or decrease the POD CLOCK delay:
1.
Move the screen cursor to the POD CLOCK field:
POD CLOCK
[ 0 nS ]
2.
Use the INCR key to increase the delay value, or the DECR key to decrease it. The adjustment
can be made in 5 ns intervals, displayed by the DAS in the following order:
[-5nS]
[
OnS 1
[+5nS]
3-43
Operating Instructions
DAS 9100 Series 91S16·91S32 Service
6 DELAY Field
The DELAY field is used to set the delay value for each of the data channels and the strobe lines relative to the pod clock. Each data channel and strobe line may have a different delay value. Use the
INCR or DECR keys to adjust the delay value in 1 ns increments within a - 5 ns to + 5 ns range relative to the pod clock.
The DAS will display the total delay relative to the pattern generator's master clock for each
channel (including the pod clock delay) in the DELAY field. The delay value for each data channel
and the strobe line will be graphically represented as a rising edge in the timing diagram. In default,
all the delay values are set to 0 ns.
NOTE
If you have used the Timing menu to adjust for pulse misalignment at the
P6464 probe tips, the delay values and graphic representation of timing
relationships shown in this menu will be misleading. You must remember to
account for any data skew adjustments made via this menu. Alternatively,
there is a deskew procedure using internal delay lines that will not affect the
timing relationships shown in this menu; that procedure can be found in the
DAS 9100 Series 91 S 16/32 Service Addendum (pIn 070.5397-00).
To increase or decrease the data channel and strobe delay:
1.
Move the screen cursor to the DELAY field.
CH 0 [ OnS]
CH 1 [ OnS}
CH 2 [ OnS}
CH 3 [ OnS]
CH 4 [ OnS]
CH 5 [ OnS]
CH 6 [ OnS]
CH 7 [ OnS]
STROBE [ OnS]
2.
Use the INCR key to increase the delay value, or the DECR key to decrease it.
The delay value can be adjusted in 1 ns increments from - 5 ns to
clock.
3-44
+ 5 ns relative to the pod
Operating Instructions
CAS 9100 Series 91516-91532 Service
91S16 PROGRAM: RUN MODE SUB-MENU
NOTE
The 91S16 Program Run Mode sub-menu appears only when the 91S16
Module is installed.
The following paragraphs show how to use the 91516 Program Run Mode sub-menu to enter
instructions and patterns for the 91516 Pattern Generator Module. They discuss each menu field
and explain all optional values.
Figure 3-13 illustrates the 91516 Pattern Generator Run Mode sub-menu and its fields. The fields,
which appear in reverse video on the screen, are bracketed [] throughout the text. The four
directional cursor keys and the NEXT key can be used to move the blinking screen cursor from one
field to another.
Refer to the numbered callouts in Figure 3-13 when reading the following paragraphs. These
numbers serve as visual references and do not imply sequence of use.
2
3
9
1
4
10
11
6
5
7
8
12
5397-20
Figure 3-13. 91516 Program: Run sub-menu.
3-45
·
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
NOTE
In the following discussion, the 91 S 16 Module is assumed to reside in slot 4.
1 PATTERN GENERATOR PROGRAM Field
Use this field (directly to the right of the menu title) to select either the 91 S16 or the 91 S32 submenu display. Refer to the Introduction to 91 S 16 and 91 S32 Sub-Menus section of this addendum.
In default, the 91 S16 Program: Run sub-menu is displayed whenever a 91 S16 Module is installed in
the DAS.
2 MODE Field
Use the MODE field to select the pattern generator's operating mode. The pattern generator
normally outputs data in real-time, synchronously with the clock signal. This mode of operation is
called Run mode, hence the name of this menu. For debugging purposes ,the pattern generator can
also output data at much slower rates, or even one step at a time. These modes of operation are
called Trace and Step, and are described under the Trace and Step Mode Sub-Menus sections of
this addendum. Descriptions of Trace and Step sub-menus are listed separately for the 91 S 16 and
the 91 S32.
Press the SELECT key while the screen cursor is in the MODE field to change between Run, Trace,
and Step modes. The MODE field defaults to Run mode on power-up.
3 START SEa Field
Use the START SEQ field to set the first sequence number the pattern generator will execute when
the START PAT GEN key or the START SYSTEM key is pressed. The START SEQ field may be
set to any number between 0 and 1023 as long as no interrupt service routine is programmed. If an
interrupt service routine has been programmed, the START SEQ field can be set to any number between 0 and 1022.
To set the START SEa field:
1.
Move the screen cursor to the START SEQ field.
START SEQ: [ 0]
2.
Use the data entry keys to enter the number of the sequence line where you want program execution to begin. For example, 500. The value you enter will appear in the field.
START SEQ: [ 500]
4 INHIBIT MASK Field
Use the INHIBIT MASK field to specify whether or not the data output channels respond to the inhibit (tri-state) signal. If the inhibit mask for a given data channel is set to 0 (unmasked), the data
channel is tri-stated whenever the inhibit signal is asserted. If the inhibit mask is set to 1 (masked),
then the inhibit signal is masked out and that data channel is not tri-stated, even though the inhibit
signal has been asserted. The inhibit mask can be set for each individual data channel by specifying
a value in the INHIBIT MASK field (default radix is hexadecimal). The default value for this field is 0,
unmasked for a" data channels.
3-46
Operating Instructions
CA5 9100 5eries 91516-91532 Service
To set the INHIBIT MASK field:
1.
Move the screen cursor to the INHIBIT MASK field.
INHIBIT
MASK
2.
: [00 00]
Use the data entry keys to specify the desired inhibit mask. The value you enter will appear in
the field. The display radix of this field matches the radix you have selected for the data fields.
This example shows hexadecimal values.
: [FO AO]
5 SEa (Sequence) Field
The SEQ field consists of a column of numbers on the left side of the display. Each number in this
column corresponds to one program line. The program lines are displayed sequentially starting with
SEQ O. There is a total of 1024 sequence lines labeled 0-1023. Only a portion of these sequence
lines are displayed at any given time.
Several methods are available to enable you to display different sequence lines. The first method is
to use the scroll keys. These keys can be used at any time. and when the cursor is in any field.
To scroll through the sequence lines:
Press the up (T) or down (1) scroll key. Additional sequence lines will scroll up from the bottom or
down from the top of the display.
The second method used to view different sequence lines is to enter the desired sequence number
directly into the SEQ field. This method allows you to jump forward or backward and display
specific blocks of sequence lines.
To move forward and display larger-numbered sequence lines:
1.
Move the screen cursor to the sequence number you wish to change. For example. move the
cursor to SEQ 11:
SEQ
11 ]
3-47
Operating Instructions
DAS 9100 Series 91S16·91S32 Service
2.
Use the data entry keys to enter the first sequence number you wish to have displayed. For example. SEa 200. The CAS will display [ 200] in place of [ 111. and then update the rest of the sequence lines following that position.
SEa
o
1
2
3
4
5
6
7
8
9
10
[ 200]
201
202
203
204
SEa 11 is changed to SEa 200,
and the rest of the sequence
numbers are automatically updated
from that position through the
bottom line of the display.
205
NOTE
When using the above procedures. observe the following two rules. First. if
the cursor is positioned below the top sequence number on the display, you
cannot enter a number smaller than the number directly above the cursor
location. Second, you cannot enter a number greater than 1023 (1022 if IRQ
CALL is used).
To move backward to a smaller-numbered block of sequence lines:
1.
Move the screen cursor to the SEa field of the line where you want the smaller sequence number to be displayed. For example. SEa 200.
SEa
[ 200]
2.
Press the DON'T CARE key.
The DAS will enter a 0 at this sequence number location.
NOTE
The number you enter must be larger than the number in the SEQ field
immediately above the cursor location. Use the top field in the display if you
want to view SEQ lines smaller than any currently displayed.
3-48
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
3.
Use the data entry keys to enter the sequence number you wish to display. For example, SEQ
15. The DAS will display 15 at that sequence number location, and then update the remaining
sequnce numbers on the screen from that position.
SEQ
o
1
2
3
4
5
6
7
8
9
10
[15]
16
17
18
19
20
SEQ 200 is changed to SEQ 15
and the display is updated
from this position to the
bottom of the screen.
6 LABEL Field
Use the LABEL field for labeling specific program lines. These labels serve as destinations for three
types of pattern generator instructions: JUMP, IF JUMP, and INTERRUPT CALL. (IF
JUMP instructions include IF R=O, IF KEY, IF IRQ, etc.) All three of these instruction
types transfer program flow to a line containing a specific label; they do not specify a destination
according to a sequence line number.
You can assign a total of 15 labels in a 91 S16 program. Each label may be up to four characters
wide, and may include letters, numbers, and spaces.
To assign a label for a specific program line:
1.
Move the screen cursor to the LABEL field associated with that program line.
SEQ
LABEL
0]
2.
4B 4A
[00 00]
Use the data entry keys to enter the label. For example, INIT. The DAS will display INIT in the
LABEL field for that particular sequence line.
SEQ
0]
LABEL
4B
4A
[IN IT]
[00 00]
3·49
Operating Instructions
OAS 9100 Series 91516-91532 Service
To remove a label:
1.
Move the screen cursor to the LABEL field you wish to remove.
SEQ
LABEL
4B
[INIT]
[00 00]
0]
2.
4A
Press the DON'T CARE (X) key. The label will be deleted from the field.
SEQ
LABEL
4B
4A
[00 00]
0]
7 #A and #8 Pattern Fields
The A and B fields that appear on the menu are used to specify the data pattern you wish to output
through the P6464 probes. The A field header designates the data pattern output through Pod A,
and the B field header designates Pod B. The number that appears before the A and the B
corresponds to the slot in the DAS where the 91 S 16 card resides.
Enter data patterns you wish to output line by line, one pod at a time. Use the DISPLAY editing
command if you wish to change the radix of the data you are entering. The default radix is
hexadecimal. Data patterns always default to O.
See the DISPLA Y Editing Command paragraphs later in this section for information about changing
the display radix of the data columns and inhibit mask.
To enter data on any program line:
1 . Move the screen cursor to the pattern field in the line you wish to program. Position the cursor
under the label for the pod you wish to program.
SEQ
LABEL
0]
2.
[00 00]
Use the data entry keys to program the pattern you desire. The DAS will display the data values you have entered in the field and then shift the cursor one space to the right. For example,
enter the value 30hex for Pod B.
SEQ
0]
3.
4B 4A
LABEL
4B 4A
[30 00]
Continue entering data values until both pods have been programmed. Then press the NEXT
key to move the cursor to the first data field of the next line.
3-50
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
8 S (Strobe) Field
Use the S (Strobe) field to select whether or not the strobe channels associated with each pod will
output signals when this particular program line is executed. Setting a 0 value for this field means
that neither the Pod A nor the Pod B strobe will be output. Setting a 1hex means that only the POd-A
strobe is output. while a 3hex means that both Pod A and Pod B strobes are output. You can program this field on a line-by-line basis, or you can use the Fill command to program whole blocks of
sequence lines in one operation. See the FILL Editing Command paragraphs later in this section for
details.
Strobe transitions are synchronous with the output clock. In default. the strobe field is set to 0 (no
strobes).
To assert a strobe:
1.
Move the screen cursor to the S field on the line you wish to program.
SEQ
LABEL
0]
2.
4B 4A
S
[00 00]
[0]
Use the data entry keys to enter the data value you desire. The 91 S 16 Strobe field contains 2
bits; the left bit correspodS to Pod B. and the right bit corresponds to Pod A. Default display radix is hexadecimal.
For example. to assert both the Pod A and Pod B strobes, enter a 3 hex.
SEQ
LABEL
0]
4B 4A
S
[00 00]
[3]
9 I (Inhibit) Field
Use the I (Inhibit) field to set the internal inhibit signal. It is used to temporarily tri-state the output of
either Pod A or Pod B. (Tri-state is TTL-level high impedance. and Eel-level logical low.) The
polarity of both the internal and external inhibit signals is programmable in the 91 S 16 Setup: Probe
sub-menu. The probes can also be programmed to react to a logical combination of the internal and
external inhibit signals. See the 91516 Setup: Probe Sub-Menu section in this manual.
For the following example. assume the following values have been set for the internal and external
inhibits: External Inhibit 1 OR Internal Inhibit 1. positive-true signals.
Setting a 0 in the I (Inhibit) field means that neither pod is tri-stated and both pods will continue to
output data, clock, and strobe lines. Setting a 1hex in this field will tri-state the outputs of Pod A.
Setting a 3hex will cause both Pod A and Pod B to be tri-stated.
Note that some data may still be output from a pod that has been tri-stated. because any value you
set in the INHIBIT MASK field will cause specific data lines to ignore the inhibit signal.
You must set values for the I (Inhibit) field for every sequence line. The default value is 0 (no pods
are tri-stated) and the default radix is hexadecimal. The internal inhibit signal becomes effective
synchronously with the output clock.
3-51
Operating Instructions
OAS 9100 Series 91S16-91S32 Service
To set an internal inhibit:
Move the screen cursor to the line you wish to program and position the cursor over the I field.
Use the data entry keys to enter the appropriate value. For example, to assert the internal inhibits for both Pod A and Pod B, (with the Setup: Probe sub-menu INHIBIT field set to
[INTERNAL 1]) enter a 3hex.
SEa
LABEL
0]
4B 4A
S
[00 00]
[0]
[3]
10 M (Interrupt Mask) Field
Use the M (Interrupt Mask) field to mask out external interrupt signals received from the P6460
probe. Entering a 1 in the M field of a particular sequence line causes the pattern generator to ignore external interrupt signals during execution of that program line. This feature allows you to protect certain programming routines from being interrupted.
The M field must be set to 1 in each line you wish to protect. In default, the M field is set to 0
(unmasked).
To mask an interrupt:
Move the screen cursor to the M field in the line you wish to program. Use the data entry keys
to enter a 1. The DAS will display a 1 in the M field.
SEa
LABEL
0]
11
sea FLOW,
4B 4A
S
[00 00]
[0]
M
[3]
[1]
CONTROL Fields
The SEa FLOW and CONTROL fields displayed on the DAS screen correspond to the identically
named keys grouped on the left-hand side of the DAS keyboard. SEa FLOW (sequence flow)
identifies a series of programming instructions that affect the order of sequence line execution (Le ..
branching, conditional branching, and halt). Selecting a SEa FLOW instruction may cause other
fields to appear. The CONTROL key allows you to select instructions that control 91 S32 pattern
generator cards, or issue triggering cues to some external device. CONTROL instructions are
optional and will appear in the same field as SEa FLOW instructions.
There are five basic types of SEa FLOW instructions and two CONTROL instructions. The default
for both types of instruction is no operation, which means the SEa FLOW, CONTROL field will be
blank and the pattern generator will output its data and then advance to the next sequence line.
SEa FLOW instructions include IF JUMP , JUMP , CALL RMT
(call remote), RETURN, and HALT.
CONTROL instructions are INCR PAGE (increment page) and TRIGGER. INCR PAGE issues a
command to 91 S32s operating in Follows 91 S 16 mode (INCR PAGE is only available when the
Memory Reload From Host field is set to OFF). TRIGGER causes a trigger signal to be output to
some external device (e.g., an oscilloscope) via the trigger-out phono connector on the back of the
91S16 module.
3·52
Operating Instructions
CAS 9100 Series 91516-91532 Service
NOTE
When entering SEQ FLOW and CONTROL instructions, position the screen
cursor on any reverse-video field associated with the sequence line you wish
to program.
To enter
sea FLOW and CONTROL instructions on
a sequence line:
1.
Move the screen cursor to any field on the line you wish to program.
2.
Press the SEQ FLOW or CONTROL key until the instruction you desire appears in the field. The
DAS displays the SEQ FLOW instructions in the following order:
[HALT
[JUMP
[IF RA=O JUMP
[IF RB=O JUMP
[IF R=O JUMP
[IF IRQ JUMP
[IF EXT JUMP
[IF KEY JUMP
[IF FULL JUMP
[IF END JUMP
[RETURN
[CALL RMT
]
][
][
][
][
][
][
][
][
][
]
]
The DAS displays the optional CONTROL instructions in this order:
[TRIGGER
]
[INCR PAGE]
To remove an instruction from a
sea FLOW,
CONTROL field:
Move the screen cursor to the SEQ FLOW, CONTROL field containing the instruction you wish
to remove. For example, to remove the IF RA=O instruction, place the screen cursor in the
SEQ FLOW, CONTROL field and press the DON'T CARE key. The DAS will remove the
instruction and leave the field blank.
To add a
sea FLOW,
CONTROL field to a sequence line:
1.
Move the screen cursor to the SEQ FLOW, CONTROL field of the sequence line you wish to
program.
2.
Press the ADD LINE key on the DAS keyboard to add a new SEQ FLOW, CONTROL field. This
will not add a new numbered sequence line; it simply creates space for you to program
additional SEQ FLOW or CONTROL instructions affecting the current sequence line. The new
SEQ FLOW, CONTROL field will appear in place of the field you already programmed and the
original field will be displayed one line below.
You may add up to two additional CONTROL fields for each sequence line (only one SEQ,
FLOW instruction per line allowed). For example, if you want to output the external trigger
signal at this point and switch any 91 S32s operating in Follows 91 S16 mode from one page of
memory to the other, you can program those instructions as follows:
3·53
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
SEa
LABEL
100
4B 4A
S
M
SEa FLOW. CONTROL
00 00
a a
a
[INCR PAGE
[ TRIGGER
]
[ IF RB=O JUMP] [label]
REG. OUT
The SEa FLOW. CONTROL instructions may be entered in any order. When the instruction sequence is redisplayed, it is displayed in a pre-defined order that reflects the order of execution.
All instructions programmed on a give sequence line will be executed.
To delete a
sea FLOW, CONTROL field that has been added:
1.
Move the cursor to the SEa FLOW. CONTROL field you wish to delete.
2.
Press the DELETE LINE key as many times as necessary. The DAS will delete a SEa FLOW,
CONTROL field each time the DELETE LINE key is pressed.
SEa
LABEL
100
4B 4A
S
M
SEa FLOW. CONTROL
00 00
a a
a
[ INCR PAGE
REG. OUT
] [/abe~ [
[ IF RB=O JUMP] [label]
NOTE
If you press the DELETE LINE key while the cursor is on a single line, al/ the
instructions on that line will be removed.
Each SEa FLOW and CONTROL instruction has individual performance characteristics. Several of
these instructions require labels as additional parameters. The following paragraphs briefly
describe each instruction and its capabilities.
,HALT. Normally. the pattern generator runs through all 1024 sequence lines before stopping
program output (assuming no loop or branch instructions are programmed). By using the HALT instruction. you may program the pattern generator to stop output on any sequence line.
When the pattern generator encounters a HALT instruction. it outputs the clock. data. and strobe
values aSSOciated with that sequence line and then halts. If the HALT instruction is encountered on
the first line the pattern generator executes. data and strobe signals are sent to the probe tips. but
not the clock signal; no clock transition occurs.
When entered on a program line. the HALT instruction appears like this:
SEa
100
LABEL
48 4A
S
00 00
a
a
M
SEa FLOW. CONTROL
a
[HALT
REG. OUT
JUMP. Use the JUMP instruction to implement program jumps. Normally. the pattern generator
outputs data in a straightforward line-by-line sequence. The JUMP instruction. however. alters this
sequential flow by specifying a jump from one program line to another. Sequential program
execution then resumes at that point.
3-54
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
When entered on a program line, the JUMP instruction appears like this:
SEa
LABEL
100
4B 4A
S
00 00
o
0
M
SEa FLOW, CONTROL
0
[JUMP
REG, OUT
] [label]
Use the empty field next to JUMP to enter the LABEL of the sequence line where you want program
execution to resume. For instance:
SEa
98
99
100
LABEL
4B 4A
S
M
[INIT]
[
]
[
]
00 00
00 00
00 00
000
000
000
SEa FLOW, CONTROL
[
[
[ JUMP
REG, OUT
[ INIT]
INIT could be the name of a block of patterns used to test the initialization software in the device under test. In this case, you would type INIT in the LABEL field of the line you wished to jump to. Information about entering a name in the LABEL field is located in the LABEL Field paragraphs found
later in this 91 S 16 Run Menu section. Enter the label by using the data entry keys on the the DAS
keyboard.
IF JUMP. Use the IF JUMP instruction to implement test and
branch instructions. Normally, the pattern generator outputs data in a straightforward line-by-line
sequence. The IF JUMP instruction, however, alters this sequential flow when the
conditions of the IF statement are satisfied. When the IF condition is satisfied, program flow is
transferred to the line containing the label specified after JUMP.
For example:
SEa
98
99
100
LABEL
4B 4A
S
[INIT]
[
]
00 00
00 00
00 00
000
000
000
[
]
M
SEa FLOW, CONTROL
[
[
[IF R=O JUMP
REG, OUT
[INIT]
When executed, this program line tests the pattern generator's register to see if it has the value O. If
R does equal 0, then program execution would resume at the sequence line that contained INIT in
the LABEL field.
The DAS displays the conditional tests for the IF JUMP instruction in this order:
RA=O
RB=O
R=O
IRa
EXT
KEY
FULL
END
3-55
Operating Instructions
CAS 9100 Series 91516-91532 Service
The following paragraphs briefly describe each conditional test.
IF RA=O JUMP, IF RB=O JUMP. The RA=O and the RB=O tests instruct the pattern generator
to examine the contents of either register RA or register RB. IF RA=O JUMP instructs the pattern
generator to examine the contents of register RA and branch if the value in RA equals O.
IFR=O JUMP. The IF R=O JUMP conditional test works the same as the IF RA=O and IF RB=O
tests described above, only this test is performed on the combined 16-bit register named "R"
(where R = RA + RB).
NOTE
The instruction for R = 0 is not displayed in the list of possible instructions if
you have configured the pattern generator register to be two 8-bit registers
named RA and RB. Similarly, the conditional tests RA = 0 and RB = 0 are not
included if you ha ve configured the pattern generator register to be one 16-bit
register called R. See the 91 S 16 Configuration Menu section for more
information about using the 91S16 Pattern Generator's internal register.
IF IRQ JUMP. The IF IRQ JUMP conditional test instructs the pattern generator to examine the
status of the P6460's IRQ (interrupt request) line. If the P6460 has detected a transition on this line
prior to this clock cycle, the condition is considered to be true. When a transient on the IRQ line
meets the following conditions, it can be recognized as an interrupt:
1.
IRQ polarity and level as specified in the 91S16 Probe sub-menu have been satisfied.
2.
The QUALIFIER line is driven to satisfy the level specified in the 91 S16 Probe sub-menu.
3.
The interrupt Mask bit (M) is set to 0 (unmasked) in the 91 S 16 Program sub-menu.
4.
The selected IRQ edge must occur 15 ns prior to the selected edge of the external clock
(minimum pule width is 15 ns).
NOTE
When the IRQ is disabled or the CALL is selected in the 91S16 Probe submenu, the IF IRQ JUMP instruction is not included in the list of conditional
tests.
NOTE
Since the pattern generator resets all the lines from the P6460 External
Control Probe at the start of execution, any external control signal test in the
first sequence line executed will fail to meet its setup and hold time specifications. If the first line executed contains an IF IRQ JUMP instruction, the
pattern generator will not jump even if an interrupt has been requested.
IF EXT JUMP. The IF EXT JUMP conditional test instructs the pattern generator to examine the
status of the EXT JUMP (external jump) line of the P6460 External Control Probe. If the the EXT
JUMP line meets the threshold level specified in the 91 S16 Probe sub-menu, then the condition is
considered to be true. Program execution will resume at the sequence line containing the label
specified.
NOTE
When EXT JUMP is disabled in the 91S16 Probe sub-menu. the IF EXT
JUMP conditional test is not displayed in the list of options.
3-56
Operating Instructions
CAS 9100 Series 91S16·91S32 Service
NOTE
Since the pattern generator resets all the lines from the P6460 External
Control Probe at the start of execution, the EXT JUMP signal will not meet its
setup and hold time specifications for the first sequence line executed. If the
first line executed contains an IF EXT JUMP instruction, the pattern genera·
tor will not jump even if the EXT JUMP line has been asserted.
IF KEY JUMP. The IF KEY JUMP conditional test instructs the pattern generator to determine
whether the SHIFT START PAT GEN key on the DAS keyboard has been pressed. If the key was
pressed before this sequence line was executed, the condition is considered to be true. This
conditional test allows communication between the user and the pattern generator while the
system is running. In this way, you can advance control of the pattern generator from one linked
looping routine to another by pushing the SHIFT START PAT GEN KEY.
IF FULL JUMP and IF END JUMP. The IF FULL and IF END conditional tests are used to support
the 91 S16's Pattern Download From Host feature. In order to use these tests, you must be using a
91S16 to control the output of one or more 91S32s. Refer to the 91S32 Configuration Sub·Menu
When Used With 91 S 16 section of this addendum for a description of the Pattern Download From
Host feature.
Large patterns downloaded from a host computer often require more memory than the 2048.line
maximum available with the 91 S32. The Pattern Download From Host feature enables you to divide
a larger pattern generator program into 1024.line blocks. output one block of program lines,
download another block of sequence lines, output the new page of vectors, and continue the
process until the entire program has be executed. The Pattern Download For Static Devices
version does not output any vectors while a new block of vectors is being downloaded from the
host.
The Pattern Download For Dynamic Devices (Keep·Alive) version does provide some 91S16
vectors to the system under test while the 91 S32s are being reloaded. This mode of operation al·
lows you to keep dynamic circuit elements active while the pattern generator is reloaded. Keep·
Alive is only available with the Option 06 GPIB interface. IF FULL JUMP and IF FULL END are used
to support the Keep-Alive subroutine. See the section of this addendum titled GPIB Programming
for detailed instructions about Keep-Alive programming.
IF FULL tests to see if the GPIB controller has sent key code 47 to the DAS. Key code 47 indicates
that the data transfer is complete. IF FULL then causes the 91 S32s to switch program execution to
the newly refilled memory page.
IF END tests to see if the GPIB controller has sent key code 46 to the DAS. Key code 46 indicates
that aU data transfers have been complete. IF END JUMP then transfers program
execution to some final sequence lines designated by the label.
NOTE
The IF FULL and IF END conditional tests are not displayed in the fist of field
options if the 91S32 Configuration sub-menu·MEMORY RELOAD FROM
HOST (FOR KEEP.ALlVE) field has not been set to ON.
RETURN. The RETURN instruction is used in conjunction with the IRQ enabled CALL
instruction programmed in the 91S16 Probe sub·menu. When the Probe sub·menu IRQ field has
been set to CALL, a label field appears. You can then enter a label name in this field that
corresponds to a set of sequence lines specifically designed to service the interrupt request. For example, call the label RSET.
3-57
Operating Instructions
OAS 9100 Series 91516-91532 Service
PATTERN GENERATOR SETUP:
[PROBE]
P6460 INPUT THRESHOLD
[TTL]
IRQ
+ 1.4V
[ ON .I ] : [
[1]
& QUALIFIER
EXT JUMP:
CALL
] [RSET]
[DISABLED]
PAUSE:
[DISABLED]
INHIBIT:
(91S16 & 91S32)
[DISABLED]
EXTERNAL START
[DISABLED]
When an interrupt request has been detected on the IRQ line from the P6460 External Control
Probe. program execution transfers to the sequence line containing the label given in the Probe
sub-menu. (It is possible to mask out the interrupt signal using the M field in the Program Run submenu.) In the example, suppose the pattern generator was executing sequence 100 at the time the
interrupt request was detected. After executing line 100, the pattern generator would execute the
sequence line containing RSET in the label field. Pattern execution will continue sequentially from
that line until a RETURN instruction is encountered in the SEQ FLOW, CONTROL field. Pattern execution will then resume at sequence line 101.
NOTE
The RETURN instruction must only be used in conjunction with the IRQ
CALL instruction. If a RETURN is executed before a IRQ CALL, the RETURN
instruction acts like a call to Itself, and the pattern generator will become
caught in an endless loop.
SEQ
LABEL
100
10
11
12
101
[RSET]
4B 4A
S
00 00
0
0
0
FF FF
AF 00
AA 1E
0
0
0
0
0
0
0
0
0
00 00
0
0
0
M
sea
FLOW, CONTROL
REG,OUT
RETURN
The RETURN instruction is programmed in the SEQ FLOW, CONTROL field in the last sequence
line designed to service the interrupt request. Program flow continues on the sequence line
following the one being executed when the interrupt request was detected.
3-58
Operating Instructions
DAS 9100 Series 91516-91532 Service
NOTE
The RETURN instruction will not be displayed in the instruction list if the
91S16 Probe sub-menu's IRQ field is set to DISABLED or IF IRQ JUMP.
CALL RMT The CALL RMT (call remote device) instruction is part of the Pattern Download for
Dynamic Devices (Keep-Alive) feature that allows the pattern generator to reload its memory from
an external device. The other instructions associated with the Keep-Alive feature are IF FULL
JUMP, and IF END JUMP.
CALL RMT is enabled when you set the MEMEORY RELOAD FROM HOST (FOR KEEP-ALIVE)
field to ON in the 91532 Configuration sub-menu.
NOTE
CALL RMT is only available when you are using DAS Option 06 GPIB. All restrictions that apply to Keep-Alive also apply to the CALL RMT instruction.
Refer to the GPIB Programming section of this addendum.
The CALL RMT instruction issues an 5RQ on the GPIB bus. This command is normally
programmed to signal a host computer or external memory device that one page of the 91 532's
pattern memory is ready to be reloaded. This signal can also be used in other situations, such as in
automated test equipment (ATE), when you want to signal any external device when the pattern
generator executes a certain program line.
NOTE
The CALL RMT instruction is not a subroutine. It is a control instruction
which asserts an SRQ on the GPIB bus. When the controller performs a
serial poll of the DAS, status byte 197 is returned to the controller. This
instruction does not save a return address on the stack.
NOTE
Another CALL RMT instruction is valid only after the IF FULL JUMP
instruction has been executed.
NOTE
If no 91S32 module is installed, or the MEMORY RELOAD FROM HOST
(FOR KEEP-ALIVE) field is set to OFF in the 91 S32 Configuration sub-menu,
the CALL RMT instruction is not included in the instruction selection list.
TRIGGER.
Use the TRIGGER instruction to generate an external device trigger signal. The
trigger signal appears at the trigger output phono connector located near the probe connectors on
the back of the 91516. Use the optional 79-inch phono-to-BNC cable to connect the trigger output
connector to an external device (such as an oscilloscope). This trigger signal is a positive-true, TILlevel, NRZ (non-return-to-zero) signal. It stays TIL-high for one cycle each time it is programmed.
NOTE
If the TRIGGER instruction is programmed for several consecutive sequence
lines, the pulse width of the TRIGGER signal will widen in proportion to the
number of TRIGGER instructions. For example, if you program the TRIGGER
instruction in line 100 and line 101, the TRIGGER output signal will stay high
for two clock cycles.
3·59
Operating Instructions
CAS 9100 Series 91S16·91S32 Service
INCR PAGE The INCA PAGE (increment page) instruction is used when 91 S32s are used in
Follows 91 S16 mode and the 91 S32 Configuration sub-menu Memory Aeload From Host field is
set to OFF. Because the 91 S32s have twice as much memory as the 91 S16. it is often convenient
to divide that memory into two 1024-line pages. These pages are called Page A and Page B. You
may want to repeat the program loaded into Page A until a certain event occurs. and then switch to
Page B. The INCR PAGE command switches 91 S32 execution from one page of memory to the
other.
12 REG, OUT Fields
The AEG. OUT column heading designates the fields used to control operation of the two 8-bit, or
one 16-bit. pattern generator registers. (Designating the pattern generator register as either two 8·
bit registers or one 16-bit register is accomplished in the 91 S16 Configuration sub-menu.) REG
stands for register, and OUT is a reminder that the instructions in this field control when the
contents of the register are output as pattern via the P6464 probes.
The AEG key on the DAS keyboard corresponds to the AEG instructions. AEG instructions include
LOAD A, INCA A (increment A). and DECR A (decrement A). If you configure the pattern generator
register to be two S-bit registers, you can select LOAD AA and LOAD RB, instead of LOAD R. If
you don't program any REG instruction, the register will simply maintain its previous value.
The OUT key on the DAS keyboard corresponds to the OUT field and instructions. OUT
instructions include OUT A (output the contents of register A as data), and OUT AEP. OUT AEP in·
structs the pattern generator to repeat whatever Pod A pattern it output on the previous sequence
line. This could be a data value or a register value.
Program any AEG or OUT instruction by pressing the corresponding instruction selection key. The
instruction selected will be displayed under the AEG. OUT field heading. Sometimes both AEG and
OUT instructions are programmed on the same line. If you want to program more than one AEG or
OUT instruction for a sequence line, you must press the ADD LINE key on the DAS keyboard. This
will cause another AEG, OUT field to appear. You can add up to two additional AEG, OUT fields for
each sequence line.
NOTE
When entering REG and OUT instructions, position the screen cursor on any
reverse-video field associated with the sequence line you wish to program.
NOTE
Before attempting to use the LOAD command, carefully read the paragraph
titled Load for instructions on loading the register(s) from the data field later in
this section.
To enter a REG or OUT instruction on a sequence line:
1. Move the screen cursor to any field on the line where the instruction is to be programmed.
2.
Press the AEG or OUT key until the desired instruction appears in the· field.
3-60
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
The DAS will display the REG instructions in this order:
[LOAD RA
[INCR RA
[DECR RA
[LOAD RB
[INCR RB
[DECR RB
OR
[LOAD R
[INCR R
[DECR R
If you have configured the 91 S 16 internal register to be two 8-bit registers. only RA and RB instructions will be displayed; if you have configured the register to be one 16-bit register. only R
instructions will be displayed.
The DAS will display the OUT instructions in this order:
[OUT RA
[OUT RB
OR
[OUT R
AND
[OUT REP
To return REG and OUT instructions to their default values:
1.
Move the screen cursor to the REG. OUT field you wish to default.
SEa
LABEL
100
2.
4B 4A
S
M
00 00
000
SEa FLOW. CONTROL
REG. OUT
[OUT RA]
Press the DON'T CARE key.
SEa
LABEL
100
4B 4A
S
M
00 00
000
SEa FLOW, CONTROL
REG, OUT
To add an additional REG or OUT field:
1.
Move the screen cursor to a field on the line where the additional REG or OUT instruction needs
to be added.
SEa
100
LABEL
M
4B 4A
S
00 00
000
SEa FLOW. CONTROL
REG, OUT
[INCR RA
3-61
1
Operating Instructions
DAS 9100 Series 91516-91532 Service
2.
Press the ADD LINE key on the DAS keyboard up to two times.
The DAS will create an additional reverse-video REG, OUT field each time you press the ADD
LINE key; note that this does not create additional sequence lines, just extensions to the
existing sequence line.
SEa
100
LABEL
4B 4A
S
00 00
a
M
a
SEa FLOW, CONTROL
a
REG, OUT
[
]
[INCR RA]
REG and OUT Instructions
Read this section carefully; REG and OUT instructions depend on the configuration of the 91S16
internal register; most operations affect the output of Pod A only. Do not assume that a REG or
OUT instruction also affects the data supplied to Pod B unless the following paragraphs specifically
state that Pod B is affected.
Each REG (register control) and OUT (output register contents as data) instruction has individual
performance characteristics. These characteristics are dependent on how you have configured the
91S16's internal register in the 91S16 Configuration sub-menu.
NOTE
You must select the configuration for the 91 S 16 internal register in the 91 S 16
Configuration sub-menu. You may select either two 8-bit registers named RB
and RA, or one 16-bit register named R. The default configuration is RB and
RA.
Keep in mind the following rules when using REG and OUT instructions:
1.
When the 91 S16's internal register is configured as two a-bit registers called RA and RB, the
initial value loaded into either register is loaded from the Pod A data field; the Pod B data field is
not used to load either register. (Two sequence lines are required to load both registers.)
The most significant bit for each data register corresponds to the most significant bit of the Pod
A data field.
When data is output from either RA or RB, it is delivered to the Pod A pattern generator probe;
the Pod B probe receives its pattern (as usual) from the Pod B data column in the Run submenu. When either RA or RB is output, the data value specified for Pod A is ignored.
2.
When the 91 S 16' s internal register is configured as a single 16-bit register called R, the initial
value is loaded from both the Pod B and the Pod A data fields.
When data is output from 16-bit register R, it is delivered to both Pod B and Pod A probes. The
most significant bit of the register is delivered to the most significant data channel of the pattern
generator probe attached to Pod B, while the least significant bit of the register is delivered to
the least significant channel of Pod A.
When register R is output, the data values for Pod B and Pod A are ignored for that sequence
line.
3.
If you have programmed a SEa FLOW or OUT instruction on the same line as a REG
instruction, the SEa FLOW or OUT instruction will be performed first. For example, if you
program IF R = 0 JUMP instruction on the same line as a LOAD R instruction, the pattern generator will test to see if R = before loading R with some new value. Both instructions
will be executed. but the conditional test will use the old value for R.
a
3·62
Operating Instructions
CAS 9100 Series 91S16·91S32 Service
LOAD Instructions
The LOAD register commands are used to load the register with some initial value. LOAD uses either RA, RB, or R as an operand. The register names displayed will depend on whether you have
selected two a-bit registers or one 16-bit register.
LOAD RA, LOAD RB. Initial values for either RA or RB are loaded from the Pod A data field in the
sequence line containing the LOAD instruction.
To load RA, move the screen cursor to the Pod A data field and use the data entry keys to specify
the value you want loaded into the register. Move the screen cursor to the REG. OUT field and
press SELECT until LOAD RA appears on the screen. LOAD RB works exactly the same way.
SEQ
LABEL
100
4B 4A
S
00 01
o
M
o
SEQ FLOW. CONTROL
REG. OUT
o
[LOAD RA
1
After executing sequence line 100, register RA will contain the value 00000001 bm.
LOAD R. The initial value of register R is loaded from the Pod B and Pod A data fields. The most
significant bit of register R is taken from the most significant bit of Pod B, and the least significant
bit of R is taken from the least significant bit of Pod A.
SEQ
LABEL
100
4B 4A
S
01 03
o
M
o
SEQ FLOW, CONTROL
o
REG, OUT
[LOAD R 1
After executing sequence line 100, register R contains the value 000000010000001 Obm.
INCR (Increment Register) Instructions
The INCR (Increment Register) instructions are used to increase the count of the specified register
by one. There are INCR RA. INCR RB, and INCR R versions of this command. The options
displayed depend on whether you have configured the internal register to be two a-bit registers
named RA and RB, or one 16-bit register named R.
INCR RA, INCR RB. These commands increment the values of their respective registers by 1 each
time the sequence line containing the instruction is executed. The range of the counters is between
and FF. The next INCR command following FF resets the register to 0; no carry signal is
generated.
o
INCR R. This command increments the value of register R each time the sequence line containing
the instruction is executed. The range for the counter is between 0 and FFFF. The next INCR command following FFFF resets the register to 0; no carry signal is generated.
Here is an example of an INCR R instruction programmed into a sequence line; data fields are not
affected by this command.
SEQ
100
LABEL
4B 4A
S
00 00.
0
M
o
3-63
o
SEQ FLOW, CONTROL
REG, OUT
[ INCR R 1
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
DeCR (Decrement Register) Instructions
The DECR (Decrement Register) instructions are used to decrease the value of the specified
register by one. There are DECR RA, DECR RB, and DECR R versions of this command. The options displayed depend on whether you have configured the internal register to be two S-bit
registers named RA and RB, or one 16-bit register named R.
DeCR RA, DeCR RB. These commands decrement the values of their respective registers by 1
each time the sequence line containing the instruction is executed. The range of the counters is between FF and O. The next DECR command following 0 sets the register to FF; no borrow signal is
generated.
DeeR R. This command decrements the value of register R each time the sequence line
containing the instruction is executed. The range for the counter is between FFFF and O. The next
DECR command following 0 sets the register to FFFF; no borrow signal is generated.
Here is an example of a DECR R instruction programmed into a sequence line; data fields are not
affected by this command.
SEa
LABEL
100
4B 4A
S
00 00
o
M
o
SEa FLOW, CONTROL
o
REG, OUT
[DeCR R 1
OUT (Output Register Contents) Instructions
The OUT (Output Register Contents) instruction allows you to output the contents of the 91 S16's
internal register as data in place of the value programmed in that sequence line's data field. There
are OUT RA, OUT RB, and OUT R versions of this instruction. The options displayed depend on
whether you have configured the internal register to be two S-bit registers named RA and RB, or
one 16-bit register named R. OUT instructions do not change the value in a register.
NOTE
OUT AA and OUT AB both provide data to the pattern generator probe
attached to Pod A; neither outputs data to Pod B. OUT A outputs data to
both Pod B and Pod A.
OUT RA, OUT RB. The value in the specified register is sent as data to the pattern generator
probe connected to Pod A. Both register RA and register RB send data to the same pattern
generator probe. You cannot have OUT RA and OUT RB instructions on the same sequence line.
OUT R. The value in register R is sent as data to the pattern generator probes connected to both
Pod B and Pod A. The most significant register bit is sent to the Pod B channel 7 data line and the
least significant register bit is sent to the Pod A channel 0 data line.
Here is an example of the OUT R instruction programmed into a sequence line. The data values
programmed into the 4B and 4A fields for this line will not be sent to the pattern generator probe
tips; these data values will be ignored by the pattern generator. (Note: the contents of data Pod B
would be output if the instruction were OUT RB or OUT RA.)
SEa
100
LABEL
4B 4A
S
M
00 00
o
o o
3-64
SEa FLOW, CONTROL
REG. OUT
[OUT R 1
Operating Instructions
OAS 9100 Series 91S16·91S32 Service
NOTE
STEP and TRACE modes allow you to see the data output as each sequence
line is executed and view the contents of the 91 S 16 's internal register for that
sequence line. Read the section of this addendum titled 91 S 16 Step and
Trace Mode Sub-Menus for instructions on using these operating modes.
OUT REP (Out Repeat) Instruction
The OUT REP (Out Repeat) instruction causes the pattern generator to ignore its current data
source for Pod A and repeat whatever vector it output for Pod A in the previous sequence line. It
does not matter if the previous sequence line's vector originated as data, a register value, or even
another OUT REP instruction.
NOTE
OUT REP only repeats the output of Pod A; it does not repeat the previous
vector supplied to Pod B. If the previous data vector was a 16-bit value from
register R, OUT REP will only repeat the 8 least significant bits (those
originally supplied to Pod A); Pod B data will be supplied by the Pod B data
field.
Here is an example of the OUT REP instruction programmed into a sequence line.
When sequence line 101 is executed, it will output AA via the probe attached to Pod A, and 00 via
the probe attached to Pod B.
SEa
LABEL
99
100
4B 4A
S
M
AA AA
00 00
0
0
o o
o o
SEa FLOW, CONTROL
REG, OUT
[OUT REP]
13 EDIT Fields
The 91 S 16 Module provides nine edit commands to manipulate labels, patterns, and instructions
on program lines. These commands are designed to simplify programming.
To select an edit command:
1.
Move the screen cursor to the edit field at the bottom of the screen:
2.
Press the SELECT key until the desired command appears in the field. You can also use the
INCR and DEeR keys to select from the edit commands.
The DAS displays the list of possible edit commands in this alphabetical sequence:
[CONVERSION]
[COpy
]
[DELETE
]
[DISPLAY ]
[FILL
]
[ INSERT 1
[MODIFY
1
[MOVE
1
[ SEARCH 1
3-65
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
Each edit command has a specialized function. The CONVERSION command has a sUb-menu
used to make and check a conversion table. Several commands have sub-fields you will use to
specify starting and ending sequence lines, or to select among additional sub-commands.
Some of the commands have fields that require you to enter setup and editing parameters.
3.
After entering the changes you wish to make for any of the edit operations, press the
EXECUTE key. Some of the fields, such as those pertaining to sequence numbers, will be
blanked after the edit operation has been completed. This is to prevent you from accidentally
pressing EXECUTE again and damaging your corrected program.
The following paragraphs briefly describe each of the edit commands.
CONVERSION. The CONVERSION command allows you to search for and replace all pattern
data values with corresponding different values in one operation. For instance, if you knew you
wanted to replace all FFs hex in your program with AAs, and replace all 1Es hex with OOs, you could
use the CONVERSION command to do that in one operation.
This feature is most commonly used when you are converting data from one coding system to another, such as from a normal binary counting method to that of the Gray code where only one bit
changes as numbers are incremented.
The CONVERSION command has two sub-commands: CONVERT, which deSignates which pod's
data is to be converted, and TABLE BUILD. The TABLE BUILD command displays a special menu
called the TABLE BUILD sub-menu that allows you to specify which bit patterns to change.
Instructions for using this menu are included in the following paragraphs.
CONVERT. This sub-command instructs the pattern generator to apply the conversion rules
outlined in the TABLE BUILD sub-menu to the data in a particular pod. The way in which the TABLE BUilD sub-menu performs conversions will become clear as you read this section. If you had a
91S16 in DAS slot 1 and you wanted to modify the data programmed for Pod B according to the
changes given in the TABLE BUilD sub-menu, you would type:
[CONVERSION] : [
CONVERT]
POD [1 B]
Press the EXECUTE key to initiate the conversion.
The TABLE BUilD sub-menu only operates on one pod of data at a time. Therefore, if you wanted
to convert a/l data patterns for a 91 S16 in DAS slot 1 from one code to another, you would have to
CONVERT POD 1A, and then CONVERT POD 1B.lt you are using 91S32s along with your 91S16,
you would have to run the conversion program four more times for each 91 S32 to convert all the
data from one code to another. However, you will often be using the different pods for different purposes, and you may only want to convert one pod's data and leave the rest of the data unchanged.
To specify which pod's data will be converted:
1.
Move the screen cursor to the POD field.
[CONVERSION] : [ CONVERT] POD [
2.
Use the data entry keys to enter a pod 1.0. For example, pod 4B. The DAS will display the pod
I.D. in the POD field.
[CONVERSION] : [ CONVERT] POD [4B]
3.
Press the EXECUTE key to start the conversion. The DAS will display· CONVERTED POD 48"
on the second line of the screen when the conversion has been completed. The DAS will also
blank the POD field to prevent accidental conversions later.
3·66
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
TABLE BUILD. Use the TABLE BUILD sub-menu to convert an existing data pattern into some
modified data pattern. The menu provides two columns of B-digit binary numbers from 00000000 to
11111111. Modifying the bit pattern in the CODE column and executing the CONVERT command
on some pod's data will cause all instances of the pattern in the right-hand DATA field to be
converted to the pattern in the CODE field.
For example, moving the screen cursor to 00000000 in the left-hand column. typing in 00000001.
and then executing CONVERT POD 1A. will cause all instances of 00000000 stored as data in
POD-1 A to be changed to 00000001.
It may be useful for you to think of the bit-patterns in the left-hand column as sequence numbers.
The bit-patterns in the left-hand DATA column represent all possible bit-patterns. Typing some
pattern in a left-hand field is a way of moving your editing window from one bit-pattern to another; it
will not change any data.
To invoke the TABLE BUILD sub-menu:
1.
Move the screen cursor to the field containing CONVERT.
[CONVERSION] : [
2.
CONVERT] POD [
]
Press the SELECT key until TABLE BUILD appears in the field. The TABLE BUILD sub-menu
will automatically appear on the screen.
Refer to Figure 3-14.
1
2
4
3
5
Figure 3-14. Table Build sUb-menu.
3-67
5397-21
Operating Instructions
DAS 9100 Series 91516-91532 Service
1
-+
Field
The ~ field indicates the direction for converting data. If the arrow is pointing to the right, data in the
right-hand column will replace the data pattern indicated in the left-hand column. If the arrow is
pointing to the left, the pattern in the left-hand column will replace the pattern in the right hand column.
When the arrow is pointing to the right, you can enter the same bit pattern in the right column for
any number of bit patterns in the left column. However, when the arrow is pointing to the left, each
pattern in the left column must convert to a unique pattern in the right column.
As long as you are mapping a unique pattern in the right column to a unique pattern in the left column, this feature allows you to change the data pattern, and then change back easily if you don't
like the results of your first conversion.
This field defaults with the arrow pointing to the right.
To change the direction of the conversion arrow:
1.
Move the screen cursor to the arrow field.
DATA [-+] CODE
2.
Press the SELECT key until the desired direction appears in the field.
DATA H CODE
2 WIDTH Fields
Use the WIDTH fields to select the bit width of the data and code columns. For both columns, you
can select bit widths ranging from 1 to 8 bits. The default field width is 4 bits for each column.
You will usually want to set both column widths to the same value. The bit width you select will determine the depth of the corresponding DATA and CODE fields. However, if you select a width of 4
bits for the DATA column and 5 bits for the CODE column, both selection fields will be 16 lines deep
(16 possible patterns from 4 bits); the field depth always truncates to match the shorter column. Selecting 8-bit field widths for both columns will generate a TABLE BUILD sub-menu with 256 lines of
bit patterns.
If you shorten the width CODE field after having entered some longer value into one of the fields,
the display will change to show the shorter pattern, but the DAS will retain the longer value in memory until the DAS is turned off.
To enter the DATA and CODe fields column widths:
1.
Move the screen cursor to the WIDTH field over the column you wish to change.
DATA
WIDTH
2.
CODE
[4] BITS
[4] BITS
Use the data entry keys to enter the desired column width. For example, 8.
DATA
WIDTH
CODE
[8] BITS
[4] BITS
Remember that no data conversion actually takes place until you EXECUTE the CONVERSION: CONVERT POD [##] command. Depending on how you configure your replacement
3-68
Operating Instructions
DAS 9100 Series 91516-91532 Service
data patterns in the TABLE BUILD menu, it is possible that the CONVERT command will
attempt to replace an 8-bit pattern with a smaller, say 4-bit, pattern. In this case, only the lowest 4 bits of the original pattern would be converted to the new pattern, and the data in the four
most significant bits would not be changed. For example, if the original pattern was
11111111 bm, and the replacement pattern from the TABLE BUILD menu was OOOObm, the
resulting data would be 1111 OOOObm.
3 DATA Column
The DATA column automatically appears whenever the TABLE BUILD sub-menu is selected. The
DATA column contains all possible bit patterns for data entered in the PROGRAM: Run sub-menu.
Bit patterns in the DATA column represent existing data, while bit patterns in the CODE column
represent planned changes to the data. (The only exception is when the direction field has the
arrow pointing to the left.)
The depth of the DATA column is dependent on the value entered in the WIDTH field. Since all possible bit patterns for a particular width are shown, most TABLE BUILD sub-menus are too long to
be displayed on one screen.
There are several ways of displaying different parts of the TABLE BUILD sub-menu. The first
method is to use the scroll keys on the DAS keyboard.
To scroll through the DATA column sequences:
Press the
T
or the ! key on the keyboard. The DAS will scroll the display up or down.
The second method used to display different DATA bit patterns is to enter the desired new pattern
into a field within the DATA column. Just as in moving through sequence lines in the Program Run
sub-menu, the DAS will display the DATA line you have entered and fill the rest of the page with
DATA lines incrementing from that point.
To move forward to a larger block of DATA lines:
1.
Move the screen cursor to the data field you wish to change. For example, line 1010.
DATA
00000101
00000110
00000111
00001000
00001001
[00001010]
00001011
00001100
00001101
3·69
Operating Instructions
CAS 9100 Series 91S16·91S32 Service
2.
Use the data entry keys to enter the first DATA line you wish to display. For example,
11001000.
DATA
00000101
00000110
00000111
00001000
00001001
[11001000]
11001001
11001010
11001011
DATA pattern 00001010 is
changed to 11001000 and
the remaining DATA patterns
increment from that line.
The DAS will display DATA line 11001000 in place of line 00001010, and then update the rest of the
DATA lines following that position.
NOTE
Entering a value in one of the DATA column fields is a method of displaying
different portions of this sub-menu; it will not change the data programmed
for a pod in the Run sub-menu.
To display a block of DATA patterns with smaller values:
1.
Move the screen cursor to the first DATA line displayed in the TABLE BUILD menu.
2.
Use the data entry keys to enter the bit pattern you want to display. The display will fill with data
lines starting with the pattern you have entered.
NOTE
Values in the DATA column are displayed in ascending order. If you wish to
display a value smaller than any currently displayed, you must enter the new
value in the topmost DATA column field.
4 CODe Column
Use the CODE column fields to enter the pattern you want to end up with after the conversion. Bit
patterns in the CODE field will replace the bit patterns in the DATA field immediately to their left.
More than one data pattern may be converted to the same CODE pattern. To do this, enter the
same CODE pattern next to two or more DATA patterns.
To enter a pattern into the CODE field:
1.
2.
Move the screen cursor to the desired CODE field:
DATA
CODE
(00000000]
[00000000]
Use the data entry keys to enter the desired pattern. The DAS will display the value you enter in
the CODE field:
DATA
CODE
[00000000]
[00001111]
3-70
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
3.
Repeat this procedure for each line until all the desired patterns are entered in the CODE fields
to the right of the existing patterns.
NOTE
If more than one DATA pattern is converted to the same CODE pattern, the
conversion of DATA to CODE can not be reversed by switching the - field to -.
5 CONVERSION Field
Use the CONVERSION field to exit the TABLE BUILD sub-menu.
To exit the TABLE BUILD sub-menu:
1.
Move the screen cursor to the CONVERSION field:
[CONVERSION] : [TABLE BUILD]
2.
Press the SELECT key. The DAS will display the 91S16 Program Run sub-menu.
[CONVERSION] : [
CONVERT] POD [
]
COpy
Use the COpy command to duplicate sequence lines programmend in the 91 S 16 Run submenu, or to copy the data programmed for one pod to another. The command has a field that allows you to select either SEa (sequences within the Run sub-menu) or POD (copy one pod's data
to another pod).
To change the COpy command mode between SEQ and POD:
1.
Move the screen cursor to the field next to COpy:
[
2.
COpy
]: [SEa] [
] THROUGH [
] BEFORE SEa [
Press the SELECT key until the desired mode appears in the field.
[
COpy
]: [POD] [
] TO [
]
SEQ Use the SEa sub-command to duplicate sequence lines of program within the 91 S 16 Run
sub-menu. When the COpy SEa command is executed. all sequence lines specified are duplicated
and placed immediately before the given destination. The sequence numbers for the menu are then
updated; labels are retained in the duplicated lines.
NOTE
Using the COPY command when a/l 1024 sequence lines have been programmed may cause some high-numbered sequence lines to be /ost from
memory. (Only 1023 sequence lines are available when IRQ CALL is enabled.) The number of sequence lines lost wiH correspond to the number of
new lines inserted. If you must add new sequence lines to a lengthy pattern,
use the DELETE command first to remove unnecessary lines and make room
for the additions.
3·71
Operating Instructions
CAS 9100 Series 91516-91532 Service
To copy sequence lines:
1.
Move the screen cursor to the SEa/THROUGH fields.
LABEL
SEa
0
1
2
3
4
5
LOOP
END
6
7
8
9
4B 4A
S
FF
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
FF
00
00
00
00
00
00
00
00
00
[ COPY] : SEa
2.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEa FLOW, CONTROL
IF R=O JUMP
JUMP
THROUGH
]
BEFORE SEa
REG,OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
[
Use the data entry keys to enter the starting and ending sequences as well as a destination se~
quence. For example, to make a copy of sequence lines 0 through 4 and to place them before
sequence line 5:
[ COPY] : SEa
3.
M
0]
THROUGH
[
4]
BEFORE SEa
5]
Press the EXECUTE key to initiate the COpy SEa command.
LABEL
SEa
0
1
2
3
4
5
6
LOOP
END
LOOP
7
8
9
10
END
11
12
13
14
[ COPY] : SEa
484A
S
FF
01
02
03
04
FF
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
0
FF
00
00
00
00
FF
00
00
00
00
00
00
00
00
00
M
0
0
0
0
0
0
0
0
0
0
0
a
a
a
0
0
0
a
a
THROUGH
0
0
0
0
0
0
0
0
0
0
0
0
SEa FLOW, CONTROL
IF R=O JUMP
JUMP
IF R=O JUMP
JUMP
REG,OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
LOAD R
END
LOOP DECR R
OUT R
OUT R
a
0
0
]
BEFORE SEa
[
The DAS will display the message 'COPIED SEa 0 THROUGH 4 BEFORE SEa 5" in the
message field at the top of the display when the operation is complete. The DAS will also blank
the SEa and THROUGH fields to prevent accidental operation.
NOTE
When sequence lines with labels are copied. these labels are duplicated in the
new lines. Before you start the pattern generator. or exit the Pattern
Generator menus. you must remove these duplicate labels.
3-72
Operating Instructions
DA5 9100 Series 91516-91532 Service
POD Use the POD sub-command to duplicate a pattern entered into memory for one pod and put
a copy of the same pattern into memory for another pod. If there is already data in the destination
pod, it will be discarded when the new pattern is copied into that pod's memory .
. To copy a data pattern from one pod to another:
1. Move the screen cursor to the COPY: POD field.
SEa
LABEL
0
1
2
LOOP
3
4
5
6
7
8
9
END
[ COpy] : POD
2.
4B 4A
S
FF
01
02
03
04
05
06
07
08
09
FF
00
00
00
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
[
]
TO
0
0
0
0
0
0
0
·0
0
0
0
0
0
0
0
0
0
0
0
0
SEa FLOW, CONTROL
IF R=O JUMP
JUMP
REG, OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
[
Use the data entry keys to enter a pod 1.0. For example, to make a copy of POD 4B and send it
to POD 4A:
[ COpy ] : POD
3.
M
[4B]
TO
[4A]
Press the EXECUTE key to start the COpy POD operation.
The DAS will display the message "COPIED POD 4B to 4A" in the message field on the second
line of the display when the COpy POD operation has been completed. The DAS will also blank
the source and destination fields to prevent accidental operation.
SEa
LABEL
o
1
LOOP
2
3
4
END
5
S
FF
01
02
03
04
05
o
o
o
o
o
o
o
o
o
o
FF
01
02
03
04
05
06 06
6
7
8
07 07
08 08
09 09
9
[ COPY]
4B 4A
POD
[
]
TO
M
0
0
0
0
0
0
0
0
0
0
SEa FLOW, CONTROL
o
o
o
o
o
o
o
o
IF R=O JUMP
JUMP
REG. OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
o
o
(
DELETE Use the DELETE command to erase sequence lines within the Program Run sub-menu.
When the DELETE command is executed, all sequence lines between the given starting and ending
sequence lines (inclusive) are deleted. The remaining sequence line numbers are automatically
updated.
3-73
Operating Instructions
CAS 9100 Series 91516-91532 Service
NOTE
When sequence lines are removed by the DELETE command, a corresponding number of new sequence lines containing default values are created at
the end of the pattern generator's memory. These new sequence lines will be
inserted after the last sequence line that contains programming data in order
to maintain a total of 1023 sequence lines (IRQ CALL enabled) or 1024 lines
(IRQ CALL disabled).
To delete one or more sequence lines:
1.
Move the screen cursor to the edit command field at the bottom of the Run sub-menu screen.
Press the SELECT key until DELETE appears in the field.
2. Move the screen cursor to the SEa field.
LABEL
SEa
0
1
LOOP
2
3
4
5
6
7
END
8
9
[ DELETE
3.
J
4B 4A
S
FF
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
FF
00
00
00
00
00
00
00
00
00
SEa
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEa FLOW, CONTROL
IF R=O JUMP
JUMP
REG,OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
THROUGH
Use the data entry keys to enter the sequence numbers of the first and last lines you wish to delete. If you only wish to delete one line, enter that sequence number in both fields.
3]
[ DELETE ] : SEa
4.
M
THROUGH
[
5]
Press the EXECUTE key to start the DELETE operation. The DAS will display the message
"DELETED SEa 3 THROUGH 5" when the DELETE operation has been completed. The DAS
will also update the remaining sequence line numbers, and blank the SEa and THROUGH fields
to prevent accidental operation.
SEa
LABEL
o
1
LOOP
2
3
4
5
6
7
8
9
DELETE
SEa
M
4B 4A
S
FF
01
02
06
07
08
09
10
11
12
000
o 0 0
0
0
000
000
000
000
000
000
000
FF
00
00
00
00
00
00
00
00
00
o
THROUGH
3-74
SEa FLOW, CONTROL
IF R=O JUMP
JUMP
REG. OUT
LOAD R
END
LOOP DECR R
Operating Instructions
CAS 9100 Series 91516-91532 Service
DISPLAY Use the DISPLAY command to select the display radix for the pod data, S (Strobe), I
(Internal Inhibit), and M (Interrupt Mask) fields. This command makes it easier for you to read the
values programmed into these fields, or to remove them from the display if they are not being used.
To remove or change the radix of the pod data,S, I, and M, fields:
1.
Move the screen cursor to the edit command field and press select until DISPLAY appears.
SEa
LABEL
0
1
2
3
4
5
6
7
8
9
LOOP
END
[ DISPLAY]
2.
4B 4A
S
FF
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
FF
00
00
00
00
00
00
00
00
00
M
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEa FLOW, CONTROL
IF R=O JUMP
JUMP
REG,OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
4B [HEX] 4A [HEX] S [HEX] I [HEX] M [HEX]
Move the screen cursor to the DISPLAY command field you want to change and press the SELECT key to change the radix or to tum off the field. For example, to change the radix for the S
and I fields to BIN (binary), and to tum off the M field:
[ DISPLAY] : 4B (HEX] 4A [HEX] S [BIN] I [BIN] M [OFF]
The DAS will then change the display of the S, I, and M fields as follows:
SEa
LABEL
0
1
2
3
4
5
6
7
8
9
LOOP
END
[ DISPLAY]
48 4A
S
FF
01
02
03
04
05
06
07
08
09
00
00
00
00
00
00
00
00
00
00
FF
00
00
00
00
00
00
00
00
00
M
00
00
00
00
00
00
00
00
00
00
SEa FLOW, CONTROL
IF R=O JUMP
JUMP
REG,OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
4B [HEX] 4A [HEX] S [BIN) I [BIN] M [OFF]
FILL Use the FILL command to automatically fiR in the values of the #8 (POD-B data), #A (PODA data). S (Strobe), I (Internal Inhibit). and M (Interrupt Mask) fields with some constant values. For
instance. if you knew you wanted all the sequence lines from line 20 through line 30 to have thesame data value for POD-A. you could use the FILL command to automatically enter that value in
each data field instead of having to enter the value for each line individually.
You might use this command to change all the default values in the S (Strobe) field from Os to 1s, or
you might want to protect a block of sequence lines from external interrupts by programming a 1
into the M (Interrupt Mask) field for each line.
3·75
Operating Instructions
CAS 9100 Series 91516·91532 Service
The FILL command displays its own fields which are used to modify each of the Run sub-menu's
data. S.I, and M columns simultaneously. You can use this command to modify all of the columns in
a single operation, or you can choose to modify just one or two columns at a time. Entering a
DON'T CARE (X) into a FILL command field means that column's data will not be affected by the
editing operation. For example, entering a DON'T CARE into the FILL command's S field means
that values entered into the Run sub-menu's strobe column will not be affected by a FILL operation.
To use the FILL command:
1. Select the FILL command by pressing the SELECT key while the cursor is in the edit command
field at the bottom of the DAS display.
2.
Move the screen cursor to the SEa field:
LABEL
SEa
0
1
2
3
4
5
6
7
8
9
LOOP
END
FF
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
FF
00
00
00
00
00
00
00
00
00
M
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEa FLOW, CONTROL
IF R=O JUMP
JUMP
REG,OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
Use the data entry keys to enter the starting and ending sequence numbers. Then move the
cursor to the appropriate field and enter the pattern you wish to place in aU the corresponding
fields within that sequence range. For example, to fill SEa lines 1 through 4 with "XX AA X 0 1":
[
4.
S
] THROUGH [
] : SEa [
]
[XX XX] [X] [X] [X] -------------
FILL
3.
4B 4A
FILL
]: SEa [
1] THROUGH [
4]
[XX AA] [Xl [0] [1] --------
Press the EXECUTE key to start the FILL operation. The DAS will display the message
"FILLED SEa 1 THROUGH 4" on the second line of the display when the FILL operation has
been completed. The DAS wilt also blank the SEa and THROUGH fields. but not the pattern
fields.
SEa
LABEL
0
1
2
3
4
5
6
7
8
9
FILL
LOOP
END
4B 4A
S
FF
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
FF
AA
AA
AA
AA
00
00
00
00
00
M
0
0
0
0
0
0
0
0
0
0
SEa FLOW. CONTROL
0
1
1
1
1
0
0
0
0
0
] THROUGH [
SEa I
]
[XX AA I [X) [0) [1] ----••-••--
3·76
IF R=O JUMP
JUMP
REG. OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
INSERT Use the INSERT command to insert additional sequence lines into the Program Run submenu. The number of additional lines specified in the LlNE(S) field are inserted just before the
destination sequence line. The SEa numbers for all the sequence lines are then updated. Newly inserted sequence lines always contain default values.
NOTE
If you are adding sequence lines to a program already containing 1023 lines
(IRQ CALL enabled) or 1024 lines (IRQ CALL disabled), you will force the last
lines in your program out of memory. The number of lines lost will correspond
to the number of new lines inserted. If you must add new sequence lines to a
lengthy pattern, use the DELETE command first to remove unnecessary lines
and make room for the new lines.
To insert sequence lines:
,.
2.
Select the INSERT command by pressing the SELECT key while the cursor is in the edit
command field at the bottom of the Program Run sub-menu.
Move the screen cursor to the LlNE(S) field.
LABEL
SEa
,
LOOP
2
3
4
END
0
5
6
7
8
9
INSERT
1: [
4B 4A
S
FF
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
FF
00
00
00
00
00
00
00
00
00
1 LlNE(S)
M
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEa FLOW, CONTROL
IF R=O JUMP
JUMP
REG,OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
BEFORE SEa [
3 . Use the data entry keys to specify the number of lines you wish to add, and the sequence line
where they are to be inserted. For example, to insert 3 lines before SEa 2:
[
INSERT
1: [
3] LlNE(S) BEFORE SEa [
3·77
2]
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
3.
Press the EXECUTE key to start the INSERT operation. The DAS will display the message" INSERTED 3 LlNE(S) BEFORE SEa 2" in the message field when the insert operation has been
completed. The DAS will also update the remaining sequence numbers, and blank the LlNE(S)
and SEa fields to prevent accidental insertions.
SEa
LABEL
o
1
LOOP
2
3
4
5
6
7
END
8
9
10
4B 4A
S
FF
01
00
00
00
02
03
04
05
06
07
000
000
000
000
000
000
000
000
000
000
000
000
000
08
09
11
12
[ INSERT] : [
]
FF
00
00
00
00
00
00
00
00
00
00
00
00
M
SEa FLOW, CONTROL
REG, OUT
LOAD R
IF R=O JUMP
END
LOOP DECR R
OUT R
OUT R
JUMP
LlNE(S) BEFORE SEa
MODIFY The MODIFY command uses logical operators to manipulate data already entered into
the Program Run sub-menu. Three logical operators are available: AND, OR, and XOR (exclusive
OR). Any programmable numeric column in the Run sub-menu can be modified by using these
operators. For instance, you can modify one or both of the data fields, and the S (strobe), I (internal
inhibit), and M (interrupt mask) fields, or any combination of the above. You can also limit the
modification to a range of sequence numbers.
By ANDing a particular column with 0, you can modify all the data in that column to Os. (Any number
ANDed with 0 equals 0.) By ORing a column with a 1, you can set all the bits in that column to 1.
(Any number ORed with a 1 equals 1.) By XORing any pattern with a 1, the bit pattern in that field is
inverted. (In other words, all FFs hex would be changed to OOs, and all 11s hex become EEs.)
Here are reminder truth tables for the AND, OR, and XOR operations:
A OR B
A AND B
A XOR B
A
B
A AND B
A
B
A OR B
A
B
A XOR B
0
0
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
1
1
0
1
1
1
0
0
0
1
1
0
1
1
1
1
1
0
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
To MODIFY a column's data:
1.
When the screen cursor is in the edit command field, press the SELECT key until the MODIFY
command is displayed.
2.
Move the screen cursor to the field immediately to the right of MODIFY and press the SELECT
key until the desired logical operator is displayed. Logical operators are displayed in this order:
AND, OR, XOR.
LABEL
SEQ
0
1
LOOP
2
3
4
END
5
6
7
a
9
[ MODIFY]
4B 4A
S
FF
01
02
03
04
05
06
07
08
09
0
0
0
0
FF
00
00
00
00
00
00
00
00
00
a
0
0
0
0
0
0
M
SEQ FLOW, CONTROL
0
0
0
0
IF R=O JUMP
JUMP
0
0
0
a
a
a
a
0
a
0
0
0
0
0
a
LOAD R
END
LOOP DECR R
OUT R
OUT R
LOGICAL [AND] SEQ [
] THROUGH [
[XX XX] [X] [X] [X] ----------
-
3.
REG, OUT
-----
Move the screen cursor to the SEQ and THROUGH fields. Use the data enty keys to enter the
number of the first and last sequence line you want to modify. For example, to modify sequence
lines 1 through 9, enter:
1] THROUGH [
9]
[ MODIFY ] : LOGICAL [XOR] SEQ [
[XX XX] [X] [X] [X] ---------- -----------
4.
Move the screen cursor down to the pattern line and enter the pattern you wish to use as a
modifier. For example, to invert all the column B data pattern, select XOR as the logical
operator and enter FFhex in the column B field. (Fields containing X are not affected by the
MODIFY command.)
[ MODIFY ] : LOGICAL [XOR] SEQ [
1] THROUGH [
9]
---[FF XX] [Xl [X] [Xl ---------- ----
5.
Press the EXECUTE key to start the MODIFY operation. The DAS will display the message
"MODIFIED SEQ 1 THROUGH 9" in the message field at the top left-hand corner of the display.
The DAS will also blank the SEQ and THROUGH fields to prevent accidental operation.
SEQ
LABEL
0
1
2
3
4
5
6
7
a
9
LOOP
END
4B 4A
S
I
M
FF
FE
FD
FC
FB
FA
F9
Fa
F7
F6
a
a
a
a
a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FF
00
00
00
00
00
00
00
00
00
0
0
a
0
0
0
0
0
0
a
SEQ FLOW, CONTROL
IF R=O JUMP
JUMP
3-79
REG, OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
Operating Instructions
OAS 9100 Series 91S16-91S32 Service
[ MODIFY
1:
LOGICAL [XOR] SEa [
1 THROUGH [
[FF XX] [Xl [X] [X] ----------- -----------
MOVE Use the MOVE command to move a block of sequence lines within a program to another
location within that same program. When MOVE is executed, all the specified sequence lines are
moved to a location just before the given destination sequence line. The sequence numbers are
then automatically updated. Labels, data, and instructions are retained when sequence lines are
moved.
Using the MOVE command will not destroy high-numbered program lines even if all 1024 lines have
been programmed.
To MOVE a block of sequence lines from one location to another:
1.
Select the MOVE command by pressing the SELECT key when the screen cursor is in the edit
command field at the bottom of the 91S16 Program Run sub-menu.
2.
Move the screen cursor to the SEa field.
SEa
LABEL
0
1
2
3
4
5
6
LOOP
END
7
8
9
MOVE
3.
S
FF
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
FF
00
00
00
00
00
00
00
00
00
M
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
] THROUGH [
] : [SEa] [
SEa FLOW, CONTROL
IF R=O JUMP
JUMP
REG,OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
] BEFORE SEa [
Use the data entry keys to enter the starting, ending, and destination sequence numbers. For
example, to move sequence lines 1 through 3 and place them before sequence line 7:
[
4.
484A
MOVE
1:
[SEa] [
1] THROUGH [
2] BEFORE SEa [
7]
Press the EXECUTE key to start the MOVE operation. The DAS will display the message
"MOVED SEa 1 THROUGH 2 BEFORE SEa 7" on the message line. The DAS will also update
all the sequence lines and blank the SEa, THROUGH, and BEFORE fields to prevent
accidental move operations.
SEa
LABEL
0
1
2
3
4
5
6
7
8
9
MOVE
END
LOOP
4B 4A
S
FF
03
04
05
06
01
02
07
08
09
0
0
0
0
0
0
0
0
0
0
[SEa] [
FF
00
00
00
00
00
00
00
00
00
M
0
0
0
0
0
0
0
0
0
0
1 THROUGH
0
0
0
0
0
0
0
0
0
0
[
3-80
SEa FLOW, CONTROL
REG, OUT
LOAD R
OUT R
OUT R
IF R=O JUMP
JUMP
] BEFORE SEa [
END
LOOP DECR R
Operating Instructions
CAS 9100 Series 91S16·91S32 Service
SEARCH Use the SEARCH command to locate some specific entry within the body of the
Program Run sub-menu. The entry may be a label. a particular data pattern. or an instruction.
The SEARCH command allows you to specify the type of entry you are going to search for. and to
specify a sequence range for the search. When executed, the SEARCH command compares all entries of the same type against the target string within the range of sequence lines you have
specified. It will then place the screen cursor on the first sequence line containing that string. and
display the total number of lines within the specified range that contain the target string. (The line
total appears in the bottom right-hand corner of the display.)
The data entry keys can be used to select the second. or third. etc. sequence line containing the target string when the screen cursor is in the [
] / # : SEARCHED field. (Instructions for using this
field are included in the following paragraphs.)
To use the SEARCH command:
1.
Select the SEARCH command by moving the screen cursor to the edit command field at the
bottom of the Program Run sub-menu and pressing the SELECT key.
2.
Select the type of pattern you are going to search for by moving the screen cursor to the field
immediately to the right of the SEARCH: command.
[ SEARCH] : [LABEL ] SEQ [
[
]
-
-- -- -
3.
] THROUGH [
- ---------
Press the SELECT key until the desired target group appears in the field.
The DAS will display the target groups in this order:
[ LABEL
]
[PATTERN ]
[SEQ FLOW ]
[JUMP LABEL]
[CONTROL 1
[REG
1
[OUT
1
To SEARCH for a data pattern:
1.
Move the screen cursor to the field immediately to the right of SEARCH:
LABEL
SEQ
0
1
2
LOOP
3
4
5
6
7
8
9
END
4B 4A
S
FF
01
02
03
04
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
{ SEARCH 1 : [LABEL
[
] --
FF
00
00
00
00
00
00
00
00
00
M
0
0
0
0
0
0
0
0
0
0
]
1 SEQ [
-- - - - -----------...-
0
0
0
0
0
0
0
0
0
0
SEQ FLOW, CONTROL
IF R=O JUMP
JUMP
THROUGH [
3-81
REG. OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
Operating Instructions
DA8 9100 Series 91816-91832 8ervice
2.
Press the SELECT key until the target group PATTERN appears in the field.
[ SEARCH ] : [PATTERN ] SEQ [
] THROUGH [
----- [XX XX] [X] [X] [X] -------~
3.
Move the screen cursor to the SEQ and THROUGH fields and enter the starting and ending sequence numbers for the block of program you wish to search. For example, enter SEQ 0
THROUGH 10 to search for a pattern programmed in lines 0 through 10 inclusive. Note: The
larger the search range you specify, the longer it takes for the edit operation to be completed.
This also increases the likelihood you will locate data you are not interested in.
4.
Move the screen cursor to the PATTERN sub-fields and use the data entry keys to enter the
pattern you wish to search for. For example, enter:
[ SEARCH ] : [PATTERN ] SEQ [ 0] THROUGH [
----- [10 00] [X] [X] [X] -------
10]
DON'T CAREs (X's) will match any pattern.
5.
Press the EXECUTE key to start the SEARCH operation. The DAS will display the message,
"<[
1] /
1: SEARCHED>" in the bottom right.hand corner of the display. The first
number in this message indicates that the screen cursor has been placed on the line containing
the first occurrence of the target pattern. The number following the slash tells you how many
lines contain the target pattern within the range you specified for the search.
For example, if you had searched for 00 in a block of text where 15 lines contained the pattern
00, the message would read, "". To see the 14th occurrence
of the target pattern, you would move the screen cursor to the highlighted field in the first part
of this message and type in 14. When you press the EXECUTE key. the screen cursor will be
placed on the line containing the 14th occurrence of the target pattern, and the message field
will read, "".
To SEARCH for an instruction:
1. To SEARCH for an instruction (for example: R OUT) move the screen cursor to the field
immediately to the right of SEARCH: and press the SELECT key until the appropriate
instruction type appears in the field. In the case of R OUT, we want the OUT (output register) instruction type to be displayed in this field.
[ SEARCH ] : [
----- -- --
OUT
] SEQ [
] THROUGH [
- - - --------[OUT R]
2.
Move the screen cursor to the SEQ and THROUGH fields and use the data entry keys to enter
the starting and ending sequence line numbers for the block of program you wish to search. For
example, to search for some target pattern between sequence lines 3 and 10, enter SEQ 3
THROUGH 10.
3.
Move the screen cursor to the OUT sub-field in the lower right-hand corner of the display. Press
the SELECT key until the desired OUT instruction appears in the field. Note that in this case
[OUT R] appears as the default choice. If you had configured the 91 S16 register to be two S-bit
registers, you would have to move the screen cursor to this field and press the SELECT key until the desired instruction appeared. (OUT RA and OUT RS would be the choices in this case.)
SEARCH ] : [
OUT
-
] SEQ [
3] THROUGH [ 10]
------------(OUT RJ
3-82
Operating Instructions
DAS 9100 Series 91516-91532 Service
4.
Press the EXECUTE key to start the SEARCH operation. The DAS will display the message
"<[
1]/
2: SEARCHED>" on the last line of the display to indicate that the SEARCH
operation has been completed. The DAS will also blank the SEQ and THROUGH fields, and position the screen cursor on the first sequence line containing the target pattern.
SEQ
0
1
2
LABEL
4B 4A
S
LOOP
FF FF
01 00
02 00
0
0
0
03 00
04
05
06
07
08
09
3
4
5
6
7
8
9
END
00
00
00
00
00
00
SEARCH ] : [OUT
M
SEQ FLOW, CONTROL
0
0
0
0
0
0
IF R=O JUMP
JUMP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
] SEQ [
REG, OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
3] THROUGH [ 10]
[OUT R]
-- -- - - - --------_...----
NOTE
In the above display sample, the range specified for the SEARCH operation
was from SEQ 3 through SEQ 10. That is why the first OUT R instruction
found was on line 3, rather than on line 2.
5.
Use the data entry keys to enter a value in the" <[
1]/
2: SEARCHED>" message
field if you wish to see a different sequence line containing the target pattern. For instance, if
you wanted to see the second sequence line containing OUT R, you would move the screen
cursor to the inverse-video field within the message and type a 2:
<[
2]/
2 : SEARCHED>
When you push the EXECUTE key the DAS will display:
SEQ
LABEL
0
1
2
3
4
5
6
7
8
9
LOOP
END
4B 4A
S
FF
01
02
03
0
0
0
0
FF
00
00
00
0
0
0
0
M
SEQ FLOW, CONTROL
0
0
0
0
IF R=O JUMP
JUMP
04 00
0
0
0
05
06
07
08
09
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEARCH ] : [OUT
00
00
00
00
00
] SEQ [
REG,OUT
LOAD R
END
LOOP DECR R
OUT R
OUT R
3] THROUGH [ 10]
[OUT RJ
-- -- - - - --------------
The message would then display, "<[
2]/
2: SEARCHED>". Of course, this feature is
more dramatic when the sequence lines containing the target pattern are farther apart.
3-83
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
91S32 PROGRAM: RUN MODE SUB-MENU FIELDS AND VALUES
NOTE
The 91532 Program Run Mode sub-menu appears only when the 91532
Module is installed.
The following paragraphs describe how to use the 91 S32 Program Run Mode sub-menu to enter
patterns for the 91 S32 Pattern Generator Module. They discuss each sub-menu field and list all optional values.
Figure 3-15 illustrates the 91832 Pattern Generator Run Mode sub-menu and its fields. The fields,
which appear in reverse video on the screen, are bracketed [ ] throughout the text. The four
directional cursor keys and the NEXT key can be used to move the blinking screen cursor from one
field to another.
Refer to the numbered callouts in Figure 3-15 when reading the following paragraphs. These
numbers serve as visual references and do not imply sequence of use.
1
--PATTERN GENERATOR PROGRAM: 91S32
5
1MASK
\ '.~
""
"-I
""I ..
6
7
---~
rIHHIBIT
~
-mJ
.0
1
2
3
4
S
6
7
a
9
1e
11
12
13
10
m:EaPAGE: iii
START SEQ: .0-
14
j.l
.. .1',.1
SOC SBA 4DC 4BA
9
8
~
i
.. ,-,
....
.. ..
.. ..
~mm
.I .i
2
3
4
....
eeee eaee aeee eaae
eea0 e000 ee00 0000
8000 aaee eeee aeee
eeee eaee eeee eeee
eeae eaee ee0e 00ee
ee00 eeee 0aeO 0e00
9000 eeee eeeo e0e0
8000 eeee 0a00 e0ae
ee00 0000 0a00 ee0e
eaae 0aee aeee aeee
eeee eaa0 00ae eaae
0000 000e 0000 00130
eeee eeae €Ieee 0000
ee00 eaee e0ae aeee
ge
Be
ee
ee
ee
ee
Be
a0
00
0a
ea
Be
00
ee
ae
00
ae
ee
oe
0e
0e
ee
ee
ee
ee
00
00
a0
:~POD.
5397-22
Figure 3-15. 91S32 Program: Run sub-menu.
NOTE
In the following discussion, the three 91532 Modules are assumed to reside
in DA5 slots 3, 4, and 5.
3-84
Operating Instructions
CAS 9100 Series 91516-91532 Service
1 PATTERN GENERATOR PROGRAM Field
Use this field (directly to the right of the menu title) to select either the 91 S16 or the 91 S32 submenu display. Refer to the description of the Sub-Menu Selections in the Menu Overview section of
this addendum. If the 91S16 Module is installed, the 91S16 sub-menu is displayed as the default
sub-menu. Otherwise, the 91 S32 sub-menu is displayed.
To change the display to show the 91S32 sub-menu:
1.
Move the screen cursor to the field directly to the right of the menu title.
PATIERN GENERATOR PROGRAM: [91S16]
2.
Press the SELECT key until 91 S32 appears in the field.
The DAS displays the sub-menu titles in this order:
[91 S16]
[91 S32]
2 MODE Field
Use the MODE field to select the Pattern Generator's operating mode.
The pattern generator normally outputs data in real-time fashion synchronously with the clock
signal. This is called Run mode, hence the name of this sub-menu. The pattern generator can also
output data at much slower rates, or even one step at a time, for debugging purposes. These
modes of operation are called Trace and Step modes, and are described in the Trace Mode and
Step Mode section of this manual.
Press the SELECT key when the screen cursor is in the MODE field to change between Run, Trace,
and Step modes. The MODE field defaults to Run mode on power-up.
3 PAGE Field
The 91 S 16 sequential pattern generator can act as a controller for one or more 91 S32s. However,
the 91 S16 has only 1024 lines of pattern memory, compared to the 91 S32 which has 2048 lines of
pattern memory. You can divide the 91 S32's memory into two 1024-line pages and use the 91 S16
INCR PAGE command to switch between the two pages. This approach has several programming
advantages which are explained under the SEQUENTIAL and FOLLOWS modes descriptions in
the 91 S32 Configuration Menu section. The PAGE field indicates which PAGE of memory (A or B) is
being displayed.
Note that there are two possible sequence numbering schemes for the 91 S32. The SEQ field has
two possible values: ASEQ and RSEQ. Instructions for changing between these values are given
later in this section, but the numbering scheme selected affects the PAGE field. When ASEQ
(Absolute Sequence) is selected, the 91 S32's program lines are numbered from 0 through 2047;
page 8 will start with sequence 1024. RSEQ stands for Relative Sequence (relative to page A or
page B). When RSEQ is selected, the 91 S32's program lines are numbered from 0 through 1023 for
page A, and from 0 through 1023 for page B. Use the numbering scheme that is most convenient to
you.
If you are using the 91 S32 with its memory divided into two pages, you can select which page of
data appears on the display. The default value for the PAGE field is A.
3·85
Operating Instr!Jctions
CAS 9100 Series 91S16-91S32 Service
To display the other memory page:
1.
Move the screen cursor to the PAGE field.
PAGE: [A]
2.
Press the SELECT, INCR, or DECR key until the desired value appears in this field. For
example, select page B:
[B]
4 START
sea
Field
Use the START SEQ field to designate the first sequence line the pattern generator will execute
when you press the START PAT GEN key or the START SYSTEM key.
If the 91 S32 is being used without a 91 S16, or if the 91 S32 is being used with a 91 S16 in the SEQUENTIAL mode, the number you enter in the START SEQ field will determine the first sequence
line executed. If the 91 S32 is being used with a 91 S 16 in the FOLLOWS mode, you cannot set a
value in this field, since the starting sequence will be set by the 91 S 16. For an explanation of SEQUENTIAL and FOLLOWS modes, see the 91532 Configuration Menu section of this manual.
The START SEQ number you enter will depend on how you have configured your SEQ field: either
ASEQ (absolute sequence numbers) or RSEQ (relative sequence numbers). If the sequence
number field is set to ASEQ, you can enter a START SEQ value between 0 and 2047. (IRQ enabled
CALL < label> mode reduces the number of availble sequence lines by one.) If you have set the sequence number field to RSEQ, you must set the memory page (A or B) and enter a sequence number between 0 and 1023. See the 5EQ Field description later in this section for information on selecting ASEQ or RSEQ.
This field defaults to page A and sequence O.
To specify the page and the sequence number for the START SEQ:
1.
Move the screen cursor to the START SEQ field.
START SEQ: [A] [ 0]
2.
Press the SELECT, INCR, or DECR key to change the page. For example, to select page B:
[B] [ 0]
3.
Use the data entry keys to enter the starting sequence number. For example, to start the
pattern generator at line 500:
[B] [ 500]
3-86
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
5 INHIBIT MASK Field
Use the INHIBIT MASK field to specify whether or not the data output channels respond to the inhibit signal. If the inhibit mask for a given data channel is set to 0 (unmasked), then that data channel is tri-stated whenever the inhibit signal is asserted. If the inhibit mask is set to 1 (masked), then
the inhibit signal is masked out and that data channel is not tri-stated, even though the inhibit signal
has been asserted. You can set the inhibit mask for each individual data channel in a pod by
specifying a hexadecimal value in the INHIBIT MASK field. The default value for this field is 0
(unmasked for all data channels).
To specify the inhibit mask for a data pod:
1.
Move the screen cursor to the INHIBIT MASK field:
INHIBIT
MASK: [0000 0000 0000 0000 0000 0000]
2.
Use the data entry keys to specify (in hexadecimal) the inhibit mask for each data pod. The
oAS will automatically move the screen cursor one space to the right after you have entered a
value.
INHIBIT
MASK : [FOOO OEOO 0000 OOOC BOOO OAOO]
6 SEa (Sequence) Field
The SEa field consists of a column of numbers running down the left side of the display. Each number in this column corresponds to one sequence line. The program lines are displayed sequentially
starting with page A, sequence O. There are 2048 total sequence lines, but they can be numbered
either of two ways. When the SEa field is set to ASEa (absolute sequence numbers), the sequence
lines are numbered from 0 through 2047. When the SEa field is set to RSEa (relative sequence
numbers), the sequence lines are divided into two pages of data, page A and page B. The sequence
lines are numbered page A, 0 through 1023, and page B. 0 through 1023. Dividing the memory into
two pages has certain programming advantages explained under the 91532 Configuration Menu
description. The PAGE field description in this section explains how to switch from one page to the
other. Only a portion of the sequence lines are displayed at any given time.
To select either ASEQ or RSEQ;
1.
Move the screen cursor to the SEa field.
[ASEa]
2.
SOC
SBA
40C
4BA
30C
3BA
S
Press the SELECT key until the desired value appears in this field. For example, RSEa.
The oAS displays optional values in this order.
[ASEa]
tRSEa]
You can display different sequence lines several different ways. The first method is to use the scroll
keys. You can use these keys at any time and with the cursor in any field.
3-87
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
To scroll through the sequences:
1.
Press the up (1) or down (L ) scroll key. Additional sequence lines will scroll up from the bottom
or down from the top of the display.
The second method for viewing more program lines requires you to enter a new number over an existing number displayed in the SEa field. This method allows you to jump forward or backward and
display specific blocks of sequence lines.
To move forward and display larger-numbered sequence lines:
1.
Move the screen cursor to the sequence number you wish to change. For example, move the
cursor to SEa 11:
[ASEa]
[ 11]
2.
Use the data entry keys to enter the first sequence number you wish to have displayed. For example, SEa 200. The DAS will display [200] in place of [ 11]. and then update the rest of the sequence lines following that position.
[ASEa]
o
1
2
3
4
5
6
7
8
9
10
[ 200]
201
202
203
SEa 11 is changed to SEa 200
and the rest of the sequence
numbers are updated from that
position to the bottom of the display.
To move backward to a smaller-numbered block of program lines:
NOTE
The preceding sequence number on the display must always be smaller than
the number you enter. If you want to display a number smaller than any
currently displayed, you must enter that number in the top-most SEQ field on
the display.
1.
Move the screen cursor to the sequence number you wish to replace with a lower number. For
example, SEa 200.
[ASEa]
[200]
3·88
Operating Instructions
OAS 9100 Series 91516·91532 Service
2.
Press the DON'T CARE key.
The DAS enters a 0 at the cursor location.
3.
Use the data entry keys to enter the sequence number to be displayed. For example, 15.
The DAS displays SEa 15 at the cursor location, then updates the rest of the sequences from
that position.
[ASEa]
o
1
2
3
4
5
6
7
8
9
10
[ 15]
16
17
18
SEa 200 is changed to SEa 15,
and the rest of the sequence
numbers are updated from
that position.
NOTE
When using the above procedures, observe the following two rules: 1), if the
cursor is positioned below the top sequence number on the display, you
cannot enter a number smaller than the number directly above the cursor
location. 2) you cannot enter a number greater than 2047 for ASEO and
1023 for RSEO.
7 #OC and #BA Pattern Field
The pattern fields that appear on the sub-menu are used to specify the data pattern you wish to
output through the P6464 probes. Data channels are grouped into pods of eight channels that
correspond to a particular P6464 probe. A data pod is identified by a letter-number scheme called
pod 1.0. The pod 1.0. number references the slot in the DAS where the 91 S32 Module resides. The
letters identify the connectors on the back of the 91 S32 where the probes are attached. For
example, a 91 S32 installed in DAS slot 5 would have data column headings named SOC and 5BA.
Data values are normally entered in hexadecimal, one pod at a time, card by card, and one line at a
time. In other words, you would program the pattern for Pod 0, and then Pod C, Pod B, and finally
Pod A. If you had another 91 S32, you would repeat this procedure until all pods had been
programmed, and then move to the next sequence line. When the pattern generator is running, all
pods output data synchronously with the output clock.
See the DISPLA Y Command description later in this section for information about changing the display radix of the data columns. Data channels default to 0 for all cards and pods.
3·89
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
To enter data on any program line:
1.
2.
3.
Move the screen cursor to the pattern field in the line you wish to program. Position the cursor
over the pod to be programmed.
6DC
6BA
5DC
5BA
4DC
4BA
[0000
0000
0000
0000
0000
0000]
Use the data entry keys to enter the pattern you desire. The DAS will display the data values
you have entered in the field and then shift the cursor one space to the right. For example, enter
the value 3hex for the 91 S32 in DAS slot 6, pod D:
6DC
SBA
5DC
5BA
4DC
4BA
[3000
0000
0000
0000
0000
0000]
Continue entering data values until all the pods have been programmed. Then press the NEXT
key and the cursor will move to the first data field of the next line.
8 S (Strobe) Field
Use the S field to select whether or not the strobe lines associated with each pod will be output
when this particular program line is executed. This field allows you to individually assert the strobe
signals for pods D, C, B, and A. Data pods are grouped into pairs, and each pair is represented by a
column in the Strobe field. Strobe values are entered according to the display radix.
When more than one 91 S32 is installed, the Strobe field width will expand. Strobe field columns will
correspond to the order of data-field columns. In other words, the data column displayed at the left
of the screen will correspond to the two high-order bits in the strobe field.
Strobes function just like additional data lines. The strobe transitions are synchronous with the
output clock. The strobes are asserted by entering a 1 Omary into the sequence line's associated S
bit. (Note: Pay attention to the display radix.) In default, the strobes are set to as. See the DISPLAY
Command description later in this section for instructions on changing the strobe field display radix.
To assert a strobe:
1.
Move the screen cursor to the S field on the line you wish to program.
S
[000]
2.
Use the data entry keys to enter the data value. For example, to assert the strobes of both pod
5A and 3D in hex, enter 108.
[108]
9 I (Inhibit) Field
Use the I (Inhibit) field to set the internal inhibit Signal. The internal inhibit signal temporarily tristates the output of one or all of the pods. Data pods are grouped into pairs, and each pair is represented by a column in the Inhibit field. Pods displayed on the left will be represented by the left-most
column in the Inhibit field. Inhibit field values are entered for two pods at a time, usually in
hexadecimal.
3-90
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
When more than one 91 S32 is installed. the Inhibit field width will expand. Inhibit field columns will
correspond to the order of the data-field columns. In other words. the data column displayed at the
left of the screen will correspond to the two high-order bits in the Inhibit field.
The 91 S32 provides two kinds of inhibit signals: Internal inhibits programmed in the 91 S32
Program Run sub-menu. and External inhibits. delivered to the 91 S32 via the P6452 External Clock
(Data Acquisition)probe attached to the DAS Trigger/Time Base module. The 91 S32 Configuration
sub-menu allows you to select the polarity of each inhibit signal. and combine the two signals using
logical operators.
For the following example. assume that the inhibit signals have been set to the following values: INHIBIT [INTERNAL 1] ONLY. (See the 91532 Configuration Sub-Menu description earlier in this
addendum.)
Setting a Ohex in the I (Inhibit) field means that neither pod in the pair is tri-stated and both pods will
continue to output data. clock. and strobe lines. Setting a 1hex in this field will tri-state the outputs
of Pod A. Setting a 3hex in this field will cause pods A and B to be tri-stated.
Note that some data may still be output from a pod that has been tn-stated, because any value you
set in the INHIBIT MASK field will cause certain data lines to ignore the inhibit signal. Inhibit mask
fields for the strobe and clock lines appear in the Configuration sub-menu.
Values for the I (Inhibit) field must be set for every sequence line. The default value is 0 and the default radix is hexadecimal. See the DISPLAY command discription under the 91532 RUN SubMenu section for instructions on selecting a different display radix. The internal inhibit signal
becomes effective in sync with the output clock.
If you are logically combining the internal and extenal inhibit signals in the Setup: Probe sub-menu,
it is wise to check the inhibit interaction by viewing a portion of your program while in Step mode.
To assert an internal inhibit:
1. Move the screen cursor to the line you wish to program and position the cursor over the
appopriate I field. In this example, there are 91 S32s in DAS slots 6, 5, and 4.
I
[000]
2.
Use the data entry keys to enter the data value. For example, to assert the internal inhibits for
pods SA, 40 and 4C in hex, enter 1CO.
The DAS will display the value you enter in the I field.
[1CO)
3·91
Operating Instructions
CAS 9100 Series 91516·91532 Service
10 EDIT Fields
The 91 S32 Module provides nine edit commands to manipulate data patterns on program lines.
These commands are designed to simplify programming.
To select the edit command:
1.
Move the screen cursor to the edit field at the bottom of the screen:
[CONVERSION] : [CONVERT
2.
] POD [
]
Press the SELECT key until the desired command appears in the field. In addition to the
SELECT key, the INCR and DECR keys may also be used to select from the edit commands.
The INCR key selects the next command given in the list below, and the DECR key selects the
previous command. Pressing anyone of these keys will cause the DAS to scroll through the list
of options.
The DAS will display the list of possible edit commands in this alphabetical sequence:
[CONVERSION
[COpy
[DELETE
[DISPLAY
[FILL
[INSERT
[MODIFY
[MOVE
[SEARCH
]
]
]
]
]
]
]
]
]
Each edit command has a specialized function. The CONVERSION command has a sub-menu
used to make and check a conversion table. Several commands have sub-fields you will use to
specify starting and ending sequence lines, or select among additional sub-commands. Some
of the commands will have fields that require you to enter setup and editing parameters.
3.
After entering the changes you wish to make for any of the edit operations, press the
EXECUTE key. Some of the fields, such as those pertaining to sequence numbers, will be
blanked after the edit operation has been completed. This is to prevent you from accidentally
pressing EXECUTE again and damaging your corrected program.
The following paragraphs briefly describe what each of the edit commands does, and how to
use them.
CONVERSION The CONVERSION command allows you to search for and replace all pattern
data values with corresponding different values in one operation. For instance, if you knew you
wanted to replace all FFs in your program with AAs, and replace aU 1Es with OOs, you could use the
CONVERSION command to do that in one operation.
This feature is most commonly used when you are converting data from one coding system to another, such as from a normal binary counting method to Gray code where only one bit changes as
numbers are incremented.
3·92
Operating Instructions
CAS 9100 Series 91S16·91S32 Service
The CONVERSION command has two sub-commands: CONVERT, which designates which pod's
data is to be converted, and TABLE BUILD. The TABLE BUILD command displays a special submenu called the TABLE BUILD sub-menu that allows you to specify which bit patterns are to
change. Instructions for using this sub-menu are included in the following paragraphs.
CONVERT This sub-command instructs the pattern generator to apply the conversion rules
outlined in the TABLE BUILD sub-menu to the data in a particular pod. The way in which the TABLE BUILD sub-menu performs conversions will become clear as you read this section. If you had a
91 S32 in DAS slot 1 and you wanted to modify the data programmed for Pod B according to the
changes given in the TABLE BUILD sub-menu, you would type:
[CONVERSION] : [
CONVERT] POD [1 B]
Press the EXECUTE key to initiate the conversion.
The TABLE BUILD sub-menu only operates on one pod of data at a time, so if you wanted to convert all data patterns for a 91 S32 in DAS slot 1 from one code to another, you would have to CONVERT POD 1A, and then CONVERT POD 1B, 1C and 1D. You will have to run the conversion program four more times for each additional 91 S32 to convert all the data from one code to another.
However, you will often use the different pods for different purposes, and you may only want to
convert one pod's data and leave the rest unchanged.
To specify which pod's data will be converted:
1.
Move the screen cursor to the POD field.
[CONVERSION] : [
2.
Use the data entry keys to enter a pod I.D. For example, pod 6B. The DAS will display the pod
I.D. in the POD field.
[CONVERSION] : [
3.
CONVERT] POD [
CONVERT] POD [6B]
Press the EXECUTE key to start the conversion. The DAS will display "CONVERTED POD 6B"
on the second line of the screen when the conversion has been completed. The DAS will also
blank the POD field to prevent accidental conversions later.
TABLE BUILD The TABLE BUILD sub-menu is used to convert an existing data pattern into
some modified data pattern. The sub-menu provides two columns of 4-digit binary numbers from
0000 to 1111. However, you can set the column widths to be up to a-digits wide. The following examples show a-digit columns to demonstrate the TABLE BUILD's maximum capabilities.
Modifying the bit pattern in the CODE column and executing the CONVERT command on some
pod's data will cause all occurrences of the pattern in the DATA field to be converted to the pattern
in the CODE field.
For example: When you enter this sub-menu, both the DATA and CODE columns will contain the
same bit pattern. Moving the screen cursor to 00000000 in the CODE column, typing in 00000001,
and then executing CONVERT POD 1A will cause all occurrences of 00000000 stored as data in
Pod-1 A to be changed to 00000001.
It may help you to think of the bit patterns in the DATA column as sequence numbers. The bit patterns in the DATA column represent all possible bit patterns. Typing some pattern in a DATA field is
one way to move your editing window from one bit pattern to another; it will not change any data.
3-93
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
To invoke the TABLE BUILD sub-menu:
1. Move the screen cursor to the field containing CONVERT.
[CONVERSION] : [
2.
CONVERT] POD [
]
Press the SELECT key until TABLE BUILD appears in the field. The TABLE BUILD sub-menu
will automatically appear on the screen. Refer to Figure 3-16.
1
2
3
4
5
5397-23
Figure 3-16. Table Build sUb-menu.
1-
Field
The ~ field indicates the direction for converting data. If the arrow is pointing to the right, data in the
right-hand column will replace the data pattern indicated in the left-hand column. If the arrow is
pointing to the left, the pattern in the left-hand column will replace the pattern in the right hand column.
When the arrow is pointing to the right, you can enter the same bit pattern in the right column for
any number of bit patterns in the left column. However, when the arrow is pointing to the left, each
pattern in the left column must convert to a unique pattern in the right column.
As long as you are mapping a unique pattern in the right column to a unique pattern in the left column, this feature allows you to change the data pattern, and then change back easily if you don't
like the results of your first conversion.
This field defaults with the arrow pointing to the right.
To change the direction of the conversion arrow:
1.
Move the screen cursor to the arrow field.
DATA
[-+]
CODE
3-94
Operating Instructions
DAS 9100 Series 91516-91532 Service
2.
Press the SELECT key until the desired arrow appears in the field.
DATA
H
CODE
2 WIDTH Fields
The WIDTH fields are used to select the bit width of the data and code columns. For both columns,
you can select bit widths ranging from 1 to 8 bits.
Usually, you will want to set both column widths to the same value. The bit width you select will determine the depth of the corresponding DATA and CODE fields. However, if you select a width of 4bits for the DATA column and 5-bits for the CODE column, both selection fields will be 16 lines deep
(16 possible patterns from 4 bits); the field depth always truncates to match the shorter column. Selecting a-bit field widths for both columns will generate a TABLE BUILD sub-menu with 256 lines of
bit-patterns.
If you shorten the width of either the DATA or CODE fields after entering some longer value into one
of the fields, the display will change to show the shorter pattern, but the DAS will retain the longer
value in memory until it is turned off. The default width for both fields is 4 bits.
To enter the DATA and CODE fields column widths:
1.
Move the screen cursor to the WIDTH field over the column you wish to change.
DATA
WIDTH
2.
[4] BITS
CODE
[4] BITS
Use the data entry keys to enter the desired column width. For example,
WIDTH
DATA
CODE
[8] BITS
[4] BITS
8~
Remember that no data conversion actually takes place until you EXECUTE the CONVERSION: CONVERT POD [##] command. Depending on how you configure your replacement
data patterns in the TABLE BUILD sub-menu, it is possible that the CONVERT command will
try to replace an 8-bit pattern with a smaller, say 4-bit, pattern. In this case, only the lowest four
bits of the original pattern would be converted to the new pattern, and the data in the four most
significant bits would not be changed. For example, if the original pattern was 11111111 om, and
the replacement pattern from the TABLE BUILD sub-menu was 00000'", the resulting data
would be 1111 OOOObtn.
3 DATA Column
The DATA column automatically appears whenever the TABLE BUILD sub-menu is selected. The
DATA column contains all possible bit-patterns for data entered in the PROGRAM: Run sub-menu.
Bit patterns in the DATA column represent existing data, where bit patterns in the CODE column
represent planned changes to the data. (The only exception to this is when the direction field has
the arrow pointing to the left.)
The depth of the DATA column is dependent on the value entered in the WIDTH field. Since all possible bit patterns for a particular width are shown, most TABLE BUILD sub-menus will be too long
to be displayed on one screen.
There are several ways of displaying different parts of the TABLE BUILD sub-menu. The first
method is to use the scroll keys on the DAS keyboard.
3-95
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
To scroll through the DATA column sequences:
Press the
T
or the
j
scroll key on the keyboard. The DAS will scroll the display up or down.
Another method more suited to big jumps is to enter the desired new pattern in a DATA column
field. Just as in moving through sequence lines in the Program Run sub-menu, the DAS will display
the DATA line you have entered and fill the rest of the page with DATA lines incrementing from that
point.
To move forward through a large block of DATA lines:
1.
Move the screen cursor to the data field you wish to change. For example, line 1010.
DATA
[00000101 ]
[00000110]
[00000111 ]
[00001000]
[00001001 ]
[00001010]
[00001011 ]
[00001100]
[00001101 ]
2.
Use the data entry keys to enter the first DATA line you wish to display. For example,
11001000.
DATA
[00000101]
[00000110]
[00000111]
[00001000]
[00001001 ]
[11001000]
[11001001]
[11001010]
[11001011]
DATA pattern 00001010 is
changed to 11001000 and
the remaining DATA patterns
increase from that line.
The DAS will display DATA line 11001000 in place of line 00001010, and then update the rest of the
DATA lines following that position.
NOTE
Entering a value in one ofthe DATA column fields is one way of displaying a
different portion of this sub-menu; it will not change the data programmed for
a pod in the Run sub-menu.
To display a block of DATA patterns with smaller values:
1.
Move the screen cursor to the first DATA line displayed in the TABLE BUILD sub-menu.
2.
Use the data entry keys to enter the bit pattern you want to display. The display will fill with data
lines starting with the pattern you have entered.
NOTE
The DAS displays DATA patterns in ascending order. To display a DATA
value smaller than any currently displayed, enter the new DATA value in the
topmost DATA column field.
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
4 CODE Field
The CODE field is used to enter the pattern you want to end up with after the conversion; the DATA
field is the pattern you start with. More than one data pattern may be converted to the same CODE
pattern. To do this, enter the same CODE pattern next to two or more DATA patterns.
To enter a pattern into the CODE field:
1.
2.
3.
Move the screen cursor to the desired CODe field:
DATA
CODe
[00000000]
[00000000]
Use the data entry keys to enter the desired pattern. The DAS will display the value you enter in
the CODE field:
DATA
CODe
[00000000]
[00001111]
Repeat this procedure for each line until all the desired patterns are entered in the CODE fields
to the right of the existing patterns.
NOTE
If more than one DATA pattern is converted to the same CODE pattern, the
conversion from DATA to CODE can not be reversed by switching the [-] field
to [-].
5 CONVERSION Field
The CONVERSION field is used to exit the TABLE BUILD sub-menu.
To exit the TABLE BUILD sub-menu:
1.
Move the screen cursor to the CONVeRSION field:
CONVERSION : [TABLE BUILD]
2.
Press the SELECT key. The DAS will display the Run sub-menu.
[CONVERSION] : [
CONVERT] POD [
]
COPY The COpy command is used to duplicate sequence lines programmed in the 91 S32 Run
sub-menu, or to copy the data programmed for one pod to another. This instruction displays a field
that allows you to select either SEQ (copy sequences within the Run sub-menu) or POD (copy one
pod's data to another pod).
To change the COpy command mode between SEa and POD:
1.
Move the screen cursor to the field to the right of COPY:
[
COpy
]: (SEQ] [
1 THROUGH
3-97
(
] BEFORE SEQ [
Operating Instructions
CAS 9100 Series 91S16·91532 Service
2.
Press the SELECT key until the desired mode appears in the field.
[
COpy
]: [POD] [
] TO [
]
SEQ Use the SEa sub·command to duplicate sequence lines of program within the 91 S32 Run
sub·menu. When the COpy SEa command is executed. all sequence lines specified are duplicated
and placed immediately before the given destination. The sequence numbers for the sub-menu are
then updated; labels are retained in the duplicated lines.
NOTE
Using the COpy command when all 2047 ASEQ sequence lines, or all 1023
RSEQ (page A or B) sequence lines have been programmed may cause some
high.numbered sequence lines to be lost from memory. The number of
sequence lines lost will correspond to the number of new lines inserted. If you
must add new sequence lines to a lengthy pattern, use the DELETE
command first to remove unnecessary lines and make room for the additions.
To copy sequence lines:
1.
Move the screen cursor to the SEa and THROUGH fields.
[ASEQ] 50C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
[COPY
2.
5BA
40C
4BA
30C
89AB COEF
0123
0123 4567
1234 5678
9ABC OEFO
1234
2345 6789
ABCO EF01
2345
3456 789A
BCOE F012
3456
4567 89AB
4567
COEF 0123
5678
5678 9ABC
OEFO 1234
EF01 2345
6789
6789 ABCO
789A BCOE
F012 3456
789A
89AB COEF
0123 4567
89AB
1234 5678
9ABC OEFO
9ABC
ABCO EF01
2345 6789
ABCO
3456 789A
BCOE F012
eCDE
COEF 0123
4567 89AB
COEF
OEFO 1234
5678 9ABC
DEFO
EF01 2345
6789 ABCD
EF01
]:[SEQ][
] THROUGH [
] BEFORE
3BA
4567
5678
6789
789A
89AB
9ABC
ABCO
BCOE
COEF
OEFO
EF01
F012
0123
1234
2345
SEa [
S
I
89A
9AB
ABC
BCD
COE
OEF
EFO
F01
012
123
234
345
456
567
678
BCD
COE
OEF
EFO
F01
012
123
234
345
456
567
678
789
89A
gAB
]
Use the data entry keys to enter the starting and ending sequences as well as a destination sequence. For example, to make a copy of sequence lines 0 through 4 and to place them before
sequence line 5:
[COpy
] : [SEa] [
01 THROUGH [
3·98
4] BEFORE SEa [
5]
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
3.
Press the EXECUTE key to initiate the COpy
SE~
command.
The DAS will display the message "COPIED SE~ 0 THROUGH 4 BEFORE SE~ 5" in the
message field at the top of the display when the operation is complete. The DAS will also blank
the SE~ and THROUGH fields to prevent accidental operation.
[ASEO] 5DC
0123
0
1
1234
2345
2
3456
3
4
4567
0123
5
1234
6
7
2345
8
3456
4567
9
5678
10
11
6789
12
789A
13
89AB
14
9ABC
[COPY ]:(SEO]
5BA
4DC
4BA
4567
89AB CDEF
9ABC DEFO
5678
6789
ABCD EF01
789A
BCDE F012
89AB
CDEF 0123
4567
89AB CDEF
5678
9ABC DEFO
6789
ABCD EF01
789A
BCDE F012
89AB
CDEF 0123
9ABC
DEFO 1234
EF01 2345
ABCD
F012 3456
BCDE
CDEF
0123 4567
1234 5678
DEFO
[ ] THROUGH [ ] BEFORE
3DC
0123
1234
2345
3456
4567
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
SE~ [ ]
3BA
4567
5678
6789
789A
89AB
4567
5678
6789
789A
89AB
9ABC
ABCD
BCDE
CDEF
DEFO
S
89A
9AB
ABC
BCD
CDE
89A
9AB
'ABC
BCD
CDE
DEF
EFO
F01
012
123
I
BCD
CDE
DEF
EFO
F01
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
POD The POD sub-command is used to duplicate a pattern entered into memory for one pod and
put a copy of the same pattern into memory for another pod. If there is already data in the
destination pod, it will be discarded when the new pattern is copied into that pod's memory.
To copy a data pattern from one pod to another:
1.
Move the screen cursor to the COPY: POD field.
[ASEO]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
[ COpy
2.
SOC
5BA
0123 4567
1234 5678
2345 6789
3456 789A
4567 89AB
5678 9ABC
6789 ABCD
789A BCDE
89AB CDEF
9ABC DEFO
ABCD EF01
BCDE F012
CDEF 0123
DEFO 1234
EF01 2345
] :[ POD ] [
4DC
89AB
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
3456
4567
5678
6789
] TO {
4BA
CDEF
DEFO
EF01
F012
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCO
3DC
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCD
BCDE
CDEF
OEFO
EF01
3BA
4567
5678
6789
789A
89AB
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
S
89A
9AB
ABC
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
I
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
789
89A
9AB
]
Use the data entry keys to enter a pod 1.0. For example, to make a copy of pod 58 and send it
to pod 30.
[COPY]: [POD] [5BJ TO [30]
3·99
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
3.
Press the EXECUTE key to start COpy POD operation.
The DAS will display the message ·COPIED POD 5B TO 3D" in the message field on the
second line of the display when the COPY POD operation has been completed. The DAS will
also blank the source and destination fields to prevent accidental operation.
[ASEQ]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
[ COpy
5BA
4DC
SOC
89AB
0123 4567
1234 5678
9ABC
2345 6789
ABCD
3456 789A
BCDE
4567 89AB
CDEF
5678 9ABC
DEFO
EF01
6789 ABCD
789A BCDE
F012
89AB CDEF
0123
1234
9ABC DEFO
ABCD EF01
2345
BCDE F012
3456
4567
CDEF 0123
DEFO 1234
5678
EF01 2345
6789
] : [POD] [ ] TO [ ]
4BA
CDEF
DEFO
EF01
F012
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCD
3DC
4523
5634
6745
7856
8967
9A78
AB89
BC9A
CDAB
DEBC
EFCD
FODE
01EF
12FO
2301
38A
4567
5678
6789
789A
89AB
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
S
89A
9AB
ABC
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
I
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
789
89A
9AB
DELETE Use the DELETE command to erase sequence lines within the Program Run sub-menu.
When the DELETE command is executed, all sequence lines between the given starting and ending
sequence lines (inclusive) are deleted. The remaining sequence line numbers are automatically
updated.
NOTlE
When sequence lines are removed by the DELETE command, a corresponding number of new sequence lines containing default values are created at
the end of the pattern generator's memory. These new sequence lines will be
inserted after the last sequence line that contains programming data in order
to maintain a total of 2048 sequence lines (ASEO) or 1023 lines (RSEO) for
both Page A and Page B.
NOTE
If you attempt to use the DELETE function across page boundries when the
91S32s are set to FOLLOWS 91S16 mode. only the lines within the current
page will be deleted; you will ha ve to change to the other page and repea t the
DELETE operation to remove the rest of the sequence lines.
To delete one or more sequence lines:
1.
Move the screen cursor to the edit command field at the bottom of the Run sub-menu screen.
Press the SELECT key until DELETE appears in the field.
3·100
Operating Instructions
DAS 9100 Series 91S16·91S32 Service
2.
Move the screen cursor to the SEQ field.
[ASEQ] 5DC
5BA
0123 4567
0
1
1234 5678
2
2345 678S
3456 78SA
3
4
4567 8SAB
SABC
5678
5
6
678S ABCD
7
789A BCDE
8
89AB CDEF
SABC DEFO
S
10
ABCD EF01
11
BCDE F012
CDEF 0123
12
13
DEFO 1234
14
EF01 2345
[DELETE] : [SEQ] [
3.
4DC
4BA
8SAB CDEF
SABC DEFO
ABCD EF01
BCDE F012
COEF 0123
DEFO 1234
EF01 2345
F012 3456
0123 4567
1234 5678
2345 6789
3456 789A
4567 89AB
5678 SABC
6789 ABCD
] THROUGH [
3DC
0123
1234
2345
3456
4567
5678
678S
789A
89AB
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
3BA
4567
5678
678S
789A
8SAB
SABC
ABCD
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
S
8SA
SAB
ABC
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
I
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
78S
89A
9AB
Use the data entry keys to enter the sequence numbers of the first and last lines you wish to delete. If you only wish to delete one line, enter that sequence number in both fields. For example,
to erase sequence lines between SEQ 3 and 5.
[DELETE ]: SEQ [ 3J THROUGH [ 5]
4.
Press the EXECUTE key to start the DELETE operation. The DAS will display the message
"DELETED SEQ 3 THROUGH 5" when the DELETE operation has been completed. The DAS
will also update the remaining sequence line numbers, and blank the SEQ and THROUGH fields
to prevent accidental operations.
[ASEQ] 5DC
5BA
0123 4567
0
1
1234 5678
2
2345 6789
6789 ABCD
3
4
789A BCDE
5
89AB CDEF
9ABC DEFO
6
7
ABCD EF01
BCDE F012
8
CDEF 0123
S
10
DEFO 1234
11
EF01 2345
12
F012 3456
13
0123 4567
14
1234 5678
[DELETE] : [SEQ] [
4BA
4DC
8SAB CDEF
SABC DEFO
ABCD EF01
EF01 2345
F012 3456
0123 4567
1234 5678
2345 6789
3456 789A
4567 89AB
5678 9ABC
6789 ABCD
789A BCDE
89AB CDEF
9ABC DEFO
J THROUGH [
3DC
0123
1234
2345
6789
789A
8SAB
9ABC
ABCD
BCOE
CDEF
DEFO
EF01
F012
0123
1234
3BA
4567
5678
6789
ABCD
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
3456
4567
5678
S
89A
9AB
ABC
EFO
F01
012
123
234
345
456
567
678
789
89A
SAB
I
BCD
CDE
DEF
123
234
345
456
567
678
789
89A
9AB
ABC
BCD
CDE
)
DISPLAY Use the DISPLAY command to select the display radix for the vector data, S (Strobe),
and I (Internal Inhibit) fields. This command is designed to make it easier for you to read the values
programmed into these fields, or to remove them from the display if they are not being used.
3-101
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
NOTE
Changing the radix of several fields when there are several 91 532s installed
may cause some data columns to disappear from the display. These data
columns can still be viewed by using the right arrow (-) scroll key to shift the
display to the right.
To remove or change the radix of the DATA, S, and I fields:
1.
Move the screen cursor to the field you wish to change.
5BA
4DC
4BA
[ASEQ] 5DC
0123 4567
89AB CDEF
0
1
1234 5678
9ABC DEFO
2
2345 6789
ABCD EF01
3456 789A
BCDE F012
3
4
4567 89AB
CDEF 0123
5678 9ABC
DEFO 1234
5
6789 ABCD
EF01 2345
6
7
789A BCDE
F012 3456
89AB CDEF
0123 4567
8
1234 5678
9
9ASC DEFO
10
ABCD EF01
2345 6789
11
BCDE F012
3456 789A
4567 89AB
12
CDEF 0123
DEFO 1234
5678 9ABC
13
14
EF01 2345
6789 ABCD
[ DISPLAY ] : 5DC [HEX] 5BA [HEX] 4DC
S [HEX] I [HEX]
2.
3DC
3BA
0123 4567
1234 5678
2345 6789
3456 789A
4567 89AB
5678 9ABC
6789 ABCD
789A BCDE
89AS CDEF
9ABC DEFO
ABCD EF01
BCDE F012
CDEF 0123
DEFO 1234
EF01 2345
[HEX] 4BA [HEX]
I
S
89A
BCD
CDE
9AB
DEF
ABC
BCD
EFO
F01
CDE
DEF
012
EFO
123
F01
234
012
345
456
123
234
567
345
678
456
789
567
89A
678
9AB
3DC [HEX] 3BA [HEX]
Press the SELECT key to change the radix or to turn off the field. For example, to change the
radix for the 4DC column to OCT (Octal) and to change the I (Internal Inhibit) field to BIN (Binary) and to turn off the S (Strobe) field:
[ DISPLAY I : 5DC [HEX] 5BA [HEX] 4DC [OCT] 4BA [HEX] 3DC [HEX] 3SA [HEX]
S [OFF] I (BIN]
The DAS will then change the display of the 4DC, I, and S fields as follows:
[ASEQ] 5DC
4DC
3BA
5BA
4BA
3DC
89AB CDEF
0123 4567
0123 4567
0
1234 5678
1234 5678
1
9ABC DEFO
2345 6789
ABCD EF01
2345 6789
2
3456 789A
3456 789A
BCDE F012
3
4
4567 89AB
4567 89AB
CDEF 0123
5678 9ABC
5
5678 9ABC
DEFO 1234
6789 ABCD
EF01 2345
6789 ABCD
6
7
F012 3456
789A BCDE
789A BCDE
89AB CDEF
8
89AB CDEF
0123 4567
9ABC DEFO
1234 5678
9ASC DEFO
9
10
2345 6789
ABCD EF01
ABCD EF01
11
3456 789A
BCDE F012
BCDE F012
4567 89AB
12
CDEF 0123
CDEF 0123
13
DEFO 1234
5678 9ABC
DEFO 1234
14
EF01 2345
6789 ABCD
EF01 2345
[DISPLAY] : SOC [HEX] 5BA [HEX] 4DC [OCT) 4BA [HEXC] 3DC
S [OFF] I [BIN]
3-102
I
101111001101
110011011110
110111101111
111011110000
111100000001
000000010010
000100100011
001000110100
0011010000101
01000101011C1
010101100111
011001111000
011110001001
100010011010
100110101011
[HEX] 3BA [HEX]
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
FILL The FILL command is used to automatically fill in the values of the #DC (PODs 0 and C
data). #BA (PODs B and A data). S (Strobe). and I (Internal Inhibit) fields with some constant values. For instance. if you knew you wanted all the sequence lines from line 20 through line 30 to have
the same data value for POD A, you could use the FILL command to automatically enter that value
in each data field instead of having to enter the value for each line individually.
You might use this command to change all the default values in the S (Strobe) field from Os to 1s.
For large scale data value changes, see the CONVERSION: CONVERT Table Build sub-menu
discription earlier in this section.
The FILL command provides editing fields to mOdify each of the data, S, and I columns in the Program: Run sub-menu. The replacement value for each column can be specified individually. You can
choose to modify the value in all columns in one operation, or choose to modify just one or two columns at a time. Enter a DON'T CARE (X) into the FILL command fields for the columns you do not
want to modify.
To use the FILL command:
1.
Select the FILL command by pressing the SELECT key while the cursor is in the edit command
field at the bottom of the DAS display.
2.
Move the screen cursor to the SEa field:
4DC
[ASEa] 5DC
5BA
89AB
0123 4567
0
1
1234 5678
9ABC
2345 6789
ABCD
2
3456 789A
BCDE
3
4
4567 89AB
CDEF
DEFO
5678 9ABC
5
6789 ABCD
EF01
6
7
789A BCDE
F012
89AB CDEF
0123
8
1234
9ABC DEFO
9
EF01
2345
10
ABCD
11
3456
BCDE F012
12
CDEF 0123
4567
5678
13
DEFO 1234
14
EF01 2345
6789
[FILL] : SEa [ ] THROUGH [ ]
[XXXX XXXX XXXX XXXX XXXX
3.
4BA
CDEF
DEFO
EF01
F012
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCD
3DC
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
3BA
4567
5678
6789
789A
89AB
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
S
89A
9AB
ABC
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
I
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
789
89A
9AB
XXXX] [XXX] [XXX]
Use the data entry keys to enter the starting and ending sequence numbers. Then move the
cursor to the appropriate field and enter the pattern you wish to place in all the corresponding
fields within that sequence range. For example, to fill SEa lines 1 through 4 with "XXXX OAOA
XXXX XXX X XXXX XXXX OCO 111".
[FILL] : SEa [ 1] THROUGH [ 4]
[XXXX OAOA XXX X XXXX XXXX XXXX] (OCO] [111]
3-103
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
4.
Press the EXECUTE key to start the FILL operation. The DAS will display the message
"FILLED SEa 1 THROUGH 4" on the second line of the display when the FILL operation has
been completed. The DAS will also blank the SEa and THROUGH fields, but not the pattern
fields.
[ASEa] 5DC
5BA
0123 4567
1234 OAOA
2345 OAOA
3456 OAOA
4567 OAOA
5678 9ABC
6789 ABCD
789A BCDE
89AB CDEF
9ABC DEFO
ABCD EF01
BCOE F012
COEF 0123
DEFO 1234
EF01
2345
] : SEa [
[XXXX OAOA XXXX XXXX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
[FILL
4DC
4BA
30C
89AB CDEF
0123
9ABC DEFO
1234
ABCD EF01
2345
BCDE F012
3456
CDEF 0123
4567
DEFO 1234
5678
EF01
2345
6789
F012 3456
789A
- 89AB
0123 4567
1234 5678
9ABC
ABCD
2345
6789
3456 789A
BCDE
4567
89AB
CDEF
DEFO
5678
9ABC
EF01
6789 ABeD
] THROUGH [
]
XXXX XXXX] [OCO] [111]
3BA
4567
5678
6789
789A
89AB
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
S
89A
OCO
OCO
OCO
OCO
DEF
EFO
F01
012
123
234
345
456
567
678
BCD
111
111
111
111
012
123
234
345
456
567
678
789
89A
9AB
INSERT Use the INSERT command to insert additional sequence lines into the Program: Run
sub-menu. The number of additional lines specified in the LlNE(S) field is inserted just before the
destination sequence line. The SEa numbers for all the sequence lines are then updated. Newly inserted sequence lines always contain default values.
NOTE
Adding sequence lines to a full memory page can cause existing sequence
lines to be lost at the page boundries. If you add sequence lines between
SEQ 0 and 1023, you may lose sequence lines at SEQ 1023. If you add
sequence lines between SEQ 1024 and 2047, you may lose sequence lines at
SEQ 2047. The number of sequence lines lost will correspond to the number
of new lines inserted. If you must add new sequence lines to a lengthy
pattern, use the DELETE command first to remove unnecessary lines and
make room for the new lines.
To insert sequence lines:
1.
Select the INSERT command by pressing the SELECT key while the cursor is in the edit
command field at the bottom of the Program Run sub-menu.
3-104
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
2. Move the screen cursor to the LlNE(S) field.
[ASEQ] 50C
a
0123
1
1234
2
2345
3
3456
4
4567
5
5678
6789
6
7
789A
89AB
8
9
9ABC
10
ABCD
11
BCDE
12
CDEF
13
DEFO
14
EF01
[INSERT] : [
5BA
40C
4BA
4567
89AB CoEF
5678
9ABC DEFO
6789
ABCo EF01
789A
BCoE F012
89AB
CoEF 0123
9ABC
DEFO 1234
ABCo
EF01 2345
BCDE
F012 3456
CDEF
0123 4567
DEFO
1234 5678
EF01
2345 6789
F012
3456 789A
0123
4567 89AB
1234
5678 9ABC
2345
6789 ABCD
1 LlNE(S) BEFORE SEQ [
30C
3BA
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
4567
5678
6789
789A
89AB
9ABC
ABCo
BCoE
CDEF
DEFO
EF01
F012
0123
1234
2345
S
89A
9AB
ABC
BCD
CoE
DEF
EFO
F01
012
123
234
345
456
567
678
BCD
CoE
oEF
EFO
F01
012
123
234
345
456
567
678
789
89A
9AB
]
Use the data entry keys to enter the number of lines you wish to add. Enter the sequence number where you want them to be inserted. For example, to insert 3 lines before SEQ 2:
[INSERT] : [ 3] LlNE(S) BEFORE SEQ [ 2]
3. Press the EXECUTE key to start the INSERT operation.
The DAS will display the message "INSERTED 3 LlNE(S) BEFORE SEQ 2" in the message
field when the insert operation has been completed. The oAS will also update the remaining se·
quence numbers, and blank the LlNE(S) and SEQ fields to prevent accidental insertions.
[ASEQ] 5DC
a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0123
1234
0000
0000
0000
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCD
BCDE
5BA
4DC
4BA
3DC
3BA
4567
5678
0000
0000
0000
6789
789A
89AB
9ABC
ABCo
BCDE
CDEF
DEFO
EF01
F012
89AB
9ABC
0000
0000
0000
ABCD
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
3456
CoEF
DEFO
0000
0000
0000
EF01
F012
0123
1234
2345
3456
4567
5678
6789
789A
0123
1234
0000
0000
0000
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCD
BCoE
4567
5678
0000
0000
0000
6789
789A
89AB
9ABC
ABCD
BCoE
CoEF
DEFO
EF01
F012
[INSERT] : [ 1 LlNE(S) BEFORE SEQ [ 1
3-105
S
89A
9AB
000
000
000
ABC
BCD
CDE
DEF
EFO
F01
012
123
234
345
BCD
CDE
000
000
000
DEF
EFO
F01
012
123
234
345
456
567
678
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
MODIFY The MODIFY command uses logical operators to manipulate data already programmed
in the Program Run sub-menu. Three logical operators are available: AND, OR, and XOR (exclusive
OR). Any programmable numeric column in the Run sub-menu can be modified by using these
operators. For example, you can modify one or both of the data fields, the S (Strobe), and the I (Internallnhibit) field, or any combination of the above. You can also limit the modification to a range of
sequence numbers.
By ANDing a particular column with 0, you can modify aU the data in that column to 0'5. (Any number ANDed with 0 equals 0.) By ORing a column with a 1, you can set all the bits in that column to 1.
(Any number ORed with a 1 equals 1.) By XORing (exclusive OR) any pattern with a 1, the bit pattern in that field is inverted. (In other words, all FFs he. would be changed to OOs, and all 11 s he, become EEs.)
Here are reminder truth tables for the AND, OR, and XOR operations:
A OR B
A AND B
A XOR B
A
B
A AND B
A
B
A OR B
A
B
A XOR B
0
0
1
1
0
1
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
To modify the pattern fields.
1.
Press the SELECT key when the screen cursor is in the edit command field at the bottom of the
Run sub-menu until the MODIFY command is displayed.
2.
Move the screen cursor to the field immediately to the right of MODIFY and press the SELECT
key until the desired logical operator is displayed. Logical operators are displayed in this order:
AND, OR, XOR
[ASEQ] 5DC
5BA
4DC
4BA
3DC
3BA
4567
0123
4567
89AB CDEF
0123
0
1
1234 5678
9ABC DEFO
1234 5678
2
2345
6789
ABCD EF01
2345
6789
3456 789A
3456
789A
3
BCDE F012
4567 89AB
4567
89AB
4
CDEF 0123
5678 9ABC
5
5678 9ABC
DEFO 1234
6789
ABCD
EF01
2345
6789
ABCD
6
7
789A BCDE
789A BCDE
F012 3456
89AB CDEF
0123
4567
8
89AB CDEF
9ABC DEFO
1234 5678
9ABC DEFO
9
10
ABCD EF01
2345 6789
ABCD EF01
BCDE F012
11
BCDE F012
3456 789A
12
CDEF 0123
4567 89AB
CDEF 0123
DEFO 1234
13
DEFO 1234
5678 9ABC
14
6789 ABCD
EF01
EF01
2345
2345
[MODIFY I : LOGICAL (AND] SEQ [ I THROUGH [ I BEFORE
(XXXX XXXX XXXX XXXX XXXX XXXXI (XXXX] (XXX]
3·106
S
89A
9AB
ABC
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
SEQ [ ]
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
789
89A
9AB
Operating Instructions
CAS 9100 Series 91516·91532 Service
3.
Press the SELECT key until the desired operator appears in the field. For example, XOR.
[MODIFY] : LOGICAL [XOR] SEa [ ] THROUGH [ ]
[XXXX XXXX XXXX XXXX XXXX XXXX] [XXX] [XXX]
4.
Move the screen cursor to the SEa and THROUGH fields. Use the data entry keys to enter the
number of the first and last sequence lines you want to mOdify. For example, to modify
sequence lines 1 through 9, enter:
[MODIFY ] : LOGICAL [XOR] SEa [ 1] THROUGH [
[XXXX XXXX XXXX XXXX XXXX XXXX] [XXX] [XXX]
5.
9]
Move the screen cursor down to the pattern line and enter the pattern you wish to use as a
modifier. For example, to invert all the Pod 3B and 3A data patterns, select XOR as the logical
operator and enter FFFFhe, in the column A field. (Fields containing X are not affected by the
MODIFY command.)
[MODIFY] : LOGICAL [XOR] SEa [ 1] THROUGH [ 9]
[XXXX XXXX XXXX XXXX XXXX FFFF] [XXX] [XXX]
6.
Press the EXECUTE key to start the MODIFY operation. The DAS will display the message
"MODIFIED SEa 1 THROUGH 9" in the message field atthe top left·hand corner of the display.
The DAS will also blank the SEa and THROUGH fields to prevent accidental operation.
[ASEa] 5DC
5BA
4DC
4BA
3DC
3BA
0123 4567
0
89AB CDEF
0123 4567
1
1234 5678
9ABC DEFO
1234 A987
2345 6789
2
ABCD EF01
2345 9876
3456 8765
3456 789A
3
BCDE F012
4
4567 89AB
CDEF 0123
4567 7654
5678 9ABC
DEFO 1234
5678 6543
5
6789 ABCD
6
EF01 2345
6789 5432
7
789A BCDE
F012 3456
789A 4321
0123 4567
89AB 3210
89AB CDEF
8
9ABC DEFO
9
1234 5678
9ABC 210F
10
ABCD EF01
2345 6789
ABCD EF01
11
BCDE F012
3456 789A
BCDE F012
12
CDEF 0123
4567 89AB
CDEF 0123
DEFO 1234
13
9ABC
DEFO 1234
5678
14
EF01 2345
EF01 2345
6789 ABCD
[MODIFY] : LOGICAL [XOR] SEa [ ] THROUGH [ ]
[XXXX XXXX XXXX XXXX XXXX FFFF] [XXX] [XXX]
S
89A
9AB
ABC
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
789
89A
9AB
MOVE Use the MOVE command to move some block of sequence lines within a program to
another location within that same program. When MOVE is executed, all the sequence lines
specified are moved to a location just before the given destination sequence. The sequence
numbers are then automatically updated. Labels, data, and instructions are rfiltained when
sequence lines are moved.
Using the MOVE command does not cause high.numbered program lines to be lost even if all 1022
sequence lines have been programmed.
3·107
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
NOTE
When 91532 Modules are used in FOLLOWS 91516 mode, you cannot
move sequence lines from one page of memory to the other (e.g., Page A to
Page B).
To MOVE a block of sequence lines from one location to another:
1.
Select the MOVE command by pressing the SELECT key when the screen cursor is in the edit
command field at the bottom of the 91 S32 Program: Run sub-menu.
2.
Move the screen cursor to the SEa field.
4BA
30C
5BA
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCo
11
BCoE
12
CoEF
13
oEFO
14
EF01
[MOVE] : SEa
4567
89AB CoEF
0123
9ABC oEFO
1234
5678
6789
ABCo EF01
2345
BCoE F012
3456
789A
89AB
4567
CoEF 0123
9ABC
oEFO 1234
5678
ABCo
EF01 2345
6789
F012 3456
BCoE
789A
89AB
0123 4567
CoEF
oEFO
1234 5678
9ABC
EF01
2345 6789
ABCo
3456 789A
F012
BCoE
4567 89AB
0123
CoEF
1234
5678 9ABC
oEFO
EF01
2345
6789 ABCo
] THROUGH [
] BEFORE
[
0
1
2
3
4
5
6
7
8
9
10
3.
40C
[ASEa] SOC
3BA
S
4567
5678
6789
789A
89AB
9ABC
ABCo
BCoE
CoEF
oEFO
EF01
F012
0123
1234
2345
SEa [
89A
9AB
ABC
BCD
CoE
oEF
EFO
F01
012
123
234
345
456
567
678
]
BCD
CoE
oEF
EFO
F01
012
123
234
345
456
567
678
789
89A
9AB
Use the data entry keys to enter the starting, ending, and destination sequence numbers. For
example, to move sequence lines 1 through 3 and place them before sequence line 7:
[MOVE] : SEa [ 1] THROUGH [ 3] BEFORE SEa [
3·108
7]
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
4.
Press the EXECUTE key to start the MOVE operation. The DAS will display the message
"MOVED SEQ 1 THROUGH 3 BEFORE SEQ 7" on the message line. The DAS will also update
all the sequence lines and blank the SEQ, THROUGH and, BEFORE fields to prevent
accidental move operations.
[ASEQ] 50C
0
1
2
3
4
5
6
7
-8
9
10
11
12
13
14
0123
4567
5678
6789
1234
2345
3456
789A
89AB
9ABC
ABCD
BCOE
CDEF
OEFO
EF01
5BA
40C
4BA
3DC
3BA
4567
S9AB
9ABC
ABCD
5678
6789
789A
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
S9AB
CDEF
DEFO
EF01
9ABC
ABCD
BCDE
F012
0123
1234
2345
3456
4567
5678
6789
CDEF
0123
1234
2345
DEFO
EF01
F012
3456
4567
5678
6789
789A
89AB
9ABC
ABCD
0123
4567
5678
6789
1234
2345
3456
789A
S9AB
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
4567
S9AB
9ABC
ABCD
5678
6789
789A
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
S
S9A
CDE
DEF
EFO
9AB
ABC
BCD
F01
012
123
234
345
456
567
678
BCD
F01
012
123
CDE
DEF
EFO
234
345
456
567
678
789
89A
9AB
[MOVE] : SEQ [ ] THROUGH [ ] BEFORE SEQ [ ]
Search. Use the SEARCH command to locate some specific entry within the body of the Program
Run sub-menu. The entry may be a particular data pattern, a strobe value, or an internal inhibit
value.
The SEARCH command allows you to specify the type of entry you are going to search for, and
specify a sequence range for the search. When executed, the SEARCH command compares all entries of the same type against the target string within the range of sequence lines you have
specified. It will then place the screen cursor on the first sequence line containing that string. and
display the total number of lines within the specified range that contain the target string. (The
number of occurrences appears in the bottom right-hand corner of the display.)
The data entry keys can be used to select the second, or third, etc. sequence line containing the target string when the screen cursor is in the [
]/ # : SEARCHED field. (Instructions for using this
field are included in the following paragraphs.)
The SEARCH command has a sub-field used to specify the pattern you want to search for. Fields
containing X's (Don't Cares) match all data patterns.
3-109
Operating Instructions
DA8 9100 8eries 91816-91832 Service
To search a pattern:
1.
Select the SEARCH command by moving the screen cursor to the edit command field at the
bottom of the Program Run sub-menu and pressing the SELECT key.
2.
Select the type of pattern you are going to search for by moving the screen cursor to the field
immediately to the right of the SEARCH command.
[ASEa] 50C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ASC
ABCO
BCDE
COEF
OEFO
EF01
5BA
40C
4BA
30C
3BA
4567
5678
6789
789A
89AB
9ABC
ABCD
BCOE
COEF
OEFO
EF01
F012
0123
1234
2345
89AB
9ABe
ABCO
BCDE
COEF
OEFO
EF01
F012
0123
1234
2345
3456
4567
5678
6789
COEF
DEFO
EF01
F012
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCO
0123
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCO
BCOE
COEF
OEFO
EF01
4567
5678
6789
789A
89AB
9ABC
ABCD
BCOE
COEF
OEFO
EF01
F012
0123
1234
2345
S
89A
9AB
ABC
BCD
COE
OEF
EFO
F01
012
123
234
345
456
567
678
BCD
CDE
DEF
EFO
F01
012
123
234
345
456
567
678
789
89A
9AB
] THROUGH [
]
[SEARCH 1 : SEa [
[XXXX XXXX XXXX XXXX XXXX XXXX] [XXX] [XXX]
3.
Move the screen cursor to the SEa and THROUGH fields and enter the starting and ending sequence numbers for the block of program you wish to search. For example, enter SEa 0 and
THROUGH 10, to search for a pattern programmed in lines 0 through 10, inclusive. Note: the
larger the search range you specify, the longer it takes for the edit operation to be completed,
and the greater the likelihood you will locate data you are not interested in.
4.
Move the screen cursor to the PATIERN sub-fields and use the data entry keys to enter the
pattern you wish to find. For example, to search for a pattern between SEa a and 10:
[SEARCH
1 : SEa
[ 0] THROUGH [ 10]
[XXXX XXXX 1234 XXXX XXXX XXXX] [123] [XXX]
3·110
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
5.
Press the EXECUTE key to start the SEARCH operation. The DAS will display the message,
"< [
1]1
1: SEARCH ED >" in the bottom right-hand corner of the display. The first
number in this message indicates that the screen cursor has been placed on the line containing
the first instance of the target pattern. The number following the slash tells you how many lines
contain the target pattern within the range you specified for the search.
[ASEa]
5
6
7
8
[ 9]
10
11
12
13
14
5DC
5678
6789
789A
89AB
[9ABC
ABCD
BCDE
CDEF
DEFO
EF01
5BA
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
F012
0123
1234
2345
4DC
DEFO
EF01
F012
0123
1234
2345
3456
4567
5678
6789
4BA
1234
2345
3456
4567
5678
6789
789A
89AB
9ABC
ABCD
3DC
5678
6789
789A
89AB
9ABC
ABCD
BCDE
CDEF
DEFO
EF01
3BA
9ABC
ABCD
BCDE
CDEF
DEFO]
EF01
F012
0123
1234
2345
S
DEF
EFO
F01
012
[123]
234
345
456
567
678
I
012
123
234
345
[456]
567
678
789
89A
9AB
[SEARCH] : SEa [ 0] THROUGH [ 10]
[XXXX XXXX 1234 XXXX XXXX XXXX] [123J [XXX]
For instance, if you had searched for 0000 in a block of text where 15 lines contained the pattern 0000, the message would read: "<[
1]1 15: SEARCHED>". If you wanted to see
the 14th occurrence of the target pattern, you could move the screen cursor to the highlighted
field in the first part of this message and type in 14. When you pressed the EXECUTE key, the
screen cursor would be placed on the line containing the 14th occurrence of the target pattern,
and the message field would read: "<[ 14]1 15: SEARCHED>".
3-111
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
91S16 PROGRAM: TRACE AND STEP MODE SUB-MENUS
NOTE
The 91516 Program Trace and 5tep sub-menus appear only when there is a
91516 installed in the DA5.
The following paragraphs describe how you can use the 91 S 16 Trace and Step modes to monitor
program execution and pattern output. 80th Step and Trace modes cause the pattern generator to
output data much more slowly than during normal operation. Trace mode causes the pattern
generator to output data at a rate slow enough for you to monitor key parameters, while Step executes a single line of program each time you press the START PAT GEN key.
80th the Trace and Step sub-menus display CLOCK (the number of sequence lines executed since
you pressed START), SEa (the sequence line currently being executed), #8 and #A (data output
from pods 8 and A), S (strobe), register and control information.
Two features distinguish Trace mode from Step mode. Trace mode outputs the test vectors as fast
as the DAS can but the corresponding data on the screen. Trace mode also allows you to set a
breakpoint to automatically stop program execution after executing some specified program line. In
Step mode, a test vector is output every time the START PAT GEN key is pressed; no breakpoint is
needed since you control every output manually.
Figures 24 and 25 illustrate the 91 S 16 Pattern Generator Trace and Step Mode sub-menus. Refer
to the numbered callouts when reading the following paragraphs. These numbers serve as visual
references and do not imply sequence of use.
NOTE
In the following discussion, the 91516 is assumed to be installed in DA5
slot 6.
1 PATTERN GENERATOR PROGRAM Field
Use this field (directly to the right of the menu title) to select either the 91 S16 or the 91 S32 submenu display. The 91 S 16 sub-menu is the default menu.
2 MODE Field
Use the MODE field to select the pattern generator's operating mode. The 91 S16 has three modes
of operation: Run. Trace, and Step. When operating in the Run mode. the pattern generator
outputs data at the clock rate selected in the CONFIGURATION sub-menu. When in Trace mode,
the pattern generator runs on a much slower clock of several hundred miliseconds. slow enough for
you to see key trends in program execution. In Step mode. pattern execution is clocked each time
you press the START PAT GEN key. Trace and Step modes assist you in debugging your pattern
generation programs.
.
The MODE field defaults to Run mode.
3-112
Operating Instructions
CA5 9100 5eries 91516-91532 5ervice
2
1
3
4
5
5397-24
Figure 3-17. 91516 Program: Trace sub-menu.
2
1
3
5
5397-25
Figure 3-18. 91516 Program: 5tep sub-menu.
Figures 3-17 and 3-18 illustrate the 91 S 16 Pattern Generator Trace and Step Mode sUb-menus.
Refer to the numbered callouts when reading the following paragraphs. These numbers serve as visual references and do not imply sequence of use.
3-113
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
TRACE The Trace mode allows continuous execution of the pattern generator program while
allowing you to monitor the execution on the Trace sub-menu display. Program execution is
monitored by a readback function in the 91 S16. This function allows you to see how often interrupt
servicing routines are called, how many times certain loops are executed, where interrupt routines
are activated, and the general branching structure of your program.
Use the START PAT GEN key to start Trace mode pattern execution. Execution stops when any
key other than the START PAT GEN key is pressed, when the pattern generator
encounters a HALT in a program sequence line, or when it reaches sequence line 1023. When the
pattern generator has been stopped for any reason, the DAS will display ·PATIERN GENERATOR
STOPPED" in the message field at the top left-hand corner of the display. If you press the START
PAT GEN key after execution has been stopped, execution will resume at the sequence line
specified in the START SEQ field of the Trace sub-menu.
NOTE
If any key other than the PAT GEN key is pressed during Trace
operation, the normal function of that key will be ignored and the pattern
generator will stop outputting data.
The pattern generator also stops execution when it encounters a breakpoint specified in the Trace
sub-menu BREAKPOINT field. The breakpoint is specified as a sequence line number. The pattern
generator will output data and perform any instruction listed in the breakpoint line before stopping.
This feature allows you to output only a narrow range of program lines by specifying the starting sequence in the START SEQ field, and specifying the ending sequence with the BREAKPOINT field.
Following a breakpoint, you can resume pattern output on the next sequence line by pressing the
START PAT GEN key. Detailed instructions for using this field are given later in this section.
STEP The Step mode SUb-menu performs the same functions as the Trace mode sub-menu but it
allows you to have more control over data execution. Program execution proceeds only as fast as
you press the START PAT GEN key. There is no breakpoint field for the Step sub-menu because
you control every step of program execution manually. When the pattern generator executes a line
containing the HALT instruction, or when it reaches the end of the pattern generator memory, the
DAS will display the message ·PATTERN GENERATOR STOPPED" in the upper-left corner of the
display. If you press the START PAT GEN key again, the pattern generator will start execution at
the first sequence line listed in the START SEQ: field.
NOTE
Use the INCR and DECR keys instead of the SELECT key to change
between Step and Trace modes; otherwise you will lose the current display.
To change the 91516 MODE of operation:
1.
Move the screen cursor to the MODE field in the upper right-hand corner of the display.
MODE: [ RUN]
2.
Press the SELECT, INCR, or DECR key until the desired mode appears in this field. The DAS
will the display the MODE field values in this order:
[ RUN]
[TRACE]
[STEP]
3-114
Operating Instructions
CAS 9100 Series 91516-91532 Service
3 START SEQ Field
Use the START SEQ field to set the first sequence number to be executed when the pattern
generator begins operation. (You can start the pattern generator by pressing either the START
PAT GEN key or the START SYSTEM key.) The START SEQ value may be any number between 0
and 1023 if no service interrupt call has been programmed, and between 0 and 1022 if the service
interrupt call has been programmed.
To enter a beginning sequence number in the START SEa field:
1.
Move the screen cursor to the START SEQ field.
START SEQ: [
2.
0]
Use the data entry keys to enter the sequence number. For example:
START SEQ: [ 500]
NOTE
If the IRQ CALL instruction has been selected in the CONFIGURATION submenu after you have programmed the START SEQ field to 1023, the START
SEQ field will be reset to.O. (Valid SEQ numbers are 0-1022 when IRQ CALL
is programmed.)
4 BREAKPOINT Field
NOTE
The BREAKPOINT field is only available in the Trace mode sub-menu. Step
mode is always manually controlled and thus does not need a breakpoint.
Use this field to set a breakpoint at any sequence line where pattern generator execution needs to
be suspended. You can only set one breakpoint at a time. When a breakpoint sequence number has
been set in the BREAKPOINT field, the pattern generator will execute all preceding sequences,
including the sequence line containing the breakpoint, and then stop. The BREAKPOINT field
default value is OFF.
To set a BREAKPOINT:
1.
Select the Trace Mode sub-menu. Move the screen cursor to the BREAKPOINT field in the upper right.hand corner of the display.
MODE: [TRACE]
START SEQ: [
0]
BREAKPOINT: [ OFF]
2.
Press the SELECT key to turn on the BREAKPOINT function. The sequence number field will
appear below the BREAKPOINT field.
MODE: [TRACE]
START SEQ: [
0]
BREAKPOINT: [ ON 1
[1023]
3-115
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
3.
Move the screen cursor to the sequence number field and use the data entry keys to enter the
number of the sequence line where you want the breakpoint to occur. For example, enter
sequence line 500:
MODE: [TRACE]
START SEa: [
0]
BREAKPOINT: [ ON ]
[ 500]
5 Program Display Column Headings
The Trace and Step mode sub-menus have six types of headings under which data is tabulated as
program execution is being traced. The number of clocks (sequence lines executed since START
was pressed). data patterns output, strobes. the contents of the pattern generator register(s), and
instructions programmed for each sequence line are displayed below these headings as each
program line is executed.
For example. if sequence line 100 was executed as the 115th sequence (some loop accounted for
the other 15 clock cycles), the Trace sub-menu might show this display:
CLOCK
115
SEa
100
6B 6A
FF 1A
S
1
RB
RA
00 04
CONTROL
INCR PAGE
Data is displayed line by line, and scrolls up from the bottom of the display when the screen is full.
CLOCK This heading shows the number of clocks generated since the pattern generator was
started. The clock begins counting at 0 and is reset when it reaches 9999. Because of loops. jumps.
and subroutine calls, the clock cycle does not necessarily correspond to the sequence line being
executed.
sea
This heading shows the sequence number of the program line that has just been executed. It
is the same sequence number that appears in the Run sub-menu. By tracking this number, program
flow can be thoroughly monitored.
#B and # A These headings display the pattern delivered to the P6464 probe tips. The number
relates to the slot in the DAS where the 91 S16 is installed, and the letter denotes the pod. A DON'T
CARE (X) in this field indicates that at least one of the channels in that pod has been tri-stated (assuming display in Hex). The radix for this field can be changed by using the DISPLAY command in
the 91 S 16 Run sub-menu.
S The S (strobe) heading displays the status of the strobe lines. A DON'T CARE (X) in this field indicates that at least one of the strobe lines has been tri-stated. The radix for this field can be
changed by using the DISPLAY command in the 91S16 Run sub-menu.
3-116
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
RB, RA These headings display the contents of the 91516 pattern generator's registers. RB
displays the contents of 8-bit register RB. RA displays the contents of register RA. If you have selected just one 16-bit register instead of two 8-bit registers in the 91516 Configuration sub-menu,
the heading changes to R. The radices for these fields are set by the radices of the #B and #A data
pattern fields. If the pattern generator register has been set to a single 16-bit register, the 8 most
significant bits of this display column follow the radix set for #B, and the 8 least significant bits of
this display column follow the radix set for # A.
CONTROL This heading covers the display of all CONTROL instructions when they are executed.
The two CONTROL instructions are TRIGGER and INCR PAGE (increment page). 5ee the
explanation for these commands in the 91516 Run Menu section of this manual. In brief, TRIGGER
causes a TTL-level signal to be output via a phono jack on the back of the 91 516. This signal can be
used to trigger an external test device, such as an oscilloscope. INCR PAGE is used by the 91516
to control 91 532s when a long pattern is being downloaded from a host computer or mass storage
device.
3-117
Operating Instructions
CAS 9100 Series 91516-91532 Service
91532 PROGRAM: TRACE AND STEP MODE SUB-MENUS
NOTE
The 91 S32 Program Trace and Step sub-menus appear only when there is a
91 S32 installed in the DAS.
The following paragraphs describe how you can use the 91 S32 Trace and Step modes to monitor
program execution and pattern output. Both Step and Trace modes cause the pattern generator to
output data much more slowly than during normal operation. Trace mode causes the pattern
generator to output data at a rate slow enough for you to monitor sequence flow, while Step
executes only one line of program each time you press the START PAT GEN key.
Both the Trace and Step sub-menus display CLOCK (the number of sequence lines executed since
you pressed START), SEa (the sequence line currently being executed), #DC and #BA (data
output from pods grouped in pairs), and S (strobe).
Figures 3-19 and 3-20 illustrate the 91 S32 Pattern Generator Trace and Step Mode sub-menus.
Refer to the numbered callouts when reading the following paragraphs. The numbers serve as
visual references and do not imply sequence of use.
2
1
3
5
5397-26
Figure 3-19. 91532 Trace sub-menu.
1
5
5397-27
Figure 3-20. 91532 Step sub-menu.
3-118
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
NOTE
In the following discussion, 91 S32s are assumed to be installed in DAS slots
3,4, and 5.
1 PATTERN GENERATOR PROGRAM Field
Use this field (directly to the right of the menu title) to select either the 91 S16 or the 91 S32 submenu display. The 91 S 16 sub-menu is the default menu.
To display the 91 S32 Program sub-menus, position the screen cursor in this field and press the SELECT key. To change back to the 91S16 sub-menu, press the SELECT key again.
2 MODE Field
Use the MOCE field to select the pattern generator's operating mode. The 91 S32 has three modes
of operation: Run, Trace, and Step. When operating in the Run mode, the pattern generator
outputs data at the clock rate selected in the CONFIGURATION sub-menu. When in Trace mode,
the pattern generator runs on a much slower clock of serveral hundred miliseconds, slow enough
for you to see key trends in program execution. In Step mode, pattern execution is clocked each
time you press the START PAT GEN key. Trace and Step modes are designed to assist you in debugging your pattern generation programs.
The MOCE field defaults to Run mode.
TRACE The Trace mode allows continuous execution of the pattern generator program while
allowing you to monitor the execution on the Trace sub-menu display. Program execution is
monitored via a readback function in the 91 S32. This will allow you to see how often subroutines
are called, how many times certain loops are executed, where interrupt routines are activated, and
the general branching structure of your program.
Use the START PAT GEN key to start Trace mode pattern execution. Execution will stop when any
key is pressed, or when the pattern generator reaches sequence line 2047. When the pattern
generator has been stopped for any reason, the CAS will display ·PATTERN GENERATOR
STOPPEC· in the message field at the top left-hand corner of the display. If you press the START
PAT GEN key after execution has been stopped, execution will resume at the sequence line
specified in the START SEa field of the Trace sub-menu.
STEP The Step mode sub-menu performs the same functions as Trace mode, except that only
one program line is executed for each time you press the START PAT GEN key. When the pattern
generator reaches the end of the pattern generator memory, the CAS will display the message
·PATTERN GENERATOR STOPPEC· in the upper-left comer of the display. Pressing the START
PAT GEN key again will cause the pattern generator to start execution at the first sequence line listed in the START SEa: field.
NOTE
When you change the mode field from Trace to Step, or to Run, the current
display is lost. To change between Trace and Step mode without losing the
current display, use the INCR and DECR keys instead of the SELECT key.
3-119
Operating Instructions
DAS 9100 Series 91S16-91532 Service
To change the 91 S32 MOCE of operation:
1.
Move the screen cursor to the MODE field in the upper-right comer of the display.
MODE: [ RUN]
2.
Press the SELECT, INCR, or DECR key until the desired mode appears in this field. The DAS
will the display the MODE field values in this order:
MODE: [ RUN]
MODE: [TRACE]
MODE: [STEP ]
3 PAGE: Heading
The page field indicates which page of the 91 S32's memory is being executed. In this sub-menu the
page value cannot be set; it is displayed here for reference purposes.
4 START SEa Field
Use the START SEa field to set the first sequence number to be executed when the pattern
generator begins operation. (You can start the pattern generator by pressing either the START
PAT GEN key or the START SYSTEM key.) The START SEa value may be any number between 0
and 2047 if you are programming in absolute sequence numbers (ASEa). If you are using relative
sequence numbers (RSEa). the range is Page A, 0 through 1023, or Page B. 0 through 1023. See
the 91S32 Program: Run Sub-Menu description for details concerning ASEa and RSEa numbers.
To enter a beginning sequence number in the START SEa field:
1.
Move the screen cursor to the START SEa field.
START SEa: [
2.
0]
Use the data entry keys to enter the sequence number. For example:
START SEa: [ 500]
5 Program Display Column Headings
The Trace and Step mode sub-menus have four types of headings under which data is tabulated as
program execution is being traced. The number of clocks (sequence lines executed since START
was pressed), the number of the sequence line currently being executed, the data patterns being
output via the P6464 probes, and the values programmed for each strobe are displayed below
these headings as each program line is executed.
For example, if sequence line 100 was executed as the 115th sequence (some loop controlled by a
91 S16 accounted for the other 15 clock cycles), the Trace sub-menu might show this display:
CLOCK
115
SEa
100
6DC
01 FF
6BA
1AEE
S
0
Data is shown line by line, and scrolls up from the bottom of the display when the screen is full.
3·120
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
CLOCK This heading shows the number of clocks generated since the pattern generator was
started. The clock begins counting at 0 and is reset when it reaches 9999. If you are using a 91 S16
with your 91 S32s, the clock cycle will not necessarily correspond to the sequence line being
executed because of loops. jumps, and subroutine calls. Starting the pattern generator at some
mid-point in the pattern will also cause a discrepancy between the CLOCK count and the SEa line
being displayed.
SEa This heading shows the sequence number of the program line that has just been executed. It
is the same sequence number that appears in the Run sub-menu. The SEa heading may be ASEa
or RSEa depending on how you set the SEa field in the 91 S32 Run sub-menu. By tracking the
SEa numbers. you can thoroughly monitor program flow.
#OC and #BA
These headings display the pattern delivered to the P6464 probe tips. The
number relates to the slot in the DAS where the 91 S 16 is installed. and the letter denotes the pod.
An X (DON'T CARE) in this field indicates that at least one of the channels in that pod has been tristated (assuming display in Hex). The radix for this field can be changed by using the DISPLAY
command while in the 91 S32 Run sub-menu.
S The S (strobe) heading displays the status of the strobe lines. An X (DON'T CARE) in this field
indicates that at least one of the strobe lines has been tri-stated. The radix for this field can be
changed by using the DISPLAY command in the 91 S32 Run sub-menu.
3-121
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
GPIB PROGRAMMING
In this section you will find:
• general information on using the GPIB to remotely load and run the 91516 and 91532 pattern
generator modules.
• a brief description of the capabilities and limitations of using GPIB commands with the Option
02 GPIB and RS-232 interfaces, and with the Option 06 GPIB interface.
• information on how to use the Option 06 GPIB interface to stimulate static devices (Pattern
Download For Static Devices).
• information on how to use the Option 06 GPIB interface to stimulate dynamic devices (Pattern
Download For Dynamic Devices {Keep-Alive}).
GENERAL INFORMATION
The General Purpose Interface Bus (GP1B) interface provided with DAS 9100 Series Options 02
and 06 conforms to the specifications contained in the IEEE 488-1978, Standard Digita/lnterface
for Programmable Instrumentation. This section describes GPI B operational elements only in
relation to 91S16 and 91S32 Pattern Generator modules installed in the DAS.
You can operate 91 S16 and 91 S32 pattern generator modules in the DA5 from a remote controller
by using the IEEE 488 General Purpose Interface Bus (GPIB) or the RS-232 master/slave interface
(using GPIB commands).
Remote operation requires that you write a program for your controller to operate the DAS. To
write such a program, you need to be familiar with your controller before you attempt to use the information in this section. The DAS can operate as a talker or a listener, but not as a controller in a
GPIB system.
This section assumes that you are familiar with the GPIB as implemented in DAS 9100 Series Logic
Analyzers. Refer to the Option 06: I/O Communication Interface Operator's Manual Addendum
(part of the DAS 9100 Series Operator's Manual package). The following documents may also be
useful to you:
• GPIB Application Support (Tektronix Part Number 070-2307-00)
• Standard Digital Interface for Programmable Instrumentation (IEEE 488-1978
standard). This document is published by The Institute of Electrical and Electronics Engineers, Inc. 345 East 47 Street, New York, New York 10017.
CAPABILITIES AND LJMITATIONS WHEN USING GPIB TO CONTROL THE
91516 AND 91S32
There are three methods of implementing remote operation of the 91S16 and 91S32 pattern
generator modules using GPIB commands. All three methods allow you to use a controller to load
the pattern generator's memory and start operation. However, the method of implementing the
Pattern Download From Host feature (described in the 91 S32 Configuration Sub-Menu When Used
With 91 S 16 section of this addendum) depends on whether you are using the Option 02 GPIB interface, the Option 06 GPIB interface, or the RS-232 interface.
3-122
Operating Instructions
OAS 9100 Series 91516-91532 Service
All three methods use GPIB commands, but only Option 06 GPIB has the HSPAT (High-Speed
PATtern download) command which allows you to use the Keep-Alive feature. Keep-Alive allows
you to reload one page of the 91 S32's memory while the 91 S16 continues to output vectors;
without this feature. the pattern generator briefly stops outputting vectors while the 91 S32
completes its reload operation. (When the pattern generator stops, the last vectors are frozen at
the probe tips.)
GPIB PROGRAMMING USING THE OPTION 02 GBIP AND RS-232 INTERFACES
Instructions for using the Option 02 GPIB and RS-232 interfaces are provided in the DAS 9100 Series Operator's Manual. Refer to that manual for more information.
GPIB PROGRAMMING USING THE OPTION 06 GPIB INTERFACE
This section only describes the Option 06 HSPAT command for the 91 S16 and 91 S32 pattern
generator modules. Refer to the Option 06 110 Communication Interface Addendum to the DAS
9100 Series Operator's Manual for an explanation of the GPIB system and description of other
GPIB commands.
HSPAT (High-Speed Pattern Generator) Command
(Option 06 only, GPIB only)
The HSPAT command loads the pattern generator's program and pattern directly into the 91 S16
and 91 S32 memory. This command is supported only by the GPIB interface.
NOTE
The HSPAT command used with the 91S16 and 91S32 Pattern Generator
modules is not the same HSPATcommand used with the 91P16132 Pattern
Generator modules.
HSPAT Command Format
The HSPAT command has two parts. The first part consists of the command header (HSPAT) and
its arguments. This part of the command is discussed under the paragraphs titled Command
Header Structure.
The second part of the HSPAT command consists of the binary end block containing the data to be
loaded into the pattern generator. This part of the command is discussed under the paragraphs titled Data Block Stucture.
The command format is:
HSPAT ,.(EOM)
@BC16
The DAS screen is turned off during data transfer. The pattern generator will stop when the HSPAT
command is executed, unless the pattern generator is running in Keep-Alive mode.
3-123
Operating Instructions
CAS 9100 Series 91516·91532 Service
Command Header Structure
The command header and its arguments teU the OAS which slot should receive the data. the
sequence line where the data should start, and the total number of sequence lines in this transfer.
The command header format is:
HSPAT , , (EOM)
is an ASCII integer representing the slot number of the pattern generator module you wish
to reload.
is an ASCII integer representing the hardware address where your program begins
loading. For the 91 S16, this number must be between 1 and 1024; for the 91 S32. this number must
be between 1 and 2048.
is and ASCII integer representing the total number of lines being downloaded in this
transfer. For the 91 S16, this number must be between 0 and 1023; for the 91 S32. this number must
be between 0 and 2047.
(EOM) is the end of message indicator. (EOM) is the EOI line asserted on the last byte of the command header if the terminator switch is set to EOL Otherwise, (EOM) is the LF (line feed) character if
the terminator switch is set to LF/EOI.
Data Block Structure
The second part of the HSPAT command specifies the data you are downloading into the pattern
generator. Data is transferred using the end block format:
@BC 1S
are a continuous stream of bytes representing the pattern generator program
microcode and patterns. The modules installed determine which data bytes are sent and their
order. The byte order is described below:
For the 91 S16:
1st
2nd
3rd
4th
5th
6th
byte
byte
byte
byte
byte
byte
vector for Pod A
vector for Pod B
microcode (byte 0)
microcode (byte 1)
microcode (byte 2)
microcode (byte 3)
For the 91 S32:
1st
2nd
3rd
4th
5th
byte
byte
byte
byte
byte
vector for Pod
vector for Pod
vector for Pod
vector for Pod
inhibit/strobe
A
B
C
0
The BC,s is always the last byte in the data byte sequence. The BC 16 can be followed by a
semicolon (;) and any formatting character (LF, CR. or SP).
Operating Instructions
CAS 9100 Series 91516-91532 Service
Cautions and Restrictions when using the HSPAT command
When you view a program downloaded into your pattern generator, data vectors, instructions,
strobes, and inhibit data will be properly displayed in the pattern generator Program: Aun submenu, but labels will not be correctly displayed. HSPAT uses hardware addresses instead of labels.
Programming the Interrupt Mode. Absolute memory addresses used by the GPIS command are
affected by the interrupt handling mode you have selected in the 91 S16 Setup: Probe sub-menu.
You must select the desired interrupt mode using the DAS keyboard before beginning GPIS
operation.
If you select "IAQ enabled, CALL mode," you must structure your controller program to
enter the first line of the interrupt service routine in hardware location O. (When an interrupt arrives,
the DAS will automatically look in the first memory location for the address of the service routine.)
This means that the first sequence line of your program (SEQ 0) should be addressed to memory location 1, and each subsequent program line is addressed to the memory location one greater than
the SEQ number.
If you have selected "IAQ disabled: or "IAQ enabled, IF IAQ mode: you should address the first
sequence line of your program (SEQ 0) to memory location 0; the memory location and the SEQ
number should match. See the Tables 3-2 and 3-3 for assistance in determining the proper memory
address for the interrupt mode you have selected.
Programming the 91 S16 Register Configuration. Instructions that use the 91 S 16 internal
register are dependant on how you have configured the register in the 91 S 16 Configutation submenu. You must select the 91 S 16 internal register to be either two a-bit registers named AA and
AS, or one 16-bit register named A, before beginning GPIS operation.
Do not program LOAD A, OUT A, INCR A, or DECR A instructions unless you have selected the
91 S16 internal register to be one 16-bit register called R. Conversely, do not program AA and AS
instructions if the 91 S 16 register is configured to be R.
Programming the RETURN Instruction. Do not program the AETUAN instruction unless you
have set the 91S16 Setup: Probe sub-menu's IAQ field to CALL mode.
Since HSPAT uses hardware addresses as Jump destinations, you can program any number of
Jump instructions (without HSPAT, you are limited to 15 labels).
Correlating Menu Sequences and Hardware Locations
Since the HSPAT command loads your program directly into the 91S16/32 memory, you must use
hardware locations to program memory. Tables 3-2 and 3-3 show the relationship between menu
sequence and hardware location.
3-125
Operating Instructions
CAS 9100 Series 91S16·91S32 Service
Table 3-2
MENU SEQUENCE AND HARDWARE LOCATION FOR 91S16
Menu Sequence
Hardware Location
IRQ enabled
CALL
IRQ disabled
or IF IRQ
reserved
0
0
1
1
1
2
3
2
3
4
2
3
4
1022
1023
1023
0
91 S32 Sequence Number to Hardware Location Adjustments
When designing the files your controller will use to download data into the 91 S32, you must take
two factors into account. First, the 91 S32 loads its memory from the bottom up, and the last
sequence line is loaded into. the very first memory location used. This factor becomes important
when you are designating the hardware location for 91 S32 data; especially if you downloading files
shorter than 2047 sequence lines to 91 S32s operating in Sequential mode, or 91 S32s operating
without a 91S16. Second, in Sequential and 91S32 Stand-Alone modes, certain combinations of
the internal and external inhibit signals (programmed in the 91 S16 Probe sub-menu) require you to
invert the inhibit bit value you download.
Table 16 shows the relationship between sequence line and hardware location for 91 S32s in both
versions of Follows 91 S16 mode, and when you are downloading a full block of 2047 sequence
lines to 91 S32s in Stand-Alone or Sequential modes.
If you are downloading fewer than 2047 sequence lines to 91 S32s in Stand-Alone or Sequential
modes, designating the correct hardware location for each sequence line is less intuitive. See the
following paragraph, titled Partial 91532 Memory Reloads, and Table 17.
3-126
Operating Instructions
CAS 9100 Series 91516-91532 Service
Table 3-3
MENU SEQUENCE AND HARDWARE LOCATION FOR EACH 91S32
Menu Sequence
Hardware Location
FOLLOWS 91S16 Mode
ID
ID
~
IRQ enabled
CALL < label>
IRQ disabled
or IF IRQ
reserved
0
1
2
3
0
1
2
3
4
1022
1023
reserved
1023 (0)
1024 (1)
1025 (2)
1026 (3)
1024
1025
1026
1027
1028
SEQUENTIAL
2047
0
1
2
3
0
1
2
3
4
1022
1023
1023
1024
1025
1026
1027
1024
1025
1026
1027
1028
~046 (END SEQ -1)
2047
-
(0)
(1)
(2)
(3)
(4)
lIS
a.
2045 (1022)
2047 (1023)
Note: This example shows SEQUENTIAL mode when the END SEQ field is
3-127
set to 2047.
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
Partial 91532 Memory Reloads. When 91 S32s in Stand-Alone or Sequential mode are reloaded
with fewer than 2047 sequence lines, the hardware address for each sequence line is dependent on
the value entered into the END SEa field. You will need to enter the END SEa value either by using
key codes via the GPIB, or else by using the DAS keyboard while in the Program: Run sub-menu
prior to downloading the vectors.
The 91S32 loads its memory from the bottom up, starting with hardware location 2047. In other
words. the highest-numbered memory locations are always filled, but the lowest-numbered
memory locations will only be filled if you are reloading the entire memory. See Table 3-4 for
examples of how the sequence numbers are loaded into hardware for various sizes of partial
reloads. Notice that the sequence line specified in the END SEa field is loaded into the first available
memory location.
Table 3-4
91S32s in Sequential and Stand Alone Modes
Menu Sequence to Hardware Location Map
END SEa 2047
ASEa
2047
0
1
2
3
2045
2046
END sea 1999
Hardware
Location
ASEa
Hardware
Location
2
3
4
1999
0
1
2
3
48
49
50
51
52
2046
2047
1997
1998
2046
2047
0
1
END sea 1
ASEa
Hardware
Location
7
0
1
2
3
4
5
6
2040
2041
2042
2043
2044
2045
2046
2047
The following equation shows you how to determine the hardware location for most sequence lines
relative to any given END SEa value. The equation for finding the correct hardware location for the
sequence line specified in the END SEa field follows. Note: This equation only applies if you are using 91 S32s in Stand-Alone or Sequential modes.
Absolute hardware address
=
2048 -
END SEa value
+
ASEa address.
For example, to find the hardware address for sequence line 25 when you are downloading 100 sequence lines, you would first set the END SEa field to 99 (100 sequences). Then, using the formula:
x = 2048 - 99
X = 1974
+
25
To find the hardware location for the sequence line deSignated in the END sea field. use the
following formula:
END SEa line hardware address = 2047 -
END SEa field value.
Note: You cannot change the END SEa field value after you have downloaded the HSPAT
command.
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
91S32 Sequential and Stand-Alone Mode Inhibit Bit Inversion. Certain combinations of the
internal and external Inhibit bits (selected in the Probe sub-menu) require you to invert the
downloaded internal inhibit value (i.e.• program a binary 0 where you would otherwise program a binary 1). The following combinations of internal and extenaf inhibit bits do not require any change:
DISABLE
INT 1 ONLY
EXT 0 ONLY
EXT 1 ONLY
INT 1 OR EXT 0
INT 1 OR EXT 1
INT 0 AND EXT 0
INT 0 AND EXT 1
The following combinations of internal and external inhibits require you to invert the internal inhibit
value inorder to obtain the expected results:
.
INT
INT
INT
INT
INT
0 ONLY
0 OR EXT 0
0 OR EXT 1
1 AND EXT 0
1 AND EXT 1
3-129
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
91S16 Microcode Bit Assignments.
NOTe
The 91516 microcode bits are assigned as shown in Table 3-5.
All bit values are given in binary.
Table 3·5: 91S16 Microcode Bit ASSignment
BYTE 0
BYTE 1
I 11 :I 51 y41 31 21
"
,1
0
I
~
1..
_ _ _ _ _ _ Jump Address -
low 8 bits
1~11=::6:::=5
=4,,~1::3:::;2~
111:::70I
.....'-,,-/~
L
Jump Address
L-OUT Instructions
--SEQ FLOW, CONTROL
Instructions
BYTE 2 1
11
6
5
41
\~~
3
~ high 2 bits
00 01 10 11 10 -
Output Vector
OUT RS (8-bit register configuration)
OUT RA (S-bit register configuration)
OUT REP (Repeat previous output)
OUT R (16-bit register configuration)
0000 - RETURN
1000 -JUMP
0100 - ADVANCE
1100 -IF RS=O JUMP
0010 -IF RA-O JUMP
1010 -IF R=O JUMP
0110 -IF EXT JUMP
1110 -IF END JUMP
0001 - IF FULL JUMP
1001 - IF KEY JUMP
0101 - IF IRQ JUMP
1101 - CALL RMT
21 11 01
lL
LI (Inhibit for Pod A)
I (Inhibit for Pod S)
S (Strobe for Pod A)
-S (Strobe for Pod S)
OO-LOAD RS
01 -INCR RS
10-DECR RS
1...._ _ _ _ _ _ _ _ _1_1_-_H_O_L_D_R_S_ _ For 16-bit
Register R
OO-LOAD RA
l....oLoad Pod A
01-INCR RA
vector into RA
10-DECR RA
11 - HOLD RA
l..-Load Pod A
vector into RS
BYTE 3
" - / l LL
I 11
61 5\ 41
3\ 21 11
01'
LNCR PAGE (Next Page)
HALT
TRIGGER (Trigger Out)
M (Interrupt Mask)
1...._ _ Not Used
3·130
0000- LOAD R
0101 -INCR R
1010 - DECR R
1111 - HOLD R
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
91 S32 Microcode Bit Assignments. Multiple 91 S32s are addressed according to their bus slot
location. Table 3-6 shows the 91 S32 strobe and inhibit bit assignments.
Table 3-6: 91S32 Strobe/Inhibit Code Bit Assignment
Strobe A
Strobe 8
Strobe C
Strobe 0
Inhibit A
Inhibit 8
Inhibit C
Inhibit 0
Using the HSPAT Command
The HSPAT command loads the DAS hardware directly; it does not set up the Pattern Generator
sub-menus. As a result, HSPAT does not show labels programmed in the 91S16 Program: Run
sub-menu.
NOTE
Instructions containing labels in the 91516 Program: Run sub-menu may
contain invalid data after the H5PAT command has been executed.
You can use HSPATwhen the 91 S16 Setup: Probe sub-menu interrupt request (IRQ) field is set to
either 'CALL ' or "IF IRQ" mode, but you must remember that "CALL " mode reqires that you enter the first line of the interrupt service routine into the first hardware memory
location.
PROGRAMMING THE PATTERN DOWNLOAD FROM HOST FEATURE
There are two versions of the Pattern Download From Host Feature: The version that stimulates
static devices can be run with any standard combination of 91S16 and 91S32 modules. This
version is called Pattern Download For Static Devices, and it does not support the Keep-Alive
feature. Dynamic circuits that require constant clock and vector inputs even while the pattern
generator module is being reloaded from the host computer require the Pattern Download For
Dynamic Devices .(Keep-Alive) version. A description of that version appears later in this section.
Pattern Download For Static Devices
When using Pattern Download For Static Devices, the pattern generator will alternately output a
block of vectors, fix the last vector at the probe tips while it reloads the next block of vectors from
the host computer, and then output the next block of vectors. No special fields need to be enabled
in order to use Pattern Download For Static Devices.
If a 91 S16 is used, you must program the HALT instruction on the last line of each 91 S 16 vector
download.
3-131
Operating Instructions
DAS 9100 Series 91516-91532 Service
HALT Instruction. When the 91S16 executes a HALT instruction, or the 91S32 completes its
specified number of LOOPs, SAQ is asserted. The DAS then responds with status byte 66
(operation complete) when polled by the controller. Status byte 66 indicates that the pattern
generator has halted with the last vector asserted at the probe tip. Execution may be resumed by
downloading a new setup to the pattern generator and then sending a start command. New setups
may be downlaoded by using either the PATGEN binary restore command or the HSPAT
co.mmand.
NOTe
When using both acquisition and pattern generator modules, it is possible for
status byte 66 to be generated twice (once for completion of acquisition and
once for completion of pattern generation). If the control/er polls the DAS
after both of these operations have been completed, only one status byte 66
will be received.
Ex~ample of Binary File that extablishes 91516 Run SUb-menu.
When downloaded, the following file (Table 3-7) results in the 91 S16 Aun sub-menu displayed at
the right (Figure 3-21). The HSPAT command and its arguments are listed in the first line of the file.
Note: The selected IAQ mode is CALL ; memory location 0 is loaded with the first line of
the interrupt servicing routine.
Table 3-1. Binary file for Pattern Download For Static Devices.
sea
Hardware
Location
Pattern Generator
Program
PAmRII GElERATOP P!I1)';PH/I
[HHIBIT
~f<')I(
-1
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
11
HSPAT
@ 00
34
FF
00
00
00
00
00
00
00
00
00
BC
4,0,12 (EOM)
07 OA 80
12 00 40
01
00 40
02 00 48
03 00 48
84 07 28
05 03 88
06 00 40
07 00 40
08 00 40
09 00 40
OA 00 00
<' m
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0
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c:
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0)
0)
(,,')
"Ol
Q)
co
0
a:s
rn
,...
"0
0
a:s
a:s
rn
,...
6'
SEQ
>-
FO
FO
3C
FO
FO
B8
FC
Fe
FO
Fe
Fe
Fe
00
08
08
08
08
08
00
02
00
00
00
00
-,...
N
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>-
>-
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>-
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rn
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0
CEJ
413...
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I
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01,,:
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FLCI>I,CONT~L
_ _ UElIiIOO _ __
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1,.q8El,
Ii1mI
0
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,...
3-132
I
LOOP
a2'JiJ
cOAt] Rf.l
'JUT Ril
2 q I
0JCOOOl
841l1)
i 1
REG, OUT
IF RAOIj JUM!'
DO~IE
JUT RA
I~JT RA
OE:,
DOME
!HT
'j
:0
:1
12
:3
05 0e
96 'JIl
Ii ~~
jlJl'f
HfllT
LOCI'
RJ<
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0'. (0)
~9
ljij
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00
ae 00
REnJRH
eeoo~ee
W:X,;i.iE:' •• :m_p.jO.
5397·28
Figure 3-21. 91816 Program: Run sub-menu display
after binary download.
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
Pattern Download For Dynamic Devices (Keep-Alive)
Pattern Download For Dynamic Devices (Keep-Alive) is only available if you are using DAS Option
06: I/O Interlace (High Speed GPIB Programming). You must use a GPIB controller and the DAS
GPIB interlace. You must have a 91S16 and at least one 91S32 installed in the DAS.
When using Pattern Download For Dynamic Devices (Keep-Alive), the pattern generator outputs a
page of vectors from both the 91 S16 and the 91 S32s. When the 91 S16 reaches the bottom of its
page, it enters a Keep-Alive subroutine that: 1) asserts the DAS SRO line and informs the GPIB
controller it is ready to receive a download (CALL RMT instruction), 2) executes the sequence lines
contained within the Keep-Alive subroutine, thus continuing to output pattern to the circuit under
test, and, 3) loops within the Keep-Alive subroutine until the controller sends a message that either
the next page of vectors has been downloaded, or there are no more vectors to be downloaded.
Upon receiving either of these instructions, the pattern generator exits the Keep-Alive routine and
either instructs the 91 S32s to begin executing the newly refilled memory page (implied INCR PAGE
from IF FULL instruction), or else jumps to a specified shut-down routine (IF END instruction).
Description of Instructions:
CALL RMT When the CALL RMT (Call Remote device) instruction is executed, the DAS asserts
the SRO (service request) line and responds with status byte 197 when polled over the GPIB.
Status byte 197 informs the control/er that the pattern generator is ready for a download.
IF FULL JUMP When the 91 S16 executes the IF FULL JUMP instruction it tests to see if the DAS
has received KEY 46 from the controller. If KEY 46 has been received, the 91S16 instructs the
91 S32s to change execution to the other memory page (implicit INCR PAGE), and begin execution
on the sequence line containing the specified label. Initially, the pattern execution begins with Page
A; the first successful IF FULL JUMP instruction transfers execution to Page B.
When constructing your controller program, you must send KEY 46 at the end of each complete
download. If you are loading two 91532 modules, the KEY 46 command should be sent only after
both 91 S32s have been loaded by HSPAT commands.
IF END JUMP When the 91S16 executes the IF END JUMP instruction it tests to see if the DAS
has received KEY 47 from the controller. KEY 47 indicates that the controller has no more vectors
to download to the 91S32s. Usually, the IF END JUMP instruction gives control to a routine that
completes the pattern generation.
3-133
Operating Instructions
CAS 9100 Series 91SJ6~91S32 Service
Example of a Binary File that establishes 91S16 Run sub-menu and Keep·Alive routine.
When downloaded, the following file results in the 91 S 16 Run sub-menu displayed at the right.
Note: The selected IRQ mode is DISABLED so memory location 0 is loaded with SeQ 0 of the pattern generator program. Refer to Table 3-8 and Figure 3-22.
Table 3-8. Binary File for Pattern Download
for Dynamic Devices.
SEa Hardware
Location
Pattern Generator
Program
PIlTTERN GEHEllArn1 i'POGRAI!'
!tfliBIT
MSk
0
1
2
3
4
0
1
2
3
4
5
HSPAT
@ 00
11
22
33
44
55
5
6
6
66
7
7
77
8
8
88
9
9
99
10
10
11
12
11
AA
BB
13
14
CC
12
13
14
DO
EE
4,0,15 (EOM)
00 00 40
11
00 40
22 00 40
33 00 40
44 00 40
55 00 40
66 00 40
77 00 40
88 00 40
99 00 40
AA 00 DO
BB 00 10
CC OE EO
DO OA 80
EE 00 40
S£Q
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
FO
00
00
00
00
00
00
00
00
00
00
00
00
00
00
02
Be
..:0::
(.)
0
as
'l:j
- - -....- - - a. a. a.
-<' co
'l:j
0
'l:j
0
~
~
ttl
ttl
ttl
ttl
s::
w
0
c::
0
-
>-
>-
>-
.0
CD
'l:j
0
()
::t
CD
CD
CD
'l:j
'l:j
'l:j
0
0
0
()
()
()
::t
::t
::t
MI.5&,III
a a a
a
a
a
e
cc cc e
00 00 e
E£ E£ a
8888
9999
Ail M
sa B8
REG.OOT
_
0
a
a
a
a
e
0
a
a
e CAU. RI!T
0 IF F\ll J.I'f
e IF Elf) J.I'f
a m
STRT
STili'
~.A
0 HALT
MiMi. . POD
•
5397·29
Figure 3-22. 91S16 Program: Run sub-menu display
after binary download.
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
Debugging HSPAT Programs
There are two methods you can use to debug your HSPAT programs. The first is based on the Pattern Generator TRACE and STEP modes, and the second is based on acquiring the program into
acquisition memory. TRACE mode is basically an automatic version of STEP mode, so the STEP
mode description applys to both.
STEP Mode Method: The STEP mode method uses the Pattern Generator STEP mode to show
you the vector sequences as they have been processed by your program. For example, if your program contains a loop, the STEP mode method allows you to single-step through the repeated
sequences. To use the STEP mode method:
1.
Press the PATIERN GENERATOR key to enter the Program: Run sub-menu. Move the screen
cursor to the MODE field and press SELECT until STEP appears.
2.
Download the HSPAT command and your program.
3.
Press the START PAT GEN key to single-step through the vector sequences.
Acquisition Method: The acquisition method allows you to look at your vector data in the State Table display. As with STEP mode, the acquisition method shows you the vector data sequences as
they have been processed by your program. Unlike STEP mode, the acquisition method allows you
to see the vector data as a whole (not one sequence line at a time).
To use the acquisition method:
1.
Connect your pattern generator module to an acquisition module with probes. Each pod used
on the pattern generator must be connected to a pod on the acquisition module.
2.
Download the HSPAT command and your progam.
3.
Acquire the data with the acquisition module.
4.
View the data in the State Table display.
SAMPLE GPIB CONTROLLER PROGRAMS
The following sample programs were written using a Tektronix 4050 Series graphic system as the
GPIB system controller. Other controllers may require some program modification to work
properly.
The sample programs use variable 01 as the talker/listener address for the DAS. You will need to
enter this variable when you run the program. This variable needs to correspond to the setting you
selected on the DAS address switch. The selected address is displayed at the top right corner of
the Input Output menu.
Each program has a subroutine for handling Service Requests (SROs). The program interrupts to
this subroutine whenever SRO is asserted.
3-135
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
NOTE
Some controllers can inadvertently Untalk the DAS by asynchronously
responding to an SRQ from the DAS. For a discussion of this situation, see
the Status Bytes, Error Codes, and Service Requests section of the Option
06 I/O Interface Operator's Addendum (Part of the CAS 9100 Series
Operator's Manual package).
Modifying the Programs.
not the following:
If you need to mOdify these sample programs to run on your controller,
• The 4050 Series controller automatically asserts Remote Enable (REN) when these programs
are run. You will need to include a statement that asserts REN in your program if your controller
does not automatically do so.
• Table 12-42 of the Option 06 Operator's Addendum shows the traffic associated with the
BASIC commands listed in the programming examples. This information may be useful to you if
your controller functions differently from the 4050.
Sample Controller Program For Pattern Download For Static Devices
The example Pattern Download From Host for Static Devices program discussed in this section
presupposes the following:
• A 91 S16 (or 91 S32) module is installed in slot 4.
• A properly formatted tape is currently mounted in the controller tape drive.
• If a 91 S16 is used, the tape contains one or more files in binary end block format that specify
vector data with a HALT instruction on the last·sequence for the 91S16 module.
• If a 91 S32 is used, the tape contains one or more files in binary end block format that specify
vector data for a 91 S32 module.
The following steps must be taken to program the example Pattern Download For Static Devices
program:
1.
Enter the 91S16 Setup: Probe sub-menu and set the IRQ field to IRQ enabled, CALL
<1000>.
2.
Enter the Setup: Timing sub-menu and set the clock rate.
3.
Adapt the following controller program program to suit your needs. An example of a binary file
that establishes the 91S16 Aun sub-menu follows the program listing.
3·136
Operating Instructions
DAS 9100 Series 91S16-91S32 SeNice
Overview of GPIB Controller Operation. The GPIB controller prompts the user for the DAS
GPIB address, then waits for the DAS to assert an SRO. When the proper SRO is detected, the
controller prompts the user for the number of the file containing data to be loaded into the first
91 S32, issues the appropriate HSPAT command, and downloads that file. The controller continues
to wait for SROs (when the pattern generator executes a HALT instruction) and then performs file
download routines until all files have been downloaded.
In order to use this feature, you must establish a GPIB controller program similar to that in Table 39. No special settings are required in the 91 S16 or 91 S32 sub-menus, but you must remember that
hardware addresses are affected by the interrupt request mode selected. When using GPIB
commands, the DAS cannot check for invalid entrys.
Table 3-9
Sample Pattern Download From Host Controller Program for Static Devices
Main Program
100 PRINT "Enter DAS address: ';
110 INPUT D1
1. Prompt the user for the DAS talker/listener address
120 ON SRO THEN 2000
2. Establish the SRO interrupt routine
130 GOSUB 1000
3. Load the pattern generator module
140 PRINT @D1:"START PGN"
4. Start the pattern generator
150 B1 =0
5. Wait for the pattern generator to halt (operation complete: SRO 66 or 82)
160 IF B!<>66 AND B1 <>82 THEN 160
170 PRINT "Downlad more vectors? (Y or N): ';
180 INPUT Z$
6. Prompt the user for more vectors to download.
190 IF Z$<>"Y' THEN 220
200 GO TO 130
7. If the response is "Y," perform another download.
210 IF Z$<>N THEN 170
220 PRINT "DONE"
230 END
8. If the response is "N," report that the downloads are
finished.
3-137
Operating Instructions
OAS 9100 Series 91S16-91S32 Service
Table 3-9 (cont.)
Sample Pattern Download From Host Controller Program for Static Devices
Pattern Generator Load Routine
1000 PRINT "Loading vectors, enter file number: "; 1. Prompt use for tape file containing binary end block.
1010 INPUT F1
1020 FIND F1
2. Find file.
1030 PRINT @D1:"HSPAT 4,0,16"
3. Send HSPAT command header.
1040 WBYTE @D1+32:64
4. Designate the DAS as a listener.
1050 READ @33:B
5. Read binary data off tape byte-by-byte.
1060 WBYTE B
6. Relay it to the DAS.
1070 IF B=>O THEN 1050
7. Final EOI sets 4050 Series sign bit negative.
1080 WBYTE @63:
8. Unlisten the DAS.
1090 RETURN
9. Return to load routine.
SRQ Handler Routine
2000 POLL A1,B1;D1
1. Poll the DAS
2010 IF 81 =66 OR B1 =82 THEN 2050
2. If the SRQ is an "operation complete" (a halt occurred),
let it pass through and be handled by the main
program.
2020 PRINT @D1 :"ERRMSG?"
3. Otherwise, query the DAS for an error message.
2030 INPUT @D1 :E$
4. Receive the error message from the DAS.
2040 PRINT "Status =" ,B1 ,E$
5. Print the status and error messages.
2050 RETURN
6. Return to main program.
3-138
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
Sample Controller Program for Pattern Download For Dynamic Devices (KeepAlive)
The example Pattern Download For Dynamic Devices (Keep-Alive) program listed here presupposes the following:
• A 91S16 is installed in slot 4 and a 91S32 is installed in slot 5.
• A Properly formatted tape is currently mounted in the controller tape drive.
• The tape contains a file in binary end block format that specifies the vector data and Keep-Alive
routine for the 91 S16 module.
• The tape contains one or more files in binary end block format that specify vector data for a
91 S32 module.
The following steps must be taken to enter the example Keep-Alive program listed below:
1.
Enter the 91 S32 Configuration sub-menu and select FOLLOW 91 S16 mode. Set the MEMORY
RELOAD FROM HOST (FOR KEEP-ALIVE) field to ON.
2.
Enter the 91S16 Setup: Probe sub-menu and set the IRO field to DISABLED.
3.
Enter the Setup: Timing sub-menu and set to clock rate to 40 ns or greater.
4.
Adapt the following controller program to suit your needs. A sample binary file that establishes
the 91 S 16 Run sub-menu. including the Keep-Alive routine, follows the controller program.
Overview of GPfB Controller Operation. The GPIB controller prompts the user for the DAS
GPIB address. then waits for the DAS to assert an SRO. When the proper SRO is detected. the
controller prompts the user for the number of the file containing data to be loaded into the 91 S 16.
The controller then issues the HSPAT command and downloads the contents of the file. It then
prompts the user for the number of the file containing data for the first 91 S32. issues the
appropriate HSPAT command. and downloads that file. The controller continues to wait for 5ROs
and then perform file download routines until aU files have been downloaded.
In order to use this feature you must establish a GPIB controller program similar to that in Table 3-10.
No special settings are required in the 91S16 or 91532 sub-menus. but you must remember that
hardware addresses are affected by the interrupt request mode selected. When using GPIB
commands. the DAS cannot check for invalid entrys; you must not program instructions that have
been disabled.
3-139
Operating Instructions
DAS 9100 Series 91516-91532 Service
Table 3-10
Sample Pattern Download For Dynamic Devices Controller Program (Keep-Alive)
Main Controiler Program
100 PRINT "Enter DAS address: ";
110 INPUT 01
1. Prompt user for DAS talker/listener address
120 ON SRO THEN 4000
2. Establishes SRO interrupt routine
130 GOSUB 1000
3. Load 91S16
140 GOSUB 2000
4. Load 91S32
150 PRINT @D1:"START PGW
160 81 ... 0
5. Start Pattern Generator
170 IF B1 <>197 AND B1 <>213 THEN 170
6. Wait for CALL RMT to occur
180 PRINT "Download more vectors? (Y or N):";
190 INPUT Z$
7. Prompt the user for continuation of Keep-Alive
200 IF Z$<>"Y" THEN 270
8. If the response is "Y," send another page to the
91S32, issue "KEY 46" to indicate "FULL," wait for
another "CALL RMT."
210 GOSUB 2000
220 PRINT @D1:"KEY 46"
230 GO TO 160
9. If the response is "N," issue "KEY 47" to indicate
"END."
240 IF Z$<>"N" THEN 180
250 PRINT @D1:"KEY47"
1QReport when finished
260 PRINT "DONE"
270 END
91S16 Load Routine
1000 PRINT "Loading 91 S16, enter file number: ";
1010 INPUT F1
1. Prompt user for tape file containing binary end block
1020 FIND F1
2. Find file
1030 PRINT @D1:"HSPAT 4,0,16"
3. Send HSPAT command header
1040 GOSUB 3000
4. Send binary end block to 91S16
1050 RETURN
5. Return to main program
3-140
Operating Instructions
CAS 9100 Series 91516-91532 Service
Table 3-10 (cant.)
Sample Pattern Download For Dynamic Devices Controller Program (Keep-Alive)
91S32 Load Routine
2000 PRINT "Loading 91S32, enter file number:";
2010 INPUT F1
1. Prompt for tape file containing binary end block
2020 FINO F1
2. Find file
2030 PRINT @D1:"HSPAT 5,0,16"
3. Send HSPAT command header
2040 GOSUB 3000
4. Send binary end block to 91S32
2050 RETURN
5. Return to either main program or to SRQ handler
routine
Binary Transfer Routine
3000 WBYTE @D1 +32:64
1. Designate the DAS as listener
3010 READ @33:B
2. Read binary data off tape byte-by-byte
3020 WBYTE B
3. Relay it to the DAS
3030 IF B==>O THEN 3010
4. Final EOI sets 4050 Series' sign bit negative
3040 WBYTE @63:
5. "Unlisten" the DAS
3050 RETURN
6. Return to either 91 S16 or 91 S32 load routine
SRQ Handler Routine
4000 POLL A1,B1;D1
1. Poll the DAS for status
4010 IF B1 ==197 OR B1 ==213 THEN 4050
2. If the SRQ is a "CALL RMT," let it pass through and
be handled by the main program.
4020 PRINT @D1:"ERMSG?"
3. Otherwise, query the DAS for the error message.
4030 INPUT @D1 :E$
4. Receive error message from the DAS.
4040 PRINT "Status == ",B1 ,E$
5. Print status and error message
4050 RETURN
6. Return to main program.
3-141
Operating Instructions
CAS 9100 Series 91S16-91S32 Service
ERROR AND PROMPTER MESSAGES:
Additions with the 91516 and 91532 Pattern Generator Modules
NOT A 91S16 POD
Appears in the 91 S16 Program: Run sub-menu when you enter an invalid
pod 1.0. in the CONVERSION: CONVERT POD editing command. Check
to see which OAS slot the 91 S 16 is installed in and enter the appropriate
pod 1.0.
NOT A 91 S32 POD
Appears in the 91 S32 Program: Run sub-menu when you enter an invalid
pod 1.0. in the CONVERSION: CONVERT POD editing command. Check
to see which DAS slot the 91 S16 is installed in and enter the appropriate
pod 1.0.
CALL UNAVAILABLE:
"IF IRQ" USED IN PROGRAM
Appears in the 91 S 16 Setup: Probe sub-menu when you attempt to
change the interrupt request (IRQ) mode. You must remove any IF IRQ
JUMP instructions from the Program: Run sub-menu before
changing modes.
CALL UNAVAILABLE:
SEa FLOW USED AT SEQ 1023
Appears in the 91 S16 Setup: Probe sub-menu when you attempt to
change the interrupt request (IRQ) mode. CALL mode reserves the first
memory location for the interrupt routine jump address; this reduces the
number of available sequence lines from 1023 to 1022. You must remove
any sequence flow (SeQ FLOW) instructions programmed in SEa 1023
before selecting CALL mode.
"IF IRQ" UNAVAILABLE:
"RETURN" USED IN PROGRAM
Appears in the 91S16 Setup: Probe sub-menu when you attempt to
change the interrupt request (IRQ) mode. You must remove the RETURN instruction programmed in the 91 S16 Program: Run sub-menu
before selecting IF IRQ mode.
PROCESSING IRQ SETUP
Appears when you attempt to exit the Setup: Probe sub-menu after
changing IRQ modes. This message will disappear when the processing
is complete. No action is required.
"R" USED IN PROGRAM
Appears in the 91 S 16 Configuration sub-menu when you attempt to
select two a-bit internal registers named RA and RB. Remove any
instructions pertaining to the 16-bit internal register named R from the
Program: Run sub-menu before changing the configuration of the 91 S16
internal register.
3-142
Operating Instructions
DAS 9100 Series 91S16-91S32 Service
ERROR AND PROMPTER MESSAGES:
Additions with the 91516 and 91532 Pattern Generator Modules
"RA" OR "RB" USED IN PROGRAM
Appears in the 91816 Configuration sub-menu when you attempt to
select a single 16-bit internal register named R. Remove any instructions
pertaining to the 8-bit registers named RA and RS from the Program:
Run sub-menu before changing the configuration of the 91 816 internal
register.
"IF FULL", "IF END", or
"CALL RMT" USED IN PROGRAM
Appears in the 91832 Configuration sub-menu when you select OFF in
the MEMORY RELOAD FROM H08T (FOR KEEP-ALIVE) field. Remove
any IF FULL, IF END, and CALL RMT instructions from the 91816
Program: Run sub-menu before selecting OFF in this field.
PROCESSING END ASEQ SETUP
DA8 is processing setup changes. No action required.
EDIT IN PROGRESS: < < < < < < <
Appears in the Program: Run sub-menu whenever lengthy edit operations are in progress. Chevrons will disappear as the process continues.
No action required.
3·143
Section 4
THEORY OF OPERATION
Section Organization
This section is designed to familiarize service personnel with
the operation of the 91Sl6 and 91532 circuitry. It is divided
into five main subsections:
1. 91S16/91S32 System Architecture describes how 91516 and 91S32
modules fit into the DAS architecture.
2. 91S16 General Description describes the 91Sl6 at the
functional block level.
3. 91S32 General Description describes the 91532 at the
functional block level.
4. 91S16 Detailed Circuit Description describes 91Sl6 operation
at the component level.
5. 91S32 Detailed Circuit Description describes 91S32 operation
at the component level.
Throughout this section, references are made to the 91Sl6 and
91S32 block diagrams and schematics located in the Diagrams
section at the back of this addendum. The schematic and block
diagram pages have tabs indicating the page title. Tabs on
schematic pages include the numbered diamond assigned as the
schematic number.
Schematics are often referred to by the
numbered diamond on the schematic tab.
For a more complete understanding of the 91Sl6 and 91532 modules,
you may also want to refer to the signal glossary in the
Reference Information section and to the diagnostic information
in the Maintenance: Troubleshooting section.
Logic Conventions
In this manual, digital logic is described using the positive
convention. The more positive voltage indicates a true or 1
state~ the more negative voltage indicates a false or 0 state.
In logic descriptions, the more positive voltage is referred to
as high, and the more negative voltage is referred to as low.
The specific voltage that specifies a high or low state varies
depending on the type of logic device. TTL, ECL, and CMOS
devices all have different logic threshold levels.
Signal names on schematics are normally asserted high. Only
signal names with overscores are asserted low. In this text,
signals asserted high have the suffix (H)~ PAGA(H), for example.
Those asserted low have the suffix (L), such as MWEM(L).
4-1
Theory of Operation
DAS 9100 5eries 91516-91532 5ervice
91516/91532 5ystem Architecture
The 91516 and 91532 Pattern Generator Modules are designed to
reside in any of the instrument bus slots (1 through 6) of any
DA5 9100 mainframe. All 91516 and 91532 modules should be placed
in adjacent bus slots. The mainframe must contain firmware
version 1.11 or higher, along with the hardware changes
associated with the firmware version. In particular, the 91S16
and 91532 modules must be installed in DAS slots served by the
new 22 amp 5 V power supply. More information on firmware
version 1.11 is located in the Operating Instructions section of
this addendum.
Both types of modules are initialized and read by the Controller
board in the DA5 mainframe. The firmware that allows the
Controller board to operate is located on the 91516 and 91532
modules. The Trigger/Time Base board provides the clock to each
module for synchronous operation. The only exception to this is
when the 91516 is operating as a controller for 91532 modules, in
which case the 91516 supplies the clock to the 91532s.
91516 ALGORITHMIC PA'r'l'BRN GENERATOR
The 91516 is an algorithmic pattern generator providing 16 data
output channels, two clock lines and two strobe lines. 5trobes
can be used as additional output channels. The master clock can
be supplied either from the DA5 internal clock or from an
external device. Maximum clock rate is 50 MHz. Data output is
normally synchronous with the master clock, but individual PODs
(probes) can be programmed to output data +5 ns relative to the
master clock. Individual data and strobe lines within each POD
can be programmed to output data an additional +5 ns relative to
their POD clock. Pattern memory is 1024 sequence lines (vectors)
deep.
The 91516 provides an internal l6-bit data register (or two 8-bit
data registers) which can be used as counters or as an alternate
source for pattern output. The 91516 instruction set includes 9
instructions ranging from simple JUMP to label commands to IF
Register = a JUMP to label. Fifteen different labels can be
programmed, plus a special interrupt service routine.
Only one 91516 can be installed in the DA5, however the 91516 can
be used as a controller for up to five 9l532s.
91532 RAM-BASED PA'r'l'BRN GENERATOR
The 91532 is a RAM-based pattern generator providing 32 channels
of data, four strobes, and four clock lines. In addition, the
strobe lines can be used as extra data channels. Maximum clock
speed is 50 MHz. Pattern depth for all channels is 2048 sequence
lines (vectors). However, special features allow you to split
4-2
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
the memory into two 1024-line pages and reload alternate pages of
memory while the pattern generator is outputting data (this
requires a 91516). The 91532 can also be programmed to execute
its program repeatedly.
The 91532 usually executes its program in a sequential,
beginning-to-end fashion. However, if you use the 91532 in
conjunction with a P6452 probe attached to the DA5 Trigger/Time
Base module, you can use inputs from that module to supply
External 5tart, External Inhibit, and Pause signals. Data output
is normally synchronous with the master clock~s rising edqe, but
individual PODs can be adjusted +10 ns relative to the master
clock. Individual data and strobe lines can be adjusted an
additional +10 ns relative to their POD clock.
91816 AS CONTROLLER FOR 91S32
One 91516 can serve as a controller for up to five 9l532s. In
this configuration, you can supply up to 16 data channels with a
memory depth of 1024 lines, plus 160 data channels with a memory
depth of 2048 lines. There are also 22 clock and 22 strobe lines
available.
Also, this configuration provides all the branching instructions
and interactive features available with the 91516 in addition to
the large number of data channels and pattern depth afforded by
the 9l532s.
There are two different operating modes available when the 91516
and 9lS32 are used together. These modes are named 5equential
mode and Follows mode.
Sequential Mode
This operating mode allows the 91516 and 91532 to operate
simultaneously. The 91516 will supply the clock signal to the
91532. However, each card will execute its program
independently. In other words, the 91516 can be performing
branching operations, but the 915325 will continue to output
their data in a straight sequential line-by-line manner. The
91516 can be set to automatically restart from the beginning when
it reaches the end of its memory. This will keep all data
channels alive for as long as desired.
4-3
Theory of Operation
DAS 9100 Series 91516-91532 Service
Follows Mode
This operating mode allows the 91516 to have much more active
control of the output of the 9l532s. The 91532 will follow
instructions programmed in the 91516 that govern its sequence
line execution.
In the Follows mode, the vector memory address register of the
91516 acts as the vector memory address register for the 9l532s
via an interconnect cable. This means that if the 91516 executes
a loop, the 91532s will also loop.
The 9lSl6 also supplies the master clock to the 91532 modules.
Usually you would want the 91516 and 91532 to output data
according to the same clock, but you can program the 91532 to
execute its program at one-half, or one-fourth the clock rate
supplied by the 91Sl6 module.
In Follows mode, the memory of the 91532 is divided into two
1024-line pages called Page A and Page Be The size of these
pages matches the memory depth of the 91S16. The 91516 has
control over which memory page the 91532 will execute. You can
enter two different programs in the 91532 (one in each page) and
use the 91516 to switch between the programs based on some signal
sensed by the 91Sl6~s P6460 External Control Probe.
One major feature provided by Follows mode is the automatic
reload function. If your pattern generator program is very
large, or if you have developed the program on a host computer,
the entire program may be too large to fit into the 9l532~s
memory. Follows mode allows you to divide the 9lS32~s memory
into two pages and reload one page while the other page is being
executed. Instructions for communicating with the host computer
or external storage device are programmed into the 91516.
Keep-Alive
Down-loading a pattern from a host computer usually takes longer
than executing the other memory page. This can cause a problem
with dynamic circuit elements that require constant clock and
vector inputs. The 91516/32 combination provides a keep-alive
function to supply the clock and a few vectors to keep the
circuit under test active until the other memory page has been
reloaded. Keep-alive is essentially a subroutine that you
program into the 91516. 5tatic devices being tested so not
require this feature.
4-4
Theory of Operation
DAB 9100 Series 91S16-91S32 Service
91S16 General Description
In the following description, refer to the general block diagram
for the 91Sl6 and the 91S32, located in the Diagrams section.
The schematic numbers are included in the headings for your
convenience.
The 91Sl6 circuitry is divided into the following functional
blocks.
91S16 COlftROLLER nrrBRI'ACB AND ROMs
<92>
The controller interface and ROMs block allows communication
between the DAS Controller board and 91Sl6. Any block in the
91516 general block diagram identified with an asterisk (*) uses
the 91Sl6 controller interface.
The 91516 contains three ROMs which are read by the DAS
Controller board. Board identification, control codes, and
pattern generator menu data are stored in these ROMs.
PATTERN GlSI!IBRATIOR PROBBS
There are two P6464 Pattern Generation probes used with the
91516. They are attached at the back of the module to connectors
labeled POD A and POD B. Each probe is capable of generating
eight channels of data, one clock, and one strobe for either TTL
or ECL logic systems. Programmable features include:
9 TTL or ECL output levels
o output clock polarity
o inhibit (respond to an internal or external inhibit signal)
o data channel timing advance or delay relative to the POD clock
The 9lSl6 can accept an optional P6460 Data Acquisition Probe
used as an External Control Probe. This probe is attached at the
back of the module to a connector labeled POD C. This probe
accepts interrupt, inhibit, jump, and pause signals. This probe
is an active device that converts unbalanced line signals into
differential line signals for transmission to the 91516 module.
4-5
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
PROBE INTERFACE
<92> <94>
The probe interface establishes the serial probe communications
link for the probes, the controller interface, and the status
readback circuitry. This allows the DAS to read the vector being
delivered by the pattern generator probe and also identifies
which probe is attached to each connector (POD). The Probe
interface also sets the proper threshold voltage for the probes.
PROBE RECErvERS
<93> <94> <99>
The probe receivers acquire differential EeL output from the
acquisition and pattern generator probes and convert the signals
to TTL levels.
START IN
<93>
The external start signal enters the 91Sl6 via a phono jack on
the back of the module. The 91Sl6 will start when:
o the external trigger has been enabled in the 91S16 Setup Probe
menu, and
o a transition on the START IN line occurs while the STOP PG(H)
signal is high.
CLOCK COlftROL <93>
Various pattern generator clock rates can be selected using
either internal or external clock signals. The clock can be
stopped by:
o the PAUSE signal supplied by the P6460 probe,
o the STOP PG(H) signal supplied by the DAS Trigger/Time Base
module, and
o the HALT(H) signal supplied by the microcode RAM
VECTOR AND MICROCODE MEMORY
<96>
The vector memory is a lK x 16 bit RAM. The microcode memory
(micro-instruction memory) is a lK x 28-bit RAM. Pattern
generation is controlled by the output of the microcode memory.
4-6
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
Vector and Microcode Assignments
VBO - VB1S vector
JAO - JA9 jump address
MCO output select
MC1 output select
MC2 inhibit A
MC3 inhibit B
MC4 strobe A
MCS strobe B
MC6 PC control
MC7 PC control
MCa PC control
MC9 PC control
MCIO RB control
MC1I RB control
MCl2 RA control
MC13 RA control
MC14 next page ( to the 91532 )
MCIS halt
MC16 trigger out
MCl7 interrupt mask
PROGRAM COON"l'ER COR'l'ROL MULTIPLEXER AND RESET
<95>
The program counter control codes are interpreted by the
multiplexer to determine the next address for the vector memory
output and the microcode memory_ The instruction decoder applies
appropriate reset signals to the external signal latches and
generates a signal used to control the 91532.
ST~
SETUP
<94> <94>
The start setup circuitry establishes the initial signal
conditions in preparation for the start procedure.
PROGRAM COON"l'ER AND
STACK
<95>
The program counter takes the output of the instruction
multiplexer and applies the address to the vector memory and the
microcode memory. The stack performs the same functions, except
that after receiving an interrupt signal the stack stores a
return address.
4-7
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
INTERRUPT LOGIC
<94>
The interrupt logic circuit accepts the external interrupt
signal, clocks it through a register, and applies the appropriate
logic.
EXTERNAL SIGNAL LATCHES
<94>
The external signal latches accept the external signals from the
P6460 probe and hold them. After the appropriate instruction
tests the appropriate bit in a latch, it is automatically reset
by hardware.
91S32 TRANSCErvER
<93> <94> <96>
The 91532 transceiver provides a clock and control logic for
9lS32s operating in the Sequential or Follows mode with a 9lSl6
controller.
REGISTER CONTROL <97>
The 9lSl6 has two a-bit internal registers (or one-16 bit
register). The output of these registers is sent to the
instruction multiplexer through the zero judging circuit and the
pattern selector.
PATTERN SELECTOR <97>
The pattern selector determines the next output pattern. It
selects the output pattern from any of three sources: the vector
memory, the internal register, or the first latch before the
clock (repeat previous vector).
FIRST LATCHES
<97>
Values from the pattern selector and microcode RAM are clocked
into the latches and held until the next value is clocked in.
CLOCK POSITIONING
<98>
The POD clock may be delayed in 5 ns steps over a range of -5 to
+5 ns. This provides the time difference between PODs.
4-8
Theory of Operation
DAB 9100 Series 91S16-91S32 Service
OUTPUT LATCHES
<98>
Values from the first latches are clocked into the output latches
by the delayed POD clock and held until the next value is clocked
in.
TRIGGER OUT
<98>
The 91516 can generate a TTL-level trigger signal supplied via a
phono jack on the back of the instrument module.
CLOCK LINE
<99>
Once the clock is selected, four distinct clock lines are
provided for the system. Each clock line contains the appropriate
delay lines to make the system work synchronously.
INHIBIT CONTROL <99>
The inhibit control circuitry selects either the programmed
internal inhibit signal stored in the microcode memory or the
external inhibit signal received from the P6460 probe. It can
also perform appropriate logic operations between the internal
inhibit and the external inhibit signals.
STATUS READBACK
<100>
The status readback circuits take the data from the microcode
memory, the program counter, and the first latches and performs
appropriate logic operations. The information is divided into
8-bit words for transfer to the controller.
+3 VOLT POWER SUPPLY
<98>
The +3 volt power supply is a switching current pump bootstrapped
to +5 V. It powers the EeL terminating resistors.
4-9
Theory of Operation
DAS 9100 Series 91516-91532 Service
91532 System Synopsis
The 91S32 Pattern Generator Module resides in any of the
instrument bus slots (slots 1 through 6) of a DAS 9100 Series
Mainframe. The 9lS32 module with its four pattern generator
probes issues up to 2048 pattern vectors 32 bits wide, at
sampling rates up to 50 MHZe In addition, each 91S32 provides
four clock signals and four strobe signals. Strobe lines can be
used as additional data lines.
The 91S32 has both a loop counter and a word depth counter (end
sequence counter). You can use a single 91S32 Pattern Generator
module, or combine up to six 9lS32 modules for especially wide
patterns. The 91S32 can also be controlled by a 91S16 pattern
generator module.
A 91S16 used as a controller can accept up to five 91S32
expansion modules. Pattern generator modules must be in adjacent
slots in the DAS with the 9lS16 module on the end. Each
additional 91S32 module supplies an additional 32 data channels,
four clocks, and four strobes. When using the 9lSl6 as a
controller, maximum clock speed is 25 MHz. Clock and Address
signals are sent from the 91Sl6 to the 91S32s through a 40-wire
flat cable attached to a card-edge connector on the top of each
instrument module.
The 9lS32 pattern output can be clocked in several different
ways. When 91S32s are used without a 91Sl6 module, they can
receive their master clock either from one of the DAS~s internal
clocks or from an external clock signal delivered through an
external control probe attached to the DAS Trigger/Time Base
module.
When a 91Sl6 is used to control the 9lS32, the 91S32~s clock is
supplied by the 91Sl6 module. Usually, you will want the 91S32~s
clock to be the same as that for the 91Sl6, however you can also
program the 9lS32 to run at one-half or one-fourth the 91S16
clock rate.
A pattern is generated from the memory on each clock cycle.
Pattern generation stops when the Trigger/Time Base module
asserts the stop-pat tern-generator signal.
4-10
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
91S32 General Description
The following description refers to the general block diagram
located in the Diagrams section. Schematic numbers «iii» where
the functional blocks can be located are included.
91S32 CONTROLLER INTERFACE
<101>
The controller interface provides a means of communication
between the Controller Module and the 9lS32. The interface stores
information when written to and provides data for the Controller
when called for. Any block in the 9lS32 general block diagram
identified with an asterisk (*) is used by the 9lS32 controller
Interface.
HIGH SPEED ADDRESS BUS BUPFER
<103>
91S32 receives address, data, and clock signals from 9lSl6
Pattern Generator when the 9lS32 Pattern Generator is in Follows
mode. The 9lS32 high-speed address bus buffer latches the
address, data, and clock signals, and sends them to the address
multiplexer block.
<103>
FRBE-RURNING ADDRESS
When no 9lSl6 is present, or when the 9lS32 is operating in
Sequential mode, the free-running address counter generates the
internal vector address and increases the address each time the
clock edge moves from low to high. This result is selected by
the multiplexer and becomes the address for the pattern memory.
LOOP COURTER
<104>
The loop counter stops the free-running address counter if a loop
value has been programmed.
PAGE CONTROLLER
<103>
The page controller changes the page latch status between Page A
and Page B.
CLOCK DISTRIBUTION
<102>
The clock distribution circuit sends the clock to all other 9lS32
functional blocks.
4-11
Theory of Operation
DAB 9100 Series 91S16-91S32 Service
CLOCK
DELAY
<105>
The clock delay selects and adjusts the delayed clock timing
value programmed in the Configuration menu or the Timing menu.
ADDRESS MULTIPLEXER
<103>
The address multiplexer selects a buffered address from the 91516
or from the internal address counter and sends the address to the
vector memory.
RAM
~TE
<104>
The RAM write circuitry determines which page of memory data is
written to, and determines the ECL RAM write timing.
VECTOR RAM
<107>
The vector RAM stores the data pattern. When the pattern
generator is started, the vector RAM sends data to the output
latches.
OU'rPtr.r
LA'l'CBBS ABO DRIVER
<107>
The output latches and driver circuit receives the data from the
memory and sends it out to the P6464 probes.
DATA RBADBACK
<106>
The data readback circuit receives the data pattern and sends it
out to the microprocessor bus.
ADDRESS
RBADBACK
<103>
The address readback circuit receives the A-Page address and
sends it out to the microprocessor bus.
4-12
Theory of Operation
DAS 9100 Series 91516-91532 Service
PROBE INTERFACE
<105>
The probe interface verifies probe attachments and sets the probe
threshold voltages.
PATTERN GENERATION PROBES
There are four P6464 Pattern Generator probes used with the
91532. These probes are attached to connectors labeled POD A
through POD D on the back of the instrument module. Each probe
is capable of generating eight data channels, one clock, and one
strobe signal. The strobe channel can be used as an additional
data channel. The probes can operate at TTL, ECL, or variable
voltage levels.
+3 VOLT POWER SUPPLY
<104>
The +3 volt power supply is a switching current pump bootstrapped
to +5 V. It powers the ECL terminating resisters.
91816 Detailed Circuit Description
OVERVIEW
Refer to the schematics in the Diagrams section of this manual
while reading this detailed circuit description. The numbered
diamonds on the schematic tabs in the Diagrams section are keyed
to numbered diamonds in the detailed circuit descriptions.
Components are identified by a component designation preceded by
an ECB assembly designation.
4-13
Theory of Operation
DAS 9100 Series 91516-91532 Service
FUNCTIONAL BLOCKS
The 9lS16 circuitry is divided into the following functional
blocks:
9lSl6 Controller Interface and ROM---Schematic 92
Pattern Generator Probes
External Control Probe
Probe Interface----------------------Schematics 92 and 94
Probe Receivers--------------------- Schematics 93, 94, and 99
Start In-----------------------------Schematic 93
Clock Control------------------------Schematic 93
Vector and microcode Memory----------Schematic 96
PC Control Multiplexer and Reset-----Schematic 95
Program Counter and Stack------------Schematic 94
Start Setup--------------------------Schematics 94 and 95
Interrupt Logic----------------------Schematic 94
External Signal latches--------------Schematic 94
9lS32 Transceiver--------------------Schematics 93, 94, and 96
Register Control---------------------Schematic 97
Pattern Selector---------------------Schematic 97
First Latches------------------------Schematic 97
Clock Positioning--------------------Schematic 98
Output Latches-----------------------Schematic 98
Trigger Out--------------------------Schematic 98
Clock Line---------------------------Schematic 99
Inhibit Control----------------------Schematic 99
Status Readback----------------------Schematic 100
+3 Volt Power Supply-----------------Schematic 98
CIRCUIT DESCRIPTIONS
91S16 Controller Interface and ROM
<92>
The 9lSl6 controller interface performs two major functions:
1. It takes data from the controller and sends it to appropriate
registers by decoding the lowest four bits on the address bus
and interpreting BWR(L), PORT(L), and BRD(L) from the
controller.
2. It takes data from the module and writes it on the data bus.
4-14
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
Examples of read and write procedures follow.
PROCEDURE. The controller is reading the CARD ID. The
address bus has OOH written in the three LSB positions.
Simultaneously, PORT(L) and BRD(L) are asserted, which enables
Ul12. Ul12 decodes the address, and Ul12-l is asserted (L).
U112-l going low enables CARD ID register U132, putting data on
the data bus.
READ
WRITE PROCEDURE. The write procedure is similar, except that the
BWR(L) and PORT(L) signals must be active to enable decoder Ul18.
See the following table for a listing of register links to the
data bus through signal lines BWR(L), BRD(L), and PORT(L) , and by
hex address.
Hex
Addr
XXOO
XXOO
XXOl
XXOl
XX02
XX02
XX03
XX03
XX04
XX04
XX05
XXOS
XX06
XX06
XX07
XX08
XX09
XXOA
XXOB
XXOC
XXOD
XXOE
XXOF
BWR(L) BRD(L)
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
POR'l'(L) Control Line
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CARD ID (L)
MAP REG(L)
RO ROM(L)
THRESHOLD(L)
DATA CLOCK
PROBE R/W ( L)
STACK RESET (L)
PROBE DATA
RDBACK GATE(L)
ROBACK SEL(L)
OUTPUT CLK
SEL RAM(L)
RS CLK (L)
RAM WE (L)
F-LATCH CLK (L)
SELO(L)
SELl (L)
SEL2 (L)
SEL3 (L)
SEL4(L)
SELS (L)
STEP CLK
PC RESET
Chip Affected
U132
Ul16
U108
U320
P6460,P6464
U130
U4l6-U420
U194
U960
U900
U134,U2l8
U502
U134,U2l8
U422
U134,U302
U804
U806
U808
U8l0
U8l2
U8l4
U206
U4l0-U4l4
Scheme
No.
92
92
92
94
92
95
92
100
100
93
96
93
96
99
99
99
99
99
99
99
93
95
The ROM resident on the 91516 contains the Pattern Generator
menu. There are three 256K-bit EPROMs on the 91S16. Register Ul16
selects which ROM is accessed by the Controller to control the
Pattern Generator menu.
4-15
Theory of Operation
DAB 9100 Series 91S16-91S32 Service
Probe Interface
<92> <94>
The probe interface is functionally divided into two sections:
probe-to-9l5l6 communication, and the probe threshold circuitry.
PROBE-TO-91S16 COMMUNICATION. The 91516 can preset the status of
a probe by sending data to the probe, and can detect it by
reading data from the probe. To do this, the R/W bits in U130 are
set low by writing to port PROBE R/W.
Write Mode. The lower three bits (bit 0-2) in U130 are sent low
by writing to port PROBE R/W. This instructs the probe that the
91516 is going to send the status. The 91516 sends a status bit
to the probe by writing to port PROBE W-DATA (U194). The 91516
then reads to port DATA CLOCK. One bit of data is sent to the
probe. This procedure is repeated as many times as required by
the probes. U130 and U194 read/write status is as follows.
0130
bit
bit
bit
bit
bit
bit
0
1
2
4
5
6
POD
W or R
A
B
C
A
B
C
W
W
W
0194
bit 0
bit 1
bit 2
POD
A
B
C
R
R
R
Read Mode. The upper three bits (bit 4-6) in U130 are sent low by
writing to port PROBE R/Wo This instructs the probe that the
91516 is going to read the status. The 91516 then reads to port
DATA CLOCK. DATA CLOCK is repeated eight times. Each time, a new
status bit is read from each of the three probes. This procedure
is repeated each time the status of the probes is required.
PROBE THRESHOLD CIRCUITRY. Digital-to-analog converter (DAC) U320
has level-setting information written to it by the 91516
controller interface. The threshold voltage required in the
probe is selected by writing to port THRE5HOLD(L). The selected
voltage then appears at U320-l8. The first stage of this circuit
takes the error voltage generated by the user ground and adds it
to the selected threshold voltage. The next stage of this circuit
does two functions:
4-16
Theory of Operation
DAB 9100 Series 91S16-91S32 Service
1.
The error of the offset sense voltage is subtracted from the
selected threshold voltage.
2.
This stage also attenuates the threshold voltage by a
feedback resistor located in the probe and connected between
the threshold voltage line and the threshold sense line.
NOTE
This circuit cannot adjust unless DAC U320 (an NE50l8)
is lot date number 8335 or smaller.
Probe Receivers
<93>
<94>
<99>
The probe receiver acquires the differential ECL output of the
acquisition probe. The resistors attached to these lines are line
terminators to match the impedance of the transmission line. Each
line is run through a delay line and a polarity selector. The
delay line allows the selected clock sufficient time to set up
before clocking data into each latch. The polarity selector can
select a high or low level, or a rising or falling edge for each
line.
Start In
<93>
The START IN signal, which is received via a phono connector, is
converted from TTL level to ECL level through resistors R272,
R274 and R276. U222A is a buffer. Trigger polarity to U704B
determines whether the system start will occur on the rising or
falling edge of the external start signal. When START IN is
disabled, U2l2A-5 is usually low and U2l2A-4 is high. The
start/stop of the 9lSl6 is controlled by the STOP PG(H) signal
received through the DAS interconnect board.
When the 9lSl6 selects the SYSTEM START given by an external
signal, U2l2A-2 is programmed high in the setup program before
the system starts. Once the START SYSTEM key or START PAT GEN key
is pressed, the STOP PG(L) signal goes low. Then the 9lSl6 can
accept an external start signal. The 9lSl6 may start by the
selected transition of this line. Resistors R282, R284, and R286
on the STOP PG line convert the signal from TTL level to ECL
level. U302A is a buffer and U222D is a gate that controls the
STOP PG{L) signal.
4-17
Theory of Operation
DAB 9100 Series 91S16-91S32 Service
Clock Control
<93>
The clocks selected by U206 are 9lA32 INTL CLK(L), 9lA08 INTL
CLK(L), EXT CLK(H), EXT CLK(L), and STEP CLK(L}. The output of
U206-15 is sent to the pause circuit and the stop circuit through
buffer U640C. The 9lS16 may start when both the U2l2-2 (START IN)
and the U302-3 (STOP PG) are low. The external PAUSE signal line
is wire-ORed with the START IN and STOP PG line. When the PAUSE
line becomes high, U208 stops supplying a clock to the stop
circuit. U638B prevents extra clock pulses.
If the PAUSE signal is low, U208 clocks through it on the rising
edge of the selected clock pulse. U2l6B generates a clock pulse
the same pulse width as the selected clock. U208-3 makes a
rising-edge clock pulse by setting U216B. The output of U208-14
is a reset pulse to make the duty cycle of the clock 50% by
resetting U216B. U208-3 goes low whenever the PAUSE signal, the
START IN signal, or the STOP PG signal is high. The output of
U638B-3, which is wire ORed with the PAUSE signal, stops the
clock to prevent extra clock pulses.
The output of register U216B is supplied to U214. Register U214
produces the halt state from the microcode instruction. Register
U214 clocks the HALT(H) line on the rising edge of the selected
clock. When the HALT(H) line is high, the output of U214-3 goes
low and the selected clock is not transferred through register
U214 to buffer U218. The output of U214-l4 is a reset pulse which
establishes the duty cycle of the clock pulse. Comparator U956B
converts the HALT(H) signal from ECL to TTL and sends the status
to the 9lSl6 controller interface. Clock lines are provided for
the system by buffer U218 as follows.
U218-9
U2l8-l5
U218-11
U218-l4
U218-6
U2l8-3
U218-5
U218-2
Reference clock (TP280)
91S32 clock O(L)
Program Counter
RESET CLK(L)
Output clock path
OUT CLK (L)
R CLK
Not Connected
Comparator U212B checks whether a clock is supplied to the system
in the Trace mode.
4-18
Theory of Operation
DAS 9100 Series 91516-91532 Service
Vector and Microcode Memory
<96>
The output vector is loaded in vector RAM U504-U5l0. The vector
is stored in a l6-by-l024 bit format. The microcode is loaded in
the microcode RAM U512-U524, then recalled for decoding into
instructions. The microcode is stored in a 28-by-l024 bit
format. This memory is loaded from the data bus through buffer
U500 with eight bits set. Resistor network R560, R562, R564, and
R566 convert the data from TTL to ECL. The address being loaded
is loaded directly or through buffers U530 and U532 by the
program counter U410-U4l4. The memory being loaded is set by
register U502. RAM content and microcode decoding are shown in
the following tables.
Reg. ( U502
}
24fXlll1l10
24fXll1l10l
24fXllllOll
24fXl1l0lll
24fXl10ll11
24fXlOlllll
24fXOll1ll1
D7
D6
D5
D4
D3
D2
Dl
DO
VB7
VB15
JA7
VB6·
VB14
JA6
VB5
VB13
JA5
VB4
VB12
JA4
VB3
VBl1
JA3
MCI
VB2
VBlO
JA2
MCO
VB1
VB9
JA1
JA9
VBO
VB8
JAO
JA8
MC9
MC13
MC8
MC12
MC7
MCl1
MC6
MCIO
MC5
MC17
MC4
MC16
MC3
MC15
MC2
MC14
MICROCODE DECODING
VMB
Schematic 92
VECTOR
VBO - VB15
JAO - JA9
JUMP ADDRESS
JAB
Schematic 92
MCO-MCl Output selector
MCO
2 8 BIT
0
1
0
1
MC2
MC3
MC4
MC5
MCl
1 16 BIT
0
0
1
1
INSTRUCTION
OUT VECTOR
OUT RA
OUT RB
OUT REPEAT
Inhibit
Inhibit
Strobe
Strobe
A
B
A
B
4-19
OUT VECTOR
OUT REGISTER
Prohibit
OUT REPEAT & VECTOR
.un::uc¥ OJ: uperation
DAB 9100 8eries 91816-91832 Service
MC6-Me9 Program flow control
MC9 MC8 MC7 MC6
a
a
1
a
a
a
1
a
a
a
a
1
1
a
a
1
1
1
1
1
1
1
0
1
0
1
0
0
0
1
1
1
0
0
0
a
a
a
a
a
a
a
0
0
1
1
1
1
:INSTRUCTION
RETURN
JUMP
ADVANCE
IF RB(L)=O
IF RA(L)=O
IF R(L)=O
IF EXT J(L)
IF END (L)
IF FULL(L)
IF KEY (L)
IF IRQ (L)
CALL REMOTE
MC10-MCll Reg. B control
MCll MC10
o
o
o
o
1
1
1
1
LOAD VECTOR INTO RB
INCREMENT RB
DECREMENT RB
HOLD RB
MC12-Me13 Reg. A control
Mel3 MC12
o
o
o
1
1
1
1
LOAD VECTOR INTO RA
INCREMENT RA
DECREMENT RA
HOLD RA
o
MC14
MClS
MCl6
MC17
Next Page
Halt
Trigger OUT
Interrupt mask
4-20
Theory of Operation
DAS 9100 Series 91516-91532 Service
Program Counter (PC) Control Multiplexer and Reset
<95>
Microcodes MC6-MC9 are interpreted by the multiplexer to
determine the next address for the vector memory and the
microcode memory. Instructions controlled by microcode MC6-MC9
are ADVANCE, JUMP, RETURN, IF R=O, IF RA=O, IF RB=O, IF IRQ, IF
KEY, IF EXT J and IF LOAD.
If microcode MC6-MC9 are all zero, both U432-2 and U406-8 are
low. This specifies that the PC may load the output of the stack
(Return Address) through multiplexers U400, U402 and U404.
Microcodes MC6, MC8, and MC9 also are interpreted by the decoder
U408 to generate the reset signals FULL(L}, KEY{L}, IRQ(L), and
the 91532 control signal KA(L). The output (L) of U8l4 makes the
external signal latches go to the initial state after these
instructions are executed.
Program Counter and Stack
<95>
The output of U406-8 controls the program counter U4l0-U414 and
stack U416-U420. When U406-8 is high, the program counter and
stack are counted up on the positive going edge of PC CLOCK (H) •
When it is low, they may load a 10-bit jump address from
microcode memory on the positive-going edge of the clock.
When the 91516 accepts the external interrupt signal in the IRQ
CALL mode, the interrupt logic applies an interrupt pulse to the
reset pin 12 of program counter (PC) U4l0, U4l2, and U414. The PC
accepts an interrupt pulse on the positive going edge of a clock.
The address of the PC output for the vector and microcode memory
is OOH. Then, the first line of an interrupt subroutine is
written at address OOH. U4l4-l4 is usually high. But when the
91516 receives an interrupt, U414-l4 goes to LOW and sets the
stack to a holding state through U3l6C (schematic 94).
When accepting an inter rupt, the 'stack clocks according to the
output of U406-6. After the interrupt is accepted, the stack
goes to the holding state, and does not obey the output of U406,
until the microcode memory provides a RETURN instruction. The
RETURN instruction terminates the holding state, and U414-14 goes
high.
4-21
Theory of Operation
DAS 9100 Series 91516-91532 Service
Start Setup
<94> <95>
03l4A is used when the 91516 starts from SEQOENCE O. A clock is
sent to all circuits, but the PC, stack, and internal registers A
and B work from a second clock. Before the pattern generator
starts, 03l4A is set by the controller not to send a first clock
to those registers. 03l4A is reset by the clock and provides a
half cycle delay after the 9lSl6 starts. An interrupt signal is
disabled by 03l4B when the 9lSl6 is in a halt state. When the
9lSl6 stops, the HALT (H) signal is clocked through resister 03l4B
and the QOALIFY(H) line is set low. This inhibits register 0308
from again passing an interrupt signal.
Interrupt Logic
<94>
The interrupt logic accepts the external interrupt signal, clocks
it through a register, and applies a reset pulse to the program
counter. The interrupt logic accepts two external signals,
QUALIFY (H) and INTERROPT(H). Receiver U300A and B acquires the
differential ECL output of the acquisition probes. 0200A
establishes a logic level to qualify the acquisition of the
interrupt signal. 02000 determines the positive-going or
negative-going edge of the interrupt signal to be accepted by the
interrupt logic.
0820A is the gate of the QOALIFY(H) signal. When the 9lSl6 is in
a halt state, 0314-14 is low and the interrupt logic does not
acquire an interrupt signal. 0324A controls whether QUALIFY is
enabled or disabled. The enabled QOALIFY means that an acceptance
of the interrupt signal may be qualified by the external signal.
The disabled QOALIFY means that the interrupt logic may usually
acquire an interrupt signal. When a qualify line is programmed
with an interrupt mask (MC17), gate 0332C goes low.
0308 is the first latch for an interrupt. A qualify signal enters
U308-7,10 and an interrupt signal enters 0308-9. If 0308 acquires
an interrupt signal when the qualify line is high, both U308-2
and 0308-15 may go high. 0308-15 is the output for the IF IRQ
instruction. The INT(H) signal is clocked through register
U306A. The high output of U306A-2 resets program counter 0410U4l4 as an interrupt, and 0414-15 goes low. The output of 0414-14
resets latch 0308A through buffers U3l6A and 03l6C.
The output of 0414-14 is also sent to 0306B as a clock through
gate U3l6C and generates the STACK HOLD SIGNAL(H} signal. This
also resets register U306A. The output at 0306-2 goes low and
produces an interrupt pulse. Latch U308 can receive the next
interrupt signal. Register 0306-14 goes low, allowing 03l0A to
accept a RETORN signal. When a RETURN instruction is executed,
the RETURN (H) signal is clocked through register 0310A and resets
register U306B. The output of U306-14 resets 0310A. Then U3l0A-2
produces a reset pulse for the stack holding circuit. The stack
4-22
Theory of Operation
DAB 9100 Series 91S16-91S32 Service
is released from the holding state and again works the same as
the program counter. The MPU resets the PC athrough US02A.
External Signal Latches
<94> <95>
IF EXT J. U200C (Schematic 93) selects a logic level for the IF
EXTJ instruction. The EXT (H) signal is clocked through register
U212B on the positive-going edge of the clock and is applied to
instruction multiplexer U406.
INTERRUPT MASK(MC17). When the INT MSK(H) signal (an interrupt
mask from microcode RAM) is clocked through register U330A and
sent to gate U332C, latch U30SA cannot accept an interrupt signal
for the duration of one cycle.
IF IRQ. The IRQ (H) signal, which is acquired when the qualify
signal is high, is clocked through register U310B. The output of
U310-14 is sent to register U330B through buffer U302 and the
multiplexer U406. Register U310B holds an IRQ signal until the
IRQ instruction is performed. The IF IRQ(L) signal is wire ORed
with IRQ RESET(L) (the output of U40S-11). When both IF IRQ(L)
and IRQ RESET(L) are low, the IF IRQ instruction is executed,
U330B generates a reset pulse and sends it to registers U310B and
U30S. U3l0B and U30SB are cleared via gate U332D by the
controller when a START key is pressed.
IF KEY. The input of U312-l0 is low and U3l2-l5 is high. When
U3l2-ll receives a key clock from the controller, the output of
U3l2-l5 goes low and is clocked to the multiplexer U406 via
U232B. The IF KEY(L) signal through buffer U302 is wire-ORed
with the KEY RESET(L) signal. When both IF KEY(L) and KEY
RESET(L) are low (which mean this instruction is executed), U304A
generates a reset pulse and both U312-15 and U232-l5 go high.
IF FULL. The IF FULL logic is almost identical with the IF KEY
procedure. But the signals which are wire-ORed are the IF FULL(L)
and FULL RESET(L) signals, and are sent to the 91S32 module
through driver U230A. U304BA produces a reset pulse and resets
register U216A also. All registers used in IF KEY and IF FULL
are reset by the controller through gates U332A and B.
CALL REMOrE. The KEEP-ALIVE(L) signal, which is given by decoder
U40S-10, is clocked through register U2l6A and is converted from
EeL to TTL by U956A. This signal specifies that the 91Sl6 and
9lS32 may enter into the keep alive mode.
4-23
'~'neory of Operation
DAS 9100 Series 91S16-91S32 Service
IF END. This instruction is used in the keep-alive mode. When the
controller receives the end-of-message terminator through GPIB or
RS232C, the controller signals the 9lSl6 by way of U334A, and the
9lSl6 goes out of the keep-alive mode.
Register Control
<97>
The 9lSl6 has two 8-bit counters or one l6-bit counter, either of
which can count up, count down, hold, and preset. This is
controlled by microcode. When the input of U638-5 is low, this
circuit can operate as two 8-bit counters. When U638-5 is high,
it can operate as one l6-bit counter. Register A consists of U600
and U602. Register B is U604 and U606. When the Sl and 52 of
each counter are simultaneously low, these counters may load the
vector. The following list shows the modes controlled by 51 and
52.
Sl S2
Operating mode
Load vector
Count up
H L Count down
H H Hold
L
L
L
H
When the 8-bit counter mode is selected, Both register A and
register B may load VBO-VB7 on the positive-going edge of REG
CLK(H). In the l6-bit counter mode, register A loads VBO-VB7 and
register B loads VB8-VBIS through multiplexers U608 and U6l0.
U640B is used as the start setup gate to start at an initial
state. The output of registers A and B are sent to the zerojudging circuit. The zero-judging circuitry checks whether the
outputs of the registers are all low. The zero-judging circuit
consists of gates U626, U628, and U640A. The zero-judging
outputs are sent to the instruction multiplexer.
4-24
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
91S32 Transceiver
<93>
<94>
<96>
The controller can select the master-slave mode between the 9lSl6
and the 9lS32. The outputs of PC are sent to the 9lS32 through
drivers U426, U428, and U430. The following signals are sent to
the 9lS32.
Signal
Driver
R~e
9lS32 Clock
Output of PC U426
Next Page
FULL
EXT INHIBIT
Schematic
U230C
U428 and U430
U430A
U230A
U430C
93
96
96
94
99
The NEXT PAGE(H) signal, provided from microcode RAM U524-22,
tells the 9lS32 to change a page. The FULL(H) signal, from pin 2
of register U3l2, tells the 9lS32 to exchange the memory bank. It
is asserted when the controller sets the output of register
U3l2B-15 low and the IF FULL instruction is executed. See the
External Signal Latches description which appears earlier in
this discussion.
The EXT INHIBIT (H) signal is sent as an external inhibit signal
to the 9lS32. The polarity of the external inhibit signal is
selected by U800A. The 9lS32 clock has three clock types which
are divided by 1, 2, or 4 (Schematic 93). A reset pulse is sent
to U250-4 and U250-l2 to insure proper phase of clocks at U230C
pins 14 and 15. U250A makes a 1/2 clock and U250B makes a 1/4
clock. Clock division coding is shown in the following table.
U218-13
U250-13
L
H
H
H
H
L
Pattern Selector
U422-13
H
L
H
Clock Division
1/1 clock
1/2 clock
1/4 clock
<97>
The pattern selector determines which pattern is generated at POD
A and POD B. The pattern output is selected from the vector
memory, register, or the output of the first latch by microcode.
U6l6 through U622 select the pattern generated at POD A.
U6l2
and U6l4 select the pattern generated at POD B.
4-25
rneory of Operation
DAS 9100 Series 91S16-91S32 Service
The pattern generated at POD A is selected by microcode. When the
91Sl6 selects two S-bit registers, the pattern generated at POD B
is VBS-VB1S because the output of U3l6-l4 is high. When both
MCO(H) and MC1(H) are high, the pattern generated at POD A is
selected at the output of the first latches. See the following
tables for microcode pattern selection.
8 bit register mode
Microcode Pattern Out
MCO(B)
Mel (B)
POD A
L
VBO-VB
Output of Reg. A
Output of Reg. B
Output of latch
L
L
H
H
H
L
H
POD B
VBS-VBlS
VBS-VBlS
VBS-VBlS
VBS-VBIS
When one 16-bit register is selected, the output of U3l6-l4 goes
low , and multiplexers U6l2 and U6l4 are controlled by the output
of U224-l2.
16 bit register mode, Microcode Pattern Out
MCO(B)
L
L
H
H
Mel (B)
L
H
L
H
POD A
VBO-VB7
Output of Reg. A
Prohibit
Output of latch
POD B
VBS-VBlS
Output of Reg. B
Prohibit
VBS - VBlS
US32A and US32F are used when the controller reads the output of
the register in the trace mode.
First Latches
<97>
The first latches (U632, U634, and U636) act as registers,
clocking through the value from the output selector. This adjusts
the data channel skew for making POD clock edge positioning.
While pins 4 and 13 of U630 are high, the internal INHIBIT
instruction is disabled.
Clock Positioning
<98>
Each POD clock may be positioned in a -S ns to +S ns range in
S ns steps. Each delay line DL760, DL7S0, introduces S ns
4-26
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
delay, including the gate delay. The POD clock is sent to the
probe through the drivers U7l4A and U7l4B, and is provided to the
registers through buffer U700 or U702. Clock positioning is
shown in the following table.
POD A DLAO(L), DLAl(L), DLA2(L) Delay Time
POD B
L
H
H
H
DLBO (L)
DLBl(L)
H
H
L
H
H
L
H
H
DLB2(L)
-5 ns
o ns
+5 ns
No output
CLOCK SENSE. In the trace mode, the clock sense circuit checks
whether a clock is provided to the last latch or the probes. The
output of U702-15 is sent to flip-flop U7l6A-6 (Schematic 93). If
U716A receives a clock, the level at U716-2 (Schematic 93) is
changed. The controller reads it via comparator U954B.
Output Latches
<98>
The output latches operate as a register, clocking through
vectors from the first latch by each POD clock. The outputs of
registers U706 through U7l2 are sent through connectors to the
pattern generator probes with the differential ECL output while
the OUT LATCH CLK line is low.
Trigger Out
<98>
U716B clocks through microcode MC16 (H) from the microcode RAM.
The output of U716-15 is converted from ECL to TTL by transistors
0720 and 0722 and is sent to phono connector J180 through
buffers U222B and C.
Clock Line
<99>
Delays inserted into each line allow the selected clock
sufficient time to be set up before clocking the vector and
microcode into each register. DL820 is the delay line adjusting
the delay time to the output system. The delay time to the first
latch is adjusted by DL800. The F LATCH CLK(H) signal is a step
clock from address decoder U1l2 (Schematic 92) to the first latch
(U630A). This clock is used when the controller reads the
contents of memory. The delay time to the output latch is
adjusted by DL700 (Schematic 98).
4-27
4uevJ.X VL uperat10n
DAS 9100 Series 91S16-91532 Service
Inhibit Control
<99>
U820B and U8200 turn the external inhibit on or off. The outputs
of gates U820B and U8200 are wire-ORed with the internal inhibit
line. An internal inhibit accepts the logical ANO/OR with the
external inhibit line by setting the exclusive-OR gates U800A,
U8000, U224B and U224C (Schematic 96). An inhibit signal is sent
to the probe through the exclusive-OR gate. Each channel in the
probe can be inhibited (tristate) by ANDing it with a probe
inhibit control. An internal inhibit is disabled by U630
(Schematic 97). See the following list for inhibit function
coding.
<96>
U2245,7
L
H
L
X
X
H
H
L
L
L
L
H
H
<99>
U8005,14
<99>
U800-9
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
Status Readback
X
H
<99>
U8206,12
L
L
L
H
H
H
H
L
H
H
H
L
L
H
H
H
L
H
L
H
H
H
<97>
U6304,13
H
L
L
H
H
L
L
L
L
L
L
L
L
Inhibit
Function
Disable
Internal 0 only
Internal 1 only
External 0 only
External 1 only
Int 0 or Ext 0
Int 0 or Ext 1
Int 1 or Ext 0
Int 1 or Ext 1
Int 0 and Ext 0
Int 0 and Ext 1
Int 1 and Ext 0
Int 1 and Ext 1
<100>
This circuit divides the data from the system into 8-bit words
for transfer to the controller. Comparators U902 through U958
convert data from ECL level to TTL level. Register U900
determines which 8-bit information is read. Resistor arrays R940
and R942 establish the EeL threshold level. The following tables
show status readback position and readback information.
4-28
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
Readback Position
*
Vector
Memory
Vector, Strobe, Inhibit
--->
First Output
Latch ---> Latch
I
--> Comparator --> Controller
*
JAO-JA9, MCO-MC1, MC6-MC17
Microcode
Gates or
memory ---> Latches
I
--> Comparator --> Controller
Readback Information <100>
PORT Content Read Infomation
RBADBACK SEL Bit
( 16104 )
01
02
04
08
10
20
40
80
When 16#05
00
7
6
VB7
VBls
JA7
MC9
MC13
VB6
VB14
JA6
MC8
MC12
PC7
PC6
5
4
3
VB5
VB4
VB3
VB13
JAs
MC7
MCII
lBO
PCs
VB12
JA4
MC6
MClO
lAO
PC4
VBll
JA3
MCI
MCs
MC17
PC3
2
1
o
VB2
VBlO
JA2
MCO
MC4
MC16
PC2
A/J
VBl
VB9
JAI
JA9
MC3
MCls
PCl
PC9
VB8
JAO
JA8
MC2
MC14
PCO
PC8
VBO
= 2#lXXXXXXX
C.O.
IBO
Internal Inhibit Output at POD B
lAO
Internal Inhibit Output at POD A
C.O. : COUNT OVER (The PC out is out of range)
Clk
Check a clock
K.A.
go to a Keep Alive
A/J
Advance/Jump
4-29
Halt Clk
K.A.
Tneory of Operation
DAS 9100 Series 91S16-91S32 Service
+3 Volt Power Supply
<98>
The +3 volt power supply generates the voltage for the ECL
terminating resistors. It consists of a +3 V switching current
pump. The +3 V power supply disposes of surplus current to keep
the supply at 3 V. This supply disposes of the surplus current
by bootstrapping it into the +5 volt supply. Resistors R958,
R960, and R964 form a voltage divider to give a +3 V reference to
comparator U980B. The non-inverting pin of the comparator is
connected to the +3 V line through R954.
Whenever the +3 V line goes over-voltage, the output of
comparator U980B goes high. This turns on Q950 and turns off
Q952. This in turn raises the base voltage at Q954, the side of
L952 tied to Q954 is pulled to ground, and current flows from the
+3 V supply into L952.
Because of the inductance of L952, most of the current drawn is
stored in the magnetic field of the inductor rather than going
through Q954 to ground. When inductor L952 has drawn enough
current, the +3 V line drops below the reference voltage. This
reverses the above procedure, making Q954 not conduct. When Q954
stops conducting, L952 stops drawing current from the +3 V
supply. However, there is still a magnetic field around L952 that
stores the energy previously pulled out of the +3 V supply.
The magnetic field around L952 starts to collapse when Q954 stops
conducting, so L952 is forced to dissipate as much power as it
absorbed from the +3 V supply. L952 forces out a pulse of current
at +5 V which goes through CR960 into the +5 V supply. L954 evens
out the current spikes coming through CR960.
Comparator U980 works as an over-current sensor by monitoring the
voltage across R952. If Q954 is conducting too much of the time,
the current through L952 will become great enough to activate
this comparator and shut down Q954.
4-30
Theory of Operation
DAS 9100 Series 91516-91532 Service
91532 Detailed Circuit Description
OVERVIEW
Refer to schematics in the Diagrams section of this addendum
while reading this detailed circuit description.
FUNCTIONAL BLOCKS
The 91532 circuitry is divided into the following functional
blocks.
91532 Controller Interface------------Schematic
High-Speed Address Bus Buffer---------Schematic
Free-Running address counter----------Schematic
Loop Counter--------------------------Schematic
Page Controller-----------------------Schematic
Clock Distribution--------------------Schematic
Clock Delay---------------------------Schematic
Address Multiplexer-------------------Schematic
RAM Write-----------------------------Schematic
Vector RAM----------------------------Schematic
Output Latches and Driver-------------Schematic
Data Readback-------------------------Schematic
Address Readback----------------------Schematic
Probe Interface-----------------------Schematic
Pattern Generator Probes
+3 Volt Power Supply------------------Schematic
101
103
103
104
103
102
105
103
104
107
107
106
103
105
104
CIRCUIT DESCRIPTIONS
91532 Controller Interface
<101>
The 9lS32 controller interface performs two major functions.
1. It takes data from the Controller board and sends it to
appropriate registers by decoding the lowest five bits on the
address bus and interpreting BWR{L), BPORT{L), and BRD(L)
signals issued by the Controller board.
2. It takes data from the module and writes it on the data bus at
the command of the Controller board.
4-31
----.J _.
V~C~Q~~an
DAS 9100 Series 91S16-91S32 Service
Examples of read and write procedures follow.
READ EXAMPLE. The DAS Controller Board is reading the card ID.
The address bus has 0 (hex) written in the four least
significant bit positions. Simultaneously, PORT(L) and BRD(L) are
asserted, which enables U11S. UllS decodes the address, and U11S4 is asserted (L). Ul1S-4 going low enables the CARD IO register,
U122, which put the card I.D. data on the data bus.
WRITE EXAMPLE. The write procedure is similar, except that the
BWR(L) and PORT(L) signals must be active to enable decoders
U106.
The following table is a list of register links to the data bus
through signal lines BWR(L), BRD(L}, and PORT(L), and by
hexadecimal address.
91832
Hex
Addr
XXOO
XXOO
XXOl
XXOl
XX02
XX02'
xx03
XX03
XX04
XX05
XX06
XX07
XX08
XX09
XXOA
XXOB
XXOC
XXOD
XXOE
XXOF
BRW(L)
BRD(L)
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CO~ROLLER I~RFACE MAP
H
a
a
a
a
a
a
a
H
H
H
H
H
Control
Line
PORT(L)
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CARD IO(L)
MAP REG(L)
POD STATUS(L)
SPARE
DATA CLOCK
PROBE R/W(L)
ROB (L)
PROBE DATA(L)
MPUCLK
MWEM(L)
WP(L)
PORT7(L)
PORTS (L)
PORT9 (L)
PORTA(L)
PORTB (L)
PORTC (L)
PORTO{L)
PAGB (H)
PAGA (a)
4-32
ICs
Affected
ScbelD
U122
U206
U120
101
102
101
P6464
U5l6
U650
U520
U216
U40S
U400
U104
Ul12
U302
U3l4
U512
U5l4
U72S
U34S
U348
105
106
105
102
104
104
101
101
103
103
105
105
101
103
103
Theory of Operation
DAS 9100 Series 91516-91532 Service
High Speed Address Bus Buffer
<103>
U300, U308, and U3l2 receive the address and clock from the 91516
Pattern Generator over the 40-wire flat cable.
The high speed
address bus buffer is only used when the 91532 is in Follows mode
with a 91516 installed.
Free-Running Address Counter
<103>
This circuit controls the vector address of the 91532 except when
the 91532 is in Follows mode in conjunction with a 91516. U304,
U3l6, U330, and U340 generates the internal vector address. When
the address comes to full value (7FF), the data stored in U302
and U3l4 is loaded into the loop counter. When the MPU writes the
address to this counter, U3l4-l5 should be low and U350 AND-GATEs
are all off, and counter ICs parallel-load enables are all low.
The MPU writes the address into the U302 & U3l4 and sends the
load clock to these ICs. The following tables show how vector
loop values are set.
VECTOR LOOP VALUE SET
Port no.
bit
vector address depth
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
09
09
09
09
09
09
09
09
OA
OA
OA
5
6
7
8
9
10
OTHER PORT OA CONTROL BITS
Bit
3
4
5
6
7
Function
On or Off
Spare
Spare
Self Load
Internal Clock Output Control
SEQ/FOLLOW
4-33
O:off
l:on
O:on
l:off
O:follow l:seq
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
Loop Counter
<104>
U406, U4l2, U4l4, and U4l6 count the loop value. The 9lS32
controller interface loads the loop value to these counters using
WEA(L) and WEB(L). While the 9lS32 is in the Run mode, LOOP
COUNT(L} comes the vector address counter, the loop counter
counts up, reaches terminal count, then U4lS-l0 goes to high and
latches the stop signal. The output U4lSB-15 stops the clock
circuit U2l4 flip-flop.
Page Controller
<103>
This circuit switches between Follows mode and Sequential mode.
U32S-A, U32S-B, U32S-C,U33S-A, and U346-A become active in
Follows mode. U352-C, U33S-B, U33S-C, and U33S-D become active
during the Page mode.
Page A locations: 0000-1023
Page B locations: 1024-2047
Clock Distribution
<102>
U20S and U2l6B and C select one of three clocks 91AOS INTLCLK(L),
PGEXTCLK(L), and MPUCLK(L). U2l6-A controls PGEXTPAU5E(H). U2lSA
and B, U224A and B, and U2l0B distribute the clock to the address
loop counter, page latch, delay lines, and output latches. There
are several modes in which to send the clock to each block. When
9l532s are used with a 9lSl6, each 91532 receives its clock from
the 9lSl6.
In the Follows 9lSl6 mode, NOR gate U224B sends the clock signal
to the output latches. NOR gate U2l0B sends the clock to the
address counter. The page latch receives the clock directly from
U220A.
In the Sequential mode, U2lSB sends the clock to the vector
address counter, delay lines, and output latches.
When only 9l532s are installed, one of the 9l532s becomes the
master and the others become slaves. The master 9lS32~s U2l0D,
U22SA, and U22SB send the selected clock to the slave 9lS32s. The
slave 9l532's U220B and U224A receive the clock and send the
clock to the vector address counter, delay lines, and output
latches. In the setup mode, U2lSA sends the clock to the latches.
P204 and P206 are the termination resistors for the clock from
the master 91532. P200 and P202 are the termination resistor
straps for the clock from the 91516. Straps to P200 and P202 are
installed only on the 91532 furthest from the 91516.
4-34
Theory of Operation
DAB 9100 Series 9lSl6-91S32 Service
Clock Delay
<105>
This block consists of delay lines and gates. The output latches
and buffer clock are delayed by the delay lines OL140, OL160,
OL180, OL200, and OL220 and selected by the gate consisting of
U500, U502, U504, and U506. Using this delayed clock, flip-flops
U640, U642, U644, U646, U720, U722, U724, and U726 load the
vector data. The following tables show delay timing control.
9lS32 CLOCK LINE DBLAY
Probe
POD
A
A
A
B
B
B
C
C
C
0
0
0
Delay
Value
Write'OB
01234567
Write'OC
01234567
5
0
-5
5
0
-5
5
0
-5
5
0
-5
OllXXXXX
101XXXXX
110XXXXX
XXXOllXX
XXXlOlXX
XXXllOXX
XXXXXXOI
XXXXXXIO
XXXXXXll
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
lXXXXXXX
lXXXXXXX
OXXXXXXX
XOllXXXX
XlOlXXXX
XllOXXXX
n
n
n
n
n
n
n
n
n
n
n
n
X: this bit not affected.
O'lBBR POR'.r OC COR'l'ROL BITS
Bit
4
5
6
7
Punction
Stut:us
Card Select
Stop pg line
SYSTEM CLOCK
Internal Clock Input Control
Address Multiplexer
0:S16
O:on
O:on
O:on
1:S32
l:off
l:off
l:off
<103>
U306, U3l0, U3l8, U324, and U332 receive the address either from
the 91Sl6 or from the internal address counter described earlier.
These data are used to provide the A-block and B-block memory
addresses.
4-35
-~-~~I
VL
vperaC10n
DAS 9100 Series 91516-91532 Service
RAM Write
<104>
U402 and U4l0 select the vector memory address block; either chip
can write to the memory block for Page A or Page B. U400
determines the write channel block. When one of U400's output
channel changes low, MWRM(L) becomes effective. This signal, and
MODEA(L) or MODEB(L), are ANOed in U402 or U100 to produce write
enable.
Vector RAM
107>
U700 through U7l8 comprise a 1024 x 4-bit random access memory.
When WE{L) input level is low, all data outputs are in a highimpedance state (tri-stated). When the outputs are tri-stated,
the MPU writes the pattern data to the memory.
Output Latches and Driver
<107>
The data from the memory is clocked into this block and the data
is converted to differential data and sent out to the P6464
probe.
Data Read Back
<106>
The data readback circuit receives the memory data; readback is
determined by the value of Ul12 output data. Comparators U620,
U622, U624, U626, U628, U630, U632, U634, U636, U638, U652, U654,
U656, U658, U660, U662, U664, U666, U668, and U670 take data from
the memory data output of channels 0 to 31, strobe and inhibit,
convert it from ECL to TTL, and write it on the ROBO-RDB7 bus to
the 91S32 controller interface. The output from the comparator is
divided into five 8-bit bytes. Each corresponding bit in the
five bytes is wire-ORed. Readback bytes are selected by RDO(H),
RDl(H), RD2(H), RD3(H) and R04(H), causing the selected byte to
output data and the non-selected byte to output zeros (go to a
high-impedance state).
Address Readback
<103>
The address readback circuit receives A-block memory and status.
Comparators U320, U326, U334, and U344 take data from the address
output of RAOA to RA9A, SELINH(L), PAGE-A/B, HALFCK,
START/STOP (H) , and LSTOPM(L), convert it from ECL to TTL, and
write it on the RDBO-RDB7 bus to the 9lS32 controller interface.
The readback port and the sequence is the same as the data read.
4-36
Theory of Operation
DAS 9100 5eries 91516-91532 5ervice
Probe Interface
<105>
The 91532 can detect the status of a probe by reading data from
the probe. The 91532 reads back one data line from each probe to
determine the status. To do this, the four 91532 read bits in
U516 are sent low by writing low to PORT(L). The 91532 then reads
DATA CLOCK from the POD 5TATU5{L) port. When the 91532 sends DATA
CLOCK (H) to read the next probe status, a new status bit can be
read from each of the four probes. This procedure is repeated
each time the status of the 91532 probes is required.
The 91532 writes one bit to each probe to set up the pattern
generator probe. To do this, the four 91532 write bits in U516
are sent low by writing to PROBE WRITE. The 91532 then writes to
port PROBE DATA (port 03) and sends DATA CLOCK (H) • This instructs
the probe that the 91532 is going to write the status. Each time,
a new setting data bit can be written to the probe.
Pattern Generator Probes
The P6464 ECL/TTL Pattern Generator Probe is used by the 91516
and the 91532 Pattern Generator modules. The probe puts out 10
channels of data at ECL and TTL logic levels. The output levels
of the probe (Vout) are set by the voltages present at the probe
input~s VH (high output level) and VL (low output level).
+3 Volt Power Supply
<104>
The +3 volt power supply is used for biasing ECL circuits on the
91532. 5ince +3 V is not supplied by the power supplies, it is
created on the module by this +3 V switching current pump.
In ECL circuitry, the +3 V biasing supply tends to float up to
+4 V. The +3 V supply must then dispose of surplus current to
keep the supply at +3 V. This supply disposes of the surplus
current by bootstrapping it into the +5 V supply. The +5 V Power
Supply Module that is driving the 91532 then adjusts for
the extra current to maintain the +5 V regulation.
Resistors R216, R214, and R230 form a voltage divider to give a
+3 V reference to comparator U222B. The noninverting pin of the
comparator is connected to the +3 V line through R210. Whenever
the +3 V line goes over-voltage, the output of comparator U222B
goes high which turns on Q200 and turns off Q202. This, in turn,
raises the base voltage at Q204, so the side of L202 tied to Q204
is pulled to ground.
4-37
Theory of Operation
DAS 9100 Series 91S16-91S32 Service
When the side of L202 that is attached to Q204 is pulled to
ground, current flows from the +3 V supply into L202. Because of
the inductance of L202, most of the current drawn is stored in
the magnetic field of the inductor rather than going through Q204
to ground.
When inductor L202 has drawn enough current, the +3 V line drops
below the reference voltage. This reverses the above procedure,
making Q204 not conduct. When Q204 stops conducting, L202 stops
drawing current from the +3 V supply. However, there is still a
magnetic field around L202 that stores the energy previously
pulled out of the +3 V supply.
The magnetic field around L202 starts to collapse when Q204 stops
conducting, so L202 is forced to dissipate as much power as it
absorbed from the +3 V supply. The only place that the power can
be dissipated is through CR200 into L204. The result is that L202
forces out a pulse of current at +5 V which goes through CR200
into the +5 V supply. L204 evens out the current spikes coming
through CR200 to ease regulation of the +5 V supply.
Comparator U222A works as an over-current sensor by monitoring
the voltage across R220. If Q204 is conducting too much of the
time, the current through L202 will become great enough to
activate this comparator and shut down Q204. The only place that
the power can be dissipated is through CR200 into L204. The
result is that L202 forces out a pulse of current at +5 V which
goes through CR200 into the +5 V supply.
4-38
Section 5
VERIFICATION AND ADJUS'l'MElIT PROCEDURES
Introduction
This section contains three main parts: functional check
procedures, adjustment procedures, and probe check procedures.
These procedures allow a qualified technician to verify the
operation of a 91Sl6 or 91S32 Pattern Generator module, to adjust
variables to achieve the proper performance.
A diagram showing the locations of components is located in the
Diagrams section of this addendum.
FtJRCTIOJIAL CHECK PROCEDURES
These tests verify that the device being tested is operational.
The procedures exercise the main user interfaces of the device to
verify their operation. They also verify that the main internal
features are operating. These tests determine whether adjustment
or repair is necessary.
ADJUS'l'MElIT PROCEDURES
These adjustments bring the device being adjusted to meet, or
exceed, product specifications. If the device cannot meet the
specifications given in this addendum after adjustment, repair is
necessary.
~
Verify installation of up-graded +5 V Power Supplies in
your DAS mainframe before performing any of the
procedures in this section. A verification procedure
is provided at the end of this section.
5-1
Verif. & Adj. Procedures
DAB 9100 Series 91S16-91S32 Service
Test Setup Information
SUGGESTED TEST INSTRUMENTS
The following test instruments and accessories are required for
the functional checks and adjustment procedures provided in this
section of the addendum. Unless otherwise specified, equivalent
equipment may be substituted for the recommended type.
ROTE
Each procedure uses only some of the equipment given in
these tables. Check the required equipment for each
procedure before appropriating test equipment for that
procedure.
Equipment Required for the Functional Checks
DAS Mainframe with VI.ll firmware and a 22 A +5
no substitute
V
Power Supply,
9lA08 Data Acquisition Module, no substitute
P6452 Data Acquisition Probe, Tektronix PIN 010-6452-01, no
substitute
P6454 100 MHz Clock Probe, Tektronix PIN 010-6454-01, no
substitute
Service Maintenance Kit, Tektronix PIN 067-0980-00, no
substitute
Oscilloscope, Dual Trace, 300 MHz, with probes, Tektronix 2465
or equivalent.
TM500 Series Mainframe (TM503 or higher)
Digital Multimeter, 0.05% dc
equivalent
V
Accuracy, Tektronix DM50lA or
Pulse Generator, 100 MHz, Tektronix PG502 or equivalent
BNC-PHONO Cable, 79 inches long, Tektronix PIN 176-8165-00 or
equivalent
+5
V
Power Supply, Tektronix PS503 or equivalent
Four flying lead sets pin 131-2230-00 or equivalent
Two capacitors, 1 uF, pin 290-0891-00 or equivalent
5-2
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
Equipment Required for the DAC Threshold Adjustment
TM500 Mainframe
TM503 or higher
Digital Multimeter
0.05% dc V Accuracy
DM501
*Threshold Fixture
*This is the same fixture used as a service tool for the
Tektronix 1240 Logic Analyzer. If you have the l24a fixture,
it is not necessary to build another one. If you do not have
one, refer to the construction procedure at the beginning of
the Adjustments subsection.
Equipment Required for Threshold Pixture Construction
Qty.
Description
Part Number
1
Terminal Connector Holder
(2 holes-by-8 holes)
352-0484-00
5
Mini PV Female Connectors
131-0484-00
1
Resistor, 10.5 Kohm, 1%
321-0291-00
3
Wires, 26-guage, I-inch
long
Equipment Required for the Delay Adjustments
DAS 9100 Series Mainframe
DAS Main Extender Board
350 MHz oscilloscope with two channels
Two P6230 probes for the oscilloscope
Probe Power Supply
Alignment tool, pin 003-1134-00
Four flying lead sets pin 131-2230-00 or equivalent
Two capacitors, 1 uF, pin 290-0891-00 or equivalent
5-3
verif. & Adj. Procedures
DAS 9100 Series 91516-91S32 Service
91816, P6464, and P6460 Punctiona1 Check
This subsection contains functional check procedures for the
91S16 with P6464 and P6460 probes. This procedure allows a
qualified technician to verify the operation of the 91Sl6 module
and a P6464 or P6460 probe.
These instructions are limited to the procedures necessary to
verify the modules. Detailed information about normal menu
operation may be found in the first three sections of this
addendum, and in the DAS 9100 Series Operator~s Manual. Detailed
information about diagnostic menu operation is located in the DAS
9100 Series Service Manual.
---
5-4
Verif. & Adj. Procedures
DAS 9100 Series 91516-91532 Service
91516 Functional Check
This procedure verifies the pattern generation capabilities of
the 91S16.
You will need the following equipment to perform this procedure:
1 1
1
2
1
1
2
1
1
1
1
1
1
1
DAS 9100 Mainframe with V1.l1 firmware and:
- 22 A, +5V Power Supply in a position to power slot 1
- 9lSl6 Pattern Generator Module in slot 1
- P6464 Pattern Generation Probe
- P6460 Data Acquisition Probe
- 91A08 Data Acquisition Module in slot 6
- P6452 Data Acquisition Probe
- P6454 100MHz Clock Probe kit
- 300 MHz dual-trace oscilloscope with P6230 probes
- TM500 mainframe
- digital multimeter
- variable power supply
- 100 MHz pulse generator
- +5 V external power supply
Refer to Section 3, Operating Instructions in this addendum for
instructions on module installation.
Mainfra.e Setup for the Functional Check
The following steps configure the DAS for the functional check.
1.
Turn off the mainframe.
2.
Install the 91S16 in slot 1 and the 91A08 in slot 6.
that slot 1 is powered by the 22 A, +5 V supply.
3.
Turn on the mainframe.
Ensure
(1) Executing the Diagnostic Self Test
Use the following procedure to enter the DAS Diagnostics menu and
operate the ALL mode tests for each level.
1.
Turn off the mainframe. Turn on the mainframe while holding
down the STOP key on the keyboard. This causes the power-up
self test to fail.
2.
Press START SYSTEM to enter the Diagnostics menu.
3.
Select SINGLE in the MODULE field.
5-5
.~~~~.
~
AO).
~rocedures
DAB 9100 Series 91S16-91S32 Service
4.
Move the cursor to the SLOT field and enter 1 to test the
91516 in slot 1.
5.
Set the MODE field to SINGLE and run all functions.
The DAS diagnostics will perform all available tests on the slot.
All Diagnostics tests should pass.
(2) Probe Connector Functional Tests
This test verifies:
o the operation of the probe R/W line and the POD R/W IC
o the runs from the POD R/W IC to the probe connectors
o the POD STATUS register and its selector.
For these tests, a P6460 probe is connected to POD C and a P6464
probe is connected to POD A, then to POD B.
~
A probe must not be connected or removed while a
pattern Is being generated. Doing so can damage the
probe.
1.
Press the POD ID button on the P6464 probe in POD A, and
verify that the display shows POD lA in the upper left
corner.
2.
Remove the probe and verify that POD lA DISCONNECTED appears
in the upper left corner of the DAS display.
3.
Reconnect the P6464 probe to POD A and verify that the
display shows POD lA CONNECTED~
4.
Repeat steps 1 through 3 for POD B on the 91Sl6 module.
Using the P6460 probe, repeat steps 1 through 3 for POD C.
(3) POD A Data OUtput Test
Test Setup
The following procedure provides the initial setup for these
tests. You will modify the probe setup as you perform the
functional check.
5-6
Verif. & Adj. Procedures
DAB 9100 Series 9lS16-9lS32 Service
1.
Connect a P6464 Pattern Generator Probe A to POD connector A
of the 91Sl6, a P6464 B to POD connector B, and the P6460
external control probe to POD connector C. When probes are
installed, the mainframe should beep and show the message POD
lA (or lB or lC) CONNECTED.
2.
Connect the data acquisition probe to the 91A08 Data
Acquisition module in slot 6.
3.
Connect the pattern generator probe podlets to the data
acquisition probe using flying-lead sets and connector pins
pin 131-2230-00 connector pins or equivalent. Connect P6464
to POD A, and P6452 to the 91A08 in slot 6.
4.
Connect the strobe line of the pattern generator probe to the
qualifier line of the data acquisition probe.
5.
Connect the ground lead of the data acquisition probe to an
appropriate ground lead of the P6464 probe.
6.
Connect the P6454 100 MHz Clock Probe to the coaxial
connector on the 91A08 module in slot 6.
7.
Connect the IN line of the 100 MHz Clock Probe to the clock
output of the pattern generator probe.
8.
Connect the REF line of the 100 MHz Clock Probe to the unused
GND SENSE line of the data acquisition probe.
Pattern Generator Probe Setup
The following procedure connects the P6464 Pattern Generator
Probes to the DAS and to an external +5 V power supply. The
probes are also decoupled from variations in the supply with a
1 uf capacitor (pin 290-0891-00 or equivalent).
NOTE
If a PS503A is used as the +5 V external power supply,
install it in the high-power slot of your TMSOO Series
mainframe.
1.
Connect P6464 Pattern Generator Probes to the POD connectors
of the 9lSl6 in the DAS mainframe. If a label on a probe
identifies it by POD number, it must be connected to that POD
connector.
2.
Connect a 2 foot (0.6m) wire to the +5 V output of the power
supply. Connect a 2 foot wire to the ground of the power
supply.
5-7
Verif. & Adj. Procedures
DAB 9100 Series 91S16-91532 Service
3.
Connect the VL lines (black) and common lines (green) of all
pattern generator probes to the 2 foot wire attached to the
ground output of the +5 V, 2 A power supply.
4.
Connect the VH lines (red) of all pattern generator probes to
the 2 foot wire attached to the +5 V output of the +5 V, 2 A
power supply.
5.
Connect one 1 uF ceramic capacitor across the VH and VL
inputs to each probe. The best and easiest way to connect
these capacitors is to hook one end of each ceramic capacitor
under the hook tip that connects the probe to the +5 V
source. Place the other end of each ceramic capacitor under
a hook tip that connects to the ground wire.
6.
After connecting a ceramic capacitor, check to make sure that
connections to the +5 V power supply and ground are secure.
(V-ref of podlets, VL and common of the P6464, DAS ground, PS501
ground, and P6452 ground are all common.)
7.
Leave the Diagnostics menu by pressing the PATTERN GENERATOR
key. In the Pattern Generator Timing sub-menu, verify that
the pattern generator clock is set to 1 microsecond.
S.
Enter SEQ 1000 after SEQ O.
9.
Enter the following program in the Pattern Generator Program
menu.
SEQ
0
1000
1001
1002
1003
1004
1005
1006
1007
100S
1009
1010
1011
LABEL
1000
B
A
S I M
00
00
01
02
04
OS
10
20
40
55
SO
00
00
01
02
04
OS
10
20
40
55
SO
0
0
0
0
0
0
0
0
0
AA AA
FF FF
3
0
3
0
o0
o0
o0
o0
o0
o0
o0
o0
o0
o0
o0
o0
o0
SEQ PLOW,
CON'rROL REG, OUT
JUMP
1000
JUMP
1000
10. Enter the Trigger Specification menu and set the MODE field
to 91AOS ONLY. See Figure 5-1.
5-S
Verif. & Adj. Procedures
DAS 9100 Series 91516-91532 Service
11. In the Trigger Specification menu, set the acquisition clock
to external falling edge.
12. Press the POD ID button on the back of the data acquisition
probe. Read the POD number off the DAS screen. Set the
qualifier of the acquisition module to O.
TRIGbER
SPECIFICHTI~
TRIG.~
POSITlI]t: . . .
H
fBi
TRIGGER 00
lEI
!1.ITQ£S . .
PC(!£C
ST!Y.£ M.Y IF:
Q=•
5397-30
Figure 5-1.
Trigger Specification menu organization.
The next steps verify that the 9lSl6 can transmit data, strobe,
and clock signals through POD connector A.
13. Press the START SYSTEM key.
14. Enter the Timing Diagram menu.
15. Press and hold the POD ID button on the back of the Data
Acquisition probe.
Read the POD number off the DAS screen.
16. Set the magnification in the Timing Diagram menu to 10; this
should show a display like Figure 5-2. The 9lA08 should
trigger on sequence 18.
5-9
ver1re & Adj. Procedures
DAB 9100 Series 91S16-91S32 Service
TII1IHi
OI~
~,-
GlITCHES' _
ClRSOR SEQ:
DELTA TItE:'
SRCH =
POD Of HtlE
Iii _
8
8
6C6
6C5
6C4
8
6C3
6C2
6C 1
6C
8
I
o
8
8
1
e
5397031
Figure 5-2.
Timing Diagram menu, POD A transmission test.
(4) POD B Data Output Test
This test verifies that the 91S16can transmit data, strobe and
clock signals through POD connector B.
Connect the P6464 Pattern Generator Probe (B) to POD connector B,
and to the data acquisition probe of the 9lAOS in slot 6.
1.
When the probe is installed in POD connector B, the DAS
mainframe should beep and show the message "POD lB
CONNECTED" •
2.
Press the POD ID button on the back of the pattern generator
probe housing. The DAS mainframe should beep and display the
message "POD lB".
5-10
Verif. & Adj. Procedures
DAS 9100 Series 91516-91532 Service
3.
Enter the Trigger Specification menu and set the qualifier
for the data acquisition probe to 0 (active low).
4.
Press the START SYSTEM key.
5.
Enter the Timing Diagram menu.
6.
Press the POD ID button on the back of the data acquisition
probe.
Read the POD number on the DAS screen. Adjust the
Timing Diagram menu to show data from this POD.
7.
Set the magnification of the Timing Diagram to 10: this
should again show a display like Figure 5-2. The 9lA08
should trigger on sequence 18.
(5) Inhibit Control Test
Test setup
1.
Disconnect the P6452 qualifier lead from the P6464 and
connect the strobe lead from the P6464 probe to the INHIBIT
(red) lead of the P6460 input probe.
2.
Enter the Pattern Generator menu. Verify the that INHIBIT
MASK field in the Pattern Generator program is 0000, and that
the INHIBIT MASK field in the Configuration sub-menu for
clock and strobe inhibit masks is set to 1. Enter the Probe
sub-menu and set the INHIBIT field to EXTERNAL 1 ONLY.
3.
Enter the Timing menu and set the CLOCK field to 2 us.
4.
Set the strobe to 3 on lines 1008 and 1009 lines of the
pattern generator program. The program should now look like
the following listing.
INHIBIT
MASK
SEQ
00 00
LABEL B
0
1000 1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
00
00
01
02
04
08
10
20
40
80
FF
A
S I M
00
00
01
02
04
08
10
20
40
80
FF
0
0
0
0
0
0
o
o
o
o
0
0
0
0
0
o
o
o
o
o
3
3
o0
0
0
o
SEQ PLOW,
CONTROL REG, OU'r
JUMP
1000
0
0
0
0
0
0
JUMP
5-11
1000
Verif. & Adj. Procedures
DAS 9100 Series 91516-91532 Service
Test Description
This test verifies that the 91Sl6 responds to an external inhibit
signal through the P6460 probe.
Test sequence
5.
Press the START SYSTEM key.
6.
When data acquisition is complete, enter the Timing Diagram
menu. The display should look like Figure 5-3.
MAG: _
TI MIt«; DItt;RAIt
ClRSOR SEQ: 496
IlITCI£S: . .
DELTA TIrE:
=
<-I
POOCHHAI£.
li_
SRCH
6C 6
6C5
6C 4
6C 3
6C 2
6C 1
6C
e
IIiI
I
I
L.J'1'-_.....I '--__IL.._ - - , ,"-_-in I
lJ1
nl
Ln
n
1
n.......,.~........_ _
e
e
e
I
I
lJ"I'--_....InL.._.....InL.._.....InL.._-..ln I nL.._........r 8
f'1...................n...._ ........nL.._____nL.._____n I n n . e
•
I
n...._ ........n...._ ........n...._ ........n
nL.._____nL.._____n...._ ........n
I
I
I
I
I
I
I
I
I
I
Pigure 5-3.
I n
rL
Inn....
I
I
I
I
I
I
I
I
I
I
Test data, inhibit control test.
5-12
e
e
5397-32
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
The next steps verify the operation of the internal inhibit.
7.
Enter the Pattern Generator menu, and set the INHIBIT field
to 1 as in the following display. Enter the Probe sub-menu
and set the INHIBIT field to INTERNAL 1 ONLY.
INHIBIT
MASK
LABEL
SEQ
a
1000 1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
00 00
B
A
S I M
SEQ PLOW,
CONTROL REG, OUT
00
00
01
02
04
08
10
20
40
80
FF
00
00
01
02
04
08
10
20
40
80
FF
a a
JUMP
1000
0
aaa
aaa
aaa
a
0 a
000
oa a
a 0 a
aaa
aaa
030
JUMP
1000
8.
Press START SYSTEM.
9.
When data acquisition is finished, enter the Timing Diagram
menu. The display should again look like Figure 5-3.
(6) External Jump Line Test
Test Setup
1.
Connect the strobe line to the EXT JUMP (orange) lead of the
P6460 input probe.
2.
Enter the SETUP PROBE sub-menu and set the EXT JUMP field to
IF 1, and disable the INHIBIT field.
3.
Enter the Pattern Generator Program menu and set the IF EXT
JUMP instruction as shown in the following display.
5-13
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
SEQ
LABEL
0
1000 1000
1001
1002
1003
1004 1004
1005
1006 TEST
1007
1008
1009
B
A
S I M
SEQ PLOW,
CONTROL REG, OUT
00
00
01
02
04
80
FF
08
10
20
40
00
00
01
02
04
80
FF
08
10
20
40
0
0
0
3
0
0
0
0
0
0
0
JUMP
1000
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
IF EXT JUMP TEST
JUMP
1000
JUMP
1004
This test verifies that the 91S16 responds to the IF EXT signal
through the P6460 input probe.
4.
Press the START SYSTEM key.
5.
When displayed on the Timing Diagram menu, the data acquired
from the pattern generator should look like the data shown in
Figure 5-4.
TIHIN;
SRCH
DI~
=
Pro CH M
11_
MAG: _
GlITCHES: _
ClRSOR SEQ:
OELTA TII£:
I
I
8
8
6C4
6CJ
9
8
8
6C2
6C 1
6t8
Pigure 5-4.
o
e
6C6
6C5
1
Test data, external jump line test.
5-14
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
(7) IRQ Test 1
Test Setup
1.
Connect the strobe line of POD A to the interrupt line
(yellow) of the P6460 input probe, and connect the strobe
line of POD B to the qualify line (green) of the P6460 input
probe.
2.
Enter the Probe sub-menu and set the IRQ field to ON rising
edge, CALL TEST, and Enter the Program sub-menu. Disable the
EXT JUMP field, push DON~T CARE to eliminate sequence flow
and control commands, then type in the program as follows.
SEQ
LABEL
a
1000 1000
1001
1002
1003
1004
1005
1006 TEST
1007
1008
1009
B
A
S I M
SEQ FLOW,
CONTROL REG, OUT
00
00
01
02
04
80
FF
08
10
20
40
00
00
01
02
04
80
FF
08
10
20
40
000
JUMP
1000
JUMP
1000
a a a
aa 0
2 a 0
100
a a 0
a a a
000
oa a
a a a
a a a
RETURN
Test Description
This test verifies that the 9lSl6 responds to an INTERRUPT signal
through the P6460 input probe.
It checks the qualifier line
through the P6460 probe, and checks the interrupt mask
instruction.
Test Sequence
3.
Press the START SYSTEM key.
4.
When IRQ test data is displayed on the Timing Diagram menu,
the data acquired from the pattern generator should look like
the data shown in Figure 5-5.
5-15
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
OJRCJDR SEQ:
DELTA TIfE:
I
i
~
n
n
r1
18
iii
rL--
i
I
e
ilrl-Ilf'L--.J'ln.----11.TL-- ~
r~'"L'"L-.J'"L..f1_ _rl...rL..-J" ~
LJLJL__. n_-fl_. . .rLJ"L""""rU'l__IL ~
6G 6
6e 5
UL""IL_fl.......I',-....JL_n_1L_il__fL, e
L'1_-1L. . .JL"""""",J1__JL"""""",rL...n__n. .......1'"L...... ~
rL-.lL..JL__fl.-11-...JLJL_..Ju1- a
J
q.n.___f1. .ri...-.-lUi-.. . . . . ru'L-. 1
5397-34
Figure
5-5.
Test data, interrupt test 1.
The next steps verify the operation of the qualify line.
5.
Enter the SETUP PROBE sub-menu and set the QUALIFIER field
to 1.
6.
Press the START SYSTEM key.
7.
The Timing Diagram menu should again look like the data shown
in Figure 5-5.
8.
Enter the PROBE sub-menu and set the QUALIFIER field to
9.
Press the START SYSTEM key.
O.
10. The Timing Diagram menu should look like the data shown in
Figure 5-6.
5-16
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
tnIIfI; OI~
SRCH
PI))
Ct$~~~ ~~~:
DELTA TIfE:
=
I
i
LrL....rL-..J'L-..lr--tL-l-1-J~
Of tW£
111_
18
Dii
r
n__SL--J1-n--..rL--lL--lL--
6C6
6C5
6C4
!
6C3
6C2
6Cl
6C8
LnwL_f1..rL-l-uL....1-Ut--rLfL..-l-u-LJLfl.J·L
~
iL.JL--J-L--l~L-_r"~L-.
~
f'L-rL--JL-...rL--lL-...J~L--
~
r5...--ini-..-..lL-...rL-...inL--..l~r;_._
!lJ"'u-L.rL-f'Juw-u-u l""L.J'1.-1-L...rLluL
~
~1.rLJ1.r~-L1LJ1..rl-'''LJL_rl.r''L_~-W-L-
5397-35
Pigure 5-6.
Test data, qualify line test.
The next steps verify the operation of the interrupt mask.
Test setup
11. Enter the Program sub-menu and set the M field as follows.
SEQ
LABEL
0
1000 1000
1001
1002
1003
1004
1005
1006 TEST
1007
1008
1009
B
A
S I M
00
00
01
02
04
80
00
00
01
02
04
80
0
0
0
2
1
FF FF
08
10
20
40
08
10
20
40
a
a
0
a
a
0
o0
o0
o0
a1
o0
aa
aa
o0
o0
o0
oa
SEQ PLOW,
CONTROL REG, OUT
JUMP
1000
JUMP
1000
RETURN
5-17
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
12. Enter the Probe sub-menu and set the qualifier field to X.
Test sequence
13. Press the START SYSTEM key.
14. The Timing Diagram menu should again look like the data in
Figure 5-6.
(8) IRQ '.rest 2
1.
Enter the Program sub-menu and remove the RETURN at sequence
1009.
2.
Enter the Probe sub-menu and set the IRQ field to ON rising
edge: IF IRQ ENABLED, and enter the Program sub-menu. Write
the program as follows.
SEQ
LABEL
0
1000 1000
1001
1002
1003
1004 1004
1005
1006 TEST
1007
1008
1009
B
A
S I M
00
00
01
02
04
80
FF
08
10
20
40
00
00
01
02
04
80
FF
08
10
20
40
0
0
o
1
o
o
o
o
o
o
o
o
o
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEQ PLOW,
CON'lROL REG, oU'!'
JUMP
1000
IF IRQ JUMP TEST
JUMP
1000
JUMP
1004
Test Description
This test verifies that the 91Sl6 responds to the INTERRUPT
signal through the P6460 input probe.
Test Sequence
3.
Press the START SYSTEM key.
4.
The Timing Diagram menu display shows the data acquired from
the pattern generator. The display should again look like
the data shown in Figure 5-5.
5-18
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
The next steps verify the operation of the qualify line.
5.
Connect the strobe line of POD B to the qualifier line
through the P6460 input probe.
6.
Enter the Probe sub-menu and set the QUALIFIER field to 1.
7.
Press the START SYSTEM key.
8.
The Timing Diagram menu should again look like the data shown
in Figure 5-5.
9.
Enter the Probe sub-menu and set the QUALIFIER field to O.
10. Press START SYSTEM.
11. The Timing Diagram menu should again look like the data shown
in Figure 5-6.
(9) Transmission Test of the EXT eLK Signal
Test Setup
This test requires the use of an external clock source. The
recommended clock source is a square wave or pulse generator with
a 50 MHz output between ground and +5 v.
1.
Connect the output of the signal generator to the EXT CLK
line on the P6460 input Probe.
2.
The signal generator must have a common ground with the
probes. To accomplish this, connect the ground of the signal
generator to the two clips that connect the data acquisition
probe ground sense to the P6460 input Probe ground line.
3.
Enter the Probe sub-menu and set the IRQ field to DISABLE,
and enter the Timing sub-menu and set the CLOCK field to
EXTERNAL rising edge.
4.
Adjust the pattern generator program to match the following
display.
5-19
ver1r. & Adj. Procedures
DAS 9100 Series 91516-91532 Service
SEQ
LABEL
a
1000 1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
5.
B
A
S I
M
SEQ PLOW,
CONTROL REG, OUT
00
00
01
02
04
08
10
20
40
80
FF
00
00
01
02
04
08
10
20
40
80
FF
a
1
a
a
a
a
a
a
a
0
a
a
a
a
a
a
a
JUMP
1000
a
a
a
a
0
a
a
a
a
a
a
0
0
a
a
a
JUMP
1000
Enter the Trigger Specification menu and set the acquisition
clock to External Falling edge.
~est
Description
This test verifies the transmission of the EXT eLK signal through
the P6460 Input Probe.
Test Sequence
6.
Press START SYSTEM.
7.
When acquisition is finished, examine the Timing Diagram
menu. The data acquired from the pattern generator should
look like the data shown in Figure 5-7.
A display like Figure 5-7 means the pattern generator external
clock is being properly received and processed.
5-20
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
EJ: £,
6C 5
6C 4
e
rL.J1~flJl_JwL-..l-L...r~L-.-f" e
~
r~1_---'r'-i_---'r-'....
' _---'r-t-
~
~
~
fliL--.ll..fL__rtfi-SJ1_ _ e
rL-.J'L-.l-LJL-SL_rL_r~L-.f~L
0
L-L-_fLJ"L---l~~L.....l-L-lL-.f~L
LIL....JL_.r~~L.._r"'tL-J"L..i-L-...J-L1"'L
i
L-JLJ'L-_.rL.rL----lLrl_~-L.r~L_
§
ruL--.l1J"'L--.l-u-L--.....iZ"·Lr~L-
5397-36
Figure 5-7.
Test data, EXT CLK transmission test.
(10) TRIGGER OUT Signal Control Test
Test Setup
1.
Enter the Timing sub-menu and set the CLOCK field to 200 ns.
2.
Connect the phono connector TRIG OUT Jl80 (jack nearest
POD C) to an oscilloscope with the BNC-phono cable, and set
the oscilloscope as follows:
TRIGGER --------- AUTO
CH. 1 ----------- 2 V/div.
TIME BASE -------500 ns/div.
3.
Adjust the pattern generator program to match the following
display.
5-21
Verif. & Adj. Procedures
DAB 9100 Series 91S16-91S32 Service
SEQ
LABEL
0
1000 1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
B
A
S I M
00
00
01
02
04
08
10
20
40
80
FF
00
00
01
02
04
08
10
20
40
80
FF
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEQ PLOW,
CONTROL REG, OUT
JUMP
TRIGGER
1000
JUMP
1000
Test description
This test verifies the 91816 can transmit the trigger out signal
through the phono connector.
Test Sequence
4.
Check that a square pulse is generated and looks like Figure
5-8.
III
III
5397-37
Pigure 5-8.
TRIGGER OUT pulse.
5-22
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
(11) External Pause Signal Control Test
Test Setup
These steps require the use of an oscilloscope and an external
signal. The external signal required is a square wave with a 10
microsecond period and an output between ground and +5 v.
1.
Enter the Probe sub-menu.
2.
Enter the Timing sub-menu.
using the DECR key.
3.
Attach the PAUSE input (brown lead) from P6460 to PG502
output. Attach the probe for channel 1 of the oscilloscope
to the external signal. Attach the probe for channel 2 of
the oscilloscope to the P6464 probe clock output. Set the
oscilloscope to trigger on a rising edge in channell.
Attach the ground leads of the probes to the ground of the
P6460 and the P6464 probe.
TRIGGER ------CH. 1 -------CH. 2 -------TIME BASE -----
Set the PAUSE field to ON O.
Set the CLOCK field to 200 ns by
NORM
2 v/div.
2 v/div.
2 microseconds/dive
Test Description
The next steps verify that the 9lSl6 responds to the PAUSE signal
through the P6464 External Probe.
Test Sequence
4.
Press the START PAT GEN key.
5.
The oscilloscope display should look like the one shown in
Figure 5-9.
5-23
ver~r. ~ Adj. Procedures
DAB 9100 Series 91S16-9lS32 Service
5397-38
Figure 5-9.
External pause pulse, PAUSE •
o.
6.
Enter the Probe
7.
Press the START PAT GEN key.
8.
The oscilloscope display should look like the one shown in
Figure 5-10.
sub~menu.
Set the PAUSE field to ON 1.
5-24
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
5397-39
Pigure 5-10.
External pause pulse, PAUSB
= 1.
(12) External Start Control Test
Test Setup
1.
Connect the output of the pulse generator (PG502) to phono
connector J160 with the BNC-PHONO cable, and set both TRIG
and DURATION to EXTERNAL. Set the output level of the
generator to TTL (0 V to +5 V).
2.
Enter the Probe sub-menu.
3.
Set the EXTERNAL START field to ON rising edge, and set the
oscilloscope to trigger on channel 2.
Set the PAUSE field to DISABLED.
Test Description
The following steps verify that the 9lSl6 responds to the START
signal through the phono connector.
5-25
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
Test Sequence
4.
Press the START PAT GEN key.
5.
Check that the 9lSl6 starts generating a clock at the P6464
probe when you press the MANUAL TRIGGER button on the pulse
generator.
6.
Enter the Probe sub-menu.
falling edge.
7.
Press START PAT GEN.
8.
Check that the 91Sl6 starts generating a clock when you
release the MANUAL TRIGGER button.
Set the EXTERNAL START field to
(13) POD Clock Delay Control Test
Test setup
1.
Enter the Timing sub-menu and set the CLOCK field to 200 ns.
2.
Connect the probe for channell of the oscilloscope to the
clock lead of the P6464 probe at POD A.
3.
Connect the probe for channel 2 to the clock lead of POD B.
4.
Remove the phono connector from J160.
Test description
This test verifies the POD clock delay_
Test sequence
5.
Set the POD field to lB (not the reference POD) and set the
POD CLOCK field to 0 ns.
5-26
Verif. & Adj. Procedures
DAS 9100 Series 91516-91532 Service
6.
Check that the rlslng edge on channell is overlapping the
rising edge on channel 2.
(The overlap should be +500 ps if
the tight tolerance adjustment was used to align the clock
channels between POD A and POD B, or should be +2.5 ns if
clock alignment was done at the P6464 connector-between POD A
and POD B).
7.
Set the lB POD CLOCK field to +5 ns and check that the rlslng
edge in channel 2 is 5 ns after the rising edge in channell.
(The overlap should be +1.5 ns if the tight tolerance
adjustment was used to align the clock channels between POD A
and POD B, and should be +3.5 ns if the clock alignment was
done at the P6464 connector between POD A and POD B.)
8.
Set the lB POD CLOCK field to -5 ns and check that the rising
edge in channell is 5 ns after the rising edge in channel 2.
9.
Set the POD CLOCK field to 0 ns and set the POD field to lAo
10. Verify that the POD CLOCK field is set to 0 ns and repeat
steps 3 through 5 for POD A.
11. Set the POD CLOCK field to +5 ns and check that the rising
edge in channel 2 is 5 ns after the rising edge in channell.
5-27
91532 PA'l"l'ERN GENERATOR MODULE FUNCTIONAL CHECK
You will need the following equipment to perform this procedure:
DAS 9100 mainframe with Vl.ll firmware version and a 22 A, +5 V
Power Supply
Four P6464 TTL/MOS Pattern Generator Probes
P6452 External Clock Probe
P6452 Data Acquisition Probe
9lA08 Data Acquisition Module
P6454 100 MHz Clock Probe
350 MHz oscilloscope with two channels
Two probes for the above oscilloscope
100 MHz (or higher) pulse generator
Refer to the Operating Instructions section of this addendum for
information on module installation and on the use of the
Diagnostic menu. Refer to the beginning of this Verification and
Adjustment Procedures section for information on connecting
probes together with the diagnostic lead set.
(1) Mainframe Setup for the Functional Check
The following steps configure the DAS mainframe for use in this
functional check. If, due to insufficient +5 V power supply
modules or some other constraint, the mainframe is not configured
in the recommended way, some functional check procedures will
require modification. Configure the mainframe according to the
following steps.
~
Do not install or remove any electrical module or subassembly in a DAS mainframe while the power is on.
Doing so can damage the module or sub-assembly.
NOTE
The following steps may require removing modules that
were previously installed in the mainframe.
5-28
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
1.
Turn off the mainframe.
2.
Remove the 9lSl6 from the mainframe.
3.
Install a 9lA08 in. slot 6.
4.
Install the 91S32 to be checked in slot 5 of the DAS
mainframe that receives power from the 22 A, +5V supply.
Install jumpers on J206 and J208. If there is another 9lS32
module in the mainframe, remove it.
NOTE
The 9lS32 module may be tested in any powered slot.
However, this procedure will be easier to follow if the
9lS32 module is installed in slot 5.
(2) Executing the Diagnostic Self-Test
The following procedure runs all available Self-test diagnostics
on the 91S32 module.
1.
Turn on the mainframe while holding down the STOP key on the
keyboard. This will cause the power-up self-test to fail.
2.
Press START SYSTEM to enter the Diagnostic menu.
diagnostic tests on slot 5, the 9lS32 module.
3.
Select ALL mode, then press START SYSTEM. The DAS
diagnostics will perform all available tests on the slot.
All diagnostic VECTOR RAM tests should pass.
Run
(3) Probe Setup for the Functional Check
The following procedure provides the initial probe setup for
these tests.
1.
Connect the P6464 pattern generator probe to POD connector D
on the 9lS32. When the probe is installed, the mainframe
should beep and show the message POD 5D CONNECTED.
2.
Press the POD ID button on the back of the probe housing.
The mainframe should beep and display POD 5D.
3.
Connect the P6452 data acquisition probe to the 9lA08
acquisition module.
4.
Connect the P6464 Pattern Generator Probe podlets to the
P6452 data acquisition probe with the flying-lead set and
connector pins pIn 131-2230-00 or equivalent. Use all the
ground connections.
5-29
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
5.
Connect the strobe line of the pattern generator probe to the
qualifier line of the data acquisition probe (the white
flying lead from the acquisition side of the Diagnostic Lead
Set).
6.
Connect the P6452 external clock probe to POD connector C of
the Trigger/Time Base Module.
7.
Install a flying lead set in the P6452 external clock Probe.
Also install a ground lead in the GND DIAGNOSTIC connector on
the clock probe.
8.
Install a ground lead in one of the GND SENSE connectors of
the P6452 Data Acquisition Probe. Connect the ground lead of
the external clock Probe to one of the grounds on the P6464
pattern generator probe.
9.
If a 91A08 module is being used as the acquisition module in
the functional check, connect the 100 MHz Clock Probe to its
connector on the 9lA08 module in slot 6.
10. Connect the IN line of the 100 MHz Clock Probe to the clock
output of the pattern generator probe.
11. Connect the REF line of the 100 MHz Clock Probe to the unused
GND SENSE line on the pattern generator probe.
12. Set the external power supply output to +5 V.
13. Connect the red lead from the P6464 probe to the +5 V output
of the external power supply.
14. Connect the power supply ground, V-ref on the podlets, and
all probe grounds to the same ground point.
(4) Initial Menu Setup for the Functional Check
The procedure organizes the menus so that the remainder of the
functional checks requires a minimal change to the menus.
1.
Leave the Diagnostic menu by pressing the PATTERN GENERATOR
key. Select the Timing sub-menu and verify that the pattern
generator clock is at 1 microsecond (default).
2.
Select the Pattern Generator Configuration sub-menu and enter
END SEQ 11, FREE RUN; then select the 91S32 Program sub-menu.
3.
Set the pattern generator program to match Figure 5-11.
5-30
Verif. & Adj. Procedures
DAS 9100 Series 91516-91532 Service
1«£:"
PfI:iE:
m
STAAT SEQ:_
..
Is!1
50: $A
I~*I~I*I*I
0101 0101
~"'92
'-
02'dZ
3
4
0-#J4 04M
?,
5
6
~
i
3
9
fi:300 flOOS
1010 1010
7&"
4a43
5555
8ff88
2329
4040
5:65
0000
r-
.j
II II
a 0
0 0
a 0
0 0
a a
0 a
a a
F a
a a
18
lHYt lHYt
F
11
FFFF FFFF
8
•
II • • :
I
8
8
1_
• • • • Pm _
5397-40
Pigure 5-11.
Pattern Generator Program sub-menu to start 91532
functional test.
4.
Enter the Trigger Specification menu.
9lA08 only.
5.
In the Trigger Specification menu, set the acquisition clock
to external falling edge.
6.
Press the POD ID button of the
probe.
7.
Read the POD number on the DAS screen.
corresponding to that POD to O.
5-31
9lA08~s
Set the MODE field to
P6452 data acquisition
Set the qualifier
y~~~~.
G Aa].
~rocedures
DAS 9100 Series 91S16-91S32 Service
(5) Verifying POD Connector D
The following procedure verifies that the 91S32 can transmit
data, strobes, and clock signals through POD connector D.
1.
Press the START SYSTEM key.
2.
Enter the Timing Diagram menu.
3.
Press the POD ID button on the back of the acquisition probe.
Read the POD number on the DAS screen. Adjust the Timing
Diagram menu to show data from this POD.
4.
Set the magnification of the Timing Diagram to 101 this
should show a display like Figure 5-12. The actual position
of the cursor and trigger will depend on the type of
acquisition module used. A 91A08 should trigger on
sequence 18-.
TIftlt«; DltaM
SRCH
JW;:EI
Q.ITOES: . .
=
pro CH
[Ii _~
6[6
6[5
6[4
Cl.RS(i SEQ:
1B
!E.TA TI!£: . .
a
I !1..fL-.f1...IL_J1..JL__JUL_-11.. a
L1LlL-1LIL.-JL.1..-J1~ a
1.-----'
'--_...I
n
L.._--J
---fa
!
i
!
i
I
I
Figure 5-12.
. 5397-41
Timing Diagram menu for POD connector D.
5-32
Verif. & Adj. Procedures
DAS 9100 Series 91516-91532 Service
5.
Enter the Pattern Generator Program sub-menu. Set the lowerleft corner sub-menu to MODIFY, and enter LOGICAL XOR SEQ 0
THROUGH 9 XXXX XXXX 8 X. Press the EXECUTE key. See Figure
5-13.
PATTERK
Ga£RATtR~:
91532
PAGE: II
START SEQ:"
I~IBIT
MASk : ·'1Ii'IIWl'liE,lim
a
lmn
. . 5OC5BA
IUE:"
S I
. . '@iI!,iIiM 1111
1 8181 8181 8 8
2
3
4
0292 9292
9494 8484
0898 8898
8 9
8 8
8 9
5
1918 1818 8 9
6
7
8
9
2828
4848
8888
FFFF
2828
4848
8988
FFFf
8
8
8
8
9
8
9
9
.'111,*0111 : M'IlUW,i_ pro _
5397-42
Figure 5-13.
Pattern generator setup for POD D check.
6.
Enter the Trigger Specification menu. Set the qualifier for
the data acquisition probe to 1 (active low).
7.
Press START SYSTEM.
8.
The data acquired should again match Figure 5-12.
(6) Verifying POD Connector C
The following procedure verifies that the 91532 can transmit
data, strobes, and clock signals through POD connector C.
1.
Remove the P6464 Pattern Generator Probe from POD connector D
of the 9lS32 module. Reconnect the probe to POD connector C
of the 91532 module.
5-33
ver1r. & Adj. Procedures
DAS 9100 Series 91516-91532 Service
2.
When the probe is installed in POD connector C, the mainframe
should beep and display the message POD 5C CONNECTED.
3.
Press the POD ID button on the back of the pattern generator
probe housing. The mainframe should beep again and display
POD 5C.
4.
Enter the Trigger Specification menu and set the qualifier
for the acquisition probe to 0 (active low).
5.
Press START SYSTEM.
6.
Enter the Timing Diagram menu.
like Figure 5-12.
The display should ag·ain look
The previous steps have verified the operation of the clock,
data, and strobe lines.
7.
Enter the Pattern Generator Program sub-menu. Set the lowerleft corner of the sub-menu to MODIFY, enter LOGICAL XOR SEQ
o THROUGH 9 XXXX XXXX 4X, and press EXECUTE. See Figure 5-14
PATTERN GEt£RATIR
91532
Pm;RAtI:
INHIBIT
t1ASK : .miiiiiil'i5!"
II!I SIX SBA
_
1m:'"
Pta: II
STMTSEQ: . . .
S I
11111,111111111
1
8181 8181 4 8
2
8282 8282
4 8
3
4
5
6
7
8
9
8484
8898
1818
2828
4848
8888
FFFF
4
4
4
4
4
4
4
8484
8888
1818
2828
4848
8888
FFFF
8
8
8
8
8
8
8
_"111'1 : MlJlmljfj_ POO •
5397-43
Figure 5-14.
Pattern generator setup for POD C check
5-34
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
8.
Enter the Timing Diagram menu. Set the qualifier for the
data acquisition probe to 1 (active high).
9.
Press START SYSTEM.
10. The data acquired should again match Figure 5-12.
(7) Verifying POD Connector B
The following procedure verifies that the 9lS32 can transmit
data, strobes, and clock signals through POD connector B.
1. Remove the P6464 Pattern Generator Probe from POD connector C
of the 9lS32 module. Reconnect the probe to POD connector B
of the 9lS32 module.
2. When the probe is installed in POD connector B, the mainframe
should beep and display the message POD 5C CONNECTED.
3. Press the POD ID button on the back of the pattern generator
probe housing. The mainframe should beep again and display
POD 5B.
4. Enter the Trigger Specification menu and set the qualifier for
the acquisition probe to 0 (active low).
5. Press START SYSTEM.
6. Enter the Timing Diagram menu.
like Figure 5-12.
The display should again look
The previous steps have verified the operation of the clock,
data, and strobe lines.
7.
Enter the Pattern Generator Program sub-menu. Set the lowerleft corner of the sub-menu to MODIFY, and enter LOGICAL XOR
SEQ 0 THROUGH 9 XXXX XXX X 2 X. Press the the EXECUTE key.
See Figure 5-15.
5-35
Verif. & Adj. Procedures
DAB 9100 Series 91S16-91S32 Service
PATTERN
GEt£RAT(I~:
91S32
m· . .
STMT
INHIBIT
M:;E'11
SEQ: ~
JItA5K ; liii@iljle'
lUI
:it 5BA
S I
__ i'll.lalj!!l,@,. II
1 0191 0191 2 0
2
8282 8292 2 0
3
4
5
6
7
8
9
8484
0888
1910
2829
4848
8988
FFFF
8484
88\l8
1918
2829
4848
8888
FFFF
2
2
2
2
2
2
2
8
8
8
8
8
8
8
MJllljitOJJI : _'~ld. PIlI •
5397-44
Figure 5-15.
Pattern generator setup for POD B check
8.
Enter the Timing Diagram menu. Set the qualifier for the
data acquisition probe to 1 (active high).
9.
Press START SYSTEM.
10. The data acquired should again match Figure 5-12.
(8) Verifying POD Connector A
The next steps verify that the 91532 can transmit data, strobes,
and clock signals through POD connector A.
1.
Remove the P6464 Pattern Generator Probe from POD connector B
of the 91532 module. Reconnect the probe to POD connector A
of the 91532 module.
2.
When the probe is installed in POD connector A, the mainframe
should beep and display the message POD5A CONNECTEDo
5-36
Verif. & AOJ. ~roceau~es
DAS 9100 Series 91516-91532 Service
3.
Press the POD ID button on the back of the pattern generator
probe housing. The mainframe should beep again and display
POD 5A.
4.
Enter the Trigger Specification menu and set the qualifier
for the acquisition probe to a (active low).
5.
Press START SYSTEM.
6.
Enter the Timing Diagram menu. The display should again look
like Figure 5-12.
The previous steps verified the operation of the clock, data and
the strobe.
7.
Enter the Pattern Generator Program sub-menu. Set the 10werleft corner of the sub-menu to MODIFY, and select LOGICAL XOR
SEQ a THROUGH 9 XXXX XXXX 1 X. Press the EXECUTE key.
See
Figure 5-16.
~TTERH
GEtBlTCR
IHHIBIT
PQ;RAtt:
·lijlm'm~iil·iim:.r.'I
BB
SX::sA
1
~:.
SEQ: ~
S I
IM@ljOOJij'.1I
8181 8181 1 8
2
0292 0292
1 9
3
4
9484 8484
0888 8888
1 8
1 8
6
2929 2929
1 8
7
4948 4948
1 8
8
9
8988 8888
FFFF FFFF
1 8
1 8
5
1m:"
STMT
MASK :
_
91532
1818 1918 1 8
.'W.itOlIi : -nUw.3. POO •
5397-45
Pigure 5-16.
Pattern generator setup for POD A check.
5-37
Yec~c. ~ AQJ. Procedures
DAS 9100 Series 91516-91532 Service
8.
Enter the Timing Diagram menu. Set the qualifier for the
data acquisition probe to 1 (active high).
9.
Press START SYSTEM.
10. The data acquired should again match Figure 5-12.
(9) Verifying the PG INHIBIT Line
The following procedure verifies that the 91S32 responds to the
PG INHIBIT signal through the external clock probe.
1.
Disconnect the strobe lead of the pattern generator probe
from the qualifier lead of the data acquisition probe.
2.
Connect probes and set up the Configuration sub-menu as
follows:
3.
a.
Connect the strobe lead from the pattern generator probe
to the PG INHIBIT lead of the external clock probe (the
red lead), and connect the P6452 probe to P7C on the
Trigger/Time Base module.
b.
Connect the ground of the P6452 external clock probe to
the P6454 ground.
c.
Enter the Configuration sub-menu and enter END SEQ 9,
FREE RUN, set clock and strobe inhibit masks to 1, and
press EXECUTE. See Figure 5-17.
Set the program to match Figure 5-18.
5-38
Verif. & Adj. Procedures
DAS 9100 Series 91516-91532 Service
pr·,
:_l:i.1
iJJTPUT
LE~ti.
CT,
~
t::--
iii
'"""
2
·k
.j
~
4
,JH
C'.~
:""'-r::-,r:CLO(:K
ItfiIBIT ~f.: lfi1IBIT i'iHSK
CUCK
P€-4FA
;:;-"
..
.~
;:;!~uc=C.
~,
•
•
•
•
•
•
l·tL~:iiT
II
..
1M
R
•
•
R
•
P((~
CLOCK
.~!M
....
.~!M
5397-46
Figure 5-17.
Pattern Generator Configuration sub-menu, PG
inhibit line test.
PATTERN GEl£RATtR
PR~AI1:
91S32
MODE:"
PAGE:
MASK : IbM_U
IIiI
~
5BA
11
START SEQ:"
INHIBIT
S I
. . ',@!5@IMIlIIIII
1
9181 9181
9 9
2
0292 9282
9 9
3
8484 8484
8 8
4
8898 8898
9 8
6
7
2928 2929
4948 4948
9 9
9 8
8
9
8888 8888
FFFF FFFF
8 8
F 8
5
1818 1818 8 8
.zwl.'. : M••iIWja_ PI]) •
Figure 5-18.
5397-47
Pattern Generator Program menu for PG inhibit line
test.
5-39
Verif. & Adj. Procedures
DAS 9100 8eries 91816-91832 Service
4.
Enter the Pattern Generator Timing sub-menu.
to 50 microseconds.
5.
Press START SYSTEM.
6.
When data acquisition is finished, enter the Timing Diagram
menu. The display should again look like Figure 5-12.
7.
Enter the Pattern Generator Probe sub-menu.
EXTERNAL 1 ONLY.
8.
Press START SYSTEM.
9.
When data acquisition is finished, enter the Timing Diagram
menu. The display should look like Figure 5-19.
·T'I"ir
.... · ~
'.......1
'_~;j. E a .
Ii
C~~
Set the CLOCK
Set INHIBIT to
SEG:
18
[aTA THE:
~tl
6e 6
E"J: 5
61: 4
-
!
I
~
n
n..._---'r,....._---'n....._ _ e
n
n..._---'f e
ll.-!_---in..._---'n!....._ _ fL e
n..._ - - . Jn,....._---in...._ _ fL B
~'1
i n
Ln
~
~rl.-!__---iI~i_---,r~,
__---,ri.....____fL-e
f!i....
' _---'1';...._---'I~i_--Iro-'_--,i'"l-- e
il!I,..._ _....Jrl.l _---ir....
, _--'f"I....._--....IIi- 1
.-__---'r,....__---'r,....__---'r,.....__---ifL--B
!
e:
6e
5397-48
Pigure
5-19.
Timing Diagram menu, PG inhibit line test.
5-40
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
10. Enter the Pattern Generator Probe sub-menu. Set INHIBIT to
INTERNAL 1 ONLY, and set SEQ 9 I column to F.
11. Press START SYSTEM.
12. When data acguisition is finished, enter the Timing Diagram
menu. The display should again look like Figure 5-19.
13. Enter the Pattern Generator Probe sub-menu.
to EXTERNAL 1 AND INTERNAL 1.
Set the INHIBIT
14. Press START SYSTEM. Enter the Timing Diagram menu.
display should again look like Figure 5-19.
The
15. Enter the Pattern Generator Program sub-menu. Set the the
lower-left corner of the sub-menu to MODIFY, and enter
LOGICAL XOR SEQ 0 THROUGH 9 XXXX XXXX F F. Press EXECUTE.
See Figure 5-20.
(This step puts Fs in place of Os in the S
and I columns, and Os in place of Fs from the previous test.)
PATTERH
r;emT~ PR~:
I'IOIE: . .
PAGE: 1:1
START SEQ: ~
91S32
INHIBIT
t1ASK : 1'$i!OOmld
_ _ III!IIIIIIIWOO
1
8191 8181 F F
2
8282 8282
F F
3
9484 9484
F F
4
5
6
7
8
8888 8888
F F
9
FFFF FFFF
1818 1918 F F
2928 2928 F F
4848 4848 F F
8988 8888 F F
8 8
. . SEQ _
1lROIJCH _
II
Figure 5-20.
5397-49
Pattern Generator Program Submenu modified, PG
inhibit line test.
5-41
ver1t. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
16. Enter the Pattern Generator
EXTERNAL 0 ONLY.
Probe sub-menu.
Set INHIBIT to
17. Press START SYSTEM.
lB. When data acquisition is finished, enter the Timing Diagram
menu.
The display should again look like Figure 5-19.
19. Enter the Pattern Generator
INTERNAL 0 ONLY.
Probe sub-menu.
Set INHIBIT to
20. Press START SYSTEM.
21. When data acquisition is finished, enter the Timing Diagram
menu. The display should again look like Figure 5-19.
22. Enter the Pattern Generator Probe sub-menu.
to EXTERNAL 0 OR INTERNAL O.
Set the INHIBIT
23. Press START SYSTEM.
24. When data acquisition is finished, enter the Timing Diagram
menu. The display should again look like Figure 5-19.
(10) Verifying the EXTERNAL START Line
The following procedure verifies that the 91S32 responds to the
PG START signal through the external clock Probe.
1.
Connect the output of the pulse generator to the PG INTERRUPT
line (the orange line) on the P6452 external clock probe.
Set the signal generator for a 0 to +4 V signal, then set the
pulse width and duration for manual triggere
2.
Connect EXT START (orange lead) to the output of the pulse
generator.
3.
Set the pattern generator program to again match Figure 5-1B.
4.
Enter the Pattern Generator Probe sub-menu.
START ON rising edge.
5.
Press START SYSTEM, then manually trigger the pulse
generator.
5-42
Select EXTERNAL
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
6.
When displayed on the Timing Diagram menu, the data acquired
from the pattern generator should again look like the data
shown in Figure 5-12.
A display like Figure 5-12 means that the interrupt signal is
being properly received and processed. The next steps verify the
operation of the external start signal.
7.
Enter the Pattern Generator
START ON rising edge.
Probe sub-menu.
Select EXTERNAL
8.
Press START SYSTEM, then manually trigger the pulse
generator.
9.
When displayed on the Timing Diagram menu, the data acquired
from the pattern generator should again look like the data
shown in figure 5-12.
10. Disconnect the PG INTERRUPT line from the signal source.
11. Press START SYSTEM.
12. The display should show WAITING FOR 91A08 TRIGGER.
13. Press STOP.
(11) Verifying the PG eLK Line
The following procedure verifies the transmission of the PG CLK
signal through the external clock probe. These steps require the
use of an external clock source. The recommended clock source is
a square wave or pulse generator with an output that oscillates
between ground and +5 V with an 8 ns pulse width and a frequency
of 50 MHz.
1.
Connect the output of the signal generator to the PG CLK line
(brown) on the P6452 external clock Probe.
2.
The signal generator must have a common ground with the
probes. To accomplish this, connect the ground of the signal
generator to the two clips that connect the data acquisition
probe ground senses to the external clock probe ground line.
3.
Enter the Pattern Generator
START DISABLED.
Probe sub-menu.
5-43
Select EXTERNAL
Verif. & Adj. Procedures
DAS 9100 Series 91Sl6-91S32 Service
The probes and the signal generator are now connected and the
test can be performed.
4.
Enter the Pattern Generator Timing sub-menu.
generator clock to external rising edge.
Set the pattern
5.
Adjust the pattern generator program to again match Figure 518.
6.
Enter the Trigger Specification menu and set the acquisition
clock to external falling edge.
7.
Press START SYSTEM.
8.
When acquisition is complete, examine the Timing Diagram
menu. The data acquired from the pattern generator should
again look like the data shown in Figure 5-12.
A display such as Figure 5-12 indicates that the pattern
generator external clock is being properly received and
processed. The next steps verify the inversion operation of the
external clock signal.
9.
Enter the Pattern Generator Timing sub-menu.
generator clock to external falling edge.
Set the pattern
10. Press START SYSTEM.
11. When acquisition is complete, examine the Timing Diagram
menu. The data acquired from the pattern generator should
again look like the data shown in Figure 5-12.
(12) Verifying the PG PAUSE Line
The next steps verify that the 9lS32 responds to the PG PAUSE
signal through the external clock Probe. These steps require the
use of an oscilloscope and an external signal. The recommended
clock source is a square wave with a 10 microsecond period and an
output between ground and +5 V.
1.
Disconnect the strobe line from the inhibit line.
2.
Enter the Pattern Generator Timing sub-menu.
to 200 ns.
Set the CLOCK
3.
Enter the Pattern Generator Probe sub-menu.
to DISABLED. Set PAUSE to O.
Set the INHIBIT
5-44
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
4.
Connect the output of the pulse generator to the PG PAUSE
line (yellow) of the P6452 probe.
5.
Set up the oscilloscope as follows:
a.
Attach the probe for channel 1 of the oscilloscope to the
external signal and set sensitivity for 2 V/div.
b.
Attach the probe for channel 2 of the oscilloscope to the
P6464 probe clock podlet (podlet must also be grounded).
c.
Set the oscilloscope to trigger on a rising edge in
channelL
d.
Attach the ground leads of the probes to the ground of
the P6452 and the P6464 probe.
6.
Press START PAT GEN.
7.
The oscilloscope display should look like the one shown in
Figure 5-21.
5397-50
Figure 5-21.
PG PAUSB line response, PAUSB
5-45
= O.
Verif. & Adj. Procedures
DAS·9100 Series 91S16-91S32 Service
8.
Enter the Pattern Generator Probe sub-menu.
PAUSE ON 1.
9.
Press START PAT GEN.
Select
10. The oscilloscope display should look like Figure 5-22.
5397-51
Pigure 5-22.
PG PAUSB line response, PAUSE = 1.
5-46
Verif. & Adj. Procedures
DAS 9100 5eries 91516-91532 5ervice
91S32 PATTERN GENERATOR FUNCTIONAL CHECK WITH 91516
You will need the following equipment to perform this procedure:
DA5 9100 mainframe with Vl.ll firmware and 22 A +5
5upply
V
Power
91516 Pattern Generator Module
Two P6464 Pattern Generator Probes
P6460 External Clock Probe
P6452 Data Acquisition Probe
9lA08 Data Acquisition Module and P6454 100 MHz Clock Probe
+5
V
external power supply, Tektronix P5503A or equivalent
(13) Mainframe setup for the functional check of 91532 with
91S16.
The following procedures verifies the operation of a 91532 used
with a 91516.
~
Do not install or remove any electrical module or subassembly in a DA5 mainframe while the power is on.
Doing so can damage the module or sub-assembly.
1.
Turn off the mainframe.
2.
Install a 9lA08 Acquisition Module in slot 6.
3.
Install the 91516 in slot 4 of the mainframe.
5-47
Verif. & Adj. Procedures
DAB 9100 Series 91516-91532 Service
NOTE
J402 must be in place on the 9lA32, regardless of the
configuration.
Also, the mainframe will not operate with more than one
91516 Pattern Generator Module installed at the time of
power-up. Make sure there are no 91516 duplicates in
the mainframe.
4.
Install the 91532 to be checked in slot 3 of the DAS
mainframe. If there is another 9lS32 module in the main
frame, remove it.
5.
Place jumpers on J302, J304, J306, J30S, J3l0, J3l2, J3l4,
J3l6, J3lS, J320, J322, J324, J202, J204, and Jl02 of the
9lS32, then connect the flat cable from P2 of the 9lS16 to P2
of the 9lS32.
(14) Executing the Diagnostic Self-test
The following procedure runs all available self-test diagnostics
on the 9lS32 module.
1.
Turn on the mainframe while holding down the STOP key on the
keyboard. This will cause the power-up self-test to fail.
2.
Press START SYSTEM to enter the Diagnostics menu.
diagnostic tests for the 9lS32 module in slot 3.
3.
Select SINGLE mode, then run all functions.
4.
Repeat steps 2 and 3 for slot 4.
Select
(IS) Probe Setup for the Functional Check
1.
Connect a P6464 Pattern Generator Probe to POD connector A of
the 9lS32.
2.
Connect a P6464 Pattern Generator Pprobe to POD connector A
of the 9lSl6.
3.
Connect the Data Acquisition Probe to the 9lAOS Acquisition
Module.
5-4S
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
4.
Connect the pattern generator probe from the 91S32 to the
data acquisition probe with the diagnostic lead set.
S.
Connect the P6460 external clock probe to POD connector C of
the 91S16.
6.
Install a flying lead set in the P6460 external clock probe.
Connect the ground lead of the external clock probe to one of
the grounds of the P6464 Pattern Generator Probe.
7.
Connect the P6464 100 MHz clock probe to its connector on the
91AOS module in slot 6.
S.
Connect the IN line of the P6464 100 MHz clock probe to the
clock output of the 91S16~s Pattern Generator Probe.
9.
Connect the REF line of the P6464 100 MHz clock prQbe to the
unused GND SENSE line on the pattern generator probe of the
91S16.
10. Adjust the external power supply for +S V using a digital
multimeter. Connect common and ground together if a
Tektronix PSS03A Power Supply is used. Turn off the power
supply.
11. Connect one red lead from each P6464 probe to each +S V
source on the power supply.
(The Tektronix PSS03A can only
drive two probes.)
12. Connect all black and green leads from the P6464s together,
and connect them to the ground on the power supply.
13. Connect the power supply ground to all probe grounds and
V-ref leads of the podlets.
(16) Initial Menu Setup for the Punctional Check
The next steps organize the menus so that the remainder of the
functional check will require a minimum of menu manipulation.
1.
Leave the Diagnostics menu by pressing the PATTERN GENERATOR
key. In the Pattern Generator Program sub-menu, verify that
the pattern generator clock is set to 40 ns. Go to the
Timing sub-menu and select the 40 ns clock.
2.
Adjust the 91516 program in the Program sub-menu to match
Figure S-23.
S-49
Verif. & Adj. Procedures
DAB 9100 Series 91S16-91S32 Service
PATTERN !lHERATOR PROGRI1I:
IJIIlI
1m:
START SEQ:
INHIBIT
\IIASK : IJD.I
1JIBEL
SEQ
4B 4A S I "
SEQ F1JJtICOKTRrl.
_ _ DID 11 1111-;1"
1. 1998 98 00
1881
91 81
1982
82 02
1883
84 04
1884
98 08
1985
18 18
1986
28 28
1987
48 48
1888
88 88
1'19
FF FF
1018
88 98
1811
98 ee
1912
08 88
1913
98 ee
_ __
0
8
9
9
9
8
e
e
e
8
JUIf
1988
9
e
8
_.- :-"#i9
Pal •
5397-52
91S16 Prograa sub-menu setup, 91S32 with 91S16.
Pigure 5-23.
PATTERN IDERATOR PRtY'.aWI: . . .
...-1.
ItifIBIT
~
i@I"iiM'
D:3BA
---.,W.,--:
_
1881
1982
1883
1884
1985
1086
1987
POE:"
!'ta:a
START SEQ: A
e
S I
iijiiij'i"iiii' 1111
9 8
9181 8181 9 9
9282 9282 8 9
9484 94S4 8 e
9 9
1818 1818 e 9
2028 2828 e e
4848 4848 e e
8 8
FFFF FFFF 9 e
9 9
8 9
8 9
e 8
9888_
lees
1089
1818
1811
1812
1913
Pigure 5-24.
REfi,M
-.,IIWO_ Pm •
5397-53
91S32 Prograa sub-menu setup, 91S32 with 91S16.
5-50
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
3.
Set the 9lS32 pattern generator program to match Figure 5-24.
4.
In the Trigger Specification menu, set the acquisition clock
to external falling edge. The trigger word for the 9lA08 can
be left at DON~T CARE (X).
(17) Verifying POD Connector A of 91S32
The following procedure verifies that the 9lS32 can transmit data
through the POD connector A.
1.
Press the START SYSTEM key.
2.
Enter the Timing Diagram menu.
3.
Press the POD ID button on the back of the acquisition probe.
Read the POD number on the DAS screen. Adjust the Timing
Diagram menu to show data from this POD.
4.
Set the magnification of the Timing Diagram to 10. This
should create a display like Figure 5-25. The actual
position of the cursor and trigger will depend on the type of
acquisition module used. The 9lA08 should trigger on
sequence 18.
[aTH
~-i,-_~~
TI~:
'-~_---'r......_---'~
. l ____Jl.rL__..l'. .l.rL__
~__J"twL--J-U-L..--...i,.l_rL_IL..,j-L_._f
~
ri.__11_---i-LIL_IL_rL-...fl..--i-L-..IL
~
rlfL_---1r"'1J~
Lrl_Jl_Jl_--i-L-i-L-i~-t...-rL-l-L
e:
L-L-.I"L-l-i---J'""'L.IL_Jt_JL___1L. .rt_
lrL--l-LSL--.l1JL__---1l..IL_ILfL._
5397-54
Figure 5-25.
Timing Diagram menu, POD connector A.
5-51
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
(18) Verifying Clock Divider
The following procedure verifies that 9lSl6 can divide the clock
and send it to the 9lS32 pattern generator.
1.
Enter the Pattern Generator CONFIGURATION 9lS32 mode.
the 9lS32 MODE to SEQUENTIAL END SEQ A: 9.
2.
Set the 9lS32 pattern generator program to match Figure 5-26.
3.
Select the Trigger menu and select 1 microsecond for the
9lA08 clock.
PATTERH GEl£RA1TI PROGRAIf: . .
ItIUSll
Set
I'QE:"
PAGE: 11
STMTSEQ: . _
MASK : .-Il,IIIIII,'-m=-a-
. . . IICJIA
S I
_ 1 ·'''''iIi"1I1I
0181 0101 8 9
2
8Z92 8282 0 0
3
4
5
6
9484
9888
1918
2829
7
8
9
sesesese e e
6484
9888·
1818
2828
8
9
8
8
8
8
8
8
4948 ·4948 9 9
FFFF FFFF F. 8
IIMIIIII : •••llw#i_ poo •
5397-55
Pigure 5-26.
91832 Program sub-menu for clock divider test.
5-52
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
4.
Press START SYSTEM.
5.
When data acquisition is complete, enter the Timing Diagram
menu.
6.
Set the magnification of the Timing Diagram to 5. this should
create a display like Figure 5-27.
~:f=""LU
C~
fW£
rii _
6C6
6CS
6C4
6C3
6(;2
bel
6C0
I"" Y'!'f'trc· ~
\31.11·...,..;.,,· . . . .
~'SI](
SEQ:
lB
Laiii THE:
3'
I
L l-..l·l__rL-...f'L.-..l-L...,.J-L......J'L...J-L..-.lL-fL-J1. 8
M
LfllL.JdLJiil_JUL...nil...Jb'L_JIiL_JULJIJ'LJ'..Il_mL a
l.1UL_Jl.1L.lUi....JIJL.Jul_JUL....n,iLJi..n......1'u'LJ'u'L_il.l1.. a
tll.n_nJL.J1JLJuL1L.IL.....'Ln......I1..Jut...uu1..... n....'lJlJL a
!Ln_JLrwUl. . JLILi'Ul...fwUw'lJLJU1_n_iL1LJLn. e
I n_n_..lu'l.. . . p._n. . . .ll.JUut.....i1...iLti.Jl........ll.il.....JULlLUI.. a
L_ilJL_R1L....n..iL.....l'L'L....l'iJL.....l'ULJul.......l'IJLJLIL...l'lrL......JI.. 1
LJUl........JULJIlLJIlL........I'u'L-..!1Il......JUL......1UL.........'il'L.......'llL......ur
a
5397.56
Pigure 5-27.
~taing
Diagram menu for clock divided by 1.
5-53
Verif. & Adj. Procedures
DAB 9100 Series 91S16-91S32 Service
7.
Enter the Pattern Generator Configuration 91S32 sub-menu.
Set the 91S32 CLOCK to 91S16 DIVIDED BY 2.
8.
Press the START SYSTEM key.
9.
When data acquisition is complete, enter the Timing Diagram
menu. The display should look like Figure 5-28.
~:
i:'Oi"ii _
..
Q..ITO£S: . .
CURSOR SEQ:
18
raTA mE:
;;lI\.Y1 -
6C6
6C5
6(4
i
LrL.-fL.JL-1L_JL..1'L.JL_JLJ1-.iI'L_n. a
6C2
6(1
!iCe
Lr----P......IL--i1..JL.....r",-_fL_JL..n__Il.....fL
a
ii__n....IL.......JLJL.....J1...Il-....rt_JL......JU1...... e
L __lUL.......Jln
nn___rtrL............J'J!":""" 1
~
s
;
I
I
!
!
5397-57
Figure 5-28.
Tiaing Diagram .enu with 91816 clock divided by 2.
5-54
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
10. Enter the Pattern Generator Configuration 91S32 sub-menu.
Set the 91S32 CLOCK to 91S16 DIVIDED BY 4.
11. Press the START SYSTEM key.
12. When data acquisition is complete, enter the Timing Diagram
menu. The display should look like Figure 5-29.
TIlutl;
DI~
Wb:_
Q..ITQ£S: . .
SRCH =
Pm Of
~SEQ:
18
iE.Iii TIl'E:
~
~i_
6C6
6e S
6C4
6C3
6C2
6C1
6C9
5397-58
Pigure 5-29.
Timing Diagram menu with clock divided by 4.
5-55
Verif. & Adj. Procedures
DAB 9100 Series 91S16-91532 Service
(19) Verifying the PG INHIBIT Line from 91516 to 91S32
The following procedure verifies that the 91532 responds to the
PG INHIBIT signal through the external clock probe connected to
91S16.
1.
Connect the P6460 probe to the 91516.
2.
Connect the P6460 inhibit lead (red) to the P6464 strobe
output of 91S32 POD A.
3.
Enter the 91532 Pattern Generator menu. 5e1ect PROGRAM: RUN,
and set the INHIBIT MASK field in the Pattern Generator
Program menu to 0000 0000 (default).
4.
Enter the Pattern Generator Configuration: 91532 sub-menu.
Set 91S32 MODE to FOLLOWS 91S16. Set the 91532 CLOCK to
91S16 DIVIDED BY 1. Set the configuration clock to match
Figures 5-30 and 5-31.
5.
Set the Program sub-menus to match Figures 5-32 and 5-33.
5-56
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
PATTERN GEt£RATr:R COl'flGURATIOH: . . .
_.$:-
REGISTER:
Pm
148
P6464
_
OOTPUT LE1JB.
-
C 8 BITS =1
CLOCK
I
C 8 BITS =1
ClOCK
S1ROBE
ItliIBIT MSI( INHIBIT_
POLARITY
•
•
•
II
•
II
....
POD ClOCK
, 5397-60
Figure 5-30.
91S16 configuration clock setup for PG inhibit
test.
91532 CLOCK:
91532
pro
1 3D
2 3C
3
~
4 2+1
m:
91516 DIVIDED
FOlLOWS 91S16
P6464
IJJTPUT LEU
..
iii
iii
iii
~T
CLOCK
Pf..L«IT'T
•
•
•
•
lUI
tBRY RELIHJ FRet! trJST: i i i
( FIJ( KEEP-!i..II£ )
CLOCK
STm
ltiiIBIT !"ASK ItfiIBIT MASK
II
II
II
•
lUI
•
lUI
•
....
....
Fl"J.J CLO)(
5397-59
Figure 5-31.
91S32 configuration clock setup for PG inhibit
test.
5-57
Verif. & Adj. Procedures
DAB 9100 Series 91516-91532 Service
PATTERH GEHERATtR PRCtAAI'I:
l11li
I(U:"
STMT SEQ:"
ItIIISIT
MAS< : DDI
IJI8EL
SEQ
_
4B 4A
"
SEQ FlQW,COOR(l
BDlII. IIm"-
_
18 1009
1081
1002
1083
1804
1085
Ul86
1987
1988
1989
1919
1911
1912
1913
.'1Il'1I0!II :
Figure 5-32.
S I
08 00 9 9 9
91 91 9 9 8
92 92 9 9 e
94 84 9 8 9
98 88 9 9 9
19 18 a 9 8
2929 9 9 9
40 49 8 8 9
89 88 8 a 8
FF FF 9 9 9 ..JIJf
99 ee 9 9 9
98 08 e 9 9
89 98 9 a 9
08 98 9 8 8
REG,rur
. . __
Ul08
-mw,a- PIll •
5397-66
91516 Program sub-menu for PG inhibit test.
PATTERN GEt£RATIR PROGRAI1:
m= . .
Pta: II
IBII
START SEQ: A
INHIBIT
8
PIASK : "!j@!'il•
_ ... 11.
. . . 3DC3BA
1008
__
S I
9 9
1991
9181 8181 8 8
1882
0292 0282
9 9
1883
1004
9494 9494
0898 9898
8 9
8 8
1805
1918 1919 8 9
1996
2829 2929
9 8
1097
4948 4948
8 8
1811
__
8 8
1912
1013
9098 8088
09BB 0990
9 9
9 9
1098 . 9889 8989 9 e
1099 FFFF FFFF F e
1918 08B0 8899 9 9
.,w,1I11I : -lIllijlia_ PIll •
5397-67
Figure 5-33.
91532 Program SUb-menu for PG inhibit test.
5-58
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
6.
Enter the Pattern Generator Timing sub-menu.
to 50 microseconds.
Set the CLOCK
7.
Enter the Pattern Generator Probe sub-menu.
to EXTERNAL 1 ONLY.
Set the INHIBIT
B.
Enter the Trigger Specification menu and set the 91AOB clock
to EXTERNAL falling edge.
9.
Press START SYSTEM.
10. When data acquisition is finished, enter the Timing Diagram
menu and set the magnification factor to 10. The display
should look like Figure 5-34.
Q..ITa£S: . .
SRI)!
~SEQ:
=
prj) CH
~
I!i _
~,..
it
-.J
6C4
be2
61:1
61: a
n
n
n
n
c;
6C3
n
M
n
6(6
IjiJ
18
raTA TIl'E:
l ...nL.-..._....Inl..._---'n
!J1
f'l....
' _ - - 'f1
j"ll...!_---'nl..._---'f1
...
;;a,liI-_....n....._____
n
.
n
n
n
n
n
a
a
ra
11_ a
M
n_l!
!L
e
''---
1
n...... a
n
~
5397-68
Pigure 5-34.
Tiaing Diagram menu for the PG inhibit test.
5-59
Verif. & Adj. Procedures
DAB 9100 Series 91516-91532 Service
(20) Verifying the POD Delay
The following procedure verifies the POD to POD delay.
steps require the use of an oscilloscope.
These
1.
Connect the P6464 Pattern Generator Probes to PODs A and B.
2.
Enter the Pattern Generator Timing sub-menu. Set the pattern
generator clock to 200 ns.
3.
Enter the Pattern Generator Program sub-menu and program the
following.
SEQ
o
1
4.
0000
0000
FFFF
FFFF
o
F
0
0
Enter the Configuration sub-menu and enter END SEQ 1 FREE
ROO.
5.
Set up the oscilloscope as follows:
a.
Attach the probe for channel 1 of the oscilloscope to the
P6464 probe clock output of POD-A.
b.
Attach the probe for channel 2 of the oscilloscope to the
P6464 probe clock output of POD-B.
c.
Provide power to probes A and B.
d.
Set the oscilloscope to trigger on a rising edge in
channel 1 and set the sweep rate to 2 ns/div.
e.
Attach the ground leads of the probes to the V-ref of the
P6464 probe clock outputs.
6.
Press START PAT GEN.
7.
The rising edge of channel 1 and channel 2 should be
approximately the same.
5-60
Verif. & Adj. Procedures
DAB 9100 Series 91S16-91S32 Service
8.
Set the Pattern Generator Timing sub-menu POD CLOCK of 3A to
+5 ns using the INCR key.
9.
Press START PAT GEN.
10. The rising edge of channel 2 should occur 5 ns before the
rising edge of channell. See Figure 5-35 •
..,
rJ
~
~
~
5397-69
Pigure 5-35.
+5 ns POD delay_
5-61
Verif. & Adj. Procedures
DAB 9100 Series 91S16-91S32 Service
11. Set the Pattern Generator Timing sub-menu POD CLOCK for POD
5A to -5 ns.
12. Press START PAT GEN.
13. The rising edge of channel 2 should occur 5 ns after the
rising edge of c~anne1 1. See Figure 5-36.
,
1/
-V
~.,.
,....
5397-70
Pigure 5-36.
-5 DS POD delay.
5-62
Verif. & Adj. Procedures
DAB 9.100 5er ies 91516-91532 5ervice
14. Set the Pattern Generator Timing sub-menu POD CLOCK for SA to
o ns. Change the selected POD field from SA to 5B.
15. Set the Pattern Generator Timing sub-menu POD CLOCK for SB to
-5 ns.
16. Press START PAT GEN.
17. The rising edge of channel 2 should occur 5 ns before the
rising edge of Channell.
18. Set the Pattern Generator Timing sub-menu POD CLOCK for 5B to
+5 ns.
19. Press START PAT GEN.
20. The rising edge of channel 2 should occur 5 ns after the
rising edge of channell.
~
Do not move probes from pod to pod with the pattern
generator started. Doing so can damage the pattern
generator module.
21. Set the Pattern Generator Timing sub-menu POD CLOCK for SB to
o ns.
22. Move the P6464 pattern generator probe to POD connector C.
23. Set the Pattern Generator Timing sub-menu POD CLOCK for 5C to
-5 ns.
24. Press START PAT GEN.
25. The rising edge of channel 2 should occur 5 ns before the
rising edge of channell.
26. Set the Pattern Generator Timing sub-menu POD CLOCK for 5C to
+5 ns
27. Press START PAT GEN.
28. The rising edge of channel 2 should occur 5 ns after the
rising edge of channell.
5-63
Verif. & Adj. Procedures
DAB 9100 Series 91S16-91S32 Service
29. Set the Pattern Generator Timing sub-menu POD CLOCK for SC to
o ns.
30. Press START PAT GEN.
31. The rising edge of channel 2 and Channel 1 should
approximately coincide.
32. Make sure the pattern generator is stopped, then move the
P6464 Pattern Generator Probe to POD connector D.
33. Set the Pattern Generator Timing sub-menu POD CLOCK for 50 to
-5 ns.
34. Press START PAT GEN.
35. The rising edge of channel 2 should occur 5 ns before the
rising edge of channell.
36. Set the Pattern Generator Timing sub-menu POD CLOCK for 50 to
+5 ns.
37. Press START PAT GEN.
38. The rising edge of channel 2 should occur 5 ns after the
rising edge of channell.
39. Set the Pattern Generator Timing sub-menu POD CLOCK for SC to
o ns.
4.0. Press START PAT GEN.
41. The rising edge of channel 2 and channel 1 should
approximately coincide.
(21) Verifying the data delay
The following procedure verifies the clock-to-data delay.
steps require the use of an oscilloscope.
1.
Enter the Pattern Generator Program sub-menu and enter the
following program.
SEQ
o
1
2.
These
0000
FFFF
0000
FFFF
o
F
0
0
Enter the Configuration sub-menu and enter END SEQ 1 FREE
RUN.
5-64
Verif. & Adj. Procedures
DAB 9100 Series 91516-91532 Service
3.
Connect as many P6464 probes as can be powered by the +5 V
external power supply to the 91532, star ting at POD SA.
(The
Tektronix PS503A can power only two P6464s.)
4.
Set all clock delays in the Pattern Generator Configuration
sub-menu to 0 ns.
5.
Enter the Pattern Generator Timing sub-menu. Set the POD
field to SA. Set each data and strobe delay to +5 ns.
6.
Set up the oscilloscope as follows:
a.
Attach the probe for channel 1 of the oscilloscope to the
P6464 probe clock output of POD SA.
b.
Attach the probe for channel 2 of the oscilloscope to the
P6464 probe DATA 0 output of POD SA.
c.
Set the oscilloscope to trigger on a rising edge in
channel 2.
d.
Attach the ground leads of the oscilloscope probes to the
ground leads of the pattern generator probes.
7.
Press START PAT GEN.
8.
The rising edge of channell should occur 5 ns before the
rising edge of channel 2.
9.
Move the probe for channel 2 sequentially from DATA 0 through
DATA 1, 2, 3, 4, 5, 6, 7, and Strobe of POD SA. Each channel
waveform should be the same as the signal at DATA 0 output.
10. Repeat steps 4 through 8 for PODs 5B, 5C, and 5D.
This completes the functional check procedure for the 91532
Pattern Generator Module using a 91S32-on1y configuration.
~
Do not install or remove any electrical module or subassembly in a OAS mainframe while the power is on.
Doing so can damage the module or sub-assembly.
5-65
_~~4.
~
ftUJ.
~roceaures
DAS 9100 Series 91S16-91S32 Service
ADJUSTMENT PROCEDUBES
91S16 ADJtJS'rMBN'l PROCEDUBE
Test point and adjustment locations for this procedure can be
found in the 91516 Parts Location drawing in the Diagrams section
of this addendum.
DAC Adjustment for the P6460 Input Probe
The 91516 Pattern Generator uses one P6460 Probe. The threshold
level for the P6460 is adjusted on the 91516 module. The
following instruments are required for this adjustment.
Equivalent test instruments may be substituted.
NOTE
This adjustment cannot be performed unless DAe U320 (an
NE5018) is lot date number 8335 or smaller.
Equipment Required for Threshold Test
RecODIIIlended
Equipment
Specification
Type
DAS Mainframe
DAS 9100 Series
with Vl.ll
firmware and 22 A,
+5 V power supply
TM500 Mainframe
TM503 or higher
Digital Multimeter
0.05% dc V
~ccuracy
DM501
Main Extender
Board from DAS
Service
Maintenance Kit
Module Extender
Local
manufacture, see
following
procedure. See
also Figure 5-37.
*Threshold Fixture
*This is the same fixture used as a service tool for the
Tektronix 1240 Logic Analyzer. If you have the 1240 fixture, it
is not necessary to build another one.
5-66
ver~L.
~
aUJ.
c~~~~
__ ~_~
DA5 9100 Series 91516-91532 5ervice
Equipment Required for Threshold Fixture Construction
Qty.
Description
Part Number
1
Terminal Connector Holder
(2 holes by 8 holes)
352-0484-00
5
Mini PV Female Connectors
131-0484-00
1
Resistor, 10.5 K, 1%
321-0291-00
3
Wires, 26-gauge, l-inch
long
Construction Procedure.
follows:
Assemble the Threshold Fixture as
1.
Connect three of the Mini-PV connectors to three lengths of
wire.
2.
Connect the remaining two Mini-PV connectors to the resistor,
one at each end.
3.
Install the three wire/Mini PV connector combinations into
holes 1, 4, and 7 of the Terminal Holder Connector.
4.
Solder the three free ends of the wires together.
5.
Install the two ends of the resistor/Mini-PV connector
combinations in holes 13 and 16 of the Terminal Holder
Connector.
4342-38
Figure 5-37.
Threshold Fixture. (The arrow on the fixture
indicates the pin-l end.)
5-67
.~~~~.
~
AaJ.
~rocedures
DAS 9100 Series 91S16-91S32 Service
Threshold Adjustment. Adjust the 91Sl6 DAC threshold
according to the following procedure. This procedure assumes
that the 91Sl6 is installed on the DAS Main Extender Board, and
that the DAS is powered up.
DAC
~
Do not install or remove a module from the DAB
mainframe with the Pgwer turned on. Doing so can
damage the module.
1.
Install the threshold fixture into POD C (J140) of the 91Sl6.
NOTE
As a substitute for steps 2 through 5, use the DAS
Diagnostics. Select SINGLE mode and test function 6 in
the Diagnostics menu, then press START SYSTEM.
2.
Enter the sub-menu by pressing the START PAT GEN key and the
SETUP key.
3.
Select the VAR mode in the P6460 INPUT THRESHOLD field.
4.
Move the cursor to the voltage field to the right of VAR.
5.
Keep pressing the DECR key until you select becomes O.OOV.
6.
Press START PAT GEN.
7.
Connect the DMM high lead to test pin THRES, and connect the
low lead to GND.
8.
Adjust R390 for a DMM reading of 0.00 V +2 mV.
9.
Change the VAR value to +6.35 V (maximum value) with the INCR
key.
10. Press START PAT GEN.
11. Adjust R392 for -1.587 V +2 mV.
12. Set the VAR to -6.40 V (minimum value) with the DECR key.
13. Press START PAT GEN.
5-68
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~
~UJ.
C~~V~~W4~w
DAS 9100 Series 91S16-91S32 Service
14. Check for +1.600 V +6 mV by switching between the two range
extremes. Readjust-R390, if necessary, to equalize the
difference in voltage between the two settings within the
specified 6 mV.
15. Disconnect the DMM leads and remove the Threshold Fixture.
Adjusting Delay Lines in Clock Control
The 91S16 has a total of six different variable delay lines in
three different circuitry areas. There is one adjustment in the
register timing circuitry, three in the POD clock positioning
circuitry, and two in the deskew circuitry between the POD
clocks.
The following equipment is necessary to perform this adjustment
procedure.
DAS 9100 Series Mainframe with V1.11 firmware and 22A +5 V
power supply
DAS Main Extender Board
350 MHz oscilloscope with two channels
Two P6230 probes for the oscilloscope
+5 V Probe Power Supply, Tektronix PSS03A or equivalent
Alignment tool, p/n 003-1134-00
91Sl6/32 overlay for the DAS keyboard
NOTE
The same menu setup and equipment used to adjust these
delay lines is used for subsequent procedures.
~
Use only the alignment tool p/n 003-1134-00 or damage
to components may result.
5-69
----~.
~J. rLuceaures
DAB 9100 Series 91S16-91S32 Service
g
This procedure assumes that the 9lSl6 is installed on the DAS
Main Extender Board, and that the DAS is powered up and has
passed all diagnostics.
~
Do not install or remove a module from the DAS
mainframe with the power turned on. Doing so can
damage the module.
1.
Ensure power is off, then remove covers from all delay lines
on the extended 9lSl6.
2.
Connect one P6464 probe to POD connector A and another P6464
to POD connector B.
3.
Power up the DAS.
4.
Enter the Pattern Generator menu by pressing the PATTERN
GENERATOR key.
5.
Select the Pattern Generator Program sub-menu and write the
following program.
SEQ
o
1
LABEL
A
A
FF
00
B
FF
00
S
I
M
000
000
SEQ FLOW,
CON'lROL
JUMP
REG, Otrr
A
6.
Enter the sub-menu by pressing the SETUP key, then press
SELECT to enter the Timing sub-menu.
7.
Set the pattern generator clock to 200 ns.
Delay Line Adjustaent for the Pirst
Line
Latch~s
Clock in the Clock
1.
Attach the probe for channel 1 of the oscilloscope to TP2802, and connect probe ground leads to convenient GND test
points. (TP280 is the reference point for the system clock.)
2.
Attach the probe for channel 2 of the oscilloscope to TP6l02, and connect probe ground leads to convenient GND test
points.
5-70
Yt::'.L.L.a.._
-
....... J .
- - - - - - - - __ _
DAS 9100 Series 91S16-9lS32 Service
3.
Set the oscilloscope to trigger on channell.
4.
Press START PAT GEN.
like Figure 5-38.
Adjust the oscilloscope for a display
,.
J
~
...-
,
/
~
iIIIIIIi.
5397-71
Figure 5-38.
First-latch clock line delay.
5.
Adjust delay line DL800 so that the rising edge on channel 2
is 25.5 ns +1.0 ns after the rising edge on channell.
6.
Move the position of all remaining variable delay lines
except DL800 to approximate center.
5-71
------ - .... J. Cl.v,-"cuures
DAB 9100 Series 91S16-9lS32 Service
Adjusting Delay Lines for the Clock Line in the P6464 Probe
1.
Attach the probe for channel 1 of the oscilloscope to TP7202, and attach the probe for channel 2 to TP780-2. Connect
probe grounds to GND test points.
2.
Press START PAT GEN. Adjust delay line DL720 so that the
rising edge of channell is 3 ns +0.5 ns after the r~s~ng
edge of channel 2.
(Channell is-clock, channel 2 is data.)
See Figure 5-39. Replace cover on DL720.
3.
Move the probe for channel 2 to TP760-2. Adjust delay line
DL740 so that the rising edge in channel 2 is 0 ns +0.5 ns
after the rising edge in channell. Replace cover on DL740.
~
,,-
:"WI!"
--
W.
"- ~
5397-72
Figure 5-39.
P6464 clock line delay_
5-72
-
DAS 9100 Series 9lSl6-91S32 Service
Adjusting Delay Lines for the POD clock in Clock Positioning
1.
Enter the Timing sub-menu, then set the POD B clock delay to
-5 ns. Set POD A clock delay to 0 ns (default for POD A) •
See Figure 5-40.
-Ie -s
a +5 +18
I ~ ... ! .... j ••.. I ... _~
I
-1~
CH
a
CH
CH
CH
CH
CH
2
-5
----l
----'
3
---1
---1
4
5
6
S1TUE
~
+5
+18
..
I..
1.... 1.... 1.... 1.... 1
CH 1
ell 7
Figure 5-40.
!E..i~Y
I
i
----'
i
----'
---1
---1
---1
~
..
~
§
!I
";;l!
.
;;
•
'I!!"
~
5397-73
POD clock line delay line setup.
2.
Press START PAT GEN.
3.
Adjust delay line DL760 so that the r1s1ng edge in channell
is 5.0 ns +0.25 ns after the rising edge in channel 2. See
Figure 5-41. Reinstall cover on DL760.
5-73
DAS 9100 Series 91516-91532 Service
~
I
J
.,
~~ l1li"""
5397-74
Figure 5-41.
Clock line delay for delay line DL760.
5-74
"''i;;;'''~_",
- ---J- ----
DAS 9100 Series 91516-91532 Service
4.
Set POD B clock
START PAT GEN.
edge of channel
edge of channel
delay to +5 ns in the sub-menu and press
Adjust delay line DL780 so that the rising
1 occurs 5.0 ns +0.25 ns before the rising
2. See Figure 5=42.
.J
r
...,.
J ~
!f
5397-75
Figure 5-42.
Clock line delay for delay line DL780.
Delay Line Adjustment for the Last Latch Clock
1.
Move the oscilloscope channell probe to test point TP280-2,
and the probe for channel 2 to test point TP700-2.
2.
Select the Timing sub-menu, then set the POD A clock delay to
-5 ns.
Press START PAT GEN.
(Leave the POD B clock delay as
it is.)
5-75
U~ ~LUU
Series 91S16-91S32 Service
3.
Adjust delay line DL700 so that the rlslng edge of channel 2
occurs 35.0 +0.25 ns after the rising edge of channell; See
Figure 5-43.-
4.
Reinstall the cover on DL700.
l...)
r
....
I
-.J
5397-76
Pigure 5-43.
Clock line delay for DL700.
5-76
ver1r. ~ BO]. rLV~~UUL~~
DAS 9100 Series 91S16-91532 Service
91S32 ADJUSTMENT PROCEDURE
Test point and adjustment locations for these procedures can be
found in the Parts Location drawing in the Diagrams section of
this addendum.
Delay Timing Adjustment
You will need the following equipment to perform this procedure.
DAS 9100 5eries Mainframe with Vl.ll firmware and 22 A +5 V
power supply
DA5 Main Extender Extender Board
350 MHz oscilloscope with two channels
Two P6230 oscilloscope probes
Delay line alignment tool, pin 003-1134-00
~
Do not install or remove any electrical module or subassembly in a DA5 mainframe while power is on. Doing
so can damage the module or sub-assembly.
1.
Turn off the DA5 mainframe.
2.
Remove all 91532 or 91516 Pattern Generator Modules from the
mainframe.
3.
Adjust the square-pin shorting jumpers on the Main Extender
Board to accept a 91532 module (slots 1 through 6).
4.
Insert the Main Extender Board in the slot where the 91532
was removed. Install the 91532 to be tested on the extender.
Remove the covers from all delay lines on the 91532.
5.
Attach square-pin shorting jumpers J206 and J208 of the
91532.
5-77
--~~~.
~ nUJ.
rroceaures
DAS 9100 Series 91S16-91S32 Service
6.
Connect the four P6464 Pattern Generator Probes to the 91532.
7.
Turn on the DA5. After the power-up sequence is successfully
completed, enter the 91S32 Pattern Generator menu.
8.
Enter the Pattern Generator Timing sub-menu and set the clock
to 200 ns.
9.
Enter the Configuration sub-menu and select END SEQUENCE
2047, FREE RUN.
10. Check PODs A through D to ensure delays are 0 ns (default).
11. Connect oscilloscope probes and set up the oscilloscope as
follows:
a.
Channel 1 to TP500.
b.
Channel 2 to TP580.
c.
Connect probe grounds to GND test points near TP500 and
TP580.
d.
Trigger on a rising edge in channell.
12. Press START PAT GEN and adjust the oscilloscope to show a
display like Figure 5-44.
5-78
Verit. & AaJ. ~roceuu~e5
DAS 9100 Series 91516-91532 Service
~
...
If
~
--
~
5397-77
Figure 5-44.
91832 pre-adjustment setup.
13. Adjust DL240 so that the pulse delay between channell and
channel 2 is 4 ns (~O.25 ns). Reinstall the cover on DL240.
14. Connect the channell probe to TP580 and the channel 2 probe
to TP600. Set the oscilloscope to trigger on a rising edge
in channell.
(14)
(Tight specification): Connect the channell probe to the
P6464 probe clock output of POD A. Connect the channel 2
probe to the P6464 clock output of POD B. Attach the
ground leads of the oscilloscope probes to the grounds of
the P6464s. Trigger the oscilloscope on the rising edge of
channell.
15. Adjust DL260 so the pulse delay between channell and
channel 2 is 0 ns (+0.25 ns) see Figure 5-45. Reinstall the
cover on DL260.
-
5-79
_
___ j
•
... •
,-,,",,~"""u..Lt::::::i
DAS 9100 Series 91S16-91S32 Service
~
"
c,
~
~
5397-78
Pigure 5-45.
91S32 timing delay for DL260.
16. Move the channel 2 probe to TP620.
(16)
(Tight Specification): Move the channel 2 probe to the P6464
clock output of POD C. Attach the ground lead of the
channel 2 probe to the ground of the P6464 clock probe.
17. Adjust DL280 so that the pulse delay between channel I and
channel 2 is 0 ns (~O.25 ns). Reinstall the cover on DL280.
18. Move the channel 2 probe to TP640.
(18)
(Tight Specification): Move the channel 2 probe to the P6464
probe clock output of POD D. Attach channel 2 probe ground
to the ground of the P6464 clock probe.
19. Adjust DL300 so that the pulse delay between channell and
channel 2 is 0 ns (~O.25 ns). Reinstall the cover on DL300.
5-80
ve~~L.
~
~aJ.
rLU~~UUL~~
DAS 9100 Series 91S16-91S32 Service
Adjusting 5 ns POD-to-POD Delay
20. Connect the channell oscilloscope probe to TP580 and the
channel 2 probe to TP600. Connect the probe ground leads to
the grounds associated with those test points. Set the
oscilloscope to trigger on a rising edge in channel 2.
(20)
(Tight Specification): Attach the channell oscilloscope
probe to the P6464 probe clock output of POD A. Attach the
channel 2 probe to the P6464 probe clock output of POD B.
Attach the ground leads of the oscilloscope probes to the
grounds of the P6464 clock probes. Trigger the oscilloscope
on a rising edge in channel 2.
21. Select the Timing sub-menu and set POD A delay value to 0 ns,
and set POD B delay value to -5 ns.
22. Press START PAT GEN, then adjust the oscilloscope for a
display like Figure 5-46.
- ,
I
....
,..
~
5397-79
Figure 5-46.
Setup for -5 ns POD-to-POD delay adjustment.
5-81
ver~r. & AdJ. Procedures
DAS 9100 Series 91516-91532 Service
23. Adjust DL200 so that the pulse delay between channell and
channel 2 is 5 ns (~O.25 ns). Reinstall the cover on DL200.
24. Set the POD A delay to 0 ns and POD B delay to +5 ns. Trigger
the oscilloscope on a rising edge in channell.
25. Press START PAT GEN and adjust the oscilloscope for a display
like Figure 5-47.
-,
J
J
I
I
r
~
5397-80
Pigure 5-47.
Setup for +5 ns POD to POD delay_
5-82
J
DAS 9100 Series 91S16-91S32 Service
26. Adjust DL220 so that the pulse delay between channel land
channel 2 is 5 ns (~0.25 ns).
Resinstall the cover on DL220.
27. Connect the channel 1 oscilloscope probe to TP200 and the
channel 2 probe to TP500.
28. Adjust DLl40 so that the pulse delay between rising edges of
channel 1 and channel 2 is 33 ns (+0.5 ns).
See Figure 5-48.
Reinstall the cover on DLl40.
-
r
~
J
I""""
....
I
I
5397-81
Figure 5-48.
Oscilloscope display for DLl40 adjustment.
5-83
DAS 9100 Series 9l5l6-9lS32 Service
29. Set the clock in the Timing sub-menu to 20 ns and press START
PAT GEN.
30. Adjust DLl60 so that the pulse delay between the rising edge
of channell and the second rising edge of channel 2 is 31 ns
(+0.5 ns). See Figure 5-49. Reinstall the cover on DL160.
,
,--
~
~r
U
~~
~
Figure 5-49.
~
~
~
,
~
{ ~
~
,'\
~
l
~
~
~
I
I
~
~~
~
Oscilloscope display for DL160 adjustment.
5-84
DAS 9100 5eries 91516-91532 5ervice
31. Repeat the procedure for each 9lS32 in your system.
32. Disconnect the oscilloscope. Turn off the DAS mainframe,
remove the 9lS32 from the Main Extender Board, then remove
the Main Extender Board. Finally, reinstall the 9lS32 in its
slot.
This completes the 91532 delay timing adjustment procedure.
91532 Board 5kew Adjustment Without a 91516
The same equipment used to adjust the 9lS32 clock delay is used
in this procedure. This procedure assumes the clock delay
adjustment has been performed.
1.
Install jumpers on J206 and J20S of the first and last 9lS32
in the system.
(This is the standard jumper configuration
when no 91516 is present.)
2.
Remove covers from DL140 and DL160 on a 91532.
3.
Remove the Main Extender board and install two 9lS32s in
slots powered by a 22 A +5 V power supply.
4.
Connect P6464 probes to the 91532 POD A connectors.
5.
Connect the channell oscilloscope probe to TP5S0 of the
9lS32 in the slot closest to slot 7. Connect the channel 2
probe to TP5S0 of the 9lS32 to be adjusted.
(5)
(Tight specification): Connect the channel 1 oscilloscope
probe to the P6464 POD A clock output of the 91532 in the
maximum slot. Connect the channel 2 probe to the P6464 POD A
clock output of the 9lS32 to be adjusted. Ground the
oscilloscope probes to the V-ref of the P6464 clock podlets.
6.
5elect the Timing sub-menu and set the clock to 200 ns.
7.
Enter the Configuration sub-menu and select END SEQUENCE
2047, FREE RUN.
S.
Press START PAT GEN, then adjust the oscilloscope for a
display like Figure 5-45.
5-85
~J -
-
-
-_,,-'-&"".L
Ci:)
DAB 9100 Series 91S16-91S32 Service
9.
Adjust DL140 so that the pulse delay between channell and
channel 2 is 0 ns (+0.5 ns). Reinstall the cover on DL140.
10. Select the Timing sub-menu, set the clock to 20 ns, and press
START PAT GEN.
11. Adjust DL160 so that the pulse delay between channel 1 and
channel 2 is 0 ns (~0.5 ns). Reinstall the cover on DL160.
12. If another 91S32 is present, repeat the procedure for that
module.
(Work from first to third, first to fourth, etc.)
13. Turn off DAS power and remove the 91532 modules.
91S32 Board Skew Adjustment With a 91516
Equipment required for this procedure is the same as for previous
procedures. This procedure assumes the clock delay adjustment
has been performed on the 91516 and 91532 modules.
1.
Install square-pin shorting jumpers on JI02, J302, J304,
J308, J310, J312, J314~ J316, J318, J320, J322, J324, J202,
J204, J206, and J208 of the 91532.
HO'l'E
If multiple 91532s are inSEa:rled, position the 91532
with the jumpers furthest from the 91516.
2.
Connect the channell oscilloscope probe to test point TP720
on the 91516. Connect the channel 2 probe to TP580 on the
91532 to be adjusted.
(2)
(Tight specification): Connect the oscilloscope channel 1
probe to the P6464 POD A probe clock output of the 91516.
Attach the channel 2 probe to the P6464 POD A probe clock
output of the 91S32 to be adjusted. Connect oscilloscope
probe grounds to the P6464 grounds and podlet V-refs.
5-86
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
3.
SEQ
0
1
Set the 9lSl6 Pattern Generator menu to the Program sub-menu
and enter the following program.
Label
A
A
B
00
00
00
00
S
0
0
I
0
0
M
0
0
SEQ FLOW, CONTROL
~G,
O~
JUMP
4.
Select the Timing sub-menu and set the clock to 200 ns.
5.
Press START PAT GEN and adjust the oscilloscope for a display
like Figure 5-45.
6.
Adjust DL140 on the 9lS32 so that the pulse delay between
channell and channel 2 is 0 ns (+0.5 ns).
This completes all 9lSl6 and 9lS32 adjustment procedures.
Disconnect the test equipment and restore the DAS to the standard
operating configuration.
5-87
Verif. & Adj. Procedures
CAS 9100 Series 91S16-91S32 Service
P6464 TTl/ECl PATTERN GENERATOR PROBE CHECK
You will need the equipment specified in Table 5-1 (or equivalent) to complete this check procedure.
Table 5-1
EQUIPMENT NEEDED FOR THE P6464 PERFORMANCE CHECK
Equipment
DAS 9100 Mainframe with firmware version 1,11 and upgraded
+5 V module for 91S16/S32
slots
No substitute allowed
91S16 or 91S32 Pattern
Generator Module
No substitute allowed
Pulse or square wave generator
Power Supply
Programmable Universal
Counter/Timer
Equivalent
Tektronix Instrument
Specifications
Tektronix part number 020-0707-01
100 MHz pulse rate. min.
Output swing between +5 V
and ground.
PG 502
Min output ± 5 V @ 1 A
PS 503A
Capable of measuring 125
MHz
DC 5010 or DC 503A
P6460 Data Acquistion Probe
with flying lead set
No substitute allowed
P6462 Clock Probe with flying
lead set
No substitute allowed
Oscilloscope
Min. 350 MHz bandwidth
485
82
n resistor
0.2SW.5%
Tektronix part number 315-0820-00
51
n resistor
0.25W,5%
Tektronix part number 315-0510-00
BNC T
Tektronix part number "1 03-0030-00
Probe Tip to BNC Adapter
Tektronix part number 013-0084-01
For instructions on use of the various menus, refer to the Operating information section of this manual.
(1) Mainframe Setup using the 91516
Use the following procedure to setup the DAS mainframe for this performance check procedure using the
91S16.
5-88
Verif. & Adj. Procedures
CAS 9100 Series 91S16-91S32 Service
WARNING
I
Do not install or remove any electrical module or sub-assembly in a DAS
mainframe while the power is on. Doing so will probably damage the module
or sub-assembly.
1. Turn off the DAS mainframe.
2. Install the 91S16 module in any slot powered with the upgraded +5 V module.
3. Connect the P6464 TTUECL Pattern Generator Probe to pod connector A on the rear edge of
the 91 S16 module.
4. Connect the P6460 Data Acquisition Probe to pod connector C on the rear edge of the 91 S16
module.
5. Turn on the DAS mainframe.
6. Enter the Setup:timing menu and set the clock to External S.
7. Enter the Setup:probe menu and set the P6460 Input Threshold to ECL.
8. Enter the Configuration menu and set the P6464 for ECL.
(2) Maximum Frequency Verification using the 91S16
The following procedure verifies the operation of the probe at 50 MHz, using the 91S16 card.
1. Connect a scope to the output of the pulse generator using a BNC-T to BNC-probe adapter.
2. Connect the P6460 external clock (black lead) to the unused side of the BNC T.
3. Set the pulse generator as follows:
PERIOD to 10 ns
PULSE DURATION to 5 ns
BACK TERM out
LEVEL OUTPUT (VOLTS) to -3
HIGH LEVEL OUTPUT (VOLTS) to 2
NORM/COMP switches set to NORM
4. Using the multimeter, set the power supply for outputs of +2 V and -3 V. Ground the common
terminal.
5. Set the programmable counter/timer as follows:
CHANNEL A TERM switch to 50 11
CHANNEL A COUPL switch to DC
CHANNEL A SLOPE switch to +
AVGS to 2
5-89
Verif. & Adj. Procedures
DAS 9100 Series 91S16·91S32 Service
6. Connect CHANNEL A of the counter/timer to the output of the pulse generator.
7. Push the AUTOTRIGGER switch of the pulse generator. Adjust the frequency of the pulse
generator to 50 + MHz, and observing the scope, adjust the pulse width to 7 ns.
8. Connect the P6464 VH (red) to +2 V, Vl (black)to -3 V, and GND (green) to common on the
power supply.
9. Connect the P6464 clock channel podlet to the counter/timer CHANNEL A.
10. Press the counter/timer PERIOD A and AUTO TRIG switches.
11. Press START PAT GEN on the DAS.
12. The counter/timer should read
~
20 ns or
~
50 MHz.
(3) Eel Mode Verification using the 91S16
The following procedure verifies each channel for ECl mode.
1. Program the 91 S16 card for ECl mode.
2. Adjust the power supply for V +
3. Connect the 51
n resistor
= 2
and V -
-3.
=
in parallel with the scope probe.
4. Connect the scope probe to the SIGNAL OUT of the channel 0 podlet. Connect REF of the podlet to the power supply common.
5. Press the START PAT GEN key on the DAS mainframe.
6. Measure the high and low voltage levels of the signal.
70 The low level should be below .35 V and the high level should be above 1 V.
8. Measure each of the remaining channels
(4) TTL Mode Verification using the 91S16
The following procedure verifies each channel for TTL mode.
1. Program the 91 S 16 card for TTL mode.
2. Adjust the power supply for V + = 2.6 and V 3. Connect the 82
n resistor
=
-2.4.
in parallel with the scope probe.
4. Connect the scope probe to the SIGNAL OUT of the channel 0 podlet. Connect REF of the podlet to common.
5. Press the START PAT GEN key on the DAS mainframe.
6. Measure the high and low voltage levels of the signal.
7. The low level should be below -1.65 V and the high level should be above 1.1 V.
8. Measure each of the remaining channels.
5·90
Verif. & Adj. Procedures
CAS 9100 Series 91516-91532 Service
(1) Mainframe Setup using the 91532
Use the following procedure to setup the DAS mainframe for this performance check using the
91 S32.
1. Turn off the DAS mainframe.
2. Install the 91 S32 module in any slot powered with the upgraded +5 V module.
3. Connect the P6464 TIL/ECl Pattern Generator Probe to pod connector A on the rear edge of
the 91 S32 module.
4. Connect the P6452 to the rear edge of the Trigger/Timebase card.
5. Turn on the DAS mainframe.
6. Enter the Setup:timing menu and set the clock to External S.
7. Enter the Setup:probe menu and set the P6452 Input Threshold to ECL.
S. Enter the Configuration menu and set the P6464 for ECL. Set END SEQ to 1 and FREE RUN.
9. Enter the Program:run menu set a O-F-O-F pattern for the pod by setting SEC 0 to all Os and 1 to
all Fs.
(2) Maximum Frequency Verification using the 91532
The following procedure verifies the operation of the probe at 50 MHz, using the 91 S32 card.
1. Connect a scope to the output of the pulse generator using a BNC-T to BNC-probe adapter
2. Connect the P6452 PG ClK (brown lead) to the unused side of the BNC T.
3. Set the pulse generator as follows:
PERIOD to 10 ns
PULSE DURATION to 5 ns
BACK TERM out
lOW lEVEL OUTPUT (VOLTS) to -3
HIGH LEVEL OUTPUT (VOLTS) to 2
NORM/COMP switches set to NORM
Add a 50 Q terminator to the OUTPUT
4. Using the multimeter, set the power supply for outputs of +2 V and -3 V. Ground the common
terminal.
5. Set the programmable counter/timer as follows:
CHANNEL A TERM switch to 50 Q
CHANNEL A COUPL switch to DC
CHANNEL A SLOPE switch to +
AVGS to 2
6. Connect CHANNEL A of the counter/timer to the output of the pulse generator.
5-91
Verif. & Adj. Procedures
CAS 9100 Series 91S16-91S32 Service
7. Push the AUTOTRIGGER switch of the pulse generator. Adjust the frequency of the pulse
generator to 50+ MHz and, observing the scope, adjust the pulse width to 7 ns.
8. Connect the P6464 VH (red) to +2 V, and Vl (black) to -3V, and connect the GND (green) lead
to common on the power supply.
9. Connect the P6464 clock channel pod let to the counter/timer CHANNEL A.
10. Press the counter/timer PERIOD A and AUTO TRIG switches.
11. Press START PAT GEN on the DAS.
12. The counter/timer should read
~
20 ns or
~
50 Mhz.
(3) Eel Mode Verification using the 91S32
The following procedure verifies each channel for ECl mode.
1. Program the 91 S32 card for ECl mode.
2. Adjust the power supply for V + = 2 and V -
= -
3.
3. Connect the 51 Q resistor in parallel with the scope probe.
4. Connect the scope probe to the SIGNAL OUT of the channel 0 podlet. Connect REF of the podlet to the power supply common.
5. Press the START PAT GEN key on the DAS mainframe.
6. Measure the high and low voltage levels of the signal.
7. The low level should be below .35 V and the high level should be above 1 V.
8. Measure each of the remaining channels.
(4) TTL Mode Verification using the 91S32
The following procedure verifies each channel for TTL mode.
1. Program the 91 S32 card for TTL mode.
2. Adjust the power supply for V + = 2.6 and V 3. Connect the 82
Q
=
- 2.4.
resistor in parallel with the scope probe.
4. Connect the scope probe to the SIGNAL OUT of the podlet of channel O.
5. Press the START PAT GEN key on the DAS mainframe.
6. Measure the high and low voltage levels of the signal.
7. The low level should be below -1.65 V and the high level should be above 1.1 V.
8. Measure each of the remaining channels.
5-92
Verif. & Adj. Procedures
CAS 9100 Series 91516-91532 Service
SERVICE INFORMATION
VERIFYING INSTALLATION OF THE UPGRADED
+ 5 V POWER SUPPLY
DAS 9100 mainframes can be configured using either an upgraded or an original-design + 5 V
power supply. The original + 5 V power supplies provide up to 18 amps current, while the
upgraded + 5 V power supplies provide up to 22 amps. 91 S16 and 91 S32 Pattern Generator
modules require power from the upgraded + 5 V power supply. Therefore, it may be necessary to
determine which + 5 V supplies are installed in your DAS.
A fully configured DAS contains three + 5 V power supplies; each supply provides power to two
module slots. 91 S 16 and 91 S32 Pattern Generator modules must be installed in slots supplied by
the upgraded high-current + 5 V power supply. Other DAS modules may not require this supply.
You may want to install only enough upgraded + 5 V power supplies to satisfy your 91 S16 and
91 S32 modules, and then restrict module placement accordingly.
DAS 9100 instruments with the following serial numbers and greater will automatically have the upgraded power supply installed:
• Monochrome DAS 9109, serial numbers 8050326 and higher
• Color DAS 9129, serial numbers 8060100 and higher
• DAS 9119, serial numbers 8010102 and higher
To identify the
+
5 V power supply models in your mainframe, proceed as follows:
Remove Top Panel and Covers
Figure 5-50 illustrates how to remove the top panel and the module compartment cover.
1.
Loosen the two large slotted screws in the upper corners of the back panel. Rotate me
brackets behind these screws until they no longer block the edge of the top panel.
2.
Press backward on the ridges at the front of the top panel. Simultaneously, pull on the rear
edge until the front disengages.
3.
Lift the panel up and off the mainframe.
NOTE
Step 4 is not necessary if you do not need to determine the position of the
91S16 and 91S32 modules.
4.
Loosen the slotted-head screws that secure the module compartment cover until approximately 1/4 inch of each screw is exposed. Grasp the front edge of the cover and lift it off the
mainframe.
5-93
Verif. & Adj. Procedures
DAS 9100 Series 91S16·91S32 Service
Figure 5·50. Removing the_ top panel and the module compartment cover
I WARNING
I
The power supply cover should be removed only by qualified service personnel. Hazardous voltages may be present; use extreme caution. Be sure
power is off and the power cord is disconnected before removing the cover.
There are three holes located in the power supply cover. Chrome pins show through these holes to
indicate the position of the + 5 V power supplies already installed. Locate these pins without
removing the power supply cover; if all three pins are present, the DAS contains three + 5 V power
supplies; this does not necessarily mean that upgraded + 5 V power supplies are installed.
• The + 5 V power supply module in the left position (adjacent to the main power supply)
provides power to bus slots 1 and 2; this power supply is provided as a part of the basic DAS
mainframe.
• The
+
5 V power supply module in the center position provides power to bus slots 5 and 6.
• The + 5 V power supply in the right position (closest to the instrument modules) provides
power to bus slots 3 and 4.
5·94
Verif. & Adj. Procedures
DAS 9100 Series 91S16-91S32 Service
Remove Power Supply Cover
WARNING
I
DANGEROUS VOLTAGES ARE PRESENT ON THE CAPACITOR BRACKET BOARD DURING OPERATION AND FOR FIVE MINUTES AFTER
POWER-DOWN. Each filtering capacitor can hold a 160 V charge. Wait at
least five minutes for the capacitors to discharge before accessing the power
supplies or related assemblies.
1.
Remove the flat-head, POZIDRIVE screws that secure the power supply cover.
2.
Uft the cover up and off.
Identify Power Supply Models
Refer to Figure 5-51 and identify the + 5 V power supplies that serve the DA5 bus slots where
91516 and 91532 modules reside. If original 18 amp + 5 V power supplies are installed, contact
your Tektronix sales representitive to obtain an upgraded 22 amp + 5 V power supply.
NOTE
If you have a color DAS, and you need to obtain upgraded 22-amp + 5 V
power supplies, you must also obtain the accompanying EMI kit. The EMI kit
contains a shield that is placed between the color CRT gun and the +5 V
module compartment. The EM' kit is not necessary for monochrome DAS's.
Part-number tags are fastened to the back of the chassis on each + 5 V power supply. Part
numbers 620-0296-00 are for the original-design 18 amp models. Part numbers 620-0296-01 and
up are for the upgraded 22 amp models.
ORIGINAL +5 VOLT~
PS MODULE
."
18 AMP. .\ T
UPGRADED +5 VOLT
PS MODULE
22 AMP.
~
5396·52
Figure 5-51. Identifying the
5-95
+
5 V power supply.
Section 6
MAINTENANCE: GENERAL INFORMATION
Tektronix maintains repair and recalibration facilities at its
local Field Service Centers and at the Factory Service Center.
For further information or assistance, contact your local
Tektronix Field Office or representative.
NOTE
Refer to the DAS 9100 Series Service Manual for general
maintenance procedures and precautions. Only new or
changed maintenance information is included in this
addendum.
Maintenance Precautions
The general maintenance precautions for 91Sl6 and 91S32 Pattern
Generator modules are nearly identical to those of other DAS
instrument modules. Observe the following special precautionary
measures while performing maintenance on the 91Sl6 or 91S32.
~
Do not ground signal test points; this will damage ECL
outputs.
Do not connect the P2 ribbon cable while DAS power is
on; this action will damage the line drivers in the
91S16 (or in the master 91S32 if a 91Sl6 is not used).
Do not connect P6464 probes while the pattern generator
is running; this will damage probe circuits.
Podlets are extremely static-sensitive. Handle them
only in a static-free environment, and make sure you
are grounded while handling them.
Do not operate a 91Sl6 or 91S32 on an extender without
an external fan blowing air on the component side of
the board. Heat will build up and damage the boards.
Do not subject variable delay lines to cleaning
solutions. Doing so will degrade delay-line
performance.
6-1
"'~Cl.LlU;.: l..7enera.l ~nt:ormation
DAS 9100 Series 91S16-91S32 Service
Installing and Removing Instrument Modules
~
The 91S16 and 91S32 modules are fragile. Be very
careful when removing or installing these modules. Be
especially careful not to exert excessive pressure, or
to flex the modules when they are extended for
maintenance. Pressure or flexing will cause broken
board runs and separated component connections.
The procedure for installing or removing 91S16 and 91S32 modules
in a DAS mainframe is nearly identical to that of any other DAS
instrument module. For specific information on module
installation or removal, see the Operating Instructions section
of this addendum.
INSTALLATION SLOT RESTRICTIONS
Power to the DA5 mainframe slots in which a 9lS16 or 91532
resides must be provided by a DAS 22 A, +5 V Power Supply.
Earlier DAS power supplies with less current capability cannot
supply these modules.
Preventive and Corrective Maintenance
Preventive maintenance procedures for 91Sl6 and 9lS32 modules and
probes are the same as preventive maintenance procedures for
other modules and probes in the DAS system. Refer to the DAS
9100 Series Service Manual for this information.
~
Do not brush the module while rinsing with isopropyl
alcohol. Brushing causes the solder residue to adhere
to the board where it remains after the alcohol
evaporates. This can degrade operation by causing
leakage between the board runs. While rinsing the
module with isopropyl alcohol, be especially careful to
avoid getting the solution on or near the variable
delay lines.
6-2
Maint: GeneraL ~n~orma~1on
DAS 9100 Series 91S16-91S32 Service
When cleaning a 91Sl6 or 91S32 module after soldering, perform
the following steps.
1.
Flush the module repeatedly with isopropyl alcohol (do not
brush). DO NOT ALLOW "l'RE SOLUTION TO GET ON, OR NEAR, "l'RE
VARIABLE DELAY LINES.
2.
Wait 60 seconds after flushing, then blow-dry with lowvelocity air.
REPAIRING 91S16 AND 91S32 MODULES
Repair procedures for 9lSl6 and 9lS32 modules are generally the
same as those for the other DAS modules. Refer to your DAS 9100
Series Service Manual for these procedures. However, observe the
precautionary measures stated in the Maintenance Precautions
provided earlier in this section.
When extending a 9lSl6 or 9lS32, use extender ribbon cable pin
175-9782-00 instead of the standard ribbon cable.
~
When operating a 9lSl6 or 9lS32 on an extender, blow
air onto the component side of the board with an
external fan. Without the external fan, excissive heat
will build up and damage the board.
Repackaging Information
All DAS 9100 Series products are shipped in specially designed
transportation packaging. If you need to ship a product, use its
original packaging. If the original packaging is no longer fit
for use, contact your nearest Tektronix Field Office and obtain
new DAS packaging.
If you need to ship any part of your 91516/91532 Pattern
Generator system, include all components of the system: all 91516
and 91532 modules, and their probes, podlets, and leads.
6-3
Maint: General Information
DAS 9100 Series 9lSl6-9lS32 Service
When you ship a product to a Tektronix Service Center, be sure to
attach an identifying tag to the product (inside the packaging).
On this tag include:
your name,
the name of your company,
the name and serial numbers of the enclosed products,
a detailed description of all failure indications,
and a description of the service requested.
DISASSEMBLY OF THE P6464 PROBE
The following steps are used to disassemble the P6464.
1. With a small flat-blade screwdriver, unlatch the latches
located on the side of the P6464.
2. Grasp the top and bottom halves of the probe and pull.
The inside is now exposed for troubleshooting. The heat sink and
plate must stay in place if you need to troubleshoot the probe.
If desired, the boards can be pulled from the case.
~
The hybrid and podlets are static sensitive. Full
static precautions should be used when handling the
probe.
3. Using a small pozidrive screwdriver, unscrew the four screws
holding the heats ink to the hybrid.
4. Pull up the heats ink and the plate underneath to expose the
hybrid. The hybrid can now be replaced.
Assembly of the P6464 Probe is in the reverse order.
6-4
Section 7
MAIN'rBNANCE: TROUBLESHOOTING
Refer to Section 8, Maintenance: Diagnostic Test Descriptions.
Use the description of the failed function and test, along with
the schematics, to analyze the failure.
7-1
Section 8
MAINTENANCE: DIAGNOSTIC TEST DESCRIPTIONS
This section contains information on troubleshooting the 91Sl6
and 91S32 Pattern Generator modules using the DAS diagnostics.
91S16 PATTERN GENERATOR DIAGNOSTICS
THE DIAGNOSTICS MENU
The DAS diagnostics present information in two menus: the powerup display and the Diagnostics menu.
The DAS self-diagnostics are only accessible when the power-up
display shows that one of the modules has failed the power-up
diagnostics. The power-up diagnostics are a limited number of
brief functional tests that are run whenever the DAS is turned
on. These tests verify the basic functions of the DAS, but should
not be considered comprehensive.
It is possible for a module in the DAS to fail in such a way that
the power-up diagnostics do not detect the failure. To access the
self-diagnostics in this situation, the operator can induce a
diagnostic failure from the keyboard (except the shift key) from
the time the DAS is turned on to the time the power-up
diagnostics are finished.
NOTE
Do not press any key other than the START SYSTEM key.
If you do, you may leave the power-up display and lose
access to the Diagnostics menu. The only time the
diagnostics are accessible is when the power-up display
shows a failure.
The Diagnostics menu is controlled in the same way as the
standard menus. All changeable fields are shown in reverse
video. Fields are changed by moving the blinking screen cursor to
the field to be altered. Cursor movement is controlled by the up,
down, right and left cursor arrows, and the NEXT key. The value
in the field is changed either by using the SELECT key, or by
entering a hexadecimal value from the data entry keys.
After the various fields have been changed to run the desired
test, the test can be started by pressing the START SYSTEM key.
A test can be stopped at any time by pressing the STOP key.
8-1
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
The Diagnostics menu may be exited by pressing any menu selection
key while no tests are running. This will display the selected
menu on the screen. The diagnostics cannot be re-entered from the
standard menu displays.
DIAGNOSTICS CONTROL SUMMARY
In summary, the diagnostics are controlled in the following waYe
1. A power-up diagnostics failure is forced by pressing and
holding down a keyboard key immediately after the DAS is
turned on.
2. The START SYSTEM key is pressed to enter the Diagnostics menu.
3. The reverse video fields on the display are changed to the
desired values using the cursor control keys and the data
entry keys.
4. The START SYSTEM key is pressed to start the diagnostic test
or function.
5. The function will either stop by itself, or the STOP key may
be pressed to stop the function at any time.
6. The Diagnostics menu may be exited at any time by pressing a
menu selection key while no tests are running. The DAS must be
turned off or reset to re-enter the Diagnostics menu.
ORGANIZATION OF DIAGNOSTIC FUNCTION AND SUBTEST DESCRIPTIONS
Information on the diagnostic functions is organized as follows:
1. A listing of quick reference diagnostic function descriptions
is given for the 91S16.
2. Each diagnostic function and its subtests are described in
detail.
8-2
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
There are six diagnostic function descriptions. They are as
follows:
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
0
1
2
3
4
5
6
CLK PATH (Clock Path)
MEM ADDR (Memory Address)
VECTOR RAM
REGISTER
INSTR (Instructions)
INTERRUPT
DAC THRESH (Threshold)
Each of the above functions contains one to seven subtests. All
of the functions above and their subsets are run on the 9lSl6.
QUICK REFERENCE FUNCTION DESCRIPTIONS
The following list briefly describes the diagnostic functions for
the 9lSl6 Pattern Generator module. If functions are run
individually, they should be run in the listed order under the
module type. Only the functions for the module in question need
be run.
The tests in each function can be selected individually only when
the diagnostics are in a looping mode using the SELECT key.
CLK PATH
This function verifies that a clock is given to the last latches
from the input clock selector through the main clock line. Most
of the circuitry tested by this function is shown on schematics
93, 98 and 99.
MEM ADDR
This function verifies the operation of the program counter and
the register for selecting a memory. This test checks the
circuitry that addresses the vector and micro-code RAMs. Most of
the circuitry tested is shown on schematics 95, 96 and 100.
8-3
Maint: Diagnostic Test Descriptions
DAS 9100 8eries 91816-91832 Service
VECTOR RAM
This function verifies the vector and micro-code memory and
checks associated write and readback circuits. The VECTOR RAM
function tests all RAMs that are used by the 91Sl6 to generate
any pattern. Most of the circuitry tested by the VECTOR RAM
function is shown on schematics 96, 97 and 100.
RBGIS'l'BR
This function verifies the operation of the two registers. Most
of the circuitry tested by the REGISTER function is shown on
schematic 96, 97 and 100.
lNSH
This function verifies the instructions controlling a program
flow and checks associated circuitry. Most of the circuitry
tested by the INSTR function is shown on schematic 94, 95, 96 and
97.
This function verifies the operation of the stack and the CALL
IRQ and RETURN instruction. Most of the circuitry tested by the
INTERRUPT function is shown on schematic 94, 95, 96 and 100.
'l'IIRBSH
This function tests the DAC that specifies threshold levels on
the data acquisition probes. This function exercises the DAC to
verify the voltage accuracy, and to make sure all voltages may be
selected. The circuitry exercised by this function is on
schematic 94. Since there is no readback in the DAC THRESH
circuitry, a diagnostic routine is provided to aid in adjustment.
This test requires the technician to monitor specified test
points while the test is running.
91S16
PUR~IOR
0 CLK PATH
Circuit OVerview
A clock is sent to the last latches through the clock selector,
PAUSE circuitry, HALT circuitry, some gates and some delay lines.
The controller gives a step clock, and a clock is received at
flip-flop after the last gate.
8-4
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Function Description
A clock is controlled by such signals as PAUSE, HALT, etc. This
function verifies that a clock is transferred to the last latch
by using a step clock.
Tested circuitry includes
U206, U640C, U208, U2l6B, U2l4, U2l8 (Schematic 93)
U502 (Schematic 96)
DLB20, U802B, DLBOO, U802D (Schematic 99)
DL700, U700B, DL760, U702B (Schematic 98)
U7l6A, U954, U960 (Schematic 93 & 100)
Readback Ports
The 91Sl6 reads the level of U7l6-2, before and after a step
clock is generated. A status is read from U952 and U960. When
U900-l2 (read8(H»
is asserted, U952 is enabled, and the status
is read from U960 on the data bus (BDO-BD7).
Test Run Sequence
1. Disables PAUSE line and HALT line.
2. Select the step clock mode.
3. Read a status from port hex04 after U952 is enabled.
4. Send a clock by writing to port hexOE.
5. Read the status.
Reading the Error Code
Both expected and actual value should be 00 or 02.
8-5
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91816-91532 Service
Error Indication
If this function has failed, set the LOOPING field to ON, and
check for a clock signal along the path with an oscilloscope.
While the test is running, the controller sets a level at each
point as follows:
CKT t
U206
U208
U214
U218
U954
pin t
level (ECL)
7
L
9
10
H
H
7
7
7
7
L
L
L
3.7V
For setting U208-7 to a low level:
CKT t
pin t
U820
U222
U212
10
11
4
5
7
U638
level (EeL)
L
H (TTL)
H
L
L
For setting U954-7:
CKT t
pin t
U502
U900
12
2
19
5
16
6
15
9
12
level
(TTL)
H
L
L
L
L
L
L
L
L
8-6
Maint: Diagnostic Test Descriptions
DAS 9100 5eries 91516-91532 5ervice
91516 FUNCTION 1
HEM ADDR
Circuit Overview
The program counter consists of a 10 bit up-counter (composed of
three individual counters) which supplies the address for all
memory. When the counter exceeds the maximum count (3FF) , a
status bit (COUNT OVER) is set. As the DA5 has an 8 bit bus line,
the micro-code and vector memories are shared every 8 bits for
read/write. Then the 91516 has selection lines for setting which
memory is read or written.
Function Description
The MEM ADDR function consists of three tests.
Test a writes a value to the program counter (U4l0, U4l2, U4l4)
and resets it. The PC count is then read back.
Test 1 exercises the PC to count from 000 to 3FF, and reads back
the result every clock. This test also runs on power-up and
verifies the count from hex2AA to hex3FF.
Test 2 writes a value to a memory, and checks each address line
and memory selection line.
Readback Ports
The output of the program counter is read through U934-U942 and
U960. When U900-9 (read7(H» is asserted, U936-U942 are enabled,
and PCO-PC7 are read from U960 on the data bus (BDO-BD7) . When
U900-l2 (read8(H» is asserted, U934 is enable, and PC8-PC9 are
read from U960 on the data bus (BDO-BD1).
Test 0 General Description
This test checks the clear, load, and readback of the program
counter.
Clearing the counter. A reset pulse to the counter is generated
by writing data to port hexOF (Ul18-l7).
8-7
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Setting the counter to a load mode. A jump instruction is clocked
into memory.
Clocking the counter. A clocking pulse is generated by writing
data to port hexOD(Ul18-15).
Reading the output of the counter. U900-9(H) enables the output
PCO-PC7 of the counter to the data bus(SRDO-SRD7) through U936U942. U900-l2(H) enables the output PC8-PC9 of the counter to the
data bus (SRDO-SRD1) through U934.
Tested circuitry includes
Ul18, U134, U2l8 (Schematic 93)
U424C, U410, U412, U4l4 (Schematic 95)
U500, U502, U422B, U512, U514, U5l6 (Schematic 96)
U812 (Schematic 99)
U900, U934, U936, U938, U940, U942, U960 (Schematic 100)
Test 0 Readback Port
Comparators U934, U936, U938, U940 and U942 are enabled and Test
o results are read back through port hex04 (U960)
e
Test 0 Run Sequence
Test 0 includes:
1. Writing hex2AA to the memories U512, U514 and U5160
2. Writing hex8X to the memory U520.
3. Loading hex2AA to the PC.
4. Reading back the PC.
5. Clearing the PC by writing to port hexOF.
6. Reading back the PC.
7. Writing hex155 to the memories.
8. Loading hex155 to the
pc.
9. Reading back the PC.
8-8
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
10. Clearing the PC.
II. Reading back the PC.
Test 0 Error Code
Address
Expect
Actual
Step 1. hexOD
hexlD
hexAA
hex02
hexAA (PCO-PC7)
hex02 (PCS-PC9)
Step 2. hexOD
hexlD
hexOO
hexOO
hexOO (PCO-PC7)
hexOO (PCS-PC9)
Step 3. hexOD
hexlD
hex55
hexOl
hex55 (PCO-PC7)
hexOl (PCS-PC9)
Step 4. hexOD
hexlD
hexOO
hexOO
hexOO (PCO-PC7)
hexOO (PCS-PC9)
Error Indication
Possible Cause O. Check that there are many pulses when the
LOOPING field is ON.
Check Item
Check point
A clock for the PC
Pin 13 of U4l0
A resetting pulse for the PC
TP440
Possible Cause 1. If the test fails, check the following: In the
following table, X, which is in the Actual, specifies the
position where the actual data does not match the expected data.
N is a hexadecimal value.
Address
Actual
Memory
hexOD
hexNX
hexXN
hexOX
U5l2
U5l4
U5l6
hexlD
8-9
PC
Readback
U4l0
U4l2
U4l4
U936 & U93S
U940 & U942
U934
Maint: Diagnostic Test Descriptions
DAB 9100 Series 91516-91532 Service
If ACTUAL data is hexXX, check U520 which is written with the
JUMP instruction.
Possible Cause 2. Check the logic level at each point.
While the test is running, the circuitry has the following
condition.
Loading a data to the PC:
CKT I
pin I
U2l8
TP400
U406
12
2
17
19
20
21
2
19
5
16
6
15
9
12
U502
level (ECL)
L
L
H
L
L
L
H (TTL)
H (TTL)
L (TTL)
L (TTL)
L (TTL)
H (TTL)
H (TTL)
H (TTL)
Setting TP400 to a low level :
crr
I
U314
U424
pin I
level (ECL)
2
5
10
L
L
L
Reading the output of PC:
CKT I
pin I
U502
U900
12
2
19
5
16
6
15
9
12
level (TTL)
PCO-PC7
PC8-PC9
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
8-10
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Test 1 General Description
This test checks the clear, count-up and readback of the program
counter. The test contains the steps which include clearing,
setting an incremental mode and reading the counter.
Setting an incremental mode. For setting an incremental mode,
pin 5 of U410-U414 are set to a high level by writing 1 to bit 2
at port hexOB (U812).
Reading the counter. (The same as Test 0)
Test 1 Readback Port
Test 1 results are read back through port hex04 (U960) •
Test 1 Run Sequence. Test 1 includes the following:
1. Clearing the PC by writing to port hexOF.
2. Setting an incremental mode by writing XXXXXXlX to port
hexOB.
3. Counting up to 1023.
4. Reading back the PC at every clock.
Test 1 Error Code
Address : hexaD
Expect
Actual
hex3FF (a number of clocks)
: output of the PC
Error Indication
Possible Cause O. Check that there are many pulses when the
LOOPING field is ON.
Check Item
Check Point
A clock for the PC
Pin 13 of U4l0
A resetting pulse for the PC
TP440
8-11
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Possible Cause 1
A checked device follows.
data) •
Address
AC'l'UAL
PC
hexOD
hexNNX
hexNXN
hexXNN
U4l0
U4l2
U4l4
(X is missing data and N is correct
Readback
U936 & U938
U940 & U942
U934
Possible Cause 2
Check a logic level at each point.
For an incremental mode:
CKT'
pin ,
TP400
U424
TP440
10
level (ECL)
2
H
H
L (while the PC is receiving a clock)
2
For reading the pc:
CKT'
pin
U502
U900
12
2
19
5
16
6
15
9
12
,
level
PCO-PC7
L
L
L
L
L
L
L
H
L
(TTL)
PC8-peg
L
L
L
L
L
L
L
L
H
Test 2 General Description
This test checks the connection between the program counter and
memories, and between the RAM selector and memories. This test
contains the steps wh~ch include counting up the PC, writing to
memory and reading from memory.
8-12
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Writing to Memory. The data, which is a two raised to the Nth
power, is written to all memory.
Readback the Content of Memory. Vectors and two strobes are
loaded to the latches (U630, U632, U634, U636) by addressing port
hex07. After loading, they are read via comparators. Other
content of memory are read directly through comparators.
Test 2 Readback Port
Test 2 results are read back through port hex04 (U960) •
Test 2 Run Sequence
1. Clearing the PC and setting an incremental mode.
2. Incrementing the PC until a two raised to the Nth power.
3. Writing the incremented value to each memory
4. Clearing the PC.
5. Readback the written data from each memory at the address
which is two to the Nth power, and comparing the .readback data
with the written data.
6. If the read data matches the write data, the RAM is cleared.
Test 2 Error Code
The high 4 bits of the ADDR field specifies an address line's
number. The low 4 bit of the ADDR field specifies the memory. The
EXPECTED is write data and the ACTUAL is read data.
Error Indication
If the test fails, loop on FUNCTION 2 VECTOR RAM.
8-13
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
Possible Cause 0
Check that there are pulses when the LOOPING field is ON.
Check Item
Check Point
A clock for the PC
Pin 13 of U410
A clock for latch
TP610
Possible cause 1
As the bus line is an 8-bit line, micro-code and vector RAM are
shared. The low 4 bits of the ADDR specifies RAM. The high 4
bits specifies an address line's number. When a FAIL message
appears, the ADDR specifies a bad address line, a bad RAM
selections line or bad RAM.
ADDR
Xl
X2
X3
X4
X5
X6
Memory
Buffer
U504,U506
U508,U510
U512,U514
U516,U520
U518,U522
U524
U502-3
U502-19
U502-5
U502-16,6
U502-15
U502-9
ADDR
Address line
ox
PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
IX
2X
3X
4X
5X
6X
7X
8X
9X
or
or
or
or
or
or
or
or
or
or
SPCO
SPCl
SPC2
SPC3
SPC4
SPC5
SPC6
SPC7
SPC8
SPC9
PC
Buffer
U410-3
U410-2
U410-15
U4l0-l4
U412-3
U412-2
U412-15
U412-14
U414-3
U414-2
U530-15
U530-2
U530-14
U530-3
U530-13
U530-4
U532-4
U532-13
U532-3
U532-14
8-14
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Expect (ACTUAL)
(Address for write)
Output of PC
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
10000001
10000010
DATA line
TDO
TD1
TD2
TD3
TD4
TD5
TD6
TD7
91S16 FUNCTION 2
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
Buffer (TTL -> ECL)
U500-9
U500-8
U500-7
U500-6
U500-S
U500-4
USOO-3
U500-2
VECTOR RAM
Circuit Overview
The vector and micro-code memory of the 91S16 consists of eleven
4 X 1024 bit RAMs for a total of 1024 words by 44 bits.
Function Description
The data to RAM is read/written to/from the MPU bus with one byte
at a time. To write to the memory, two memories (one byte) are
assigned by writing the appropriate data to port hexOS and a
write pulse is generated by writing to port hex06.
The VECTOR RAM function consists of six separate tests. All tests
are basically identical, and will be described in detail once.
Memory is selected by writing to port hexOS (US02). Once the
memory is selected, data is written to port hex06 to be loaded to
the selected memory. Test 0, test 1, and test 4 require a clock
to load the memory output to a latch. The data is read back from
the latches by the comparators.
8-15
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
To read results, comparators U902-U958 must be selected by
writing to port hex04 (U900). A content of memory is read from
port hex04 (U960).
Test 0 General Description
This test checks the memories U504, U506. These memories are used
for vector VBO-VB7.
This test contains the steps which include clocking the PC,
writing and reading a memory, selecting an output multiplexer,
loading first latches, and reading the memory.
Tested circuitry includes:
Ul18,
U4l0,
U500,
U6l6,
U900,
U134,
U4l2,
U502,
U6l8,
U908,
U2l8
U4l4,
U504,
U620,
U9l0,
(Schematic 92 & 93)
U422, U424 (Schematic 94)
U506, U530, U532 (Schematic 96)
U622, U634, U636 {Schematic 97}
U9l2, U9l4, U960 (Schematic 100)
Test 0 Readback Port
Comparators U908, U9l0, U9l2 and U9l4 are enabled. Test 0 results
are read back through port hex04 (U960).
Test 0 Run sequence
1. Selecting the memories U504 and U506 by writing hex7E to port
hex05 (U502) •
2. Set the PC to an incremental mode by writing 1 to bit 2 of
port hexOB (U8l2) and clearing the PC by addressing port hexOF
(Ul18) •
3. Writing hexAA to the memories with a write pulse which is
generated from port hex06 (Ul18).
4. Giving a clock to the first latches (U632-U636) by reading the
port hex07. The output of the memories are loaded to the first
latches.
8-16
Maint: Diagnostic Test Descriptions
DAB 9100 Series 91516-91532 Service
5. Selecting the comparators (U908, U910, U912 and U914) by
writing hex01 to port hex04 (U900) and reading the output of
first latches from port hex04 (U960).
6. Comparing the data and writing hex55 to the memories via port
hex06.
7. Reading the data by the same method
8. Giving a clock to the PC for incrementing up the address to
memory.
9. Repeating the sequences from 2 to 6 until the PC is 1023.
Test 0 Error Code
The ADDR specifies a value of the program counter. The EXPECT
specifies a written data and the ACTUAL is a read data.
Error Indication
Possible Error 0
Check Item.
Check Point
write pulse
U504-16,
load pulse
TP610
Levels
CK'l' I
pin I
U502
2
19
5
16
6
15
9
12
2
19
5
16
6
15
9
12
U900
Level
(TTL)
L
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
8-17
U506-16
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
CRT I
pin I
U616
U618
U620
U622
7,9
7,9
7,9
7,9
Level (ECL)
L
L
L
L
Possible Cause 1
When an EXPECTED value does not match an ACTUAL value, check rcs
according to the following table:
Bit
Memory
Mux
Latch
Comparator
0
1
2
3
4
5
6
7
U504-22
U504-3
U504-23
U504-2
U506-22
U506-3
U506-23
U506-2
U616-2
U616-15
U618-2
U618-15
U620-2
U620-15
U622-2
U622-15
U634-14
U634-2
U634-15
U636-4
U636-13
U636-3
U636-14
U636-2
U908-8
U908-2
U910-8
U910-2
U912-8
U912-2
U914-8
U914-2
Test 1 General Description
Test 1 checks the memories U508, U510. These memories is used for
VECTOR VB8 - VB15. The steps are the same as Test O.
New tested circuitry includes:
U508, U510 (Schematic 96)
U612, U614, U224C, U316D, U632, U634 (Schematic 97)
U916, U918, U920, U922 (Schematic 100)
Test 1 Readback Port
Comparators U916, U918, U920 and U922 are enabled. Test 1 results
are readback through port hex04 (U960) •
8-18
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Test 1 Run Sequence
The following steps differ from test O. All other steps in this
test are the same as test O.
1. Selecting the memories U508, U5l0 by writing the data hex7D to
port hex05 (U502) •
5. Selecting the comparators (U9l6, U9l8, U920 and U922) by
writing hex02 to port hex04 (U900) and reading the output of
the first latches from port hex04 (U960).
Test 1 Error Code
(The same as Test O).
Error Indication
Possible Error 0
Check Item
Check Point
write pulse
U508-l6,
load pulse
TP6l0
U5l0-l6
Levels
CKT I
pin I
U502
2
19
5
16
6
15
9
12
2
19
5
16
6
15
9
12
U900
Level
(TTL)
H
L
H
H
H
H
H
L
L
H
L
L
L
L
L
L
8-19
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
CXT I
pin I
U616
U618
U620
U622
7,9
7,9
7,9
7,9
Level (ECL)
L
L
L
L
Possible Cause 1
When an EXPECTED value does not match an ACTUAL value, check res
according to the following table:
Bit
Memory
Mux
Latch
Comparator
0
1
2
3
4
5
6
7
U508-22
U508-3
U508-23
U508-2
U510-22
U510-3
U510-23
U510-2
U612-14
U612-1
U612-15
U612-2
U614-14
U614-1
U614-15
U614-2
U632-4
U632-13
U632-3
U632-14
U632-2
U632-15
U634-4
U634-13
U916-8
U916-2
U918-8
U918-2
U920-8
U920-2
U922-8
U922-2
Test 2 General Description
This Test checks the memories U512 and U514. These memories are
used for the destination (JAO-JA7) of the JUMP instructione
The steps are the same as Test O.
New tested circuitry includes:
U512, U514 (Schematic 96)
U924, U926, U928, U930 (Schematic 100)
Test 2 Readback Port
Comparators U924, U926, U928 and U930 are enabled. Test 2 results
are readback through port hex04 (U960).
8-20
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Test 2 Run Sequence
The following steps differ from test O.
test are the same as test O.
All other steps in this
1. Selecting the memories U512 and U514 by writing hex7B to port
hex05 (U502) •
4. This sequence is not needed.
5. Selecting the comparators (U924, U926, U928 and U930) by
writing the data hex04 to port hex04 (U900) and reading the
content of the memories from port hex04 (U960) •
Test 2 Error Code
(The same as Test 0).
Error Indication
Possible Error 0
Check Item
Check Point
write pulse
U512-16,
load pulse
TP610
Levels
CKT I
pin I
U502
2
19
5
16
6
15
9
12
2
19
5
16
6
15
9
12
U900
Level (TTL)
H
H
L
H
H
H
H
L
L
L
H
L
L
L
L
L
8-21
U514-16
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Possible Cause 1
When an EXPECTED value does not match an ACTUAL value, check res
according to next table.
Bit
Memory
Comparator
0
1
2
3
4
5
6
7
U512-22
U512-3
U512-23
U512-2
U514-22
U514-3
U514-23
U514-2
U924-8
U924-2
U926-8
U926-2
U928-8
U928-2
U930-8
U930-2
Test 3 General Description
This test checks the memories U5l6 and U520. These memories are
used for the destination (JA8 and JA9) of the JUMP instruction,
the OUT instruction, and the instructions for controlling the
program flow. The steps are the same as Test O.
New tested circuitry includes
U5l6, U520 (Schematic 96)
U958, U902, U906 (Schematic 100)
Test 3 Readback Port
Comparators U958, U902 and U906 are enabled (same as Test 0).
Test 3 Run Sequence
The following steps differ from test O. All other steps in this
test are the same as test O.
1. Selecting the memories U516 and U520 by writing hex67 to port
hex05 (U502) .
4. This sequence is not needed.
5. Selecting the comparators (U902, U946 and U958) by writing the
data hex08 to port hex04 (U900) and reading the content of the
memories from port hex04 (U960).
8-22
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
Test 3 Error Code
(The same as Test 0) •
Error Indication
Possible Error 0
Check Item
Check Point
write pulse
U516-16,
U520-16
Levels
CRT t
pin t
U502
2
19
5
16
6
15
9
12
2
19
5
16
6
15
9
12
U900
Level
(TTL)
H
H
L
L
H
H
H
L
L
L
L
H
L
L
L
L
Possible Cause 1
When an EXPECTED value does not match an ACTUAL value, check ICs
according to next table.
Bit
Memory
Comparator
0
1
2
3
4
5
6
U516-22
U516-3
U516-23
U516-2
U520-22
U520-3
U520-23
U520-2
U958-2
U958-13
U906-2
U906-13
U904-2
U904-13
U904-1
U904-14
7
8-23
Maint: Diagnostic Test Descriptions
DAB 9100 Series 91S16-91S32 Service
Test 4 General Description
This test checks the memories U5l8 and U522. These memories are
used for the INHIBIT and STROBE instructions, and the instruction
for the register control. The steps are the same as Test O.
New tested circuitry includes
U5l8, U522 (Schematic 96)
U630, U634, U636 (Schematic 97)
U946, U948, U904 (Schematic 100)
Test 4 Readback Port
Comparators U946, U948 and U904 are enabled (same as Test 0).
Test 4 Run Sequence
The following steps differ from test O. All other steps in this
test are the same as test O.
10 Selecting the memories U5l8 and U522 by writing hex5F to port
hex05 (U502) .
5. Selecting the comparators (U904, U946 and U948) by writing the
data hexlO to port hex04 (U900) and reading the content of the
memories from port hex04 (U960).
Test 4 Error Code
(The same as Test 0).
Error Indication
Possible Error 0
Check Item
Check Point
write pulse
U5l8-l6,
load pulse to latch
TP6l0
U522-l6
8-24
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
Levels
CRT I
pin I
U502
2
19
5
16
6
15
9
12
2
19
5
16
6
15
9
12
U900
CRT I
pin I
U616
U618
U620
U622
7,9
7,9
7,9
7,9
Level (TTL)
H
H
H
H
L
H
H
L
L
L
L
L
H
L
L
L
Level (ECL)
L
L
L
L
Possible Cause 1
When an EXPECTED value does not match an ACTUAL value, check
according to the following table.
Bit
Memory
Gate
Latch
Comparator
0
1
2
3
4
5
6
7
U516-22
U516-3
U516-23
U516-2
U522-22
U522-3
U522-23
U522-2
U224-10
U224-3
U630-15
U630-2
U636-15
U634-3
U946-8
U946-2
U948-8
U948-2
U904-2
U904-13
U904-1
U904-14
8-25
rcs
Maint: Diagnostic Test Descriptions
DAB 9100 Series 91516-91532 Service
Test 5 General Description
This test checks memory U524. This memory is used for the NEXT
PAGE, HALT, TRIGGER OUT, and INTERRUPT MASK instruction~ The
steps are the same as Test O.
New tested circuitry mainly includes
U524 (Schematic 96)
U906, U958 (Schematic 100)
Test 5 Readback Port
Comparators U906 and U958 are enabled (the same as Test 0).
Test 5 Run Sequence
The following steps differ from test O.
test are the same as test O.
All other steps in this
1. Selecting the memory U524 by writing hex3F to port hex05
(U502) •
4. This sequence is not needed.
5. Selecting the comparators (U906 and U958) by writing the data
hex20 to port hex04 (U900) and reading the content of the
memories from port hex04 (U960).
Test 5 Error Code
(The same as Test 0) •
Error Indication
Possible Error 0
Check Item
Check Point
write pulse
U524-l6
8-26
Maint: Diagnostic Test Descriptions
DAB 9100 Series 91516-91532 Service
Levels
CKTI
pin I
U502
2
19
5
16
6
15
9
12
2
19
5
16
6
15
9
12
U900
Level (TTL)
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
L
Possible Cause 1
When an EXPECTED value does not match an ACTUAL value, check rcs
according to the following table.
Bit
Memory
Comparator
o
U524-22
U524-3
U524-23
U524-2
U958-1
U958-14
U906-1
U906-14
1
2
3
4
5
6
7
91516
FUNCTION 3
REGISTER
Circuit Overview
The 91516 has two 8 bit registers (or one 16bit register). These
registers can load, hold, count up or down by micro-code
instruction. The program flow is controlled by these registers.
And the output of these register is transferred to probes via the
OUTPUT selector and two latches.
8-27
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Functional Description
Test 0 checks the load, count up, and count down functions of
register A (U600 and U602); and readback the value of the
registers.
Test 1 checks the load, count up, and count down functions of
register B (U604 and U606); and readback the value of the
registers.
Test 2 checks the load and increment functions.
8-28
91516
FUNCTION 3
REGISTER
Circuit OVerview
The 91S16 has two 8-bit registers (or one 16-bit register). These
registers can load, hold, count up or down by micro-code
instruction. The program flow is controlled by the result of
these registers, and the output is transferred to probes via the
output selector and two latches.
Punctiona1 Description
The REGISTER function consists of four tests.
A~s function (U600 and U602) which are the
load, count up, and count down; and reads back the value of the
registers.
Test 0 checks register
B~s function (U604 and U606) which are the
load, count up, and count down; and reads back the value of the
registers.
Test 1 checks register
Test 2 checks the load and increment functions as a 16 bit
register. This test does not run at power-up.
Test 3 checks the load and increment functions as a 16 bit
register. This test does not run at power-up.
Writing a value to a register
A desired value are written to the memories (U504, U506, U508 and
U510). And the control bits for register are written to the
memory U522. Registers RA and RB are controlled by giving a
clock, according to the output of the memory (U522).
Reading a value from a register
A output of a register is passed to the first latches (U632U636)by selecting the multiplexer (U612-U622) , and is clocked to
the first latches by reading from port hex07 (U112). After they
are clocked in, the output of the first latch is read via
comparators.
Test 0 General Description
This test checks register A~s function which are the LOAD, HOLD,
INCRE, and DECRE modes. The results are read via selector,
latches, and comparators.
8-29
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
Setting the mode
The memory U522 is selected by writing hex5F to port hex05 (U502)
and the following data is loaded in memory U522 by writing to
port hex06 (Ul18).
bit 7
o
o
1
1
bit 6
0 load vector to register A
1 Increment
0 Decrement
1 Hold
Setting the OUTPUT SELECTOR
The OUTPUT SELECTOR is selected by OUT RA. The data hex20 is
written to port hexOC (US14) via the disabled RAM (U5l6).
Loading to the first latches
The output of register A is loaded into the first registers by
reading from port hex07.
Reading the data loaded to the first latches
The same as the steps which read vector VBO-VB7.
Tested circuitry includes
U422, U500, U502, U504, U506, U522 (Schematic 96)
U600, U602, U616, U6lS, U620, U622, U634, U636 (Schematic 97)
U900, U908, U9l0, U9l2, U9l4, U960 (Schematic 100)
Test 0 readback port
Comparators U908, U9l0, U9l2 and U9l4 are enabled. The output of
the register A can be read via the OUTPUT SELECTOR and the first
latches.
Test 0 Run Sequence
1. Sets the output selector to OUT RA.
8-30
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
2.
Selects the memories U504 and U506 by writing hex7E to port
hex05 (U502).
3.
Loads the vector hex55 to the memories by writing to port
hex06.
4.
The initial data (hex55)
5.
Selects the memory U522 for loading MC12 and MC13 by writing
hex5F to port hex05.
6.
To set register A to an incremental mode, selects the memory
U522 and writes the data hex7F to port hex06 (write pulse).
7.
Clocks register A until the output of register A is hexFF.
8.
The value of register A is read back after being loaded to
the first latches after every clock.
9.
Selects the memories U504 and U506 by writing hex7E to port
hex05 (U502).
is loaded to register A.
10. Loads the vector hexAA to the memories by writing to port
hex06.
11. The initial data (hexAA)
is loaded to register A.
12. Selects the memory U522 for loading MC12 and MC13.
13. To set register A to a decremental mode, writes the data
hexBF to port hex06 (write pulse).
14. Clocks register A until the output of register A is hexOO.
15. The value of register A is read back after being loaded to
the first latches after every clock.
Test 0 Error Code
The ADDR specifies the incremental or decremental mode. EXPECT is
a number of clocks which are given to register A and ACTUAL is
the output of the register A.
8-31
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
Error Indication
Possible Cause
Check that there are many pulses at test point:
Check Item
Check Point
Clock for register
TP600
Clock for latch
TP610
For an incremental mode:
ADDR
= hex70
CK'l' I
pin I
U600
7
9
7
9
U602
Level (ECL)
H
L
H
L
For a decremental mode:
ADDR = hexBO
CK'l' I
U600
pin I
7
9
U602
7
9
Level (ECL)
L
H
L
H
Output Selector selects the output of register A.
CK'l' I
U616
pin I
7
9
U618
7
U620
7
9
9
U622
7
9
Level (ECL)
L
H
L
H
L
H
L
H
8-32
Maint: Diagnostic Test Descriptions
DAB 9100 Series 91S16-91S32 Service
Readback port:
CKT I
pin I
U502
U900
12
2
19
5
16
6
15
9
12
Level (TTL)
L
H
L
L
L
L
L
L
L
Possible Cause 1
When an EXPECTED value does not match an ACTUAL value, check ICs
according to following table:
Bit
0
1
2
3
4
5
6
7
register A
U600-14
U600-15
U600-2
U600-3
U602-14
U602-15
U602-2
U602-3
Mux
U616-2
U616-15
U618-2
U618-15
U620-2
U620-15
U622-2
U622-15
Latch
C01DParator
U634-14
U634-2
U634-15
U636-4
U636-13
U636-3
U636-14
U636-2
U908-8
U908-2
U910-8
U910-2
U912-8
U912-2
U914-8
U914-2
Test 1 General Description
This test checks register B~s function which are the LOAD, HOLD,
INCRE, and DECRE modes. The results are read via OUTPUT selector,
latches, and comparators.
8-33
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Setting the mode
The memory U522 is selected by writing hexSF to port hex05 (U502)
and the following data is loaded to the memory U522 by writing to
port hex06 (Ul18).
bit 5
o
o
1
1
bit 4
0
1
0
1
load vector to register B
Increment
Decrement
Hold
Setting the OUTPUT SELECTOR
The OUTPUT SELECTOR is selected by OUT RB. The hexlO data is
written to port hexOC (U814) with the disabled RAM (U516).
Loading to the first latches
The output of register B is loaded to the first registers by
reading from port hex07.
Reading the data loaded to the first latches
The same as Test 0 sequence.
New tested circuitry includes:
U608, U610, U604, U606 (Schematic 97)
Test 1 readback port
The output of the register A is read via the OUTPUT SELECTOR and
the first latches.
8-34
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Test 1 Run Sequence
1.
Sets the output selector to OUT RB.
2.
Selects the memories U508 and U510 by writing hex7D to port
hex05 (U502).
3.
Loads the vector hex55 to the memories by writing to port
hex06.
4.
The initial data (hex55)
5.
Selects the memory U522 for loading MCIO and MCll by writing
hex5F to port hex05.
6.
To setting register B to an incremental mode, selects the
memory U522 and write the data hexDF to port hex06 (write
pulse) •
7.
Clocks to register B until the output of register B is hexFF.
8.
The value of register B is read back after being loaded to
the first latches after every clock.
9.
Selects the memories U508 and U5l0 by writing hex7D to port
hex05 (U502).
is loaded to register A.
10. Loads the vector hexAA to the memories by writing to port
hex06.
11. The initial data (hexAA)
is loaded to register B.
12. Selects the memory U522 for loading MCIO and MCll.
13. To set register B to a decremental mode, write the data hexEF
to port hex06 (write pulse).
14. Clocks to register B until the output of register B is hexOO.
15. The value of register B is read back after being loaded to
the first latches after every clock.
8-35
---___ _
_
_
_ _ ';II • • ~~ '-........
...
'C""...
U~::)~.;J• .LJ:'1:.~ons
DAB 9100 Series 91816-91532 Service
Test 1 Error Code
The ADDR specifies the incremental or decremental mode. EXPECT is
a number of clocks which are given to register B and ACTUAL is
the output of the register B.
Error Indication
Possible Cause
Check that there are many pulses at the test points:
Check Item
Check Point
Clock for register
TP600
Clock for latch
TP6l0
For an incremental mode:
ADDR = hexDO
crr
I
pin I
U604
7
9
U606
7
9
Level (BCL)
H
L
H
L
For a decremental mode:
ADDR = hexEO
Cft I
U604
U606
pin I
7
9
7
9
Level (EeL)
L
H
L
H
8-36
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91Sl6-91S32 Service
For loading data to register B:
CRT •
pin
U608
U6l0
9
9
•
Level (ECL)
H
H
Output Selector selects the output from the register B.
err •
U6l6
U6l8
U620
U622
pin
•
7
9
7
9
7
9
7
9
Level (ECL)
H
L
H
L
H
L
H
L
Readback port:
crr •
pin
U502
U900
12
2
19
5
16
6
15
9
12
•
Level (TTL)
L
H
L
L
L
L
L
L
L
Possible Cause 1
When an EXPECTED value does not match an ACTUAL value, check ICs
according to next table.
8-31
·~~ ... u ....
"""'Q~UVO;)I..~I;,;
-~-e::>~
lJeSCr~ptlons
DAS 9100 Series 91S16-91S32 Service
Bit
register B
0
1
2
U604-14
U604-15
U604-2
U604-3
U606-14
U606-15
U606-2
U606-3
3
4
5
6
7
Mux
Latch
U616-2
U616-15
U618-2
U618-15
U620-2
U620-15
U622-2
U622-15
U634-14
U634-2
U634-15
U636-4
U636-13
U636-3
U636-14
U636-2
Comparator
U908-8
U908-2
U910-8
U910-2
U912-8
U912-2
U9l4-8
U914-2
Test 2 General Description
This test checks a 16 bit register~s function which are the LOAD
and INCRE mode. The results are read via OUTPUT selector, latches
and comparators.
Setting the mode
The 16 bit register mode is selected by setting bit 6 of U808 to
1. The memory U522 is selected by writing hex5F to port hex05
(U502) and the following data is loaded to the memory U522 by
writing to port hex06 (Ul18).
bit 5 & 7
o
o
bit 4 & 6
o
1
load vector to register
Increment
Setting the OUTPUT SELECTOR
The OUTPUT SELECTOR is set to select OUT RA. Hex20 is written to
port hexOC (U814) with the disabled RAM (U516).
Loading to the first latches
The output of the registers are loaded to the first latches by
reading (clocking) from port hex07.
8-38
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Reading the data loaded to the first latches
The lower 8 bits are read by the same steps as vector VBO-VB7.
The higher 8 bits are read by the same steps as vector VB8-VB1S.
New tested circuitry includes:
U508, U510 (Schematic 96)
U638, U612, U614, U632 (Schematic 97)
U916, U918, U920, U922 (Schematic 100)
Test 2 readback port
The output of the register is read via the OUTPUT SELECTOR and
the first latches.
Test 2 Run Sequence
1. Sets the output selector to OUT RA.
2. Selects the memories U504, U506, U508 and U510 by writing
hex7C to port hex05 (U502).
3. Loads the vector hex55 to the memories by writing to port
hex06.
4. The initial data (hex5555) is loaded to register.
5. Selects the memory U522 for loading MC10 - MC13 by writing
hex5F to port hex05.
6. To setting the register to an incremental mode, selects the
memory U522 and write the data hex5F to port hex06 (write
pulse).
7. Clocks to register until the output of Register is hex6000.
8. The value of the register is read back after being loaded to
the first latches after every clock.
Test 2 Error Code
The ADDR specifies the incremental or decrementa1 mode. EXPECT is
a number of clocks which are given to Register and ACTUAL is the
output of the Register.
8-39
n.............
1.14ClYllU::il;:l.C Test: Oeser iptions
DAS 9100 Series 9lSl6-9lS32 Service
Error Indication
Possible Cause 0
Check that there are pulses at the test point
Cheek Item
Check Point
Clock for register
TP600
Clock for latch
TP6l0
For an incremental mode:
ADDR
= hex50
cn
I
U600
U602
U604
U606
pin I
Level (ECL)
7
9
7
9
7
9
7
9
H
L
H
L
H
L
H
L
Output Selector selects the output from register
CKT I
U6l6
U618
U620
U622
pin I
Level (ECL)
7
9
7
9
7
9
7
9
L
H
L
H
L
H
L
H
For a 16 bit register:
CKT I
U638
U612
U614
pin I
5
9
9
Level (ECL)
H
L
L
8-40
A~
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
Readback port:
Low 8 bit
CRT t
pin t
U502
U900
12
2
19
5
16
6
15
9
12
High 8 bit
Level (TTL)
Level (TTL)
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
Possible Cause 1
When an EXPECTED value does not match an ACTUAL value, check rcs
according to the following table.
Bit
register A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
U600-14
U600-15
U600-2
U600-3
U602-14
U602-15
U602-2
U602-3
U604-14
U604-15
U604-2
U604-3
U606-14
U606-15
U606-2
U606-3
Mux
U616-2
U616-15
U618-2
U618-15
U620-2
U620-15
U622-2
U622-15
U612-14
U612-1
U612-15
U612-2
U614-14
U614-1
U614-15
U614-2
Latch
Comparator
U634-14
U634-2
U634-15
U636-4
U636-13
U636-3
U636-14
U636-2
U632-4
U632-13
U632-3
U632-14
U632-2
U632-15
U634-4
U634-13
U908-8
U908-2
U910-8
U910-2
U912-8
U912-2
U914-8
U914-2
U916-8
U916-2
U918-8
U918-2
U920-8
U920-2
U922-8
U922-2
8-41
Ma1nt: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Test 3 General Description
This test checks the 16 bit register~s LOAD and DECRE modes. The
results are read via OUTPUT selector, latches and comparators.
Setting the mode:
The 16 bit register mode is selected by setting bit 6 of U808 to
1. Memory Us22 is selected by writing hexsF to port hexOs (us02)
and the following data is loaded in the memory us22 by writing to
port hex06 (Ul18).
bit 5 & 7
bit 4 & 6
o
1
o
o
load vector to register
Decrement
Setting the OUTPUT SELECTOR:
The OUTPUT SELECTOR is set to select OUT RA. Hex20 is written to
port hexOC (U8l4) with the disabled RAM (U5l6).
Loading to the first latches:
The output of the registers is loaded to the first latches by
reading from port hex07.
Reading the data loaded to the first latches:
The lower 8 bits are read by the same steps as vector VBO-VB7.
The high 8 bit are read by the same steps as vector VB8-VBlSe
Test 3 readback port:
The output of the register is read via the OUTPUT SELECTOR and
the first latches.
Test 3 Run Sequence
1. Sets the output selector to OUT RAe
2. Selects the memories Us04, Us06, U508 and U5l0 by writing
hex7C to port hexOs (Us02).
8-42
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
3. Loads the vector hexAA to the memories by writing to port
hex06.
4. The initial data (hexAAAA) is loaded to Register.
5. Selects the memory U522 for loading MClO - MCl3.
6. To set the register to a decremental mode, writes the data
hexAF to port hex06 (write pulse).
7. Clocks to Register until the output of Register is hex9FFF.
8. The value of the register is read back after being loaded to
the first latches after every clock.
Test 3 Error Code
The ADDR specifies the incremental or decremental mode. EXPECT is
a number of clocks which are given to Register and'ACTUAL is the
output of the Register.
Error Indication
The same as the Test 2, excluding the following:
For a decremental mode:
ADDR
= hexAO
CKT
U600
U602
U604
U606
t
pin t
Level (ECL)
7
L
9
H
7
L
9
H
7
L
9
H
7
L
9
H
8-43
____ 4. __
~
......
~U...,
.............
~C;o\..
uescr J. pt:. loons
DAS 9100 Series 91S16-91S32 Service
91S16 FUNCTION 4
INSTR
Circuit Overview
This test checks some of the sequence flow instructions. The
multiplexer (U406)is controlled by micro-code MC6-MC9 which
selects the sequence flow instruction. If the output (U406-8) of
the multiplexer is low, it means that the PC should be loaded
with a new 10 bit value at the next rising edge of the clock. If
it is high, the PC is incremented by one.
Punctiona1 Description
This functional test includes the following:
Test 0 checks the ADVANCE and JUMP instruction.
Test 1 checks the IF RA=O JUMP, IF RB=O JUMP, and IF R=O JUMP
instruction.
Test 2 checks the IF KEY JUMP, IF END JUMP, and CALL RMT
instruction.
Writing an instruction :
Memory U520 is selected, and a bit pattern which specifies an
instruction is written to U520.
Readback a status
The output of the multiplexer U406-8 is passed to comparator U952
via U432B. The read status value is inverted by U432B. The
output of U952 is transferred to the CPU bus via U960 by writing
hexaO to port hex04.
Test 0 General Description
Test 0 checks that a correct control signal is given to the
program counter from the multiplexer according to the
ADVANCE/JUMP instruction. Test 0 contains the steps which include
loading micro-code to memory, and reading the status.
8-44
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
When the ADVANCE instruction is written to memory U520, the /PE
pin of the PC (U4l0-U4l4) should receive a high level signal from
multiplexer U406.
When the JUMP instruction is written to the memory, the /PE pin
of the PC should receive a low level signal from the multiplexer
(U406) •
Tested circuitry includes:
Ul18,
U406,
U500,
U900,
U134,
U432
U502,
U952,
U2l8 (Schematic 92 & 93)
(Schematic 95)
U530, U532, U520, U422 (Schematic 96)
U960 (Schematic 100)
Test 0 Readback Port
A signal to the PC is passed to comparator U952 via NOR gate
U432B. Then the comparator receives an inverted level of the
multiplexer. The result is transferred to the BD2 bus through
U960.
Test 0 Run Sequence
1. Clears the PC
2. Selects comparator U952 for reading the status by writing
hex80 to port hex04.
3. Selects the memory U520 to write the micro-code MC6-MC9.
4. Writes the micro-code to U520.
Instruction
ADVANCE
JUMP
Write Data (micro-code)
OlOOXXXX
1000XXXX
5. Read the status (output of the multiplexer U406) for each
case.
Test 0 Error Code
ADDR specifies the micro-code. EXPECT is the desired status and
ACTUAL is the read value. The read status is inverted because it
is read back through the NOR gate.
8-45
- ___ - -
-
--:::> •• ~~ - ... ""
... """"...
"'Ci:)~.L .1.pl:~ons
DAS 9100 Series 91S16-91S32 Service
Error Indication
If the test fails, set the LOOPING field to ON.
Possible Cause 0
The ADDR specifies the executing instruction.
Instruction
ADDR
ADVANCE
JUMP
hex40
hex80
While these instructions execute, the following levels are
maintained:
Levels
err t
pin
U432
U424
U424
U406
U406
U520
12
11
10
24
23
17
t
Level (ECL)
L
L
L
H
L
L
If U432-l2 is a high level, examine TEST 2 in FUNCTION 4
INTERRUPT.
Por readback
CKT
U502
U900
t
pin
12
2
19
5
16
6
15
9
12
t
Level ('l'TL)
L
L
L
L
L
L
L
L
H
8-46
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
For ADVANCE instruction
CKT I
pin I
U406
17
19
20
21
8
Level (ECL)
L
H
L
L
H
For JUMP instruction
I
CKT
U406
pin I
17
19
20
21
8
Level (ECL)
H
L
L
L
H
Test 1 General Description
Test 1 checks the flow control instructions sent to the RA and RB
registers. This test contains the steps which include writing the
data to registers, writing the micro-code memory, and reading the
status at the /PE pin of the program counter.
Writing the data to the RA and RB registers
Data to load to a register is written to the memory for vector
and A clock is given to the RA and RB registers.
Writing an instruction
An instruction is written to the memory U520. The multiplexer
selects a status line for each instruction according to the
written pattern. A pattern for instruction is as follows.
Instruction
Write Data (micro-code)
IF RA=O JUMP
IF RB=O JUMP
IF R=O JUMP
OOlOXXXX
1100XXXX
lOlOXXXX
8-47
--------
- - - ; : r u ........... .&.v
L~o:::.l.
LI~5Crl.pt:l.ons
DAS 9100 Series 91516-91532 Service
New tested circuitry includes:
U406, U432 (Schematic 95)
U504, US06, U508, USlO, US20 (Schematic 96)
U608, U6l0, U600, U602, U604, U606, U626, U628, U638, U640
(Schematic 97)
Test 1 Readback Port
The same as Test O.
Test 1 Run Sequence
1. Disables all memories and sends a clock to RA and RB registers
by reading from port hexOSe Registers are cleared.
2. Selects the memory U520 and writes the micro-code for the
IF RA=O JUMP instruction to the memory by writing to port
hex06.
3. Selects the comparator U952 for reading the status by writing
hex80 to port hex04.
4. Reads the status at the output of multiplexer U406-8 from port
hex04.
5. Writes the data hexFF to the vector RAM and produces a clock.
A register loads data hexFF.
6. Repeats sequence 2, 3 and 4.
7. Repeats the sequence 1 to 6 for each instruction.
Test 1 Error Code
ADDR specifies the instruction. EXPECT is the desired status and
ACTUAL is the read status. The read status data is the inverse of
what was actually read back because of the NOR gate.
8-48
Maint: Diagnostic Test Descriptions
DAB 9100 Series 91S16-91S32 Service
Error Indicator
Possible Error
If the test fails, execute the diagnostics FUNCTION 3 REGISTER.
Verify that FUNCTION 3 REGISTER passes. ADDR specifies the
executing instruction.
Instruction
IF RA=O JUMP
IF RB=O JUMP
IF R=O JUMP
ADDR
hex20
hexCO
hexAO
Levels
err I
pin I
U432
U424
U424
U520
12
11
10
17
Level (EeL)
L
L
L
L
If U432-12 is a high level, examine TEST 2 in FUNCTION 4
INTERRUPT.
Por readback
err I
pin I
U502
U900
12
2
19
5
16
6
15
9
12
Level
(TTL)
L
L
L
L
L
L
L
L
H
8-49
Ma1nt: Diagnostic Test Descriptions
DAB 9100 Series 91S16-91S32 Service
Por IP RA=O JUMP instruction
Cft I
pin I
U406
17
19
20
21
Level (EeL)
L
L
H
L
L or H (They are the same logic level as
U626-2,15 minus a little delay time).
8
If U626-2,15 do not go to a low level or a high level, examine
TEST 0 in FUNCTION 3 REGISTER.
Por IP RB=O JUMP instruction :
eltT I
pin I
U406
17
19
20
21
8
Level (EeL)
H
H
L
L
L
or H (They are the same logic level as
U628-2,15 minus a little delay time).
If U628-2,15 do not go to a low level or a high level, examine
TEST 1 in FUNCTION 3 REGISTER.
Por IF R=O JUMP instruction
Cft I
pin I
U406
17
19
20
21
8
Level (EeL)
H
L
H
L
L or H (When both U626-2,15 and U628-2,15
U640-2 are low, U640-2, U406-8, and
U626-2,15 go to the low level with
little U628-2,15 delay time).
8-50
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
Test 2 General Description
Test 2 checks the IF KEY JUMP, IF END JUMP, CALL RMT and IF FULL
JUMP instruction. Test 2 contains the steps which include
clearing the latch, writing the instruction to the memory, and
reading the status.
NOTE
The IF FULL JUMP instruction is also checked in the
91532 Diagnostic Routine if the 91532 exists.
Writing the instruction :
The same as Test 0 and Test instructions.
Clearing the latch :
The latches for the IF KEY JUMP instruction are U3l2B and U232B.
They are cleared by setting a high level to bit 7 of U8l0 (port
hexOA). At the same time, the latch for CALL RMT instruction is
cleared by executing the IF FULL JUMP instruction.
Readback the status:
The same as Test O.
Latch for the IF END JUMP instruction
Bit 7 of port hex07 (U804) is for the IF END THEN instruction. If
data from a host computer is ended, the controller writes 1 to
bit 7 of port hex07. Its signal is passed to the PC via
multiplexer U406.
Latch for the CALL RMT instruction:
The micro-code for the CALL RMT instruction is written to memory
U520. It is decoded at U408, sent to U2l6A, and loaded by a
clock.
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Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
~a1nt:
New tested circuitry includes
U2l6A, U3l6B, U956A (Schematic 93)
U3l2B, U232B, U304A, U332, U302, U334 (Schematic 94)
U408 (Schematic 95)
Test 2 Readback
The same as the status.
Test 2 Run Sequence
1.
Clears latches U232B and U3l2B by writing 1 to bit 7 of port
hexOA (U8l0).
2.
To provide a KEY, writes
(U8l4) •
3.
Selects the memory for the flow control instruction and
writes it with the pattern OOOlXXXX for the IF KEY JUMP
instruction.
a
and 1 to bit 2 of the port hexOC
4. Reads back a status.
5. Clears the latches and reads back a statuso
The following verify the IF END JUMP instruction.
6.
Writes 1 to bit 7 of port hex07 (U804) and clocks latch
U334A.
7.
Selects memory U520 for the flow control instruction and
writes it with the pattern 1110XXXX.
8.
Reads back the status.
9.
Writes 0 to bit 7 of port hex07 (U804) clocks latch U334A.
10. Reads back the status.
11. Clears latch U2l6A for CALL RMT instruction.
12. Writes the micro-code to memory U520 and clocks the memory.
13. Reads back the status.
14. Produces a clock for a LOAD END by writing 1 and 0 to bit 19
of U8l4.
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15. Clocks the LOAD signal through U232B.
16. Writes pattern OOOlXXXX to memory U520. The pattern specifies
the IF FULL JUMP instruction.
17. Reads back the status at TP400 via gate U432.
18. Executes the IF FULL JUMP instruction, and clears latch
U216A. U216A is used for holding CALL RMT bit.
19. Reads back a status.
Test 2 Error Code
ADDR specifies an instruction. EXPECT is a desired status and
ACTUAL is the inverse of what was read back because of the NOR
gate.
Error Indication
Possible Cause 0
The ADDR specifies the executing instruction.
Instruction
ADDR
IF KEY JUMP
IF END JUMP
CALL RMT
IF FULL JUMP
Reset CALL RMT
hex90
hexEO
hexDO
hexll
hexlO
Verify that there are many pulses
Check Item
write pulse
latch clock
Check point
U422-3
U304-9
U232-9
U334-6
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Levels
err t
pin t
0432
0424
0424
12
10
11
Level (BCL)
L
L
L
If 0432-12 is a high level, examine TEST 2 in FUNCTION 5
INTERRUPT.
Possible Cause 1
IF KEY JOMP Instruction
Levels
err t
pin t
0406
17
19
20
21
Level (BCL)
H
L
L
H
If they are an incorrect level, check FUNCTION VECTOR RAM.
When EXPECTED = hex04 and ACTUAL
at each point.
Cft t
pin t
0312
0312
0232
0304
0332
0304
11
15
15
7
7
7
= hexOO,
check the logic level
= hex04,
check the logic level
Level (BeL)
L to H
L
L
L
L
L
When EXPECTED = hexOO and ACTOAL
at each point.
Cft I
pin t
Level (BCL)
0408
0302
12
11
H to L
L
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Possible Cause 2
IF END JUMP Instruction
Levels
CRT I
pin I
U406
17
19
20
21
Level (ECL)
H
H
H
L
When EXPECTED = hex04 and ACTUAL
at each point.
CRT I
U334
pin I
7
2
pin
U334
7
2
check the logic level
= hex04,
check the logic level
Level (ECL)
L
L
When EXPECTED = hexOO and ACTUAL
at each point.
CRT I
= hexOO,
t
Level (ECL)
H
H
Possible Cause 3
CALL RMT Instruction
When ADDR = hexDO, EXPECTED
logic level at each point.
= hexOl
8-55
and ACTUAL
= hexOO,
check the
u1agnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
fta~n~:
Cft ,
pin
U406
17
19
20
21
8
10
U408
,
Level (ECL)
H
H
L
H
H
L
When ADDR := hexll, EXPECTED := hex04, ACTUAL := hexOO For latch
U232A for load end is not set.
Check the logic level at each point.
Cft ,
pin
U406
17
19
20
21
8
5
2
2
U3l2
U232
,
Level (ECL)
L
L
L
H
L
L
L
L
When ADDR := hexlO, EXPECTED := hexOO and ACTUAL := hex04 Latch
U2l6 for CALL RMT is not cleared by executing the IF FULL JUMP
instruction.
Check the logic level at each point. If next setting is
satisfied, a pulse appears at U2l6-5.
CRT'
pin
U406
17
19
20
21
8
2
15
12
U232
U302
U304
,
Level
(EeL)
L
L
L
H
L
L
L
L
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91516 FUNCTION 5
INTERRUPT
FUNCTION 5 General Description
This FUNCTION Test checks the stack and the interrupt circuitry.
The operation of the stack is the same as the program counter,
excluding after receiving an interrupt signal.
Test 0 writes a value to the stack (U4l6, U4l8 and U420) and
resets it. The output of the stack is readback via the PC.
Test 1 exercises the PC to count from hexOOO to hex3FF, and reads
back the result every clock. This test also runs on power-up and
verifies the count from hex2AA to hex3FF.
Test 2 checks a logic operation in the interrupt cireuitry.
Test 0 General Description
This test checks the operation of the stack. The test contains
the steps which include clearing and loading the stack.
Clearing the stack :
A reset pulse to the stack is generated by reading from port
hex03.
Setting a mode and clocking the stack:
The operation of the stack is basically the same as the PC.
Tested circuitry includes:
Ul12,
U134,
U400,
U422,
U900,
Ul18
U218
U402,
U424,
U934,
(Schematic 92)
(Schematic 93)
U404, U406, U4l0, U4l2, U414, U416, U418, U420
U432 (Schematic 95)
U936, U938, U940, U942, U960 (Schematic 100)
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l.IJ.d9nOS1:~c Test Oeser iptions
DAS 9100 Series 91S16-91S32 Service
A-UU.l1\.. ;;
Test 0 Readback Port
There is no readback port for the stack. The output of the stack
has to be loaded to the program counter and is read as the output
of the pc. The output of the stack is passed to the pc via
Selector U400, U402 and U404 by disabling the memory U520. The
PC is loaded from the stack with a clock pulse. The loaded data
to the PC is read with the same method as Test 0 in FUNCTION 1
MEM ADDR.
Test 0 Run Sequence
Test 0 includes:
1. Clearing the stack by reading from port hex03 (Ul12).
2. Writing the data hex2AA to the memories U5l2, U5l4 and U5l6.
3. Writing hex8X, which specifies the JUMP instruction, to the
memory U520.
4. Loading it to the stack by writing to port hexOD.
5. Loading the output of the stack to the PC by disabling RAM and
writing to port hexOD.
6. Readback the
pc.
7. Repeating the sequence from 1 to 6 with data hex155.
Test 0 Error Code
Step
Address
Expected
Actual
Step 0
hexOD
hexlD
hexAA
hex02
hexAA fRARO-RAB7}
hex02 (RAB8-RAB9 )
Step 1
hexOD
hexlD
hexOO
hexOO
hexOO (RABO-RAB7)
hexOO (RAB8-RAB9)
Step 2
hexOD
hexlD
hex55
hexOl
hex55 (RABO-RAB7 )
hexOl (RAB8-RAB9)
Step 3
hexOD
hexlD
hexOO
hexOO
hpxOO (RABO-RAB7 )
hexOO (RAB8-RAB9 )
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Error Indication
Before this test is executed, it is a necessary that FUNCTION 1
MEM ADDR passes.
Possible Cause 0
Check that there are pulses when the LOOPING field is ON.
Check Item Check point
A clock for the PC at Pin 13 of U4l6
A reset pulse for the PC at Pin 12 of U416
Possible Cause 1
If the test fails, refer to the following table for devices
checked. In the table, X in the Actual column specifies the
position where the actual data does not match the expected data.
N is a Hexadecimal value.
Address
Actual
Memory
Stack
MUX
PC
Readback
hexOD
hexNX
hexXN
hexOX
U512
U514
U516
U4l6
U4l8
U420
U400
U402
U404
U410
U412
U414
U936 & U938
U940 & U942
U934
hex1D
If ACTUAL data is hexXX, check U520.
Possible Cause 2
Check for a logic level at each point.
While the test is running, the circuitry has the following
condition.
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Loading data to the stack
crr
I
U218
TP400
U406
U424
U400
U402
U404
pin
,
level (ECL)
12
2
17
19
20
21
12
13
9
9
9
L
L
H
L
L
L
L
L
L
L
L
If U424-13 is a high level, execute test 2 in this function.
Test 1 General Description
This test checks the clear, count-up and readback of the program
counter. The test contains the steps which include clearing,
setting an incremental mode, and reading the counter.
Setting an incremental mode
For setting an incremental mode, pins 5 of U416-U420 are set to a
high level by writing 1 to bit 2 at port hexOB (U812).
New tested circuitry includes
none.
Test 1 Readback Port
The same as Test O. The results are read back through port hex04
(U960).
Test 1 Run Sequence
Test 1 includes:
1. Clearing the stack by reading from port hex03.
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2. Setting an incremental mode by writing XXXXXX1X to port
hexOB.
3. Counting up to 1023.
4. Readback the stack via the PC at every clock.
Test 1 Error Code
ADDR specifies hexOD. EXPECTED specifies a number of given
clocks. ACTUAL is the output of the stack.
Error Indication
Possible Cause 0
Check a logic level at each point.
For an incremental mode :
err I
pin I
U432
U424
15
10
15
level (ECL)
H
H
L
Possible Cause 1
If test fails while counting up, examine a bit according the
table at Possible Cause 1 in Test 0 as a reference. Remember the
ADDR is hexOD.
Test 2 General Description
Test 2 checks the interrupt circuitry. The test contains the
steps which include making a stack hold state when an interrupt
signal is received, and clearing the hold state when the RETURN
instruction is executed. When a qualify signal is high, an
interrupt signal is received to U308. The output of U308 is
clocked in U306A which is treated by the PC as a clearing signal.
An output of the PC, which is generated only when the PC is
cleared, becomes a clock to U306B through U3l6C and clears U308.
After the interrupt circuit receives an interrupt signal, the
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output of U306B becomes a high level and the stack cannot accept
a clock. This test checks the output of U306B. The output of
U306B is cleared when the RETURN instruction is executed. The
RETURN instruction is written to the memory as micro-code and a
clock pulse is given. U306B becomes a low level. This level is
verified again.
New tested circuitry includes:
U308, U306, U3l0, U316C (Schematic 94)
U406, U4l4, U432 (Schematic 95)
U900, U952, U960 (Schematic 100)
Readback Port
The same as the FUNCTION Test 4.
Test Run Sequence
1. Resets latch U306B.
2. Makes an interrupt signal by controlling U308.
3. Clocks an interrupt signal in U306A. The stack hold signal is
then sent to the stack.
4. Reads back the leve1.
5. Writes the RETURN instruction to memory U520.
6. Provides a clock pulse and executes the RETURN instruction.
7. Reads back the status.
Read Error Code
ADDR specifies the checked circuitry, EXPECTED is the desired
status, and ACTUAL is the readback status.
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Error Indication
The ADDR value meanings are as follows:
ADDR
Checked function
hexOl
Clears the hold signal for the stack.
hex02
A hold signal is set at U306-15 by an interrupt
signal.
hex03
A hold signal is cleared by executing the RETURN
instruction.
Possible Cause 0
If test fails, set the LOOPING field to ON, and check that there
are signals at the following points:
Check Item
Test point
Reset pulse for the PC
Clock for a reset pulse
Clock for RETURN
TP440
TP360
U3l0-9
Possible Cause 1
= hexOl
When ADDR
Check for a pulse at U306-l3, and check that U306-15 goes to a
low level.
Possible Cause 2
When ADDR
= hex02
Check circuit operation with an interrupt signal. Check the level
at each of the following points.
CKT I
pin I
U308
2
4
5
11
9
10
U4l4
U316
U306
Level (ECL)
H
L
H
H
L to H
H
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When ADDR
= hex03
When checking a circuit operation by the RETURN instruction, it
is necessary to know what the next condition is.
CRT I
U3l0
pin I Level (BCL)
7
4
H
L
91516 FUNCTION 6 TBRSH
NOTE
The DAC threshold fixture must be inserted before this
test is run in order for the output voltages to be
accurate. Refer to the Test and Verification section
of this addendum for test fixture construction and
installation details.
Circuit Overview
The DAC THRESHOLD circuitry controls the threshold for the P6460
data acquisition probe.
Punctiona1 Description
There is no readback in the DAC circuitry, therefore it cannot be
tested. However, as an aid in calibration, an exercise routine
is provided to facilitate adjustment and verification of the DAC.
DAC Threshold General Description
The THRSH function tests the DAC that specifies threshold levels
on the external signal acquisition probe. Most of the circuitry
being tested can be seen on schematic 94.
This function has no readback capability, so the output of the
DAC must be monitored by connecting a digital multimeter between
test point THRES and test point PGND. THRES and PGND can be
found right behind the P6460 connector. The indications should
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be 0.00 V, +1.60 V, -1.587
two points is chosen using
THRESHOLD SET field.
This
been individually selected
V and a ramp. The voltage between the
the SELECT key in the special DAC
field only appears when the test has
and START SYSTEM has been pressed.
The DAC threshold test writes data corresponding to the voltage
to be produced. This data is latched to DAC U320 as follows.
DATA (Hexadecimal
00
80
FF
OUTPU'l'
-1. 587 V
0.00 V
+1.60 V
A ramp is generated by incrementing from 00 to FF with a delay to
settle the DAC.
The steady voltages in the DAC threshold function can be used to
determine the accuracy and correct operation of the DAC
circuitry. The ramp can be used to determine whether all
selectable voltages are available.
8-65
91S32 PATTERN GENERATOR DIAGNOSTICS
Organization of Diagnostic Punction and Subset Description.
Information on the diagnostic function is organized as follows:
1. A listing of quick reference diagnostic function
descriptions are given for the 9lS32.
2. Each diagnostic function and its subtests are described in
detail. Troubleshooting information is included.
There are eight diagnostic function descriptions. They are as
follows:
Function
Function
Function
Function
Function
Function
Function
Function
0
1
2
3
4
5
6
7
VECTOR GEN
LOOP COUNT
VECTOR RAM
CLK SEL
START FF
INHIBIT
PROBE IF
BUFFER
(Vector Generator)
(Loop Counter)
(Vector Ram)
(Clock Selector)
(Start Flip Flop)
(Inhibit from TRIG/TIMEBASE board)
(Probe Interface)
(Input Buffer from 9lSl6 or 91532 Clock
Buffer)
Each of the above functions contains one to seven subtests. All
of the functions above and their subtests are run on the 91S32.
The 9lS32 runs all of the above functions except:
FUNCTION
FUNCTION
FUNCTION
FUNCTION
3
4
5
7
CLK SEL
START FF
INHIBIT
BUFFER
(Clock from TRIG/TIMEBASE board)
(Start from TRIG/TIMEBASE board)
(Inhibit from TRIG/TIMEBASE board)
(Input Buffer from 91516)
Each function subsection (for example, Function 0 VECTOR GEN)
details function and subtest operation as follows:
1. There is a theory overview of the circuitry exercised by the
diagnostic function.
2. There is a brief description of the diagnostic routine within
the function~ This specifies how data is loaded and readback
on the function level.
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3. There is a description of the first subset (TEST X) within the
function. This description includes:
o a diagram showing circuitry blocks of the 91S32 exercised
by TEST X
o a detailed description of the subtest diagnostic routine
including readback ports
o a detailed description of the TEST X pass sequence as the
TEST X diagnostic routine is run.
QUICK REFERENCE FUNCTION DESCRIPTIONS
The following list briefly describes the diagnostic functions for
the 91532 Pattern Generator modules. If Functions are run
individually, they should be run in the listed order under the
module type. Only the functions for the module in question need
be run.
The tests in each function can be selected individually only when
the diagnostics are in a looping mode. For more information,
refer to the description of LOOPING provided earlier in this
section.
VECTOR GEM
This function verifies that the vector generate
counters can be loaded, incremented, and read. Most of the
circuitry tested by the VECTOR GEN function is on schematic
<103>.
This function verifies that the loop counters can be
loaded, incremented, and read. Most of the circuitry tested by
the LOOP COUNT function is on schematic <104>.
LOOP COURT
VECTOR RAM
This function verifies that the operation of the
vector RAM and the write enable registers. Most of the circuitry
tested by the VECTOR RAM function is on schematics <104>, <106>,
and <107>.
This function checks the operation of the clock
selector gates and latches. Most of the circuitry tested by the
CLK SEL function is on schematic <102>.
CLK SEL
START FP
This function tests the operation of the start flip
flop set/reset circuit and trigger start line. Most of the
circuitry tested by the START FF function is on schematic <104>.
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INBIBI~
This fUnction tests the operation of the probe inhibit
signal line. Most of the circuitry tested by the INHIBIT function
is on schematics <101>, and <103>.
PROBB IF This function checks the operation of the probe
interface latches, receivers, and buffers. Most of the circuitry
tested by the PROBE IF function is on schematics <101>, and
<105>.
BuFFER This function checks the operation of the clock buffer
and receiver of 9lS32 or address receiver and clock receiver of
the signals from 9lSl6. Most of the circuitry tested by the
BUFFER function is on schematics <102>, and <103>.
91S32 FUNCTION
CIRCUI~
0 VECTOR GBR
OVERVIEW
The Vector Generator circuit consists of a II-bit counter
(composed of four individual counters) which supplies the
address for the vector RAM. When these counters reach their
maximum count (7FF) a load pulse for these counters counts up the
loop counter.
FUNCTION DBSCRI"ION
The VECTOR GEN fUnction consists of eight separate tests.
~est
0 sets the page flip-flop to B.
~est
1 sets the page flip-flop to A.
~est
2 writes hex55 to each of the 4-bit counter U304 and U3l6
then reads the counter.
Test 3 writes hexOS to each of the 4-bit counter U330 and U340
then reads the counter.
Test 4 writes hexAA to each of the 4-bit counter U304 and U3l6
then reads the counter.
5 writes hex04 to each of the 4-bit counter U330 and U340
then reads the counter.
~est
Test 6 loads the vector generator with
then reads the count.
~est
O~s
and counts up to 555
7 loads the vector generator with 555 and counts up to 7FF
then reads the count.
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Readback ports
Test data is read from U650 <106> through U320, U326,U334, and
U344 <103>. When Ul12-15 (R05(H»
is asserted, U320 and U326 is
enabled, and data is sent from the RAOA-RA7A bus to the ROBO-ROB7
bus. When Ul12-9 (RD6(H»
is asserted, U334 and U344 are enabled,
and data is sent from RA8A-RA9A and PAGE SELECT to RDBO-ROB7.
Test 0 General Description
This test sets the U348A flip-flop to PAGE-B mode using port *OF
from U106 -15.
Test 0 Readback Port
Test a result is read back from port 03 (U650 on schematic <106>)
through U344-7 on schematic <103>.
Test 0 Run Sequence
1. HexOO is written to port OA (U314) <103>.
2. A pulse is sent to the port OE. This sets the page to B.
3. Hex40 is written to port 08 (U112) <101> so that the address
data can be read.
4. The test passes if hex10 is read at port 03.
Test 1 General Description
This test sets the U348A flip-flop to PAGE-A mode using port tOE
from U106 -14.
Test 1 Readback Port
Test 1 result is read back from port 03 (U650 on schematic <106»
through U344-7 on schematic <103>.
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Test 1 Run Sequence
1. HexOO is written to port OA (U314) <103>.
2. A pulse is sent to port OF. This sets the page to A.
3. Hex40 is written to port 08 (U112) <101> so that the address
data can be read.
4. The test passes if hex 00 can be read at port 03.
Test 2 General Description
This test loads U302 hexs5 and sends it to U304 and U316 using
the MPU clock, then U306 and U316 select the data for page-A
memory address bus RAOA-RA7A.
Test 2 Readback Port
Test 2 result are read back from port 03 (U6s0 on schematic
<106>) through U320 and U326.
Test 2 Run Sequence
1. A MPU clock path is selected.
2. Hex55 is written to port 09 (U302) <103>0
3. HexOO is written to port OA (U314) <103>.
4. A clock is sent from port 04 to load the data from U302 to
U304 and U3l6.
5. The test passes if hex55 can be read at port 03.
Test 3 General Description
This test loads U3l4 hexOs and sends it to U330 and U340 using
the MPU clock then U332 select the data for page-A memory address
bus RA8A-RA9A.
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Test 3 Readback Port
Test 3 results are read back from port 03 (U650 on schematic
<106» through U334-6,7 and U344-7.
Test 3 Run Sequence
1. An MPU clock path is selected.
2. Hex05 is written to port OA (U3l4) <103>.
3. A clock is sent from port 04 to load the data from U3l4 to
U330 and U340.
4. The test passes if hex05 is read at port 03.
Test 4 General Description
This test loads U302 with hexAA and sends it to U304 and U3l6
using the MPU clock, then U306 and U3l6 select the data for pageA memory address bus RAOA-RA7A.
Test 4 Readback Port
Test 4 results are read back from port 03 (U650 on schematic
<106» through U320 and U326.
Test 4 Run Sequence
1. An MPU clock path is selected.
2. HexAA is written to port 0 (U304) <103>.
3c A clock is sent from port 04 to load the data from U302 to
U304 and U3l6.
4. The test passes if hexAA is read at port 03.
Test 5 General Description
This test loads U3l4 hex04 and sends it to U330 and U340 using
the MPU clock then U332 selects the data for page-A memory
address bus RA8A-RA9A.
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Test 5 Readback Port
Test 5 results are read back from port 03 (U650 on schematic
<106» through U334-6,7 and U344-7.
Test 5 Run Sequence
1. An MPU clock path is selected.
2. Hex04 is written to port OA (U3l4) <103>.
3. A clock is sent from port 04 to load the data from U3l4 to
U330 and U340.
4. The test passes if hex04 is read at port 03.
Test 6 General Description
This test loads U302 and U3l4 with Os and sends it to U304, U3l6,
U330, and U340 using the MPU clock then single steps it to 555.
After each step, the vector generator is read through RAOA-RA9A
to verify that it contains the correct count.
Test 6 Readback Port
Test 6 result are read back from port 03 (U650 on schematic
<106» through U330, U340, U334, and U344.
Test 6 Run Sequence
1. An MPU clock path is selected.
2. HexOO is written to port 09 (U304) <103>.
3. HexOO is written to port OA (U314) <103>.
4. A clock is sent from port 04 to load the data from U304 and
U3l4 to U304, U3l6, U330, and U340.
5. Hex25 is written to port OA (U3l4) <103> and the vector
counter is set to the count mode.
6. 681 clock is sent from port 04.
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7. The test passes if hex555 is read at port 03.
Test 7 General Description
This test loads U302 and U3l4 with 555 and sends it to U304,
U3l6, U330, and U340 using the MPU clock then single steps it to
7FF. After each step, the vector generator is read through RAOARA9A to verify that it contains the correct count.
Test 7 Readback Port
Test 7 results are read back from port 03 (U650 on schematic
<106» through U330, U340, U334, and U344.
Test 7 Run Sequence
1. A MPU clock path is selected.
2. Hex55 is written to port 09 (U304) <103>.
3. Hex05 is written to port OA (U3l4) <103>.
4. A clock is sent from port 04 to load the data from U304 and
U3l4 to U304, U3l6, U330, and U340.
5. Hex25 is written to port OA (U3l4) <103> and set the vector
counter to the count mode.
6. 1366 clock is sent from port 04.
7. The test passes if hex7FF is read at port 03.
91532 FUNCTION
1 LOOP COUNT
CIRCUIT OVERVIEW
The loop counter consists of a l6-bit up-counter (Us 404, 406,
412, 414, and 416) which generates the stop signal for the loop
count function. When these counters reach their maximum count
(FFFF) stop latch U4l8 is set.
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FUNCTION DESCRIPTION
The LOOP COUNT function consists of five separate tests.
Test 0 loads the loop counter with FFFD, counts up to FFFE, and
reads back the carry.
Test 1 loads the loop counter with FFFE, counts up to FFFF, and
reads back the carry.
Test 2 loads the loop counter with EEEO, counts up to FFFE, and
reads back the carry.
Test 3 loads the loop counter with EEEO, counts up to FFFF, and
reads back the carry.
Test 4 loads the loop counter with 0000, counts up to FFFF, and
reads back the carry.
Readback Ports
Test data is read from U650 <106> through U344 <103>. When Ul12-9
(RD6(H»
is asserted, U334 and U344 is enabled, then STOP/START
data is sent through the RDB6 to the BD6.
Test 0 General Description
This test loads the loop counter with FFFD and then single steps
it to FFFE. After a step, The stop latch U418B <104> is read to
verify that it is not in the stop mode.
Test 0 Readback Port
Test 0 result is read back from port 03 (U650 on schematic <106»
through U344-11 <103>.
Test 0 Run Sequence
1.
An MPU clock path is selected.
2.
A pulse is sent to port OF and PAGE is set to A.
3.
HexFF is written to port 09 (U302) <103>.
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4.
Hex87 is written to port OA (U314) <103>.
5.
A clock is sent to port 04.
6.
Hex07 is written to port OA (U314) <103>.
7.
A pulse is sent to port OE and PAGE is set to B.
8.
HexAE is written to port 07 (U10 4) <101>.
9.
HexFD is written to port 04 (U406 and U412) <104>.
10. HexEE is written to port 07.
11. A pulse is sent to port OF and PAGE is set to A.
12. Hex6E is written to port 07.
13. HexFF is written to port 04 (U414 and U416) <104>.
14. HexEE is written to port 07.
15. HexFF is written to port 09.
16. HexA7 is written to port OA.
17. HexE8 is written to port 07.
18. A clock is sent to port 04.
19. Hex40 is written to port OS.
20. The test passes if hexSO is read at port 03.
Test 1 General Description
This test loads the loop counter with FFFE, then single steps it
to FFFF. After a step, the stop latch U41S <104> is read to
verify that it is in the stop mode.
Test 1 Readback Port
Test 1 results is read back from port 03 (U650 on schematic
<106» through U344-11 <103>.
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Test 1 Run Sequence
1.
An MPU clock path is selected.
2.
A pulse is sent to port OF and PAGE is set to A.
3.
HexFF is written to port 09 (U302) <103>.
4.
HexS7 is written to port OA (U314) <103>.
5.
A clock is sent to port 04.
6.
Hex07 is written to port OA (U314) <103>.
7.
A pulse is sent to port OE and PAGE is set to B.
S.
HexAE is written to port 07 (U104) <101>.
9.
HexFE is written to port 04 (U406 and U412) <104>.
10. HexEE is written to port 07.
11. A pulse is sent to port OF and PAGE is set to A.
12. Hex6E is written to port 07.
13. HexFF is written to port 04 (U414 and U416) <104>.
14. HexEE is written to port 07.
15. HexFF is written to port 09.
16. HexA7 is written to port OA.
17. HexES is written to port 07.
18. A clock is sent to port 04.
19. Hex40 is written to port 08.
20. The test passes if hexOO is read at port 03.
Test 2 General Description
This test loads the loop counter with EEEO, then single steps it
to FFFE. After a step, the stop latch U41S <104> is read toverify that it is not in the stop mode.
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Test 2 Readback Port
Test 2 Results is read back from port 03 (U650 on schematic
<106>) through U344-11 <103>.
Test 2 Run Sequence
1.
An MPU clock path is selected.
2.
A pulse is sent to port OF and PAGE is set to A.
3.
HexFF is written to port 09 (U302) <103>.
4.
HexS7 is written to port OA (U314) <103>.
5.
A clock is sent to port 04.
6.
Hex07 is written to port OA (U314) <103>.
7.
A pulse is sent to port OE and PAGE is set to B.
S.
HexAE is written to port 07 (U104) <101>.
9.
HexEO is written to port 04 (U406 and U412) <104>.
10. HexEE is written to port 07.
11. A pulse is sent to port OF and PAGE is set to A.
12. Hex6E is written to port 07.
13. HexEE is written to port 04 (U414 and U416) <104>.
14. HexEE is written to port 07.
15. HexFF is written to port 09.
16. HexA7 is written to port OA.
17. HexES is written to port 07.
IS. 43S2 clock is sent to port 04.
19. Hex40 is written to port OS.
20. The test passes if hexOO is read at port 03.
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Test 3 General Description
This test loads the loop counter with EEEO, then single steps it
to FFFF. After a step, the stop latch U41S <104> is read to
verify that it is in the stop mode.
Test 3 Readback Port
Test 3 result is read back from port 03 (U650 on schematic <106»
through U344-11 <103>.
Test 3 Run Sequence
1.
A MPU clock path is selected.
2.
A pulse is sent to port OF and PAGE is set to A.
3.
HexFF is written to port 09 (U302) <103>.
4.
HexS7 is written to port OA (U314) <103>.
5.
A clock is sent to port 04.
6.
Hex07 is written to port OA {U314} <103>.
7.
A pulse is sent to port OE and PAGE is set to B.
S.
HexAE is written to port 07 (U104) <101>.
9.
HexEO is written to port 04 (U406 and U412) <104>.
10. HexEE is written to port 07.
11. A pulse is sent to port OF and PAGE is set to A.
12. Hex6E is written to port 07.
13. HexEE is written to port 04 (U414 and U416) <104>.
14. HexEE is written to port 07.
15. HexFF is written to port 09.
16. HexA7 is written to port OA.
17. HexES is written to port 07.
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18. 4383 clock is sent to port 04.
19. Hex40 is written to port 08.
20. The test passes of hexOO is read at port 03.
Test 4 General Description
This test loads the loop counter with 0000, then single steps it
to FFFF. After a step, the stop latch U418 <104> is read to
verify that it is in the stop mode.
Test 4 Readback port
Test 3 results is read back from port 03 (U650 on schematic
<106» through U344-11 <103>.
I.
An MPU clock path is selected.
2.
A pulse is sent to port OF and PAGE is set to A.
3.
HexFF is written to port 09 (U302) <103>.
4.
Hex87 is written to port OA (U314) <103>.
5.
A clock is sent to port 04.
6.
Hex07 is written to port OA (U314) <103>.
7.
A pulse is sent to port OE and PAGE is set to B.
8.
HexAE is written to port 07 (U10 4) <101>.
9.
HexOO is written to port 04 (U406 and U412) <104>.
10. HexEE is written to port 07.
1I. A pulse is sent to port OF and PAGE is set to A.
12. Hex6E is written to port 07.
13. HexOO is written to port 04 (U414 and U416) <104>.
14. HexEE is written to port 07.
15. HexFF is written to port 09.
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16. HexA7 is written to port OA.
17. HexES is written to port 07.
IS. 65535 clock is sent to port 04.
19. Hex40 is written to port OS.
20. Data is read from port 03 and it is checked for hexSO.
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91S32 FUNCTION
2 VECTOR RAM
CIRCUIT OVERVIEW
The vector memory of the 91S32 consists of twenty 1024 X 4 bit
RAMs for a total of 2048 words by 40 bits.
FUNCTION DESCRIPTION
TEST 0 checks the write enable, chip select and the read/write
logic on the 91S32 memory.
Test
Test
Test
Test
Test
1
2
3
4
5
checks
checks
checks
checks
checks
U600,
U604,
U610,
U614,
U608,
U602,
U606,
U612,
U616,
U618,
U700,
U704,
U708,
U712,
U716,
and
and
and
and
and
U702
U706
U710
U714
U718
memory.
memory.
memory.
memory.
memory.
Readback Ports
Test data is read from U650 <106> through U620, U622, U624, U626,
U628, U630, U632, U634, U636, U638, U652, U654, U656, U658, U660,
U662, U664, 666, U668, and U670.
Test 0 General Description
This test checks the write enable and the read/write logic on the
91S32 memory.
Test 0 Readback Port
Test 0 results are read back from port 03 (U650 on schematic
<106» through 620 to U670.
The 91S32 VECTOR RAM TEST 0 provides test results like the
following:
2 VECTOR RAM
TEST 0
ADDR
53EF A
I
a
I
b
EXPECTED
OOOOOOAA
I
c
ACTUAL
00000000
I
d
PASS
I
e
a. This indicates memory address error bit position plus one. If
this value is 5 then address 4 line (pin 8) is bad.
b. This indicates. test address pattern.
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c. This indicates the error page, page-A or page-B.
d. This indicates expected data. This always shows AAAAAAAA,
55555555, OOOOOOAA, or 00000055. The OOOOOOAA and 00000055
pattern is used for 0608, U618, U716, and U718. The AAAAAAAA and
55555555 pattern is used for another 10422 memory. This means the
following.
AAAAAAAA
55555555
I »»» U600,U700
I»»»>
U602,U702
»»»»
»»»»>
»»»»»
»»»»»>
»»»»»»
»»»»»»>
U604,0704
U606,U706
U610,0708
U612,0710
U614,0712
U616,U714
OOOOOOAA
00000055
' »»»
I»»»>
U608,U716
U618,0718
e. This is the data pattern which is actually read from memory.
Test 0 Run Sequence
1.
2.
3.
4.
HexOO is written to entire memory.
Hex55 is written to memory address hex001.
HexAA is written to memory address hexOOO.
Data is read from memory address hex001 and is expected to
compare with hex55.
5. HexOO is written to memory address hex001.
6. Hex55 is written to memory address hex002.
7. HexAA is written to memory address hexOOO.
8. Data is read from memory address hex002 and is expected to
compare with hex55.
9. HexOO is written to memory address hex002.
10. Hex55 is written to memory address hex004.
11. HexAA is written to memory address hexOOO.
12. Data is read from memory address hex004 and is expected to
compare with hex55.
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13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
HexOO is written to memory address hex004.
Hex55 is written to memory address hex008.
HexAA is written to memory address hexOOO.
Data is read from memory address hex008 and
compare with hex55.
HexOO is written to memory address hex008.
Hex55 is written to memory address hexOl0.
HexAA is written to memory address hexOOO.
Data is read from memory address hex010 and
compare with hex55.
HexOO is written to memory address hexOl0.
Hex55 is written to memory address hex020.
HexAA is written to memory address hexOOO.
Data is read from memory address hex020 and
compare with hex55.
HexOO is written to memory address hex020.
Hex55 is written to memory address hex040.
HexAA is written to memory address hexOOO.
Data is read from memory address hex040 and
compare with hex55.
HexOO is written to memory address hex040.
Hex55 is written to memory address hex080.
HexAA is written to memory address hexOOO.
Data is read from memory address hex080 and
compare with hex55.
HexOO is written to memory address hex080.
Hex55 is written to memory address hexl00.
HexAA is written to memory address hexOOO.
Data is read from memory address hexl00 and
compare with hex55.
HexOO is written to memory address hexl00.
HexOO is written to entire memory.
HexAA is written to memory address hex7FE.
Hex55 is written to menory address hex7FF.
Data is read from memory address hex7FE and
compare with hexAA.
HexOO is written to memory address hex7FE.
HexAA is written to memory address hex7FD.
Hex55 is written to memory address hex7FF.
Data is read from memory address hex7FD and
compare with hexAA.
HexOO is written to memory address hex7FD.
HexAA is written to memory address hex7FB.
Hex55 is written to memory address hex7FF/
Data is read from memory address hex7FB and
compare with hexAA.
HexOO is written to memory address hex7FB.
HexAA is written to memory address hex7F7.
Hex55 is written to memory address hex7EF.
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is expected to
is expected to
is expected to
is expected to
is expected to
is expected to
is expected to
is expected to
is expected to
Maint: Diagnostic Test Descriptions
DAB 9100 Series 91S16-91S32 Service
53. Data is read from memory address hex7F7 and
compare with hexAA.
54. HexOO is written to memory address hex7F7.
55. HexAA is written to memory address hex7EF.
56. Hex55 is written to memory address hex7FF.
57. Data is read from memory address hex7DF and
compare with hexAA.
58. HexOQ is written to memory address hex7EF.
59. HexAA is written to memory address hex7DF.
60. Hex55 is written to memory address hex7FF.
61. Data is read from memory address hex7DF and
compare with hexAA.
62. HexOO is written to memory address hex7DF.
63. HexAA is written to memory address hex7BF.
64. Hex55 is written to memory address hex7FF.
65. Data is read from memory address hex7BF and
compare with hexAA.
66. HexOO is written to memory address hex7BF.
67. HexAA is written to memory address hex77F.
68. Hex55 is written to memory address hex7FF.
69. Data is read from memory address hex77F and
compare with hexAA.
70. HexOO is written to memory address hex77F.
71. HexAA is written to memory address hex6FF.
72. Hex55 is written to memory address hex7FF.
73. Data is read from memory address hex6FF and
compare with hexAA.
74. HexOO is written to memory address hex6FF.
75. HexAA is written to memory address hex5FF.
76. Hex55 is written to memory address hex7FF.
77. Data is read from memory address hex5FF and
compare with hexAA.
78. HexOO is written to memory address hex5FF.
79. HexAA is written to memory address hex3FF.
80. Hex55 is written to memory address hex7FF.
81. DAta is read from memory address hex3FF and
compare with hexAA.
82. HexOO is written to memory address hex3FF.
is expected to
is expected to
is expected to
is expected to
is expected to
is expected to
is expected to
is expected to
The DAS should display EXPECT 0000 and ACTUAL 0000.
Test 1 Genera1 Description
This test loads U600, U602, U700, and U702 with 55 and is read
through the memory readback ports (U~s 620, 622, 624, 626, and
650 <106». It is checked for hex55 then loaded with hexAA and
verified as hexAA.
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Test 1 Readback Port
Test 1 results are read back from port 03 (U650 on schematic
<106» through U620, U622, U624, and U626.
Test 1 Run Sequence
1.
2.
3.
4.
HexOO
Hex55
HexOO
These
up.
5. HexAA
these
6. HexOO
7. These
up.
is written to U600, U602, U700, and U702.
is written to the same memory and the data is read back.
is written to the tested address memory.
data are checked one by one when the address is counted
is written to these memory and the data is read from
memory.
is written to the tested address memory.
data are checked one by one when the address is counted
Test 2 General Description
This test loads U604, U606, U704, and U706 with 55 and is read
through the memory readback ports (U~s 628, 630, 632, 634, and
650 <106» and checked for accuracy. It then loads the memory
with AA and checks for accuracy.
Test 2 Readback Port
Test 2 results are read back from port 03 (U650 on schematic
<106» through U628, U630, U632, and U634.
Test 2 Run Sequence
1. HexOO is written to whole address of U604, U606, U704, and
U702.
2. Hex55 is written to the memory and the data is read from these
memory.
3. HexOO is written to the tested address memory.
4. These data are checked one by one when the address is counted
up.
5. HexAA is written to the memory and the data is read from these
memory.
6. HexOO is written to the tested address memory.
7. These data are checked one by one when the address is counted
up.
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Test 3 General Description
This test loads U610, U612, U708, and U710 with 55 and is read
through the memory readback ports (U~s 652, 654, 656, 658, and
650 <106» and checked for accuracy. It then loads the memory
with AA and checks for accuracy_
Test 3 Readback Port
Test 3 results are read back from port 03 (U650 on schematic
<106» through U652, U654, U656, and U658c
Test 3 Run Sequence
1. HexOO is written to entire address of U610, U612, U708, and
U710.
2. Hex55 is written to these memory and the data is read from the
memory.
3. HexOO is written to the tested address memory.
4. These data are checked one by one when the address is counted
up.
5. HexAA is written to these memory and the data is read from the
memory.
6. HexOO is written to the tested address memory.
7. These data are checked one by one when the address is counted
up.
Test 4 General Description
This test loads U614, U616, U712, and U714 with 55 and is read
through the memory readback ports (U~s 660, 662, 664, 666, and
650 <106» and checked for accuracy. It then loads these memory
with AA and checks for accuracy.
Test 4 Readback Port
Test 4 results are read back from port 03 (U650 on schematic
<106» through U660, U662, U664, and U666.
Test 4 Run Sequence
1. HexOO is written to entire address of U614, U616, U712, and
U714.
2. Hex55 is written to the memory and the data is read from the
memory.
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3. HexOO is written to the tested address memory.
4. These data are checked one by one when the address is counted
up.
5. HexAA is written to these memory and the data is read from the
memory.
6. HexOO is written to the tested address memory.
7. These data are checked one by one when the address is counted
up.
Test 5 General Description
This test loads U608, U618, U716, and U7l8 with 55 and is read
through the memory readback ports (U~s 636, 638, 668, 670, and
650 <106» and checked for accuracy. It then loads these memory
with AA and checks for accuracy.
Test 5 Readback Port
Test 5 results are read back from port 03 (U650 on schematic
<106» through U636, U638, U668, and U670.
Test 5 Run Sequence
1. HexOO is written to whole address of U608, U618, U716, and
U7l8.
2. Hex55 is written to these memory and the data is read from the
memory.
3. HexOD is written to the tested address memory.
4. These data are checked one by one when the address is counted
up.
5. HexAA is written to these memory and the data is read from the
memory.
6. HexDD is written to the tested address memory.
7. The data is checked one by one when the address is counted up.
91S32 PUNCTION
3 eLK SEL
CIRCUIT OVERVIEW
The clock selector is made up of NOR gates U208 and U216.
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FUNCTION DESCRIPTION
The eLK SEL function consists of six separate tests.
Test
Test
Test
Test
Test
Test
Test
0
1
2
3
4
5
6
checks
checks
checks
checks
checks
checks
checks
the
the
the
the
the
the
the
step or trace mode clock.
pause line low state.
pause line high state.
MPU load clock.
91A08 clock.
91A32 clock.
EXT clock.
Readback Ports
Test data is read from U650 <106> through U344 <103>. When Ul12-0
(RD6 H) ) is asserted, U334 and U344 is enabled, and then
STOP/START signal line data is sent through the RDB6 to the BD6.
Test 0 General Description
This test checks the step or trace mode clock. The step clock
gate U2l6-7 <102> is set low and sends a clock from hex04 port,
then reads the state of flip-flop U4l8B <104>.
Test 0 Readback Port
Test 0 results are read back from port 03 (U650 on schematic
<106» through U344-ll <103>.
1.
2.
3.
4.
5.
The loop counter is loaded with hexFFFD.
HexFO is written to port 07 (U104) <101>.
A clock is sent from port 04.
Hex40 is written to port 08 (U112) <101>.
The test passes if hexOO is read at port 03.
Test 1 General Description
This test sets the pause line low. The pause line gate U208-l3,
the stop gate U2l6-5 and MPU clock gate U2l6-ll <102> are set low
and send a clock from port hex04, then reads the state of stop
flip-flop U4l8B <104>.
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Test 1 Readback Port
Test 1 results are read back from port 03 (U650 on schematic
<106» through U344-ll <103>.
Test 1 Run Sequence
1.
2.
3.
4.
5.
The loop counter is loaded with hexFFFD.
HexFO is written to port 07 (Ul04) <101>.
A clock is sent twice from port 04.
Hex40 is written to port OS (Ul12) <101>.
Test passes if hexOO is read at port 03.
Test 2 General Description
This test sets the pause line high state. The pause line gate
U20S-13, the stop gate U2l6-5 and MPU clock gate U2l6-11 <102>
are set low and send a clock from port hex04. It then reads 91532
stop flip-flop U4lSB <104> state.
Test 2 Readback Port
Test 2 results are read back from port 03 (U650 on schematic
<106» through U344-1l <103>.
Test 2 Run Sequence
1.
2.
3.
4.
5.
6.
7.
S.
9.
10.
HexOO is written to the Trigger/Time Base port 02.
Hex07 is written to the Trigger/Time Base port 00.
The loop counter is loaded with hexFFFD.
HexES is written to port 07 (Ul04) <101>.
HexCF is written to port OC (U514) <105>.
HexFO is written to port 00 (U72S) <107>.
A clock is sent twice from port 04.
Hex40 is written to port OS (Ul12) <101>.
Test passes if hexOO is read at port 03.
HexOS is written to the Trigger/Time Base port 02.
Test 3 General Description
This test checks the MPU load clock. MPU clock gate U2l6-ll
is<102> set low and receives a clock from hex04 port. It then
reads the state of stop flip-flop U4lSB <104>.
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Test 3 Readback Port
Test 3 results are read back from port 03 (U650 on schematic
<106» through U344-l1 <103>.
Test 3 Run Sequence
1.
2.
HexOO is written to the Trigger/Time Base port 02.
Hex27 is written to the Trigger/Time Base port 00.
3. The loop counter is loaded with hexFFFD.
4. HexES is written to port 07 (U104) <101>.
5. HexCF is written to port OC (U514) <105>.
6. HexFO is written to port 00 (U72S) <107>.
7. A clock is sent twice from port 04.
S. Hex40 is written to port OS (Ul12) <101>.
9. Test passes if hexOS is read at port 03.
10. HexOS is written to the Trigger/Time Base port 02.
Test 4 General Description
This test checks the Trigger/Time Base 91AOS CLK line. The
91AOSCLKCTRL line U20S-5 <102> is set low and receives a 91AOS
clock from Trigger/Time Base board. It then reads the state of
stop flip-flop U41SB <104>.
Test 4 Readback Port
Test 4 results are read back from port 03 (U650 on schematic
<106» through U344-11 <103>.
Test 4 Run Sequence
1. The loop counter is loaded with hexFFFD.
2. HexES is written to Trigger/Time Base port 04.
3. HexFS is written to port 07 (U104) <101>.
4. HexD4 is written to port 00 (U72S) <107>.
5. A clock is sent twice from Trigger/Time Base port 09.
6. Hex40 is written to port OS.
7. Test passes if hexOO is read at port 03.
Test 5 General Description
This test checks the Trigger/Time Base 91A32 CLK line. The
91A32CLKCTRL line U20S-7 <102> is set low and receives a 91A32
clock from Trigger/Time Base board. It then reads the state of
stop flip-flop U41Sa <104>.
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DAS 9100 Series 91S16-91S32 Service
Test 5 Readback Port
Test 5 results are read back from port 03 (U650 on schematic
<106» through U344-11 <103>.
Test 5 Run Sequence
1.
2.
3.
4.
5.
6.
7.
The loop counter is loaded with hexFFFD.
HexES is written to Trigger/Time Base port 00.
HexFS is written to port 07 (U104) <101>.
HexB4 is written to port 00 (U72S) <107>.
A clock is sent twice from Trigger/Time Base port 09.
Hex40 is written to port OS.
Test passes if hexOO is read at port 03.
Test 6 General Description
This test checks the Trigger/Time Base EXT CLK line. The PG EXT
CLK CTRL line U20S-11 <102> is set low and receives a PG EXT CLK
from Trigger/Time Base board. It then reads the state of stop
flip-flop U41SB <104>.
Test 6 Readback Port
Test 6 results are read back from port 03 (U650 on schematic
<106» through U344-11 <103>.
~est
6 Run Sequence
l. The loop counter is loaded with hexFFFD.
2.
3.
4.
5.
6.
7.
S.
9.
Hex07 is written to Trigger/Time Base port
HexFS is written to port 07 (U104) <101>.
Hex74 is written to port 00 (U72S) <107>.
Hex17 is written to Trigger/Time Base port
Hex07 is written to Trigger/Time Base port
Hex17 is written to Trigger/Time Base port
Hex40 is written to port OS.
Test passes if hexOO is read at port 03.
8-91
00.
00.
00.
00.
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
91S32 FUNCTION
4 START FF
CIRCUIT OVERVIEW
The start flip>flop is made up of NOR gate and flip-flop UIOO amd
U41S <104>
FUNCTION DESCRIPTION
The START FF function consists of three separate tests.
Test 0 verifies the start flip-flop reset line.
Test 1 verifies the start flip-flop set line.
Test 2 verifies the start 91S32 line from Trigger/Time Base
board.
Test 0 General Description
This test verifies the START flip-flop U41S <104> RESET line.
Test 0 Readback Port
Test 0 results are read back from port 03 (U650 on schematic
<106» through U344-9 <103>.
Test 0 Run Sequence
1.
2.
3.
4.
HexF9 is written to port 07.
HexFS is written to port 07.
Hex40 is written to port OS.
Test passes if hexOO is read at port 03.
Test 1 General Description
This test verifies the START flip-flop U4l8 <104> SET line.
Test 1 Readback Port
Test 1 results are read back from port 03 (U650 on schematic
<106» through U344~9 <103>.
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DAS 9100 Series 91S16-91S32 Service
Test 1 Run Sequence
1.
2.
3.
4.
HexFA is written to port 07.
HexF8 is written to port 07.
Hex40 is written to port 08.
Test passes if hex40 is read at port 03.
Test 2 General Description
This test verifies the START flip-flop U418 <104> START line from
Trigger/Time Base board.
Test 2 Readback Port
Test 2 result are read back from port 03 (U650 on schematic
<106» through U344-9 <103>.
Test 2 Run Sequence
1. Hex07 is written to Trigger/Time Base port 00.
2.
3.
4.
5.
6.
7.
HexE4 is written to 9lS32 port 00.
HexF9 is written to port 07.
HexF8 is written to port 07.
Hex47 is written to Trigger/Time Base port 00.
Hex40 is written to port 08.
Test passes if hex40 is read at port 03.
91S32 FUNCTION
5 INHIBIT
CIRCUIT OVERVIEW
The inhibit circuit is made up of OR, NOR, and EXCLUSIVE OR GATES
as follows: UIOO <104>, U228 <102>, U648 <106>, and U730 <107>.
FUNCTION DESCRIP'.rION
The INHIBIT function consists of two separate tests.
Test 0 checks the inhibit line high state.
Test 1 checks the inhibit line low state.
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DAS 9100 Series 91516-91532 Service
Readback Ports
Test
{RD6
line
RDB2
data is read from U650 <106> through U344 <103>. When Ull2-9
(H)
is asserted, U334 and U344 are enabled. INHIBIT signal
data is selected by U22S-7 <102> and is sent through the
to BD2.
Test 0 General Description
This test checks for a high on the INHIBIT line from the
Trigger/Time Base.
Test 0 Readback Port
Test 0 results are read back from port 03 (U650 on schematic
<106» through U334-9 <103>.
Test 0 Run Sequence
1.
2.
3.
4.
Hex07 is written to Trigger/Time Base port 00.
HexF5 is written to port 00.
Hex40 is written to port OS.
Test passes if hexOO is read at port 03.
Test 1 General Description
This test checks for a low on the INHIBIT line from the
Trigger/Time Base.
Test 1 Readback Port
Test 1 results are read back from port 03 (U650 on schematic
<106» through U334-9 <103>.
Test 1 Run Sequence
1.
2.
3.
4.
HexS7 is written to Trigger/Time Base port 00.
HexF5 is written to port 00.
Hex40 is written to port OS.
Test passes if hex04 is read at port 03.
8-94
Maint: Diagnostic Test Descriptions
DAB 9100 5eries 91516-91532 5ervice
91532 FUNCTION
6 PROBE IF
CIRCUIT OVERVIEW
The probe interface consists of U120 receiver, US16 latch, and
US22 buffer.
FUNCTION DESCRIPTION
The PROBE IF function consists of two separate tests.
Test 0 writes hexOS to US20 and reads it from U120.
Test 1 writes hexOA to US20 and reads it from U120.
Readback Ports
Test data is read from U120 <101>. When Ul18-S (POD5TATU5 (L») is
asserted, U120 is enabled, and data is read from the data bus
(BDO-BD3) •
Test 0 General Description
This test writes hexOS to US20 port i03 and reads it from U120.
Test 0 Readback Port
Test 0 result are read back through port 01 (U120 on schematic
<101» •
Test 0 Run Sequence
1.
2.
3.
4.
Data is read from port 02.
HexOS is written to port 03.
Hex01 is written to port 02.
Test passes if hexOS is read at port 03.
5. HexOO is written to port 02.
6. HexOF is written to port 03.
Test 1 General Description
This test writes hexOA to US20 (port i03) and reads it from U120.
8-95
Maint: Diagnostic Test Descriptions
DAB 9100 Series 91516-91532 Service
Test 1 Readback Port
Test 1 results are read back through port 01 (U120 on schematic
<101».
Test 1 Run Sequence
1.
2.
3.
4.
S.
6.
Data is read from port 02.
HexOA is written to port 03.
HexOl is written to port 02.
Test passes if hexOA is read at port 03.
HexOO is written to port 02.
HexOF is written to port 03.
91532 FUNCTION
7 BUFFER
CIRCUIT OVERVIEW
The buffer circuit consists of three 10115 (U~s 300, 308, and
312) and a 10116 (U220), and a 10Hl02 (U228).
FUNCTION DESCRIPTION
The BUFFER function consists of two blocks. The first block,
which tests the 91532 clock circuit, consists of three tests.
Test 0 checks the internal clock buffer and receiver.
Test 1 checks the master clock buffer and slave clock receiver.
Test 2 checks the slave clock receiver.
The second block tests the signal from the 91516, and consists of
seven separate tests.
Test 0 receives address data hex1S5 from the 91516.
Test 1 receives address data hex2AA from the 91516.
Test 2 checks the 91516 clock for the 91532.
Test 3 checks the 91516 divided clock for the 91532.
8-96
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
Test 4 verifies 91516 PAGE, FULL line LOW state.
Test S verifies the 91516 PAGE signal line.
Test 6 verifies the 91516 FULL signal line.
Readback Ports
Test data is read from U650 <106> through U320, U326, U334, and
U344 <103>. When Ul12-l5 (RDS(H) is asserted, U320 and U326 are
enabled and data is sent from RAOA-RA7A to RDBO-RDB7. When Ul129 (RD6{H»
is asserted, U334 and U344 are enabled and data is
sent from RA8A-RA9A and PAGE 5ELECT signal to RDBO-RDB7.
This test changes according to the 91516 configuration.
If a
91516 is installed, the buffer test runs from 0 to 6. If there
is no 91516 installed, only one test is run.
91532 Only
Test 0 General Description
Test 0 results are read back from port 03 (U650 on schematic
<106» through U344-5 (schematic <103».
Test 0 Run Sequence
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Hex40 is written to port OA on each 91532 installed.
HexF4 is written to port 00.
Hex3F is written to port 06.
HexEE is written to port 07
HexEC is written to port 07.
HexOO is written to port OA.
HexFF is written to port OB.
Hex6F is written to port 00.
Hex40 is written to port 08.
Port 03 is set to hexOO.
A clock is sent to port 04.
Data is read from port 03, and verifies that the data has
changed to hex20.
Test 1 Genera1 Description
This test sends out an MPU clock from the master board to the
slaved 91532.
It then verifies that the clock has been received.
8-97
Maint: Diagnostic Test Descriptions
DAB 9100 Series 91S16-91S32 Service
Test 1 Readpack Port
Test results are read back from port 03 (U6S0 on schematic <106>
through U344-5 <103>.
Test 1 Run Sequence
1.
2.
3.
4.
5.
Hex40 is written to port OA on all 9lS32s installed.
HexOO is written to port OA on the master board.
Port 03 is set to hex20.
A clock is sent from the master board.
Data is read from port 03, and it is verified that the data
has changed to hexOO.
Test 2 General Description
This test sends no MPU clock from the master board, and the
slaved 9lS32 is checked for non-receipt of clock.
Test 2 Readback Port
Test results are read back from port 03 (U650 on schematic <106>
through U344-5 <103>.
Test 2 Run Sequence
1.
2.
3.
4.
Hex40 is written to port OA of all 9lS32s installed.
HexOO is written to port OA of the master board.
Port 03 is set to hex20.
Data is read from port 03, and data is verified to be hex20.
8-98
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91516-91532 Service
91532 with 91516
Test 0 General Description
This test checks the address receiver, multiplexer, and readback
comparator. The 91516 sends address hexlSS to P2, and:
U300, U30S, and U3l2 <103> receive it,
U306, U3lS, and U332 select it,
U320, U326, U334 <103> and U6S0 <106> reads it.
This verifies the address to be hex1SS.
Test 0 Readback Port
Test 0 results are read back from port 03 (U6S0 on schematic
<106» through U320, U326, and U334 <103>.
Test 0 Run Sequence
1.
2.
3.
4.
S.
6.
7.
S.
9.
10.
Address hex1SS is sent from the 91516.
HexOO is written to port OA.
A pulse is sent to port OF.
Hex40 is written to port OS.
Data is read from port 03, and is memorized.
HexOO is written to port OA.
A pulse is sent to port OF.
Hex20 is written to port OS.
Data is read from port 03 and added to the memorized data.
The data in step 9 is verified to be hexlSS.
Test 1 General Description
This test checks the address receiver, multiplexer, and readback
comparator. The 91516 sends address hex2AA to P2. U300, U30S,
and U3l2 <103> and U6S0 <106> read the address to verify that it
is hex2AA.
Test 1 Readback Port
Test results are read back from port 03 (U6S0 on schematic <106»
through U320, U326, and U334 <103>.
8-99
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Test 1 Run Sequence
1.
2.
3.
4.
5.
6.
7.
S.
9.
Address hex2AA is sent from the 9lSl6.
HexOO is written to port OA.
A pulse is sent to port OF.
Hex40 is written to port OA.
Data is read from port 03 and memorized.
HexOO is written to port OA.
A pulse is sent to port OF.
Hex20 is written to port OS.
Data is read from port 03, and is added to the memorized
data.
10. The data in step 9 is verified to be hex2AA.
Test 2 General Description
This test verifies the 9lS16 clock to the 9lS32.
Test 2 Readback Port
Test results are read back from port 03 (U650 on schematic <106»
through U320, U326, and U334 <103>.
Test 2 Run Sequence
1.
2.
3.
4.
5.
6.
7.
The 9lS16 generates a clock for the 9lS32.
The loop counter is loaded with hexFFFD.
HexFS is written to port 07.
HexAF is written to port OC.
The 9lS16 sends a clock twice to the 9lS32.
Hex40 is written to port OS.
Data is read from port 03, and verified to be HexOO.
Test 3 General Description
This test verifies the 9lSl6 divided clock to the 91S32.
Test 3 Readback Port
Test results are read back from port 03 (U650 on schematic <106»
through U320, U326, and U334 <103>.
Test 3 Run Sequence
1.
2.
3.
4.
The 9lSl6 generates
The loop counter is
HexFS is written to
HexAF is written to
a divided clock for the 9lS32.
loaded with hexFFFD.
port 07.
port OC.
8-100
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
5.
6.
7.
The 91516 sends a divided clock twice to the 91532.
Hex40 is written to port 08.
Data is read from port 03, and verified to be HexOO.
Test 4 General Description
This test sets the 91516 PAGE FULL line low, reads the PAGE
signal level, sends a clock from the 91816, reads the PAGE signal
line again, and checks the difference.
Test 4 Readback Port
Test results are read back from port 03 (U650 on schematic <106»
through U320, U326, and U334 <103>.
Test 4 Run Sequence
1.
2.
3.
4.
5.
6.
7.
HexOO is written to port OA.
HexD8 is written to port 07.
The 91816 sets PAGE and FULL lines low.
Hex40 is written to port 08.
Data is read from port 03, and is memorized.
A clock is sent from the 91816.
Data is read from port 03, and compared with the memorized
data.
Test 5 General Description
This test sets the 91816 FULL signal line high, reads the PAGE
signal level, sends a clock from the 91816, reads the PAGE line
again, and checks the difference.
Test 5 Readback Port
Test results are read back from port 03 (U650 on schematic <106»
through U320, U326, and U334 <103>.
8-101
Maint: Diagnostic Test Descriptions
DAS 9100 Series 91S16-91S32 Service
Test 5 Run Sequence
1.
2.
3.
4.
5.
6.
7.
HexOO is written to port OA.
HexDB is written to port 07.
Hex40 is written to port OB.
Data is read from port 03, and is memorized.
The 9lSl6 sets the PAGE line low.
The 9lSl6 sends a clock to the 9lS32.
Data is read from port 03 and compared with the memorized
data.
Test 6 General Description
This test sets the 9lSl6 FULL line high, reads the PAGE signal
level, sends a clock from the 9lSl6, reads the PAGE line again,
and checks the difference.
Test 6 Readback Port
Test results are read back from port 03 (U6S0 on schematic <106»
through 0320, U326, and 0334 <103>.
Test 6 RUD Sequence
1.
2.
3.
4.
5.
6.
7.
B.
HexOO is written to port OA.
Hex DB is written to port 07.
The 9lSl6 generates a FOLL signal low sequence.
Hex40 is written to port OB.
Data is read from port 03 and memorized.
The 9lSl6 sets FOLL to a low level.
The 9lSl6 sends a clock to the 9lS32.
Data is read from port 03 and compared with the memorized
data.
8-102
Section 9
REFERENCE INFORMATION
This section contains diagrams and look-up tables to assist
service personnel in identifying cable connections; locating test
points, adjustments, and jumpers; and identifying signal
functions.
System Connections
Figures 9-1 and 9-2 show how the 91516 and 91532 are connected to
each other, to the DA5, and to the device under test. Table 9-1
identifies the signals passed between the 91516 and the 91532 in
a master-slave configuration.
(SEE NOTE)
./
P6464
----<
----<
DEVICE
UNDER
P6464
.....
,
TEST
(OUT)
P6460
.....
,
SYNC
PULSE OUTPUT L---/
FORSCOPE ~
TTL START
PULSE
>-<
tp2
( J100 (POD A)
(
J120 (POD B)
(
J140 (POD C)
l' FLAT
A CABLE
91S16
~ J180
( J140
P1
PO
~
~
v
HIGH·SPEED BUS
V
CPU BUS
DAS
5397-83
NOTE
This is an output to the slaved 91532(s), and is not
used in the 91516-only configuration. See Table 9-1
for signal details.
Figure 9-1.
91S16 cable connections.
9-1
Reference Information
DAB 9100 Series 91S16-91S32 Service
(SEE NOTE)
I
P6464
DEVICE
UNDER
TEST
(OUT)
I
tp2
( J200 (POD 8)
<
:
P6464
:
FlAT
CABLE
( J100 (PODA)
I
P6464
t
( J300 (POD C)
91S32
( J400 (POD D)
P6464 JL
P1
PO
J,
t
V
HIGH-SPEED BUS
V
CPU BUS
DAS
5397-84
NOTES
1.
Not used in the single-9l532 configuration.
2.
This is an output to the slave 91532(5) if this
91532 is the master.
3.
This is the input from the master 91816 or 91832 if
this 91832 is the slave.
4.
8ee Table 9-1 for signal details.
Figure 9-2.
91S32 cable connections.
9-2
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-1
91S16/91S32 P2 SIGNAL DETAIL
Signal
GND
Pin
91S32 Jumper
Connector
Bl to B20
none
GND
Al
none
EXAO
A2
P302
EXAl
A3
P304
EXA2
A4
P306
EXA3
AS
P308
EXA4
A6
P3l0
EXAS
A7
P3l2
EXA6
A8
P3l4
EXA7
A9
P3l6
EXA8
AlO
P318
EXA9
All
P320
PAGE
Al2
P322
FULL
A13
P324
S16INHIBIT (L)
Al4
PlO2
GND
AIS
none
S16CLK(H)
Al6
P202
S16CLK(L)
Al7
P204
GND
A18
none
ICLK(H)
A19
P206
ICLK (L)
A20
P208
9-3
Reference Information
DAS 9100 Series 91516-91532 Service
Test Point, Jumper, and AdjustBent Locations
Test points, jumpers, and adjustments are listed in Tables 9-2
and 9-3 (91516) and Tables 9-4 and 9-5 (91532). The tables are
arranged in pairs. Test points, jumpers and adjustments are first
listed alpha-numerically by component designation number~ then
the list is repeated alpha-numerically by the signal description.
Schematic and board location zones are provided in each table.
Refer to the Diagrams section of this addendum for parts-location
drawings and schematics.
Table 9-2
91516 TBS'r POnr.rs, JUMPERS, AND ADJUS'rMBN'.rS (COMPONENT LISTING)
Component
Location Zone
Board Schematic
Description
DL700
BI
<98> C3
Last-latch clock line delay
adjustment
DL720
Bl
<98> El
P6464 clock-line delay adjustment
(with DL740)
DL740
BI
<98> E5
Part of P6464 clock-line delay
adjustment (with DL720)
DL760
Bl
<98> D3
POD-clock delay adjustment (with
DL780)
DL780
Bl
<98> D3
POD-clock delay adjustment (with
DL760)
DL800
C2
<99> CI
First-latch clock line delay
adjustment
DL820
C2
<99> Cl
OUT CLOCK delay adjustment
R390
C4
<94> D5
Threshold adjustment, 0.00
V
+2 mV
R392
C4
<94> D5
Threshold adjustment, -1.587
V
+2 mV
TP200
A4
<93> A4
External clock input from P6460
9-4
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-2 (cont.)
91S16 TEST POINTS, JUMPERS, AND ADJUSTMENTS (COMPONENT LISTING)
Component
Location Zone
Board Schematic
Description
TP240
03
<93> Cl
TTL START input circuit, output
signal
TP280
E4
<93> F4
Clock reference for system clock
TP400
E2
<95> B5
Program counter output
TP440
E2
<95> 05
Address register reset
TP600
C2
<97> Al
Register clock
TP6l0
C2
<97> Fl
First-latch clock line delay
TP700
Bl
<98> E2
Last-latch clock delay
TP720
Al
<98> El
P6464 clock-line delay
TP760
A2
<98> E5
Threshold, 0.00 V +2 mV
TP780
Al
<98> Fl
P6464 clock-line reference
TP800
B3
<99> B2
Inhibit input
TP860
G2
<98> A4
Ground reference to OAS
TP9l0
F4
<98> A4
Ground reference to OAS
TP930
E3
<98> A3
Ground reference to OAS
TP940
F3
<98> A3
Ground reference to OAS
TP950
C2
<98> A3
Ground reference to OAS
TP960
Bl
<98> A3
Ground reference to OAS
TP970
A3
<98> A3
Ground reference to OAS
TP980
F2
<93> F4
SIG CLOCK output to 9lS32
TP990
G2
<98> Al
+3 V power supply
9-5
Reference Information
DAB 9100 Series 91516-91532 Service
Table 9-3
91S16 TEST POrNTS, JUMPERS, AND ADJUSTMENTS (SIGNAL LISTING)
Location Zone
Board
Schematic
Description
Address register reset, TP440
E2
<95> D5
CLOCK output to 91S32, TP980
F2
<93> F4
Clock reference for system clock, TP280
E4
<93> F4
Clock from P6460, TP200
A4
<93> A4
First-latch clock line
delay adjustment, DL800
C3
<99> Dl
First-latch clock line delay, TP6l0
C2
<97> FI
Ground reference to DAS, TP860
G2
<98> A4
Ground reference to DAS, TP9l0
F4
<98> A4
Ground reference to DAS, TP930
E3
<98> A3
Ground reference to DAS, TP940
F3
<98> A3
Ground reference to DAS, TP950
C2
<98> A3
Ground reference to DAS, TP960
Bl
<98> A3
Ground reference to DAS, TP970
A3
<98> A3
Inhibit input, TP800
B3
<99> B2
Last-latch clock line
delay adjustment, DL700
Bl
<98> C3
Last-latch clock delay, TP700
Bl
<98> E2
OUT CLOCK delay adjustment, DL820
C2
<99> Cl
P6464 clock-line delay
adjustment, DL720 (with DL740)
Bl
<98> El
P6464 clock-line
delay adjustment, DL740 (with DL720)
Bl
<98> ES
P6464 clock-line delay, TP720
Al
<98> El
9-6
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-3 (Cont.)
91S16 TEST POIN"l'S, JUMPERS, AND ADJUSTMENTS (SIGNAL LISTING)
Location Zone
Board
Schematic
Description
P6464 clock-line reference, TP780
Al
<98> Fl
POD-clock delay adjustment,
DL760 (with DL780)
Bl
<98> 03
POD-clock delay adjustment,
DL780 (with OL760)
Bl
<98> 03
Program counter output, TP400
E2
<95> BS
Register clock, TP600
C2
<97> Al
Threshold adjustment, 0.00 V +2 mV, R390
C4
<94> 05
Threshold adjustment, 1.587 V +2 mV, R392
C4
<94> 05
Threshold, 0.00 V
A2
<98> ES
TTL START input circuit, output of, TP240
03
<93> Cl
+3 V power supply, TP990
G2
<98> Al
~2
mV, TP760
9-7
Reference Information
DAB 9100 Series 91S16-91S32 Service
91S32
TBS~
Component
Table 9-4
POrRTS, JUMPERS, AND ADJUS'l'MEN'lS (OOMPORBRT
Location Zone
Board Schematic
LIS~IHG)
Description
OL140
02
<105> Bl
BCLK delay adjustment (with OL160)
OL160
02
<105> B1
BCLK delay adjustment (with OL140)
OL200
02
<105> Cl
BCLK delay adjustment (with OL220)
OL220
02
<105> Cl
BCLK delay adjustment (with OL200)
OL240
Bl
<105> E2
ACLOCKIN delay adjustment
OL260
Bl
<105> E2
BCLOCKIN delay adjustment
OL280
Cl
<105> E3
CCLOCKIN delay adjustment
OL300
Cl
<105> E3
OCLOCKIN delay adjustment
J102
F2
<107> CS
Configuration jumper
J202
Fl
<102> BS
Configuration jumper
J204
Fl
<102> B5
Configuration jumper
J206
F1
<102> E2
Configuration j'umper
J208
F1
<102> F2
Configuration jumper
J302
F1
<103> B3
Configuration jumper
J304
Fl
<103> B3
Configuration jumper
J306
F1
<103> B3
Configuration jumper
J308
Fl
<103> B3
Configuration jumper
J310
Fl
<103> B3
Configuration jumper
J3l2
Fl
<103> B3
Configuration jumper
J314
Fl
<103> B3
Configuration jumper
J316
Fl
<103> B3
Configuration jumper
9-8
Reference Information
DAS 9100 Series 91516-91532 Service
Table 9-4 (cont. )
91532 TEST POINTS, JUMPERS, AND ADJUSTMENTS (COMPONENT LISTING)
Component
Location Zone
Board Schematic
Description
J3l8
Fl
<103> B3
Configuration jumper
J320
Fl
<103> B3
Configuration jumper
J322
Fl
<103> B3
Configuration jumper
J324
Fl
<103> B3
Configuration jumper
TP200
El
<102> F3
ACLK to address multiplexer
TP300
Al
<104> F4
Ground reference to DAS
TP320
A3
<104> F4
Ground reference to DAS
TP340
D3
<104> F4
Ground reference to DAS
TP360
El
<104> F4
Ground reference to DAS
TP380
E3
<104> F4
Ground reference to DAS
TP400
Gl
<104> F4
Ground reference to DAS
TP420
G2
<104> F4
Ground reference to DAS
TP500
B2
<105> F2
LCLKO to output latches
TP520
B2
<105> F3
LCLKl to output latches
TP540
B3
<105> F3
LCLK2 to output latches
TP560
B4
<105> F4
LCLK3 to output latches
TP580
Al
<105> F2
ACLKIN probe clock to POD A
TP600
A2
<105> F2
BCLKIN probe clock to POD B
TP620
A3
<105> F3
CCLKIN probe clock to POD C
TP640
A4
<105> F3
DCLKIN probe clock to POD D
TP660
F2
<104> E3
+3 V power supply
TP680
El
<104> Es
+5 V from DAS
9-9
Kererence Information
DAB 9100 Series 91S16-91S32 Service
Table 9-5
91S32 '!'EST POIlft'S, JUMPERS, AND ADJUS'l'MER'rS (SIGNAL LISTING)
Location Zone
Board
Schematic
Description
ACLK to address multiplexer, TP200
El
<102> F3
ACLKIN probe clock to POD A, TPS80
Al
<105> F2
ACLOCKIN delay adjustment, DL240
B1
<105> E2
BCLK delay adjustment, DL140 (with DL160)
D2
<105> Bl
BCLK delay adjustment, DL160 (with DL140)
02
<105> Bl
BCLK delay adjustment, DL200 (with DL220)
02
<105> Cl
BCLK delay adjustment, DL220 (with DL200)
02
<105> Cl
BCLKIN probe clock to POD B, TP600
A2
<105> F2
BCLOCKIN delay adjustment, DL260
Bl
<105> E2
CCLKIN probe clock to POD C, TP620
A3
<105> F3
CCLOCKIN delay adjustment, DL280
Cl
<105> E3
Confiquration jumper, Jl02
F2
<107> C5
Configuration jumper, J202
Fl
<102> BS
Configuration jumper, J204
Fl
<102> BS
Configuration jumper, J206
Fl
<102> E2
Configuration jumper, J208
Fl
<102> F2
Configuration jumper, J302
Fl
<103> B3
Configuration jumper, J304
Fl
<103> B3
Configuration jumper, J306
Fl
<103> B3
Configuration jumper, J308
Fl
<103> B3
Configuration jumper, J3l0
Fl
<103> B3
9-10
Reference Information
DAB 9100 Series 91S16-91S32 Service
Table 9-5 (Cont.)
91S32 TEST POrRTS, JUMPERS, AND ADJUSTMENTS (SIGNAL LISTING)
Location Zone
Board
Schematic
Description
Configuration jumper, J312
F1
<103> B3
Configuration jumper, J314
F1
<103> B3
Configuration jumper, J316
F1
<103> B3
Configuration jumper, J318
F1
<103> B3
Configuration jumper, J320
F1
<103> B3
Configuration jumper, J322
F1
<103> B3
Configuration jumper, J324
F1
<103> B3
DCLKIN probe clock to POD D, TP640
A4
<105> F3
DCLOCKIN delay adjustment, DL300
C1
<105> E3
Ground reference to DAS, TP300
Al
<104> F4
Ground reference to DAS, TP320
A3
<104> F4
Ground reference to DAS, TP340
D3
<104> F4
Ground reference to DAS, TP360
E1
<104> F4
Ground reference to DAS, TP380
E3
<104> F4
Ground reference to DAS, TP400
G1
<104> F4
Ground reference to DAS, TP420
G2
<104> F4
LCLKO to output latches, TPSOO
B2
<105> F2
LCLK1 to output latches, TPS20
B2
<105> F3
LCLK2 to output latches, TPS40
B3
<105> F3
LCLK3 to output latches, TPS60
B4
<105> F4
+3 V power supply, TP660
F2
<104> E3
+5 V from DAS, TP680
E1
<104> ES
9-11
Re~erence Information
DAS 9100 Series 91516-91532 Service
Signal Glossary
The following signal glossaries are arranged in alphanumeric
order. Each entry contains the signal mnemonic, the number of
the schematic(s) where it can be found, and a description of
the signal function. Table 9-6 lists 91516 signals and Table
9-7 lists 91S32 signals.
Table 9-6
91516 SIGNAL GLOSSARY
Signal
Schematic
AO-A12
92
Address from the controller
on the 91S16
ADDR REG RESET (H)
94, 95
Reset for the program
counter
BAO-BA12
92
Address bus from the DAS
Controller
BDO-BD7
92
Data bus to/from the DAS
Controller
BRD(L)
92
Buffered read request from
the DAS
BWR(L)
92
vuffered write request from
the DAS
CHAO-CHA15
98
Positive pattern output to
the P6464 probe at POD A
CHAO-CHA15(L)
98
Negative pattern output to
the P6464 probe at POD A
CHBO-CHB15
98
Positive pattern output to
the P6464 probe at POD B
CHBO-CHB15{L)
98
Negative pattern output to
the P6464 probe at POD B
CLK A(H)
98
Positive clock line to the
P6464 probe at POD A
CLK A(L)
98
Negative clock line to the
P6464 probe at POD A
eLK B(H)
98
Positive clock line to the
P6464 probe at POD B
9-12
Description
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-6 (Cont.)
91S16 SIGNAL GLOSSARY
Signal
Schematic
Description
CLK B (L)
98
Negative clock line to the
P6464 probe at POD B
CLK SENSE(H)
93, 98
Detects a generated clock
CNTL LINE(H)
95
Checks the output of
instruction multiplexer
U406
COUNT OVER (H)
93, 95
Indicates the program
counter has gone to overrun
CSO-CS5(L)
96
Code to select the enabled
memory
DLAO-DLA2
98, 99
Clock delay control for
POD A
DLBO-DLB2
98, 99
Clock delay control for
POD B
EDO-ED7
96
Data line to the memory
EXAO-EXA9
96
Address lines to the 91S32
EXT CLK (H)
93
External positive clock
from the P6460 probe
EXT CLOCK(L)
93
External negative clock
from the P6460 probe
EXT JUMP POL (H)
93, 99
External signal polarity
for the IF EXT JUMP
instruction
EXT JUMP SET (H)
93, 99
Sets the IF EXT JUMP
instruction to false
EXT JUMP(H)
93
External signal for IF EXT
JUMP instruction from the
P6460 probe
EXT JUMP(L)
93
External negative signal
for IF EXT JUMP instruction
from the P6460 probe
F INH A,B(H)
96, 97
Internal inhibit signal to
the first latch
9-13
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-6 (Cant.)
91S16 SIGNAL GLOSSARY
Signal
Schematic
Description
F LATCH eLK (H)
93, 99
Clock to the first latch
F LATCH STEP CLOCK(H)
92, 99
Clock for loading the
pattern to the first latch
FULL RESET(L)
94
Indicates that the IF FULL
JUMP instruction has been
executed
FULL (H)
94
Page change request signal
to the 91S32
HOLD/COUNT (H)
94, 95
Hold signal for the stack
IBA, IBB (H)
98
Internal inhibit signals to
the last latch
IF ENDO (L)
94, 99
Indicates that KEY 47 has
been received through GPIB
IF ENDI(L)
94, 95
Status for the IF END JUMP
INSTRUCTION
IF EXT(L)
93, 95
Latched status for the IF
EXT JUMP instruction
IF FULL (L)
94
IF IRQ(L)
94, 95
Latched status for the IF
IRQ JUMP instruction
IF KEY (L)
94, 95
Status for the IF KEY JUMP
instruction
IF R=O (L)
95, 97
Checks whether the output
of the 16-bit register is 0
IF RA=O(L}
95, 97
Checks whether the output
of 8-bit register RA is 0
IF RB=O (L)
95, 97
Checks whether the output
of 8-bit register RB is 0
IF RESET(L)
95, 97
Disable reset signal for
several instructions
INH 2 OR/AND (H)
96, 99
Inhibit control
<}s
9-14
for the IF FULL JUMP
instruction
~tatus
Reference Information
DAB 9100 Series 91516-91532 Service
Table 9-6 (Cont.)
91516 SIGNAL GLOSSARY
Signal
Schematic
Description
INHIBIT A, B(H)
98, 99
Internal inhibit signal to
POD A or B
INHIBIT(H)
99
Positive external inhibit
signal from the P6460 probe
INHIBIT(L)
99
Negative external inhibit
signal line from the P6460
probe
INT INHIBIT DIS (H)
99
Internal inhibit disable
INT POL (H)
94, 99
Polarity for an interrupt
signal
INT RESET(H)
94, 99
Resets the latch for an
interrupt signal
INT RESET(L}
94, 95
Stack hold signal given by
receiving an interrupt
signal
INT SET (H)
94, 99
Sets the latch for an
interrupt signal
INTERRUPT(L)
94
Negative interrupt signal
line from the P6460 probe
INTERRUPT: (H)
94
Positive interrupt signal
line from the P6460 probe
IRQ RESET(L)
94, 99
Indicates that the IF IRQ
JUMP instruction has been
executed
JAO-JA9
95
Address loaded to the
program counter
JABO-JAB9
95, 96,
100
Destination for the JUMP
instruction
KA RESET(H)
93, 94
Resets the latch for CALL
RMT instruction
KA(L)
93, 95
Indicates that the CALL RMT
instruction has been
executed
9-15
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-6 (Cont.)
91S16 SIGNAL GLOSSARY
Signal
Schematic
Description
KEY CLK (H)
94, 99
Generated if a key is pressed
while the program is running,
used as a latch clock
KEY RESET (L)
95
Indicates that the IF KEY
JUMP instruction has been
executed
L
94
Resets the latch for the IF
FULL JUMP and the IF KEY JUMP
instruction
LOAD CLOCK (H)
94, 99
Used as the page-change
signal to the 91532,
generated when the command
KEY 46 is received from the
GPIB
MAIN CLOCK
93
Clock source for the 91532
MCO-MCI
100
Selects either the pattern or
the output of a register as
the output to the probe
MClO-MCll
97
Control for register RB
MC12-MC13
97
Control for register RA
MC16 (H)
96, 98
Triggers data from the
microcode memory
MC17 (H)
94
Mask signal for an interrupt
MC2-MC3
100
Strobe signal line
MC4-MC5
96, 97
Internal inhibit signal line
MC6-MC9
95
Flow control instruction
OUT CLK
93, 99
Main clock to the output
system
OUT CLK (L)
93, 97, 99
Clock to the register
&
K RESET (H)
9-16
Reference Information
DAB 9100 Series 91S16-91S32 Service
Table 9-6 (Cont.)
91S16 SIGNAL GLOSSARY
Signal
Schematic
Description
OUT CLOCK 0 (L)
92, 93
Clock to the output system
OUT LATCH CLK
98, 99
Clock line to the last
latches
CLK A(L)
92
Clock to the P6464 probe at
POD A
P CLK B (L)
92
Clock to the P6464 probe at
POD B
P CLK C (L)
92
Clock to the P6464 probe at
POD C
P INHIBIT A, B(H)
99
Inhibit signal to the P6464
probe
PAGE (H)
96
Page change request signal
to the 91S32
PAUSE ON/OFF(H)
93,
PAUSE POL (H)
93
Selects the PAUSE polarity
PAUSE (H)
93
Pause line from the P6460
probe
PAUSE(L)
93
Inverse pause line from the
P6460 probe
PC CLK 0 (L)
92
Clock for incrementing the
program counter
PC CLK
93, 95
Clock to the program
counter
PC INCR(H)
95, 99
Sets the program counter to
an incremental mode
PC RESET(L)
92, 94
Reset pulse for the program
counter
PC SET (H)
95, 99
Clock hold signal for
starting the pattern
generator
PCO-PC9
95, 96,
100
Output of the program
counter
P
99
9-17
Turns the PAUSE signal on
or off
Kererence Information
DAS 9100 Series 91S16-91S32 Service
Table 9-6 (Cont.)
91S16 SIGNAL GLOSSARY
Signal
Schematic
Description
PERSONALITY (H)
92
A memory map output from
the DAS Controller that
selects the personality
ROMs
PGND SENSE(H)
94
The ground level fed back
from an input probe
POD A, B, C DATA
92
Data line to the P6464
probe at POD A, B, or C
POD A, B, C READ (H)
92
Set the P6464 at POD A, B,
or C to the read mode
POD A, B, C WRITE(H)
92
Set the P6464 at POD A, B,
or C to the write mode
POFFSET SENSE(H)
94
Feeds back the offset
level from an input probe
PORT(L)
92
Indicates when the slotselect logic is to write
data to the selected
module
PROBE DATA CLOCK(L)
92
Clock for loading the data
into the probe
PROBE R/W (L)
92
Sets probes to the
read/write mode
PROBE W DATA(L)
92
Loads the latch with the
probe data
QUAL OFF/ON(H}
99
Turns the qualify signal
line off or on
QUAL POL (H)
94, 99
Polarity for the qualify
signal
QUALIFY (H)
94
Positive qualify signal
line from the P6460 probe
9-18
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-6 (Cont.)
91S16 SIGNAL GLOSSARY
Signal
Schematic
Description
QUALIFY(L)
94
Negative qualify signal
line from the P6460 probe
R CLK
93, 94
Main clock to the external
signal input system
RAO-RA7
97
The output of register A
RABO-RAB9
95
Return address from the
stack
RAM WE(L)
92, 96
Generates a write pulse
for the RAM
RBO-RB7
97
The output of register B
READ 0 (E)
93, 95
Selects the readback gate
for the current status
READ l-READ 8
100
Selects the desired read
status
READ SEL(L)
92, 100
Selects a port for reading
the status
READ STATUS GATE(L)
92
Enables a gate for reading
the status
REG CLK OFF/ON
97, 99
Turns the clock gate to
the registers off or on
RESET CLK(E)
93, 95
Clock for resetting the
latch which is used as the
start setup
RESET CLK(L)
92
Resets the latch for the
start setup
RETURN (E)
94, 95
Indicates that the RETURN
instruction has been
executed
RS CLK 0
93
Clock pulse for the
external signal latch
9-19
Reterence Information
DAS 9100 Series 91S16-91S32 Service
Table 9-6 (Cont.)
91S16 SIGNAL GLOSSARY
Signal
Schematic
S16 CLK
93
Positive clock line to the
91532
S16 CLK (L)
93
Negative clock line to the
9lS32
S16 INHIBIT(L)
99
Inhibits the signal line
to the 91532
SCLK
93, 94
Clock source for the
system
SEL 0 (L)
92, 99
Loads data to latch U804
SEL 1 (L)
92, 99
Loads data to latch U806
SEL 2 (L)
92, 99
Loads data to latch U808
SEL 3 (L)
92, 99
Loads data to latch U8l0
SEL 4 (L)
92, 99
Loads data to latch U8l2
SEL s(L)
92, 99
Loads data to latch U8l4
SEL 8/16 E (H)
99
Selects two 8-bit
registers or one l6-bit
register
SEL RAM(L)
92, 96
SEL SLOT(L)
92
Selects the RAM to be read
from or written to
Indication from the DAS
Controller slot-select
logic as to which
personality ROM is being
read
SET OUT 0, 1 (H)
97
Selects the output latch
to the probe
SPCO-SPC9
96
Address to the pattern and
microcode memory
SRDO-SRD7
93, 95,
100
Reads back the selected
status signal
9-20
Description
Reference Information
DAS 9100 Series 91516-91532 Service
Table 9-6 (Cont.)
91516 SIGNAL GLOSSARY
Signal
Schematic
Description
STACK RESET (H)
92, 95
Clears the content of the
stack
START CONTROL l(H}
93, 95
Setup signal used at
pattern-generator start
START CONTROL 2(H}
95, 97
Controls a clock for the
register at startup
START IN (H)
93
External trigger signal
for starting the pattern
generator
START SET (H)
94, 99
Setup signal for starting
the system
STB A, B
98, 99
Strobe A or B
STEP CLK(L}
92, 93
A step clock for the
system
STOP PG(H)
93
Start/stop control signal
from the controller
STOP/START
93, 99
Controls the start/stop
control signal
TDO-TD7
92, 94, 96,
99, 100
Data on the 9lSl6 data
bus
THRESHOLD (L)
92
Threshold voltage control
for the P6460 external
signal probe
TRIG IN RESET (H)
99
Resets the stop/start
control latch
TRIG IN SET (H)
99
Sets the stop/start
control latch
TRIGGER CLK
98, ·99
Clock line for the trigger
output
TRIGGER POL (H)
93, 99
Sets polarity of the
external start signal
9-21
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-6 (Cont.)
91S16 SIGNAL GLOSSARY
Signal
Schematic
Description
TRIGGER(H)
98
Trigger signal output
VO-VlS
97
Pattern output from the
pattern selector to the
first latch
VBO-VBlS
97, 98,
100
Pattern from the first
latches to the last
latches
VMBO-VMBlS
96, 97
Pattern generated from the
memory
VTHRESH SENSE(E)
94
Feeds back the threshold
level from an input source
VTHRESHOLD
94
Threshold for an input
probe
9lAOS INTL (E)
92
9lAOS clock from the
Trigger/Time Base
9lA08 INTL (L)
93
9lA08 negative clock from
the Trigger/Time Base
9lA32 INTL (L)
93
9lA32 clock
9lS32 CLK 0, 1, 2(H)
93, 99
Control clocks to the
91S32
9lS32 CLK RESET (H)
93, 99
Sets the polarity of the
S16 clock signal
9-22
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-7
91S32 SIGNAL GLOSSARY
Signal
Schematic
Description
AO-A12
101, 102
Internal address bus
ACLK (H)
101, 102
Clocks the vector
generation counter to
count up or load the
address data
ACLOCKIN (H)
105
High-speed clock output
for POD A P6464 probe
ADATACLK
105
The clock for the POD A
P6464 probe setup data
AlC (L)
101, 102
Trace/step clock control,
controls the clock from
the MPU when the
trace/step mode is
selected
BAO-BA12
101
Buffered address from the
DAS Controller
BCLK (H)
102, 105
Clocks the last data latch
BCLOCKlN(H)
105
High-speed clock output
for POD B P6464 probe
BDO-BD7
101, 102,
106
Buffered address from DAS
Controller
BDATACLK
105
The clock for the POD B
P6464 probe setup data
BRD (L)
101
Buffered read request from
the DAS Controller
BRW(L)
101
Buffered write request
from the DAS Controller
9-23
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-7 (Cont.)
91S32 SIGNAL GLOSSARY
Signal
Schematic
CARD ID(L)
102
Card identification signal
which enables card ID
buffer U122
CCLK (H)
and
102, 103,
Clocks the loop counter
104
the page latch
CCLOCKIN (H)
105
High-speed clock output
for POD C P6464 probe
CCLOCKIN (L)
105
Inverse line for
CCLOCK IN ( H)
CDATACLK
105
The clock for the POD C
P6464 probe setup data
CEO-CHS
106, 107
Two-line, high-speed data
for the P6464 probe
DASINHC(L)
101, 107
DAS inhibit control which
enables the inhibit signal
from the DAS Controller
DATA CLK
101, 105
Clock for the P6464 probe
setup data
DATA OUTA
101
Setup data input/output
line for the POD A P6464
probe
DATA OUTB
101
Setup data input/output
line for the POD B P6464
probe
DATA OUTC
101
Setup data input/output
line for the POD C P6464
probe
DATA OUTD
101
Setup data input/output
line for the POD D P6464
probe
DATA
101, 105
Probe data A (same as DATA
OUTA)
9-24
Description
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-7 (Cont.)
91S32 SIGNAL GLOSSARY
Signal
Schematic
DATB
101, 105
Probe data B (same as DATA
OUTB)
DATC
101, 105
Probe data C (same as DATA
OUTC)
DATD
101, 105
Probe data D (same as DATA
OUTD)
DCLK
102, 103
Clock for the page flipflop
DCLOCKIN(H)
105
High-speed clock output
for POD D P6464 probe
DCLOCKIN (L)
105
Inverse line for
DCLOCKIN(H}
DDATACLK
101, 105
The clock for the POD D
P6464 probe setup data
EXAO-EXA9
103
Address from the 91Sl6
EXT GATE
101, 107
Controls external inhibit
signal from 9lSl6 or DAS
Controller
EXT INH(H)
101, 106,
107
External inhibit control
from DAS data word, USED
when internal inhibit is
not used
FREE/PAGE
103
Selects the sequential
mode or follows the 91Sl6
mode
FULL(H)
103
Page-full signal from the
9lSl6 when the 91Sl6 is in
the CALL REMOTE mode and
the 91S32 vector memory is
reloaded
HALFCR
102, 103
Main clock divided by two
9-25
Description
Reference Information
DAS 9100 Series 91516-91532 Service
Table 9-7 (Cont.)
91S32 SIGNAL GLOSSARY
Signal
Schematic
ICIC (L)
102, 105
Internal clock input
control which enables the
internal clock input gate
ICLK (H)
102
Internal clock used
between multiple 9lS32s
ICLK (L)
102
Inverse line for ICLK(H)
ICOC(L)
102, 103
Internal clock output
control which enables the
intern~l clock output
IDO-ID7
101, 104,
106, 107
Internal data bus 0-7
which supplies ECL-level
MPU bus
INHIBIT(H)
106, 107
Inhibits P6464 probe
output
INHIBIT(L)
106, 107
Inverse line for
INHIBIT (H)
INPOL(H)
101, 106,
107
Same as EXTINH{H)
INTGATE(H)
107
Internal inhibit gate
which disables the
internal inhibit signal
KEEP (L)
101, 102
Keep-alive signal which
enables the keep-alivemode clock when the 9lS32
follows the 9lSl6
LCLKO
105, 106
Last clock 0, clocks the
POD A last latch
9-26
Description
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-7 (Cont.)
91S32 SIGNAL GLOSSARY
Signal
Schematic
LCLKl
105, 106
Last clock 1, clocks the
POD B last latch
LCLK2
105, 106
Last clock 2, clocks the
POD C last latch
LCLK3
105, 106
Last clock 3, clocks the
POD D last latch
LOOP COUNT ( L)
103, 104
Enables the loop counter
to count up
LSTOPM(L)
103, 104
Loop-stop monitor, goes
low when the loop counter
stops
MASKT(L)
101, 104
Mask trigger, enables the
trigger-start signal
MODEA(L)
103, 104
Selects the A-page memory
MODEB(L)
103, 104
Selects the B-page memory
MPUCLK
101, 102
Clock line from the
processor
MPUCLKCTRL(L)
101, 102
Enables the MPU clock line
MRD(L)
101, 102
Memory read, instructs the
controller microprocessor
to read the data bus
MWRM(L)
101, 104
Memory write mode, enables
data,to be written to the
vector memory
PA 0
105
Probe A delay 0, sets
probe A POD delay to 0 ns
PA 5
105
Probe A delay 5, sets
probe A POD delay to +5 ns
PA-5
105
Probe A delay -5, sets
probe A POD delay to -5 ns
PAGA
101, 103
Sets the page latch to
page A
9-27
Description
AeLerence Inrormation
DAS 9100 Series 91516-91532 Service
Table 9-7 (Cont.)
91532 SIGNAL GLOSSARY
Description
Signal
Schematic
PAGB
101, 103
Sets the page latch to
page B
PAGE (H)
103
Page change signal from
the 91516, changes the
page-latch output
PAUSE (H)
101, 102
Enables the external pause
signal
PB 0
105
Probe B delay 0, sets
probe B POD delay to 0 ns
PB 5
105
Probe B delay 5, sets
probe B POD delay to +5 ns
PB-5
105
Probe B delay -5, sets
probe B POD delay to
-5 ns
PC 0
105
Probe C delay 0, sets
probe C POD delay to 0 ns
PC 5
105
Probe C delay 5, sets
probe C POD delay to +5 ns
PC-5
105
Probe C delay -5, sets
probe C POD delay to
-5 ns
PD 0
105
Probe D delay 0, sets
probe D POD delay to 0 ns
PO 5
105
Probe D delay 5, sets
probe D POD delay to +5 ns
PD-5
105
Probe D delay -5, sets
probe D POD delay to
-5 ns
PERSONALITY (L)
101
Memory map from the DAS
that selects the
personality ROMs
PG EXT CLK CTRL(H)
101, 102
Enables the PG EXT CLK(L)
input
9-28
Reference Information
DAS 9100 Series 91516-91532 Service
Table 9-7 (Cont. )
91532 SIGNAL GLOSSARY
Signal
Schematic
PG EXT
Description
eLK (L)
102
External clock input from
the DAS
PG EXT INT (H)
104
External interrupt from
the DAS
PG EXT PAUSE (H)
102
External pause input from
the DAS
PGND
106, 107
Ground for the P6464
probes
PODA INH
106, 107
Inhibit signal for POD A
PODB INH
106, 107
Inhibit signal for POD B
PORT
o (L)
101, 102
Port 0 write, writes to
U206
PORT 2 (L)
101, 105
Port 2 write, writes to
U516
PORT 3 (L)
101, 105
Port 3 write, writes to
U520
PORT 9 (L)
101, 103
Port 9 write, writes to
U302
PORTIO
(L)
101, 103
Port 10 write, writes to
U314
PORTll (L)
101, 105
Port 11 write, writes to
U512
PORT12 (L)
101, 105
Port 12 write, writes to
U514
PORT13
101
Port 13 write, writes to
U728
103
Programmed start, start
address data of the vector
counter
(L)
PSO-PS9
9-29
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-7 (Cont.)
91S32 SIGNAL GLOSSARY
Signal
Schematic
PSTART CH)
101, 104
Pre-start, sets the loop
counter start latch
RAO-RA9
103
Buffered address data from
the 91S16
RAOA-RA9A
103, 106
Memory address for A-page
memory
RAOB-RA9B
103, 107
Memory address for B-page
memory
RBO-RBg
106
Extender address from
91516
ROO-R06
101, 103,
106
Enables one of the readback blocks
ROB (L)
101, 106
Readback, enables data on
the bus to be read
S16 CLK (H)
102
Clock from the 91S16
S16 CLK(L)
102
Inverse line for S16
CLK (H)
S16INHC
101, 107
Inhibit control, disables
the inhibit signal from
the 91S16
S16INHIBIT(L)
107
Inhibit input from the
91S16
SELINH
102, 103
The selected inhibit
signal
SR4-SR10
103
Start register data, the
original address of the
vector counter
9-30
Description
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-7 (Cont.)
91S32 SIGNAL GLOSSARY
Signal
Schematic
START (H)
101, 104
Sets the 91S32 start flipflop
START/STOP
103, 104
Goes high when the 9lS32
starts
STOP (H)
101, 104
Resets the 91S32 start
flip-flop
STOP/START
103, 104
Inverse line for
START/STOP
STOPGATE (L)
102, 105
Enables the 91S32 clock
path
SYSCLK (L)
102, 105
System clock, enables the
9lS16 clock gate when the
9lS32 runs in the
sequential mode
T/B OFF/ON
102, 104
Time base off/on control,
controls the selected
clock from the DAS
Trigger/Time Base
VMBO-VMB39
106, 107
Vector memory bus, data
from the memory to the
output latch
WAO-WA4
104, 106
Write enable for the Apage 0-4 block memory
WBO-WB4
104, 107
Write enable for the Bpage 0-4 block memory
9-31
Description
Reference Information
DAS 9100 Series 91S16-91S32 Service
Table 9-7 (Cont.)
91832 SIGNAL GLOSSARY
Signal
Schematic
WEA(L)
101, 104,
106
Write enable for the Apage memory
WEB (L)
101, 104,
107
Write enable for the Bpage memory
WP(L)
101, 104
Write port, loads memory
write block data
9lA08 INTL CLK{L)
102
9lA08 negative clock from
the DAS Trigger/Time Base
9lA08 CLK CTRL(L)
101, 102
9lA08 clock control,
enables the 9lA08 clock
9lA32 INTL CLK(L)
102
9lA32 negative clock from
the DAS Trigger/Time Base
9lA32 CLK CTRL (L)
101, 102
9lA32 clock control,
enables the 9lA32 clock
9-32
Description
Section 10-91S16,91S32
REPLACEABLE
ELECTRICAL PARTS
PARTS ORDERING INFORMATION
Replacement parts are available from or through your local
Tektronix. Inc. Field Office or representative.
Changes to Tektronix instruments are sometimes made to
accommodate improved components as they become available,
and to give you the benefit of the latest circuit improvements
developed in our engineering department. It is therefore important. when ordering parts. to include the following information in
your order: Part number. instrument type or number, serial
number. and modification number if applicable.
If a part you have ordered has been replaced with a new or
improved part. your local Tektronix. Inc. Field Office or representative will contact you concerning any change in part number.
Only the circuit number will appear on the diagrams and
circuit board illustrations. Each diagram and circuit board
illustration is clearly marked with the assembly number.
Assembly numbers are also marked on the mechanical exploded
views located in the Mechanical Parts List. The component
number is obtained by adding the assembly number prefix to the
circuit number.
The Electrical Parts List is divided and arranged by
assemblies in numerical sequence (e.g .. assembly A1 with its
subassemblies and parts, precedes assembly A2 with its subassemblies and parts).
Chassis-mounted parts have no assembly number prefix
and are located at the end of the Electrical Parts List.
Change information. if any, is located at the rear of this
manual.
TEKTRONIX PART NO. (column two of the
Electrical Parts List)
LIST OF ASSEMBLIES
A list of assemblies can be found at the beginning of the
Electrical Parts List. The assemblies are listed in numerical order.
When the complete component number of a part is known, this list
will identify the assembly'in which the part is located.
Indicates part number to be used when ordering replacement part from Tektronix.
CROSS INDEX-MFR. CODE NUMBER TO
MANUFACTURER
SERIAL/MODEL NO. (columns three and four
of the Electrical Parts List)
The Mfr. Code Number to Manufacturer index for the
Electrical Parts List is located immediately after this page. The
Cross Index provides codes, names and addresses of manufacturers of components listed in the Electrical Parts List.
Column three (3) indicates the serial number at which the
part was first used. Column four (4) indicates the serial number at
which the part was removed. No serial number entered indicates
part is good for all serial numbers.
ABBREVIATIONS
Abbreviations conform to American National Standard Y1.1,
COMPONENT NUMBER (column one of the
Electrical Parts List)
A numbering method has been used to identify assemblies,
subassemblies and parts. Examples of this numbering method
and typical expansions are illustrated by the following:
Example
------
NAME & DESCRIPTION (column five of the
Electrical Parts List)
In the Parts List, an Item Name is separated from the
description by a colon (:). Because of space limitations. an Item
Name may sometimes appear as incomplete. For further Item
Name identification, the U.S. Federal Cataloging Handbook HS-1
can be utilized where possible.
component number
8.
A23R1234
Assembly number
A23
R1234
~ ~ Circuit number
MFR. CODE (column six of the Electrical Parts
List)
Indicates the code number of the actual manufacturer of the
part. (Code to name and address cross reference can be found
immediately after this page.)
Read: Resistor 1234 of Assembly 23
component number
Example b,
r
.A.
"
A23A2R1234
A23
A2
R1234
Assembly
~ Subassembly
Circuit
number
number
number ~
L-
Read: Resistor 1234 of Subassembly 2 of Assembly 23
MFR. PART NUMBER (column seven of the
Electrical Parts List)
Indicates actual manufacturers part number.
10-1
Replaceable Electrical Parts - 91516,91532
CROSS INDEX Mfr.
Code
01121
01295
04222
04713
MFA.
Manufacturer
Address
City. State. ZIP Code
allEN-8RADlEY co
TEXAS INSTRUMENTS INC
SEMICONOUCTOR GROUP
avx CERAMICS DIY Of AVX CORP
1201 SOUTH 2ND ST
MILKQUKEE WI 53204
DALLAS TX 75265
54583
55680
57668
71744
75915
76493
MOTOROLA INC
SEMICONOUCTOR GROUP
UNION CARBIDE CORP MATERIALS SYSTEMS
DIY
GENERAL INSTRUMENT CORP
GOVERNMENT SYSTEMS OIY
fAIRCHILD CAMERA nNO INSTRUMENT CORP
SEMICONDUCTOR OIV
TRW INC
TRW ELECTRONICS COMPONENTS
TRIj IRC fIXED RESISTORS/BURLINGTON
CTS Of BERNE INC
CRYSTEk CRYSTALS CORP
SIGNETICS CORP
MEPCO/ElECTRA INC
A NORTH AMERICAN PHILIPS CO
OU PONT E I OE NEMOURS nNO CO INC
OU PONT CONNECTOR SYSTEMS
UNION CARBIOE CORP
ELECTRONICS OIY
PLESSEY INC
PLESSEY OPTOELECTRONICS AND
MICROWAYE
TOk ELECTRONICS CORP
NICHICON IAMERICAI CORP
ROHM CORP
GENERAL INSTRUMENT CORP LAMP DIY
LITTELfUSE INC
BELL INDUSTRIES INC MILLER J " DIY
80009
TEKTRONIX INC
82389
SWlTCHCRAfT INC
SUB Of RAYTHEON CO
DALE ELECTRONICS INC
05397
05828
07263
07716
11236
13454
18324
19701
22526
31433
52648
91637
10-2
CODE NUMBER TO MANUFACTURER
13500 N CENTRAL EXPRESSWAY
P 0 SOX 225012 MIS 49
19TH AVE SOUTH
POBOX B67
5005 E MCDOWELL RD
MYRTLE BEACH SC 29577
PHOENIX AZ 85008
11901 MADISON AYE
CLEVEUINO OH 44101
600 " JOHN ST
HICKSVILLE NY 11802
464 ELLIS ST
MOUNTAIN VI(H CA 94042
2850 MT PL€llSIINT AVE
BURLINGTON IA 52601
406 PARR ROAO
1000 CRYSTAL OR
B11 E ARQUES
POBOX 760
BERNE IN 46711
fT MYERS FL 33901
SUNNYVALE CA 94086
MINERAL WELLS TX 76067
30 HUNTER LANE
CAMP HILL PA 17011
PO BOX 592B
GREENVILLE SC 29606
1641 KAISER AYE
IRVINE CA 92714
755 EASTGATE BLVD
927 ESTATE PKY
16931 MIllIKEN AYE
4433 N RAVENSWOOD AYE
800 E NORTHWEST HWY
19070 REYES AVE
POBOX 5825
4900 S I( GRlfF!TH OR
POBOX SOO
5555 N ELSTRON AVE
GAROEN CITY NY 11530
SCHAUMBURG IL 60195
IRVINE CA 92713
CHICAGO IL 60640
DES PLAINES IL 60016
COMPTON CA 90224
POBOX 609
8EAVERTON OR 97077
CHICAGO IL 60630
COLUMBUS NE 68601
Replaceable Electrical Parts - 91516,91532
Comegnent No.
Tektronix
Part No,
Serial/Assembly No.
Effective
Dscont
Mfr.
Code
Mfr. Part No.
CIRCUIT BO A55Y:PATT GEM NODULE
(91516 ONLY)
CIRCUIT BO 1155Y:PATT GEM NODULE
(91532 ONLY)
CIRCUIT BO 1155Y:MIIIN
(P6464 ONLY)
CIRCUIT BO 1155Y:MAIN
(P6464 ONLY)
CIRCUIT BD AS5Y:3V PNR 5PLY
(P6464 ONLY)
BOOO9
670-8810-00
BOO09
670-8811-00
B0009
670-S742-00
BOO09
670-S742-01
BOO09
670-88OS-00
80009
670-8810-00
04222
04222
04222
04222
04222
MA20SE1 04MAA
MA105E104MAA
MA20SE104MAA
MA10SE1 O4MAA
MA20SE1 O4MAA
Name & Descrietion
1134
670-8810-00
113S
670-8811-00
1136
670-B742-OO B010100
1136
670-S742-o1 B010674
1137
670-8808-00
1134
670-8810-00
1134(106
1134C10S
1134(110
1134(112
1134C114
281-077S-OO
281-077S-OO
281-077S-00
281-o77S-00
281-o77S-00
CIRCUIT BD 115SY:PATT GEM NODULE
(91516 ONLY)
CAP ,FXD,(ER 01 :0.1UF ,201,5OV
CAP,FXD,CER 01:0.1UF,201,5OV
CAP,FXO,(ER 01:0.1UF,201,5OV
CIIP,FXO,CER OI:0.1UF,201,5OV
CAP,FXD,CER 01:0.1UF,201,5OV
1134C116
1134C118
1134(120
1134C122
1134C124
1134C126
281-o77S-00
281-0775-00
281-o77S-00
281-0775-00
281-o77S-00
281-o77S-00
CAP,FXO,CER
CIIP,FXO,CER
CAP ,FXO,CER
CAP,FXO,CER
CIIP,FXO,CER
CAP ,FXO,CER
01:0.1UF,201,5OV
01:0.1UF,201,5OV
01 :0.1UF ,201,5OV
01:0.1UF,201,5OV
01:0.1Uf,201,5OV
01 :0.1UF ,201,5OV
04222
04222
04222
04222
04222
04222
MA2OSE104MAA
1411205E104MAA
141120SE104MAA
MAZOSE104MAA
141120SE1 04MAA
MA105E104MAA
A34C128
1134C200
1134C204
1134C208
1134C212
1134C216
281-0775-00
281-o77S-00
281-0775-00
281-o77S-00
281-o77S-00
281-o77S-00
CAP,FXO,CER
CIIP,FXD,CER
CIIP,FXD,CER
CIIP,FXO,CER
CIIP,FXO,CER
CIIP,fXO,CER
OI:0.1UF,201,5OV
Or:0.1UF,201,5OV
01:0.1UF,201,5OV
OI:0.1UF,201,5OV
01:0.1UF,201,5OV
Or:0.1UF,201,5OV
04222
04222
04222
04222
04222
04222
MII2OSE104MAA
MA20SE104MAII
MA20SE104MA1I
MA2OSE104M1I1I
MA10SE104MAII
MA20SE1 O4MA1I
1134C22O
1134C222
1134C228
A34C258
A34C264
1134C322
281-o77S-00
281-o77S-00
281-o77S-00
281-077S-00
281-077S-00
119-1762-00
CAP,fXO,CER OI:0.1UF,201,5OV
CAP,FXO,CER 01:0.1UF,201,5OV
CIIP,FXO,CER 01:0.1UF,201,5OV
CAP,FXO,(ER 01:0.1UF,201,5OV
CIIP,FXO,CER 01:0.1UF,201,5OV
FILTER,Rfl:22000PF,5OV "ITH FERRITE BEAD
04222
04222
04222
04222
04222
BOO09
MA20SE104MAA
MA1OSE104MIIlI
MA2OSE104MIIII
MA2OSE104MAA
MA20SE104MAA
119-1762-00
1134C330
1I34C342
1134C346
A34C360
1134(370
1134C3n
119-1762-00
281-077S-00
281-0775-00
281-o77S-00
281-0792-00
281-0775-00
FILTER,RFI:22DooPF,5OV "ITM FERRITE BEllO
CAP ,FXO,CER 01 :0.1UF ,201,50V
CAP,FXO,CER 01:0.1UF,201,5OV
CAP,FXO,CER 01:0.1UF,201,50V
CAP ,fXO,CER 01 :82PF ,101,1OOV
CAP,FXO,(ER 01:0.1UF,201,5OV
SOO09
04222
04222
04222
04222
04222
119-1762-00
141120SE104l4AlI
MII20SE104MAA
MA20SE104MA1I
MA101A820KAII
MAZOSE1 O4MAA
1134C374
1134C376
1134(378
1134(380
1134(382
1134C384
283-0059-00
283-o0S9-o0
281-0813-00
281-0773-00
281-0773-00
281-om-oO
CAP ,FXIl,CER
CAP,fXD,(ER
CAP ,FXO,CER
CAP,fXO,CER
CAP,fXO,CER
CAP,FXO,CER
31433
31433
05397
04222
04222
04222
C330C105MSR5CA
C330C105MSR5CA
C412C4731015V2(A
MA201C103ICAA
MII201C103ICAA
MA201C103ICAA
1134(386
1134C388
1134C390
1134C394
1134C396
1134C398
281-0813-00
281-0813-00
281-0773-00
283-OOS9-00
283-OOS9-00
119-1762-00
CAP,FXO,CER 01:0.047UF,201,5OV
(AP,FXO,CER 01:0.047UF,201,5OV
CIIP,FXO,CER OJ:0.01UF,101,100V
CAP,FXO,CER 01:1UF,+80-201,5OV
CAP ,FXO,CER OJ :1UF, +80-201,5OV
FILTER,RFI:22DooPF,50V "ITH FERRITE BEAD
05397
05397
04222
31433
31433
80009
C412C473MSV2CA
C412C473M5V2CA
MII201C1031(IIA
C330C105M5RSCA
C330C105MSRSCA
119-1762-00
1134C500
1134C502
1134C504
1134C506
1134C508
1134C510
290-1014-00
290-1014-00
290-1014-00
290-1014-00
290-1014-00
290-1014-00
CAP,FXO,EL(TLT:1UF,35V
CAP,FXO,ELCTLT:1UF,35V
CAP,FXO,ELCTLT:1UF,35V
CIIP,FXO,ELCTLT:1UF,35V
CIIP,FXO,ELCTLT:1UF,3SV
CliP ,FXD,ELCTLT: 1UF,35V
SOO09
80009
B0009
80009
B0009
290-1014-00
290-1014-00
290-1014-00
290-1014-00
290-1014-00
290-1014-00
8010673
01 :1UF, +80-201,5OV
01:1UF,+SO-201,5OV
OJ :0.047UF ,201,5OV
01:0.01UF,101,100V
01:0.01UF,101,100V
OI:0.01UF,101,100V
80009
10-
Replaceable Electrical Parts - 91516,91532
ComQQnent No.
Tektronix
Part No.
A34C512
A34C514
A34(516
A34C518
A34C520
A34C522
290-1014-00
290-1014-00
290-1014-00
290-1014-00
290-1014-00
290-1014-00
A34C524
A34C526
A34C570
A34C574
A34C578
A34C602
290-1014-00
290-1014-00
290-1014-00
290-1014-00
290-1014-00
281-0775-00
A34C606
A34C610
A34C614
A34C618
A34C622
A34C626
Serial/Assembly No.
Effective
Dscont
Mfr.
Code
Mfr. Part No.
CAP,txO,ELCTLT:1Uf,35V
CAP,txD,ELCTLT:1Uf,35V
CAP,txD,ELCTLT:1Uf,35V
CAP ,fXO .ELCTLT: 1Uf ,35V
CAP,txO,ElCTlT:1Uf,35V
CAP,fXO,ELCTlT:1UF,35V
SOO09
80009
80009
SOO09
80009
SOO09
290-1014-00
290-1014-00
290-1014-00
290-1014-00
290-1014-00
290-1014-00
CAP,txD,ELCTlT:1Uf,3~V
CAP,txD,ElCTlT:1UF,35V
CAP,txD,ELCTlT:1UF,3&V
CAP ,txD ,ElCTlT: 1Uf ,35V
CAP,txD,ElCTlT:1UF,35V
CAP,txD,CER OI:0.1UF,201.SOV
SOO09
80009
!lU009
80009
80009
04222
290-1014-00
290-1014-00
290-1014-00
290-1014-00
290-1014-00
14A205E1 04MtlA
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
CAP,fXD,CER
CAP,txO,CER
CAP,txD,CER
CAP,txD,CER
CAP,txO,CER
CAP,txO,CER
OI:0.1UF,201,SOV
DI:0.1Uf,201,SOV
DI:O.1UF,201,SOV
DI:0.1UF,201,SOV
DI:0.1UF,201,50V
DI:0.1Uf,201,SOV
04222
04222
04222
04222
04222
04222
14A205E1041011\A
14A205E104MAA
I4A205E104MAA
I4A205E104141\A
14A205E104MtlA
14A205E104MnA
A34C630
A34C634
A34C638
A34C662
A34C666
A34C670
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
CAP,txO,CER
CAP,txD,CER
CAP,txO,CER
CAP,txD,CER
CAP,txO,CER
CAP,txO,CER
DI:0.1UF,2Dl,50V
DI:0.1UF,201,SOV
DI:0.1UF,201,SOV
DI:0.1UF,201,SOV
OI:0.1UF,201,SOV
OI:0.1UF,ZOl,SOV
04222
04222
04222
04222
04222
04222
MA205E104MAA
14A205E104MM
I4A205£104MI\A
14A205E104MM
I4A205E104MtlA
MA205E104101AA
A34C676
A34C680
A34C702
A34C706
A34C710
A34C714
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
CAP,txD,CER
CAP,txD,CER
CAP,txO,CER
CAP.fXO.CER
CAP,fXO,CER
CAP,fXD,CER
OI:O.1UF,201,SOV
OI:0.1UF,201,SOV
DI:0.1UF,201,SOV
01:0.1Uf,201,SOV
DI:0.1UF.201,SOV
DI:0.1Uf,201,SOV
04222
04222
04222
04222
04222
04222
MA205E104MAA
I4112D5E 104MnA
I4A205E104MI\A
NA205E1011MAA
MA205E104MM
MAZ05E104101nA
A34(720
A34C760
A34C762
A34C764
A34C782
A34C786
281-0775-00
281-0775-00
281-0775-00
281-0775-00
119-1762-00
290-1014-00
CAP,FXD,CER DI:0.1Uf,201,SOV
CAP,FXD,CER DI:D.1UF,201,SOV
CAP,FXD,CER DI:0.1Uf,20%,SOV
CAP,FXO,CER OI:0.1Uf,201,SOV
fIlTER,RfI:22000Pf,SOV KITH fERRITE BEAD
CAP,FXO,ELCTLT:1Uf,35V
04222
04222
04222
04222
80009
SOO09
MA205E104MM
I4A205E104MAA
I4A205E104MIlA
14A205(1041AnA
119-1762-00
290-1014-00
A34C788
A34C790
A34C800
A34C802
A34C804
A34C806
283-0059-00
119-1762-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
CAP, FXD,CER 01: 1UF, +SO-20l,SOV
fILTER ,RfI : 22000Pf ,SOV KITH fERRITE BEAO
CAP,FXD,CER DI:0.1Uf,201,SOV
CAP,FXO,CER DI:0.1UF,20l,SOV
CAP,FXO,CER OI:O.1Uf,201,SOV
CAP,FXO,CER 01:0.1UF,2O%,SOV
31433
80009
04222
04222
04222
04222
C330C105M5R5CA
119-1762-00
I4A205E104IAAA
MA205E1041AIlA
I4A205E104IAAA
I4A2OSE104MflA
A34C808
A34C810
A34C828
A34C8110
A34C900
A34C902
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXD,CER
DI:0.1UF,201,SOV
DI:0.1Uf,201,SOV
DI:0.1UF,201,SOV
OI:0.1UF,201,SOV
DI:0.1UF,201,SOV
OI:0.1UF,201,SOV
04222
04222
04222
04222
04222
04222
14A205E104NAA
I4A205E104WIlIl
14A205E104MnA
I4A205E104NIlIl
14A205E104141lA
I4AZ05E104141iA
A34C904
A34C906
A34C910
A34C912
A34C916
A34C960
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
283-0059-00
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXD,CER
CAP,FXO,CER
DI:0.1UF,201,SOV
DI:0.1UF,201,SOV
OI:0.1Uf,201,SOV
OI:0.1Uf,20I,SOV
DI:0.1UF,201,SOV
DI:1UF,+SO-201,SOV
04222
04222
04222
04222
04222
31433
MA205E104MIlA
I4A205E104MAA
14A205E104MnA
14A205E104101f1A
I4A20SE1 OIlMIlA
C330C105M5R5CA
A34C964
A34C966
A34C968
A34C970
A34C976
290-1084-00
119-1762-00
281-0775-00
119-1762-00
281-0775-00
CAP,FXO,ElCTLT:100UF,201,16V
fIlTER,Rfl:22000Pf,SOV KITH FERRITE BEAD
CAP,FXD,CER 01:0.1Uf,201,SOV
fllTER,RfI:22000Pf,SOV KITH fERRITE BEAD
CAP,FXO,CER 01:0.1Uf,201,SOV
80009
80009
04222
80009
04222
290-100'1 l)O
119-1762-0lJ
I4A205E104NAA
119-1762-00
NA205E104101AA
10-4
Name & DescriQtion
Replaceable Electrical Parts - 91816,91832
9zmQgnent No,
A34(986
A34C988
A34C990
A34C992
A34C996
A34CR240
Serial/Assembly No.
Tektronix
Oscont
eart No,
~ffective
283-0059-00
119-1762-00
290-1083-00
281-0814-00
283-0833-00
152-0882-00
Name II Q!scril!tion
CAP,FXD,CER DI:1UF,+BO-2OX,SOV
FILTER,RFI:22DOOPF,SOV KITH FERRITE BEllO
CAP,FXD,ELCTLT:220UF,2DX,16V
CAP,FXD,CER 01:100 PF,101,100V
CAP ,FXO,CER 01 :1ooUF, +8O-2DX,25V
SENICOND OVC,OI:SI,100MA,BOV
Mfr.
9zde
31433
BOO09
BOO09
04222
BOO09
SOO09
Mfr. Part No.
C330C105M5RSClI
119-1762-00
290-1083-00
MA101A101KAA
283-0833-00
152-0882-00
A34CR32O
A34CR340
A34CR700
A34CR72O
A34CR960
A340L240
152-0882-00
152-0882-00
152-0882-00
152-0882-00
152-0881-00
119-1891-00
SEMICONO DVC,OI:SI,100MA,BOV
SEMICONO DVC,OI:SI,100MA,BOV
SENICOND OVC,DI:SI,100MA,BOV
SENICOND DVC,OI:SI,1OOMA,BOV
SENICONO OVC,DI:SI,4A,30V
DELAY LINE,ELEC:5NS,1000HM,3 SIP
BOO09
SOO09
BOO09
BOO09
BOO09
SOD09
152-0882-00
152-0882-00
152-0882-00
152-0882-00
152-0881-00
119-1891-00
A340L280
A34DL290
A34DL310
A340l32O
A34Dt400
A340l420
119-1893-00
119-1891-00
119-1893-00
119-1891-00
119-1893-00
119-1893-00
DELAY
DELAY
DELAY
DELAY
DELAY
DELAY
LINE,ELEC:3NS,1oo0HM,3
LINE,ELEC:5NS,1oo0HM,3
LINE,ElEC:3NS,1oo0HM,3
lINE,ElEC:5NS,1000HM,3
LINE,ElEC:3NS,1oo0HM,3
lINE,ElEC:3NS,1000HM,3
BOO09
BOO09
BOO09
BOO09
SOO09
SOO09
119-1893-00
119-1891-00
119-1893-00
119-1891-00
119-1893-00
119-1893-00
A340l60D
A34DL700
A34DlnO
A340L740
A34DL760
A340t780
119-1894-00
119-1889-00
119-1889-00
119-1889-00
119-1890-00
119-1890-00
DELAY
DELAY
DELAY
DELAY
DELAY
DELAY
lINE,ElEC:2NS,1000HM,3 SIP
lINE,ElEC:1ONS,INPUT SO/OUTPUT
LINE,ELEC:1ONS,INPUT SO/OUTPUT
lINE,ELEC:1ONS,INPUT SO/OUTPUT
LINE,ELEC:5NS,INPUT SO/OUTPUT
LINE,ELEC:5NS,INPUT SO/OUTPUT
B0009
BOO09
BOO09
80009
BOO09
B0009
119-1894-00
119-1889-00
119-1889-00
119-1889-00
119-1890-00
119-1890-00
A340L800
A34Dl820
A34J1oo
A344120
A34J140
A34J160
119-1889-00
119-1922-00
131-3087-00
131-3087-00
131-3087-00
131-3068-00
DELAY LINE,ElEC:1ONS,INPUT SO/OUTPUT
DELAY l1NE:13NS,1oo0HM,16 DIP
CONN,RCPT,ElEC:HEADER,RIGHT ANGLE,2 X 17
CONN,RCPT,ElEC:HElIDER,RIGHT ANGlE,2 X 17
CDNN;RCPT,ElEC:HElIDER,RIGHT ANGLE,2 X 17
JACK,TELEPHONE:SUBMINIATURE,CKT BD NT
SOO09
BOO09
22526
22526
22526
82389
119-1889-00
119-1922-00
679SO-OO1
679SO-OO1
679SO-o01
MDPC-2/HIA
A34J1BO
A34L952
A34l954
A340720
A340722
A3409SO
131-3068-00
108-1248-00
108-1248-00
151-0221-00
151-0221-00
151-0809-00
JACK,TELEPHONE:SUBMINIATURE,CKT BD NT
CDIL,RF:FXD,BOUH
COl L,RF: FXD ,BOUH
TRANSISTOR:PNP,SI,TO-92
TRANSISTOR:PNP,SI,TD-92
TRANSISTOR:HPN,SI
82389
B0009
BOO09
04713
04713
BOOO9
MDPC-2A-RA
108-1248-00
108-1248-00
SPS246
SPS246
151-0809-00
A340952
A340954
A34R160
A34R162
A34R164
A34R180
151-0B08-00
151-0807-00
307-0913-00
307-0913-00
307-0913-00
307-0904-00
TRANSlSTOR:PNP,SI
TRANSISTOR:NPN,SI
RES NTKK,FXD,FI:(8)4.7K OHM,Sl,O.125M EACH
RES NTKK,FXD,FI:(8)4.7K OHM,Sl,O.125M EACH
RES NTKK,FXD,FI:(8)4.7K OHM,Sl,O.125M ElICH
RES NTKK,FXD,FI:(4)10K OHM,Sl,O.125M EACH
80009
80009
B0009
80009
151-0808-00
151-0807-00
307-0913-00
307-0913-00
307-0913-00
307-0904-00
A34R258
A34R260
A34R264
tl34R266
A34R268
A34R270
307-1183-00
307-1182-00
307-0489-00
307-0489-00
307-0489-00
313-0101-00
RES NTNK,FXD,FI:(6) ,75-360 ,Sl,O. 125M
RES NTKK,FXD,FI: (6) ,62OHM ,Sl,O. 125M
RES NTWK,FXD,FI:7,100 OHM,2DX,1.0K
RES NTKK,FXD,FI:7,100 OHM,2DX,1.OK
RES NTKK,FXD,Fl:7,100 OHM,201,1.0H
RES,FXD,FILM:1oo OHM,Sl,O.166M
B0009
BOO09
11236
11236
11236
80009
307-1183-00
307-1182-00
750-81-R100
750-81-R100
7SO-81-R100
313-0101-00
A34R272
A34R274
A34R276
A34R282
tl34R284
A34R286
313-0331-00
31HJ471-00
313-0202-00
313-0331-00
313-0471-00
313-0202-00
RES,FXD,FILM:330 OHM,Sl,O.166H
RES,FXD,FILM:470 OHM,Sl,O.166H
RES,FXD,FILM:2K OHM,Sl,O.166M
RES,FXO,FILM:330 OHM,Sl,O.166H
RES,FXD,FILM:470 OHM,Sl,O.166M
RES,fXD,FILM:2K OHM,Sl,O.166M
80009
80009
80009
BOO09
B0009
BOO09
313-0331-00
313-0471-00
313-0202-00
313-0331-00
313-0471-00
313-0202-00
A34R3SO
A34R352
A34R360
A34R362
tl34R364
307-0489-00
307-0489-00
307-0489-00
307-0489-00
307-0489-00
RES
RES
RES
RES
RES
11236
11236
11236
11236
11236
750-81-R100
750-81-R100
7SO-81-R100
750-81-R100
750-81-R100
NTWK,FXD,FI:7,100
NTKK,FXD,FI:7,100
NTKK,FXO,FI:7,100
NTKK,FXD,FI:7,1oo
NTMK,FXD,FI:7,1oo
SIP
SIP
SIP
SIP
SIP
SIP
OHM,2DX,1.0K
DHM,2DX,1.0H
OHM,2DX,1.0K
OHM,201,1.OK
OHM,2DX,1.OK
80009
80009
10
Replaceable Electrical Parts - 91516,91532
ComQQnent No,
Tektronix
Part No,
A34R366
A34R368
A34R370
A34R372
A34R374
A34R376
307-0489-00
307-0489-00
315-0474-00
321-0248-00
321-0142-00
321-0289-07
A34R378
A34R380
A34R382
A34R384
A34R386
A34R388
Serial! Assembly No.
Effective
Dscont
Mfr.
Code
Mtr. Part No.
RES NTKK,FXO,fI:7,100 OHM,2OX,1.0K
RES NTKK,FXO,fI:7,100 OHM,201,1.0K
RES,FXO,fILM:470K OHM,Sl,O.2SH
RES,FXO,fILM:3.74K OHM,11,0.12SH,TC=TO
RES,FXO,fILM:294 OHM,11,0.125H,TC=TO
RES,FXO,frLM:10.0K OHM,0.11,0.125H,TC=T9
11236
11236
19701
19701
07716
19701
75O-81-R100
75O-81-R100
5043CX470KOJ92U
5043ED3K740f
CEA0294ROf
5033RE10K008
315-0103-00
315-0103-00
321-0289-07
321-0924-07
315-0392-00
321-0414-04
RES,FXO,fILM:10K OHM,Sl,0.25H
RES,FXD,fILM:10K OHM,Sl,0.25H
RES,FXD,fILM:10.0K OHM,0.11,0.125H,TC=T9
RES,FXO,fILM:40K OHM,O.11,0.125H,TC=T9
RES,FXO,fILM:3.9K OHM,Sl,O.25M
RES,FXO,fILM:200K OHM,O.1I,O.125H,TC=T2
19701
19701
19701
07716
57668
19701
S043CX10KOOJ
5043CX10KOOJ
5033RE10K008
CEAE40001B
NTR25J-ED3K9
5033RCZOOK08
A34R390
A34R392
A34R45O
A34R452
A34R454
A34R460
311-2041-00
311-0634-04
307-0489-00
307-0489-00
307-0489-00
307-0489-00
RES,VAR,NONHW:CKT 80,10K OHM,1OX,O.SH
RES,VAR,NONHW:TRMR,500 OHM,201,0.SH
RES NTKK,fXO,fI:7,100 OHM,2OX,1.0K
RES NTHK,FXD,FI:7,100 OHM,201,1.0K
RES NTHK,FXO,fl:7,100 OHM,201,1.0K
RES NTHK,FXO,FI:7,100 OHM,201,1.0K
80009
80009
11236
11236
11236
11236
311-2041-00
311-0634-04
75O-81-R100
75O-81-R100
75O-81-R100
75O-81-R100
A34R462
A34R464
A34R466
A34R468
A34R4i'0
l!34R472
307-0489-00
307-0489-00
307-0489-00
307-0489-00
307-0489-00
307-0489-00
RES
RES
RES
RES
RES
RES
NTKK,FXD,FI:7,100
NTHK,FXD,FI:7,100
NTKK,FXD,FI:7,100
NTHK,FXD,fI:7,100
NTKK,fXD,fI:7,100
NTHK,fXO,fI:7,100
OHM,20%,1.0K
OHM,201,1.0K
OHM,201,1.0K
OHM,201,1.0K
OHM,201,1.0K
OHM,201,1.0K
11236
11236
11236
11236
11236
11236
75O-81-R100
75O-81-R100
75O-81-R100
75O-81-R100
75O-81-R100
75O-81-R100
A34R4i'4
l!34R476
A34R480
A34R482
l!34R560
A34R562
307-0489-00
307-0489-00
307-0489-00
307-0489-00
307-1186-00
307-1186-00
RES
RES
RES
RES
RES
RES
NTHK,fXD,fl:7,100 OHM,20I,1.0W
NTKK,fXD,fI:7,100 OHM,201,1.0K
NTHK,fXO,FI:7,100 OHM,201,1.OH
NTWK,fXO,FI:7,100 OHM,201,1.0K
NTHK,FXD,FI: (4) ,2K,Sl,0.125K
NTHK,FXO,fI:(4),2K,Sl,0.125H
11236
11236
11236
11236
SOO09
80009
75O-81-R100
75O-8Hl100
75O-81-R100
75O-81-R100
307-1186-00
307-1186-00
A34R564
A34R566
A34R568
1134R570
A34R572
A34R5i'4
307-1185-00
307-1185-00
307-0489-00
307-0489-00
307-0489-00
307-0489-00
RES
RES
RES
RES
RES
RES
NTKK,fXO,FI:(4),2.7K,1.3K,5%,0.125H
NTHK,fXO,FI:(4),2.7K,1.3K,Sl,0.125H
NTHK,fXO,fl:7,100 OHM,20I,1.0W
NTHK,fXO,FI:7,100 OHM,201,1.0W
NTKK,fXO,fl:7,100 OHM,201,1.0W
NTKK,fXO,fI:7,100 OHM,201,1.0H
80009
80009
11236
11236
11236
11236
307-1185-00
307-1185-00
75O-a1-Ri00
750-81-R100
75O-81-R100
75O-81-R100
A34R576
1134R578
A34R580
1134R590
A34R592
A34R658
A34R658
307-0489-00
307-0489-00
307-0489-00
313-0272-00
313-0822-00
307-0489-00
307-0489-00
RES NTNK,fXO,fI:7,100 OHM,201,1.0K
RES NTKK,fXO,FI:7,100 OHM,20I,1.0K
RES NTKK,FXO,FI:7,100 OHM,20I,1.0K
RES,fXD,fILN:2.7K OHM,Sl,0.166"
RES,fXO,fILN:8.2K OHM,Sl,O.166H
RES NTKK,fXO,FI:7,100 OHM,20%,1.0K
RES NTKK,FXD,fI:7,100 OHM,20I,1.0K
11236
11236
11236
80009
80009
11236
11236
75O-81-R100
750-81-11100
75O-81-R100
313-0272-00
313-0822-00
75O-81-R100
75O-81-1!100
A34R660
A34R660
A34R662
A34R662
1134R664
A34R666
307-0489-00
307-0489-00
307-0489-00
307-0489-00
307-0489-00
307-0489-00
RES
RES
RES
RES
RES
RES
NTKK,FXO,FI:7,100
NTKK,fXD,fI:7,100
NTKK,fXD,fI:7,100
NTHK,fXD,fl:7,100
NTKK,fXO,FI:7,100
NTHK,FXO,FI:7,100
OHM,201,1.0K
OHM,20I,1.0K
OHM,2Ol,1.0K
OHM,20I,1.0K
OHM,201,1.0W
OHM,201,1.0K
11236
11236
11236
11236
11236
11236
75O-81-R100
75O-81-R100
75O-81-R100
750-81-R100
75O-81-R100
75O-81-R100
A34R668
A34R670
A34R672
A34R676
A34R678
A34R680
307-0489-00
307-0489-00
307-0489-00
307-0489-00
307-0489-00
307-0489-00
RES
RES
RES
RES
RES
RES
NTKK,fXO,fl:7,100
NTKK,fXO,FI:7,100
NTWK,fXO,fI:7,100
NTKK,FXO,fl:7,100
NTKK,FXO,fI:7,100
NTHK,fXO,fI:7,100
OHM,201,1.0K
OHM,2OI,1.0H
OHM,201,1.0K
OHM,201,1.0K
OHM,201,1.0K
OHM,20I,1.0K
11236
11236
11236
11236
11236
11236
75O-81-R100
75O-81-R100
750-81-R100
75O-81-R100
75O-81-R100
75O-81-R100
A34R684
A34R694
A34R760
A34R762
307-0489-00
307-0489-00
307-0489-00
315-0330-00
RES NTHK, FXO ,f!
RES NTKK,fXO,FI
RES NTKK,fXO,fl
RES,FXO,FILN:33
7,100 OHM,201,1.0K
7,100 OHM,2Ol,1.0K
7,100 OHM,20%,1.0K
OHM,Sl,O.25H
11236
11236
11236
19701
75O-81..,R100
75O-81-R100
75O-81-R100
5043CX33ROOJ
10-6
Name & DescriQtion
Replaceable Electrical Parts - 91516,91532
ComQ2nent No.
Tektronix
Part No.
"34R764
113411766
1134R770
113411818
113411850
113411852
315-0270-00
315-0270-00
313-0101-00
307-0489-00
307-1185-00
307-1185-00
1134R854
11341!856
11341!858
113411860
113411862
A3411864
Serial I Assembly No.
!;;ffective
Dscont
Mfr.
Code
Mfr. Part No ...._
RES,FXD,FILM 27 OHM,St,0.2~
RES,FXD,FILM 27 OHM,SX,0.2~
IIES,FXD,FILM 100 OHM,St,0.166M
RES NTMK,FXD,FI:7,100 OHM,20I,1.0M
RES NTHK,FXD,FI:(4),2.7K,1.3K,SX,O.12~
RES NTMK,FXD,FI:(4),2.7K.1.3K,SX,O.12SM
19701
19701
BOO09
11236
80009
80009
5043CX271100J
5043CX271100J
313-0101-00
750-81-11100
307-1185-00
307-1185-00
307-1185-00
307-1185-00
307-1185-00
307-1185-00
307-1185-00
307-1185-00
RES
RES
RES
RES
RES
RES
NTMK,FXD,FI:(4),2.7K,1.3K,SX,0.12SH
NTMK,FXD,FI:(4),2.7K,1.3K,SX,0.12SH
NTMK,FXD,FI:(4),2.7K,1.3K,St,O.12SH
NTMK,FXD,FI:(4),2.7K,1.3K,St,0.12SH
NTMK,FXD,FI:(4).2.7K,1.3K,SX,O.12SH
NTMK,FXD,FI:(4),2.7K,1.3K,SX,O.12SH
80009
80009
BOO09
BOO09
BOO09
BOO09
307-1185-00
307-1185-00
307-1185-00
307-1185-00
307-1185-00
307-1185-00
1134R866
113411868
11341!870
113411872
113411874
A34R876
307-1185-00
307-1185-00
307-1185-00
307-1185-00
307-1185-00
307-1185-00
RES
RES
RES
RES
liES
RES
NTMK,FXD,FI:(4),2.7K,1.3K,St,O.12SH
NTMK,FXD,FI:(4),2.7K,1.3K,St,O.12SH
NTMK,FXD,FI:(4),2.7K,1.3K,St,0.12SH
NTMK,FXD,FI:(4),2.7K,1.3K,SX,O.12SH
NT"K,FXO,FI:(4),2.7K,1.3K,SX,O.12SW
NT"K,FXD,FI:(4),2.7K,1.3K,St,O.12SH
80009
BOO09
80009
BOO09
BOO09
BOO09
307-1185-00
307-1185-00
307-1185-00
307-1185-00
307-1185-00
307-1185-00
113411940
113411942
1134R944
A3411950
A34R952
A3411954
307-1184-00
307-1184-00
307-0913-00
308-0849-00
313-0101-00
313-0101-00
RES NTMK,FXD,Fl:(4),8.2K-2.7K,St,O.12SH
RES NT"K,FXD,Fl:(4),8.2K-2.7K,SX,O.12SH
RES NTMK,FXD,Fl:(8)4.7K OHM,SI,O.12SH EACH
RES,FXD,HH:30M OHM,10I,2H
RES,FXD,FILM:100 OHM,SX,O.166"
RES,FXD,FILM:100 OHM,SX,O.166W
BOO09
BOO09
BOO09
BOO09
BOO09
80009
307-1184-00
307-1184-00
307-0913-00
308-0849-00
313-0101-00
313-0101-00
A3411956
113411958
A341196{l
A3411962
A3411964
113411966
313-0122-00
321-0235-00
321-0121-00
315-0180-00
321-0221-00
315-0102-00
RES,FXD,FILM:1.2K OHM,SX,O.166W
RES,FXD,FILM:2.74K OHM,1I,0.12SH,TC=TO
RES,FXD,FILM:1780HM,1I,O.12SH,TC=TO
RES,FXO,FILM:18 OHM,5I,O.2SH
RES,FXD,FILM:1.96K OHM,1I,O.12SH,TC=TO
RES,FXD,FILM:1K OHM,5I,0.2SH
BOO09
07716
07716
19701
19701
57668
313-0122-00
CEA027400F
CEA0178110F
5043CX181100.i
5043ED1K960F
NTR25JE01KO
A34TP200
A34TP240
1134TP280
A34TP300
A34TP320
A34TP360
131-0590-03
131-0590-03
131-0590-03
214-0579-00
214-0579-00
131-0590-03
TERMINAl,PIN:0.38
TERMINAl,PIN:0.38
TERMINAl,PIN:0.38
TERM,TEST POINT:
TERIoI,TEST POINT:
TERMINAl,PIN:0.38
BOO09
BOO09
80009
BOO09
80009
BOO09
131-0590-03
131-0590-03
131-0590-03
214-0579-00
214-0579-00
131-0590-03
A34TP400
A34TP440
A34TP600
A34TP610
A34TP700
A34TP720
131-0590-03
131-0590-03
131-0590-03
131-0590-03
131-0590-03
131-0589-00
TERMINAl,PIN:0.38 l X 0.025 SO,NO
TEIIMINAl,PIN:0.38 l X 0.025 Sa,NO
TERMINAl,PIN:0.38 L X 0.025 Sa,NO
TERMINAl,PIN:0.38 l X 0.025 Sa,NO
TERMINAL,PIN:0.38 l X 0.025 Sa,NO
TERIoI,PIN:0.46L X 0.025 sa BRZ OLD
FERRULE
FERRULE
FERRULE
FERRULE
FERRULE
PL
BOO09
80009
BOO09
80009
80009
22526
131-0590-03
131-0590-03
131-0590-03
131-0590-03
131-0590-03
48283-029
A34TP740
A34TP76{l
A34TP780
A34TP800
A34TP860
1134TP910
131-0590-03
131-0590-03
131-6590-03
131-0590-03
214-0579-00
214-0579-00
TERIoIINAL,PIN:0.38
TERMINAL,PIN:0.38
TERMINAl,PIN:0.38
TERMINAl,PIN:0.38
TERM,TEST POINT:
TERM,TEST POINT:
FERRULE
FERRULE
FERRULE
FERRULE
BOO09
80009
80009
80009
80009
80009
131-0590-03
131-0590-03
131-0590-03
131-0590-03
214-0579-00
214-0579-00
1134TP930
A34TP940
tl34TP950
A34TP960
A34TP970
A34TP980
214-0579-00
214-0579-00
214-0579-00
214-0579-00
214-0579-00
131-0590-03
TERM,TEST POINT:
TEIIM,TEST POINT:
TERIoI,TEST POINT:
TERM,TEST POINT:
TERM,TEST POINT:
TERMINAl,PIN:0.38 L X 0.025 sa,NO fERRULE
80009
80009
80009
80009
BOO09
80009
214-0579-00
214-0579-00
214-0579-00
214-0579-00
214-0579-00
131-0590-03
A34TP990
A34U100
"34U102
A34U106
A34U108
214-0579-00
156-1111-02
156-1111-02
156-1111-02
156-1111-02
TERM,TEST POINT:
MICROCKT,DGTL:OCT
MICROCKT,DGTL:OCT
MICROCKT,DGTl:OCT
MICROCKT,DGTl:OCT
BOO09
01295
01295
01295
01295
214-0579-00
SN74lS245N3
SN74 LS245N3
SN74LS245N3
SN74LS245N3
Name & DescriQtion
L X 0.025 SO,NO FEIIRUlE
l X 0.025 SO,NO FERRULE
L X 0.025 SO.NO FERRULE
l X 0.025 SO,NO FERRULE
L X 0.025
L X 0.025
l X 0.025
l X 0.025
BUS
BUS
BUS
8US
XCVRS
XCVRS
XCVRS
XCVRS
sa,NO
sa,NO
sa,NO
sa.NO
M/3
N/3
M/3
N/3
ST
ST
ST
ST
OUT
OUT
OUT
OUT
10-
Replaceable Electrical Parts - 91516,91532
ComQQnent No,
Tektronix
Part No,
A34U112
A34U114
A34U116
A34U118
A34U120
A34U122
156-2316-00
156-0541-02
156-0392-03
156-2302-00
160-3134-01
160-3133-00
A34U124
A34U130
A34U132
A34U134
A34U180
A34U182
totfr,
Serial! Assembly No.
Effective
Oscont
!;&de
Mfr. Part No.
MICROCKT,OGTL:3/8 LINE DECODER
MICROCKT,OGTL:DUAL 2-TO 4-LINE DCDR/DEMUX
MICROCKT,OGTL:OUAD LATCH "ICLEAR,SCRN,
MICROCKT ,OGTL:4/16 LINE DECODER
MICROCKT,OGTL:32768 X 8 EPROM,PRGM
MICROCKT,OGTL:32768 X 8 EPROM,PRGM
80009
04713
07263
80009
80009
80009
156-2316-00
SN74LS139NOS
74LS175PCQR
156-2302-00
160-3134-01
160-3133-00
160-3132-02
156-2315-00
156-2300-00
156-2309-00
156-2301-00
156-2301-00
MICROCKT,OGTL:32768 X 8 EPROM,PRGM
MICROCKT,OGTL:3 STATE OCTAL 0 TYPE fF
MICROCKT,OGTL:OCTAl 8UffER W/3 STATE OUT
MICROCKT ,DGTL:HEX INVERTER
MICROCKT,OGTL:OUAD 8UFfER "/3 STATE
MICROCKT,OGTL:OUAD BUffER "/3 STATE
80009
80009
80009
80009
80009
80009
160-3132-02
156-2315-00
156-2300-00
156-2309-00
156-2301-00
156-2301-00
A34U194
A34U200
A34U206
A34U208
A34U210
A34U212
156-2310-00
156-2314-00
156-1667-01
156-1639-02
156-1640-02
156-0230-00
MICROCKT,OGTL:HEX TYPE fF
MICROCKT,OGTL:QUAO EXCL OR
MICROCKT,OGTL:B LINE NUX
MICROCKT,OGTL:ECL,DUAL 0 MA-SLAVE FF
MICROCKT,OGTL:TRIPlE LINE RCVR
MICROCKT,OGTL:ECL,DUAL 0 MASTER-SLAVE FF
80009
80009
80009
SOO09
- 80009
04713
156-2310-00
156-2314-00
156-1667-01
156-1639-02
156-1640-02
MC 10131 (L OR P)
A34U214
A34U216
A34U218
A34U222
A34U224
A34U230
156-1639-02
156-1639-02
156-1668-01
156-1743-00
156-1676-01
156-1640-02
MICROCKT,DGTl:ECl,OUAlD MA-SLAVE FF
MICROCKT,OGTl:ECl,DUAL 0 MA-SLAVE FF
MICROCKT,OGTL:QUAO 2 INPUT OR/NOR
MICROCKT,OGTL:ASTTL,QUAO 2-INPUT NOR GATE
MICROCKT,OGTL:TRIPlE 2 INPUT EXCL
MICROCKT,OGTL:TRIPLE LINE RCVR
SOO09
80009
80009
18324
80009
80009
156-1639-02
156-1639-02
156-1668-01
74F02 NIl OR fB
156-1676-01
156-1640-02
A34U232
A34U25O
A34U300
A34U302
A34U304
156-0230-00
156-1639-02
156-0308-05
156-0543-02
156-0880-04
MICROCKT,DGTL:ECL,DUAl 0 MASTER-SLAVE FF
MICROCKT,OGTL:ECL.DUAlO MA-SLAVE FF
MICROCKT,OGTL:ECL,RECEIVER QUAD DIFF LINE
MICROCKT,OGTL:HEX SUFFER
MICROCKT,DGTL:DUAL D-TYPE MASTER SLAVE FLIP
FLOP
04713
80009
80009
80009
80009
MC1D131 (L OR P)
156-1639-02
156-0308-05
156-0543-02
156-0880-04
A34U306
A34U308
156-1639-02
156-0880-04
80009
80009
156-1639-02
156-0880-04
A34U310
A34U312
A34U314
156-0230-00
156-0230-00
156-1639-02
MICROCKT,DGTL:ECL,DUAL 0 MA-SLAVE FF
MICROCKT,DGTL:DUAL D-TYPE MASTER SLAVE FLIP
FLOP
MICROCKT,OGTL:ECL,DUAlO MASTER-SLAVE FF
MICROCKT,OGTL:ECl,DUAlD MASTER-SLAVE FF
MICROCKT,DGTL:ECL,OUAL MA-SLAVE FF
04713
04713
SOO09
MC10131(L OR P)
MC10131(L OR P)
156-1639-02
A34U316
A34U320
A34U322
A34U324
A34U330
156-0759-00
156-1311-01
156-1699-00
156-1020-01
156-0880-04
MICROCKT,DGTL:ECL,QUAD 2 IMP OR GATE
MICROCKT,LINEAR:D/A CONVERTER
MICROCKT,LINEAR:DUAl SI-FET,OPNL AMPL
MICROCKT,DGTL:DUAL MUX M/LATCH
MICROCKT,OGTL:DUAL O-TYPE MASTER SLAVE FLIP
FLOP
04713
18324
01295
80009
SOO09
MC10103 L OR P
NE5018N8
TL288CP
156-1020-01
156-0880-04
A34U332
A34U334
A34U400
A340402
A340404
A340406
156-0759-00
156-0230-00
156-1891-01
156-1891-01
156-1891-01
156-1085-02
MICROCKT,OGTL:ECL,OUAO 2 INP OR GATE
MICROCKT,DGTL:ECL,OUAL MASTER-SLAVE FF
MICROCKT,DGTl:QUAO 2 LINE NUX
MICROCKT.DGTL:QUAD 2 LINE MUX
MICROCKT,OGTL:QUAO 2 LINE MUX
MICROCKT,DGTL:ECL,16 INP MULTIPLEXER
04713
04713
80009
80009
80009
07263
MC10103 L OR P
MC10131(L OR P)
156-1891-01
156-1891-01
156-1891-01
F1001640C
A340408
A340410
A340412
A340414
A340416
A340418
156-2313-00
156-2313-00
156-2313-00
156-2313-00
156-103S-00
156-1038-00
MICROCKT ,DGTL:3/8 LINE OECOOER
MICRDCKT,DGTL:3/8 LINE DECODER
MICROCKT,DGTL:3/8 LINE OECODER
MICROCKT,DGTL:3/8 LINE OECODER
MICROCKT,OGTL:ECL,4 SIT SINARY COUNTER
MICROCKT,OGTL:ECL,4 81T 8INARY COUNTER
80009
80009
80009
80009
07263
07263
156-2313-00
156-2313-00
156-2313-00
156-2313-00
F100160C
F100160C
A340420
A340422
A34U424
A34U426
A340428
156-1038-00
156-0759-00
156-0759-00
156-0308-05
156-0308-05
ICROCKT ,OGTl:ECL,4 81T BINARY COUNTER
MICROCKT,DGTL:ECL,QUAO 2 INP OR GATE
MICROCKT,OGTL:ECL,QUAO 2 INP OR GATE
MICROCKT,OGTL:ECL,RECEIVER QUAO DIFF LINE
MICROCKT,OGTl:ECL,RECEIVER QUAO OIFF LINE
07263
04713
04713
80009
80009
F10016DC
MC10103 L OR P
MC10103 L OR P
156-0308-05
156-0308-05
10-8
Name & Ogscril2tion
°
°
°
.101
Replaceable Electrical Parts - 91516,91532
ComQ!2nent No.
Tektronix
Part No.
Serial I Assembly No.
Effective
Dscont
Mfr.
Code
A34U430
A340432
A34U500
A34U502
A34U504
A34U504
156-0308-05
156-2308-00
156-1111-02
156-2315-00
156-2307-00
156-2557-00
Mfr. Part No.
WICROCKT,DGTL:ECl,RECEIYER QUAO DIFF LINE
WICROCKT,DGTL:DUAL 4-5 INPUT OR/NOR
WICROCKT,DGTL:DCT BUS XCVRS "/3 ST OUT
WICROCKT,DGTL:3 STATE OCTAL 0 TYPE FF
WICROCKT,DGTL:1024 X 4 STATIC RAW
WICROCKT,DGTL:1024 X 4,ECl,RAW
80009
80009
01295
80009
80009
80009
156-0308-05
156-2308-00
SN74LS245N3
156-2315-00
156-2307-00
156-2557-00
300101
300236
300235
A34U506
A34U506
A34U508
A34U508
A34U510
A34U510
156-2307-00
156-2557-00
156-2307-00
156-2557-00
156-2307-00
156-2557-00
300101
300236
300101
300236
300101
300236
300235
WICROCKT,DGTL:1024
WICROCKT,DGTl:1024
WICROCKT,DGTl:1024
WICROCKT,DGTl:1024
WICROCKT,DGTl:1024
WICROCKT,DGTL:1024
X 4 STATIC RAW
X 4,ECL,RAW
X 4 STATIC RAM
X 4,ECL,RAW
X 4 STATIC RAW
X 4,ECl,RAM
80009
80009
SOO09
80009
80009
80009
156-2307-00
156-2557-00
156-2307-00
156-2557-00
156-2307-00
156-2557-00
1134U512
A34U514
A34U516
A34U518
A34U518
A34U520
A34U520
156-2307-00
156-2307-00
156-2307-00
156-2288-00
156-2557-00
156-2307-00
156-2557-00
WICROCKT,DGTL:1024
WICROCKT,DGTL:1024
WICROCKT,DGTL:1024
WICROCKT,DGTL:1024
MICROCKT ,DGTL:1024
WICROCKT,DGTL:1024
WICROCKT,DGTl:1024
X 4 STATIC RAM
X 4 STATIC RAW
X 4 STATIC RAM
X 4 STATIC RAM
X 4,ECL,RAM
X 4 STATIC RAW
X 4,ECl,RAM
80009
SOO09
80009
SOO09
80009
80009
80009
156-2307-00
156-2307-00
156-2307-00
156-2288-00
156-2557-00
156-2307-00
156-2557-00
A34U522
A34U524
A34U524
A34U530
A34U532
A34U600
156-2307-00
156-2307-00
156-2557-00
156-0543-02
156-0543-02
156-1889-01
MICROCKT,DGTL:1024 X 4 STATIC RAM
WICROCKT,DGTL:1024 X 4 STATIC RAW
WICROCKT,DGTL:1024 X 4,ECL,RAM
WICROCKT,DGTl:HEX BUFFER
WICROCKT,DGTl:HEX BUFFER
WICROCKT,DGTL:UNIVERSAl HEX COUNTER
80009
80009
80009
80009
80009
80009
156-2307-00
156-2307-00
156-2557-00
156-0543-02
156-0543-02
156-1889-01
A34U602
A34U604
A34U606
A34U608
A34U610
A34U610
156-1889-01
156-1889-01
156-0641-00
156-0746-02
156-0746-02
156-1891-01
MICROCKT,DGTL:UNIYERSAl HEX COUNTER
WICROCKT,DGTL:UNIVERSAl HEX COUNTER
MICROCKT,DGTL:UNIVERSAl HEXIDECIMAl CNTR
WICROCKT ,DGTL:ECL,QUAD2-INPUT NON-INY WUX
MICROCKT,DGTl:ECL,QUAD 2-INPUT NON-INV MUX
WICROCKT,DGTl:QUAO 2 LINE MUX
80009
SOO09
04713
80009
80009
80009
156-1889-01
156-1889-01
WC10136l
156-0746-02
156-0746-02
156-1891-01
A34U612
A34U614
A34U616
A34U618
A34U620
A34U622
156-0746-02
156-0746-02
156-0637-02
156-0637-02
156-0637-02
156-0637-02
WICROCKT,DGTL:ECL,QUAD 2-INPUT NQN-INV NUX
MICROCKT,DGTL:ECL,QUAO 2-INPUT NQN-INV WUX
WICROCKT,DGTL:DUAL 4 TO 2 MUX
WICROCKT,DGTl:DUAL 4 TO 2 WUX
MICROCKT,DGTl:DUAl 4 TO 2 WUX
WICROCKT,DGTL:DUAl4 TO 2 WUX
80009
80009
SOO09
80009
80009
80009
156-0746-02
156-0746-02
156-0637-02
156-0637-02
156-0637-02
156-0637-02
A34U626
A34U628
A34U630
A34U632
A34U634
A34U636
156-2308-00
156-2308-00
156-0230-00
156-0633-00
156-0633-00
156-0633-00
WICROCKT ,DGTL:DUAl 4-5 INPUT OR/NOR
MICROCKT,DGTL:DUAl4-5 INPUT ORINOR
MICROCKT,DGTL:ECl,DUAL D MASTER-SLAVE FF
MICROCKT,DGTL:ECL,HEX 0 MASTER-SLAVE FF
MICROCKT,DGTl:ECL,HEX D MASTER-SLAVE FF
MICROCKT,DGTL:ECl,HEX 0 MASTER-SLAVE FF
80009
80009
04713
04713
04713
04713
156-2308-00
156-2308-00
WC10131(L OR P)
MC10176L
MC10176L
MC10176l
A34U638
A34U640
A34U700
A34U702
A34U704
1134U706
156-1674-01
156-1642-02
156-1641-02
156-1641-02
156-1676-01
156-1512-00
MICROCKT,DGTl:QUAO 2 INPUT ANO GATE
MICROCKT,DGTl:TRIPLE 2-3-2 IN OR/NOR GATE
MICROCKT,DGTL:ECl,QUAD 2-INPUT NOR GATE
WICROCKT,DGTL:ECl,QUAD 2-INPUT NOR GATE
MICROCKT,DGTl:TRIPlE 2 INPUT EXCl
MICROCKT,DGTl:ECl,HEX D FLIP-FLOP
80009
SOO09
80009
80009
SOO09
07263
156-1674-01
156-1642-02
156-1641-02
156-1641-02
156-1676-01
F100151DC
A340708
A34U710
A34U712
A34U714
A34U716
A34U716
156-1512-00
156-1512-00
156-1512-00
156-1640-02
156-0230-00
156-1639-02
WICROCKT,DGTL:ECl,HEX D FLIP-FLOP
WICROCKT,DGTL:ECl,HEX D FLIP-FLOP
MICROCXT,DGTL:ECl,HEX D FLIP-FLOP
WICROCKT,DGTL:TRIPlE LINE RCVR
MICROCKT,DGTl:ECl,DUAl D MASTER-SLAVE FF
WICROCKT,DGTl:ECl,OUAlO MA-SLAVE FF
07263
07263
07263
SOO09
04713
SOO09
F1001510C
F1001510C
F1001510C
156-1640-02
WC10131(L OR P)
156-1639-02
A34OO00
11340002
A34U804
A34OO06
156-1676-01
156-1641-02
156-2315-00
156-2315-00
WICROCKT,DGTl:TRIPlE 2 INPUT EXCl
MICROCKT,DGTl:ECL,QUAO 2-INPUT NOR GATE
WICROCKT,DGTl:3 STATE OCTAL 0 TYPE FF
WICROCKT,DGTl:3 STATE OCTAL D TYPE FF
80009
80009
80009
80009
156-1676-01
156-1641-02
156-2315-00
156-2315-00
300235
300235
300101
300236
300101
300236
300235
300101
300236
300235
300101
300236
300101
300236
300235
300235
300235
Name & Descrietion
10
Replaceable Electrical Parts - 91S16,91532
ComQ2nent No,
Tektronix
Part No,
A34OO08
A34U810
A34U812
A34U814
A34U82O
A34U900
156-2315-00
156-2315-00
156-2315-00
156-2315-00
156-1674-01
156-2315-00
1134U902
A34U904
A34U906
A34U908
A34U910
A34U912
Seriall Assembly No.
EH§ctive
Dscont
Mfr.
Code
Mtr, Part No.
MICROCKT,DGTL:3 STATE OCTAL 0 TYPE FF
MICROCKT,OGTL:3 STATE OCTAL 0 TYPE FF
MICROCKT,OGTL:3 STATE OCTAL 0 TYPE FF
MICROCKT,OGTL:3 STATE OCTAL 0 TYPE FF
MICROCKT,DGTL:QUAO 2 INPUT AND GATE
MICROCKT,DGTL:3 STATE OCTAL 0 TYPE FF
80009
80009
SOO09
SOO09
SOO09
SOO09
156-2315-00
156-2315-00
156-2315-00
156-Z315-00
156-1674-01
156-2315-00
156-1783-00
156-1783-00
156-1783-00
156-2305-00
156-2305-00
156-2305-00
MICROCKT,LINEAR:QUAO
MICROCKT,LINEAR:QUAO
MICROCKT,LINEAR:QUAO
MICROCKT,LINEAR:DUAL
MICROCKT,LINEAR:DUAL
MICROCKT,LINEAR:DUAL
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
SOO09
SOO09
SOO09
SOO09
SOO09
SOO09
156-1783-00
156-1783-00
156-1783-00
156-2305-00
156-2305-00
156-2305-00
A34U914
A34U916
A34U918
A34U920
A34U922
A34U924
156-2305-00
156-2305-00
156-2305-00
156-2305-00
156-2305-00
156-2305-00
MICROCKT,LINEAR:DUAl
MICROCKT,LINEAR:DUAL
MICROCKT,LINEAR:DUAL
MICROCKT,LINEAR:DUAL
MICROCKT,LINEAR:OUAL
MICROCKT,LINEAR:OUAL
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
BOO09
80009
SOO09
SOO09
80009
80009
156-2305-00
156-2305-{)0
156-2305-00
156-2305-00
156-2305-00
156-2305-00
A34U926
A34U928
A34U930
A34U934
A34U936
A34U938
156-2305-00
156-2305-00
156-2305-00
156-2305-00
156-2305-00
MICROCKT,LINEAR:DUAL
MICROCKT,LINEAR:OUAL
MICROCKT,LINEAR:DUAl
MICROCKT,LINEAR:DUAL
MICROCKT,LINEAR:DUAL
MICROCKT,LINEAR:DUAL
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
COMPARATOR
80009
SOO09
SOO09
80009
80009
SOO09
156-2305-00
156-2305-00
156-2305-00
156-2305-00
156-2305-00
156-2305-00
A34U940
A34U942
A34U946
A34U948
A34U9SO
A34U952
156-2305-00
156-2305-00
156-Z305-00
156-2305-00
156-2305-00
156-2305-00
MICROCKT,LINEAR:DUAL
MICROCKT,LINEAR:OUAL
MICROCKT,LINEAR:OUAL
NICROCKT,LINEAR:OUAL
NICROCKT,LINEAR:DUAl
MICROCKT,LINEAR:DUAL
COMPARATOR
COMPARATOR
COMPARATOR
CONPARATOR
COMPARATOR
COMPARATOR
SOO09
80009
80009
80009
BOO09
80009
156-2305-00
156-2305-00
156-2305-00
156-2305-00
156-2305-00
156-2305-00
A34U954
A34U956
A34U958
A34U960
A34U980
A35
156-2305-00
156-2305-00
156-1783-00
156-2300-00
156-1778-00
670-8811-00
MICROCKT,LINEAR:DUAL COMPARATOR
NICROCKT,lINEAR:OUAL COMPARATOR
NICROCKT,LINEAR:QUAD COMPARATOR
NICROCKT,OGTL:OCTAL BUFFER W/3 STATE OUT
MICROCKT,LINEAR:DUAL COMPARATOR
CIRCUIT 80 ASSY:PATT GEN MOOULE
(91532 ONLY)
80009
80009
80009
SOO09
80009
SOO09
156-2305-00
156-2305-00
156-1783-00
156-2300-00
156-1778-00
670-8811-{)0
A35C200
A35C202
A35C204
A35C206
A35C400
A35C402
290-1083-00
281-0814-00
283-0059-00
283-0833-00
290-1084-00
281-0775-00
CAP,FXO,ELCTLT:220UF,20I,16V
CAP,FXO,CER 01:100 PF,10I,100V
CAP,FXO,CER DI:1UF,+80-20I,SOV
CAP,FXO,CER OI:100UF,+80-20I,25V
CAP ,FXD ,ElCTlT:100UF,20I,16V
CAP,FXO,CER 01:0.1UF,20I,SOV
80009
04222
31433
80009
SOO09
04222
290-1083-00
MA101A101KIlA
C330C10SWSR5CA
283-0833-00
290-1084-00
MAZ05E104MAA
A35C404
A35C406
A35C40B
A35C410
A35C412
A35C414
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
01:0.1UF,20I,SOV
01:0.1UF,20I,SOV
01:0.1UF,20I,50V
01:0.1UF,ZOI,50V
01:0.1UF,20I,50V
OI:0.1UF,20I,50V
04222
04222
04222
04222
04222
04222
MA205E104MnA
MA205E104MnA
NA205E104101AIl
MA205E104MAil
MA205E104MAil
MAZ05E104MAIl
A35C416
A35C418
A35C420
A35C422
A35C424
A35C426
281-0775-00
2B1-0775-00
281-0775-00
281-0775-00
281-0775-00
281-0775-00
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
CAP,FXO,CER
DI:0.1UF,20I,50V
01:0.1UF,20%,50V
OI:0.1UF,20I,50V
01:0.1UF,20I,50V
01:0.1UF,20I,50V
01:0.1UF,2Ol,50V
04222
04222
04222
04222
04222
04222
MA205E104MAil
MA205E104141l1l
MA205E1 04141lA
MA205E104141l1l
MAZ05E10414tlA
MA205E1 O4MIlA
A35C428
A35C430
A35C432
A35C434
281-0775-00
281-0775-00
281-0775-00
281-0775-00
CAP. FXO ,CER
CAP,FXD,CER
CAP,FXO,CER
CAP.FXD,CER
01 :0. 1UF ,201 ,50V
01:0.1UF,201,50V
OI:0.1UF,201,50V
OI:0.1UF,2Ol,50V
04222
04222
04222
04222
MIl205E104141lA
MA205E10414M
MIlZ05E104I4AA
MAZ05E10414M
10-10
156~2305-00
Name & Q§scriQtion
Replaceable Electrical Parts - 91516,91532
Come2n~nt
No,
Tektronix
Part No,
Serial! Assembly No.
I;ffective
Dscont
Name & Descrietion
Mfr.
Code
Mfr. Part No.
1135C436
1135C438
1135C440
A35C442
1135C444
A35C446
281-o77S-OO
281-077S-OO
281-o77S-OO
281-o77S-00
281-o77S-00
281-o77S-00
CAP ,FXO,CER
CAP,FXD,CER
CAP ,FXD,CER
CAP,FXO,CER
CAP ,FXO,CER
CAP,FXO,CER
01 :O.lUF ,m,50V
DI:0.1UF,20t,50V
01 :O.lUF ,m,50V
01:0.1UF,20t,50V
01 :0.1UF ,m,50V
01:0.lUF,20t,50V
04222
04222
04222
04222
04222
04222
MA2OSE104MAA
MAZOSE104MAA
MAZOSE104MAA
MA2OSE104MAA
MA20SE104MAtl
MA2OSE104MAtl
1135(448
1135C45O
A35C452
A35C454
A35C4S6
1135C458
281-0775-00
281-0775-00
281-o77S-00
281-o77S-00
281-0775-00
281-0775-00
CAP,FXD,CER
CAP ,FXD,CER
CAP,FXD,CER
CAP, FXO ,CER
CAP ,FXD,CER
CAP ,FXD,CER
DI:0.1UF,m,50V
DI :0.1UF ,m,50V
DI:0.1UF,m,50V
01 :0.1UF ,m,sov
01 :0.1UF ,2Ot,SOV
DI :0.1UF ,m,sov
04222
04222
04222
04222
04222
04222
MAZOSE104Mtltl
MA20SE104Mtltl
Mtl2OSE104MAtl
MII20SE104MAA
MA205E104MAA
Mtl2OSE104MtlA
1135C460
1135C462
1135C464
1135C466
1135C468
A35C470
281-o77S-00
281-o77S-00
281-077S-00
281-o77S-00
281-o77S-00
281-0775-00
CIIP,FXD,CER
CIIP,FXO,CER
CAP.FXD,CER
CAP.FXD.CER
CAP .FXD,CER
CAP,FXD,CER
01:0.1UF,2Dt,50V
DI:0.1UF.20t.50V
OI:0.1UF.2Dt.SOV
DI:0.1UF.m,SOV
DI :0.1UF ,m,50V
DI:0.1UF,20t.50V
04222
04222
04222
04222
04222
04222
MA205E104MAtl
MA2OSE104MAA
MA205E104Mtltl
MA2OSE104MAA
MA20SE104MAtl
MA205E104MAtl
1135C472
A3SC474
1135C476
1135C478
1135C480
1135C482
281-o77S-00
281-o77S-00
281-o77S-00
281-o77S-00
281-o77S-00
281-o77S-00
CIIP,FXD,CER
CAP,FXD,CER
CAP,FXD,CER
CAP ,FXD,CER
CAP,FXO.CER
CAP.FXD,CER
DI:0.1UF,m,50V
DI:0.1UF,20t,50V
DI:0.1UF,m,50V
01 :O.lUF ,m,50V
DI:0.1UF,20t,50V
OI:O.lUF,20t.50V
04222
04222
04222
04222
04222
04222
MA2OSE104MAtl
MA20SE1 04MAA
MA20SE 104MAA
MA2OSE104MtlA
MA20SE104MtlA
MA20SE 104MAA
1135C484
A35C486
1135C488
A35C490
A35C492
A35C494
281-o77S-OO
281-o77S-00
281-o77S-00
281-o77S-00
281-o77S-00
281-o77S-00
CIIP.FXD.CER
CAP,FXD,CER
CAP,FXD,CER
CAP,FXO,CER
CAP,FXO.CER
CAP ,FXO,CER
DI:0.1UF.m,50V
DI:0.1UF,m,50V
DI:0.1UF,m,50V
DI:0.1UF,m,50V
DI:0.1UF,m,SOV
01 :O.lUF ,m,sov
04222
04222
04222
04222
04222
04222
MA2OSE104MAA
MA20SE1 04MA1I
MA205E104MAA
MA205E104MAtl
MII20SE1 04MAtl
MII20SE104MA1I
A35C496
A35C498
A35CSOO
A35CS02
tl35CS04
A35C506
281-o77S-00
281-o77S-00
281-o77S-00
281-o77S-OO
281-o77S-00
281-0775-00
CAP,FXO,CER
CAP,FXD,CER
CAP.FXO,CER
CAP,FXO,CER
CAP .FXO ,CER
CAP,FXD,CER
DI:0.1UF,2Dt,SOV
OJ:0.1UF,2Ot,50V
DI:0.1UF,2Dt,SOV
Dl:0.1UF,20t,SOV
01 :O.lUF ,m,50V
01:0.1UF,20t,SOV
04222
04222
04222
04222
04222
04222
MA20SE1 04MAA
Mtl20SE104MAtl
MA2OSE104MAA
MA20SE104MAtl
MA20SE104MAtl
MA2OSE104MAtl
A35CS08
A35C510
A3SC512
A35C514
A35CS16
A3SC518
281-o77S-00
281-o77S-OO
281-077S-00
281-o77S-00
281-o77S-OO
119-1762-00
CIIP,FXO,CER Dl:0.1UF.m.50V
CAP •FXO ,CER DI :O.lUF ,m,sov
CAP,FXO,CER Dl:0.1UF,20t,50V
CAP,FXO.CER DI:0.1UF,20t,SOV
CIIP,FXD,CER OI:O.lUF,m,50V
FILTER,RFI:22DooPF,SOV MITH FERRITE BEAD
04222
04222
04222
04222
04222
B0009
MA20SE1 04MAA
MA205E104MAA
MA20SE104MAtl
MA205E104MtlA
MA2DSE1 04MA1I
119-1762-00
A35CS2D
1135C522
A3SC524
113SC526
1135C600
1135C602
119-1762-00
119-1762-00
119-1762-00
119-1762-00
281-077S-00
281-o77S-OO
FILTER.RFI:22000PF,SOV MITH FERRITE
FILTER,RFI:22DOOPF,SOV MITH FERRITE
FILTER,RFI:22DOOPF,50V MITH FERRITE
FILTER,RfI:22000Pf,SOV MITH FERRITE
CAP.FXO,CER DI:0.1UF,20t,50V
CAP,FXO,CER DI:0.1Uf,m,50V
80009
BOO09
80009
BOO09
04222
04222
119-1762-00
119-1762-00
119-1762-00
119-1762-00
MA20SE104MAA
MA20SE104MAtl
1135C604
1135(606
1135C608
1135C610
1135C612
1135C614
281-0775-00
281-o77S-00
281-o77S-00
281-o77S-00
281-o77S-00
281-o77S-00
CAP,FXO,CER
CAP,FXO,CER
CAP,FXD,CER
CIIP,FXD,CER
CAP ,FXD,CER
CAP,FXO,CER
DI:0.1UF,m,50V
DI:0.1UF,2Dt,SOV
DI:0.1UF,2Dt,50V
DI:0.1Uf,m,SOV
01 :0.1UF ,2Dt,50V
DI:0.1UF,2Dt,50V
04222
04222
04222
04222
04222
04222
MA205E104MAA
MA2DSE104MAtl
MA205E 104MllIl
MA2OSE104MAA
MA205E104MAtl
MA205E104Mtltl
1135C616
1135C61B
1135C620
1135C622
1135C624
281-077S-OO
281-o77S-00
281-0775-00
281-o77S-00
281-0775-00
CAP ,FXD,CER
CAP,FXO,CER
CAP,FXO,CER
CIIP,FXO.CER
CAP,FXO,CER
OI :0.1Uf ,20t,50V
DI:0.1UF,2Dt,SOY
OI:O.lUF,2Dt,SOY
DI:0.1UF,2Dt,SOY
OJ:0.1UF,20t,50Y
04222
04222
04222
04222
04222
MII2D5E104Mtltl
MA205E104MtlA
MA205E104MAA
MA205E104MtlA
MA205E104MAtl
BEAD
BEAD
BEAD
BEAD
10·"
Replaceable Electrical Parts - 91S16,91S32
Coml22nent NQ.
Tektronix
Part No.
Serial/Assembly No.
Effective
DSSiQnt
A35C626
A35C628
A35C700
A35C702
A35C704
A35C706
281-0775-00
281-0775-00
283-0059-00
281-0775-00
281-0775-00
281-0775-00
CAP,fXO,CER
CAP,fXD,CER
CAP,fXO,CER
CAP,fXO,CER
CAP,fXD,CER
CAP,fXD,CER
A35C708
435C710
435(712
A35C800
A35C802
A35C804
281-0IT5-00
290-1084-00
290-1084-00
281-0775-00
281-0775-00
281-0775-00
A35C806
A35CR200
A3SOl120
A3SOl140
A3SOL 160
A3SOL1BO
Mfr.
Code
Mfr, Part No.
04222
04222
31433
04222
04222
04222
NA205E104MAA
MA205E104MAA
C330(105M5R5CIl
NIl205E104NAIl
NA205E104;.tAA
NA205E104MAA
CAP,FXD,CER DI:0.1UF,2O%,50V
C4P,FXD,ElCTLT:100UF,2O%,16V
CAP,fXD,ELCTLT:100UF,20%,16V
CAP,fXD,CER DI:0.1UF,20%,50V
CAP,fXO,CER OI:0.1UF,20%,50V
CAP,fXD,CER DI:0.1UF,20I,SOV
04222
80009
BOO09
04222
04222
04222
NA205E1QlOO1A
290-1084-00
290-1084-00
NA205E104NAII
NA205E104MM
NA205E10414AI.\
281-0775-00
152-0881-00
119-1891-00
119-1892-00
119-1889-00
119-1891-00
CAP,fXD,CER DI:0.1UF,20%,SOV
SEMICDNO OVC,01:SI,4A,30V
DELAY LINE,ELEC:5NS,1000HM,3 SIP
DELAY LINE,ELEC:20NS,INPUT 5O/0UTPUT
DELAY LINE,ELEC:10NS,INPUT SO/OUTPUT
OELAY LINE,ELEC:5NS,1000HM,3 SIP
04222
BOO09
BOO09
BOO09
BOO09
80009
NA205E104MI\I\
152-0881-00
119-1891-00
119-1892-00
119-1889-00
119-1891-00
A3SOL200
A35DL220
A350L240
A3SOL260
A3SOL2BO
A3SOL300
119-1890-00
119-1890-00
119-1889-00
119-1889-00
119-1889-00
119-1889-00
OELAY
DELAY
DELAY
DELAY
DELAY
DELAY
LINE,ELEC;5NS,INPUT SO/OUTPUT
LINE,ELE(:5NS,INPUT SO/OUTPUT
LINE,ELEC:10NS,INPUT SO/OUTPUT
LINE,ELEC:10NS,INPUT SO/OUTPUT
LINE,ELEC;10NS,INPUT SO/OUTPUT
LINE,ELEC:10NS,INPUT SO/OUTPUT
80009
80009
BOO09
BOO09
80009
80009
119-1890-00
119-1890-00
119-1889-00
119-1889-00
119-1889-00
119-1889-00
A350L320
A35J100
A35J102
A35J200
A35J202
A35J204
119-1891-00
131-3087-00
131-0590-03
131-3087-00
131-0590-03
131-0590-03
DELAY LINE,ELEC:5NS,1000HM,3 SIP
CONN,RCPT,ELEC:HEAOER,RIGHT ANGLE,2 X 17
TERNINAL,PIN:0.38 L X 0.025 SO,NO FERRULE
CONN,RCPT,ELEC:HEADER,RIGHT ANGLE,2 X 17
TERNINAL,PIN:0.38 L X 0.025 SO,NO FERRULE
TERMINAL,PIN:0.38 L X 0.025 SO,NO FERRULE
80009
22526
80009
22526
80009
80009
119-1891-00
679SO-001
131-0590-03
679SO-001
131-0590-03
131-0590-03
A35J206
A35J208
A35J300
1135.1302
435.1304
A35J306
131-0590-03
131-0590-03
131-3087-00
131-0590-03
131-0590-03
131-0590-03
TERMINAL,PIN:0.38 L X 0.025
TERJ4INAL,PIN:0.38 L X 0.025
CONN,RCPT,ELEC:HEAOER,RtGHT
TERNlNAL,PIN:0.38 L X 0.025
TERNINAL,PIN:0.38 L X 0.025
TERNINAL,PIN:0.38 L X 0.025
SO,NO FERRULE
SO,NO FERRULE
ANGLE,2 X 17
SO,NO FERRULE
SO,NO FERRULE
SO,NO FERRULE
80009
BOO09
22526
80009
BOO09
80009
131-0590-03
131-0590-03
679SO-001
131-0590-03
131-0590-03
131-0590-03
A35J308
A35J310
A35J312
A35J314
A35J316
435.1318
131-0590-03
131-0590-03
131-0590-03
131-0590-03
131-0590-03
131-0590-03
TERMlNAl,PIN:0.38
TERMINAL,PIN:0.38
TERNINAL,PIN:0.38
TERNINAL,PIN:0.38
TERNINAl,PIN:0.38
TERMlNAL,PIN:0.38
Sa,NO
SO,NO
Sa,NO
SO,NO
SO,NO
Sa,NO
FERRULE
fERRULE
FERRULE
FERRULE
FERRULE
FERRULE
BOO09
80009
80009
80009
BOO09
80009
131-0590-03
131-0590-03
131-0590-03
131-0590-03
131-0590-03
131-0590-03
A35J32O
A35J322
1l35J324
1l35J400
A35J402
A35L202
131-0590-03
131-0590-03
131-0590-03
131-3087-00
131-0590-03
108-1248-00
TERMINAL,PIN:0.38 L X 0.025
TERMINIlL,PIN:0.38 LX 0.025
TERNINAL,PIN:0.38 L X 0.025
CONN,RCPT,ELEC:HEAOER,RIGHT
TERMlNAL,PIN:0.38 L X 0.025
COIL,RF:FXO,BOUH
Sa,NO FERRULE
SO,NO FERRULE
SO,NO FERRULE
ANGLE,2 X 17
SO,NO FERRUI.E
80009
80009
80009
22526
80009
80009
131-0590-03
131-0590-03
131-0590-03
67950-001
131-0590-03
108-1248-00
A35L204
A35P102
A35P202
A35P204
A35P206
A35P208
108-1248-00
131-0993-00
131-0993-00
131-0993-00
131-0993-00
131-0993-00
COIL,RF: FXO ,BOUH
BUS,CONOUCTOR:SHUNT
8US,CONOUCTOR:SHUNT
BUS,CONOUCTOR:SHUNT
BUS,CONOUCTOR:SHUNT
BUS,CONOUCTOR:SHUNT
ASSEMBLY,8LACK
ASSEMBLY,8L1lCK
ASSEMBLY,BLIlCK
ASSEMBLY,BLACK
ASSEMBLY,BLACK
BOO09
22526
22526
22526
22526
22526
108-1248-00
65474-005
65474-005
65474-005
65474-005
65474-005
A35P302
A35P304
A35P306
435P308
A35P310
131-0993-00
131-0993-00
131-0993-00
131-0993-00
131-0993-00
BUS ,CONDUCTOR: SHUNT
BUS,CONOUCTOR:SHUNT
BUS,CONOUCTOR:SHUNT
BUS,CONOUCTOR:SHUNT
BUS,CONOUCTOR:SHUNT
ASSEMBLY,BLACK
ASSEMBLY,BLACK
ASSEMBLY,BLACK
ASSEMBLY,8LACK
ASSEMBlY,8LACK
22526
22526
22526
22526
22526
65474-005
65474-005
65474-005
65474-005
65474-005
10-12
Name &
Descri~tion
OI:0.1UF,20%,50V
OI:0.1UF,20%,50V
OI:1UF,+BO-20%,50V
OI:O.1UF,20%,50V
DI:0.1UF,20I,50V
DI:D.1UF,20I,50V
l X 0.025
L X 0.025
L X 0.025
L X 0.025
L X 0.025
L X 0.025
Replaceable Electrical Parts - 91516,91532
ComQ2nent No.
Tektronix
Part No.
Serial I Assembly No.
Effective
Oscont
A35P312
A35P314
A35P316
A35P318
A35P320
A35P322
131-0993-00
131-0993-00
131-0993-00
131-0993-00
131-0993-00
131-0993-00
BUS,CONDUCTOR:SHUNT
BUS,CONDUCTOR:SHUNT
BUS,CONOUCTOR:SHUNT
BUS,CONDUCTOR:SHUNT
BUS,CONOUCTOR:SHUNT
BUS,COHDUCTOR:SHUNT
A35P324
A35P402
A35Q200
A35Q202
A35Q204
A35R100
131-0993-00
131-0993-00
151-0809-00
151-0808-00
151-0807-00
307-0913-00
A35R102
A35R104
A35R106
A35R108
A35R110
A35R112
IlAfr.
Code
IlAfr. Part No..
22526
22526
22526
22526
22526
22526
65474-005
65474-005
65474-005
65474-005
65474-005
65474-005
BUS,CONDUCTOR:SHUNT ASSEMBLY,BLACK
BUS,CONOUCTOR:SHUNT ASSEMBLY,BLACK
TRAHSISTOR:NPN,SI
TRANSISTOR:PNP,SI
TRAHSISTOR:NPN,SI
RES NT"K,FXD,FI:(8)4.7K OHM,5t,O.12~ EACH
22526
22526
80009
BOO09
80009
80009
65474-005
65474-005
151-0809-00
151-0808-00
151-0807-00
307-0913-00
307-1186-00
307-1186-00
307-1186-00
307-1186-00
307-1184-00
307-1184-00
RES
RES
RES
RES
RES
RES
NTHK,FXD,FI:(4),2K,5t,0.12SH
NTHK,FXO,FI:(4),2K,5t,O.12SH
NTHK,FXD,FI:(4),2K,5I,O,12SW
NTHK,FXO,FI:(4),2K,5t,O.12SH
NTHK,FXO,FI:(4).8.2K-2.7K,5I,O.12SW
NTHK,FXO,FI:(4),8.2K-2.7K,5I,O.125H
80009
80009
80009
80009
80009
80009
307-1186-00
307-1186-00
307-1186-00
307-1186-00
307-1184-00
307-1184-00
A35R126
A35R128
A351<130
A35R138
A35R140
A35R142
313-0101-00
307-1186-00
307-1186-00
313-0102-00
307-0913-00
307-0913-00
RES,FXO,FILN:100 OHM,5t,O.166H
RES NTHK,FXO,FI:(4),2K,5t,O.12SW
RES NTHK,FXD,FI:(4),2K,5t,O.12SW
RES,FXD,FILM:1K OHM,5t,O.166"
RES NT"K,FXO,Fl:(8)4.7K OHN,5t,O.12~ EACH
RES NTHK,FXO,FI:(8)4.7K OHN,5t,O.12SW EACH
SOO09
SOO09
80009
SOO09
SOO09
80009
313-0101-00
307-1186-00
307-1186-00
313-0102-00
307-0913-00
307-0913-00
A351<200
A35R202
A35R204
A35R208
A35R210
A35R212
307-0493-00
307-0493-00
313-0101-00
313-0101-00
313-0101-00
313-0122-00
RES NTHK,FXO,FI:(7) SO OH~,5t,O.1~ RES
RES NT"K,FXO,FI:(7) SO OHM,5t,O.12SW RES
RES,FXO,FILM:100 OHM,51,O.166W
RES,FXO,FILM:100 OHN,5t,O.166W
RES,FXD,FILM:100 OHM,5t,O.166W
RES,FXD,FILM:1.2K OHM,51,O.166W
11236
11236
80009
SOO09
80009
80009
75O-81-RSO OHM
7SO-8HlSO OHM
313-0101-00
313-0101-00
313-0101-00
313-0122-00
A35R214
A35R216
A35R218
A35R220
A35R230
A351<232
321-0235-00
321-0121-00
315-o1SO-00
308-0849-00
321-0221-00
315-0102-00
RES,FXD,FILN:2.74K OHM,1I,O.12SW,TC=TO
RES,FXD,FILM:178 OH~,1I,O.12SW,TC=TO
RES,FXO,FILM:18 OHM,5I,O.2SW
RES,FXO,WW:30M OHM,10l,2W
RES,FXD,FILM:1.96K OHM,1I,O.12~,TC=TO
RES,FXO,FILM:1K OHM,5t,O.2SW
07716
07716
19701
BOD09
19701
57668
CEA027400F
CEA0178ROF
S043CX18ROOJ
308-0849-00
S043E01K960F
NTR25JE01KO
A35R234
A351<236
A35R238
A351<240
A351<300
A35R302
313-0101-00
307-1186-00
313-0101-00
131-3411-00
307-1185-00
307-1185-00
RES,FXD,FILM:100 OHM,5t,O.166"
RES NTWK,FXD,Fl:(4),2K,5I,O.12SW
RES,FXD,FILM:100 OHN,5t,O.166W
CONN,I ~"" "-
Test Voltage
,_~
1.1..)
3,Ql1 K / '
""16
•• ,•• ___ '., •• """ .....
Modi fi ed
Com ponent
(Depicted in Grey, or With
Grey Outli ne) - See Parts Ust.
DS9C2l
,
_ P
[R~~
I
Etched Circuit Board
Outlined in Black
Refer to Waveform - -
10Hl16
10115
"2 I
LJ
-~----.--
.p~~-
-
ex; signifies p,in No, 1
External Screwdriver Adj.
Shielding
Selected
value, see
Parts Ust
and Malntenan~e
Section
for
Selection Critena
..
<3>
Decoupled or Filtered
Voltage
Refer 10 Diagram Number
• COMPONENT NUMBER EXAMPLE
SYNC
Schematic Name
and Number
10136
10158(H)
10H161
10H164
10174
10176
10188
10209
10231
10474-8
10474-15
100151
100164
74F02
74HC04
74HC125
74HC138
74LS139
74HC154
74HC174
74LS175
74HC245(LS)
74HC374
AN6913
F10016
LF412
MBM27C256-30
MC10H016L
NE5018
uPC339C
uPC393
Vee or Voo
1,16
1,16
1,16
1,16
1.16
1.16
1,16
1,16
1.16
1,16
1,16
1,16
16
1,16
1.16
1,16
1,16
1,16
1,16
1,16
1,24
1,24
6,7
6,7
14
14
14
16
16
24
16
16
20
20
+6V 1,9
1,16
+12V 8
28
1,16
+12V 19
+6V 3
8
GND
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
12
12
18
18
7
7
7
8
8
12
8
8
10
10
5
8
-12V 4
14
8
-12V 17
12
4
:iE
91S16·91S32 Service
~
II:
o
,-------
~
C
~
(,)
o
...J
III
...
...en
CD
I
en
---- ------
TRIGGER
OUT
START
SETUP
QUALIFY, INTERRUPT
P6460
EXTERNAL
CONTROL
PROBE
I
II
----'
j--v
I
I
I
I
@-I
r--
I--
E~
PROGRAM
COUNTER
I--
.-- r--
'"
P6460
EXTERNAL
CONTROL
INPUTS
V-
r
~
PC CONTROL
MULTIPLEXER
AND RESET
1
K:=J
EXTERNAL
SIGNAL
LATCH
----
v---
.
r--v
I--
I VECTO~
VECTOR AND
MICRO-CODE
MEMORY
r-------v
PATTERN
SELECTOR
(1)
I
~
~
,
..
I
I
'"
REGISTERS
A, B
MICRO-CODE
~
~
PATTERN
SELECTOR
(2)
"
V
r-r-
~
~
FIRST
LATCHES
...
r-----v
.-----
VECTOR
OUTPUT
LATCHES
"-
I
r-
...
INHIBIT
CONTROL
(2)
I
TTL
START
INPUT
f---
~
~
.
-
L_
INHIBIT
CONTROL
(1)
CLOCK
POSITIONING
.
~7
~
t.-
,......
INHIBIT~
CLOCK
LINE
f---
I
I
I
P6464
PATTERN
GENERATOR
PROBE POD B
I
L..-
.
V
I
.
EXT CLK, PAUSE
CLOCK
CONTROL
P6464
PATTERN
~ GENERATOR
PROBE POD A
~
II
I--
STACK
I
A
ADDRESS"
I-
I
P6464
PROBE
INTERFACE
P6460
PROBE
INTERFACE
I
<
..
I
[ICRO-CODE
I
I
@
,
,
,
I
P6460
DAC
THRESHOLD
-,
------ ------ ---- ---- --- --- -- - ---- ---- -- -- - - -- ---
91S32
TRANSCEIVER
I
""Zi>-
I
.
I
91 A32 INT ClK
91 ADS INT ClK
LV-~
91S32
CLOCK
DAS
CONTROLLER
INTERFACE
AND ROMS
.
- - --------- - - -
/).
--- - - - --- -- - - - - -
.
¢=;
STATUS
READBACK
,
.
I
+3V
POWER
SUPPLY
----------
I
'SETTING
"READBACK
I
__J
"(7
HIGH SPEED BUS II TO 91 S32
'" 7'
HIGH SPEED BUS I
"
...
A
~
CPU BUS
"
5397-62
Figure 11·1. 91S16 Block Diagram.
91816-91832 8ervice
r------I
LOOP
COUNTER
I
-=>
>-«
I
I
HIGHSPEED
ADDRESS
BUS
BUFFER
•
FREE
RUNNING
ADDRESS
COUNTER
"1/
ADDRESS
MULTIPLEXER
>--
PAGE
CONTROLLER
~
r--
r-
r-V'"
I
OUTPUT
LATCHES
& DRIVER
I
I
I
r
«
I
'<.7
I
~
CLOCK
DISTRIBUTION
--V
I--
RAM
WRITE
DATA
READBACK
I{O
CONTROLLER
~>.
I
V
~
PATTERN GENERATOR
PROBE A
9-PATTERN CHANNELS
1-CLOCK
«
PATTERN GENERATOR
PROBE B
9-PATTERN CHANNELS
1-CLOCK
*
~
~
'"
v'
CONTROL
LINES
TO ALL
91S32
BLOCKS
WITH *
•
«
~
I
-
.
~
v
I
-
I
L- -
VECTOR
RAM
....
,.---y
I
I
I
.
~
~
/":0.
I
ADDRESS
READBACK
"
1/"
*
I
I
----,
I
- - - --- - - - -- ----- -- - --- ---
PATTERN GENERATOR
PROBE C
9-PATTERN CHANNELS
1-CLOCK
*
PATTERN GENERATOR
PROBE D
9-PATTERN CHANNELS
1-CLOCK
*
CLOCK
DELAY
*
--------
------ - --
-- ----
I
__ ...1
HIGH SPEED BUS II
<
<
~~
HIGH SPEED BUS I
'-...7
CPU BUS
Figure 11-2_ 91832 Block Diagram.
5397-63
A34 91S16 PAT. GEN. BD.
& COMPONENT LOCATIONS
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CLOCK CONTROL CIRCUITRY
CIRCUIT
NUMBER
CR240
OL240
OL280
OL290
J140
J140
J160
P1
P1
P1
P2
R180A
R258A
R2580
R258E
R260B
R260C
R260F
R264A
R264B
R264C
R2640
R264E
R264F
R264G
R266A
R270
R272
R274
R276
R282
R284
R286
R350E
R350F
R3600
R360E
R362C
R364A
R364B
R364C
R3640
R364E
R364F
R366A
R366B
R3660
R368E
R368F
R450C
R460C
R4600
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BOARD
LOCATION
CIRCUIT
NUMBER
B1
E5
B2
E5
A4
R4700
R470E
R472B
R4740
R572F
R666A
R666B
R6660
R8180
R8500
R852C
TP200
TP240
TP280
TP980
U134E
U134F
U200B
U200C
U206
U208A
U208B
U210A
U210B
U212A
U212B
U214A
U214B
U216A
U216B
U218
U222A
U2220
U230B
U230C
U250A
U250B
U300C
U3000
U302A
U302B
U316B
U4220
U638B
U640C
U704B
U716A
U820C
U954B
U956A
U956B
A4
A2
A1
A3
A4
A2
F4
B1
A3
A4
05
05
A2
A3
C3
04
C3
C4
C4
04
F4
F1
A1
B1
B1
B1
B2
B2
B2
F5
E5
01
B2
E1
C2
B4
B4
B3
02
C1
03
C3
03
B2
E5
E3
F4
F4
B3
B3
B3
A3
A3
A4
B4
B4
B4
F1
A4
B3
B3
B3
B3
B3
B3
03
03
03
03
03
03
03
F2
A4
B4
B4
B4
B4
B4
B4
C3
C3
B3
B3
04
B3
B3
B3
B3
B3
B3
E3
E3
E3
B4
B4
E2
E2
E2
SCHEMATIC
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04
04
04
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03
03
B2
B3
B3
C3
F2
F2
I
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Ie Pinout. (Vee &. Gndl·
CLOCK CONTROL CIRCUITR'Y
1j}
A
c
B
D
E
F
Table 11-4
EXTERNAL SIGNAL CNTL. AND DAC THRESHOLD
~
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BD., ASSY. A34
CIRCUIT
NUMBER
C322
C330
C360
C370
C372
C374
C376
C378
C380
C382
C384
C386
C388
C390
C394
C396
C398
C782
C788
C790
CR320
CR340
OL310
OL320
J100
J120
J140
J140
J140
R2588
R25BF
R258G
R260A
R260D
R268C
R268D
R268E
R268F
R3508
R350C
R350D
R360C
R360F
R360G
R362A
R362E
R366G
R368A
R3688
R368C
R3680
R370
R372
R374
R376
R378
R380
R382
SCHEMATIC
LOCATION
BOARD
LOCATION
CIRCUIT
NUMBER
F2
F2
F4
05
E5
E4
E5
F5
F5
F5
F5
E4
F4
F5
F2
F2
F2
F3
F3
F3
E4
F4
82
81
F3
F3
F2
A1
F4
A1
A1
03
A2
A2
E2
02
02
E1
03
C2
C1
01
C1
C2
02
C4
01
C2
C2
82
82
05
E5
05
E4
E5
E5
F4
A3
A3
84
C4
C4
C4
C4
84
A3
A3
R384
R386
R388
R390
R392
R466C
R474E
R474F
R474G
R482G
R5788
R578C
R5780
R578E
R666F
R684F
R818E
R818G
R870A
TP300
TP320
TP360
U200A
U2000
U230A
U232A
U2328
U300A
U3008
U3020
U302E
U302F
U304A
U3048
U306A
U3068
U308A
U3088
U310A
U310B
U312A
U312B
U314B
U316A
U316C
U320
U322A
U322B
U324
U330A
U330B
U332A
U332B
U332C
U3320
U334A
UB02A
U820A
A4
84
84
A4
A3
A3
A3
A3
A3
A3
84
84
83
84
A1
A2
A3
A3
A3
83
83
83
83
83
04
04
04
04
C3
C3
C3
83
83
83
04
04
E3
84
84
84
84
C4
C4
C4
B4
84
84
84
RESET______________________________________________________________________________________________ 8
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C5
C4
C5
C4
85
84
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84
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82
C1
E3
F4
F5
82
81
81
C4
B4
85
B1
81
C3
C5
C4
85
84
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02
03
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85
B2
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F4
F4
C1
C2
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C5
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84
84
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i
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A
c
B
D
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PC"'~
Table 11-6
VECTOR & MICRO-CODE RAM CKT.
CIRCUIT
NUMBER
P2
R266B
R452
R462E
R462F
R462G
R466B
R466F
R466G
R470A
R480A
R480B
R480C
R4800
R480E
R480F
R480G
R482A
R482B
R482C
R482E
R560
R562
R564
R566
R568A
R568B
R568E
R570C
R570E
R570G
R572A
R572B
R572C
R574B
R574F
R576C
R5760
R576E
R576F
R576G
SCHEMATIC
LOCATION
F1
04
B1
B2
B2
B2
05
05
E5
B3
F2
F1
F2
F2
F1
F1
F1
F2
F2
F2
F2
B3
B4
B4
B5
02
02
02
E1
E1
E3
03
04
04
F4
F4
E4
E3
E4
E4
E4
BOARD
LOCATION
F1
F2
01
01
01
01
F2
F2
F2
03
E1
E1
E1
E1
E1
E1
E1
F1
F1
F1
F1
E3
E3
E4
E4
C1
C1
C1
C2
C2
C2
F2
F2
F2
B1
B1
C2
C2
C2
C2
C2
~
-- 91S16 PAT. GEN. BD., ASSY. A34
R5800
R580E
R580F
R580G
R590
R592
R658C
R658E
R660C
R660E
R664C
R664E
R668B
R6680
R668G
R676A
R676B
R6760
R678C
R8740
U224B
U224C
U422B
U426
U428
U430
U500
U502
U504
U506
U508
U510
U512
U514
U516
U518
U520
U522
U524
U530
U532B
SCHEMATIC
LOCATION
04
04
03
04
B5
B5
E2
E2
E1
E1
E2
E2
02
E3
01
01
01
01
E3
A3
F4
F4
B3
F1
F2
F3
A3
A4
C1
C2
01
02
03
04
05
E3
E3
E4
E5
A1
A2
F2
F2
F2
F2
E4
E4
C2
C2
B2
B2
C2
C2
C1
C1
C1
C1
C1
C1
C1
E4
SPCI
I
5
a
SPCI
3 I
14- SPcz.
4 I
SPC3
"l
A3
PC3
~
3 SPC3
5
SPC4
8
A4
7
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7 I
4
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spes
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pes
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ALL RESISTORS AF1I.E. loon " ..... LUE.
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ED3
to O't4 oO>'.j-=2__.c.M
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3
PAGE
AI21
VB6
3
USCG
TD¢-TD7
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8
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15
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1 1.3K
1'2..'7K
13 0
II
IL
5
j
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_____ _
10
R 5Si,.o;,.~1
, A23 A2 R1234 '
IA:::~: .....JTT~sCh,m","
MeB
L'Cncur'
Subilss~mblv
(of used)
~E~0='=-~2C::, 0 L 4- D04FZ__-'.Mc.C=".:.j
Number
lIurll~el
+3V
CS:,H 1"7 E5
'~-I
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I'I_J~~...'.:'fc~
CS4n cs
I'=E.:.D~4'-:.:'8"1 01 I DO \ r2.~2,--_M-=-C__'O-+,,"',--'-~-E~-~--1-:
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tc
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tv\C13 71
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rCODE MEfoAORY
DAS 9100 SERIES
I
4
3
3
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t: INH
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HMI0414-S
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Me 17
J
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V-________-"M.::C==~_-_M~C::."___ \9~
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COMPONENT NUMBER EXAMPLE
HMl0474-E!>
E04
~.cw=<,----,
U50t
~
tSV
I
-~--~~~~~-~~----~
I-f
7
II
loC
E QZ
TD3
TOS
02
02
02
02
,
I
74.LS24S
I
9
3
TD2
E3
E4
01
01
01
E2
02
02
E2
E2
-,
II
US5'2B
2
-
+3V
U504
hs~p:.C¢~~..:.r;,,~¢'--l wU - - -
PC2.
q , -_ _-;'0'108
C2
C2
E2
E1
F1
F1
E1
I
PCI
pes
BOARD
LOCATION
+3\1
,00
2. 1- -
IS SPC¢
VP~C:_:4:__-'~Di-
CIRCUIT
NUMBER
R4-S2.
pA~E,
U4-[",
tV:\ Static Sensitive Devices
\Z::I See Mamtenance SectIOn
Pjo
A34
Q\SI0
PATTj:RN
S3~(
GENE.RATOR
- 105
¢
<5J?
~----------------__M__C:c'__0=_. . ~q
' -______________-'AA~C=_.7~__ ~
NOTE: Table 11·1 shows
IC Pinout. (VeC & Gnd).
BD.
VECTOR
$
MICRO-CODE RAM CIRCUITRY
~
A
+-sv
I
-T1 u.t:
1
I
+3\)
CIRCUIT
NUMBER
C106
C108
C110
C112
C114
C116
C118
C120
C122
C124
C126
C128
C200
C204
C208
C212
C216
C220
C222
C228
C258
C264
C342
C346
C500
C502
C504
C506
C508
C510
C512
C514
C516
C518
C520
C522
C524
C526
C570
C574
C578
C602
C606
C610
C614
C618
C622
C626
C630
C634
C638
C662
C666
C670
C676
SCHEMATIC
LOCATION
BOARD
LOCATION
63
63
63
63
63
63
63
63
63
63
63
63
61
61
61
61
61
61
61
61
A1
61
F4
F4
E4
C4
E4
C4
E3
G4
G4
A4
A4
A1
A1
A1
A1
A1
63
64
64
64
64
64
64
84
64
A1
84
64
83
63
63
63
63
63
63
63
63
63
63
63
63
63
A4
G3
G3
F2
E1
E2
04
C1
C3
61
61
A2
61
64
64
E2
C1
C3
63
61
C2
01
02
03
04
E3
E1
E2
C1
03
A1
A2
A3
63
64
63
C3
C3
03
E4
F1
F1
E4
E2
01
E2
CIRCUIT
NUMBER
C680
C702
C706
C710
C714
C720
C760
C762
C764
C786
C800
C802
C804
C806
C808
C810
C828
C840
C900
C902
C904
C906
C910
C912
C916
C960
C964
C966
C968
C970
C976
C986
C988
C990
C992
C996
CR700
CR720
CR960
OL700
OL720
OL740
OL760
OL780
J100
J120
J180
L952
L954
PO
P1
P2
0720
0722
0950
~
02
C2
C2
C1
C2
C1
62
63
61
A4
A2
62
A1
A1
A1
61
C5
C5
61
C3
E1
E5
03
03
F1
F4
F4
61
61
A4
A3
A5
65
65
A2
A4
A4
A4
G2
61
61
61
61
61
A1
A2
A4
G2
G1
E4
64
F1
64
64
G1
~~~~~~
CZ.22.~ SuPPLY
c'Z.o8
c2.2~
C'2I2.
C'21 (0
C'2:(p~
CIRCUIT
NUMBER
'SY
0952
0954
R352A
R3606
R368G
R760C
R7600
R760E
R760F
R760G
R762
R764
R766
R770
R8186
R950
R952
R954
R956
R958
R960
R962
R964
R966
TP700
TP720
TP740
TP760
TP780
TP860
TP910
TP930
TP940
TP950
TP960
TP970
TP990
U2228
U222C
U700A
U700C
U702A
U702C
U704A
U7040
U706
U708
U710
U712
U714A
U7146
U714C
U7166
U980A
U9806
A2
62
E2
65
65
C2
E1
02
02
E5
65
C5
C5
65
E4
62
A1
A2
A2
A2
A2
62
A2
62
E2
E1
E4
E5
F1
G1
G1
61
63
64
62
62
62
62
82
64
A4
A4
A3
A3
A3
A3
A3
A1
C5
C5
02
C3
04
03
E2
E4
F1
F2
F3
F4
E1
E5
E5
65
A2
A2
I
"7
A4
A4
62
62
62
62
62
62
61
A1
62
A2
62
62
62
63
G2
G2
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QI
QI
\JB14
COMPONENT NUMBER EXAMPLE
By
AI-I.. 8
PINS
61-62.0
.
13
,
74FOZ.
..I _ _ _ _ _ _ _ _ _---'~.s~?j--~
"'-.1.:5 ~
R,jO
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r - --,
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L _
4
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z.
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• . -__R"""=7""'_Ic...
-....rq r ~...,...
...
® Static Sensitive Devices
See Maintenance SectIOn
r _ -,
~
~
~ ;~~~':r
SulJimemblr
Number (lfuleJ)
ChaSSls'mountedcQmpo~entshovenuk;semlJl\'Number
prefix-see end ot Replaceabie Eledricol PartsL,st
21
~, M~ ~CR7aOl
'~¥R1234'
J • ~S(;h~maIiC
-.
NOTE: Table 11.1 shows
____________________
'" DZ
~'i.;cB~I~S--,17-1
Component Number
U222B-?C
AIS
AlB
I
C:,:H.::3:.....t-:.'''''_4
Q4p.z=-____________c::
1
5
p-"o-________________.::C::.H~Z~~9~
\/BII e D4- Q41-3"-________;C~H='3"-+_"":....."
H,
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10
{"TP 8iCO
U704D
lOHIOZ.
t;lL.B¢
OS
+3V
U 70ZA
\OO,rF
AS
64
Q¢~I~"----~B-'~N~H~'B~I~T~~
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QI ~'O~______________~C~H~G7~~a~~
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,
~
15. Ot
~'~__
' +-____- .____________~I~
4
ze"
vee
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/ A<
CHB
C"7(.oO
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A3
I
V84 1'4 o¢ Q¢ ~1_:3:----------------.:;C;;,H~4,;,...+'_::44
+3Y
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7100
R7f>OE
laO
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f-''l_____________C::,:,;H~',-j_
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CH8
2.6
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30
TPfbO
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__ 7
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ve.s I "IIj
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IOHltCo
2-2.
NC (
7
~~~~'C~P~;"~'"~'.~(V~C~C~'~G~"~d)~'~~~~~~~~~~~~~~~~~~~~~~~~~~~C~L~K~S~E~N~5~E~~.~~·~3~~;~~il
+5\1
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Pjo
DAS 9100 SERIE.S
18
q" ~9----------------__;C~H~w;-~e~l~
Q"
+3~
II
p-'O=-________________~C:,:H~S:.....t-:.'7~~
A34-
<:?ISI~
PATTE.RN
539?-107
GENERAiOR
BD.
OUTPUT DATA ~ C.LOCK CONTROL C.IRCUIIR.Y
SYNC. P0LSE
~OR.
.sC.OPE
c
B
A
D
F
E
+3V
1R"",,,,o,
U30'Z.C
~ ~F~"~A~T~C~H~S~T~E~P_C~L~K~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _7_.~,~'>o4~'-B-B---~Bl.~-'-o-o--_____________________~F_~L_A_T_C_~_~~-~L~K~_..~~
1
+3V
I
CLOCK L.INE
"
UB-ZOB?O
IOHIO.q.
Table 11-9
CLOCK & SETTING CONTROL
CIRCUIT
NUMBER
OL800
OL820
J100
J120
J140
P2
R258C
R260E
R364G
R466A
R666G
R672E
R6840
R684E
R7606
R818C
R818F
R854
R856
R858
R860
R862
R864
R866
~
-
91S16 PAT. GEN. BD., ASSY. A34
SCHEMATIC
LOCATION
BOARD
LOCATION
CIRCUIT
NUMBER
01
C1
F2
F2
A2
F2
A2
A2
62
C2
01
C2
01
C1
E1
C2
62
04
63
64
64
65
03
04
C3
C2
A1
A2
A3
F1
63
63
63
F2
E4
A2
C3
C3
62
62
62
04
04
04
04
04
04
E4
R86a
R870
R872
R874
R876
TP800
U210C
U302C
U430C
U800A
U8006
U8000
U8026
U802C
U8020
U804
Ua06
U80a
U810
U812
U814
U8206
U8200
SCHEMATIC
LOCATION
05
F3
F4
F4
F5
62
62
01
C2
C2
62
C2
C1
01
01
A3
A5
C3
C5
E3
E5
B2
B2
BOARD
LOCATION
2
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F3
F3
TF'BOO::,
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\:t::I See Mamtenance SectIOn
91510
PATiE.RN
~
Ch<,,,,,,,,,,,,l,dcuop",, .1'
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p,elI!-'" end oj Hepl""DI. ,."tl
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17 0
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START ~E-r
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COMPONENT NUMBER EXAMPLE
"TOI
SEI..3
PC INCR
PC S,E.T
t.,.,,"
S~
Z.7K
311.3K
j
q ~ N.C.I
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NOTE: Table 11-1 shows
Ie Pinout. (vee" Gnd).
BD.
CLOCK ~ 'SETTING CONTR9L CIRCUliRY
A
c
B
o
F
E
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__R~E=A~O=-~S~T~A~T~U~S=-~=-A~T~E=-____________________,
1
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~
-
~
Mer/; - Me 3,
kS:.
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Table 11-10
___
C-'-'F_'_I_N_H_A+_~o;t-
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CIRCUIT
NUMBER
R940
R942
R944
U900
U902
U904
U906
U908
U910
U912
U914
U916
U918
U920
U922
U924
SCHEMATIC
LOCATION
B5
B5
F3
A5
E4
E4
E5
B2
B3
B3
B4
B2
B3
B3
B4
C2
BOARD
LOCATION
CIRCUIT
NUMBER
F4
F4
E3
F4
U926
U928
U930
U934
U936
U938
U940
U942
U946
U948
U950
U952
U958A
U958B
U960
F2
C2
B2
A2
A2
B2
A1
A3
B2
A2
A2
SCHEMATIC
LOCATION
C3
C3
C4
04
02
03
03
04
E3
E2
E1
E1
C4
E3
F3
BOARD
LOCATION
2
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7
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See Mamtenance SectIOn
SIiOossembly
Numli€r (If used)
c~'Tlp(Jne~1s
prellx-sep.
01 Replaceable ElecUical Parts list
en~
have no
Number
Chass,s-mounted
~s,errbly
NUrlber
NOTE. Table 11·1 shows
Ie Pinout (Vee & Gnd).
PATTERN G'E..NERATOR. BD.
5"397 - log
READ
STATUS CIRCUITRY
~
A35 91532 PAT. GEN. BD.
& COMPONENT LOCATIONS
CIt
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I
B
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R 312
"I
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U510
"I············
02E[[[J
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U626
U620
.
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o:::?II2:J
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-I
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ru
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8
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PROCESSOR INTFC_ & ClK_ CNTL
-
U200
1
Table 11-12
A¢
91S32 PAT_ GEN. BO., ASSY. A35
10
A1>
I'---~=_z_..:B=_
OL120
J202
J204
J206
J208
P1
P2
P2
P202
P204
P206
P208
R200A
R2008
R200C
R2000
R200E
R200F
R200G
R202A
R202B
R202C
R2020
R202E
R202F
R204
R234
R236A
R238
R240
R326G
R332E
R332F
R334E
R334F
R336E
84
85
85
E2
F2
A3
F3
A5
85
85
E2
F2
C3
C4
C4
C3
C4
83
03
E4
03
04
04
E3
E4
B3
84
84
C4
C4
C5
B5
85
E3
F3
E3
C4
F1
F1
F1
F1
B4
F1
F1
harmonica
harmonica
harmonica
harmonica
01
01
01
01
01
01
01
E1
E1
E1
E1
E1
E1
84
84
82
C4
01
E3
F2
F2
F2
F2
F2
R336F
R402G
TP200
U110
U120A
U200
U202
U203
U2048
U204E
U206
U208
U210A
U210B
U210C
U2100
U212A
U2128
U214A
U214B
U216A
U216B
U216C
U2160
U218A
U2188
U220A
U2208
U224A
U2248
U226A
U2268
U226C
U228A
U2288
E3
04
F3
E1
A4
81
C1
01
02
C2
B2
84
E4
E4
83
03
03
04
03
04
C4
83
83
C3
E4
E4
C5
E3
E5
E4
83
C4
84
E3
E3
F2
C2
E1
G4
82
G4
G3
l33
G4
G4
G3
C4
E1
E1
E1
E1
E1
E1
01
01
01
01
01
01
E1
E1
F2
F2
E1
E1
B4
84
84
F2
F2
00
~A:..."'-,-_",-,
A4
~"=S_..:S:.j A5
t'--'Ao,-,-_"'-I
AW
\1
De
f--:,,--0-'1,
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t'--'''5=--....:5-1 AS
t'--'A"'
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0"'1-'_"'__0:.. "'-1
t'--'A7-'---'-"=-1 A0
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2
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163
184
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4
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0
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24 Aq
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583
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04
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17
05
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03
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05
05
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07
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13
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603
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20
10
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U204 E.
U204B
74l.504
'------'
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MSM2{C2.5~-30
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0203
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I R200~
3
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R200D
50
.----.--10 5
50
~
R202B
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PC
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4_,L>_3.3ts____~=-------------!j---------j--------------------------------------___________________....::~~..
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_
D~LK 1
LA _
U220~8
BV
HALF CLK: J\ <@>
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r ~
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2
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100 J2.04
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.. ,3.V
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f--t---;:5'FP'_.
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63
63
63
B3
B3
B3
B3
B3
B3
B3
B3
B3
A1
B3
B3
B3
B3
63
63
B3
B3
B3
B3
B3
B3
C1
C2
C3
C2
E2
E2
E4
E4
E4
E4
E2
E2
E4
E4
E4
E4
E1
E1
E1
E3
E3
E3
E3
E1
05
65
C1
65
64
~
U30"
r--i---------t-t-~~S~"~~~~';rpp¢~(Q~¢~~3~~p~s~¢~I+--~.~0~¢0¢¢-l'0'
:10
'B
J302
J304
J306
J308
J310
J312
J314
J316
J318
J320
J322
J324
P2
P302
P304
P306
P308
P310
P312
P314
P316
P318
P320
P322
P324
R300
R302
R304
R306
R308A
R3086
R308C
R3080
R308E
R308F
R308G
R308H
R310A
R3106
R310C
R310E
R312A
R3126
R312C
R3120
R312E
R312F
R312G
R312H
R316A
R316A
R316C
R3160
R316E
R316F
R316G
R318
R320A
R3206
R320C
R3200
R320E
R320F
R320G
COuNT
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1'3
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0320
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R.ASA
F'A",A
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14 R06G
=ft>- -+"':"':--=-=1
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4
13 RDB,
U334
R.31i4>F
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100 ...,
-"Nv----<
RDB¢
R3~SB
2.; - I
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+3V~
1
1
3:
I
I
1
COMPONENT NUMBER EXAMPLE
5
<€P
PAG,B
4
r,h"''''-m""~t"(. compn~ents have no Assemtly
PTefIX-,"C ~"u ~I Riiplocl'able E'eclne,1 Pari,
Number
U,t
I
P3
q:. f"-:-'_1-1-1--1~--':....'.'-.;;F~
q4 j.:'-:-"--1'-1--1-1-+~~~'....;;E'.-J
D4
QS ~
L -
AI5
I
r-______~~~~~~3~------W=A~I..
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6 PINS
81-6<::0
,.....__~'+ !:D-F"___.:::W::::A2. . <€9
r-__---='~o~t~+='3'-------w~A~'..
I
1
'
r----='.:.;'~~~_~''-~-------'-~'-A+~J
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R402.A
U410
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IOIQ"7
5
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7
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:
100\(0
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3
10110
,
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P-__
7 :-D
'--+-'-------~'-I~--------------
'0
~
~
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4-
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II
I
WB4
'i~.-t-::-'4---:::::;~~
WS3
r"
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L-______________________________________________________
~+3"
IOHI03
7
+-H-++_-'S=-j_ -r '0F2 _______""=B¢.1
.
U40B
~
r:; -p~--+4=-----+-+-+-+------------
O
C4,5",=,
C4B8
C4~2.
c4'90
C404
C40G::.
C40e,
~
A,
.,
At
CSDC
c soe.
C42.8
C42.G:>
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,OHI03
4
~
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~ -.-0
2
WA¢
.-__________
""15
_ ~.
. +"---------'=
..'
4
2
PC
" , - _ - . , \C\qj
U400
j\:..ID::.2~.:.;'0:.j P2
1"-1D:....___
'
PIG
U'l-OZ
U400
~
F
R,.o,.04
""rD::.',-_":.j P'
E3
E4
C3
83
04
82
C4
C4
C3
04
04
E
r-______________________________~--'O-O------~T~'~B~O=F~F~/o-~N~~
1ViWRN\
BOARD
LOCATION
E1
G1
G1
G1
G1
G1
G1
G2
G1
G1
E4
E4
E4
E4
E4
C2
C2
C2
C2
C2
C2
E2
E2
02
02
02
A1
A3
03
E1
E3
G1
G2
F2
E1
84
G1
G1
E4
E2
C2
C2
C2
C2
C2
F4
E2
C2
C2
C2
E2
E2
02
o
WP
<@9{
Tabl~14
LOOP COUNT
c
B
l{
J T
0.\
0.1
1
-I-T
:
c, '\CiDOra CCOIIO
C0ZZ. T'OOJ.lI" L _
CG.E4 ~. I
Z
CiDO& C""'i3
Cf&,2.8
c",oz.
eCoze:,
Be
:c..S2.0
_I
,02.2
I.JC400
'(co "lIZ.
CiNO
51"1-
AS
.s
C 51(0
7
P¢~
t,V
.
c-ZOG
JIOO;"'+
TP080
COMPONENT NUMBER EXAMPLE
Component Number
5
OW4
I
~TA.2 R1234 \
Assembly __ J
Number
--':S0emavc
Sub.,,'embly
Number (Ii USo(r)
R.z.2.0
.0"
IV:\ Static Sensitive Devices
NOTE:
I
START/STOP
CIRC.UITR"f " ]
PIO
DAS '1100 SERIE.S
A3S
~IS32.
PATTERN
GENERATOR
'lEE
AND
PIN 8
U"'tO"T
\J::J/
CF" U400) 0412, U4',4) U41(o)
ARE CONN~CTEC TO ~ND2..,
so..
LOOP COUNT
$
See Mamtenance Section
NOTE: Table '1-1 shows
Ie Pinout. (Vee &. Gnd),
RAM
\NRITE
CONTROL CIRC\)ITR'{
~
A
c
B
o
I
E
I"'
PIC
CLOCK
,J"',OQ
AnA,,,, CLOCK
DATA
CL.t<
UI,-OB
~_ _~74I-SZ<:l,"t
1
Ta~1-15
CLOCK OUTPUT & PROBE INTFC. ~ -
91S32 PAT. GEN. BD., ASSY. A35
RSOZG
100
BCLK
CIRCUIT
NUMBER
OL140
OL160
0L180
OL200
OL220
OL240
OL260
OL280
OL300
J100
J100
J100
J200
J200
J200
J300
J300
J300
J400
J400
J400
R142C
R142E
R142G
R500A
R5008
R500C
R5000
R502A
R5028
R502C
R5020
R502E
R502F
R502G
R504
R506
R508
SCHEMATIC
LOCATION
81
81
C1
C1
01
E2
E2
E3
E3
F4
F2
F1
F4
F2
F1
F3
F1
F4
F4
F1
F3
F1
F1
F1
E3
E3
E2
E2
03
03
C4
81
C2
81
A1
82
83
83
BOARD
LOCATION
02
02
C1
02
02
81
81
C1
C1
A1
A1
A1
A2
A2
A2
A3
A3
A3
A4
A4
A4
82
82
82
81
81
81
81
02
02
02
02
02
02
02
02
02
02
CIRCUIT
NUMBER
R510
R516
TP500
TP520
TP540
TP560
TP580
TP600
TP620
TP640
U1208
U500A
U5008
U5000
U502
U504
U506
U508A
U5088
U508C
U5080
U510A
U5108
U510C
U5100
U512
U514
U516
U518A
U5188
U518C
U5180
U520
U522A
U5228
U522C
U5220
SCHEMATIC
LOCATION
84
85
F2
F3
F3
F4
F2
F2
F3
F3
F1
C1
C1
82
02
03
03
E2
E3
E3
E4
E2
E2
E3
E3
A2
83
04
81
81
C1
01
C4
E4
E5
E5
E4
BOARD
LOCATION
U5\BA,B
OLl"l-O
IOh101
\,1052110
0-201\S
8"'"
,
A4
82
02
02
02
C1
01
01
C1
C1
C1
C1
r
I
~ _~
L-._-,-!' __
r-;;>-""1
\00
ID!=
L _ _ _I
OL',(,O
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1
163
17
0
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R500B
100
100113
Iq
4
TH
Pia
J~
iPCo20
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•
2-9
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I,OC
U522A
PIO
~'.;_----_+-----""------------------------------..:.----~3~'~
J~
q~5~-------+-r----~----------------------------------------------------------~3~'~,
q_9
__________t-t-____-r________________________________________________________________
-r
U522D
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rv~~~~------------------------~~~
, A23 A2 R1234 '
.. " IT+ :___ Schematic
STOP GATE.
~_________________________________________________________________________________________________________________________S=~~S~C~L~K~~}~
CMssis-mDun\ed comoooents have no Assembly Number
prefl~-sce end of Replaceable Electrical Part, List
1etc
IV:\ Static S~nsitive Oevices
\Z::I See Maintenance SectIOn
A"35
~\S3'2.
PATTERN
GENER.ATOR
J~
~/O J400
3'
2~
I
P/O
J~,
JZO
G! ~'::.s_ _ _ _ _t_------.....,~---------------------------------+2:'S~
Component Number
OAS glOD SERI ES
,
fa
COMPONENT NUMBER EXAMPLE
Circwl
Number
~~
L----,~--------------~~~~-+LA~-~
USOS5
10'"\5
13
I
w-;-;'
SVD.sse~bly
30
oA
,-____~2.~.~;>3=--7;.:4~H~C~'.::Z.::s------------------------------------------O~A~T~A~~ ~
IB,4 11- 0
Number (!fused)
~
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3"
--v
"
Number
~
'--'1
'+,7K
L.C.LK¢
IOHIOI
YOSIIO
7.q..HC374
15"1-
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2.B "
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7
10
: RSIO
4
5
J~
J400
I"
,..5V
BCLOCKIN
12.L_ _.......J~
_R_,'.;~;.)';~2..:~i.______;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;~P:D=.,:j'~3
fS: ~
110
!.- ____________ ~
142~
~~~-----~~------------------~-------------=CC~C.::K:.:.'~~
•
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°"....:2=4--1_ _ _."-1
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3.
I
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RSOZA
:B
11,"3,K
R
USIOB
R500C
t-__________________~------------~~~--~P:c:+:5~!£f..::'0~~~Io~e~2~-----~~:o~aL-'O)-~_'O
-+:P:D:¢=~"ti~
f
_R_5~Z;OC2-'B'L
I '"
'7:
!B
+3\,1
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~----__-------4--~P-B-~~~~
1 R506
1a
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R6020
R602E
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R604B
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R6040
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R604F
R604G
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R606C
R6060
R606E
R608A
R608B
R608C
R6080
R608E
R608F
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U60a
U602
U604
&
Table 11-16
DATA OUTPUT
ASSY. A35
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BOARD
LOCATION
CIRCUIT
NUMBER
F1
F3
B1
B1
B1
A3
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E1
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E2
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E2
E2
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E3
E3
E3
E4
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E4
F5
A1
A2
A2
A1
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C3
C3
C3
C3
C3
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A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
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A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
E3
E3
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U606
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U610
U612
U614
U616
U618
U620
U622
U624
U626
U628
U630
U632
U634
U636
U638
U640
U642
U644
U646
U648A
U648B
U650
U652
U654
U656
U658
U660
U662
U664
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U668
U670
- 91S32 PAT. GEN. BD.,
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B2
B3
B4
C1
C1
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C3
C4
C4
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~ Q300yo:!!
~;I ~ ~ ~ ~ ~ ~ ~ ~ :2 ~
TO
I
314t
4t
1
I Jz;:l4t
I
I
+[5V
Q501~+----~h3w;;.30---c
20 mA
3.5 ns maximum (20% to 80% of logic
level), resistive load
Transition Time
ECl Mode
Drive Capability
V LOUT = VH -1.65V
VH OUT = VH -1 V
20 mA (500 to VH -2 V)
50 pF maximum
2.5 ns maximum (20% to 80% of logic
level), resistive load
Transition Time
REV JAN 1986
Nominal open emitters
1·32
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