07908 90907_7908_Engineering_Reference_Package_Jun84 90907 7908 Engineering Reference Package Jun84
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. . - - - - - - - - (fiJ ~:~a.m
ENGINEERING REFERENCE
PACKAGE
7908
DISC/T APE DRIVES
Manual part no. 07908-90907
Printed: JUN 1984
Printed in U.s.A
07908-90907
E0684
IMPORTANT NOTICE
This document is intended to provide trained lpecialists with information about replaceable
component parts and the function and operation of this product. However. Hewlett-Packard
does not encoura,e component level repair by its customers. Customers who choose to repair
to the component level do 10 entirely at their own risk. Any damaae relultina from cu.tomer repair. il excluded from warranty or service contract coveraae.
BEFORE USING THIS DOCUMENT, "rifE CUSTOMER SHOULD CONSIDER THE
FOLLOWING LIMITATIONS:
1) Hewlett -Packard does not auarantee the completeness or accuracy of the
drawin,s.
2) The drawings may not include all production changes made to the equipment.
3) This documentation is internal Hewlett-Packard documentation and is not
normalJy supplied to our customer engineers. CUstomer engineers may not be
prepared to answer questions relating to these drawin,s,
4) The information does not include certain resources such as test procedures or
dia,nostic programs designed for Hewlett-Packard', internal test systems.
S) Component level training is not available for every product.
HEWLETT -PACKARD COMPANY
P.O.60x 39 BOISE. IOAHO 83707, U.S.A.
PRINTING HISTORY
-
New editions incorporate all update materi~l sir:c; ~he previous edition. Changes, when issued between editions, will contain additional and revised informa lion to be incorporated into the document by the user. The
date on the title pale changes only when a new edition is published.
First Edition ""........... JUN! 984
NOTICE
The information contained in this document is subject to change without notice.
HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND, WHETHER WRITTEN OR ORAL,
\VITH REGARD TO TilE INFORMATION IN THIS DOCUMENT. HEWLETT-PACKARD
SPECIFICALL Y DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE. Hewlett-Packard shall not be liable for enors contained herein or for
incidental or consequential damages in connection with the furnishing, performance or use of this
information.
This document contains proprietary information which is protected by copyright. All rights are reserved.
Reproduction, adaptation or distribution of this document is prohIbited, exceN as authorized under the
copyright laws.
ii
CONTENTS
07908-60002 MICROPROCESSOR PCA-AS
07908-60004 MOTHERBOARD PCA-A 7
07908-60006 SERVO PCA-A2
07908-60007 REGULATOR PCA-AI
07908-60009 DISC MEMORY ACCESS (DMA) PCA-A4
07908-60G12 POWER INTERCONNECT PeA-AIO
07908-60013 RECTIFIER PCA-A9
07908-60142 SWITCH PeA-AI S
07908-60205 READ/WRITE PCA-A3
07908-6024) TAPE INTERFACE BOARD (TIB) PCA-A6
07908-60340 TAPE MODULE
iii/iv
P-/N 07908-60007
REGULA TOR PCA-A 1
Series Code F-2301
+------------------------------------------- I I hp
HEW L E ~ T - PAC K
NOTE:
A R D C O.
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ER48
DIH: 50A
-----------------------------+
'l'hi. pace provides a nmning history ot changes f'or a IlUlti-pa.ge
drawing which cannot ~nvenientlr be re-issued completely atter
each cht.l.'p. When making a change, list tor each. pace all beforeand-after nuabers (within reason; use judgement. and use
"extensiv." revision note it lo.s ot past history i. tolerable. or
retype complete page) and associate with each a symbol made up of
the change letter and a .erial subscript to ap~ar bere and on
the pace involved (there enclosed in a circle, triancle. or other
attention-,e'tting c;utline).
(L403)
t
LTRI
REVISIONS
,
DATE
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1M
IF
---I··-----r------------------------------------------,-.-------,-------,-10-20-82 .r/ML M
A AS ISSUED PER PeO ~-6021
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,--+---------+-------+---------+------------------+---------_._-----------------,
IA 148-6021 I sr/ML 110-20-82 IMODEL 7908
ISTK , 0790 8-60007
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I I I - - 1 REGULATOR - IMS
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,--+---------+-------+---------+-----------------------+-----------------------,
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IBY
IDATE APR 30. 1984
1
1--+----_·_---+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR , Die: fAPPD
ISHEET , 1 OF 15
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1--+---------+-------+---------+-----------------------+----+------------------1
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REVISIONS
I SUPERSEDES
IDWG 'A-07908-60007-5 f
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+------------------------------------------- / I bp
B E V LIT T -
PAC
K A R D C O.
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ER48
D/H: 50A
-----------------------------+
IMS FOR THE REGULATOR BOARD
(01908-60001)
Not.: The 1908 power supply is compos.d of two assBblie.:
1) the rectifier assembly. 07908-60011, and
2) the recule.tor board, 07908-60007.
~i8
docu.ent represents one-halt of the INS for the
1908 power supply.
TABLE OF COHTElf'l'S
I.
ABSTRACT
I I.
FUNCTIONAL BLOCK DIAGRAM
III. CRITICAL CCI!POKENTS AND MATERIALS
A. ELECTRICAL ~NENTS
1. ZENER REFERENCr DIODE
3.
PRECISION RESISTOR 1fETW0RIt
OP-AMPS
1,.
a. +5V SUPPLY (LM 3071')
b.
SUPPLIES (HC 1~58)
DRIVER TRAlfSIS'l'ORS
2.
+/-12V
5.
6.
1.
8.
9.
10.
11.
12.
a. IfPN:TIP ~lA
b. PNP:TIP ~2A
PASS TRANSISTORS
a. IfPN: 21f5885
b. PNP:2If5883
DRIVER TRAlfSIS'l'OR EHITl'ER RESISTOR
CURRENT SEllSE RESISTOR
OP-AMP BYPASS CAPACITOR
a. 100 PF
b. 470 PF
c. 1000 Plo"
4. .01 UF
MATCHED DIODE PACK
POWER RECTIFIER DIODE
a. GENERAL PURPOSE: 1.4004
b. HIGH CURRENT: GE Al5A
SILICON-CONTROLLED RECTIFIER
THERMAL SWITCH
--+---------+-------+---------+------------------+-------------------------_._1~~-6021 I sr/ML 110-20-82 IMODEL 1908
1ST! , 07908-60007
1--+---------+-------+---------+------------------+--------------------------..
1 1
I / I - - I REGULATOR - IMS
1--+---------+-------+---------+-----------------------+------------------------1
, ,
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IDATE APR 30, 1984
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,--+---------+-------+---------+-----------------------+----------------------·-1
ILTI P.C.' I APPR 1 DATE IAPPD
ISHEET ,
2 fE 15
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REVISIONS
ISUPERSEDES
IDWG 'A-07908-60007-5 I
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I B E WLET T - PAC K A R D C O.
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TABLE or CONTENTS
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(COMT)
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B. MECBAHICAL COMPOJIElITS
1
1. BEAT SIa
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a. MECHANICAL DESIGH
I
b. MATERIAL
I
2. TRANSISTOR INSULATORS
I
&.
TO-3
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BARD ANODI ~ ALUMINUM
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PRE-COATED MICA .
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b. TO-220
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ER48 D/B: 50A
-----------------------------+
THERMAFILM
PRE-COATED 'l'HERMAFILM
IlfSULATIIlG WASHERS FOR TRAHSISTORS
a.
It.
IV.
TO-3
b. 'l'O-220
IHPt1.r VOLTAGE CaftiECTOR
ELECTRICAL FUlfC'l'IOB " 1'BE REGULATOR BOARD
A. !HEORY OF OPERATIOlf
1. OBJECTIVES AID COBSTRAIJrl'S
2. ImGULATOR BOARD IllPUT AHD otn'PU'l' VOLTAGE AND
CURRENT SPECIFIC~IOHS
3. SEQUElfCIlfG OF '!'HE REGULATED SUPPLIES
a. TURN-ON SEQUEllCE
It.
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5.
6.
7.
8.
b. TURN -OFF SEQUEMCE
BASIC CIRCUIT CONFIGURATION
a. DESCRIPTIOJf
b. GENERIC SCHEMATIC
REGULATOR DESCRIPl'I01:
a. +12V SUPPLIES
b. -12V SUPfLIES
e. +5V SUPPLIES
OVERVOLTAGE PROTECTIOlf
OVERctJRRElfT PROTECTION
OVERTEMl'ElW.'URE PROTECTION
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--+---------+-------+---------+------------------+------------_··_-------------1
1~-6021 1 .r/ML 110-20-82 IMODEL 7908
1ST! , 01908-60001
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I t ' I / I - - I REGULA..."'OR - IMS
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1--+---------+-------+---------+-----------------------+---------·--------------1
I I
I I I - I BY
IDATE APR 30 1984
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1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR I DATE
IAPPD
I SHEET , 3 CE 15
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,._-+---------+-------+---------+-----------------------+-----------------------1
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REVIFT(IIS
ISUPERSEDES
lIM; 'A-01908-60007-5 I
+------------------------------------------------------------------------------+
JA
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+------------------------------------------- I I hp
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R E WLET T - PAC K A ft D C O.
I.
ABSTRACT
II.
FUHC'l'IOlfAL BLOCK DIAGRAM
III.
CRITI.CAL CCfIPONENTS AJfD MATERIALS
I
I
I
ER48 DIB: 50A
-----------------------------+
A. ELEC'DUCAL COMPOKEHTS
1.
Zene:r Reterence Diode:
1902-0692
!be stability of the reference voltage over & wide
range ot operating conditions is vital tor the proper
relUlation ot the supplJ volta,.s. This 6.3v zener
diode is temperature eo.pensated and .pecified to be
within one percent of the nOilinal value at its specified cur:...nt.
2.
Precision Resi.tor Network: 1810-0548
Precision 10k resistor n.twork. are uled to
.inimize errors due to component tolerance. in
'the reference voltage circuit and the rel'1lated
Voltage feedback to the controlling op-amps. The
re.i.tance between pack. i. specifi.d to be within
0.5' of the .nominal value. Within a given re.i.tor
network, the resi.tor. will be within 0.5' of each
other.
3.
Controllin, Op-Amp
•• +5v supplJ (LM 307X): 1820-0493
The LM 307N op-amp i. u ••d to control the +5v
regulator circuit because its input voltage.
can equal its politive supply volta,e.
,
J
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,--+---------+-------+---------+------------ -----+---------------------------IA 148-6021 I sr/ML 110-20-82 IMODEL 7908
1ST! , 07908-60007
1--+---------+-------+---------+------------------+----------------------------
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REGULATOR - IMS
,--+---------+-------+---------+-----------------------+-----------------------,
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IDATE APR 30, 1984
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1--+---------+--------+---------+-----------------------+-----------------------,
'tTl P.C.' I APPR I DATE
IAFPD
ISHEET ,
It C6 15
1
r--+---------+-------+---------+-----------------------+-----------------------1
I
REVISIONS
ISUPERSEDES
Iowa 'A-07908-60007-5 I
+-----------------,-------------------------------------------------------------+
+-------------------------------------------/ /hp / / ER48 D/H: 50A
HEW LET T - PAC K A R D C O.
1 1 -----------------------------+
III.
CRITICAL C<»1PONEHTS AND MATERIALS (CONT)
b.
+/-129 supplies (MC1458): 1826-0139
The MC1458 dual op-amp is preferable to the pin
compatible MC~558 because it has a wider dirferential
~ut voltage range aDd a single pole frequency
response. InitiallJ the Mc4558 was u.ed a. the
controlling op-up in the +1-12v supplies until it was
observed that op-amps were occasionally destroyed by
input signals within their specified ditferential input
voltace range. Tests conducted by Rick Wells showed
that the Mc4558 would break down tor ditterential input
voltage ot +1-15v rather than tor +/-3Ov as the device
i. specitied.
~.
Driver Transistor
a. IPB (TIP ~1A): 1854-0456
b. PKP
(TIP ~2A):
1853-0234
These transistors are employed ba.ed upon their rea~
availabili ty, TO-220 package type, lIlaXimum power
dissipation ot 65w at 25C, and a CUl~rent pin ot 15
to 75 at a collector current 01 three amps.
5.
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Paaa Trans iator
a. JfPB (21f5885): 185~-0679
b. P.NP (2N5883): 1853-0~25
Selection ot the pasa tranaiators is baaed upon their
ex-tremely low collector to emitter saturation volta,e
ot 1.Ov max, current gain ot 20 to 100 at a collector
current ot ten ampa, a lDaximum junction temperature
ot 200C, and low cost.
6.
Driver Emitter Re.istor (10 ohm): 0698-3601
The ch·.lice ot this resistor ia based upon its power
dissipation ability and potential as an auto-ins.rtable
part.
,--+---------+-------+---------+------------------+--------------,--------------1
IA 148-6021 I ar/ML 110-20-82 ~i-!ODEL 1908
ISTK , 07908-60001
1
,--+---------+-------+---------+------------------+----------------------------1
I 1
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1
1--+---------+-------+---------+-----------------------+-----------------------1
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IDATE APR 30, 1984
1
1--+---------+-------+---------+-----------------------+-----------------------,
ILTj P.C.' I APPR I DATE IAPPD
ISHEET , 5 OF 15
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1--+---------+-------+---------+-----------------------+-----------------------1
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REVISIONS
JSUPERSEDES
IDWG 'A-07908-60001-5 I
+_._----------------------------------------------------------------------------+
+---------------.----------------------------
II
B E WLET T - PAC K A R D C O.
III.
I
I ER48 DIB: 50A
I hp I
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CRITICAL COMPONENTS AID MATERIALS (CONT)
7.
Current Sense R.sistor (0.01 ohm): 0811-3511
An accurate, low resistance, power resistor is needed to
Sf' 'se the current drawn by the two pas. transistors used
in the +5v reaulator circuit.
8.
:>p-amp Bypass Capacitors
a. 100 pf: 0160-2204 .
b. ~70 pt: 0160-3533
c. 1000 pf:0160-2218
d. 0.01 uf: 0160-0161
Fixed dip mica and aylar filii capacitors are used to
compensate the regulating op-amp. and stabilize the
circuit ~spon.e to abrupt change. in the load
current. The choice. of the.e capacitors i. due to
their ,ood frequency response characteristics and
Ready availability.
9. MatChed Diode Pack: 1906-0248
It is preferra~le to use matched diod.. in th. undervoltage deter.t circuit to eliminate measure.ent .rror
due to uneq'~l diode volt.... drop.. I.portant
.pecificati~. used in choo.in, this device are it.
forward current .pecification of 400RA. total power
dissipation ability of 60o.w, and peak revers. volta,e
ot 40v.
--+---------+-------+---------+------------------+---------------------------I sr/HL 110-20-82 IMODEL 7908
ISTK , 07908-60007
1--+---------+-------+---------+------------------+---------------------------I I
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1--+---------+-------+---------+-----------------------+----------------------I I
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IDATE APR 30, 1384
1--+---------+-------+---------+-----------------------+----------------------LTI P.C.' I APPR I DATE
IAFPD
ISHEET' 6 OF 15
(--+---------+-------+---------+-----------------------+----------------------1
REVISIONS
ISUPERSEDES
Iowa , A-07908-60001-5
+------------------------------------------------------------------------------+
fA 1~-6021
.------------------------------------------- /
I ER48 DIH: 50A
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10. Power Rectifier Diode.
a. General Purpo.e (1N4004): 1901-0743
b.
Biah Current (A15A): 1901-0673
u..
Selection or the power rectifier diode. for
in
the overvoltap circuit i. based upon their current
ratingl - averaa. continuous rectified current and
peak .ura. current. Their cpecification. are:
J
a.
I.
Uf4004- 1A aaxi.mua, 30A aaxiJnwD .urge;
A15A- 5A .axillwa, 125A .aximula lur,e.
11. Silicon-Controlled R.ctifier: 1884-0268
Iaportant charact.ristic. of the SCR are it. a••race
rectified current (25A), peak lur,e current (300A).
peak rate power ratiDc (20W), and the TO-220
•• chanical pactaae type.
12.
~ermal
Switch: 3103-0093
'l'b.e therllal Iwitch i. delilDed to have contact. which
are capabl. ot Iwi tching current loadl from 101aA to
2A. Some vi tal charact.ril iCI ot the thenaal witch
ar.:
&. clo.e on temperature rile at 200F +/- 8F;
b. open on t.aperature tall at 120F +1- 8F;
e. COld flalh on the cont&ct~ to allow
IwitchtQc at .er.v low current.;
d. ..chanical pack... delian atfordl ealY
a ••••bly ot the thermal Iwitch onto the .ide
ot the heat stnt.
f
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I--+-----~---+-------+---------+------------------+-----------~----------------I
IA 148-6021 I .r/ML 110-20-82 IMODEL 7908
ISTK , 07908-60007
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1--+---------+-------+---------+------------------+----------------------------1
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,1--+---------+-------+---------+-----------------------+-----------------------,
I 1
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IDATE APR 30, 1984
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1--+---------+-------+---------+-----------------------+-----------------------1
JLTI P.C.' I APPR 1 DATE
IAPPD
ISHEET , 7 OF 15
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1--+---------+-------+---------+--------------------+-----------------------1
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REVISIONS
ISUPERSEDES
IDWG 'A-07908-60007-5 I
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~------------------------------------------- I
B E V LET T - PAC K A R D C O.
III.
I ER48 D/B: 50A
I hp I
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CRITICAL COMPONENTS AND MATERIALS (CONT)
B.
MECHANICAL COMPONENTS AND MATERIALS
1.
Beat Sink: 07908-20002
a. Mechanical Design
The heat sink is an aluminwn extrusion with multiple
tins. Mounting holes for eight TO-3 transistora,
eight '1'0-220 transistor., and two thermal switch••
are machined by the heats ink .anufacturer. Al.l ot
the mounting locations are not being used prest:A1.q
but were included for flexibility in fUturo de.iens.
~e tlatness specification for Thermalloy's standard
extrusion is 0.004 inches per linear inch.
b. Materials
Aluminum is used because ot it. low thenaal
resistance, approximately one degr.e C per watt, and
it is easily extruded and machined.
2.
Transistor Insulators
a. TO-3
Bard anodized aluminum: 1200-0043
Bard anodized aluminum insulators are u.ed tor the
power transistors because ot their low thermal
resistance and ready availabilty. The necessity ot
coatine the insulators with heat sink compound i. a
disadvantage ot this type ot insulator trom a
manutacturing point ot view. The silicone rubber
impregnated insulators were avoided due to tearing
and cracking ot the insulators ~ich resulted in
electrically shorting the transistors to the heat
sink.
--+---------+-------+---------+------------------+---------------------------ISTK , 01908-60007
1--+---------+-------+---------+------------------+----------------------------,
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IDATE APR 30, 1984
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l.TI P.C.' 1 APPR 1 DATE
IAPPD
ISHEET , 8 OF 15
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r--+-----~---+-------+---------+-----------------------+-----------------------,
1
REvISIONS
ISUPERSEDES
IDWG 'A-0790S-60007-5 I
+------------------------------------------------------------------------------+
+---------,---------------------------------I
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2.
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Transistor Insulators (cont)
a. 1'0-3 (cont)
Pre-coated Mica (IHSUL-COTE):
I
048
DIB:
50A
-----------------------------+
0340-0978
The mica insulators that are pre-coated with thermal
co.pound are less expensive, easie~ to ~ssemble, and
.ar. uniforalY eoated than their discrete CQunterparts .entioned above. An automatic dispens inC
.achiDe, on loan trolD Til.nalloy, is being used on
the production line at present.
b. 1'0-220
Thermaltilm: 0340-0473
,
A J)C'lyimide plas,tic insulator i. used with each
1'0-220 packa". transistor. The_3 insulator. IlU.t
be coa 1. .. 1 with tberaally conductive compound.
t
Pre-coated Thermalfilm:
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03~0-xxxx
In the .&Dual coatinc procedure, several insulator.
are plac.d between two .ponges that are saturat.d
with themal compound. Dust, dirt, and metal l.ads
can contaainat. the spoages, .tick to the insulator.,
and cau••• eriou. board failure.. As .. t •• t ca.e,
pre-coated Thermaltilm transi.tor insulator. and a
dispensinc _chine are being examined by P.C.
production tor u•• in the as ••mblY proces ••
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1--+---------+-------+---------+------------------+---------------------------IA 148-6021 I .r/ML 110-20-82 IMODEL 7908
ISTK , 07908-60007
1--+---------+-------+---------+------------------+---------------------------I I
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1--+---------+-------+---------+-----------------------+----------------------I I
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IDATE APR 30, 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
I SHEET ,
9 OF 15
1·--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
1SUPERSEDES
IDWG , A-07908-60001-5
+------------------------------------------------------------------------------+
+------------------------------------------- I I bp
B E W LIt' t' - PAC J[ A R D
3.
C O.
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I ER48 DJB: 50A
/ ---------------- .. ------------+
I
Insulating Washers for Transi&tors
a. 'l'O-3 Insulating Flange Bushing: 1200-0081
The screws used to attach the 1'0-3 transistors· to 'the
heat stnk and the heat sink to the p.c. board also
provide the electrically conductive path fro. the ease
(collector) of the ~ran3istor to the pad on the board.
Iylon bushings are used to insulate the screw. from
the heat sink. Six additional nylon bushings are
required 'to ensure tha't the heat sink i. elevated a
Wliform "i.tance above the p.e. board. The extra
bushings l.imit wobble ot the heat sink under vibra'tion
and prevent electrical/mechanical contact ~t the heat
sink and the p.c. board.
b.
TO-2~~
Shoulder Wa.her; 3050-1021
Shoulder wa.hers, made ot po~rpheny1ene su1tide, are
u.ed to insulate the tab of the TO-220 'transistors
trom the beat sink. The diameter ot the Ilountinl hole
in the tab ot the '1'0-220 packa,ed transistors has Dot
been .~andardized amone the various manufacture~s.
lhie shoulder ~sher i. designed to .echanically tit
any and all 1'0-220 packages.
~.
Input Volta,e Connector: 1251-5535
Selection of 'this connector i. based largely upon
.echanical design constraints. The connector a ....blY
can not extend pa.t 'the edge ot the p.c. board without interferin, with thea rear panel. This rightangle connector has ten pins and is capable ot carrying seven up. per pin. The Fan-Rectifier cab1.,
01908-60024, CODl.t!tctS the regulator board via this
connector to the rectifier assembly.
--+---------+-------+---------+------------------+---------------------------I sr/ML 110-20-82 IMODEL 1908
1ST! , 07908-60001
1--+---------+-------+---------+------------------+---------------------------I I
'I I
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1--+---------+-------+---------+-----------------------+----..
-----------------I 1
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fDATE APR 30, 1984
,--+---------+-------+---------+-----------------------+-----------------------".ITI P.C., I APPR I DATE IAFPD
ISHEET I 10 OF 15
IA 148-6021
~-+---------+-------+---------+-----------------------+-----------------------
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REVISIOBS
ISUPERSEDES
IDWG , A-07908-60001-5
+---------------------------------_._------------------------------------------+
+------------------------------------------I
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I
I IV.
J
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I
I
J
I
J
I
,
I
~
I
I
J
t
1
I
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J
Electrical Function of the Regulator Board
A. Theory of Operation
1. Objectives and Constraints
power dissipation of the regulator circuit.
particulariq 'the pass transistors. had to be lIinillized
to allow the printed circuit board to be placed in the
card cage aDd cooled adequateq. A sch..e of
preregulattQg 'the voltaces i~ressed upon the pass
transistors is employed to curtail the power
dissipation and increase the operatinc efficiency of
the power supply. See the INS for the Rectifier
Ass..blY, 07908-60011, for the theory of loperation or
the pre-regu1ation circuit.
~e
2. Regulator Board Input and Output Voltace and Current
Specifications
Four volt...s are i~ressed upon the reculator board
from which .be reculated voltaces are derived. Tabl.
1.1 on the rollowinc pace li.ts all of the input. and
outputs for the regulator board and typical value ••
In addition two dicita1 siena1s, Ma.ter R•• et (MRST-L)
and Po •• ible Power Fail (PfAIt-L). are sent to the
drive electronics from the reculator board. These
s ilDals are used under power on. power oft. and power
tail conditions. Durin, nomal operation of the driv••
PFAIL-L and MRST-L are in tbe hieb atate ~: +5V. )
1
I
1
I
J
I
I
1--+---------+-------+---------+------------------+---------------------------IA 148-6021 1 sr/HL 110-20-82 IMODEL 7908
1ST! , 01908-60007
1--+---------+-------+---------+------------------+----------------------------,
I I
I I
I
I REGULATOR - IMS
I
1--+---------+-------+---------+-----------------------+-----------------------,
I I
I I
I
IBY
IDATE APR 30, 1984
I
1--+---------+-------+---------+-----------------------+-----------------------,
ILTI P.c., I APPR I DATE IAPPD
1SKEET , U OF 15
I
1--+---------+-------+---------+-----------------------+-----------------------1
I
REVISICIlS
ISUPERSEDES
IIMG 'A-07908-60007-5 1
+------------------------------------------------------------------------------+
+------------------------------------------- I /hp
B E Wt E ! ~ - PAC K A R D C
o.
Table
/
/
I
I
ER~ D/B: 501
-----------------------------+
7.1
/ Output / Unregulated Input I Rated
/
/ Voltage / Voltage (average) / Current /
/
/ at Rated Current /
/
I
I
Purpose/Comments
/
/---------/-------------------/---------/-----------------------------/
/
I
/
/ +5v 1s used by f.J.l p. c.
/
/
/
/
+5V
-~,+5~
/ dc= 1.75V
/ ripple: l·SYp-p
/
/
/
/
lOA
/ dCI: 17. OV
/ ripple: 2.0Vp-p
/
/
U
/ boards and tape drive.
/ TUrn-on of +5V occurs
/ after +12L is up.
I
/
/
/-------,--/-------------------/---------/-----------------------------/
/
/
/
/ +12VS powers the I~I npindle/
/
/
+12VS
-5~,+5~
/ and voice coil. There i.
/ delay at turn-on.
DO/
I
/---------/-------------------/---------/-----------------------------/
/
/
/
/ +12T is used by the tape
/
/
/
+12T
-5~,+5~
/ dcc: 17. OV
/ ripple: 2.0vp-p
/
/
/ del: 17.0V
/ ripple: 2.0Vp-p
/
/
/
/
/ aodule alone. '!'urn-on
auree/ 1. dependent upon +5V.
lAI
~A
/
I
/---------/-------------------/---------/-----------------------------/
/
/
/
/ +12L is used to supply
/
/
/
/
+12t
-5~,+5~
1A
/ electronic components on
/
/ all p.c. boards. This
/
/ supplJ turns on immediate17./
/---------/-------------------/---------/-----------------------------/
/
/
/ The -12VS is used to operate/
/
/
/
/
-12VS
-5~,+5~
/ dc. -17.0V
/ ripple· 2.0Vp-p
/
/
/
/
~A
/ the IM1 spiDdle and voice /
/ coil. This supply turn. OD /
/ t.aediatel.y.
/
/ - - - - - - - - - / - - - - - - - - - - - - - - - - - - - / _____ 0 ____ / _ - - - - - - - - - - - _________________ /
/
/
/
/
-12t
-5~,+5~
/
/ dc. -17.0V
/ ripple· 2.0Vp-p
/
/
/
/
/
/ -12L is u.ed to supply the
lA
/
/ electronics on the pc bds. /
/ There is DO delay in turn-on/
/ ot the supplJ.
/
/--------,-/-------------------/---------/-----------------------------/
/
/
/
/ +12V UM is sent to the
/
/ +12V UN / del: 17.0V
/
/ ripple= 2.0Vp-p
/
/
1A
/ -12V UN / de. 11.0V
/
1A
/ aotherboard, but is Dot
/ presently used.
/
/
/ motherboard, but is Dot
/
/----------/-------------------/---------/-----------------------------/
/
/
/
/ -12V UM is sent to the
/
I /
/ ripple= 2.0Vp-p /
/ presently used.
I
I ---------.-------------------------------------------------------------1
1
1
I
,1--+---------+-------+---------+------------------+----------------------------1
IA 148-6021 I sr/HL 110-20-82
IHODEL 7908
1ST! , 07908-60001
I
1--+---------;-------+---------+------------------+----------------------------1
I 1
I I
1
I REGULATOR - IHS
I
1--+---------+-------+---------+-----------------------+-----------------------1
I 1
1 I
I
IBY
IDATE APR 30, 198~
I
1--+---------+-------+---------+-----------------------+-----------------------1
ItTI p.e., 1 APPR 1 DATE IAPPD
ISHEET' 12 OF 15
1
1--+---------+-------+---------+-----------------------+------------------------1
I
REVISIOHS
ISUPERSEDES
IDWG 'A-01908-60007'-5 I
+-------------------------------------------------------------------------_._---+
+------------------------------------------- I I hp
HEW LET T - PAC K A R D C O.
3.
Sequencing of the Regulated
I
Supp~
I
I
I
ER48 D/B: 50A
-----------------------------+
Voltages
a. Turn-on
The tum-on of the regulated voltages is coc)rdinated
and sequenced t.:hen powering up the drive. When power
is applied to the reculator board the +12VS. +12L,
-l2VS, and -12L supplies begin imm"diat.~. The +5V
supply i8 dependent upon +12L being within its
specified voltage limit.. '!'he +12T supp~, which
operates the tape aodule, is required to be held oft
until the +5V supply is within its acceptable voltage
range. There is no specified time del&)' between the
turn-on of each .upp~; instead, the +12T supply i.
dependent upon the voltage level ot the +5V supply.
In powerine up the drive MRsr-L initiates assumption
of .icroprocessor control of the disc drive tirst,
tollowed by the tape drive.
b. Turn-ott
When the power i. ahut otf tor &n7 reason. PFAIL-L will
tall low (OV) to warn the electronics ot the impending
lOll of power. Atter. time delay ot no le •• than 700
microseconds. MRST-L will •• sert (tall low) indicating
that the power suppliel are at their minimum acceptable
volta,e level. The time del&)' between PFAIL-L and
MRST-L allow. the aicroprocessor controlling the di.c
to co.plete its operation. in an orderly ra.hion. The
shut down at the tape drive will not be orderly because
it would require about thirty milliseconds to tini.h
writing a blockl Atter HRST-L is .et low, t,he drive
electronic. will not be operational •
•I
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I
1--+---------+-------+---------+------------------+---------------------------fA 148-6021 I 8r/ML 110-20-82 IHODEL 7908
ISTK , 07908-60007
1--+---------+-------+---------+------------------+----------------------------1
I I
I I
I
I REGULATOR - IMS
I
)--+---------+-------+---------+-----------------------+-----------------------,
I ,
I
I
I
IBY
IDATE APR 30, 1984
I
J-~---------+-------+---------+-----------------------+-----------------------1
ILTI
P.c.,
I
APPR
I
DATE
IAFPD
ISHEET'
13
OF
15
I
,--+---------+-------+---------+-----------------------+---_._------------------,
I
REVISIONS
I SUPERSEDES
Iowa 'A-07908-60007-5 I
+----------------------------------------------------------_._------------------+
+------------------------------------------- I I bp I I
B E W LIT T - PAC I A R D C O.
I
ER48 D.~: 50A
I ------------
--------------+
4. Basic Circuit Confiauration
&. Description
Dle circuit topology used is the "backwards" pas.
transistor in a linear, series reculation circuit, see
Ficur- T.1. The advantage ot this circuit desien is
that the power transistor. will continue to operate tor
tDput voltaces only the transistor collector-to-emitter
saturation voltace Ireater than the regulated output
voltace. By choosinc pow.r transistor. with an
extr8llleq lov co:,lector-to-ellitter saturation voltage
the circuit operatinc range i. lIuillized and device
power di.sipation is lIinimized. The teedback
capacitors around the op-a.ps atabilize the circuit
response to step chance. in the current load. The
value. of the capacitors cho.en were based pri~-l1y on
"piric&! evidence. An1 resistive element introduced
tDto the teedback was tound to _ake the circuit
UIlstable ..
b. Generic Schematic Diacr&Jll
--+---------+-------+---------+------------------+---------------------------ISTK , 07908-60007
1--+---------+-------+---------+------------------+---------------------------1 1
I I I
I REGULATOR - IMS
1--+---------+-------+---------+-----------------------+----------------------I I
I I I
I BY
IDATE APR 30, 1984
1--+---------+-------+---------+-----------------------+-----------------------1
IL'l'1 P.C.' I APPR I DATE IAPPD
ISHEET' 14 OF 15
I
1--+---------+,-------+---------+-----------------------+-----------------------1
I
REVISIONS
ISUPERSEDES
IDWG 'A-07908-60001-5 1
+------------_._----------------------------------------------------------------+
IA 148-E021 1 sr/ML 110-20-82 IMODEL 7908
+------------------------------------------I
I
I
B E W LET T - PAC K A R D
C
o.
I
I ER48 D/B: 50A
Ibl
I
I -----------------------------+
1
I
I
I
I
I
I
I
5.
Re,..- -
a.
~UF."Il.y
Description
~~ Supp~
Based on calculations of junction temperature by Dan
Michaud, it was determined that two transistors should
share the lOA current. One supply consisting of U222,
Ql14, and Ql36 is very similar to the +12VS, +12V and
+12L 5upplies without the precision attenuation in the
teedback. The master supply matches its reference
voltage. The other SLAVE supply consisting of U148,
Ql96 and Q114 looks at the current through R162 and
causes that current to pass through R144. Because of
the low dissipation, low voltage drop requirements,
Rl62 and R144 are 10 mil.liohlll res istors. li'llis puts
the vol.tage across these resistors into the 10 to 50mv
range where input offset voltages on 0148 .are quite
iaportant. Since the SLAVE circuit is a current matching arran,..ent, it will. wrongly match a non-existent
current due to an error in input offset voltage.
Thus acting as a current source, the full unregulated
voltage may be applied to a small load. To overcome
this probl.. the SLAVE is held off by pul.ling approxi.ately 1ma (_ore when the unregulated voltage is higher corra.ponding to smal.ler loads) through the parallel cOlllbination of R124 and Rl28. Typically, the current to the +5V load must be 1 amp before t;he SLAVEcircui t start. to condu:t current. R124 and R128
tOI'll an attenuator for the voltage drop acr'os. Rl44.
10 that the SLAVE gets an under .stimate ot, its current. It therefore contribut•• more than half the
incremental ~ent once it ,et. rollin,. At the
10 amp level, typically both circuit. are carrying
5 amps.
1
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I
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I
I
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1--+---------+-------+---------+------------------+---------------------------IA 148-6021 I sr/ML 110-20-82 IMODEL 7908
1ST({ , 01908-60001
1--+---------+-------+---------+------------------+---------------------------I I
I /
J
I REC'JLATOR - JMS
1--+---------+-------+---------+-----------------------+----------------------I I
I I
I
IBY
IDATE APR 30, 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI p.e., I APPR I DATE
IAPPD
ISHEET' 15 OF 15
,--+---------+-------+---------+--- --------------------+---- -_._---------- ------
I
REVISIONS
1SUP.ERSEDES
Iowa , A-01908-60001-5
+------------------------------------------------------------------------------+
PAGE 1
DATE: 05/09/84
MRFD047R
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART lfUMBERS
PART-NUMBER(S) :
07908-60007
07908-66007
07908-68007
DATE CODE :
1-2300 .. ",d :t3tH
REFERENCE DESIGHA'l'OI\
Cl26
C150
C160
C210
C212
C21a.
C216
C22a.
C226
C232
c238
C252
c256
C258
C306
C310
C312
C318
C332
C33!t
c356
C364
C376
C38!t
C392
CRl06
CRl08
CR112
CRl66
CRl93
CRl95
CR202
CR26a.
CR266
CR276
CR282
CR288
CR292
CR354
CR368
CR370
CR380
CR390
.1138
MPl
MPlO
MPl2
COHPONEMT PART
0180-0291
0160-2218
0160-0161
0160-2218
0160-2218
0160-2218
0160-2218
0160-2218
0160-2218
0160-2201f
0160-2201f
0160-2201f
0160-2201f
0160-0127
0160-2204
0160-3879
0160-2218
0160-3533
0180-069~
0180-0091f
0180-0692
0180-0692
0180-0692
0180-0692
0180-0692
1901-00160
1901-00160
1901-00160
1901-00160
1901-0040
1901-00160
1901-0040
1901-07163
1901-07163
1901-07163
1901-0743
1901-07163
1901-0743
1901-0743
1901-0743
1901-07163
1901-0743
1901-0743
1251-5535
7120-6830
1480-0116
2200-0600
MATERIAL LIST CorrIJfUES
DESCRIPl'ION
CAP 1UF IOJ
CAP 1000PF S~
CAP .01UF 1~
CAP 1000PF 5~
CAP 1000PF 5J
CAP 1000PF 5J
CAP 1000PF 5J
CAP 1000PF 5J
CAP 1000PF 51
CAP 100Pl' 5J
CAP 100Pl' 5J
CAP 100PF 5J
CAP 100PF 5J
CAP 1UF 2~
CAP 100PF 5J
CAP .01UF 2~
CAP 1000PF 5J
CAP !t70PF 5J
C-F 220UF 35V AL
CAP 100UF -10.·15~
C-F 220UF 35V AL
C-F 220ur 35V AL
C-F 220UF 35V At
C-F 220UF 35V' At
C-F 220ur 35V At
DIODE-SWITCHING
DIODE-SWITCHING
DIODE-SWITCHIJlG
DIODE-SWITCHING
DIODE-SWITCHING
DIODE··SWITCHING
DIODE-SWITCHING
DIO-1Jf4004
DIO-1Jf4004
DIO-1I4004
DIO-1I4004
DIO-1I4004
DIO-1I4004
DIO-1I4004
DIO-1I4004
DIO-lJf4004
DIO-1I4004
DIO-1lf4004
CONN 10-PIIl M
LABEL-INFO
PIN GRV .062X.25
SCREW-MACHIIlE
a. IIEXT PAGE •••
~l47R
DATE: 05/09/8'"
MATERIAL
PAGE
LIST FOR PC-BOARD
PART-IlUMBER(S) :
07908-60001
01908-66001
07908-68007
DATE CODE :
.. -2300
CacPOSED OF IlULTIPLI
B-P PART IIUMBERS
ct __ cI Jl S" .
REFERENCE mSIGliATOR
CCIIPCIIEI'l' PART
DESCRIPl'IOH
HP7
1200-0043
1200-0081
0403-0451
07908-80007
07908-20002
0340-0473
3050-1021
2200-0602
601t0-0239
lIPS
2260-0009
1M: la-ItO
0624-0541
1854-0456
1854-0456
1854-0456
1854-0456
1853-0425
1853-0425
1853-0425
1853-0425
1854-0679
1854-0679
1853-0425
1853-023'"
1853-0231t
1854-0456
1884-0268
1884-0268
1884-0268
0698-3601
0698-3601
0698-3601
0698-3601
0698-34"'3
0698-3435
0757-0346
0757-0279
0757-0279
0811-3511
0757-0280
0757-0280
lIS 6-20 .15L TX
TRAIlS TIP Ita
TIWIS TIP Ita
TIWIS TIP ...a
'l'RAIIS TIP ...a
XSTR PJ(P 2115883
XSTR PlIP 2115883
XSTR PIP 215883
XSTR !'lIP 215883
XSTR JrPII 2115885
XSTR IrPII 215885
ZSTR PIP 215883
MPlIt
MP15
MPl6
HP2
HP3
HP4
MP5
MP6
IIP9
Q105
Ql,07
Q110
Q111t
Q130
Q132
Q131t
Q136
Q170
Q172
Q;t71t
Q192
Q194
Q196
Q358
Q37J,
Q388
R116
R118
R120
R121
Rl22
Rl24
Rl28
Rlllo
R142
Rl44
Rl46
R152
Rl62
Rl68
RlT8
R182
R186
R206
R230
M.A1'ERIAL
~11-3511
0757-0401
0698-3601
0698-3601
0698-3601
0757-0280
0757-0439
LIST CCllTDUES
(II
DSL-XS1'R '1'03 AL
DfSUL-rLG-BSBG
EX'fR-PC 8D '1
BD-acRED
BEAT SIB-REO
lliSUL -1S'l'R
WSBR-SBLIIt
MS,4-40 .375 L
COIPOUJO)-'DIERMAL
wILl(
TRARSI~
'l1WISI~
J,lA
'l'BYR-2Jf6508 sea
'l'BYR-216508 sea
'l'IIYR-216508 sea
RES 10 51 I
RES 10 51 I
RES 10 51 2
RES 10 51 I
RES 348 11 .5
RES 38.3 11.125
10 11.125
RES
RES 3.16K 11.125
RES 3.16K 11.125
RES .01 11 2W
RES 1K 11.125
RES 1K 11.125
RES .01 1J 2W
RES 100 11.125
RES 10 51 2
RES 10 51 2
RES 10 51 2
RES l.K 11.125
RES 6.81K 11.125
1'IWIS TIP
IIEIT PAGE • • •
2
PAGE 3
DATE: 05/09/84
MRFD047R
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART IlUMBERS
PART-Ii1IGER(S) :
01908-60007
01908-66007
07908-68007
DATE C(I)E :
F-2300 A"J 230'
REFERENCE DESIGNATOR
R246
R250
1254
R262
R302
R308
R314
R320
1322
1324
R326
R328
1336
1340
1342
1346
R347
R348
1349
1350
R352
1360
R362
R372
R386
8190
TPlOl
TPI02
TPl54
TPl56
TPl58
'1'Pl64
TP176
TP180
TPl84
TPl88
TPl~~
m.4B
u204
U218
U220
U222
U228
U236
u240
U242
u260
COMPONENT PARr
0757-0439
0757-0470
0757-1094
0757-0466
0698-3439
0757-0442
0757-0438
0698-3152
0698-3161
0698-3155
0757-0464
0757-0278
0757-0398
0757-0428
0757-0290
0698-3154
0757-0439
0757-0447
0757-0459
0698-3155
0757-0274
0698-3444
0698-3435
0698-3435
0698-3435
3103-0093
0360-1682
0360-1682
0360-1682
0360-1682
0360-1682
0360-1682
0360-1682
0360-1682
0360-1682
0360-1682
0360-1682
1820-0493
1810-0338
1826-0139
1826-0139
1820-0493
1810-0455
1810-0S48
1826-0139
1826-0138
1810-0338
DESCRIPTION
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
I:F
RES
RES
RES
RES
RES
RES
6.81K 1~.125
162K IJ.125
1.47K 1~.125
110K 1~.125
178 1~ .125W
10K 1~.125
5.11K 1~.125
3.48K 1~.125
38.3K 1~.125
4.64x 1~.125
90.9K 1J.125
1.78x 1~.125
75 lJ.125
1.62K 1~.125
6.19K 1~.125
4.22K 1~.125
6.81K 1~.125
16.2K lJ.125
56.2K 1~.125
4.64K IJ.125
1.2lK 11.125
316 1~.125
38.3 IJ.125
38.3 IJ.125
38.3 11.125
SWITCH -THERMAL
TERM-PIN
TERM-FIN
'l'ERM-PIN
TERM-PIN
TERM-PIN
TERM-PIN
TERM-PIN
TERM-PIN
TERM-PIN
TERM-PIN
TERM-PIN
IC LH301N
NETWORK - .lla8
IC MC14S8 P1
IC MC14S8 P1
IC LH301N
IfETWORK -RES DIP
NETWOKRK-10KX8
IC MC14S8 P1
IC LM339
NETWORK - .l.KX8
MATERIAL LIST CONTINUES ON NEXT PAGE • • •
DATE: 05/09/84
1IRFD047R
PAGE
ML"'ERIAL LIST FOR PC"'BOARD COMPOSED OF MULTIPLE B-P PART lUMBERS
PARr-KUMBER(S):
01908-60001
01908-66007
07908-68007
DATE CODE :
F-2300
ct..J
.2301
REFERENCE DESIGNATOR
moll
0330
U344
VR123
VR208
VR263
VR281
VR378
COMPONENT PART
1826-0138
1810-0548
1906-0248
1902-30168
1902-0692
1902-3104
1902-3193
1902-3193
Elm OF MATERIAL LIST.
DESCRIPl'ICIf
Ie LM339
RETWOKRK -1 oKX8
DIODE -ARRAY
DIODE ZIfR 3.48V
DIO-ZNR 6.3V 1~
DIODE BD 5.62V
DIODE ZIfR 13.3V
DIODE ZIfR 13.3V
II
M
OATt COV... WA6 zn~ ~.
"GO _411 00_,0 (u._ _ _ c_)
N
LJ£7AIL
REV'\) flU
c.o4601't~
A
H
DfST AlICE BETWEEN •
UGlS11lATION TARGETS 12.500 • .G03
oJ
SEC. DE..'TA/L
A
REFERENCE DRAWWrlOS:
SCHEMATICD-079OS'''OOO7 -SO
UNLESS OTHERWISE SPECFIER:
r--
t __ -'I
I
ZONE 2
&.
T"'P.
'"IPLC5.
• -12L
• -12V
ei
1t1U
~
It 171
~
---
•
•
0111
0"1
~
•
Q17.
••••••••
..0..-.
fiJ
it&&£
--
• SPARE
e-II-_"1_----JJ-e
-
AUTOMAT1C INSERTION STANDARDS AS PER
AXIAL LEAD MANUAL DATED. 4- eo
I • THIS BOARD CONFORMS TO UNIVERSAL TEST
FIXTURES. ALL COMPONENT HOlES ARE ON
ONE - TENTH GRID CENTERS.
NOTES:
"STALl(DED AFTER LINE TEST.
~ ~PR.: 28.: MARK ASSEMSLY DATE CODE
F' ZSOI
=---
.+5V~
• .,2V
• .,2T
• .,2L
1 • THIS BOARD CONFORMS TO CORPORATE
I--.J
01.
Ii]
OPR. 285: MASK PRIOR TO LOADING.
~ OPR. 288: TOUCH lIP, INSTAU. (lAP;) ) THP.LJ
(MPe)
=
rn RC. PRODUCTION:
ORDER NUMBfR.
=--
.
=
MARIC ASSEMBLY
W'IIORK
& 13
GND
~. 21D~' I~ALL
~T !=>INS.
NUT
II
~
•
•
•••
~
~.~
~
~~
e-[!iii)-e
.-1
caM
f-e
•
.~
IlUO
1l1.
1-
-
i
l-
TYP. 2 f'LC8 •
..... -...
..
...
....• ••
H ....
•
•ell ••
~~
• •
•
•
~
~
~1._
f-e
•
•
~ ~~
@
IIIIiiiiie
1l1ft
I--.J
r-:..:
I
~
.,
..
P1 ..
".11 ..0..-.
~
~
~
':::
=
~
c--fi::i. ,.• :I-• ~7ClINF-;~
~I
•
6V
REF
•
2 Pl.C5
DE-TAIL
"AD MASTER
F- 07908-80007-3
C
0.110 (JI7Z J GI74
o.l3l/,Q.f3Z.,Q/3~. 0'3"
~PS
TYP
&
,
PL.C~
SEE OE'TA'L
~.
SE.E.. DE"TA.IL
C
NU'T
10-8-82
f- 0790&-80007-10
F- 07908-80007-12
INSL
2
TARGET MASTER
10-8-82
FLG. SUSHINC:,
--,-,
,+------------------------------------------HEW LET T - PAC K A R D C O.
NOTE:
I
I ER48 D/B: 50A/50B
I hp I
I
I -----------------------------+
This page provides a running history of changes for a multi-page
drawing which cannot conveniently be r~-issued completely after
each change. When making a change. list for each page all befor.and-after numbers (within reason; use judgement. and use
"extensive" revision note if loss of past history is tolerable. or
retype complete page) and associate with each a symbol made up of
the chanre letter and a serial subscript to appear here and on
the page involved (there enclosed in a eircle. triangle. or other
attention-gettina outline).
(L207)
LTR I
REVISIONS
B
CORRECTED PG 2. ADDED APPElfDIX A PER PPCO 48-4364
REVISED PER DATE CODE B,E-2203, PER PCO 48-4624
REVISED PER DATE CODE F-2232 PER PeO 48-4968
CHANGED MRST TIMING PER PeO 48-6354
I
1M
I
1 DATE 1 I.IT IF
---1--------------------------------------------------1--------1-------1-A AS ISSUED
12-02-81 SB/ML M
C
D
E
1-04-82
2-12- 2
10-13-)2
6-21- 3
SR,ML M
JMMJML
M
SR,ML M
CR,ML
----~----------------------. -------------------~------+_----_r-
--+---------+-------+---------+------------------+---------------------------ISR/ML 110-13-82 IMODEL 7908
ISTK , 07908-69007
1--+---------+-------+---------+------------------+---------------------------IE 148-6354 ICR/ML I 6-21-83 I UPDATE/REVISION PROC
1--+---------+-------+---------+-----------------------+---------.-------------IF Ico480015 ICR/ML I 6-28-83 IBY
IDATE 12-01-81
1--+---------+-------+---------+-----------------------+---------·--------------1
ILTI P.C.' I APPR I DATE
IAFPD
1SHEET , 1 OF 6
1
1--+---------+-------+---------+-----------------------+-----------------------1
I
REVlSIOIS
ISUPERSEDES
IDWG 'A-O,908-69007-1 I
+------------------------------------------------------------------------------+
ID 148-4968
+------------------------------------------HEW LEt' T - PAC K A R D
o.
C
I
I
hp
I
I
I
I
ER48 DIB: 50A/50B
-----------------------------+
UPDATING AND REVISION PROCEDURE
07908-69007
This procedure contains instruetions tor aoditieation ot the
regulator PCA, 07908-60007 to version 07908-69007.
1
I
I
I
I
1
1
I
II
REFERENCES :
SML:
07908-68007
07908-66007
Untested PCA
Reel
Dwgs:
F-07908-60J07-1
D-07908-60007-50
A-07908-60007-2
A-07908-60007-3
07908-80007
As.embly INc.
Sehematics
~e.t
procedures
Debua procedures
I
I
I
I
I
II
I
I
Tape aaster.
Production Changes:
48-~085
Fix ahorted pins p2-43,~4
48-4087
Change U344 tr'lD 1906-0249 to 1906-0248 (non-mandator,y)
48-4092
Change R206 to 11 (0757-0280)
48-4100
Chan.e VR281,VR378 to 1902-3193 (13.3V zener)
48-4136
Adds rework tor MRST,output load, SCR's
48-411,1,
Chan,. C318 to 1t7Opt (0160-3533) t adds 100 pF tro.a
U222-3 to ,round
48-4191
Chan,e R328 to 1.78K, chan,e U228 to DIP reaistor
48-4199
Implements Rev E board
48-4339
Implements chang. in Rev B rework
48-1t624
Improves margins tor triggering SCR crowbar circuits
48-4968
Implements Rev F Board
COlt80015
Stopped using
therm~l
compound (Non-mandatory Change)
--+---------+-------+---------+------------------+----------------------------1
ISR/ML 110-13-82 IMODEL 7908
1ST! , 07908-69007
,
1--+---------+-------+---------+------------------+----------------------------,
IE 148-6351, ICR/ML I 6-21-83 I UPDATE/REVISION PROC
1
1--+---------+-------+---------+-----------------------+-----------------------1
IF Ico480015 ICR/ML I 6-28-83 IBY
IDATE 12-01-81
1
1--+---------+-------+---------+-----------------------+-----------------------1
'LTI P.c. I
I APPR I DATE IAPPD
ISHEET ,
2 OF 6
1
1--+---------+-------+---------+-----------------------+-----------------------1
I
REVISIOBS
I SUPERSEDES
IDWG 'A-07908-69007-1 I
+------------------------------------------------------------------------------+
ID 148-4968
+------------------------------------------I
I
I hp
IRE WLIT T - PAC K A R D C O.
I
I
I
I
I
I
I
ER48 DIS: 50A/50B
-----------------------------+
t
I INTRODUCTION:
I
I This article will provIde information concerning the eligibilty ot
J the regulator board tor revision and also concerning the revisions
themselves.
I
I
I
I
I
I
I
t
REVISABLE ASSEMBLIIS:
The tirst asse.bly which .~ be revi.ed is B-2108. All prior
assembli.s are to be scrapped. Also scrap any C or D revision
boards.
1
J
I REVISIONS:
I
I
I
B-2108
I
I
B-2118
I
I
B-2126
I
J
1-2126
J
I
I
I
~
J
48-~100t~092t4087,4085
48-4136,4144
48-4191
48-4199
B,I-21~0
48-4339
B,I-2203
48-4624
F-2232
48-4968
F-2300
48-6354
)
•
I
I
I
I
1
I
I
CURRENT ASSEMBLY:
B,E-2300; F-2300
F-23C1
I'
I
I
I
I
I
.--+---------+-------+---------+------------------+-------------_._------------ID 148-4968 ISR/ML 110-13-82 IMeDEL 1908
1ST! , 07908-69007
1--+---------+-------+---------+------------------+-------------_.-------------IE 1~8-6354 ICR/ML I 6-21-83 I UPDATE/REVISION PROC
1--+---------+-------+---------+-----------------------+---------.-------------IF Ico480015 ICR/ML I 6-28-83 IBY
IDATE 12-01-81
.--+---------+-------+---------+-----------------------+----------------------ILTI p.e., I APPR I DATE
IAPPD
1SHn:T' 3 OF 6
,--+---------+-------+---------+---------------------+----------------------,
REVISIONS
1SUPERSEDES
iOWG , A-07908-69007-1
+----------------------------------------------~-------------------------------
+------------------------------------------B E W L E '1 T - PAC K A RD
C O.
I
I
I
hp
I
I
I
ER48 DIH: SOA/50B
-----------------------.------+
1.0
Inspect all boards for general •• chanical and co ••• tic dof.cts
per ~-5950-9205-1. Repair all component malfunctions.
2.0
IdentitJ all boards with the followina loco:
07908-69007
2300
To replace existing 10,0.
3.0
Affix t near the logo t • 7120-5480 label which has been stamped
with the month and year of tinal inspection.
--+---------+-------+---------+------------------+---------------------------ISR/ML 110-13-82 IMODEL 7908
ISTK , 07908-69007
•
1--+---------+-------+---------+------------------+----------------------------1
IE 1a.a-6354 ICR/ML I 6-21-83 I UPDATE/REVISION PROC
I
1--+---------+-------+---------+-----------------------+-----------------------1
IF Ico480015 ICR/ML I 6-28-83 IBY
IDATE 12-01-81
I
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR I DATE
IAPPD
ISHEET' lJ OF 6
I
,--+-------- ._+- - -----+---------+--------------------- --+-------------- -- - --·----1
ID 148··11968
I
REVISIONS
ISUPERSEDES
lIM; 'A-07908-6900jr-1 I
+- ---------- ._-- --- ----------- ---- ------ ------- - - ------- ----------------- --_._---+
+------------------------------------------- I I hp / I ER48 D/B: 50A/50B
B E WLET T - PAC K A R D C O.
I
I -----------------------------+
~.O
On board
revision:
B-2108
(to Cet 2U8)
A) Insure that the trace troll p2-~4 to nearest feedthru
has been cut. Also that there is a wire fro. u242-14 to
p2-44. See Mod. DNa. F-07908-60007-20.
B) Irote:
U34~ .1.1' be
either 1906-0249 or 1906-0248
C) It R206 i. no~ 1.OK ohml. replaee with 0757-0280.
D) It
VR281 and VP378 are not 13.3V replace with 1902-3193.
E) It u262 hal • 1X network resistor loaded. replace with
a 5.1lE (0757-0438) in the location tor pins 3.14.
Rerer to Mod. Dwg. r-20 and hlY DYI. F-1.
F) Make other .oditieationl per F-07908-60007-20
e318 i. 100 pf replace with 470 pt (0160-3533)
add 100 pi (mod 10) 0160-2204 trom U222-3 to ground.
Refer to Mod. Ow,. F-07908-60007-20.
G) It
I 4.1 On board revision:
B-2118
(to .et 2126)
A) Replace R328 with 1.78K (0757-0278)
B) It the header at U228 il detective. remove and replaee
with 57K network resi.tor (1810-0455).
It the header i . ,ood. 40 Dot replaee it.
4.2 On board revision:
B-2126
(to .et
21~)
A)
Move resistor and zener diode trom eonnector area to
spare DIP location and put on test pins.
B)
Install eyelet on edge COllllllector finger and install
Jumper. (Rework current jumper).
Refer to Mod.
Ow,.
F-07908-60007-20 Rev c.
--+---------+-------+---------+------------------+---------------------------ISTK , 07908-69007
1--+---------+-------+---------+------------------+----------------------------1
IE 148-6354 ICR/ML I 6-21-83 I UPDATE/REVISIOH PROC
1
1--+---------+-------+---------+-----------------------+-----·------------------1
IF Ico480015 ICR/ML I 6-28-83 IBY
IDATE 12-01-81
I
1--+---------+-------+---------+-----------------------+----·-------------------1
ILTI P.C.' I APPR I DATE
IAFPO
ISHEET ,
5 at 6
I
1--+---------+ -------+---------+-----------------------+------------------------I
JD 148-q968 ISR/ML 110-13-82 IMODEL 7908
I
~~:OIS
I SUPERSEDES
IDWG ,A-07908-69007-1
I
+-- - --- --.- - -- - --- ------ - ---- ----- - -- - - --- - --- -------- ----- --.. - - -- - -- - - - - -- - -- --+
+-------------------------------------------I I hp
B E WLET! - PAC K , R D C o.
~.3
On board revision B,E-2140
A)
~.4
4.5
ER48 DIB: 50A/50B
-----------------------------+
(to get 2203)
F-2232
Replace R262 with a 1101 (0157-0466).
with a 162K (0757-0410).
(to get 2300)
Replace R250
On board revision B,E-2300i '-2300; 2301
A)
4.6
I
I
Remove res istors R362, R312. R386 and replace
with 38.3 ohm resistor (0698-3435).
On boLFd revision S, E- 2203i
A)
I
I
Current Assemblr
Test per
A-07908-60001-3
--+---------+-------+---------+------------------+-------------------------ISR/Nt 110-13-82 IMOIEL 7908
ISTK , 01908-69001
,--+---------+-------+---.------+-.. ----------------+---------------------------IE 148-6354 ICR/ML I 6-21-83 I UPDATE/REVISIOJl PROC
1--+---------+-------+---------+-----------------------+----------------------IF Ico480015 ICR/ML '6-28-83 IBY
IDATE 12-01-81
1--+---------+----- .-+---------+-----------------------+----------------------ItTI P.C.' I APPR I DATE
IAPFD
1SHEET ,
6 OF 6
,--+---------+-------+---------+-----------------------+-----------------------1
I
REVIS:UlrS
ISUPERSEDES
IDWG 'A-01908-69001-1 I
+------------------------------------------------------------------------------+
ID 1~-4968
E
A
F
---~T.-
•
,tt)
4c~
~ zw ...
g
1· C~4
C.Rl.iJ.
t\Z.V
iPISe
)45 V
r---------------~~----._--_r--~_.----------------------~----------------~----------~----~--------------------~{.'nl~D~
CRl~
•
~
TPIS("
I~~
'iJ
.t
CP.ZB!>!
TP~
t)
r-----------+-~--------+__+--+__r------------------------------------+_--------_+--------------------------~,Il~~
2
\-I1Y "..,,~
nll!ll
ClNO
-
r-;;=I ... 1-_-_-:-___
------1-1_-:-. ._.-_
. 1-..__ 1-'"-'-.
J m=
_.. ,...
P IN 07908-60006
SERVO PCA-A2
Series Code E-2338
+------------------------------------------B E WLET T - PAC K A R D C O.
I
I ER48 D/B 50A
I hp I
I
I -----------------------------+
This page provides a running history ot changes for .. aulti-page
drawinc which cannot conveniently be re- issued c:ompl,etel.y after
each change. When lIaking a change, list for eac:h page all beforeand-after nua~rs (within reason; use judgement, and use
"extensive" revision note if loss of past history is tolerable, or
retype complete page) and associate with each a symbol made up of
the change letter and a serial subscript to appear here and on
the pale involved (there enclosed in a circle, triangle, or other
attention-getting outline).
(L40o)
ROTE:
I
111M
REVISIONS
1 DATE I IRIT IF
---1--------------------------------------------------1--------1-------1-AS ISSUED PER pco48 -4919
A
10-19_-83 srlCW M
LTRI
B
REVISED PER C0480296
09-28-83 db/ML
1
--+---------+-------+---------+------------------+---------------------------Isr/CW 110-01-82 IMODEL 7908P/1908R ISTK , 07908-60006
1--+---------+-------+---------+------------------+---------------------------IB Ico480296 Idb/ML 109-28-83 1 SERVO-IHS
1--+---------+-------+---------+-----------------------+-----------------------1
I I
I
I
IBY
IDATE 10-07-82
I
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR I DATE
IAPPD
1SHEET ,
1 OF 35
I
1--+---------+-------+---------+-----------------------+-----------------------1
I
REVISIONS
1SUPERSEDES
IDWG 'A-07908-60006-1 I
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------- I I bp I I ER48 D/H 50A
B E WLET ~ - PAC K A R D C O.
/
I -----------------------------+
INTERNAL MAINTENANCE SPECIFIATIOH
7908 SERVO PCA
IRTRODUC'l'IOH
I.
A.
B.
Purpose/Functions of Servo PeA
Overview of bow IMS is organized.
II •
RELATED DOCUMEM'l'S
III.
FUNCTIONAL BLOCK DESCRIPl'IOlfS
A.
B.
C.
D.
E.
F.
G.
H.
I.
J.
K.
L.
IV.
Interface Block Diagram
Signal List
Servo Board Block Dialram
Carrier Amplifier
Peak Detection/Position Sipal Generation
Phase-locked Loop
Position Comparators
~rack Following Loop
Seek Electronics
Power Amplifier
Diapostic Hardware
Servo Calibration
TECHNICAL DESCRIPl'IONS
A.
B.
C.
D.
E.
F.
G.
B.
Tri-bit Servo Recor4inc Pattern
Position Sienal Generation
Phase-locked Loop
Servo Bit Pattern Detection
Track Following Loop
Track Seekin,
Power Amplifier
Diagnostic Signal Injecto~
--+---------+-------+---------+------------------+---------------------------I.r/CW 110-01-82 IMODEL 1908P/7908R 1ST! , 01908-60006
1--+---------+-------+---------+------------------+---------------------------IB Ico480296 Idb/ML 109-28-83 I SERVO-IMS
,--+---------+-------+----------+-----------------------+----------------------I I
I
1
IBY
IDATE 10-01-82
,--+---------+-------+---------+-----------------------+-----------------------1
',TI P.C.' 1 APPR I DATE
IAPPD
I SHEET ,
2 at 35
I
IA IISSUED
~-+---------+-------+---------+-----------------------+-----------------------1
I
REVlS I OIS
I SUPERSEDES
IDWG 'A-01908-60006-7 I
+-----------------_.------------------------------------------------------------+
+------------------------------------------I
/ ER48 D/H 50l
1
/~/
J B E WLET T - PAC K A R D C O.
/
/ -----------------------------+
I
I
I
J
,
I
I
J
LIST OF FIGURES
Ficure 1:
Interface Block Diagram
Figure 2:
Servo Block Diaaraa
Figure 3:
Tri-bit Servo Code
Fieur- It:
IMI Track Format
Figure 5:
Carrier Amp Block Diaera-
Figure 6:
Peak Detector/Position Generator Block Diagram
Figure 7:
Peak Detector Timina
Figure 8:
PLL Phase Detection
Figure 9:
Sync Bit Timinc
Figure 10:
Tracking Loop Block Diaaraa
:rigure 11:
5-'l'rack Seek
--+---------+-------+---------+------------------+----------------------------1
Isr/CW 110-07-82 IMODEL 7908P/7908R ISTK , 07908-60!006
1
1--+---------+-------+---------+------------------+----------------------------1
JB IC0480296 Idh/ML 109-28-83 I SERVO-!MS
1
IA IISSUED
I--+---------+-------+--------~+-----------------------+-----------------------1
I
I
I
IBY
IDATE 10-07-82
1
J
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C. I I APPR 1 DATE IAPPD
ISHEET , 3 OF 35
1
1--+---------+-------+---------+-----------------------+-----------------------1
I
ftEVISIClfS
ISUPERSEDES
IDWG 'A-01908-6oo06-7 1
+--------------------------------------------------------_._----_._-------------+
+------------------------------------------,
B E V LET T - P A CX A R D C O.
I
I
hp
I
I
INTRODUCTION
I-A
Purpose/Functions of Servo PCA
I
I
I
ER48 DIB 50l
-----------------------------+
1.
Obtain actuator position information b,y readtng the
tri-bit .ervo code trom disc.
2.
Derive clock fro. servo code for .ector timina and
write data clocktng.
3.
Generate index pulae. outer cuardband. and inner
guardband signals from servo code.
~.
Provide electronics for track following loop.
5. Provide amplifier for actuator coil.
6.
Provide uP interface for s.eking.
7. Servo Specifications:
Average physical seek time:
36 .s.c.
8.3 ..s.c.
Avera,e latency:
Sinlle track aeek tille:
5 IIsec.
65 .sec.
379 track seek:
Seek soft error rate:
1 in 10"'6
1--+---------+-------+---------+------------------+----------------------------1
IA IISSUED
Isr/CW 110-01-82 IMODEL 7908P/7908R 1ST! , 07908-60006
I
1--+---------+-------+---------+------------------+----------------------------1
IB Ic0480296 Idb/HL 109-28-83 1 SERVO-INS
I
1--+---------+-------+---------+-----------------------+-----------------------1
1 I
1
I
IBY
IDATE 10-07-82
I
1--+---------+-------+---------+-----------------------+-----------------------1
'4TI P.C.' I APPR 1 DATE
IAPPD
ISHEET , ~ CF 35
1
~-+---------+----.---+---------+-----------------------+-----------------------1
I
REVISIONS
1SUPERSEDES
Iowa 'A-07908-60006-7 I
+------------- --_ .. ------------------------------------------------------------+
+---------,-------------------- -------------- /
/ hp I
B E WLET T - PAC K A R D C O.
I-B
Overvie~
of
ho~
/
/
/
:m48 DIB 50A
-----------------------------+
IMS is organized.
Section 3 presents a functional block diagram of the
servo board and explains how it interfaces ~ith 'the
rest of the product. Each sect ion in the block is then
described in a ceneral way to provide an understand iDe
of how 'the board functions.
S.ction ~ provides aore in-depth technical and design
details on ho~ the hardware functions.
II
RELATED DOCUMENTS
A.
IRS
B.
Test Proeedures
Diagnostic. INS
Seek INS
Servo Adaptation INS
Lab Hotebook.
DMD Journal Article.
C.
D.
E.
F.
Q.
III
FUNCTIONAL BLOCK DESCRIPTIONS
III-A Interrace Block Diacram
Firure 1 illu.trate. how 'the .ervo PeA phy.ical~
interact. with the power 8Upp17 (reculator PeA),
read/write board, microproce.sor board, and the IMI
disc a.chani••.
)
I
I
I
I
I
I
I
I
I
1--+---------+-------+---------+------------------+-------------.--------------IA IISSUED
Isr/CW 110-07-82 IMODEL 7908P/7908R ISTK , 07908-E;oo06
,--+---------+-------+---------+------------------+------------_._-------------IB Ico480296 Idb/ML 109-28-83 I SERVO-IMS
1--+---------+-------+---------+-----------------------+--------.--------------I I
I
I
IBY
IDATE 10--07-82
1--+---------+-------+---------+-----------------------+-----------------------ILTI P.C. I I APPR I DATE IAPPD
ISHEET ,
5 OF 35
1--+---------+-------+---------+-----------------------+-----------------------I
REVISIONS
ISUPERSEDES
IDWG , A--07908-60006-7
+-------------------------------------------------------------------------------+
+------------------------------------------HEW LET T - PAC K A R D C O.
III-S
I
I ER48 D/H 50A
I bp I
I
I -----------------------------.'
Signal List
INPUTS TO BOARD
uP:
SAL:
Enable A
Enable S
Read Enable
Write Enable
Ha.ter Reset
Board
Board
SSL:
ROL:
WRL:
MRSTL:
DATA BUS:
2 input latchc~ a. folloR
BOARD ENABLE A WITH WRL
2'. complement 8 bit. to DAC for current command
BOARD ENABLE B WI'l'H WRL
DO:
Dl:
D2:
D3:
D4:
D5:
D6:
D1:
CVHL--C,ylinder Even (odd or even track tollow)
PMDS--Position Mode (track tollow enable)
SKH---SAek RiCh (enable current comaand)
YFB---Yellow Function Button (secondary latch clock)
TEH---Test Enable (enable .ienal injector)
TFOH--Track Follow Ott.et (de.ensitize ott-traek
comparilon)
unused
RVOH--Rever.e Direetion
MECH:
SSl, SS2:
Difterential .ervo .ienal. trom bead amplifier
POWER SUPPLY:
+12L:
-12L:
+12V:
-12V:
+5V :
DGJID:
AGND:
LGND:
Low power--15Oma
Low power--18Oma
Servo actuator power--2 Amps peak
Servo aetuator power--2 Amps peak
Logie power--10Oma
Digital Ground
Servo actuator ,round
Analog low power ,round
--+---------+-------+---------+------------------+---------------------------Isr/CW 110-01-82 IMODEL 7908P/1908R ISTK , 07908-60006
,--+---------+-------+---------+------------------+---------------------------IB Ico480296 Idb/ML 109-28-83 I SERVO·IMS
,--+---------+-------+---------+-----------------------+-----------------------1
I I
I
I
IBY
IDATE 10-07-82
I
1--+---------+-------+---------+-----------------------+-----------------------,
ItTI P.C.' I AP.PR I DATE
IAFPD
I SHEET , 6 OF 35
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REVISIOJlS
ISUPERSEDES
IDWG 'A-07908-60006-7 I
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------/ /
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J B E W LET T - PAC K A R D C O.
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ER48 D/B 50A
/ -----------------------------+
OUTPUTS FRC»J BOARD
uP:
I
SERVO
RBO:
RBl:
RB2:
RB3:
RB4:
RB5:
RB6:
RB7:
STATUS LIKES
CYL---c,ylinder addr LSB (CVHL ~ed back)
IDXL--Index pul•• (3 uSEC)
ONH---On Track (+/-lV window)
TCH---Traek Cro •• Pul •• (pul•• at zero crossing)
DIFB--Dirt.rentiator phase
IGBL--Inn.r Guard Band
OFH---Otr ~ek (+/-2.5V window)
OGBL--Outer Guard Band
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TKX:
Track Cro •• pulse to eTC chip (sam. as TCB)
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DATA BUS
BOARD ENABLE B WI'l'H RDL
DO:
Dl:
D2:
PLL--Pha.e Lock (inver•• or PLEL to F/lateh)
LMH--L1near Motor (>1 volt on motor coil)
PLEH--Pha.e Lock Error (ill.,al .ervo patter.n)
R/W:
P2L:
P8L:
PMDL:
PLEL:
ONH:
Servo clock (648 KHZ)
Servo clock (2.59 MHZ)
Position M04e
Phase Lock Error to Fault Latch
On Track (a180 to Fault Latch)
MECH:
LMAt LMB:
-8.2R:
GN'D:
SP, SM:
Linear Motor Drive lines
Servo head amplifier supply
Servo head amplifier ground
Carriage loek solenoid power
1
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IA IISSUED Isr/CW 110-07-82 IMODEL 7908P/7908R 1ST! , 07908-60006
I
'J--+---------+-------+---------+------------------+----------------------------1
B Ico480296 Idb/ML 109-28-83 I SERVO-INS
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1--+---------+-------+---------+-----------------------+-----------------------1
1 I
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IDATE 10-107-82
1
1--+---------+-----+---------+-----------------------+-----------------------I
fLTI P.c., 1 APPR 1 DATE
IAPPD
1SHEET ,
7 OF 35
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1--+---------+-------+---------+-----------------------+-----------------------1
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REVISIONS
I SUPERSEDES
fDWG 'A-07908-60oo6-7 1
+------------------------------------------------------------------------------+
+------------------------------------------- /
HEW LIT T - PAC K A R D C O.
III-C
/
BR48 D/H 50A
/ hp /
/
/ -.---------------------------+
Servo Board Block Diagram
Figure 2 presents the functional block dia&r&m of the servo
board. 'lbe uP controller communicates to the .ervo PeA by
sending eomands across the ~~~a bu. while activating the proper select lines (SAL or SSL) with WRL alserted. by reading
the data bus with select line and ROL. or by reading the
.ervo status word. Functional descriptions are included in
the following paragraphs.
III-D
Carrier Amplif'.,r
The carrier amplifier's purposes are:
1.
2.
3.
4.
/1
Amplify differential servo signals coming fro.
the .ervo head preamplifier
Provide low pa•• filtering
Provide Automatic Gain Control with the amplification
Convert amplified differential sianals to .~le
ended sienal for use by the peak detector.
The .ervo ~ignals contain a tri-bit servo pattern (see
Section IV for explanation) with a fundamental frequ.ncy
of 324 KHZ.
The carrier amp output signal drives the pet..i< detectors and
also creates a sync pulse tor the phase-locked loop.
III-E
Peak Detection/Position Signal Generation
The two positive peaks or each cell or the carrier amp
tri-bit signal are detected and held by active peak detector••
The voltace level of the two peaks is summed and forced to be
a constant level via AGe feedba'k to the carrier ~nplirier.
~e difference or the two peaks is used to generate a signal
proportional to servo he~d distance trom track center (Position
Signal or Position Error Signal).
--+---------+-------+---------+--------.---------+---------------------------Isr/OW 110-07-82 fHODEL 7908P/7908R ISTK , 07908-60006
1--+---------+-------+---------+------------------+---------------------------IB Ic0480296 Idb/ML 109-28-83 I SERVO-IMS
1--+---------+-------+---------+-----------------------+-----------------------1
1 I
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IDATE 10-07-82
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ILTI P.C.' I APPR I DATE
IAPPD
ISHEET ,
8 OF 35
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(
~SIONS
ISUPERSEDES
IDWG 'A-07903-60006-7 I
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------- I I hp
HEW LET T - PAC K A R D C O.
III-F
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/
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ER48 DIs 50A
-----------------------------+
Phase-locked Loop
The negative swing of the CA output creates a sync pulse every
3 microseconds (324 KHZ). The servo phase-locked looped locks
onto this sync pulse and Ilultiplies it. frequency b7 16. The
8x frequency (P8L signal) is sent to the R/W board tor use in
in write data clockgenention. The 2X frequency (P2L signal)
i. al.o .ent to the R/W board tor byte counting ad .ector
timing. The 1X frequency (PCK) is used by the .ervo peak
detectors to determine proper peak detection windows.
Some unique p"ttern. of rlttssing pul.es in the servo signal. are
detected by the servo board to produce a once-around index pul.e
(for usc in sector counting) and both inner- and outer-auardband
detection. Tbere are 30 outer-auardband tracks outside track 0
(the fir.t valid data track) and up to 17 inner-guardband tracks
ins ide track 389.
111-0
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Position Comparators
The position sienal is u.ed to create an "on track" indication
(ONH). an "off track" indication (OFH). and a track cro •• pul••
(TCH and TKX). The "on track" indicator i. a nalTOW window
around track center which remain. active when the .ervo head
i. po.ition.d within 12J or the track c.nter. The "oft track"
indicator i. u •• d b.Y the .e.k routine to indicate 3~ ott track.
A track cro.s pulse is created each tim. the po.ition .ianal
cro •••• through zero volt. (track center).
The •• comparator level., or "window.", can be widened to twice
their normal size by activating the TFOB command bit. Thi.
permit. track following with off.et to about 24~ oft track betore trigg~ring ONH low.
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1--+---------+-------+---------+------------------+----------------------------1
JA 11Sst'ED
lar/Cil 110-07-82 IMODEL 7908P/7908R ISTK , 107908-60006
I
1--+---·-----+------- .-------+------------------+----------------------------I
is Ic04B0296 Idbiffu : ~'. -28-83 I SERVO-INS
1
t--+---------+-------+ .--------+-----------------------+-----------------------I
til
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IBY
IDjU'E 10-07-82
1
1--+--------- -------+---------+-----------------------+-----------------------1
ILTI :~.r., 'APPR 1 DATE
IAPPD
ISHEET' 9 OF 35
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ISUPERSEDES
IDWG 'A-07908-6oo06-7 1
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+---~~-------------------------------------- I
B E W LIT T - PAC K A R D C
III-B
Track
Follo~inl
o.
/
/ hp /
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ER48 D/B 50A
/ --------------------.. --------+
Loop
For track following th~ position signal is ~iltered and
passed on to) the Linear notor Current amplifier when the PMOH
(Position Mode Bigh) co~and bit ia enabled. !he two
integratl~us (acceleration to position) through the Linear
M~tor Coil require lead compensation in the tracking loop
~ilt.r ~or stahility.
The tracking loop will keep the
position signal around zero volts when following a track
center .uccesstully.
Track following with orrset is po~8ible by enabling both PMOH
and SIB (track tollow ftnd ~eek). jbe orrset aagnitude i.
then controlled by the DAC voltage injected into the loop.
111-1
Seek Electronics
For .eeking, the actuator is accelerated (or decelerated)
acro •• the disc on command ot the uP controller. The
controller sends an actuator coil current co_and through an
8-bit Digital/Analog converter (DAC) which is ,ated through
to the Linear Motor Current amplifier when the seek bit i.
enabled. The current coaanand direction i. determined by the
RVDH command bit. Current direction can also be aanipulated
by the 2
complement command word to the DAC. Thi. 2
complem.nt capability also facilitates current command
ott.et. during track tollowin, and .eeking.
I.
I •
While the .ervo h.ad moves across the di.c. theuP receiv•• track cro.sing pul ••• and various level
comparator output. trom the position sirnal. A desired
actuator velocity protile a. a function ot distance to
target track is resident in the uP. The uP counts track
crossing pulses to determine distance-to-go information
and measures the time between track crossing pulses to
determine velocity intormation. The software seek
algorithm then determines the actuator current command
to bring the actuator velocity in line with the desired
velocity profile.
--+---------+-------+---------+------------------+-------------------------..
_'sr/CW 110-07-82 IMODEL 7908P/7908R 1ST! , 07908-60006
1--+---------+-------+---------+------------------+-------------------------.-IB Ico480296 Idb/HL 109-28-83 I SERVO-IMS
1--+---------+-------+---------+-----------------------+----------------------, 1
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IDATE 10-07-82
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAFPD
ISHEET' l.0 OF 35
1--+---------+-------+---------+-----------------------+----------------------I
REVIS I OKS
ISUPERSEDES
IDWG , A-07908-60006-7
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------I
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III-J Linear Motor Current Amplifier
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ER48 D/B 50A
-----------------------------+
A voltage proportional 'to the Linear Motor Current c:ommand is
gated to 'the power amplifier via 'the PMDH and/or SKH command
bits. This power stage is a high gain amplifier with current
sense feedback and high frequency roll off to preven.t
oscillations.
If the command bits PMI:II and SKH are both low (by either
controller command or .aster rese't). the amplifier is
disabled and a "retract" current of about l80ma pulls the
actuator to the outside. This is to Ket the heads otf of the
data area &f!c! into the "park zone" or "landing area" on the
outside diameter in case of power failure or other problems.
~ power down the 180ma retract current will be main·tained
tor a few tenths of a .econd and a mechanical carriage lock
will catch and hold the head assembly in the park zone.
I
I
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III-I
J
The purpose ot the diacnostic hardware is to isolate 'the
cause of servo tailures to either the IMI mechanism or the
servo PCA. Considerable intormation c&n be obtained throu,h
"normal" hardware channels - Position Sienal Comparators. DAC
command. etc. The carrier amp. AGe. Peak Detectors, and
phase-locked loop can be verified by injecting an on board
cenerated test sianal into the carrier amplifier (enablinc
TEll cOlMland bit will do this). The phase lock detect~ circuit
and poSition .ianal comparator. can then be checked for
proper behavior to determine board integrity. A Linear Motor
Coil voltace .ensor can also report to the processor whether
voltage is being applied to the coil.
,
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)--+---------+-------+---------+------------------+---------------------------Isr/CW 110-07-82 'MODEL 7908P/7908R ISTK , 07908-60006
1--+---------+-------+---------+------------------+---------·-------------------1
JB Ico480296 Idb/HL 109-28-83 I SERVO-IMS
I
1--+---------+-------+---------+-----------------------+----··------------------1
I I
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1
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ItTI P.c" , I APPR I DATE
IAPPD
I SHEET , 11 OF 35
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REVISIONS
ISUPERSEDES
IDWG 'A-07908-6oo06-7 I
+-----------------------------------------------------------_._-----------------+
IA IISSUED
+------------------------------------------- I I hp
HEW L E ~ T - PAC K A R D C O.
III-L
/
/
/
/
ER48 DIH 50A
-----------------------------+
Servo Calibration
Three important measurements of drive servo par3ll1eters are
made when poller is applied to the unit. These measurements
are:
1.
DC actuator force (such as Cravity).
2.
Effective linear motor force constant.
3.
Track center spacinc.
These parametors directlY affect track follow and aeek
perfonnance. Instead of requiring manual offset measurements
and adj1l.stments the uP measures and nulls these .ffects. 1'I1e
IX: force is nulled by an offset to the current command duriq
both seeks and track following. The motor torce constant is
offset by adjusting the DAC gatn via hardware on the servo
board. The track center spacing can also be adjusted with
position sienal offsetting via board hardware.
,1--+---------+-------+---------+------------------+---------------------------IA IISSUED
Isr/CW
110-01-82 IMODEL 7908P/1908R
ISTK ,
01908-60006
1--+---------+-------+---------+------------------+---------------------------IB Ic0480296 Idb/ML 109--28-83 I SERVO-IMS
1--+---------+-------+---------+-----------------------+----------------------1 I
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IDATE 10-01-82
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' 1 APPR I DATE IAPPD
ISHEET' 12 OF 35
1--+---------+-------+---------+-----------------------+----------------------I
REVIS I OIlS
I SUPERSEDES
I DWG , A-01908-60006-'T
+------------_._----------------------------------------------------------------+
+------------------------------------------- I I hp
HEW LET t - PAC X A R D C O.
/
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ER48 D/H 50A
-----------------------------+
IV. TECHNICAL DESCRIPTIONS
This section will provide teChnical and design details not
presented in Section III.
IV-A Tri-bit Servo Recording Pattern
The underside of the lowest disc platter contains a dedicated
servo surfac. for cont inuous" selVo feedback. r igure 3
illustrates how IMI encodes a tri-bit servo pattern ~nto the servo
surface. The sync pulse magnitude will be constant since it is
coincident on both "A" and "8" servo tracks. The S7DC pulse is
used to set up tbtinC windoWli to sample (peak detect) the A and B
field magnitudes. A+B is forced to be a const&nt via the AGe
circuit. A-8 (or 8-A, depending on even or odd cylin,c!er) is used
to produce a signal proportional to head position. A typical
sirnal level comLng from the se~o head preamplifier (differential
SSl and SS2 signals) might be 6o.v O-to-peak for the sync pulse.
The signal levels on tracks near the outside diameters may be up
to 10~ Ireater than on tracks near the inside. Figure ~ shows
the servo track fonaat. There is DO servo code written in the
"park" zone. Th. inner- and outer-cuardband areas have unique
patterns encoded on the servo surface so that they can be detected
(S•• Section IV-D).
II
1
IV-B Position Sienal Generation
,
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Th. differential servo signals fro. the disc (SSl and SS2) are
lated throulh the analog switch (U111) when TEH is low Csee Figure
5). TEB high ,at.s the diagnostic signal througb (see section IVH). Ul12 is an IF amplifier with a voltage sensitive gain control
input OD pin 5. The output filter network on Ul12 provides three
low pas. poles at about 2 MHz. Typical differential signal
amplitude at the opposite ends of R205/R206 is 1 volt O-to-peak
for the sync pulse. The transistor array network (U311) provides
dual- to singleended signal conversion. amplification (about 5).
and proper placpment of the output around 0 volts. This output i.
called the carrier amp, or CA signal.
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,--+---------+-------+---------+------------------+---------..
-----------------'A IISSUED
Isr/CW 110-07-82 IMODEL 7908P/7908R 1ST! , 079C8-6ooo6
,--+---------+-------+---------+------------------+--------_._-----------------IB Ic0480296 Idb/ML 109-28-83 I SERVO-IMS
1--+---------+-------+---------+-----------------------+----..
-----------------I I
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IDATE 10-07-82
1--+---------+-------+---------+-----------------------+----_.----------------ItTI p.e., I APPR I DATE
IAPPD
ISHEET' 13 OF 35
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REVISIONS
'SUPERSEDES
IDWG , A-07908-60006-7
+------------------------------------------------------------------------------+
+------------.. ..-----.--------------------- /
B E WLET i
~ A C K A R D C o.
I ER48 D/H 50A
I hp I
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Figure 6 gives a block diagr~D showing the peak detectors and
position signal generators. The CA signal is presented to the
diode array (U231) for peak detection. When enabled, Q134 and
Q135 are active sources tor driving C226 ar.~ C231 to tte positive
peak volt..,.. Q134/135 are enabled in turn by the Phase-locked
Loop to 'coincide with the A and 8 servo fields (see Figure 7).
Q228 and Q229 with their respective emitter resistors cause a
constant current (138 ua.) to ramp dOMn the peak capacitor
voltage at a constant rate (63mV/usec). U252 pins 1 and 1 are the
buffered A and 8 peak detector outputs trom which the sum and
differences are taken tor AGe and Position circuits, respectively.
The purpose ot the AGC circuit is to force a constant A+B
mapi tud~ (about 6v.). This is important because the resul tine
volts/inch at the position signal (typically 2520 V/in or 8.4
v/track at PES1) needs to be held fairly constant. Otherwise
track inc loop gain and position signal comparisons would vary tro.
drive to drive and trom track to track within a drive. Ul12
provides a range ot 60dB ot power gain as pin 5 goes trom +5 to +1
volts. It normally operates around 6 v. so a tiltered +12 V. is
sWIIIJed with the Ul22 output. which then operate I around ground
potential. This summation/attenuation eives added resolution and
noise immunity at 11122. Ul22 is a dual op amp used on'.y in the
AGe because I have previously had crosstalk into the lensitive AGe
circuit from a shared quad device.
When an even cylinder is selected the 8-A signal eenerat.1 a
voltaee proportional to position at U252 pin 8 (PES1). This It.,e
providel hieh trequency roll-ott with a single low pasl tilter at
5.6IHz. A second order Butterworth low pais tilter at 10.7KHz and
unity gain produce. PES2 trom PES1. PES2 also allowl tor voltaee
ottsetting through signal OFS by controller command (lee' section
IV-F). The OFS signal thr: ~ R313 causes a slight attenuation in
the Position signal magnitUde (2.5~) trom PESl to PES2.
--+---------+-------+---------+------------------+---------------------------Isr/CW 110-01-82 IMODEL 7908P/7908R ISTK , 01908-60006
1--+---------+-------+---------+------------------+---------------------------IB Ico480296 Idb/ML 109-28-83 I SERVO-IMS
1--+---------+-------+---------+-----------------------+----------------------I I
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1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR 1 DATE
IAPPD
ISHEET' 14 OF 35
1--+---------+-------+---------+-----------------------+----------------------I
REVISIOJIS
1SUPERS::DES
IDWG , A-07908-60006-7
+-----------_._-----------------------------------------------------------------+
IA IISSUED
+------------------------------------------- / /hp
HEW LET T - PAC K A R D C O.
IV-C
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ER48 D/H 50A
-----------------------------+
Phase-locked Loop
The CA signal is nm through a -2.5 V. comparison (11541 pin 2) to
create the logic signal SHCH. SHCH is used to ~rive the Phaselocked Loop and plays a vital role in the pattern detect circuits
(see section IV-D). The LM339 comparator (U541) ha. a specified
typical large signal response time ot 300 nsec., but no maximum
specification is given. In this application the optimum response
tilDe is about 190 nsec. or less. Slower response times result in
peak detector windows being delayed so that the "A" sample period
111&1 overlap the beginning of the "s" peak. Certain manufacturers
and certain date code part& are, in fact, too slow ~or this
application (Motorola, Texas Instr. 8109 date code). A new BP
part number will lik_l1 be set up with the response time specified
to fit our application.
3) is provided tor in the SICH side
ot the phase detector. This i. for the pattern detect circuitry
to inject a pulse in the event SHCB is missinc (see .ection IV-
An additional input (0571 pin
D) •
A recent change vas lIade to the charge pump in the PLL to compensate
tor the phase error induced b,y 0541 and other components in the
circuit. This include. changing CR247 to a Schottky diode and
lowertnc R159 frOID 5.111 to 4.641. The etfect of this change 1~ to
speed up the response ot the amplifier Ql57/158 to SNCB and, as a
result lessen the phase error between SHCH and PCI when the loop i.
locked. Thi. also increases the lain of SHCB through the amplifier
which makes noise more likely to disturb the PLL, but is necessar.y
to adequately decrease the phase error. Lowering the lain of PC!
was considered as a method of reducina the phase error, but it did
not have enough aftect to cure the seek problems that were occuring.
--+---------+-------+---------+------------------+---------------------------Isr/CW 110-07-82 IMODEL 790SP/7908R ISTK' 0790S-Ei',0006
1--+---------+-------+---------+------------------+----------------------------1
IS Ic04S0296 Idb/ML 109-2S-83 1 SERVO-IMS
1
1--+---------+-------+---------+-----------------------+-----------------------1
I I
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I,LTI P.C.' I APPR I DATE
IAPPD
ISHEET' 15 OF 35
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ISUPERSEDES
IDWG 'A-01908-6oo06-1 I
+------------------------------------------------------------------------------+
fA IISSUED
r------------------------------------------- /I hp I /
H E V ~ E T T - PAC K A R D C O.
I
/
1R48 5(lA
-----------------------------+
edI..
Th. object ot the pha.e d.tector (U472) is to liv. an appropriate
output it the talliq
of the co.pared input • isnal. do not
liDe up. The pha•• detector i. ea.pri ••d ot a dual flip-tlop with
the Q output. AImed and t.d back to 'the CLEAR input.. Thi. provide. both pha•• aDd frequency detection. Ficure 8 ahow. pha••
detector operation tor various .equenc•• of inpu't ••
Q157/158 and it. n.twork provid•• aD invertinl amplitier with the
loop filter. R2~5 i. a pull-up re.i.tor tor the aaplifi.r. The
PLL bandwidth is about )1Hz. Thi•••all bandwidth will not let
the loop respond quickly to input di.turbance. (particlular~
ai.sinc/delayed SMCB pul.e.) and provid•• a "jitt.r-tre." clock to
the R/W board for write data elock~. Acquisition peraaeter. are
not critical .inee the .ervo cod. i. continuou••
U37l is a dual veo with one halt us.d in the PLL and the other
halt (noraally di.abled to prevent eros.talk) u.ed tor th.
diagnostic sienal injector. Pin 2 i. the volta,. control input
and pin 3 the ranee control ( ••t to 2.5V. in this contiruration).
Pins 16 and 9 are the dili tal .upp17 and pin. 15 and 8 the analo,
supply. I have .eparated the.e and used a 5-Volt resulator
(Q141) tor the analol supply to provide for i.olation and cross.talk t.munity. C348 was cho.en to .et the proper frequency
ranle. Typical trequency output tor a 2. 5V control input i.
5.7MHz with a 2MHz/V respon•••
r
--+---------+-------+---------+--------------~---+------------.---------------
IA IISSTJED
Isr/CW
110-07-82 IHODEL 1908P/790SR
1ST! ,
01908-60006
1--+---------+-------+---------+------------------+----------------------------1
IB IC0480296 Idb/HL 109-28-83 I SERVO-IMS
1
,--+---------+-------+---------+-----------------------+-----------------------1
I I
I
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IBY CRAIG WALlER
IDATE 10-07-82
1
._-+---------+-------+---------+-----------------------+-----------------------,
.,toT I P.C.' I APPR 1 DATE
IAPPD
ISHEET' 16 OF 35
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1--+---------+-------+---------+-----------------------+-----------------------1
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ISUPERSEDES
IDWG 'A-01908-60006-7 I
+-------------------------------------------------------------------- ---------+
+------------------------------------------- I I hp
HEW LET T - PAC K A R D C O.
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ER48 DIH 50A
-----------------------------+
The veo output goes to • divide-by-16 counter (U361) to give
various frequency outputs. u432 driving the CLEAR input; on the
counter provides capability for breaking the loop during board
test. The PLL output frequencies for a nominal 324 KHz SlCH
input frequency are:
veo
1
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output
pBH
5.18rmz
648KHz
2. 59MHz
PCK
324KHz
P2H
8 whenever PCI lag. OCR (PLL too sl~)'5l) U472
pin 6 will go low. This pulls current through the Q151/158
feedback and raises the collector volta,.. thus raising 'the veo
control voltage and increas ing the frequency. Conversel,y. when
PC! leads SHCB (PLL too fast) u412 pin 9 goes high and pushes
current through the feedback- to lower the control v01tage and
frequency. At equilibrium (SHCH and PCl negative eclces lined up)
pins 6 and 9 will go active simultaneouslY causing the clear pulse
to "eras." themselves very quickly. With pins 6 and 9 both
inactive (as is normally the cas. when phaae locked) the diodes
CR246/247 isolate them from the amplifier network and the status
quo i . maintained. '
As Ihown in Figure
Detection of proper phale lockin, is implemented with U552 pins
12 and 13 Ilonitorina the length of th. "too slow" anel "too fast"
pulses out of u412. During proper phase lock U552 pin 13. will
have a low duty cycle and U492 pin 1 will be low.
I
--+---------+-------+---------+------------------+----------------------------1
Jsr/CW 110-01-82 IMODEL 1908p/1908R ISTK , 01908-60006
1
,--+---------+-------+---------+------------------+-------------,---------------1
IB Ic0480296 Idb/ML 109-28-83 I SERVO-IMS
1
,--+---------+-------+---------+-----------------------+-----------------------1
I I
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1BY
IDATE lO-07-82
1
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ILTI P.C.' 1 APPR 1 DATE
IAPPD
ISHEET' 17 OF 35
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REVISIONS
I SUPERSEDES
IDWG • A-(-7908-60oo6-7 I
+------------------------------------------------------------------------------+
JA JISSUED
\.------------------------------------------- I
I 048 D/B 50A
I hp I
B E WLET T - PAC K A R D C o.
I
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The frequency detection capability of the u472 phase detector is
not desirable after proper phase lock has been achieved-stray
crosstalk/noise or servo defects could knock the loop out ot
lock. Therefore, the circuit around u462 pin 6 was included to
disable the frequency detection capability while in phase
lock. Signal P2L causes pin 6 to 10 lov and it PLL is hich (no
phase lock) pin 6 will stay low. When pin 6 loes hilh the phase
detector is cleared. Durinl phase lock pin 6 loes high once
ever.r servo bit (see Figure 9).
IV-D
Servo Bit Pattern Detection
Normally, the servo .)'nC, A, and B pulse. are encountered ever.r
3usec. Special patterns are encoded on the .ervo code, however,
in the fo~of s~ecific patterns of missinl pul.... ~es. special
patterns define the inner/outer-cuardband regions (.ee F~ ~)
and a once··around index pul.e for rotational registration. Th.
index pulle (IDXL) i~ .ent to the R/W board tor sector tiainc and
is also checked by the controller for proper di.c .pin velocity.
For future reference, a servo bit c.ll is the 3usec window in
which a .ync, At and B pulse is normally found.. It the.e pul•••
are present the servo bit is defined to be a "1". It they are
lIlis.ing the bit is a ·'0". Actually, only the. sync pul •• i. used
for bit determination but a liven servo track will al~s omit
both the .ync pulse and the A or B pul.e within the "0" bit
cell. The special patterns are detined by the tollowinc .equences
of ••rvo bi.ts:
Index
Outer-cuardband
Inner-cuardband
••• 111111101011010111111111 •••
••• 011101110111011101110111 •••
••• 011110110111101101111011 •••
Eight bits are requir.d to deteC't each of thes. patterns so U452
serves a. a .erial shitt register for storing the eight
bi ts • 11551 i. a 256x4 PROM ~ich serv.. as the pattern detect
logic (the 8 address bits .~e the input. and the 4 output bits
respond to the patterns). US61 i. a clocked IIdeglitcher"/buffer
to prevent the shifting address lines on U551 tr(..·" causinl
glitches on. the signal lines.
--+---------+-------+---------+------------------+---------------------------'sr/OW 110-07-82 1MODEL 7908P/7908R ISTK , 07908-60006
1--+---------+-------+---------+------------------+---------------------------IB Ic0480296 Idb/ML 109-28-83 I SERVO-INS
1--+---------+-------+---------+-----------------------+-----------------------1
1 I
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IDATE 10-r"(-82
I
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",LTI P.c., I APPR I DATE
IAFPD
ISHEET t 18 OF 35
1
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I
REVISIONS
I SUPERSEDES
IDWG 'A-07908-60006-7 1
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------- / I hp
B E V LET T - PAC K A R D C O.
i
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ER48 D/H 50A
-----------------------------+
The circuitry around the 4-bit counter (U361 pins 8-11) serves two
tunctions--to decode the servo bits and to coo!pensate the phase
detector tor missinc .ync pulse.. Figure 9 abow. that. until a
.ync pulse is missing. the 0361 counter will not count past·
7. About 200 nsec. atter the tront edge of a mis8 ina S7DC pulse
the count ot 8 is reached and U571 pin 13 sends a pulse to satisfy
the phase detector. When the count ot 12 is reached this phase
detector pulse is terminated and the counter clock is t~isabled
until the next sync pulse clears the counter. The delayed
"substitute" S)'DC pulse will cause a minor disturbance to the
PLL. This has caused write clock disturbances and writ. data
errors in the past but the PLL bandwidth has s inc. been 10wered
.olve this proble••
U452 is a .erial 8-bit shift re,ister which clocks in 'the decoded
.ervo bit when the PCKH sianal ,oes high. When a sync pulse is
ai •• tnt (.ee Figur. 9) the 0361 count is 11 Mben U452 shitts in a
"0" bit. Vi th regular sync pul.e. the U361 count won 1~ exceed T
and • "1" bit will always be .bitted in.
I
There i. onlY one PROM addre.. (01011010) which will detect the
in1ex pulse--thus it become•• 3u.ec pulse output. OGB and 1GB.
on the other hand. are continuous patterns so all "rotated
repre.entation. ot their .ddr••••• must be detected. Valid OGB
patt.rn •• tor instance ••re 01110111. 11101110. 11011101. and
10111011. There are eiCht valid representations/rotations ot 1GB.
II
Two thin,s .hould be poir.ted out .t this tiae.
Th. til-st is that
the OGB pattern 1. not trulJ continuous completelY around the
di.c. There i. a strine ot 8 "1'." injected into the patt.rn
coincidina with where the data tracks have the index pulse. ~u.
the OGB .ipal will
inactive tor 40u.ec (13 servo bi.t tille.)
once each rotation. The other thine is that track -1 is
designated as an outer-cuardband track but the OGB detection will
be unreliable near the track center. The reason 1s the servo
track towards the inside ot track -1 will not have the mi.sing
pul.e. whi1. the .ervo track toward. the outside will. The .ervo
head will pick up "halt" ot the sync pulse and "0" detection aay
or may not occur. For the .ame reason 1GB detection at track 390
will be unreliable.
,0
t
1--+---------+-------+---------+------------------+---------------------------IA IISSUED Ilr/OW 110-07-82 IMODEL 790SP/7908R 1ST! , 07908-60006
.--+---------+-------+---------+------------------+---------------------------IB Ico480296 Idb/ML 109-28-83 I SERVO-IMS
1--+---------+-------+---------+-----------------------+----------------------I I
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IDATE 10-01-S2
1--+---------+-------+---------+-----------------------+----------------------ILTI P.c., I APPR I DATE IAPPD
ISHEET I 19 OF 35
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
ISUPERSEDES
Iowa , 4l-0190S-60006-1
+------------------------------------------------------------------------------+
+------------------------------------------- /
HEW LET T - PAC KA R D C O.
IV-E
Track
I ER48 DIH 50A
I hp /
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/ -----------------------------+
Follo~ing Loo~
Figure 10 Ihows the tracking loop block diagram tor use in
analysis and simulation. FrOID this .odel the follo~ing loop
parameters can be calculated:
Loopband~idth
240 Hz.
Gain aargin 15 DB
Phas margin 50 deg.
Gain at runout 16 DB (60 Hz.)
Stiffness, measured as actuator torce per unit otttrack. is 1.6
pounds per track ( 0 •5 Ib ./.001 in. off'track).
Unlike the seek operation, track tollo~ing il accomplished
entirely with hardware on the servo board. The PMDH signal ,0iOl
high ~ill enable track following.
Schematically, there are three filter blocks in the track
follo~ing loop.
The tirst is a single pole low pass (5.51 KHz.)
at the formation of the PESl signal. The Ilext i3 a two pole low
pass (10.7 KHz.) to create PES2. The compensating filter, or
tracking loop tilter (U292 pin 14). has the lead corner at 76 Hz.
tor loop Itability. It also hal two low pass poles at 1.34
1Hz. The reasoll tor each ot the low pass filters i. tor noise
suppression.
There are two reasons, and two .ethodl. tor inJectinl position
signal or track tollo~inl ott.et.. Any non-zero .ienal added to
the position lignal in the tracking loop will result in a
proportional track tollowin, ott.et. The .eek calibration routine
aealure. track syncopation (uneven spacing ot track centers)
acro.s the dilc. Track Iyncopation il a term uled to describe
alternately narrow and wide track center spacings--tor example.
when tracks 1 and 2 are cloler to,ether than 2 and 3. 3 and 4
closer together than 4 and 5, etc. The seek algorithm requires
even track spacings tor accurate velocity .easurementl. The OFS
signal is the ottset injected into the poSition signal to
compensate tor apparent track syncopation during .eekl. The
magnitude ot OFS is lovemed by the result ot the leek calibration
routine tor each are. ot the disc and can vary the apparent track
center by up to +/-2.5~.
--+---------+-------+---------+------------------+---------------------------IA IISSUED
Isr/CW
110-01-82 IHODEL 1908P/7908R ISTK' 01908-60006
1--+---------+-------+---------+------------------+---------------------------IB Ico480296 Idb/ML 109-28-83 1 SERVO-IMS
,--+---------+-------+---------+-----------------------+-----------------------1
,
,
1
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IDATE 10-07-82
1
1--+---------+-------+---------+-----------------------+-----------------------1
'tTl P.C.' I APPR I DATE
IAPPD
ISHEET' 20 OF 35
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~--+---------+-------+---------+-----------------------+-----------------------1
~SIONS
ISUPERSED&C
IDWG 'A-07908-60006-1 1
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+------------------------------------------------------------------------------+
+------------------------------------------- /
/ hp /
B E WLET T - PAC K A R D C O.
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/ ER48 D/H 50A
-----------------------------+
The other method for producing a track following offset is by
enabling the SKH bit and injecting an offset value through the DAC
(US31). In fact, the SKH and RVDH bits are always enabled during
track following to allow cOilpensation for "DC" force o".fsets (due
to gravity, flex circuit, etc.) on the actuator. The :Beek
calibration routine measures force offsets and these are
compensated for during both seeking and track following by sending
a current through the 4. ••C. Each incremental DAC value :results in
49mv. at DRV and about 0.8J track following offset. I·t should be
It should be noted that the OFS induced offset is injected before
the position comparators and does not affect the ofttrack
indicator. ~e offset injected through the DAC is after ~:he
position eomparator~ and adds to any other effects at the offtrack
indicators. Therefore, an offset value ot 15 at the DAC input
will result in an outright "not on track" fault during a write
operation (1 volt at PES2). Lesser values will reduce margins
proportionately.
Finally, the signal TrOB desensitizes the otf track comparators by
a factor of two. This is to provide more margin during reads (2
volts for not on track fault) where off tracks are not fatal
(won't destroy data).
IV-F
~
Seeking
As mentioned in section III-I, the seek trom one track to another
involves much interaction between the hardware and the seek
algorithm resident in the controller. The controller accepts
DIrB, OFH, ONH, and TKX lipall trom the servo board and makel
decilionl based on them. The lervo board then receives control
lignall SKII, RVDH, PMDH, and CVNL, al well al DAC ·values. The
secondary port i. set up at the beginning ot the .eek to adjust
the DAC cain and the syncopation otf.et.
The actuator i. moved by sending current· through a voice coil in
the IMI .echanism. The n070inal acceleration/current is about
420,000 tracks per sec.··2 per amp. The rise time for current in
the coil is about 1 Dsec. Each incremental DAC value results in
49 mV. at DRV, or about 12.3 .a. steady state current in the
coil. The maximum current possible is nominally 12V./8 Ohms, or
1.5A. (630,000 tracks per lec.··2).
J
1--+---------+-------+---------+------------------+------------·----------------1
JA IISSUED Isr/CW 110-07-82 IMODEL 7908P/7908R ISTK , 07908-60006
I
1--+---------+-------+---------+------------------+------------·----------------1
IB Ico480296 Idb/ML 109-28-83 I SERVO-IMS
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1--+---------+-------+---------+-----------------------+-------·----------------1
t I
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IBY
IDATE 10-07-82
1
1--+---------+-------+---------+-----------------------+-------·----------------1
ILTI P.C.' I APPR I DATE
IAPPD
ISHEET' 21 OF 35
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I
REVISIONS
ISUPERSEDES
IDWG 'A-07908-6oo06-7 I
+-------------------------------------------------------------_._---------------+
+------------------------------------------- I I hp
'-....,. HEW LET T - PAC K A R D C O.
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ER~8 D/H
50A
-----------------------------+
Figure 11 sho·fS what several signals and eomrnands might look like
for a 5-traek seek. The initial forward eurrent command begins
to move the heads, as seen in the position signal. Forward is
considered as the direction or increasing track numbers, or
towards the ins5de of the disc. After traveling one full track
the current is reversed and the heads begin to slow down. The
time between the track center crossings from track 1 to track 2
is measured by the controller and a decision is made as to the
magnitude of reverse current to apply next (track 2 to traek 3).
At two tracks out (track 3 in this case) no current is commanded
so that an accurate .easurement of velocity can be made. A stop
pulse of variable duration is then applied to bring the velocity
into the track following capture range (about ~OO tracks per
sec.). The "final curve" (between tracks a. and 5) is detected by
the DIFH circuit. It is simp~ a differentiated position signal
to indieate the slope or PES1. When the slope changes sign at the
target track then the track follow (PMOH) command is givt"l1 and the
hardware loop takes over.
I
I
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J
The DAC (U531) pulls between 0 and 2 ma. through pin 4, depending
on the 8 input bits. The resulting DACV voltage at U292 pin 1 is
made bipolar by the 1 mao current drawn through ~2~8. By inverting the most significant bit (US31 pin 5) at the DAC input the 8bit command takes on a 2'. complement toraat.
As mentioned earlier (sections III-L and IV-E) there is a servo
calibration, or adaptation, routine which i. executed at each
drive power-on or selt-test which measures DC forces, track
.pac ing, and motor constant. The aleori tbms for these are
discussed in other documents. The hardware i.ple.entation tor
adjusting tor track syncopation and motor con.tant i. made through
the .econdary port (US21). Data is entered into this port via the
DAC port by activating YFB control bit. The lower three bit.
control the OFS signal macnitude. A value ot 4 in the.e three
bits i. the nominal .ettin, and one increment in either direction
result. in about 87mV. off.et at PES2.
The upper two bits in this 8-bit port (U521) are unused buv the
middle three bits adjust the DAC gain in accordance with the motor
constant measurement. Again, a value of 4 i. the nominal
setting.
--+---------+-------+---------+------------------+---------------------------Isr/CW 110-07-82 IHODEL 7908P/7908R 1ST! , 07908-60006
1--+---------+-------+---------+------------------+---------------------------IB Ic0480296 Idb/ML 109-28-83 I SERVO-IHS
1--+---------+-------+---------+-----------------------+----------------------I I
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IBY
IDATE 10-07-82
1--+---------+-------+---------+-----------------------+----------------------'·'t'l p.e., I APPR I DATE
IAfrD
ISHEET' 22 OF 35
+---------+-----,--+---------~ .----------------------+----------------------~
REVISIONS
ISUPERSEDES
IDWG , A-07908-60006-7
+------------------------------------------------------------------------------+
rA IISSUED
+-------------------------------------------
I
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ER48 D/B SOA
•
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B E WLET T - PAC K A R D C o.
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I
I
An increment in either direction changes the DAC reference
I
•
•JI
I
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,,
J
I
1
current by O.041ma., a change of about 2J in DAC gain since
the nominal reference current is about 2ma. A value of 1 will
increase DAC gain, and motor current applied, by 6J- -a value
of 0 will r'!duce motor currents in a tlhot tl drive by about 8~.
IV-G
Linear Motor Current Amplifier
The linear motor current amp (signal DRV to LMB, LHA) has the
function of converting voltage commands at DRV into current in the
voice coil. The first op amp (U491 pin 8) takes the DRV input and
compare. it with the feedback voltage trow the current sense
resistor (Rl52). The result is that, steady state, each volt at
DRV cOlDlllands 0.25 A. in the coil.
current amp block itselt is a rather complex circuit with
.everal teedback pathl. The voltage gain inside the loop is quit.
high
care must be taken to avoid instabilities. The purpose ot
the feedback section Rl11 and c264 is to shunt higher frequenciel
and reduc~ their gain. The coil current cannot respond reasonably
(1 msec. rise time) to frequencies greater than 100 KHz. R193
teeds back the coil voltage which must be overcome by the teed
torward voltage/current cODUlland. C191 lerves to shunt higher
trequencies.
~e
.0
There is a problem involving Iwi telling tilDes of tbe To-66
tran.istor. (Ql83 and Ql90)--they tend to turn on a few usee.
taster than they turn otf. When a current command il reversed,
signal SO will slew at itl maximum rate and attempt to turn one
transistor oft and the other on, in that order. The transistor
switching time Ikews caus. both tranliltors to conduct for 1 or
2 usec.--thil result. in large momentary currents trom +12VP to
-12VP and also cause. crosstalk o~ the board. The .everity ot
this problem was reduced by making R193 smaller (reducing internal
voltage gain). This problem onlJ occurs when maximum currents are
commanded and achieved (Ql83 or Ql90 in saturation).
ot the board selt-test, th£·re is a coil v()ltage sensing
comparator (U492 pin 14) which gives feedback to the controller as
to whether the coil voltage exceeds IV. This helps isolate faults
to board vs. IMI mechanism when the heads won't move.
As part
--+---------+-------+---------+------------------+----------------------------1
Isr/CW 110-01-82 IMODE:L 7908P/7908R ISTK , 07908-60006
I
1--+---------+-------+---------+------------------+----------------------------1
IB Ico480296 Idb/ML 109-28-83 I SER'JO-IMS
I
1--+---------+-------+---------+-----------------------+-----------------------1
I 1
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I BY
'D.ATE 10-01-82
1
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR I DATE
IAFPD
ISHEET I 23 OF 35
I
.--+---------+-------+---------+-----------------------+-----------------------1
I
REVISIONS
ISUPERSEDES
IDWG 'A-01908-6oo06-1 1
+-------------------------------------------------------_._---------------------+
fA IISSUED
+------------------------------------------HEW LET T - PAC K A R D C
o.
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/ ER48 DIH 50A
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The automatic retract current is presently set at about 18Oma.
The retract command (SDLL) is enabled whenever there is no track
follow command (PMDH) or seek command (SKB). such as when MRSTL is
active on a power-on or power-off. When retract is enabled then
Q470 serves to disable the normal current amp driving path and
Q471 then commands the 18Oma. retract current. Coil voltage i8
..onitored via R160/R249 to maintain the proper retract cur-rent.
VR481 and VR462 serve to protect the transistors trom excessive
emitter-base voltages. Upon retract during power down Ql11 will
shut off current to the carriage locking solenoid and allow the
retracted carriage to lock in the park zone.
IV-II
Diagnostic Signal Injector
The diagnostic lignal injector circuitr,y synthesizes a substitute
for the tri-bit signal from the disc servo code. To enable thil
diagnostic circuitry. the command bit TEH is activated. T.his
enables the other half of the dual veo (0371) to run at a
frequency controlled by the DAC port value. A sawtooth wave i.1
generated b,y an integrator (C169) tollow~g a 25~ duty cyle TTL
waveform (U471). This sawtooth wave, nomina~ly 300 KHz. and
150mV. peak-peak, is then injected into the servo signal path
with analog switch U111. Sync pulse detection and phase locking
occur as normal but the asymmetry in the triangle wave will result
in a non-zero position lignal. The position lignal magnitude
should exceed 1V. and cause OHH to go low. In addition, proper
phase lock il checked (PLE-L signal) and the CVNL signal i.
manipulated to create track crossing. (TKX signal) to verity
proper servo board operation independent ot the IMI mechanism.
--+---------+-------+---------+------------------+---------------------------Isr/OW 110-07-82 IHODEL 7908P/7908R 1ST! , 07908-60006
1--+---------+-------+---------+------------------+------------------------.---IB Ico480296 Idb/ML 109-28-83 I SERVO-IMS
1--+---------+-------+---------+-----------------------+----------------------I I
I
1
IBY
IDATE 10-01-82
1--+---------+-------+---------+-----------------------+-------------------.---ILTI P.C.' 1 APPR 1 DATE
IAPPD
ISHEET, 24 OF 35
1--+---------+-------+---------+-----------------------+-------------------.---I
REVISIONS
I SUPERSEDES
IDWG , A-07908-6ooo6'-7
+-------------------------------------------------------------------------_._---+
IA IISSUED
1M!
MEC\4AN\5M
j
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j
ILl
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DATA
J
Pal (fij)J)
P2l ("/'11)
lftw)
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(.up)
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PAGE 1
DATE: 05/09/84
MRFDOIf7R
MATERIAL LIST FOR PC-BOARD COMPOSED OF MUT·TIPLE H-P PART NUMBERS
PART-NUHBER(S) :
07908-60006
07908-66006
07908-68006
DATE CODE :
E2338
REFERENCE DESIGNATOR
c104
e105
C108
C109
C110
Cl17
C123
C124
c142
c143
c144
c145
c147
C151
c161
c168
c169
C170
c17l
c191
C196
c204
C207
C208
C212
C222
C226
c231
c235
C239
c240
c263
c264
C274
c280
c283
c287
C293
C302
C303
c304
C305
C321
C32S
C329
C33l
C332
COMPONENT PART
0160-5332
0160-5436
0160-5298
0160-5332
0160-5332
0160-5332
0160-5354
0160-5298
0160-5298
0160-5298
0160-5313
0160-5354
0160-5298
0160-5354
0160-5298
0160-5332
0160-5312
0160-5320
0160-5315
0160-5313
0160-5364
0160-5326
0160-5332
0160-5332
0160-5298
0160-54)8
0160-5354
0160-5354
0160-5354
0160-5298
0160-5298
0160-5332
0160-5319
0160-5311
0160-5298
0160-5318
0160-5298
0160-5298
0160-5332
0160-5298
011)0-5332
0160-5311
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
DESCRIPl'ION
CAP.1UF 2~ 50V
CAP- FXD 120 PF
CAP .01UF 20%
CAP .1UF 2~ 50V
CAP.1UF 2~ 50V
CAP 1UF 2~ 50V
CAP 2200PF 5~
CAP .01UF 2~
CAP .01UF 2~
CAP .01UF 2~
CAP 1 OOOPF 5~
CAP 2200PF 5~
CAP .01UF 2~
CAP 2200PF 5~
CAP .01UF 20J
CAP .1UF 2~ 50V
CAP .OlUF 1~
CAP 6800PF5J100V
CAP .10UF l~
CAP 1000PF 5~
CAP-FIXED .27UF
CAP 27PF 5J 200V
CAP.1JF 2~ 50V
CAP .1UF 2~ 50V
CAP .01UF 2~
CAP -FXO lUF
CAP 2200PF 5J
CAP 2200PF 5~
CAP 22QOPF 5J
CAP .01ur 2~
CAP .01UF 2~
CAP.IUF 2~ 50V
CAP 5600PF5J100V
CAP 1000PF 2~
CAP .01UF 2~
CAP 240PF 5J200V
CAP •Cl1UF 2~
CAP .01UF 2~
CAP .1UF 2~ 50V
CAP .0lUF 20J
CAP .1UF 20% SOV
CAP 1000PF 2~
CAP .OlUF 20J
CAP .OlUF 2~
CAP .OlUF 20J
CAP .0lUF 2~
CAP .01UF 2~
MATERIAL LIST CONTINUES ON IrEXT PAGE . • .
MRFD047R
PAGE
DATE: 05/09/84
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE B-P PART NUMBERS
PART-NUMBER(S):
DATE
07908-60006
07908-66006
07908-68006
CODE :
E2338
REFERENCE
DESI~TOR
C331
C338
C342
C343
C341
C348
C353
C354
C355
C361
C378
c406
C414
C420
C421
C422
C423
C424
C425
c432
C433
c434
c435
c436
c440
c441
c451
c452
C461
c473
c482
C501
CS02
CS03
C504
C505
cS06
CS07
C511
CS12
cS16
C517
CS18
CS19
CS25
cS26
CS27
COMPONENT PART
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5329
0160-5298
0160-5298
0160-5310
0160-5298
0160-53n
0160-5307
0160-5298
0160-5332
0160-5298
0160-5298
0160-5298
0160-5307
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5354
0160-5332
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0180-0374
0160-5298
0160-5298
018\J-0374
0160-5298
0180-0374
0180-0374
0180-0374
DESCRIPl'ION
CAP
.01UF
2~
CAP .01UF 2~
CAP
CAP
CAP
CAP
CAP
CAP
.01UF 2~
.01UF 2~
.OlUF 2~
47PF 5~
.01UF 2~
.01UF 2~
CAP 220PF
5J
.01UF 2~
1000PF 2~
CAP 68PF 5~
CAP .01UF 2~
CAP .1UF 2~ 50V
CAP .01UF 2~
CAP .01UF 2~
CAP .OlUF 2~
CAP 68PF 5~
CAP .01UF 2~
CAP .01UF 2,lJ
CAP .OlUF 2~
CAP • "1UF 2~
CAP .OlUF 2~
CAP .01UF 20J
CAP .01UF 20J
CAP .OlUF 20J
CAP .01UF 20J
CAP .OlUF 20J
CAP .OlUF 20J
CAP
CAP
CAP 2200PF
5J
CAP .1UF 2~ 50V
CAP .OlUF 2~
CAP .OlUF 2~
CAP .01UF 2~
CAP .OlUF 2~
CAP .01UF 2~
CAP .OlUF 20J
CAP .OlUF 2~
CAP .OlUF 2~
CAP 10UF 1~
CAP .OlUF 2~
CAP .OlUF 2~
CAP lOUF l~
CAP .OlUF 2~
CAP 10UF 1~
CAP lOUF l~
CAP 10UF l~
'1ATERIAL LIST CONTDJUES ON JIEXT PAGE • • •
2
PAGE
DATE: 05/09/8~
KRFDOll7R
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART NUMBERS
PART-NUHBER(S):
07908-60006
07908-66006
07908-68006
DATE CODE :
E2338
REFEREHCE DESIGNATOR
C534
C545
C546
C547
C555
C562
C564
C565
C566
CR112
CR172
CR17~
CR2l16
CR247
CRl53
CR258
CR269
CR273
CR427
CR463
CR480
CR485
CR486
CR530
L201
L203
MP1
MP2
HP3
MF4
MP5
HP7
MF8
011
034
Ql35
Ql57
Ql.58
Ql.83
COMPONENT PART
0160-5332
0160-5298
0160-5298
0160-5298
0160-5320
0160-5332
0180-0100
0160-5298
0180-0291
DIO-1N~00~
DIO-1N~00l:
DIO-IN400~
1901-0040
1901-0518
1901-0040
1901-0040
DIODE-SWITCHING
DIODE-SCHOTTKY
DIODE-SWITCHING
DIODE-SWITCHING
DIODE-SWI'f1CHING
DIODE -SWITCHING
DIODE-SWITCHING
DIODE-SWITCHING
DIODE-SWITCHING
DIODE-SWITCHING
DIODE-SWITCHING
DIODE-SWITCHING
COIL 33UH 5~
COIL 33UH 5~
1901-00~0
1901-0040
1901-0040
1901-0040
1901-00~0
1901-0040
1901-0040
1901-00~0
~U ...
085
090
Q228
Q229
Q319
Q320
Q464
1853-0413
1854-0477
1854-0477
1853-0281
1853-0281
1854-0477
_ _ _ .~ - - -
CAP .1UF 2~ 50V
CAP .01UF 2~
CAP .01UF 2~
CAP .01UF 2~
CAP 6800PF5~100V
CAP.1UF 20J 50V
CAP ~. 7UF 101
CAP .01UF 201
CAP 1UF lOJ
1901-07~3
1901-07~3
1901-07~3
9100-1625
9100-1625
07908-80006
7120-6830
2360-0464
2420-0003
2190-0414
1480-0116
0403-0452
1854-0477
1853-0281
1853-0281
1854-0071
1854-0071
1854-0072
1053-0281
-L!~_~~
DESCRIPTION
1854-0~77
&I)-ETCHED
LABEL-INFO
MSI6-32X.37
IRJT 6 -32 . 250M
WSHR-LX EXT T
PIN GRV • 062X. 25
£XTR-PC BD
15TH
ISTR
XSTR
ISTR
X5TR
XSTR
XSTR
XSTR
ISTR
ISTR
ISTR
XSTR
XSTR
XSTR
MATERIAL LIST CotrrlIlUE5 ON NEXT PAGE • • .
12
2N2222~T018
PNP 2i2907A
PNP 2i2907A
NPH SI PL5
NPN 51 PL5
2N3054 T066
PNP 2N2907A
2N2222AT018
PNP 216049
2N2222AT018
2N2222AT018
PNP 2N2907A
PNP 21,2907A
2N2222AT018
3
PAGE II
DATE: 05/09/84
MftFD047R
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART JruMBERS
PART-NUMBER(S):
01908-60006
01908-66006
01908-68006
DATE CODE :
£2338
REFERENCE DESIGNATOR
Q471
RlO2
RlC3
Rl06
Rl07
Rl15
Rl16
Rl18
Rl19
Rl25
Rl26
R127
R128
Rl29
R136
R137
Rl38
Rl39
Rl40
Rl48
R149
Rl50
R152
R153
R154
Rl56
R159
R160
R1~~
~J.63
R173
R175
R176
Rl77
R192
R193
R194
R202
R205
R206
R209
R213
R214
R215
R216
R221
R223
COMPONENT PART
1854-0417
0698-3437
0698-3437
0151-0444
0698-3429
0751-0280
0151-0438
0151-0346
0151-0438
0698-3442
0151-0317
0698-3153
0698-3156
0698-3156
0698-3153
0698-3442
0151-0317
0151-0280
0698-0083
0751-0442
0151-~442
0151-0289
0811-3415
0151-0280
0751-0428
0698-0082
0698-3155
0698-3132
0151-0280
0151-0280
0751-0280
0151-0280
0751-1001
0151-0199
0151-1001
0698-3609
0764-0033
0698-3429
0151-0416
0151-0416
0698-0083
0151-0462
0698-3153
0698-3157
0698-3157
0698-3159
0151-0438
MATERIAL LIST CONTINUES
ON
DESCRIPTION
XSTR 2N2222AT018
RES 133 1J.125
RES 133 1J.125
RES 12.1K 1J.125
RES 19.6 1J.125
RES 1K 1J .125
RES 5.11K 1J.125
RES 10 lJ.125
RES 5.1lE 1J.125
RES 237 lJ.125
RES 1.33K 1J.125
RES 3.83K lJ.125
RES 14.7K 1J.125
RES 14.7K 1J.125
RES 3.83K 1J.125
RES 231 IJ.125
RES 1.33K IJ.125
RES 1K IJ.125
RES 1.96K lJ.125
RES 10K lJ.125
RES 10K lJ.125
RES 13.31t lJ.125
RES .4 lJ 3W PW
RES lit lJ.125
RES 1.621: lJ.125
RES 1164 lJ.125
RES 4.641t lJ.125
RES 261 1J.125
RES lK 1J.125
RES 1K 1J.125
RES 1K IJ.125
RES 1K IJ.125
RES 56.2 1" .5
RES 21.51t IJ.125
RES 56.2 lJ .5
RES 22 5J 2
RES 33 5J 2
RES 19.6 1".125
RES 511 lJ.125
RES 511 1".125
RES 1.96K 1J.125
RES 15K 1J.125
RES 3.83K 1".125
RES 19.6K 1".125
RES 19.6K 1J.125
RES 26.1K l.J.125
RES 5.11K l.J .125
REXT PAGE • . •
MRFD047R
DATE: 05/09/84
PAGE
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE B-P PART
PART-NUMBER(S) :
07908-60006
07908-66006
07908-68006
DATE CODE :
12338
REFERENCE DESIGNATOR
R227
R230
R236
R237
R238
R244
R245
R248
R249
R254
R255
R256
R257
R259
R262
R265
R266
R267
R268
R271
R272
R276
R277
R278
R279
R281
R282
R284
R285
R286
R288
R289
R294
R301
R308
R309
R312
R313
R314
H315
R316
R317
R325
R326
R327
R336
R349
COMPONENT PART
0757-0463
0757-0463
0757-0289
0757-0289
0757-0289
0757-0~40
0757-0280
0698-3279
0757-0401
0757-0280
0757-0280
0757-0280
0757-0280
0757-0280
0698-3162
0698-0082
0757-0440
0757-0420
0757-0280
0757-0280
0757-0280
0757-0280
0757-0438
0757-0424
0757-0279
0698-4479
0698-4479
0698-4462
0757-0447
0757-0280
0698-3161
0757-0443
0757-0463
0698-0083
0698-3157
0757-0417
0757-0200
0757-0438
0698-3150
0757-0416
0698-0083
0698-3438
0757-0438
0698-4435
0757-0280
0757-0438
0757-0280
MATERIAL LIST CONTINUES
lfUHBEftS
DESCRIPl'ION
RES 82.5K 1~.125
82.5K 1~.125
RES 13.31[ 1~.125
RES 13.31[ 1~.125
RES 13.3K 1~.125
RES 7.51 1~.125
RES 1£ 1~ .125
RES 4.99K 1~.125
RES 100 1~.125
RES 1£ 1~ .125
RES 1£ 1~.125
RES 1£ 1~.125
RES 1£ 1~.125
RES 1X 1~.125
RES 46.4K 1~.125
RES 464 1~ . 125
RES 7.5! 1~.125
RES 750 1~,,125
RES 1K 1~.125
RES 1K 1~.125
RES 1K 1l.125
RES 1X 1~ .125
RES 5.11K 1~.125
RES 1.1K 1~.125
RES 3.16K 1~.125
RES 11&K 1J .125w
RES 11&K 1J .1.25w
RES 768 1J .1.25W
RES 16. 2K 1~.125
RES 1K 1~.125
RES 38.)! 1~.125
RES 11K 1~.125
RES 82.5K 1~.125
RES 1.96K 1~.125
RES "9.6K 1~.125
RES 562 1~.125
RES 5.62K 1~.125
RES 5.11K 1~.125
RES 2.37K 1~.125
RES 511 1".125
RES 1.96K 1~.125
RES 147 1~.125
RES 5.11K 1~.125
RES 2.49K 1~
RES lK 1~ .125
RES 5.11K 1". :L25
RES lK 1~ .125
P~S
OM IiEXT PAGE • • •
5
PAGE 6
DATE: 05/09/84
MRFD047R
MATERIAL LIST FOR PC-BOARD CcttPOSED OF MULTIPLE B-P PART HUKBERS
PART-IfUMBER(S} : 07908-60006
07908-66006
07908-68006
DATE CODE :
82338
REFERENCE DESIGNATOR
R357
R358
R359
R360
R365
R366
R373
R374
R375
R376
R377
R379
R380
R401
R402
R403
R404
R405
R407
R408
R409
R410
R411
R412
R413
R415
R416
R417
R418
R419
R426
R428
R429
R430
R447
R449
R460
R466
R469
R472
R474
R475
R483
R484
R531
R532
R541
COMPONENT PART
0757-0280
0698-3279
069cl-3279
0698-3279
0757-0442
0757-0442
0698-3459
0751-0442
0751-0280
0751-0420
0751-0440
0757-0438
0757-0438
0757-0442
0757-0421
069&-3157
0757-0442
0757-0417
0698-3150
0698-3150
0757-0467
0698-3266
0698-3160
0757-0460
0757-0467
0757-0458
0757-0467
0757-0460
0757-0460
0698-3160
0757-0280
0757-0280
0757-0442
0757-0280
0757-0280
0757-0438
0757-0465
0757-0442
0698-0082
0698-3159
0698-3159
0757-0438
0698-3157
0757-0438
0757-0280
0757-0280
0757-0419
DESCRIPl'ION
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
Ri;'.....
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
lK lJ.125
4.99¥. lJ.125
4.99K lJ.125
4.99K lJ.125
10K lJ.125
10K lJ.125
3831 lJ.125
10K lJ.125
lK lJ.125
750 lJ.125
7.51{ 1J.125
5.111 1J.125
5.111 lJ.125
10K lJ.125
825 lJ.125
19.6K 1J.125
10K lJ.125
562 1J.125
2.371 lJ.125
2.371 1J.125
1211 1J.125
2371 1J.125
31.6K 1J.125
61.9K 1J.125
121K 1J.125
51.11 1J.125
121K 1J.125
61.91 lJ.125
61.91 1J.125
31.61 lJ.125
lK lJ.125
J.K 11.125
109 lJ.125
1K lJ .125
1K lJ .125
5.111 lJ.125
1001 lJ.125
26.11
26.11
5.11K
1~.125
1~.125
1~.125
1~.125
1~.125
19.61
1~.125
101
~4
5.11K 1~.125
1K 1J .125
1K 1J.125
681 1~.125
MATERIAL LIST CON'l'IMUES ON IIEXT PAGE •••
PAGE
DATE: OS/21/84
MRFD047R
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTI~LE B-P PART lfUHBERS
PART-NUMBER(S) :
01908-60006
01908-66006
01908-68006
DATE CODE:
£2338
REFERENCE DESIGNATOR
R542
R543
R544
R550
R556
R551
R558
R559
R560
R561
R561
TPl46
TPl89
U111
U112
U122
U231
U252
U292
U311
U351
U361
U371
U381
U422
U431
u432
U441
U451
u452
U462
u471
U472
U482
U491
U492
11511
11512
U521
11531
11532
U541
U542
U551
U552
U561
U562
COMPONENT PART
0698-3447
0698-3447
0157-0419
(\1598-3159
1)157-0442
0698-3150
0698-0085
0698-4037
0698-4031
0157-0424
0157-0191
0360-1682
0360-1682
1826-0502
1826-0159
1826-0328
1906-0248
1826-0323
1826-0323
1821-0001
1820-0411
1820-2096
1820-2369
1820-1374
1810-0083
1820-1417
1820-1199
1820-1197
1820-1197
1820-1433
1820-1112
1820-1112
1820-1212
1826-0138
1826-0323
1826-0138
1820-1641
1820-1730
1820-1730
1826-0188
1820-1730
1826-1033
1820-1416
1'101893
1820-1191
1820-1195
1820-1640
DESCRIPl'IOIf
RES 422 1•. 125
RES 422 1•. 125
RES 681 1~.125
RE~ 26.11 1~.125
RES 10K 11.125
RES 2.37K 11.125
RES 2.611 1~.125
RES 46.a. 1~.125
RES 46." 1J.125
RES 1.lK 11.125
RES 90.9 11 .50
TERM-PDf
TERM-PDf
IC llt066B
IC 1350
IC 4558
DIODE-ARRAY
IC op AMP
IC OP AMP
XSTk ARY 14p··DIP
IC SN7406lf
IC SllW39311
IC Sl71aLs62911
IC 751001
IETWORlt -RES DIP
IC S1114LS26lf
IC Slf1ltLS04H
IC SJf1lfLS 0011
IC SH1_LSOOH
IC Slf14LS164
IC m-.LS741
IC SH711LS '..
IC SH1~LS11211
IC LM339
IC OP AMP
IC LM339
IC SN14LS36511'
IC SN74LS2131'
IC SN74LS27311'
IC MC1408L-8
IC SJI74LS273H
LINEAR IC
IC 914LS141f
IC-PRCII
IC mJaLsool
IC SN7liLS175H
IC Slf74LS3661
MATERIAL LIsr CONTIMUES 01f NEXT PAGE • • •
7
MRFD047R
DATE: 05/09/811
PAGE 8
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART IItImERS
PART-NUHBER(S):
01908-60006
01908-66006
01908-68006
DATE CODE :
E2338
REFERENCE DESIGNATOR
U5n
11572
11581
VR1111
VR141
VR275
VR330
VR431
VR450
VR462
VR481
VR568
COMPONENT PART
1820-1144
1820-1640
1820-1199
1902-0184
1826-0276
1902-3082
1826-0555
1902-3002
1902-3082
1902-0041
1902-0041
1902-3140
END OF MATERIAL LIST.
DESCRIPl'ICIf
IC SJ74LS021
IC SM14LS3661
IC SJl74Lsol&l
DIODE 16.2V
IC MC78L05ACP
DIO-ZIR
64v 51
IC LM340LAZ-5
a..
DIO-Zitt~
2.37V 51
a..
DIO-ZIR
64v 51
DIODE ZlfR 5.nv
DIODE ZHR 5.nv
DIO-ZIR 8.25V 21
+------------------------------------------- I I hp
HEW LET T - PAC K A R D C
NOTE:
o.
/
e~
/
I
ER48 D/B: 50A, ,..
/ -----------------------------+
This pale provides a running history of changes for a multi-page
dra~ing ~hich cannot conveniently be re-issued completely after
each change. When making a change, list for each page all beforeand-after numbers (within reason; use judgement, and use
"extensive" revision Dote if loss of past history is tolerable, or
retype complete page) and associate ~ith each a symbol made up of
the change letter and a serial subscript to appear here and on
the page involved (there enclosed in a circle, triangle, or other
attention-I.tt~ outline).
(L206)
I
I
I
1M
LTRI
REVISIONS
I DATE I INIT IF
J ---1--------------------------------------------------1------·--1-------1-112-02-81 sb/ML M
I A r AS ISSUED
0§_-02- 2 sb CW M
I B REVISED PER PC~8-~6~
106-10- 2 sr CS M
I C REVISED PER PC48-4830
12-20- 2 clr CW M
I D REVISED PER PC~8-6025
09-28-« )3 db 'ML M
I E PLL PHASE ERROR CHANGE PER CO~029~
REVISED
TO
INCLUDE
NEW
FIELD
RETURN
TEST
C0480545
S4 de/ML 1M
01-10F
I
03-20-)4 de/,'}.., 11'I G REVISED 4.2 AND 4.3 PER co480717
I
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I
I
I
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1
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I
I
I
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--+---------+-------+---------+------------------+-------------._-------------Ic0480296 Idb/ML 109-28-83 IHODEL 7908
ISTK , 07908-60006/69006
E
I--+~--------+-------+---------+------------------+-------------._--------------
IF Ico480545 Ide/ML 101-10-84 I UPDATE/REVISION PROC
1--+---------+-------+---------+-----------------------+----------------------la Ico480717 Ide/ML 103-20-84 I
IDATE 12-01-81
1--+---------+-------+---------+-----------------------+---------.--------------;
ItTI P.C.' I APPR I DATE
JAPPD
ISHEET ,
1 OF 4
I
1--+---------+-------+---------+-----------------------+---------·--------------1
I
REVISIONS
ISUPERSEDES
IDWG 'A-CI7908-69006-1 I
+------------------------------------------------------------------------------+
+------------------------------------------HEW LET T - PAC K A R D C
o.
/
I
/ hp /
/
/
ER48 D/B: 50A. 50S
-----------------------------+
UPDATING AND REVISION PROCEDURE
07908-69006
This procedure contains instructions for modification of the
servo PCA. 07908-60006 to version 07908-69006.
REFERENCES:
SML:
07908-68006
07908-66006
Dwgs:
F-07908-60006-1
D-07908-60006-50
A-07908-60006-2
A-07908-60006-3
F-07908-60006-20
07908-80006
Untested PCA
Reel
Assembly DIq.
Schematics
'rest procedures
Debug procedures
Mod Dwg.
'rape II&sters
Production Changes:
48-4069
48-4093
48-4108
48-4155
48-4175
48-4208
48-4285
48-4400
48-4666
48-4830
48-6025
C048-0296
Change Cl71 to 0160-5375
Add wire to Rev A bd
Ch3nge U231 from 1906-0249 to-0248
Adds test pins
Crosstalk filter change
Solves extra track cross problem
Rev. C
PLL bandwidth change
Rev. D Servo Board.
Retract current and current amp changes
Rev E. Servo Board
PLL Phase Error Chance
--+---------+-------+---------+------------------+---------------------------ISTK , 07908-60006/69006
J--+---------+-------+---------+------------------+---------------------------IF Ic0480545 Ide/ML 101-10-84 I UPDATE/REVISION PROC
1--+---------+-------+---------+-----------------------+----------------------10 IC0480717 Ide/ML 103-20-84 IBY
IDATE 12-01-81
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
I SHEET ,
2 OF 4
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
1SUPERSEDES
IDWG , A-07908-69006-1
+--------------_._--------------------------------------------------------------+
IE lC0480296 Idb/ML 109-28-83 IHODEL 7908
+------------------------------------------HEW LET T - PAC K A R D C
r).
/
I
I
I
I
hp
/
ER48 D/B: 50A, 50B
-----------------------------+
INTRODUCTION:
This article will provide infonaa"~ion concerning the eligibilty
of the servo board for revision and also concerning the rev:lsioDs
themselves.
REVISABLE ASSEMBLIES:
The first assembly which may be revised is D-2207. All prior
a8semblie. are to be scrapped.
REVISIONS:
A-2108
48-4093
C-2108
48-4069,4108,4155
C-2125
48-4175
C-2129
48-4208
C-2144
48-4400
D-2207
48-4285.4666
D-2214.c-2214
48-4830
£-2240,£-2241
48-6025
£-2338
C04B-0296
CURRENT ASSEMBLY:
,I
I
I
I
I
t
£-2338
II
I
1--+---------+-------+---------+------------------+------------·----------------1
1£ Ic0480296 Idb/HL 109-28-83 IHODEL 7908
ISTK , 07 908-60006/69006
I
1--+---------+-------+---------+------------------+------------·----------------1
IF Ic0480545 Ide/HL 101-10-84 I UPDATE/REVISION PROC
I
1--+---------+-------+---------+-----------------------+-------·----------------1
IG Ic0480711 Ide/ML 103-20-84 IBY
IDATE 12'-01-81
I
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR I DATE
IAPPD
ISHEET ,
3 OF 4
I
1--+---------+-------+---------+-----------------------+-------··---------------1
I
REVISIONS
ISUPERSEDES
.. IDWG' A··01908-69006-1 1
+-------------------------------------------------------------_ .. _--------------+
+------------------------------------------- / I ER48 D/H: 50A 50B
I hp /
J B E W LET T - PAC K A R D C O.
/ / -----------------------------+
t
II
I
I
I PROCEDURE:
II
J
I 1.0 Inspect all boards for general mechanical and cosmetic detects
per A-5950-9205-1. Repair all component malfunctions.
I
I
I
I 2.0 Identity all boards with the following logo:
07908-69006
I
Current Date Code
I
to replace existing logo for date codes 2207 or later.
J
J
3.0 Aftix. near the logo. a 7120-5480 (made in USA) label which
has been stamped with the .onth and year of final inspection.
4.0
On
board revision:
D-2207
(to Cet to D-2214)
a) Replace R160 with 0698-3132 (261 )
b) Replace R193 with 0698-3609 (22 )
c) Replace R249 with 0757-0401 (100 )
4.1
On
board revision:
D-2214.E-2240 t E-2241 (to Cet to Dt E-2338)
a) Replace R159 with 0698-3155 (4.64K)
1
I
b) Replace CR247 with 1901-0518 (Schottky Diode)
1
1 4.2
On
board revision:
J
D-2338
£-2338
a) Current Assembly
4.3
On all Rev D boards manufactured at Loveland (88809L follows
board number in upper lett corner) he lure that insula',or
pads (0340-0140) have been installed under Ql83 and Q190.
This prevent I collector shorts to base or emitter pads.
4.4 Test per A-5955-3476-1
and A-07908-69006-2
I
.. J
r
3060 Test Procedure
I/O Field Return Test Procedure
--+---------+-------+---------+------------------+---------------------------109-28-83 IMODEL 7908
ISTK , 07908-60006/69006
1--+---------+-------+---------+------------------+---------------------------IF IC0480545 Ide/ML 101-10-84 1 UPDATE/REVISION PROC
,--+---------+---_._--+---------+-----------------------+----------------------10 Ic0480717 Ide/ML 103-20-84 IBY
IDATE 12-01-81
1--+---------+---_·_--+---------+-----------------------+----------------------tTl P.C.' I APPR 1 DATE
IAPPD
ISHEET ,
4 OF 4
(--+---------+---_._--+---------+-----------------------+----------------------I
REVISIONS
I SUPERSEDES
Iowa , A-01908-69006-1
+------------------------------------------------------------------------------+
IE IC0480296 Idb/ML
DlST ANa BETWEEN
REGISTRATION TARGETS 12.500! .003
~PLCS
.--•
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T.-s BOAN) txXs mT CONFORM TO
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US61
UNIVERSAl TEST FlX1\IES.
•
£::::::J:
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US51
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F~7908-80006-' 1
F-07908-80006-~
f
2
01908-80006-9
TARGET MASTER
PAD MASTER
GR"PHICSC()WONENl 510£
8-31-82
-, .. ,
+------------------------------------------- I I hp
HEW LET T - PAC K A R D C
NOTE:
o.
/
e~
/
I
ER48 D/B: 50A, ,..
/ -----------------------------+
This pale provides a running history of changes for a multi-page
dra~ing ~hich cannot conveniently be re-issued completely after
each change. When making a change, list for each page all beforeand-after numbers (within reason; use judgement, and use
"extensive" revision Dote if loss of past history is tolerable, or
retype complete page) and associate ~ith each a symbol made up of
the change letter and a serial subscript to appear here and on
the page involved (there enclosed in a circle, triangle, or other
attention-I.tt~ outline).
(L206)
I
I
I
1M
LTRI
REVISIONS
I DATE I INIT IF
J ---1--------------------------------------------------1------·--1-------1-112-02-81 sb/ML M
I A r AS ISSUED
0§_-02- 2 sb CW M
I B REVISED PER PC~8-~6~
106-10- 2 sr CS M
I C REVISED PER PC48-4830
12-20- 2 clr CW M
I D REVISED PER PC~8-6025
09-28-« )3 db 'ML M
I E PLL PHASE ERROR CHANGE PER CO~029~
REVISED
TO
INCLUDE
NEW
FIELD
RETURN
TEST
C0480545
S4 de/ML 1M
01-10F
I
03-20-)4 de/,'}.., 11'I G REVISED 4.2 AND 4.3 PER co480717
I
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ISTK , 07908-60006/69006
E
I--+~--------+-------+---------+------------------+-------------._--------------
IF Ico480545 Ide/ML 101-10-84 I UPDATE/REVISION PROC
1--+---------+-------+---------+-----------------------+----------------------la Ico480717 Ide/ML 103-20-84 I
IDATE 12-01-81
1--+---------+-------+---------+-----------------------+---------.--------------;
ItTI P.C.' I APPR I DATE
JAPPD
ISHEET ,
1 OF 4
I
1--+---------+-------+---------+-----------------------+---------·--------------1
I
REVISIONS
ISUPERSEDES
IDWG 'A-CI7908-69006-1 I
+------------------------------------------------------------------------------+
+------------------------------------------HEW LET T - PAC K A R D C
o.
/
I
/ hp /
/
/
ER48 D/B: 50A. 50S
-----------------------------+
UPDATING AND REVISION PROCEDURE
07908-69006
This procedure contains instructions for modification of the
servo PCA. 07908-60006 to version 07908-69006.
REFERENCES:
SML:
07908-68006
07908-66006
Dwgs:
F-07908-60006-1
D-07908-60006-50
A-07908-60006-2
A-07908-60006-3
F-07908-60006-20
07908-80006
Untested PCA
Reel
Assembly DIq.
Schematics
'rest procedures
Debug procedures
Mod Dwg.
'rape II&sters
Production Changes:
48-4069
48-4093
48-4108
48-4155
48-4175
48-4208
48-4285
48-4400
48-4666
48-4830
48-6025
C048-0296
Change Cl71 to 0160-5375
Add wire to Rev A bd
Ch3nge U231 from 1906-0249 to-0248
Adds test pins
Crosstalk filter change
Solves extra track cross problem
Rev. C
PLL bandwidth change
Rev. D Servo Board.
Retract current and current amp changes
Rev E. Servo Board
PLL Phase Error Chance
--+---------+-------+---------+------------------+---------------------------ISTK , 07908-60006/69006
J--+---------+-------+---------+------------------+---------------------------IF Ic0480545 Ide/ML 101-10-84 I UPDATE/REVISION PROC
1--+---------+-------+---------+-----------------------+----------------------10 IC0480717 Ide/ML 103-20-84 IBY
IDATE 12-01-81
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
I SHEET ,
2 OF 4
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
1SUPERSEDES
IDWG , A-07908-69006-1
+--------------_._--------------------------------------------------------------+
IE lC0480296 Idb/ML 109-28-83 IHODEL 7908
+------------------------------------------HEW LET T - PAC K A R D C
r).
/
I
I
I
I
hp
/
ER48 D/B: 50A, 50B
-----------------------------+
INTRODUCTION:
This article will provide infonaa"~ion concerning the eligibilty
of the servo board for revision and also concerning the rev:lsioDs
themselves.
REVISABLE ASSEMBLIES:
The first assembly which may be revised is D-2207. All prior
a8semblie. are to be scrapped.
REVISIONS:
A-2108
48-4093
C-2108
48-4069,4108,4155
C-2125
48-4175
C-2129
48-4208
C-2144
48-4400
D-2207
48-4285.4666
D-2214.c-2214
48-4830
£-2240,£-2241
48-6025
£-2338
C04B-0296
CURRENT ASSEMBLY:
,I
I
I
I
I
t
£-2338
II
I
1--+---------+-------+---------+------------------+------------·----------------1
1£ Ic0480296 Idb/HL 109-28-83 IHODEL 7908
ISTK , 07 908-60006/69006
I
1--+---------+-------+---------+------------------+------------·----------------1
IF Ic0480545 Ide/HL 101-10-84 I UPDATE/REVISION PROC
I
1--+---------+-------+---------+-----------------------+-------·----------------1
IG Ic0480711 Ide/ML 103-20-84 IBY
IDATE 12'-01-81
I
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR I DATE
IAPPD
ISHEET ,
3 OF 4
I
1--+---------+-------+---------+-----------------------+-------··---------------1
I
REVISIONS
ISUPERSEDES
.. IDWG' A··01908-69006-1 1
+-------------------------------------------------------------_ .. _--------------+
+------------------------------------------- / I ER48 D/H: 50A 50B
I hp /
J B E W LET T - PAC K A R D C O.
/ / -----------------------------+
t
II
I
I
I PROCEDURE:
II
J
I 1.0 Inspect all boards for general mechanical and cosmetic detects
per A-5950-9205-1. Repair all component malfunctions.
I
I
I
I 2.0 Identity all boards with the following logo:
07908-69006
I
Current Date Code
I
to replace existing logo for date codes 2207 or later.
J
J
3.0 Aftix. near the logo. a 7120-5480 (made in USA) label which
has been stamped with the .onth and year of final inspection.
4.0
On
board revision:
D-2207
(to Cet to D-2214)
a) Replace R160 with 0698-3132 (261 )
b) Replace R193 with 0698-3609 (22 )
c) Replace R249 with 0757-0401 (100 )
4.1
On
board revision:
D-2214.E-2240 t E-2241 (to Cet to Dt E-2338)
a) Replace R159 with 0698-3155 (4.64K)
I
I
b) Replace CR247 with 1901-0518 (Schottky Diode)
1
1 4.2
On
board revision:
J
D-2338
£-2338
a) Current Assembly
4.3
On all Rev D boards manufactured at Loveland (88809L follows
board number in upper lett corner) he lure that insula',or
pads (0340-0140) have been installed under Ql83 and Q190.
This prevent I collector shorts to base or emitter pads.
4.4 Test per A-5955-3476-1
and A-07908-69006-2
I
.. J
r
3060 Test Procedure
I/O Field Return Test Procedure
--+---------+-------+---------+------------------+---------------------------109-28-83 IMODEL 7908
ISTK , 07908-60006/69006
1--+---------+-------+---------+------------------+---------------------------IF IC0480545 Ide/ML 101-10-84 1 UPDATE/REVISION PROC
,--+---------+---_._--+---------+-----------------------+----------------------10 Ic0480717 Ide/ML 103-20-84 IBY
IDATE 12-01-81
1--+---------+---_·_--+---------+-----------------------+----------------------tTl P.C.' I APPR 1 DATE
IAPPD
ISHEET ,
4 OF 4
(--+---------+---_._--+---------+-----------------------+----------------------I
REVISIONS
I SUPERSEDES
Iowa , A-01908-69006-1
+------------------------------------------------------------------------------+
IE IC0480296 Idb/ML
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ISHEET' 11 OF 69
1--+---------+-------+---------+-----------------------+----------------------1
REVISIONS
ISUPERSEDES
IDWG' A-01908-60205-~
+-------_._---------------------------------------------------------------------+
IA IISSUED
1
+------------------------------------------- /
/ hp /
B E W LET T - PAC K A R D C
IV.
SECTOR TIMING LOGIC
o.
/
/
I
ER48
D/B: C2
-----------------------------+
(Continued)
Since 300 - 260 ~ ~O, this assures that sector 0
always begins preciselY ~O bytes after I~J)X-L is
asserted. Flipflop U691 and NARD gate U6~1 serve to
generate a one byte sync pulse, INDX-L, which is sent
to the microprocessor PeA at the beginning of sector 0
to indicate the actual beginning of physical sector O.
IDX-L is not used tor this purpose because IDX-L is
two bytes in duration. [Note that one "byte duration"
equals the time interval required to read eight bit.
of HRZ data from the disc].
Hote that' counters U6101, U6111, and U6112 have
synchronous load and clear inputs. Hote also that
flipflops U582 and U592 have asynchronous clear inputs
which override their asynchronous preset inputs.
I
1
1
1
1
1
1
--+---------+-------+---------+------------------+-----------------------------1
Ijmm/LACI01-20-82 IMODEL 1908
ISTK , 07908-60205
I
J--+---------+-------+---------+------------------+----------------------------1
1 I
I
/
I
I INTERNAL MAINTENANCE SPECIFICATION
I
1--+---------+-------+---------+-----------------------+-----------------------1
I I
I I
I
IBY
I DATE MAY 7, 1984
1
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C. I I APPR I DATE
IAPPD
ISHEET' 12 OF 69
1
J--+---------+-------+---------+-----------------------+-----------------------1
I
REVlSIONS
I SUPERSEDES
Iowa I A-01908-60205-~ I
+------------------------------------------------------------------------------+
IA IISSUED
+----- -.------ ---- ---------------- ------- ---- I
I ER48 D/H: C2
I hp I
B E W LET T - PAC K A R D C O.
I
I -----------------------------+
V.
FORHAT'l'ER
A ddtailed block diagram of the formatter is depicted
in Figure 7. There a ..·• three blocks: The transition
logic. the MFM Encoder, and the Sync Bit Generator.
The Sync Bit GeLerator determines when the Data Start
Bit is to be recorded on the disc. The Sync Bit
Generator is comprised of flipflops U522 and part of
US32 and NAND gate 11641. The circuit is shown in
Figure 8.
Prior to the Start of Sector, the signals are as Shc,WD
in Figure 8. When SOS-L is asserted, CLR-L is
immediately asserted and is sent to the MFM encoder.
This assures proper phasing of the veo sync field
which the Transition Logic will begin to record.
Since SOS-L is asserted for one byte-time, and since
RWC-H is the bit clock, SOS-L will be asserted for
8 cycles of RWC-H.
During the time between SOS-L ,oing low and DTP-L
going low, the Transition Logic is recording the VCO
sync field on the disc. Atter D'l'P-L is asserted, CI.R-L
is de-asserted. The next bit to be recorded will be
the Data Start Bit. When Start-L is asserted, the MYM
Encoder will cause a "1" transition to be recorded cn
the disc.
The MFM Encoder is shown in Figure 9. The actual
encoding is performed by NOR gates US62 and OR gates
u681. The output CODE-L carries the MYM transition
information in the falling edge of CODE-L.
J
I
I
1--+---------+-------+---------+------------------+----------·------------------1
IA IISSUED Ijmm/LACI07-20-82 IMODEL 7908
1ST! , 07908-60205
1
1--+---------+-------+---------+------------------+----------------------------1
I 1
1 / 1
I INTERNAL MAINTENANCE SPE~!FICATION
1
1--+---------+-------+---------+-----------------------+------------------------1
I I
I
/
I
IBY
IDATE HAY 7, 1984
I
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I AI-i"R 1 DATE
IAPPD
I SHEET , 13 OF 69
1
1--+---------+-------+---------+-----------------------+------·-----------------1
1
REVISIONS
ISUPERSEDES
IOWG' A-07908-60205-4 I
+------------------------------------------------------------------------------+
r------------------------------------------- I I hp / I
B E WLET T - PAC K A R D C o.
V.
FORMA'rl'ER
/
I
ER48 DIS: C2
-----------------------------+
(Continued)
In MFM codinc. a transition occurs at the bit cell
boundary between adjacent "0" bits or in the center of
the bit cell of a "1" bit. Transistions between
adjacent "0" cells are controlled by RWC-L being
asserted. Transitions in the center of ttl" cells are
controlled b,y RWC-H being asserted.
The Data St~rt Bit is generated by START-L being
asserted. Prior to START-L, the flipflops U542 are in
the cleared state. (See Figure 8). When START-L is
asserted, the first flipflop is preset to the "1"
state. This "1" is then clocked through the encoder.
Serial NRZ data line WDA-H follows this start bit with
data from the DNA PCA.
r
The Transition Logic is shown in Fiaure 10. Flipflop
U532 is a tOlgle flipflop which changes state with
each negative-goinl adg. ot CODE-L. 0532 is a
schottky part, because its very clos. aatching between
output rise and fall times is required for .inimizing
write jitter. A Low Power Schottky part has too much
mismatch to be used in this application.*
Level shifter U541 convert. the TTL levels output from
U532 to ECC compatible outlets aa required by the
write driver.
• Some Schottky parts sometimes have a temperature
problem that slows their switching speed. It this
happens to U532, the symptom will be a temperature
dependent incre~ae in hard errors. Changing U532
will cure this problem.
--+---------+-------+---------+------------------+---------------------------Ijmm/LACI01-20-82 IHODEL 1908
ISTK , 01908-60205
,--+---------+-------+--------.-+------------------+----------------------------1
I I
I / I
1 INTERNAL MAINTENANCE SPECIFICATION
I
,--+---------+-------+---------+-----------------------+-----------------------1
I
I
I I 1
IBY
1DATE MAY 1.1984
,
-+---------+-------+---------+-----------------------+-----------------------,
'-.,c;TI P.C.' I APPR I DATE
IAPPD
ISHEET, 14 OF 69
1
,--+---------+-----,--+---------+-----------------------+-----------------------1
I
REV1SIONS
1SUPERSEDES
IDWG' A-01908-60205-4 1
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------HEW LET T - PAC K A R D C O.
VI.
I
I ER48 D/H: C2
I hp I
I
I -----------------------------+
WRITE DRIVERS
The Write Driver circuitry is shown in Figure 11.
When the write gate. WRG-L. is de-asserted. the open
collector outputs of U3-21 are high impedances. In
this case, the voltage at the base of transistors Q157
is roughlJ zero volts. Q151 is therefore. in the
cutoft state since RCD-B rand RCD-L are alwa,1
voltages less then zero.
When WRG-L is asserted. both comparators U321 clanap
their outputs to roughly -12 volts. ~is draws
current through CR244 and acts to bias Q151. Q157
then. acts as a hieh gain ditterential amplifier to
input~
RCD-B and RCD-L.
,0
The outputs DX and DY
to the preamplitier ICs
located in the disc mechanism which record DI and DY
on the disc.
Two comparators U321 are used in this circuit to
assure that sutticient current sink capability exists
to bias Ql57.
J
--+---------+-------+---------+------------------+---------------------------IJ_/LACI07-20-82 IMODEL 7908
ISTK , 07908-61~205
,--+---------+-------+---------+------------------+-------------.--------------I I
1 I I
I INTERNAL MAIIlTENANCE SPECIFICATION
1--+---------+-------+---------+-----------------------+--------.--------------I I
I I
I
I BY
IDATE APR 12. 1984
1--+---------+-------+---------+-----------------------+--------.--------------ILTI P.C.' I APPR I DATE IAPPD
ISHEET' 15 OF 69
1--+---------+-------+-- ------+-----------------------+----------------------I
REVISIOIS
I SUPERSEDES
I DWG' A··07908 -60205-11
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------- I /hp / / ER48 D/H: C2
B E W LET T - PAC K A R D C O.
/
/ -----------------------------+
VII.
SIGlIAt PROCESSING BLOCK
The Signal Processing Circuitry is shown on page If of
the R/W schematic. A detailed block diagram of this
section is given in Figure 12. The differential input
signal DX-DY is applied to an AGe amplifier which
determines the output signal level. The lev~l
.:ontrolled output is passed througp a low pass filter
to remove out of band noise. This signal is
differentiated by a tuned amplifier to recover the
zero crossings information. The signal is limited to
convel·t it to TTL compatible levels at output RDA.
The analog signal at the output of the tuned amplifier
is passed through a full wave average detector and
applied to an integrator which .ets the AGe control
voltage such that the full wave average of SIGH-SIGL
is equal to a reference voltage.
The AGe amplifier circuit is shown in Figure 13. The
amplifier is a differential cascode amplifier who.e
gain is set bf current rationing in the cascode
transistors. fance Figure 13 looks a little
intimidating, let'. look at it a little at a time.
Capacitors C1S3 and c184 have very low impedance at
the signal frequencies of interest. For the moment,
let'. consider them to be zero ohms at the signal
frequencies. In this case, the bases of the cascode
transistors, 0181, are AC grounds. The small signal
differential .ode AC model of the amplifier 1 :·en looks
like Figure 14. In this figure, all cp~citances are
omitted since, at the frequencies of i.. .;erest, their
impedances &ore very low. Also, Rl54 is redrawn as a
series connection of two B1 ohm resistors.
--+---------+-------+---------+------------------+---------------------------Ijmm/LACI07-20-82 IMODEL 7908
ISTK , 079 08-60205
1--+---------+-------+---------+------------------+---------------------------..
I ;
I /
I
1 INTERNAL MAINTENANCE SPECIFICATION
1--+---------+-------+---------+-----------------------+----------------------··1
I I
I
/
I
IBY
IDATE APR 12, 1984
I
1--+---------+-------+---------+-----------------------+----------------------··1
ILTI P.C.' I APPR I DATE IAFPD
ISHEET' 16 OF 69
I
1--+---------+-------+---------+-----------------------+----------------------··1
I
REVISIONS
1SUPERSEDES
IDWG' A-01908-60205-4 1
+------------------------------------------------------------------------------+
IA IISSUED
+--------,----------------------------------I
, B E WLET
VII.,
i
-
PAC K A R D C O.
SIGNAL PROCESSING BLOCK
I
I
I
I~I
I
ER48
D/B: C2
-----------------------------+
(Continued)
When DX-DY is a differential signal. we can use thle
symmetry of the circuit in Figure 14 to analyze the
ar-lifier since we know that the small signal
co~lector current icl is equal to
ic1
= -ic2
Furthermore.
icl
= ic3
+ ic4
and
icl - dVi/81 Ohms
The output of the amplj.fier is
dVo = -(ic3)(237) Ohm
}'igure 15 shows the small signal model tor detennining
ic3 and ic4 given iel. The amount ot collector
current drawn by each ot trans istors Q3 and t!4 will be
detel"lllined by the ratio ot the base currents in eacb
transistor. This ratio is given by
ib3
c
(fel/B) hie4/(hie3 + hie4), NOTE: B
= Beta
ib4 ~ (iel/B) hie3/(hie3 + hie4)
so
ib3/ib4
= hie4/hie3
--+---------+-------+---------+------------------+---------------------------IISSUED
IJmm/LACI07-20-82 IHODEL 7908
ISTK , 07908-60205
,--+---------+-------+---------+------------------+---------------------------I 1
I /
I
I INTERNAL MAINTENANCE SPECIFICATION
,--+---------+-------+---------+-----------------------+----------------------I I
I /
I
1BY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+---.------------------ILTI P.C.' I APPR I DATE IAPPD
ISHEET , 17 OF 69
1--+---------+-------+---------+-----------------------+----------------------I
REVISIOHS
I SUPERSEDES
Iowa, A-07908-60205-4
.'----------------------------------------------------------------------------JA
+-------------------------------------------
SIGNAL PROCESSING BLOCK
I
hp
I
HEW LET T - PAC K A R D C O.
VII.
I
I
I
I
ER48 D/B: C2
-----------------------------+
(Continued)
The parameter hie of a bipolar transistor is determined
by "the bias conditions. If lib is the base bias current
then
hie = Vt/(B*Ib)
Vt = 26 • 10E-3 at room tp.mperature.
~.re
Therefore,
ib3/ib4
= [Vt
/(B*Ib4») * [(B*Ib3)/ Vt)
= Ib3/Ib4
or
so
ib3
= [(icl/B»)
ic3
= B*ib3
K
• [(Ib3/Ib3 + Ib4)]
[Ib3/(Ib3 + Ib4)] • riel]
The output of the AGe amplifier is then
dVo
= (ie3)
* (237)
= [Ib3/(Ib3
= [Ib3/(Ib3
The amplifier gain is
Avs
= (237/81)
ohn;·~
+ Ib4)] • (iel)
+
* (237) ohms
Ib4)] • [(dVi)/81ohms] *
(237o~~s)
dVo/dVi, which is
•
(I~)3)/(Ib3 +
Ib4)
--+---------+-------+---------+------------------+---------------------------Ijmm/LACI07-20-82 IMODEL 7908
ISTK , 07908-60205
1--+---------+-------+---------+------------------+---------------------------I I
1 / 1 - I INTERNAL MAINTENA.."CE SPECIFICATION
,--+---------+-------+-- ------+-----------------------+-----------------------1
I I
I I 1 - - IBY
JDATE APR 12, 1984
1
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR I DATE
IAPPD
ISHEET , 18 OF 69
I
; -+---------+-------+---------+-----------------------+----------------------·1
IA IISSUED
I
REVISIONS
ISUPERSEDES
IDWG' A-07908-60205-~ I
~------------------------------------------------------------------------------+
+------------------------------------------B E W LET
VII.
T -
PAC K A R D
C O.
SIGNAL PROCESSING BLOCK
I
I ER48 D/H: C2
I hp I
I
I -----------------------------+
(Cont inued)
low. t~e base currents. Ib3 and Ib4. of the cascode
transistors are DC bi~s conditions which depend upon
the va ~\.le of the AGe control voltage. As the AGe
control voltage in Figure 13 changes. the ratio of
Ib3 to Ib4 in each of the cascode transistor pairs
will change.
For instance. it the AGe control voltage is 6 volts,
then the base-emitter voltages of Q3 and Q\ are the
same and to the degree allowed by the match of' the
transistors. Ib3 = Ib4. In this case. the gain
becomes Av = [237/81] • (1/2) = 1.5
If the AGe control vol tag.s increases. th.-n the dc
base-e.itter voltage of Q4 becomes larger than that
of Q3. 'l'heretore. Ib4 > Ib3. III the limit wh,ere
Ib4 » Ib3. Av -> o.
If the AGe control voltage drops belo~ 6 volts,
Ib3 > Ib4. In the limit where Ib3 » Ib4. Av ->
o.
If the AGe control voltage drops below 6 volts .•
Ib3 > Ib3 > Ib4. In the limit where Ib3 » Ib4.
Av -> [237/81] c 2.9. Theretore. increasing the
AGe control voltage deCl"eases. the gain ot the
AGe amplifier. and decreasing the AGe control
voltage inCl"eaSeS the gain ot the AGe amplifier.
--+---------+-------+---------+------------------+------------.---------------IISSUED
Ijmm/LACI01-20-82 IHODEL 7908
ISTK , 07908-60205
,--+---------+-------+---------+------------------+-----------_ .. --------------I I
I I I
I INTERNAL MAINTENANCE SPECIFICATION
,--+---------+-------+---------+-----------------------+----------------------I I
I I I
IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+-----------------------,
ILTI P.C.' I APPR I DATE
IAPPD
ISHEET' 19 OF 69
I
,--+---------+-------+---------+-----------------------+------------------------1
I
REVISIONS
I SUPERSEDES
IDWG' A-01908-60205-4 I
+------------------------------------------------------------------------------+
IA
.&.--------------.-----------.-----------------B E WLET T - PAC K A R D C o.
VII.
SIGNAL PROCESSING BLOCK
I
I ER48 D/H: C2
I hp I
I
I -----------------------------+
(Colltinued)
C183 plays a very important role in the AGe amplifier
since, without it, the AC ground assumption made in
designing the amplifier is invalid. If c183 is bad,
the effect will probably be that the amplifier circuit
will oscillate at roughly 250 MHZ to 300 MHZ.
The low pass filter is shown in Figure 16. Also shown
is the small silllal model of Vle output stage ot the
AGe amplifie~. Also shown is the tuned amplifier
circuit.
low pass filter is a simple ladder network applied
to a differential input signal. It has a Beasel
response with a 5 MHZ cutoff trequency. .ct~ce that
the filtt:! response depends. upon the output i.npedance
of the AGe amplifi6r stage. If bypass capacitor C187
in th' AGe amplifier is bad, the filter response will
be upset.
~e
tuned amplifier stage has a gain at its resonant
frequency of appro).imately 50. The resonant ';"l'equeney
is roughly 7 MHZ. Tt,e respons. ot the tuned amplifier
is a 2nd order Bes'dl response with a differentiator
zero added.
~e
The overall frequency r.sponse, in terms of a
normalized input level, is ,iven in Figure 17. In
this figure, the magnitude Icale i. normalized. 80
only relative magnitudes are meaningful. The group
delay scale is absolute.
--+---------+-------+---------+------------------+------------- . _-----------Ijmm/LACI07-20-82 IMODEL 7908
1ST! , 01908-60205
1--+---------+-------+---------+------------------+----------------------------1
1 I
I / I
I IJrI'ERNAL MAINTENANCE SPECIFICATION
1
1--+---------+-------+---------+-----------------------+-----------------------1
IA IISSUED
I I
I
IBY
IDATE APR 12, 198'.:
I
1--+---------+-------+---------+-----------------------+-----------------------~
ILTI P.C.' i APPR I DATE IAPPD
ISHEET' 20 OF 6~
I
1 I
1--+---------+-------+---------+-----------------------+-----------------------1
1
REVISIONS
I SUPERSEDES
Inwa, A-01908-60205-4 I
~------------------------------------------------------------------------------+
+------------------------------------------- /
/ hp /
HEW LET T - PAC K A R D C O.
VII.
SIGNAL PROCESSING BLOCK
/
I
/ ER48 D/H:C2
-----------------------------+
(Continued)
The limiter circl1it is shown in Figure 18. DC
blocking capacitors C~76 and c477 remove de voltage
levels established by other circuits. U4102 is a vpry
fast comparator with TTL compatible outputs. Its main
claim to fame is that the output skew a symmetry is
guaranteed to be less than 2 nsec worst case. Since
we are trying to locate the zero crossings of SIGH and
SIGL as c1 sely as possible, we need a ver.y good zero
cross ing detectol·. The AM686 fits this need. It is
superior to designs using the 8T20. It is a ~~ast
improvement over the LM361.
R479 Ill.': R)~83 supply & dc bias path for the input
stage of Ul~102. R484 and R485 are chosen to arinimize
the slew rate ot the device.
The full wave average detector and the reference
voltage circuit are shown in Figure 19. Wb~n SIGH and
SIGL are zero volts ac, the dc voltages in the circuit
are as shown. The transistors are all part of U3101.
The Q designatora in Figure 19 are tor discussion
purposes only and do not correspond to Q designators
on the PCA.
Q3 and Q5 are current sources which draw appro1ximately
1 all each. The matching ot these bias currents
improves the temperature tracking pertormance of Q1,
Q2, and Q4.
Transililtor Q4 is the vo1ta,e reference c::'rcuit. ft.e
output VREF is a dw ~oltage at roughly -1.5 volts.
The voltage is determined by R353 and R349 and the
base emitter drop across Q4. This base emitter drop
aatches and tracks the base emitter drops across Q1
and ,2.
--+---------+-------+---------+-------.. ----------+---------------------------Ijmm/LACI07-20-82 IMODEL 1908
ISTK , 07908·-60~05
1--+---------+-------+---------+------------------+-----------.----------------1 I
1 I I
1 INTERNAL MAIJITENANCE SPECIFICATION
1--+---------+-------+---------+-----------------------+----------------------I I
1 /
1
IBY
fDATE APR 12,. 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' 1 APPR 1 DATE
IAPPD
ISHEET' 21 OF 69
1--+---------+-------+---------+-----------------------+-------.---------------I
REVlSIOHS
I SUPERSEDES
IDWG' A-07908-60205-~
+-------------------------------------------------------------_._---------------+
IA IISSUED
+------------------------------------------B E W LET T - PAC K A R D C O.
VII.
SIGNAL PROCESSING BLOCK
I
I ER48 D/H: C2
I hp I
I
I -----------------------------+
(Continued)
Ql and Q2 form a full wave rectifier, When SIGH >
SIGL, Ql turns on and Q2 turns off. The voltage at
the emitter of Ql is simply SIGH less one VISE drop.
When SIGH < SIGL, Q1 is off and Q2 turns on. The
emitter voltage is then SIGL. Thus, at the emitters
of Ql and Q2 is developed a full wave rectified
version of SIGH-SIGL. There is no "crossover
distortion" because current source Q3 guarantees that
either Ql or Q2 will be on at all times.
The full wave rectified signal is filtered by R266 and
c262 to detect the average value of this waveform. It
is this average value that the AGe loop attempts to
hold constant. Resistors R473 and ~474 set a dc
baseline for SIGH-SIGL which determines the peak to
peak amplitude of SIGH-SIGL when the AGe is working
properly.
The AGe loop integrator is shown in Figure 20. OpAmp
U2101 is a standard integrator circuit. It is
important that a low bandwidth opamp like the MC1458
be used because the signal V/AVG will contain small
levels ot high frequency ripple due to imperfect
filtering by the F.W.A. detector. It a wider
bandwidth op amp such as the Mc4558 is used, these
high frequency elem~nt5 will bleed through the device
and appear on the AGe control voltage. This will
cause distortion in the output ot the AGC amplifier
and will degrade the error rate.
Transistor Q199 and diode CR192 are voltage clamps
which restrict the AGe control voltage range. CR192
limits AGe control to +",. volts maximum. Q199 limits
AGC control to 5.5 volts minimum. This limiting is
necessary to ensure that the AGC amplifier remains
biased in the active region. Otherwise, during a
seek, the AGe amplifier could be slammed on and ott.
This would create system noise and probably isn't good
tor the components.
--+---------+-------+---------+------------------+----------------------------1
Ijmm/LACI07-20-82 IMODEL 7908
ISTK , 07908-60205
I
,--+---------+-------+---------+------------------+----------------------------1
I I
I
/
I
I INTE~AL MAINTENANCE SPECIFICATION
I
1--+---------+-------+---------+-----------------------+-----------------------1
I I
I /
I
IBY
IDATE HAY 7, 1984
1
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C., I APPH 1 DATE
IAPPD
ISHEET, 22 OF 69
I
,--+---------+-------+---------+-----------------------+-----------------------1
I
REVISIONS
ISUPERSEDES
IDWG' A-07908-60205-4 1
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------- /
/
/ hp /
B E WLET T - PAC K A R D C O.
VIII.
/
/
048,
D/B: C2
-----------------------------+
TIMING RECOVERY BLOCK
The Tilling Recovery and Separator circuits are shown on
page 3 of the schematics. A decailed block diacram of
the Timin, Recovery Block is liven in Figure 21.
During a ~rite, the Data/Clock Nux selects the servo bit
clock, pa-L. It also select. this cl"'ck dur~l1g seeks or
whenever an offtrack occurs. During a read operation,
the Data/eloek Mux select. the data lignal, RDA.
J
I
I
f
1
1
1
I
I
1
The Edge Detector generates a pulse whenever it receives
a Change in the level ot its input. This circuit is
necessary because all intontation in an MFM-encoded
sirnal is carried in the sienal transitions. '!'here tore ,
we need to focus on the transitions to recover timing
information.
The clock select logic determines which elockl will be
applied to the phase lock loop'. phase detector. '!'he
circuit has two operatin, modes, called Acquisition Mode
and MFM 1I0dp.
Acquisition Mode is used durin, writes, I.eks, and
during the first 10 byte. ot the VCO lynC field during
a read. The purpose of MFM mode is to process the VCO
clock sienal in Buch a way that the variationl in the
edees of the data sienal caused by MFM encoding do not
cause excesBive jitter in the output of the VCO.
The phase/frequency detector puts out a voltage pulse
Whose width is proportional to the magnitude ot the time
difference between the negative-going edge's of MFM-L alld
'l"'RF-L. The polarity of this voltage pulse is positive
it TRF-L leads MFH-L. The polarity is neg:ative if
TRF-L lags MFM-L.
--+---------+-------+---------+------------------+----------------------------
I A I ISSUED
I jJlUn/LAC I 07 - 20-82 I HODEL 7908
I STK , 07'908 -60205
1--+---------+-------+---------+------------------+------------------------~---I I
1 / 1
I IJl'I'ERNAL MAINTENANCE SPECIlf'ICATIOIf
1--+---------+-------+---------+-----------------------+----------------------I I
1 I I
IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+---,--------------------1
ILTI P.C.' 1 APPH I DATE
IAPPD
ISHEET' 23 OF 69
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1--+---------+-------+---------+-----------------------+------------------------1
1
REVISIONS
ISUPERSEDES
IDWG, A-07908-60205-4 I
+---------------------------------------------------------_._-------------------+
+------------------------------------------HEW LET ~ - PAC K A R D C O.
'VIII.
TIMING RECOVERY BLOCK
I
I ER48 DIB: C2
I hp I
I
I -----------------------------+
(Conti!1ued)
!he loop filter provide. compensation for the phase
locked loop. It. characteristics set such loop
parameters as acquisition time, Doise bandwidth, and
.usceptibility to pattern-induced jitt~r.
The VCO is a square wave oscillator who.e frequency of
oscillation depends upon the magnitUde of the control
voltage output from the loop filter.
!he R/W clock IOlic takes the basic timing information
contained in the VCO output and uses it to generate the
R/W bit clock.
Th. data/clock awe circuit!")' i. shown in Fiet ~ 22. The
select logic U552, U562, and C452 cause one of the two
flipflop~ US81 to be preset.
This will mask out the
sienal associated with that flop. The other flop will
be in the cleared .tate and its associated sienal passe.
through the awe. An example tiaing diagram i. included
in Figure 22.
This whole circuit i. an overly fancy atavi.m which
spranl from function. and capabilities we no longer
include in the read/write board. The flipflop. US81 no
lODger .erve a real purpose. Yes, Vircioia, it could be
.inplified. We Ju.t didn't catch it in time.
The EdCe Detector i •• hown in Figure 23. This circuit
i. designed to generate a negative-goin, ~ul •• each tiae
input D/C hal an edge. The width of the puIs. is Dot
important. The delay from positive edge to pul.e out
must equal the delay from negative ed&e to pulse out.
--+---------+--,-----+---------+------------------+---------------------------Ijam/LACI07-20-82 IHODEL 7908
ISTK , 07908-60205
1--+---------+-------+---------+------------------+---------------------------1 1
1 I I
I INTERNAL MAINTENANCE SPECIFICATION
1--+---------+-------+---------+-----------------------+----------------------I I
I I
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IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C., 1 APPR I DATE
IAFPD
ISHEET' 24 OF 69
1--+---------+-----,--+---------+-----------------------+-----------------------1
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ISUPERSEDES
Iowa, A-07908-60205-4 I
+------------------------------------------------------------------------------'.
A IISSUED
+------------------------------------------J
I HEW L E
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VIII.
T - PAC K A R D C O.
TIMING RECOVERY BLOCK
I
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bp
I
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FR48 D/B: C2
I ------
--------------------+
(Continued)
the rising edge of D/C, exclusive OR gate U561B
clocks a 1 into flipflop U551. This propagates a one
through U442, ~ich in turn causes the output of U422 to
fall. This taIling signal is ted back through u452 and
C429 to clea~ 0551.
On
The falling edge 01' D/C causes the same behavior through
the other flipflop. The exclusive-ORs 0561 and
flipflops 0551 are closel1 matched so that no bias due
to edge direction is introduced.
Inverters u452 and capacitor C429 serve to set the width
of the output pulse by creating a short delay in the
output feedback to U551. U422 is a 50-ohm line driver
required for driving the load presented to the edge
detector by the clock select logic.
A detailed block diagram of the Clock Select Logic is
given in Figure 24. The mode is controlled by the 2line-to-1-line DIUX, U511. When the mode clontrol input
is a "zero", the delayed signal MFHD and the output of
the VCO Pulse Swallower are passed througt
When the
mode control is a .. one", the delayed signal Mnm and the
output of the divide by 2 counter are passed through.
The VCO divide bf 2 counter sets the basic operating
frequency of the VCO during acquisition mode. It is a
simple tOlgle flipflop circuit.
--+---------+-------+---------+------------------+--------.. ------------------Ijmm/LACI07-20-82 IMODEL 7908
ISTK , 07908-60205
1--+---------+-------+---------+------------------+---------------------------1 I
I I I
1 IN'I'ERHAL MAINTENANCE SPECIF'ICATION
1--+---------+-------+---------+-----------------------+---.. ------------------I I
I I
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IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------tLTI P.C.' I APPR I DATE
IAPPD
ISHEET' 25 OF 69
1--+---------+-------+---------+-----------------------+----------------------1
REVISIONS
ISUP~EDES
IOWG, A-07908-6020S-4
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------- / I bp
HEW LET T - PAC K A R D C O.
VIII.
TIMING RECOVERY BLOCK
/
I
/
I
ER48 DIB: C2
-----------------------------+
(Continued)
The VCO Pulse Swallower Circuit suppresses the timing
reterence output TRF-L when no data edge is present in
HYMD. This is d~ne to lessen the sensitivity ot the
phase locked loop' s pbase detector cir,:ui t to the
modulation of MFMD caused by the data during a read.
(Refer to Figure 9, CODE-L. tor an example of bow the
edges of an MFM signal under,o pulse position
modulation). The output DARN-H ot the Pu1se Swallower
is a putse which a high to lOll transition tor eacb MFM
data edge. This pulse ;s s),Dchronized to the VCO clock.
VCO-H, and is used to develop a phase reference b.y the
R/W clock generator.
100 usec. delay lino, U521, ~a used to allow the
pulse swallower tiMe to set up. In order for the
timing recovery block to work properly, the amount of
time delay used must be roughly 1/2 of a bit cell time.
For the 7908, this is roughly 94 D•• C. The additional 6
nsec allow some additional time for th. Pulse Swallower
to set up. The 100 nsec delay can not be shortened or
lengthened by more than a':,out
6nsec.
~'he
veo
+/-
The VCO Pulse Swallower Circuit is shown in Figure 2~.
A negative-going edge on MFHD sets the first flipflop,
U412A. upon the next negative edge of VCO-H, VCOM is
clocked thru to DARK. On the next rising edge ot VCO-B,
both flipflops U412 are reset. A timin, diagram is
shown in Figure 25. The phase locked loop circuitr,y
establishes VCO-H such that the~edges of DARM and VCOM
line up with MFM-L as shown.
I
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1--+---------+-------+---------+------------------+----------------------------,
IA IISSUED
Ijmm/LACI01-20-82 IMODEL 7908
ISTK , 07908-60205
1--+---------+-------+---------+------------------+---------------------------1 I
I /
I
I INTERNAL MAINTENANCE SPECIFICATION
1--+---------+-------+---------+-----------------------+----------------------I I
I / I
IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
I SHEET , 26 OF 69
,--+---------+-------+---------+-----------------------+-----_. ---------------I
REVISIONS
I SUPERSEDES
IDWG' A-07908-60205-4
+------------------------------------------------------------------------------+
+------------------------------------------HEW LET T - PAC K A R D
VIII.
C O.
TIMING RECOVERY BLOCK
I
I ER48 :O/H: C2
I hp I
I
I -----------------------------+
(Continued)
If you should bro~se through the TTL data b~ok someti~e,
you will find that the minimum pulse width l~pplied to
the clear input of a 1~S112 is supposed to be 8 nsec.
If the puIs·: applied to the clear input is less than
this, the flipflop milht oscillate.
If you browse further, you will see that the typical
delay from clear to Q output of a 74s112 is 5 nsec.
Furthermore, the typical delay through a 74S00 gate is
3 nsec. 3 + 5 = 8, .0 typically things will be just
dandy with the Pulae Swallower circuit.
Bowever, it i. polaible for a Schottky flipf.lop to clear
in as little as 3 naec. Fttrther, it il possible for a
1400 to pass a signal in ~ little as 2 nsec. 2 + 3 is
less than 8, so you .ight expect trouble. Sould you
worry about it?
It turns out that if you examine the insides of a
148112, you will find that feeding Q back tel the clear
input through a NAND late i. okay. The circui't is built
in auch a fashion that the flipflop will stabilize.
Therefore. you c1'"'\n' t have to worry about 3 ... 2 c 8.
That would not be the cale tor a 74s112 circ:uit in which
NOT Q i. fed back to the CLEAR through an O~; gate. That
would be an unstable configuration and could, oscillate
even though the "logic" is apparently the sa.,,~e as our
Pulse Swallower.
--+-----,----+-------+---------+------------------+----------------------------1
Ijmm/LACI07-20-82 IMODEL 1908
ISTK , 0790,B-60205
I
1--+----_·_---+-------+---------+------------------+----------------------------1
I I
1 / I
1 INTERNAL MAINTENANCE SPECIFICATION
I
,--+-----.----+-------+---------+-----------------------+-----------------------1
IA IISSUED
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IDATE
IAPPD
ISHEET'
4~R
12, 1984
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I-~+---------+-------+---------+-----------------------+-----------------------1
ILTI
P.C.'
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APPR
I
DATE
27
OF
69
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,--+---------+-------+---------+-----------------------+-----------------------1
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REVISIORS
1SUPERSEDES
Iowa, A-07908-60205-4 I
+------------------------------------------------------------._-----------------+
----------------.-------------------------- I
/ ER48 D/H: C2
I hp /
B E WLET T - PAC K A R D C o.
/
I -----------------------------+
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VIII.
TIMING RECOVERY BLOCK
(Continued)
By the way, the Pulse Swallower circuit is also used
in the HP 13037 Formatter/Separator on the 13031-68028
board.
The Phase Detector circuit is shown in Figure 26. '!'he
phase detector triggers on the negative-going edges of
MFM-L and 'l'RF-L. The NOT Q outputs of flipflops U441
are applied to a difference amplifier to generate an
output puls. whose width is proportional to the timing
ditference between MFM-L and TRY-t. When MFH-L leads
TRF-L, a negative pulse is produced. This case is
illustrated in the waveform diagrams on Figure 26.
When TRF-t leads MFM-L, a positive pulse is produced.
Re.istors R425, R427, R426, an~ R424 set the gain of the
difference amplifier roughly Av = 0.1. This level of
attenuation is required to prevent the op amp U351 from
slew rate limiting. The 160 pf capacitors c438 and c442
are high frequency "snUbs" which act to slow d01m the
very fast pulses put out by the flipflops. This
snubbin, is necessary to prevent a non-linear behavior
in op amps known as "rectification". Rectification i.
the phenomena whereby the base-emitter capacitance of
the input differential amplifier conduct ver,v high
frequency pulse. to the emitter of the differential
amplifier. Since the input signal i. differential _ode,
the positive-going pul.e will cause one of the
tran.istor. to become cut off. [This is illustrated in
Fieure 27]. CUtttng otf these transistors cause the op
amp's output to become amplitude .odulated. A photo uf
this etfect is LIIO given in Figure 21.
--+---------+-------+-------~------------------+----------------------------I
~ISSUED
Ijmm/LACI07-20-82 IMODEL 7908
ISDK , 07908-60205
I
1--+---------+-------+---------+------------------+----------------------------,
I I
I / I
I III'l'ERNAL MAINTENANCE SPECIFICATION
I
,--+---------+-------+---------+-----------------------+-----------------------1
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IDATE APR 12, 1984
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IAPPD
ISlIEET' 28 OF 69
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REVISIOKS
I SUPERSEDES
IDWG, A-07908-60205-4 I
+------------------------------------------------------------------------------+
I
+------------------------------------------- /
/ hp I
B E WLET T - PAC r A R D C O.
VI I I.
TIMING RECOVERY BLOCK
/
I
/ ER48 D/H: C2
-----------------------------+
(Cont inued)
This amplitude modulation not only screws up the
phase locked loop's trequency response, but also
couples into the power supply and messes up the other
circuits. It's a bad deal, and the capacitors
prevent it.
Capacitor C318 is a compensation capacitor needed to
stabilize the op ~np 80 that it doesn"t oscillate.
The phase detector lain from the input phase
difference to phase error sienal, Oe, is Ed = 0.05
volts/radian. The loop filter is shown in Ficure 28.
It is a standard active filter. The only things
particularly noteworthy are the 5.6 pt capacitor
c145, which stabilizes u261. and the compensa"tion
circuit composed of R321 and C420 which act as a snub
for high frequency components wh~-h do appear at the
output of the phase comparator.
The VCO circuit is a 74LS629 VCo chip. This chip has
a very high lain, Xv • 21.10E6 rad/volt-sec. To
desensitize the VCO to noise inputs, resistors R311.
R236 and R325 and capacitor c433 are placed at the
control input to scale dow.n the efrective sensitivity
and filter out input noi... This network reduces the
effective Xv to 1.1.10E6 rad/volt-sec. The 14LS629
can drive 12 schottky loadl.
--+---------+-------+---------+------------------+----------------------------1
Ijmm/LACI07-20-82 IMODEL 7908
ISTK , 07908-60205
I
1--+---------+-------+---------+------------------+----------------------------1
1 1
1 / 1
1 INTERNAL MAINTENANCE SPECIFICATION
I
1--+---------+-------+---------+-----------------------+-------·----------------1
I 1
I / 1
IBY
IDATE APR 12, 1984
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1--+---------+-------+---------+-----------------------+-------·----------------1
ILTI P.C., 1 APPR 1 DATE
IAPPD
ISHEET' 29 OF 69
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,--+---------+-------+---------+-----------------------+-----------------------1
IA IISSUED
I
REVISIONS
I SUPERSEDES
IOWG'
A-07908-60205-4 I
+---------~--------------------------------------------------------------------+
+------------------------------------------R E WLET T - PAC K A R D C o.
VIII.
TIMING RECOVERY BLOCK
I
I ER48 D/B: C2
I hp I
I
I -----------------------------+
(Continued)
The phase comparator, loop filter. and VCO fora a
phase locked loop. The loop is 2nd order with a
cutoff frequency of 296 -10E3 rad/sec and a damping
coefficient of 2.16.
R/W clock logic is shown in Figure 29. This
block is supposed to take the VCO output 8 ienal and
use it to generate the read/write clocks. RWC-H and
RWC-L. A timing diagram ot this circuit's operation
is shown in Figure 30.
~e
Durir:-g a read. DARM-R will initial~ clock on the MFM
transitions caused by the all-zeroes pattern in the
VCO synchronize field. Theretore~ at the time when
,DECOD-H is asserted the DARH-H ilulse i. auarantead to
,represent a "zero" bit to the saparator.
As shown in Figure 30. when DECOD-H is asserted
:flipflops U432 begin to clock flipflop U482 such that
the rising edge of RWC-B i . coincident with the
rising edge of DEOO-H. This £'lax'antees that the RWC
is properly phased in order tor the separator to
decode the HFM data properly.
I
I--+---------+-------+---------+-----------~------+---------------------------Ijmm/LJCI01-20-82 IHODEL 1908
I~~ , 07908-60205
fA IISSUED
1--+---------+-------+---------+------------------+---------------------------1 I
I I
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I INTERNAL MAINTENANCE SPECIFICATION
1--+---------+-------+---------+-----------------------+----------------------I I
1 I I
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IDATE APR 12, 1984
--+----- ----+-------+---------+-----------------------+----------------------....,TI P.C.' I APPR 1 DATE IAPPD
ISHEET' 30 OF 69
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
I SUPERSEDES
IDWG' A-01908-60205-~
+------------------------------------------------------------------------------+
+--------,----------------------------------- I
B E WLET T - PAC K A R D C O.
IX.
I ER48 D/1~: C2
I hp I
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DATA SEPARATOR
To understand how to decode HFM data into NRZ elata,
refer to Figure 31. Figure 31 e~hibits the
l'elationship between NRZ data, HFM encoded data, and
the derived edge pulse DEDG-H which is derived in the
Timin, Recovery Block.
As. can be seen from ."igure 31, transitions of DEDG-H
which are due to "zero" data bits occur only at the
bOlmdaries between bit cells. Transitions of DEDG-H
which are due to "one" data bits occur only in the
center of the bit cells.
The VCO clock has one positive-going transition at
each cell boundary. These transitions are given even
numbers (0,2,4,6 •••• ) in Figure 31. The veo clock
also has one positive-going transition in the center
ot each bit cell. These tra.Ylsitions are given c)dd
numbers (1,3,5,7, •••• ) in Fi,,'!'e 31.
MFM decoding is very simple. If a positive-going edge
of DEDG-H is coincident with an "odd" numbered veo
pulse, that edge was caused by a "one" data bit"
Otherwise, the bit associated with that bit cell is a
zero.
The R/W clock logi~ is constructed 80 that the falling
edge ot DTQ2 ia caused :>nly by even-numbered vee.
pulse.. The rising edge ot DTQ2 occurs only during
odd-numbered veo pulses. Hence, DTQ2 makes the ideal
clock for the separator.
--+---------+-------+---------+------------------+------------_._-------------IISSUED
Ijll1lD/LACI01-20-82 IMODEL 190B
ISTK , 0190B-60205
1--+---------+-------+---------+------------------+-----------------------------1
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1--+---------+-------+---------+-----------------------+------------------------1
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IDWG' A-0790B-60205-4 I
.------------------------------------------------------------------------------+
IA
+------------------------------------------- /
B E WLET T - P A e I A R D C O.
IX.
DATA SEPARATOR
I ER48 D/B: C2
I hp /
/
/ -----------------------------+
(Continued)
The separator is shown in Figure 32. If DEDG-B is
high ~rior to an even-numbered veo pulse, that Ileans
that DEDG-B went high during an odd-numbered VCO
pulse. Therefore, on the next falling edge of' DTQ2,
DEDG-B will cause a "1" to clock into U492.
Therefore, the "1" bits are properly decoded.
If DEDG-B is high prior to an odd-numbered veo pulse,
'that means that DEDG-H Ilust have gone high during an
even-numbered veo pulse. In this case, as can be seen
in Figure 31, the next falling edge of DTQ2 will close
a zero into U492.
Therefore, the Q output uf U492A will be the desired
NRZ data. Separation complete I
Well, then, what does the rest of that Junk do? For
starters, the separator needs to detect the Data Start
Bit before it signals the DHA PCA that valid data is
coming. That'. what U492B does. Until the tirst
'''1'' bit is detected, U492B has Q -= 0 tor its output.
(That was caused when SOS-L went low). While in this
st:lte, it holds shift register U5101 to an all-allzeroes state and disallows SOD-L, the start of' data
signal to the DMA, from beine asserted.
After the first "1" bit ia detected, u492B assert.
SOD-L and allows the output data to pasa through shift
register 05101.
What does U5101 do?
Peter Galen, the DMA
clocked to it before
U5101 just pads some
real data.
Well, for reasons best known to
PCA wants to see 3-zero bits
it will be ready to receive dat~.
garbage zeroes in front of the
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t--+---------+--··----+---------+------------------+---------------------------IA IISSUED Ijmm/tACI07-20-82 IMODEL 7908
ISTK , 07908-60205
1--+---------+-_··_---+---------+------------------+----------------------------1
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!DATE APR 12, 1984
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IAPPD
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Inwc, A-07908-60205-4 I
+------------------------------------------------------------------------------+
+------------------------------------------- /
B E WLET T - PAC K A R D C O.
X.
/
ER4B
D/H: C2
I hp /
/
/ -----------------------------+
DISC MECHANISM INTERFACE
The last major block is the Disc Mechanism Interface.
This section is shown on page 5 of ~he schematics.
The D.M.I. is really just a collection of different
independent circuits. A "block diagram" is sbololll in
Figure 33.
The Write Fault Comparator, U161, normally outputs +5
Yolts, when PSAF-H, from the disc meche'.'l.isM, cUps
below 5.3 Yolts, that indicates that a write c)JW~ation
was bad and destroyed data on the disc. If PSAF··H
dips below 5.3 volts, U161asserts DWF-L.
!be -4 volt supply is U341. It i. just a high current
dc amplifier. It'. a straight-torward circuit except
for one thine. C136 must be 0.01uf or BO. If it's
made too larce (like 0.1 uf), Q233 will oscillate.
The +6 volts supply is Q627.
The Write Select Circuit 1s TJ~21 and Q101. When
reading, WSE-L is zero voItEl, then wri tj.ng WSE-L is
+3.5 volts.
The Head Select Circuitry is U421, U541 , U~52, and
U512. U421 and U5~1 are level translators. U552 and
U512 form an interlock which prevents CSO-L and CSI-L
trom being simultaneously asserted.
--+---------+-------+---------+------------------+---------------------------Ijmm/LACI07-20-82 IMODEL 7908
ISTK , 079°8 .. 60205
1--+----------+-------+---------+------------------+---------------------------I I
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1 INTERNAL MAINTENANCE SPECIFICA.TION
1--+---------+-------+---------+-----------------------+----------------------I I
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IDATE AFR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
ISHEET' 33 OF 69
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
1SUPERSEDES
IDWG' 1-07908-60205-4
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------- I I hp
HEW LET T - PAC K A R D C
X.
o.
DISC MECHANISM INTERFACE
I
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ER48
D/H: C2
-----------------------------+
(Continued)
The last circuit is the Write Current Circuit. This
circuit is shown in Figure 34. Q221 and Q222, which
are part of the write current circuit, are omitted
from this drawing. Their role will be explained
shortly.
U341 and Q226 form a constant current source that
Chaws roughly 45 mAo Q225 is a current switch. When
doing a write, open-collector comparators U321 have
high impedance outputs. Resistor R113 then turns Q225
off. and all of Q226's current is drawn trom the
preamplifier chips located in the disc mechanism.
This current is drawn through CR304.
When Master Reset is asserted or when WRG-L is deasserted (ie. when we are reading), one ot comparators
U321 clamps its output voltage to -12 volts. This
saturates Q225. and all of the current required by
Q226 is supplied thru Q225. No current is drawn
through CR304.
If transistor Q225 is bad, this will lometimes appear
as a drive fault when trying to write to the dilc.
What happens is that instead of a nice square wave
pulse at J2-25 ot about -3 voltl. yeu will see a very
short voltage pulle at WRHA which appear. to have an
oscillation riding in it. (S~~e Figure 35). If this
happens, Q225 is probably bad.
U421 , Q222, and Q221 are current-level switches. When
WC1-GH is asserted, U421 turns on Q222 which dumps
roughly 8 sA of current into R223 and R224. U341 then
acts to reduce the current drawn by Q226 by this
amount. WC2-H causes limilar action by Q221. By
controlling WC1 and WC2, the microprocessor can change
vrite current levels at different points on the disc.
,
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1--+---------+-------+---------+------------------+---------------------------IA IISSUED
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PAGE 1
DATE: 04/12/84
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART NUMBERS
PART-NUHBER(S) :
07908-60009
07908-68009
DATE CODE :
D-2302
REFERENCE DESIGNATOR
C110
C210
C215
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COi-iPONENT PART
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5332
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
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0160-5298
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0160-5298
0160-5298
0160-5298
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0160-5298
0160-5298
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0160-5298
0160-5298
0160-5298
0160-5298
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0160-5298
0160-5298
DESCRIPl'ION
CAP .01UF 2~
CAP .01UF 2~
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CAP .01UF 2~
CAP .0lUF 2~
CAP .OlUF 2~
CAP .01UF 2~
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CAP .01UF 2~
CAP .01UF 20%
~AP .01UF 20%
CAP .01UF 20%
CAP .01UF 2~
CAP .01UF 20%
CAP .01UF 2~
CAP .01 UF 20%
CAP .01UF 2~
CAP .01UF 2~
CAP .01UF 20%
CAP .01UF 20%
CAP .OlUF 20%
CAP .OlUF 20%
CAP .01UF 20%
CAP .01UF 20%
CAP .01UF 2~
CAP .01 UF 20%
CAP .01UF 20%
CAP .01UF 2a,;
CAP .OlUF 2~
CAP .OlUF 20%
CAP .OlUF 20%
CAP .01UF 20%
CAP .01UF 2~
CAP .01UF 2~
CAP .01UF 20%
CAP .01UF2Q%
CAP .01UF :20%
MATERIAL LIST CONTINUES ON NEXT PAGE . . •
PAGE
DATE: 04/12/84
MRFD047R
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART NUMBERS
PART-NUMBER(S):
07908-60009
07908-68009
DATE CODE:
0-2302
REFE~:NCE
DESIGNATOR
caS5
C860
C865
C870
C875
C880
C925
C930
C935
C940
C960
C970
C980
C985
L955
HPl
HP10
HP2
HP3
HP4
HP5
HP6
HP7
HP8
HP9
R265
S150
Ul101
U1111
U1121
U131
u141
U151
u161
U171
u181
U191
U211
U2111
U2121
U2131
U221
U231
u241
U251
U261
U3101
COMPONENT PART
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0180-1146
0160-5298
0160-5298
0160-5298
0180-2208
9100-1188
07908-80009
07908-00011
7120-6830
0403-0454
1480-0116
2190-0586
1530-1098
0361-0079
1251-3283
0380-0643
0698-3136
3101-2264
1820-2058
1820-2058
1813-0224
1820-1281
1810-0256
1820-1885
1820-1885
1820-1416
1820-2058
1820-2058
1820-1438
1AA6-6104
1816-1527
1820-1191
1820-1430
1820-1278
1820-1568
1820-2075
1820-2641
1820-1195
MATERIAL LIST CONTINUES ON
NEXT
DESCRIPl'ION
CAP .01UF 2~
CAP .01UF 2~
CAP .01UF 20J
CAP .01UF 2~
CAP .OlUF 2~
CAP .OlUF 2~
CAP .01UF 2~
CAP .01UF 2~
CAP .01UF 2~
CAP 15UF l~
CAP .OlUF 2~
CAP .01UF 2~
CAP .01UF 2~
CAP 220UF 1~
CHOKE-WIDE BAND
ETCHED BO-DMA
GROUNDING BKT.
LABEL-INFO
EXTR-PC BD 14
PIN GRV .062X.25
WSHR - LK HLCL
CLEVIS
RIVET .123DX.312
CONN 24-PIN F
STANDOFF-METRIC
RES 11.8K 1~.125
SWITCH-ROCKER
IC HC3448AL
IC MC3448AL
CLOCK CSC 12MHZ
IC SN74LS139N
NETWORK-RES DIP
IC ,)M74LS173N
IC DM14LS173N
IC SN74LS14N
IC MC3448AL
IC MC3448AL
IC SN74LS257AN
PHI
IC MEMORY
IC SN74s175N
IC-SN74LS161N
IC SN74LS191N
IC SN74LS125N
IC SN14LS245N
IC SN74LS314N
IC SN74LS175N
PAGE • . •
2
MRFD047R
PAGE
DATE: 04/12/84
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART NUMBERS
PART-NUMBER(S):
07908-60009
07908-68009
DATE CODE :
D-2302
REFEFENCE DESIGNATOR
U311
U3111
U3121
U3131
U321
U331
U341
U351
U361
U371
U381
U391
U4101
U411
U4111
UI!121
U4131
U421
U~_ 1_
U4 11
'
U4,1
U461
U471
U481
U491
U5101
U511
U5111
U5121
U5131
U521
U531
~'541
U551
U561
U571
U581
0591
U6101
U611
U6111
U6121
U6131
U621
u631
u641
u651
COMPONENT PART
1820-1438
1820-1195
1820··1322
1820-0681
1820-1195
1820-1438
1820-1438
1820-1h38
1820-1275
1820-1278
1820-1208
1820-1438
1816-1526
1820-1438
1820-1191
1820-1191
1820-1158
1820-1430
1820-1438
1820-1438
1820-1885
1820-1195
1820-1428
1820-0629
1820-1633
1820-1076
1820-1278
1820-1367
1820-1319
1820-0688
1820-1278
1820-1278
1820-1218
1820-2024
1820-1730
1820-0693
1820-0693
1820-0629
1820-1322
1820-1218
1e20-1212
1820-0686
1820-1322
1820-1218
1820-1121
1820-1216
1820-1216
IC SN74LS2~.7AN
IC SN74LS115N
IC SN74S02Y
IC SN74s00N
IC SN74LS175N
IC SN74LS257AN
IC SN74LS251AN
IC SN74LS251AN
IC SN74S260N
IC SN74LS191N
IC SN74LS32N
IC SN74LS257AN
IC MEMORY
IC SN7)·!T S251AN
IC SN: J.S115N
IC SN (4S115N
IC SN74s51N
IC-SN74LS161N
IC SN74LS25'7AN
IC SN74LS25'7AN
IC DM74LS113N
IC SN74LS115N
SN74LS158N
IC SN74S112N
IC SN14s240N
IC SN74S114N
IC SN74LS191N
IC SN74s08N
IC SN14s151N
IC SN14S20N
IC SN"l4LS191N
IC SN7hr,s191N
IC SN74LS191N
IC SN74LS244N
IC SN74LS213N
IC SN74S14N
IC SN74s"(4~r
IC SN74s112N
IC SN74s02N
IC SN74LS191N
IC SN74LS112N
IC SN74S11N
IC SN7)4S02N
IC SN74LS191N
IC 8093N
IC SN74LS138N
IC SN74LS138N
MATERIAL LIST CONTINUES ON IEXT PAGE . • .
3
DATE: 04/12/84
MRFD047R
PAGE
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART NUMBERS
PART-NUMBER(S):
07908-60009
07908-68009
DATE CODE ::
0-2302
DESCRIPl'ION
REFERENCE DESIGNATOR
u661
u611
u681
u691
U7101
U7111
U7121
U7131
U721
U131
U741
U751
U761
U771
U781
U191
U8101
U811
U8111
U8121
08131
U821
U831
u841
(J851
u861
U871
U881
U891
U93.01
U9J02
U911
U9111
U9112
U912
U9121
U9122
U9131
U941
U951
U971
U972
U981
U982
U991
U992
1820-1112
1820-1367
1820-0681
1620-1112
1820-0693
1820-1197
1820-0693
1820-0694
1820-1438
1820-1438
1820-1208
1820-1367
1820-1208
1820-1203
1820-1202
1820-0683
1820-1367
1820-1438
1820-0683
1820-1430
1820-1130
1816-0124
1816-0724
1820-1917
1820-1911
1820-2075
1820-1677
1810-0256
1820-0685
1820-1156
1820-0629
1818-1716
1820-1433
1820-0629
1818-1718
1820-1077
1820-1433
1820-1922
1820-1641
1820-2024
1820-1885
1820-1885
1820-1300
1820-1300
1820-1633
1820-0693
END OF MATERIAL LISTo
IC SN74LS74N
IC SN74sOSN
IC SN74s00N
IC SN74LS14N
IC SN74s14N
IC SN74LSOON
IC SN74S74N
IC SN14s86N
IC SN74LS251AN
Ie SN74LS257AN
IC SN74LS32N
IC SN74s08N
IC SN74LS32N
IC SN74LS11N
IC SN74LS10N
IC SN74S04N
IC SN74s08N
IC SJ-174LS251AN
IC S~14so4N
IC-SN74LS161N
Ie SN74LS273N
Ie-MEMORY
Ie-MEMORY
IC SN74LS240N
IC SN14LS240N
Ie SN74LS245N
IC SN74s374N
NETWORK - RES DIP
IC SN74S10N
IC SN'(l,S51N
Ie SN°,.I!S112N
RAM2KX8
Ie SN74LS164
Ie SN74s112N
RAM 2K X 8
IC SN74S157N
Ie SN74LS164
Ie SN74LS166N
Ie SN74LS365N
Ie SN74LS244N
Ie DH74LS113N
Ie DH74LS113N
IC SN74LS195AN
Ie SN74LS195AN
Ie SN74s240N
Ie SN14s14N
4
DISTRNCE BETWEEN
REGISTRRTION TRRGETS 317.50
ZONE :3
ZONE 4
+/-
.08
ZONE 5
NOTES.
UNLESS OTHERWISE SPECIFIED
1. THIS BORRD CONFORMS TO CORPORRTE
AUTOMATIC INSERTION STRNORRDS AS
PER RXIRL LERD MRNUAL DATED 4- 14-8" •
~ ARTWORK DRTE
7-1-83
•
~ ~HARK ASSEMBLY DRTE CODE 0-2302
liJ BORRD ERROR CORRECTION H1LES.
C111
~--
U211
BBB
.-,.-..
- -BOARD RSSEt18LY
"2 n
DETAIL A-A
~-
..
..,,-
DMA.
__ 11'7911'8
'-;-'3 _ _ _.SEE WHERE USED
_
_
... 21 1
J~08-60009
0-07908-600"9-1
+------------------------------------------8 E WLET T - PAC I A R D C O.
I
I
I
hp
I
I
I
ER48 D/H: C2, 50A
-----------------------------+
REVISIONS
The first assembly which may be revised is A-2138.
assemblies are to be scrapped.
A-2138
(PCO 48-4538)
All prior
Cbanged extracto~. on PeA
so they have ide~'.tification
number indicati.l1:; where the
PeA is to be placed in the
card cage.
--+---------+-------+---------+------------------+---------------------------I sb/ML 112-02-81 IMODEL 7908
ISTK , 01908-69009
1--+---------+-------+---------+------------------+---------------------------Is 148-6179 I jr/JSKI02-01-83 I UPDATE AND REVISION PROCEDURE
1--+---------+-------+---------+-----------------------+----------------------1 I
I
I
I
IBY
IDATE APR 12t 1984
J--+---------+-------+---------+-----------------------+----------------------ItTI P.C.' I APPR I DATE
IAPPD
I SHEET ,
3 OF 4
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
ISUPERSEDES
IOWG , A-0I7908-69009-1
.------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------- /
I
HEW LET T - PAC K A R D C O.
I
hp /
/
I
ER48 DID: C2, 50A
-----------------------------+
PROCEDURE:
1.0
Inspect all boards ~or general mechanical and
defects. Repair all visible detects.
2.0
Identity all boards with the following logo:
cosmeti~
07908-69009
2138
3.0 Affix, near the logo, a 7120-5480 lauel whl.ch indicates
the month and year of final inspection.
--+---------+-------+---------,------------------+---------------------------I sb/ML 112-02-S1 IMODEL 7908
ISTK , 07908-69009
,--+---------+-------+---------+------------------+---------------------------IB 148-6179 I jr/JSKI02-01-S3 I UPDATE AND REVISION PROCEDURE
1--+---------+-------+---------+-----------------------+----------------------I ,
I I
I
IBY
IDATE APR 12, 1984
1--+---------+-------+-----_·_--+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
1SHEET ,
4 OF 4
1--+---------+-------+---------+-----------------------+----------------------IA IISSUED
1
~~VISIONS
1SUPERSEDES
IDWG , A-0790S-69009-1
~------------------------------------------------------------------------------+
+------------------------------------------- /
I
/ hp
HEW LET T - PAC K A R D C O.
NOTE:
I
/
/
ER48
D/l!f: C2, 50A
-----------------------------+
This page provides a running history of changes for a multi-~age
drawing which cannot conveniently be re-issued completely &ofter
each change. When making a change, list fOl· each page all beforeand-after numbers (within reason; use judgement, and use
"extensive" revision note if loss of past history is tolerable, or
retype complete page) and associate with each a symbol made up of
the change l~tter and a serial subscript to appear here .nd on
the page invulved (there enclosed in a circle, triangle, or other
?~ttention-getting outline).
(L208)
I
I
1M
REVISIONS
I DATE 1 INIT IF
---1--------------------------------------------------1--------1-------1--
LTRI
A 1 AS ISSUED
B I UPDATED PER PC ~8-E;179
-1!2-02-81I sb/ML 1M
.-
jr/JSK M
02-01-83
I
I
I
I
I
,
I
o.
I
-
,
,I
..
,I
I
L
j
1--+---------+-------+---------+------------------+---------------------------IA IISSUED
I sb/ML 112-02-81 IMODEL 1908
ISTK I 07908-69009
1--+---------+-------+---------+------------------+---------------------------IB 148-6179 1 jr/JSKI02-01-83 I UPDATE AND REVISION PROCEDURE
1--+---------+-------+---------+-----------------------+----------------------I 1
I /
I
IBY
,CATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
I SHEET ,
1 OF 4
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
'SUPERSEDES
IDwa I A-07908-690Q9-1
f------------------------------------------------------------------------------+
+------------------------------------------HEW LET T - PAC K A R D C
o.
I
I ER48 D/H: C2, 50A
I hp /
I
I -----------------------------+
UPDATING AND REVISION PROCEDURE
07908-69009
This procedure contains instructions for modification of the Disc
Memory Access (DMA) peA, 07908-60009 to version 07908-69009.
RELATED DOCUMENTS AND PROCEDURES
07908-68009
F-07908-60009-1
F-07908-60009-20
F-07908-60009-21
D-07908-60009-50
A-07908-90047-1
Material List
Assembly Drawing
Modification Drawing
Modification Drawing
Schematics
I/O Line Processing Procedure
--+---------+-------+---------+------------------+---------------------------I sb/ML 112-02-81 IMODEL 7908
ISTK , 07908-69009
1--+---------+-------+---------+------------------+---------------------------IB 148-6179 I jr/JSKI02-01··83 1 UPDATE AND REVISION PROCEDURE
1--+---------+-------+---------+-----------------------+----------------------I I
I
/
I
IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI P.c., I APPR I DATE
IAPPD
ISHEET ,
2 OF 4
1--+---------+-------+---------+-----------------------+-.------------------I
REVISIONS
I SUPERSEDES
IDWG .' A-07908-690Q9-1
+------------------------------------------------------------------------------+
IA IISSUED
I)
+
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1-. ~ D- 07908·
WOO9.50
P IN 07908-60002
MICROPROCESSOR PCA-AS
Series Code 0-2139
+---------------------------------------.--- /
/ hp /
HEW LET T - PAC K A R D C O.
NOTE:
/
/
/ ER48 D/H: C2,50A
-----------------------------+
This page provides a running history of changes for a aUlti-page
drawing which cannot conveniently be re-issued completely after
each change. When making a change, list for each page all beforeand-after numbers (within reason; use judgement, and use
"extensive" revision note if loss of past history is tolerable, or
retl~ complete page) and associat~ with each a symbol made up of
the change letter and a seri~l subscript to appear here and on
the page involved (there enclosed in a circle, triangle, or other
attention-getting outline).
(L142)
I
1M
LTRI
REVISIONS
I DATE I INIT IF
---1--------------------------------------------------1-----·---1-------1-AS ISSUED
A
104-22-811 sblRT 1M
B
CORRECTED PER DeO _~-6199
102-09-83 db/JSijM
I
I
1
tI
I
I
I
I
,I
-
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,
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I
I
-
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-
----+-----------+------......;--t--
--+---------+-------+---------+------------------+---------------------------'sb/RT 104-22-81 IMODEL 7908
ISTK , 07908-60002
1--+---------+-------+---------+------------------+------------_.--------------I B148-6199 ,db/JSXI02-09-83' I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+----------------------I'
I I
I
IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAFPD
ISHEET ,
1 OF 34
,--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
I SUPERSEDES
IDWG , A-07908-60002-4
,t------------------------------------------------------------------------------+
IA 'ISSUED
+------------------------------------------HEW LET T - PAC K A R D C O.
I
I
I
I
hp
I
I
ER48 D/H: C2,50A
-----------------------------+
folICROPROCESSOR IN'l'ERNAL MAINTENANCE SPECIFICATION
FOR THE
MICROPROCESSOR BOARD OPERATION
07908-60002
~-....-1
I
I
I
I
I
,
I
I
1
I
I
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1
1
1
,
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I--+---------+-------+---------~------------------+---------------------------'ISSUED
I sb/RT 104-22-81 IMODEL '7:)08
ISTK , 07908-60002
IA
1--+---------+-------+---------+------------------+---------------------------I B148-6199 I db/JSKI02-09-83 I I.H.S. MICROPROCESSOR BOARD
1--+---------+----_·_-+---------+-----------------------+----------------------1 I
I I 1
IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------·,TI P.C.' I APPR I DATE
IAPPD
1SHEET ,
2 OF 34
'-......r-+-- ------ -+-- -- .. --+-- --- ---. -+-- ---- ---- ------ --- ----+--- ---- ---- ---- ---- ---I
REVISIO~S
I SUPERSEDES
IDWG , A-07908-60002-4
+-----------------------------------------------------------------------------+
+------------------------------------------- /
I
,
I
I
I
t
I
I
/ hp /
HEW LET T - PAC K A ROC O.
,
/
TABLE OF CONTENTS
I Section
I
I
~
/
/ ER48 D/H: C2,50A
-----------------------------+
SCOPE
2
RELATED DOCUMENTS
4
3
BLOCK DIAGRAM • • •
Overview..
• ••
Brief Description of Each Block. •
CPU ••
•
Clock Circuit
Control Logic.
• ••
•
Address Decode & Bus Control Logic
Memory •••
4
4
3·1
3·2
3·2.1
3·2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
4
4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
4.7
4.8
4.9
4.10
4.11
C'l'C
• • • . • • •
4
1
•• • •
Linus Counter.
Drive Sense Register •
Self-Test Switches & Display •
LOGICAL OPERATION
•
•
MPU Address & Data Bus Structure •
SOB Interface
Clock Circuit
Control Logic.
Control auffer
Control Latch
Latched Write Flip-Flop
Rom Chip Enable Circuit.
Address Decoding LOlie •
Rom & Patch Eprom Decodin, •
Ram, Register & Board Select
Decoding •
I/O Decoding .
Bus Control Logic
Memory •
C'l'C..
•••
Linus Counter
Drive Sense Register
Self-Test Switches' Led Display .
)
5
5
5
5
5
6
6
6
6
7
7
8
9
9
9
10
10
11
11
12
13
14
15
15
16
16
17
18
--+---------+-------+---------+------------------+---------------------------I sb/RT 104-22-81 IHODEL 1908
ISTK , 07908-60002
,--+---------+-------+---------+------------------+---------------------------'B148-6199 ,db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+----------------------, I
'I I
IBY
IDATE APR 12. 1984
,--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
I SHEET ,
3 OF 34
,--+---------+-------+---------+-----------------------+------------------------1
I
REVISIONS
I SUPERSEDES
IDwa 'A-0790a-6oo02-4 I
+------------------------------------------------------------------------------+
IA IISSUED
+--------------------------.----------------- /
~f
HEW LET T - PAC K A R D C O.
1
/
/
/~I
/
ER48
D/H: C2,50A
-----------------------------+
SCOPE
This IMS details operation of the Micro}ll'ocessor Board
(07908-60002) of the Low Cost Controller.
2
RELATED DOCUMENTS
l.
2.
MOSTEK Microcomputer z30 Data Book
MPU Board Schematics (D-07908-60002-50)
3
BLOCK DIAGRAM
3.J
oveRVIEW
The detailed block diagram (Figure 1) sho~ the basic
structure of the microprocessor (MPU) board. Central
to the diagram is the Z80A Central Processing Unit
(CPU) with its address and data buses (shown on the
diagram as the Z-buses. All information to and
from the CPU passes on the Z-Data bus. To prevent over
loading this b4S, bufrers are used to distribute the load
over three other buses. They are the Memory Data (MO) Bus.
Processor Data (PO) Bus and Motherboard Data (D) Bus. All
memory on board is connected to the Memory Data Bus.
The Processor Data Bus accesses most of the l'emaining
hardware on the board. The Motherboard Data bus co~ects
the Z Data Bus to other boards in the drive which
must communicate with the processor board.
The Z-Address Bus from the CPU is buffered and becomes the
Memory Address (MA) Bus. It addresses the memory and is used
by the address decode hardware for accessing circuitry on the
rest of the board. orr the Memory Address Bus is the lat :\ed
Motharboard Address (A) Bus. This bus is used to address
ot.herboards in the d~'ive unit.
--+---------i----··--+---------+------------------+----------------------------
A
'ISSUF~
I sb/RT 104-22-81 IMODEL 7908
ISTK ,
07908-60002
--+---------+------~+---------+------------------+----------------------------
B148-6199
I db/JSKI02-09-B3 I I.M.S. MICROPROCESSOR BOARD
--+---------+---- . --+---------+-----------------------+----------------------/
IBY
loATE APR 12, 1984
--+---------+-------+---------+-----------------------~-----------------------
TI P.C.'
I APPR
DATE
IAPPD
ISHEET ,
4
OF
34
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ISUPERSEDES
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+------------------------------------------------------------------------------+
'~-+------
+------------------------------------------HEW LET T - PAC K A R D C O.
3.2
BRIEF DESCRIPTION OF EACH BLOCK
3.2.1
CPU
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D/H: C2,50A
-----------------------------+
The Central Processing Unit, a ZSOA-CPU, is the heart
of the processor board. The Z80A-CPU has a maximum
clock frequency of ~ MHz. On this board the clock
frequency is 3.75 MHz.
3.2.2
Clock Circuit
The function of the processor clock circuit is to provide
a reliable clock signal meeting the specification~ of the
processor chip.
3.2.3
Control Logic
This block of circuitry takes the control signals of the
ZSOA-CPU and generates signals necessary to control both
on and off board memory and registers.
J.2.~
Address Decode and Bus Control Logic
This logic takes information on the address bus &n,d
generates select signals to allow accessing of the device
being addressed. This section ot circuitry also determines
which of the three data buses are to be connected to the
microprocessor data bus.
3.2.5
Memory
There are three types of memol'J which may be u3ed C)f.& the
board: Read Only Memory (ROM) for program storage. Read/
Write Memory (RA~) for temporary storage of program
varia.bles, 8J"d Era~J.ble Programmarle Head Only Hemc)ry
(EPROM) for program storage.
:--+---------+-------+---------+--------,---_. ----+---------------------------I sb/RT 104-22-81 IMODEL (908
ISTK , 01908-·60002
1--+---------+-------+---------+------------------+----------------------------,
I B148-6199 I db/JSKI02-09-83 I I.M.S. MICROPROCESSOH BOARD
1
1--+---------+-------+---------+-----------------------+-------,----------------1
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ILTI P.C.' 1 APPR I DATE
IAPPL)
ISHEET ,
5 OF 34
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ISUPFRSEDES
IDWG 'A,-01908-60002-4 l
+----------------------------------------------------- ------------------------+
IA IISSUED
~-----------------.--------------------------
''-r<
HEW LET T - PAC K A R D
3.2.6
C O.
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/ .-----------------------------I~
CTC
The ZSOA-CTC (CoUllter Timer Circuit) chip provides the
microprocessor board with four independently programmable
counter/timers, each capable of generating an interrupt
to the processor.
3.2.7
Linus Counter
The Linus Counter is a four bit counter which is cascaded
with one channel of the CTC to provide a 12 bit cou.~ter
which is used to l:eep track ot sectors on 'the LINUS tape
drive.
3.2.8
Drive Sense Register
The Drive Status Register provides 'the processor with
eight input lines for monitoring vital drive functions.
3.2.9
'..,..'
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Self Test
~~itches
and Display
The se,lf test .~ .:"tches and display provide user interface
to the self test routines executing on the processor board.
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1--+---------+-------+----------+------------------+----------------------------1
IA IISSUED
1 sb/RT 104-22-81 IMODEL 7908
ISTK , 07908-60002
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1--+---------+-------+---------+------------------+-------------------p--------I
1 BJ4B-6199
I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
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I--~---------+-------+----------+-----------------------+-----------------------1
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'1 P.C.' I APPR I DATE
IAFPD
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6 OF 34
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IST.'PERSEDES
IDWG 'A-07908-60002-1, 1
+-----------------_._-----------------------------------------------------------+
+------------------------------------------I
, B E WLET T - PAC K A R D C O.
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If
LOGICAL OPERATION
1f.1
MPU ADDRESS AND DATA BUS STRUCTURE
'lbe ZSOA-CPU address bus (ZAOH-ZAl5H) is buffered by
0141 and U111 to form ~he Memor,y Address Bus (MAOB-MAl5H).
Except for the ROMs (U241, u261, U271, U291, and U2101)
which are on the Z-Address Bua,
all othQr deviees are on the Memory A~dress BUI. The
Memory Address Bus is buffered by transparent latches U431
and !!432 to torm the Motherboard Addl'ess Bus (lOR-AllH).
The ZSo data bus (ZDOB-ZD7H) has three bi-directional
butfers ereatina the Memory Data Bus (MOOH-MOTH) through
U312, the Processor Data Bus (PDOH-PD7H) throulh U422,
and the Motherboard Data Bus (DOH-D7H) through U412.
1--+---------+-------+---------+------------------+------------.---------------IA 1ISSUED
I sb/Irr 104-22-81 IMODEL 7908
ISTK , 07908-·60002
1--+---------+-------+---------+------------------+---------------------------I BI48-6199 I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
1--+-------,--+-------+---------+-----------------------+-----------------------1
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1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR I DATE
IAFPO
ISHEET ,
7 OF 34
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1--+---------+-------+---------+-----------------------+-----------------------1
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I SUPERSEDES
IDWG 'A-07908-60002-4 I
+------------------------------------------------------------------------- -----+
+------------------------------------------- /
'....., I
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»..2
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ER48 D/H: C2,5~A
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SOB INTERFACE
The zao emulator board (SOB) connects directly on the
Z-Buses (ZAOB-ZA15B and ZDOH-Z07H) throuth connecto!' n.
All the control lines are directly accessable to the SOB
through Jl except tor MlL and RFSHL. When the SOB is
connected to 31, it grounds the Bu. Reque.t line (BUSRQL)
torcing the processor to tri"state all coctrol line.
except MlL and RFSBL.
Since MIL and RFSBL are not tri-stateab1e, a tri-state
butter (Ul·'2) is used to d:i.=:;able them upon a Bus Request
trOll the SOB. !"he bufter is inverting because M1L is
needed active high in the control 10,ic circuitr,v and
timing is too critical to use a non-invertiDc
butter anl~ then invert the sipal. S:i.nce the butter
is inverting, this requires RFSHL to be buftered ttorice
to obtain the proper polarity.
The M1L signal trom the SOB nst be inverted
to match the polarity required on the MPU board.
Since this inverter (0172) is not tri-stateable
(it is always enabled), a jumper (E158) is used to
connect it to the control logic. A trace .Ult also
be cut betweem 0161-27 amd U172-6 prior to connecting
the SOB to the MPU board.
Also since the SOB hal its own on-board clock, U181
Blust be removed trom the board to peni t the us. of
an external cl.ock.
--+---------+-------+---------+------------------+---------------------------I sb/RT 104-22-81 IMODEL 7908
ISTK , 07908-60002
1--+---------+-------+---------+------------------+---------------------------I B148-6199 I db/JSKI02-Q9-83 I I.H.S. MICROPROCESSUR BOARD
1--+---------+-------+---------+-----------------------+----------------------1 1
I I
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IBY
IDATE APR 12, 1984
1--+---------+-------+---------+--------_·· ------------+----------------------IA IISSUED
'JTI P.C.'
I
APPR
1
DATE
IAPPD
ISHEET
,
8
OF
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,~-+---------+-------+---------+-----------------------+-----------------------
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REVISIONS
ISUPERSEDES
Jowa , A-07908-60002-4
+------------------------------------------------------------------------------+
+------------------------------------------- /
HEW LET T - PAC K A R D C O.
~.3
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ER48
D/B: C2,50A
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CLOCK CIRCUIT
The clock circuit takes a 7.5 MHz single-chip oscillator,
Y192, and divides the output by two with flip-flop 0181
to lenerate a 3.75 MHz sienal with a 5~ duty cycle.
Gat. U191 is used to disable the oscillator signal to the
flip-flop and allow DTS-70 to control the proc~ssor clock
by togglinl the preset and clear inputs of the flip-flop.
The 3.15 MHz output of the flip-flop goes to an active
pull-up circuit to meet the ZSOA-CPU clock specification
which requires the minimum hieh level to be .6v ~~low Vcc,
and a rise and fall time of 30 nsec.
The active pull-up consists of a 74s2~0 inverting butfer,
Ul72, and transistor Q193. A high output fro. the flipflop turns off Q193 and causes Ul72 to go low. A low
output from the flip-flop causes U172 to 10 high and
turns on Q193 which quickly pulls the output of U172
close to Vec.
~.~
CONTROL LOGIC
The control logic buffers and latches control
.ignals from the processor and generate other signals
necessary to intertace with hardware both internal and
external to the MPU board.
~.~.l
J
J
Control Butter
U371 i . used to buffer the ZMREQL, ZIORQL, and ZRDL
lin •• from the processor, the power on relet (GRSTL),
the latched read .ignal (ROL) from U351, and the latched
write signal (LWRL) from U181. RDL (latched by U351 when
LBSElfL i. active) is used by the proce.~or to ini,tiate
reads from other boards in the drive. The buftered
latched write signal (WRL) is similarly used to initiate
a write. See timing diagrams (figure. 2-6).
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1--+---------+-------+---------+------------------+----------·------------------1
JA IISSUED I sb/RT 10~-22-81 IMODEL 7908
1ST! , 07~u8-60002
I
I--~---------+-------+---------+------------------+----------------------------1
I B148-6199
I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
1
1--+---------+-------+---------+-----------------------+------------------------1
1 I
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IDATE APR 12, 1984
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1--+---------+-------+---------+-----------------------+------------------------1
ItTI P.C.' 1 APPR I DATE
IAPPD
I SHEET ,
9 or 34
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1--+---------+-------+---------+-----------------------+------------------------1
I
REVISIONS
1SUPERSEDES
lowe 'A-07908-60002-~ I
+-------------------------------------------------------------------------------+
+--------------- --------------------------- /
/ £R48 DIH: C2.50A
/ -----------------------------+
/ hp /
B E WLET T - PAC K A R D C o.
~.4.2
/
Control Latch
Quad-latch U382 is used to generate and latca various
control signals. The first flip-flop, 10, i8 used to
latch the buffered I/O signal from U371. Gate U372 is
used to OR the latched I/O signal and the 10RQL signal
to provide a latched signal ~hich loes active soon
after IORQL.
The next flip-flop, 20. creates the latched interrupt
signal, IITL. Gate U372 provides an active sianal
to the ~lip-flop when MlH goes active without a
BMREQL (this condition signals an interrupt acknowledge
cycle to the processor).
Flip-flop 3D is used to produc~ the latched memory l~quest
signal (LMREQL). G~te U352 provides an active signal to
this flip-flop when buff~red memory request (BMREQL) is
active and there is no refr.. sh or interrupt cycle (0342).
The lalt flip-flop, ~D, generates a bus enable signal,
BUSENL, when there is either an I/O or memor,y request
without an interrupt or refresh cycle (U392 and U3~2).
J-K flip-flop, U3102, provides a latched bUI enable signal
(LBSENL) which is synchronized to the falling edge of the
procellor clock.
See timing diagrams (figurel 2-6).
4.4.3
Latched Write Flip-flop
The latched write flip-flop, 0181, loes active on the
fallin, edge of the processor clock after BUSENL goes
active and there il no read or power-on-reset signal.
Gate U322 genera.tes a window for toggling the flip-flop.
Gate U312 will hold the flip-flop inactive if there is
a read (or power-on-reset).
See timing diagrams (figures 2-6).
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1--+---------+-------+---------+------------------+----------------------------1
IA 'ISSUED
'sb/RT 104-22-81 IHODEL 7908
ISTK , 07908-60002
,
1--+---------+-------+------,---+------------------+----------------------------1
1 BI48-6199 J db/JSKI02-09-83 I I.H.S. MICROPROCESSOR BOARD
,
1--+---------+-------+---------+-----------------------+------------ ----------1
I 1
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IDATE APR 12, 1984
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1--+---------+-------+---------+-----------------------+-----------------------1
'LTI P.C.' I APfd I DATE
IAFPD
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REVISIONS
I SUPERSEDES
IOWG
'A-07908-60002-~
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+------------------------------------------------------------------------------+
+------------------------------------------- / I hp I / ER48 D/H: C2,50A
B E W LET T - PAC I A R D C O.
/
/ -----------------------------+
~.4.4
ROM Chip Enable Circuit
This circuit lenerates the chip enable signal for
l1asked ROMs. When EPROMs are used in the ROM slots.
the trace at E3113 Irounds the chip enable and holds
the EPROMs always enabled (this reduces noise on the
board). The output enable is t'.len used to select the
addressed EPROM. ROMs, however~ require the chip
enabl~ signal to
high for a period between each
access cycle.
,0
Jumper E3114 connects the chip enab~e (ClL) to the ROM
chip enable circuitry. This lienal il produced by J-K
flip-flop U3102. On an op-code fetch. U3102 is activated on the falling e~ge of the processor clock when
M1 il active. CEL goe$ inactive, when buffered read
(BRDL) loel itl,t:tive. On a memory read eycle, 03102
is activated b~ BRDL ,oinl active and turned off when
BRDL ,oes inactive. Bote that the trace at E3113 must
be cut to use ROM.. See timinl diagrams (figures 2-6).
~.5
ADDRESS DECODING LOGIC
The addre.s decoding and bus control functions are PROM
based to provide maximum flexibility. PROM U311 takes
address lines MAl5H thru MA9H and divide. the 64 !byte
aemory space into 128 blocks of 512 bytes. The A7 input
ot U311 is a lense line for the SOB. It allows one
to disable the ROM memory lpace on the processor
board in order to use the 16K byte. ot dynamic RAM on
the SOB for procram .emory.
The PROM's two chip select linel are tied to inverter U391
which has a resistor to +5v on its input. This allows
the DTS-70 to disable the address decode logic.
The PROM pattern for the Address Decode PROM is shown
in rieure 13.
--+---------+-------+---------+------------------+-----------.. _--------------1 sb/M 104-22-81 IMODEL 7908
l5'l'I , 07908-·60002
.--+---------+-------+---------+------------------+-----------... --------------I BI48-6199 1 db/JSKI02-09-83 1 I.t-i.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+----------------------I I
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IDATE APR 12, 198..
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
ISHEET' 11 OF 34
1--+---------+-------+---------+-----------------------+----------------------1
REVISIONS
1SUPERSEDES
IDWG , A-07908-60002-4
+------------------------------------------------------------------------------+
IA IISSUED
+----------------.-----------.---------------
~I
B E WLET T - PAC K A R D C O.
~. 5.1
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ROi1 and Patch EPROM Decoding
The four output lines (DO-D3) of U311 Co to the bus control
PROM, U3~1, and the transparent latch 0351. This latch
waits until the PROM outputs are valid before latching.
The four output lines of the latch 10 to a 3 to 8 decoder,
U361. When latched ~ROH output DO is low, U361 activates
the enable lines for the ROMs andlor EPROMs. The output
of the decoder is synchronized by latched memory request
(LMREQL) and disabled if there ia a latched interrupt
(INTL) •
With a total of seven select lines, the ROMs and EPROM.
can be configured in a number of W&7s. For development,
all seven selects can be used with ~Kb~e EPROMs to provide
a total of 28 Kbytes (see fieur. 1). For 8 Ibyte masked
ROM. or EPROM., six select lines can be used for a total
of 4S Kbytes (see figure 8).
--+---------+---~---+---------+------------------+----------------------------
IA IISSUED
1 sb/RT 104-22-81 IMODEL 790S
ISTK , 0790S-60002
1--+---------+-------+---------+-------------------+---------------------------I B14S-6199 I db/JSKI02-09-83 1 1.1.f.8. MICROPROCESSOR BOARD
1--+---------+-------+---------+----_·_----------------+----------------------1 I
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IDATE APR 12, 1984
+___ ------+-------+---------+----------------------_+----------------------1 __
.IT I P.C.' I APPR I DATE
IAPPD
ISHEET , 12 OF 34
~-,r--+---------+-------+---------+--------------------- --+-----------------------
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REVISIONS
ISUFERSEDES
IDWG , A-0790S-60002-4
+------------------------------------------------------------------------------+
+------------------------------------------I
I B E W LET T - PAC K A R D C O.
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Ram. Register and Board Select Decoding
Latched PROM outputs D1 and D2 also become .elect lines SELA
and SELB for the register and board select 101ic. The bus
control PROM U341 generates an enable tor the register
and board select logic. This is output D1 of U341. It is
latchecl by U351 and synchronized with LMREQL thru t13B1This signal, OTHERL. goes to the enable of the upper half
of u442, a 2-to-4 decoder with SELA and SELB as input ••
The upper half of u442 generates enables lines RAMEH1L
and f'J.MEH2L (for the two RAM sockets) and SL1L (the board
.elect signal tor the DNA BUFFER). It al~o produces an
enable signal for other board select and register select
101ic.
The lower half of u442 is enabled when the above enable
and addre.. line. A9H and ABH are both low (.ee gates u441
and U451). This part of U442 decodes address line. LA6H
and LA78 into four 64 byte blocks for the register selects.
CLSTOL and CLST1L are used to reset the two .elf-test switch
latch•• , ETSELL i. used to select registers on a previously
used IT, and MPREG enable. the 2-to-4 decoder U321. U321
decod•• addre.s bits LA4H and LA5H into four 16 byte blocks.
SLSEKL i. used to .elect the drive senae reeister and
SLREVL to .elect the rev-rework register (see figure 9).
The board .elect. ar~ generated by 3-to-8 decoder U452.
It is enabled by LMREQL and the enable generated by output
line 0 of the upper halt of U442. U452 decod•• addre ••
bit. LA6H. LATH and ASH into eight 64 byte block. when
address bit A9H ia high (.ee figure 9). See Figure 11
tor assignment of these selects to the various boards.
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J--+---------+-------+---------+------------------+---------------------------IA IISSUED
I sb/ff! 104-22-81 IMODEL 7908
ISTK , 07908·6,0002
1--+---------+-------+---------+- -----------------+---------------------------I 1148-6199 I db/JSKI02-C9-83 I I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+------------------------+----------------------I I
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1--+---------+-------+---------+----------------------+----------------------ILTI P.c.' I APPR I DATE IAPPD
ISHEET' 13 OF 34
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
I SUPERSEDES
ID~G , A-07908-60002-4
+------------------------------------------------------------------------------+
+------------------------------------------B E V LET T - PAC K A R D C O.
/
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ER48 D/8: C2,50A
-----------------------------+
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~.5.3
I/O Decodinc
A 3 to 8 decoder (U421) il used to decode the I/O
space. Address line LA7H enable. the decoder when
it is active high. This .elect. the upper 128 byt.~.
of the I/O .paCA. The other three address line.,
LA4B-LA6H, divides this space into .ight block. ot
16 byte. ( ••• figure 10). The.e decod.d I/O line.
are used to select the PHI chip on the DMA board,
the CTC chip and other devic•• on the "PU board.
See table in figure 12 tor select line a •• ian-ent ••
,
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1--+---------+-------+---------+------------------+---------------------------fA IIsSUED
I sb/M 104-22-81 IMODEL 1908
ISTK , 07908-60002
1--+---------+-------+---------+------------------+---------------------------1 BI48-6199 I db/JSKI02-09-83 1 1.".5. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+----------------------I I
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IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------LTI P.C.' I APPR I DATE
IAfPD
I SHEET , 14 OF 3iJ
1--+---------+-------+---------+-----------------------+----------------------I
REVISIons
I SUPERSEDES
low , A-07908-60002-~
+-------------------------~----------------------------------------------------+
+------------------------------------------- /
/ hp /
B E W LET T - PAC K A R D C O.
4.6
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/ ER48 D/U: C2,50A
-----------------------------+
BUS CONTROL LOGIC
The bus contl'ol logic is PRat based to main tain the
same flexibility as the address decoding lOlic. Outputs
D2 and D3 of PROM U341 are latched by U351 and go to a
2-to-4 decoder, 'J321- The lower three outputs of this
decoder enable the data bus transceivers for the
Memory Data Bus (enable line MBENL) , the Processor Data Bus
(enable line RBSENL)9 and the Motherboard Data Bus (enable
lin~ MBSENL).
The decoder o~tputs are synchronized
with BUSENL thru gate U381.
Inverter 0112 and pu1l-up resistor R191 are provided to
disable the data bus transceivers tor Signature Analysis
and DTS-TO by grounding the data bus enable line (DBENB).
The inputs to the PROM include the four output lines
from the address decode PROM, the latched I/O signal
(LIORQL) and the outputs of three ,ates, U451, U461. and
U322. Gate u451 helps to separate bus control functions
for the board selects and register selects. LIORQL,
late U322 and both uJ.61 ptes, help separate bus control
functions on the I/O mapped board and register .elect••
See Figure 14 tor the PROM pattern.
4.1
MEMORY
The on board aemory consists of ROM, rtAM and EPROM.
The processor board has six slots for 8 Kbyte ROMs
or EPROMs for a tota1 of 48 Kbyte.. It al.o has one
slot for a 4 Kbyte EPROM.
There are two RAM slots tor use with either 1 !byte or
2 Kbyte RAMs. There are 3 Kbytes ot memory space available
tor RAM.
--+---------i-------+---------+------------------+------------.. --------------I sb/RT 104-22-81 IMODEL 1908
ISTK , 07908-60002
1--+---------+-------+---------+------------------+------------.. --------------. 1 BI48-6199 I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+-----------------------I I
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IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+--------.--------------ILTI P.C.' I APPR I DATE
IAPPD
I SHEET , 15 OF 34
1--+---------+-------+---------+-----------------------+--------.--------------I
REVISIONS
1SUPERSEDES
IDWG , A-·07908-60002-4
+----------------------------------------------- ------------------------------+
fA fISSUED
+-------------------------------------------
I~I
R E WLET T - PAC K A R D C o.
4.8
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CTC
Channel 0 of the etC (U211) il triggered bf the Track Crossing
signal (TKX) which comes from off-board and is buffered
with Scbaitt-trigger U3101. This channel is used b.Y t4e
firmware in instrumenting seeks.
Channel 1 is cascaded with Channel 0 to produce a 16 bit
counter which il used by the Command Executive.
Channel 2 is eascaded with the Linul counter and is
used for seeks in the Linus tape drive. The output of
this channel (CTCMOH) is buffered bf U311 and lent to the
Linus TIS board.
Channel 3 of the CTC is triggered by the sector ttminc
pulse signal (STPL) which comes fro. ofr-board and il
buffered by Schmi·tt-trigger 03101. This channel is used
to count sectors in read and write firmware routines.
'!'he interrupt line of the CTC i. tied directly to the
maskable interrupt input of the ZSOA-CPU. The CTC
uses Mode 2 interrupt configuration.
LINUS COURTER
'!'he Linus Counter. u462, is a four-bit down counter
which can be loaded ~ the 'procelsor and read through
the drive .ense regilter (lee figure 16). Gate u441
cenerate. a load sienal to the counter when the
Linul counter select line (LCJrl'I{L) and latched write
(LWRL) are active.
The counter i. clocked by an offboard ligna1 (Cl'CTH)
from the Linus TIB board. This signal is buftered b.Y
by Schmitt-trigger U3101 ~d inverted b,y U391 to obtain
the proper polarity.
'!'he Linus Counter is cascaded with Channel 2 of the CTC.
The erc is clocked by ,ate U461 when the Linus Counter
reaches a count of zero (MIN/HAX output active)
and CTCTH is active. The MIN/MAX
output (CTCLOH) also goes oftboard to the TIB.
--+---------+----,---+---------+------------------+---------------------------,sb/Frr 104-22-81 IMODEL 1908
ISTK , 01908-60002
1--+---------+-------+---------+------------------+---------------------------1 BI48-6199 1 db/JsxI02-09-83 1 I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+----------------------1 I
I I I
IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+-----------------------1
IA 'ISSUED
ITI
~-..,.--+-
I
'APPR J DATE
fAPPD
ISHEET' 16 OF 34
I
------- -+- - -- .. --+- --- --- --+-- ---------------- --- --+- - - - --- - --- - - - - - - - -- ---I
P.C.'
REVISIONS
I SUPERSEDES
IDWG'
A-01r~8-60002-4
I
+------------~-----------------------------------------------------------------+
+------------------------------------------- /
/ hp /
HEW LET T - PAC K A R D C O.
~.10
/
/
/ ER48 D/H: C2,50A
-----------------------------+
DRIVE SENSE REGISTER
The drive sense register consists of two multiplexers,
u472 and u492. The A channel ot the multiplexer connects
ei,ht .ense line. to the Processor Bus. The table in fig.15
define. the bits in the register. All of the sense lines
sense lines come directly off the mother board and into
the sense reaister except for the index pulse (RB1). It
is buffered with a schmitt-trigger, U3101, and used to
toggle • flip-flop, U332. 7his allows the processor to
catch the short ihdex pulse by watching for the register
bit to toggle with each index pulse.
The lower two bits ot the B channel indicate the status
ot the self-test latches. The ~bird bit is not us~d.
The fourth bit is used by the tirmware to detect the
connection ~t the Signature Analysis test fixture used
in manufacturing. !he upper four bit. of the B char~el
contains the status (count) ot the Linus Counter.
See figure 16.
1
I
l
I
I
I
I
I
Memor, address bit 0 (MAOH) is used to select between the
channels. Gate U451 is used to enable the output of the
multiplexers by taking the sense register select line
(SLSEML) and bating it with the buttered read signal (BRDL)
to produce a low true signal when the former two are active.
--+---------+-------+---------+------------------+----._-----_ .. _--------------,
1 sblRT 104-22-81 IMODEL 7908
ISTK , 07908-60002
I
,--+---------+-------+---------+------------------+----------------------------1
I BI~8-6199 'db/JSKlo2-09-83 1 I.M.S. MICROPROCESSOR BOARD
I
1--+---------+-------+---------+--- --------------------r-----------------------I
I 1
1 I
I
IBY
IDATE APR 12, 1984
I
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C., I APPR 1 DATE
IAPPD
1SHEET , 17 OF 34
1
1--+---------+-------+---------+-----------------------+--:-----·---------------1
I
REVISIONS
f SUPERSEDES
IDWG 'A-I17908-60002-4 I
+------_._----------------_._----------------------------------_ .. _-------------+
fA IISSUED
+------------------------------------------B E WLET T - PAC K A R D C
11 .11
o.
I
/ hp I
I
I
I
ER~
D/H: C2,50A
-----------------------------+
SELF -TEST SWITCHES AND LED DISPLAY
The t"O self-test s"itches, Sl?O and Sl~O, set two
flip-flops (both in 0142) when activated. These tlip-flops
can be read by channel B of th~ drive sense register
(see figure 16). Each flip-flop can be cleared by address in,
it (processor read or write to latch addresses).
The self-test display, DS129, i. a seven-segment LED
driven by an eight-bit latch, U131. Resistor pack, R130.
limits current in the LEDs. Gate 0381 clocks the latch
When the LED select line (LEDSLL) and la~:hed write (LWRL)
are asserted.
--+---------+--.. ----+---------+------------------+---------------------------I sb/RT 10~-22-81 IMODEL 7908
ISTK , 07908-60002
1--+---------+-------+---------+------------------+---------------------------I BI ~8-6199 I d1:)/JSKI02-09-83 1 I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+----------------------"+----------------------I I
1 I
I
IBY
IDATE APR 12, 1984
1--+---------+--------+---------+-----------------------+----------------------ILTI P.C., I APPR I DATE
IAPPD
1SHEET , 18 OF 34
'1--+---------+-------·---------+-----------------------+----------------------I
REVISIONS
I SUPERSEDES
IDWG , A-07908-60002-1I
+------------------------------------------------------------------------------+
IA IISSUED
!
•
•.
r-
.
-
~I
·• .
I
I
,.
r.mmp.CTIC'N
~
;.
o
•
•
0
I
...
r'
16
,
II'
rITI
...
T
.1
G
~
!
1"""7
'l'
zn
'"
G
:
:...
~6 MA
~
CPU
~
- "]1"
Z}.
.
0
fTI
~
RCM
I
~
1:
WI
OR
Ir'o
zsn
-;,
I
!P)Qf
~I'
~~
l
,.•
," ...c i
.·
I
Emr.t'.AL
~
~
,
,~
,
8
fo!D
~
['.
'll
..:...
,
.
• ..
~
I
I-
I
0
LOGIC
I
~
g
~
CLOCK
ClnCUlT
-
-
I
r
.
'I'
~
~8
zo
I
....
.I
""""
~
,
CTC
-
,
DECODe AND
BUS CONTROL
,
..!!I.
LOGIC
-
-
•• ~
C\
~
& 5
~
a
~
0
....
ro
CD
CJ\
"'I"
~
~
I
0
0
0
~,
Cl
~....
~
~
I
0
0
,
~
....
-
8
~
I
FIGURE 1
DIAGIW1
~.J
,
-,
i
I
Ut!US
Cc(~Tr:R
4
I
8
.JI
~
,
,
I
-
DRIve
STATUS
.I
--....
.6
~
.-
I
MI'U BOARD StOCk
~
I
I
- "u
Ptl
1
f' •
~
...::::.
......
,
L
I
\.oj
I
D
I
r'
.0
~
~OTJ1ER80ARt
-"
lJ
C
12
, TO . . .
I
~
~
~
I
,
~
"
>
()
.Jl
8
os
">
0
I
-
~
I
BOARD SEi,ECT
AND REGISJER
DECODE LOGIC
A
.I
I--
\0
,-,- .
-f
-
ROM ADDRESS
-
......
nl
I-CONTROL
~
,.
-I
~J
II
SELF-
SELF-
T£:ST
TUST
SWiTCH
SWITCH
• 1
, 0
I
+------------------------------------------- /
/ bp /
HEW LET T - PAC K A R D C O.
T2
Tl
I_I
eLK
ZHREQL
ZM1L
_,-,
/-\
\
--\
1-
/
/
/
\
/
\
LMREQL
\
/
BUSENL
\
/
LBSENL
J
I noL
/
T4
T3
-,
ZRFSIIL
ZRDL
/
/ ER48 D/B: C2.50A
-----------------------------+
/
\-
/
\
J
I
J
CEL
\
/
FIGURE 2
OP-CODE FETCH CYCLE
--+---------+-------+---------+------------------+---------------------------I sblRT IO~-22-81 IHODEL 7908
ISTK , 07908-60002
1--+-------_·_+-------+---------+------------------+---------------------------'8148-6199 I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+----------------------I ,
I /
I
IBY
IDATE APR 12. 1984
.--+---------+-------+---------+-----------------------+----------------------ILTI P.c., I APPR 1 DATE
IAPPD
ISHEET' 20 OF 34
1--+---------+-------+---------+-----------------------+----------------------,
REVISIONS
I SUPERSEDES
IOWG , A-07908-6ooo~~-4
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------- I
I
B E W LET
PAC
T -
KA
ZMREQL
. ,
ER48
D/H: C2,50A
,-----------------------------+
'1'3
1- -
I
\
I
\
I
,
\
BUSENL
I
I
I
\
LBSENL
,--
I
\
RDL
\
CEL
\
/ --
I
I
\
LWRL
C O.
I
_-:-'_-:-'-:--'_'.'-1--
LMREQL
ZRDL
D
T2
Tl.
CLK
R
I
bp
\
I
t
I
I
I
I
I
I
FIGURE 3
MEMORY READ/WRI'l'E CYCLE
1
I
I
,
1--+---------+-------+---------+------------------+----------------------------1
IA 'ISSUED
1 sb/rrr 104-22-81 IMODEL 7908
ISTK , 07908-60002
1
1--+---·_-----+-------+---------+------------------+----------------------------,
I BI48-6199 I db/JSKI02-09-83 1 I.M.S. MICROPROCESSOR BOARD
I
1--+---------+-------+---------+-----------------------+-----------------------1
I I
I / , - - 1BY
IDATE APR 12, 1984
1
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR 1 DATE
IAPPD
ISHEET , 21 OF 34
I
,--+---------+-------+---------+-----------------------+------------------------1
,
REVISIONS
I SUPERSEDES
IDWG I A-01908-60002-4 I
+-------------------------------------------------------------------------------+
/ +------------------------- .. ----------------B E WLET T - PAC K A R D C O.
T2
Tl
CLK
TIl
D/H: C2,50A
-----------------------~-----+
T3
,
/
/-
\
LIORZL
LWRL
I
/
\
I
LBSENL
ZWRL
ER48
/
\
I
BUSENL
RDL
/
bp /
-,--,_,-,_,-,_,-,
1-',
,
I
,-,
ZIORQL
ZRDL
I
I
I
I
----\
1
I
---
/
I
\----y/
/-
\
\
I
/
\
/
FIGURE 4
I/O READ/WRITE CYCLE
I
I
1
I
f
I
I
1--+---------+-------+---------+------------------+-----.----------------------~
IA IISSUED
I sb/rrr 104-22-81 IHODEL 7908
,STK , 07908-60002
I
,--+---------+-------+---------+------------------+----------------------------~
I BI4e-6199 I db/JSKI02-09-83 , 1.M.5. MICROPROCESSOR BOARD
II
1--+---------+-------+---------+-----------------------+-----------------------1
I I
I l , - - 1BY
IDATE APR 12, 1984
I
--+---------+-------+---------+-----------------------+-----------------------,
1LTI P.C.' 'APPR 1 DATE
IAPPD
ISHEET' 22 OF 34
I
1--+---------+-------+---------+-----------------------+-----------------------1
f
REVISIONS
I SUPERSEDES
IDWG I A-07908-60002-1i I
+---------------------------------------------------------~--------------------+
+-------------------------------------------
I
I
B E WLET ~ - PAC K A R D
LAST
T-STATE
eLK
Tl
T2
C
o.
TW
"p
I
I
TW
I
I
ER48
D/B: C2,50A
-----------------------------+
T3
T4
-'-'-'-'-'-'_'-'_-,-'_'-'_'-1_1
,
I
I
I
,
,
,
,
ZINTL --\-y-I-
=,= = =,= : =,= ==,= ==,= : =,= = =,= =
'--,-1
·ZMREQL
ZMlL
,
\,
I
\,---....----,
I -
ZRFSHL
ZIORQL
TNTL
1-
I
I
\
,
_I
i
LHREQL
BUSENL
LBSENL
.'IGURE
5
INTERRUPl' REQUEST/ACKNOWLEDGE CYCLE
--+---------+-------+---------+------------------+---------------------------I sb/Frr 104-22-81 'MODEL 7908
ISTK' 0790 8-60002
,--+---------+-------+---------+------------------+---------------------------I BI4&-6199 I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+----------------------I ,
I /
I - IBY
IDATE APR 12, 1984
,--+----------+-------+---------+-----------------------+-----------------------,
'LTI P.c., I APPR I DATE IAPPD
I SHEET , 23 OF 34
I
1--+----------+-------+---------+-----------------------+-----------------------,
I
REVISIONS
ISUPERSEDES
IOWG # A-07908-60002-4 1
+--------._---------------------------------------------------------------------+
fA IISSUED
1
+------------------------------------------- /
/ bp /
I
B E WLET T - PAC K A R D C O.
LAS'!'
i'-STATE
Tl
T2
/
T4
T3
I
ER48
D/B: C2,50A
-----------------------------+
T5
CLK
NMIL
=: -::\'._1-= ==:: =:: ==~ :: :: :: =: : : =: ::
-0
\
ZMREQL
1-\__1
:
ZM1L
ZRFSHL
\
I
\ ---
/
IHTL
LMREQL
\,_ _ _ _,1
BUSENL
\ _ _ _ _,1
LBSENL
\._--_./
FIGURE 6
,
,
J
MON -MASKABLE INTERRUPr REQUEST
1
I
I
I
1
I
I
1--+---------+-------+----,-----+------------------+---------------------------IA IISSUED
I sb/RT 104-22-81 IMODEL 1908
ISTK , 07908-60002
1--+---------+-------+---------+------------------+---------------------------I BI48-6199 I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
,--+---------+--------+---------+-----------------------+-----------------------1
I I
I I I
IBY
IDATE APR 12, 1984
I
,--+---------+-------+---------+-----------------------+-----------------------,
ILTI P.C., 1 APPR , DATE IAPPD
ISHEET' 24 OF 34
I
,--+---------+--------+---------+-----------------------+-----------------------1
,
REVISIONS
ISUPERSEDES
.
IDWG 'A-07908-60002-4 ,
+--------------_._--------------------------------------------------------------+
+-------------------------------------------
I
I ER~ D/H: C2,50A
I hp I
I
I -----------------------------+
B E W LET T - PAC K A R D C O.
AlO
All
Al5
A14 Al3
00
A12
01
10
0
0
0
0
EPROM 1
0
0
0
1
EPROM 2
0
0
1
0
EPROM 3
0
0
1
1
EPROM 4
0
1
0
0
EPROM
0
1
0
1
EPROM 6
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
1
11
I
I
<---
4
Kbytes
~
EPROM 7
\ \ \ \ \ \ \ \ \ \1
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\ \
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\ \
\
\
\
\
\
\
\
\
\
,
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
I
\ 1
\ \1
\
\
\
I
\ 1
\1
I
\ \ 1
\ \ \1
\ \ \ \ \ \ \ \ \ I
,--\--\--\--\--\--\--\---\---\-1
, SL1L
I
,\
\ \ \ \ \ \ \ \1
,1-\.-\,',',-\r\-\--\-\_:
~DMA BUFFER~
\
0
1
1
1
REGISTER & BOARD
SELECTS
(SEE FIGURE 9)
I
/
'_\_\_1
~~I
FIGURE 7
HEMORY HAP (EPROMs)
--+---------+-------+---------+------------------+----------------------------1
I sb/RT 104-22-81 IMODEL 7908
ISTK , 07908-60002
I
1--+---------+-------+---------+------------------+----------------------------1
I BI48-6199 I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
1
1--+---------+-------+---------+-----------------------+-----·------------------1
I I
I
I
I - IBY
IDATE APR 12, 1984
1
1--+---------+-------+---------+-----------------------+-----·------------------1
ILTI P.C.' I APPR I DATE
IAPPD
ISHEET' 25 OF 34
I
1--+---------+-------+---------+-----------------------+-----------------------1
I
REVISIONS
ISUPERSEDES
Iowa 'A-01908-60002-4 1
+------------------------------------------------------------------------------+
IA IISSUED
,
~
------------------------------------------- I
I
I~I
HEW LET T -
PAC
I ARD
I
O.
A14
A13
01
10
o
0
0
o
01
1
0
0
1
o
o
1
o
o
o
1
1
o
1
o
o
o
1
o
1
o
1
1
o
o
1
1,
1
1
o
o
1
o
o
1
01
EPROH5
I
1 ' ________________________
1
o
1
1
o
1
1
1
o
1
1
o
1
1
1
1
1
D/H: C2.50A
------------------------~----+
I
A15
A12
00
C
ER48
11
1-:---1--1--,1
EPROM1
1
1
1
EPROM2
c---
EPROM3
8 Kbytes
EPROM4
I
01
EPROM6
I
1 I
1r-",......,\~\~\--r'\----r\-\--r"\o ,_,_\_,_,_,_,_\_,_
I
I c:--1 1
SL1L lIm BUFFER)
I 4 Kbyt8S
1\ \ \ \ \ \ \ \ 1
1
REGISTER
o
:1
1-'-\1\\,'\}-\-'-'-I
'_,._1_"_\_1
RAM (2K)
I
& BOARD I
SELECTS
I
(SEE FIGURE 9)
FIGURE
8
MEMORY MAP (EPROMs)
--+---------+-------+---------+-,-----------------+---------------------------I sb/ra f 04-22-81 IMODEL 7908
ISTK , 07908-60002
1--+---------+------,-+---------+------------------+---------------------------I BI48-6199 I db/JSKI02-09-83 1 1.M.S. MICROPROCESSOR BOARD
1--+---------+--------+---------+-----------------------+-----------------------1
1 I
1 I 1 - - 1BY
1DATE APR 12. 1984
I
+---------+-------+---------+-----------------------+-----------------------1
"~""'" P.C., I APPR I DATE
IAPPD
ISHEET' 26 OF 34
I
,--+---------+-------+---------+-----------------------+-----------------------1
fA f I~'-;UED
I
REVISIONS
I SUPERSEDES
IDWG
'A-07908-60002-4
+--------------------------------------------------------------------------.
I
--+
+-------------------------------------------
~2
M4 M3
~l~O
I
bp /
I
HEW LET T - PAC K A R D C O.
M5
I
I
ER48 DIB: C2,50A
------~-----.-----------------+
I
1
1111001
----------__--------1
A9
1.8
AT 1.6
000
000
o
0
1
o
0
1
010
010
1
oI
CLSTlL
1 1
ETSEJ.L
I
I
o I
CLSTOL
1 HOT I
I HOT I
1
1 1 USED I SLSEHL I USED 1 SLREVL 1
1\ \ \ \ \ \ ~ \ , \ \ I
o
1-',',',',',-',',',',.',',:
1 "
I \
011
011
o
1
0
o
100
1
1
0
1
o
1
0
1
1
110
o
110
1
111
o
111
1
1
0
,
,
,
,
,
NOiI
,
,
,
,
,
I
'DECODED \" \" , - \" "
1\'\',',',',',',',\,',':
1_'...,-,-,-,_\_,-,-'_'_'_1
<--- 1
I
I
I
I
I
I
I
I
,___
I
I
I
I
I
I
6'If
byter.
SL2L
SLTL
~~9L~
REGISTER
___________
SLeL
SLltL
SL3L
.SLOL
SL6L
&
FIGURE 9
BOARD SELECT MEMORY MAP
--+---------+-------+---------+------------------+------------._--------------1 sb/RT 104-22-81 IMODEL 7908
ISTK , 01908-60002
1--+---------+-------+---------+------------------+------------.. --------------~ BI48-6199
1 db/JsxI02-09-83 1 I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+-------.. --------------I I
I I I - - IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+-------.. --------------'LTI P.C. I I APPR I DATE
IAPPD
ISHEET' 27 OF 34
f--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
I SUPERSEDES
Inwc I A-07908-60002-4
+------------------------------------------------------------------------------+
JA IISSUED
.------------------------------------------ I
I ER48 DIB: C2,50A
I_I
B E W LET T - PAC K A R D C o.
I
I -----------------------------+
~
SP; .NF
A7 A6
A5
A4
000
000
001
001
010
010
011
011
100
100
(NOT USED)
1
0
1
0
~'1
0
1
1
110
0
1
0
1
111
0
111
1
PRRBIL
CTCSLL
"CNTRL
1
SPTSTL
(NOT USED )
LEDSLL
FIGURE 10
I/O MAP
--+---------+-------+---------+------------------+-----~----------------------
IA
IISSUED
I sb/RT 104-22-81 IMODEL 7908
ISTK ,
07908-60002
1--+---------+-------+---------+------------------+---------------------------I B148-6199 I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+----------------------I I
I I
I - IBY
IDATE APR 12, 1984
+---------+-------+---------+-----------------------+----------------------,~I P.C.' 1 APPR I DATE
IAPPD
ISHEET' 28 OF 34
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
I SUPERSEDES
IDWG , A-07908-60002-4
+------------------------------------------------------------------------------+
+------------------------------------------HEW LET T - PAC K A R D C O.
I
I
hp
I
I
/
I
ADDRESS
SLOL
F380
SAL
SLlL
DOOO
BUFSL
SL2L
F200
SBL
SL3L
F340
DMASL
DHA SELECT
SL4L
F300
RWSL
READ/WRITE
SL5L
80(r/o)
IOSL
I/O SELECT (PHI)
SL6L
F3CO
TIBSL
TIB SELECT
SL7L
F240
FSSL
FORMATTER/SEPARATOR
SL8L
F2CO
SL9L
F280
)fAME
SERVO SELECT A
DHA BUFFER SELECT
SERVO SELECT B
-Not Us.d-
FLSL
C2,50A
-----------------------------+
SELECT
LINE
SYMBOL
ER48 D/H:
SELECT
SELECT
--- Not Used '.--
FAULT LATCH SELECT
---
FIGURE 11
BOARD SELECT ASSIGNMENT
--+---------+-------+---------+------------------+----------~--.---------------
IA IISSUED
1 sblRT 104-22-81 IMODEL 7908
ISTK , 07908-60002
1--+---------+-------+---------+------------------+---------------------------1 B148-6199 I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+-----------------------1
I 1
I I I - - IBY
IDATE APR 12, 1984
I
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' 1 APPR 1 DATE
IAPPD
ISHEET' 29 OF 34
I
1--+---------+-------+---------+-----------------------+-----------------------,
I
REVISIONS
ISUPERSEDES
IDWG 'A-Cl7908-60002-4 I
+------------------------------------------------------------------------------+
+------------------------------------------B E WLET T - PAC K A R D C O.
ADDRESS I
SYMBOL
80
SL5L
90
-Not Used-
I
I
/ bp
/
I
/
ER48 D/H: C2.50A
-----------------------------+
FUNCTION
I/O (PHI) SELECT
---Hot Used
--~
Disc Status Register Bit 1
AO
PRRB1L
~'eset
BO
C'JX:SLL
CTC
CO
LCNTRL
LINUS COUNTER SELECT (t'lrite Only)
DO
SPTSTL
Speed OK Test (Mot Used on 1908)
EO
FO
-Mot UsedLEDSLL
SELf.;CT
---Hot Used --LED DISPLAY SELECT (Write Only)
FIGURE 12
I/O SELI!:C'l'S
--+---------+---.----+---------+------------------+---------------------------1 sb/RT 104-22-81 IHODEL 1908
ISTK , 01908-60002
1--+---------+-------+---------+------------------+-------------------------- I BI48-6199 I db/JSKI02-09-8 3 1 I.M.S. MICROPROCESSOR BOARD
,--+---------+-------+---------+-----------------------+----------------------, 1
I I I - - IBY
IDATE APR 12, 1984
,--+---------+--------+---------+-----------------------+-----------------------1
,~LTI P.C.' 1 APPR I DATE
IAPPD
ISHEET' 30 OF 34
I
,--+---------+---.. ---+---------+-----------------------+-----------------------1
I
REVISIONS
I SUPERSEDES
IDWG ,A-01908-60002-4 1
+----------------_._------------------------------------------------------------+
IA IISSUED
+------------------------------------------B E WLET T -
PAC
ADDRESS
I
I
I
K A R D C O.
I
bp
I
I
ER48
D/B: C2,50A
-----------------------------+
DECODE PROM
(U311)
ADDR
0
1
2
3
~
5 6
7
8
9 A B C D E F
OOB
lOB
20H
30B
40B
50H
60H
70H
80H
90H
AOH
BOH
COB
DOH
EOH
FOH
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
2
...F
F
F
F
F
F
F
F
F
0
F
F
F
F
F
F
F
F
F
F
F
0
2
F
F
F
F
F
F
F
F
F
~
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
F
F
0
2
2
4
6
8
A
F
F
4 4 ~ ~ 4 4 II 4 4 ~ 4 4 4 4
6 6 6 6 6 6 6 6 6 6 6 6 6 6
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
..
"
r
F
F
0
2
F
F
F
0
2
F
F
0
2
2
F
F
F
F
r
r
F
F
F
F
F
F
F
F
F
F
5 5 5 5 5 5 5 5
1 1 7 1 3 3 3 3
0
2
0
0
2
2
0
2
0
2
0
2
0
2
0
2
4
6
A
F
F
A A
F
F
r
F
A
F
F
A A A
F
F
F
F
A
A A A
A A A A
r-' 5 5 5 5 5 5 5 5
F
1
1
7
1 3 3
3
3
FIGURE 13
ADDRESS
DECODE
PROM PATI'ERH
--+---------+-------+---------+------------------+-----_ .. _-------------------1 sb/RT 104-22-81 IHODEL 7908
ISTK , OJ908-6oo02
1--+---------+-------+------_·_-+------------------+---------------------------I BI48-6199 I db/JSKI02-Q9-83 I I.H.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+----------------------I I
I I
I - IBY
IOATE APR 12, 1984
1--+---------+-------+---------+-----------------------+------ .---------------ILTI P.C.' I APPR 1 DATE IAPPD
ISHEET' 31 OF 34
1--+---------+-------+---------+-----------------------+--- .------------------I
REVISIONS
I SuPERSEDES
IDWG , A-07908-60002-4
+----------------------------------------_._------------------------------- ----+
IA IISSUED
+--------------.----------------------------HEW LET T - PAC K A R D C O.
I
I
hp
I
I
/
I
ER48
DIB: C2,50A
-----------------------------+
BUS CONTROL PROM
(U341)
ADDR
OOB
lOB
20B
30B
40H
50H
60H
70H
80H
90H
AOH
BOH
COB
2
3
11 5 6 7 8 9 A B C D E F
7 S F
3
1
1
7
7
1
7
7
7
7
7
7
7
0
7
7
7
1
B
B
B
B
B
B
F
F
F
F
7
F
1
F
1
7 B F
1 7 7
7 7 7
7 7 7
7 7 7
9 9 D
DOH 1
EOB F
FOH F
1
F
F
1
F
F
3
3
3
3
3
3
3
7
7
7
7
B
F
B F
B F
B F
B F
B F
F
B F
7 7
1 7
7 7
7 7
B
3 1
3 7
3 7
3 1
3 7
3 7
3 1
3 1
B F
B F
B
B
F
F
3
3
3
3
F 3
F 3
F 3
B F 3
7 1 7 7 7
7 1 7 7 7
7 7 7 7 1
7 7 1 7 7
B
B
B
1
1
1
1
7
7
1
!
7
7
7
7
5
5
B F
B F
B F
B
F
F
3
3
3
3
B
B
B
F
3
F
3
B
F
3
7
7
7
7
D 1 1 1 1 5 5 5 5
5
1 1 1 1 :'I- 5 5 5 5
5
F F F F F F F F r F F
r F F F F F F F F F F
,I
I
-j
-j
7 7
7
7
7
F
F
F
F
7
7
5 5
5 5
O(
I
I
I
,
1
I
I
I
I
I
I
I
I
,
FIGURE 14
BUS CONTROL PROM PATTERN
,--+---------+--------+---------+------------------+---------------------------I ISSUED
I sblIrr 104-22-81 IHODEL 7908
,ST]{ I 07908-60002
1---+---------+-------+---------+------------------+---------------------------I B148-6199 I db/JSKI02-09-·83 I I.H.S. MICROPROCESSOR BOARD
,--+---------+--------+---------+-----------------------+----------------------I I
I I
I - IBY
IDATE APR 12~ 1984
'--+---------+-------+---------+-----------------------+-----------------------,
,....,LTI P.C.' 'APPR I DATE
IAPPD
ISHEET I 32 OF 34
,
,--+---------+--_ .. _--+---------+-----------------------+-----------------------,
I
REVISIONS
I SUPERSEDES
IDWG 'A-0790B-60002-4 ,
+------------------------------------------------------------------------------+
fA
+-------------------------------------------
I
I
I
I
bp
I
B E WLET T - PAC K A R D C O.
OGBL I OFH I IOBL
I
I
I
TeH
OND
DI/H: C2.50A
-----------------------------+
I
PIIDE'l'
ER48
1 INDXL
CY ~L
___ 1__ 1__- _ _ _ _ _ _ _ 1______
BIT
BIT 7
~
DRIVR SENSE REGISTER
(ADDRESS FODO)
CYLL
- Cylinder
Ad(~·..es.
LSB
INDXL - Latched Index Pulse
OBB
- On Track
TCH
- Track Crossinl Pulse
PKDET - Peak Detect (Position Error Signal)
IGBL
- Inner Guard Band
OFB
- Off Track
OGBL
- Outer Guard Band
FIGURE 15
DRIVE SENSE REGISTER
- CHANWEL A -
--+---------+-------+---------+------------------+---------------------------1 sb/RT 104-22-81 IMODBL 1908
ISTK , 01908 -60C:i2
t--+---------+-------+---------+------------------+------------------.. --------I B148-6199 I db/JSKI02-09-83 1 I.M.S. MICROPROCESSOR BOARD
1--+---------+-------+---------+-----------------------+----------------------I 1
I I I
IBY
IDATE APR 12. 1984
1--+---------+-------+---------+-----------------------+----------------------:LTI P.C.' I APPR I DATE
IAPPD
ISHEET' 33 OF 34
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
1SUPERSEDES
IOWG , A-07908-60002-4
+------------------------------------------------------------------------------+
IA 1ISSUED
+-----------.. ------------------------------o.
HEW LET T - PAC K A R D C
I
I
/
hp /
I
I
ER48
D/H: C2,50A
-----------------------------+
SA
1LC3H
LC2H
LCIH
LCOH
TEST
STIH
1
STOM
1__ .' ___ 1__- ____ ._ _ _ _ _ _ _ _ __
BIT 7
BIT 0
SELF-'rEST LATCHES/: rHUS COUNTJi:R. REGISTER
(ADDRESS
FODl)
STOH
- Self-Test Switch Latch 0
STlTi
- Self-Test Switch La tc: 1
SA
1
- Not Used. Always High
TE~'
- Test flag tor SA Test ET
LCOH-LC3H - Contents of Linus Counter
I
FIGURE 16
I
,
I
I
I
I
1
I
DRIVE SENSE REGISTER
- CHANNEL B -
,1--+---------+-------+---------+------------------+---------------------------IA IISSUED
I sb/RT 104-22-81 IHODEL 7908
ISTK , 07908-60002
1--+---------+-------+---------+------------------+---- -----------------------I BI48-6199 I db/JSKI02-09-83 I I.M.S. MICROPROCESSOR BOARD
f--+---------+-------+---------+---------------------- -+----------------------I 1
1 I 1
IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------ItTI P.C.' I APPR I DATE
IAPPD
ISHEET' 34 OF 34
1--+---------+-------+---------+-----------------------+--------------------·---1
I
PEVISIOHS
ISUPEi-. .;iIIDES
IDWG 'A-07908-60002-4 I
+---------------------------- .-------------------------------------------------+
1JA:.l'~:
]PAGE
U4/1CJ/fj~
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART RUHBERS
PART-NUMBER(S):
07908-68002
07908-66002
07908-60002
DATE CODE:
D-2l39
REFERENCE DESIGNATOR
cl04
ClOT
Cl12
Cl14
C13T
c144
c163
c164
C1T8
Cl88
C205
C215
C225
C235
c245
C255
c265
C305
C318
C328
C335
C345
C358
C365
C378
C385
C398
C408
C418
C425
c438
C445
C458
c460
c465
c478
C485
c498
DSl29
MP1
HP2
HP3
MP4
Q193
R130
R138
R139
COMPONENT PART
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-4350
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0180-0229
0160-5298
0160-5298
0160-5298
0160-5298
1990-0452
07908-80002
7120-6830
0403-('455
1480-0116
1853-0405
1810-0283
0757-0280
0757-0280
DESCRIPl'ION
.01UF 201
.01UF 201
.01UF 201
.01UF 201
.01UF 201
.01UF 201
.01UF 201
.01UF 201
.01UF 201
68PF 51
.01UF 201
.01UF 2~
.01UF 2~
.01UF 2~
.01UF 2~
.01UF 2~
.01UF 2~
.01UF 201
.01UF 2~
.01UF 201
.01UF 2~
.01UF 201
.01UF 2~
.01UF 2~
.OlUF 2~
.OlUF 2~
.01UF 2~
CAP .OlUF 2~
CAP .OlUF 2~
CAP .OlUF 2~
CAP .01UF 2~
CAP .OlUF ~~
CAP .01UF 2~
CAP 33UF 1~
CAP .OlUF 2~
CAP .01UF 2~
CAP .OlUF 2~
CAP .OlUF 2~
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
INDICATOR
BD-ETCHED
LABEL-INFO
EXTR-PC BD
15
PIN GRV • 062X. 25
XSTR P1fP 2114209
HETWORK-RES DIP
RES lK 1J.125
RES lK 1J .125
MATERIAL LIST COMTDtUES 01 JlEXT PAGE • • •
1
PAGE
MATERIAL
LI~~
FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART NUMBERS
PART-NUHBER(S):
07908-68002
07908-66002
07908-60002
DATE CODE :
D-2139
REFERENCE DESIGNATOR
R148
R1S4
R1S6
R165
R181
R182
R183
R190
R191
R195
Rl96
R197
R3111
R362
R411
S120
s140
TP171
TP173
U112
U131
Ul.41
Ul.42
Ul.61
U1n
u112
U181
U191
U211
U3101.
U3102
U311
U312
U321
U322
U332
U341
U342
U351
U352
U361
U3n
U372
U381
U382
\1391
U392
DESCRIPrION
COMPONENT PART
0151-0442
0151-0280
0751-0280
0751-0280
0751-0280
0751-0280
0751-0280
0751-0214
0751-0422
0151-0219
0751-0346
0751-0280
1810-0083
1810-0083
1810-0162
3101-1675
3101-1675
0360-1682
0360-1682
1818-1611
1820-1461
1820-2024
1820-1112
1820-2298
1820-2024
1820-1633
1820-0629
1820-1367
1820-2301
1820-1416
1820-0629
1816-1528
1820-2075
1820-1072
1820-1201
1820-1112
1816-1499
1820-0681
1820-1676
1820-1449
1820-1216
1820-2075
1820-1367
1820-1208
1820-1191
1820-0683
1820-1158
RES
RES
RES
HES
RES
RES
RES
RES
RES
RES
RES
RES
10K 11.125
1K 1~ .125
11{ 1~
.125
lK
1~.12~)
11 1~.125
1K 1~ .125
1K 1~ .125
1.21K 11·.125
909 11,·125
3.16K 11 . 125
10 11 . 125
lK 1~.125
NETWORK-RES DIP
NETWORK-RES DIP
HTWK-RES DP 4.7K
SW-TGL DPST KS
SW-TGL DPST liS
TERM-PIN
TERM-PIN
IC-MEMORY
IC SJf74273N
IC SJf74LS244N
IC SN74LS74N
IC-ZSOA-CPU
IC SH74LS244N
IC SJf74S24011
IC SN74s112N
IC SN74s0811
IC-ZSOA-CTC
IC SH74LS14.
IC SN74s11~r
IC MEMORY
IC SJf74LS24SN
IC SN14s139N
IC SN74LSOBN
IC SN74LS74N
MEMORY PROM
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
SN74sooli
SN74S373AN'
SN74S32N
SN74LS138N
SN74LS245N
SN74s08H
SN74LS32N
SN74s175N
SN74so4H
SN74s51M
MATERIAL LIST CONTlHUES ON N':X'f PAGE • • •
2
DATt;: 04/19/H4
MRFD041R
PAGE
MATERIAL LIST FOR PC-BOARD COMPOSED CiF MULTIPLE H-P PART NUMBERS
PART-MUMBER(S):
07908-68002
07908-66002
07908-60002
DATE CODE:
D-2139
REFERENCE DESIGNATOR
U412
U421
U422
U431
U432
U441
u442
U451
U452
u461
u462
u472
U492
Xl. 21
X129
X2101
x241
x261
X?71
X291
Y192
CC»!PONENT PART
1820-2075
1820-1240
1820-2075
1820-2102
1820-2102
1820-1208
1820-1072
1820-1"49
1820-1240
1820-1197
1820-1278
1820-1"38
1820-1"38
1200-0861
1200-0640
1200-0861
1200-0861
1200-0861
1200-0861
1200-0861
1813-0198
END OF MATERIAL LIST.
DESCRIPrION
IC SN74LS245M
IC SN74s138N
IC SN7lJLS245N
IC SH7lJLS313li
IC SH7lJLS313N
IC SH7lJLS32N
IC SH74s139N
IC SN7lJs32N
IC SH7lJS138N
IC SH74LSOOH
IC. SN7lJLS191N
IC SN74LS257AN
IC SH74LS257AN
SKT-IC 28 CONT
SKI -DSPL 14-CONT
SKT-IC 28 CONT
SKT-IC 28 CONT
SJ('J'- IC 28 CONT
SKT-IC 28 CONT
SKT- IC 28 CONT
CLOCK OSC 7.5KHZ
3
- -
·1
DlST NICE KTWEEN
MGlSTIlATlOII TAMKTS
1I.100! .OOJ
OAT
P2
~I
•• 10
•
......_ OT. . . . . . PlqtIp
!tea IIOAMI COWOMIIS TO ~ft
AUTOMATIC
8'AtIDAII08
.,.,..
"'''noN
I!J
+
+
..
..........ii; • •
X121
SPARE..
~- ••••••••
U111
•
~
.I+.......U112
ZONE 1
f-07908-I'0002- "
F-071108-80002-3
..........~
U211
ZONE 2
TARGET IIASTEII
Pail IrASTO
TYP.
2 PL.CS.
f - C:7908S0CC2-!;
3-26-82
.-.n'_
2
F
-O-"oe-~,
+-------------------------------------------
I
I ER48 D/H: C2, 50A
I hp I
~
B E W LET T - PAC K A R D C O.
I
I -----------------------------+
I
I
NOTE: This page provides a running history of changes for a multi -pa;,\l
I
drawing which cannot conveniently be re-issued completely after
I
each r.hange. When making a change, list for each page 'toll beforeI
and-after numbers (within reason; use judgement, and use
.I
"extensive" revision note if loss of past history is tolerable, or
I
retype complete page) and associate with each a symbol ,made up of
I
the change letter and a serial subscript to appear here and on
the page i~volved (there enclosed in a circle, triangle, or other
attention-getting outline).
(L204)
1M
---1--------------------------------------------------1--------1-------1-A I AS ISSUED
12-02-B1 sb/ML 1M
B
REVISED PER PC48-4345. REV B
05-14-82 jr/ML M
C I UPDATED PER PC!J8-6178
02-0~-B3 sd/JSK M
1
I DATE
REVISIONS
L'ml
I
1 INIT IF
-
-
-
.-
I
__1
I
I
I
I
1
--+---------+-------+---------+------------------+--------------_·_------------1
1 sb/ML 112-02-81 IMODEL 7908
ISTK , 07908-6901)2
I
1--+---------+-------+---------+------------------+----------------------------1
IB 148-4345 I jr/ML 105-14-82 I uPDATE AND REVISION PROCEDURE
I
1--+---------+-------+---------+-----------------------+------------------------1
I CI48-6178 I sd/JSKI02-08-83 IBY
IDATE APR 12. 1984
I
1--+---------+-------+---------+-----------------------+-----------------------1
IA I ISSUED
1 OF 6
I
1--+---------+-------+---------+-----------------------+----------------~------I
ILTI P.c.,
I
1 APPR
REVISIONS
I DATE
IAPPD
I SUPERSEDES
ISHEET ,
IOWG 'A-07908-69002-1
I
+----------------------------------------~------------------------_._-----------+
+---------------,---------------------------HEW LET T - PAC K A R D C O.
I
/ hp /
I
I
ER48
D/S: C2, 50A
I - .. ---------------------------+
UPDATING AND REVISION PROC1U)URE
07908-69002
This procedure ~ontains instructions for modification of the
microprocessor (MPU) peA, 07908-60002 to version 07908-69002.
RELATED DOCUMENTS AND PROCEDURES:
07908-68002
07908-66002
F-07908-60002-1
D-07908-60002-50
F-07908-60002-20
A-07908-9004',-1
Material List
Material. List
Assembly Drawing
Schematic
Modificatio~ Drawing
I/O Line Processing Procedure
--+---------+-------+---------+------------------+---------------------------1 sb/HL 112-02-81 IMODEL 1908
ISTK I 01908-69002
1--+---------+-------+---------+------------------+---------------------------IB 148-4345 1 jr/ML 105-14-82 I UPDATE AND REVISION PROCEDURE
1--+---------+-------+---------+-----------------------+----------------------'CI48-6178 I sd/JSKI02-08-83 ISY
IDATE APR 12, 1984
4--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
ISHEE'l"
2 OF 6
1--+---------+-------+---------+-----------------------+----------------------IA IISSUED
•
REVISIONS
I SUPERSEDES
IDWG , A-07908-69002-1
.---------------------------------------------------~--------------------------+
+------------------------------------------HEW LET T - PAC K A R D C O.
I
I ER48 D/H: C2, 50A
I hp I
I
I -----------------------------+
REVISIONS:
1~e first revision ~ich may be revised is B-2106.
assemblies are to be scrapped.
B-2106
B-2128
B-2133
All prior
(PeO 48-4053)
Removes components used in the
"Speed OK" portion of the
circuitry si~ce it is used
on the 791X and not the 7908 .
(PeO q8-4071)
Changes 6qK EPROHS to 64K ROMS.
(PeO 48-1&091)
RC»! Memory space
32K to qOK by changing
EPROHS.
(PeO q8-4188)
Changes configuration of EPRC~
~rom 2-8K and 6-4K to 5-8K EPROMS,
and changes Decode Pro.s.
Allo adds 2 jumpers to allow
1611A Logic AnalYzer tr be hooked
up to J1 connector. C:·anges
Date code to 2128.
Il1ereas~s
~rom
(PCO 48-4226)
Updates Firmware.
Code to 2133.
(fCO 48-4245)
Reltructures EPROHS from MPU
Board to Disc Module Assembly.
This allows EPROM changes to be
made without affecting the
MPU PCA.
Changes Date
--+---------+-------+---------+------------------+---------------------------I sb/ML 112-02-81 IMODEL 1908
ISTK , 07908-69002
1--+---------+-------+---------+------------------+---------------------------IB 148-4345 I jr/ML 105-14-82 I UPDATE AND REVISION PROCEDURE
,--+---------+-------+---------+-----------------------+----------------------I C148-6118 I sd/JSKI02-08-83 IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' I APPR I DATE
IAPPD
I SHEET ,
3 OF 6
,--+---------+-------+---------+-----------------------+-------_._-------------I
REVISIONS
I SUPERSEDES
IDWG , A-07908-69002-1
+------------------------------------------------------------------------------+
IA IISSUED
+------------------------------------------B E WLET T - PAC K A R D C
o.
I
I ER~B D/B: C2. 50A
I hp I
I
I -----------------------------+
REVISIONS: (con It)
Adds space tor 6th BK EPRCII
thus bring inc total memor,y
space to ~BK and change.
Decode Prom.
Deletes all socket. on the
board except ~or tho.. on
EPROMS. Changes Date Code
to 2139.
B-2139
PCO
(4B-~53B)
Changes Extractors on PCA
they have identification
80
nuaber indicating where the
PCA is to be placed in the
card cage.
PCO
(48-~657)
Changes EPROM sockets to a
more reliable type.
--+---------+-------+---------+------------------+---------------------------I sb/ML 112-02-B1 I HODEL 1908
I STK , 0190B-69002
I A I ISSUED
1--+---------+-------+---------+------------------+--------------------------~1B 14B-4345 I jr/HL 105-14-B2 1 UPDATE AHD REVISION PROCEDURE
1--+---------+-------+---------+-----------------------+----------------------'CI4B-6178 I sd/JSKI02-0B-B3 IBY
IDATE APR 12, 1984
-+---------+-------+---------+-----------------------+----------------------''T(TI P.C.' I APPH I DATE IAPPD
I SHEET ,
~ OF 6
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
I SUPERSEDES
fDWG , A-0790B-69002-1
+---------------------- -------------------------------------------------------+
+------------------------------------------- /
R E W.L E T T - PAC K A R D C O.
/ ER48 D/H: C2, 50A
/ hp /
/
/ -----------------------------+
PROCEDURE:
1.
Inspect all boards for general mechanical and cosmetic defects.
Repair all visible defects.
2.
Identify all boards ",ith
th~
following logo:
07908-69002
2139
3. Affix, near the logo, a 7120-5480 label which indicates the month
and year of final inspection.
A)
On
1)
2)
1)
4)
Board Revision:
B-2106
(to get to 2128)
See PCO 48-4188 and Hod Dra",ing 07908-60002-20,Rev.D
Remove Decode PROM 07900-89008 at Ul11
Connect 0161-27 to Ul71-6 using 30 AWG White
wire as shown on the Mod Drawing.
Install Jumper Wire (8159-0005) at E185.
--+---------+-------+---------+------------------+----------------------------
IA IISSUED
I sb/ML 112-02-81 IHODEL 7908
ISTK , 07908-69002
I B 148-4345
I jr/ML 105-14-82 1 UPDATE AND REVISION PROCEDURE
I--+~--------+-------+---------+------------------+----------------------------
1--+-------_·_+-------+---------+-----------------------+-------------------- -J CI48-6178 1 sd/JSKI02-08-83 IBY
IDATE APR 12, 1984
1--+---------+-------+---------+-----------------------+----------------------ILTI P.C.' 1 APPR I DATE
IAPPD
ISHEET ,
5 OF 6
1--+---------+-------+---------+-----------------------+----------------------I
REVISIONS
ISUPERSEDES
IDwa , A-0"7908-69002-1
+_._----------------------------------------------------------------------------+
+------------------------------------------- /
/ hp /
B E W LET T - PAC K A R D
B)
On Board Revision
C O.
B-2128
/
I
ER48
D/H: C2, 50A
/ ----------------------.-------...
(to get to 2139)
1) See PeO 48-4345 and Mod Drawing 07908-60002-20,Rev.E.
2) Replaee Deeode PROM at U311 with 07908-89018 PROM.
3) Connec'i; the fo1lowinc points together using 30 AWG
Wb;.te "ire ~.s shown on Mod Drawing~
Ul21-26
Ul21-1
Ul11-4
U111-5
U111-6
U111-7
C)
to
to
to
to
to
to
On Board Nevision
0121-27
0121-28
Ulll-12
0111-9
0111-10
0111-11
B-2139
1) See PeO 48-4657
2) If the Board has been returned because one or more
of the Sockets on the EPROMS have failed, and the
Soeket Part Number is 1200-0567, e '.1 of the sockets
must te removed and replaced ~ith Part Number
1200-0861 Sockets.
--+---------..I -------+---------+------------------+---------------------------sb/ML Il2-02-81 IMODEL 7908
ISTK , 07908-69002
1--+---------+-------+---------+------------------+-----.---------------------IB 148-4345 1 jr/ML 105-14-82 1 UPDATE AND REVISION PROCEDURE
1--+---------+-------+---------+-----------------------+-----------------------1
1 CI48-6178 I sd/JSKI02-08-83 IBY
IDATE APR 12, 1984
1
--+---------+-------+---------+-----------------------+-----------------------1
'....,.-tTl P.C.' f APPR I DATE
IAFPD
ISHEET ,
6 OF 6
1
1--+---------+---_·_--+---------+-----------------------+-----------------------1
1
REVISIONS
I SUPERSEDES
Iowa ,A-07908-69002-1 I
+------------------------------------------------------------------------------+
fA IISSUED
COO.
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PIN 07908-60241
TAPE INTERFACE BOARD (TIB) PCA-A6
Series Code F-2336
D/H:C6
HEWLET1--PACKARD
NOTE:
co.
This page prouides a running history of changes for a Multi-page
drawing which cannot conueniently be re-issued cOMpletely after
each change. When Moking a change, list for each page all beforeQnd-a~ter nUMbers (within reason; use judgeMent, and use
"extensive" reuision note if los$ of PQ~t history is tolerable, or
retype cOMplete page) and associate with ~Qch a SYMbol Made up of
the change letter and Q serial subscript to appear here and on
the page inuolved (there enclosed in a Circle, triangle, or other
attention-getting outline).
(L460)
1M
LTR:
REVISIONS
DATE
INIT IF
---l-------------------------------------------------- :--------:-------:-_fi_l_~~_1~~u~~_e~.R_~~Q_~e=Q~_1e
______ ._. _________.________ l~J::.1S.·:~!~.1._~jQ.t..RE.lt1_.
___ LI _______________________________________ - __________ L• ________ LI _______ L_
I
___ L• __________________________________________________ LI ________ LI _______ LI __
___ LI __________________________________________________ LI ________ LI _______ LI __
___ LI __________________________________________________ LI __ - _____
~
,
_______ L, __
___ LI _________________________________________ . ________ _ LI __ - _____ L, _______ L, __
___ LI __________________________________________________ LI ________ L-_____ LI __
•
___ LI __ - _______________________________________________ LI __ - _____ LI _______ I
___ LI _______________________________________ - __________ LI ________ L
_______ LI __
I
___ L, __________________________________________________ LI ____ - ___ LI _______ L, __
___ LI _______________________________________ - - _________ LI ________ LI _______ L
• __
___ LI __ - _______________________________________ - _______ LI ________ L
I _______ L
• __
___ LI __________________________________________________ L
________ L• _______ L
__
I
I
L~_
___ LI _______________________________________
- __________ LI ________ I
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'
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___ LI _______________________________________ - __________ LI ___ . _____ LI _______ L• __
___ LI __________________________________________________ LI ________ L______ LI __
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__
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• __
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I
I __
A
4A-b116
sjb/RF
03-15-83
'-'ODEL
/
P.C.NO.
APPROVED
REVIS:ONS
83~2861
(5182)
ISTK. NO.
07908-60241
INTERNAL MAINTENANCE SPECIFICATION, TAPE INT
/
LTR
7908
DATE
MAR 13 .. 1984
BY
DATE
Appt;.
SHEET NO.
SUPERSEDES
OWG.NO.
1
OF
8a
A-07908-60241-10
ER48
HEWLETT-PACKARD CO.
~a
D/H : C6
TABLE OF CONTENTS
Section
Page
Contents
·····
·········
·········
········
BLOCK DIAGRAMS and General Descriptions
· ·· ·· · ·· ·
Mlcroprocessor Interface
·
·
·
·
·
·
·
·
·
·· · ·
Clock Generation
·
·
·
·
·
·
·
·
·
·
·
State Machin\! Controller
· · · ·· ·· · ·· · ·· · · · ·
HCD-7S Tape Dr.i\'e Control · Path
· ·· · ·· · ·· ·· ·· ··
Direct He",ory Access (DMA) Interface
Data ManageMent .
TIB to Tape Data Path · · · · · · · · · · · · · · · ·
· · · · ·, ·· ·, ·· ·· ·· ·, ··
Control Lines and Hodes ·of· Operation
,
THEORY OF OPERATION
· · · · ·· ·· ··
· ·COMMands
· · Status
· · , · and
Microprocessor In terface,
Clock Generation
· · · ·· ·· ·· ·· · ·· ·· ·· ·· ·· ·· ·· ·· ··
State Hachine Controller
Read/Write Interface 'to Tape
Dri\'e
·· ·· ·· ·· ·· ·· ·· ·· ··
DMA Intt!rfllcE
.
·
·
·
·
·
Modes of Operation
··· ········ ···
Gl.OSSARY of Terfl'ts
· · · ·· ·· ·· · ·· · ·
·· ··
INDEX of Illustrations
· ··
SCOPE of this DOCuMent
····
DOCUMENTS
RELATED
·· ·
TABLE of Contents.
1
2
3
3.1
3.2
3.3
3.4
3.S
3.6
3.7
3.B
4
4.1
4.2
4.3
4.4
4.5
4.6
5
A
48-6116
P.C."O.
sjb/RF
03-15-83
f
-
-
J
-
-
APPROVED
DATE
MODEL
7908
I
I
STK. NO.
,...
3
4
4
6
6
6
,
6
7
8
10·
16
35
35
38
39
43
61
62
72
._-
,-
07908-60241
.-
INTF.RNAL MAINTENANCE SPECIFICATION> lAPE H·P
-----
MAR 13, 19;14
BY
DATE
APPO.
SHEET NO.
2
OF
88
----REVISIONS
8320-2861 (51821
·
I
,
LTR
··
··
··
·
SUPERSEDES
OWG. NO.
A-0'7908-60241-i 0
ER48
HEWLET1--PACKARD
co.
D/H:C6
(6~
INDEX OF ILLUSTRATIONS
Tables
Page
Description
16
20
3.2
TIB COMMand/Status Registers
TIB Mode Selection Bits • • • • •
4.3
4.4
State Machine Control IHts • •
• ••••
MFM PrecoMpensation PROM Contents as Percent
3.1
42
56
•
Figures
3.B
TIB Functional Block DiagraM. • • • •
•.
TIB to Tape Doto Path
•
•
.,.
••
•
Tope ForMat • . • • •
•
•••••
• •••
Key Expected (KYEXP) TiMiMg
•••
• •••
Tape Inter~Qce Register Mop •
•••••
4.4.1
4.4.2
4.4.3
4,4.4
Key Expected (KYEXP) Circuitry..
••
Read Data Pllth.> Block DiagraM.
• •••
MFM Dt!code.r and TiMing.
• •••••••
Phose Lock Loop (PLL) Lockup. • •
..,
3.1
3.7.1
3.7.2
3.7.3
A
48-611.6
~jb/RF
/
/
03-15-83
-
~ODEL
-
7908
ISTK.NO-
· .
· .
.
5
. 13
• 14
1S
·
·
17
···
57
· · · 58
· ·· ·· 59
· · · 60
07908-60241
INTERNAL MAINTENANCE SPETIF"ICATION
BY
DATE
~
TAPE
INl
MAR 13 .. 1984
t---+---------+-----.---t'-------f--------------f--------------OF
8S
SHEET~O.
3
APPO.
APPROVED
DATE
P.C.NO
LTA
~~--------~-----~---------+--------------------+--------------------OWG.NO. A-0790B-b0241-i 0
SUPERSEDES
REVISIONS
11320-2861 '5182)
ER48
HEWLETT-PACKARD CO.
1 .0
[hl)
D/H:C6
SCOPE
This dOCUMent describes the Tape Interface Board (TIB) which is used
to interface the HCD-7S tape driYe Module l OEMed by the 3M COMpany, ~.
the set of Controller boards presently used by the HP7908 and HP7912
disc d r i ve s .
2.0
RELATED DOCUMENTS
2.1
Linus Final Proto ERS (Rev. D)--10/24/80
2.2
Diagnostics
2.3.1
~or
the Tape Interface Board--1/27/81
Interface Infor"ation, HCD-7S Driye Hodule--7/29/BO
2.3.2
Description~
DC600HC High Capacity Data Cartridge, Prerecorded
for"at--4/9/S0
2.3.3
2.4
DC600HC Recorded ForMat, 16 Tracks, 67.1 Megabytes
Tape Interface Boord State Machine Flowchart, 07908-60241-11
~~--------r-------~--------~------------------r----------------------------'-
A
48-6116
sjb/RF
/
- - -
APPROVED
DATE
/
LTR
P.C.HO.
REVISIONS
13~2861
.51121
03-15-83
MODEL
790S
ISTK.NO.
07908-60241
ItJTfRNAL MAINTENANCE SPECIFICATION> TAPE IN
MAR 13, 1984
BY
DATE
APPO.
SHEETNO.
SUPERSEDES
DWG. NO. A-0790B-602~1-1
4
OF
88
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FIGURE 3.1
TIB FUNCTIONAL
BLOCK DIAGRAM
1m
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p~
HEWLETT-PACKARD CO.
3.0
D/H:C6
BLOCK DIAGRAMS and General Descriptions
The lIB can be considered a cOMposition o~ seven blocks.
EQch block
will be described brie~ly here as to its function and relationship to
the others.
A cOMprehensive explanation of the circuitry can be found
in Se c t ion 4.
3.1
Microprocessor
Interfac~
The lIB is treated os a MeMorY-Mapped peripheral to the
Microprocessor.
As such it uses ten bytes of systeM MeMory space,
seven for status to be read by the processor and three COMMand bytes
to control the state Machine and tape drive.
When TIBS-L is active,
RD-L or WR-L pulses will be gated frOM the processor to the Me"Ory
location selected by AO-H through A3-H.
The processor's data bus
(DO-H through D7-H) will then be logically connected to the lIB's
internal data bus to accept statvs frOM Addresses 0 through 6 ~or RD-L
to latch Q COMMand at Addresses 8 through 10 in response to WR-L.
3.2
Clock Generation
A 19.2-MHz hybrid crystal oscillator is at the basis of the lIB's
tiMing circuits. FrOM this Master oscillator is derived a 9.6-MHz
clock with ~ifty-percent duty cycle which beCOMes RWC during DMA
transfers.
A 4.B-MHz clock that is high 75% of the tiMe free-runs for
use as SCLK to the state Machine.
Further divisions produce a
free-running BITC-H that is gated for WCLK when writing to the tape.
BYTCK-H is the lowest frequency derived frOM the crystal tiMe-base and
runs at one-'eighth of the 600-kHz BITC-H rate or 37)500 Hz. The
tiMing derived frOM the phase-locked loop during reads frOM the tape
wlil be discussed separately in the sections on Tope Data Paths.
3.3
Stote Mochine Controller
power needed by the TIB to Manipulate data paths, bOTh to the DMA
and the tope, as well as interfacing control paths with the tape drive
and ~icroprocessor, is derived frOM Q PROM-based state Machine.
Having nearly five hundred 5tote~ this MQchine tests thirty-two
conoitions and outputs COMbinations of twenty-eight control bits,
being the equivalent of 0 helJ.'Jily vertical Micro--coded Machine whir:t.
would use a 44-bit Mlcroword.
Th~
~-------""---
__'--------r"'----------r--------.-- -.-------
1
STK_ NO-
07908-60241
-----------------------
MAINTfNANCE SPECIFICATION. TAPE IN
DATE
MAR 13, 1984
._---+--------------+-----------_._------- .
b
88
SHEET NO.
OF
+-______.______-+ ____
.________
._____ .. _
_ _ _ _ _ _....L-._ _ _.-L_ _ _ _ _ _
O.VG. NO.
A--0790H-b0241-1 0
ER48
HEWLET1--PACKARD
3.4
co.
(hi.]
D/H: C6
HCD-7S Control Path
The control path for the tape drive lnt~rfaces priMo;-ily to the
Microprocessor, with only one lnstQnce where the state Machine
interv~nes.
The COMMands sent to the drive to control Motion o~ the
tQpe~ stepping of the head and other functions (see reference 2.3.1>
are stored by the processor into the latch at Address 8.
The
processor then issues a CSTROBE via Add~ess 10, which register is also
used to acknowledge drive ~ault status with SACKN. Drive status,
whether priMary (norMal) or secondary (in case of a fault), is relayed
to the processor through Address 0 and the drive's willingness to
accept new COMMands can be Monitored using SSTROBE and CACKN located
at TI~ Address 1. Also at this address is SWO which May be used to
select between two tape drives connected to the saMe TIB.
The
powerful RESET bit which initiates the drive's Autoload sequence a
clears fault status is contained 1n cOMMond register 10.
I
The one instance in which the state Machine takes control of the drive
is when it overrides the current drive COMMand stored at address 8 and
forces a Stop Motlon COMMand using its own FCSTR in place of the
,
CSTROBE COMing frOM the processor through register 10. This May be
done to terMinate Q Seek at the target block, to interrupt a Tape
Verify at Q faulty block for inspection, or when the processor issues
a nonsensical COMMand or fails to respond predictably and in a tiMely
foshion when its attention is needed. This jaMMing of the drive
cOM"and bus is only initiated when the drive is willinq to accept new
COMMands and will not override an already faulty drive condition in
which CQse the drive Hhould brlng itself 10 an or'derly holt.
~"S
Direct MeMory Access (DMA) Int€rface
Data is passed between the RAM buffers and external DNA asseMbly under
control of the stat~ Machine.
The state M~chine generates SOS-L and
SOD-L plus the proper nUMber of dUMMY bits depending upon the
direction of the transfer, then passes the header and user data 10 or
frOM the RAM followed by SPQ~e holding dUMMies for two bytes of CRC
and flve (Fire Code used by SOMe discs) ECC bytes.
The data is either
received frOM the DMA on DOUT-H which beCOMes FIDAT-H or is output to
DIN-H after transforMation ~roM FODAT-H.
In all cases, without r€gard
to the direction of transfer, the clock RWC-L is produced by the clock
generator on the TIB ond gated by the state Machin€ using DMAEN-H even
though RWC runs at twice the frequency of the state Machine clock
SCLK.
II
t
I
A
48-6116
Isjb/RF
03-1S-83
... ODEL
7908
ISTk NO.
INTERNAL MAJrHENANCE SPECIFICATION,, -TAPE
/
I---+------.------+------~t__------------
/
LTR
P.C.NO.
APPROVED
DATE
MAR
BY
DATE
APPD.
SHEET~D.
SUPERSEDES
OWG. NO.
1 3, 1 9B 4
7
.320-2861 15182)
.
-~;.t,
i
_;_--------.------ --- -
1--...&.-_ _ _ _-'--_ _ _1 - -_ _ _ _1---_ _ _ _ _ _ _ _ _ _-+_ _ _ _ _
REVISIONS
I
07908-60241
~
-----1
OF
88
- - - -----
--1t
A-O"7908-60241-1 0 ,
HEWLETT-PACKARD CO.
Data ManageMen~, including Data
Correction
3.6
Bu~fers
(hP.JER48
D/H:C6
and Error Detection and
As data is written frOM the DMA to the TI8, i~ is converted froM
serial to byte-parallel forM via a pair o~ id~ntical universal shift
registers operating in the right shift Mode. Dep~nding upon the fraMe
(,ector) counter the output of one of these regl~rers will be loaded
into its corresponding RAM at the end o~ each byte) the ~irst two
fraMes go into RAMO and the second two are loaded into RAMi. Each RAM
is two kilobytes in size, allowing for the storage of two fraMes plus
the header which had been assigned by the Microprocessor for the
particular fraMe with a given target block address on the tape; the
73~ of the RAM locations that reMain unused results in an overall
cost-effective, efficient and reliable design (see Section 4.6 for an
explanation of how this can be so).
Based upon Mode control lines and proMpting frOM the state Machine,
the next logical step is to write this data to the tape. This is done
by running the address (byte) A8-counter frOM on initial address
SMaller than that of the location of the first header byte in RAM and
decoding these extra unused addresses to output the all-zero sync
field followed by a single one-bit inserted at the appropriate count
by SYNC1. The state Machine then ~etches the header and user data·
frOM the proper RAM and routes it through its corresponding universal
shift register in a left shift fashion appending two CRC bytes to the
end of each fraMe using CWE-L. The ~our data fraMes are written in
this Manner, two ~roM each of RAMO and RAM1, then the two ECC fraMes
are generated and added to the block. The headers for the ECC fraMes,
nUMbered 5 and 6, are produced by using HINST-H to add four
arithMetically to the headers frOM the ~irst ~wo data fraMes.
The
data for the ECC fraMes is generated by retrieving data siMultaneously
frOM both RAMs and exclusive-DRing the two alternate ~raMes together
bit-by-bit. CRe is then appended to the concocted fraMes as it is
shipped off to be encoded into MFH before being written to the tope.
A
48-6116
sjb/RF
03-15-83
MODEL
/
P.C.NO.
APPROVED
RFV'SfONS
~20-2861
(51821
STK. NO.
1
---------------,-
07908-60241
INTERNAL MAINTENANCE SPECIFICATION, TAPE IN
/
....., lTA
7908
DATE
MAR 13, 1984
BY
DATE
APPO.
SHEET NO.
SUPERSEDES
OWG.NO.
8
OF
88
A-07908-60241-10
ER48
HEWLET1--PACKARD
co.
[hJl
D/H: C6
On the return trip, during a read ~roM the tape, the read circuitry
will recover RClK ~roM the data,~treaM at RDDATB and supply it, alon,
with decoded data, to the buffer circuit block.
loading of the
inforMation to the RAMs is accoMplished in the 5aMe Manner as during a
DMA transfer except that all trans~ers between the TIB and tape use a
left shift Mode while the DHA interfaces via right shi~ts. As the
data is shifted into the S~RDES, the CRC Checker Monitors it, header
included, and at the end of each ~ra"e a ~lag is strobed into the
CRC-flag register at address S, being set if an error was detected or
cleared if not. Each of the four user data fraMes is stored into the
SaMe RAM locations that it would have passed through during a write.
When the ECC fraMes are reached, SOMe decisions Must be Made as to
their utility. If, ~or instance, the first dat~
rOMe had resulted in
an erroneous CRe being calculated, then the firs' ECC fraMe, nUMber S,
will be needed in order to exclusive-OR it bit-by-bit with fraMe 3 to
reproduce fraMe 1. Therefore, as fraMe S is read frOM the tape and
decoded, it will be overlaid in RAM onto the bad data stored for fraMe
1~ unless fraMe 3 was also known to be bad 1n which case the errors
ore uncorrectable and fraMe 5 will be ignored.
Si~ilarly, i~ fraMe 3
hod been detected as bad, but fraMe 1 was good, then fraMe 5 would be
written over the bad nUMber 3 to be excluslve-ORed later with fraMe 1
to perforM the recovery. Also, siMilarly, when fraMe 6 1s read, 1t
will be saved as necessary to correct either o~ fraMes 2 or 4,
providing the alternate has been detected as good. Of course, if a
pair of data fraMes was both good, that is 1 and 3, or 2 and 4, then
there is no need to save the contents of the ECC fraMes.
~~----------r-------'-----------~------------------~------------------------------~
A
48-6116
f-)jb/RF
03-15-83
~ODEL
7908
ISTK.NO.
07908-60241
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
/
~~----------+-------~----------~------------------------~-----------------------.-I
D'.TE
MAR 1~, 1984
BY
LTR
P.C.NO.
APPROVED
REVISIONS
832().28451 15182)
DATE
APPD.
SHEET NO.
SUPERSEDES
OWG.NO.
9
OF
BS
A-079C8-60241-1 0
ER48
HEWLETT-PACKARD CO.
D/H:C6
l6p']
Now that the d~ta has been retrieved froM the tape and set up as
necessary for recovery frrM errors, the final step in the round trip
would be to perforM a Read to the DHA. During this operation, the
saMe CRC flags that were generated and stored in register 5 above are
ag~intested by the state M~chine in order to deterMine the origin of
each fra"e, and hence the activity necessary to restore usable data,
If, for a data fraMe poir, neither or both of the CRe flags had been
set during the reading frOM the tape, then the data will be taken as
is frOM the RAM and output to the DHA, as the data is either good or
uncorrectable. On the other hand, if one and only one CRe flag has
~een set in a fraMe pair, then the ECC fraMe would have been overlaid
upon the flagged erroneous fraMe and to restore the data, this ECC
field Must be exclusive-ORed bit-by-bit with its Mated fraMe in the
pair as it is sent to the DHA interface. This Method, of a two-part
correction, the first being perforMed during the read frOM the tape
and the second during the Dr.. transfer, is used within the two
triplets) fraMes 1, 3 and 5, and fraMes 2, 4 and 6, to recover frOM
bursts of errors as lo~g as two ~ra"es in length on-the-fly, without
the necessity of a rewind and retry.
3.7
TIB to Tape Data Path
The basic block diagraM of the read and write data paths frOM the TIEe
buffers to the HCD-7S drive Module is shown in Figure 3.7.1. A br ief
description of the functional blocks and signals is presented in
Sections 3.7.1 through 3.7.4. An exhaustive COMponent level
description is deferred until Section 4.4.
~~------------------~--------~--------------------~-----------------------------.A 48-b116 sjb/f
:-:
}a..--WR-~rw.T"B----t ~--~ h'RDATA
encoded)
--,.
Encoder
•
----------------,~~I ~BITC-H
I
WEN-.H)~-------i-HFII
RDATA
.~ RCLK-H
__
WDATA>
GAPX-L
,(m!m
,
buffer
, ... '
I
, ,
FIGURE 3.7.l
Simplified Block Diagram of
"TIB to Tape- Data Pat.;
,
=A=-=07=9=O=8=-6=O=2=41=-=l=O=====:s=~=e£T==1=3==O=F=8=8==1 ~~ ~!~.z:~~
:======:=OA=TE===1=-2=8=-=83===:=OW=N=g=·.
b.}
a.J
Forward Key (10 bytes)
j
Interkey Gap (2 bytes)
Reverse Key (10 bytes)
Front Gap
....
Frame 1 (270 bytes data)
Interframe Gap (2 bytes)
-i'""
~
rrame 2 (270 bytes data)
...,
C)
Frame 3 (270 bytes data)
t.J
'0
e
0
0
--
Frame 4 (270 bytes data)
0\
Q
....
l
Frame 5 (270 bytes ECC)
Frame 6 (270 bytes BCe)
Rear Gap
Fozvard Key
t
Reverse Key
FIGURE 3.7.2
GAPX-L SIGNAL SHOWING rAPE FORMAT FOR
a.} BLANK AND b.) RECORDED TAPES
DATE 1-28-83
DWG.
NO.
A-07908-60241 -10
SwEET 14
OF
88
r/iD'l
HEWLETT
-.:~ PACKARD
b.)
a.)
XYEXP-B
KYEXP-H
GAPX-L
Back Gap
Forward lCey
Reverse lCey
Front Gap
Frame 1
Frame 2
Frame 3
Frame
4
Fraz..e S
Frame 6
Rear Gap
Forward Key
Reverse Key
Front Gap
FIGURE 3.7.3
KYEXP-H Signal for a.)
forward and b.) reverse
Tape Motion. Note:
t:hat
the frames are numbered
for an even number (forward
motion) track.
OATE
1-2S-83
OWG.
NO
A-0790S-60241-10
SJoIEET 15 OF 88
rh~
~~
HEWLETT
PACKARO
ER4B
HEWLETT-PACKARD CO.
3.B
(h~
D/H:C6
Control Lines and Modes of Operation
The TIB recognizes three bytes of COMMand frOM, and offers seven bytes
of status to, the Microprocessor.
The ten co~trol registers used are
in a sixteen-byte subspace of the 64-byte regl~;ter space covered by
the TI8 Select line, TIBS-L.
Table 3.1 shows the allocation of This
register space as an offset frOM the base address of !F3tOj figure 3.B
giues Q bit-by-bit description.
Table 3.1
TIB COMMand/Status Registers
ADDR
RD-L WR-L
---- ---- ---0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
X
Dllta Bus
--------
1
1
1
1
1
1
1
X
Drive Status STOO-ST07
Tape Interface Status
Key NUMber, Hore-Significant-Byte
Key NUMber, Lesser-Significant-Byte
Task COMpletion Code
CRC Flags
PC Revision/Rework NUMber
unused
8
9
1
0
0
10
1
0
Drive COMMand CHDOO-CHD07
Tape Interface Control
DrJve Interface Control
11-1S
X
X
unused
XXXX
0
0
illeglll
1
I
~~----------,~----------------~-------------------,--------------.------------------,-
A
LTR
48-6116
P.C.HO.
sjb/RF
03-15-83
I
I
- - -
BY
DATE
APPROVED
DATE
APPO.
SHEET NO.
SUPERSEDES
OWG.NO.
REVIStONS
e32C).2861 15182)
MODEL
7908
STK. NO.
07908-60241
INTERNAL MAINTENANCE SPECIFICATION, TAPE IN'
MAR
16
1:~,
1984
OF
8S
A-07908-60241-10
D/H: C6
co.
HEWLET1--PACKARD
Drive Status Regis~er
Addr.ss 0
D6
D7
DS
DJ
D4
DO
D1
D2
:-------:-------:-------:-------:-------:-------:-------:-------:
:
:
:
:
:
:
:
:
:
:ST07-H :ST06-H :STOS-H :ST04-H :ST03-H :ST02-H :ST01-H :STOO-H :
.
.
.
:-------:-------:-------:-------:-------:-- ---_._-----_._-----_.
Tope
Status
Address 1
Inter~ace
DO
D1
D7
.._------.------_._-----_._------1-------.------_·_------.-------.
. D6 . DS . D4 . D3 .
.
.
.
:Int: Unit
:Sector :UnloQd :Restore: Save
:CoMMand:Status:
D2
: errupt: Select: Toggle: Switch: Swltch:Switch :Acknow-: Strobe:
: Flag
: Switch: (STOG): (SW3) : (SW2) : (SW1):
ledge:SSTROBE:
:-------:-------:-------:-------:-------:-------:-------:-------:
Block NUMber, upper byte
Address 2
D6
D7
DS
D3
D4
DO
D1
D2
:-------:-------:-------:-------:-------:-------:-------:-------:
:New Key:
: 4096
2048
1024
512
256
o
: flag
:
: (NEWKY) ~
: (------------Key
: (Msb)
N~Mber---------------)
:-------:-------:-------:-------:-------:-------:--------:-------:
Block NUMber, lower byte
Address 3
DS
D6
D7
D4
D3
DO
D1
D2
:-------:-------:-------:-------:-------:-------:--------:-------:
128
64
32
16
8
4
2
1:
(--------------------------Key NuMber-------------------------) :
(lsb) :
:-------:-------:-------:-------:-------:-------:--------:-------:
Figure 3.8-1
A
LTR
48-6116
P.C.NO.
sjb/RF
03-15-83
I
-
I
-
APPROVED
REVISIONS
8320-2861 (5182)
Tope Interface Status Register Mop, lower
-
DATE
~OOEL
7908
hal~
-
ISTK. NO.
07908-60241
INTERNAL MAINTENANCE SPECIF1CATION, TAPE INl
MAR 13, 1984
BY
DATE
APPD.
SHEET NO.
SUPERSEDES
DWG. NO.
17
OF
88
A-07908-60241-10
lhP.1
HEWLETT-PACKARD CO.
Task
D7
D6
R48
D/H:C6
Code Register
Address 4
Co~pletion
D3
D4
DS
DO
D1
D2
:-------:-------:-------:-------:-------:-------:-------:-------:
:Suc:Blonk
: Zero
:Loss
:Drive
:Self:
o~:Verify
:cessful: Data
: Count : Hand- : Error : Fault : Test
: unused :
:CoMpl1n: FraMes:
: Shake:
:
:Results:
:(SUCCS):(BLANK):(ZCNT) :(LOHS) :(VERR) :(ST07) :(STEST):
:-------:-------:-------:-------:-------:-------:-------:-------:
CRe Flag Register
Address S
D7
D6
D3
D4
DS
D1
D2
DO
:-------:-------:-------:-------:-------:-------:-------:--------:
:CRC of :Good
:CRC of :CRC of :CRC of :CRC of :CRC o¥ :CRC
:
o~
:
Key
:Key Not:
ECC
: ECC
: Data : Data
: DQta
: Data
:
:
: Found :FraMe 2:FraMe 1:FroMe 4:Fra"e J:FrQ~a 2:FraMe 1:
: (CRCI() :(CRCNF):(CRCS) :(CRC4) :(CRC3) :(CRC2) :(CRC1) :(CRCO) :
:--~----:-------:-------:-------:-------:-------:-------:--------:
Tape Interface Reyision Register
Address 6
Db
D7
DS
D1
D2
D3
D4
DO
:-------:-------:-------:-------:-------:-------:-------:-------:
: <-----------) :
: (-----Artwork
:
R~visions-----):
(lsb):
Rework
Revisions
:unused
:(GAPX
:
:
:
-L):
:-------:-------:-------:--------:-------:-------:-------:-------:
Addre.ss 7
D7
DS
D6
D3
D4
DO
D1
D2
._-----_.------_.------_._-----_.------_._-----_._-----_._-----_.
•
•
•
•
f
•
•
•
•
: (--------------------------unused---------------------------)
:
:-------:-------:-------:-------:-------:-------:-------:-------:
Figure 3.8-2
A
48-6116
LTR
P.C.NO.
sjb/RF
Tape Interface Status
03-15-83
MODEL
-
7908
~egister Hap, upp~_r__h~_l_f_________
I
STK. NO.
~
07908-60241
/
-
/
- -
BY
DATE
APPROVED
DATE
APPO.
SHEET NO.
SUPERSEDES
OWG. NO.
INTERNAL MAINTENANCE SPECIFICATION, TAPE IN'
MAR
13, 1984
18
OF
as
~1IIiIIIiI'"
REVISIONS
~J20-286'
(5'821
I
A-0790B-60241-10
ER48
D/H:C6
~ll
HEWLET1--PACKARD CO.
Drive COMMond Register
Address 8
D7
D6
DS
,
_______ I
_______ t
_______ I
•
t
•
•
D4
_______
D3
I
_______ I
•
•
D2
_______
DO
D1
,
_ _ _ _ _- _ _ 1
_______ 1
•
•
•
:CMD07-H:CMD06-H:CHDOS-H:CMD04-H:CMD03-H:CMD02-H:CMD01-H:CMDOO-H:
·
,
_______
.
I
_______
.
.·
'"
.
t _______ ,
.
_______ • _______ I
_______
.
,
.
________ •
_______
.
t
Tope Interface Mode Register
Address 9
D7
DS
D6
D4
D3
D2
D1
DO
·:RUN-H/ .:Self'- .. DHA .:Block .:Drive .:
.
.
Mode Se lect
:Restart: Test :Connect: Enable: Select: (-------------------)
.
.
(see no te)
Select:
· -L:: (STEST):
·
(DMAC): (BLKEN): (SELO) : M2
HO
:
tU
·
.
.
.
.
.
.
.
,
t
_______ t
_______ • _______ t
_______
,
_______ • _______ • _______ • _______ ,
Note:
_______ I
_______ t
_______
I
_ _ _ _ _• _ _ I
_ _ _• _ _ _ _ • _ _ _ _ _ _ _ I
.
_______ t
_______
·
··
·.
t
See Table 3.2 ~or f'unction of' Mode Select bits
with respect to STEST
Drive Interface/Front Panel Register
Address 10
D7
D6
DS
D4
D3
D2
D1
DO
·._-----_._------.------_._-----_._-----_._------_._------._-----_.
.
.
.
.
.
.
.
.
:
:
:
: Bus~
:Protect:
:StOtU5 :CoM~and:
:unused :unused :unused: LaMp: LaMp
: RESET :Acknow.: Strobe:
:
:
:
:(l.AMP2):(LAMP1):
: (SACKN):CSTROBE:
:-------:-------:-------:-------:-------:-------:-------:-------:
Figure 3.B-3
A
LTA
48-6116
P.c.NO.
~~------
___
sjb/RF
03~1S-B3
/
-
-
/
-
-
APPROVED
DATE
-"ODEL
7908
ISTK.NO-
07908-60241
INTERNAL MAINTENANCE SPECIFICATION) TAPE INl
MAR 13
BY
DATE
APPD.
SHEET NO.
19
t
1984
OF
88
--L-------~--------_+------------------~----_+--------.----_--------_---
REVISIONS
e320-286f (5'82)
Tape Interface COMMand Register Map
SUPERSEDES
DWG.NO.
A--0790B-b0241-1 0
•
ER48
D/H:Cb
l6p']
HEWLETT-PACKARD CO.
Table 3.2
TIB Mode Selection Bits
Operation when:
STEST
H2 Hi 110
=0
STEST
=1
-------0
0
not supported
Loop on Write
0
0
1
Write TIB to Tape
Write Bad eRC on FraMes 2 & 5
0
1
0
Read Tape to TIB
rl0t
0
1
1
Read TIB to DHA
Loop on Read of TIB to DMA
1
0
0
Verif'y N Blocks
not supported
1
0
1
Seek N Blocks
not supported
1
1
0
illegal
Buf'fer FlII of' TIB RAM for DMA
1
1
1
illegal
illegal
Note:
'~.......,
LTR
48-6116
P.C.HO.
o~
supported
112, M1, MO and STEST are located in the register Qt
address 9.
A
DMA to TIB
0
sjb/RF
See Figure 3.8-3.
(13-15-83
/
- -
/
-
APPROVED
REVISIONS
-
DATE
MODEL
7908
JSTK.NO.
07908-60241
INTERNAL MAINTENANCE SPECIFICATION, TAPE IN·
I1AR 13,,, 1984
BY
DATE
APPD.
SHEET NO.
SUPERSEDES
DWG. NO.
20
OF
88
A-07908-b0241-1 0
~------------------------------~----------------------~-------------------------
8332861 (5182)
ER 48
(hp]"
HEWLET1--PACKARD CO.
J)/H : C6
Status Registers
3.8.1
Address 0, Drive Status: Data Bus will pass Status STOn-ST07
directly frOM drive in real-tiMe buffered by Q 74LS244, an
octal three-state driver.
Address 1, Tope Interface Status:
DO
= Status
D1
= COMMand
STROBE directly fro" Drive
ACKNowlege directly frOM Drive
D2 = Save, Disc to Tape,
DJ
D4
DS
= Restore~ Tape
= Unload, front
= Sector Toggle
~ront
panel switch
to Disc, front panel switch
panel switch
bit assists Microprocessor with control of
DMA by signalling transfer of each new sector to or fro"
the DMA.
•
D6 = Unit Select switch, signals processor to exchange unit
nUMbers between tape and systeM disc. This switch is not
presently loaded.
D7 = Interrupt FLAG is set by lIB upon COMpletion of
whether successfully or by ~ault.
Q
task,
~~----------~------,-----------r-------------------~----------------------.-------~
A
48-6116
sjb/RF
/
- _.
- -
APPROVED
DATE
/
LTR
P.C.NO.
fUVIS'ONS
9321>2861 (5182)
03-15-83
~C'DEL
7908
ISTK.NO. 07908-6024:L
INTERNAL MAJNTENANCE SPECIFICATION, TAPE INl
MAR 13., 1984
BY
DATE
APPD.
SHEET NO.
SUPERSEDES
DWG. NO.
21
OF
88
A- 07908 -60241-1 0
ER48
(h~
HEWLETT-PACKARD CO.
D/H:C6
Addre5s 2) Flock NUMber, upper byte:
DO-D4
= Fiye
DS
= unused
Db
=
D7
= NEW
l
Most-signi~icQnt
bits
o~
last Key NUMber reod
should be 0
8AD
~eY, a copy o~ bit Dh
address 5 below.
~rOM
the CRC Flag register at
KeY is set when the Key NUMber is loaded into its
register ~ro" the tope and cleared autoMatically when the
least significant byte of that register (address
3) is
read. Failure of the Microprocessor to read the Key
NUMber register , walt out the appropriate nUMber of clock
periods to satisfy DMA and ECC requireMents, issue
Start-ol-Data and then transfer a sector of data based upon a
bit clock rate of 9.6-HHz.
Th~s procedure will be repeated
for Q total of four sectors, accepting 1k-byte of user or disc
data with headers in accc~d with the tope forMat and allowing
space for, but ignoring the contents of, CRe and ECC bytes in
keeping with the DHA/ECC forMats.
This transfer will end
after an extra Sector TOGgle has signalled the end of transfer
to the Microprocessor. The state Machine will then loop with
Q SUCCeSsful COMpletion code waiting for acknowledgMent of
task COMpletion 1n response to its Interrupt FLoG. This Mod~
will ordinarily be used only for test purposes, a5 Mode 1
incorporates this procedure followed by an autoMotic transfer
to tape.
,
I
r
I
)
I
I
I
t---r------r---r----------,.------------il
A 48-6116
sjb/RF 03-15-83
7908
'-'ODEL
ISTK.NO.
I
07908-60241
t---+-----.-t-----+-------t------------L.---------------.-------1
/
- INTERNAL MAINTENANCE SPECIFICATION, TAPE IN~
---_.- ...,
-
i
I
DATE
MAR 13, 1984
BV
t - - + - - - - - - - - I r - - - - + - - - - - - - + - - - - - - - - L . I . . - - - - - - f - - - - - - - - - - ----- - --.- ----.,
LTR
P.C.NO.
APPROVED
DATE
APPO.
SHEET NO.
;.'7
Of
88
.
~-----"----.L.--.--+__--__+__----_---.-- ___ ~
DWG. NO. A-0790S-60241-1 0 J
REVISIONS
SUPERSEDES
e320 2861 151821
ER48
HEWLETT-PACKARD CO.
3, .. 8.3.2
~P.l
D/H:C6
Mode 1, Write DMA to Tape
As Mentioned obove, this Mode is a co~bination of two More
specific functions.
It consists of Q Write froM TIB to Tape
with an eMbedded Write frOM DMA to TIS (Mode 0) autoM~tically
included.
After 'the tape head has been 10cQted o~, the desired trQck and
the driYe has achiev~d the requested operating speed in the
direction appropriate to that track, this ~ode beCOMes
Meaningful. First, the state Machine reads a key and sets the
NEW KeY flag, provided th~t the preYious key had been read in
order to Qvoid a Loss Of HandShake error.
Then a tiMer,
contained .in Q CTC chip on the processor board, will be
triggered to tiMe out a long enough delay so that the erase
head will SQfely clear the key Marks which are a part of the
preforMatted tape.
While the tiMer is running, the state
Mac.hine will watch ~or the processor to set BLocK ENable,
signalling that the current block is the intended target and
that the DMA has been connected to the TIB in readiness for Q
datQ transfer. When the DMA transfer Is COMplete, the state
Machine will check the eTC tiMer to ~ake certain that it has
not tiMed out as this would result in an excessively long gap
on the tope.
If the DMA COMpleted too late and the tiMer has
run o~t, Q Loss Of HandShake flog will be set; but i f the DMA
COMpleted in tiMe, the tiM~r will be allowed to tiMeout and
then be retriggered when the erase current is establIshed to
begin Q write to the tape.
~-r----------r-------~----------r-------------------~------------------------------'48-b116 sjb/RF 03-1 S-83 MODEL 7908
A
STK. NO. 07908-60241
I
INTERNAL MAINTENANCE SPfCIFICATION, TAPE INl
/
/
'.,.... LTA
~-L
p.e.fllo.
APPROVED
BY
DATE
APPD.
____________L - .________~_______________~___________
DATE
MAR 13, 1984
SHEET NO.
28
OF
BB
--------------------1-----------------------.--------------1
L-____- -__________________________~___________________________________________________
DWG.NO. A-07908-60241-10
REVISIONS
932C). 286' C5182)
SUPERSEDES
D/H:C6
HEWLET1·-PACKARD
co.
At the end of this second tiMeout, writing o~ data will
begin.
The four s~ctors of data acquired froM the DMA will be
placed in the first four f,aMes along with the appropriate
header inforMation) which hod been generated by the
Microprocessor and passed through the DMA) and th~ CRe bytes
which will be produced in the TIB.
Two additional fraMes will
be generated in the TIB by creating headers froM those used
for the first two fraMes) cOMbining dota via the exclusive-OR
function froM alternate datQ fraMes) and append~ng proper
CRCs.
The state MQchine then requests a third tiMeout at the
end o~ which the drive will have its write current switch~d
off) having erased any stray transitions or overwritten data.
The BLocK ENable signal is nulled by the TIB upon recognition
o~ each new block (key Mark) and Must be set again by the
processor after verifying the key nUMber. The Microprocessor
will then be sent on Interrupt FLoG along with a SUCCeSsful
cOMplet~on code, asking it to issue another COMMand.
3.8.3.3
Mode 2, Read frOM Tope to TIB
Like the Write Mode above) this cOMMQnd is sent to the TIB by
the "icroprocessor while it hold5 ReSTaRT active and tells the
drive to go to the desired speed Qnd direction.
When RUN is
asserted, the TIB will wait until the requested speed has been
achieved and begin to look for key nUMbers. When Q key nUMber
has been recognized) it will be stored and the NEW KeY flog
set.
If the previous key hod not been reod prior to this, the
lIB will flog a Loss Of HQndShake error and force the tap~
drive to Q stop.
In the case of an unrecognizable key nUMber
due to a CRe error on the key Mark, the state Mochine will
atteMpt to recover the key nUMber frOM the heQ~er of the four
data ~raMes, which are protected by ECC; if all three fraMes
are bad then the data is uncorrectable so that the key nUMber
is unn~cessary. In a Multi-block r~od It is necessary only to
extract the key nUMber frOM the preforMotted key Mark of the
first blnck for orientation. On successive blocks the state
Machine will tiMe past any MiSSing key Marks and recover bloc~
nUMbers frOM the data fraMes.
This procedure is yalid only
for read operations and does not apply To writing or verifying
of tapes.
~~----------~------~-----------r--------------------T-----------.-------------.--------~
(~
48-6116
isjb/RF
I
I
LTA
P.C.NO.
APPROVED
REVISIONS
S3n2861.51821
03-15-83
-
"'OOEL
-
-
DATE
7908
ISTK. NO.
0'7908-60241
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
MAR 13, 1984
BY
DATE
APPO.
SHEET ~"'O.
SUPERSEDES
OWG.NO.
29
OF
8S
A-0790B-b0241-10
ER48
HEWLETT-PACKARD CO.
[,s~
D/H:C6
Data ~or the current block will be read and buff~red in RAM on
the TIB. The first four fraMes of data are read as written,
headers being stored and CRC/s being checked.
A bit to
signify a zero (good) or non-zero (bad) CRe will be placed 1n
the CRC register, Status address 5~ for each fraMe.
If any of
the first four data fraMes is in error. the ECC fraMe that
corresponds to it will be stored in place of the bad data in
the RAM os the first of two phases of the error correctio
process. That is, if fraM~ 1 or 3 results in Q non-zero CRe
check, then fra,e S will be stored in its position, and a
siMilar situation for data fraMes 2 and 4 and ECC fraMe 6.
If, however, both of a dato fraMe pair are found to be in
error, then the error is known to be uncorrectable and the
overlay will not toke place, as is olso the case when both
data fraMes are thought to be good.
[The ECC fraMes in these
instances will be d~ubly buffered and carefully stored oway 1n
one of a pair of bit buckets to be recalled as necessary for
correction of future tapes.]
After dota has been read and buffered in RAM, BLocK ENable
will be checked to see if the processor has decided that this
block is of yr.llue.
If the enable is not set} then the data
will be ignored and Q search will begin for the next key Mark;
this constitutes provision for a fine seek under close
supervislon by the Microprocessor.
On the other hand, if the
block was enabled, but contolned no previously written dota,
it will be assuMed that a Mistake has been Made with regard to
the hostls directory, a BLANK COMpletion code will be issued
and the drive brought to a stop.
With a previously written
tape, .if th~ blOCk was enahled J the TIF would signal Q
SUCCeSs~ul cUMpletion and ~ssue on Interrupt FLaG. then await
further instructions, preSUMably Q DMA transfer.
As in the
Wrlte Mode above, ~he BLocK ENable is ~leQred after each new
key nUMber is read and Must again be set by the processor for
each block.
A
LTR
48-6116
P.C.NO.
'sjb/PF
03-15-83
/
-
-
/
-
-
APPROVED
DATE
MOOEL
7908
INTERNAL
I
-------.- -1'
MAR 1:5; 1984
BY
DATE
APPD.
SHEET NO.
SUPERSEDES
CWO. NO.
::s 0
\)F
8S
.-.......IL------.. . - - - - - ' - - - - - - - - i r - - - - - - - - - - - - - - - l t - - - - - - - - - - - - -----4
AEVISIONS
'320-2861 15182)
A-07908-b0241-1 0
j
ER48
HEWLET1--PACKARD
3.8.3.4
Moci~
3
1
co.
(hPJ
D/H:C6
Read froM TIB into DMA
As was the case ~or Hode 0, the TIB will aSSUMe that the DMA
has been set up to expect four sectors of dota and connected
to the TIB. This transfer will norMally be executed during
the final gop, between the lost fraMe of a block and the
following key "ark, but this tiMing is not necessary.
Start-Of-Sector and Sector TOGgle signals are issued identical
to those used in the Write Mode. Data transfer begins l
following a Start-Of-Data pulse and appropriate dUM~Y bits,
header first 01 a rate of 9.6-Mbps.
If a correctable COMbination of CRC ~lags are set, then the
second phase of the autoMatic. error correction process will
take place. To wit, if froHe 1 was thought to be in error and
froMe 3 was good, then upon reading ~raMe 5 ~ro" the tape it
would have overlayed fraMe 1. During the DMA transfer the
apparent contents of fraMe 1, which is actually ECC
inforMation frOM fraMe 51 will be exclusive-ORed with fraMe 3
to recreate a good data fraMe 1. Other data fraMes May be
recreated accordingly as the data is passed to the DMA RAM.
•
It should be noted that this Mode in conjunction with Mode 0
can be used to iMpleMent Q loopback of data through RAM on th~
TIB to self-test 0 significant portion of the operation of the
lIB. During a DMA Write (Mode 0), the CRC flags are cleared
so that when this feature is used there will be no
interference frOM CRe flags reMaining frOM a recent reading of
the tape. Such CRG bits would lnvok~ tho autoMatic error
correction, generating perhQPs pr~dictable but definitely
unexpected results.
I
t-~-----""'----~-----""'------------r-------.--
A
48-6116
sjb/RF
/
03-15-83
-
-
~ODEL 7908
STK. NO.
079t1e-b0241
--------t
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
~~-------'----~----.'--~----------~-------------------------r-------------.---------.---/
DATE
MAR 13} 1984
BY
-
LTA
P.C.NO.
REVISIONS
832()'286 i 151'821
-
--~--------~~--.----------------------~---------------------.---OF
88
SHEET NO. 31
APPROVEO
APPD.
DATE
SUPERSEDES
DWG.NO.
A·-07908-60241-10
,
t
i
ER48
HEWLETT-PACKARD CO.
3.8.3.5
Mode 4,
Veri~y
[h~
D/H:C6
N Blocks
This "ode is siMilar to a Read frOM Tape to TIB, Mode 2,
above. Before releasing the ReSTaRT-L line to begin the
~peration, the Microprocessor "ust set the block counter in
the CTC chip to the nUMber of blocks to be veri~ied.
Since
the s1ate MQchine on the TIB is not capable of selecting head
positions and tape speeds, this block counter is liMited to
4096, the nUMber of blocks which can be contained on a single
track. This block count is stored in part in one of the eighT
bit channels of the CTC chip with the necessary reMaining four
bits contained in another discrete counter register) all on
the f'1PU board.
When the TIB is released to RUN, it begins by looking for key
nu"bers. When one is found, it is reported to the
Microprocessor a~ always. The TIB reads the data and checks
CRCs as norMal until the entire block has been read. The
BLocK ENable line is then cheeked.
If the block was not
enabled, the results are ignored and a new key nUMber is
sought, as for a slow seek. The Microprocessor Must Monitor
this slow seek by reading key nUMbers in order to ovoid Loss
Of HandShake error until the BLocK ENoble is set) after which
the TIB is on its own and the key nUMbers need not be read by
the processor, though they will be available if desired.
If the block was enabled, the TIS will continue to read and
verify the data stored on the tape using CRCs until an error
is found, whether it be in a data fraMe or an ECC frOMe or
even in the key Mark. Any of these errors will cause the tape
to be stopped and an Interrupt FLaG to be raised along with a
COMpletion code indicating a Verify ERRor. Blank data blocks
are ignored so that key Marks May be verified on new tapes.
Each block that passes this verification causes the block
counter to be decreMented.
If the tape is stopped due to on
error, the operation May be reSUMed without a~justing the
block counter. When the counter decreMents to zero, the tape
will be stopped with an indication of Zero CouNT. This
verification procedure is intended to be capable of use in ao
off-line Monner where the processor needs only to
occQsslonally test for an Interrupt FLaG, otherwise the TI8
will be self-controlled.
A
~g-6j.16
sjb/RF
/
03-15-83
-
P.C. HO.
APPROVED
REVISIONS
DATE
7908
lSTK.NO.
07908-60241
----------.------------~
-
/
LTR
MODEL
INTERNAL MAINTENANCE SPECIFICATiON, TAPE IN'
MAR 13, 1984
BY
DATE
APPD.
SHEET NO.
SUPERSEDES
OWG.NO.
32
OF
88
A-07908-60241-10
~------------------------------~------------------------~-------------------------
ta32(). 286' CSl82t
D/H:C6
HEWLET1--PACKARD
3.8.3.6
co.
Mode 51 Seek N Blocks
The processor sets up the ClC block counter as Mentioned under
Verify, Mode 4 above, and selects the Mode while the TI& 1s
idle due to ReSTaRT. A,.ter its release to RUN, the TIB waits
~or the drive to reach operating speed, whether it be 60- or
90-ips, the faster being pre~erred for Seeks. The TIB then
decreMents the block counter each tiMe it encounters a key
Mark until the count is exhausted, at which tiMe it stops the
drive a~d signals a Zero CouNT with an Interrupt FLoG.
This process will count only the blocks seen while at the
requested speed; the Microprocessor will have to Make
allowance for the ef~ects of varying tape loads on the ti~e to
accelerate and decelerate.
This is a coarse seek only and the
processor will need to verifv the location o~ the tape bV
reading the key nUMber as required by the fine seek po~tion of
any other tape operation, though it should be repeatable to
within one block of the target.
3.S.3.7
Mode 6, DMA Test
This Mode causes the saMe behavior as Mode 3, Read TIB to DMA,
with Q single exception. Prior to tranSMitting data to the
DMA, the state Machine generates a known data p~ttern by
Manipulating the CLR~/1 control line~ to the SERDES to produce
zeros and using the output enable lines in conjunction with
th~ pullup resistors to produce ones while clocking the data
into the RAM using a COMbination of WCLK and RWC.
This
procedure preloads the RAM on the TIB with Q known pattern,
including header, user data and eRC space.
This pattern is a
checkerboard alternating between four bytes of all ones and
four byt~s o~ all zeroes. This Mode will usually be
associated with Q DHA loopbQck, utilizing both directions of
DMA transfers, Modes 0 and 3, for use in isolating the Mode
which May be causing di~ficulties in CQse of' IJ ftlilure.
For
More detailed instructions as to the use of this Mode, re~er
to the dOCUMent of section 2.2. Note that sel~ction of this
Mode also requires assertion of the Self-Test Mode Select bit
D6 of COMMand register 9.
A
48-6116
rsjb/RF
/
03-15-83
-
P.C.NO.
I
APPROVED
REVISIONS
8320- 2861 f 5182)
DATE
ISTK.NO.
07908-60241
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
-
/
LTA
"'OOEL 7908
MAR 13,
BY
DATE
APPO.
SHEET NO.
SUPERSEDES
OWG.NO.
33
1984
OF
88
A-07908-60241-1 0
ER48
HEWLETT-PACKARD CO ..
3.B.3.B
Write to
Tap~,
~P.1
D/H:C6
Self-Test
This diagnostic Mode is selected by asserting the Self-Test
Select bit, D6 of COMMand register 9} ot the SOMe tiMe as
Write to Tape, Mode 1, is chosen.
FrOM the processor and DHA
viewpoint, the operation proceeds as norMal, but upon readback
it will be noted that the CRC fields were written iMproperly
so as to cause errors to be detected on the second and fifth
froMes.
This causes the eRe Flags at status register S to
show !12. A subsequent DHA read should result in an
invocation of the autoMatic error correction procedure so as
to restore the dato of fraMe 2 to its initial contents; the
only indication thot this has taken place will be that the
header will be Mostly :eroed-out by the exclusive-OR
processing. Since the data fraMes corresponding to the
presuMably erroneous fifth fraMe (first ECC fraMe) are not
flogged as bod, error correction will not be invoked in this
case and only the CRe flags will be affected. More on this
con be found in the discussion of diagnostics at reference
2.2.
~~----------r-------~----------T--------------------r--------------.--------------A 48-6116 ISjb/RF
03-j 5-83 MODEL 7908
TK.NO. 07908-60241
Js
-_._--
INTERNAL MAINTENANCE SPECrFICA1ION, TAPE IN
/
~~----------+-------~----------+-------------------------~,~-------------------.-/
DATE
MAR 13 .. 19&4
BY
LTR
P.C.NO.
APPROVED
DATE
APPD.
SHEET NO . .34
OF
as
-1
~~--------~~------~---------~~---RS-E-D-E-S----------------~DW--G-.-NO--.-A---O-7-9--o-a----6-o-2-41=io]
REVISIONS
e320-2861
(~."821
ER4B
HEWLET1-·PACKARD
4.0
THEORY OF OPERATION
4.1
Microprocessor Interface
co.
lhPl
D/H:Cb
The Tape Inter~ace Board interfaces in turn to the
Microprocessor ~or reception of cOMMands and return of status
according to the control words Mentioned in Section 3.8
above. These control words are passed through a three-state
bi-directional buffer, U422 a 74LS24S, in order to reduce the
loading seen by the drivers on the MPU PCA.
This buffer is
enabled by TIBS-L, which is decoded on the HPU peA, in order
to avoid interference with other devices on the data bus.
Tht
direction of the dot a passing through U422 is controlled by
RD-L, which reMains in its inactive high state during Writes
to the TIB. All data bus lines are pulled up via R41B on the
lIB side of the buffer 50 as to guarantee a high level, for
test purposes, when the bus is turned off. ~tatus words read
frOM the TIB by the processor Qr~ addressed via the 74LS13B
decoder U432 enabled by TIBS-L and RD-H; whereas COMMands are
sent tq their target register as selected by another decoder
U442 enabled by TIBS-L and WR-L.
t--~-----9----
A
48-6116
sjb/RF
__-------'_---------"""""--------- --.-----.1'
O:~-l
5-83
"ODEL
/
P.C.NO.
APPROVED
REVISIONS
e32()':1861 f 5/821
790B
ISTK.NO. 07908-60241
----------
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
/
LTA
•
DATF
MAR
BY
DATE
APPD.
SHEET NO.
SUPERSEDES
DWG.NO.
3S
9'84-----'
OF
88'-
13,. i
.-1
A-0790B-60241- 1
01
ER48
HEWLETT-PACKARD CO.
(h~
D/H:C6
Tape Interface Boord Status
4.1.1
Status froM the TIB is stored in or buffered through seven
registers. STOO to STO' froM the HeD-7S is passed through the
three-state buffer U131 when enabled by RDST-L froM the
address decoder. SiMilarly, Status of the Interface,
including front panel switches and drive control) as well as
the Interrupt Flag frOM the TIB, is handled by U171. The CRC
Flags stored in U221 are output by buffer U112 when requested
by RCRCF-L, as ~he contents of the Revision/Rework register
U421 are output under control of REVNO-L.
The COMpletion Code
register U111 is an octal flip-flop which is latched by the
rising edge of the Interrupt Flag, which is saMpled by the
Microprocessor via U171 as Mentioned above with RIF-L, and
connected to the data bus by a low level on RCCOD-L.
As the Key NUMber is read frOM the tape by the TIB it is
stored in the register pair U431 and U441. These Universal
Shift Registers are used in the left-shift Mode with serlal
input frOM RDATA-H since the data is stored on the tape In a
least-significant bit first Manner. They are loaded by the
NEWKEN COMMand frOM the state Machine and their three-state
outputs are activated by RkNH-L and RKNL-L to place their
contents onto the data bus. RKNM-L has the additional
function of enabling two quarters of the quad three-state
buffer U451 to place copies of iADKEY and NEWKeY onto the data
bus in place of the upper two bits of the block address which
would otherwise be unused due to the fact that the MaxiMUM
block nUMber occoModates 4096 blocks of user data and a ~€W
overhead blocks) thereby requiring barely thirteen bits.
The
NEWKeY flag is set into U322 by SNUKY-L frOM the state
Mochine, read os just Mentioned using RKNM-L, and cleared
autoMatically on the trailing edge of a read of the lower byte
of the Key NUMber using RKML-L.
I
~'----------7------~~--------~------------------'-----------------------------'~
A 48-b116 Is jb/RF
03-15-83 MODEL 7908
STK. NO. 07908-60241
/
- - -
BY
DATE
APPROVED
DATE
APPO.
SHEET NO.
SUPERSEDES
DWG. NO.
I
LTR
P.C.NO.
REVISONS
t3»2M1
csm)
INTERNAL MAINTENANCE SPfrIFICATION, TAPE INl
MAR 13, 1984
36
i1IF
88
A-0'90a·-68241-10
ER48
HEWLET1--PACKARD
4.1.2
co.
[hJl-
D/H:
C~.
Tape Interface Boord COMMands
There are three cOMMand registers nddressed with TIBS-L and a
hexadeciMal address o~ 8, 9, or ~A, as decoded by U442, a one
of eight decoder. COMMands, as defined by the 3M COMpany in
the reference of section 2.3.1, to be sent to the HCD-7S tape
drive ar~ loaded into octal latch U161 by the decoding of
WDHOD-L corresponding to TIB address 8. The Microprocessor
May then generate a CSTROBE and send it to the drive by
setting the proper bit (DO> Into the Write Interface IQtch
U122, addressed by !A, decod~d as WIF-L.
Also contained in
the 'A register are the processor's copies of SACKN and RESET?
as well os control bits for the two front panel laMps BUSY and
Write Protect.
In SOMe instances the TIB's own state Machine
May deeM it necessary ~o stop the Motion of the tape drive;
this is done by using JAM-L to connect Q hard-wired !3D, the
Stop Motion COMMand, to the dr~ye Module yia U141 in place of
the norMal output register U161, by switching the three-state
output enables with JAM.
9 is contained in U312, an octal latch, and half of
a D-type flip-flop.
The upperMost bit of the octal
latch contains the Restart bit which is used to hold the state
Machine at state 0, when the bit is low, or to allow 1he state
Machine to run, wh~n high. The DMAC and DSELO bits are used,
re.spectively, to connect the TIB to the DMA and to select one
of two tape drives tied to the SaMe TIB.
(This latter feature
is not and probably will not be used.> BLKEN is held by the
flip-~lop being set by the Microprocessor and cleared (U332)
by the reading of a New Key except when the Verify Mode has
been selected.
R~gister
U322,
The reMaining ~our bits o~ the WFMDD latch U312, naMely MO-H2
and 5TE5T, deterMine the operation to be cQrr~ed out by the
state MQchine wh~n it is allowed to run by raising Restart-L.
These Modes will be described in detail later in Section 4.S.
~~------------------~----------~------------------,-----------------------.--------~
A
48-6116
~Jb/RF
/
/
03-15-83
- - -
~ODEL
7908
ISTK.NO.
07908-60241
------_.-
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
BY
DATE
MAR 1:3, 1984
~~----------+-------~----------r-------------------------~--------------------------SHEET NO. 37
OF
88
APPROVED
P.C.NO.
DATE
LTR
APPO.
~~----------~------~-----------r-------------------------~------'------------------~
OWG.NO. A-07908-b0241-1D
REVISIONS
SUPERSEOES
.32G-2861 151821
ER48
HEWLETT-PACKARD CO.
4.2
PP.l
D/H:C6
Clock Generation
The heart of the clocking circuits is a 19.2-MHz hybrid
crystal oscillator Y2131 (scheMatic zone C4) containing Q
bu~fered, sel~-starting circuit.
Schottky NAND gates ~rOM
U2132 provide further buffering and the pull-up resistors on
their other inputs provide Means of controlling the Master
clock during testing. This 19.2-HHz signal is used directl,
by U3131, a 14L5164 eight-bit shift register acting as a
digital dlfferentiator in the Tape Read circuitr~, and by the
half of U292) a 74974 D-type flip-flop) that generates the
MFM-encoded WRDATB.
The buffered Master clock is also ~ed to U2102) another 74574,
each half of which produces Q fifty-percent divided-by-two
version of the input with the outputs of the two halves in
quadrature. A NAND gate U291 serves to OR together all of the
negative portions of the two half-ratp clocks yielding 5CLK-H
which is a qunrter-rate 4.8-MHz clock with seventy-five
percent duty cycle. 5CLK-H is inverted by Ul102 (AID) to
provide the alternate phase of the two-pha~e clock needed by
the state Machine. The pull-up resistors on the NAND gates
are again used for test purposes.
U3121, an exclusive-OR
gate, picks o~f the two quarters o~ the sequence when the
outputs of U2t02 are at Oppo~lte logic levels.
This produces
a fifty-percent 9.6-HHz RWCB-H clock for use in DHA
operations. Generation of the RWC in this "anner guarantees
the correct phasing of it with respect to the state clock
5CLK , so thQt even though the DMA operations occur at twice
the stot~ rat~, the state Mochine can Manage theM without
confusion.
Two reMaining quorters of U1102 (AS) are used 0$
inverting buffers to provide the alternQte phase of RWC with
propagation delays roughly Matched to those in the SCLK path
and to allow control o~ the individual phases while testing
the PCA.
J--~-----r---
A
48-6116
LTR
P.c .... O.
__-----""'T""'----------""'---------------0:5'-15--83
7908
I
07908-60241
sjh/RF
MODEL
/
.-
-.
I
.•
-
-
APPROVED
DATE
INTERNAL MAINTENANCE
BY
APPD.
"'I
REVISIONS
.3~2861
15182'
t STK . HO .
SUPERSEDES
SPEr.IrICATIo~~~~E·
DATE
MAR 13, 1984
I
IN1
-I
:::OA::79~~~~~1_1~
fR4B
HEWLET1--PACKARD
co.
~P.l
D/H:C6
The final us£ of the Master oscillator is to feed the four-bit
counter U2112. This 748163 is used to provide ti~ing for
write datQ precoMpensation as well as acting as the lower half
of an eiQht-bit divider along with U2122. U3111 and U392 act
as dec.oder and buffer, respectively, to produce BIT Clock
~ITC-H, a 600-kHz signal with a one-eighth duty cycle.
WCLK
is 01.0 picked off of this divider as a bOO-kHz clock but with
fifty-percent duty cycle.
The last tap on this divider chain
results in SYTeK which is at the byte rate, one-eight of the
bit rate.
4.3
State Machine Controller, General
The control intelligence for the lIB is derived frOM Q
PROM-based state Machine.
The PROMS U142 and U241 are
adrtressed by a nine-bit counter COMprised of 74LS163's U212,
U222 and U232. This counter is cleared to select state nUMber
zero in response to GTO-L as Q result of Restart, Drive Fau}t
or Master Reset upon power-up. When GTO is relea~ed the
addresses will begin to sequence on the rising edge of
SClK-H. GTO is synchronized via U1111 (zone F20) to allow for
the fact that the nine-bit PROM address counter is cOMposed of
three different Ie packages which May hove varying set-up tiMe
requireMerts.
I
I
,
The caparity of each PROM is 512 eight-bit bytes. They ore
connected in parallel to produc.e 512 sixteen-bit words of
output. These outputs are defined in ~able 4.3. The two
Most-significant bits of the output words are used to select
between one of two output register pairs or to choose to
bronch on Q s~lected condition at the tiMe o~ the riSing edge
of the opposite phose of the state clock, na~ely SCLK-L. The
output registers are built frOM two pairs of 74LS377 octal
latches WIth ~ynchronized enable lin~s, When the M05t
slgnlficant PROM output bit is low at the appropriate edge of
SCLK, the word presented by the PROM will be latched into
Output Register pair nUMber One, U152 and U2bl, Llkewise, the
next significant PROM bit belng low at clock tiMe will couse
the adrtressed contents of the PROM to be loaded into OREGO.
U1b2 and U251. Sjnce the upper two bits of the output word
are uc;el1 to select which of' the two o"~put registers is to be
loaded, it should ~e noted thot eoch register contains only
fourteen usoble control blt., for 0 total of tw~nty-eight
control lInes to be distributed around the lIB. Under special
CirCUMGtonces, and only with the utMost of cautlon, both
"
,
I
I
~~--------~----~------~---------------~----------------------~J
A
4A-'6116 sjb/RF 03-15-83 t,10DEL 7908
ISTK.NO. 07908-60;:~41
I
f--f---.-------+-------f--.-----f.----->--
------.-1-------+------+---------------I
BY
1 - - - + - - - - - - - --- >---.----+-------+---------------- - -
LTR
P.C. NO
APPROVED
DATE
APPO.
f - - -.------~----~-----+_-------------------
REVISIONS
enD- 2961
15.112 J
. _._-.--
.- -'--"-'
INTFRNAL hAINlfNANCE SP[ClrlCA1ION. TAPE
/
SUPERSEDES
.---~----
DATE
t-)AR
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IN~
-----------.-. ---- -- ---SHEET!'.IO. ~.t;9
DWG.NO.
I
-----.--.
13. 1984
OF
88
-_.- ---- --- -- --A--07908-60241-10
ER4B
HEWLETT-PACKARD CO.
[h~
D/H:C6
output registers MQy be loaded siMultaneously (obuiously both
with the SaMe contents) SiMply by coding the PROMs to have
both enable bits low; this feature is used to inhibit activity
while the state Machine is held at state zero.
In the instance of neither output register being selected,
that is, the upper two bits of the PROM word being both high,
a JUMP condition will be tested. The particular qualifi~r to
be exaMined will be selected by the decoding of the next five
bits of the PROM word. A ~irst layer of decoding is done by
the one-of-eight selector U172, a 74S138. Decoder outputs 0
to 3 ore unused. The two output register control bits act to
enable the decoding of the four outputs 4 to 7, each of which
in turn is used to enable one of the four eight-bit qualifier
selectors, U311, U321, U331 or U341. The enabled 74S251 then
selects one of its eight inputs, based ·upon the next three
b~ts of the PROM word, and passes this condition bit to its
output where it is wire-ORed to beCOMe SADAT, the feedback
line used for testing by Means of Signature Analysis.
The
rising edge of SClK-L captures this result in the D-type
flip-flop U371 with pin 9 FALSE-L beCOMing the signal tho'
indicates a JUMp If Condition Not Met. When a tested
condition fails, FALSE-L will cause the nine-bit PROM address
counter to synchronously IOQd the next address frOM the lower
nine bits of the current PROM word.
If the condition which is
tested proves to be true, FALSE being high, then no branch
occurs and the address counter increMents to select the n~xt
higher rkOM word.
You May recall frOM Section 4.2 on Clock Generation that SCLK
has a seventy-five percent duty cycle.
It is the riSing edge
of SCLK that begins selection of a new PROM address. The
selected output MUst then be ready to be latched into the
output registers on the opposite clock edge, on the one hond,
the pas~er case, or the PPOM outputs Must be decoded to select
one ~T thirty-two qUQllfiers, which takes "ore tiMe. At the
~~lling edge of SCLK, the output registers are latched for new
cCMMond words or the test condition result is latched and then
set-up to load the next PROM address into the counter.
Both
of these paths are very quick cOMpared to the delays through
the PROMs and qualifier Multiplexor# hence, the aSYM~etrlc
clock.
In SOMe CQses the Qddress counter will reach state nu~ber 511,
known as LAST, either sequentially or through Q special
~~----------r-------~--------~r-------------------~-------------.---------------'A 48-6116 ISjb/RF 03-15-83 MODEL 7908
STK. NO. 07908-60241
/
- - -
APPROVED
DATE
/
I
INTERNAL MAINTENANCE SPECIFICATION,
BV
DATE
TAPE IN'
MAR 13, '1984
'_TR
P.C.NO.
APPD.
+-________________________
~_-L_ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _
REVISIONS
SUPERSEDES
i:~F
88 .___
SHEET
NO. 40
_______________________
~
DWG.NO.
A-07908--60241-1D
~--------------------------------~------------------------~--------------.-----------
8320- 2861 151821
ER4R
HEWLET1--PACKARD
co.
(hlJ
D/H:C6
branch.
It wIll then rollover through a do-nothing state to
state O. This guarantees that the upperMost bit of the
address counter toggles frOM high to low giuing on edge on
SASS to oct as the Start and Stop signal for Signature
Analysis. Also, for testinG purposes, the PROM outputs MOY be
disabled to float by pulling the input of the inverter U192
low causing ROMEN-L to go hlgh.
~~--------~~----------------~------------------~------------.---.--------------------~
A 48-6116 sjb/RF 03-15-83 -"ODEl 7908
ISTK.NO. 07908-60241
~~--------.~~--------~---------+------------------~----.--------------------------.-
INTERNAL MAINTENANCE SPECIFICATION " TAPE INl
/
~~-------'~~----~--------+-------------------r-----------
/
BY
DATE
MAR 13,
----,---
1984
~~--------.~~----~--------+-----------------------~----------------------LTA
~~
P.C.HO.
_______
APPO.
APPROVED
DATE
_ _ _ _L -_ _ _ _ _ _ _-+______________________
,~~
REVISIONS
8320- 2861 CSI82J
SUPERSEDES
OF
88
41 .___________
________
SHEET NO.
~
DWG. NO.
.~
A-O'j'908-b0241-1 0
ER48
D/H:C6
Pi]
HEWLETT-PACKARD CO.
Toble 4.3
State Hochine Control Bits
Outputs
Posi t ion
Reglster 0
o
LDAB-l
1
LDCRC-L
SNUKY-L
NEWKEN-H
2
3
4
Fl-H
·F2-H
F3-H
JAM-H
CSO-l
CS1-L
CLRO-l
CLR1-l
5
6
7
8
9
RCFLG-L
FCSTR-H
CTCT-H
DRNW-H
IFLG-H
RE.N-l
DMAEN-H
WCt\EN-H
WEN-L
CRCMR-H
10
11
12
13
lOHS-H
VERR-H
2CNT-H
BLANK-H
SUCCS-H
CWE-L
QUQlif'.i~r
Pos.ltion
Register 1
Mu)(
0
Fits
Mux 1
Hux 2
Hux J
};c2S0-H
0
t
t1()-H
H1.-H
ABCLI(-L
ABel K-H
CRCA-H
CRCB-H
2
H2-H
CRCD
Jc6-H
3
4
F;-~-H
JcU( FN-H
GAPX-H
FO-L
FO-H
CMPOK-H
f( YEXP-H
CRCL-H
CRCK-H
CRCNF-H
Fl-H
F3-H
REN·-H
IrIT7-H
UNCOND
5
PC1C-H
ATSP i)--H
NEWKY-L
6
7
B2-H
B3-H
1I0-H
STESl-H
-------------------------~
I
t.
LTR
48-6116
P.C."O.
5
jb/RF
03-15-83
/
-.
_.
/
-
-
APPROVED
DATE
MODEL
790A
STK. NO.
07908-60241
1 NTERNAL MINTfHANCE SPfCIFICATION. TAf'E
BY
DATE
MAP 13.
1~
"20-2861 (6/82'
t
APPO.
t-...L-----.....L..-----'--------I-------------t-- - - - - - - - . - --REVISIONs.
J~
,
SUPERSEDES
OWG.NO.
-.~~-,
A-0790B-b'241-1~
HEWLET''''-PACKARD
4.4
co.
l6P.]ER4B
D/H:C6
Read/Write InterfQce to Tape Drive
A cOMprehensive description
o~ the read and write data paths
froM the TIB bu~~ers to the HCD-7S drive Hodule follows in the
next four sections.
4.4.1
Gap Detection
The HCD-75 drive Module contains all the electronics for the
support o~ the read head l including prea"plifiers,
differentiQtors~ zero crossing detectors~ etc.
These are
necessary to generate a TTL-level signal RDDATA which toggles
every tiMe the read head encounters 0 flux transition. Note
that this waveforM is still HFM-encoded.
Gaps in the tape
forMat are detected by waiting for the RDDATA line to quit
toggling.
The drive "odule uses a data d~nsity of 10~OOO bits per inch
(bpi) and Q read/write tape 5peed o~ 60 inches per secon~
(ips). Therefore the burst data transfer rote on RDDATA i~
600 1 °00 bits per second or i.61-Microseconds per bit.
The
longest distance between two consecutive transitions in on MFM
wavefor" is two bit-tiMes or 3.3-Microseconds. (HFH coding
rules ore discussed in Section 4.4.3.> Any tiMe that there is
not at least one transition on RDDATA every S-Microseconds the
gap detection circuitry drops GAP-L to indicate thot the read
head is presently in a gap.
GAP-L i~ returned high by the
first tronsltion after the gap.
The GAP-L signal is iMpleMented as the Q (active high,) output
one-shot which uses RDDATB
lriput.
In actuality the
bidirec1i~nal one-shot is ~or"ed using both halves o~ U391~ a
74LS123, (one half triggered on the rising edge o~ RDDATB, the
other trjgQered on the falling edge) with the two Q outputs
OR-ed together. Both halves of the 'LS123 use Q S-Microsecond
pul~f-width ~hich is conservatively larger than the "aXiMUM
transitiDn spacing of 3.3-"icroseconds. As long as valid MFH
code is present on RDDATB the one-shots will ke.ep retrigge.ring
and GAP-L will reMain high.
As soon os RDDATB quits toggling
GAP-L drops low.
o~ a bidirectional retriggerable
(buf~ered RDDATA> as the trigger
A
lTR
48-6116
P.C.NO.
IS jb/RF
/
- -
/
-
APPROVED
REVISIONS
.320-2861 (5182)
03-15-83
-
DATE
~EL
7908
'STK.NO.
07908-61[)241
INTERNAL MAINTENANCE SPECIFICATION-,--l-A-P-E--I-N~~
--1
--- -1
S3
--J
MAR 13, 1984
BY
DATE
APPO.
SliEET NO.
SUPERSEDES
OWG. NO.
43
OF
A-(J790e-b0241-1 0
j
__-------------------------------------------
HEWLETT-PACKARD CO.
FR48
lhp']
D/H:C6
The HCD-75 drive Module uses a single track head and steps it
across ~he tope to access one of stxteen tracks.
This head
contains three gapped ferrite cores: one for reading and
writing and the other two ~or straddle erasing. The erase
core is energized in the front gap of a block to be written
and le~t energized until the rear gop. The turning on and o~~
of the erase core records two undesirabl~ transitions in the
Midst o~ the gaps. This probleM is encountered in all
saturation "agnetic recording products and has acquired the
trade nOMe of "crop in the gap." These undesired transitions
will trigger the GAP-l one-shots for S-Microseconds thus
creating noise on the GAP-L signal.
The GAPX-L signal is a cleaned up version o~ the GAP-L
signal. GAPX-L goes high sixteen bit periods
(27-"icroseconds) after GAP-L goes high and goes low
iMMediately with GAP-L. Thus) GAPX-L never has Q chance to
respond to isolated transitions.
The penalty is that GAPX-L
does no~ COfte high until two bytes into the sync ~ield of any
~ra"'e or key"
4.4.2
Recognition of pre-recorded forMat
The DC600 tape cartridges as sold are preforMatted with key
Marks approxiMately every 1.'S-inches. Each key "ark contains
a forward and a reverse key nUMber (with CRC) so ~hat the key
can be read in either direction. These key Marks delineate
4096-blocks per track each block of which can store 1024-bytes
of user data for a total tope capacity of 67-Megabytes per
cartridge. The quarter length DC615HC cartridge contains 1024
such blocks per ~rack for a forMatted capacity of over 16-HB.
Each block 15 recorded as four 256-byte ~rQ"es of user dat~
plus two 256-byte fraMes of ECC} thus the error correction
sche"e cho5e~ by 3M consists of SOX redundant recording. Note
that the preaMble and postaMble bring each fra",e up to
270-b,tes. The ~Qpe forMat 1s shown in Figure 3.7.2. For
More in~orMation c.onsult reference 2.3.3.
~~---------,~------r_--------_r------------------_T--------------.----------------.-
A
48-6116
sJb/RF
03-15-83
MODEL
/
p.c. ~O.
APPROVED
REVISIONS
ISTK.NO.
07908-6024.1
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
/
LTA
7908
DATE
MAR 13.. 1984
BY
DATE
APPD.
SHEET NO.
SUPE~EDES
owe.NO. A-07908-b0241-10
44
OF
SR
1
D/H:C6
HEWLETle-PACKARD
co.
Besides GAPX-L (se~ Section 4.4.1), the TIB state Machine
requires only one other signpl in order to deterMine the
current location of the read/write head on the tape.
This
signal is KYEXP-H which COMes high during a gap to indicQt~
that a key nUHber which can be read in the current direction
of tape travel is expected to iMMediately follow the present
gap_ Figure 3.7.3a shows KYEXP-H assu~in9 that the tape is
currently "oving forward and Figure 3.1.3b shows KYEXP-H
aSSUMing that the tape 1S Moving in reverse.
The circuit which generates KYEXP-H Must dIstinguish the front
gap during forward Motion and the rear gap during reverse
Motion without actually knowing which direction the tape is
Moving. The circuit to aCCOMplish this is shown in Fig'·"'t:!
4.4.1.
The 74LSlb1 counter U1122 is clocked once per byte.
If it
rEaches a count of fifteen, then it will latch up In this
state until cleared. The ripple carry-out constitutes
KYEXP-H. The counter is cleared by GAP-H so it only counts
during gaps. The fact that it has to count up to fi~teen
guarantees that KYEXP-H will not COMe on in the inter-key gap
(which is only two bytes long) or in any of the inter-fraMe
gap~ (also two bytes long).
The only reMaining proble" is t.
decide between the front and rear gaps and this is
aCCOMplished by the 74LS123 one-shots l U1121.
The first
one-shot fires for 500-Micro~econds on the rising edge of
GAPX-L. The second one-shot ~ires for roughly IS-Milliseconds
on the falling edge of GAPX-L if the first one-shot is still
active. ThUS, the only tiMe that the second one-shot gets a
chance to fire is right at the inter-key gap, since this is
the only tiMe that GAPX-L's fallinQ edge follows within
SOO-Microseconds of its rising edge.
(Note that
SOD-Microseconds represents roughly 37 bytes at 60-1ps.)
While the second one-shot is active, the 74LS161 counter is
disabled. Therefore, while in forward tape Motion the second
one-shot disables the counter during the front gap and when in
reverse Motion the counter is disabled during the rear gop.
This ensures that KYEXP-H will COMe up only in the re.ar gap
during forward tape Motion and in the front gap during reverse
tape Motion. Figure 4.4.1 shows the GAP-L, GAPX-L, Q1 (output
of first one-shot), Q2 (output OT second one-shot), and
KYEXP-H signals for forward and reverse tape Motion.
A
LTR
48-6116
p.c. NO.
sjb/RF
03-15-B3
I
- -
/
-
APPROVED
REVISIONS
8320-2861 (5182)
-
DATE
t.AODEL
7908
-
ISTK. NO.
07908-60241
INTERNAL MAINTENANCE SPECIFICATION, TAPE INT
MAR 13, 1984
BY
DATE
APPO.
SHEET NC'.
SUPERSEDES
OWG.NO.
45
OF
88
--
--
A-D79D8-b0241-1 0
__------------------------------------------
HEWLETT-PACKARD CO ..
4.4.3
ER48
(hpl
D/H:C6
MFH Encoder
The HCD-75 dr i ve f"Iodu le ret: ords do to usIng ttle HFH (or- ttl IIer)
code.
This code is defined by th£ ~ollowing encryption rules:
1) Each data bit is encoded in one bit cell.
(The HCD-7S
records 10,000 bit~ per lnch at 60 inches per second
so the bit cell period is 1.67-Microseconds.)
2) Transit.ons are allowed only at the beginning or
",iddle of a bit cell (but not both).
However,
~ach bit cell need not contQ~n a transitIon.
3) A transition in the ",lddle of a bit cell indicates
that that bit cell represents a "one."
4)
A transition between two bit cells indicates that
these two adJQcent bit cells both represent "zeros.~
Thus MFH only allows three di~~erent spacings between
transitions: 2T, 3T, and 4T, where 2T 1s the bit cell width.
These transition rates correspond to the 2f, 1.5f, and 1f
~requencles, respectively, whJch are often used to ~pecify the
frequency response of Mognetic heads. A continuous string o~
zeros or of ones gets encoded as a square wave of perlod 4T,
or a transition ~o transition distance of 2T. The data
pattern 100100100 ... gets encoded as a square wave of p~riod
6T and the data pattern 10101010 ... has Q period of 8T.
StraiQht MFM encoding is easily accoMplished by Merely Q few
Unfortunately, the job is cOMplicated by the need
for pre~oMpen~at~on.
In soturation MQgn~tlc recording each
transition is forM~d (written) by revprsina the direction of
the flux in the write head core.' Due to the inductive tiMe
constants, this reversal in flux More reseMbles on arctangent
funct~on than a true ~tep function.
lhe read head output 1s
proportional to the tiMe rate of change of the flux linking
the read head core by Faraday's law.
Therefore l the
ar(:1~nQent flux reversal produces Q Lore.ntzian type read
pulse. Now, at hlQh data densities the lorentzian pulses fro"
adjacent transitions overlap and interfere with each other.
This interference tends to shift the peaks o~ the read pulses
away frOM each other, a phenoMenon referred to as "peak
sh~ft."
I~ the peak Shift 15 too severe, then the phase lock
loc.p which tracks tt,e transitions r'eod bock will be
unnecessarily ogitated and Might dUMP iMproperly decode the
dota.
fl1p-~lops.
A
LTA
48-b116
P.c .... O.
'sjh./RF
MODEL
I
-
i
- -
BY
N'PROVED
DATE
APPD.
REVISIONS
83202861 (5182)
03-15-83
-
7'/08
I
,
07908-6-0-2-41---'---1
STk. NO.
J.NTERNAL MAINTENANCE
SUPERSEDES
DATE
ER4B
HEWLET1--PACKARD
co.
D/H:C6
(hJ1:l ------------------------
The purpose of precoMpensation then is to slightly shorten the
distance between inter~ering transitions so that upon read
back the peak shift pheno"enon will push the peaks bQck to
their correct position. Each MFH data pattern has its own
chQracterlstic peak shift which can be estiMated bas~d upon
the recording density (flux reversals per inch) and the
Lorentzjan pulse wid1h observed for on isolated transition.
The wo~st case peak shift for MFH encoding occurs ~or the 2T,
4T, 2T, 4T ... (i.e. 1101101 ••. ) data pattern. Most HFI1
encoders only bother to watch for and precoMpensate the "ost
severe dotQ patterns. However, the MFH encoder on the TIB caa
assign a different preco"pensQtion value to every different
~ive bit pattern.
This is to soy that the MFH encoder looks
at the i-2. i-1, i. i+l, i+2 bits in the write data streaM to
decide how to encode the i-th bit. It is assuMed that the i-th
bit is not af~ected by bits ~arther away than two bit cells.
The MFM encoder eMploys Q Master clock (provided by a crystal
Y2131) which runs at 32 tiMes the bit rate.
This
Master clock drives Q S-bit counter which is iMpleMented With
two 745163 counter chips U2112 and U2122. Counts 28 through
31 are decoded by a three-input AND gate U3111 on the three
Most significant bits of the counter. The output of this AND
yat. is delayed one clock period by U491, Q 14LS109 flip ~lop,
to beCOMe the bit clock (BITe-H). Thus,BITC-H has only Q
one-eighth duty cycle.
o~cilIQtor,
The bit clock gates binary data into the MFH encoder frOM the
write data buffers via the WDATA line. Thus, the five-bit
counter goes through an entire cycle of thirty-two states for
each data bit.
The binary data bits are fed into Q five-bit
shift re.qister U2121. The ~iddle ~lt 1n the five-bit shi~t
register is the bit currently being encoded and the other
neighboring bits ore provided so that the encoder con decide
on the appropr~ate aMount of precoMpensation.
I
~~--------~--------r----------r------------------~------------------------------~
A
48-6116 rs.ib/RF 03-1S-R3 ~OOEL 7908
STK. NO. 07908-60241
I
>-
lTR
-
-
INTERNAL MAINTENANCE SPE.CIFICATION;- TAPE
IN~
.
----------~------~---------~r_----------------------_,-----------------------_;
I
DATE
MAR
1984
BY
P.C-NO.
APPROVED
REVISIONS
-
DATE
13,
APPO.
SHEET NC.
SUPERSEDES
DWG.NO.
47
OF
S8
A-0790B-b0241-10
~------------------------------~------------------------~-----------------------~
8320-2261 15182)
ER48
HEWLETT-PACKARD CO.
~Rl
D/H:C6
------------------------~
The decision ~Qking eleMent is PROM U2111 which uses the five
consecutive WDATA bits as its address and outputs a five-bit
quantity which represents the count at which the HFH
transition for the "iddle shift register bit should be
generated. When the fiue-bit counter ~atches the five-bit
PROM output, the 14585, Q five-bit cOMparator, caus~s aD-type
flip-flop U292 to toggle. This flip-flop's output (WRDATB) is
the actual HFM code, which after buffering becoMes WRDATA and
is sent to the drive ~odule.
Since the Master clock runs at 32 tiMes the bit frequency
there ore 32 places within the bit cell where the HFM
transition can be l~cated.
Thus, we hove 3X resolution in our
precoMpensation. The HFM transition for Q one is placed in
the Middle of the bit cell which has been defined as Q count
of eight. The MFM transition for a pair of zeros is ploced
between the two bit cells which is then Q count of 24 C= S +
32 I 2). If we want to precoMpensate Q -one" transition 12~
early then we code the PROM for an output of 4 (= e - 12% /
3%).
If we want to precoMpensate a paired zero transition 6%
late then we code the PROM ~or an output of 26 (= 24 + 6% /
3%),
Certain HFM patterns
PrecoMpensate all 2T, 4T patterns by 15%.
2.)
PrecoMpensate all 2T, 3T patterns b, 12%.
3.>
PrecoMpensate all 3T, 4T patterns by 3%.
The worst case HFH pattern is the 1101 (or its dual 1011)
which gets encoded as a 4T transltion followed by Q 2T
transition. The transition corresponding ~o the "iddle "one"
bit gets severely peak shifted ahead. Therefor~, we
precOMpensate the location of this Middle transition by "oving
it back 15X frOM its norMal location, which would have been a
courit o~ 8, so that the PROM gets coded with a count of
thirteen for the five-bit patterns 01101 and 11101.
SiMilarly, U2111 is coded for Q count of 3 for the patterns
10110 and 10111.
A
48-6116
~jb/RF
/
- -
/
- -
APPROVED
DATE
I--
LTR
P.c.NO.
03-15-83
..,OOEL
7908
'$TK. NO.
07908-60241
----------------.
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
MAR 13, 1984
BY
DATE
APPD.
SHEETNC.
49
OF
88
~~--------~------~~--------~------------------------~--------.----..----------~
DWG.NO. A-()790S-60241-10
SUPERSEDES
REVISIONS
83»2N1 15182)
ER48
HEWLETT-PACKARD CO.
4.~.4
lhp']
D/H:C6
HFM Decoder
The decoding of an HFH waveforM bock into binary data is a
straightforward task. The only cOMplication (and it's Q
beaut) is that this HFH waveforM has COMe off a Moving tape
and thus is dlstorted due to tape speed variation and peak
shift proble"s. The peak shift probleM is addressed by the
precoMpensQtion circuitry covered in the previous section at
the tiMe datQ is written. The tape speed variation probleM is
solved by phase locking a local oscillator to the output of
the read head. This local oscillator is then used as a clock
to decode the HFH wovefor~. A COMplete block diagraM of the
read data path Is shown in Figure 4.4.2.
I will delay discussion of the phase locked loop MOMentaril,
in order to first describe the siMpler task of HFH d~coding.
The decoder requires only three inputs, "VeO", "R", and
"LOCK-UP". ASSUMe the existence of a local oscillator called
"Veo· which is synchrorized with the inCOMing MFH code. This
oscillator runs at twice the frequency of the incoMing bit
rate, or 1.2-Megohertz. We feed the MFH encoded read data
line RDDATB into Q bidirer.tional one-shot of period T/2, where
2T is the HFH bit cell period.
Note that this bidirectional
one-shot Is iMpleMented by a diqital circuit consisting of a
shift register U3131, giving Q delay of T/2, and an
exclusive-DR gate U3121 (scheMatic zone D2). The digital
circuit was chosen over an analog one-shot so that no tri"
pots would be required to set the pulse-width. The output of
this bidirectional one-shot is known as R (standard notation
for one of the phase detector inputs in a phase locked loop).
A third signal LOCK-UP COMes high once we are assured that th
phase lock loop hQ~ synchronized veo with RDDATB.
These three
signals are fed 1nto the MFM decoder to produce a binary data
output ROATA which is clocked into the TIB data buffers by
RCLK. The HFM decoder consists of four flip-flops and is best
explained by the ti"ing diagraM o~ Figure 4.4.3.
A
48-6116
sjb/RF
03-15-83
1
- - -
/
MODEL
7908
------_._----_._.-..
ISl .... NO.
07908-60241 .____ _
INTERNAL HAINTfNANCE SPECIFICATION) lAPE IN'
BY
DATE
MAR 13 #
1984
--~--------~------~----------~----------------------~~-----------------------
'.....- LTR
P.C.HO.
APPROVED
DATE
APfID.
SHEF.TNO.
50
\)F
88
~~--------~~----~~--------~------------------------+---------------~---------DWG.NO. A-079CB-6D241-10
SUPERSEDES
REVISIONS
':'»2861 '&182'
j
EP.4B
HEWLET1--PACKARD
co.
[hP.l
D/H:C
The first flip-flop U492 is "erely Q diuide-by-two on the VCO
line to produce ·UCO/2.· The next flip-~lop serues to detect
ones in the data strea". A ·one- bit is detected whene,er the
rising edge of R (therefore any edge or RDDATB) occurs during
the ·ones window" which is defined by VCO/2-L. After each bit
cell the detect ones flip-~lop is cleared.
The third flip-flop, the other hal~ o~ U492, latches the
output of the ones detector and properly synchronizes it with
RCLK. This flip-flop's output is the read data (RDATA) which
is transfered to the TIB data buffers. The fourth flip-flop
U491 serues as a "data valid" flag. After the lock-up s1gnal
goes high (indicating that the VCO is properly synchronized)
this flip-flop begins watching the RDATA line ~or any detected
ones. The lock-up signal goes high 32 bits lnto the 48-bit
sync field. Prior to this tiMe the veo "ight not be properl,
phase lOCked and the RDATA line Might detect spurious ones.
But by the thirty-second bit the decoder should be stably
detecting all zeros. Now the 4B-bit sync field actuall,
consists of 47 zeros plus Q one. This final bit is the ·sync
bit" and heralds the end o~ the sync field and the start of
data, It is this one bit for which the dQta ualid ~lip-flop
watches. Once this first one is detected the RCLK is enabled
and the data transfer to the lIB data buffers actually
begln~.
Note that the sync bit is swallowed and is not
tran~fered to the data buffers.
The only probleM l~ft is that of keeping the veo synchronized
with RDDATB and th~s is the job of the phase locked loop. Any
phase lOCk loop (~LL) consists of three basic ~unctionQI
blocks! a phase c'etector, Q loop -fllter, and Q voltage
controlle.d oscilla\or (se~ FiQure 4.4.2). The phase detector
has two inputs, R and V, and two outputs, ·speed-uph and
"slow-down." R is the output of Q bidirectional one-shot
triggered by RDDATB.
The one-shot period is T/2 where the bi1
cell period is 2T. N~te that the only allowed MFH transition
spacings are 2T, 3T, and 4T (corresponding to the 2f, 1.5f,
and if -frequencie~ used in specifying ~Qgnetic heads).
A
48-6116
sjb/RF
/
03-15-83
__ODEL
790B
ISTK. NO.
07908-60241
INTERNAL "AINT£NANCE SPECIFICATION, TAPE INT
~~--------~-------~r---------~------------------------'--------------------------/
BY
DATE
~~--------~------~~--------~----------------.--------~--------------.------~
Of
SS
SHEETNC. 51
,.c. NO.
APPROVED
LTR
DATE
APPD.
REVISIONS
e32~2861
CS/82)
SUPERSEDES
DWG.NO.
A-07908-60241-10
i
ER4B
HEWLETT-PACKARD CO.
D/H:C6
PP.l
The R phase detector input got it~ naMe because this is the
signal to which you are phase/~requency locking a
local oscillator. The other phase detec~or input V is ~ed
back froM the voltage controlled oscilla~or. The phase
detector COMpares the two input waveforMS R and V and signals
on its two outputs whether the veo needs 10 speed up or slow
down to Match the reference. HFH decoding requires an edge
sensitive phase detector. That iS I it outputs 0 correction
Signal only between the falling edges of the R and V pulse
inputs. Thus l R and V need not have the SOMe duty cycle to
achieve lock UPI although in actuality the, do.
re~erence
The loop ~ilter accepts the two phase de~ector outputs and
filters theM to present a SMoothly varying control signal
(Verror in Figure 4.4.2) to the VCO. This loop filter is
generally an int~grator and its tiMe constants are the Major
deterMinant of the PLL1s +ransient (locking and tracking)
behavior and noise b~ndwidth. Thes~ tiMe constants are chosen
so that Verror displays roughly critical daMping and achieves
lock-up about half way (40-Microseconds) into the sync ~ield.
The PLL bandwidth is set by the loop filter at the absolute
Mln~MUM that will still allow lock-up within the first half of
the sync field. This bandwidth Means tha~ the PLl can track
(without losing lock or Misdecoding data) a plvs or Minus five
percent sinusoidal speed variation on RDDATA at up to Q
4400-Hz typical Modulation ~requency and ten percent variation
up to Q 1400-Hz Modulation frequency.
A
LTR
48-6116
...c.HO.
/
- -
/
- -
BY
DATE
APPROVED
DATE
APPD.
SHEET NO.
SUPERSEDES
DWG. NO.
MODEL
7908
,-
-
03-15-83
REVISIO,.
8320-28&1 (5182)
IST~.NO.
sjb/RF
07908-60241,
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
MAR 13, 1984
S2
OF
88
A-0790B-60241-10
ER48
HEWLET1-·PACKARD
co.
(hi]
D/H:C6
The R phase detector input will receive a pulse, of width T/2,
on ever~ edge of RDDATB. These pulses can be separated ~y 2T,
3T, or ~T. The feedback na~ure of the phase locked loop
atte"pts to align a pulse on V with every pulse on Rand
therefor~ V Must run with period T so that there js Q V pulse
availabl~ to "atch up with each inco"ing R pulse.
The excess
V pulses MU~t not confuse the phase detector into thinking
that th~ VCO needs to b~ slowed down. The phase detectcr Must
output a correction signal only when on R and V pulse arrive
roughl~ siMultaneously and Mus1 output no correction when a V
pulse arrives by itself. Recall that the phase detector
aligns only the negative edges of the R and V pulse trains so
that it 1s pos~ible to use the puls~ width of R to define what
is "eant by "arriving roughly si"ult. ~eously." I~ V goes
through a COMplete cycle (l.e., rises and falls) before R even
starts a cycle (rises), then the phase detector ignores this V
pulse and does not generate a correction signal. If> however,
R is high when V falls then a "slow down" signal is sent frOM
the falling edge of V until the falling edge of R. AnytiMe R
falls before V Q "speed up" correction is output.
Vou can consider each pul~e on the R and V inputs to carry a
certain OMount of inforMation about the current
synchronization of the two signals. We Make use of all the
inforMation available on the R input. Every R pulse will
result in SOMe type of speed correction being output. At
MOSt, only every other V pulse results in the generation of a
correction Signal.
Every recorded area on the tape (including key nUMbers) has
the basic for"ot of sync field, preaMble (header), data and
postaMble (CRe). The sync. fleld is lntended for the sole use
01 the PLl.
It provldes the PLL Q chance to acquire lock with
the RDDATB signal before actual HFH d~coding begins. The
~lrst data actually passed out of the decoder 1s the preaMble.
~~--------~------~~--------,-------------------~-----------------------------~
A
48-6116 sjb/RF 03-15-83 ""ODEL 7908
ISTK NO 07908-60241
J
INTERNAL MAINTENANCE
/
I
P.c.NO..
DATE
REVlSIONS
8320-2861 t5J82)
.
.
SPECIFICATION~
TAPE INl
MAR 13, 1984
BY
DATE
AP'D.
SHEETNC.
SUPERSEDES
DWG.NO.
53
OF
88
A-0790S-60241-10
ER4B
HEWLETT-PACKARD CO.
Pi]
D/H'C6
While the tape head is in Q gap, the PLL is locked to an
alternate clock derived frOM the 19.2-Hhz crystal. This keeps
the PLL running ot roughly the correct ~requency in order to
MiniMize the tiMe required to lock to RDDATB. The GAP-L
signal COMes high at the beginning of the sync ~ield. This
switches the R phase detector input fro" the crystal to actual
RDDATB.
Since it is always known whot is written in the sync ~ield (47
zeros followed by the sync bit), the PLL can be configured to
take MaxiMuM advantoge of the pattern. The R input will be a
regular pulse train of T/2-width pulses separated by 2T. This
is shown in Figure 4.4.4. To take advantage of this ~act the
phase detector is placed in the acquisition Mode by having the
LOCK-UP signal low. In this ~ode the. phase dete.ctor Is Made
both phase and frequency sensiti~e and only every other veo
pulse is fed back to the V input. The R and V inputs are
identical during acquisition. The feedback nature of the PLL
then forces the veo to adopt a frequency of liT in phose with
RDDATB. Two-thirds (32 bits) of the sync field are allocated
for the PLL to settle to the RDDATB Signal.
After the sync field, the R phose detector input will beCOMe
on unknown pattern of 2T, 3T, and 4T ~paced pulses.
Therefore, the phase detector 'Ilnnot re"ain frequency
sensitiv~.
The PLL ~ust now generate speed correction signals
only when roughly coincident R and V pulses arrive at the
phase de tec tor.
A bit counter waits until 2/3 of the sync field has passed
before ra!sing LOCK-UP to signify the end of the acquisition
Mode and the beginning of the track Mode. In trark Mode the
phase detector is only phase sensitive and does not Mind the
fact that V runs with twice the ~OXiMUM frequency of R. The
VCO signal is now fed back in its entirety to the V phase
detector input so that there is always a V pulse availa~le to
line up with the R pulses regardless of whether thes~ pulses
arrive with 2T, 3T, or 4T spacing. It is now up to the phase
detector to choose aMong the V pulses £n generating speed
correction signals to the veo.
A
48-6116
sjb/RF
03-15-83
MODEL
7908
J
07908-b-O-2-4-1------~
~
STk.NO.
I
INTERNAL HAINTfNANCE SPECIFICATION, _T_A_P_E IN
/
lTR
P.C.NO.
APPROVED
REVISIONS
.3~2861
f 5182)
BY
DATE
APPO.
SUPERSEDES
DATE
MAR 13 ,
j
984
E'R48
HEWLET1--PACKARD CO.
[hi)
D/H: Cb
When LOCK-UP goes high 2/3 of the way into the sync ~ield, the
VCO will be properly synchronized with RDDATB, and decoding of
HFH is therefore possible. The MFM decoder is enabled by
LOCK-UP and begins watching for the first one bit) which will
be the sync bit. After ~inding the sync bit the decoder
begins clocking the succeeding preoMble bits into the data
buffers. Since the sync ~leld has ended, the R input will
quit being a constant frequency squarewave and will beCOMe a
COMplicated PUlSE train with 21, 3T, and 4T pulse spacings.
The phase detector now occassionally has to wait up to two
bit-cells be~ore it sees coincident R and V pulses so that it
can output a new speed correc.tion signal on Verror to the VCO.
No discussion o~ the read process for Magnetic tapes woul~ be
COMplete without a Mention of drop-outs. A Media iMperfection
or a MOMentary head to tape separation will cause Q
degradation in signal aMplitude known as a drop-out. At the
TTL-level interface to the drive Mndule a drop-out is
characterized by ~issing transitiols in Q fraMe or key. Any
MISSing transitions will just about guarantee that the data
will be incorrectly decoded. Therefore, it is up to the SOX
redundant recording Method of error correction to COMe to the
rescue ond recover the data.
Once the HFH d~coder has begun shipping data to the TIB datQ
buffers it will continue to do so until the lIB controller
drops the REN-H line. Thus, once LOCK-UP COMes high it will
reMain high until REN-H drop~. Therefore, it is up to the
controller to distInguish between valid forMat gaps and
drop-outs. Once the controller requests data, the PLL will
reMain locked to the RDDATB signal (regardless of whether or
not it 1~ even toggling) until the controller h~s decided thai
it has received enough bits.
The controller will then drop
REN-H which will drop LOCK-UP and the PLL will return to
tracking the alternate clock generated frOM the on-boQrd
crystal. Note that RCLK (which clocks decoded dat~ into the
lIB buffers> is enabled by DATA VALID which in turn is enabled
by LOCK-UP which is enabled by RfN-H.
If it 5h~uld happen that the PLL reMoins enabl~d through a
dropout where RDDAT& is not toggl1ng (50 that t~e R phase
detector input is qUiet>, the VCO Will coast at the current
frequency.
Neither speed-up nor slow-down signals will be
generated.
A
LTA
48-6116
P.C.NO.
sjb/RF
03-15-83
/
-
-
/
-
-
APPROVED
DATE
"'OOEL
7908
I
STK.NO.
I
07908:b(1241---it
---_ .... _---_.,
INTERNAL MAINTENANCE RPECIFICATION 1 TAPE
BY
DATE
MAR
13:-
i984----1
- - - - - - . - - - ------1~-------.----------.--
APPO.
SHHTHC.
SS
I)F
88
---L.-----+--.---------.---------1~--------------
REVISIONS
932~2861 '5182)
IN~
SUPERSEDES
-- -. - -
DWG. NO. A-- 0 790 a-i) 0241-1 0
ER48
·
D/H'C6
[lSi.]
HEWLETT-PACKARD CO.
Table 4.4
HFM PrecoMpensation PROM Contents as Percent
PROM Input
hex
A4 3 2 1 0
..
0 0
0
0
0
1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1
1
1
0 1 0
0 1 0
0 1 0
0 1 0
0 1 1
0 1 1
G 1 1
0 1 1
1 o 0
1 o 0
1 o 0
1 o 0
1 o 1
1 o 1
1 o 1
1 o 1
1 1 0
1 1 0
1 1 0
1 1 0
1 1 1
1 1 1
1 1 1
1 1 1
0 0
0 1
,
0
1
3
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
2) 2
2) 2
2) 3
2, 3
3) 3
3,
., 4
0
0
2
0
4
5
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 I
Prect'Mpensation
in percent
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 0
Transition
Pattern
6
7
8
9
-12
-12
0
-3
+i2
+12
NA
2
'"')
3, 2
none
none
none
none
A
B
16
17
18
19
1A
1F.c
Ie
1D
1E
1F
+12
+12
0
0
+3
0
+15
+15
NA
NA
NA
NA
-12
-15
0
0
2, 3
28
1e
8
B
9
4
4
4
0
2, 4
2, 2
2, 2
18
18
4
NA
NA
-12
-15
0
2, 4
2, 2
2, 2
3, 2
3, 2
3, 3
3, 3
4, 3
4, 4
4, 2
4, 2
none
none
none
none
24
24
28
9
HA
2, 3
C
D
E
F
10
11
12
13
14
1S
PROM Output
hex
dec
Ie
31
31
31
31
12
1F
1F
1F
lF
13
D
8
8
20
20
24
24
7
8
3
8
8
14
3
C
14
1J
19
?
8
3
3
31
31
31
31
12
13
8
IF
iF
IF
1F
8
8
C
D
8
A
,.
This bi t .is the one being encoded.
A
LTR
48-6116
P_C.~O.
sjb/RF
MODEL
7908
I
STK. NO.
-
/
- -
BY
DATE
APPROVED
DATE
APPD.
SHEET NO.
SUPERSEDES
DWG. NO.
-
.-
---
07908-60241
/
REVISIONS
9320-2861 (5182)
03-15-83
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
MAR 13, 1984
S6
OF
88
---1
-~
A-07908-60241-10
Pulse Width -
Pulse Widt..~ -
soo Ir.sec
15 msec
::t.
~
Q,
GAPX-L
----u
GAP-L
u
'"
\0
~
~
~
u
~
11:1
Lt
e"
...
2
Q;
~
~
~
~he
L504
:J\
:
Q,
CI)
~
~
....
r-.
.u
Cb
CLI
~
e
CII
~
Q:
crap in
gap,---u-l the
IV
~
~
t...
""
I fJap
-:- - - - - , r---1
,
U
u
~---..r-LSLJ
-.r-LII~_-"",
Kl'EXP-A
e
nn'----,r-u--ur-
crap in
U
+So~
KYEXP-H
~
16 bytes
-1Lll
r
Kl'EXP-~
I
I
H
16 bytes
FIGURE 4.4.1
Key Hark Recognition Circuit
Showing Operation During a.)
Forward and b.) Reverse Tape
,"otion. Note that the Frames
3re N~~beced Eor dn Even Number
(F0cward HvtionJ Track.
OATE
1-28-83
OWG.
.... 0. A-07908-60241-10
SWEET
57
OF
88
rhO'l
HEWLETT
&::~ PACKARD
veO/2
Alternate Clock
(generated from crystal)
NUX
vco
of 2
flipflop
YeO
NUX
vco
veO/2
RDDATA
REN
Gap
teet
Decoder
RDATA
ReLIC
Key
Nark
t--r--'lRecog-
1-00---11.
KYEXP-H
ition
GAPX-L
FIGURE 4.4.2
Block Diagram of Read Da ta Pa th
Showing Phase Lock Loop and NTN Decoder
DA'TE
1-28-83
OWG.
NO.
14-7908-60241-10
SHEET
58 OF 88
r"O't PACKARO
HEWLETT
a:a
R
VCO/2-B
RDATA
VCD-S
J
data
valid
LS109
0
K
LS04
CLR
RCLK
VCO/2-L
locJc-up
o
Rdda~
(mfm encoded)
1
o
1
1
- - . 2r . . , , - - - - •
- - - ~
'------T"-~
--flc- TIl
I
R
o
I
I
n__n__
I
I
I
-.--_n,--~n_,,---_,~
I
VCO-S
L
jVCO/2-L
l.,ones window)
detect ones
~--------~------~------~---~~-------,----~
-u---Lr
clear
data valid
sync
RDATA
bit
first
preamble
L~
bitll~
--------------------------------------------45th
RCLK
sync field
zero
FIGURE 4.4.3
HFH Decoder Circuit
and Timing Diagram. Note that
LOCK-UP has been high since 32nd
/J
__________________________________
__
______________________________________
l ______
CJ:J
~
s_·_~n_c
DATE
1-28-83
DWG.
~O.
f_~_·eld
A-07908-60241-10
:b~i~t
~
SHEET 59
OF 88
r/iptl.
HEWLETT
I.:~ PACKARD
o
~
~
1.1
....I
....,
CD
I
CD
gap-L
W
Rd data
R
,
o
)I
-..J
\0
o
CD
I
.....
0\
-fl"__---'n. . ._-'n
v
n
n ___n
Slow
down-L
n
n
n
n
n
LILJ
n
n
n
U
U
n
n
U
r
r
J
n
n
rL--.rLJl..
nJ--u-u-Ln.
-,-
[
Speed up-L ______~~----_T------------------------------------------------------~------------~
o....,
....I
veo
o
J
Lock-Up
M
.(
"',It-t
0\
o
o,.
CD
CD
f
If'. Source
J2nd Sync
rJeJd BJt
here Js tM
alternate
clock
gener.ted troll
crystal
~,----~~----~
AcquJsJtJon
~e
~------~~-----~~
"rack lfotJe
ER48
HEWLET1--PACKARD
4.5
co.
D/H:C6
[hpl
DNA Interface, including State Machine Control
The interface between the lIB and the DHA (Direct MeMory
Access) boards consists of f!ve signal lines.
Only one of
these, DOUT-H, is always connected to the corresponding outpu~
signal fro" the DHA, whereas the r~Malning four are inputs to
the DHA being driven by the TIB and are capable of being
disconnected vla a three-state buffer (U4S2) under control of
the "icroprocessor by "eons of the DMAC-H signal. lhis allows
another device, such as a disc drive to tiMeshare the saMe DHA
port.
Three of these ~our lines ore used for control in
passing DOUT-H or the ~ourth line, DIN-H.
The RWC-L, a
9.6-MHz clock signal with a fifty percent duty cycle, was
covered in section 4.2 above.
The other two control lines are
SOS-L and SOD-L.
The TIB pulses SOS-L to its active low state (U462, U4S2) for
two full RWC periods as it loads its own byte counter (using
LDAB-L) with an initial count of 248.
This acts as a wakeup
alarM to get the Qtten~ion of the DMA.
Several clock cycles
after this Start Of Sector, the TIB will pulse low on SOD-L
(through the other hal~ of U462) to indicate the Start 0
Data.
The nUMber of clock periods between these two control
pulses depends upon the direction of data transfer, being
twelve for a write fro" the DNA to the TIB and eighteen for a
read frOM the TIB to the DMA, and is controlled by gate U262
(scheMatic zone F24).
The data transfer begins in a
Most-significant bit first Manner with the six-byte header
followed by 256 bytes of dota, a two-byte CRC and place
holding dUMMY bits for five bytes of Fire Code check word
which May later be filled in by SOMe discs.
Due tc DHA design
requireMents, the first usable bit of data is separated froM
the SOD-L pulse by four dUMMY bits in the ~ode in which the
DMA is writing to the TIB and by six dUMMY bits jn the r~Qd
Mode.
The Microprocessor is responsible for setting up the
DMA circuitry to converse with the TIB.
The Sector Toggle
STOG-H line is used to Monitor the progress of the transaction
since the TIB expe~ts to transfer four ~ectors (one block) of
data at a tiMe whereas a disc connected to the SOMe DMA port
would only pass one sector at Q tiMe.
A fifth SlOG transition
and a fifth 50S pulse are sent to the Microproc.essor and DMA,
respectively, to terMinate a block transaction.
More
inforMation on the DMA interface can be found in the IMS for
that board.
A
48-6116
~jb/RF
0:3-15-83
MODEL
7908
ISTK.NO. 07908-60241
INTERNAL MAINTENANCE SPE.CIFICATION, TAPE lNl
I
~~----'------~--I----~--------~~------------------------'-------------------------BY
OATE
MAR 13, 1984
LTR
P.C.NO.
APPROVED
REVISIONS
83~2861
(51821
DATE
APPD.
SHEET NC.
SUPERSEDES
OWG.NO.
61
OF
88
A-07908-60241-10
ER48
HEWLETT-PACKARD CO.
4.6
D/H:C6
(hP.l
Modes oT Operation
4.6.1
Non VatQ-TransTer Operations
The lIB is capable oT controlling and/or participating in
various Modes which do not involve the transTer of data.
These include seeking to a particular block on the tape, an
oTT-line veri~ication of any nUMber of blocks on the tape
track currently over the head, and various diagnostic and
debug ,",odes.
4.6.1.1
Seek (Coarse)
Certainly the Most frequently invoked, and yet the Most
hUMble, Mode is Seek. Prior to atteMpting a read, write or
verify on a particular block on the tape, the controlling
Microprocessor Must first cau~e the transport to locat~ that
block. The processor has djrect access, via control register
8 Mentioned in section 3.8, to the dri~e electronics ~or the
positioning oT th~ head onto the proper track of the tape and
can initiate Motion along that track, but Must rely on the TIB
to locate the desired block.
Since the TIB is only capable of
carry~ng out a relatlve ~eek 1t Must in turn rely on the
processor to set uo the length. But then the processor only
knows where it wonts to go and cannot COMpute the relative
distance until it knows the current 10cat10n. This is easy 1f
either BOT or EDT (~eginnlng or End or Tope) status is showing
in the Drive Statu~ register 0, but, jf not, the TIB MUSt be
requested to do a "Fine Seek" in order to return the current
location.
This "FJ~e Seek" is a sobset of any data transfer
operation and will be covered 1n section 4.6.2.
A
48-6116
03-1S-R:3
sjb/PF
,,
,
I
LTR
P.c .... O.
APPROVED
-
-
-
DATE
MODEL
7908
I
STK. NO.
INTERNAL MAINTENANCE
~
07908-60241
,
SPEClrICATIO~~~~E ~~
BY
DATE
APPO.
SHEET NO.
MAR 1:3
62
~ 198~___ . __
OF
.j
88
~~----------'~------~----------+--------------------------r--------------------------DWG. NO. A-O 7908-602~1-1 0
SUPERSEDES
-REVISIONS
832G2861 (5/82)
ER 48
HEWLET'--PACKARD CO.
D/H : £:6
(h~
Given the current location of the tape and knowing the target
address along a given track) the processor COMput@s the
relative distance in units of data blocks and sets this nUMber
into a register in the Count@r TiMer Circuit (CTC) on its own
board. This nu~ber 1s adjusted to allow for worst case rates
of acc@l@ration and deceleration of the tape drive as well as
an offset to allow for pre-positioning for the n~xt
operation. This offset will stop short of the target for the
case in whjch the next operation will continue in the SOMe
direction as the seek or it will cause the tape to oversho01
the target to allow for an acceleration following a reversal
in direction.
Once the seek length is loaded into the CTC and the tape is in
Motion) the processor requests the TIB (via register 9) to
begin the countdown to 1he target. The state Machine first
waits for the tape drive to return At Speed status, then
begins Monitoring the KVEXP signal which was covered 1n
sec.tion 4.4.2. Since only one KYEXP pulse occurs per block
and since this circuitry was designed to work for both the
60-ips read/write speed and the 90-ips seek speed, all the
state Machine has to do is to count the nUMber of pulses. The
state MQchine pulses the eTC on the processor board each tiMe
KYEXP goes high and watches for the eTC to return a carry
output. The state Machine then JUMPS ·0 its ZCNT (zero count)
routine and jaMS Q Stop Hotion COMMand to the tape drive,
while returnjng appropriate status to the processor.
A
48-6116
iSjb/RF
03-15-83
/
-
-
/
-
-
~
MODEL
7908
I
STK. NO.
07908-60241
INTERNAL MAINTENANCE SPECIFICA110N-; TAPE IN12
BY
DATE
MAR 13, 1984
~~-----------+-------~----------~------------------------~------------------------~
B8
SH~ET "c. 63
OF
APPROVED
r.C.NO.
DATE
APPD.
LTA
~~-----------~------~.----------~------------------------~----------.-----------.----~
REVISIONS
8320-2861 (5182)
SUPERSEDES
DWG.NO.
A-0790B-b0241-10
ER4B
HEWLETT-Pl~CKARD
4.6.1.2
Read
Key~
co.
b/H:C6
(h~
or NFine Seek M
While not a Mode by itsel~~ a "~ine seek N is a necessary
prerequisite to any activity involving data and the tope.
This operation therefore is a subset of the read) write and
veri~y Modes.
The coarse seek of the preceding section puts
the target block on the tape near the head then requests one
of the dnta transfer Modes which includes this ~ine
positionino algorithM.
Essentially, the data transfer
operation ~s begun, but no data is actually transfered pending
the assertion of BLKEN (Block Enable) by the processor.
The
state Machine will continue reading the tape and passing bloc~
nUMbers to the processor until it finds the desired targ~t
(known only to the processor) and then enables the block for
transfer.
Hore speCifically, the stat~ Machine waits for the tape drive
to return At Speed status and then begins looking ~or a Key
Hark.
In this case the KYEXP hardware is not us~d but a
siMilar algorithM is iMpleMented in firMware.
8asicallYJ this
aMounts to watching the GAPX signal and picking out gaps
having a width exceeding the tiMe equivalent of twenty-seven
bytes (a conv~nient count, greater than sixteen), or
360-usecs.
Gaps of this length occur as long dropouts in data
fraMes, or legitiMately between the Reverse Key Hark and the
first data fraMe of Q b~ock, or iMMediately prior to the
Forward Key Hark.
It is the latter that we wish to segregate.
The state Machine b~gins with the aSSUMption that any data
following such Q Q~P is indeed a key Mark until proven
otherwise.
In this Manner it signals the PlL (part of section
4.4.4) to Lock-up and to begin passing data following
recognition of the Sync bit.
The state Machine shifts the
first two bytes of this data, least significant bit first,
into a sixteen bit register cOMposed of U431 and U441 enabled
by control bit NEWKEN.
This saMe data streaM along with the
next two bytes, preSUMably the eRe code bytes for the Key
Mark, are routed to the eRe checker U1112.
If, after these
four bytes have been trapped, the eRe syndrOMe tests equal t.
zero, then we hQve Made a successful cQpture of the Key and
will so notify the processor by using SNUKY to set the NEUKY
flag U322.
I~ the CRe does not go to zero) we still have a
chance that this reQlly was the Key Hark but contQined an
error.
We can double-check by testing that the length of the
data fleld is QPpropriate to a -four-b'lte Key Hark, following
~~---------~--------r----------r------------------~--------------'----------------.sjb/RF 03-15-83
A 48-6116
07908-60241
MODEL
INTERNAL
/
/
~."
7908
BY
1
HAINTENANCE
STK. NO.
SPECIFICATION, TAPE IN1
DATE
MAR 13,
1984
~~--------~--------~--------~------------------------~------------------------.88
SHEET NO. 64
OF
APPO .
• .c.NO.
APPROVED
DATE
LTR
REVISIONS
.:t20-2e&1 151821
SUPERSEDES
DWG.NO.
A-0790B-60241-10
ER 48
HEWLET1--PACKARD
co.
D/H :: C6
PP.l
the usual six-byte sync Tield, which was stripped by the PLl.
circuitry. I~ the data area is o~ the. proper length but
contains a CRe-detected error, we will continue, Qssu"ing that
at least we ore properly oriented with respect to the block
ti~ing on the tape.
In the'case of this being a fine seek
which is part of Q read operation) we will later extract the
correct block nUMber f:·o .. the data -fraMes) in which CQse we
will wait with SNUKY, but if we are being asked to do a write
operation, we will set NEWKY and rely on the processor to
notice the CRe flag set in register S for the bod key and
therefore to hold off on BLKEN. If, in the re~aining case,
the data field is too long to be a valid Key Hark, then we
Must have co~e upon either the first data fraMe or have
stUMbled into Q dropout} in either cose, the state Mochine
returns to searching for a twenty-seven byte gop.
In Q read or verify Mode, the state Machine will continue
toward the dato transfer portion of the operation followIng
recognition o~ 0 Key Hark, whether the data is correct or
not. For a write operation, howeyer~ further action depends
upon the condition of BLKEN. Once Q Key Hark is detected,
good or bad, the CTC, which had been set up by the processor
as Q tiMer, is triggered by the state Mochine to begin a
tiMeout to guarantee that the erase head clears the
preforMatted region of the tape b~ a suitable Margin. This
saMe tiMe interval allows the processor to pass judgMent on
the key nUMber and its eRe. If the proc.essor likes what it
sees it will set BLkEN high and the state MQchine will ju~p to
the DMA portion of the data transfer. If, on the other hand,
the processor either sees a eRe flag or the wrong target
nUMber, it will withhold ICLKEN, the state MQchir.e will see 'the
CTC tiMe out, and return to f!nd the next Key Mark} the
default is to abort the write. to tape..
A
48-61 j.6
sjb/RF
03-15-83
MODEL
790B
I
STK . NO.
0790B-60241
___
INTERNAL MAINTENANCE SPECIFICATION, TAPE INT
I
~~--------~------~----------~------------------------~-------------------------.-I
MAR 13, 1984
DATE
BY
LTR
PoC.NO.
APPROVED
REVISIONS
DATE
APPD.
SHEETNC.
SUPERSEDES
DWG.NO.
6S
OF
88
A-,0790B-68241-10
ER48
HEWLETT-PACKARD CO.
D/H:C6
~~ --------------------------,
Data Tranfer Operations
~.6.2
4.6.2.1
Write Data froM DMA to Tape via TIB
A Write to Tape operation is accoMplished in several steps.
The first of these requires positioning of the tape head at
the appropriate location on the tapej this is accoMplished b,
utilization of the coarse and fine Seeks which were covered in
section 4.6.1. Once the proper block on the tape has been
found through the coars~ seek, the Microprocessor will put the
TIB state "achine into the Write Mode and it will do the fine
seek. This locates the block to be written~ usually
(explanation COMing soon).
Before passing control to the TIB, the processor will have
preloaded the appropriate channel of the eTC with a delay tiMe
corresponding to the tiMe between the Key Mark and the turn-on
of the erase current, varying according to ~orward or revers~
direction of tape Motion. If the key nUMber read by the TI~
and passed to the processor is the proper target, the
processor will raise BLKEN prior to the expiration of the
delay. On the other hand, if the key read is not the torget
or it hus a bad eRe, then the processor will allow the CTC to
tiMeout without raising BlKEN and the TIB will return to the
fine seek Mode looking for the next key. (In reality, the
processor restarts the eTC with a tiMe value set near zero so
that it will tiMe out very quickly, but without giving
BLKEN. )
Once the target has been found and the first CTe value has
tiMed out with BLKEN present, the state Machine will retrigger
the eTC for the delay frOM erase to data and begin a DMA
transfer. During the first delay the processor will have
loaded the eTC with the proper tiMe value and set up the DMA
buffers as needed. As soon as this second delay expires, the
TIB will begin writing frOM its RAM buffers to the tape. The
four dota fraMes are copied directly frOM the RAM with
insertions for sync fields. The two ECC fraMes are created on
the fly by siMultaneously reading data frOM both RAMs and
exclusive-DRing the results for tranSMission to the HFH
encoder and on to the tape. HINST is ORed into t~e data
streaM to create the proper fra~e nUMber in the header of the
ECC ~rQ"es. Two-byte interfrQ"e gaps are generated between
adjacent fraMes.
I
.-
~~---------,--------~---------r-------------------r-----------------
A
48-6116
sjb/RF
03-15-83
MODEL
/
P.c.HO.
AWROVED
REVlSIONS
n:zo.2861 C5182)
STK.ND.
07908-60241
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
I
.~~ LTR
7908
DATE
MAR 13, 19B4
BY
DATE
APPD .
SHEET NO.
SUPERSEDES
OWG.NO.
66
OF
88
A-0790B-60241-10
ER4B
HEWLET1--PACKARD
co.
l'il
D/H:Cb
At the end of the data area of the block) the state Machine
again triggers the CTC (preset by the processor) and holds the
WRDATA line qUiet to erase a clean flnal gap. When the CTC
co"pletes, the TIB reverts to the fine seek "ode in
preparation for the next block.
4.b.2.2
Read Data frOM TQpe to DHA via TIB
To read fro" the tape it is first necessary to find the target
blockJ this is accoMplished using the Seek Modes Mentioned
earlier. The target Is approached using the flne seek
contained in Read Mode 2. After each Key Hark is recognized
and passed back to the processor, the stQte "achine continues
reading the data Qn~ storing it in the appropriate RAMs. If,
after the reading frOM the tape 1s COMplete, the TIB notices
that the processor has set BLkEN high, then Q Successful
COMpletion status will be passed to the HPU and the state
ftQchine will halt expecting to be restarted ~or a DHA Read
transfer. If, however, BLKEN had not been set prior to
COMpletion of the read frOM tope, then the state Machine will
treQt Its activity as Q fine seek and continue to do "ore of
the saMe. This process will continue until either the TIB is
restQrted, the tape runs Into BOT or EDT, or the processor
fails to clear the New Key flng NEWKY by reading one key
nUMber prior to the receipt of the next, in which case the TIB
will stop the tape using JAM and issuing a Loss of Handshake
status Message.
While reading data frOM the tape, the first two fraMes are
stored into RAMO U362 and the next two lnto RAMi U4bl. At the
end of each fraMe the CRC status for that fraMe'. header and
datQ areas is saMpled and stored away into the eight-bit
addressable latch U221. When the fifth fraMe is reached on
t·· ... ~~pe, 'the CRC's for the first and third fraMes are checked
to ~etect whether or not error correction is required. If the
fraMes are signalled to be either both good or both bad, then
the fifth fraMe is not stored and the first and third will
stand without alteration. If, on the other hand, one of the
pair of data fraMes is shown to be good and the other bad,
then the first step of the two-part correction procedure will
take place, naMely the overwriting of the bad data fraMe with
the preSUMed good error correction fraMe. SiMilarly, the
sixth fro"e "oy be used to overwrite either the second or
fourth fraMe in the upper half of one of the RAMs. The actual
writing of the data into the RAMS is controlled by the state
A
48-6116
l.TR
P.c.NO.
sjb/RF
03-15-83
/
/
- - -
APPROVED
DATE
REVISIONS
832C).28a1
~,
MODEL
790B
ISTK. NO.
07908-60241
INTFRNAL MAINTENANCE SPECIFICATION) T.,\PE INT
MAR 13 1 1984
BY
DATE
AHD.
SHEET~C.
SUPERSEDES
DWG. NO.
67
OF
88
A--07908-60241-i 0
ER48
HEWLETT-PACKARD CO.
Pi]
D/H:C6
Machine through its output reglster U2S1 using the chip
selects to select one RAM at a tiMe even though both will
receive a co""on write enable RAHWE and output disable (a
function of MOUT).
After BlKEN has been recognized following the read of a block
of data frOM the tape and the rIB has sent a Successful
COMpletion flag to the processor, it Is assuMed that the
processor will set up the DMA, connect it to the TIB using
DMAC and reSlart the state Machlne in Hode 3 for the actual
transfer of data to the DHA. It is during this transfer tha1
the second of the two-part error correction scheMe is
executed. Prior to the tranSMission of any fraMe the state
Machlne will saMple the CRe status bit in U221 for that
particular fraMe. If the bit is low, the fraMe being good ,
then the fraMe will be sent as lSI However, a high CRC due to
Q bad fraMe will cause tranSMission of the bit-by-bit
exclusive-OR function of the fraMe in question and its
correspondent in the fraMe pair (that is, fraMe one with three
and two with four). The aSSUMption here is that if a fraMe is
Marked bad then it has already been overlayed by the proper
error correctlon fraMe. For a specific exaMple, take the case
of Q bad fra"e two. When fraMe slx was read frOM the tape it
would have been written to RAM oyer the top of fraMe two -this is the first phase. During the DMA transfer it is noted
that the second frQMe was bad and therefore preSUMably
overwritten by the slxth which will now be exclusiye-ORed wIth
the fourth to create a good copy of the second,provlding g~
course that the sixth was good -- the second, and COMpleting
phase, In any case where the error correction fraMe in use Is
also bad the error Is autOMatically uncorrectable, since the
correctIon would not haye been atteMpted If another associated
fra"e had not also been bad. It is left to the Microprocessor
to deterMlne directly frOM the contents of U221 whether or not
an uncorrectable error has occurred.
~~---------'~------~---------T------------------~------------------------------.sjb/RF 03-15-83 MODEL 7908
A 48-6116
ISTK.NO. 07908-60241
INTERNAL MAINTENANCE
/
/
LTR
P.c.NO.
APPROVED
DATE
SPECIFICATION~
TAPE IN'
MAR 13 .. 1984
BY
DATE
APPD.
SHEET NO.
SUPERSEDES
~.NO.A-01908-60241-10
68
OF
88
ER48
HEWLET1--PACKARD
4.6.2.3
Tape
Veri~ication,
co.
(lp]
D/H'C6
--------------------------,
Offline by TIB
,
Though not presently supported by the Microprocessor with
regard to user data, this "ode (TIB op code S) is used to
verify the systeM blocks (spare tables and such). Very
si"ilar to the Read froM Tape, the hardware Verify begins with
a ~ine seek phase. The processor loads the lIB's channel of
the eTC with the nUMber of blocks to be verified, ~p to 4096
for one full track. Once BLKEN is asserted to show approval
of the key nUMber, the TIB will do the equivalent of the read
operation without requiring the processor to approve any
additional key nUMbers. The Verify varies froM the read in
the action perforMed at the end of the block. If the block
was COMpletely acceptable, the eTC will be counte~ down by
pulses froM the state Machine until it reaches zero. At the
zero count, lCNT status is asserted and the tape is stopped by
the TIB via the JAM signal which strobes a !3D COMMand to the
HCD-1S. On the other hand, any ti"e that even a single ~raMe
or a key is found to be in error based upon the eRe results,
the tape is also brought to a halt by the saMe Means and Q
Verify Error status is reported. In the course of a
verification blocks that are not recorded are distinguished
frOM long dropouts and are not flagged as faulty so that thi~
Mode May be used to verify the key Marks on an otherwise
unwritten preforMatted tape. Since this Moue i~ COMpletely
self-contained once set up, disc operations can be executed by
the processor while the tape is running on its own without
lntervention, until the end of the track is reached, at which
tiMe the processor is needed to step the head to the next
track and 1ni1ia1e 1h! change of direction of "otion COMMand
sequence to the tape "echan~s".
It is possible for the
processor to be clever and set Q Much larger nUMber into the
CTC and rely on the EDT and BOT detectors in the tape
MechaniSM to stop the tape and flag the processor through the
TIB; in this Manner a full tape could be verified essentially
without attention except on a periodic interrupt basis 10 step
tracks and reverse direction.
A
48-6116
sjb/RF
/
- - -
APPROVED
DATE
/
LTR
P.C.NO.
REVISIONF
e32G-2M1 (5182»
03-15-83
MODEL
1908
1
STK. NO.
INTERNAL MAINTENANCE
07908-60241
SPECIFICATIO·~ ,
TAPE INl
MAR 13, 1984
BY
DATE
APPD.
SHEETNC.
SUPERSEDES
OWG.HO.
4)9
OF
as
-
A--0790B-b0241-1D
£R48
HEWLETT-PACKARD CO.
4.6.3
4.6.3.1
D/H:C6
(hi.]
Diagnostic Modes
DMA Loopbock
Selection of Mode 0 causes a response alMost identical to t~e
DHA portion o~ the Write froM DHA to Tape Mode 1. In this
Manner a transfer frOM the DHA to RAM on the TIB can be
executed without the presence of a tape. When this is
followed by a Mode 3 transfer frOM the TIB's RAM ba~k to the
DHA, the loopback is COMpleted. This sequence, controlled by
the "icroprocessor which is responsible for generating the
randoM data patterns, storlng theM in the DMA's RAM and
cOMparing the dato when it is returned, is used a~ a quick
det~ction of probleMS in the RAMs ~nd SE~DES as well as the
interfoce cir:.uits between the DMA and TIB boards. Mode 0
only differs frOM the DMA portion of "ode 1 in thot the eRe
flags stored in U221 ar'e clea.'ed prjor to the first (write)
transfer so os to avoid the unpredictable results thot would
occur if the subsequent call of Mode 3 were to atteMpt the
second phase of the error correction process descrIbed in the
appropriat~ s~cti~n above.
4.6.3.2
Buffer Fill Mode
If execution of the DMA/TIB loopback sequence should point up
a failure in SOMe portion of the cir~uitry tested, it beCOMes
desirable to narrow the field of suspected COMponents. This
is assisted by use of Mode b.
This Mode when called upon will
cause the TIB's state Machine to generate a known data pattern
and store it into the RAM.
The pattern can then be
transferred to the DMA via Mode 3 and checked by the proc.essor
to segregate probleMS between the rlQd and write paths
connecting the TIB and DMA. The p~ttern g~nerQted is an
alternQtion of four bytes eoch of 011 ones and all zeros
through 011 four ~rQMes.
A
48-6116
sjb/RF
P.c.HO.
MODEL
790B
I
srK NO
07908-60241-------
~
I . . SPECIFICATION, TAPE i~
INTERNAL HAINTENANCE
/
- - -
BY
DATE
APPROVED
DATE
APPD.
SHEET NO.
/
LTR
03-15-83
------_.j
MAR 13:. 1984
70
QF
8B
~-L--_ _------~----_ _~_ _ _ _- - - - - - + _______- -______----------~----------------------
REVISIONS
8320-2861 '511t4
sur.: RSEDES
OWG.NO.
A-07908-60241-10
I
ER4B
HEWLET1--PACKARD
4.6.3.3
Write Bad
eRe
co.
D/H:C6
[hP.)
to Tape
By raising the Self Test Select bit s~"ultaneously with the
selection of Mode 1, the TIB can be cOMManded to write
inforMation containing known faults to the tape.
The specific
~oults are bad CRCs on the second and fifth froMes.
A
subsequent read of the i"properly written block will show eRe
togs set for these two frCMes, cause the error correction
circuitry to be invoked to restore froMe two and produce no
Error correction response to the faulty fifth fraMe.
This
~ode is norMally executed as part of the power-on self-test on
Q particular block in the systeM area o~ the tape near BOT.
~-r----------~-----A 48-6116 ~ jb/RF
__03-1S-A3
----------~--------------------r-----------------------'--------~
790B
07908-60241
JSTK. NO.
~~----------+-------~----------~--------------------~---------------------"----------/
-
/
- -
MODEL
-
INTERNAL MAINTENANCE SP£CJFICAlION, TAPE INl
BY
DATE
MAR 13, 1984
-t----,------f------+---------t----------------------t----.------------.--------S8
SHEE1" NC. •? 1
OF
lTR
P.C.NO.
APPROVED
DATE
APPD.
----~~--------~~---------------------~-------------"----------DWG.NO. A-0790B-60241-10
REVISIONS
SUPERSEDES
I
9320-2861 (5 1l2)
ER48
HEWLETT-PACKARD CO.
S.O
GLOSSARY of Signal
[hP.l
D/H'C6
and Other TerMs
NQ~es
The lower four bits of the Microprocessor's
AO-H thru A3-H:
address bus are decoded on the TIB to select one of the
ten registers which are used in the processor interface.
When A3 is at a logical low~ one of seven Status
registers May be read ot the concurrence of TIBS-L and
RD-L. One of three COMMand registers May be written when
both TIBS-L and WR-L ore active.
ACO through AC2: These three signals are the outputs of the
bit counter and will be decoded for various tiMing
signals that occur within each byte.
A8CLK-H: A COMposite signal Mode up of RCLK-H when REN-H is
active in a Read frOM Tape "ode, or BITC-H during on
active WCKEN-H in the Write to Tope Mode, or RWCB-H while
DHAF.N-H is asserted during Q DMA transfer in either
direction.
AS":
AlQorithMic Stat~
a sequential logic
of variable inputs
Chris Clare's book
Machines ".
Machine is the naMe used within HP for
circuit whose outputs are a function
with regard to their history. See
"Designing Logic SysteMS Using State
ATSPD-H: ';i.e conjunction of ST06-H being asserted while
ST07-H is low signifies that the HCD-7S Drive Module is
At the requested operating Spe~d.
BO-H through B7-H:
These eight signal lines are the outputs
of the counter which deter"ines the current byte location
within a page of the RAM buffer. They will be decoded
for the placeMent of various control and overhe.ad bytes
associated with each sector of Q DMA transfer and eoch
fraMe of Q Tape transfer.
B2-H:
Recognition of this Signal, one of the eight above,
allows the stote Mochine to watch data pass in four-byte
lncre~ents.
D3-H:
The state Machine Monitors this line, one of the eight
above, to count off data in eight-byte parcels.
~~----------'~------~---------r------------------~------------------------------'A 48-6116
sjb/RF
03-1S-83
MODEL
I
P.c.HO.
APPROVED
REVISIONS
.3~2861
45182)
ISTK.NO. 07908-60:241
INTERNAL MAINTENANCE SPECIFICATION, TAPE IN'
/
LTR
7908
DATE
MAR 13, 1984
BY
DATE
APPD.
SHEET NO.
SUPEFbEDES
DWG.NO.
72
OF
88
A-07908-b0241-10
ER48
HEWLET1--PACKARD
B6-H:
[hP.]
co.
A state Machine qualifier
at a t,1tte.
~or
counting
D/H'C6
sixt,-fo~r
bytes
Byte 249 is one of~the outputs decoded frOM the byte
counter while FO-H is deasserted. This signal is used to
generate the SOD-L pulse for the DMA interface at the
appropriate tiMe during a Write frOM the DMA to the TIB.
~249-L:
B250-L: Byte 250, also decoded frOM the byte counter whenever
FO-H is deasserted, serves two purposes. During DHA
Reads fro" the TIB, the SOD-L will be placed during this
byte, wherea~ during Q Write to the Tape, this byte
signifies the end of the sync field.
B253-L: Byte 253, locates the Track/FraMe-NuMber Byte of the
header during a data transfer when FO-H is low.
BIT2-L: A Marker for the third bit (counting 0 to 7) of each
byte, this locates SOD-L for DMA Reads and Modifies fraMe
nUMbers ~or writing the headers of the Error Correction
FraMes to the tape.
BIT4-L: Harks the fifth bit (nUMbered frOM 0) of each byte
and is used to place the SOD-L ~or a DMA Write operation.
8IT6-L: The seventh bit of each byte provides an edge that is
tiMed appropriately for writing into the RAM bu~fer.
The location of the last bit of each byte
the state Machine to count out the passage of
bytes and, when in the Write to Tape Mode, is
appropriate tiMes to insert the final one-bit
of the all-zeroes sync field.
~IT7-L:
BITe-H: Bit Clock occurs at 600-kHz for
tape.
writln~
is used by
single
used at
at the end
data to the
BLANK-H: When the Microprocessor requests a block of data to
be read ~roM the tape and the TIB finds that that block
contains no user data, a BLANK error status is returned
indicating that the read operation should not have been
perfor"ed on the block in question. This avoids the
confusion that would result if the data reMalning in ~he
RAM frOM Q previous read were to be transferred to the
DMA as i~ it CaMe frOM the current block.
A
48-6116
~jb/RF
03-15-83
MODEL
7908
lSTK. NO.
07908-60241
,-------------------
INTERNAL MAINTENANCE SPECIFICATION> TAPE INl
/
~;---------~r---~---~--------~------------------------~------------------------'-/
MAR 13, 1984
DATE
BY
LTR
P.c . NO.
~AOVED
REVISIONS
9320-2861 (5182)
DATE
73
OF
89
APPD.
SHEETNC.
SUPER:iEDES
DWG.NO. A-07908~60241-10
ER4B
(hpl
HEWLETT-PACKARD CO.
D/H:C6
------------------------
Block Enable~ cOMMand ~roM "icroprocessor raises high
o~ter key has been accepted so state Machine con read or
write.
BLKEN:
BSOD-L:
Buffered Start-o~-Data is the SUM of the signals for
the DMA read and write Modes decoded ~ro" appropriate bit
and byte locations.
BYTeK-H:
Byte Clock~ occurring with a 13-1/3 ~icrosecond
period, is used as a tiMer input to circuitry which
anticipates the preforMat of the tape during a Read
operation.
CACKN-H:
COMM(.lnd Acknowledge froM- the HCD-7S Drive Module
indicates readiness ~or another cOMMand or ~or the second
byte of a two-byte cOMMand frOM the TIB.
CLRO-L,CLR1-Lr
These two signals Clear the respective
contents o~ the two SERDES (Serial/Parallel) Registers
which interfoce the DMA and tape to the buf~er RAM.
They
are generated dir~ctly by the state Machine.
CLRX:
Shorthand notation
at the SOMe tiMe.
~or
referring to both CLRO and CLR1
CMDOO thru CMD07:
The COMMond Bus frOM the TIB to the Drive
Module is defined in the 3M COMpany dOCUMent "enTioned in
Section 2.3.1 abov~.
The COMMands sent to the drive on
this bus ordinarlly are generated by the Microprocessor
and passed through the TIB COMMand Register at Address 8,
but in SOMe cases where the lIB deterMines that the drive
should be halted More quickly than the ~icroprocessor May
be able to re~pond, the TI8 May issue a Stop COMMond (3D,
hexadeciMal) on its own.
CMDOK-H:
COMMand Okay is the conjunction of both CACKN and
SSTROBE beLnq deasserted, indicatinq that current Drive
Status is VQlid and that the driv~ is ready to accept
onother COMMand.
eRe:
A
48-6116
Industry st~ndard ahbreviation ~or Cyclic Redundancy
Code or Check.
The code used to de~ect errors in data
tranSMissions betw~en TIB and tape is CRC-fb, also known
a5 Bl-Sync, with the polyno~ial XA1b+XA1S+XA2+1.
sjb/RF
03-1S-A3
MODEL
7908
I
07908-6-0-2--4·1---------·--i
STK. NO.
MAINTENANCE SPECIFICATION, TAPE IN
1--+-------+-----;-------.----------------,-------------/
DATE
MAR 13, 1984
BY
I~TERNAL
/
LTR
P.C.NO.
APPROVED
REVISIONS
taJ20-2861 '5'82)
DATE
APPO.
SUPERSEDES
f
:=OA::7908:60:~~
ER48
H.EWLET1--PACKARD CO.
DlH:C6
(hi.]
CRCA-H: Cyclir-Redundancy-Check Results, 0 i~ good and 1 l~
in error, are reported for the firs~ two data fraMes
depending upon the odd/even condition of ~he frOMe
nUMber. If the fraMe nUMber is even) Fl l~w, then CRC
status ~or the first fraMe (CRCO) is shown here; if
currently selecting an odd fraMe, Fl high, then CRCA is
equivalent to the CRC status of the second ~raMe, CRC1.
CRCB-H: As for CRCA above, this bit reflects ~he status of
the CRC Results for the third or fourth data fraMes, bits
2 or 3 of the CRC Flag Register at Status Address 5,
depending upon the present value of F1, the
least-significant-bit of the fraMe counter.
CRCD-H: Data to the Cyclic-Redundancy-Code Generator/Checker
is derived frOM RDATA-H or WDDAT-H depending upon which
one of REN-H or WCKEN-H is asserted.
CRCK-H: CRe Results for the Key, referred to as fraMe 7, ore
reported to the state Machine via this bi~.
CRCL-H: CRC Latched is a MeMory bit that indicates whether or
not ony CRe error has occurred within the block being
read.
This is used during ,he Verify Mode so that all
errors within a block will be detected before the process
is interrupted.
CRCMR-H: CRe Master Reset allows the state Mochine to clear
the CRC Generator/Checker at the appropriate tiMe to
assure valid operation.
CRCNO-H: CRC Not Zero indicates that the CRe Generating and
Checking Register does not currently contaln all
(sixteen) zeroes,
If this occurs at the end of a fraMe
during a Read, it indicates that an error has been
detected.
CRCNF-H: eRe Not Found is a MeMory bi~ that indicates,
priMarily to the state Machine) that Q ualid Key has not
yet been found for the block currently being read.
If
the Key eRe ~hOW5 an error, on atteMpt will be Mode to
recover 0 valJd Block NUMber frOM the first four data
fraMes.
(Th~re is no point in looking further as the
data would show unrecoverable errors anyhow so the Block
NUMber would be irreleuant.)
I
I
~--~--~--~----~------·-----~I'
I
I--t----.--+-----+------+-----------..&..-------.----.---.----..
- A
48-6116
sjta/RF
03-15-83
MODEL
7908
STK.NO.
07908-60241
,
INTERNAL MAINTENANCE SPECIFICATION, TAPE
/
IN~
t---t------+---.--+------+--------------,-----------.--.- ._- --~•
/
-
-
BY
DATE
MAR 13 ..
1984
------Of
SS
i
.--,
SHEET !\IO. '75
f
APPD_
P.C.NO.
APPROVED
LTR
DATE
............-------L----L--.--.--f.---------t---.-----------~
REVISIONS
DWG.NO. A-07908-b0241-10 j.
SUPERSEDES
8320-2861 15182)
ER4B
HEWLETT-PACKARD CO.
~~
D/H"C6
CSO-L,CS1-L: Chip Selects to the lower and upper bu~fer RAMs
are generated directly by the state Machine. Ordinarily
only one o~ these will be active
BY
DATE
APPO.
SHEET NO.
SUPERSEDES
DWG. NO.
1 :~_4__ ___
I
1
A-07Y08-b0241 :"-U-J
86
OF
88
~
FR48
HEWLET1--PACKARD
co.
(hJJ
D/H:C6
VERR-H: Verify Error is output by the state "achine in
response to CRCL-H at the end of any block in which aCRe
error, whether in dQta or key Mark, was detected during Q
Verify operation. The drive will be sent Q Stop Motion
COMMand so that the Mi~roprocessor May eXQMine the CRC
bits before atteMpting Q retry.
VFY-l: V~rify N Blocks Mode has been selected when this line
is low.
WCKEN-H: Write Clock Enable is a state Machine output used to
select WClK-H as the source for ABCLK-H.
This Is done
not only durinq write to tape operations, but also during
periods when the state Machine uses the low frequency
(bOO-kHz) crystal-controlled WCL~-H as a tiMer in order
to anticipate the duration of gaps.
WDATA-H: Write Data is the cOMposite of sync ~ield, header,
user dato and CRe bytes as sent to the HFM encoder to be
converted before being written to the tape.
WDDAT-H: Write DData (the stuttering is necessary) is the
result of in~erting header bits and sync ~ield into the
data streoM token frOM the RAM. This is fed to the eRe
Gft.nerator.
WEN-H: Write Enable is Q control line. generated by the state
Machine to enable the write encoder during a write to
tflpe operation.
WR-L:
The Write pulse frOM the Microprocessor is used to
latch the contents of the data b~s into one of the three
COMMand registers on the TIB.
WRDATA-H: Write Data is the buffered version of WRDATB-H as
it appears at the ribbon cable going to the drive.
WRDATB-'H: Write Data (before being) BlJf'fered is the
MFM-encoded forM o~ WDATA-H which will be buffered and
sent to the drive to be written onto the tcp~.
A
48-6116
sjb/RF
O]-1S-fJ3
MODEL
7908
I_TK.NO.
I
07908-60241
~~--------~--··-----~-------------r---IN--T-£-R-N-A-L--M-A-I-N-l-E~.N~A-N-(-:E---S-\P-E--C-.,-IF--'I--CAT:rON~~~~t~
I
I
-
-
BY
DATE
MAR 13) 1984
I
t--~----'-------~------~-----------r---------------------------+----------------------------
LTR
P.C.NO.
APPROVED
REVISIONS
e320-2861 15/82)
DATE
APPD.
SHEET NO.
SUPERSEDES
OWG. NO.
87
OF
BS
A-07908-60241-=io-.
ER4B
HEWLETT-PACKARD CO.
D/H:C6
~P.l
ZCNT-H: Zero Count is a status bit set by the state MQchine
to indicate to the Microprocessor that either a Seek or a
Verify operation has terMinated by virtue of the eTC
block counter having been decreMented to zero at the
target block.
I
~~---------,--------r----------r-------------------r--------------------------'--'A 48-6116 sjb/RF 03-15-83
MODEL
/
p.e.HO.
APPROVED
REVISIONS
9320-2861 (5182)
STK. NO.
07908-60241
INTERNAL MAINTENANCE SPECIFICATION, TAPE INl
/
LTR
7908
DATE
MAR 13, 1984
BY
DATE
APPD.
SHEET NO.
SUPERSEDES
OWG.NO.
88
OF
~
S8
A-07908-60241-10
PAGE
DATE: 02/09/84
MRFD041R
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PAR.T NUMBERS
PART-NUMBER(S) :
07908-60241
07908-68241
07908-67241
DATE CODE :
F-2336
REFERENCE DESIGNATOR
CI00
CI05
CI10
C113
Cl15
C120
C125
C130
C135
c140
c145
C150
c160
c165
C170
C175
C180
c185
C205
C210
C215
C225
C230
C235
c240
c245
C249
C250
c255
c260
c265
c210
c275
C285
c300
c305
C310
C32'l
C325
c330
C340
C345
C350
c360
C365
c375
c380
07908-66241
COMPONENT PART
0160-5298
0160-5298
0160-5298
0160-5311
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-4002
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5313
DESCRIPl'IOH
CAP .OlUF 2~
CAP .OlUF 2~
CAP .OlUF 2~
CAP 330PF 5J
CAP .OlUF 2~
CAP .OlUF 2~
CAP .OlUF 2~
CAP .OlUF 20J
CAP .OlUF 2~
CAP .01UF 2~
CAP .OlUF 2~
CAP • 01UF 20J
CAP .OlUF 20J
CAP .OlUF 20J
CAP .22UF lOJ
CAP .01UF 2~
CAP .OlUF 20J
CAP .OlUF 20J
CAP .OlUF 20J
CAP .OlUF 2~
CAP .OlUF 2~
CAP .OlUF 20J
CAP • 01UF 20J
CAP .OlUF 20J
CAP .OlUF 20J
CAP .01UF 20J
CAP . 01UF 20J
CAP .OlUF 2~
CAP .01UF 20J
CAP .01UF 20J
CAP .OlUF 20J
CAP . 01UF 20J
CAP . 01UF 20J
CAP .01UF 2~
CAP.01UF 20J
CAP .OlUF 20J
CAP . 01UF 20J
CAP .01UF 2~
CAP . 01UF 20J
CAP .OlUF 20J
CAP . 01UF 20J
CAP . 01UF 20~
CAP .01UF 2~
CAP .01UF 2~
CAP .01UF 20J
CAP . 01UF 20J
CAP 10QOPF 5~
MATERIAL LIST CONTINUES ON NEXT PAGE • • •
1
PAGE 2
DATE: 02/09/84
MRFD047R
MATERIAL
LJ~
FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART NUMBERS
P~-NUMBER(S):
07908-602~1
07908-682~1
07908-672~1
DATE CODE:
F-2336
REFERENCE DESIGNATOR
C385
C390
C395
C397
C399
C412
C~20
C422
C424
C426
C42b
c432
c434
c438
c442
c444
c446
c4~8
c450
c452
c454
C456
c460
c462
c464
c466
c468
c470
c472
CR492
J1
L435
HP1
HP2
HP4
HP5
HP6
R118
R1?8
R132
R154
R158
R168
R188
R222
R248
R328
MATERIA! LIS'!"
07908-66241
COMPONENT PART
0160-5313
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0160-5298
0180-2207
0160-5298
0160-5298
0160-5298
0180-0374
0160-5298
0160-5298
0160-5298
0160-5316
0160-5298
0160-5312
0160-5311
0160-5312
0160-5298
0160-5316
0160-5310
0160-5298
0160-52~ .
0160-5310
1901-0033
1251-5647
9100-1788
07908-80241
7120-6830
1480-0116
1251-5595
0403-0456
1810-0280
1810-0275
0151-0401
0757-0401
1810-0275
0757-0467
0757-0467
1810-0280
1810-0275
1810-0275
CONTINUES ON NEXT
DESCRIPl'ION
1000PF 5~
.01UF 20J
.01UF 20~
.01UF 20J
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NTWK RES 9X10K
HT'WZ{ RES 9XlK
RES 100 1~.125
RES 100 1~.125
NTWK RES 9XIK
RES 121K 1~.125
RES 121K 1".125
In'WK RES 9X10K
HTWK RES 9XlK
HTWK RES 9XlK
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
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CAP
CAP
CAP
CAP
CAP
CAP
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PAGE . • •
5"
MRFDo41R
PAGE 3
DATE: 02/09/84
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART NUMBERS
PART-NUHBER(S) :
01908-60241
01908-68241
01908 -61241
DATE COlE :
F-2336
REFERENCE DESIGNATOR
R368
R386
R388
R418
R436
R458
R416
R418
R480
R482
R484
R490
R494
R498
Ul101
UlI02
0111
Ull11
01112
0112
U1121
U1122
0121
U122
U131
u141
u142
0152
U151
Ul62
U111
Ul12
U182
Ul91
Ul92
U2101
U2102
U211
U2111
U2112
U212
U2121
U2122
U2132
U221
U222
U232
01908-66241
COMPONENT PART
1810-0280
0698-3156
0698-3156
1810-0215
1810-0280
1810-0215
0698-3156
0698-3156
0698-3156
0698-3156
0157-0438
0157-0438
0157-041,1
0157-041,3
1816-1550
1820-0681
1820-2641
1820-1112
1820-2016
1820-2024
1820-1423
1820-1430
1820-2024
1820-1196
1820-202~
1820-2024
01908-89012
1820-1858
1620-1611
1820-1858
1820-20211
1820-1240
1820-1208
1820-11411
1820-1199
1820-1321
1820-0693
1820-1410
01908-89014
1820-1453
1820-1432
1820-1433
1820-1453
1820-0681
1820-1129
1820-1432
1820-1432
DESCRIPl'IOH
NTWK RES 9X10K
RES 14.71 IJ.125
RES 14.71 IJ.125
NTWK RES 9X1K
NTWK RES 9X10K
NTWK RES 9X1K
RES 14.11 IJ.125
RES 14.71 1J.125
RES 14.71 1J.125
RES 14.71 1J.125
RES 5.11K 1J.125
RES 5.11K IJ.125
RES 16.2K 1J.125
RES 11K 1~.125
IC-HEM 1K BIT
IC SN14s00H
IC SH14LS314N
IC SN14LS14N
IC 9401PC
IC SH14LS244N
IC SH14LS123N
IC-SN74LS161N
IC SN74LS244N
IC SN74LS174N
IC SH14LS244N
IC SN14LS244N
PROM TIB
IC SH14LS3111f
IC SH14s314H
IC SH14LS3111f
IC SN74LS244H
IC SN74s138H
IC SH14LS32N
IC SN14LS02N
IC SH14LS04H
IC SN74s85N
IC SH14s74N
IC SH14LS157H
PROM-MEMORY
IC SN14s163H
IC SH14LS163H
IC SN14LS164
IC SH74s163H
IC SN14s00N
IC SN14LS259H
IC SN14LS163H
IC SN74LS163N
MATERIAL LIST CONTIHUES ON NEXT PAGE • • •
PAGE
DATE: 02/09/84
HRFD047R
MATERIAL LIST FOR PC-BOARD COMPOSED OF MULTIPLE H-P PART NUMBERS
PART-NUMBER(S) :
07908-60241
07908-68241
07908-67241
DATE CODE:
F-2336
REFERENCE DESIGNATOR
0241
u242
U251
U252
u261
u262
U271
U272
U281
U282
U291
U292
U3101
U3102
U311
U3111
U3112
U312
U3121
U3122
U3131
U3132
U321
U322
U331
U332
U341
U342
U351
U352
U361
U362
U371
U381
U382
U391
U392
U4101
U4111
U4112
U422
u431
u432
'J441
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u451
u452
07908-66241
COMPONENT PART
07908-89073
1820-1240
1820-1858
1820-1216
1820-1858
1820-1206
1820-1197
1820-0694
1820-1210
1820-1199
1820-0688
1820-0693
1820-1208
1820-1197
1820-1302
1820-1204
1820-1210
1820-1730
1820-0694
1820-1430
1820-1433
1820-1282
1820-1302
1820-1112
1820-1302
1820-1201
1820-1302
1820-1112
1820-1430
1820-1430
1820-1430
1818-1611
1820-0693
1820-1144
1820-3104
1820-1423
1820-1199
1820-1112
1826-0519
1820-2369
1820-2015
1820-1981
1820-1216
1820-1987
1820-1216
1820-1568
1820-1633
DESCRIPl'ION
PRCJt1 TIB
IC SN74s138N
IC SN74LS377N
IC SN74LS138N
IC SN74LS377N
IC Sli74LS2TH
IC Sli74LSOOH
IC Sli74S86N
IC SN14LS5111
IC SH74LS04N
IC Sli74s20N
IC SM74S74N
IC Sli74LS32H
IC SJf74LSOOH
IC SN14s2511l
IC Slf74LS20N
IC SN14LS51N
IC SN74LS273N
IC Slf74S86N
IC-SN14LS161N
IC SN14LS164
IC SN14LS109N
IC SN74s2511l
IC SH74LS74H
IC SN74s2511l
IC SH74LS08H
IC SN748251N
IC Slf74LS741f
IC-SN14LS161N
IC-SN14LS161N
IC-SN14LS161N
IC-MEMORY
IC SH74S74N
IC SH14LS02H
Ie 74ALS299
IC SN14LS123N
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TL 071
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Ie SN74LS245N
Ie AM74LS299N
Ie Slf14LS138N
Ie AM74LS299N
Ie SN14LS138N
IC SN14LS125N
Ie SN74S240N
MATERIAL LIST CONTINUES ON NEXT PAGE . • •
4
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1IRFD047R
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05/16/~~
MATERIAL LIST FOR PC-BOARI CC»fPOSED OF MULTIPLE B-P PART IlUMBERS
PART-IfUMBER(S):
07908-60013
07908 -68013
07908 -69013
DATE CODE : £ - 22~O
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drawing whiCh cannot conveniently be re-issued completely atter
each change. When !Daking a change. list for each page all beforeand-after numbers (within reason; use judgement. and use
"extensive" revision note if loss of past history is tolerable, or
retype complete page) and associate with each a sTaobol made up of
the chance letter and a serial subscript to appear here and on
the page involved (there enclosed in a circle, triangle, or other
attention-letting outline).
(L430)
I
111M
LTRI
REVISIONS
I DATE I INIT IF
---1--------------------------------------------------1--------1-------1-AS ISSUED PER 1>(;0 48-6074
A
112/16/82 clr/ML M
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--------------------------1--+---------+-------+---------+------------------+----------------.. ----------I I
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1--+---------+-------+---------+-----------------------+-----------------------1
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IDATE FEB 13, 1984
I
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C., I APPR I DATE
IAPPD
I SHEET , 1 OF 21
I
,--+---------+-------+---------+-----------------------+-----------------------1
I
REVISIONS
ISUPERSEDES
Iowa, A-07908-60340-2 1
--+---------+-------~---------+------------------+-
IA 148-6074
Iclrt-,- 112-16-82 'MODEL 7908
lS'fK' 07908-60340
+----------------------------------------------------------------------------~-+
~..,-----------------"-----------'--------------HEW LET T - PAC K
AnD
C O.
I
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/
/
hp /
/
ER48 DH:c6/50A
-----------------------------+
HCD-75 DRIVE MODULE INTERFACE ERS
(07908-60140)
GENERAL DESCRIPTION
This document describes the BCD75 (3M Company Product No.)
cartridge tape drive interface to our Controller. A brief
description of the OC600HC preformatted cartridge used by
the drive is also included.
The Controller referenced in this document consists of the
following elements:
MICROPROCESSOR Assy
(or equivalent)
DMA Assy
(or equivalent)
'?-'
TI B As sy
The cartridge il pre-recorded by a full 1:"idth recording
device which writes completely across th,! full one quarter
inch width ot the tape. The 600 foot tal~ length is divided
into three areas. There is a unique "Beginning ot Tape"
(BOT) pattern area at the front of tape, a unique "End of
Tape" (EDT) pattern area at the end of tape and a data area
for user recording. The data area is divided into 4114
erased areas which are separated by identifying key marks.
It is important that the BOT, EDT and short key recordings
should not be erased in user recording. The 4114 erase~
areas between keys are each approximately 1.75 inches l,'ng.
Four thousand ninety six of these areas can be recorded ~V
the user on 16 tracks across the width ot the tape. A
movable write-read head on the drive will select the desired
track. Fifteen areas are reserved for system diagnostics
and usage.
--+---------+------."+---------+------------------+---------------------------ISTK , 01908-60340
1--+---------+--------+---------+------------------+----------------------------1
I I
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I HCD-75 DMI ERS
1
1--+---------+-------+---------+-----------------------+-----------------------1
I •
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t
'BY
lOME FEB 13, 1984
I
I ---------+-------+---------+-----------------------+-----------------------1
'~P.C. I I APPR I DATE
IAPPD
1SHEET ,
2 OF 21
1
1--+---------+-------+---------+-----------------------+-----------------------1
1
REVIS I mlS
ISUPERSElJES
IDWG 'A-01908-60340-2
I
+------------------------------------------------------------------------------+
IA 'q8-6014 Iclr/ML 112-16-82 jHODEL 7908
+.------------------------------------------B E W LET T - PAC K A R D C O.
GENERAL DESCRIPTION
/
I
/ hp I
/
/
ER48 DH:c6/50A
-----------------------------+
(Continued)
Serpentive recording is used. This method writes and
reads forward on even numbered tracks, and reverse on odd
DUIIlbered tracks ( the 1st track is 0). This .ethod saves
rewind times by using the 600 feet of recording area
in a continuous flow.
!he keys identify the record areas in ascending numerical
order from BOT. Key zero is near BOT. Key 4112 is near
EOT.
learly gapless recording can be employed by the user.
Small gaps must be provided to inhibit the possibility
of speed variations accidently erasing the k!ys. A
read operation is always required before writing occurs.
The recording zone must first be identified.
The drive module is cabled with a 50 pin tlat cable.
10 termination resistors are used, but tri-state
drivers will function v~ll over a maximum 15-toot cable
length. The Controller has all its drivers in the
constant enable mode; the drive must not see the
tri-state condition. It must see only one ot the two
T.T.L. levels.
After a power up reset. the drive will wait tor cartridge
insertion and then execute an automatic cartridge load
sequence. This sequence starts at the end of tape area
and takes about two minutes to execute. The purpose is
to condition the cartridge, set the electronic gain
control, and locate a positive reference tor track location.
After this sequence, the drive will "park" at BOT and wait
tor commands.
J
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1--+---------+-------+---------+------------------+---------------------------IA 148-6074 I clr/ML 112-16-82 IMODEL 7908
ISTK , 07908-60:340
1--+---------+-------+---------+------------------+------------------------~--1
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I BCD-75 DMI ERS
I I
1--+---------+-------+---------+-----------------------+---------.-------------I I
I
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IBY
IDATE FEB 13, 1984
1--+---------+- -----+---------+-----------------------~----------------------ILTI P.C.' I APPR 1 DATE
IAPPD
ISHEET I
3 OF 21
1--+---------+-------+---------+-----------------------+---------..
------------I
REVISIONS
I SUPERSEDES
IDWG , A-01908-60340-2
+------------------------------------------------------------------------------+
~
·------------------------------------------ /
/~I
B E W LET T - PAC K A R D C O.
/
/
/
ER48 DH:c6/50A
-----------------------------+
BCD-75 DRIVE SPECIFICATIONS
MEDIA:
CC600HC or nc615HC Data Cartridge
POWER SUPPLY:
NOMINAL CtrnRENT (AMPS)
IDLE
+5VDC -2I/+5J
+12VOC
-5~/+1~
RUNNING
1.5
SURGE
1.5
0.75·
0.13
3.5 (45 MS,@ 60 ips)
1.0 •
3.5 (80 ms,@ 90 ips)
1.0 STEPPING·
• ADDITIVE DEPENDING UPON
OPERATIONS
TYPI CAL POWER:
9W IDLE
l8w RUNNING
,
WEIGHT:
6
SERVO:
60 ips +/90 ips +/-
I
I
I
POUNDS
3~
3~
forward-reverse. 75 mS ramp.
forward-reverse. 100 mS ramp.
I
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"
1--+---------+-------+---------+------------------+---------------------------IA 148-60114 I clr/HL 112-16-82 IHODEL 7908
I STK , 07908-60340
,--+---------+--------+---------+------------------+----------------------------1
I I
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I
,--+---------+--------+---------+-----------------------+-----------------------1
I 1
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IBY
IDATE lEB 13, 1984
1
..+---------+-----.--+---------+-----------------------+-----------------------,
I P.C.'
1 APPR I DATE
IAPPD
I SHEET ,
4 OF
21
I
~+---------+-----.--+---------+-----------------------+-----------------------1
I
REVISIONS
'SUPERSEDES
Iowa 'A-07908-6034o-2
I
+-----------------_.------------------------------------------------------------+
.------------------------------------------- /
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B E W LET T - PAC K A R D
C O.
/
/ hp /
HCD-75 DRIVE SPECIFICATIONS
/
ER48 DH:C6/50A
/ -----------------------------+
(Continued)
0.00078 inch head movement per step.
HEAD STEPPER:
19 steps per track. driven at 100 steps
per second.
16 tracks on 1/4 inch tape.
1
HEAD:
Single track, ferrite construction.
RECORDING METHOD:
Serial M.F .M. 10,000 t .r.p. i.
60 Lp.s.
TRANSFER RATE:
60
C/J\1RIDGE INTERLOCK:
Locked when head is on tape.
max
at
K bits per second (exclusive ot gaps).
Released when head is at its 10west
mechanical travel.
-~---------+-------+---------+------~-----------+----------------------------
IA 148-6074
Iclr/HL 112-16-82 IMODEL 7908
ISTK , 01908-60340
1--+---------+-------+---------+------------------+---------------------------I I
I
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I HCD-75 DHI ERS
1--+---------+-------+---------+-----------------------+-----------------------1
IBY
IDATE FEB 13, 1984
I
I-~---------+-------+---------+-----------------------+-----------------------1
J
1
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ILTI P.C.' I APPR
J
I DATE
IAFPD
ISHEET ,
5 OF 21
1
1--+---------+-------+---------+-----------------------+-----------------------1
I
REVISIONS
1SUPERSEDES
IDWG 'A-()7908-6034o-2 1
+---------------------------------------------------------------_._-------------+
+--------------..:---------------------------- /
B E W LET T - PAC K A R D C O.
/
/ hp /
/
/ --
HCD-75 DRIVE SPECIFICATIONS
ER48 DH:c6/50A
.-.-----------------------+
(Continued)
OPERATION ENVIRONMENT:
Temperature:
Relative Humidity:
Max Wet Bulb Temp:
41 degrees
degrees
(5 degrees
degrees
Fahrenheit to 113
Fahrenheit
Centigrade to 45
Centigrade)
2~
Don-condensing
to
8~
79 degrees
Fahrefu~eit
(26 degrees Centigrade)
"
STORAGE/TRANSPORTATION ENVIRONMENT:
Temperature:
-40 degrees Fahrenheit to 149
degrees Fahrenheit
(-40 degrees Centigrade to 65
degrees Centigrade)
MEAN TIME BETWEEN' FAI LURE (M. T . B. r . ) :
Greater than 10,000 hours
--+---------+-------+---------+------------------+----------------------------1
Iclr/ML 112-16-82 IHODEL 1908
ISTK , 01908-60340
1
1--+---------+-------+---------+------------------+----------------------------1
1 I
I
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I HCD-75 OMI ERS
I
1--+---------+-------+---------+-----------------------+-----------------------1
1 I
1
I
IBY
IDATE FEB 13, 1984
I
. --+------ ---+-- -----+--- --- ---+ -- .------ --------------+-.., ------- --- ---- -------1
IA 1~-6014
, 1'1 P.C.' 1 APPR I DATE IAPPD
ISHEET , 6 OF 21
I
~-+---------+-------+---------+-----------------------+-----------------------1
1
~SIONS
I~JPERSEDES
IDWG 'A-01908-60340-2 1
+------------------------------------------------------------------------------+
+------------------------------------------- /
I
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B E W LET T - PAC K A R D C O.
/
HCD-75 DRIVE SPECIFICATIONS
/
ER48 DB:c6/50A
/ -------------~---------------+
(Continued)
MOHINAL LIFETIME:
Drive M?tor:
Greater tb~ 15,000-600 ft.
cartridge cycles
Head:
Greater than 50,000,600 ft.
cartridge cycles
Stepper Motor:
Greater than 15,000,000 steps.
MATIMG INTERFACE CONNECTOR:
3M 3425
Socket Connector
(50 Contacts)
3M 3469/50 Flat Cable, 15 Ft. Max.
HATIMG POWER CONNECTOR:
HOLEX 09-50-3041, housing and three,
HOLEX 2 GL pins.
Minimum 16 GA. wire, 4 ft. max.
MATIMG INDICATOR CONNECTOR:
MOLEX 22-01-2085, housing and eight
HOLEX 08-56-0110, pins
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1--+---------+-------+---------+------------------+--------------·--------------1
IA 148-6014 Iclr/ML 112-16-82 IHODEL 7908
ISTK , 07908-60340
1
.--+---------+-------+---------+------------------+-------------_._-------------,
I
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I
I--+---------+-------+---------+---------------------~-+-----------------------1
I
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fBY
'DATE
FEB
13, 1984
1
,--+---------+-------+---------+-----------------------+-----------------------,
ILTI P.C.' I APPR I DATE
IAPPD
I SHEET ,
7 OF 21
I
,--+---------+-------+---------+-----------------------+-----------------------1
I
REVISIONS
1SUPERSEDES
IOWG 'A-OY908-60340-2 I
+------------------------------------------------------------------------------+
~
.----------------------------------------- /
I_I
B E W LET T - PAC K A R D C O.
/
I
/
ER48 DH:06/50A
-----------------------------+
BCD-75 DRIVE INTERFACE
COMMAND LINES CHD07 through CMDOO
The eight command lines (07m.s.b.) convey the command
which the selected drive is to execute. These lines'
are T. T. L. high true for a binary one. They must
be stable on the leading edge of the minimum one
microsecond long CSTROBE pulse.
CSTROBE Line
The command strobe line is a minimum one microsecond
long T.T.L. positive going pulse which the Controller
sends at command transfer. The command data shall be
stable on the leading positive edge. The drive will
accept the command on the negative going trailing edge.
"'-'CACKI
Line
The command acknowledge is a positive going T.T.L. pulse
which is used to synchronize command transfers. The
leading positive edge ot command acknowledge will occur
on the trailing edge of command strobe. The Controller
must wait for the trailing negative going edge ot command
acknowledge before sending the second byte ot a command
or betore testing status of execution tor the present
command.
,1--+---------+-------+---------+------------------+----------------------------1
IA 148-6074
Iclr/ML 112-16-82 IHODEL 7908
I·"'....... P.C.'
1
ISTK , 07908-60)40
I
1--+---------+-------+---------+------------------+----------------------------1
! 1
1
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1
1--+---------+-------+---------+-----------------------+-----------------------1
1 1
1
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iDATE FEB 13, 1984
1
I- "---------+-------+---------+-----------------------+-----------------------1
APPR
I
DATE
IAPPD
ISHEET
,
8
OF
21
I
1--+---------+-------+---------+-----------------------+-~---------------------I
1
REVISIONS
ISUPERSEDES
IDWG 'A-07908-6034o-2 I
+------------------------------------------------------------------------------+
+------------------------------------------- I I hp
B E WLET T - PAC K A R D C O.
I
HCD-15 DRIVE INTERFACE
I
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ER48 DB:c6/50A
-----------------------------+
(Continued)
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STATUS LINES STOT through STOO
The eight status lines (07m.s.b.) convey primary and
secondary status as well as memory read data from the
selected drive. These lines are T.T.L. high true for
a binary one.
Normally these lines have primary status in real time
and ST07 is a O. They can then be sensed at any time
without acknowledge. If a drive fault condition
occurs, secondary status will appear and STOT will be
a 1. Secondary status .ust be ackno~ledged. It data
is requested, the lines must be sampled and acknowledged
only after SSTROBE goes low.
STROBE Line
The statu. strobe line is a T.T.L. compatible level
~ich i. used as a drive busy tlag.
Status strobe
must be low betore a command ~ill be accepted by a
selected drive. ~en a command is transferred, status
strobe will go high betore the trailinc edge of command
acknowledge. Status .trobe will remain high during
execution ot the command. Status strobe will return low
only after command execution is over or when a drive fault
has occurred during the execution ot the command. For the
four motion commands 31, 34, 37, 3A, execution is over
atter the drive has achieved the requested operating speed.
--+---------+-------+---------+------------------+-------------_·_-------------1
Iclr~L 112-16-82 IMODEL 1908
ISTK , 0790e-60340
I
1--+---------+-------+---------+------------------+------------·----------------1
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1--+---------+-------+---------+-----------------------+-----------------------1
I I
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IDg"£ FEB 13, 1984
I
1--+---------+-------+---------+-----------------------+-----------------------1
ILTI P.C.' I APPR I DATE
IAPPD
ISHEET ,
9 OF 21
I
1--+---------+-------+---------+-----------------------+-----------------------1
JA 148-6014
I
REVISIONS
I SUPERSEDES
IDWG 'A-Oir908-6o340-2 1
+----------- -.. _----- --- ---- ----- ------------------------- ----------- --- --- ------+
+~
~
-----------------'-"':-------------------- /
I~I
HEW LET T - PAC K A R D C o.
I
BCD-15 DRIVE INTERFACE
I
ER48 DH:c6/50A
/
-----------------------------+
(Continued)
SACKN Line
The status acknowledge line ia a T.T.L. compatible pulse
which is used by the Controller to acknowledge certain
drive status transfers. When issued 9 it is a po~itive
pulse of one microsecond minimum duration. The Co~tro11er
need only acknowledge these status transfers:
~s
a)
Secondary status drive fault transfers
by ST01
1.
b)
Memory read data transfers upon completion of a
command.
=
indicated
16
It should be noted that drive fault conditions are not tested
during (b) above so that ST07 = 1 will not be confused with
secondary status. The drive will always revert back to primary
·~atus after acknowledge.
SELECT LINES SELl AND SELD
The select lines (l•.•. b.) are T.T.L. high true for a
binary one. They are used to select one of four drives
tor use. They must be stable for all data, status or
command transfers. Only one drive at a time can be
on the interface.
--+---------+-------+---------+------------------+----------------------------1
Ic1r/ML 112-16-82 IMODEL 7908
1~f.K I 07908-60340
I
1--+---------+-------+---------+------------------+---------------- ------------1
I I
1
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I
1--+---------+-------+---------+-----------------------+-----------------------1
I I
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IBY
IDATE FEB 139 1984
I
1--------+-------+---------+-----------------------+-----------------------1
ILT~. C., I APPR I DATE I APPD
I SHEET I 10 OF 21
I
1--+---------+-------+---------+-----------------------+-----------------------1
I
REVISIONS
I SUPERSEDES
IDwa I A-07908-60340-2 1
IA 148-6074
~------------------------------------------------------------------------------+
+------------------------------------------- /
I
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H E V LET T - PAC K A R D
C O.
/
HCD-15 DRIVE INTERFACE
/
/ ER48 DH:c6/50A
-----------------------------+
Ic----------------User Space----------------->I<------->I
spare table
error log •
diag.blocks
(Including Spares)
Linus EftS
Page 2
use logs
3.0
OPERATOR IHTEFACTIOH
3.1
Controls and Indicators
UNLOAD button - This button is lIounted on the front panel ot
the tape mechanism and provides the user a way of indicating to
the controller that the tape should be unloaded. When the
controller senses that the button has been depressed it will:
a) During an autoload - stop the autoload and UNLOAD.
b) During a SAVE or RESTORE operation - temporarily stop those
operations. If it is then pushed a second tille and while
the busy light is flickering, an UNLOAD will occur. If it
is not pushed in 5 sec., the SAVE or RES will resu.e.
c) During any other active operation
invoke the unload
sequence (below).
~e unload sequence tirst requests release from the host system
wben release is granted, the controller upda~es the error logs
(near the tront of tape), rewinds the tape to "End ot Tape
(EOT), updates the Use log, and unlocks the cartridge with an
audible buzz.
II
EJECT lever - This Ilide lever eJects the c&rtridge out ot the
drive .. chanis•• A mechanical interlock prevents its actutation
unless the cartridge has "unloaded" as described above.
·SAVE button - Thil button i. located behind the
tront panel.
It is intended for use by lervice personnel and users 1Ihen the
host .ystem is down and a copy of the disc is desired. Backup
il normal!y done with system comaands.
Pushing the SAVE button will initiate a tull volume transter of
the disc '. contentl to the in-place tape cartridce. The
transter will start troll logical block zero on the dilc and
tape, and proceed until the disc volume has been ca.pletely
transtered, or end ot volume occurs on the tape. After the last
block i. written, a tile mark il added. Misaatched volume lizes
between the dilc and tape are allowed within the above
definition.
The 791~ will, after the first tape, prompt the user to load
another tape. With this second tape the controller restarts the
cop,y trom WOere it left off on the disc. The address ot the
first disc sector .tored on each tape i . recorded in a tape
maintenance block.
The SAVE operation starts with a request tor release from the
hOlt. After release has been ,ranted the busy light is
flickered. It the button is pushed again within 5 seconds, the
controller will start copying the disc data onto the tape. If
no button or the wrong button i~ pushed, the subsystem returns
to its idle state. If a data error is encountered on the disc,
the best guess i. sent to the tape, and the SAVE continues to
completion. Ho~ever, the tape is not unloaded and the ~lash~
busy light indicates a fault. Pushing the unload button no~,
unloads the cartridge and clears the
fault
conditions.
Unreadable keys on the tape are marked in the spare table and
skipped. The SAVE continues to conclusion with no fault
indicated, and the cartridge unloaded. If a hard~re fault
Linus ERS
Page 3
interupts the SAVE, the busy lipt tlashes (it possible) and
the tape is stopped. At the completion of the tirst tape on the
7914 the busy LED is flashed alternately fast and slow to
prompt the user tor another tape. It end ot volume is reached
on the disc a tile mark is written on the tape and the tape
unload sequence is invoked. It the end of the tape (second tape
on the 7914) is encountered first the tape unload sequence onlY
is inYOked.
-RES"l'(fiE button - This button is also Ilounted behind the front
panel. It functions the same as SAVE but in reverse (tape to
disc). Additionally. RESTORE will stop at tile marks and blank
blocks. Data and hardware faults are handled analogously to
SAVE. Tbe 7914 uses the disc address written on the tape for
restoration of both tapes.
BUSY indicator -
This LED visible from the front panel
indicates that a tape operation is in progress when it is lit.
Durinc Save and RES sequences this LED is flickered (B/sec. )
while waiting for a button, tlashed (l/sec) to indicate a
tault, and strobed while tlickering to indicate that the 7914
is waiting for a second tape.
WRITE PROTECT indicator - when lit this LED. visible trom the
tront panel. indicates that the cartridge is write protected,
and t.hat write. to the tape are not allowed. When write
protected, the controller cannot 2odit,y the system block. on a
tape so sparing t logging ot errors. and tallYing og total tape
use are disabled.
*These switches are onlY used on the shared controller version.
of Linus.
3.2
Cartridge Loading
The loading sequence is initiated wbenever a cartridge i.
plugged in. The tape is Iloved to the beginning ot tape (BOT).
the drive tests itselt. then calibrates itselt
to
the
particular cartridge in the .echanism. This process take. about
two ainut.es tor the "Lit. or about 55 seconds tor the "s"
cartridge. At the conclusion ot this. it is ready to be
accessed ~ the host.
3.3
Cartridge Unloading
The Wlload sequence (described under the UJlLOAD button) has to
be executed to remove a cartridge from the drive. It can take
up to 80 seconds to rewi:1d the tape to EOT for a tiL" cartridge,
and 20 seconds tor an .. s .. cartridge.
Linus ERS
Page 4
1t.0
HOST SYSTEM llTERACTIOH
1t.1
Functional Description or Ca.mand Sequence
To acc.as the tape, a atartinc block address,
burst size and
transrer length must be specitied. The ~'sical block size is
1021& bytes ,. and up to tour blocks .ay be buffered by the
controller. 'lbe starting address is converted internally to a
tvo dilMnsional key and track address. A locate and read (or
writ~ or verity) command initiates the shortest seek
to this
key and track location. Seek t~es are 195 .sec per track,
about 100 .sec accel. and decel. tiaes per seek, plus about 20
.sec per key traversed. (ie, to 10 trom block 0 to block ~081
takes 80 seconds. To Co from Block 0 to Block 8111 takes about
390 a.ec.). Seeks can take relatively long periods or time,
especialq it done without regard to the inherent personali ty
of the tape.
e&ce the target address il reached, writes, reads and verities
are ~enced in auch the lame aanner as with dilc.. If the
tranlaction overflows a track, auto seeks to the Dext track are
done. Retries are al.o accomodated during reads and veririel.
Verities can be done at the conclusion ot a write transter.
They abould not in general be done on a block by block basi.,
however, as this results in extreaely poor perforaance, and
excesli"e wear on the drive and cartridp.
1t.2
LiDu. File H'U'k Capability
3M .eU. a controller tor a .tand alone Lin'.1 conticuration
which ~le.ents tile .ark capability. The 3M contr~ller ule.
data block headers to record tile aark. which are reque.ted b.r
the uler via a write tile mark coaand. In order to allow BP
controllers to be cOlllp&tible with 3M tapes. an equivalent
function vill be ~l. .ented on Linus.
The rule. tor bandl~ tile markl involve a ne. write tile aark
ca.mand, and .odification to locate and read
to
allow
termination ot a transfer when a tile .ark is encountered. rile
aark. are not involved in tape rositioning prior to a read,
write, or verity command. Mo akip tile mark cOllUlland£ are
imple"ntecl.
Whenever a tile mark i. encountered during a read, the data
transfer il tenninated. The End ot File indication in the
atatul request .. ssage becomes asserted when the bost attempt.
to access the byte arter tbe last byte in a tile. Whenever Eo..
il encountered, a aessage tenainator byte, "01",. is aent to the
host. !be contents of this byte are not part of tbe r&quested
data.
Unless a tile aark is encountered, the length of the execution
lies sage i. deterained by the current value of the length
parameter. It a data transter ends on the last byte ot a file,
the Ear indication is .aved until the host attempt. to read the
next byte. In this case the message terminator byte i8 sent in
a single byte execution message. If an EOF is encountered in
Linus ERS
Page 5
the lIiddle of a data transfer, that transfer is terminated and
EOF occurs immediately. In this case the message te~inator
~ is appended
to the data aessage. The length ot the
execution message is never longer than the length parameter
specification. Burst .ode cperation is independent of the rules
involving file marks.
~.3
Defect Handling
'1'vo types of media errors are possible with the Linus tape : an
key for a given block and sn unrecoverable data
error. Bad keys are relatively common (0
10 per ItL"
cartridge) and can be detected on a virgin tape during any
operation. With the internal error correction, uncorrectable
data errors are rather infrequent «1 in 10 "L" cartridges) but
can only be detected during read and verify operations. To ease
the handling of errors the Linus controller sets aside one
block in 512 as a spare (total of 32 blocks on the .. s.. tape and
128 on the ilL "tape) • These blocks are not in the users
addressing space and are only used to replace bad blocks.
~dable
TWo .ethod. of using the spare blocks are provided by the Linu.
controller. In the first aethod, refered to h~re as skip
sparing, a bad block is spared by adding its address to a table
ot blocks to be skipped and relloving the next available spare
troll the same table. This type of sparing re.ults in minillal
latene,y but the addresses ot the blocks between the bad block
and its spare are altered. In the second .ethod, Jump spar inc ,
the bad block is directlr replaced bf the closest, by seek
tille, ava ilable spare. An.y tuture rete renee to the block
,enerates a seek ~o its spare requirinc on the average a
latene,y ot 2.5 seconds to cet to it and nearly the .ame tim. to
resuae with the next sQquential block. This .ethod, however,
does not alter the address of other blocks and is safe for us.
when needed data resid~H beyond the bad block. In the special
ca.e when a skip
is asked for but DO spar. blocks are
available beyon~ ~~e bad block. Jump spar. is substituted for
the skir. Ther,. is a 1111i t of 32 Jump spares for IUlJ Linus
tape.
.par.
Sparira is invoked by the host sending a Spare
~
...
Block command,
with a parameter byte indicating the method, or by the host
wri1:iDg to a known bad block after enabling Auto Sparing via
·..ne Set Device Specitic Options command. Each spare operation
requires the controller to rewrite a sparing information block
near BOT, this vill be done at the end of any transaction
causing the spare but before status is returned.
ColBlllaDds Supported by Linus
~.".1
Locate and Write
Ll:"luS will execute the locate and write command in the same
aanner as the disc. Complete disc operations .~y be
executed in parallel with the 'locate' portion ot a Linus
transaction, as described under parallel operations (to be
Linus ERS
Page 6
impleme;.~ted at a later date). Also Dote the
in section 4.4.
After completion
of a
write operation,
sparing
the
tape
rules
will
be repositioned to a point in front of the
next block to be written. This way the seek required in
automa~icall.y
preparation for a sequential write will take place in
parallel with the receiving and decoding of the next
cOllUDand •
Locate and Read
The read and cold load read operations are executed in the
same manner as the disc, with the following exce~tions.
File marks will be treated as mentioned earlier.
The user will be able to configure the drive to take
advantage of character count capability during reads. This
is necessar.y for 3M controller compatability. If character
counts are ignored, partial blocks will be padded with O's
to their full length during a read operation. If the
character count function is enabled, the controller viII
skip the unfilled part of a partially written block, and
proceed with the next block. The default is to ignore this
powerful capability.
Upon completion of a read co.-and, the controller will
instruct the tape drive to read the next block, in case a
.equential read command should tollow. Thi. is done in
parallel with other controller activity, and does Dot
impact the controller'. interaction with the host.
Attempting to read a block which
will terminate the transfer with
error.
has never been written
a No Data Found media
Veri f'I COlIIIDand
The verity command on LiDu~ operates like the disc verit,y
command.
The
host
should
cons ider
the
following
characteristics Mhen using this command:
1 - The command will verity n logical blocks where D equals
the transfer length divided by 1024. There is no
adjustment for empty, partial or filemark blocks within
this range.
2 - Verity will terminate ~ftediately on an unrecoverable
data error unless the bad block has been spared.
3 - Verify will not terminate on a file mark.
Linus ERS
Page 1
Cop)' Data
Copy data is described in the CS tsO (Feb 1981) ref.ranee
manual. '!'be followin& comments should be noted when using
this cOJllllland:
:1 - When Linus is the .ource unit and a End of
is encountered thft
status is reported.
File (EOF)
Copy transaction stops and EOF
2 - If an unwritten l,lock is encountered while Linus is the
source device, the '~ransfer will be terminated with a
No lAta Found aecUa error.
3 - The full 7914 dilC iIIa,e
~ incle tape cartl idge.
~
cannot be backed up on a
- The command is net executable on the
version of the 7911, 7912 and i:J14.
~.4.2 Compl~entary
dual
controller
Co.mands
!he followiaa complimentar,v commands are implemented:
SET
SET
Block Address
Block Displacement
LenC"th
Burst
Retry Tille
Status Mask
Device specific Options
SIr
SET
SET
SIT
SIr
Allot this commands function in exactly the same .anner .s
described in the CS 80 reference .anu.l with the tollowiDi
extension:
S.t Device Specitic Options
C,R
:OOll1000: :OOOOOASC:
C
C
:I:
:I:
0:
1:
A :I: 0:
A = 1:
S
S
= 0:
=1:
Disable character count capability.
Enable character count capability.
Auto sparing disabled.
Auto sparing enabled.
Auto spare invo.k.s Jump Sparing.
Auto spare invokes Skip Sparing.
7be C bit in this complementary command configures
the
controller to utilize the tape drive's
character count
capablilty. This does not impact wri te operations. Character
counts are always written in block headers. It this function is
disabled tor a read operation, partially filled blocks will be
padded with O's during a read. It the function is enabled, onlv
the filled portions ot blocks will be sent to the host. The
Linus EftS
Page 8
Character count will be used to cause Linus to skip to the next
block when all of the user data in a given block has been sent •
• 0 d~ data is synthesized.
When the A bit is set the Linus controller
has permission to
bad blocks encountered while writing user blocks. Bad
b10cks are limited to those ~ith an unreadable key and any
b10cks previously put in the error log. If the S bit is set
Auto sparing will use the skip rather than the jump method of
s~ing. The skip method is recommended wrien the user doesn't
care about any d.ta which may reside beyond the current target
address.
s~ ~
4.4.3
General Co~~ands
Describe
The format of the describe message does not require
modification for Linus. The number of user blocks given by
describe reflect the size of the current cartridge loaded
in the drive. It will be zero when no cartridge is loaded,
16352 for a ..s .. cartridge with spares, and 65408 tor a "L"
cartridge with spares. A cartridge which has never been
written to or has been initialized to have no spares would
be describes as having 16384 or 65536 blocks.
Releas., Release Denied
The Linus controller requests
events:
release
for
the
tollo~ing
1 - A tape cartridge
finishes auto load. Release is
required to obtain controller relource. to execute
Linus Selt Test and Table initialization routine •.
2 - The operator
pushes the Store, Restore, Unload or
Selftelt buttons. Release is of course required before
any ot these actons can be taken as
controller
resources are needed and the host· may have tile or
director,y maintenance to pertorm betor. allowing such
drastic actions.
3 - !he run
ti~e error table in the controller
fills. The
controller then requests release tor Maintenance so it
can post the new errors.
!be host grants or denies release ~ith the appropriate
co~d. It a controller defined timeout (-2 seconds)
elapses before the host acts on a request tor r~lease the
Linus control~er grants itself release and proceed3 as it
desires.
Linus ERS
Page 9
Write File Mark
:01001001:
This Real Time command causes a file mark to be written at
the current position of the tape. The actual file mark
indication appears as a bit in the header of a data block
(lK). No data is stored in the block containing the file
mark. This is a real time command.
Spare Block Command
:00000110:
s = 0:
s = 1:
C,R
:OOOOOOsl:
Skip spare.
Jump spare.
This command causes the controller to spare the current
target block by the method indicated in the option byte.
This action includes updating the sparing table near BOT
thus tape motion is involved and this command may take 90
seconds to execute. This command does not retain data in
the spare block.
Initialize Tape
:00110111:
:OOOOOCWZ:
:00000000:
= 0: Rewrite sparing table with no ;~1ap spares.
Z = 1: Reset sparing table to initial spares.
Z
W = 0: Initial spare. are every 512th block plus
a track offset.
W c 1: Initial spare. are no spares.
C = 0: Runs certification if necessar,y.
C = 1: Does not force a certify test.
With all the option bits (Z,W,C) cleared, this command
certifies a tape (if it hasn't alrea4y been certified),
sets up a spare table on the ta~ (if one hasn't already
been set up), and spares out any
detective
blocks
discovered during the certify test. If the Z bit is
cleared, but a spare table does exist on the tape, all jump
spares are converted to skip spares. If the Z bit is set,
the spare table 1s cleared and rewritten to an initial
state as per bit W. In this case if N is zero there will be
an unused spare for each 512 blocks and thebe available
spares are staggered from block to block. No spares are
used; thus all bad blocks are to be rediscovered. For W 1
a null spare table is ~ritten allocating no spares on the
tape. The certify test 1s also skipped. Sparing becomes the
=
Linus ERS
Page 10
responsibility of the user as the controller is left with
no resources for it. This option should be used only for
coapatibility with non-BP systems. When the C bit is set
the certit.y test is not done. The media will return an
initialized media status ~en loaded into a drive in this
condition, even though the spare table is initialized. The
command takes 15-60 minutes to execute on an uncertified
tape.
The following table defines the controller activity for all
poss ible combinations of previous tape stOate and format
parameters.
\ c 1
\ w1
0
0
0
1
0
0
0
1
1
'l
1
0
0
1
0
1
1
1
0
1
1
1
1
1
I 0 1
1 0 1
1
1
1
1
1
--------------1-----+-----+-----+-----+-----+-----+-----+-----+
No Spare Table I
1
1
I
I
I
1
1
1
1 C J C I X 1 X 1 BIB 1 X I X I
Not Certified 1
I
1
1
I
I
1
I
1
--------------1-----+-----+-----+-----+-----+-----+-----+-----+
Spare Table
I
1
1
I
1
1
1
I
I
I C 1 C 1 X I X 101 B I X I X I
Not Certified 1
1
1
1
I
1
I
1
1
------------ ---1-- ---+-----+-----+--- --.: --- --+-- ---+-----+-----+
Tape State \Z
Spare Table
I
I
I 0
1 C I
I
Certified
I
1
I
I
1
I
X I X 101
I
1
1
I
I
I
B I X I X I
I
I
1
C - Certity the tape
Optimize the spare table
B - Build a new spare table
I - Clear the spare table
o-
C,R
Unload
:01001010:
When the Linus controller receives an unload tape command,
the error log is written, if necessary, and the tape is
unloaded. This action may require rewritting a block at BOT
as well as EOT so prepare for a possible three minute wait
until status is returned. The controller supports parallel
disc operations during this operation.
4.5
Diagnostic Commands
The three following Diagnostic Commands are supported:
Request Status
Initiate Diagnostic
Execute Utility
With these catagories of commands, it is possible
Linu!: ERS
Page 11
to
initiate
tests and gather results at both the intertace and tunctional
levels. In addition. the utilities provide a mechanism tor'
retrival o~ logs. diagnostic results. and characterization ot
the head/media interface. The Error Rate Test Log and the Error
Log will be stored in the system blocks tound near the BOT
(Between KEYS 9&10 and 10&11 respectively). As part of the
unload sequence the "USE Log will be updated. The "USE" log
resides betwen physical 4107 & 4108 on the ilL" tape and 1035 Ie
1036 on the .. s .. tape. A short discussion of the purpose and
content ot the above .entioned logs are included in the
explanatio'ls of the utilities which pertain to thea.
II
4.5.1
Request Status
:00001101:
The Request Status command operates exactly as described in the
disk ERS. In summar.y. the Request Status command returns a 20
byte status report (in an execution message) indicat~ the
status ot the last transaction. The status request consists ot
a 2-byte identification ~ield. an 8-byte error classification
field. and 10 bytes of additional error dependent parameters. A
summar" ot the format ot the status report is found in the
cs-80 Instruction Set Manual. A more detailed discussion ot
this comaand is provided in the CS-80 ERS.
4.5.2 Initiate Diagnostic
:00110011:
: LOOP PARAMETER :
: SECTION':
OPCODE
2 bytes
1 byte
The Initiate Diagnostic command will perform the phase or the
internal diagnostic which is indicated by the d1agnostic
section number. The internal diarnostic is divided into several
sections. the tollowing two of which pertain to Linus. These
tests are invoked at Power-On, and may be run individually
through the Initiate Diagnostic command. TCP two Linus related
diagnostic sections are specified as tollows.
: 8:: - TIB MICRO Diagnostic:
Functional tes~ing ot the Tape Interface Board.
including ··.pecial diagnostic lIode testing.
:11:
(A)-Initi.ate AUTO-LOAD Sequence:
Performs the OEM Self Test. tensioning. and Head
alignment functions with the cartridge in place.
(B)-DHA/TIB MACRO Diagnostic:
Tests all control lines and the serial data
path between the DMA and Tape Interface Boa:a.-ds
(C)-TIB/LINUS MACRO Diagnostic:
Tests control and data paths between the Tape
Linus EftS
Page 12
Interface Board and the LINUS .echanism •••
includes a short R/W and command/response tests.
The R/W test will seek to a diagnostic key Dear
Bar and attempt to write a test pattern on 2 of
16 tracks. Tape length is also retrieved from
the "manuf'acturer's block".
~.5.3
Execute. Utility
:001100XX:
:u OPCODE:
0-4 PARAMETER BYTES
1BY'l'E
xx • Ekecution Message Qualifier
00
01
10
->
->
->
.0Receive
Execution Message
Execution Message
Send Execution Message
The Execute Utility Co_and is followed by a Ilicro-opcode which
define. a variety of' disc and tape utili ties. Dependinc on the
utility selected, a pre-defined number of parameter bytes may
be expected to follow the utility number. Although, the
interface to this familY of utilities tends to be device
independent, the internal algorithms do depend on the specific
device. The f'ollowing Linus utilities present a consistent
disc/tape interf'ace.
Pattern Error Rate Test:
:11001000:
LOOP
TYPE
u OPCODE
1 byte
1 byte
: TST AREA: : DATA SRC:
1 byte
1 byte
Pal'ameter Definition:
LOOP
->
~
->
1-255
c
Loop Count
o
c
HOT Allowed
00
01
10
c
c
c
Read only ERT
Write/Read ERT
Certification
(Sparing lEY errors and
blks with >=2 frame errors)
TST AREA
->
00 = Use Current Address ,
Current Length. (Logical)
01 = Specified & Hext Track
(Phy)-(XXXX0001),
Where XXXX=Specified Track
10 = Entire Tape(Pby)
SRC
->
Defines data source
00 = Use Internal Pattern Thl.
01 = Use User defined patter.n.
10 = Use Random Data
DATA
Linus ERS
Page 13
This error rate test and certification utility is provided
to aid in characterizine
the
head/media
interface.
Write/Read and certification tests are destructive to
stored data. Tape certification includes a write/read pass
on all physical blocks While sparine all blocks with a key
errror or two or more frames in error. Therefore, the test
area is ignored when certification is selected. The test
area may be either logical. using the current address and
length, or physical. specifying a p~ir of tracks or the
entire tape. The data source may be from a pseudo-random
data generator, an internal Pattern Table, or user defined
by the ··RECElVE USER PATl'ERN tt utility described later. The
results of this may be recovered usine the ttRead ERT Log
Utility··. ·Permanent correctable and ·uncorrectable data
errors are logged, including their logical addresses Where
possible. Since reserved spare blocks may also exhibit
errors. the appropriate error counts "ill be incremented.
but no records will be returned for those blocks because
there is no corresponding loeical address. The sum of the
error counts (permanent and key). may therefore. be larger
than the number of records returned. ·Transient data errors
and key errors are counted. Since the error log is written
to a system block on the tape. rather than returned
directly to the user. the tape must not be write protected
even for a Read Only ERr. The parameters bytes for this
test are position specific. Therefore. a parameter bounds
error ~ill not be set when undefined bit positions in the
byte are used.
Read Error Rate Test Log:
:11000110: :00000000:
1 byte
u OPCODE
The ERT Data Error Loe is the standard loe for all errors
found while executinc the Pattern Error Rate Test. The
sinele byte "nUll" parameter indicates that the results
will cover all blocks specified durine the BaT run. The log
is composed of a header ~ich contains the number of blocks
accessed and error counts. and records which contain
relevant addresses and error qualifiers. This log contains
data and key errors. and is kept separate from the uRun
Time tt Error log so cumulative errors are not a concern
during testing. Records are kept for permanent errors
(correctable and uncorrectable) and key errors.
Log Format:
LOG HEADER
,
,
• ,
• ,
• ,
of
of
of
of
of
records
blocks accessed
permanent errors
transient errors
uncorrectable errors
Linus ERS
Page 14
1 byte
~
bytes
2 bytes
2 bytes
1
byte
, ot key errors
1 byte
LOG RECORD
ADDRESS PORTION:
Logical Block
addr~ss
_ _ 2 bytes
ERROR PORTION:
ERROR BYTE(See definition below) _ 1 byte
ERROR BYTE - Bit 0
Bit 1
Bit 2
Bit 3
Bit If
Bit 5
Bit 6
Bi t 7
= 0 f"rame
= 1 f"rame
= 0 f"rame
= 1 f"rame
= 0 f"rame
= 1 frame
= 0 frame
= 1 f"rame
• o ECC 5
=
1 ECC 5
1 NO CRC error
1 CRC error
2 NO CRC error
2 CRC error
3 XO CRC error
3 CRC error
4 NO CRC error
4 CRC error
- NO CRC error
- CRC error
o ECC 6 - 10 CRC error
1 ECC 6 - CRC error
= 0 correctable error
= 1 uncorrectable error
= 0 Frame error
= 1 Key error
=
=
• A PERMANENT ERROR is a block with one or more defect.
in the data area. Most detects are correctable. A
block with 2+ detects in non-adjacent frames is an
UJiCORRECTABLE ERROR. A TRM"SIENT ERROR is &nJ frame
error that disappears in less than three retries.
As a suggested output format f"or the ERROR byte, display
only those categories of ec-rors which are "active" (Bit
position = 1).
Read Error Log
:11000101: :00000000:
u OPCODE
1 byte
This Run Time Log provides a history of perf"ormance
for a
given tape. The "nUll" parameter byte indicates the results
are over all tracks and all blocks. The Clear Log Utility
(Described later) will clear this log of all records and
counts. The only records kept are for uncol'rectable and key
errors. This log is stored near BOT, between KEYS 10' 11,
in the following f"ormat. Certification is
zero
for
uncertified tapes; otherwise greater than zero.
LOG FORMAT:
LOO HEADER
, or records ___________ 1 byte
Linus ERS
Page 15
,
,
o~
o~
TYPe
uncorrectable errors
1
key errors __~~_____________ 1
of certification1
~.
~.
~.
LOO RECORD
THE Loo RECORD IS OF THE SAME FORMAT AS THAT
KEPI' FOR THE ERT LOO.
·Possible values for the "Type of
o = .ot certified
1 3M certified
2 = HP factory certified
q = Certified on-line
certi~ication"
are:
=
Read "USE" Log
:11000111:
The "USE" log provides a history o~ the total tape
activity. It contains two entries, auto-load count and
number of blocks accessed. This log resides at physical
block 1035 on the "s" tape and 4107 on the "t" tape. The
log is only updated durin, the unload ••quenc. and will
therefore remain unchanged during any sing1. session where
a tape is inserted. To preserve an accurate record ot tape
activity, this 101 may not b3 cleared. The "USE" log has
the following tormat:
LOG RECORD
Count of Auto-load sequences
performed on this tape
2 bytes
Count of blocks accessed ________ 4 bytes
Read Drive Tables
:Table N-.unl- r:
: 1.1000100:
This coaunand will return
4 RAM values stored in the drive
table specified by the i 'ameter value. 1bis intomation
can be used to achieve • understanding ot the drive state.
The possible parameter oyte values and the associated
tables are:
Table Humber
= 10
Manut ;ure'. Block table
Spare 'lock Table
:: 12 Copy i.,)·"art Address
= 11
Linus EftS
Page 16
MANUFAC'roRER'S TABLE
The aanutacturer's table i. the only .y.te. block not
wri tten by BP controller. • It
i.
wri tten by
the
manutacturer as part ot media formatting. Unlike the other
blocks on the tape it is written in the same direction on
all tracks (moving towards EoT) between keys zero and one.
Its data is recorded in 1 bit ASCII code with the most
.ignificant bit set to zero. The foraat is as follows:
DC6"HC
""
Format cO MINH. MINIHG AND MFR. CO,
~
Cartridge type - II i. 00 for the long tape
or 15 for the short tape
Line 2 Humber of u.er blocks per track, 4096 or 1024
Line 3 Copywrite notice
Line" Cartriqe identification cod.
XXXXIX is the manutacturer'. control cod.
HNMNHHHNHH is the date code
Line 1
The cartridge identification code contains both numeric and
alphabetic character. and i. unique for each cartridg••
The sy.bols , , , and )."epre.ent the
carriage
control.
1inefe.d.
backspace,
and e.cape
character. respectively. The manutacturer's block i. used
by the Linu. controller to determine the length ot the tape
just loaded. The fUll block i. available to ho.t coaputer.
thru the use ot a utility.
SPARE BLOC'It TABLE
Th. Spare Block table contains the
phy.ical adelr..... ot
all tho.e block. which are .pared. It aay be c1.ar.d br
u.ina the Initialize Tape
CS-80
command
with
the
appropriate parameters. The Table i. provided to intor.
external diagnostic utilities which areas ot the cartridge
are bad but are not mentioned in the Error Log, because
phy.ica1 addressing is not available to the host. There i.
no direct way to verify these blocks.
TABLE HEADER
, ot table entries
_ _ _ 1 byte
TABLE RECORD
Block number______________ 2 ~es
Track nUMber
1 byte
COPY START
ADDRESS
•
This table is holds a six b,yte logical address that
indicates where 3D image restore ot this tape should begin
on the disc. The address is given in block mode with the
Linus ERS
Page 11
most significant byte sent first.
Receive User Pattern
:11010001:
This utility will accept 64 bytes of data (passed from the
host) and write them to 'the controller RAM area for later
use with the error rate 'test.
Clear Logs
:11001101:
: LOG CODE:
This utility will clear 10,s
byte.,
LOI Code = 0
=1
indicated
by the
Clear the Error Lol ani
Clear the ERr 101 only.
~
parameter
log.
Read Revision Humber.
:11000011:
Thi. utility reads the firmware revi.ion number. for
disc/tape/and controller 1'il"lllW&r8. The 1'ir8t byte- returned
is equal to the number of byte. which will tollow.
Pre8et Drive
:11001110:
This conmand will torce all periodic upkeep required b.y the
device controller. This include. updating logl containing
run time data error. or drive faults. This command should
be issued periodically by the host, 80 it ~ control over
the tilling of periodic loggin,.
Read Error SWIUIlary
:11000001: :Recent or Previous:
u OPCODE
Parameter:
1 byte
o
1
= MOlt resent result8 (1 summary)
Lalt 4 summaries with error8.
(Does not include curren't lumaary.)
=
Linus EftS
Page 18
!his utility returns 1 or 4 (parameter dependent) 64 byte
'"bi1; maps" which represent the results of all test.
executed. Where the Linus Drive i. the only unit beside.
the controller, the "0" par8J:leter is the only valid
~eter. When the controller is common to disc and
tape,
the previous 4 error summaries may be cleared with the
CLEAR LOGS (ALL) command issued to the disc. Since the bit
positions correspond to actual errors, their definition is
DOW in
progress. One test's successtul completion .ay
clepend on the results of another test, and therefore, the
bos1; may intelligently combine a lIst ot test dependencies
with these results to perform tault isolation. This utility
is provided 80 field testing tools may intelligently adapt
to ~ield experience.
4.6
POwer-On Sequence
Four
se~te
diagnostic phases are entered during Linus System
Power-~.
They are:
(1) Controller (Including the Tape Interface
board) power on diagnostics.
(2) Linus Auto-Load Sequence.
(3) Tape Intertace Board to Linus
interface tests (Macro-diagnostics)
(4) System blocks are loaded into
controller RAM.
The Linus auto-load sequence (2) , begins when a tape is
detected in the drive. If a tape :IS present at power-on, the
auto-load sequence and the controller power-on diagnostic.
execute in parallel with the disc coming on-line betore the
more leaatby auto-load is complete. In the noraal situation,
the controller will be "up" when the tape i. inserted. For this
ease, phase (2), (3), and (4) swmnarize the Linus Tests before
COllin& on line.
In 'the !,irst phas., the controller and disc (if pre.ent) "board
and htertace" te.ts are executed. Thi. include. controller to
Tape Interface Board Data and Control Path T.stin,. Thi.
testiac occurs whether or not a tape i. pre.ent in the drive.
In the second phase, the Linu. drive perforas tape tensionin,
and head alignment functions, .s well as checking internal RAM
and registers tor proper operation. This phase i. initiated
when a tape is inserted or found (during s),stem power-on) in
the drive. The functions are all performed with the Linus '.
intemal aicro-processor.
In 'the third phase, the controller attempt. to communicate with
the cartrid,e usm,. short Read/Write test. This test is
non-destructive, using blocks invisible to the user. In the
last phase, the controller reads system intcrmation from the
Linus cartridce into the controller RAM. This information
includes the manutacture'. block and Spare tables.
Linus ERS
Page 19
LINUS POWER-ON
~QUElfCE
Tape
LIIIlJS
Presence
Detected
LOAD
Atn'O -
CONTROLLER
Power-On
POWER - ON
:<-Detected
BEGIlfS
--->:
I I
V
IF DISC PRESENT. :
IT COMES OK-LINE.:
OTHERWISE. WAIT
FOR At1l'O- LOAD TO :
: (TAPE PRESENCE
: DETECTION MAY
: OCCUR AT POWER:
: OK OR ANYTIIfg
: TBEREAF'l'ER)
:
CalPLETE
I I
I I
I I
f I
f I
AUTO - LOAD
CClfPLETE
I I
V
V
f f
V
IF A SIlfGLE CONTROLLER EXISTS
FOR BOTH TAPE AHD DISC. IT MUST
:REQUEST RELEASE OF THE OIl-LINE DISC:
I I
V
:TIB/LINUS MACRODIAGNOSTIC:
I I
V
: SYS'l'EH BLOCKS • ~ CONTROLLER RAM:
I I
V
•••••••••••••••••••••••
• LINUS COMES ON-LINE •
•••••••••••••••••••••••
Linu.ERS
Pace 20
5.0
PERFORMANCE SPECIFICATIONS
5.1
DATA CAPACITY
67.0 Mbytes Per ItL Cartridge
16. 7 Mbytes Per ··S.. Cartridge
Formatted Data Capacit7:
5.2
II
Data Transter Rate
Avera,. Data Transter Rate:
Burst Transter Rate:
5.3
35.0K b7tes/sec. (2.1Mbyte/miD)
- 9001 bytes/sec.
Access Tiae
Total access time is the sum ot the tollowing tactors:
195 msec:/traek
19.8 asec/ke7 (lKbyte/ke7)
Track to Track Seek
ley to Key Search
(Worst ease access is 83 see.)
5.~
Tape Speed
Read/write/Verit.y
Seareh (Key)
5.5
60 ips
90 ips
RecordtDa Parameters
lneodiDc Teclmique
Bit DensiV
lwaber of 1Tacb
-Number ot User Bloeks
Data/Block
5.6
MFM
10000 bpi
16
65408 tor "L", 16352 tor liS"
1024 byte.
Error Rate
c
2 errors in 10EI0 bits transtered, unrecoverable e.r.
- For initialized tape
Linus F.RS
Psge 21
6.0
ERVIRONMENTAL
The Linus tape subsystem
is designed to meet the Class B
the BP Corporate Ervironmental Specification
A-6950-5344-1. Exceptions to this specification are noted.
requir.. .nts
6.1
o~
Teaperature
OPERATING - five
degrees
centigrade
to
forty
five
degrees
centigrade.
NOH-OPERATING - negative forty degrees centigrade
degrees centigrade.
6.2
~
NON~OPERA7ING
to
-
5~
8~
to
non-condensing.
95~
non-condensinc.
Vibration
Operat~
6.1,
sixty five
Huai4ity
OPERAXING -
6.3
t~
and non-operating per DMD dwg A-5955-3439-1
Shoek
11 asec, 1/2 sme wave, 30 I'. non-operatinc.
6.5
Altitude
!be unit will withstand altitudes ~ro. 300 .eter. below sea
level to 4600 meter. above .ea
level.
operatin,;
and
Don-operatinc to 15000 ..ters.
Linus ERS
Page 22
1.0
RELIABILITY
1.1
Failure Rate
The failure rate goal is 6.6~ /1000 hours of power on time, and
t&pe moving at 17% duty cycle.
1.2
Repair Time
The mean time to repair (MTi'R) goal is <1 hour excluding tra~"el
tL.e.
1.3
Average Use Estimates
Pover on -
5~
duty cycle
Tape in motion - 2 hours/day average
1.4
Service
No field preventative maintenance is required. The head and
c Lpstan can be cleaned by the customer us ing a chemical head
cieaner. (Every week)
1.5
Cartr:idge Life
Average life of the cartridge is 2500 end to end cycles ot
tape. One cycle is moving troll EOT to BOT to EO'!'.
Linus ERS
Page 23
the
8.0
PHYSICAL SPECIFICATIONS
8.1
Size
Drive Module - 117mm. high x 178mm. wide x 21Omm. deep
Tape Interrace Bd. - 178mm. x 305mm. (1/2 Amigo size)
8,.2
Input Power
5v - 3.6 amps
12v - .75 amps (4.0 amp surge)
Linus ERS
Page 24
Examples ot Linus media defect handling
90,0
The following examples show how the host should interact with 'the
Linus controller to minimize error handling problems. For these
examples the tape has a bad key for block 5, a bad data area in
block 10; blocks 7 and 15 are allocated as spares. The host is
working with a. 18 kbyte file starting at block O.
14 15 16 17 18
0 1 2 3 ~ 5 6
7 8 9 10 11 12 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+-
L
*
I ** I
I ss I
I ss I
Ii
+--+--+--+--+--+--+--+--+--+--+--+-~+--+--+--+--+--+--+--+--+--+-
P
0 1
23
4
5 6
7 8
9 10 11 12 13 14 15 16 17 18 19 20
- - detect over key
detect in block
ss - available spare block
xx - block deleted by sparing
*- -
P-II indicates physical block ".
NOTE:
Physical addresses
are not accessible to the host.
L-II indicates logical block " .
All host addresses
are Logical addresses.
Case 1
-
Writing the file
OD
virgin tape.
1be host issues a write at 0 for 18 kbytes.
Linus writes blocks L-O to L-~.
The Linus controller adds block 5 to the Error Log.
Linus accepts and sinks blocks L-5 to L-17.
The returned status indicates that block 5 is ot no use.
The host should issue a command to skip spare block L-5.
The host then reissues a write at 0 tor 18 kbytes.
writes blocks L-O to L-~.
skips block P-5.
writes block L-5 (in block P-6).
writes blocks L-6 to L-13. (P-7 becomes a data block)
skips block P-15.
writes blocks L-14 to L-17. (in blocks p-16 to P-20)
returns normal status as the error at block 10 cannot
be detected yet.
Linus
Linus
Linus
Linus
Linus
Linus
Linus
The tape DOW contains •.•
L 0 1 2 3 ~
5 6
1~ 15 16 17 18
7 8 9 10 11 12 13
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+-
·xx I
I·· I
I ss I
I
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+P 0 1 2 3 ~ 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Linus ERS
Page 25
Case 2
Reading the above file.
The host issues a read at 0 for 18 kbytes.
Linus returns data from blocks L-O to L-4.
Linus skips block P-5.
Linus reads data from blocks L-5 to L-8.
The Linus controller enters block P-10 in the Error Log.
Linus returns it's best guess for L-9. and reads L-10 to L-13.
Linus skips block P-15.
Linus reads blocks L-14 to L-17 (from blocks p-16 to P-20).
The returned status indicates unrecoverable data in block ]~-9.
Case 3
Re~iting
the above file.
The host reads the error log and is told about block L-9.
The host issues a Spare Block L-9 command. with jump option.
Linus logs P-10 in its Jump block table with a link to P-15.
The host issues a write at 0 for 18 kbytes.
Linus
Linus
Linus
Linus
Linus
Linus
Linus
Linus
Linus
Linus
writes blocks L-O to L-4.
skips to block p-6.
writes blocks L-5 to L-S.
seeks to block P-15.
writes block L-9.
seeks to block P-11.
writes blocks L-I0 to L-13.
skips block P-15.
writes blocks L-14 to L-17.
returns a normal completion.
The tape now contains •••
L 0 1 2 3 4
5 6
7 8
10 11 12 13
9 14 15 16 1718
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+-
I
I
I ·xx I
I
I
Ixx I
I
I
I
I
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+-
P
0 1
Case 4
2
-
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20
Reformatting the Tape
The host issues a Initialize Tape command. saving spares.
Linus logs blocks P-5 and P-I0 in the skip table.
Ljnus clears the Jump table.
Linus returns good completion.
The host issues a write to 0 tor 18 kbytes.
Linus writes blocks L-O to L-4.
Linus skips block P-5.
Linus writes blocks L-5 to L-8 (in blocks p-6 to P-9).
Linus skips blocks P-10.
Linus writes blocks L-9 to L-17 (in blocks P-17 to P-19).
Linus reports good completion.
Linus EftS
Page 26
The tape DOW contains •••
L 012 3 ~
5 678
9 10 11 12 13 14 15 16 17 18
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+-
·xxl
Ixxl
+--+~-+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+-
P 0 1
Case 5
2
-
3
~
5 6
7 8
9 10 11 12 13 14 15 16 17 18 1920
Use of Auto sparing
Start with situation before case 1
The host enables Auto sparing with the skip option.
ine host then says to write 18 Kbytes starting at block O.
Linus writes blocks L-O to L-4 (P-O to p-4).
Linus detects the bad key at P-5 and skip spares that block.
The tape now maps as at the end of case 1.
Linus writes blocks L-5 to L-13 (p-6 to P-1~).
Linus skips the spare block P-15.
Linus writes blocks L-14 to L-17 (p-16 to P-19).
Linus rewrites the sparing table and returns status.
Some time later the host has read the file (see case 2)
and found it lacking in quality.
As the directory shows there are files present beyond this
one the host enables Auto sparing with the jump option.
The host recreates the file and tells Linus to write it.
Linus writes blocks L-O to L-4 (P-O to p-4).
Linus skips spared block P-5.
Linus writes blocks L-5 to L-8.
Linus jump spares block P-I0 to P-15 because it was logged.
Linus writes block L9 at P-15.
Linus writes blocks L-10 to L-13 (P-ll to p-14).
Linus writes blocks L-l~ to L-17 (p-16 to P-19).
Linus rewrites the sparing table and returns status.
The tape is now as at the end of case 3.
Linus ERS
Page 27
10.0
LOGICAL INTERCHANGE COMPATIBILITY
linus is compatible with the HP Logical Mas. Meaor.y Format
Standard (LIF) as revised in January '81. Tbe following notes
apply 'to Linus when used for LIF:
1.
Sector (physical block) = 1024 bytes
2.
The number of usable sectors per take is readable from
!ESCRlBE command (16352 tor initialized short tape, 65408
initialized long tape).
3.
For writing. use skip spacing, SPARE BLOCK cODmland S· c o.
(Auto skip spacing is recommended, device specific options A=
1. S = 1).
4.
On used tapes convert
DITIALIZE TAPE. E = 1.
5.
It is also recommended that a file mark be written at the
third sector to prevent the disc from accidentallY being
"image· restored by a LIF tape.
jump
1
Linus ERS
Page 28
spares
to
skip
the
for
spares,
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