0948262 9701A DS10 Cartridge Disk Controller Depot Maintenance Manual May82

0948262-9701A_DS10_Cartridge_Disk_Controller_Depot_Maintenance_Manual_May82 0948262-9701A_DS10_Cartridge_Disk_Controller_Depot_Maintenance_Manual_May82

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Model 990 Computer
DS10 Cartridge Disk Controller
Depot Maintenance Manual

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DRIVE UNIT SELECT A
TILINE POWER FAIWRE WARNING PULSE
TILINE POWER RESET
TI LINE I/O RESE T

.......

}

DRIVE UNIT SELECT B
PERIPHERAL
RESET

DISK SELECT (REMOVABLE/FIXED)
HEAD SELECT (UPPER/LOWER)

~

~

INDEX MARK

L.

..

SECTOR MARK
SECTOR ADDRESS (5 LINES)

}

ROTATIONAL
POSITION

}

STAruS

ON LI NE
SEEK ERROR
FAULT
WRI TE PROTECT

L.

READY (ON CYLINDER)

'" swnCH UNn

on

(O.'V' A)

ID SWITCH UNIT 2/3 (DRIVE B)

2282597

Figure 2-1. DSIO Disk Controller Interface Signals

I

CAB LE ADAPTER
JUMPERS

1

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~

946262-9701

There is one data interrunt re1ated to controller
.I.

•

-

-

oner~tlon·
- ___

" . . 1.-

'_"0

••••

TILINE Interrupt. This is the general interrupt from the controller slot location to the 990
processor.

The peripheral reset signals clear the controller and the disk drive to safe states in the event of an I/O
reset instruction or a power shutdown. These signals are:
•

TILINE Power Failure Warning Pulse. A signal preceding TLPWRES- that indicates a
computer power-down sequence is in progress.

•

TILINE Power Reset. This signal line goes low to reset the controller and all other
TILINE devices. It is generated as part of the computer power-down and power-up
sequences.

•

TILINE 110 Reset. When this signal is low, it halts and resets all TILINE 110 devices.
This signal is developed by the 990 processor.

The signals exchanged between the disk controller and the disk drive(s) fall into five categories;
write, read, access control, disk platter rotational position, and drive status.
The write signals include:
•

Write Data and Clock. Serial double-frequency (FM) waveform in which data and clock
pulses are multiplexed on one signal line.

•

Write Gate. An enabling command that allows the drive to supply write current to the
specified read/write head.

•

Erase Gate. An enabling command that turns on erase current to the straddle erase heads.

The read enabling signals include:
•

Read Data. A serial bit stream separated from the clock bit stream by a clock/ data
separator circuit in the disk drive electronics.

•

Read Clock. Clock pulses from the previously recorded write data and clock bit stream.

•

Read Gate. Enables the disk drive read heads and read electronics.

The access control signals include all the signals necessary to select a drive unit, platter, head and
track. These signals include:
•

Cylinder Address. Nine lines that specify the required position of the head carriage.

•

Cylinder Address Strobe. A pulse that loads the cylinder address into the disk drive
electronics.

•

Address acknowledge. Confirmation by the drive that a valid (0-407) cylinder address was
accepted.

•

Restore. A master clear command that clears the disk drive fault latches and address
register, and runs the head carriage through a full stroke (forward to track 407, back to
track 0).

2-3

Digital Systems Division

~------~

946262-9701

•
•
•

Drive Unit Select A and B. Lines that specify the first or second disk drive.
Disk Select. Specifies the fixed or the removable disk drive.
Head Select. Specifies the upper or lower surface of the disk platter.

The rotational position signals are used to keep track of the disk position as it rotates under the
heads. It is important to note that the sector/index marks are sensed separately on the fixed and on
the removable platter. The sector encoder for the fixed disk is hard-mounted on the spindle. The
sector slots for the removable cartridge are built into a ring within the individual cartridge. The
rotational position signals (which apply to the platter currently selected) are:
•

Index Mark. Pulse that occurs once per revolution, at the beginning of sector O.

•

Sector mark. Pulse that occurs at the start of each sector (20 times per revolution). Serves
as a timing reference and indicates that the current sector address is stable and valid.

•

Sector address. Five-bit binary sector address supplied by the disk drive electronics
derived from sector pulses.

The status signals from the selected disk are:
•

On-Line. Drive power applied, disk up to speed, and other conditions (described with the
disk interface logic).

•

Seek Error. Fault detected in head carriage positioning.

•

Fault. Generalized fault indication.

•

Write Protect. Selected disk platter protected from write operations by WRITE
PROTECT-FIXED or WRITE PROTECT-CART switch on disk drive front panel.

•

Ready. Ready to start read or write with head carriage at specified cylinder, no faults
detected.

The interface figure (figure 2-1) also shows the logical unit number reversing jumpers on the cable
adapters.
2.2 DISK CONTROLLER BASIC BLOCK DIAGRAM DESCRIPTION
The Model OSlO Cartridge Disk Controller is a microprocessor-based "smart" controller that
manages disk control and data transfers independently of the Model 990 computer after accepting a
group of control parameters.
Figure 2-2 shows that the disk controller logic may be partitioned into three major functional
groups: the TILINE interface, the microprocessor-based sequence controller (microcontroller), and
the disk interface logic.
2.2.1 TILINE INTERFACE. The TILINE interface consists of the TILINE slave logic, the TILINE
master logic, and the line drivers and receivers. The slave logic is activated when the 990 processor
addresses one of the eight TILINE slave addresses that are assigned to the controller. These eight
TILINE slave addresses are dedicated to control and status words WO-W7, and are used to load
control words (TILINE slave write operation) or to request status words (TILINE slave read
operation). The term "slave" is applied to these operations because the controller responds to an
externally-supplied address and to a read/write command, much like a memory.

2-4

Digital Systems Division

MICRO-

MICRO--

,
ADDRESSES

!~~E;R':P\R;:NS~~IONSI
~~~~~~~~~---.
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COMPUTER

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PROGRAM
ROM

ADDRESS

5'2 WORDS
X 40 BITS

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MICRO-

INSTRUCTION

PROGRAM
ADDRESS
GENERATOR

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CONTROL

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BR_A_N_C_H_T_E_s_T_B_IT__. -____. ____~----~I

~~~~~~~Y

INTERRUPT

(F6-FO)

.

TILINE
TILINE

TRAP

L:.0N~I~

~ FU6'~ri~ON

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SLAVE TRAP

to'"

ADDRESS

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TILINE

MASTER AND
SLAVE LOGIC

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~~~DRESS

SPECIAL FIELDS

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TO ALL

CARRY

ARRAY

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H------..

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CONTROLLER LOGIC

CENTRAL PROCESSING
ELEMENT (CPE)

,.......i----'---:::l

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MICRO-INSTRUCTION
DECODE

,+++!+++

(RO U)

UX (K)
MASK

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TILINE BUS

(X,Ve,)

39

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rr

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LOGIC

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COMMAND

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14-_____........S..T.A..
TU.S...._ _-I
DISK

DRIVE SELECT AND CONTROL

~'

INTERFACE

MEMORY
DATA IN
DATA OUT
(D)
(M)

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LOGIC
CLOCK

PROCESSOI~

BUS
(PBUSOO- THRU , 5-)

.. DRIVE STATUS

r,-"Wc:..:R~IT:..:E:..:D:.:;A'-'T.:..:A..:.A::..:N:::.D-=C;.:L:::.OC:;;K"--___~~
READ DATA

L. READ CLOCK

...
MICROPROCESSOR

LEFT. RIGHT
eYTE CLOCKS

CLOCK
TILlf'JE INTERFACE

MICROCONTROLL.I:::R

DISK INTERFACE

(C), 3'686

Figure 2-2. OSlO Disk Controller Simplified Block Diagram

;.

~::~~' SK

~_
946262-9701
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_ _ _ _ __

The TILINE master logic is activated to transfer data between the disk drive and a specified (by
control words) buffer area of 990 memory. The TILINE master logic requests and attains bus
control, and manages the "handshaking" exchange of signals necessary to transfer each word ..
2.2.2 MICROCONTROLLER. The microcontroller uses a 16-bit processor and a permanent onboard microprogram to control execution of the operations specified by control words WO-W7.
The processor is an array of eight 3002 central processing element (ePE) devices. Each high-speed,
bipolar ePE is organized as a two-bit slice of a complete processor, including input buses, output
buses, internal storage registers, and an arithmeticjlogic unit. The ePEs are connected with external
shift and look-ahead carry logic, in an array that can process eight-bit bytes or 16-bit words. The
ePEs perform the add, subtract, complement, shift, store, mask and logical operations required by
the microprogram.
The ePE array uses internal registers for storage of control word WO-W7 and also for the scratchpad
storage necessary to maintain loop counters and store other operands and intermediate results. The
ePE array does not have access to an external read/write memory for scratch pad purposes.
The main data transfer path through the disk controller is the 16-bit processor bus (P-bus), which
links the TILINE line drivers/ receivers, the ePE array and the disk interface~ The ePE array can
accept data from the processor bus or place ePE accumulator data on the bus, as commanded by the
mIcroprogram.
Disk controller internal status and disk drive status are supplied to the ePE array on the external
input (I-bus) lines. The masking and bit-testing capabilities of the ePE array are used by the
. microprogram to sense the progress of ongoing operations and steer microprogram execution based
on current conditions. A separate disk status word is available over the processor bus for the same
purposes.
The mask input (K-bus) of the ePE array is used by the microprogram to load constants and masks
into the ePE array.
The CPE address (A-bus) outputs are used to supply 16 bits of the 20-bit TILINE address during
TILINE master cycles; i.e., when the controller is acting as a master to control data transfers to and
from 990 memory.
The disk controller microprogram is burned into a group of 512-word read-only-memory (ROM)
devices. Each microprogram instruction or microinstruction is 40 bits wide. The microinstruction is
divided into multiple fields, each of which controls some aspect of TI LINE interface,
microcontroller, or disk interface operation. Fields within the microinstruction select processor bus
sources and destinations, clock generation, ePE array left byte/right byte/full word mode, ePE
function code, ePE mask inputs, disk drive control signals, and microinstruction address selection.
This is only a partial list, but serves to emphasize the fact that the microinstructions are intimately
involved in all aspects of disk controller operation.
The microprogram address generator selects each microinstruction from read-only-memory. The
address generator can step through sequential addresses, branch conditionally or unconditionally,
link to subroutines, and return conditionally or unconditionally to addresses stored in a four-word
stack, or branch to predefined interrupt trap locations.
2.2.3 DISK INTERFACE. The disk interface logic performs the operations necessary to convert
between the serial recording format required by the disk drive and the parallel formats imposed by
the processor bus and TILINE bus, compensates for clock and data rate differences, checks data
integrity, supplies drive control signals and monitors drive status and rotational position signals.

2-6

Digital Systems Division

~------~

946262-9701

Figure 2-3 shows the major functional blocks of the disk interface. The 16-word first-in, first-out
(FIFO) buffer compensates for the differences in data transfer rates between ihe TiLiNE (or the
CPE array) and the disk. This is necessary because the TILINE is shared between multiple users and
is not always instantly available, while the disk data rate is inflexibly fixed by the inertia of a rotating
mass.
The serial/ parallel shift register, like the FIFO, is used on both read and write operations. During
disk read, the shift register assembles serial data into 16-bit parallel words. During disk write, the
shift register accepts 16-bit parallel data from the FIFO and converts it to serial form.
The cyclic redundancy check (CRC) generator calcuiates a data integrity code during write
operations, and transmits that code following the last data word of the record. During read
operations, the CRC code is recalculated and checked against the previously recorded value. If they
compare, the integrity of the entire write, store, and read operation is verified.
2.3 BASIC DATA FLOW
The following paragraphs describe data flow through the disk controller for five important cases.
2.3.1 DATA FLOW - LOADING COMMAND WORDS INTO THE DISK CONTROLLER.
Refer to figure 2-4, which shows the data flow involved in loading command words WO-W7 into the
disk controller. Each command word is sent from the 990 processor to the controller as a TILINE
data word. The 990 processor acts as a TILINE master during these operations. It acquires control of
the TILINE, supplies the TILINE address, the read / write control signal and the word to be sent to
the controller. The controller acts as a TILINE slave, decoding the address and responding to the
read/write signal by accepting a 16-bit word.
Each of the eight command words is assigned a unique TILINE address ranging from the TILINE
base address to the base address +7 word addresses. The addresses are assigned in order; i.e., control
word WO is assigned the base address, WI is assigned the base address + 1 word address, and so on.
The disk controller microprogram has eight unique trap addresses assigned to write operations on
control words WO-W7. The decoded TILINE address initiates the slave write trap for the particular
command word. The microinstructions in the trap routine steer the TILINE data word onto the
processor bus and command the CPE array to store the control word in the correct CPE scratch pad
register. CPE scratch pad registers RO-R7 are assigned to store control words WO-W7, respectively.
The microprogram disables the TILINE slave logic after receiving a control word W7 with a zero in
the idle bit, which initiates decoding and execution of the command.
The slave logic remains disabled until the controller has completed the commanded operation.
Therefore, control words WO-W6 may be transmitted in any order, but W7 must be the last word.
2.3.2 DATA FLOW FOR DISK WRITE OPERATIONS. Refer to figure 2-5, which shows the
simplified data flow for the disk write operations, write data and write unformatted. During a write
data or a write unformatted operation, the disk controller is operating under its internal
microprogram, using previously stored command words WO-W7 as parameters.
NOTE
During a write data operation, the controller reads back and verifies
the record header prior to recording any data. That data flow is
shown in figure 2-8. The data flow in this paragraph also does not
apply to the write format operation.

2-7

Digital Systems Division

I

FROM MICROINSTRUCTION
DECODE

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.~

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I

DRIVE
SELECT
AND
CONTROL

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...

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STATUS
RECEIVERS

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TI LINE LINE
DRIVERS AND
RECEIVERS.
CPE D-BUS
OUTPUTS.
M-BUS INPUT S

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2282591

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WRITE

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FROM MICROINSTRUCTION
DECODE

DIRECT
READ
REGISTER

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......

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1
SERIAL
WRITE
DATA

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16-BIT
SERIALI
PARALLEL

20-8 I T
X
16-WORD
FIFO
BUFFER

~

f----t.

....-..

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WRITE
CLOCK

k;ENi~;TOR r------

ENCODED
WRITE DATA
• AND CLOCK

I

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I

SEI~IAL

READ DATA

TO DISK
CLOCK
DISTRIBUTION

Figure 2-3. Disk Interface Simplified Block Diagram

DS10
DISK
DRIVE(S)

I

WRITE DATA
AND CLOCK
ENCODING

PARALLE L. READ DATA

SYNC
DETECT

I

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r

F L.AG 5

Ir

r

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~ ~

AND
CHECKER

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1
DISK CLOCK
DI STRIBU TION

o

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TEST CLOCK

READ CLOCK

~

r~

~

FLA~

tv
tv
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0\

1

PROCESSOR BUS (PBUSOO- THRU 15-

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NI

.,f:;I..

0\

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~

\0

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+
CPE I-BUS

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..

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~

DISK IIF
CONTROL

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TO CPE
I-BUS
INPUTS

.

INSTRUCTION
DECODE

r!7

I

.

FROM M,eRO-{

L..
READ DATA
AND CLOCK
BUFFERS

I
I

READ DATA

I READ CLOCK

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MICROPROGRAM
ADDRESS
GENERATOR

...

MICROPROGRAM
ROM
~------~

SLAVE TRAP
ADDRESS

________J

~}

CPE FUNCTION
CONTROL

:
TI LI NE ADDRESS 0- 19

TI LI NE
SLAVE LOGIC

OTHER
CONTROLS

F
LEFT BYTE
CPE ARRAY

0-7

........~ M---,
I
I

,""- - .- -*- -- - - - -- RO

- - - - - - - - - -~~ -- -- -- --- -- -- ---_.-

~l

~

.B:a _ _ _ _ _ _ _ __

I-

990
SYSTEM IIF

_ _ _ _ _ _ _ _ _ •

I-

_R~

I-

_R.§ _ _ _ _ _ _ ___ _
R6

R7 - - - - - - - - -

I--

TILINE LINE
RECEIVERS
TILINE DATAD-I 5

:. F
PROCESSOR BUS 0- 1 5

8-15

I
I

I
I

I
2282584

DISK CONTROLLER

I
Figure 2-4. Simplified Data Flow -

Loading Command Words Into the Disk Controller

TILINE
ADDRESS 16-19
TILINE MSB ADDRESS REGISTER

TILINE ADDRESS 0-191
L

r

TILINE
ADDRESS 0- 1 5
CPE ADDRESS (A) BUS OUTPUTS

990 MAIN
MEMORY

OPERATION AT
TILINE IIF
DATA RATE

NI

II

o

r"

TILINE
DATAo-16

I

PROCESSOR
BUS DATA 0-15

~

FIFO
INPUT
0-15

I
I

CYCLIC
REDUNDANCY
CHECK (CRC)

-

CRC CHARACTER (END OF RECORD)

OPERATION AT
DISK IIF
DATA RATE

I
I

FIFO OUTPUT 0-15

I

16-WORD

~:~~+:g~'T

(FIFO) BUFFER

I

TILINE DATA TO
PROCESSOR BUS
ENABLE

I

I
(B) 138626

. . tr-rY
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c:: :>:--------1----.
I

~---'+
FLAGS

FLAGS

eee,

DOUBLE-FREQUENCY
WRITE
DATA AND
CLOCK

READ/wRITE
SELECTION

PARALLEL
TO SERIAL
CONVERSION

SEROAL DATA

.1--<

DISK CONTROLLER
DISK WRITE
CLOCK
DATA/CRC
SELECTION

Figure 2-5. Simplified Data Flow for Disk Write Operation

I

TO SELECTED DISK
(LOGICAL UNIT 0-3)

~_
946262-9701
Jd75\
_ _ _ _ __

The disk controller acts as a TILINE master to read the data from 990 memory and load it into the
16-word FIFO buffer. The initial TILINE address and the transfer word count for this operatIon are
parameters supplied by the control words. The ePE array updates the TILINE address and
decrements the word count as the operation proceeds.
The operation of requesting and obtaining access to the TILINE, transferring data, and
relinquishing control of the TILINE, is called a TILINE master cycle. One TILINE master read cycle
is performed for each data word that is to be recorded. Master cycles are initiated by the
microprogram, based on such conditions as whether there is space available in the FIFO and
whether the word count has been decremented to zero.
The FIFO serves as a buffer to adapt the variable data rate of the TILINE to the fixed data rate of
the disk. All operations from the FIFO output to the encoded write data and clock output are synchronized to a crystal-controlled write clock oscillator.
The parallel-to-serial conversion occurs in the serial/ parallel shift register. The eRe logic operates
on this serial bit stream and, at the end of the transmission, the 16-bit eRe character is shifted out
instead of serial data.
2.3.3 DATA FLOW FOR DISK READ OPERATION. Figure 2-6 shows the simplified data flow
for the disk read operations, read data and read unformatted.
NOTE
The data flow in this paragraph does not apply to reading and
verifying a record header prior to reading the record.
After the specified track and sector are located by the drive and the record header is checked against
parameters supplied in the control words, the disk controller turns off the read gate for a short time
to eliminate transient pickup, and then reenables it.
Read data and clock are supplied to the disk interface on separate lines by a phase-locked clock/ data
separator in the disk drive electronics. The all-clock (data zeros) waveform in the prerecord gap locks
in the clock/ data separator.
Read clock from the disk is used to clock all data operations between the read data buffer F / Fs and
the FIFO input.
The shift register shifts serial data in, but no additional operations occur until the 6E 16
synchronization character is recognized. At that point, the eRe generator is preset, a 16-bit counter
is cleared, and the FIFO accepts the next 16-bit word assembled by the serial/ parallel shift register.
The microprogram is notified (via the ePE I-bus) that data is available for transmission to 990
memory. The microprogram initiates a TILINE master write cycle each time there is a data word
available in the FIFO when the I-bus bit is checked, as long as the transfer word count has not been
decremented to zero.

If the transfer word count reaches zero before the end of the record, the controller microprogram
stops requesting TILINE master cycles, but continues to read the complete record in order to verify
the eRe character.
If the transfer inhibit bit (W 1, bit 4) were set, the controller would read the entire record, but would
not request any TILINE master cycles, preventing any data flow to the 990 memory. The eRe
would be checked at the end of the operation. This is a means of checking a previously recorded
record without tying up the TILINE with unnecessary data transfers.
2-11

Digital Systems Division

TILINE
ADDRESS 1 6- 1 9
TILINE MSB ADDRESS REGISTER

TI LI NE ADDRESS 0- 1 9
L

I
TILINE ADDRESS 0-15
CPE ADDRESS (A) BUS OUTPUTS

CRC ERROR

"'~t-----1

CYCLIC
REDUNDANCY
CHECK (CRC)

990 MAIN
MEMORY

OPERATION AT
TILINE IIF
DATA RATE

•

NI

PROCESSOR

TILINE DATJ
0-15

/

~~~\DATA/

I

PROCESSOR
TO TILINE
ENABLE

I

FIFO

~T~T

OPERATION AT
DISK IIF
DATA RATE

•

16-WORD

r--

5.

FIFO
INPUT

~_ _ _

~ i}

eus

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i--""""--)..O.-.l

N

-

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fi:tl:Jtjt
(FIFO) BUFFER

r-

PARALLEL DATA 0-15

/

l1li11

-

FLAGS

SERIAL TO
PARALLEL
CONVE:RSION

•

FLAGS

SERIAL DISK
DATA IN

READ
DATA
BUFFER
F/F'S

READIWRITE
SELECTION

I

READ CLOCK

CONTROLLER

I
I
II

SERIAL
READ DATAl

...

I
"

(B) 138627

Figure 2-6. Simplified Data Flow for Disk Read Operation

FROM SELECTED

~~~~ &'=.~~ICAL

"ij/
~------946262-9701

2.3.4 DATA FLOW FOR A WRITE FORMAT OPERATION. Refer to figure 2-7, which shows
data flow for a write format operation.
The write format operation is performed on every eligible sector of the specified track starting at
sector o. If the specified format is one sector per record, every sector is eligible to serve as the start of
a record. For a two sectors per record format, sectors 0, 2, 4 ... 18 are eligible.

The write format operation records an all-zeros preamble, a synchronization character, a three-word
record identification header, and a CRC character at the beginning of every eligible sector.
The data necessary to select the sectors and develop the record identification headers is included in
control words WO-W7 so that information is stored in the CPE internal registers.
The write format operation also requires that the controller fill each prerecord gap with clock pulses,
record a synchronization character, fill each data area with repeated copies of a filler word, and store
the CRC character at the end of each record.
The control words include a TILINE address which is the location of the filler word. The first data
flow cycle of a write format operation retrieves the filler word from 990 memory (with a TILINE
master read cycle) and gates it into the direct read register for temporary storage. It is then gated
onto the processor bus and stored in one of the CPE internal scratch pad registers.
The remaining data transfer cycles involve data flow from the ePE accumulator (D-bus) output to
the FIFO input via the processor bus, and from the FIFO output to the disk over the same data path
described in paragraph 2.3.3.

l

2.3.5 DATA FLOW FOR A VERIFY RECORD HEADER OPERATION. The read data and
write data operations require that the record identification header be checked before reading or
writing the data record. This operation provides a 3-way check between the format recorded on the
disk, the record parameters specified by the control words, and the physical track and sector location
of the read/ write heads.

The desired track location is supplied by the control words, and the disk controller commands the
disk drive to move the head carriage to that physical location and select the proper recording surface.
When the seek is complete, the disk controller monitors for sector marks, and reads each sector
address, waiting for the specified sector to rotate under the read/write heads. It is important to note
that this sector address supplied to the controller is not read from the record identification headers.
It is developed by the disk drive electronics by tallying sector marks from index mark to index mark.
When the sector address supplied in the control words agrees with the sector address sampled from
the disk drive, the controller enables the read gate, monitors for the synchronization character, and
then reads the three-word header into the CPE array and checks the CRC character.
If the record header compares correctly to the parameters supplied in the control words, it indicates
that the format previously recorded on the disk is correct and recoverable, that the disk drive
accessing electromechanical and electronic components are working, and that the parameters of the
record as specified for the read / write operation agree with the parameters of the physical record on
the disk platter.

Figure 2-8 shows the data flow for reading a record header. Between the disk drive and the output of
the serial/parallel shift register, the data flow is identical to a read data or read unformatted
operation.

2-13

Digital Systems Division

TILINE
ADDRESS 16-19
/////////

TILINE MSB
ADDRESS REGISTER

1/
1/
1/
1/
1/
II
II

TILINE ADDRESS 0-1 5

~

I

~

~

///////(LLL/

~

~

1/

~

990 MAIN
MEMORY

I

0-15

'///

CPE
ARRAY

A

o

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PROCESSOR BUS 0-15

"""","",",

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DIRECT
READ
"""""""'"
REGISTER

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I
I

tv
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M

f:f

TILINE DATA TO PROCESSOR
BUS ENABLE

o

--

r--

CRC CHARACTER

I
FLAGS

~:

CYCLIC
REDUNDANCY
CHECK (CRC)

FLAGS

~

...

~.
~
~
j.:>"
-

I

PARALLEL!
SERIAL
CONVERSION

I

r-

v-

CONTROLLER

I

DOUBL.E-FREOUENCY
HEADER DATA &

~

Q)

DISK WRITE
CLOCK
DATA/CRC
SELECT
2282592

Figure 2-7. Simplified Data Flow for Write Format Operation

I

CLO~~

I
I

TO SELECTED DISK
(LOGICAL UNIT 0-3)

I
I

I~

K
CPE
ARRAY

I)::=::)

I

CRC ERROR

...
41--------~

I
I
I

NI

Ul

I
I
I
I

I

CONTROLLER

PROCESSOR BU S
DATA 0-15
. _• • • • •- .

"FIFO"
INPUT

DIRECT

RE~ft_?ER

./

I'"

PARALLEL DATA 0-15

r

14--I11III-_
0-15

'f'..~

•••
SERIAL TO
PARALLEL
CONVERSION

DIRECT READ REGISTER TO
PROCESSOR BUS ENABLE

READ/wRITE
SELECTION

SERIAL DISK
DATA IN

READ
DATA
BUFFER
F/F'S

i

I
(B) 138628

Figure 2-8. Simplified Data Flow for Verify Record Header Operation

-

SERIAL READ DATA

FROM SELECTED!

3~~~ &':.~~ICA'READ CLOCK

~------~

946262-9701

The FIFO buffer is not used while reading record headers. Instead, each word is loaded into the
direct read register and then transferred over the processor bus to the M-bus inputs of the ePE
array. The data and clock inputs to the direct read register are wired in parallel with the FIFO input.
The FIFO buffer is not required when reading record headers because there are no TILINE data
transfers required. It is the variable data rate of the TILINE, which is shared by multiple, competing
masters, which imposes the need for a FIFO in the disk controller. The microprogram and the ePE
array operate much faster than the disk data rate, so the FIFO is not needed for this operation.
2.4 DISK CONTROLLER MICROPROGRAM CONTROL
The 512-word microprogram is always running when power is applied to the controller. The
microprogram consists of 40 routines and subroutines which perform internal "housekeeping"
operations, control the acceptance of WO-W7, run controller self-tests, and execute the operations
specified by the control words.
2.4.1 MICROINSTRUCTION FORMAT. The 40 output bits of the microprogram read-only
memory, ROMOO-39 are collectively called the ROM bus. These microinstruction bits control every
aspect of disk controller operations, including clock control, bus source/ destination control,
initiation of TILINE master cycles, initiation of disk interface operations, control of ePE array
arithmetic, and logical and bit testing functions, among others.

NOTE
Because the microinstructions control so many functions distributed
throughout the controller logic, and because of their critical
importance in directing operations, a thorough understanding of
microinstruction capabilities and format is necessary to understand
the disk controller logic.
The microinstruction format is shown in figure 2-9. The first sheet of this drawing shows the overall
functional grouping of microinstruction bits into 12 main fields and six subfields (special fields).
Detailed breakdowns of each field describe the function performed by each possible bit combination
within the field.
Each microinstruction field is briefly described below.
2.4.1.1 CPE Conditional Clock - ROMO. Bit 0 is the ePE conditional clock control. It may be
used to stop the ePE clock so the ePE can perform nondestructive t~sting of data. No ePE register
contents are changed in the absence of the clock pulse. The ePE clock is stopped as part of a
conditional branch or conditional return instruction. The test bit is checked during the interval that
the ePE clock is stopped, and the test bit determines the next microprogram address. Note that only
the clock input to the ePE array is stopped. Clock pulses to the other microcontroller logic,
including the microprogram address generator, remain enabled.
2.4.1.2 CPE Function Control Field (F and R Fields) - ROMOI-07. The ePE function control
field controls the function code inputs, F6-FO, of the 3002 ePEs. The function code consists of a
three-bit function field and a four-bit register field. The function field selects one of the eight Fgroups, or function groups, of the 3002 ePE. The F-group determines the type of ePE operation.
The four-bit register field selects one of the 12 ePE internal registers for the operation. The ePE
registers are divided into three R-groups, R-Groups I, II and III. The transfer and accumulator
registers are the only registers in R-Group II and R-Group III. They are also included in R-Group I.
Refer to the detailed 3002 ePE data for the ePE instruction set.

2-16

Digital Systems Division

RO MO

2

1

~LKI,

3

I

4

5

I

I

F

6

8

7

I

I

I

R

I

WS

I

V

0

9

I

I

1

12

I
KC

Ic.

13

I

14

1"

I

I

BUS
SOURCE

'"'

16

IENSLV

17

I

18

I

19

20

I

21
I

BRANCH

DEST

1

22

23

I

,

24

,

25

26

27

I

28

29
I

I

30
I

31
I

32

33

I

34

I

NEXT ROM ADDRESS

35
I

36

37

I

I

38

I

39

I

IMMEDIATE
TILINE \SPECIAL
OP
G:~~P

3002 CPE
FUNCTION CODE

SPECIAL
FUNCTION 0
SPECIAL
FUNCTION 1
SPECIAL
FUNCTION 2

'-------~
IWS FIELD

CLK
FUNCTION

COMMENT
BITS8. 9

BIT 0
0

NOP

1

CLKSTP

NO FUNCTION -

CLOCK REMAINS ENABLED

STOPS CLOCK INPUT TO CPE SO THAT OUTPUTS OF

8~~~YFO~H~b~-~~~.f~u"~;I't~E~~S~II~~U b~R6A~~: B~O

CPE REGISTER CONTENTS ARE CHANGED IN THE
ABSENCE OF THE CLOCK PULSE.

-

FUNCTION

COMMENT

0

0

WORD

CPE CARRIES ARE CONFIGURED FOR FULL 16 BIT WORD
OPERATIONS

0

1

SHIFT WORe

CPE SHIFT LINES CONFIGURED FOR FULL WORD RIGHT
SHIFT

1
1

0
1

LEFT BYTE
RIGHT BYTE

CPE LEFT BYTE OPERATI':.NS (INCLUDING SHIFT)
CPE RIGHT BYTE OPERATIONS (INCLUDING SHIFT~

'F-FIELD

K·-BUS CONTROL FIELD

N
I

-...J

SPECIAL
FUNCTION 3

WO RD SELECT FIELD~

CPE CONDITIONAL CLOCK

F-GROUP

R?r6~'

ROM02
(F5)

ROM03
(F4)

0
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

2

3
4
5
6
7

I

R-FIELD

BIT POS ITIONS
R-GROUP

CPE
REGISTERS

I

Ro
R,
R2
R3
R4
R5
R6
R7
R8

~9

AC

ROM04
(F3)
0
0
0
0
0
0
0
0
1
1
1

1

THE 7-BIT FUNCTION CODE FOR THE 3002 CPE
CONSISTS OF A 3-BIT FUNCTION FIELD AND A
KC FIELD
4-BIT REGISTER FIELD. THE FUNCTION FIELD
SELECTS 1 OF THE 8 FUNCTION GROUPS. THE
REGISTER FIELD SELECTS ONE OF THE 11 CPE
31TS10 11
SCRATCHPAD REGISTERS (RO-R9. T) OR THE
CPE ACCUMULATOR REGISTER (AC). THE CPE
0
0
REGISTERS ARE DIVIDED INTO 3 GROUPS. THE
T AND AC REGISTERS MAY BELONG TO ANY GROUP
DEPENDING ON THE CODE USED IN THE R-FIELD.
THE OPERATION PERFORMED BY THE CPE IS
DETERMINED BY THE F-GROUP. THE R-GROUP.
0
1
AND THE MASK DATA ON THE K-BUS. REFER TO
THE CPE INSTRUCTION SET DESCRIPTION.
NOTE THAT THE PROCESSOR CONTROL BUS
NUMBERING ROMO 1-07. RUNS COUNTER TO THE
MICRO-FUNCTION BUS NUMBERING. F6-FO.
1
0
WITHIN THE CPE DEVICES.
1

ROM05
(F2)

ROM06
(Fl )

ROM07
(FO)

0
0
0
0
1
1
1
1
0
0
1

0
0
1

0
1
0

1

1

0
0

0

1

0

1

1

1
0
0
0
0
1

1\

T
AC

1
1

0
0

III

T
AC

1
1

1

1

1
0

1
0
1

1

FUNCTION

COMMENT

FFFF - K.
ENSPEC

LOADS ALL ONES INTO CPE K BUS INPUTS.
ALSO ENABL.ES DECODING OF SPECIAL FIELI:'S
(TILINE OP SPECIAL GROUP. AND SPECIAL
FUNCTION) IN BITS32-39.

OOOO-K.
ENSPEC

~E~gSE ~~~L.~~Rg~c~J~N~ ~~ ~-P~lf:1AI~ ~~~E[IS
(TILINE OP. SPECIAL GROUP. AND SPECIAL
FUNCTION) IN BITS 32-39.

1M

-K

LOADS INVERTED IMMEDIATE OPERAND FIELD
INTO CPE K-BUS INPUTS.

rM-K

HEXADECIMAL
EQUIV.
0
1
2
3
4

C

5
6
7
8
9
C
D

1

0

1

A
B

1
1

0
1

E
F

CI
BIT 12

CARRY IN FIELD

FUNCTION

0

1 -CI CARRY/ONE-FILL

1

O-CI NO CARRY/ZEROFILL

COMMENT
CONTROLS THE CARRY INPUTS TO THE CPE
DEVICES AS SPECIFIED BY THE WS FIELD.

~fcc~~~~~.?i.f16"JRm~TMGJ.f ~~I~~~~:

--

(B) 138252 (1/4)

Figure 2-9. Microinstruction Format

PROCESSOR BUS SOURCE FIELD

BITS

13 14 IS

BC

BUS
SOURCE

COMMENT

0

0

0

ZEROS

ALL ZEROS TO PROCESSOR BUS (PBUSOO-I,5)

0

0

1

CPE WORD

CPE LEFT BYTE TO PBUSOO-07 • RIGHT BYTE TO PBUS08- I 5

0

1

0

EXTERNAL

FLOATING BUS -

0

1

1

TILINE

TILINE OATA TO PROCESSOR BUS

~

0

0

DSKDATA

1

0

1

UNDEFINED

1

1

0

DSKSTATUS

1

1

1

UNDEFINED

-

FUNCTION

COMMENT

0

0

UNCONDITIONAL INCREMENT TO CURRENT
ADDRESS + 1

0

0

1

~~~~S~'t~AI~R8~lc'tOM6gt~~~Ei~~~~~I~~F:J~DDhR,1CTREAD

UNCONDITIONAL BRANCH
TO NEXT ROM ADDRESS
(NRA)

0

1

0

CONDITIONAL BRANCH IF
TRUE TO NEXT ROM
ADDRESS (NRA)

TESTBITQ TRUE TO ENABLE BRANCH. OTHERWISE
INCREMENT ADDRESS

STATUS BITS FROM DISK DRIVE TO PROCESSOR BUS

0

1

1

CONDITIONAL BRANCH IF
FALSE TO NEXT ROM
ADDRESS (NRA)

TESTBITQ FALSE TO ENABLE BRANCH, OTHERWISE
INCREMENT ADDRESS

1

0

0

UNCONDITIONAL BRANCH
AND LINK TO NEXT ROM
ADDRESS (NRA)

CURRENT ADDRESS +1

1

0

1

CONDITIONAL RETURN IF
T~~~l::ANCH TO NRA

RETURN TO THE ADDRESS STORED IN THE STACK OF
THE SN74S482 MCU ADDRESS GENERATOR IF
TESTBITQ IS TRUE, FOR TESTBITQ FALSE. BRANCH
TO NRA.

1

1

0

CONDITIONAL RETURN IF
~#.,.~'tl:: BRANCH TO NRA

RETURN TO THE ADDRESS STORED IN THE STACK OF
THE SN74S482 MCU ADDRESS GENERATOR IF
TESTBITQ IS FALSE. FOR TESTBITQ TRUE. BRANCH
TO NRA.

1

1

1

UNCONDITIONAL RETURN

RETURN TO THE ADDRESS STORED IN THE STACK OF
THE SN74S482 MCU ADDRESS GENERATOR.

TILINE SLAVE CONTROL

TO STACK

~~~E~l~'6'k-b~~~~tsM. A~~~E~ivf~tf~'6DN'+~lt?S) AI~.?~6~~M~~~/~cipS~'?~:?i6'6lJ. ~3~iT-S
PLEXER AND OUTPUT REGISTER.
DESCR IPTIONS.

REFER TO THE SN74S482 AND BRANCH CONTROL ROM

THE OCCURRENCE OF A TRAP WILL STORE THE BRANCH ADDRESS DETERMINED ABOVE IN THE
STACK AND CAUSE A JUMP TO THE TRAP ADDRESS. WHICH REPLACES THE NRA FIELD.

ENSLV
BIT
16

BITS
17 18 19
0

NO DATA TRANSFER VIA PBUS

t;J

00

BRANCH CONTROL FIELD

FUNCTION

COMMENT

0

NOP

DISABLE TILINE SLAVE

1

ENSLV

ENABLE SLAVE FLIP-FLOPS TO EXECUTE A SLAVE CYCLE
IF REQUESTED BY AN EXTERNAL TILINE MASTER. SUCH
AS THE 990 PROCESSOR,

PROCESSOR BUS DESTINATION FIELD

BITS
20 21

o

NOP

NO FUNCTION

0

I

UNITLOAD *

LOAD DISK UNIT SELECT SIGNALS INTO THE UNIT
SELECT REGISTER

1

0

FIFO*

LOADS,CPE OUTPUT WORD INTO FIFO FOR TRANSMISSION TO DISK. NOT REQUIRED FOR TILINE
TO DISK TRANSFER

1

1

CYL ADDR*

LOADS CPE OUTPUT WORD INTO DISK ADDRESS
SELECT REGISTER

cO'

-

iif

COMMENT

FUNCTION

0

0

*
(B) 138252 (2/4)

Figure 2-9. Microinstruction Format (Sheet 2 of 4)

COMMAND IS STROBED ON NEXT MICROPROCESSOR CLOCK
(MPCK-) PULSE.

IMMEDIATE OPERAND

FIE~

KC = 1 (lOR 1 1

m

FIEL.D
COMMENT

BITS
32--39

THE 8-BITS OF THE I~MEDIATE OPERAND FIELJ) ARE APPL.IED

l2cTr~,~-Jl~~~~W "~&1~ ?:Vl~~E'6CJ~V¥H~r~p~Y~BUS
INPUTS.

I

NEXT ROM ADDRESS FIEL.DI

I

NRA
22 23 24 25 26 27 28 29 30 31

I

THE NEXT ROM ADDRESS FIEL.D. ROM22-31. IS USED TO SUPPL.Y BRANCH ADDRESSES
AS DESCRIBED WITH THE BRANCH CONTROL. FIEL.D. BIT 22 IS A SPARE.
WHEN A TlL.INE SL.AVE TRAP OCCURS. THE NRA BITS ARE REPLACED AS FOL.L.OWS:
NRA 23

o

24

25

26

27

TIL.INE
SLAVE
ACTIVE(1 )

I

28

29

30

31

TIL.INE ADDRESS. 3 L.SB

READ-

WHEN AN INTERRUPT TRAP OCCURS. THE NRA SITS ARE REPL.ACED AS FOL.L.OWS:

NRA 23

I

0

24
TIL.INE
SL.AVE
ACTIVE(O)

1

25

26

INTERRUPT
ADDRESS

27

I

28

29

30

31

0

o

o

o

I
TIL.INE CONTROL. FIEL.D

~

KC = OOOROI
BITS
33

32

FUNCTION

COMMENT

0

0

NOP

NO FUNCTION

0

1

SL.VTRM

::::t:~~ ~t~~~ ~b~\~~~~Sl,~~Mf~tJ,1:'T1:~UJI~~TE

1

0

MSTRD

TIL.INE MASTER READ. CAUSES TILINE MASTER
L.OGIC TO GAIN ACCESS TO THE BUS AND READ ONE
WORD FROM COMPUITER MEMORY.

1

1

MSTWT

TIL.INE MASTER WAITE. CAUSES TIL.INE MASTER
L.OGIC TO GAIN BUS; ACCESS AND WRITE ONE WORD
TO COMPUTER MEMORY

(TL. TM-) SIGNAL.

(B) 138252 (3/4)

Figure 2-9. Microinstruction Format (Sheet 3 of 4)

GROUP SELECT AND SPECIAL FUNCTION FIELDS
KC

OOOROI

BIT
37 38

39

0

0

0

0

NOP

RST TE STMODE

RST SPAREOUTI

0

0

0

1

CLK STOP MASTER

SET TESTMODE

SET SPAREOUTI

36

SPECIAL FUNCTION 0
(BITS 34, 35
00)

=

SPECIAL FUNCTION 1
(BITS 34,35
01)

=

SPECIAL FUNCTION 2
(BITS 34, 35 ~ 1 0)

SPECIAL FUNCTION 3
(BITS 34, 35 ~ 11)

0

0

1

0

CLR DSK I/F *

SET TESTCLK

RST RESTORE

BIT 36

0

0

1

1

MSB ADDR LD

RST TESTCLK

SET RESTORE

OUTPUT TO DISK.

0

1

0

0

STOP VFCONTROLLER*

RST I/F WRT

RST ERASE

BIT 37

0

1

0

1

MSB ADDR INCREMENT*

SET I/F WRT

SET ERASE

CHARACTER GENERATOR TO ALL I'S.

0

1

1

0

Cl.R SECT/INDEX F/F'S*

RST DIRECT MODE

RST WRITE GATE

0

1

1

I

NOP

SET DIRECT MODE

SET WR ITE GATE

~

BIT 38 :

1 ENABLES CRC

1 PRESETS THE CRC

I LOADS A SPEC IAL FLAG

BIT INTO THE FIFO TO DETECT

NI
N

o

I

0

0

0

START IIF CONTROLLER*

RST TILINE INT

RST READ

1

0

0

I

NOP

SET TILINE INT

SET READ

I

0

1

0

TRIGGER TIMER RESET

SET BUSY

RST SPAREOU"T2

1

0

1

1

NOP

RST BUSY

SET SPAREOUT2

RST HEADSEL .

I

1

0

0

RST DIRECT READY *

SET FAULT

I

1

0

1

NOP

RST FAULT

SET HEADSEL

1

1

1

0

CLR DISK CONTROL

SET DIAG FAULT

RST ADDSTB

I

1

1

1

NOP

RST DIAG FAULT

SET ADDSTB

ROM 36 -

39 ARE MULTIPLE PURPOSE CONTROL BITS.

BITS 34 AND 35 STEER THESE 4 OUTPUT BITS TO THE CCR;/":CT GROUP OF CONTROL
GATES AND FLIP-FLOPS.
COMMAND IS STROBED ON NEXT MICROPROCESSOR CLOCK

(MPCK-) PULSE

o

--

<9:
m

(8)138252

BIT 39 IS A SPARE FLAG BIT

THEY ARE USED PRIMARILY FOR

CONTROLLING OUTPUTS TO THE DISK DRIVE.

*

WHEN A STOP CONDITION IS PRESENT.

(4/4)

Figure 2-9. Microinstruction Format (Sheet 4 of 4)

~------~

946262-9701

2.4.1.3 Word Select Field - ROM08, 09. The CPE array is subdivided into two eight-bit blocks, the
left byte and the right byte. The interconnection between the bytes and the carry and shift logic is
controlled by the word select field. This field also controls the CPE clock modes and the K-bus
configuration. The word select field can configure the array for left byte, right byte, full word, or
right-shift word operations.
2.4.1.4 K-Bus Control Field - ROMI0-l1. The K-bus control field selects the input to the mask bus
(K-bus) inputs of the CPE array. That input may be a hardwired all zeros or all ones code, or it may
be an eight-bit immediate operand (IM-) from ROM32-39. If the immediate operand is not selected,
ROM32-39 may be used for the special function subfields described in subsequent paragraphs.
2.4.1.5 Carry In Field - ROMI2. This field controls the least significant carry-in bit of the active
CPE array, as determined by the word select field. It also selects zero-fill or one-fill into the most
significant active stage during right shifts.
2.4.1.6 Processor Bus Source Field - ROMI3-15. The three-state processor bus (P-bus) is the main
data flow path in the microcontroller. The bus may be driven from anyone of multiple sources.
ROM13-15 enables the three-state outputs of one source to drive the bus. There are three codes
which allow the bus to float during operations which do not require bus transfers. These codes were
used during development to allow an external RAM board to control the bus.
2.4.1.7 TILINE Slave Enable Field - ROMI6. This bit is set to enable the TILINE slave logic to
execute a slave cycle, if requested by an external master such as the 990 processor. This slave cycle
either loads a· control word into a CPE register or reads a status word from a CPE register. The
controller microprogram sets the slave bit while it is idling. After accepting control words and
initiating the operation, slave cycles are disabled to prevent interference to the current operation.
2.4.1.8 Branch Control Field - ROMI7-19. The branch control field of the currently executing
microinstruction specifies how the next microinstruction is to be selected. The next microinstruction
may be at the next sequential address, or at a branch address (specified in ROM22-31) that is selected
unconditionally or on the basis of a bit test in the CPE array. The next microinstruction may be at a
return address stored during some previous branch. Returns may be unconditional, or they may be
selected as the result of a bit test within the CPE array.
2.4.1.9 Processor Bus Destination Field - ROM 20,21. The processor bus destination field enables
one of three registers to accept data from the processor bus. These registers are the disk unit select
register, the FIFO input stage and direct register, and the cylinder address register.
2.4.1.10 Next ROM Address Field - ROM22-31. The next ROM address field supplies the branch
address for conditional or unconditional branches specified in ROM 17-19.
2.4.1.11 Immediate Operand Field - ROM32-39. The eight bits of the immediate operand field are
supplied to the mask (K) bus inputs of the active CPE byte. Each bit is inverted by the CPE K-bus.
To enter a mask of FF 16 , 00 16 must appear in ROM32-39.

If the entire 16-bit CPE array is active, the immediate operand is loaded into the right (less
significant) byte and the sign (MSB) is extended to the left byte K-bus inputs.
Typical applications of the immediate operand field include supplying constant numerical values,
loading initial loop counts or shift counts, and masking status words to test specific bits.

If the K-bus control field commands all zeros or all ones into the CPE K-bus inputs, no immediate
operand value is needed. This frees bits 32-39 to serve as subfields of the microinstruction. These
fields are: TILINE operation control, special group select, and four special function fields, as
described below.

2-21

Digital Systems Division

~------~

946262-9701

2.4.1.12 TILINE Control Field - ROM32-33. This field controls the initiation of TILINE master
read or write cycles, and the termination of TILINE slave cycles.
2.4.1.13 Special Group Select Field - ROM34-35. This field selects one of the four special function
decoders that operate on the ROM36-39. In other words, the group select bits specify which special
function (1-4) occupies the last four bits of the microinstruction.
2.4.1.14 Special Function Fields (0-3) - ROM36-39. These fields control a variety of individual
signal lines and control flip-flops, primarily for interface control. Refer to the last sheet of the format
drawing for a detailed breakdown of these functions.
2.4.2 MICROPROGRAM ORGANIZATION. The disk controller microprogram is organized into
13 major routines and a large number of subroutines which may be accessed repeatedly or nested
within the course of executing a major routine.
Each routine or subroutine is assigned a three-letter mnemonic, as shown in table 2-1. Flowcharts for
these program segments are included in Appendix e, and a complete microcode listing is in
Appendix D. Both the listing and the detailed flowcharts use the mnemonic and a two-digit
instruction number to uniquely identify each microinstruction. Microinstruction addresses are also
supplied on the listing and the flowcharts.
Figure 2-10 is the principle flowchart, which shows the overall program organization and the
relationship between the major routines.
In the absence of any current operation, the controller microprogram continually executes the idle
(IDL) loop. The idle loop takes about 1.5 microseconds for each pass (5 microinstructions at 300
nanoseconds per clock cycle). The enable slave bit is set during the entire loop, so that a control word
may be loaded (or status word read) via a TILINE slave cycle. The idle/busy bit is checked on each
pass to determine if a controller operation has been commanded (W7, bit 0 = 0).
When the 990 computer addresses the disk controller with a write operation, and a slave operation
(ROM 16) is enabled, the controller jumps to a trap address and executes a slave write (SWR)
routine. There are eight different slave write routines, one for each control word address. When the
control word has been loaded into the ePE internal register, the slave write routine issues a slave
terminate command and returns to the idle loop. In the special case of a W6 control word, the slave
write routine performs logical unit selection before returning to the idle loop.
The 990 computer may also read any of the eight slave registers, causing the controller
microprogram to jump to one of the eight slave read (SRD) routines. When the controller has
enabled the data word into the TILINE, it issues a slave terminate signal.
As a typical example, assume that a slave write 7 routine has loaded a control word with the idle bit
reset. On the next pass through the idle routine, a mask and bit test instruction detects the state of the
idle bit, and causes a branch to the initialize routine.
The initialize routine (INI) sets the busy latch and resets the slave enable. Any subsequent attempt to
perform a slave write will be rejected, and a slave read will be answered by a simulated W7 word. The
INI routine proceeds to clear the interrupt latch and controller status in W7 (except the interrupt
enable bit). The microprogram then branches to the self-test routine, ZDT. The self-test is not shown
on the principle flowchart. Any mnemonic which starts with a capital Z, (ZDT, ZER, ZEH and so
on) identifies a self-test instruction.

2-22

Digital Systems Division

~
946262-9701
J17~
_
_

_ _ _ __

Table 2-1. Mnemonics for Microprogram Routines and Subroutines
Mnemonic

RoutineiSubroutine Name

CCS

Check CRC and Stop

DST

Delay Start

DWS

Disk Write Start

HCU

Head/Cylinder Update

INC, FAV

Increment

IDL

IDLE

INI

Initialize

iNT

Interrupt Traps

LTC

Long Test Check

RDD

Read Data

RDU

Read Unformatted

RST

Restore

RUP

Record Update

SDS

Search, Delay, Start

SKS

Seek Subroutine

SRD

Slave Read

SWR

Slave Write

SRG

Store Registers

SRW

Store Registers Write

SSS

Start Sector Search

SSX

Secondary Start Transfer

STX

Start Transfer

TRM

Terminate Routine

VID

Verify ID Words

WCS

Write CRC and Stop

WFT

Write Format Track

WHD

Write Header

WRD

Write Data

WRU

Write Unformatted

WST

Write Stop

ZAC

Z Abort Check

ZDR

Z Direct Register

ZDT

Z Diagnostic Test

ZER

Z Error Routine

ZRF

Z Register Fill

ZRH

Z Read Header

ZRT

Z Register Test

ZSU

Z Status Update

ZTC

Z Test Clock

2-23

,A~C

and FIFO Available

Digital Systems Division

~------~

946262·9701

ABORT
INTERRUPTS
INT

TERMINATE
ROUTINE
TRM

TILINEROUTINES
SLAVE
READ
SRD

~

"~
\~''------I

TILINE SLAVE
WRITE
ROUTINE
SWR

r?

IDLE LOOP

IDL

,
INI TIALIZE
ROUTINE
INI

(SEEK) SKS

STORE
REGISTERS
SRG

READ DATA
ROD

,

,

WRITE DATA
WRD

UNFORMAT
READ
RDU

RESTORE
RST

--

.::1

w

I

iJ'i

Ir

:t:
,,',

UNFORMAT
WRITE
WRU

'"'
:t:
~J

w
~~

~
«

~

'-

FORMAT
WFT

""
a:
I-

«
0

Lll

!:
r

,

a:

,Ir

~

,

I

~r

SUBROUTINE
"POOL"

(B) 138273

Figure 2-10. Microprogram Principal Flowchart

2-24

Digital Systems Division

~------~

946262-9701

Upon successful completion of the self-test, control returns to the INI routine, which performs those
operaiions ihai are common io all ihe disk commands. When ihis common segment is finished, INI
decodes the command (W 1, bits 5-7) and branches to the store registers, read data, write data, read
unformatted or restore routine. A SEEK command causes a branch to the terminate routine.
Each of the major command routines ends at the terminate routine, which performs common
housekeeping functions, then updates the disk controller status word, W7, before returning to the
idle loop.
2.5 CONTROLLER TIMING
"'JI"Pr"v
~r~n"~pll'l1
;n th~ D~l
rt;~k
lY.l ,-,.1'\..-, I~s "" .... e ""f' hun 1-'''.1.l''~''
.. ~ t;Tn;ng
"'.u........... tl'llrTnS
.....,........ l1Sl'lIrt
y...,~ ............ ...,
....,... 0 ~
. . '" "" "on...,
troller. Microprocessor clock and its derivatives are used for clocking, gating, enabling, and synchronizing the controller functions which do not directly interface with the disk drive. MPCK482-,
for example, is the timing term which causes the microprogram address generator to fetch the next
4O-bit microinstruction from control memory. Disk interface timing is described with the disk interface logic.

-- - -- Cl-~lK
IVllcr0 prU\,;e:sSUI
. U\,; ,

'-,!"!

VI.l

V.l

"'\'TV

.0..&

2.5.1 MICROPROCESSOR CLOCK - GENERAL. The clock pulse, MPCK-, is an 80nanosecond active-low pulse. The results of CPE operations are stored in the CPE registers on the
leading (negative-going) edge. The TTL logic external to the CPEs is clocked on the trailing
(positive-going) edge of the pulse. The period between successive M PCK - pulses is determined by the
type of operation in progress.
The microprocessor clock logic has three operating modes: free-running, TILINE-triggered, and test.
The free-running clock consists of a constant-period waveform with a period of 300 nanoseconds.
The TILINE-triggered clock has a variable period which is determined by the completion of TILINE
operations. The test mode allows the clock to be held inactive by an external state board.
During normal operations, the controller clock changes from free-running to TILINE-triggered to
free-running with no hitches or cycle losses. If the controller operated solely on a free-running clock,
. there would be, on the average, one half of a clock period wasted for each TILINE transfer. The
TILINE-triggered clock avoids this time waste by restarting the clock immediately at the end of the
TILINE transfer. Also, holding off the clock during a TILINE cycle prevents waste of controller
states during the message operation.
The timing circuit is based on three RC delay timers, a latch and associated gating circuitry. The time
delays inherent in the TTL gates and those due to the three delay timers determine the pulse width
and period of the MPCK- waveform. The timing circuit is very similar to the main timing circuit on
the 990/10 AU2 board.
Figure 2-11 is the schematic of a typical delay timer circuit. With a low input signal, the SN7407
open-collector buffer holds the capacitor close to zero volts. When the input signal goes high, the
capacitor starts charging (through the resistor) toward +5 volts. When the capacitor voltage reaches
the positive-going threshold voltage of the SN74132 Schmitt-trigger NAND gate, the circuit output
goes low. The time between this negative transition at the output and the positive transition at the
input is the timer delay.
The timer output remains low until the input signal drops low. The output goes high as fast as the
SN74132 can switch. The capacitor is discharged through the open collector output circuit of the
SN7407. This discharge time, which is much faster than the charge time, determines the minimum
retrigger time for a reliable delay. Notice that the input pulse must be longer than the delay time to
get an output from the circuit.

2-25

Digital Systems Division

946262-9701
Jd7)\ _
_ _ _ _ __
~

vee
R

74132

INPUT

:+

OUTPUT ____~I~-------------~

DELAY,A

+1_____

(A) 135693

Figure 2-11. Delay Timer Circuit

2.5.2 DETAILED DEVELOPMENT OF MPCK-. This description of microprocessor timing
development is keyed to the simplified logic drawing, figure 2-12, and the timing diagram, figure
, 2-13. The description starts at a convenient point in the timing cycle and continues until the same
conditions are reached.
Assume that CLKT2- is high so that it will be possible to set the clock on latch, and that the clock
circuit is not inhibited by the CLKINH or SLTMA- signal. CLKT3- from delay 3 goes low to enable
CLKEN and CLKSTRT-. The CLKON output of the clock latch goes high and. since CLKT2- is
high, the clock latch sets.
The CLKON signal performs the following three functions:
•

Disables the CLKSTRT- signal via the CLKOFF inverter and the output gate of the delay
3 timer (delay 3 is not initiated yet). The pulse width of CLKSTRT- is approximately 55
nanoseconds, all due to gate delays.

•

Combines with CLKTI- to enable the MPCK-, MPCK, and MPCK482- timing pulses.
These pulses remain active until delay 1 expires.

•

Initiates delay 1, which determines clock pulse width.

Delay I expires (CLKTI- goes low) 80 nanoseconds after the clock on latch sets. When delay 1
expires, the clock pulse has been produced and all the remaining operations are concerned with
setting the period of the clock waveform.
The inverted form of CLKTI- initiates the delay 2 timer, which clears the CLKON latch after
approximately 20 nanoseconds. An external test input to the delay 2 timer allows the clock to be held
for single stepping.
2-26

Digital Systems Division

~~.-----------------------------~-----------~

946262-9701

CPE CONDITIONAL CLOCK
FROM MICROINSTRUCTION

ROMOO

CLKSTP(CLOCK STOP)

FROM
INTERRUPT
LOGIC

TRAP

FROM WORD{
SELECT
FIELD

(RIGHT BYTE ONLY)

(RIGHT BYTE ONLY)

(ROM08~09)l

CLKSTP-

LFBYT-

bF8YT-

DI="COnINr.:

RTBYT

RTBYT-

RTBYT-

(LEFT BYTE ONLY)

(LEFT BYTE ONLY)

CPE LEFT
BYTE CLOCK

CPRCK-

CPE RIGHT
BYTE CLOCK

CLKT1-

CLKON

CLKON

CPLCKCLKON

LFBYTCLKSTPCLKON

CLKT3-

DELAY 3
125NSEC

CLKT1RETRIGGER DELAY
FROM MICROINSTRUCTION
SPECIAL
GROUP 0
DECODERS
(ROM34-39=

000001)

CLKSTPMST(CLOCK
STOP
MASTER
CYCLE)

CLKON
MPCKCLKT1-

CLKINH
CLKT1MPCK482CLKON

CLKSTRTCLKON

FROM TI LI NE _M
__
D_A_C_T_-_ ___.....____.....
MASTER LOGIC (MASTER
DEVICE
ACTIVE)
SLTMAFROM TILINE
SLAVE LOGIC
(SLAVE TERMINATE ACCESS)
CLKT 1-

MICROPROCESSOR
CLOCK

CLKT1-

DELAY 1
80NSEC

CLKON

MPCK

PU LSE WIDTH CONTROL

CLKT2-

TRANSPARENT
D-LATCH
P/O PBUS
CONTROL
REGISTER

CLKTl

PBUSEN
CLKRUN

TEST SOCKET

PBUSENL
D

Q~---+----------------------------------------------------~

TO PROCESSOR
BUS (PBUS)
SOURCE CONTROL
DECODER

ENABLE
FROM TILINE
MASTER LOGIC

(c) 137632

MDACT-

MDACT-

CLKT 1-

CLKT 1-

Figure 2-12. Microprocessor Clock (MPCK-) Logic
Simplified

2-27/2-28

Digital Systems Division

A.

MPCK-

B. PROCESSOR BUS ENABLE AND MICROPROCIESSOR CLOCK
COMPARISON
I
300±10
I

MICROPROCESSOR CLOCK PARAMETERS

:.,

300±10
NSEC

+

I

~

MP~~

I

I
________

80--5
- - : N SEq'4-

I

I~

PBUSENL.

:

I

C.

-t~

NSEC

U

~
+

+ I

I

....: 1 00-5 1+ 120-!')!4I NSEC I
NSEC I

MICROPROCESSOR CLOCK DEVEL.OPMENT

NOTE: PULSE
WIDTHS AHE
MEASURECI
AT THE 1.4
VOLT LEVEL.
OF THE
RISING/
FAL.LlNG
EDGE

(EXPANDED SCALE'

1

CLKEN

CLKSTRT-

CLKON
CLOCK LATCH
CLKT1PULSE WIDTH

NI
N
\0

RESTART
:::::::80 NSEC
DELAY

MPCKMICROPROCESSOR
CLOCK

CLKT2-

CLKOFF

(CLKON-~

1"="_--___- -

'\,

CLKT3RE-TRIGGER
DELAY

:::::::125 NSEC DELAY

~-------'r-:OLDING
STATE
IF CLOCK DISABLED
FOR TI LINE OPERATION

PROCESSOR

E~~~LE

{

CLKTl
PBUSEN

----------------~I\
...
I_~~

~I~~\------------~J~l---------------------•

_________~I~----------------------~I )

.~

DEVEL.OPMEN

PBUSENL

•

-------------------------------------~I

+

-1~------------------~t ~l-------------------------------

(B) 137643

Figure 2-13. Timing Diagram -

Microprocessor Clock

~------~

946262-9701

When the CLKON latch clears, delay 3 (125 nanoseconds) is initiated. The clock circuit cannot
retrigger until delay 3 expires to partially enable the CLKEN gate. Delay 3 guarantees that there is
adequate time for the capacitors in delays 1 and 2 to return to the initial (discharged) state.
At the expiration of delay 3, the circuit is back in the initial state. If the clock is not inhibited by
CLKINH or SLTMA-, the clock circuit retriggers when CLKT3- goes low (free-running mode).
If the clock is inhibited, the circuitry remains in the holding state until the inhibiting condition is
removed. This is the TILINE-triggered mode. The effect of a TILINE cycle on the clock waveform is
shown in figure 2-14.

2.5.2.1 TILINE-Triggered Mode. Microprocessor clock may be inhibited and then restarted during
either a slave or a master cycle. In either case, the inhibiting signal is controlled by a field in the 40-bit
microinstruction, and logic conditions in the TILINE interface.
A TILINE slave operation is initiated by the 990 CPU in an attempt to load a control word into a
CPE register (slave write) or read a word from a CPE register (slave read). The controller responds
to the slave read or write request if the ENSL V bit (ROM 16) of the microinstruction is set and the
TILINE address compares to the slave address switch settings. The controller microprogram traps to
a slave read or slave write routine.
During a slave read, for example, the requested data is moved from the ePE register to the
accumulator and enabled out to the TILINE drivers. At this point, the microprogram issues a slave
terminate command (ROM 32, 33 == 00). The SLVTRM- output of the decoder stops the
microprocessor clock by forcing the slave terminate access (SLTMA-) signal low, and also sends a
TILINE terminate (TL TM -) signal to the 990 CPU. The controller state remains fixed, with the data
on the output lines, until the 990 CPU indicates that the transfer is complete by disabling the
TILINE go (TLGO-) signal. Microprocessor clock is restarted when the TLGO- forces SL TMAhigh again, and the microprogram begins executing again.
The operation is similar for a slave write, except that the TILINE data is loaded into the CPE
accumulator, transferred to the proper register, and then the slave terminate is issued.
Microprocessor clock stops until the 990 CPU acknowledges completion of the transfer by disabling
TLGO-.
Microinstruction bits 32 and 33 enable a master read or master write cycle. The MSB address register
is updated and the CPE devices place the lower 16 address bits on the TILINE address drivers. The
data path between the TILINE drivers/ receivers and the FIFO is established. The microprocessor
clock is suspended by special field 00 == (ROM 36·,-39) == 0001, which enables CLKSTPMST-. The
clock remains inhibited until the word is transferred and MDACT- (master device active) goes high.
A 20-microsecond timer is initiated at the start of each TILINE master cycle. If the TILINE
operation hangs, the timer expires, clearing the TILINE logic and restarting the clock circuit.

2.5.2.2 Microprocessor Oock Output Gating Logic. Refer to the timing outputs at the right side of
the simplified timing logic diagram. CPLCK- and CPRCK- are the gated clock outputs to the CPE
left byte clock and CPE right byte clock, respectively. When enabled, the CPRCK- and CPLCKoutputs coincide with microprocessor clock, MPCK-.
The 3002 CPE devices are connected to perform left byte, right byte, or full word operations, as
specified by the 40-bit microinstruction. The word select field of the microinstruction determines
whether the left byte clock, right byte clock, or both should be enabled. The word select field, ROM
8, 9 is decoded to produce the RTBYT- and LFTBYT- signals. The RTBYT- signal, when low,
disables the left byte clock, so that only the right byte CPEs are clocked. The LFTBYT - signal, when
low, disables the right byte clock.

2-30

Digital Systems Division

~ ____9_46_2_6_2-_9_70_1___________________________________________________
MPCK-

U-----'U
(A) 137633

u

I

I
•10. __ ..1I

~

u u

I

U

r-

CLOCK DELAY·'
DUE TO TILINE CYCLE

Figure 2-14. Microprocessor Clock Delay Due to TILINE Cycle

The clock stop bit of the microinstruction (ROM02) can disable the CPE clock pulse during a
microcycle. This is generally done as part of a conditional branching microinstruction, in which the
important result is the branch (or nonbranch), rather than the value calculated by the CPE. Refer to
the CPE detailed description for more information on nondestructive data testing and conditional
clocking.
The TRAP signal into the NOR gate disables the CPE clock pulse while the address generator
retrieves the new microinstruction at the trap address.
2.5.2.3 Processor Bus Enable Timing. The processor bus enable-latched (PBUSENL) output of the
timing circuits is used to enable the processor bus source decoder. The time delay between the rising
(trailing) edge of microprocessor clock, MPCK-, and the rising edge of PBUSENL is a critical timing
parameter. The rising edge of MPCK- clocks the microprogram address generators, and the
microinstruction outputs become unstable until after the settling time of the address generators and
the microinstruction ROM. PBUSENL remains low, disabling the PBUS source decoder during this
period, and keeping noise off of the processor bus. A 100-nanosecond setting time is allotted, and
then PBUSENL goes high, enabling the PBUS source decoder. Approximately 120-nanoseconds
remain before the leading edge of the next MPCK- pulse. This is adequate set-up time for all devices
which accept data from the processor bus.

The bottom three lines of the timing diagram show the development of PBUSENL, which is essentially a delayed version of CLKTI. The PBUS control register is a "transparent" D-Iatch. As
long as MDACT- remains high (no TILINE master operation in progress), PBUSENL follows
PBUSEN or (CLKTI-, fine line) with only a gate delay. A TILINE master operation latches the
PBUSENL output.
2.5.2.4 Controller Timing Adjustments. The waveforms shown in part B of the timing diagram
illustrate the critical timing parameters. The RC component values in delays 1, 2, and 3 may be
changed to meet the parameters. The adjustments (in order) are:
1.

Pulse width of MPCK-, controlled by delay 1.

2.

Delay from MPCK- rising edge to PBUSENL rising edge, adjusted by delay 2. The
capacitor in this delay is omitted at manufacture. It may be installed if the gate delays
alone are insufficient.

3.

Period of MPCK-, adjusted by delay 3.

2.6 TILINE BUS
The powerful TILINE high-speed data bus architecture is used to incorporate the disk controller
directly into the addressable memory space of the 990 system. The TILINE is an asynchronous, highspeed, 16-bit data transfer bus, with the associated control lines which transfer data between highspeed system elements. These elements include the CPU, the memory, the disk files, and the magnetic
tape transports.

Data is transferred along the TILINE data bus as 16-bit parallel words, accompanied by 20-bit word
addresses. The TILINE is capable of transferring approximately 50-million bits per second.

2-31

Digital Systems Division

~------~

946262-9701

2.6.1 MASTER-SLAVE CONCEPT. There are two classes of devices that connect to the TILINE:
TILINE master devices that initiate data transfers, and TILINE slave devices that generate or accept
data in response to some master device. Data transfers in either direction always occur between one
master and one slave. The central processor is an example of a master device, and a memory module
is an example of a slave device.
A master device initiates data transfers on the bus, which may consist of reading data words from a
slave device or writing data words to a slave. Master devices must compete with each other for access
to the TILINE. A positional priority scheme is used to resolve conflicts between masters. A scheduling scheme allows a master to reserve the next TILINE access during the current operation. This
overlapping reduces the overhead time to transfer bus control between masters. When a master gets
access to the bus, it must place a 20-bit address on the TILINE and exchange "hand-shaking" control signals for each data word transferred to or from a slave device.

Each slave device recognizes a specific range of addresses, and is activated only when the 20-bit
TILINE address falls within that range. Pencil switches on the logic board of the slave device set the
starting address, called the TILINE base address. The slave device accepts TILINE addresses that
range from the TILINE base address to an upper limit determined by the nature of the slave. For
example, an 8K memory module would respond to addresses from the TILINE base address to base
address + 1FFF.
The DSIO disk controller is both a master and a slave device. It acts as a slave when the computer
reads or writes control words WO-W7. These control words provide disk and previous command
status, specify the parameters of a disk operation and initiate the operation. Control words WO-W7
are assigned eight consecutive TILINE addresses, from the switch-selected TILINE base address to
TILINE base address + 7. The controller acts as a master when it performs the disk-to-memory or
memory-to-disk data transfers specified by the control words. Once the controller operation has
been initiated, it operates independently of the 990 processor, and competes with other masters for
bus access each time it has to transfer a data word to or from memory.
2.6.2 TILINE PERIPHERAL CONTROL SPACE (TPCS). The TILINE peripheral control space
is a range of TILINE slave addresses reserved for assignment to peripheral device controllers, such as
the disk controller. The range includes 512 word addresses, extending from FFCOO l6 to FFDFF i6 •
Each peripheral controller is assigned a block of up to 16 addresses in the TPCS. These addresses are
used for the control and status words which are used to set up and monitor the peripheral controller
operations. The disk controller only requires eight slave addresses for control and status words WOW7.
The 990 processor contains a hardware mapping function which maps 16-bit CPU byte addresses
F800 16 through FBFF 16 into the TILINE peripheral control space. This hardware mapping is performed if CPU status register bit 8 is 0, indicating that map file 0 is in use.
2.6.3 TILINE INTERFACE SIGNALS. Figure 2-15 shows the TILINE interface signals in the 990
computer chassis, and table 2-2 defines each of the TILINE signals.
2.6.4 TILINE BUS TIMING - WRITE CYCLE. Figure 2-16 is a timing diagram for a TILINE
write cycle. It applies to any TILINE master and slave devices. It does not include the operations
necessary for the master to achieve access to the bus.

2-32

Digital Systems Division

946262-9701
Ja7)\ _
_ _ _ _ __
~

........
TO ALL TILINE
MASTER OR SLAVE
DEVICES

....

LOGIC VOLTAGES

-

TLPRES-

1'-....

.....".
~

... __ ... -

r"'on
....... n
..,:;;

.......

POWER
SUPPLY

TLPFWP-

TLGOTLREAD
TLADR (0-1 9)
TLDAT (0-15)
TLTMTLMERTILINE
MASTER

FROM CENTRAL
PROCESSOR/
PROGRAMMER
PANEL

TLAG (OUT)

TLGO-

TLAG (IN)

TLREAD

TLAK-

TLADR (0-19)

TLAV

TLDAT (0-15)

TLWAIT-

TLTM-

TLIORES-

TLMER-

TLIORES-

TLGO-

TILINE
SLAVE

TLREAD
TLADR (0-19)

FROM COU PLERS
OR MEMORY

TLWAIT-

TLDAT (0-15)

TILINE
SLAVE

TLTMTLMERTLGOTLREAD
TLADR (0-19)
TLDAT (0-15)
TLTMTLMER-

TILINE
MASTER

TLAG (OUT)

TLAG (IN)
TLAKTLAV
TLWAITTO OTHER
TILINE DEVICES

TLiORES-

(A) 138255

Figure 2-15. TILINE Interface Signals

2-33

Digital Systems Division

~

946262-9701

Table 2-2. TILINE Signal Definitions
Signature

Pin No.

Definition

TLGO-

PI-25

TILINE Go: Initiates all data transfers when transition from high (3.0V)
to low (1.0V) occurs. See note 1.

TLREAD

PI-ll

TILINE Read: When high (3.0V) designates a read from SLAVE
operation; when low (l.OV) desIgnates a write to SLAVE operation ..
See note I.

P2-55
P244
P2-51
P2-53
P2-57
P2-59
P247
P249
P2-17
P2-19
P2-10
P2-12
P2-11
P2-15
P2-8
P2-9
P2-29
P2-27
P2-25
P2-31

TILINE Address to define the location of data during a fetch or store
operation. When high p2.0V) the corresponding address bit is a zero;
when low (~.8V) the corresponding address bit is a one. See note 2.

TLADROO0102030405060708091011-

12131415161718TLADRI9TLDATOO0102030405060708091011121314TLDATl5-

P2-67
P2-69
P2-35
P2-37
P2-61
P2-63
P243
P245
P2-21
P2-33
P2-23
P2-20
PI-27
PI-28
PI-30
PI-3l

TLTM-

PI-20

TILINE Data: Bidirectional data lines that when high p2.0V) represent
zero data bits, and when low (~.8V) represent one data bit. See note 2.

TILINE Terminate: When low (1.0V) indicates that the SLAVE device
has completed the requested operation. See note I.

Note 1: Received by SN75138; driven by 36 milliampere, minimum, open-collector driver.
Note 2: Received by one, maximum, standard SN74-load per card slot; driven by SN74LS367/8.

2-34

Digital Systems Division

~------~

946262-9701

Table 2-2. TILINE Signal Defmitions (Continued)
Signature

Pin No.

Definition

TLMER-

PI-55

TILINE Memory Error: When low (~.8V) indicates that a nonrecoverable error has occurred during a memory read operation.
See note 2.

TLAG (in)

P2-6

TILINE Access Granted: When high ~2.0V), this signal indicates that
no higher priority device has requested use of the TILINE. When low
(~.8V), this signal prevents the receiving device from gaining access to
the TILINE bus.

TLAG (out)

P2-5

TILINE Access Granted: When high ~2.0V), this signal indicates that
neither the sending device nor any higher priority device is requesting
use of the TILINE. When low (~.8V), this signal indicates that either
the sending device or some higher priority device is requesting use of
the TILINE bus and prevents all lower priority devices from gaining
access to the bus.

TLAK-

PI-71

TILINE Acknowledge: When high (3.0V), this signal indicates that no
TILINE device has been recognized as the next device to use the
TILINE. When low {I.OV), this Signal indicates that some TILINE
device has requested access, has been recognized, and is waiting for
the bus to become available. See note 1.

TLAV

PI-58

TILINE Available: When high (3.0V), this signal indicates that no
TILINE device is using the bus. When low (1.0V), this signal indicates
that the TILINE bus is busy. See note 1.

TLWAIT-

PI-63

TILINE Wait: A normally high (3.0V) signal that when low (l.OV),
temporarily suspends all TILINE MASTER devices from using the
TILINE bus. This signal is generated by bus couplers to allow them
to use the bus as the highest priority user. See note 1.

TLIORES-

PI-14
P2-14

TILINE I/O Reset. A normally high (~2.0V) signal that when low
(~O.8V), halts and resets all TILINE I/O devices. This signal is a
100 to 500 nanosecond pulse generated by the RESET switch on the
control console or by the execution of a Reset (RSET) instruction in
the AU. Driven by SN7437; Received by 2 (maximum) standard
SN74- loads per slot.

TLPRES-

Pl-13
P2-13

TILINE Power Reset: A normally high (~2.0V) signal that goes low
(~O.8V) to reset all TILINE devices and inhibit critical lines to external equipment. The signal is generated by the power supply at
least 10 microseconds before dc voltages begin to fail during powerdown, and until dc voltages are stable during power-up. Driven by
80-milliampere open-collector driver (160 milliamperes with
4O-ampere power supply).

TLPFWP-

Pl-16
P2-16

TILINE Power Failure Warning Pulse: A 7.0 millisecond pulse preceding
TLPRES-. When low (~.8V), this signal indicates that a power-down
sequence is in progress, allowing the AU to perform its power failure
interrupt subroutine. Driven by SN7437; received by two, maximum,
standard SN74- loads per card slot.

Note 1: Received by SN75138; driven by 36 milliampere, minimum, open-collector driver.
Note 2: Received by one, maximum, standard SN74- load per card slot; driven by SN74LS367/8.

2-35

Digital Systems Division

~_
946262-9701
Jd7~
_

_ _ _ __

Table 2-2. TILINE Signal Defmitions (Continued)
Signature

Definition

Pin No.

TLHOLD-

TILINE Hold Signal: A normally high (3.0V) signal that goes low
(l.OV) to assert that a central processor is executing an ABS instruction.
TILINE Hold prevents interference from another processor on the
TILINE while the first processor is performing the ABS instruction.
This signal is used and propagated by TILINE COUPLERS in multiprocessor systems. See note 1.

P2-26

Note 1: Received by SN75138; driven by 36 milliampere, minimum, open-collector driver.
Note 2: Received by one, maximum, standard SN74-load per card slot; driven by SN74LS367/8.

AT MASTER

TLG0-

TLTM-

(R)
*TLREAD

(T)I\'__~________- 4__-+____~1

*TLADR-

"--r----

I.
VALID
!/
(T)I~~~________~~____~II

*TLDAT-

(T)I~,__~V_A_L_I_D____-4__-+____~~

TLMER-

--

AT SLAVE

TLGO-

S; 1 .5!J.s

~~)

\

(R)
TLTM-

(T)
TLREAD

~

"--r~

<120
-NSEC

----

4-

~-,

~L

__

I

L

\ VALID

,

L __

\ VALID

I

~
(R)

TLADR-

__

(R)
TLDAT(R)

~---

TLMER-

NOTES:

NUM 3ERS IN PARENTHESES DENOTE TIM E PERIODS REFERENCED IN TEXT.
TILINE DELAY IS EXAGGERATED FOR CLARITY)
T) " TRANSM ITTED
R) 0 RECE IVED
*+t~6~DIS l~~~~-;"E6'.ND TLDAT- MUST BE STABLE AT THE TIME (OR BEFORE)

~

(A)133122

Figure 2-16. TILINE Master to Slave Write Cycle Diagram

2-36

Digital Systems Division

~------~

946262-9701

The master places the 20-bit slave address and the dtitti word on the lines, with TLREAD low to
specify a write operation. It asserts TLGO- to initiate the operation, and holds TLGO- low for the
duration of the cycle.

All the slave devices on the TILINE receive TLGO- transmitted by the master. The slave devices
must decode the address to determine which slave is being addressed. The slave generates a delayed
go signal (using a timer circuit) and uses that signal to strobe for a valid address decode. It is the
responsibility of the slave device to delay go for a time sufficient to accommodate the worst case
address decode time and the 20-nanosecond worst case TILINE skew.
When the slave device has delayed go and decoded the address as valid, it performs the write cycle
and then asserts TLTM-. At the time the slave device asserts TLTM-, it must be finished with the
TLDAT-, TLADR, and TLREAD signals from the TILINE. The action just described occurs during
time one. This time is defined as the slave access time and should be less than 1.5 microseconds for all
TILINE slaves except the TILINE coupler. When the TILINE master receives the asserted TL TM-,
it must release TLGO-, TLREAD, TLADR-, and TLDAT- within 120-nanoseconds. This occurs
during time two. At this time, the master device may relinquish the TILINE to another master
device. When the slave receives the release of TLGO-, it must release TLTM- within 120nanoseconds as shown in time three. When the master device receives the release of TLTM-, it may
begin a new cycle if it has not relinquished the TILINE to another master device. This is shown as
time four. Most TILINE masters, including the disk controller, only perform one read or write cycle
per bus access.
2.6.5 TILINE BUS TIMING - READ CYCLE. Figure 2-17 is a timing diagram for a TILINE read
cycle. It applies to any TILINE master and slave devices and does not include the operations
necessary for the master to get access to the bus.
The master asserts TLGO- and at the same time generates a valid address (TLADR-) and TLREAD
signal. All slave devices on the TILINE receive the TLGO- transmitted by the master. The slave
devices delay the go signal and decode the address as is done for a write cycle. As in the write cycle, it
is the responsibility of the slave device to delay go for a time sufficient to accommodate the worst
case TILINE skew (defined as 20-nanoseconds maximum) and worst case address decode time.
When this has been done and the address is decoded as valid, the slave device begins to generate read
data. In the case of a memory module, this means starting a read cycle. When read data is valid, the
slave device asserts TLTM- and at this time must have finished using TILINE signals TLADR- and
TLREAD. If a read error is detected during a read cycle, the READ ERROR (TLMER-) signal is
asserted by the slave. This signal must have the same timing as read data. This action occurs during
time one.
2.6.6 TILINE MASTER OPERATION OF DSIO CONTROLLER. The DSIO disk controller acts
as a TILINE master when transferring data from 990 main memory to disk, or from disk to 990
memory. The controller performs a single TILINE master cycle for each word transferred on the bus.
The master cycle consists of the actions necessary to acquire access to the bus, transfer the data word,
and release bus control. The TILINE master cycle is controlled by the TILINE master access logic
(logic drawing 937502, PWB, or 2262102, fine line) and by designated fields in the controller
microinstructions.
A TILINE master read or master write cycle does not represent a trap condition, unlike a slave read
or write, because the master cycles are initiated by the controller as the result of a need to transfer a
data word. The code segments that control TILINE master cycles are incorporated directly into the
major microcode routines, such as Read (RDD), Read Unformatted (RDU), Store Registers (SRG),
Write Data (WRD), Write Unformatted (WRU), and Write Format (WFT).
Each of the major command routines is initiated by a series of control words, WO-W7, from the 990
processor. These control words supply the command code and parameters for executing that.
2-37

Digital Systems Division

----

AT MASTER
TLGO(T)

~

TLTM(R)

<120
-NSEC

--

(2~V

(4)

~

! tL- - - - -

fe-/

*TLREAD
(T)
*TLADR(T)

~

~'-. ~---

I

VALID

TLDAT

r\

(R)

1/

VALID

TLMER-

---

(R)

-

::; 1 .51J.S

r-

\ .. ~--

TLGO(R)

~~

TLTM-

~

~

..

ERROR

--

AT SLAVE
NI
W
00

---

~ (T)

~120
NSEC

.'

~_If

~

~cv

~--

If

'---

TLREAD
(R)
TLADR(R)

\ VALID

**TLDATVALID

I

(T)
**TLMER-

,-

(T) \..

-. ~-I-- --ERROR

NOTES:

'I

NUMBERS IN PARENTHESES DENOTE TIME PERIODS REFERENCED IN TEXT.
(TILINE DELAY IS EXAGGERATED
FOR CLAR I TV)
(T) == TRANSM ITTED (R) '" RECE I VED
*'tLREAD AND TLADR- MUST BE STABLE AT THE TIME (OR BEFOf~E) TLGO-IS ASSERTED
**TLDAT- AN'D TLMER- MUST BE STABLE AT THE TIME (OR BEFORE) TLTM- IS ASSERTED

(A) 133123

Figure 2 17. TILINE Master to Slave Read Cycle Timing Diagram
a

~------~

946262-9701

command. These control ·words are stored in the 3002 ePE scratchpad registers by a series of
TILINE slave write operations. One of the parameters supplied in the control words is the starting
TILINE memory address of any data transfers from the controller to 990 memory or memory to
controller. The least significant 15 bits of the TI LINE address are stored in CPE register R6, and the
most significant 5 bits are stored in R5.
If the controller were commanded to perform a Read Data operation with a word count of 50, it
would have to read 50 words from the disk and achieve access to the TILINE 50 times, once for each
data word. The control words contain only the starting address of the 50-word buffer, so part of the
microprogram must be concerned with the "housekeeping" details of maintaining the correct
TILINE address as the buffer operation proceeds. Prior to the first TILINE master cycle, the CPEs
must load the four most significant bits of the TILINE address into an external (to the CPEs) MSB
address register. If the TILINE address crosses a 64K word boundary, the MSB address register
must be incremented. The MSB address register is controlled by four bits in special function group 0
of the microinstruction, as follows:
ROM

36

37

38

OPERATION

39

001

M S B Address Load

o

Increment MSB Address Register

0

2.6.6.1 Master Device TILINE Acquisition. Access to the TILINE is competitive between the
TILINE masters on the bus; there is no centralized bus control logic. Conflicts between competing
masters are settled by a positional priority system and a bus reservation scheme. The master device in
the highest-numbered chassis slot has the highest priority. Priority ranking decreases with each
chassis slot toward the 990 central processor, which has the lowest priority. The TLAG signal that
runs through each TILINE master, establishes the priority, as shown in figure 2-18.
TLAGIN (from a higher priority master) enters each master on P2, pin 6, and TLAGOUT leaves the
master on P2, pin 5. Logic on the master allows it to block the output to lower priority masters.
Jumpers on the 990 backplane are installed to insure line continuity across slots not occupied by
TILINE masters.
The master access logic of any TILINE master is based on a standard four-state access sequence.
These states are: Idle, Device Access Request, Device Acknowledge, and Device Access, as shown in
the master access flowchart, figure 2-19.
If the TILINE master does not have any data to transfer, the master access logic remains in the Idle
state, and TLAG is passed on to lower priority masters. Do not confuse the Idle state of the master
access logic with the idle mode of the DSIO controller. The idle mode of the controller refers to the
controller operating on the idle loop of the microprogram ready to accept control words. The Idle
state of the master access logic is the rest state of the access logic when it is not attempting to gain bus
access and transfer a data word.

When the master requires access to the bus, it goes into the Device Access Request state and blocks.
TLAG to the lower priority masters. While in the Device Access Request state, the controller'
monitors TLAGIN. If TLAGIN is high, the controller can monitor TLAK- after a 2oo-nanosecond
delay. A high TLAK- signal indicates that no other controller is in the Device Acknowledge state,
and allows this controller to go into the Device Acknowledge state. The Device Acknowledge state is
essentially a confirmed reservation for the next available bus access. The overlap of the current
operation with reservations for the next operation reduces bus dead time and increases throughput.
In the Device Acknowledge state, the master access logic pulls TILINE acknowledge low to prevent
any other controller going into the Device Acknowledge state. It continues to disable TLAGOUT,

2-39

Digital Systems Division

TILINE

..-

..

TLAV (TIL.INE
AVAIL.ASLE

....

TLAK- (TILINI;.
ACKNOWLEDGE)

..

~

*

NC

Ne
TLAG (TI LI NE
4ACCESS
GRANTED)
P2 -6

r--+ ••.• +-P2-5

P2-6

P2-5

TLAGIN

--

TLAGOUT

>
:>

P2-6

--Tr-1 )-

mESS

TLAGIN

TLAGOUT

-

.

>

T'" )-

mESS

--

~

0
vee

M~SlER
D VI E "0"

0
vee

TLAGIN

C)

MASTER
DEVICE ","

vce

TLAGOUT

TLAGOUT

-

}

" T ~_
.
~f8ESS

•••

NI

o

P2- 5

P2-5 P2-6

TLAGIN

MASTER
DEVICE "N"

~

.

--T~ }
-

C)

vec

~SS

MASTER
DEVICE "CPU"

I

ill HIGHEST PRIOR ITY

* NC MEANS

LOWEST PRIORITY

NO CONNECTION

o

cO'
;::;:

-

*

r+

Q)

(A) 138254

Figure 2-18. TILINE Master Devices Priority Interconnections

•

~------~

946262-9701

r--

I~---~--.~
MA:)IC.n: &..JJUI"""

I

DEVICEAcKNOWLEDGESTATE""

I

IDLE STA
..T_E_1_D_L_E--,r-lfo_ _ _ _--,
MDAK=1

I

MDGO=I
MDACT=I
TLAGOUT=O
TLAK-=O
MDAR=O

TLAGIN -TLAGOUT
MDGO = 0
MDACT = 0

MOM

="

MDAI< = 0
MDAC = 0
CLOCK (MPCK-) RUNNING

I

I
I

I
I

i

I

I
'-MDGO F/F

'-MDACT FIF
STOP MIC~
PROCESSOR CLOCK
START 20 MICROSECOND TIMER

~ICEACC~
REQUEST STATE

I

I

I
---1

I
I

o

STATE

I

I

TLAG IN= TLAGOUT
TLAK-='
GO=,

ACCESSOK-=O
ACCESSOK=l
TLGo-=O

I

I

I

I

I

I
L

MDGO='
MDACT='

o -MDAK

I
I

I

I

MDAC=l

I
I

I

I

--1

I~ICE7ccE;;

I
MDAR- .. O
-TLAGOUT

I

I -MDAC

! -MDAK

I
I
I

__ -.J

L

(8) 137629

O-MDGO
0 - MDAC
0 - MDACT
RESTART MICROPROCESSOR CLOCK
STOP 20 MICROSECOND TIMER

---

J

.

Figure 2-19. TILINE Master Access Flowchart

2-41

Digital Systems Division

~ ____9_46_2_6_2_-9_7_01___________________________________________________
and monitors TILINE available. When TLA V goes high, the access logic advances to the Device
Access state and initiates the read or write cycle. TLAGOUT is enabled so the next controller can
prepare for access. At the end of the read or write cycle, the access logic clears the Device Access
state, sending TILINE available to the other controllers, and returns to the Idle state.
2.6.6.2 Detailed Operation of TILINE Master Access Logic. Figure 2-20 shows the TILINE master
access logic, and the flowchart of figure 2-19 shows the simplified sequence of operations.
TILINE master access operations are initiated by the TILINE control field of the microinstruction,
bits 32 and 33, when the special field decoders are enabled by the K-bus control field, bits 10 and 11.
The TILINE control field bits are decoded as follows:
ROM

32

33

o

Operation
TILINE Master Read
TILINE Master Write

Refer to the input of the master device go F I F at the left edge of the figure and assume that the new
microinstruction specifies a TILINE master read or write. The resulting MSTSTB signal sets the
master device go (MDGO) F/F that immediately sets the master device active (MDACT) F/F.

The microprogram disables the microprocessor clock (MPCK-) via the clock stop master special
field combined with MDACT. Microprogram control of the clock allows the controller to suspend
operations until the TILINE master cycle is completed. Clearing MDACT restarts the clock and
allows program operations to continue.
The accessor signal active F/F initiates a 10-microsecond (approximate) TILINE timer. The
10-microsecond delay timer prevents a TILINE data transfer failure from hanging up TILINE and
DS10 controller operations indefinitely. The timer is reset if a TILINE wait has been asserted by a
TILINE bus coupler. The master device active F/F outputs also latch up the P-bus control register,
and prepare the FIFO or direct register to accept or supply the data word.
The set output of the master device go F / F (MDGO) combines with the high MDAC- signal to
disable the TILINE access granted output to lower priority TILINE masters.
If a higher priority master is holding TLAGIN low, there is a wait until that master lets TLAGIN
return high. The high TLAGIN signal and the inactive (high) MDAK- signal enable MDAREN-.
MDAR goes high, indicating that the access logic is in the device access request state. MDAR

initiates a 200-nanosecond (approximate) delay, which determines the minimum time to advance to
the next state.
If no other TILINE master is in the device acknowledge state, the low TILINE acknowledge (TLAK)
signal and the delay output, MDAROK- combine to set the device acknowledge F / F. This advances
the master access logic to the device acknowledge state.

The MDAK- signal disables MDAR, but MDAR- remains low, and continues to disable
TLAGOUT to lower priority masters. The MDAK output to the TLAK- line driver prevents any
other controller entering the device acknowledge state. At this time, the master access logic has an
acknowledged reservation for the next available access. If another controller is in the device access
state transferring data, there is a wait until the TILINE is available. When the TILINE becomes
available, the TLAV- and MDAK- signals set the device access F I F, and the logic advances to the
device access state.

2-42

Digital Systems Division

"'i:Y
~----------------------------946262-9701

i[ ~~~~~____~r-L-~=>~_G_O_IN_H--------,

TLAV
TILINE" L:NE

TILINE LINE
RECEiVERS

RECE1'v'ERS

{

~

FROM HIGHER-

PRIORITY T1UNE
MASTERS

,

TO LOWER PRiORITY

TLAGOUT

r-------------------~----------------------------_+------------------------------------------------_+---------------------------------------------.TILINEMASTERS

MOGO

"I" -

_

D::~~~

FROM MICRO-

[

INSmUCnON

TIUNE CONTROL

MSTRO-

'\.

MS1WRT-

V

MSTSTB

TER READ
MASTER WRITE

I

T
...,"

'------'-

[)

Q ...M_D_A_C_T_'IIMDAK-

__

J

MDAR

~ 200 nSEC

):D'-M;;;;D;;.;A.;.;;RE",N.;..--a
___
J

F/F

I

MDACT-

t-M=CC:;.M:;:P__

TLPRES -

F/F

• TO FIFO OUT/ZERO MUX (BELOW)

TLP

MCTM

..::-:.....-

""

L

~

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r-+----...;.;".---I CK

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rD-"':"::";:":';:;':""""cL.-I

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r
MICROINSTRUCTION{

II

ROM

"OMI3L-ISL

ROM20. 21

RONZOL. ZIL
PBUS

P/O DISK

r::-ACT _________

r.R"'OM::.''''3:.L_I-I~

I

DATA OR STATUS

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PBUSOOTILINE
DATA.

TiLINE DATA

PBUS1S-

CPU SEL MUX,

SL TM

ERROR LATCH

TLTM

ACCESS
MDACCK

F /F

::::~_

MDAKCLR-

CK

MASTER

DRIVER/

DRIVER!

'-----------------------:T="L-=G':"O---------,..

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_....:.T=L.:.:TM::.....____________________......~[

FROM GO GATE
(ABOVE)

jb
SH3

{

::~S~~

I

TILINE DATA
DRIVER ENABLE

.----4~

CPU IDENTIFICATION (990/9 VS 990110) MULTIPLEXER STEERING
MCTMEN

DRiVERS (eELOW)

)---

TILINE LINE

I

TO TILINE DA.TA LINE

TM'---:t-C-rl--.:.A~C=C~DA:..TE:!:N~JL..)

--'

--

T

ACCESSCIK-

LATCHES

I

CPUIC

CONT~OL

-------------1..'- - -:::~ _T_L_'OR__ES______~I- _ _ _ I-:;.,;;~::.;W?R.::.;A.;;.,:S-~......

TLPRE:S-

--I
MDCMP-

TILINE

~E.£E!:!E!!S

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TLTM-

..§...I-T:..::LA:::..:.V--...........

G

I

~

CPU 1O

r-

---=.=-----"'"

MCTMEN
MASTER DEVICE

(LSB)

TERMINATE'

p/o

TIUNE

CPU ID

MUX

------II

"I"

(990 '0)

.....

ROM33L

I
I
I

TILINE ERROR LATCH
1

=

MASTER WRIT!:

TLERR-

(OR SLAVE TERM)
FROMGOGATE

- -- ---,

-r-~-~/O
lMOCMP- "1

~

I

}~~;~..II

TLMER-

r
~. ~
----,GO~

CHASSIS

~::~EL GROUP 0

p/O

~

1

..RO
.....
M..;.36;..:,....3_7,;",._3B;..:,....3_"-r-_ _ _ _ _ _ _ _ _ _ _ _ _...

INTRST-

PFWP-

"'i..r

__
M_S_BA_C_R_'N_C_-______

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-v ROM33Lr

ROM33L

TLPFWP-

FROM
900

MICROINSTRUCTION {

~

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~~~

SH18

ROM33L~ =-::~

~D-.T.;:;LS;;;;;H",OU=..;Ta-_

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~:~,:~~.U:EGISTER

DISK I/F....
LOGIC
"TLSHIN-

I I
I

LINE
RECEIVERS

~

~

II

I

0 DEVICE

RECEIVERS

-,

FIFOOUTOO

-

....

MDAC
1r--______________~;;;.LA;;.;DA.;.;;~'--------~{lE~~~
t---+--.....--....:;.:="----~------+_-----'

+-+M~DT.:...;~O'-------f--"TlMEaJT LATCH

~I
__ _

"0"

L (-r:p":" F~D~ HI~ ..J

{

BUS SOURCE =DISK

~

j-:R~O:::M:.:3:::3L,,--_ _ _;;.....,
PBUSENL

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Q

ID

MUX

I

p7::,C:=S::CT:=OE::N:-l

ROM13-IS

MCTORC

5H2

(NOT A TRUE LATCH)

I

I PBUSEN
~~:i:.r~~
~IM:.:C~AC~T~-____~CK

NASTER DEVICE ACTIVE
F/F (ABOVE)

'~'SEC

MCCMP-

• ROM..

___________

MCACRST

~

I

~

I

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TLE .... L-

o

0

o

I

,I""S8
1

\0

SLAVE ADDRESS

ADDRESS LOAD
INCREMENT MSB ADDRESS REG

TO INTERRUPT

TLAEIORT-

L..OGIC (SEE MICROPROGRAM

TILINE ABORT LATCH

,n~ - ~I-IO-R-E-S---- .;J-_-'-'-IN...;T""A"'D""Z'--___-.J

INTERRUPi

.=rl
-rJ--"-

,..--~.-

'~~)_--T;,.R~A..;,P;,.-----_I~~

,

/

TO BRANCH DECODER ROM

TRAP

IN MICROPROGRAM
ADDRESS GENERATOR

SLAVE
TRAP

MICROINSTRUCTION - - - - - ; . , . R . . ; , o ; , . M ; . : . I . : . 6 - - - - - - - - - - - - - - - - I - , " " " " " ' \ " n -_ _ _ _=Lv.!;A=D-_-i
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s

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ENABLE SLAVE BIT

I

fROM 16

I

0
I

SLAVE A

I

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ENABLE SLAVE

F/F

f

GND
SLVACT

SLVACT

~

l.INTADI

<

NRAOI

•
•
•
•

liNTAD2
r--+--;CK

TLADROo- (MSB)

•

~rr"
I ~~

INTADO

F/F
SLVA

MPCK- - - - " ' - - - ; C K

TILINE
ADDRESS

O~~S~L~V~e-~----4~~~~~~

SLAVE B

MPCK-

{

TLADRI7-

TLADRI7

TLADRIB-

TLADRI8

R~

-----'---------~~~~-----+--------------------r_--------_1
D

TOL'.' {

TO 990 PROCESSOR

L _____ ..J
I

TI..READ

TILINE TERMINATE

I

r---------------,
37

TO MICROPROCESSOR
CLOCK GATING (ZERO
HALTS MPCK-)

SEE BOX

SPECIAL GROUP I DECODER/REGISTER
ROM 36

NRA09

TLTM----..
L - - - ...J
~ r-t-S_L_T_M-tf"..Jt>
~_~-----;S~L~T~M~B~-~------------------------------~---------~-~
____
L-~~'
BASIC
r __ - -- - __ --,

SLXFR-

SELSWI5-

0 I

ADDRESS GENERATOR

,
1Wr>--.1~~------------------+-----------S~L~T~M~A..;,----__--~.
_S;.;;L_V'"'T'_'R""M;.;.-____J'IIQ_~J

FROM MICROINSTRUCTION DECODE

12

3

'0-

CK

~

SLVA-

TRANSFER

SLAVE

10

2

- ""
,.. ...,

~

.....

01-SLAVE

TILINE
i

•
•
_ _R_OM_3_1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~R~O;.;.M~3'_'1___-+_~

9

GND

ROM23

{

INSTRUCTION

••

SLAVE ADDRESS
SELECTION SWITCHES

SLXFR

r-----

TO MICROPROGRAM

13

14

15
1

TLDATAOITILINE
DATA
LINE
DRIVERS

•
•

TLDATAI5-

I TILINE DATA TO PBUS

Figure 2-21. TILINE Slave Logic

2-49/2-50

Digital Systems Division

"ij/
~------946262-9701

\'-___

V

ADDRESS SETTING RANGE
TILINE: FFCOO -

FFC78 IN 8-WORD INCREMENTS

I

"

-----1
v
--

NOTE THAT SWITCH
SEC TI ON S DO NOT
FOLLOW BINARY ORDER

F800 - F8FO IN 16-BYTE I NCRE::::S LSB' S SELECT i OF 7 REGISTERS

CPU:

(RO-R7) I NTERNAL TO THE CPE-DEVICES,
VIA A TILINE SLAVE TRAP ROUTINE.

---.J

(A) 137639

Figure 2-22. TILINE Slave Address Comparison

ROM 16, the enable slave clock bit, serves as a lockout to prevent a slave trap operation when the
disk controller is not in the idle mode. The slave A F/F resets on the trailing edge of the first
microprocessor clock pulse, forcing the interrupt priority encoder outputs, INTA- and INTADO-2,
to all ones and enabling TRAP-. Slave B resets on the next clock pulse to limit TRAP- to a single
clock period.
The TRAP signal to the branch decoder ROM causes the microcode address generator to store the
current address in the return stack and jump to the trap address selected by the next ROM address
(NRA) mUltiplexer.
The TRAP- signal steers the NRA multiplexer to select the trap address as follows:
Address
OFO

Operation
Slave Read

CPE Scratchpad

Register 0

OFt

I

OF2

2

OF3

3

OF4

4

OF5

5

OF6

6

OF7

Slave Read

CPE Scratchpad

Register 7

OF8

Slave Write

ePE Scratchpad

Register 0

OF9

I

OFA

2

OFB
OFC

4

OFD

5

OFE

6

OFF

ePE Scratchpad

Slave Write

Register 7

The three least significant bits of the TILINE address in combination with the READ- and
signals select the appropriate trap address.

2-51

S:_ VACT

Digital Systems Division

~------~

946262-9701

The slave read trap routine typically consists of two microinstructions. The first microinstruction
transfers the selected CPE register contents into the CPE accumulator (AC) register in preparation
for the transfer. The second microinstruction loads the AC contents onto the processor bus
(PBUSOO- through PBUS15-), and commands the TILINE slave operation terminate (ROM32, 33 ==
01). This microinstruction also contains the return which directs the microprogram back to the idle
loop. Both microinstructions hold the enable slave bit set.
The TLDATEN- signal enables the TI LINE data line drivers when the slave A F I F is set, but the
PBUS data is not meaningful at that time. The TILINE slave operation terminate in the last
microinstruction is decoded to produce the SLVTRM- signal.

The SL VTRM- and SL VA- signals combine to produce the active low slave terminate access signal,
SL TMA-. The slave terminate access signal stops the microprocessor clock and enables slave
terminate (SL TM) to the TL TM- line driver. If ECN 428311 is installed, CLKT3- delays TL TMapproximately 115 nanoseconds after SL TMA-. TL TM- serves as a strobe to notify the TILINE
master that valid slave data is currently available on the TILINE data lines. The master accepts the
data and ends the TILINE cycle by releasing the TLGO- command.
When TLGO drops low, it clears the slave transfer F I F and presets the slave A F / F. The slave A
outputs disable the TILINE data line drivers and the TILINE terminate signal. and restart the
microprocessor clock.
The last microinstruction of the slave read operation continues active on the ROM 00 - 39 lines until
the first clock pulse (M PCK-) from the restarted clock loads the return address from the stack in the
microprogram address generators. This same M PCK- pulse clocks the slave B F I F, returning the
slave logic to the original state and enabling the interrupt priority encoder. The one-state delay
imposed by slave B assures that the microprogram executes at least one instruction in the idle loop
before jumping to any pending interrupt trap routine.
2.6.7.2 TILINE Slave Read with Controller Not Idle. Before issuing a set of command words to the
disk controller, the 990 computer must check the idle / not idle status of the controller by reading and
testing W7. bit O. If W7, bit 0 is a one. the controller is not busy with some operation, and the
controller microprogram is cycling in the idle loop ready to accept commands. If W7. bit 0 is a zero,
the controller is busy (not idle). and cannot execute a slave trap operation.
The busy F / F and logic allow the disk controller to respond wtih a simulated W7 word if the
controller is busy. This simulated W7 word has a 0 at bit 0 to identify not idle status. and bits 1-15 are
meaningless. No slave read trap operations are performed, and the on-going controller operation is
not disrupted.
Assume that the controller has been commanded to perform some operation, so that the
microprogram branches from the idle loop to the initialize routine. The first microinstruction of this
routine (lNIOO. location 02E) disables the slave traps (ROM 16 == 0) and sets the busy F/ F. Special
field one of the microinstruction controls the busy F / F as follows:
Group Select
ROM

34

o
o

Special Field 1
35

ROM

36

37

38

39

100

o

2-52

Set Busy F IF
Reset Busy F I F

Digital Systems Division

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946262-9701

The busy F F is one stage of the SN74LS259 8-bit auuressabie iaich ihai comprises the speciai group
1 decoder register. The busy F/ F remains set (busy- = 0) until the last instruction of the terminate
routine (TRM25. location ODF) is executed. This instruction also includes a branch to the Idle
routine.
Assume that the 990 computer attempts to check the idle/not idle status with a TILINE read
operation addressed to ePE scratch pad register 7. The TLREAD- output of the TI LINE line
receiver is 0 to identify a read operation. and the slave address compaTes (SLADOK = I) to the
board address. At the expiration of the slave go delay, the slave transfer F / F sets and the slave write
F / F resets.

The enable slave bit (ROM 16) is zero, so the slave A and slave B FIFs are not allowed to enter a trap
cycle. TLDATEN is held low, disabling the line drivers for TLDATA01- through TLDATAI5-, and
disabling one of the two TLDATAOO-line drivers. The outputs of the slave transfer and busy flipflops combine to enable the active low slave terminate-busy (SL TM B-) gate. S LTM B- enables an
immediate TILINE terminate signal to the 990 computer. The SL TM B- signal combined with the
READ-signal enables the hardwired TLDA T AOO- driver. The line driver output of the driver
corresponds to a 0 in the bit 0 position of the simulated W7 word. indicating that the controller is
busy. The bit 0 line driver remains active until the 990 computer signals the end of the TI LINE cycle
by releasing the TLGO. The low TLGO signal clears the slave transfer F / F. disabling the TILINE
terminate and data bit 0 line drivers.
Microprocessor clock is not stopped and microprogram execution is not affected by this cycle.
The three LSBs of the TILINE address are not decoded. This means that a read operation addressed
to any of the eight slave registers will be treated as though it were addressed to R 7, if the controller is
busy. It is the responsibility of the device service routine programmer to assume that idle status is
checked before attempting to read RO-R 7.
If the 990 computer attempts a write operation to the disk controller while it is busy. the SL TM Bgate issues an immediate terminate signal and the controller does not accept the word. Again. it is the
responsibility of the device service routine programmer to check idle status before attempting to
transmit control words to the disk controller. The device service routines supplied wtih OX 10 and
other OS I 0 disk-compatible operating systems perform this check in a manner transparent to the
user program.
2.6.7.3 Slave Write. The OS I 0 disk control words are loaded into the CPE registers during a
sequence of eight slave write operations. Operation of the TILINE slave logic is similar to slave read
operations except for the state of the slave write F/ F and the direction of TILINE data flow.
Assume that the DS 10 disk controller is in the idle mode and the 990 computer sends a control word
WI over the TILINE. The slave address comparator compares the 17 most significant TI LINE
addresses against the board address. The IOO-nanosecond slave go delay assures that the address and
TILINE data word are stable before clocking the slave transfer and slave write flip-flops. The enable
slave bit (ROM 16) is set, enabling the slave A flip-flop to initiate the slave trap operation.
The trap address is determined by the three least significant bits of the TI LIN E address, the READsignal (READ = l) and the slave active (SL VACT = l) signal. Trap address assignments are
included with the slave read description.
A slave write trap routine contains a minimum of two microinstructions. The slave write traps for RO
and R6 are longer because they perform additional functions. but the operation of the TI LINE sla ve
logic remains the same. The bus source field (ROM 13-15) of the first microinstruction gates the

2-53

Digital Systems Division

~------~

946262-9701

incoming TI LINE data word onto the processor bus. The PBTLDAT- signal from the PBUS source
decoder enables the line receiver outputs onto the bus. The CPE function code (ROM 01 - 07)
commands the CPE array to read the PBUS contents into the accumulator. The enable slave bit
(ROM 16) remains set for both microinstructions.
The second microinstruction transfers the data word from the accumulator to the specified
scratchpad register. RO - R7. The TILINE operation field (ROM 32.33) commands TILINE slave
operation terminate (SLVTRM-).
The SL VTR M- signal combines with the output of the slave A F / F to disable the microprocessor
clock (SL TMA-) and issue a TL TM- signal. If ECN 428311 is installed. TL TM- is delayed
approximately 115 nanoseconds by CLK T3-. The microprocessor clock remains in the holding state
until the 990 computer releases the TLGO. ending the TI LINE cycle. The low TLGO signal clears the
slave transfer F / F and presets the slave A F / F. so microprocessor clock is restarted.
The next microprocessor clock pulse returns microprogram execution to the point in the idle loop
where the slave trap occurred. It also clocks the slave B F / F. which returns the slave logic to the
initial state and enables the interrupt logic.

2.7 3002 CENTRAL PROCESSING ELEMENTS (CPEs)
The disk controller uses an array of eight 3002 bit-slice central processing elements controlled by a
permanent on-board microprogram to execute the disk control commands. The CPE array is
organized as 8-bit left and right bytes. Each 3002 device is a 2-bit slice of a general-purpose
processor. The principle features of a 3002 CPE are:
•

Eleven scratchpad registers (RO-R9 and T)

•

A full-function accumulator register (AC)

•

Independent memory address output register (MAR)

•

Two 3-state. fully buffered output buses (A. D)

•

Three independent input buses (M,

•

Full look-ahead and ripple carry

•

Two's complement arithmetic

•

Logical AND, OR. NOT, exclusive-NOR

•

Left shift or right shift

•

Bit testing and zero detection

•

Single clock input, which may be conditional for nondestructive bit and word testing.

L K)

2.7.1 3002 CPE BLOCK DIAGRAM. Refer to figure 2-23 which is a functional block diagram of a
single 3002 device. Note that the three input data buses (M, I, K) and the two output data buses (A,
D) use an active-low signal level to represent a data one. That is, a data one is represented by a
voltage level less than 0.8 volts, and a data zero is represented by a voltage greater than 2.8 volts.
The bubbles on the device outline identify the active low input and output lines. Table 2-4 lists the
CPE input and output signals.

2-54

Digital Systems Division

~------~

946262-9701

MAIN MEMORY
ADDRESS

DATA OUT

(A)

(D)

____

A~;.~

r--

__ __ _

D..!..si~

I

_E_A
__

(CPE)
A-BUS

D-BUS

~l~________________~~1 A:~SUT:pTUET
I

1

ADDRESS

I

DRIVERS

I
I

OUTPUTS

I
CLK

~I

~

....--.,.--I ...

MEMORY ADDRESS REGISTER (MAR)

SELECT

t

1

CODE

{

OUTPUTS

CLK

(ALU)

:~'I:~>~F

B

~

-=--"I'I---"hll
F2
Fl

R

:::::;i::::::ir
I

RIGHT
SHIFT
OUTPUT

t

I~

MICRO-

FUNCTION
DECODER

I
I-------------...---I--~r
RO

RO
A

F5
':::":"-......
F4

LCI

CI ~------------~---4~--~r----CARRY IN

UNIT

ALU FUNCTION SELECT

FO

CLOCK

ENABLE

I

ARITHMETIC /LOGIC

I
I

JACCUMULATOR

I

~--~~~----~--------------------~co

F3

ED

~--------------~---DATA

I

~_~I---+--------------~x
+-______

CPE
FUNCTION

I
I

FAC) REGISTER

X
LOOK-AHEAD {
Y
~__~L+-____
~~==~~==~y
CARRY OUT!'>UTS
RIPPLE CARRY OUT CO
LI
LEFT IN (FOR ____~------~------------------~LI

F6

3-STATE
D-OUTPUT
DRIVERS

REGISTER

I
I
I
RIGHT SHIFT)

I

CESSING ELEMENT

I
I

ENABLE

_ _ _ _ _.,
3002 CENTRAL PRO-

1------------------1-------.,
l~~
t!~X
........ ~~ ~l!
..
~

~
~

MUX CONTROL

M
.....

A.C. . . . . .

....
A.C. . . . . . . . . . . . . .. .

CLKJ .... CLK
,...;..;;;;.;.CII_L....

I
I

SCRATCH-

REGISTER

~______.-S_E_L_E_C_T__~·~~EG7:~ERS

I

RO-R9.T
CLK~

I
I

t

ALU

I

I

L

-

Ml-C~

-

-

-

-

-

-11'~';-

7,' s;;;. -

MEMORY
DATA (M)

EXTERNAL

MASK

INPUT (I)

(K)

BUS IN

BUS IN

BUS IN

- - - NOTE.

T

+I

=ACTIVE
LOW INPUT
OR OUTPUT
SIGNAL

(B)135704

Figure 2-23. 3002 CPE Block Diagram

2-55

Digital Systems Division

~_
946262·9701
J17~
_ _ _ _ __

The three input data buses (M, L K) are shown at the bottom of the figure. The M-bus is the main
data input of the CPE as used in the disk controller. The M-bus inputs are connected to the
processor bus (PBUS), which is the main data path through the controller. The I-bus is used for

reading flags into the CPE array. The K-bus is also known as the mask bus, because the K-bus inputs are ANDed, bit-for-bit, with the ALU B-input operand. For some instructions, the
B-multiplexer output is set to all ones, so the K-bus data can be used as an immediate operand.
There are II general purpose scratch pad registers (RO-R 9. T) in the CPE. Each of these registers may
be individually loaded with data from the AL U output and the contents of any of these registers may
be selected as an ALU input operand. Scratchpad registers ROthrough R7 are used as TILINE slav'e
registers. They are used to store control words WO - W7, respectively, from the 990 processor.

Two multiplexers select the operand inputs to the arithmetic/logic unit (ALU). The inputs to
multiplexer A are accumulator register (AC), the selected scratchpad register, and the M-bus inputs.
The inputs to multiplexer B are the accumulator register or the I-bus inputs. The outputs of
multiplexer B are ANDed bit-for-bit with the K-bus inputs, allowing the K-bus contents to be used
to mask the I-bus inputs or the accumulator contents. Multiplexer B outputs can be selected to all
ones, gating the K-bus inputs into the ALU.
Table 2-4. 3002 CPE Input and Output Functions
CPE
Pins
1,2

CPE

Bus

X,Y

Type
Signals

Name and Description

10 - 11

3,4

5,6

Controller
Signal

External bus input. The external bus input provides a separate input port for external
input devices.

Active low

CPK(OO - 15)-

Mask bus input. The mask bus
input provides a separate input
port for the microprogram
memory, to allow mask or
constant entry.

Active low

CPX(0-7),
CPY(0-7)

Standard carry look-ahead
cascade outputs.

Active high

Ripple carry output. The
ripple carry output is only
disabled during shift right
operations. Not used.

Active low
Three-state

7

co

8

RO

CPSHIFT(N)-

Shift right output. The
shift right output is only
enabled during shift right
operations.

Active low
Three-state

9

LI

CPSHIFT(N)-

Shift right input.

Active low

10

CI

CARRY(0-6)-

Carry input.

Active low

2-56

Digital Systems Division

~
CPE
Pins

946262-9701
Table 2-4. 3002 CPE Input and Output Functions (Continued)

CPE

Type
Signal

Bus

Controller
Signal

11

EA

ACCESSOK-

Memory address enable input.
When in the low state, the
memory address enable input
enables the memory address outputs, TLADR(04-19)-.

Active low

12,13

Ao - Al

TLADR(04-19)-

Memory address bus output.
The memory address bus output is the buffered output
of the memory address
register (MAR).

Active low
Three-state

14

GND

15-17

F6 - Fo

ROM(01-07)

Microfunction bus input.
The micro function bus input-c
controls ALU function and
register selection.

18

CLK

CPRCK - or CPLCK-

Clock input.

19,20

Do -DI

PBUS(OO-IS)-

Data bus output. The data
bus output is the buffered
output of the full function
accumulator register.

Active low
Three-state

21,22

Mo - Ml

PBUS(OO-IS)-

Data bus input. The data
bus input provides a separate input port for data.

Active low

23

ED

PBCPE-

Data enable input. When
low, the data enable input
enables the data output,
PBUS(OO-IS)- .

Active low

Name and Description

Ground.
Active high

The arithmetk/logic unit (ALU) performs a variety of arithmetic and logic operations on the input
operands, including two's complement addition, incrementing, shifting, logical AND, logical OR,
exclusive-NOR and logical complements. The ALU has provisions for a carry input (CO from a less
significant stage, and both ripple (CO) and look-ahead (X, Y) carry outputs to more significant
stages. The ALU has a right-shift output (RO) and a left-bit input (LI) for right shift operations.
The ALU has two sets of output lines, one to the MAR, and one to the AC and the scratchpad
registers. The accumulator contents may be used as operand inputs for the next operation, or gated
out of the CPE via the three-state D-bus output drivers. The output drivers are gated by the enable
data (ED) input. In the disk controller, all the CPEs are simultaneously enabled by the PBCPEsignal on the ED inputs.
The MAR outputs may be gated out of the CPE by the three-state A-bus output drivers. The drivers
are enabled by the enable address (EA) input. In the disk controller. the TILINE access OK

2-57

Digital Systems Division

~ ____9_46_2_6_2-_9_70_1__________________________________________________
(ACCESSOK-) signal enables the A-bus outputs, which supply 16 bits of the TILINE address for
master operations.

The micro function decoder provides the register selection, ALU input multiplexer steering, and
ALU function control signals based on a seven-bit CPE function code, inputs F6-FO. The CPE
function code is supplied by seven bits (ROM 01 - 07) of the 4O-bit microinstruction ROM. Note that
the numbering of the ROM bus function code runs counter to the F6-FO numbering on the device.
The clock input is used to load the results of an ALU operation into the selected registers. Clocking
occurs on the negative-going transition of the external clock. The CPEs in the left byte are clocked
by the CPE left byte clock (CPLCK-) and the right byte CPEs are clocked by CPE right byte clock
(CPRCK-). The CPRCK- and CPLCK- signals are in phase with microprocessor clock (MPCK-),
but are gated by the word select field and clock stop bit of the 40-bit microinstruction.
The ALU function control, register output selection and multiplexer steering are not clocked. It is
possible to command operations and test the results via the nonclocked carry or right shift output
without altering the contents of any CPE registers. The clock pulse which would store the results of
the operation is omitted under microprogram control. During nonarithmetic operations, the carry
circuits perform a wordwise inclusive-O R of the AL U output bits. This can be used to test the results
of an ALU operation or register contents for a nonzero value. If masking is also specified, individual
bits or bit groupings may be tested. Bit testing is described in detail with the CPE carry and shift
logic.
Figure 2-24 summarizes the CPE internal operating sequence in flowchart form.

2.7.2 CPE INSTRUCTION SET INTRODUCTION. During each microinstruction, a CPE
function code on the ROM bus, ROM (01-07), is applied to the function code (F-bus) inputs of the
3002 CPEs. These inputs on the F-bus are decoded within the 3002 CPEs by the microfunction
decoder. Within the CPEs, the operands are selected by the A and B multiplexers, the appropriate
scratchpad registers are addressed, and the specified operation is performed by the ALU. The result
of the ALU operation may be loaded into the AC, the MAR, or one of the scratchpad registers.
The conditional branching and return microinstructions use the results of ePE internal bit or
register tests to control the branch, as described with the CPE carry and shift logic. The clock input
to the CPE may be omitted (under control of ROM 00) during these conditional operations. This
allows the unclocked carry and shift outputs to be used for testing without altering the CPE register
contents.
CPE operations for each of the microinstructions are documented in the flowchart descriptions of
the microprogram, Appendix C, and microinstruction listing, Appendix D.

2.7.3 FUNCTION CODE FORMATS. The most significant three bits of the function code, ROM
(01-03), specify one of seven F-groups, as shown in table 2-5. Each F-group determines a type of
operation. The other four bits, ROM (04-07), are used for register selection as shown in table 2-6.
The registers are divided into three groups, R-group I, R-group II, and R-group III. The register
group number modifies the function specified by the F-group. R-group I contains scratchpad
registers RO-R9, T, and AC (designated Rn for convenience). R-groups II and III contain only the T
and AC registers. Reference to the table shows that there are three individual codes which select the
T register: C 16 (R-group I), A 16 (R-group II), or E16 (R-group III). The AC register may also be
selected by any of three codes: 0 16 (R-group I), B16 (R-group II), or F16 (R-group III). The CPE
function descriptions in the next paragraph are keyed to this F-group and R-group scheme.

2-58

Digital Systems Division

~--~---~

946262-9701

ACCEPT NEW CPE FUNCTION CODE
ON POSITIVE LEVEL OF
MICROPROCES~OCK.

!
DECODE CPE FUNCTION CODE

SELECT ALU INPUT OPERANDS
VIA MULTIPLEXERS A AND B

!
PERFORM ALU OPERATION. CARRY
AND RIGHT SHIFT OUTPUTS ARE
VALID. IF NEGATIVE CLOCK
TRANSITION IS OM ITTED, CARRY
OR RIGHT SHIFT OUTPUTS MAY BE
USED FOR NON-DESTRUCTIVE
TESTING

ON NEGATIVE CLOCK TRANSITION,
STORE ALU RESULT IN MAR,
AC OR SCRATCH PAD REGISTER.

DATA OUTPUTS ON A ,0 BUSES
ARE VALID.
WAIT FOR CLOCK TO RETURN TO
HIGH LEVEL FOR NEXT
INSTRUCTION

(A)135705

Figure 2-24. CPE Internal Operating Sequence

2-59

Digital Systems Division

~

946262-9701
Table 2-5. Function Group (F-group) Format
F-Group

ROM 01
(F6)

ROM 02
(F5)

ROM 03
(F4)

0

0

0

0

I

0

0

I

2

0

3

0

0

I

I

4

0

0

5

0

I

6

0

7

Table 2-6. Register Group (R-group) Format
R-Group

Registers

ROM 04
(F3)

ROM 05
(F2)

ROM 06
(Fl)

Ro
RJ
R1

0

0

0

0

0

0

0

0

I

I

0

0

0

2

R3

0

0

I

3

R..\
R,
R6
R7
Rs
R9

0

0

0

4

0

0

I

5

0

6

Rn

0
0

III

Hexadecimal
Code

1

I

I

7

0

0

0

8

0

0

I

9

0

0

C

0

I

0

T
II

ROM 07
(FO)

AC

I

T

0

0

A

AC

0

1

B

0

E

T
AC

F

2-60

Digital Systems Division

~_
946262-9701
J}7~
_ _ _ _ _ __
'l '7 Ii

... ,.""

rDV

'-'.a.&...oll

'-'.1""" .... "'.l,,IIJI.

];TT~rTTnl\'J~
•

Tn}.,.1". "') i
~"UJ.,", L"",-,

;" n ""...",...",n ..."
I,:)

U

':'Ull1111UI'y

,-,.t i-l-.".
1{\{\"') rDt:' t" .... ,...i-;,..,. .... " Tl-.L"'> ""...",...",,, ...,, :" : ...
1.'1'-' _'VV~ '-.l.L.... lUll\"..1,.1Vll .."l.
I l l ..... ':'Ullll11UI)
l~
III

VI

generalized form, with no assumptions about the data on the mask bus. If the K-bus contents are 00
or II, the general Boolean expressions are considerably simplified. Each F-groupj R-group
combination is briefly described below.
In step I of table 2-7 (F-group 0, R-group I), the contents of the Ae are logically ANDed with the
data on the K-bus. The result of this ANDing is added to the contents of Rn and also to the value of
the carry input (el). The sum is placed in Rn and AC.
In step 2 (F-group 0, R-group II), the contents of AC are logically AN Ded \vith the data on the
K-bus. The result is added to the data on the M-bus and also added to el (carry input). The sum is
deposited in AC or T, as specified.
Step 3 (F-group 0, R-group III), if the K-bus contents are zero, shift Ae or T-register one bit to the
right. The lower-order bit is shifted out on Ro, and the higher order bit is filled from LI. If the K-bus
contents are nonzero, the shift is a function of both the I-bus and K-bus contents.
In step 4 (F-group 1, R-group I), the data on the K-bus is logically 0 Red with the contents of Rn. The
result is placed in the MAR. Also, the contents of Rn is added to the data on the K-bus and to carry
in (CI). The result is deposited in Rn.
In step 5 (F-group 1, R-group II), the data on the K-bus is ORed with the data on the M-bus. The
result is deposited in the MAR. Also, the data on the M-bus is added to the data on the K-bus and to
Cl. The sum is deposited in AC or T, as specified.
In step 6 (F-group I, R-group III), the complement of the contents of AC or T, as specified, is 0 Red
with the data on the K-bus. The result is added to the logical AND of the specified AC or T-register
and the data on the K-bus. The sum is added to eI and the result is deposited in Ae or T, as
specified.
In step 7 (F-group 2, R-group I), the contents of AC are ANDed with the data on the K-bus. The
value of 1 is subtracted from the result and the difference is added to Cl. The sum is deposited in Rn.
In step 8 (F-group 2, R-group II), the data on the K-bus is ANDed with the contents of Ae. The
value of one is subtracted from the result and the difference is added to Cl. The sum is deposited in
AC or T, as specified.
In step 9 (F-group 2, R-group III), the data on the I-bus is ANDed with the data on the K-bus. One is
subtracted from the result and the difference is added to Cl. The sum is deposited in AC or T, as
specified.
In step 10 (F-group 3, R-group I), the contents of AC are ANDed with the data on the K-bus. The
result is added to the contents of Rn and to el. The sum is deposited in Rn.
In step 11 (F-group 3, R-group II), the contents of AC are ANDed with the data on the K-bus. The
result is added to the data on the M-bus and to CI. The sum is deposited in AC or T, as specified.
In step 12 (F-group 3, R-group III), the data on the I-bus is logically ANDed with the data on the Kbus. Add the result to AC or T as specified, and to CI. Deposit the sum in AC or T, as specified.
In step 13 (F-group 4, R-group I), logically AND the data on the K-bus with the contents of AC.
Logically AND the result with the contents of Rn. Logically OR the value of CI with the word-wise
OR of the bits of the final result. Place the value of the carry OR on the carry output (CO) line.

2-61

Digital Systems Division

4P

946262-9701
Table 2-7. Summary of CPE Microfunctions
Step

F-Group

Microfunctions

R-Group

Rn + (AC" K) + CI ~ Rn. AC

1
II

M + (AC" K) + CI ~ AT

III

LI V [(IH "KH)" ATH] ~ ATH
ATL" (IL" Kd ~RO
[ATL" (IL" Kd] V [ATH V (IH" KH)] ~ ATL

4

KvR n ~MAR

Rn + K + CI ~ Rn

5

II

KVM~MAR

M+K+CI~AT

6

III

(AT v K) + (AT" K) + CI ~ AT

2

0

3

(AC" K) ·1 + CI ~ Rn

7

8

2

9
10
11

3

12

II

(AC" K)·1 + CI ~ AT

III

(I" K)·1 + CI ~ AT

14

Rn

II

M + (AC" K) + CI ~ AT

III

AT + (I " K) + CI ~ AT
Cl v(Rn/\ AC"

4

15

5

18

K)~CO

Rn I\. (AC /\ K) ~ Rn
K)~

II

CI v (M " AC" K) ~ CO

M" (ACA

III

CI V (AT AI" K) ~ CO

AT" (I " K) ~ AT

II

CI V(Rn " K) ~ CO
CI v (M A K) ~ CO

K"M~AT

III

CIV(AT"

16
17

+(AC"K)+CI~Rn

I

13

1

(See NoteQ)}

K)~CO

K" Rn

~

AT

Rn

KI\.AT~AT

19

CI v (AC A K) ~ CO

Rn v (AC A K) ~ Rn

20

II

CI v (AC" K) ~ CO

Mv (AC" K)~ AT

III

CI v (I " K) ~ CO

ATV(I"K)

6

21

CI v (Rn A AC" K) ~ CO

Rn.e(ACA K)~ Rn

II

CI v (M A AC " K) ~ CO

M e (AC " K) ~ AT

III

ClV(ATAIAK)~CO

AT e (I " K) ~ AT

22

23
24

7

~AT

NOTE:CD2's complement arithmetic adds 111 ... 11 to perform subtraction of 000 ... 01.
LEGEND:
Symbol
I,K,M
CI, LI
CO,RO
Rn
AC
AT
MAR
+
A

V

a;

H
L

Meaning
Data on the I, K, and M buses, respectively
Data on the carry input and left input. respectively
Data on the carry output and right output. respectively
Contents of register n including T and AC (R-Group 1)
Contents of the accumulator
Contents of AC or T, as specified
Contents of the memory address register
2's complement addition
2's complement subtraction
Logical AND
Logical OR
Exclusive·NOR
Deposit into
As a subscript, refers to the higher order bit of the 2 bits in a CPE device
As a subscript, refers to the lower order bit of the 2 bits in a CPE device

2-62

Digital Systems Division

~------~

946262-9701

In step 14 (F-group 4, R-group II), !ogicaHy AND the data on the K-bus with the contents of AC.
Logically AND the result with the data on the M-bus. Deposit the final result in AC or T, as
specified. Logically OR the value ofCI with the word-wise OR of the bits of the final result. Place the
value of the carry 0 R on the CO line.
In step 15 (F-group 4, R-group III), logically AND the data on the I-bus and the data on the K-bus.
Logically AND the result with the contents of AC or T, as specified. Deposit the final result in the
specified register, AC or T. Logically OR CI with the word-wise OR of the bits of the final result.
Place the value of the carry 0 R on the CO line.
In step 16 (F-group 5, R-group I), logically AND the data on the K-bus with the contents of Rn.
Deposit the result in Rn. Logically OR CI with the word-wise OR of the result. Place the value of the
carry 0 R on the CO line.
In step 17 (F-group 5, R-group II), logically AND the data on the K-bus with the data on the M-bus.
Deposit the result in AC or T, as specified. Logically OR CI with the word-wise OR of the result.
Place the value of the carry 0 R on the CO line.
In step 18 (F-group 5, R-group III), logically AND the data on the K-bus with the contents of AC or
T, as specified. Deposit the result in the specified register, AC or T. Logically OR CI with the wordwise OR of the result. Place the value of the carry OR on the CO line.
In step 19 (F-group 6, R-group I), logically OR CI with the word-wise OR of the logical AND of AC
and the data on the K-bus. Place the result of the carry OR on the CO line. Logically OR the
contents of Rn with the logical AND of AC and the data on the K-bus. Deposit the result in Rn.
In step 20 (F-group 6, R-group II), logically OR CI with the word-wise OR of the logical AND of
AC and the data on the K-bus. Place the value of the carry OR on the CO line. Logically OR the data
on the M-bus with the logical AND of AC and the data on the K-bus. Deposit the final result in AC
or T, as specified. Deposit the final result in the specified register, AC or T.
In step 21 (F-group 6, R-group III), logically OR CI with the word-wise OR of the logical AND of
the data on the I-bus and the data on the K-bus. Place the value of the carry OR on the CO line.
Logically AND the data on the I-bus with the data on the K-bus. Logically OR the result with the
contents of AC or T, as specified. Deposit the final result in the specified register, AC or T.
In step 22 (F-group 7, R-group I), logically OR CI with the word-wise OR of the logical AND of the
contents of Rn and AC and the data on the K-bus. Place the value of the carry OR on CO. Logically
AND the data on the K-bus with the contents of AC. Exclusive-NOR the result with the contents of
Rn. Deposit the final result in Rn.
In step 23 (F-group 7, R-group II), logically OR CI with the word-wise OR of the logical AND of the
contents of AC and the data on the K-bus and the M-bus. Place the value of the carry OR on CO.
Logically AND the data on the K-bus with the contents of AC. Exclusive-NOR the result with the
data on the M-bus. Deposit the final result in AC or T, as specified.

In step 24 (F-group 7, R-group III), logically OR CI with the word-wise OR of the logical AND of
the contents of the specified register (AC or T) and the data on the I -bus and the K-bus. Place the
value of the carry OR on CO. Logically AND the data on the K-bus with the data on the I-bus.
Exclusive-NOR the result with the contents of AC or T, as specified. Deposit the final result in the
specified register, A C or T.

2-63

Digital Systems Division

~_
946262-9701
)217)\
_ _ _ _ __

2.7.5 CPE ARRAY
The OS 10 disk controller uses an array of eight 3002 central processing elements to perform
masking, shifting, logic, and arithmetic operations on status. control. and data words. The ePE
array is organized into an eight-bit left byte and an eight-bit right byte, each comprised of four CPEs.
The CPE array may operate in left byte mode, right byte mode or full word mode, as determined by
the WS field (ROM08, 09) of the current microinstruction. The WS field controls gating of the left
byte clock (CPLCK-), right byte clock (CPRCK-) and the routing of CPE carry and shift signals.
Typical full word operations include accepting a control word (WO - W7) from the TILINE during a
slave write trap generation, supplying a status word to the TILINE during a slave read trap,
supplying a header word to the disk drive, and performing calculations with 16-bit control words and
housekeeping data in the CPE internal registers. Note that the main disk to 990 memory or 990
memory to disk data flow does not go through the CPE array. After the initial header set-up / check,
the main buffer operation takes place over the PBUS. The CPE array does, however, perform
housekeeping calculations and tests between successive TILINE master cycles. Recall from the
description of the TILINE master access logic that a separate TILINE master cycle is required for
each word transfer.
Typical left-byte operations include masking and testing the flag bits connected to the I-bus inputs of
the left-byte CPEs, performing calculations and tests on control word fields which lie in the left byte
(0-7) of the CPE internal registers, and loading data into the unit select register.
Typical right-byte operations include masking and testing the flag bits connected to the I-bus inputs
of the right byte CPEs, performing calculations and tests on control word fields stored in the right
byte (8-15) of the CPE internal registers, and loading the most significant TILINE bits into the
TILINE MSB address register.
This list of typical operations is not intended to be exhaustive, but to illustrate that in many cases it is
possible to conserve CPE internal register space by performing byte rather than full word operations.
The flowcharts of Appendix C are clearly annotated to identify left byte, right byte, and full word
operations.
Refer to figure 2-25, the simplified diagram of the CPE array inputs and outputs. The diagram shows
the relationship between the microprogram ROM, the CPE array, the CPE carry and shift logic, and
the CPE input and output buses.
All the CPE devices receive the same function code on bits 1-7 of the ROM bus, but do not store the
results in the internal registers until the negative-going transition of the clock pulse. The clock pulse
to both bytes may be disabled by the CPE conditional clock bit (ROMOO). Also, left byte clock is
disabled for right byte operations (ROM08, 09 = II) and right byte clock is disabled for left byte
operations (ROM08,09 = 10). Both CPE left and right byte clocks are gated versions of M PCK-.

The three-state D-bus output drivers are driven by the CPE accumulator AC register contents and
enabled on a full-word basis. The CPE to P-bus enable signal (PBCPE-) is connected in parallel to
the enable data (ED) inputs of all the CPEs. It is possible to enable the 16 data outputs during a left
or right byte operation. For example, loading the four most significant TILINE address bits into the
TILINE MSB address register is a right-byte operation involving PBUS 11-14. All 16 CPE
accumulator output bits are placed on the P-bus. The MSB address load signal, decoded from the
special group 00 of the microinstruction, loads the applicable four bits into the MSB address
register. The unused 12 bits appear on the bus, but do not affect operations.

2-64

Digital Systems Division

ROM12

CARRY INTO LS ACTIVE STAGE, RIGHT SHIFT INTO MS ACTIVE STAGE

ROMl-7

CPE FUNCTION CODE

.. F6-FO

RO

r---- -,
ROMO, 8,9 ..

MICROPROGRAM
ROM
40 BITS
512 WORDS

~~~d~'

11,

ROM13-15
r

I
1
1
1

I
I
I

---.

MCUADRl-9

ADDRESS {
CONTROL
LOGIC

LEFT. RIGHT.
CONDIT IONAL CLOCK

I

K-BUS INPUT

I
I
I

ENABLE DATA OUTPUT

.. CK

I

L_-r_J

ROM20,
21

ROMI~~}

DECODING
LOGIC

LI

I
1

---

CI

-

.

~
CPE
CARRY
AND
SHIFT
LOGIC

I

.. ED

TEST BIT

CPE
ARRAY

OTHER
LOGIC

FLAGS AND DISK
')TIMING

(
ENABLE ADDRESS
OUTPUT

•
•

I

PROCESSOR BUS

M

...
~

EA

TILINE
MASTER
LOGIC

(A) 1 35706A

Figure 2-25. CPE Array Simplified Inputs and Outputs

.

ADD! ~ESS
CON TROL
LOGIC

0

I
...

-

X,Y

K

CLOCK

ROM22-31 • ROM 17-1 9

.

A

::oJ
TILINE ADDRESS

(~

•

~------~

946262·9701

The address (A-bus) outputs are enabled on a full-word basis by the TILINE access OK output of the
TILINE master logic. The A-bus outputs supply the 16 least significant bits (TLADR04- through
19-) of the TILINE address during a TI LINE master cycle operation. This is the only use of the CPE
A-bus outputs.

The CPE array has three input buses, the I-bus, K-bus, and the M-bus. Bit assignments for these
buses are given in figure 2-26. The I-bus inputs, which represent disk timing and flag inputs, are
fixed (hardwired) inputs. The M-bus and K-bus inputs are controlled by the currently active
microinstruction. The M-bus inputs are wired to the processor bus, PBUS (00-15)-, so that the
M-bus input data is determined by the processor bus source field, ROMI3-15. The use which the
CPE makes of the M-bus input, if any, is determined by the function code, ROM 01-07.
The K-bus inputs to the CPE array are supplied by multiplexers which are steered by the KC field of
the active microinstruction. The multiplexer output may be all ones, all zeros, or the eight-bit
immediate operand field of the active microinstruction. The K-bus inputs are active low, so selecting
all ones with the KC field puts low levels on CPKOO- through CPK 15-. The K-bus inputs are used to
mask one of the ALU inputs.
Each individual CPE has a carry input. and two look-ahead carry outputs. The ePE carry and shift
logic contains an array of multiplexers and SN74S I 82 look-ahead carry generators. These carry
generators supply the carries which are required from one two-bit ePE to the next higher significant
CPE. The multiplexers are steered to handle the carries on a left byte. right byte. or full word basis.
The right-shift inputs and outputs within the bytes are hardwired from CPE to ePE. The source of
the right shift input (LI) to the most significant stage of a byte. and the destination of the right-shift
output of the byte are dependent upon the mode selected, left byte, right byte. or full word. The ePE
carry and shift logic performs the shift steering between bytes for these modes.
The conditional branch! return test bit is incorporated in the CPE carry and shift logic. This test bit
controls the execution of the conditional branches and returns specified by ROM 17-19. the BC field
of the microinstruction. Some nonarithmetic ePE instructions use the carry output as an auxiliary
bit to identify the results of a bit or word test. The carry output from the most significant active stage
controls the TESTBITQ flip-flop, which in turn controls execution of conditional branches and
returns. For example. an F-group 5. R-group III microfunction causes the contents of the AC or T
register to be ANDed with the K-bus input, and ORed with the carry input. A carry output is
generated if the result of the word-wise inclusive-OR is nonzero. The latched carry out. TESTBITQ.
may be used to select one of two possible microprogram paths. The carry and shift operates with or
without the microprocessor clock.
The microinstruction which sets up the test and conditional branch may stop the ePE clock (via
ROM 00), so that the contents of the ePE registers are not modified. Omitting the ePE clock allows
the bit or word testing to be nondestructive.
2.7.6 CPE ARRAY AND PROCESSOR BUS. Figure 2-27 is a detailed block diagram of the CPE
array and the processor bus. This figure shows all the important signals associated with control of
the processor bus and the left/ right byte CPE arrays. The CPE carry and shift logic is not included in
the diagram.

2-66

Digital Systems Division

A. CPE K-BUS (MASK) INPUTS
WS FIELD
(ROM08. 09)

KC FIELD
(ROM10. 11)

CPKO

00

1-

01

~.--

4

3

5
I

~

6

'7

8

---~

ALL ZEROS*

- - -...

EXTE.NDED SIGN BIT (ROM32)

-----.

XX

FULL WORD
WORD SHIFT OR

10

10)

11

4--._-

LEFT BYTE

10

-

1M

(ROM32-39)

10

11

~.--

1M

(ROM32-39)

~~1>'1::T E~~1:1>~ANY
EXTENDED SIGN BIT (ROM32)

10

9

I

I

ALL ONES *I(SEE NOTE)

I

11

'12
I

I

14

13

I

15

i

I

ALL ONES

ALL ZEROS

'""'"

-+

}

SPECIAL FIEL:>
DECODING ALSO
ENABLED

.

1M (ROM32·-39)

~

.
..

1M

(ROM32--39)

1M

(ROM32--39)

...

1M

(ROM32--39)

.

B. CPE I-BUS FLAG INPUTS

o

2

3

4

5

6

'7

8

9

(B) 138251 (1/2)

Figure 2-26. CPE Input Buses (Sheet 1 of 2)

10

11

12

13

14

15

C.
BUS SOURCE
FIELD
ROM 13 14 15

SELECTED
SOURCE

0

0

0

ZEROES

0

0

1

CPE OUTPUT
WORD
(AC REGISTER)

0

1

0

HI-Z

PBUSO

0*

2

PROCESSOR BUS (CPE M-BUS) INPUTS
4

5

6

7

8

9

10

"

0

0

0

0

9

10

14

15

0

0

13

14

15

12

13

0

0

12

0

0

0

0

0

0

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1

2

3

4

5

6

7

FIFO
OUT
8

9

10

11

12

13

14

15

DIRECT
REG
0

1

2

3

4

5

6

7

DIRECT
REG
8

9

10

11

12

13

14

15

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

OFFLINE

NOTRDY

~~~~1:7;T

WCHK
~WRITE
HECK)

SPAREING

SECTORB

SECTORB

08

04

02

01

X

X

X

X

CPE

CPE
0

8

"

~LOATING

US)

TLDATA

TLDATA
0

1

1

TILINE

1

0

0

DISK*K
DATA
UNDIRECT
ODE)

DISK DATA
(DIRECT
MODE)

N

~

0

FIFO
OUT
0

00
1

0

1

NOT DEFINED

1

1

0

DISK STATUS

,

1

1

NOT DEFINED

X

X

WP

X

SPA

SKIC

~~g~-

SPA

PLETE)

X

X

X

R

REI

E

N-

X

IN-

X

SWBIN
fRIVE B
IXED/
REMOVABLE)

SWAIN
SPAREIN4 SECTORB
(DRIVE A
FIXED/
16
REMOVABLE)

X

X

X

X

SECTORB SECTORB

NOTES.

* THE

DATA INPUT AND OUTPUT BJ SES FOR THE 3002 CPE ARE ACTIVE LOW. THUS. WHEN THE PBUS
IS COMMANDED TO "ALL ZEROES". THE VOLTAGE LEVELS ON PBUSOO-THROUGH PBUS 15- ARE HIGH
( ::::: 2. 8 VOLTS).

** DISK
READ DATA IS CONVERTED FROM SER IAL TO PARALLEL (PARDATOO
ROUTED TO THE DIRECT READ REGISTER AND FIRST IN-FIRST OUT (FIFO)

THROUGH PARDAT 15)
AND
BUFFER INPUTS. OUTPUT
SELECTION IS CONTROLLED BY THE DIRECT/INDIRECT MODE F/F. WHICH IS SET OR RESET BY SPECIAL
GROUP 01 OF THE MICROINSTRUCTION.

(B)138251

(2/2)

Figure 2-26. CPE Input Buses (Sheet 2 of 2)

~~-----------------------------------------~

946262-9701

TILiNE BUS

.... ;~ INE BUS

TILINE BUS

1

ROMQO-39

FROM MICRO-

f

f

PROGRAM ROM

MICROCODE CONTROL
ROM BUS (ROM)
PBZERQPROCESSOR

,

BUS

ROMI3L-15L

SOURC":.£

DECODER
FROM MICRO-

"-

PBUSE'I.

PROCESSOR
CLOCK LOGIC

SH12

I

RQMI3L-15L
PROCESSOR

CONTROL

PBUSENL

PBUSENL

REGISTER

SHU

ROM20, 21

'"

5

} ".'0"",. "C,
(PBUS) SOURCE

CONTROL

PBOSKSTAPBDSKOAT-

G

BUS

ROMI3-IS

Q

~9TL!)AT-

PBCPE-

ROM20L,21L

UNITL')AD

PROCESSOR
BUS DES-

ROM20L,21L

ROM20L.21L

C~, o~,",C

DEC'JDER

f

MDACT-

F"RO .... TILINE
MASTER LOGIC

} '''" .0,.,,,

OSKBUSLD-

TINATION

G

UTCSHIN-

SH12

FIFO CONTROL

G

FROM MICRQ-

{

FROM CPE

CARRY AND
SHIFT LOGIC

FROM CPE

CARRY AND
SHIFT LOGIC

¥

MPCK

PROCESSOR

{

CLOCK LOGIC
MSBADRLD-

•

TILINE

TLADROO- THRU

MSB
11-1.4
C.

LI

"

ROMOI-07

J

""

t:::::~:;:
FLAGS

"'-

"-

REAOQQOIAGFAUL TO-

"."
"0"

-----

" " ROM07

"-

~

-----

"

I

V

LEFT

FO

CPE

CPXO 3
X

v

4

PROCESSOR

CK

CLOCK LOGIC

ROM36-39

TO FIF"O

FIFOOUT18

""'""-

FIFOQUT19

"'-

SPAREIN2
SPAREIN1

3002
DEVICES)

FROM BUS SOURCE DECODER

CPK08-THRU 15

3
To RIGHT BYTE CPE

INPUT MUX

I

BYTE
ARRAY

.

CLJCK

•

} .. ..

X

V

REG •

PBUSIS

PBCPE..-

"""","0

r4

EO

PARALLEL

3002
M

DEVICES)

PBUS08 THRU15

T~

0

"~"~

04-07

V

PBTLDAT
4

FROM TI LINE I F

SH10, 11

FROM DISK 1/1=" FIFO OUT/ZERO MUX

DISK

SEl.ECTASELECTB-

UNIT

FROM BUS

SELECT

DISKSEL-

~_SPAREOUTQI-

REG_
SHI4

S'.)URCE
DECODER

I)
P-BUS BUFFER

PBUSOO

PBUSOO THRU PBUS15

THRU PBUS'S

BUI="!="ERED PROCESSOR BUS

NOTE:

SH15

ALL SHEET REFERENCES A RE TO

LOGIC DRAWiNG 937502.

F"ROM DISK STATUS UNE RECEIVERS
F"ROM DISK DIRECT READ REGISTER

(9 LINES)

>

t

RECEiVERS SHB-l1
PBU50Q-THR

CPRCK

j

ADD256-

UNITLQAD-

TILINE DRIVER!
8·, ROR-

PBUS08 - THRU 15·

PROCESSOR BUS (PBU500- THRU 15 )

t---D

SH14

RO

K

SHe.9
PBUSOo- THRU 07-

SELECT

AND SHIFT LOGIC

LO~IC

0

ADDRESS

CPSHIFT6-THRU

CPKOB- THRU 1.5

5

ADDOOO1- THRU

DISK

7-15

", , " ,

CPY4-7
V

CK

EO

M

CPE

CPX4 ·7

(CPE RIGHT

I
PBUSOo- THRU 15-

RIGHT

FO

BYTE CLIJCK)

+

ACCESSOK-

DISKBUSLD-

RQM07

PBCPE-

5

F6

SHIFT L )GIC

3

.

FIELD DECODER

~
~
~
~
~
.....

CARRY AND

PRQCESS,)R

PBU500-THRU 07-

'"
"

~o",

"'RO~

SPAREOUTQl .........
DCRCERRQ-

MSBADRINC

SPECIAL

"-

"-

FROM MICRO

PARALLEL

CPLCK-

}

STQPFLAG

• ROL-

(.

(CPE LEFT

"-

(WS. KC FIELOS)ROM8 -11

om,
CPSHIFT2- THRU

BYTE CLOCK)

A

INDEXMRKQ·

RO

K
FROM MICRO-

SIGNBIT-

,~o. t

.6

CPKOO-THRU 07-

SH7

EA

FROM ROM

.

.....

COUNTER
SI-Ill
.NC

TLADRI2- THRUI9-

ACCESSQK-

~_ TLAOR03-

REG/

2

ARRAY

MUX

riM)ROM32-'l1

A

EA

BYTE

"'-

TESTMODEQ

r-

6

t-... ROMO'
t-... ROM02
t'--. ROM03
t-... ROMO'
t'--. RaMOS
t'--. ROM06

"-

OSTARTe

RDYOIRSTATQADDACQ

TO RIGHT BYTE CPE

.

TLAOR04 THRU 1 t-

ACCESSOKFROM TILINE MASTER LOGIC

ADDRESS

C,

LI

PBUSOo- THRU 15PBUSOO- THRU '5-

TO FII=O INPUT fo.,i'.liX

(D) .37646

Figure 2-27. CPE Array and Processor Bus (PBUS)
Block Diagram

2-69/2-70

Digital Systems Division

~------~

946262-9701

Tho t-h .... aa C"+n+.o. ........ "'.n.,n,.C'I .... _ _ l... .. 'I"":1"'< +t... _ _ _ :_ ,.J...,. .. _
I U"

LU1""-':H.U.L'"

l-'lV"''''~~VI

UU;:,

I~

lll'" l u a l l l u a l a

+_...,._ro.f __ __ +t.... ..... ~+1-...:_ +L.. ...... nC'lf).
llall;)l~l

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lll\"

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l J J I V Ul;:)l\.

_ . . . . _ .... __ 11 __
~Vl1l1VllCl.

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processor bus, under microinstruction control, can transfer data from any bus source to any bus
destination. The following are typical examples:
PBUS Source

Destination

CPE

TILINE output drivers
Disk, via FIFO and parallel/ serial shift register
Test data shift register. via FI FO and parallel/ serial shift register
Disk (sector) address register
U nit select register

TILINE line receivers

ePE M-bus inputs
Disk, via FIFO and parallel/ serial shift register

Disk Data (indirect)

TILINE output drivers, via FIFO
CPE M-bus inputs, via FIFO

Disk Data (direct)

CPE M-bus inputs via direct read register
TILINE output drivers via direct read register

Disk Status

CPE M-bus inputs

All Zeros

Any of the above

The bus source field of the microinstruction (ROM 13-15) determines which data is gated onto the
processor bus. The bus source decoder ROM, which is described with microinstruction decoding,
supplies the source control signals. These signals are:
Signal

Description

PBZERO-

Enable zeros (from FIFOOUT / Zero mux) onto P-bus.

PBCPE-

Enable ePE D-bus outputs.

PBTLDAT-

Enable TILINE line receivers.

PBDSKDAT-

Enable direct read register or FIFO output, depending on
state of direct/ indirect F / F.

PBDSKSTA-

Enable disk status line receivers.

The processor bus source decoder is strobed by PBUSENL, which is a delayed version of MPCK-.
Figure 2-28 shows the timing relationship between microprocessor clock and PBUSENL. The address generator selects a new microinstruction on the rising (trailing) edge of MPCK-. There is an
unsettled period as the ROM outputs change and the new microinstruction is decoded. The low
PBUSENL signal delays P-bus source decoding until 100 nanoseconds after the rising edge of
MPCK-. This delay allows conditions to stabilize before any data is gated to the P-bus, preventing
noise bursts on the bus.
The ROM 13L-15L and PBUSENL signals are supplied to the decoder by the processor bus source
control latch. This latch is transparent unless a TILINE master cycle is in progress. That is, the
ROM 13L-15L and PBUSENL outputs follow the ROM 13-15 and PBUSEN or CLKTI-, fine line

2-71

Digital Systems Division

~------~

946262-9701

300±10
NSEC
MPCK-

~: 80±5~

I

,NSEd
I

,
-.'
I

,I

l

120±5

i4-

NSEC I

I

PBUSENL - - - - , - .
I
,-~

_.I

(A) 137634

100±5 t ..

........ NSEC~
I
I

Figure 2-28. Microprocessor Clock and PBUS Enable

inputs with only a gate delay, unless the TILINE master device active (MDACT-) signal goes active
(low). A low MDACT- signal latches up the states which existed on the negative MDACT- transition.
ePE output data may be routed to one of several destinations. Recall that the CPE output data (Dbus) is supplied by the AC register in the CPE. CPE data may be sent to the TILINE line drivers and
on to the 990 memory during a slave read trap operation or a STORE REGISTERS command. CPE
data may be sent to the disk. via the FIFO and serial/ parallel register when updating header
information, or as part of a TRACK FORMAT command. Data is transferred to a test data shift
register as part of the controller self-diagnostic tests. The path to the test data shift register is
identical to the write data path, except that the serial data is gated into a shift register rather than a
disk 1/ F line driver.
CPE output data is loaded into the unit select and disk address select registers as part of any
command which involves data transfer to or from the disk (READ DATA. READ
UNFORMATTED, WRITE DATA. WRITE UNFORMATTED. or WRITE FORMAT).
CPE output bits 11-14 must be l~aded into the TILINE MSB address register before any series of
TILINE master cycles. The MSB address register supplies TILINE address bits 0 - 3, and the CPE
A-bus outputs supply address bits 4 - 19. The CPEs keep track of the number of words transferred
and increment the MSB address register each time a 64K word boundary is passed.

The TILINE line receivers supply a data word to the CPE M -bus inputs on each TILINE slave write
cycle initiated by the 990 computer. The eight DS10 control words, WO-W7, are loaded into the
CPE scatchpad registers by a sequence of eight slave write cycles. Also, during a disk write operation, the DS10 controller, acting as a TILINE master, reads data words from the 990 memory to the
disk via the TILINE, the FIFO buffer, and the serial/parallel converter.
Data read from the disk is converted from serial to parallel form and routed to the inputs of the read
direct register and the first in, first out (FIFO) buffer. The direct register is selected to supply data to
the CPE in the case of checking header words. However, when a buffer from disk to 990 memory is
required, the FIFO is selected in order to allow for data rate differences between the disk and the
TILINE.
Disk status words are routed from the status line receivers to the CPE M-bus inputs. The sector addresses and other disk status information in these words must be checked repeatedly during any
operation which involves data transfer to or from the disk.

2-72

Digital Systems Division

~------~

"0
~.o

946262-9701

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The functions of the CPE carry and shift logic include:
•

Carry generation for arithmetic operations in left byte, right byte, and full-word groups

•

Test bit generation for the conditional branching microinstructions

•

Conventional right-shifting of 16-bit words

Each 3002 ePE processes a two-bit slice of data on the I, 1\.-1, and/ or K-bus inputs. Each device has
the necessary internal interconnections for shift and carries within the device. In order to process
eight-bit bytes or 16-bit words, carry and right shift interconnections are made between the devices.
Each device must be connected to accept a carry input, send a carry output, right shift a bit and
accept a right-shifted bit from another stage. The CPEs are grouped to operate in right byte, left
byte, and full-word modes.
Figure 2-29 shows the CPE carry and shift circuitry. The CPE data input, output, and function
control signals are omitted for clarity. The CPE signals involved in carry and shift operations are:
CI

Carry input

CO

Ripple carry output (not used)

X,Y

Carry propagation and operation outputs for high-speed look-ahead carry

RO

Right shift output (three-state, enabled only during right shift operations)

LI

Right shift input from the adjacent (more significant) state. Also called "'left
input".

In addition to the ordinary arithmetic functions, the carry outputs are used during comparison
operations to indicate the result of a comparison. For example, the TZR instruction (F-group 5,
R-group I, K= II) will test the specified register for zero contents, and force a carry output if the
register is nonzero. The carry is used to set a test bit flip-flop, which steers the execution of
conditional branch instructions. This is the way in which execution is steered through alternate paths
in the microcode program.
2.8.1 THE TEST BIT F IF AND CONDITIONAL BRANCHING. The branch control (BC) field
of a microinstruction specifies how the controller is to select the next microinstruction. There are
four conditional branch control codes:
ROM

17,

18,

0

19

Description

0

Conditional branch (if TESTBITQ true) to next
ROM address (NRA) else RA + I

0

Conditional branch (if TESTBITQ false) to next
ROM address (NRA) else RA + I
0

Conditional return (if TESTBITQ true) to address
stored in stack of address generator else NRA
0

Conditional return (if TESTBITQ false) to address
stored in stack of address generator else NRA

2-73

Digital Systems Division

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946262-9701

These conditional branches/ returns all use the output of the test bit flip-flop. TESTBITQ, as the test
condition.
The test bit flip-flop monitors a number of conditions. depending on the ePE operation commanded
by the microinstruction. For any ePE operation other than shift. the test bit F; F monitors the carry
output of the most significant ePE state. For shift operations. the test bit F; F monitors the right
shift output of the least significant ePE stage. The carry and shift multiplexers select the
carries; shifts from the left or right byte. as specified by the microinstruction WS field . Table 2-8
gives a complete listing of test bit F I F inputs.
Table 2-8. Test Bit Flip-Flop Inputs
CPE Functions

Byte/Word Selection

TESTBIT-Source

Shifts:
Left byte

Right shift output of left byte LSB (ROL-)

Right byte

Right shift output of right byte LSB (ROR-)

Word shift

Right shift output of word LSB (ROR-)
from right byte

Left byte

Carry output of left byte MSB

Right byte

Carry output of right byte MSB (CIL-)

Word

Carry output of M S B (left byte)

Arithmetic
Operations
or
Bit Testing:

The output of the test bit flip-flop, TESTBITQ, the TRAP signal, and the branch control field of the
microinstruction, ROM 17-19, supply the address input to the branch control ROM. This ROM
supplies control signals to the address generator based on the Be field and the test condition, or on
the existence of a trap.
The 3002 ePE has a number of nonarithmetic instructions which use the carry lines to indicate the
results of a data test. Refer to the ePE instruction set for a complete list. The A NM instruction, for
example, logically ANDs the M-bus input of the ePE with the accumulator contents. A carry is
generated if the result is nonzero, and the result is placed in the accumulator or T-register. A carry
input from the adjacent (less significant) stage will also cause a carry out. Each ePE tests a two-bit
slice, but the carry circuitry makes the carry output of the MSB valid for the whole byte or word.
For right byte operations with an ANM instruction (F-group 4, R-group II, K-bus = II), a carry
output from the right byte indicates that the eight-bit result is nonzero.
The zero or nonzero result of the data test is often much more important than the eight or I6-bit
value. By omitting the ePE clock pulse, it is possible to perform the data test without storing the
result. The ALU, carry, carry look-ahead and right shift logic of the ePEs is not controlled by the
ePE clock. The ePE registers do not accept the result of the operation until the negative-going edge
of the ePE clock pulse.
The ePE conditional clock bit (ROMOO) allows the microinstruction to inhibit the ePE clock for
nondestructive testing. This may be done in conjunction with one of the conditional branching
microinstructions. The ePE performs the operation specified in ROM 0 I - 07, and the test bit flip-

2-74

Digital Systems Division

~~-----------------------------------------------------~ 946262-9701

TEST BIT F/F
TESTBIT-

MICROPROCESSOR
CLOCK

MPCK

0

I
I

Q

Q

CK

~~T~E~S~T~B~I~T~Q~

I

.

TRAP

______________________________________________~~

I

I

MCUCI
BRANCH
CONTROL
ROM

ROMI9
ROMI8

WS FIELD

MCUSI-6

FUNCTION

I

•

ROMI7

~ ADD~OGIC-SH6 L.._:::~~=_..I____

RIGHT SHIFT MUX
L1R-

ROM 8,9

.-J

RTSHFTRO*

RTBYT-

LFTBYT-

o

0

ROL-

ROR

1

1

WORD

o

1

ROL-

ROR

1

1

SHIFT WORD

1 0

ROL-

ROL

o

t

LEFT BYTE ONLY

1

ROMI2

ROR

1

o

RIGHT BYTE ONLY

1

'RTSHFTRO 15 ALWAYS ZERO UNLESS A RIGHT
SHIFT (F-O, R-ll1) FUNCTION 15 EXECUTED.
CARRY PROPAGATION

..

TESTBIT-

Cn+Z

Cn

WORD LOOK-AHEAD CARRY GENERATOR

y

X

2

C
n+y

2

Y

X

1

x

1

c

T
1

CPE OPERATION

ROMI2

o

,

LEF! BYTE
OVERFLOW

RTSHFTRO

CI FIELD

ROM12

I'"

SHIFT

ALL OTHERS

o

SHIFT ONES INTO MSB

CARRY INTO LSB

1

SHIFT ZEROS INTO MSB

NO CARRY INTO LSB

r - - - SHFCMD
CPE FUNCTION CODE
000111X
tr-GROUP 0

CPXLA

.. , .. ----to

14-

CPXRA

LEFT
BYTE CARRY
MUX
•

CPXL

DI;=S'g,kRY
PROPAGATION

V

SHFCMD

MULTIPLEXERS

14--

RIGHT
BYTE CARRY
MUX
i- CPXR

CPYRA
CPYLA

CARRY EQUATIONS FOR SN74S181 WITH ACTIVE [J)W CARRY OUTPUTS
X

··0"

c-=
YO(XO+~)
N+X
-C--

"I·'

N+Y =

Xo Y;- YO~)
tHX

C N+ Z = Y 2 (X 2+ XI Y

t

)
X0Y0 Y

Y = Y 3{X:: X 2 Y 2+ X t Y I Y 2+

RTBYT-

X=

LFBYT-

X+X+X+X
3

2

1

t

Yo Y I (; N )

yo Y 1 Y 2)

0

CARRY PROPAGATION

CARRY PROPAGATION

"--

Y1(X ,+

y I(X,+ C

~~'

CPYL

=P,Y
=G
KKK
K

'---

Y

X

C
LEFT BYTE LOOK-AHEAD CARRY GENERATOR L..-- X

3

,

j

3

N+Z

c

x

X

I

Ll

"'"

RO ... CPSHIFT2-~

Ll

ROMt2

~9 }

X

Y

X

Y

Y

Y

3

L1

Ll

RO .....

00

I

PBUS07-

PBUSOO(MSB)

Y

~ARRY4

Ul

~
o

(

LIR-

ROL-

x

Y

1-_ _ _

~3

RIGHT
SHIFT
MUX
RTSHFTRO

..--- 0

,--v

-

LI

01

L1

X

CARRY5Cl_

3002
CPE

3002
CPE
RO ....CPSHIFT6-.,.

FROM
MICRO-PROGRAM
ROM

X

Y

0

+X

o

o

Cl,..,...-

3002
CPE
RO ..... CPSHIFT4- _

01

DO

X
C I [....
, . .______...J

Ul

C

1

ROM12

N,...

SHI2

Y

2

3

WORD
SELECT
FIELD

Y

Cl

3002
CPE
RO ~CPSHIFT3- ~

X

(CARRY-)

r-

I '(
01

Y

o

o

CI~

ROMI2,.

Y

o

ROM08

3002
CPE

CPE

x

I

rACCV'

3002

N+X

~

X

Y

,

C

Y

1

1'1

DO

o

o

N+Y

Y

X

o

o
~

X

C

C

Y

X

RIGHT BYTE LOOK-AHEAD CARRY GENERATOR -

SHI2

CI
3002
CPE

CPSHIFT7- _
RO

~

Ll

x

Y

h.£ARRY6...-

.... CPSHIFT8- .,.,
RO
-....

DO

C!p+3002
CPE

L1
01

I

'·1"

Y

RO

~ ROR-

DO

p15-

P8US08-

(LSB)

1~1

·1'

ROR

MULTIPLEXED RIGHT SHIFT OUTPUT
(e) 137638

Figure 2-29. CPE Carry and Shift Logic

2-75/2-76

Digital Systems Division

~_
946262-9701
Jd7~
_

_ _ _ __

flop monitors the test resuii (carry ouipui). The condiiionai branch is performed. based on ihe iesi
results, and the next microinstruction is fetched. The eight or 16-bit result is not stored.
The CPE right shift outputs are supplied by three-state drivers which are enabled when a right shift
function (F-group 0, R-group III) is specified. The test bit flip-flop monitors the right shift output
from the least significant state of the left or right byte. This allows the LS B to be used to control
conditional branching. If the CPE conditional clock bit (ROM 00) is set. the register contents do not
actually shift, and the test is nondestructive.
2.8.2 SN74S182 LOOK-AHEAD CARRY GENERATORS. Look-ahead carry generation is based
on the fact that it is possible to use combinational logic on the data inputs to an adder circuit to
determine in advance if that stage will generate a carry or allow a carry from a lower stage to
propagate through as a carry. The carry propagate and generate function outputs from individual
stages are combined to determine the anticipated carries for all the stages and to supply those carries.
As word lengths become longer, carry look-ahead becomes much faster than ripple carry.

The look-ahead scheme does require that the adder contain the additional logic necessary to develop
the carry generate and propagate functions. Carry look-ahead can be used to combine multibit adder
circuits which have internal ripple carry.
The SN74S182 is a four-stage look-ahead carry generator which provides rapid carry generation for
four binary stages or groups of stages. The most significant stage of the SN74S I 82 develops carry
propagate and generate outputs which may be connected to the inputs of another SN74S 182. These
devices may be cascaded in this manner to perform full look-ahead across n binary stages.
The SN74S182 can be used in either active high or active low carry propagation schemes. The 3002
CPE generates active high look-ahead outputs, X and Y, and requires active low carry inputs. The
carry equations in this form are:

The group carry look-ahead outputs from the SN74S 182 are:

Note that the group carry look-ahead outputs, X and Y, are developed only from the individual X
and Y inputs, and do not incorporate the ripple carry input. Cn -. When'S 182 generators are
cascaded, the ripple carry input must be routed to all the carry generators.
As shown in figure 2-29, a single SN74S 182 device provides carries for the left byte CPEs, and
another one serves the right byte CPEs. An additional'S 182 is used to link the left and right bytes
during full word operations. This unit is also used in the conditional branching operations.

2-77

Digital Systems Division

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946262-9701

2.8.3 CARRY AND SHIFT LOGIC CONTROL. The carry and shift logic is controlled by the
processor control microinstructions, either directly or through decoders. The word select field, ROM
08, 09 determines whether the CPEs operate in word, word shift, left byte, or right byte modes. Refer
to the WS field decoding table incorporated in figure 2-24.
ROM 08 and 09 are used to steer the right shift multiplexer. These two bits also control the left byte
(LFBYTE-) and right byte (RTBYTE-) signals as shown. The LFBYTE- signal steers the right byte
carry multiplexer, and the RTBYTE- signal steers the left byte carry multiplexer. The LFBYTEsignal, when low, disables the CPE right byte clock signal, CPRCK-. The RTBYTE- signal, when
low, disables the CPE left byte clock, CPLCK-.
ROM 12 controls the carry input, CI, to the least significant active CPE. For right byte or full word
operations, this carry is directly wired to the least significant bit of the right byte. For left byte
operations, the carry is routed through the word look-ahead carry generator to the LSB of the left
byte. The CPE interprets ROM 12 as follows:
ROM 12

o ==
1 ==

carry or one fill for shift operations
no carry or zero fill for shift operations

The right shift output of a CPE, RO-, is a 3-state output which is enabled only when the CPE function code specifies a right shift operation. The CPE performs right shifts for F-group 0, R-group III
function codes. The processor control bits which supply this function code are:
ROM 01 02

03

o o

04
1

05
1

06
1

07
X

x
X

= 0, shift T -register

=

1, shift AC (accumulator) register

These bits are also decoded external to the CPEs to produce the shift command (SHFCMD) signal.
The SHFCMD signal is used to disable the left and right byte carry multiplexers during shift
operations.
2.8.4 RIGHT BYTE CARRY OPERA TIONS. A carry may be generated by a CPE as the result of a
two's complement arithmetic operation or a bit test operation. Assume that the processor control
microinstruction (ROM 00-39) specifies an arithmetic operation on the right byte. The right shift
interconnections and the entire left byte may be ignored for this description.
ROM 12 is the carry input to the least significant stage of the right byte and the 'S182 carry
generator. The 'S182 generates the interstage carry signals, CARRY6-, CARRY5-, and CARRY4-,
as required.
Assume that there is a carry overflow from the most significant stage of the right byte. The right
byte look-ahead carry outputs, CPXR and CPYR, go through the right byte carry multiplexer as
CPXRA and CPYRA. These signals are the X o, Yo inputs to the word carry look-ahead generator.
The carry bit, ROM 12, from the processor control microinstruction is wired to the C,,- input. The
output of the first stage of the word look-ahead carry generator is:
CIL-

==

CPYRA (CPXRA

+

ROM 12-)

CIL- is not used by the left byte for this example but it is used in carry propagation within the 'SI82.
The left byte multiplexer is steered by the RTBYTE signal to select the hardwired 0 and 1 levels for
CPYLA and CPXLA, respectively. These levels are selected to allow a carry from the first 'S182
stage (CI L-) to continue through the 's 182.
2-78

Digital Systems Division

~------~

946262-9701

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thP
~pl'nn£l
d~O"P nf
thp
'''J~?
""""''''1"''''''''' nf
'-'.&.
..
....,.& ...
U"-l:)_ .....
.aa. _ _
..

.&a. .....................

.1..& ......

~

&

__ ,

r._
-IITY

,

j~ "f"lt l1~pri
pytprn~1
--... _ _ - - - - - - - - - -

........... _ -

to
thp.
c::Irrv
-----_J _ _ _

J

Q"enerator The

""""

•

operation for this term is:
C n+y-

=

CPYLA

(CP~LA

+

CIL-)

For this example, Cn+y- = CIL-, and the carry, if any, goes to the third stage of the carry generator.
The external inputs to the third stage of the 'S182 are a hardwired logic 1 and RTSHFTRO.
RTSHFTRO is the right shift output of the right byte, as selected by the right shift multiplexer. For
a right byte (only) operation. ROM 8. 9 = II. which selects ROR, the right shift output of the right
byte. In the absence of a shift command, ROR- is pulled high and ROR is a logic o.
The general equation for the TESTBIT- signal is:
TESTBIT-

=

1 (RTSHFTRO

+

Cn-ty-)

For this example, the equation reduces to:
TESTBIT- = CI L-

= CPYRA (CPXRA + ROM 12-)
= CPYR (CPXR + ROMI2-)

The TESTBIT- output of the'S 182 is clocked into the test bit flip-flop on the positive-going edge of
the microprocessor clock signal, M PCK. The TESTBITQ output of the flip-flop goes to the branch
control ROM. If a conditional branch was specified as part of the microinstruction (ROM 17, 18,
19), TESTBITQ determines whether the branch occurs.
2.8.5 LEFT BYTE CARRY OPERATIONS. Assume that the processor control microinstruction
specifies a left byte only operation (ROM 8,9 = 10). and CPE operation is not a right shift. The right
shift interconnections and the entire right byte may be ignored for this description.
The ripple carry input to the left byte, CIL-, is ROM 12 for the left byte operations. This allows the
microinstruction to command a carry into the LSB of the active byte. ROM 12 is gated to CILthrough the first (least significant) stage of the word look-ahead carry generator.
The outputs of the right byte carry mUltiplexer, CPXRA and CPYRA are steered to 0 and 1,
respectively, by the LFBYTE- signal. This combination gates the carry in bit, ROM 12-, through the
's 182 as follows:
Cn+z-

= CIL-

= CPYRA (CPXRA +
= 1 (0 + ROMI2-)

ROM 12-)

= ROMi2The left byte look-ahead carry generator uses the ROM 12 ripple carry input and the X and Y outputs
of the individual CPEs to produce the required left byte carries.
Assume that there is a carry overflow from the most significant bit of the left byte. The left-byte lookahead carry outputs, CPXL and CPYL, go through the left byte carry multiplexer as CPXLA and
CPYLA, and ~re wired to the Xl Y I inputs of the'S 182.
The output of this stage of the'S 182 is:
Cn-ty-

= Y1(X I + C n+x-)
= CPYLA(CPXLA

+ ROM12-)

2-79

Digital Systems Division

~------~

946262-9701

Cn+y- is not used external to the'S 182, but it is an input term to the next stage of the look-ahead carry
generator.
The external inputs to the third stage of the 'S182 are a hardwired logic 1 and RTSHFTRO.
R TS H FTRO is the right shift output of the left byte, as supplied by the right shift mUltiplexer. It is I
for this example. This combination sets the Cntz- output equal to the C n+y - output.
The TESTBIT- output of the 'S182 is determined as follows:
TESTBIT-

1 (RTSHFTRO + Cn+y-)
Cn+y= CPYLA (CPXLA + ROMI2-)
= CPYL (CPXL + ROM 12-)

=
=

The TESTBIT - signal is loaded into the test bit flip-flop and used to control conditional branching.

2.8.6 FULL 16-BIT WORD CARRY OPERATIONS. Full 16-bit arithmetic requires the ability to
propagate carries from the right byte into the left byte. For a full word operation, ROM 8, 9 = 0, 0,
which makes LFTBYT- = R TBYTE- = I.

The ripple carry input to the left byte is controlled by the carry bit of microinstruction. The right
byte look-ahead carry generator (SN74S182) uses ROM 12 and the X and Y outputs of the CPE
stages to develop CARRY6-, CARRY5-, and CARRY4- as required. The look-ahead outputs of the
right byte carry generator, CPXR and CPYR, are cascaded (via the right byte carry multiplexer) to
the Xo , Yo inputs of the word look-ahead carry generator. ROM12 is also wired to the ripple carry
input of the word look-ahead carry generator. This is not a duplication, because the ripple carry
input is not incorporated in the logic equations for CPXR and CPYR.
The carry input to the left byte, CIL- is:
CIL-

= Yo(Xo + Cn-)
= CPYR(CPXR +

ROM 12-)

The left byte carry generator uses the CIL- input and the X, Y outputs of the CPE to develop
CARRY2-, CARRYI-, and CARRYO- inputs to the CPEs as required.
The look-ahead outputs of the left byte carry generator, CPXL and CPYL are cascaded to the XI,
Y 1 inputs of the word look-ahead carry generator. C n+y-, which is not wired externally to the'S 182, is
given by:
C n+y-

=

CPYLA (CPXLA + CIL-)
(CPXL + CIL-)

= CPYL

The X2 and Y2 inputs to the next stage are 0 and I respectively, which has as the effect of transferring
the C n+y- output, unmodified, to the C n+z- output.
The equations are:
TESTBIT-

= Y 2(X 2 + Cn+y-)
=1 (RTSHFTRO + C n+y-)
=C n+y= CPYL (CPXL + CIL-)

RTSHFTRO is always 0 unless a CPE right shift function code (F-group 0, R-group III) is executed.

2-80

Digital Systems Division

~------~

TJ...""
....'"

946262-9701

TJ:~TUIT_
....... oJ.I

C';nn~l

;C' 1"' ... ;1,"",J

~"6""U".I~

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J.vuu",u

;,." .. ", .. }..", .. ", ..... }..:+ +1:_ +1~_
U.lLV

LlI'"

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11IP-IIVP

~_

VU

+L.~

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_~,,+

11"'/\'~

_~n:+:.,~ ~~:_~ + ............. : .. :"',.,.

PV..,ILIV"'-5V1l15

",f

Lla.lI"ILlVU V.I

microprocessor clock, MPCK. The TESTBITQ signal from the flip-flop goes to the branch control
ROM, where it may be used to control conditional branching.
2.8.7 RIGHT SHIFT OPERATIONS - GENERAL. The 3002 CPE performs a one-bit right shift
in response to an F-group 0, R-group III function code. This is a simple right shift (SRA) if the Kbus contents are all zeros. The contents of the accumulator (AC) or T-register are shifted one place to
the right. The previous low-order bit is placed on the right shift output, RO-, and the high order bit is
filled from the right shift input, LI-. Note that an individual right shift microinstruction is required
for each desired one-bit shift. If the K-bus contents are nonzero, the right shift includes a
combination of masking and right-shifting. The equations for this case are included in the detailed
3002 CPE description.
The right shift output, RO-, of the 3002 is supplied by a three-stage driver which is only enabled
when the CPE executes a right shift operation. Within the left or right byte, the RO- outputs are
wired directly to the adjacent LI- inputs. Multiplexers and control circuitry configure the CPEs to
perform left byte shift, right byte shift, full word shift, or CRC shift.
The test bit flip-flop may be used to monitor the right shift output of the least significant stage and to
control conditional branching.
2.8.7.1 Full Word Right Shift Operations. Full word right shift operations are selected when
ROMOI - 07 = OOOIIIX (F-group 0, R-group III) and ROM 8,9 = 01. The function code commands
the CPE operation and the WS field steers the multiplexers. The carries from the CPEs are irrelevant
during shift operations, and the left and right byte carry mUltiplexers are disabled (all zeros out) by
the SHFCMD signal.
A word shift to the right creates a vacancy at the MSB position. The ROM 12 signal from the
microinstruction selects zero-fill or one-fill, as follows:
ROM12

o
1

one-fill MSB
zero-fill MSB

ROM12 is directly wired to the LI- input of the left byte. Bits are right-shifted between two-bit CPEs
by CPSHIFT2-, CPSHIFT3, and CPSHIFT4-. ROL- is the right shift output of the left byte. It is
pulled high during any operation except left byte or full word right shift. For a full word shift,
ROM8,9 steer ROL- through the right shift multiplexer. The multiplexer output, LIR-, is the left
input to the right byte.
Bits are right-shifted through the right byte on the CPSHIFT6-, CPSHIFT7-, and CPSHIFT8-lines.
ROR- is the right shift output of the right byte. It is pulled high during any operation except right
byte, CRC, or full word shift. ROR- is inverted and routed through the right shift multiplexer as
RTSHFTRO.
RTSHFTRO is the right shift output of the least significant right-shifted stage. It is routed to the X2
input of the word look-ahead carry generator, and the Y2 input is hardwired to l. The Xo, Yo, XI and
Y I inputs to the 'S182 are all zeros, because SHFCMD disables the left and right byte carry
multiplexers. Under these conditions, TESTBIT- is simply RTSHFTRO in inverted form:
TESTBIT-

= RTSHFTRO

For the case of full word or right byte shifts, TESTBIT- = ROR-. Notice that the ROM 12 input to
the'S 182 has no effect on TESTBIT - for right shift operations.

2-81

Digital Systems Division

~------~

946262-9701

2.8.7.2 Left-Byte Right Shift Operations. An F-group 0, R-group III function code with
ROM8,9 = 10, commands a right shift of the left byte (only). ROM12 supplies the right shift input
to the MSB position, as described with full word shifts. The right shift output of the left byte,
ROL-, is inverted and steered through the right shift multiplexer as RTSHFTRO, right shift output
of the LSB. The LIR- output of the right shift multiplexer has no effect for left byte shifts.
RTSHFTRO is routed to the word look-ahead carry generator to develop the TESTBIT- signal, as
described with full word shifts:
TESTBIT-

=
=

RTSHIFTRO
ROL- (left byte shifts)

The test bit flip-flop stores the TESTBIT- signal and may be used to control conditional branching.
2.8.7.3 Right Byte Right Shift Operations. The word select field ROM8,9 selects the right byte with
an 11 code. The right shift multiplexer selects ROM12 as the left input to the right byte, LIR-. This
allows the microinstruction to select zero-fill (ROM12 = 1) or one-fill into the MSB position.
The right shift output of the right byte, ROR-, is inverted and selected by the right shift multiplexer
as RTSHIFfRO.
The TESTBIT- output of the word look ahead carry generator is:
TESTBIT-

=

RTSHIFTRO
(right byte or full word shifts)

= ROR-

2.9 MICROPROGRAM ADDRESS CONTROL
The branch control (BC) and next ROM address (NRA) fields of the current microinstruction
determine the address of the next microinstruction to be executed. The branch control field, ROM
17-19, provides conditional and unconditional address control functions. All the conditional address
control functions use the test bit flip-flop output, TESTBITQ, as the test condition. The test bit flipflop is described with the CPE carry and shift logic.

Function
Unconditional increment to current address

+I

Unconditional branch to next ROM address (NRA)

+I
RA + I

Conditional branch (if test bit true) to NRA, else RA
Conditional branch (if test bit false) to NRA, else
Unconditional branch and link to NRA (RA

+I

to stack)

Conditional return (if test bit true) to address stored in stack of address
generator. Otherwise, branch to N RA.
Conditional return (if test bit false) to stack address. Otherwise, branch
to NRA.
Unconditional return to stack address.

The branch control functions, test bit, and trap functions are decoded by a branch control ROM, as
shown in the simplified block diagram, figure 2-30. The function control and carry outputs of the
branch control ROM control the operations of the address generator. The NRA field of the

2-82

Digital Systems Division

~------~

946262-9701

CONDITIONAL
BRANCH
TEST BIT

POWER RESET
TRAP

TRAP

MICROPROCESSOR
CLOCK
MICRO-PROGRAM
CONTROL TO OTHER
CONTROLLER
FUNCTIONS

r

ROM

CARRY INPUT

1----.-...-.1

INTERRUPT
CONDITIONS

i

~

{

S-:~6~~~riER

--t

AND
PRIORITY
ENCODER

POWER RESET TRAP

i

r

20,

MICRO-

MCUADR~-9

~~g~~~~ Fj....:.:.:..=-:.;=..:..:...:.--=--~
GENERATOR

ADDRESS

~~b~~~~ROGRAM

MICRa- PROGRAM
ROM

ROM17-19

512 WORDS
X 40 BITS

i' ' "
(SN74S48'2)

MUX

..-II

I ~?~<;~:'~~' .

CLR

C1

TRAP

--t

-II

I
I

q

•

!S~~6

r----

ROM22-31
A

~L-_~_~

_________________N_E_XT__
RO_M__
AD_D_R_ES_S_F_I_EL_D______________

SLAVE TRAP

~

II

MOCROPROCESSOR CLDC"
BRANCH CONTROL FIELD

(A) 138265

Figure 2-30. Microprogram Address Control - Simplified Block Diagram

microinstruction supplies a nine-bit address input in the absence of a trap or interrupt. The output of
the address generator, MCUADRI-9, fetches the next microinstruction from microprogram
memory.
2.9.1 ADDRESS GENERATOR. The address generator is based on the SN74S482 expandable
control element. Each SN74S482 controls a four-bit slice of the address. An internal full adder, fourword push/ pop stack, output register multiplexer and clocked output register provide straightforward and versatile address control.
Figure 2-31 is a functional block diagram of a single SN74S482 device. The address output register is
. clocked on the positive-going edge of the clock signal (MPCK-). The output register source,
controlled by S5 and S6, may be the current address, the stack output, the adder output, or the direct
data-in address.
The push/ pop stack can be used for nesting up to four levels of program return addresses. The stack
control functions, controlled by S3 and S4, are load, push, pop, and hold. In the load mode, the
adder output is loaded into the top of the stack, replacing the previous stack output. In the push
mode, all addresses are moved down one location, and the adder output is loaded on top of the stack.
The bottom word is lost. In the pop mode, the words in the stack are moved up one location on each
clock pulse. The top word is lost. The bottom word remains, and is duplicated in the adjacent stage.
After three pop commands, the bottom word would be duplicated in all four stack locations. The
hold function causes no change in stack contents.

The adder function is controlled by Sl and S2. The adder output may be equal to carry in, carry in
+ current output, carry in + direct data in, or carry in + current output + direct data in.

2-83

Digital Systems Division

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946262-9701

CARRY IN

CLOCK

CLEAR

Ir-----------------'-----~I
Cj

CK

I
I

~

I
I

_DATA
IN AO-A3 +I______*lAi
____

Cj

4,

'\

I
I

CLR

'"

CK

I
I
I

CLR

4,

1

ADDER

,... 0,

'0 >-

I

~

:

:

~~

I

I

rr--

I

4-WORD

STACK

FO-F3 '.
MUX

4

REGISTER

/0/

ADDRESS OUT

I

-

=

I
I
I

CONTROL

~

I

I
I

I

L _ _ _Sl~ ~--~~_--S2.~--~4---~I-~6-----..J

ADDER
CONTROL

CARRY
OUT

STACK
CONTROL

REGISTER
INPUT SELECTION

(A)' 3S71 ,

Figure 2-31. SN74S482 Functional Block Diagram

Tables 2-9, 2-10 and 2-11 summarize the function control inputs SI-S6 of the address generator. The
three control groupings are independent, so that multiple address control functions may be
performed on the next clock transition. For example, it is possible to select the branch address and
store the incremented current address in the stack on the same clock pulse. This branch and save
operation requires carry in = 1, SI, S2 = 10, S3, S4 = II, and S5, S6 = 00. Up to four branches may
be nested, with the return addresses stored in the stack.
Table 2-9. Address Generator Adder Control
MCV

SI,

S2

Adder Output

0

0

Bi + Ai + Cin

0

I

Ai

0

Bi

Comment

+ next ROM address field + carry
Next ROM address field + carry
Current address + carry
Current address

+ Cin
+ Cin

Cin

MCU carry

2-84

Digital Systems Division

~------~

946262-9701

TAb:'; 2-10. Address Geiiefiiluf Slack COillfoi

MCU

S3,

S4

o
o

o

o

Stack Function

Comment

Hold

No stack change

Load

Store word at top of stack, writing over previous
top word

Pop

Move stack up one position, losing top word

Push

Store word at top of stack, move stack down
one position, losing bottom word

Table 2-11. Address Generator Output Control
MCU

Comment

S5,

S6

Output Register Source

0

0

Data in

0

I

Adder output

0

Stack output

I

I

Output register

Current address

X

X

Clear = 0

Forces register outputs to all zeros

NRA field

2.9.2 BRANCH DECODER ROM. Table 2-12 is a listing of the contents of the SN74S288 branch
decoder ROM. In this application, the ROM is being used as a decoder to produce seven address
generator control functions. Four ROM words are dedicated to each of the eight basic branch
commands. The condition of the test bit and trap inputs determine which specific word is selected.
In the BRANCH CONDITIONAL IF TRUE command, refer to the address generator control
tables to interpret the branch decoder ROM words. If there is no trap, and test bit is false, the carry is
high, the adder output is current address + 1, and the adder is selected for output. The address
generator selects the next sequential microinstruction.
If the test bit is high, and no trap occurs, the adder selects the NRA field, no stack functions are
performed, and the output register selects the adder output. Thus, the test bit causes a
straightforward branch.

Careful examination of the branch decoder ROM listing shows that the ROM output is identical for
any trap, regardless of the test bit or the branch control field of the current microinstruction.
If a trap occurs, regardless of the test bit, the adder passes the current address, which is pushed into
the stack. The output register selects the direct data input, in which the trap address has replaced the
NRA field of the microinstruction. Thus, the trap routine is performed before the current
instruction. At the end of the trap routine, the program gets back to the trap point by accessing the
stack.

2.9.3 ADDRESS CONTROL LOGIC. Figure 2-32 is a simplified logic drawing of the address
control logic. This paragraph and subsequent paragraphs describe the address control operations
involved in normal microinstruction accessing, TILINE slave trap processing, microcode interrupt
processing, power and 110 reset trap processing.

2-85

Digital Systems Division

~

946262-9701
Table 2-12. Branch Control ROM Listing
Outputs

BC-Field
ROM 17,18,19

Test
Bit

Trap

LLL
(000)

L
L
H
H

L
H
L
H

H
H
H
H

L
L
L
L

L
H
L
H

L
H
L
H

L
L
L
L

H
L
H
L

H
L
H
L

X
X
X
X

Increment
Unconditional

LLH
(001)

L
L
H
H

L
H
L
H

L
H
L
H

L
L
L
L

L
H
L
H

L
H
L
H

L
L
L
L

L
L
L
L

L
L
L
L

X
X
X
X

Branch
Unconditional

LHL
(010)

L
L
H
H

L
H
L
H

H
H
L
H

L
L
H
L

L
H
L
H

L
H
L
H

L
L
L
L

H
L
H
L

H
L
L
L

X
X
X
X

Branch
Conditional If
Test Bit True

LHH
(011)

L
L
H
H

L
H
L'
H

L
H
H
H

H
L
L
L

L
H
L
H

L
H
L
H

L
L
L
L

H
L
H
L

L
L
H
L

X
X
X
X

Branch
Conditional If
Test Bit False

HLL
(l00)

L
L
H
H

L
H
L
H

H
H
H
H

L
L
L
L

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

H
L
H
L

X
X
X
X

HLH
(101)

L
L
H
H

L
H
L
H

L
H
L
H

L
L
L
L

L
H
H
H

L
H
L
H

L
L
H
L

L
L
L
L

L
L
L
L

X
X
X
X

Conditional
Return If
Test Bit True

HHL
(110)

L
L
H
H

L
H
L
H

L
H
L
H

L
L
L
L

H
H
L
H

L
H
L
H

H
L
L
L

L
L
L
L

L
L
L
L

X
X
X
X

Conditional
Return If
Test Bit False

HHH
(l11)

L
L
H
H

L
H
L

L
L
L
L

H
H
H
H

L
H
L
H

H
L
H
L

L
L
L
L

L
L
L
L

X
X

H

L
H
L
H

X

L
L
H
H

L
H
L
H

L
H
L
H

L
L
L
L

H
H
H
H

L
H
L
H

H
L
H
L

L
L
L
L

L
L
L
L

X
X
X
X

HHH
(111)

MCU MCU MCU
SI
S2
S3

2-86

MCU
S4

MCU MCU MCU
S5
S6 CIl

Unused

X

Comment

Branch and
Link
Unconditional

Unconditional
Return

Unconditional
Return

Digital Systems Division

"i::(
~------946262-9701

The tr..ree SN74S482 devices have a combined addressing capability of 12 lines, but orJy nine lines
are required by the microprogram ROMs. The addresses selected are determined by the address
select code and address carry from the branch control ROM, and by the input from the next ROM
address (NRA) multiplexers. The TILINE power reset, TLPRES-, is the single exception. TLPRESis directly wired to the clear input of the address generator output registers, and causes an asynchronous jump to trap vector address 000 16 •
In the absence of any trap conditions, the currently executing microinstruction determines which
instruction is to be executed next as shown in the detailed timing diagram, figure 2-33. For
conditional instructions, such as conditional branches or conditional returns, the test bit is used to
select one of the two possible alternative instructions. This information is carried in the branch
control (ROM 17-19) and next ROM address (ROM 23-31) fields of the current microinstruction.
The next ROM address field is routed through the next ROM address multiplexers (in the absence of
a trap) to the address generator inputs. The branch control ROM decodes ROM 17-19, the test bit
and the trap input to determine the address selection code and address carry.
The address generators are clocked on the trailing (positive-going) edge of microprocessor clock. The
SN74S482 devices require a fast-rising edge for proper triggering. This sharp edge is provided by
MPCK482-, which is an isolated and lightly loaded version of microprocessor clock, MPCK-.
MPCK482- is dedicated to the three SN74S482 devices; no other devices are clocked by M PCK482-.
The rising (trailing) edge of MPCK482- clocks the address generators to place a new nine-bit
microinstruction address (MCUADR 1-9) on the microprogram ROM input lines.
2.9.3.1 Trap Operation of Address Logic. Trap operations can be divided into three types for
purposes of description. These types are:
•

TILINE slave traps

•

Microcode interrupt traps

•

Power and I/O reset traps

TILINE Slave Traps. A TILINE slave trap allows the 990 central processor to load a control word
into one of the TILINE slave registers, RO-R 7, or to read a status word from one of these registers.
The TILINE slave registers are scratch pad registers RO-R 7 of the 3002 CPE devices. Reading from a
CPE register, or writing into it, requires at least two CPE instructions.
The TILINE slave traps can be enabled or disabled under microprogram control. Bit 16 of the
microinstruction is the enable slave bit. If it is a logic 0, the slave logic is disabled, and the controller
rejects the attempted operation. Refer to the TILINE slave logic description for the details. In order
to prevent a slave trap from interfering with an on-going operation, bit 16 is not enabled unless the
microprogram is in the idle loop, or is in the process of executing a previously initiated slave trap.
Assume that the controller microprogram is in the idle loop, and the 990 processor initiates a slave
read or write operation. The SL VA and SL VB- signals from the TILINE slave logic combine to
enable the TRAP, TRAP-, and SLVACT signals, as shown in the timing diagram, figure 2-34. The
TRAP signal into the branch control ROM causes the address generator to store the current
instruction address in the stack for later return.
The TRAP- signal to the next ROM address multiplexers takes control of the NRA field away from
the microprogram ROM and gates the slave trap address onto these lines.
TRAP- forces NRAOI to zero and selects SLVACT and INTADO-2 to supply NRA02-0S. SLVACT
is high, disabling the interrupt priority encoder, so INTADO-2 are also high. Thus, the two most
significant (hexadecimal) digits of the trap address are always OF 16.

2-89

Digital Systems Division

~------~

946262-9701

TRAP- steers the NRA multiplexer to select READ-, TLADRI7, 18, 19 to supply NRA 06-09.
TLADRI7-19 are the three least significant TILINE address bits, which select the individual
register. The TILINE read slave trap addresses for RO-R7 are OFO-OF7, respectively. The write slave
trap addresses for RO-R7 are OF8-OFF, respectively.
Microcode Interrupt Traps. The microcode interrupt traps are initiated by error conditions which
require immediate attention at the expense of the on-going operation, if any. Unlike the slave read
and write traps, the interrupt traps cannot be disabled under microprogram control. The interrupt
trap conditions, in order of priority, are:
•

TILINE Abort (TLABORTL-)

•

TILINE Master Device Timeout (MDTOL-)

•

TILINE Error (TLERRL-)

•

FIFO Write Timing Error (WRITIMERR-)

•

Command Timer Delay Expired (CMDTMRDL Y-)

The so-called TILINE abort is a special case which is actually a power failure, power reset or general
I/O reset trap. These conditions affect the controller logic in a way different than the other
microcode interrupt traps, so they are described under the heading "Power and I/O Reset Traps",
following.

Figure 2-35 is a timing diagram for the interrupt trap and return. The trap conditions occur asynchronously, but are synchronized to the trailing edge of MPCK- in an SN74LS174 register. A priority encoder assigns an address (INTADO-2) to the highest priority active interrupt and enables the
TRAP, TRAP- and INITRAP signals.
.
The TRAP- signal forces NRAOI to zero, and steers the next ROM address multiplexer to select
SLVACT (which is zero) and INTADO-2 as the NRA 02-05 inputs to the address generator. The
INTTRAP- signal forces NRA06-09 to all zeros. The resulting trap address assignments are:
TILINE Abort
TILINE Master Device Timeout
TILINE Error
FIFO Write Timing Error
Command Timer Delay Expired
Spares

000
010
020
030
040
050-070

The TRAP signal steers the branch control ROM to a standard trap instruction. The MCUSI-6
outputs of the branch control ROM cause the address generator to store the current output address
in the stack~ and select NRAO 1-09 on the next positive going edge of microprocessor clock.
The instruction that is on the ROMOO-:39 lines when the TRAP- goes active (low) is arbitrarily called
instruction N. In the absence of a trap, the results of instruction N would be stored in the CPE
internal registers on the negative- going edge of microprocessor clock. However, the TRAP signal
suppresses the CPE clock inputs, CPRCK- and CPLCK-.

2-90

Digital Systems Division

~----------------------------~

946262-9701

MICROPROCESSOR
CLOCK

--,

300NS

MPCK- OR
MPCK482-

o

-----.I~~f
I
;+-

f
\

I

-.,

8

(l NS

RESULTS OF N STORED IN
CONTROLLER REGISTERS
(OTHER THAN CPE
INTERNAL) 1. START
ACCESS FuR N+ 1

I
I

1Lt~I
ADDRESS OUTPUT
MCUADR1
THRU
MCUADR9

t '

I I
----A--D-D-R-E-S-S--N----l----~){r------------A-D-D-R-E-S-S--N------------------)(~__________A_D_D_R_E_S__S_N__+_1__________________~

o
I

14

;::::::60NS
MICROINSTRUCTION
ROMOO
THRU
ROM39

NRAOI
THRU
NRA09

ADDRESS SEL.ECT
MCUS1
THRU
MCU S6 t MCUC I

~15NS

o

I
I

~

INSTRUCTION 1<-1
0

o

I

I
~

INSTRUCTION N

i
NRA FIEL.D (ROM23-31) .,.""'....,.~ ...........
NRA FIELD OF INSTRUCTION N
OF INSTRUCTION N-1
I

I

I

I

KEY:

I

I

~30,+--

I

INS I

PERIOD QF INSTABILITY. SUCH
AS R8M SETTING TIME

CODE FOR SEL.ECTING
NEXT INSTRUCTION

N-l • N. N+l

SEQUENCE 'JF M ICROC.JOE IN-'
STRUCTIONS. IN ORDER OF
EXECUTION. NOT NECESSARILY
STORED AT CONSECUTIVE ROM
ADDRESSES

I

~'00NS~~'---120NS~

P-BUS GATE
ENABL.E
PBUSENL.

Q

--------------------~
I
I

I
I

I

I

MINIMUM

SETUP TIM E
I
4Q-70NS
fl41------.l-

CPE LEFT,lRIGHT
BYTE CL.OCK
CPL.CK- ;CPRCK-

o
CPE FUNCTION
CODE FOR INSTRUCTION
N ACCEPTED ON HIGH
LEVEL OF CPE CLOCK

RESULTS OF N STORED
IN CPE INTERNAL
REGISTERS 0 (CLOCK
PULSE MAY BE
SUPPRESSED FOR NONDESTRUCTIVE TESTS)

ALL 3-STATE PROCESSOR BUS
(PBUS) DRIVERS DISABLED
DURING UNSETTLED
PERIOD 0

(A)138264

Figure 2-33. Detailed Timing Diagram of Normal
Microinstruction Access Cycle

2-91/2-92

Digital Systems Division

~

946262-9701

MICROPROCESSOR CLOCK
MPC':K482OR MPCK-

0

ENSLV

0

SLXFR

0

__~---;J

~

SLVA

0

f
r----I---I-----~;J

Sl.VB0

SLVACT

RETURNED TO
INITIAL STATE
BY TILINE GO

0

INTADO-2
0

ALL ONES UNLESS
ACTIVE INTERRUPT

HELD AT ALL ONES BY SLVACT

t ' r - - - I_

TRAP-

----!

0

NRAOI
THRU
NRA09

0

MCUADRI
THRU
MCUADR9

0

INSTRUCTION
N-l

ROMOO
THRU
ROM39

0

MCUSI
THRU
MCUS6

0

C PE CLOCK PU LS E
SUPPRESSED BY
TRAP

0

CPE CL0CK
CPLCK- OR
CPRCR-

o
CPE ACCEPTS
FN CODE
FROM N-l

CPE STORES
RESULTS FROM
N-l

CPE ACCEPTS
FN CODE
FROM N

~-

ASYNCHRONOUS EVENT

- PERIOD OF INSTABILITY.
SUCH AS ROM SETTLING
TIME
(B)138262

Figure 2-34. Detailed Timing Diagram for TILINE Slave Trap

2-93

Digital Systems Division

~------~

946262-9701

Clock inputs to the address generator are not suppressed, so the microprogram jumps to the
interrupt trap address on the positive-going (trailing) edge of microprocessor clock. INTB- goes low
on this same edge, disabling TRAP, TRAP- and INITRAP. Microprocessor clock to the CPE inputs
is enabled, and the address control logic reverts to a non trap mode. The second instruction in the
trap sequence will be selected according to the branch control and NRA fields of the first trap
instruction.
After the initial jump to the first trap address, the remainder of the trap sequence executes like any
other code sequence. The branch control field of the last trap instruction commands a return to the
address stored in the SN74S482 stack register, the address of instruction N. On the next positive. going clock edge, instruction N is read from the microcode ROMs and placed on output lines
ROMOO-39. Instruction N executes normally, and the microprogram advances to instruction N + 1.

NOTE
N-I, N, and N+ 1 refer to the planned instruction sequence in the
interrupted segment of microcode. They are not necessarily located at
sequential addresses.

Power and I/O Reset Traps. The power and I/O reset trap may be initiated by any of three signals
from the 990 backplane to the controller. These signals are: TILINE power failure warning pulse
(TLPFWP-), TILINE power reset (TLPRES-), and TILINE I/O reset (TLIORES-). Each signal affects the controller logic in a slightly different way, but they share a common microcode trap
routine.
The TLPRES is a normally high signal from the 990 chassis power supply that goes low at least 10
microseconds before a normal or fault shutdown of dc power. TLPRES- remains low during a power
failure and is not released until all dc voltages from the power supply are up and stable. TLPRES- is
a protective signal that resets all peripheral device controllers and the 990 CPU. Logic in each
peripheral device controller forces the device control signals to a safe state, so that the peripheral
does not damage itself while the controller and CPU are down. The TLPFWP is a normally high
signal (except in 990/9) from the 990 chassis power supply. The occurrence of this low pulse is a
warning that a power shutdown is in progress, and that a TILINE power reset is imminent. This
early warning signal goes low at least 7 milliseconds before the power reset, allowing the CPU time
to execute a power shutdown routine before the logic reset. The power failure warning pulse remains
active until the power reset (TLPRES-) occurs.
The TLIORES is a control signal from the 990 CPU. TLIORES- goes low to halt and reset all input
output devices and controllers. It is a 100- to 500-nanosecond low pulse generated as the result of the
CPU executing a reset (RSEn instruction. The RSET instruction may be written into a program, or
it may be generated as a result of depressing the RESET button on the programmer panel.
All three of these trap conditions share the same microcode trap sequence, shown in the flowchart of
figure 2-36. Note that these trap routines end in the idle (lDL) routine, and do not return to the
interrupted sequence. The occurrence of any of these traps will abort anyon-going operation and set
the abnormal completion bit in the controller status register (CPE internal register R7). Notice that
the trap routine uses the long diagnostic test check (LTC), Z diagnostic test (ZDT) and terminate
(TRM) sequences as subroutines.
Refer to the simplified logic drawing and to the detailed timing diagram for I/O reset, figure 2-37.
The TLIORES- input occurs asynchronously with respect to microprocessor clock (MPCK-) in the
disk controller. The general reset signals, RST, RSTI, are isolated versions of TLIORES- which

2-94

Digital Systems Division

~----------------------------~

946262-9701

MiCROPROCESSOR CLOCK

1
MPCK- ,
MPCK482-

0

INTERRUPT
CINDITION
0

SYNCHRONIZED
INTERRUPT
CONDITION

Lll

0

INTADO-2

INTERRUPT
CONDITION
CLEARED AS
PART OF
TRAP ROUTINE

0

INTA
0

H -

I .....TB0

PERIOD OF INSTABILITY
SUCH AS ROM OR PRIORITY
ENCODER SETTLING TIME

TRAP-

Ul--=.

0

n"-----I}5

INITRAP
0

NRAOI
THRU
NRA09

0

MCUADR1
THRU
MCUADR9

0

ROMOO
THRU
ROM39

FIRST TRAP
INSTRUCTION

INSTRUCTION N-l
0

~

MCUS1-S6

INSTRUCTIONS N-l ,N ,N+l REFER TO THE PLANNED
SEQUENCE OF INSTRUCTIONS. THEY ARE NOT
NECESSARILY AT SEQUENTIAL ADDRESSES.

INTERRUPT TRAP
ADDRESS

ADDRESS N

60NSEC

LAST TRAP
INSTR ADDRESS

SECOND TRAP
INSTRUCTION

:

ADDRESS N

LAST TRAP
INSTRUCTION

~

INSTRUCTION N

RESTORE ADDR
N FROM STACK

GET INSTRUCTION N

ASYNCHRONOUS EVENT

ADDRESS N+l

~

GET NEXT
INSTRUCTION

1

14

CPE CLOCK
CPLCK- OR
CPRCK-

U/

1

CPE ACCEPTS
FUNCTION CODE
FROM N
(8}138263

__

90NSEC

J /

CPE ACCEPTS
FN CODE
FROM TRAP
SUPPRESSED
BY TRAP
;

~

CPE STORES
RESULTS
FROM TRAP
INSTRUCTION

CPE STORES
RESULTS FROM
LAST TRAP I NSTR
CPE STORES
RESULTS
FROM N

Figure 2-35. Detailed Timing Diagram for Interrupt
Trap and Return

2-95/2-96

Digital Systems Division

946262-9701
Jd1s\ _
_ _ _ _ __
~

unconditionally force the interface contiol logic to a safe state. TLIORES- is latched (as
TLABORTL-) and then synchronized with microprocessor clock as TLABORTQ-. From this point
on, the logic operation is identical to that for any of the microcode interrupts.

The synchronized TLABORTQ- signal into the priority encoder enables the group select output,
INTA, that in turn enables the TRAP- signal. The address outputs of the encoder INTADO-2 go to
000. The TRAP- signal forces NRAO low and steers the NRA multiplexers to select INTAD0-2 as the
source for NRA02-05. INITRAP, which is simply an active high version of TRAP-, puts all zeros on
the NRA06-09lines. The resulting address input to the address generators is 000 (hex), but the jump
is not made until the next II"..icroprocessor clock pulse (trailing edge).
At the time that TLIORES- occurred, the controller was executing some instruction, which is
arbitrarily labeled instruction N-I in the timing diagram. The first clock pulse steps the address
generator to instruction N on the trailing (positive-going) edge. After a brief ROM settling time,
instruction N is on microcode ROM output lines ROMOO-39. However, the active TRAP- signal
disables CPE left and right byte clocks. Therefore, the CPE operations associated with instruction N
are not executed. The function code, ROMOI-07, is loaded into the CPEs, but the leading (negativegoing) edge which would store the results in the CPE registers does not occur. If this were a regular
microcode interrupt, it would be necessary to return to instruction N and execute it when the trap
sequence completed. However, the power and I/O reset traps all end in the idle routine, rather than
with a return to the interrupted sequence.
During the time that TRAP- is selecting an address input to the address generators, TRAP is
determining the address selection code, MCUSI-6, via the branch control ROM. Regardless of any
other inputs to the branch control ROM, the TRAP signal fetches a standard trap code from the
ROM; MCUSI-6 = 101100 and MCUCII = O. This code causes the address generator to put the
current-output address (the address of instruction N) into the push-down return address stack, and
to select the input address (NRAOI-09 = 00(16) as the next output address. These actions are performed on the next positive-going (trailing) edge of microprocessor clock, MPCK482-. (The trap
signal does not disable the general microprocessor clock, MPCK-, or the isolated version,
MPCK482-, which clocks the SN74S482 address generators.)
The clock pulse which forces the jump to trap address 000 also disables TRAP, TRAP-, and
INITRAP via the INTB- output of the interrupt synchronizing register. The active duration of
TRAP- is one clock period, about 300 nanoseconds, between successive trailing edges of
microprocessor clock.

Refer to the I/O and power reset trap flowchart, figure 2-36. The I/O reset has caused a jump to the
first instruction, INTOO, of this trap routine. CPE left and right byte clocks are reenabled so that the
operation shown in the INTOO box is actually performed on the next clock pulse. That clock pulse
advances the address generator to the address specified by the branch control and NRA fields of
microinstruction INTOO. The dotted box may be ignored because a power reset is not involved. The
second instruction of the trap sequence is LTCOI, which is part of the long diagnostic jumper check
(LTC) subroutine. This is a branching control subroutine which tests a jumper to determine whether
the diagnostic test (ZDT) should be performed. Like all the conditional branching microinstructions, LTCOI sets the clock stop bit (ROMOO) and suppresses the next CPE clock pulse, as
shown on the timing diagram.
The remainder of the trap routine executes like any other sequence of microinstructions. The
TLIORES- pulse that initiated the trap is approximately 250 nanoseconds wide. When TLIORES- is
released, the INTA and CLKOFF signals combine to reset the interrupt latch with the INTRESpulse. The CLKOFF signal assures that the interrupt reset does not occur too close to the clock pulse
to meet setup time requirements. The next two clock pulses clear the interrupt logic to its initial
~~.

.

2-97

Digital Systems Division

~------~

946262-9701

W

CLEAR COMMAND REGISTER
SET BUSY F/F

NOT INSTALLED

LTC01
IF9

W
INT01
001

(0000)-R7
t-STBCLR

CLEAR CONTROLLER STATUS
REGISTER AND CLEAR DISK IIF L.INES

ZDTOO
18A

INT02
002

R7L + (01)R7L.
CSTMST

SET ABNORMAL COMPLETION
STATUS BIT STOP CL.OCK (MPCK-)
UNTIL. TIL.INE MASTER CYCL.E

''----r---'"' COMPLETE
L.B
INT03
003

(FF):-R2 L
ZEROS-DBUS

INT04
004

(OOOO)-RO
t -D$KCLR

INT05

(0000)-R4
t -DSKCLR

PUT MAXIMUM SECTORS/RECORD
VAUJE IN R2.

w
CLEAR DISK STA11JS REGISTER
CLEAR DISK L.INES

W

005

CLEAR TIUNE WORD COUNT TO ZERO
CLEAR DISK LINES

TRMOO
04F
NOTE:
CSTMST IS CL.OCK STOP-MASTER
SEQUENCE (SPECIAL. FUNCTION O. ROM39= 1 )
10L.00
027

(B) 138256

Figure 2·36. I/O and Power Reset Flowchart

2-98

Digital Systems Division

~----------------------------~

946262-9701

MICROPROCESSOR
CLOCK
MPCK- OR
MPCK482-

0

TLIORES-

o

RST-

TLABORTQ-

INTA

o

o

o

INTB-

0

5

TRAP0

NRAOl
THRU
NRA09

TLABORT-TRAP
ADDRESS

0

NRA FIELD OF
CURRENT INSTR

NRA FIELD OF
CURRENT INSTR
KEY:

MCUADRl
THRU
MCUADR9

ROMOO
THRU
ROM39

TRAP ADDRESS
000

ADDRESS N
0

INTOO

5

TRAP ADDRESS
lF9

TRAP OPERATION
ENDS AT
IDLE ROUTINE.
DOES NOT RETURN
TO INTERRUPTED
SEQUENCE

~ -ASYNCHRONOUS
TRANSITION
~

_.IiI_i..:w:.
......_

-PERIOD OF INSTABILITY
SUCH AS ROM SETTL I NG
TIME.

LTCOI

0
N-l,N ,N+l -SEQUENCE OF INSTRUCTIONS
IN INTERRUPTED ROUTINE.
NOT NECESSARILY AT
SEQUENTIAL ADDRESSES.

MCUS!
THRU
MCUS6

CPE CLOCK
CPLCK- OR
CPRCK-

o

SELECT NEXT
ADDRESS

SELECT NEXT
ADDRESS

o

u

u

~--~

U

""" SUPPRESSED
DUE TO TRAP-

CONDITIONAL

~~i't'C¥

I

L_~
~ SUPPRESSED AS

PART OF CONDITIONAL
BRANCH IN L Teo 1

(B) 138259

Figure 2-37. Detailed Timing Diagram for TILINE
I/O Reset (TLIORES-) Trap

2-99/2-100

Digital Systems Division

~------~

946262-9701

Refer to the sirnplified logic diagram and the detaiied timing diagrams for the power faiiure warning
trap, figure 2-38. The TLPFWP- input to the controller occurs asynchronously with respect to
microprocessor clock. The power failure warning is latched as TLABORTL-, and synchronized with
MPCK- as TLABORTQ-. Unlike the 110 reset or the power reset, the power failure warning does
not issue a general reset to the controller interface logic. The power failure warning trap is executed
like the other microcode interrupt traps (TILINE master device timeout, TILINE parity error, clear
write, command timer expired), except that it has first priority.

The trailing (positive-going) edge of MPCK- synchronizes the power failure warning as
TLABORTQ-. The Sl'",J"74148 priority encoder develops the interrupt address (INTADO-2 = (00)
and the group select output (lNTA) enables TRAP- and INITRAP. INITRAP and TRAP- cause an
address of 000 16 to appear at the inputs of the address generator. The TRAP- signal to the branch
control ROM fetches a standard trap command, MCUSI - S6 = 101100 and MCUCIl = O. This
code causes the address generator (on the next positive-going MPCK482- edge) to store the current
output address in the internal pushdown stack and to latch the trap address as the new address
output.
The TRAP- signal also disables microprocessor left and right byte clocks, CPLCK- and CPRCK-.
This prevents the microprocessor-related operations of the current microinstruction from being
executed. In the absence of an active TRAP- signal, the active CPEs would have accepted the CPE
function code (ROMOI-07) on the high level of microprocessor clock, and would have executed on
the rising (trailing) edge of the clock. The TRAP- signal suppresses the clock pulse (holds CPRCK-,
CPLCK- high) so the CPEs do not execute instruction N.
Note that TRAP- only disables the clock into the CPE array, not the general microprocessor clock,
MPCK-, or the isolated version which clocks the address generators, MPCK482-. The same clock
pulse which clocks the address generators to jump to the trap address also clears the TRAP- signal
by latching INT A into the synchronizing register as INTB. INTB, after inversion, disables the
TRAP- signal, so that the duration is only one clock period, 300 nanoseconds. If TRAP- were not
released in this manner, the microcode program would remain hung up on the initial trap vector
instruction at address 000 (hex).
After the initial jump, the trap sequence executes like any other sequence of microinstructions. The
trap sequence involves setting safe values into some of the CPE internal registers, and executing an
automatic self-diagnostic routine. At the end of the trap sequence, the controller goes into the idle
routine.

The power failure warning pulse remains active for at least seven milliseconds and is not released
until after the TILINE power reset occurs. TLABORTL- and TLABORTQ- remain active, but have
no effect, since the duration of TRAP- is set by microprocessor clock, not by the duration of the
power failure warning.
The time between the onset of the power failure warning and the power reset, approximately seven
milliseconds, is very large with respect to the time required to execute the trap routine, so the
controller will be idling when the power reset occurs. The right side of the timing diagram shows the
initial operations of the power reset cycle. See the power reset description in the next paragraph.
Refer to the simplified logic drawing and the detailed timing diagram for the TILINE power reset
operation, figure 2-39.
Recall that TLPRES- goes active (low) before a power failure, remains low during the power failure
and remains low until all dc voltages are up and stable. The TLPRES- signal is directly wired to the
clear inputs of the SN74S482 address generators. Therefore, TLPRES-, unlike any other trap

2-101

Digital Systems Division

~------~

946262-9701

condition, can asynchronously disrupt an on-going microinstruction and force an immediate jump to
the trap vector, location 000 16 • All other trap conditions are serviced after synchronization with
microprocessor clock.
The power reset should be preceded by a power failure warning, TLPFWP-, so that when TLPRESoccurs, the controller should be idling and the TLABORTL-, TLABORTQ-, INTA, and INTBsignals should be as shown at the left edge of the timing diagram. If any of them are in alternate
states, as shown by the dotted lines, TLPRES- corrects them asynchronously.
TLPRES- is wired to the direct clear input of the SN74S 164 interrupt synchronizing register. When
TLPRES- occurs, it forces all outputs of the synchronizing register low so INTB- goes high. With all
its inputs forced low, the priority encoder selects the highest priority input (TLABORTQ-) and gates
out an address of 000, and a group select output. The address is not 'meaningful at the moment,
because TLPRES- unconditionally resets the address generators.
TLPRES- forces INT A and INTB- high so that TRAP- and INITRAP remain active until the first
clock pulse after the power reset releases. TRAP- suppresses CPE left and right byte clock so that no
CPE operations are performed for the duration of the power reset.
The microcode program remains hung at address 000 (instruction INTOO) for the duration of the
power reset. The register clear operation shown on the trap flowchart at instruction INTOO is not
executed, because CPE clock is disabled.
When the power reset is finally released, the logic performs a normal trap to location 000. That is, the
TRAP- and INITRAP signals continue to provide an all zeros address on NRAO 1-09, and the trap
select code from the branch control ROM (MCUSI-6) is no longer over-ridden by TLPRES-. The
address generator steps through the rest of the trap operation like any other microcode sequence,
and ends at the idle routine.
2.10 ROM BUS AND MICROINSTRUCTION DECODING
The disk controller operates under the control of a permanent microinstruction program. This
microprogram consists of 512 microinstructions of 40 bits each which are burned into five
SN74S482 devices. The microprogram-controlled operations, with particular emphasis on CPE
operations, are summarized in the flowcharts of Appendix D. A complete listing is provided in
Appendix E.
The outputs of the microprogram read-only memory devices, ROMOO-39, are collectively called the
ROM bus. The ROM bus signals are distributed throughout the disk controller. Decoding of the different microinstruction fields is distributed throughout the controller rather than being centralized
in one giant decoder. Figure 2-9, which shows the microinstruction format, is useful for understanding the decoding scheme.
Figure 2-40 shows the ROM bus and the highlights of microinstruction decoding. Branch control
decoding and next ROM address control are omitted from this figure and included with the
microprogram address control logic.
2.10.1 PROCESSOR BUS SOURCE AND DESTINATION FIELDS. The processor bus source
field (ROM 13-15) determines which data is gated onto the three-state processor bus, PBUSOO-15.
This is the main data transfer bus within the disk controller. The processor bus destination field,
ROM20 and 21, selects one of several registers to accept data from the processor bus.
These two microinstruction fields, along with ROM 33 and a P-Bus enable signal (or CLKTI-, fine
line), are connected to the inputs of the processor bus control register. It is the register outputs
which are actually decoded. The processor bus control register is an SN74S373 transparent D-Iatch

2-102

Digital Systems Division

~ ___9_4_62_6_2_-9_70_1_________________________________________________
register. As long as the enable input (MDACT-) to the register is held high, the register outputs
follow ihe register inputs with no iatching action. This is the transparent mode of operation.
MDACT-, master device active, is high for any controller operation except a TILINE master access
cycle. Therefore, unless a TILINE master read or master write cycle is in progress, PBUSENL is
identically PBUSEN (or CLKTI-, fine line), ROM13L-15L is identically ROM13-15, ROM33L is
identically ROM33, and ROM 20L and 21L are identically ROM20 and ROM21.

Operation during a TILINE master cycle is described below, after the general description of bus
source and destination decoding.
The processor bus source decode is an SN74S138 3:8 decoder/multiplexer. The decoder is enabled
by PBUSENL. PBUSENL is basically a delayed form of microprocessor clock. PBUSENL goes low
immediately after a new microprogram address (MCUADRl-9) is selected and disables bus source
decoding until 100 nanoseconds after the trailing edge of microprocessor clock. This prevents any
device from putting data onto the processor bus until the ROM bus transients have settled, and
ROMOO-39 are stable on the lines. Refer to the detailed timing diagram (figure 2-33) for a normal
microinstruction access cycle and for more information on PBUSENL timing.

With PBUSENL high, ROMI3L-15L are decoded as follows:
ROM13L-15L
000
001
010

OIl
100
101

ItO
III

Decoder Output
Signal
PBZEROPBCPE(none connected)
PBTLDATPBDSKDAT(none connected)
PBDSKSTA(none connected)

Definition
All zeros (high levels) on P-bus
CPE D-bus outputs on P-bus
No P-bus activity
TILINE line receiver outputs on P-bus
Disk data from FIFO (or direct read
register) on P-Bus
No P-bus activity
Disk drive status on P-bus
No P-bus activity

The processor bus destination decoder is an SN74S 139 2:4 decoder. In addition to the destinations
enabled by this decoder, one of the special function encoders enables loading of the TILINE MSB
address register from PBUSII-14. ROM20L, 21L are decoded as follows:
ROM20L,21L

Decoder Output
Signal

00
01

(none connected)
UNITLOAD-

10

UTCSHIN-

II

DSKBUSLD~

Definition

Loads disk unit select code from
PBUS04-07 into the disk select register
Shifts CPE output word into FIFO for
transmission to disk. Not required for
TI LINE to disk transfers
Loads PBUS07-15 into disk address
select register.

ROM33L from the processor bus control register does not perform any function unless a TILINE
master cycle is in progress.

2-103/2-104

Digital Systems Division

~----------------------------"i::(

946262-9701

MICROPROCESSOR
CLOCK
MPCK- OR
MPCK482-

o

III

TLPFWP-

o

TLPRES-

TLPFWP- IS
RELEASED AFTER
TLPRES- OCCURS

o

TLABORTQ-

o

INTA

o

INTB-

o

TRAP-

0

NRAOl
THRU
NRA09

MCUADRl
THRU
MCUADR9

ROMOO
THRU
ROM39

TLABORTTRAP ADDRESS

NRA FIELD OF
CURRENT INSTR

0

TRAP ADDRESS
000

ADDRESS N

0

INSTRUCTION
N-l

INTOO

:

NRA FIELD OF
CURRENT INSTR

IRRELEVANT FOR DURATION
OF TLPRES-

:__________
:
~

TRAP ADDRESS
lF9
TRAP
ROUTINE
ENDS
IN
IDLE
ROUTINE

LTCOl

0

J)(~__ ~
-J

_____F_O_R_C
__
E_D_T_O
__O_O_0
__
'_6______

IDL(N)

~_0_0_0_'_6~:

INTOO

INTOO

:

REFER TO
TLPRESTRAP
TIMING

DISRUPTED INSTRUCTION

MCUS1
THRU
MCUS6
CPE LEFT/RIGHT
BYTE CLOCK.
CPLCK- /CPRCK-

o

u

u

SELECT NEXT
ADDRESS

SELECT NEXT
ADDRESS

SELECT NEXT
ADDRESS

L_J,

U

' " SUPPRESSED
DUE TO TRAP-

5

i
I

L _

I

I

.J

u

IRRELEVANT FOR DURATION
OF TLPRES-

I

L __

i

I

I

I
I
L __ J

.J

SUPPRESSED AS PART OF
CONDITIONAL BRANCH
IN LTCOl

(B)138261

Figure 2-38. Detailed Timing Diagram for TILINE
Power Failure Warning (TLPFWP-) Trap

2-105/2-106

Digital Systems Division

~_9_4_6_26_2_-9_70_J________________________________________________________________________________________________________________________________________
MICROPROCESSOR
CL'JCK
MPCK- OR
MPCK482-

o

u

u

u

u

u

u
f

TLPRES(ISSUES GENERAL RESET. RST, RST 1 )

o

TLABORTL-

RELEASED BY TLINTRST- = (CLKOFF· INTA)TIMING DETERMINED BY PROXIM ITY OF TLPRESTRAILING EDGE TO MPCK-

o

TLABORTQ-

I

o

INTA

~------------------------------,~~- _ _ _ _ _ _ _ J

~-----------------------------,~~-

- - - - --...,
I

0 __________ _

J

iNTB-

o

~----------------~--

---

--

_J

TRAP-

o

NRA01
THRU
NRA09

MCUADR 1
THRU
MCUADR9

(IRRELEVANT FOR DURATION OF TLPRES-)
O _______________~
~~~_~~___________________________________
~

o

____________..Jx,.___Jx

o

____________________

CPE CLOCK
CPLCK- OR
CPRCK-

,6

~~~QUL--r~~~~---------I-N-T-O--O--------~--------IN-T-O-O

________

I
I
MCUS1
THRU
MCUS6

ADDRESS 000

~

:

ROMOO
THRU
ROM09

FORCED TO 000 , 6

~ DISRUPTED

HIGHEST PRIORITY TRAP ADDRESS (000)

ADDRESS 000

~ ~::
__

,6

ADDRESS 000

,6

INTOO

INTOO

ADDRESS 000

ADDRESS 1 F9

m

INTOO

ADDRESS DETERMINED
BY TEST BIT

LTCOI

INSTRUCTION
(IRRELEVANT FOR DURATION OF TLPRES-)

STORE CURRENT ADDRESS. GO TO TRAP

SELECT NEXT
ADDRESS

CONDITIONAL
ADDRESS SEL

o

o

u

I

CPE CLOCK
SUPPRESSED
BY TRAP-

!

L

.....

u

I
L

f

I
.J

SUPPRESSED BY CLKSTP
BIT IN CONDITIONAL
TEST INSTRUCTION L TCO 1

POWER OFF

I
TRAP OPERATION L SIM ILAR TO OTHER
INTERRUPT TRAt"S, NO RETURN TO
INTERRUPTED SEQUENCE

J

(B)138260

Figure2-39. Detailed Timing Diagram for TILINE
Power Reset (TLPRES-) Trap

2-107/2-108

Digital Systems Division

m _____________________________
~

946262-9701

. .... , .........

.....1'- ........ ,._ ........... -

ROMOI-07

CPE FUNCTION CODE

~

ROM36-39
ROM34, 35

'"

SPECIAL FUNCTION 0-3
SPECIAL GROUP SELECT

}

IMMEDIATE OPERAND ,1M)

ROM32. 33

TILINE CONTROL

ROM22-31

NEXT ROM ADDRESS (NRA)

MCUADR3

ROM20,21

PROCESSOR BUS DESTINATION CONTROL

MICROPROGRAM
ROMS

MCUADR6

512 WORDS

ROMOS

RDM17-19

MICROPROGRAM BRANCH CONTROL

ROMI6

TILINE SLAVE ENABLE/DISABLE

ROM13-15

PROCESSOR BUS SOURCE SELECTiON

ROMI2

CPE CARRY CONTROL

09

ROMIO, II

K-BUS SOURCE SELECT
CPE CARRY CONTROL

TROL LOGIC

MCUADRB
MCUADR9(LSB)

ROMOS.09

CPEO WORD SEOLECT (WS)

ROMOO

~
MASTER CYCLE CLOCK STOP

CL.KSTPMST-

MSBADRLODSKSTRRST-

CPE FUNCTION CODE

SPEOCiAL

MSBADRINC-

FUNCTION 0

CLRSECIDX-

DECODEOR
DSKSTRTCK-

CPEO CONDITIONAL. CLOCK

TRIGTMRSH6
RDYDIRRST
MPCK
ROM11-19

"-

TO CPE CARRY AND SHIFT LOGIC, RIGHT SHIFT

GROUPOo-

ROM36-39
RDMOI,07

RIGHT/LEFT BYTE CPE CLOCK SELECTION. CPE
CARRY AND SHIFT LOGIC
TO K-BUS INPUT SELECTION MUX

INPUT (LI) OF CPE ARRAY MSB, CARRY INPUT
OF CPE ARRAY LSB

DSKCL.RCPE K-BUS CONTROL (KC)

TO K-BUS INPUT SELECTION MULTIPLEXER,

ROMI2

ADDRESS CONROMIO, II

TO LEFT, RIGHT BYTE CPE CLOCK GATING

CPE WORD SELECT

BY 40 BITS
MCUADR7

MICROPROGRAM

_..

TO F6-FO INPUTS OF CPE DEVICES

OR INTERFACE CONTROL

MCUADR2

MCUADR5

....

-

MCUADRI

MCUADR4

_

ROM 22-31

STBCLR-

"

CL.EAR DISK I/F

..
..
.."
..
..

LOAD MSB ADDR. REG

TO MICROPROCESSOR CLOCK LOGIC
TO DISK INTERFACE LOGIC
TO TIL.INE MSB ADDRESS REGISTER/COUNTER

DISK START F/F RESEOT

TO DISK INTERFACE

INCREMENT MSB ADDR. REG

TO TlL.INE MS9 ADDRESS REGISTER/COUNTER

CLEAR SECTOR AND INDEX F/F'S

TO SECTOR, INDEX MARK FLIP-FLOPS

DISK I/F START CLOCK
TO DISK INTERFACE
TRIGGER COMMAND TIMER RESET

TO I-BUS INPUT VIA SYNCH FL.lP-FLOPS

CLEAR DISK CONTROL LATCHES

SHI3

I

BRANCH CONTROL. AND NEXT ROM
ADDRESS FIEL.DS

GROUP 01-

!
PBUSENL

~
ROMI3L THRU
ROMISL

FROM

PBUSEN

TIMING
LOGIC

ROMI3-15, 20, 21,33

PROCESSOR
BUS CONTROL

,

--

I
ENABLE ZEROS ONTO P-BUS

PBCPE-

ENABLE CPE OUTPUTS TO P-BUS

PROCESSOR
PBTLDAT-

ENABLE TILINE DATA TO P-BUS

DECODER

PBDSKDAT-

ENABLE DISK DATA TO P-BUS

SHI2

PBDSKSTA-

ENABLE DISK DRIVE STATUS TO P-BUS

BUS SOURCE

ACCESS LOGIC

PROCESSOR

SPECIAL
FUNCTION I

}

UNITL.OAD-

SHI3
CLR

ROM20L,21L

BUS
DESTINATION

UTCSHIN-

SHIFT P-BUS TO FIFO DIRECT REG

DECODC:R
LOAD P-BUS TO SECTOR ADDRESS REG

BUSYQ-

BUSY (NOT IDLE) FLAG

FAULTQ-

HARDWARE FAULT FLAG

DIAGFAULTQ-

DIAGNOSTIC FAUL.T FLAG

}

SPECIAL.
ROM36-39

STBCL.R-I
RSTINTRST-

TILINE SLAVE ENABLE

1 ""\

STBRST-

L
I

FUNCTION 2

ROM32

TIL.INE

33

OPERATION
DECODER
5HI3

ROMIO

-

I
CLKTITRAP-

J1,
L ..r
I

ENSPEC-

DECODER
REGISTER

EG

ERASE GATE
WRITE GATE

RG

READ GATE

MASTER READ

MSTRWT-

MASTER WRITE

HDSEL

HEAD SE _ECT

ADDSTB

ADDRESS STROBE

,.

NOTES:

---./"

SHEET REFERENCES ARE TO

LOGIC DRAWING 937502.

*-

~ ENFLG-

DECODED AS A PULSE STROBED BY MPCK,

DSKWRTQ

SLAVE LOGIC

ROM36-39

t'-.

ROM36
ROM37
ROM38
ROM39

-~
FIFO FLAG

GROUPOO-

GROUP

GROUPOIGROUPIo-

"0"

....
T
IMERRQ

ROM BUS (ROM32-39)

FIFOIN 16-19

TO FIFO BUFFER INPUT

P
SHI7

CRCERR

....

GROUPIISPECIAL GROUP SELECTION

ROM BUS

INVERTING LINE DRIVERS

TO TILINE
MASTER AND

SEL.ECT
SHI3

TO DISK DRIVE VIA

SPAREOUT2

GROUPII-

!

DECODER

-

~

~

SPECIAL.
ROM34, 35

MSTRD-

•

....

WG

~
SLAVE TERMINATE

TO 990 AU
TO TIL.INE SLAVE LOGIC, TL.OATAOO - OUTPUT

~

SHI3
CLR

SL.VTRM-

TO DIRECT REGISTER, FIFO CONTROL

SPAREOUTI

DISK
INTERFACE

CLOCK

ROMI6

990 INTERRUPT FLAG

RESTORE

~

MPCK-

READ DIRECT MODE FLAG

TL.lNTQ

!

LOGIC

DSKBUSLD-

DISK READ/WRITE FLAG

DSKDIRQ

TO SEL.F-TEST DIAGNOSTIC LOGIC, I-BUS
!NPUTS

TO DISK I/F READ/WRITE LOGIC, CRC, FIFO
CONTROL

TO DISK CL.OCK AND DATA I/F, CPE I-BUS

L.OAD DISK UNIT SELECT REG

PROCESSOR

DSKWRTQ

>

TO FAULT L.ED

PROCESSOR BUS
SOURCES

ERROR LOGIC

SHI2

MICRO-

DIAGNOSTIC MODE CLOCK

TO VARIOUS

TO FIFO CONTROL, TILINE

ROM33L

ROM33L

G

MDACT-

DIAGNOSTIC MODE FLAG

TEOSTCL.K-

REGISTER

GROUPIO-

SHI2

MASTER

ROM36-39

TESTMODEQ

DECODER
PBZERo-

REGISTER

FROM TILINE

TO COMMAND TIMER

READY DIREOCT FLAG RESET

IMMEDIATE OPERAND IIM\TO

ROM32-39

K-BUS INPUT MUX

2281595

Figure 2-40. ROM Bus and Microinstruction
Decoding

2-109/2-110

Digital Systems Division

~ _
946262-9701
Jdl)\
_ _ _ _ __

The TILINE master cyclt: is initiated by a microinstruction. if the master cycie was initiated for a
disk-to-memory or a memory-to-disk data transfer, the controller CPEs are not involved in the
transmission. The initiating microinstruction establishes whether it is a master read or master write
operation (ROM32,33) and establishes the data path on the P-bus with the P-bus source and
destination fields (ROMI3-15L, ROM20,2IL). The master device active F / F sets at the beginning of
the master cycle, and MDACT - goes low to latch the processor bus control register. With these
outputs latched, the controller is free to execute other microinstructions independently of the
TILINE master cycle. As long as these microinstructions do not require any P-bus data transfers,
there is no interference between the parallel operations. The controller uses this time for
bookkeeping within the ePE devices, such as updating the TiLINE word count maintained in
register R4.
2.10.2 IMMEDIATE OPERAND/TILINE OPERATION/SPECIAL FUNCTION FIELD.
ROM32-39 is a mUltiple-purpose field of the microinstruction. If the K-bus control (KC) field which
controls CPE mask bus inputs is 10 or II, ROM32-39 serves as an eight-bit immediate operand to
the K-bus inputs of both CPE bytes. The K-bus inputs are active low, so the contents of ROM32-39
are effectively inverted. A typical use for an immediate operand is to AND the left or right byte of a
status word with the eight-bit immediate operand to test an individual status bit. The result of the
test is used to control a conditional branch in the microprogram.
If the KC field is 00 or 01, a constant value (FFFF I6 or 0000 16 ) is loaded into the CPE K-bus inputs,
and TILINE and special function decoders are enabled. These decoders are shown at the right side of
the decoding block diagram.

The enable special fields (ENSPEC-) signal is enabled if ROMIO = 0 (KC field = OX), no trap
operation is in progress, and the CLKTl- signal is high. CLKTl- is used as a hold-off signal to prevent decoding of ROM32-39 before the ROM outputs have settled.
ROM 32 and 33, the TILINE control field, are decoded as follows:

ROM32,33

o0
o1
10
1 1

Decoder Output
Signal
(none connected)
SLVTRMMSTRDMSTWRT-

Definition
NOP
Terminate slave operation

Master read cycle
Master write cycle

ROM 34 and 35 are used as a special function group select field. The code in ROM34,35 determines
whether ROM36-39 are decoded as special function 0, 1,2, or 3. The outputs of the special function
group decoder enable one of the four special function decoders. This is a straight numerical decode
as follows:
ROM 34,35

Decoder Output

o0

GROUPOOGROUPOIGROUPIOGROUPII-

o1
1 0

1 1

Refer to the timing diagram for special function decoding, figure 2-41. The trailing (positive-going)
edge of CLKTI- starts the decoding chain. ENSPEC- goes low after one gate delay, and the
appropriate function group select (GROUPOO- through GROUP1I-) goes active after a short
decoding delay.

2-111

Digital Systems Division

946262-9701
J17)\ _
_ _ _ _ __
~

There are two distinct classes of functions included in special function 0 if it is selected. All of the odd
opcodes are decoded in one decoder which is unclocked. The output signals are asserted as soon as
the decoder delays have expired, about 85 nanoseconds from the trailing edge of MPCK-. This delay
is important because it is the trailing edge of MPCK- that triggers the address generator to select a
new microinstruction. If the special field were decoded before the ROM outputs settle, false decodes
could occur. The trailing edge of CLKT1- may be delayed by addition of capacitor C2, as shown on
sheet four of logic drawing 937502 (PWB) or on drawing 2262102 (fine line), to correct this problem
if it arises. Normally the inherent gate and decoding delays are long enough to prevent the problem.
The even opcodes in the special function 0 field are strobed functions, and the output signals are
developed by a clocked decoder. The inverted form of microprocessor clock, MPCK, serves as a
decoding strobe. If the microinstruction is selected by clock pulse n, the strobed output signal
corresponds to clock pulse n + I, plus about 30 nanoseconds of decoder delay inherent in the
SN74LSI38 device. With the exception of the command timer trigger (TRIGTMR.:.), the strobed
outputs are disk interface control signals. Table 2-13 summarizes the special function 0 decoding.
Special function fields I and 2 control the inputs to a pair of SN74LS259 eight-bit addressable
latches. The addressable latches act as decoders and as registers. The group select signal (GROUPOIor GROUPIO-) enables one of the SN74LS259 devices. ROM36-38 serve as an address to select one
of the addressable latches, and ROM39 serves as the setl reset (D) input to the selected latch. Tables
2-14 and 2-15 summarize the speciai field 1 and 2 decoding.
Special function field 2 is used to assert control signals to the disk drive. This register can be cleared
by a general reset (RST-), an interrupt reset (lNTRST-), or a strobe clear from the special function 0
decoder (STBCLR-). Special function field I is dedicated to controller internal functions, and the
register can be cleared by a general reset (RST-).
The disk interface first-in, first-out (FIFO) buffer has 16 bits dedicated to disk read/write data, and
four bits dedicated to flags. The four flag inputs to the FIFO, FIFOINI6-19, are selected by the
FIFO flag input multiplexer. Special function field 3 allows the active microinstruction to set any of
these four flag bits during a disk write operation.
Unlike the other special function fields, special function field 3 is positionally coded, with each bit
dedicated to a specific flag, as follows:
ROM 36

37

38 39

FIFO
Input Bit

Flag Register
Output

FIFOIN19

(no connection)

Spare flag bit

FIFOIN18

STOPFLAG

Flag that accompanies last
word of a TILINE-to-disk
transfer through the FIFO,
and notifies CPEs that the
write buffer is done.

FIFOIN17

CRCPREFLAG

Preset CRC generator to all
ones.

FIFOIN16

CRCENFLAG

Enable CRC output to disk.

Defmition

The decoding diagram covers only the highlights of decoding and the routing of microinstruction
bits to other circuits within the controller. The functions of these bits are included in the individual
functional block descriptions.

2-112

Digital Systems Division

~----------------------------~

946262-9701

MICROPROCESSOR
CLOCK
. MPCK-.
MPCK482-

f
~'5

~45

NS

NS

~

r--r----------------------------------~~----------~

CLKT1-

o

ENSPEC-

o

GROUP XX

GROUP 00
EVEN
FUNCTIONS
(STROBED
BY MPCK)

GROUP 00
ODD
FUNCTIONS

f

o

KEY:

l!.

o

o

GROUP

llt 1 0

OUT~TS

i-ADJUSTABLE BY
CAPACITOR C2 IN
TI M ING C IRCU ITS
(937502,SH4)

_ _... - J

ACCEPT ADDRESSED INPUT

o

MEMORY
MODE

(B) 138266

Figure 2-41. Detailed Timing Diagram for
Microinstruction Special Function
Decoding

2-113/2-114

Digital System$ Division

~

946262-9701
Tabie 2-i3. Speciai Function U Decoder Outputs

(KC Field)
ROM 10, 11

(Function Group)
ROM 34, 35

ROM 36, 37, 38, 39

0 X

0

0

0

0

0

0 X

0

0

0

0

0

0 X

o0

0

0

0 X

o0

0

0

0 X

o0

0

0

0 X

o0

0

0

0 X

o

0

0

0 X

0 0

0

0 X

0 0

0

0

0 X

0 0

0

0

0 X

0 0

0

0 X

0 0

0

0 X

0 0

0

0 X

0 0

0

0 X

0 0

0 X

o0

0

0

0

0

Signal Output

*Synchronized/
Unsynchronized

(none)

Defmition
No operation.

CLKSTPMST-

U

Microprocessor clock
(MPCK-) stop until
TILINE master cycle
complete.

DSKCLR-

S

Disk clear strobe- clears
FIFO, disk start, and disk
timing error logic.

MSBADRLD-

V

Enable load of four most
significant TILINE
address bits from
PBUSll- 14 into MSB
address register.

DSKSTRRST-

S

Disk start transfer latch
reset (disk stop). Stop
disk transfer. Similar to
DSKCLR- above, but
does not clear the FIFO.

MSBADRINC-

U

Increment TILINE MSB
address register.

CLRSECIDX-

S

Clear sector mark and
index mark detection
latches.

S

Disk start transfer clock.

S

Retrigger (reset)
command timer to
prevent expiration of
190-200 millisecond
delay and consequent
interrupt trap operation.

(none)
0

DSKSTRTCK(none)

0

TRIGTMR-

(none)
0

RDYDIRRST-

Reset ready direct status
latch.

(none)
0

STBCLR-

S

Clear drive control outputs of group 2 decoder/
register.

(none)

Note:
*Synchronized outputs are strobed by next (inverted) microprocessor clock pulse, MPCK. Synchronized outputs are delayed
approximately 150 nsec with respect to unsynchronized outputs.

2-115

~

946262-9701
Table 2-14. Special Function 1 Decoder/Register Outputs

KC Field
ROM 10,11

Function
Group Set.
ROM 34, 35

Latch Selection
ROM 36,37,38

Data
ROM 39

Latch Output

Description

0

X

0

0

0

0

0
1

TESTMODEQ = 0
TESTMODEQ = 1

Disk interface diagnostic mode flag.
ROM 39 = 1 selects the test mode.

0

X

0

0

0

1

0

TESTCLK- = 0

Disk interface diagnostic clock,
TESTCLK-,cycles data into or
out of the 264-stage test data shift
register. Shifting occurs on the
positive-going edge of TESTCLK-.

TESTCLK-

=1

.

~

0

X

0

0

1 0

0

DSKWRTQ=O
DSKWRTQ = 1

Disk interface read/write flag.
ROM 39 = 1 Selects write mode.

0

X

0

0

1

1

0
1

DSKDIRQ -0
DSKDIRQ = 1

Disk read direct mode flag.
ROM 39 = 1 enables a read from the
direct register, bypassing the FIFO.

0

X

0

1 0

0

0

TLINTQ = 0

Controller interrupt "TILINE
interrupt" to the 990 CPU.
ROM 39 = 1 lights the interrupt
LED indicator and enables the
'interrupt to the 990 processor.

TLINTQ = 1

1

0
1

BUSYQ-= 0
BUSYQ- = 1

Controller busy flag. ROM 39 = 0,
lights the BUSY indicator, and causes
the controller to respond to any
attempted slave read operation
with a simulated controller status
word in which the idle/busy bit
indicates that the controller is busy.

1

1 0

0
1

FAULTQ- = 0
FAULTQ- = 1

Controller hardware fault flag.
ROM 39 = 0 lights the FAULT
indicator.

1

1

0

DIAGFAULTQ- = 0
DIAGFAULTQ- = 1

Controller diagnostic fault nag.
ROM 39 = 0 lights the fault
indicator and serves as a CPE
I-bus flag input.

0

X

0

1 0

0

X

0

0

X

0

1

Table 2-15. Special Function 2 (Drive Control) Decoder/Register Outputs
KC Field
ROM 10, 11

Function
Group Sel.
ROM 34, 35

X

0

0

0

0
1

SPAREOUTI = 0
SPAREOUTI = 1

o X

o

001

o

RESTORE
RESTORE

0

Latch Selection
ROM 36,37,38
0

Data
ROM 39

1

2-116

Latch Output

=0
=1

Description
Spare bit which is used to generate an
oscilloscope sync pulse each time
the diagnostic self-test performs
a disk status update. Used for
troubleshooting, in conjunction
with scope delayed sweep.
Restore disk head carriage to
cylinder zero. Also called "return
to zero seek (RTZS)". ROM 39 = 1
initiates the restore operation.

Digital Systems Division

~_
946262-9701
)}lS\
_ _ _ _ __
Table 2-15. Special Function 2 (Drive Control) Decoder/Register Outputs (Continued)

KC Field
ROM 10, 11

Function
Group Set.
ROM 34, 35

Latch Selection
ROM 36,37,38

Data
ROM 39

o X

o

010

0

EG=O
EG = 1

Erase gate. Enables erase current
during a write operation.
ROM 39 = 1 enables the erase gate.

o X

o

o

{"\

llT"" -

Write gate. EnableS write current
during a write operation. ROM 39 =
1 enables the write gate.

v

Latch Output

{"\
nu - v

WG= 1

o X

o

100

0
0

RG=O
RG= 1

Read gate. Enables read data and
read clock out of the drive to the
controller.

o X

o

1 0

1

0
1

SPAREOUT2 = 0
SPAREOUT2 = 1

Spare bit

o

X

o

1 1 0

0
1

HDSEL = 0
HDSEL= 1

Head select. Selects one of the
two read/write heads on a disk drive.
ROM 39 = 1 (HDSEL = 1) selects the
lower (fIxed disk) head. ROM 39 = 0
selects the upper (removable
cartridge) head.

o X

o

1 1 1

o

ADDSTB = 0
ADDSTB = 1

Address strobe (also called cylinder
strobe). Strobes the address on
the ADDOOl- through ADD256outputs into the disk drive cylinder
address register.

1

Note:

Description

*All the drive control outputs are inverted for transmission to the disk drive. Erase gate, write gate, and address strobe are
disabled by a TILINE power reset (TLPRES-).

2.11 COMMAND TIMER
Occasionally, a hard or soft failure will occur in a drive or in a controller, preventing normal completion of an operation. If there is a specific microcode interrupt associated with the condition, such
as the write timing or TILINE parity error, the controller traps to an interrupt routine and the controller can execute retries or notify the 990 AU of a hard failure. The command timer provides a
catch-all microcode interrupt to detect any condition which prevents completion of an operation
within about 190-200 milliseconds. The command timer prevents the controller from hanging up in
some error state without at least notifying the controller microprogram that a problem exists.
Figure 2-42 summarizes command timer operations. An NE555 timer is used as an RC-controlled
digital oscillator, with an output frequency of approximately 320-340 HZ. The oscillator output
clocks an SN7497 binary rate multiplier device, which is used as a-=- 64 counter. While the controller
is cycling in the idle loop, a stream of clear pulses prevents the counter from saturating and
generating a command timer delay signal. Each clear pulse (TRIGTMR-) is decoded from special
function group 0 of a microinstruction.
When the controller leaves the idle loop to perform an operation, the stream of clear pulses stops,
and the SN7497 counts toward saturation. If the operation by design takes more than about 150
milliseconds, a command timer clear will be included in the operation microcode. When the
operation completes, the controller returns to the idle loop, and a stream of clear pulses prevents
expiration of the command timer delay.

2-117

Diaital Svstems Division

FROM
MICROINSTRUCTION
SPECIAL FUNCTION
o CLOCKED DECODER

TRIGTMRCMDTMRCLR
RST-

VCC

15K

DISCHARGE

15K

CMDFRECUCK SN7497

CMDTMRDLYEO D---4.......- - - - - - - - i...

TO INTERRUPT SYNCHRONIZING REGISTER,
FAULT LED INDICATOR

NE555
TRIGGER
THRESHOLD

+64 CIRCUIT
AS T AS LE MU L T I V I S RA TOR

A.

COMMAND TIMER CIRCUIT

NI
~
~

00

~3

MSEC

:=:::2 MSEC

CMDFRECLK(EXPANDED
SCALE)

CMDTMRCLK

I

CMDTMRDLY-

I

14

-J~11.MSEC

CMDTMRCLK

TRIGTMR-

-=::::;192 M I LLI SECONDS
(3 MSEC X 64)

I
~------~

.,

:

tI

S~-----~
I

NOTE:

B.

TIMES ARE NOT TO SCAL.E.

COMMAND TIMER EXPANDED WAVEFORMS

~

COMMAND TIMER INTERRUPT PROCESSED, ENDING IN IDLE LOOP

C.

COMMAND TIMER EXPIRATION

(A)138269

Figure 2-42. Command Timer

~ ___9_46_2_6_2-_9_70_1_____________________________________________________________
Assume that a fault condition hangs up the operaiion. APPloxiulately 190-200 nanoseconds after the
last command timer reset, the counter reaches saturation and CMDTMRDLY - goes active (low),
CMDTMRDLY- shuts off the clock input (CMDTMRCLK), to latch up the counter output in the
active state. CMTMRDLY- is connected to the input of the interrupt synchronizing latch, and
initiates a command timer delay microcode trap. Refer to the instruction access logic for a detailed
description of microcode interrupt traps. CMDTMRDLY also lights the FAULT light-emitting
diode indicator.
The interrupt trap routine executes, and ends in the idle routine. The idle routine sends command
timer reset puises to the counter. The first TRIGTfvtRS- pulse clears the C~ADTMRDLY- signal,
and subsequent pulses retrigger the counter as previously described.

A general reset, initiated by either TLIORES- or TLPRES-, will also clear the command timer.
2.12 DISK INTERFACE
The disk interface logic performs those functions which are directly involved in transmitting data to
a disk drive for recording and retrieving data previously recorded on a disk drive. These functions
include:
•

Selecting the disk drive logical unit for the operation

•

Controliing the selected disk drive unit

•

Addressing a specific recording area (cylinder, head) on the disk

•

Processing and transferring disk unit status and rotational position (sector address, sector
mark) information

•

Formatting, buffering, and transferring read and write data to and from the disk unit

•

Error checking of data and header information read from the disk unit.

Disk interface operations are initiated and controlled by the 512-word ROM microcode program.
The group select (ROM34, 35) and special function fields (ROM36-39) of the 4O-bit microinstruction are primarily used for disk interface control. The 16-bit CPE array under microinstruction control performs such functions as reading the disk status word from the processor bus,
monitoring other status bits on the I-bus, supplying the disk logical unit selection code via the processor bus, and supplying the cylinder address selection code via the processor bus. The CPE array is
not in the data path for read or write operations. The write data path goes from the 990 main
memory, over the TILINE, the processor bus, through a first-in, first-out (FIFO) buffer and
parallel/serial converter in the disk interface, and out to the selected drive. One TILINE master read
cycle is required to transfer each 16-bit word from the 990 memory to the disk interface. Each
TILINE master cycle is initiated under microinstruction control, and the TILINE address is supplied by the TILINE MSB address register and the address (A) bus outputs of the CPE array.
The read data path goes from the selected disk unit through a serial/ parallel converter and FIFO in
the disk interface, over the processor bus and into the 990 main memory over the TILINE. A
TILINE master write cycle is required to transfer each 16-bit word from the disk interface to the 990
main memory. Again, the master cycle is initiated under microinstruction control, and each TILINE
address is supplied by the MSB address register and the CPE address outputs.
Three different clock rates are involved in this transfer. The TILINE interface operates at an
asynchronous, variable word rate which is partly determined by activity on the bus. The
microinstruction ROM, CPE array and associated processing operate at the microprocessor clock

2-119

Digital Systems Division

~_
946262-9701
j}t1s\
_ _ _ _ __

rate set by MPCK-. This clock may be stopped and restarted in order to communicate over the
TILINE. The disk interface operates at a disk read or write clock rate. For disk write operations, this
clock is developed by an oscillator in the disk interface, and multiplexed into the data stream written
on the disk. For read operations, this clock is recovered and separated by the disk drive electronics
and supplied to the disk interface. Any variation in disk rotational speed varies the read clock rate.
The 16-word FIFO averages out short-term differences between disk and TILINE data rates.
Excessive delay in the TILINE interface, beyond the 16-word capacity of the FIFO, will cause a
FIFO timing error (rate error) microcode interrupt during write operations. For read operations,
bad status will be reported at the end of the operation. The TILINE interface, however, cannot
outrun the disk interface because each TILINE word is transferred by a separate TILINE master
cycle operation. The microcode program initiates the master cycle only when the disk interface is
ready.
Formatted read and formatted write operations are the most commonly performed disk operations.
For a formatted track, each record has a sector identification header which must be read and verified
before the data is read or written. The data flow path for the verify sector header operation goes from
the disk, through the serial to parallel converter, and into the direct read register (rather than the
FIFO). The direct read register contents are transferred over the processor bus (P-bus) to the CPE
M-bus inputs. The actual values read from the disk header are compared to expected header values.
If these values compare, the read or write operation proceeds, using the data paths previously
described.

The write format operation writes the sector headers on a disk, and prefills all the sectors on a given
track with the same data word. Two data paths through the disk I/F are used during the course of a
write format operation. A write format command is sent to the DS10 controller in the form of eight
successive slave write operations, as described in Section 1. The parameters supplied to the controller include a TILINE address, a record word count, number of sectors per record, and the
header parameters for all the records on the specified track. At the start of the write format operation, the CPEs request the data word which is stored at the TILINE address supplied by W5 and
W6. The data word is read from 990 memory, gated onto the processor bus, and temporarily stored
in the direct read register. At a later point in the sequence, this word is transferred over the processor
bus and into a CPE internal register. This TILINE-processor bus-direct read register-CPE data path
is exercised only once, at the beginning of the write format operation. Each time a new record comes
under the read/write head, the CPE transmits three sector header words via the processor bus,
FIFO, parallel/serial converter and serial data path to the disk. The CRC generator appends a 16-bit
cyclic redundancy check character to the header data transmission. After the gap time has expired,
the CPE starts filling the data area of the sector with repeated copies of the one specified word,
which is stored in the CPE. When the record word count expires, a CRC character is written. The
operation repeats at each sector mark which corresponds to the beginning of a record until the entire
track is formatted.
Figure 2-43 is a detailed functional block diagram of the disk interface logic. Some portions of the
block diagram, such as disk selection and status monitoring, are very straightforward. These sections
of logic perform simple functions and operate in only one manner. Other logic, such as the
serial/ parallel shift register and FI FO buffer are shared between read and write operations with

differing signal flow for these operations. The multiple possible data routes in these logic areas
make the block diagram representation more complex. The simplified data flow diagrams, figures
2-5 through 2-8, are helpful in keeping track of the data flow.
2.12.1 DISK INTERFACE LOGIC. Each section of logic shown on the disk interface block
diagram is described in subsequent paragraphs.

2-120

Digital Systems Division

~----------------------------~

946262-9701

FROM CPE o-BUS

PBUSOo- THRU PBUS15

PROCESSOR BUS

PBUSOO - THRU PBUSI5-

PROCESSOR BUS

PBUSOo-THRU PBUS 15

-

TO CPE loll-BUS

PROCESSOR BUS

IN PUTS T!LINE

OUTPUTS, TILINE

LI NE DRIVERS

LINE RECEIVERS

ROTATIONAL POSITION
PULSES FROM
SELECTED UNIT

INDMRK-

{

INDEX MARK (NOT USED)
TO CPE

SECMRKADDACK

.

sE.l;:TOR MARK

I-BUS
LATCHES

CYLINDER ADDRESS ACKNOWLEDGE

I-BUS
INPUTS
DISK CONTROLLER

SH16

(DISK START_CJ~cKl ~-

{

START/STOP CONTROL FROM MICROINSTRUCTION
SPECIAL GROUP 00
DECODER

..lDlSK

!iF

CLEAR~

--"'

START

DSKCLR-

CONTROL
TO OTHER
FI FOOUTI6-:-"
D~SK :/F
FUNC-

-"NO
DISK CONTROLLER

{

"...

RDYSRW-

DISK STATUS

OFFLINE-

INSTRUCTION

NOTRDV-

SPECIAL GROUP 01
DECODER

WP-

LOCA TION FROM
SELECTED UNIT

F/F

(SEEK IN<"nuPI_ETE ERROR)

LINE

FIFO
INPUT MIXES

....

PBUSOo-THRU PBUSI5-

RECEIVERS

....

SWBIN-

WRITE FLAGS

READ FLAGS

08-

:-

02-

-

~
READ DATA-

SH 16

,

PARDATOo-15

RCLK-

CLOCK AND DATA
FROM SELECTED UNIT

{

READ CLOCK

....

DCLK1READ

151
QA

>

r r r rrrrrrr rr

0

F/FS
SH 19

-

N

1

FIFOOUT1Q

TERRUPT

Q

0

LOGIC
DCRCERRQ--

CONTROL

RDYSTATUS- TO CPE I-BUS
SH 13 .1S,

ISHIFTIN

CK

16,18
FIFOINI6-19

"

SHIFTIN
SHIFTOUT

~

~

-

16-WORD

;>CPE I-BUS

INRDY
OUTRDY
FIFOOUT16-19

~

BUFFER
SH -17

-..

F'FOOUT19

,....

FIFO

FIFOiNOO-iS

-

Q

FIFOOUTOo-lS

~

"0"--'

"FIFO
DATA

SHIFT REGISTER

DATA

....

PARALLEL FORM
PARDATOo-lS

V

(READ DATA VIA FIFO' PBUSOo-THRU PBU51S-

.....

FIFO OUT/ZERO MUX

0
SYNCH

SERIAL/PARALLEL

BUFFER

1'10- READ DATA

r-

PBUSOo-I5

--"'

I
I

:FLAGS

TIMERRQ

DIRECT REG

-

ERROR SET

I

,FIFO

04-

SECTORBOI-

SEPARATED READ

lrV1

SHIFT

FIFO,

TO CRC
GENERATOR

CRCPRES-

SWAIN-

{

SPARE

CRC ERROR

DRIVES A AND B

CURRENT SECTOR

CPEI-BUS

TO IN-

STATUS

CABLE ADAPTERS ON

STOPFLAG

f------4

SH 14

(WRITE PROTECT)

DISK

{

FLAG
REGISTER

~

_(WRITE CHECKl

SKIC

UNIT NUMBER JUMPER
POSITIONS FROM

FL-AGMUX

TIONS

CONTROL

(DISK DIRECT) DSKDIRQ-

TO FIFO

.,,-

DISK
WRITE

~

WCHK-

FIXED/REMOVABLE

READ/WRITE

(DISK WRrrJ;l DSKWRT-

{

MODE FROM MICROFILERDY-

GENERATOR

CONTROLLER

-

(DISK START REsE;Il

TOCRC

CRCENFLAG-

DISK

~

READ

CHARACTER

'--

PARDAT09-15

SH17

TO READ/
SYNC6E

(6E)

"Hn -tnnn u

~~~~~OL ~

DETECTOR

DIRECT
(DIRECT READ DATA) PBUSOO-THRU PBUSI5REGISTER
SH 15
DISK UNIT

(WRITE DATA - PARALLEL. FORM~

PBUS04-07

SELECTA-

SELECT

SELECTB-

REGISTER
AND DRIVERS

DISKS.EL-

}

LOGICAL
UNIT 0-3
SELECTION

SPAREOUTQ1NOTE:

SH 14

ALL SHEET REFERENCES ARE TO
LOGIC DRAWING 937502
SERIAL
PARDATOO

(WRITE

...J!!BIQATD

SMHZ WRITE

DISK

WRITE TIMING TO OTHER

CLOCK

DATA)

ADD256- ..lMSB.l

OSCILLATOR

ADDRESS

064-

SH 19
PBUS07-15

WCLK

L--.t

GENERATION
AND

DISK WRiTE DATAJ

DOUBLE FREQUENCY (2.5-5.0 MHZ)

SH 14

WRITE DATA AND CLOCK TO SELECTED
DISK UNIT

CRCERR

TO FIFO
FLAG MUX

ADooOlADDRESS STROBE

~

i\ND DRIVER

DISK CYLINDER
;> ADDRESS

-

002WDNCL~

-...

DISK
CONTROL DECODER/REGI- RESTORE-

SH 19

DISKDATIN ....

004-

DRIVERS

OUTPUT

LOGIC

(SERIAL READ DATA)

~

DISK DATA

FORMATTER

CHECKING

DISKDATIN

~

016008-

AND CLOCK

CRC

SH19

032-

REGISTER
AND

WRITE
DATA
MUX,

~
~

128-

DISK I/F FUNCTIONS

FROM
MICROINSTRlICTIONS
ROM

ROM 36-:><>

STER

RG-

CYLINDER ADD-

READ GATE

WG- WRITE GATE
EG-

ERASE GATE

)

READ/WRITE,
STRADDLE ERASE
CONTROL
UPPER/LOWER

HDSEL2281580

RESS RETURN
TO ZERO SEEK

HEAD SELECTION

SH 13

Figure 2-43. Disk Interface Block Diagram

2-121/2-122

Digital Systems Division

~_
946262-9701
J}]~
_ _ _ _ __

Table 2-16 lists ali tnt: signais inierchanged between the disk controiier and the disk drive unit(s).
These are the signals which the disk interface logic must either control or monitor during disk
operations. A brief description of each signal is included in the table. The reader should be familiar
with the contents of the table before continuing with this description. Appendix F contains detailed
pin assignments for the controller-disk drive I/O connectors, P3 and P4.

2.12.1.1 Disk Unit Select, Disk (Cylinder) Address and Disk Control Decoder Registers. The controller to disk drive output signals, except the write data and clock (WDNCLK-) signal, are isolated
in figure 2-44. The disk unit select register and disk address register are shown on sheet 14 of logic
drawing 937502 (PWB) or 2262102 (fine line), and ihe disk control decoder/register is shown on
sheet 13.
Disk unit selection is a necessary prerequisite for any operation which involves the drives. A disk unit
must be selected before it can accept any data or control inputs (except the select inputs). It must also
be selected before it can supply data or status outputs to the disk controller.
Table 2-16. Disk IfF and Disk Drive Interface Signals
Signal Name in Controller

Description

Controller to Disk Signals:

(Active in the low voltage state unless otherwise specified.)

ADDOOl-

Cylinder address. Valid when cylinder address strobe, ADDSTB, is
high. A read or write operation need not load a new cylinder address
unless the heads must seek to a new track.

AD DOO2ADDOO4-

ADD256ADDSTB-

Cylinder address strobe. Loads cylinder address into disk drive
electronics when low. For read or write seeks, ADDSTB remains
active until Address Acknowledge (ADDAK-) is issued. For
Restore-, strobe remains active for at least one microsecond.

SELECTA-

Select disk drive A. When low, selects the dual disk drive which is
designated "A". The select line must be active (low) to allow the drive
unit to accept data or any other control signals, and to generate any
control status signals except seek error and unit ready. This line selects
a drive which contains two independent logical units. The select line
and disk select signal are both required to uniquely specify logical unit
o or I.

SELECTB-

Select dial disk drive B. When low, selects the disk drive which is
designated "B". The select line and the disk select signal are both
required to uniquely specify logical unit 2 or 3. See SELECT A-,
above.

DISKSEL-

Disk select. Selects one of the two platters within a disk drive. When
low, DISKSEL- selects the fixed disk, when high selects the
removable disk. The controller must check the position of the fixed/
removable logical unit reversing jumper (SW AIN- or SWBIN-) before
setting the polarity of DISKSEL-.

2-123

Dioital Svstems Division

~ ___9_4_6_2_62_-9_7_0_1__________________________________________________
Table 2-16. Disk IfF and Disk Drive Interface Signals (Continued)
Signal Name in Controller

Description

HDSEL-

Head Select. Selects the read/write head on the upper
(HDSEL- low) or the lower surface (HQSEL- high) of the
fixed or removable disk platter. H DSEL- is stable for at
microseconds before the leading edge of a write gate, and
stable for the duration of a read or write operation.

RG-

Read gate. Enables read data and clock through the disk drive
electronics to the controller. Leading edge of read gate enables phaselock circuitry in disk drive electronics clock/ data separator.

WG-

Write gate. Enables write current during a write operation.

EG-

Erase gate. Enables erase current during a write operation, so the
erase heads can "shear" flux splatter at the outer track edges (straddle
erase).

WDNCLK-

Double-frequency encoded write data and clock to the disk unit.
Minimum pulse width is 100 nanoseconds, with a rise/fall time less
than 50 nanoseconds.

RESTORE-

Restore to Track Zero, also known as Return to Zero Seek (RTZS-).
Causes the head carriage to advance to the forward limit of travel and
then return to the home (track 000) position. Also clears disk cylinder
address registers and counters, and clears disk unit fault latches.
Essentially a master clear to the selected disk drive. Cylinder Address
Strobe (ADDSTB-) must be low for the disk to accept the
RESTORE command.

surface
selected
least 10
remains

Disk to Controller Signals:
ADDAK-

Address Acknowledge. Acknowledges acceptance and validity of
cylinder address loaded into the disk drive electronics. Addresses
greater than 407 are considered invalid.

FILERDY-

Disk File Ready. Active (low) if the disk cartridge is installed, disk
spindle is up to speed, heads are loaded, dc voltages are within
tolerance, unit selected, no fault latches set, terminator and terminator
power present. Inverted within the disk controller as OFFLINE-.

RDYSRW-

Ready to start Read/Write (also called "on cylinder"). Indicates that
the head carriage has reached the specified cylinder address, and the
heads are stable. Also incorporates all file ready conditions. Inverted
within the disk controller as NOTRDY-.

SKIC-

Seek Incomplete (also called seek error, SKER). Indicates that the
disk drive failed to properly seek to the desired cylinder address. This
condition may be cleared by a Restore operation.

2-124

Digital Systems Division

~ ____94_6_2_62_-9_7_0_1_________________________________________________
Table 2-16. D!sk IfF and Disk Drive Interface Signals (Continued)
Signal Name in Controller

Description

INDMRK-

Index Mark. A reference pulse which occurs once every disk revolution
when sector 0 rotates under the R/ W heads. The controller has the
logic to monitor INDMRK-, but the controller microprogram makes
no use of it. The controller depends instead upon the sector address
supplied by the selected disk unit. Generated separately for the fixed
and removabie disks.

SECMRK-

Sector Mark. A rotational position pulse (50 microseconds) which
identifies the start of each disk sector. The leading edge is used as the
timing reference for starting read or write operations. Generated
separately for the fixed and removable disks.

SECTORBOI-

Sector Address. The disk drive electronics has a sector counter which
uses the index and sector marks to keep track of the current rotational
position of the selected disk. The disk controller compares this current
sector address to the desired sector address to determine whether the
desired sector is under the read/write heads. The sector address is
updated at the end of a sector, about four microseconds before the
next sector mark. It is stable when the sector mark occurs, and remains
stable until four micros:econds before the next sector mark.

SECTORB02SECTOR B04SECTORB08SECTORBI6SECTORB32·
RD-

Read Data. A clock/ data separator in the disk drive electronics uses
phase-lock techniques to separate the double-frequency recorded clock
and data stream into separate clock and data outputs to the controller.
Nominal pulse width is 100 nanoseconds, with variations allowable
from 50-ISO nanoseconds. Leading edge is the reference.

RCLK-

Read Clock. Clock recovered from disk which is used as basic disk 1/ F
clock for read operations. Recovered from recorded double-frequency
clock data stream by phase lock techniques. Nominal pulse width is
100 nanoseconds, with allowable variations from 50-ISO nanoseconds.
Leading (falling) edge is the timing reference.

WP-

Write Protect. Indicates that data may not be written onto the
the selected disk because the associated WRITE PROTECT switch on
the disk drive control panel is on.

WCHK-

Write Check (also called Fault). Indicates that the disk drive electronics has detected a fault condition and inhibited the write and erase
currents. Fault conditions which may be cleared by a restore signal, if
temporary, include:
I.
2.
3.
4.

More than one head selected
Read and write gates simultaneously active Oow)
Read and erase gates simultaneously active Oow)
Erase gate active without write gate for more than
20 microseconds.

?-12~

DiaitRi

~V!l:tAm.c:

niv;.c:inn

~~-----------------~

946262-9701

Table 2-16. Disk I/F and Disk Drive Interface Signals (Continued)
Description

Signal Name in Controller

5. Write or erase gate on when not on cylinder (RDYSR W- high)
6. Low dc voltages in disk drive
7. Emergency retract condition, such as motor under speed.
Cable Adapter to Controller:
SWAIN-

Position of fixed/ removable disk logical unit number reversing jumper
for 1st dual disk drive (disk drive A). SWAIN- high means that the
reversing jumper is not installed, so that the removable disk cartridge is
logical unit I and the fixed disk is logical unit O. This is the normal
situation. SWAIN- low means that the reversing jumper is installed,
so that the removable disk is changed to logical unit 0 and the fixed
disk is changed to logical unit 1.

SWBIN-

Position of fixed/removable disk logical unit number reversing jumper
for the second dual disk drive (disk drive B). SWBIN- high means
that the reversing jumper is not installed, so that the removable
disk cartridge is logical unit 3 and the fixed disk is logical unit 2. This
is the normal situation. SWBIN- low means that the reversing jumper
is installed on the cable adapter, so that the removable disk is changed
to logical unit 2 and the fixed disk is changed to logical unit 3.
The disk controller senses the state of SWAIN- or SWBIN- before
setting the DISKSEL- output level. The controller microprogram
forces the DISKSEL- polarity to the correct level to select the disk
specified in the logical unit select field of control word R6.
The reversing jumpers are physically located on the cable adapter
board .

. A DSIO disk drive has two disk platters (one fixed, one removable cartridge). These disk platters are
treated by the disk controller as though they were two entirely distinct disk units, each with its own
logical unit number. This is true even though both platters share basically the same set of
read/write/control electronics, and rotate on the same spindle. A single read/write head carriage
assembly moves the four read / write / erase heads to the proper disk cylinder. One conseq uence of this
is that independent, overlapped seek operations may not be performed on DSIO drives. With two
DSIO disk drives daisy-chained to one controller, there are four distinct logical unit numbers
available for selection. It would be confusing to assign numbers to drives and to logical units, so this
manual will refer to the first disk drive on the daisy chain as drive A. Drive A contains logical units 0
and I. The second disk drive, if any, is called drive B, and contains logical units 2 and 3. The standard configuration (in the absence of optional reversing jumpers) is:
Drive A
Fixed disk -

Drive B

logical unit 0

Removable disk -

logical unit

Fixed disk -

logical unit 2

Removable disk -

logical U uit 3

The reversing jumpers are mounted on printed circuit board cable adapters mated to the drive
input/ output connectors. The controller senses the jumper positions to determine the appropriate

2-126

Digital Systems Division

~------~

·946262-9701

CQ

CK

AOOI28-

TO
DISK
ORIVES

AOO064-

PBUStt

OISK
(CYLINDER)
ADORESS
REGISTER

PSUSt 2

~V

AOO032-

V

AOOOI6-

V- AOOO08V-

PBUS13

AOOO04-

paUSI4

AOOO02-

PBUSIS

AOOOOI-

ROM BUS
FROM MICROPROGRAM
ROM

t"--.

ROM36

SPAREOUTI

r--.....

ROM37

RESTORE

AOORESS

ROM38

SPAREOUTl-

V-

EG

TLPRE~-

U

ROM39
OATA

FROM SPECIAL
GROUP SELECT
DECODER

GROUPIO-

INPUT
STROBE

T
STSCLR-

:-=0\1 SPECI AI..
=-~,C7ICS

:;=01..:;>00

,

S·· '. C ","'0 "lOU S

::::::OOER

INTRST-

RG

..,L-/

ST8RST-

V

AOOSTB-

I

'"

NOTES:
1.

DISK CONTROL DECODER REGISTER IS AN 8-BIT
AODRESSABLE LATCH.
UNITL..OAC'- ANO 0ISK8USLO- ARE SYSCHRONIZEC
WITH MICROPROCESSOR CL..OCK

DISK8USLO-

O~

SPAREOUT2HOSEL-

TLPRES-

I'

MPCK-

U:-l17L..DAOOR

V

HOSEL
AOOSTB

~

WG-

RG-

SPAREOUT2

CLR

RST-

EG-

I

WG

DISK
CONTROL
OECOOER
REGtSTER

RESTORE-

~VE
EDGE

3.

STROBE CI..EAR. STBCLR-.
WITH MPCK-.

IS AL..:iiO

SYNCHRO~;:

ZEO

Ftgure 2-44. Disk Unit Select, Disk (Cylinder) Address Select, and Disk Control
DecoderIRegister Logic

2-127

Digital Systems Division

~------~

946262-9701

disk unit selection code. This code is placed on the processor bus by the left byte CPEs and strobed
into the disk unit select register by UNITLOAD-. UNITLOAD-, which is a pulse synchronized to
microprocessor clock, is decoded from the P-bus destination field (ROM20,21) of the active
microinstruction.
Open-collector driver/inverters transmit the selection code to the disk drive(s). SELECTA-, when
low, selects the first disk drive, and SELECTB-, when low, selects the second disk drive. DISKSELis the signal which determines whether the fixed disk platter or the removable disk cartridge is
selected. DISKSEL- low selects the fixed disk platter, and DISKSEL- high selects the removable
disk cartridge. Table 2-17 summarizes the logical unit selection outputs of the disk controller.
Upper / lower head selection is described with the disk control decoder/register outputs.

Table 2-17. Logical Unit Selection
Without Reversing Jumpers

With Both Reversing Jumpers

ControUer Unit Select
Code Input (positional Code)
(R6, bits 4-7)

SELECfA-

SELECfB-

DlSKSEL-

0

1 0 0 0

L

H

H

1

0 1 0 0

L

H

L

2

0 0 1 0

H

L

H

Fixed

3

0 0 0 1

H

L

L

Cartridge

Logical Unit

ControUer Select Code Outputs

ControUer Select Code Outputs
Platter Type

SELECfA-

SELECfB-

DlSKSEL-

Fixed

L

H

L

Cartridge

Cartridge

L

H

H

Fixed

H

L

L

Cartridge

H

L

H

Fixed

Platter Type

The contents of the disk address register determine the physical position of the head carriage. The
head carriage is at cylinder 0 of both platters when it is at the read/write track farthest from the
spindle. The carriage is at cylinder 407 when it is closest to the spindle (farthest into the disk). The
head carriage servo uses a current position register to compare with the specified address to control
the direction and rate of head carriage movement. The operation is called seeking or track seeking.
The cylinder address is supplied to the controller in one of the eight initial control/parameter words.
As part of the read or write sequence, the CPEs supply the cylinder address over the processor bus,
and DISKBUSLD- strobes the address into the nine-bit disk address register. The DISKBUSLD
pulse is decoded from the processor bus destination select field (ROM20,21) of the microinstruction
and synchronized with MPCK-. The nine-bit cylinder address is transmitted to the disk drive as
ADDOO1-, ADDOO2-, ADD004-, through ADD256-. This address is actually loaded into the disk
drive electronics by an address strobe developed by the disk control decoder/register.
The disk unit select register and the disk address register both accept CPE output data from the processor bus. The disk control register/decoder is an eight-bit addressable latch which is controlled by
special group 2 of the controller microinstructions. Each control signal output is set up by a separate
microinstruction. ROM36-38 addresses one of the eight internal latches, and ROM39 either sets or
resets the specified latch, as described with the microinstruction format. The input strobe,
GROUIP10-, is supplied by ROM34,35 through the special group select decoder. All eight register
stages are simultaneously cleared by an STBRST- (strobe reset) signal. The strobe reset may be part
of a general controller reset, an interrupt reset, or a specific strobe clear (STBCLR-) command from
a controller microinstruction. The strobe reset allows rapid clearing of the drive control signals to
inactive states. For example, if a TILINE power reset (TLPRES-) occurs, it is undesirable to leave
erase current and write current enabled. TLPRES- directly disables the output drivers, and the
general reset clears out the latch contents.

2-128

Digital Systems Division

~------~

946262-9701

Outputs of the disk control decoder/register drivers arc: SPAREOUTI-, RESTORE-, EG-, WG-,
RG-, SPAREOUT2-, HDSEL- and ADDSTB-. ADDSTB-, the cylinder address strobe, enables the
disk drive to accept a new cylinder address from the ADDOOI- through ADD256-lines. HDSEL-,
the head select signal selects either the upper (HDSEL- low) or the lower (HDSEL- high) surface of
the disk. RG-, the read gate, allows the disk drive electronics to synchronize the phase-locked
clock/ data separator to the read data and clock data stream read from the disk.
The read gate is enabled in advance of the actual data read operation, to allow synchronization of the
phase-locked clock-data separator. The write gate and erase gate (WG- and EG-) are both enabled
during a write operation. The write gate allows write current to flow, so that data may be written on
the disk. The write gate is actually enabled during the gap before a record. All zeros (clock without
data) are written into the gap. On read, the clock pulses recorded in the gap are used to synchronize
the clock/ data separator circuits. The erase gate allows current to flow in the straddle erase circuits.
Straddle erase head gaps follow the write head gap and shear the flux splatter on both track edges.
The RESTORE- signal initiates a disk drive return to zero seek (RTZS) operation. This operation
moves the head carriage to the fully extended position, return it to the track 0 position, and performs
a general reset of the disk drive address control and fault detection logic.
2.12.1.2 Disk Status Inputs to Processor Bus and I-bus. Figure 2-45 is a block diagram which shows
the disk status inputs to the controller disk interface logic. All disk status signals are sampled by the
CPEs. There are two basic paths for the disk status signals to reach the CPEs: the CPE I-bus or the
processor bus.

The I-bus is a group of 16 individual signals which are connected to the I-bus inputs of the 16-bit
CPE array. Each of these signals comes from a single source and has a single destination. Many of
the I-bus lines are used to monitor internal progress of disk controller operations. For example, a
special stop flag is written into the FIFO after the last word in a disk write buffer. The controller
microprogram monitors this flag bit at the FIFO output (STOPFLAG) to determine if the disk write
buffer is complete. Typically, this monitoring is done with a single microinstruction which activates
the left byte or the right byte CPEs, stops CPE clock, and forces the CPEs to AND eight-I-bus input
lines with an 8-bit immediate operand on the K-bus. The result of the AND operation steers a
conditional branch. The branch or nonbranch is determined by the masked I-bus input signal. The
single-byte limitation on I-bus monitoring is due to the availability of only eight bits of mask
information in the microinstruction immediate operand field.
The disk rotational position pulses, sector mark and index mark, are connected to I-bus inputs, as
are the disk address acknowledge signal and two spare signals. The disk controller microprogram
does not make use of the index mark, but the monitoring capability is available. Sector and index
marks are generated when a sector slot or index slot rotates past a fixed transducer in the disk drive.
The fixed disk slot transducer is hard mounted to the spindle. The disk cartridge contains slots in a
sector rim built into the cartridge. An index mark identifies the beginning of sector 0, and a sector
mark identifies the beginning of each sector.
Referring to the diagram, the sector and index mark flip-flops are cleared by the clear sector I index
pulse (CLRSECIDX-) pulse decoded from special group 0 of the microinstruction. When a sector
slot on the selected platter comes under the transducer, the low SECMRK- pulse sets the sector F / F.
The F / F output, SECTORMRK-, is synchronized with microprocessor clock in the I-bus latches,
and SECTORMARQ- at the CPE I-bus input goes active (low). The controller microprogram clears
the sector and index F / Fs after masking the left byte I-bus inputs with 80 16 to test for the sector
mark. Note that the CPE devices use a logic convention of I = 0 volts and 0 = +2.8 volts, so any low
input is interpreted as a data 1, and any high input is interpreted as a data O.
Figure 2-46 shows typical microprogram flow chart segments for I -bus bit testing. The functions
monitored by the left byte CPEs are: sector mark, ready status, disk start, direct register ready,

2-129

Digital Systems Division

946262-9701
Jd7)\ _
_ _ _ _ _~

address acknowledge, diagnostic fault and test mode. To test for the presence of one of these bits,
the left byte CPEs are commanded to AND the I-bus inputs bit-by-bit with an 8-bit immediate
operand from the microinstruction. The CPE clock is stopped, so that no CPE internal register contents are modified. The left byte carry output is used as a test bit to determine if the result of the
AND operation is zero (CO =0) or nonzero (CO = 1).
The carry output is latched in the test bit F / F. The test bit controls a conditional branch, causing the
microprogram to continue to look for the status bit or to advance to a new segment. The figure
shows the immediate operands (in hexadecimal form) which are used as selection masks for each of
the I-bus input signals. These immediate operands are supplied by ROM32-39, the 1M field, to the
K-bus inputs of the CPE array. The polarity of the I -bus input signal determines which output of the
decision block represents "condition detected." Notice that the entire bit test operation is complete
within one microinstruction, and does not require access to the processor bus.
In addition to monitoring selected disk status bits on the I-bus, the microprogram can gate a 16-bit
disk status word over the processor bus to the CPE M-bus inputs. The bus source field of the
microinstruction (ROMI3-15 = 110) enables the status line receiver outputs onto the processor bus.
The first II bits of the disk status word are individual, independent signals which may be masked and
tested as shown in figure 2-47. The bit testing operation is very similar to the I-bus testing described
in the preceding paragraphs. The last 5 bits of the disk status word form the current sector address.
This sector address becomes valid approximately four microseconds before the sector mark, and
remains valid until approximately four microseconds before the next sector mark. If the .disk
controller is commanded to perform a read or write operation starting at sector 6, it starts sampling
the I-bus for the sector mark. At each sector mark, the controller checks the disk status word looking
for a sector address of 6. When the addresses compare, the read or write sequence proceeds to
completion.
SW AIN- and SWBIN- identify the presence or absence of the fixed/ reversible disk logical unit
reversing jumpers. SW AIN- is pulled high (on the controller) unless a grounding jumper is installed
between J I (gnd) and J3 of the cable adapter at drive A.

2.12.1.3 Disk IfF Start and Read/Write Control Logic. Figure 2-48 is a simplified version of the
disk I/F start and R/W control logic (drawing 937502, PWB or 2262102, fine line). This logic
initiates read or write transfer operations when commanded by the special function field of the controller microinstruction.
A write or read data transfer is specified by the DSKWRTQ (disk write latched) output of the special
group 1 decoder/register. The state of the DSKWRTQ signal is set up before the transfer is initiated,
and, since it is latched, remains at that state until specifically changed by a microinstruction.
DSKWRTQ is high to specify a write data transfer. DSKWRTQ high places a constant
(STRTREAD-) on the read F / F and a constant preset on the sync character detection F / F.
DSK WRTQ high partially enables the input to the write F / F.
DSKWRTQ is low for a read data transfer, and disables the WRITEQD input to the write F / F,
while allowing the sync F / F and read F / F to operate normally.
Remember that a write data operation (R6. bits 5-7 = 011) involves reading the sector header before
writing the data. Therefore, the state of DSK WRTQ will be low while the sector header is verified,
and will switch high during the write header gap.
The microprogram commands the disk interface logic to start with a DSKSTRTCK- (disk start
transfer clock) pulse decoded from special group 0 of the microinstruction. The DSKSTR TCKpulse is synchronized with the microprocessor clock pulse, MPCK-. The trailing (rising) edge of

2-130

Digital Systems Division

~ __9_~_U_2_-_97_0_1__________________________________________________________________________________________________________________________________
SECTOR t-/t-

Q

"1"- D

SECMRK-

r

n

CK
CLR
CLRSECIDX-

Y

ADDACK-

FROM FI FO AND
DIRECT REGISTER
CONTROL

ADDACK

-V

INDEX F/F

","-

FROM
SELECTE
DISK UNI ~<

Q f--

0

'v'r .... '"

1
SECTORMRK~

FROM FIFO
INPUT MUX

..

SECMRK

MICROPROCESSOR
CLOCK

FROM 01 SK CONTROLLER START
AND READ/WRITE
CONTROL

..

..

INDMRK

.....

FROM MICROINSTRUCTION
SPECIAL GROUP 0 DECODER
SPAREIN2SPAREIN1-

V"~

RDYDIRSTATQ-

RDYDlRSTAT

...

AODACK
REAOQ-

--....

....

SECTORMRKQ-

I-BUS
LATCHES

RDYSTATUSQ-"
FROM DISK CONTROLLER
START AND R/W
CONTROL

-...

SH16

ADOACQ

READQQ-

INOEXMRKQ-

OFFLINE-

FILERDY-

NOTRDY-

'VwpWCHKSPAREIN6-

SPAREIN3FROM
SELECTE
DISK UNI

SPAREIN5-

~

SWBINSWAINSPAREIN4-

SPAREOUTQl

SPAREIN2

SPAREINl

SPAREINl

SPAREINl

.
.

r,
I .... ) - -

PBUSOO-

L ' .... J

PBUS01-

-1

~

r

PBUS02-""
..-

PBUS03-

-""
..-

.

PBUS04-

.

PBUS05-

...

PBUS06-

~

...
.....

3-STATE
DISK
STATUS
LINE
... RECEIVERS

~

......
......

SECTORB 16- --.

PBUS07PBUS08PBUS09PBUS10-

SH16

PBUS1'-

r

PBUS12-

SECTORB08- --.

{

PBUS13-

SECTORB02- ..

PBUSI4-

...

PBUS15-

-

SECTORB01- --.

....

ENBL
FROM MICROINSTRUCTION BUS
SOURCE FIELD
DECODER

PBDSKSTA-

f

-

-

BYTE

............

............

..........

FIFOOUT18
FIFOOUT19

"

"""

"""

"

"

CPE
I-BUS

...........
...........

"""
"""
"""
"""

I
ALL ONES ALL ZEROS O,B
IMMEDIATE OPERAND (1M)
FROM ROM32-39

...........

...........

LEFT BYTE

-

-

-

A

K

CPE
ARRAY

-

RIGHT BYTE

""'"

...

...........

M

D

...........

..-

SECTORB04- ~

LEFT BYTE

- RIGHT
-

"

OCRCERRQ-

FROM CRC ERROR F IF
SPAREIN2

..-

SKIC-

STOPFLAG

FROM 01 SK WRI TE FLAG
REGISTER
FROM DISK UNIT SELECT
REGISTER

Y

............

TESTMODEQ

SPAREIN2

..-

RDYSRW-V"_

{

"

01 AGF AU L TQ- ............

INDEXMRKQ- "

FROM FIFO FLAG
OUTPUTS

"

RDYDIRSTATQ~

READQQFROM M ICROINSTRUCTION SPECIAL
GROUP 1 DECODER.!
REGISTER

"
"

DSTARTQ-

AODACQ

CK
CLR

CLRSECIDX-

SECTORMRKQ-

RDYSTATUSQ-

RDYSTATUS:

INOEXMRKINOMRK-

CK

i

i

CPLCK-

CPRCK-

•

""'"
...........

PBUSOO-THRU PBUS15-

""'"

NOTE:
CLRSEClDX (CLEAR SECTOR/INDEX)IS SYNCHRONIZE o
WITH MPCK- AS SHOWN BELOW.

"""

MPCKPROCESSOR BUS

PROCESSOR BUS

I __C

EDGE WHICH
FETCHES
INSTRUCTION

Lr

CLRSECIDX-

2282583

Figure 2-45. Disk Status Inputs to I-Bus and
Processor Bus

2-131/2-132

Digital Systems Division

LEFT BYTE
FUNCTION

5S02

IL /\ (XX)

CLKSTP

CLKSTP

SIGNAL NAME

MASK

SECTOR MARK

SECTORMRKQ-

XX",80

READY STAWS

RDYSTATUSQ-

40

DISK START

DSTARTQ-

20

READY DIRECT

RDYDIRSTATQ-

10

ADDRESS
ACKNOWLEDGE

ADDAKQ

08

READQQ-

04

READ

CO FOR
CONDITION PRESENT
YES

16
16
16
16

YES
YES
YES
NO

16
YES
16

CONDI TION
DETECTED
A.

DIAGNOSTIC FAULT

DIAGFAULTQ-

02

TEST MODE

TESTMODEQ

01

YES
16
NO
1 Ei

CONDITION
DETECTED

B.

ACTIVE LOW
INPUT SIGNAL
(XYXY-), LEFT BYTE

ACTIVE HIGH INPUT SIGNAL
(XYXY), LEFT BYTE

RIGHT BYTE
FUNCTION

t;-J
"""""
w
w

I

/\ (XX)

R

MASK

INDEX MARK

INDEXMRKQ-

STOP FLAG

STOPFLAG

40

SPAREOUTQl

SPAREOUTQl

20

DELAYED CRC
ERROR

DCRCERRQ-

10

/\ (XX)

I

R

SIGNAL NAME

CO FOR
CONDITION PRESENT
YES

XX=80
16

NO
lei

CLKSTP

CLKSTP

NO
16

SPARE IN 2

SPAREIN2

08

SPARE IN 1

SPAREINI

04

FIFO 18 OUT

FIFOOUTI 8

02

FIFO OUT 19

FIFOOUT19

01

NO
16

C.

CONDITION
DETECTED

ACTIVE LOW INPUT SIGNAL
(XYXY-), RIGHT BYTE

D.
NOTES:

ACTIVE HIGH INPUT SIGNAL
(XYXY), RIGHT BYTE

/\

=

LOGICAL AND

(XX)

•

HEXADECIMAL CONSTANT

CO

•

TEST BIT F/F OUTPUT, SUPPLIED BY CARRY OUTPUT OR RIGHT
SHIFT OUTPUT FROM CPE ARRAY.
FOR NON-ARITHMETIC OPERATIONS,
THE CARRY OUTPUT IS OFTEN USED TO INDICATE THAT THE 8-BIT OR
1 6-BIT RESULT OF A LOGICAL OPERATION IS NON-ZERO.

CLKSTP= CPE CLOCK STOP (ROMOO).
INHIBITING THE CLOCK ALLOWS THE CPE'S
TO PERFORM NON-DESTRUCTIVE TESTS ON DATA VALUES.
2282593

Figure 2-46. Bit Testing -

I-Bus

NO

16>
NO
16>
NO
16>

CONDITION
DETECTED

YES

16

NOTES:
STATUS -AC

L

AC

=

L

= LEFT BYTE (SL'BSCRIPT)
=
•

R

A
A(XX)

AC
L

CLKSTP

DISK STATUS WORD,
SIGNAL NAME

CLKSTP

= CPE
CLOCK STOPINHIBITS CPE CLOCK
INPUT SO NO REGISTER
CONTENTS ARE CHANGED.
DOES NOT AFFECT MAl N
MICROPROCESSOR CLOCK.

DISK OFF LINE

OFFLINE-

NOT READY

NOTRDY-

XX=80

16

40

WRITE PROTECT

WP-

20

WCHK-

10

SPAREIN6-

08

SKIC-

04
16

SPARE

SPAREIN5-

02
01

16
, 6

CARRY OUTPUT USED IN
NON-ARITHMETIC OPERATIONS TO TEST ZERO
OR NON-ZERO CONTENTS
OF A REGISTER.

RIGHT BYTE

SIGNAL NAME

MASK

SWBIN-

REVERSING
JUMPER A
INSTALLED

SWAIN-

YES
YES

SPARE

SPAREIN4-

20

YES

SECTOR ADDRESS 24
3
SECTOR ADDRESS 2

SECTORBI6-

10

SECTORB08-

08

SECTOR ADDRESS 22

SECTORB04-

SECTOR ADDRESS 2'

SECTORB02-

SECTOR ADDRESS 2 0

SECTORB01-

YES

16

FUNCTION

t

REVERSING
JUMPER B
INSTALLED

YES

16

SPARE

SPAREIN3-

YES

16

SEEK INCOMPLETE
SPARE

DISK STATUS WORD

CO FOR CON01 TION PRESENT

16

WRITE CHECK

•

CONDITION
DETECTED

LEFT BYTE
MASK

LOGICAL aIT-BY-BIT AND

= -8
HEXADECIMAL CONSTANT
BITS

CO

FlJNCTION

RIGHT BYTE (SUBSCRIPT)

(XX)

CLKSTP

CONDITION
DETECTED

CPE ACCU MU LA TOR

YES
YES

2282594

Figure 2-47. Bit Testing -

Disk Status Word

XX=80
16
40
16

16
16
16
04
16
02
16
01
16

CO FOR CONDITION PRESENT
YES

YES

YES
YES
YES
YES
YES
YES

~------------------------------~

946262-9701

WRITEQO

I
I
I

OPERATIONS
SYNCHRONIZED TO

II

OPERATIONS

•

I
I

MICROPROCESSOR
CLOCK

SYNCHRONIZED TO
DISK READ OR
WRITE CLOCK

(WRITE)READ)

FROM MICROINSTRUCTION

I

DSKWRTQ
WRITEQD

1

DSTARTQ

SP£CIAL GROUP1

I

DCLK-

DECODER/REGISTER

I

Q

0

'--""

WRITEQ

WRITEF/F

WORD I

1

CK

WRITEQO

TO DATA/
CRC MUX

WRITEQ-

WRITEQ-

WRITEQ

f----+

-

DISKDATLO-

CNTEQ~

!

:l:SKSTRQ

DSKSTRO

I-.......WORDS 2-N

TO FIFO TIMING
ERROR F/F

l

TO DISK WRITE FLAG REGISTER,
SERIAL/PARALLEL REGISTER
LOAD (WRITE OPERATION)

DISKDATLD

TO FIFO OUTPUT CONTROL
(WRITE OPERATION)

DISK START
TRANSFER F/F

Q

··1··-0

DSKSTRQ

TOCPE

DSTARTQ

Q

D

I-BUS
INPUT

DISK51lI'.RT

I

F/F
DCLK-

DSKSTRTCK- (DISK START XFER CLOCK)
MICROINSTRUCTION
SPECIAL GROUPO
DECODER (SYNCHRONIZED WITH MPCK
PULSE)
GENERAL

DSKCLR- (DISK CLEAR)

<

&i~~1~~1FER RESET)
AND

INTERRUPT RESETS

READ CLOCK FROM
RE.I\D DATA BUFFER.
WRITE CLOCK FROM

CK

CK

{

RSTINTRST-

.J

~DSKSTRTR-

V
OJ

I

DSKSTRO

J

WRITEO-~
CLRCNTRREAOQ-

~
H
~~

DCLK- (DISK READ OR WRITE CLOCK)

WRITE F/F
SYNC F/F
(

READ F/F
OAI--R/W 16-BIT COUNTER

QBI---DSTARTO- _

(

F"ROM MICROINSTRUCTION

DSKWRTO
RST-

WRITE CLOCK

SPECIAL GROUPI

OSCILLATOR

DECODE RiREGISTER

:J

DCLKCK

STRTREAD-

""'"

Qcl--QDr--

./

CNTEQIS-

00

GENERAL

TO FIFO INPUT CON-

TROL (READ OPERATION)

RESET
READ/WRITE IS-BIT
COUNTER (0-15)

NOTES:

,.,~v.",~c{

REGISTER

··0··

~ARDATIO

( DCLK-

PARPATII
PARDATI2PAROATt3

PARDATI4

~

~

SVNC6E-

J

Q

BUFFER

TOCRC

oJ DATA

MPCK-

SYNCQ

0

Q

Q'----j
READ

J

6E,oOI 10111 0
I

OCLK-

CK

a
If

U

DSKSTRTCLK-

F/F
(

(LSB) DISKDATIN-

u~u

MUX

CK SYNC
F/F
K

DSKSTRTCLK-, DSKCLR-, DSKSTRRST
ARE SYNCHRONIZED WITH MPCK- PULS

SVNCO-

PARDATIS
READ DATA

I.

P

PARDAT09-

READO-

TO I-BUS
INPUT LATCH

2.

DCLK- 15 EITHER READ CLOCK RECOV ERED
FROM DISK. WRITE CLOCK GENERATE DIN
CONTROLLER. OR TEST CLOCK DECODED
FROM MICROINSTRUCTION.

(C) 138641

Figure 2-48. Simplified Disk II F Start and Readl
Write Control Logic

2-135/2-136

Digital Systems Division

~------~

946262-9701

DSKSTRTCK- clocks the disk start transfer F / F, which supplies DSKSTRQ. DSKSTRQ releases
the constant reset on the write F / F and supplies the D input to the disk start F / F. Nothing happens
until the first disk clock pulse, DCLK-.
DCLK- is read from the disk (for read operations) or supplied by the controller's on-board write
clock oscillator, depending on the state of DSK WRTQ.
The first DCLK- pulse sets the disk start F/F, resynchronizing operations to disk clock. The disk
start F/F output, DSTARTQ, notifies the CPEs via the I-bus that the commanded operation has
sta.~ed and pa.~ia1ly enables the read, sync and write F IF inputs.
For a write transfer, the previously enabled DSK WRTQ and the DST ARTQ signal load the first
write data word from the FIFO into the parallel/ serial shift register (DISKDA TLD-). The write F / F
sets on the second disk clock pulse. The WRITEQ output removes the constant clear (CLRCNTR-)
from the read / write 16-bit counter and allows it to tally disk clock pulses starting with the third one.
Each disk clock pulse corresponds to one bit shifted out at the parallel/ serial shift register and
transmitted to the selected disk unit. When the counter saturates (CNTEQ15 goes high), it is time to
load another 16-bit from the FIFO into the parallel/serial shift register (DISKDATLD-).
For a read transfer, the low DSKWRTQ signal and DSTARTQ allow the sync character to start
monitoring for the 01101110 (6E I6 ) pattern which precedes either the header or the data. The sync
detector gate monitors the parallel outputs of the serial/parallel shift register until it recognizes a
6E 16 pattern. The SYNC6E- signal clears the sync pulse F/F on the next disk clock pulse, indication
that a sync pattern has occurred.
The Sync F/F outputs, SYNCQ- and SYNCQ, enable the CRC generator/checker to start
monitoring downstream data and set the read F / F on the next disk clock pulse. READQ- notifies
the I-bus of the controller operation and enables the read/write counter to monitor the number of
received bits. The CNTEQ15- signal loads the FIFO input when a 16-bit word is available on the
parallel outputs of the serial/ parallel converter.
The disk operation may be terminated by a disk start transfer reset (DSKSTRRST-) or a disk clear
(DSKCLR-) microinstruction, by a general reset, or by an interrupt reset. Any of these inputs forces
DSKSTRTR- low, which unconditionally forces the logic to a reset state.
2.12.1.4 First In, First Out (FIFO) Buffer. A FIFO buffer is a special memory device which is commonly used to transfer data between devices with differing clock rates. If a FIFO is initially empty,
the first word entered into the FIFO falls through to the output where it is available for unloading.
If words are unloaded at a slower instantaneous rate than they are loaded, the data words stack up
in the order of entry. FIFOs are sometimes referred to as silo memories because of the similarity to
the operation of a top-loading hay feeder. The cows at the bottom get the hay in the order that it was
pitched into the silo, and the rate at which the cows consume the hay is unrelated to the rate the hay
is pitched in as long as the silo is neither depleted nor overfilled.
FIFOs can be loaded and unloaded at asynchronous rates and can adjust for short-term differences
in the input and output data rates as long as the FIFO capacity is not exceeded.
The disk controller uses an array ofSN74S255 five-bit by 16-word FIFO devices to form a composite
20-bit by 16-word FIFO. Sixteen of the bits in a FIFO word are used for data, and the other four bits
are used for flags. The FIFOs adjust for the difference in data rates between the disk interface and
the TILINE interface or the microprocessor clock cycle.
Figure 2-49 is a simplified block diagram for an SN74S255 device. For any operation requiring a
FIFO, DISKDIRECT- is inactive (high), qualifying the SHIFTIN input. The low to high transition

2-137

Digital Systems Division

~~-----------------~

946262-9701

SHIFTOUT-

J"L

SHIFTIN

V

A

DlSKDIRECT-

""

B

..)

-

I

>

ORDY

CKIN
(UNLOAD
CLOCK)

IRDY

CONTROL LOGIC
DSKCLR-

...

-"

"

,, ,, ,,

~

,

--..

FIFO I N (B+ 1 )
FIFOIN (B+2)
FIFOIN(B+3)
FIFOIN(B+4)

....

....
..

..

~

>CLR

~,

FIFOIN(B)

....

..

, .. , ,,

, ,r " ..

....

..,
..

..

..

16

FIFOOUT(B)
FIFOOUT(B+1 )

RIPPLE
DIRECTION
LAST
WORD
ENTERED

....

~

•

FIRST
WORD
ENTERED

5 BIT X 16-WORD FALL-THROUGH
MEMORY ARRAY

FIFOOUT(B+2)
' FIFOOUT(B+3)
FI FOOU T(B+4)

(A) 138634

Figure 2-49. SN74S2SS FIFO Device Internal Block Diagram

of SHIFTIN loads the five FIFOIN (B) bits into the first stage of the FIFO. The five bits are rippled
through the FIFO (by internal clock pulses) to the end of the output queue. The input ready (lRDY)
signal goes low for 42-65 nanoseconds as each data word is loaded into the buffer, but it returns high
unless the FIFO is filled to its 16-word capacity.
The output ready (ORDY) signal is high when data is available for output. ORDY is delayed
approximately 215 nanoseconds from the first shift in signal while the data word shifts through the
intermediate stages to the output. The output ready signal indicates that valid data is available at the
FIFO output. After accepting the data word, the external circuitry unloads the word from the FIFO
with a SHIFTOUT- signal. The positive-going (trailing) edge of SHIFTOUT moves the next word in
line to the FIFO output stage. The ORDY output is held low for the duration of the SHIFTOUT
signal, but returns high unless the entire FIFO has been unloaded.
The clear input (DSKCLR-) clears the
the output ready (ORDY) low. The
locations in the FIFO, but the output
loaded into the FIFO and shifted to

control logic on the negative-going (leading) edge, and forces
clear does not actually clear out all the internal memory
ready remains low, indicating invalid data, until new data is
the output stage.

,
Figure 2-50 shows timing relationships for an SN74S255 FIFO device. Part A of the figure shows the
simplest possible case, fully loading the FIFO and then unloading it, with no overlapping of input
and output operations. This case is shown only to show the differences between input and output
operations.
Part B of the diagram shows the conditions which actually occur within the controller. In this
example, load and unload operations are both going on at differing rates. The ORDY and IRDY
outputs are used externally to prevent conflicts between input and output operations. Arbitrary

2-138

Digital Systems Division

~

946262-9701

A.

LOADING . - -

NON-OVERLAPPED TIM ING (FOR REFERENCE ONLY):

I
I

I

---+

UNLOADING

I

CONSTANT HIGH ENABLE FOR FIFO LOADING

DISKDIRECT---------------------------------------------------------~5 j~------------------------------------------------------------------------~1 ~f----------------------------~5

SHIFTIN

___I

#1

________+ #2

~------------~5 ~

!

I.....

I

I

IRDY

U~--------------~~L
NSEC

'0IIII
I
ORDY

DATA OUT

SHIFTOUT-

..
-,

~42NSEC

~------------------------------------------------------------~j~1----------------------------~r

hi

SA WR.ATEO BUFFER
-16 WORDS ENTERED

..

5 ~S--__~I________________________________~I----------------------------------~fS

FIRST SHIFTIN
TO ORDY

rl--------------------------------~5 ~j----------------------~

I

FIRST WORD

S

--------------------------------------------------------~$

t

LOAD FIRST WORD

,

J

1
J'
}

.'

SECOND WORD \

t

LOAD SIXTEENTH WORD

I

I

t
UNLOAD FIRST WORD

'i

1
~ ~

t

t

LOAD SECOND WORD

r---------------~f~S--------------.

1,

s

~

l
B.

~

~215

,

#16

t

THIRD WORD

)5

SIXTEENTH

5

WORD

~J

UNLOAD SECOND WORD

l

UNLOAD
SIXTEENTH
WORD

OVERLAPPED TIMING (PRACTICAL-EXAMPLE):

DISKDIRECT

SHIFTIN

IRDY

+
U

-tlf I+- ~42
ORDY

DATA OUT

WORD Y

,

NSEC

\
I

t
(B) 138635

,

LOAD WORD X

-..-__r

I

WORD Y+l

-'1

)
SHIFTOUT-

u
I

. WORD Y+2

NOTE:

X-V

~

15

1

\~

+
t

f

UNLOAD WORD Y

tt

""'"-_....t
LOAD WORD X+ 1

UNLOAD WORD Y+l

Figure 2-50. SN74S255 FIFO Basic Timing

2-139/2-140

Digital Systems Division

~~-----------------~

946262-9701

numhers X and Yare used to represent the input and output data words, respectively. The 133rd
word in the data sector might be X, and Y might be the 126th word of the data sector. The important
parameters are that X is greater than or equal to Y, because it is not possible to unload a word before
loading it, and that the difference (X-Y) must be less than or equal to 15, or the 16-word storage
capacity of the FIFO is exceeded.
Figure 2-51 is a detailed block diagram which shows the FIFO array and the related input, output,
and control logic. The FIFO array consists of four SN74S225 devices with common control inputs.
The input ready outputs of the four devices, IRDYA-IRDYD, are combined to produce a summary
INRDY - signal for the FIFO array. Similarly, the output ready signals, ORDY A-IRDYD are
combined to produce the summary output ready, ORDY-.

It is important to note that the disk controller must adapt to the data rate of the disk, and not the
other way around. On disk read operations, for example, the data rate from the disk is determined by
the rotational speed of ~ physical platter. This speed may vary somewhat due to mechanical
imperfections, but inertia prevents any effective data rate control on a bit-to-bit or word-to-word
basis. Therefore, on disk read operations, the disk loads the FIFO at a rate independent of the
controller and the operating microprogram. The controller must adapt to that rate by reading and
unloading the FIFO fast enough to prevent the FIFO from being saturated.
On disk write operations, the data rate from the FIFO output to the disk is fixed by a crystalcontrolled oscillator. Therefore, the rate of FIFO unloading is fixed (within the drift limits of the
oscillator) and the controller must adapt to that data rate by loading the FIFO fast enough to
prevent being "outrun" by the disk.
The summary INRDY- and OUTRDY- signals playa key role in adapting the controller data rate to
the disk and detecting any FIFO errors which do occur.
During a disk read operation, the controller must unload the FIFO and initiate TILINE master write
cycles fast enough to prevent the FIFO from overloading but without attempting to read when no
data is ready. The OUTRDY - signal is steered through a multiplexer and supplied to the ePE I-bus
input as RDYST A TUS-. RDYST A TUS- low informs the controller microprogram that the data is
available so it can initiate a TILINE master cycle. The SHIFTOUT- signal is issued by the TILINE
master logic upon completion of each single-word TI LINE data transfer.
The FIFO capacity is exceeded if a SHIFTIN is issued while INRDY - is high, indicating a full buffer.
These signals, steered through the multiplexer as ERRORSET and SHIFT, control the FIFO timing
error flip-flop.
During a disk write data operation, the controller must load the FIFO fast enough to keep up with
the disk. The summary INRDY - signal is steered through the multiplexers as RDYST A TUS-.
RDYST A TUS- low informs the controller microprogram that space is available in the FIFO. The
controller microprogram responds by initiating a TILINE master read cycle to obtain a data word.
The TILINE master logic shifts the word into the FIFO upon completion of the cycle. For this case,
a FIFO timing error would consist of a SHIFTOUT command from the disk interface with no FIFO
output word available (OUTRDY - high). OUTRDY - and SHIFTOUT are selected by the
multiplexers to control the FIFO timing error F / F.

NOTE
For a FIFO timing error detected during a disk write operation,
TIMERRQ generates a vectored interrupt to the controller
microprogram. The interrupt is not generated if the FIFO timing

2-141

Digital Systems Division

~------~

946262-9701

error occurs during a disk read operation. Instead the TIMERRQ
signal is routed to the bit 18 input of the FI FO flag mUltiplexer. The
timing error flag is appended to the next data word shifted into the
FIFO, as FIFOINI8.
The corresponding output bit, FIFOOUTI8, is monitored by the
CPE I-bus. Therefore, when that data word reaches the FIFO output,
the controller microprogram is notified that a FIFO timing error
occurred on the previous data word.
The data inputs to the FIFO, FIFOINOO-15, are supplied by a group of FIFO input multiplexers.
The disk I/F read/write signal, DSKWRTQ, selects either processor bus data (DSKWRTQ = 1) or
parallel read-back data (DSKWRTQ =0). Notice that the 16 data inputs to the FIFO are also connected to the inputs of the direct read register. The same SHIFTIN signal which loads a data word
into the FIFO also loads it into the direct read register. The three-state outputs of this register are
not enabled unless direct mode has been selected by a previous microinstruction, and the transfer is
enabled by the bus source field of the current microinstruction. The direct read register is used when
verifying sector headers in a formatted read or write operation.
Four of the FIFO inputs, FIFOINI6-19, are devoted to flags. Signal selection for the flag inputs is
performed by the FIFO flag multiplexer. This multiplexer is enabled (ENFLAG-) during read operations, or for special group 3 microinstructions. For other cases, the multiplexer supplies all zeros at
the output.
The FIFO flag multiplexer outputs are:
Read Operation (DSKWRTQ=O)

Special Group 3
Microinstruction Bits

Other

Outputs

0

FIFOINI6
FIFOINI7
FIFOINl8
FIFOINI9

0
0
TIMERRQ

ROM38

0
0

CRCERR

ROM39

0

ROM36
ROM37

The four flags are routed into a FIFO device, and are effectively appended as extra bits to an incoming data word. With the exception of FIFOINI9, these flags perform no function until they
reach the FIFO output.
The CRC error flip-flop is directly controlled by FIFOIN 19, so that the CRC character in a sector
header can be checked in read direct mode. The output of the CRC error flip-flop is monitored by
the CPE I-bus input for read direct operations. For other read operations, FIFOIN 19 is monitored
by the CPE I-bus when it reaches the FIFO output (FIFOOUTI9).
When FIFOINI6, 17, and 18 reach the FIFO output (FIFOOUTI6, 17, and 18), they are stored in
the disk write flag register by a disk clock pulse. FIFOOUT16 controls the CRC enable flag,
CRCENFLAG and CRCENFLAG-. For a read operation, the hardwired 0 into the FIFO input
multiplexer reaches the disk write flag register (as FIFOOUTI6) and holds CRCENFLAG low, so
that read data may enter the CRC generator/checker to be monitored for CRC read-back errors
(CRCERR). For a write operation, bit 36 (ROM36) of a special group 3 microinstruction controls
the flag. CRCENFLAG must be held low for the duration of the data transmission, to calculate the
CRC character. ROM36 changes the flag as the last data word enters the FIFO. When that data
word and the flag reach the FIFO output, CRCENFLAG goes high to disable additional CRC
inputs and gate the CRC character through the write datal CRC multiplexer to the disk.

2-142

Digital Systems Division

~----------------------------~

946262-9701

DISK READ OR
WRITE CLOCK

r-...

•

I '-

READ/WRITE
CONTROL
FROM READ
BUFFERS

'-

(SERIAL WRITE DATA) CRC GENERATOR

0

SERIAl}

--.-

•

-~

(MS8)lPARDATOO
--

-to
-to

-

PARALLEL _
SHIFT
__

FIFOOUTI5
DISKDATLO-

•
•

DAT~

~K

(SERIAL READ

~~~~~~~S;:~;IO~N - - - -.....---l~

FIFOINOO

••

t:- • .;

~

:..

~
)lIIiBiiUiiSiIIIIPIliBU_SilOO-ililiI'5i11• • •I!IJ~fo"
T

~G

BUFFERED PROCESSOR

t:. . .

PROCESSOR BUS.PilBUiiiSiilS....

re
r-FIFOINIS

PBUSOO....

RSTPBUSOo- THRU

~

SHI7

I

...

FIFO FLAG

~

MUX

0

CRCERR

I

WRr"E =1!

REA

°
TIMERRQ
CRCERR

PBUSOO-IS

:~~~~

:::~:~:~
FIFOINI8
FIFOINI9

ROM37

FIFOINI8

B

ROM38

_____+-__R_O_M_3_9_ _~~

........,

"''-

~)

-

l

MDCMP-

16-WORD FIFO
DATA BUFFER

rSH17

U;::;..::.TC~S~H~IN-~

______________

~~~~ ~~S~H~I~F~T~IN~-+
__

____

~~

=~O~.J

DISK CLOCK

CNTEQI5

•

DSKWRTQ-

r

DCLK

L

READ

-.

~M~D~C~M~P_ _ _ _ _ _ _ _ _ _ _~~a~
SHI6

MICROINSTRUCTION

-

;..0--41>--------0
;J
SHI5

.r

~

FIFOINI8

--"0

FIFOINI9

~

~+-~I~s~H~I~FT~IN
1f';\.
11\..:.1

..../

FIFOOUTI4

MICROINSTRUCTION
PROCESSOR BUS
SOURCE CONTROL

r
IRDYA-C

DECODE

D-

WRITE DATA

.;;..:;==.:..;;;;;....------------rJ

SHI8
DCLK

FIFOSEL

I

PBZERo-

,......:F....:Ic:...F..::.OD;::;A..::.T~E~N--(:::JL__
./"

ZERODATEN-

t

DISK WRITE
FLAG REGISTER

~~~
I

CLR

IR

SH17
OR

FROM

r

TLSHOUT-

TYPICAL FOR

AL~IFO~ITS_ _

}

~

TOCRC
GENERATOR/CHECKER

~F~IF~0~OU~T~I~7____________________________~B

Q8 CRCPREFLAGr-...

~F~IF~OOU~~T_l~8______~____________________~C

QC~___________
V_~
__....:S;::;T~O;::;P~F~LA~G=-__4-______~

FIFOOUTI9

CRCPREFLAGCPEI-BUS

__..:D:..:C:..:L:::K~I_----fCK SHI 8
DISK READ OR

CLR

WRITE CLOCK

~}

I
I

I
__ -.J

CPE 1-8US

DSTARTQ

INPUTS

FROM DISK I/F
START LOGIC

GROUP 00

CRCPREFLAG-

FIFO TIMING
ERROR F/F

~

SHIFTOUT-

IRDYB

~___________~IR_D_Y~C~-t

IRDYD

'"
INRDY..
~~~-+-+--OU--T-R-D-Y--~

CRCPRES-..

-,u-

K

'----.,...---I~

B

CRCPREFLAG:

SHI4

CRC GENERATOR

~

-

TIMERRQ
__--------i~ INTERRUPT
LOGIC

SHI7

~

UTCSHOUT-~}-__~S~H~I~F~T~OU~T____________________+--e>--______________~S~H~I~F~T~OU~T________________________________________________________S_H_I_6______-i~~S~H~I~F=T~OU~T~
DSKSHOUT-:::J....-/

CRCENFLAG-

V

QA~_______________C~RC~E~N..::.F~LA..::.G~______- - .

r I
DSKCLR-

_

1

~F~IF~OOU~~T~I~6____________________________~A

G

L....:D::.:S::.:K.:.:W~R:.:.T.:..Q=-_ _ _ _ _...:D::.S::K~W.:.:..:.:R~T.::Q:..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---=D:.:S:.:..K:.:.W:.:R.:.T:..:Q=--------------~f

SPECIAL GROUP I

FROM DISK I/F READ/ DISKDATLD
WRITE CONTROL

-

-SHI8

MICROINSTRUCTION

V

"'

ORDYA-C

16·WORD FIFO DATA
AND FLAG BUFFER

r - - -- 1

_______

L

.-.

;]

TILINE
MASTER LOGIC

DECODER

SHI8

READ

FIFOINI7

DISKDlRECT-

READ

~

•

I.-!=~:":"--~I-"""
ROMI3L
MDACT

FIFOOUTI5

r--~O~

______

DSKSHIN-

ROM33L-

.../

IR

i

I

•

r--.-""

r - - - - --,

CKIN

-

WRITE FORMAT, GAP

_ __________________________________

DISK READ OR
WRITE CLOCK

r-

FIFOINI6

SHI8

FROM DISK
R/W CONTROL {

A

RST-

~

FROM MICROINSTRUCTION

PBUSOO- THRU PBUSI5(READ DATA)

....

·o·'--~""'--"'"

FROM P-BUS SOURCE
CONTROL REGISTER

_

ENFLAG-

~U~T~C~S~H~IN~-

-~

F,.,ooTOO

t;.F,t,,: B
FIFOOUTOO . /

-Jp

--------'--IN PU T

~[>_ _ _T~LS~H~IN~-_ _ _- - ,

DSKDIRQ

..

DCRCERRQ_ _ CPEI-BUS

WRITE DATA

ROM33L

TROL DECODE

....
....

"",-FI;.;..F.;.;OI;;.;.N;...;14-..

Q-

DSKWRTQ

LATCHED VERSION
OF ROM33

(READ)

• ..

FIFOINI5

INSTRUCTION SPECIAL

PBDSKDAT-

I

41- •

GROUPI'-

GROUP FIELD DECODER

P-BUS SOURCE CON-

PBUS15~

.-e

SHI8

~G

FROM DISK I/F READ/ DSKWRTQ
WRITE CONTROL
"::':::":':::":':'~----------1.......~r

FROM TILINE
MASTER LOGIC

FIFOOUT/ZERO
MUX (3STATE)

SHI5

"'-

~-'---'---'-----4D

DSKWRTQ

TILINE CONTROL
FIELD (LATCHED)

••

FIFOINOo-15

ROM38
ROM39

FIFOINI9

ROM36

FROM TILINE
MASTER LOGIC

SHI5

-

OUTPUTS

CRC ERROR
F/F

FIFOIN17

FROM MICRO-

••

~FOINI5

FIFOINI6

SHI7

{

INPUTS (DIRECT READ
DATA)

PBUSOO-

OE

r-.,FIFOINOO

GENERATOR/CHECKE~--------=~~~-----~r-------~

FLAGS

FIFOINOO

SHIFTIN

TIMERRQ

MICROINSTRUCTION SPECIAL GROUP 3

TO TILINE LINE

(WRITE)

r---.---------------~CK

NO EFFECT PARDA;Oo-l

"0"

T

DSKWRTQ

O

PROCESSOR BUS

FIFO INPUT AND FLAG MUX SELECTION

ENFLAG-

.O---'-"'~-~
FROM CRC

BU~

PROCESSOR

............................................................iiii....................,"....~ ~:IVC~ES~~~~DATA)

,

A

SHf7

DATA)L---=C~fr-....J

DIRECT READ
REGISTER

DIRDATIN-

MUXES

-to

REGISTER
(LS8) PAR!ATI5
151-'---'--------iM
J

~

P8DSKDAT-

-----D-S-K-D-IR-E-C-T---~:IT-....
"

DECODER

FIFO INPUT

---~~~~~--~~S/L

DISKDATIN

MICROINSTRUCTION
PROCESSOR BUS
SOURCE CONTROL
DECODER

TO WRITE DATA BUFFERS,

I

CK

::!
...

•

r---

PARDATOO

-..;;;..;;..::;."'----""1,

FIFOOUTOO

tFROM DISK I/F
START AND

-u-

DCLKI-

FROM DISK
I/F START
LOGIC

"0"

DSTRQ

I

FIFO TIMING AND CRC
PRESET MUX SELECTION
READ
INRDYOUTRDYSHIFTIN
SYNCQ

WRITE

OUTPUTS

OUTRDY-

ERRORSET

INRDYSHIFTOUT

RDYSTATU5SHIFT

CRCPREFLAG

CRCPRES-

1

2281583

Figure 2-51. First In, First Out (FIFO) Buffer
and Related Logic

2-143/2-144

Digital Systems Division

~------~

946262-9701

_= __

A'-' ~_ :-1 ___ .:- ___ 1 ____ 1"""'" ... 1- .... 1-. ....
=___ £' .... _~_....l __ ... 7_;+.0 + ... n~C'I.fo ....
l'iUlll,;t; llHtl \...-I'\.\"'-Cl'ir L/"\.\J l~ i:1IWi:1y~ IUW i:1l lIlt; Ut;~l1l111J1~ Ui a. il;"a.U Vi \IV.lH .... Uu,u.> ........ ,

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hD"l)Il1~~

thp

rfl~1r

.... '"''''' ........ ..., ... u ........... ~.~

write flag register is held reset until the disk start F / F sets.

Flag bit 17 controls the CRC preset flag output of the disk write flag register. The CRC generator
internal registers must be preset to all ones before starting to calculate or check a CRC character.
For write operations, ROM37 of a special group 3 microinstruction is sent through the FIFO
(FIFOOUT17) before the first data word. ROM37 high sets the CRC preset flag stage of the register,
and the inverted output CRCPREFLAG- is selected by a multiplexer and sent to the CRC generator
as CRCPRES-.
For read operations, the state of CRCPREFLAG- is irrelevant, because a multiplexer selects the
synchronization detector output, SYNCQ, as the source for CRCPRES-. SYNCQ holds the CRC
generator constantly preset until the synchronization character (6E 16 ) is detected.
Flag bit 18 controls the stop flag (STOPFLAG) for write operations. A special group 3
microinstruction loads a stop flag into the FIFO with the last data word. When the data word
reaches the FIFO output, the stop flag informs the microprogram that the data transmission is
complete.

For read operations, flag bit 18 is used to inform the microprogram of FIFO timing errors. FIFO
timing errors are detected by the FIFO timing error flip-flop (TIMERRQ). For read operations,
TIMERRQ is gated through the FIFO flag multiplexer and through the FIFO, and monitored
(FIFOOUT18) by the CPE I-bus.

FIFO Input Loading. Two inputs, DISKDIRECTIN- and SHIFTIN, control the loading of data
and flags into the FIFO. DISKDIRECT- acts as a constant (high) enable when the controller is not
in the direct mode. The direct mode is used when the controller verifies sector headers from the disk.
Since this operation does not require the TILINE, there is no need to use the FIFO. The controller
uses the direct read register for verifying sector headers. For all other operations involving data
transfer to or from the disk, the FIFO is used, and DISKDIRECT - is held inactive (high).
The SHIFTIN signal is the strobe which actually loads data into the direct read register, the FIFO,
the CRC error F I F and (for read operation only) the FIFO timing error F I F. Data is shifted in on
the positive-going (leading) edge of SHIFTIN.

A SHIFTIN signal is generated if TLSHIN-, UTCSHIN-, or DSKSHIN- is active (low). TLSHIN-,
TILINE shift in, is generated during write data or write data unformatted operations (R1, bits
5-7 = 011 or 101). During these operations, the disk controller, acting as a TILINE master, reads
words from 990 memory and transfers them over the TILINE and the processor bus to the FIFO
input. ROM33L, a latched version of microinstruction bit ROM33, is low to command a TILINE
master read cycle. The master device complete (MDCMP-) pulse shifts the data word into the FIFO
and restores the TILINE master access logic to its initial state.
UTCSHIN- is generated to load a word from the CPE outputs into the FIFO. UTCSHIN- is
generated by a microinstruction which specifies the FIFO as the processor bus destination (ROM20,
21 == 10).
As an example of this type of operation, consider the gap and synchronization character which must
precede a header or a data record on the disk. The disk electronics includes a phase-locked read
clockl data separator. In order to phase lock the disk drive variable frequency oscillator (VFO)
before reading the record, the prerecord gap must be filled with clock pulses as part of the write
operation. This is equivalent to saying that the disk controller must write an all-zeros record into the
gap which precedes the data record. Also, the last eight bits of the gap must be a 6E 16
synchronization character, to notify the controller to start reading data and start performing the
CRC calculation.

2-145 .

Digital Systems Division

~ ___9_46_2_62_-9_7_01__________________________________________
NOTE

There cannot be any phase jumps or discontinuities between the end
of the all-zeros (clock only) record written in the gap and the actual
data record. For this reason, if a record is to be rewritten (as in an
update) the preceding gap and sync character must also be rewritten.
There will be glitches at the very beginning of the rewritten area of the
track, but this is an area which is not monitored during read
operations.
The CPE array supplies the all-zero words and the 006E word which marks the end of the gap and
the beginning of the data record or header. Each of these words is strobed into the FIFO by a
microinstruction which specifies the FIFO as the processor bus destination (ROM20, 21 = 10). The
controller requests data words via the TILINE and loads them into the FIFO while the write gap
operation is in progress.
As another example, CPE output data is loaded into the FIFO and transmitted to the disk during a
write format operation (Rl, bits 5-7 = (01). This operation writes the record headers on a track,
and fills the data area with a data word. The sectors per record parameter determines which sectors
get record headers. There are no TILINE to disk transfers during a write format operation.
Data read from the disk is converted to parallel form in the serial to parallel shift register, and loaded
into the FIFO (or direct read register) by a DSKSHIN- pulse. DSKSHIN- is generated during read
operations (DSK WRTQ- high) when a full 16-bit word has been shifted into the serial/ parallel shift
register (CNTEQ15 high). A disk clock pulse (DCLK) strobes the command on the leading edge. The
first bit of the next data word is shifted into the shift register on the trailing edge of disk read cloc-k.
FIFO Output Unloading. Output data is unloaded from the FIFO on the trailing (rising) edge of
SHIFTOUT-.
NOTE

FIFO output data is valid and available before the SHIFTOUTpulse. The external circuitry (CPE input, serial/ parallel shift register
or 990 main memory) accepts or stores the FIFO output before the
SHIFTOUT- pulse.
The SHIFTOUT- pulse allows the next word in line to reach the FIFO output stages and, after
ripple-through time, frees an input word location for reuse. The output ready signal is disabled for
the duration of the FIFO unload (SHIFTOUT-) pulse.
Three signals, TLSHOUT-, UTCSHOUT-, and DSKSHOUT-, can enable a SHIFTOUT- pulse.
TLSHOUT- (TILINE shift out) occurs during read data or read unformatted operations. During
these operations, data is read from the disk and stored in 990 memory by a series of TILINE master
write cycles. ROM33L- is low to command a TILINE master write cycle. A low master device complete (MDCMP-) pulse occurs upon completion of the master write operation. MDCMP- returns the
TILINE master access logic to a reset state and enables TLSHOUT-.
In some cases it is desirable to read data from the disk through the FIFO and over the processor bus
without transferring the data over the TILINE.
For example, during closed-loop self-testing of the controller, data is transferred out through the
FIFO to a test memory and then transferred back through the FIFO to the CPE inputs. The
UTCSHOUT- pulse is used during the read-back operation to unload the FIFO.

2-146

Digital Systems Division

~_
946262-9701
J}7_S\
_ _ _ _ __

The DSKSHOUT- pulse causes a FIFO unload pulse (SHIFTOUT-) each time a data word is loaded
into the serial/ parallel shift register for transmission to the disk. The parallel data is loaded into the
seriall parallel shift register on the leading edge of the DISKDATLD- pulse. The next disk clock
pulse enables the DSKSHOUT- pulse. The trailing edge of that disk clock pulse disables
DISKDATLD- and performs the FIFO unload function.
During read operations, FIFO output data is routed to the processor bus via the FIFOOUT Izero
mUltiplexer. This multiplexer supplies all data zeros (high levels to the active low processor bus)
when commanded by the P-bus source field of a microinstruction. It is in the high impedance state if
neither zeros or FIFO data are required. If disk data is required for a TILINE master cycie or for
CPE input, FIFO data is gated through the mUltiplexer. When no source of data is selected, the
PBUS is in the high impedance state, and can be manipulated by an external source such as a RAM
board.
During write operations, FIFO output data is loaded into the seriall parallel shift register by the
trailing edge of a DISKDATLD- pulse from the disk II F start and read I write control logic.
Subsequent disk clock pulses shift the data serially through the register and clockl data encoding
logic to the selected disk unit.
2.12.1.5 Cyclic Redundancy Check (CRC) Circuitry. The cyclic redundancy check provides a
rigorous method of error detection over the course of an entire data record. All the serial data in a
record is processed by an error-checking algorithm as it is transmitted to the disk drive. The result of
the CRC calculation is a 16-bit CRC character which is transmitted at the end of the record. When
the record is read back, the read data is reprocessed according to the same checking algorithm. At
the end of the record, the CRC character calculated during the read operation must compare to the
CRC character recorded at write time or an error has occurred.

The disk controller uses a 9401 programmable CRC generator I checker. The programming inputs
are hardwired low to permanentl~ select the CRC-16 algorithm. This algorithm divides the write
data stream by the polynomial X 6 + XIS + X2 + 1. The CRC character is the remainder left after
that modulo 2 division. During read operations, the record is again divided by the polynomial. When
the recorded CRC is shifted into the 9401, the new remainder and the recorded CRC character
should cancel, leaving all zeros in the CRC generator internal registers.
The important thing to know about the cyclic redundancy check is that it is much superior to a
simple parity check. A parity check can only detect odd numbers of errors. The CRC algorithm used
in the disk controller can detect:
•

All odd numbers of error bits

•

All 16-bit or shorter error bursts

•

99.9969% of all 17-bit error bursts

•

99.9984% of all longer error bursts.

These error burst figures assume a single error burst in the transmission.
Figure 2-52 is the equivalent circuit for the 9401 CRC generator I checker as used in the disk
controller. The CRC generator has flip-flop stages connected as a feedback shift register. The
exclusive-OR gates in the feedback chain correspond to the terms of the CRC polynomial.
All stages in the 9401 must be preset to ones just before processing a write or read data record. A low
CRCPRES- signal presets the generator. CRCPRES- is supplied by the FIFO timing and CRC

2-147

Digital Systems Division

CRCPRES-

2

r;I

CHARACTERISTIC POLYNOMIAL, X l6
PRESET LINE

+ XIS + X2 +

I

1 (CRC-16)

-----'-,- - - - - -

---- -----..

FEEDBACK LINE

--------------+----

I

I

FEEDBACK LINE

---------------4---------~--------~~----.------------+_--------------1_--------_,

I
CRCDATIN

11

CRCENFLAG-l0

I

10

II

CWE

DO

12 CRCDATOUT

CHECK
WORD
ENABLE

CLOCK LINE

DCLK

SO

S 1

.---~~--~

}

EO

CRC POLYNOM IAL
SELECTION
(OM ITTED)

1,

I

S3

. . .- - - - - - - ' j

I

GND

L -_________________________________________________________________________- ,

L

I
~

NOTES:
1.

~~~T~H5~~AW~.f~E~~~BLd'W~%t)S~N~~THEi:'~t~JjI~~ ·S~r~_?~0/~~EC~~Stt~~~~Tg:c TgH~~~g~~ (Jj~liglt~.f5~~V~R
A VALID CRC ERROR INDICATION (READ).

2.

THE ERROR OUTPUT (EO) IS VALID AFTER THE CRC GENERATOR HAS PROCESSED THE ENTIRE READ DATA STREAM AND
ACCEPTED THE LAST BIT OF THE CRC CHARACTER WHICH WAS APPENDED AT WRITE TIME. EO REMAINS VALID UNTIL
THE NEXT NEGATIVE-GOING CLOCK TRANSITION.

(B) 138624

Figure 2-52. Equivalent Circuit for CRC Generation

3 CRCERR

946262-9701
Jd7)\ _
_ _ _ _ __
~

preset mUltiplexer. CRCPRES- i:s developeJ a:s the result of detecting the synchronization character
(read) or as the result of a CRC preset flag which is enabled by a special group 3 microinstruction,
shifted through the FIFO in advance of the transmission, and latched in the disk write flag register.
CRCENFLAG- must be high to allow read or write data to be shifted into the CRC generator. For a
write operation, CRCENFLAG- must go low at the end of the record to allow the CRC character to
be shifted out. CRCENFLAG- and its complement CRCENFLAG are controlled by a special group
3 microinstruction. ROM36 of the microinstruction is routed through the FIFO flag multiplexer and
through the FIFO (FIFOOUTI6), and latched in the disk write flag register.

CRCDATIN is the serial read or write data input to the CRC generator/checker. Disk clock,
DCLK, loads the data on the negative-going (trailing) edge.
The CRC character is serially transmitted out of the 9401 on the CRCDATOUT line. The CRCERR
output is valid at the end of a read operation, when the CRC generatorI checker internal registers
should contain all zeros.

Figure 2-53 shows the CRC generator/ checker and the associated multiplexers. The CRC read/write
multiplexer selects read data (DISKDA TIN) or write data (PARDA TOO) as the data input,
CRCDATIN. During write operations, the serial output of the serial/ parallel shift register feeds the
write data encoding circuits until the CRC enable flag gates the CRC character through the
datal CRC mUltiplexer.
2.12.1.6 Read Data Buffers and Disk Read/Write Clock Distribution. Figure 2-54 shows the read
data buffers and disk read/write clock selection circuitry. The figure also shows the sections of the
CRC logic which apply to read operations. This description also requires reference back to figure
2-48, disk 1/ F start and read! write control.
Data is serially recorded on the disk in double frequency FM form, that is, with clock and data
pulses multiplexed into the same bit stream. The time between the leading edges of the successive
clock pulses is a bit cell. To record a data one on the disk, a pulse is recorded in the middle of the bit
cell; and to record a data zero, no pulse is recorded in the middle of the bit cell. The instantaneous
frequency of the waveform is determined by the data being recorded. If all zeros are recorded, as in
gap 1 or gap 2, only clock pulses appear on the track, and the frequency is 2.5 Mhz. If all ones are
recorded, the frequency is 5Mhz. During typical operations, the frequency varies with the data
pattern between these limits.
A phase-locked clock/ data separator in the disk drive electronics supplies clock (RCLK-) and data
(RD-) to the disk controller on separate lines. For read operations, RCLK- serves as the source for
the disk clock signals (DCLK, DCLK-, DCLK 1-, DA TCLK) distributed through the disk interface
circuits of the controller.
Read buffer timing is shown in figure 2-55. The top two signals in this diagram are disk clock (read
clock) and read data. The diagram clearly shows that the read data pulses fall in the middle of the bit
cells defined by DCLK-. DCLK and DCLK- are used to time all read data operations up through
FIFO loading. FIFO unloading is asynchronous to disk clock during read operations.
The disk clock pulse at the beginning of a data cell clears the read 1 F IF in preparation for the data
pulse. The read pulse width is specified between 50 and 150 nanoseconds, with 100 nanoseconds
nominal. The time between two successive disk clock leading edges (400 nanoseconds, nominal)
defines a sampling window for the data pulse. The data pulse (RD-), if any, asynchronously sets the
read 1 F IF. The disk clock pulse which ends the sampling period transfers the data bit to the read 2
F IF, and prepares read 1 for another input.

2-149

Digital Systems Division

SERIAL WRITE
DATA FROM SHIFT
OUTPU T (MSB) OF
SERI AL/PARALLEL
SHIFT REGISTER,
SH17.

... -

DATA/CRC MUX
PARDATOO

D

CRC

r--JI

""

I
I
I
I
READ/
WRITE MUX

DISKDATIN

...

I

2.

I
I

A SINGLE SE T OF CONTROL
SIGNALS STE ERS BOTH
MULTIPLEXE RS.

3.

CRCENFLAG- HIGH TO SHI FT
READ OR WRI TE DATA INTO
t 6-BIT CRC GENERATOR/
CHECKER.

4.

CRCENFLAG- LOW TO SHIFT
16-BIT CRC CHARACTER OU T
TO DISK.

5.

CRCERR VALl D FOR ONE
CLOCK TIME AFTER LAST
16-BIT WORD OF RECORD
SHIFTED IN.

FROM FIFO
TIMING AND
CRC PRESET
MUX. SH17

W

CRCPRES-

I
I

t

PRESET

CRCDATIN
(READ OR WRITE
DATA)
R

~

V

DCLK

JL

......

D
9401
CRC
GEN/CHECK

.~

'"

CK
EO
CWE

FROM DISK R/W
CONTROL, SH14

DSKWRTC

j~

CRCENFLAG
FROM DISK
{
WRITE FLAG
REGISTER, SH1 8

CRCENFLAG-

2

CRCDATOUT

(SERIAL CRC CHARACTER)

I
I

I CRC

SERIAL READ DATA
FROM READ DATA
BUFFERS

THIS LOGIC S HOWN ON DWG
937502
SH1 9 (PWB) OR DWG
226210 , SH 19 (FINE LINE).

I
I

I

..

1•

I

I

TO WRITE
DATA/CLOCK
ENCODING
LOGIC

NOTES:

I

I

.-

WRTDATD (WRI TE DATA OR CRe)

CRCENFLAG-

2282579

Figure 2-53. eRC Generator/Checker Input/Output Connections

CRCERR

....

TO CRC
ERROR F/F,
FIFO FLAG
MUX, SH17

~-------------------~-------------~

946262-9701

FROM FIFO TIMING AND

CRCPRES-

CRC PRESET MUX
CRC READ/WRITE MUX

-------

....

~
r---..w..----,
I"l~
CRCDATIN

V

DISKDATIN

CRC
GENERATOF
AND
CHECKER
~

DCLK

CRCERR

I

READ DATA

RD-

1

DISK UNIT

FROM DISK WRITE
CRCENFLAGFLAG R EGIST ER
----....;.......;;..;;;;...,;.;...;;;;;;..;..:;;......---l

READ1 F/F

WRITE CONTROL

J

Q

CK

DIAGFAULTQ-

r

RDATA-

...J

WRTDATOUT-

-"'"

READ2 F/F
D"

L,../

TESTRDDAT-

Q

DCLK1SIL
- - - -....I>CK

DISK DATA
IN F/F
RDATAQ

t - -.....--------t D

--IL
. ._. :

QI--...D.....:..IS:.:K...:;D:.;A;.;...;.T.;;.;IN-=--_ _ _ _

.

,---,---,--

FROM DISK IIF
DISKDATLD
START AND READ/

DCLK

TO FIFO INPUT
FLAG MUX

r

RDA-

FROM SELECTED

is

SH

~

((

(

I

I

I . ••

~

~

SERIAL/PARALLEL
SHIFT REGISTER

SH 17
, DCLK-

L..-D_C_L_K_--I C K
J

RST-

FROM WRITE

WRITDATOUT-

DATA ENCODING

r-- - - ---- - - - - - - - - - -,
I

(TEST ONLY)
TESTMODEQ

i
I

I
FROM MICROI NSTRIJ CTION
SPECIAL
GROUP!
DECODERI

1

TESTCLK-

CK

RST1-

~ TESTRDDAT-

264-BIT
SHIFT REGISTER

I
I

L ______________ _

REG

T

PARDATOo-15

I

t'...

PARDAT!O

I

t'...

PARDATll

H>-

PARDATI2-

r-...

PARDAT13

I'.

PARDAT14

I
I
___ ...1

PARDAT09

TO SYNCH CHARACTER (6E)
DETECTOR IN DISK I/F
READ/WRITE CONTROL

PARDAT15
DISKDATIN-

DISKDATIN-

-,
I
I

TESTCLK-

FROM SELECTED

~DCLOCK

L __________ _

o

13

I'----l>

READ CLOCK

WRITE

i4

,

CONTROLLER SELF-TEST

DISK UNIT

5

•••

I
I
I

TEST DATA

TESTDATA

j

Qr-___D_IS_K_D_A_T_IN_-_ _- ,

I

DCLK1-

~

DCLK

DISK CLOCK TO ALL

;>

DATCLK

DISK READIWRITE CLOCK SELECTION AND DISTRIBUTION

DISK INTERFACE
CIRCUITS

DCLK-

~

_

I
I
I

.. _ _ _ _ _ ...1I

(C) 138643

Figure 2-54. Read Data and Clock Buffers, Self-Test,
and Disk Clock Distribution

2-151/2-152

Digital Systems Division

READ
CLOCK

DCLK-

DATA
RD-,
RDA--

"'I
r
-U......----..U
...

---11
I

B IT CELL 400 NSEC
NOMINAL

t4I

1 00 NSEC
NOMINAL

(50-1 50 NSEC)

U--LJ---.iU. . . . ._LJ

l

o

u

U ~O-150 N~EC

----.t 14--

u

:

(100 NSEC NOM INAL)

READ 1 F/F
RDATA-

NI

0

0

0

0

0

0

READ 2 F/F
RDATAQ

""""
til
W

L

DISKDATIN

SHIFT
REG.
LSB PARDAT15
__________________________________

~

1 DISK
CLOCK TIME
DELAY

(A) 138632

Figure 2-55. Read Buffer Timing

I

,"----

~------~

946262-9701

The read 2 F / F converts the incoming data from bit-cell format to nonreturn to zero (NRZ) format.
This format (see RDA T AQ) is the most natural for serial data processing. There is a disk clock pulse
width delay (approximately 100 nanoseconds) between the RDAT AQ and DISKDATIN
waveforms, as RDAT AQ is clocked on the leading edge of disk clock, and DISKDA TIN is clocked
on the trailing edge.

DISKDATIN is routed to the CRC logic for error checking, and to the shift register for serial to
parallel conversion. DISKDATIN- is used in synchronization character detection, described later in
this section.
DISKDATIN is loaded into the least significant stage of the shift register (PARDATI5) on the next
disk clock trailing edge. Subsequent disk clock pulses shift the data until a full 16-bit word is
available on the PARDATOO-15 lines. A disk clock pulse counter in the disk 1/ F start and read/write
control logic tallies these shifts so 16-bit data is correctly loaded into the FIFO and direct register.
Figure 2-56 is a detailed timing diagram which shows the principle events which occur at the
beginning of a read operation. These events include the disk interface start command, reception and
recognition of the synchronization character, and shifting of the first data word into the FIFO
buffer / direct register. In addition to the read buffer logic of figure 2-54, refer back to the disk
interface start and read/write control logic, figure 2-48.
This description applies to reading data as part of a read data or read unformatted operation, and
also to reading sector ID headers as part of a read data or a write data operation. This description
assumes that the read gate (RG-) to the disk has previously been asserted, and that the read gate
delay has been counted down in the controller microprogram. This is equivalent to saying that the
clock/ data separator logic has been enabled for a period sufficient to lock on to the disk clock.
Recall that disk clock is recorded in the preheader and prerecord gaps (gap I, gap 2) to make this
synchronization possible.
The disk read/write command, DSKWRTQ, must be low for the duration of the operation. This
signal is supplied by the microinstruction special group I decoder/register, and the state is latched,
so that a specific microinstruction must be used to change read or write mode. This disk 1/ F start
logic is initiated by a disk start transfer clock (DSTRTCK-) pulse. This pulse is synchronized to the
microprocessor clock pulse, and sets the disk start transfer F / F (DSKSTRQ).
The next disk clock pulse resynchronizes the operation to disk clock by setting the disk start F / F
(DSTARTQ). All remaining disk interface operations, up to the point of loading the FIFOj direct
register, are synchronized to the clock pulses recovered from the disk.

During the gap prior to the header or first data word, the read buffer and serial/parallel shift
register cycle on all zeros, waiting for the hexadecimal6E synchronization character which serves as
a pointer to the first header or data word. The synchronization detector monitors the shift register
parallel outputs, looking for the following combination:
PARDAT
09

o

PARDAT
10

11

12

13

o

14

15

DISKDATIN

o

Note that the shift direction for data entry is from DISKDATIN to PARDATI5, to PARDATI4, ..
. toward PARDATOO. The sync pulse (SYNC6E-) is actually generated one disk clock cycle before
the sync character is fully shifted into the shift register. The synchronization F / F, SYNCQ, clocks as
the last bit of the sync character shifts into the shift register. Note that the sync F / F is connected in
an upside-down configuration.

2-154

Digital Systems Division

~

946262-9701

DISK START
TRANSFER CLOCK
DSKTRTCK-

READ/WRITE
DSKWRTQ

o

o~

SYNCHRONIZED
WITH MPCK-

S"'-------

~

NO CHANGE FOR
DURATION OF
READ OPERATION

f
DSKSTRQ

o

DSTARTQ

0

f f

J

SYNC6E-

j

!

....

I

0

I

I

SYNCQ

0

>

READQ-

NO CHANGE FOR
DURATION OF
READ OPERATION

I

0

~

I

CNTEQ15

0

I

SHIFTIN

Cl

0

f S
RO-

if

O

r
0:

I

I

I

1

SYNCHRONIZATION CHARACTER

U
0

DISKDATIN

0
SHIFT REG LSB
PARDAT15

0
DCLK-

0

J

J

; f

,

.

U

I

I

I

1

t

,

1

I

I

(

1

10.

I

u u u

1

,

1

U

U

U

0

,

,

I
I

:0:

.

I

I

I

·r

BITO

BIT',

~

13

0

1

I
I

FIRST
DATA WORD

I
I

BITO

BIT2

BIT3

l@

~

I

BIT1

I

BITO

I
I

f

FIRST DATA

W~

SECOND
DATA WORD

f

BIT'5

fiE)

BIT2

IHB!T141

BIT 1

1ft

BITt

BIT2

BIT3

EJ

EJ

13

BIT15

IBIT14

1.1

u u u u u u u u

I
I

BITO

BITt5

I
I

"'
~

I

BIT2

BIT 1

BITO

RD INTO FIFO

I

u u u

f

)

BIT'

,

(B) 138642

Figure 2-56. Timing for Synchronization Character
Detection and FIFO Loading

2-155/2-156

Digital Systems Division

~------~

946262-9701

The read F / F sets on the next disk clock pulse, removing the constant clear input to the bit counter.
The bit counter starts at 00 as the first data bit enters the shift register. The next clock pulse advances
the bit counter to 0 I as the register shifts in the second data bit.
The sixteenth shift pulse enters the last data bit into the shift register, and the bit counter indicates
saturation (CNTEQI5) for the next disk clock period.
The trailing edge of disk clock is used for shifting the data. The SHIFTIN pulse is enabled on the
leading edge of disk clock when CNTEQI5 is high, so that stable data is loaded into the direct read
register or FIFO input. The trailing edge of the disk clock pulse shifts in the first bit of the next data
word, and rolls the bit counter over to 00, so CNTEQI5 is disabled. Successive disk clock pulses shift
the register until the next 16-bit data word is assembled on the PARDATOO-15 output lines. The
shift, count, and load to FIFO I direct read register sequence repeats until the entire record is read.

2.12.1.7 Write Data and Clock Encoding. Figure 2-57 summarizes disk write clock generation and
write datal clock encoding. The basic timing reference for write operations is a crystal-controlled
5 Mhz square-wave oscillator. The oscillator runs constantly, although the output, DSKOSC, may
be gated off by external clock stop signals (WOSCTST-, WOSCSTOP-). A controller fault detected
during self-test also will disable the clock output. In this case, a special group 1 microinstruction
disables the oscillator output and lights the FAULT indicator with the DIAGFAULTQ- signal.
The output of the oscillator gating logic is the 5 Mhz write clock signal, WCLK. A divide-by-two
circuit produces a 2.5 Mhz square wave, WCLKAQQ-. WCLKAQQ- is used in write data encoding,
as described in this section. Also, reference back to the disk clock distribution circuits of figure 2-54
(Read Data Clock Buffers, Self-test, and Disk Clock Distribution) shows that WCLKAQQ- serves
as the source for disk clock during write operations. DCLOCK, DATCLK and DCLK are (except
for gate delays) identical to, and in phase with, WCLKAQQ- if disk write (DSKWRTQ) is high and
no fault is detected.
Notice that disk clock, DCLK, is a symmetrical wave train with a 50% duty cycle for write
operations, while disk clock has a 25% duty cycle for read operations.
Figure 2-58 is a timing diagram which shows the write data and clock encoding. This timing diagram
assumes that a parallel data word has been loaded into the shift register and is available for transmission. The complete operation, including the details of shift register loading, is described on
another timing diagram in this section.
Serial data is shifted to the MSB output of the seriall parallel shift register, PARDATOO, on the
trailing edge of disk clock (rising edge of DCLK-). One-half clock time (200 nanoseconds) later, the
data bit is loaded into the write data out F IF. WRTDA TOUT-and WCLKAQQ- are combined in a
NAND gate to produce write data and clock enable, WDNCLKEN.
WDNCLKEN serves as a gating signal to gate 100-nanosecond WCLK pulses through the write data
and clock (WDNCLK-) NAND gatel driver to the selected disk drive. Whenever WDNCLKEN is
high, write clock (WCLK) pulses are inverted and transmitted to the drive. WDNCLKEN drops low
for 200 nanoseconds in the middle of a bit cell if a zero data bit is to be transmitted. The low
WDNCLKEN signal blocks transmission of the mid-bit cell pulse. WDNCLKEN returns high before
the end of the bit cell, to enable the output clock pulse which marks the start of the next bit cell. If a
data one is to be transmitted, WDNCLKEN remains high in the middle of the bit cell, and the 100
nanosecond data pulse is transmitted in the middle of the bit cell.
Figure 2-59 is a large, detailed timing diagram which shows disk interface operations for a write data
operation. This description assumes that the read direct operation (for record header verification)
has already been performed.

2-157

Digital Systems Division

~~-----------------~

946262-9701

Refer back to the disk 1/ F start and read/write control logic, figure 2-48. The disk interface is
commanded to write mode (DSKWRTQ=l) by a special group 1 microinstruction. The operation is
initiated by a disk start transfer clock pulse (DSKSTRTCK-), decoded from a special group 0
microinstruction and strobed by MPCK-. The disk start transfer F / F sets on the trailing (rising) edge
of DSKSTR TCK-, releasing the constant reset from the disk start and write F / Fs.
The disk start F / F resynchronizes the operation to disk clock on the next rising (trailing) edge of
DCLK-. The write F / F sets one clock time later. The first disk data load (DISKDA TLD) pulse of
the operation is enabled in the interval between the rising edge of DST ARTQ and WRITEQ.
DISKDATLD loads the first data word into the serial/ parallel shift register. The first disk data load
pulse is a special case; the remaining DISKDATLD pulses are generated at 16-bit intervals when
CNTEQ 15 from the bit counter goes high.
The first data words are all zeros. They are written into the gap prior to the data record to provide
synchronization inputs to the disk drive read clock/ data separator circuits. The all-zeros data words
cause only clock pulses to be recorded on the disk. Timing loops in the controller microprogram
determine the duration of clock-only output.
The synchronization word, 006E 16 , is recorded immediately following the end of the gap. The last
eight bits represent the 6E synchronization character. The encoded bit stream which represents the
6E character is shown in the middle of the timing diagram.
As the last bit of the synchronization character is transmitted, the first data word is loaded into the
serial/ parallel register and unloaded from the FIFO.
Data transmission takes place in the sequence previously described, with the disk interface shifting a
word out of the FIFO every 16 disk clock times, and the processor initiating TILINE master read
cycles to supply FIFO input data.
When the record word count maintained by the CPEs expires, all the data words have been loaded
into the FIFO. The processor loads an all zeros data word with the CRC enable flag (bit 16) set, and
then another all zeros word with the stop flag (bit 18) set. These words stack up in the FIFO until the
disk interface transmits the iast word of the record. The CRC enable flag (CRCENFLAG) changes
the steering of the write data/CRC multiplexer and enables the CRC generator to shift out a 16-bit
check character. When the last bit of the CRC character is transmitted, the all-zeros word with the
stop flag is shifted out of the FIFO, and the stop flag is latched up in the disk write flag register. The
stop flag informs the CPEs that the last data word has been transmitted. The microprogram
terminates the operation with a disk clear pulse, changes DSK WR TQ to zero, and disables the write
gate, stopping the write operation at the disk drive.

2.12.1.8 Self-Test. A self-test capability built into the controller provides verification of controller
integrity and aids in troubleshooting. The self-test has two forms, short and long. The short self-test
verifies the read and write data paths, including the processor bus, FIFO, parallel/serial converter,
CRC generator/checker, sync character detection, direct register, and parts of the read and write
data I/O circuits. The long self-test performs all the short test checks, plus command timer and CPE
internal register checks. A status count is maintained as the self-test executes. If the test fails, the
status count may be used to determine how far the test executed before the failure.
The short self-test is performed each time a new controller operation is specified by control words
wo-W7. The long test is performed if the specified command is Store Registers (W 1, bits 5-7 =
000). The short self-test is also executed on power up or I/O reset, as part of the TILINE abort interrupt trap routine. For controller test purposes only, the long test jumper, J2, causes the controller
to execute the long test on power up or I/O reset. The long test jumper should not remain in place
when the controller is returned to normal service.

2-158

Digital Systems Division

~~9~~=U=2~-9~W~I______________________________________________________________________________________________________________
WRITE CLOCK GENERATION
AND CONTROL

TP

WOSCTST-

TP

WOSCSTOPWCLK

MICROINSTRUCTION

(5MHZ)

DIAGFAUL TQ-

SPECIAL GROUP 1

WRITE CLOCK DIVIDER F IF

DSKOSC

DECODER

o

5MHZ

p

DISK CLOCK
CRYSTAL
OSCILLATOR
~

(2.5 MHZ)

_ _..... CK

QI-.......~.....- - -...

TO DISK CLOCK
DISTRIBUTION
(WRITE ONLY)

WCLK

WCLKAQQ-

ENCODED CLOCK
WDNCLKAND DATA TO

RST1-

WRTDATOUT-

SELECTED DISK

DATA/CRC MUX
FROM
FIFO

WRITE DATA OUT F/F

BUFFER
WRTDATD

o

D

SERIAL/PARALLEL
WRTDATOUT-

SHIFT REGISTER
DCL

DATCLK

1-

CK

CRCPRES-

Q

TO TEST CIRCUIT
FOR LOADING TEST
MEMORY

15

(LSB)

I
I

I

I

I

I

I
I

I
I

I
I

I
I

I
I

I
I

I
I

I

I

I

I

I

I

I

I

I

,. • .. • .. + .. + + .. +.. • • .. ./

CRCDATOUT

PARDATOO
9401

(MSB)
CRCDATIN

V

RST1-

CRC
GEN/

PARDATOO-15 OUTPUTS

CHECKER

FOR READ OPERATION

DCLK

FROM
MICROINSTRUCTION

DSKWRTQ

SPECIAL GROUP 1
DECODER
FROM DISK

CRCENFLAG

WRITE FLAG

2282581

REGISTER

2-159/2-160

Digital Systems Division

200
NSEC

--M----.r
I
,

100
NSEC

SMHZ WRITE
CLOCK WCLK

DISK CLOCK
WCLKAQQ-,
DATCLK,
DCLK

()

WRITE DATA
PARDATOO
OR
CRCDATOUT,
WRTDATD

~

WRTDATOUT-

w/w4A

WRITE DATA AND
CLOCK ENABLE
WDNCLKEN

~

0

0

0

L~
0

NI

0

0

0

r

r-----,

0

0

'""'"
0'\

0

0

'""'"

,

~~~~C

0

~

~

_I

14
ENCODED
WRITE DATA
AND
CLOCK WDNCLK-

: 0 :

W

CLOCK

: 0:'

1

BI T CELL

400 ~SEC

W::~
-.I \.- ~~~C

l!.S~

o·

•

NOTES:

o

UNDETERM INED Ol~
IRRELEVANT LEVe:L

ce:

-Q)

WRI TE CLOCK PUl.SE
TO DRIVE

(B) 138646

Figure 2-58. Timing Diagram for Write Data and Clock Encoding

~_
946262-9701
Jd7~
_ _ _ _ __

Figure 2-60 is a simplified data flow diagram for self-test operations. The self-test operation is performed under control of the Z diagnostic test (ZDT) and subordinate routines in the controller
microprogram.
No data is transferred over the TILINE during the course of a self-test operation. Test data patterns
are supplied in the immediate operand field (ROM32-39) of the microinstruction and loaded into the
CPE via the K-bus.
Test write data is transferred over the processor bus and loaded into the FIFO input. FIFO output
data is converted to serial form and sent to the CRC generator and the write data logic. Instead of
being encoded and sent to the disk, the data is loaded into a TMS 3129 serial test memory.
After the simulated transmission into the test memory, the data is read back through part of the read
data buffers, and into the serial/ parallel shift register. The CRC character is checked during the read
operation. The data follows the normal read data path through the FIFO and onto the processor
bus. The CPE accepts the data and checks it against the previously transmitted values.
This closed-loop test verifies the integrity of most of the read and write data paths. It does not test
the encoding circuitry which converts write data into bit cell form, and it does not test the read data
buffer which converts data from bit cell form to NRZ form. It tests the disk clock drivers, but not the
disk clock generation circuits. Various data patterns (0000, FFFF, 5555, AAAA) are used in this
loop-back test to detect pattern sensitivity and stuck bits.
The short self-test also includes direct register read and write operations, to verify the ability of the
direct register to accept and store data.
A microprogram-controlled test clock supplies disk clock (DCLK, DCLK-, DCLK 1-, DATCLK)
during test operations. Special group I microinstructions control the test clock (TESTCLK-)
waveform. A diagnostic test subroutine, Z test clock, controls the on time and off time of the test
clock waveform.
The period of the test clock waveform is approximately 1.2 microseconds (833.33 KHz). This
corresponds to two microprocessor clock cycles with test clock on, and two cycles with test clock off.
Test clock is slower than the normal (2.5 MHz) read or write clock due to the speed limitations of the
TMS 3129 serial memory device.

Self-Test Logic. Refer to figure 2-54, which shows the read data and clock buffers, self-test logic,
and disk clock distribution. The TESTCLK- signal from the microinstruction special group 1
decoder/register replaces the read or write disk clock (DCLOCK-) as the source for disk clock
distribution.
For write test operations, the WRTDATOUT- signal from the write data encoding circuits is routed
through the read 2 F/F (RDATAQ) and stored in the TMS 3129 shift register memory. TESTCLKserves as the shift register clock.
During read test operations, the TESTMODEQ signal gates test data into the read 2 F /F again. This
time, the output of the read 2 F /F goes through the normal read data path, through the disk data in
F/F, and into the serial/parallel shift register.
If the controller microprogram detects a fault during self-test, it sets the diagnostic fault F/F, lights
the FAULT indicator, and inhibits distribution of normal read or write disk clock. The
DIAGFAULTQ- signal also holds the read 2 F/F in the reset state.

2-162

Digital Systems Division

~----------------------------~

946262-9701

DISK START
TRANSFER CLOCK
DSTRTCK-

NO CHANGE UNTIL NEXT READ
OR WRITE OPERATION

1 - - , ,-§S0

LJ---

SYNCHRONIZED
WITH MPCK-

READ/WRITE
OSKWRTQ

DSKWRTQ

1

-------L-

S

5 ,...,

0

S

r-------------------------------------------------~5r____~

DSTARTQ

DSTARTQ

0-----4

r-------~;_+t=

0

NO CHANGE UNTIL END
OF WRITE OPERATION
WRITEQ

I

0

DSKSTRQ

DSKSTRQ

WRITEQ

O-----~--_i

0

1
CRCENFLAG
CRCENFLAG

0

STOPFLAG

0

o

jr-----------------------~ff~------J

STOPFLAG 0

r----------------------------~jfl----------------------~ij~----~

DSKCLRDSKCLR-

o

0

CNTEQ15

0

_______

II

~~----~-------------~I~I----~

r - .I

I

DISKDATLD

0

~---------~---------4~--------~

0

I_
BITO
(MSB)

WRITE DATA/CRC
WRTDATD

________

r-----1.---,.---,

r---t

~,~

~f~--------------------------JJ

GAP WORDI - ALL ZEROS
FOR SYNCHRONIZATION

BIT14

r----l
f~
~~f----------------------------------~·

GAP
WORDZ • • •

51

BIT!

BITO
I

______

~r~

GAP
WORDN

) jI

8 LEADING ZEROS
OF SYNC WORD

'4

0

BIT1SI

8-BIT SYNCHRONIZATION CHARACTER (6E)16

'14

I )) I

0

0

~~

r--.

'~=-----------frr---J

U

'14
BIT'

J~

\I

WORD 2 AND ALL
SUBSEQUENT WORDS

u

DSKSHOUT-,
SHIFTOUT-

WDNClJ{-

~

**

0

....

'r

01
~IIg

01

Iilill

DATA
WORDN

0)

r
B~~ I

~,~---------------

'~f

~

•••

~~,------------

~~

r-------~(J_J- - -...

~tJt,

SYNCHRONIZED
WI TH MPCK-

** GAP
OF ALL ZEROS UNTIL GAP COUNT
EXPIRES, DSKCLR- ISSUED, WRITE GATE

CRC
BITO

I ,U

DISABLED.

"-

CRC WORD

B~Ir~ I

0

0

I j}

0

o

o

DISK CLOCK
WCL.KAQQ-,
DCU<, DATCU<

o

5MHZ
WCU<

o

WRITE CLOCK PULSE TO DRIVE

NOTES.

IRRELEVANT OR UNDETERMINED LEVEL

--a--

DATA- ONE IF PULSE PRESENT, ZERO IF ABSENT

* AS
ALL ZEROS DATA WORD LOADEO INTO SHIFT REGISTER
FLAG LOADED INTO DISK WRITE FLAG REGISTER
+:*
(B) 138649

STOP FLAG AND ALL ZEROS WORD IS LAST WORD
LOADED I NTO FIFO.
ALL ZEROS REPEATEDLY STROBED
FROM FIFO INTO SHIFT REGISTER DURING POST-RECORD GAP.

Figure 2-59. Detailed Timing for Write Data Operation

2-163/2-164

Digital Systems Division

\ICC

>-r~~M'C'N'
I
\

,

UI

l)J';,~

CLOCK
"fHIUII flON

------.

J.~

1

~~~~;

: : JIIMPUl

(11) I :jOh4/

Figure 2-60 . Controller Self-Test D ata Flow

~------~

946262·9701

The DIAGFAUL TQ- remains latched to prevent a faulty controller from writing data to a disk or
reading from the disk. The test mode and diagnostic fault signals also serve as controller status
inputs to the microprogram, via the ePE I-bus inputs.
To clear a diagnostic fault indication, a general reset (power reset or 1/0 reset) must be executed.
The self-test is executed as part of the reset recovery, so if a hard fault exists, it will be detected again
by the self-test, and readlwrite operation will be inhibited again.
Status Count and Status Update Strobe. The controller self-test uses ePE internal register R9 to
maintain a status count. The status count starts at zero, and is incremented as various parts of the
self-test are successfully completed. Thus the status count tracks the progress of the self-test.

When an error occurs, the test is aborted, but the status count is preserved. The count serves as a
,pointer to the last successfully executed test segment. The self-test microprogram flowcharts, at the
end of Appendix D, are annotated with status count values at the points where they are updated.
Any error discovered during self-test steers the microprogram to the standard self-test error
termination routine (Z error routine). This routine moves the status count from ePE register R9 to
R2, where it is available for reading over the TILINE to the 990 epu or the programmer panel
(address F804 if CPU base address is F8(0). The error routine also places the status count on the
processor bus so that it may be observed with a logic analyzer. It is also loaded into the disk address
register. Table 3-3 in Section 3 is a summary of the self-test status counts and their meanings.
The error routine loads all ones (FF) into the right byte of R 7 to identify a self-test error, and
terminates.
The status update strobe is issued each time the status count in R9 is updated. An otherwise unused
output, SPAREOUT1, from the microinstruction special group 1 decoder (logic drawing 937502,
sheet 13, PWB, or 2262102, sheet 13, fine line), is used as the status update strobe. The
SPAREOUTI signal, or its complement, may be used as a synchronization source for a logic
analyzer or oscilloscope.
Section 3 includes a detailed description of troubleshooting the disk controller with the self-tests.

2-166

Digital Systems Division

~ ____94_6_2_62_-9_7_0_1_______________________________________________

SECTION 3
MAINTENANCE
3.1 GENERAL
This section describes depot-level maintenance for the DS I 0 Disk Controller when operating in a
system with a IO-megabyte disk drive. Fault isolation procedures are given to the Ie, gate or signal
level. Detailed instructions for connecting the disk system to an operating 990 computer system, and
general procedures for performing diagnostic test procedures are given in the related publications
listed in the preface of this manual. Troubleshooting and repair procedures for the 10-megabyte,
disk-drive units are contained in the Peripheral Equipment Field Maintenance Manual, and in
Control Data® Cartridge Disk Drive Model 94274 Hardware Maintenance Manual. The program
description document for the diagnostic test is drawing number 2250113-9901.
3.2 MAINTENANCE PHILOSOPHY
Depot maintenance for the disk controller, in conjunction with the compatible disk drive units, is
based upon the use of a hot mock-up system or an operating 990 computer and the use of the selfdiagnostic capability of the controller board. Typical drive system components are listed in table 3-1.

The interconnection for a typical hot mock-up system, based on the use of a Model 990 computer
system, is shown in figure 3-1. In addition to the interface connector for the disk-drive units, the
controller also provides a test connection that can accommodate a state display, or more
sophisticated test equipment, such as a logic analyzer. A list of special test equipment is given in
table 3-5.
3.2.1 STATE DISPLAY. The state display is a locally-manufactured item originally designed as
factory test equipment. This state display is useful in troubleshooting and fault isolation. Local
manufacture details are given in figures 3-2 and 3-3. Figure 3-2 is an illustration of typical front panel
controls and indicators, and figure 3-3 provides a logic diagram of the unit. Figure 3-4 shows the
interconnecting wiring from the test connector of the disk controller to the state display, along with
signal names used in associated test procedures.

Table 3-1. System Components for Disk Controller and to-Megabyte Disk Drive
Disk Drive System Components

Part Number

IO-Megabyte Disk Drive
50-Wire Cable
40- Wire Cable
Cable Adapter Board

937513-00XX
937516-0001
937515-0001
937510-000 1

Table 3-2. List of Special Test Equipment and Documentation
Equipment

Part Number

975170-0001
937507-0001
Table 3-1
974846-0001

Double-Slot Extender Board
Scratch Cartridge
Drive System Components
State Display

3-1

Digital Systems Division

~~

. "'\ ~<:~

i~ .~'

~ ___9_4_62_6~"~~~~_'_;1______________________________________________
~

.~

Table 3-2. List of Special Test Equipment and Documentation (Continued)
Equipment

Part Number

Logic Analyzer

Hewlett-Packard Type 1600A
or equivalent
Tektronix Model 475
or equivalent

Dual Trace Oscilloscope
Diagnostics (under DOCS)
Cassette
Operating Procedure
Program Description
. Fiche Kit (Depot)
OSlO PO, Linked Test

2250113-0001
2250113-9920
2250113-9901
2250113-0009
2250113-1006

(OP)
(PO)
(SP)
(FLO)

Documentation

Model 990 Computer Family Maintenance
Drawings, Volume IV, Peripherals
Logic Diagram, 10-Megabyte
Disk Controller
Model 990 Computer Peripheral
Equipment Maintenance Manual
Control Data® Cartridge Disk Drive
Model 9427H Hardware Maintenance
Manual

945421-9704
937502-0001 (PWB)
2262102 (fine line)
945419-9701
937517 -9701

NOTE
U G06 is the standard test connector provided on the disk controllers
and is wired as shown in figure 3-4.
The state display facilitates gate-level troubleshooting of the controller in conjunction with TILINE
interface controls, disk drive unit controls, and internal functions of the controller. The state board
can provide the following functions:

•

Clock stop

•
•
•

Clock run
Single step clock

•

Loop on breakpoint.

Locate breakpoint

The state display is connected to three clock functions of the controller:
•

MPCKMNT is synchronous and simultaneous with the controller master clock (MPCK-)

•

CLKT2- is delayed 20 nanoseconds from the master clock

•

CLKRUN can stop the operation of the controller clock at any desired state by
manipUlation of the state display control switches.

3-2

Digital Systems Division

~----------------------------~

946262-9701

990
MAI:-.ITENANCE
UNIT

I

-...-------- -------- - - - - - -

I

I

L ___ .J

r

I

.---,I
CASSETTE
T RANSPORT

I
I

I

PROGRAMMERS
PANEL
l/F BOARD

h

1

~~-------I

I

I
990/10
AU2
BOARD

I

944952

I

I
I

I

I

I
I

I

115 VAC.
50- 60HZ,
SINGLE PHASE

I
I
I
I

AU 1
BOARD

I
I

944932

I

r-

MEMORY
BOARD

945093-6

MAIN
SUPPLY

~~----~--

--,
I
I
I

I
I

I

I
I

I

STATE
DISPLAY
BOARD
959371-1

937510-1
P2

PI

I

I
I

r

r

990/1 0
MEMORY
EXPANDER
BOARD

DS10
DISK DRIVE

I

CABLE
ADAPTER

fERMINATOR~~

P8
>9

>A
>B
>C

>D
>E
>F
>10
>11

Part 2 consists of subtests >4 through >13.
3-30

Digital Systems Division

~~-----------------~

946262-9701

Subtest 4

This test issues seek commands to cylinders 0, 10, 20, 30, and 40 and checks the controller status,
register 7, to see if the idle and complete bits have been set. After each seek command is issued and
the correct status has been returned the attention interrupt mask for the unit under test is set. With
the controller idle this should cause an interrupt. Checks are made to ensure that an interrupt did
indeed occur, and then a restore command is issued.
Subtest 5
This subtest verifies that unformatted writes and reads can be done. A write unformatted specifying
16 words is issued to the disk, after which a read unformatted with interrupts enabled is issued also
specifying 16 words. The data written is compared with the data read. Any miscompares will
generate an error message. A total of ten writes and reads are issued, using this pattern: 0, >1111,
>2222, >4444, >8888, >5555, >AAAA, >3333, >CCCC, >6666, >9999, >7777, >EEEE, >BBBB,
>DDDD, >FFFF.
Sub test 6
This subtest verifies that the write format command can be done. A write format command is issued
to different tracks on the disk. After each write a read unformatted command is issued and the
format read is checked against the correct format. If any miscompares occur an error message will
be generated. Ten writes and reads are issued during this subtest.
Subtest 7
This subtest verifies that write and read data commands can be performed. This is done by formatting a cylinder, issuing a write data command specifying 16 words, issuing a read data command
specifying 16 words, and then comparing the data written with that read. Any miscompares that
occur will cause an error message to be printed. This sequence is looped on 32 times and issued to
different cylinders.
Subtest 7 also verifies the auto retry code on the controller. One track is formatted at one sector per
record and maximum word count. A write data command is issued to that track specifying one full
track of data for the word count. This write data command is timed so as to allow only one retry of
the command (the controller standard) on each sector. If the command is not finished within the
allowed time an error message is generated. This sequence is looped on for ten passes.
Sub test 8
Sub test 8 tests for the correct operation of the transfer inhibit bit. To check this, track 0 on the disk
is formatted with sectors per record = 1, word count = 4 and the data = 0000. An area in memory
in then initialized with the data >AAAA. A read command is issued to the disk with the transfer
inhibit bit set specifying the previously initialized memory area. The memory area is then checked to
ensure that it still contains >AAAA. If not, an error message is printed.
Subtest 9
Subtest 9 verifies that an ID header error (IE) can be generated and detected by the controller. To do
this, a write format command is issued to a track on the disk. A read unformatted command is
issued to obtain the header parameters. The test then changes each of the three words of the header
and the CRC one at a time, and, using an unformatted write command, replaces the good header information on the disk with the modified header values. The test then issues a write data command
using the good header information, which should cause an ID error. After the write data command
completes, the returned controller status is checked to see if an ID error was reported. If not, an
error message is printed.
3-31

Digital Systems Division

)}7,5\
_ _ _ _ __
~_
946262-9701
Subtest >A
Subtest >A verifies that a search error (SE) can be generated and detected by the controller. This is
done by issuing a write format command to a track specifying two sectors per record. A read data
command is then issued starting at sector one, where there is no header information. The controller
is then checked to verify that a search error was detected by the controller. After this, a write format
command is issued to the same track as before starting with sector 0, which will write over the
header information of sector O. A read data command is issued to sector 0 of the track. The controller is checked to verify that a search error was detected. If not, an error message will be printed.
Subtest >B
Subtest >B checks to ensure that a data error can be generated and detected by the controller. A
write format command is issued to a track on the disk specifying a word count of 80. Then an unformatted read is issued to the same track to get the header information. The returned word count, in
word 3 of the header information, is changed to a value of two. The new word count is used along
with the other header values to generate a new CRC character value. These are then written to the
disk using an unformatted write. The test then issues a read data command specifying a word count
of two. A CRC error should result and the DE bit should be set.
Sub test >C
Sub test >C verifies that a command time-out (CT) can be caused and that the controller can detect
its occurrence. This is done by issuing a read data command specifying a sector address equal to the
maximum address plus six. The controller is then checked to ensure that the CT bit is set. If not, an
error message will be printed.
Subtest >D
Subtest >D verifies that a seek incomplete (SI) error can be generated and that the SI bit will set
upon its occurrence. This is done by:

1,

Formatting the last track on the disk with the sectors per record = maximum and the
word count = 100 words.

2.

Doing a write to the last track with the word count

3.

Checking the controller and disk status. The controller status should be >A801. Disk
status should be >04XX where XX is an indeterminate value.

4.

After the write, issuing a restore to clear the disk.

=

101 words.

Subtest >E
Subtest >E verifies that no data will be transferred during a write operation with a word count = o.
It also verifies that the destination record of the write gets set to all zeros. This is done by issuing the
following commands:

=

1.

A write format command is issued to track 0 specifying sectors per record
count = 2.

2.

A write data command is issued with the word count = 0 and data initialized to >1234.

3.

A read data command is issued with a word count = 2. The data read back is checked to
ensure that it has all been set to zeros.

3-32

1 and word

Digital Systems Division

~------~

946262-9701

Subtest >F
Subtest >F checks for the correct operation of the idle bit. A state of 0 means the controller is busy,
and a state of 1 means the controller is idle. The check is made by issuing a write data command using the TILINE address in the memory address portion of the write command word. Since the controller should be busy while the write is being done, the most significant bit of the controller status
should be set to o. Use the following commands:
1.

Issue write format to track 0 with word count = 12.

2.

Issue a write data with the word count = 8 and the TILINE address equal to the address
of the controller.

3.

Issue a read data with a word count = 8. Check the most significant bit of the controller
status word. It should be O. If not, an error message will be generated.

Subtest >10
Subtest >10 verifies that a TILINE time-out can occur and that the controller can detect its occurrence. This is done by issuing a store registers command with an illegal memory address specification. As soon as the idle bit sets to aI, controller idle, the controller status is checked to confirm
that the TILINE time-out bit (TT) is set. If it is not set, an error message will be generated.
Subtest >11
Sub test >11 verifies that a rate error can occur and that the controller can detect its occurrence.
After issuing a write format command to a track, a read data command is issued. The timing is
deliberately thrown off during the read by moving data from a nonexistent memory location >800
times. The controller status is checked to see if the rate error bit (RE) is set. If not, an error message
is printed. The expected controller status = >A008.
This test is valid only on DSI0 controller boards of revision R or later. Boards before this time cannot generate predictable rate errors.
Subtest >12
Sub test >12 verifies that the disk drive can correctly switch heads from the maximum cylinder of
head 0 to cylinder 0 of head 1. First a write format command is issued specifying 1 sector per record
and a maximum word count. After this, a write data command is issued with a word count of
>4096, enough words to cause the controller to switch heads. After the write data command is completed, the controller status is inspected for a status of >C800. If this status is not detected, an error
message will be printed.
Subtest >13
Subtest >13 verifies that the controller can read successfully when it is forced to switch heads and
cylinders. Use the following commands:
1.

Issue a write format command to cylinder >FF, head 0, last sector, with a word count = 10.

2.

Issue a write format command to cylinder >100, head 1, beginning with sector 0, with a
word count = 10.

3-33

Digital Systems Division

~

946262-9701

-----------------------------------------------------------------------= 20.

3.

Issue a write data command to cylinder >FF, head 0, last sector, with a word count
Use various data.

4.

Issue a read data command to cylinder >FF, head 0, last sector, with a word count = 20.

5.

Compare the data written with the data read. If any miscompares are found, issue an
error message.

3.7.2.3 Part 3 - Disk Addressing Test. Part 3 of the diagnostic checks the controller's and disk's
ability to address every record on a track and every track on the disk. Part 3 is composed of subtests
>14 through >16.
Sub test >14
Subtest >14 verifies that the controller can address all of the sectors on one track correctly. To do
this it goes through the following sequence:
1.

Issues a write format command to track 0 with sectors per record = 1 and word count = 8.

2.

Issues a write data command specifying eight words of data to each sector on the track.
The write is done in reverse sector order, with the last sector written first and the sector
address decremented to O. This is done so that if a write modifies the next sector, the
following write will not cover up the error. The data word used is the number of sectors
per record and sector address. After this, a read data command is issued and the data read
is checked against what was written. The read starts at the first sector on track O.

3.

Checks the controller for improper sector selection in the disk drive or an incorrect cartridge. This is done by issuing a write unformatted command to sector >15, the maximum
sector number plus one. The controller status register is examined to see if the CT error bit
has been set. If not, an error message is printed.

Subtest >15
Subtest >15 verifies that the controller can address every track on the disk. To do this it goes
through the following sequence:

=

Formats the whole disk with sectors per record

2.

Issues a write data command specifying eight words to the first record on each track. The
data is equal to the cylinder address.

3.

Issues a read data command and compares the data read to the data written. In reading
the data back, the test starts at the middle cylinder, then increments by one and
decrements by two, increments by three and decrements by four, etc., until all cylinders
are read.

4.

Performs 2000 random read data commands on the disk. The controller is checked to see
that each command completes successfully. If not, an error message is printed.

3-34

1 and words per record

=

1.

8.

Digital Systems Division

Jd7~
_ _ _ _ __
~_
946262-9701
Suhtest >16
Subtest >16 verifies that the controller can do writes and reads with variable sectors per record and
auto increments. To do this it goes through the following sequence:
1.

Issues a write format command to the first 80 tracks of the disk with sectors per record =
x (where x goes from 1 to the maximum allowed) and the word count = 1 word per
record. The data used is the sectors per record value.

2.

Issues a read data command with the word count equal to >50 words, and checks the data
read. If any miscompares occur an error message is printed.

3.

Increments sectors per record count and reexecutes the test. This is done until the sectors
per record count = maximum.

3.7.2.4 Part 4 - Memory Addressing Test. Part 4 of the diagnostic tests the ability of the controller to address all of TILINE memory. At least 4K words of memory past the end of the
diagnostic must be available for the sub tests to run.
Part 4 consists of subtests >17 and >18.
Subtest >17
Subtest >17 tests the controller's ability to read and write to unmapped memory. Unmapped
memory includes every memory location from the end of the diagnostic to the end of memory or the
end of the first 32K block of memory, whichever comes first. All of this memory is used as the
read/write buffer for the tests. The test first verifies that there is at least 4K words of memory
available for its buffer. If a total of 4K words is not available then INSUFFICIENT MEMORY will
be printed and the subtest will be skipped. If sufficient memory is available then the address is
written as data into each buffer location. The whole buffer is then written to disk and the buffer is
cleared. The data is then read back from the disk into the buffer and each buffer location is checked
to verify that it contains its own address as data. If any miscompares occur an error message will be
printed.
Subtest >18
Subtest >18 verifies the controller's ability to read and write to memory locations in mapped
memory. If there is no mapped memory a message will be printed stating this and the sub test will be
skipped. The test first verifies that there is at least 4K words of memory available for its buffer. If
4K words are not available then INSUFFICIENT MEMORY will be printed and the sub test will be
skipped. If sufficient memory is available then the first >80 bytes of each 4K-word block of mapped
memory will be written to and read from. Every two words of data in each >80-byte block will contain the processor address and the mapped bias used by the processor to address the mapped buffer.
The block is then written to disk and the buffer is cleared. The data is then read back from disk to its
mapped buffer area and each data pair is checked to verify that it contains the correct address and
bias. All mapped memory is checked in this way. If any part of a 4K-word segment fails to initialize,
that 4K-word segment is skipped.

3-35

Digital Systems Division

~------~

946262-9701

3.7.2.5 Part 5 - Media Integrity Test. The media integrity test uses the eRe character to verify the
recording reliability of the disk using four different data patterns. Part 5 consists of subtest >19.
Subtest >19
Subtest >19 uses the eRe character to verify data written to the entire disk. It does this in the
following way:
1.

A write format command is issued to the entire disk with the sectors per record = maximum (1 record per track) and the word count = maximum.

2.

A read data command with the word count = 1 is done from each track. The word that is
read is checked and if a bit is bad anywhere on the track a status error should be reported
with the DE error bit set. If the data word that is read back is incorrect, the read is
executed ten times and the number of failures in ten tries is added to the data error count.
(It is not possible simply to read back all of the words from the disk and check them,
because it would take a very long buffer to accommodate the data.) The disk is formatted
and read four times with different data each time. The four data patterns used are 0000,
FFFF, AAAA, and 5555. When the disk is being formatted, each track gets a data pattern
different from that on the track before. The pattern of data used goes as follows:
Loop
1

2

Track

Data

0

0000

1
2
3
4

FFFF
AAAA
5555

Max
0
1
~
'"
3
4

3

Max
0
1
2
3
4

4

Max
0
1
2
3
4

()()()()

FFFF
AAAA
5555

0000
FFFF
AAAA
5555

0000
FFFF
AAAA

5555

0000
FFFF
AAAA
5555

Max

3-36

Digital Systems Division

~------:----~

946262-9701

3~ 7 ~Z~6 Part 6 - Interactive Write-Protect Test. Part 6 verifies that a power cycle of both the computer and the disk unit will not cause the data on the disk to be modified. Part 6 also tests the writeprotect function of the drive. Because Part 6 requires the operator's intervention, there are no verbs
to loop on in it. Part 6 consists of subtest >IA.

Subtest >lA
Subtest >IA uses the data written during Part 5 to verify that a power cycle will not modify data on
the disk. Because of this it is necessary to execute Part 5 before executing this subtest. When the test
starts execution it asks the operator if Part 5 (subtest >19) has been run. If the operator enters a 0
(no) a message will be output asking him to run Part 5. If a 1 (yes) is entered the test will output a
message asking if the power has been cycled. If the answer is 0 (no) the test will output a message
telling the operator to cycle power. To do so, the operator does the following:
1.

Turn off power to the computer.

2.

Turn off power to the disk.

3.

Turn power on to the disk.

4.

Turn power on to the computer.

If the answer is 1 (yes), the test verifies that the data on the disk has not been modified by the power
cycle.

NOTE
When the question asking if the system power has been cycled is
answered with 0, the computer should go into an idle state. If the
operator does not want to cycle the system's power, the operator can
get back to the DOCS verb decoder by depressing the HALT /SIE
button and then depressing the RUN button.
'This should cause the diagnostic to return to the verb decoder. The return will be signaled by the
prompt VERB?- being displayed on the I/O device.
Upon completion of the power cycle test the write-protect function of the disk drive is tested. This is
done by having the operator first put the drive in the write-protect mode. The diagnostic then attempts to write data out to the disk drive. The area where the write was issued is then read to see if it
has been modified. If the data on the disk has been modified then a error message is generated. If
not, the operator is asked to depress the write-protect switch again to put the drive in the read/write
mode. The controller is then checked to verify that the write-protect bit has been cleared and the
drive can be written to.
The messages that appear to the operator are:
WRITE-PROTECT THE DISK DRIVE CURRENTLY UNDER TEST.
HIT RETURN WHEN READY UNPROTECT THE DISK DRIVE CURRENTLY UNDER TEST, PUT IT IN
READ/WRITE MODE. HIT RETURN WHEN READY -

3-37

Digital Systems Division

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946262-9701

3.7.3 DIAGNOSTIC TEST INITIALIZA nON. Refer to the Model 990 Computer Diagnostics
Handbook for loading procedures.
NOTE
Before conducting the disk diagnostic test program, always install a
scratch disk cartridge in the drive and write protect the fixed disk if
user information or operating system is installed.
NOTE
Loading the diagnostic into the computer from the cassette tape
requires about seven minutes.
3.7.4 ERROR MESSAGES. All of the error messages contained within the DS10PD diagnostic are
explained in this section. When an error occurs in the execution of any part or subtest of the
diagnostic, an error message will be printed out, provided that the print error flag = 1.
The error message will be preceded by a line indicating the subtest number in which the error occurred. This line will print out for both part executions and subtest executions (for example:
ERROR IN SUBTEST #12).
The error in subtest line will end with the error number. The error number is a two-digit hexadecimal
number. The numbers do not run consecutively from part to part because of the format of the
number. The fIrst digit of the error number can be either 1-6 or the hexadecimal (hex) digit >C. The
fITst digit designates the part of the diagnostic generating the error message. The digit >C is used to
designate the common error-generating subroutines (the command issuer subroutine and the status
checker subroutine). The second digit designates the message number within the part represented by
the fITst digit. An error number of 42 represents the second error message in that list of error
messages unique to part 4.
Following the error message number will be the text of the error message. The error message will
generally list these three things:
1.

What was happening at the time of the error.

2.

The specific incident which caused the error to occur.

3.

The expected data and/or status and the received data and/or status condition.

3-38

Digital Systems Division

'i:Y
~------946262-9701

3.7.4.1 Part 1- Error Messages. The error messages that can be generated in Part 1 are as follows:
ERROR #

MESSAGE

>11

DID A WRITE AND READ OF ALL BITS IN THE CONTROLLER
REGISTERS. EXPECTED THE SAME DATA READ AS WAS
WRITTEN.

= XXXX
DATA WRITTEN = XXXX
DATA READ

CONTROLLER REGISTER (0-7)
>12

SET ALL UNIT SELECT LINES IN REG. 6 OF THE CONTROLLER
=0. EXPECTED THE OL AND NR BITS IN REG. 0 TO BE SET.
STATUS EXPECTED

>13

= XXXX

= XXXX

STATUS RETURNED

= XXXX

DID TWO READS OF THE CONTROLLER STATUS, REG. 7.
EXPECTED THE LOCKOUT BIT TO BE SET.
STATUS EXPECTED = XXXX

>15

STATUS RETURNED = XXXX

DID AN I/O RESET AND READ THE CONTROLLER STATUS,
REG. 7. EXPECTED THE IDLE, ERR AND AC BITS IN REG. 7 TO
BE SET.
STATUS EXPECTED

>14

= XX

STATUS RETURNED = XXXX

SELF-TEST ERROR
AFTER ISSUING A STORE REGISTERS COMMAND REG. 2 OF
THE CONTROLLER WAS CHECKED FOR THE SELF-TEST
RETURN STATUS.
STATUS EXPECTED

= XXXX

STATUS RETURNED = XXXX

(Consult paragraph 3.7.4.3 for status error definitions before continuing
the diagnostic.)
>16

STORE REGISTERS ERROR
DID A STORE REGISTERS COMMAND AND EXPECTED THE 3
WORDS RETURNED TO COMPARE WITH THE TABLE OF
KNOWN VALUES.
VALUE RETURNED

= XXXX VALUE EXPECTED = XXXX

INCORRECT VALUE IS WORD # XX
NOTE:
Store register values should equal:
>OFOO, >1430, >1198

3-39

Digital Systems Division

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946262-9701

3.7.4.2 Part 2 - Error Messages. The error messages that can occur in Part 2 are as follows:
ERROR #

MESSAGES

>20

WITH THE CONTROLLER IDLE BIT SET TO 1, (CONTROLLER
IDLE), THE ATTENTION INTERRUPT MASK BIT IN REG. 0 WAS
SET TO CAUSE AN INTERRUPT. THE EXPECTED INTERRUPT
WAS NOT RETURNED WITHIN 3 SECONDS.

>21

DID A WRITE TO AND THEN A READ FROM THE DISK USING 16
PATTERNS. EXPECTED THE PATTERNS READ TO COMPARE
WITH THE PATTERNS WRITTEN.
PATTERNS
READ
XXXX

>22

PATTERNS
WRITTEN
XXXX

DID A WRITE FORMAT TO AND THEN AN UNF. READ FROM A
SPECIFIED TRACK. EXPECTED THE FORMAT READ TO COMPARE WITH THE FORMAT WRITTEN.
DATA REC. XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
DATE EXP. XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

>23

RETRY LOOP ERROR
ISSUED A WRITE DATA COMMAND AND TIMED IT TO ALLOW
ONLY ONE RETRY (THE CONTROLLER STANDARD) PER
SECTOR. THE CONTROLLER WAS STILL RETRYING THE COMMAND WHEN IT TIMED OUT.

>24

A READ FROM AN AREA ON DISK CONTAINING ZEROS TO A
MEMORY AREA CONTAINING AAAA'S WAS ISSUED WITH THE
TRANSFER INHIBIT BIT SET. DID NOT EXPECT THE MEMORY
AREA TO BE CHANGED.
DATA
RECEIVED
XXXX

>25

DATA
WRITTEN
XXXX

ID WORD ERROR
AFTER CHANGING ID WORD #1 OF A TRACK WITH AN UNF.
WRITE DID A WRITE DATA TO THE SAME TRACK. THE
EXPECTED CONTROLLER STATUS WAS NOT RECEIVED.
R7 STATUS EXP = XXXX REC

>25

= XXXX

ID WORD ERROR
AFTER CHANGING ID WORD #2 OF A TRACK WITH AN UNF.
WRITE DID A WRITE DATA TO THE SAME TRACK. THE
EXPECTED CONTROLLER STATUS WAS NOT RECEIVED.
R7 STATUS EXP

= XXXX

3-40

REC

= XXXX

Digital Systems Division

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946262-9701
>25

ID WORD ERROR
AFTER CHANGING ID WORD #3 OF A TRACK WITH AN UNF.
WRITE DID A WRITE DATA TO THE SAME TRACK. THE
EXPECTED CONTROLLER STATUS WAS NOT RECEIVED.
R7 STATUS EXP = XXXX

>25

REC = XXXX

ID WORD ERROR
AFTER CHANGING THE HEADER CRC OF A TRACK WITH AN
UNF. WRITE DID A WRITE DATA TO THE SAME TRACK. THE
EXPECTED CONTROLLER STATUS 'VAS NOT RECEIVED.
R7 STATUS EXP = XXXX

REC = XXXX

NOTE:
The above 4 errors all share the same error number because they are all
ID errors. The error generating routines are all unique.
>26

SEARCH ERROR
DID A WRITE OVER THE SYNC CHARACTER WITH AN VNF.
WRITE AND THEN DID AN UNF. READ. THE EXPECTED CONTROLLER STATUS WAS NOT RECEIVED.
R7 STATUS EXP = XXXX

>27

DATA ERROR
AFTER CHANGING THE HEADER CRC OF A TRACK WITH AN
UNF. WRITE DID A READ DATA OF THE SAME TRACK. THE
EXPECTED CONTROLLER STATUS WAS NOT RECEIVED.
R7 STATUS EXP = XXXX

>28

REC = XXXX

COMMAND TIME ERROR
ISSUED A FORMATTED READ COMMAND WITH THE SECTOR
ADDRESS = MAX+6 TO CAUSE A COMMAND TIMER TIMEOUT. RECEIVED THE TIME-OUT BUT THE EXPECTED CONTROLLER STATUS WAS NOT RECEIVED.
R7 STATUS EXP

>29

REC = XXXX

= XXXX

REC

= XXXX

SEEK INCOMPLETE ERROR
AFTER FORMATTING THE LAST TRACK WITH SIR = MAX
AND THE WORD COUNT = 100 A WRITE PAST THIS ADDRESS
WAS ATTEMPTED AND THE EXPECTED STATUS WAS NOT
RECEIVED.
RO STATUS EXP = 04XX , REC = XXXX
R7 STATUS EXP = A80! , REC = XXXX

>2A

A WRITE COMMAND WITH A BYTE COUNT = 0 WAS ISSUED
TO VERIFY THAT NO DATA WOULD BE TRANSFERRED, BUT
DATA WAS WRITTEN TO THE DISK.

3-41

Digital Systems Division

"-V
~------946262-9701
>2B

BUSY FLAG SET ERROR
AFTER WRITING THE TPC REG. TO DISK AND READING BACK,
THE IDLE BIT IN REG. 7, MSB OF THE LAST WORD WRITTEN,
SHOULD NOT BE SET SINCE THE CONTROLLER WAS EXECUTING THE COMMAND WHEN REG. 7 WAS WRITTEN. REG.
7 (MSB SHOULD BE 0) WAS XXXX.

>2C

TILINE TIME-OUT ERROR
ISSUED A STORE REGISTERS COMMAND TO A NONEXISTENT
MEMORY LOCATION. THE EXPECTED CONTROLLER STATUS
WAS NOT RECEIVED.
R7 STATUS EXP = XXXX REC = XXXX

>2D

WRITE AMP RECOVERY ERROR
AFTER FORMATTING TRACKS 0 AND 1, A WRITE WAS ISSUED
SPECIFYING 4096 WORDS, WHICH SHOULD HAVE CAUSED
THE CONTROLLER TO SWITCH HEADS. THE EXPECTED CONTROLLER STATUS WAS NOT RECEIVED.
R7 STATUS EXP = XXXX REC

>2E

HEAD SWITCHING ERROR
AFTER FORMATTING MAX HEAD, CYL FF AND CLEARING
HEAD 0, CYL 100 A WRITE DATA AND A READ DATA COMMAND WERE ISSUED TO CAUSE THE CONTROLLER TO
SWITCH HEADS.
DATA
RECEIVED
XXXX

>2E

DATA
WRITTEN
XXXX

HEAD SWITCHING ERROR
AFTER FORMATTING MULTIPLE SECTORS AND TRACKS A
READ WAS DONE TO CAUSE THE CONTROLLER TO SWITCH
HEADS AND THE EXPECTED CONTROLLER STATUS WAS NOT
RECEIVED.
R7 STATUS EXP =XXXX

>2F

= XXXX

REC = XXXX

RATE ERROR
ISSUED A READ DATA COMMAND AND THEN CAUSED AN
INTENTIONAL ERROR IN THE TIMING. SHOULD HAVE
FORCED A RATE ERROR BUT THE EXPECTED CONTROLLER
STATUS WAS NOT RECEIVED.
R7 STATUS EXP = XXXX

3·42

REC

= XXXX

Digital Systems Division

946262-9701
~\_-----~

3.7.4.3 Part 3 - Error Messages. The Part 3 error messages are as follows:
ERROR #

MESSAGES

>31

DID A WRITE OF DATA PATTERN TO EACH SECTOR ON
TRACK O. EXPECTED DATA READ BACK TO COMPARE TO
DATA WRITTEN.
DATA
RECEIVED

xxxx
>32

= XXXX

REC = XXXX

DISK ADDRESSING ERROR
DID WRITE OF 8 WORDS OF DATA TO 1ST SECTOR OF EACH
TRACK USING THE CYL NUMBER AS DATA. EXPECTED THE
DATA READ TO COMPARE TO THE DATA WRITTEN.
DATA
RECEIVED
XXXX

>34

xxxx

ISSUED A WRITE COMMAND TO THE MAXIMUM SECTOR
NUMBER + 1, (21 DECIMAL), AND EXPECTED THE COMMAND
TO TIME OUT ON THE ILLEGAL SECTOR NUMBER. THE
EXPECTED CONTROLLER STATUS WAS NOT RECEIVED.
R7 STATUS EXP

>33

DATA
WRITTEN

DATA
WRITTEN
XXXX

DID A WRITE FORMAT AND THEN A READ DATA ON THE
FIRST 100 TRACKS INCREMENTING THE SECTOR/RECORD
VALUE FROM 1 TO >15. THE EXPECTED SEC/REC VALUE WAS
NOT RETURNED.
DATA
RECEIVED
XXXX

3-43

DATA
WRITTEN
XXXX

Digital Systems Division

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946262-9701

3.7.4.4 Part 4 - Error Messages. The error messages that can occur in Part 4 are as follows:
ERROR #

MESSAGE

>41

INSUFFICIENT MEMORY ERROR
NEED TO HAVE AT LEAST 4K WORDS OF MEMORY BEYOND
THE END OF THE DIAGNOSTIC TO RUN THIS TEST.

>42

MAPPED MEMORY SUBTEST TIPPED
DID WRITE OF ADDRESS THEN BIAS TO CONSECUTIVE
MEMORY LOCATIONS WITH MAP ENABLED. EXPECTED BIAS
VALUE TO BE CONVERTED TO THE ADDRESS OF THE
LOCATION.
ADDRESS

>43

= XXXX

BIAS VALUE

= XXXX

ERROR IN ADDRESSING UNMAPPED MEMORY
THE CONTROLLER IS SET UP TO READ AND WRITE EVERY
ADDRESS INTO ITSELF FROM THE END OF THE DIAGNOSTIC
TO THE END OF THE 1ST 32K BLOCK OF MEMORY. THIS
ADDRESS DID NOT CONTAIN ITS OWN ADDRESS AS DATA.
DATA
RECEIVED
XXXX

>44

DATA
WRITTEN
XXXX

ERROR IN ADDRESSING MAPPED MEMORY
THE CONTROLLER IS SET UP TO READ AND WRITE MAPPED
ADDRESSES FROM MEMORY. A COMPARE IS THEN MADE.
THE FOLLOWING ADDRESSES DID NOT COMPARE.
MAP ADDR = XXXX MAP BIAS = XXXX
TILINE ADDR = XXXXXX
EXP DATA = XXXX REC DATA = XXXX

3.7.4.5 Part 5 - Error Message. The error message for Part 5 is as follows:
ERROR #

MESSAGES

>51

MEDIA INTEGRITY ERROR
DID A WRITE FORMAT USING MAX SEC/REC AND MAX WORD
COUNT WHILE WRITING VARIABLE DATA PATTERNS. THEN
DID A READ TO VERIFY DATA INTEGRITY.

CYL
XXX

BAD TRACK LIST (IN
DATA
HEAD
WRITTEN
XX
XXXX

3-44

HEXADECIMAL)
DATA
# OF ERRORS
READ
IN >A RETRIES
XXXX
X

Digital Systems Division

"iY
~------946262-9701

3.7.4.6 Part 6 - Error Messages. The error messages in Part 6 are as follows:
ERROR #

MESSAGES

>61

DID A READ OF THE DATA PATTERNS WRITTEN DURING
PART 5 EXPECTING THE DATA READ TO COMPARE WITH
WHAT WAS WRITTEN BEFORE THE POWER CYCLE.
DATA
WRITTEN

XXXX
>62

DATA
READ
XXXX

CYL
ADDR
:XX:X

HEAD
ADDR
XX:

****WARNING****
THE DS10 CONTROLLER IS UNABLE TO SET THE WRITEPROTECT BIT, BIT 2, IN THE CONTROLLER STATUS REGISTER,
REG. O. THE DRIVE CANNOT BE WRITE-PROTECTED.

>63

ISSUED A WRITE AND THEN A READ DATA COMMAND TO
THE UNIT UNDER TEST WITH THE WRITE-PROTECT BIT SET
IN THE CONTROLLER STATUS REGISTER. THE DRIVE WAS
WRITE-PROTECTED, DATA ON THE DISK WAS MODIFIED.
THE DISK IS NOT PROTECTED WITH THE WRITE-PROTECT
SWITCH SET.

>64

****WARNING****
THE WRITE-PROTECT BIT IN THE CONTROLLER STATUS
REGISTER CANNOT BE CLEARED.
THE DISK DRIVE CANNOT BE PUT INTO THE READ/WRITE
MODE.

3.7.4.7 Common Error Messages. The following are common error messages:
ERROR #

MESSAGES

>C1

AFTER ISSUING A COMMAND THE CONTROLLER FAILED TO
GO TO IDLE WITHIN 20 SECONDS.

>C2

UNEXPECTED DISK INTERRUPT AT LOCATION XXXX.

>C3

THE CONTROLLER HAS TIMED OUT WHILE WAITING FOR
THE IDLE BIT TO SET AFTER AN INTERRUPT WAS
GENERATED USING THE ATTENTION INTERRUPT MASK BITS.

>C4

**STATUS CHECKER ERROR **
CONTROLLER STATUS COMP=X

3-45

ERR=X

IDLE=X

Digital Systems Division

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946262-9701

3.7.5 SYSTEM ERROR MESSAGE ANALYSIS. When the diagnostic test program detects a fault
and reports this fault as a printout, the printed error message should be carefully analyzed for information that will provide a key to the problem and indicate a direction toward fault isolation. There
are two basic types of error messages generated by the diagnostic test program. One is a specific
error generated by a specific test condition and the other is a general error message created when an
error occurs which does not fall into the same area being tested by the diagnostic.
After a fault has been reported by the diagnostic test program, the procedure is to analyze the
reported error message, set up a scoping loop, and proceed to isolate the fault. Faults can be
classified into various types of failures, which can be associated with specific logic sections of the
controller. In the following paragraphs, the faults are described and what to look for and where to
trace in the logic is explained.
3.7.5.1 TILINE Time-out Error (System TILINE Time-out). A system TILINE time-out error
message can be caused by any failure of controls or signals between the computer TILINE and the
associated circuits on the controller. An example of a TILINE time-out error message is shown
below:
TILINE TIMEOUT
Work Pointer PC And Status At Time Of Error
WP=lB38 PC=lB72 ST=240F
NOTE
This type of TILINE timeout error message has nothing to do with a
TILINE timeout reported by the controller in status register 7 (W7).
The message reported in W7 is due either to a wrong address specified
by a read or write operation or to a malfunction of the master part of
the controller. This type of error will be considered later.
The first step is to find out what instruction caused the error. With the aid of a diagnostic listing,
identify the previous legitimate opcode before the instruction identified by PC printed out in the
error message.
This is not necessarily the previous address, because the previous instruction may be a two- or threeword instruction or the instruction may have caused a branch. After the instruction has been located
(it must be a memory reference instruction), the next step is to compute the effective address. This
should be done by using WP and the opcode of the instruction. Two situations may occur: either the
address points to a nonavailable memory location, or an address points to one of the eight controlword addresses in the controller.

Address Points To A Nonavailable Memory Location. If the address points to a nonavailable
location, then the diagnostic has been altered. There is no reason that the diagnostic would be
modified if all the other components of the system (memory, AU boards, etc.) work properly, unless
a previous read operation of the controller has deposited some words in an area where the diagnostic
resides. Unless there is some doubt about the system, the fault is due to the controller.
I.

Turn the computer off and unplug the controller.

2.

Check TLADROO- through TLADR14- for shorts to GND and VCC or for open
connections.

3.

Plug the controller board back into the extender board and turn the computer on.

3-46

Digital Systems Division

~
o

VI

946262-9701

-------------------------------------------------------------------------4.

Reload the diagnostic.
CAUTION
After the diagnostic has been loaded, DO NOT run any parts of EO
through E6 because the program maybe altered in the same way as
the previous case when the error was reported.

5.

Be sure a scratch disk is installed and is ready to be activated.

6.

Set the following command sequence in an available area of memory (for example, at
address 8000) using the MM verb:
Memory Address

Data

8000
8002
8004
8006
8008
800A
800C
800E
8100

0000
0100
0100
0000
0060
8100
0400
0000
FOFO

This is a write format command of >30 words.
7.

Loop on this command and check the TILINE interface signals as per figure 3-8. (Use the
logic diagrams to locate the signal lines on the board.) At the question: CHECK
STATUS?, respond with a O.

8.

Stop the cycling of the command by depressing the space bar on the 733 ASR.

9.

Set the following command in an available area of memory:
Memory Address

Data

8010
8012
8014
8016
8018
801A
801C
801E

0000
0200
0100
0000
0060
8200
0400
0000

...

This is a READ command and will be used to read the records previously written in step 6.
10.

Loop on this command (with 0 answer at the CHECK ST? question) and check the
TILINE interface signals as per figure 3-9. (Use the logic diagrams in order to localize the
signal lines on the controller board.)

If the address TILINE control signals do not show any abnormality, then the MeV address lines must be verified. This can be done by using a logic analyzer or state board and
setting the breakpoint to 027. Ensure that the controller sequences through the idle state
in the proper sequence.
3-47

Digital Systems Division

-

AT MASTER

..

NSEC

.-

(I-'-,

TLGO(T)

~120

\

TLTM(R)

(4)

~

! '-- ----

!fe-/

*TLREAD
(T)
*TLADR(T)

~

If

VALID

TLDAT

r\

(R)

-

~ 1 • 5~S

(R)

\~~

TLTM-

TLREAD

~

..

----

ERROR

---

AT SLAVE
TLGO-

--- ~_~I

\- ---

(R)

~

1----

I

VALID

TLMER-

--

\\....

(T)

~120
NSEC

~

'~ I

'----

If

~-

(R)
TLADR(R)
**TLDAT-

"- VALID

\

'---

I

VALID

(T)
**TLMER-

~-

(T) \ ..

o

ERROR

r '-. ~-I-"

---

NOTES:

I

NUMBERS IN PARENTHESES DENOTE TIME PERIODS REFERENCED IN TEXT.
(TILINE DELAY IS EXAGGERATED
FOR CLAR I TY)
(T) '" TRANSM ITTED (R) -'" RECE I VED
*'tLREAD AND TLADR- MUST BE STABLE AT THE TIME (OR BEFORE) TLGO-IS ASSERTED
**TLDAT- AND TLMER- MUST BE STABLE AT THE TIME (OR BEFORE) TLTM- IS ASSERTED

--

<9:
Q)

(A) 133123

Figure 3-8. TILINE Master to Slave Read Cycle Timing Diagram

~------~

946262-9701

I~

_AT MASTER

:::~~
TLREAD

TLADR-

~

..

..... __ ......

IA ........ """...

."

''1 _ . .I~'AI 1"""'-1.-.

t:"

+~"."~"v.~+1~: t:~ T~~ ~ :~-f:.-

m:'
I

(R)

vcr

---:\
(T)I,

V

I
--X

I

I,

~

I

VALID

I
I

I
I

~~ _I

i

V
1
V

VALID

~

,/& -: -

I
I

1

(T)
TLDAT-

..... _ •• _._...

i

~'\.. _1___

1
X\..

TLMER-

I

_1___
I

AT SLAVE
TLGO(R)

I

TLTM-

I~

I

I.
1

TLREAD
(R)

V
I
V
1
V
1

1\
I

TLADR(R)

~

VALID

I

TLDAT(R)
TLMER-

1\
1

VALID

I '--

~

I

I

I
(T)

.~

TRANSM ITTED}

(R)

c=

RECEIVED

TD

=- TILINE TRANSM ISS ION

WITH RESPECT
TO COMPUTER

DELAY (EXAGGERATED
FOR CLAR ITY)
(A) 1286558

Figure 3-9. TILINE Write Cycle Timing

Address Points To One Of The Eight Controller Addresses. In this case, the failure is due to the
slave part of the controller. First, be sure the DIP switches are correctly set for the proper TILINE
address of the controller, as shown in Appendix A. After checking the DIP switch settings, isolate
the fault, performing the following general steps:

1.

Turn the computer off.

2.

Turn the computer on again.

3.

Try to read the eight slave registers of the controller from the front panel. These should be
as shown in table 3-6.

3-49

Digital Systems Division

946262-9701
J2n5\ _
_ _ _ _ __
~

After the last reading (location F80E). depress the MOO switch on the computer front
panel again. (Read location F80E second time.) This time the content must be A900. If the
readings do not correspond, perform the following steps:
a.

Be sure the controller is looping on the idle loop by performing in step 10 in the
paragraph titled Address Points to a Nona va ila b Ie Memory Location.

b.

Check the PROCNT16 signal on MIl (PWB) pin 1 or UDK061 (fine line) pin 5.

c.

Verify SLXFR signal on MIl (PWB) pin 2 or UDK061 (fine line) pin 4.

d.

Enter the following short program (test loop 1) from the front panel switches:
Memory Address
8000
8002
8004
8006

Data

Comments

C050
lOFE
F80E
9000

Move Wo-W2
Jump back one
WO
W2

e.

Then enter 8000 into PC, 8004 into WP.

f.

Depress RUN. Loop 1 continually reads disk control and status register R 7 from
address F80E.

Table 3-6. Controller Slave Register Contents After Power Reset
Memory Address

Displayed Data

F800

0000
0000

2
4

g.

FFOO

6
8
A
C

XXXX
XXXX
XXXX

E

AlOO
XXXX - irrelevant (can be any data)

xxx x

Check the following signals:
• TLADROO- through TLADR19- on A05, C03, E03, C04, E04, COl, E02, E01, and
C02 (PWB) or UAE039, UCC036, UBE036, UCC051, UBE051, UCCOO6,
UBE021, UBEOO6, and UCC021 (fine line).
• T -type inputs on DM8136 (A02, A03, A04, PWB, or UAE050, UAE083 ,
UAE028, fine line) to check the proper ground or VCC level.
• TLGO on M09 (PWB) or UBK072 (fine line), pin 1.
• SLGODLY on M09 (PWB) or UBK072 (fine line), pin 3.
• Check SLADOK on M09 (PWB) or UBK072 (fine line), pin 2.
3-50

Digital Systems Division

~

946262-9701

•
•
•
•
•
•
•
•
h.

SLXFR on 1\111 (PWB) pin 2 or UDK072 (fine line) pin 4.
SLVA- on GIl (PWB) or UDE072 (fine line), pin 9.
SL VACT on 112 (PWB) or UDK039 (fine line), pin 8.
TRAP- on H12 (PWB) or UDK072 (fine line), pin 8.
ENSPEC- on 111 (PWB) or UEE050 (fine line), pin 15.
TLDATEN on J08 (PWB) or UDK050 (fine line), pin 4.
SLTM on B09 (PWB) or UBE116 (fine line), pin 4.
TLTM- on PI (connector) pin 20.

If the readings of the slaves match table 3-6, then write the word 8800 (from the front
panel) in all eight locations. Check the written data. If one or more locations failed
to properly load the word 8800, stop the program. Then, successively modify the
location 1004 with one of the following values: F88C, F88A, F888, F886, F884,
F882, F880. For each of the previous values, run the program and check the above
signals.

3.7.5.2 Unexpected Interrupt Level Error Message. This error message might occur at the beginning of the PDT (while running part 0) or during the time when another program is running on the
system with the disk controller. An example of this type of error message is shown in figure 3-10.
NOTE
The interrupt level (09 as shown in figure 3-10) must be that assigned.
to the disk controller slot.

VERB ? - PART 0
UNEXPECTED INT LEVEL= 09
990/10 10 MEG TEST
VERSION=XX/XX/XX
ENTER THE 733 INTERRUPT LEVEL DEFAULT-06
Figure 3-10. Unexpected Interrupt Level Error Message

This error message must not be confused with the UNEXPECTED INTERR UPT AT XXXX error
message.
In order to isolate this type of fault, perform the following general steps:
1.

Be sure the slave logic is working properly (can read from and write into controller slave
registers). If necessary, perform the fault isolation procedure explained in the previous
paragraph.

2.

From the computer front panel, enter the following short program (test loop 2):

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~

Memory Address

8000
8002
8004
8006

Data

Comments

C401

Move Wo-@W.
Jump back one

IOFE
F80E

9000

Then enter 8000 into PC, and "8004 into WP. Depress RUN.
Loop 2 continually loads register R 7 with 9000 16 at address F80E.
3.

Check the following signals:
•

PBTLDAT- on B05 (PWB) or UAK083 (fine line), pin 1.

•

TLINT- on G05 (PWB) or UBE072 (fine line), pin 2.

•

TRAP- on 110 (PWB) or UFK017 (fine line), pin 1.

•

READ- on 110 (PWB) or UFK017 (fine line), pin 5.

If all above signais are correct, then determine if the interrupt wire is properly connected on the 990
motherboard.

3.7.5.3 Status Error Message Analysis. The controller status error messages will be analyzed in this
paragraph. Figure 3-11 shows a typical status error message.
*STATUS ERROR
CONTROLLER STATUS COMP=X ERR=X IDLE=X
U.T.C. REG
DISK STAT COM SA SIR RA CYLA BYTEC MEMAD SEL CO NT STAT
XXXX XXXX xx xx xx XXX X XXXX XXXXXX xx XXX X
COMMAND ISSUED
DISK STAT COM SA SIR RA CYLA BYTEC MEMAD SEL CONT STAT
XXXX XXXX xx XX XX XXXX XXXX XXXXXX XX XXXX

Figure 3-11. Typical Status Error Message

A status error does not necessarily indicate a controller malfunction. For example, detection of a
write protect from the disk will cause the controller to set the write protect status bit. Refer to the
formats of controls words WO and W7 to determine the status conditions which will cause the
controller to indicate a status error in R 7, bit 2. The messages which are printed by the PDT as a
result of a status error are useful in tracking down faults in the test system and in the controller.
Because this type of error message can occur as a result of malfunction of another system component
(as for example a bad disk cartridge media), it is important to make a careful analysis of the error
message in order to isolate the fault. In some situations, a message analysis must be combined with
further action in order to isolate the fault.

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There are eight fields in both Disk Registers and Command Issued rows. The data printed in each
field is a hexadecimal representation of the device register contents after the operation has been
completed (first row) and the data loaded into these registers at the time when the command was
issued (second row).
These eight fields are:
DISK STAT

Device register 0

COM

Bytes 5-7 of device register 6; head select 10-15

SECT
(SA, SIR, RA)

0-7 Sectors/ record
8-15 Start sector address

CYLINDER ADRS
(CYLA)

Device register 3

WORD COUNT
(BYTEC)

Device register 4

MEMAD
(MEMAD)

Device register 5 concatenated with bits 11-15 of device register 6 in
the MSB position of the field.

UNIT
(SEL)

Bits 4-7 of device register 6 (disk unit selected)

R7 STAT

Device register 7

For further analysis the meaning of each bit in the message is important. For reference see figure 1-12
(Control and Status Word Formats).

Status Register 7 Bit 15 Set. This error is reported when the controller detects the disk drive in an
abnormal condition to be used. Once this status is reported, the disk status in Register 0 bits 0-7
should be checked to determine what was the cause of the unit error status. The disk status should be
investigated according to the procedures listed in the following steps:
1.

Check to see if RO bit 0 is set. If this bit is set (1), then the drive has not been selected
properly or the status from the disk is not being seen or reported properly by the
controller. Check the following signals. If any are found to be faulty, signal trace through
the logics until the fault is isolated. Check the following signals on the controller.

•

SELECTB- on R06-2 (PWB) or UJJ017-6 (fine line)

•

SELECTA- on R03-6 (PWB) or UJJ017=2 (fine line)

•

DISKSEL- on R06-4 (PWB) or UJJ061-12 (fine line)
NOTE
These lines are decoded at the disk drive and are used to select a
particular drive and platter.

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Select BDrive

a

Select A-

a

I

a

I

a
a

Drive I

Disksel
a Fixed
I Removable
a Fixed
I Removable

If these signals are not of proper value, be sure that the proper unit select bits have been
entered into register 6 of the controller. If these signals are good, then the status lines from
the disk should be checked. Probe the following signals:

•

OFFLINE- on R08-I2 (PWB) or UJD006-8 (fine line) or FILERDY- on R08-I3
(PWB) or UJD006-9 (fine line)
If FILERDY - is a logic low, then the disk drive is reporting proper status and the
problem should then be signal traced through the logics until the fault is found. If
FILERDY is a logic high at this point, then the drive is reporting improper status.
Turn power off on the computer and disk drive and check resistances on this line
between the drive and controller, insuring that no shorts or opens exist in the cable or
between signals on the board.
A good way to trace the 0 FFLINE status through the logics is to put the controller
in the following loop:
Memory

8000
8002
8004
8006

Address

C050
IOFE

F800
8000

Then enter 8000 into PC, and 8004 into WP. Depress RUN.
This continually reads register RO and loads it into memory.

Check:

PBDSKSTA- on R05 pin 1 (PWB) or UJD028 pin 19 (fine line)
TLDATAOO- on A06 (PWB) or UAE06I (fine line) -6

2.

Once RO bit 0 is a logic 0 to show that the unit is selected, the other status bits can then be
checked for problems. The next status bit from the drive that should be checked is RO Bit
1, the ready status bit. Check the following:

•

RDYSRW- on R08 (PWB) or UJJ039 (fine line) -1

When the drive is selected and the unit is idle, the RDYSRW-line should be at a low logic
level. If this line is low but the status is still being reported bad, the same loop as given in
step I should be run and this signal then traced through the logics and out onto the
TILINE.

NOTE
If the state display is used to stop on breakpoints to check signal
levels, the system will have TILINE timeouts because the controller
will be stopped and not respond properly to the TILINE commands.

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-------------------------------------------------------------------------3.

If RO bit 2 (write protect on) is reported in the disk status register when the unit error
status bit 15 in register 7 is reported, the drive write protect switches should be checked.
These switches are active when depressed and the indicator is lighted. If this switch is ON,
it should be deactivated provided a scratch cartridge has been installed or the fixed disk
does not contain needed information. If the write protect status is being reported when it
has not been selected at the drive, the input line from the drive should be checked. Check
the following signals:
•

WP- on R05 (PWB) or UJJ050 (fine line) -8

•

PBDSKSTA- on R05 (PWB) or UJJ050 (fine line) -1

Signal trace the write protect (WP-) status line through the controller and out to the
TILINE until the problem is isolated. If a read command is being issued to the drive and
the write protect has been selected, the controller should not be reporting unit error status
in register 7. If this is happening, then check the write gate (WG-) at R02 pin 11 (PWB) or
UJD050 pin 8 (fine line). This signal should not be going to a logic low level; if it is, trace
the signal back through the logics until the fault is isolated.
4.

If RO bit three becomes set upon the issuing of a command, the controller will report a unit
error status in R7. If this should occur, the fault should be cleared by either depressing the
FAULT/RESET indicator/switch on the drive front panel or by issuing a RESTORE
command to the drive. If the indicator should fail to become extinguished, the problem
causing the fault is solid. The first thing that should be done is to unplug the controller to
drive cable and depress the FAULT/RESET indicator/ switch. If the light stays on, then
the fault condition is in the drive, but if the light becomes extinguished, then the fault
condition is caused by the controller. The controller should be reconnected to the drive
and a disk command should be set up in memory and issued (looped on) such that the fault
is obtained. An example of a command issued is shown below (use MM verb):
Address

Data

8000
8002
8004
8006
8008
800A
800C
800E
9000

0000
0010
0100
0060
0050
9000
0400
0000

FOFO

Comments
Disk status and interrupts
Disk command
Sectors per record/ record address
Cylinder address
Byte count
Memory address (data source)
Unit select (removable)
Controller status
Data to be written

Once this has been entered in memory, enter an @ on the keyboard to get back to verb
decoding. Then enter an LO command and answer with a "1" to the number of commands to be executed and a 0 for check status. The command should then be repeatedly
executed by the controller. The FAUL T lRESET indicator on the drive should now come
on and stay on and should not stay off when depressed. Once the failure mode has been
caused by the controller, the following signals on the controller should be checked:
•

WG- on R02-11 (PWB) or UJD050 (fine line) -8

•

EG- on R02-6 (PWB) or UJD050 (fine line) -3

•

RESTORE- on R04-6 (PWB) or UJJ061 (fine line) -6

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•

HDSEL- on R03-10 (PWB) or UJJ028 (fine line) -10

•

ADDSTB- on R02-3 (PWB) or UJDOSO (fine line) -11

•

FILERDY- on R08-13 (PWB) or UJDOO6 (fine line) -9

When checking these signals, ensure that the write and erase gate are turning on and off
within approximately 10 microseconds of each other. The restore signal should not be
active if commands other than a restore command are being executed. The head select line
should be stable and should not be toggling unless multiple commands with different head
selects are being executed. Sync the scope on ADDSTB- on channel one and look at signal
FILERDY- on channel two. FILERDY- should always be a logic low when ADDSTBgoes to a logic low (on negative edge).

If any of these signals does not meet the above criteria or is not of proper voltage level or
waveshape, then that signal should be traced through the controller until the fault is
isolated.
S.

If a unit error in register seven status was set and bit S in register 0 (RO) was set, then the
fault was the result of a seek incomplete or illegal cylinder address (address interlock)
being reported by the disk drive. To troubleshoot this type of failure, set up the same type
of command as shown in Step 4. It may be necessary to try various cylinder addresses
(address 8006) before a failure is reported. Once a command has been set up that will
report the error, the error status reporting should not be selected and the interface signals
to the drive should be checked. Check the following signals:
•

ADDSTB- on R02-3 (PWB) or UJDOSO (fine line) -11

•

ADDOOl- on R06-12 (PWB) or UJJ028 (fine line) -8

•

ADDOO2- on R06-8 (PWB) or UJJ061 (fine line) -4

•

ADD004- on R03-4 (PWB) or UJJ017 (fine line) -10

•

ADDOO8- on R04-8 (PWB) or UJJ028 (fine line) -12

•

ADD016- on R06-6 (PWB) or UJJ061 (fine line) -2

•

ADD032- on R03-8 (PWB) or UJJ017 (fine line) -4

•

ADD064- on R04-12 (PWB) or UJJ017 (fine line) -8

•

ADDI28- on R04-4 (PWB) or UJJ028 (fine line) -2

•

ADD2S6- on R04-10 (PWB) or UJJ028 (fine line) -4

When probing these signals, sync the scope on ADDSTB- and look at the various address
signals issued to the drive. These signals should be stable approximately SOO nanoseconds
before address strobe goes active and should remain for approximately SOO nanoseconds
after ADDSTB- is removed.
By changing the address at 8006 and reissuing the command, each of the address lines can
be made to toggle. Each bit location should be checked for proper level and to insure that
the proper address (same as in Memory Location 8006) is being loaded into the D-Bus and
is being presented to the drive.

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With channel one connected and synced on ADDSTB-, look at address acknowledge
(ADDACK-) and ensure that the trailing edge of strobe is not turned off until the address
acknowledge signal (ADDACK-) is received at P07-11 (PWB) or U11039-9 (fine line).
Status Register 7 Bit 14 Set. When this status is reported, the controller has failed to detect the sync
character within the sector that it started reading from. The controller is designed such that it will
automatically attempt one retry when a search error is reported. This means that the controller has
attempted to read that sector twice before reporting the error. The controller checks for this error by
reading the sector address and when the desired sector is found, the controller clears the sector
latch/flag and starts polling the READQ status and the sector status. If the controller finds that the
sector status has become active (sector pulse occurred) before the READQ status line, then a sector
frame was read without a sync character being detected, causing a search error to be reported.
This type of failure is best found by setting up a scoping loop and probing the associated control
signals. The disk should be formatted first to ensure that all sectors have proper information. Once
this has been done a write data command should be set up in memory as listed below:
Memory
Address

Data

8000
8002
8004
8006
8008
800A
800C
800E

0000
0300
0100
0000
0060
8300
0400
0000

Comments
Disk status
Write data 0200 RO data
1 sector/record
Cylinder address
Byte count
Write 8200 read
U nit select (fixed)
Controller status

Once this data has been entered in memory, initiate the command by issuing an IC command. Once
this has been completed, change to a READ DATA command by changing the contents of memory
location 8002 from 0200. The controller should execute the command, and the erroring status
should be reported. To find the fault, put the controller in a looping command LO at address 8000
with status checking not selected (0). The following signals on the controller should then be checked:
•

SECTORMRK- on P04-6 (PWB) or UHJ039-8 (fine line)

•

SECTORMRKQ- on J05-12 (PWB) or UFK039-12

If these two signals are always active, probe CLRSECIDX- on P04-1 (PWB) or UH1039-13 (fine
line). This signal should pulse low during the cycle to clear the latch. If it does not pulse low, trace
the signal until the fault is isolated. If the two signals listed above never went to the active (low)
state, then P04-1 (PWB) or UHJ039-13 (fine line) should be checked to insure that this signal is not
being held at a constant low level. If this signal is functional, P04-3 (PWB) or UH1039-11 (fine line)
(SECMRK) should be checked to insure the controller is receiving sector pulses from the disk drive
(20 per revolution).
If the above signals were all correct, then the following signals should be probed.

Sync the scope (channel 1 at P04-3, PWB, or UHJ039-11, fine line) and observe the following
signals.

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RG- on R03-2 (PWB) or UJJ028-10 (fine line) (active ~ 40 microseconds after sector pulse
for sector zero)
•

DSKSTRQ on Rll-9 (PWB) or UJJl16-9 (fine line) (becomes active after sector pulse on
sector address 0 for command given).

•

DSTARTQ- on Rll-6 (PWB) or UHJ094-6 (fine line)

•

STRTREAD- on RIO-6 (PWB) or UGEl16-12 (fine line) (goes positive after DSTARTQ
goes active).

•

SYNC6E- on N02-8 (PWB) or UJD083-8 (fine line) (check to see that this signal goes low
about 78 microseconds after the sector pulse for sector address 0).

If SYNC6E- is going negative (detecting the sync pattern from the disk) the following signals should
be traced:
•

SYNCQ on N12-9 (PWB) or UGE094-9 (fine line)

•

READQ- on L12-8 (PWB) or UHD094-8 (fine line)

•

READQQ- on J05-7 (PWB) or UFK039-7 (fine line)

If SYNC6E- did not go negative at the appropriate time, trace the data path back through the logics
ensuring that data is being received from the drive properly. Check the following signals:
•

PARDAT (9-15) on N02 pins 2-6, 11, and 12 (PWB) or UJD083 pins 1-4,6, 11, and 12
(fine line)

•

DISKDATIN- on N02-1 (PWB) or UJD083-5 (fine line)

If the parallel data is not passing data properly but DISKDATIN- seems to be toggling properly,
trace the data through the serial/parallel register (M03, M04, L04 and L03, PWB, or UHJ083,
UHD083, UFK061, and UFK083, fine line). If DISKDATIN is not toggling properly, check the
following signals:
•

RDATAQ on P03-5 (PWB) or UHDl16-9 (fine line)

•

RDATA on P09-6 (PWB) or UHJl16-8 (fine line)

•

RDATA- on Nll-8 (PWB) or UJDl16-6 (fine line)

•

RDB on Nll-12 (PWB) or UJDl16-2 (fine line)

•

RDA- on N11-10 (PWB) or UJDl16-4 (fine line)

•

DCLK on L07-14 (PWB) or UFKl16-14 (fine line)

Insure that the DCLK signal has a 400 nanosecond pulse width and an off time of approximately 100
nanoseconds.

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If the read data path is deemed to be working properly, then the problem may be that write data path
is faulty. Stop the command and by using an MM verb, change the command to a write format

command. Change data at memory location 8002 from 0200 to 0100. Once this has been done, put
the controller back in a looping command at address 8000 with status being ignored. Once this has
been done, probe the following signals and trace any problems found through the logic until the fault
is isolated.
•

WG- on R02-11 (PWB) or UJD050-8 (fine line) turns on after leading edge of sector pulse
and turns off after CRC has been written, which should occur before leading edge of the
next sector pulse.

•

EG- on R02-6 (PWB) or UJD050-3 (fine line) turns on and off within 10 microseconds of
WG-

•

WDNCLK- on R02-8 (PWB) or UJD050-6 (fine line)

•

WCLK on R02-9 (PWB) or UJD050-4 (fine line)

•

WDNCLKEN on N08-11 (PWB) or UJDI05-3 (fine line)

•

WRDATOUT- on N07-6 (PWB) or UHD116-6 (fine line)

•

WRTDATD on N06-7 (PWB) or UHDI05-7 (fine line)

•

PARDATOO on N06-5 (PWB) or UHDI05-5 (fine line)

If PARDATOO does not seem to be toggling properly, trace the data through serial/parallel register
looking for a bad bit.

NOTE
The sync character for the ID field will be written on the disk
approximately 78 microseconds after the leading edge of the sector
pulse. All zeros will be output prior to this time.
If the data is not being passed properly in the serial/parallel register, check the controlling inputs.
Check that DISKDATLD- on N09-6 (PWB) or UJD094-6 (fine line) is pulsing on every 16 disk clock
pulses. If not, trace this signal until reason is found. If the input data to this register is not charging,
probe the FIFO chips and assure that the input data lines are functioning properly and the
input/output control signals are functioning properly.

Status Register 7 Bit 13 Set. When this status bit becomes set, the controller is reporting the fact
that it had tried to execute a disk command but failed to complete the operation in the allotted time
(200 milliseconds). The first thing to do is to issue various commands to the disk until this failure is
reported. After this, a logic analyzer or state board should be used to find out where in the command the controller is hanging up. This is easily done by setting the breakpoint on the first address
of the command timer interrupt routine (040) and then looking to see what the previous address
was. Once this address is obtained, the function the controller was trying to execute at the time can
be found by looking back at the previous address. By finding this address in the microcode
flowcharts (Appendix D), the failing operation can be isolated and the circuitry of this operation can
be investigated by putting the controller in a scoping loop with status errors deleted.

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When the controller detects this type of error, it turns on the Red Fault LED on the top of the
controller board. When the controller services this interrupt and goes through the terminate routine,
the fault LED is turned off. After this status is reported, the operator should observe the fault LED.
If the LED remains lighted, it indicates that the controller failed to sequence through the terminate
routine properly or the command timer circuitry itself is bad. Check these signals:
•

CMDTMRDLY- on J07-7 (PWB) or UFEI05-7 (fine line)

•

FAULTQ- on Hll-ll (PWB) or UFK050-11 (fine line)

If CMDTMRDL Y- is active then check to see if the controller is in the idle loop. When in the idle
loop, the timer should be being cleared. Trace the signal back until the reason it is not being cleared
is found. If it is not in the idle loop, then the MCV address generation logic should be probed.

If the command timer and fault latch are cleared, but the status bit in R7 has been set, then the controller sequencing is probably functioning properly but one of the test conditions the controller is
waiting for (such as address acknowledge, FIFO available, sector address compare, etc.) did not
occur. By breakpointing on entry point of the interrupt and looking back at the previous address,
the problem circuitry should be identified and the fault isolation should just be a matter of tracing
these signals through the logics.
Status Register 7 Bit 12 Set. This type of an error is caused by the FIFO not being ready to receive or
give a word when required by the controlling signals. If the controller is writing data to the disk, it
must keep data in the FIFO so the drive can continually pull words out and shift them serially to the
disk. If the controller is taking words from the disk and putting them in memory, it must keep the
FIFO from becoming full and unable to accept the words in as they are ready, thereby losing information. The rate error detection flip-flop is set (causing trap to rate error interrupt routine on controller) by having a shift pulse when the ERRORSET (INRDY-IOUTRDY-) signal is active. To find
this type of pulse, put the controller in a read or write data loop and signal trace from the rate error
detection flip-flop back until the problem is isolated. Check the following signals:
•

TIMERRQ on N12-6 (PWB) or UOE094-6 (fine line)

•

ERRORSET on N12-2 (PWB) or UOE072-12 (fine line)

•

SHIFT on M05-9 (PWB) or UOE050-9 (fine line)

Check that a shift pulse is occurring every 15 DCLK pulses, once the disk operation is started. If
ERRORSET is always positive, then the FIFO is never coming ready. Trace OVTRDY - back if
doing write to disk and INRDY - if reading from the disk until the reason these signals are not going
ready is determined.

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Status Refdster 7 Bit 11 Set. This status indicates that the header information read from the disk
failed to ci'gree with the data for that command resident in the controller registers. Another possibility is that the CRC character for the three header words was wrong. The first thing is to do an
UNFORMATTED READ data command at the location where the ID error occurred. Set up the
. following command in memory using the erroring sector address and cylinder address as entries to
the command:
Address

Comments

Data
8000

0000

Disk status

8002

0400

Disk command (unformatted RD)

8004

OIXX

Erroring starting sector address

8006

XXXX

Error cylinder address

8008

0060

Byte count

800A

8100

Memory address

800e

OXOO

Unit select

800E

0000

Controller status

x-

these values are entered from the values given in the error status reporting.

Once this data has been entered, this command should be executed by entering an IC command after
verb and then depressing the space bar. The values of the header information read from the drive
should be read from memory and compared with the command entered. To do this, enter an MM at
address 8100 and depress the space bar three times. The CRT or ASR will then display the header
words read from the disk. The first word displayed is the track address where the heads are to be
positioned. This data should be the same as the information entered in register 3 of the controller
word (same as memory location 8006). If these two registers do not compare, the most likely cause of
the problem is a faulty cylinder address issued from the controller to the disk drive. If these values do
not compare, the value loaded in the disk address should be probed and any discrepancies should be
investigated.

NOTE
The header word containing the cylinder address will also have the
head select added to the word. The head select bits are given in bit
locations 0-4 and the cylinder address bits are given in bits 5-15.
If the cylinder bits compare, check that the proper head select was

read. Compare the word read from the disk (bit 4) with the head
select of the command issued. If they do not compare, probe the head
select bit to the drive.

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The second header word is the sector per record and sector starting
address. The second word read from disk should compare with the
value in register 2 of the command issued. If these words fail to compare, the sector address logic received from the disk and read by the
controller may be faulty. Probe SECTORB(l-16)- on R07 pins 8, 6,
4,2, and 17 (PWB) or UJD028 pins 8, 6, 4, and 2 and UJJ050 pin 17
(fine line) for proper pulses.
The third word contains the word count of the number of data words
stored. This value is not compared with controller register values.
If the words compare properly but the status bit still is reporting the

ID failure, the error would be reported from a CRC miscompare on
the header words. This type of error should be checked by carefully
observing the data path that feeds the CRC generator for both write
format and read data operations.

Status Register 7 Bit 10 Set. This status error tells that the controller was attempting a TILINE
master cycle but failed to complete the operation within the 10 microseconds allotted by the controller. Once the controller decides to do a master cycle it starts a 10 microsecond delay, during
which time the controller must acquire access to the TILINE and complete the cycle before the delay
value is reached. If the controller does not complete its operation in time, the time delay will cause
an internal interrupt, stop the master cycle, report the erroring status, and go back to the idle loop
to wait for another command. Either the TILINE handshake circuitry is failing or the TILINE
address output by the controller is an illegal value.
One of the most effective methods of troubleshooting this type of failure is to disable the TILINE
timer, causing the system to hang so that the signals can be probed. The fault causing the error
should be isolated quite easily. The timer is disabled by connecting a ground wire to B09 pin 15
(PWB) or UBE116-15 (fine line). Once this has been done, the MASTER CYCLE command that
had caused the error should be reissued. The controller should not be hung with the fault condition
causing the problem. The first thing that should be checked is the TILINE address that the controller is gating to the TILINE [TLADR(OO-19)-]e Ensure that a valid address is present on the
TILINE and that all lines are within logic voltage specifications. Once the addresses have been
verified to be good, the handshake interface signals should be probed. Check the following signals
and verify that they are correct:
•

TLGO- on A08-15 (PWB) or UAE094-15 (fine line)

•

TLREAD on A08-2 (PWB) or UAE094-2 (fine line)

•

TLTM- on B09-2 (PWB) or UBE116-2 (fine line)

•

TLAV on B09-7 (PWB) or UBE116-7 (fine line)

•

TLAK- on B09-9 (PWB) or UBE116-9 (fine line)

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In addition to these signals~ check the signals that can cause the TILINE circuitry to be disabled.
Insure that none of these signals are active.
•

TLIORES- on A08-7 (PWB) or UAE094-7 (fine line)

•

TLWAIT- on A08-9 (PWB) or UAE094-9 (fine line)

•

TLPRES- on L07-5 (PWB) or UFKl16-4 (fine line)

•

TLPFWP- on A10-1 (PWB) or UAK105-2 (fine line)

If all of these signals are of proper polarity and have good voltage levels, then the TLTM- signal
should be traced to find out why the controller has not relinquished the use of the TILINE. If all
signals are normal and the cycle completes normally, the ground should be taken off the delay circuit, a scoping loop should be set up, and the time delay of the TILINE timer should be checked.
Probe B12-8 (PWB) or UBE094-8 (fine line) and see that it goes low approximately every 10
microseconds when looping on a MASTER CYCLE command with status reporting deleted.
Status Register Bit 9 Set. This bit is set whenever the controller reads information from the disk and
the CRe generator has not gone to zero when the data and CRC character have been passed through
the CRC generator chip. This essentially means that the information written to the disk is not the
same as the data read back.
NOTE

Care must be taken when doing UNFORMATTED READ or
UNFORMATTED WRITE commands. If the exact number of
words for the UNFORMATTED READ are not the same as the
number of UNFORMATTED WRITE, a data error will result. Also,
if an UNFORMATTED READ is used to read data that has been
written with formatted data, a data error will result if more than three
words are specified (Header Data).
The first thing that should be done is to determine if the data paths are good or bad or if the CRC
generator/checker logic is at fault. This is best done by running test 5 (E5) of the PDT or by use of
WRITE/READ commands and looking at the data returned from the disk. If it is decided to check
the data by using the WRITE/READ commands, enter and issue the following commands after the
disk has been formatted:
Memory
Address

8000
8002
8004
8006
8008
800A

800C
800E

Data

Comments

0000
0500
0100
0000
0240
9000

Disk status
Unformatted write (400 unformatted read)
1 Sector I record
Cylinder 0
Maximum byte count
Starting address for data
Removable disk
Controller status

0400
0000

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After this command has been entered, the PDT should be put back to verb decoding mode by entering an @ on the keyboard. The data to be written should be entered by issuing an MI command at
address 9000. When it asks for data, an easily recognized pattern should be entered, such as AAAA
or 5555. Once this has been done, do an IC command at address SOOO to write this data out to the
disk. After this has been completed, change the data at S002 from 0500 to 0400 (Unformatted Read)
and the data at SOOA from 9000 to 9300. Clear the memory at location 9300 to all zeros, using an 1M
command. Now issue the command at SOOO and then check to see what the data transferred was.
The data at 9300 should now read what was written to disk (AAAA or 5555). Carefully observe the
data for any irregularities such as a bit stuck at one or zero. This type of failure seems to represent
something wrong with the parallel data path and not the serial disk interface portion. To
troubleshoot this, put the controller in the write mode and look at the data stream for the proper
data pattern. If the data pattern is not correct, trace the problem back until the problem is located.
If the write data path looks good, put the controller in a read cycle and trace the data coming from
the disk until the fault is found. If the data received from the disk was the same as the data sent to
the disk, but a data error was still reported, then the problem may be with the CRC generation logic.
Check the following signals:
•

CRCPRES- on M06-2 (PWB) or UGEI05-2 (fine line)

•

CRCENFLAG- on M06-10 (PWB) or UGEI05-10 (fine line)

•

CRCDATIN on M06-11 (PWB) or UGEI05-11 (fine line)

•

CRCDATOUT on M06-12 (PWB) or UGEI05-12 (fine line)

•

CRCERR on M06-13 (PWB) or UGEI05-13 (fine line)

If irregularities are found, replace the CRC chip at M06 (PWB) or UGEI05 (fine line).

Status Register 7 Bit 8 Set. This status indicates that the device sending data to the controller has
detected bad parity on this data. When this condition is reported to the disk controller, the controller
traps to an interrupt routine (command aborted) and reports this status in controller status register
7.
To troubleshoot this type of error the command being executed when this status is reported should
be put in memory and put in a looping command such that the controller signals can be probed.

Once this has been done the signal TLMER- on AIO pin 5 (PWB) or UAK094 pin 3 (fine line) should
be probed. If this signal never goes low but this status is reported, then the problem lies in the controller logic. This signal should be traced through the logic until the reason that this interrupt is
being reported is found. Ensure that an interrupt trap is being generated (INTTRAP on M12-3 on
the PWB or UFEOO6-6 on the fine line version of the disk controller). If this is being generated, it
should be a matter of tracing the signals until the fault is isolated. If this signal is not being produced
but this status is being reported, then the problem most likely is in the address sequencing logic.
Probe these signals to see why the microcode is sequencing through the interrupt.

Status Register 7 Bit 7 Set. This status is caused by the controller receiving a TLIORES-, TLPFWPor TLPRES- from the TILINE. Any of these signals will cause the controller to trap to interrupt 0
and set this status in register 7. All operations in progress are suspended at this time.
To troubleshoot this type of failure, the controller should be put in a scoping loop with status checking deleted. Once this has been done, probe F09-1 (PWB) or UEE094-1 (fine line) (TLPRES-) and
F09-11 (PWB) or UEE094-11 (fine line) (TLABORTL-) to see which one is going to a logic low level
causing the interrupt and error reporting status. It should now be just a matter of tracing the erroring signal back through the logics until the fault is isolated.

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946262-9701

Status Ref!ister 7 Bits 7-ij Set. This condition tens that the controller experienced a self-test
diagnostic ~failure while executing one of the commands. This type of failure is troubleshot by first
reading the status count in register 2 of the controller (enter F804 on front panel, depress MA and
then depress MD and record the value on front panel). After obtaining the status count, look at
status error printout and see what type of command was being executed (RI I) at the time of the
failure. If it was anything other than a store registers command, the controller was executing the
short diagnostic test when the error was encountered. Refer to table 3-3 (Status Error Decode) and
find the status error count (if short test failure) that corresponds to the long test count. Once the
corresponding long test count failure status count has been found, the troubleshooting procedure for
that status count given in section 3.6.6 should be followed until the fault is isolated.

NOTE
Because the status is updated after the successful completion of a test,
the procedure to follow in troubleshooting must be the next one from
the status count given. If status count was FF07, then follow
procedure for FF08 in section 3.6.6.

Special Diagnostic Error Messages. The PDT is composed of five major tests. The major tests are
broken down into smaller subtests that comprise the larger test. How each test is broken down and
what each test does is described in paragraph 3.7.2. Errors encountered during the executing of the
PDT that result from the failure of a unique test will result in a specific printout telling what test
failed. This will be accomplished by the following message being printed preceding the error
message:
ERROR IN TEST XXXX
The leftmost two bits will identify the major test that the failure had occurred in (E1-E5). The rightmost two bits identify which of the sub tests was being executed at the time of the error. By reading
the error message following this printout and by· reading the test description given in paragraph
3.7.2 for this failing test, a good idea of where the problem lies should have been obtained. If a stepby-step description is desired to troubleshoot this problem, the status error that closest resembles
this problem should be followed. By reading the description of the failing test, a command sequence
can many times be set up to duplicate the error. Once this has been done, a status error will be
reported and the detailed procedure for troubleshooting this type of problem can be followed.

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APPENDIX A
INSTALLATION DATA AND SWITCH SETTINGS

Digital Systems Division

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946262-9701

APPENDIX A
INSTALLATION DATA AND SWITCH SETTINGS
The following installation data has been reprinted from Model DS10 Cartridge Disk System
Installation and Operation, P / N 946261-970 I.
WARNING
This short-form tabulated data is not a substitute for the installation
and operation procedures in the installation and operation manual.
This information is supplied here solely for convenience in working
on, or with, a properly installed disk controller and drive.
A.I DISK CARTRIDGE INSTALLATION AND REMOVAL.
Before installing or removing a disk cartridge from the disk drive, be sure that the spindle of the disk
drive is not rotating. Do not attempt to install or remove a cartridge unless the brush indicator on
top of the disk drive is aligned with the black area as shown in figure A-I. A coin or screwdriver may
be used to make the alignment.

CAUTION
DO NOT REMOVE THE DISK
CARTRIDGE UNLESS THE
SLOT IS IN THE BLACK AREA.
A COIN MAY BE USED TO
MAKE THE ALIGNMENT.

~
~

BRUSH

INDICATOR

(A) 137259

Figure A-I. Brush Indicator

A.I.I Disk Cartridge Installation.

1. Raise cartridge access door (cabinet mount) or pull disk drive out of rack (rack mount).
NOTE
Power must be on and START I STOP lamp must be extinguished to
release lock on hold-down arms.
Refer to figure A-2 for the remainder of this procedure.
2.

Pull back hold-down arms.

3.

Set disk cartridge upright on a firm supportive surface.

A-I

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~- - - - - - 946262-9701

t
DUST COVER

COVER RELEASE
BUTTON

DISK CARTRIDGE
HOLD DOWN

J

ARM
COVER RELEASE
BUnON

l

DISK CARTRIDGE AND
DUST COVER IN PLACE

DUST COVER

(A) 137260

Figure A-2 , D'Isk Cartridge Installation

A-2

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946262-9701
J2n~
_

_ _ _ __
NOTE

There are two types of disk cartridge available. One type has a dust
cover lock that disengages when the slide button is moved to the left.
The other type disengages the lock when the slide button is pushed
towards center.
4.

Push disk cartridge cover release button to left, or towards the center depending on the
type cartridge, while lifting cartridge handle to separate dust cover and disk.

5.

Disengage dust cover from disk. Set cover aside.
CAUTION

Do not make abusive contact between disk and spindle. Ensure that
the read/write heads are fully retracted and the brushes are
completely out of the disk area. Remove any dust from magnetic
chuck.
6. Position head opening of disk toward rear of disk drive and place disk onto spindle hub.
7.

Rotate cartridge slowly back and forth until cartridge seats over spindle.

8. Turn handle down to seat cartridge.
9. Place dust cover (removed in step 5) open end down over cartridge.
10. Position hold-down arms over cartridge and dust cover.
11. Close cartridge access door (cabinet mount) or push disk drive into rack (rack mount).
A.1.2 Disk Cartridge Removal. Refer to figure A-2 for the following procedure.

1.

Press START/STOP switch and wait for START/STOP indicator to be extinguished.
CAUTION
If START/STOP indicator is still illuminated after 2-1/2 minutes
and brushes are not fully retracted contact the customer service
engineer.

2.

Raise cartridge access door (cabinet mount) or pull disk drive out of rack (rack mount).

3.

Pull back hold-down arms (arms will not move until cartridge rotation has stopped and
START / STOP indicator is extinguished).

4.

Remove cartridge dust cover.

5.

Push cartridge release blltton to left, or towards the center, while lifting cartridge up and
out of disk drive by handle.

6.

Place cartridge inside dust cover and hold down handle until a snap is heard indicating
that the cartridge and dust cover are locked together, or slide the release button away from
the center.

A-3,

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946262-9701

7.

Close cartridge access door (cabinet mount) or push disk drive back into rack (rack
mount).
NOTE
If no cartridge is to be installed for any long period of time, install the
dust cover received with the disk drive.

A.I.3 Removal of Disk Cartridge Following Power Failure or for Emergency. Removal of the disk
cartridge following power failure or in an emergency situation, should be performed only by the
customer service engineer.
I.

Wait approximately three minutes for cartridge to stop spinning.

2.

Raise cartridge access cover (cabinet mount) or pull disk drive out of rack (rack mount),

3.

Release pack locks by inserting a flat head screwdriver (or similar object) into hole on top
of pack lock (see figure A-3). Press solenoid plunger into solenoid and tilt pack lock.

4.

Pull back hold-down arms.

5.

Remove cartridge dust cover.

6.

Lift cartridge handle, hold cover release button to left, or towards the center, and lift
cartridge up and out of disk drive by handle.

7.

Place cartridge inside dust cover and fold down handle until a snap is heard indicating that
the cartridge and dust cover are locked together, or slide the release button away from
center.

8.

Close cartridge access door (cabinet mount) or push disk drive back into rack (rack
mount).

PUSH

INWAR~

PLUNGER. INTERLOCK
SOLENOID RELEASE

(A) 137261

Figure A-3. Cartridge Locks

A-4

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~------946262-9701

A.2 CHANGING DISK LOGICAL UNIT NUl\tIBER ASSIGNl\tIENTS.
The fixed disk in the primary (or only) disk drive is normally designated disk 0, and the cartridge is
designated disk I. The corresponding designations for the secondary disk drive are disks 2 and 3. A
jumper on the cable adapter board permits reversing the designations for a given disk drive.
The jumper plug is normally stored as shown in figure A-4. To reverse designations for disks 0 and 1,
remove the jumper plug and insert it to connect 11 and 13. To reverse designations for disks 2 and 3,
remove the jumper plug and insert it to connect 11 and 14.

0

0

lLJ

lLJ

X

X

IL.

IL.

(Y)

lZ
:J

IZ
:J

D

D

-

J4

J3

J1

J2
(A)143536

Figure A-4. Disk Designation Reversing Jumper on Cable Adapter

A.3 CHANGING TILINE SLAVE ADDRESS SWITCH SETTINGS.
The disk controller is assigned a block of eight TILINE word addresses, corresponding to command
words WO-W7 (and to internal registers RO-R7). The base (lowest) address of this group is set by an
on-board switch as shown in figure A-5 and table A-I.
TLADR 16 - - - - -.......
TLADR 13 - - _ - - .

(A) 137250

Figure A-S. TILINE Slave Address Switches

A-5

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946262-9701
Table A-I. TILINE Slave Address Switch Settings and Addresses

CPU

TILINE
Address
(Hex)

Address
(Hex)

1

2

3

4

FFCOO
FFC08
FFCIO
FFC18
FFC20
FFC28
FFC30
FFC38
FFC40
FFC48
FFC50
FFC58
FFC60
FFC68
FFC70
FFC78

F800
F810
F820
F830
F840
F850
F860
F870
F880
F890
F8AO
F8BO
F8CO
F8DO
F8EO
F8FO

Off
Off
On
On
Off
Off
On
On
Off
Off
On
On
Off
Off
On
On

Off
Off
Off
Off
On
On
On
On
Off
Off
Off
Off
On
On
On
On

Off
Off
Off
Off
Off
Off
Off
Off
On
On
On
On
On
On
On
On

Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
On
On

Switches

A.4 DISK CONTROLLER JUMPERS.
The standard setting of the disk controller on-board jumpers is shown in figure A-6. Note that the
drawing does not correspond to the physical jumper locations on the board. Refer to figures 1-2 and
1-3, the board photographs, for assistance in locating the jumpers.
1.

Jumper Jl has no current purpose. It grounds the unused SPAREINI-line if installed

(937502, sheet 11 or 2262102).
2.

Jumper J2 may be installed during unit test, to force the controller to execute the longform self-test on power up. It must be removed prior to normal operations. J2 grounds the

SPAREIN2-line, if installed (937502, sheet 11 or 2262102). Jumper sensing is part of the
controller microprogram.
3.

Jumpers J3, J4, J6 and J7 change the read/write data format from double frequency
(FM) to a higher density format. The jumpers must be in the positions shown for a 10
megabyte disk system (937502 or 2262102, sheet 19).

4.

Jumper J5 provides the capability to alter the write clock phase by 180 degrees, as a skew
compensation measure. No combination of cable lengths and cable capacity currently in
use has required that correction capability.

A-6

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946262-9701

o

o

D

D

J1
SPAREIN1

o o

D

J2
SPAREIN2

DIAGNOSTIC TEST

o
J4

J5

J7

o
J3

J6

NOTE:
THE LONG SELF-TEST JUMPER MAY BE
INSTALLED BETWEEN THE SPAREIN2 LINE
(J2) AND GROUND FOR TEST PURPOSES ONLY.
IT MUST BE REMOVED TO RESUME NORMAL
OPERATIONS.

PWB VERSION

UGG047

o

UKC041

o

D

0

UGC047

UKC038

SPAREINl

EJD135

EHJ128

EJD130

EHD127

EJG128

o

o

EJD133

EHJ 135

EHJ130

o

EJB128

EHJ132

SPAREIN2

o

D
EJD132

EHDf30

EJD127

EJB 133

EHJ127

FINE LINE PWB VERSION

(A)143534A

Figure A-6. Disk Controller Standard Jumpers

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A.5 DISK DRIVE OPTION SWITCH SETTINGS
The disk drive has option switches on five of the logic boards in the electronics card cage. These
switches must be set to a specific configuration to allow the disk drive to operate with the DSIO
cartridge disk controller. A label on the power supply cover identifies the switch locations and
mandatory settings. This label is reproduced in figure A-7.
The 110 board switches are accessible from the rear of a rack-mount drive if the cable adapter board
is removed. On a pedestal-mount drive, it will be necessary to remove the sheet-metal dust cover by
lifting it straight up. It may also be necessary to remove the cable clamp and to disconnect the flat
3M-type cables. Checking or changing the switch settings on the remaining boards will require
removal of the solid electronics cover plate and the card cage clamp and lid. The individual boards
must be removed from the cage to gain access to the switches.
,-

CONTROL
BOARD

SWITCH
DESIGNATOR

***

SI

SWITCH POSITION

DATA
RCVRY
BOARD

SERVO
BOARD
SI

SECTOR
BOARD

I/O BOARD

* S2*

S3

S4

S5

0

UNI INTt

0

0

0

0

0

UN2 INT2

1

1

0

0

0

UN3 INT3

0

**
I

0

1

0

UN4 IN14

0

1

0

S2

S3

SI

S2

S3

S4

SI

S2

S3

S4

0

**
0

0

0

1

0

1

1

0

1

0

0

0

1

0

0

1

0

I

0

0

1

I

1

0

1

0

1

2

1

1

o

I*t

3

1

1

0

I

4

****

0

1

0

5

0

1

0

6

0

1

0

7

1

1

0

8

0

1

**
0
0
**
**
0
1
**
0 *0*
**
1
1

SI

1

0

0

1

0

1

0

0

0

0

0

0

1

0

0

0

1

1

1

0

1

1

0

0

0

1

0

0

1

0

0

1

0

9

1

0

0

10

0

1

1

*
**

***

-* * * *
SERVO
S30

SI AND S2 - UN AND INT SWITCHES MUST HAVE SAME UNIT SELECTED
SWITCHES ARE REVERSED FOR 960/980 APPLICATIONS
I=ON O=OFF
CDC PN 75886537 OR 75297105 FOR 990,CDC PN 75881050 FOR 960/980

****

DATA RCVRY
S40

1/0

SECTOR
S30 S4D

c:::::J

c:J
oS3
oS2 SID
S2D
SID

S20

SID

.------.

,----,

S2D SID
S3D
S40 S5D

SPECIAL FOR 960/980

OSlO SWITCH SETTINGS
THIS UNIT SET FOR 990B 960/980

0

Figure A-7. OSlO Disk Drive Option Switch Settings

A-8

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APPENDIX B
PWB SIGNAL DICTIONARY

Digital Systems Division

y~------~

946262-9701

APPENDIX B

PWB SIGNAL DICTIONARY

937502
Signature

Sheet. N o.

Gate - Pin

Definitions

ACCDATEN

2

Cll-IO

Access data enable. Partially enables the
TLDATEN gate when access logic is in the device
access state (ACCESSOK- = 0) and TILINE terminate has not occurred.

ACCESSOK-

2

BII-3

TILINE access okay. During TILINE master
cycle, enables TILINE address drivers,
TLREAD, TLOO- drivers. For write operations,
also partially enables TILINE data line drivers.

ADDACK-

16

Disk Drive

Address acknowledge, from selected disk unit.
Acknowledges that the drive has accepted the
cylinder address supplied by the controller.

ADDACKQ

16

J5=5

Latched version of address acknowledge
(ADDACK), stored in I-bus input latch.

ADDSTB-

13

R2-3

Address strobe. Output which, when low, strobes
the cylinder address (ADDOOI- thru ADD256-)
into the selected disk drive.

ADDOOI-, 2-, 4-,
8-, 16-, 32-, 64-,
128-, 256-

14

R3, R4, R6

Cylinder address, to the selected disk unit.
Addresses 0-407 are valid.

BUSYLED-

13

65-6

Open-collector output that lights the BUSY
indicator when low. Controlled by BUSYQ-.

BUSYQ-

13

H 11-10

Controller busy. Output of microinstruction
decoder / register that indicates that the controller
is busy performing a command. Lights BUSY
indicator and enables busy indication for any
TILINE master read operation.

CARRY (0-6)-

12

C7, D7

Carry signals from carry look-ahead units to
mIcroprocessors.

CIL-

12

D8-I2

Carry input to left byte CPE array.

CLKEN

4

Fll-I

Clock enable. Retriggers microprocessor clock
cycle or in free-running mode when delay 3
expIres.

B-t

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937502
Sheet No.

Gate - Pin

Definitions

CLKINH

4

Fll-4

Clock inhibit. Disables microprocessor clock
generation during a TILINE master cycle.

CLKLED-

4

G5-8

Clock indicator. Open-collector verSIon of
CLKOFF that lights an LED indicator each time
the clock on latch sets.

CLKOFF

4

M7-6

Clock off. This signal which has the same period
as MPCK- is used in the development of microprocessor clock, MPCK-. It is also used as a
synchronizing term in clearing interrupt latches.
CLKOFF goes low coincident with the leading
(falling) edge of MPCK-. CLKOFF remains low
for 125 nanoseconds, then goes high for 175 nanoseconds (more if the clock waveform is extended
by a TI LINE master cycle).

CLKON

4

F8-6

Clock on. Latch output which activates the microprocessor clock generation cycle. The period is the
same as the period of MPCK-, and the high level
pulse width is 125 nanoseconds.

CLKRUN

4
18

R17-2
G6-II

Clock run. Pulled high except during single-step
control by an external tester.

CLKSTP-

8

FII-13

CPE clock stop. Disables CPE left and right byte
clocks when commanded by microinstruction bit
o or when a trap occurs. Does not stop MPCKclock generator.

CLKSTPMST-

13

M8-15

Clock stop, master cycle. Stops microprocessor
clock during a TILINE master cycle to prevent
waste of controller states during the data transfer.
Decoded from special group 0 of microinstruction
(ROM36-39 = 00(1).

CLKSTRT-

4

J12-6

Clock start. Set input to clock on latch. Initiates
the microprocessor clock generation cycle.

CLKTI-

4

H8-3

Output of delay 1 timer in microprocessor clock
circuit. Sets pulse duration of MPCK-.

CLKTI

4

L8-12

Inverted form of CLKTI- used to trigger delay 2
and develop PBUSEN.

CLKT2-

4

H8-6

Output of delay 2 timer in microprocessor clock
circuits.

CLKT3-

4

H8-8

Output of delay 3 timer in microprocessor clock
circuits. Determines minimum retrigger time for
clock circuit.

Signature

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Pin

Definitions

CLKIRC

4

H7-2

RC term used in development of CLKTI-.

CLK2RC

4

H7-IO

RC term used in development of CLKT2-.

CLK3RC

4

H7-8

RC term used in development of CLKT3-.

CLRCNTR-

14

~111-8

Clear shift counter.

CLRSECIDX-

13

NIO-12

Clear sector latch and index latch.

CLRWRTQ-

5

F9-2

Clear Write. Latched and synchronized microcode interrupt condition that is generated if
a FIFO timing error occurs during a disk
write operation. Synchronized verSIon of
WRTTIMERR-.

CMDFRECLK-

5

R2-3

Command frequency clock. Approximate 320 Hz
output of RC-controlled NE555 timer that is
counted down to produce the 200 millisecond
command timer delay.

CMDTMRCLK

5

J6-3

Command timer clock. Gated version of 320 Hz
CMDFREQCLK-.

CMDTMRCLR

5

J6-8

Command timer clear generated as a result of a
general reset or a trigger timer microinstruction.

CMDTMRDLY-

5

J7-7

Command timer delay. The command timer
allows a 200 millisecond (approx) time frame for
an operation to occur. Generates a microcode
interrupt if the timer is allowed to expire.

CMDTMRQ-

5

F9-12

Command timer delay, latched. Latched and
resynchronized (to microprocessor clock) version
of the command timer delay. Enables command
timer interrupt trap, if low.

CNTEQI5

14

PI0-15

Count equals 15. Indicates that the disk clock bit
counter has reached a count of 15. Used to keep
track of 16-bit words as they are shifted through
the serial/ parallel shift register during disk read
and write operations.

CPKONES

7

EII-I0

Command CPE K-bus to all ones. Disables K-bus
input multiplexers placing all low levels on CPE
K-bus inputs. These low levels are interpreted as
data ones by the active-low K-bus.

CPK (00-15)-

7

A7, B7,

K-bus active low inputs 0-15.

B6, B8

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Definitions

Gate - Pin

CPLCK-

8

E8-8

CPE left byte clock. Microprocessor clock
(MPCK-) input to the left byte CPE array, gated
by microinstruction word select field (ROM08,
09), CPE clock stop (ROMOO) and the TRAP
signal.

CPRCK-

10

E8-6

CPE right byte clock. Microprocessor clock
(MPCK-) input to the right byte CPE array gated
as described with CPLCK-, above.

8, 9,
10, II

C3, E3, C4,
E2, CI, EI

Right shift outputs of CPE devices to shift
inputs (LI) of less-significant CPE stages.

CPUID

13

990 chassis

Central processor unit identifier. The input pin
floats (and is pulled high) in a 990/9 chassis. The
input is grounded (logic'zero) for a 990/ 10 chassis.
The distinction between processors is necessary
due to minor differences in TILINE timing.

CPXL

12

C7-7

Carry propagation output from CPE left byte
carry generator.

CPXLA

12

C9-4

Carry propagation output of CPE left byte carry
multiplexer.

CPXR

12

D7-7

Carry propagate output from CPE right byte
carry generator.

CPXRA

12

C8-9

Carry propagate output from CPE right byte
carry multiplexer.

CPX (0-7)

8, 9,
]0, II

C3, E3, C4
E4, E2, CI
EI, C2

Carry propagate outputs from individual CPE
devices to carry generators.

CPY (0-7)

8, 9,
10, II

C3, E3, C4
E4, E2, CI
EI, C2

Carry propagate outputs from individual CPE
devices to carry generators.

CPYL

12

C7-10

Carry propagate output from CPE left byte carry
generator.

CPYLA

12

C9-12

Carry propagate output from CPE left byte carry
multiplexer.

CPYR

12

D7-IO

Carry propagate output from CPE right byte
carry generator.

CPYRA

12

C8-12

Carry propagate output from CPE right byte
carry multiplexer.

CPSHIFT
(2, 3, 6-8)-

B-4

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Gate - Pin

Definitions

CRCDATIN

19

N6-9

CRC data in. Serial read or write data into CRC
generator / checker.

CRCDATOUT

19

M6-12

CRC data out. Serial CRC character out of CRC
generator / checker at the end of a write operation
(header or data) to disk.

CRCENFLAG

18

L5-14

CRC enable flag. Used to enable data input to (or
CRC character out of) the CRC checker/
generator.

CRCERR

19

M6-13

CRC error. Indicates that the CRC character
calculated on read did not agree with the CRC
character recorded at write time.

CRCPREFLAG

18

L5-13

CRC preset flag. An output of the disk write flag
register which presets the CRC generator to all
ones prior to writing data to the disk.

CRCPRES-

17

M5-7

CRC preset. Preset signal enabled by the sync
character detector (read) or CRC preset flag
(write). Presets CRC generator/checker to all
ones.

DATCLK

19

N8-6 or
L8-10
(Jumper
Selected)

Disk data write clock input to write data out F / F.
In phase with DCLK and DCLOCK unless phase
inverting jumper J5 is installed.

DBUSHI

14

P4-9

Disk bus high. Most significant bit out of disk
(cylinder) address register. Inverted to supply
ADD256-.

DCLK

19

L7-14

Disk clock. Clock signal for disk interface circuits.
Supplied by crystal oscillator and divider for write
operations, disk for read operations, microinstructions for self-test operations.

DCLOCK-

19

N9-8

Disk read or write clock.

DCLOCK

19

N8-6

Disk read, write or test clock.

DCLOCKl-

19

L8-10

Inverted form of DCLOCK. Not used unless
excessive write skew requires installation of clock
phase correcting jumper J5.

DCRCERRQ-

18

N4-6

CRC error, latched.

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Gate - Pin

Definitions

DIAGFAUL TQ-

13

H 11-12

Diagnostic fault. Output of microinstruction
special group 1 decoder/register which indicates
that a fault was detected during controller selftest. Inhibits read, write, lights FAULT indicator.

DIRDATEN-

15

G 12-11

Direct data enable. Enables 3-state outputs of
direct read register onto the processor bus. Used
during record leader verification when FIFO is
bypassed.

DISKDATIN

19

P6-5

Disk data in. Serial read data from the read data
buffers to the serial input of the serial/ parallel
shift register.

DISKDATLD

14

N9-6

Disk data load. A strobe issued during disk write
operations which loads parallel data into the
serial/ parallel shift register. Data is shifted out of
the register (serially) to the write data encoding
circuits.

DISKSEL-

14

R6-4

Disk Select. When low, selects the fixed disk.
When high, selects the removable cartridge.
SELECT A- and SELECTB- are also required to
complete the selection.

DSKBUSLD

12

MIO-7

Disk bus load. Loads inverted processor bus outputs PBUS07- through PBUS15- into disk address
register. Output of disk address register is cylinder
address ADDOOl-through 256- to disk drive.

DSKCLR-

13

NI0-14

Disk clear. Microinstruction-controlled clear to
disk interface logic of controller.

DSKDIRECT-

13

FI2-IO

Disk direct. When low, disables FIFO input, and
partially enables direct read register outputs to
P-bus.

DSKDIRQ

13

H 11-7

Disk direct mode. Microinstruction-controlled
mode bit.

DSKOSC

19

PIl-3

5MHz output of oscillator used to clock write
data to the disk drive.

DSCOSC-

19

LIO-8

Disk Oscillator. Gated verSIOn of 5MHz disk
oscillator output. Used to clock disk interface
logic during write operation.

DSKSHIN-

18

P9-8

Disk shift in. Shifts disk read data from the
serial/ parallel shift register into the FIFO buffer.

Signature

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Gate - Pin

Definitions

DSKSHOUT-

18

18-8

Disk shift out. Unloads data from FIFO output
stage during write operations.

DSKSTRQ

14

R 11-9

Disk start transfer latch output. Set by a microinstruction at the beginning of a disk read or write
operations.

DSKSTRRST-

13

N 10-13

Reset disk start transfer F / F. Clears disk interface
logic as the result of a microinstruction command.

DSKSTRCK-

13

NIO-II

Disk start transfer clock. This pulse is enabled by
a microinstruction and strobed by MPCK- to
form the initial event of any disk interface
operation.

DSKSTRTR-

14

P12-6

Disk start transfer F / F summary reset. Clears
disk 1/ F logic in case of general reset, interrupt
reset, DSKSTRRST-, or DSCLR- microinstruction-controlled reset.

DSTARTQ

14

RII-5

Disk start. Resynchronized (with disk clock) disk
interface start signal.

EG-

13

R2-6

Erase gate to disk drive. Enables straddle erase in
disk drive.

ENFLG-

17

M 12-11

Enable flag. Enables FIFO flag multiplexer to
gate H flag bits (FIFOINI6-19) into the FIFO.
The flags accompany write data through the
FIFO.

ENSPEC-

13

LIO-6

Enable special field decoders. ROM32-39 of the
controller microinstruction may be interpreted as
an immediate operand to be loaded on the K-bus,
or as special purpose fields. If ROM 10=0 and
there is no trap, the high level of CLKTI enables
ENSPEC-. ENSPEC- enables the TILINE
operation decoder and the special function group
select decoder.

ERRORSET

17

M2-12

Error set. Input to FIFO timing error F / F which
sets it in case of a FIFO rate error.

FAULTLED-

13

G5-4, 10

Two-wire ORed open-collector outputs which
light the controller F AUL T indicator in case
the command timer expires (CMDTMRDL Y-)
or a fault is detected during self-test
(DIAGFAULTQ-). Note that DIAGFAULTQ
and FAUL TQ are microinstruction fields.

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Gate - Pin

Definitions

FAULTQ-

13

Hll-II

Microinstruction-controlled fault output from
special group 1 decoder/register. Lights FAULT
indicator via FAULTLED-.

FIFODATEN-

15

G 12-3

FIFO output data enable. Enables three-state
outputs of FIFO out/ zero mix onto processor bus
if direct mode is not specified and disk data to
P-bus is specified by the appropriate microinstruction fields.

FIFOOUT (00-19)

17

K3, K7,
K4, K5

FIFO output data from 16-word first-in/first-out
buffer. Bits 16-19 are flag bits.

FIFOSEL

15

G12-6

FIFO select. Gates FIFO data through the FIFO
out/ zero multiplexer to the processor bus and on
to the TILINE line drivers.

FILERDY-

16

Drive

Disk file ready. Output from the disk drive which
indicates the drive is ready for operation; i.e., dc
power ok, up to speed, heads loaded, no faults
detected, terminator installed. Inverted in
controller as OFFLINE-.

FLED-

13

L9-3

Fault LED. Lights FAULT indicator in case of
microinstruction-specified fault during normal or
self-test operations.

GO

2

F12-6

Inverted output of GO gate that is used during
TILINE master cycle to supply the TILINE GO
line driver.

GOINH

2

Bll-8

Go inhibit. Prevents the setting of the GO gate if a
TILINE GO or TILINE terminate is active when
the master access logic reaches the device access
state.

GROUPOO-,
01-,10-,11-

13

Jll

Microinstruction special group 0-2 decoder
enabling signals. ROM34, 35 are decoded to
enable the special group microinstruction
decoders. Requires ENSPEC- low.

HDSEL-

13

R3-10

Head select. Output to the disk drive that selects
the upper surface (HDSEL-Iow) or the lower surface (HDSEL- high) of the selected platter.

IDLE

19

M12-8

Idle. An input to the CRC multiplexers that forces
CRCDA TIN low when not checking read data or
write data.

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Gate - Pin

Definitions

INDEXMRK-

16

P6-8

Index mark, latched. The index mark is a
reference pulse (supplied by the disk drive) which
occurs once every disk revolution. The index
mark is latched as INDEXMRK-.

INDEXMRKQ-

16

J 5-10

Index mark latched for I -bus input and resynchronized to microprocessor clock.

INDMRK-

16

Disk Drive

Index mark. Generated by sensors in the disk
drive once per revolution. Identifies the start of
sector O.

INRDY-

16

K2-6

FIFO summary input ready. Indicates FIFO
buffer has space available for loading additional
input data.

INTA-

5

FIO-14

Interrupt A. Group select output of the interrupt
address encoder that indicates, when low that at
least one active, synchronized microcode interrupt
condition is present. Used (in inverted form as
INTA) to enable the TRAP- signal and to enable
INTB, which disables TRAP- after one clock
time.

INTAD (0-2)

5

FIO-9,
7, 6

Interrupt address bits 0-2. Outputs of the interrupt
address encoder that form part of a trap vector
address for the highest priority active (and
synchronized) interrupt condition.

INTB

5

F9-15

Interrupt B. Interrupt B goes high one clock time
after INT A goes high. INTB (in inverted form as
INTB-) disables TRAP- one clock time after
INT A. INTB also prevents trap conditions from
occurring too close together.

INTRST-

5

J12-11

Interrupt reset. Clears the unsynchronized
mterrupt latches after the synchronized interrupt trap operation starts. INTRST - (CLKOFF.INT A)-.

INTTRAP

5

MI2-3

Interrupt trap. This signal forces the NRA 06-09
multiplexer outputs to all zeros as part of a microcode interrupt trap operation. INTRAP is
essentially an inverted form of TRAP-, but it is
not enabled for TILINE slave trap operations.

10RES-

2

AIO-4

I/O reset. TILINE I/O reset input to TILINE
abort interrupt trap latch.

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Definitions

Gate - Pin

IRDY A- IRDYD

Input ready. Outputs from individual five bit by
16-word FIFO devices which indicate that the
FIFOs are ready to accept additional input data.
Summarized as INRDY-.

LFBYT-

10

C12-6

Left byte only. Decoded from word select field
(ROM08, ROM09) to disable clock to the right
byte and disable the right byte carry multiplexer.
See R TBYTE-.

LIR-

12

E7-7

Output of right shift multiplexer which supplies
right shift input (LI) of right byte CPE array.

LMXSEL

7

B12-6

Left byte K-bus input multiplexer select. Steers
eight-bit immediate operand field of microinstruction through multiplexer to K-bus inputs.

MI2V

10
J.J

990 chassis

Negative 12 volt de power for TMS3!29
TESTDATA shift register.

MCUADR
(1-9)

6

69,610, H9

Microcontrol unit address, bits 1-9. Outputs of
the SN74S482 address generators which select the
4O-bit microinstruction from ROM.

MCUCI (1-3)

6

19-2, H9-3,
GI0-3

Microcontrol unit carries. M CU CI 1 is generated
by the branch decoder ROM and is used for
address incrementation. The other carries are
between the 'S482 address generators.

MCUS (1-6)

6

19

Microcontrol unit select code. This code,
developed by the branch decoder ROM, determines the operation(s) to be performed by the
address generators.

MDAC

3

D12-9

(Master) device access. Output of device access
F / F which identifies the device access state of the
TILINE master cycle.

MDACCK

3

All-9

(Master) device access F / F clock. This multiplexer-selected clock pulse clears the device access
state at the end of a TILINE master cycle.

MDACRST

3

CII-4

(Master) device access reset (990/9 only). Source
for MDACCK selected by the CPU ID multiplexer in a 990/9 chassis.

MDACSET-

3

Bl1-6

Device access F / F unconditional set. Advances
the TILINE master cycle from the device
acknowledge state to the device access state.

B-IO

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Definitions

MDACT

3

G 11-5

(Master) device active F / F output. Indicates that
the TILINE master access logic is performing a
master cycle. Disables microprocessor clock,
enables the 20-microsecond timeout delay, latches
up the PBUS control register.

MDAK

3

D 12-5

(Master) device acknowledge F I F output. This
F / F when set indicates that the TILINE master
cycle is in the device acknowledge state.

MDAKCK

3

E 11-4

Device acknowledge F / F clock. Advances the
TILINE master cycle from the device access
request state to the device acknowledge state.

MDAKCLR-

3

C 10-8

Device acknowledge F / F unconditional reset.
Clears the device acknowledge F / F when the
TILINE master cycle advances to the device
access state.

MDAR

3

CII-13

(Master) device access request. Initiates the 100nanosecond timer which determines the minimum
time that the master cycle spent in the device
access request state.

MDAR

3

C12-3

Device access request state. Disables TLAGOUT
to lower priority masters during the period
between the initiation of the master cycle and the
start of the device access state.

MDAREN-

3

CI2-11

(Master) device access request enable. Partially
enables the MDAR gate if TILINE access granted
is available and if the TILINE master cycle has
not reached the device acknowledge state.

MDAROK-

3

F7-8

(Master) device access request ok. Output of delay
timer that indicates that the access logic has been
in the device access request state for the minimum
required time.

MDARRC

3

H7-6

RC timing term used In the development of
MDAROK-.

MDCMP-

3

B12-8

(Master) device complete. Indicates that the
TILINE data transfer operation is complete. Used
to restore master access logic to the initial state.

Signature

NOTE
The MDCMP- and MDTOL gate
configuration resembles a latch, but is
not a latch.

B-ll ,

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Signature

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Gate - Pin

Definitions

MDGO

3

B 10-5

(Master) device go. F / F output that initiates
TILINE master cycle and remains active throughout the cycle.

MDTM

3

B12-12

(Master) device terminate. Identifies the end of
the TILINE data transfer, and is used to reset
master access logic to the idle state, on leading
and trailing edges.

MDTMEN

3

All-12

(Master) device terminate enable. An output of
the CPU identification multiplexer used in the
development of MDTM. Equal to hardwired I for
990/9, GO for 990/10.

MDTO-

3

F7-6

(Master) device timeout. Output of 20microsecond (approximate) timer. The timer is
initiated when device active F / F sets. If it expires
before master device complete (MDCMP-),
indicates a hung TILINE cycle.

MDTOEN-

2

BII-II

(Master) device timeout enable. Initiates 20microsecond timer at start of TILINE master
cycle, if no wait condition exists.

MDTOL

2

E 12-7

Master device time-out, latched. Latched version
ofMDTO-.

MDTOQ-

5

F9-5

Latched and synchronized (with MPCK-) version
of MDTO-.

MDTORC

2

B9-15

RC timing term used in the development of
MDTO-. MDTO- is enabled when the MDTORC
voltage reaches the input threshold of the MDTOgate.

MPCK

4

L9-11

Microprocessor clock. Active high version of
MPCK-.

MPCK-

4

F8-8

Microprocessor clock. Active-low mam timing
term for controller logic.

MPCKMNT

18

P7-4

Microprocessor clock maintenance. An isolated
version of MPCK- which is available to an external tester at the test sockets.

MPCK482-

4

F8-11

Microprocessor clock (MPCK-) signal with fast
rise time, dedicated to the SN74S482 address
generator clock inputs.

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Pin

Definitions

MSBADRINC

13

M8-13

Most significant address register increment.
Output of microinstruction special group 0
decoder which increments the four-bit TILINE
MSB address register when a TILINE master
operation passes a 65K address boundary.

~v1SBADRLD-

13

M8-14

~vfost significant address register load. Loads a
four-bit address from the processor bus into the
TILINE MSB address register.

MSBADR (0-3)

8

H5

Four most significant TILINE address bits.
Stored in an external TILINE MSB address
register because there are only 16 address bits
available from the CPE array at one time.

MSTRD-

13

111-6

Master read. Output of microinstruction decoder
which initiates a TILINE master read cycle.

MSTSTB

3

112-3

Master cycle strobe. Clock input which triggers
the master device go F / F to set and initiate a
TILINE master read or master write cycle.

MSTWRT-

13

111-7

Master write. Output of microinstruction decoder
which initiates a TILINE master write cycle.

NOTRDY-

16

R8-2

Not ready to start read/write, Inverted form of
RDYSRW- (ready to start read/write) from
selected disk unit. NOTRDY- high indicates that
the head carriage has reached the specified
cylinder and the heads have had time to settle, in
addition to the FILERDY- conditions.

NRA (01-09)

5

L9, HI0,
510

Next ROM address bits 1-9. Outputs of the NRA
multiplexers, which serve as A inputs to the
address generators.

OFFLINE-

16

R8-12

Disk offline. Inverted form of FILERDY - from
disk drive.

ORDYA,B,C,D

17

K3, K7,
K4, K5

FIFO output ready signals from each of the fivebit by 16-word FIFO devices. Indicates that the
FIFO has data available at the outputs.
Summarized as OUTRDY-.

OUTRDY-

16

K2-8

Summary FIFO output ready.

PARDATOO

17

L3-12

Parallel data, bit O. Most significant bit, and shift
output, of serial/ parallel shift register.

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Definitions

PARDAT (00-15)

17

L3, L4,
M4, M3

Parallel data outputs of serial/ parallel shift
register.

PBCPE-

12

EI0-14

CPE to processor bus enable. An output of the
PBUS source decode which enables the threestate CPE D-bus outputs onto the processor
bus.

PBDSKDAT-

12

EI0-11

Disk data to processor bus enable. An output of
the PBUS source decoder which partially enables
the FIFO and disk direct read register three-state
outputs onto the P-bus. Selection between these
sources is determined by direct/ indirect mode
F/F.

PBDSKSTA-

123

EI0-9

Disk status to processor bus enable. An output of
the PBUS source decoder which enables the threestate status line receiver outputs onto the
processor bus.

PBTLDAT-

12

EI0-12

Processor bus sourced by TILINE data. An
output of the PBUS source decoder which enables
data from the TILINE line receivers onto the
processor bus. Controlled by bus source field
(ROMI3-15) of microinstruction.

PBUSEN

12

H 8-11

Processor bus enable. A delayed version of
CLKTI which drives the PBUSENL latch in the
PBUS source control register. PBUSENL follows
PBUSEN except during TILINE master cycles.

PBUSENL

12

E9-2

Processor bus enable latched. Disables the processor bus source decoder during the time (immediately after MPCK- rising edge) that
microinstruction outputs are unsettled. Signal is
latched only if MDACT- goes active; otherwise,
follows PBUSEN.

8-11

Multiple
source bus

PBZERO-

12

EI0-15

Processor bus zero. Output of microinstruction
bus source decoder that commands the processor
bus to all zeros (high logic levels).

PFWP-

3

AIl-4

Power failure warning pulse output of CPU
selection multiplexer. See TILINE power failure
warning pulse, TLPFWP-.

PBUS (00-15)

Processor bus.

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Definitions

RCLK-

19

Disk Drive

Read clock. One hundred nanosecond (nominal)
active low clock pulses read from the selected disk
track and separated from data by the clock/ data
separator in the disk drive.

RD-

19

Disk Drive

Read data. One hundred nanosecond (nominal)
active low data pulses read from the selected disk
track and separated from clock by the clock/ data
separator in the disk drive.

RDA-

19

L8-8

RDATA-

19

Nll-8

Read data output of read 1 F / F.

RDATAQ

19

P3-5

Read data output of read 2 F / F, converted from
bit cell to NRZ format. Also used to store data in
the test memory during closed-loop self-testing.

RDB

19

RDYDIRRST-

13

NIO-9

Ready direct reset. Strobed output of microinstruction special group 0 decoder that resets
the ready direct status F / F. Note that the F / F is
in an upside down configuration, and
RDYDIRRST- is wired to the preset input.

RDYDIRSTAT-

13

N4-9

Ready direct status. F / F which toggles on first
FIFO/ direct register SHIFTIN pulse after
RDYDIRRST-. Indicates that valid data is
available in the direct read register.

RDYDIRST ATQ-

16

15-15

FIFO ready status. Latched and synchronized
to microprocessor clock for I-bus input.

RDYSRW-

16

Disk Drive

Ready to start read / write. Active when all file
ready conditions are met and head carriage is at
specified cylinder and head selection transients
have dissipated.

RDYSTATUS-

17

L2-4

FIFO ready status. FIFO ready to accept data
(disk write) or supply data (disk read).

RDYST ATUSQ-

16

15-15

FIFO ready status. Latched and resynchronized
to microprocessor clock for CPE I-bus input.

READ-

2

BIO-9

Slave read. TILINE slave logic read/write mode
F / F output, controlled by TILINE read line
receiver.

READQ-

14

L12-8

Disk interface read. Set during disk read
operations after synchronization pulse is detected.

Read data into preset input of read 1 F / F.

Grounded D-input of read 1 F / Fo

B-15

Digital Systems Division

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~'{j~o
_ _ _ _ _ _ _ _ _ _ _ _ _ __ _

937502
Sheet No.

Gate - Pin

Definitions

READQQ-

16

15-7

Disk interface read latched and resynchronized to
microprocessor clock for CPE I-bus input.

RESTORE-

13

R4-6

Restore to track zero (also called return to zero
seek). Output to disk drive which drives carriage
to fully extended position and back to the home
position, and clears drive fault latches and
cylinder address register.

RG-

13

R3-2

Read gate. Enables disk drive read circuits.

ROL-

9

E4-8

Right shift output of left byte CPE array.

ROM (00-07)

6

F5

Controller microinstruction ROM output bits 0-7.

ROM (8-15)

6

F6

Controller microinstruction ROM output bits
8-15.

ROM (16-23)

6

K9

Controller microinstruction ROM output bits
16-23.

ROM (24-31)

6

KI0

Controller microinstruction ROM output bits
24-31.

ROM (32-39)

6

K8

Controller microinstruction ROM output bits
32-39.

ROM 13L, 14L,
15L, 20L,
21L, 33L

12

E9

Latched versions of the bus source, bus
destination fields and bit 33 of the controller
microinstruction. These are latched in a transparent D latch. When the enable signal,
(MDACT-) is high, the output follows the input.
When MDACT- is low (during TILINE master
access cycle) outputs are latched up.

ROR-

II

C2-8

Right shift output of least significant stage of
right byte CPE array.

RST

2

L 7-7

Reset. General controller interface reset enabled
by TILINE 110 reset (TLIORES-) or power reset
(TLPRES-).

RTBYT-

8

F7-11

Right byte (only). Decoded from the microinstruction word select field (ROM08,09) for
right byte only instructions. Disables CPE left
byte clock and left byte carry mUltiplexer.

RTSHFTRO

12

E7-9

Right shift output of least significant CPE stage
from right shift mUltiplexer. Zero unless right
shift (F-group 0, R-group Ill) is performed.

Signature

·B-16

Digital Systems Div;

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946262-9701

937502
Signature

Sheet No.

Gate - Pin

Definitions

SECMRK-

16

Disk Drive

Sector Mark. A rotational position pulse which
identifies the start of each sector.

SECTORBOl-, 0204-, 08-, 16-

16

Disk Drive

Sector address. Sampled by the disk controller
after the sector mark is sensed.

SECTORMRK-

16

P4-6

Sector mark - latched. The sector mark latch sets
on the first sector mark after a microinstructioncontrolled clear sector and index (CLRSECIDX-)
pulse. Stores sector mark for the I-bus input latch.

SECTORMRKQ-

16

J5-12

Sector Mark. Latched and resynchronized to
microprocessor clock. Provides sector mark input
to CPE I-bus.

SELECTA-

14

R3-6

Select disk drive A. When low, selects the dual
disk drive designated A, usually the first drive.
DISKSEL- also required for individual logical
unit selection.

SELECTB-

14

R6-2

Select disk drive B. When low, selects the dual
disk drive designated B, usually the second drive.
DISKSEL- also required for individual logical
unit selection.

SHFCMD

12

E11-1

Shift command. Active when CPEs perform a
shift operation (F-group 0, R-group III). Disables
left and right byte carry multiplexers when active.

SHFTPRE

12

Ell-13

Partially decoded term used in development of
SHFTPRE- and, consequently, SHFCMD.

SHFTPRE-

12

DII-8

Partially decoded term used in development of
SHFCMD.

SHIFT

17

M5-9

Shift command used to clock the FIFO timing
F / F. Supplied by SHIFTIN for read operations,
SHIFTOUT for write operations.

SHIFTIN

18

P9-12

Shift command to FIFO input circuits. Loads a
20-bit data and flag word into the FIFO.

SHIFTOUT

18

LI0-12

Shift command to FIFO output circuits. Unloads
a 20-bit data and flag word from the FIFO, so
that the next word in line may be shifted to the
FIFO output.

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937502
Sheet No.

Gate - Pin

Definitions

SIGNBIT-

7

J6-6

Sign bit. The immediate operand (1M) field of a
microinstruction contains only eight bits. Except
for left byte only instructions, the immediate
operand is supplied to the right byte CPE K-bus
inputs, and SIGNBIT- extends the sign bit to all
the left byte K-bus inputs.

SKIC-

16

Disk Drive

Seek incomplete, also called seek error. Disk
output which indicates that the head carriage
failed to seek to the specified cylinder address.

SLADOK

4

A4-9,
A2-9
A3-9

TILINE slave address okay. Sets the slave
transfer F IF if the received TILINE slave address
equals the local board address as determined by
switches and hardwired address bits.

SLBUSY-

4

DI0-6

Slave busy. Strobe which returns a hardwired 1 on
TILINE bit 0 output if a slave read is attempted
on a busy controller.

SLGODLY

4

J8-10

Slave go delay. A protective delay (100 nsec)
which assures that the incoming TILINE slave
address has stabilized before it is decoded.

SLGORC

4

H7-4

RC term used in development of SLGODL Y-.

SLSW (13-16)-

4

B2-3, 2,
I, 4

SLTM

4

C12-8

TILINE slave terminate. Output to the TILINE
terminate line driver. Indicates that the slave logic
has completed the specified operation. If a slave
read is directed to a busy controller, an immediate
slave terminate is issued, accompanied by a data 1
in the date word bit 0 position.

SLTMA-

4

K12-3

Slave terminate access. Enables a normal slave
terminate at the completion of a slave cycle (controlled by SL VTRM- from microinstruction
decoder).

SLTMB-

4

DIO-8

Slave terminate B. Enables an immediate
terminate and busy indication if asia ve read is
addressed to a busy controller.

SLVA-

4

GII-9

Output of one of the two FIFOs which control
TILINE slave operation.

SLVACT

5

J12-8

Slave active. Disables interrupt priority encoder
and serves as a slave trap address input.

Signature

TILINE slave address switch outputs.

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937502

Sheet No.

Gate - Pin

Definitions

SLVAD-

4

MI1-3

Slave cycle enable. Enables a TILINE slave cycle
if the enable slave bit (ROM 16) of the microinstruction is set and the slave transfer F / F is set.

SLVB-

4

LI2-5

Output of one of the two F / F's which control
TILINE slave cycles.

SLVTRM-

13

JI1-5

Slave terminate. Output of microinstruction
special field decoder, controlled by ROM32, 33.
Causes TILINE slave logic to issue a TILINE
terminate, ending the slave cycle.

SLXFR

4

M9-5

Slave transfer. Slave transfer F / F sets upon
expiration of the 100 nanosecond slave go delay if
the incoming TILINE address equals the board
slave address.

SPAREINl-

11

No Connection

SPAREIN2-

11

Jumper J2
(test only)

Long test check jumper, if installed, grounds
SP AREIN2-. This causes the microprogram to
execute the long self-test on power-up for test
only.

SPAREIN (3-6)-

16

No Connection

Spare inputs from disk drive to disk status word
(processor bus) input.

SPAREOUTI-

13

R4-2

Status update strobe. During self-test the
controller microprogram maintains a status count
which is updated as various test segments are successfully completed. SPAREOUTI- is pulsed each
time the status count is updated. Available as a
strobe to synchronize logic analyzer or oscilloscope.

SPAREOUT2-

13

R6-10

Spare output.

SPAREOUTQI-

14

P3-I2

Latched spare output. A spare output of the disk
select register.

STBCLR-

13

NIO-7

Allows a deliberate clearing of the disk control
functions In the special function 2 decoder /
register.

STBRST-

13

PI2-8

Strobe reset. Clears the special function 2
decoder/register in the event of a general reset
(RST-), an interrupt reset (lNTRST-), or a strobe
clear from special function 0 (STBCLR-).

Signature

Spare input from disk drive to CPE I-bus.

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937502
Sheet No.

Gate - Pin

Definitions

STOPFLAG

18

L5-12

Write data (to disk) transfer stop flag. This flag
accompames the last TILINE-to-FIFO word
through the FIFO. When it reaches the FIFO
output, the transfer to disk should be stopped.

STRTREAD-

14

SWAIN-

16

Signature

RI0-6
Adapter
Board

Interface read logic clear.
Switch fixed/ removable unit numbers on drive A,
if low. Controlled by jumper JI-J3 of adapter
board mounted on drive A. Normal designation
(SW AIN- high) is:
unit 0 - fixed disk
unit 1 - removable disk cartridge.

SWBIN-

16

Adapter
Board

Switch fixed / removable unit numbers on drive B,
if low. Controlled by jumper JI-J4 of adapter
board mounted on drive B. Normal designation
(SWBIN- high) is:
unit 2 - fixed disk
unit 3 - removable disk cartridge.

SYNCQ-

14

N12-10

Synchronization character detected and latched.
Enables read operations after the 6E synchronization character is detected.

SYNC6E

14

N2-8

Synchronization character present. Goes low for
one disk clock time when the 6E synchonization
character is detected.

TESTBIT-

12

D8-9

Input to test bit flip-flop from word look-ahead
carry generator.

TESTBITQ

12

M9-8

Output of test bit F / F which steers execution of
all conditional branch and conditional return
microinstructions.

TESTCLK-

13

HII-5

Test clock. Microinstruction-controlled clock
pulse which replaces disk read or write clock as
the disk 1/ F timing source during controller selftest. Burst frequency is approximately 833.3 KHz.

TESTDATA

19

Lll-3

Test data output of TMS 3129 serial shift register
memory used for controller closed-loop self-tests.

TESTMODEQ

13

Hll-4

Test mode output of microinstruction special
group 1 decoder/register. Sets up data paths for
controller closed-loop self-test.

B-20

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Signature

Sheet No.

Gate - Pin

Definitions

TESTOUTIN

19

Ll1-6

The TMS 3129 serial test memory consists of 2
sections, each with a I-by-132 capacity.
TESTOUTIN connects the output of one section
to the input of the other, for a I-by-264 net
capacity.

TESTRDDAT-

19

MII-6

Test read data. Test data out of the serial test
memory to the read data logic, as gated by
TESTMODEQ. Self-test only.

TIMERRQ

14

N12-6

FIFO timing error - latched. Detects FIFO errors
during read and write operations such as
attempting to load a full FIFO or attempting to
retrieve data from a FIFO without any data in it.

TLABORT-

2

CI0-6

TILINE abort. Input to TILINE abort latch
which sets the latch if a power failure warning
(TLPFWP-) or a general 110 reset (IORES-)
signal is received.

TLABORTL

2

E12-9

TILINE abort latch. Sets if controller operations
are to be aborted by the power failure warning
pulse (TLPFWP-), the power reset (TLPRES-) or
a general 110 reset (TLIORES-).

TLABORTQ-

5

F9-10

Latched and synchronized (with MPCK-) version
of TLABORTL. This microcode interrupt signal
generated if a power failure warning, power reset,
or 1/0 reset is issued to all the controllers in the
990 chassis.

8, 9,
10, 11

A5, CPE
devices,
TILINE

TILINE address. A 20-bit address which accompanies any word transferred on the TILINE.

TLAGIN

3

P2-6

TILINE access granted input from higher priority
masters. TLAGIN must be high for the TILINE
master cycle to initiate the 100 nanosecond device
access request minimum timer.

TLAGOUT

3

CI0-3

TILINE access granted output to lower priority
masters. TLAGOUT is disabled during the device
access request and device acknowledge states of
the TILINE master cycle.

TLAK-

2

PI-71

TILINE acknowledge. As an input, must be
inactive (high) for the TILINE master cycle to
advance to the device acknowledge state. As an
output, is asserted during the device acknowledge
state.

TLADR (00-19)

B-21

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Signature
TLAV

TLDA T A (00-15)-

937502
Sheet No.

Gate - Pin

Definitions

2

PI-58

TILINE available. As an input, must be active for
the TILINE master cycle to advance to the device
access state. Disabled by the controller in device
access sate.

8, 9,
10, 11

A6, B4,

TILINE data.

B3, B5.
TILINE

TLDATEN-

2

HI2-6

TILINE data enable. Enables TILINE data line
drivers during a master write or slave read cycle.

TLERR-

2

D 11-6

TILINE error. Sets the TILINE error latch if a
parity error (TLMER) is returned by TILINE
memory during a master read cycle.

TLERRL-

2

EI2-I3

TILINE error latch output. See TLERR-.

TLERRQ-

5

F9-7

Latched and synchronized version of TLERRL-,
used in interrupt trap circuits. Initiates a microcode interrupt trap if a memory parity error is
detected while the controller is reading data from
990 memory for transmission to the disk.

TLGO-

2

P 1-25

TILINE go. Control strobe asserted by a TILINE
master throughout a data transfer. Used by slaves
to enable slave address decoding, initiate slave
response.

TLINT-

.l..l

1'1

G5-2

TILINE interrupt. Disk controller interrupt to the
990 CPU. Enabled by a special group 1 microinstruction.

TLINTLED

13

G5-I2

TILINE interrupt indicator. Light-emitting diode
indicator that lights when the controller sends an
interrupt (TLINT-) to the 990 CPU.

TLINTQ-

13

HII-9

TILINE interrupt. Output of microinstruction
special group I decoder I register which enables an
interrupt (TLINT-) to the 990 CPU.

TLIORES-

2

PI-14

TILINE I/O reset. Master clear signal from 990
CPU to all 110 controllers.

TLMER

2

PI-55

TILINE memory error. Asserted by TILINE
memory if a parity error is detected as part of a
memory read operation.

B-22

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Sheet No.

Gate - Pin

Definitions

TLPFWP-

3

PI-16

(TILINE) Power failure warning pulse. Advance
notice from the 990 power supply that a power
failure is imminent. Precedes power reset.

TLPRES-

2

PI-13

(TILINE) Power failure reset. Reset signal from
990 power supply that assures that I/O logic is
cleared, and that it restarts in an orderly manner.

TLREAD-

2

PI-II

TILINE read.
operations.

TLSHIN-

18

D 10-11

TILINE shift in. Generated during write data or
write data unformattted operations to shift data
from the TILINE line receivers into the FIFO.

TLSHOUT-

18

G12.8

TILINE shift out. Generated during read data or
read data unformatted operations. Shifts a new
word to the FI FO output after a word is transmitted to 990 memory via a master write cycle.

TLTM-

2

PI-20

TILINE terminate. Asserted by TILINE slave
when read data is available or write data has been
accepted.

TLWAIT-

2

PI-63

TILINE wait. Asserted only by TILINE bus
couplers.

TRAP-

5

H12-8

Trap signal that steers the next ROM address
mUltiplexers to gate a trap vector address to the
address generators. Generated while servicing a
TILINE slave trap, microcode interrupt trap,
power or I/O reset trap.

TRIGTMR-

13

N 10-10

Trigger command timer. Output of microinstruction special group 0 decoder that retriggers
command timer, preventing expiration of the 200
millisecond delay.

UNITA

14

P3-5

Select unit A. Disk select output which when high
specifies the dual disk drive designated A (the first
drive). Requires DISKSEL for complete selection
of a logical unit.

UNITB

14

P3-2

Select unit B. Disk select output which specifies
dual disk drive B. Requires DISKSEL for
complete logical unit selection.

UNITLOAD-

12

MIO-5

U nit load. Loads the disk selection signals from
the processor bus into the disk select register.

Signature

B-23

Identifies read/write TILINE

Digital Systems Division

~_
946262-9701
J2h\
_ _ _ _ __
937502
Sheet No.

Gate - Pin

Definitions

UTCSHIN-

12

MI0-6

UTC shift in. Loads a word from the CPE outputs
into the FIFO, such as when writing headers
during a write format operations.

UTCSHOUT-

18

G 12-8

UTC shift out. Unloads a word from the FIFO
output when the CPE has accepted the word, such
as during self-tests.

WCHK-

16

Disk Drive

Write check, also called fault. Indicates that the
disk drive electronics has detected a fault
condition and inhibited write and erase currents.

WCLK

19

Mil-II

Write clock. A SMHz square wave (200 nanosecond pulse width) clock used to encode write
data and clock.

WCLKAQQ-

19

N7-8

Write clock divider output. The 2.S MHz output
of clock divider. Serves as the source for DCLK
(disk clock) during write operations. Also used in
write data and clock encoding.

WDNCLK-

19

R2-8

Write data and clock. Double-frequency (FM) bit
cell encoded data and clock to disk drive.

WDNCLKEN

19

N8-11

Write data and clock enable. A signal used in
write data and clock encoding. Always high at
clock time, high at data I time, low (to inhibit
output pulse) at data 0 time.

WG-

!3

R2-11

Write gate, to disk drive, enables write current.

WOSCSTOP-

19

TP I

Write oscillator stop, external test input.

WOSTST-

19

TP2

Write oscillator stop-external test input.

WP-

16

Disk Drive

Write protect. Indicates that data may not be
written to the selected logical unit because the disk
drive WRITE PROTECT switch for that fixed or
removable disk is ON.

WRITEQ

14

Nll-S

Write, latched. Output of write F/F in disk I/F
start and read/write control logic.

WRITEQD

14

L9-8

Input to write F I F in disk II F start and readl
write control logic. Enabled when microinstruction specifies a write operation
(DSKWRTQ = I) and the disk start FI F
(DST ARTQ) sets.

Signature

B-24

Digital Systems Division

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937502
Signature

Sheet No.

Gate - Pin

Definitions

WRTDATD

19

N6-7

Serial output of write datal CRC multiplexer to
write data and clock encoding circuits.

WRTDATOUT-

19

N7-6

Serial write data out, in NRZ form to write data
and clock encoders. Also, self-test write data to
serial test memory via read 2 (RDA T AQ) F IF.

WRITTIMERR-

5

NS-3

W rite timing error. Generated if a FI FO timing
error is detected during a write to the disk. This
signal is synchronized (as CLR WRTQ-) to initiate
a microcode interrupt trap routine.

ZERODATEN-

15

CIO-ll

Zeros or data enable. Enables three-state outputs
of FIFO data out I zero multiplexer onto processor bus.

B-25/B-26

Digital Systems Division

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946262-9701

APPENDIX C
FINE LINE SIGNAL DICTIONARY

Digital Systems Division

~------~

946262-9701

APPENDIX C
FINE LINE SIGNAL DICTIONARY

2262102
Signature

Sheet No.

Gate - Pin

Definitions

ACCDATEN

2

UCE072-1

Access data enable. Partially enables the
TLDATEN gate when access logic is in the device
access state (ACCESSOK- = 0) and TILINE terminate has not occurred.

ACCESSOK-

2

UBK094-6

TILINE access okay. During TILINE master
cycle, enables TILINE address drivers,
TLREAD, TLGO- drivers. For write operations,
also partially enables TILINE data line drivers.

ADDACK-

16

UJJ039-9

Address acknowledge, from selected disk unit.
Acknowledges that the drive has accepted the
cylinder address supplied by the controller.

ADDACKQ

16

UFK039-5

Latched version of address acknowledge
(ADDACK), stored in I-bus input latch.

ADDSTB-

13

UJD050-11

Address strobe. Output which, when low, strobes
the cylinder address (ADD001- thru ADD256-)
into the selected disk drive.

ADDOOI-, 2-, 4-,
8-, 16-, 32-, 64-,
128-, 256-

14

UJJ017,
UJJ028,
UJJ061

BUSYLED-

13

UBE072-10

Open-collector output that lights the BUSY
indicator when low. Controlled by BUSYQ-.

BUSYQ-

13

UFK050-10

Controller busy. Output of microinstruction
decoder / register that indicates that the controller
is busy performing a command. Lights BUSY
indicator and enables busy indication for any
TILINE master read operation.

CARRY(O-6)-

12

UAKOO6,
UAK050

CIL-

12

UAK072-12

Carry input to left byte CPE array.

CLKEN

4

UCE072-10

Clock enable. Retriggers microprocessor clock
cycle or in free-running mode when delay 3
expIres.

Cylinder address, to the selected disk unit.
Addresses 0-407 are valid.

Carry signals from carry look-ahead units to
mIcroprocessors.

C-l

Digital Systems Division

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2262102
Sheet No.

Gate - Pin

Definitions

CLKINH

4

UCE072-4

Clock inhibit. Disables microprocessor clock
generation during a TILINE master cycle.

CLKLED-

4

UBE072-6

Clock indicator. Open-collector verSIOn of
CLKOFF that lights an LED indicator each time
the clock on latch sets.

CLKOFF

4

UAK094-12

Clock off. This signal which has the same period
as MPCK- is used in the development of microprocessor clock, MPCK-. It is also used as a
synchronizing term in clearing interrupt latches.
CLKOFF goes low coincident with the leading
(falling) edge of MPCK-. CLKOFF remains low
for 125 nanoseconds, then goes high for 175 nanoseconds (more if the clock wa veform is extended
by a TILINE master cycle).

CLKON

4

UDE083-6

Clock on. Latch output which activates the microprocessor clock generation cycle. The period is the
same as the period of MPCK-, and the high level
pulse width is 125 nanoseconds.

CLKRUN

4
18

UEEI05-3
XDKOO6-11

Clock run. Pulled high except during single-step
control by an external tester.

CLKSTP-

8

UDE028-10

CPE clock stop. Disables CPE left and right byte
clocks when commanded by microinstruction bit
o or when a trap occurs. Does not stop MPCKclock generator.

CLKSTPMST-

13

UHD050-15

Clock stop, master cycle. Stops microprocessor
clock during a TILINE master cycle to prevent
waste of controller states during the data transfer.
Decoded from special group 0 of microinstruction
(ROM36-39 = 00(1).

CLKSTRT-

4

UCE083-11

Clock start. Set input to clock on latch. Initiates
the microprocessor clock generation cycle.

CLKTI-

4

UDKI05-3

Output of delay 1 timer in microprocessor clock
circuit. Sets pulse duration of MPCK-. On fine
line board, drives PBUSENL latch in the PBUS
source control register. PBUSENL follows
CLKTl- except during TILINE master cycles.

CLKTI

4

UDK094-8

Inverted form of CLKTI- used to trigger delay 2
and develop PBUSEN.

CLKT2-

4

UDKI05-11

Output of delay 2 timer in microprocessor clock
circuits.

CLKT3-

4

UCE083-3

Output of delay 3 timer in microprocessor clock
circuits. Determines minimum retrigger time for
clock circuii.

C-2

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Signature

2262102
Sbeet No.

Gate - Pin

Definitions

CLKIRC

4

UEEI05-2

RC term used in development of CLKTI-.

CLK2RC

4

UEEI05-12

RC term used in development of CLKT2-.

CLK3RC

4

UBE072-8

RC term used in development of CLKT3-.

CLRCNTR-

14

UFKI05-8

Clear shift counter.

CLRSECIDX-

13

UJJ072-12

Clear sector latch and index latch.

CLRWRTQ-

5

UEE094-2

Clear Write. Latched and synchronized microcode interrupt condition that is generated if
a FIFO timing error occurs during a disk
write operation. Synchronized verSIon of
WRTTIMERR-.

CMDFRECLK-

5

UDKl15-3

Command frequency clock. Approximate 320 Hz
output of RC-controlled NE555 timer that is
counted down to produce the 200 millisecond
command timer delay.

CMDTMRCLK

5

UDKI05-6

Command timer clock. Gated version of 320 Hz
CMDFREQCLK-.

CMDTMRCLR

5

UJDI05-11

Command timer clear generated as a result of a
general reset or a trigger timer microinstruction.

CMDTMRDLY-

5

UFEI05-7

Command timer delay. The command timer
allows a 200 millisecond (approx) time frame for
an operation to occur. Generates a microcode
interrupt if the timer is allowed to expire.

CMDTMRQ-

5

UEE094-12

Command timer delay, latched. Latched and
resynchronized (to microprocessor clock) version
of the command timer delay. Enables command
timer interrupt trap, if low.

CNTEQ15

14

UFEl16-15

Count equals 15. Indicates that the disk clock bit
counter has reached a count of 15. Used to keep
track of 16-bit words as they are shifted through
the serial/ parallel shift register during disk read
and write operations.

CPKONES

7

UDE028-13

Command CPE K-bus to all ones. Disables K-bus
input multiplexers placing all low levels on CPE
K-bus inputs. These low levels are interpreted as
data ones by the active-low K-bus.

CPK (00-15)-

7

UAK017,
UDE017,
UDE039,
UAK039

K-bus active low inputs 0-15.

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Definitions

CPLCK-

8

UDE06l-8

CPE left byte clock. Microprocessor clock
(MPCK-) input to the left byte CPE array, gated
by microinstruction word select field (ROM08,
09), CPE clock stop (ROMOO) and the TRAP
signal.

CPRCK-

10

UBK083-8

CPE right byte clock. Microprocessor clock
(MPCK-) input to the right byte CPE array gated
as described with CPLCK-, above.

UBE036,
UCC036,
ueC05l,
UBE05l,
uecOO6,
UBE02l,
ueC02l,
UBEOO6

Right shift outputs of CPE devices to shift
inputs (LI) of less-significant CPE stages.

epSHIFT

8, 9,

(L,3,9,6-8)

10, 11

CPUID

13

990 chassis
(UAKl05-1)

Central processor unit identifier. The input pin
floats (and is pulled high) in a 990/9 chassis. The
input is grounded (logic zero) for a 990/ 10 chassis.
The distinction between processors is necessary
due to minor differences in TILINE timing.

CPXL

12

UAK050-7

Carry propagation output from CPE left byte
carry generator.

CPXLA

12

UAK061-4

Carry propagation output of CPE left byte carry
mUltiplexer.

CPXR

12

UAKOO6-7

Carry propagate output from CPE right byte
carry generator.

CPXRA

12

UAE072-9

Carry propagate output from CPE right byte
carry multiplexer.

UBE036,
Uee036,
uee051,
UBEOSl,
UBE021,
UeeOO6,
UBEOO6,
Uee021
UBE036,
Uee036,
UeeOSl,
UBEOSl,
UBE021,
UeeOO6,
UBEOO6,
UCC021

Carry propagate outputs from individual CPE
devices to carry generators.

CPX (0-7)

8, 9,
10, 11

CPY (0-7)

8, 9,
10, 11

Carry propagate outputs from individual CPE
devices to carry generators.

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Gate - Pin

Definitions

CPYL

12

UAKOSO-IO

Carry propagate output from CPE left byte carry
generator.

CPYLA

12

UAK061-12

Carry propagate output from CPE left byte carry
m u]ti plexer.

CPYR

12

UAKOO6-10

Carry propagate output from CPE right byte
carry generator.

CPYRA

12

UAE072-12

Carry propagate output from CPE right byte
carry mUltiplexer.

CRCDATIN

19

UHDIOS-9

CRC data in. Serial read or write data into CRC
generator / checker.

CRCDATOUT

19

UGEIOS-12

CRC data out. Serial CRC character out of CRC
generator / checker at the end of a write operation
(header or data) to disk.

CRCENFLAG

18

UHJ028-14

CRC enable flag. Used to enable data input to (or
CRC character out of) the CRC checker/
generator.

CRCERR

19

UGEI05-13

CRC error. Indicates that the CRC character
calculated on read did not agree with the CRC
character recorded at write time.

CRCPREFLAG

18

UHJ028-13

CRC preset flag. An output of the disk write flag
register which presets the CRC generator to all
ones prior to writing data to the disk.

CRCPRES-

17

UGE050-7

CRC preset. Preset signal enabled by the sync
character detector (read) or CRC preset flag
(write). Presets CRe generator/checker to all
ones.

DATCLK

19

UJDIOS-6 or Disk data write clock input to write data out F / F.
UHJIOS-8
In phase with DCLK and DCLOCK unless phase
(Jumper
inverting jumper J5 is installed.
Selected)

DBUSHI

14

UJD017-9

Disk bus high. Most significant bit out of. disk
(cylinder) address register. Inverted to supply
ADD256-.

DCLK

19

UFKl16-14

Disk clock. Clock signal for disk interface circuits.
Supplied by crystal oscillator and divider for write
operations, disk for read operations, microinstructions for self-test operations.

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Definitions

DCLOCK-

19

UJD094-S

Disk read or write clock.

DC LOCK

19

U.TDI05-6

Disk read, write or test clock.

DCLKl-

19

UFKl16-9

Inverted form of DCLOCK. Not used unless
excessive write skew requires installation of clock
phase correcting jumper J5.

DCRCERRQ-

IS

UFK02S-S

eRC error, latched.

DIAGFAULTQ-

13

UFK050-12

Diagnostic - fault. Output 01 microinstruction
special group I decoder/register which indicates
that a fault was detected during controller selftest. Inhibits read, write. lights FAULT indicator.

DIRDATEN-

15

UFE050-11

Direct data enable. Enables 3-state outputs of
direct read register onto the processor bus. Used
during record leader verification when FI FO is
bypassed.

DISKDATIN

19

UHD094-9

Disk data in. Serial read data from the read data
buffers to the serial input of the serial/ parallel
shift register.

DISKDATLD-

14

UJD094-6

Disk data load. A strobe issued during disk write
operations which loads parallel data into the
serial/ parallel shift register. Data is shifted out of
the register (serially) to the write data encoding
circuits.

DISKSEL-

14

UJJ061-12

Disk Select. When low, selects the fixed disk.
When high, selects the removable cartridge.
SELECT A- and SELECTB- are also required to
complete the selection.

DSKBUSLD

12

UFE028-9

Disk bus load. Loads inverted processor bus outputs PBUS07- through PBUS15- into disk address
register. Output of disk address register is cylinder
address ADDOOl- through 256- to disk drive.

DSKCLR-

13

UJJ072-14

Disk clear. Microinstruction-controlled clear to
disk interface logic of controller.

DSKDIRECT-

13

UGE039-4

Disk direct. When low, disables FIFO input, and
partially enables direct read register outputs to
P-bus.

DSKDIRQ

13

UFK050-7

Disk direct mode. Microinstruction-controlled
mode bit.

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Definitions

DSKOSC

19

UJJ12S-S

5MHz output of oscillator used to clock write
data to the disk drive.

DSCOSC-

19

UHJl16-12

Disk Oscillator. Gated verSIOn of 5MHz disk
oscillator output. Used to clock disk interface
logic during write operation.

DSKSHIN-

18

UHJl16-6

Disk shift in. Shifts disk read data from the
serialj parallel shift register into the FIFO buffer.

DSKSHOUT-

18

UFKI05-11

Disk shift out. Unloads data from FIFO output
stage during write operations.

DSKSTRQ

14

UJJl16-9

Disk start transfer latch output. Set by a microinstruction at the beginning of a disk read or write
operations.

DSKSTRRST-

13

UJJ072-13

Reset disk start transfer Fj F. Clears disk interface
logic as the result of a microinstruction command.

DSKSTRTCK-

13

UJJ072-11

Disk start transfer clock. This pulse is enabled by
a microinstruction and strobed by MPCK- to
form the initial event' of any disk interface
operation.

DSKSTRTR-

14

UJJI05-S

Disk start transfer F/ F summary reset. Clears
disk I j F logic in case of general reset, interrupt
reset, DSKSTRRST-, or DSCLR- microinstruction-controlled reset.

DSTARTQ

14

UHJ094-5

Disk start. Resynchronized (with disk clock) disk
interface start signal.

EG-

13

UJD050-3

Erase gate to disk drive. Enables straddle erase in
disk drive.

ENFLG-

17

UFEOO6-11

Enable flag. Enables FIFO flag multiplexer to
gate H flag bits (FIFOIN16-19) into the FIFO.
The flags accompany write data through the
FIFO.

ENSPEC-

13

UEEOS3-12

Enable special field decoders. ROM32-39 of the
controller microinstruction may be interpreted as
an immediate operand to be loaded on the K-bus,
or as special purpose fields. If ROM 10=0 and
there is no trap, the high level of CLKTI enables
ENSPEC-. ENSPEC- enables the TILINE
operation decoder and the special function group
select decoder.

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Definitions

Gate - Pin

ERRORSET

17

UGE072-12

Error set. Input to FIFO timing error F I F which
sets it in case of a FIFO rate error.

FAULTLED-

13

UEEI05-8,lO

Two-wire ORed open-collector outputs which
light the controller FAUL T indicator in case
the command timer expires (CMDTMRDLY-)
or a fault is detected during self-test
(DIAGFAULTQ-). Note that DIAGFAULTQ
and FAULTQ are microinstruction fields.

FAULTQ-

13

UFK050-11

Microinstruction-controlled fault output from
special group I decoder I register. Lights FA U LT
indicator via FAULTLED-.

FIFODATEN-

15

UFE050-3

FIFO output data enable. Enables three-state
outputs of FIFO outl zero mix onto processor bus
if direct mode is not specified and disk data to
P-bus is specified by the appropriate microinstruction fields.

FIFOOUT (00-19)

17

UFE072 ,
UGE061,
UHD072 ,
UHD028

FIFO output data from 16-word first-inl first-out
buffer. Bits 16-19 are flag bits.

FIFOSEL

15

UFE050-6

FIFO select. Gates FIFO data through the FIFO
outl zero multiplexer to the processor bus and on
to the TILINE line drivers.

FILERDY-

16

Drive
(UJD006-9)

Disk file ready. Output from the disk drive which
indicates the drive is ready for operation; i.e., dc
power ok, up to speed, heads loaded, no faults
detected, terminator installed. Inverted in
controller as OFFLIN E-.

FLED-

13

UFK094-6

Fault LED. Lights FAULT indicator in case of
microinstruction-specified fault during normal or
self-test operations.

GO

2

UDK094-6

Inverted output of GO gate that is used during
TILINE master cycle to supply the TILINE GO
line driver.

GOINH

2

UBK094-8

Go inhibit. Prevents the setting of the GO gate if a
TILINE GO or TILINE terminate is active when
the master access logic reaches the device access
state.

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Definitions

GROUPOO-,
01-, 10-, 11-

13

UEE050

Microinstruction special group 0-2 decoder
enabling signals. ROM34, 35 are decoded to
enable the special group microinstruction
decoders. Requires ENSPEC- low.

HDSEL-

13

UJJ028-6

Head select. Output to the disk drive that selects
the upper surface (HDSEL- low) or the lower surface (RDSEL- high) of the selected platter.

IDLE

19

UFK094-8

Idle. An input to the CRC multiplexers that forces
CRCDATIN low when not checking read data or
write data.

INDEXMRK-

16

UHJ039-6

Index mark, latched. The index mark is a
reference pulse (supplied by the disk drive) which
occurs once every disk revolution. The index
mark is latched as INDEXMRK-.

INDEXMRKQ-

16

UFK039-10

Index mark latched for I-bus input and resynchronized to microprocessor clock.

INDMRK-

16

Disk Drive
(UJJ039-4)

Index mark. Generated by sensors in the disk
drive once per revolution. Identifies the start of
sector O.

INRDY-

16

UFE061-6

FIFO summary input ready. Indicates FIFO
buffer has space available for loading additional
input data.

INTA-

5

UFE094-14

Interrupt A. Group select output of the interrupt
address encoder that indicates, when low that at
least one active, synchronized microcode interrupt
condition is present. Used (in inverted form as
INT A) to enable the TRAP- signal and to enable
INTB, which disables TRAP- after one clock
time.

INTAD(0-2)

5

UFE094~6,

Interrupt address bits 0-2. Outputs of the interrupt
address encoder that form part of a trap vector
address for the highest priority active (and
synchronized) interrupt condition.

7, 9

INTB

5

UEE094-15

Interrupt B. Interrupt B goes high one clock time
after INT A goes high. INTB (in inverted form as
INTB-) disables TRAP- one clock time after
INT A. INTB also prevents trap conditions from
occurring too close together.

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Definitions

Gate - Pin

INTRST-

5

UCEOS3-S

Interrupt reset. Clears the unsynchronized
interrupt latches after the synchronized interrupt trap operation starts. INTRST - (CLKOFF.INT A)-.

INTTRAP

5

UFEOO6-6

Interrupt trap. This signal forces the NRA 06-09
multiplexer outputs to all zeros as part of a microcode interrupt trap operation. INTRAP is
essentially an inverted form of TRAP-, but it is
not enabled for TILINE slave trap operations.

IORES-

2

UAK094-S

110 reset. TILINE 110 reset input to TILINE
abort interrupt trap latch.

IRDY A- IRDYD

17

UFE072-2,
UGE061-2,
UHD072-2,
UHD02S-2

Input reasy. Outputs from individual five bit by
16-word FIFO devices which indicate that the
FIFOs are ready to accept additional input data.
Summarized as INRDY-.

LFBYT-

10

UCEOS3-6

Left byte only. Decoded from word select field
(ROMOS, ROM09) to disable clock to the right
byte and disable the right byte carry multiplexer.
See RTBYT-.

LIR-

12

UDE050-7

Output of right shift multiplexer which supplies
right shift input (LI) of right byte CPE array.

LMXSEL

7

UBE094-12

Left byte K-bus input multiplexer select. Steers
eight-bit immediate operand field of microinstruction through multiplexer to K-bus inputs.

MI2V

19

990 chassis
(PI-41)

Negative 12 volt dc power for TMS3129
TESTDATA shift register (UFKI27-4).

MCUADR
(1-9)

6

UH JOO6 ,
UHD006,
UGEOO6

Microcontrol unit address, bits 1-9. Outputs of
the SN74S4S2 address generators which select the
.40-bit microinstruction from ROM.

MCUCI (1-3)

6

UFKOO6,
UGEOO6,
UHD006

Microcontrol unit carries. M CU CI 1 is generated
by the branch decoder ROM and is used for
address incrementation. The other carries are
between the 'S482 address generators.

MCUS (1-6)

6

UFKOO6

Microcontrol unit select code. This code,
developed by the branch decoder ROM, determines the operation(s) to be performed by the
address generators.

MDAC

3

UCEI05-9

(Master) device access. Output of device access
F I F which identifies the device access state of the
TILINE master cycle.

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Uefinitions

MDACCK

3

UAKI05-9

(Master) device access F / F clock. This multiplexer-selected clock pulse clears the device access
state at the end of a TILINE master cycle.

MDACRST

3

UBKI05-1

(Master) device access reset (990/9 only). Source
for MDACCK selected by the CPU ID multiplexer in a 990/9 chassis.

MDACSET-

3

UBKl16-11

Device access F / F unconditional set. Advances
the TILINE master cycle from the device
acknowledge state to the device access state,

MDACT

3

UDEI05-9

(Master) device active F / F output. Indicates that
the TILINE master access logic is performing a
master cycle. Disables microprocessor clock,
enables the 20-microsecond timeout delay, latches
up the PBUS control register.

MDAK

3

UCEI05-5

(Master) device acknowledge F / F output. This
F / F when set indicates that the TILINE master
cycle is in the device acknowledge state.

MDAKCK

3

UBKI05-10

Device acknowledge F / F clock. Advances the
TILINE master cycle from the device access
request state to the device acknowledge state.

MDAKCLR-

3

UCE094-6

Device acknowledge F / F unconditional reset.
Clears the device acknowledge F / F when the
TILINE master cycle advances to the device
access state.

MDAR

3

UBKI05-13

(Master) device access request. Initiates the 100nanosecond timer which determines the minimum
time that the master cycle spent in the device
access request state.

MDAR-

3

UBEI05-11

Device access request state. Disables TLAGOUT
to lower priority masters during the period
between the initiation of the master cycle and the
start of the device access state.

MDAREN-

3

UBEI05-6

(Master) device access request enable. Partially
enables the MDAR gate if TILINE access granted
is available and if the TILINE master cycle has
not reached the device acknowledge state.

MDAROK-

3

UDKI05-8

(Master) device access request okay. Output of
delay timer that indicates that the access logic has
been in the device access request state for the
minimum required time.

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Definitions

MDARRC

3

UEEI05-6

RC timing term used in the development of
MDAROK-.

MDCMP-

3

UBE094-8

(Master) device complete. Indicates that the
TILINE data transfer operation is complete. Used
to restore master access logic to the initial state.
NOTE
The MDCMP- and MDTO- gate configuration resembles a latch, but is not a
latch.

MDGO

3

UDEI05-5

(Master) device go. F / F output that initiates
TILINE master cycle and remains active throughout the cycle.

MDTM

3

UBE094-6

(Master) device terminate. Identifies the end of
the TILINE data transfer, and is used to reset
master access logic to the idle state, on leading
and trailing edges.

MDTMEN

3

UAKI05-12

(Master) device terminate enable. An output of
the CPU identification multiplexer used in the
development of MDTM. Equal to hardwired I for
990/9, GO for 990/10.

MDTO-

3

UBEI05-8

(Master) device timeout. Output of 20microsecond (approximate) timer. The timer is
initiated when device active F / F sets. If it expires
before master device complete (MDCMP-),
indicates a hung TILINE cycle.

MDTOL-

2

UDE094-13

Master device time-out, latched. Latched version
ofMDTO-.

MDTOQ-

5

UEE094-5

Latched and synchronized (with MPCK-) version
of MDTO-.

MDTORC

2

UBE116-15

RC timing term (lOll second) used in the develop~
ment of MDTO-. MDTO- is enabled when the
MDTORC voltage reaches the input threshold of
the MDTO- gate.

MPCK

4

UFK094-3

Microprocessor clock. Active high version of
MPCK-.

MPCK-

4

UDE083-8

Microprocessor clock. Active-low main timing
term for controller logic.

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Definitions

MPCK482-

4

UDE083-11

Microprocessor clock (MPCK-) signal with fast
rise time, dedicated to the SN74S482 address
generator clock inputs.

MSBADRINC

13

UlII>050-13

Most significant address register increment.
Output of. microinstruction special group 0
decoder which increments the four-bit TILINE
MSB address register when a TILINE master
operation passes a 65K address boundary.

MSBADRLD-

13

UHD050-14

Most significant address register load. Loads a
four-bit address from the processor bus into the
TILINE MSB address register.

MSBADR (0-3)

8

UlID039

Four most significant TILINE address bits.
Stored in an external TILINE MSB address
register because there are only 16 address bits
available from the CPE array at one time.

MSTRD-

13

UEE050-6

Master read. Output of microinstruction decoder
which initiates a TILINE master read cycle.

MSTSTB

3

UDK061-3

Master cycle strobe. Clock input which triggers
the master device go F / F to set and initiate a
TILINE master read or master write cycle.

MSTWRT-

13

UEE050-7

Master write. Output of microinstruction decoder
which initiates a TILINE master write cycle.

NOTRDY-

16

UJJ039-2

Not ready to start read/write, Inverted form of
RDYSRW- (ready to start read/write) from
selected disk unit. NOTRDY- high indicates that
the head carriage has reached the specified
cylinder and the heads have had time to settle, in
addition to the FILERDY- conditions.

NRA (01-09)

5

UFEOO6,

Next ROM address bits 1-9. Outputs of the NRA
multiplexers, which serve as A inputs to the
address generators.

UHD017,
UFK017
OFFLINE-

16

UJD006-8

Disk offline. Inverted form of FILERDY - from
disk drive.

ORDYA, B,C, D

17

UFE072,
UGE061,
UHD072,
UHD028

FIFO output ready signals from each of the fivebit by 16-word FIFO devices. Indicates that the
FIFO has data available at the outputs.
Summarized as OUTRDY-.

OUTRDY-

16

UFE061-8

Summary FIFO output ready.

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Signature

Sheet No.

Gate - Pin

Definitions

PARDATOO

17

UFK083-12

Parallel data, bit O. Most significant bit, and shift
output, of serial/ parallel shift register.

PARDAT (00-15)

17

UHJ083,
UHD083 ,
UFK061,
UFK083

Parallel data outputs of serial/parallel shift
register.

PBCPE-

12

UEE039-14

CPE to processor bus enable. An output of the
PBUS source decode which enables the threestate CPE D-bus outputs onto the processor bus.

PBDSKDAT-

12

UEE039-11

Disk data to processor bus enable. An output of
the PBUS source decoder which partially enables
the FIFO and disk direct read register three-state
outputs onto the P-bus. Selection between these
sources is determined by direct/ indirect mode
F/F.

PBDSKSTA-

12

UEE039-9

Disk status to processor bus enable. An output of
the PBUS source decoder which enables the threestate status line receiver outputs onto the
processor bus.

PBTLDAT-

12

. UEE039-12

Processor bus sourced by TILINE data. An
output of the PBUS source decoder which enables
data from the TILINE line receivers onto the
processor bus. Controlled by bus source field
(ROMI3-15) of microinstruction.

PBUSENL

12

UEE028-2

Processor bus enable latched. Disables the processor bus source decoder during the time (immediately after MPCK- rising edge) that
microinstruction outputs are unsettled. Signal is
latched only in MDACT- goes active; otherwise,
follows CLKT1-.

PBUS (00-15)
PBZERO-,

8-11
12

Multiple
source bus
UEE039-15

Processor bus.
Processor bus zero. Output of microinstruction
bus source decoder that commands the processor
bus to all zeros (high logic levels).

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PFWP-

3

UAKI05-4

Power failure warning pulse output of CPU
selection multiplexer. See TILINE power failure
warning pulse, TLPFWP-.

RCLK-

19

Disk Drive
(UJJ039-11)

Read clock. One hundred nanosecond (nominal)
active low clock pulses read from the selected disk
track and separated from data by the clock/ data
sepaiatoi in the disk drive.

RD-

19

Disk Drive Read data. One hundred nanosecond (nominal)
(UJD006-13) active low data pulses read from the selected disk
track and separated from clock by the clock/ data
separator in the disk drive.

RDA-

19

UJDl16-4

Read data into preset input of read I F / F.

RDATA-

19

UJDl16-6

Read data output of read I F / F.

RDATAQ

19

UHDl16-9

Read data output of read 2 F / F, converted from
bit cell to NRZ format. Also used to store data in
the test memory during closed-loop self-testing.

RDB

19

UJDl16-2

Grounded D-input of read I F / F.

RDYDIRRST-

13

UJJ072-9

Ready direct reset. Strobed output of microinstruction special group 0 decoder that resets
the ready direct status F / F. Note that the F / F is
in an upside down configuration, and
RDYDIRRST- is wired to the preset input.

RDYDIRSTAT=

13

UJD017-5

Ready direct status. F / F which toggles on first
FIFO/ direct register SHIFTIN pulse after
RDYDIRRST-. Indicates that valid data is
available in the direct read register.

RDYDIRST ATQ-

16

UFK039-2

FIFO ready status. Latched and synchronized
to microprocessor clock for I-bus input.

RDYSRW-

16

Disk Drive
(UJJ039-1)

Ready to start read/write. Active when all file
ready conditions are met and head carriage is at
specified cylinder and head selection transients
have dissipated.

RDYSTATUS-

17

UFK072-4

FIFO ready status. FIFO ready to accept data
(disk write) or supply data (disk read).

RDYST ATUSQ-

16

UFK039-15

FIFO ready status. Latched and resynchronized
to microprocessor clock for CPE I-bus input.

C-lS

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Signature

Sheet No.

Gate - Pin

Definitions

READ-

2

UDE072-5

Slave read. TILINE slave logic read/write mode
F / F output, controlled by TILINE read line
receiver.

READQ-

14

UHD094-6

Disk interface read. Set during disk read
operations after synchronization pulse is detected.

READQQ-

16

UFK039-7

Disk interface read latched and resynchronized to
microprocessor clock for CPE I-bus input.

RESTORE-

13

UJJ061-6

Restore to track zero (also called return to zero
seek). Output to disk drive which drives carriage
to fully extended position and back to the home
position, and clears drive fault latches and
cylinder address register.

RG-

13

UJJ028-10

Read gate. Enables disk drive read circuits.

ROL-

9

UBE051-8

Right shift output of left byte CPE array.

ROM (00-07)

6

UDEOO6

Controller microinstruction ROM output bits 0-7.

ROM (8-15)

6

UDK017

Controller microinstruction ROM output bits
8-15.

ROM (16-23)

6

UEEOO6

Controller microinstruction ROM output bits
16-23.

ROM (24-31)

6

UGE017

Controller microinstruction ROM output bits
24-31.

ROM (32-39)

6

UEE017

Controller microinstruction ROM output bits
32-39.

ROM 13L, 14L,
15L, 20L,
21L, 33L

12

UEE028

Latched versions of the bus source, bus
destination fields and bit 33 of the controller
microinstruction. These are latched in a transparent D latch. When the enable signal,
(MDACT-) is high, the output follows the input.
When MDACT- is low (during TILINE master
access cycle) outputs are latched up.

ROR-

11

UCC021-8

Right shift output of least significant stage of
right byte CPE array.

RST

2

UFK116-7

Reset. General controller interface reset enabled
by TILINE I/O reset (TLIORES-) or power reset
(TLPRES-).

C-16

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Sheet No.

Gate - Pin

Definitions

RTBYT-

8

UDK061-11

Right byte (only). Decoded from the microinstruction word select field (ROM08,09) for
right byte only instructions. Disables CPE left
byte clock and left byte carry multiplexer.

RTSHFTRO

12

UDE050-9

Right shift output of least significant CPE stage
from right shift mUltiplexer. Zero unless right
shift (F-group 0, R-group Ill) is performed.

SECMRK-

16

Disk Drive
(UJJ039-13)

Sector Mark. A rotational position pulse which
identifies the start of each sector.

SECTORB01-, 0204-, 08-

16

Disk Drive
(UJD028)

Sector address. Sampled by the disk controller
after the sector mark is sensed.

SECTORB16-

16

Disk Drive
(U J J050-17)

Sector address. Sampled by the disk controller
after the sector mark is sensed.

SECTORMRK-

16

UHJ039-8

Sector mark - latched. The sector mark latch sets
on the first sector mark after a microinstructioncontrolled clear sector and index (CLRSECIDX-)
pulse. Stores sector mark for the I-bus input latch.

SECTORMRKQ-

16

UFK039-12

Sector Mark. Latched and resynchronized to
microprocessor clock. Provides sector mark input
to CPE I-bus.

SELECTA-

14

UJJ017-2

Select disk drive A. When low, selects the dual
disk drive designated A, usually the first drive.
DISKSEL- also required for individual logical
unit selection.

SELECTB-

14

UJJ017-6

Select disk drive B. When low, selects the dual
disk drive designated B, usually the second drive.
DISKSEL- also required for individual logical
unit selection.

SHFCMD

12

UCE072-13

Shift command. Active when CPEs perform a
shift operation (F-group 0, R-group III). Disables
left and right byte carry multiplexers when active.

SHFTPRE

12

UDE028-4

Partially decoded term used in development of
SHFTPRE- and, consequently, SHFCMD.

SHFTPRE-

12

UDE061-6

Partially decoded term used in development of
SHFCMD.

SHIFT

17

UGE050-9

Shift command used to clock the FIFO timing
F I F. Supplied by SHIFTIN for read operations,
SHIFTOUT for write operations.

e-17

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Sbeet No.

Definitiom

Gate - Pin

SHIFTIN

18

UEE083-8

Shift command to FIFO input circuits. Loads a
20-bit data and flag word into the FIFO.

SHIFTOUT

18

UEE083-6

Shift command to FIFO output circuits. Unloads
a 20-bit data and flag word from the FIFO, so
that the next word in line may be shifted to the
FIFO output.

SIGNBIT-

7

UDK039-3

Sign bit. The immediate operand (I M) field of a
microinstruction contains only eight bits. Except
for left byte only instructions~ the immediate
operand is supplied to the right byte CPE K-bus
inputs, and SIGNBIT- extends the sign bit to all
the left byte K-bus inputs.

SKIC-

16

Disk Drive
(UJJ050-2)

Seek incomplete, also called seek error. Disk
output which indicates that the head carriage
failed to seek to the specified cylinder address.

SLADOK

4

UAE028 ,
UAE050,
UAE083

TILINE slave address okay. Sets the slave
transfer F IF if the received TILINE slave address
equals the local board address as determined by
switches and hardwired address bits.

SLBUSY-

4

UBE083-3

Slave busy. Strobe which returns a hardwired I on
TILINE bit 0 output if a slave read is attempted
on a busy controller.

SLGODLY

4

UDK050-6

Slave go delay. A protective delay (100 nsec)
which assures that the incoming TILINE slave
address has stabilized before it is decoded.

SLGORC

4

UBE072-12

RC term used in development of SLGODLY-.

SLSW (13-16)-

4

UAE0834, 6, 10, 12

TILINE slave address switch outputs.

SLTM

4

UBEI05-3

TILINE slave terminate. Output to the TILINE
terminate line driver. Indicates that the slave logic
has completed the specified operation. If a slave
read is directed to a busy controller, an immediate
slave terminate is issued, accompanied by a data 1
in the data word bit 0 position.

SLTMA-

4

UBE083-6

Slave terminate access. Enables a normal slave
terminate at the completion of a slave cycle (controlled by SL VTRM- from microinstruction
decoder).

C-18

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Defin!!inns

UitU; - • III

SLTMB-

4

UBEOS3-11

Slave terminate B. Enables an immediate
terminate and busy indication if a slave read is
addressed to a busy controller.

SLVA-

4

UDE072-9

Output of one of the two FIFOs which control
TILINE slave operation.

SLVACT

5

UDK039-8

Slave active. Disables interrupt priority encoder
and serves as a slave trap address input.

SLVAD-

4

UDK061-6

Slave cycl~enable. Enables a TILINE slave cycle
if the enable slave bit (ROM 16) of the microinstruction is set and the slave transfer F / F is set.

SLVB-

4

UFK02S-5

Output of one of the two F / F's which control
TILINE slave cycles.

SLVTRM-

13

UEE050-5

Slave terminate. Output of microinstruction
special field decoder, controlled by ROM32, 33.
Causes TILINE slave logic to issue a TILINE
terminate, ending the slave cycle.

SLXFR

4

UBK072-5

Slave transfer. Slave transfer F / F sets upon
expiration of the 100 nanosecond slave go delay if
the incoming TILINE address equals the board
slave address.

SPAREINl-

11

Disk Drive
(UOE039-1)

Spare input (Jl) from disk drive to CPE I-bus.

SPAREIN2-

11

Disk Drive
(UJJ039-5)

Long self-test check jumper (J2), if installed,
grounds SPAREIN2-. This causes the microprogram to execute the long self-test on power-up
for test only.

SP AREIN (3-6)-

16

UJD02S,
UJJ050

Spare inputs from disk drive to disk status word
(processor bus) input.

SPAREOUTI

13

UJJ061-10

Status update strobe. During self-test the
controller microprogram maintains a status count
which is updated as various test segments are successfully completed. SPAREOUTI- is pulsed each
time the status count is updated. Available as a
strobe to synchronize logic analyzer or oscilloscope.

SPAREOUT2-

13

UJJ061-S

Spare output.

SPAREOUTQI-

14

UJJ017-12

Latched spare output. A spare output of the disk
select register.

C-19

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Gate - Pin

Definitions

STBCLR-

13

UJJ072-7

Allows a deliberate clearing of the disk control
functions In the special function 2 decoder /
register.

STBRST-

13

UJJI05-6

Strobe reset. Clears the special function 2
decoder/register in the event of a general reset
(RST-), an interrupt reset (INTRST-), or a strobe
clear from special function 0 (STBCLR-).

STOP FLAG

18

UHJ028-12

Write data (to disk) transfer stop flag. This flag
accompanies the last TILINE-to-FIFO word
through the FIFO. When it reaches the FIFO
output, the transfer to disk should be stopped.

STRTREAD-

14

UOE116-12

Interface read logic clear.

SWAIN-

16

Disk Drive
(UJJ050-13)

Switch fixed/removable unit numbers on drive A,
if low. Controlled by jumper 11-13 of adapter
board mounted on drive A. Normal designation
(SW AIN- high) is:
unit 0 - fixed disk
unit I - removable disk cartridge.

SWBIN-

16

Disk Drive
(UJJ050-11)

Switch fixed / removable unit numbers on drive B,
if low. Controlled by jumper 11-J4 of adapter
board mounted on drive B. Normal designation
(SWBIN- high) is:
unit 2 - fixed disk
unit 3 - removable disk cartridge.

SYNCQ-

14

UOE094-10

Synchronization character detected and latched.
Enables read operations after the 6E synchronization character is detected.

SYNC6E

14

UJ0083-8

Synchronization character present. Goes low for
one disk clock time when the 6E synchonization
character is detected.

TESTBIT-

12

UAK072-9

Input to test bit flip-flop from word look-ahead
carry generator.

TESTBITQ

12

UBK072-8

Output of test bit F / F which steers execution of
all conditional branch and conditional return
microinstructions.

TESTCLK-

13

UFK050-5

Test clock. Microinstruction-controlled clock
pulse which replaces disk read or write clock as
the disk II F timing source during controller selftest. Burst frequency is approximately 833.3 KHz.

C-20

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Definitions

Gate - Pin

TESTDATA

19

UFK127-3

Test data output of TMS 3129 serial shift register
memory used for controller closed-loop self-tests.

TESTMODEQ

13

UFK050-4

Test mode output of microinstruction special
group 1 decoder I register. Sets up data paths for
controller closed-loop self-test.

TESTOUTiN

19

UFK127-6

The TMS 3-129 serial test memory consists of 2
sections, each with a I-by-132 capacity.
TESTOUTIN connects the output of one section
to the input of the other, for a I-by-264 net
capacity.

TESTRDDAT-

19

UFKI05-6

Test read data. Test data out of the serial test
memory to the read data logic, as gated by
TESTMODEQ. Self-test only.

TIMERRQ

14

UGE094-6

FIFO timing error -latched. Detects FIFO errors
during read and write operations such as
attempting to load a full FIFO or attempting to
retrieve data from a FIFO without any data in it.

TLABORT-

2

UCE094-8

TILINE abort. Input to TILINE abort latch
which sets the latch if a power failure warning
(TLPFWP-) or a general 110 reset (lORES-)
signal is received.

TLABORTL

2

UDE094-4

TILINE abort latch. Sets if controller operations
are to be aborted by the power failure warning
pulse (TLPFWP-), the power reset (TLPRES-) or
a general 110 reset (TLIORES-).

TLABORTQ-

5

UEE094-10

Latched and synchronized (with MPCK-) version
of TLABORTL. This microcode interrupt signal
generated if a power failure warning, power reset,
or 1/0 reset is issued to all the controllers in thel
990 chassis.

8, 9,
10, 11

CPE
devices,
TILINE

TILINE address. A 20-bit address which accompanies any word transferred on the TILINE.

TLAGIN

3

TILINE
(UCE094-2)

TILINE access granted input from higher priority
masters. TLAGIN must be high for the TILINE
master cycle to initiate the 100 nanosecond device
access request minimum timer.

TLAGOUT

3

TILINE
(UCE094-3)

TILINE access granted output to lower priority
masters. TLAGOUT is disabled during the device
access request and device acknowledge states of
the TILINE master cycle.

TLADR (00-19)

C-21

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Gate - Pin

Definitions

TLAK-

2

TILINE
(UBEl16-9)

TILINE acknowledge. As an input, must be
inactive (high) for the TILINE master cycle to
advance to the device acknowledge state. As an
output, is asserted during the device acknowledge
state.

TLAV

2

TILINE
(UBEl16-7)

TILINE available. As an input, must be active for
the TILINE master cycle to advance to the device
access state. Disabled by the controller in device
access sate.

8, 9,
10, 11

UAK028 ,
UAE061,
UAE017,
UAK083

TILINE data.

TLDATEN-

2

UDK072-6

TILINE data enable. Enables TILINE data line
drivers during a master write or slave read cycle.

TLERR-

2

UBK083-6

LINE error. Sets the TILINE error latch if a
rity error (TLMER) is returned by TILINE
memory during a master read cycle.

TLDATA (00-15)-

&

TLERRL-

2

UDE094-7

TILINE error latch output. See TLERR-.

TLERRQ-

5

UEE094-7

Latched and synchronized version of TLERRL-,
used in interrupt trap circuits. Initiates a microcode interrupt trap if a memory parity error is
detected while the controller is reading data from
990 memory for transmission to the disk.

TLGO-

2

TILINE
TILINE go. Control strobe asserted by a TILINE
(UAE094-15) master throughout a data transfer. Used by slaves
to enable slave address decoding, initiate slave
response.

TLINT-

13

UBE072-2

TILINE interrupt. Disk controller interrupt to the
990 CPU. Enabled by a special group 1 microinstruction.

TLINTLED-

13

UBE072-4

TILINE interrupt indicator. Light-emitting diode
indicator that lights when the controller sends an
interrupt (TLINT-) to the 990 CPU.

TLINTQ

13

UFK050-9

TILINE interrupt. Output of microinstruction
special group I decoder I register which enables an
interrupt (TLINT-) to the 990 CPU.

TLIORES-

2

TILINE
TILINE 110 reset. Master clear signal from 990
(UAE094-7) CPU to all I10 controllers.

C-22

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2262102
Signature

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Definitions

- .....

TLMER

2

TILINE
(UAK094-4)

TILINE memory error. Asserted by TILINE
memory if a parity error is detected as part of a
memory read operation.

TLPFWP-

3

TILINE
(UAKI05-2)

(TILINE) }3ower failure warning pulse. Advance
notice from the 990 power supply that a power
failure is imminent. Precedes power reset.

TLPRES-

2

TILINE
(UDE094-3)

(TILINE) Power failure reset. Reset signal from
990 power supply that assures that I/O logic is
cleared, and that it restarts in an orderly manner.

TLREAD-

2

TILINE
(UAE094-3)

TILINE read.
operations.

TLSHIN-

18

UBK094-11

TILINE shift in. Generated during write data or
write data unformattted operations to shift data
from the TI LINE line receivers into the FIFO.

TLSHOUT-

18

UBK094=3

TILINE shift out. Generated during read data or
read data unformatted operations. Shifts a new
word to the FIFO output after a word is transmitted to 990 memory via a master write cycle.

TLTM-

2

TILINE
(UBEl16-2)

TILINE terminate. Asserted by TILINE slave
when read data is available or write data has been
accepted.

TLWAIT-

2

TILINE
(UAE094-9)

TILINE wait. Asserted only by TILINE bus
couplers.

TRAP-

5

UDK072-8

Trap signal that steers the next ROM address
multiplexers to gate a trap vector address to the
address generators. Generated while servicing a
TILINE slave trap, microcode interrupt trap,
power or I/O reset trap.

TRIGTMR-

13

UJJ072-10

Trigger command timer. Output of microinstruction special group 0 decoder that retriggers
command timer, preventing expiration of the 200
millisecond delay.

UNITA

14

UHJ017-5

Select unit A. Disk select output which when high
specifies the dual disk drive designated A (the first
drive). Requires DISKSEL for complete selection
of a logical unit.

UNITB

14

UHJ017-2

Select unit B. Disk select output which specifies
dual disk drive B. Requires DISKSEL for
complete logical unit selection.

C-23

Identifies

read/write TILINE

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Definitions

Gate - Pin

UNITLOAD-

12

UFE02S-11

U nit load. Loads the disk selection signals from
the processor bus into the disk select register.

UTCSHIN-

12

UFE02S-10

UTC shift in. Loads a word from the CPE outputs
into the FIFO, such as when writing headers
during a write format operations.

UTCSHOUT-

18

UFE050-S

UTC shift out. Unloads a word from the FIFO
output when the CPE has accepted the word, such
as during self-tests.

WCHK-

16

Disk Drive
(UJJ050-6)

Write check, also called fault. Indicates that the
disk drive electronics has detected a fault
condition and inhibited write and erase currents.

WCLK

19

UJDI05-S

Write clock. A 5MHz square wave (200 nanosecond pulse width) clock used to encode write
data and clock.

WCLKAQQ-

19

UJJ116-6

Write clock divider output. The 2.5 MHz output
of clock divider. Serves as the source for DCLK
(disk clock) during write operations. Also used in
write data and clock encoding.

WDNCLK-

19

UJD050-6

Write data and clock. Double-frequency (FM) bit
cell encoded data and clock to disk drive.

WDNCLKEN

19

UJDI05-3

Write data and clock enable. A signal used in
write data and clock encoding. Always high at
clock time. high at data 1 time, low (to inhibit
output pulse) at data 0 time.

WG-

13

UJD050-S

Write gate, to disk drive, enables write current.

WOSCSTOP-

19

HHI24

Write oscillator stop. External test input.

WOSTST-

19

JJI24

Write oscillator stop external test input.

WP-

16

Disk Drive
(UJJ050-S)

Write protect. Indicates that data may not be
written to the selected logical unit because the disk
drive WRITE PROTECT switch for that fixed or
removable disk is ON.

WRITEQ

14

UHJ094-9

Write, latched. Output of write FIF in disk I/F
start and readlwrite control logic.

WRITEQD

14

UFK094-11

Input to write F I F in disk II F start and readl
write control logic. Enabled when microinstruction specifies a write operation
(DSKWRTQ = 1) and the disk start F;F
(DSTARTQ) sets.

C-24

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Gate - Pin

Definitions

WRTDATD

19

UHDI05-7

Serial output of write data CRC multiplexer to
write data and clock encoding circuits.

WRTDATOUT-

19

UHD116-5

Serial write data out, in NRZ form to write data
and clock encoders. Also, self-test write data to
serial test memory via read 2 (RDATAQ) F/F.

WRITTIMERR-

5

UFKI05-3

Write timing error. Generated if a FIFO ti..1lling
error is detected during a write to the disk. This
signal is synchronized (as CLRWRTQ-) to initiate
a microcode interrupt trap routine.

ZERO DATEN-

15

UCE094-11

Zeros or data enable. Enables three-state outputs
of FIFO data out/zero multiplexer onto processor
bus.

C-2S/C-26

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~------~

946262-9701

APPENDIX D
MICROCODE FLOWCHARTS

Digital Systems Division

~ ___9_4_6_26_2_-9_7_01______________________________________________
APPENDIX D
MICROCODE FLOWCHARTS
D.I GENERAL
The disk controller operations are controlled by a microprogram which is permanently burned into a
set of five ROM devices. The microprogram consists of 512 words of 40 bits each. This appendix
contains a complete set of flowcharts for the microprogram. The flowcharts, together with the
listings of Appendix E, form a powerful tool for trou~leshooting and analysis at the most detailed
level. The flowcharts also provide insights into controller operation that cannot be provided by a..TlY
other means.
The principle flowchart in Section 2 (figure 2-10) shows the overall program organization and the
relationship between the major routines.
D.2 USING THE FLOWCHARTS
Each process block in the flowcharts represents a single microinstruction, which may also be
considered a controller state. Each block is identified by a three-letter mnemonic (ID L, INI, RDU)
and a two-digit decimal number. The mnemonic identifies the routine or subroutine, and the number
identifies the individual state (microinstruction). The three-digit hexadecimal address of the
instruction is also shown adjacent to each process block. The identifiers and addresses also appear in
the microprogram listings to simplify cross references between the two forms of documentation.
The information within each process block summarizes the 3002 CPE operation and identifies the
most important of the other functions performed by the microinstruction. Table D-l defines the
symbols which are used in the process blocks. Registers RO-R9, T, and AC refer to registers internal
to the 3002 CPE devices.
Conditional branches or returns are represented by a process block and a decision block. The
decision is based on the carry or right shift output of the ePE operation. The process block
associated with a conditional branch/return usually specifies ePE clock stop (CLKSTP). The CPE
clock stop inhibits the clock input to the CPE, but does no~ affect microprocessor clock to other
parts of the controller, such as the ROM address generator. The CPE clock stop allows the CPE to
perform nondestructive bit testing and select the next microprogram address without changing the
contents of any CPE registers. Refer to the 3002 CPE description and the test bit de~cription for
additional information.
Table 0-2 is an index to all the flowcharts in this appendix. The flowcharts are arranged
alphabetically by mnemonic. The sheet numbers refer to the sheets of figure 0-1, rather than to
page numbers in this appendix.
Figure 0-2 contains a short microcode segment (SKS subroutine) that has been superseded by ECNs
428322 and 428323.

D-I

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Table D-l. Symbols Used in Flowcharts
Symbol

Definition

I

Data on the I-bus

CI

Carry In

LI

Left In

CO

Carry Out

RO

Right Out

AC

Contents of the accumulator

T

Contents of T

MAR

Contents of the memory address register

+

Two's complement addition
Two's complement subtraction

/\

Logical AND

V

Logical OR
Exclusive-NOR
Deposit into

L

(Subscript) Left byte operation

R

(Subscript) Right byte operation

D-2

Digital Systems Division

Note: Offsheet references take the form "D-X" or "D-X, Y" and should be read "see Figure D-X, sheet Y."
Note: 'Refer to figure D-2 for SKS subroutine prior to ECNs 428322, 428323.

D-3

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DIGITAL SYSTEMS DIVISION
HOUSTON. TEXAS

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Figure D-l. Microcode Flowcharts (Sheet 1 of 101)

D-4

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Digital Systems Division

~------~

946262-9701

937500
DWG NO

NOTES CONTI NUED:
~ WHEN SHIPPED WITH AN ENCLOSURE REQUIRING AN AMERICAN STYLE NEMA 6-15 PLUG,
REPLACE THE PLUG ON THE DRIVE WITH A 972529-2 PLUG lAW FIGURE 1 AND TEST PER
940040-9901. NO OTHER PLUGS ARE TO BE SHIPPED AS PART OF THE 937500 KIT
WHEN THE SUBSTITUTION IS MADE. THE DRIVE VOLTAGE MUST BE SET PER KIT DASH
NUMBER REQUIREMENT. IN LEU OF REPLACING THE POWER CORD CAP ON KITS REQUIRING·
THE 937513-9 DRIVE, THE 937513-4 DRIVE CAN BE USED AS A SUBSTITUTE.

[1J

I

937500-0039

-0038
-0037
-0036
-0035
-0034
-0033
-0032
-0031
-0030
,1 r -0029
~ 937500-0028
~37g;o -002. 7
4.

KIT, 10 MB CAB DISK, SEC DISK, 240V, 50 Hz
~
CAB DISK, PRIM DISK, 240V, 50 Hz
CAB DISK, ~1ASTER, 240V, 50 Hz
CAB DISK, SEC DISK, 220V, 50 Hz
CAB DISK, PRIM DISK, 220V, 50 Hz
CAB DISK, MASTER, 220V, 50 Hz
RACK DISK, SEC DISK, 240V, 50 Hz
PRIM DISK, 240V, 50 Hz
~1ASTER, 240V, 50 Hz
SEC DISK, 220V, 50 Hz
PRIM DISK, 220V, 50 Hz
KIT, 10 MB RACK DISK, MASTER 220V, 50 Hz

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KIT.. 10 Me, RAc..K
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la Mt:6A BYTe 0151<
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~------~

946262-9701

NOTES:
I. REMOVE ADHE5/VE COVER FRO/V1
LA8EL
PH ~4004c..
2. IAJ5TALL LAI3EL ON DISK
DRIVE A:5 5f10WN l3ELOvv. MAKE
5(JR.E Or CORR.ECT VERTICAL. ALI6AJMEIVT
WITf.I !30TI-I EIJDS. MAKE .sURE OF
CDeeECT HO£.IZOAJTAL AL.16A.JMEAlT
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TV Ski /TCI-IE:5.

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1000001

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J17~
_~_ _- _
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LABEL 22.b2106
TOP V1E.W
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Jd75\
_ _ _ _ __
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DWG NO

937500

TABLE I
KIT IDENTIFICATION UNDER 937500

10 MB DISK KITS WITH DISK PACK
...................._ - ' RACK MOUNTED
CABINET MOUNTED
MASTER
PRIM
SEC
MASTER --. --_._-------_.-.
PRH~
SEC
--- .. - -... .. --0009
-0008
-0010
-0017
-0018
-0019
.
..._- ._._._- -.---.- ._- .._ - -0025
-0026
-0027
-0022
-0023 I_.::OO.~~
-0001
-0003
-0004
-0011
-0012
--_...---- --0013
--\
-0028
-0029
-0030
-0034
-0035 +- -0036
-0005
-0006
-0007
-0014
-0015
-., -." . _.... t·"'-0016
----...._- I
-0033
-0037
-0031
-0032
- 00~8__-1.-=-0039__
....

KIT,
KIT,
KIT,
KIT,
KIT,
KIT,

DISK,
DISK,
DISK,
DISK,
DISK,
DISK,

100V,
100V,
120V)
220V,
230V,
240V,

50
60
60
50
50
50

Hz
Hz
Hz
Hz
Hz
Hz

~

-_

:+

I

10 MB AUXILIARIES
r-----------,--------------.
. . . .-----

SPARE PARTS
WITH PWB
DRIVE ONLY
---I
-0021
-0020

INTERFACE
ONLY
-0002

KIT, 50 OR 60 Hz

~----------------~------------------~------------~----------

~~

I_~
TEXAS,}c~~p1~~~ENTS
Dallas TtxlM

OWN

K. Doerfler

REV

Cj-TE

7/25/79

ISSUE DATE
SCALE

I

I

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6

IAA

t
G-8

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~~-----------------~

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VJIRf"

WIRE

REC.ONFIG

FUSE
-+---

BROWN WIRE
GR£t;N / YELLOW
BLUE WIRE

WJRE

F I GUR.E
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(TERMINALS SEEN F120M TOP)

REV

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~--~---~

946262-9701

t

APPLICATION
PRO). NO.

DASH NO.

y

REVISIONS
DATE

DESCRIPTION

LTR

~Lj>,': ,~" ~. "

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(1)

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946262-9701
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TEXAS INSTRUMENTS

~

INCORPOR"TED

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(

NUMSfR

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QUANTITY

UNIT
Of
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ASSEMBLY

ORIGINAL COPY
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DWG.
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PAGE 1

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-

II

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VENDOR PART NUMBER

DESCRIPTION

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CDC DISK CONTRf'LLER

2<'62100-0001

EA

aOOOl.OOO

LIST 01' MATERIAL

o 1I26/82

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9H505-1 I S AN ACCEPTABLE

OOOlA

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SUI3ST HUTE FOR

000113

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CABtE ASSY,40 PIN,20FT

FA

0937516-0001

CABLE ASSY,50 PIN, 20FT

EA

0937510-0001

CABLE ADAPTER,10 MEGA BYTE DISK

0002

Oll,)Ol.OOO

EA

Oa03

00001.000

0004

00001.000

0005

REF

til

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0931503-9901

SPECI FICA TlON, DISK CONT,10 "lE:;A BYTE

REF

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EA

0937509-9901

TEST PROC,SYS,10 ''It:GA BYTE DISK

OOOtl

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D[ SI( DRIVE,60HZ,120V,RACK "lOUNT

0009

00001.000

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0937507-0001

O[SC CARTR[OGE,TYPE 5440-HJGH DENSITY

0010

00001.000

EA

0<)40042-0001

LABEL,10 MEGA BYTE D[SK DRIVE

EA

2261625-<)901

OIA,FAMILY TREE,lO "lEGA BYTE DISK

0:)01

B34484-68

I

0012
0013
0014

REF
00001 • .100

EA

0996 745-0001

CABLE CARRI ER

OJ009.000

EA

0972632-0016

STRAP,TlEOOWN 14 112 LG,BUNOLE DIA 0-4

EA

09'06261-9701

MNL,OS10 DISC SYS INSTAlLATlON/OPER-9901

0015

00001.000

OOlT

00001.000

0018

00001.000

I

EA

2262101-0001

I KIT, RETRACTOR

EA

0<)45180-0001

ILABEl,OSlO SWITCH SETTING

I 006383-SEf II

I
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':!'R4
,
' /-Z7-#Z

I

I

DATE

OAT':

APPO.-MFG.

DATE

I""". PROJ,er'NGINl!!!

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D~GN EfG>EER

DATE

DATEI ........ O
DATE

~ TEXAS INSTRUMENTS
INCORPORATED
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ITEM

QU~~

UNIT
Of

I
KIT 010 MB lUCK O[SK, MASTER ,120V, 60HZ

175;0

ILM0937500-0001 A'S

[

ORIGINAL copy
DATE

DWG

I TITLE

01126/82

LIST 01' MATERIAL

PAGE

2

00001.000

EA

2262106-0001

DESCRIPTION
LABEL, OS 10 LOGICAL UNIT,PRIMARY

0028

00001.000

EA

2268591-9901

MNl,REPACK INSTR(;,ClSI0 DISK DRIVE

..........y

ISSUE

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PART NUMBER

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DATE

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DATE, TInE

DATEjDeolGNENGINEER

KIT ,10 "IB UCK ot SK, MASTER, 120V ,l'>OHl
APPO.·MfG

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DATEI ........O

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LM0931500-0 0 01

DATE I..aJECTNO

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Sd75\
_ _ _ _ __
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INCORPORATED

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DATE

UNIT

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00001.000

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00001.000

0004

00001.000

0937515-0001

CABLE ASSY,40 PlfII,20FT

EA

0937516-0001

CABLE ASSY,50 PIN, 20FT

EA

0937510-0001

CABLE AOAPTER,10 MEGA BYTE OISK
SPECIFICATlON,OISK CONT,10 ME:;A BYTE

EA

0005

REF

EA

0937503-9901

0006

REf

EA

0931509-9901

0007

REF

EA

0940040-9901

REF

EA

2261625-9901

DIA,FAMllY TREE,10 MEGA BYTE DISK

EA

0946261-9701

"fIIL,OS10 01 SC SYS I NSTALLATION/OPER-990

0009

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931505-1 I S AN ACCEPTABLE

QOO2

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CDC DISK CONTROLLER

2262100-0001

0001B

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PAil NUM'"

PAGE

DESCRIPTION

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PART NUMBER

oz,

ISSUE

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LIST

01126/82

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TEST PROC,SYS,10 MEGA BYTE OISK

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00001.000

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0005

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01/26/82

NUM"'!

LIST Of MATERIAL

PAGE

1

I

0937513-0001

I

0937 507-0001

DISC CARTRIIlGE.T'fPE 5440-HIGH DENSITY

EA

093653't-9901

PACKING PROC,lO 118 OISK OR,RACK MOUNTED

REf

EA

0937509-9901

TEST PROC,SYS,10 MEGA BYTE OISK

EA

0940042-0001

LABEL,10 MEGA BYTE DISK ORIVE

REF

.... NUMIE.

VENDOR PART NUMBER
I 11'4'+81,-68

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PART NUMBER
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IILMD931500-0002
....
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2261625-9901

OIA,FAMILY TREE,IO MEGA BYTE JISK

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00001.000

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0996745-0001

CABLE CARRIER

016499-CC 11

0009

00009.000

EA

0972632-0016

STRAP,TlEOOWN 14 112 LG,BUNOLF nlA 0-4

006383-SEE TI

0010

00001.000

EA

0946261-9701

""IL,OS10 DISC SYS INSTALLATION/OPER-990

0017

00001.000

EA

2262107-0001

KIT,RETRACTOR BRACKET,OS10

0018

00001.000

EA

0945180-0001

LABEL,OSlO SWITCH SETTING

0026

00001.000

EA

2262106-0001

LABEL,OS10 LOGICAL UNIT,PRIMARY

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2268591-9901

I1"1L ,REPACK INSTRC,DS10 OISK DRIVE

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ORIGINAL COPY
DATE

!:

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DATE

LIST

01/2&/82

ORIGINAl. COPY

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PAGE

1

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09)7513-0001

DISK DRIVE,bOHI,120V,RACK MOUNT

0002

00001.000

FA

0931501-0001

DISC CARTRIDGE,TYPE 5440-HIGH DENSITY

UU03

(JOOOl.OOf)

EA

0937515-0001

CABLE ASSY,40 PIN,20FT

00001.00\.1

EA

0931516-0001

CABLE ASSY,50 PIN, 20FT

00001.000

EA

0931510-0001

CABLE ADAPTER.I0

REF

EA

093&534-9901

PACKING PROC,lO I1B DISK DR,RACK MOUNTED

I

REF

EA

0931509-9901

TEST PROC,SYS,10 MEGA BYTE DISK

I

EA

0940042-0001

LABEL.I0 MEGA 8YTE DISK DRIVE

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0007
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0996145-0001.

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0945180-0001

LABEL, OSLO SWITCH SETTI NG

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00001.000

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2262106-0002

LABEL,DSIO LOGICAL UNIT,SECONOARY

0028

00001.000

EA

2268591-9901

MNl,REPACK INSTRC,DSI0 DISK DRIVE

0030

00001.000

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0912031-2100

NETWORK,RES 100

REF

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VENDOR PART NUMBER

0011

0010

Jl'AItTNUMlER

ILM0931500-0004 i ... '"

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NUMBER

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01/26/82

DATE

PART NUMBER

I..oJECTNO

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PAGE

2262100-0001

1

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'AITNUMBER
ILM0931500-0005

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0931515-0001

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00001.000

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0003

<.l0001.000

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0931516-0001

CABLE ASSY,50 PIN. 20FT

0004

00001.000

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0931510-0001

CABLE ADAPTER,10 MEGA BYTE DISK

0005

kEF

EA

0936534-9901

PACKING PROC,10 MS DISK DR,RACK MOUNTED

0006

REF

EA

0937503-9901

SPECIFlCATInN,DISK CONT,lO MEGA BYTE

0007

REF

EA

0937509-9901

TEST PROC,SYS,10 MEGA BYTE DISK

EA

0931513-0009

DISK DRiVE,50HZ,220V,RACK MourH

0008

P'Jo.RTNUMBER

LM0931500-0D04

DESCRIPTION
CDC DISK CONTROLLER

0001A

0002

OATf

KIT,lO MB RACK DISK,SEC OlSK,lZOV,60HZ

00001.000

OOOSA

834484-69

REPLACE POWER PLUG WITH

OOOSI:I

ITEM 29 PER FIGURE 1 OF

OOOSC

SHEET 1.

OOOSO

SET VOLTAGE PER 940040.

0009

0:)001.000

0010

00001.000

EA

0011

REF

EA

0012

RfF-

EA

0937507-0001

DISC CARTRIDGE,TYPE 5440-HIGH DENSITY

0940042-0001

LABEL,lO MEGA RYTE DISK DRIVE

0940040-9901

PROCEDURE,V{1LTAGE AND FREQ. ((\I\IVERSION

I '"

OIA,FAMIlY TREE,10 MEGA BYTE LlISK

162H'01

DATE

I "'~GN

"""I

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DATE

I

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KIT,lO "IB !tACK DISK,HASTER,230V,50IH

uT..aJECT NO

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G-13

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!LM0931'j00-000S i AB

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Digital Systems Division

~------~

946262-9701

~ TEXAS INSTRUMENTS
~

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UNIT

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0013

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00001.000

0014

00009.000

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DATE

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00001.000

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0946261-9101

00001.000

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2262107-0001

KIT,RETRACTOR BRACKET ,OSlO

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00001.000

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0945180-0001

lA8El,DSI0 SWITCH SETTING

0026

00001.000

EA

2262106-0001

lA8El,DSI0 lOGICAL UNIT,PRIMARY

0028

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1.0

SCOPE
This procedure is written to allow Texas Instruments
the option of changing the operating requirements of
voltage and frequency on Control Data Corporation 10
Mega Byte Disc Drive.

2.0

REFERENCE DOCUMENTS
For further information refer to Control Data Incorporated

Reference Manual 77614950 (formerly 77834675) that has been assigned
TI PN 937517.

3.0

VOLTAGE ADJUSTMENT

3.1

Turn off DC power to the disk drive and wait until
the READY indicator light goes off.

3.2

Turn off AC power (breaker at the rear of the unit)
and remove the power cord from the wall outlet.

WARNING:

Line voltages are present in the area of
of the drive motor even when the main circuit breaker is off.

Failure to disconnect

or turn off main power source may result
in injury to service personnel.

TI-425~·£

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3.3

Remove the rear cover from the unit (remove holding
screws) .

3.4

Remove A1P12 plug from the drive.

This plug is 10-

cated at the lower rear portion, next to power cord,
of the drive.

3.5

There will be two (2) plug locations to be changed
when altering voltage requirement.

Table I gives a

list of the voltage ranges along with the plug jumper position required for each of these voltage settings.

For each voltage there are two jumper plugs,

one end of each plug goes to a fixed pin location.
These ends should never be removed or changed on
the plug (pins 14 and 15).

The location of each

pin in connector P12 is shown in Figure 1 and should
be studied closely to insure the proper numbering
sequence is understood before proceeding to change
the jumpers.

3.6

Example
If it is desired to change a unit from a 110 volt unit
to a 230 volt unit the jumpers shall be changed as
listed below:
Jumper #1 - No Change Required
Jumper #2 - Remove wire and pin at location Number 7
on Plug P12 and move it to location Number
9 on Plug 12

T1-4259-E

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110
120
130

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9

FRONT VIEW (PIN SIDE)
FIGURE 1
JUMPER PIN ADJUSTMENT

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3.7

Once the desired changes have been made the plug P12
should be inserted back into its connector at the rear
of the drive.

3.8

If the voltage changes such that a new type of cord
connector is required, the cord should be changed or
the old connector should be taken off and the appropriate connector installed. If the cord or connector is changed,

the Hipot Test must be executed.
3.9

See Appendix A for Hipot instructions.

Document the voltage change in the space provid.ed' on the power supply
identification plate at the rear of the unit with a black permanent ink:

3.10

If only the voltage operating range is to be changed
and not the line frequency, the rear cover can be replaced and fastened down with the retaining screws.
The drive can now be connected to the appropriate
new power source and brought up to speed.

If the fre-

quency of operation is not to be changed, Paragraph 4.0
can be skipped.

4.0

FREQUENCY ADJUSTMENT
NOTE:
Frequency conversions to 60HZ for del ivery within UL-CSA jurisdi,ctions
are forbidden. Frequency conversions to 50HZ require that the FCC
"Non-Compliant" label be removed.

~
{/

TI-4ZI18-E

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4.1

Depress START/STOP switch to remove DC voltage from
the unit.

Wait until the spindle stops rotating

(START/STOP lamp extinguished) and then turn the AC
power off by tripping the two breakers at the left
rear area of the drive.

Disconnect the unit from

the main power source by unplugging the cord from
the power outlet.
CAUTION:

Line voltages are present in the area of
of the drive motor, even when the main
circuit breaker is off.

Failure to dis-

connect or turn off main power source may
result in injury to service personnel.

4.2

Hardware Removal

4.2.1

Remove the front panel by removing six screws.

4.2.2

Remove the control panel by disconnecting A5P1 connector from switchboard assembly by removing four screws.

4.2.3

Remove the bottom cover by removing three screws.

4.2.4

Disconnect the IDLER clutch spring by removing the
6-32 screw from the IDLER arm.

4.2.5

Remove ,the drive belt from the motor and spindle
pulleys.

TI-4259.E

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4.2.6

Remove the drive pulley from the motor by loosening
the pulley clamp screw.

4.3

Hardware Installation
The parts required for modification (50 or 60 HZ) are
listed in TI Drawing 937506.

4.3.1

Fit the new pulley onto the motor shaft so the collar
is away from

4.3.2

~he

motor.

Install the new collar and screw over the four pronged
hub of the new pulley just installed.

Tighten the

screw in the collar to 5 + 0.5 inch-pounds,

4.3.3

Install the new drive belt such that the smooth side
of the belt is against the drive motor and spindle
pulley faces.

4.3.4

Rotate the IDLER clutch spring (in free direction) to
align with the tapped hole in the IDLER ARM and replace the screw that was removed in Paragraph 4.2.4.

4.3.5

Install the bottom cover by installing the 3 screws
removed in Paragraph 4.2.3.

4.3.6

Install the control panel and connect plug A5P1.

~

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4.3.7

_ _ _ __

The AC power cord should be removed and replaced with
the appropriate cord and connector for the new frequency and voltage.

4.4

The new operating frequency should be recorded in the

sp~ce pr~vided

on the power supply identificati.on plate at the rear of the unit with
a black permanent ink.

4.5

The rear cover can now be put back on and anchored with
the screws removed earlier.

The drive can now be plugged

in to the appropriate A.C. outlet and normal operation
started.

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APPENDIX A
HIPOT PROCEDURE
1.0

SCOPE

1.1

The tests called for in this appendix are to ensure that the ground terminal
on the device's power cord is attached to and making good electrical contact
with the devicels frame. The test also insures that there is sufficient
electrical isolation between the frame and the live electrical parts of the
device.

2.0

TEST EQUIPMENT

2.1

Slaughter Co. Model Al16/213 Dielectric Breakdown Tester.

WARNING
HIGH VOLTAGE IS PRESENT
APPROPRIATED PRECAUTIONS
SHOULD BE OBSERVED
3.0

TEST SET-UP

3.1

Verify that the power cord is connected to the plug as shown in Figure 2,
3, or 4, depending on plug used.

3.2

The switches on the Hipot tester should be set in the following positions:
CONTROL
POSITION
Grd. Lead Bypass
Run Test Disable
AC/DC
124/240V.
On/Off
Test voltage

Down
Up
DC
120V. (All Devices)
On
Adjust for a reading of 1.7 kilovolts on
meter
Up (On)

Continuity Disable
(If option avail.)

TI-4Z!5I1·E

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3.3

The front panel light indicators should be as follows;
The Pilot and 120V lights should be on.
The Grd. Lead Bypass, HV. on and 240V. lights should be off.

3.4

Ensure that the devicels main power switch is turned on.

3.5

Attach the ground returen lead (red lead with alligator clip) to the exposed
portion of the units frame, Care should be taken to prevent scratching the
metal with the clip.

3.6

Insert the devicels power plug into the appropriate socket extension on the
front panel of the test set. If the plug does not fit in the extension socket,
select the appropriate adapter plug and then insert the power cord in the
corresponding socket.

4.0

DETAILED TESTS
ENSURE THAT NO ONE IS IN CONTACT
WITH THE CHASSIS UNDER TEST BEFORE
PROCEDING WITH THIS TEST

4.1

Momentarily depress the test switch on the front panel of the test set until
the fault buzzer sounds or the test complete light comes on.

4.2

Observe the test set lights on the front of the test set and take the
appropriate action as indicated below if they come on:
TEST SET LIGHT
Breakdown
Grd. Open
Li nelLi ne Short

Unit has failed dielectric test.
Unit has failed ground continuity test.
Primary lines shorted together. (Should
not occur if Continuity Disable is on.)
Primary lines execeed input resistance limits.
(Should not occur if Continuity Disable is on.)
Test is complete and voltage is no longer being
applied.

Continuity Fail
Test Complete
4.3

TI-4259·E

UnRlug the device under testis power cord from the test set and then
disconnect the test setls ground clip.

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TI-42!19·E

R£CONFIG

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Digital Systems Division

~------~

946262-9701

ALPHABETICAL INDEX

Digital Systems Division

~---~--~

946262-9701

ALPHABETICAL INDEX
INTRODUCTION
HOW TO USE THE INDEX
The index, table of contents, list of illustrations, and list of tables are used in conjunction to obtain
the location of the desired subject. Once the subject or topic has been located in the index, use the
appropriate paragraph number,. figure number, or table number to obtain the corresponding page
number from the table of contents, list of illustrations, or list of tables. The table of contents does
not contain four-level paragraph entries. Therefore, for four-level paragraph numbers such as
2.3.1.2, use the three-level number and the corresponding page number. In this case, the three-level
number is 2.3.1.

INDEX ENTRIES
The following index lists key words and concepts from the subject material of the manual together
with the area(s) in the manual that supply major coverage of the listed concept. The numbers along
the right side of the listing reference the following manual areas:
•

Sections - References to Sections of the manual appear as "Section x" with the symbol
x representing any numeric quantity.

•

Appendixes - References to Appendixes of the manual appear as "Appendix y" with the
symbol y representing any capital letter.

•

Paragraphs - References to paragraphs of the manual appear as a series of alphanumeric
or numeric characters punctuated with decimal points. Only the first character of the
string may be a letter; all subsequent characters are numbers. The first character refers
to the section or appendix of the manual in which the paragraph is found.

•

Tables - References to tables in the manual are represented by the capital letter T followed immediately by another alphanumeric character (representing the section or
appendix of the manual containing the table). The second character is followed by a
dash (-) and a number:
Tx-yy

•

Figures - References to figures in the manual are represented by the capital letter F
followed immediately by another alphanumeric character (representing the section or
appendix of the manual containing the figure). The second character is followed by a
dash (-) and a number:
Fx-yy

•

Other entries in the Index - References to other entries in the index are preceded by
the word "See"followed by the referenced entry.

The index is divided into sections for the letters of the alphabet. Acronyms and mnemonics (words
made up entirely of capital letters) are listed first within each section. Words that begin with a
capital letter follow the acronyms and mnemonics.

Index-l

Digital Systems Division

~------~

946262-9701

AC, Abnormal Completion . . . . . . . . . 1.7.8.6
Abnormal Completion AC . . . . . . . . . 1.7.8.6
Access Logic, TILINE . . . . . . . . . . . . 2.6.6.2
Access, TILINE . . . . . . . . . . . . . . . . 2.6.6.1
Address Compare, TILINE Slave ...... F2-22
Address Control Logic. . . . . . . . . . . .. 2.9.3
Address Control, Microprogram ... 2.9, F2-32
Address Control Simplified,
Microprogram . . . . . . . . . . . . . . . . . F2-30
Address Generator. . . . . . . . . . . . . . .. 2.9.1
Control . . . . . . . . . . . . . T2-9, T2-10, T2-11
I/O Reset and Power Interrupt
Traps . . . . . . . . . . . . . . . . . . . . 2.9.3.1
Microcode Interrupt Traps . . . . . . . . 2.9.3.1
Microprogram . . . . . . . . . . . . . . . . . F2-31
TILINE Slave Traps . . . . . . . . . . . . 2.9.3.1
Address:
Sector . . . . . . . . . . . . . . . . . . . . . 1.7.3.2
Switch Settings, TILINE . . . . . . . . . . . T2-3
Addresses, Control Word TILINE
Slave ................................ 1.6.1
Addressing, Disk, Test ................. 3.7.2.3
Addressing, Memory, Test .............. 3.7.2.4
Adjustment:
Microprocessor Clock ................ 2.5.2.4
TILINE Timing ........................ 3.4
Address, Cylinder ....................... 1.7.4
Array, CPE ........................... F2-25
Array and Processor Bus PBUS, CPE ..... F2-27
Assembly:
Drawings, Logic and ............ Appendix G
Photograph, Controller ........... FI-2, F-I-3
Attention Interrupt Mask . . . . . . . . .. 1.7.1.7
BC, Branch Control. . . . . . . . . . . . . . 2.4.1.8
Bit Testing:
CPE Input Bus . . . . . . . . . . . . . . . . F2-46
Disk Status Word . . . . . . . . . . . . . . F2-47
Block Diagram:
CPE . . . . . . . . . . . . . . . . . . . . 2.7.1, F2-23
Controller . . . . . . . . . . . . . . . . . . . . . F2-2
Block Diagram Description, Controller .... 2.2
Block Diagram:
Disk:
Interface . . . . . . . . . . . . . . . . . . . . F2-3
System . . . . . . . . . . . . . . . . . . . . . FI-I
Branch Control:
BC . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1.8
ROM . . . . . . . . . . . . . . . . . . . . . . . T2-12
Branch Decoder ROM . . . . . . . . . . . .. 2.9.2
Branch or Return:
Conditional . . . . . . . . . . . . . . . . . .. 2.8.1
Test Bit Inputs for Conditional ...... T2-8
Buffer, First In, First Out (FIFO) ....... 2.12.1.4
Bus:
CPE Input .......................... F2-26
PBUS, CPE Array and Processor ....... F2-27
CI, CPE Carry In . . . . . . . . . . . . . . . 2.4.1.5
CPE:
Array . . . . . . . . . . . . . . . . . . . 2.7.5, F2-25
Array and Processor Bus
PBUS . . . . . . . . . . . . . . . . . 2.7.6, F2-27
Block Diagram ... . . . . . . . . . 2.7.1, F2-23
Bus, Disk Status Inputs to . . . . . . . . F2-45
Carry In CI . . . . . . . . . . . . . . . . . 2.4.1.5

Index-2

Carry and Shift . . . . . . . . . . . . . 2.8, F2-29
Conditional Clock . . . . . . . . . . . . . 2.4.1.1
F Group Formats . . . . . . . . . . . . . . . . T2-5
Function Code Format . . . . . . . . . . . 2.7.3
Function Control . . . . . . . . . . . . . . 2.4.1.2
Input Bus . . . . . . . . . . . . . . . . . . . . F2-26
Input Bus Bit Testing . . . . . . . . . . . . F2-46
Input/ Output Signals . . . . . . . . . . . . . T2-4
Instruction Set . . . . . . . . . . . . . . . .. 2.7.2
Operating Sequence . . . . . . . . . . . . . F2-24
Operation Summary . . . . . . . . . . . . . . T2-7
Operations . . . . . . . . . . . . . . . . . . . 2.7.4
R Group Formats . . . . . . . . . . . . . . . T2-6
3002 . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7
CRC:
Cyclic Redundancy Check . . . . . . . . 2.12.1.5
Generation, Cyclic Redundancy
Check . . . . . . . . . . . . . . . . . . . . . F2-52
Generator and Checker . . . . . . . . . . . F2-53
CT, Command Timer Timeout ...... 1.7.8.6
Cabinet Mount:
Disk Drive ............................ FI-5
Disk Drive Cutaway View .............. FI-12
Cable Adapter Photograph ............... FI-9
Cabling:
System .............................. 1.5.1
For Single Drive, System ............... FI-I0
For Two Rackmount Drives, System ..... Fl-ll
Carry:
Generator . . . . . . . . . . . . . . . . . . .. 2.8.2
In CI, CPE . . . . . . . . . . . . . . . . . . 2.4.1.5
Left Byte . . . . . . . . . . . . . . . . . . . . 2.8.5
Right Byte . . . . . . . . . . . . . . . . . . . 2.8.4
Word . . . . . . . . . . . . . . . . . . . . . . . 2.8.6
Carry and Shift, CPE . . . . . . . . . . 2.8, F2-29
Carry and Shift Control. . . . . . . . . . .. 2.8.3
Central Processing Elements 3002,
Microprocessor . . . . . . . . . . . . . . . . . . 2.7
Character, Synchronization . . . . . . . . . . . . 1.9
Checkout:
Microprocessor Clock . . . . . . . . . . . 3.3.1.1
Preliminary . . . . . . . . . . . . . . . . . .. 3.3.1
Clock:
Adjustment, Microprocessor . . . . . . . 2.5.2.4
Buffer, Read . . . . . . . . . . . . . . . . . . F2-54
CPE Conditional ... . . . . . . . . . . . 2.4.1.1
Delay for TILINE Cycle . . . . . . . . . . F2-14
Distribution, Disk . . . . . . . . . . . . . . F2-54
Encoding:
Timing Diagram, Write Data and .. F2-58
Write Data and . . . . . . . . . . . . . . F2-57
Gating, Microprocessor . . . . . . . . . . 2.5.2.2
Microprocessor . . . . . . . . . . . . F2-12, F3-5
TILINE Triggering Microprocessor .. 2.5.2.1
Timing Diagram, Microprocessor .... F2-13
Timing, Microprocessor. . . . . . . . . .. 2.5.1
Write Oscillator . . . . . . . . . . . . . . . . . F3-6
Codes, Disk Command .. . . . . . . . . . . . T 1-4
Command:
Codes, Disk . . . . . . . . . . . . . . . . . . . T 1-4
Completion With Interrupts . . . . . . .. 1.6.4
Completion Without Interrupts . . . . .. 1.6.3
Example:
Read Data . . . . . . . . . . . . . . . . . . . TI-7
Read Unformatted . . . . . . . . . . . . . . T 1-8
Seek . . . . . . . . . . . . . . . . . . . . . . . TI-9

Digital Systems Division

~~-----------------~

946262-9701

Store Registers . . . . . . . . . . . . . . . . Tl-5
Wriie Formal . . . . . . . . . . . . . . . . . TI-6
Initiation. . . . . . . . . . . . . . . . . . . .. 1.6.2
Read Data . . . . . . . . . . . . . . . . . . . 1.8.3
Read Unformatted . . . . . . . . . . . . . . 1.8.5
Restore. . . . . . . . . . . . . . . . . . . . .. 1.8.8
Seek . . . . . . . . . . . . . . . . . . . . . . . . 1.8.7
Store Registers. . . . . . . . . . . . . . . .. 1.8.1
Timer . . . . . . . . . . . . . . . . . . . 2.11, F2-42
Timeout CT . . . . . . . . . . . . . . .. 1.7.8.6
Words, Data Flow Loading . . . . . . . . 2.3.1
Data Flow for Loading . . . . . . . . . . F2-4
Write Data . . . . . . . . . . . . . . . . . .. 1.8.4
Write Format . . . . . . . . . . . . . . . . . 1.8.2
Write Unformatted . . . . . . . . . . . . .. 1.8.6
Commands, Controller . . . . . . . . . . . . . . . 1.8
Complete . . . . . . . . . . . . . . . . . . . . . 1.7.8.2
Components, System . . . . . . . . . . . . . . . T3-1
Conditional:
. Branch or Return . . . . . . . . . . . . . . . 2.8.1
Test Bit Inputs for . . . . . . . . . . . . . T2-8
Configuration, System . . . . . . . . . . . . . . . 1.5
Control, Address
Generator . . . . . . . . . . . T2-9, T2-1O, T2-11
Control Word:
TILINE Slave Addresses ............... 1.6.1
WO ................................. Fl-14
WI ................................ . Fl-IS
W2 ................................. FI-16
W3 ................................. FI-17
W4 ................................. FI-1S
WS ................................. FI-19
W6 ................................. FI-20
W7 ................................. FI-21
Control and Select, Disk ............... 2.12.1.1
Control and Status Word Formats ........ FI-13
Control and Status Word Formats WO
through W7 ............................ 1.7
Controller:
Assembly Photograph (PWB) ........... FI-2
Assembly Photograph (Fine Line) ........ FI-3
Block Diagram ... . . . . . . . . . . . . . . F2-2
Block Diagram Description . . . . . . . . . . 2.2
Commands . . . . . . . . . . . . . . . . . . . . . 1.8
Interface Signals . . . . . . . . . . . . . . 2.1, F2-1
Introduction . . . . . . . . . . . . . . . . . . . . 1.3
LED Fault Indicators . . . . . . . . . . . . . F3-7
Microinstruction Format . . . . . . . . . . . . 2.4
Physical Description . . . . . . . . . . . .. 1.3.1
Programming .......................... 1.6
Quick Test ......................... 3.7.2.1
Self-Test .......................... 2.12.1.8
Status ............................... 1.7.8
Controller and Disk, Quick Test ....... 3.7.2.2
Controls and Indicators,
Disk Drive . . . . . . . . . . . . . . . FI-5, TI-I
Cyclic Redundancy Check CRC . . . . . . 2.12.1.5
Generation . . . . . . . . . . . . . . . . . . . F2-52
Cylinder . . . . . . . . . . . . . . . . . . . . . . . . . 1.9
Cylinder Address . . . . . . . . . . . . . . . .. 1.7.4
Cylinder Address Select, Disk Control
Decoder and . . . . . . . . . . . . . . . . . . F2-44
Data Error . . . . . . . . . . . . . . . . . . . . 1.7.8.6
Data Flow:
Disk Read . . . . . . . . . . . . . . . . . . . 2.3.3

Disk Write . . . . . . . . . . . . . . . . . . . 2.3.2
Loading Command Words . . . . . . . . . 2.3.1
Self-Test ............................ F2-60
Verify Record Header ................. 2.3.5
Write Format. ........................ 2.3.4
Data Flow for:
Loading Command Words . . . . . . . . . . F2-4
Read Operation . . . . . . . . . . . . . . . . . F2-6
Verify Record Header Operation . . . . . . F2-8
Write Format Operation . . . . . . . . . . . F2-7
Write Operation . . . . . . . . . . . . . . . . . F2-5
Decoder:
Special Function 0 . . . . . . . . . . . . . . T2-13
Special Function I . . . . . . . . . . . . . . T2-14
Special Function 2 . . . . . . . . . . . . . . T2-15
Decoder and Buffer, Read Data . . . . . . F2-54
Decoder and Cylinder Address Select,
Disk Control . . . . . . . . . . . . . . . . . . F2-44
Decoding:
Microinstruction ................ 2-10, F2-40
Special Field ...................... 2.10.2
Read Data ......................... 2.12.1.6
Timing Diagram, Microinstruction
Special Function ................... F2-41
Definitions, Signal (PWB) .......... Appendix B
Definitions, Signal (Fine Line) ...... Appendix C
.Delay Timer ........................... F2-11
Diagnostic Test:
Error Messages ....................... 3.7.4
Fault Isolation with ..................... 3.7
Initialization ......................... 3.7.3
Introduction ......................... 3.7.1
Parts of ............................. 3.7.2
Utility Verbs .......................... T3-S
Verbs ................................ T3-4
Diagram, FIFO Block ................... F2-49
Disk:
Addressing Test ..................... 3.7.2.3
Clock Distribution .................... F2-S4
Command Codes ...................... TI-4
Control Decoder and Cylinder Address
Select ............................. F2-44
Control and Select .................. 2.12.1.1
Drive:
Cabinet Mount. ....................... Fl-S
Controls and Indicators ........... FI-6, Tl-l
Cutaway View, Cabinet Mount ......... FI-12
Interface Block Diagram .......... F2-3, F2-43
Interface Logic .................. 2.2.3,2.12
Interface Signals ..................... T2-16
Interface Start and R W Control ......... F2-48
Interface Start and Read Write
Control ......................... 2.12.1.3
Introduction ........................... 1.4
Photograph .......................... FI-7
Rack Mount .......................... FI-4
Read, Data Flow . . . . . . . . . . . . . .. 2.3.3
Specifications . . . . . . . . . . . . . . . . . . . TI-2
Status Inputs to CPE Bus . . . . . . . . . F2-45
Status Inputs to IBUS and PBUS ... 2.12.1.2
Status Word Bit Testing . . . . . . . . . . F2-47
System:
Block Diagram . . . . . . . . . . . . . . . . F I-I
Part Numbers . . . . . . . . . . . . . . . . . TI-3
Write, Data Flow . . . . . . . . . . . . . . . 2.3.2

Index-3

Digital Systems Division

~------~

946262-9701

Documentation, Special Test
Equipment and . . . . . . . . . . . . . . . . . T3-2
Documents, Related ................... Preface
Drawings, Logic and Assembly ...... Appendix G
ENSLV, TILINE Slave Enable ...... 2.4.1.7
Enable, Interrupt. . . . . . . . . . . . . . .. 1.7.8.4
Encoding, Write Data and Clock ..... 2.12.1.7
Error ................................ 1.7.8.3
Codes, Self-Test Status ................. T3-3
Message:
Analysis .......................... . 3.7.S
Status ..................... 3.7 .S.3, F3-11
TILINE Time-out ................... 3.7.1
Typical Status ...................... F3-11
Unexpected Interrupt Level ... 3.7 .S.2, F3-10
Error Messages, Diagnostic Test ........... 3.7.4
Example:
READ DATA Command . . . . . . . . . . TI-7
READ UNFORMATTED Command .. TI-8
SEEK Command . . . . . . . . . . . . . . . . TI-9
STORE REGISTERS Command ..... TI-S
WRITE FORMAT Command ....... TI-6
F Group Formats, CPE .................. T2-S
FIFO:
Block Diagram ....................... F2-49
Buffer, First In, First Out ............ 2.12.1.4
Buffer Logic ......................... F2-S1
Input Timing Diagram, Sync
Character and . . . . . . . . ........ F2-S6
Timing Diagram. . . . . . . ......... F2-50
Fault:
Analysis . . . . . . . . . . . . . . . . . . . . . . . 3.S
Indicators:
Controller LED .... . . . . . . . . . . . F3-7
LED . . . . . . . . . . . . . . . . . . . . . . 3.6.3
Isolation with:
Diagnostic Test ....................... 3.7
LED Indicators ..................... 3.6.4
Self-Test .......................... . 3.6.S
First In, First Out (FIFO) Buffer ........ 2.12.1.4
Flowchart:
I/O Reset and Power Reset Trap ........ F2-36
Microprogram Principal ............... F2-1 0
TILINE Access ...................... F2-19
Flowcharts, Microprogram ......... Appendix D
Format:
CPE Function Code ................... 2.7.3
Controller Microinstruction .............. 2.4
Microinstruction ...................... F2-9
Microprogram Instruction .............. F2-9
Record ................................ 1.9
Header Data ....................... FI-23
Sector .............................. FI-26
Sector and Track ..................... FI-2S
Store Registers Data .................. FI-22
Formats:
CPE:
F Group ........................... T2-S
R Group ........................... T2-6
Control and Status Word .............. FI-13
WO through W7, Control and
Status Word . . . . . . . . . . . . . . . . . . . 1.7
Function Control, CPE . . . . . . . . . . . 2.4.1.2

Index-4

Gap I through Gap 3 . . . . . . . . . . . . . . . 1.9
Gating, Microprocessor Clock ....... 2.5.2.2
Head Layout .......................... FI-24
Header Data Format, Record ............. FI-23
Header, Record Identification .............. 1.9
Hot Mockup Test System ................. F3-1
110 Board Photograph, Winchester ........ FI-8
110 Reset and Power Interrupt Traps,
Address Generator .................. 2.9.3.1
I/O Reset Trap Timing Diagram,
TILINE . . . . . . . . . . . . . . . . . . . . . F2-37
I/O Reset and Power Reset Trap
Flowchart . . . . . . . . . . . . . . . . . . . . F2-36
IBUS and PBUS, Disk Status
Inputs to . . . . . . . . . . . . ....... 2.12.1.2
10 Word Error IE . . . . . . . . . . . . . . 1.7.8.6
IE, 10 Word Error . . . . . . . . . . . . . . 1.7.8.6
1M, Immediate Operand . . . . . . . . . . . 2.4.1.11
Identification Header, Record .............. 1.9
Idle ................................. 1.7.8.1
Immediate Operand .................... 2.10.2
1M ............................... 2.4.1.11
Indicators:
Controller LED Fault .................. F3-7
Disk Drive Controls and ........... FI-6, TI-I
Fault Isolation with LED ............... 3.6.4
LED Fault ........................... 3.6.3
Initialization, Diagnostic Test ............. 3.7.3
Input/Output:
Pin Connections ................ Appendix F
Signals, CPE ......................... T2-4
Installation Data, Jumper Switch
Settings and ........ : ........... Appendix A
Instruction Format, Microprogram ......... F2-9
Instruction Set, CPE .................... 2.7.2
Integrity, Media, Test ................. . 3.7.2.S
Interactive Write-Protect Test ........... 3.7.2.6
Interface:
Block Diagram, Disk ........ F2-3, F2-43
Logic, Disk . . . . . . . . . . . . . . . . 2.2.3, 2.12
Signals:
Controller . . . . . . . . . . ...... 2.1, F2-1
Disk Drive . . . . . . . . . . . . . . . . . . T2-16
TILINE . . . . . . . . . . . . 2.6.3, F2-15. T2-2
Start and R/W Control, Disk ........... F2-48
Start and Read/Write Control, Disk ... 2.12.1.3
TILINE ............................. 2.2.1
Interrupt:
Enable . . . . . . . . . . . . . . . . . . . . . 1.7.8.4
Mask, Attention . . . . . . . . . . . . . .. 1.7.1.7
Traps:
Address Generator I/O Reset and
Power . . . . . . . . . . . . . . . . . . 2.9.3.1
Address Generator Microcode .... 2.9.3.1
Trap Timing Diagram . . . . . . . . . . . . F2-35
Interrupts:
Command Completion With. . . . . . .. 1.6.4
Command Completion Without ..... 1.6.3
Introduction:
Controller . . . . . . . . . . . . . . . . . . . . .. 1.3
Diagnostic Test . . . . . . . . . . . . . . . . 3.7.1
Disk Drive . . . . . . . . . . . . . . . . . . . .. 1.4
Maintenance . . . . . . . . . . . . . . . . . . . . 3.1

Digital Systems Division

~------~

946262·9701

TILINE

1 ..,
•••••••••••••••••••••••

l.~

Jumper Switch Settings and
Installation Data . . . . . . . . . . Appendix A
Jumpers, Unit Selection . . . . . . . . . . . . T2-17
KBUS Control KC . . . . . . . . . . . . . . 2.4.1.4
KC, KBUS Control . . . . . . . . . . . . . . 2.4.1.4
LED:
Fault:
Indicators, Controller .......... 3.6.3, F3-7
Indicators, Fault Isolation with .......... 3.6.4
Left Byte:
Carry ............................... 2.8.5
Shift .............................. 2.8.7.2
Listing, Microprogram ............. Appendix E
Loading:
Command Words, Data Flow ........... 2.3.1
Command Words, Data Flow for ........ F2-4
Lockout ............................. 1.7.8.5
Logic and Assembly Drawings ...... Appendix G
Logical Unit Selection ................... T2-17
ME, Memory Error . . . . . . . . . . . . . . ·1.7.8.6
Maintenance:
Introduction . . . . . . . . . . . . . . . . . . . . 3.1
Philosophy . . . . . . . . . . . . . . . . . . . . . 3.2
Mask, Attention Interrupt .............. 1. 7.1. 7
Master Operation, TILINE ............... 2.6.6
Master ISlave, TILINE, . , ... , ....... , .... 2.6.1
Media Integrity Test ................... 3.7.2.5
Memory Addressing Test ............... 3.7.2.4
Memory Error ME .................... 1.7.8.6
Message:
Typical Status Error .................. F3-11
Unexpected Interrupt Level Error ....... F3-10
Microcode Interrupt Traps,
Address Generator . . . . . . . . . . . . . 2.9.3.1
Microcontroller . . . . . . . . . . . . . . . . .. 2.2.2
Microinstruction:
Access Cycle Timing Diagram ...... F2-33
Decoding . . . . . . . . . . . . . . . . 2.10, F2-40
Format . . . . . . . . . . . . . . . . . . . .2.4, F2-9
Special Field Decoding . . . . . . . . . . . 2.10.2
Special Function Decoding Timing
Diagram .......................... F2-41
Microprocessor:
Central Processing Elements 3002 ......... 2.7
Clock . . . . . . . . . . . . . . . . . . . F2-12, F3-5
Adjustment . . . . . . . . . . . . . . . . . 2.5.2.4
Checkout . . . . . . . . . . . . . . . . . . 3.3.1.1
Gating . . . . . . . . . . . . . . . . . . . . 2.5.2.2
TILINE Triggering . . . . . . . . . . . 2.5.2.1
Timing . . . . . . . . . . . . . . . . . . . . 2.5.1
Timing Diagram . . . . . . . . . . . . . . F2-13
Microprogram:
Address Control .................. 2.9, F2-32
Address Control Simplified ............ F2-30
Address Generator .................... F2-31
Flowcharts ..................... Appendix D
Instruction Format .................... F2-9
Listing ........................ Appendix E
Organization ......................... 2.4.2

Index-5

Principle Flowchart . . . . . . . . . . . . . F2-! 0
Routine Mnemonics . . . . . . . . . . . . . . T2-i
Mnemonics, Microprogram Routine ..... T2-1
Mockup Test System, Hot . . . . . . . . . . . F3-1
NR, Not Read Bit. . . ... . . . . . . . . .. 1.7.1.2
NRA, Next ROM Address . . . . . . . . . 2.4.1.10
Next ROM Address NRA . . . . . . . . . 2.4.1.10
Not Ready Bit NR . . . . . . . . . . . . . . 1.7.1.2
OL, Offline Bit . . . . . . . . . . . . . . . . . 1.7.1.1
Offline Bit OL . . . . . . . . . . . . . . . . . 1.7.1.1
PBUS
CPE Array and Processor Bus .. 2.7.6, F2-27
Destination . . . . . . . . . . . . . . . . . . 2.4.1.9
Enable Timing . . . . . . . . . . . . . . . . 2.5.2.3
Source .. . . . . . . . . . . . . . . . . . . . 2.4.1.6
Part Numbers, Disk System . . . . . . . . . . TI-3
Photograph:
Cable Adapter ........................ FI-9
Controller Assembly .............. FI-2, Fl-3
Disk Drive ............................ FI-7
Winchester I/O Board .................. FI-8
Physical Description, Controller ........... 1.3.1
Pin Connections, Input/Output ..... Appendix F
Power Failure Warning Trap Timing
Diagram, TILINE .................... F2-38
Power Reset:
Trap:
Flowchart, 110 Reset and . . . . . . . . F2-36
Timing Diagram, TILINE . . . . . . . . F2-39
Preliminary Checkout. . . . . . . . . . . . .. 3.3.1
Priority, TILINE . . . . . . . . . . . . . . . . . F2-18
Processor Bus:
Enable . . . . . . . . . . . . . . . . . . . . . . F2-28
PBUS, CPE Array and . . . . . . . 2.7.6, F2-27
Programming, Controller ... . . . . . . . . . . 1.6
R Group Formats, CPE . . . . . . . . . . . . . T2-6
RE, Rate Error . . . . . . . . . . . . . . . . . 1.7.8.6
ROM:
Branch Control . . . . . . . . . . . . . . . . T2-12
Branch Decoder . . . . . . . . . . . . . . .. 2.9.2
Bus . . . . . . . . . . . . . . . . . . . . 2.10, F2-40
ROMOO through 39 . . . . . . . . . . . . . . . . 2.10
Rack Mount Disk Drive .................. FI-4
Rackmount Drives, System Cabling
for Two ............................. FI-II
Rate Error RE ........................ 1.7.8.6
Read:
Buffer Timing Diagram . . . . . . . . . . . F2-55
Clock Buffer . . . . . . . . . . . . . . . . . . F2-54
Cycle Timing Diagram, TILINE ..... F2-17
Data:
Command . . . . . . . . . . . . . . . . . . 1.8.3
Example . . . . . . . . . . . . . . . . . . . TI-7
Decoder and Buffer . . . . . . . . . . . . F2-54
Decoding . . . . . . . . . . . . . . . . . . 2.12.1.6
Operation, Data Flow for . . . . . . . . . . F2-6
Timing, TILINE. . . . . . . . . . . . . . . . . F3-8
Unformatted:
Command . . . . . . . . . . . . . . . . . . 1.8.5
Example . . . . . . . . . . . . . . . . . . . TI-8

Digital Systems Division

~_
946262·9701
Jd7~
_ _ _ _ __
Write Control, Disk Interface
Start and . . . . . . . . . . . . . . . . . . 2.12.1.3
Record:
Format . . . . . . . . . . . . . . . . . . . . . . . . 1.9
Header Data Format . . . . . . . . . . . . FI-22
Identification Header . . . . . . . . . . . . . . 1.9
Word Count .. . . . . . . . . . . . . . . .. 1.7.5
Register Contents after Power Reset ........ T3-6
Related Documents ................... Preface
Reset and Power Reset Trap Flowchart,
I/O ................................ F2-36
RESTORE Command ................... I.S.S
Return, Conditional Branch and ........... 2.S.1
Right Byte:
Carry . . . . . . . . . . . . . . . . . . . . . .. 2.S.4
Shift . . . . . . . . . . . . . . . . . . . . . . 2.S.7.3
Right Shift. . . . . . . . . . . . . . . . . . . .. 2.S.7
SE, Search Error ...................... 1.7.S.6
SI, Seek Incomplete Bit. ................ 1.7.1.5
Search Error SE ....................... 1.7.S.6
Sector ................................... 1.9
Address ............................ 1.7.3.2
Format ............................. FI-26
Sector and Track Format ................ FI-25
Sectors per Record ..................... 1.7.3.1
Seek:
Command . . . . . . . . . . . . . . . . . . . . I.S.7
Example . . . . . . . . . . . . . . . . . . . . TI-9
Incomplete Bit SI . . . . . . . . . . . . . . 1.7.1.5
Select, Disk Control and ... . . . . . . . 2.12.1.1
Selection:
Jumpers, Unit ....................... T2-17
Unit ................................ T2-17
Self-Test .......................... 3.6, F2-54
Controller ......................... 2.12.1.S
Data Flow . . . . . . . . . . . . . . . . . . . F2-60
Fault Isolation with . . . . . . . . . . . . . 3.6.5
Status Count:
FFOA . . . . . . . . . . . . . . . . . . . . 3.6.6.11
FFOB· . . . . . . . . . . . . . . . . . . . . 3.6.6.12
FFOC . . . . . . . . . . . . . . . . . . . . 3.6.6.13
FFOD . . . . . . . . . . . . . . . . . . . . 3.6.6.14
FFOE . . . . . . . . . . . . . . . . . . . . 3.6.6.15
FFOF . . . . . . . . . . . . . . . . . . . . 3.6.6.16
FFOO . . . . . . . . . . . . . . . . . . . . . 3.6.6.1
FFOI . . . . . . . . . . . . . . . . . . . . . 3.6.6.2
FF02 . . . . . . . . . . . . . . . . . . . . . 3.6.6.3
FF03 . . . . . . . . . . . . . . . . . . . . . 3.6.6.4
FF04 . . . . . . . . . . . . . . . . . . . .. 3.6.6.5
FF05 . . . . . . . . . . . . . . . . . . . . . 3.6.6.6
FF06 . . . . . . . . . . . . . . . . . . . . . 3.6.6.7
FF07 . . . . . . . . . . . . . . . . . . . . . 3.6.6.S
FFOS . . . . . . . . . . . . . . . . . . . . . 3.6.6.9
FF09 . . . . . . . . . . . . . . . . . . . . . 3.6.6.10
FFIO . . . . . . . . . . . . . . . . . . . . . 3.6.6.17
FFll . . . . . . . . . . . . . . . . . . . . . 3.6.6.IS
FF12 . . . . . . . . . . . . . . . . . . . . . 3.6.6.19
FF13 . . . . . . . . . . . . . . . . . . . . . 3.6.6.20
FFI4 . . . . . . . . . . . . . . . . . . . . . 3.6.6.21
FFI5 . . . . . . . . . . . . . . . . . . . . . 3.6.6.22
Status Error Codes . . . . . . . . . . . . . . . T3-3
Status Interpretation. . . . . . . . . . . .. 3.6.2
Sequence, CPE Operating . . . . . . . . . . . F2-24

Shift:
CPE Carry and ....................... F2-29
Control, Carry and .................... 2.S.3
Left Byte ........................... 2.S.7.2
Right ................................ 2.S.7
Right Byte .......................... 2.S.7.3
Word Right ........................ 2.S.7.1
Signal Definitions (PWB) ........... Appendix B
Signal Definitions (Fine Line) ....... Appendix C
Signals, TILINE Interface ................ T2-2
Slave:
Address Compare, TILINE ............ F2-22
Enable ENSL V, TILINE ............. 2.4.1.7
Operation, TILINE . . . . . . . . . . . . . . 2.6.7
Read, TILINE . . . . . . . . . . . . . . . . 2.6.7.1
Read When Busy, TILINE . . . . . . . 2.6.7.2
TILINE . . . . . . . . . . . . . . . . . . . . . F2-21
Master. . . . . . . . . . . . . . . . . . . .. 2.6.1
Write, TILINE. . . . . . . . . . . . . . . . 2.6.7.3
Special:
Field Decoding, Microinstruction ....... 2.10.2
Function Decoding Timing
Diagram, Microinstruction ........... F2-41
Function Fields .................... 2.1.1.14
Function Group ................ 2.4.1.13
Function 0 Decoder . . . . . . . . . . . . . T2- 13
Function 1 Decoder . . . . . . . . . . . . . T2-14
Function 2 Decoder . . . . . . . . . . . . . T2-15
Test Equipment and Documentation ... T3-2
Specifications, Disk Drive . . . . . . . . . . . . TI-2
State Display:
Logic . . . . . . . . . . . . . . . . . . . . . . . . F3-3
Panel . . . . . . . . . . . . . . . . . . . . . . . . F3-2
Test Connections . . . . . . . . . . . . . . . . F3-4
Status:
Controller ........................... 1.7.S
Count:
FFOA, Self-Test .................. 3.6.6.11
FFOB, Self-Test .................. 3.6.6.12
FFOC, Self-Test .................. 3.6.6.13
FFOD, Self-Test .................. 3.6.6.14
FFOE, Self-Test .................. 3.6.6.15
FFOF, Self-Test .................. 3.6.6.16
FFOO, Self-Test ................... 3.6.6.1
FFOl, Self-Test ................... 3.6.6.2
FF02, Self-Test ................... 3.6.6.3
FF03, Self-Test ................... 3.6.6.4
FF04, Self-Test ................... 3.6.6.5
FF05, Self-Test ................... 3.6.6.6
FF06, Self-Test ................... 3.6.6.7
FF07, Self-Test ................... 3.6.6.S
FFOS, Self-Test ................... 3.6.6.9
FF09, Self-Test .................. 3.6.6.10
FFI0, Self-Test .................. 3.6.6.17
FF11, Self-Test .................. 3.6.6.1S
FFI2, Self-Test .................. 3.6.6.19
FF13, Self-Test .................. 3.6.6.20
FFI4, Self-Test .................. 3.6.6.21
FFI5, Self-Test .................. 3.6.6.22
Error Codes, Self-Test ................... T3-3
Error Message .................. 3.7.5.3, F3-11
Inputs to CPE Bus, Disk ................. F2-45
Inputs to IBUS and PBUS, Disk ........ 2.12.1.2
Interpretation, Self-Test ................. 3.6.2

Digital Systems Division

~------~

946262-9701

Word:
Bit Testing, Disk . . . . . . . . . . . . . . F2-47
Formats WO through W7, Control and. 1.7
Store Registers:
Command ........................... 1.8.1
Example ........................... TI-5
Data Format ......................... FI-22
Summary, CPE Operation ................ T2-7
Switch Settings, TILINE Address .......... T2-3
Switch Settings and Installation
Data, Jumper .................. Appendix A
Sync Character and FIFO Input
Timing Diagram ...................... F2-5t!
Synchronization Character ................. 1.9
System:
Block Diagram, Disk ................... Fl-l
Cabling .............................. 1.5.1
Cabling for Single Drive ............... FI-I0
Cabling for Two Rackmount Drives ..... FI-II
Components . . . . . . . . . . . . . . . . . . .T3-1
Configuration . . . . . . . . . . . . . . . . . . . 1.5
Part Numbers, Disk . . . . . . . . . . . . . . TI-3
TIH, Transfer Inhibit. . . . . . . . . . . . .. 1.7.2
TILINE:
Access . . . . . . . . . . . . . . . . 2.6.6.1, F2-20
Flowchart . . . . . . . . . . . . . . . . . . F2-19
Logic . . . . . . . . . . . . . . . . . . . . 2.6.6.2
Address Switch Settings . . . . . . . . . . . T2-3
Control ........................... 2.4.1.12
Cycle, Clock Delay for ................ F2-14
I/O Reset Trap Timing Diagram ........ F2-37
Interface ............................. 2.2.1
Interface Signals ........... 2.6.3, F2-15, T2-2
Introduction . . . . . . . . . . . . . . . . . 1.2, 2.6
Master Operation . . . . . . . . . . . . . .. 2.6.6
Master / Slave . . . . . . . . . . . . . . . . .. 2.6.1
Power Failure Warning Trap
Timing Diagram . . . . . . . . . . . . . . F2-38
Power Reset Trap Timing Diagram ... F2-39
Priority . . . . . . . . . . . . . . . . . . . . . . F2-18
Read Cycle Timing Diagram . . . . . . . F2-17
Read Timing . . . . . . . . . . . . . . . . . . . F3-8
Slave . . . . . . . . . . . . . . . . . . . . . . . F2-21
Address Compare . . . . . . . . . . . . . F2-22
Addresses, Control Word . . . . . . .. 1.6.1
Slave Enable ENSL V . . . . . . . . . . . 2.4.1.7
Slave Operation . . . . . . . . . . . . . . . . 2.6.7
Slave Read . . . . . . . . . . . . . . . . . . 2.6.7.1
Slave Read When Busy . . . . . . . . . . 2.6.7.2
Slave Trap Timing Diagram . . . . . . . . F2-34
Slave Traps, Address Generator .... 2.9.3.1
Slave Write . . . . . . . . . . . . . . . . . . 2.6.7.3
Starting Address for Word Transfers.. 1.7.6
Time-out IT ........................ 1.7.8.6
Error Message .................... 3.7.5.1
Timing:
Adjustment .......................... 3.4
Read . . . . . . . . . . . . . . . . . . . . . . 2.6.5
Write . . . . . . . . . . . . . . . . . . . . . 2.6.4
Triggering Microprocessor Clock. . . . 2.5.2.1
W rite Cycle Timing Diagram . . . . . . . F2-16
Write Timing . . . . . . . . . . . . . . . . . . . F3-9
TPCS . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2
TT, TILINE Timeout . . . . . . . . . . . . . 1.7.8.6

Test:
Bii ................................. . 2.8.i
Bit Inputs for Conditional Branch
or Return .......................... T2-8
Connections, State Display .............. F3-4
Diagnostic, Parts of ................... 3.7.2
Disk Addressing ..................... 3.7.2.3
Equipment and Documentation,
Special ............................. T3-2
Interactive Write-Protect ............. 3.7.2.6
MediaIntegrity ..................... 3.7.2.5
Memory Addressing ................. 3.7.2.4
Quick, Controiler ................... 3.7.2.1
Quick, Controller and Disk ........... 3.7.2.2
Self ................................ F2-54
System, Hot Mockup .................. F3-1
Utility Verbs, Diagnostic ............... T3-5
Verbs, Diagnostic ..................... T3-4
Timer:
Command . . . . . . . . . . . . . . . . 2.11, F2-4'"
Delay . . . . . . . . . . . . . . . . . . . . . . . F2-ll
Timing:
Adjustment, TILINE .................... 3.4
Diagram:
FIFO ............................. F2-50
Interrupt Trap ..................... F2-35
Microinstruction Special Function
Decoding ........................ F2-41
Microinstruction Access Cycle ........ F2-33
Microprocessor Clock ... . . . . . . . F2-13
Read Buffer . . . . . . . . . . . . . . . . . F2-55
Sync Character and FIFO Input ... F2-56
TILINE:
I/O Reset Trap . . . . . . . . . . . . . F2-37
Power Failure Warning Trap .... F2-38
Power Reset Trap . . . . . . . . . . . F2-39
Read Cycle . . . . . . . . . . . . . . . . F2-17
Slave Trap . . . . . . . . . . . . . . . . F2-34
Write Cycle . . . . . . . . . . . . . . . . F2-16
Write Data . . . . . . . . . . . . . . . . . . F2-59
Write Data and Clock Encoding ... F2-58
Microprocessor Clock . . . . . . . . . . .. 2.5.1
PBUS Enable . . . . . . . . . . . . . . . . 2.5.2.3
Read, TILINE . . . . . . . . . . . . ...... 2.6.5
TILINE:
Read . . . . . . . . . . . . . . . . . . . . . . . F3-8
Write . . . . . . . . . . . . . . . . . . . . . . F3-9
Write, TILINE. . . . . . . . . . . . . . . .. 2.6.4
Track ................................... 1.9
Format, Sector and ................... FI-25
Transfer Inhibit TIH .................... 1. 7.2
Trap:
Flowchart, 110 Reset and
Power Reset . . . . . . . . . . . . . . . . . F2-36
Timing Diagram:
Interrupt . . . . . . . . . . . . . . . . . . . F2-35
TILINE:
I/O Reset . . . . . . . . . . . . . . . . . F2-37
Power Failure Warning . . . . . . . . F2-38
Power Reset . . . . . . . . . . . . . . . F2-39
Slave . . . . . . . . . . . . . . . . . . . . F2-34
Traps:
Address Generator:
I/O Reset and Power Interrupt ... 2.9.3.1
Microcode Interrupt . . . . . . . . . . . 2.9.3.1

Index-7

Digital Systems Division

~------_~

946262-9701

UE, Unit Error ........................ 1.7.8.6
US, Unsafe Bit ........................ 1.7.1.4
Unexpected Interrupt Level
Error Message ................ 3.7.3.2, F3-10
Unit Error UE ........................ 1. 7 .8.6
Unit Select ............................. 1.7.7
Unit:
Selection ............................ T2-17
Jumpers .......................... T2-17
Unsafe Bit US ........................ 1.7.1.4
Utility Verbs, Diagnostic Test ............. T3-S
Verbs:
Diagnostic:
Test ............................... T3-4
Utility ........................... T3-S
Verify Record Header
Data Flow . . . . . . . . . . . . . . . . . . . 2.3.S
Operation, Data Flow for . . . . . . . . . . F2-8
WP, Write Protect Bit. ................. 1.7.1.3
Winchester I/O Board Photograph ......... FI-8
Word:
Carry ............................... 2.8.6
Count .............................. . 1.7.S
Formats, Control and Status ........... Fl-13
Right Shift ......................... 2.8.7.1
Select .............................. 2.4.1.3
Words, Data Flow Loading Command .. 2.3.1

Index-8

Write:
Cycle Timing Diagram, TILINE ..... F2-16
Data:
Clock Encoding ........ 2.12.1. 7, F2-S7
Timing Diagram . . . . . . . . . . . . . F2-S8
Command . . . . . . . . . . . . . . . . . . 1.8.4
Timing Diagram . . . . . . . . . . . . . . F2-S9
Format:
Command Example . . . . . . . . . . . . . Tl-6
Data Flow . . . . . . . . . . . . . . . . .. 2.3.4
Operation, Data Flow for . . . . . . . . . F2-7
Operation, Data Flow for . . . . . . . . . . F2-S
Oscillator Clock . . . . . . . . . . . . . . . . . F3-6
Protect Bit WP ...................... 1.7.1.3
Protect Test, Interactive .............. 3.7.2.6
Timing, TILINE ...................... F3-9
WRITE UNFORMATTED Command ..... 1.8.6
WRITE FORMAT Command ............ 1.8.2
WO, Control Word ..................... FI-14
WO through W7, Control and Status
Word Formats ......................... 1.7
WI, Control Word .................... . Fl-IS
W2, Control Word ..................... FI-16
W3, Control Word ..................... FI-17
W4, Control Word ..................... FI-18
W5, Control Word ..................... Fl-19
W6, Control Word ..................... FI-20
W7, Control Word ..................... FI-21

Digital Systems Division

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Manual Title:

Model 990 Computer 0810 Cartridge Disk Controller Depot
Mai ntenance Manual (946262-9701)

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