0950 0324 10 K500 D Service Manual Mar85

0950-0324-10_K500-D_Service_Manual_Mar85 0950-0324-10_K500-D_Service_Manual_Mar85

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Publication Number 0950-0324-10 Rev.A
March 1985

KSOo-D LOGIC ANALYZER

SERVICE

MANUAL

Gould Inc., Design & Test Systems Division
4650 Old Ironsides Drive
Santa Clara, CA 95054-1805
Telephone: (408) 988-6800
TWX/TELEX # 910-338-0509

P-3/85

Copyright © 1985. No part
of this publication may be
reproduced without written
permission from Gould, Inc.,
Design and Test Systems
Division. Printed in U.S.A.

WARNING

This equipment has not been tested to show compliance with new FCC Rules (47 CFR Part 15) designed
to limit interference to radio and TV reception.
Operation of this equipment in a residential area
is likely to cause unacceptable interference to
radio reception requiring the operator to take
whatever steps are necessary to correct the interference.
The following procedures may help to alleviate the
Radio or Television Interference Problems:
1.

Reorient the antenna of the receiver receiving
the interference.

2.

Relocate the equipment causing the interference
with respect to the receiver (move or change
relative position).

3.

Reconnect the equipment causing the interference into a different outlet so the receiver
and the equipment are connected to different
branch circuits.

4. Remove the equipment from the power source.
Note:
The user may find the following booklet prepared
by the FCC helpful:
How to Identify and Resolve
Radio-TV Interference Problems. This booklet is
available from the u.s. Printing Office, Washington, D.C. 20402. Stock No. 004-000-00345-4.

iii

PREFACE

This manual contains information for servicing and maintaining the GouldBiomation K500-D Logic Analyzer. Separate sections present information about
the theory of operation of printed-circuit board functions, calibration of
internal circuits, and maintenance. Maintenance treats the use of the K500-D
the self-diagnostic routines. The last section contains service aids in the
form of assembly drawings, schematic diagrams, and parts lists.
This service manual is a continuation of the K500-D Operating Manual.
Therefore, this manual begins with Section IV, and pagination begins with page 4-1.
The material in this manual reflects the Control Firmware level valid on
February 30, 1985, and is up-to-date at the time of this publication.
This
information is subject to change without notice.
Copies of this and other publications of Gould Inc., Design and Test Systems
(DATS) Division, may be obtained from the Gould Inc., DATS Division sales
office or distributor serving your localitYe
RELATED PUBLICATIONS
The following
manual:

support

documentation may be used in

conjunction

with

this

K50o-D Logic Analyzer Operating Manual, Publication Number 0950-0004-10
which describes the capabilities, functions, and operation o~ the K500-D
Logic Analyzer.
ASSISTANCE
If you require assistance with this product, please call Gould Inc.,
and Test Systems Division Customer Service on the toll-free, hot-line
listed below:

Nationwide (800) 538 9320/9321
California (800) 662 9231

v

Design
number

WARRANTY

The Gould-Biomation KSOO-D Logic Analyzer is warranted against defects in
materials and workmanship for a period of one year from the date of shipment.
Gould Inc., Design and Test Systems (DATS) Division will repair or replace
units that prove to be defective during the warranty period.
Warranty service must be performed at a Gould Inc., DATS Division authorized
service facility. The customer must call Gould's Customer Service department
at the toll-free numbers listed in the front of this manual and obtain a
Return Authorization number prior to returning the unit for service.
If a
unit fails within 30 days of shipment date, Gould Inc. will pay all shipping
charges related_to the repair of the unit. Units under warranty, but beyond
the 30-day period, should be sent to Gould Inc., prepaid, and Gould Inc. will
return the unit prepaid. The customer must pay all shipping for units out of
the warranty.
Misuse of, abuse of, or tampering with this unit will, at the discretion of
Gould Incorporated, cause this warranty to be null and void.

vii

CONTENTS

Page

Section

IV

THEORY OF OPERATION • • •
4.1 INTRODUCTION • • • •
4.2 BASIC DESCRIPTION • • • • • •
4.2.1
Keyboard •
4.2.2
Front Panel ••
4.2.3
CRT Display
••••
4.2.4
Power Supply • • • • • • • • • • •
4.2.5
Data-Display Board • • • • • •
4.2.6
MPU Board • • • • • •
4.2.7
Threshold/GPIB Board • • • • • • •
4.2.8
Input Board • • • • • • • • • • •
4.2.9
Record-Control Board •
4.2.10
Analog Board.

4-1
4-1
4-1
4-1
4-1
4-1
4-3
4-3
4-8
4-10
4-13
4-15
4-18

V

CALIBRATION PROCEDURES • • • •
5.1 RECALIBRATION OF INTERL~AL CIRCUITS •
5.2 REQUIRED TEST EQUIPMENT • • • • • • •
5.3 CALIBRATION OF RASTER SCAN DISPLAY •
5.3.1
Front-Panel Controls • • • • • • •
5.4 POWER-SUPPLY ADJUSTMENTS • • • • • •
5.4.1
Type I and Type II Power-Supply
Adjustment Procedures • • • • • • • • •
5.4.2
Type III Power-Supply Maintnance
Procedures • • • • • • • • • • •
5.5 PROBE POWER-SUPPLY VERIFICATION ••
5.6 THRESHOLD ADJUSTMENTS. • •
• •••
5.7 RECORD-CONTROL ADJUSTMENTS.
• •••••••
5.8 ADJUSTMENT OF INPUT BOARDS
••••••••
5.9 ANALOG-BOARD ADJUSTMENT. •
• ••••••••
5.9.1
Analog-Probe Compensation ••
5.9.2
Comparator Check • • • • • •
5.9.3
Calibration • • • • • • •
5.9.4
Square-Wave Tests • • • •
5.9.5
Sine-Wave Performance ••

5-1
5-1
5-1
5-2
5-2
5-4

5-7
5-8
5-8
5-9
5-10
5-11
5-12
5-12
5-13
5-13
5-14

MAINTENANCE • • • • • • • • • • • • •
6 • 1 INTRODUCTION. • • • • • • • • • .•
6.2 DIAGNOSTIC ROUTINE AND INDICATIONS •
• •••
6.2.1
2.1-Level Firmware. ••
• ••••
6.2.2
Memory Error Interpretation ••
6.2.3
3.1-Level Firmware • • • • • •
6.3 REQUIRED TEST EQUIPMENT • • • • • • • •
6.4 DIAGNOSTIC AND TROUBLESHOOTING PROCEDURES.
6.4.1
Equipment Set-Up • • •
• • ••
6.4.2
Combinational Trigger. •
• • ••
6.4.3
Threshold Checks •
• • • •
6.4.4
Internal Clock • • • • •
6.4.5
Filter Test. • • • • • • • • • • •
6.4.6
Trigger Delay Test • • • • •
6.4.7
Analog Test.

6-1
6-1
6-1
6-1
6-6
6-6
6-9
6-11
6-11
6-12
6-12
6-12
6-13
6-13
6-14

VI

ix

5-5

Section
VI

VII

Page
MAINTENANCE (Cont'd.)
6.4.8
Display Functions • • • • • • • • •
6.4.9
Auto-Compare Operation • • • • • •
6.4.10
Input Performance (Glitch Capture)
6.4.11
Qualifier Tests • • • • • • •
6.4.12
Self-Test Mode • • • • • • • •
6.4.13
K500-D Self-Test Description •

6-14
6-22
6-23
6-25
6-25
6-26

SCHEMATIC AND ASSEMBLY DRAWINGS
7.1 INTRODUCTION • • •
7.2 LIST OF DRAWINGS • • • • • •

7-1
7-1
7-1

Figure

Page

4-1
4-2
4-3
4-4
4-5

KSOO-D Block Diagram
K500-D Horizontal Timing.
KSOO-D Vertical Timing. •
Memory Map. • • • • •
CRT RAM Addressing. • • •

4-2
4-4
4-7
4-9
4-11

5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10

Status Display and Keyboard •
••• • •
Position of Status-Mode Display • • • • • •
Data-Display Assembly • • • • • •
• • • •
Power-Supply Adjustments. • • •
• •••••
Power~SupplyMonitoring Points and Status LEDs.
Type III Power-Supply Voltage Measurements.
Threshold/GPIB/RS232 Board. • • • • • •
Record-Control Board • • • • • • • • • • • • •
Input Board (two per L500-D) • • •
Analog-Board Adjustment • • • • •

5-3
5-3
5-4
5-5
5-5
5-7
5-8
5-10
5-11
5-12

6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24

High-Speed-Record Memory Failure. •
Checksum-Test Failure • • • • • • •
Microprocessor RAM-Test Failure •
Glitch-Termination Fixture, Schematic •
Normal Status-Display Screen. •
Display-Functions Test, Timing ••
Display-Functions Test, X10
Display-Functions Test, X20 • •
Display-Functions Test, X50 • • •
Display-Functions Test, Binary Data • • • • •
Display-Functions Test, Octal Data ••
Display-Functions Test, Hexidecimal Data.
Display-Functions Test, Special Data. • •
Display-Functions Test, Search Data • • •
Display-Functions Test, Sequence Hexidecimal Data
Display-Functions Test, Sequence Hexidecimal Data
Display-Functions Test, X50 Timing. • • • •
Display-Functions Test, Sequence Timing • •
Display-Functions Test, Analog X20 Timing
Display-Functions Test, Scroll Timing •
Input-Performance Test, ECL 10MHZ • • • • • •
Input-Performance Test, TTL 10MHZ •
Input-Performance Test, EeL SMHZ • • • • • •
Input-Performance Test, TTL 5MHZ ••

6-5
6-7
6-8
6-10
6-11
6-15
6-15
6-16
6-16
6-17
6-18
6-18
6-19
6-19
6-20
6-20
6-21
6-21
6-22
6-22
6-23
6-23
6-24
6-24

x

Page

Figure

6-25
6-26

Self-Test, Status Display Screen ••
Self-Test Summary • • • • • • • • • •

Table

4-1
5-1
6-1
6-2
6-3

6-25
6-26
Page

Sync/Blanking Relationship. • •
Test Equipment • • • • • • • • • • • • • • • • • •
Identification of F~iled Record Memory IC Package
Related to the Input Channel and Clock Phase.
Powerup RAM-Test Location Map • • • • •
• • • • •
Internal Clock Tests. • • • • • • • • • • • •

xi

4-5
5-1
6-7
6-9
6-13

OPERATING AND SERVICE MANUAL
MODEL KSOO-D LOGIC ANALYZER
SECTION IV
THEORY OF OPERATION

4. 1

I ntrod uction

This section provides a detailed block diagram description of the Model
K500-D Logic Analyzer.
4.2

Basic Description

Figure 4.1 is a Block Diagram of the K500-D. The blocks are arranged in
their approximate physical locations as viewed from the top of the instrument.
4.2.1

Keyboard

The keyboard consists of 48 keys and an error LED that are controlled by
the microprocessor through the data display board. The keys are arranged
in an X-Y matrix. There are eight columns (vertical) and six rows (horizontal). When a key is pressed it makes a connection between the appropriate row and column. The microprocessor scans the entire matrix 60 times
per second and any resulting key codes are stored in a queue for further
processing. Any. improper sequence of commands will result in turning on
the error LED.
4.2.2

Front Panel

The Front Panel contains, from left to right, the power ON/OFF switch, a
power on indicator LED, the switches for controlling the auto/manual mode
for the Arm, Enable and Trigger functions, the M to A switch and the connectors for the Probes. The switches on the front panel are read by the
microprocessor as one of the rows of the X-Y matrix on the keyboard. The
connectors provide power (+11 V and -5.2 V) and threshold voltages from the
mother board to the digital probes. The data from the probes is connected
directly to the input boards. Channels 0-3 connect to input board #1, the
board on the inside of the record control. Channels 4-7 connect to input
board #2, the outside board. The external clock and the trigger qualifier
connect to the Record Control board. The analog probe is hooked directly
to the analog board.
4.2.3

CRT display

The CRT display
It displays 240
refresh rate.
CRT and yoke are

is a seven-inch (diagonal measure) raster scan display.
lines of noninterlaced video at either a 50 Hz or 60 Hz
All of the power requirements and drive signals for the
derived from the data display board.

They are:
-horizontal deflection
-vertical deflection
-video: +30 V, cathode
-brightness: -40 V grid
-filament: +12 V
-focus: +200 V, grid 2 and 3
-anode: +10 KV

COMPOSITE
VIDEO

RESET

GPIB BUS
INTERFACE

I

SWITCHING
POWER
SUPPLY
:t 15V
:t 5V

- 2V
-5.2V

CRT
KEYBOARD
INTERRUPTS

CLOCK
ARM
OUT
IN
TRIGGER
IN OUT
I

I

MICRO
PROCESSOR

GPIB
INTERFACE

8086
RAM
ROM

THRESHOLD
VOLTAGES

ANALOG
TO
DIGITAL
CONVERTER

INPUT
#1

RECORD
CONTROL

INPUT
#2

CHANNELS
0·3

EXTERNAL
CLOCK

CHANNELS
4·7

TRIGGER
QUALIFIER

t

f

.-----_+---.---I

t

t

t

~

~'-+-+D~A~T~A~B~U~SS~-------l~~I-----~--~--------r-~------~~-------+~--~

CRT
DISPLAY

ADDRESSI

FRONT PANEL

KEYBOARD

~,--------,~,--------~#

PROBES

Figure 4-1.

KSOO-D Biock Diagram

4-2

Power Supply

4.2.4

4.2.4.1

Type I and Type II Power Supplies

The Types I and II power supplies for the K500-D are
operate from 50 Hz or 60 Hz power at 110 V or 220 V.
the rear panel is used to select the voltage range.

designed
A switch

to

on

The power supplies provide regulated power at the following voltages
and currents:
+15
-15
+ 5
- 2
-5.2

volts
volts
volts
volts
volts

up
up
up
up
up

to
to
to
to
to

1.5
1.0
10
12
30

amps
amps
amps
amps
amps

+5 V and -5.2 V ate available at up to 1 amp each on Lemo connectors
on the rear panel for operating accessories.
The power supplies use a 20 kHz switching regulator to provide the
-5.2 V output, and secondary voltages are provided by standard
linear regulators. All of the outputs are current limited.
The
power supplies also have a series of LED indicators showing the
status of operation: a green indicator for proper voltage, and a red
indicator for over-current conditions.
/ 4.2.4.2

Type III Power Supply

The description of the Type III power supply is the same as that of
Types I and II. power supplies except there are no LED indicators for
voltage and over-current conditions.
4.2.5

Data-Display Board

(Reference Schematic 0114-0191)

The data-display board provides circuitry for the following functions:
CRT Controller
Horizontal Deflection and High Voltage
Vertical Deflection
Video
Keyboard and Front Panel Interface
Interrupt Processing Interface
4.2.5.1

CRT Controller

(Reference Sheet 3)

The CRT controller drawing is shown in the schematic section of the
manual. The desired CRT display pattern is computed by the microprocessor and stored in the RA~1 as a complete dot map; i. e., every dot
location of the CRT is represented by a bit in the RAM ell n = white
"a" = black). A typical procedure is:
'
1)

The CRT display addresses are all set to zero (blanking the
CRT) .

2)

The microprocessor converts each displayed character into a
pattern of "1 t s" and "0 t sit and stores them in the proper locations in RAM.

3)

The CRT controller continuously cycles through the RAM and
translates the information to the CRT. A 16-bit word is read
from the RAM every 2 ps and converted into a string of 16 dots
on the CRT.

The CRT Controller generates a standard raster scan display format
with data being presented as a series of horizontally scanned lines.
Each horizontal line is presented starting at the left side and proceeding to the right side. The first horizontal line is displayed at
the top and the last is at the bottom. Standard sync and blanking
signals are generated.
Horizontal Timing - Each horizontal scan line is 64 ps long and presents 52 ps of video with 12 ps blanked and a 6 ns sync pulse during
the blank time. The horizontal sequence generated by the timing
counter is shown in Figure 4.2.

TIMING

lIS

62

63

0

3'

2

4

5

6

7

8

9

10

11

12

13

14

15

'Iz MHz CLOCK
AO

.J

L
L

A1
A2

L

___________________________________________r

A3

A4

'ti1ii:A'NK (PROM)
H!YNC (PROM)
HORIZONTAL BLANKING _ _ _ _ _ _ __
HORIZONTAL SYN; _ _ _ _ _ _ _ _ _ _

HORIZONTAL DRIVE

=A4

DISPLAYED DATA

----..II

WORD 31

I

B~}T,~
~ITO

.---.1

WORD 0

·-=====~B[LAiANNiKKiEr.:D)::======:::'=':;~:rl----

~hEI~~EI

t

WORD 1

WORD 2

WORD 3

WORD 4

I

nJ

B~}T,~
~TO

BIT 7

Figure 4-2.

WORD 5

I

BIT 7

KSOO-D Horizontal Timing

4-4

.

WORD 6

~hEI~~EI §

t

'1 r"

The counter runs continuously at a 500 kHz rate generating the five
address lines for the horizontal ROM. The ROM decodes the address to
produce the blanking sync and top count (end of line) pulses. Horizontal blanking interval occurs for the first 12 ~s after the counter
rolls over, states 0 through 5. The sync pulse s·tarts 2 ~s after the
blanking and lasts 6 ~s. In addition to addressing the ROM, the fifth
address line is used by the horizontal drive for the deflection. The
horizontal timing is not affected by 50 Hz/60 Hz selection.
Note:

The Enable Address Counter signal is not used on the K500-0.

Vertical Timing - The vertical timing is generated by the higher order
bits of the same counter as the horizontal timing. The relationship
between the sync and the blanking for both 50 Hz and 60 Hz operation
are shown in Table 4-1.

Table 4-1.

Sync/Blanking Relationship

60 Hz
3 lines

50 Hz
28 lines

3 lines
15 lines

3 lines
40 lines

240 lines

240 lines

Delay from beginning of blanking
to sync
Width of sync
Delay from end of sync to end of
blanking
Width of scan (display)

4-1:)

The vertical timing sequence begins as the counter rolls over (000).
The vertical ROM decodes the states of the counter as shown in the
timing diagram, Figure 4.3, producing the vertical blanking and sync
signals. At the end of the blanking, the vertical top count (VTC)
combined with the HTC will preset the counter to the state corresponding to 240 lines before rollover. Then, after the 240 active
(displayed) lines are counted, the counter rolls over and the process
is repeated. A pulse is generated at the end of the blanking interval
that sets the timer interrupt that is used for initiating the keyboard
read routine.
4.2.5.2

Horizontal Deflection and High Voltage

(Sheet 1)

The horizontal drive signal from the CRT controller synchronizes the
horizontal scanning with the retrace blanking by controlling the horizontal drive transistor.
The horizontal drive transistor serves two purposes; it provides energy to the flyback transformer, and it draws current from the horizontal deflection coil to generate the scan from left to right. The
flyback transformer provides the energy for the rapid retrace from
right to left and it serves as a DC to DC converter for generating the
operating voltages for the CRT. These voltages are +10 KV for the
anode, +200 V for focus, +30 V for the cathode and -40 V for the grid.
The focus and brightness of the CRT are adjustable on this circuit
board. The deflection circuity also contains variable inductors for
control of horizontal width and horizontal linearity.

4.2.5.3'

Vertical Deflection

(Sheet 2)

The vertical processor generates and synchronizes the vertical scanning. The vertical processor drives the vertical deflection coil directly and senses the current through the coil through a sense
resistor. The processor contains an oscillator that is synchronized
to the vertical sync pulse, an adjustable constant current source ramp
generator, an emitter follower, and a power. amplifer to drive the
coil. The vertical processor circuitry allows adjustment of vertical
hold, vertical height, and vertical linearity.

4.2.5.4

Video

(Sheet 3)

Controlling the brightness on the CRT is done by combining the digital
data with the horizontal and vertical blanking signals and switching
the cathode voltage between 0 V (white) and +30 V (black). In order to
provide a sharper display presentation the video is modulated by an 8
MHz clock signal. A composite video signal is also generated and is
available at the rear panel for use with another monitor or a video
printer.

4.2.5.5

Keyboard and Front-Panel Interface

(Sheet 4)

Sheet 4 of the data display schematic contains the microprocessor
interface for the keyboard front panel and the interrupt processor.
The keyboard and the front panel are addressed by the microprocessor
at the same time. The interface circuitry decodes eight addresses out
of the memory page assigned for I/O functions. Each address corresponds to a row in the keyboard array. Each row is read as a byte at a
60 Hz rate(or 50 Hz, depending on the vertical rate selected), ~~y key
contact that is closed will be stored as a zero within that byte.
Each bit of the byte corresponds to a column on the keyboard.

4-6

HORIZONTAL TC ..LI...II...II...II...II....I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
VERTICAL ADDRESS

~~ ~~ ~

VTC--------------------------------__LJ

FOR
60 Hz

~ ~ ES~ ~ ~

VERTICAL BLANK _ - _...

VERTICAL SYNC _ _ _ _ _

~I1L.--------------------

~uo~~g~NM~~~~=mR96

-I -

\

i' ;

J

~~

~R129

aRa7
0R94

•••••••••
•••••••••
•••••••••
•• •• ••• • •
•••••••••
•••••••••
::::::(;~~

eR141

..... 1

> ..... '

~: ~ ~

""1;,.,,,,\
@j

Type I

'!

I

*
.

Type II

Figure 5-4.

Power-Supply Adjustments

Type I and Type II Power-Supply Adjustment Procedures

5.4.1

The overcurrent adjustments (I) have been calibrated at the factory
and should not need any readjustment. A special test load and current
probe is necessary to set the overcurrent conditions.
Precise settings can only be performed at the factory.

Note:

Refer to Figure 5-5 for power-supply monitoring point.

N
&n
...,

I

+

I

~~;~~ii~~~

N
•

_(\,1\1')101)

1·····!00•• ·1

•
"'.."
Ll'Lf)N_ ...

+

I

•

+ •

~0

J2

1

Io..-I0_ _J_l

_---'11

GREEN
LEOS

Type I
Figure 5-5.

RED
LEDS

Type II
Power-Supply Monitoring Points and Status LEDs

5-5

Power Supply Adjustments (Type I)

1.

Adjust R87 for -5.30 V ±0.01 V at J1-11, 13, 15, 17, or 19.

2.

Adjust R141 for +5.05 V ±0.01 V at J2-3, 5, 7, or 9.

3.

Adjust R63 for +15.0 V ±0.01 V at Jl-3.

4.

Adjust R64 for -15.0 V ±0.01 V at J1-1.

5.

Adjust R129 for -2.10 V ±0.01 V at Jl-5, 7, or 9.

Power Supply Adjustments (Type II)

Note:

1.

Adjust -5.2V POT for -5.30 V ±0.01 V at Jl-4,5,6 and J3-4,5.

2.

Adjust +5V POT for +5.05 V ±0.01. V at Jl-2,3 and J3-2,3.

3.

Adjust +15V POT for +15.0 V ±0.01 V at J4-7.

4.

Adjust -15V POT for -15.0 V ±0.01 V at J2-8.

5.

Adjust -2V POT for -2.1 V ±O. 01 V at J2-4,5 and J4-3.

All 5 green LEOs should be on. If any red error status LEOs flash,
determine which voltage or voltages have overcurrent conditions. Read
the labeling of the LEOs to determine which is which.

5-6

5.4.2

Type III Power-Supply Maintenance Procedures

The Type III Power Supply does not contain adjustments accessible to the
user. A voltage measurement check is conducted to determine if the power
supply is functioning properly.
If the measured voltages are not within
the specified limits, the power supply must be replaced.
'Measure the voltages at locations on the power supply terminal board
which are accessible to the user.
Refer to Figure 5.6.
Take the measurement between the specified voltage signal and its respective return.
The measured voltages must be within the following ranges:
RANGE
NOMINAL VOLTAGE

MINIMUM

MAXIMUM

+15V

+14.5V

to

+15.5V

+ 5V

+ 4.8V

to

+ 5.2V

- 2V

- 2.25V

to

- 1.95V

- 5.3V

- 5.50V

to

- 5.00V

-15V

-15.40V

to

-14.60V

POWER
SUPPLY

N

tu

en

w

a:

~

+

~

~

~

~

z z
t~ a:

~

~

~

~

~

+

~
~

+

Figure 5.6.

+

I

~

Z
t-

a:

~
~

I

~

N
I

m

N
I

0

~

N

~

~

Z
t-

N

N

N

I

I

I

~

~

Z

Z

~

~~~~~~~~

Z

~ a:

.

N

N
I

lIS

lIS

lIS

~ ~
N

N

I

I

lIS

lIS

Z

t-

a:
N

lIS
I

Type III Power-Supply Voltage Measurements

5-7

~O

5.5

Probe Power-Supply Verification

Using a DVM, check the voltage at the upper-left corner pin of all ten of the
probe connectors at the front panel.
The probe voltage at this point should
read +11.10 V + 0.20 V.
Also check the voltage at the lower-right corner pin
of all ten probe connectors.
The voltages at these points should read -5.2 V
+ 0.05 V.
5.6

"Threshold Adjustments

Turn the K500-D on and allow five minutes for power supply to stabilize.
Status mode should appear. Refer to Figure 5.6.
Monitor the lower-left corner pin of front-panel probe connectors for all
10 channels with DVM. Use ground clip test point on top of MPU board.

ITHRESHOLD I '" ~VAR A (Step 1~

KEYSTROKE

tENTER I ,

~

ISPECIFYI

IAUTOARM I.

IENTERI,

Rl

R2

R3

R5

Figure 5.7.
NOTE:

(10 times),

VAR A (Step 2)
VAR B (Step 3)
VAR B (Step 4)

~~!
VAR

w-

B

+

,VAR B

R6

R7

~~~:~ ~~J
(Step

[§],

. , rn, rn

3)

(Step 4)

R8

R9

Threshold/CPIB/RS232 Board

When adjusting VAR A (pots R9 and R6) for set up, readjustment may be
necessary until both positive and negative voltages are correct.
A
similar notice applies to VAR B (pots R2 and R1).

Use ItVAR A","VAR A", and "_" for set up. Threshold test point for each
connector sh~uld read +5.08 V ±50 mV. Adjust pot R9 to obtain proper value.
Use "VAR A", "VAR A", and "+" for set up. Threshold test points for each
connector should read -5.08 V ±50 mV. Adjust pot R6 to obtain proper value.
Use "VAR BIf, "VAR Bit, and ,,_It for set up. Threshold test point for each
connector should read +5.08 V ±50 mV. Adjust pot R2 to obtain proper value.
Use "VAR B", "VAR B", and "+" for set up. Threshold test point for each
connector should read -5.08 V ±50 mY. Adjust pot Rl to obtain proper value.
5-8

To adjust R44 (precision +10-volt adjustment), place the positive (+) lead of
DVM on the right side of R38 and negative (-) lead on the nearby Analog ground
(A ground). Adjust R44 until a reading of +10.00 volts is obtained. Earlier
units may not have an R44 adjustment.
To adjust R3 and R5 ADC calibration pots, set up Self-Test to loop on Test 50.
Adjust R3 offset pot until the result equals 0 volts.
Loop on Test 60, and
adjust R5 until the result equals +10.0 volts.

Note:

The Self Test DAC adjustments (R3 and R5) have been factory calibrated
and should not need any readjustment. They are adjusted properly if
K500-D passes Self Test numbers 50 and 60.

KEYSTROKE THRESHOLD
1.

, TTL (10 times), ENTER, AUTO ARM .

Test point should read -1.12 V ±50 mV.

Readjust R8 to obtain proper

value.
KEYSTROKE THRESHOLD
1.

, ECL (10 times), ENTER,

Test point should read +1.04 V ±50 mV.

AUTOARM.
Readjust R7 to obtain proper

value.
5.7

Record-Control Adjustments

Remove the Record Control Board and place it on an extender card. It is necessary to disconnect some of the coaxial cable connectors in order to remove the
board.
Reconnect any cables that were disconnected, and turn on the KSOO-D.
Tests are performed using power-up status mode.
1)

If the error light starts flashing, push the "CE!! button so that the Status
mode appears. Verify that the K500-D status display shows "CLOCK 2 nSEC".

2)

Refer to Figure 5.8. Monitor IC 1B pin 7 with Tek P62"01 FET ·probe using
Tektronix 7A19 vertical amplifier in Tektronix 7904 mainframe oscilloscope
(or Tek 485). It is extremely important to use special Tektronix probe tip
bayonet assembly in order to probe at the nearest possible ground while
looking at the signal of interest. Pins 6 and 7 are ground for all lOOK ECL
ICs. Adjust R4 for best possible 200 MHz ECL waveform. The signal at this
point &hould swing symmetrically about ECL threshold (-1.3 V) and have 50%
duty cycle. There should be no edge jitter or fuzziness of waveform edges.

3)

With same oscilloscope set up as in step 2, monitor IC 3C pin 2. Adjust R80
for best possible, 250 ~1Hz, ECL threshold. The signal should swing
symmetrically about ECL threshold, have 50% duty cycle, and no edge jitter
or fuzzy edges. Be sure to simultaneously probe ground point with probe
tip bayonet assembly at either IC 3C pin 6 or 7.

4) Using Frequency counter, monitor IC 3C pin 2.

Note:

It may be easier to use bottom lead of R71 instead of IC 3C pin 2.
Verify if frequency counter needs to be capacitively coupled externally.
If necessary; use 200 pF capacitor in series with the frequency counter
lead.

5)

Adjust trimmer capacitor C84 until frequency is very close to, but slightly
below 250 MHz. Signal may still be unstable in frequency.

6)

Adjust trimmer capacitor C13 until signal locks in.
now read 250 MHz ± instability in last digit (LSB).

5-9

The frequency should

Note:

These two adjustments in steps 5 and 6 are very sensitive, and care
must be taken to insure proper frequency. It may be advisable to use
an adjustment tool with a non-metallic tip, as the metal tip tool can affect
the adjustment.

7)

Monitor IC llA pin 21 with scope. Pick up ground connection at adjacent
coaxial connector. Adjust R39 for Symmetrical ECL signal about threshold.
Frequency should be 250 MHz.

8)

Verify that 250 MHz ECL signals are also at IC llA pins 8, 9, 23, and 24.
Use pins 6 or 7, or coax connector for ground.

9)

Monitor IC 20A pin 15 with DVM.
Adjust R55 for 1.375 V + 0.010
This adjustment is for Trigger Qualifier.

V~

Monitor IC 8B pin 17 with DVM.
Adjust R41 for 1.375 V + 0.010 V.
This adjustment is for External Clock.
Note: Steps 9 and 10 are nominal adjustments and may require readjustment
using scope with signal applied to T .Q. or Ext. Clock probe inputs.
Whether or not adjustment with scope is necessary may be determined in
the Maintenance section of this manual.

10)

11)

Replace the Record Control board back into its chassis position.
that all cables are reconnected properly.
R41

R39

~ ••

~

...

Verify

f":"'"l].,..

~:

' "'E}: ...
~
fit

t

......

-=-~

hi

R4 ___~
R80

R55

C13
C84

Figure 5.8.
5.8

Record Control Board

Adjustment of Input Boards

Remove the channel '0-3' Input board from its chassis position and place it on
an extender card.
It is necessary to disconnect some of the coax connectors
in order to remove the board.
Reconnect any cables that were disconnected,
and turn on the K500-D. Tests are performed using power-up status mode.
1)

If the error light starts flashing, push the blue CE button so that the
status mode appears. Verify that the K500-D status display shows "CLOCK 2
nSEC" .

5-10

2)

Refer to Figure 5.8. Monitor IC 19D pin 5 with Tek P6201 FET probe using
Tektronix 7A19 vertical amplifier in Tektronix 7904 mainframe oscilloscope
or (Tek 485). It is extremely important to use special Tektronix probe tip
bayonet assembly in order to probe the nearest possible ground point while
probing at the signal of interest. Use pin 6 or 7 of any lOOK ECL IC, or a
coax cor~ector for ground. Adjust R49 until a good symmetrical, 50% duty
cycle, 250 MHz ECL waveform is present.

3)

Monitor the following points with DVM, and adjust the
for -1.375 V + 0.005 V.
14B
14D

lIB
lID

pin
pin
pin
pin

21
21
21
21

pot
pot
pot
pot

correspondi~g

pots

R41
R73
R69
R70

Note: Step 3 adjusts the data pots to a nominal value. These pots may
require readjustment using scope with data applied to the channel inputs
of interest. Whether or not adjustment with oscilloscope is necessary
may be determined in the Maintenance section of this manual.

4)

Remove the '0-3' Input board from the extender board and replace it into
the chassis position. Carefully reconnect all cables.

5)

Remove the '4-7' Input board from its chassis position and place it on an
extender board in the chassis. Repeat steps 1 through 4 for the channel
'4-7' input board.

6)

Press and release the reset switch on the back panel. The K500-D should
now re-cycle and status mode should appear on the CRT display .

. R73

Figure 5.9.
5.9

R41

Input Board (two per K500-D)

Analog Board Adjustment

Remove the Analog board from its chassis position and place it on an
extender card. Reconnect any cables that may have been disconnected for easier
removal of the board. Turn on the K500-D and allow 10 minutes for warm-up
period. STATUS mode should appear. Refer to Figure 5.9 for Analog board
adjustments.
5-11

Note:

When the Analog board is on the extender card, the Analog input cable
from the front panel BNC will not reach the Analog board. Use special
Analog input 9' test cable instead. The test cable is the same length as
cable to front panel.

R21 & R32 Junction

R158
•
Kl Pin 14--+--------11.

Rl17
R79
Gain
R126

P3

•
Figure 5.10.
5.9.1

Analog-Board Adjustment

Analog-Probe Compensation

1)

With the Analog board on the extender card in the analog slot of the
KSOO-D, connect the Analog clock (CLKAA) cable from the Record
Control board to the ribbon cable from the '0-3' Input board (match
pin 1 with the square pad, hole 1). Connect the plug-end of the Tek
P6108 Analog probe to the BNC-end of the test Analog-input jack on
the Analog board.
Plug a BNC "Tee" into the scope input (50 ohm)
and connect one branch of the "Tee" to the output of the Tek PG502
pulse generator using a BNC cable. Insert a "stub" of wire into the
other branch of the "Tee", and connect the Analog probe-tip to the
stub and the probe-ground lead to the BNC "Tee" ground with the
alli,gator clip.
Use 50-ohm back termination of pulse generator.
Use short ground.

2)

Set the pulse-generator output for 1.0 KHz square waves at an amplitude of 2.0 volts, peak to peak, centered about ground.

3)

Set the K500-D as follows: Analog mode, auto-trigger, 100 usec
clock, 1.0 V/div, 0 V offset, and timing display. Press auto arm and
adjust the probe compensation (at the probe body using an adjustment
tool) until the K500-D display shows a waveform of maximum amplitude
with clean leading and trailing edges. Expanding the display to X20
will make this easier to see.
If necessary, adjust pot R79 (GAIN)
so the displayed waveform has an amplitude of 2.0 volts, p-p.
Do
not be concerned at this time if the waveform is offset from 0
voltR.
5-12

5.9.2
1)

Comparator Check
Connect the BNC cable to the output of the function generator, and set
it for a 2.0 V p-p triangle wave at 100 Hz. Change the K500-D clock to
1 ps, gain setting to 0.5 V/div, and press manual arm. Timing X20.
The display should show a staircase of 15 discrete levels. If not all
of the levels are shown, the board must be repaired befo~e the
alignment procedure can continue.
Determine which comparator
output(s) are not switching or have wrong levels and troubleshoot and
repair. Recheck the display for all 15 discrete levels.

5.9.3

Calibration

1)

Disconnect the BNC cable from the function generator, and leave it
disconnected. Set the K500-D for a 2 nsec clock, and press manual arm.
With the FET probe, look at U24 pin 13, using the shortest possible
ground lead. Adjust pot Rl17 (CLKAA REFERENCE) for a 50% duty cycle
clock signal.

2)

Connect the DVM (+) lead to the bottom of R150 near the LM324 op-amp.
Connect the (-) lead to analog ground.

3)

Make sure the K500-D Analog offset is still 0 volts and the gain is 0.5
V/div. Adjust R148 (DAC OFFSET) for a DVM reading of 0 V ±20 mV.

4)

Change the offset to +5.0 V, and adjust R143 (DAC GAIN) for a reading
of +5.0 V ±20 mV.

5)

Check the other offset settings to see if they are all within ±20 mV of
their nominal setting. If necessary, readjust the DAC offset and DAC
gain pot.

6)

Move the DVM (+) lead to the bottom of R90 (junction with R64) and
adjust R109 (REFERENCE) for a reading of 250 mV ±1 mV.

7)

Change the offset back to 0 volts. Connect the DVM (+) lead to pin 14
of relay K1. Adjust R126 (1st OFFSET) so that the reading varies no
more than 2 mV from the highest to lowest reading, as the gain is
changed from 0.5 to 1.0 to 2.0 V/div.

8)

Move the DVM (+) lead to the junction of R21 and R32. Adjust R158 (2nd
OFFSET) so that all three gain settings read as c.lose as possible to
-45 mV ±2 mV.

9)

Verify the proper calibration by observing the timing display at 0 V
and -1 V offset, and all three gain settings. At -1 V offset and 0.5
V/div, the trace line is one bit below zero; at all others, the line
is at 7 V. If not, repeat steps 6 through 8.

10) Turn the Self-Test switch on and run the 700-Series Tests.
should now pass.
5.9.4

The board

Square-Wave Tests

These tests and adjustments must be performed with the Analog board
installed in the chassis, using the actual input cable built into the
K500-D.

5-13

1)

Plug the BNC ~able into the pulse generator and verify that it is still
set for a 2.0 V p-p square wave at 1 KHz. Set the K500-D for a 100
microsecond clock and press auto arm. Adjust the probe compensation
for the maximum amplitude with clean rising and falling edges. If
necessary, adjust the GAIN and 2nd OFFSET pots to obtain a display that
is exactly 2.0 volts p-p, and is centered about O. No other pots
should be adjusted at this stage of the procedure. View the analog
signal in Timing X20.

2)

Change the pulse generator to a 1 MHz square wave at 2.0 volts p-p.
Change the K500-D clock rate to 100 nsec, and press auto arm. Verify
that the probe, gain, and offset adjustments are still correct by
observing the timing display in X20.

3)

Repeat step 2, except change the pulse generator to a 10 MHz, 2.0 V p-p
square wave, and the K500-D clock to 10 nsec. There may be a slight
"notch" in the rising edge of the displayed waveform. This is
acceptable.

5.9.5

Sine-Wave Performance

The following tests must be performed to ensure that the K500-D will
have acceptable analog performance.
1)

Connect the BNC cable to the sine wave generator, and set it for 1.75 V
p-p at 100 MHz. Set K5'00-D clock to 2 nsec, Analog mode, Analog
trigger, offset = 0 gain = 1 V/div, Auto Enable, Timing X10, Auto Arm.
Verify that the sine wave displayed is ~2. 0 V p-p and is properly
centered about O. Adjust the 2nd OFFSET pot, if necessary, to make it
centered.

2)

Increase sine wave generator output amplitude to 2.75 V p-p and verify
that the displayed waveform is ~2. 0 V p-p and is properly centered
about o.

3)

Set sine wave generator frequency to 50 ~rnz. Adjust amplitude to 1.75
V p-p and verify that the displayed waveform is ~2. 0 V p-p and is
properly centered about O.

4)

Increase sine wave amplitude to 2.75 V p-p at 50 MHz and verify that
the displayed waveform is ~2.0 V p-p and is properly centered about O.

5)

Set sine wave generator frequency to 10 ~rnz. Adjust amplitude to 1.75
V p-p. Change K500-D clock to 5 nsec and auto arm. Verify that the
displayed waveform is ~2.0 V p-p is centered about O.

6)

Increase amplitude to 2.25 V p-p at
X20. Manual arm 10 times. Observe
for any "nicks", which indicate the
out of ten of the ten recordings must

7)

Verify that the analog board still passes the 700 series self test.

10 MHz. Expand timing display to
the displayed waveform each time
converter is non-monotonic. Nine
display no "nicks II •

THIS COMPLETES THE CALIBRATION OF THE KSOO-D.

5-14

OPERATING AND SERVICE MANUAL
MODEL K500-D LOGIC ANALYZER
SECTION VI
MAINTENANCE

6. 1

Introduction

This section covers the K500-D self-diagnostic routine within the
instrument. The diagnostic routine checks the microprocessor ROMs and RAMs.
Repair of other boards can be performed with the aid of the technical
description or additional information from the factory.
The drawings in Section VII have been included to aid service personnel who
wish to troubleshoot to the component level. Additional assistance in a·
particular problem can be obtained by contacting the Customer Service Department
at the factory: Phone (408) 988-6800, TWX 910-338-0509.
In summary, there are two methods of service available:
1.

Return the entire unit to the factory or service center for repair.

2.

Troubleshoot the problem to the component level with the aid of the
Technical Description and schematics or with the aid of factory personnel.

6.2

Diagnostic Routine and Indications

6.2.1

2.1 level firmware

The following procedure pertains to the 2.1 and earlier firmware levels.
(The firmware level is displayed in the lower-right of the CRT screen upon
power up.)
The KSOO-D diagnostic routine performs the following checks
every time the power is ~urned on.
The K500-D diagnostic routine performs the following checks
power switch is turned on.

every time the

1.

All keys and switches on the front panel, except AC POWER, are checked for a
"not pressed" condition. If any key or switch is pressed or shorted, an
error indication is given.

2.

All 32,768 bytes of microprocessor RAM are checked by writing and reading
data to and from every bit. If any failure is detected, an error indication
is given.

3.

All 65,536 bytes of microprocessor ROM are checked. A CRC byte is generated
for each ROM when the ROM is "burnt". CRC is an abbreviation for "Cycle
Redundancy Check", and is a type of error detection method where a check
character for each ROM is created. The diagnostic routine will compare the
evaluated CRC byte with a byte contained in each respective ROM. If there
is a difference, an error indication is given.

4.

All 2048 words of high speed record memory are checked by writing and
reading to and from every bit.
If any failure is detected, an error
indication is given.

6-1

If no errors are discovered by the diagnostic routine, the following occurs:
1)

As soon as the AC POWER switch is turned on, the ERROR light at the
top of the keyboard will light. The CRT will display a white
vertical bar pattern. (If the KSOO-D is "cold" when the power is
turned on, nothing will be displayed until the CRT warms up).

2)

A pattern of grouped-together alternating black and white vertical
lines will shift slightly. By the end of this step, about 4 seconds
will have gone by since the power was turned on.

3)

The CRT will show 'walking zeros in a field of ones'. This has the·
appearance of an essentially all white display with moving dark
segments down and across the screen.

4)

After about 13 seconds from power on, the ERROR light will go off
and the STATUS display will appear on the CRT. The fact that the
STATUS display appears is an indication that power-up is complete.

If an error has occurred, an error indication will be given. The following is a
list of the error indications which can occur and the associated error
description.
ERROR INDICATION

ERROR DESCRIPTION

The ERROR light is still on
at least 20 seconds after
power is turned on.
It is not blinking.

The Microprocessor has failed
to reset and/or cannot run
properly. No operation of
the KSOO-D is possible.

6-2

ERROR INDICATION

ERROR DESCRIPTION

The ERROR light starts to blink
within about six seconds after power
is on. Pressing only the black "X"
key for at least one second turns
the ERROR light off for as long as
the key pressed.

An error has been detected in either
ROM or RAM of the microprocessor.
To determine which part of ROM or
RAM has the error, do the following
steps.

1.

Press the black "1" and black
"0" keys down one at a time.
Hold the key pressed for at
least one second. Do not press
any other key or switch. One of
these keys will turn the ERROR
light off for as long as the key
is pressed. The other key will
have no effect of the ERROR
light. If the "1" key turns the
ERROR light off, the error is in
ROM. If the "0" key turns the
ERROR light off, the error is in
RAM.

2.

Press the white keys one key at
Hold the key pressed
for at least one second. Do not
press any other key-or switch.
One of these keys will turn the
ERROR light off for as long as
the key is pressed. The other
keys will have no effect on the

a time.

ERROR light.

Note the number or

letter of the key which turns
the ERROR light off. If the
error is a ROM error, do steps 3
and 5. I f the error is a RAM
error, do steps 4 and 5.

6-3

3.

Find
the
ROM
on
the
microprocessor PC board which
has the same number or letter as
noted in step 2. (The number or
letter will be on the PC board
immediately above the ROM) .
That will be the ROM in error.

4.

The table below gives the
relationship between the number
or letter of the key which turns
off the ERROR light and the code
for the defective RAM.

ERROR DESCRIPTION
Key

RAM Code

0
1
2
3
4
5
6
7

6A (bit
6B (bit
6C (bit
6D (bit
6E (bit
6F (bit
6G (bit
6H(bit

0)
1)
2)
3)
4)
5)
6)
7)

8

4A
4B
4C
4D
4E
4F
4G
4H

0)
1) ~lost
2) Sig3) nificant
4) Byte
5)
6)
7)

9

A
B
C
D
E
F

(bit
(bit
(bit
(bit
(bit
(bit
(bit
(bit

Least
Significant
Byte

The RAM code gives the PC board
column number (either 4 or 6)
and the row letter (A through
H). The column numbers and row
letter are printed on the PC
board, not the chip.
Note: The "4H" RAM is the
first
RAM
tested.
If
it
appears to be in error, it is
likely that the problem is
really somewhere else (e.g., a
short in the address lines or
chip select lines). A check
should be made for these
other,
possible
problems
before
replacing the
RAM
chips.

5.

The operator may attempt to
bypass ROM or RAM by pressing
the CE key for at least one
second.
If the CE key is pressed, the
K500-D will skip the remaining
diagnostics and· go to the
STATUS display.
The message "POWER ON ERROR"
will be in the upper-left
corner of the screen.
Note that the K500-D may not
function properly if an error
is bypassed in this way.

6-4

ERROR INDICATION

ERROR DESCRIPTION

The ERROR light start to blink 6 to
13 seconds after power on.
A
display
similar
to figure 6.1
appears on the CRT.

An error has been detected in high
speed record memory. The display on
the
CRT
gives
the
following
information. Hold down Delay button
to stop address scrolling.

cm-1PARE
Cor-1PAF.:E
COt-1PARE
Cor-1PAF.:E
Cor-IPARE
Cor-1PARE
COt-1PARE
Cor-1PARE
Cor-1FAF.~E

Cor-1FAF.:E
COt-1PARE
CDt-1PAF~E

Cm-1PAF.:E
Cot-IPARE
COt-1PAF.:E
cm-1PAPE
COt-1PAF.~E

Cor-IPAPE
COt-1PARE
COt-1PARE
cm-1PARE
COt-1PARE
cm-1PARE
COMPARE

ERROR ADDF.~ESS: ~}'"..t"!..l
ERROR ADDRESS: [w4.':.i'
ERF.~OR ADDRE:::;S: [W--t;;lW
EF~F~OR ADDRE:;S: t-'?'i*l
ERF.:OR ADDRE:;S: [-.}-'..{-.f!
ERROR ADDRESS: ["~..!i1
ERROR ADDRE:;:;: ["~"I:'
EF.:ROR ADDF.:ESS: ["Y~-;;ri
ERROr;: ADDRESS: ["i'~"l:;l
EF.:POP ADDF.:ESS: ["~,,J,i
ERF.:OF.: ADDF.:ESS: f.,r~,:;I~l
EPF.:OP ADDPESS: t':.F'-i-;;}:1
ERPOR ADDF.:ESS: [o;,~-;;!ij
ERF.:DR ADDRE:::;S: ["~--N~l
ERROR ADDF.:E:3S: t"Y.l"l~
ERPOR ADDF.:ESS: t':.Y-Nj
ERROP ADDRESS: [..n~)
EPPOR ADDRESS: [w.,§~1
EPF.:OR ADDF.:ESS: M4~
ERROR ADDPEcc, [W~~l
ERF.:OR ADDRE;3;3: ,..
ERF.:OR ADDRESS: [*~;i1
ERROR ADDRESS: ~
ERROR ADDRESS:~

Figure 6-1.

iii!

~lROTE: ~ READ: ~
~JF.:OT E: ~ READ: ~
~lROT E:
READ:

ru

I-JPOT E:~
~lROT E: §:j
~JROT E: ~
l-lFWTE: lilli
l-lROTE: ~
l-lROT E: ~
l-lROT E: [j!J
l-JF.:OTE: ~
I-JROT E:~

READ:
READ:
READ:
READ:
PEAD:
READ:
READ:
F.:EAD:

m

1.

ADDRESS - The address within
high-speed record memory (0
through 2047) where the error
was detected °

2.

PHASE - The clock phase within
high-speed record memory (0
through 7) where the error was
detected.

3.

BIT PATTERN WRITTEN - The bit
pattern that was written to
high -speed record memory. Each
Hex character byte corresponds
to input channels 0 through 7.

4.

BIT PATTERN READ
The bit
pattern that was read back from
high-speed record memory.

~
~

(ffij
(ilil
~
~

~
~
READ:~

~-lROTE: ~

F.:EAD: ~
F.:EAD: m;=l
F.:EAD: ill!l
R.EAD: ~
F.:EAD: ~
PEAD: ~
.PEAD: ~
~lRnT~' [ii PEADo ~
l-JR;:IT §j F.:EAD: ~
l-lROT E: m; READ:!llii
I-IRaTE: ffij F.:EAD: ~
WROTE:ij READ:~

l-JROT E: ml
l-lROT E: illj
I-JROT E: fa
l-JROTE: ~
I-JROTE: [j]
l..mOTE: ~

E:

High-Speed Record-Memory
Failure

Any difference between what was
written and what was read is an
error. Up to 24 addresses will be
displayed on the CRT at anyone
time. Usually, when a particular
chip is bad, all addresses will
have the same channel bit wrong.
Refer to the Input board schematic
to locate the bad chip. I f more
than one phase is wrong, the error
is usually a shorted trace or other
PC board error.
Other kinds of
errors
can
cause
these
same
indications.
The operator may attempt to bypass
errors in high-speed record memory
by pressing the CE key for at least
1 s. The KSOO-D will go to the
STATUS display.
The message "POWER ON ERROR" will be
in the upper-left corner of the
screen.
Note that the KSOO-D may not
function properly if an error is
bypassed in this way.

6-5

Memory Error Interpretation

6.2.2

The following setup shows how to read the Record Memory errors.
to Figure 6.1

Refer

COMPARE
COMPARE
COMPARE
COMPARE
COI-IPARE
COMPARE
COMPARE
COMPARE
COMPARE
COMPARE
COMPARE
COMPARE

F3
F3
F3
F3
E3
D3
B3
73
F3
F3
F3
F3

ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR
ERROR

ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:
ADDRESS:

0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
020A
020B

WROTE:
WROTE:
WROTE:
WROTE:
WROTE:
WROTE:
WROTE:
WROTE:
WROTE:
WROTE:
WROTE:
WROTE:

FE
FD
FE
F7
EF
DF
BF
7F
FE
FD
FE
F7

READ:
READ:
READ:
READ:
READ:
READ:
READ:
READ:
READ:
READ:
READ:
READ:

CHANNELS
CHANNELS
7 6 5 432 1 0 7 6 5 4 3 2 1 0
1 1 110 1 1 1 1 1 1 100 1 1
Ch. 2 in error
Note:

Upon reading this chart,· notice Ch"annel designation 2 has 1
written and 0 read out of memory. Th is shows Ch. 2 data is
incorrect at Memory Address 020B. A pattern of all even
addresses denotes one or more of the even number phases in error
(WE 0, 2, 4, 6). A pattern of all addresses denotes one or more of
the odd number phases in error (WE 1, 3, 5, 7).

Phase location on PCB:
PHASE

COLUMN on PCB

WEO
WEI
WE2
WE3
WE4
WE5
WE6
WE7
Note:

7
4
8
3
9
2

10
1

The errors shown were a result of the "ClK DA" cable to the "0-3"
Input board being disconnected. This results in the low nibbles of
the bytes read being all the same (Hex 3). The diagnostic system
clock is generated on the "0-3" Input board. Notice that the high
nibbles of the bytes written and read are in agreement. This
means the memory on "4-7" I nput board is operating correctly. If
the least significant nibble in each address appears more than
once, one or more phases are failing.
Locate the channel where the failure to read back what was written has
occurred. Determine the phase of failure and its location in memory.
Verify inputs on the failed memory IC. See Table 6.1.

6-6

Table 6.1

Identification of Failed Record Memory IC Package Related
to the Input Channel and Clock Phase.

Channel

I

1

2

3

4

5

7C
4C
BC
3C
9C
2C
lOC

7C
4C
8C
3C
9C
2C
lOC
lC

7C
4C
BC
3C
9C
2C
lOC
lC

7C'
4C'
BC'
3C'
9C'
2C'
IOC'
lC'

7C'
4C'
BC'
3C'
9C'
2C'
lOC'
lC'

0

,

0

Phase
WEO
1
2
3
4
5

6
7
Note:

6.2.3

7C
4C
BC
3C
9C
2C
lOC
lC

Ie

7C'
4C'
BC'
3C'
9C'
2C'
lOC'
lC'

I

7

7C'
4C'
BC'
3C'
9C'
2C'
lOC'
lC'

Prime designation (') denotes other input board.

3.1 level firmware

The information in this section pertains to current models of the K500-D
containing 3. I-level firmware. (The firmware level is displayed in the
lower-right of the CRT screen 'upon power up.)
The K500-D diagnostic
routine occurs every time the power is turned on.
With the exception of the ROM and microprocessor RAM tests, the K500-D
diagnostic routines are identical to those checks performed under the 2.1
firmware; i.e., stuck key and high-speed memory tests.
Using 3. I-level firmware, all 65,536 bytes of microprocessor ROM are
checked.
A checksum is generated for each ROM when the ROM is "burnt. "
Checksum is a type of error detection method where a check word for each
ROM is created. The diagnostic routine compares the checksum for each ROM
wi th a table contained in ROMs 15 and 16.
If ther.e is an difference, the
ERROR light flashes, and an error message identifies the defective ROM by
part number, and gives the expected and actual checksum values. Refer to
Figure 6.2.

CHECKSUM ERROR:

ROM

Figure 6-2.

9#

EXPECTED:

24D6#

Checksu~Test

6-7

ACTUAL:

Failure

lC40

Using 3.1-level firmware, the microprocessor RAM is tested with a march
test. The test clears the RAM, fills it with all "O"s, and checks for all
"0" entries.
RAM is then filled with "l"s, and these entries are tested.
If the test fails, the ERROR light flashes, and a error message identifies
the defective RAM.
The error message displays "MICROPROCESOR RAM TEST FAILED:" followed by a
line of hexadecimal numbers representing the RAM IC chips.
A heavy horizontal bar below the defective RAM number identifies the defective chip.
The CRT screen may also display vertical lines or other noise.
Refer to
Figure 6.3.

Figure 6-3. Microprocessor RAM-Test Failure
To find the location of the defective chip, identified by the microprocessor RAM Test, or identify other defective RAM IC chips, refer to
Table 6-2.

6-8

Table 6-2

Powerup RAM-Test Location Map

,

DEFECT INDICATION

CHIP LOCATION

CHIP NUMBER
6A
6B
6C
6D
6E
6F
6G
6H

0
1
2

3

4
5

6
Defective-RAM identification number

7

4A
4B
4C
4D
4E
4F
4G
4H

8
9

A
B

l

6.3

C
D
E
F

Required Test Equipment

The following test equipment is required to perform the diagnostic procedure:

1)

Two pulse generators capable of <1 ns rise and fall times. A
minimum pulse width of 1 ns and output adjustable from -5 V to +5
V into 50 Q with single pulse capability (Tektronix PG502) .

2)

One Biomation glitch termination fixture.

3)

One Tektronix 7904 mainframe Oscilloscope.

4)

One Tektronix 7B92A Time Base plug-in.

5)

One Tektronix 7A19 Vertical Amplifier plug-in.

6)

One (DC to 900 MHz) Tektronix P6201 FET Probe.

7)

One Tektronix Probe tip bayonet assembly (PIN 013-0085-00).

8)

One Hewlett-Packard HP5316A Frequency Counter.

6-9

See Figure 6.22.
(or Tek 485)

Male BNC (Scope Input)
(Rin = 50 )

BNC
FEMALE
SIGNAL INPUT TO PROBE

INPUT FROr·1 PG502
OUTPUT COAX

SIGNAL GROUND

Figure 6-4.

Glitch-Termination

6-10

Fix~ure,

Schematic

6.4

Diagnostic and Troubleshooting Procedures

DIAGNOSTIC PROCEDURE
6.4.1

Equipment Set-Up

Connect the KSOO-D to AC power cord. Turn on the KSOO-D and allow a few
minutes for STATUS mode to appear.

The appearance of the STATUS mode after power- up diagnostics is
the indication that power-up is complete. If failure occurs, verify
step 6.2, diagnostic.

Note:

Connect the ten individual probes to the KSOO-D.
Display should be as in Figure 6-5.

STATUS r;l

CLOCK 4""'¥Fid§#U

t10DE lllNlel1
SEQUENCE
IPOLAR I T't
ENABLE

FILTER

~

DELA'i

V/DIV

~

mm

11m

T C
Q K

(A) 0 IiII

~

;

IIIU

;

TRIGGER (C) 0

~

~

~I~.

~

[rHIIMt@

OFFSET

r:nv

THRESHOLD
INPUT MODE

SAt-1PLE

SEARCH
ARt1 t-10DE
r;1QilIJ
GPIB 09=--, LOC, NPR
READY
VAR A ~v

Figure 6-5.
Note:

VAR B

~'...'

[2.1]

Normal Status-Display Screen

The Power Up Status mode condition can be selected for either
TTL or ECl Threshold. The Clock can be selected for INT or
EXT
via the options switch on the Data Display board. The
switches are factory set so that all channels power up with ECl
Th resholds and I nternal Clock.
Depress 1Manual Arml IManual Enabld, IManual Triggerl. Verify that lower
left-hand corner of the display changes; READY ~ ENAB? ~ TRIG? ~ BUSY ~
READY.
Depress lTIMINGI, verify eight traces on the screen. Data should be all
logic high levels.
Depress ISTATUSI, trHRESHOLDI ,'TTL) (10 times), 'ENTER), (Auto Ard.

&._"
v

~~

6.4.2

Combinational Trigger

Set an external pulse generator for 1 MHz square wave output at +3 V
level (0 VDC baseline). Connect the generator output to the channel '0'
probe input.
Press IAuto AriIj, tAuto Enabl~, ISTATU~, ITRIGGERI , IAuto Ariij. Verify that
lower left-hand corner of the disp ay changes; READY ~ BUSY rapidly.
Press ttIMINGI. Verify data on channel '0' of screen. Trigger point
should show up on rising edge of waveform at center of screen.
Press ISTATUSI, IENABLFJ ,
Press ttRIGGERJ,

'lXi'

'lXi'

(6 times),

Move generator to channel
rapidly changes.

'IIi', 'i&l' ,.IENTERI.
'iD' , 'W' ,'ENTERI , tAuto Arnt

(6 times),

'1' probe input. Verify display READY

~ BUSY

Repeat for channels 2 through 7. ChangeJENABLEI andlIRIGGERI to 'Da' for
the individual channel under test. Return channels not under test to
'l&;'. Verify display READY ~ BUSY rapidly changes.
Perform same test starting with channel '0', but changeITRIGGEi bit to
"0". Verify results.
Connect external pulse generator to channel' 0 I with all ENABLES set to
"X" . Set channel '0' TRIGGER to "1", all other channels to "X". Press
'AUTO ENABLEJ and IAUTO ARM). Verify READY ~ BUSY.
Set external pulse generator to 1 MHz square wave output at ECL levels
(-0.8 V to -2.0 V).
Press ISTATUS I , ITHRESHOLDI , fECL1 (8 times), liRIGGERI,
rENTERI. Connect generator to channel' 0' probe input.

I!J

(2 times),

Press IAUTO ARMi, ITIMING), verify data on channel '0' of display. Remove
generator from channel 0'. Repeat test for channels 1 through 7.
6.4.3

Threshold Checks

, I±l, [fJ, ., [QJ, [Q],

IENTERJ,

Set external generator, for 1 MHz square waves at +5 V level (0 VDC
baseline) . Connect generator to channel '0'. Press lTIMMING', verify
data on screen.
Repeat tests for channels 1-7.
verify results.
6.4.4

Repeat test using

lID

in place of

mand

Internal Clock

Press lSTATUSI, ITHRESHOLij , ITTLI (8 times), JENTER', IAuto Ar~.
Set external generator to rates in Table 6.2. Verify TIMING diagram.
Specify clock as in Table 6.2. Rearm (Auto Arm) is necessary after
clock change.
Data may be input to any channel. Set combinational trigger for channel
under test to a "1", or "0"; and set all unused channels to "X".

6-12

Table 6-3.
Gen. Frequency

(25 KHz)
(2.5 KHz)
(250Hz)
(25 Hz)
(2.5 Hz)
.c0.25 Hz)
(0.025 Hz)
6.4.5

Internal-Clock Tests

Data Rate

Clock Rate

(Generator Period)
4 ps (TTL sq. wave)
4 ps (TTL sq.wave)
4 ps (TTL sq. wave)
4 ps (TTL sq.wave)
40 ps (TTL sq.wave)
40 ps (TTL sq.wave)
40 ps (TTL sq.wave)
400 ps (TTL sq.wave)
400 ps (TTL sq.wave)
400 ps (TTL sq.wave)
4 ms (TTL sq.wave)
4 ms (TTL sq.wave)
4 ms (TTL sq.wave)
40 ms (TTL sq.wave)
40 ms (TTL sq.wave)
40 ms (TTL sq.wave)
400 ms (TTL sq. wave)
400 ms (TTL sq.wave)
400 ms (TTL sq.wave)
4 s (TTL sq.wave)
4 s (TTL sq.wave)
4 s (TTL sq.wave)
40 s (TTL sq.wave)

Display Cycles

2 ns
5 ns

10
20
50
100
200
500
1
2
5

10
20
50
100
200
500
1
2

5
10
20

50

ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ms
ms
ms
ms
ms
ms

1

2.5
5

10
2.5
5

10
2.5
5

10
2.5
5

10
2.5
5

10
2.5
5

10
2.5
5
10

2.5

Filter Test

Return all settings as in Figure 6-5.
Press IFILTERI, IAuto Arij. Set external pulse generator PGS02 output to
ECL levels (900 mV swing about -1.3 V ECL Threshold). Set pulse width
to 4 ns and 20 ns period. Connect generator output to channel O. Verify
TRIG? Increase pulse width to 6 ns. Verify that unit triggers.
Minimum pulse width required for filtered trigger to occur is 6 ns at 2
ns internal sample clock rate.
6.4.6

Trigger-Delay rests

Return all settings as shown in Figure 6-5.
Press IAUTO ENABLEI switch, IDELAY) ,

ill, (]), [Q], [Q], IENTERI.

Set external pulse generator (PGS02) output to ECL levels, 1 ps pulse
width, and single pulse capability. Connect generator output to channel

o.

Press IAuto Arml Switch and manually pulse the generator. Press ITIMINGI.
Display should show pulse at 399 (TRIGGER is T marker line).
Press ISTATUSI, 'DELAY', [8], ~, (Q], IENTER I , (Auto Arml. Manually pulse
the generator, press (TIMINci. Display should show pulse at 1199
(TRIGGER=T) .
Press ISTATUSI, !DELAY), [?;J, 101, [Q), tENTERI, IAuto ArlIt Manually pulse
the generator, press ITIMINGI. Display should show pulse at 1599
(TRIGGER=T) .

6-13

Press ISTATUSI, JDELAYI ~,
the generator, press ~.
(TRIGGER=T).
Press IsTATuSl, IDELAYJ,
the generator, press
(TRIGGER=T).

rr

miNG.

~,

~lanually pulse
Display should show pulse at 1799

[Q], IENTERJ, IAuto Arllj.

[Q], IENTERJ, IAuto Ar[ij. Manually pulse
Display should show pulse at 1899

Return all settings as shown in Figure 6-5. Pulse generator should be
set for 1 ps pulse width.
'DELAYl ,

[ID, IENTERt· 'DELAY),

rn,

IENTERI,

Pulse generator 5 times. Verify that edge (positive-going) is at the
center of the screen (Trigger at 999).
Press mELAYi, lID, IENTERI , IAuto Arlit Pulse the generator 9 times.
Verify that the edge (positive-going) is at the center of the screen
(Trigger at 999).
Note:

500 MHz operation is not specified in EVENTS DELAY.

6.4.7

Analog Tests

First compensate the X10, 10 MQ Analog probe to the K500-D by applying a
1 MHz, 2 V p-p square wave centered about ground (zero DC offset) to the
probe tip at the output of the pulse generator. Set K500-D for Analog
record mode, Analog trigger, clock = 100 ns, offset = 0 volts, 0.5
volt/div., Autoarm, Timing, X20, specify cursor to 990. Adjust probe
compensation capacitor at probe body with adjustment tool so that the
square waves displayed have clean edges with no overshoot or rounding of
corners.
Now apply a 10 MHz, 2 V p-p square wave centered about ground (zero DC
offset). Change to clock = 10 ns, 0.5 V/div., Autoarm, Timing, X20,
specify cursor to 990. Verify that tri,~er marker is at ,fliNt it~Hf
swrare waves displayed. Press IsfATOSI, I IGGERI, (CURSOR +),
L,
,
IA OARtt, ITIMIN~. Verify false triggering by observing falling edge at
trigger marker.
6.4.8

Display Functions

Power down the K500-D, then turn it on.

Allow 5 minutes for warm-up.

Press ITIMING!. Verify data as in Figure 6-6.
Press ~.

Verify data as in Figure 6-7.

Press

m.

Verify data as in Figure 6-8.

Press

rx!Ql. Verify data as in Figure

6-14

6-9.

DIGITAL A Xl

CLOCK 2

nSEC

DELAY

1000

CLOCKS

T

~

7

6
5

4

LnJ1J1J

~10

n10

l

1
I,Jruu1fffulli~lUlJUlru1lli1fil11J1mrlflflf~l1uUlfU1Ju~Tulflf{~nuulffHlJulJfulJlfUl10

UUlJUmnmUmnnmmhmUUUUlHJlJUUUlftr
.

••••••••••••••••••••••••• , •••• , •••• , •••• , ••••••••• ;1 •.••• 1 ••••••••• ! • • • • • • • • • • . • . • ' . • . . 1 •••.•.••••••

o

1000

!I

1959C

o
READY

T: 999

Figure 6-6.

DIGITAL A X10
7

C(

0) R(1959) R-C

Display-Functions Test, Timing

CLOCK 2

nSEC

DELAY

I

J

61

=+1959(3.918~S)

:

1000 CLOCKS
Tot
0

:0L0

:

JJ-..n~n~n~n~n~1l0
I
iii I
4

,1....•.... , ....•....•....•.... , ....•.... , ....•.... , .. ··I····I····'····I····I····I····I····.····!··

o

98

195 C

3

2

o
READY

T: 999

Figure 6-7.

C(

0) R(1959) R-C

=+1959(3.918~S)

Display-Functions Test, X 10

6-15

DIGITAL A X20

CLOCK 2

nSEC

DELAY

1000 CLOCKS
T~

7

I
J

0

6

J

0

5j

r0

4

J!.....
I

I

I

I

I

o

Le

I

I •••• I ..... I •••• I •••• I •••• I ..... I •••• I •••• f •••• I ....... I ....... I ....... I ........ I ...

~ • I ....... I •••• I ...... ! . . . . . . ..

49

97

C

:j
LflfU1JlllfUlJlJ0

J
oJ
1

uuuuuUlnnruuuUUU1Jl0

READY

T:

999

Figure 6-8.

DIGITAL A X50

C(

0) R(1959) R-C

=+1959(3.918~S)

Display-Functions Test, X 20

CLOCK 2

n8EC

DELAY

1000

CLOCKS
T~

7

I

0

6

0

5

I

4

READY

T: 999

Figure 6-9.

C(

0) R(1959) R-C

I

0

I

0

=+1959(3.918~S)

Display-Functions Test, X 50

Press (SPECIFYI , E1 (CURSOR), ill, [Q], (QJ, [Q], tENTERI. Verify that
the vertical line at the left-hand edge of the display is "T".

G

ill,

rn,

ill,

Press (SPEC I FYI ,
(REFERENCE),
IQ],
IENTERI. Verify that
the vertical line about 1/2 inch to the right of the center of the
display is "1024".
Observe the characters at the bottom of the display.
as follows:
READY T:

1000 C <1000> R <1024> R-C=+24 <48 ns>

6-16

They should read

rn,

EJ

OJ,

Press ISPECIFYl,
(REFERENCE),
[QJ,
[Q], !ENTERl. Verify that
the vertical line about 3/4 inch to the left of the center of the
display is "1010".

Observe the characters at the bottom of the display.

They should read

as follows:
READY T:

1000 C <1000> R <1010>

Press lDATAI, JBINI.

Verify that the display is as shown in Figure 6-10.

DI 131 TAL A

B1 N

c 1e.e.e.

1 1 10

[,,:3EC
DELA'r'
CLDCi< 2
f';{;;:
....
-t,;l e@i..l
1020 1 1 1 1
10e.0
100 1
102 1 1 1 1 1
112122 1 1 1 1
10 10
10.23 1 1 1 1
1121 1 1
1 1 0121
1024 00121121
1 10 1
1025 0000
122E. 0002
1 1, '1 0
,,,.-,..., 000121
i
11
1
102S 000121
12000
.;.
1 02'7' 0000
00 10
i 03121 0020
00 1 1
103 1 0200
0 100
1it:..::~ e0~0
0 10 1
1233 L='i,.''L.:t:,.;
12 1 10
10:34 0000
10:35 ee.00
12 1 1 1
10:36 0002
1000
112137 0200
100 1
103:::: 0000
10 10
10:3';:- 0000
10 1 1

102 1 1 1 1\3
112102 1 1 1 0

101213 1 1 1121
11211214 1 1 1121
1005 1 1 10
1 006
1 1 1e.
101217 1 1 10
100:::: 1 1 1 1
100';:- 1 1 1 1
P 10 10 1 1 1 1
1121 1 1 1 1 1 1
10 12 1 1 1 1
10 13 1 1 1 1
10 14 1 .;. 1 1
10 15 1 1 1 1
10 lE- 1 1 1 1
10 17 1 1 1 1
10 i:::: 1 1 1 1
10 19 1 1 1 1

.

.

T:

Figure 6-10.

~,,:::,,,,

.

:~,-'::"'1r.

i!..;ii:;~:

.

F:.EAD'T'

R-C=+10 <20 ns>

:~!~:~,,.

1:;:1';:11:;:'

c< 1000> r<:< 10 10>

ft:-C =

102e. CLOCI<:3
1 1e.e.,
1 10 ...
1 1 10
1 1 11
001210,
01212
02 10
02
,.,iL; < 1

.

. .0e~1
e i 1121
."

~,

.

0 11 1
220
1;,.;.:....:' ..
1121 ,1 ~
1.;r: <...
1 100
1 1121 1
:"'"l,""l

."

1i

...
...

~;

111i
+ 10 .::

20 nS)

Display-Functions Test, Binary Data

6-17

Verify that the display is as shown in Figure 6-11.

Press IOCTALI.

DIGITAL A OCTAL CLOCV ;::
~

112,20 :374
1021 :::::75
12122 :::::76
l"!.'L'~' 377
1024 121210
1025 001
1026 1202
1027 12103

C 110100 3':,0

11001 :;:51
11004 :::;:54

110215
1006

DELA'r'

nSEC

~

f-.iFJ

1040 1212121
1041 :"'1:.-,.-,
221
1042 It.!LL
104:3 e23
1044 024
112145
1046

READ't'

Press [HEX).

:-,

,:!";,,-+:-,

1~49

006
01217
010

031

:36 . .
370
371
:::::72
373

112130
12031
1032
1033
.034
1035
1036
1037
1038
1e!:;:'?

T: 999

C(10ee> R(101e) F:-C =

Figure 6-11.

~?45

10~,2

246

12-=,3
1264

1065
10~6

eS3
l"!.'C:
106:::' 034
106 055
'\! :"l: ..-

o(;~.-:

1

100'?
F.:101e
1'2111
1012
11613
11614
11615
1'2116
1017
1018
101'?

112160 1?44
1061

1052

1051
1052 034
1053
1054 036

oi

1..

,z,:,·-,
i{.; l ..:..

:"'J:.-,!:"

011
01'-'

It.,,~,,_,

01:3
014
015
016
12117

0S7
\?f,0
261
.-"
~

- .-.

1055

1075

105~,

lr'6 0EA

1057 2141
105:::: 042
105'7' 12143

1077 065

11217:::: e~·6
12179 06;
+le(

Display-Functions Test, Octal Data

Verify that the data is as shown in Figure 6-12.
[II

GI TAL A

HEX

C 102121
lee 1
1002
112103
10214
1005
lee6
101217
1120:3

lee'?

F: 1121 10
1121 1 1
112112
112113
1014
1015
1016
1017
10 1'=''-'
112119
READ',..

Figure 6-12.

E'::'
E'?
EA
EB
EC
ED
EE
EF
Fe
Fl
F2
F3
F4
F5
FE.
F"7"
F'=''-'
F';;'
FA
FE:
',J

T: 99'?

CLeel:: 2
rl~-=-t!

11212121
1021
112122
1023
112124
112125
1026
1227
1212:3
11212';;'
112130
112131
1032
HD3

Fe
FD
FE
FF
00
101
102
103
104
1215
06
107

1~:34

0A
eB
ec
e,D
0E
eF

1035
1036
112137
10:;:::::
1121:::::';;'

DELA',;

n.:3EC

~~ll'.l

123
0:;'

1040
104 1
112142
11214:::::
112144
112145
112146
1047
104::::
104';;'
105121
11215 1
1052
of :'":itt::'.-,

J.

~'-_;.;I

10S4
1055
105E.
le57
105::::
11059

1121
11

12
13
14
15
If.
17
1::::
1";;:'

1A
1E
0(

,-.

.i,.'_-

lD
lE

1F
2121
21
.-:--:.

2:3

C( 1eee} R( 11211121> R-C

1222 CLOCKS

1060 24
1ICo::, 1 .-.t:'
"'::"-'
1e~,2

..:::,:.

27
100::,4 2E
le~,3

1065 2"7-

2A

10~E.
10~7

..:::t:.

le6;::

2C

10'::';;' 2D

1 !:>~'::OO
~: " 1(;
..:..t:..

107 1
1e72
1073
1074
le75

2F

-to"''''':
li!..',,· ..'

:35

.

:~:0

:::'2

33
11676 :34

1107:::: ::::s
107';;- 37
+ 10(

2en::;)

Display-Functions Test, Hexidecimal Data

6-18

Press

5PCLI .

Verify that the data is as shown in Figure 6-13.

DI GITAL A SPCL
C1000 E

110101
11002
11003
110104
110105
11006
110107
110108
1100';;R101e.
1011
1012
101:3
1014
1015
1016
1017
1018
101'?

READV

E
E
E
E
E
E
E
F
F
F
F
F
F
F
F
F
F
F
F

~

t"•• SEC

j¢NI~)

DELA'r'

1020 F

11021
1022
11023
11024
11025
11026
1027
1028
102'7'
1030
11031
1032
1033
10:34
1035
103E,
1037
10:38
1039

9
A

B

C
D

E
F
10
1
2
:3

4
5
6
7

:3

9
A
B

T: 999

Figure 6-13.
Press ISEARCH).

8

CLOCI< 2

F
F
F
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0

1000 CLOCKS

C
D

E
F
10
1
2
.-.
.,;..
4
e:-

._'

6
7

:::
' 7'

A
B

C
D

E
F

C(1000) R(1010) R-C =

+le.(

20t\S)

Display-Functions Test, Special Data

Verify that the data is as shown in Figure 6-14.

DIGITAL A SPCL

CLOCK 2

nSEC

ilHl FfBl

DELAV

1000 CLOCKS

Cle.00 E 8
1020 ~ C
1021*F D
1001*E 9
1022 F E
1002 E A
le.03*E B
1023*F F
11024 0 10
1004 E C
le.e.5*E D
11025*0 1
110106 E E
1026 0 2
le.07*E F
1027*0 3
10108 F 0
1028 0 4
1009*F 1
11029*10 5
Rle.10 F 2
110310 10 6
le.ll*F 3
1031*0 7
11012 F 4
11032 0 8
1033*0 9
1013*F 5
1034 10 A
1014 F 6
1015*F 7
1035*0 B
1016 F 8
1036 10 C
1037*0 D
1017*F 9
1018 F A
1038 0 E
1019*F B
1039*0 F
EVENTS= 1000
FIRST=
1
NEXT= 1001
LAST= 1999
READV
T: 999 C(1000) R(1010) R-C = +10(
20t\S)

Figure 6-14.

Display-Functions Test, Search Data

Press [!) (CURSOR down).
Display should update (address change).
Single step 6 (CURSOR); verify single increments of Address. Return
cursor to Address 1000 by ~ressing E3 (CURSOR up). Return cursor to
Address 1000 by depressing l!:J (CURSOR up).

6-19

mm,

Press
'SPACEJ (3 times), IENTERI,
is as shown in Figure 6-15.
DIGITAL A HEX

~SEC

CLOCK 2

m

,HEX'.

~

Verify that the display

DELAY

1000 CLOCKS

1060 04
C1000 08
1020 lC
1040 10
1061*05
1001*09
1021*lD
1041*11
1062 06
1002 0A
1022 IE
1042 12
1063*07
1003*0B
1023*IF
1043*13
1064 08
1004 0C
1024 00
1044 14
1065*0'?
1005*0D
1025*01
1045*15
1066 0A
1006 0E
1026 02
1046 16
1007*0F
1027*03
1047*17 .
1067*0B
1068 0C
1008 10
1028 04
1048 18
106'?*0D
1009*11
1029*05
1049*19
1070 0E
R1010 12
1030 06
1050 lA
1071*0F
1011*13
1031*07
1051*IB
1072 10
1012 14
1032 08
1052 lC
1073* 11
1013*15
1033*09
1053*lD
1074 12
1014 16
1034 0A
1054 IE
1075~d3
1015*17
1035*0B
1055*IF
1076 14
1016 18
1036 0C
1056 00
1077*15
1017*19
1037*0D
1057*01
1078 16
1038 0E
1058 02
1018 lA
107';:'* 17
1019*IB
1039*0F
1059*03
LAST= 1999
EVENTS= 1000
FIRST=
1
NEXT= 1001
20nS)
READY
T: 999 C(1000) R(1010) R-C = +10(

Figure 6-15.
Press ~,

Display-Functions Test, Sequence Hexidecimal Data

rnJ,

ISPACEI, ~, ISPACEJ,

IENIERI. Verify display as in Figure 6-16.
DIGITAL A

HEX

CLOCK 2

1¢;=-I1-:'1

nSEC

~

m,
DELAY

lID, Ill, lID,

~, ~,

1000 CLOCKS

1060 42
C1000 8E
1020 CF
1040 01
1061*52
1001*9E
1021*DF
1041*11
10~,2 62
1002 AE
1022 EF
1042 21
106:3*72
1003*BE
1023*FF
1043*31
1064 B2
1024 00
1044 41
1004 CE
1065*';:'2
1005*DE
1025*10
1045*51
1006 EE
1026 20
1046 61
10S6 A2
le67*E~2
1007*FE
1027*30
1047*71
1008 0F
1028 40
1048 81
10SE: (2
10S';:'*D2
1009*IF
1029*50
1049*91
1070 E2
R1010 2F
1030 60
1050 Al
1011*3F
1031*70
1051*Bl
1071*F2
1012 4F
1032 80
1052 Cl
1072 03
1013*5F
1033*90
1053*Dl
1073*13
1014 6F
1034 A0
1054 El
1074 23
1015*7F
1035*B0
1055*fl
1075*33
1016 8F
1036 C0
1056 02
1076 43
1017*9F
1037*D0
1057*12
1077*53
1018 AF
1038 E0
1058 22
1078 63
107'7'*7:3
1019*BF
1039*F0
1059*32
EVENTS= 1000
FIRST=
1
NEXT= 1001
LAST= 1'?99
READY
T: 999 C(1000) R(1010) R-C = +10(
20nS)

Figure 6-16.

Display-Functions Test, Sequence Hexidecimal Data

6-20

IXill

Press ITIMINGI ,
6-17.

Verify that the display is as shown in Figure

X50

CLOCK 2

nSEC

DELAY

1000 CLOCKS

o

I

I

;l,------Jnl---...L---7

e

EVENTS= 1000
FIRST=
1
NEXT= 1001
LAST= 1999
READY
T: 999 C(1000) R(1010) R-C = +10(
20nS)

Figure 6-17.

Display-Functions Test, X 50 Timing

rn,

Press mEQl
Ii) , [IJ, lQJ, (SPACEI (6 times), tENTERI.
as in Figure 6-18.
DIGITAL A X50

CLOCK 2

nSEC

DELAY

Verify display

1000 CLOCKS

toT

j-----,

3

2

o

I

1000
FIRST=
1
NEXT= 1001
LAST= 1999
T: 999 C(1000) R(1010) R-C = +10(
20nS)

Figure 6-18.

Display-Functions Test, Sequence Timing

Reset the KSOO-D by using the rear panel reset switch. Status mode
should appear as in Figure 6-5, after completion of power-up
diagnostics.

6-21

Press IANALOGI , 'TIMING! , ~ , IManual Ariij, ,Manual Triggerl.
display as in Figure 6-19.

DIGITAL A X20

CLOCK 2

nSEC

DELAY

1000 CLOCKS
T-+

:j

:

~

5J
4

Verify

L0

J

.\ ... ,.......... ,.... , .... , ....., .... ,.... ,....•.... ,····'····1····'····,····.····,· . ··'····1····'··
o
49
97 C

-r---

+ 0- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

l- -Jt?----A ----lilt ---. -/r!1. ----/':1
-L-,--J--j-- --- !--L- j -- --I-J--I--

-}!::::b::::: :_:::::b:::::v:::::v::::: ,
READY

Figure 6-19.

T: 999

C(

0) R(1959) R-C

=+1959(3.918~S)

Display-Functions Test, Analog X 20 Timing

Reset the K500-D. Status mode should appear.
Verify display as in Figure 6-20.

mm.

DIGITAL A Xl

CLOCK 2

r:§

T

nSEC

Press \TI~nNGI,

DELAY

ISCROLLI

1000 CLOCKS

.................. I ........ , ........ I ........ I ........ I ....... I ........ I ........ I ...... '~I ....... I ........ I ........ I ........ I ........ I ........ , ........ , ........ I ........ I ...

o

1000

:

. READY

T: 999

Figure 6-20.
6.4.9

C(

1959C

.

0) R(1959) R-C

=+1959<3.918~S)

Display-Functions Test, Scroll Timing

Auto-Compare Operation

The Auto Compare feature for most K500-D's is accessible through the
keyboard. Earlier K500-D's have the Auto Compare feature accessible
only through the GPIB interface. Refer to section 3.2.5.5 on Memory
Accessing. Keystroke Record Keycodes may be used to access the 'B'
memory and allow it to be compared with the' A' memory. In auto-compare
mode, the A and B memories may be compared automatically for either an
A;B or A=B condition.
6-22

6.4.10

Input Performance (Glitch Capture)

I!J

Return all setttn,s as in Figure 6-5. Press (TRIGGERI
(2 times),
lENTER] , ITIMING', X5, IAuto Arij. Set PG502 pulse generator for output as
in Figure 6-21. Use special Glitch-termination fixture. Do not back
terminate PG502 with 50 Q. Use 50 Q scope input amplifier plug~in
(7A19). Connect a BNC cable from KSOO-D Analog Input BNC'connector at
front panel to (+) trig/duration input of PG502 pulse generator. This
provides a better ground path.
Verify individual Input channel
performance.

FREQUENCY = 10 MHZ
PULSE WIDTH = 3ns at Vth

-1.000V
-1. 3y' J

-0.800V

Y.!~L -f--------\ -------------------------\----------J------:.!.:.

3
V

-1.600V
-1.800V
+ GOING Eel

Figure 6-21.

- GOING ECl

Input-Performance Test, EeL 10 MHz

I~)no data dropouts.

IfTml .

Allow to run a few minutes. Press
(2· times) ~ENTERI, JTHRESHOLDI,
(8 times), E
,
, ~ , IAuto A IDI. Input data as in Figure 6-22.
Verify
individual channel performance.
GG

rr:m

,1Il

FREQUENCY = 10 MHZ
PULSE WIDTH = 3ns at Vth

+1.700V
+1. 40y'

+1.900V

_lY.!~L --t--------\------------------------- -~----------/-------::::::v

+0.900V
+ GOING TTL
Figure 6-22.
Verify no data dropouts.

- GOING TTL
Input-Performance Test, TTL 10 MHz
Allow to run a few minutes.
6-23

~. m
nS~i~ JINP~
trn;:'
r
u
.
me2
IE
:HR1~i, =--.
data as in Figure 6-23. Verify individual Input channel performance.
Press ISTA¥t!~

(5
times).

fENTER! •

•

LATCH (8 times).
uta r . Input

FREQUENCY = 5 MHZ
PULSE WIDTH = 2ns at Vth

-l.OOOV

-O.800V

-1'30Y-!Y!~2--f----------~---------------------~-----------J-------:!;~QV

-1.800V

.

+

GOING ECl

-1.600V

- GOING ECl

Figure 6-23.
Verify no data dropouts.

Input-Performance Test, EeL 5 MHz

Allow to run a few minutes.

Press IstATUsl, 'TRIGGERI, III (2 times), IENTERI, 'TIMINGf, W ,~
Input data as in Figure 6-24. Verify individual Input channel
performance.

~

FREQUENCY = 5 MHZ
PULSE WIDTH = 2ns at Vth

+1.700V

I_ _ _ _ _ \_ _ _ _ _ _ _ _ _ _ _ _

+1.4~~_i~~~1 __

~

+0. 900V____-...

\

I

----------j--------~~~~::v

.

+ GOING TTL

- GOING TTL

Figure 6-24.
Verify no data dropouts.

Input-Performance Test, TTL 5 MHz

Allow to run a few minutes.

6-24

+1.900V

6.4.11

Qualifier Tests

Return all settings as in Figure 6-5.
Connect two hybrid probes to a PG502 pulse generator output. Adjust
pulse generator output for 10 MHz ECL square waves. Plug in one probe
into the the TQ input. Plug in the other probe into channel 0 input
connector. Press ITRIGGERIIXXXX XXX»,
(TQ =' l' ) , IAUTO ARM), ITIMINGL
X10. Verify that square waves are displayed on channel o. Rising edge
of square waves displayed should line up with the trigger marker line
within ±4 clocks. Return all settings as in Figure 6-5 ~

rn

6.4.12

Self-Test mode

Refer to Self Test description for a full explanation of self test.
Figures 6-25 and 6-26 show the self test mode format and possible
assignments of self test parameters, respectively.

STATUS

CLOCK

r:1

~=

__@;;;.o.;;;o:Co;,o.

FILTER 00ii

t10DE '1Imtl!l.

SEQUENCE
rlt4t1
IPOLARITY ~

~fll~.
~

(A) U

~

~

TRIGGER (C) 0

~

~

ENABLE

THRESHOLD
INPUT t-l0DE

V/DIV

~

T C SELF TEST MODE
G! K

FI RST TE::H 1i'"1'"1
LAST TEST
~l~
TE::n EN
~
LOOP EN lij:lilU:l.
~ §"

SAt-1PLE

STATUS
TEST/CH

RESET
NA

le0

LIt-lI T+0. 00±. 100')

F.:ESUL T
+ 0.
LOOPS DONE

SEARCH
ARM MODE
~UI~
GPIB 09=--1 LOC} NPR
READY
VAR A CI"l~]\J

Figure 6-25.

OFFSET 1:1]'.•.'

VAR B

00',/

~V

Self-Test, Status Display Screen

6=25

PARAMETER
CR~J
LIN
NAME
NO.

5
6 first test
7 last test
8 test EN
9 loop EN
10
11 Status
Test
12 1 channel
Limit
13 Delay, or
.Subtest
14 Result
15 Loops Done

FIELD
MAX. POSSIBLE
NO. OF ASSIGNMENTS
CHAR.

Blank
000 to 800 } can be changed
via keyboard
000 to 999
auto/manual when status is
IInot testing"
auto/manual
6
Blank
Reset
Testing
Passed
Fa il ed
000 to 600 I'
3
to 7
2{ a
TQ or CK
-·--±·--V,
Continually
-±·----S
~changing when
5
a to 65536 STATUS is
7
- E- T"TESTING II
--.--V,
-.---.us,
---.-ns,
a to 99999
4
a to 9999

3
3
6

7{

9{

7{

Figure 6-26.
6.4.13

REMARKS

-~

Self-Test, Summary

KSOO-D Self-Test Description

This mode is entered by pressing the "Self Test" key. The Self Test
status display will appear on the CRT, which consists of a "w" status
display with the following display box added.
FIRST TEST
LAST TEST
TEST EN
LOOP EN

100
AUTO
MANUAL

STATUS
TEST/CH
LIMIT
RESULT
LOOPS

RESET
100 NA
0.00
0.00
0

999

Testing is initiated by pressing the 'START' switch. While testing is
in progress, the cursor will appear to the right of the words "SELF TEST
MODE". All tests from 100 to 800 will be performed in sequence. If a
test fails, testing will stop, the status field will display 'FAILED'
and the error LED will slowly flash. The LED can be turned off by
pressing' CE I •

n

For troubleshootin or running special tests on the KSOO-D, the values
for "FIRST TEST", LAST TEST", "TEST EN", and "LOOP EN" may be changed.
When not testing, the cursor will normally appear under the "FIRST TEST"
field. The cursor or reference keys can be used to move the cursor to
the other fields. "FIRST TEST" and "LAST TEST" are changed by keying
6-26

in new numbers and pressing 'ENTER', while "TEST EN" and "LOOP EN" are
changed with the enable switch.
Whenever "FIRST TEST" is changed, testinfi will begin with the new value
entered. Testing will also begin with FIRST TEST ii if the status is
reset, or if testing had been stopped because "LAST TEST" had been
reached. At any other time, however, testing will resume from the test
number at which it had stopped. The status can be changed to "RESET" by
pressing 'CE' in the absence of an error condition.
The "LAST TEST" field simply indicates the test at which testing is to
stop. For tracing signals with an oscilloscope, this field can be set
to "777". When set to this number, a single test is performed
repeatedly as fast as possible, so that a repetitive signal will be
produced. Test 800 cannot be run in this mode. If an error is made in
keying in either "FIRST TEST" or "LAST TEST", the 'CE' key can be used
to restore the previous value 'to this field, if the 'ENTER' key has not
yet been pressed.
The "TEST EN" field can be set to "AUTO" or "~1ANUAL". When "MANUAL",
only one pass/fail test will be performed each time that start key is
pressed. If the start key is held down, the tests will be stepped, at a
rate of about four tests per second. This is useful for getting to the
exact test, channel number and subtest number desired for using the
"777" feature.
The "LOOP EN" field can be set to "AtJTO" or "MMTUAL".

When "AUTO",
testin does not stop when the last test is reached. Instead, the
"LOOPS ft number is incremented and testing starts over from "FIRST TEST" .
As always, testing stops if a test is failed. Stopping and starting
will not reset the Loop Counter. To clear the Loop Counter, reset self
test by pressing 'CE'.
Not all tests performed result in a passed or failed condition. Tests
with numbers ending in '0' or '00' generally serve to set up the KSOO-D
for the tests which follow. These tests do not stop testing, even when
test enable is "MANUAL", so the user need not be concerned about them.
Self Test will automatically insert these tests into the test sequence
whenever necessary.
The hundreds digit of a test number determines the quantity that is
being tested. This in turn determines the format of the expected and
result display. When Self Test is first entered, the expected value
field is labelled "LIMIT", and displays an expected voltage and
tolerance. When different types of tests are performed, both the label
and the data format change to match the tested format is similar to that
of the expected value field.

6-27

Quantity Tested

Expected-Value Field Display

100

VOLTAGE

LIMIT

200
300

DELAY
ENABLE & TRIGGER

DELAY
SUBTEST

400

TIME BASE

LIMIT

500

SMfPLE/LATCH

SUBTEST

600
700

GPIB INTERFACE
ANALOG BOARD

EXPECT
LEVEL

800

TRACE LOCATION

SUBTEST

Test Series




E
T


E
T


«ADC Gray Code»
E
T

The actual hardware test performed is determined by three numbers: The
test number , the channel number and the subtest number. As shown
above, subtest number is only displayed for 300, 500, and 800 series
test.
The channel number is displayed to the right of the test number. Tests
that are not channel-oriented in nature display 'NA' in the channel
number field.
Two tests have been added for bringing up the ADC on the Threshold/GPIB
board. These tests are not part of the normal Self Test sequence.
Test 50 - Analog Ground Test. This test repeatedly outputs the ADC
value for analog ground until the 'STOP' key is pressed. This
is to be used when bringing up Threshold/GPIB boards for
adjusting the ADC offset. It is properly adjusted when the
voltage reads 0.00 V. When testing is stopped, the comparison
DAC is set to the code for 0 volts.
Test 60 - Ten Volt Reference Test. This repeatedly outputs the ADC
value for the ten volt reference until the 'STOP' key is
pressed. This is to be used when bringing up Threshold/GPIB
boards for adjusting the ADC gain. This is properly adjusted
when 10. OV is read out. When testing is stopped, the
comparison DAC is set ot the code which should be 10.00V.
100 Series Tests - Voltage Measurements

The voltage to be tested is selected by CMOS Multiplexers on the
Threshold/GPIB board. The selected voltage goes into a comparitor,
where it is compared with the output of a DAC. To measure a voltage, the
software first sets the multiplexers to the desired test point. Then it
turns on the DAC bits, one by one, from most significant to least. If
turning on any bit causes the output of the comparitor to change, that
bit is turned off again. When "all bits have been done, the code on the
DAC is proportional to the voltage at the test point. Since the range
of the DAC is ±10.24 Volts, voltages greater that this are divided by
two prior to entering the multiplexers.
When testing is stopped, the multiplexers and the DAC are left at the
last value written to them, to make it easier to troubleshoot this
circuit.
The value obtained for Analog Ground will be subtracted from all other
values read, to compensate for offset. The value obtained for +lO.OV
6-28

(if within tolerance)
misadjustment.

will

be used to compensate for minor gain

All voltage measurements are performed four times, each of which is a
full pass or fail subtest. With test ENABLE=MANUAL, testing will stop
after each of these subtests.
Test#

Note:

Supply Measured

Expected Voltage

Tolerance(+/-)

111
112
113
114
115
116
117
118
119

Analog Ground
+10.0 V (ref-01)
-10.0 V
-2.0 V
-5.2 V
+5.0 V
+11.0 V
+15.0 V
-15.0 V

120
130

EeL THRESHOLD
TTL THRESHOLD

+1.038
-1.115

0.05 V
0.05 V

141
142
151
152

VAR
VAR
VAR
VAR

+5.12
-5.08
+5.08
+5.04
+4.96
+4.80
+4.48
+3.84
+2.56
0.00

0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05

V
V
V
V
V
V
V
V
V
V

+5.12
-5.08
+5.08
+5.04
+4.96
+4.80
+4.48
+3.84
+2.56
0.00

0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05

V
V
V
V
V
V
V
V
V
V

153

VAR

154
155
156
157
158

VAR
VAR
VAR
VAR
VAR

A = -6.40
A = +6.35
A = -6.35
A = -6.30
A = -6.20
A = -6.00
A = -5.60
A = -4.80
A = -3.20
A = 0.00

161
162
171
172
173
174
175
176
177
178

VAR
VAR
VAR
VAR
VAR
VAR
VAR
VAR
VAR
VAR

B
B
B
B
B
B
B
B
B
B

=
=
=
=
=
=
=

-6.40
+6.35
-6.35
-6.30
-6.20
-6.00
-5.60
= -4.80
= -3.20.
= 0.00

0.00
+10.00
-10.00
-2.10
-5.25
+5.00
+11.00
+15.00
-15.00

0.10
0.20
0.20
0.15
0.25
0.20
0.40
0.50
0.40

V
V
V
V
V
V
V
V
V

Eel TTL, VAR A AND VAR B Threshold tests first measure the
threshold voltage at its source, then at each channel input. When
the source is measured, the channel field will display "NA".

6-29

Tests 180-189 - Walking Eel in VAR B

On each test, one channel is set to ECL threshold and all others are set
to VAR B, which is set to 0.00 V. The threshold voltage is then measured
at all channel inputs.
Test IF
180
181
182
183
184
185
186
187
188
189

Channel Thresholds Expected Voltage
7654 3210 TQ CK
+1.038 if
EBBB BBBB B B
or 0.000 if
BEBB BBBB B B
or 0.000 if
BBEB BBBB B B
or 0.000 if
BBBE BBBB B B
or 0.000 if
BBBB EBBB B B
or 0.000 if
BBBB BEBB B B
BBBB BBEB B B
or 0.000 if
BBBB BBBE B B
or O. 000 if
or O. 000 if
BBBB BBBB E B
or 0.000 if
BBBB BBBB B E

(Tolerance
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channe I
Channe I
Channel

= 0.05

V)

= IE I
= 'B'
= 'B'
= 'B'
= 'B'
= 'B'
= 'B'
= 'B'
= 'B'
= 'B'

200 Series Tests - Delay

In these tests, the delay is set to some number of clocks and the
trigger combination is set to "1XXX XXXX X". A pattern of all zeroes is
written 2080 times to the input boards. Then a pattern of all ones is
written repeatedly to the input boards until the end-of-record bit is
set. The number of times that this pattern must be written is adjusted
by subtracting 22 and is displayed as the result. For delays of less
than 8, the expected result is zero.
TEST IF
211
212
213
214
215
216
217
218
219
221
222
223
224
225
226
227

228
229

CLOCKS DELAY

o
1

2
4
8

16
32
64
128
256
512
1,024
2,048
4,096
8,192
16,384
32,768
65,000

Test 230 - Events Delay Test

In this test, the trigger is set to "1XXX XXXX X" and the delay is set to
8 events. Patterns of all ones and all zeroes are alternately written
to the input boards until the end-of-record bit is set. The number of
times that this alternating pattern must be written is displayed as the
resul t . The expected result is 122.

6-30

300 Series Tests - Enable and Trigger
In these tests, some enable or trigger condition is created and the
hardware enable and trigger bits are tested. These bits are displayed
as the letter "e" followed by the enable bit (1=Enabled, O=Not Enabled),
and the letter "TI! followed by the trigger bit C1=Triggered, O=Not
Triggered). The expected value is preceded by a single digit indicating
the subtest being performed.
The enable and trigger tests are broken down into three groups:
Manual/Auto tests, Combinational tests and Filter tests. These tests
are presented here in that order.

Manual! Auto Enable and Trigger Tests:
Test 311 - Auto Enable Test
Auto Enable is selected and the unit is armed.

Expect E

= 1,

T =

o.

Test 312 - Manual Enable Test
Subtest·1 -

Manual Enable is selected, the unit is armed and a
pattern· of all zeroes is written to the input
boards. Expect E = 1, T = O.

Subtest 2 -

The Manual Enable key is simulated.

= o.

Expect E = 1, T

Test 321 - Manual Trigger
Subtest 1 -

Auto Enable/Manual Trigger is selected and a
pattern of zeroes is written to the input boards.
Expect E = 1, T = o.

Subtest 2 -

Manual Trigger key is simulated Expect E = 1, T = O.

6-31

Enable and Trigger Combination Tests:
In each test, enable or trigger is set to the indicated value. On each
subtest, the dummy pattern is written to the input boards a number of
times.
Then, the test pattern is written to the input boards once,
after which the dummy pattern is again written to the input boards a
number of times. The subtests occur in odd-even pairs. The first
subtest writes an odd number of dummy patterns before the test pattern,
the second subtest writes an even number of dummy patterns before the
test pattern. This ensures that both halves of the enable and trigger
circuits are tested. The patterns given below are for channel = 7. For
other channels, rotate the patterns.

Enable True Combination Tests
TESTtI SUBTESTtI COMBINATION DUMMY PATTERN TEST PATTERN DUMMY WRITES EXPECT
7654 3210 TQ 7654 3210TQ BEFORE AFTER
313

314

315

316

1 ENACT)=lXXX XXXX X 0000 0000 0
0000 0000 0
2
0111 1111 1
3
0111 1111 1
4
0000 0000 0
5
0000 0000 0
6
0111 1111 1
7
8
0111 1111 1

0111
0111
0000
0000
1000
1000
1000
1000

1111
1111
0000
0000
0000
0000
0000
0000

1
1
0
0
0
0
0
0

9

1 ENACT)=OXXX XXXX X 1111
1111
2
1000
3
4
1000
1111
5
6
1111
7
1000
8
1000

1111 1
1111 1
0000 0
0000 0
1111 1
1111 1
0000 0
0000 0

1000
1000
1111
1111
0111
0111
0111
0111

0000
0000
1111
1111
1111
1111
1111
1111

0
0
1
1
1
1
1
1

9

1 ENACT)= 1000 0000 0 0000 0000 0
2
0000 0000 0
3
0000 0000 0
4
0000 0000 0
5
1111 1111 1
6
1111 1111 1
7
0000 0000 0
8
0000 0000 0

0111
0111
1111
1111
0000
0000
1000
1000

1111
1111
1111
1111
0000
0000
0000
0000

1
1
1
1
0
0
0
0

9

1 ENACT)=Olll 1111 1
2
3
4
5
6
7
8

1000
1000
0000
0000
1111
1111
0111
0111

0000
0000
0000
0000
1111
1111
1111
1111

0
0
0
0
1
1
1
1

9

1111
1111
1111
1111
0000
0000
1111
1111

1111 1
1111 1
1111 1
1111 1
0000 0
0000 0
1111 1
1111 1

6-32

8
9
8
9
8
9
8

8
9

8
9
8
9
8
8
9
8
9
8
9
8
8
9
8
9
8
9
8

11
11
11
11
11
11
11
11

EO
EO
EO
EO
E1
E1
E1
E1

TO
TO
TO
TO
TO
TO
TO
TO

11
11
11
11
11
11
11
11

EO
EO
EO
EO
EO
EO
EO
EO

TO
TO
TO
TO
TO
TO
TO
TO

11
11
11
11
11
11
11
11

EO
EO
EO
EO
E1
E1
E1
E1

TO
TO
TO
TO
TO
TO
TO
TO

11
11
11
11
11
11
11
11

EO
EO
EO
EO
EO
EO
E1
E1

TO
TO
TO
TO
TO
TO
TO
TO

Trigger True Combinations
TESTtI SUBTESTtI COMBINATION DUMMY PATTERN TEST PATTERN DUMMY WRITES EXPECT
7654 3210 TQ 7654 3210TQ BEFORE AFTER
322

1 TRG(T)=lXXX XXXX X 0000 0000 0
0000 0000 0
2
0111 1111 1
3
0111 1111 1
4
0000 0000 0
5
0000 0000 0
6
0111 1111 1
7
0111 1111 1
8

0111
0111
0000
0000
1000
1000
1000
1000

1111
1111
0000
0000
0000
0000
0000
0000

1
1
0
0
0
0
0
0

9
8
9
8
9
8
9
8

13
13
13
13
13
13
13
13

E1
E1
E1
E1
E1
E1
E1
E1

TO
TO
TO
TO
T1
T1
T1
T1

323

1 TRG(T)=OXXX XXXX X 1111 1111
1111 1111
2
1000 0000
3
1000 0000
4
1111 1111
5
1111 1111
6
1000 0000
7
1000 0000
8

1
1
0
0
1
1
0
0

1000
1000
1111
1111
0111
0111
0111
0111

0000
0000
1111
1111
1111
1111
1111
1111

0
0
1
1
1
1
1
1

9
8
9
8
9
8
9
8

13
13
13
13
13
13
13
13

E1
E1
E1
E1
E1
E1
E1
E1

TO
TO
TO
TO
T1
T1
T1
T1

324

1 TRG(T)= 1000 0000 0 0000 0000
0000 0000
2
0000 0000
3
0000 0000
4
1111 1111
5
1111 1111
6
0000 0000
7
0000 0000
8

0
0
0
0
1
1
0
0

0111
0111
1111
1111
0000
0000
1000
1000

1111
1111
1111
1111
0000
0000
0000
0000

1
1
1
1
0
0
0
0

9
8
9
8
9
8
9
8

13
13
13
13
13
13
13
13

E1
E1
E1
E1
E1
E1
E1
E1

TO
TO
TO
TO
TO
TO
T1
T1

325

1 TRG(T)=Olll 1111 1 1111
1111
2
1111
3
1111
4
0000
5
6
0000
1111
7
1111
8

1111 1
1111 1
1111 1
1111 1
0000 0
0000 a
1111 1
1111 1

1000
1000
0000
0000
1111
1111
0111
0111

0000
0000
0000
0000
1111
1111
1111
1111

0
0
0
0
1
1
1
1

9
8
9
8
9
8
9
8

13
13
13
13
13
13
13
13

E1
E1
E1
E1
E1
E1
E1
E1

TO
TO
TO
TO
TO
TO
T1
T1

6-33

Enable False Combinations
TESTfj SUBTESTfj COMBINATION DUMMY PATTERN TEST PATTERN DUM~tY WRITES EXPECT
7654 3210 TQ 7654 3210TQ BEFORE AFTER
333

1 ENA(F)=1XXX XXXX X 1111 1111 1 1000 0000 0
1111 1111 1 1000 0000 0
2
1000 0000 0 1111 1111 1
3
1000 0000 0 1111 1111 1
4
1111 1111 1 0111 1111 1
5
1111 1111 1 0111 1111 1
6

9
8
9
8
9
8

11
11
11
11
11
11

E1
EO
E1
E1
E1
E1

TO
TO
TO
TO
TO
TO

334

1 ENA(F)=OXXX XXXX X 0000 0000 0
0000 0000 0
2
0111 1111 1
3
4
0111 1111 1
0000 0000 0
5
0000 0000 0
6

0111
0111
0000
0000
1000
1000

1111
1111
0000
0000
0000
0000

1
1
0
0
0
0

9
8
9
8
9
8

11
11
11
11
11
11

EO
EO
EO
EO
E1
E1

TO
TO
TO
TO
TO
TO

335

1 ENA(F)= 1000 0000 0 1000 0000 0
1000 0000 0
2
1000 0000 0
3
4
1000 0000 0
1000 0000 0
5
1000 0000 0
6
7
1000 0000 0
8
lOOO 0000 0

1000
1000
0000
0000
1111
1111
0111
0111

0000
0000
0000
0000
1111
1111
1111
1111

0
0
0
0
1
1
1
1

9
8
9
8
9
8
9
8

11
11
11
11
11
11
11
11

' EO
EO
EO
EO
EO
EO
E1
E1

TO
TO
TO
TO
TO
TO
TO
TO

336

1 ENA(F)=0111 1111 1 0111 1111 1
2
0111 1111 1
3
0111 1111 1
4
0111 1111 1
5
0111 1111 1
6
0111 1111 1
7
0111 1111 1
8
0111 1111 1

0111
0111
1111
1111
0000
0000
1000
1000

1111
1111
1111
1111
0000
0000
0000
0000

1
1
1
1
0
0
0

9
8
9
8
9
8
9
8

11
11
11
11
11
11
11
11

EO
EO
EO
EO
EO
EO
E1
E1

TO
TO
TO
TO
TO
TO
TO
TO

6-34

a

Trigger False Combinations
TEST!! SUBTEST!!

CO~iBINATION

DUMMY PATTERN TEST PATTERN DilllMY WRITES EXPECT
7654 3210 TQ 7654 3210TQ BEFORE AFTER

342

1 TRG(F)=lXXX XXXX X 1111 1111 1 1000 0000 0
1111 1111 1 1000 0000 0
2
1000 0000 0 1111 1111 1
3
1000 0000 0 1111 1111 1
4
1111 1111 1 0111 1111 1
5
1111 1111 1 0111 1111 1
6

9
8
9
8
9
8

13
13
13
13
13
13

EO
EO
E1
E1
E1
E1

TO
TO
TO
TO
TO
TO

343

1 TRG(F)=OXXX XXXX X 0000 0000 0 0111 1111 1
0000 0000 0 0111 1111 1
2
0111 1111 1 0000 0000 0
3
0111 1111 1 0000 0000 0
4
0000 0000 0 1000 0000 0
5
0000 0000 0 1000 0000 0
6

9
8
9
8
9
8

13
13
13
13
13
13

EO
EO
EO
EO
E1
E1

TO
TO
TO
TO
TO
TO

344

1 TRG(F)= 1000 0000 0 1000 0000 0 1000 0000 0
1000 0000 0 1000 0000 0
2
1000 0000 0 0000 0000 0
3
1000 0000 0 0000 0000 0
4
1000 0000 0 1111 1111 1
5
1000 0000 0 1111 1111 1
6
1000 0000 0 0111 1111 1
7
1000 0000 0 0111 1111 1
8

9
8
9
8
9
8
9
8

13
13
13
13
13
13
13
13

EO
EO
EO
EO
EO
EO
El
E1

TO
TO
TO
TO
TO
TO
TO
TO

345

1 TRG(F)=Olll 1111 1
2
3
4
5
6
7
8

9
8
98
9
8
9
8

13 EO TO
13 EO TO
13 EO TO
13 EO TO
13 EO TO
13 EO TO
13 E1 TO
13 E1 TO

0111
0111
0111
0111
0111
0111
0111
0111

1111 1 0111 1111 1
1111 1 0111 1111 1
1111 1 1111 1111 1
1111 1 1111 1111 1
1111 1 0000 0000 0
1111 1 0000 0000 0
1111 1 1000 0000 0
1111 1 1000 0000 0

Test 350 - Trigger Filter
TRG (T) = 1XXX XXXX X . -This Test is not channel orientedSUBTEST
1
2
3

4
5

6
7

FILTER
ON
ON
ON
ON
ON
ON
OFF

DUMMY WRITES
BEFORE
9
8
9
8
9
8
9

VALID PATTERN
WRITES
1
1
2
2
3
3
3

6-35

DUMMY WRITES
AFTER
13
13
13
13
13
13
13

EXPECT
E1
E1
E1
E1
E1
E1
E1

TO
TO
TO
TO
T1
T1
T1

400 Series Tests - Time Base Measurements

In these tests, the 8253 timer chip on the Threshold/GPIB board is used
to measure the internal clock speeds. In tests 412 to 423, the timer is
turned on for one record cycle. In tests 424 to 439, the timer is turned
on for one clock period. If a given time base signal is completely
missing, tests 412 through 423 may never see an end-of-record signal.
In this case, it will be necessary to press the 'STOP' key to end the
test.
For clocks of one millisecond or longer, the 8253 timer interrupt (level
4 interrupt) is used. If the results of these tests are all wrong, it is
possible that the interrupt line is stuck. This can be checked at Pin
22 of the 8259A interrupt controller chip. It should be low when not
testing, and have occasional pulses on it when test 436 through test 439
is run. The 8253 timer chip is gated by pin 11 and should have a precise
2 MHz clock signal on pin 9.
TEST NUMBER

CLOCK SPEED

TOLERANCE

TIMER GATE

412
413
414
415
416
417
418
419

2 nanoseconds
5
10
20
.50
100
200
500

1.0%
1.0%
1.0%
0.1%
0.1%
0.1%
0.1%
0.1%

RECORD CYCLE

421
422
423
424
425
426
427
428
429

1 microsecond
2
5
10
20
50
100
200
500

0.4%
0.4%
0.4%
3.0%
2.0%
0.6%
0.3%
0.2%
0.1%

RECORD CYCLE

431
432
433
434
435
436
437
438
439

1 millisecond
2
5
10
20
50
100
200
500

0.1%
0.1%
0.1%
0.1%
0.1%
0.1%
0.1%
0.1%
0.1%

CLOCK CYCLE

"

II

"
"
"
"
II

II

AFFECTED BY INTERRUPT
NO

"
"

II
II

"
"
"
NO

"

CLOCK CYCLE
II

"

II

"
II

"
"
"
"
"

II

II
II

II

ONLY IF STUCK HIGH

"
"
"
"
ALWAYS
"
"
"

500 Series - Walking Latch in a Field of Sample

510

For channels 7 through 0, one channel at a time has its input set
to "LATCH" and its trigger set to "I II • All other channels have
their inputs set to "SAMPLE" and their triggers set to "X". A
pattern of all zeroes is written 2080 times to the input boards. A
pattern of all ones is written once, then a pattern of all zeroes
is written 12 times. The trigger bit is now tested. The expected
end result displays are identical to the enable and trigger tests.
The expected result is E = 1, T = 1.

6-36

520

Same as 510, except the selected channel has its trigger set to "0"
and the patterns are inverted from those described above. The
expected result is E = 1, T = 1.

600 Series - GPIB Tests
There are two groups of GPIB tests: the data bus tests (611-629) and
the management bus tests (631-634). After setting up the GPIB hardware,
the data bus tests simply write bit patterns to the GPIB data bus and
read them back. These patterns are displayed in binary. The management
bus tests write bit patterns to the management bus which are transformed
by the hardware into a different bit pattern which can be read back from
the management bus. The bottom four bits read back from the management
bus are not important, and so are displayed as "xxxx" in the expected
value field, and are not displayed at all in the result field.
TEST"

PATTERN WRITTEN AND READ BACK FROM GPIB DATA BUS

611
612
613
614
615
616
617
618
619

0000
0000
0000
0000
0000
0001
0010
0100
1000

0000
0001
0010
0100
1000
0000
0000
0000
0000

621
622
623
624
625
626
627
628
629

1111
1111
1111
1111
1111
1110
1101
1011
0111

1111
1110
1101
1011
0111
1111
1111
1111
1111

631
632
633
634

WRITTEN TO MANAGEMENT
1001 0000
1010 0000
1000 0001
1100 0000

EXPECT TO
0001
0010
0100
1000

READ BACK
XXXX
XXXX
XXXX
XXXX

700 Series - Analog Board Tests
In these tests, a relay on the analog board is used to ground the analog
input. Then the analog offset DAC is used to input a voltage level to
the flash converter. A recording is taken and all 2000 samples read in
are compared with the expected value. If any sample does not match, the
test fails. Both the expected value and the result are displayed as a
level followed by the corresponding gray code value in parentheses.
TEST IF
711
712
713
714
715
716
717

OFFSET DAC CODE
44H
SOH
58H
60H
68H
70H
78H

OFFSET
-3.75
-3.00
-2.50
-2.00
-1.50
-1.00
- .50

V/DIV
2.0
2.0
2.0
2.0
2.0
2.0
2.0

6-37

EXPECTED ADC
1000B
1001B
1011B
1010B
1110B
1111B
1101B

OUTPUT /LEVEL
15
14
13
12
11
10
9

718
719
721
722
723
724
725
726
727

80H
88H
90H
98H
AOH
A8H
BOH
B8H
COH

- .00
+ .50
+1.00
+1.50
+2.00
+2.50
+3.00
+3.50
+4.00

2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0

1100B
0100B
0101B
0111B
0110B
OOlOB
0011B
0001B
OOOOB

8
7
6
5
4

731
732
733

30H
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Test 800 - Trace Location Test
This is the last test of the series. A distinctive pattern is written
to the high speed rams, and then is read back into memory and displayed
as timing traces. If auto looping is not enabled, this display will
remain until the operator presses 'STOP'. W"ith auto looping, the traces
will be displayed for about one second before testing starts over again.
When the test is stopped, the enable and trigger are tested. The
expected result is E = O~ T =0.

6-38

OPERATING AND SERVICE MANUAL
MODEL KSOO-D LOGIC ANALYZER
SECTION VII
SCHEMATIC AND ASSEMBLY DRAWINGS

7. 1

I ntrod uction

This section contains assembly drawings, schematic diagrams, and parts
The drawings are listed in a
lists (LMs) for the K500-D Logic Analyzer.
functional order as follows:

7.2

•

Top Assembly, Chassis, and CRT,

•
•

Keyboard and Lower Front Panel

•

PC Boards (from left to right)

•

Probes

Power Supplies

List of Drawings

Top Assembly, Chassis and, CRT
TITLE

PART NUMBER

REVISION

1.

Top Assembly
1 sheet (LM 2 sheets)

0950-0002

u

2.

Chassis Assembly, K500-D
2 sheets (1M 2 sheets)

0950-0003

x

3.

CRT Assembly
1 sheet (LM 1 sheet)

0950-0131

J

Keyboard and Front Panel
4.

Keyboard Assembly
1 sheet (LM 1 sheet)

0112-0120

C

5.

Schematic, XI00-D Keyboard
1 sheet

0112-0121

A

6.

Lower Front PWB Assembly
1 sheet (LM 1 sheet)

0950-0010

B

7.

Schematic, Lower Front PWB
1 sheet

0950-0011

C

8.

Data Input Cable Assembly
1 sheet (LM 1 sheet)

0950-0114

H

7-1

Type 1 Power Supply
TITLE

PART NUMBER

REVISION

9~

Top Assembly, Power Supply
2 sheets (1M 3 sheets)

0285-0003

x

10.

Assembly, Power Supply PWB
3 sheets (1M 13 sheets)

0285-0010

KS

11.

Schematic, Power Supply
4 sheets

. 0285-0011

KS

12.

Assembly, Face Plate
1 sheet (LM 1 sheet)

0285-0156

D

13.

Assembly, Power Supply Filter Board
1 sheet (1M 1 sheet)

0285-0160

F

14.

Schematic, Power Supply Filter Board
1 sheet

0285-0161

E

15.

Assembly, Power Supply Filter Board
1 sheet (LM 1 sheet)

0285-0180

J

16.

Power Supply Schematic, Filter Board
1 sheet

0285-0181

H

Type 2 Power Supply
17.

Top Assembly, K101/K500 Power Supply
2 sheets (1M 2 sheets)

0114-0320

K

18.

Assembly PCB, Soft Start Power Supply
1 sheet (1M 7 sheets)

0114-0090

S

19.

Schematic, Soft Start Power Supply
4 sheets

0114-0091

S

20.

Face Plate Assembly, Power Supply
1 sheet (1M 1 sheet)

0114-0340

B

21.

Assembly, Filter Board, Power Supply
1 sheet (1M 1 sheet)

0114-0360

F

22.

Filter Board Schematic
1 sheet

0114-0361

F

0114-0330

E

23.

Heat Sink Assembly
. 1 sheet (LM 1 sheet)

7-2

PC Boards
TITLE

PART NUMBER

REVISION

24.

Motherboard PCB Assembly
1 sheet (LM 2 sheets)

0950-0020

G

25.

Interconnect Diagram, K500 Motherboard
1 sheet

0950-0021

F

26.

Assembly, Data Display Board
2 sheets (LM 8 sheets)

0114-0190

u

27.

Schematic, Data Display PWB
6 sheets

0114-0191

P

28.

Assembly, K101, K500 MPU Board
1 sheet (LM 12 sheets)

0114-0185

v

29.

Schematic, 8086 MPU
6 sheets

0114-0186

v

30.

Assembly, Threshold/GPIB/RS232
1 sheet (LM 5 sheets)

0114-0170

AC

31.

Schematic, Threshold/GPIB/RS232
5 sheets

0114-0171

AC

32.

Assembly, Analog Board
1 sheet (LM 7 sheets)

0950-0025

Q

33.

Schematic Diagram, Analog PWB
3 sheets

0950-0026

M

34.

Assembly, Input Board
3 sheets (LM 4 sheets)

0950-0115

AA

35.

Schematic, Input Board
7 sheets

0950-0116

AA

36.

Assembly, Record Control PCB
1 sheet (LM 5 sheets)

0950-0005

EK

37.

Schematic Diagram, K500 Record Control PCB
5 sheets

0950-0006

EK

Probes
38.

Probe Cable Assembly (IBM Adaptable)
I sheet (LM 1 sheet)

0950-0254

E

39.

Probe Cable Assembly
1 sheet (LM 1 sheet)

0950-0045

E

40.

K500 Probe Hybrid
2 sheets

0950-0121

E

7-3

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017,021
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30
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NUMBE~

FOWER SUPPLY

LM

ASSY PWA

MODEL
QTY PER ASSY

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U/II

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DRAWING NO.

0285-0010
4500

DESCRIPTION

ISHEET

KS

3

OF

13

REFERENCE DESIGNATION

37
38
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40 1700 - OOg6
41 1700 - 0080
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- 0066
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48 1820 - 0072
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1
3

I.e. 'ILM358
I.e., LM324

U12
U3,4.9

1

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,14175
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1
1
1
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52

1

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2.

~ERM!STa<,RL0~- 328-59-52

2

RESISTOR, 150K

RTl,RT2.

54

55
510 3000 -1503

TITLE

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ITEM
NO.

57

PART NUMBER

!=OlVER SUPPLY
ASSY PWA·

y4W 570
LM

MODEL
QTY PER A88Y

-10 -20 ~03 -04-08

U/M

R150,151
REV

DRAWING NO.

0285 -0010
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4

OF

13

REFERENCE DESIGNATION

DESCRIPTION

RESISTCR • 100il,Y4W, 5t R31,40

3000 -1000

2

58
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1002

11

10K

00

1003

61
62

2202

0
1

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63

2204

4

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RIDS, 1~4 , 153, 154

4301
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2200

1
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1803

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1

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100-108.110,125
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R142.

64
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70
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TITLE

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NO.

PART NUIIBER

77 3000 - 5103
78
2401
7g
270200
81

4700

82

4700

POWER SUPPLY
ASSY PWA

LM
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U/II
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I-HEIT

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RESISTOR ~ 510K

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2.4 K, 1j4W, 5% R140
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4
1

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470./lJ

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4.7K

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R15.80) 112
R45,46,140

1

1

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83

4701

84
85
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5601

3
3

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3

2701

4

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3300

1

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81

qo

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51

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91

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1
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%
TITLE

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ITEM
NO.

PART NUMBER

g7 3000 -1102

POWER SU PPL\(
ASSY PWA

LM
IIODEL

OTY PER ASSY

-10 -20 -03 -04-05

U/M

DRAWING NO.

REV

0285-0010
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DESCRIPTION

ISHEET

KS

10

OF

13

REFERENCE DESIGNATION

R7q
RESISTOR ~ 11 K
20K,Y4W,5% R41,82.
20K, 1/8W. 1t R83,122.
8.2K,~4W,51 R52

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2
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101
102 3000 -1502

1

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1

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103
104
105 3100 - 1503
100 3100 - 5621

107 3100 - 3921
108
109
110
11 1 3120 - 1002
f 12
113 3100 - 8871
1-14 3100 - t151
115 3050 -1507
111013050 - 8200

1
1

R123
5.62K,1j8W,I70 R127
3.Q2K,Y8W,11- R128

8

10K, Ysw, .5

1
1

8.87K,Yew, It R158

2

I I2 I I I I

•

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R50.58.68. 09 ,71,72,73,74

R15g
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IRESISTOR. 820Sl. yZw, 51.IR2Q. 30

TITLE

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NO.

POWER 5UPPLY

PART NUMBER

117
118 3200 - 003g

LM

ASSY PWA

GOULD

0285-0010

MODEL
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U/U

I

4500

DESCRIPTION

SHEET

KS

7

OFJ3

REFERENCE DESIGNATION

RESISTOR, 22J1, 2'vV

1

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Ri39

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120 3070 - 3000
121 3070 - 4700
12Z 3050 -1007
123 0285 - 0200-20
124
125 3080-5002
120 3000-5100
127 3050-1200
128

2.
1

,300Jl, lW, 51470n, lW. 51.

1
1

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RtOO,131
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R143
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2

56K,2W, sf.

Rl0,11

1

51Il.2W.570

1

lZ!2 •YZW. 51.

R157
R150

12<1 3200 -0037
130 3200 -0033

1
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L
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135 0285 - 0200-10

2
2.

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2 MILL! OHM

130 3J50 -1800

1

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131 3200 -0035
132 3080 - 3900

Ill Y2W,51.
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R33,34 1 1'33

R35.30
RCf1

133
134

0285 - 01Q9

TITLE

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NO.

GOULD
PART NUMBER

137
138 3300 - 0005
139 3300 -0068
140
141 3200 - 0038
142
143

POWER SUPPLY
ASSV PWA

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U/M

RB9,91
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DRAWING NO.

LM

0285 -0010

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R75,76

4500

ISHEET

KS

6

OF

13

REFERENCE DESIGNATION

DESCRIPTION

n

5
5

VAR. RESISTOR~2(x)
VAR. RESISTOR, 5K

2

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147 4010 - 0101

1

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148 4010 - 0103

1
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R134,1G1

1M
145
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150 4010 -0104
151
152 4000-0044
153 4100-0007
154 4200-0000
155 4000-0007

1'5(01 Ll100 -0015
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(a,)334,37AZ,M,47,49.59,71

C22.23
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13 I I I I I CAPKJTOR, 1000j1j, rq)QV IC15, 10 ,30

TITLE

-} GOULD
ITEM
NO.

PART NUMBER

157 4100 - 0018

158 4010 - 0471
159
100 4300-0024

161 4010-0822
162
103
104 4400-0037
105 4010 -0332
100 4400-0050

101 4400-0052
168
1(09

4300 -0009

170
111 4200-0036
172. ~OO-0050
173 4200-0041
174 4400 -0051
175 0100 -0150
170 0100-0149

aTY PER ASSY

-10 -20 -03 -04 -05

177 0400-0039
178 7200-0037
179 7200 -0031
180
181
182 6400-0052
183 ~200 - OO~ -10
184 flZOD -002..7-10
185 (olOO -OD3lD -10
186 2500 -0010- 20
187 gOOO-Ol64
188 g(()() - 0075
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190 gOOO-OO78

4500

I

REFERENCE DESIGNATION

CI7,18,35

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470JJ;j, 12. V C53,54.55
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SOCKET .040 DIA TERM

XQ18,XQ20
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POWER SUPPLY
ASSY PWA

aTY PER ASSY

C5f ,52

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LM
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4
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470.PJ-, r:o;/lOCN C4i ,70

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2
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1
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1
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TITLE·

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054.5,0,7

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TITLE

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NO.

PART NUMBER

POWER SUPPLV
ASSY PWA

LM
MODEL

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197
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-02
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203
204
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201
202

0285 -0010

DESCRIPTION

SHEET

KS

11

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13

REFERENCE DESIGNATION

2

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227 7150-0016 -01
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DESCRIPTION

217
218

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TITLE

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ITEM
NO.

PART NUMBER

237 7150 -0012 -15

POWER SUPPLY
ASSY PWA

LM
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QTY PER AllY

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1

U/M

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LIST OF MATERIAL

PROBE CABLE..
A55EMBL'1

IMODEL KSOO

eKD

APPD

i4l-"

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R23

R22

VREF

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lN82~

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+18%

I!l

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811ur

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4

4

INPUT
1391(+18%
ISPARI<..6AP

R7

R8

Rll

R18

QSeH1629

11K HOM.

R21
58+5%
VOUT

QSCH1629
2N2987A
21<+2%
R5
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R18
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R19
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6

R4
188

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Tol"r

R6
11. II<
NOTES:

6

1Ur

1. UI-MC4741 OR EQUIYALENT QUAD 741 OP AMP.
2. R8 & R18 AND/OR R27 & R28 ARE ACTIYELV TRIMMED
SO AS TO SET VOLTAGE ACROSS R15 & Rl6 RESPECTIVELV;
TO 2.4+.15 VOLTS.
3. R23 IS ACTIVELV TRIMMED SO AS TO SET VOUT
TO -I. 321!. ee5 VOLTS ~HEN VIN, YTH AND YRTN ARE GROUNDED.
4. ALL RESISTORS ARE !1% TOLERANCE UNLESS
S. ALL CAPACITORS ARE !21%

C

OTHER~ISE

~--+-------~__~DRA~N

SPECIFIED.

J.A~ewQSikPo~n

DATE

..~ 6(lIJD DESIGN & TEST

~--+-____--~__~PRO~ENGR

~ R13 & R14 TO BE !18% TOLERANCE ~ITH !1% RATIO MATCHING.

r-__+-______-r__~~~~~~~__--~TITLE
~--4-------~--~"ANUFACTURING

R18 & R19 TO BE +5% TOLERANCE ~ITH +1% RATIO MATCHING.

9. YENDOR TO MARK PART

B

UNLESS

SPECIFIED.

~ ADJUST Cl FOR INPUT COMPENSATION ~HICH PRODUCES e TO 18".

[!]

8

TOLERANC~

OTHER~ISE

D

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CURRENT REYISION LEYEL.

18 8958-8254
DASH NUMBER
QTY ECO NO.
NO. NEXT ASSEMBLY

G

H

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2

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RESISTOR SPECIfICATIONS
RESISTORS
3

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••

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•

8.848 +.883

-

TRANSISTORS

I

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18

137.61<

148.3K

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18

119.8K

112.1K

18eK

R3

2~

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23.7~

26.25

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R4

18e

5

185

58

95
13.76K

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11.21K

leK

f

R7, 11,25,26

2K

2

1.961(

2.84K

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R8,18,27 .. 28

6-181(

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11~

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A. T.

R9

388

1

297

383

11(

R12

51e

1

584.9

5115. 1

11(

R13

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18

91<

111(

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18

181<

221<

18K

R15,16

2el

1

198

282

58

R17

15

5

14.25

15.75

58

R18 .. 19

688

5

646

714

lK

R28

158

5

47.15

52.5

58

1

R21

38

15

28.5

31.5

58

R22

51<

R23

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R24

5

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