0M910200 XXX 6_DSTD 102_CPU_and Serial_IO_Operation_Manual_Jul83 6 DSTD 102 CPU And Serial IO Operation Manual Jul83
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Document No. O?I910200-XXX-6 DSTD- 102 CPU AND SERIAL V O OPERATION MANUAL PREPARED BY d y 4 SYSTEMS INC DATED JULY 1 llh. 1983 DY-4 SYSTEMS INC., 888 LADY ELLEN PLACE, OTTAWA, ONTARIO, CANADA K1Z S M 1 (613)728-3711 NOTICE n The p r o p r i e t a r y i n f o r m a t i o n c o n t a i n e d i n t h i s document m u s t n o t be d i s c l o s e d t o o t h e r s f o r any purpose, nor used f o r m a n u f a c t u r i n g p u r p o s e s , w i t h o u t w r i t t e n p e r m i s s i o n o f dy-4 SYSTEMS INC. The a c c e p t a n c e o f t h i s document w i l l b e c o n s t r u e d a s an a c c e p t a n c e o f t h e f o r e g o i n g c o n d i t i o n . CHANGE NOTICE R e v i s i o n 6 o f t h e DSTD-102 c o n t a i n s s e v e r a l s i g n i f i c a n t enhancements o v e r r e v i s i o n 4 and e a r l i e r boards. These e n h a n c e m e n t s h a v e been added f o l l o w n g c u s t o m m e r r e q u e s t s t o t a k e advantage o f r e c e n t technology developments. 1. The DSTD-102 now s u p p o r t s 8 k b y t e RAMS ( I n t e l 2 1 8 6 ) and 16 k b y t e EPROMs. N o t e t h a t t h e a d d i t i o n o f t h i s f e a t u r e r e q u i r e d t h e r e - l a y o u t o f t h e memory d e v i c e j u m p e r b l o c k s J B 9 , J B 1 0 a n d JB12. R e f e r t o s e c t i o n 3.2 f o r a complete description. 2. The memory d e c o d e PAL now s u p p o r t s s i x d i f f e r e n t memory c o n f i g u r a t i o n s , i n c l u d i n g 2K, 4K, 8K a n d 16K c o n f i g u a t i o n s i n t h e o n e PAL 3. Using a jumper b l o c k t h e DSTD-102 w i l l now s u p p o r t b o t h tfsynchronousu edge t r i g g e r e d push button r e s t ( a v a i l a b l e on r e v 4 b o a r d s ) and l e v e l s e n s i t v e r e s e t s (new). The l e v e l s e n s i t i v e p u s h b u t t o n r e s e t c a p a b i l i t y i s r e q u i r e d when u s i n g brown-out d e t e c t i o n l o g i c s u c h a s t h a t on t h e DSTD 703. 4. T h i s r e v a l l o w s f u l l a c c e s s t o t h e on-board I / O d e v i c e s from o t h e r c a r d s i n t h e system. T h i s i s p a r t i c u l a r l y . u s e f u l when t h e DSTD-103 s l a v e p r o c e s s o r i s b e i n g used. TABLE OF CONTENTS SECTION 1 GENERAL INFORMATION Introduction 1 - 1 DSTD S e r i e s G e n e r a l D e s c r i p t i o n 1 - 1 DSTD-102 F e a t u r e s 1 - 1 SECTION 2 FUNCTIONAL HARDWARE DESCRIPTION Introduction 2 - 1 Block Diagram D e s c r i p t i o n 2 - 1 CPU Clock G e n e r a t o r CTC ( C o u n t e r / C i r c u i t ) Memory Decode Logic R e s e t C o n t r o l Logic Wait S t a t e G e n e r a t o r Serial Ports SECTION 3 USER-SELECTABLE OPTIONS Introduction 3 - 1 Debug/Single S t e p C o n f i g u r a t i o n Memory O p t i o n s 3.3.1 3.3.2 3.3.3 R e s t a r t Address Memory C o n f i g u r a t i o n On-board Memory D i s a b l e L a t c h 3 - 1 3 - 2 3 6 - 6 WAIT S t a t e G e n e r a t o r 3 Counter/Tirner O p t i o n s 3 - 7 n 3.6 S e r i a l Channel O p t i o n s 3.6.1 3.6.2 3.6.2.1 3.6.2.2 3.6.3 4.0 Baud Rate G e n e r a t o r DTE/DCE C o n f i g u r a t i o n s DCE C o n f i g u r a t i o n DTE C o n f i g u r a t i o n Synchronous O p e r a t i o n SECTION 4 4.1 SPECIFICATIONS Functional Specifications Word S i z e Cycle Time Memory C a p a c i t y Memory Access Time 1 / 0 Addressing I / O Capacity Interrupts System Clock 4.2 Electrical Specifications STD B u s I n t e r f a c e Serial Ports Operating Temperature Power Supply Requirements 4.2.1 4.2.2 4.2.3 4.2.4 n 4.3 Mechanical S p e c i f i c a t i o n s 4.3.1 4.3.2 4.3.3 5.0 SECTION 5.1 5.2 Card Dimensions STD Bus Edge Connector S e r i a l P o r t Connector 5 FACTORY NOTICES Factory Repair S e r v i c e L i m i t e d Warranty APPENDICES n APPENDIX A Option Programming Summary APPENDIX B STD-BUS S i g n a l s APPENDIX C Parts L i s t APPENDIX D Schematic n LIST OF FIGURES FIGURE 1 - 1 2 - 1 C - 1 DESCRIPTION PAGE DSTD-102 Module F u n c t i o n a l Block Diagram DSTD-102 S i l k S c r e e n LIST OF TABLES TABLE DESCRIPTION Memory Socket/Jumper Block Assignment Memory S o c k e t C o n f i g u r a t i o n Memory Address/Enable O p t i o n s MI Memory Cycle Wait S t a t e s Timing 2.5Mhz MI Memory Cycle Wait S t a t e s Timing 4.0Mhz Wait S t a t e O p t i o n s Baud Rate G e n e r a t o r Programming RS-232C D C E Jumper C o n f i g u r a t i o n RS-232C DTE Jumper C o n f i g u r a t i o n Synchronous D C E I DTE Jumper C o n f i g u r a t i o n S e r i a l Cable C o n n e c t i o n s PAGE 3 3 3 3 3 3 3 3 3 3 3 --- 354 , -6 - 7 - - 7 8 9 9 10 11 GENERAL INFORMATION (7 SECTION 1 1.0 GENERAL INFORHATION 1.1 Introduction - T h e d y - 4 SYSTEMS1 DSTD-102 CPU, F i g u r e 1 1, i s a 280 based I t f e a t u r e s a CPU c h i p , t w o s e r i a l microcomputer board. c o m m u n i c a t i o n s c h a n n e l s , 4 c o u n t e r / t i m e r s a n d t h r e e 2 8 p i n memory s o c k e t s f o r b y t e - w i d e memory d e v i c e s . DSTD Series General Description 1.2 T h e DSTD s e r i e s w a s d e s i g n e d t o s a t i s f y t h e n e e d f o r l o w c o s t O E M microcomputer modules. T h e DSTD-Z80 BUS u s e s a m o t h e r b o a r d i n t e r c o n n e c t s y s t e m c o n c e p t . The m o d u l e s f o r t h e STD-Z80 BUS a r e a c o m p a c t 4.5 x 6.5 i n c h e s w h i c h p r o v i d e s f o r s y s t e m p a r t i t i o n i n g by f u n c t i o n , e.g. CPU, M e m o r y , I / O , e t c . T h i s s m a l l e r m o d u l e s i z e m a k e s s y s t e m p a c k a g i n g e a s i e r , w h i l e i n c r e a s i n g MOS-LSI d e n s i t i e s p r o v i d e h i g h f u n c t i o n a l i t y p e r module. 1.3 DSTD-102 Features . U t i l i z e s t h e powerful 280 m i c r o p r o c e s s o r P r o v i d e s t h r e e 2 8 p i n s o c k e t s w h i c h may b e s t r a p p e d t o a c c e p t any combination o f t h e f o l l o w i n g i n d u s t r y s t a n d a r d memory d e v i c e s . EPROM 2758 (lkx8) STATIC RAM 4118 ROM (lkx8) Four cascadable counter/timer channels - 2 s e r i a l RS-232C c h a n n e l s Channel A h a s two a d d i t i o n a l RS-232C d r i v e r s a n d r e c e i v e r s f o r e x t e r n a l c l o c k i n g allowing f u l l synchronous operation. T r a n s m i t a n d R e c e i v e LEDs on C h a n n e l A . F u l l y b u f f e r e d s i g n a l s f o r system e x p a n d a b i l i t y G E N E R A L INFORMATION DSTD-102 (7 S e l e c t a b l e r e s e t a d d r e s s t o e i t h e r OOOOH o r EOOOH . . . . . A l l o n - b o a r d memory c a n b e d i s a b l e d a n d e n a b l e d u n d e r software control S e l e c t a b l e WAIT s t a t e g e n e r a t o r f o r memory d e v i c e s on a l l MI c y c l e s , M E M R Q c y c l e s o r a l l INTAK c y c l e s C o m p a t i b l e w i t h MDX-SST d u r i n g debugging 4MHz v e r s i o n a v a i l a b l e STD-Z80 b u s c o m p a t i b l e for single step operation GENERAL INFORMATION FIGURE 1 - 1 DSTD-102 MODULE FUNCTIONAL HARDWARE DESCRIPTION SECTION 2 2.0 FUNCTIONAL HARDWARE DESCRIPTION 2.1 Introduction T h e DSTD-102 u t i l i z e s a 2 8 0 m i c r o p r o c e s s o r a s t h e s y s t e m controller. I t f e a t u r e s t h r e e 2 8 p i n memory s o c k e t s w h i c h e n a b l e s t h e u s e r t o p o p u l a t e t h e module w i t h any c o m b i n a t i o n o f d e s i g n a t e d ROM a n d EPROM. Cus.tom a d d r e s s d e c o d i n g a l l o w s t h e u s e r t o c o n f i g u r e t h e m e m o r y o n a n y 8K b o u n d a r y o f t h e 64K m e m o r y map. A PAL d e c o d e r i s s u p p l i e d t o a l l o w t h e u s e r t o c h o o s e o n e o f six p o p u l a r memory c o n f i g u r a t i o n s , o r i f d e s i r e d t h e u s e r may i m p l e m e n t o t h e r m i x t u r e s o f memory d e v i c e s s i m p l y by p r o g r a m m i n g t h e PAL a c c o r d i n g l y . A 4 c h a n n e l c o u n t e r / t i m e r c i r c u i t i s i n c l u d e d f o r s o f t w a r e cont r o l l e d c o u n t i n g and t i m i n g f u n c t i o n s . On-board s t r a p p i n g o p t i o n s m a k e i t p o s s i b l e t o c a s c a d e t h e f o u r CTC c h a n n e l s f o r l o n g c o u n t s e q u e n c e s . T h e CTC may a l s o b e u s e d a s a b a u d r a t e g e n e r a t o r f o r t h e s e r i a l c h a n n e l s i f n o n - s t a n d a r d baud r a t e s a r e required. f9 The DSTD-102 h a s t w o s e r i a l c h a n n e l s i m p l e m e n t e d u s i n g t h e Z80SIO LSI c h i p . The SIO a l l o w s f o r b o t h a s y n c h r o n o u s a n d s y n c h r o n o u s (SDLC, HDLC, BISYNC, e t c . ) m o d e s . C h a n n e l A c a n b e u s e d a s b o t h a s y n c h r o n o u s and s y n c h r o n o u s modes and c h a n n e l B p r o v i d e s asynchronous operation. ( S y n c h r o n o u s o p e r a t i o n i s a v a i l a b l e on t h e DSTD-102A v e r s i o n o f t h e b o a r d n o t t h e s t a n d a r d DSTD102.) C h a n n e l A h a s a d d i t i o n a l RS-232C d r i v e r s a n d r e c e i v e r s f o r e x t e r n a l c l o c k s . I n a s y n c h r o n o u s mode b o t h c h a n n e l s w i l l o p e r a t e u p t o 19.2k b a u d u s i n g t h e b a u d r a t e g e n e r a t o r . T h e CTC may b e used f o r h i g h e r rates. C h a n n e l A w i l l r u n t o 307 k i l o b a u d i n s y n c h r o n o u s mode. - A strapping option a l l o w s t h e user t o select the r e s e t address t o b e e i t h e r O O O O H o r E O O O H . T h e EOOOH o p t i o n i s r e q u i r e d f o r u s e o f s t a n d a r d s o f t w a r e a n d h a r d w a r e p r o d u c t s i n c l u d i n g dy-4 SYSTEMS Debug M o n i t o r ( D D M ) a n d D i s k C o n t r o l M o n i t o r ( D C M ) f i r m w a r e p r o d u c t s . A l s o t h e s e p r o d u c t s r e q u i r e o n b o a r d RAM s t r a p p e d t o r e s i d e a t l o c a t i o n FCOOH t o FFFFH. The DSTD-102 i s a v a i l a b l e i n 2.5 MHz and 4 Mhz v e r s i o n s . Block Diagram D e s c r i p t i o n 2.2 n - 1 is a block diagram i l l u s t r a t i n g t h e flow o f system Figure 2 a d d r e s s , d a t a a n d c o n t r o l s i g n a l s on t h e DSTD-102. The f o l l o w i n g p a r a g r a p h s d e s c r i b e t h e f u n c t i o n of each o f t h e m a j o r blocks. t FUNCTIONAL H A R D W A R E DESCRIPTION ("I 2.2.1 CPU I t f e t c h e s , decodes and The 2 8 0 i s t h e s y s t e m c o n t r o l l e r . e x e c u t e s i n s t r u c t i o n s f r o m memory and g e n e r a t e s t h e n e c e s s a r y a d d r e s s and c o n t r o l s i g n a l s t o c o - o r d i n a t e d a t a f l o w between t h e CPU a n d m e m o r y o r b e t w e e n t h e CPU a n d s y s t e m 1 / 0 d e v i c e s . 2.2.2 Clock G e n e r a t o r The DSTD-102 h a s a c r y s t a l c o n t r o l l e d o s c i l l a t o r t o g e n e r a t e t h e A divideb a s i c c l o c k s i g n a l s f o r t h e CPU and p e r i p h e r a l c h i p s . by-two c i r c u i t e n s u r e s a 50% d u t y c y c l e and a n a c t i v e p u l l u p c i r c u i t ensures proper clock levels. An i n v e r t e d c l o c k i s s u p p l i e d t o t h e b u s f o r u s e by o t h e r m o d u l e s . 2.2.3 n CTC ( C o u n t e r / C i r c u i t ) T h e C o u n t e r / T i m e r C i r c u i t (MK3882/Z80-CTC) p r o v i d e s f o u r independent, programmable channels f o r e i t h e r s o f t w a r e o r hardware c o n t r o l l e d c o u n t i n g and t i m i n g f u n c t i o n s . Each c h a n n e l c a n b e c o n f i g u r e d by t h e CPU f o r v a r i o u s m o d e s o f o p e r a t i o n a n d t h e built-in daisy chain p r i o r i t y i n t e r r u p t l o g i c provides f o r automatic, independent i n t e r r u p t vectoring. The I/O p o r t a d d r e s s e s f o r t h e CTC a r e h a r d - w i r e d a s f o l l o w s : 1/0 PORT ADDRESS CTC CHANNEL A s t r a p p i n g o p t i o n h a s a l s o been i n c l u d e d t o p e r m i t any o r a l l o f t h e f o u r CTC c h a n n e l s t o b e c a s c a d e d f o r l o n g c o u n t s e q u e n c e s . Section 3 provides t h e necessary information f o r u t i l i z i n g t h i s o p t i o n . F o r a c o m p l e t e d e s c r i p t i o n o f t h e CTC o p e r a t i o n , r e f e r t o e i t h e r t h e M o s t e k MK3882 o r Z i l o g Z80-CTC T e c h n i c a l Manual o r Appendix A-15 o f t h i s m a n u a l . 2.2.4 f7 Memory The DSTD-102 h a s b e e n d e s i g n e d t o a c c o m m o d a t e a n y c o m b i n a t i o n o f t h e b y t e - w i d e R A M , ROM a n d EPROM d e v i c e s . T h r e e 2 8 - p i n s o c k e t s h a v e b e e n p r o v i d e d , e a c h o f w h i c h may b e s t r a p p e d f o r any -of t h e a l l o w a b l e memory t y p e s . These user-selectable o p t i o n s a r e f u l l y d e s c r i b e d i n S e c t i o n 3. FUNCTIONAL HARDWARE DESCRIPTION (7 2.2.5 Decode L o g i c T h i s s e c t i o n c o n s i s t s p r i m a r i l y of a PAL w h i c h d e c o d e s t h e h i g h o r d e r s i x b i t s o f memory a d d r e s s a n d g e n e r a t e s t h e a p p l i c a b l e c h i p s e l e c t i f o n - b o a r d memory i s t o b e s e l e c t e d . T h e P A L p r o The memory v i d e s s i x s e p a r a t e memory c o n f i g u r a t i o n s . ' c o n f i g u r a t i o n s a r e s e l e c t e d u s i n g an o p t i o n jumper block a s e x p l a i n e d i n S e c t i o n 3. The DSTD-102 h a s a l a t c h t o d i s a b l e a l l o n - b o a r d memory u n d e r s o f t w a r e c o n t r o l . On p o w e r - u p a n d r e s e t , t h e l a t c h i s p r e s e t e n a b l i n g t h e on b o a r d memory. O n - b o a r d memory i s d i s a b l e d by w r i t i n g a ' 1 ' t o 1 / 0 p o r t 07BH. The o n - b o a r d memory c a n b e r e - e n a b l e d by w r i t i n g a '0' t o p o r t 07BH. 2.2.6 Reset Control Logic T h i s i s a s t r a p p i n g o p t i o n t h a t c a u s e s a h a r d w a r e - f o r c e d memory s t a r t i n g a d d r e s s upon s y s t e m r e s e t . A r e s e t a d d r e s s o f e i t h e r OOOOH o r EOOOH may b e s e l e c t e d . n T h i s l o g i c i s r e q u i r e d f o r u s e o f s t a n d a r d MOSTEK h a r d w a r e a n d s o f t w a r e p r o d u c t s i n c l u d i n g DDT-80, FLP-80DOS/MDX, MDX-SST, and MDX-DEBUG and dy-4 Debug M o n i t o r (DDM) and CP/M s o f t w a r e . A l s o t h e p u s h b u t t o n r e s e t f u n c t i o n may b e e d g e t r i g g e r e d o r l e v e l s e n s i t i v e d e p e n d i n g on j u m p e r b l o c k 5815. The e d g e t r i g g e r e d r e s e t i s s y n c h r o n i s e d w i t h MI t o e n s u r e t h a t t h e c o n t e n t s o f any d y n a m i c RAM i n t h e s y s t e m a r e p r e s e r v e d d u r i n g t h e r e s e t p r o c e s s . The l e v e l s e n s i t i v e o p t i o n i s r e q u i r e d when i t is necessary t o hold t h e p r o c e s s o r i n a r e s e t s t a t e i n d e f i n i t e l y such a s i n a tbrown-out' s i t u a t i o n . Wait S t a t e Generator T h i s f u n c t i o n , if e n a b l e d , c a u s e s memory r e a d and w r i t e c y c l e s t o b e l e n g t h e n e d by o n e c l o c k p e r i o d i n o r d e r t o a l l o w s u f f i c i e n t a c c e s s t i m e when s l o w e r memory d e v i c e s a r e used. W a i t s t a t e s c a n be enabled s e l e c t i v e l y , namely, a l l memory c y c l e s o r o p c o d e f e t c h c y c l e s o n l y o r a l l memory c y c l e s a c c e s s i n g on-board memory d e v i c e s o r a l l o p c o d e f e t c h c y c l e s a n d a l l memory c y c l e s a c c e s s i n g o n b o a r d memory. An a d d i t i o n a l w a i t s t a t e may a l s o b e inserted during INTAK cycles. - FUNCTIONAL HARDWARE DESCRIPTION A 2.2.8 Serial Ports The DSTD-102 h a s t w o RS-232C s e r i a l p o r t s i m p l e m e n t e d u s i n g t h e Z80-SIO/MK3884. Each p o r t h a s a s o f t w a r e p r o g r a m m a b l e b a u d r a t e The g e n e r a t o r . T h e b a u d r a t e i s s e t by w r i t i n g t o p o r t 7 A H . l e a s t s i g n i f i c a n t 4 b i t s s e t t h e baud r a t e f o r C h a n n e l A a n d t h e m o s t s i g n i f i c a n t 4 b i t s a r e f o r C h a n n e l B. B o t h C h a n n e l s w i l l o p e r a t e f r o m 5 0 b a u d t o 19.2K b a u d . I n a d d i t o n t h e CTC may b e used t o g e n e r a t e t h e r e c e i v e and t r a n s m i t d a t a c l o c k s o f Channel A a l l o w i n g f o r n o n - s t a n d a r d baud r a t e s . The CTC c a n o n l y b e u s e d f o r a s y n c h r o n o u s modes b e c a u s e it d o e s n o t g e n e r a t e a 50% d u t y c y c l e c l o c k . C h a n n e l A a l s o h a s a d d i t i o n a l RS-232C d r i v e r s a n d r e c e i v e r s t o enable it t o handle e x t e r n a l c l o c k s f o r f u l l sync h r o n o u s o p e r a t i o n (SDLC, HDLC, BYSYNC, MONOSYNC e t c . ) . USER-SELECTABLE OPTIONS fl SECTION 3 3.0 3.1 USER-SELECTABLE OPTIONS Introduction The DSTD-102 i n c o r p o r a t e s many s t r a p p i n g o p t i o n s t o p r o v i d e t h e user with a high degree o f f l e x i b i l i t y i n system configurations. T h i s s e c t i o n d e s c r i b e s t h e u s e o f t h e a v a i l a b l e jumper options. 3.2 n Debug/Single S t e p C o n f i g u r a t i o n s The DSTD-102 s u p p o r t s t h e MDX-SST module. T h i s module g e n e r a t e s a N M I ( n o n - m a s k a b l e i n t e r r u p t ) a n d a s s e r t s t h e DEBUG s i g n a l . T h i s d e b u g s i g n a l when e n a b l e d f o r c e s a l o g i c '1' o n t o t h e m o s t s i g n i f i c a n t t h r e e b i t s of t h e a d d r e s s bus. Thus t h e i n t e r r u p t s e r v i c e r o u t i n e i s l o c a t e d a t E066H. If t h e debug is d i s a b l e d t h e i n t e r r u p t s e r v i c e r o u t i n e i s a t t h e n o r m a l a d d r e s s (0066H). To e n a b l e t h e d e b u g l i n e , i n s t a l l a j u m p e r b e t w e e n 5 8 8 - 2 a n d JB83 and b e t w e e n JB13-4A t o JB13-4B. E n s u r e t h a t t h e memory o p t i o n s t r a p p o s i t i o n t h e m o n i t o r s o f t w a r e a t EOOOH. dy-4 SYSTEMSt DDM firmware supports t h e single s t e p f a c i l i t i e s . 3.3 Memory Options T h e PAL m e m o r y d e c o d e r s h i p p e d w i t h DSTD-102 f r o m t h e f a c t o r y supports the options discussed i n the following sections. 3.3.1 n R e s t a r t Address The DSTD-102 i s c a p a b l e o f s t a r t i n g e x e c u t i o n a t e i t h e r O O O O H o r . EOOOH a f t e r r e s e t . R e s e t a d d r e s s EOOOH i s i m p l e m e n t e d i n hardware. S i n c e t h e program counter ( i n t e r n a l t o t h e 280 m i c r o p r o c e s s o r ) a l w a y s resets t o OOOOH, e x t e r n a l h a r d w a r e i s r e q u i r e d t o f o r c e t h e most s i g n i f i c a n t t h r e e b i t s o f t h e d a t a bus t o a l l o n e s t o g e t OEOOOH. A m u l t i p l e x e r a n d a l a t c h t o c o n t r o l t h e m u l t i p l e x e r a r e used t o p e r f o r m t h i s f u n c t i o n . The f i r s t i n s t r u c t i o n a t E O O O H s h o u l d b e IJMP E 0 0 3 ' t o s e t t h e p r o c e s s o r s i n t e r n a l p r o g r a m c o u n t e r t o t h e c o r r e c t memory l o c a t i o n . T h e hardware l a t c h f o r c i n g t h e address b i t must then be cleared. This i s d o n e a u t o m a t i c a l l y by t h e f i r s t 1 / 0 c y c l e t h a t t h e p r o c e s s o r p e r f o r m s . I f n o 1 / 0 p o r t a c c e s s i s n o r m a l l y m a d e t h e n a dummy 1 / 0 r e a d o f a n u n u s e d p o r t a d d r e s s m u s t b e d o n e o t h e r . w i s e memory a c c e s s e d w i l l b e c o n s t r a i n e d t o a d d r e s s e s E O O O H t h r o u g h FFFFH. To e n s u r e p r o p e r o p e r a t i o n a f t e r reset, t h e f o l l o w i n g code sequence s h o u l d b e p l a c e d i n memory a t t h e EOOOH. n USER-SELECTABLE OPTIONS EOOO C3 0 3 EO J P E003H ; jump i n s t r u c t i o n ; t o u p d a t e program counter ; r e a d u n u s e d 1/0 ; p o r t nn t o c l e a r ;reset a d d r e s s l a t c h ; first instruction ; o f u s e r program When u s i n g s t a n d a r d dy-4 SYSTEMSt o r M o s t e k s o f t w a r e ( i n c l u d i n g D D M , D C M , DDT-80, FLP-80, DOS/MDX o r MDX-DEBUG), t h e r e s e t a d d r e s s m u s t b e EOOOH. The p r o g r a m c o u n t e r a n d a d d r e s s l a t c h modification instructions previously described a r e already c o n t a i n e d w i t h t h e DDM ROM. E n s u r e t h a t p i n s 2 a n d 3 o f JB8 a r e * c o n n e c t e d when t h e MDX-SST m o d u l e i s u s e d . 3.3.2 n Memory C o n f i g u r a t i o n T h e DSTD-102 i n c o r p o r a t e s t h r e e 28 p i n s o c k e t s w h i c h c a n b e independently configured t o accept a variety of pin compatible memory d e v i c e s . T a b l e 3 1 lists each socket, its corresponding jumper block, and its a d d r e s s space for t h e s t a n d a r d c o n f i g u r a t i o n s . T h e m e m o r y d e c o d i n g i s d o n e u s i n g a PAL d e v i c e . 2 shows f o r r e f e r e n c e t h e s i g n a l s brought t o t h e jumper Table 3 b l o c k f o r e a c h o f t h e d i f f e r e n t memory t y p e s . T a b l e 3- 3 i l l u s t r a t e s t h e necessary jumper connections f o r configuring a s o c k e t t o a c c e p t e a c h memory d e v i c e . - - C o n s u l t t h e f a c t o r y f o r PAL p r o g r a m m i n g d e t a i l s f o r n o n - s t a n d a r d requirements. O p t i o n n u m b e r s a r e b i n a r y c o d e d u s i n g J B 1 4 . J B 1 4 , 1A-1B h a s a w e i g h t i n g o f ' 1 ' ; J B 1 4 , 2A-2B h a s a w e i g h t i n g o f ' 2 l a n d J B 1 4 , 3A-3B h a s a w e i g h t i n g o f '4'. F o r e x a m p l e , i f o p t i o n 5 ( 1 0 1 i s d e s i r e d J B 1 4 , 1A-1B, 3A-3B a r e l e f t o p e n a n d J B 1 4 , 2A-2E a r e inserted. USER-SELECTABLE OPTIONS n DSTD-102 TABLE 3 - 1 MEMORY SOCKET/JUMPER BLOCK ASSIGNMENT MEM TYPE OPTION MEM RANGE U20(JB11) U19(JB10) U18(JB9) 2K 2K 4K 4K 7(111) 6(110) 5(101) 4(100) 2(010) O(000) E000-FFFF 0000-1FFF E000-FFFF 0000-3FFF 0000-7FFF 0000-BFFF E000-E7FF 0000-07FF E000-EFFF 0000-OFFF 0000-1FFF 0000-3FFF E800-EFFF 0800-OFFF F000-FBFF 1000-1FFF 2000-3FFF 4000-7FFF F000-FFFF 1000-1FFFc FCOO-FFFF 2000-3FFF4000-7FFF 8000-BFFF 8K 16K NOTE: F o r 2K, 4K a n d 8K d e v i c e s t h e memory r a n g e f o r U18 i s t w i c e a s l a r g e a s f o r U19 a n d U20. H e n c e when u s i n g t h e s a m e memory d e v i c e s i z e s f o r a l l t h r e e s o c k e t s , memory e x p a n s i o n o f f board w i l l n o t be contiguous. O p t i o n 5 i s t h e memory c o n f i g u r a t i o n u s e d f o r t h e b o o t p r o m s and m o n i t o r i n d y - 4 ' s STD B u s b a s e d m i c r o c o m p u t e r d e v e l o p m e n t systems. TABLE 3 - 2 MEMORY D E V I C E JUMPER STRAPS TYPE PART NO. 27 26 PINS 23 21 1 Vcc Vpp GND - vcc vpp vcc VCC Vpp A10 Vcc All A10 - 4Kx8 EPROM - 8Kx8 EPROM PGM n/c All A10 Vpp 16Kx8 EPROM PCM A13 All A10 Vpp VCC /WE CND - VCC /WE A10 - 1Kx8 EPROM 1Kx8 EPROM 2Kx8 EPROM 2758 2Kx8 RAM - 8Kx8 RAM /WEJ n/c AI 1 J AIOJ - VCC /WE A10 1Kx8 RAM 2Kx8 EEROM 0 RDY~ - n USER-SELECTABLE DSTD- 1 0 2 OPTIONS TABLE 3 - 3 MEMORY DEVICE JUMPER STRAPS TYPE PART NO. JUMPER BLOCKS J B 9 a n d 5812 JUMPER BLOCK JB10 1 K x 8 EPROM 2758 B2-A6 B3-B4 ; A5-A6 A2-B4 C1-C2 ; B3-B4 1 K x 8 EPROM 2759 B2-A6 B3-B2 ; A5-A6 A2-B4 C1 -B3 ; B3-B4 2 K x 8 EPROM 2716 B2-A6 B3-A3 ; A5-A6 A2-B4 B1-C1 ; B3-B4 4 K x 8 EPROM 2732 B2-A6 B3-A3 ; A4-A5 A2-B4 B1-C1 ; B3-B2 8 K x 8 EPROM 2764 B1-B5 B3-A3 ; A4-A5 ; A1-A6 A3-C3 B1-C1 ; B2-B3 ; A4-B4 1 6 K x 8 EPROM 27128 B1-B5 B3-A3 B2-B6 ; A4-A5 ; A1-A6 A3-C3 B1-C1 C4-A2 ; B2-B3 ; A4-B4 n 1 K x 8 RAM . 4801 B2-A6 B3-A6 ; A5-B5 A2-B4 C1-C2 ; B3-C3 2 K x 8 RAM 4802 B2-A6 B3-A3 ; A5-B5 A2-B4 B1-C1 ; B3-C3 8 K x 8 RAM 2 1 86 B1-B5 B3-A3 ; A4-A5 ; A1-A2 A3-C3 B1-C1 ; B2-B3 ; A1-A4 2 K x 8 EEROM X2816A B2-A6 B3-A3 ; A5-B5 A2-B4 B1-C1 ; B3-C3 USER-SELECTABLE OPTIONS n 3.3.3 DSTD-102 On-board Memory D i s a b l e L a t c h A l l o n - b o a r d memory c a n b e e n a b l e d a n d d i s a b l e d u n d e r s o f t w a r e control. To u s e t h i s f e a t u r e j u m p e r J B 1 4 4A-4B i s i n s t a l l e d . T h i s j u m p e r a l l o w s t h e memory d i s a b l e l a t c h t o b e u s e d . The l a t c h i s l o c a t e d a t a d d r e s s 7BH. W r i t i n g a ' 0 ' t o t h i s l a t c h e n a b l e s o n - b o a r d memory. W r i t i n g a '1' t o t h e l a t c h d i s a b l e s onb o a r d memory. A power-up o r RESET c l e a r s t h e l a t c h t h u s e n a b l i n g o n - b o a r d memory. WAIT S t a t e Generator 3.4 T h r e e j u m p e r s a r e p r o v i d e d t o a l l o w t h e u s e o f s l o w memory d e v i c e s . T h e f i r s t j u m p e r g e n e r a t e s a WAIT s t a t e o n a l l m e m o r y cycles. The s e c o n d j u m p e r g e n e r a t e s a WAIT s t a t e f o r MI memory c y c l e s only. Table 3 4 l i s t s t h e a c c e s s t i m e s o f memory d e v i c e s i n t e r n a l and e x t e r n a l t o t h e c a r d f o r t h e two d i f f e r e n t m e m o r y c y c l e t y p e s f o r b o t h t h e 2.5 MHz a n d 4.0 MHz DSTD 1 0 2 cards. T h e t h i r d j u m p e r g e n e r a t e s a WAIT s t a t e o n i n t e r n a l memory a c c e s s e s o n l y . T h i s m e a n s t h a t s l o w e r EPROMS c a n b e u s e d A fourth o n t h e DSTD-102 a l o n g w i t h a h i g h s p e e d RAM c a r d . j u m p e r a l l o w s t h e g e n e r a t i o n o f a WAIT s t a t e o n i n t e r r u p t 5 gives the connections for the acknowledge cycles. Table 3 WAIT s t a t e o p t i o n s . - n - TABLE 3 - 4A MI-MEMORY CYCLE WAIT STATES TIMING 2.5MHZ FUNCTION JB11 Connections INTERNAL MI Other MI EXTERNAL Other . 620 950 No WAIT s t a t e s WAIT s t a t e s on MI cycles WAIT s t a t e s on a l l memory c y c l e s 3A t o 3B 1180 1150 ( i n nanoseconds) USER-SELECTABLE OPTIONS n TABLE 3 MI-MEMORY - 4B CYCLE W A I T STATES T I M I N G 4.0MHZ JBll Connections INTERNAL MI Other EXTERNAL MI Other --- 330 455 300 425 WAIT s t a t e s on MI cycle 1A t o 1B 590 455 560 425 WAIT s t a t e s on a l l memory c y c l - e s 3A t o 3B 590 705 560 675 No W A I T s t a t e s b TABLE 3 ( i n nanoseconds) - 5 WAIT STATE OPTIONS OPTION 3.5 JB11 No W A I T s t a t e s No Jumpers A l l MI c y c l e s 1A t o 1 B A l l Memory c y c l e s 3A t o 3B I n t e r n a l Memory c y c l e s only 4A t o 4 B I n t e r n a l Memory c y c l e s and e x t e r n a l MI c y c l e s 4 A t o 4B 1 A t o 1B I n t e r r u p t acknowledge c y c l e 2A t o 2B Counter/Timer O p t i o n s The f o u r C o u n t e r / T i m e r c h a n n e l s may be c a s c a d e d f o r e x t e n d e d c o u n t i n g and t i m e r f u n c t i o n s . Appendix A-6 shows t h e jumper p i n n u m b e r s f o r t h e C T C . R e f e r t o t h e MK3882 T e c h n i c a l Manual o r t h e Z i l o g Data Book f o r a c o m p l e t e d e s c r i p t i o n of t h e CTC o p e r a t i o n . P r o v i s i o n i s made on t h e Counter/Timer o p t i o n block t o e n a b l e t h e N M I i n p u t of t h e p r o c e s s o r t o be connected t o one of t h e o u t p u t s o f t h e C T C . N M I i s p i n 5A o f JB5. USER-SELECTABLE OPTIONS DSTD- 102 9 f-i I n a d d i t i o n t h e CTC c a n b e u s e d a s a b a u d r a t e g e n e r a t o r f o r t h e s e r i a l c h a n n e l s t o c r e a t e n o n - s t a n d a r d baud r a t e s . Two commonly unused p i n s on t h e STD b u s (MEMEX and IOEXP) m a y b e c o n n e c t e d t h r o u g h J B 1 3 a n d b u f f e r s t o t h e CTC. One p i n i s u s e d a s a n i n p u t (IOEXP) and t h e o t h e r i s u s e d a s an o u t p u t ( M E M E X ) . 3.6 S e r i a l Channel O p t i o n s 3.6.1 Baud R a t e G e n e r a t o r T h e DSTD-102 h a s a d u a l s o f t w a r e - p r o g r a m m a b l e b a u d r a t e g e n e r a t o r . I t i s a c c e s s e d t h r o u g h 1 / 0 p o r t 7AH. T h i s p o r t i s a w r i t e - o n l y p o r t . B i t s 0 t o 3 c o n t r o l c h a n n e l A and b i t s 4 t o 7 Table 3 7 shows t h e p r o g r a m m i n g i n f o r m a t i o n c o n t r o l c h a n n e l B. f o r t h e baud r a t e g e n e r a t o r . - Table 3 - 6 Baud R a t e G e n e r a t o r Programming BAUD RATE D3/D7 D2/D6 D1/D5 DO/D4 (HEX 1 Thus t o s e t p o r t A t o 9600 baud and p o r t B t o 1200 baud o u t p u t a 7EH t o 1 / 0 a d d r e s s 7AH. USER-SELECTABLE OPTIONS n 3.6.2 DTE/DCE C o n f i g u r a t i o n s 3.6.2.1 DCE Configuration When c o n n e c t i n g t o a C R T , p r i n t e r o r s i m i l a r equipment t h e s e r i a l p o r t i s w i r e d a s Data C o m u n i c a t i o n s Equipment. The s i g n a l names Table i n d i c a t e c o n t r o l and d a t a f l o w ]dmr e s ~ e c t thew. 3 7 i t e m i z e s t h e j u m p e r c o n f i g u r a t i o n s f o r t h i s inode o f operation. - TABLE 3 -7 RS-232C DCE Jumper C o n f i g u r a t i o n b EIA(DCE1 S i g n a l Name TX RX RTS CTS DTR DCD DSR SIO Function RX TX CTS RTS DCD DTR +12V (2) (3) (4) (5) (20) (8) (6) I n s t a l l e d Jumpers JB3#JB4 to to to to to to to 2B 1A 4A 5B 7A 6A 8A 1B 2A 5A 4B 6B 7B 8B 52/53 P i n Numbers 3 4 5 9 8 6 (JB3 o n l y ) DTE C o n f i g u r a t i o n 3.6.2.2 When c o n n e c t i n g t o a MODEM o r s i m i l a r equipment t h e s e r i a l p o r t i s w i r e d a s Data T e r m i n a l Equipment. The s i g n a l names i n d i c a t e 8 c o n t r o l and d a t a f l o w w i t h r e s ~ e c t PSTD-102. Table 3 i t e m i z e s t h e jumper c o n f i g u r a t i o n f o r t h e mode o f o p e r a t i o n . - TABLE 3 -8 RS-232C DTE Jumper C o n f i g u r a t i o n EIA(DTE1 S i g n a l Name TX RX RTS CTS DTR DCD DSR (2) (3) (4) (5) (20) (8) (6) SIO Function I n s t a l l e d Jumpers JB3,JB4 TX RX RTS CTS DTR DCD 1A 2B 3A 4A 6A 7A to to to to to to ------ 1B 2A 3B 4B 6B 7B 52/53 P i n Numbers USER-SELECTABLE OPTIONS DSTD-102 (7 3.6.3 Synchronous Operation The DSTD-102A a l l o w s s y n c h r o n o u s o p e r a t i o n on C h a n n e l A. T h a t i s , a d d i t i o n a l RS-232C d r i v e r s a n d r e c e i v e r s a r e p r o v i d e d f o r interfacing external clocks. Two c o n f i g u r a t i o n s a r e p o s s i b l e . The D C E p r o v i d e s b o t h t r a n s m i t and r e c e i v e t i m i n g information. When t h e DSTD-102A i s t h e D C E , t w o RS-232C d r i v e r s a r e r e q u i r e d . When t h e DSTD-102A i s t h e DTE t w o RS-232C r e c e i v e r s a r e r e q u i r e d . i) The D C E p r o v i d e s t h e t r a n s m i t t i m i n g i n f o r m a t i o n and t h e DTE p r o v i d e s t h e r e c e i v e t i m i n g i n f o r m a t i o n . The DSTD-102A p r o v i d e s t h e r e c e i v e t i m i n g i n f o r m a t i o n . The DSTD-102 u s e s b o t h t h e RS-232C d r i v e r and t h e RS-232C receiver. ii) - 9 shows t h e j u m p e r i n g r e q u i r e d f o r e a c h c o n f i g u r a t i o n . Table 3 Note t h a t t h e same d r i v e r s used f o r t h e e x t e r n a l c l o c k s a r e a l s o u s e d t o d r i v e t h e o n - b o a r d TX a n d R X L E D t s . When t h e s e d r i v e r s a r e t o be used f o r e x t e r n a l clocking t h e LEDts should be disconnected. TABLE 3 DCE provides both clocks. -9 DSTD-102A i s t h e DCE JB2 TX Clock 2A 1A RX Clock 3A 4A JB3 - - 2B 2A - 4A 4B DCE p r o v i d e s both c l o c k s . 52 EIA 9A - 9B 10 15 11A - 11B 11 17 DSTD-102A i s t h e DTE JB2 JB3 52 EIA 11 17 TX Clock RX Clock - 3B 3A 10A - 10B DTE p r o v i d e s t h e t r a n s m i t c l o c k . receive clock. DSTD-102A i s DCE. JB2 TX Clock RX Clock 1A 2A 3A - DCE provides t h e JB3 2A 2B 3B 10A 9A 52 EIA 9B 10 24 10B 11 17 n USER-SELECTABLE OPTIONS DSTD-102 DTE p r o v i d e s t h e t r a n s m i t c l o c k , r e c e i v e c l o c k . DSTD-102A i s DTE. JB2 RX C l o c k 1A TX C l o c k 2A 4A - DCE p r o v i d e s t h e JB3 1B 8A - 3A 4B 11A - 52 EIA 8B 10 24 11B 11 17 Note t h a t t h e c l o c k names g i v e n above refer t o d a t a f l o w w i t h r e s p e c t t o t h e DTE. EIA r e f e r s t o t h e DB25 p i n n u m b e r s a s s i g n e d t o t h e s e s i g n a l s by t h e EIA RS-232C s p e c i f i c a t i o n s . T a b l e 3-10 s h o w s t h e c a b l e c o n n e c t i o n s t o a s t a n d a r d RS-232C 'DB25S c o n n e c t o r . T y p i c a l l y t h e c a b l e i s t h e s a m e f o r b o t h DCE a n d DTE s y s t e m s w i t h t h e c o n f i g u r a t i o n b e i n g d e t e r m i n e d b y t h e o n based jumpers. TABLE 3-10 SERIAL CABLE CONNECTIONS 52/53 RS232C/DB25S EIA CIRCUIT P i n 12 (DB25S p i n 19) i s i n c l u d e d t o a c c o m o d a t e s o m e NOTE: p r i n t e r s t h a t u s e p i n 19 f o r f l o w c o n t r o l . SPECIFICATIONS n SECTION 4 SPECIFICATIONS Functional Specifications Word S i z e Instructions: 8, 1 6 , 24, o r 32 b i t s Data: 8 bits C y c l e Time A 4.1.3 C l o c k p e r i o d (T s t a t e ) : 4 0 0 n s f o r DSTD-102-2.5 2 5 0 n s f o r DSTD-102-4.0 I n s t r u c t i o n Cycle: Min. 4 T s t a t e s Max. 2 3 T s t a t e s Memory C a p a c i t y T h r e e 2 8 p i n s o c k e t s a r e p r o v i d e d w h i c h may b e p o p u l a t e d w i t h a n y m i x t u r e of t h e f o l l o w i n g d e v i c e s : 2 7 5 8 ( 1 K x 8 EPROM) 2 7 5 9 (1K x 8 EPROM) 2 7 1 6 (2K x 8 EPROM) 2 7 3 2 (4K x 8 EPROM) 2 7 6 4 (8K x 8 EPROM) 27128(16Kx 8 EPROM) MK 3 4 0 0 0 (2K x 8 EPROM) 4 1 1 8 (1K x 8 S t a t i c R A M ) 4801 (1K x 8 S t a t i c R A M ) 4 8 0 2 (2K x 8 S t a t i c R A M ) 2 1 8 6 (8K X 8 P s e u d o S t a t i c R A M ) X2816 (2K x 8 EEROM 4.1.4 f-7 Memory A c c e s s T i m e T h e t i m e r e q u i r e d t o a c c e s s o n - b o a r d m e m o r y by e x t e r n a l D M A c o n t r o l l e r s i s 1 0 0 n s p l u s t h e a c c e s s time o f t h e memory d e v i c e . T h i s is d e f i n e d a s t h e time i n t e r v a l between t h e time t h a t t h e m e m o r y a d d r e s s i s v a l i d o n t h e STD-BUS a n d t h e t i m e t h a t t h e o u t p u t d a t a i s v a l i d on t h e STD-BUS. n SPECIFICATIONS 4.1.5 1/0 Addressing The o n - b o a r d addresses: 1/0 addressing is hard wired t o t h e following p o r t PORT ADDRESS BAUD RATE GENERATOR ON-BOARD DISABLE LATCH f CTC CH 0 ' CTC r SIO SIO SIO 4.1.6 CH CH CH CH CH 3 A A B B DATA CONTROL DATA CONTROL 1/0 Capacity The 280 CPU u t i l i z e s t h e l o w e r 8 b i t s o f i t s a d d r e s s b u s f o r I / O addressing t o y i e l d a t o t a l o f 256 p o s s i b l e p o r t addresses. n 4.1.7 Interrupts T h e CPU may b e p r o g r a m m e d t o p r o c e s s i n t e r r u p t s i n a n y o f t h r e e d i f f e r e n t modes (mode 0, 1, o r 2 a s d e s c r i b e d i n any 280 T e c h n i c a l Manual). Mode 2 o p e r a t i o n ( v e c t o r e d i n t e r r u p t s ) i s by f a r t h e m o s t p o w e r f u l a n d i s c o m p a t i b l e w i t h dy-4 DSTD a n d MOSTEK MDX S e r i e s c a r d s . M u l t i - l e v e l i n t e r r u p t p r o c e s s i n g i s a l s o p o s s i b l e w i t h t h e Z80 CPU. T h e l e v e l o f s t a c k i n g i s l i m i t e d o n l y b y a v a i l a b l e m e m o r y space. The DSTD-102 w i l l a l s o a c c e p t n o n - m a s k a b l e a r e s t a r t a t l o c a t i o n 0066H. 4.1.8 System Clock Electrical Specification i n t e r r u p t s which f o r c e SPECIFICATIONS n 4.2.1 4.2.2 4.2.3 STD B u s I n t e r f a c e Bus I n p u t s : One 74LS l o a d max. Bus O u t p u t s : IOL= 2 4 mA min. e VOL = 0 . 5 V o l t s IOH= 1 5 mA m i n . @ VOH = 2 . 4 V o l t s Serial Ports Inputs: One 74LS l o a d max. Outputs: +/- 12V C u r r e n t L i m i t e d t o 10mA Operating Temperature 0 Degrees C t o 50 Degrees C 95% humidity non-condensing 4.2.4 Power Supply R e q u i r e m e n t s +5V +/- 5 % @ 1.2A +12V +/- 5 % @ 0.1A -12V +/- 5 % @ 0.1A ( e x c l u d i n g memory p o w e r r e q u i r e m e n t s ) Mechanical S p e c i f i c a t i o n s Card Dimensions 4.50 i n . long ( 1 1 . 4 3 cm.) w i d e by 6 . 5 0 i n . 0.48 i n . ( 1 . 2 2 c m . ) maximum h e i g h t 0.062 i n . thickness 4.3.2 (0.16 cm.) printed circuit STD B u s Edge C o n n e c t o r 56 p i n Dual Readout; 0.125 i n . c e n t e r s Mating Connector V i k i n g 3VH28/1CE5 V i k i n g 3VH28/1CND5 V i k i n g 3VH28/1CN5 ( 1 6 . 5 1 cm) (printed circuit) (wire wrap) (solder lug) board . SPECIFICATIONS (7 4.3.3 S e r i a l P o r t Connector 12 P i n Dual Readout; 0.100 i n c h g r i d Mating Connector Amp 87631-8 (housing) Amp 86016-2 (contact) or equivalent SPECIFICATIONS 77 SECTION 5 5.0 FACTORY N O T I C E S 5.1 Factory R e p a i r Service In t h e event t h a t d i f f i c u l t y is encountered with t h i s unit, it may b e r e t u r n e d d i r e c t l y t o d y - 4 f o r r e p a i r . T h i s s e r v i c e w i l l be provided free of charge i f t h e u n i t is returned w i t h i n t h e warranty period. However, u n i t s which have been m o d i f i e d o r a b u s e d i n a n y way w i l l n o t b e a c c e p t e d f o r s e r v i c e , o r w i l l b e r e p a i r e d a t t h e owner's expense. When r e t u r n i n g a c i r c u i t b o a r d , p l a c e i t i n s i d e t h e c o n d u c t i v e p l a s t i c b a g i n w h i c h i t w a s d e l i v e r e d t o p r o t e c t t h e MOS d e v i c e s f r o m e l e c t r o s t a t i c d i s c h a r g e . T H E C I R C U I T BOARD M U S T N E V E R B E Enclose a l e t t e r PLACED I N CONTACT W I T H STYROFOAM MATERIAL, containing the following information with the returned c i r c u i t board: Name, a d d r e s s a n d p h o n e number o f p u r c h a s e r Date and p l a c e o f p u r c h a s e Brief description of the difficulty M a i l a c o p y o f t h i s l e t t e r SEPARATELY t o : S e r v i c e Department dy-4 SYSTEMS I N C . 888 Lady E l l e n P l a c e , Ottawa, Ontario K1Z 5M1, Canada or S e r v i c e Department dy-4 SYSTEMS I N C . , 3582 D u b a r r y Rd. I n d i a n a p o l i s , I N 46226 S e c u r e l y package and m a i l t h e c i r c u i t board, p r e p a i d and i n s u r e d , t o t h e same a d d r e s s . 5.2 Limited Warranty dy-4 w a r r a n t s t h i s p r o d u c t a g a i n s t d e f e c t i v e m a t e r i a l s a n d w o r k m a n s h i p f o r a p e r i o d o f 90 d a y s . This warranty does not apply t o any p r o d u c t t h a t h a s been s u b j e c t e d t o m i s u s e , a c c i d e n t , improper i n s t a l l a t i o n , improper application, o r improper operati o n , n o r d o e s it a p p l y t o any p r o d u c t t h a t h a s been r e p a i r e d o r a l t e r e d by o t h e r t h a n a n a u t h o r i z e d f a c t o r y r e p r e s e n t a t i v e . There a r e no w a r r a n t i e s which e x t e n d beyond t h o s e h e r e i n s p e c i f i c a l l y given. NOTICE r l T h e a n t i s t a t i c b a g i s p r o v i d e d f o r s h i p m e n t o f t h e d y - 4 PC b o a r d s t o prevent damage t o t h e components due t o e l e c t r o s t a t i c discharge. F a i l u r e t o use t h i s bag i n shipment w i l l VOID t h e warranty. FACTORY N O T I C E S n APPENDIX A OPTION PROGRAMMING SUMMARY OPTION P R O G R A M M I N G SUMMARY n APPENDIX A O P T I O N PROCRAHHING SUMHARY -1 OPTIONAL JUMPER BLOCKS The f o l l o w i n g i s a l i s t o f t h e o p t i o n J u m p e r B l o c k s on t h e STD102 c a r d . 8 - 2 JB 1 LED c o n n e c t i o n JB2 S e r i a l Channel A Clock TTL S i d e JB3 S e r i a l Channel A DTE/DCE C o n f i g u r a t i o n Block JB4 S e r i a l Channel B DTE/DCE C o n f i g u r a t i o n Block JB5 Counter Timer Jumper Block JB6 LED T r a n s m i t JB7 LED Receive JB8 R e s t a r t Address Jumper Block JB9 Memory Socket C o n f i g u r a t i o n Block f o r ~ 1 ' 8 JB10 Memory S o c k e t C o n f i g u r a t i o n Block f o r U19 JB11 WAIT S t a t e G e n e r a t o r o p t i o n s JB12 Memory S o c k e t C o n f i g u r a t i o n Block o f U20 JB13 CTC/Bus I n t e r f a c e Jumper Block JB 14 On-board Memory O p t i o n s JB15 Reset Mode LED C o n n e c t i o n s ( J B 1 ) These jumpers a r e i n s t a l l e d t o d r i v e t h e LED'S. Note t h e jumpers s h o u l d n o t be i n s t a l l e d i f S e r i a l Channel A i s used i n synchronous mode and i s s u p p l y i n g t h e c l o c k s t o e x t e r n a l equipment. Driver 1 1 o---- o LED 1 Driver 2 2 o---- o LED 2 ---- I n d i c a t e s Factory Default n OPTION P R O G R A M M I N G SUMMARY A - 3 DSTD-102 S e r i a l Channel A C l o c k Jumpers TTL S i d e ( J B 2 ) T h i s jumper b l o c k a l l o w s t h e s e l e c t i o n o f t h e T r a n s m i t and r e c e i v e c l o c k s f o r Channel A. T r a n s m i t Clock ( i n p u t ) l o RS232 Clock Receiver 1 2 o I o I n t e r n a l Baud Rate G e n e r a t o r o RS232 Clock T r a n s m i t t e r 1 Receiver Clock ( i n p u t ) 3 0 0 RS232 Clock R e c e i v e r 2 I n t e r n a l Baud Rate G e n e r a t o r 4 o o RS232 Clock T r a n s m i t t e r 2 R e c e i v e r Clock ( i n p u t ) 5 0 0 CTC o u t p u t T r a n s m i t Clock ( i n p u t ) 6 o o CTC o u t p u t I OPTION PROGRAMMING SUMMARY DSTD-102 (1 A - 4 Channel A DTE/DCE C o n f i g u r a t i o n Block (JB3) These jumpers a l l o w t h e board t o be c o n f i g u r e d a s Data T e r m i n a l E q u i p m e n t o r D a t a C o m m u n i c a t i o n s E q u i p m e n t when u s e d w i t h a s t a n d a r d dy-4 SYSTEMS C a b l e . The s i g n a l s g i v e n a r e t h o s e o f t h e SIO d e v i c e whi c h i s l a b e l l e d a s Data T e r m i n a l Equipment. T r a n s m i t Data l o o I I Connector 52 P i n 2 Connector 52 P i n 3 2 0 0 Received Data Request t o S e n t (RTS) 3 0 0 Connector 52 P i n 4 I C l e a r t o Send (CTS) 4 0 0 Connector 52 P i n 5 Connector 52 P i n 4 5 0 0 Request t o Send (RTS) Data Terminal Ready ( D T R ) 6 o o Connector 52 P i n 9 Data C a r r i e r D e t e c t ( D C D ) 7 o o Connector 52 P i n 8 RS-232C R e c e i v e r 1 8 0 0 Connector 52 P i n 10 RS-232C T r a n s m i t 1 9 0 0 Connector 52 P i n 10 RS-232C R e c e i v e r 2 10 o o Connector 52 P i n 11 RS-232C T r a n s m i t 2 11 o o Connector 52 P i n 11 +12 t h r o u g h 3 k ohms 12 0--0 Connector 52 P i n 6 n OPTION PROGRAMMING SUMMARY A - 5 C h a n n e l B DTE/DCE C o n f i g u r a t i o n B l o c k (JB4) T h i s jumper b l o c k a l l o w s t h e c h a n n e l t o be c o n f i g u r e d a s Data T e r m i n a l Equipment o r D a t a C o m m u n i c a t i o n s Equipment. T r a n s m i t Data ("\ l o I o I 0 Received Data Connector 52 Pin 3 2 0 R e q u e s t t o S e n t (RTS) 3 0 Connector 52 Pin 2 0 k Connector 52 Pin 4 l 0 0 Connector 52 Pin 5 C l e a r t o Send (CTS) 4 Connector 52 P i n 4 5 I b D a t a T e r m i n a l Ready (DTR) 6 o D a t a C a r r i e r Detect ( D C D ) 7 0-0 Connector 52 Pin 8 +12 t h r o u g h 3k ohms 8 0--0 Connector 52 Pin 6 A - 6 ! o R e q u e s t t o Send (RTS) Connector 52 Pin 9 -0 C o u n t e r T i m e r J u m p e r B l o c k (JB5) T h i s jumper block a l l o w s t h e c o u n t e r / t i m e r c h a n n e l s t o be casIt a l s o provides access t o the caded f o r longer sequences. a u x i l i a r y i n p u t and o u t p u t b u f f e r s which a r e connected through JB12 t o MEMEX and IOEXP b u s s i g n a l s . The SIO c l o c k i s used when t h e CRT i s u s e d a s a baud r a t e g e n e r a t o r . Auxiliary Input l o o SIO Clock CTC Channel 0 i n p u t 2 0 0 C T C Channel 0 z e r o d e t e c t CTC Channel 1 Z e r o d e t e c t 3 0 0 CTC Channel 1 i n p u t CTC Channel 2 i n p u t 4 0 0 CTC Channel 2 z e r o d e t e c t I n t e r n a l Non-Maskable I n t e r r u p t 5 o o A u x i l i a r y Output CTC Channel 3 i n p u t 0 0 N/C 6 OPTION PROGRAMMING SUMMARY DSTD-102 JB6/7 LED B l o c k s A - 7 T h e s e j u m p e r s a r e i n s t a l l e d t o d r i v e t h e L E D s . They s h o u l d b e removed when Channel A i s o p e r a t e d i n Synchronous mode. TX Driver 0-00 LED D r i v e r U7 (JB6) RX Driver 0--0 LED D r i v e r U6 (JB7) A - 8 Restart A d d r e s s Jumper B l o c k JB8 I n s t a l l i n g t h e j u m p e r b e t w e e n p i n s 2 and 3 f o r c e s t h e r e s t a r t I n s t a l l i n g t h e jumper between p i n s 1 and 2 a d d r e s s t o EOOOH. f o r c e s a r e s t a r t a d d r e s s t o 0000H. 1 o F o r c e OOOOH I o I o 2 3 Restart address control F o r c e EOOOH Memory S o c k e t C o n f i g u r a t i o n B l o c k s JB9, JB12 11-9 P I 4' 1 B 0 0 1 I B o I o o A 0 0 0I I 0 O O i o or o - ~ I A 0 0 o 0 o o 0--0-l l I f o r s o c k e t U20 (2K EPROM) f o r s o c k e t U18 (1K RAM) A1 Socket P i n 1 ( p s t a t i c RAM ready/Vpp) B1 S o c k e t P i n 27 (Pseudo s t a t i c RAM A2 Processor wait l o g i c B2 S o c k e t P i n 26 (Vcc/A13) /WE) n OPTION PROGRAMMING SUMMARY A - 10 DSTD-102 A3 P r o c e s s o r Address B i t A10 B3 Socket Pin 21 A4 P r o c e s s o r Address Pin All B4 Ground A5 Socket P i n 23 85 Processor Write Strobe A6 +5V 86 P r o c e s s o r Address B i t 13 (AlO/L) (All/WE/Vpp) Hemory Socket Configuration Block JB10 C 0 0 0 0 o o--0-l I I B , o ( f o r s o c k e t U19) I I A o o o 0 1 I I --------. A1 Processor wait l o g i c A2 Socket P i n 26 (Vcc/A13) A3 Socket Pin 27 (Pseudo s t a t i c RAM A4 Socket Pin 1 ( p s t a t i c RAM ready/Vpp) B1 P r o c e s s o r Address B i t A10 B2 P r o c e s s o r Address P i n All B3 Socket Pin 23 B4 +5V C1 Socket P i n 21 C2 Ground C3 Processor Write Strobe C4 P r o c e s s o r Address B i t 13 (All/WE/Vpp) (AlO/L) /WE) OPTION PROGRAMMING SUMMARY (7 A A n - 11 DSTD-102 Wait S t a t e G e n e r a t o r C o n f i g u r a t i o n B l o c k J B l l - 12 A1 ,B1 W a i t on MI c y c l e s A2,B2 W a i t on I n t e r r u p t Acknowledge c y c l e s A 3 , B3 W a i t on MREQ c y c l e s A4,B4 W a i t on On-board Memory C y c l e s CTC/BUS I n t e r f a c e ( J B 1 3 ) T h e s e j u m p e r s a r e i n s t a l l e d t o a l l o w c o u n t e r / t i m e r 1/0 t o b e accessed using two l i n e s o f t h e backplane t h a t a r e n o t normally u s e d by t h e 2 8 0 STD b u s c a r d s . T h e s e s i g n a l s u s e t h e BUS l i n e s n o r m a l l y r e f e r r e d t o a s MEMEX a n d IOEXP. T h i s j u m p e r b l o c k a l s o c o n t a i n s t h e Debug f u n c t i o n e n a b l e j u m p e r . A - 13 MEMEX ( 5 1-36 1 o o CTC O u t p u t Ground o o Ground CTC I n p u t o o IOEXP ( 5 1-35 1 DEBUG (51-381 0--0 debug f / f On B o a r d Hemory O p t i o n s ( J B 1 4 ) Memory o p t i o n w e i g h t ' I t r ' 2 I t a n d ' 4 ' s e l e c t s t h e m e m o r y c o n f i g u r a t i o n f o r t h e DSTD-102. T h i s j u m p e r b l o c k i s u , s e d i n a b i n a r y c o d e d f a s h i o n . S e e s e c t i o n 3.3.2 f o r d e t a i l s . - 4B h a s t o To u s e t h e o n - b o a r d memory d i s a b l e f e a t u r e j u m p e r 4A be i n s t a l l e d . P o r t 7B c a n t h e n b e u s e d t o c o n t r o l t h e memory. n OPTION PROGRAMMING SUMMARY Ground Memory O p t i o n 1 Weight '1' 1 o--o Memory O p t i o n 2 Weight '2' 2 0 0 Ground Memory O p t i o n 3 Weight ' 4 ' 3 0 0 Ground 4 of-o DSMEN L a t c h I n p u t A - 14 DSMEN O p t i o n O u t p u t Reset node (JB15) J u m p e r J B 1 5 i s u s e d t o s e l e c t t h e p u s h b u t t o n r e s e t mode. T h e push b u t t o n l o g i c i s edge s e n s i t i v e i f t h e jumper i s o m i t t e d and is l e v e l s e n s i t i v e i f it i s i n s t a l l e d . Push Button I n p u t A- 15 0 11 o o Reset ' ~ o g i c Programming The CTC Channel S e l e c t i o n DSTD p r o d u c t s u s i n g t h e 2 8 0 CTC d e c o d e t h e CTC t o o c c u p y 4 contiguous p o r t addresses. Writing t o t h e appropriate port a d d r e s s w i l l a u t o m a t i c a l l y select t h e c o r r e c t r e g i s t e r i n t h e CTC. 2) Interrupt Vectors I f a n y o n e o f t h e CTC c h a n n e l s i s g o i n g t o b e u s e d w i t h i t s i n t e r r u p t enabled. an I n t e r r u p t Vector must be w r i t t e n t o t h e CTC. T h e u s e r n e e d o n l y s u p p l y t h e 5 h i g h b i t s o f o n e v e c t o r a s t h e CTC a s s u m e s t h e v e c t o r p o i n t s t o 4 c o n t i g u o u s b y t e p a i r s c o r r e s p o n d i n g t o t h e 4 c h a n n e l s . N o t e t h a t DO m u s t e q u a l 0 t o i n d i c t e t h a t t h e word b e i n g w r i t t e n t o t h e CTC i s a n i n t e r r u p t v e c t o r ; t h i s a l s o r e q u i r e s v e c t o r e d a d d r e s s e s t o s t a r t a t a n e v e n memory l o c a t i o n . D7 V7 D3 D5 D4 D6 V3 V5 V4 V6D2 Dl X X DO 0 O P T I O N PROGRAMMING SUMMARY DSTD-102 (1 3) Channel C o n t r o l R e g i s t e r The c o n t r o l r e g i s t e r b i t f u n c t i o n s a r e a s i l l u s t r a t e d b e l o w . D7 INT ENA D6 MODE D5 RANGE D4 SLOPE D3 TRIG D2 LOAD TC D1 DO RESET 1 DO = 0 i n d i c a t e s t h e b y t e i s a n I N T E R R U P T VECTOR. DO = 1 i n d i c a t e s t h e b y t e i s a CONTROL WORD. D l = 0 t h e channel continues c u r r e n t operation. D l = 1 t h e c h a n n e l i s i m m e d i a t e l y R E S E T t o c o n t r o l word v a l u e s . D 2 = 0 i n d i c a t e s NO T I M E CONSTANT t o f o l l o w . D 2 = 1 t h e n e x t 1 / 0 b y t e w i l l b e a T I M E CONSTANT. D3 D3 ( 1 t o 256) = 0 timer w i l l FREE-RUN s t a r t i n g on n e x t p r o c e s s o r c y c l e . = 1 i n d i c a t e s timer w i l l s t a r t on E X T E R N A L T R I G G E R . D 4 = 0 i n d i c a t e s e x t e r n a l t r i g g e r on N E G A T I V E - G O I N G D 4 = 1 i n d i c a t e s ' e x t e r n a l t r i g g e r on P O S I T I V E - G O I N G edge. edge. D5 D5 = 0 i n d i c a t e s p r e s c a l e r f a c t o r o f 16. (timer mode o n l y ) = 1 i n d i c a t e s p r e s c a l e r f a c t o r o f 256. (timer mode o n l y ) D6 D6 = 0 i n d i c a t e s T I M E R mode. ( p r e s c a l e r i s e n a b l e d ) = 1 i n i d c a t e s COUNTER mode. ( p r e s c a l e r d i s a b l e d ) D7 = 0 INTERRUPT DISABLED f o r t h a t channel. D 7 = 1 I N T E R R U P T on z e r o c o u n t ENABLED f o r t h e c h a n n e l . APPENDIX B STD-280 BUS P I N OUT APPENDIX B S T D - Z 8 0 B U S P I N OUT AND D E S C R I P T I O N BUS DESCRIPTION MNEMONIC 1 5V 5Vdc s y s t e m power 2 5V 5Vdc s y s t e m power 3 GND Ground System s i g n a l ground and DC r e t u r n 4 GND System s i g n a l ground and Ground DC r e t u r n 5 -5V -5Vdc s y s t e m power - -5Vdc s y s t e m p o w e r Data Bus ( T r i - s t a t e , i n p u t / o u t p u t a c t i v e h i g h ) . DO-D7 c o n s t i t u t e a n 8 - b i t b i d i r e c t i o n a l d a t a bus. The d a t a bus is used f o r d a t a exchange w i t h memory a n d 1 / 0 d e v i c e s A d d r e s s Bus ( T r i - s t a t e , active high). output, STD-Z80 B U S P I N OUT AO-A15 m a k e u p a 16-bit address b u s The a d d r e s s bus p r o v i d e s t h e a d d r e s s f o r memory ( u p t o 65k b y t e s ) d a t a exchanges and f o r 1/0 device data exchanges. 1/0 addressing uses t h e lower 8 address b i t s t o allow the user t o directly s e l e c t up t o 256 i n p u t o r 256 output ports. A0 i s t h e l e a s t signficant address bit. ,During r e f r e s h time, t h e l o w e r 7 b i t s contain a valid refresh address for dynamic memories i n t h e s y s t e m . Memory Write ( T r i - s t a t e , o u t p u t , /WR i n d i c a t e s t h a t a c t i v e low). t h e CPU d a t a b u s h o l d s v a l i d d a t a t o be stored i n the addressed memory o r 1/0 d e v i c e . Memory R e a d ( T r i - s t a t e , output* a c t i v e l o w ) . /RD i n d i c a t e s t h a t t h e CPU w a n t s t o r e a d d a t a f r o m memory o r a n 1/0 d e v i c e . The a d d r e s s e d 1/0 d e v i c e o r memory s h o u l d u s e t h i s signal t o gate data onto the CPU d a t a bus. Input/Output Request (Tri-state, output, a c t i v e low). The /IORQ signal indicates t h a t t h e lower half of t h e address bus holds a v a l i d 1/0 a d d r e s s f o r an 1/0 r e a d o r w r i t e o p e r a t i o n . An / I O R Q s i g n a l i s a l s o g e n e r a t e d w i t h a n /MI s i g n a l when a n i n t e r r u p t i s b e i n g acknowledged t o i n d i c a t e t h a n an i n t e r r u p t response v e c t o r can be p l a c e d on t h e d a t a bus. I n t e r r u p t Acknowledge o p e r a t i o n s o c c u r d u r i n g /MI t i m e , w h i l e 1 / 0 o p e r a t i o n s n e v e r o c c u r d u r i n g /MI time. Memory R e q u e s t ( T r i - S t a t e o u t p u t * a c t i v e low). T h e /MEMRQ s i g n a l i n d i c a t e s t h a t t h e addreqs bus h o l d s a v a l i d a d d r e s s f o r a memory r e a d o r write o p e r a t i o n . 1/0 expansion, S y s t e m s DSTD. n o t u s e d on dy-4 STD-Z80 BUS P I N OUT Memory e x p a n s i o n , n o t dy-4 S y s t e m s DSTD c a r d s . used on /REFRESH ( T r i - s t a t e , o u t p u t , a c t i v e l o w ) . /REFRESH i n d i c a t e s t h a t t h e lower 7 b i t s of the address bus c o n t a i n a r e f r e s h a d d r e s s f o r dynamic m e m o r i e s and t h e /MEMRQ s i g n a l should be u s e d t o perform a r e f r e s h cycle f o r a l l dynamic RAMS i n t h e system. During t h e r e f r e s h c y c l e A7 i s a l o g i c z e r o a n d t h e u p p e r 8 b i t s of the address bus contains t h e I register. /DEBUG ( I n p u t ) u s e d i n c o n j u n c t i o n w i t h DDT-80 o p e r a t i n g s y s t e m a n d t h e MDX S i n g l e S t e p c a r d f o r i m p l e menting a hardware s i n g l e step. When p u l l e d l o w , t h e /DEBUG l i n e w i l l set a l a t c h t h a t w i l l f o r c e t h e upper three address l i n e s t o a l o g i c 1. To r e s e t t h i s l a t c h , a n 1/0 o p e r a t i o n m u s t b e p e r f o r m e d . M a c h i n e Cycle One ( T r i - s t a t e , o u t put, a c t i v e low). /MI i n d i c a t e s t h a t t h e c u r r e n t machine c y c l e is i n t h e opcode f e t c h c y c l e o f an instruction. Note t h a t d u r i n g t h e e x e c u t i o n o f a 2 - b y t e o p c o d e s , /MI w i l l be generated a s each opcode is fetched. These two-byte op-codes a l w a y s b e g i n w i t h a CBH, D D H , EDH o r FDH. /MI a l s o o c c u r s w i t h / I O R Q t o i n d i c a t e an i n t e r r u p t acknowledge cycle. STATUS 0 DMA p r i o r i t y c h a i n i n p u t . /BUSAK Bus Acknowledge (Output, a c t i v e low). Bus Acknowledge i s used t o indicate t o the requesting device t h a t t h e CPU a d d r e s s b u s , d a t a b u s , and c o n t r o l bus s i g n a l s have been set t o t h e i r high impedance s t a t e a n d t h e e x t e r n a l d e v i c e c a n now c o n t r o l t h e bus. sTD-Z80 BUS P I N OUT Bus Request ( I n p u t , a c t i v e low). T h e /BUSRQ s i g n a l i s u s e d t o r e q u e s t t h e CPU a d d r e s s b u s , d a t a bus, and c o n t r o l s i g n a l bus t o go t o a high impedance s t a t e s o t h a t o t h e r devices can c o n t r o l those buses. When /BUSRQ i s a c t i v a t e d , t h e CPU w i l l s e t t h e s e b u s e s t o a high impedance s t a t e a s soon a s t h e C u r r e n t CPU m a c h i n e c y c l e i s termin a t e d , and t h e Bus Acknowledge (/BUSAK) s i g n a l i s a c t i v a t e d . I n t e r r u p t Acknowledge ( T r i - s t a t e output, a c t i v e low). T h e /INTAK s i g n a l i n d i c a t e s t h a t an i n t e r r u p t acknowledge c y c l e is i n progress, and t h e i n t e r r u p t i n g d e v i c e should p l a c e i t s r e s p o n s e v e c t o r on t h e d a t a bus. I n t e r r u p t Request (Input, a c t i v e low). The I n t e r r u p t Request S i g n a l i s g e n e r a t e d by 1/0 d e v i c e s . A r e q u e s t w i l l b e honored a t t h e end of the current instruction if the internal software controlled interrupt enable flip-flop (IFF) is e n a b l e d a n d i f t h e /BUSRQ s i g n a l i s n o t a c t i v e . When t h e CPU a c c e p t s t h e i n t e r r u p t , an acknowledge s i g nal (/IORQ during an / M I ) is s e n t out a t t h e beginning of the next instruction cycle. /WAI TRQ WAIT REQUEST ( I n p u t , a c t i v e l o w ) . W a i t r e q u e s t i n d i c a t e s t o t h e CPU t h a t t h e a d d r e s s e d memory o r 1/0 devices a r e not ready f o r a data transfer. T h e CPU c o n t i n u e s t o enter wait s t a t e s for a s long a s t h i s s i g n a l i s a c t i v e . The s i g n a l a l l o w s memory o r 1/0 d e v i c e s o f a n y speed t o be synchronized t o t h e CPU. ' S T D - ~ 8 0BUS PIN OUT n 46 /NMIRQ Non-Maskable I n t e r r u p t r e q u e s t ( I n p u t . n e g a t i v e e d g e t r i g g e r e d ) . The Non-Maskable I n t e r r u p t r e q u e s t h a s a h i g h p r i o r i t y t h a n /INTRQ a n d i s a l w a y s recognized a t t h e end o f t h e c u r r e n t i n s t r u c t i o n , independent o f the status of the interrupt enable flip-flop. /NMIRQ automatically f o r c e s t h e CPU t o r e s t a r t t o l o c a t i o n 0066H. The p r o g r a m c o u n t e r i s a u t o m a t i c a l l y saved i n t h e e x t e r n a l stack s o t h a t the user can return t o t h e program t h a t was interrupted. Note t h a t c o n t i n u o u s WAIT c y c l e c a n p r e v e n t t h e c u r r e n t i n s t r u c t i o n f r o m e n d i n g , and t h a t a /BUSRQ w i l l o v e r - r i d e a / N M I R Q . 47 /SY SRESET S y s t e m Reset ( O u t p u t , a c t i v e l o w ) . T h e S y s t e m Reset l i n e i n d i c a t e s t h a t a reset h a s been g e n e r a t e d from e i t h e r an e x t e r n a l reset o r The t h e power-on reset c i r c u i t . system r e s e t w i l l o c c u r o n l y o n c e p e r reset r e q u e s t and w i l l b e approximately 2 microseconds i n durat i o n . The s y s t e m r e s e t w i l l a l s o f o r c e t h e CPU p r o g r a m c o u n t e r t o zero, d i s a b l e i n t e r r u p t s , set t h e I r e g i s t e r t o OOH, set t h e R r e g i s t e r t o OOH a n d s e t I n t e r r u p t Mode 0. P u s h b u t t o n Reset ( I n p u t , a c t i v e low). The P u s h b u t t o n reset w i l l g e n e r a t e a debounced system reset. Processor Clock (Output, a c t i v e low). S i n g l e phase system clock. 50 CNTRL A u x i l i a r y Timing 51 PC0 P r i o r i t y Chain Output (Output, a c t i v e high.) T h i s s i g n a l is used t o form a p r i o r i t y i n t e r r u p t d a i s y c h a i n when more t h a n o n e i n t e r r u p t d r i v e n d e v i c e is b e i n g used. A h i g h l e v e l on t h i s p i n i n d i c a t e s t h a t no o t h e r d e v i c e s o f h i g h e r p r i o r i t y a r e b e i n g s e r v i c e d by a CPU i n t e r r u p t s e r v i c e r o u t i n e . w STD-Z80 BUS PIN OUT P r i o r i t y Chain I n ( I n p u t , a c t i v e high). T h i s s i g n a l is used t o form a priority interrupt daisy chain when m o r e t h a n o n e i n t e r r u p t d r i v e n d e v i c e is b e i n g used. A h i g h level on t h i s p i n i n d i c a t e s t h a t n o o t h e r devices of higher priority are b e i n g s e r v i c e d b y a CPU i n t e r r u p t service routine. AUX GND A u x i l i a r y Ground ( B u s s e d 1 AUX GND A u x i l i a r y Ground ( B u s s e d ) +12Vdc s y s t e m p o w e r -12Vdc s y s t e m power NOTES: The r e f e r e n c e t o i n p u t a n d o u t p u t o f a g i v e n s i g n a l i s made w i t h r e s p e c t t o t h e CPU m o d u l e . APPENDIX C DSTD-102 PARTS LIST ..-.-.,--.. b DSTD 102 PARTS L I S T - ------------ ___--------------_--- - -- ---c---- DYQPART UTY DESCRIPTIDN DESIG:J9TION ..................................................................................................... ( I n PT012008 1 PT012014 1 Pl012020 1 PT012074 2 PT012112 1 1 PT012164 PTO12243 1 PT012244 2 ~~012245 3 KO12257 1 PT013074 1 PT015009 1 1 PT015013 1 PT015017 no16001 2 ~~016002 2 PT036001 1 PT036002 2 PT041101 1 1 PT041122 PT041220 1 PT041221 1 PT041302 2 PT041472 2 PT041473 1 PT041681 1 2 PT043012 1 PT043017 1 PT051004 PTO52003 1 PT052004 8 1 PT052009 PT052010 18 1 PT052013 PTO53000 1 PT061003 1 - PT071000 -1 PT073001 2 PTO9lOOO 1 PTO91002 1 PT101000 1 PT!01005 1 PT111873 1 PT122003 3 PT122004 1 PT123003 2 3 PTl26020 PT126028 4 2 PT126040 P1344901 1 PT711003 1 . 74LS08 TTI-LS 741514 TTL-LS 74LS20 TTL-LS 741574 TTL-LS -14LS112 TTL-LS 7415164 TTL-LS 74LS243 RL-LS 7418244 TTL-LS 7415245 ~ L - L S 74LS257 TTL-LS 74574 T n - S NK3880n (280-CPU) 2.5 HHZ CPU NK3882n (280-CTC) 2.5 NHZ CTC . NK3E84n (280-SIWO) 2.5 HHZ SIO/O 75180 OR ncises INTERWE 75189 OR nc1489 INTERFACE PALl2Ld PAL1618 1/4 WTT, 100 OH, 5Z RESISTOR 1 / 4 W , 1.2K0Ml ZRESISlOR 1/4 UATI. 22 OM, 5% RESISTOR 1/4 W, 220 OH, SA RESISTOR 1/4 WTT, 3K OM, 5% RESISTOR 1/4 UQTI. 4.7K OM, 5% RESISTOR 1/4 16911, 47K OH, ?A RESISTOR 1/4 WTT, 680 OH, Z RESISTOR 8 PIN, 7 RESISTOR, 4.7K OM, SIP RESISTOR NRUORK 10 PIN, 9 RESISTOR, 4.7K O,W, SIP RESISTOR NRUORK 034-55101 OR 035-561 01, 100uf, RADIAL ELECTROLYTIC CAPACITOR CK059X330Kl 33vf, 20W CERAHIC CAPACITOR CK05BX331Kt 330pf, 200V C E W I C CAPACITOR 8131-100-25U-474I4, ,47uf, SOU, C E M I C CAPACITOR . l u f , 50W.1 ID. SP.) 8121-050-2511-10414, C E M I C CAPACITOR .luf ,5W t.2 LD. SP.) 8121-050-25U-104n) (102 BMRD aYLY) TAGlON25, IOuf , 25V T W A L U I CAPACITOR 2N3906 TRANSISTOR IN4148 SIGN91 DIODE . IN4001 RECTIFIER HMP6300 W L L RED LED HWP6500 W L L GREEN LED K11354 CRYSTAL OSCILUTOR GENERATOR K l l l M 5.000 NHZ CRYSTAL OSClLLATOR S208-1 C4RD EJECTOR UlTH PINS CHDd96OUIS 60 PIN DOUBLE RUd HMDER CHS693ddIS 36 PIN SINGLE ROW HEADER 875!6-2 12 PIN RIGHT FJYGLE CMiECTOR ( M P CtiLY) 640464-3 20 PIN I.C. SOCKET 640362-3 28 PIN I.C. SOCKET 640379-3 40 PIN I.C. SOCKET DSTD 102 DY00449-H+l-6 102 M W L U15 U5 U10 U3,U14 U11 U4 U27 U28, U29 U22, U24 ,U25 U13 U12 U17 ~8 Ul6 u6 UI ,u2 U23 UP, U26 R12 R4 R6 R5 R1 ,R7 R2, R3 R10 R13 lUi2,fU43 RN4 C35 C2 C6-13 C3 C16,17,19,21-34,36 C14 C18 Ql 03 D l ,D2 LED2 LED1 U21 U30 mu JE1-J85, JB9-JB15 JB6, JB7-JBlOc, JB15 52.53 U9, U?3,U26 U18-U20 ,U8 Ul6,U17 C -1 APPENDIX C DSTD 102 PARTS LIST .-------------------------------------------------------------DY4PART QTY DESCRIPTION ........................................................................................................ n n PT012008 1 PT012014 1 PT012020 1 PT012074 2 PT0!2112 1 YO12164 1 PT012243 1 PTO12244 2 PT012245 3 PT012257 1 ~~013074 1 PT015810 1 ~~015014 1 1 PT015020 PT016001 2 PTOl6002 2 PT036001 1 PT036002 2 ~~041101 1 1 PT041122 PT041220 1 PT041221 1 PT041302 2 Pl041472 2 PT041473 1 Pi041681 1 PT043012 2 PT043017 1 Pi051004 1 PT052003 1 PT052004 8 PT052109 1 PT052010 18 PT052013 1 ?TO53000 1 Pi061003 1 PT071000 1 KO73001 2 PTO9lOOO 1 PT09lOOl 1 PTl01000 1 PT101007 1 PT111073 1 PT122003 2 PT122004 1 PT123003 2 Pf126020 3 4 PT!?JO29 PTl26GJO 2 ?T344901 1 ! PT?!!403 74LS08 llL-LS 74LS!4 TTL-LS 74LS20 TrL-LS 74LS74 TTL-LS 7415112 TTL-LS 74LS164 llL-LS 74LS243 TTL-LS 74LS244 TrL-LS 74LS245 i l L - L S 749257 TTL-LS 74874 m-s M3880n-4 (Z80A-CPU) 4.00 HHZ CPU ~ ~ 3 8 8 % - 4(28011-CTC) 4.00 HHZ CTC WK3884n-84 (Z8M MRT) 4.00 HHZ DART 75188 OR tic1488 INTEPFACE 79189 OR tic1489 IKIERMCE PAL12Lb PAL1618 1/4m, ~OOO~,~RESI~OR 114 UT, 1.2K OM, 5% PESISTOR 114 Mil, 22 OH?, S! RESISTOR 1 / 4 M T l , 220OW,S!:!aElSTOR 1/4 MTT, 3K OM, Z REZISTOR 1/4 Mil, 4.7K Om, Z RESISTOR 1/4 WATT, 47K 0HM, 5% RESISTOR 1/4 Mil, 680 OM, S! RESlSTOR 8 PIN, 7 RESISTOR. 4.7K OM, SIP RESISTOR NETWORK 10 PIN, 9 RESIgOR, 4.7K CHI, S!P RES!STOR NETk'ORK 034-55101 OR 035-56101, 100ui, PAD!AL ELECTROLYTIC CAPACITOR CK05BX330K. 3 3 ~ f ,200V C E W I C CAPACITOR CK05BX331K, 3 3 0 ~ f , 200V CE.W!C CAPACITOR 9131-100-25U-474!l, .47uf, 50V, CE.W!C C4PACITC)R .luf, 5W(.1 LD. S?.) 8121-05!J-Z5?r-!04H, CEWIC GlWCITOR ,luf ,50V (,2 LD, Sf.) 9121-050-Z5U-!04H) (102 0W.SD MJLY) TAG10H25, IOuf , 2% TIWALL?! CAPACITOR 2N3906 TWSISTOR IN4148 S I W L DIODE IN4001 RECTIFIER HMP6300 WILL RED LED HLnP6400 WALL YELLOW LED K1133 MUD MTE GMERATOR K l l l M 8.000 HHZ C,PYSTFIL OSCILfiTOR 5208-1 CARD EJECTOR WITH PIHS CHD6960UIS 60 PIN DOUBLE RCW HE46ER CHS693dldIS 36 PIN SINGLE RYd vG4DE.S 97516-2 !2 PIN RIGilT MGLE C8tiECTOR !MP 3 L Y ) 640464-3 20 P!N I,C. SOCKET 440352-3 29 ?!!I !.C, S5CKET 644379-3 40 PIN I.C. SOCKET hSTD 102 i)YOOJJ?-!+l-? 102 W J M L DESIWT!W1 U15 U5 U10 U3,U14 Ul 1 U4 U27 U28, U29 U22, U24. U25 U13 U12 U17 U8 Ul6 06, U7 U1 ,U2 U23 U9, U26 R12 14 R6 35 R1 ,R7 R2, R3 R10 913 RN2, RN3 IW4 C35 C2 C6-13 C3 C!6,!7,!9,?!-34,36 C14 Cl 9 a! D3 Dl ,D2 LED2 ?ED! U21 U30 JB1-dg5, J89-J9! 5 J86, JB?-JE!Oc ,JB!5 52-53 i19.023. U26 U! 8-il?!l, U0 U16.!!!7 - b PARTS LIST FIGURE C-1 DSTD-102-4 SILK SCREEN APPENDIX D SCHEHATIC UNUSED GATES me u2e - SCALE IDRN 3. NI-LSIC"~ APP'O 1 TOL ! TITLE OWG NO 7-T-. -21, I02 DATE, , ,, , 1 FINISH ]MAT L I 1 ( 3 $ i E ? -.& G'-13. TASLE) DY00449-1-41-6 , 115s t I sn OF: - - DISABLE INTERRUPTS IFF1. IFF2 0 Flgure 9 for tlmlng details.) Interrupt Thls 8-blt the devlce wlth an Interrupt under servlce and brlng IEO Low) a t any tlme, It Is p o r s l b l e for: a devlce whose Interrupt I s cur- when the ED I s seen durlng t h e ED-4 l n s t r u d l o n fetch. The devlce whos between bib within a character is approximately constant, since the clocks or "baud C~AMCIIIascstvm I . L ~ ~ L ~ I . C X I S I ~ S ~ WUSIU I u u y n I o Flpur* 1. Aaynchronoua Data Formot This application note refers to products a s Z80"AW,"B"etc. to specifiythe speed grade. We are no longer uslng those characters for the speeds. For more details, please refer to the ordering Informationsection. 541 , in part, from an "interrupt vector" (8-bit byte) supplied by the SIO during the interrupt acknowledge cycle. In Block Transfer mode, the SIO is used in designed to interface easily to shown in Figure 2. Other re require a small amount of to generate the necessary interrovides a sophisticated vectoredility to signal events that require Interrupt mode is independent of the choice of synchronous or asynchronous 110. This latter choice is usually determined by the type of device to which the system is communicating. SECTION ' dhannels supported by the SIO if both chan- Operatlonal Conrrlderations. some of the basic charactsristics of SIO oper- it- When transmitting asynchronously, the S f 0 automatically inserts one start bit (logic 0)at number of 1s in the character (including parity ~. 1, will be transmitted; thus l f i stop bits means bit) even or odd, depending on whether even that a 1 will be transmitted for the length of or odd parity is selected. The SIO can be set clock time that I '/l bits would normally take either even oraoddparity can be chosen. This "bits per character" is less than eight, parity . . with logic 1s (marking). If the "bits per char- transmitted to the CPU. t A change in the status of certain external inputs to the SIO will cause status bits in the SIO to be set. h the Polled Mode, these status bits can be read by the CPU. In the Interrupt mode, the SIO can also be programmed to interrupt the CPU when the change occurs. There are three such "externavstatus" conditions that can cause these events: , DCD. ~ ~ fthe lvalue ~ of~the tDCD ~ input, 8 CTS. Reflects the value of the ?%input. Breuk. A series of logic 0 or "spacing" bits. Interrupts 'SnItializcrtlon , * The SIO contains eight write registers for Channel B (WRO-WR7) and seven write registers for Channel A (all except write register WR2). These are described fully in the 280 SIO Technical Manual and are Note that the DCD and CTS status bits are ' the inverse of the S s n e s , i.e., the DCD bit will be 1 when the DCD line is Low. Any transition in any direction (i.e., to logic 0 or to logic 1) on any of these inputs to the SIO will cause the related status bit to be latched and (optionally) cause an interrupt. The SIO status bits are latched after a transition on any one of them. The status must be reset (using an SIO command) before new transitions can be reflected in the status bits. , programmed separately for each channel to configure the functional personality of the channel. WR2 exists only in the Channel B register set and contains the inteirupt vector for both channels. Bits in each register are named (most significant) through Do. With the exception of WRO, programming the write read registers, but register RR2 exists only in Channel B. sequence. Except for step E, this loading is done for each channel when both are used. Steps E and F are described further in the section on "Interrupt-Driven Environmente." Registers WR6 and WR7 are not used in asynchronous I/0. They apply only to synchronous communication. 280 SIO Technical Manual, pages 9-12 ("Asynchronous Operation") ' . , C. Load WR3. This specd~eathe number 01 recelve bits per character, Auto Enable selection. and turna on the receiver enabling bit. D. Load WR5. This specilies the number of transmit bits per character, turns off the bit that transmits the Break s~gnal,turns on the bits indicating Data Termlnal Ready and Request To Send, and turns on ihe transmitterx enabling btt. . E. Load WR2. (Interrupt mode only and Channel B only.) This spec~fiesthe interrupt vector. ' F. Load WR1. liniermpt mode only.) This spec~lies vanous interrupt-handling options that will b e explained later. , NOTES: Stepa A through Fare perlormed In Pequencs. 'Channsl B only tlnterrupt mode only. Poiltnp mode bqlna UO alter step D. Figure 4. Typlcal Inltldlzation Sequeaca (On*Cham . Character To check that an initialized SIO is ready to Transmission transmit a character on a channel, and if so to transmit the character, the steps illustrated in Figure 6 should be followed. We assume that the Request To Send (RTS) bit in WR5, if required by the external receiving device, and the Transmit (Tx) Enable bit were set at initialization. Depending on the external receiving device, the following bits in register RRO should be checked: bit 3 (DCD), to determine if a data carrier has been detected; bit 5 (CTS), to determine if the device has signalled that it is clear to send; and bit 7 (Break), to determine if a Break sequence has been received. If any of these situations have occurred, the bits in register RRO must be reset by sending the Reset Externsl/Status Ihterrupts command, and. the transmit sequence must be started again. Next, bit 2 of register RRO is checked. If this bit is 0, then the transmit buffer is not empty and a new character cannot yet be transmitted. Depending on the capabilities of the CPU, this is repeated until a,character can be trans, mitted (or a timeout occurs), or the CPU may return to other tasks and start again later. If bit 2 of register RRO is 1, then the transmit buffer is empty and the CPU may pass the Inltlalizatlon (Continued) C / 6 character to be transmitted to the SIO, completing the transmit processing. On the 280 CPU, this is done with an OUT instruction to the SIO data port. 4 w-1 1 S T A W I INTERRUPTS - WTCHARACTER IN T i SUFFER Figure 8. Polled Trarumlt Assumptions Now let us consider some examples in more for an detail. We assume we are given an external Example device to which we will input and output 8-bit characters, with odd parity, using the Auto Enables feature. We will support this device -with IJO polling routines following the patterns illustrated in Figures 5 and 6. (We assume that the CPU will provide space to receive characters from the SIO as fast as the characters are received by the SIO, and that the CPU will transfer characters as fast as the output can be accomplished by the SIO. We specify this example by giving the control bytes (commands) written to the SIO and the status bytes that must be read from the SIO. Recall that to write a command to a register, except register WRO, the number of the register to be written is first sent to register , WRC the following byte will be sent to the named register. Similarly, to read a register other than RRO (the default), the number of the register to be read is sent to register WRO; the following byte will return the register named. We begin with the initialization code for the SIO. This follows the outline illustrated in Figure 4. In the following sample code, each time register WRO is changed to point to another register, the Reset External/Status Interrupts command is given simultaneously. Whenever a transition on any of the external lines occurs, the bits reporting such a transition are latched until the Reset ExternaVStatus Interrupts command is given. Up to two transitions can be remembered by the SIO. Therefore, it is desirable to do at least two different Reset ExternaVStatus Interrupts commands as late as possible in the initialization so that the status bits reflect the most recent information. Since it doesn't hurt, we include these commands each time WRO is changed to point to another register. This is an easy way to code the initialization to insure that the appropriate resets occur. I_n the example below, the logic states on the CJD control line and the system data bus (D7-Do) are illustrated, together with comments. In the re1 low, we tre, Data Carric sequence" RRO to refk the pins. Tk the Reset E mand and k The comma register WE Reset and Error s*quences Pprrnlh the r h * ; Roeelve and T r d t Routines This comr for such thil 4-6 of regist occurs and i Now we w of the recei\ preceding d Recepti0n.l' The frami~ on a characi Effects and Comments (Rwelve Routlnm) Read a byte from RRO (the deiault read register), if Do = 0 then no character is ready to be received In this case. if Dg (Break) or q (Data Carrier Detect) have changed state, then execute a "reset sequence " 11 Do=O and 4 and Dg have not chanqed state, then no character Is ready to be recelved; either loop on this read or try again later. (Continued) each WR1 an lr Point WRO to read from RR1; we will now check for errors m the character read. Note that Reset ExternaVStatus lnterrupt Commanda are not done normally to avoid losing a line-status change. Read a byte from RR1; if either bit D6= l (framing error), DS = (receive overrun error), or D4 = l (parity error), the character is inval~dand an "error sequence'' should be executed after the following step. Read in the data byte recelved. This must be done to clear the S10 buifer even if an error Is detected. c/rd 5 Bltm rent a n d ruelved Da D, D, Da D, Dl Da Effects a n d Commentm (TrmumIt Routine) ' ' 86CT101P Interrupt-Driven Environments. In a typical interrupt-driven environment, the SIO is initialized and the first transmission, if any, is begun. Thereafter, further I/O is interrupt driven. When action by the CPU is needed, an SIO interrupt causes the CPU to branch to an interrupt service routine after the CPU first saves state information. In common usage, if I/0 is interrupt driven, all interrupts are enabled and each different , type of interrupt is used to cause a CPU branch to a different memory address. There is perhaps one frequent exception to this: parity ' errors are sometimes checked only at the end of a sequence of characters. The SIO facilitates thls kind of operation since the parity error bit in read reglster RRl is latched; once the bit is set it is not reset until an explicit Chanr Read a byte from RRO; If either bit DJ (Data Carrier Detect), Ds (Clear To Send) or Dg (Break) have changed state, a "reset sequence" should be executed. If D3$ DS and D7 have not changed state, then if D2=O, the transmit buffer is not yet empty and a transmit cannot take place; either loop, reading RRO, or try again later. Send the data byte to be transmitted. reset operation is done. Thus, if a parity error has occurred on any character since last reset, bit 4 in register RR1 will be set. It is then possible to set register WR1 so that parity errors do not cause an error interrupt when a character is received. The user then has the obligation to poll for the value of the partty bit upon completion of the sequence. SIO initialization for Interrupt mode normally requires two steps not used in Polled mode: an interrupt vector (if used) must be stored in write register WR2 of Channel B and write register WRl must be initialized to specify the form of interrupt handling. It is preferable to initialize the interrupt vector in WR2 first. In this jvay an interrupt that arrives after the enabling bits are set in WRl will cause proper interrupt servicing. Chanr to 0 Chann Chann For I tor hac Affects interru transit1 tained I Initlallzatlon ' In ge illustrat necessa of Chan register to be en interrup Now 11 characte , rupt vector is normally taken as one byte of an address used by the CPU to find the location of the interrupt service routine. It is also possible to cause the particular type of intermpt condition to modlfy the address vector in WR2 before branching, resulting in a branch mine the situation before proceeding, can be quite inefficient. This is usually undesirable since the speed of interrupt-service routines is often a critical factor in determining system performance. We dc registers Techn~cc bit assigl Input/Ob at the en Ro (D5-D3). 3t Exterlroughout o another Status 1b0ve. Of course, this last routine is probably f a r , too simple to b e useful. It is more likely that a n interrupt routine will fill u p a buffer of characters. A more complex example of a receive interrupt routine is contained in the SlOextlnt: s (from left P bits per PUSH AF ;save registers which will be used'in this routine LD OUT 1N LD POP El RETI A.KJO10000B (SlOctrl) ,A A,(SlOctrl) (XI .A , AF ;send a Reset ExternaVStatus lnterrupts command Finally, we give the processing for a transmit interrupt routine in the case where no more characters a r e to b e transmitted. It is likely that this code would just be a portion of a more general transmit interrupt SlOtrnlnt: , chapter entitled "A Longer Example." W e now, give a simple interrupt routine for a n ExternaVStatus Interrupt, again assuming that the status contents of SIO register RRO a r e stored in temporary location X: PUSH LD OUT AF : A.00101000B (SlOctrl) ,A ;fetch register RRO ;store reault for later analysis ;restore saved reglutera ;enable interrupts :return irom Interrupt ' routine which would transmit a buffer-full of informatioii at a time. A more complex example is included in the section entitled "A Longer Example." ;save registers which will b e used in this routine ;send a Reset Tx Interrupt Pending command ' A Special Receive Condition interrupt Condition Interrupts there is a receiver overrun error (data is being overwritten because the channel's three-byte receiver buffer is full and a new character is being received), or (c) if there is a framing error. The processing in this case is the fol1. Issue an Error Reset command (to register WRO) to reset the latches in register RRI. 2. Read the character from the read buffer and discard it to empty the buffer. It may be desirable to read ana store the c/D 4 the character. In some applications, a character may still be acceptable if received with a framing error. In specifying the result of reading register RRO, RRI, or specifying data, we will indicate the values as follows: D7 Do Ds D4 D3 Da Dl DO D I D ~ D I D I D I D ( D / D ~~~d byte from the designofed mgister. We now present an example of processing a Special Receive Condition interrupt. Blt. wnt and r.cm1v.d De Ds D4 D3 D1 Dl Do E f f e 8 and Cammmnta loalng a valtd Interrupt. received. This must be done to fier, but the character will gener- you wish to find the specific cause of the c 4 Blm u n t and rmnlr*d Do Ds D4 DJ Dz Dl Do Etf*ct. and Cammmnb Read register RRO; btt D7 (Break), DS (Clear To Send). or D3 (Data Carrier Detect) will have had a transltlon to indicate the cause oi the Interrupt. Give a Reset ExtemaVStatus lnterruptn command to set the latches In RRO to thelr current valuea and stop ExternallStatua interrupts untll another transltlon OCCUrB. Tranrmit (Tx) The final kind of interrupt is a Tx Buffer Buffer Empty Empty interrupt. If another character is ready is ready to transmit, it may be desirable to mark the availability of the transmit mechanism for future use. In addition, you should send a Reset Tx Interrupt Pending command. This command prevents further transmitter inter- rupts until the next character has been loaded into the transmitter buffer. Pending commmd,. no Tx E~,,,,, inferR~~~~T~ ntpk will b e given until offer the next chorncter hos been . placed m the tmnsmit buffer. 555 ' If the CPU does not have the return from interrupt sequence (RETI instruction on the Z80 CPU), how may the SIO be informed of the completion of ~nterrupthandling? A: This may be done by wr~tingthe Return From Interrupt command (binary, 001 11000) to WRO in Channel A of the SIO. Q. If the CPU dan be interrupted but cannot be used with vectored interrupts, how should processing be done? A: Immediately after being interrupted, proceed in a manner similar to polling the SIO for both receive and transmit. Alternatively, the Status Affects Vector bit (bit 2 in register WR1) may be set and a 0 byte placed into the interrupt vector (register WR2 in Channel B). Then, the contents of the interrupt vector can be used to determine the cause of the interrupt and the channel on which the interrupt occurred. This can be q u e r i e d k r e a d i n g register RRl of Channel B. Also, M1 should be tied High and no equivalent to an ~nterruptacknowledge should be issued. Q: How can the WaitIReady (W/RDY) signal be used by the CPU in asynchronous 1/07 A: ~h~ w ~ signal y f s most commonly used in Block Transfer Mode with a DMA, and this use is described in the Z8O DMA Technical Manual. However, W/RDY may be directly connected to the 280 CPU WAIT line in order to,use the block I/O insti-uctions OTDR, OTIR, INDR, and INIR. In this case, the SIO can be used for block transfer reception. To do this, the SIO is configured to interrupt on the first character received only (by settings bits 4 and 3 of register ' WR1 to 01) and additional characters are sensed using the W/RDY line. The block I/O instructions decrement a byte counter to determine when I/O is complete. Q: Can the pin have any use in asynchronous I/0? A: It may be used as a general-purpose input. For example, by connecting it to a modem ring indicator, the status of that ring indicator can be monitored by the CPU. Q: How can the SIO be used to transmit characters containing fewer than 5 bits? A: First, set bits 6 and 5 in register WR5 to indicate that five or fewer bits per character will be transmitted. The SIO then determines the number of bits to actually transmit from the data byte itself. The data byte should consist of zero or more Is, three Os, and the data to be transmitted. Thus, beginning the data byte with 1111OOO1 will cause only the last bit to be transmitted: Q: Contents of data byte (d= arbitrary value) 4 D6 D5 D4 D3 D2 l l l l 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 d d 'The O 0 0 d O 0 d d d d DI DO O d d d d d l d 2 d 3 d 4 . 5 rlohlrnoat number 01 bit8 lndlcated will be Iran~mltled. Q: Can a Break sequence be sent for a fixed number of character periods? A: Yes. Break is continuously transmitted as logic 0 by setting bit 4 of register WRS. You can then send characters to the transmitter as long as the Break level is desired to persist. A Break signal, rather than the characters sent, will actually be transmitted, but each bit of each character sent will be clocked as if it were transmitted. The All Sent bit, bit O of register RRl, is set to 1 when the last bit of a character is clocked for transmission, and this may be used to determine when to reset bit of register WRS and stop the Break Q: If a Break sequence is initiated by setting bit 4 of register WR5, will any character in the process of being transmitted be , completed? A: No. Break is effective immediately when bit 4 of WR5 is set. The "all sent" bit in register RRl should be monitored to determine when it is safe to initiate a Break sequence. , I 557 Longer Example (Continued) 1 parameters as the interrupt-driven example in the previous section. The table-driven version is presented simply as an alternative means of coding this material. A short routine for filling the receive buffer with "FF" (hex) characters and buffer definitions follows the ,510-Init routine. This in turn is followed by the transfer routine, Figure 8, which begins transmitting on Channel A; transmission and reception is thereafter directed by the interrupt routines. After the transfer routine begins output, it checks for various error conditions and loops until there is either completion or an error. Then the four interrupt routines follow: TxBEmpty, Figure 9, is called on a transmit buffer interrupt; it begins transmission of the next character in the buffer. A carriage return stops transmission. RecvChar, Figure 10, is called on a normal receive interrupt; it places the received character in the buffer if the buffer is not full and updates receive counters. The routines SpRecvChar, Figure 11, and ExtStatus, Figure 12, are error interrupts; they update information to indicate the nature of the error. The code of this example can be used in a situation where data is beina sent to a device which echoes the data sent. In such a case, the transmit and receive buffers could be compared upon completion for line or transmission errors. - BUFFER COUNTERANDRECEIVEIUFFER W I N T E R STORE II REOISTER CONTENTS WHERE RECEIVE BUFFER POINTS TO. S R RECEIVE STATUS WORD RESTORE SAVE0 REOISTERS RETURN FROM INTERRUPT Figure 10. Receive Character Interrupt Routine SAVE REOISTERS I STORE CONTENTS OF RR1 I N RECEIVE STATUS WORD. I I RESET ERROR LATCHES 6 ' I SAVE REOISTERS STORE CONTENTS OF RRO I N THE TRANSMIT STATUS WOAD. I SEND THE RESET EXTERNALISTATUS INTERRUPTSCOMMAND. RESTORE SAVED REOISTERS RESTORE SAVED REOISTERS RETURN FROM INTERRUPT ' Figure 11. Special Receive Condition Interrupt Routine RETURN FROM INTERRUPT Figure 12. ExtemaYStatus h t e r ~ pRouthe t * Appendix B R e a d Register Bit Functions RUD RECISIER 0 1. UHDERRUNlEOY 'UtOd Wlth "Ex1011~ffimI~s I"1LftMI" MWs READ RE01STER 1t t 0 1 0 1 o 1 1 0 0 o 0 0 1 1 0 0 0 0 0 1 U s d With S+xctaI ReSeim W t t m MWe RUD REGISTER 2 ( V l l i l b l ~I1 "SI.IY9 AIlUl, VUIOI" U Plogrammd I . Using the 280 SIO With SDLC Appkation Brief ' INlRaWrION DEsX3lmliM Th I s appl l c a t l o n k l e f descrl bes t h e use of The reader ,shou I d be tam1 Il a r wfth hardware t h e 280 S10 w l t h t h e l n c r e a s l n g l y p o p u l a r aspects of the S10 such as lnterfaclng t o the Synchronous Data L I n k Contro 1 (SDLC) corn CPU and a modem. A more detal led .descrlptlon muntcatlons protocol. A general descr l p t Ion o f t h e SDLC p r o t o c o l . I s g l ven I n t h e IBM o f t h e SDLC p r o t o c o l and lmplementatlon of p u b l l c a t f o n Synchronous Data L l n k Control the protocol u s l n g t h e S10 a r e dfscussed. . General lnformatlon (document CGA27-3093-2). Descr 1 p t Ions f o r transmlt and recelve operaA dsscrlptlon of the 280 S10 can be found I n t f o n s are glven f o r use w l t h s lmple Conto1 the Z l log Data B w k (document C 00-20344). frame sequences. Data communlcatlon today requlres a ccmununlc a t l o n p r o t o c o l t h a t can t r a n s f e r d a t a q u l c k l y and r e 1 lably. One such protocol, Synchronous Data Llnk Control (SDLC), I s t h e 1 nk control used by the 1BM Systems Network ArJIltecture (SNA) communlcatlon Package. SDLC I s a c t u a l l y a subset o f t h e Internst l o n a l Standards O r g a n l z a t l o n (!SO) 1 I n k c o n t r o l c a l l e d Hlgh Level Data Llnk Control (mLC)t *hlch 1s used for l n t e r n a t l o n a l data camun1catlon. , Is Blt-Orlente# Pr*ocol (*)* It d l f fers from Byte-Control P r o t o c o l s (BCPs), such as blsync, I n havlng a few b l t patterns f o r c o n t r o l functions I n s t e a d o f s e v e r a l s p e c l a l character sequences. The a t t r l b u t e s of the SDLC protocol are pos It Ion dependent r a t h e r than character dependent, so control l a determined by the locatlon of the b y t e as we1 I as by the bl t pattern. A character I n SDLC I s s e n t as an o c t e t , a group of elght blts. Several octets m b l n e t o form a message frame I n such a way t h a t each o c t e t belongs t o a p a r t l c u l a r fleld. Each message frame cons1 s t s o f an openlng f l a g , address, c o n t r o l , lnformatlon, Frame Check Sequence (FCS), and c l o s l n g f l a g f lelds. The f l a g f l e l d c o n t a l n s a unlquq blnary pattern, 01 1 1 11 10, whlch lndlcates the Thls b e g l n n l n g and end of a message frame. pattern s l m p l l f l e s the hardware I n t e r f a c e I n r e c e l v l n g devlces so t h a t m u l t l p l e devlces connected t o a canmon 1 I n k do n o t conf 1 l c t w l t h one another. The r e c e l v l n g d e v l c e s respond only a f t e r a v a l l d f l a g character has been detected. Once ccmnunlcatlon I s esta- , . bllshed f o r a p a r t l c u l a r devlce, t h e o t h e r devlces Ignore t h e message u n t l l the next f l a g character I s detected. The address f l e l d contalns one or more octets t h a t are used t o select a p a r t l c u l a r s t a t l o n on t h e data Ilnk. An address o f a l l I s I S a g l o b a l address code t h a t s e l e c t s a l l t h e devices on the IInk. When a p r l m r y station sends a frame, the address f l e l d I s used t o select a secondary statlon. When a secondary station sends a message t o t h e p r lmary stat l o n , t h e address f l e l d contalns the secondary s t a t l o n address, I.e., the sour- o f the message. ' ' . The c o n t r o l f l e l d follows the address f l e l d and contalns l n f o r m a t l on about t h e type o f frame belng sent. The control f l e l d conslstq. of One o c t e t and I s always present. . , The l n f o r m a t l o n f l e l d c o n s l s t s o f zero o r more8-blt o c t e t s and c o n t a l n s any a c t u a l data transferred. However, because of the 1 lmltatrons of the error-checklng algorithm used I n t h e frame-check sequence, mxlmum recanmended block slze I s approximately 4096 octets* The Frame Check Sequence (FCS) follows the lnformatlon f l e l d or the c o n t r o l f l e l d , dependlng on t h e t y p e o f message frame sent. The FCS I s a 16-b1.t Cycl l c Redundancy Code (CRC) o f t h o b l t ~I n t h e address, control, and lnformatlm fields. The FCS I s based on the CRC-CCllT code, whlch uses the polyncinlal (x~~+x~~+x~+ The I ) .280 S10 contalns the c l r c u l t r y necessary b generate and check t h e FCS fleld. This application note refers to products as Z80 "A", "B"etc. to specifiy the speed grade. We are no longer ' t 01111110 Zero Insertlon/Deletlon and CRC Accumulation I One One Zero or more 16-bit 8 - b l t character 8 - b l t character 8 - b l t characters CRC-CCllT 01111110 r e c e l v e f l a g c h a r a c t e r s w l t h shared 0s ( 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 * * * ) # It can o n l y t r a n s m l t f l a g c h a r a c t e r s without s h a r e d 0 s (011111100111111001111110...). lnltlal l z a t l odn e f i n e s the basic mode of operation for the Table shows the sequence of steps used t o l n l t l a l l z e t h e SIO,. along w l t h t h e necessary parameters. S l nce vectored l n t e r r u p t s a r e used, t h e SIO I s programmed w l t h t h e s t a t u s a f f e c t s v e c t o r (SAV) b l t (WRI, b l t 2) set. Table 1. Reglster O t h e r f u n c t l o n b l t s t h a t can be Included a r e t h e external I n t e r r u p t enable b l t (WRI, b l t O), whlch r e s u l t s I n an I n t e r r u p t f o r each DCD o r CTS change, TX u n d e r r u n o r a b o r t change; a d d r e s s s e a r c h b l t (WR3, b l t 21, w h l c h when set, p r e v e n t s t h e SIO from respondlng t o data recefved u n l e s s t h e a d d r e s s b y t e matches t h e c o n t e n t s o f WR6 o r t h e g l o b a l (FFH) address; auto e n a b l e b l t (WR3, b l t 51, whlch causes t h e l n a c t l v e CTS l e v e l t o d l s a b l e t h e t r a n s m l t t e r and t h e l n a c t l v e DCD l e v e l t o d l s a b l e t h e recelver; and DTR (WR5, b l t 7 ) and RTS (WR5, b l t l), whlch can ,n o f t h l s c~w~ATION A f t e r t h e S10 has been I n l t l a l l zed and enabled, It can begln sendlng SDLC frames by software a c t l v a t l o o of t h e transmltter. A c t l v a t l n g t h e t r a n s m l t t e r lncludes r e s e t t l n g t h e transml t t e r l n a c t l v e semaphore (a prtqram Indicator), r e s e t t l n g t h e TX CRC accumula- SIO l n l t l e l l z a t l o n Sequence Funct ton Data 0 2 OOO11OOO (Vector) 4 1 7 5 00100000 00011111 (Address) 01111110 11101011 3 11001001 ' 6 ' Channel r e s e t I n t e r r u p t vector lower e l g h t b l t s '(channel B only) SDLC mode I n t e r r u p t control RX address f l e l d Flag f l e l d TX character length, enable, CRC enable 'RTS and DTR RX character length, enable, and CRC . . tlon, sendlng a character t o t h e S10, and res e t t l n g t h e TX underrun/EM l a t c h I n t h e SIO. F l g u r e 3 shows t h e sequence f o r t r a n s m l t t l n g a t y p l c a l c o n t r o l message frame uslng l n t e r rupts. SDLC Ty Control Mepsage Frame - += Flgure 3. Transmtt B u f f e r Empty External/Status Change A Typlcal Transmlt Control Frame Sequence . , c h a r a c t e r I n the TX buffer u n t l l the current f l a g character has completed shl ftlng. After t h e address b y t e 1s t r a n s f e r r e d I n t o t h e shift a Transmit fer (TBE) condltlon, dependlng upon t h e p r e v l o u s r e c e l v e condl t Ion. For example, when the SIO has been I n l t l a l Ired, the r e c e l v e c l r c u l t r y and abort, and passes t h e s t a t u s on t o t h program a t the next-hlgher level. After the FCS bfles have been sh 1 fted o',,t the SIO generates a TBE Interrupt t o lndfcat u n t l 1 the next f l a g I s found, a f t e r whfch the S10 agaln searches f o r an address match. Contlnuous , . ( I f deslred) data data Check errors; Error Reset; D 1scard , Character* ' * The SRC r o u t l n e normally reads the data character t o clear the SIO buffer. Thls should be done a f t e r the program Issues an Error Reset cmand. 'RCA . I s not discarded by SRC routlne, t h l s RCA I n t e r r u p t occurs. 1 "SRC = Rece lve Character Ava Il a b l e = Speclal Recelve Condl t l o n (hlgher p r l o r l t y than RCA) Reset TX CRC Data t o S10 (Address f l e l d byte) Reset TX Underrun/EOM l a t c h External/Status Chanqe (ESC) : Clear DCD, CTS, abort semaphores I f (abort) Set a b o r t semaphore Else I f (DCD change) Set DCD semaphore Else I f (CTS change) Set CTS semaphore Transmlt B u f f e r Empty 'TEE) : I f (MC cleared) Recelve Character A v a l l a b l e (RCA): Clear MC Set TX l n a c t l v e Reset TEE condl t l o n S t a r t Response t l m e r Read and dlscard data E1se, Store data ' Speclal Recelve Condltlon (SRC): Read SIO RRI Set EOF semaphore . E l s e I f (CRC e r r o r ) Set RX CRC e r r o r semaphore E l s e I f (RX overrun) Set RX overrun semaphore Issue E r r o r Reset ' Read data 6 dlscard Table 2. SIO SDLC I n t e r r u p t S e r v l c e Routlnes ' d e t e c t and DCD o r CTS change. Thls sectlon t l m e r t l m e s , out, . t h e l l n e I s I n an a b o r t another ESC I n t e r r u p t occurs, then t h e II I s l d l e and the program can'pursue an appr DCD and CTS Change. The program handles DM) . p r t a t e course of a c t Ion. A possl b l e mec cond 1t Ions. ' m o n l t o r s t h e semaphores and determlnes a course of actlon based on what these semaphores Indicate. Abort and l d l e A b o r t end I d l e L l n s [kt&. l l n e detect are a b l t more compllcated, slnce l d l e l lne I s detected. , counter I s programned f o r e l g h t c l o c k tr s l t l o n s and , I s s t a r t e d as soon as the Interrupts t h e WU wlth an a b o r t c o n d l t l On 1 y e l g h t c l o c k t r a n s l t l o n s need t o counted because by the tlme t h e SIO generat t h e ESC I n t e r r u p t , a t l e a s t seven I s have Thls detection can be l l n e actlve. I f another ESC I n t e r r u p t occurs wlthtn the abort wlndow and the abort b l t I s cleared, the program has detected an abort. Otherwise, when the counter/ tlmer explres, an l d l e 1 lne has been protocol. Perf s u l t l n g I n an ef t h a t reduces Following I s the l l s t l n g of a slmple SIO t e s t progam t h a t uses t h e SDLC p r o t o c o l . Thls sent. I f t h e response t l m e r explres, t h program on t h e n e x t h l g h e r l e v e l normall short SDLC control frame c o n s l s t l n g o f d r e s s 9EH, C o n t r o l 19H. and Data 81H. response t l m e r t l m e s t h e response o f r e c e l v l n g s t a t l o n a f t e r a message has AdThe the been t r a n s m l t count has n o t y e t expired). Th program transmits continuously u n t l l t processor I s r e s e t or Interrupted by an e ternal source. LOC TEST. SDLC OBJ CODE M STMT SOURCE STATEMENT 1 I 2 3 4 i C03 , SIO SDLC TEST PROGRAM . 01-21-81/MDP I N I T I A L CREATION before the an a b o r t 3ut before t h e Il n e an appro2 l e mechrndlon Is Is t l e d t o )Its. The ~ c kt r a n IS t h e S I O bndltlon. ed t o be 5 ; THIS PROGRAM SENDS ADDRESS 9EH, CONTROL 19H. 6 ; AND DATA B l H CONTINUOUSLY USING THE 2 9 0 VECTORED 7 i INTERRUPT MODE. THE S I O I S I N I T I A L I Z E D TO USE B ; SDLC WITH THE BAUD RATE CLOCK SUPPLIED BY ; HARDWARE INTERNAL TO THE SYSTEM. 9 10 11 i EQUATES 12 1 3 ADIXIESS: EQU 9EH IADDRESS F I E L D 1 4 CTU: EQU 19H ICONTROL F I E L D 1 5 DATA: EQU B1H 1INFORMATION F I E L D 1 6 M S ~ E N ' : EQU 1 iMESSACE LENGTH 1 7 RAM: EQU 2000H ;RAM O R I Q I N 1 8 RAb8IZ: EQU 1OOOH r RAM S I Z E 19 SICDA: EQU 0 r S I O PORT A DATA EQU SIODA+I IS I O PORT A CTRL 2 0 SIOCA: , 2 1 SICDB: EQU SIODA+2 I S I O PORT B DATA 22 SICCB: EQU SIODB+l r S I D PORT B CTRL EQU 8 ICIO PORT C 2 3 CICIC: CIm: EQU CIOC+l I CIO PORT B 24 23 CIW: EQU CIOC+2 ICIO PORT A 2 6 CICICTL: EQU . CIOC+3 I C I O CTRL PORT 27 BAUI: EQU 9600 r ASYNC BAUD RATE 28 RAE: EQU BAUD/100 2 9 CICCNT: EQU 9216/RATE 30 L I E : EQU OEOH r L I Q H T PORT 3 1 RSPCNT: EOU 100 IRESPONSE TIMER VALUE 32 33 i SIO PARAMETERS 34 3 5 SIIIJRO: EQU 0 36 CHRES: EQU 1BH I CH. RESET CMD 1OH IESC RESET CMD 37 ESCRES: EQU 38 TBERES: EQU 2BH I TEE RESET CMD J RETI CH. A 39 RETIA: EQU 3BH ENINRX: EQU 20H IENAB. INT. NEXT RX SRCRES: EQU ISRC RESET CMD 30H , RCRCRE: EQU 40H I RX CRC RESET CMD 8OH ITX CRC RESET CHD 43 TCRCRE: EQU 44 EOMRES: EQU OCOH IEOM RESET CMD 43 49 30 31 32 53 54 33 36 WREN: RDY: WRONR: RXIFC: RXIAP: RXIA: SIOSAV: EQU EQU EQU EGU EQU EQU EQU BOH 40H ZOH 8 1OH 1BH 4 TXI: EXTI: EQU EQU 2' I ;WAIT/RDY ENABLE IREADY FUNCT. ,WAIT/RDY ON RX INT. FIRST CHAR IRX INT. ALL + PARITY IRX INT. ALL ISTATUS AFFECTS VECT. I (CH. B ONLY) I TX INT. ENABLE IEXT. INT. ENABLE iRX I (CH. 59 60 61 62 63 64 63 CB 69 70 71 72 73 74 73 6 17- 1564-0001 SIWR3:- EOU RXB: RX6: RX7: RXS: AUTOEN: HUNT: RXCRC: ADSRCH: SYNINH: RXEN: 3 EQU EQU EQU EQU EQU EGU EQU EQU EQU EQU SIOJR4: 4 EQU EQU EQU EQU X64: X32: X16: ' OCOH BOH 40H 0 20H 1OH 4 .2 1 OCOH' BOH 40H B ONLY) ;RX 8 BITS IRX 6 B I T S iRX 7 B I T S $iRX 3 BITS r AUTO ENABLES i HUNT NODE IRX CRC ENABLE iADDR SEARCH ISYNC LOAD I N H I B I T 1RX ENABLE 164X CLOCK r 32X CLOCK I 16X CLOCK i 1X CLOCK , 2-25-8 1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EGU 30H 20H 1OH 0 OCH '8 4 0 2 EQU EGU EQU EQU EQU EQU EQU EGU EQU EQU 8OH 60H 40H 20H 0 1OH 8 4 2 EXTSYN: SDLC: SYN16: SYNB: STOP2: STOP15: STOPI: SYNCEN: EVEN: PARITY: 80 81 82 83 84 85 89 90 91 92 93 DTR: TXB: TX6: . TX7: TX5: BREAK: TXEN: CRC16: RTS: TXCRC: 93 96 97 99 100 101 102 i8 B I T SYNC i 2 STOP B I T S il.5STOPBITS i 1 STOP B I T iSYNC ENABLE ,EVEN PARITY iPAR I TYb ENABLE . ACT IVATE DTR ' i T X 8 BITS i TX 6 B I T S i T X 7 BITS iTX 5 BITS i TX BREAK i TX ENABLE iCRC-16 MODE iACTIVATE RTS i TX CRC ENABLE I SIOJR6: EQU 6 i LOW SI(WR7: EQU 7 i H I Q H SYNC OR FLAO SIOFLQ 106 107 i EXT. SYNC ENABLE i SDLC MODE i 16 B I T SYNC BIT' i = SYNC OR ADDR FLAQS FOR S I O STATUS --- SET CONDITION TX ACTIVE MESSAQE COMPLETE 115 116 117 118 119 121 122 123 124 127 128 0016 0010 OOlA OOlC OOlE , . 0020 0023 0025 0027 0029 OO2C OF01 3BOl 4301 4001 5101 - 314020 ED5E 3E00 ED47 214320 369E 132 133 134 135 136 137 138 139 140 144 7 i RX END OF FRAME *E **+ MAIN 1 1 JP PROQRAM *** BE0 I N I 0 0 MAIN PROORAM INTERRUPT VECTORS (MUST START ON EVEN BOUNDARY) \ I i OR0 a. AND. DEFW DEFW" DEFW DEFW . DEFW CHDSRC CHATDE CHAESC CHARCA CHASRC LD IM SP, STAK 2 iINIT LD (HL), ADDRESS i STORE ADDRESS iSTORE CTRL BYTE OFFFOH. OR. 1OH INNEC: SIWEC: . BEOIN: ' SP iVECTOR INTERRUPT MODE OBJ CODE M STMT SOURCE LOC 0041 00% 009F 00A2 00A4 MODE -- TC -I 2-25-8 OOA6 0049 OOAA OOAC OOAD OOBO 0003 0004 617- 1564-0007 CD7DOO . 155 ' BT~TEMEN; CALL AEM WAKF ,., CD3901 214020 CB4E 201D 210 2 11 212 213 CALL LD BIT JR HL, SIOFLQ 1. ( H L ) NZ, CHBTB2 3A4120 B7 280F 3D 324120 2A4320 7E D302 214 2 15 216 217 218 219 220 221 LD OR JR DEC LD LD LD OUT At (BYTES) A Z, CHBTBI A (BYTES), A HL, (BUFPTR) At ( H L ) (SIODB' A 573 rn 0 - OOBD OOBF OOCl 3EC0 D303 1809 00C3 OOC3 00C7 OOC9 CB8E CB86 3E64 324220 OOCC OOCE OODO 3E28 D303 C9 OODl 00D4 00D7 00D9 OODB OODD OODF OOEO 00E2 OOES 00E7 OOEA OOEC OOEF OOFl CD5901 214020 CB96 CB9E CBA6 DB03 47 CB58 C4FB00 CB68 C4FEOO CB7B C4F800 CB4E 2800 ' 00F3 00FS OOF7 3E10 D303 C9 OOF8 OOFA CDE6 C9 OOFB OOFD CEDE C9 OOFE 0100 CBDL C9 0101 0104 0106 0109 OlOA OlOB OlOE CDS901 DB02 2A8520 iSET ' OlOF 0112 0 11 4 0116 0118 0119 OllC OllE 0120 0123 0125 0128 012A 240 2 41 242 243 244 245 CHDESC: , CALL LD RES RES RES SAVE HL, S I O F L G 2, ( H L ) 3t(HL) 4,(HL) A, ( S I O C B ) CALL , 258 259 260 26 1 A, ESCRES (SIOCB),A OUT RET iRESET . ESC SETABT: SET 4#(HL) SETCTS: SET RET 270 2 71 272 273 274 RRO NZr SETDCD . 21(HL) CHDRCA: CALL IN SAVE A, ( S I O D B ) LD . LD H L t (RBPTR) (HL)rA jCH. B RX CHAR A V A I L . . # G E T READ BUFF PTR Ol6D (RBPTR), H L 279 280 2 81 282 283 '284 285 286 287 Ol6F CHKRC: CALL LD OUT IN LD LD RES BIT CALL SAVE At 1 ~SIOCB),A AI ( S I O C B ) B, A HL, S I O F L O 6, ( H L ) 7, B NZ, SETEFF CALL NZ, SETOVR csbe C43201 j CH. B EXTERNAL/STATUS r QET FLAG BYTE iREAD 228520 C9 CD5901 3EOl D303 DB03 47 , 214020 CBB6 CB78 C43801 CB70 C43501 MC FLAG ,(SIOCB), A A* RSPCNT 266 77 23 OUT, 228 ICH. B S P E C I A L AX CON r READ RR 1 I SAVE I N %B i C L E A R CRC r CHECk EOF iBRANCH I F iCHECK CRC 0170 ERROR FLAG BIT NOT EOF ERROR )CHECK OVRRUN B I T . ' 0174 0175 0 17 6 0 17 7 0 17 9 TEST. SDLC OBJ C 0 D E . M STMT SOURCE STATEMENT 368 SIOTB: 017A 00 369 DEFB SIOWRO . ICHAN. RESET DEFB CHRES 0170 18 , 370 IVECTOR REG. 02 371 DEFB SIOWR2 017C DEFB SIOVEC. AND. 2 5 5 372 0 1 7 D . 10 SIOWR4 DEFB 04 373 017E DEFB X 1 +SDLC+SYNC6N 20 374 017F . iCHAN. CHARACS. SIOWRl 375 DEFB 0180 . 0 1 IF 376 DEFB RXIA+SIOSAV+TXI+EXTI 0181 06 377 DEFB SIOWR6 I ADDRESS 0182 9E 378 DEFB ADDRESS 0183SIOWR7 07 379 DEFB 0184 7E 380 DEFB 01 11111OB Ol'85 0 5 3 8 1 DEFB SIOWR5 r TX PARAMS. 0186 E B 3 8 2 DEFB DTR+TXB+TXEN+RTS+TXCRC 0187 IRX PARAMS. ' 03 383 DEFB SIOWR3 0188 0189 Cl ' 384 ' DEFB RXB+RXEN 3 8 5 SICEB: EGU S LOC 386 018C Ol8D Ol8E '018F 0190 0191 0192 0193 0194 0195 0196 0197 2B EE 1C C2 16 00 17 390 39 1 392 393 394 395 . 60 01 Fo . , 399 OA 06 403 DEFB DEFB DEFB DEFB DEFB DEFB DEFB DEFB DEFB DEFB DEFB DEFB DEFB DEFB 28H OOOOOOOOB 2BH 111OlllOB ICH 11OOOOlOB . ' 1 6 ~ 0 17H CIOCNT 1 111lOOOOB 10 0 0 0 0 0 1 1OB RAM IPORT B MODE I DATA DIRECTION IC T l MODE IC T l IMASTER REG. j C T 1 TRIGGER . ORG 409 STPH: EQU ISTACK . iS I O 6 17-1564-0007 CONFIQ. *E 407 411 412 413 414 415 416 TC MSB BYES: RSPTMR: BUFPTR: BURER: RBPTR: RBV: DEFS DEFS DEFS DEFS DEFS EGU 1 1 2 64 2 * 576 AREA $ . FLAG BYTE IBUFFER BYTE COUNT IRESPONSE TIMER IBUFFER POINTER I BUFFER i READ BUFF PTR Binary Synchronous Communication Using the 1 8 0 SIO Application Note A popu l a r comnunlcatlon protocol used to exchange lnformatlon tatween data processlng devlces has been I n use f o r some tlme. Thls protocol, developed by IBM, I s cal led blnary synchronous protoco I, o r b l sync. The ZBO SIO provldes a f l e x l b l e and powerful t o o l f o r the lmplernentatlon of the blsync protocol. How- , ever, there are some deslgn conslderatlons t h a t requlre speclal attentton. Thls paper w I I I dlscuss these deslgn conslderatlons and o f f e r an approach t o uslng blsync wlth the ZBO SIO. Speclflc examples are presented and readers who are unfamlllar w l t h t h e blsync protocol should r e f e r t o t h e ANSI standard (1) o r the IBM publlcatlon (2) l l s t e d a t the end of t h l s paper. , Blsync I s a character-orlented protocol wlfh lnformatlon transmltted I n blocks between two (or more) data communlcatlon devlces. The medlum through whlch t h l s lnformatlon I s conveyed I s ca l led the data I 1nk. The part l c u l a r data lInk discussed I n t h l s paper I s a polnt-to-polnt l l n k uslng t h e ASCII transmlsslon code. M h e r codes, such as EBCDIC, are not covered, but the format f o r blsync I s basically the same. The data l l n k conslsts of a master s t a t l o n (usually a computer) and a slave s t a t l o n (usually a terminal) wlth the associated communlcatlon gear I n between-modems, phone Ilnes, etc. The master s t a t l o n controls message flow by p o l l l n g and selectIng the slave statlon. Pol l l n g lnvolves sendIng a general request message t o t h e slave statlon(s) t o deterrnlne whether o r not'any of the slaves have data t o send ( t r a f f lc). If a slave statloti does have t r a f f l c , It responds t o the p o l l and the master can then select t h a t particular slave f o r Information exchange. Slaves can only respond t o a master devlce and cannot l n l t l a t e communlcatlon on the data IInk. . lnformatlon I s exchanged by means of a we1 1Message blocks def lned block structure. conslst of a header, body, and t r a l l e r (Flgure 1). The header I s made of two o r more SYN characters (hence the name blsync), a s t a r t of header (SOH) character, and addresslng and control lnformatlon f o r a p a r tl cular slave s t a t Ion. Ftgure 1. Bastc Fkusg. Block Foclat f o r Blsync R o t o o o t The body beglns wlth a s t a r k o f t e x t (STXI character and encompasses the ent I r e t e x t Informat Ion. The body general l y contalns ASCII t e x t data, although 8-blt blnary data can be transmltted uslng transparent t e x t mode. The t r o l l e r contalns the end o f t e x t (ETX) character and the block check character (BCC). The 802 I s used f o r d e t d l n g errors through "cycllc redundancy checklng",(CRC) o r nlongltudal redundancy checklngn (LRC). Error d e t e d l o n I s essentlal when transferr l n g lnformatlon between data processlng equlpmmt. Slnce ASCI I speclf les only seven b l t s r f o r I t s code, t h e elghth b l t I s used f o r v e r t l c a l redundancy checklng (VRC), m r e c-nl y known as character parlty. I n synchronous comnunlcatlons, character p a r l t y I s generally odd, whereas I n asynchronous cornmunlcatlons It I s even. Flgure 2 shows t y p l cal ASCII characters w l t h parlty. The SIO can be,programned f o r 7-blt characters wlth odd p a r l t y enabled to rnlnlmlze 'software overhead. This appllcatlonnote refersto productsas 280 "A", "B" etc. to speclflythe speed grade. We are no longer uslng those charactersfor the speeds. For more details, please refer to the orderlng information sectbn. . tages resu It from t h Is. FIrst, the maste and slave requlre a means o f conversion, e l t h e r software or hardware, addlng cost the data IInk. Slnce the slave (terminal) I s burdened most by thls, such an approach I s usually not feasible. The other disadvantage I s t h a t the exchange of lnformatlon I s slower Figure . 2 Odd VRC. N u m k of 1s should k odd. Because VRC applles only t o t h e IndlvIdual character, the e n t l r e message block has an LRC t h a t makes up the BCC. The LRC I s a slmple b l t posltlon checksum where the number of IS f o r each posltfon (O through 6) IS even f o r a block o f data. Slnce t h e BCC I s a character, LRC I s subject t o t h e same character p a r l t y rules as the r e s t of t h e data block. The LRC Includes a l l characters, / cannot calculate the LRC, the task I s l e f t up -to the user. LRC can be generated on a mlcroprocessor wlth l l t t l e e f f o r t by taklng the massage block and Xmlng the data w ~ t han l n l t l a l value of zero t o provlde even LRC. Flgurm 3. Characters Includad I n BBC Another type of BBC I s generated by a cyc lI c redundancy check (CRC), wh lch r e s u l t s I n a more powerful method of block checking. CROIZ I s used f o r 6 - b l t transmlsslon code and CRC-16 I s used f o r 8 - b l t transmlsslon code. CRC I s used I n l Ieu of character p a r i t y and LRC, as wIth transparent t e x t mode The remainder of t h l s paper I l l u s t r a t e s how t o use t h e SIO I n three speclal cases of the blsync protocol: transparent text'mode, abort/Interrupt procedures, and e r r o r recovery procedures. Transparent t e x t mode I s useful I n blsync when lnformatlon exchanged between master and slave I s not ASCII data. For example, a blnary data f Il e (obJect program) mlght be sent from master t o slave. ASCl l transmls. slon code I s only seven b l t s long maklng It d l f f l c u l t t o send 8-blt blnary data. One t o t h e slave and r e m n v e r t . I t back I n t o blnary a t the slave. However, two dfsadvan- mode transmlsslon. I n t h l s mode, charac p a r l t y I s dlsabled, allowlng t h e f u l l e l b I t s to be used f o r data. However, t o a control w l t h l n the conStraIntJ of the Pr col, there are c e r t a l n llmItatIons on t h blnarY data pattern* The PrlmarY d f f f e r ISt h a t during transparent mode 5catlon control characters are preceded b character, actual l Y makfng the c o n k characters a two-character sequence. To shows the c m m n f c a t l o n control characters t h a t are v a l l d durfng transparent mode. Another character change occurs when the SYN character I s used f o r llne f I 1 I. Normal ly, the SYN character I s Ignored, but durlng transparent mode t h e SYN I s preceded by a DL€, and both are consequently Ignored by t receiver. I n t h e event t h a t the CPU does n have a character ready t o send, the SIO aut matlcally Inserts SYN characters I n t o the data stream. WIth the SIO programmed f o r 16-blt sync characters, two syncs are sent from the Sf0 ( w r l t e ' registers WR6 and WR7) when I t s transmlt buffer I s empty. I n trans parent mode, the user r u s t change WR6 and WA t o DLE,SYN I n order f o r t h e SIO to provlde In accordthe proper l lne f 1 I 1 characters. ance wlth t h e ANSI standard, l l n e f l l l characters are not Included I n the SIO CRC calcu l a t l o n dur lng transml t. Durlng recsptlon In transparent mode, the software must dlsable CRC accumulation when t h e DLE SYN character sequence I s detected. Whlle I n transparent mode, the user must be concerned wIth the e r r o r detectton codes. I . p a r l t y I s enabled I n the SIO normal ly, It must be dfsabled durlng transparent mode. Thls change I n SIO operatlon a f fects both transmlt and recelve and should therefore considered I f uslng f u l l duplex. master slon, by cost t o mlnal) I s ~ a c hIS sadvantage I s slower ; a r e sent The ;end ing ~ n tte x t aracter I elght t o allow e proton the f ference commun Isd by a 3ntrol To 31 DLE, mother the f l r s t >le 1 ~cters ' Ing by a d by t h e does n o t 10 autothe for sent WR7) n transand WR7 -ov ide accordI char:calcutlon I n 'sable 'acter Table 2.. The sendlng s t a t l o n abort I s s l m l l a r t o the block abort, except t h a t the sendlng s t a t l o n does not necessarily do a block abort but slmply ends the current message block, walts f o r a response o r tlmeout, and then sends bn EOT t o regaln control o f t h e data Ilnk. The sendlng s t a t l o n abort I s useful when transmlsslon t o a p a r t l c u l a r recelver I s necessary due t o a hlgher p r l o r l t y message, b u f f e r overflow condltlon, e r r o r detectlon, etc. Once the sending s t a t l o n abort sequence I s made, the master can perform any data IInk control functlon. From the recblver slde, a termlnatlon lnterr u p t causes t h e sendlng s t a t l o n t o stop transmlsslon. Such a procedure i s useful when the recelver cannot accept any more data o r Incurs an e r r o r condltlon, such as paper Jam, card Jam, hardware error, etc. To accompl lsh a termlnatlon Interrupt, the recelvlng stat l o n sends an EOT lnstead of t h e normal response. The EOT resets a l l s t a t l o n s on t h e l l n k and allows t h e master t o Issue any cont r o l sequence. Characters I n c l u d e d / 0 m i ~ In CRC During Transparent Mode Omltted from CRC Included I n CRC OLE OLE DLE DLE ETX ETB STX SYN SOH STX* * I f n o t preceded by transparent header w l t h l n same block of of of of DLE DLE DLE DLE DLE ETX ETB STX** , # * I f preceded by DLE SOH w l t h l n same block The reverse l n t e r r u p t (RIM) I s used when the recelvlng s t a t l o n needs t o transmlt durlng reception o f several message blocks. The R I M occurs when a recelver detects a v a l l d CRC o r LRC and, lnstead o f returnlng an ACK, sends a DLE "<" character sequence t o slgnal an a f f l r m a t l v e acknowledgement and t o stop transmlsslon of data. Some exceptlons and a more detalled descrlptlon o f R I M can be found In t h e ANSI standard. . 1st be les. If It de. 0th o r e be *l block sequence I s used. Slnce a block abort puts the data l l n k back I n nontransparent mode, NAK I s t h e v a l l d response t h e recelver should send I n both transparent and nontransparent modes. Stnce t h e SIO allows CRC enable/dlsable on the f l y , the software can e a s l l y c o n t r o l CRC accumulatlon I n both recelve and transmlt. Durlng transmit, t h e CRC must be enabled/ dlsablqd before the character I s transferred During rel n t o the s e r l a l s h l f t reglster. celve, t h e CRC accumulatlon I s delayed e l g h t blts. A f t e r t h e ctiarader I s transferred frm t h e s e r l a l s h l f t r e g l s t e r l n t o t h e buffer, t h e user has t o read t h a t character, declde whether o r not t o contlnue CRC accumulation, and dlsable/enable CRC before t h e next character I s transferred t o t h e buffer. Thls I s not generally a problem, slnce character t r a n s f e r s occur about every 833 m l c r b seconds a t 9600 baud. Table 2 shows t h e characters Included and omltted I n the CRC durlng transparent mode. When CRC accumulatlon I s t o be resumed, the software should enable CRC before t h e deslred character I s transferred t o t h e recelve buffer. For example, suppose a DLE p a l r I s recelved during transparent t e x t mode. The 510 generates an l n t e r r u p t when t h e f l r s t DLE I s transferred t o the recelve buffer. The d r l v e r program reads t h e DLE and lmmedlately dlssbles CRC. When the next l n t e r r u p t occurs, t h e d r l v e r reads t h e second DLE and I d l a t e l y enables CRC t o Include the second DLE i n t o t h e CRC accumulatlon. The temporary l n t e r r u p t procedure, WACK (Walt. Before Sendlng P o s l t l v e Acknowledge), I s used by t h e recelvlng s t a t l o n t o lndlcate p o s l t l v e acknowledgement and an I n a b l l l t y t o recelve more data. Such a response may be necessary when the recelvlng s t a t l o n cannot accept data contlnuously, such as durlng a p r l n t l n g operation. The WACK conslsts of a DLE ";" character sequence and I s sent I n place of an ACK o r ACKn. The sendlng s t a t l o n then sends E y s (Enquiry) u n t l l t h e recelvlng s t a t i o n stops sendlng WACKs. The sendlng s t a t l o n can' resume transmitting data when t h e receivlng s t a t l o n sends an ACK o r ACKn. The second category of i n t e r e s t Includes I abort and i n t e r r u p t procedures. There are &O types o f aborts: block abort and .sending s t a t l o n abort. There are three types o f termlnatlon Interrupt, reverse Interrupts: l n t e r r u p t and temporary Interrupt. The block abort I s used by the sendlng stat l o n when, I n the process o f transmlttlng a data block, t h e sending s t a t l o n detects an e r r o r condltlon I n the data and decldes t o tennlnate the block so t h a t t h e recelvlng s t a t l o n w l l l dlscard It. I n nontransparent mode, block abort I s accompl lshed by endlng the block w l t h an ENQ character, lnstead o f ElX o r ETB. The sendlng s t a t l o n then walts f o r a r e p l y f r m t h e recelver, whlch should be a NAK. The transparent mode procedure i s l d a n t l c a l except t h a t a DLE ENQ character Recovery procedures provlde a means of pre-' venting data l l n k I n s t a b l l l t y . The recovery mechanism conslsts malnly of timers, grouped l n t o four baslc areas, and a NAK counter. The NAK counter I s used t o prevent repeated NAKs frcm l n h l b l t l n g f u r t h e r communlcatlons. The sendlng u n i t counts how many NAKs It recelves f o r a p a r t l c u l a r data block so t h a t a f t e r a predetermlned number o f r e t r l e s , It can recover and pursue another course o f '9 10/24/80 , adlon. The particular count value and course of actlon taken when t h e count explres are l e f t up t o t h e user. Four timers (tlmer A o r response timer, timer B o r recelver tlmer, tlmer C o r gross tlmer, and tlmer D o r no a c t l v l t y tlmer) prevent the data l l n k frcm g e t t l n g "hung" o r golng I d l e f o r extended perlods o f tlme. General ly, the shortest i n t e r v a l I s used with t i m e r A, and the longest Interval i s used w l t h tlmer D. For maxlmum system e'fflclency, however, t h e receiver tlmer (tlmer B) should tlmeout The before t h e response tlmer (tlmer A). p a r t i c u l a r lmplementatlon of these tlmers varles from system t o system, and some f 19x1b l 1 lty of exact tlmer values i s l e f t up t o the user. Slnce It I s assumed t h a t i n t e r r u p t s w l l l be used wlth t h e SIO, an I n t e r r u p t drlven recelver tlmer count I s kept I n memory and I s r e l n l t l a l lzed each time a character I s r e celved (recelve Interrupt). The same applles f o r t h e response tlmer, except t h a t when a tlmeout occurs, the transmlt d r l v e r has several optlons t o follow. I f t h e SIO i s set t o transmit CRC on transmlt underrun, then the d r l v e r could slmply s e t I t s flags and n o t f 1I I the buffer. Thls a1 lows a normal exlt, slnce t h e SIO w l I I then send i t s CRC bytes. If t h e SIO i s s e t t o n o t transmlt CRC on transmlt underrun, then It sends sync characters (SYN SYN o r DLE SYN, whichever was l a s t w r l t t e n t o WR6 and WR7) u n t l l the transmit b u f f e r i s f l l l e d o r transm l t data I s set to marklng. properly decode CRC. Because o f t h e character delay I n the S10 durlng CRC accumulatlon, about 20 clock cycles are necessary a f t e r t h e l a s t CRC byte I s sent to ensure adequate decoding tlme. (See the SIO Technica I Manual f o r f u r t h e r detal Is.) The SIO could be programned t o send pad characters e l t h e r by dlsabllng p a r i t y and sendlng 8 - b l t FFs (hex) o r by f 1I 1 l n g WR6 and hR7 w i t h FF hex. I f enabled, t h e SIO automatlcal l y sends whatever I s I n i t s sync r e g i s t e r s upon transm l t underrun. M u l t l p l e message blocks do not have t o be separated by pad characters as long as CRC I s v a l l d f o r the prevlous message block. However, t o insure adequate tlme f o r the recelver t o process CRC, It i s recunmended t h a t a t least two pad characters follow t h e l a s t character o f a block. Using t h e SIO f o r t h e blsync protocol I s f a i r l y stralghtforward. Care should be exerclsed when uslng t h e SIO I n transparent t e x t mde, but the lnplementatlon i s g r e a t l y s l m p l l f led by t h e SlO's f l e x l b l l i t y , as cunpared t o other s e r l a l communlcatlons ICs. The CRC c a p a b l l i t i e s of t h e S10 provide a powerful means o f maintalnlng imxlmum data I n t e g r i t y with mlnimum software overhead. with the Ond the Interrupt capabllltles the ZBO processor, the user will f l n d the SIO an excel l e n t cholce I n serving data communicatlOn needs* - (1 Amarican Natlonal Standards Institute. ANSI X3.28 1976. - (2) "General lnformatlon Binary Synchronous Ccmmuni~ations.~ Pub. number GA273004-2. I n any event, enough time must be allowed b f t e r CRC i s sent so t h a t the receiver can 580 . , I s used CTC and and ferred t o t r a n s f e r 1nformatlonJetween t h e CPU. The c o n t r o l Ilnes, RD, ICRQ, MI, determine what data I s b e l n g t r a n s and when. M1 and a r e used durlng E, .Table 1. Channel S e l e c t Values c a r e f u l n o t t o overload t h e d r l v e r . The cap c l t a n c e o f t h e c l o c k lnput t o t h e CTC (20 p should be noted as t h l s may a f f e c t t h e syst c l o c k r l s e and fa1 1 tlmes. The CTC I n t e r n a l l y p r l o r l t l z e s each counter/ t l m e r w l t h respect t o I n t e r r u p t g e n e r a t l o n , Th I s mar lmlzes performance by resolving cont e n t lon between channe I s shou 1d t w m o r more l n t e r r u p t c o n d l t l o n s occur slmultaneously. Table 2 shows t h e r e l a t l v e p r l o r l t y l e v e l s of each counter/tlmer w l t h l n t h e CTC. Channel 2 Channel 3 Table 2. CTC Channel l n t e r r u p t Prlortty The CTC system c l o c k lnput iequlrements a r e s l m l l a r t o those o f t h e 280 CPU. F o r both, t h e system c l o c k lnput Low l e v e l should be no greater then 0.45 V, t h e Hlgh l e v e l should'be CTC FKX)ES There a r e two baslc modes under whlch t h e CTC can operate: Tlmer mode and C o u n t e r mode. Each mode has c e r t a l n programmable character- l s t l c s t h a t enable t h e CTC t o be used I n a wlde v a r l e t y o f appllcatlons. TIMER MODE A t y p l c a l use o f t h e CTC I n Tlmer &de I s t o provlde regular, f lxed-Interval I n t e r r u p t s t o t h e CPU used as a tlme-base r e f e r e n c e t o a l l o c a t e t h e processor resources e f f l c l e n t l y. For example, a m u l t l t a s k l n g system mlght have t h e processor execute a t a s k f o r a glven l e n g t h o f t l m e and then l n t e r r u p t executlon o f t h e program a t one-second I n t e r v a l s t o scan t h e t a s k queue f o r h l g h e r - p r l o r l t y tasks. Thls sys'tem t l m e l n t e r v a l can be p r o - Another use o f CTC Tlmer mode operatlon I s t o implement a n o n r e t r l g g e r a b l e one-shot u s l n g e x t e r n a l c l r c u l t r y . The d l g l t a l approach t o t h e o n c s h o t p r o v l des a programmab 1e t lme d e l a y under CPU c o n t r o l and provldes greater nolse lmmunlty than t h e more common analog -+lay c l r c u l t s provlde. F l g u r e 3 shows a c l r c u l t t h a t uses p a r t o f a 74LS02 package I n a d d l t l o n t o one CTC channel. 256) I s possible. IAc l o c k d r l v e r by Hybrld House, 1615 Remuda La., 75 1-1809-0003 602 San Jose, CA 951 12. LOC TEST CTCO OBJ CODE M STMT SOURCE STATEMENT 003D 003E FB ED4D 0040 0043 0046 0047 004A 004B 004D 0050 0953 0 ~ 5 4 0097 0059 CD5AOO 3A4020 3D 324020 CO 3E78 324020 3A4120 2F 324120 D3EO C9 005E GO01 0062 (3063 0064 Ooh5 0666 €3 D5 C5 F5 CD68OO F1 C1 Dl E l FR ED4D OPb8 €9 OO5A 0050 1>05C OO5D ' 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 ICTC1: ICTC2 ICTC3 ICTCO. CALL LD DEC LD RET LD LD LD CPL LD OUT RET SAVE A, (COUNT ) A (COUNT), A NZ A, TIME ( COUtdT) * A A, ( D I S P ) I SAVE ROUTINES REGISTERS ,CHANGE TIMER COUNT ,EXIT 1 , ~ I F NOT DONE RESET ~ ~ ~ TIMER , ,Dl. I N K L I T E S (DISP),A (LIT€), A SAVE REOISTER ROUTINE * SAlE EX PUSH PUSH PUSH CALL POP POP POP POP EI RET I 94 95 96 97 98 99 100 101 102 103 104 105 106 107 ; DUMMY €1 RETI (SP)>HL DE BC AF GO AF BC DE HL GO (HL) JP DATA AREA 111 ORG DEFS RAM 64 DEFS 1 I STACK AREA jTlMER COUNT VALUE 116 117 118 RUPT MODE DIP. END I 75 1- 1809-0005 , L I T € DISPLAY BYTE VALVE 2 3 4 5 i i i 9 i THIS PROGRAM USES THE CTC I N CONTINUGUS ' TIMER NODE. THE CTC SUPPLIES A B I T RATE CLOCK TO THE SIO FROM THE SYSTEM CLOCK. THE SYSTEM CLOCK I S 3 . 6 8 6 4 NHZ, WHICH I S DIVIDED BY 1 6 BY THE PRESCALER, AND DIVIDED BY A TIME CONSTANT VALUE OF 3 TO PROVIDE A 16Xn 4 8 0 0 BAUD CLOCK TO THE SIO. OTHER BAUD RATES CAN BE OBTAINED BY PROGRAMWINO DIFFERENT TINE CONSTANT VALUES INTO THE CTC. 10 i 13 14 i PROGRAM EQUATES 16 17 18 19 PO 21 CTM: CTCl: CTC2: CTU: TIM: EQU EQU EQU EQU EQU 23 24 25 26 27. 28 29 30 i CTC EQUATES ccw: EQU INTEN: EQU CTRMODE: P256: EQU RISEDG: EQU PSTRT: EQU TCLOAD: EQU RESET: EQU 15 34 35 0000 0002 0004 0006 0008 3E07 D30E 3E03 D30E 18FE 39 40 41 42 43 44 45 46 47 i ; *** 12 CTCO+1 CTCO+2 CTC0+3 3 I 80H EQU 20H 1OH 8 4 MAIN PROGRAM LD OUT LD OUT i CTC 0 PORT CTC 1 PORT i CTC 2 PORT r CTC 3 PORT ;TIME CONSTANT VALUE i 401j *** A, TCLOAD+RESET+CCW (CTC2)t A i SET CTC MODE A, TINE (CTC2). A i SET TIME CONSTANT MAIN PROORAM COE9 HERE +E JR S ' r LOOP FOREVER Flgure 5. would use t h e CTC t o check t h e t a s k queue t o t h e transmlt clock l lne o f t h e s e r l a l d e v l c e s have no way t o determlne the status of sync characters sent, t h e user must use hand I lng softrare. Flgure 6 shows t h e needed t o achleve the countlng functlo LOC TEST. CTC 1 ODJ CODE M STMT SOURCE STATEMENT DATA AREA ORG RAM ' i STACK AREA i L I T E DISPLAY BYTE 106 END INITIALIZE CPU ENABLE INTERRUPTS READ FLAG BYTE SET FLAG BYTE RESTORECPUSTATUS a) Maln Program b) I n t e r r u p t Servlce Routlne TEST. CTC3 LOC 75 1- 1809-0005 OBJ CODE 0041 0042 FB ED4D 0044 0045 0047 0049 004C 004E 0051 0052 0053 08 3E03 D30F CiA0020 CBC7 320020 08 FB ED4D M STMT SOURCE STATEMENT 73 74 75 76 77 78 79 80 IClc2: IDUMMY INTERRUPT ROUT1 I EI RETI ICTC3: AF, AF' A, 0000001 1 8 (CTCJ), A EX LD OUT J RESET CTC 3 r SET PROGRAM FLAG 85 86 87 88 89 EI RETI *E I I DATA CIREA 61 1
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