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•
iSBC 21S™
WINCHESTER
DISK CONTROLLER
HARDWARE REFERENCE MANUAL
•
Order Number: 121593-002
•
•
•
I
Copyright
©
1980, 1981 Intel Corporation
REV.
PRINT
DATE
REVISION HISTORY
-001
Original Issue
1181
-002
Manual updated for minor corrections.
9/81
•
•
Additional copies of this manual or other Intel literature may be obtained from:
Literature Department
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
•
The information in this document is subject to change without notice.
Intel Corporation makes no warranty of any kind with regard to this material, including, but
not limited to, the implied warranties of merchantability and fitness for a particular purpose.
Intel Corporation assumes no responsibility for any errors that may appear in this document.
Intel Corporation makes no commitment to update nor to keep current the information
contained in this document.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry
embodied in an Intel product. No other circuit patent licenses are implied.
In tel software products are copyrighted by and shall remain the property of Intel
Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel's software
license, or as defined in ASPR 7-104.9(a)(9).
•
No part, of this document may be copied or reproduced in any form or by any means without
the prior written consent of Intel Corporation.
The following are trademarks of Intel Corporation and its affiliates and may be used only to
identify Intel products:
HXP
CREDIT
i
ICE
iCS
im
INSITE
Intel
Intel
Intelevision
Intellec
iRMX
iSHC
iSBX
Library Manager
MCS
Megachassis
Micromainframe
Micromap
Multibus
Multimodule
Plug·A·Bubble
PROMPT
Promware
RMXIRO
System 2000
UPI
IlScope
and the combination of ICE, iCS, iRMX, iSBC, iSBX, MCS, or RMX and a numerical suffix.
11
•
•
[ ______________.________
P_R_E_F_A_C_E~
This manual provides information regarding the installation, programming,
operation, and servicing of the iSBC 215™ Winchester Disk Controller.
Relateci documents include:
•
•
The SOS6 Family User's Manual, Order No. 9800722
•
Intel MULTIBUgrM Specifications, Order No. 9800683
•
Intel SOSO/S085 Assembly Language Reference Manual, Order No. 9800301
•
MCS-S6™ MACRO Assembly Language Reference Manual, Order No. 900640
•
MCS-86/SSTM Family User's Manual, Order No. 121506
•
S089 Assembler User's Guide, Order No. 9800938
•
iSB)(fM Bus Specification, Order No. 142686
•
iSBX 21S™ Flexible Disk Controller Hardware Reference Manual, Order No.
121583
•
•
•
111
CONTENTS
CHAPTER 1
GENERAL INFORMATION
CHAPTER 2
PREPARATION FOR USE
Introduction .................................... 2-1
Unpacking and Inspection ...................... 2-1
Board Installation Considerations .............. 2-1
Power Requirement ........................... 2-2
Cooling Requirement ......................... 2-2
Multibus Connector ............................. 2-2
Switch/Jumper Configurations ................. 2-2
Wake-Up Address Selection ................... 2-6
Wake-Up 110 Port Address Selection ......... 2-7
System Data Bus Selection ................... 2-7
Interrupt Priority Level ....................... 2-7
Any Request Selection ........................ 2-7
Common Bus Request .......................... 2-7
Winchester Drive Interface ..................... 2-7
-5- V olt Selection
(8" Shugart/Quantum Drives Only) ........... 2-8
Cabling Requirements ........................ 2-8
Drive Installation ............................. 2-9
iSBX Multimodule Interface ................... 2-22
iSBX 218 Board Installation ................... 2-23
Power Up/Down Considerations ............... 2-24
Diagnostic Check .............................. 2-24
CHAPTER 3
PROGRAMMING INFORMATION
Introduction .................................... :3-1
Programming Options .......................... 3-1
Disk Organization .............................. 3-1
Track Sectoring Format ........................ 3-2
Controller 110 Communications Blocks ......... :3-2
Host CPU-Controller-Disk Drive Interaction .... 3-4
Wake-Up 110 Port .............................. 3-4
Wake-Up Block ................................. 3-4
Channel Control Block ......................... 3-4
Controller Invocation Block ..................... 3-4
110 Parameter Block ........................... 3-4
Typical Controller Operations ........ . . . . . . . . .. 3-6
Initializing the Controller ..................... 3-6
Track Formatting ............................. 3-9
Alternate and Defective Track Handling ..... :3-12
Data Transfer and Verification .............. 3-12
Read Sector ID .............................. 3-1:3
Read Data ................................... 3-1:3
Read Data Into Controller Buffer and Verify :3-14
Write Data .................................. 3-15
Write Data from Controller Buffer to Disk ... 3-15
Initiate Track Seek .......................... :3-15
IV
Page
Page
Introduction .................................... I-I
Description ..................................... 1-2
Specifications ................................... 1-3
Execute iSBX 110 Program ..................
110 Transfer Through iSBX Bus ............
Buffer 110 ...................................
Diagnostic ...................................
Posting Status .................................
Transfer Error Status ..........................
Interrupts ......................................
Controlling Data Transfer
Through the iSBX Bus ....................
110 Transfers Using iSBC 215
Controller Resident Firmware ..............
Data Transfer Using User Written
110 Transfer Programs ....................
Example Controller 110 Program ..............
•
:3-16
:3-16
3-17
3-18
:3-18
3-19
3-20
:3-20
:3-20
:3-20
3-2:3
CHAPTER 4
PRINCIPLES OF OPERATION
Introduction .................................... 4-1
Schematic Interpretation ........................ 4-1
Functional Overview ............................ 4-2
Detailed Functional Description ................ 4-5
Controller to Host Communications ............. 4-6
Multibus Interface .............................. 4-6
8089 I/O Processor (lOP) ....................... 4-6
Clock Circuit ................................... 4-6
Bus Arbiter ..................................... 4-7
Bus Controller Logic ............................ 4-8
Multibus Interface
Data Transfer Logic ........................ 4-8
Controller Initialization ......................... 4-8
Wake-Up Address Comparator .................. 4-9
Controller Reset and Clear .................. 4-10
Establishing A Link With
110 Communications Blocks ............... 4-10
Interrupt Priority Logic ........................ 4-11
Local Memory Map ............................ 4-11
ROM .......................................... 4-11
RAM .......................................... 4-11
Local Memory Mapped 110 Ports
and iSBX 110 Ports ....................... 4-11
Controller to Disk Drive Communications ..... 4-12
Controller to Winchester
Disk Drive Interface ....................... 4-12
Control Cable Signals ......................... 4-1:3
Read/Write Cable Signals ..................... 4-14
Controller to iSBX Connector Interface ........ 4-14
Controller to Disk Drive Interface Timing ..... 4-15
DMA Mode .................................. 4-15
Disk Formatting ............................. 4-16
Write Data Transfer ......................... 4-18
Read Data Transfers ........................ 4-20
SER/DES Logic ............................... 4-20
Sync Byte Comparator Logic ................ 4-21
•
•
•
•
[
•
CONTENTS (Continued)
----Page
Page
32-Bit ID Comparator Logic ...................
ECC Generator Logic ..........................
Status Register Logic ..........................
Line Drivers and Receivers ....................
4-21
4-21
4-21
4-22
Service and Repair Assistance .................. 5-1
Self Diagnostic ................................. 5-1
Replaceable Components ........................ 5-1
CHAPTER 5
SERVICE INFORMATION
APPENDIX A
Introduction .................................... 5-1
Service Diagrams ............................... 5-1
EXAMPLE HOST PROCESSOR
DISK CONTROL PROGRAM
HANDSHAKE SEQUENCES AND
•
•
[ _______________________T_A_BLES
Table
1-1.
1-2.
2-1.
•
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-R.
2-9.
:1-l.
:3-2.
3-3.
•
Title
Page
Board Speciflcations ................... 1-:3
Winchester Disk Drive
Characteri,;tics ....................... 1-5
Multibus Connector PI
Pin Assignment ...................... 2-2
iSBC 215 COl1troller/Multibus
Interface PI Signal Descriptions ..... 2-3
iSBC 215 Controller/Multibus
Interface Signal Characteristics ...... 2-6
Configuration Jumpers and Switches .. 2-7
Interrupt Priority Level Selection ...... 2-7
Winchester Drive
Manufacturer Selection ............... 2-8
-5-Volt Selection ....................... 2-9
J3 and J4 Pin Assignments ........... 2-22
iSBX Bus Control Jumper Pins ....... 2-24
Error Status Buffer ................... 3-20
Bit Functions in Hard and
Soft Error Bytes .................... 3-21
iSBX Bus IIO Port Addresses ......... 3-22
Table
:'3-4.
3-5.
3-6.
3-7.
4-l.
4-2.
4-::3.
4-4.
4-5.
4-6.
4-7.
4-S.
5-l.
5-2 .
Title
I
Page
iSBC 215 Controller RAM
Available for Program and
Parameter Storage .................. 3-22
SOS9 Handshake and Control Lines
on the iSBX Bus .................... 3-22
Control and Status Lines
on the iSBX Interface ............... 3-23
J urn per Connections Allowing Option
Lines to be Driven .................. 3-23
80R9 Status Line Decodes .............. 4-R
Host Wake-Up Commands ............. 4-9
Local IIO Ports ....................... 4-12
iSBX Bus IIO Port Addresses ......... 4-12
Control Cable Line Functions ......... 4-13
Read/Write Cable Line Functions ..... 4-14
iSBX Bus Mnemonics-to-Controller
Line Name .......................... 4-15
Status Register Bits ................... 4-22
Code for Manufacturers ................ 5-2
Controller Board Electrical Parts List .. 5-2
v
ILLUSTRATIONS
Figure
1-l.
1-2_
1-3.
2-l.
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
3-1.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
vi
Title
Page
Typical Multiple Drive System
Using Winchester Disk Drives
1-1
Typical Multiple Drive System
Using Flexible Disk Drives and
iSBX 218 Flexible Disk Controller
1-2
Automatic Error Checking
and Correction ... , ................... 1-3
Serial Priority Resolution .............. 2-1
Master Command Access Timing ...... 2-4
8" Shugart/Quantum Drive Interconnecting
Cable Requirements ................. 2-10
Fujitsu 2300/Memorex/14" Shugart Drive
Interconnecting Cable Requirements 2-12
Pertec Drive Interconnecting
Cable Requirements ................. 2-14
Priam Drive Interconnecting
Cable Requirements ................. 2-16
5 1/1" RMS Drive Interconnecting
Cable Requirements ................. 2-18
Control Data Corporation Drive Interconnecting Cable Requirements ..... 2-19
Control Data Corporation Drive Interconnecting Cable Requirements ..... 2-20
Controller to Drive Interfacing ........ 2-21
Installing the iSBX 218 Board on
the iSBC 2] 5 Controller Board
2-23
Disk Drive Organization and
Terminology ........................... 3-1
Sector Data Format .................... 3-2
Host CPU-Disk ControllerInteraction Through the
I/O Communications Block .......... 3-3
Wake-Up Block ......................... 3-5
Channel Control Block ................. 3-5
Controller Invocation Block . _.......... 3-6
I/O Parameter Block Description ...... 3-7
110 Communications Blocks Linking
3-10
Track Formatting ..................... 3-11
Alternate Track Formatting ........... 3-12
Read Sector ID ........................ 3-13
Figure
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
3-22.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
5-1.
5-2.
5-2.
Title
Page
Read Data ............................ 3-14
Read Data into Controller Buffer
and Verify .. _....................... 3-14
Write Data ............................ 3-15
Write Data from Controller Buffer
to Disk .............................. 3-15
Initiate Track Seek ... _................ 3-16
Execute iSBX Interface 110 Program
3-16
I/O Transfers Through iSBX Interface 3-17
Buffer 110 ............................ 3-18
Diagnostic ............................ 3-19
Transfer Error Status ................. 3-19
Execution of iSBX Bus
110 Program from RAM ............ 3-23
Logic Conventions ..................... 4-1
Simplified Block Diagram
of iSBC 215 Controller ............... 4-2
iSBC 215 Controller Functional
Block Diagram ....................... 4-3
Bus Arbitor and Bus Controller Logic
4-7
Data Transmission Between Multibus
Interface and Controller Data
Transceivers ......................... 4-9
Wake-Up Address Logic ............... 4-10
Address Fetches in
Initialization Sequence .............. 4-11
Local Memory Map ................... 4-11
Timing Diagram for RDY Signal ..... 4-16
Timing Diagram for Disk
Formatting Sequence ................ 4-17
Timing Diagram for Write Data ...... 4-19
Timing Diagram for
Read Data Transfer ................. 4-20
iSBC 215 Controller Jumpers
and Switch Locations ................ 5-5
iSBC 215 Winchester Disk
Controller Parts Location Diagram ... 5-7
iSBC 215 Winchester Disk
Controller Schematic Diagram ....... 5-9
•
•
•
•
•
•
•
[
CHAPTER 1
.___________G_E_N_E_R_A_L_IN
__
FO_R_M
__A_T_IO_N~
1-1. INTRODUCTION
The Intel iSBC 215™ Winchester Disk Controller
allows up to four Winchester technology disk drives
(see Table 1-2 for disk specifications) to be interfaced
with any Intel Multibus ™ interface compatible
computer system. It supports drives that use either
open loop head positioning (Shugart SA600, SAlOOO
and SA4000, Quantum Q2000 or Fujitsu 2300, RMS
500, CDC Finch or Memorex 101) or closed loop head
positioning (Pertec D8000 or Priam 3350 and 3450).
It's design is based on the Intel 8089 I/O Processor,
which allows Direct Memory Access (DMA) transfers, error detection and correction, and data
management. The controller can operate in a multi·
processor environment and is fully compatible with
all Intel 8·bit and lEi-bit computers. The number of
tracks per surface, sectors per track, bytes per sector
and alternate tracks per surface are software selectable for each drive unit. (In addition, the Memorex,
14" Shugart and Priam drives require that the sector
•
size be set internally as shown in Chapter 2.) The
single board assembly also features automatic error
recovery and retry, transparent data error correction
and multiple sector transfers. Seek operatipns on
multiple drives can be overlapped with a read/write
operation on another drive. The iSBC 215 controller
is fully compatible with Intel 8086 CPU 20-bit
addressing.
A typical multiple drive system using four Winchester disk drives and the iSBC 215 controller is shown
in Figure 1-1. The controller also provides two Intel
iSBXTM Bus connectors, J3 and J4, which allow other
storage devices such as floppy disk drives or magnetic
tape eartridge drives to be interfaced with Multibus
interface compatible systems. The Intel iSBX 218™
Flexible Disk Controller, for example, attaches to one
iSBXTM Connector, J4, allowing the controller to be
interfaced with up to four double-density floppy disk
drives. Figure 1-2 shows a typical multiple drive system using four 5 1/ / ' or 8" floppy disk drives, the iSBC
INTERNAL
TERMINATOR
DRIVE 1
DRIVE 2
DRIVE!
READIWRITE CABLE
•
,--'-I
CONTROL CABLE
--I
I
----:":""-----)
I
I
L _____ _
,-(
J3
I
J1
I
)
(
J4
I
I
_ ____ J
P2
(Not used)
iSBC 215" WINCHESTER DISK CONTROLLER
•
Multlbus" Interface
Figure 1-1. Typical Multiple Drive System Using Winchester Disk Drives
1-1
iSBC 215
General Information
215 controller and the iSBX 218 Flexible Disk Controller_ It should be noted that the controller can
interface concurrently with Winchester disk drives
through connectors Jl and J2, and with other
storage devices through the iSBXTM Connectors, J3
and J4_
1-2. DESCRIPTION
The iSBC 215 Winchester Disk Controller is a single
board assembly_ It may reside in any Intel backplane
or in a custom-designed configuration that is
physically and electrically compatible with the Intel
Multibus interface_
The host Central Processing Unit (CPU) communicates with the Disk controller via four blocks of
information in host memory_ Once the controller is
initialized, a CPU I/O write to the controller WakeUp Address initiates disk activities. The controller
accesses the four blocks in the host memory to
determine the specific operation to be performed,
fetches the required parameters and completes the
specified operation without further CPU intervention.
The controller board generates all drive, control and
data signals and receives the drive status and data
signals required to perform the entire disk drive
interfacing task. During a disk read operation, the
controller accepts serial data from the disk, interprets synchronizing bit patterns, verifies validity of
the data, performs a serial-to-parallel data conversion, and passes parallel data or error condition
indications to host memory. During a disk write
operation, the controller performs parallel-to-serial
data conversion and transmits serial write data and
the write clock to the drive. As part of the disk
format and write function, the controller appends an
Error Checking Code (ECC) at the end of each ID
and data field. Using this ECC, the controller
hardware can detect errors of up to 32 bits in length;
controller firmware can correct errors of up to 11 bits
in length (see Figure 1-3).
The Intel 8089 I/O Processor provides optimum
performance with minimum CPU overhead. An Intel
8288 Bus Controller and 8289 Bus Arbiter control
access to the Multibus interface. Intel 2732 EPROMs
provide on-board storage of the controller I/O
control program and a resident diagnostic exerciser,
and 2114 Static RAMs provide local memory for data
buffering and for temporary storage of read/write
parameters.
INTERNAL
TERMINATOR
DRIVE 0
DRIVE 1
DRIVE 2
I
J1
I
(
)
I
I
L _____ _
--I
I
J2
ISBX 218'· FLEXIBLE
DISK CONTROLLER
(CONNECTS TO J4)
J3
P1
P2
(NOT USED)
•
•
DRIVE 3
1-------
•
•
I
I
I
MULTI BUS'· INTERFACE
Figure 1-2 Typical Multiple Drive System Using Flexible Disk Drives
and iSBX 218™ Flexible Disk Controller
1-2
•
General Information
iSBC 215
•
CONTROLLER FIRMWARE
CORRECTS ERRORS WITHIN
11 CON!IECUTIVE BITS
•
CONTROLLER FIRMWARE
DETECTS ERRORS WITHIN
32 CONSECUTIVE BITS.
•
Ifoolll(f------" 32
TRACK n
Figure 1-3. Automatic Error Checking and Correction
1-3. SPECIFICATIONS
•
BITS-----~
Table 1-1 lists the physical and performance specifications of the iSBC :215 Winchester Disk Controller;
Table 1-2 lists typical characteristics of the Winchester disk drives that are compatible with the iSBC 215
controller.
Table 1-1. Board Specifications
COMPATIBILITY
CPU:
Any Intel mainframe or any Multibus™ interface compatible CPU. The
controller can operate with either 16- or 20-bit addresses and with either 8- or
16-bit data bus widths.
Disk Drive:
Winchester disk drives (see Table 1-2); both open-loop and closed-loop head
positioning types.
Two versions of controller firmware (located in ROMs U87 and U88) are
available, one for use with open·-Ioop type drives and one for closed-loop
drives.
•
Flexible disk drives through on-board iSBX™ Connector (see iSBX 218™
Flexible Disk Controller specifications)
1-3
iSBC 215
General Information
Table 1-1. Board Specifications (Continued)
DATA ORGANIZATION AND CAPACITY
Bytes per Sector
and Sectors per
Track:
SECTORS'
5'/.. ' Rotating
14"
Fujitsu 23001
Memory Systems Shugart
Memorex
54
64
96
31
57
38
17
31
21
9
16
11
Bytesl
Sector
128
256
512
1024
Formatted Disk
Capacity:
Bytes
Sector
128
256
512
1024
5'/4' Rotating
Memory Systems
8.40
9.65
10.58
11.21
Bytes
Sector
128
256
512
1024
MBytes
MBytes
MBytes
MBytes
Pertec
69
42
24
12
FORMATTED CAPACITYIDRlVE2
Control Data
8" Shugartl
Corp
Quantum
29.25
28.03
24.98
19.50
MBytes
MBytes
MBytes
MBytes
7.08
8.12
8.91
9.43
MBytes
MBytes
MBytes
MBytes
8"
Priam
70
42
23
12
14"
Priam
104
62
34
18
14"
Shugart
19.86
23.58
25.65
26.48
MBytes
MBytes
MBytes
MBytes
FORMATTED CAPACITY/DRIVE2 (Cont.)
Fujltsul
Memorex
7.99
9.49
10.49
10.98
Drives per Controller:
Error Detecting and Correction:
Pertec
MBytes
MBytes
MBytes
MBytes
12.35
15.03
17.17
17.18
MBytes
MBytes
MBytes
MBytes
8"
14"
Priam
Priam
23.29
27.94
30.62
31.95
MBytes
MBytes
MBytes
MBytes
•
22.40
26.71
29.29
31.02
•
MBytes
MBytes
MBytes
MBytes
Winchester Disk Drives - Up to four 8" Shugart, Quantum, Pertec or Priam
drives through connectors J1 and J2 (see Table 1-2); up to two Memorex
drives or 14" Shugart drives.
Flexible Disk Drives - Up to four 5'.4" or 8" drives through the iSBX 218
Flexible Disk Controller connected to the iS8C 215 TO board's iS8X TO
connector, J4.
The controller hardware can detect errors of up to 32 bits in length; controller
firmware can correct errors of up to 11 bits in length (see figure 1-3).
•
CONTROLLER CHARACTERISTICS
Mounting:
Physical Characteristics:
Width:
Length:
Height:
Weight:
Power Requirements:
Occupies a card slot in iS8C 604/614 Modular Cardcage/8ackplane or equivalent Multibus™ backplane connector.
17.2 cm (6.8 inches)
30.5 cm (12.0 inches)
1.3 cm (0.5 inches)
0.54 kg (19 ounces)
•
+5 Volts ±5% @ 3.25 amperes maximum;
-5 Volts ±5% @ 0.15 amperes maximum.
NOTE
Jumper and on-board voltage regulator allow -5 Volts or -12 Volts
from Multibus TO connector to be used as voltage source for -5 Volt.
Environmental:
Temperature:
Humidity:
O°C to +55°C, operating (-'-32° F to +131°F).
-55°C to +85°C, non-operating (-67°F to +185°F).
Up to 90%, non-condensing.
'Maximum allowable for corresponding selection of Bytes per Sector.
'Applies to the following drive models: 5'.4" RMS 512, Control Data Corp 9410-32, 8" Shugart SA 1004, Quantum Q2010, 14"
Shugart SA4008, Memorex 101, Fujitsu 2301, Pertec 08000, 8" Priam 3450 and 14" Pram 3350.
1-4
•
General Information
iSBC 215
•
Table 1-2. Winchester Disk Drive Characteristics
Rotating
Memory
Systems 512'
Capacity (Unformatted)
Read/Write Surfaces
T racks/Su rface
ByteslTrack
Transfer Rate
Average Access Time
Control
Data Corp
9410-32 2
Fujitsu
Shugart
SA1004'/ Quan
2301'
tum Q2010
Memorex 101
Pertec
08020'
12.7 MBytes
~189 MBytes 10.6 MBytes
11.7 MBytes
20.13 MBytes
8
4
4/2 3
3
~
153
595
256
244
466
10.4 KBytes
13.4 KBytes
10.4 KBytes
12 KBytes
14.4 KBytes
625 KBytes/sec 806 KBytes/sec 524 KBytes/sec 593 KBytes/sec 864 KBytes/sec
70 msec
50 msec
70 msec
70 msec
50 msec
Rotational Latency
8.33 msec
3 ms
Track to Track
'Open loop step positioner.
8.33 msec
10 ms
9.6 msec
19 msec
10.1 msec
20 msec
8.34 msec
12 msec
Priam
34502
34.94 MBytes
5
520
13.4 KBytes
806 KBytes/sec
50 msec
8.3 msec
10 msec
'Closed loop servo voice coil technology.
'Quantum Q2010 has 2
•
•
•
•
1-5
•
•
•
•
•
•
CHAPTER 2
[
___________P_R_E_P_A_R_A_T_IO_N__F_O_R_U_S_E~
Carefully unpack the shipping carton and verify
that the following items are included:
2-1. INTRODUCTION
This chapter provides information for use in preparing and installing the iSBC 215 Winchester Disk
Controller. Included are instructions for unpacking
and inspection, installation, setting switches,
installing jumpers, and interfacing the controller
board with the Multibus connector and disk drives.
•
iSBC 215 Winchester Disk Controller Printed
Wired Assembly
•
iSBC 215 Winchester Disk Controller Schematic
Diagram
2-3. BOARD INSTALLATION
CONSIDERATIONS
2-2. UNPACKING AND INSPECTION
•
•
On receipt of the iSBC 215 controller from the
carrier, immediately ilnspect the shipping carton for
evidence of damage. If the shipping carton is
damaged or water-stained, request that the carrier's
agent be present when the carton is opened; if the
carrier's agent is not present at the time of opening,
keep the carton and packing materials for subsequent agent inspection.
For repairs or replacement of an Intel product
damaged during shipment, contact Intel Technical
Support Center (refer to Chapter 5) to obtain a
Return Authorization Number and further instructions. A copy of the Purchase Order should be
submitted to the carrier with the claim.
•
The iSBC 215 controller can be installed in any Intel
cardcage/backplane or any user-designed backplane
that is compatible with the Multibus interface and
meets the controller's power and Multibus connector
dimensional requirements. The controller occupies
one backplane slot.
When installing the controller in a serial priority
environment (e.g., within any of the Intel system
chassis), wiring modifications are required to
support serial priority; a daisy-chain technique, see
Figure 2-1, establishes priority, The priority input
(BPRN I) of the highest priority master is tied to
ground. The priority output (BPRO/) of the highest
priority master is then connected to the priority
HIGHEST
PRIORITY
r)
LOWEST
PRIORITY
BPRNI
rO
rO
BPRNI
BPRNI
(NOT INTERNALLY
CONNECTED)
BPROI
p-
BPROI
~~
P-
BPROI
H
~
~
(
--
•
l
l
Figure 2-1. Serial Priority Resolution
2-1
iSBC 215
Preparation for Use
input (BPRN I) of the next lowest priority master,
and so on. (" I" following the signal name indicates
an active low). This technique can accommodate a
limited number of masters due to gate delays
through the daisy-chain.
2-4. POWER REQUIREMENT
The board requires a +5 Volt ±5% power supply at a
maximum current of 3.25 amperes, supplied through
the Multibus connector. When interfacing with 8"
Shugart/Quantum drives, an additional-5 Volt ±5(),()
source at 150 milliamperes maximum is required.
This -5-Volt supply can be obtained directly from the
Multibus connector or from an on-board regulator
that uses either the -10 or -12-Volt source from the
Multibus connector (refer to Paragraph 2-14). When
interfacing with an iSBX Bus through J3 or J4,
additional voltage sources of +12 Volts, -12 Volts or
both may be required, also supplied through the
Multibus connector. (See individual iSBX Board
specifications for tolerances and current requirements of these supplies.) Before installing the
controller in a system chassis, make certain that the
associated power supplies can supply the additional
current that the controller board requires.
2-5. COOLING REQUIREMENT
When the controller is installed in a high temperature environment, make certain the ambient operating temperature does not exceed +55°C.
2-6. MULTIBUS™ CONNECTOR
The controller communicates with the CPU and
other boards via the Multibus interface. Table 2-1
lists the Multibus connector pin assignments; Table
2-2 describes the controller Multibus interface
signals. Figure 2-2 provides a diagram of the
controller/Multibus interface timing signals and a
table of the timing requirements. Table 2-3 gives
current requirements and other characteristics
related to the controller/Multibus interface.
•
The controller is connected to the Multibus interface
through connector P1, an 86-pin, double-sided,
printed circuit edge connector with 3.96 mm (0.156
in) contact centers. Connector P2 is not used.
2-7. SWITCH/JUMPER CONFIGURATIONS
A number of switches and jumpers (see Table 2-4) are
provided on the controller board that allow the user
to conveniently set the controller for the system
environment in which it is to operate (8-bit or 16-bit
system data bus, 8-bit or 16-bit 110 addressing, etc.)
and for the type of drive to which it is to be
interfaced (Shugart/Quantum, Memorex, etc., or
iSBX board). Figure 5-1 shows the location of these
switches and jumpers on the board. They should be
set, as described in the following paragraphs, prior
to installing the board in a card cage or backplane.
•
•
Table 2-1. Multibus™ Connector PI Pin Assignment
P1 (Component Side)
Pin
Mnemonic·
Description
P1 (Circuit Side)
Pin
Mnemonic·
Description
Power
Supplies
1
3
5
7
9
11
GND
+5V
+5V
+12V
-5V
GND
Signal GND
+5Vdc
+5Vdc
+12Vdc
-5Vdc
Signal GND
2
4
6
8
10
12
GND
+5V
+5v
+12V
-5V
GND
Signal GND
+5Vdc
+5Vdc
+12Vdc
-5Vdc
Signal GND
Bus
Controls
13
15
17
19
21
23
BCLKI
BPRNI
BUSYI
MRDCI
10RCI
XACKI
Bus Clock
Bus Pri. In
Bus Busy
Mem Read Cmd
1/0 Read Cmd
XFER Acknowledge
14
16
18
20
22
24
INITI
BPROI
BREQI
MWTCI
10WCI
INH11
Initialize
Bus Pri. Out
Bus Request
Mem Write Cmd
1/0 Write Cmd
Inhibit 1 disable RAM
Bus
Controls
and
Address
25
27
29
31
33
Reserved
Byte High Enable
Common Bus Request
Constant Clk
Intr Achknowledge
26
28
30
32
34
INH21
Inhibit 2 disable PROM or ROM
BHENI
CBRQI
CCLKI
INTAI
2-2
ADR101
ADR111
ADR121
ADR13
Address
Bus
•
•
Preparation for Use
iSBC 215
•
•
•
Table: 2-1. Multibus™ Connector PI Pin Assignment (Continued)
P1 (Circuit Side)
P1 (Component Side)
Pin
Mnemonic·
Interrupts
35
37
39
41
INT6/
INT4/
INT2/
INTO/
Address
43
45
47
49
51
53
55
57
ADRE/
ADRC/
ADRA/
ADR81
ADR61
ADR41
ADR2/
ADROI
Data
59
61
63
65
67
69
71
73
DATE/
DATC/
DATAl
DAT81
DAT6/
D}\T41
DAT2/
D,£\TOI
GND
Power
Supplies
75
77
79
81
83
85
• "r
-12V
+eiV
+~;V
GND
Description
Pin
Mnemonic·
Description
36
38
40
42
INT7/
INT5/
INT3/
INT1/
Parallel
Interrupt
Requests
44
48
50
52
54
56
58
ADRF/
ADRD/
ADRB/
ADR9/
ADR7/
ADR5/
ADR3/
ADR1/
Address
Bus
Data
Bus
60
62
64
66
68
70
72
74
DATF/
DATDI
DATB/
DAT9/
DAT7/
DAT51
DAT3/
DAT1/
Data
Bus
Signal GND
Reserved
-12Vdc
+5Vdc
+5Vdc
Signal GND
76
78
80
82
84
86
GND
Parallel
Interrupt
Requests
46
Address
Bus
-12V
+5V
+5V
GND
Signal GND
Reserved
-12Vdc
+5Vdc
+5Vdc
Signal GND
following the signal name indicates an active low.
Table 2-2, iSBC 2I5™ ControllerlMultibus™ Interface PI Signal Descriptions
Signal
•
•
Functional Description
ADRO/, ADRF/
ADR101-ADR131
Address. These 20 lines transmit the address of the memory location or I/O port to be accessed. For
memory access, ADROI (when active) enables the even byte bank (DATOI-DAT7/) on the Multibus'·
connector; i.e., ADRO/ is active for all even addresses. ADR13/ is the most significant address bit.
BCLKI
Bus Clock. Used to synchronize the bus contention logic on all bus masters.
BHENI
By'e High Enable. When active low, enables the odd byte banl< (DAT8/-DATF/) onto the Multibus'·
cOllnector.
BPRNI
Bus Priority In. When low indicates to a particular bus master that no higher priority bus master is
requesting use of the bus. BPRN/ is synchronized with BCLK/.
BPRO/
Bus Priority Out. In serial (daisy chain) priority resolution schemes, BPROI must be connected to the
BPRN/ input of the bus master with the next lower bus priority.
BREQ/
Bus Request. In parallel priority resolution schemes, BREQ/ indicates that a particular bus master
requires control of the bus for one or more data transfers. BREQ/ is synchronized with BCLKI.
BUSYI
Bus Busy. Indicates that the bus is in use and prevents all other bus masters from gaining control of
tile bus. BUSY/ is synchronized with BCLKI.
CBRQ/
Common Bus Request. Indicates that a bus master wishes control of the bus but does not presently
have control. As soon as control of the bus is obtained, the requesting bus controller raises the
CBRQI signal.
DATOI-DA TF I
Data. These 16 bidirectional data lines transmit and receive data to and from the addressed memory
location or 1/0 port. DATFI is the most-significant bit. For data byte operations, DATOI-DAT7 is the
even byte and DAT8-DATFI is the odd byte.
2-3
iSBC 215
Preparation for Use
Table 2-2. iSBC 2I5™ ControllerlMultibus™ Interface PI Signal Descriptions (Continued)
Functional Description
Signal
INITI
InWalize. Reset the entire system to a known internal state.
INTOI-INT71
Interrupt Request. These eight lines transmit interrupt requests to the appropriate interrupt handler.
INTOI has the highest priority.
IOWCI
liD Write Command. Indicates that the address of an liD port is on the Multibus™ connector address
lines and that the contents on the Multibus™ connector data lines are to be accepted by the addressed
port.
MRDCI
Memory Read Command. Indicates that the address of a memory location is on the Multibus™ connector
address lines and that the contents of that location are to be read (placed) on the Multibus™ connector
data lines.
MWTCI
Memory Write Command. Indicates that the address of a memory location is on the Multibus™ connector
address lines and that the contents on the Multibus™ connector data lines are to be written into that
location.
XACKI
Transfer Acknowledge. Indicates that the address memory location has completed the specified read or
write operation. That is, data has been placed onto or accepted from the Multibus™ connector data
lines.
BUSYI
X::
Master Command Access Timing
BUS ACCESS
BUS RELEASE
Y
•
•
~Io.j
ADDREss __________J)Er;~-------------------~-------~A-D-D-R-E-S-S-ST-A-B-L-E================~)(~___________
WRITE DATA
-------1
f\..---------DATA
r-'"=1'--
STABLE--------~A
r-IOHW~
READDATA __________~~------~----------J)E.----DATASTABLE
?Cr--~-----------I
r-'"~
COMMAND
(MRDC/OR MWTC/)
'----1
05-
'""P__
X--...:..I·-----.,I,....--IX-KCO~
X A C K / - - - - - - - -............._____\ _ _ _----'/~----
Slave Command Timing
ADDRESS
~~~-------------ADDRESSSTABLE-------------~~~
I/O WRITE DATA
(FROM SYSTEM CPU)
---~~~~~------------DATASTABLE------------~?>,C~r-------
1/0
~~
XACKI
------.;
l_tSDHW-1
1
~
II-~- - I A C C - -__
II
I_~IXKO
\~ ___----J)r--
Figure 2-2. Master Command Access Timing
2-4
•
~~~
t=:f=ISDS
COMMAND
(IOWC/)
•
•
iSBC 215
Preparation for Use
•
Bus Exchange Timing
~--.
BCLKI
.-J
BREQI
"" -r ", t-""1
~"I'
"--------I
I-''"°LI.
\"/
'
Y
'\
\"---'/
,~)--t-W-A-IT----------·~I-----~----tO-B-P-N--------+-------------------
BPRNI
'\
-------------~n
~~-------------------------------
•
•
•
•
tOBYF -+-10l-----1
BUSYI
q - tOBY
________________________~()I~()--------------~--------J)I~HIGHZ~'\~------____
r-toBPo-1
BPROI
\--------,
Time in Nanoseconds
Parameter
Description
Minimum
tSAS
tsos
tSAH
tSOHW
tACC
tXKO
Maximum
50
0
15
30
8000
100
tsCY
tSl
tSH
tORQ
tOSY
tOSYF
tDSPN
tosPO
tWAIT
125
65
35
tos
tsc
tXKCO
tAH
tOHW
tOHR
tosx
50
50
35
50
35
15
25
00
750
50
50
0
0
Address Setup Time to I/O Command
Data Setup Time to I/O Command
Address Hold Time from I/O Command
Data Hole Time from I/O Command
I/O Access Time
XACK/Hod Time from I/O Command
Bus Clock Cycle Time
Bus Clock Low
Bus Clock High
Bus Request Delay
Bus Busy Turn On Delay
Bus Busy Turn Off Delay
Priority Input Setup Time
BPRO/Serial Delay from BPRN/
Requesting Master Bus Access Time
Busy to Address/Data Delay
Address/Data Setup to Command
XACK/ to Command Turn Off
Address Hold Time
Data Hold Time
Read Data Hold Time
Data Setup Time Before XACK/
Figure 2-2. Master Command Access Timing (Continued)
2-5
iSBC 215
Preparation for Use
Table 2-3. iSBC 215™ ControllerlMultibus™ Interface Signal Characteristics
Driver 1, 3
Location
Bus
Signals
Type
Receiver 2, 3
Location
IOL
IOH
Co
Min ma
Minl'a
Min pt
IlL
IIH
CI
Max ma
Maxl'a
Max pt
DATO/DATF/
(16 lines)
Masters
TRi
32
-5000
300
Masters
and
Slaves
-0.5
125
18
ADRO/ADR13/,
BHEN/
(21 lines)
Masters
TRI
32
-5000
300
Slaves
-0.8
90
18
MRDC/,
MWTC/
Masters
TRI
32
-5000
300
Slaves
-0.7
50
18
Slaves
--{).4
20
5
Masters
-1.2
60
18
Master
-0.5
60
18
Master
-0.5
60
18
Ail
Masters
-0.5
60
18
All
-0.5
60
18
IOWC/
XACK/
Slaves
TRI
48
-2000
300
BCLK/
BREQ/
Each
Master
TTL
10
-400
60
BPRO/
Each
Master
TTL
10
-400
60
BPRN/
All
Masters
BUSY/,
CBRQ
O.C.
20
-
250
INIT/
INTO/INT7/
(8 lines)
Slaves
O.C.
40
-
Notes:
1.
Driver Requirements:
IOH =
IOL =
Co =
TRI =
O.C.=
TTL =
2.
High Output Current Drive
Low Output Current Drive
Capacitance Drive Capability
3-State Drive
Open Collector Driver
Totem-pole Driver
Receiver Requirements:
IIH
IlL
CI
= High Input Current Load
= Low Input Current Load
= Cap Active Load
2-8. WAKE-UP ADDRESS SELECTION
The controller communicates with the host CPU
through four I/O communications blocks located in
the host memory. When the controller is to receive
instructions, it goes to the beginning address of the
first I/O communieation block. This address is
called the wake-up address (WUA). The WUA may
be at any address in host memory. 8ixteen WUA
2-6
300
3.
•
•
•
Low and High Voltage Requirements:
Receiver:
0~VIL~0.8V
2.0V ~ VIH
~
5.5V
Driver:
O~VOL ~0.5V
2.4V ~ VOH
~
•
5.5V
switches (81-1 through 81-8 and 82-3 through 82-10,
see Figure 5-1) are provided on the controller board
that allow the user to set the controller for the
selected wake-up address. The function of each
switch is shown in the table in Figure 5-1. Any
switch set to ON represents a logical 1.
The controller multiplies the settings of the WUA
switches by 24 (shifts the number four places to the
•
{SBC 215
•
Preparation for Use
left) to create a 20-bit WUA. Note that due to this
shift, the four least-significant bits of the selected
WUA must be zeros. When accessing host memory,
the controller transmits the entire 20-bit WUA
through the Multibus interface. If the host memory
uses 16-bit addressing" the four most significant bits
ofthe 20-bit WUA must be zero. This is accomplished
by setting the four most significant bits of the WUA
switches (SI-1 through SI-4) to zero.
2-11. INTERRUPT PRIORITY LEVEL
The controller's internal interrupt request signal can
be assigned to any of eight interrupt priority levels
(INTO I to INT7 I) on the Multibus connector. To
select the interrupt request priority level, place a
jumper link as shown in Table 2-5 and Figure 5-1.
Table 2-5. Interrupt Priority Level Selection
Wire Wrap
Table 2-4. Configuration Jumpers
and Switches
Function
Wake-Up Address
•
8-Bit or 16-Bit System
Data Bus Capability
8-Bit or 16-Bit Host
Processor 1/0 Port
Addressing
I nterru pt Priority Level
Pin or Switch
S1-1 through S1-8
S2-3 through S2-10
S2-1
S2-2
W19-C to W19-0
through W19-7
Any Request
Common Bus Request
Voltage Selection
•
•
Winchester Drive
Manufacturer Selection
iSBX Bus Control
Priority
Level Selected
To Pin
0
W19-C
W19-0
1
W19-C
W19-1
2
W19-C
W19-2
3
r
W19-C
W19-3
W19-C
W19-4
5
W19-C
W19-5
6
W19-C
W19-6
7
W19-C
W19-7
W18
W23
W2D- and W21
W1, W2, W5, W6
through W10
W13 through W17, W22
W3, W4, W11 and W12, W24
2-12. ANY REQUEST SELECTION
The any request function allows the controller to be
set to relinquish control of the Multibus interface
following a request from:
2-9. WAKE-UP I/O PORT
ADDRESS SELECTION
The host processor communicates with the controller
through an 110 port. The WUA switches also set the
address of this 110 port. For a host processor with
8-bit 110 port addressing, bits 0 through 7 of the
un shifted WUA determine the wake-up 110 port
address; for a host processor with 16-bit I/O port
addressing, bits 0 through F determine the address.
I/O Address Selection switch S2-2 on the controller
board (see Figure 5-1) determines the type ofI/O port
addressing the host processor uses: ON for 16-bit
addressing; OFF for 8-bit addressing.
System data bus selection switch S2-1 on the controller board (see Figure 5-1) sets the controller for
the type of system data bus with which the controller
is to interface: ON for 16-bit bus, OFF for an 8-bit
bus. This switch allows the controller to use its 16-bit
data transfer mode to access the system bus (if the
system memory supports 16-bit accesses), even
though the host processor only supports 8-bit
accesses.
1.
A higher priority device only (jumper between pins W18-1 and W18-2 on the controller board).
2.
Any device, lower or higher priority, (jumper
between pins W18-1 and WI8-3).
Figure 5-1 shows the location of the selection pins.
2-13. COMMON BUS REQUEST
The common bus request function allows the controller to take advantage of higher bus transfer rates
by arbitrating for the use of the bus only when other
bus controllers have access requests pending. The
controller will:
1.
Arbitrate for the bus on every access, (jumper
between pins W23-1 and W23-2 on the controller).
This mode is used when other bus controllers do
not implement common bus request.
2.
Arbitrate for the bus to acquire the bus for the
first access and rearbitrate only when another
bus controller requests use of the bus.
2-10. SYSTEM DATA BUS SELECTION
•
From Pin
2-14. WINCHESTER DRIVE INTERFACE
The iSBC 215 Winchester Disk Controller has been
designed to communicate with any of four unique
2-7
iSBC 215
Preparation for Use
Table 2-6. 8" Winchester Drive Manufacturer Selection
MANUFACTURER
Jumper
No.
Function
Memorex/
8" Shugart! 14" Shugart
5 '/,' RMS
Pertec
Quantum Fujitsu 2300
From To From To From To From To
1
W1
1
3
W2
-
-
W5
1
2
1
W6
1
2
1
W7
W8
1
1
2
2
1
W9
-
W10
1
W13
1
2
1
W14
1
2
1
W15
--
-
2
-
-
1
1
1
.-
3
1
-
1
3
3
3
3
2
2
2
2
1
-
1
1
1
1
3
2
1
2
2
2
1
2
1
1
2
1
2
1
2
-
1
2
2
1
1
-
1
1
1
1
-
1
1
2
1
2
1
1
1
3
3
2
1
3
2
2
2
3
1
1
-
3
-
1
3
1
2
INDEX Select
1
2
1
2
Pertec RD Clock Select
1
3
1
1
3
1
1
2
1
3
2
2
1
1
2
1
2
1
-
1
1
Open/Closed Head Positioning
Vendor Select
3
3
3
3
2
2
3
3
2
2
1
1
2
1
1
2
1
W22
1
-
2
W17
2
-
-
1
2
1
-
2
1
CDC
From To
-
-
1
W16
3
2
2
2
2
2
Priam
From To
1
•
RDRD +
RDCL +
RDCL-
}
Level
Select
Shugart Tri-State Select
Radial Select
Hard/Soft Sectoring
Shugart AM Control
Shugart GAP Control
Hard/Soft Sectoring
NOTE
•
- means not instaliej
The iSBX bus control jumpers, W3, W4, W11 and W12, are factory wired for the configuration required when the
iSBX Bus is not being used. See Paragraph 2-17 and Table 2-9 for a description of the use of these jumpers.
Winchester technology disk drive interfaces: 8"
Shugart/Quantum, Memorex/14" Shugart, Pertec
and Priam. 1 The Shugart, Quantum and Memorex
drives use a stepper motor for head positioning
(called open-loop head positioning); the Pertec and
Priam drives use a linear positioner coupled with a
servo surface on one disk for position feedback
(closed-loop head positioning).
1 The manufacturer's models with which the controller interfaces are: 8" Shugart (Models SAlO02 and
SAI004). Quantum (Models Q201O. Q2020, Q2080
and Q2040), Memorex (Models 101 and 102), 14"
Shugart (Models SA4004 and SA4008), Pertec (Model
mWOO). Rotating Memory Systems (Models .506 and
512) and Control Data Corporation (Models 9410 24
and 82). Priam (Models .570, 1070, 20.50, 8350 and
;)4.50).
The controller can control up to four 8" Shugart,
Quantum, Pertec or Priam drives, or up to two
Memorex or 14" Shugart drives. It cannot control
drives of different manufacturers concurrently.
The jumpers listed in Table 2-6 allow the controller
to be set for the selected drive type. In addition, two
versions of the controller firmware (located in ROMs
U87 and U88) are available, one for use with openloop type drives and one for closed-loop drives.
Boards configured for use with open-loop drives
come from the factory with open-loop firmware
installed and with jumpers preset for 8" Shugart/
Quantum drives; boards configured for closed-loop
2-8
drives come with closed-loop firmware and with
jumpers preset for Pertec drives. Converting the
controller from the 8" Shugart/Quantum interface to
a Memorex/14" Shugart interface or from Pertec to
Priam merely requires changing the connections of
some of the jumpers as shown in Table 2-6 and
Figure 5-1. Converting the controller from an openloop interface to a closed-loop interface, and vice
versa, requires the ROMs to be changed in addition
to changing jumpers.
•
Interface cables must also be constructed and installed according to the type of drive being used as
described in Paragraph 2-15.
•
2-15. -5-VOLT SELECTION (8" SHUGART/
QUANTUM CDC DRIVES ONLY)
Figure 5-1 shows the location of the Voltage Selection
pins for the -5 Volt power supply. Install jumpers as
described in Table 2-7 to select -5 volts either from
the Multibus connector or from the on-board regulator and to select the voltage source for the regulator.
2-16. CABLING REQUIREMENTS
Interface cables between the controller and the disk
drives must be fabricated according to the type of
drive being used and the number of drives. Figures 2-3
through 2-7 show the connector pin assignments for
the controller and for each type of drive. A 50-pin
mass-terminated socket connector 3M 3425/6050 or
•
Preparation for Use
iSBC 215
•
•
•
equivalent, is recommended for mating with J1 of
the controller board. A 40-pin 3M :3417-6040 or
equivalent connector is recommended for mating
with J2. The mass-terminated sockets are easily
attached to flat ribbon cable using the jig that the
connector manufacturer supplies. The Control Cable
that connects to J1 requires a 50-conductor ribbon
cable; the Read/Write cable that connects to J2
requires one or two 20-conductor ribbon cables,
depending on the drive configuration (refer to Paragraph 2-16). Cable length for the control cable cannot
exceed a total length of 10 feet; total length for any
Read/Write cable must not exceed 10 feet. See the
respective service manual for the type of connectors
required for the cable end that connects to the drives.
separate MFM read/write cable is then required to
transmit read/write information between the data
separator and the drive.
Each of the cables shown in Figures 2-:1 through 2-7
require a number of wire cross-overs "scrambling"
between the controller connectors and the drives. It
is suggested that the scrambling be done at the drive
interface connector.
Memorex 101 and 102 or Shugart SA4000. The
controller can drive one or two Memorex/14" Shugart
drives. When connecting the controller to a single
drive, both a control and a read/write cable are
required. When controlling two drives, a single
cable, such as the control cable described for the
Shugart/Quantum drives, is required that daisychains the contro.! information to both drives as
shown in Figure 2-10. A split (bifurcated) cable is
required to route NRZ read/write data to and from
the two drives.
NOTE
The cabling and drive interconnecting information given in Paragraphs 2-15 and 2-16
and in Figures 2-3 through 2-6, reflect the
specifications at the time this manual was
printed. Before proceeding with construction
of interconnecting- cables, check the drive's
hardware reference manual for current pin
assignments and interface requirements.
The requirements for eonnecting the controller to the
disk drive or drives varies between drive types. The
following discussion and Figure 2-10 describes the
specific interconnection requirements for each drive
type.
Pertec D8000 and Priam 570, 1070, 2050 and
3450. The connector on the Pertec and Priam drives
transmit both control and read/write data. When
connecting the controller to a single drive, a bifurcated (split) cable that combines the control lines
and the read/write lines from the controller is
requires as shown in Figure 2-10. When controlling
multiple drives, a cable such as the control cable
described for the Shugart drives is required that
daisy-chains the control and read/write information
between the four drives.
Shugart SA1000 or Quantum Q2000. When
connecting the controller to a single 8" Shugart/
Quantum drive, a Shugart SA1200 Data Separator
and three interconnecting cables are required (see
Figure 2-10. One control cable and one NRZ read/
write cable are requiJred to interface the controller
with the drive and data separator, respectively. A
RMS 500. When connecting the controller to a
single RMS drive, an RMS Data Separator and three
interconnecting cables are required. See Figure 2-8
similar to Shugart SA1000 and Quantum Q2000
above.
2-17. DRIVE INSTALLATION
•
When controlling multiple drives, Drive 0 (which is
called the master and is equipped with the data
separator) allows control and read/write data to be
routed to and from up to three additional slave
drives. The control cable for multiple drive configurations is daisy-chained from the master to the slave
drives. Physically, the cable consists of a ribbon
cable with an in-line connector for each drive. One
MFM read/write cable is required from each slave
drive to the master drive.
Table 2-7. -5-Volt Selection
•
Jumper
From
To
W21
1
2
3
2
3
1
W20
1
1
Function
Select -5 volts from Multibus'· connector
Select -5 volts from regulator (requires jumper to be set on W20)
Select -10 volts from Multibus'· connector as source for -5 Volt regulator
Select -12 volts from Multibus'" connector as source for -5 Volt regulator
2-9
iSBC 215
Preparation for Use
8" Shugart/Quantum Drive Cable Wiring Diagrams
iSBC 215 Controller·
Mating Connector J1
8" Shugart/Quantum Drive 0
Mating Connector
50-Pin
(2)
50-Pin
0
Shugart Data Separator iSBC 215 Controller Connectors·
Mating Connector J5
J1 Mating Connectors J2
20-Pin
1
2
3
4
...
Ground (GND)
-Head Select 2' (-HS2/)
2
30
3
27
4
5
5
6
6
7
7
8
9
-SEEK COMPLETE (SKCOM/)
.
..
Ground (GND)
19
8
44
9
10
10
11
11
12
12
13
14
..
Ground (GND)
.
-HEAD SELECT 2°(-HSO!)
31
13
26
14
15
15
16
16
17
18
19
20
21
22
Ground (GND)
-HEAD SELECT 2 (-HS1/)
Ground (GND)
-INDEX (INDEX/)
..
..
..
....
Ground (GND)
-READY (READY!)
32
17
2
18
39
19
15
20
11
26
27
28
29
30
31
32
33
34
35
36
..
....
-DRIVE SELECT 2 (US1/)
Ground (GND)
-DRIVE SELECT 3 (US2/)
Ground (GND)
Ground (GND)
..
47
4
24
5
..
..
48
6
25
7
49
8
21
9
..
-STEP (STEP/)
20
38
40
41
42
43
44
45
-WRITE GATE (WF1GATE/)
-TRACK 000 (TRA::K 0/)
Ground (GND)
..
-WRITE FAULT (FAUlT/)
Ground (GND)
46 through 50 -
...
..
..
..
Ground (GND)
...
no connections
1
2
3
..
-DIRECTION IN (DIR/)
22
37
39
-AMF (SECTOR!)
Ground (GND)
..
-WRAM (ADMKEN/)
..
Ground (GND)
-RWC (RDWRCUR/)
0
40-Pin
16
37
42
40
+NRZ WRITE DATA (WRO+)
-NRZ WRITE DATA (WRO-)
Ground (GND)
+WRITE CLOCK (WRClO-)
-WRITE CLOCK (WRClO+)
Ground (GND)
+READ CLOCK (RDClO+)
-READ CLOCK (RDClO-)
Ground (GND)
+NRZ READ DATA (RDO+)
-NRZ READ DATA (RDO-)
Ground (GND)
13
38
17
41
9
34
0
•
12
..
.
....
....
27
8
5
24
25
26
..
6
•..
..
7
3
23
.
..
.
4
..
-DRIVE SElECTED/
Ground (GND)
SPARE
Ground (GND)
SPARE
Ground (GND)
SPARE
Ground (GND)
+TIMING ClK
20-Pin
2
22
0
....
..
....
.....
..
.
..
-TIMING ClK
10
Ground (GND)
11
Ground (GND)
12
+MFM Write Clock
13
-MFM Write Clock
14
Ground (GND)
15
Ground (GND)
16
+MFM READ DATA
17
-MFM READ DATA
18
Ground (GND)
19
Ground (GND)
~
20
'iSBC 215'· Controller (signal name) in parentheses.
..
.....
......
..
..
..
•
21
8" Shugart/Quantum Drive 0
Mating Connector
Figure 2-3. 8" Shugart/Quantum Drive Interconnecting Cable Requirements
2-10
CD
36
Ground (GND)
Shugart Data Separator
Mating Connector
23
...
-DRIVE SELECT 4 (US3/)
...
..
.
-READ GATE (RDGATE/)
Ground (GND)
20-Pin
24
-DRIVE SELECT 1 (USO/)
50-Pin
35
23
25
0
1
•
2
3
4
5
6
7
8
9
10
11
•
12
13
14
15
16
17
18
19
20
•
iSBC 215
Preparation for Use
•
--~~ 49/33
~
25
- - - - -.... 20
~ 50
21 -----il~~ 40
°1
. - -..
~~ 50/34
2
26
------i.~ 13
2
•
•
20
0)
Shugart/Quantum
50-Pin Card
Edge Connector
0
RMS
34-Pin Card
Edge Connector
40-Pln 3M Female
Connector
f:\
2o-Pln Card
~ Edge Connector
8" Shugart/Quantum/RMS
Drive 0
iSBC 215 Controller
50-Conductor
Ribbon Cable
•
•
>
J1
Scramble Wires
at drive.
Data Separator
Drive 0
Data Separator
~
~.
01~~~==~2~o-con~duct~or~~~~~0
Ribbon Cable
f---
1-------
•
--
-
~
---
.-
~-----_=------_
Figure 2-3. 8" Shugart/Quantum Drive Interconnecting Cable Requirements (Continued)
2-11
iSBC 215
Preparation for Use
Fujitsu 2300/Memorexll4" Shugart Drive Cable Wiring Diagram
Memorex/14" Shugart Drive
Mating Connector
50-Pin
1
(2)
-Head Select 0 (-HSO/)
2
Ground (GND)
3
-Head Select 1 (-HS1/)
4
Ground (GND)
5
-Head Select 2 (-HS2/)
6
Ground (GND)
7
iSBC 215 Controller>
Connector J1
50-Pin
0
..
..
.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
-Direction (DIR/)
Ground (GND)
-Step (STEP/)
-Fault Clear (FL T CI_R/)
-Write Gate (WRGATE/)
Ground (GND)
-Track 0 (TRACK 0/)
Ground (GND)
-Write Fault (FAULT I)
Ground (GND)
-Read Gate (RDGA -rEI)
37
38
Ground (GND)
Ground (GND)
Drive 0 20-Pin
0
3
2
4
31
~
32
27
5
6
Seek Complete (SKCOMO/)
7
8 Ground (GND)
9 -Write Data (WRO-)
....
...
•.
...
....
~
.
..
.
15
40
11
36
16
41
22
47
23
48
24
49
10
+Write Data (WRO+)
Ground (GND)
11
12 -Write Clock (WRCLO-)
13 +Write Clock (WRCLO+)
14 Ground (GND)
0
29
....
..
....
10
5
24
22
....
26
6
4
..
....
Memorex/14" Shugart Drive
Mating Connector
Drive 1
21
20-Pin
44
0
iSBC 215 Controller·
Connector J2
40-Pln
CD
..
38
•
1
2
18
3
..
..
13
5
4
38
6
17
7
33
8
9
9
35
10
12
11
37
12
40
13
14
15
16
'iSBC 215'· Controller (signal name) in parentheses.
"When interface with a 14" Shugart drive pins 15 and 16 on
both radial connectors s.hould be swapped: pin 15, +PLO
Clock (RDCLO+); pin 16, -PLO Clock (RDCLO-).
-Seek Complete (SKCOM1/)
Ground (GND)
-Write Data (WR 1-)
+Write Data (WR1+)
Ground (GND)
-Write Clock (WRCL 1-)
+Write Clock (WRCL 1+)
Ground (GND)
-PLO Clock (RDCL 1-)
+PLO Clock (RDCL 1+)
Ground (GND)
17
+Read Data (RD1+)
18
-Read Data (RD1-)
19
Ground (GND)
20
..
..
..
..
..
..
....
....
..
..•
Figure 2-4. Fujitsu 2300/Memorexll4" Shugart Drive Interconnecting Cable Requirements
2-12
•
..
..
..
25
20
..
15 .. _-P_L_O_C_IO_C_k....;(:...R_D_C_L_O-...:.)_ _ _ _ _ _ _ _---l~
23
+PLO Clock (RDCLO+)
16
3
Ground (GND)
17
25
18 +Read Data (RDO+)
21
19 -Read Data (RDO-)
2
20 Ground (GND)
7
..
...
.
..
....
40-Pin
•
2
30
..
..
..
iSBC 215 Controller>
Connector J2
1
26
8
9
-Index (INDEX/)
10
Ground (GND)
11
-Drive Ready (READY/)
12
Ground (GND)
13
-Sector/Byte Clock ISECTOR/)
14
Ground (GND)
15
-Drive Select 1 (USO/)
16
Ground (GND)
17
-Drive Select 2 (US1/)
18
Ground (GND)
19
-Drive Select 3 (US~~/)
20
Ground (GND)
21
-Drive Select 4 (US3/)
22
Memorex/14" Shugart Drive
Mating Connector
13
14
•
33
34
35
15
31
32
12
16
30
11
36
•
iSBC 215
Preparation for U8e
•
~ 25
~ 49
0C
~ 50
1---~19
•
0C~
2
~
26
8
0
20
..
40
101
101
2
~
~ 50
21
0
8
50-Pin Card
Edge Connector
50-Pin 3M Female
Connector
40-Pin 3M Female
Connector
20-Pin Card
Edge Connector
29
Memorex/14" Shugart
Drive 0
iSBC 215 Controller
r--
0-
•
•
---==
50-Conductor
-- - Ribbon Cable-
-----
-----"r-~:::~i'.:u:g~a~rt~~ ~=-__________-=: : -~_~_~_:-: -:_:~ - -_- ~_~:4_R:~:b~=-~:~:":": ~:~ :_-_: ~:_:-: -:_~_~_~_-=: ~
________
Memorex/14" Shugart
Mating
~
___
___
__
J2
Connectors
Scramble Wires
at drive.
•
Figure 2-4. Fujitsu 2300/Memorex/14" Shugart Drive Interconnecting Cable Requirements
(Continued)
2-13
iSBC 215
Preparation for Use
Pertec Drive Cable Wiring Diagram
Pertec Drive Mating Connector
50-Pin
1
2
Q)
J1 50-Pin
1/0 Bus Bit 0 (BUS 0/)
1/0 Bus Bit 1 (BUS 1/)
3
1/0 Bus Bit 2 (BUS 2/)
4
110 Bus Bit 3 (BUS 31)
5
6 I/O Bus Bit 4 (BUS 4/)
1/0 Bus Bit 5 (BUS 51)
7
I/O Bus Bit 6 (BUS 6/)
8
9 I/O Bus Bit 7 (BUS 7/)
Ground (GND)
10
Ground (GND)
11
Call Request (COMMAND/)
12
13 Ground (GND)
Drive Request
14
Ground (GND)
15
Transfer Acknowledge (BUS ACK/)
16
17
18 Safe (GND)
19
20
21
Drive Ready
Ground (GND)
I/O Ready (SKCOM/)
22
23 Ground (GND)
Write Gate
24
Ground (GND)
25
Read Gate
26
Ground (GND)
27
28 ReadIWrite Data Plus (RDO- and WRO-)
CD
iSBC 215 Controller Connector-
..
26
..
27
.-
31
32
Ground (GND)
Unit Select a
Unit Select 1
Unit Select 2
33
Unit Select 3
34
Ground (GND)
35
36 ReadIWrite Clock Plus RDCLO-)
37 ReadIWrite Clock Minus (RDCLO+)
Ground (GND)
38
39 Read/Write Address Mark (ADMKEN/)
40
Address Mark Detect (SECTOR/)
41
42 Ground (GND)
Index
43
44
45
46
47
48
49
....
..
..
..
..
..
..
..
..
..
..
..
......
..
..
.........
.-
..
..
..
..
..
..
..
3
4
29
5
30
31
7
•
32
8
33
14
11
36
19
37
13
38
12
39
40
22
!
t
:
:
24
2
5
24
25
41
•
21
23
..
..
23
..
22
..
4
3
•
44
42
16
47
15
Ground (GND)
*iSBC 215'· Controller (signal name) in parentheses.
..
Figure 2-5. Pertec Drive Interconnecting Cable Requirements
2-14
•
28
Ground (GND)
Ground (GND)
0
2
29 ReadIWrite Data Minus (RDO+ and WRO+)
30
J2 40-Pin
1
25
•
Preparation for Use
iSBC 215
•
~
•
2
o
49
~ 50
iO~Pin
3M Female Connector
26
..
25
..
50
21
G
40
215
Ribbon Cable
~1C=======5~o_con~duet~or========~0
~
Pertee Mating
Connector
•
..
iSBC Controller
Pertec
•
20
40-Pin 3M Female Connector
Drive
•
~
\
J1
at drive.
Scramble Wires
40-Conduetor
Ribbon Cable
J2
Figure 2-5. Pertec Drive Interconnecting Cable Requirements (Continued)
2-15
iSBC 215
Preparation for Use
Priam Drive Mating Connector
50-Pin
1
Priam Drive Cable Wiring Diagram
CD
J1 50-Pin
2 +DBUS 0 (BUS 0/)
•
+DBUS 1 (BUS 1/)
3 ~~~~~~~-----------------------------------------~.~
+DBUS 2 (BUS 2/)
4 --~--~----~.----------------------------------------~.~
+DBUS 3 (BUS 3/)
5 __----~--~~-----------------------------------------~.~
6 +DBUS 4 (BUS 4/)
..
+DBUS 5 (BUS 5/)
7
8 +DBUS 6 (BUS 6/)
9 +DBUS 7 (BUS 7/)
Ground (GND)
10
-READ GATE
11
12 Ground (GND)
......
..
....
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
_G_ro~u~n~d_(~G~N~D~)____.________________________________________~..~
-WRITE GATE
~--~~~----.----------------------------------------~..~
Ground (GND)
..
-RD
~=-----------.----------------------------------------~.~
-WR
--------------.----------------------------------------~.~
+AD1
--------------.----------------------------------------~.~
+ADO
~--~~~----.----------------------------------------~..
~
Ground (GND)
~-D~R~IV=E~S~E~L~E~C~T~1------------------------------------------~..
~
~-D~R~IV=E~S~E~L~E~C~T~2------------------------------------------~.~
--D~R~IV=E~S~E~L~E~C~T~3------------------------------------------~..~
--D~R~IV=E~S~E~L~E~C~T~4------------------------------------------~..
~
------__
~--------------------------------------------~..~
Ground (GND)
~--~~~----.----------------------------------------~.~
Ground (GND)
--------------.----------------------------------------~.~
-HEAD SELECT 3
~~~~~~~----------------------------------------~.~
-HEAD SELECT 2
~~~~~=-~.----------------------------------------~.~
-HEAD SELECT 1
------------------------------------------------------~.~
Ground (GND)
•
-INDEX
~--~~~----.----------------------------------------~..
~
Ground (GND)
--~RE~A~D~Y~--~--------------------------------------------~..
~
~--~~~----.----------------------------------------~..
~
Ground (GND)
--S~E~C~T~O~R~M7A~R~K~------------------------------------------~..
~
~--~~~----.----------------------------------------~..
~
Ground (GND)
~~~~~-------------------------------------------~..
+WRITE DATA
®
iSBC 215 Controller Connector
J240-Pin
0
1
26
2
27
3
28
4
29
5
30
12
31
32
•
13
33
7
20
45
21
35
22
23
24
25
38
39
43
18
10
41
15
19
11
44
16
47
-WRITE DATA
Ground (GND)
+WRITE CLOCK
-WRITE CLOCK
Ground (GND)
+READ/REFERENCE CLOCK
-READ/REFERENCE CLOCK
Ground (GND)
+READ DATA
•
..
•
..•
•
•..
..•
•
5
24
22
26
6
4
23
3
25
48 ~-R~E~A~D~D~A~T~A------------------------------------------------------------------~.. 21
49
.. 2
50 Ground (GND)
*iSBC 215 Controller (signal name) in parentheses .•
TO
7
Figure 2-6. Priam Drive Interconnecting Cable Requirements
2-16
•
•
iSBC 215
Preparation for Use
•
~ 49
•
o
. . 50
. . 25
26
..
21
50
(2)
50·Pin 3M Female Connector
..
20
..
40
40-Pin 3M Female Connector
Priam
iSBC 215 Controller
Drive
--~
•
5G-Conductor
Ribbon Cable
Priam Mating
Connector
\
J1
Scramble Wires
at drive.
•
•
40-Conduetor
Ribbon Cable
J2
Figure 2-6. Priam Drive Interconnecting Cable Requirements (Continued)
2-17
iSBC 215
Preparation for Use
51ft" RMS Drive Cable Wiring Diagrams
Isec 215 Controller'
Mating Connector J1
5'1'" RMS Drive 0
Mating Connector
34-Pin
(2)
0
50-Pin
1
1
2
3
-Head Select 22 (-HS21)
4
Ground (GND)
5
Write Gate (WRGATE)
6
Ground (GND)
7
-SEEK COMPLETE (SKCOM!)
8
Ground (GND)
9
Track 000 (TRACK01)
10
Ground (GND)
11
Write Fault (FAULT!)
12
Ground (GND)
13
-HEAD SELECT 2° (-HSO!)
14
Ground (GND)
15
16
17
-HEAD SELECT 2' (-HS1!)
18
Ground (GND)
19
-INDEX (INDEX!)
20
Ground (GND)
21
-READY (READY!)
22
Ground (GND)
23
Step (STEP!)
24
25
-DRIVE SELECT 1 (USO!)
26
Ground (GND)
27
-DRIVE SELECT 2 (US11)
28
Ground (GND)
29
-DRIVE SELECT 3 (US2!)
30
Ground (GND)
31
-DRIVE SELECT 4 (US3!)
32
33
-DIRECTION IN (DIR!)
34
.. 27
.. 30
~
13
•
.
38
..
19
44
.. 17
41
....
•
9
34
.. 26
.. 31
•.. 322
.
.•
....
•
15
39
11
35
.. 20
22
47
.. 23
.. 48
.··24
.. 49
..
•
25
21
RMS Drive 0
Mating Connector
RMS Data Separator
Mating ~nector
2o-Pin
4
..
-DRIVE SELECTED!
Ground (GND)
2o-Pin
1
0
3
4
5
•..
6
7
..•
...
8
9
.. 10
.. 11
.. 12
13
14
15
..
.
16
18
19
.. 20
0
•
....
•
iSeC 215 Controller Connectors'
J1 Mating Connectors J2
-READ GATE (RDGATE!)
Ground (GND)
50-Pin
2
-AMF (SECTOR!)
3
Ground (GND)
4
-WRAM (ADMKEN!)
5
Ground (GND)
6
-RWC (RDWRCURI)
7
Ground (GND)
8
+NRZ WRITE DATA (WRO+)
9
-NRZ WRITE DATA (WRO-)
10
Ground (GND)
11
+WRITE CLOCK (WRCLO-)
12
-WRITE CLOCK (WRCLO+)
13
Ground (GND)
14
+READ CLOCK (RDCLO+)
15
-READ CLOCK (RDCLo-)
16
Ground (GND)
17
+NRZ READ DATA (RDO+)
18
-NRZ READ DATA (RDQ-)
19
Ground (GND)
20
0
•
17
•
4o-Pin
•
12
.. 36
.. 16
.
~
37
42
• 40
*iSBC 215'· Controller (signal name) in parentheses .
Figure 2-7. 5W' RMS Drive Interconnecting Cable Requirements
2-1 R
2
..
....
•
1
..•.
2
SPARE
3
Ground (GND)
4
SPARE
5
Ground (GND)
6
SPARE
7
Ground (GND)
8
+TIMING CLK
9
-TIMING CLK
10
Ground (GND)
11
Ground (GND)
12
+MFM Write Clock
13
-MFM Write Clock
14
Ground (GND)
15
Ground (GND)
16
+MFM READ DATA
17
-MFM READ DATA
18
Ground (GND)
19
Ground (GND)
20
RMS Data Separator
Mating Connector J5
8
2o-Pin
27
8
..• 245
.
25
.. 26
..•
..
6
7
3
23
4
.. 21
....
2
22
•
iSBC 215
•
Preparation lor Use
Control Data Corp Drive Cable Wiring Diagrams
Isac 215 Controller*
Mating Connector J1
Drive Mating
Connector
50-Pin
(2)
50-Pin
0
1
•
•
•
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Ground (GND)
Read Enable (RDGATE/)
..
.. 37
12
.
Fault Reset (FLTCLI~1)
.
-Head Select 2' (HS4)
Ground (GND)
....
Head Select 2° (HSO/)
Ground (GND)
18
2
31
Vcc
T
Byte Clock"
26
30
to Sector
Pulse Conversion
Logic
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Step (STEP/)
•
Write Gate (WRGATE/)
Ground (GND)
TRACK 0 (TRACK O/)
.. 13
.. 38
.. 17
...
Ground (GND)
Write Fault (FAULT/)
Ground (GND)
.
(SECTOR/)
-Direction (DIR/)
Ground (GND)
,
•
...
.....
..
9
33
16
215 Controller
Mating Connector J2
15
.. 40
1
2
~
~~ .. J2 - 29 (SKCMO) 3
4
5
.. 40
6
22
7
47
8
• 23
9
~ 48
10
24
11
49
12
25
13
14
21
15
44
16
17
18
19
20
35
Isac
Drive Mating Connector
2o-Pin
-INDEX (INDEX/)
Ground (GND)
Drive Ready (READY/)
Ground (GND)
Byte Block
Ground (GND)
Drive Select 1 (USO/)
Ground (GND)
Drive Select 2 (US1/)
Ground (GND)
Drive Select 3 (US~:/)
Ground (GND)
Drive Select 4 (US:::/)
20
~
--~..
~ J1 - 15
- - - - '..
~ J2 - 10
To Sec tor Generator Board
)-
J 1 - 11
Write Data + (WRO+)
Write Data - (WRO-)
Ground (GND)
Write Clock + (WRCLO+)
Write Clock - (WRCLO-)
Ground (GND)
Servo Clock + (RDCLO+)
Servo Clock - (RDCLO-)
Ground (GND)
Read Data + (RDO+)
Read Data - (RDO-)
Ground (GND)
...
5
24
..
.....
...
22
26
6
4
3
23
38
21
2
7
.....
.
"Refer to Drive Manufacturer for Application Details
•
Figure 2-8. Control Data Corporation Drive Interconnecting Cable Requirements
2-19
iSBC 215
Preparation for Use
•
..
81
2
81
..
..
..
49
01
I
..
50
19
...
26
... 20
25
I01
21
50
•
8
50-Pin Card
Edge Connector
0
40-Pin 3M Female
Connector
(0
50-Pin 3M Female
Connector
0)
2o-Pln 3M Female
Connector
40
29
Memorex/14" Shugart
iSBC 215 Controller
Drive 0
50-Conductor
Ribbon Cable
J1
•
•
Memorex/14" Shugart
Drive 0
~==;::_=~=-~---~~---IG
•
J2
Scramble Wires
at drive.
Figure 2-9. Control Data Corporation Drive Interconnecting Cable Requirements
2-20
•
iSBC 215
•
DRIVE
o
Preparation for Use
DATA
SEPARATOR
DRIVE 2
DRIVE 1
•
DRIVE 3
'Internal Termination:
Jl
220/330 n, RPAK,
DIP @ IC Location
Shugart - BC
Quantum - J6
RMS -
J2
iSSC 215
CONTROLLER
INTERFACE WITH 8" SHUGART/QUANTUM OR 5'1<" RMS DRIVES
NOTE
Termination locations
may change. Consult
DRIVE 0
DRIVE 1
manufacturer's
hardware reference
manual for drive.
'Internal Termination:
220/330 n, RPAK.
DIP @ IC Location
Memorex - 18D
Shugart - 3H
•
CONTROL
Jl
J2
iSSC 215
CONTROLLER
•
INTERFACE WITH MEMOREX/14" SHUGART DRIVES
DRIVE 1
DRIVE 0
DRIVE 2
DRIVE 3
CONTROL AND
RIOADIWRITE
READIWRITE
CONTROL
31nternal Terminator:
220/330 nRPAK,
DIP, located @
Pertec - U134
J1
Priam - Near Interface
Connector
J2
ISBC 215
CONTROLLER
•
INTERFACE WITH PERTEC AND PRIAM DRIVES
Figure 2-10. Controller to Drive Interfacing
2-21
Preparation for C se
Table 2-8. J3 and J4 Pin Assignments
Pin
Mnemonic
43
MD8
41
Description
Description
Pin
Mnemonic
MDATA Bit 8
44
MD9
MOATA Bit 9
MDA
MOATA Bit A
42
MDB
MOATA Bit B
39
MOC
MDATA Bit C
40
MOD
MOATA Bit D
37
MOE
MDATA Bit 3
38
MOF
MDATA Bit F
35
GNO
Signal Ground
36
+5V
+5 Volts
33
MDO
MOATA Bit 0
34
MORQT
M OMA Request
31
M01
MOATA Bit 1
32
MOACKI
M OMA Acknowledge*
29
M02
MOATA Bit 2
30
OPTO
Option 0
27
MD3
MDATA Bit 3
28
OPT1
Option 1
25
MD4
MOATA Bit 4
26
RDMA
Terminate DMA
23
MD5
MDATA Bit 5
24
21
MD6
MDATA Bit 6
22
MCSOI
M Chip Select 0
19
M07
MDATA Bit 7
20
MCS11
M Chip Select 1
17
CND
Signal Gnd
18
+5V
+5 Volts
15
10RDI
1/0 Read Cmd
16
MWAITI
M Wait
13
10WRT/
1/0 Write Cmd
14
MINTRO
M Interrupt 0
11
MAO
M Address 0
12
MINTR1
M Interrupt 1
9
MA1
M Address 1
10
7
MA2
M Address 2
8
MPSTI
iSBX Multimodule
Board Present
5
RESET
Reset
6
MCLK
M Clock
3
GND
Signal Gnd
4
+5V
+5 Volts
1
+12V
+12 Volts
2
-12V
-12 Volts
All undefined pi ns are reserved for future use.
2-18. iSBX MULTIMODULETM INTERFACE
Controller board connectors J3 and J4 have each
been designed to interface with Intel iSBX I/O
controllers or other I/O modules designed to meet
the Intel iSBX Bus Specifications. The Intel iSBX
218 Flexible Disk Controller connects to the J4
connector and provides an interface between the
iSBC 215 controller board and up to four 5W' or 8"
double density flexible (floppy) disk drives. The
iSRX 218 controller interfaces directly with the iSBC
21.5 software as described in Chapter:03. Instructions
for installing the iSBX 218 controller on iSBC 21.5
board are given in Paragraph 2-18.
Reserved
Reserved
"The iSBC 215 does not drive this signal.
•
•
•
•
1/0 modules that interface the iSBC 215 controller
with other storage devices such as magnetic tape
cartridge drives or bubble memories can also be
designed and connected to J3, J 4 or both, (see Table
2-8). The device select function of the iSBC 215 software allows the controller to be interfaced with up to
256 devices through an iSBX connector, J3 and J4.
Note that DMA Acknowledge Pin 32 is not connected on the iSBC 215. A more detailed description
of the iSBX Bus is given in the Intel iSBX Bus Specification manual, Order No. 142686.
The iSBX bus control pins, W3, W4, WH, W12 and
W24 (see Table 2-9), control the External Terminate,
•
iSBC 215
Preparation for Use
•
•
,SBG " 215 BOARD
•
•
Figure 2-D. Installing the iSBX 21WM Board on the iSBC 215™ Controller Board
and DMA request lines on the iSBX bus. (See Figure
5-1 for the location of these pins on the controller
board.) The asterisks in Table 2-9 indicate the
required jumper configuration for these pins when
the iSBX bus is not to be used. Information on the
USE' of these pins fOI" user designed iBBX bus interfaces is given in Paragraph ~l-32.
•
Instructions for writing controller-to-drive interface
software for I/O modules designed to the iSBX Bus
Specifications are given at the end of Chapter ;1.
2-19. iSBX 218™ BOARD INSTALLATION
The iSEX 218 board connects to J4. Six screws and
three threaded spacers secure the Multimodule board
to the controller board as shown in Figure 2-9. Before
installing the iSBX 218 board, install a jumper wire
between pins W12-1 and W12-3 and between pins W41 and W4-2 on the iSEX 215 board. A single cable
that transmits both control and read/write information is required to connect the iSEX 218 controller to
the flexible disk drives as shown in Figure 1-2. Refer
to the iSEX 21 grM Flexible Disk Controller Hardware
Reference Manual. In tel Order No. 121 fiH::l. for
further installation details and operating information.
2-2:)
iSBC 215
Preparation for Use
Table 2-9. iSBXTM Bus Control Jumper Pins
Pins
W3
Pin
Connection
1-2*
-
W4
W11
W12
External Terminate (J3) driven by
iSBX I/O Controller
External Terminate (J4) terminated
on controller board
-
External Terminate (J4) driven by
iSBX I/O controller
1-2
OPOO (J3) driven
1-3
- *
OP01 (J4) driven
1-2
OP10 (J3) driven
OP11 (J4) driven
1-2
1-3
- *
I
External Terminate (J3) terminated'
on controller board.
1-2*
1-3
- *
W24
f'unction
OPOO and OP01 receiving
OP10 and OP11 receiving
The iSBX I/O controller on J4 uses
DMA request and the iSBX i/O controller on J3 does not use DMA request or is not installed.
The iSBX I/O controller on J3 uses
DMA request and the iSBX I/O con·troller on J4 does not use DMA request or is not installed.
Either both iSBX I/O controllers are
not installed or both use the DMA
request or neither use the DMA
request.
*Required configuration when either the external terminate function or when the iSBX'· Bus is not being used
(factory wi red).
2-20. POWER UP/DOWN
CONSIDERATIONS
If power is applied to, or removed from, the system
while a drive is READY, a spurious disk write
operation could occur. To prevent this from happening always ensure that the drives are not spinning
when system power to the controller is switched on
or off.
•
2-21. DIAGNOSTIC CHECK
A PROM-resident self-diagnostic may be used to
verify the controller operation. Instructions for
execution of the diagnostic are given in Chapter 3.
•
•
•
2-24
•
•
[
CHAPTER 3
_ _ _ _P_R_O_G_R_A_M_M_IN_G_IN_F_O_R_M_A_T_IO_N_____
3-1. INTRODUCTION
This chapter describes the programming conventions that must be followed to initiate and monitor
the transfer of data between the host memory and a
disk drive (or the iSBX connector). Included in this
section are a discussion of: disk organization, track
sectoring format, diBk controller communications
protocol, interrupt handling, the use of disk control
functions, and special instructions for programming
I/O transfers through the iSBX interface.
•
•
3-2. PROGRAMMING OPTIONS
The iSBC 215 Winchester Disk Controller has been
designed to interface with Winchester technology
disk drives as specified in Chapters 1 and 2. The
board also has two iSBX connectors that allow it to
communicate with other I/O devices through an
iSBX I/O Controller such as the iSBX 218 Flexible
Disk Controller.
The iSBC 215 controller contains a ROM resident
I/O transfer program, designed to control data
transfers between the controller and Winchester
drives as well as between the controller and flexible
disk drives connected to the iSBX 218 controller.
Paragraphs 3-5 through 3-30 provide instructions for
using the iSBC 215 controller firmware.
In addition, the iSBC 215 controller can also execute
programs that the user has written in 8089 assembler
code to control other I/O devices through the iSBX
bus on the board. Instructions for writing and using
these programs are provided in Paragraphs 3-31 and
3-32.
3-3. DISK ORGANIZATION
In the following discussion, a head is assumed to be
associated with a single disk surface. Each surface
can have up to 4096 tracks (circular data paths
numbered 0 through 4095). The set of tracks on
multiple recording surfaces at a given head position
or location is referred to as a "cylinder" (see Figure
3-1). A drive that has 4096 tracks per surface thus
has 4096 cylinders.
Each track is divided into equal-sized sectors. Each
of these sectors includes a sector identification block
with error checking information and a data block,
also with error checking information. The iSBC 215
controller allows the user to select the size of the data
block; the size of the data block then determines the
maximum number of sectors permitted per track (as
shown in Table 1-1).
TRACK
•
•
HEAD
SURFACE
/
=
Figure 3-1. Disk Drive Organization and Terminology
3-1
iSBC 215
Programming Information
3-4. TRACK SECTORING FORMAT
3-5. CONTROLLER 1/0
COMMUNICATIONS BLOCKS
The controller generates the format of the sector
identification block, the data block and the error
checking fields of each sector of the disk, one track at
a time. Figure 3-2 shows how the controller organizes
this information for 8" Winchester drives. Refer to
Paragraph 3-14 and 3-15 for further information on
track formatting. Refer to the iSBX 218™ Flexible
Disk Controller Hardware Reference Manual for
information on flexible disk track formatting.
The host processor and the disk controller use four
blocks of host memory and one host I/O port to
exchange instructions and status. The I/O communications blocks are titled: Wake-Up Block, Channel
Control Block, Controller Invocation Block and I/O
Parameter Block. Sixty-eight bytes of host memory
must be dedicated to the I/O communications
blocks.
•
_________________________________________________________nL
INDEX
INDEX
-11~
_ __
•
DATA BYTES (128. 256. 512 or 1024)
•
GAP AND FIELD SIZES IN BYTES
FIELD
GAP 1
ADDRESS MARK
OR SECTOR PULSE
GAP 2
ID FIELD
GAP 3
ADDRESS MARK
(Beginning of
Data Field)
8" SHUGART/RMS/
QUANTUM
FUJITSU 2300/
MEMOREX/
14" SHUGART
CDC 9410 - 32
PERTEC
11
1
0
0
9
12
14
9
9
9
12
20
0
20
l'
14
0
133
261
517
1029
17
133
261
517
1029
8
133
261
517
1029
22
133
261
517
1029
8
0'
11
3
PRIAM
0
02
12
0
•
DATA FIELD
Bytes/Sector
128
256
512
1024
GAP 4
'8" Shugart/Quantum drives only.
'Sector Pulse
'GAP 5 is of indeterminate length. It is residual unused space.
Figure 3-2. Sector Data Format
3-2
•
Programming Information
iSBC 215
•
®
HOST
PROCESSOR
r---------,
II [
WAKE-UP
BLOCK
r--------,
I
I
INTEL
8089
I
lOP
'
DISK
DRIVE
UNIT
I
I
I
o
'I
I
I
I
•
•
I
I
I
I
I
[
CHANNEL
CONTROL
BLOCK
~ ONTROLLER
INVOCATION
BLOCK
([
1/0
)
PARAMETER
~
BLOCK
[
DATA
MEMORY
I
IL
HOST SYSTEM MEMORY
---------
I
I
J
Figure 3-3. Host CPU-Disk Controller Interaction Through the I/O Communications Block
•
•
NOTE
Following the initialization of the controller,
the Wake-Up Block, Channel Control Block
and Controller [nvocation Block must be
maintained at their assigned locations. The
location of the I/O Parameter Block can be
changed providirlg that the I/O Parameter
Block Pointer in the Controller Invocation
Block is changed to correspond to the new
location.
The controller uses these blocks to perform three
basic functions: initialize the controller, check and
transmit status, and obtain user selected disk access
functions and parameters. In addition to these I/O
communications blocks, certain controller functions
(such as track formatting) also require data/parameter buffers in host mem'ory. Dedicated locations in
host memory, however, are not required for these
buffers. One I/O port in the host processor's address-
able I/O space is also required. The host uses this
port, called the Wake-Up I/O Port, to initiate
controller activity.
The sequence in which the controller accesses these
blocks varies with the type of operation being
performed, but for general data transfers (reads or
writes), the blocks are accessed as follows:
The host loads the I/O Parameter block in
system memory with a command and parameters for the function the controller is to
perform (for example read data). See Figure 3-3.
®
The host then transmits a wake-up command
(OlH) to wake-up I/O port, signaling the controller to go to I/O communications blocks for
instructions.
®
The controller goes to the Channel Control
Block and links its way through the Controller
Invocation Block to the I/O Parameter Block.
(The Wake-Up Block is used only during controller initialization and by R089 firmware.)
3-3
iSBC 215
Programming Information
®
®
At the 110 Parameter Block, the controller reads
the command and parameter data into its RAM
and begins the data transfer function.
The controller reads data from the selected drive
into its RAM, then performs a DMA transfer of
the data from RAM into system memory.
When the data transfer is complete, the controller posts the status in the Controller Invocation
Block, sends an interrupt to the host and awaits
further instructions.
These 110 communications blocks are accessed in a
similar manner when performing a write function.
A detailed description of these blocks and the data
required in each is provided in Paragraphs 3-7
through 3-11. Refer to Paragraphs 2-7 through 2-10
for a discussion of selecting the wake-up address,
wake-up 110 port address and 8-bit or 16-bit host.
3-6. HOST CPU-CONTROLLER-DISK
DRIVE INTERACTION
RESET CONTROLLER - Performs hardware reset of controller. A clear interrupt (OOH) must
be initiated following this command. (Each time the controller
is reset, the communications
link between the controller and
the host must be re-established
through the Initializing function.)
03H through FFH Reserved.
02H
•
The sixteen wake-up address switches on the controller board determine the address of the wake-up 110
port as described in Paragraph 2-9.
3-8. WAKE-UP BLOCK
The Wake-Up Block is the first ofthe 110 communications blocks (see Figure 3-4). It is used to establish
a link between the controller and the 110 communications blocks in host system memory.
•
3-9. CHANNEL CONTROL BLOCK
Figure 4-2 shows a simplified block diagram of the
major hardware sections of the host CPU, host
memory, controller and disk drives. The host system
memory contains all the controller 110 communications blocks. as well as the data buffers. The host
initiates controller activity through the wake-up 110
port, which it addresses through the Multibus interface. The Intel 8089 I/O processor (lOP) handles all
communications between the host CPU, host memory and disk drives, once the host has initiated controller activity. Controller operations software is
contained in on-board PROM. RAM on the controller
board facilitates intermediate data storage between
the host and the disk drive. The iSBX bus provides a
second 110 transfer path between the controller and
an 1/0 controller such as the iSBX 218 Flexible Disk
Controller.
3-7. WAKE-UP I/O PORT
To invoke controller activity, the host CPU transmits
a wake-up command byte to the controller through
the wake-up 110 port. Three wake-up commands are
allowed:
OOH
OlH
3-4
CLEAR INTERRUPT - Controller to host interrupt is reset;
eontroller reset is cleared.
START OPERATION - Instructs controller to start the
operation that the elements of
the 110 parameter block define.
The controller uses the Channel Control Block to
indicate the status of the internal processor (the
Intel 8089 110 Processor) and to invoke processor
program operations. The Channel Control Block
requires 16 bytes (see Figure 3-5). Except for the
BUSY 1 flag (byte 1) and the Controller Invocation
Block address (bytes 2 through 5), the information
contained in this block is used to invoke controller
operations that are transparent to the host.
•
3-10. CONTROLLER INVOCATION BLOCK
The controller uses the Controller Invocation Block
(CIB) to post status to the host CPU and to locate the
starting address for the controller's on-board disk
interface program. The status semaphore byte (byte
3) has a special purpose. The host uses this byte to
indicate to the controller whether it has read the
current contents of the status byte and is ready for a
status update. The Controller Invocation Block
requires 16 bytes (see Figure 3-6).
•
3-11. I/O PARAMETER BLOCK
The 110 Parameter Block (IOPB) contains the
controller operating commands, which define the
function the controller is to perform (read, write,
etc.), and the parameters of the function (memory
address, disk head and cylinder, etc.). The 110
Parameter Block requires 30 bytes of host memory
space. Figure 3-7 describes the function of each byte.
•
iSBC 215
Programming Information
•
I
(Reserved) •
1
0
7
0
7
01H
0
3
CCB Offset
2
5
CCB Segment
4
~
Wake-Up Address
• Set to all zeros.
Function
Byte
0
SYSTEM OPERATION COMMAND -
1
Reserved.
CHANNEL CONTROL BLOCK (CCB) ADDRESS (Address = Offset + Segment X 24).
2 through 5
•
Must be set to 01 H.
Address of first byte of Channel Control Block.
Figure 3-4. Wake-Up Block
0
7
1
•
7
I
BUSY 1
0
CCW 1
0
3
CIB Offset
2
5
CIB Segment
4
7
(Reserved)'
6
9
I
BUSY 2
CCW 2
8
11
CP Offset
10
13
CP Segment
12
15
CONTROL POINTER
14
• Set to all zeros.
•
0
1
2 through 5
6 and 7
8
9
10 through 13
14 and 15
•
Function
Byte
CHANNEL CONTROL WORD 1 - Indicates location of Intel 8089 1/0 Processor control store program:
01 H - Controller local memory (ROM)
03H - Host system memory. (Used only when executing user written 1/0 program from host memory.
(Refer to paragraph 3-32.)
f3USY 1 FLAG - Indicates whether controller is busy or idle.
OOH - Idle
FFH - Busy
CONTROLLER INVOCATION BLOCK (CIB) ADDRESS Invocation Block.
Address of fifth byte of Controller
r~eserved.
CHANNEL CONTROL WORD 2 - Must contain 01H.
BUSY 2 WORD - Not meaningful to host CPU.
CONTROL POINTER ADDRESS - Address must point to the Control Pointer in the next sequential
word.
CONTROL POINTER - Must be set to 0004H.
Figure 3-5. Channel Control Block
3-5
iSBC 215
Programming Information
7
0
0
7
1
Op. Status
(Reserved) •
0
3
SI. Sema.
CMND Sema.
2
5
CSA Offset
4
7
CSA Segment
6
9
IOPB Offset
8
11
IOPB Segment
10
•
12
13
(Reserved )'
15
14
• Set to all zeros.
Function
Byte
0
Reserved.
1
CONTROLLER OPERATION STATUS - Bits 0 through 2 indicate event completed. Bit 3 indicates
the device that completed the event. Bits 4 and 5 indicate drive associated with event. Bit 6 indicates
error: soft (recoverable), 0, or hard, 1. Bit 7 indicates a summary error that can be checked through
the transfer error status function (refer to paragraph 3-28).
I 71 6 15
•
41 3 1 2 1 1 1 0 1
---
I
Operation Complete
Seek Complete
Media Change Detected
Device: 0 = Winchester Disk Drive
1 = iSBX 218'· Flexible Disk Drive
Unit ID
•
Hard Error
•
Summary Error
2
COMMAND SEMAPHORE processor interlock.
3
STATUS SEMAPHORE - Controller posts status only when this byte is OOH: when new status has
been posted, controller sets byte to FFH. When host CPU has read status, it sets this byte to OOH .
4 through 7
12 through 15
Reserved
Controller does not use this byte. It is provided for use as a multi-
CONTROL STORE PROGRAM ADDRESS program Set to OOOOH.
I/O PARAMETER BLOCK ADDRESS -
Starting address of controllers on-board disk interface
Address of first byte of I/O parameter block.
•
Figure 3-6. Controller Invocation Block
3-12. TYPICAL CONTROLLER
OPERATIONS
The following section describes how to set up the I/O
communications blocks in the host memory, how to
initialize the controller and how to perform the
various data transfer operations. It is assumed that
the controller board has been properly installed as
descrihed in Chapter 2.
3-6
3-13. INITIALIZING THE CONTROLLER
The controller must be initialized before any data
transfer activities between the host system memory
and the disk drives can be initiated, Initialization of
the controller involves:
1.
Establishing a link between the 8089 and the
I/O communications blocks in host system
memory.
•
Programming Information
iSBC 215
•
o
7
3
o
7
(Reserved)'
o
(Reserved),
2
4
5
Actual Transfer Count
6
7
11
13
Modifier
15
Cylinder
10
12
14
16
Head
19
DB Offset
18
21
DB Segment
20
22
23
Requested Transfer Count
25
24
26
General Address
Pointer Offset
General Address
Pointer Segment
29
•
Unit
I
Sector
27
•
I
Function
17
•
8
Device Code
9
28
, Set to all zeros.
Byte
o through
3
4 through 7
Name and Function
Fleserved.
ACTUAL TRANSFER COUNT - Count of bytes actually transferred between the system and the disk
Cor controller. Four-byte binary number, least significant bits in first byte. Controller writes count to
I OPB following termination or completion of an operation. If count does not match requested transfer
count, operation was prematurely terminated; check status. When performing the track formatting
function, a count of 6 is set in the Actual Transfer Count word. When performing the status transfer
function, the count is set to 12. When initializing drive 0, this word has a special function. It is used to dis-play the controller firmware's version number as shown below:
[7 16 151 4131211 I0I
'T
-y--'I...- _ _----..
:: Revision Level
- Version Minus 1
8 and 9
10
DEVICE CODE -
Code for type of device being accessed.
0003H - iSBX 218 5V.' Flexible Disk
OOOOH - 8" Winchester Drive
0001H - iSBX 218 8" Flexible Disk
UNIT - Code for drive unit being accessed: bits 0 and 1 address unit code; bits 2 through 7 are reserved.
[7 16 151 41 31 211 I 0I
-C-'-----l:~ Unit:
o through
11
•
.-----l~
3
I
Volume:
0 - Fixed
1 - Removable
FUNCTION - Code for operation to be performed. Refer to following discussion of typical controller
operations for a detailed discussion of these operations:
OOH
INITIALIZE
01 H
TRANSFER STATUS
02H
FORMAT
Figure 3-7. 1/0 Parameter Block Description
3-7
iSBC 215
Programming Information
12 and 13
14 and 15
16
17
18 through 21
22 through 25
26 through 29
READ SECTOR ID
03H
READ DATA
04H
READ TO BUFFER AND VERIFY
05H
WRITE DATA
06H
WRITE BUFFER DATA
07H
INITIATE TRACK SEEK
08H
Reserved
09H - OBH
iSBX EXECUTE
OCH
iSBX TRANSFER
ODH
BUFFER I/O
OEH
DIAGNOSTIC
OFH
MODIFIER - Code to modify function codes.
Suppresses interrupt on command completion when set to 1.
Bit 0
Bit 1
Automatic retries for error recovery are inhibited when set to 1.
Bit 2
Allows READ DATA, READ TO BUFFER AND VERIFY, WRITE DATA and
WRITE BUFFER DATA functions to be modified to read or write deleted
data, respectively, through the iSBX 218'· I/O controller: 0 = Normal Data;
1 = Deleted Data.
Reserved.
Bits 3 through 15
CYLINDER - Binary number specifying logical cylinder code; bit 0 is least significant bit of number.
HEAD - Binary number specifying logical head code; bit 0 is least significant bit of number.
SECTOR - Binary number specifying logical sector code; bit 0 is least significant bit of number.
DATA BUFFER ADDRESS - Address of first byte in host system memory data (parameter) buffer.
REQUESTED TRANSFER COUNT - Count of bytes requested to be transferred between the system
and the disk or controller. Four-byte binary number, least significant bits in first byte. See description
of ACTUAL TRANSFER COUNT, bytes 4 through 7 in 10PB.
GENERAL ADDRESS POINTER -
NOTE
Reading the parameters that describe the disk
drives with which the controller is to interface
into the controller's RAM buffer, using the
Initialize function (FUNCTION:: OOH).
When the system is first powered-on, the
Pertec or Priam drives will not spin until
each has received an initialize command.
For each drive, the initialize command thus
cannot be completed until the drive has
reached its operating speed and entered the
ready state. This spin-up time varies from
approximately 20 seconds for the Priam
drives to 90 seconds for the Pertec drives.
This initialization must be performed following a:
1.
Power-on event.
2.
Controller reset
port).
(O~~H
written to the wake-up I/O
After the controller has been initialized, any of the
data transfer functions described in Paragraphs 3-14
through 3-25 can be performed in any sequence.
(Refer to Paragraphs 4-12 through 4-15 for a detailed
explanation of controller initialization.)
The following procedure gives the sequence in which
the controller initializing activities must be performed. Prior to initializing the controller, check that
the system data bus switch (S2-1), the host system
I/O address switch {S2-2), the wake-up address
switches (Sl-l through Sl-8 and S2-3 through S2-1O),'
and the interrupt level jumper have been set as
described in the procedure titled Switch/Jumper
Configurations in Chapter 2.
3-8
•
General purpose address pointer.
Figure 3-7. I/O Parameter Block Description (Continued)
2.
•
The Shugart and Memorex drives spin-up as
soon as power is applied. If an initialize
command is issued to a unit that has not yet
reached operating speed, a not ready error is
posted.
•
•
To initialize the controller, the host CPU must
perform the following steps:
1.
Establish addresses for the four 110 communications blocks in host memory:
Wake-Up Block
Channel Control Block
Controller Invocation Block
I/O Parameter Block
6
16
16
30
Bytes
Bytes
Bytes
Bytes
Remember that the address of the first byte of
the Wake-Up Block must be equal to the wake-up
•
iSBC 215
•
•
•
address set in the controller's wake-up address
switches times ~: I. For example, if the switches
are set to 067:3H, the address of byte 0 of the
Wake-Up Block is:
06730H
67:30H
•
20-Bit Addressing
16-Bit Addressing
2.
Set up the shaded bytes in the Wake-Up
Block (see Figure 3-8).
:3.
Set BUSY 1 flag (Optional). Set the BUSY 1
flag (byte 1 of t:he Channel Control Block) to
non-zero (FFH). This allows the host to monitor
the BUSY 1 flag to find out when the initialization procedure i:, complete.
4.
Reset the controller. Host writes a 02H to the
wake-up I/O po:,t.
5.
Clear the reset. Host writes a OOH to the
wake-up I/O port.
6.
Establish the host-controller communications link. Write a 01 H to the wake-up I/O
port. The controJer goes to the Wake-Up Block
in host memory and records the address of the
Channel Control Block, then goes to the Channel
Control Block and clears the BUSY 1 FLAG. On
all subsequent 01H commands to the wake-up
I/O port, the controller will go to the Channel
Control Block.
7.
Set up the shaded bytes in the Channel
Control Block as shown in Figure 3-8.
8.
Set up the shaded bytes in the Controller
Invocation block as shown in Figure 3-8.
Be sure the STATUS SEMAPHORE, byte :3, is
set to DOH.
9.
•
Programming Information
Set up the shaded bytes in the 110 Parameter Block as shown in Figure 3-8. Be sure
the UNIT, byte 10, is set for the correct unit
number and the FUNCTION, byte 11, is set for
the Initialize function (FUNCTION = DOH).
Initialize unit () first.
10. Establish parameter buffer. Set up a disk
drive parameter data buffer with the parameters
for the drive to be initialized as shown in Figure
:3-8. Be sure the data buffer address in the I/O
Parameter Block points to the first address of
this data buffer.
II. Start initialize function. Poll the BUSY 1 flag
(Byte 1 of the CeB) and write a OlH to the wakeup 110 port when the flag is zero. The controller
goes to the Channel Control Block, then links its
way through the Controller Invocation Block
and 110 Parameter Block and reads the disk
drive parameters for the unit specified.
12. Respond to and process the resulting interrupt or status or both.
13. Reset 110 Parameter Block. Set the UNIT,
byte 10, for the next unit to be initialized and set
the data buffer address, byte 18 through 21, for
the beginning address of the unit's disk parameters.
14. Repeat steps 9 through 12 for each drive
unit. Note that the initialization procedure
MUST BE PERFORMED FOR ALL FOUR
IJRIVE UNITS. starting with unit 0, even if one
or more of the drives do not exist. Initialize all
unattached drives with all zeros.
15. Initialize flexible disk drive units. If an
iSBX 218 controller is installed on the iSBX 215
controller board, repeat steps 9 through 14 for all
four flexible disk drive units.
NOTE
The Winchester disk drive units must be
initialized before initializing the flexible
disk drive units.
The controller is now initialized. This procedure
need not be repeated except after a power-on or a
controller reset. For all subsequent disk activities,
the host communicates with the controller through
the Channel Control Block, the Controller Invocation
Block and the I/O Parameter Block.
3-14. TRACK FORMATTING
The Format Track function (FUNCTION = 02H)
writes the gaps, sector headers and data field~ (see
Figure 3-2) on a track - one track per command. A
track can be designated as a normal, assigned
alternate or defective track. A defective track always
points to an assigned alternate track. Refer to the
discussion of alternate and defective track handling
in Paragraph 3-15.
Use the following procedure to format a track.
1.
Set up the 110 Parameter Block as shown
in Figure 3-9.
2.
Set up a 6-byte data buffer for the type of
track to be formatted as shown in Figure 89. A track can be designated as a data track.
assigned alternate track or defective track. The
user pattern is repeated throughout the data
field of every sector. In the ease of a defective
track, the user pattern is a pointer to the
alternate track. If the alternate track is defective,
it can not be used to point to another alternate.
An interleave factor of 1 corresponds to consecutive sectors.
:1-9
iSBC 215
Programming Information
3.
Initiate the format operation. Write a OIH to
the wake-up I/O port.
NOTE
4.
Respond to and process the resulting interrupt or status or both.
Always format the last track on head 0 as a
data track. This track should then be reserved for use by the on-board diagnostic.
Wake-Up Block
~iiililillilliil
(Reserved)
3
5
I/O Parameter Block
o
707
•
Wake-Up Address
7
0 point to this byte.
2 Switches must
3
4
5
o 7
o
(Reserved)
o
(Reserved)
2
4
Actual Transfer Count
7
6
9
8
o
11
10
3
2
13
Modifier
12
5
4
15
Cylinder
14
6
17
16
8
19
18
21
20
Channel Conltrol Block
(Reserved)
7
9
BUSY 2
11
13
12
22
23
Requested Transfer Count
15
14
25
24
27
General Address Pointer Offset
26
29
General Address Pointer Segment
28
•
•
Controller Invocation Block
(Reserved)
o
CMND Sema.
2
Op. Status
3
5
4
7
6
9
8
Data Buffer
Starting address
for controllers
on-board
program.
11
13
12
(Reserved)
15
14
Note: Set up the shaded bytes in each of the I/O
communications blocks and in the data buffer.
7
o
o
o
3
2
5
4
7
6
•
• Bytes 5 and 6 are a word, 5 being the low byte,
6 the high byte.
"This byte defines the bit encoding scheme
when initializing a flexible disk unit connected
to the iSBX 218 T• controller: OOH for FM (single
density) and 01 H for MFM (double density). The
iSBX 218 T• controller does not support 128 bytes
per sector in the MFM mode.
Figure 3-8. 1/0 Communications Blocks Linking
3-10
7
•
Programming Information
iSBC 215
•
1/0 Parameter Block
o
7
3
o
7
(Reserved)
o
(Reserved)
2
4
5
Actual Transfer Count
•
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
22
23
Requested Transfer Count
24
25
•
27
General Address Pointer Offset
26
29
General Address Pointer Segment
28
NOTE
Select one of
the three depending
on the type of
track being formatted.
Data Buffer
o
•
3
2
5
4
Format Data Track
o
Format Assigned Alternate Track
3
2
5
4
o
Format Defective Track
3
2
5
4
'Byte 1 -
•
low byte; byte 2 -
high byte.
Figure 3-9. Track Formatting
3·11
iSBC 215
Programming Information
•
ALTERNATE
TRACK AREA
TRACK ZERO
•
Figure 3-10. Alternate Track Formatting
3-15. ALTERNATE AND DEFECTIVE
TRACK HANDLING
3-16. DATA TRANSFER AND
VERIFICATION
It is suggested that each disk surface be divided into
two areas (see Figure 3-10), the data track area and
the alternate track area. The user assigns the
number of tracks in the alternate track area,
typically 1 - 2(!1) of the total number of available
tracks on the surface. If a disk surface has 512
tracks, tracks 0 through 500 would constitute the
data track area and tracks 501 through 510 would
constitute the alternate track area. The last track
at Head 0 must be reserved for the diagnostic
program.
Nine data transfer and verification command
functions are allowed, selected through the FUNCTION byte in the I/O Parameter Block: Read Sector
ID, Read Data, Read Data to Buffer and Verify,
Write Data, Write Data from Buffer, Initiate Track
Seek, Execute iSBX 110 Program, 110 Transfer
through iSBX Bus, and Buffer I/O.
When a track within the data track area is deemed
defective, the host reformats the track, giving it a .
defective track code and entering the address of the
next available alternate track in the data fields. The
alternate track that is selected must be formatted as
an assigned alternate track.
When the controller accesses a track that has been
previously marked defective, it will automatically
invoke a seek to the assigned alternate track and use
the alternate as if it were in the data track area. This
operation is automatic and is invisible to the user,
except for the added time required to complete the
operation.
3-12
NOTE
All data transfers between the host system
memory and a disk drive unit are buffered
through the controller's on-board RAM
buffer. During a write, the controller performs a DMA transfer of a one-sector block
of data from the host system memory to the
RAM buffer. It then transfers the sector
serially from the RAM buffer to the disk in
two byte increments. When reading from the
disk, the controller performs a serial transfer
of a sector of data from the disk to the RAM
buffer in two byte increments. When the
entire sector has been read into the RAM
and all error checking has been completed,
the controller then performs a DMA transfer
of the one-sector block from the RAM to host
system memory.
•
•
•
Programming Information
iSBC 215
•
•
The controller contains a burst error checking code
(ECC) computing circuit that creates an error
checking code for each sector ID and each data block
written into disk memory. When reading data from
the disk, the controller verifies the sector ID and the
information in the data blocks using these error
checking codes. If e:rrors are detected that can be
corrected (occur within an eleven-bit burst or less),
they are corrected and the remainder of the operation
is completed. If the error cannot be corrected, the
sector is re-read. If after 3 retries the errors remain
un correctable, the operation is terminated and a
Hard Error is indicated in the operation status byte
(byte 1) of the Controller Invocation Block. To obtain
detailed information on the nature of the error,
perform the Transfer Error Status function (refer to
Paragraph 3-28).
Each of the data transfer and verification functions
is described in detail in the following paragraphs. To
use anyone of these functions, the host CPU must
perform the following steps:
1.
2.
•
Set up the I/O parameter block as shown
in the paragraph describing the function.
Initiate the operation. Write a 01H to the
wake-up I/O port.
Respond to and process the resulting interrupt or status or both.
3-17. READ SECTOR ID
The Read Sector ID function (FUNCTION = 03H)
searches for the first error free sector ID on the
selected track and writes the contents of the sector
ID field into a 5-byte data buffer in host memory (see
Figure 3-11). An implied seek, head select or volume
change, is not performed. The Read SE!ctor ID is
performed on the cylinder, volume and head that the
previous function selected. One use of this function
is to search the alternate track area for tracks that
have not been assigned as alternates.
To perform this function, set up the shaded bytes in
the I/O parameter block as shown in Figure 3-11,
and reserve a 5-byte data buffer in host system
memory.
3-1B. READ DATA
The Read Data function (FUNCTION = 04H) reads
data from the disk into host system memory. It
begins reading with the first byte of the selected
1/0 Parameter Block
3
(REtserved)
o
(Reserved)
2
5
Data Buffer
4
Actual Transfer Count
•
3.
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
3
High Cylinder
Low Cylinder
o
Sector
Head
2
Flags
4
Byte 4
Flags
-Czeros
• Sector Size
00 - 128 Bytes
01 - 256 Bytes
10 - 512 Bytes
11 - 1024 Bytes
'-------~ Track Type
22
Requested Transfer Count
25
•
24
27
General Addmss Pointer Offset
26
29
General Address Pointer Segment
28
00
01
10
11
-
Normal
Assigned Alternate
Defective
Invalid
Figure 3-11. Read Sector ID
3-13
Programming Information
iSBC 215
sector and ends reading when the requested byte
count is reached, end of media is reached or a hard
failure is detected. If multi·sector data transfers are
requested the controller automatically seeks to the
next sector, the next head and the next cylinder, in
that order. Automatic head increments are supported
only within the volume, fixed or removable, but not
between volumes, fm example, fixed across to
removable. The last sector, head and track address
in the data track area defines the end of media. An
implied seek is invoked ifthe current head position is
different from the specified track identification. The
DATA BUFFER address set in the I/O parameter
block is the address in host system memory where
the first data byte read from the disk is to be
transferred. Since the data being transmitted from
the disk drive is buffered in the controller's RAM,
data overruns cannot occur. To perform this function, set up the shadpd bytes in the I/O parameter
block as shown in Figure :3-12.
1/0 Parameter Block
o 7
7
o
(Reserved)
o
(Reserved)
2
byte of the selected sector and ends reading when the
requested byte count is reached, end of media is
reached or a hard failure is detected. The multisector data verification is supported through the
auto-sector, auto-head, auto-cylinder protocol described for Read Data function. End of media and
implied seek are also supported as described for the
Read Data functions.
The Read Data into Controller Buffer and Verify
function has three applications:
1.
2.
3.
Allows data to be verified after it has been
written from host system memory to the disk.
Allows data to be transferred from one disk
location to another by coupling this function
with the Write Data from Controller Buffer
function.
Allows data to be transferred from an Winchester disk to a device connected to the iSBX bus. To
perform this operation, the Read to Buffer and
Verify command is coupled with either the iSBX
Execute command or the Write Buffer Data
command (iSBX 218 controller is specified to
receive the data).
4
To perform the Read Data into Controller Buffer and
Verify function, set up the shaded bytes in the 1/0
parameter block as shown in Figure 3-1:3.
7
6
1/0 Parameter Block
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
3
5
Actual Transfer Count
3
(Reserved)
o
(Reserved)
2
5
27
General Address Pointer Offset
26
29
General Adclress Pointer Segment
28
Figure
:~-12.
Read Data
3-19. READ DATA INTO CONTROLLER
BUFFER AND VERIFY
The Read Data into Controller Buffer and Verify
function (FUNCTIOl\" = OilH) reads data from the
disk into the controller on-board RAM and checks
the ECCs to verify the sector ID and data fields for
all sectors affected. It begins reading with the first
:'3-14
•
•
•
4
Actual Transfer Count
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
27
General Address Pointer Offset
26
29
General Address Pointer Segment
28
Figure 3-13. Read Data into Controller
Buffer and Verify
•
•
iSBC 215
•
•
Programming Information
3-20. WRITE DATA
The Write Data function (FUNCTION = 06H) writes
data from host system memory onto the disk. It
begins reading from the specified host data buffer
address and writes to the first byte of the selected
sector. It ends writing when the requested byte count
is reached, end of media occurs or a hard failure is
detected. When writing to more than one sector, the
sector selection is automatic as described for the
Read Data function. Auto-head increments and
implied seek are also supported as described for the
Read Data function. If writing ends in the midst of a
sector, the remaining area of the sector is filled with
zeros.
(4010H) and writes to the first byte of the selected
disk sector. It ends writing when the requested byte
count is reached, end of media occurs or a hard
failure is detected. When writing to more than one
sector, the sector selection is automatic as described
for the Read Data function and the data in the buffer
is repeated for each sector written. Auto-head
increments, implied seek and end of media are also
supported as is described for the Read Data function.
If writing ends in the midst of a sector, the remaining
area of the sector is filled with zeros.
To perform this function, set up the shaded bytes in
the 110 parameter block as shown in Figure 3-15.
To perform this function, set up the shaded bytes in
the 110 parameter block as shown in Figure 3-14.
I/O Parameter Block
I/O Parameter Block
3
(Reserved)
o
(Reserved)
2
(Reserved)
o
(Reserved)
2
4
5
Actual Transfer Count
6
7
3
9
5
4
Actual Transfer Count
•
7
9
11
13
15
17
19
•
21
!gf~!~f
•
I
I1iJ
"'i",''''
11
•
'::/
ti
6
13
{""
i>
15
«<', • "'<
'. " . i.
~~i~l~
14
16
18
20
22
24
27
General Address Pointer Offset
26
29
General Address Pointer Segment
28
Figure 3-15. Write Data From Controller
Buffer to Disk
Figure 3-14. Write Data
3-22. INITIATE TRACK SEEK
3-21. WRITE DATA FROM CONTROLLER
BUFFER TO DISK
•
The Write Data from Controller Buffer to Disk
(FUNCTION = 07H) writes data from the controller
on-board RAM onto the disk. It begins reading from
the first address of the controller's data buffer
The Initiate Track Seek function (FUNCTION =
08H) positions the read/write head on a specified
track, if the head is not already on that track. When
issued sequentially to several drives, this command
allows multiple disk drives to perform concurrent
(overlapping) seeks. If a seek to a cylinder beyond
the end of media, including alternates, is initiated,
the drive automatically performs a rezero operation
3-15
iSBC 215
Programming Information
and posts invalid address error. If an operation
complete interrupt is enabled, it is invoked when the
seek command has been initiated and a seek complete interrupt (which is always enabled) is invoked
when the seek is completed. The operation complete
interrupt allows a function to be initiated on a
second drive while the seek is being performed on the
first drive.
To perform this function, set up the shaded bytes in
the I/O parameter block as shown in Figure 3-16.
To perform this function, set up the shaded bytes in
the I/O parameter block as shown in Figure 3-17.
The outlined bytes are optional. Their use depends
on the requirements of the user written I/O program.
1/0 Parameter Block
3
(Reserved)
o
(Reserved)
2
4
5
Actual Transfer Count
1/0 Parameter Block
6
7
(Reserved)
o
9
(Reserved)
2
11
4
13
Modifier
12
7
6
15
Cylinder
14
9
8
17
10
19
Data Buffer Offset
18
13
12
21
Data Buffer Segment
20
15
14
23
16
25
3
5
17
I:i~
Sector
Unit
Data Buffer Offset
18
27
21
Data Buffer Segment
20
29
22
Requested Transfer Count
25
24
27
General Address Pointer Offset
26
29
General Address Pointer Segment
28
Sector
Head
10
16
24
:>
::::
::.:
::::: :::::
.,•.•,.,•. . .• ,' .,.,•. ,:. •,•.:..•..•..
,: .•·.H
i:.,,:.' . ,•....•••••...•.•. :' •......'" ...'
L
26
28:1
•
When accessing controller RAM,
General Address Segment must be
set to OOOOH.
Figure 3-17. Execute iSBXTM Interface
I/O Program
Figure 3-16. Initiate Track Seek
3-23. EXECUTE iSBXTM I/O PROGRAM
3-24. 110 TRANSFER THROUGH iSBXTM BUS
The Execute iSBX I/O Program function (FUNCTION = OCH) transfers program control to a program stored in the controller on-board RAM memory.
This program must be coded in 8089 assembler code.
It is loaded into RAM using the Buffer I/O function
(FUNCTION I/O =OEH). Program control is transferred to the RAM address specified in the General
Address Pointer, bytes 26 through 29 in the I/O
parameter block. Upon completion of the program,
the program must exit to ROM location OOC5H. The
programs, which this function activates, are written
to perform I/O transfers to peripheral devices
through the iSBX bus (refer to Paragraphs 3-31 and
3-32 for more information concerning the use of this
function).
The I/O Transfer Through iSBX Bus function
(FUNCTION = ODH) transfers a block of data between host system memory and the iSBX bus ports.
The beginning address in host system memory and
the number of bytes to be transferred is specified in
the respective locations in the 110 parameter block.
The iSBX bus port address, width of the port (8 bit or
16 bit), direction of transfer and mode of transfer are
specified in the cylinder and head locations of the
I/O parameter block (Refer to Paragraphs 3-31
through 3-32 for more information concerning the
use of this function.)
3-16
•
22
Requested Transfer Count
19
23
8
Device Code
Actual Transfer Count
11
•
To perform this function, set up the shaded bytes in
the 110 parameter block as shown in Figure 3-18.
•
•
Programming Information
iSBC 215
•
Byte 14 and 15
liD Parameter Block
IiSBX'· Bus 1/0 Port Address I
(Reserved)
0
(Reserved)
2
Port
3
ISBX Bus Port Address Assignments
J3Channel 0
5
6
0
1
C070
C071
COBO
COB1
CODO
COD1
COEO
COE1
9
8
3
4
C073
C074
COB3
COB4
BOD3
COD4
11
10
5
C075
COB5
COD5
COE3
COE4
COE5
13
12
6
7
C076
COB6
C077
COB7
COD6
COD7
15
14
17
16
19
18
21
20
23
22
25
24
29
General Address Pointer Offset
General Address Pointer Segment
•
COE6
COE7
Byte 16
:
o - Unsynchronized
DMA Mode
1 - Synchronized DMA Mode
o - 8 Bit
Transfer
1 - 16 Bit Transfer
26
Fleserved
a - From
iSBX'· Interface to Host
1 - From Host to iSBX'· Interface
28
Figure 8-18. 1/0 Transfers Through iSBXTM Interface
8-25. BUFFER I/O
The Buffer 110 function (FUNCTION = OEH)
transfers data between the host system memory and
controller on-board RAM. Beginning addresses in
the host system memory and controller buffer
memory are specified. Data transfer begins at these
addresses and ends when the requested byte count is
reached. Since the controller has only 64K bytes of
local memory address space, the most significant
bytes of the REQUESTED TRANSFER COUNT
(bytes 24 and 25) are ignored.
Data transfers from the host system memory
to the controller-buffer must be written to
addresses within the range of 4000H to
4600H.
•
J4Channel 1
7
27
•
J4-
4
Actual Transfer Count
•
J3-
Channel 1 Channel 0
The beginning address in controller memory and the
direction of data transfer are specified in the
CYLINDER and HEAD fields, respectively:
Bytes 14 and 15 Starting controller memory address:
Bytes 14 and 15 Starting controller memory address:
Byte 15 - High Byte
Byte 14 - Low Byte
Byte 16
Direction of data transfer:
OOH - From controller to host
FFH - From host to controller
The Buffer I/O function has three applications. Its
primary purpose is for use with the diagnostic
program. It also allows memory-to-memory transfers
with a minimum of host overhead. In addition, it
allows down-loading of user written, I/O transfer
control programs from system memory to controller
memory. Such programs allow 8089 control of I/O
transfers through the iSBX bus as discussed in Paragraph 3-23.
To perform this function, set up the shaded bytes in
the I/O parameter block as shown in Figure 3-19.
3-17
iSBC 215
Programming Information
•
1/0 Parameter Block
3
(Reserved)
o
(Reserved)
2
4
5
Actual Transfer Count
6
7
Device Code
9
11
13
15
l
8
iiiliililililill;~=
10+- though the specified unit is not accessed.
Unit address must be entered even
12
Starting Controller
Memory Address:
Byte 15 - High Byte
Byte 14 - Low Byte
17
Direction of
Data Transfer:
Byte 16 - OOH (from controller to host)
FFH (from host to controller)
19
21
23
22
25
24
27
29
General Address Pointer Offset
General Address Pointer Segment
26
28
•
Figure 3-19. Buffer 110
3-26. DIAGNOSTIC
The diagnostic function (FUNCTION =OFH) causes
the controller to perform a go/no-go self-diagnostic
test that verifies internal data and status electronics
and checks position and read/write electronics in
the disk units. The diagnostic test program is contained in the controller's on-board PROM.
The diagnostic track is always located on a drive
unit's last (highest number) track of head O. When
allocating memory space for the disk unit, this track
must be dedicated to the diagnostic program. When
initiating the diagnostic program, the head and
cylinder are selected automatically, the user selects
the drive unit. The diagnostic test is divided into
three parts. The upper byte of the MODIFIER field
(byte 13) determines the part of the diagnostic test
that is executed:
Byte 13
OOH
3-18
Function Executed
Controller seeks the designated diagnostic track, performs a read ID and
verifies the track position. It then
writes and reads sector 0 with a
•
55AAH data pattern and verifies
that the data read matches the data
written.
OlH
02H to
FFH
Controller performs a ROM checksum test to verify the contents of
ROM.
Controller recalibrates the drive.
Any errors in the reading or writing are posted in the
error status registers.
•
To perform this function, set up the shaded bytes in
the I/O parameter block as shown in Figure ::3-20.
3-27. POSTING STATUS
When the controller has completed an operation
(read data, seek track, etc.), it posts the operation
status in byte 1, the OPERATION STATUS byte, of
the controller invocation block, using the following
procedure:
•
iSBC 215
•
Programming Information
1/0 Parameter Block
3
(Reserved)
o
(Reserved)
2
4
5
Actual Transfer Count
6
7
9
b~~¢e 4Gb
11
i
10
'>t
12
13
•. ·. ·....I
ii
•
Sector
8
14
Head
Data Buffer Offset
18
21
Data Buffer Segment
20
22
23
Requested Transfer Count
24
1.
3.
4.
•
27
General Address Pointer Offset
26
29
General Address Pointer Segment
28
3-28. TRANSFER ERROR STATUS
The Transfer Error Status function (FUNCTION =
OIH) transfers error status from the I2-byte error
status buffer in the controller memory to a data
buffer in the host system memory. The user can then
examine the status bits to determine the cause ofthe
error. Table 3-1 shows the information stored in each
byte of the error status buffer. Table 3-2 describes
which kind of errors are indicated by the setting of
the hard (unretrievable) error and soft (retrievable)
error bits in bytes 0 through 2. To perform the
Transfer Error Status function, set up the shaded
bytes in the 110 parameter block as shown in Figure
3-21.
Figure 3-20. Diagnostic
2.
•
16
19
25
•
It should be noted that error status information is
not cumulative. The error status buffers are cleared
at the beginning of each new command operation,
except the Transfer Error Status Command.
••••••••
Cylinder
15
17
I.· • i
recorded in the error status buffer in the controller
memory. To examine this error status the user
transfers the information in the error status buffer
from the controller to host system memory using the
transfer error status function (FUNCTION = OlH)
described in Paragraph 3-28.
The controller checks the STATUS SEMAPHORE byte (byte 3 of the controller invocation
block) for OOH.
If the STATUS SEMAPHORE byte is non-zero,
it indicates that the host CPU has not checked
the OPERATION STATUS byte for the last
status posted. When the host CPU does check
the operation status, it sets the STATUS SEMAPHORE byte to OOH and clears the interrupt.
1/0 Parameter Block
3
The status posted includes: operation complete, seek
complete, media change detected and errors detected.
If an error was detected, the unit on which the error
occurred and an indication of whether the error was
a hard error or a summary error is posted (see Figure
3-6). A more detailed description of the error is
o
(Reserved)
2
5
4
Actual Transfer Count
7
6
DeVice Code
8
10
When the controller reads OOH in the STATUS
SEMAPHORE byte, it posts the current status
in the OPERATING STATUS byte, sets the
STATUS SEMAPHORE byte back to non-zero
and sets an interrupt if enabled (see MODIFIER,
bytes 12 and 13, in Figure 3-7).
The host CPU in turn, either polls the STATUS
SEMAPHORE byte periodically for a non-zero
or is interrupted, indicating that new status is
present.
(Reserved)
12
Cylinder
14
Requested Transfer Count
24
25
27
General Address Pointer Offset
26
29
General Address Pointer Segment
28
Figure 3-21. Transfer Error Status
3-19
iSBC 215
Programming Information
Table 3-1. Error Status Buffer
Function
Byte
o and
1
2
3 and 4
5
6
7 and 8
HARD ERROR STATUS - See Table 3-2.
SOFT ERROR STATUS - See Table 3-2.
1.
Commands from the iSBC 215 controller ROM
based I/O program.
DESIRED CYLINDER
2.
User written I/O program.
•
DESIRED HEAD AND VOLUME
DESIRED SECTOR
ACTUAL CYLINDER AND FLAGS'
9
ACTUAL HEAD AND VOLUME
10
ACTUAL SECTOR
11
NUMBER OF RETRIES ATTEMPTED
'Flags located in bits 4 through 7 of byte 8.
3-29. INTERRUPTS
The controller normally posts interrupts to the host
on three conditions:
1.
Command complete
2.
3.
Seek complete
Media change (change disk pack)
The interrupt on command complete can be disabled
by entering a one in bit 0 of the Modifier word in the
I/O parameter block (bytes 12 and 13). The seek
complete and media change interrupts can not be
disabled. To clear an interrupt, the host writes a OOH
to the Wake·Up I/O port.
Pins on the controller board allow the interrupt
priority level of the controller to be set from 0 to 7.
Refer to the discussion of interrupt priority level
selection in Chapter 2.
3-30. CONTROLLING DATA TRANSFER
THROUGH THE iSBX™ BUS
Two iSBX connectors, J3 and J4, are provided on the
iSBC 215 board, which allow access to the controller's iSBX bus. The iSBX bus is an Intel standard
I/O interface (refer to the Intel iSBxr M Bus Specification, Manual Order No. 142686 for detailed information on this standard). It provides 16 data lines and
three address lines, providing a total of eight 16-bit
1/0 ports per connector. Using both J3 and J4, the
iSBC 215 controller can thus communicate through
the iSBX bus with up to 16 separate peripheral ports.
The iSBX 218 Flexible Disk Controller connects to
iSBX connector J4 and allows communication with
up to four flexible disk drives. In addition, users can
design I/O controller devices that interface with the
iSBX bus and use the 8089 to control data transfer.
3-20
Two methods are available to control the transfer of
data between the iSBC 215 controller and a device
connected to the iSBX interface:
The iSBX 218 Flexible Disk Controller uses the ROM
based I/O program to control data transfers to and
from the flexible disk drives, as described in
Paragraphs 3-5 through 3-29. The following paragraphs describe how data can be transferred between
the iSBC 215 controller and a user designed I/O
controller connected to the iSBX bus, using either
the ROM based I/O program or a user written I/O
program.
3-31. I/O TRANSFERS USING iSBC 215™
CONTROLLER RESIDENT FIRMWARE
As has been described at the beginning of this
chapter, the controller has a ROM based 110
transfer program that is designed to control Winchester drives through the on-board drive interface
or flexible disk drives through an iSBX 218 board,
which has been attached to iSBX connectors J4. The
iSBX TRANSFER command in this program can
also be used for general data transfer between the
host system memory and a user designed 110
controller, which has been connected to the iSBX
bus.
The iSBX TRANSFER command allows the transfer
of data between the host memory and the iSBX bus
in the same manner as with the WRITE DATA or
READ DATA commands. In this case, however, the
user must provide the necessary interface hardware
between the iSBX connector(s) and the I/O device
with which the controller is to communicate. This
interface can be very simple, involving data buffers
and limited handshaking capability, or as sophisticated as the disk drive interface circuitry used in the
iSBX 218 and iSBC 215 controllers. The complexity
of the interface will depend on the type of I/O device
being interfaced with and the desired data transfer
rate.
•
•
•
3-32. DATA TRANSFER USING USER
WRITTEN I/O TRANSFER PROGRAMS
A second method of initiating and controlling data
transfer between the host and the iSBX interface is
through a user designed program written in 8089
assembler code. This method is more difficult to
implement, but also more flexible. Such programs
can be executed either from host memory or from the
iSBC 215 controller on-board RAM.
•
Programming Information
iSBC 215
•
Table 3-2. Bit Functions in Hard and Soft Error Bytes
0
Function
Bit
Byte
o through
2
RAM ERROR -
Controller RAM error was detected.
4
5
ROM ERROR -
Controller ROM error was detected.
SEEK IN PROGRESS - Indicates a seek was already in progress for a unit when another
disk operation was requested.
ILLEGAL FORMAT TYPE - Both alternate track and defective alternate track flag set indicating an attempt to create an alternate track for a defective alternate track, which is not
allowed, or an attempt to access an unassigned alternate track.
END OF MEDIA - End of media was encountered before requested transfer count
expired.
6
7
1
•
2
•
•
•
Reserved for future use.
3
8
ILLEGAL SECTOR SIZE - Sector size read from the sector ID field conflicts with sector size
information that controller specified in initialization command.
9
DIAGNOSTIC FAULT -
A
NO INDEX -
Micro-diagnostic fault detected.
Controller did not detect index pulse.
B
INVALID COMMAND -
C
SECTOR NOT FOUND -
D
INVALID ADDRESS -
E
SELECTED UNIT NOT READY ing to unit connect request.
F
WRITE PROTECTION FAULT -
o through
2
Invalid function code detected.
Desired sector could not be located on selected track.
Invalid address was requested.
Selected unit is not ready, not connected, or not respondAn attempt has been made to write to a write protected unit.
Reserved for future use.
3
DATA FIELD ECC ERROR - Error has been detected in the data field of a sector. If bit 6
in Controller-Invocation status byte (byte 1) is set, error is hard and uncorrectable. If bit 6 is
not set, error is soft and correctable.
4
ID FIELD ECC ERROR - Error has been detected in the ID field of a sector. If bit 6 in
Controller-Invocation status byte (byte 1) is set, error is hard and uncorrectable. If bit 6 is
not set, error is soft and correctable.
5
DRIVE FAULT - Hardware fault detected in selected drive unit. Fault characterized by:
read/write fault, pOSitioner fault, power fault or speed fault.
6
CYLINDER ADDRESS MISCOMPARE the expected cylinder address.
7
SEEK ERROR -
ID field contains a cylinder address different from
Hardware seek error was detected
Executing the program from host memory is inherently slower than executing the program from onboard RAM, because it requires constant access of
the Multibus interface. This method, however,
allows the size of the program to be virtually
unlimited. The procedure for executing a program
from host memory is much the same as for executing
a program stored in controller local memory:
1.
I/O communications blocks are established in
host system memory.
2.
The Wake-Up Address switches in the controller
are set for the address of the first byte of the
wake-up block.
3.
The host initiates program execution with OlH
written to the wake-up I/O port.
There are two important differences in the set up of
the I/O communications blocks when executing I/O
programs from host system memory.
1.
Byte 0 of the channel control block must be set to
03H to indicate to the controller that the I/O
program is located in host memory.
2.
The controller invocation block becomes the I/O
parameter block. Refer to the 8086 Family User's
Manual, Manual Order No. 9800722 for detailed
information on setting up an I/O parameter
block when the I/O program is to be executed
from host system memory.
Executing the program from on-board RAM presents
space limitations, but allows data transfers to be
performed at the 8089's full program execution
speed. To overcome some of the limited RAM space
problems, the program can be divided into shorter
routines, which are stored in the host memory and
read into RAM as needed. Separate routines might
thus be written for disk formatting, checking status,
writing and reading. The iSBX EXECUTE com-
3-21
iSBC 215
Programming Information
mand, allows an I/O transfer routine or program
that is stored in iSBC 215 controller RAM to be
started from a host program. When writing an I/O
transfer program, the following software and
hardware considerations should be noted.
I/O PORT ADDRESSING
The eight iSBX bus ports reside in the controller's
memory mapped I/O space, with each I/O port
being given two addresses: one to connect it to
connector J3 and another for ,J4. Table 3-3 shows
these addresses. To access any of these ports for a
data transfer. the R089 merely executes a write or a
read to the address of the selected port.
Table 3-3. iSBXTM Bus I/O Port Addresses
Port
0
1
3
4
5
6
?
ISBX Bus Port Address Assignments
J4J3J3J4Channel 0 Channel 1 Channel 0 Channel 1
C070
C071
C073
C074
CO?5
CO?6
CO??
COBO
COB1
COB3
COB4
COB5
COB6
COB?
CODO
COD1
BOD3
COD4
COD5
COD6
COD?
COEO
COE1
COE3
COE4
COE5
COE6
COE?
PROGRAM STRUCTURE
In writing a program in 8089 assembly code, reference to the 8089 Assembler User's Guide, Manual
Order number 9800938 and the 8086 Family User's
Manual, Manual Order No. 9800722 is essential. The
8089 offers a number of techniques for implementing
handshaking between the 8089 and the iSBX bus,
including the user of wait states and DMA transfers
(essentially an interrupt driven mode) of whole
blocks of data. These and other interfacing techniques are discussed in this user's guide.
HARDWARE CONSIDERATIONS
There are two groups of interface control lines
between the 8089 and the iSBX bus. The first group
includes handshake and control lines; the second
group includes program lines.
Table 3-5 lists the first group of lines. The 8089 uses
these line~ directly to control data transfer through
the iSBX bus.
Table 3-5. 8089 Handshake and Control Lines
on the iSBXTM Bus
J3 or J4 Pin
RAM SPACE ALLOCATION
The controller RAM is used for a variety of purposes,
and as such. only a portion of it is available for
storage of an iSBX bus I/O program and its
parameters. The available RAM space is shown in
Table :3-4. Note that enough space has been reserved
in the data buffer to store an entire 1024 byte disk
sector of data. If the sectors are to be smaller or if for
some other reason less data buffer space is needed,
some of this space can be used for program storage.
Table 3-4. iSBC 2l5™ Controller RAM
A vail able for Program and Parameter Storage
Description
Address Range
Data Buffer'
4000 to 440F
Program Storage
4410 to 45FF
46CO to 4?3A
Scratch PAD'
4600 to 46BF
Variable Storage"
4?BO to 4?CF
4?EO to 4?FF
'May be modified by 215 command usage
"Not available if iSBX 218 is installed
3-22
•
Description
iSBX Bus
Mnemonic
34
Request DMA Transfer
MDRQT
32
Acknowledge DMA Transfer
MDACKI
16
Initiate Wait State
MWAITI
Multibus Clock
MCLK
6
15
I/O Read
10RDI
13
1/0 Write
10WRTI
26
Terminate DMA Activity
TDMA
The second group of lines are used for control and
status. The 8089 accesses these lines through a read
to memory mapped I/O address 8000H for connector
J3 and R008H for connector J4. Table 3-6 lists these
lines, their pin assignments and bit assignments.
Jumpers can be connected on the iSBC 215 controller
to allow the 8089 to also write bits onto the Option
lines (as shown in Table 3-7). The option lines on
only one of the interface connectors may be driven at
a time. To drive the lines, the 8089 writes to memory
mapped I/O port 80I8H. Bit 1 drives OPOO or OPOl,
but not both at onetime, bit 2 drives OPI0 and OPll,
but not both at one time. All other bit positions in
the data word must be set to zero when driving
the Option lines.
•
•
•
•
Programming Information
iSBC 215
•
Table 3-6. Control and Status Lines on the iSBXTM Interface
Connector 1
J3
Address
8000H
Connector 2
J4
OPOO
OP10
INTROO
Bit B
OP01
Bit C
Bit 9
INTR10
Bit A
OP11
INTR01
INTR11
MOPSTI
Bit 8
M1PSTI
Address
8008H
Pin
No.
Bit 3
Bit 4
30
28
14
12
Bit 1
Bit 2
Bit 0
ISBX Bus
Mnemonic
Description
Option 0
OPTO
Option 1
Interrupt 0
Interrupt 1
OPT1
MINTRO
MINTR1
MPSTI
iSBX Board Present
8
Table 3-7. Jumper Connections Allowing
Option Lines to be Driven
ISBX
Connector
Jumper Connection
OPOO
J3, OPO
W11, 1-2
OP11
J4,OPO
W11, 1-3
OP10
J3, OP1
W12, 1-2
OP11
J4, OP1
W12, 1-3
Line
•
I/O
PARAMETER
BLOCK
GA POINTER
NOTE
~
If an iSBX controller is not installed on the
•
iSBC 215 board, or if an iSBX controller that
has been installed on a particular iSBX connector does not drive its respective Terminate DMA Activity line, the connector's
corresponding jumper (W3 1-2 or W4 1-2)
must be installed.
I
I
ISBX INTERFACE
PROGRAM
OOC5H
I~
/
ROM
When loading and executing a user written I/O
transfer program or routine, the following procedure
is used:
1.
2.
•
RAM
I
PROGRAM EXECUTION
•
~
Load the program or routine into RAM using the
BUFFER I/O command from the iSBC 215
controller firmware.
Execute the iSBX EXECUTE command to start
the program. Note that the General Address
Pointer in the I/O parameter block for this
command must point to the address of the start
of the program in on-board RAM (see Figure
3-22). Also, upon entering the program, the
following 8089 registers are defined as:
GA: 7EOOH
Scratch Pad Stack
Unit Number
IX: 0 to 3
Exit from the program must always be to ROM
location 00C5H and the 8089 BC register must
be set to FFH and the 8089 GC register must be
set to 7F3BH.
Figure 3-22. Execution of iSBXTM Bus
1/0 Program From RAM
3-33. EXAMPLE CONTROLLER
I/O PROGRAM
Appendix A provides an example of a host processor
program to initiate data transfers between the host
system memory and disk drives through the iSBC
215 controller.
3-23
•
•
•
•
•
CHAPTER 4
PRINCIPLES OF OPERATION
•
4-1. INTRODUCTION
•
This chapter provides a functional description ofthe
iSBC 215 Winchester Disk Controller circuit operation. The discussion assumes that the reader has a
working knowledge of digital electronics and has
access to the individual component description of
each integrated circuit used on the board. As a
prerequisite, the reader should be familiar with the
programming conventions discussed in Chapter 3 of
this manual, and the functional operation of the
Intel 8089 I/O processor and the Multibus interface.
Familiarity with the disk drive's operation and
interface specifications will also prove beneficial in
understanding the controller operation.
4-2. SCHEMATIC INTERPRETATION
A set of schematic diagrams for the controller board
(Figure 5-3) and a component location diagram
(Figure 5-2) are included in Chapter 5 ofthis manual.
•
•
The schematics are drawn to standard drafting
conventions with input signals entering from the left
and output signals exiting to the right. Input and
output signals between individual sheets of a
schematic include a location coordinate code imme·
diately preceeding (input signals) or following
(output signals) the signal name. This code defines
the location of the origin or destination of the signal
ACTIVE INPUT
RELATIVE
HIGH
A
ACTIVE
OUTPUT
RELATIVE
---~LOW Y
ACTIVE INPUT
RELATIVE'
A
LOW
B
8
ACTIVE
OUTPUT
RELATIVE
HIGH
Y
within the schematic diagrams. The first digit of the
code is the schematic sheet number, and the last two
characters specify the zone defined by the horizontal
and vertical grid coordinates, which are printed
around the perimeter of each schematic sheet. For
example, the code "7B8" indicates that the origin or
destination of the associated signal appears on sheet
7 of the schematic set within the zone defined by grid
coordinates "B" and "8".
An "X" for one of the grid coordinates indicates an
entire vertical column or horizontal row on the
schematic sheet. For example, the code "7BX"
indicates the entire "B'" zone on sheet 7.
The logic symbols used in this manual are drawn as
specified in ANSI Standards 14.15 and Y32.14.
Standard definitions are used for symbols and active
line levels on inputs and outputs (see Figure 4-1). A
small circle on the input of a logic element indicates
that a relative low level is needed to activate the
element. The absence of a circle indicates that a
relative high level is needed to activate the element.
Output levels are indicated in the same manner.
Logic gating symbols are drawn according to their
circuit function rather than the manufacturer's
definition. For example, the gate, which the truth
table in Figure 4-1 defines, can be drawn in one of
the two configurations shown, depending on its circuit application.
B
Y
L H
L H
H H
ACTIVE INPUT
RELATIVE
LOW A
ACTIVE
OUTPUT
RELATIVE
HIGH
Y
ACTIVE INPUT
RELATIVE
HIGH A
ACTIVE
OUTPUT
RELATIVE
LOW
Y
BB
BE>
EXCLUSIVE
OR
•
Figure 4-1. Logic Conventions
4-1
Principles of Operation
iSBC 215
In addition to the inversion symbol convention,
signal nomenclature also follows an active state convention. When a signal (or level) is active in its low
state, the signal name is followed by a virgule or
"slash" (e.g., XACK/); when a signal is active in its
high state, the slash is omitted from the signal
name, (e.g., XACK). This convention corresponds to
putting a bar over a signal name to indicate it is
active in its low state (e.g., XACK).
4-3. FUNCTIONAL OVERVIEW
General. The function of the iSBC 215 Winchester
Disk Controller board is to allow the host system to
access any location on a specific disk of a selected
disk drive and either:
1.
Transfer data to that disk location from system
(host) memory (write operation), or
2.
Transfer data from that disk location to system
memory (read operation).
To accomplish this task, the controller circuitry is
divided into two sections (see Figure 4-2):
l.
Logic that controls communications and data
transfer between the host processor and the
controller through the Multibus interface, and
2.
Logic that controls data transfer between the
controller and the disk drive(s) through the disk
interface, and between the controller and the
iSBX bus through the iSBX bus interface.
The Intel 8089 I/O processor (lOP) controls the data
transfer process, using a program stored in on-board
ROM. It receives instructions from the host processor
through four I/O communications blocks in system
memory. Once the host instructs the controller to
begin a data transfer, the 8089's internal processor
makes a DMA transfer to or from system memory,
independent of the host processor.
2K bytes of RAM are included on the board for intermediate storage of data and to allow on-board error
checking. This data buffer allows DMA transfer to
be made between the controller and host system
memory, which minimizes Multibus™ overhead and
eliminates disk drive overruns.
Communicating with the host. Figure 4-3 provides a detailed block diagram of the controller. The
Bus Arbiter and the Bus Controller manage the
transfer of data between system memory and controller through the Multibus interface. The Bus
Arbiter negotiates with the current bus master for
control of the Multibus interface. The Bus Controller
generates control signals that gate data transfers
,-------------------------,
I
I
•
•
•
I
I
I
I
I
iSBC
MICROCOMPUTER
8089
lOP
I
I
iSBX BUS
INTERFACE
lOP
INTERFACE TO
MULTIBUS··
INTERFACE
LOCAL
BUS
INTERFACE
DISK
INTERFACE
ROM
SYSTEM
MEMORY
•
RAM
1/0 COMMUNICA-
TIONS BLOCKS
Figure 4-2. Simplified Block Diagram of iSBX 215™ Controller
4-2
•
1IIIC11.
r-I"
........
.
-
~
ATIII
ca .........
II
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-
t ....
-
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IT
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.
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•
r+
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•
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our.
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•
t
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Iti
t 1
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COIfI'ROL
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--
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ax:
32 BIT
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SIERIAl.
SERIAL IIIPUT DATA
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-
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CI
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AIJDIIIE!IIS
n
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•
.....c::+
SERIAL INIIIJT DATA
DISK
~
COIfI"HOL
~
LOGICJii
-'
I
DISI( CONTROl.
..
~
~
r---
CONTROL
RECENED
IXSK
14--
STATUS
AND
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-
~
CONTROL
DRIVERS
f4--
DIS«
~
r----
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TO
Ju r-----0tSIC
DRlYE
Figure 4-3. iSBC 215™ Controller Functional Block Diagram
4-3/4-4
Principles of Operation
iSBC 215
•
•
•
•
•
between system memory and the on-board RAM. It
also controls the transfer of data from RAM to the
disk communication circuitry.
The Multibus interface Address Latches transmit 20bit addresses to system memory via the Multibus
interface. The Multibus interface Data Transceiver
transmits data either to or from system memory via
the Multibus Interface. The controller data bus is 16bits. The Data Transceiver uses a byte-swap technique to allow data transfer with either an 8-bit or
16-bit system memory.
The Wake-Up Address Comparator is used to assign
the controller a host system 110 port address and to
set up a communications link between the 8089 lOP
and the 110 communications blocks in system
memory. (A detailed discussion of the controller
initialization procedure is given in Chapter 3 and in
Paragraphs 4-12 through 4-15 in this section.)
Communicating with the disk. The 8089 lOP
treats the ROM, RAM, iSBX 110 ports and disk
communications side of the controller circuitry as
local memory. The Local Address Latches transmit
16-bit addresses to local memory. The Local Data
Transceiver transmits data either to or from local
memory. Some of the addresses in local memory
provide access to local 110 ports (see Paragraph 4-20
for a detailed discussion of local 110 ports). The
Address Decoder decodes these addresses and
generates chip select or enable signals that control
the transfer of data to and from the disk. For
example, the address 8028H enables the 16-Bit Write
Buffer to receive a data word from the local memory.
The ROM and RAM are also assigned specific
ranges of addresses in local memory.
The 16-Bit SER/DES (SerializerlDeserializer) performs the serial-to-parallel and parallel-to-serial
conversion required to transfer data between the
disk and system memory. The I6-Bit Write Buffer
and the I6-Bit Read Buffer provide intermediate
storage for a single I6-bit parallel word between the
RAM and the SER/DES. On a write operation, a 16bit word is transferred from RAM to the write buffer.
The SER/DES then converts the word from parallel
to serial and transmits it to the disk through the
write data driver. On a read operation, a 16-bit serial
word is transmitted from the disk through the Read
Data Receivers to the SER/DES. The SER/DES
then performs a serial-to-parallel conversion and
stores the resulting parallel word in the read buffer.
The Write Data Driver and the Read Data Receivers
are designed to generate and read the differential
NRZ drive signals.
The 32-Bit ID Comparator determines when the
selected sector on the disk is found during the search
for sector ID operation that precedes a write or read
function. When a write or read is initiated, the 32-bit
sector identification (cylinder, head and sector
number) is loaded in the 32-Bit ID Comparator.
Sector IDs from the disk are then read and compared
with the selected sector ID. When the selected sector
is found, data transfer is initiated.
The 32-Bit ECC Generator creates an error checking
code (ECC) that is appended to the end of each sector
ID field and to each data field (see Figure 3-2). This
ECC is used for error checking and correction of data
errors. It allows all the errors in a burst of up to 11
bits to be corrected, and allows errors in a burst of 32
bits to be detected.
The Gap Control Logic controls the spacing of data
within a sector. Three programmable Counters,
which count disk clock pulses, provide timing for the
Gap Control Logic. The ability to program the
Counters allows the disk(s) to be formatted for a
number of different record sizes and gap lengths.
The Disk Control Logic transmits disk control
information to the disk drive units through the
Control Line Drivers. The Input Control Logic
receives status information from the disk drive units
and controls the sequencing of the controller read
and write operations.
The iSBX Interface provides the ability to connect
Intel iSBX Multimodule devices to the controller
board in order to control other 110 devices such as
flexible disk drives or magnetic tape cartridge
drives. The iSBX interface is discussed in more
detail in Paragraph 4-25.
A more detailed overview of the read and write
operations is given in Paragraph 4-29 through 4-33.
4-4. DETAILED FUNCTIONAL
DESCRIPTION
The detailed functional description of the iSBC 215
Winchester Disk Controller circuitry is divided into
two major sections: Controller to Host Communications and Controller to Disk Communications.
Within each of these sections, the following subjects
are discussed:
Controller to Host Communications:
•
Multibus™ Interface
•
•
•
•
8089 lOP
Bus Arbiter
Bus Controller
Multibus™ Data Transfer Logic
4-5
iSBC 215
Principles of Operation
•
Controller Initialization
•
Wake-Up Address Comparator
•
Controller Reset and Clear
•
Establishing a Link with I/O Communications
Blocks
•
Interrupt Priority
•
Memory Map
•
ROM
•
•
RAM
I/O Port Decode Logic
Controller to Disk Communications
•
Controller to Disk Drive Interface
•
DMA Mode
Disk Formatting
•
•
Write Data Transfer
•
Read Data Transfer
•
•
SERIDES Logie
•
•
•
32-Bit ID Comparator Logic
Status Register Logic
•
Line Drivers and Receivers
Sync Byte Comparator Logic
ECC Generator Logic
4-5. CONTROLLER TO HOST
COMMUNICATIONS
and mass storage devices such as disk drives. Its
ability to perform DMA data transfers independent
of the host processor allows it to carry out most
system memory-to-disk transfers of data simultaneously with other host processor operations. Refer to
The 8086 Family User's Manual, Manual Order
Number 9800722 for a detailed explanation of the
8089 and supporting IC devices.
A number of 8089 control lines have important functions in the controller design. The PWR-RST line
(4Dl), when pulled high, resets the 8089 to the
beginning of its internal firmware control program.
Channel Attention line CA (4B4) allows the host to
gain the attention of the 8089. On the first channel
attention following a reset, the 8089 fetches the
contents of address FFFF6H and begins an internal
initialization procedure. On subsequent channel
attentions, the 8089 looks to the I/O communications
blocks in system m~mory for further instructions.
Refer to Paragraphs 4-12 through 4-15 for a detailed
discussion of the controller initialization procedure
and the use of the CA line.
•
The Bus Interface Unit (BIU) in the 8089 controls
the controller local data bus cycles, transferring
instructions and data between the 8089 lOP and
external memory or the disk. Every bus access is
associated with a register tag bit that indicates to
the BIU whether the host system memory or local
memory is to be addressed. The BIU outputs the type
of bus cycle on status lines 80/, 81/ and 821. The
8288 Bus Controller decodes these lines and provides
signals that selectively enable one bus or the other.
•
The following discussion provides a detailed functional description of the section of the iSBC 215
Winchester Disk Controller that communicates with
the host through the Multibus interface.
The 8089 is a 16-bit processor, but it is capable of
making both single-byte fetches (8-bit system
memory) or two-byte fetches (l6-bit system memory).
The address zero line, lADR-O (5B7) .. controls the
byte swapping facility of the controller when
communicating with an 8-bit system memory.
4-6. MULTIBUS™ INTERFACE
4-8. CLOCK CIRCUIT
The 8089 lOP communicates with the host processor
and the system memory through the Multibus
interface. The Multibus interface signal description
and pin configurations are explained in Chapter 2. A
detailed description of the Multibus interface
operation can be found in the Intel Multibus™ Speci·
fication Manual Order Number 9800683.
The clock circuit consists of U55, an 8284A Clock/
Driver (4C6), and a 15 MHz crystal. The 8284A
dividE'S the crystal output by three to produce the 5
MHz CLK necessary to drive the 8089 lOP. The
8284A produces a reset signal mST), which is used
on power-up to reset the 8089, Interrupt Latch U56
(:m5) and the Read/Write Control logic. In addition
to the reset signal, the 8284A also produces a
synchronized ready (RDY) input to the 8089. A high
on the RDY line received from the addressed device
(XACK/ from external memory or the iSBX interface,
or RDY from the on-board read/write port), indicates
that the memory or read/write port has accepted
data during a write operation or data is ready to be
read during a read operation.
4-7. 8089 1/0 PROCESSOR (lOP)
The 8089 lOP, U84 (4X4), is a microprocessor device
that has been designed specifically to perform high
speed I/O transfers of data between system memory
4-6
•
•
•
Principles of Operation
iSBC 215
•
RDY 1
RDY
U55
RESET
RESET
FROM
WAKE-UP
LOGIC
(U39)
READY
,-----c
TRANSFER ACKNOWLEDGE
(XACK/)
RDY 2
AEN 1
AEN2
CLKI4
U90
BUS
CLK ARBITER
CHNL ATTN
•
=D--
EXT 1
AEN
SOl-52!
14
c:
1/0 READ of
1/0 WRITE
•
~
STB
/
/
U85/UB6
ADO-AD19
MWTC 0 - - - - _ MEMORY WRITE COMMAND
INTA
10RC
U91
10WC
OE
PDEN DT/R DENI3
UB1-U83
/20
14
T
/
U52-U53
MULTIBUS
ADDRESS
LINES
(ADR-OI - ADR-13/, BHEN/)
6.
V
T
OE
16
ADO-AD15
U96-U98
/16
/
14
MULTIBUS DATA LINES
(DAT-O - DAT-F)
14
Figure 4-4. Bus Arbiter and Bus Controller Logic
4-9. BUS ARBITER
•
CLK
/
1
~
MRDC. 0 - - - - _ MEMORY READ COMMAND
20
Is
16
50/-521
BUS
CONTROLLER
STB
16
OE
•
f3
ALE
~
LOCAL
DATA
IDAT-O-IDAT-F
AEN
SEL
ADO-AD19
LOCAL
ADDRESS
IADR-O - IADR-F
50/-521
BOB9
UB4
CHANNEL
SELECT
(RDC18)
END
TIME
EXT
TERM
.--
CLK
CA
MUL TlBUS
CONTROL
LOGIC
The 8289 Bus Arbiter, U90 (3D6). controls the 8089
lOP's access to the Multibus interface (see Figure 44). The 8289 monitors the 8089's status lines (SOl,
S1I and S2I). When the lines indicate that the 8089
needs a Multibus interface cycle, and the 8089 does
not presently control the bus, the 8289 activates a
bus request (BREQ/). The low on BREQI is transmitted to the bus priority resolving circuitry in the
host processor, which returns a low on Bus Priority
In line BPRN I, gIVmg the 8089 access to the
Multibus interface. Having received access to the
Multibus interface, the 8289 activates its busy signal
(BUSY I), indicating to the other masters on the
system that the Multibus interface is in use. The
8289 then activates the address enable signal
(AEN I), which is transmitted to the 8288 Bus
Controller, U91 (3C4), to enable its command
outputs, to the 8284A Clock Generator, U55 (4C6), to
enable its bus ready logic, and to the System
Address Latches, U8I, U82 and U83 (4X2), to allow
an address to be gated on to the Multibus interface.
4-7
iSBC 215
Principles of Operation
Jumper pins WI8-I, 2 and 3 allow the user to select
the Any Request option. A jumper installed between
pins WIS-l and 2 causes the controller to relinquish
control of the Multibus interface following a request
from a higher priority device only. A jumper
installed between pins WI8-1 and :3 causes the
controller to relinquish control of the Multibus
interface following a request from any device, higher
or lower priority.
4-10. BUS CONTROLLER LOGIC
The 8288 Bus Controller, U91 (3C4), decodes the
status line outputs (SO/, S1I and S2/) from the 8089
lOP and generates the appropriate bus cycle signal.
Table 4-1 shows the different signals generated for
each configuration of the lOP's status lines.
Table 4-1. 8089 Status Line Decodes
Status Input
521 51/
SOl
CPU Cycle
8288 Command
0
0
0
Instruction Fetch,
Local
INTAI
0
0
1
Read Memory,
Local
IORCI
0
1
0
Write Memory,
Local
IOWC/, AIOWCI
0
1
1
Halt
1
0
0
Instruction Fetch.
System
MRDCI
1
0
1
Read Memory,
System
MRDC/
1
1
0
Write Memory,
System
MWTCI, AMWC/
1
1
1
Passive
None
NOlle
These bus cycle signals can be divided into two
groups: those which allow the 8089 to access system
memory (MWTC/ and MRDC/) and those which
allow the 8089 to access local memory (l-AIOWC/
and I-IORC/). The 8089 uses the I/O Read (I-IORC/)
and I/O Write (I-AIOWC/) signals to read information from the local ROM, U87 and U88, (6X7), or to
read from or write to the local RAM, U99 through
UI02, (6X4). The 8089 also uses I-IORC/ and 1AIOWC/ to gate on the Read and Write Function
Decoders, U35 and U36 (5B2 and 5A2). The function
decoders are explained further in Paragraph 4-20.
The 8288 Bus Controller also generates a group of
signals that control address and data flow throughout the iSBC 215 controller. The Address Latch
Enable line (ALE) is used to strobe addresses from
the 8089 into both the system Address Latches, USlU83 (4X2), and the Local Address Latches, U85-U86
(5X7).
4-8
Data TransmitlReceive (DT /R), Data Enable (DEN),
and Peripheral Data Enable (PDEN/) control the
data flow through the controller. DT/R controls the
direction of data transmission through the Multibus
interface and local transceivers. If DT /R is high,
data is transmitted either on to the Multibus
interface through transceivers U96, U97 and U9S
(4X7) or on to the local bus through transceivers U52
and U53 (4X6). If DT IR is low, the data transfer is in
the opposite direction, into the 80S9 through one of
the two sets of transceivers. DEN and PDEN
controls the selection of the transceivers. If DEN is
high the Multibus interface transceivers U96, U97
and U98 are enabled, and if PDEN/ is low (indicating a peripheral cycle) local transceivers U52 and
U53 are enabled.
4-11. MULTIBUS™ INTERFACE DATA
TRANSFER LOGIC
The controller has three sets of Multibus interface
data transceivers: low-byte transceiver U97, which
buffers DAT-O/ through DAT-71, high-byte transceiver U96, which buffers DAT-8/ through DAT-F/,
and swap-byte transceiver U98, which takes the
data from DAT-O/ through DAT-71 on the Multibus
interface and switches it to high-byte data bus lines
AD8 through AD15 on the controller board (see
Figure 4-5). This byte-swap is performed only when
the controller is interfacing with a 16-bit system
memory in byte mode. In this case, every odd
address read from system memory is transmitted to
the high-byte data lines of the controller. The
procedure is reversed when writing to the 8-bit
system memory. Three signals control the transceiver: ENBL HI BYTE/ (5Cl), which controls the
high-byte transceiver; ENBL LO BYTE/ (5Cl),
which controls the low-byte transceiver (derived
from ADRO/); and ENBL SWAP BYTE/ (5CI),
which controls the swap byte transceiver. Figure 4-5
shows when each of the control signals is active.
•
•
•
•
4-12. CONTROLLER INITIALIZATION
Before data can be transferred between system
memory and the controller, the controller must be
initialized. The initialization procedure, which is
described in Paragraph 3-12, involves:
1.
Resetting the 8089 lOP.
2.
Clearing the reset.
3.
Establishing a communication link between the
8089 and the I/O communications blocks in
system memory.
4.
Reading the disk drive parameters from system
memory to the controller on-board RAM.
•
Principles of Operation
iSBC 215
•
HIGH
BYTE
"
MULTIBUS'·
INTERFACE
•
HIGH
BYTE
BUFFER
/8
LOW
BYTE
/8
8089
ADDRESS/
DATA BUS
ADOAD1S
SWAP
BYTE
BUFFER
/8
LOW
BYTE
BUFFER
-'"
•
,
8
LOW I
BYTE
iSBC 21S'" CONTROLLER
I-ADRO!
•
HIGH
BYTE \,
8
...
8-BIT
SYSTEM MEMORY
•
/8
L
I-ADRO!
ENBL LO BYTE!
L
H
ENBL SWAP BYTE!
H
L
ENBL HI BYTE!
H
H
16-BIT
SYSTEM MEMORY
H
I-ADRO!
,
L
I-ADRO!
H
L
,
H
,
L
'NOT APPLICABLE
Figure 4-5. Data Transmission Between Multibus™ Interface and Controller Data Transceivers
The following paragraphs describe the hardware
operations that take place during this initialization
procedure. (See Figure 4-6.)
4-13. WAKE-UP ADDRESS COMPARATOR
For the purpose of resetting the controller, clearing
the reset or getting the attention of the 8089 lOP
(raising CAl, the host addresses the controller as an
I/O port in its system I/O space. To perform one of
these functions it writes a one byte command to the
specified I/O port called the wake-up I/O port. Table
4-2 shows the three possible commands. The user
determines the address of the I/O port at which the
controller is to reside (called the "W ake-U p Address")
and sets the address on the Wake-Up Address
switches Sl-1 through Sl-8 and S2-3 through S2-1O
(2X6), on the controller board. When the host issues a
write command (lOWC/) to the Wake-Up Address in
system I/O space, U77 through UHO (2X5) on the
controller compare the address with the switch
settings. If they agree, WAKEUPI is pulled low,
enabling the controller to decode the command on
the Multibus interface data lines and determine the
action to be taken.
The host may use 8-bit or 16-bit I/O port addressing.
The user sets switch S2-2 (2A 7) to indicate to the controller the type of addressing that is being used.
When S2-2 is open (8-bit addressing), pin 9 of U75 is
held high, creating a "don't care" situation for the
outputs of High-Byte Wake-Up Address Comparators
U77 and U78.
Table 4-2. Host Wake-Up Commands
Command
OOH
Description
Clear Interrupt and Clear Reset
01H
Channel Attention (Start 8089 lOP)
02H
Reset 8089 lOP
As it is discussed in Chapter 3, the controller also
uses the setting of the Wake-Up Address switches to
calculate the address of the first byte of the Wake-U p
Block, which is the first I/O communications block
in system memory.
4-9
iSBC 215
Principles of Operation
WAKE-UP
ADDRESS
DAT-O-D~
MULTIBUS"
INTERFACE
DATA
TRANSCEIVER
AD-O - AD-15
V16
/
16
WAKE-UP
BUFFERS
/
SWITCHES
MULTIBUS'·
INTERFACE
WAKE-UP
/16
I--
U93 - U95
8089
U84
16-BIT
SYSTEM
BUS
CA
r----'
RESET
WAKE-UP
ADDRESS
- COMPARATOR
~____~CH~N=L~A~TT~N~____~
WAKE-UP
DECODER
U65
WAKE-UP 1/0 PORT
~~~~~~g~
WAKE-UP
ADDRESS TO
SYSTEM MEMORY
TO BEGIN
COMMUNICATION
r '- - - -:
8/16
BIT
S2-2
WAKE-UP
ADDRESS FROM HOST /16
ADR-OI - ADR-FI
/
•
/ 16
__D_A_T-_O/_a_"_d_D_AT_-_1/_--r/_1_6_ _~
RESET
CLEAR
RESET
RESET
LATCH
U63
CNTLR RST I
ADDRESS
•
OOH - CLEAR RESET
01H - INITIALIZE
02H - RESET 8089
Figure 4-6. Wake-Up Address Logic
4-14. CONTROLLER RESET AND CLEAR
The first operation that must be performed during
the initialization of the controller is a reset of the
8089 lOP. To reset the 8089, the host processor writes
an 02H to the wake-up address. The WAKE-UP/
line goes low and gates the 02H (DAT-9/ high and
DAT-II low) into the Wake-Up Decoder, U65 (3B7),
producing a low on the controller reset (CNTLR
RST /) line. A low on CNTLR RST / resets the 8089
(4X4), resets Read/Write Control Logic U42 (sheet 8)
and clears Control Register U3 (l2B5). Once the
controller has been reset, the host processor writes a
OOH (Clear Interrupt) to the wake-up address, which
clears the reset. The Wake-Up Decoder U65 decodes
the highs on DAT-O/ and DAT-II to raise CNTLR
RST/.
ATTN, which in turn raises the CA input to the 8089
lOP (4C4).
Being the first Channel Attention following reset,
the 8089 begins an internal initialization process.
The first step of this process is to do a fetch of
address FFFF6H. The address is transmitted on the
8089 Address/Data lines (ADO-ADI5) to latches U85
and U86 (5B7). Gates U66 and un through U76
(5D4) decode the output of these latches. The output
of U76 enables U89 (5D3), gating the status of the 16bit SYS BUS switch (S2-1) through Data Bit 0 line
(DAT-O/) to the 8089. Switch S2-1 on (16 Bit SYS
BUS/ low) indicates that the host memory system
supports 16-bit data transfers and S2-1 off indicates
8-bit data transfers. Inverter U89 also generates
Transfer Acknowledge (XACK/), which is sent to the
8089 (through the 8284A) indicating that the
operation has been completed.
•
•
4-15. ESTABLISHING A LINK WITH I/O
COMMUNICATIONS BLOCKS
Following a power-up event or a software reset (02H
written to the wake-up 110 port), the link between
the controller and the 110 communications blocks in
system memory must be established. To establish
this link, a clear reset (OOH) is written to the wake-up
110 port followed by a channel attention (01 H). The
OlH is gated into U65, producing a high on CHNL
4-10
After determining the width of the system bus (8-bit
or 16-bit) the 8089 fetches the addresses shown in
Figure 4-7 as part of the initialization sequence.
Fetching addresses FFFF8/9H gates zeros into the
8089. Fetching addresses FFFF A/BH causes the
GATE SWS/ line (RCI) to go low. GATE SWS/ gates
the settings of the wake-up address switches, Sl-1
•
iSBC 215
•
•
Principles of Operation
through Sl-8 and S2-3 through S2-1O through buffers
U93, U94 and U95 (2X3) and into the 8089. The 8089
multiplies the settings ofthe wake-up switch by 2\ to
determine the 20-bit address of the wake-up block,
the first 110 communications block in system
memory. The 8089 then uses this address to fetch the
wake-up block and establish a link with the I/O
communications blocks. On subsequent channel
attentions (host writes OlH to the wake-up I/O port),
the 8089 skips the wake-up block and goes directly to
the channel control block, the second I/O communications block. The 8089 uses the channel control
block to obtain the starting address ofthe controller's
ROM resident 1/0 transfer program (also called the
channel control program). From this point on, this
firmware program directs the controller activities.
One of the first operations of the firmware is to
again fetch the starting address of the wake-up
block. It then links its way through the channel
control block and the controller invocation block to
the I/O parameter block where it obtains instructions and parameters for a specific 110 operation.
•
8038H
8000H
47FFH
4000H
1FFFH
OOOOH
L..._ _ _ _ _ _ _ _ _ _ _ _ _- '
SHADED AREA
INDICATES UNUSED
ADDRESS SPACE
Figure 4-8. Local Memory Map
Figure 4-7. Address Fetches In Initialization
Sequence.
4-16. INTERRUPT PRIORITY LOGIC
4-19. RAM
Wire wrap pins W19-C and W19-0 through W19-7
(3B2) allow the user to select the interrupt priority of
the controller with respect to other peripherals in the
system. To issue an interrupt to the host, the 8089
lOP writes an OlOOH to local 110 port 80l0H. A high
on data line BDAT-8 and a low on write decoder line
WDClOI is then generated, causing interrupt latch
U56 (3B5) to pull its output high and pull the selected
interrupt line to the Multibus interface low. A OOH
written to the system I/O port wake-up address,
clears the interrupt (refer to Paragraph 4-14).
The controller RAM consists of four (lK x 4-bit)
RAM devices, U99 through Ul02 (6X4). On any read
or write to local memory in the range of 4000H to
47FFH, chip select decoder U65 (5B4) pulls RAM
chip-select line CSRAM/low, enabling the RAM
devices.
SYSTEM BUS
16-BIT
SYSTEM BUS
4-17. LOCAL MEMORY MAP
•
COOOH
The controller ROM, which contains the 8089 lOP's
disk control program, consists of two (4K x 8-bit)
ROM devices, U87 and U88 (6X7). On any read from
local memory in the range of OOOOH to lFFFH, chip
select decoder U65 (5B4) decodes address lines
IADR-E and IADR-F and pulls ROM chip-select line
CSROMI low, enabling the ROM devices.
8-BIT
•
~
C01EH
4-18. ROM
FFFF6
FFFF8J
FFFF9
FFFFA
FFFFB
FFFFH
As was discussed in the Functional Overview, the
8089 IOP addresses the ROM, RAM, iSBX I/O ports
and the disk communications side of the controller
circuitry as local memory. Figure 4-8 shows a map of
this local memory. The following paragraphs
discuss the ROM, RAM and 110 ports.
4-20. LOCAL MEMORY MAPPED 1/0
PORTS AND iSBX™ 1/0 PORTS
The 8089 lOP views the controlling devices in the
disk control circuitry (such as ID comparators,
counters, write buffer, read buffer, etc.) and theiSBX
bus ports as local 110 ports, each with an address in
local memory space. To enable one of the disk
control devices, the 8089 executes a read or a write to
the devices respective address. On any read or write
to local memory in the range 8000H through 8038H,
chip select decoder U65 (5B4) pulls its pin 10 low.
4-11
iSBC 215
Principles of Operation
Table 4-3. Local I/O Ports
Read (U33 Enabled)
Address
Write (U32 Enabled)
Enable Line
Function
Enable Line
Function
ROCOOI
Read Disk Status
WDCOOI
Write control data to disk drive and enable AM SEARCH/, RDGATE and WRT
GATE.
8008H
WDC081
Clear index and I D not compare latches
8010H
WDC101
Write to disk control register.
8000H
8018H
RDC181
Raise 8089 Ch 2 CA input.
WDC181
Write to Unit Select and Control register
8020H
RDC201
Read contents of counter 2
WDC201
Load counter 0
8022H
RDC201
Read contents of counter 1
WDC201
Load counter 1
8024H
RDC201
Read contents of counter 2
WDC201
Load counter 2
WDC201
Write mode word
8026H
Read contents of read buffer
WDC281
Write data to write buffer
8030H
WDC301
Write sector ID to high comparator,
start track format operation.
8038H
WDC381
Write sector I D to low comparator
8028H
RDC281
When this low on pin 10 ofU65 is accompanied by a
low on I/O read line I-IORC/, read I/O port address
decoder U36 (5B2) is enabled; when the low on pin 10
of U65 is accompanied by a low on I/O write line 1AIOWC/, write I/O port address decoder U35 (5A2)
is enabled, When enabled, U35 or U36 decode local
memory address lines IADR-3 through IADR-5 to
select the desired disk control device. Table 4-3
shows the address of each local I/O port and its
function.
The two iSBX bus connectors, J3 and J4, on the
iSBC 215 board provide access to the controller's
iSBX bus. The iSBX bus provides 16 data lines and
three address lines, providing a total of sixteen 16-bit
I/O ports per connector. Each of these I/O ports has
an address in local memory space (see Table 4-4).
4-21. CONTROLLER TO DISK DRIVE
COMMUNICATIONS
The following discussion provides a detailed functional description of the section of the iSBC 215
controller that communicates with the disk drive
through the Winchester drive interface, and a
description of the controllers interface with the iSBX
bus through iSBX connectors, J3 and J 4. The
discussion is broken into four areas: (1) description
of the disk interface and iSBX bus signals; (2)
explanation of how the controller formats a disk
prior to performing the read and write functions; (3)
explanation of how writes and reads are performed;
and (4) descriptions of the various circuits that
perform the data transfer.
Table 4-4. iSBXTM Bus I/O Port Addresses
Port
ISBX Bus Port Address Assignments
J3-
J3-
J4-
J4-
Channel 0
Channel 1
Channel 0
Channel 1
CODO
COD1
COEO
BOD3
COE3
0
1
C070
COBO
C071
3
C073
COB1
COB3
4
C074
COB4
COD4
COE4
S
6
7
C07S
COBS
COB6
COB7
CODS
COD6
COD7
COES
COE6
COE7
C076
C077
COE1
When the 8089 executes a read or a write to one of
these ports, chip select decoder U65-9 (5B4) activates
the CSMMIO/ line. Gates U30 (l3C3) and inverter
U3l (13C4) decode the CSMMIO/ and IADR-4 lines
to select either J3 or J4. Address lines IADR-1,
IADR-2 and IADR-3 are transmitted to connectors
J3 and J4, pins 11, 9 and 7, respectively (5Cl), to
select the I/O port on the selected connector.
4-12
4-22. CONTROLLER TO WINCHESTER
DISK DRIVE INTERFACE
All the signals that are transmitted between the
controller board and the 8" Winchester disk drives
are transmitted through either the Control Cable
(J1) or the Read/Write Cable (J2). The physical
configuration of these cables is described and
illustrated in Chapter 2. All the signals transmitted
between the drives except for the read, write and
clock signals are TTL level. The read, write and
clock signals are transmitted as differential signals.
The interface signals that the controller supports are
described in the following paragraphs. Each of the
drive manufacturers, Shugart/Quantum, Memorex,
Priam and Pertec, use the available lines differently.
For the specific use of the lines being employed,
consult Figure 2-3 through 2-6 and the drive manufacturer's user manual.
•
•
•
•
•
Principles of Operation
iSBC 215
•
4-23. CONTROL CABLE SIGNALS
1.
Control and status information is exchanged between the controller and the drive through the
Control Cable. Output signals are defined as those
signals that the controller transmits and input
signals as those the controller receives. The Control
Cable is connected to J1 on the iSBC 215 board and
goes to the first drive and up to three subsequent
drives in a daisy chain fashion as shown in Figure
2-7. The functions of the 37 Control Cable lines can be
divided into five categories:
2.
3.
4.
5.
Device Select (Output)
Head Select (Output)
General Purpose Data Bus (Bidirectional
Priam and Pertec Only)
Control (Output)
Status (Input)
Table 4-5 describes the function of each of the lines
transmitted through the Control Cable.
Table 4-5. Control Cable Line Functions
Line Name
•
Function
Description
DEVICE SELECT
USO/-US3/
Unit Select
Four lines; each selects one of four disk drive units.
HSO/-HS3/
Head Select
Four binary coded lines select one of sixteen heads in selected drive.
BUSO/-BUS7/
Data Bus
WRGATE/
Write Select
Enables the write circuitry in drive, permitting write data that is sent to the drive
through the Read/Write cable to be written on the selected disk surface. Used
with AD MK EN/ line to write address mark on soft sectored disk.
RDGATE/
Read Select
Enables the read circuitry in drive, permitting data to be read from the selected
sector of the disk. Used with AD MK EN/ to read address mark from soft sectored
disk.
DIR/
Direction
Controls direction in which head is moved (Low
head positioner.
STEP/
Step Head
Initiates movement of head in direction that DIR/ has specified.
COMMAND/
Command Data
Indicates command data is present; used in bus cycle handshaking.
PARAMETER/
Parameter Data
Indicates parameter data is present; used in bus cycle handshaking.
DRIVE REQ/
Status Data
Indicates status data is present; used in bus cycle handshaking.
BUS ACK/
Bus
Acknowledge
Acknowledges a bus cycle; used in bus cycle handshaking with commands,
parameters and status.
AD MK EN/
Address Mark
Enable
Enables writing or detecting of address marks (beginning of sectors) when used
in conjunction with WRGATE/ and RDGATE/, respectively. Refer to SECTOR/
under status data.
FL T CLR/
Fault Clear
Clears FAUL T/ line in selected drive. Signal has no effect if fault condition has
not been corrected.
SAFE/
Controller
Power Condition
Indicates to drive that power condition of controller is safe.
BAO/ and BA1/
Bus Address
Two binary coded lines specify source or destination register in selected drive
for bus data.
INDEX/
Index
Pulse received from selected disk drive once every disk revolution.
SECTOR/
Beginning of
Sector
Signal indicates beginning of a sector: address mark for soft sectored disks,
sector pulse for hard sectored disks.
FAULT/
Fault Condition
Indicates to controller that an unsafe condition has been detected in the selected
drive, which would make the reliability of read/write operation questionable.
Normally, logic in drive disables the read, write and positioning circuitry until
rezero operation, fault clear or operator intervention occurs.
HEAD SELECT
GENERAL PURPOSE DATA BUS (Priam and Pertec Onld
Eight-bit, bi-directional data bus transmits command and status information
between controller and drives. Data transmitted includes head and cylinder data.
COMMAND DATA
•
•
= in.
High = out) when stepping
STATUS DATA
•
ILL ADR/
Illegal Add ress
Indicates drive has received an illegal cylinder address.
SK COM/
Seek Complete
Indicates to controller that selected drive has successfully completed the initial
head load, seek operation, or rezero operation within drive specified time limits.
READY/
Drive Ready
Indicates that drive is powered up and is ready to receive or transmit data.
4-13
iSBC 215
Principles of Operation
Table 4-5. Control Cable Line Functions (Continued)
Line Name
Function
Description
STATUS DATA (Continued)
WR PRO!
Write Protected
I ndicates that the selected drive is set for write protected operation. Controller is
then inhibited from writing to the drive.
TRACK 01
Track Zero
Indicates that heads of selected drive have been positioned to cylinder (track)
zero.
4-24. READ/WRITE CABLE
SIGNALS
4-25. CONTROLLER TO iSBX™
CONNECTOR INTERFACE
Read Data, Write Data, Clocks, and two status lines
constitute the information exchanged over the
Read/Write cables. Output signals are defined as
those signals that the controller transmits to the
disk drives, and input signals those that the
controller receives. For the Memorex or 14" Shugart
drives, the Read/Write cables are connected from the
controller to the disk drive in radial fashion, that is
one cable from the controller to each of the drives. J2
provides read, write and clock signals for two drives,
for example, l:{DO (t and -) and RD1 (t and -). One of
these signals goes to physical address 0 and the
other to physical address 1. When using 8" Shugart,
Quantum, Priam or Pertec drives, only the signals
associated with physical address 0 are used. These
signals are then daisy chained between drive units
allowing the controller to communicate with up to
four drives. Chapter 1 describes the cabling requirements for the various drive manufacturers. The
physical configuration of these cables is explained
and illustrated in Chapter 2. Table 4-6 describes the
function of each of the lines transmitted through the
Read/Write Cables. Note that the read. write and
clock signals are differential signals, requiring two
lines in the cable; the status lines are TTL level
signals.
All the signal and control lines transmitted between
the controller and the iSBX bus are transmitted both
through connectors J3 and J 4. These lines are
discussed only in general in this manual as they
pertain to the remainder of the discussion of the
controller interface with the Winchester drives. For a
more detailed discussion of these lines refer to the
Intel iSB)(fM Bus Specification, Manual Order No.
142686.
It should be noted that the controller does not support any parallel-to-serial or serial-to-parallel conversion of data for transmission through the iSBX
connectors. It interfaces with any device connected
to these connectors through an 8 or 16-bit parallel
bus and a number of control and handshake lines.
The interface thus resembles the read/write port,
made up of the write buffer and the read buffer, that
is used in the controller interface to the Winchester
drives.
The names in the schematic diagrams for the signal
and control lines from the iSBC 215 Controller that
are connected to iSBX connectors J3 and J4 often
differ from the respective line name from the iSBX
bus specifications. Table 4-7 lists both the iSBX bus
mnemonic and the controller line name for each line
in the iSBX bus that the controller supports.
Table 4-6. Read/Write Cable Line Functions
Line Name
Function
Description
WRO and WR1
(+ and -)
Write Data
Write Data line pairs transmit serial NRZ data from the controller to the drive for
recording on the disk surface. Write Clock synchronizes data transfer.
WRClO and
WRCl1
(+ and -)
Write Clock
Write Clock line pairs transmit clock signal to drive that is used to synchronize
write data transmission. Write Clock is derived from Read Clock, which the controller receives from the selected drive. Since the Read Clock is obtained from
the rotating disk. it reflects any speed variations and thus ellsures the proper bit
rate transmission when writing as well as when reading.
ROO and RD1
(+ and -)
Read Data
Read Data line pairs transmit serial NRZ data from the disk drive to the controller.
The controller converts the differential signal into TTL levels for transmission to
the host memory. The Read Clock synchronizes Read Data transfer.
RDClO and
RDCl1
(+ and -)
Read Clock
Read Clock line pairs transmit clock signal to controller that is used to synchronize read data transmission and as a timing signal for the controller disk interface
circuitry. Read Clock is derived from rotating disk.
SECTO! and
SECT1!
Beginning of
Sector
Same as SECTORI signal transmitted to controller through Control Cable, one
signal from each physical address.
SKCOMO! and
SKCOM11
Seek Complete
Same as SKCOM! signal transmitted to controller through Control Cable, one
signal for each physical address
RD WR CURl
Reduced Write
Current
Output Signal used to control the write electronics for the inner tracks with higher
bit densities.
4-14
•
•
•
•
•
Principles of Operation
iSBC 215
•
•
•
•
•
Table 4-7. iSBXTM Bus Mnemonic-to-Controller Line Name
Pin
iSBX Bus
Mnemonic
J4
J3
Pin
iSBX Bus
Mnemonic
J3
J4
43
MD8
IDAT-8
IDAT-8
44
MD9
IDAT-9
IDAT-9
41
MDA
IDAT-A
IDAT-A
42
MOB
IDAT-B
IDAT-B
39
MDC
IDAT-C
IDAT-C
40
MOD
IDAT-D
IDAT-D
37
MOE
IDAT-E
IDAT-E
38
MDF
IDAT-F
IDAT-F
35
GND
GND
GND
36
+5V
+5V
+5V
33
MOO
IDAT-O
IDAT-O
34
MDRQT
DREQO
DREQ1
31
MD1
IDI\T-1
IDAT-1
32
MDACKI
N/C
N/C
29
MD2
IDAT-2
IDAT-2
30
OPTO
OPOO
OP01
27
MD3
IDAT-3
IDAT-3
28
OPT1
OP10
OP11
25
MD4
IDAT-4
IDAT-4
26
TDMA
EXTRO
EXTR1
23
MD5
IDAT-5
IDAT-5
24
21
MD6
IDAT-6
IDAT-6
22
MCSOI
CSMMIOOI
CSMMI021
19
MD7
IDAT-7
IDAT-7
20
MCS11
CSMMI011
CSMMI031
17
GND
GND
GND
18
+5V
+5V
+5V
15
IORDI
I-IORCI
I-IORCI
16
MWAITI
MWAITOI
MWAIT11
13
IOWRTI
I-AIOWCI
I-AIOWCI
14
MINTRO
INTROO
INTR01
11
MAO
IADR-O
IADR-O
12
MINTR1
INTR10
INTR11
9
MA1
IADR-1
IADR-1
10
7
MA2
IADR-2
IADR-2
8
MPSTI
MOPSTI
M1PSTI
5
RESET
PWR RST
PWR RST
6
MCLK
CCLK
CCLK
3
GND
GND
GND
4
+5V
+5V
+5V
1
+12V
+1:2V
+12V
2
-12V
-12V
-12V
All undefined pins are reserved for future use.
4-26. CONTROLLER TO DISK DRIVE
INTERFACE TIMING
The following paragraphs provide a detailed discussion of the inter-circuit timing that occurs when
formatting a disk, writing to a disk or reading from a
disk. The discussion is provided to describe the interaction of the timing logic shown on Sheet 8 of the
Schematic Diagram, with the disk drive interface
receivers and drives shown on sheets 9 through 12
and the other data transfer circuitry described in
Paragraphs 4-31 through 4-36.
4-27. DMA MODE
In general, when the controller is performing a read
or a write function it locates the area of the disk
where the read or write is to be performed, then
enters its DMA mode to perform the actual transfer.
(The process oflocating the area to be read or written
to is discussed in the following paragraphs.) In the
DMA mode, the 8089 IOP (see Figure 4-2) controls
the transfer of data between the local RAM block
and the write and read buffers (called the read/write
port). The data transfer circuitry on the controller
board controls the transfer of data between the read/
write port and the disk.
The RDY (Ready) line (8D1) is used for hand shaking
between the 8089 and the data transfer circuitry.
When RDY is low, the HOR9 is quiescent; when RDY
is high, the 80R9 performs a DMA transfer of data
either from local RAM to the write buffer (block-toport) or from the read buffer to local RAM (port-toblock). Gates U40, U41 and U12 (8D3) control the
RDY line.
To perform a write or a read, the 8089 executes firmware to set up data (write only) and condition the
hardware for the selected operation. It then enters
the DMA mode and attempts to transfer data. At
this time: the TIME OUT line (8D8) is low; the
MWAIT/ line is high; the R/W GATE line (RDl) is
high (see Figure 4-9); U21-R (8D3) is high, held so by
the low on the ENBL XFER line (8Dl); and the
R/WDC 28 line, the output of Ull-ll (8D7), is low.
The low on R/WDC 28 is thus keeping RDY activated. On this first attempt to transfer data in the
DMA mode, the 8089 activates either RDC 28/ or
WDC 28/ (RD8), depending on whether a read or a
write is being performed, respectively (refer to
Paragraph 4-31). When RDC 28/ or WDC28/ is
activated, the R/WDC 28 lines is activated, lowering
RDY and putting the 8089 into its quiescent (wait)
state. When the controller's data transfer circuitry
has found the area on the disk where the read or
write is to begin, it activates ENBL XFER (8Dl). On
4-15
iSBC 215
Principles of Operation
the next occurance of a Bit Ring-O pulse, BRO (8D1),
following the activation of ENBL XFER, U21-8
(8D3) is activated, activating RDY. The 8089 then
immediately performs the data transfer (writes a
word into the write buffer or reads a word from the
read buffer) and lowers R/WDC 28. On the next
clock into U21-11; U21-8 is raised. On the 8089's next
attempt to perform a data transfer, R/WDC 28 is
also raised, lowering RDY. The data transfer does
not occur and the 8089 goes into its wait state.
During this time, the SER/DES either transfers the
word from the write buffer to the disk or reads
another word from the disk into the read buffer.
Then on the next BR-O pulse, RDY is again activated
and the next DMA data transfer occurs. The 8089
continues in this DMA mode until the R/W GATE
line is lowered.
Note that two other lines have potential control over
the RDY line. The TIME OUT line (8D8) is provided
to allow the 8089 to be activated if a sector cannot be
found on a cylinder. While the drive is searching for
a sector, the RDY line is held low. If after two
revolutions, the drive does not locate a sync byte, the
time out line is raised. U41 (8D3) gates the TIME
OUT signal through to U12 (8D1) and activates
RDY.
The MWAITI line (8D8) is an iSBX Interface control
line, derived from MWAITOI and MWAITlI (13D8).
MWAITI exercises the same control over the RDY
line as U40 (8D3) and can thus be used to set up a
handshaking arrangement between an I/O controller connected to one of the iSBX interface connectors
(J3 or J4) and the 8089. Refer to the discussion ofthe
8089 in the 8086 Family User's Manual for a more
detailed explanation of the various uses of the 8089
wait states.
4-28. DISK FORMATTING
Before the surfaces of a disk can be used for the
writing and reading of data, the disk must be
formatted. Formatting is the operation of writing all
the address fields, gaps, ID headers, etc. for the
complete disk. The controller performs this operation
under software control. The software routine that
controls this disk formatting operation allows only a
single track to be formatted for each Format
command. The host thus issues a new Format
command to the controller board for each track to be
formatted until the formatting of the entire disk is
complete.
The implementation of the Format command is
divided into two operations. During the first operation, address marks (soft sectored disks only), gaps
and ID fields are written during a single disk
revolution. During the second operation, data fields
BR-O
(SOl)
U21-S ----~
(S03)
•
•
•
r---;---'
•
Ull-ll~
RIWOC 2S
(S07)
ROY
(SOl)
R/W GATE
(SOl)
ENBL XFER
(801)
CTR11
I
J~
-------J)
Figure 4-9. Timing Diagram for RDY Signal
4-16
•
iSBC 215
•
•
•
are written (using the write data sequence described
in Paragraph 4-31) with user supplied data. The
second operation requires two disk revolutions, one
to write the odd physical data fields (1, 3, 5, ... ) and
one to write the even physical data fields (0, 2, 4, ... ).
Three disk revolutions are thus required to format a
single track. The hardware execution portion of the
format operation is discussed in the following
paragraphs. This discussion pertains to the formatting of a soft sectored disk. The iSBC 215 controller
supports both soft and hard sectored disks. I The
formatting procedure, however, is essentially the
same. The differences are described at the end ofthis
section, along with the slight differences in the
sector format used with the Shugart/Quantum
drives. When the Format command is issued to the
controller, the 8089 lOP performs a seek to the
desired track (cylinder) to begin the format operation.
When the heads are positioned over the selected
track, the 8089 writes a COH (for unit 0), a C8H (for
unit 1), a DOH (for unit 2) and a D8H (for unit 3) to
110 port 8018 (decoded as WDC 18/). The activation
of WDC181 enables U3 (12A5) and activates the
WRT GAT-F and FORMAT lines (12Bl) and WRT
GATE (12Cl) (see Figure 4-10). WRT GAT-F and
FORMAT enable the controller format control
circuitry. The controller then writes all zeros to the
drive while the 8089 waits for the receipt of the first
INDEXI pulse (11D8).
'A soft sectored disk (as used in Shugart/Quantum
and Pertec drives) requires an address mark to be
written at the beginning of each sector during the
formatting operation. Hard sectored disks (as used
in Memorex and Priam drives) provide a sector pulse
at the beginning of each sector, thus address marks
do not need to be written.
The time that the 8089 allows between the detecting
of Index and the activating of U63 (8B7) is approximately 11 byte times, which is the time the controller
requires to perform a number of firmware steps in
preparation for writing the first address mark and
ID field, (see Figure 3-2 for a pictorial representation
of the track format). During this time, the 8089
WRT GATE-F
•
Principles of Operation
The receipt of INDEX I sets latch U34 (lID6), which
in turn sets bit F of the Status Register, U44 (lID5).
To monitor the Status Register, the 8089 polls (reads)
1/0 port 8000H bit F (decoded as RDC 00/). Upon
detecting Index, the 8089 writes a XXXXH to I/O
port 3030H (decoded as WDC 30), which triggers U63
(8B7), activating the WRT AMI line (8Bl) and
causing the first address mark to be written on the
disk through the ADMKENI line (12Dl).
--...J"'~--------------------------------~?~
(
FORMAT--...J'
(
,
INDEXI
WRT GATE
WDC 301
WRT AMI
CTR 01
CTR 11
CTR 21
WRT XFERI
ECC TIMEI
END TIME
•
Figure 4-10. Timing Diagram for Disk Formatting Sequence
4-17
Principles of Operation
writes the sync byte (0019H) to the write buffer, U46
and U49 (7C7 and 7D7), by writing to I/O port 8028H
(decoded as WDC 28/). It performs this operation in
preparation for writing the ID field on the track.
The activation of WRT AMI also starts counter I,
CTR 1 of U69 (8A 7). (The 8089 preset the counters in
U69 at the beginning of the format operation.) When
CTR 1 times out at the end of 11 byte times, it
activates the WRT XFERI line through U63-7 (8C3),
and starts CTR 2. The activation of WRT XFERI
initiates the 8089's DMA mode (as discussed in
Paragraph 4-27), during which time the sync byte
and the sector ID are written onto the disk. CTR 2
times out at the end of the ID field, starting CTR 0
and activating the ECC TIME line (8Bl). During the
ECC TIME, the ECC code from the ECC generator is
written following the ID field (refer to Paragraph 4-34
for a description of the operation of the ECC generator). At the end of ECC TIME, the END TIME line is
enabled, which lowers the WRT XFERI line and
takes the 8089 out of the DMA mode. After the last
ID field is written, the FORMAT line is deactivated,
which inhibits the writing of any additional address
marks.
CTR 0 is set for a time equal to the ECC+G3+DATA+
G4. which the 8089 sets according to the sector size
selected for the drive. When CTR 0 times out. it
activates WRT AMI and CTR 1, which begins the
formatting of the second sector. This procedure is
repeated until the 8089 determines that the last ID
field has been formatted. The 8089 then begins
searching for the Index pulse. Upon receipt ofIndex,
the RST FRMT I line is activated, resetting WRITE
GATE-F and FORMAT, and inhibiting the writing
of the next address mark. The 8089 then continues
through the Format routine to the second operation,
which is the writing of the data fields with user
supplied data. The write data function, discussed in
Paragraphs 4-29, describes the write data operation.
For hard sectored disks, a jumper is connected
between terminals WIG 1-3 (8B8). The formatting of
the first sector thus begins when the first SECTORI
pulse from the disk following the INDEXI is
received, rather than when WDC :301 is activated.
When the SECTORI line (llB8) is activated, it
activates the INDEX-SECTORI line (11Cl), which
starts CTR 1. Formatting then continues in the same
manner as with soft sectored disks, except that the
beginning of the next sector occurs at the receipt of
the next SECTORI pulse rather than at the timing
out of CTR O.
The 8" Shugart/Quantum drive seetor format differs
in two ways from that ofthe other three drive types.
In the 8" Shugart/Quantum drives, an address mark
is placed before both the In field and the data field,
4-18
iSBC 215
with no gap between the address mark and the sync
byte. In addition, a D9H is used for the sync byte in
the data field rather than a 19H. When the controller
sync byte detector circuit, U54, U68 and U73 (7B5),
detects a sync byte (19 or D9) following an address
mark and, the SR-6 (7Bl) line is activated, (D9 only
detected), the DATA SYNC and IDNCMPRL lines
are activated through latch U37 (9A6). DATA SYNC
and IDNCMPRL then set bits 3 and 6, respectively,
of status register UI0 (lIC5) indicating to the
controller the presence of the data field instead of an
ID field. In the Memorex, 14" Shugart, Pertec and
Priam drives, a data field is assumed to follow an ID
field without an intervening address mark.
A second difference between the 8" Shugart!
Quantum drive and the other three drives is that
with the 8" Shugart/Quantum drives, a 4EH pattern
is written in the gaps rather than zeros. Inverters
U58 and U17 (8D6) and gates U19 (8D5) creates the
4EH pattern. U40 and U60 (8A3) gate the pattern
through to the SER/DES when the SHUGART and
WRT GAT-F lines are activated during a format.
•
•
4-29. WRITE DATA TRANSFER
The write operation is divided into two steps: (1) read
sector ID and (2) write data. When a write is
initiated, the 8089 lOP writes 0006H to I/O port
8000H (decoded as WDCOO). Latch U24 (l2C5) then:
activates the AM SEARCH/, ADMKENI and RD
GATEI lines, which enables the drive to search for
the address mark and enables the controllers read
circuitry (see Figure 4-11).
The 8089 has previously written to I/O port 8020H
(decoded as WDC20/) to load counters 0, 1 and 2 of
U69 (8A 7). It also writes to I/O ports 8030H and
8038H (decoded as WDC301 and WDC38/), loading
the TD of the sector to be written to, into the ;32-bit ID
comparator logic.
When the address mark (or sector pulse) is detected,
SECTORI is acti vated, which activates the AMFNDSECTORI line (lIB 1). The low on AMFNDSECTORI resets U34 (8C7) and deactivates the ID
FIELD line. The low on the ID FIELD line, deactivates the AMMKENI line and activates the ALW
SYNC SRCH, initiating the search for the sync byte.
(Note that with the Shugart drives, the sync byte
follows the address mark directly. The activating of
AM FND-SECTORI thus activates ALW SYNC
SRCH directly through jumper W14 1-2 (12C3).)
In searching for the sync byte, serial data from the
disk is read into the SERDES. Sync byte comparator
U73 and U54 (7B5) monitors the outputs of the SERDES and pulls the SYNC BYTEI line (7B1) low
•
•
•
Principles of Operation
iSBC 215
•
I~I
AM ENABLE
RD(BC8)
GATE
J~L..
I~I
DATA
DATA
___________"'"
r-----------------..,
,H\._ _ _ _ _ _ _ _ __
---.Jrf
AM FND·SECTORI - - - . . . ,
(8B8)
SYNC FNDI - - - - - - - ,
(9Cl)
~_ _ ~
~--------------~~---..,
ECC TIMEI
(8Al)
END TIME
(8Bl)
_ _ _ _ _+-_~---I
•
CTR 01
(8B6)
CTR 11
(8A6)
------1a
--------\n
CTRU
(8A6) _ _ _ _ _ _ _~----------------------~~
I'L_ _ _ _- - l
WRT
GATE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-----'
(8C8)
WRTXFER/ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
•
•
•
~
t....._ _ _ _ _ _---l
(8Cl)
Figure 4-11. Timing Diagram for Write Data
when 19H - the sync byte - is detected. The
enabling of SYNC BYTE I, enables the SYNC FNDI
lines (9Cl), which in tum activates the ID comparawr Ul, U2, U22 and U23 (9DX) and word clock U20
(8D7). (See the discussion of the Sync Byte Comparator Logic in Paragraph 4-32.)
SYNC FNDI also raises the ENBL XFER line, (8Cl),
which enables the ECC Generator logic (7AX) and
Ready Latch U2l (8D4), and gates on counter 0 of
U69 (8A7).
The 32-bit comparator (see Paragraph 4-33) compares the ID read from the disk with the ID of the
selected sector. At the end of the ID time, counter 0
times out, pulling the ECC TIMEI line (7A8) low and
initiating the ECC compare (see Paragraph 4-34). If
the ID and the ECC are valid, bit 6 of the controller
status register UlO (l1C5) is reset. At the end ofECC
time, U42-10 (8B2) activates the END TIME line
which resets RD GATE. The 8089 then checks bit 6
of control status register UlO (11C5). If the bit is
inactive, the 8089 continues with the write operation.
If the ID or ECC are not valid (bit 6 active), the AM
ENABLE and RD GATE lines are then reasserted
and the controller searches for the next address
mark.
To begin the second step of the write operation, the
8089 writes a OlH to 110 port 8000H (decoded
WDCOO/) and enables the write gate (WRT GATE),
through U24 (12B5), enabling the drive's write
circuitry. When counter 0 times out, counter 1 is
started. Counter 1 is set for a time interval equivalent
to the ECC time plus GAP 2. When counter 1 times
out, counter 2 is started and the U63-7 (8C3) is set,
activating WRT XFER/. WRT XFERI enables write
buffers U46 and U49 (7C7) and the ECC comparator
logic (7 AX), and raises the RDY line high indicating
to the 8089 that the write buffer is ready to receive
data.
The 8089 then enters its DMA mode to write data
from local RAM to the disk (see the discussion of the
DMA mode in Paragraph 4-27). The controller continues transferring data to the disk in this manner
until Counter 2 times out, indicating the end of the
data field, and raises the ECC TIME line. With the
ECC TIME line activated, the ECC generated during
the data transfer is written to the disk. END TIME
then terminates the write operation.
4-19
Principles of Operation
iSBC 215
I~I
I~I
DATA
DATA
•
AM ENABLE..J
/
RD GATE
(8C8)
10 DOES NOT
COMPARE
/ 1 0 DOES COMPARE
~--------------------------,
AM FND SECTORI - - - - - ,
(8B8)
SY~;c~rDI - - - - - - - - - . . ,
L---l,F'
+-__--,
ECC TIME/ _________
(SA1)
+ __
END TIME _________
(881)
~--...J
CTR 01 _ _ _ _ _ _.........
(SB6)
CTR2/ ________________________________________________________
(8A6)
~
L..-_ _ _....I
•
Figure 4-12. Timing Diagram for Read Data Transfer
4-30. READ DATA TRANSFERS
The read operation is divided into two steps: (1) read
sector ID and (2) read data. The reading of the sector
ID is performed in the same manner as for the write
operation (see Figure 4-12).
When the desired sector is located, the RD GATE is
again raised to search for the sync byte of the data
field. When SYNC FND/ is activated, counter 2 is
started through U6I·8 (8C4) and U59 (8B6), the ECC
generator is enabled and the RDY line is activated,
initiating the DMA read data transfer mode. Data is
then transferred from the disk to local RAM for the
duration of counter 2.
During a write operation (WRT XFERI low), the
8089 IOP writes to I/O port address 8028H. Write
I/O port address decoder U35 (5A2) decodes this
address and pulls WDC281 low, clocking the data to
be written to the disk (BDAT-O through BDAT·F)
into write buffer U46 and U49 (7C7). A high on load
serial register line LDSR (7C6), derived from word
clock U20 (8C7) loads the contents of the write buffer
(SR·O through SR-F) into the SER/DES (7C5).
Read/write clock R/W CLK-B (7B8) then clocks the
data bit by bit through the QH' output of U50 (7D5),
and through selector U70 (7 A 7) to the WRT DATA
line. R/W CLK-A clocks the serial data string on
WRT DATA through UI8 (10C3) to the selected
drive.
•
•
When counter 2 times out, ECC TIME is activated.
Following ECC TIME, END TIME is raised, terminating the read operation.
4-31. SER/OES LOGIC
The serial/deserialize logic performs two functions:
(1) converts parallel data words into a serial string of
bits to be sent to the disk drive during a write
operation, and (2) converts a serial string of bits into
16-bit words during a read operation. The SER/DES
logic is made up of Write Buffer U46 and U49 (7C7),
SERializer/DESerializer U47 and U50 (7C5), Read
Buffer U48 and U51 (7C4), and Selector U70 (7A7).
4-20
During a read operation, the R/W CLK-B (lOBI)
gates the serial data string (RD DATA) from the disk
drive through U18 (10B4) and selector U70 (7A7) and
into the SI input of U47 (7C5), creating a 16-bit
parallel word. Bit ring-O line BRO (7B8) then clocks
this word into read buffer U48 and U51 (7C4). BR-O
is derived from word clock U20 (8C7). With the read
buffer loaded, the 8089 initiates a read to I/O port
address 8028H. Read I/O port address decoder U36
(5B2) decodes this address and pulls RDC281 low,
which clocks the data word from the read buffer onto
internal data bus IDAT-O through IDAT-F.
•
iSBC 215
•
•
•
•
•
Principles of Operation
4-32. SYNC BYTE COMPARATOR LOGIC
4-34. ECC GENERATOR LOGIC
The sync byte comparator detects the presence of a
sync byte during a read operation and synchronizes
word clock U20 (8C7) with the data. A sync byte is
written preceding each sector ID and each data field
to indicate to the controller that datil to be read is
forthcoming (see Figure 3-2). The sync byte value is
always 19H except for the Shugart/Quantum drives,
which use a D9H for data fields.
The error checking code (ECC) logic performs two
functions: (1) during a write operation, it generates a
four byte ECC polynomial that is appended to the ID
field (format operation only) and the data field
(normal write) of a record (see Figure 3-2), (2) during
a read operation, it regenerates the ECC polynomial
and compares it to the ECC field read from the disk
record to ensure that the correct data was read from
the drive.
During a read operation, sync byte decoder U54 and
U73 (7B5) monitors the output of the SER/DES, U47
and U50 (7C5). When a 19H is detected, SYNC
BYTEI goes low indicating the presence of the sync
byte. SYNC BYTEI and the next output of R/W
CLK-B set the SYNC FND flip-flop, U57 (9C6).
SYNC FND activates word clock U20 (8C6), and
activates the read/write logic (sheet 8). A further
explanation of the sync byte logic can be found in
Paragraphs 4-29 through 4-31.
4-33. 32-BIT 10 COMPARATOR LOGIC
The 32-bit ID comparator logic compares the sector
ID of the record being searched for with the sector ID
being read from the disk drive. The sector ID is made
up of the flags, cylinder number, sector number and
head address.
To load the sector ID of the record being searched for
into :32-bit In comparator Ul, U2, U22 and U23
(9DX), the 8089 lOP writes to I/O ports 80:)OH,
enabling the WDC301 and WDC381 lines, respectively. WDC:301 and WDC381 initiate the loading of
the sector ID into the ID comparator. This loading
occurs prior to performing either a read or write data
operation. The ID compare operation begins after
the sync byte of an ID field has been detected (SYNC
FND). R/W CLK-B clocks the ID information, which
is stored in the ID comparator, out ofU22 (pins 7 and
9) bit by bit. U26 (9D2) compares the serial string of
bits with the sector ID from the disk drive (RDDATA). If the two sector IDs differ, ID no-compare
line ID NCMPRI is activated; if they are the same,
ID NCMPRI is raised. Selector U70 (7 A 7) ORs the
ID NCMPRI and the ECC NCMPRI lines (see
Paragraph 4-37). The resulting ID-ECC NCMPRI
lines is latched into U37 (9B6). The QI output ofU37,
ID NCMPR-L, is transmitted to bit 6 of status
register UlO (lIC5). The 8089 lOP then reads the
contents of the status register and checks the
condition of bit 6. Bit 6 being set high indicates that
the record read from the disk was either not the
record being searched for or had an ECC error;
conversely, bit 6 being set low indicates that the ID
field compared and that there was not an ECC error.
The 8089 lOP can then read or write the data portion
of the record.
During a write operation, serial data (either an ID
field or a data field) is transmitted from the
SER/DES (7C5) through selector U70 (7 A 7) and into
the ECC generator through pins 1 and 2 of UI03
(7A6), where the ECC polynomial is generated. At
the same time a high on the WRT XFER DL YD line
(7B8), transmitted through gate U68 (7B4), enables
the serial data to be transmitted through U71 (7 A2)
and selector U70 (7 A 7) to the WRT DATA line, where
it is transmitted to the disk. At ECC time (end of
data field), WRT XFER DLYD goes low, inhibiting
write data from being transferred through gate U68
(7B4). The ECC TIMEI line goes low, causing the
ECC polynomial to be written onto the disk through
un (7A3), U70 (7A7) and the WRT DATA line.
During a read operation, serial data (again either a
sector ID or a data field) is read into the ECC
generator through selector U70 (7 A 7) and into the
SER/DES through U71 (7 A3) and U70. At ECC
time, U71 compares the ECC polynomial from the
ECC generator bit by bit with the ECC polynomial
from the disk and transmits the difference through
U70 to the SER/DES for storage in RAM. If the
difference is zero, the ID-ECC NCMPRI line is
pulled high indicating correct data or sector ID
(Paragraph 4-33). If the result of the comparison is
non-zero, the difference is called the error syndrome.
The 8089 uses syndrome to correct errors in a sector
ID or data field (if correctable),
4-35. STATUS REGISTER LOGIC
Status register UlO and U44 (llX5) and U9 (llB3)
transmit status information from the selected disk
drive, the iSBX interface and various lines within
the controller disk interface circuitry to the controller. When the 8089 lOP issues a Read Status
command, or checks status as an internal operation,
read decode enable lines RDC 001 and RDC 081 are
acticated, causing the contents of status registers
UlO and U4, and U9, respectively to be transferred
onto the internal bus (IDAT-8 through IDAT-F). The
8089 then analyzes the status information and either
uses it for an internal operation or communicates the
4-21
Principles of Operation
iSBC 215
Table 4-8. Status Register Bits
Bits
8000H (Upper Byte)
U44 (1105)
F
C
Index
Drive Request
Illegal Address
Option Bit 10'
B
Option Bit 00'
A
9
S
Interrupt 10'
Interrupt 00'
iSBX Board Present at J3'
E
0
Function
8000H (Lower Byte)
U10 (11C5)
8008H (Lower Byte)
U9 (11B3)
7
Time Out
6
5
10 No Compare
Bus Acknowledge
4
Fault
Option Bit ii'
3
2
1
Data Sync
Option Bit 01'
Seek Complete
Ready
a
a
Interrupt 11'
Interrupt 01'
iSBX Board Present at J4'
Write Protected
Track Zero
Vendor
'iSBX Bus lines.
status of the data transfer operation to the host processor through system memory (Controller Invocation Block). Table 4-8 lists the status register bits.
Refer to Chapter 3 for information on the status
information transmitted to the host.
4-36. LINE DRIVERS AND RECEIVERS
All the serial data and high speed clock signals
transmitted between the controller and the disk
drive use differential pair line drivers and receivers.
•
The polarity on these lines is positive true logic i.e.,
when the + side of the line is more positive than theside ofline, a positive logic" 1" is being transmitted.
The controller's differential drivers, U16 (lOX3) are
referenced to 0 volts and +5 volts. The controller's
receivers that receive differential signals from the
Memorex, 14" Shugart, Pertec and Priam drives,
V13 (lOX6), are also referenced to 0 volts and +5
volts. The receivers for the 8" Shugart and Quantum
drives receive differential signals, Vl5 (IOX5), are
referenced to -5 volts and +5 volts.
•
•
•
4-22
•
•
CHAPTER 5
SERVICE INFORMATION
5-1. INTRODUCTION
This chapter provides service and repair assistance
instructions, service diagrams, a complete electronic
parts list for the printed circuit board assembly and
a reference to the controller's self diagnostic.
Use the following numbers for contacting the Intel
Product Service Hotline:
Telephone:
All U.S. locations,
Except Alaska, Arizona, & Hawaii
(800) 528-0595
All other locations: (602) 869-4600
5-2. SERVICE DIAGRAMS
•
I.
•
•
The controller board jumper and component locations, and schematic diagrams (Figure 5-1 through
5-3) are included at the end of this chapter. Note that
these diagrams are intended only for reference; they
reflect the iSBC 215 controller design at the time this
manual was printed. The schematics and component
location diagrams packaged with the controller
reflect the design version shipped and thus supercede the diagrams in this manual.
TWX Number:
910 - 951 - 1330
Always contact the Product Service Hotline before
returning a product to Intel for repair. You will be
given a repair authorization number, shipping
instructions, and other important information
which will help Intel provide you with fast, efficient
service. If you are returning the product because of
damage sustained during shipment or if the product
is out of warranty, a purchase order is required
before Intel can initiate the repair.
5-3. SERVICE AND REPAIR ASSISTANCE
United States customers can obtain service and
repair assistance from Intel by contacting the Intel
Product Service Hotline in Phoenix. Arizona.
Customers outside the United States should contact
their sales source (Intel Sales Office or Authorized
Distributor) for service information and repair
assistance.
Before calling the Product Service Hotline, you
should have the following information available:
a.
Date you received the product.
b.
Complete part number of the product (including
dash number). On boards, this number is usually
silk-screened onto the board. On other MCSD
products, it is usually stamped on a label.
c.
Serial number of product. On boards, this number is usually stamped on the board. On other
MCSD products, the serial number is usually
stamped on a label.
d.
Shipping and billing addresses.
e.
If your Intel Product warranty has expired, you
must provide a purchase order number for
billing purposes.
f.
If you have an extended warranty agreement, be
sure to advise the Hotline personnel of this
agreement.
5-4. SELF DIAGNOSTIC
A self diagnostic is provided with the iSBC 215
controller, stored in the on-board PROM. It performs
a go/no-go test of the controller hardware and
firmware. If the controller passes the test, it
indicates with a high degree of certainty that the
controller is operating properly. See the discussion of
the diagnostic in Chapter 3 for a description of the
program and instructions for initiating the operation.
5-5. REPLACEABLE COMPONENTS
This section contains the information necessary to
procure replacement components directly from
commercial sources. Component manufacturers
have been abbreviated in the parts list with a two to
five character code. Table 5-1 cross-references the
manufacturer's code with the name and location of
the prime commercial source. Table 5-2 lists all the
replaceable components on the controller board.
Note that the components that are available commercially are listed in the "MFR CODE" column as
"COML" and that they are ordered by description
(OBD). Procure commercially-available components
from a local distributor whenever possible.
5-1
Service Information
iSBC 215
•
Table 5-1. Code for Manufacturers
Mfr.
Code
BECK
Manufacturer
Beckman Instruments Inc.
Location
Fullerton, CA
BOUR
Bourns, Inc.
Riverside. CA
CRYST
Crystek
Ft. Meyers. FL
CTSK
CTS Keene, Inc.
Paso Robles, CA
DALE
Dale Electronics
Columbus, NE
FAI
Fairchild Semiconductor
Mt. View, CA
INTEL
Intel
Santa Clara, CA
MOT
Motorola
Phoenix, AZ
SNGMO Sangamo-Weston, Inc.
Pickens, SC
SPEC
Spectrol Electronics Corp.
City of Industry, CA
Adams, MA
SPRG
Sprague Electronic Co.
3M
3M Co.
St. Paul, MN
TI
VIK
Texas Instruments
Viking Industries, Inc.
Dallas, TX
Chatsworth, CA
COML
Any Commercial Source; Order By Description
(OBO)
•
Table 5-2. Controller Board Electrical Parts List
Reference Designation
Description
Mfr. Part No.
Mfr. Code
Qly.
C1. C2
Capacitor. 22jJF, Tant, 110%.15V
1500226X901SB2
SPRG
2
C3
Capacitor, 2.2jJF. Tant, ±10%, 20V
1S0022SX9020A2
SPRG
1
C4
Capacitor. 0.33jJF. Cer. Z5U
OBO
COML
1
C5
Capacitor. 10jJF. Tant, :l10%, 20V
1500106X9020B
SPRG
1
C6
C7 through C12
C14 through C44
Capacitor, 10pF, Mica, ±S%.
01S-SC100J03
SNGMO
1
Capacitor. 0 10jJF, Cer. ZSU
OBO
COML
37
1
J1
Connector, Header SO Pin
3433-1302
3M
J2
Connector. Header 40 Pin
3432-1302
3M
1
J3 J4
Connector. 44 Pin
68-369
VIK
2
RP1
RP3
Resistor Pack. 220/330 O. 10 Pin
Resistor Pack, 100 O. 8 Pin
76S-5-R220/330
764-3-R100
BECK
BECK
1
1
RP4
Resistor Pack. 56 0, 6 Pin
763-1-R56
BECK
1
RP5, RP7 through
RP13
Resistor Pack, 10 kO. 8 Pin
764-1-R10K
BECK
8
RP6
Resistor Pack. 220/330 0, 8 Pin
764-5-R220/330
BECK
1
R1. R4, R7
through R9, R13, R14
Resistor. Carb .. 10 KO. "'W. +5%
OBO
COML
7
R2. R3. R6. R12.
R1S. R16
Resistor. Carb, 270 0, '/,W, +S%
OBO
COML
6
RS
Resistor, Carbo 100 kO, '/4W, ±5%
OBO
COML
1
R10, R11
Resistor, Carb. 680 O. '!4W, ±5%
OBO
COML
2
1
5-2
S1
Switch, 8 Position, DIP
206-08LPST
CTSK
S2
Switch. 10 Position, 01 P
206-10LPST
CTSK
1
U1, U2. U22, U23
IC, 8 Bit Shift Reg.
SN74LS16SN
TI
4
U3
IC. Octal, 0 Type. Flip-Flop
SN74LS273N
TI
1
U4 through U6.
U81 through U83
IC. Octal Latch. Inverting
8283
INTEL
6
U7, U27
IC, Quad Driver, Inverting, OC
U8
IC, Dual 4 to 1 Selector/MUX
SN74LS153N
TI
1
U9, U85, U86
IC, Octal 0 Type Latch
SN74LS373N
TI
3
7438
2
•
•
•
Service Information
iSBC 215
•
•
•
•
Table 5-2. Controller Board Electrical Parts List (Continued)
Reference Designation
Mfr. Part No.
Mfr. Code
Qly.
U 10, U44, U46,
U48. U49, U51
IC, Octal D Type Flip-Flop
SN74LS74N
TI
6
U11, U61, U68,
IC Quad 2 Input NAND
SN74LSOON
TI
3
U12, U29, U59. U72
IC, Quad 2 Input AND
SN74LS08N
TI
4
U13
IC, Quad Line Receiver
3486
U14
IC, Dual Line Receiver
75107A
TI
1
U15. U89
IC, Quad 3 State Buffer
SN74LS125N
TI
3
U16
IC, Quad Line Driver
3487
TI
1
U17
IC. Hex Inverter
SN74S04N
TI
1
U18
IC, Dual Pos. Edge Trig. Flip-Flop
SN74S4
U19, U26
IC, 2 Wide. 3 in, 2 in. AND-OR-INV
SN74LS51N
TI
2
U20
IC. 4 Bit Binary Counter
SN74LS161N
TI
1
U21. U37. U56,
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5-29/5-30
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5-27/5-28
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5-25/5-26
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5-7/5-8
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5-5/5-6
•
APPENDIX A HANDSHAKE
SEQUENCES AND EXAMPLE HOST
PROCESSOR DISK CONTROL PROGRAM
INTRODUCTION
The information contained in this appendix is
provided to illustrate various methods of implementing data transfers between one or more host processors and the iSBC 215 controller. The flow charts
illustrate the handshake procedures required between a host processor and the controller. User
sequences are shown both for single and multi-user
processing environments. A sequence for initiating
overlapped seeks is also given.
•
The program listing provides an example program
that a host processor would run to direct data transfer between the host and the iSBC 215 controller.
The program is written in MCS-86™ Macro Assembler language. It illustrates the data structures that
the iSBC 215 controller requires and shows a few
simple disk operations drivers.
SINGLE USER SEQUENCE
WITH OVERLAPPING SEEKS
The flow chart in Figure A-2 shows the handshake
sequence between a single host processor and the
controller for data transfer operations that user overlapping seeks.
MULTI-USER SEQUENCE
The flow chart in Figure A-3 shows the handshake
sequence between a host processor and the controller
when more than one processor is transferring data
between the disk drives through the same controller
(multi-processor environment). Note that in this case
the Command Semaphore byte in the Controller
Invocation Block is also used. Overlapping seeks in
a multi-processor environment are implemented the
same as in single processor environments.
SINGLE USER SEQUENCE
•
The flow chart in Figure A-I shows the handshake
sequence between a single host processor and the
controller for basic data transfer operations (with no
overlapping seeks). Note that communication between the host and the controller is through the
Status Semaphore and Operation Status bytes of the
Controller Invocation Block.
EXAMPLE HOST PROCESSOR
DISK CONTROL PROGRAM
The following program example is for a single user
environment. Some of the techniques illustrated in
the flow charts in this appendix are implemented in
this program, but not all.
•
•
A-I
Appendix A
iSBC 215
•
SET UP
}
1/0 PARAMETER
BLOCK
WRITE '01' TO
WAKE-UP 1/0
PORT
Set up command and parameters for desired data
transfer operation.
} Iniliate data Iran,fer op.,.lion.
NO
NO
SET
ST. SEMA.
- 0
l
Check to see if controller has completed operation
(STATUS SEMAPHORE byte is non-zero).
}
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was completed without error.
•
•
YES
SET
ST. SEMA.
- 0
FINISH
} Chock E",,, Stalu, buffer and p,o,""" ,"",.Its.
FINISH
Figure A-I. Flow Chart for Single User Handshake Sequence Without Overlapping Seeks
A-2
•
•
Appendix A
iSBC 215
•
SET UP
110 PARAMETER
BLOCK
} Set Up comma nd and parameters f m seek operatio n .
} Initi.te d.ta tmnsf" op".tion.
BRANCH TO
OTHER
PROCESSING
TASKS
/
•
} Perlonn oth'" processing tasks.
OP COMPLETE INTERRUPT
NO
SET
ST. SEMA.
o 0
YES
Set u~ command and parameters for next seek
} operatIOn.
SET 1/0 PARAMETER BLOCK FOR
NEXT OPERATION;
SET ST. SEMA 0
•
•
Respond to operation complete interrupt; Check
} OPERATION STATUS byte to see if operation was
completed without error.
FINISH
WRITE '01' TO
WAKE-UP
1/0 PORT
} Initiate next data transf", o"",.tion.
BRANCH TO
OTHER PROCESSING TASKS
/
} Perlonn oth" pmcessing tasks.
OP COMPLETE INTERRUPT
NO
SET
ST. SEMA.
=0
Respond to operation complete interrupt; check
} OPERA nON STATUS byte to see if operation was
completed without error.
YES
SET ST. SEMA.
= 0; BRANCH
TO OTHER PROCESSING TASK
} Continue with oth" processing tasks.
FINISH
•
Figure A-2. Flow Chart for Single User Handshake Sequence With Overlapping Seeks
A-3
iSBC 215·
Appendix A
•
SEEK COMPLETE INTERRUPT
l
NO
Respond to seek complete interrupt for first opera
tion; check status buffer to determine if seek opera
tion was completed without error.
YES
•
SET
ST. SEMA.
" 0
GO TO SEEK
ERROR HANDLING
ROUTINE
BRANCH TO
OTHER PROCESSING TASKS
/
SEEK COMPLETE INTERRUPT
NO
SET
ST. SEMA.
" 0
l
Respond to seek complete interrupt for second opera
tion; check status buffer to determine if seek operation was completed without error.
•
YES
SET
ST. SEMA.
" 0
FINISH
GO TO SEEK
ERROR HANDLING
ROUTINE
FINISH
Figure A-2. Flow Chart for Single User Handshake Sequence With Overlapping Seeks (Continued)
A-4
•
•
Appendix A
iSBC 215
•
LOCK THE
MULTIBUS'·
INTERFACE
UNLOCK
MULTIBUS'·
INTERFACE
}
NO
Obtain control of disk controller. Test and set COM·
MAND SEMAPHORE byte.
YES
SET COMM. SEMA.
TO NON-ZERO
AND UNLOCK
MULTIBUS'· INTER.
•
•
B
Set up command and parameters for desired data
} transfer operation.
SET UP
I/O PARAMETER
BLOCK
WRITE '01' TO
WAKE-UP 1/0
PORT
} Initiat, data t,-an,f" opemtion,
BRANCH TO
OTHER PROCESSING TASKS
} Continu, with othe< proc""ing t.,ka,
/ ' OP COMPLETE INTERRUPT
•
NO
SET
ST. SEMA.
o 0
Respond to operation complete interrupt; check
} OPERATION STATUS byte to see if operation was
completed without error.
YES
SET
ST. SEMA.
o
} Relinquiah controll", of disk controll"',
0
A
FINISH
•
Figure A-3. Flow Chart for Multi-User Handshake Sequence
A·5
Appendix A
iSBC 215
•
YES
SET
COMM. SEMA.
= 0
•
FINISH
•
•
Figure A-3. Flow Chart for Multi-User Handshake Sequence (Continued)
A-6
•
Appendix A
iSBC 215
•
10/27/80
tSBC 215 8" WINCHESTER DISK CONTROLLER PROGRAMMING EXAMPLE
MCS-86 MACRO ASSEMBLER
PAGE
ISIS-II MCS-86 MACRO ASSEMBLER V2.1 ASSEMBLY OF MODULE EXMPRG
OBJECT MODULE PLACED IN :FI:EXMPRG.OBJ
ASSEMBLER INVOKED BY:
ASM8n :FI:EXMPRG.MMO DATR(IO/2l18D) XREF OEBUG
LOC
LINE
OBJ
SOURCr:
$PAGELENGTH(85) PAGEWIDTH(115) TITLE(iSBC 215 8" WINCHESTER DISK CONTROLLER PROG
RAMMING EXAMPLE) XREF
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
2I
22
23
24
25
26
27
28
29
30
31
32
33
•
•
34
=1
35
36
37 +1
38 +1
,.
.""""""""""."", •• ,."""."""""" ••••••• """,,##,#"
.,
iSBC 215
DISK CONTROLLER PROGRAMMING EXAMPLE
"
".""",.",#,#,###, •• ##.# •••• " •• """., •••• #.".",".# •• ".""""
THIS PROGRAM ILLUSTRATES THE DATA STRUCTURES REQUIRED BY THE llsc 215
DISK CONTROLLER. A FEW SIMPLE DISK OPERATION DRIVERS ARE ALSO SHOWN.
THE HARDWARE CONFIGURATION SUPPORTED IS:
I.
2.
3.
4.
5.
iSHC 86/12A HOST CPU
20 BIT SYSTEM MEMORY ADDRESS WIDTH
16 BIT SYSTEM DATA BUS WIDTH
16 HIT SYSTEM lID ADDRESS WIDTH
iSBC 215
a. WAKE UP ADDRESS ( WUA ) AT I/O PORT 0635H
b.
INTERRUPT 5
c.
-12 VOLTS INPUT
d.
RELINQUISH BUS CONTROL ON ANY REQUEST
FOR (2), PROGRAMMING OF DATA TRANSFERS MUST TAKE THIS INTO ACCOUNT,e.g. THERE
IS NO WRAPAROUND IN SEGMENTS IF MORE THAN 64K BYTES ARE TRANSFERRED.
iSSC 215 SWITCH AND
JU~PER
SETTINGS:
FOR (3), SWITCH 52-1 IS CLOSED.
FOR (4), SWITCH S2-2 IS CLOSED.
FOR (Sa), SWITCHES SI-6,SI-7,S2-5,S2-6,S2-8, AND S2-10 ARE CLOSED, THE
RE~AINING ADDRESS SELECT SWITCHES ARE OPEN.
FOR (5b), WI9-C CONNECTS TO WI9-5; INTERRUPT VECTORS MUST SE SET UP PROPERLY.
FOR (5c), W21-1 CONNECTS TO W21-3
FOR (5d), W2-1 CONNECTS TO W2-2.
$INCLUDE(:FI:COMBLK.~MD)
$EJECT TITLE(iSBC 215 COMMUNICATION BLOCKS)
•
•
A-7
iSBC 215
Appendix A
MCS-86 MACRO ASSEMBLER
iSBC 215 COMMUNICATION BLOCKS
LOC
LINE
OBJ
0635
0000
0000 01
0001 00
0002 0000----
0000
0000 01
0001 00
00112 0400----
0006
0008
0009
OOOA
0000
01
00
OEOO----
OOOE
OOOE 0400
A-8
=I
=1
=1
=I
=1
=1
=1
=1
=I
=1
=1
=I
=I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=1
=I
=1
=1
=1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=1
=1
=1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94 +1
10/27/80
PAGE
SOURCE
COMMUNICATION BLOCKS
I.
•
S CB
THE SCB TELLS THE 8089 ON THE iSBC 215 THE WIDTH OF THE 8089's LOCAL
BUS AND POINTS TO THE CCB.
***********************************************************************
THE MEMORY ADDRESS OF THE SCB IS EQUAL TO THE 1/0 WAKE-UP ADDRESS
*
( WUA ) OF THE iSBC 215 MULTIPLIED BY 16.
*
***********************************************************************
WUA
EQU
0635H
WAKE-UP ADDRESS
I/O PORT NUMBER
SCBSEG
SEGMENT AT WUA
PUTS SCB AT ADDRESS 06350H
SCB
SOC
CCBPTR
LABEL
DB
DB
DO
TELL 8089 IT IS ON A 16 BIT LOCAL BUS
RESERVED
POINTER (SEGMENT + OFFSET) TO CCB
SCBSEG
ENDS
II.
FAR
01H
OOH
CCB
CCB
•
THIS BLOCK CONTAINS THE CONTROL BYTES, BUSY FLAGS, AND POINTERS TO THE
STARTING ADDRESSES OF THE CHANNEL PROGRAMS FOR THE 8089.
CCBSEG
SEGMENT
CCB
CCWI
BSYFLGI
CHIPTR
LABEL
DB
DB
DD
DW
CCW2
DB
BSYFLG2 DB
CH2PTR DD
CH2PC
LABEL
DW
CCBSEG
ENDS
$EJECT
CCB MUST BE CONTIGUOUS
FAR
01H
OOH
CHIPC
OOOOH
OIH
OOH
CH2PC
FAR
0004H
START CH. 1 PROGRAM IN LOCAL MEMORY
CH. 1 BUSY FLAG
POINTER TO FIFTH BYTE OF CIB, WHICH
CONTAINS STARTING ADDRESS OF CH. I
FIRMWARE PROGRAM
RESERVED
START CH. 2 PROGRAM IN LOCAL MEMORY
CH. 2 BUSY FLAG
POINTER TO LAST WORD OF CCB, WHICH
CONTAIN S ST ART ING ADD RESS OF CH. 2
FIRMWARE PROGRAM
•
STARTING ADDRESS OF CH. 2 PROGRAM
•
•
iSBC 215
•
Appendix A
HCS-86 MACRO ASSEMBLER
iSSC 215 COMMUNICATION BLOCKS
Loe
LINE
OSJ
=1
=1
=
=1
=1
=1
=
0000
0000
0001
0002
0003
0004
0004
0008
OOOA
OOOC
00
00
00
00
00000000
0000
00000000
•
•
1
0000
0000
0004
0008
OOOA
OOOB
OOOC
OOOE
0010
00 11
0012
0014
0016
001A
00000000
00000000
0000
00
00
0000
0000
00
00
0000
0000
00000000
00000000
1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144 +1
145 +1
10/27/80
PAGE
SOURCE
III.
CIB
THIS BLOCK CONTAINS GENERAL PURPOSE COMMAND AND STATUS BYTES, SEMAPHORES, AND POINTERS TO ALLOW THE USE OF THE iSBC 215 IN A MULTIPROCESSOR/MULTI-PROCESSING SYSTEM.
bIBSEG
SEGMENT
CIB
C lBCrlD
OPSTS
CMDSEfl
STSSEM
CH1PC
LABEL
DB
DB
DB
DB
LABEL
DO
IOPBOFF OW
IOPBSG
OW
DO
CIBSEG
IV.
; CIS MUST BE CONTIGUOUS
FAR
OOH
DOH
DOH
DOH
FAR
00 DOH
OFFSET IOPB
IOPBSEG
OOOOH
CIS COMMAND BYTE NOT USED BY iSBC 215
CIB STATUS BYTE IS USED BY iSBC 215
COMMAND BYTE SEMAPHORE
STATUS BYTE SEMAPHORE
STARTING ADDRESS OF CH.
POINTER TO IOP8
1 PROGRAM
RESERVED
ENDS
IOPB
THIS BLOCK CONTAINS THE DEVICE DEPENDENT CONTROL INFORMATION FOR THE
iSBC 215 CONTROLLER.
IOPBSEG SEGHENT
IOPB MUST BE CONTIGUOUS
,
IOPB
ACTCNT
DEVCOD
UNIT
FUNC
MODIFY
CILNDR
HEAD
SECTOR
BUFOFF
BUFSEG
REQCNT
LABEL
DO
DO
OW
DB
DB
OW
OW
DB
DB
OW
OW
DO
DO
FAR
OOOOH
OOOOH
OOOOH
DOH
DOH
OOOOH
00 DOH
DOH
DOH
OOOOH
00 DOH
OOOOH
00 DOH
RESERVED
ACTUAL TRANSFER COUNT (32 BIT INTEGER)
DEVICE CODE (OH-WINCHESTER 0IH-FLOPPY)
UNIT NUMBER (0 (= UNIT (= 3)
FUNCTION CODE (0 (= FUNCTION (= OFH)
MODIFIER WORD
CYLINDER NUMBER
HEAD NUMBER
SECTOR NUUBER
POINTER TO DATA BUFFER
REQUESTED TRANSFER COUNT (INTEGER)
RESERVED
IOPBSEG ENDS
,
$INCLUDE(:F1:INITBL.MMD)
$EJECT TITLE(DISK DRIVE INITIALIZATION TABLES)
•
•
A-9
iSBC 215
Appendix A
MCS-86 MACRO ASSEMBLER
DISK DRIVE INITIALIZATION TABLES
LOC
LINE
OBJ
=1
=1
=1
=1
=1
=1
=1
=1
=1
=I
=1
= I
0000
0002
0003
0004
0005
0007
0001
04
00
IF
0001
05
0008
OOOA
OOOB
OOOC
0000
OOOF
0001
02
00
11
0002
05
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
-I
=1
=1
-I
-I
0010
0012
0013
0014
0015
0017
0000
00
00
00
0000
00
0018
OOIA
OOIB
ODIC
0010
OOIF
0000
00
00
00
0000
00
178
179
180
181
182
183
184
185
186
187
=1
=1
-I
-I
-I
-I
-I
=1
-I
-I
-I
- IF A DRIVE IS NOT PRESENT, ITS INITIALIZATION TABLE MUST BE ALL ZEROES.
8 " WINCHESTER HARD DISK DRIVES
1
BYTES PER SECTOR
1
MAXIMUM SECTORS PER TRACK
1
1---------------------+--------------------------------I
128
54
1
1
256
512
1024
1
1
1
INITBLSEG
1
1
31
17
1
9
1
SEGMENT
DRIVE #0 ---SHUGART MODEL SAI004 (10.6 MEGABYTES STORAGE)
DW
DB
DB
DB
OW
DB
256
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
4
o
31
256
5
OF
OF
OF
OF
OF
OF
CYLINDERS
FIXED READ/WRITE SURFACES
REMOVABLE R/W SURFACES
SECTORS PER TRACK
BYTES PER SECTOR
ALTERNATE CYLINDERS
DRIVE #2
256
2
o
17
512
5
•
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
OF
OF
OF
OF
OF
OF
CYLINDERS
FIXED READ/WRITE SURFACES
REMOVABLE R/W SURFACES
SECTORS PER TRACK
BYTES PER SECTOR
ALTERNATE CYLINDERS
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
OF
OF
OF
OF
OF
OF
CYLINDERS
FIXED READ/WRITE SURFACES
REMOVABLE R/W SURFACES
SECTORS PER TRACK
BYTES PER SECTOR
ALTERNATE CYLINDERS
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
OF
OF
OF
OF
OF
OF
CYLINDERS
FIXED READ/WRITE SURFACES
REMOVABLE R/W SURFACES
SECTORS PER TRACK
BYTES PER SECTOR
ALTERNATE CYLINDERS
NONEXISTENT
191
200
201
202
203
204
205
206
207
208 +1
•
DRIVE #1 ---SHUGART MODEL SAI002 (5.3 MEGABYTES STORAGE)
189
190
193
194
195
196
197
198
199
•
THIS SEGMENT CONTAINS THE DRIVE CONFIGURATION DATA TABLES THAT ARE USED
BY THE INITIALIZATION ROUTINE. THEY MUST BE MODIFIED TO REFLECT THE
PARTICULAR DRIVES BEING USED WITH THE iSBC 215 DISK CONTROLLER.
188
-I
-I
=1
DISK DRIVE INITIALIZATION PARAMETER TABLES
DW
DB
DB
DB
OW
DB
192
-I
PAGE
SOURCE
177
-I
-I
A-lO
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
10/27/80
OW
DB
DB
DB
OW
DB
DRIVE #3
DW
DB
DB
DB
OW
DB
$EJECT
OOOOH
DOH
DOH
DOH
OOOOH
DOH
•
NONEXISTENT
00 DOH
DOH
DOH
DOH
OOOOH
DOH
•
•
Appendix A
•
iSBC 215
MCS-86 HACRO ASSEMBLER
LOC
DISK DItIVE INITIALIZATION TABLES
OBJ
LINE
~I
~I
~I
~I
I
=1
~
~I
=1
~I
0020
0022
0023
0024
0025
0027
•
•
0028
002A
002B
002C
0020
002F
0030
0032
0033
0034
0035
0037
0038
003A
003B
003C
0030
4000
00
02
IA
0001
01
4DOO
00
02
IA
8000
00
0000
00
00
00
0000
00
0000
00
00
00
0000
=1
=1
=1
=1
=1
=1
=1
=I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=I
=1
=1
=1
=1
=1
=I
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260 +1
261 +1
10/27/80
PAGE
SOURCE
.............. '" .......................................
8"
'0
FLEXIBLE
••••••••••••••••••
0
••
DISK DRIVES
0
••••••••••••••••••••••••••••••••
MAXIMUM SECTORS PER TRACK
1 BYTES PER SECTOR
1
1
1---------------------+--------------------------------I
128
26 (FM)
1
1
1
256
26 (MFM)
1
1
1
512
15 (MFM)
1
1
1
1024
8
(MFH)
1
1
1
•••••••••••••••••••••••••••••••••••••••••••
0
••••••••••••
"-----------------------------------------------------------------------------DRIVE 110 ---SHUGART MODEL 850
DW
DB
DB
DB
DII
DB
77
a
2
26
256
01
DRIVE III ---SHUGART MODEL 850
DW
DB
DB
DB
OW
DB
DRIVE 112
DI,
DB
DB
DB
Oil
DB
DRIVS 113
OW
DB
DR
DB
Oil
DR
INITRLSEG
77
a
2
26
128
00
(1.0 MEGAByn;S STORAGE)
NUMBER
NUMBER
NUI1BER
NUMBER
NUMBER
IIFM( I)
OF CYLINDERS
OF FIXED READ/WRITE SURFACES
OF REMOVABLE R/W SURFACES
OF SE CTORS PER TRACK
OF BYTES PER SE CTOR
OR FM(O) RECORDING MODE
(1.0 ) IIEGABYTES STORAGE)
NUMBER
NmlBER
NUMBER
NUMBER
NUMBER
HFII (I)
OF
OF
OF
OF
OF
OR
CYLINDERS
FIXED READ/WRITE SURFACES
REMOVABLE R/II SURFACES
SE CTORS PER TRACK
BYTES PER SECTOR
FH(O) RECORDING MODE
NUMBER
NUMBER
NUIIBER
NU~IB ER
NUMBER
MFM( I)
OF
OF
OF
OF
OF
OR
CYLINDERS
FIXED READ /WRITE SURFACES
REMOVABLE R/W SURFACES
SECTORS PER TRACK
BYTES PER SECTOR
FM(O) RECORDING MODE
NUMBER
NUMBER
NUMBER
NUilBER
NUI1BER
HFll( I)
OF
OF
OF
OF
OF
OR
CYLINDERS
FIXED READ/WRITE SURFACES
RE/IOVABLE R/W SURFACES
SECTORS PER TRACK
BYTES PER SECTOR
FM(O) RECORDING MODE
NONEXISTENT
OOOOH
DOH
DOH
DOH
OOOOH
OOH
NONEXISTENT
00 DOH
DOH
OOH
DOH
OOOOH
DOH
ENDS
$INCLUDE( :FI :DATSEG.IIMD)
$EJECT TITLE(DATA SEGMENT)
•
•
A-ll
iSBC 215
Appendix A
MCS-86 MACRO ASSEMBLER
DATA SEGMENT
LOC
LINE
OBJ
=1
~1
:1
=1
=1
=1
=1
=1
=1
:1
=1
=1
=
1
=1
=1
=1
=1
=1
=1
0000
0000
0001
0002
0003
:1
= 1
00
00
00
00
=1
=1
=1
= 1
=
1
:1
=1
0004
0004
0005
0006
00 () 7
=
00
00
00
00
1
=1
=1
=1
=1
= 1
0008
0008
0009
OOOA
0008
00
00
00
00
=1
=1
=1
=1
=1
=1
=1
=
I
=1
=1
OOOC
OOOE
DOOF
0011
0012
0013
0015
0016
0017
0000
00
0000
00
00
0000
DO
00
00
=1
=
1
=1
=1
=1
= 1
=1
=1
=1
=
1
= 1
=1
=1
=1
0018 00
=1
0019 90
=1
=1
=1
001A
A-12
262
263
264
265
266
267
268
269
270
271
272
10/27/80
SOURCE
DATA SEGMENT
•
;
DATASEG SEGMENT
THIS SEGMENT CONTAINS VARIOUS DATA THAT ARE USED BY THE iSBC 215 DRIVER
SOFTWARE_
273
- THE FLAGS ARE SET BY THE INTERRUPT SERVICE ROUTINE, AND ARE COPIES OF THE
CIB STATUS POSTED BY THE iSBC 215.
THE ROUTINES THAT USE THE FLAGS ARE
RESPONSIBLE FOR CLEARING THEM AFTER USE.
274
275
276
277
278
279
280
281
282
283
284
285
280
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
PUBLIC
OPCMP,SKCMP,PKCHG,ERRSTS
OPERATION COMPLETE FLAGS
;
OPC;,!P
OPCMPO
OPCHP 1
OPCMP2
OPO!P3
LABEL
DB
DB
DB
DB
BYTE
DOH
DOH
DOl!
OOH
OPERATION
OPERATION
OPERATION
OPERATION
COMPLETE
COMPLETE
COMPLETE
COMPLETE
S KCt!P
SKC'IPO
SKCMPI
SKCMP2
SKCHP3
UNIT
UNIT
UNIT
UNIT
LAB EL
DB
DB
DB
DB
BYTE
OOH
OOH
DOH
OOH
SEEK
SEEK
SEEK
SEEK
COMPLETE
COMPLETE
COMPLETE
COMPLETE
PACK
PACK
PACK
PACK
CHANGE
CHANGE
CHANGE
CHANGE
ON
ON
ON
ON
UNIT
UNIT
UNIT
UNIT
a
•
PACK CHANGE FLAGS
PKCHG
PKCHGO
PKCHG 1
PKCHG2
PKCHG3
LABEL
DB
DB
DB
DB
BYTE
OOH
DOH
DOH
DOH
ON
ON
ON
ON
UNIT 0
UNIT
UNIT
UNIT
ERROR STATUS BLOCK
(LOADED FROM CONTROLLER BY ERROR HANDLER)
ERRSTS
SFERST
DESCYL
DESHD
DES SEC
ACTCYL
ACTHD
ACTSEC
NMRTRY
317
ow
DB
DW
DB
DB
Ol,
DB
DB
DB
OOOOH
OOH
OOOOH
DOH
DOH
OOOOH
OOH
OOH
0011
ERROR STATUS WORD
SOFT ERROR STATUS BYTE
DESIRED CYLINDER
DESIRED HEAD
DESIRED SECTOR
ACTUAL CYLINDER + FLAG BITS
ACTUAL HEAD
ACTUAL SECTOR
NUMBER OF RETRIES MADE
LAST OPERATION COHPLETE BYTE
(COPIED FROM CIB BY WAIT215)
318
319
320
321
ON
ON
ON
ON
SEEK COMPLETE FLAGS
LSTSTS
DR
DOH
1
322
323
324
ENDDAT
=1
=1
325
326
DATASEG ENDS
=1
327
328 +1
329 +1
$INCLUDE(:Fl:USER.MMD)
$EJECT TITLE(SYSTEM DEPENDENT INITIALIZATION)
=
PAGE
,
EVEN
LABEL
FAR
END OF DATA SEGMENT
•
•
•
iSBC 215
•
MCS-86 MACRO ASSEMBLER
SYSTEM DEPENDENT INITIALIZATION
LOC
LINE
OBJ
0005
•
Appendix A
0094
0094 0000
0096 0000
0000 (64
00
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
10/27/80
PAGE
SOURCE
SYSTEM DEPENDENT INITIALIZATION
THIS ROUTINE SETS UP THE INTERRUPT VECTOR FOR AN iSBC 86/12A CPU
RUNNING UNDER THE iSBC 957A INTERFACE/EXECUTION PACKAGE.
- TRE 8259 INTERRUPT CONTROLLER AND OTHER INITIALZATIONS ARE PERFORMED
BY THE iSBC 957A FIRMWARE.
INTERRUPT VECTOR DEFINITION
INTRPT
EQU
SEGOOOO SEGMENT AT OOOOR
INTRIP
INTRCS
,
ORG
80H + 4*INTRPT
OW
OOOOR
OOOOH
Oil
iSBC 220 INTERRUPT NUMBER
INTERRUPT VECTORS ARE FROM ABSOLUTE
ADDRESSES OOOOOR TO OOFFOR
LOCATION OF INTERRUPT VECTOR WITH
iSBC 957A FIRMWARE
- INSTRUCTION POINTER
- CODE SEGMENT
SEGOOOO ENDS
STACK ALLOCATION
STACK
SEGMENT
STACK SEGMENT
DB
64 DUP(OOH)
ENDSTK
LABEL
FAR
STACK
ENDS
ALLOW 64 BYTES FOR STACK
)
•
0040
0000
•
0000
0001
0004
0006
0009
OOOC
OOOE
0014
001A
001C
001E
0020
0021
FA
B8---8EDO
BC4000
B80000
8ED8
C70694003D02
C7069600---E4C2
24DF
E6C2
FB
CC
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=1
-1
=1
=1
=1
•
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404 +1
405 +1
,
,
STACK AND INTERRUPT CONFIGURATION ROUTINE
USERSEG SEGMENT
PUBLIC
ASSUME
CONFIG
CONFIG
DS:SEGOOOO
PROC FAR
CLI
MOV
MOV
MOV
MOV
MOV
MOV
1I0V
IN
AND
OUT
AX,STACK
SS,AX
SP,OFFSET ENDSTK
AX,OOOOR
DS,AX
INTRIP,OFFSET INT215
INTRCS,SEG INT215
AL,OC2R
AL,11011111B
OC2H,AL
STI
,
CONFIG
INT
; DISABLE INTERRUPTS WRILE SETTING UP
;;; SET UP STACK
GET POINTER TO SEGMENT OOOOR
SET UP INTERRUPT VECTOR
INPUT INTERRUPT MASK FROM 8259
ENABLE INTERRUPT 5
WRITE NEW MASK OUT TO 8259
ENABLE INTERRUPTS
GO TO MONITOR
ENDP
USERSEG ENDS
SBC215DRIVER
,
SEGMENT
ASSUME CS:SBC215DRIVER
$INCLUDE(:Fl:RESET.MMD)
$EJECT TITLE(CONTROLLER RESET ROUTINE)
A-13
iSBC 215
Appendix A
MCS-86 MACRO ASSEMBLER
CONTROLLER RESET ROUTIN!
LOC
LINE
OBJ
0000
so
0000
0001
0002
0003
0004
53
51
52
1E
0005
0008
OOOA
0010
0016
B83506
8ED8
C70600000100
C70602000000
C7060400----
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
-1
R =1
=1
=1
=1
001C C5060200
0020
0026
002C
0032
0038
003E
0044
C706000001FF
C70602000400
C7060400---C70608000100
C7060AOOOEOO
C7060COO---C7060E000400
=1
=1
=1
=1
R =1
=1
=1
R =1
=1
=1
=1
=
004A
004D
004F
0055
005B
0061
0067
B8---8EDS
C70600000000
C70602000000
C70604000000
C70608000000
C7060AOO----
1
=1
R =1
=1
=1
=1
=1
=1
R =1
-I
=1
A-14
10/27/80
PAGE
SOURCE
406
407
408
409
410
CONTROLLER RESET ROUTINE
•
411
412
413
414
415
416
4I7
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480 +1
RES215 SETS UP THE COM~UNICATION BLOCKS FOR THE iSBC 215, LINKS THEM
TOGETHER AND GIVES A RESET, CLEAR RESET, CHANNEL ATTENTION SEQUENCE TO
THE CONTROLLER. THIS CAUSES THE 8089 ON THE CONTROLLER TO SET UP ITS
INTERNAL POINTER TO THE CCB BY THREADING DOWN THE LINKS STARTING WITH
THE SWITCHES ON THE CONTROLLER.
SUBSEQUENT CA's WILL CAUSE THE 8089 TO
FETCH ITS POINTERS STARTING AT THE CCS.
-
IF THE CH. I BUSY FLAG IS NOT CLEARED WITHIN A "REASONABLE" AMOUNT OF TIME,
THEN THE iSSC 215 IS PROBABLY NOT RESPONDING TO THE CHANNEL ATTENTION.
ON THE CONTROLLER: CRECK SWITCH SETTINGS; VOLTAGES; RESET, CLEAR RESET,
CHANNEL ATTENTION SIGNALS; READY INPUT TO 8089; 8089 STATUS LINES; R/W
STROBES.
- THE SYSTEM INTERRUPT LOGIC AND VECTORS FOR THE CONTROLLER ARE ASSUMED TO BE
CONFIGURED BY AN EXTERNAL PROGRAM.
INPUT DATA:
NONE
OUTPUT DATA:
CARRY FLAG:
= 0 IF RESET OKAY
=
RES215
PUBLIC
RES215
PROC
FAR
PUSH
PUSH
PUSH
PUSH
PUSH
AX
BX
CX
DX
DS
I IF CH.
I BUSY FLAG NOT RESET
(NOT RESPONDING)
SAVE REGISTERS
SET UP LINKS BETWEEN COMMUNICATION BLOCKS
SCB
ASSUME
DS:SCBSEG
MOV
AX,SCBSEG
f!OV
DS,AX
MOV WORD PTR SOC,OOOIR
MOV WORD PTR CCBPTR,OFFSET CCB
MOV WORD PTR CCBPTR+2,SEG CCB
•
GET POINTER TO SCB
SET SOC BYTE AND CLEAR RESERVED BYTE
SET POINTER TO CCB
•
CCB
LDS
AX,CCBPTR
ASSUME
DS:CCBSEG
MOV WORD PTR CCWI,OFF01H
MOV WORD PTR CHIPTR,OFFSET CHI PC;
MOV WORD PTR CHIPTR+2,SEG CHI PC ;
MOV WORD PTR CCW2,OOOlH
,
MOV WORD PTR CH2PTR,OFFSET CH2PC;
MOV WORD PTR CH2PTR+2,SEG CH2PC
MOV WORD PTR CH2PC,0004H
GET POINTER TO CCB
SET CCWI AND CH. I BUSY FLAG
SET POINTER TO FIFTH BYTE OF CIB
(HAS STARTING ADDRESS FOR CH. 1)
SET CCW2 AND CLEAR CH. 2 BUSY FLAG
SET POINTER TO CH. 2 STARTING ADDRESS
SET CH. 2 STARTING ADDRESS
CIB
ASSUME DS:CIBSEG
MOV
AX,CIBSEG
MOV
OS, AX
MOV WORD PTR CIBCMD,OOOOH
MOV WORD PTR CMDSEM,OOOOH
MOV WORD PTR CHIPC,OOOOH
MOV
IOPBOFF,OFFSET IOPB
MOV
IOPBSG,SEG IOPB
•
GET POINTER TO CIB
CLEAR CIB COMMAND AND CIB STATUS BYTES
••• AND SEMAPHORES
SET CH. I STARTING ADDRESS
SET IOPB POINTER
$EJECT
•
iSBC 215
•
•
HCS-86 MACRO ASSEMBLER
CONTROLLER RESET ROUTINE
LOC
LINE
0060
0070
0072
0075
0078
007e
0070
DOlE
0080
0083
0085
0086
0088
0089
008B
OBJ
B8---8E08
B90DOO
BBDOOO
C7070000
43
43
EOF8
BA3506
B002
EE
BODO
EE
BOOI
EE
a08C B8---008F 8ED8
0091 890010
0094 F8
0095 F6060100FF
009A 7403
G09C EOF7
•
Appendix A
009E
009F
OOAO
OOAI
GOA2
GOA3
GOA4
F9
IF
5A
59
58
58
CB
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=I
R =I
=1
=1
=1
=1
=1
=1
=1
=1
=1
"I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
481
482
483
484
485
486
487
488
489
490
491
492
10/27/80
9
SOURCE
CLEAR OUT DATA SEGMENT
CLRLP:
ASSUHE DS:DATASEG
HOV
AX,DATASEG
HOV
DS,AX
MOV
CX,(OFFSET ENDDAT)/2
HOV
BX,OOOOH
MOV WORD PTR [BX],OOOOH
INC
BX
INC
BX
LOOPNE
CLRLP
493
494
495
496
497
498
499
500
5 01
502
503
504
505
506
507
508
509
5 10
51 1
512
511
514
515
516
5I7
518
519
520
521
522
523
524
525
PAGE
GET POINTER TO DATA SEGMENT
GET COUNT (II WORDS IN DATA SEGMENT)
CLEAR INDEX REGISTER
CLEAR NEXT WORD IN DATA SEGHENT
POINT TO NEXT WORD
DONE?
NO--CLEAR ANOTHER WORD
YES--INITIALIZE COMMUNICATION LINKS
OUTPUT RESET/CLEAR RESET/CHANNEL ATTENTION TO CONTROLLER
!10V
NOV
OUT
~10V
OIJT
XOV
OUT
ASSUHE
110V
lIOV
RSSLP:
REsnN:
DX, WUA
AL,0211
DX,AL
AL,OOH
OX,AL
AL,Ol11
OX,AL
DS:CCBSEG
AX,CCBSEG
DS,AX
HOV
CLC
TEST
CX,IOOOH
BSYFLGI,OOFFH
JZ
RESDN
LGOPNE
Rl'SLP
STC
POP
POP
POP
POP
POP
RET
ns
DX
CX
EX
AX
526
527
RfS215
528 +1
529 +1
$ I NCL un E ( : F I : I NI TE X. IIMD )
SEJECT TITLE(INITIALIZATION ROUTINE)
GET WAKE-UP I/O PORT ADDRESS
GET RESET CO!IHAND BYTE
OUTPUT TO WAKE-UP I/O PORT
GET CLEAR RESET COMHAIIIl BYTE
OUTPUT TO WAKE-UP I/O PORT
GET CHANNEL ATTENTION COMMAND BYTE
OUTPUT TO WAKE-UP I/O PORT
GET POINTER TO CCB
(OTHER [MPLEMENTATIONS OF RES215 COULD
INITIALIZE OTHER DEV ICES WHILE THE
iSBC 21 '; DOES ITS RESET SEQUENCE HERE)
SET TIME-OUT COUNTER
CLEAR CARRY FLAG
CHECK CH. I BUSY FLAG:
ZERO FLAG = BSYFLGI
FFH
BUSY FLAG CLEARED?
YES--RETURN CARRY CLEAR
NO--DECREHENT COUNTER
IF ex = 0, THEN BSYFLGI NEVER GOT
CLEARED, SO SET CARRY FLAG
RESTORE REGISTERS
RETURN
ENDP
•
•
A-15
iSBC 215
Appendix A
~CS-86
LOC
MACRO ASSEMBLER
OBJ
00A5
ODA5
OOA6
OOA7
OOAA
OOAC
00B2
00S7
50
IE
B8---8ED8
C70608000000
C6060BOOOO
C7060COOOOOO
OOBO C7061400---00C3
00C9
OOCB
0000
0003
C7061200FBFF
BOOO
8306120008
A20AOO
E8ECOO
0006 7214
(JOD8 40
0009 3C04
OODS 75EE
0000
OOEO
00E2
{JOE4
OOEA
OGEC
OOED
OOP.E
A10800
3COO
7508
C70608000100
EBDF
IF
58
CB
LINE
=1
=1
=1
=1
=1
=I
=1
=1
=1
=1
=1
=1
=1
=I
=1
=1
=1
=1
=1
=I
=1
=1
=1
=1
=I
=1
=1
R =1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=1
=1
=1
-I
=1
=1
=1
=1
=1
=1
=1
=1
=I
=I
=1
=1
=1
=I
=1
A-I6
10/27/80
INITIALIZATION ROUTINE
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
503
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588 +1
589 +1
PAGE
10
SOURCE
INITIALIZATION ROUTINE
•
INIT215 INITIALIZES THE iSSC 215 CONTROLLER BY LOADING PERTINENT INFORMATION ABOUT THE DISK DRIVE(S) ATTACHED.
-
IF A DRIVE THAT IS SPECIFIED AS PRESENT WILL NOT RESPOND,
IMMEDIATELY WITH THE CARRY FLAG SET.
INIT215 RETURNS
INPUT DATA:
DISK DRIVE INITIALIZATION TABLES, IN SEGMENT "INITBLSEG".
OUTPUT DATA:
CARRY FLAG
PUBLIC
ASSU~E
INIT215 PROC
PUSH
PUSH
INIT215
DS:IOPBSEG
FAR
MOV
AX
DS
AX,IOPBSEG
DS,AX
DEVCOD,OOH
FUNC,OOH
MODIFY,OOOOH
MOV
BUFSEG,INITBLSEG
}10V
HOV
MOV
~10V
MOV
MOV
INITLP: ADD
1IOV
CALL
BUFOFF,-8
AL,OOH
BUFOFF ,8
UNIT,AL
G0215
JC
INITDN
INC
eMP
lNZ
AX
AL,4
UHTLP
MOV
CNP
JNZ
HOV
JIIP
INITDN: POP
POP
RET
= 0 IF CONTROLLER INITIALIZED SUCCESSFULLY
= 1 IF INITIALIZATION ERROR
AX,DEVCOD
AL,O
INITDN
DEvcon,ol
INITLP
OS
AX
INIT215 ENDP
,
$INCLUDE(:FI:FORMAT.M1ID)
$E1ECT TITLE(FORMAT TRACK ROUTINE)
SAVE REGISTERS
GET POINTER TO IOPB
PUT IN OS REGISTER
WINCHESTER DRIVES INITIALIZED FIRST
SET IOPB FUNCTION BYTE ~ INITIALIZE
CLEAR ~ODIFIER (ENABLE RETRIES AND
INTERRUPT ON COMPLETION)
PUT INITIALIZATION TABLES' SEGMENT IN
IOPB DATA BUFFER POINTER
START INITIALIZE WITH UNIT 0
CLEAR UNIT COUNTER
POINT TO NEXT DRIVE's INITIALIZE TABLE
PUT UNIT INTO IOPB
DO INITIALIZE
(RETURNS CARRY FLAG SET OR CLEAR)
UNIT INITIALIZED?
NO--TERMINATE WITH CARRY BIT SET
YES--INCREMENT UNIT COUNTER
CHECK UNIT COUNTER (CLEARS CARRY)
LAST DRIVE INITIALIZED?
NO--INITIALIZE NEXT DRIVE
YES--FLOPPIES INITIALIZED YET?
•
•
YES--INITIALIZE FUNCTION FINISHED
NO---INITIALIZE FLOPPY DRIVES
RESTORE REGISTERS
RETURN
•
•
Appendix A
iSBC 215
•
MCI-86 MACRO ASSEMBLER
FORMAT TRACK ROUTINE
LOC
LINE
OBJ
=1
=1
=1
=1
=1
=1
=1
•
=1
=
1
=1
-I
=1
=1
=1
=1
=1
-I
=1
- 1
=1
=1
=1
-I
•
•
•
=1
-I
=1
OOEF
-I
OOEF 50
OOFO IE
OOF! B8---00F4 8ED8
00F6 8B460A
00F9 A30800
OOFC 8A4600
OOFF A20AOO
0102 8B4601
0105 A30EOO
0108 8A4603
010B A21000
010E 892E1200
0112 8306120004
0117 8CI61400
OIIB C6060B0002
0120 C7060COOOOOO
-I
=1
0126 E89900
=I
R =1
-I
- 1
=1
=1
-I
=1
=1
=1
=1
598
659
660 +1
661 +1
-I
-I
-1
-1
-I
-1
-I
=)
=)
=)
=)
=)
=)
=)
=)
=)
=)
DEVICE CODE
INTERLEAVE FACTOR
USER DATA BYTE 3
USER DATA BYTE
USER DATA BYTE
USER DATA BYTE 0
TYPE OF FORMAT
HEAD
CYLINDER
UNIT
OUTPUT DATA:
CARRY FLAG
- 0 IF TRACK FORMATTED SUCCESSFULLY
1 IF NON-RECOVERABLE ERROR OCCURRED
=
- INTERLEAVE FACTOR OF 1 IMPLIES SEQUENTIAL SECTOR NUMBERING.
- USER DATA BYTES 0 - 3 ARE REPLICATED THROUGHOUT THE DATA FIELD.
- INTERLEAVE TYPES:
00
NORMAL TRACK (ONLY FORMAT FOR FLOPPY)
40 = ALTERNATE TRACK (POINTED TO BY EXACTLY ONE DEFECTIVE TRACK,
CANNOT SUBSEQUENTLY BE FORMATTED DEFECTIVE)
80 = DEFECTIVE TRACK (DATA FIELD POINTS TO ALTERNATE TRACK)
- TO SET UP A POINTER TO AN ALTERNATE TRACK, SET:
USER DATA BYTE 0
ALTERNATE CYLINDER LOW BYTE
USER DATA BYTE
ALTERNATE CYLINDER HIGH BYTE
USER DATA BYTE
ALTERNATE HEAD
USER DATA BYTE
OOH
FMT215
644
-I
- I
-1
INPUT DATA:
BP + 10
BP + 9
BP + 8
BP + 7
BP + 6
BP + 5
BP + 4
BP + 3
BP +
BP
599
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
-I
-I
-I
FMTTRK SETS UP THE IOPB FOR A FORMAT TRACK FUNCTION, AND
INVOKES THE iSBC 215 CONTROLLER TO PERFORM THE OPERATION.
597
645
646
647
648
649
650
651
652
653
654
655
656
657
658
=1
0129 IF
012A 58
0128 CAOAOO
595
600
= I
FORMAT TRACK ROUTINE
593
594
1
- 1
- 1
=1
SOURCE
592
596
=1
=1
=1
=1
=1
=1
=1
11
PAGE
590
591
=1
=1
=1
=1
=
10/27/80
FMTDN:
,
FMT215
,
PUBLIC
ASSUME
FMT215
DS:IOPBSEG
PROC
FAR
PUSH
PUSH
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ADD
MOV
MOV
MOV
AX
AX,IOPBSEG
DS,AX
AX, [BP+I0J
DEVCOD,AX
AL, [BP J
UNIT,AL
AX,[BP+IJ
CYLNDR,AX
AL,[BP+3J
HEAD,AL
BUFOFF,BP
BUFOFF,4
BUFSEG,SS
FUNC,02H
MODIFY,OOOOH
CALL
G0215
POP
POP
RET
OS
SET FUNCTION = FORMAT
CLEAR MODIFIER (ALLOW ERROR RECOVERY
AND INTERRUPT ON COMPLETION)
START iSBC 215 AND WAIT FOR DONE
(RETURNS CARRY FLAG SET OR CLEAR)
RESTORE REGISTERS
AX
10
RETURN (AND POP INPUT DATA OFF STACK)
SAVE REGISTERS
OS
GET POINTER TO IOPB
GET DEVICE CODE INTO IOPB
GET UNIT NUMBER INTO IOPB
GET CYLINDER NUMBER INTO IOPB
GET HEAD INTO IOPB
GET POINTER TO FORMAT ARGUMENT LIST
INTO DATA BUFFER POINTER
ENDP
$INCLUDE(:Fl:RDWRT.MMD)
$EJECT TITLE(READ DATA ROUTINE)
A-17
iSBC 215
Appendix A
MCS-86 MACRO ASSEMBLF.R
READ DATA ROUTINE
LOC
LINE
OBJ
012E
012E
012F
0130
0133
0135
0138
013B
013E
0141
0144
0147
014A
0140
0150
0153
0156
0159
01SC
015 F
0162
0165
50
IE
B8---8ED8
8B460D
A30800
8A4600
A20AOO
8B4601
A30EOO
8B4603
A31000
8B4605
A31200
8B4607
A31400
8B4609
A31600
8B460B
A31800
C7060COOOOOO
0168 C6060BOO04
GI70 E84FOO
0173 IF
0174 58
0175 CAODOO
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=I
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=I
~I
=1
=1
=1
=1
=1
=1
=1
~1
=1
~1
=I
=1
~1
=1
=1
=1
=1
=1
=1
=1
=1
~I
A-18
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724 +1
10/27/80
PAGE
12
SOURCE
--------------------READ DATA
---------------------
•
RD215 SETS UP THE IOPB FOR A READ OPERATION, AND
INVOKES THE iSBC 215 TO PERFORM THE OPERATION.
INPUT DATA:
BP + 13 =)
BP + II =)
BP +
9 =)
7 =>
BP +
5 =)
BP +
4 ,=)
BP +
BP +
3 =)
1 =)
BP +
=)
BP
DEVICE CODE
BYTE COUNT HIGH WORD
BYTE COUNT LOW WORD
DATA BUFFER SEGMENT
DATA BUFFER OFFSET
SECTOR
HEAD
CYLINDER
UNIT
OUTPUT DATA:
CARRY FLAG
DATA BUFFER
= 0 IF TRANSFER OCCURRE 0 WITH NO OR RECOVERABLE ERROR
= 1 IF UNRECOVERABLE ERROR OCCURRED
FILLED IIITH DATA FROM DISK IF NO UNRECOVERABLE ERROR
-----------------------------------------------------------------------------
RD21S
PUBLIC
ASSUME
RD215
DS:IOPBSEG
PROC
FAR
PUSH
AX
PUSH
OS
HOV
AX,IOPBSEG
HOV
DS ,AX
MOV
AX, [BP+13]
MOV
DEVCOD,AX
:.IOV
AL, [llP]
UNIT,AL
MOV
AX, [BP+I]
HOV
CYLNDR,AX
ti0V
110V
AX,iBP+3]
tlOV WORD PTR HEAD,AX
HOV
AX,iBP+5]
tlOV
BUFOFF,AX
MOV
AX, [llP+7]
tlDV
BUFSEG,AX
MOV
AX, [BP+9]
MOV WORD PTR REQCNT,AX
AX, [lIP+ll]
MOV
tlOV WORD PTR REQCNT+2,AX
[10 V
llODl FY, GOOOH
RD215
'10V
CALL
FUNC,04H
G0215
POP
POP
RET
OS
AX
13
ENDP
SEJECT TITLE(WRITE DATA ROUTINE)
SAVE REGISTERS
•
GET POINTER TO lOPS
GET DEVICE CODE INTO IOPB
GET UNIT INTO IOPB
GET CYLINDER INTO
[0
PB
GET HEAD AND SECTOR INTO
IOPB
GET DATA BU FF ER POINTER INTO 10 PB
GET BYTE COUNT INTO IOPB
CLEAR HODIFIER (ENABLE INTERRUPT ON
COtlPL ET ION AND RETRIES)
SET PUNCTION = READ DATA
START FUNCTION AND WAIT FOR COMPL ET ION
(RETURNS CARRY FLAG SET OR CLEAR)
RESTORE REGISTERS
POP PARAMETERS OFF STACK AND RETURN
•
•
•
iSBC 215
•
Appendix A
MCS-86 MACRO ASSEMBLER
WRITE DATA ROUTINE
LOC
LINE
OBJ
=1
=1
-I
-I
-I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=I
•
•
•
•
=1
=1
=1
=1
=1
=1
=1
=I
0178
0178
0179
017A
017D
Ol7F
0182
0185
0188
Ol8B
018E
0191
0194
0197
019A
0190
OIAO
OlA3
0lA6
OlA9
OIAC
OlAF
50
IE
B8---8EDS
8B460D
A30800
8A4600
A20AOO
8B4601
A30EOO
8B4603
A31000
8B4605
A31200
8B4607
A31400
8B4609
A31600
8B460B
A31800
C7060COOOOOO
0lB5 C6060B0006
OIBA E80500
01 BD IF
OIBE 58
OIBF CAODOO
=1
=1
=1
=1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788 +1
789 +1
10/27/80
PAGE
13
SOURCE
WRITE DATA
WRT215 SETS UP THE IOPB FOR A WRITE OPERATION, AND
INVOKES THE iSBC 215 TO PERFORM THE OPERATION.
INPUT DATA:
BP +
BP +
BP +
BP +
BP +
BP +
BP +
BP +
BP
->
=>
9->
7 =>
5 =>
4 =>
3 =>
I·>
=>
13
II
DEVICE CODE
BYTE COUNT HIGH WORD
BYTE COUNT LOW WORD
DATA BUFFER SEGMENT
DATA BUFFER OFFSET
SECTOR
HEAD
CYLINDER
UNIT
DATA BUFFER CONTAINS INFORMATION TO BE WRITTEN TO DISK
OUTPUT DATA:
CARRY FLAG
PUBLIC
,
WRT215
~SSUME
WRT215
DS:IOPSSEG
PROC
FAR
PUSH
PUSH
MOV
MOV
MOV
MOV
rIO V
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
WRT215
=
=
0 IF TRANSFER OCCURRED W~TH NO OR RECOVERABLE ERROR
I IF UNRECOVERABLE ERROR OCCURRED
AX
DS
AX,IOPBSEG
DS,AX
AX, [BP+13]
DEVCOD,AX
AL, [BP]
UNIT,AL
AX,[BP+I]
CYLNDR,AX
AX, [BP+3]
WORD PTR HEAD,AX
AX,[BP+5]
BUFOFF,AX
AX, [BP+7]
BUFSEG,AX
AX,[BP+9]
WORD PTR REQCNT,AX
AX, [BP+II]
WORD PTR REQCNT+2,AX
MODIFY,OOOOH
MOV
CALL
FUNC,06H
G0215
POP
POP
RET
OS
AX
13
SAVE REGISTERS
GET POINTER TO IOPB
PUT DEVICE CODE IN IOPB
GET UNIT INTO lOPS
GET CYLINDER INTO IOPB
GET HEAD AND SECTOR INTO IOPB
GET DATA BUFFER POINTER INTO IOPB
GET BYTE COUNT INTO IOPB
CLEAR MODIFIER (ENABLE INTERRUPT ON
COMPLETION AND RETRIES)
SET FUNCTION = WRITE DATA
START iSBC 215 AND WAIT FOR DONE
(RETURNS WITH CARRY SET OR CLEAR)
RESTORE REGISTERS
POP PARAMETERS OFF STACK AND RETURN
ENDP
$INCLUDE(:FI:CORE.MMD)
$EJECT TITLE(START FUNCTION AND WAIT FOR COMPLETION)
A-19
iSBC 215
Appendix A
MCS-86 MACRO ASSEMBLER
START FUNCTION AND WAIT FOR COMPLETION
LOC
LINE
OBJ
0le2
0lC2
OlC3
0lC4
0lC7
0lC9
OleA
50
52
BA3506
BOOI
EE
F80800
oleo 7303
OICF E82900
0102 SA
58
0104 C'l
o I·D3
=1
=1
=1
=1
=1
=1
=1
=1
=I
=I
=1
=1
=1
=1
=I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=I
=1
=1
=1
=1
=1
=1
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826 +1
10/27/80
PAGE
14
SOURCE
START FUNCTION AND WAIT FOR COMPLETION
•
THIS ROUTINE GIVES A CHANNEL ATTENTION (WAKE-UP) TO THE iSBC 215 AND
WAITS FOR THE FUNCTION SPECIFIED (BY THE CALLING PROCEDURE) TO FINISH.
IF AN ERROR OCCURRED, THE ERROR HANDLER IS INVOKED.
INPUTS:
NONE
OUTPUTS:
CARRY FLAG:
G021S
PROC
NEAR
PUSH
PUSH
MOV
AX
OUT
CALL
JNC
AL,OIH
OX,AL
WAIT215
DONE
CALL
ERROR
POP
POP
RET
AX
HOV
DONE:
OX
OX, \,UA
ox
= 0 IF NO ERROR OR A RECOVERABLE ERROR OCCURRED
= I IF UNRECOVERABLE ERROR OCCURRED.
SAVE REGISTERS
GET ADDRESS OF WAKE-UP I/O PORT
GET WAKE-UP COMMAND BYTE
GIVE WAKE-UP TO iSBC 215
WAIT FOR FUNCTION COMPLETE
ERROR?
NO--RETURN
YES--CALL ERROR HANDLER (RETURNS WITH
CARRY FLAG SET OR CLEAR)
RESTORE REGISTERS
•
RETURN
;
GO 2 I 5
ENDP
SEJECT TITLE(WAIT FOR FUNCTION COMPLETE ROUTINE)
•
•
A-20
Appendix A
iSBC 215
•
LOC
LINE
OBJ
-1
-I
-I
-I
=1
=1
=1
=1
=1
-1
-I
-1
=1
=1
= I
=1
= I
=1
=1
=1
=1
-I
•
•
•
•
=1
=1
-I
=1
=1
-1
=1
=1
0lD5
0lD5
01 D6
0lD7
0108
OIDB
OIDD
OlEO
OIEI
0lE2
0lE3
0lE7
50
53
IE
BB---8EDB
BBFFFF
FB
F4
43
81E30300
F607FF
-1
-1
-I
=1
R =1
-I
=1
-I
-I
-I
=1
-I
=1
=1
OlEA 74F6
-I
-I
OIEC 7906
=1
-I
01EE
OIFO
OlF3
OlF4
OlF7
01F8
OlF9
01FA
-I
-I
8A07
A21800
F9
C60700
IF
5B
58
C3
10/27/80
WAIT FOR FUNCTION COMPLETE ROUTINE
MCS-86 MACRO ASSEMBLER
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
-1
877
-I
878
879
880
881
882
883
884
885
886 +1
887 +1
-I
=1
=1
=1
=1
=1
=1
PAGE
15
SOURCE
WAIT FOR FUNCTION COMPLETE
NORMALLY, THIS WAIT ROUTINE WOULD TRAP TO THE SYSTEM DISPATCHER/
SCHEDULER TO ALLOW ANOTHER TASK TO EXECUTE WHILE THE iSBC 215 COMPLETED
ITS FUNCTION.
HOWEVER, FOR THIS EXAMPLE, THE ROUTINE SIMPLY WAITS FOR
THE INTERRUPT SERVICE ROUTINE TO LOAD THE OPERATION COMPLETE STATUS
FROM THE CIB OPERATION STATUS INTO THE DATA SEGMENT.
IF AN ERROR
OCCURRED, THE STATUS IS AVAILABLE THERE FOR SUBSEQUENT PROCESSING BY
AN ERROR HANDLER.
INPUT DATA:
OPERATION COMPLETE STATUS FROM THE CIB, COPIED INTO THE DATA SEGMENT
BY THE INTERRUPT ROUTINE
OUTPUT DATA:
OPERATION COMPLETE BYTE
CARRY FLAG
CLEARE 0
0 IF NO ERROR
=
= 1 IF ERROR OCCURRED
COpy OF CIS OPERATION STATUS
IN "LSTST5" IF ERROR OCCURRED
( OPERATION COllPLETE BYTE AND "LSTSTS" ARE IN SEGMENT "DATASEG"
ASSUME
WAIT215 PROC
PUSH
PUSH
PUSH
MOV
HOV
HOV
STI
HLT
liAITLP: INC
AND
TEST
DS:DATASEG
NEAR
AX
BX
OS
BX,DATASEG
DS,BX
BX,-I
BX
BX,0003H
BYTE PTR [BX],OFFH
JZ
WAITLP
JNS
WAlTON
MOV
AL, [BX]
HOV
LSTSTS,AL
STC
WAlTON: MOV BYTE PTR [BX] ,OOH
DS
POP
POP
BX
POP
AX
RET
SAVE REGISTERS
GET POINTER TO DATA SEGHENT
INITIALIZE INDEX REGISTER
MAKE SURE INTERRUPT CAN GET THROUGH
***** WAIT FOR INTERRUPT *****
GET INDEX FOR NEXT UNIT
HASK UPPER BITS
OPERATION COMPLETE STATUS = OOH?
(SIGN FLAG - BIT 7 OF OP. STATUS,
TEST INSTR. CLEARS CARRY FLAG)
STATUS <> DOH (OPERATION COMPLETE)?
NO--CHECK NEXT UNIT
YES--ERROR OCCURRED DURING FUNCTION?
NO--RETURN WITH CARRY FLAG CLEAR
YES--SAVE CIB OP. STATUS IN "LSTSTS"
SET CARRY FLAG TO INDICATE ERROR
CLEAR OPERATION COMPLETE BYTE
RESTORE REGISToRS
RETURN
WAIT215 ENDP
$INCLUDE(:Fl:ERROR.MMD)
$EJECT TITLE(ERROR HANDLER)
A-21
iSBC 215
Appendix A
MCS-86 MACRO ASSEMBLER
ERROR HANDLER
LOC
LINE
OBJ
~1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
-1
01FB
01FB
OlFC
OIFD
0200
0202
0205
0206
0209
020A
0210
0216
021B
50
IE
B8---8ED8
A11200
50
A11400
50
C70612000COO
C7061400---C6060BOOOI
C7060COOOOOO
0221
0224
0225
0228
0229
022C
022F
0231
0232
0235
0237
E89EFF
58
A31400
58
A31200
B8---8ED8
F8
A01800
2440
7401
0239
023A
023B
023C
F9
IF
58
C3
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
R -"1
=1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=1
=1
=1
R =1
=1
= I
=1
=1
=1
=1
= I
=1
: I
=1
=1
=1
=1
A·22
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
PAGE
16
SOURCE
ERROR HANDLER
•
THIS ROUTINE IS SYSTEM DEPENDENT.
IN THIS EXAMPLE, THE ERROR INFORMATION FROM THE CONTROLLER IS READ INTO SOFTWARE REGISTERS IN DATASEG,
WHERE IT CAN BE EXAMINED. MORE SOPHISTICATED SYSTEMS MIGHT LOG THE
ERRORS TO DETERMINE WHEN A TRACK IS GOING BAD, FOR EXAMPLE.
- THE TRANSFER STATUS FUNCTION WILL NOT RETURN AN ERROR.
- THE UNIT NUMBER IN THE IOPB IS NOT CHANGED, SO THAT THE OPERATION COMPLETE
STATUS FOR THE TRANSFER STATUS FUNCTION WILL BE POSTED AGAINST THE SAME
UNIT AS CAUSED THE ERROR.
INPUT DATA:
CIB OPERATION STATUS
IN I'LSTSTS'! IN DATA SEGMENT
OUTPUT DATA:
ERROR STATUS FROM CONTROLLER
CIB OPERATION STATUS
CARRY FLAG
ASSUME
ERROR
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950 +1
951 + 1
10/27/80
NEAR
PUSH
PUSH
MOV
MOV
MOV
PUSH
MOV
PUSH
MOV
MOV
MOV
MOV
AX
OS
AX,IOPBSEG
DS,AX
AX,BUFOFF
AX
AX,BUFSEG
AX
BUFOFF,OFFSET ERRSTS
BUFSEG,DATASEG
FUNe,GIH
MODIFY,GOOOH
CALL
POP
MOV
POP
G021S
AX
BUFSEG,AX
AX
BUFOFF,AX
AX,DATASEG
DS, AX
MOV
MOV
CLC
MOV
AND
JZ
STC
SFTERR: POP
POP
RET
ERROR
DS:IOPBSEG
PROC
flO V
IN DATA SEGMENT
IN "LSTSTS" IN DATA SEGMENT
= 0 IF SOFT (RECOVERABLE) ERROR
z
1 IF HARD (UNRECOVERABLE) ERROR
AL,DS:LSTSTS
AL,40H
SFTERR
DS
AX
ENDP
$INCLUDE(:FI:INTRPT.MMD)
$EJECT TITLE(INTERRUPT SERVICE ROUTINE)
SAVE REGISTERS
•
GET POINTER TO IOPB
SAVE IOPB DATA BUFFER POINTER
GET POINTER TO DATA SEGMENT ERROR
STATUS REGISTERS
SET FUNCTION = TRANSFER STATUS
CLEAR MODIFIER (ENABLE INTERRUPT ON
COMPLETION AND RETRIES)
START FUNCTION AND WAIT FOR COMPLETE
RESTORE IOPB DATA BUFFER POINTER
•
GET POINTER TO DATA SEGMENT
CLEAR CARRY FLAG
GET OLD (ERROR) CIB OPERATION STATUS
CHECK HARD ERROR BIT
HARD ERROR BIT SET?
NO--LEAVE CARRY FLAG CLEAR
YES--SET CARRY FLAG
RESTORE REGISTERS
•
•
iSBC 215
•
MCS-86 MACRO ASSEMBLER
INTERRUPT SERVICE ROUTINE
LOC
LINE
DB]
023D
•
•
023D
023E
023F
0240
0241
53
FE
50
0242
0245
0247
024A
024e
0251
0253
0257
0259
025B
025D
025F
R8---8ED8
AOOI00
BADO
C606030000
8AD8
81E33000
DIEB
DIEB
DIEB
DIEI
250600
0262
DIED
52
1E
0264 03D8
0266 88---0269 8ED8
026~ 8817
026D BA5063
0270 ROO2
0272 EF
0273 1 F
0274 SA
027\ 58
0276 FA
•
•
Appendix A
0277
0279
027B
027C
B020
E6CO
58
CF
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
R =1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019 +1
1020
1021
10/27/80
17
PAGE
SOURCE
INTERRUPT SERVICE ROUTINE
THIS ROUTINE SERVICES THE INTERRUPT GENERATED BY THE iSBC 215 UPON
OPERATION COMPLETE, SEEK COMPLETE, OR DISK PACK CHANGE.
IT COPIES THE
CIB OPERATION STATUS INTO ONE OF FOUR BYTES ASSOCIATED WITH EACH OF
THESE EVENTS.
IT IS ASSUMED THAT SYSTEM PROGRAMS MAKE USE OF THE
INFORMATION TO RESUME TASKS, HANDLE ERROR LOGGING/RECOVERY, AND KEEP
FOR THIS PROGRAMMING EXAMPLE, ONLY
TRACK OF DIRECTORY INFORMATION.
THE OPERATION COMPLETE BYTES ARE USED.
-
THE SYSTEM INTERRUPTS ARE CONFIGURED BY EXTERNAL PROGRAMS.
INTI15
PUBLIC
INT215
PROC
FAR
STI
PUSH
PUSH
PUSH
PUSH
ASSUME
MOV
:1OV
MOV
MOV
:IOV
110 V
AND
SHR
SHR
SHR
SHR
AND
US:CIBSEG
AX,CIBSEG
DS,AX
AL,OPSTS
DL,AL
5T5SFll,00H
BL,AL
BX,0030H
BX,I
BX ,I
BX ,I
BX,I
AX,0006H
SHL
AX,I
BX,AX
DS:DATASEG
AX,DATASEG
NOV
DS, AX
?10V
[BX],DL
DX,WUA*16
GET POINTER TO CIB
GET CIB OPERATION STATUS
SAVE IT
CLEAR eIR STATUS SEMAPHORE
MOVE IT TO INDEX REGISTER
MASK ALL BITS EXCEPT UNIT NUMBER
SHIFT UNIT NUMBER TO BITS 0 AND 1
MASK ALL BITS EXCEPT SEEK COMPLETE
AND PACK CHANGE
SHIFT LEFT TO GET OFFSET INTO PROPER
BYTE IN DATA SEGMENT
COMBINE WITH UNIT IN INDEX REGISTER
GET POINTER TO DATA SEGMENT
'10 V
AL,02H
nUT
DX,AL
MOVE OPERATION STATUS TO DATA SEGMENT
GET POINTER TO I/O WAKE-UP ADDRESS
GET CLEAR INTERRUPT COMMAND BYTE
OUTPUT TO iSBC 215
POP
POP
POP
eLI
os
RESTORE REGISTERS
DX
BX
MOV
OUT
POP
IRET
,
ENABLE HIGHER PRIORITY INTERRUPTS
SAVE REGISTERS
ox
os
ADD
ASSUME
,·10 V
~'10V
INT215
AX
BX
AL,20H
OCOH,AL
AX
DISABLE INTERRUPTS FOR RESTORE
(RESTORATION OF INTERRUPT LOGIC STATE
IS SYSTEM DEPENDENT. THIS EXAMPLE USES
THE iSBC 86/12A CPU.)
'"
GET END-OF-INTERRUPT COMMAND
" , OUTPUT EOI COMMAND TO 8259
INTERRUPT RETURN ENABLES
INTERRUPTS
ENDP
SBC215DRIVER
ENDS
END OF iSBC 215 DRIVER CODE
$TITLE(SYM80L TABLE AND CROSS REFERENCE)
END
END OF PROGRAMMING EXAMPLE
A-23
iSBC 215
Appendix A
SYMBOL TABLE AND CROSS REFERENCE
KCS-86 MACRO ASSEMBLER
10/27/80
XREF SYMBOL TABLE LISTING
NAME
TYPE
??SEG
ACTCNT.
ACTCYL •
ACTHD
ACTSEC.
BSYFLGI
BSYFLG2
BUFOFF.
BUFSEG.
CCB
CCBPTR.
CCBSEC.
CCWI.
CCW2.
CHIPC
CHIPTR.
CH2PC
CH2PTR.
CIB
CIBCMD.
CIBSEG.
CLRLP
CMDSEM.
CONFIG.
CYLNDR.
DATASEG
DESCYL •
DESHD
DESSEG.
DEVGOD.
DONE.
ENDOAT.
ENDSTK.
ERROR
ERRSTS.
FMT215.
FMTDN
FUNG.
G02D
HEAD.
INIT215
INITBLSEG
INITDN.
INITLP.
INT215.
INTRCS.
INTRIP.
INTRPT.
IOPB.
IOPBOFF
IOPBSEG
IOPBse.
LSTSTS.
UODlFY.
NMRTRY.
OPCMP
OPCMPO.
OPCMPI.
OPCMP2.
OPCMP3.
OPSTS
PKCHG
PKCHGO.
PKCHG 1.
PKCIIG2.
PKCIIG3.
RD2l5
REQCNT.
RES215.
RESDN
RESLP
SBG215DRIVER.
SCB
SCBSEG.
SECTOR.
SEGOOOO
S EG~! ENT
V DWORD
V WORD
v BYTE
V BYTE
v BYTE
v BYTE
v WORD
V WORD
L FAR
V DWORD
SEGHENT
V BYTE
V BYTE
L FAR
v DWORD
L FAR
V DWORD
L FAR
v BYTE
SEGMENT
L NEAR
V BYTE
L FAR
V WORD
SEG'IENT
V WORD
v BYTE
V BYTE
V WORD
L NEAR
L FAR
L FAR
L NEAR
V WORD
L FAR
L NEAR
V BYTE
L NEAR
V BYTE
L FAR
SEGMENT
L NEAR
L NEAR
L FAR
V WORD
v WORD
NUMBER
L FAR
A-24
V WORD
SEGMENT
v WORD
V BYTE
V WORD
V BYTE
V BYTE
v BYTE
v BYTE
v BYTE
v BYTE
V BYTE
v BYTE
V BYTE
V BYTE
v BYTE
v BYTE
L FAR
V DWORD
L FAR
L NEAR
L NEAR
SEGMENT
L FAR
SEGMENT
V BYTE
SEGIlENT
VALUE
0004H
0013H
0015H
0016H
0001H
0009H
0012H
0014H
OOOOH
0002H
OOOOH
0008H
0004H
0002H
OOOEH
OOOAH
OOOOH
OOOOH
0078H
n002H
OOOOH
OOOEH
OOOFH
00 II H
0012H
OOOSH
0lD2H
001AH
0040H
OIFBH
OOOCH
OOEFH
0129H
OOOBH
01C2H
OOIOH
00A5H
OOECH
OOCBH
023DH
0096H
0094H
G005H
OOOOH
OOOSH
OOOAH
0018H
OOOCH
0017H
OOOOH
OOOOH
0001H
0002H
0003H
0001H
000811
0008H
000911
OOOAH
OOOBII
012EH
OOII)H
OOOOH
009FH
0095!!
OOOOH
OOIIH
ATTRIBUTES, XRE FS
SIZE=OOOOH PARA PUBLIC
IOPBSEG 12911
DATASEG 31211
DATASEG 3 I 311
DATASEG 31411
CCBSEG 7911 512
CCBSEG 8511
IOPBSEG 13711 565 567 646 647 706 770 922 926 935
13811 563 648 708 772 924 927 933
IOPBSEG
CCBBEC 64 7711 454 455
SCBSEG 6411 454 455 459
7511 92 460 504 505
SIZE=OOI0H PARA
CCBSEG 7811 461
CCBSEG 8411 464
CIBSEG SO 11 01/ 462 463 476
CCBSEG 8011 462 463
CCBSEG 86 8911 465 466 467
CCBSEG 8611 465 466
10511
CIBSEG
CIB S EG 10611 474
1031/ 116 471 472 978 979
SIZE=0010H PARA
SBC215DRIVER 48811 491
CIBSEG 1081! 475
USERSEG PUBLIC 377 380/1 396
IOPBSEG
134/1 643 702 766
268 II 326 483 484 854 861 927 936 995 996
SEE=OOIAH PARA
30911
DATASEG
DATASEG 31011
DATASEG 31111
IOPBSEG 13011 559 577 580 639 698 762
SBC215DRIVER 816 82011
DATASEG 32411 486
STACK 36711 385
SBC215DRIVER 818 91611 948
DATASEG PUBLIC 278 30711 926
SBC2l5DRIVER PUBLIC 629 63211 658
SBC215DRIVER 654/1
IOPBSEG
13211 560 649 715 779 928
SBC2150RIVER 569 652 716 780 80811 824 931
IOPBSEG
13511 645 704 768
SBC215DRIVER PUBLIC 550 55311 586
SIZE=003FH PARA
17011 258 563
SBC215DRIVER 571 579 58211
SBC215DRIVER 56711 575 581
SBC215DRIVER PUBLIC 388 389 969 97111 1015
SEGOnOO 35511 389
SEGOaOO 354/1 3S8
34711 352
IOPBSEG 112 12711 477 478
CIBSEG 11211 477
SIZE=OOIEH PARA
113 12511 142 551 557 630 636 689 695 753 759 914 920
CIBSEG 11311 478
DATASEG 32011 876 939
IOPBSEG 13311 561 650 713 777 929
DATASEG 31511
DATASEG PUBLIC 278 28211
DATASEG 28311
DATASEG 28411
DATASEG 285 II
DATASEG 28611
CIBSEG
10711 981
DATASEG PUBLIC 278 29811
DATASEG 29911
DATASEG 30011
DATASEG 30111
DATASEG 302#
SBC215DRIVER PUBLIC 688 69tH 722
IOPBSEG 13911 710 712 774 776
SBC215DRIVER PUBLIC 436 43811 526
SBC215DRIVER 514 519 II
SBC21SDRIVER 512/1 516
SIZE=027DH PARA
400# 402 1017
SCBSEG 61#
SIZE=0006H PARA ABS
5911 66 450 451
IOPBSEG 13611
SIZE=0098H PARA ABS
34911 357 378
PAGE
18
•
•
•
•
•
Appendix A
iSBC 215
•
MCS-86 MACRO ASSEMBLER
NMIE
SFERST.
SFTERR.
SKCMP
SKCMPO.
SKCMPI.
SKCMP2.
SKCMP3.
SOC
STACK
STSSEH.
UNIT.
USERSEG
WAIT215
IlAITDN.
WAITLP.
WRT215.
WUA
SYMBOL TABLE AND CROSS REFERENCE
TYPE
VALUE
ATTRIBUTES, XREFS
V BYTE
NEAR
V BYTE
V BYTE
V BYTE
V BYTE
V BYTE
V BYTE
SEGMENT
V BYTE
V BYTE
SEGMENT
L NEAR
L NEAR
L NEAR
L FAR
NUMBER
OOOEH
023AH
0004H
0004H
0005H
0006H
0007H
OOOOH
DATASEG 30811
SBC215DRIVER 941 94411
DATASEG PUBLIC 278 29011
DATASEG 29111
DATASEG 29211
DATASEG 29311
DATASEG 29411
SCBS!:C 6211 453
SIZE~0040H PARA
CIBSEG 1091/ 983
IOPBSEG 131# 568 641 700 764
375# 398
SIZE=0022H PARA
SBC215DRIVER 815 856# 884
SBC215DRIVER 873 878#
SBC215DRIVER 866# 871
SBC215DRIVER PUBLIC 752 755# 786
5711 59 497 812 999
L
0003H
OOOAH
0lD5H
O1F4H
01E2H
0178H
06351l
10/27/80
PAGE
19
ASSEMBLY COMPLETE, NO ERRORS FOUND
•
•
•
•
A-25/A-26
•
•
•
•
•
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