143154 001_i SBX_488_GPIB_Multimodule_Hardware_Ref_Jun81 001 I SBX 488 GPIB Multimodule Hardware Ref Jun81

143154-001_iSBX_488_GPIB_Multimodule_Hardware_Ref_Jun81 143154-001_iSBX_488_GPIB_Multimodule_Hardware_Ref_Jun81

User Manual: 143154-001_iSBX_488_GPIB_Multimodule_Hardware_Ref_Jun81

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iSBX 488™ GENERAL PURPOSE
INTERFACE BUS (GPIB)
MULTIMODULETM BOARD
HARDWARE REFERENCE MANUAL
Order Number: 143154-001

REV.

PRINT
DATE

REVISION HISTORY

6/81

Original Issue

-001

Additional copies of this manual or other Intel literature may be obtained from:
Literature Department
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
The information in this document is subject to change without notice.
Intel Corporation makes no warranty of any kind with regard to this material, including, but
not limited to, the implied warranties of merchantability and fitness for a particular purpose.
Intel Corporation assumes no responsibility for any errors that may appear in this document.
Intel Corporation makes no commitment to update nor to keep current the information
contained in this document.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry
embodied in an Intel product. No other circuit patent licenses are implied.
Intel software products are copyrighted by and shall remain the property of Intel
Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel's software
license, or as defined in ASPR 7-1D4.9(a)(9).
No part of this document may be copied or reproduced in any form or by any means without
the prior written consent of Intel Corporation.
The following are trademarks of Intel Corporation and its affiliates and may be used only to
identify Intel products:
BXP

CREDIT
i

ICE
iCS
im
Insite
Intel

Intel
Intelevision
Intellec
iRMX
iSBC
iSBX
Library Manager
MCS

Megachassis
Micromap

Multibus
Multimodule
PROMPT
Promware
RMX/HO
System 2000
UPI
.uScope

and the combination of ICE, iCS, iRMX, iSBC, iSBX, MCS, iMMX or RMX and a numerical
suffix.

A812/1282/1.SK NeG

PREFACE

This manual provides general information, preparation for use instructions,
programming information, principles of operation and service information for the
iSBX 488 GPIB Multimodule Board. Additional information is available in the
following publications:
•
•
•
•

•

Intel iSBX Bus Specification, Order Number 142686.
Intel Multibus Specification, Order Number 9800683.
Using the 8292 GPIB Controller, Application Note AP-66.
IEEE Standard Digital Interface for Programmable Instrumentation, Order
Number IEEE Std 488-1978. Published by the Institute of Electrical &
Electronics Engineers, Inc. Address: 345 East 47th Street, New York, N.Y.
10017.
Intel Component Data Catalog

iii

•

CONTENTS

CHAPTER 1
GENERAL INFORMATION

PAGE

Introduction ....................................
Description .....................................
Documentation & Equipment Supplied ..........
Specifications ...................................

1-1
1-1
1-2
1-2

CHAPTER 2
PREPARATION FOR USE
Introduction .................................... 2-1
Unpacking & Inspection ........................ 2-1
Installation Considerations ..................... 2-1
Power & Cooling Requirements ................. 2-1
Physical Dimensions . . . . .. . .. . . . . . . . . . . .. . . . . .. 2-1
Installation Procedure .......................... 2-1
Jumper Configurations ......................... 2·3
iSBX Connector Pin Assignments (PI) .......... 2-4
iSBX Connector AC & DC Signal Characteristics 2-4
GPIB Connector Pin Assignments (Jl) ... . . . . .. 2·4
GPIB AC & DC Signal Specifications .......... 2-4
Connector & Cable Information ................ 2-7
Installation Summary ......................... 2-10

CHAPTER 3
PROGRAMMING INFORMATION
Introduction .................................... 3-1
iSBX 488 Multimodule Board Protocol .......... 3-1
iSBX 110 Port Addressing ...................... 3-1
8291A Registers ................................ 3-2
Data Registers ................................. 3-2
Interrupt Registers ............................ 3-2
Status Bits .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
Serial Poll Registers .......................... 3-4
Address Registers ............................. 3-5
Command Pass Through Register ............ 3-6
Auxiliary Mode Register ...................... 3-7
End Of Sequence Register .................... 3-9
8292 Programming ............................ 3-10
8292 Registers ................................. 3-11
Interrupt Status Register .................... 3-11
Interrupt Mask Register ..................... 3-11
Controller Status Register ................... 3-12
GPIB Status Register ........................ 3-12
Event Counter Register ...................... 3-12
Event Counter Status Register ............... 3-12
Time Out Register ........................... 3-13
Time Out Status Register .................... 3-13
Error Flag Register .......................... 3-13
Error Mask Register ......................... 3-14
Command Field Register ...... . . . . . . . . . . . . .. 3-15

PAGE
8292 Operation Commands ....................
8292 Utility Commands ........................
8292 Interrupts ................................
8282 General Purpose Port .....................
Board Power OnlReset ........................
Board Initialization ............................
Software Drivers ...............................

3-15
3-16
3-19
3-19
3-19
3-20
3-21

CHAPTER 4
PRINCIPLES OF OPERATION
Introduction ....................................
Functional Description ..........................
iSBX Bus Interface ...........................
Control Lines ...............................
Command Lines ..........................
DMA Control Lines .......................
Initialize Line ............................
System Control Line ......................
Address and Chip Select Lines ...........
Address Lines ............................
Chip Select Line ..........................
Data Lines ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interrupt Lines .............................
Option Lines .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power Lines ................................
110 Command Operations ..................
1/0 Read ...................................
1/0 Write ...................................
Direct Memory Access ........................
GPIB Interface Functions . . . . . . . . . . . . . . . . . . ..
Coding Logic .................................

4-1
4-1
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-2
4-3
4-3
4-4
4-4
4-5

CHAPTER 5
SERVICE INFORMATION
Introduction ....................................
Service and Repair Assistance ..................
Replacement Parts ..............................
Service Diagrams ...............................

APPENDIX A
PL/M 80 SOFTWARE
DRIVER LISTING EXAMPLE
INDEX

5-1
5-1
5-1
5-1

TABLES

TABLE
1·1
2·1
2·2
2·3
2·4
2·5
2·6
2·7
2·8
2·9

TITLE

PAGE

iSBX 488 Multimodule Board
Specifications ......................
Address Jumper Configurations ........
iSBX 488 Jumper Configurations
Summary ..........................
iSBX Connector Pin Assignments ......
iSBX Connector Signal Descriptions '"
iSBX Multimodule Board I/O DC
Specifications (P1) . . . . . . . . . . . . . . . ..
iSBX Multimodule Board I/O
AC Specifications ..................
GPIB Connector (J1) Pin Assignments
GPIB Connector Signal Descriptions ...
GPIB AC Timing Specifications ........

TABLE

1·2
2·4

2·10
2·11
3·1

2·4
2·5
2·5

3·2
3·3
3·4

2·5

3·5
3·6
3·7

2·7
2·7
2·8
2·9

5·1
5·2

TITLE

PAGE

GPIB Interface, J1 DC Specifications .. 2·9
Pin Correspondence ................... 2·10
110 Port Addresses & Chip Select
Assignments ....................... 3·1
8291A Registers ........................ 3·2
Interrupt Register Bit Identification .... 3·4
Defined/Undefined Commands
Received ... . . . . . . . . . . . . . . . . . . . . . . .. 3-6
Auxiliary Command Identification ..... 3·8
8292 Registers & Port Addresses ...... 3·10
Summary of 8292 Operation & Utility
Commands ........................ 3·18
Replacement Parts List ................ 5-2
Manufacturers' Names ................. 5·2

ILLUSTRATIONS

FIGURE
1·1
2·1
2·2
2·3
2·4
2·5
2·6
3·1
3·2
3·3
3·4

TITLE

PAGE

iSBX 488 GPIB Board ................. 1·1
Physical Dimensions ................... 2·2
Mounting Clearances ................... 2·2
Mounting Technique ................... 2·3
P1 Interface Timing Specifications ..... 2·6
GPIB AC Timing Waveforms .......... 2·8
iSBC 988 Cable Installation ........... 2·10
8292 Event Counter Block Diagram ... 3·13
8292 Timeout Counter Block Diagram 3·14
Register Read Without Utility
Command ......................... 3·17
Read GPIB Bus Status Register ....... 3·18

FIGURE
3·5
3·6
3·7
4·1
4·2
4·3
4·4
5·1
5·2

TITLE

PAGE

SPI Interrupt Logic ................... 3·19
System Controller ..................... 3·21
Non·System Controller ................ 3·22
iSBX 488 Multimodule Board Block
Diagram ........................... 4·1
I/O Read Timing ...................... 4·3
I/O Write Timing ...................... 4·3
DMA Read Timing ..................... 4·4
iSBX 488 Multimodule Board
Parts Location Diagram ..... . . . . .. 5·3
iSBX 488 Multimodule Board
Schematic Diagram ................ 5·5

CHAPTER 1
GENERAL INFORMATION

1-1. INTRODUCTION
The iSBX 488 GPIB Interface Multimodule Board
implements the 1978 IEEE Standard 488 bus, using
Intel Large Scale Integration (LSI) devices. The
board is designed to interface a host iSBC Single
Board Computer to one or more (up to 15) peripheral
devices via the General Purpose Interface Bus
(GPIB). The iSBX 488 Multimodule Board may reside directly on the component side of any iSBX
Multimodule compatible iSBC board, and is interfaced to and powered by the host board through the
iSBX connector (Figure 1-1).

performing the functional subsets allowed by the
IEEE-488 Standard. In general, these functions are
Acceptor Handshake, Listener Handshake, Talker,
Listener, Service Request, Remote-Local, Parallel
Poll, Device Clear & Device Trigger.

1-2. DESCRIPTION

The iSBX 488 Multimodule Board also utilizes an
Intel 8292 GPIB Controller in conjunction with the
8291A. The 8292 acts as a slave processor to the host
CPU thus performing the GPIB controller interface
function. The actual electrical interface between the
iSBX 488 Multimodule Board and the IEEE-488 bus
is performed by two Intel 8293 GPIB Transceivers.
These bidirectional drivers are specifically designed
for GPIB applications.

The iSBX 488 Multimodule Board utilizes several
Intel support devices to perform most of the processing associated with the IEEE-488 bus. The
8291A GPIB Talker/Listener device is used to
perform most of the interfacing between the host
single board computer and the external IEEE-488
bus. Its capabilities include but are not limited to

The iSBX 488 Multimodule Board may be interfaced
with the IEEE 488 bus by connecting to the iSBC
988, GPIB cable assembly, for connection to the
IEEE 488 bus. This flat cable is approximately onehalf meter long, and is terminated with a 26-pin edge
connector at one end and a 24-pin GPIB plastic
receptacle at the opposite end.

Figure 1-1. iSBX 488™ GPIB Board

1-1

General Information

iSBX488

The iSBX 488 Multimodule Board is shipped from
the factory with a corresponding set ofschernatic
diagrams. These diagrams should be inserted into
the back of this manual for future reference. See
section 5-4 for related information_

1-3. DOCUMENTATION & EQUIPMENT
SUPPLIED
The iSBX 488 Multimodule board is shipped with the
following documentation & equipment:
a.
b.
c.
d.

Schematic Diagram
1 Nylon Spacer (0.5 in. X 6/32 in.)
2 Nylon Screws (0.25 in. X 6/32 in.)
8 Jumper Receptacles

1-4. SPECIFICATIONS
Specifications of the iSBX 488 Multimodule Board
are provided in Table 1-1.

Table 1-1. iSBX 488 Multimodule™ Board Specifications
Vcc = +5 Vdc ± 5%
Icc = 600 Milliamps maximum

POWER REQUIREMENTS:
ENVIRONMENTAL REQUIREMENTS:
Operating Temperature:
Relative Humidity:
Heat Dissipation:

0° to 55° C
90% Maximum, non-condensing
45.9 Gram-Calories/minute (0.18 Btu/min)

PHYSICAL DIMENSIONS:
Width:
Length:
Height:
Weight:

9.40.cm
7.24 cm
2.04 cm
87.80 gm

Symbol
GPIB FUNGTION
Source Handshake ............................ (SH)
Acceptor Handshake .......................... (AH)
Talker ........................................ (T)
Extended Talker .............................. (TE)
Listener ....................................... (L)
Extended Listener ............................. (LE)
Service Request ............................... (SR)
Remote Local ................................. (RL)
Parallel Poll ............ ............... ........ (PP)
Device Clear .................................. (DC)
Device Trigger .......................... ...... (DT)
Control/er ................... ; ................... (C)
'

INTERFACE CONNECTORS.:
Interface
P1, iSBX
J1, GPIB

No of
Pins
36
26

(3.70
(2.85
(0.80
(3.10

in.)
in.)
in.)
oz.)
Subsets
SHO, SH1
AHO, AH1
TO through T8
TEO through TE8
LO through L8
LEO through LE8
SRO, SR1
RLO, RL 1
PPO, PP1", PP2
DCD, DC1, DC2
DTO,DT1
CO through C28

Pin Centers
in
mm
0.1
2.54
0.1
2.54

Mating Connectors

Intel 103059:001
3M 3462-'0001
AMP 88373-5
"The host processor must interpret the remote commands PPU, PPC, PPE and PPD and send local message, Ipe, to
the iSBX .488 board. Refer to Section 3-12, Parallel Poll Protocol.

1-2

CHAPTER 2
PREPARATION FOR USE

NOTE

2-1. INTRODUCTION
This chapter provides instructions for installing the
iSBX 488 Multimodule Board onto your host iSBC
Single Board Computer. Instructions for configuring
the Multimodule board jumpers are also given.
Board DC and AC operating characteristics are
specified in this chapter.

2-2. UNPACKING & INSPECTION
Inspect the shipping carton immediately upon
receipt for evidence of mishandling during transit. If
the shipping carton is severely damaged or waterstained, request that the carrier's agent be present
when the carton is opened. If the carrier's agent is
not present when the carton is opened and the contents are damaged, keep the carton and packing
material for the agent's inspection.
For repairs to a product damaged in shipment contact the Intel Product Service HOTLINE to obtain a
return authorization number and further instructions (see section 5-2). A purchase order will be
required to complete the repair. A copy of the
purchase order should be submitted to the carrier
with your claim.

2-3. INSTALLATION CONSIDERATIONS
The iSBX 488 board can be installed on any 8-bit or
8/16-bit iSBC board equipped with an iSBX Multimodule connector. Power requirements and operating temperature ranges are provided in Chapter 1,
Table 1-1.

2-4. POWER & COOLING REQUIREMENTS

In some card cage models, two slots are used
by the host iSBC & iSBX board combination.

2-6. INSTALLATION PROCEDURE
The iSBX 488 Multimodule Board can be easily
installed without special equipment or tools. The
following procedure outlines iSBX 488 Multimodule
Board installation:

Host iSBC board must be removed from
chassis or card cage for proper installation.
Tum off power before removal.

Locate pin 1 on the host iSBX connector.
Similarly, locate pin 1 on the iSBX 488 Multimodule Board iSBX connector.

Carefully match the connectors at pin 1 and
insert the iSBX 488 Multimodule Board into the
host board iSBX connector until it is fully
inserted and correctly seated. The iSBX 488
Multimodule Board Jl connector should be
oriented in the same direction as the host
board's I/O connectors.
Push the remaining 114 inch screw up through
the bottom of the host board and thread it into
the spacer.
Tighten down both screws as shown in Figure
2-3.
Refer to Section 2-7 for jumper connection
information. If no jumper connections are
required, install the host board back into its
chassis.

The host iSBC board provides power to the iSBX 488
Multimodule board via the iSBX connector. The
maximum power requirement for the iSBX 488 board
is 600 rnA @ 5V. (±0.25 V).
The iSBX 488 board dissipates a maximum of 45.9
gram-calories per minute of heat. Adequate air
circulation must be provided to prevent a chassis
temperature rise over 55°C (131°F).

2-5. PHYSICAL DIMENSIONS
g.
Physical dimensions of the iSBX 488 board are provided in Figure 2-1. Mounting clearance detail is
shown in Figure 2-2.

Some iSBC Single Board Computers have up to
three iSBX Multimodule connectors. Choose the
connector location which corresponds to the
host I/O addressing you select. Refer to the host
board hardware reference manual for the base
address identification.
Install the supplied threaded spacer on the
solder side of the Multimodule Board (at the
hole). Secure the spacer by hand-tightening one
of the supplied 114 inch screws through the
component side of the iSBX 488 Multimodule
Board (refer to Figure 2-3).

2-1

iSBX488

Preparation for Use

3.70
1.245

I
I
I":

-I

1.390

.550

.200
MOUNTING HOLE

EB----------

2.85

iSBX 488'·

MOUNTING HOLE

EB - - - - -

.550

2.100

1.50

Figure 2-1. Physical Dimensions (Inches)

.400 MAX.
.580
SOCKET

.809

t
1

ISBX MULTIMODULE'· 1/0 PWB

.093

I
I

I
I
I
~-

Figure 2-2. Mounting Clearances (Inches)

2-2

iSBX 488

Preparation for Use

COMPONENT SIDE

iSBX MULTIMODULE BOARD
SOLDER SIDE
",- THREADED NYLON SPACER

COMPONENT SIDE

ISBC MICROCOMPUTER .sOARD
"," 6-32 NYLON SCREW

SOLDER SIDE

Figure 2-3. Mounting Technique

2-7. JUMPER CONFIGURATIONS
The iSBX 488 Multimodule Board has several
optional jumper configurations which may be
implemented to match your application.

Address Jumpers
Table 2-1 provides the options available for the
Address jumpers. These jumpers are not installed at
the factory. Push-on jumper receptacles are provided
for configuring the jumper options of your choice.
All jumper connections in Table 2-1 are general purpose, and must be used with the appropriate software programming to provide the desired function.
The table indicates the function typically assigned
to these particular jumpers.
The address jumper matrix allows you to set the 5-bit
binary address, talk address bit, listen address bit,
and jumper E8-E16 is used to indicate if the on-board
8292 circuit is or is not the GPIB system controller.

processor. The TCI interrupt flags the host processor
that certain commands have been executed. In the
factory configuration (E20-E27), the status of TCI
may be read from the on-board 8282 latch (bit D7).
The 8291A device sources a jumper selected interrupt
(DMA Request). This is connected to the iSBX board
pin Pl-34. Simultaneously, this signal may be
jumpered from post E24 to the destination indicated
in the table (i.e., E24-E25, E24-E26, or E24-E27).

NOTE
Only one interrupt souce may be connected
to any individual destination.

Count Input Jumper
The count input jumper allows source selection of the
Count Input pin on the 8292 device (pin 39). This
jumper is default connected (E18 - E19) to count EOI
transitions for sending or receiving multiple blocks
of data. Alternatively, the COUNT input may be
connected (E17 - E18) to count NDAC transitions for
sending or receiving a single block of data.

Interrupt Output Jumpers

TRIG Jumper

Three jumper connections are used to route optional
8292 interrupts to the host iSBC board. The following
table indicates the factory configuration:

Destination

The TRIG signal originates from the 8291A device
and may be jumpered to iSBX signals, OPTO (E23 E25) or to OPTI (E23 - E26). This normally low
signal, generates a 1 microsecond (minimum) high
pulse in response to the Group Execute Trigger GPIB
command.

P1-30 (OPTO)
P1-28 (OPT1)
DI7 on 8282 Latch

Summary

Interrupt

Jumper Pair

OBFI
IBFI
Tel

22 - 25
21 - 26
20 - 27

The OBFI & IBFI interrupts are typically used when
transferring data between the 8292 device and a host

Table 2-2 summarizes the factory installed and
optional jumper configurations on the iSBX 488
board.

2-3

iSBX 488

Preparation for·Use

Table 2-1. Address Jumper Configurations
Jumper Pair

E7-E15

ES-E14

E5-E13

E4-E12

E3-E11

E2-E10

E1-E9

Recommended
Assignment

ET/DT

EL/DL

ADS

AD4

AD3

AD2

AD1

Talker Address

Talk Address

Listener Address

Listen Address

Tal ker/Listener
Address

Talk/Listen Address

Don't Care

Notes:
1.
Address bit ADi = Logic 1 when Jumper is not installed.
2.

Enable Talk Address (ET)
Enable Listen Address (EL)

Jumper IN

Disable Talk Address (DT)
Disable Listen Address (DL)

Jumper E18-E16 is not general purpose. A jumper installed disables the System Controller Function of the
board.

Jumper OUT

NOTE: None of these jumpers are installed at the factory; only one System Controller (SYC) allowed per GPIB.

Table

2-2.

iSBX 488™ Jumper Configurations Summary
Source Location

Destination
Location

OBFI
U3pin35

IBFI
U3pin36

Tel
U3pin32

DREQ··
USpin6

TRIG
USpin6

EOI
U6pin3

NDAC
U6pin10

OPT 0, P1-30
OPT 1, P1-28
017, U1pin8
COUNT,U3pin39

E22-E25*
E22-E26
E22-E27

E21-E25
E21-E26*
E21-E27

E20-E25
E20-E26
E20-E27*

E24·E25
E24-E26
E24-E27

E23-E25
E23-E26
E23-E27
E23-E18

E19-E18*

E17,E18

NOTES:

•=

** =
hyphen =

Factory Installed
OREQ should not be jumpered whenever the host baseboard is terminating OREQ at connector P1-34.
Not applicable or recommended.

2-8. iSBX CONNECTOR PIN
ASSIGNMENTS (P1)

2-10. GPIB CONNECTOR PIN
ASSIGNMENTS' (J1)

Pin assignments for the iSBX connector (PI) on the
iSBX 488 Multimodule Board are provided in Table
2-3. Signal descriptions are given in Table 2-4,

Pin assignments for the GPIB connector (Jl) on the
iSBX 488 Multimodule Board are provided in Table
2-7. Signal descriptions are given in Table 2-8.

2-11. GPIB AC and DC SIGNAL
SPEClfl.CATIONS
2-9. iSBX CONNECTOR AC & DC SIGNAL
SPECIFICATIONS
Interface loading specifications for the iSBX connector signals are provided in Table 2-5. Timing specifications are shown in Figure 2-4 and Table 2·6.

2-4

The timing protocol for a typical GPIB transaction
is shown in Figure 2-5. The AC specifications are
given in Table 2·9. The DC loading specifications for
the GPIB interface (Jl connector) are provided in
Table 2-10.

iSBX 488

Preparation for Use

Table 2-3. iSBXTM Connector Pin Assignments
PIN
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

MNEMONIC
GND
MDO
MD1
MD2
MD3
MD4
MD5
MD6
MD7
GND
lORD
10WRTI
MAO
MA1
MA2
MRESET
GND
+12V

DESCRIPTION

MNEMONIC

36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

+5V
MDRQT
MDACKI
OPTO
OPT1
TDMA

SIGNAL GROUND
MDATA BIT 0
MDATA BIT 1
MDATA BIT 2
MDATA BIT 3
MDATA BIT 4
MDATA BIT 5
MDATA BIT 6
MDATA BIT 7
SIGNAL GROUND
10 READ COMMAND
10 WRITE COMMAND
M ADDRESS 0
M ADDRESS 1
M ADDRESS 2
RESET
SIGNAL GROUND
+12 Volts'

DESCRIPTION
+5 Volts
M DMA REQUEST
M DMA ACKNOWLEDGE
OPTION 0
OPTION 1
TERMINATE DMA'
"RESERVED*
M CHIP SELECT 0
M CHIP SELECT 1
+5 Volts
M WAIT*
M INTERRUPT 0
M INTERRUPT 1
RESERVED*
M PRESENT
M CLOCK'
+5 Volts
-12 Volts*

MCSOI

MCS11
+5V
MWAITI
MINTRO
MINTR1
MPSTI
MCLKI
+5V
-12V

NOTE: * = Not used on iSBX 488 board.

Table 2-4. iSBXTM Connector Signal Descriptions
10RDI

Commands the Multimodule board to perform the read operation.

10WRTI

Commands the Multimodule board to perform the write operation.

MRESETI

Initializes the Multimodule board to a known internal state.

MCSOI

Chip select O.

MCS11
MAO-2

Chip select 1.
Least significant three bits of the 1/0 address. Used in conjunction with the chip select and command lines.

MPSTI

Multimodule present indicator. Informs host board that a Multimodule board(s) is installed.

MINTRO-1

Interrupt request lines from the Multimodule board to the host board interrupt matrix.

OPTO-1

Optional use lines. May be used for additional interrupt request lines.

MDO-7
MDRQT

Bidirectional data lines.
Multimodule DMA Request issued by iSBX 488 Board.

MDACKI

DMA Acknowledge response from the host board DMA controller.

Table 2-5. iSBXTM Multimodule Board 1/0 DC Specifications (PI)
Output
Bus Signal
Name

Type
Drive

IOL MAX
-Min (rnA)

@ Volts
(Vol Max)

IOH MAX
-MIN (/JA)

@ Volts
(VOH Min)

CO (Min)
(pI)

MDO-MD7
MINTRO-1

TRI
TTL

1.6
2.0

0.5
0.5

-200
-100

130
40

MDRQT
OPT1-2

TTL

1.6

0.5

- 50

2.4
2.4
2.4

TTL
**

1.6

0.5

- 50

2.4

@ Vin Max
(volts)

MPSTI

40
40

Input
Bus Signal
Name

Type
Receiver

ilL MAX
(rnA)

@ VIN Max
(volts)

IIH MAX
(/JA)

MDO-MD7
MAO-MA2

TRI
TTL

-0.5
-0.5

0.8
0.8

70
70

2.2
2.0 (2.2) *

CO (Min)
(pI)
40

MCSO/-MCS1 I

TTL

0.8

100

2.0

MRESET

TTL

-4.0
-2.1

40
40

0.8

100

2.0

MDACKI

TTL

-1.0

0.8

100

2.0

10RDI 10WRTI
OPT1-0PT2

TTL

-1.0
-2.0

0.8

100
100

2.2

2.0

TTL

0.8

NOTES:
TTL = standard totem pole output. TR1 =Three-state
* = VIN ~ 2.2 volts required for MAO only
** = MPSTI is connected to signal ground

2"5

Preparation for Use

iSBX 488

}

MA(N)

I
\
LI7

MCS(N)I

!.-Is--l

112

10WRTI
II.

•

113

. ' III

114

MDO-MD7

iSBX Multimodule™ Board 110 Write Timing
MA(N)

)
f+-12-

I
MCS(N)I

IJ
10RDI

I---- Is----1
~15_

1----17_
11

MDO-MD7

J
iSBX Multimodule™ Board 1/0 Read Timing
~)

MDRQT

---1

(

)

MDACKI

(

f.- 1,6_
10 CMDI

------~?~--------~

iSBX Multimodule™ Board 1/0 DMA Timing

4.75~
+5 VOLTS

>0 NSEC ---.-

----

Ig & 1,5

RESET

iSBX Multimodule™ Board 110 Reset Timing

Figure 2-4. PI Interface Timing Specifications

2-6

Preparation for Use

iSBX 488

Table 2-6. iSBX Multimodule™ Board I/O AC Specifications
Symbol

Parameter

Address stable before read

Address stable after read

t3
t4

Read pulse width
Data valid from read

Data float after read
Time between RD andlor WRT

Max (ns)

50
30
300
0
0

250
150

Note 3

25
30

CS stable before CMD

I?
t8
t9
tlO
t11
t12
t13
t14
t 15
t16
t17
t18

Min (ns)

CS stable after CMD
Power up reset pulse width
Address stable before WRT

50 Msec
50
30
300
250
30
10 Msec
100
30

Address stable after WRT
Write pulse width
Data valid to write
Data valid after write
Reset pulse width
DACK set up to 1/0 CMD
DACK hold
CMD to DMA ROT removed to end of data cycle

200

Figure
Reference

2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4

NOTE:
Time dependent on the host iSBC board to which the Multimodule board is connected.

Table 2-7. GPIB Connector (Jl)
Pin Assignments
Pin No

1
2
3
4
5
6
7
8
9
10
11
12
13

Signal

0105
0101
0106
0102
0107
0103
0108
0104
REN
EOI
GND
DAV
GND

Pin No.

14
15
16
17
18
19
20
21
22
23
24
25
26

Signal
NRFD

assembly. The pin numbering conventions used on
the board and the two cable connectors are not
identical. Table 2-11 provides pin correspondence
among the three connectors.

GND
NDAC
GND
IFC
GND
SRO
GND
ATN

The 26-pin connector should be inserted onto the
iSBX 488 Multimodule Board Jl edge connector. The
24-pin connector should be connected to the GPIB.
The two extra ground lines are shield lines which
can be used for earth termination purposes.

GND
SHIELD
SHIELD
SHIELD

2-12. CONNECTOR & CABLE
INFORMATION
The iSBX 488 Multimodule Board is compatible with
the iSBC 988 GPIB interface cable/connector

Since the Jl connector is actually a two-row l3-pin
connector, care must be exercised when installing
the cable assembly. Odd numbered pins are on the
component side of the iSBX 488 Multimodule Board,
with pin 1 located at the corner edge (board is
marked accordingly). Both board and cable connector have triangle reference marks which should be
aligned as shown in Figure 2-6 to ensure proper
board to cable interface.

2-7

Preparation for Use

iSBX 488

Table 2-8. GPIB Connector Signal Descriptions
Description

Signal

Data Bus

Lines 0101 through 0108 are used to transfer addresses, control information and data. The
formats for addresses and control bytes are defined by the IEEE 488 standard. Data formats
may be ASCII (with or without parity) or binary. 0101 is the Least Significant Bit (bit 0).

Management Bus
ATN

Attention. This signal is asserted by the Controller to indicate that it is placing an address or·
control byte on the Data Bus. ATN is de-asserted to allow the assigned Talker to place status or
data on the Data Bus. The Controller regains control by reasserting ATN.

EOI

End or Identify. This signal has two uses as its name implies. A talker may assert EOI
simultaneously with the last byte of data to indicate end of data. The Controller may assert EOI
along with ATN to initiate a Parallel Poll.

SRO

Service Request. This line is like an interrupt: it may be asserted by any device to request the
Controller to take some action. The Controller must determine which device is asserting SRO
by conducting a Serial Poll at its earliest opportunity.

IFC

Interface Clear. This signal is asserted only by the System Controller in order to initialize all
device interfaces to a known state.

REN

Remote Enable. This signal is asserted only by the System Controller. Its assertion does not
place devices into Remote Control mode; REN only enables a device to go remote when
addressed to listen.

Transfer Bus
NRFD

Not Ready For Data. This handshake line is asserted by a listener to indicate it is not yet ready
for the next data or control byte.

NDAC

Not Data Accepted. This handshake line is asserted by a Listener to indicate it has not yet
accepted the data or control byte on the 010 lines.

DAV

Data Valid. This handshake line is asserted by the Talker to indicate that a data or control byte
has been placed on the 010 lines and has had the minimum specified settling time.

0101-0108

VALID

fTr
DAV

NOT VALID

..--T3---+- ...-TS ......

IC.-

r- r-T7---+- .....

NRFD

~I~

~T2-+-

NDAC

-J-

DREQ (SH)

DREQ (AH)

I I VALID
~

~T4"1

.-T
I'-

..J

Figure 2-5. GPIB AC Timing Waveforms

2-8

iSBX 488

Preparation for Use
Table 2-9. GPIB AC Timing Specifications

Symbol

Parameter

GPIB State

Min (ns)
167

Max (ns)

Reference

T1
T2

DIO Valid to DAV

SDYS

DAV to DAC

ACDS

730

Section 3-11
Figure 2-5

DAC to DAV false

Figure 2-5

DAV to DREQ
DAV false to NDAC

SWNS
AH & LACS

430

650

Figure 2-5

ANRS

440

Figure 2-5

ACRS
ACRS

430

DAV false to RFD
10RD/ to RFD

10WR/ false to DIO

TACS

310

Figure 2-5
Figure 2-5
Figure 2-5

RFD to DREQ

SH & TACS

450

Figure 2-5

T5
T6

2750

530

Table 2-10. GPIB Interface, Jl, DC Specifications
Symbol

Limits

Parameter
Min

Unit

Test
Condition
IOL=4BmA
IOH=-5.2mA

Max

VIL

Input Low Voltage

O.B

VOL

Output Low Voltage

0.5

VOH
VT+-VT

Output High Voltage

VIT

Receiver Threshold H to L
Lto H

IpD

Bus Power Down
Leakage Current

-10

IlL
IIH

Low Input Load Current
High Input Load Current

- 3.2
0.0

Receiver Input Hysteresis

2.4

400
O.B
2.0

mV
V
V

f.lA

- 1.3
2.5

Vcc=OV
VIL =O.4V
Vlw3.7V

2-9

iSBX 488

Preparation for Use

Table 2-11. Pin Correspondance
GPIB Signal
Name

PWA, J1
Connector

2S-Contact
Edge
Connector

0101
0102
0103
0104
0105
0106
0107
0108

2
4
6
8
1
3
5
7
12
14
16
10
9
18
20
22
11
13
15
17
19
21
23
24
25
26

1
3
5
7
2
4
6
8
11
13
15
9
10
17
19
21
12
14
16
18
20
22
24
23
26
25

DAV
NRFD
NDAC
EOI
REN
IFC
SRQ
ATN
GND
GND
GND
GND
GND
GND
GND
SHIELD
SHIELD
SHIELD

2-13. INSTALLATION SUMMARY

24-Contact
Receptacle

1
2
3
4
13
14
15
16
6
7
8
5

The following list summarizes the complete iSBX
488 board installation procedure:

Perform any required jumper modifications on
the iSBX 488 board (refer to Section 2-7).

Install the iSBX 488 board onto the host iSBC
board (refer to Section 2-6). Ensure that host
iSBC board is removed from its cardcage and
power is not applied.

Install the host iSBC board and iSBX 488 board
combination back into the cardcage. Ensure
that power is not present and that physical
clearance is provided for combined board height.

Install iSBC 988 Cable Assembly (or equivalent)
between iSBX 488 board and GPIB (refer to section 2-12). Ensure that power is not applied to
the iSBC/iSBX system or the GPIB system.

Check other I/O cables on host iSBC board
system for correct seating.

9
10
11
18
19
20
21
22
23
24
12
Void
Void

26-PIN P1
CONNECTOR

iSBX 488'·
BOARD

SHIELD LINES (2)

PIN 1 MARKER

INSTRUCTIONS: PLUG P1 CONNECTOR INTO J1 EDGE CONNECTOR ON iSBX
488 BOARD. ENSURE THAT TRIANGLE MARKERS ARE ALIGNED. PLUG P2
CONNECTOR INTO GPIB MATING PLUG.

Figure 2-6. iSBX 988™ Cable Installation

2-10

24-PIN
GPIB
RECEPTACLE (P2)

CHAPTER 3
PROGRAMMING INFORMATION

3-1. INTRODUCTION
This chapter provides programming instructions
and protocol information for the iSBX 488 Multimodule Board. This information includes 110 addressing, register descriptions, system initialization,
and programming examples.

3-2. iSBX 488 MULTIMODULE BOARD
PROTOCOL
All communication between the host iSBC board and
the iSBX 488 Multimodule Board is executed via the
iSBX connector. The 8291A device and the 8292
device can each communicate independently with
the host processor.
The 8291A device handles all GPIB non-controller
functions in which data or command/status information may be read from or written to the host board
system program. Direct Memory Access (DMA) operation is available for bus data transfer operations.

DMA is discussed in section 4-6. Indicating 8291A
status may be interrupt driven or polled.
The 8292 device handles all GPIB controller functions. Communication to the host CPU may be interrupt driven or status polled.
The 8282 device is used as a general purpose readonly register, except bit D7. Bit D7 may be used to
indicate TCI (Task Completion Interrupt) status in
polling 8292 related routines.

3-3. iSBX 1/0 PORT ADDRESSING
110 Port addressing for the iSBX 488 Multimodule
Board can be divided into three groups: 8291A registers, 8292 registers, and the 8282 register. The host
board must assert the proper chip select signal in
conjunction with the desired address to perform 110
read or write operations. Table 3-1 summarizes the
I/O addresses and chip select requirements.

Table 3-1. 1/0 Port Addresses & Chip Select Assignments
iSBX Address Lines
8291A Registers
Multimodule Chip Select 0 (MCSO/=O)
Write
Read
Data In
I nterrupt Status 1
Interrupt Status 2
Serial Poll Status
Address Status
Command Pass Through
Address 0
Address 1

Data Out
I nterrupt Mask 1
Interrupt Mask 2
Serial Poll Mode
Address Mode
Aux Mode
Address 0/1
EOS

iSBX I/O Port

MA2

MA1

MAO

Hex Address """

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

XO
X1
X2
X3
X4
X5
X6
X7

8292 Registers
Multimodule Chip Select 1 (MCS1/=O)
Read
"Interrupt Mask
"Error Flag
"Error Mask
"Event Counter Status
"Time Out Status
"Controller Status
"GPIB Status
Interrupt Status

Write
*"Interrupt Mask
""Error Mask
"Event Counter
"Time Out
Command Field

8282 Register
Read (MCS1/=O)

0
0
0
0
0
0
0
1

N
N
N
N
N
N
N
N
N

XA
XA
XA
XA
XA
XA
XA
XB

or
or
or
or
or
or
or
or

XE
XE
XE
XE
XE
XE
XE
XF

X8 or X9 or,
XC or XD

NOTES:
"This register is accessed for an IlPpropriate read or write by first writing a specific byte to the Command Field Register. See
section 3-14for more details.
*" The Interrupt Mask and Error Mask register are distinguished from each other by the value of the most significant bit, 07, in the
byte written to the 8292. See Table 3-6 for more details.
N indicates an irrelevant condition.
Low Voltage state.
1 indicates a High Voltage state.

o indicates a

""" The hex addresses correspond to an 8-bit iSBC board only. The first digit of each I/O address is represented as X since it will
change depending on the type of host iSBC board used. Refer to the HRM for your host iSBC board to determine the first digit
required for the I/O address.

3-1

Programming Information

iSBX488

3-4; 8291A REGISTERS

3-:6. INTERRUPT REGISTERS

The 8291A circuit utilizes 16 internal registers to
communicate with the host board. Register addressing was described in section 3-3. Table 3-2 provides a
summary of register bit identification, and the associated iSBX I/O port address.

CPT

APT

GET

END

DEC

ERR

INTERRUPT STATUS 1

Sections 3-5 through 3-14 describe the 8291A registers.

INT

SPAS

LLO

CPT

APT

GET

REM I SPC
I LLOC
I
INTERRUPT STATUS 2

END

DEC

I REMC

ERR

IADSC

INTERRUPT MASK 1

I DMAO I

DMAI

SPC

LLOC I REMC

I ADSC I

INTERRUPT MASK 2

3-5. DATA REGISTERS
016

017

015

014

013

012

011

010

001

000

The 8291A is configured to generate an interrupt (to
the host iSBC board) on occurrence of any of 12 GPIB
conditions or events. The host board reads the 8291A
interrupt status register to determine which event
has occurred, and then executes the appropriate service routine. The bit mnemonics are summarized in
Table 3-3. Most bits in the Interrupt Status 1 & 2
Registers have a corresponding bit mask. The bit is
enabled by writing a logic one to the mask. Notice
that four of the bits in the Interrupt Status 2 Register
are status-only bits and do not generate interrupts.

DATA IN

007

006

DOS

004

003

002

DATA OUT

The 8291A utilizes two data registers: the data-in
register and the data-out register. The data-in register is used to move data from the GPIB to the host
iSBC board when the 8291A is an active listener.
The data-out register is used to move data from the
host iSBC board to the GPIB when the 8291A is an
active talker. The data from the GPIB is latched into
the data-in register, and its contents are not destroyed
by writing to the data-out register. Likewise, a read
of the data-in register does not destroy information
in the data-out register.

The interrupt status registers are cleared when read
or when a local PON message is executed. The bits in
the interrupt status registers are enabled regardless
of the corresponding enable bit in the Interrupt Mask
Registers. The INT bit is cleared whenever the appro
priate interrupt bit(s) is read and cleared from the
Interrupt Status 1 and/or 2 Registers.

Table 3-2. 8291A Registers

READ REGISTERS

WRITE REGISTERS
PORT # (HEX)

I
I
I
I

017

CPT

INT

I
I
I
I

016

APT

SPAS

SROS

I
I
I

015

GET

I
I
I
I

014

I
I
I
I

013

012

END

DEC

I
I

ERR

INTERRUPT STATUS 1
LLO

011

010

'X' 0

REM

SPC

LLOC

I
I

REMC

I
I

ADSC

I
I

'X' 1

ton

Ion

CPT7

CPT6

EOI

LPAS

TPAS

CPT5

I
I

CPT4

I
I

CPT3

I
I

CPT2

COMMAND PASS THROUGH
INT

DTO

'X' 2

'X' 3

DlO

AD5-0

AD4-0

AD3-0

CPTl

AD2-0

I
I

MJMN

CPTO

AD1-0

I
I

'X' 4

'X' 5

OT1

3-2

CPT

006

APT

I
I

005

GET

Oll

ADS-I I

AD4-1 I AD3-1

ADDRESS 1

I
I

004

003

DATA OUT
END

DEC

I
I

002

ERR

I
I

001

I
I

000

I
I

SPC
DMAI
I
I LLOC I
INTERRUPT MASK 2

I DMAO I

I
I
I

CNT2 I

rsy

CNT1

I
I

CNTO

S5
84
I
I
I
SERIAL POLL MODE

I
I

ADDRESS MODE
COM4

COM3

I
I

COM2 I

REMC I

ADMl

COMl

I
I

ADSC I

ADMO

COMO

I
I

AUX MODE
'X' 6

ADDRESS 0

I
I

INTERRUPT STATUS 2

ADDRESS STATUS

I
I

007

INTERRUPT MASK 1

SERIAL POLL STATUS
I

DATA IN

ARS

ADS

AD4

AD3

EC2

AD2

ADl

ADDRESS 011

A02-l

AD1-l

'X' 7

EC7

EC6

EC5

EC4

I
EOS

EC3

ECl

ECO

Programming Information

iSBX 488

BO & BI Interrupts
The BO and BI interrupts are used to perform data
transfer cycles. BO indicates that a data byte should
be written to the Data Out Register. Similarly, BI
indicates that a data byte may be read from the Data
In Register. BO is set whenever the 8291A is in TACS
• (SWBS + SGNS) state and the RFD signal is true
(passive high). When an active GPIB controller
(other than the 8292 component) takes control (synchronously), the 8291A will source handshake the
last byte out successfully. If the controller takes control asynchronously the 8291A will clear the output
data and enter TADS • SIDS. The BO interrupt will
reset. If the controller enters the standby mode, releasing ATN, the 8291A will enter TACS. SGNS and
BO will be set.
If an IFC is issued by the System Controller the

8291A will exit TACS and enter TIDS, clearing BO.
After IFC returns false and the 8291A is in the talkonly mode (refer to section 3-9 for information on
addressing modes) the 8291A will enter TACS and
set BO after ATN is released. BI is set whenever the
8291A is in the LACS. ACDS state.
The BI (BO) interrupt is reset after a byte has been
read from (written to) the 8291A. BO and BI are also
reset by issuing a "pon" command (refer to Auxiliary
Commands in section 3-11), or by reading the Interrupt Status 1 Register. Data cycles may be performed
without reading the Interrupt Status 1 register if all
interrupts except BO & BI are disabled. BO & BI will
reset automatically after each byte is transferred.

APT Interrupt
This interrupt indicates (to the host iSBC board) that
a secondary address has been received and is ready
to be validated by reading the command pass
through register. This interrupt will only occur in
Mode 3 addressing. See section 3-9.

Group Execute Trigger (GET)
This interrupt is set by the 8291A when the GET
message is received. The 8291A must be addressed to
listen. The TRIG output is asserted for at least 1
microsecond when the GET message is received.

END Int
The END interrupt bit is used to detect the end of a
multibyte transfer. The bit is set when the 8291A is
an active Listener and EOS (if enabled by Aux Reg
A) or EOI is received. See Aux Mode Register, section
3-11.

DEC Int
The DEC Bit is set whenever a DCL message is received or the 8291A is addressed to Listen and a SDC
message is received.

ERR Int
The ERR bit is set when the 8291A is an active talker
and tries to send a byte to the GPIB and no Listeners
are active.

Serial Poll Complete Interrupt (SPC)
3-7. STATUS BITS
The serial poll complete interrupt is set when the
Controller-In-Charge has accepted (DAC true) the
8291A status byte after the 8291A has requested
serVlce.

Command Pass Through (CPT) Interrupt

Bits 4 through 7 of the Interrupt Status Register 2
are available to the Host board as status bits. These
bits are status only. They will not generate Interrupts nor do they have corresponding mask bits. For
example, if the Host board receives a REMC interrupt the nature of the interrupt can be determined by
reading the REM Status Bit.

This interrupt indicates (to the host iSBC board) that
an undefined command or a secondary command
following an undefined command, has been received
from the GPIB. Any message not decoded by the
8291A becomes an undefined command. The command is stored in the CPT register for use by the host
board. See section 3-10 for further details ofthe CPT
register and defined/undefined commands.

Bits 4 and 5 (DMAI, DMAO) of the Interrupt Mask 2
Register are available to enable direct data transfers
between the iSBX data bus and the GPIB: DMAI
(DMA in) enables the DREQ (DMA request) pin of
the 8291A to be asserted upon the occurrence of BI.
Similarly, DMAO (DMA out) enables the DREQ pin
to be asserted upon the occurrence of BO. One might
note that the DREQ pin may be used as a second
interrupt output pin, monitoring BI and/or BOand

3-3

Programming Information

iSBX 488

enabled by DMAI and DMAO. One should note that
the DREQ pin is not affected by a read of the Interrupt Status 1 Register. It is reset whenever a byte is
written to the Data Out Register or read from the
Data In Register.
Bit 3 (SPC) of the Interrupt Status 2 Register indicates when a serial poll is complete, (assuming the
8291A had previously issued a service request, [SRQ],
from the Controller-In-Charge). The SPC flag and
interrupt (if unmasked) is set when the 8291A is exiting the SPAS. APRS state and entering the TADS.
NPRS state. (I.e., when ATN is reasserted by the
Controller-In-Charge.)
Bits 0, 1 and 2 (ADSC, HEMC and LLOC) in the
Interrupt Status 2 Register are used to indicate state
changes. Bit 0, ADSC, indicates a transition in LIDS
- LADS or TIDS - TADS or Major/Minor addressing (refer to section 3-9 for information on addressing
modes). Bit 1, REMC, indicates a transition in LOCS
- REMS. Bit 2, LLOC, indicates a change in LWLS
- RWLS. The status bit and interrupt (if unmasked)
will remain set even if more than one transition in
that particular state has occurred (e.g., LIDS LADS - LIDS). The nature of the state may be interrogated by reading bits 4, 5 or 6 of the Interrupt
Status 2 Register.

3-8. SERIAL POLL REGISTERS
S8

SRQS

SERIAL POLL STATUS

rsv

SERIAL POLL MODE

The serial poll mode register is used to establish the
status byte that the iSBX 488 Multimodule Board
will issue to the GPIB in response to the serial poll
enable (SPE) message. Setting bit 7 (rsv) causes the
8291A to assert the SRQ line (Jl-20), indicating its
need for attention from the Controller-In-Charge of
the GPIB. When service has been granted, the rsv bit
is automatically cleared by the 8291A. The SPC
interrupt is generated (if unmasked) after the
Controller-In-Charge has reasserted ATN, ending
the serial poll. The other bits of the register are available for sending status information over the GPIB.
The CPU may request service by writing another
byte to the Serial Poll Mode Register with the rsv bit
set. If the controller performs a serial poll when the
rsv bit is clear, the last status byte written will be
read, but the SRQ line will not be driven by the 8291A
and the SRQS bit will be cleared in the status byte.

Table 3-3. Interrupt Register Bit Identification

An undefined command has been received.

CPT
APT

GET

4
3

END
DEC
ERR
BO
BI

INTERRUPT
A group execute trigger has occured.
STATUS 1
An EOS or EOI message has been received.
REGISTER
Device Clear Active State has occurred.
Interface error has occurred; no listeners are active.

BIT 7

2
1

Shows status of the INT pin
The 8291A has been enabled for a serial poll
The 8291A is in local lock out state.

INT
SPAS
LLO

The 8291A is in a remote state.

REM

7
6

3
2
1

BIT 0

SPC
LLOC
REMC
ADSC

A secondary address must be passed through
to the microprocessor for recognition.

A byte has been output.
A byte has been input.

These are status only. They will not generate
interrupts. not do they have corresponding
mask bits ..

Serial Poll Complete Interrupt
......
Local lock out change interrupt LLO....~ LLO
Remote/Local change interrupt. RemotVocal
Address statu~hange interrupt.*
Addressed Unaddressed

*In ton (talk-only) and Ion (listen-only) modes. no ADSC interrupt is generated.

3-4

---

INTERRUPT
STATUS 2
REGISTER

iSBX 488

Programming Information

The Serial Poll Status Register is available for reading the status byte in the Serial Poll Mode Register.
The processor may check the status of a request for
service by polling bit 7 of this register, which corresponds to the SRQS (Service Request State). When a
Serial Poll is conducted and the Controller-InCharge reads the status byte, the SRQS bit is
cleared. The SRQ line is tied to this bit, so that a
request for service is terminated when the 829IA
status byte is read by the Controller-In-Charge. The
Controller-In-Charge may, however, read the status
more than once before ending the serial poll. The
829IA will continue to source handshake the status
stored in the status register until the controller ends
the poll by asserting ATN.

3-9. ADDRESS REGISTERS
There are five separate registers associated with
GPIB addressing:
a. Address Mode Register d.
b. Address Status Register e.
c. Address 0/1 Register

Address 0 Register
Address 1 Register

07H implies a non-valid secondary address

OFH implies a valid secondary address

See section 3-11 for details on the Auxiliary Mode
Register.
Address mode is selected by writing one of the following bytes to the address mode register:
Command
Byte

Address Mode Register

In Mode 3, the 829IA handles addressing as in Mode
1, except each Major or Minor primary address must
be followed by a secondary address. All secondary
addresses must be verified by the microprocessor
when Mode 3 is used. When the 829IA is in TPAS or
LPAS (talker/listener primary addressed state), and
it does not recognize the byte in the DIO lines, an
APT interrupt is generated. The GPIB handshake is
held off with NRFD true and the byte becomes available in the CPT (Command Pass-Through) Register.
As part of its interrupt service routine, the microprocessor must read the CPT Register and write one
of the following responses to the Auxiliary Mode
Register:

ADM1

ADMO

ADDRESS MODE

The address mode register is used to select one of the
five addressing modes available for the 829IA device.
Setting the "TO" bit puts the 829IA in a Talk only
Mode while setting the "La" bit puts the 829IA in a
Listen only Mode. These bits may be used by the
Controller-In-Charge to set itself up for remote commands or data communication. These may also be
used to allow a device to operate as a Talker or a Listener in an interface system without a controller.
In Mode 1, the content of the Address 0 Register constitutes the "Major" talker/listener address while the
Address 1 Register represents the "Minor" talker/
listener address. In applications where only one
address is needed, the major talker/listener is used,
and the minor talker/listener should be disabled.
Loading an address via the Address 0/1 Register
into Address Registers 0 and 1 enables the major and
minor talker/listener functions respectively.
In Mode 2, the 829IA recognizes two sequential address bytes: a primary followed by a secondary. Both
address bytes must be received to enable the device
to talk or listen. In this manner, Mode 2 addressing
implements the extended talker and listener functions as defined in the IEEE-488 standard.
To use Mode 2 addressing, the primary address must
be loaded into the Address 0 Register, and the
Secondary Address is placed in the Address 1 Register. With both primary and secondary addresses
residing in the 829IA, all addressing sequences are
handled without processor intervention.

Mode
Enable Talk-Only Mode (TON) Bit TO=1
Enable Listen-Only Mode (LON) Bit LO=1
8291A Self Talk, Bits TO=1, LO=1
Mode 1: Primary - Primary Bit ADMO =1
Mode 2: Primary - Secondary Bit ADM1 =1
Mode 3: Primary / APT - Primary /
APT Bits ADMO=1, ADM1 =1

10000000
01000000
11000000
00000001
00000010
00000011

Address Status Register

ton

Ion

EOI

LPAS

TPAS

I MJMN I

ADDRESS STATUS

The address status register is used by the host board
to handle its own addressing. This includes status
bits which monitor the address state of each talker/
listener.
The Address Status Register contains information
used by the microprocessor to handle its own addressing. This information includes status bits that
monitor the address state of each talker/listener,
"ton" and "Ion" flags which indicate the talk and
listen only states, and an EOI bit which, when set,
signifies that the END message arrived with the last
data byte. LPAS and TPAS indicate that the listener
or talker primary address has been received. The
microprocessor can use these bits when the secondary address is passed through to determine whether
the 829IA is addressed to talk or listen. The LA (listener addressed) bit will be set when the 829IA is in
LACS (Listener Active State) or in LADS (Listener
Addressed State). Similarly, the TA (Talker Addressed bit) will be set to indicate TACS or TADS,
but also to indicate SPAS (Serial Poll Active State).

3-5

Programming Information

iSBX 488

The MJMN bit is used to determine whether the
information in the other bits applies to the Major or
Minor talker/listener. It is set to "I" when the Minor
talker/listener is addressed. Note that only one
talker/listener may be active at anyone time. Thus,
the MJMN bit will indicate which, if either, of the
talker/listeners is addressed or active.

Address 011 Register
lARS

ADS

AD4

AD3

AD2

ADl

ADDRESS Oil

The Address 0/1 Register is used for specifying the
device addresses according to the format selected in
the Address Mode Register. Five bit addresses may
be loaded into the Address 0 and Address 1 Registers
by writing into the Address 0/1 Register. The Address Register Select (ARS) bit is used to select which
of these registers the other seven bits will be loaded
into. The DT and DL bits may be used to disable the
talker or listener function at the address signified by
the other five bits. When Mode 1 addressing is used
and only one primary address is desired, both the
talker and the listener should be disabled at the
Minor address.
As an example of how the Address 0/1 Register
might be used, consider an example where two primary addresses are needed in the device. The Major
primary address will be selectable only as a talker
and the Minor primary address will be selectable
only as a listener. This configuration of the 8291A is
formed by the following sequence of write operations
by the microprocessor.

Operation

Write
Data

1. Select addressing Mode 1
00000001
2. Load major address into
001AAAAA
Address 0 Register with
listener function disabled.
3. Load minor address into
110BBBBB
Address 1 Register with talker
function disabled.

Port
Address
Hex
X4
X6

At this point, the addresses AAAAA and BBBBB are
stored in the Address 0 and Address 1 Registers
respectively, and are available to the host microprocessor. Thus, it is not necessary to store any address
information elsewhere. Also, with the information
stored in the Address 0 and Address 1 Registers, processor intervention is not required to recognize addressing by the controller. Only in Mode 3, where
secondary addresses are passed through, must the
processor intervene in the addressing sequence.

3-6

Address 0 and Address 1 Register
DTO

INT

DLO

ADS-O I

AD4-0 I AD3-0 I

AD2-0 I AD1-0

ADDRESS 0

DTO

DLO

ADS-O I

AD4-0 IAD3-0

AD2·0 I AD1·0

ADDRESS 1

The Address 0 Register contains a copy of the Interrupt Status 2 Register (INT) bit 7. This is to be used
when polling for interrupts. Software should poll
register 6 checking for INT (bit 7) to be set. When
INT is set, the Interrupt Status Register should be
read to determine which interrupt was received.

3-10. COMMAND PASS THROUGH
REGISTER
CPT7

CPT6

CPT5

CPT4

CPT3

CPT2

CPT1

I CPTO

COMMAND PASS THROUGH

The command pass through register (CPT) stores the
most recent 8-bit command received from the GPIB
Controller-In-Charge (off board). This includes undefined as well as defined GPIB commands. (Note: The
8291A interprets any 8-bit data as a GPIB command
whenever the data was accepted (DAC) while ATN
was true). Table 3-4 lists all commands that are defined and undefined by the 8291A. Defined commands are acted upon automatically by the 8291A.
Undefined commands have no effect on the 8291A
operation but are stored (1 byte) in the CPT register
for the. host CPU to read and interpret.

Table 3-4. Defined/Undefined
Commands Received
Mnemonic

Message

ATN
DCL
GET
GTL
LLO
MLA
MTA
MSA
*PPC
*PPE
*PPD
*PPU
SDC
SPD
SPE
*TCT
UNL

Attention
Device Clear
Group Execute Trigger
Go To Local
Local Lock Out
My Listen Address
My Talk Address
My Secondary Address
Parallel Poll Configure
Parallel Poll Enable
Parallel Poll Disable
Parallel Poll Unconfigure
Selective Device Clear
Serial Poll Disable
Serial Poll Enable
Take Control
Unlisten

NOTE:
* =This command is undefined to the 8291A but isstored in
the CPT register for read access.

iSBX 488

Programming Information

An APT or CPT interrupt may be sent to the host
CPU and the aPIB handshake (SH and AH) halted
indicating the availability of a secondary address or
an undefined command in the CPT register. This
feature is discussed in section 3-11 under Auxiliary
Register B and section 3-9 under Mode 3 addressing.
An added feature of the 8291A is its ability to handle
undefined secondary commands following undefined
primaries. Thus, the number of available commands
for future IEEE-488 definition is increased.
The recommended use of the 8291A undefined command feature is for a remote configured Parallel Poll
(subset PP1). The PPC message is an undefined primary command typically followed by PPE or PPD,
an undefined secondary command. For details on
this procedure, refer to the section on Parallel Poll
Protocol.

NOTE
All commands received are held in the CPT
register but a Handshake Hold Off on CPT
Interrupt is not generated unless it is an
undefined command. The content of this
register is destroyed when a new command
is received.

3-11. AUXILIARY MODE REGISTER

I CNT2 I

CNT1

CNTO

COM4

COM3

COM2

COM1

COMO

AUX MODE

The auxiliary mode register contains a three-bit
control field linked with a five-bit command field. It
is used for the following purposes:
a.

To issue commands and GPIB local messages
from the host board.

To load auxiliary registers.

To preset an internal counter.

Internal Counter
The internal counter is used to generate the T1 delay
in the source handshake function, as defined in
IEEE 488. By writing 00l0F,F2FIFo into the Auxiliary Mode Register, the counter is preset to match a
6.0 MHz clock input, where F,F2FIFo is the binary
representation ofNF (1 ,,;;NF";; 8). Example: when NF
= 6 (F,F2FIFo=01l0), a 2 psec TI delay will be generated before each DAV asserted.

Equation 1 TI(psec) = NF (psec) + tsync (psec)
3
tsync is a synchronization error ";;0.083

If 1'1 = 2ps is not suitable, NF may be set to a value
other than 6. In this manner, data transfer rates
may be programmed for a given system. In small
systems, for example, where transfer rates exceeding
GPIB specifications are required, one may set N F< 6
to decrease TI. The maximum TI is 2.75 psec (N F=8).
Since the 8293 devices are Tri-State Drivers (during
non Parallel Poll operation) a faster transfer (Lower
TI) may be achieved by enabling the high speed
transfer bit in Auxiliary Register B. (See Auxiliary
Register B description.) In the aforementioned case,
setting N F=6 causes a TI delay of 2ps (from equation
1) for the first byte transmitted, and a delay of 500ns
(see equation 2) for all subsequent bytes transmitted.

Equation 2 TI(High Speed) psec = NF (psec) + tsync
(psec)

Thus, the shortest Tl is achieved by setting N F=l
(T1 = 1/12 + 0.083 = 0.167 psec max.)

Code
Command

Control
Field

Command
Field

CNT2-CNTO

COM4-COMO

000

OC3C2C,CO

001

Preset internal counter for
T1 SH delay from 0.167 to
2.75 microseconds. FFFF
(base 2 is the scalar.)
A4A3A2A,Ao Write A4A3A2A,Ao into
auxiliary register A

100
101
011

Execute auxiliary command CCCC

OF4F2F,Fo

6463B26,60 Write 6463626,60 into
auxiliary register 6
USP3P2P,

Parallel Poll Enable (PPE)
or Parallel Poll Disable
(PPO) either in response to
remote messages (PPC followed by PPE or PPO) or as
a local Ipe message. (Enable if U=O, disable if U=1.)

Auxiliary Commands
Auxiliary commands are issued by the 8291A device
whenever the "execute auxiliary command" command is asserted. There are twelve different auxiliary
commands, each with its own 4-bit code. These
commands are identified in Table 3-5.
Auxiliary registers A and B are "hidden" 5-bit
registers used to enable various iSBX 488 Multimodule Board features.
Auxiliary commands are executed by the 8291A
whenever 0000C3C2C1CO is written into the Auxiliary Mode Register, where C3C2C 1CO is the 4-bit
command code.

3-7

Programming Information

iSBX 488

Table 3-5. Auxiliary Command Identification
4-BII Code
(C3C2C1 CO)

Description

0000

Immediate Execute pon - This command
is used to release the "initialize" state
generated by either an external reset
pulse or the Reset (0010) command. This
command forces the 8291A to enter idle
states (SIDS, AIDS, TIDS, LIDS, NPRS,
LOCS, PPIS, DCIS and DTIS).

0010

Chip Reset (Initialize) - This command
has the same effect as a pulse applied to
the Reset pin. The 8291A is reset to an
initialization state in which case the
8291A does not participate in any GPIB
bus activity. The following registers are
cleared: Interrupt Status, Auxiliary A and
B and Serial Poll Mode. The following bits
are cleared: Parallel Poll Flag and the EOI
bit in the Address Status Register. The
Internal Counter, NF, is reset to 8, thus
causing a T1 delay of 2.75 Ilsec (see
section on Internal Counter.) This state is
released by an "immediate execute pon"
command.

0011

Finish Handshake - This command finishes a handshake that was stopped because of a holdoff on RFD Command.
(Refer to Auxiliary Register A.)

0100

Trigger - A "Group Execute Trigger" is
forced by this command. It has the same
effect as a GET command received from
the Controller-In-Charge of the GPIB, but
does not cause a GET interrupt.
Clear/Set rtl - These commands correspond to the local rtl (return to local)
message as defined by the IEEE-488. The
8291A will go into local mode when a Set
rtl Auxiliary Command (0101) is received
if local lockout is not in effect. The 8291 A
will exit local mode after receiving a Clear
rtl Auxiliary Command (1101) if the 8291 A
is addressed to listen.

0101,1101

0110

Send EOI - The 8291A EOI line may be
asserted with this command. The command causes EOI to go true with the next
byte transmitted. The EOI line is then
cleared upon completion of the handshake for that byte.

Auxiliary Register A
Auxiliary Register A is a "hidden" 5-bit register
which is used to enable some of the 8291A features.
Whenever a 100 A4A3A2AI Ao byte is written into the
Auxiliary Mode Register, it is loaded with the data
A4A3A2AIAo. Setting the respective bits to "I"
enables the following features.
Ao - RFD Holdoff on all Data: When the 8291A is
listening (in LADS or LACS) RFD will be held false
after a data byte has been accepted (DAC) to holdoff
further data transfers across the GPIB. This feature

3-8

4-Bit Code
(C3C2C1CO)

Description

0111, 1111

Non-ValidlValid Secondary Address or
Command (VSCMD) - This auxiliary
command is used in three separate instances where the host processor is responding to the 8291A: response to an
APT interrupt, response to a CPT interrupt and a response to a GET or DEC
interrupt. See section 3-6 for a description
of these interrupts. When an APT interrupt occurs the host processor must read
and interpret the secondary address
(Mode 3 Addressing only) and respond to
the 8291A with a valid (1111) or invalid
(0111) command. Either response will release the RFD holdoff on the GPI8. Only a
valid response will release the 8291A into
a TADS or LADS state. When a CPT interrupt occurs and the Undefined Command
Pass Through (bit 80 in Auxiliary Register B) feature has been enabled, the host
processor must read and interpret the
undefined command and respond to the
8291A with a valid or invalid command to
release the RFD holdoff. This operation is
similar for a response to the GET or DEC
interrupt when RFD holdoff is enabled by
bit 84 in Auxiliary Register B.

1000

pon - This command puts the 8291A into
the pon (power on) state and holds it there.
It is similar to a Chip Reset except none of
the Auxiliary Mode Registers are cleared.
I n this state, the 8291 A does not participate in any bus activity. An Immediate
Execute pon following this command releases the 8291A from the pon state and
permits the device to participate in bus
activity.
Parallel Poll Flag (local "ist" message) This command sets (1001) or clears (0001)
the parallel poll flag. A "1" is sent over the
assigned data line (PPR-Parallel Poll
Response true) only if the parallel poll flag
matches the sense bit from the Ipe local
message (or indirectly from the PPE message). For a more complete description of
the Parallel Poll features and procedures
refer to the section on Parallel Poll
Protocol.

0001, 1001

is enabled for each data byte accepted until disabled.
To continue the handshake a "finish handshake"
auxiliary command is required.
Al - RFD Holdoff on End: This feature enables the
holdoff on EOI or EOS (if enabled). However, no
holdoff will be in effect on any other data bytes.
A2 - End on EOS Received: Whenever the byte in
the Data in Register matches the byte in the EOS
Register, the END interrupt bit will be set in the
Interrupt Status 1 Register.

iSBX 488

A, - Output EOI on EOS Sent: Any occurrence of
data in the Data Out Register matching the EOS
Register causes the EOI line to be sent true along
with the data.

A4 - EOS Binary Compare: Setting this bit causes
the EOS Register to function as a full 8-bit word.
When it is not set, the EOS Register is a 7·bit word
(for ASCII characters).

If Ao=AJ=I, a special "continuous Acceptor Handshake cycling" mode is enabled. This mode should
be used only when the 8292 is the Controller-InCharge ofthe GPIB. It provides a continuous cycling
through the Acceptor Handshake diagram, requiring
no local rdy messages from the microprocessor; the
rdy local message is automatically generated when
in ANRS. As such, the 829IA Acceptor Handshake
serves as the 8292 controller Acceptor Handshake.
Thus, the controller cycles through the Acceptor
Handshake without delaying the data transfer in
progress. When the tcs local message is executed, the
8291A should be taken out of the "continuous AH
cycling" mode, the GPIB will hang up in ANRS, and
a BI interrupt will be generated to indicate that control may be taken. A simpler procedure may be used
when a "tcs on end of block" is executed; the 829IA
may stay in "continuous AH cycling." Upon the end
of a block (EOI or EOS received), a holdoff is generated, the GPIB halts in ANRS, and control may be
taken.

Programming Information

sent with the status byte; EOI is set true in Serial
Poll Active State. Otherwise, EOI is sent false in
SPAS.

B2 - Enable High Speed Data Transfer: The data
transfer rate is determined by the T J delay time
generated in the Source Handshake function. When
the "High Speed" feature is enabled, TJ is determined
by equation 1 (refer to Internal Counter in section 311) for the first byte transmitted after each true to
false transition of ATN. For all subsequent bytes, TJ
is determined by equation 2 (which is equal to 1/4 of
equation 1). Refer to the Internal Counter section for
an explanation of TJ duration as a function of B2
and the clock frequency.

B, - Enable Active Low Interrupt: Setting this bit
causes the polarity of the INT pin to be reversed.

B4 - Enable RFD holdoff on GET or DEC: Setting
this bit causes RFD to be held false until the VSCMD
is written to the 8291A after any GET, SDC or DCL
commands are received. This allows the host CPU to
hold off the bus until it has completed a clear or trigger routine.

3-12. END OF SEQUENCE REGISTER

Auxiliary Register B
EC7

EC6

ECS

EC4

EC3

EC2

EC1

ECO

EOS

Auxiliary Register B is a "hidden" 5-bit register
which is used to enable some of the features of the
829IA. Whenever a 101 B4B3B2BJBo is written into
the Auxiliary Mode Register, it is loaded with the
data B4B3B2BJBo. Setting the respective bits to "1"
enables the following features:

Bo - Enable Undefined Command Pass Through:
This feature allows any commands not recognized
by the 829IA to be handled in software. If enabled,
this feature will cause the 829IA to holdoffthe hand·
shake when an undefined command is received. The
microprocessor must then read the command from
the Command Pass Through (CPT) Register and
send the VSCMD auxiliary command. The handshake holdoff will be in effect until the VSCMD command is sent.
BJ - Send EO! in SPAS: This bit enables EO! to be

The end of sequence (EOS) register and its features
offer an alternative to the "Send EO!" auxiliary
command. A seven bit ASCII character or eight bit
byte may be placed in the register to flag the end of a
block or read. The type of EOS byte to be used is
selected in Auxiliary Register A bit A4.
If the 829IA is a listener, and the "End on EOS Received" is enabled with Auxiliary Register A bit A2,
then an END interrupt is generated in the Interrupt
Status 1 Register whenever the byte in the Data-In
Register matches the byte in the EOS Register.
If the 829IA is a talker, and the "Output EO! on EOS
Sent" is enabled with Auxiliary Register A bit A"
then the EOI line is sent true with the next byte
whenever the contents of the Data Out Register
match the EOS register.

3-9

Programming Information

iSBX 488

Parallel Poll Protocol

If a subset PPI * implementation is desired, the undefined command features of the 829lA must be used.
In PPI, the 829lA is indirectly configured for Parallel
Poll by the active controller on the GPIB. The sequence of the 8291A being enabled or disabled
remotely is as follows:

Writing a 011 USP3P2PI into the Auxiliary Mode
Register will enable (U=O) or disable (U=l) the 829lA
for a parallel poll. When U =0, this command is the
"lpe" (local poll enable) local message as defined in
IEEE-488. The "S" bit is the sense in which the
8291A is enabled; only if the Parallel Poll Flag ("ist"
local message) matches this bit will the Parallel Poll
Response, PPRN, be sent true. (Response = 1 only if
"S" = "ist"). The bits P3P2PI specify which of the
eight data lines PPRN will be sent.
P3

PPR message

0
0
0
0
1
1

0
0
1

0
1

PPR1
PPR2
PPR3
PPR4
PPR5
PPR6
PPR7
PPR8

0
1

1
0
0
1
1

1
1

0
1
0
1

The PPC message is received and is loaded into
the Command Pass Through Register as an undefined command. A CPT Interrupt is sent to the
microprocessor; the handshake is automatically
held off.
The microprocessor reads the CPT Register and
sends VSCMD to the 8291A, releasing the handshake.
Having received an undefined primary command, the 829lA is set up to receive an undefined secondary command (the PPE or PPD
message). This message is also received into the
CPT Register, the handshake is held off, and the
CPT interrupt is generated.
The microprocessor reads the PPE or PPD message and writes this message command into the
Auxiliary Mode Register (bit 7 should be cleared
first). Finally, the microprocessor sends VSCMD
and the handshake is released.

GPIB
Response Line
0100
0101
0102

0103
0104
0105

0106
0107

Thus, once the 829lA has been configured for
Parallel Poll, whenever it senses both EOI and ATN
true, it will automatically compare its PP flag with
the sense bit and send PPRN true or false according
to the comparison.

*This subset of the Parallel Poll Function is defined
in the IEEE Std. 488.

If a subset PP2* implementation is desired, the "lpe"
and "ist" local messages are all that are needed.
Typically, the 829lA can be configured for Parallel
Poll immediately after initialization. During normal
operation the microprocessor will set or clear the
Parallel Poll flag (ist). The 829lA will be set up to
give the proper response to IDY (EOI and ATN)
without involving the microprocessor.

3-13. 8292 PROGRAMMING
The 8292 controller contains eight read registers,
and five write registers. Register bit identification
and their address assignments are provided in Table
3-6.

Table 3-6. 8292 Registers & Port Addresses
READ REGISTERS

WRITE REGISTERS
PORT # tHEX)

INTERRUPT STATUS

SYC

I
I

CSBS

REN

ERR

I
I
I

SRQ

USER

I
I

ERROR FLAG'
X

IFCR

TOUT,

I
I

IBF

OBF
Do

TOUT21 TOUT,

COMMAND FIELD

'X' B or
'X' F

I , I , I , I

'X' A or

I , I

I
I
I
I

'X' A or

'X' E

OAV

I
I
I
I

SYCS

SYC

I
I
I

IFC

EVENT COUNTER STATUS'
0

TIME OUT STATUS'

TCI

SYC

OBFI

IBFI

SRQ

I
I

I
I
I
I

REN

ATN

I
I
1

SRQ

'X' E

'X' A or
'X' E

:X' A or
'X' E

I~SER

'I
1

0
0
1 TOUT, 1 TOUT2 1TOUT,
I
1
EVENT COUNTER'
I

'X' A or
'X' E

NOTES:
'THIS REGISTER IS ACCESSED tREAD OR WRITTEN) BY FIRST WRITING A
SPECIFIC BYTE TO THE COMMAND FIELD REGISTER.
"THIS REGISTER MAX ALSO BE ACCESSED FOR A READ OPERATION BY
FIRST WRITING A SPECIFIC BYTE TO THE COMMAND FIELD REGISTER.

3-10

ERROR MASK"
IFC

GPIB BUS STATUS'

EOI

INTERRUPT MASK"
SPI

CONTROLLER STATUS'
CA

0
I
TIME OUT'

I
1

I
I

iSBX488

Programming Information

3-14. 8292 REGISTERS

D5 SRQ=I

The 8292 registers may be used in numerous ways
for controlling the GPIB. monitoring activity on the
GPIB. reporting timeout bus errors, and counting
bus data transfers on the bus. The registers are each
described in the following paragraphs.

D6 ERR=I

3-15. INTERRUPT STATUS REGISTER

D7 SYC=I

Service Request. Notifies the 8292
that a service request (SRQ) message has been received. It is cleared
by the lACK command.
Error occurred. The type of error
can be determined by reading the
Error Flag Register. This interrupt
flag is cleared by the lACK command.
System Controller Jumper Change.
Notifies the processor that the state
of the system controller jumper (E8EI6) has changed. The actual state
is contained in the GPIB Status
Register. This flag is cleared by the
lACK command.

INTERRUPT STATUS
SYC

ERR

SRO

IFCR

IBF

OBF
Do

The 8292 can be configured to interrupt the microprocessor for one of several conditions. Upon receipt
of the interrupt the microprocessor must read the
8292 interrupt status register to determine which
event caused the interrupt before the appropriate
subroutine can be performed. With the exception of
OBF and IBF, these interrupts are enabled or disabled by the SPI interrupt mask. OBF and IBF have
their own bits (OBFI and IBFI) in the interrupt mask
register. Each bit of the Interrupt Status Register is
described below.
DO OBF=I

Output Buffer Full. A byte is waiting
to be read by the microprocessor.
This flag is cleared when the data
byte is read. The byte to be read
originates from any of the registers:
Error Flag, Controller Status, GPIB
Bus Status, Event Counter Status,
Time Out Status, Interrupt Mask
and Error Mask.

DI IBF=I

Input Buffer Full. A byte has been
written by the microprocessor to the
8292. If another byte is written to
the 8292 before this flag clears, data
will be lost. IBF is cleared when the
8292 accepts the data byte. The
destination of the byte is to any of
the registers: Command Field, Inter
rupt Mask, Error Mask, Event Counter and Time Out.

D2 IFCR=I

Interface Clear Received. The GPIB
system controller has set IFC. The
8292 has become idle and is no
longer in charge of the bus. The flag
is cleared when the lACK command
is issued. This situation assumes
that the 8292 is not the system controller of the GPIB.

D4 EV=I

Event Counter Interrupt. The requested number of blocks or dl1-ta
bytes has been transferred. The EV
interrupt flag is cleared by the
lACK command.

NOTE
The lACK command is a utility type of command written to the Command Field Register for clearing the status bits IFCR, EV,
SRQ, ERR and SYC. See section on lACK
Utility Command.

3-16. INTERRUPT MASK REGISTER
INTERRUPT MASK

SPI

TCI

SYC

OBFI

IBFI

SRO
Do

The Interrupt Mask Register is written to directly
and is used to enable or disable (mask out) the interrupt pins OBFI, IBFI, TCI and SPI. It is also used to
enable or disable two distinct conditions SRQ and
SYC which may generate a SPI interrupt. The desired interrupt or condition may be enabled by writing a logic "I" to the appropriate register bit. Note
that the Interrupt Status Register is not affected by
the masking or unmasking of the Interrupt Mask
Register. The Interrupt Mask Register may also be
read by first writing a utility command RINM, (E5
Hex), to the Command Field Register. When the
register is read bits DI and D7 are undefined.
DO SRQ=I
D2 IBFI=l

D3 OBFI=l

Enable interrupts on SRQ received.
Enable IBF interrupt pin for input
buffer empty. Note that this interrupt is true when the IBF bit in the
Interrupt Status Register is False
(0), that is, the 8292 is ready to accept of another byte from the host
processor.
Enable OBF interrupt pin for output
buffer full. Note that this interrupt
is true when the OBF bit in the
Interrupt Status Register is true (1).
That is, a byte is waiting to be read
from the host processor.

3-11

Programming Information

D4 SYC=1

iSBX488

Enable interrupt on a change of
state of the system controller jumper
E8-EI6.
Enable TCI interrupt pin for tasks
completed. Certain commands executed by the 8292 return a TCl.
These commands are discussed in
section 3-26 and 3-27.

D5 TCI=1

D6 SPI=1

Enable SPI interrupt pin for special
occuring events. These events (IFCR,
EV, SRQ, ERR, SYC) are discussed
in the Interrupt Status Register.

NOTE
The remaining conditions for generating a
SPI interrupt are IFCR, EV and ERR. The
IFCR condition cannot be masked (always
enabled). The EV condition is enabled by
first writing an operation command, GSEC
(F4 Hex), to the Command Field Register
discussed in section 3-15. The ERR condition
is masked by writing to the Error Mask
Register (discussed later in this section).

3-18. GPIB STATUS REGISTER
GPIB BUS STATUS

REN

OAV

EOI

SYC

IFC

1 ANTI

SRO

The GPIB Status Register is used to monitor the state
of the bus lines. Note that lines SRQ, IFC, REN and
SYC are duplicated in the Controller Status Register.
This register is read by first writing a utility
command, RBST (E7 Hex) to the Command Field
Register.
DO
Dl
D2
D3

SRQ=1
ATN=1
IFC=1
SYC=1

D5 EOI=1
D6 DAV=1
D7 REN=1

SRQ Line is active low
ATN Line is active low
IFC Line is active low
SYC Line is active high
EOI Line is active low
DAV Line is active low
REN Line is active low

3-19. EVENT COUNTER REGISTER
EVENT COUNTER

1 07

3-17. CONTROLLER STATUS REGISTER
CONTROLLER STATUS

1 CSBS

1 x

1 SYCS

IFC

REN

SRO

The Controller Status Register is used to determine
the controller state of the 8292 and to monitor four
8292 lines. This register is read by first writing a
utility command, RCST (E6 Hex) to the Command
Field Register.
DO SRQ=1
Dl REN=1
D2 IFC=1
D3 SYCS=1

D6 CA=1

D7 CSBS=1

SRQ Line is active low
REN Line is active low
IFC Line is active low
System Controller Line is high (i.e.,
E8-E16 not jumpered). The 8292 is
configured for a System Controller.
8292 is the Controller-In-Charge
and is one of the three states, CACS
or CAWS or CSWS.
8292 is the Controller-In-Charge
and is in the state, CSBS.

NOTE
If both CA and CSBS are not set the 8292
will be in the CIDS state. These states are
defined by the IEEE std. 488.

3-12

1 0

DID

The Event Counter Register contains the initial
value loaded into the event counter. The counter
decrements the count on every high to low signal
transitions on pin 39 (COUNT) ofthe 8292. It may be
connected to the EOI (default jumpered EI8-EI9) or
NDAC (EI7-EI8) buffered line to count blocks or
bytes respectively during controller standby state.
The minimum count period is approximately 7.5
microseconds, the minimum high pulse width is
approximately 500ns and the minimum low pulse
width is approximately 3.0 f.1sec. This register cannot be read and is written to by first writing the utility
command, WEVC (E2 Hex), to the Command Field
Register. A value of 00 Hex = 256 counts, FFH = 255,
FEH = 254, ... etc ... and OIH = 1.

3-20. EVENT COUNTER STATUS REGISTER
EVENT COUNTER STATUS

This register contains the current value in the event
counter. The event counter decrements from the
initial value stored in the Event Counter Register to
zero and then generates an Event Counter Interrupt.
This register is read by first writing the utility command, REVC (E3 Hex), to the Command Field Register. See Figure 3-1 showing the block diagram of the
Event Counter Function.

Programming Information

iSBX488

EVENT COUNTER
REGISTER
E19
•

NDAC'

~
7.5/l118C

WEVC COMMAND
FOLLOWED BY 10 WRITE OF
INITIAL COUNT VALUE

E18 COUNT

GSEC COMMAND.
(ENABLES COUNTER)

E17
E O I ' - -__'"

minimum
REVC COMMAND
FOLLOWED BY 10 READ OF
CURRENT COUNT VALUE.

NOTE:
'BUFFERED FROM THE GPIB LINES.

Figure 3-1. 8292 Event Counter Block Diagram

3-23. ERROR FLAG REGISTER

3-21. TIME OUT REGISTER

ERROR FLAG
TIME OUT'

x
00

The Time Out Register is used to store the count
value used for the time out error function. See the
individual timeouts (TOUTl, 2, 3) to determine the
units of this counter.
This register cannot be read and it is written to by
first writing the utility command WTOUT (El Hex)
to the Command Field Register. A vlaue of OOHEX =
256 counts, FFH = 255, FEH = 254 .... etc ... D1H = 1.

3-22. TIME OUT STATUS REGISTER
TIME OUT STATUS

This register contains the current value in the time
out counter. The time out counter decrements from
the original value stored in the Time Out Register.
When zero is reached, the appropriate error interrupt
is generated. If the register is read while none of the
time out functions are active, the register will contain the value reached during the previous active
Time Out function. This register is read from by first
writing the Utility Command RTOUT (E9 Hex) to
the Command Field Register. See Figure 3-2 for a
block diagram of the Time Out Function.

USER

TOUT3

TOUT,

The Error Flag Register shows the status of the three
TIME OUT errors and the USER error. Each ofthese
flags can be enabled by writing a 1 to the corresponding bit in the Error Mask Register. This Register cannot be written and it should be read by first
writing the RERF (E4 Hex) command to the Command Field Register after the ERR bit is set in the
Interrupt Status Register.
TOUTl. Time out Error 1 is used by the GPIB
Multimodule board when attempting to receive control of the Bus, becoming CIC (Controller in Charge).
This error occurs when the controller that is passing
control of the bus has not released the ATN line for
the time period specified in the Time Out Register.
Each count in the Time Out Register is approximately 4.5 milliseconds. The count is started when
the TCNTR command (FAH) is issued to the Command Field Register. When this command is written,
the content of the Time Out Register is transferred to
the Time Out Status Register and the count-down
begins. When the count equals zero the TOUTI bit
and the ERR bit in the Interrupt Status Register are
set. After flagging the error, the 8292 will remain in
a loop trying to take control until the current controller stops sending ATN or a new command is
issued by the microprocessor. If a new command is
issued, the 8292 will execute the command and
return to the loop checking the ATN line. If a RSTI
command is issued the 8292 will stop checking ATN
and clear the ERR and TOUT bits.

3-13

Programming Information

iSBX488

PROGRAMMING INFORMATION
ATN'

,....-- - - -

COUNT'

1--- - - -

DAV'

~- - - -

LOADS INITIAL TIMEOUT
VALUE. ENABLES COUNTER.
CHECKS FOR ATN FALSE.
1 counl = 4.5 mlllisec.

TOUT1
r-- (Indicates
Error Count)

LOADS INITIAL TIMEOUT
VALUE. ENABLES COUNTER.
CHECKS FOR
COUNT TRANSITION.
1 count = 113 IJS8C

COMMAND
r-- tlndlcates
TOUT2
Error Count)

LOADS INITIAL TIMEOUT
VALUE. ENABLES COUNTER.
CHECKS FOR DAV FALSE.
1 count = 4.5 millisec

TOUT3
!-+- (Indicates
Error Count)

TCNTR COMMAND

GTSB OR GSEC

TCSY COMMAND

I
I
I

I
I
ILlENABLEl!.E0UNTE

TIME OUT REGISTER
(Loads Initial count)

WTOUT COMMAND

by 10 Write of
r-- followed
Inilial Timeout Value

!!!

TIME OU/COUNTER
DECREMENTS COUNT.
(update status)

,
I

TIME OUT STATUS
REGISTER

RTOUT COMMAND

by 10 Read of
!-+- followed
Current Timeout Value.

NOTE: 'STATUS ONLY.

Figure 3-2, 8292 Timeout Counter Block Diagram

TOUT2. The TOUT2 Error function checks for bus
activity, i.e., EO! (factory jumpered) or NDAC high
to low transitions at the COUNT input to the 8292
after the GTSB or GSEC commands are written to
the Command Field Register. The count in the Time
Out Status is decremented until there is either an
EOI transition or a count of OOH detected. IF EOI
occurs before a count of zero is reached, the count is
reinitialized and begins counting down again until
the nextEOI is encountered. If a count of zero is
reached before NDAC or EOI occurs, the TOUT2
and ERR bits will be set. Thereafter, the number of
counts will be 256 until the next EOI transition.
Each count in the Time Out Register is .appro ximately 113tJsec. Thus, for a count of 20Hex (32Decimal) the Time Out will wait 3.6 milliseconds for EOI
to become active on the bus. IF NDAC is jumpered to
COUNT instead of EOI, the byte transfer rate for a
count of 20H must be at least 1/3.6 milliseconds or
275 bytes per second,
TOUT3. Time Out Error 3 occurs when the TCSY
Command (FD Hex) is written to the 8292 and the
8292 has not succeeded in taking control because
DAV is held low (Active) longer than the value in the
Time Qut Register. The TOUT3 flag will be set when
the count in the Time Out Status Register is decre-

3-14

mented to OOH. Each count in the Time Out Register
is approximately 4.5 milliseconds. The 8292 will continue checking DAV until it becomes false, or a new
command is received. After executing the last command, the 8292 will return to checking DAV. A RSTI
command will stop the 8292 from checking ATN and
will clear the ERR and TOUT bits.
USER. User error occurs when the host CPU requests the 8292 to assert IFC or REN and the 8292 is
not the system controller.

3-24. ERROR MASK REGISTER

USER

ERROR MASK'

I TOUT, I TOUT, I TOUT, I
Do

The Error Mask Register is used to mask the ERR
interrupt from a particular type of error. Each type
of error interrupt is enabled by setting the corresponding bit in the Error Mask Register. This register can be written to directly (bits D3, D4, D6, and D7
must be low [0]. To read this register, first write the
REFM command (EA Hex) to the Command Field
Register. When. reading the Error Mask Register bits
DJ, D4, D6 and D7 are undefined.
.

iSBX488

Programming Information

:l-25. COMMAND FIELD REGISTER

RSTI - Reset Interrupts (Command = OF3H)

COMMAND FIELD

C
Do

Tht'rt' an' two categories of commands distinguished
by tht' OP (operation) bit (1)4). The first category consists of tht' operation command (OP=l). These commands initiate some activity on the GPIB. The
st'cond category is the utility commands (OP=O).
Tht'st' commands are used to aid communication
lwtween the host board processor and the 8292.

3-26. 8292 OPERATION COMMANDS
This category contains 14 commands (identified by
hex bytes FO, F1, F2, F3, F4, F5, F6, F7, F8, F9, FA,
FC, FD, and FE) for either resetting the 8292, enabling/disabling the counter interrupts or initiating
controller actions on the GPIB. These commands are
discussed below in numerical order.

SPCNI - Stop Counter Interrupts
Command = OFOH)
The 8292 will not generate an EV interrupt when the
counter reaches o. Note that the counter will continue
counting. TCI will not be set.

GIDL - Go to Idle (Command = OF1H)
If the 8292 is not the Controller-In-Charge and in
CACS, it will ignore this command and not set TCI.
Otherwise it sets ATN FALSE, enters CIDS, and sets
TCI TRUE. This command is used after the TCT
command has been sent to and accepted by another
GPIB controller, during a pass control operation.

RST - Reset (Command OF2H)
This command has the same effect as an external reset applied to the 8292 (pin #4). The resulting actions
are:

This command clears all pending interrupts and
error flags. The 8292 will stop waiting for actions to
occur (e.g., waiting for ATN to go FALSE in a
TCNTR command or waiting for the proper handshake state in a TCSY command). TCI will not be set.

GSEC - Go to Standby and Enable Counting
(Command = OF4H)
The 8292 COUNT input is jumpered to the buffered
EOI line but may be jumpered to the buffered NDAC.
When the counter reaches zero, it sets EV (and SPI if
enabled) in the Interrupt Status Register and will set
EV every 256 counts thereafter. Note that there is a
potential loss of count information if the CPU does
not respond to the EV before another EV has occurred. TCI will be set at the end of the command.

EXPP - Execute Parallel Poll
(Command = OF5H)
If the 8292 is not Controller-In-Charge, it will ignore
this command. TCI will not be set. If it is the Controller-In-Charger then it sets IDY (EOI & ATN)
TRUE. If the 8291A is configured as a listener, it will
capture the Parallel Poll Response byte in its data
register. Since TCI is not generated, the CPU must
detect the BI (Byte In) from the 8291A which serves
as a task complete indicator.

GTSB - Go To Standby (Command = OF6H)
If the 8292 is not the Controller-In-Charge, it will
ignore this command and not set TCI TRUE. Otherwise, it enters the Controller Standby State (CSBS),
sets ATN FALSE and TCI TRUE.
If a data transfer does not start within the specified
Time-Out, the 8292 sets TOUT2 TRUE in the Error
Flag Register and sets SPI (if enabled). The controller continues waiting for a new command. The
CPU must decide to wait longer or to regain control
and take corrective action.

8092 interrupt lines SPI, TCI, OBFI and IFBI
will go high (TRUE) for approximately 17.5 I1sec
before returning low. The host processor should
mask any interrupt inputs during this period.

SLOC - Set Interface to Local Mode
(Command = OF7H)

These registers will be cleared: Interrupt Status,
Interrupt Mask, Error Mask, Time Out, Event
Counter and Error Flag.

If the 8292 is the System Controller, it will set REN
FALSE for at least 100l1s and TCI TRUE. Otherwise,
it only sets the User Error Flag.

If the 8292 is the System Controller (SYC jumper
is open), then IFC will be set TRUE for approximately 100 I1sec and the 8292 will be in charge of
the bus (CACS state). If the 8292 is not the System Controller, it will enter the Idle state (CIDS
state).

SREM - Set Interface to Remote Control
(Command = OF8H)

If the 8292 is the System Controller, it will set REN
and TCI TRUE. Otherwise it only sets the User Error
Flag.

3-15

Programming Information

iSBX 488

ABORT - Abort all operations and Clear
Interface (Command = OF9H)

STCNI - Start Counter Interrupts

If the 8292 is not the System Controller this command will be ignored and the USER ERROR flag
will be set in the Error Flag Register. No TCI will
occur.

Enables the EV Counter Interrupt. TCI will not be
set. Note that the counter must be enabled by a
GSEC command.

If the 8292 is the System Controller then IFC is set
TRUE for 100 jJsec minimum, and the 8292 becomes
the Controller-In-Charge and asserts ATN. TCI will
be set, only if the 8292 was not the Controller-InCharge.

3-27. 8292 UTILITY COMMANDS

TCNTR - Take Control (Command = OFAR)
If the 8292 is not in cms it ignores this command
and does not set TCI. Otherwise it waits for the current Controller-In-Charge to set ATN FALSE. If this
does not occur within the specified Time Out, the
8292 sets TOUT1 in the Error Flag Register and sets
SPI (if enabled). It will not proceed until ATN goes
false or it receives an RSTI command. Note that the
Controller-In-Charge must previously have sent this
controller (via the 8291A's command pass through
register) a TCT message. When ATN goes FALSE
the 8292 sets ATN and TCI TRUE and enters CACS.

TCAS - Take Control Asynchronously

(Command = OFEH)

This category contains 10 commands (identified by
Hex bytes E1, E2, E3, E4, E5, E6, E7, E9, EA, and the
lACK command.) These commands are used to read
from or write to the 8292 registers that are not directly accessible.

NOTE
The Registers that are directly accessible
are the Command Field (write), Interrupt
Mask (write), Error Mask (write), and the
Interrupt Status (read).
For writing into registers the general sequence is:
1.
2.

Check for IBF = 0 in Interrupt Status Register.
Write the appropriate utility command to the
8292 Command Field Register (port XB or XF).

Write the desired register value to the 8292 (port
XA or XE) with no other writes intervening.

(Command = OFCR)

For reading a register the general sequence is:
If the 8292 is not in Standby, it ignores this command and does not set TCI. Otherwise, it arbitrarily
sets ATN TRUE and TCI TRUE. Note that this
action may cause devices on the bus to lose a data
byte or cause them to interpret a data byte as a
command byte. Both actions can result in anomalous behavior. TCAS should be used cautiously. If
TCAS fails, the System Controller may have to issue
an IFC and/or DCL.

TCSY - Take Control Synchronously

(Command = OE1H)

Wait for IBF = 0 in Interrupt Status Register.

Write the appropriate utility command to the
8292.
Wait for a TCI (Task Complete Interrupt).

Read the value of the accessed register from the
8292 register (port XA or XE).

WTOUT - Write to Time Out Register
(Command = OFDH)
If the 8292 is not in Standby,it ignores this command and does not set TCI. Otherwise, it waits for
the proper handshake state (DAV line high) and sets
ATN TRUE. The 8292 will set TOUT3 if the handshake never assumes the correct state and will
remain in this loop waiting until the handshake is
proper or a RSTI command is issued. If the 8292
successfully takes control, it sets TCI TRUE.

This is the typical way to regain control at the end of
a Send, Receive, Transfer or Serial Poll System Command. If TCSY is not successful, then the controller
must try TCAS. Refer to the description of the continuous acceptor handshake mode for the 8291A,
(section 3-11; Auxiliary Register A.)

3-16

The byte written following this command will be
loaded into the Time Out Register. Because the register is 8 bits, the maximum count is 256 time increments. When the command is complete IBF will be
set to a "0" and will cause an IBFI interrupt if
masked on.

WEVC - Write to Event Counter
(Command = OE2H)
Following this command the byte written will be
loaded into the Event Counter Register for event
counting. The counter is decremented on a high to
low transition of the COUNT input. The counter is
an 8 bit register and therefore can count up to 256
maximum.

Programming Information

iSBX488

When the 8292 has completed the command, IBF
will become a "0" and will cause an IBFI interrupt if
masked.

REVC - Read Event Counter Status
(Command = OE3H)

RERM - Read Error Mask Register
(Command OEAH)
This command enables the content of the Error Mask
Register to be read. TCI will be set.

lACK - Interrupt Acknowledge
This command enables the content of the Event
Counter Status Register to be read. The 8292 then
sets the TCI interrupt (if not masked). The CPU may
then read the value from the 8292.

RERF - Read Error Flag Register
(Command OE4H)
This command enables the content ofthe Error Flag
Register to be read. TCI will be set.

RINM - Read Interrupt Mask Register
(Command = OE5H)
This command enables the content of the Interrupt
Mask Register to be read. TCI will be set.

RCST - Read Controller Status Register
(Command = OE6H)

SYC

ERR

SRQ

IFCR
03

This command is used to acknowledge and reset any
condition of the five SPI interrupts: SYC, ERR, SRQ,
EV, and IFCR. Each bit (D2, D4-D7) is an individual
acknowledgement to the corresponding bit in the
Interrupt Status Register. The command clears SPI.
SPI will be set again if not all interrupts were
acknowledged.
If a pending User or Time Out Error occurs while an
lACK command was written, the ERR bit (D6) will
be set and thus activate the SPI interrupt (if enabled).
The TCI interrupt will also be set, indicating that the
Error Flag Register may be read directly (Read XA
or XE) without having to issue an RERF command.

An example (Figure 3-3) shows how to write and read
from registers that do not require utility commands.
The example is based on the status polling method.
This assembly language program shows how to
enable the SPI interrupt and SRQ interrupt condition.

This command enables the content of the Controller
Status Register to be read. TCI will be set.
IMR

EOU

BOH

Intrpt Mask Register, Base
Content

RBST - Read Bus Status Register
(Command OE7H)

SRO

EOU

01H

Intrpt Mask Register, SRO
Bit 00

SPI

EOU

40H

Intrpt Mask Register, SPI
Bit 06

This command enables the status of the GPIB
management lines to be read. TCI will be set.

IMP

EOU

XAH

Intrpt Mask Port No. XA or
XE

ISP

EOU

XBH

Intrpt Status Port No. XB or
XF

IBF

EOU

02H

Intrpt Status Register, IBF
Bit 01

RTOUT - Read Time Out Status Register
(Command = OE9H)
This command enables the content of the Time Out
Status Register to be read. TCI will be set.
If this register is read while a time-out function is in
process the value will be the current time-out count.
If it is read after a time-out, the content will be zero.
If it is read when no time-out function is in process
the content will contain the value reached in the
previous time-out function.

BACK:

CaNT:

ISP
IBF

Check IBF = 0

ANI
JNZ

BACK

If false, Jump Back.

MVI

A,IMR

ORI
ORI

SRO
SPI

OUT

IMP

If true continue

Unmask SRO & SPI bits

Figure 3-3. Register Read
Without Utility Command

3-17

iSBX 488

Programming Information

An example (Figure 3-4) shows how to read from a
register requiring a utility command. This particular
example shows how to read the GPIB Bus Status

RBST

EQU

OE7H

"Read Bus Status" Utility
Command

CFP

EQU

XBH

Command Field Port No.
XB or XF

BSP

EQU

XAH

Bus Status Port No. XA or
XE

GPP

EQU

X8H

8282 General Purpose Port
No.
8282 Port, TCI Line Status

*TCIS

EQU

80H

BACK:

Check IBF

ANI

ISP
IBF

JNZ

BACK

If false, Jump Back

If true, continue

CaNT:

WAITL:

WAlTH:

MVI

A, RBST

Write RBST utility command

OUT

CFP

to command Field Register.

GPP

Wait for TCI Line

ANI

TCIS

to transition high

JNZ

WAITL

to low. (i.e., command
accepted)

GPP

Wait for TCI Line

ANI

TCIS

to transition low to

WAlTH

high (i.e., task complete)

BSP

Host Processor may read
the bus Status Register

*TCI is default jumpered to line D7 of the 8282 port (X8H)

Figure 3-4. Read GPIB Bus Status Register

Table 3-7. Summary of 8292 Operation and Utility Commands
Code

Name

FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FC
FE
-

SPCNI
GIDL
RST
RSTI
GSEC
EXPP
GTSB
SLOC
SREM
ABORT
TCNTR
TCAS
TCSY
STCNI
lACK

Stop Counter Interrupts
Go To Idle
Reset
Reset Interrupts
Go To Standby and Enable Counting
Execute Parallel Poll
Go To Standby
Set Interface to Local Mode
Set Interface to Remote Control
Abort all operations & Clear Interface
Take Control
Take Control Asynchronously
Take Control Synchronously
Start Counter Interrupts
Interrupt Acknowledge

E1
E2
E3
E4
E5
E6
E7
E9
EA

WTOUT
WEVC
REVC
RERF
RINM
RCST
RBST
RTOUT
RERM

Write
Write
Read
Read
Read
Read
Read
Read
Read

to Time Out Register
To Event Counter
Event Counter Status
Error Flag Register
Interrupt Mask Register
Controller Status Register
Bus Status Register
Time Out Status Register
Error Mask Register

Tel'

IBFI

No
Yes
No
No
No
No
Yes
Yes
Yes
Note'
Yes
Yes
Yes
No
No

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No

No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

NOTE:
If the 8292 is not the System Controller, no TCI will be generated. If the 8292 is the System Controller and not Controller-InCharge, TCI will be generated after IFC has been asserted for 100 IJsec.
2 TCI will reset approximately 1.2 IJsec after a command has been written (trailing eldge of IOWR/). TCI wi" remain low for
approximately 100 IJsec to 525 IJsec, depending on the command written, before it is set.

3-18

Programming Information

iSBX 488

3-28. 8292 INTERRUPTS

3-29. 8282 GENERAL PURPOSE PORT

The 8292 controller can issue four different interrupts:

The 8282 is configured as a transparent latch, and
the contents may be read by an 110 Read to the port
hex address X8, X9, XC OR XD. Bits DO through D6
represent the status of jumpers El-E9, E2-ElO, E3Ell, E4-E12, E5-E13, E6-E14, and E7-E15 respectively. Bit D7 represents the status of the 8292 TCI
output (default juinpered E20-E27). Although the
jumper inputs to bits DO-D6 are general purpose it is
a software convenience to assign specific meanings
to these bits. That is, bits DO-D4 may represent the 5bit GPIB address while bits D5 and D6 may represent
the listen-only or talk-only mode for the iSBX 488
Multimodule Board.

OBFI
IBFI
TCI
SPI

Output buffer full interrupt.
Input buffer NOT full interrupt.
Task completed interrupt
Special interrupt

The SPI interrupt line is connected to the MINTRI
line on the iSBX bus. The other three interrupts are
jumper connected as follows:
Jumper Pair

Interrupt
OBFI
iBFl
TCI
SPI

Destination
P1-30 (OPTO)
P1-28 (OPT1)
DI7 on 8282 Latch
P1-12 (MINTR1)

E22 - E25
E21 - E26
E20 - E27

The OBFI output is asserted whenever the 8292 output buffer is full, waiting to be read. Similarly, the
IBFI output is asserted whenever the input buffer is
empty, waiting for the next data byte to be written.
The SPI output becomes active when the following
special events occur:
1.

2.
3.
4.
5.

System Controller Jumper Change.
Event Counter decrements to zero.
Service Request received.
Time Out or User error occurred.
Interface clear received

3-30. BOARD POWER ON/RESET
Mter power-on or after RESET/ at Pl-5 is asserted,
the following events occur:
•

GPIB Signal Lines. These lines are buffered by
the 8293 transceivers U4 and U6.
a.

See Figure 3-5 for a representation of the SPI interrupt logic.

Receiver Mode. The following GPIB lines
will be in a receiver mode.
DIOl-DI08
DAV
ATN (momentarily)
EO! (momentarily)
IFC (If 8292 #- System Controller)
REN (If 8292 #- System Controller)

SYC --------....
}-------,
ENABLE 111--""1-_
EV --~-'___ _
ENABLE 121 - - " " L_ _

ENABLESRQ--~-L-_~======~
/11--____,

MINTR1

I IP1-121

ERR --....-----....'____--'
ENABLE 131
IFCR--~-

141

SPI

NOTES:
1. This condition
2. This condition
3. This condition
4. This condition

is
is
is
is

)-----'

8292

iSBX
P1

/11-----------------'

enabled through the use of the Interrupt Mask Register.
enabled through the use of the FSEC (F4H) or disabled by the STCNI (FEH) Operation Command.
enabled through the use of the Error Mask Register.
always enabled.

Figure 3-5. SPI Interrupt Logic

3-19

Programming Information

Driver Mode (High Output State) The following GPIB lines will be drivers:

The Interrupt Status Registers are cleared (not
Interrupt Mask Registers).

NDAC (Open Collector off state)

Auxiliary Registers A and B are cleared.

NRFD (Open Collector off state)

The Serial Poll Mode Register is cleared.

SRQ (Momentarily)

The Parallel Poll Flag is cleared.

IFC (If 8292 = System Controller)

The EO! bit in the Address Status Register is
cleared.

REN (If 8292
8292

•

iSBX 488

= System

Controller)

NF in the Internal Counter is set to 8. This setting causes the longest possible TJ delay to be
generated in the Source Handshake (2.75 jJsec).

The following 8292 events occur:

The rdy local message is sent. (I.e., 8292 is ready
to accept a command from the host processor.)

NOTE

The initialization state is released by an "immediate execute pon" command (OOH written
into the Auxiliary Command Register).

The following events also take place following a RST command.
a.

Interrupt Outputs
TCI, SPI, OBFI & IBFI outputs will become
High during Reset active and go low immediately after Reset is inactive.
Registers Cleared:
Interrupt Status
Interrupt Mask
Error Flag
Error Mask

Software Command Reset
The 8291A and 8292 may be independently reset by
program control. The RST (F2H) command written
to the 8292 Command Field Register forces the reset
events discussed earlier. The auxiliary command
chip reset (02H) written to the 8291A forces events
discussed earlier.

Time Out
Event Counter (counter disabled)
c.

If 8292 =System Controller (i.e., Jumper off)
The 8292 ABORT command executes; and
the 8292 becomes Controller-In-Charge
(Controller Active State).

ATN transitions from receiver to driver
mode at the GPIB and is asserted active low.
EOI is reconfigured from receiver to transceiver mode. SRQ is reconfigured from driver
to receiver mode.
If 8292 =1= System Controller

3-31. BOARD INITIALIZATION
The initialization process is application dependent
(i.e., whether or not the 8292 is configured as a System Controller.

8292 remains in Controller Idle State. The
ATN, EOI, & SRQ will not change from
their previous driver or receiver mode.
•

If the 8291A is to be used solely without the
8292 central functions, the 8292 should be
configured as a non-system controller (i.e.,
install jumper E8-EI6).

8291A
The following 8291A events occur:

•

NOTE
The following events also take place following an 8291A Auxiliary Reset Command.
A "pon" local message as defined by IEEE-488
is held true until the initialization state is released.

3-20

8292
If the iSBX 488 board is to have some controller
capability (subsets CI-C28, of Table 1-1 in Chapter 1) it is necessary to enable the TCI interrupt
via the 8292 Interrupt Mask Register. The TCI
interrupt or its status may be used for interrupt
driven or polling routines respectively. The TCI
status may be read from the 8282 general purpose port.

iSBX 488

•

Programming Information

8291A
Set the initial conditions for the appropriate subsets desired (see Table 1-1 for subset list), by
writing into the Interrupt Mask, Serial Poll Mode,
Address Mode, Address all, and EOS Registers.
The Auxiliary Mode Registers should be written
to configure/unconfigure the parallel poll, preset
the internal counter for setting time Tl, and to
enable the desired functions in Auxiliary Registers A & B. Next, send the "immediate execute
pon" command to the Auxiliary Mode Register
to release the 8291A from the "initialize" state.
If the iSEX 488 board is configured as a System
Controller, the 8291A will not need its own talk
or listen address. The Address Mode Register
should be set up with Talk Only or Listen Only
capability.
If the iSEX 488 board is configured as a non-System Controller, the 8291A will have to be set up

SEQ
1
2

3
4

5
6
7

8
9
10
11
12
13

14
15
16
17
18
19
20
21
22

23
24
25
26

SOURCE
NAME

with a Talk and/or Listen Address in the Address all Register. This address may be set and
dynamically changed by using general purpose
jumpers as described in section 3-29.
Figures a-6 and :3-7 depict examples of a minimal
initialization sequence program for a system
controller and non-system controller.

3-32. SOFTWARE DRIVERS
Following initialization, the host board program
may contain individual drivers which support GPIB
functions (Talker, Listener, Device Trigger, Parallel
Enable, LOCAL, Service Request, Interface Clear,
etc.) to the capability level (subset) desired. The
Talker Routine may, for example, call a module to
send a block of data to several GPIB devices. This
module may be called SEND and is described m
Appendix A as a PL/M 80 program.

STATEMENT
SINIT

THIS PROGRAM INITIALIZES THE iSBX 488 BOARD AS A SYSTEM
CONTROLLER. BASE PORT ADDRESS (20H) IS logical OR'ed WITH THE
8291A, 8292 and 8282 PORT ADDRESS.
PUBLIC
SINIT
CSEG
A, OAOH
SINIT: MVI
OUT
2AH
;ENABLE TCI, 8292
BACK: IN
OFBH
;WAIT FOR 8292 IBF LOW
ANI
02
;BEFORE CONTINUING
BACK
JNZ
;CLEAR A
XRA
A
21H
;8291A CLEAR INTERRUPT MASK 1,
OUT
22H
OUT
;CLEAR INTERRUPT MASK 2
MVI
A,80H
;SET UP
OUT
24H
;TALK ONLY MODE, 8291A
A,06
MVI
OUT
26H
;DISABLE ADDR 0, 8291A
MVI
A,OEOH
OUT
26H
;DISABLE ADDR 1, 8291A
A,26H
MVI
;SET NF TO 6, T1 TO 2 USEC
OUT
;SET INTERNAL COUNTER, 8291A
25H
XRA
A
;CLEAR MESSAGE
;PON MESSAGE, 8291A
OUT
25H
RET
END

Figure 3-6. System Controller

~)-21

iSBX488

Programming Information

SEQ

2
3
4
5
6
7

SOURCE
NAME

THIS PROGRAM INITIALIZES THE iSBX 488 BOARD AS A NON SYSTEM
CONTROLLER WITH ADDRESSING MODE 1 BASE ADDRESS IS 20H
PUBLIC
CSEG

8
9 CINIT: MVI
10

11
12

13
14
15
16
17
18
19
20
21

22
23
24
25
26

27
28
29

STATEMENT
CINIT

OUT
BACK: IN
ANI
JNZ
XRA
OUT
OUT
MVI
OUT
IN
ANI
OUT
MVI
OUT
MVI
OUT
XRA
OUT
RET
END

CINIT

A,OAOH
2AH
OFBH
02
BACK
A

21H
22H
A,01
24H
28H
1FH
26H
A,OEOH
26H
A,26H
25H
A

25H

;ENABLE TCI, 8292
;WAIT FOR 8292 IBF LOW
;BEFORE CONTINUING
;CLEAR A
;CLEAR INTERRUPT MASK 1
;CLEAR INTERRUPT MASK 2, 8291A
;SET UP
;ADDR MODE 1, 8291A
;INPUT JUMPER ADDRESS FROM 8282
;MASK FOR TALK/LISTEN ADDRESS
;ENABLE ADDR 0, 8291A
;DISABLE AD DR 1, 8291A
;SET NF TO 6, T1 to 2 USEC
;SET INTERNAL COUNTER
;CLEAR A, 8291A
;PON MESSAGE to 8291A

Figure 3-7. Non-System Controller

3·22

CHAPTER 4
PRINCIPLES OF OPERATION

4-1. INTRODUCTION

Device Functions: Defined by the iSBC host
board functionality (including software). The
interface is the iSBX connection.

This chapter provides a brief operational description
of the iSBX 488 Multimodule Board. The functional
description of the iSBX interface, the GPIB interface
and the board's internal architecture are included in
this chapter. This chapter assumes the reader is
familiar with the published IEEE Standard 488
GPIB (1978 Version) and the Intel iSBX Bus Specification, Manual Order Number 142686.

Interface Functions: programmable functions
defined by the IEEE 488 Standard and implemented by the 8291A and 8292.

Message Coding Logic: communication to
and from the interface functions defined in terms
of messages and state linkages as implemented
by the 8291A and 8292.

4-2. FUNCTIONAL DESCRIPTION
The iSBX 488 Multimodule Board is designed to
interface a host iSBC Single Board Computer to the
IEEE 488 General Purpose Interface Bus (GPIB).
The board is divided into several hardware components as shown in Figure 4-1. Board operation is
determined by programming the 8291A and 8292
components and is application dependent. The iSBX
488 Multimodule Board in conjunction with the
iSBC host hoard may be conceptually partitioned
into the following three major areas:

The iSBX 488 Multimodule Board combines the
interface functions and the message coding within
the 8291A and 8292 microcomputers. The iSBX Bus
connector signal lines connect the device functions
to the interface functions. The connection from the
message coding logic to the driver/receiver unit is
implemented within the two 8293 transceivers. The
remaining logic supports iSBX address decoding,
interrupt line routing, clock generation, jumper selections and a general purpose jumper input port.

~TORI

iSB
CONNE

6 mhz

,-...

clock

DMA

I--@J
BlK

I.......

INTR

I
I

8291A
TAlK/
liSTEN

f
I

L.:..
ADDRESS.
SELECT.
IORIW

>---

GPIB

TRANSCEIVER & SUPPORT
lOGIC

GPIB INTERFACE
FUNCTIONS

DEVICE I
FUNCTION

8292
CONTROL

8293
XCVR

DATA

TRANSFER

8293
XCVR

MGMT

'---

DECODE

-,-

8282
BUFFER

SYSTEM JUMPER
CONTROL lOGIC

f----TAlK/
liSTEN
ADDRESS

Figure 4-1. iSBX 488™ Multimodule Board Block Diagram

4-1

Principles of Operation

4-3. iSBX BUS INTERFACE

The iSBX bus interface is grouped into six functional
classes:
a.
b.
c.
d.
e.
f.

Control Lines
Address and Chip Select Lines
Data Lines
Interrupt Lines
Option Lines
Power Lines

4-4. Control Lines. The control lines provide the
host iSBC board with a means to communicate with
the iSEX 488 board. This communication link is provided by four unique groups of lines (Command,
DMA Control, Initialize, and System Control) and
are described in the following text.

4-5. Command Lines. The Command Lines (lORDI,
10WRT I) are active low signals that provide the
communications link between the base board and
the iSBX 488 board. An active command line,
conditioned by Chip Select (MCSO/), indicates to the
iSBX 488 board that the address lines are valid and
the board should perform the specified 1/0 operation.

4-6. DMA Control Lines. The DMA Lines (MDRQT,
MDACK/) are the handshake control between the
DMA controller device on the host board and the
iSBX 488 board. MDRQT is an active high signal
output from the iSBX 488 board to the DMA controller on the host iSBC board, requesting a DMA cycle.
MDACKI is an active low input signal to the iSEX
488 board from the DMA controller, acknowledging
that the requested DMA cycle has been granted. One
byte of data is transferred between the iSBX 488
board and the host board for each DMA cycle.

iSBX 488

The base board decodes 110 addresses and generates
the chip select signals for one to three multimodule
boards. The base board decodes all but the lower
order three address bits in generating the multimodule board chip select signals. Thus, a base board
would normally reserve two blocks of 8 110 ports for
each iSBX board used.

4-10. Address Lines. Address lines MAO-MA2 are
used to select the 8 read and 8 write registers in the
829lA component. MAl and MA2 selects the 8 read
and 5 write registers in the 8292 component. MAl is
used to select the single read register of the 8282
component. See Table 3-1 of Chapter 3.

4-11. Chip Select Line. Chip select line MCSOI is
used to select the 829lA component. MCSlI is used
to enable selection of the 8292 and 8282 components
while address line MAl determines which component is actually selected.

4-12. Data Lines. Eight bidirectional data lines
(MDO-MD7) are used to transmit or receive information to or from the iSBX port. These lines are bussed
with other 110 ports on the iSBC host board and
other iSBX boards. The 829lA, 8292 and 8282 ports
are in a high impedance state unless accessed for an
10 read operation.

4-13. Interrupt Lines. The Interrupt Lines (MINTRO, MINTRl) are active high output lines used to
make interrupt requests to the host iSBC board. The
MINTRO line is generated from the 829lA INT
output. The MINTRI originates from the SPI output
of the 8292 component.

4-7. Initialize Line. The Initialize Line (RESET)
sent to the iSBX 488 board is generated by the base
board to put the iSBX 488 board in a known reset
state.

4-8. System Control Line. The System Control
Line (MPST I) is an output signal from the iSBX 488
board to the base board. The signal, identified as
Multimodule Board Present, is active low and indicates to the base board 110 decode logic that an
iSEX 488 board is installed. The MPSTI signal is
electrically grounded on the iSEX 488 board.
4-9. Address And Chip Select Lines. The iSEX
connector provides three address lines (MAO, MAl,
MA2), and two chip select lines (MCSOI, MCSlI). All
address and chip select lines are utilized by the is EX
488 Multimodule board to decode the selection of the
829lA, 8292 and 8282 components.

4-2

4-14. Option Lines. There are two option lines
(OPTO, OPTl) provided as reserve lines, that connect
to wire wrap posts on both the base board and the
iSBX 488 board. They are used for optional interrupt
lines or the TRIG line originating from the iSBX 488
board.
4-15. Power Lines. The iSBX connector provides
for the base board to supply +5, +12 Volts and ground.
However, the iSBX 488 board requires only +5 Volts
and ground.

4-16. I/O Command Operations. The 110 command lines from the base board are driven by tristate drivers with pull-up resistors or standard TTL
totem pole drivers. These lines indicate (to the iSBX
488 board) what action is being requested.

Principles of Operation

iSBX488

4-17. 1/0 Read. The I/O Read command timing is
shown in Figure 4-2. The base board generates a
valid port address and chip select for the iSBX 488
board. After the set up timings are met the host iSBC
board activates the IORD/ line. The iSBX 488 board
must put valid data on the data bus (MDO-MD7)
within 250nsec. The host iSBC board reads the data
and removes the read command, address, and chip
select signals.

MAO

4-18. 1/0 Write. The I/O Write command timing
is shown in Figure 4-3. The host iSBC board generates a valid I/O address and chip select for the iSBX
488 board. After the set up timings are met, the base
board activates the IOWRT / line. The IOWRT / line
remains active (low) for 300ns and the data is valid
for 250ns before IOWRT / is removed. The host iSBC
board then removes the data address and chip select
signals.

VALID ADDRESS

MCSI

IORDI

MDO-MD7

---------~.....________....Jx

VALID DATA

}l-------

Figure 4-2. 110 Read Timing

MAO

VALID ADDRESS

MCSI

IOWRTI

MDO-MD7

VALID DATA

Figure 4-3. 1/0 Write Timing

4-3

iSBX488

Principles of Operation

4-19. DIRECT MEMORY ACCESS (DMA)
The iSBX 488 board can be operated in DMA or non,
DMA mode. When the base board is equipped with a
DMA controller the iSBX bus will support DMA
operation, permitting the host board processor to
perform other tasks while data is being transferred.
The following timing example shows the interface
lines in their operational sequence. Because of the
similarity between aDMA read and DMA write,
only the DMA Read is illustrated, Figure 4-4.
A DMA cycle is initiated when the iSBX 488 board
activates MDREQ to the DMA controller on the base
board. Once the DMA controller gains control of the
iSBX bus, it acknowledges back to the iSBX 488
board with MDACK/. The DMA controller then activates an I/O Read cycle and the iSBX 488 board puts
valid data on the data bus (MDO-MD7) within 250
nsec from the leading edge of IORDI. The DMA controller then activates MEM WRITEI to load the Read
data into the host iSBC board memory. The MDACKI
signal acts as a chip select and address to the Multimodule board (the MCS and MAO-MAl signals are
unrletermined as they are driven by the memory
address). The iSBX 488 board removeS the MDRQT
during the cycle to stop the DMA cycle. Once the read
operation is complete the DMA controller deactivates
the read command providing a data hold time. If the
DMA request signal was removed, the DMA controller will release the iSBX bus back to the host processor and remove MDACK/. If the request is not removed, the DMA controller will proceed to another
DMA cycle.

4-20. GPIB INTERFACE FUNCTIONS
There are ten (10) interface functions specified by the
IEEE 488 standard. Not all devices will have all
functions and some may only have partial subsets.

The ten functions are sUlrimarized below With the
relevant section number from the IEEE 488 document given at the beginning of each paragraph. For
further information please see the IEEE standard.
1.

SH - Source Handshake (IEEE section 2-3)
This function provides a device with the ability
to properly transfer data from a Talker to one
or more Listeners using the three handshake
lines.
AH - Acceptor Handshake (IEEE section 2-4)
This function provides a device with the ability
to properly receive data from the Talker using
the three handshake lines. The AH function
may also delay the beginning (NRFD) or end
(NDAC) of any transfer.

T - Talker (IEEE section 2-5) This function
allows a device to send status and data bytes
when addressed to talk. An address consists of
one (Primary) or two (Primary and Secondary)
bytes. The latter is called an extended Talker.

L - Listener (IEEE section 2-6) This function
allows a device to receive data when addressed
to listen. There can be extended Listeners (analogous to extended Talkers above).

SR - Service Request (IEEE section 2-7) This
function allows a device to request service
(interrupt) the Controller. The SRQ line may be
asserted asynchronously.

RL - Remote Local (IEEE section 2-8) This
function allows a device to be operated in two
modes: Remote via the GPIB or Local via the
manual front panel controls.
PP - Parallel Poll (IEEE section 2-9) This
function allows a device to present one bit of
status to the Controller-In-Charge. The device
need not be addressed to talk and no handshake is required.

SOURCE

SIGNAL

ISBX BD

MDRQT

BASE BD

MDACKI

f~~ ______________________~r--

BASE BD

lORD!

frf----~\~________________~/

BASE BD

MEM WRITE

MDOoMD7

\~~-------------------

-----ift-f---------"'\

---------1(~___....Jx

ISBX VALID READ DATA

Figure 4-4. DMA. Read Timing

4-4

I
)

Principles of Operation

iSBX 488

DC - Device Clear (IEEE section 2-10) This
function allows a device to be cleared (initialized) by the Controller. Note that there is a difference between DC (device clear) and the IFC
line (interface clear).

DT - Device Trigger (IEEE section 2-11) This
function allows a device to have its basic operation started either individually or as part of a
group. This capability is often used to synchronize several instruments.

10.

C - Controller (IEEE section 2-12) This function allows a device to send addresses, as well
as universal and addressed commands to other
devices. There may be more than one controller
on a system, but only one may be the ControllerIn-Charge at anyone time.

At power-on time the controller that is wired to be the
System Controller becomes the active Controller-InCharge. The System Controller has several unique
capabilities including the ability to send Interface
Clear (IFC - clears all device interfaces and returns
control to the System Controller) and to send Remote
Enable (REN - allows devices to respond to bus data
once they are addressed to listen). The System Controller may optionally Pass Control to another controller, if the system software has the capability to
do so.
4-21. CODING LOGIC
All GPIB related signals (i.e., DIOl-DI08, DAV, EOI,
ATN, SRQ, IFC, NDAC, NRFD, and REN) at internal nodes have a slash (I) suffix to indicate that the
low voltage state equals a logicall. These signals are
buffered by U4 and U6, 8293 non-inverting transceivers, for GPIB interfacing. The I suffix is removed
from the signals at the GPIB interface, however the
logical definition does not change. Refer to the
schematic diagram in Figure 5-2.

and U4. T/R2 is an output from U5 and an input to
U6. The 829lA may send EIOI as an END remote
message over the GPIB indicating the end of a
multiple byte transfer sequence, or in conjunction
with ATN/, receive an EOIl during a parallel poll
sequence. T/R2 controls the send/receive direction
of EOIl at U6. EOIl will normally be received from
the GPIB whenever another GPIB device is sending
an END message and the 829lA is addressed to
listen. ATNI is monitored by the 829lA to interpret
the data on the DIOI lines. ATNI and EOIl are
ANDed within U 4 to control the type of output (tristate or open collector) on DIOl-DI08 and DAV
lines. These lines will have tristate outputs at all
times except when both ATNI and EOIl are low
(logical "I"). Whenever the 8292 is the Controller-InCharge of the GPIB the ATNI line is forced high by
U6. If the 8292 is not the Controller-In-Charge the
ATNI level will be determined by ATN from the
GPIB.

COUNT INPUT TO 8292
This input monitors EOIl or NDACI (EOIl by
default jumper). Every low to high transition of
EOIl (or NDAC/) increments a counter internal to
the 8282. A count of EOII (or NDAC/) transitions
represent the number of data blocks (or bytes) that
have taken place. The minimum period allowed for
consecutive transitions is 7.5 microseconds. If the
8292 is he active Controller of the GPIB, a GSEC
command written to the 8292 will force the 8292 to
standby state, CSBS, and then enable the internal
counter and corresponding Event Counter Interrupt.
When the 8292 is not the active Controller a GSEC
command will exit immediately. The interrupt may
be disabled by a SPCNI command written to the
8292 or when the 8292 exits CSBS. However the
counter will continue to count transitions.
REN/, IFC/, SYC

DI01/-DI08/, DAV/, T/Rl
The DATA (1-8)/ and DAVI lines are bidirectional.
T IRI is an output of U5 (829lA) which controls the
transmit!receive direction for these signals at U4
and U6 (8293). The 829lA sends and receives data
(over DIO lines) for both the Talker/Listener (829lA)
functions and the Controller (8292) function. The
DAVI is sent by the 829lA during a Source Handshake and received during an Acceptor Handshake
function. The 8292 sends a DAVI during a Parallel
Poll and monitors DAVI during a "Take Control
Synchronously" function.
EOl/, ATN/, T/R2
EOIl is bidirectional to U5 (829lA), bidirectional to
U6 (8293), and input to U4 (8293), and an input to U3
(8292). ATN I is an output from U6 and inputs to U5

RENI is an output of U3 (8292), an input to U5
(8291A), and bidirectional to U6 (8293). IFCI is bidirectional to both U3 and U6 and an input to U5. SYC
is pulled high by RPI (12 K ohm) or shorted low by a
jumper, and it is an input to U3 and U6. The 8292
monitors SYC to determine its initialization sequence
at power on. If the 8292 input is the System Controller (SYC = High = 1) it will execute an ABORT Command, become the Controller-In-Charge, and enter
the CACS state. If it is not the System Controller, it
will remain in CIDS. SYC also controls the transmit!
receive direction of RENI and IFC/ at U6. When
SYC is High both IFCI and REN I is transmitted on
the GPIB from U6, where both are controlled by the
8292. The 829lA monitors IFCI and RENI whether
it be sourced from the 8292 or from the GPIB. The
8292 only monitors IFCI when it is not the System
Controller.

4-5

Principles of Operation

NRFDI, NDACI, TIRl
NRFDI and NDACI are both bidirectional to U5
(8291A) and U6 (8293). The transmit/receive direction of both signals are controlled by T IRI (at 8291A).
When T IRI is High, both signals are received from
the GPIB while the 8291A is in a Source Handshake
sequence. When T/RI is Low, both signals are transmitted to the GPIB while the 8291A is in an Acceptor
Handshake sequence.
SRQI, ATNI/, ATNOI, IFCLI, CLTHI, CICI
SRQI is an input to U3 (8292), an output from U5
(8291A) and bidirectional to U6 (8293). ATNII is an
output from U6 and an input to U3. ATNOI is an
output from U3 and an input to both U6 and U4
(8293). IFCLI is an output from U6 and an input to
both U3 and U 4. CLTH and CICI are both outputs
from U3 and both inputs to U6. The 8291A may send
SRQI during a Serial Poll sequence to the 8292 andl
or out to the GPIB through U6. The 8292 receives
SRQI from the 8291A and/or from the GPIB through
U6. The transmit/receive direction for SRQI at U6 is
determined by several other signals as discussed
later. The ATNII signal is monitored by the 8292. Its
source is either from ATN off the GPIB or from the
ATNOI signal controller by the 8292. The source for
generating ATNII is determined by several other
signals as discussed later. IFCLI is monitored by the
8292 when it is not the System Controller (SYC =
Low). IFCLI is a latched low output from U6 when-

4-6

iSBX488

ever an off-board System Controller sends IFC. The
latch is cleared High after the 8292 sends CLTH
(High pulse) to U6. ATNOI, IFCL!, and T/RI are
gated in U4 to control the direction ofDAV/. If the
8292 is the Controller-In-Charge conducting a Parallel Poll sequence the 8291A must capture the Parallel
Poll Response for the 8292. The 8291A becomes a
listener while the 8292 asserts DAV I. T/Rl, IFCL/,
and ATNOI are gated such that the DIOI lines are
received by the 8291A while DAVI is neither transmitted nor received by U4. The direction control for
SRQI and the source for generating ATNII is determined by CICI and IFCL/. If IFCLI is not latched
Low or has just been cleared and CICI is Low, then
SRQI is a buffered output from SRQ, and ATNOI is
the source for both ATNII and ATN outputs. If
IFCLI is latched Low or CICI is High, then SRQI is
an input buffer driving SRQ, and ATN is the source
for both ATNI and ATNII.

EOl21
EOI2! is bidirectional to both U3 (8292) and U6
(8293). The 8292 sends or monitors EOI2! during a
Parallel Poll sequence. The transmit/receive direction of EOI2I is controlled by ATNOI and IFCL/. If
the 8292 is conducting a Parallel Poll both ATNOI
and E0I21 is asserted Low by the 8292. ATNOI Low
enables E0I21 to be transmitted as EOI on the GPIB
except when IFCLI is latched Low by the System
Controller.

CHAPTER 5
SERVICE INFORMATION

5-1. INTRODUCTION
This chapter provides the following service related
information:
a. ,Repair assistance information.
b. Replacement parts list and diagram.
c. Jumper post location diagram.
d. Schematic diagrams.

5-2. SERVICE AND REPAIR ASSISTANCE
United States Customers can obtain service and
repair assistance by contacting the Intel Product
Service Hotline in Phoenix, Arizona. Customers outside the United States should contact their sales
source (Intel Sales Office or Authorized Distributor)
for service information and repair assistance.

Always contact the Product Service Hotline before
returning a product to Intel for repair. You will be
given a repair authorization number, shipping
instructions, and other important information which
will help Intel provide you with fast, efficient service.
If you are returning the product because of damage
sustained during shipment or if the product is out of
warranty, a purchase order is required before Intel
can initiate the repair.

In preparing the product for shipment to the Repair
Center, use the original factory packing material, if
possible. If this material is not available, wrap the
product in a cushioning material such as Air Cap
TH - 240, manufactured by the Sealed Air Corporation, Hawthorne, N.J. Then enclose in a heavy duty
corrugated shipping carton, and label "FRAGILE"
to ensure careful handling. Ship only to the address
specified by Product Service Hotline personnel.

Before calling the Product Service Hotline, you
should have the following information available:
a.
b.

d.
e.

Date you received the product.
Complete part number of the product (including
dash number). On boards, this number is usually
silk-screened onto the board. On other products,
it is usually stamped on a label.
Serial number of product. On boards, this number is usually stamped on the board. On other
products, the serial number is usually stamped
on a label.
Shipping & billing addresses.
If your Intel product warranty has expired, you
must provide a purchase order number for billing
purposes.

5-3. REPLACEMENT PARTS
A complete list of replacement parts is provided in
Table 5-1. This list provides the part number, manufacturer, description and quantity of the item. Notice
that each item is referenced in the parts location diagram. Table 5-2 provides the full name of the manufacturer which is abbreviated in Table 5-1. Some of
the parts are available from any normal commercial
source, and should be ordered by their generic
description. These items are called out as CML,
rather than listing a specific part number. Figure 5-1
shows the location of each iSBX 488 referenced part
in Table 5-1.

If you have an extended warranty agreement, be
sure to advise the Hotline personnel of this
greement.

Use the following numbers for contacting the Intel
Product Service Hotline:
TELEPHONE
All U.S. locations, except Alaska, Arizona, & Hawaii:
(800) 528 - 0595
All other locations: (602) 869 - 4600
TWX NUMBER: 910 - 951 - 1330

5-4. SERVICE DIAGRAMS
Figure 5-2 provides a schematic diagram of the iSBX
488 Multimodule Board. The schematic diagrams are
current when the manual is printed. However, minor
revisions to the diagrams may occur between manual
printings. Therefore, Intel provides photocopies of
the current schematic diagrams with the board,
when it is shipped from the factory. These diagrams
should be inserted into this manual for future reference. In most instances, the diagrams shipped with
the board will be identical to those printed in the
manual.

5-1

Service Information

.. jSBX488
Table 5-1. Replacement Parts List

------------------------------------~------------------------------------------

Ref

Description

Part Number

Manllfacturer

Cl-6
C7

Capacitor, Cere Z5U AXL .10 uf
Capacitor, Tant. 22 uf 15v, 10%

OBD
OBD

CML
CML

6
1

Oscillator, Crystal 6MHz

HY-4550-6

Hytek

Connector, iSBX Multimodule 36 pin

292-0001

Viking

Rl-2
RP1

Resistor, 470 ohm, 1/8W, 5%
Resistor Pack, 10-pin 12K

OBD
OBD

CML
CML

2
1

Octal Latch
Hex Inverter
GPIB Controller
GPIB Transceiver
GPIB Talker/Listener
2 Input Positive OR Gate

8282
74LS04
8292
8293
8291A
74LS32

Intel
TI
Intel
Intel
Intel
TI

U2
U3
U4, 6
U5
U7

1
1
1

2
1
1

-----------------------------------------------~------ -------------------------

Table 5-2. Manufacturers' Names

Abbreviation
Hytek
Viking
TI
CML
OBD

5-2

Description
Hytek Microsystems, Inc.
Viking Connectors, Inc.
Texas Instruments, Inc.
Any commercial source
Order by description

iSBX488

Service Information

NO.

1-'l2'62.l

.... REV

DESCRIPTION

E.CO

"'10 - 2.044

B ECO "'10- 2183

).1d\RStDE.

@--

IUOTE':>:
I.
l.

U,,"lE<;S

O''''ER.IN'~E.

PAR.T

~UM.BE_K

PAR.T~

Uoe:. T Prt.!\.IO

WORKMA,,"~\'!IP

"PEC.IFIED

\.tJ,'2.'i'2..'l -002. THIS DOC.UMENT ..
WIRE. U~ T
I\R.E \i!!.~tKIM(... D OC.UMEl\l."lS

PER.

"''' -0001 -001.

AS~E.MBl'
OIlS\.! ,,"UMBER. MJO REV LEVEL W,T'"
COI\J"TRASTINC:t PER.Mft..ftJEr\.lT COLOR J t..JOI\.l- tONOUCTIVE J

M"ilK.

.11. ... tC, ..... !>.PPR.Ol
M.~R.K.

WHERE <; ,-lOW t\!.

ASSEM.BLY VEI\lOOR..

PER.MAf\l~I\l"

I'.PPRDlt

WITH

C.OI\l.TRASTIt..1C."

c...OLOR., fUDtu-t.OfoJDU(TI\lE

.12 HIG.H",

INHERE ';HOWN.

SEE S£PARA,!:: PAR..TS

LIST

!>.ND

W IR.E

LIST
DESCRIPTION

UNLESS OTHERWISE SPECIFIED;

L DIMENSIONS ARE IN INCHES.

NEXT ASSY

~'iq

USED ON

...

SlGNATU

2. 8R£AK ALL stWtP EDGES.

CHI(

3. DO NOT SCAlE DRAWING.

APVD
APVD

.1OL£IIANClSo
ANGlES _ _

1"'12 74 l:lf5X

PARTS UST

XX±_
XXX±_
SURFACe FINISH

""TE
'/Z
" <

inteI"

3DSS lOWERS AYE.
BAHT, ClARA
CALlF.1!III5l

TInE

PRIIUTE-D WIR.I~C, IISSEM!3LV,
Go PI B IIUT£R.FI>.c..E-

APYD

.
."

SHEET

5
OFI

Figure 5-1. iSBX 488™ Multimodule Board Parts Location Diagram

5-3/5-4

Service Information

iSBX488

3
ZONE REV

DESCRlPTlON

1"SV

~2E>e2

""""-"'"

MOO I D0
0101 2e. DIOI/
0101/ ?<; DATAI<;Zl BU
DIal
p 1-.::0
P I - 3 I (------I~~~ 11;02
DI03i!DI03/
10 DATA!:>
BU5!:~
MD2, P 1-29~
IMD1 II:> D3
DIO'! 10104/
1lI04 9 OATA5
BU55~
MD.3, P I - ,,7(------~5
17 D4
0105
DD~51.1
ilia
OAT.... 4
BUS-'I{b Dl05
~-.II D-~, P 1-25~
~D5
uS
~
fDJOIo/7C~ATA3
""'~~115DI06
MD5, P I - 2.3<'IA-D'/:> '1-8
DIOb ~ DIO''!
1
OJ"""~
"""'..,
M D Ib, P 1-21f--t"'D7 19 Db B291A D107~
I~:J 6 c DATA a 6U52P DID7
~ D7
010 l;.35 DIOS/
~ DATA I
6Uslrl""-"'DI"'o"'e"'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~1 co DIO I
MD7, P 1-19f--~-____;,--------..,--+.t'-;.'A7:'_·7;_';::l~ R5
T/R I p - 1 : : ; - - - - - - - - - - - - - - - . . - - - - - : c L . . j 1 T/RI
J 1~4: DIO "MAQt>, P
MAl
""1'151
DAY
3b
?f.
DATA")
l-b,D:l:03
I'v'IAI,P
MAO;
:::3
R52
EO!
~
3
EOl
U4
r"-v'lA2, P 1- 7
ATN ao
4 ATN 82.9.3
J 1- e., DIO-4
lORDI, P 1- 15 ~-----_ - - - - - H ' - t _ + - - : 4
7
"2.
4
JI-12,DA'I
MDACKt P 1-3~ r l - - -......-H1+----06'=lDACK/
TIRO: r2~5::-++h
U7 Ib
REN ~
~74LS.32.
+5Y
P1-I2, MINTP.I
MDRQT, P 1-,34 ~---+......Hc-t_+--'''-IORE.Q
~TRI6
CL
DII:>'"'7_ _ __+-4-1-t-+-+--+_+---+T""'O~N_:E~7,_o
~MD5 l..q D05 U I D15P.b' ! - - - _ + -.......I---+-+--+-+'-t---:L""O;;;N;.-E=.I:>:;.o
7
~MD4 15 DO-4 6282 m..q r5;-_ _
-- D03
D13 r.4;;--_ __ + - - - -....+-+'-t---:A;';D4;,;-;:E-4:::-o
fMD2 17 002
DI2p-:?>:---_+-----....-+_+---:A"'O="'3,..;E'='300
~MDI la DO I
Dl I f-'2.~_ __ + - - - - - -....._+---:A"'D:-72.'cE~2=o
MD<;Z>,

t--......,DI

D"'~

,"" "D'

li~",e

i=~.d

...s.

~:::::::::::::::::::::::::::::::::t~~~:::t::::::::::I~1

!:~~

rr=r=
llo

~~ !

~5~ ~c

+ __

~------------------ri_+++_t--------++--_++~rt++----------------~M~D0~~19oo¢

DI¢rl~----+--------------

17 D5
la Do

~D7

MI'

.3 EOJ:
s~'"'_::c.=I+--H~---------+=E.::.:.Te=-...:~=II9.:.....-l';e~

COUNT

, - - - - - - I.....+---'5='cjRD
L....-+.=;:;:-..JI":a~yyp.
13.lJ<::4~LSM2

3b IBFI
XI!-'2==--t--H_+-+-------'
++_--,.3",2.=tTC I
5P I ,.".33=-+-_H_+_+-------_+-'
-4. RESET
tMD¢ 12 D0 U3
tMDI 13 DI eaQ2.

R~';:;""3el

IFC
ATNO
ATNI
EOT
IFeR
CIC
CLTH

DATA~
A

BUSbrle~----_I----------------------t-------------.------- ) JI-IIQ, NDAC
8U55rI7~----_I~--------------------t-------------------------------------~JI-14, NRFD

~~It::>7------1L....--------------------t-------------------------------------~ JI- 20, SRQ

BUS2r.1:?>~----_t--------------------+-------------------------------------7 JI-

23
2.9
2.2.
3"1
I
31
2.7

,= DATAe

BUS7~19~----~---------------------I--------_-_----------------------------~) JI - 22,ATN
~~15~----+--------____------+__------____________--------------~.JI- 10, EO!

,~.~ ~~~ OPTA~
6

9, REN

BUSI~12~----~---------------------I--------------------------------------_7 JI-15,IFC

U(:,

II DATA7 6<9.3
7 D"o-TA3
~ DATAI INTERFACE
LSBX-4ee
R. .

"'EET

USED ON

3OIi5 BOWERS AVE.
SANTA ClARA
CALlf.95Q51

14252q

7" 5BX"168

NEXT ""'"

inteI

C
""I

Figure 5-2. iSBX 488™ Multimodule Board Schematic Diagram

5-5/5-6

iSBX 488

Service Information

1
REVISIONS
DESCRIPTION

ZONE

toc.o

D
PIN I

PI CONNECTOR

SPECIFIED

I. P~RT NUMBER IS 142505-001. THIS DOCUMENT

o
[JJ

IT]

P2 CDI\lNtc.TOR
SIDE VIEW

SIDE VIEW

tIlOTE9; UNLESS OTUERWI9E

I )>------------------« I
Z)
( I,.

AND PARg LIST ARE TRACKING DOCUMENTS,

MARK P~RT NUMBER AND REVISION LEVEL WIT~
CDIHRMTING PERMANENT COLOR, .12 HIG~,
APPRDXIMATELY WfiERE ~\-\OWlJ.

CONTRASTING PH?MAIIlENT
COLOR •• 12 HIGH. APPRDXI MATELY WHERE SHOW~.
WORKMAWH11P PER 9Q-0007-00 I
MAR k REFEREN CE OESIG.NAT ION WITI-4 CONT RASTI NG
PERMANENT CDLOR, .1'2. HIGI-I, APPROXIMATELY
WHERE G\-\OWN.
SEfjARATE 2 SPARE CONDUCTORS NOT TERMll\JATfD
APPROXIMAiELY ONE INCH IN FRDM CABLE EtJD.

MP-.Rk VE\\JDOR ID WITI-!

:»

(

"I )

(

1)
'i!)

( 4
( 110

q)
10)

(

>
>
>

(1
( I'!

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19

( 2J

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< Il
.KATE PI\R"TS

LI:,"T

DESCRIPTION

PART NUMBER

@] PIN

NO_ I STRI PE IS OPTIONAL AND MUST
BE ORIENTATED AS SHO\,NN IF USED.

"IO-W"I"I

PARTS LIST
3065 BOWERS AVE.
SANTA CLARA
CALIF. 95051

L DIMENSIONS ARE IN

INCHES.
2. BREAK ALL SHARP
EDGES.

3. 00 NOT SCALE

~~t:'r!:~CES!

ANGLES

:!::

~±.~
NEXT ASSY

9300019

USED ON

2·

~R~c11~INISH 7'

ENGR

I-!A~PV~D!.l:!::.a.W!tl~pi!flOo7H, oaSH. OeOH);

'II/

WAIT$T:PROCEDURE EXTERNALi
END WA IUT;
I.

'II/

SEND:PROCEDUP.E (LISTENHTP.,[lATA$PTR . COUHT . EOS) PUBLIC;
DECLARE (LISTEH$PTR,DATASPTR) ADDRESS;
DECLARE (COUNT.EOS) BYTE;
DECLARE LISTENER BASED lISTEN$PTR BYTE;
DECLARE DATUM BASED DATASPTR BYTE;

2
2

/.
/*

18
19
20

2
2
2

21
22
23
24
25

2
3
3
3
J

26
27
28

2
2
2

29
30
31
32
33
34

2
3
3
3
3

J5
36

'.2
2
2
2

39
40

41
42
43

2
2

A-2

BEGIN PROGRAM HERE

'II/

1* SEND MY TALK ADDRESS *;

OUTPUTCDATASOUT) = MTA:

WAIT$BO;
1* WAIT FOR 90 BrT SET IN 8291A *1
OUTPUT(OATA$OUT) = UNL;
;* SEND UNIVERSAL UHLISTEN *1
CAlL WAIUBO;
OUTPUTCEOS$REG) = EOS;
1* LOAD EOS IN 91A EOS REG'll/
1* ADDRESS LISTENERS */
DO WHILE «LISTENER )= 20H) AHD (LISTENER (= 3EH»;
OUTPUT(OATA$OUT) = LISTENER;
CALL WAIUBO;
LISTENSPTR = LISTENtPTR + 1;
END;
/* THEN GO TO STANDBY'll/
OUTPUT(CHOSREG) = GTSB;
CALL WAITSTJ
1* WAIT FOR Tel lOW THAN HIGH*I
OUTPUT 0) AND (DATUM () EOS»;
OUTPUT
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