144779 001_i SBC_80_16_Hardware_Reference_Manual_Aug82l 001 I SBC 80 16 Hardware Reference Manual Aug82l
144779-001_iSBC_80_16_Hardware_Reference_Manual_Aug82l manual pdf -FilePursuit
144779-001_iSBC_80_16_Hardware_Reference_Manual_Aug82l 144779-001_iSBC_80_16_Hardware_Reference_Manual_Aug82l
User Manual: 144779-001_iSBC_80_16_Hardware_Reference_Manual_Aug82l
Open the PDF directly: View PDF 
.
Page Count: 132
| Download | |
| Open PDF In Browser | View PDF |
•
iSBC® 80/16
SINGLE BOARD COMPUTER
HARDWARE REFERENCE
MANUAL
•
Order Number: 144779-001
•
•
,.
•
I
Copyright©1982, Intel Corporation
Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051
I
REV.
-001
Original
REVISION HISTORY
Issue
DATE
8/82
•
•
•
Additional copies of this manual or other Intel literature may be obtained from:
Literature Department
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
The information in this document is subject to change without notice.
Intel Corporation makes no warranty of any kind with regard to this material, including, but not
limited to, the implied warranties of merchantability and fitness for a particular purpose. Intel
Corporation assumes no responsibility for any errors that may appear in this document. Intel
Corporation makes no commitment to update nor to keep current the information contained in this
document.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied
in an Intel product. No other circuit patent licenses are implied.
•
Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use,
duplication or disclosure is subject to restrictions stated in Intel's software license, or as defined in
ASPR 7-104.9 (a)(9).
No part of this document may be copied or reproduced in any form or by any means without prior
written consent orIntel Corporation.
The following are trademarks of Intel Corporation and its affiliates and may be used only to identify
Intel products:
BXP
CREDIT
i
ICE
iCS
im
iMMX
Insite
ii
Intel
Inlel
Intelevision
Inten""
iOSP
iRMX
iSBC
iPDS
iSBX
Library Mana.er
MCS
M....ctwai.
Micromainframe
Mircromap
Multibus
Multichannel
Multimodule
Plul-A-Bubble
PROMPT
RMX/80
System 2000
UPI
•
A901 / 283/ 3K DO
PREFACE
•
•
•
This manual provides general information, installation and setup
instructions, programming guidelines for the on-board, programmable
devices, board level principles of operation, and service information for
the iSBC 80/16 Single Board Computer. Related information is provided in
the following publications:
•
iSBC® Applications Manual, Order NUmber: 142687
•
Intel Multibus® Specification, Order NUmber: 9800683
•
Intel Multibus® Interfacing, Application Nbte, AP-28A
•
•
MCS-80 Assembly Language Programming Manual,
•
Intel iSBX· Bus Specification,
•
Designing iSBX-Multimodule- Boards, Application Nbte AP-96
•
Using the iRMX- 80 Operating System, Application Nbte AP-86
•
In tel Component 1B ta Ca talog
•
The MCS 80/85 Family Users Manual
~der
Number: 9800640
PL/M 80 Programming Manual, Order NUmber: 9800466
~der
Number: 142686
NOTE TO READERS
•
This hardware reference manual uses a visual scheme to denote section
levels, rather than a numerical scheme used in many technical documents •
This visual scheme allows you to more readily identify which section
headings are sub-sections. The visual distinction among the different
sizes used in the paragraph headings indicates what level or order a
particular paragraph occupies. Refer to the Table of Contents to see how
the paragraph levels compare to each other •
•
iii
•
•
•
•
•
•
•
CONTENTS
PAGE
CHAPTER 1
GENERAL INFORMATION
Introduction •••••••••••••••••••••••••••••••••••••••••••••••••••••••
Ilescription •••••.••••••••.••••••.•..•.•..•••..••••....•••.•••.••...
System Software Development ••••••••••••••••••••••••••••••••••••••••
Equipment Supplied •••••••••••••••••••••••••••••••••••••••••••••••••
Equipment Required •••••••••••••••••••••••••••••••••••••••••••••••••
Specifications ••••••••••••••••••••••••••••••••••••• '••••••••••••••••
•
CHAPTER 2
PREPARATION FOR USE
Introduction ••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Unpacking and Inspection ••••••••••••••••••••••••••••••••••••••••••••
Installation Considerations •••••••••••••••••••••••••••••••••••••••••
Power Requirements ••••.•.•••••••••••.••.
Cooling Require.ents ••••••••••••••••••••••••••••••••••••••••••••••
Physical Dimensions •••••••••••••••••••••••••••••••••••••••••••••••
t
•
•
••••••••••••••••••••••••••
User-Furnished Components •••••••••••••••••••••••••••••••••••••••••
User-Furnished Component Installation•••••••••••••••••••••••••••••
Memory Device Installation ••••••••••••••••••••••••••••••••••••••
Line Driver Installation ••••••••••••••••••••••••••••••••••••••••
Jumper Configurations •••••••••••••••••• ,•••••••••••••••••••••••••••
On-Board Memory Configuration •••••••••••••••••••••••••••••••••••••
Decode PROM Operation Select ••••••••••••••••••••••••••••••••••••
Installing EPROM Devices Onto The Board •••••••••••••••••••••••••
Installing 2708 EPROM Devices Onto The Board ••••••••••••••••••••
Installing Static Byte~ide RAM Devices Onto The Board ••••••••••
Installing E2pROM Devices Onto The Board ••••••••••••••••••••••••
80/l0A and 80/1OB Mu1tibus Interface Emulation Configurations •••••
Shadow Memory Configurations ••••••••••••••••••••••••••••••••••••••
Ready Circuitry Jumper Configuration••••••••••••••••••••••••••••••
Baud Rate Generator Jumper Configuration ••••••••••••••••••••••••••
8255A PPI Jumper Configuration••••••••••••••••••••••••••••••••••••
Interrupt Jumper Configuration ••••••••••••••••••••••••••••••••••••
8251A PC I and Serial Interface Jumper Configuration •••••••••••••••
Timeout Jumper Configuration ••••••••••••••••••••••••••••••••••••••
Mu1tibus Interface Jumper Configuration •••••••••••••••••••••••••••
Mu1tibus Interface Information ••••••••••••••••••••••••••••••••••••••
Signal Characteristics ••••••••••••••••••••••••••••••••••' ••••••••••
•
1-1
1-2
1-4
1-4
1-4
1-4
Auxiliary (P2) Interface Information ••••••••••••••••••••••••••••••••
Parallel I/O Interface Information ••••••••••••••••••••••••••••••••••
Parallel I/O Cabling Requirements •••••••••••••••••••••••••••••••••
Serial I/O Interface Information ••••••••••••••••••••••••••, ••••••••••
Serial I/O Cabling Requirements •••••••••••••••••••••••••••••••••••
iSBX Bus Interface Information ••••••••••••••••••••••••••••••••••••••
iSBX Mu1timodu1e Board Installation •••••••••••••••••••••••••••••••••
iRMX 80 System Software •••••••••••••••••••••••••••••••••••••••••••••
Final Installation ••••••••••••••••••••••••••••••••••••••••••••••••••
v
2-1
2-1
2-1
2-2
2-2
2-2
2-3
2-8
2-9
2-11
2-13
2-19
2-19
2-19
2-22
2-22
2-23
2-26
2-26
2-27
2-28
2-29
2-31
2-32
2-33
2-33
2-34
2-34
2-44
2-45
2-48
2-49
2-49
2-51
2-52
2-54
2-54
CONTENTS (continued)
PAGE
CHAPTER 3
PROGRAMMING INFORMATION
Introduction •••••••••••••••••••••••••••••••••••••••••••••••••••••••
Memory Addressing ••••••••••••••••••••••••••••••••••••••••••••••••••
I/O Mdressing ..••••••••..•••••••••••••••••••..•••••.••••• '••....•••
System Initialization ••••••••••••••••••••••••••••••••••••••••••••••
825lA PCl Programming ••••••••••••••••••••••••••••••••••••••••••.•••
Mode Instruction Word Format •••••••••••••••••••••••••••••••••••••
Sync Characters ••••••••••••••••••••••••••••••••••••••••••••••••••
Command Instruction Word Format ••••••••••••••••••••••••••••••••••
Reset ..••••••••••••••••...••.••••••••..•••••.•...•.••• '•••••••••
Addressing .••.•••••••••..•..••••••••..•••.•••••••••••.••••••••.
Initialization •••••••••••••••••••••••••••••••••••••••••••••••••
825SA PPI Programming ••••••••••••••••••••••••••••••••••••••••••••
PPI Control Word Format ••••••••••••••••••••••••••••••••••••••••••
Mdresslng •••••••••••••••••••••••••••••••••••••••••••••••••••••••
Initialization •••••••••••••••••••••••••••••••••••••••••••••••••••
Operation ••••••••••••.••••••••••••••••••••••••••••••••••••••••.•.
3-1
3-1
3-2
3-2
3-4
3-4
3-7
3-7
3-8
3-8
3-8
3-13
3-13
3-15
3-15
3-16
•
•
CHAPTER 4
PRINCIPLES OF OPERATION
Introduction ••••••••••••••••••••••••••••••••••.•••••••••••••••••••••
Clock Circuits •••••••••••••••••••••••••••••••••••••••••••••••••••••
Central Processing Unit (CPU) Group ••••••••••••••••••••••••••••••••
Serial I/O Interface •••.••••••••••••••••••••••••••••••••••••••••••.
Parallel I/O Interfaces ••••••••••••••••••••••••••••••••••••••••••••
JEDEC-COmpatible Memory ••••••••••••••••••••••••••••••••••••••••••••
Chip Select Decode Logic •••••••••••••••••••••••••••••••••••••••••••
iSBX Mu1timodu1e Board Interfaces ••••••••••••••••••••••••••••••••••
Multibus Interface •••••••••••••••••••••••••••••••••••••••••••••••••
ibId 8f!quence ••••••••••••••••••••••••••••••••••••••••••••••••••••
Interrupt Sequence •••••••••••••••••••••••••••••••••••••••••••••••
4-1
4-2
4-2
4-3
4-4
4-5
4-5
4-6
4-6
4-7
4-7
CHAPTER 5
SERVICE INFORMATION
Introduction •••••••••••••••••••••••••••••••••••••••••••••••••••••••
Replaceable Parts •••••••••••••••••••••••••••••••••••••••••••••••••.
Se rvice Diagrams ................................................... .
Service And Repair Assistance ••••••••••••••••••••••••••••••••••••••
5-1
5-1
5-1
5-4
•
•
APPENDIX A
DECODE PROM PROGRAMMING
Introduction •••••••••••••••••••••••••••••••••••••••••••••••.•••••••
Decode PROM Function Description •••••••••••••••••••••••••••••••••••
Programming Option 8 •••••••••••••••••••••••••••••••••••••••••••••••
PROM Data Definitions ••••••••••••••••••••••••••••••••••••••••••••••
vi
A-1
A-1
A-2
A-2
•
CONTENTS (continued)
•
FIGURES
1-1.
2-1.
2-2.
2-3.
2-4.
2-5.
iSBC 80/16 Single Board Computer •••••••••••••••••••••••••••
iSBC 80/16 Board User-Furnished COmponent Locations ••••••••
Memory Device Installation •••••••••••••••••••••••••••••••••
JEDEC MeIIory Socket Pairs ••••••••••••••••••••••••••••••••••
JEDEC Memory Socket Configuration Examples •••••••••••••••••
2-6.
Memory Configuration Jumper Matrix {Typical) •••••••••••••••
Typical Configurations •••••••••••••••••••••••••••••••••••••
Multibus Memory and I/O Timing (WRITE) •••••••••••••••••••••
Multibus Memory and I/O Timing (READ) ••••••••••••••••••••••
Multibus Control Exchange Timing •••••••••••••••••••••••••••
Spacer Installation Technique •••••.•••••••••••••••••••••••••
iSBX Multimodu1e Board Orientation •••••••••••••••••••••••••
Memory Map (as-shipped configuration) ••••••••••••••••••••••
PCI Synchronous Mode Instruction Word Format •••••••••••••••
PCI Synchronous Mode Transmission Format •••••••••••••••••••
PCI Asynchronous Mode Instruction Word Format ••••••••••••••
PCI Asynchronous Mode Transmission Format ••••••••••••••••••
PCI Command Instruction Word Format ••••••••••••••••••••••••
Typical PCI Initialization and Data I/O Sequence •••••••••••
2-7.
2-8.
2-9.
2-10.
2-11.
•
•
2-12.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
4-1.
5-1.
5-2.
A-1.
A-2.
A-3.
Jumper Location Diagram••••••••••••••••••••••••••••••••••••
PCl Status Read Format •••••••••••••••••••••••••••••••••••••
PPI Control Word Format ••••••••••••••••••••••••••••••••••••
PPI Port C Bit Set/Reset Control Word Format •••••••••••••••
Functional Block Diagram•••••••••••••••••••••••••••••••••••
iSBC 80/16 Board Parts Location Diagram ••••••••••••••••••••
iSBC 80/16 Board Schematic Diagram (Sheet 1 of 10) •••••••••
Ten-bit PROM Address Creation ••••••••••••••••••••••••••••••
I/O Map In The Decode PROM •••••••••••••••••••••••••••••••••
Memory Map In The Decode PROM ••••••••••••••••••••••••••••••
1-1
2-4
2-9
2-10
2-11
2-13
2-25
2-25
2-41
2-42
2-43
2-53
2-53
3-2
3-5
3-5
3-6
3-6
3-7
3-9
3-12
3-15
3-16
4-1
5-5
5-7
A-3
A-4
A-5
TABLES
•
1-1.
Specifications •••••••••••••••••••••••••••••••••••••••••••••
2-2.
User-Furnished Connector Information•••••••••••••••••••••••
Parallel Port Receiver/Driver Socket Assignment ••••••••••••
Jumper Listing By Numerical Order ••••••••••••••••••••••••••
Memory Address Ranges/Configurations Allowed At Each
Socket By Each Decode PROM Operating Mode ••••••••••••••••
EPROM Jumper Configurations ••••••••••••••••••••••••••••••••
2708 EPROM Jumper Modifications ••••••••••••••••••••••••••••
Static RAM Jumper Configurations •••••••••••••••••••••••••••
E2PROM Jumper Configurations •••••••••••••••••••••••••••••••
E2pROM Jumper Functions ••••••••••••••••••••••••••••••••••••
Emulation Mode Select Jumpers ••••••••••••••••••••••••••••••
SHADOW PROM Jumper Connections •••••••••••••••••••••••••••••
Wait-state Jumper COnfiguration 2 •••••••••••••••••••••••••••
Baud Rate Configuration For Rate Generator •••••••••••••••••
Parallel Port Jumper Configuration For U19•••••••••••••••••
Parallel Port Jumper Configuration For U20 •••••••••••••••••
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
2-13.
2-14.
•
2-15.
2-16.
vii
1-5
2-7
2-12
2-14
2-20
2-21
2-22
2-23
2-24
2-24
2-26
2-27
2-28
2-29
2-30
2-30
TABLES (continued)
PAGE
2-17.
2-18.
2-19.
2-20.
2-21.
2-22.
2-23.
2-24.
2-25.
2-26.
2-27.
2-28.
2-29.
2-30.
2-31.
2-32.
2-33.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
5-1.
5-2.
A-1.
Interrupt Source Jumper Configurations •••••••••••••••••••••
Serial Interface Jumper Configurations •••••••••••••••••••••
Mu1tibus Interface Jumper Options ••••••••••••••••••••••••••
Connector P1 Pin Assignments •••••••••••••••••••••••••••••••
Conector P1 Signal Descriptions ••••••••••••••••••••••••••••
P1 Connector DC Characteristics ••••••••••••••••••••••••••••
P1 Connector AC Characteristics With Continuous Bus Control
P1 Connector AC Characteristics with Bus Control Exchange ••
Auxiliary Connector P2 Pin Assignments •••••••••••••••••••••
Parallel I/O Connector J1 Pin Assignments ••••••••••••••••••
Parallel I/O Connector J2 Pin Assignments ••••••••••••••••••
Parallel I/O Connector J1 DC Characteristics •••••••••••••••
Parallel I/O Cabling Information•••••••••••••••••••••••••••
Serial I/O Connector J3 Pin Assignments ••••••••••••••••••••
RS232C Cable Types •••••••••••••••••••••••••••••••••••••••••
iSBX Bus Connector J4 And J5 Pin Assignments •••••••••••••••
iSBX Bus Signal Descriptions •••••••••••••••••••••••••••••••
I/O Port Addresses •••••••••••••••••••••••••••••••••••••••••
Typical PCI Mode or Command Instruction Subroutine •••••••••
Typical PCI Data Character Read Subroutine •••••••••••••••••
Typical PCI Data Character Write Subroutine ••••••••••••••••
Typical PCI Status Read Subroutine •••••••••••••••••••••••••
Parallel I/O Interface Configurations ••••••••••••••••••••••
Typical PPI Initialization Subroutine ••••••••••••••••••••••
Typical PPI Port Read Subroutine •••••••••••••••••••••••••••
Typical PPI Port Write Subroutine ••••••••••••••••••••••••••
Replaceable Parts ••••••••••••••••••••••••••••••••••••••••••
Manufacturer's Codes •••••••••••••••••••••••••••••••••••••••
Data Entries For The Decode PROM •••••••••••••••••••••••••••
2-31
2-32
2-33
2-35
2-36
2-37
2-39
2-40
2-45
2-46
2-47
2-48
2-49
2-50
2-50
2-51
2-52
3-3
3-10
3-11
3-11
3-12
3-14
3-17
3-17
3-17
5-1
5-3
A-3
•
•
•
•
•
viii
•
CHAPTER 1.
1-1.
GENERAL INFORMATION
INTRODUCTION
The iSBC 80/16 Single Board Computer is a complete computer system that
is designed around the 8-bit 8080A-l MOS microprocessor, clocked at a
rate of 2.048 MHz.
•
•
The iSBC 80/16 board provides an iSBC 80/1OB board replacement for many
applications. The board contains 6 JEDEC-compatible memory chip sockets
(for installation of up to 64k bytes of user-provided memory), a serial
communications port providing an RS232C interface, two parallel I/O ports
providing 48 individual I/O lines, two iSBX Bus connectors providing
functional expansion by interfacing to all 8-bit iSBX Multfmodule boards,
and a Multibus interface supporting 8-bit data transfers. The board is
shipped with 2k bytes of Static RAM installed into one of the
JEDEC-compatible memory sockets.
The iSBC 80/16 board is compatible with the Multibus interface when the
board is operated as the only master on the interface, and requires the
use of a special Multibus interface control exchange mechanism if used
with another bus master. The board receives one interrupt signal from
the Multibus interface and is configurable for operation as a limited bus
master in a system environment. Compatibility of the iSBC 80/16 board
with the iSBC 80/1OB board includes compatibility with most of the
software designed for the iSBC 80/1OB board.
•
•
Figure 1-1.
iSBC· 80/16 Single Board Computer
1-1
GENERAL INFORMATION
1-2.
DESCRIPTION
The iSBC 80/16 Single Board Computer, shown in Figure 1-1, is an I/O
intensive processor board designed around the 8080A-1 cpu. The
iSBC 80/16 board can be configured for compatibility with the software
and hardware functions provided by the iSBC 80/10B board, except for the
current loop operation, AACK/ support, 2758 EPROM support, and 110 baud
operation on the serial interface.
•
The features of the iSBC 80/16 board are listed in the following text.
cpu
*
8080A-1
*
Software compatible with the iSBC 80/1OB Single Board Computer in
most applications.
*
Six JEDEC-compatible 24/28 pin sockets for installation of up to 64k
bytes (maximum) of memory onto the board; 2k bytes of Static RAM is
shipped with the board.
*
Two iSBX Bus connectors providing interfaces to all 8-bit iSBX
Multimodule boards.
*
48 programmable parallel I/O lines on two I/O connectors (J1 and J2)
via the 8255A Programmable Peripheral Interface devices.
*
1 interrupt signal from the Multibus interface via the EXT INTR1/
signal line.
*
1 serial RS232C-compatible I/O port provided via the 8251A
Programmable Communications Interface device.
*
Mu1tibus interface compatibility.
providing operation at 2.048 MHz clock frequency.
The 8080A-1 CPU is a 40-pin LSI device providing an interface with 8-bit
systems. The 808~-1 CPU contains six 8-bit general purpose registers.
The 8-bit registers may be addressed individuallY or in pairs, providing
both single and double precision operators. The 808~-1 CPU supports a
wide range of addressing modes and data transfer operations, and logical
operations. The architecture of the 8080A-1 CPU allows you to control
the address and data busses via the HOLD signal, a derivitive of the Bus
Priority In signal (BPRN/) on the Multibus interface.
Two iSBX Bus interfaces are available on the iSBC 80/16 board via the J4
and J5 connectors. The iSBX Bus connectors allow expansion of the
functionality of the iSBC 80/16 board in small increments by installing
Multimodule boards such as the iSBX 311 Analog Input Multimodule Board,
the iSBX 328 Analog Output Multimodule Board, the iSBX 350 Parallel I/O
Multimodule Board, the iSBX 351 Serial I/O Multimodule Board, the
iSBX 331 Fixed/Floating Point Math Multimodule Board, the iSBX 332
Floating Point Math Multimodule Board, and others. Each iSBX Bus
connector is capable of interfacing to only 8-bit iSBX Multimodule boards.
1-2
•
•
•
•
GENERAL INFORMATION
•
•
•
The iSBC 80/16 board can hold a maximum of 64k bytes of memory in six
JEDEC-compatible memory sockets. The six 24/28 pin IC sockets accommodate
user-installation of read only memory, electrically erasable memory, or
static RAM devices. The sockets may be filled with different memory
components in three independent sets of two sockets. Configuration jumpers
allow memory device size increments of 2k, 4k, Sk, or 16k bytes.
The iSBC 80/16 board includes 48 programmable parallel I/O lines
implemented by means of two Intel 8255A-.5 Programmable Peripheral
Interface (PPI) devices. The I/O signals are jumper selectable to many
combinations of unidirectional input/output and bidirectional ports. The
I/O interface may be customized to meet specific peripheral requirements
and, in order to take full advantage of the large number of possible I/O
configurations, IC sockets are provided for installation of user-supplied
I/O line drivers and terminators. This further enhances the flexibility
of the parallel I/O interface by allowing combinations of optional line
drivers and terminators to provide the required sink current, polarity,
and drive/termination characteristics for each application. The 48
programmable I/O lines and signal ground lines are available at two 50-pin
edge connectors (J1 and J2).
The RS232C-compatible serial I/O port at connector J3 is controlled and
interfaced by an Intel 825lA Programmable Communications Interface (PCI)
device. Integrated circuits U13 and U14 on the iSBC 80/16 board provide
the serial RS232C interface termination for the J3 interface. The PCI is
individually programmable for operation 1n synchronous or asynchronous
data transmission modes •
In the synchronous mode the following features are programmable:
a.
b.
c.
Character length,
Sync character (or characters), and
Parity.
In the asynchronous mode the following features are programmable:
•
•
a.
b.
c.
d.
Character length,
Baud rate factor (clock divide ratios of 1, 16, or 64),
Stop bits, and
Parity.
In both the synchronous and asynchronous modes, the serial I/O port
features half- or full-duplex, double buffered transmit and receive
capability on an RS232C compatible interface. In addition, PCI error
detection circuits can check for parity, overrun, and framing errors. The
PCI transmit and receive clock rates are supplied by a jumper selectable
baud rate generator. These clocks may optionally be supplied from an
external source. The RS232C command lines, serial data lines, and signal
ground lines are brought out to a 26-pin edge connector (J3).
Multibus interface control requests from another bus master are sensed in
the iSBC 80/16 board via the Bus Priority In (BPRN/) signal. The jumperconfigured signal can suspend 8080\-1 CPU operation while the other master
accesses the Mu1tibus interface resources. Note that this bus exchange
timing on the iSBC 80/16 board is not compatible with the requirements
described in the INTEL MULTIBUS SPECIFICATION (see Figure 2-10).
1-3
GENERAL INFORMATION
1-3.
SYSTEM SOFTWARE DEVELOPMENT
The development cycle of iSBC 80/16 Single Board Computer based products
may be significantly reduced using an Intel Intellec Series II
Microcomputer Development System (MDS) with an ISIS-II software package.
The ISIS-II Software package includes the high level programming language
PL/M 80. PL/M 80 allows programming in a natural, algorithmic language
and eliminates the need to manage register usage or memory allocation.
The programs can be written in a much shorter time than Assembly Language
programs for a given application.
•
Program develoJ;ment may be performed on the In tel Personal Development
System (iPDS) products, however, the iPDS products do not provide the
ability to emulate as does the MDS.
1-4.
EQUIPMENT SUPPLIED
Each iSBC 80/16 board is shipped with a current revision of the schematic
diagram for the board. Insert the current revision drawing into this
manual. NO other equipment is provided with the iSBC 80/16 board.
1-5.
EQUIPMENT REQUIRED
A list of components required to configure the iSBC 80/16 board is
provided in Chapter 2. Because the iSBC 80/16 board is designed to
satisfy a variety of applications, the user must purchase and install
only those components required to satisfy his particular needs.
1-6.
•
•
SPECIFICATIONS
Specifications of the iSBC 80/16 Single Board Computer are listed in
Table 1-1.
•
•
1-4
GENERAL INFORMATION
•
Table 1-1.
CPU
•
•
Intel 808CV\.-l
WORD SIZE
Instruction:
Data:
Address:
•
Specifications
8, 16, or 24 bits.
8 bits.
16 bits.
SYSTEM CLOCK SPEED:
2.048 MHz +0.1%
INSTRUCTION CYCLE TIME
At 2.048 MHz:
1950 nanoseconds •
MEMORY ARRAY
On-board Memory:
6 JEDEC-compatible chip sockets hold
user-provided memory devices in 1kx8, 2kx8,
4kx8, 8kx8, 16kx8, or 32kx8 capacity. Sockets
must be configured in pairs; 3 independent
pairs possible:.
Note: Installation of 1kx8 and 32kx8 devices
requires programming a decode PROM. Refer to
Table 2-5 for a list of devices supported by
the decode PROM in the as-shipped configuration.
On-board Static RAM:
JEDEC-compatible Static RAM devices; either
2kx8 or 8kx8. One 2k by 8 Static RAM is
provided in socket U45. Refer to paragraph
2-12 for more information.
On-board E2pROM:
JEDEC-compatible E2pROM devices in socket
pair U43/U44 and/or U45/U46. Refer to
paragraph 2-12: for more information.
MAXIMUM MEMORY
ADDRESS RANGE
64k bytes; 0000 to FFFFH. Addresses at each
JEDEC-compatible memory socket depends on the
type of decode PROM operation selected.
I/O CAPABILITY
•
Parallel:
48 programmable I/O lines using two 8255A PPI
devices and pa.rallel I/O connectors J1 and J 2.
Serial:
1 programmable RS232C-compatible interface
using the 825lA PCI device.
Expansion:
2 iSBX Bus connectors providing expansion via
either single-wide or double-wide 8-bit iSBX
Multimodu1e boards.
1-5
GENERAL INFORMATION
Table 1-1.
•
Specifications (continued)
SERIAL COMMUNICATIONS
CHARACTERISTICS
Synchronous:
5 to 8 bit characters; internal or external
character synchronization; automatic sync bit
insertion.
As ynchronous :
5 to 8 bit characters; break character
generation; 1, 1 1/2, or 2 stop bits; false
start-up detection.
Baud Rates:
Output
Frequency
(in kHz)
Baud Rates
Sync Mode
Asynchronous Mode
(xl)
(x16 )
(x64)
-------
307.2
153.6
76.8
38.4
19.2
9.6
4.8
38400
19200
9600
4800
---
460.8
230.4
115.2
57.6
28.8
14.4
7.2
---
---
---
28800
14400
7200
19200
9600
4800
2400
1200
600
300
--14400
7200
3600
1800
900
450
4800
2400
UOO
600
300
150
75
7200
3600
1800
900
450
225
112.5
•
•
•
PHYSICAL CHARACTERISTICS
Width:
length:
Thickness:
Weight:
30.48 em. (12.00 in.)
17.15 cm. (6.75 in.)
1.27 em. (0.50 in.)
371 gm. (13.0 oz.)
•
1-6
GENERAL INFORMATION
•
!able 1-1.
Specifications (continued)
ENVIRONMENTAL REQUIREMENTS
Operating Temperature:
Relative Humidity:
to 90%, non-condensing
ELECTRICAL CHARACTERISTICS
DC Power Requirements:
•
•
+5V
iSBC 80/16 boar d 1
Without memory devices
+12V
-5V2
(All voltages +/- 5%)
Lcc=1.95A
Idd=160mA
-12V
Ibb=OmA
Iaa=100mA
Notes: 1. EKc1udes power requirements for byte-wide devices, I/O
driver/terminator devices, and iSBX Mu1timodu1e boards.
2. The Vbb power is required only when using 2708 EPROM devices •
•
•
1-7
•
•
•
•
•
•
•
•
•
CHAPTER 2.
2-1.
PREPARATION FOR USE
INTRODUCTION
This chapter provides instructions for preparing the iSBC 80/16 Single
Board Computer for use in a user-defined environment. Included in this
chapter are instructions on unpacking and inspection; installation
considerations; component installation; jumper configuration; interface
configuration for the Multibus, the iSBX bus, the parallel I/O, and the
serial I/O interfaces; connector information; serial I/O cabling
information; parallel I/O cabling information; and board installation
information. Ensure that you have a firm understanding of the contents
of the entire chapter before beginning the configuration and installation.
2-2.
UNPACKING AND INSPECTION
Inspect the shipping carton immediately upon receipt for evidence of
mishandling during transit. If the shipping carton is severely damaged
or waterstained, request that the carrier's agent be present when the
carton is opened. If the carrier's agent is not present when the carton
is opened and the contents of the carton are damaged, keep the carton and
the packing material for the agent's inspection.
For repair to a product damaged in shipment, contact the Intel Product
Service Center to obtain a Return Authorization Number and further
instructions. Telephone numbers for the various centers are listed in
Chapter 5 of this manual. A purchase order will be required to complete
the repair. A copy of the purchase order should be submitted to the
carrier with your claim.
It is suggested that the salvageable shipping cartons and packing
material be saved for future use in the event that the product must be
shipped.
When unpacking your iSBC 80/16 board, you: will find a current copy of the
schematic drawing for the board. Place that copy of the schematic
drawing into this manual.
2-3.
INSTALLATION CONSIDERATIONS
Installation considerations such as power requriements, cooling
requirements, physical size requirements, and user-furnished components
for the iSBC 80/16 board are outlined in the following paragraphs.
•
2-1
PREPARATION FOR USE
2-4.
POWER REQUIREMENTS
The iSBC 80/16 board normally requires a +5 volt (1.95 A) power source, a
+12 volt (160 mA) power source, and a -12 volt (100 mA) power source.
The iSBC 80/16 board uses the -12 volt supply and an on-board regulator
to provide a local -5 volt power source for the 8080A-l CPU. All
voltages, including the -5 volts for the 2708 devices, are drawn from the
Multibus interface.
•
The +12 volt power is required for the clock generator device, the
8080A-l CPU, and the RS232C interface driver. The -12 volt power is
required for the RS232C interface receiver and for the -5 volt
regulator. The current requirements for the +12 volt and the +5 volt
supplies increase if an iSBX Multimodule board is installed.
2-5.
COOLING REQUIRMENTS
The iSBC 80/16 board dissipates 937 (maximum) gram-calories of heat per
minute (3.79 BTU per minute) with all worst case memory devices and iSBX
Multimodule boards installed. Adequate circulation of air must be
provided to prevent a temperature rise above 55°C (131°F). Typically, a
minimum air flow of 200 linear feet per minute will satisfy these cooling
requirements. The system chassis units available from Intel include fans
that provide adequate intake and exhaust of ventilating air.
2-6.
PHYSICAL DIMENSIONS
The outside dimensions of the iSBC 80/16 board are as follows:
a.
b.
c.
Width:
Length:
Thickness:
30.48 cm (12.00 inches)
17.15 cm (6.75 inches)
1.27 cm (0.50 inch)
2.91 cm (1.16 inches) board with
iSBX Multimodule board
Greater detail of the outside dimensions of the iSBC 80/16 board may be
obtained from the INTEL MULTIBUS SPECIFICATION.
•
•
•
•
2-2
PREPARATION FOR USE
•
•
2- 7.
USER ~URNISHED COMPONENTS
The user-furnished components required to configure all intended
applications of the iSBC 80/16 board are listed in Table 2-1. !able 2-2
contains a list of the connector manufacturers from which you may obtain
parts to interface with the PI, P2, J1, .12, J3, J4, and J5 connectors on
the iSBC 80/16 board. Cable configuration information for serial I/O
connector J 3 and parallel I/O connectors J 1 and J 2 is listed in paragraph
2-30 through 2-33. Figure 2-1 shows the mounting locations on the
iSBC 80/16 board for each of the user-provided components. fuly those
components required to satisfy the application need be installed.
When installing the integrated circuit packages into the sockets on the
iSBC 80/16 board, ensure that pin 1 of the chip is oriented closest to
the white dot (indicating pin 1 of the socket) that is silk-screened onto
the board •
If installing 24-pin devices into the
28-pin EPROM sockets, refer to
paragraph 2-9 for installation
information •
•
•
•
2-3
~
Port A Driver/Terminators
Port C Driver/Terminators
~
Port B Driver/Terminators
E2PROM Timing Caracitor
Installation Sites (4
Port B Driver/Terminators
1'1
CD
N
J
I-'
•
....CIl
t::d
C"l®
00
o
U3
I -'
0'\
~
U2
b:I
o
~
IU
1'1
Q.
N
J
~
~
000000000000000000
000000000000000000
000000000000000000
000000000000000000
iSBX™ Connector J4
iSBX™ Connector J5
H
H
CD
~
I
1
o
I
~
1'1
1:1
....
CIl
;:;1'
CD
Q.
Iz;I
~
opg
l
(
p
c::
Cf.I
tz:I
(
C"l
o
U42
~
U43
U44
U45
U46
8CD
1:1
r1'
~
S
IU
....o
(')
r1'
1:1
CIl
Decode Prom
•
JEDEC - Compatible Memory Sockets (6)
•
•
1002
•
•
PREPARATION FOR USE
•
Table 2-1.
Item
No.
Function
De scription
I
iSBC 604/614
iSBC 608/618
Modular Backplane and Cardcage. Provides power input and
Includes 4 or 8 slots with bus Multibus signal interface
between the CPU board and
terminators.
up to 15 other boards.
2
Connector
(mates
with P1)
See Multibus Connector details
in Table 2-2.
3
Connector
(mates
with P2)
See Auxiliary Connector details Used for special interface
in Table 2-2.
functions.
4
Memory
Chips
2, 4, or 6 each of the
following types:
EPROM
2708
1kx8
2716
2kx8
2732A
4kx8
2764
8k.x8
27128 16kx8
32kx8 (when available)
Ultraviolet Erasable PROM
(EPROM) for dedicated
program storage. Use of
2708 devices is restricted
to four sockets.
2, 4, or 6 each of the
following2 t ypes: Static
RAMs or E PROM devices,
in capacities as follows:
E2PROM or Static RAM
for data storage. Refer
to paragraph 2-9. Use of
E2 pROM devices is restricted to four sockets.
•
•
Item
User-Furnished Components
•
STATIC and E2PROM
Power inputs and Multibus
signal interface. Not
required if the CPU board
is installed in an Intel
cardcage/backplane.
2kx8
8kx8
•
5
Connector
(mates
with J3)
See serial connector cabling
details in Table 2-2.
Provide compatible cables
for serial I/O interface
to the 825LA PCI device.
6
Connector
(mates
with J1,J2)
See parallel connector cabling
details in Table 2-2.
Provide compatible cables
for parallel I/O signal
interface to the 8255A PPI
devices.
2-5
PREPARATION FOR USE
Table 2-1.
Use r-Furnished Component s (continued)
Item
lb.
Item
7
Une
Drivers
8
Line
Terminators
Function
~scription
Number
SN7403
SN7400
SN7408
SN7409
SN7437
SN7438
Type
I, OC
I
NI
NI, OC
I
I, OC
Current
16 mA
16 mA
16 mA
16 mA
48 mA
48 mA
The parallel I/O ports
E5, E6, E8, E9, and EA
are affected. Requires
two line drivers for each
8-bit parallel output port.
Interface parallel I/O ports E5, E6, E8, E9, and EA with
Intel 8255t\ PPI devices. Requires two iSBC 901 Dividers
(220/330 ohm) or two iSBC 902 Pull-Ups (lk ohm) for each
8-bit parallel input port.
+5V
220
iSBC 901
iSBC 902
,"
~ 330
9
10
External
Timing
Capacitors
Line Iriver
Receiver
Capacitors C32, C33, C34, and C35 provide timing functions
required when installing 2817 E2PROM devices into memory
chip sockets U43, U44, U45, and U46, respectively. Refer
to manufacturer's specifications for capacitor values.
!bte that 2817A E 2pROM device do not require
installation of these capacitors.
The iSBC 80/16 board includes an inverting 8287 Octal Bus
Transceiver in socket U2 as the interface to port A of
Connector J1. The interface may be configured for
non-inverting operation by installing an 8286 Octal Bus
Transceiver into the socket at U2.
2-6
•
•
•
•
•
PREPARATION FOR USE
•
•
•
•
Table 2-2.
Connector
Type
Function
It of
Pins
Parallel
Connectors
(Jl,J2 )
25/50
0.1
Wirewrap
Parallel
Connectors
(J1, J2)
25/50
0.1
Soldered
Parallel
Connectors
(Jl,J2)
25/50
Centers
Inches
Vendor
Name
TI
VIKING
H311125
3VH25/lJND5
AMP
TI
2-583485-6
H312125
2VH25/1JV5
VIKING
0.1
Flat Crimp
Vendor
Number
3M
88083-1
609-5015
3415-0000 (ears)
3415-0001 (w/o ears)
AMP
ANSLEY
3M
Serial
Connector
(J3)
13/26
0.1
Wirewrap
TI
H311113
Serial
Connector
(J3)
13/26
0.1
Soldered
TI
AMP
H312113
1-583485-5
Serial
Connector
(J 3)
3M
13/26
0.1
Flat Crimp
AMP
ANSLEY
3462-0001
88106-1
609-2615
Mu1tibus
Connector
(PI)
43/86
0.156
Soldered
VIKING
ELFAB
VIKING
2KH43/9AMK12
BS1562D43PBB
2VH43/lAV5
ELFAB
EDAC
ELFAB
EDAC
BW1562D43PBB
337086540201
BW1562A43PBB
337086540202
ELFAB
EDAC
BS1020A30PBB
345060524802
Multibus
Connector
(PI)
•
User-Furnished Connector Information
Auxiliary
Connector
(P2)
43/86
0.156
Wirewrap
30/60
0.1
Soldered
2-7
PREPARATION FOR USE
Table 2-2.
Function
Auxiliary
Connector
(P2)
iSBX Bus
Connector
8-bit
No tes:
2-8.
II of
Pins
User-Furnished Connector Information (continued)
Centers
Inches
30/60
0.1
36
0.1
Connector
Type
Vendor
Name
Vendor
Number
Wirewrap
ELFAB
EDAC
TI
VIKING
BS1020D30PBB
345060540201
H421121-30
3KH30/9JNK
Soldered
VIKING
VIKING
000292-0001 male
000291-0001 female
Pin numbers appearing on the connector may not agree with the
numbers on the board; notice that the even pin numbers are on the
component side of the parallel and serial I/O connectors.
Wirewrap pin lengths are not guaranteed to conform to Intel
packaging standards.
USER-FURNISHED COMPONENT INSTALLATION
Instructions for installing the user-provided components (memory and line
driver/terminator devices) onto the iSBC 80/16 board are contained in the
following paragraphs. When installing these components, ensure that pin 1
of the component is closest to the white dot indicating pin 1 of the
respective IC socket, unless otherwise noted.
CAUTION
All MOS devices such as EPROM and RAM
devices are highly susceptible to
damage from static electricity. Use
extreme caution when installing MOS
devices in a low humidity environment.
Always ground yourself before handling
MOS devices to ensure that a static
charge build-up is not dissipated
through or around the MOS devices.
•
•
•
•
•
2-8
PREPARATION FOR USE
•
•
•
2-9.
Memory Device Installation
A maximum of 64k bytes of memory may be installed into the JEDEC-compatib1e
memory sockets U41 through U46 on the iSBC 80/16 board and may consist of
several different types of memory devices. Possible memory devices that
can be installed onto the board include EPROM devices, E2PROM devices,
and Static byte-wide RAM devices. Howeve!r, in selecting memory devices for
installation into the memory sockets, you must adhere to two restrictions:
1) the memory sockets must be jumper-configured in pairs, and 2) not all
types of devices may be installed into each chip socket.
The iSBC 80/16 board contains six JEDEC memory sockets into which you can
install memory devices. Sockets U41 and U42 accept all types of EPROM and
Static RAM devices. In addition to these types of devices, the sockets at
U43, U44, U45, and U46 also accept E2PROM devices. If 2708 EPROM devices
are installed, the board accepts up to four, and those four must be
installed into memory chip sockets U41, U42, U43, and U44. The jumper
configurations and other considerations required for each type of memory
device are outlined in later sections of this chapter.
The iSBC 80/16 board is designed to accommodate both 24- and 28-pin JEDEC-compatib1e
memory components in the same socket. The
24-pin component must bE~ installed as shown
in Figure 2-2; pin 1 of the component
should line up with pin 3 of the socket.
The JEDEC memory sockets may be configured to provide three independent
sections of memory address space. Figure 2-3 shows the three pairs of
JEDEC memory sockets and the actual orientation of the sockets on the
iSBC 80/16 board.
•
28-PIN
POSITION
24-PIN
POSITION
Pin 1 for
28-pln devices
Pin 1 for
24-pln devices
•
1003
Figure 2-2.
Memory Device Installation
2-9
PREPARATION FOR USE
U41/U42
Jumper Matrix
• •••••••
•••
•••••
•
..
U43/U44
Jumper Matrix
U45/U46
Jumper Matrix
•••••••••
•••••••••
•••••••••
••••••
•.:.::--------:~
~------:....
~,--------~¥~------~
PAIR
Figure 2-3.
¥
PAIR
•
~,--------~¥~------~
PAIR
1004
JEDEC Memory Socket Pairs
The memory address space at each pair of sockets can vary depending on the
operation of the decode PROM (U33) on the board. Jumper connections allow
configuration of the address and control signals to the JEDEC memory
sockets. The following paragraphs describe the jumper configurations
required for each component. You must remember to configure the decode
PROM jumpers to select the proper operating mode for the decode PROM on
the iSBC 80/16 board. A detailed description of the operating modes
available and the jumper configurations required to select each mode of
operation of the decode PROM is provided in paragraph 2-13.
As shipped from the factory, the iSBC 80/16 board is configured to accept
four user-provided 2716 EPROM devices at sockets U41, U42, U43, and U44
and to accept two 2k by 8 bit Static RAM devices in sockets U45 and U46
(Note: the 2k by 8 bit Static RAM at U45 is provided with the board).
This configuration places the local EPROM at memory addresses 0000 through
lFFFH and the local RAM at memory addresses 3000H through 3FFFH; 3800H
through 3FFFH are installed when shipped.
If a different type of configuration is required, the decode PROM provides
you with seven readily available options that you can select by
reconfiguring the jumpers as descri~ed in paragraph 2-13. Reference the
special instructions for 2708 and E PROM devices if either type of
memory device is installed into the JEDEC memory sockets. Figure 2-4
shows some examples of memory configurations that are available without
reprogramming the decode PROM.
After selecting the memory device type to best suit your application,
carefully insert each device into its socket.
2-10
•
•
•
•
PREPARATION FOR USE
•
Never insert MOS devices into a board
when power is applied. Doing so could
damage the devices.
Chip
Sockets
Chip
Type
U41
2716
•
Address
Range
0 000
0 000
0 FFF
0 7FF
0 800
2718
U42
2732
2764
1 FFF
2000
1 000
2732
2716
U44
2716
1 7FF
1 800
1 FFF
2732
U45
2kx8
SRAM
U46
2kx8
SRAM
2kx8
SRAM
3 FFF
3 000
•
F800
4 FFF
4 000
2kx8
SRAM
4 7FF
of
27128 EFFF
W/0
F800
2764
W/L-:;
FFFF
F000
2kx8
SRAM
F7FF
7 FFF
7 FFF
8 000
8kx8
SRAM
27128
5 FFF
6 000
9 FFF
8 FFF
A000
Empty
Socket
8kx8
SRAM
B FFF
E000
E000
8kx8
SRAM
E000
8kx8
SRAM
FFFF
FFFF
FFFF
C 000
C 000
C 000
8kx8
SRAM
F7FF
27128
7 FFF
8 000
4 000
8kx6
SRAM
2kx8
SRAM
FFFF
F000
27128
3 FFF
4 000
8kx8
SRAM
8kx8
SRAM
0 FFF
0 FFF
0 FFF
DOPT=lll
DOPT=110
DOPT=lOl
DOPT=lOO
DOPT=Oll
DOPT=OlO
DOPT=OOl
1
2
3
~:
5
6
7
1005
Notes:
•
The number listed under each configuration example is the
input configuration required at the decode PROM to obtain that
memory map. Refer to Table 2-5 for more information.
In option number 4, the upper 3/4 of the address space in the
fourth 27128 (socket U44) is overlayed by Static RAM and not
used.
Figure 2-4.
2-10.
•
~///.;::
~
B FFF
C 000
3 FFF
4 000
3 FFF
2764
27128
5 FFF
6 000
27128
27128
2764
0 000
0 000
i
1 FFF
2000
7 FFF
8 000
2kx8
SRAM
2kx8
SRAM
3 7FF
27128
7 FFF
3 FFF
4 800
3 800
2764
0 000
2764
3 FFF
4 000
3 FFF
4000
2764
2 FFF
3 000
0 000
27128
1 FFF
2 000
1 000
0 FFF
U43
0 000
2764
2732
JEDEC Memory Socket Configuration Examples
Line Driver Installation
In the as-shipped configuration, the iSBC 80/16 board contains RS232C
driver and receiver devices for the serial RS232C interface on the J3
connector and contains an 8287 Octal Bus Transceiver performing part of
the parallel interface to the Jl connector. You must provide line driver
and/or receiver devices for the remainder of the Jl connector interface
(chip sockets U3, U4, US, and U6) and for all of the J2 connector
interface (chip sockets U7, U8, U9, U10, Ull, and U12).
2-11
PREPARATION FOR USE
The parallel I/O interface at connector J1 includes four 14-pin chip
sockets (U3 through U6) for installation of user provided line drivers and
tel'1llinators to configure the I/O port signals on Fort B and Fort C of the
8255A PPI device. Table 2-1 lists some of the common types of line drivers
and tel'1llinators that may be installed. The iSBC 80/16 board includes an
8287 Octal Bus Transceiver device (U2) that interfaces the Fort A I/O
signals to/from the 825~ PPI.
The parallel I/O interface at connector J2 includes six 14-pin chip sockets
(U7 through U12) for installation of user provided line drivers and
tel'1llinators to configure the I/O port signals on Fort A, Fort B, and Fort C
(respectively) of the 825~ PPI device. Dable 2-1 lists some of the common
types of line drivers and tel'1llinators that may be installed. Table 2-3
lists the chip sockets and shows their correlation to the parallel port
interface signals.
Table 2-3.
825~
PPI Device
Parallel Fort Receiver/Driver Socket Assignment
Fort
Number
Driver/Receiver
Socket
Operating Modes
Available
U19, Connector J1
Fort A
U2 (8287)
Mode
Mode
Mode
Mode
Mode
0
0
1
1
2
Input
Output (Latched)
Input (Strobed)
Output (Latched)
Bidirectional
U19, Connector J1
Fort B
US, U6
Mode
Mode
It)de
Mode
0
0
1
1
Input
Output (Latched)
Input (Strobed)
Output (Latched)
U19, Connector J1
Port C2
U3, U4
Mode 0 8-bit Input
Mode 0 8-bit Output (latched)
U20, Connector J2
Fort A
U7, U8
Mode 0 8-bit Input
Mode 0 8-bit Output (Latched)
U20, Connector J2
Fort B
U11, U12
Mode 0 8-bit Input
Mode 0 8-bit Output (Latched)
U20, Connector J2
Fort C
U9, U10
Mode
Mode
Mode
Mode
0
0
0
0
8-bit
8-bit
4-bit
4-bit
•
•
•
•
Input
Output
In, 4-bit Out
Out, 4-bit In
Notes: Refer to Table 2-1 for a list of chip types that may be installed
into the Driver/Tel'1llinator sockets.
The control signals for modes 1 and 2 depend on ports A and B.
2-12
•
•
PREPARATION FOR USE
•
2-11.
JUMPER CONFIGURATIONS
The iSBC 80/16 board provides a variety of jumper-selectable options to
allow user-configuration of the board for a particular application.
Iab1e 2-4 lists all jumpers on the iSBC 80/16 board in numerical order
and provides a short description of each. Figure 2-5 shows the appro~
imate location of each of the jumper posts. Some of the jumper functions
and configuration requirements are detailed in subsequent paragraphs •
•
•
:
E63_~ • • • _E89
\ E59
E55
E68-:--- ·\1:94
E75E~1 E88
El08
......
...
.... ......
...
•
.....
~ ••
E99
'0"'.0"'0"'00'""0-;:-;00""0"'"00""'0"'0"'00'""0-;:";00'"
E98°ooooooooooooooooo
El03
.~105 000000000000000000
E104
I
000000000000000000
~::::::::::::::::::]
..-
E166E167
E 168
.
E19l
--
E ll0
E12~ ••••••• ~136 E14t •••••• 1156
Elll1
E137
••• ••••• ~E126
--E127
••••••••• _E145
•••••••
·-E146 ---E208
E163
[lDJ~1U!DD
E174
E18'-1189
E62
E111 •••••• 1118
•
---
E184 E186
E190
I
··
E60
...................
E69 \ E,3 E50
~97
~5~56
....--
'::./
E78
E96
E95"
•
E46
E45
•
E177
•
E180
•
E183
--
E192
E193
1006
•
Figure 2-5.
Jumper IDeation Diagram
2-13
PREPARATION FOR USE
Table 2-4.
Jumper
Number
El-&2*
E3-E8*
E4-E9*
E5-ElO*
E6-Ell*
E7-E12*
E13-E14
E15
E16-&21*
E17-&22*
E18-E23*
E19-&24*
E20-&25*
E26-E27*
E28
E29
E30
E32
E34
Jumper Listing By Numerical Order
~scription
Provides a nominal 10 millisecond timeout before generating
a READY input to the 8080A-1 CPU.
Connects Port C bit 7 (Port address E6) from the 8255A PPI
to parallel interface socket U3 and to Connector J1, pin 31.
Connects Port C bit 5 (Port address E6) from the 8255A PPI
to parallel interface socket U3 and to Connector J1, pin 27.
Connects Port C bit 1 (Port address E6) from the 8255A PPI
to parallel interface socket U3 and to Connector J1, pin 29.
Connects Port C bit 0 (Port address E6) from the 8255A PPI
to parallel interface socket U3 and to Connector J1, pin 25.
Provides a constant LOW signal level (LOWLVL2), disabling
generation of the 8255A interrupt request signal (INT55) to
the interrupt generation logic.
Connects the Power Fail Sense Reset signal (PFSR/) to the P2
connector.
Provides access to the selectable length (either 1 mS or 10
mS duration) interrupt request output signal (MST) from U16.
Connects Port C bit 4 (Port address E6) from the 8255A PPI
to parallel interface socket u4 and to Connector J1, pin 21.
Connects Port C bit 6 (Port address E6) from the 8255A PPI
to parallel interface socket U4 and to Connector J1, pin 23.
Connects Port C bit 2 (Port address E6) from the 8255A PPI
to parallel interface socket U4 and to Connector Jl, pin 19.
Connects Port C bit 3 (Port address E6) from the 8255A PPI
to parallel interface socket U4 and to Connector J1, pin 17.
Provides a constant LOW signal level (LOWLVL2), disabling
generation of the 8255A interrupt request signal (INT55) to
the interrupt generation logic.
Connects the "running" signal to the driver input for LED
OSl; a high input to E27 lights the LED indicator.
Access for Port C bit 1 (Port address EA) between the 8255A
PPI and parallel interface socket U10 (to Connector J2, pin
23) •
Configures one of the three mode select signals (00PT2) for
the proper decode PROM operation; may be connected to +5 (no
jumper installed), ground (E207), or parallel port control.
Access for Port C bit 0 (Port address EA) between the 8255A
PPI and parallel interface socket U10 (to Connector J2, pin
25) •
Access for Port C bit 2 (Port address EA) between the 8255A
PPI and parallel interface socket U10 (to Connector J2, pin
21) •
Access for Port C bit 3 (Port address EA) between the 8255A
PPI and parallel interface socket U10 (to Connector J2, pin
19).
2-14
•
•
•
•
•
•
PREPARATION FOR USE
•
Table 2-4.
Jumper
Number
E3l-E37
E33-E39
•
E35-E36*
E38
E40
E41-E42
E43-E42*
E44-E45
•
•
•
E46-E51
Jumper Listing By Numerical Order (continued)
Description
Configures one of the three mode select signals (DOPTO) for
the proper decode PROM operation; connected to +5 volts (no
jumper installed), ground (when installed), or parallel port
control.
Configures one of the three mode select signals (OOPTl) for
the proper decode PROM operation; connected to +5 volts (no
jumper installed), ground (when installed), or parallel port
control.
Provides a LOW signal level to the driver input for LED OS2
disabling its use; a high input to E36 lights the LED.
Controls the enabling/disabling of the shadow EPROM feature;
a low signal level disables the normally active memory chip
selects.
Clears the timeout interrupt latch when LOW; may be
controlled via parallel port.
Places +5 volts on Connector J2, pin 1.
Places ground on Connector J2, pin 1.
Enables the Receive Clock signal (RXC) to be sent off-board
(via Connector J3, pin 8) when installed •
Connects the Chassis Ground signal (CHASSIS GND on Connector
J3, pin 1) and the iSBC 80/16 board ground, when installed.
E47 to E50,
and E52 to
E59
Select the required output frequency from the baud rate
generator logic; refer to Table 2-14 for more detail.
E6o-E61*
Selects a divide by 15 count-value for the baud rate
generator.
E62-E61
Selects a divide by 10 count-value.
E63-E64
Allows the RTS signal to provide a CTS signal to the 825lA
PCI device •
E63-E69*
Allows the Request-To-Send (RTS/) signal to be sent
off-board; connects Request-To-Send from the 825lA to the
Clear-to-Send (CTS) signal line at Connector J3, pin 9.
E64-E65*
Allows the Clear-to-Send (CTS/) signal to drive off-board;
connects Clear-to-Send (CTS/) from the 825lA to the
Request-To-Send (RTS) signal line at Connector J3, pin 7.
E66-E67
Allows the Transmit Clock signal (TXC/) to originate from
off-board; connects the Transmit Clock input to the 825lA
PCl with the TXC/OTR signal on Connector J3, pin 14 when
used as a Transmit Clock signal.
E67-E68*
Allows the Data Set Ready signal (DSR/) to originate from
off-board; connects the Data Set Ready input to the 825LA
PCI with the TXC/DTR signal line on Connector J3, pin 14,
when used as a Data Terminal Ready signal.
E69-E70
Activates the CTS/ signal on the Jl connector.
E71-E78*
Allows the Receive Clock signal (RXC/) to originate from the
on-board baud rate generator output.
2-15
PREPARATION FOR USE
Table 2-4.
Jumper
Number
E71-E72
E73-E74*
E75-£74
E76-E77*
E79-E80*
E81-E80
E82-E84
E83-E84
E85-E84*
E86-E87*
E88-E87
E89-E90
E91-E90*
E92-E93*
E94-E93
E95
E96
E97-£98
Jumper Listing By Numerical Order (continued)
~scription
Allows the Receive Clock signal (RXC/) to originate from
off-board.
Disables generation of an interrupt request as a result of
the SBXBlNTO signal from the iSBX Bus Connector J4, pin 14.
Allows generation of an interrupt request as a result of the
SBXBlNTO signal from the iSBX Bus Connector J4, pin 14.
Allows the Transmit Clock signal (TXC/) to originate from
on-board; connects the Transmit Clock output from the baud
rate generator to the 8251A PCl.
Disables generation of an interrupt request signal as a
result of the SBXBlNT1 signal from the iSBX Bus Connector
J4, pin 12.
Allows generation of an interrupt request signal as a result
of the SBXBlNT1 signal from the iSBX Bus Connector J4, pin
12.
Enables the Transmit Buffer Empty signal (TXE) to generate
the 825lA PCl interrupt signal (lNT51/) to the interrupt
logic and to the 8080A-1 CPU.
Enables the Transmitter Ready signal (TXRDY) to generate the
8251A PCl interrupt signal (INT5l/) to the interrupt logic
and to the 8080A-1 CPu.
Disables generation of the 8251A PCl interrupt signal
(INT51/) to the interrupt logic and to the 8080A-l CPU.
Disables generation of an interrupt request signal as a
result of the SBXAlNT1 signal from the iSBX Bus Connector
J5, pin 12.
Allows generation of an interrupt request signal as a result
of the SBXAlNT1 signal from the iSBX Bus Connector J5, pin
12.
Enables the Receiver Ready signal (RXRDY) to generate the
825lA PCl interrupt signal (INT51/) to the interrupt logic
and to the 8080/\.-1 CPU.
Disables generation of the 8251A PCl interrupt signal
(INT5l/) to the interrupt logic and to the 8080A-1 CPU.
Disables generation of an interrupt request signal as a
result of the SBXAlNTO signal from the iSBX Bus Connector
J 5, pin 14.
Allows generation of an interrupt request signal as a result
of the SBXAlNTO signal from the iSBX Bus Connector J5, pin
14.
Accesses the SBXBOPT1 signal on pin 28 of the iSBX Bus
Connector J 4.
Accesses the SBXBOPTO signal on pin 30 of the iSBX Bus
Connector J 4.
Forces insertion of one Wait-state into all bus cycles.
2-16
•
•
•
•
•
PREPARATION FOR USE
•
Table 2-4.
Jumper
a"mber
Jumper Listing By Numerical Order (continued)
Il;!scription
E99-E100*
•
•
•
Provides a common reset signal (INIT/) for the iSBC 80/16
board and the Multibus interface (via Connector P1, pin 14)
when the jumper is installed.
E101-E102* Configures the 8287 Bus Transceiver on Bort A of the U19
8255 PPI as an output port.
E103-E102
Allows 8255A PPI Port C, bit 6 to control the direction of
the 8287 Bus Transceiver for Bort A of the 82551\ PPI; if bit
6 is LOW, Bort A is an output port, if Bort C bit 6 is HIGH,
Bort A is an input port.
E104
Accesses the SBXAOPT1 signal on pin 28 of the iSBX Bus
Connector J 5.
E105
Accesses the SBXAOPTO signal on pin 30 of the iSBX Bus
Connector J 5.
E108-E109
Enables generation of a 10 millisecond latched interrupt
signal (MST); must be enab1e:d by installing E15-E20.
E110-E109
Enables generation of a 1 millisecond latched interrupt
signal (MST); must be enabled by installing E15-E20.
E111 thru
E127
E128 thru
E146
E147-E148*
E149 thru
E163
Provides configuration options for placing various types of
memory devices into memory chip socket pair U41 and U42;
refer to paragraph 2-14 for more information.
Provides configuration options for placing various types of
memory devices into socket pair U43 and U44; refer to
paragraph 2-14 for more information.
Configures socket pair U43 and U44 on the board for use
without E2pROM devices; remove jumper if installing
E2PROM devices requiring the timing capacitors.
Provides configuration options for placing various types of
memory devices into socket pair U45 and U46; refer to
paragraph 2-14 for more infc>rmation.
E164-E165*
•
Configures sockets U45 and U46 on the board for use without
E2PROM devices; remove jumper if installing E2pROM
devices requiring the timing capacitors.
E166-E167* Enables an interrupt request signal from parallel I/O
Connector J1, pin 49 to the interrupt generation logic.
E169-E170
Provides a negative-true Bus Priority In (BPRN/) signal to
the HOLD input on the 808~-1 cpu.
E171-E170* Provides a positive-true Bus Priority In (BPRN) signal to
the HOLD input on the 808~-1 cpu.
2-17
PREPARATION FOR USE
Table 2-4.
Jumper
Number
Jumper Listing By Numerical Order (continued)
Description
E172, E173,
E174
Allows for installation of 2708 EPROM devices into memory
socket U4l; refer to paragraph 2-15 for more information.
E175, E176,
E177
Allows for installation of 2708 EPROM devices into memory
socket U42; refer to paragraph 2-15 for more information.
E178, E179,
E180
Allows for installation of 2708 EPROM devices into memory
socket U43; refer to paragraph 2-15 for more information.
E181, &182,
&183
Provides control of the EPROM shadowing option; refer to
paragraph 2-19 for more information.
E19<
1~
-
CJ
gl T
>
0
lI::
CJ
~
III
~
"-
Q
w
e
III
III
II:
Q
Q
e
Figure 2-9.
e
Ie
Q
1
•
C)
Z
"-
~
Z
. . . . ::::iC/)
::IE
::IE
0
CJ
lIIi:~1-
CJ::IE!i
ceo
><11I~
"lI::
CJ
e
><
Multibus® Memory and I/O Timing (READ)
2-42
•
PREPARATION FOR USE
•
•
I/)
::l
III
I/)
....I
I/)
0
a:
III
9
.....
z
0
•
0
co
~
(:)
IX)
T
•
1
>
III
9
1
a:
a:W
w .....
..... cc
J:I/)
O::l!
•
Figure 2-10.
"-
z
>
a:
I/)
II.
III
::l
III
Multibus® Control Exchange Timing
2-43
PREPARATION FOR USE
2-29.
AUXILIARY (P2) INTERFACE INFORMATION
A mating connector can be installed in the iSBC 604/614 Modular Cardcage
to accommodate auxiliary connector P2 (refer to Figure 2-1). Table 2-2
lists some 60-pin connectors that are compatible; both solder and
wirewrap connector types are listed. Table 2-25 lists the pin
assignments for the P2 connector.
•
The P2 connector contains 4 output signals and 4 input signals. The
function of each signal on the P2 interface is outlined in the following
paragraphs.
a.
"ALE". The address latch enable (ALE) signal is an internally
generated output signal can be used to monitor the status of the
system.
b.
HALT/. The halt signal is an internally generated output signal
that is made available to the interface for status monitoring
purposes.
c.
AUX RESET/. The auxiliary RESET signal is an externally
generated RESET signal input to the iSBC 80/16 board.
d.
PFIN/. The power fail interrupt signal (PFIN/) is an externally
generated input signal that can be used to interrupt the CPU if a
power fail occurs.
e.
PFSN/. The power fail sense signal (PFSN/) is implemented as a
general purpose input signal.
f.
PFSR/. The power fail sense reset signal (PFSR/) is implemented
as a general purpose output signal.
g.
WAIT/. The wait signal is an internally generated term that is
made available to the interface for status monitoring purposes.
h.
VPP. The EEPROM voltage required to re-program an electrically
eraseable ROM is generated externally input signal to the iSBC
80/16 board, and must conform to the requirements of the chips,
as described in the data sheet for each.
•
•
•
•
2-44
PREPARATION FOR USE
•
•
Table 2-25.
Pin
Mnemonic
1
2
6
13
17
19
21
22
28
30
32
38
2.
3.
2-30.
•
Description
GND
GND
vpp
PFSR/
PFSN/
PFIN/
GND
GND
HALT/
WAIT/
ALE
AUX RESET/
Notes: 1.
•
Auxiliary Connector P2 Pin Assignments
Ground
Ground
E2pROM VPP
Power Fail Sense Reset
Power Fail Sense
Power Fail Interrupt
Ground
Ground
CPU Halt
CPU Wait
Address Latch Enable
Reset Switch
All even-numbered pins (2,4,6, etc., 26) for this connector
are on the component side of the board. Pin 2 is the
left-most pin when viewed from the component side of the
board with the extractors at the top.
Cable connector numbering convention may not agree with board
connector numbering convention.
All unlisted pin numbers are reserved and not used by the
iSBC 80/16 board.
PARALLEL I/O INTERFACE INFORMATION
i
The parallel I/O interface at the J1 connector on the iSBC 80/16 board is
controlled by the 8255A PPI device (U35). Table 2-26 provides a list of
the parallel I/O interface pin assignments for connector Jl. Table 2-27
provides a list of the parallel I/O interface pin assignments for
connector J2. Table 2-28 provides a listing of the dc characteristics
for the signals found on the J1 connector. The pin assignments on
conector Jl can be readily modified via the jumpers included on the
iSBC 80/16 board; refer to Table 2-4 for more information.
•
2-45
PREPARATION FOR USE
Table 2-26.
Pin
Number
Driver/
Receiver
Parallel I/O Connector J1 Pin Assignments
Function
1
3
5
7
9
11
13
15
U6
U6
U6
U6
U5
U5
U5
U5
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
B
B
B
B
B
B
B
B
. .;.
-
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
3
2
1
0
4
5
17
19
21
23
25
27
29
31
U4
U4
U4
U4
U3
U3
U3
U3
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
C
C
C
C
C
C
C
C
-
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
3
2
4
33
35
37
39
41
43
45
47
49
U2
U2
U2
U2
U2
U2
U2
U2
none
6
7
6
0
5
1
7
PORT A - BIT 7
PORT A - BIT 6
PORT A - BIT 5
PORT A - BIT 4
PORT A - BIT 1
PORT A - BIT 0
PORT A - BIT 2
PORT A - BIT 3
EXT INTR 0/ or +5V
i f required
Port
Address
Pin
Number
E5
E5
E5
E5
E5
E5
E5
E5
2
4
6
8
10
12
14
16
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
E6
E6
E6
E6
E6
E6
E6
E6
18
20
22
24
26
28
30
32
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
E4
E4
E4
E4
E4
E4
E4
E4
34
36
38
40
42
44
46
48
50
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Function
Notes: All even-numbered pins on this connector are located on the
component side of the board.
Cable and connector pin numbering conventions may not agree with
the pin numbering conventions used on the board edge connectors.
•
•
•
•
•
2-46
PREPARATION FOR USE
•
•
•
•
Table 2-27.
Pin
Number
Driver/
Receiver
Parallel I/O Connector J2 Pin Assignments
Pin
Number
Function
---
2
Ground
Port
Address
Function
1
--
Ground or +5V
3
5
7
9
11
13
15
17
U12
U12
U12
U12
Ull
Ull
Ull
Ull
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
B
B
B
B
B
B
B
B
-
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
3
0
1
2
4
5
6
7
E9
E9
E9
E9
E9
E9
E9
E9
4
6
8
10
1"
llf
16
18
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
19
21
23
25
27
29
31
33
UlO
U10
U10
U10
U9
U9
U9
U9
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
C
C
C
C
C
C
C
C
-
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
3
2
1
0
4
5
6
7
EA
EA
EA
EA
EA
EA
EA
EA
20
2"
24
26
28
30
32
34
..
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
35
37
39
41
43
45
47
49
U8
U8
U8
U8
U7
U7
U7
U7
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
AAAAAA AA -
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
7
6
5
4
0
1
2
3
E8
E8
E8
E8
E8
E8
E8
E8
36
38
40
42
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
~.
41~
46
48
50
Notes: All even-numbered pins on this connector are located on the
component side of the board.
Cable and connector pin numbering conventions may not agree with
the pin numbering conventions used on the board c~dge connectors •
•
2-47
PREPARATION FOR USE
Table 2-28.
Signals
Bidirectional
Drivers
8255A.
Driver/
Receiver
EXT INTRO/
Symbol
•
Barallel I/O Connector J1 DC Characteristics
Parameter
Description
Test
Conditions
Min.
Vol
Voh
Vil
Vih
lil
lih
*Cl
o;j
•
•
•
•
DI
'""
~
ID
Ii
t\)
B9
VI
I
t-'
•
"
'en""
t;I:l
n
en
®
t"l
00
~
H
.g
t-'
C'\
0
~
o
~
Ii
~
~~
11
Ii
"en
z
S
('J
~~I~ lPR~~:~cc£
~
"'""
-003
0
NOTES; UNL.ESS
::I
A5SEMBL'(' PART
;HI~
3.
o
~
m
t.
2.
~cJM3ER
15
1440G8 .. 'i(X.
[2J
OOCUN'ENT, PARTS LIST AND WIRE
IA
~
WORK.rY1A:>.j~ ..!!P
PER
~
99-0007-001.
IYt""R ..... ASSEM5LY DASH N'_'fY16ER AND RE.vISION L.E.VEl.
YV,TH CCNTR ...... ST1NG PER:'(IANE"-'~D;...'CT ;:'OuE .::..5 ;:;'t..)ul~f:..':> wITH
PERMANENT CONTRASTING COLO>:!, .!2 H'G~,
t-JON-CONDuCTIVE, APPROXIMATELY WHERE SHOWN.
"'iI~~,
5~OwN.
SOCKE:T RE""E.R,~_""CE. Dt.SGNA,TOR5 ARE. TI"iE. cr--"""'~QNENT
RE::fE.i=l.EN:t:: .. '<-SI';r-.ATC'<':;' PRE.FlxE..D ...... Tt; x·,
15
6Cl/IG
,...\ARK ALPHA
CONTR,o..5TING
r-..DN-CONOvCnvE
\JVh;:~E.
6,
~
J
~PECIF:!:D
UST ARE. T ....... "KINc.;. DOC.'JMENT:',
IX
OQ
Ii
CTHERvVI5E
~
I
VI
t:rl
H
.
VI
n
t;I:l
~
_ _ .twu..
00 '-Of tc.Lt
-... --~-----
TE.RMINAL REFE."'~~C.;' ;:;~S:~N"""ION5,
-~i:--
-----
~~-
INST .....LL ITE><1 ~ ON SCI...Ce:R ~dDE. AT _/34-, So THAT
Ir_ ? .... DS ,...1''3.. F'R:;:;' OF L;...BE.L. .t..Nt::> f-<..DI"IE.5I'vE.
6
~
•• ,~.
2:~~~
I-'R;NiE.:::; B()AR.r.:.: .A..55EMeL'T'
~SBC.
eO/16,eO;16D
SERVICE INFORMATION
•
•
•
•
•
5-6
•
•
•
•
,...
•
6
~
OQ
I
B
~
fCC .:1;)- 2999
EC040-3481
C.
1'1
(1)
o
Vl
I
N
•
r--,...,----- ... SOV
I
;
p",.~
+Sv
AU""
,---
Pl.-I ( (".IoJD
P2.-2. ( (;>ND
en
td
("')
®
PZ-z! (
GND
PZ-Z2.(
GND
C
I
0
III
1'1
n
:::r
PI·~~
ul5
14l~33
~
+~
UI4UI3
u34
PI-&'
o
1".,;1,54 1"
n
PI-I
TI~~,lor.
(&'-.\;)
Pl-t- (
~
7
4i..)4S-S'S
.1
III
I
20
7
14
7
7
2
8
8224
~
H
I.
I:;;l
C")
t:rJ
28
't:o
9
14-
28
~
~~ r---
_
~
20
_+_ e _1--'6
.
1
9(.02
~
o
~-I
1420
16
U3£38
:~ -~
H
20
I ~~~~~
I--~~
t-:I
H
C------_
I--
_
---+--t-------+--_____+___+_
I
~~ t= r-=-r--
PI-bS _
1'1
III
8
10
B
114-0
PI-II.
FI-75
PI-1(,o
OQ
en
t:rJ
5
"
16
~F911 20
~_
PI-II
I U2.B-6
7
e
75188
75189A
8oBJA-t
097
~~2.5~
t "
~
I.
'~~;~1~AM~
U39
1-1, II, 13 18, "',"'--Z',3<) 36-43
1
'4-
12
7451£-";
74LS240
7"4-:LS3"§O
~ ~~~-64-
PI-(.::>
Pl-&!./
( • -~~
'.
~
;:c~~o -~ ~
7
74L520
74532
74L532
U27
31 32
UI7
U~54
,:l.
en
,4
PI_l<1/- 12.,.V
PI-IO -" -6V
L...QG,,\(.. e.Le..MENT
OUTPUT PIN!>
~
7
7406
U2 % 38
U47
p,"""
+S\lJo.U~
' ..
74LS04-
U2'
utJu!:>ED
-12.v
,.
7
7404-
4'
~ u~~ 28
td
'-I
74500
74~S02
UI8
u30
......
TYPE::
U3,
-r .... 'BLE
~~ ~ ~~~:~ :I~~
DE.VICe
U2
37
... 12......
PI-6 ./ +-11-V
.g
I
CEoVICE
tl.E.FE:.IZ.E."-.:Ce.
DE.!>I&~,b.."IOI>J
PI-7~
00
Vl
o
P2.-4-~
,...
C1\
AU'"
PI-BlD/ G.>JD
~=~~-~--~==t-~. ---------
a
,....
en
-
:::r
(1)
(1)
NOTES;
r-t
......
0
H'I
......
0
-....;
UNL..r:~!>
OTrI.STANCE:. VA.LLlE:!;> A. ...... E; IN O~M5
2- c..A-PAC,T.A.NC£ v,rro..L...UE:~ ,e..il.e:.
+601~, ·201., 50Vcx.
A
o
f4l
r5l
-
G:J
,j,J
±
5,.,
1/4 WA.TT.
MICIZ..OFA .....A-DS
TD GROUND.
AN~
\J~)7
TO
FOR 50/'bD ON..'t.
P40
RPS
~-~ ARE CU'5TOMER 5L'PP~:f:D
~~~
'NSTALL~::; .
THRU U-C"->
r::cos,
T"'"
E205
8EFA'JlT JUtl"PER
C8,C::::-35 A\J.)
f:\ [JE5IS~A~T~O'~~~~~~~~;;~~~~~~~~~=====;;;;;;;==~
-:;:::'::';2F:'~"
~.,.,.,."
bREF
ALL EvEN PINS ,---"N JI AND J2 .A.RE. CONNE.CTED
,c.=--"), '--'RW c..:oz
"';ur-',PEP. E2..C4:~J,.:,,:) .
---s
,-::a-.o,M3.9, JUMPE.P,
E2::(--:>, ":>~L1" 'J'::>T':"l. __ ~~1:'
•
CAUTION:
YI
DlME~'O>OOTS~~ <)~~"'N:;
IU_4~1~£ ~ ~U"iS
c~.
9>".'-
~~"
--
~~::'. '~,:"'iL,
~;: ~:~
T"L[
I'.... JI
s.:.1-o.~\';"TtC::: A(:,.;2.t>..M
~c:..::l.C 80/!0,80/;6D
'"
These schematic diagrams may have been revised. See "Service
Information" chapter for details.
c. ".,
' . " co. ~ ••, . ,
•••••
o
lZ
SERVICE INFORMATION
•
•
•
•
•
5-8
•
•
•
•
•
6
....Ioz:l
()Q
LI:.~E.T
s:
~
o
VI
.
I
.....,
10
I~TIL
,I."
...sv
....
en
o:o..E:::: 5
110
Aai,
A0-:AF ,.., 3
"
'AB¢
ABiZ\-A62 0.9
1
4L532
~BASI/
~:
"OWl
~
-
ABa'-~1
.AB~
~i8
~4("S-;-Z
7404
PI-14( INIT!
U49
WAIT
• {).:os
I -- 7~LS04-
I -'
0-
=
"1404
R40
I~~
's ¢
e.:z.2..4
+-_+-~_~2' ~
I, .:!I't'tJ"-
~
,~
10K
WP-/
::>~I'.I
~"
PI
h
~ I
::
8-
10K
liB
7
'?
01
8
oc..
07
D1.
DBI
CU
DB2
U40 DB
7
D$
D(o
12.
~ ;';
5
~
8
D4
-.i2L-:n
~ MI.t)6.
z.,
2
I
DS4 Ie ;~:
DBSw
De.<..
9"22""wr--....9J,ool
iI3i--...·
,_~
DB6 7
Del
,4L504
DB7-
74~4
~ - -RP5
I
=
Nv-tSY
::t
~
~
2.2 K
PROCESSOR
SECTION
a
,.....
R35
t-5v--
20K
::.,
"'740c.,
LON LYl I
~32
or
CD
CD
pu
1\
U37
'l/7404f-
4
"
ALE
.,- Pz.-!.l.
S""~c..'o 4,10
D""I..D ...
0
PI-ILD.At/
A
0:z.(TTI.-) n
t-h
I-'
0
'-"
CAUTION:
z
4.'"
1,...)37
0
~
o
~."
+-5101'
~4 I~i.
rt
~
Ot>¢-D&7
~,,>4
en
::r
~
o
Ut8
.!;.v
1'1
III
tZJ
H
~
,OK
III
H
C"l
3, S
,i4L..~':z.
:3e!
~:;
I
()Q
tZJ
~
!>,7,8.'"
0 Je,S
.....
D~0
DI
~o_
~ iD
D
7
.3
'"'L
MWIZ../
l.o~cl
~DI
"l41-S,3z...
n'oC(I/'y LJC4 4 ~ .
C>:.. TL
en
+
,-----------I~~~JL-------.lt;.eO""""'!L"-/__o.), 140,7, 6,"
INTE!&
0
0 )0
D¢,Olp3 94-,D6 0
+5<1
Q.
I
WAtT
P2.-$& ( ...... 1.,))< IU..~~TI
0
III
1'1
.....,
.
AA-AF 04-
A~
00
0
1.0
A.
USB
~
U31
PI-IS
D
~
,
~ lO~
f,PI'l.N
=
I
&"
2. .."'"
CD
V1
<." i,
0
~-tS"
1'1
These schematic diagrams may have been revised. See "Service
Information" chapter for details.
....
3
'A
SERVICE INFORMATION
•
•
•
•
•
5-10
•
•
•
•
•
....
I2j
~
~
(D
V1
2-
AV> AF
D
.
2~18
Art
AI
A2
.
I
N
,
b:I
T
7
"
-
fL37
I
~
~
til
()
r.oWRI
2
2.
(.
18
o
~
4O-=N/
()
20 DS,D:;>.ol
"
9
AD,","F'/
U53
-
PI- SZ-
.;.
PI-
"1-4,}
~ PI-4("
~ P'-43
Cli2..E.1
> PI-44
lowe! -------7
-
MvvTC.1
102.<='/
-
MI2.Oc.1
I
so
> PI-41
> PI-4e
> PI-4S
~
7
60":>1
51
-"
ADI2.e,;
A
•
~O'!2D:'
MRD/
1"1'
9
A.DI2..~
A 012.. A[
"
S~
S4
~I-
AD~'"
I"
~
'2
17
P,-
> ?I+
)
~"
L~
~~6~
IOR.D/
"
....
.
10
~~
5
Mv-...R/
2
~
(D
10<-
uso
0
V1
AB
/>',C
AD
,AE
AF
t
b:I
~
~
2
AD~"l1
9
~
~<1
0'\
III
,
A. ...y~.51
AD~I
p~
I
'5V
A:; 12..4
7
A8
~
3
~
13
@
00
0
AD~
17
15
10"-
DHLDA
12
'6
12.36
("')
_54
AC
A
....til
AD~'L __ ~
AD"z.1
; "I-S<;;'
,14-
8
A3
AO~~_----,> PI- SI
'6
6
PI-2.:~.
....
III
t:;j
o. ,
~
" DB;;
) PI-ZI
> PI-I~
~.DB2
p83
~
()Q
~
DB
EI
.D86
DS7
III
31~
l~
DAT¢!
~p-"
~?'74~:~~;
..;.":5
,
B2.87
:!
------7
PI-7'
DAl-4~ ~:~:~
_
DATS!
8
til
Ul8
~
2
U50~
DHLDA/
-~AO'"
5 r>6
14[,)'3
o Mel-K
6 0
CO~"-/)
B\,.I!:oY!
E201
'202
:)D
) Pt-l1
PI_>I
1"1'
W
0
I-h
MULTI BUS
INTERFACE:
_ _ _ _---'E:':Z:::.~.~IS9
~PI-I~
,41...";;.04
~
0
'-'
f
CAUTION:
Z
">:j
o
~
.......
(D
(D
tr.1
H
t-3
~
J2fLl
~
H
(")
) ;;>,-2.0
~ -.J
-~~'6,~
~ EISS
CJ)
t:
Ali
COPT¢
a
OFTI
8
DOPT2
r'-~4===~j====~~~=====t;;;======;nE±f
P4
PROM
0 S
0 5
· ... 5/......n
5
3(cz,"S,I>.. I
:aIM
Y7to-=--------2W~-~¢/_~ .,
$f.X~ ;~'3
y,"
2 0 D¢,DI,03.D4,0t;
:rO;M
Gleo
DO>
en
&~xa., :S.aSl s '3
OS!!>,,!!>.<511 ::: ~
II
04
'(~
I~
S$c:.~
'1' 2,.
I~
'(I
14
ssc:.! 1/ .(] B
51 C;:..:-.J
~
's
txJ
~
wi --C 7
H
~'"
C"'l
txJ
i4!:>1=-f>
til
C')
DI
P"
ADV.ANCED
5TATUS
LATCHES
(I)
~
rt
D~
I
3 D
QG~
~4B Q 1+
'i4L~"'IS
t!jD Q['O~~
4 (i,U48.;
'"'"
C')
()Q
~ .• _~I
E,!)wc.:.
BweS-51
DECODE
Q.
::zIII
~5
z.I a s
e.wc!. >/ o 5
15A~ ~~'c' ----------------~==~======~=======j;~~)t~--~ii~
1:1:1
0
III
1"1
w
0,
--~5
Bwe
nAI.
.....
\.11
-
13
IG:> :
.g
.....I
Oz.
O:s 11-
I As U33
00
C'\
~
t
,'---"''---_J'''., A ,
....til
1:1:1
a! 10
O!c::.2.
A"'-A.1=
N
n
I
~+sv
eo 0 !:>>-IAoDOVoJ!
(I)
\.11
D~P~U~~~
''''-IT/
2. 0 sY ..... c'
"
D3
0:;
e.UF OIl'.
a
0"-1 aiO!.D
010
H
Z
.!.~
~
~
~8
9745010
"''!~'&.=-o "
;4 .... ~7SI
1"1
III
UE:IA DII2.
1:I~U+B~~
"
~I
S
z
rOi:.N/O~
""74~~2.
....... ' ';:.is
S
t il
P"
(I)
(I)
DECODE
rt
SECTI01-J
.t:-
A
O
H'I
.....
0
......
CAUTION:
These schematic diagrams may have been revised. See "Service
Information" chapter for details.
SERVICE INFORMATION
•
•
•
•
•
5-14
•
•
I'%j
()Q
+5V
c:
~
I
J
I
....
•
•
•
I
I
I
E"
..9
RD
IK
'tD"'
V1
.
I
N
....tr.l
=
A0-AE
Z.
P'l.-~
Vpp
dv
.
-
C"l
®
!>WCS 1/
J
~6
II
4
0
2..
C' DBaI- :JR7
~6 ~~
%uri
~~j
I
~~?~IN
...,-. ~, '6
....
::r'
A'
AA
tD
rt
H
~
V1
0
'-"
' ~;
>OS
4
=
f'
~
H
Z
US7,
i:B
ui .... 00VT '
PIN
~
~~
g8.3 "'z.:.;"?
t~~
%..IT ~ ....
COvT
D:N
:;'''1
2~
() ::.,.,t>
~XlT;
Dc"r: :),,.,
I
U60
I
Ubi
062.
I
U64:
U63
-
',G .c...10
; All
A"
",'
~E..I-A DIR
f-
LOCAL
MD.10RY
0rN CoLlT
~PAM
U59
~~
J
~6
1
u58
A7
AD
.
H
Z
o
~fK;-"
14_'''z...
-
P2.·z.0
Z
~
.....~
t::
~,:~~
(l)
t-'
tzl
f,wc.5-S
~
g
HI
n
uNiVERSAL
MEMORy
EXPAN510N
SITES
O.
o
en
0
H
Ej"
~?__~_j:z.2..
I
9
4 :
IU
SITE 5
t:I:j
· .we..
~~
~
IU
4
::g
~Vv'C.:::'¢
4 u e.WC.5z./
()Q
,.....
en
trJ
~
IU
t-'
U46
&
,
~
'-'PR.OI
'-' eDl
I',;' 1~~:;;7':;"'"
Z.
1
I
CAUTION:
l
T
I
1
These schematic diagrams may have been revised. See "Service
Information" chapter for details.
"I
I~'
SERVICE INFORMATION
•
•
•
•
•
5-16
•
•
•
•
•
6
I'>:j
~
()Q
~
2..
t;
O.s.c..
BAUD
I'D
VI
GE~lERATION
PATE.
M(..L.."
§j U23)7~:-L5-2-0--
D
lI • .,
D
I
~
~
~OW6VI..z.. Q 1,8,10
til
~
n
®
r---r=~-
00
2.
&
.g
+.v
LO'NL.Vl.1
c.. r
M'!oT
.....
Q\
en
=
~.J3-7
'T)c~~~TI2., ) ..J!o -14-
t;
D-ni Tl'C-
t%l
o
III
VI
.....I
......
c:lo
E7<
W
E78
::r
---Ef
i
.
~. ~~
~
13
7SIS9
~D
~
III
()Q
I"j
;
75169
'£.68
~
II
Ii!.
tow;z...1
4
~
.s,c..s.!
•
.. • .,
10
Ol"Ol2O/
, ::'
.......
~
UI3
5
l!o
II
~
:;
til
::r
ro~
I'D
I'D
I"t
rof,
~D'
..
Cf'5.
WI:'
~
C~
,~ C/o
10:3
"J 0
iii<.
E I
E.f6
!:iII;S::>,~
u!3
n
Q\
eZ.SIA
2,
..
b
Eb7
~
I"t
o
E.77
~2
I
~ WI4- 51~81
1'1(0
~
ffi
T$o
U21
b
"7
8
E'3
D
SERIAL
CAUTION:
.J5-S
~3
,
C~!2.
.1'_11
IJI4-l
:;
EE9
E.&+
tk
:> J~-8
£.xo _
-------r::::....4"!i188I
t.!o
9 E70
I
""ISles
~
..L
~
)
C.~J3z,
-0
c ...
E.+to
~,.s (.NO) ..J~-I
~ ~._,~
~
,,",0
o'-zGo
0)
~
Ie:
01
U2.2.
EEl!3
Tl'~
[/0
~
INTSI I
U 10
~
ES4- 'E.8S"
",,- f".5!..--+-f-+--~32
H'I
.....
o
'-"
0
,
:91
Z.
0
"-x'-
e.I+
,8
._ 1114
-+
H
(")
tz:I
H
E45
~31881
~;' : : : j'_ -ll ~9 E~90
I II
!O~-r07
I
S~~~:2-
~
eG8
.1
These schematic diagrams may have been revised. See "Service
Information" chapter for details.
Z
tzj
o
§
S
z
SERVICE INFORMATION
•
•
•
•
•
•
5-18
•
•
•
•
•
I'Zj
~
~1'1
I
(1)
e"""eve,
(p
<101
D
VI
.
p<."
I
N
b
PF.>JI
MST
~
til
~
l r~
1
,
.---
..
..
_~
ro,,-ol
2.
e./,i-A61
".........
,.
A8jZ
AB'
OJ
$~
" '0
PA2
2
<01
wtl-/
U1'
PAS '"
,.
.5"
II
<-,
RP'
312
I.
,"-
17 ~9
31 .11 - 4~
.II -41
IB
u2
Haze7
..J1
<'l
6
7
.2L
J! -45
.11-41
~
15
.II -!:>9
:;
I
PORT A
JI-!>1
,)1- 35
JI- !>.3
I
~
~
C'\
0=
•
0 SSc:It¢1
I\)
1'1
......
-
Jd
~~~~~~~~~~~~~
1
~
>~ I "'\>1
'!oS
__
......
\Q
-
-+---J.
••,1-'P"'6~
p~1~7
.g
I
~~--
,:;..
74L.!o<:J4-
00
VI
.9 IZ..Pl.
~"
EI03
0
PA¢ 4
=
C"l
.,'"
"q
£14
PFSIZ../
0--
7
P2~1>
til
tzl
'.
::
+5"
~
JI"!o1
JI-1.7
H
n
.11-2.9
JI-1.S
~
tzl
PORT C
~
~
L--J
!I c fOa! -r07
::T
I
I
o
§
J! ~ 2-1
JI-U
M
JI-!~
~
.11-11
(')
:x
i"-lJ'iS'
~
2:
010
I\)
()Q
,
1'1
I\)
PROGRAMMABLE
Ii
PERIPHERjC,~
,....
------7 JI- 7
)
, D-
INTERFACE:Z
J 1-
s
J 1-
~
J J- I
(PPI (0)
til
PORT
::T
(1)
(1)
l:
M
-..J
A
0
H'I
......
r:l
;'"' 1:,.1,
~
","
~"'
r==
--') j'_"
J,-.
-----c>
- - ) ,j 11
2
.
[Ij
)JI:"50
0
'-'
4
CAUTION:
B
These schematic diagrams may have been revised. See "Service
Information" chapter for details.
SERVICE INFORMATION
•
•
•
•
•
5-20
•
•
•
....
>zj
3~
~
'"'
LOWL.VL.z"
1~2C;-----"S.V
a
2.UN
!
r--;;::;;;
PI'!;
D
I
"sal ABI
N
AB0
A81
•
.....
en
='
C"l
'Z.
:tO~D
2.
LO'Jo./2.1
z.
2.
~
3'"
55
I
I
I
~
I
0
S.S(.~I/
V: qC5/
~
I
E28
E3Sro:'-t{' ,~
E207 06 d E.38~39
m
"o
.....
to:.
!II D3
!O D4z.ot; D5
L6 Db
l.l D7
I04
lOS
:0,,-,
101
::zIII
DI
D2
~~
()Q
'"'
III
OOPTj
00
4
4
4
DOprlZS
I
f.
I
7
---~>-----i-~ ----,-';0-1
G::>
XUIO
e
"""TO
en
t:I:J
j2-Z.S
~
Jz.-l.I
J<-U
(")
JZ-I!>
t:I:J
!
H
81
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~
~
)
,
------0»
sz
J2.-3,,3
JZ- 2
'Ii]
J2~50
)
J2.-S
;0
)
J2-i
1-===============±
1
~
J2.-z' 7
-!--..-------------------~
~~
~
Jz..z.,
pel
(pP! I)
H
..12.-31
Pa:~
J2-"!I
)~
PORT B
pe4rc~"~--------------------~~
(I)
"
J~
JZ·~S
PROGRLrY~Mj.:3LE
I
PORT A
J'-41
~z.-&!:I
I
PER I PHE?~L
INTEql-~,CE
.......
en
::r
(I)
~
)J2-1
E."'3
PORT C.
p~~'~B
S
~l
~
I'
E+Z
_
~3~·~'7___________________~_ _~
'!o~
32.
J2.-41
J'2.-4,
Eil
~
E,."IO-=-
eZ5;;A
=01
:OL
I
~
lsi',,, '''~'''T
I I I I
PC2~1"""''-------------t---~
f'~MJp~
)
-
:>cue
D
j~:::
~EZ9?
'"'
9 0 101/1 -101
+SII
~
Pc I IS
W
::r
SIolJ>..OOVV/O 4
"Trio&'
+5v
~.
III
~
'bPS, Ii:...~-tsv
~20
~
~
I~
I
•
3
~
I
! I
E26H_
Pc~ 14
\
I
E27
4
XU7
l.!.-
~
I
U20
~
7-
~
I
I
-,4014:1
~.----~.
PA3
PA7 37
....
....
Z
.~
.g
I
PA2
PAS
P.A6 Zoe.
00
V1
3
I
RDI
WR(
RST
®
N
PAl
e. AJ
I
r
A¢
I
4
PA4t- 40
'"
o='
u:s
'~.DSZ ~5
Cl
(I)
V1
•
PBSr
pe,~
A
o
P87~
I-h
......
o
XUII
'
W
i.
~
~) ~i:~~
)sJ'Z.·I~
JZ·,1
'---
CAUTION:
These schematic diagrams may have been revised. See "Service
Information" chapter for details.
"
SERVICE INFORMATION
•
•
•
•
•
5-22
•
•
I
....
>%j
()Q
J.~~
D
\J1
.
N
~
i
4
eu~
2..
De.¢-ot:.7
rill
-
~J;,e
t
liD [}\TA Bl.JFFER
107
..15 _z.j MOG:.
..15 _I") MD7
rOI
-t
.-----(
J+-'
-----< J +- 10
J'" - ~
--< J4-ts
- < J5 -
j~ =~~ ~~:¢jl
MDZ
MDb
J4-10) MD7
A~ Jt-II
~~S~RVED
SBXBo~ ~!=~ ~~~~
£104
5BXAOPTI
Eas
S6XBDPTj
:'::..15 -z.&OPT!
J5-3Z, MDACK/
J5 -,3(Q +SV
-- j"s -i8 ;-5\/
+~v
2~; =~ ~,I~:'
'::-
~ J5
1'1
III
+3V
::~~
:
I
MDKK/
~V
§ .)
_
4-35
~
----< J~:=
4 -34-
.... 5v
_
H
GND
o
~.~6
Z
M:CRGT
~I
.
~ j~~i~ ~;~:;:~¢
SBX91NT
0
SBxe lNT I
MWAIT S/
-
010
010
10
[J
I-
SB'><_A----.!.!::!I... 0)0
SBXA lNT \
MWAIT A. /
::r
CD
CD
rt
L
SBX
INTERFACe:
010
010
CONNECTCRS
~
0
HI
......
0
'-'
f
CAUTION:
~
~
+5V
~ ~1=~ -:I~_:
~
MDRen
IC---:i~; ::! ~:~~~~
()Q
tz:I
J.-
J4-z.e OPTl
--CQ
tJ--------< J4-IB
~ J4-4
J5 -35 GND
t------S 3~ -'+
~~ ~~g
~
III
(j
.;+-to MCSl!
E%
c=::;
~
H
MP5T/
SBXAOPT~ j:-_~~ ~~~~
::~~
t:.I
RESERVED
MC.LK
Ek:}5
J5 -4
Ct.l
MAl
MAal
~: ~~ ~~¢T/
J5 -%0 Me':!l!
b--<
(')
.;4 -2..1
A.BI
+$V -----+--~
rt
....
-2...'
..14
..14 -z1 MD3
..14 -Z.5 MD4
..14 -z.'3 MDS
ABz< j!=~'"
MAl
J!5 -II MA¢'
I-
..1+ '~I MOl
IDa
104
----<
m
~: ~~ ~~~V
I03
I06
TO?
Ie RE':!ERVED
--<..15 -Ct;, MeLK
..15 -6 MP5T/
4- '::::' sex'... C$(t>/
4 ... !>t.X p,C.SI/
R.5ET
J4 -13 J:.OvoJRT/
,..e.~ j;=~4 r~~~ERV=D
Ae.
III
\0
~5B"''=>Ic:.NA.L
52JO - .
i
A e . I ' ; 5 --,
.--. !OOl-I01
::r
a
""'
Ct.l
II
I
I
-I.., MD 2
104
lOS
-<
~
(')
J'-
".)5 -2.7 MD:3
.15 -z.s MD 4
J5 -~ MDS
ro~
IO~).J
II
Ica'
J5 _~I MD ,
IOI
4- [)
II
D
(~; =~ ~ODR~/
IO~
tld
0
III
1'1
N
W
[DIP
!
lOZ.
Q\
JS-S REsrr
( J5 9Ib=:OWAT!
S2.
......
Ct.l
eSBX 516"",-
~
00
I
i
I
DIll.
®
\J1
,
1>..&x&lrr.lr¢
t-'
t1§
'"
0
I,.QWI,..VI...z..
~
I-'tr.I
=
n
®
1~-rs5
E'~ '~
~&)(A INT¢
00
(1'1
=
cl
R..2;t
t;
I
VI
?4L~Z.
104
~
MWAIT"";
9
IoAW,Io.IT'
..
.'w
s
W
::r
m
III
0
a
en
tz:I
.sv
I
~
,,-pz
1l.Pz.
H
10<-
101::....
e
6
(")
13
61
:~
tz:I
!.l2S 8
.9
H
74L.~U)
Z
t'Zj
I
';!A_Gt:..!
IWv'IN
lE.97
\VAIT"
O~
INiERRUPT
GENERATION
LOGIC
14t...$O'Z.
13
0>,) e.IZ.D
PI-2.!! (
2..
IQIC..
4
rt
I-'-
f,1Z.f"'£:'
I",""
U 2.3)6
9
8~
I
Q.
to.)
E.7"'1
d
!§>"
It.,ji5J/
"
0
III
VI
10
EI6S
pl=lloJl
E.lt:j 1~'tIO!.O
PI--4Z.(
"-P2
(12
:)E.96
0.68
"-
READY GENER-'lTIOI\.
LOGIC
11-1
~4Sv
~
2..
III
a S>Y_"'_'-_'_ _ __
"
EZ
10
01
~4-51/
10"-
OQ
t;
I. ~
H
0
47"-
IZ.U~
Z
08
TI~./,E
CUT
10 MSEC NOMINAL
III
S
~+Sl/
1"-
"'"'
tr.I
z...
::r
0 WAIT/
EI~2: ~3
W4.1T!
) PZ.-30
C'D
C'D
rt
t-'
0
0
"
"
t"1'a
t-'
0
'"'"
CAUTION:
These schematic diagrams may have been revised. See "Service
Information" chapter for details.
SERVICE INFORMATION
•
•
•
•
r
•
5-26
•
APPENDIX A.
A-I.
DECODE PROM PROGRAMMING
INTRODUCTION
The local memory and I/O address decoding and chip select generation on
the iSBC SO/16 board is performed via a factory programmed memory decode
PROM (U33) on the board. The PROM contains a bit pattern that decodes
the ten input address lines, reads data from a memory location, and
provides four output signals whose states depend on the data.
•
The iSBC SO/16 board provides you a certain amount of configuration
control by allowing you to change the data that is stored; for other than
option 8, this involves providing an entirely new decode PROM. Note that
option 8, the user programmed option, contains OFH (unprogrammed)
throughout that portion of the PROM (for both memory and I/O).
A-2.
•
•
DECODE PROM FUNCTION DESCRIPTION
The decode PROM on the iSBC SO/16 board consists of a 3625A PROM, an
lS-pin device that is preprogrammed to output a specific bit pattern for
a specific range of addresses. By changing the data pattern within the
decode PROM, you cause the iSBC SO/16 board to generate a different
output signal pattern for any given memory or I/O address. As a result
of changing the output signal pattern, you control which chip select
signal is generated on the board.
The decode PROM uses address bits AA through AF, DOPTO, DOPTl, DOPT2, and
the IO/M signals as address bits for the decode PROM. Figure A-I shows
how the various signals and address bits are assembled to form a ten-bit
PROM address and shows a relationship between the chip select signals and
the decode PROM input signals on the iSBG SO/16 board •
The IO/M signal enables generation of an I/O chip select when LOW and
enables generation of the memory chip select signals when HIGH. The
DOPTO, DOPTl, and DOPT2 signals are user-configured via jumpers and
select one of the eight sections of the decode PROM. Selecting one of
the eight memory map configurations is performed by connecting jumper
posts on the iSBC SO/16 board as described in paragraph 2-13 of this
manual.
Depending on the data stored within the selected area of the decode PROM,
the decode PROM generates a specific chip select signal on the board.
The correlation between a particular data byte and the chip select
signals that it generates is described in Table A-I. Those data patterns
that are not listed may cause undesireable results and should be avoided.
•
The procedure for writing data into one of the 3625A decode PROMs may
vary depending on the type of PROM programming device used; refer to the
operator's manual on the PROM programming device for details of a
specific programming procedure.
A-I
PROGRAMMING THE DECODE PROM
A-3.
PROGRAMMING OPTION 8
When providing programming for option 8 of the existing 3625A Decode
PROM, you must copy the contents of the other seven options into the
memory buffer within the PROM programming device, add to that the
requirements for option 8 of the Decode PROM, and then rewrite the entire
PROM rather than just the option 8 portion of the decode PROM. This
method avoids errant entries into the other option areas of the decode
PROM that would cause faulty operation of options 1 through 7.
A-4.
•
PROM DATA DEFINITIONS
Each option provided by the decode PROM contains sufficient space (64
possible entries) to define the entire 256 bytes of I/O space (if IO/M is
LOW) or the 64k bytes of memory space (if IO/M is HIGH).
In Figure A-2, the contents of the upper left memory location within each
option define the chip select signal that is generated for all accesses
to I/O addreses 0 through 3H (a 4 byte block). The next entry to the
right defines the chip select signal that is generated for all accesses
to I/O locations 4H through 7H, and so on, through the 64 data entries
within each option. The last entry in each option defines the chip
select signal that is generated for all accesses to I/O addresses F8H
through FFH.
In Figure A-3, the contents of the upper left memory location within each
option define the chip select signal that is generated for all accesses
to memory locations 0 through 3FFH (a lk byte block). The next entry to
the right defines the chip select signal that is generated for all
accesses to memory locations 0400H through 07FFH, and so on, through the
64 data entries within each option. The last entry in each option
defines the chip select signal that is generated for all accesses to
memory locations FOOOH through FFFFH.
•
•
•
•
PROGRAMMING THE DECODE PROM
•
Table A-I.
Type Of
Operation
Stored Data
Chip Select
Value
Signal Generated
OF
OE
OD
Memory
Memory
Memory
Memory
Memory
Memory
Memory
•
Data Entries For The Decode PROM
OC
OB
OA
00
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OF
OE
OD
OC
DB
OA
09
00
Function Performed
By the Chip Select
BWCSO/
BWCSI/
BWCS2/
BWCS3/
BWCS4/
BWCS5/
none
Chip select for U4l
Chip select for U42
Chip select for U43
Chip select for U44
Chip select for U45
Chip select for U46
No local c.hip select
generated; operation is for
an off-board resource •
SBXA.CSO/
SBXA.CSI/
SBXBCSO/
SBXBCSl/
55CSO/
55CSI/
5ICS/
none
Chip select for J5, MCSO/
Chip selec:t for J5, MCS1/
Chip select for J4, MCSO/
Chip select for J4, MCSl/
Chip select for 8255 PPI U19
Chip seleet for 8255 PPI U20
Chip select for 8251 PCI
No local chip select
generated; operation is for
an off-board resource.
•
•
PROM
Address
9
Bit
8
10/M DOPT2
I
6
7
DOPT1
DOPTO
V'
1
5
4
3
2
I
0
AF
AE
AD
AC
AB
AA
I
'V"
+
1
Upper address lines from CPU
User-configured via jUlllpers
I
0=1/0 map selected
l=Memory map selected
•
Figure A-I.
Ten-bit PROM Address Creati.on
A-3
1
PROGRAMMING THE DECODE PROM
Decode
PROM
Address
(hex) 0
•
DOPTO
DOPT1
DOPT2
1
2
3
4
5
6
7
8
000
010
020
030
OF OF OF
OF OF OF
OF OF OF
OF OF OF
040
050
060
070
00
00
00
OD
00
00
00
OD
00 00 00 00
00 00 00 00
00 00 00 00
OC OC 00 00
00
00
00
00
00
00
00
00
00
00
00
00
080
090
OAO
OBO
00
00
00
OD
00
00
00
OD
00 00 00 00
00 00 00 00
00 00 00 00
OC OC 00 00
00
00
00
00
00
00
00
00
OCO
ODO
OEO
OFO
00
00
00
00
00
00
00
00
00 00 00 00
00 00 00 00
00 00 00 00
OC OC 00 00
00
00
00
00
100
110
120
130
00
00
00
OD
00
00
00
00
00 00 00 00
00 00 00 00
00 00 00 00
OC OC 00 00
140
150
160
170
00
00
00
OD
00
00
00
OD
180
190
lAO
lBO
00
00
00
OD
1CO
100
lEO
1FO
00
00
00
OD
9
ABC
OF OF OF OF OF OF OF OF OF OF
OF OF OF OF OF OF OF OF OF OF
OF OF OF OF OF OF OF OF OF OF
OF OF OF OF OF OF OF OF OF OF
0
E F
OF OF
OF OF
OF OF
OF OF
OF
OF
00 00 00 00
00 00 00 00
00 00 00 00
OB OA 09 OF
00
00
00
OF
00
00
00
OE
00
00
00
OE
00
00
00
00
00 00 00 00
00 00 00 00
00 00 00 00
OB OA 09 OF
00
00
00
OF
00 00
00 00
00 00
OE OE
00
00
00
00
00
00
00
00
00 00 00 00
00 00 00 00
00 00 00 00
OB OA 09 OF
00 00 00
00 00 00
00 00 00
00
00
00
00
00
00
00
00
00
00
00
00
00 00 00 00
00 00 00 00
00 00 00 00
OB OA 09 OF
00
00
00
OF
00 00
00 00
00 00
00 00 00 00
00 00 00 00
00 00 00 00
OC OC 00 00
00
00
00
00
00
00
00
00
00
00
00
00
00 00 00 00
00 00 00 00
00 00 00 00
OB OA 09 OF
00
00
00
OF
00 00
00 00
00 00
OE OE
00
00
00
OD
00 00 00 00
00 00 00 00
00 00 00 00
OC OC 00 00
00
00
00
00
00
00
00
00
00
00
00
00
00 00 00 00
00 00 00 00
00 00 00 00
OB OA 09 OF
00
00
00
OF
00 00
00 00
00 00
00
00
00
00
00 00 00 00
00 00 00 00
00 00 00 00
OC OC 00 00
00
00
00
00
00
00
00
00
00
00
00
00
00 00 00 00
00 00 00 00
00 00 00 00
OB OA 09 OF
00 00 00
00 00 00
00 00 00
OF OE OE
Figure A-2.
OF
OF
000
0 0 1
UserDefined
•
0 1 0
0 1 1
OF OE OE
•
1 0 0
OE OE
1 0 1
•
1 1 0
OE OE
I/O Map in the Decode PROM
A-4
I
1 1 1
•
PROGRAMMING THE DECODE PROM
•
•
•
•
•
DOPTO
DOPT1
DOPT
Decode
PROM
Address
(hex) 0
1
2
3
4
5
6
7
8
9
OF
OF
OF
OF
ABe
OF
OF
OF
OF
OF
OF
OF
OF
E
F
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
200
210
220
230
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
OF
240
250
260
270
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF OF OF OF OF OF OF OF
OE OE OE OE OE OE OE DE
280
290
2A0
2BO
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OA
OF
OE
00
OB
2eo
200
2EO
2FO
OF
00
00
OA
OF
00
00
OA
OF
00
00
OA
OF
00
00
OA
OF
00
00
OA
OF
00
00
OA
OF
00
00
OA
OF
00
00
OA
OE OE OE OE OE OE OE OE
300
310
320
330
OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF
OE OE OE OE OE OE OE OE OE OE OE OE OE OE DE OE
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
OC OC OC OC OC OC OC OC OC OC OC OC OA OA OB OB
340
350
360
370
OF
00
00
00
OF
00
00
00
OF
00
00
00
OF
00
00
00
OF
00
00
00
OF
00
00
00
OF
00
00
00
OF
00
00
00
00 00 00 00 00 00 00 00
00 00 00 00 OA OA OB OB
380
390
3AO
3BO
OF
OA
00
00
OF
OA
00
00
OF
OB
00
00
OF
OB
00
00
OE
00
00
00
OE
00
00
00
OE
00
00
00
OE
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00 00 00 00
00 00 00 00
00 00 00 00
3eo
300
3EO
3FO
OF OF OE OE
00 00 00 00
00 00 00 00
00 00 00 00
00
00
00
00
00
00
00
00
OC OC 00 00
00 00 00 00
00 00 00 00
00 00 00 00
00
00
00
00
00
00
00
00
OA
00
00
00
Figure A-3.
OF
OF
OF
OF
0
OC OC OC OC OC OC OC OC
.
~
o0
0
0 0 1
OB OB OB OB OB OB OB OB
OF OF OF OF OF OF OF
OE OE OE DE OE DE DE
00 00 00 00 00 00 00
0 1 0
OB OB OB OB OB OB OB
OC OC OC OC OC OC OC OC
00 00 00 00 00 00 00 00
DB OB OB OB OB OB OB OB
0 1 1
1 0 0
OE OE OE OE OE OE OE OE
OC OC OC OC OC OC OC OC
1 0 1
OC OC OC OC
OA
00
00
00
1 1 0
OB OB
00 00
00 00
00 00
1 1 1
Memory Map in the Decode PROM
A-5
UserDefined
•
•
•
•
..
•
INDEX
•
•
•
•
.
•
Addressing
I/O 3-2
Memory 3-1
Operation 4-5
CPU 1-4, 4-2
Cabling
Barallel I/O 2-49
Serial I/O 2-49
Chip Select 4-5
Clock Circuits 4-2
Oooling Requirements 2-2
Decode PROM 2-19, A-1
Emulation Mode 2-26
Equipment Supplied 1-4
I/O Addressing 3-2
Initialization 3-2
Installation 2-1
2708 EPROM Devices 2-22
Byte-Wide RAM Devices 2-22
EEPROM Devices 2-23
EPROM Devices 2-19
iSBX Multimodule Board 2-52
Line Driver 2-11
Memory Device 2-9
Interface
Auxiliary (P2) 2-44
iSBX Mu1timodu1e Board 2-51, 4-6
Serial I/O 2-49, 4-3
Bara1lel I/O 2-45, 4-4
Interrupts 1-2, 2-31, 4-11
iRMX 80 Software 2-54
iSBX Bus
Information 2-51
Installation 2-52
Operation 4-6
Pin Assignments 2-51
Signal Descriptions 2-52
JEDEC Memory Socket Bairs 2-10
JEDEC-COmpatible Memory 4-5
Jumpers
8255A PPI 2-29
82SlA PCI/Serial Interface 2-32
Baud Rate Generator 2-28
Emulation Mode 2-26
Interrupt 2-31
wcation Diagram 2-13
Mu1tibus Interface 2-33
Numerical List 2-14 to 2-18
Ready Circuitry 2-27
Timeout 2-33
Wait-state 2-28
Memory
Addressing 3-1
Map 3-2
Index-1
Multibus
AC Characteristics 2-39, 2-40
Control Exchange Timing 2-43
DC Characteristics 2-37
Signal Characteristics 2-34
Interface 4·-6
IbId Sequence 4-7
Interrupt Sequence 4-7
Jumper Options 2-33
Memory and I/O Timing (READ) 2-42
Memory and I/O Timing (WRITE) 2-41
Signal Descriptions 2-36
Multimodu1e 1-2, 2-S2, 4-6
Parallel I/O Interface
Cabling 2-49
Information 2-45
DC Characteristics 2-48
Operation 4-4
Pin Assignments 2-46, 2-47
Parts 5-1
Physical Dimens:ions 2-2
Pin Assignments:
Auxiliary Connector (P2) 2-4S
iSBX Bus 2-Sl
Multibus (Pl) 2-35
Parallel I/O Connector J1 2-46
Parallel I/O Connector J2 2-47
Serial I/O Connector J3 2-S0
Power Requirements 2-2
Programming
82SlA PCI Programming 3-4
8255A PPI Programming 3-13
Decode PROM. Programming
RS232C Cable Types 2-S0
Repair 5-4
Reset 3-8
Serial I/O Interface
Cabling 2-49
Information 2-49
Jumper Configurations 2-32
Operation 4-3
Pin Assignments 2-50
Service Assistance 5-4
Service Diagrams 5-1
Shadow Memory 2-26
Shadow Memory 2-26
Specifications 1-4
System Software 1-4
Unpacking 2-1
Wait-state Jumper 2-28
•
•
•
•
•
iSBC® 80/16 Single Board Computer
Hardware Reference Manual
144779-001
•
REQUEST FOR READER'S COMMENTS
Intel's Technical Publications Departments attempt to provide publications that meet the needs of all Intel
product users. This form lets you participate directly in the publication process. Your comments will help
us correct and improve our publications. Please take a few minutes to respond.
Please restrict your comments to the usability, accuracy, readability, organization, and completeness of
this publication. If you have any comments on the product that this publication describes, please contact
your Intel representative. If you wish to order publications, contact the Intel Literature Department (see
page ii of this manual).
1. Please describe any errors you found in this publication (include page number) .
•
•
•
2.
Does the publication cover the information you expected or required? Please make suggestions for
improvement.
3.
Is this the right type of publication for your needs? Is it at the right level? What other types of
publications are needed?
4.
Did you have any difficulty understanding descriptions or wording? Where?
5.
Please rate this publication on a scale of 1 to 5 (5 being the best rating). _ _ _ _ _ _ _ __
NAME _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
•
DATE _ _ _ _ _ _ __
TITLE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
COMPANYNAME/DEPARTMENT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
ADDRESS _________________________________________________________________
CITY _________________________
STATE _ _ _ _ _ ___
(COUNTRY)
Please check here if you require a written reply.
0
ZIP CODE _ _ _ _ _ __
WE'D LIKE YOUR COMMENTS ...
This document is one of a series describing I ntel products. Your comments on the back of this form
will help us produce better manuals. Each reply will be carefully reviewed by the responsible
person. All comments and suggestions become the property of Intel Corporation.
III "I
BUSINESS
FIRST CLASS
REPLY
PERMIT NO. 79
MAIL
BEAVERTON, OR
POSTAGE WILL BE PAID BY ADDRESSEE
NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES
•
•
•
Intel Corporation
5200 N.E. Elam Young Pkwy.
Hillsboro, Oregon 97123
OMO Technical Publications
•
•
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : Yes Create Date : 2012:12:04 19:37:11-07:00 Creator : Microtek ScanWizard 5 Modify Date : 2012:12:05 15:39:13-07:00 XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:08:04 Creator Tool : Microtek ScanWizard 5 Metadata Date : 2012:12:05 15:39:13-07:00 Producer : Adobe Acrobat 9.52 Paper Capture Plug-in Format : application/pdf Document ID : uuid:c1e06d08-2f90-4417-b3d7-5062b872ad8c Instance ID : uuid:fc2fb90e-624f-495d-9d75-98bb477d034f Page Count : 132EXIF Metadata provided by EXIF.tools