1502234_PC_Technical_Reference_Apr83 1502234 PC Technical Reference Apr83
User Manual: 1502234_PC_Technical_Reference_Apr83
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LIMITED WARRANTY The International Business Machines Corporation warrants this IBM Personal Computer Product to be in good working order for a period of 90 days from the date of purchase from IBM or an authorized IBM Personal Computer dealer. Should this Product fail to be in good working order at any time during this 90-day warranty period, IBM will, at its option, repair or replace this Product at no additional charge except as set forth below. Repair parts and replacement Products will be furnished on an exchange basis and will be either reconditioned or new. All replaced parts and Products become the property of IBM. This limited warranty does not include service to repair damage to the Product resulting from accident, disaster, misuse, abuse, or non-IBM modification of the Product. Limited Warranty service may be obtained by delivering the Product during the 90-day warranty period to an authorized IBM Personal Computer dealer or IBM Service Center and providing proof of purchase date. If this Product is delivered by mail, you agree to insure the Product or assume the risk of loss or damage in transit, to prepay shipping charges to the warranty service location and to use the original shipping container or equivalent. Contact an authorized IBM Personal Computer dealer or write to IBM Personal Computer, Sales and Service, P.O. Box 1328-W, Boca Raton, Florida 33432, for further information. ALL EXPRESS AND IMPLIED WARRANTIES FOR THIS PRODUCT INCLUDING THE WARRANTIES OF MERCHANTABILITY AND FITNESS FORA PARTICULAR PURPOSE, ARE LIMITED IN DURATION TO A PERIOD OF 90 DAYS FROM THE DATE OF PURCHASE, AND NO WARRANTIES, WHETHER EXPRESS OR IMPLIED, WILL APPLY AFTER THIS PERIOD. SOME STATES DO NOT ALLOW LIMITATIONS ON HOW LONG AN IMPLIED WARRANTY LASTS, SO THE ABOVE LIMITATIONS MAY NOT APPLY TO YOU. IF THIS PRODUCT IS NOT IN GOOD WORKING ORDER AS WARRANTED ABOVE, YOUR SOLE REMEDY SHALL BE REP AIR OR REPLACEMENT AS PROVIDED ABOVE. IN NO EVENT WILL IBM BE LIABLE TO YOU FOR ANY DAMAGES, INCLUDING ANY LOST PROFITS, LOST SAVINGS OR OTHER INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF OR INABILITY TO USE SUCH PRODUCT, EVEN IF IBM OR AN AUTHORIZED IBM PERSONAL COMPUTER DEALER HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, OR FOR ANY CLAIM BY ANY OTHER PARTY. SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR CONSUMER PRODUCTS, SO THE ABOVE LIMITATIONS OR EXCLUSIONS MAY NOT APPLY TO YOU. THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS, AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH MAY VARY FROM STATE TO STATE. ------- --- ----- - --------_.- Technical Reference Personal Computer Hardware Reference Library Federal Communications Commission Radio Frequency Interference Statement WARNING: This equipment has been certified to comply with the limits for a Class B computing device, pursuant to Subpart J of Part 15 of FCC rules. Only peripherals (computer input/output devices, terminals, printers, etc.) certified to comply with the Class B limits may be attached to this computer. Operation with non-certified peripherals is likely to result in interference to radio and TV reception. If peripherals not offered by IBM are used with this equipment, it is suggested to use shielded grounded cables with in-line filters if necessary. Notice: As sold by the manufacturer, the Prototype card does not require certification under the FCC's rules for Class B devices. The user is responsible for any interference to radio or TV reception which may be caused by a user-modified prototype card. CAUTION: This product is equipped with a UL-listed and CSA-certified plug for the user's safety. It is to be used in conjunction with a properly grounded receptacle to avoid electrical shock. Revised Edition (April 1983) Changes are periodically made to the information herein; these changes will be incorporated in new editions of this publication. Products are not stocked at the address below. Requests for copies of this product and for technical information about the system should be made to your authorized IBM Personal Computer dealer. A Reader's Comment Form is provided at the back of this pUblication. If this form has been removed, address comments to: IBM Corp., Personal Computer, P.O. Box 1328-C, Boca Raton, Florida 33432. IBM may use or distribute any of the information you supply in any way it believes appropriate without incurring any obligations whatever. © ii Copyright International Business Machines Corporation, 1981, 1982, 1983 PREFACE The IBM Personal Computer Technical Reference manual describes the hardware design and provides interface information for the IBM Personal Computer. This publication also has information about the basic input/output system (BIOS) and programming support. The information in this pUblication is both introductory and for reference, and is intended for hardware and software designers, programmers, engineers, and interested persons who need to understand the design and operation of the computer. You should be familiar with the use of the Personal Computer, and you should understand the concepts of computer architecture and programming. This manual has two sections: "Section 1: Hardware" describes each functional part of the system. This section also has specifications for power, timing, and interface. Programming considerations are supported by coding tables, command codes, and registers. "Section 2: ROM BIOS and System Usage" describes the basic input/output system and its use. This section also contains the software interrupt listing, a BIOS memory map, descriptions of vectors with special meanings, and a set oflow memory maps. In addition, keyboard encoding and usage is discussed. The publication has seven appendixes: Appendix A: Appendix B: Appendix C: Appendix D: Appendix E: Appendix F: Appendix G: ROM BIOS Listings 8088 Assembly Instruction Set Reference Of Characters, Keystrokes, and Color Logic Diagrams Specifications Communications Switch Settings A glossary and bibliography are included. iii Prerequisite Publication: Guide to Operations for the IBM Personal Computer Part Number 6025000 Suggested Reading: BASIC for the IBM Personal Computer Part Number 6025010 Disk Operating System (DOS) for the IBM Personal Computer Part Number 6024061 Hardware Maintenance and Service for the IBM Personal Computer Part Number 6025072 MACRO Assembler for the IBM Personal Computer Part Number 6024002 Related publications are listed in the bibliography. iv TABLE OF CONTENTS Section 1: Hardware IBM Personal Computer System Unit ................. IBM Personal Computer Math Coprocesser ............ IBM Keyboard .................................... IBM Expansion Unit ............................... IBM 80 CPS Printers .............................. IBM Printer Adapter ............................... IBM Monochrome Display and Printer Adapter ........ IBM Monochrome Display .......................... IBM Color/Graphics Display Adapter ................ IBM Color Display ................................ IBM 5-W' Diskette Drive Adapter ................... IBM 5-W' Diskette Drive ........................... Diskettes ......................................... IBM Fixed Disk Drive Adapter ...................... IBM 10MB Fixed Disk Drive ....................... IBM Memory Expansion Options .................... IBM Game Control Adapter. . . . . . . . . . . . . . . . . . . . . . . .. IBM Prototype Card ............................... IBM Asynchronous Communications Adapter. . . . . . . . .. IBM Binary Synchronous Communications Adapter ..... IBM Synchronous Data Link Control (SDLC) Communication Adapter .......................... IBM Communications Adapter Cable ................. 1-3 1-33 1-73 1-79 1-91 1-117 1-123 1-131 1-133 1-157 1-159 1-183 1-185 1-187 1-203 1-205 1-211 1-217 1-223 1-251 1-271 1-301 Section 2: ROM BIOS and System Usage ROM BIOS ....................................... 2-2 Keyboard Encoding and Usage ...................... 2-11 BIOS Cassette Logic ............................... 2-21 Appendix A: ROM BIOS Listings .............. A-I System BIOS ..................................... A-2 Fixed Disk BIOS .................................. A-85 Appendix B: 8088 Assembly Instruction Set Reference ................................. B-1 v Appendix C: Of Characters, Keystrokes, and Colors .................................... C-l Appendix D: Logic Diagrams ................... D-l System Board (16/64K) ............................ System Board (64/256K) ........................... Keyboard - Type 1 ................................ Keyboard - Type 2 ................................ Expansion Board .................................. Extender Card .................................... Receiver Card .................................... Printer ........................................... Printer Adapter ................................... Monochrome Display Adapter ...................... Color/Graphics Monitor Adapter .................... Color Display .................................... Monochrome Display .............................. 5-JA Inch Diskette Drive Adapter .................... 5-JA Inch Diskette Drive - Type 1 ................... 5-JA Inch Diskette Drive - Type 2 ................... Fixed Disk Drive Adapter .......................... Fixed Disk Drive - Type 1 ......................... Fixed Disk Drive - Type 2 ......................... 32K Memory Expansion Option ..................... 64K Memory Expansion Option ..................... 64/256K Memory Expansion Option ................. Game Control Adapter ............................. Prototype Card ................................... Asynchronous Communications Adapter .............. Binary Synchronous Communications Adapter ......... SDLC Communications Adapter .................... D-2 D-12 D-22 D-24 D-25 D-26 D-29 D-32 D-35 D-36 D-46 D-52 D-54 D-55 D-59 D-62 D-64 D-70 D-73 D-76 D-79 D-82 D-86 D-87 D-88 D-89 D-91 Appendix E: Specifications ..................... E-l Appendix F: Communications .................. F-l Appendix G: Switch Settings ................... G-l Glossary ........................................ H-l Index ............................................ 1-1 vi INDEX TAB LISTING Section 1: Hardware ............................. . Section 2: ROM BIOS and System Usage .......... . Appendix A: ROM BIOS Listings ................. . Appendix B: 8088 Assembly Instruction Set Reference Appendix C: Of Characters, Keystrokes, and Color Appendix D: Logic Diagrams ..................... . vii viii Appendix E: Specifications ....................... . Appendix F: Communications ..................... . Appendix G: Switch Settings ...................... . Glossary ........................................ . Bibliography ..................................... . Index ........................................... . ix x SECTION 1: HARDWARE IBM Personal Computer System Unit ................. IBM Personal Computer Math Coprocesser ............ IBM Keyboard .................................... IBM Expansion Unit ............................... IBM 80 CPS Printers .............................. IBM Printer Adapter ............................... IBM Monochrome Display and Printer Adapter ........ IBM Monochrome Display .......................... IBM Color/Graphics Display Adapter ................ IBM Color Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. IBM 5-14" Diskette Drive Adapter ................... IBM 5-1A" Diskette Drive ........................... Diskettes ......................................... IBM Fixed Disk Drive Adapter ...................... IBM 10MB Fixed Disk Drive ....................... IBM Memory Expansion Options .................... IBM Game Control Adapter. . . . . . . . . . . . . . . . . . . . . . . .. IBM Prototype Card ............................... IBM Asynchronous Communications Adapter .......... IBM Binary Synchronous Communications Adapter ..... IBM Synchronous Data Link Control (SDLC) Communication Adapter .......................... IBM Communications Adapter Cable ................. 1-3 1-33 1-73 1-79 1-91 1-117 1-123 1-131 1-133 1-157 1-159 1-183 1-185 1-187 1-203 1-205 1-211 1-217 1-223 1-251 1-271 1-301 1-1 SYstem Unit Expansion Unit System Board Expansion Board Oscillator 8088 Cassette Adapter 8 Interrupt levels Speaker Adapter 4 Channels Direct Memory Access Memory Oscillator Keyboard Adapter Read-Only Memory Math Coproctlssor (Optional) 8 Slot Expanded 110 Channel Receiver Card 5 Slot 110 Channel Extender Card Monochrome 0 isplay and Printer Adapter Monochrome Oisplay Diskette Drive Adapter Diskette Drive(s) Prototype Card Color Display Game Control Adapter Matrix Printer Light Pen Printer Adapter Home Television Binary Synchronous Communications Adapter System Block Diagram 1-2 System Unit Synchronous Data Link Control (SOlC) Adapter IBM Personal Computer System Unit The system unit is the standalone tabletop unit that contains the power supply, the speaker, and the system board. The system unit contains one of two system boards. One system board supports 16K to 64K of read/write memory. The other system board supports 64K to 256K of read/write memory. Both system boards are functionally identical. The power supply provides dc voltage to the system board and the internal drive( s). System Board The system board fits horizontally in the base of the system unit and is approximately 8-1/2 by 12 inches. It is a multilayer, single-Iand-per-channel design with ground and internal planes provided. DC power and a signal from the power supply enter the board through two six-pin connectors. Other connectors on the board are for attaching the keyboard, audio cassette, and speaker. Five 62-pin card edge-sockets are also mounted on the board. The I/O channel is bussed across these five I/O slots. Two dual-in-line package (DIP) switches (two eight-switch packs) are mounted on the board and can be read under program control. The DIP switches provide the system software with information about the installed options, how much storage the system board has, what type of display adapter is installed, what operation modes are desired when power is switched on (color or black-and-white, 80- or 40-character lines), and the number of diskette drives attached. The system board consists of five functional areas: the processor subsystem and its support elements, the read-only memory (ROM) subsystem, the read/write (RIW) memory subsystem, integrated I/O adapters, and the I/O channel. All are described in this section. System Unit 1· 3 The heart of the system board is the Intel 8088 microprocessor. This processor is an 8-bit external bus version of Intel's 16-bit 8086 processor, and is software-compatible with the 8086. Thus, the 8088 supports 16-bit .operations, including multiply and divide, and supports 20 bits of addressing (1 megabyte of storage). It also operates in maximum mode, so a co-processor can be added as a feature. The processor operates at a 4.77 MHz. This frequency, which is derived from a 14.31818-MHz crystal, is divided by 3 for the processor clock, and by 4 to obtain the 3.S8-MHz color burst signal required for color televisions. At the 4.77-MHz clock rate, the 8088 bus cycles are four clocks of 210 ns, or840 ns.I/O cycles take five 21O-ns clocks or 1.05 microseconds. The processor is supported by a set of high-function support devices providing four channels of 20-bit direct-memory access (DMA), three 16-bit timer-counter channels, and eight prioritized interrupt levels. Three of the four DMA channels are available on the I/O bus and support high-speed data transfers between I/O devices and memory without processor intervention. The fourth DMA channel is programmed to refresh the system dynamic memory. This is done by programming a channel of the timer-counter device to periodically request a dummy DMA transfer. This action creates a memory-read cycle, which is available to refresh dynamic storage both on the system board and in the system expansion slots. All DMA data transfers, except the refresh channel, take five processor clocks of 210 ns, or 1.05 Jls if the processor-ready line is not deactivated. Refresh DMA cycles take four clocks or 840 ns. The three programmable timer/counters are used by the system as follows: Channel 0 is used as a general-purpose timer providing a constant time base for implementing a time-of-day clock; Channel 1 is used to time and request refresh cycles from the DMA channel; and Channel 2 is used to support the tone generation for the audio speaker. Each channel has a minimum timing resolution of 1.05 us. 1-4 System Unit Of the eight prioritized levels of interrupt, six are bussed to the system expansion slots for use by feature cards. Two levels are used on the system board. Level 0, the highest priority, is attached to Channel 0 of the timer/counter and provides a periodic interrupt for the time-of-day clock. Level 1 is attached to the keyboard adapter circuits and receives an interrupt for each scan code sent by the keyboard. The non-maskable interrupt (NMI) of the 8088 is used to report memory parity errors. The system board supports both ROM and R/W memory. It has space for 48K x 8 of ROM or EPROM. Six module sockets are provided, each of which can accept an 8K by 8 byte device. Five of the sockets are populated with 40K bytes of ROM. This ROM contains the cassette BASIC interpreter, cassette operating system, power-on self-test, I/O drivers, dot patterns for 128 characters in graphics mode, and a diskette bootstrap loader. The ROM is packaged in 24-pin modules and has an access time of 250 ns and a cycle time of 375 ns. The difference between the R/W memory on the two system boards is shown in the following chart. System Board Minimum Storage Maximum Storage Memory Modules Soldered (Bank 0) Pluggable (Bank 1·3) 16/64K 16K 64K 16K by 1 Bit 1 Bank of 9 3 Banks of 9 64/256K 64K 256K 64K by 1 Bit 1 Bank of 9 3 Banks of 9 Memory greater than either system board's maximum is obtained by adding memory cards in the expansion slots. All memory is parity-checked and consists of dynamic 16K by 1 bit or (64K by 1 bit) chips with an access time of 250 ns and a cycle time of 410 ns. System Unit 1·5 The system board contains circuits for attaching an audio cassette, the keyboard, and the speaker. The cassette adapter allows the attachment of any good quality audio cassette through the earphone output and either the microphone or auxiliary inputs. The system board has a jumper for either input. This interface also provides a cassette motor control line for transport starting and stopping under program control. This interface reads and writes the audio cassette at a data rate of between 1,000 and 2,000 baud. The baud rate is variable and dependent on data content, because a different bit-cell time is used for O's and 1'so For diagnostic purposes, the tape interface can loop read to write for testing the system board's circuits. The ROM cassette software blocks cassette data and generates a cyclic redundancy check (CRC) to check this data. The system board contains the adapter circuits for attaching the serial interface from the keyboard. These circuits generate an interrupt to the processor when a complete scan code is received. The interface can request execution of a diagnostic test in the keyboard. Both the keyboard and cassette interfaces are 5-pin DIN connectors on the system board that extend through the rear panel of the system unit. The system unit has a 2-1/4 inch audio speaker. The speaker's control circuits and driver are on the system board. The speaker connects through a 2-wire interface that attaches to a 3-pin connector on the system board. The speaker drive circuit is capable of approximately 1/2 watt of power. The control circuits allow the speaker to be driven three different ways: 1.) a direct program control register bit may be toggled to generate a pulse train; 2.) the output from Channel 2 of the timer counter may be programmed to generate a waveform to the speaker; 3.) the clock input to the timer counter can be modulated with a program-controlled I/O register bit. All three methods may be performed simultaneously. 1-6 System Unit Number NMI 0 1 2 3 4 5 6 7 Usage Parity Timer Keyboard Reserved Asynchronous Communications (Secondary) SDLC Communications BSC (Secondary) Asynchronous Communications (Primary) SDLC Communications BSC (Primary) Fixed Disk Diskette Printer 8088 Hardware Interrupt Listing System Unit 1-11 Hex Port Number 0060 I N P U T +Keyboard Scan Code 0 1 3 3 4 5 6 7 4 5 6 o 0061 U T P U T PBO 1 2 3 4 5 6 7 0062 I N P U PCO 1 2 3 4 T 5 6 7 0063 -- PAO 1 2 2 ~ I/O Read/Write Memory (SW2-1)]I/O Read/Write Memory (Sw2-2) I/O Read/Write Memory (Sw2-3) I/O Read/Write Memory (Sw2-4) +Cassette Data In +Timer Channel 2 Out +1/0 Channel Check +Read /Write Memory Parity Check Command/Mode Register ] Binary Value X 32K Or Hex 99 17 6 5 4 3 2 11 0 0 1 1 0 0 1 0 1 ~--------------~ 1 1 PA3 Sw1-4 0 0 1 1 PA2 Sw1-3 0 1 0 1 Amount of Memory Located on System Board 16K 32K 48K 64 to 256K PA5 Sw1-6 0 0 1 1 PA4 Sw1-5 0 1 0 1 Display at Power-Up Mode Reserved Color 40 X 25 (BW Mode) Color 80 X 25 (BW Mode) IBM Monochrome (80 X 25) PA7 Swl-8 0 0 1 1 PA6 Swl-7 0 1 0 1 Number of 5-1/4" Drives in System 1 2 3 4 A plus (+) indicates a bit value of 1 performs the specified function. A minus (-) indicates a bit value of 0 performs the specified function. PA Bit = 0 implies switch "ON." PA bit = 1 implies switch "OFF." 8255A I/O Bit Map 1-12 (SW1-1) IPL 5-1/4 Diskette Drive (SW1-2) Reserved System Board Read/Write *(SW1-3) Memory Size System Board Read/Write *(SW1-4) Memory Size Or **(SW1-5) +Display Type 1 **(SW1-6) +Display Type 2 ***(SW1-7) No. of 5-1/4 Drives ***(SW1-8) ~. of 5-1/4 Drives +Timer 2 Gate Speaker +Speaker Data +(Read Read/Write Memory Size) or (Read Spare Key) +Cassette Motor Off -Enable Read/Write Memory -Enable I/O Channel Check -Hold Keyboard Clock Low -(Enable Keyboard) or + (Clear Keyboard and Enable Sense Switches) Mode Register Value Note: r-- System Unit [I/O Read/ Write Memory (Sw2-5) Start Ad dress Decimal Hex 0 16K 32K 48K 00000 04000 08000 OCOOO 64K 80K 96K 112K 10000 14000 18000 lCOOO 128K 144K 160K 176K 20000 24000 28000 2COOO 192K 208K 224K 240K 30000 34000 38000 3COOO 256K 272K 288K 304K 40000 44000 48000 4COOO 320K 336K 352K 368K 50000 54000 58000 5COOO 384K 400K 416K 432K 60000 64000 68000 6COOO 448K 464K 480K 496K 70000 74000 78000 7COOO 512K 528K 544K 560K 80000 84000 88000 8COOO 576K 592K 608K 624K 90000 94000 98000 9COOO Function 16 to 64K Read/Write Memory on System Board Up to 576K Read/Write Memory in I/O Channel System Memory Map for 16/64K System Board (Part 1 of 2) System Unit 1-13 Sta rt Add ress Decimal Hex 640K 656K 672K 688K AOOOO A4000 A800D ACOOO 704K BOOOO 720K B4000 736K B8000 Function 128K Reserved Monochrome Color/Graphics 752K BCOOO 768K 784K COOOO C4000 800K C8ODO 816K CCOOO 832K 848K 864K 880K 00000 04000 08000 OCOOO 896K 912K 928K 944K EOOOO E4000 E8000 ECOOO 960K FOOOO Reserved 976K 992K 100BK F4000 F8000 FCOOO 48K Base System ROM Fixed Disk Control 192K Read Only Memory Expansion and Control System Memory Map for 16/64K System Board (Part 2 of 2) 1-14 System Unit Start Address Decimal Hex 0 16K 32K 48K 00000 04000 08000 OCOOO 64K 80K 96K 112K 10000 14000 18000 lCOOO 128K 144K 160K 176K 20000 24000 28000 2COOO 192K 208K 224K 240K 30000 34000 38000 3COOO 256K 272K 288K 304K 40000 44000 48000 4COOO 320K 336K 352K 368K 50000 54000 58000 5COOO 384K 400K 416K 432K 60000 64000 68000 6COOO 448K 464K 480K 496K 70000 74000 78000 7COOO 512K 528K 544K 560K 80000 84000 88000 8COOO 576K 592K 608K 624K 90000 94000 98000 9COOO Function 64 to 256K Read/Write Memory on System Board Up to 384K Read/Write Memory in I/O Channel Up to 384K in I/O Channel System Memory Map for 64/256K System Board (Part 1 of 2) System Unit 1-15 Start Address Decimal Hex 640K 656K 672K 688K A 0000 A4000 A8oo0 ACooO 704K 80000 720K B4000 736K B8000 752K BCooO 768K 784K COOOO C4000 800K C8000 816K CCOOO 832K 848K 864K 880K 00000 04000 08000 OCOOO 896K 912K 928K 944K EOOOO E4000 E8oo0 ECOoo Function 128K Reserved Monochrome Color/Graphics Fixed Oisk Control 192K Read Only Memory Expansion and Control 960K FooOO Reserved 976K 992K 1oo8K F4000 F8000 FCOOO 48K Base System ROM System Memory Map for 64/256K System Board (Part 2 of 2) System Board Switch Settings All system board switch settings for total system memory, number of diskette drives, and type of display adapter are located in "Appendix G: Switch Settings." 1-16 System Unit I/O Channel The I/O channel is an extension of the 8088 microprocessor bus. It is, however, demultiplexed, repowered, and enhanced by the addition of interrupts and direct memory access (DMA) functions. The I/O channel contains an 8-bit, bidirectional data bus, 20 address lines, 6 levels of interrupt, control lines for memory and I/O read or write, clock and timing lines, 3 channels of DMA control lines, memory refresh timing control lines, a channel-check line, and power and ground for the adapters. Four voltage levels are provided for I/O cards: +5 Vdc, -5 Vdc, +12 Vdc, and -12 Vdc. These functions are provided in a 62-pin connector with 100-mil card tab spacing. A 'ready' line is available on the I/O channel to allow operation with slow I/O or memory devices. If the channel's ready line is not activated by an addressed device, all processor-generated memory read and write cycles take four 210-ns clock or 840-ns/ byte. All processor-generated I/O read and write cycles require five clocks for a cycle time of 1.05 ,us/byte. All DMA transfers require five clocks for a cycle time of 1.05 p,s/byte. Refresh cycles occur once every 72 clocks (approximately 15 ,us) and require four clocks or approximately 7% of the bus bandwidth. I/O devices are addressed using I/O mapped address space. The channel is designed so that 512 I/O device addresses are available to the I/O channel cards. A 'channel check' line exists for reporting error conditions to the processor. Activating this line results in a Non-Maskable Interrupt (NMI) to the 8088 processor. Memory expansion options use this line to report parity errors. The I/O channel is repowered to provide sufficient drive to power all five system unit expansion slots, assuming two low-power Schottky loads per slot. The IBM I/O adapters typically use only one load. The following pages describe the system board's I/O channel. System Unit 1-17 Rear Panel Signal Name .--- GND +RESET DRV +5V +IRQ2 \ -81 A1- r-- - - - - - - -5VDC +DRQ2 -12V ~ - ~ - Reserved t-- +12V ~ GND -MEMW - t-~ t-t-~ t-- -DACK1 +DRQ1 -DACKO I~ I- CLOCK +IRQ7 +IRQ6 +IRQ5 +IRQ4 +IRQ3 - I- +A17 +A16 +A15 +A14 +A13 +A12 +A11 II- - ~ ~ - I- - +5V +OSC +GND I- - ~ - ~ \ 831 +A10 +A9 +A8 +A7 - - I- A31 CH RDY +AEN +A19 +A18 - +ALE System Unit +1/0 - H/C 1-18 +D3 +02 +01 +00 820 A20 ~ -DACK2 I/O Channel Diagram -I/O CH CK +07 +06 +D5 +04 810 A10 -MEMR -lOW -lOR -DACK3 +DRQ3 Signal Name +A6 +A5 +A4 +A3 +A2 +A1 +AO '-- \ Comp onent Side I/O Channel Description The following is a description of the IBM Personal Computer I/O Channel. All lines are TTL-compatible. Signal I/O Description OSC o Oscillator: High-speed clock with a 70-ns period (14.31818 MHz). It has a 50% duty cycle. CLK o System clock: It is a divide-by-three of the oscillator and has a period of 210 ns (4.77 MHz). The clock has a 33% duty cycle. RESETDRV 0 This line is used to reset or initialize system logic upon power-up or during a low line voltage outage. This signal is synchronized to the falling edge of clock and is active high. AO-AI9 o Address bits 0 to 19: These lines are used to address memory and I/O devices within the system. The 20 address lines allow access of up to 1 megabyte of memory. AO is the least significant bit (LSB) and A19 is the most significant bit (MSB). These lines are generated by either the processor or DMA controller. They are active high. DO-D7 I/O Data Bits 0 to 7: These lines provide data bus bits 0 to 7 for the processor, memory, and I/O devices. DO is the least significant bit (LSB) and D7 is the most significant bit (MSB). These lines are active high. System Unit 1-19 Signal I/O Description ALE o Address Latch Enable: This line is provided by the 8288 Bus Controller and is used on the system board to latch valid addresses from the processor. It is available to the I/O channel as an indicator of a valid processor address (when used with AEN). Processor addresses are latched with the failing edge of ALE. I/OCHCK I -I/O Channel Check: This line provides the processor with parity (error) information on memory or devices in the I/O channel. When this signal is active low, a parity error is indicated. I/OCHRDY I I/O Channel Ready: This line, normally high (ready), is pulled low (not ready) by a memory or I/O device to lengthen I/O or memory cycles. It allows slower devices to attach to the I/O channel with a minimum of difficulty. Any slow device using this line should drive it low immediately upon detecting a valid address and a read or write command. This line should never be held low longer than 10 clock cycles. Machine cycles (I/O or memory) are extended by an integral number of CLK cycles (210 ns). IRQ2-IRQ7 I Interrupt Request 2 to 7: These lines are used to signal the processor that an I/O device requires attention. They are prioritized with IRQ2 as the highest priority and IRQ7 as the lowest. An Interrupt Request is generated by raising an IRQ line (low to high) and holding it high until it is acknowledged by the processor (interrupt service routine). 1-20 System Unit Signal I/O Description lOR o -I/O Read Command: This command line instructs an I/O device to drive its data onto the data bus. It may be driven by the processor or the DMA controller. This signal is active low. o -I/O Write Command: This command line instructs an I/O device to read the data on the data bus. It may be driven by the processor or the DMA controller. This signal is active low. MEMR o Memory Read Command: This command line instructs the memory to drive its data onto the data bus. It may be driven by the processor or the DMA controller. This signal is active low. MEMW o Memory Write Command: This command line instructs the memory to store the data present on the data bus. It may be driven by the processor or the D MA controller. This signal is active low. DRQI-DRQ3 I DACKODACK3 o DMA Request 1 to 3: These lines are asynchronous channel requests used by peripheral devices to gain DMA service. They are prioritized with DRQ3 being the lowest and DRQl being the highest. A request is generated by bringing a DRQ line to an active level (high). A DRQ line must be held high until the corresponding DACK line goes active. -DMA Acknowledge 0 to 3: These lines are used to acknowledge DMA requests (DRQI-DRQ3) and to refresh system dynamic memory (DACKO). They are active low. System Unit 1-21 Signal I/O Description AEN o Address Enable: This line is used to de-gate the processor and other devices from the I/O channel to allow DMA transfers to take place. When this line is active (high), the DMA controller has control of the address bus, data bus, read command lines (memory and I/O), and the write command lines (memory and I/O). T/C o Terminal Count: This line provides a pulse when the terminal count for any DMA channel is reached. This signal is active high. The following voltages are available on the system board I/O channel: +5 Vdc +5%, located on 2 connector pins -5 Vdc +10%, located on 1 connector pin +12 Vdc +5%, located on 1 connector pin -12 Vdc + 10%, located on 1 connector pin GND (Ground), located on 3 connector pins 1-22 System Unit Speaker Interface The sound system has a small, permanent-magnet, 2-1/4 inch )peaker. The speaker can be driven from one or both of two )ources: • An 8255A-5 PPI output bit. The address and bit are defined in the "I/O Address Map." • A timer clock channel, the output of which is programmable within the functions of the 8253-5 timer when using a 1.19-MHz clock input. The timer gate also is controlled by an 8255A-5 PPI output-port bit. Address and bit assignment are in the "I/O Address Map." PPI Bit 1.110 Address Hex 0061_ 1.19 MHz Clock In 2 AND Timer Clock Out 2 r- I-- Driver Gate 2 - Low To Pass "Speaker Filter PPI Bit O. I/O Address Hex 0061 Speaker Drive System Block Diagram Channel 2 (Tone generation for speaker) Gate 2 - Controller by 8255A-5 PPI Bit (See I/O Map) Clock In 2 - 1.19318 - MHz ose Clock Out 2 - Used to drive speaker Speaker Tone Generation The speaker connection is a 4-pin Berg connector. See "System Board Component Diagram," earlier in this section, for speaker connection or placement. Pin Function 1 Data Key Ground +5 Volts 2 3 4 Speaker Connector System Unit 1-23 Power Supply The system power supply is located at the right rear of the system unit. It is designed to be an integral part of the system-unit chassis. Its housing provides support for the rear panel, and its fan furnishes cooling for the whole system. It supplies the power and reset signal necessary for the operation of the system board, install able options, and the keyboard. It also provides a switched ac socket for the IBM Monochrome Display and two separate connectors for power to the 5-1/4 inch diskette drives. It is a dc-switching power supply designed for continuous operation at 63.5 watts. It has a fused 120-Vac input and provides four regulated dc output voltages: 7 A of +5 Vdc, 2 A of + 12 Vdc, 0.3 A of -5 Vdc, and 0.25 A of -12 Vdc. These outputs are over-voltage, over-current, open-circuit, and short-circuit protected. If a dc overload or over-voltage condition occurs, all dc outputs are shut down as long as the condition exists. The + 5 Vdc powers the logic on the system board and the diskette drives and allows approximately 4 A of +5 Vdc for the adapters in the system-unit expansion slots. The + 12 Vdc power level is designed to power the system's dynamic memory and the two internal 5-1/4 inch diskette drive motors. It is assumed that only one drive is active at a time. The - 5 Vdc level is designed for dynamic memory bias voltage; it tracks the + 5 Vdc and + 12 Vdc very quickly at power-on and has a longer decay on power-off than the +5 Vdc and + 12 Vdc outputs. The + 12 Vdc and -12 Vdc are used for powering the EIA drivers on the communications adapters. All four power levels are bussed across the five system-unit expansion slots. 1-24 System Unit Operating Characteristics Input Requirements The following are the input requirements for the system unit power supply. Voltage (Vac) Frequency (Hz) Current (Amps) Nominal Minimum Maximum +/·3Hz Maximum 120 104 127 60 2.5 at 104 Vac Vdc Output The following are the dc outputs for the system unit power supply. Voltage (Vdc) Current (Amps) Nominal Minimum +5.0 -5.0 +12.0 -12.0 2.3 0.0 0.4 0.0 Maximum 7.0 0.3 2.0 0.25 Regulation (Tolerance) +% -% 5 10 5 10 4 8 4 9 Vac Output The power supply provides a filtered, ac output that is switched on and off with the main power switch. The maximum current available at this output is 0.75 A. The receptic1e provided at the rear of the power supply for this ac output is· a nonstandard connector designed to be used only for the IBM Monochrome Display. System Unit 1-25 Power Supply Connectors and Pin Assignments The power connector on the system board is a 12-pin male connector that plugs into the power-supply connectors. The pin configurations and locations are shown below: c: c: c: c: c: c: c: c: a:: a:: a:: a:: a:: a:: a:: a::0 (J)Q. Over-Voltage/Over-Current Protection The system power supply employs protection features which are described below. Primary (Input) The following table describes the primary (input voltage) protection for the system-unit power supply. Voltage (Nominal Vac) Type Protection Rating (Amps) 120 Fuse 2 Secondary (Output) On over-voltage, the power supply is designed to shut down all outputs when either the +5 Vdc or the +12 Vdc output exceeds 200% of its maximum rated voltage. On over-current, the supply will turn off if any output exceeds 130% of its nominal value. Power-Good Signal When the power supply is turned on after it has been off for a minimum of 5 seconds, it generates a power-good signal which indicates that there is adequate power for processing. When the four output voltages are above the minimum sense levels, as described below, the signal sequences to a TTL-compatible up level (2.4 Vdc to 5.5 Vdc), which is capable of sourcing 60 /LA. When any of the four output voltages is below its minimum sense level or above its maximum sense level, the power good signal will be a TTL-compatible down level (0.0 Vdc to 0.4 Vdc) capable of sourcing 500 /LA. The power good signal has a turn-on delay of 100 ms after the output voltages. have reached their respective minimum sense levels. System Unit 1-27 Output Voltage Under-Voltage Nominal Sense level +5 Vdc -5 Vdc +12 Vdc -12 Vdc Over-Voltage Nominal Sense level +4.0 Vdc -4.0 Vdc +9.6 Vdc -9.6 Vdc +5.9 Vdc -5.9 Vdc +14.2 Vdc -14.2Vdc Cassette Interface The cassette interface is controlled through software. An output from the 8253 timer controls the data to the cassette recorder through pin 5 of the cassette DIN connector at the rear of the system board. The cassette input data is read by an input port bit of the 8255A-5 programmable peripheral interface (8255A-5 PPI). This data is received through pin 4 of the cassette connector. Software algorithms are used to generate and read cassette data. The cassette drive motor is controlled through pins 1 and 3 of the cassette connector. The drive motor on/off switching is controlled by an 8255A-5 PPI output-port bit (hex 61, bit 3). The 8255A-5 address and bit assignments are defined in "I/O Address Map" earlier in this section. A 2 by 2 Berg pin and a jumper are used on the cassette 'data out' line. The jumper allows use of the 'data out' line as a O.075-Vdc microphone input when placed across the M and C pins of the Berg connector. A O.68-Vdc auxiliary input to the cassette recorder is· available when the jumper is placed across the A and C pins of the Berg connector. The "System Board Component Diagram" shows the location of the cassette Berg pins. M A M A c c c c Microphone Input (0.075 Vdc) 1-28 System Unit Auxiliary Input (0.68 Vdc) Cassette Circuit Block Diagrams Circuit block diagrams for the cassette-interface read hardware, write hardware, and motor control are illustrated below. -5V GND Data From Cassette Recorder Earphone Jack Silicon Diode VIR=.4V Cathode GND Cassette Interface Read Hardware Block Diagram +5V 74lS38 8253 Timer # 2 t O Output OR o 0----------------. 0.678V toAUX Input 0----------------· O.075V to MIC Input GND Cassette Interface Write Hardware Block Diagram System Unit 1-29 +5V I +5V 4.7k Ohm SN75475 Relay N/O +5V- Clamp ~8 OR Motor-[O On 0 ~ In I Coil Cassette Motor Control Coil Com VSS GND Cassette Motor Control Block Diagram 1-30 System Unit S C 1---4 t VCC r-Out Rear Panel 5-Pin DIN Connector Pin Signal 1 Motor Control 2 Ground Electrical Characteristics Common from Relay 3 Motor Control Relay N.O. (6 Vdc at 1A) 4 Data In 500nA at ±13V - at 1,000 - 2,000 Baud 5 Data Out (Microphone or Auxiliary) 250 f.1A at 0.68 Vdc or ** 0.075 Vdc *AII voltages and currents are maximum ratings and should not be exceeded. **Data out can be chosen using a jumper located on the system board. (Auxiliary - 0.68 Vdc or Microphone - 0.075 Vdc). Interchange of these voltages on the cassette recorder could lead to damage of recorder inputs. Cassette Interface Connector Specifications System Unit 1-31 Notes: 1-32 System Unit IBM Personal Computer Math Coprocessor The IBM Personal Computer Math Coprocessor enables the IBM Personal Computer to perform high speed arithmetic, logarithmic functions, and trigonometric operations with extreme accuracy. The coprocessor works in parallel with the processor. The parallel operation decreases operation time by allowing the coprocessor to do mathematical calculations while the processor continues to do other functions. The first five bits of every instruction opcode for the coprocessor are identical (11011 binary). When the processor and the coprocessor see this instruction opcode, the processor calculates the address, of any variables in memory, while the coprocessor checks the instruction. The coprocessor will then take the memory address from the processor if necessary. To access locations in memory, the coprocessor takes the local bus from the processor when the processor finishes its current instruction. When the coprocessor is finished with the memory transfer, it returns the local bus to the processor. The IBM Math Coprocessor works with seven numeric data types divided into the three classes listed below. • Binary integers (3 types) • Decimal integers (1 type) • Real numbers (3 types) Coprocessor 1-33 Programming Interface The coprocessor extends the datatypes, registers, and instructions to the processor. The coprocessor has eight 80-bit registers which provide the equivalent capacity of 40 16-bit registers found in the processor. This register space allows constants and temporary results to be held in regjsters during calculations, thus reducing memory access and improving speed as well as bus availability. The register space can be used as a stack or as a fIxed register set. When used as Ii stack, only the top two stack elements are operated on: when used as a fIxed register set, all registers are operated on. The Figure below shows representations of large and small numbers in each data type. Data Type Bits Word Integer Sh ort Integer Long Integer Packed Decimal Short Real* Long Real* Temporary Real 16 32 64 80 32 64 80 Significant Digits (Decimal) 4 9 18 18 6·7 15-16 19 Approximate Range (decimal) ·32,768o;;;;Xo;;;;+32,767 ·2x10 9 O;;;;Xo;;;;+2x10 9 ·9x10 18 o;;;;Xo;;;;+9x10 18 ·99 ...99O;;;;Xo;;;;+99 ... 99 (18 digits) 8.43x1 0- 37 0;;;; IX 10;;;; 3.37x1 038 4.19x10- 307 o;;;;:X:o;;;;1.67x10 3ffi 3.4x 10- 4932 0;;;; IX: 0;;;; 1.2x 104932 *The short and long real data types correspond to the single and double precision data types Data Types 1-34 Coprocessor Hardware Interface The coprocessor utilizes the same clock generator and system bus interface components as the processor. The coprocessor is wired directly into the processor, as shown in the coprocessor interconnection diagram. The processor's queue status lines (QSO and QS 1) enable the coprocessor to obtain and decode instructions simultaneously with the processor. The coprocessor's busy signal informs the processor that it is executing; the processor's WAIT instruction forces the processor to wait until the coprocessor is finished executing (wait for NOT BUSY). When an incorrect instruction is sent to the coprocessor (for example; divide by zero or load a full register), the coprocessor can signal the processor with an interrupt. There are three conditions that will disable the coprocessor interrupt to the processor: 1. Exception and Interrupt Enable bits of the control word are set to 1'so 2. System board switch block 1 switch 2 set in the On position. 3. NMI Mask REG is set to zero. At power-on time the NMI Mask REG is cleared to disable the NMI. Any software using the coprocessor's interrupt capability must ensure that conditions 2 and 3 are never met during the operation of the software or an "Endless Wait" will occur. An "Endless Wait" will have the processor waiting for the "Not Busy" signal from the coprocessor while the coprocessor is waiting for the processor to interrupt. Because a memory parity error may also cause an interrupt to the 8088 NMI line, the program should check that a parity error did not occur (by reading the 8255 port), then clear exceptions by executing the FNSAVE or the FNCLEX instruction. In most cases, the status word would be looked at, and the exception would be identified and acted upon. Coprocessor 1-35 The NMI Mask REG and the coprocessors interrupt are tied to the NMI line through the NMI interrupt logic. Minor conversions of software designed for use with an 8087 must be made before existing software will be compatible with the IBM Personal Computer Math Coprocessor. Memory and System Board NMI 1--""" NMI NMIINT Logic 8088 Family Bus Interface Components INT 8284 Clock Generator ClKI--+-----'----'~ CLK Math Coprocessor '------lINT RU/GTt Coprocessor Interconnection 1-36 Coprocessor Multimaster System Bus Control Unit The control unit (CU) of the coprocessor and the processor fetch all instructions at the same time, as well as every byte of the instruction stream at the same time. The simultaneous fetching allows the coprocessor to know what the processor is doing at all times. This is necessary to keep a coprocessor instruction from going unnoticed. Coprocessor instructions are mixed with processor instructions in a single data stream. To aid the coprocessor in tracking the processor, nine status lines are interconnected (Q80, Q81, and 80 through 86). I r-....&....--.I I I I I Data"'-+-...-.l~ I I I I I I ! Status Address Addressing & Bus Tracking ! Reg;"" Stack I ~ I r-- ----I L _____ l __________ _ I ~:~:~:::n 0 (D) BO BIts J I Coprocessor Block Diagram Coprocessor 1-37 Register Stack Each of the eight registers in the coprocessor's register stack is 80 bits wide, and each is divided into the "fields" shown in the figure below. The format in the figure below corresponds to the coprocessor's temporary real data type that is used for all calculations. The ST field in the status word identifies the current top-of-stack register. A load ("push") operation decreases ST by 1 and loads a new value into the top register. A store operation stores the value from the current top register and then increases ST by 1. Thus, the coprocessor's register stack grows "down" toward lower-addressed registers. Instructions may address registers either implicitly or explicitly. Instructions that operate at the top of the stack, implicitly address the register pointed to by ST. The instruction, FSQRT, replaces the number at the top with its square root; this instruction takes no operands, because the top-of-stack register is implied as the operand. Other instructions specify the register that is to be used. Explicit register addressing is "top-relative." The expression, ST, denotes the current stack top, and ST(i) refers to the ith register from the ST in the stack. If ST contains "binary all" (register 3 is at the top ofthe stack), the instruction, FADD ST,ST(2), would add registers 3 and 5. Passing subroutine parameters to the register stack eliminates the need for the subroutine to know which registers actually contain the parameters. This allows different routines to call the same subroutine without having to observe a convention for passing parameters in dedicated registers. As long as the stack is not full, each routine simply loads the parameters to the stack and calls the subroutine. 79 o 64 63 I( Exponent Sign Register Structure 1-38 Coprocessor Significand Status Word The status word reflects the overall condition of the coprocessor. It may be stored in memory with a coprocessor instruction then inspected with a processor code. The status word is divided into the fields shown in the figure below. Bit 15 (BUSY) indicates when the coprocessor is executing an instruction (B= 1) or when it is idle (B=O). Several instructions (for example, the comparison instructions) post their results to the condition code (bits 14 and 10 through 8 of the status word). The main use of the condition code is for conditional branching. This may be accomplished by first executing an instruction that sets the condition code, then storing the status word in memory, and then examining the condition code with processor instructions. Bits 13 through 11 of the status word point to the coprocessor register that is the current stack top (ST). Bit 7 is the interrupt request field, and bits 5 through 0 are set to indicate that the numeric execution unit has detected an exception while executing the instruction. 15 7 ST -'-~ 0 [CZICllcoIIR[ IPEluEloEIZEloEllEI IJ~ Exception Flags (1 = Exception Has Occurred) Invalid Operation Denormalized Operand Zerodivide Overflow Underflow Precision (Reserved) Interrupt Request Condition Code Stack Top Pointer (1) Busy (11 ST values: 000 = register 0 is stack top 001 = register 1 is stack top 111 = register 7 is stack top Status Word Format Coprocessor 1-39 Control Word The coprocessor provides several options that, are selected by loading a control word register. o 15 I I -,-- I -~ I -,- ~ Exception Masks (1 = Exception is Masked) Invalid Operation Oenormalized Operand Zerodivide Overflow Underflow Precision (Reserved) Interrupt-Enable Mask (1) Precision Control(2) Rounding Control(3) Infinity Control(4) (Reserved) (1) Interrupt-Enable Mask: 0= Interrupts Enabled 1 = Interrupts Disabled (Masked) (2) Precision Control: 00 = 24 bits 01 = (reserved) 10 = 53 bits 11 = 64 bits (3) Rounding Control: 00 = Round to Nearest or Even 01 = Round Down (toward co) 10 = Round Up (toward co) 11 = Chop (Truncate Toward Zero) (4) Infinity Control: o= Projective 1 = Affine Control Word Format 1-40 Coprocessor Tag Word The tag word marks the content of each register, as shown in the Figure below. The main function of the tag word is to optimize the coprocessor's performance under certain circumstances, and programmers ordinarily need not be concerned with it. Tag values: 00 = Valid (Normal or Unnormal) 01 = Zero (True) 10 = Special (Not-A-Number, 00, or Denormal) 11 = Empty Tag Word Format Exception Pointers The exception pointers in the figure below are provided for user-written exception handlers. When the coprocessor executes an instruction, the control unit saves the instruction address and the instruction opcode in the exception pointer registers. An exception handler subroutine can store these pointers in memory and determine which instruction caused the exception. I I OPERAND ADDRESS(1) I INSTRUCTION OPCODE(2) INSTRUCTION ADDRESS(1) 10 o (1 )20-bit physical address (2) 11 least significant bits of opcode: 5 most significant bits are always COPROCESSOR HOOK (110118) Exception Pointers Format Coprocessor 1-41 Number System The figure below shows the basic coprocessor real number system on a real number line (decimal numbers are shown for clarity, although the coprocessor actually represents numbers in binary). The dots indicate the subset of real numbers the coprocessor can represent as data and final results of calculations. The coprocessor's range is approximately +4.19x 10-307 to + 1.67x 10308 • The coprocessor can represent a great many of, but not all, the real numbers in its range. There is always a "gap" between two adjacent coprocessor numbers, and the result of a calculation may fall within this space. When this occurs, the coprocessor rounds the true result to a number it can represent. The coprocessor actually uses a number system that is a superset of that shown in the figure below. The internal format (called temporary real) extends the coprocessor's range to about +3.4x 10-4932 to + 1.2x 10493 1, and its precision to about 19 (equivalent decimal) digits. This format is designed to provide extra range and precision for constants and intermediate results, and is not normally intended for data or final results. I III I I L' Negative Range (Normalized) -5 -4 -3 -2 -1 , ,I ~ ., , ., .... , ,. -1.67xl0 308 I I .. I -I I I J L~9~ -4.19xl0- 307 I I 0 Positive Range (Normalized) 4 5 , .. , n I 4.19xl0- 307 • I 'II , I J 1.67xl0 308 -2 • tQ • 2.00000000000000000 (Not Representable) 1.99999999999999999 Coprocessor Number System 1-42 Coprocessor Instruction Set On the following pages are descriptions of the operation for the coprocessor's 69 instructions. An instruction has two basic types of operands - sources and destinations. A source operand simply supplies one of the "inputs" to an instruction; it is not altered by the instruction. A destination operand may also provide an input to an instruction. It is distinguished from a source operand, however, because its content can be altered when it receives the result produced by that operation; that is the destination is replaced by the result. The operands of any instructions can be coded in more than one way. For example, FADD (add real) may be written without operands, with only a source, or with a destination and a source operand. The instruction descriptions use the simple convention of separating alternative operand forms with slashes; the slashes, however, are not coded. Consecutive slashes indicate there are no explicit operands. The operands for F ADD are thus described as: source/destination, source This means that F ADD may be written in any of three ways: FADD FADD source F ADD destination,source It is important to bear in mind that memory operands may be coded with any of the processor's memory addressing modes. Coprocessor 1-43 FABS FABS (absolute value) changes the top stack element to its absolute value by making its sign positive. FABS (no operands) Operands (no operands) Exceptions: 1 Execution Clocks Typical Range Transfers 8088 14 10-17 0 Bytes Coding Example 2 FABS FADD Addition F ADD / / source/destination,source F ADDP destination,source FIADD source The addition instructions (add real, add real and pop, integer add) add the source and destination operands and return the sum to the destination. The operand at the stack top may be doubled by coding FADD ST,ST(O). FADD Exceptions: 1,0,0, U, P Operands IIST,ST(i)/ST(i),ST short-real long-real 1-44 Execution Clocks Typical Range Transfers 8088 85 105+EA 110+EA 70-100 90-120+EA 95-125+EA 0 4 8 Coprocessor Bytes 2 2-4 2-4 Coding Example FADD ST,ST(4) FADD AI R_ TEMP [SIl FADD [BX] ,MEAN FADDP Exceptions: I, D, 0, U, P Operands Execution Clocks ST(I),ST Typical Range 8088 90 75-105 0 FIADD Bytes Coding Example 2 FADD ST(2), ST Exceptions: I, D, 0, P Execution Clocks Operands Typical word-integer short-integer Transfers Range 120+EA 102-137+EA 1125+EA 108-143+EA Transfers Bytes Coding Example 8088 2-4 2-4 2 4 FIADD DISTANCE_TRAVELLED FIADD PULSCCOUNT[SI] FBLD FBLD Source FBLD (packed decimal BCD) load» converts the content of the source operand from packed decimal to temporary real and loads (pushes) the result onto the stack. The packed decimal digits of the source are assumed to be in the range X 'O-9R'. FBLD Operands packed-decimal Exceptions: I Execution Clocks Transfers Typical Range 8088 300+EA 290-310+EA 10 Bytes 2-4 Coding Example FBLD YTD_SALES Coprocessor 1-45 FBSTP FBSTP destination FBSTP (packed decimal (BCD) store and pop) performs the inverse of FBLD, where the stack top is stored to the destination in the packed-decimal data type. FBSTP Operands packed-decimal Exceptions: I Execution Clocks Transfers Typical Range 530+EA 520-542+EA Bytes Coding Example 8088 12 2-4 FBSTP [BXl.FORCAST FCHS FCHS (change sign) complements (reverses) the sign of the top stack element. FCHS (no operands) Operands (no operands) Exceptions: I Execution Clocks Transfers Typical Range 8088 15 10-17 0 Bytes Coding Example 2 FCHS FCLEX/FNCLEX FCLEX/FNCLEX (clear exceptions) clears all exception flags, the interrupt request flag, and the busy flag in the status word. FCLEX/FNCLEX (no operands) Operands (no operands) 1-46 Execution Clocks Exceptions: None Transfers Typical Range 8088 5 2-8 0 Coprocessor Bytes Coding Example 2 FNCLEX FCOM FCOM/ /source FCOM (compare real) compares the stack top to the source operand. This results in the setting of the condition code bits. Exceptions: I, 0 FCOM Operands Bytes Range Trans· fers 8088 40·50 63·70+EA 65·75+EA 0 4 8 2 2·4 2·4 Execution Clocks Typical 45 65+EA 70+EA IIST(i) short·real long·real C3 CO Order 0 0 1 1 0 1 0 1 ST >source ST 0<11 ';: ..>:: "' 0 ,- .... u OCll t: '0 t: t: c: t: o 0 .. ,- (.) 't:" CIl ~ ;= >< 0 we.. CIl 0 ,~ (.) u.. .. ~ CIl o ~ ... e.. ........o 'c (S) ~ :::> t: c:t: o 0 'iii (.) t: .. '" CIl 0.;= /~J. ~ \..Y 0 r:-' "tl 3' ~ I/) (") 0 > Vl ~ --.. DO-D7 ,.. Data Buffer !l Data Latch ~ and Disable Circuits ?Z2 I ::l ::l <1> >' EXT DISABLE ~ l 'If, DIR ENABLE ~ T "", D;",••• and Enable I Control --- - Extender Card Block Diagram Expansion Unit 1-87 Receiver Card The receiver card is a four-plane card that fits in expansion slot 8 of the expansion unit. The receiver card redrives the I/O channel to provide sufficient power for additional options and to avoid capacitive effects. Directional control logic is contained on the receiver card to resolve contention and direct data flow on the I/O channel. Steering signals are transmitted back over the expansion cable for use on the extender card. Receiver Card Programming Considerations Several registers associated with the expansion option are programmable and readable for diagnostic purposes. The following figure indicates the locations and functions of the registers on the receiver card. Location Function Memory FXXXX(*) Port 214 Port 214 Port 215 Port 216 (*) Example: Write to memory to latch address bits Write to latch data bus bits (DO - 07) Read data bus bits (DO - 07) Read high-order address bits (AB - A15) Read low-order address bits (AO - A7) Write to memory location F123:4=00 Read Port 215 =12 Read Port 21 6 =34 (All values in hex) The expansion unit is automatically enabled upon power-up. The expansion unit and the system unit will be written to, if the expansion unit is not disabled when writing to FXXXX. However, the system unit and the expansion unit are read back separately. 1-88 Expansion Unit ~~c~o~n~t~ro~I~B~U~S~~Controlbz22~2f~~~~CZ22222Z2Z22222222~~~~ Bus .. t Buffer ~u 00-07 ., I: I: Data Bus Buffer o U I: a:: N Data Latch Circuit Q. ..... ~ NEC Floppy Disk Controller ~ r ~- I" I I f- ,reo Direction Write Enable Head Select V l/"" Index ~ .v"""1.. Write Protect ~'-J iRes~t INTR. .. <}- Step i'" I"""" ~ Read Data !'-- ~ I"""" Digital Control Port Write Data Track 0 Drive A Motor On I-- B I--C --" ~ Decoder l/""'" ~D r-B t--C r-D Drive A Select 1/'" 5-1/4 Inch Diskette Drive Adapter Block Diagram Functional Description From a programming point of view, this attachment consists of an 8-bit digital-output register in parallel with an NEC ,uPD765 or equivalent floppy disk controller (FDC). In the following description, drive numbers 0, 1, 2, and 3 are equivalent to drives A, B, C, and D. Digital-Output Register The digital-output register (DOR) is an output-only register used to control drive motors, drive selection, and feature enable. All bits are cleared by the I/O interface reset line. The bits have the following functions: Bits 0 and 1 These bits are decoded by the hardware to select one drive if its motor is on: Bit 1 0 Drive o o 0 o (A) 1 1 (B) 2 (C) 3 (D) 1 0 1 1 Bit 2 The FDC is held reset when this bit is clear. It must be set by the program to enable the FDC. Bit 3 This bit allows the FDC interrupt and DMA requests to be gated onto the I/O interface. If this bit is cleared, the interrupt and DMA request I/O interface drivers are disabled. Bits 4, 5, 6, and 7 These bits control, respectively, the motors of drives 0, 1, 2 (A, B, C), and 3 (D). If a bit is clear, the associated motor is off, and the drive cannot be selected. Diskette Adapter 1-161 Floppy Disk Controller The floppy disk controller (FDC) contains two registers that may be accessed by the main system processor: a status register and a data register. The 8-bit main status register contains the status information of the FDC and may be accessed at any time. The 8-bit data register (actually consisting of several registers in a stack with only one register presented to the data bus at a time) stores data, commands, parameters, and provides floppy disk drive (FDD) status information. Data bytes are read from or written to the data register in order to program or obtain results after a particular command. The main status register may only be read and is used to facilitate the transfer of data between the processor and FDC. The bits in the main status register (hex 34F) are dermed as follows: Bit Number DBO Description Name Symbol FDD A Busy DAB FDD number 0 is in the Seek mode. DB' FDD B Busy DBB FDD number' is in the Seek mode. DB2 FDD C Busy DCB ~DD DB3 FDD D Busy DDB FDD number 3 is in the Seek mode. DB4 FDC Busy CB A read or write command is in process. DB5 Non-DMA Mode NDM The FDC is in the non-DMA mode. DB6 Data Input! Output DIO Indicates direction of data transfer between FDC and processor. If DID = '" ," then transfer is from FDC data register to the processor. If DID = "0," then transfer is from the processor to FDC data register. DB7 Request for Master ROM Indicates data register is ready to send or receive data to or from the processor. Both bits DID and ROM should be used to perform the handshaking functions of "ready" and "direction" to the processor. 1-162 Diskette Adapter number 2·is in the Seek mode. The FDC is capable of performing 15 different commands. Each command is initiated by a multi-byte transfer from the processor, and the result after execution of the command may also be a multi -byte transfer back to the processor. Because of this multi-byte interchange of information between the FDC and the processor, it is convenient to consider each command as consisting of three phases: Command Phase The FDC receives all information required to perform a particular operation from the processor. Execution Phase The FDC performs the operation it was instructed to do. Result Phase After completion of the operation, status and other housekeeping information is made available to the processor. Diskette Adapter 1-163 Programming Considerations The following tables define the symbols used in the command summary, which follows. Symbol Name Description a AO controls selection of main status register (AO = a) or data register (AO = 1). AO Address Line C Cylinder Number C stands for the current/selected cylinder (track) number of the medium. D Data D stands for the data pattern that is going to be written into a sector. D7-00 Data Bus 8-bit data bus, where D7 sta nds for a most significant bit, and DO stands for a least significant bit. DTL Data Length When N is defined as 00, DTL stands for the data length that users are going to read from or write to the sector. EOT End of Track EOT stands for the final sector numbe'r on a cylinder. GPL Gap Length G PL sta nds for the length of gap 3 (spacing between sectors excluding VCO sync field). H Head Address H stands for head number specified in ID field. HD Head HD stands for a selected head number or 1. (H = HD in all command words.) HLT Head Load Time HLT stands for the head load time in the FDD (4 to 512 ms in 4-ms increments). HUT Head Unload Time HUT stands for the head unload time after a read or write operation has occurred (0 to 480 ms in 32-ms increments). MF FM or MFM Mode If MF is low, FM mode is selected; if it is high, MFM mode is selected only if MFM is implemented. MT Multi-Track If MT is high, a multi-track operation is to be performed. (A cylinder under both HDO and HD1 will be read or written.) N Number N stands for the number of data bytes written in a sector. Symbol Descriptions (Part 1 of 2) 1-164 Diskette Adapter a or 1, as a Symbol Name Description NCN New Cylinder Number NCN stands for a new cylinder number, which is going to be reached as a result of the seek operation. (Desired position of the head.) NO Non-DMA Mode NO stands for operation in the non-DMA mode. PCN Present Cylinder Number PCN stands for cylinder number at the completion of sense-interrupt-status command indicating the position of the head at present time. R Record R stands for the sector number, which will be read or written. R/W Read/Write R/W stands for either read (R) or write (W) signal. SC Sector SC indicates the number of sectors per cylinder. SK Skip SK stands for skip deleted-data address mark. SRT Step Rate Time SRT stands for the stepping rate for the FDD (2 to 32 ms in 2-ms increments). STO ST 1 ST 2 ST 3 Status Status Status Status ST 0-3 stand for one of four registers that store the status information after a command has been executed. This information is available during the result phase after command execution. These registers should not be confused with the main status register (selected by AO =0). ST 0-3 may be read only after a command has been executed and contain information releva nt to that particula r command. STP Scan Test During a scan operation, if STP =1, the data in contiguous sectors is compared byte-by-byte with data sent from the processor (or DMA), and if STP =2, then alternate sectors are read and compared. usa, Unit Select US stands for a selected drive number encoded the same as bits 0 and 1 of the digital output register (DOR). 0 1 2 3 US1 Symbol Descriptions (Part 2 of 2) Diskette Adapter 1-165 Command Summary In the following table, 0 indicates "logical 0" for that bit, 1 means "logical 1," and X means "don't care." Data Bus R/W D7 D6 D5 D4 D3 D2 D1 Phase DO Remarks Read Data Command W W w MT MF SK X X X 0 X 0 X 1 1 HD US1 0 Sector ID information prior to command execution. C H R N EOT GPL DTL W W W W W W Execution Result R R R R R R R Command W W w W W W W W W Execution Result 1-166 Data tra nsfer between the FDD and main system. Status information after command execution. Sector I D information after command execution. STO ST 1 ST 2 C H R N Read Deleted Data MT MF SK 0 1 1 0 X X X X HD US1 X C H R N EOT GPL DTL R R R R R R R Diskette Adapter STO ST 1 ST 2 C H R N Command Codes usa 0 Command Codes usa Sector ID information prior to command execution. Data tra nsfer between the FDD and main system. Status information after command execution. Sector ID information after command execution. Phase Data Bus R/W D7 D6 D5 D4 D3 D2 D1 DO Remarks Write Data Command W W MT MF X X w a a a X X X a 1 1 HD US1 usa C H R N EOT GPL DTL W W W W W W Sector I D information to command execution. Execution Result R R R R R R R Command W W w W W W W W W Write Deleted Data 1 1 X X X HD US1 usa C H R N EOT GPL DTL a a Execution Result R R R R R R R Data tra nsfer between the main system and FDD. Status information after command execution. Sector ID information after command execution. STa ST 1 ST 2 C H R N MT MF X X STa ST 1 ST 2 C H R N Command Codes a a Command Codes Sector ID information prior to command execution. Data tra nsfer between FDD and main system. Status ID information after command execution. Sector ID information after command execution. Diskette Adapter 1-167 Data Bus R/W 07 06 05 04 03 02 01 Phase Command W W W W W W W W W a X DO Read a Track MF SK 1 X X X X HD US1 usa C H R N EOT GPL DTL a a a a Execution Result R R R R R R R Command W W X MF X Read 10 1 1 X X HD US1 usa a a X Execution Result 1-168 R R R R R R R Diskette Adapter STa ST 1 ST 2 C H R N Command Codes Sector ID information prior to command execution. Data tra nsfer between the FDD and main system. FDC reads all of cylinder's contents from index hole to EOT. Status information after command execution. Sector I D information after command execution. STa ST 1 ST 2 C H R N a Remarks a a Command Codes The first correct ID information on the cylinder is stored in data register. Status information after command execution. Sector ID information during execution phase. Oata Bus Phase Command R/W 07 06 05 04 03 02 01 W W 0 X MF X w W W W Format a Track 1 1 0 0 0 X X X HD US1 N SC GPL D DO 0 R R R R R R R Command W W Bytes/Sector Sector /Track Gap 3 filler byte. FDC formats an entire cylinder. Status information after command execution. In this case, the ID information has no meaning. w W W W W W W STO ST 1 ST 2 C H R N Scan Equal 1 0 0 0 X X X HD US1 C H R N EOT GPL STP MT MF SK X X Execution Result R R R R R R R STO ST 1 ST 2 C H R N Command Codes usa Execution Result Remarks Command Codes usa Sector ID information prior to command execution. Data compared between the FDD and the main system. Status information after command execution. Sector ID information after Command execution. Diskette Adapter 1-169 Data Bus R/W 07 06 05 04 03 02 01 Phase Command W W w W W W W W W , , Scan Low or Equal MT MF SK 0 0 X X X X X HD US, C H R N EOT GPL STP DO , R R R R R R R Command W W Sector ID information prior to command execution. w W W W W W W STO X X , , , Scan High or Equal SK 0 X X X HD US, C H R N EOT GPL STP Execution Result 1-170 Data compared between the FDD and main system. Status information after command execution. Sector ID information after command execution. ST' ST 2 C H R N MT MF R R R R R R R Diskette Adapter STO ST' ST 2 C H R N Command Codes usa Execution Result Remarks , Command Codes usa Sector ID information prior to command execution. Data compared between the FDD and main system. Status information after command execution. Sector ID information after command execution. Data Bus Phase Command R/W 07 06 05 04 03 02 01 W W 0 0 X X Recalibrate 1 0 0 0 X X 0 X 1 USl DO 1 Remarks Command Codes usa Execution No Result Phase Head retracted to track 0 Sense Interrupt Status 1 0 0 0 0 STO PCN Command Result W Command W W W 0 0 0 -SRT ---HLT W W 0 0 X X 0 0 R R Specify 0 0 0 0 1 1 HUTND Command Codes Status information at the end of seek operation about the FOC Command Codes No Result Phase Command Result R Command W W w Sense Drive Status 1 0 0 0 0 X X X HD USl ST 3 0 0 0 Seek 1 0 X X X X X 1 1 HD USl 0 Command Codes usa Status information about FDD. 1 Command Codes usa NCN Execution Head is positioned over proper cylinder on diskette. No Result Phase Command W Invalid Invalid Codes Result R STO Invalid command codes (NoOp - FDC goes into standy state). ST 0 = 80. Diskette Adapter 1-171 No. Bit Name Symbol 07 Description 07=Oand06=O Normal termination of command (NT). Command was completed and properly executed. 07 =Oand 06 = 1 Abnormal termination of command (AT). Execution of command was started. but was not successfully completed. 07 = 1 and 06 = 0 Invalid command issue (IC). Command that was issued was never started. 07 = 1 and 06 = 1 Abnormal termination because. during command execution. the ready signal from FOO changed state. Interrupt Code IC 05 Seek End SE When the FOC completes the seek command. this flag is set to 1 (high), 04 Equipment Check EC If a fault signal is received from the FOO. or if the track 0 signal fails to occur after 77 step pulses (recalibrate command). then this flag is set. 03 Not Ready NR When the FOO is in the not-ready state and a read or write command is issued. this flag is set. If a read or write command is issued to side 1 of a single-sided drive. then this flag is set. 02 Head Address HO This flag is used to indicate the state of the head at interrupt. 01 00 Unit Select 1 Unit Select 0 US 1 US 0 These flags are used to indicate a drive unit number at interrupt. 06 Command Status Register 0 1-172 Diskette Adapter Bit No. D7 Name Symbol End of Cylinder Description EN When the FDC tries to access a sector beyond the final sector of a cylinder, this flag is set. D6 - D5 Data Error DE When the FDC detects a CRC error in either the ID field or the data field, this flag is set. D4 Over Run OR If the FDC is not serviced by the main system during data transfers within a certain time interval, this flag is set. D3 - D2 No Data ND During execution of a read data, write deleted data, or scan command, if the FDC cannot find the sector specified in the ID register, this flag is set. During execution of the read ID command, if the FDC cannot read the ID field without an error, then this flag is set. During the execution of the read a cylinder command, if the starting sector cannot be found, then this flag is set. D1 Not Writable NW During execution of a write data, write deleted data, or format-a-cylinder command, if the FDC detects a write-protect signal from the FDD, then this flag is set. DO Missing Address Mark MA If the FDC cannot detect the ID address mark, this flag is set. Also, at the same time, the MD (missing address mark in the data field) of status register 2 is set. - Not used. This bit is always 0 (low). Not used. This bit is always 0 (low). - Command Status Register 1 Diskette Adapter 1-173 Bit Name No. Symbol Description D7 - - Not used. This bit is always 0 (low). D6 Control Mark CM During execution of the read data or scan command, if the FDC encounters a sector that contains a deleted data address mark, this flag is set. D5 Data Error in Data Field DD If the FDC detects a CRC error in the data, then this flag is set. D4 Wrong Cylinder WC This bit is related to the ND bit, and when the contents of C on the medium are different from that stored in the ID register, this flag is set. D3 Scan Equal Hit SH During execution of the scan command, if the condition of "equal" is satisfied, this flag is set. D2 Scan Not Satisfied SN During execution of the scan command, if the FDC cannot find a sector on the cylinder that meets the condition, then this flag is set. D1 Bad Cylinder BC This bit is related to the ND bit, and when the contents of C on the medium are different from that stored in the ID register, and the contents of C is FF, then this flag is set. DO Missing Address Mark in Data Field MD When data is read from the medium, if the FDC cannot find a data address mark or deleted data address mark, then this flag is set. Command 1-174 Status Register 2 Diskette Adapter Bit Name No. Description Symbol D7 Fault FT This bit is the status of the fault signal from the FDD. D6 Write Protected WP This bit is the status of the write-protected signal from the FDD. D5 Ready RY This bit is the status of the ready signal from the FDD. D4 Track 0 TO This bit is the status of the track 0 signal from the FDD. D3 Two Side TS Th is bit is the status of the two-side signal from the FDD. D2 Head Address HD This bit is the status of the side-select signal from the FDD. D1 Unit Select 1 US 1 This bit is the status of the unit-select-1 signal from the FDD. DO Unit Select 0 US 0 This bit is the status of the unit-select-O signal from the FDD. Command Status Register 3 Programming Summary FDC Data Register 1/0 Address Hex 3F5 FDC Main Status Register 1/0 Address Hex 3F4 Digital Output Register 1/0 Address Hex 3F2 Bit 0 1 2 3 4 5 6 7 Drive 00: DR #A 10: DR #C Select 01: DR #B 11: DR #D Not FDC Reset Enable INT & DMA Requests Drive A Motor Enable Drive B Motor Enable Drive C Motor Enable Drive D Motor Enable All bits cleared with channel reset. OPC Registers Diskette Adapter 1-175 FDC Constants (in hex) N: SC: HUT: SRT: 02 08 F C GPL Format: 05 GPLR!W: 2A HLT: 01 (6 ms track-to-track) Drive Constants Head Load Head Settle Motor Start 35 ms 15 ms 250ms Comments • Head loads with drive select, wait HD load before R/W. • Following access, wait HD settle time before R/W. • Drive motors should be off when not in use. Only A or Band C or D may run simultaneously. Wait motor start time before R/W. • Motor must be on for drive to be selected. • Data errors can occur while using a home television as the system display. Locating the TV too close to the diskette area can cause this to occur. To correct the problem, move the TV away from, or to the opposite side of the system unit. System I/O Channel Interface All signals are TTL-compatible: Most Positive Up Level Least Positive Up Level Most Positive Down Level Least Positive Down Level 1-176 Diskette Adapter 5.5 2.7 0.5 -0.5 Vdc Vdc Vdc Vdc The following lines are used by this adapter. + DO-7 (Bidirectional, load: 1 74LS, driver: 74LS 3-state). These eight lines form a bus by which all commands, status, and data are transferred. Bit 0 is the low-order bit. +AO-9 (Adapter input, load: 1 74LS) These ten lines form an address bus by which a register is selected to receive or supply the byte transferred through lines DO-7. Bit 0 is the low-order bit. +AEN (Adapter input, load: 1 74LS) The content of lines AO-9 is ignored if this line is active. -lOW (Adapter input, load: 1 74LS) The content of lines DO-7 is stored in the register addressed by lines AO-9 or DACK2 at the trailing edge of this signal. -lOR (Adapter input, load: 1 74LS) The content of the register addressed by lines AO-9 or DACK2 is gated onto lines DO-7 when this line is active. -DACK2 (Adapter input, load: 2 74LS) This line being active degates output DRQ2, selects the FDC data register as the source/destination of bus DO-7, and indirectly gates T/C to IRQ6. +T/C (Adapter input, load: 4 74LS) This line and DACK2 being active indicates that the byte of data for which the DMA count was initialized is now being transferred. +RESET (Adapter input, load: 1 74LS) An up level aborts any operation in process and clears the digital output register (DaR). Diskette Adapter 1-177 +DRQ2 (Adapter output, driver: 74LS 3-state) This line is made active when the attachment is ready to transfer a byte of data to or from main storage. The line is made inactive by DACK2 becoming active or an I/O read ofthe FDC data register. +IRQ6 (Adapter output, driver: 74LS 3-state) This line is made active when the FDC has completed an operation. It results in an interrupt to a routine which should examine the FDC result bytes to reset the line and determine the ending condition. Drive A and B Interface All signals are TTL-compatible: Most Positive Up Level Least Positive Up Level Most Positive Down Level Least Positive Down Level 5.5 Vdc 2.4 Vdc 0.4 Vdc -0.5 Vdc All adapter outputs are driven by open-collector gates. The drive(s) must provide termination networks to Vcc (except motor enable, which has a 2000-ohm resistor to Vcc). Each adapter input is terminated with a I50-ohm resistor to Vcc. Adapter Outputs -Drive Select A and B 1-178 Diskette Adapter (Driver: 7438) These two lines are used by drives A and B to degate all drivers to the adapter and receivers from the attachment (except motor enable) when the line associated with a drive is inactive. -Motor Enable A and B (Driver: 7438) The drive associated with each of these lines must control its spindle motor such that it starts when the line becomes active and stops when the line becomes inactive. -Step (Driver: 7438) The selected drive moves the read/write head one cylinder in or out per the direction line for each pulse present on this line. -Direction (Driver: 7438) For each recognized pulse of the step line, the read/write head moves one cylinder toward the spindle if this line is active, and away from the spindle if inactive. -Head Select (Driver: 7438) Head 1 (upper head) will be selected when this line is active (low). -Write Data (Driver: 7438) For each inactive to active transition of this line while write enable is active, the selected drive causes a flux change to be stored on the diskette. -Write Enable (Driver: 7438) The drive disables write current in the head unless this line is active. Adapter Inputs -Index The selected drive supplies one pulse per diskette revolution on this line. - Write Protect The selected drive makes this line active if a write-protected diskette is mounted in the drive. Diskette Adapter 1-179 -Track 0 The selected drive makes this line active if the read/write head is over track O. -Read Data The selected drive supplies a pulse on this line for each flux change encountered on the diskette. 1-180 Diskette Adapter 34-Pin Keyed Edge Connector Component Side Note: Lands 1-33 (odd numbers) are on the back of the board. Lands 2-34 (even numbers) are on the front, or component side. At Standard TTL Levels 1-33 Unused 2,4,6 Index Motor Enable A Diskette Drives Land Number Ground-Odd Numbers 8 10 Drive Select B 12 Drive Select A 14 Motor Enable B 16 Direction (Stepper Motor) 18 Step Pulse 20 Write Data 22 Write Enable 24 Track 0 26 Write Protect 28 Read Data 30 Select Head 1 32 Unused 34 Drive Adapte Connector Specifications (Part 1 of 2) Diskette Adapter 1-181 37-Pin D-Shell • • •• • 20 • •• • •• • • •• •• • • • • • • • • • • o Pin At Standard TTL Levels Number Unused 1-5 Index 6 Motor Enable C 7 Drive Select D 8 Drive Select C 9 Motor Enable D External Drives 10 Direction (Stepper Motor) 11 Step Pulse 12 Write Data 13 Write Enable 14 Track 0 15 Write Protect 16 Read Data 17 Select Head 1 18 Ground 20-37 Connector Specifications (Part 2 of 2) 1-182 Diskette Adapter Drive Adapter 37 IBM 5-1/4" Diskette Drive The system unit has space and power for one or two 5-1/4 inch diskette drives. A drive can be single-sided or double-sided with 40 tracks for each side, is fully self-contained, and consists of a spindle drive system, a read positioning system, and a read/write/erase system. The diskette drive uses modified frequency modulation (MFM) to read and write digital data, with a track-to-track access time of 6 milliseconds. To load a diskette, the operator raises the latch at the front of the diskette drive and inserts the diskette into the slot. Plastic guides in the slot ensure the diskette is in the correct position. Closing the latch centers the diskette and clamps it to the drive hub. After 250 milliseconds, the servo-controlled dc drive motor starts and drives the hub at a constant speed of 300 rpm. The head positioning system, which consists of a 4-phase stepper-motor and band assembly with its associated electronics, moves the magnetic head so it comes in contact with the desired track of the diskette. The stepper-motor and band assembly uses one-step rotation to cause a one-track linear movement of the magnetic head. No operator intervention is required during normal operation. During a write operation, a 0.013-inch (0.33 millimeter) data track is recorded, then tunnel-erased to 0.012 inch (0.030 millimeter). If the diskette is write-protected, a write-protect sensor disables the drive's circuitry, and an appropriate signal is sent to the interface. Data is read from the diskette by the data-recovery circuitry, which consists of a low-level read amplifier, differentiator, zero-crossing detector, and digitizing circuits. All data decoding is done by an adapter card. The diskette drive also has the following sensor systems: 1. The track 00 switch, which senses when the head/carriage assembly is at track 00. Diskette Drive 1-183 2. The ind~x sensor, which consists of an LED light source and phototransistor. This sensor is positioned so that when an index hole is detected, a digital signal is generated. 3. The write-protect sensor disables the diskette drive's electronics whenever a write-protect tab is applied to the diskette. For interface information, refer to "IBM 5-1/4" Diskette Drive Adapter" earlier in this section. Media Industry-compatible 5-1/4 inch diskette Tracks per inch 48 Number of tracks 40 Dimensions Height Width Depth Weight 3.38 inches (85.85 mm) 5.87 inches (149.10 mm) 8.00 inches (203.2 mm) 4.50 pounds (2.04 kg) Temperature (Exclusive of media) Operating Non operating 50 0 F to 11 2 0 F (1 0 0 C to 44 0 C) -40 0 F to 140 0 F (-40 0 C to 60 0 C) Relative humidity (Exclusive of media) Operating Non operating 20% to 80% (non condensing) 5% to 95% (non condensing) Seek Time 6 ms track-to-track Head Settling Time 15 ms (last track addressed) Error Rate 1 per 109 (recoverable) 1 per 1012 (non recoverable) 1 per 106 (seeks) Head Life 20,000 hours (normal use) Media Life 3.0 x 106 passes per track Disk Speed 300 rpm +/- 1.5% (long term) Instantaneous Speed Variation +/- 3.0% Start/Stop Time 250 ms (maximum) Transfer Rate 250K bits/sec Recording Mode MFM Power +12 Vdc +/- 0.6 V, 900 mA average +5 Vdc +/- 0.25 V, 600 mA average Mechanical and Electrical Specifications 1-184 Diskette Drive Diskettes The IBM 5-1/4" Diskette Drive uses a standard 5.25-inch ( 133 .4-millimeter) diskette. For programming considerations, single-sided, double-density, soft-sectored diskettes are used for single-sided drives. Double-sided drives use double-sided, double-density, soft-sectored diskettes. The figure below is a simplified drawing of the diskette used with the diskette drive. This recording medium is a flexible magnetic disk enclosed in a protective jacket. The protected disk, free to rotate within the jacket, is continuously cleaned by the soft fabric lining of the jacket during normal operation. Read/write/erase head access is made through an opening in the jacket. Openings for the drive hub and diskette index hole are also provided. __ I 0.140 Inch -I L 0.25 ± 0.01 Inch (~.56 mm) ~llf6.30 ± 0.25 mm) I J----c I I Sealed Protective Jacket ....... @ m , "- .r: E ---(0, I Oxide Coated Mylar Disk \ \ gE : : It) I 5.25 Inch 66 1(133.4mm) +1 +1 o ~ Liner / COlO / I ·co C'l- ~ '---5.25Inch-l 1~(133.4m~ I Head Aperture Recording Medium Diskettes 1-185 Notes: 1-186 Diskettes IBM Fixed Disk Drive Adapter The fixed disk drive adapter attaches to one or two fixed disk drive units, through an internal daisy-chained flat cable (data/control cable). Each system supports a maximum of one fixed disk drive adapter and two fixed disk drives. The adapter is buffered on the I/O bus and uses the system board direct memory access (DMA) for record data transfers. An interrupt level also is used to indicate operation completion and status conditions that require processor attention. The fixed disk drive adapter provides automatic II-bit burst error detection and correction in the form of 32-bit error checking and correction (ECC). The device level control for the fixed disk drive adapter is contained on a ROM module on the adapter. A listing of this device level control can be found in "Appendix A: ROM BIOS Listings. " WARNING: The last cylinder on the fixed disk drive is reserved for diagnostic use. Diagnostic write tests will destroy any data on this cylinder. Fixed Disk Controller The disk controller has two registers that may be accessed by the main system processor: a status register and a data register. The 8-bit status register contains the status information of the disk controller, and can be accessed at any time. The 8-bit data register (actually consisting of several registers in a stack with only one register presented to the data bus) stores data, commands, parameters, and provides the disk controller's status information. Data bytes are read from, or written to the data register in order to program or obtain the results after a particular command. The status register is a read-only register, and is used to help the transfer of data between the processor and the disk controller. The controller-select pulse is generated by writing to port address hex 322. Fixed Disk Adapter 1-187 -, 00 00 "!1 ~. ('I> 0. o Serializer I Deserializer iii· ~ J2 > 0. ~ .... Serdes ECC ('I> "" Data Separator 1/0 Edge Connector Data Bus DB7-DBO' Control r-- Sector Buffer 8-Bit Processor Fixed Disk Drive Adapter Block Diagram To ) Drives Programming Considerations Status Register At the end of all commands from the system board, the disk controller returns a completion status byte back to the system board. This byte informs the system unit if an error occurred during the execution of the command. The following shows the format of this byte. 6 5 4 3 2 o d o o o ~I e Bits 0, 1,2,3,4,6, 7 These bits are set to zero. Bit 1 When set, this bit shows an error has occurred during command execution. Bit 5 This bit shows the logical unit number of the drive. If the interrupts are enabled, the controller sends an interrupt when it is ready to transfer the status byte. Busy from the disk controller is unasserted when the byte is transferred to complete the command. Sense Bytes If the status register receives an error (bit 1 is set), then the disk controller requests four bytes of sense data. The format for the four bytes is as follows: Bits 7 I 5 6 Byte 0 Address Valid Byte 1 0 Byte 2 Cylinder High Byte 3 0 I 0 4 Error Type d 2 3 1 0 Error Code I Head Number Sector Number Cylinder Low Remarks d = drive Fixed Disk Adapter 1-189 Byte 0 Bits 0, 1,2,3 Error code. Byte 0 Bits 4,5 Error type. Byte 0 Bit 6 Set to 0 (spare). Byte 0 Bit 7 The address valid bit. Set only when the previous command required a disk address, in which case it is returned as a 1; otherwise, it is a O. The following disk controller tables list the error types and error codes found in byte 0: Bits 1-190 Error Type Error Code 5 4 3 2 1 0 0 0 0 0 0 0 The controller did not detect any error during the execution of the previous operation. 0 0 0 0 0 1 The controller did not detect an index signal from the drive. 0 0 0 0 1 0 The controller did not get a seek-complete signal from the drive after a seek operation (for all non-buffered step seeks). 0 0 0 0 1 1 The controller detected a write fault from the drive during the last operation. 0 0 0 1 0 0 After the controller selected the drive, the drive did not respond with a ready signal. 0 0 0 1 0 1 Not used. 0 0 0 1 1 0 After stepping the maximum number of cylinders, the controller did not receive the track 00 signal from the drive. 0 0 0 1 1 1 Not used. 0 0 1 0 0 0 Fixed Disk Adapter Description The drive is still seeking. This status is reported by the Test Drive Ready command for an overlap seek condition when the drive has not completed the seek. No time-out is measured by the controller for the seek to complete. Error Type Error Code Bits 5 4 3 2 1 0 0 1 0 0 0 0 ID Read Error: The controller detected an ECC error in the target ID field on the disk. 0 1 0 0 0 1 Data Error: The controller detected an uncorrectable ECC error in the target sector during a read operation. 0 1 0 0 1 0 Address Mark: The controller did not detect the target address mark (AM) on the disk. 0 1 0 0 1 1 0 1 0 1 0 0 Sector Not Found: The controller found the correct cylinder and head, but not the target sector. 0 1 0 1 0 1 Seek Error: The cylinder or head address (either or both) did not compare with the expected target address as a result of a seek. 0 1 0 1 1 0 Not used. 0 1 0 1 1 1 0 1 1 0 0 0 Correctable Data Error: The controller detected a correctable ECC error in the target field. 0 1 1 0 0 Bad Track: The controller detected a bad track flag during the last operation. No retries are attempted on this error. 1 Description Not used. Not used. Fixed Disk Adapter 1-191 Bits Bits Error Type Error Code 5 4 3 2 1 0 1 0 0 0 0 0 Invalid Command: The controller has received an invalid command from the system unit. 1 0 0 0 0 Illegal Disk Address: The controller detected an address that is beyond the maximum range. 1 Description Error Type Error Code 5 4 3 2 1 0 Description 1 1 0 0 0 0 RAM Error: The controller detected a data error during the RAM sector-buffer diagnostic test. 1 1 0 0 0 1 Program Memory Checksum Error: During this internal diagnostic test, the controller detected a program-memory checksum error. 1 1 0 0 1 0 ECC Polynominal Error: During the controller's internal diagnostic tests, the hardware ECC generator failed its test. 1-192 Fixed Disk Adapter Data Register The processor specifies the operation by sending the 6-byte device control block (DeB) to the controller. The figure below shows the composition of the DeB, and defines the bytes that make up the DeB. Bit 7 Byte 0 Byte 1 Byte 2 6 5 4 2 3 Command Class 0 0 Opcode d 0 Cylinder High 1 I Head Number Sector Number Byte 3 Cylinder Low Byte 4 Interleave or Block Count Byte 5 Control Field Byte 0 - Bits 7, 6, and 5 identify the class of the command. Bits 4 through 0 contain the Opcode command. Byte 1 - Bit 5 identifies the drive number. Bits 4 through 0 contain the disk head number to be selected. Bits 6 and 7 are not used. Byte 2 - Bits 6 and 7 contain the two most significant bits of the cylinder number. Bits 0 through 5 contain the sector number. Byte 3 - Bits 0 through 7 are the eight least significant bits of the cylinder number. Byte 4 - Bits 0 through 7 specify the interleave or block count. Byte 5 - Bits 0 through 7 contain the control field. Fixed Disk Adapter 1-193 Control Byte Byte 5 is the control field of the DCB and allows the user to select options for several types of disk drives. The format of this byte is as follows: Bits I I 7 6 5 4 3 2 a 0 0 0 s 0 s s Remarks r = retries s = step option a = retry option on data ECC error Bit 7 Disables the four retries by the controller on all disk-access commands. Set this bit only during the evaluation of the performance of a disk drive. Bit 6 If set to 0 during read commands, a reread is attempted when an ECC error occurs. If no error occurs during reread, the command will complete with no error status. If this bit is set to 1, no reread is attempted. Bits 5,4,3 Set to O. Bits 2, 1, 0 These bits define the type of drive and select the step option. See the following figure. Bits 2. 1. 0 0 0 0 This drive is not specified and defaults to 3 milliseconds per step, 0 0 1 0 1 0 0 1 1 N/A N/A N/A 1 0 0 200 microseconds per step, 1 0 1 1 1 0 1 1 1-194 1 70 microseconds per step (specified by BIOS), 3 milliseconds per step, 3 milliseconds per step, Fixed Disk Adapter Command Summary Command Data Control Block Remarks = drive (0 or 1) = don't care Bytes 2, 3, 4, 5 = don't Test Drive Bit 7 6 5 4 3 2 1 0 d Ready Byte 0 0 0 010 0 0 0 0 x (Class 0, Byte 1 0 0 dlx x x x x Opcode 00) care Recalibrate Bit 7 6 5 4 (Class 0, Byte 0 0 Opcode 01) Byte 1 0 0 dlx Byte 5 r 0 0 0 = drive (0 or 1) = don't care r = retries s = Step Option Bytes 2, 3, 4 = don't 3 2 1 0 d 010 0 0 0 1 x x x x x 0 s s s 0 care ch = cylinder high Reserved This Opcode is not (Class 0, used. Opcode 02) = drive (0 or 1 ) = don't care Bytes 2, 3, 4, 5 = don't Request Sense Bit 7 6 5 4 3 2 1 0 d Status Byte 0 0 0 010 0 0 1 1 x (Class 0, Byte 1 0 0 dlx x x x x Opcode 03) care Format Drive Bit 7 6 5 4 3 2 (Class 0, Byte 0 0 0 1 0 Opcode 04) Byte 1 0 0 Byte 2 010 0 d Byte 3 0 0 0 0 = drive (0 or 1 ) = retries s = step option ch = cylinder high d r Cylinder Low Byte 4 0 0 Byte 5 r 0 01 Interleave 0 0 0 s s s Ready Verify Bit 7 6 5 4 (Class 0, Byte 1 0 0 Byte 1 0 0 Opcode 05) 0 I Head Number 1·0 0 ch 1 0 Byte 2 ch 3 010 0 d I 1 0 2 1 0 1 I Head Number Sector Number Interleave: 1 to 16 for 512-byte sectors. = drive (0 or 1) = retries s = step option a = retry option on d r Byte 3 Cylinder Low data ECC Byte 4 Block Count ch Byte 5 r a 0 0 0 s s = cylinder high s Fixed Disk Adapter 1-195 Command Data Control Block Remarks Format Track Bit 7 6 5 (Class 0, Byte 0 0 0 Opcode 06) Byte 1 0 0 010 0 1 1 0 d Head Number Byte 2 4 2 1 0 I 10 0 ch Byte 3 3 0 0 0 0 Byte 4 0 0 Byte 5 r 0 Interleave 01 0 0 0 s s s Format Bad Bit 7 6 5 3 2 1 0 Byte 0 0 0 010 0 1 1 (Class 0, Byte 1 0 0 d Byte 2 4 Byte 4 0 0 01 Byte 5 r 0 0 ch =cylinder high 0 s 2 Read Bit 7 6 5 4 3 Byte 0 0 0 010 1 0 Opcode 08) Byte 1 0 0 d I ch Byte 3 for 51 2-byte sectors Interleave: 1 to 16 1 0 0 I Head Number Sector Number 0 a 0 0 s r = retries s = step option s d = drive (0 or 1 ) r = retries a = retry option on data ECC error Cylinder Low r d = drive (0 or 1 ) ch = cylinder high s 0 Interleave: 1 to 16 for 512-byte sectors 0 Interleave 0 (Class 0, Byte 2 1 I Head Number ch 10 0 0 0 0 Cylinder Low Byte 3 Byte 5 r = retries s = step option Cylinder Low Track Opcode 07) d = drive (0 or 1 ) s = step option s s ch =cylinder high Reserved This Opcode is not (Class 0, used (Opcode 09) Write Bit 7 6 5 (Class 0, Byte 0 0 0 Opcode OA) Byte 1 0 0 010 1 0 1 0 d Head Number Byte 2 1 0 Sector Number 0 r = retries s = step option ch = cylinder high 0 0 0 s s 4 3 2 1 0 Seek Bit 7 6 5 Byte 0 0 0 010 Opcode OB) Byte 1 0 0 d Byte 2 1 0 1 s 1 I Head Number 10 0 ch 0 0 0 0 Cylinder Low Byte 3 x x x x x x x x Byte 5 r 0 0 0 0 s s s Fixed Disk Adapter d = drive (0 or 1 ) r = retries s = step option x = don"t care ch = cylinder high 4: Byte d = drive (0 or 1) Block Count r (Class 0, 1-196 2 Cylinder Low Byte 4 Byte 5 3 I I ch Byte 3 4 Command Data Control Block Remarks 4 3 2 01 0 1 1 0 6 5 4 3 2 1 1 0 Initialize 1 Bit Drive I Byte 0 17 6 10 0 I Bit I7 5 1 01 01 Bytes 1,2, 3, 4, 5 = don't care Characteristics* (Class 0, Opcode OC) Read ECC Burst Error Length I Byte 0 10 0 010 1 01 1 I Bytes 1, 2, 3, 4, 5 = don't care (Class 0, Opcode OD) Read Data from 1 Bit Sector Buffer I Byte 0 17 6 5 4 3 2 1 10 0 oj Bytes 1, 2, 3, 4, 5 = 01 0 1 1 1 OJ don't care 17 6 5 4 3 2 10 0 01 0 1 1 1 01 1 1 don't care 6 5 4 3 2 1 01 Bytes 1, 2, 3, 4, 5 = 1 10 0 0 0 don't care (Class 0, Opcode OE) Write Data to 1 Bit Sector Buffer I Byte 0 I Bytes 1, 2, 3,4,5 = (Class 0, Opcode OF) RAM Diagnostic I Bit 17 I Byte 0 I 1 1 01 (Class 7, Opcode 00) Reserved This Opcode is not (Class 7, used Opcode 01) Reserved This Opcode is not (Class 7, used Opcode 02) *Initialize Drive Characteristics: The DCB must be followed by eight additional bytes. Maximum number of cylinders (2 bytes) Maximum number of heads (1 byte) Start reduced write current cylinder (2 bytes) Start write precompensation cylinder (2 bytes) Maximum ECC data burst length (1 byte) Fixed Disk Adapter 1-197 Command Data Control Block Remarks 7 6 5 d = drive (0 or 1) 1 1 Ia a a 1 1 a 1 1 s = step option a a d Ix x x x x r = retries Byte 2 x x x x x x x x x = don't care Byte 3 x x x x x x x x Byte 4 x x x x x x x x Byte 5 r a a a a s s s Controller Bit 7 6 4 3 2 Internal Byte 1 1 1 10 a 1 1 a a a 7 6 5 4 3 2 1 a d = drive (0 or 1 ) 1 1 1 10 a 1 a 1 s = step option Drive Bit Diagnostic Byte (Class 7, Byte 1 Opcode 03) a a 5 4 3 2 Bytes 1, 2, 3,4,5 = don't care Diagnostics (Class 7, Opcode 04) Read Long* Bit (Class 7, Byte Opcode 05) Byte 1 a a Byte 2 ch a d I I Head Number ch = cylinder high Cylinder Low Byte 3 Byte 4 Block Count Byte 5 r a a a a s s s 7 6 5 4 3 2 1 1 1 1 10 a 1 1 a a Write Long** Bit (Class 7, Byte Opcode 06) Byte 1 a a Byte 2 ch a d I Byte 3 d = drive (0 or 1 ) s = step option I Head Number r = retries ch = cylinder high Sector Number Cylinder Low Byte 4 Byte 5 r = retries Sector Number Block Count r a a a a s s s *Returns 512 bytes plus 4 bytes of ECC data per sector. **Requires 512 bytes plus 4 bytes of ECC data per sector. 1-198 Fixed Disk Adapter Programming Summary The two least-significant bits of the address bus are sent to the system board's I/O port decoder, which has two sections. One section is enabled by the I/O read signal (-lOR) and the other by the I/O write signal (-lOW). The result is a total of four read/write ports assigned to the disk controller board. The address enable signal (AEN) is asserted by the system board when DMA is controlling data transfer. When AEN is asserted, the I/O port decoder is disabled. The following figure is a table of the four read/write ports: Function R/W Port Address Read Write 320 320 Read data (from controller to system unit). Write data (from system unit to controller). Read Write 321 321 Read controller hardware status. Controller reset. Read Write 322 322 Reserved. Generate controller-select pulse. Read Write 323 323 Not used. Write pattern to DMA and interrupt mask register. Fixed Disk Adapter 1-199 System I/O Channel Interface The following lines are used by the disk controller: AO-A19 Positive true 20-bit address. The least-significant 10 bits contain the I/O address within the range of hex 320 to hex 323 when an I/O read or write is executed by the system unit. The full 20 bits are decoded to address the read-only memory (ROM) between the addresses of hex C8000 and C9FFF. DO-D7 Positive 8-bit data bus over which data and status information is passed between the system board and the controller. Negative true signal that is asserted when the system board reads status or data from the controller under either programmed I/O or DMA control. Negative true signal that is asserted when the system board sends a command or data to the controller under either programmed I/O or DMA control. AEN Positive true signal that is asserted when the DMA in the system board is generating the I/O Read (-lOR) or I/O Write (-lOW) signals and has control of the address and data buses. RESET Positive true signal that forces the disk controller to its initial power-up condition. IRQ 5 Positive true interrupt request signal that is asserted by the controller, when enabled to interrupt the system board on the return ending status byte from the controller. 1-200 Fixed Disk Adapter DRQ 3 Positive-true DMA-request signal that is asserted by the controller when data is available for transfer to or from the controller under DMA control. This signal remains active until the system board's DMA channel activates the DMA-acknowledge signal (-DACK 3) in response. DACK 3 This signal is true when negative, and is generated by the system board DMA channel in response to a DMA request (DRQ 3). Fixed Disk Adapter 1-201 Pin 34 Pin 20 Pin 2 Signal Ground - Odd Numbers Reserved Pin Number 1-33 4,16,30,32 -Reduced Write Current 2 -Write Gate 6 -Seek Complete D isk D rive C onnector J1 8 -Track 00 10 -Write Fault 12 -Head Select 2 0 14 -Head Select 21 18 -Index 20 -Ready 22 -Step 24 -Drive Select 1 26 -Drive Select 2 28 -Direction In 34 Signal Ground Drive Select Reserved Spare Pin Number 2,~~8, 12, 16,20 1 3, 7 9, 10, 5 (No Pin) D isk Ground 11 D rive C onnector MFM Write Data 13 -MFM Write Data 14 Ground 15 J2 orJ3 MFM Read Data 17 -MFM Read Data 18 Ground 19 Fixed Disk Adapter Interface Specifications 1-202 Fixed Disk Adapter Disk Adapter Connect or J1 Disk Adapter Connect or J2 or J3 IBM 10MB Fixed Disk Drive The disk drive is a random-access storage device that uses two non-removable 5-1/4 inch disks for storage. Each disk surface employs one movable head to service 306 cylinders. The total formatted capacity of the four heads and surfaces is 10 megabytes (17 sectors per track with 512 bytes per sector and a total of 1224 tracks). An impact-resistant enclosure provides mechanical and contamination protection for the heads, actuator, and disks. A self-contained recirculating system supplies clean air through a 0.3-micron filter. Thermal isolation of the stepper and spindle motor assemblies from the disk enclosure results in a very low temperature rise within the enclosure. This isolation provides a greater off-track margin and the ability to perform read and write operations immediately after power-up with no thermal stabilization delay. Scrubbing Filter sting Disk Fixed Disk Drive 1-203 Media Rigid media disk Number of Tracks 1224 Track Density 345 tracks per inch Dimensions Height Width Depth Weight 3.25 inches (82.55 mm) 5.75 inches (146.05 mm) 8.0 inches (203.2 mm) 4.6 Ib (2.08 kg) Temperature Operating Non operating 40°F to 122°F (4°C to 50°C) -40° F to 140° F (-40° C to 60° C) Relative Humidity Operating Maximum Wet Bulb 8% to 80% (non condensing) 78°F (26°C) Shock Operating Non operating 10 Gs 20 Gs Access Time 3 ms track-to-track Average Latency 8.33 ms Error Rates Soft Read Errors Hard Read Errors Seek Errors 1 per 10 10 bits read 1 per 10 12 bits read 1 per 106 seeks Design Life 5-years (8,000 hours MTF) Disk Speed 3600 rpm ±1 % Tra nsfer Rate 5.0 M bits/sec Recording Mode MFM Power +12 Vdc ± 5% 1.8 A (4.5 A maximum) +5 Vdc ± 5% 0.7 A (1.0 A maximum) Maximum Ripple 1 % with equivalent resistive load Mechanical and Electrical Specifications 1-204 Fixed Disk Drive IBM Memory Expansion Options Three memory expansion options (32KB, 64KB, and 64/256KB) and two memory module kits (16KB and 64KB) are available for the IBM Personal Computer. Memory expansion is described in the following chart: Minimum Maximum Memory Memory Number of Number of 16K Memory 64K Memory Module Kits Module Kits Memory Module Type 16K by 1 Bit, 16 pin 16/64K System Board 16K 64K 64/256K System Board 64K 256K 1,2, Or 3 64K by 1 Bit, 16 pin 64/256K 64K 256K 1,2, or 3 64K by 1 Bit, 16 pin Memory Option 1,2, or 3 32K Memory Option 32K 16K by 1 Bit, 16 pin 64K Memory Option 64K Stacked 32K by 1 Bit, 18 pin The system board must be fully populated before any memory expansion options can be installed. An expansion option must be configured to reside at a sequential 32K or 64K memory address boundary within the system address space. This is done by setting the DIP switches on the option. All memory expansion options are parity checked. If a parity error is detected, a latch is set and an I/O channel check line is activated, indicating an error to the processor. Memory Expansion Options 1-205 In addition to the memory modules, the memory expansion options contain the following circuits: bus buffering, dynamic memory timing generation, address multiplexing, and card-select decode logic. Dynamic-memory refresh timing and address generation are functions performed on the system board and made available in the I/O channel for all devices. To allow the system to address 32K, 64K, or 64/256K memory expansion options, refer to "Appendix G: Switch Settings" for the proper memory expansion option switch settings. Operating Characteristics The system board operates at a frequency of 4.77 MHz, which results in a clock cycle of 210 ns. Normally four clock cycles are required for a bus cycle so that an 840-ns memory cycle time is achieved. Memory-write and memory-read cycles both take four clock cycles, or 840 ns. General specifications for memory used on all cards are: 16K by 1 Bit 32K by 1 Bit 64K by 1 Bit Access 250 ns 250 ns 200 ns Cycle 410 ns 410 ns 345 ns Memory Module Description Both the 32K and the 64K options contain 18 dynamic memory modules. The 32K memory expansion option utilizes 16K by 1 bit modules, and the 64K memory expansion option utilizes 32K by 1 bit modules. 1-206 Memory Expansion Options The 64/256K option has four banks of 9 pluggable sockets. Each bank will accept a 64K memory module kit, consisting of 9 (64K by 1) modules. The kits must be installed sequentially into banks 1,2, and 3. The base 64/256K option comes with modules installed in bank 0, providing 64K of memory. One, two, or three 64K bits may be added, upgrading the option to 128K, 192K, or 256K of memory. The 16K by 1 and the 32K by 1 modules require three voltage levels: +5 Vdc, -5 Vdc, and + 12 Vdc. The 64K by 1 modules require only one voltage level of +5 Vdc. All three memory modules require 128 refresh cycles every 2 ns. Absolute maximum access times are: 16K by 1 Bit 32K by 1 Bit 64K by 1 Bit From RAS 250 ns 250 ns 200 ns CAS 165 ns 165 ns 115 ns From Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 16K by 1 Bit Module (used on 32K option and 16/64K system board) -5 Vdc Data In** -Write -RAS AO A2 A1 +12 Vdc +5 Vdc A5 A4 A3 A6 Data Out** -CAS GND * * 32K by 1 Bit Module (used on 64K option) -5 Vdc Data In** -Write -RAS 0 -RAS 1 AO A2 A1 +12 Vdc +5 Vdc A5 A4 A3 A6 Data Out** -CAS 1 -CAS 0 GND 64K by 1 Bit Module (used on 64/256K option and 64/256K system board) N/C Data In*** -Write -RAS AO A2 A1 +5 Vdc A7 A5 A4 A3 A6 Data Out*** -CAS GND * * *16K by 1 and 64K by 1 bit modules have 16 pins. **Data In and Data Out are tied together (three-state bus), ***Data In and Data Out are tied together on Data Bits 0-7 (three-state bus). Memory Module Pin Configuration Memory Expansion Options 1- 207 Switch-Configurable Start Address Each card has a small DIP module, that contains eight switches. The switches are used to set the card start address as follows: Number 32K and 64K Options 64/256K Options 1 2 3 4 5 6 7 8 ON: A 19=0; OFF: A 19=1 ON: A18=0; OFF: A18=1 ON:A17=0; OFF: A17=1 ON:A16=0:OFF:A16=1 ON:A15=0;OFF:A15=1* Not used Not used Used only in 64K RAM Card* ON: A 19=0; OFF: A 19=1 ON: A 18=0; OFF: A 18=1 ON:A17=0;OFF:A17=1 ON:A16=0;OFF:A16=1 ON: Select 64K ON: Select 128K ON: Select 192K ON: Select 256K *Switch 8 may be set on the 64K memory expansion option to use only half the memory on the card (that is, 32K). If switch 8 is on, all 64K is accessible. If switch 8 is off, address bit A 15 (as set by switch 5) is used to determine which 32K are accessible, and the 64K option behaves as a 32K option. DIP Module Start Address Memory Option Switch Settings Switch settings for all memory expansion options are located in "Appendix G: Switch Settings." 1-208 Memory Expansion Options The following method can be used to determine the switch settings for the 32K memory expansion option. Starting Address = xxxK =Decimal value 32K IxxxK Convert decimal value to binary Bit ........ 4 Bit value ... 16 3 8 2 4 1 2 0 Switch bit '-----0 1..------- 2 (off = logical 1 ) '-------3 '--------4 The following method can be used to determine the switch settings for the 64K memory expansion option. Starting Address = xxxK =Decimal value 64K IxxxK Convert decimal value to binary Bit ........ 3 Bit value ... 8 2 4 0 2 Switch rn hlr 00001 bit L------O ' - - - - - - - - 2 (off = logical 1) L-._ _ _ _ _ _ _ _ 3 Memory Expansion Options 1-209 The following method can be used to determine the switch settings for the 64/256K memory expansion option. Starting Address = xxxK =Decimal value 64K IxxxK Convert decimal value to binary Bit ........ 3 Bit value ... 8 2 4 0 2 Switch Amount of memory installed on option ' - - - - 256K ' - - - - - 192K (on = logical 1) ' - - - - - - 128K 64K bit '-------0 ' - - - - - - - - - 2 (off = logical 1 ) .......-------3 1-210 Memory Expansion Options IBM Game Control Adapter The game control adapter allows up to four paddles or two joy sticks to be attached to the system. This card fits into one of the system board's or expansion board's expansion slots. The game control interface cable attaches to the rear ofthe adapter. In addition, four inputs for switches are provided. Paddle and joy stick positions are determined by changing resistive values sent to the adapter. The adapter plus system software converts the present resistive value to a relative paddle or joy stick position. On receipt of an output signal, four timing circuits are started. By determining the time required for the circuit to time-out (a function of the resistance), the paddle position can be determined. This adapter could be used as a general purpose I/O card with four analog (resistive) inputs plus four digital input points. - A9 AO I ... . ) 10 r AEN F lOW .. Convert Resistance Digital Pulse Instruction Decode AResistive Input K.. 4 I F lOR ..... - ~ 4-D7-DO A . A 8 Data Bus Buffer/ Driver ( ... Typical Frequency 833 Hz 4 Digital Inputs ..... K. 4 J Game Control Adapter Block Diagram Game Control Adapter 1-211 Functional Description Address Decode The select on the game control adapter is generated by two 74LS138s as an address decoder. AEN must be inactive while the address is hex 201 in order to generate the select. The select allows a write to fire the one-shots or a read to give the values of the trigger buttons and one-shot outputs. Data Bus Buffer/Driver The data bus is buffered by a 74LS244 buffer/driver. For an In from address hex 201, the game control adapter will drive the data bus; at all other times, the buffer is left in the high impedance state. Trigger Buttons The trigger button inputs are read by an In from address hex 201. A trigger button is on each joy stick or paddle. These values are seen on data bits 7 through 4. These buttons default to an open state and are read as "1." When a button is pressed, it is read as "0." Software should be aware that these buttons are not debounced in hardware. Joy Stick Positions The joy stick position is indicated by a potentiometer for each coordinate. Each potentiometer has a range from 0 to 100 k-ohms that varies the time constant for each ofthe four one-shots. As this time constant is set at different values, the output of the one-shot will be of varying durations. All four one-shots are fired at once by an Out to address hex 201. All four one-shot outputs will go true after the fire pulse and will remain high for varying times depending on where each potentiometer is set. These four one-shot outputs are read by an In from address hex 201 and are seen on data bits 3 through O. 1-212 Game Control Adapter I/O Channel Description A9-AO: Address lines 9 through 0 are used to address the game control adapter. D7-DO: Data lines 7 through 0 are the data bus. lOR, lOW: I/O read and I/O write are used when reading from or writing to an adapter (In, Out). AEN: When active, the adapter must be inactive and the data bus driver inactive. +5 Vdc: Power for the game control adapter. GND: Common ground. AI9-AI0: Unused. MEMR,MEMW: Unused. DACKO-DACK3: Unused. IRQ7-IRQ2: Unused. DRQ3-DRQ1: Unused. ALE, TIC: Unused. CLK,OSC: Unused. I/O CHCK: Unused. I/O CHRDY: Unused. RESETDRV: Unused. -5 Vdc, +12 Vdc, -12 Vdc: Unused. Game Control Adapter 1-213 Interface Description The game control adapter has eight input lines, four of which are digital inputs and 4 of which are resistive inputs. The inputs are read with one In from address hex 201. The four digital inputs each have a 1 k-ohm pullup resistor +5 Vdc. With no drives on these inputs, a 1 is read. For a 0 reading, the inputs must be pulled to ground. The four resistive pullups, measured to +5 Vdc, will be converted to a digital pulse with a duration proportional to the resistive load, according to the following equation: Time = 24.2 fLsec + 0.011 (r) fLsec The user must first begin the conversation by an Out to address hex 201. An In from address hex 201 will show the digital pulse go high and remain high for the duration according to the resistance value. All four bits (bit 3-bit 0) function in the same manner; their digital pulse will all go high simultaneously and will reset independently according to the input resistance value. Bit 7 Bit 6 I Bit 5 Bit 4 Bit 3 Digital Inputs Bit 2 I Bit 1 Bit 0 Resistive Inputs The typical input to the game control adapter is a set of joy sticks or game paddles. The joy sticks will typically be a set of two (A and B). These will have one or two buttons each with two variable resistances each, with a range from 0 to 100 k-ohms. One variable resistance will indicate the X-coordinate and the other variable resistance will indicate the Y-coordinate. This should be attached to give the following input data: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B-#2 B-#1 A-#2 A-#1 B-Y Button Button Button Button Coordinate 1-214 Game Control Adapter Bit 2 Bit 1 Bit 0 B-X Coordinate A-Y Coordinate A-X Coordinate The game paddles will have a set of two (A and B) or four (A, B, C, and D) paddles. These will have one button each and one variable resistance each, with a range of 0 to 100 k-ohms. This should be attached to give the following input data: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 D C BAD Bit 1 Bit 0 C B A Coordinate Coordinate Coordinate Bit 2 Button Button Button Button Coordinate Refer to "Joy Stick Schematic Diagram" for attaching game controllers. 15-Pin Male D-Shell Connector Joy Stick B r---------------, I r----------------I----!-I"9 X.Coordinate I • :'0 Butto~J 1'---1-_-,-1~1 1.. Y -Coordinate oil I I I I I I IL _____________ JI r ____J~~~~~_A___ ~ ~--+---------------~ 2 I I X-Coordinate ....}-I I ~ r-Button __ -8 Bit 10 Bit 11 Bit 12 ' - - - - - - - - - - - - - - - Bit 13 ' - - - - - - - - - - - - - - - - + - Bit 14 1..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.... Bit 15 Divisor Latch Most Significant Bit (DLM) The following figure illustrates the use of the baud rate generator with a frequency of 1.8432 MHz,. For baud rates of 9600 and below, the error obtained is minimal. Note: The maximum operating frequency of the baud generator is 3.1 MHz. In no case should the data rate be greater than 9600 baud. Desired Baud Rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 Divisor Used to Generate 16x Clock (Hex) (Decimal) 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 Percent Error Difference Between Desired and Actual 900 600 417 359 300 180 - OCO - 060 040 03A 030 020 018 010 - OOC Baud Rate at 1.843 MHz 1-238 Asynchronous Adapter - 0.026 0.058 - - 0.69 - Line Status Register This 8-bit register provides status information on the processor concerning the data transfer. The contents of the line status register are indicated and described below: Hex Address 3FD Bit 7 6 5 4 3 2 o I I 1_: 0,., R"dy (DR, Overrun Error (OR) Parity Error (PE) ' - - - - - - - - _ Framing Error (FE) '----------~ '------------~ '--------------~ Break Interrupt (BI) Transmitter Holding Register Empty (THRE) Tx Shift Register Empty (TSRE) ~---------------=O Line Status Register (LSR) Bit 0: This bit is the receiver data ready (DR) indicator. Bit 0 is set to a logical 1 whenever a complete incoming character has been received and transferred into the receiver buffer register. Bit o may be reset to a logical 0 either by the processor reading the data in the receiver buffer register or by writing a logical 0 into it from the processor. Bit 1: This bit is the overrun error (OE) indicator. Bit 1 indicates that data in the receiver buffer register was not read by the processor before the next character was transferred into the receiver buffer register, thereby destroying the previous character. The OE indicator is reset whenever the processor reads the contents of the line status register. Bit 2: This bit is the parity error (PE) indicator .. Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity-select bit. The PE bit is set to a logical 1 upon detection of a parity error and is reset to a logical 0 whenever the processor reads the contents of the line status register. Asynchronous Adapter 1-239 Bit 3: This bit is the framing error (FE) indicator. Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logical 1 whenever the stop bit following the last data bit or parity is detected as a zero bit (spacing level). Bit 4: This bit is the break interrupt (BI) indicator. Bit 4 is set to a logical 1 whenever the received data input is held in the spacing (logical 0) state for longer than a full word transmission time (that is, the total time of start bit + data bits + parity +stop bits). Note: Bits 1 through 4 are the error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions are detected. Bit 5: This bit is the transmitter holding register empty (THRE) indicator. Bit 5 indicates that the INS8250 is ready to accept a new character for transmission. In addition, this bit causes the INS8250 to issue an interrupt to the processor when the transmit holding register empty interrupt enable is set high. The THRE bit is set to a logical 1 when a character is transferred from the transmitter holding register into the transmitter shift register. The bit is reset to logical 0 concurrently with the loading of the transmitter holding register by the processor. Bit 6: This bit is the transmitter shift register empty (TSRE) indicator. Bit 6 is set to a logical 1 whenever the transmitter shift register is idle. It is reset to logical 0 upon a data transfer from the transmitter holding register to the transmitter shift register. Bit 6 is a read-only bit. Bit 7: This bit is permanently set to logical O. Interrupt Identification Register The INS8250 has an on-chip interrupt capability that allows for complete flexibility in interfacing to all the popular microprocessors presently available. In order to provide minimum software overhead during data character transfers, the INS8250 prioritizes interrupts into four levels: receiver line status (priority 1), received data ready (priority 2), transmitter holding register empty (priority 3), and modem status (priority 4). 1-240 Asynchronous Adapter Information indicating that a prioritized interrupt is pending and the type of prioritized interrupt is stored in the interrupt identification register. Refer to the "Interrupt Control Functions" table. The interrupt identification register (IIR), when addressed during chip-select time, freezes the highest priority interrupt pending, and no other interrupts are acknowledged until that particular interrupt is serviced by the processor. The contents of the IIR are indicated and described below. Hex Address 3FA Bit 7 6 543 a 2 [I I~ L~ 0 If 'oW,"p' P, odi0 9 Interrupt 10 Bit (0) Interrupt 10 Bit (1) =0 1....-_ _ _ _ _ _ I....--------~ 1....-_ _ _ _ _ _ _ _- . . L...-_ _ _ _ _ _ _ _ _ _..... a = a = a = a = Interrupt Identification Register OIR) Bit 0: This bit can be used in either a hard-wired prioritized or polled environment to indicate whether an interrupt is pending and the IIR contents may be used as a pointer to the appropriate interrupt service routine. When bit 0 is a logical 1, no interrupt is pending and polling (if used) is continued. Bits 1 and 2: These two bits of the IIR are used to identify the highest priority interrupt pending as indicated in the "Interrupt Control Functions" table. Bits 3 through 7: These five bits of the IIR are always logical O. Asynchronous Adapter 1-241 Interrupt 10 Register Bit 2 Bit 1 Bit 0 Interrupt Set and Reset Functions Priority Level 0 0 1 - 1 1 0 1 0 0 0 Interrupt Type Interrupt Source Interrupt Reset Control - None None Highest Receiver Line Status Overrun Error or Parity Error or Fra mi ng Error or Break Interrupt 0 Second Received Receiver Data Available Data Available Reading the Receiver Buffer Register 1 0 Third Transmitter Holding Register Empty Transmitter Holding Register Empty Reading the IIR Register (if source of interrupt) or Writing into the Transmitter Holding Register 0 0 Fourth Modem Status Clear to Send or Data Set Ready or Ring Indicator or Received Line Signal Direct Reading the Modem Status Register Interrupt Control Functions 1-242 Asynchronous Adapter Reading the Line Status Register Interrupt Enable Register This eight-bit register enables the four types of interrupt of the INS8250 to separately activate the chip interrupt (INTRPT) output signal. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of the interrupt enable register. Similarly, by setting the appropriate bits of this register to a logical 1, selected interrupts can be enabled. Disabling the interrupt system inhibits the interrupt identification register and the active (high) INTRPT output from the chip. All other system functions operate in their normal manner, including the setting of the line status and modem status registers. The contents of the interrupt enable register are indicated and described below: Hex Address 3F9 DLAB = Bit 7 6 a 543 2 a ~ L L...-_ _ _ _~ 1 = Enable Data Available Interrupt 1 = Enable Tx Holding Register Empty Interrupt 1 = Enable Receive Line Status Interrupt 1 = Enable Modem Status Interrupt L...------~·=O '---------~ = ' - - - - - - - - - -..... = ' - - - - - - - - - - - -. . . = a a a Interrupt Enable Register (IER) Bit 0: This bit enables the received data available interrupt when set to logical 1. Bit 1: This bit enables the transmitter holding register empty interrupt when set to logical 1. Bit 2: This bit enables the receiver line status interrupt when set to logical 1. Asynchronous Adapter 1-243 Bit 3: This bit enables the modem status interrupt when set to logical 1. Bits 4 through 7: These four bits are always logical O. Modem Control Register This eight-bit register controls the interface with the modem or data set (or peripheral device emulating a modem). The contents of the modem control register are indicated and described below: Hex Address 3FC Bit 7 6 543 2 III a I ~ Do<, Toem'''' R"dy,DTR, Request to Send (RTS) Out 1 L...-_ _ _ _ _• L...-_ _ _ _ _ _ _ L...-_ _ _ _ _ _ _ _• L...-_ _ _ _ _ _ _ _ _ _ _ Out 2 Loop = = = a a a Modem Control Register (MCR) Bit 0: This bit controls the data terminal ready (DTR) output. When bit 0 is set to logical 1, the DTR output is forced to a logical O. When bit 0 is reset to a logical 0, the DTR output is forced to a logical 1. Note: The DTR output ofthe INS8250 may be applied to an EIA inverting line driver (such as the DS 1488) to obtain the proper polarity input at the succeeding modem or data set. Bit 1: This bit controls the request to send (RTS) output. Bit 1 affects the RTS output in a manner identical to that described above for bit O. 1-244 Asynchronous Adapter Bit 2: This bit controls the output 1 (OUT 1) signal, which is an auxiliary user-designated output. Bit 2 affects the OUT 1 output in a manner identical to that described above for bit O. Bit 3: This bit controls the output 2 (OUT 2) signal, which is an auxiliary user-designated output. Bit 3 affects the OUT 2 output in a manner identical to that described above for bit O. Bit 4: This bit provides a loopback feature for diagnostic testing of the INS8250. When bit 4 is set to logical 1, the following occurs: the transmitter serial output (SOUT) is set to the marking (logical 1) state; the receiver serial input (SIN) is disconnected; the output of the transmitter shift register is "looped back" into the receiver shift register input; the four modem control inputs (CTS, DRS, RLSD, and RI) are disconnected; and the four modem control outputs (DTR, RTS, OUT 1, and OUT 2) are internally connected to the four modem control inputs. In the diagnostic mode, data that is transmitted is immediately received. This feature allows the processor to verify the transmit- and receive-data paths of the INS8250. In the diagnostic mode, the receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational but the interrupts' sources are now the lower four bits of the modem control register instead of the four modem control inputs. The interrupts are still controlled by the interrupt enable register. The INS8250 interrupt system can be tested by writing into the lower four bits of the modem status register. Setting any of these bits to a logical 1 generates the appropriate interrupt (if enabled). The resetting of these interrupts is the same as in normal INS8250 operation. To return to normal operation, the registers must be reprogrammed for normal operation and then bit 4 of the modem control register must be reset to logical O. Bits 5 through 7: These bits are permanently set to logical O. Asynchronous Adapter 1-245 Modem Status Register This eight-bit register provides the current state of the control lines from the modem (or peripheral device) to the processor. In addition to this current-state information, four bits of the modem status register provide change information. These bits are set to a logical I whenever a control input from the modem changes state. They are reset to logical 0 whenever the processor reads the modem status register. The content of the modem status register are indicated and described below: Hex Address 3FE Bit 7 6 543 2 II I: o L -_ _ _ _~ De", CI,,, '" Seod ,DCTSI Delta Data Set Ready (DDSR) Trailing Edge Ring Indicator (TERI) Delta Rx Line Signal Detect (DRLSD) '-------~ '----------....,~ Clear to Send (CTS) Data Set Ready (DSR) ' - - - - - - - - - - - Ring Indicator (RI) ' - - - - - - - - - - - - , . . Receive Line Signal Detect (RLSD) Modem Status Register (MSR) Bit 0: This bit is the delta clear to send (DCTS) indicator. Bit 0 indicates that the CTS input to the chip has changed state since the last time it was read by the processor. Bit I: This bit is the delta data set ready (DDSR) indicator. Bit I indicates that the DRS input to the chip has changed since the last time it was read by the processor. Bit 2: This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip has changed from an on (logical I) to an off (logical 0) condition. 1-246 Asynchronous Adapter Bit 3: This bit is the delta received line signal detector (DRLSD) indicator. Bit 3 indicates that the RLSD input to the chip has changed state. Note: Whenever bit 0, 1, 2, or 3 is set to a logical 1, a modem status interrupt is generated. Bit 4: This bit is the complement of the clear to send (CTS) input. If bit 4 (LOOP) of the MCR is set to a logical 1, this is equivalent to RTS in the MCR. Bit 5: This bit is the complement of the data set ready (DSR) input. If bit 4 of the MeR is set to a logical 1, this bit is equivalent to DTR in the MeR. Bit 6: This bit is the complement of the ring indicator (RI) input. If bit 4 of the MeR is set to a logical 1, this bit is equivalent to OUT 1 in the MeR. Bit 7: This bit is the complement of the received line signal detect (RLSD) input. If bit 4 of the MeR is set to a logical 1, this bit is equivalent to OUT 2 of the MeR. Receiver Buffer Register The receiver buffer register contains the received character as defined below: Hex Address 3F8 7 Bit 6 DLAB = 0 5 4 3 Read Only 2 o I ~ ~ ~ Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 ' - - - - - - - _ Data Bit 4 ' - - - - - - - -__~ Data Bit 5 Data Bit 6 1--_ _ _ _ _ _ _ _..... '---------------l~ Data Bit 7 Receiver Buffer Register (R BR) Bit ° is the least significant bit and is the first bit serially received. Asynchronous Adapter 1-247 Transmitter Holding Register The transmitter holding register contains the character to be serially transmitted and is defined below: Hex Address 3F8 Bit 7 DLAB = 0 654 3 Write Only o 2 I ~ '-- Data Bit 0 ~ Data Bitl Data Bit 2 Data Bit 3 '----------1~ Data Bit 4 ' - - - - - - - - -.... Data Bit 5 ' - - - - - - - - - -....... Data Bit 6 ' - - - - - - - - - - - -.... Data Bit 7 Transmitter Holding Register (THR) Bit 0 is the least significant bit and is the first bit serially transmitted. 1-248 Asynchronous Adapter Selecting the Interface Format and Adapter Address The voltage or current loop interface and adapter address are selected by plugging the programmed shunt modules with the locator dots up or down. See the figure below for the configurations. Module Position for Primary Asynchronous Adapter Module Position for Alternate Asynchronous Adapter D D D o Asynchronous Communications A d a pte r Current Loop Interface Dot Down u.J.J..LJ...L..L.U..!..J.jI-l.U..L.L.L..JL.J.J.J..LJ...L..L..L.f.J.J..L.J...U..J Socket Voltage Interface Dot Up Asynchronous Adapter 1-249 Rear Panel 25-Pin D-Shell Connector o 25 • • • 14 At standard RS-232C Levels (with exception of current loops) Description External Device Note: o Pin NC 1 Transmitted Data 2 Received Data 3 Request to Send 4 Clear to Send 5 Data Set Ready 6 Signal Ground 7 Received Line Signal Detector 8 +Transmit Current Loop Data 9 NC 10 -Transmit Current Loop Data 11 NC 12 NC 13 NC 14 NC 15 NC 16 NC 17 +Receive Current Loop Data 18 NC 19 Data Terminal Ready 20 NC 21 Ring Indicator 22 NC 23 NC 24 -Receive Current Loop Return 25 Asynchr onous Commu nications Adapter (RS-232 C) To avoid inducing voltage surges on interchange circuits. signals from interchange circuits shall be used to drive inductive devices. such as relay coils. Connector Specifications 1-250 Asynchronous Adapter Binary Synchronous Communications Adapter The binary synchronous communication (BSC) adapter is a 4-inch high by 7 .5-inch wide card that provides an RS232C-compatible communication interface for the IBM Personal Computer. All system control, voltage, and data signals are provided through a 2- by 31-position card-edge tab. External interface is in the form of EIA drivers and receivers connected to an RS232C, standard 25-pin, D-shell connector. The adapter is programmed by communication software to operate in binary synchronous mode. Maximum transmission rate is 9600 bits per second (bps). The heart of the adapter is an Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART). An Intel 8255A-5 programmable peripheral interface (PPI) is also used for an expanded modem interface, and an Intel 8253-5 programmable interval timer provides time-outs and generates interrupts. The following is a block diagram of the BSC adapter. TIMER EIA Drivers/ Receivers 8253 - System Bus ' I I I I I I I I I I Data Bus p:L I I I L....J 'i :L:L I Control /, I I rAddress Data Comm unication Equip ment t r ~ I I I 8251A '------ I Programmable Peripheral Interface I I I I I I I I I I I L....J r----- [;j ~ V; I USART ~'-'/); 8255A5 Bse Adapter Block Diagram BSC Adapter 1-251 Functional Description 8251A Universal Synchronous/Asynchronous Receiver/Transmitter The 8251A operational characteristics are programmed by the system unit's software, and it can support virtually any form of synchronous data technique currently in use. In the configuration being described, the 8251A is used for IBM's binary synchronous communications (BSC) protocol in half-duplex mode. Operation of the 8251 A is started by programming the communications format, then entering commands to tell the 8251A what operation is to be performed. In addition, the 8251A can pass device status to the system unit by doing a Status Read operation. The sequence of events to accomplish this are mode instruction, command instruction, and status read. Mode instruction must follow a master reset operation. Commands can be issued in the data block at any time during operation of the 8251A. A block diagram of the 8251A follows: TxD TxRDY TxE TxC RxD INTERNAL DATA BUS 8251A Block Diagram 1-252 BSC Adapter RxRDY RxC SYNDET Data Bus Buffer The system unit's data bus interfaces the 8251A through the data bus buffer. Data is transferred or received by the buffer upon execution of input or output instructions from the system unit. Control words, command words, and status information are also transferred through the data bus buffer. ReadIWrite Control Logic The read/write control logic controls the transfer of information between the system unit and the 8251A. It consists of pins designated as RESET, CLK, WR, RD, C/D, and CS. RESET: The Reset pin is gated by Port B, bit 4 of the 8255, and performs a master reset of the 8251A. The minimum reset pulse width is 6 clock cycles. Clock-cycle duration is determined by the oscillator speed of the processor. CLK (Clock): The clock generates internal device timing. No external inputs or outputs are referenced to CLK. The input is the system board's bus clock of 4.77 MHz. WR (Write): An input to WR informs the 8251A that the system unit is writing data or control words to it. The input is the WR signal from the system-unit bus. RD (Read): An input to RD informs the 8251A that the processing unit is reading data or status information from it. The input is the RD signal from the system-unit bus. C/D (Control/Data): An input on this pin, in conjunction with the WR and RD inputs, informs the 8251A that the word on the data bus is either a data character, a control word, or status information. The input is the low-order address bit from the system board's address bus. CS (Chip Select): A low on the input selects the 8251A. No reading or writing will occur unless the device is selected. An input is decoded at the adapter from the address information on the system-unit bus. BSC Adapter 1-253 Modem Control The 8251A has the following input and output control signals which are used to interface the transmission equipment selected by the user. DSR (Data Set Ready): The DSR input port is a general-purpose, I-bit, inverting input port. The 8251A can test its condition with a Status Read operation. CTS (Clear to Send): A low on this input enables the 825lA to transfer serial data if the TxEnable bit in the command byte is set to 1. If either a TxEnable off or CTS off condition occurs while the transmitter is in operation, the transmitter will send all the data in the USART that was written prior to the TxDisable command, before shutting down. DTR (Data Terminal Ready): The DTR output port is a general-purpose, I-bit, inverting output port. It can be set low by programming the appropriate bit in the command instruction word. RTS (Request to Send): The RTS output signal is a general-purpose, I-bit, inverting output port. It can be set low by programming the appropriate bit in the Command Instruction word. Transmitter Buffer The transmitter buffer accepts parallel data from the data-bus buffer, converts it to a serial bit stream, and inserts the appropriate characters or bits for the BSC protocol. The output from the transmit buffer is a composite serial stream of data on the falling edge of Transmit Clock. The transmitter will begin transferring data upon being enabled, if CTS = 0 (active). The transmit data (TxD) line will be set in the marking state upon receipt of a master reset, or when transmit enable/CTS is off and the transmitter is empty (TxEmpty). 1-254 BSC Adapter Transmitter Control Transmitter control manages all activities associated with the transfer of serial data. It accepts and issues the following signals, both externally and internally, to accomplish this function: TxRDY (Transmitter Ready): This output signals the system unit that the transmitter is ready to accept a data character. The TxRDY output pin is used as an interrupt to the system unit (Level 4) and is masked by turning off Transmit Enable. TxRDY is automatically reset by the leading edge of a WR input signal when a data character is loaded from the system unit. TxE (Transmitter Empty): register input. This signal is used only as a status TxC (Transmit Clock): The Transmit Clock controls the rate at which the character is to be transmitted. In synchronous mode, the bit-per-second rate is equal to the TxC frequency. The falling edge of TxC shifts the serial data out of the 8251A. Receiver Buffer The receiver accepts serial data, converts it to parallel format, checks for bits or characters that are unique to the communication technique, and sends an "assembled" character to the system unit. Serial data input is received on the RxD (Receive Data) pin, and is clocked in on the rising edge of RxC (Receive Clock). Receiver Control This control manages all receiver-related activites. The parity-toggle and parity-error flip-flop circuits are used for parity-error detection, and set the corresponding status bit. BSC Adapter 1-255 RxRDY (Receiver Ready): This output indicates that the 8251A has a character that is ready to be received by the system unit. RxRDY is connected to the interrupt structure of the system unit (Interrupt Level 3). With Receive Enable off, RxRDY is masked and held in the reset mode. To set RxRDY, the receiver must be enabled, and a character must finish assembly and be transferred to the data output register. Failure to read the received character from the RxData output register before the assembly of the next RxData character will set an overrun-condition error, and the previous character will be lost. RxC (Receiver Clock): The receiver clock controls the rate at which the character is to be received. The bit rate is equal to the actual frequency of RxC. SYNDET (Synchronization Detect): This pin is used for synchronization detection and may be used as either input or output, programmable through the control word. It is reset to output-mode-low upon reset. When used as an output (internal synchronization mode), the SYNDET pin will go to 1 to indicate that the 8251A has found the synchronization character in the receive mode. If the 8251A is programmed to use double synchronization characters (bisynchronization as in this application), the SYNDET pin will go to 1 in the middle of the last bit of the second synchronization character. SYNDET is automatically reset for a Status Read operation. 8255A-5 Programmable Peripheral Interface The 8255A-5 is used on the BSC adapter to provide an expanded modem interface and for internal gating and control functions. It has three 8-bit ports, which are defined by the system during initialization of the adapter. All levels are considered plus active unless otherwise indicated. A detailed description of the ports is in "Programming Considerations" in this section. 1-256 BSC Adapter 8253-5 Programmable Interval Timer The 8253-5 is driven by a divided-by-two system-clock signal. Its outputs are used as clocking signals and to generate inactivity timeout interrupts. These level 4 interrupts occur when either of the timers reaches its programmed terminal counts. The 8253-5 has the following outputs: Timer 0: Not used for synchronous-mode operation. Timer 1: Connected to port A, bit 7 of the 8255 and Interrupt Level 4. Timer 2: Connected to port A, bit 6 of the 8255 and Interrupt Level 4. Operation The complete functional definition of the BSC adapter is programmed by the system software. Initialization and control words are sent out by the system to initialize the adapter and program the communications format in which it operates. Once programmed, the BSC Adapter is ready to perform its communication functions. Transmit In synchronous transmission, the TxD output is continuously at a mark level until the system sends its first character, which is a synchronization character to the 8251A. When the CTS line goes on, the first character is serially transmitted. All bits are shifted out on the falling edge of TxC. When the 8251A is ready to receive another character from the system for transmission, it raises TxRDY, which causes a level-4 interrupt. BSC Adapter 1-257 Once transmission has started, the data stream at the TxD output must continue at the TxC rate. If the system does not provide the 8251A with a data character before the 8251A transmit buffers become empty, the synchronization characters will be automatically inserted in the TxD data stream. In this case, the TxE bit in the status register is raised high to signal that the 8251A is empty and that synchronization characters are being sent out. (Note that this TxE bit is in the status register, and is not the TxE pin on the 8251A). TxE does not go low when SYNC is being shifted out. The TxE status bit is internally reset by a data character being written to the 8251A. Receive In synchronous reception, the 8251A will achieve character synchronization, because the hardware design of the BSC adapter is intended for internal synchronization. Therefore, the SYNDET pin on the 8251A is not connected to the adapter circuits. For internal synchronization, the Enter Hunt command should be included in the first command instruction word written. Data on the RxD pin is then sampled in on the rising edge of RxC. The content of the RxD buffer is compared at every bit boundary with the first SYNC character until a match occurs. Because the 8251A has been programmed for two synchronization characters (bisynchronization), the next received character is also compared. When both SYNC characters have been detected, the 8251A ends the hunt mode and is in character synchronization. The SYNDET bit in the status register (not the SYNDET pin) is then set high, and is reset automatically by a Status Read. Once synchronization has occurred, the 8251A begins to assemble received data bytes. When a character is assembled and ready to be transferred to memory from the 8251A, it raises RxRDY, causing an interrupt level 3 to the system. If the system has not fetched a previous character by the time another received character is assembled (and an interrupt-level 3 issued by the adapter), the old character will be overwritten, and the overrun error flag will be raised. All error flags can be reset by an error reset operation. 1-258 BSC Adapter Programming Considerations Before starting data transmission or reception, the BSC adapter is programmed by the system unit to define control and gating ports, timer functions and counts, and the communication environment in which it is to operate. Typical Programming Sequence The 8255A-5 programmable peripheral interface (PPI) is initialized for the proper mode by selecting address hex 3A3 and writing the control word. This defines port A as an input, port B as an output for modem control and gating, and port C for 4-bit input and 4-bit output. The bit descriptions for the 8255A-5 are shown in the following figures. Using an output to port C, the adapter is then set to wrap mode, disallow interrupts, and gate external clocks (address=3A2H, data=ODH). The adapter is now isolated from the communication interface, and initialization continues. Through bit 4 of 8255 Port B, the 8251A reset pin is brought high, held, then dropped. This resets the internal registers of the 8251A. BSC Adapter 1-259 8255 Port A Assignments Input Port Bit 7 Address: hex 3AO for BSC hex 380 for Alternate BSC 6543210 I_I~ ___L. ~ : Ei~::t~~~~:~~~~;{:s:~ E~~~~ertace IIII L - - I : 0 = Clear-to-Send is on from Interface ' - - - - - - - - - _ Oscillating = Receive Clock Active 1 = TxROY Active ' - - - - - - - - - - - - -__ 1 = Timer 2 Output Active ' - - - - - - - - - - - - - - - _ + _ 1 = Timer 1 Output Active 8255 Port B Assignments Output Port Bit 7 6 5 4 Address: hex 3A 1 for BSC hex 381 for Alternate BSC 3 I o 2 I I ~ 0 ~ To," "" 0•• Si,",IA,OS,'oc,", 0= Turn on Select Standby 0= Turn on Test 1 = Not Used ' - -_ _ _ _ _ _ __ + _ 1 = Reset 8251 A ' - - - - - - - - - - - - . - 1 = Gate Timer 2 ' - - - - - - - - - - - - -__ 1 = Gate Timer 1 ' - - - - - - - - - - - - - - - - 1 = Gate Timers 1 and 2 to Interrupt Level 4 Address: hex 3A2 for BSC hex 382 for Alternate BSC 8255 Port C Assignments Bit 7 6 4 3 2 I 1_: 1 I 0 L-- 1 = Gate Internal Clock (Output Bit) 1 = Gate External Clock (Output Bit) ,-,- - - - _ - 1 = Electronic Wrap (Output Bit) ' - - - - - -__ 0 = Enable Timer 1 and 2, Interrupt 6 and Receive Interrupt 3 ' - - - - - - - - - _ _ + _ Oscillating = Receive Data (Input Bit) '--_ _ _ _ _ _ _ _ _ _ Oscillating = Timer 0 Output (Input Bit) ' - - - - - - - - - - - - -__ 0 = Test Indicate Active (Input Bit) ' - - - - - - - - - - - - - - - _ _ . 0 = BSC Adapter I The 8253-5 programmable interval timer is used in the synchronous mode to provide inactivity time-outs to interrupt the system unit after a preselected period of time has elapsed from the start of a communication operation. Counter a is not used for synchronous operation. Counters 1 and 2 are connected to interrupt-level 4, and are programmed to terminal-count values, which will provide the desired time delay before a level-4 interrupt is generated. These interrupts will indicate to the system software that a predetermined period of time has elapsed without a TxRDY (level 4) or RxRDY (level 3) interrupt being sent to the system unit. 1-260 BSC Adapter The modes for each counter are programmed by selecting each timer-register address and writing the correct control word for counter operation to the adapter. The mode for counters 1 and 2 is set to O. The terminal-count values are loaded using control-word bits D4 and D5 to select "load." The 8253-5 Control Word format is shown in the following chart. Control Word Format D7 I D6 D5 Address hex 3A7 D4 D3 SC1 I sca I RL 1 I RLa I M2 D2 M1 I D1 I DO Ma I BCDI Definition of Control SC - Select Counter: SC1 SCO a a Select Cou nter a a 1 Select Counter 1 1 a Select Counter 2 1 1 Illegal RL - Read/Load: RL1 RLO a a Cou nter Latch i ng operation 1 a Read/Load most significant byte only a 1 Read/Load least significant byte only 1 1 Read/Load least significant byte first, then most significant byte M - Mode: M2 M1 MO I I I I a a a Mode a I Terminal Count Interrupt BCD: a Binary Counter 16-bits 1 Binary Coded Decimal (BCD) Counter (4 Decades) 8253-5 Control Word Format BSC Adapter 1-261 8251A Programming Procedures After the support devices on the BSC adapter are programmed, the 8251A is loaded with a set of control words that define the communication environment. The control words are split into two formats, mode instruction, and command instruction. Both the mode and command instructions must conform to a specified sequence for proper device operation. The mode instruction must be inserted immediately after a reset operation, before using the 8251A for data communications. The required synchronization characters for the defined communications technique are next loaded into the 8251A (usually hex 32 for BSC). All control words written to the 8251A after the mode instruction will load the command instruction. Command instructions can be written to the 8251A at any time in the data block during the operation of the 8251A. To return to the mode instruction format, the master reset bit in the command instruction word can be set to start an internal reset operation which automatically places the 8251A back into the mode instruction format. Command instructions must follow the mode instructions or synchronization characters. The following diagram is a typical data block, showing the mode instruction and command instruction. 3A9 C/O = 1 Mode Instruction 1 3A9 C/O = 1 SYNC Character 1 3A9 C/O = 1 SYNC Character 2 3A9 cliS = 1 Command Instruction 3AB c/o = 0 Oata 3A9 C/O = 1 3AB C/O = 0 3A9 C/O = 1 Command Instruction " Oata Command Instruction Typical Data Block 1-262 BSC Adapter J Mode Instruction Definition The mode instruction defines the general operational characteristics of the 8251A. It follows a reset operation (internal or external). Once the mode instruction has been written to the 8251A by the system unit, synchronization characters or command instructions may be written to the device. The following figure shows the format for the mode instruction. Address: Hex 3A9 for BSe Hex 389 for Alternate BSe Mode Instruction Format Bit 7 6 5 II 4 3 2 1 0 I ~ N",","dlAI~" 01 Not Used (Always 0) Character Length Bit - - - Character Length Bit - - - - '",bI, 1I = ~"" Even Parity 1 = SYNDET is an Input 0= Double SYNC Character 0 I - - ., - 1 I 0 1 1 1 0 1 5 Bits 6 Bits 7 Bits 8 Bits Bit 0 Not used; always = 0 Bit 1 Not used; always Bit 2 and Bit 3 These two bits are used together to define the character length. With 0 and 1 as inputs on bits 2 and 3, character lengths of 5,6, 7, and 8 bits can be established, as shown in the preceding figure. Bit 4 In the synchronous mode, parity is enabled from this bit. A 1 on this bit sets parity enable. Bit 5 The parity generation/check is set from this bit. For BSC, even parity is used by having bit 5 = 1. Bit 6 External synchronization is set by this bit. A Ion this bit establishes synchronization detection as an input. Bit 7 This bit establishes the mode of character synchronization. A 0 is set on this bit to give double character synchronization. = 0 BSC Adapter 1-263 Command-Instruction Format The command-instruction format defines a status word that is used to control the actual operation of the 8251A. Once the mode instruction has been written to the 8251A, and SYNC characters loaded, all further "Control Writes" to I/O address hex 3A9 or hex 389 will load a command instruction. Data is transferred by accessing two I/O ports on the 8251A, ports 3A8 and 388. A byte of data can be read from port 3A8 and can be written to port 388. Address: Hex 3A9 for BSe Hex 389 for Alternate BSe Bit 7 6 5 I 4 I 3 I 2 I 1 0 ~ Transmit Enable Data Terminal Ready Receive Enable Send Break Character Error Reset Request to Send Internal Reset Enter Hunt Mode Command Instruction Format Bit 0 The Transmit Enable bit sets the function of the 8251A to either enabled (1) or disabled (0). Bit 1 The Data Terminal Ready bit, when set to 1 will force the data terminal output to O. This is a one-bit inverting output port. Bit 2 The Receive Enable bit sets the function to either enable the bit (1), or to disable the bit (0). Bit 3 The Send Break Character bit is set to 0 for normal BSC operation. Bit 4 The Error Reset bit is set to 1 to reset error flags from the command instruction. Bit 5 A 1 on the Request to Send bit will set the output to O. This is a one-bit inverting output port. 1-264 BSC Adapter Bit 6 The Internal Reset bit when set to 1 returns the 8251A to mode-instruction format. Bit 7 The Enter Hunt bit is set to 1 for BSC to enable a search for synchronization characters. Status Read Definition In telecommunication systems, the status of the active device must often be checked to determine if errors or other conditions have occurred that require the processor's attention. The 8251A has a status read facility that allows the system software to read the status of the device at anytime during the functional operation. A normal read command is issued by the processor with I/O address hex 3A9 for BSC, and hex 389 for Alternate BSC to perform a status read operation. The format for a status read word is shown in the figure below. Some of the bits in the status read format have the same meanings as external output pins so the 8251A can be used in a completely polled environment or in an interrupt-driven environment. Address: Hex 3A9 for sse Hex 389 for Alternate BSe Bits 0 ~ 1 • RxRDY 2 ~ TxEmpty 4 ~ Overrun Error (OE Flag On when Overrun Error Occurs) 5 ~ Framing Error (Not Used for Synchronous Communications) 6 7 ~ SYNDET ~ Data Set Ready (Indicates that DSR is at 0 Level) 3 _ TxR DY (See Note Below) Parity Error (PE Flag On when a Parity Error Occurs) Note: TxRDY status bit does not have the same meaning as the 8251A TxR DY output pin. The former is not conditioned by CTS and TxEnable. The latter is conditioned by both CTS and TxEnable. Status Read Format Bit 0 See the Note in the preceding chart. Bit 1 An output on this bit means a character is ready to be received by the computers 8088 microprocessor. BSC Adapter 1-265 Bit 2 A 1 on this bit indicates the 8251A has no characters to transmit. Bit 3 The Parity Error bit sets a flag when errors are detected. It is reset by the error reset in the command instruction. Bit 4 This bit sets a flag when the computers 8088 microprocessor does not read a character before another one is presented. The 8251A operation is not inhibited by this flag, but the overrun character will be lost. Bit 5 Not used Bit 6 SYNDET goes to 1 when the synchronization character is found in receive mode. For BSC, SYNDET goes high in the middle of the last bit of the second synchronization character. Bit 7 The Data Set Ready bit is a one bit inverting input. It is used to check modem conditions, such as data-set ready. Interface Signal Information The BSC adapter conforms to interface signal levels standardized by the Electronics Industry Association (EIA) RS232C Standard. These levels are shown in the following figure. Additional lines, not standardized by the EIA, are pins 11, 18, and 25 on the interface connector. These lines are designated as Select Standby, Test, and Test Indicate. Select Standby is used to support the switched network backup facility of a modem that provides this option. Test and Test Indicate support a modem wrap function on modems that are designated for business-machine, controlled-modem wraps. 1-266 BSC Adapter Driver EIA RS232C/CCITT V24-V28 Signal Levels +15 Vdc - - - - - - - - - - - - - , =0 Active/Data +5 Vdc +5 Vdc Invalid Level -5 Vdc -5 Vdc Inactive/Data = 1 -15Vdc Receiver EIA RS232C/CCITT V24-V28 Signal Levels +25Vdc .--------------------, Active/Data =0 +3 Vdc +3 Vdc I nval id Level -3 Vdc -3 Vdc Inactive/Data = 1 -25 Vdc Interface Voltage Levels BSC Adapter 1-267 Interrupt Information Interrupt Level 4: Transmitter Ready Counter 1 Counter 2 Interrupt Level 3: Receiver Ready Hex Address Device Register Name Function Primary Alternate 3AO 3A1 3A2 3A3 380 381 382 383 8255 8255 8255 8255 Port A Data Port B Data Port C Data Mode Set I nternal/External Sensing External Modem Interface I nternal Control 8255 Mode Initialization 3A4 3A4 3A5 3A5 3A6 3A6 3A7 384 384 385 385 386 386 387 8253 8253 8253 8253 8253 8253 8253 Counter 0 LSB Counter 0 MSB Counter 1 LSB Counter 1 MSB Counter 2 LSB Counter 2 MSB Mode Register Not Used in Synch Mode Not Used in Synch Mode I nactivity Time-Outs I nactivity Time-Outs I nactivity Time-Outs I nactivity Time-Outs 8253 Mode Set 3A8 3A9 388 389 8251 8251 Data Select Command/Status Data Mode/Command USART Status Device Address Summary 1-268 BSC Adapter 25-Pin D-Shell Connector C'J • • • • • • • • • • • • • • • • • • • • C'J eC'J C'~C'J J 25 14 0 Signal Name - Description No Connection External Device Pin 1 Transmitted Data 2 Received Data 3 Request to Send 4 Clear to Send 5 Data Set Ready 6 Signal Ground 7 Received Line Signal Detector 8 No Connection 9 No Connection 10 Select Standby* 11 No Connection 12 No Connection· 13 No Connection 14 Transmitter Signal Element Timing 15 No Connection 16 Receiver Signal Element Timing 17 Test (IBM Modems Only)- 18 No Connection 19 Data Terminal Ready 20 No Connection 21 Ring Indicator 22 Data Signal Rate Selector 23 No Connection 24 Test Indicate (IBM Modems Only)- 25 Binary Synchron ous Communi cations Adapter -Not standardized by EIA (Electronics Industry Association). Connector Specifications BSC Adapter 1-269 Notes: 1·270 BSC Adapter IBM Synchronous Data Link Control (SDLC) Communications Adapter The SDLC communications adapter system control, voltage, and data signals are provided through a 2 by 31 position card edge tab. Modem interface is in the form of EIA drivers and receivers connecting to an RS232C standard 25-pin, D-shell, male connector. The adapter is programmed by communications software to operate in a half-duplex synchronous mode. Maximum transmission rate is 9600 bits per second, as generated by the attached modem or other data communication equipment. The SDLC adapter utilizes an Intel 8273 SDLC protocol controller and an Intel 8255A-5 programmable peripheral interface for an expanded external modem interface. An Intel 8253 programmable interval timer is also provided to generate timing and interrupt signals. Internal test loop capability is provided for diagnostic purposes. The figure below is a block diagram of the SDLC communications adapter. ~--::,...---~ 8255A·5 Data Bus Buffer EIA Drivers Receivers System Bus Address Address Decode logic L - -_ _ _~ Controller DCE Modem Status Change logic SDLC Communications Adapter Block Diagram SDLC Adapter 1-271 The 8273 SDLC protocol control module has the following key features: • Automatic frame check sequence generation and checking. • Automatic zero bit insertion and deletion. • TTL compatibility. • Dual internal processor architecture, allowing frame level command structure and control of data channel with minimal system processor intervention. The 8273 SDLC protocol controller operations, whether transmission, reception, or port read, are each comprised of three phases: Command Commands and/or parameters for the required operation are issued by the processor. Execution Executes the command, manages the data link, and may transfer data to or from memory utilizing direct memory access (DMA), thus freezing the processor except for minimal interruptions. Result Returns the outcome of the command by returning interrupt results. Support of the controller operational phases is through internal registers and control blocks of the 8273 controller. 1-272 SDLC Adapter 8273 Protocol Controller Structure The 8273 module consists of two major interfaces: the processor interface and the modem interface. A block diagram of the 8273 protocol controller module follows. Registers Txl/R Command Rxl/R Parameter Reset Status Result Data Bus Buffer TxD TxC TxDRQ i5PLL TxDACK RxDRQ 32 x CLK RTS RxDACK PB 1 _4 TxlNT CTS CD RxlNT RD WR Ao Read Write DMA Control Logic A1 RxD RESET RxC CS---...J CLK--------' L..-_ _+_ FLAG DET Internal Data Bus-Processor Interface Modem Interface 8273 SDLC Protocol Control Block Diagram SDLC Adapter 1-273 Processor Interface The processor interface consists of four major blocks: the control/read/write logic (C/R/W), internal registers, data transfer logic, and data bus buffers. Control/Read/Write Logic The control/read/write logic is used by the processor to issue commands to the 8273. Once the 8273 receives and executes a command, it returns the results using the C/R/W logic. The logic is supported by seven registers which are addressed by AO, A I, RD, and WR, in addition to cs. AO and Al are the two low-order bits of the adapter address-byte. RD and WR are the processor read and write signals present on the system control bus. CS is the chip select, also decoded by the adapter address logic. The table below shows the address of each register using the C/R/W logic. Address Inputs Control Inputs AO A1 CS WR 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Register RD 0 1 1 0 0 1 1 0 0 1 1 0 Command Status Parameter Result Reset Txl/R None Rxl/R 8273 SOLC Protocol Controller Register Selection 1-274 SDLC Adapter 8273 Control/ReadlWrite Registers Command Operations are initialized by writing the appropriate command byte into this register. Status This register provides the general status of the 8273. The status register supplies the processor/adapter handshaking necessary during various phases of the 8273 operation. Parameter Additional information that is required to process the command is written into this register. Some commands require more than one parameter. Immediate Result (Result) Commands that execute immediately produce a result byte in this register, to be read by the processor. Transmit Interrupt Results (TxIIR) Results of transmit operations are passed to the processor from this register. This result generates an interrupt to the processor when the result becomes available. Receiver Interrupt Results (Rx/l/R) Results of receive operations are passed to the processor from this register. This result generates an interrupt to the processor when the result becomes available. Reset This register provides a software reset function for the 8273. The other elements of the C/R/W logic are the interrupt lines (RxINT and TxINT). Interrupt priorities are listed in the "Interrupt Information" table in this section. These lines signal the processor that either the transmitter or the receiver requires service (results should be read from the appropriate register), or a data transfer is required. The status of each interrupt line is also reflected by a bit in the status register, so non-interrupt driven operation is also possible by the communication software examining these bits periodically. SDLC Adapter 1-275 Data Interfaces The 8273 supports two independent data interfaces through the data transfer logic: received data and transmitted data. These interfaces are programmable for either DMA or non-DMA data transfers. Speeds below 9600 bits-per-second mayor may not require DMA, depending on the task load and interrupt response time of the processor. The processor DMA controller is used for management of DMA data transfer timing and addressing. The 8273 handles the transfer requests and actual counts of data-block lengths. DMA level 1 is used to transmit and receive data transfers. Dual DMA support is not provided. Elements of Data Transfer Interface TxDRQIRxDRQ This line requests a DMA to or from memory and is asserted by the 8273. TxDACKIRxDACK This line notifies the 8273 that a request has been granted and provides access to data regions. This line is returned by the DMA controller (DACKI on the system unit control bus is connected to TxDACK/RxDACK on the 8273). RD (Read) This line indicates data is to be read from the 8273 and placed in memory. It is controlled by the processor DMA controller. WR (Write) This line indicates if data is to be written to the 8273 from memory and is controlled by the processor DMA controller. To request a DMA transfer, the 8273 raises the DMA request line. Once the DMA controller obtains control ofthe system bus, it notifies the 8273 that the DRQ is granted by returning DACK, and WR or RD, for a transmit or receive operation, respectively. The DACK and WR or RD signals transfer data between the 8273 and memory, independent of the 8273 chip-select pin (CS). This "hard select" of data into the transmitter or out of the receiver alleviates the need for the normal transmit and receive data registers, addressed bya combination of address lines, CS, and WRorRD. 1-276 SDLC Adapter Modem Interface The modem interface of the 8273 consists of two major blocks: the modem control block and the serial data timing block. Modem Control Block The modem control block provides both dedicated and user-defined modem control function. EIA inverting drivers and receivers are used to convert TTL levels to EIA levels. Port A is a modem control input port. Bits PAD and PAl have dedicated functions. 8273 Port A (Modem Control Input Port) Bit PA 7 6 5 4 321 0 II~ PAO Clear to Send PA 1 Carrier Detect PA2 Data Set Ready PA3 CTS Change PA4 DSR Change Not Used Bit PAD This bit reflects the logical state of the clear to send (CTS) pin. The 8273 waits until CTS is active before it starts transmitting a frame. If CTS goes inactive while transmitting, the frame is aborted and the processor is interrupted. A CTS failure will be indicated in the appropriate interrupt-result register. Bit PAl This bit reflects the logical state of the carrier detect pin (CD). CD must be active in sufficient time for reception of a frame's address field. If CD is lost (goes inactive) while receiving a frame, an interrupt is generated with a CD failure result. Bit PA2 This bit is a sense bit for data set ready (DSR). Bit PA3 This bit is a sense bit to detect a change in CTS. SDLC Adapter 1-277 This bit is a sense bit to detect a change in data set ready. Bit PA4 Bits PAS to P A 7 These bits are not used and each is read as a 1 for a read port A command. Port B is a modem control output port. Bits PBO and PBS are dedicated function pins. 8273 Port B (Modem Control Output Port) Bit PB 7 6 5 4 3 2 1 0 II I~ 1- ~ PBO Re,,"" '" Seod PB 1 - Reserved PB2 - Data Terminal Ready PB3 - Reserved ' - - - - - - - _ PB4 - Reserved '--------~ '-----------~ PB5 - Flag Detect PB6 - Not Used ' - - - - - - - - - - - - - - . . PB7 - Not Used Bit PBO This bit represents the logical state of request to send (RTS). This function is handled automatically by the 8273. Bit PB 1 Reserved. Bit PB2 Used for data terminal ready. Bit PB3 Reserved. Bit PB4 Reserved. Bit PBS This bit reflects the state of the flag detect pin. This pin is activated whenever an active receiver sees a flag character. Bit PB6 Not used. Bit PB7 1-278 Not used. SDLC Adapter Serial Data Timing Block The serial data timing block is comprised of two sections: the serial data logic and the digital phase locked loop (DPLL). Elements of the serial data logic section are the data pins TxD (transmitted data output) and RxD (received data input), and the respective clocks. The leading edge of TxC generates new transmitted data and the trailing edge of RxC is used to capture the received data. The figure below shows the timing for these signals. TxC TxD RxC RxD 8273 SOLC Protocol Controller Transmit/Receive Timing The digital phase locked loop provided on the 8273 controller module is utilized to capture looped data in proper synchronization during wrap operations performed by diagnostics. SDLC Adapter 1-279 8255A-5 Programmable Peripheral Interface The 8255A-5 contains three 8-bit ports. Descriptions of each bit of these ports are as follows: 8255A-5 Port A Assignments* Bit 7 6 5 4 3 2 Hex Address 380 1 0 ~ 0= Ring Indicator is on from Interface 0= Data Carrier Detect is on from Interface Oscillating = Transmit Clock Active 0= Clear to Send is on from Interface Oscillating = Receive Clock Active 1 = Modem Status Changed 1 = Timer 2 Output Active 1 = Timer 1 Output Active *Port A is defined as an input port 8255A-5 Port B Assignments* Bit 7 6 5 4 3 2 Hex Address 381 1 0 II ~ ~ 0 Tom 00 0". Sigo.IR", S,I,ct" Modem Interface 0= Turn On Select Standby at Modem Interface 0= Turn On Test 1 = Reset Modem Status Changed Logic 1 = Reset 8273 1 = Gate Timer 2 1 = Gate Timer 1 1 = Enable Level 4 Interrupt *Port B is defined as an output port 1-280 SDLC Adapter 8255A-5 Port C Assignments' Bit 7 6 5 4 3 2 1 III Hex Address 382 0 ~ ~ 1 G." 100em" Clook ,0",,", .,,' 1 = Gate External Clock (Output Bit) 1 = Electronic Wrap (Output Bit) 0= Gate Interrupts 3 and 4 (Output Bit) Oscillating = Receive Data (Input Bit) Oscillating = Timer 0 Output (Input bit) 0= Test Indicate Active (Input Bit) Not Used 'Port C is defined for internal control and gating functions. It has three input and four output bits. The four output bits are defined during initialization, but only three are used. 8253-5 Programmable Interval Timer The 8253-5 is driven by a processor clock signal divided by two_ It has the following output: Timer 0 Programmed to generate a square wave signal, used as an input to timer 2. Also connected to 8253 port C, bit 5. Timer 1 Connected to 8255 port A, bit 7, and interrupt level 4. Timer 2 Connected to 8255 port A, bit 6, and interrupt level 4. Programming Considerations The software aspects ofthe 8273 involve the communication of both commands from the processor to the 8273 and the return of results of those commands from the 8273 to the processor. Due to the internal processor architecture of the 8273, this system unit/8273 communication is basically a form of interprocessor communication, and must be considered when programming for the SDLC communications adapter. SDLC Adapter 1-281 The protocol for this interprocessor communication is implemented through use of handshaking supplied in the 8273 status register. The bit defintions of this register are shown below. 8273 Status Register Format Bit 7 6 5 4 3 2 Hex Address 388 1 0 III~~ T.IRA 1 = TdNT R""''',,iI,bI, RxlRA 1 = RxlNT Result Available TxlNT 1 = Tx Interrupt L -_ _ _ _ _ RxlNT 1 = Rx Interrupt CRBF 1 = Command Result Buffer Full ' - - - - - - - - CPBF 1 = Command Parameter Buffer Full ' - - - - - - - - - CBF 1 = Command Buffer Full ' - - - - - - - - - CBSY 1 = Command Busy Bit 0 This bit is the transmitter interrupt result available (TxlRA) bit. This bit is set when the 8273 places an interrupt-result byte in the TxI/R register, and reset when the processor reads the TxI/R register. Bit 1 This bit is the receiver interrupt result available (RxlRA) bit. It is the corresponding result-available bit for the receiver. It is set when the 8273 places an interrupt-result byte in the Rxl/R register and reset when the processor reads the register. Bit 2 This bit is the transmitter interrupt (TxINT) bit and reflects the state of the TxINT pin. TxINT is set by the 8273 whenever the transmitter needs servicing, and reset when the processor reads the result or performs the data transfer. Bit 3 This bit is the receiver interrupt (RxINT) bit and is identical to the TxINT, except action is initiated based on receiver interrupt-sources. Bit 4 This bit is the command result buffer full (CRBF) bit. It is set when the 8273 places a result from an immediate-type command in the result register, and reset when the processor reads the result or performs the data transfer. 1-282 SDLC Adapter Bit 5 This bit is the command parameter buffer full (CPBF) bit and indicates that the parameter register contains a parameter. It is set when the processor deposits a parameter in the parameter register, and reset when the 8273 accepts the parameter. Bit 6 This bit is the command buffer full (CBF) bit and, when set, it indicates that a byte is present in the command register. This bit is normally not used. Bit 7 This bit is the command busy (CBSY) bit and indicates when the 8273 is in the command phase. It is set when the processor writes a command into the command register, starting the command phase. It is reset when the last parameter is deposited in the parameter register and accepted by the 8273, completing the command phase. Initializing the Adapter (Typical Sequence) Before initialization of the 8273 protocol controller, the support devices on the card must be initialized to the proper modes of operation. Configuration of the 825 5A -5 programmable peripheral interface is accomplished by selecting the mode-set address for the 8255 (see the "SDLC Communications Adapter Device Addresses" table later in this section) and writing the appropriate control word to the device (hex 98) to set ports A, B, and C to the modes described previously in this section. Next, a bit pattern is output to port C which disallows interrupts, sets wrap mode on, and gates the external clock pins (address = hex 382, data = hex OD). The adapter is now isolated from the communications interface. Using bit 4 of port B, the 8273 reset line is brought high, held and then dropped. This resets the internal registers of the 8273. SDLC Adapter 1-283 The 8253-5's counter 1 and 2 tenninal-count values are now set to values which will provide the desired time delay before a level 4 interrupt is generated. These interrupts may be used to indicate to the communication software that a pre-detennined period of time has elapsed without a result interrupt (interrupt level 3). The tenninal count-values for these counters are set for any time delay which the programmer requires. Counter 0 is also set at this time to mode 3 (generates square wave signal, used to drive counter 2 input). To setup the counter modes, the address for the 8253 counter mode register is selected (see the "SDLC Communications Adapter Device Addresses" table, later in this section), and the control word for each individual counter is written to the device separately. The control-word fonnat and bit definitions for the 8253 are shown below. Note that the two most-significant bits of the control word select each individual counter, and each counter mode is defined separately. Once the support devices have been initialized to the proper modes and the 8273 has been reset, the 8273 protocol controller is ready to be configured for the operating mode that defines the communications environment in which it will be used. 1-284 SDLC Adapter Control Word Format D, I SCl sca RL 1 RLa M2 Ml Ma BCD Definitions of Control SC - Select Counter: SCl sca a a Select Counter a a 1 Select Counter 1 1 a Select Counter 2 1 1 Illegal RL - Read/Load: RL 1 RLO a a Counter Latching operation 1 a Read/Load most significant byte (MSB) a 1 Read/Load least significant byte (LSB) 1 1 Read/Load least significant byte first, then most significant byte. M - Mode: M2 Ml Ma a a a Modea a a 1 Mode 1 X 1 a Mode 2 X 1 1 Mode 3 1 a a Mode 4 1 a 1 Mode 5 Mode BCD: Binary Counter l6-bits Binary Coded Decimal (BCD) Counter (4 Decades) 8253·5 Programmable Interval Timer Control Word SDLC Adapter 1-285 Initialization/Configuration Commands The initialization/configuration commands manipulate internal registers of the 8273, which define operating modes. After chip reset, the 8273 defaults to alII's in the mode registers. The initialization/configuration commands either set or reset specified bits in the registers depending on the type of command. One parameter is required with the commands. The parameter is actually the bit pattern (mask) used by the set or reset command to manipulate the register bits. Set commands perform a logical OR operation of the parameter (mask) of the internal register. This mask contains l's where register bits are to be set. Zero (O's) in the mask cause no change to the corresponding register bit. Reset commands perform a logical AND operation of the parameter (mask) and internal register. The mask 0 is reset to register bit, and 1 to cause no change. The following are descriptions of each bit of the operating, serial I/O, one-bit delay, and data transfer mode registers. Operating Mode Register 8273 Operating Mode Register Format Bit 7 6 5 4 3 2 1 0 I L ~ 1 = Flag Stream Mode ~1 = Two Preframe Sync Characters 1 = Buffered Mode 1 = Enable Early Tx Interrupt '-----~ '------~ 1 = EOP Interrupt Enable 1 = HDLC Abort Enable ' - - - - - - - Not Used '---------~ 1-286 SDLC Adapter Not Used Bit 0 If bit 0 is set to aI, flags are sent immediately if the transmitter was idle when the bit was set. If a transmit or transmit-transparent command was active, flags are sent immediately after transmit completion. This mode is ignored if loop transmit is active or the one-bit-delay mode register is set for one-bit delay. If bit 0 is reset (to 0), the transmitter sends idles on the next character boundary if idle or, after transmission is complete, if the transmitter was active at bit-O reset time. Bit 1 If bit 1 is set to aI, the 8273 sends two characters before the first flag of a frame. These characters are hex 00 ifNRZI is set or hex 55 ifNRZI is not set. (See "Serial I/O Mode Register," for NRZI encoding mode format.) Bit 2 If bit 2 is set to a 1, the 8273 buffers the first two bytes of a received frame (the bytes are not passed to memory). Resetting this bit (to 0) causes these bytes to be passed to and from memory. Bit 3 This bit indicates to the 8273 when to generate an end-of-frame interrupt. If bit 3 is set, an early interrupt is generated when the last data character has been passed to the 8273. If the processor responds to the early interrupt with another transmit command before the final flag is sent, the final-flag interrupt will not be generated and a new frame will begin when the current frame is complete. Thus, frames may be sent separated by a single flag. A reset condition causes an interrupt to be generated only following a final flag. Bit 4 This is the EOP-interrupt-mode function and is not used on the SDLC communications adapter. This bit should always be in the reset condition. Bit 5 This bit is always reset for SDLC operation, which causes the 8273 protocol controller to recognize eight ones (0 1 1 1 1 1 1 1 1) as an abort character. SDLC Adapter 1-287 Serial I/O Mode Register 8273 Serial 1/0 Mode Register Format Bit 7 6 5 4 3 2 1 0 ~ I L ~ 1 = NRZI Mode 1 = Clock Loopback 1 = Data Loopback Not Used '-----~ Not Used ' - - - - - -.... Not Used ' - - - - - - - _ Not Used ' - - - - - - - -.... Not Used Bit 0 Set to 1, this bit specifies NRZI encoding and decoding. Resetting this bit specifies that transmit and receive data be treated as a normal positive-logic bit stream. Bit 1 When bit 1 is set to 1, the transmit clock is internally routed to the receive-clock circuitry. It is normally used with the loopback bit (bit 2). The reset condition causes the transmit and receive clocks to be routed to their respective 8273 I/O pins. Bit 2 When bit 2 is set, the transmitted data is internally routed to the received data circuitry. The reset condition causes the transmitted and received data to be routed to their respective 8273 I/O pins. Data Transfer Mode Register 8273 Data Transfer Mode Register Format Bit 7 6 5 4 3 2 1 0 I I I II I IL L--L--L.---1-.-1--1--1-----;.~ 1-288 SDLC Adapter 1 = Interrupt Data Transfers Not Used When the data transfer mode register is set, the 8273 protocol controller will interrupt when data bytes are required for transmission, or are available from a reception. If a transmit or receive interrupt occurs and the status register indicates that there is no transmit or receive interrupt result, the interrupt is a transmit or receive data request, respectively. Reset of this register causes DMA requests to be performed with no interrupts to the processor. One-Bit Delay Mode Register 8273 One-Bit Delay Mode Register Format Bit 7 6 5 4 3 2 1 0 I I I I I I I: L---------I_~ Not Used 1 = One-Bit Delay Enable When one-bit delay is set, the 8273 retransmits the received data stream one-bit delayed. Reset of this bit stops the one-bit delay mode. The table below is a summary of all set and reset commands associated with the 8273 mode registers. The set or reset mask used to define individual bits is treated as a single parameter. No result or interrupt is generated by the 8273 after execution of these commands. Command Hex Code Parameter One-Bit Delay Mode Set Reset A4 64 Set Mask Reset Mask Data Transfer Mode Set Reset 97 57 Set Mask Reset Mask Operating Mode Set Reset 91 51 Set Mask Reset Mask Serial 1/0 Mode Set Reset AO 60 Set Mask Reset Mask Register 8273 SDLC Protocol Controller Mode Register Commands SDLC Adapter 1-289 Command Phase Although the 8273 is a full duplex device, there is only one command register. Thus, the command register must be used for only one command sequence at a time and the transmitter and receiver may never be simultaneously in a command phase. The system software starts the command phase by selecting the 8273 command register address and writing a command byte into the register. The following table lists command and parameter information for the 8273 protocol controller. If further information is required by the 8273 prior to execution of the command, the system software must write this information into the parameter register. 1-290 SDLC Adapter Command Description Command (Hex) Parameter Results Set One-Bit Delay A4 Set Mask None Reset One-Bit Delay 64 Reset Mask None Set Data Transfer Mode 97 Set Mask Reset Data Transfer Mode 57 Set Operating Mode Reset Operating Mode Result Port Completion Interrupt No None - Reset Mask None - No 91 Set Mask None Reset Mask None - No 51 No No No Set Serial 110 Mode AO Set Mask None - No Reset Serial 1/0 Mode 60 Reset Mask None - No General Receive CO 80,81 RIC,RO,R1, A,C RXI/R Yes Selective Receive C1 80,81,A1, A2 RIC,RO,R1, A,C RXI/R Yes Receive Disable C5 None None - No Transmit Frame C8 LO,L1,A,C TIC TXI/R Yes Transmit Transparent C9 LO,L1 TIC TXI/R Yes Abort Transmit Frame CC None TIC TXI/R Yes Abort Transmit Transparent CD None TIC TXI/R Yes Read Port A 22 None Port Value Result No Read Port B 23 None Port Value Result No Set Port B Bit A3 Set Mask None - No Reset Port B Bit 63 Reset Mask None - No 8273 Command Summary Key 80 81 LO Al A2 A - C - RXI/R TXI/R RO Rl RIC TIC - 11 Least significant byte of the receiver buffer length. Most significant byte of the receiver buffer length. Least sig nificant byte of the Tx frame length. Most significant byte of the Tx frame length. Receive frame address match field one. Receive frame address match field two. Address field of received frame. If non-buffered mode is specified, this result is not provided. Control field of received frame. If non-buffered mode is specified, this result is not provided. Receive interrupt result register. Transmit interrupt result register. Least significant byte of the length of the frame received. Most significant byte of the length of the frame received. Receiver interrupt result code. Transmitter interrupt result code. 8273 SDLC Protocol Controller Commands SDLC Adapter 1-291 A flowchart of the command phase is shown below. Handshaking of the command and parameter bytes is accomplished by the CBSY and CPBF bits of the status register. A command may not be written if the 8273 is busy (CBSY = 1). The original command will be overwritten if a second command is issued while CBSY = 1. The flowchart also indicates a parameter buffer full check. The processor must wait until CPBF = 0 before writing a parameter to the parameter register. Previous parameters are overwritten and lost if a parameter is written while CPBF = 1. No End of Command Phase 8273 SOLC Protocol Controller Command Phase Flowchart 1-292 SDLC Adapter Execution Phase During the execution phase, the operation specified by the command phase is performed. If DMA is utilized for data transfers, no processor involvement is required. For interrupt-driven transfers the 8273 raises the appropriate INT pin (TxINT or RxINT). When the processor responds to the interrupt, it must determine the cause by examining the status register and the associated IRA (interrupt result available) bit of the status register. If IRA = 0, the interrupt is a data transfer request. If IRA = 1, an operation is complete and the associated interrupt result register must be read to determine completion status. Result Phase During the result phase, the 8273 notifies the processor of the outcome of a command execution. This phase is initiated by either a successful completion or error detection during execution. Some commands such as reading or writing the I/O ports provide immediate results. These results are made available to the processor in the 8273 result register. Presence of a valid immediate result is indicated by the CRBF (command result buffer full) bit of the status register. Non-immediate results deal with the transmitter and receiver. These results are provided in the TxIIR (transmit interrupt result) or RxIIR (receiver interrupt result) registers, respectively. The 8273 notifies the processor that a result is available with the TxIRA and RxIRA bits of the status register. Results consist of one-byte result interrupt code indicating the condition for the interrupt and, if required, one or more bytes supplying additional information. The "Result Code Summary" table later in this section provides information on the format and decode of the transmitter and receiver results. The following are typical frame transmit and receive sequences. These examples assume DMA is utilized for data transfer operations. SDLC Adapter 1-293 Transmit Before a frame can be transmitted, the DMA controller is supplied, by the communication software, the starting address for the desired information field. The 8273 is then commanded to transmit a frame (by issuing a transmit frame command). After a command, but before transmission begins, the 8273 needs some more information (parameters). Four parameters are required for the transmit frame command; the frame address field byte, the frame control field byte, and two bytes which are the least significant and most significant bytes of the information field byte length. Once all four parameters are loaded, the 8273 makes RTS (request to send) active and waits for CTS (clear to send) to go active from the modem interface. Once CTS is active, the 8273 starts the frame transmission. While the 8273 is transmitting the opening flag, address field, and control field, it starts making transmitter DMA requests. These requests continue at character (byte) boundaries until the pre-loaded number of bytes of information field have been transmitted. At this point, the requests stop, the FCS (frame check sequence) and closing flag are transmitted, and the TxINT line is raised, signaling the processor the frame transmission is complete and the result should be read. Note that after the initial command and parameter loading, no processor intervention was required (since DMA is used for data transfers) until the entire frame was transmitted. General Receive Receiver operation is very similar. Like the initial transmit sequence, the processor's DMA controller is loaded with a starting address for a receive data buffer and the 8273 is commanded to receive. Unlike the transmitter, there are two different receive commands; a general receive, where all received frames are transferred to memory, and selective receive, where only frames having an address field matching one of two preprogrammed 827 3 address fields are transferred to memory. 1-294 SDLC Adapter (This example covers a general receive operation.) After the receive command, two parameters are required before the receiver becomes active; the least significant and most significant bytes of the receiver buffer length. Once these bytes are loaded, the receiver is active and the processor may return to other tasks. The next frame appearing at the receiver input is transferred to memory using receiver DMA requests. When the closing flag is received, the 8273 checks the FCS and raises its RxINT line. The processor can then read the results, which indicate if the frame was error-free or not. (If the received frame had been longer than the pre-loaded buffer length, the processor would have been notified of that occurrence earlier with a receiver error interrupt. Like the transmit example, after the initial command, the processor is free for other tasks until a frame is completely received. Selective Receive In selective receive, two parameters (AI and A2) are required in addition to those for general receive. These parameters are two address match bytes. When commanded to selective receive, the 8273 passes to memory or the processor only those frames having an address field matching either A I or A2. This command is usually used for secondary stations with A I designating the secondary address and A2 being the "all parties" address. If only one match byte is needed, Al and A2 should be equal. As in general receive, the 8273 counts the incoming data bytes and interrupts the processor if the received frame is larger than the preset receive buffer length. SDLC Adapter 1-295 Result Code Summary Hex Code T r a n s m i t R e c e i v e Result Status After Interrupt OC 00 OE OF 10 Early Transmit Interrupt Frame Transmit Complete DMA Underrun Clear to Send Error Abort Complete Transmitter Active Idle or Flags Abort Abort Idle or Flags XO X1 03 04 05 06 07 08 09 OA OB A 1 Match or General Receive A2 Match CRC Error Abort Detected Idle Detected EOP Detected Frame Less Than 32 Bits DMA Overrun Memory Buffer Overflow Carrier Detect Failure Receiver Interrupt Overrun Active Active Active Active Disabled Disabled Active Disabled Disabled Disabled Disabled Note: X decodes to number of bits in partial byte received. The first two codes in the receive result code table result from the error free reception of a frame. Since SD LC allows frames of arbitrary length (> 32 bits), the high order bits of the receive result report the number of valid received bits in the last received information field byte. The chart below shows the decode of this receive result bit. X Bits Received in Last Byte E 0 All Eig ht Bits of Last Byte BitO Only Bit1-BitO Bit2-BitO Bit3-BitO Bit4-BitO Bit5-BitO Bit6-BitO 8 4 C 2 A 6 1-296 SDLC Adapter Address and Interrupt Information The following tables provide address and interrupt information for the SDLC adapter: Hex Code Device Register Name Function 380 381 382 383 384 384 385 385 386 386 387 388 389 38A 38B 38C 8255 8255 8255 8255 8253 8253 8253 8253 8253 8253 8253 8273 8273 8273 8273 8273 Port A Data Port B Data Port C Data Mode Set Counter 0 LSB Counter 0 MSB Counter 1 LSB Counter 1 MSB Counter 2 LSB Counter 2 MSB Mode Register Command/Status Para meter /Result Transmit INT Status Receive I NT Status Data Internal/External Sensing External Modem Interface Internal Control 8255 Mode Initialization Square Wave Generator Square Wave Generator Inactivity Time-Outs Inactivity Time-Outs Inactivity Time-Outs Inactivity Time-Outs 8253 Mode Set Out=Command In=Status Out=Parameter In=Status DMA/INT DMA/INT DPC (Direct Program Control) SDLC Communications Adapter Device Addresses Interrupt Level 3 Transmit/Receive Interrupt Interrupt Level 4 Ti mer 1 Interrupt Timer 2 Interrupt Clear to Send Changed Data Set Ready Changed DMA Level One is used for Transmit and Receive Interrupt Information SDLC Adapter 1-297 Interface Information The SDLC communications adapter conforms to interface signal levels standardized by the Electronics Industries Association RS-232C Standard. These levels are shown in the figure below. Additional lines used but not standardized by EIA are pins 11, 18, and 25. These lines are designated as select standby, test and test indicate, respectively. Select Standby is used to support the switched network backup facility of a modem providing this option. Test and test indicate support a modem wrap function on modems which are designed for business machine controlled modem wraps. Two jumpers on the adapter (PI and P2) are used to connect test and test indicate to the interface, if required (see Appendix D for these jumpers). Drivers +15VdC~ Active Level: Data = 0 +5Vdc +3 Vdc Invalid Level -5Vdc ~ 3 VdC Inactive Level: Data = 1 -15VdC- 1-298 C C Receivers +25VdC SDLC Adapter -25 Vdc 25-Pin D-Shell Connector Signal Name - Description No Connection External Device Pin 1 Transmitted Data 2 Received Data 3 Request to Send 4 Clear to Send 5 Data Set Ready 6 Signal Ground 7 Received Line Signal Detector 8 No Connection 9 No Connection 10 Select Standby* 11 No Connection 12 No Connection 13 No Connection 14 Transmitter Signal Element Timing 15 No Connection 16 Receiver Signal Element Timing 17 Test (IBM Modems Only)* 18 No Connection 19 Data Terminal Ready 20 No Connection 21 Ring Indicator 22 Data Signal Rate Selector 23 No Connection 24 Test Indicate (IBM Modems Only)* 25 Synchro nous Data Lin k Control Commun ications Adapter *Not standardized by EIA (Electronics Industry Association). Connector Specifications SDLC Adapter 1-299 Notes: 1-300 SDLC Adapter IBM Communications Adapter Cable The IBM Communications Adapter Cable is a ten foot cable for connection of an IBM communications adapter to a modem or other RS-232C DCE (data communications equipment). It is fully shielded and provides a high quality, low noise channel for interface between the communications adapter and DCE. The connector ends are 25-pin D-shell connectors. All pin connections conform with the EIA RS-232C standard. In addition, connection is provided on pins 11, 18 and 25. These pins are designated as select standby, test and test indicate, respectively, on some modems. Select standby is used to support the switched network backup facility, if applicable. Test and test indicate support a modem wrap function on modems designed for business machine controlled modem wraps. Communications Cable 1-301 The IBM Communications Adapter Cable connects the following pins on the 25-pin D-shell connectors. 14 Communications Adapter Connector ·· .. ·. 13 14 Modem Connector Communications Adapter Connector Pin # Name Modem Connector Pin # 2 3 4 5 Outer Cable Shield Transmitted Data Received Data Request to Send Clear to Send 1 2 3 4 5 6 7 8 Data Set Ready Signal Ground (Inner Lead Shields) Received Line Signal Detector 6 7 8 NC NC NC 11 NC NC Select Standby NC NC NC 15 17 18 Transmitter Signal Element Timing Receiver Signal Element Timing Test 17 18 Data Terminal Ready 20 Ring Indicator Data Signal Rate Selector 22 23 Test Indicate 25 NC NC 22 23 NC NC 25 15 NC NC 20 11 NC NC NC NC NC Connector Specifications 1-302 13 25 25 Communications Cable SECTION 2: ROM BIOS AND SYSTEM USAGE ROM BIOS ........................................ 2-2 Keyboard Encoding and Usage ....................... 2-11 BIOS Cassette Logic ................................ 2-21 ROM BIOS 2-1 Notes: 2·2 ROM BIOS ROM BIOS The basic input/output system (BIOS) resides in ROM on the system board and provides device level control for the major I/O devices in the system. Additional ROM modules may be located on option adapters to provide device level control for that option adapter. BIOS routines enable the assembly language programmer to perform block (disk and diskette) or character-level I/O operations without concern for device address and operating characteristics. System services, such as time-of-day and memory size determination, are provided by the BIOS. The goal is to provide an operational interface to the system and relieve the programmer of the concern about the characteristics of hardware devices. The BIOS interface insulates the user from the hardware, thus allowing new devices to be added to the system, yet retaining the BIOS level interface to the device. In this manner, user programs become transparent to hardware modifications and enhancements. The IBM Personal Computer MACRO Assembler manual and the IBM Personal Computer Disk Operating System (DOS) manual provide useful programming information related to this section. A complete listing of the BIOS is given in Appendix A. Use of BIOS Access to BIOS is through the 8088 software interrupts. Each BIOS entry point is available through its own interrupt, which can be found in the "8088 Software Interrupt Listing." The software interrupts, hex 10 through hex lA, each access a different BIOS routine. For example, to determine the amount of memory available in the system, INT 12H will invoke the BIOS routine for determining memory size and will return the value to the caller. ROM BIOS 2-3 Parameter Passing All parameters passed to and from the BIOS routines go through the 8088 registers. The prolog of each BIOS function indicates the registers used on the call and the return. For the memory size example, no parameters are passed. The memory size, in lK byte increments, is returned in the AX register. If a BIOS function has several possible operations, the AR register is used at input to indicate the desired operation. For example, to set the time of day, the following code is required: MOV AH,l MOV CX,RIG~COUNT MOV DX,LOW~COUNT INT lAR ;function is to set time of day. ;establish the current time. ;set the time. To read the time of day: MOV AH,O INT lAR ;function is to read time of day. ;read the timer. Generally, the BIOS routines save all registers except for AX and the flags. Other registers are modified on return only if they are returning a value to the caller. The exact register usage can be seen in the prolog of each BIOS function. 2-4 ROM BIOS Address (Hex) 0-3 4-7 8-B C-F 10-13 14-17 18-1 B 1 D-1 F 20-23 24-27 28-2B 2C-2F 30-33 34-37 38-3B 3C-3F 40-43 44-47 48-4B 4C-4F 50-53 54-57 58-5B 5C-5F 60-63 64-67 68-6B 6C-6F 70-73 74-77 78-7B 7C-7F Interrupt Number 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Name Divide by Zero Single Step Nonmaskable Breakpoint Overflow Print Screen Reserved Reserved Time of Day Keyboard Reserved Communications Communications Disk Diskette Printer Video Equipment Check Memory Diskette/Disk Communications Cassette Keyboard Printer Resident BASIC Bootstrap Time of Day Keyboard Break Timer Tick Video Initialization Diskette Parameters Video Graphics Chars BIOS Entry D_EOI D_EOI NMUNT P_EOI D_EOI PRINT_SCREEN D_EOI D_EOI TIMERJNT KBJNT D_EOI D_EOI D_EOI D_EOI DISKJNT D_EOI VIDEO_IO EQUIPMENT MEMORY_SIZE_DETERMINE DISKETTEJO RS232JO CASSETTEJO KEYBOARD_IO PRINTERjO F600:0000 BOOT_STRAP TIME_OF_DAY DUMMY_RETURN DUMMY_RETURN VIDEO_PARMS DISK_BASE 0 8088 Software Interrupt Listing ROM BIOS 2-5 Vectors with Special Meanings Interrupt Hex 1B - Keyboard Break Address This vector points to the code to be exercised when the Ctrl and Break keys are pressed on the keyboard. The vector is invoked while responding !o the keyboard interrupt, and control should be returned through an IRET instruction. The power-on routines initialize this vector to point to an IRET instruction, so that nothing will occur when the Ctrl and Break keys are pressed unless the application program sets a different value. Control may be retained by this routine, with the following problems. The Break may have occurred during interrupt processing, so that one or more End of Interrupt commands must be sent to the 8259 controller. Also, all I/O devices should be reset in case an operation was underway at that time. Interrupt Hex 1C - Timer Tick This vector points to the code to be executed on every systemclock tick. This vector is invoked while responding to the timer interrupt, and control should be returned through an IRET instruction. The power-on routines initialize this vector to point to an IRET instruction, so that nothing will occur unless the application modifies the pointer. It is the responsibility of the application to save and restore all registers that will be modified. Interrupt Hex ID - Video Parameters This vector points to a data region containing the parameters required for the initialization of the 6845 on the video card. Note that there are four separate tables, and all four must be reproduced if all modes of operation are to be supported. The power-on routines initialize this vector to point to the parameters contained in the ROM video routines. 2-6 ROM BIOS Interrupt Hex 1E - Diskette Parameters This vector points to a data region containing the parameters required for the diskette drive. The power-on routines initialize the vector to point to the parameters contained in the ROM diskette routine. These default parameters represent the specified values for any IBM drives attached to the machine. Changing this parameter block may be necessary to reflect the specifications of the other drives attached. Interrupt Hex 1F - Graphics Character Extensions When operating in the graphics modes of the IBM Color/Graphics Monitor Adapter (320 by 200 or 640 by 200), the read/write character interface will form the character from the ASCII code point, using a set of dot patterns. The dot patterns for the first 128 code points are contained in ROM. To access the second 128 code points, this vector must be established to point at a table of up to 1K bytes, where each code point is represented by eight bytes of graphic information. At power-on, this vector is initialized to 000:0, and it is the responsibility of the user to change this vector if the additional code points are required. Interrupt Hex 40 - Reserved When an IBM Fixed Disk Drive Adapter is installed, the BIOS routines use interrupt hex 40 to revector the diskette pointer. Interrupt Hex 41 - Fixed Disk Parameters This vector points to a data region containing the parameters required for the fixed disk drive. The power-on routines initialize the vector to point to the parameters contained in the ROM disk routine. These default parameters represent the specified values for any IBM Fixed Disk Drives attached to the machine. Changing this parameter block may be necessary to reflect the specifications of the other fixed disk drives attached. ROM BIOS 2-7 Other ReadIWrite Memory Usage The IBM BIOS routines use 256 bytes of memory starting at absolute hex 400 to hex 4FF. Locations hex 400 to 407 contain the base addresses of any RS-232C cards attached to the system. Locations hex 408 to 40F contain the base addresses of the printer adapter. Memory locations hex 300 to 3FF are used as a stack area during the power-on initialization, and bootstrap, when control is passed to it from power-on. If the user desires the stack in a different area, the area must be set by the application. Address (Hex) Interrupt (Hex) 80-83 84-87 88-8B 8C-8F 90-93 94-97 98-9B 9C-9F AO-FF 100-17F 180-19F 1AO-1FF 200-217 218-3C3 20 21 22 23 24 25 26 27 28-3F 40-5F 60-67 68-7F 80-85 86-FO 3C4-3FF F1-FF Function DOS Program Terminate DOS Function Call DOS Terminate Address DOS Ctrl Break Exit Address DOS Fatal Error Vector DOS Absolute Disk Read DOS Absolute Disk Write DOS Terminate, Fix In Storage Reserved for DOS Reserved Reserved for User Software Interrupts Not Used Reserved by BASIC Used by BASIC Interpreter while BASIC is running Not Used BASIC and DOS Reserved Interrupts 2-8 ROM BIOS Address (Hex) 400-48F 490-4EF 4FO-4FF Mode Function ROM BIOS 500-5FF 500 DOS 504 510-511 512-515 516-519 DOS BASIC BASIC BASIC 51A-51D BASIC See BIOS Listing Reserved Reserved as Intra-Application Communication Area for any application Reserved for DOS and BASIC Print Screen Status Flag Store O-Print Screen Not Active or Successful Print Screen Operation 1-Print Screen In Progress 255-Error Encountered during Print Screen Operation Single Drive Mode Status Byte BASIC's Segment Address Store Clock Interrupt Vector Segment: Offset Store Break Key Interrupt Vector Segment: Offset Store Disk Error Interrupt Vector Segment: Offset Store Reserved Memory Locations If you do DEF SEG (Default workspace segment): Line number of current line being executed Line number of last error Offset into segment of start of program text Offset into segment of start of variables (end of program text 1-1) Keyboard buffer contents if O-no characters in buffer if 1-characters in buffer Character color in graphics mode Set to 1, 2, or 3 to get text in colors 1 to 3. Do not set to O. (Default = 3) Offset (Hex Value) Length 2E 347 30 358 2 2 2 2 6A 1 4E 1 Example 100 Print ~ 100 PEEK (&H2E) L I Hex 64 + 256*PEEK (&H2F) H I Hex 00 I BASIC Workspace Variables ROM BIOS 2-9 Starting Address in Hex 00000 BIOS Interrupt Vectors 00080 Available Interrupt Vectors 00400 BIOS Data Area 00500 User Read/Write Memory C8000 Disk Adapter FOOOO Read Only Memory FEOOO Bios Program Area BIOS Memory Map BIOS Programming Hints The BIOS code is invoked through software interrupts. The programmer should not "hard code" BIOS addresses into applications. The internal workings and absolute addresses within BIOS are subject to change without notice. If an error is reported by the disk or diskette code, you should reset the drive adapter and retry the operation. A specified number of retries should be required on diskette reads to ensure the problem is not due to motor start-up. When altering I/O port bit values, the programmer should change only those bits which are necessary to the current task. Upon completion, the programmer should restore the original environment. Failure to adhere to this practice may be incompatible with present and future applications. 2-10 ROM BIOS Adapter Cards with System-Accessible ROM Modules The ROM BIOS provides a facility to integrate adapter cards with on board ROM code into the system. During the POST, interrupt vectors are established for the BIOS calls. After the default vectors are in place, a scan for additional ROM modules takes place. At this point, a ROM routine on the adapter card may gain control. The routine may establish or intercept interrupt vectors to hook themselves into the system. The absolute addresses hex C8000 through hex F4000 are scanned in 2K blocks in search of a valid adapter card ROM. A valid ROM is defined as follows: Byte 0: Byte 1: Byte 2: Hex 55 HexAA A length indicator representing the number of 512 byte blocks in the ROM (length/512). A checksum is also done to test the integrity of the ROM module. Each byte in the defined ROM is summed modulo hex 100. This sum must be 0 for the module to be deemed valid. When the POST identifies a valid ROM, it does a far call to byte 3 of the ROM (which should be executable code). The adapter card may now perform its power-on initialization tasks. The feature ROM should return control to the BIOS routines by executing a far return. ROM BIOS 2-11 Notes: 2-12 ROM BIOS Keyboard Encoding and Usage Encoding The keyboard routine provided by IBM in the ROM BIOS is responsible for converting the keyboard scan codes into what will be termed "Extended ASCII." Extended ASCII encompasses one-byte character codes with possible values of 0 to 255, an extended code for certain extended keyboard functions, and functions handled within the keyboard routine or through interrupts. Character Codes The following character codes are passed through the BIOS keyboard routine to the system or application program. A "-1" means the combination is suppressed in the keyboard routine. The codes are returned in AL. See Appendix C for the exact codes. Also, see "Keyboard Scan Code Diagram" in Section 1. Key Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Base Case Upper Case Ctrl Esc -1 Nul (000) Note 1 @ -1 # $ -1 4 -1 5 % A RS(030) 6 -1 7 & -1 8 * ( -1 9 -1 ) 0 US(031) + -1 = Del (127) Backspace (008) Backspace (008) -1 I--(Note 1) -1(009) DCl (017) q Q ETB (023) w W Esc 1 2 3 Esc ! Alt -1 Note Note Note Note Note Note Note Note Note Note Note Note -1 -1 Note Note 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Character Codes (Part 1 of 3) Keyboard Encoding 2-13 Key Number 18 19 20 21 22 23 24 25 26 27 28 29 Ctrl 30 31 32 33 34 35 36 37 38 39 40 41 42 Shift 43 44 45 46 47 48 49 50 51 52 53 54 Shift 55 56 Alt 57 58 Caps Lock 59 60 61 62 63 64 Base Case Upper Case Ctrl e r t y u i p E R T Y U I 0 P [ 1 ENQ (005) DC2 (018) DC4 (020) EM (025) NAK (021) HT (009) SI (015) DLE (016) Esc (027) GS (029 LF (010) -1 SOH (001) DC3 (019) EOT (004) ACK (006) BEL (007) BS (008) LF (010) VT (011) FF (012) -1 -1 -1 -1 FS (028) SUB (026) CAN (024) ETX (003) SYN (022) STX (002) SO (014) CR (013) -1 -1 -1 -1 (Note 1) -1 SP -1 Nul (Note 1) Nul (Note 1) Nul (Note 1) Nul (Note 1) Nul (Note 1) Nul (Note 1) a I 1 CR CR -1 a s d f -1 A S D F G H 9 h j k I J K L " ~ -1 -1 I \ z I Z X C V B N M < x c v b n m > / ? -1 -1 (Note 2) -1 SP -1 Nul (Note 1) Nul (Note 1) Nul (Note 1) Nul (Note 1) Nul (Note 1) Nul (Note 1) * Nul Nul Nul Nul Nul Nul -1 SP -1 (Note (Note (Note (Note (Note (Note 1) 1) 1) 1) 1) 1) Character Codes (Part 2 of 3) 2-14 Keyboard Encoding Alt Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 -1 -1 -1 -1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 -1 -1 -1 -1 -1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 -1 -1 -1 -1 -1 -1 SP -1 Nul (Note Nul (Note Nul (Note Nul (Note Nul (Note Nul (Note 1) 1) 1) 1) 1) 1) Key Number Base Case 65 66 67 68 69 Num lock 70 Scroll lock Nul Nul Nul Nul (Note (Note (Note (Note -1 -1 1) 1) 1) 1) Upper Case Nul Nul Nul Nul (Note (Note (Note (Note -1 -1 Ctrl 1) 1) 1) 1) Alt Nul (Note 1) Nul (Note 1) Nul (Note 1) Nul (Note 1) Pause (Note 2) Break (Note 2) Nul Nul Nul Nul (Note (Note (Note (Note -1 -1 1) 1) 1) 1) Notes: 1. Refer to "Extended Codes" in this section. 2. Refer to "Special Handling" in this section. Character Codes (Part 3 of 3) Keys 71 to 83 have meaning only in base case, in Num Lock (or shifted) states, or in Ctrl state. It should be noted that the shift key temporarily reverses the current Num Lock state. Key Number Num lock 71 7 72 8 73 9 Base Case Home (Note 1) t Alt Ctrl Clear Screen -1 (Note 1) -1 -1 Page Up (Note 1) -1 Top of Text and Home 74 - - - -- -- -- - ---- - ---- --- -1 -1 75 4 -(Note 1) -1 Reverse Word (Note 1) 76 5 -1 -1 -1 77 6 -(Note 1) -1 Advance Word (Note 1) 78 + + -1 -1 79 1 End (Note 1) -1 Erase to EOl (Note 1) ~ 80 2 81 3 Page Down (Note 1) 82 0 Ins 83 (Note 1) Del (Notes 1,2) -1 -1 -1 Erase to EOS (Note 1) -1 -1 Note 2 Note 2 Notes: 1. Refer to "Extended Codes" in this section. 2. Refer to "Special Handling" in this section. Keyboard Encoding 2-15 Extended Codes Extended Functions F or certain functions that cannot be represented in the standard ASCII code, an extended code is used. A character code of 000 (Nul) is returned in AL. This indicates that the system or application program should examine a second code that will indicate the actual function. Usually, but not always, this second code is the scan code of the primary key that was pressed. This code is returned in AH. Second Code 3 15 16-25 30-38 44-50 59-68 71 72 73 75 77 79 80 81 82 83 84-93 94-103 104-113 114 115 116 117 118 119 120-131 132 Function - Nul Character Alt Q, W, E, R, T, Y, U, I, 0, P Alt A, S, D, F, G, H, J, K, L Alt Z, X, C, V, B, N, M F1 to F1 0 Function Keys Base Case Home t -- Page Up and Home Cursor End l Page Down and Home Cursor Ins (Insert) Del (Delete) F11 to F20 (Uppercase F1 to F1 0) F21 to F30 (Ctrl F1 to F1 0) F31 to F40 (Alt F1 to F1 0) Ctrl PrtSc (Start/Stop Echo to Printer) Ctrl-(Reverse Word) Ctrl-(Advance Word) Ctrl End [Erase to End of Line (EOL)] Ctrl PgDn [Erase to End of Screen (EOS)] Ctrl Home (Clear Screen and Home) Alt 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, -, = (Keys 2-1 3) Ctrl PgUp (Top 25 Lines of Text and Home Cursor) Keyboard Extended Functions 2-16 Keyboard Encoding Shift States Most shift states are handled within the keyboard routine, transparent to the system or application program. In any case, the current set of active shift states are available by calling an entry point in the ROM keyboard routine. The following keys result in altered shift states: Shift This key temporarily shifts keys 2-13,15-27,30-41,43-53,55, and 59-68 to upper case (base case ifin Caps Lock state). Also, the Shift key temporarily reverses the Num Lock or non-Num-Lock state of keys 71-73,75,77, and 79-83. Ctrl This key temporarily shifts keys 3, 7, 12, 14, 16-28, 30-38,43-50, 55,59-71, 73, 75, 77, 79, and 81 to the Ctrl state. Also, the Ctrl key is used with the Alt and Del keys to cause the "system reset" function, with the Scroll Lock key to cause the "break" function, and with the Num Lock key to cause the "pause" function. The system reset, break, and pause functions are described in "Special Handling" on the following pages. Alt This key temporarily shifts keys 2-13, 16-25,30-38,44-50, and 59-68 to the Alt state. Also, the Alt key is used with the Ctrl and Del keys to cause the "system reset" function described in "Special Handling" on the following pages. ° The Alt key has another use. This key allows the user to enter any character code from to 255 into the system from the keyboard. The user holds down the Alt key and types the decimal value of the characters desired using the numeric keypad (keys 71-73, 75-77, and 79-82). The Alt key is then released. If more than three digits are typed, a modulo-256 result is created. These three digits are interpreted as a character code and are transmitted through the keyboard routine to the system or application program. Alt is handled internal to the keyboard routine. Keyboard Encoding 2-17 Caps Lock This key shifts keys 16-25, 30-38, and 44-50 to upper case. A second depression of the Caps Lock key reverses the action. Caps Lock is handled internal to the keyboard routine. Scroll Lock This key is interpreted by appropriate application programs as indicating use of the cursor-control keys should cause windowing over the text rather than cursor movement. A second depression of the Scroll Lock key reverses the action. The keyboard routine simply records the current shift state of the Scroll Lock key. It is the responsibility of the system or application program to perform the function. Shift Key Priorities and Combinations If combinations of the Alt, Ctrl, and Shift keys are pressed and only one is valid, the precedence is as follows: the Alt key is first, the Ctrl key is second, and the Shift key is third. The only valid combination is Alt and Ctrl, which is used in the "system reset" function. Special Handling System Reset The combination of the Alt, Ctrl, and Del keys will result in the keyboard routine initiating the equivalent of a "system reset" or "reboot." System reset is handled internal to the keyboard. 2-18 Keyboard Encoding Break The combination of the Ctrl and Break keys will result in the keyboard routine signaling interrupt hex 1A. Also, the extended characters (AL = hex 00, AH = hex 00) will be returned. Pause The combination of the Ctrl and Num Lock keys will cause the keyboard interrupt routine to loop, waiting for any key except the Num Lock key to be pressed. This provides a system- or application-transparent method of temporarily suspending list, print, and so on, and then resuming the operation. The "unpause" key is thrown away. Pause is handled internal to the keyboard routine. Print Screen The combination of the Shift and PrtSc (key 55) keys will result in an interrupt invoking the print screen routine. This routine works in the alphanumeric or graphics mode, with unrecognizable characters printing as blanks. Other Characteristics The keyboard routine does its own buffering. The keyboard buffer is large enough to support a fast typist. However, if a key is entered when the buffer is full, the key will be ignored and the "bell" will be sounded. Also, the keyboard routine suppresses the typematic action of the following keys: Ctrl, Shift, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins. Keyboard Encoding 2-19 Keyboard Usage This section is intended to outline a set of guidelines of key usage when performing commonly used functions. Function Comment KeY(5) Home Cursor Home Editors; word processors Return to outermost menu Home Menu driven applications Move cursor up Page up, scroll backward 25 lines and home Move cursor left Move cursor right Scroll to end of text Place cursor at end of line Move cursor down Page down, scroll forward 25 lines and home t PgUp _Key 75 - End ~ Pg Dn Full screen editor, word processor Editors; word processors Text, command entry Text, command entry Editors; word processors Full screen editor, word processor Editors; word processors Text, command entry Start/Stop insert text at cursor, shift text right in buffer Ins Delete character at cursor Del Text, command entry -Key 14 Text, command entry Destructive backspace Tab forward -t Text entry Tab reverse I- Text entry Clear screen and home Scroll up Scroll down Scroll left Scroll right Delete from cursor to EOL Exit/Escape Ctrl Home ,t -- Ctrl End Esc Command entry In scroll lock mode In scroll lock mode In scroll lock mode In scroll lock mode Text, command entry Editor, 1 level of menu, and so on Start/Stop Echo screen to printer Ctrl Prt Sc (Key 55) Any time Delete from cursor to EOS Advance word Ctrl PgDn Ctrl- Text, command entry Text entry Reverse word Ctrl- Text entry Window Right Ctrl- When text is too wide to fit screen Window Left Ctrl- When text is too wide to fit screen Enter insert mode Ins Line editor Keyboard - Commonly Used Functions (Part 1 of 2) 2-20 Keyboard Encoding Function Key(s) Comment Exit insert mode Ins Line editor Cancel current line Esc Command entry, text entry Suspend system (pause) Ctrl Num Lock Stop list, stop program, and so on Resumes on any key Break interrupt Ctrl Break Interrupt current process System reset Top of document and home cursor Standard function keys Secondary function keys Alt Ctrl Del Reboot Ctrl PgUp F1-F10 °° ° Shift F1-F1 Ctrl F1-F1 Alt F1-F1 Extra function keys Alt Keys 2-13 (1-9,0,-,=) Extra function keys Alt A-Z Ed itors, word processors Primary function keys Extra function keys if 10 are not sufficient Used when stickers are put along top of keyboa rd Used when function starts with same letter as one of the alpha keys Keyboard· Commonly Used Functions (Part 2 of 2) Keyboard Encoding 2-21 Function Carriage return Line feed Bell Home Cursor up Cursor down Cursor left Cursor right Advance one word Reverse one word Insert Delete Clear screen Freeze output Tab advance Stop execution (break) Delete current line Delete to end of line Position cursor to end of line Key ~ Ctrl~ Ctrl G Home .t -- Ctrl CtrlIns Del Ctrl Home Ctrl Num Lock -t Ctrl Break Esc Ctrl End End BASIC Screen Editor Special Functions Function Suspend Echo to printer Stop echo to printer Exit current function (break) Backspace Line feed Cancel line Copy character Copy until match Copy remaining Skip character Skip until match Enter skip mode Exit insert mode Make new line the template String separator in REPLACE End of file in keyboard input Key Ctrl Num Lock Ctrl PrtSc (Key 55 any case) Ctrl PrtSc (Key 55 any case) Ctrl Break Key 14 Ctrl .--J Esc F10r_ F2 F3 Del F4 Ins Ins F5 F6 F6 DOS Special Functions 2-22 Keyboard Encoding BIOS Cassette Logic Software Algorithms - Interrupt Hex 15 The cassette routine will be called by the request type in AH. The address of the bytes to be read from or written to the tape will be specified by ES:BX and the number of bytes to be read or written will be specified by ex. The actual number of bytes read will be returned in DX. The read block and write block will automatically tum the cassette motor on at the start and off at the end. The request types in AH and the cassette status descriptions follow: Request Type AH =0 AH = 1 AH =2 AH =3 Function Turn Cassette Motor On Turn Cassette Motor Off Read Tape Block Read CX bytes into memory starting at Address ES:BX Return actual number of bytes read in DX Return Cassette Status in AH Write Tape Block Write CX bytes onto cassette starting at Address DS:BX Return Cassette Status in AH Cassette Status AH AH AH AH AH =00 =01 =02 =04 =80 Description No Errors Cyclic Redundancy Check (CRC) Error in Read Block No Data Transitions No Leader Invalid Command Note: The carry flag will be set on any error. Keyboard Encoding 2-23 Cassette Write The write-block routine writes a tape block onto the cassette tape. The block is described in "Data Record Architecture" later in this section. The write-block routine turns on the cassette drive motor and a synchronization bit (0) and then writes the leader (256 bytes of all 1's) to the tape. Next, the routine writes the number of data blocks specified by CX. After each data block of 256 bytes, a 2-byte cyclic redundancy check (CRC) is written. The data bytes are taken from the memory location pointed at by ES. The write-byte routine disassembles and writes the byte a bit at a time to the cassette. The method used is to set Timer 2 to the period of the desired data bit. The timer is set to a period of 1.0 millisecond for a 1 bit and 0.5 millisecond for a 0 bit. The timer is set to mode 3, which means the timer outputs a square wave with a period given by its counter register. The timer's period is changed on the fly for each data bit written to the cassette. If the number of data bytes to be written is not an integral mUltiple of 256, then, after the last desired data byte from memory has been written, the data block is extended to 256 bytes of writing multiples of the last data byte. The last block is closed with two CRC bytes as usual. After the last data block, a trailer consisting of four bytes of all 1 bits is written. Finally, the cassette motor is turned off, if there are no errors reported by the routine. ~250f.1s-+l Zero Bit 1414--- 500 f.1S ----.t.1 --JI One Bit l...-_ _ _ _ _ _ _ _ ~14~--------1000f.1S--------~·1 2-24 BIOS Cassette Cassette Read The read-block routine turns on the cassette drive motor and then delays for approximately 0.5 second to allow the motor to come up to speed. The read-block routine then searches for the leader and must detect all 1 bits for approximately 1/4 of the leader length before it can look for the sync (0) bit. After the sync bit is detected, the sync byte (ASCII character hex 16) is read. If the sync byte is read correctly, the data portion can be read. If a correct sync byte is not found, the routine goes back and searches for the leader again. The data is read a bit at a time and assembled into bytes. After each byte is assembled, it is written into memory at location ES:BX and BX is incremented by 1. After each multiple of 256 data bytes is read, the CRC is read and compared to the CRC generated. If a CRC error is detected, the routine will exit with the carry flag set to indicate an error and the status of AH set to hex 01. DX will contain the number of bytes written memory. The time of day interrupt (IRQO) is disabled during the cassetteread operation. BIOS Cassette 2-25 Data Record Architecture The write-block routine uses the following format to record a tape block onto a cassette tape: Motor Off Motor On Component Description Leader Sync Bit Sync Byte Data Blocks CRC 256 Bytes (of All 1 's) One 0 Bit ASCII Character Hex 16 256 Bytes in Length 2 Bytes for each Data Block Data Record Components Error Recovery Error recovery is handled through software. A eRe is used to detect errors. The polynomial used is G(X) = X16 + X12 + Xs + 1, which is the polynomial used by the synchronous data link control interface. Essentially, as bits are written to or read from the cassette tape, they are passed through the eRe register in software. After a block of data is written, the complemented value of the calculcated eRe register is written on the tape. Upon reading the cassette data, the eRe bytes are read and compared to the generated eRe value. If the read eRe does not equal the generated eRe, the processor's carry flag is set and the status of AH is set to hex 01, which indicates a eRe error has occurred. Also, the routine is exited on a eRe error. 2-26 BIOS Cassette APPENDIX A: ROM BIOS LISTINGS Page Line Number A-2 A-2 A-2 A-2 A-5 A-21 12 34 66 74 229 1493 A-22 A-26 A-36 A-46 A-47 1551 1818 2426 3201 3327 A-73 A-73 A-74 A-80 A-82 A-84 5177 5208 5253 5769 5903 6077 Fixed Disk I/O Interface ................ A-87 Boot Strap Loader ...................... A-92 1 399 System ROM BIOS Equates .............................. . 8088 Interrupt Locations ............... . Stack ................................ . Data Areas ........................... . Power-On Self-Test .................... . Boot Strap Loader ..................... . I/O Support Asynchronous Communications (RS-232C) ......................... . Keyboard .......................... . Diskette ............................ . Printer ............................. . Display ............................ . System Configuration Analysis Memory Size Determination .......... . Equipment Determination ............. . Cassette I/O Support ................... . Graphics Character Generator ........... . Time of Day .......................... . Print Screen .......................... . Fixed Disk ROM BIOS System BIOS A-I LOC OBJ LINE SOURCE $UTlE(BIOS t=OR IBM PERSONAL COHPUTER) ; --------------- --------------------- -- ------------- -- ---- ------THE BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH SOFTWARE INTERRUPTS ONLY. THE LISTINGS NOT FOR ARE INCLUDED REFERENCE. ABSOLUTE ANY ADDRESSES PRESENT IN ONL. Y fOR COMPLETENESS. APPLltATIONS WHICH ADDRESSES WITHIN THE REFERENCE CODe SEGMENT VIOLATE THE STRUCTURe AND DESIGN OF BIOS. 10 11 ; ---------------------------------------------------------------- 12 ~ ---------------------------------------- 13 EQUATES 1. 0060 0061 15 PORT_A 16 PORT_B 0062 0063 17 PORT_C 18 19 CMD_PORT 20 INTAOI 0020 0021 0020 INTAOO 21 EO! 0040 22 TIMER 0043 23 TIM_CTL 0040 24 TIHERO 0001 0006 25 TMINT 26 DMA06 EOU EOU EOU 60H j 61H ; 62:55 PORT B ADDR 62H , 62:55 PORT C ADDR EOU EOU 63H 20H ; 62:59 PORT EOU EOU EOU EOU EOU 21H i EOU EOU EOU 62:55 PORT A AoDR 82:59 PORT 20H 40H 43H ; 8253 TIMER CONTROL PORT ADDR 6253 TIMER/CNTER 0 PORT ADDR 40H j 01 ; TIMER 0 INTR RECVO MASK o. ; DMA STATUS REG PORT ADDR 00 ; DMA CHANNEL 0 ADDR REG PORT ADDR 0000 27 DMA 0540 2. MAXj'ERIOO 29 MIN_PERIOD 30 KBD_IN 31 32 33 KBDINT KB_DATA 34 35 ; ....--------------------------------------6088 INTERRUPT LOCAnONS 36 ; ---------------------------------------ABSO SEGMENT AT 0 0410 0060 0002: 0060 0061 KB_CTL EOU EOU EOU EOU EOU EOU STG_LOCO 0008 37 38 39 0008 40 NHI_PTR 0014 0014 0020 41 0020 44 INT_ADDR LABEL 0020 45 INT_PTR LABEL 0040 46 .7 48 49 50 51 0000 0040 0074 0074 0060 0060 42 LABEL ORG LABEL INT5_PTR 0078 52 0078 53 007C 007C 54 VIDEO_IHT PARM_PTR BASIC_PTR DISK_POINTER 410H 60H j KEYBOARD INTR MASK j KEYBOARD SCAN CODE PORT 61H i CONTROL BITS FOR KB SENSE DATA BYTE 2" WORD 5'4 LABEL WORD ... WORD DWORD ORG 10H*4 LABEL WORO ORG lOH*4 LABEL aWaRD ORG 18H*4 ; POINTER TO VIDEO PARMS ENTRY POINT FOR CASSETTE BASIC WORD j ORG 01EH*4 ; INTERRUPT 1EH LABEL OWORD LABEL "". 01FH*4 DWORD 55 56 EXT_PTR lABEL 0100 11?1 0102 ?11? 57 IO_ROM_INIT 58 IO_ROM_SEG 0400 0400 59 60 DATA_AREA 0400 61 DATA_WORD 7COO 62 ORG 7COOH 7COO 63 BOOT_LOCN LABEL 6. "R ABSO ENOS 0100 J KEYBOARD DATA IN ADOR PORT 60H 02 ORG ORG 43 S40H ORG J LOCATION OF POINTER J POINTER TO EXTENSION 04QH*4 ow ow ; ROUTINE j ORG 400H LABEL BYTE LABEL WORD OPTIONAL ROM SEGMENT I ABSOLUTE LOCATION OF DATA SEGMENT 65 66 I --- --------------------- - - - - -- ------- --- - --- - - - - - -- ----- 67 0000 1128 0100 STACK -- USED DURING INITIALIZATION ONLY 68 I --- --------------- - -- ----- - - - - -- ---- - --- - - - - - - - - -- - - - --- 69 STACK 70 SEGMENT AT 30H OW 128 OUPI? I WORD 71 TDS LABEL 72 STACK ENOS 7. A-2 74 75 ; --- ------ -- - - --- - - --- ------- --- - ---- ---ROM BIOS DATA AREAS 76 77 ; ---------------------------------------DATA SEGMENT AT 40H System BIOS LaC OBJ LINE 0000 (4 78 0008 (4 7. 0010 ???? 80 0012 ?? 81 MFG_TST 0013 ???? 82 MEMORY_SIZE 0015 7??? 83 IO_RAM_SIZE 84 ; 85 0017 ?? 86 87 88 89 SOURCE ow 4 DUP(?) I ADDRESSES OF RS232: ADAPTERS it DUP(?) I ADDRESSES OF PRINTERS I INSTALLED HARDWARE OW D. ; INITIALIZATION FLAG ow ow I MEMORY SIZE IN K BYTES I MEMORY IN I/O CHANNE L ------------------------------ --- ------KEYBOARD DATA AREAS 1---------------------------------------- KBJLAG DB ; ----- SHIFT FLAG EQUATES WITHIN KBJLAG .0 ooao 0040 91 92 INS_STATE EQU 80H CAPS_STATE EQU 40H I CAPS LOCK STATE HAS BEEN TOGGLED NutCSTATE EQU 20H ; HUH LOCK STATE HAS BEEN TOGGLED I INSERT STATE IS ACTIVE SCROLL_STATE EQU lOH J SCROLL LOCK STATE HAS BEEN TOGGLED 0010 9'94 oooa 95 Al T_SHIFT EQU 08H ; ALTERNATE SHIFT KEY DEPRESSED 0004 96 97 ClL_SHIFT EQU 04H I CONTROL SHIFT KEY DEPRESSED 0002 lEFT_SHIFT EQU 0001 98 RIGHT_SHIFT EQU O2H O1H I RIGHT SHIFT KEY DEPRESSED 0018 ?? 100 0020 9' ; LEFT SHIFT KEY DEPRESSED ; SECOND BYTE OF KEYBOARD STATUS DB 101 0080 0040 0020 10' 10' 104 IS DEPRESSED INS_SHIFT EQU EQU 80H 40H I INSERT KEY CAPS_SHIFT NUtCSHIFT EQU 20H ; NUtl LOCK KEY IS DEPRESSED I CAPS LOCK KEY IS DEPRESSED 0010 105 SCROLL_SHIFT EQU lOH ; SCF LAST_VAL DB ; LAST INPUT VALUE 174 ; ---------------------------------------- 175 TIMER DATA AREA 17. D06t 1111 006E ???? 0070 ?1 171 TIMER_lOW 178 17. 18. TIMER_HIGH 181 182 I.' I.' 185 TIMER_OFl DW DW DB ;COUNTS_SEC EQU ; COUNTS_MIN EQU 1092 ; COUNTS_HOUR EQU 65543 ;COUNTS_DAY EQU 1573040 0071 11 0072 111? 0074 1111 0076 ???? 0078 (4 J HIGH WORD OF TIMER COUNT , TIMER HAS ROLLED OVER SINCE LAST READ 18 = 1800BOH ; - - --- --- - - ------ - -- - ----- -- -- - -- - - ------ 186 187 ; LOW WORD OF TIMER COUNT SYSTEM DATA AREA ; ------------ ------ -------------- - -- -- - -BIOS_BREAK DB J BIT 7 188 18. RESET]lAG 190 191 ; ---------------------------------------FIXED DISK DATA AREA 192 19> J ---------------------------------------- DW ; WORD BREAK KEY WAS DEPRESSED IF KB RESET UNDERWAY DW DW I •• 195 196 J -------.-------------------------------PRINTER AND RS232 TIMEOUT CTRS : 197 ; PRINT_ TIH....0UT 198 = 1 IF = 1234H - --------------------------------------DB 4 DUP(?) ; PRINTER TIME OUT COUNTER '" DUP(?) J RS232 TIME OUT COUNTER I 007C (4 I •• 200 201 2.2 0080 ???? 0082 1111 0000 ?? 2.3 2.4 EXTRA KEYBOARD DATA AREA ------------------ ------------- --------- ; BUFFER_START OW DW 205 DATA 206 207 J ------------------ - ---- ----------------- 208 209 i ------------ ------ - ----- ---------------XXDATA SEGHENT AT SOH ". 211 212 213 214 215 216 A-4 ; ---------- ---------- ------ -------------- ENDS EXTRA DATA AREA DB ENDS 1---------------------------------------VIDEO DISPLAY BUFFER ,---------------------------------------VIDEO_RAM SEGMENT AT oeaOOH System BIOS LaC OBJ LINE SOURCE 0000 0000 0000 (16384 217 REGEN REGENW 0000 (57344 218 219 2: 21 222 223 224 225 LABEL LABEL BYTE WORD DB 16384 CUP!? J 'NDS ; ------ -- - -- - - -- -- -------- --- --- --- -----ROM RESIDENT CODE 1---------------------------------------CODE SEGMENT AT OFOOOH ~ DB 57344 aUPI? 1 DB '1501476 COPR. IBM FILL LOWEST 56K 226 EOOD 31353031343736 227 1~~1' ; COPYRIGHT NOTICE 20434F50522EZO 49424020313938 32 228 2: 2: 9 1--- --------------- - - ---- ----- ---- -- - - - --------- - -- --- --- - - -- - --- 230 231 232 233 234 235 E016 DIED 236 237 238 239 INITIAL RElIABILITY TESTS -- PHASE 1 ;---------------------------------------------------------------ASSUME CS:COOE ,SS:CODE .ES:ABSO .DS:DATA 1---------------------------------------DATA DEFINITIONS ; ---------------------------------------C1 OW Cll ; RETURN ADDRESS J -- - --- --------- - - - - -- -- ------ ---- - - - - - ------- - - - -- - ---------------- - ---THIS SUBROUTINE PERFORMS A READ/WRITE STORAGE TEST ON 240 241 A 16K BLOCK OF STORAGE. 1 ENTRY REQUIREMENTS: 242 ES = 243 OS = ADDRESS ADDRESS OF STORAGE SEGMENT BEING TESTED OF STORAGE SEGMENT BEING TESTED 244 WHEN ENTERING AT STGTST_CNT, CX MUST BE LOADED WITH 245 THE BYTE COUNT. 246 ; EXIT PARAMETERS: ZERO FLAG:: 0 IF STORAGE ERROR {DATA COMPARE OR PARITY CHECK. AL ;: 0 DENOTES A PARITY CHECK. ELSE AL;:XOR'ED BIT 247 248 Z49 PATIERN OF THE EXPECTED DATA PATTERN VS THE 250 ACTUAL DATA. READ. 251 252 AX,BX,CX,DX.DI, AND SI ARE ALL DESTROYED. ; -- - ----- ------- - - ---- - -- ----- - ------ - - - - - - - -- - - - - - - -- - ------------------ 253 E018 254 PRDC NEAR E018 890040 255 MOV CX,4000H ; SETUP CNT TO TEST A 16K BLK EOIB EOIB Fe 256 STGTST_CNT: 257 ClD EDIt 8809 258 I10V BX,ex ; SAVE BYTE CNT (4K FOR YIDEO OR 16K) fOIE BBAAAA 259 MOV AX,OAAAAH ; GET DATA PATTERN TO WRITE EOZI BA55FF 260 MaY' DX,OFF55H ; SETUP OTHER DATA. PATTERNS TO USE E024 2BFF 261 SUB 01,01 ; 01 E026 f3 262 REP STOSB ; WRITE STORAGE LOCATIONS DI ; POINT TO LAST BYTE JUST WRITTEN STGTST i E027 AA , C3: E028 263 E028 4F 264 DEC E029 FD 265 STD SET oIR flAG TO INCREMENT = OFFSET 0 RELATIVE TO ES REG STSOI I SET OIR FLAG TO GO BACKWARDS C4: EOlA 266 EOlA 8BF7 267 foze 86ce 268 f02E 269 EDa AC 270 LOOSB E02F 32C4 271 XOR .H,AH E031 7525 272 JNE C7 ; E033 BAC2 273 MOV AL,OL I GET NEXT DATA PATTERN TO WRITE E035 AA 274 STOSB E036 E2F6 275 LOOP C5 , AND AH,AH I ENDING ZERO PATTERN WRITTEN TO STG l' C6X I YES - RETURN TO CALLER WITH Al::O MOV SI,DI NOV CX,BX C5: ; SETUP BYTE CNT I INNER TEST LOOP ; READ OLD TST BYTE FROM STORAGE [SI)+ ; DATA READ AS EXPECTED? NO - GO TO ERROR ROUTINE I WRITE INTO LOCATION JUST READ [011+ DECREMENT BYTE COUNT AND LOOP CX 276 E038 22E4 277 E03A 7416 278 JZ E03e BAEO 279 MDV AH,AL E03E e6F2 280 XCHG DH.OL ; MOVE NEXT DATA PATTERN TO OL E040 22E4 281 AND AH.AH I READING ZERO PATTERN THIS PASS? E042 7504 282 JHZ C6 I CONTINUE TEST SEqUENCE TILL ZERO DATA. E044 8AD4 283 MDV DL,AH E046 EBED 284 JMP C3 'ooa 285 ; SETUP NEW VALUE FOR COMPARE ELSE SET ZERO FOR END READ PATTERN ; ANO MAKE FINAL BACKWARDS PASS C6: System BIOS A-5 LOC OBJ LINE E048 Fe 286 287 288 CLD E050 EB06 289 290 291 292 E052 293 E049 47 E04A 74DE E04C 4F E040 8AOI00 SOURCE ; SET OIR FLAG TO GO FORWARD INC DI JZ C4 • SET POINTER TO BEG lOCATION ; READMRITE fORWARO IN STG DEC OI ; ADJUST POINTER MOV OX.OOOOlH I SETUP 01 fOR PARITY BIT JMP C3 ; REAO/WRITE BACKWARD IN STG ; AHO 00 FOR END C6X: E052 E462 294 IN AL.PORT_C ; 010 A PARITY ERROR OCCUR ? E054 24CO 295 ANIl AL.OCOH 1 ZERO FLAG WILL BE OFF PARITY ERROR E056 BODO 296 MOV AL.OOOH 1 AL=O DATA COMPARE OK EOS8 297 E058 Fe 298 CLO E059 C3 299 RET 300 I 30 302 303 C7: STGTST ; SET DEFAULT DIRCTN flAG BACK TO INC EtilP 1---------------------------------------------------------------8088 PROCESSOR TEST ; DESCRIPTION 304 VERIFY 8088 FLAGS. REGISTERS AHO COHOITIONAL JUMPS 1---------------------------------------------------------------- E05B 305 306 307 308 309 E05B FA E05B E058 ASSUME RESET tS :CODE .DS:NOTHING. ES: NOTHING,SS:NOTHIHG DRG OE05BH LABel FAR START: 310 tLI EOSC 8405 311 MOV EOSE 9E 312 SAHF E05F 734C 313 JNC ERROl ; GO TO ERR ROUTINE IF CF NOT SET E061 754.4. 314 JNZ ERROl I GO TO ERR ROUTINE IF ZF NOT SET E063 7848 315 JHP ERROl ; GO TO ERR ROUTINE IF PF NOT SET ERROl ; GO TO ERR ROUTINE IF SF NOT SET CL.S ; LOAD tNT REG WITH SHIFT tNT AH.Cl ; SHIFT AF INTO CARRY BIT POS f065 7946 316 JNS ED67 9F 317 LAHF E06S BIOS 318 MOV E06A D2EC 319 SHR I DISABLE INTERRUPTS AH.OD5H I SET SF. CF. ZF. AND AF FLAGS ON I LOAD FLAG IMAGE TO AH EObC 733F 320 JNC ERROl ; GO TO ERR ROUTINE IF AF NOT SET ED6E 6040 321 MOV AL,40H ; SET THE OF F LAG ON E070 ODED 322 SHL AL,I i SETUP FOR TESTING f072 7139 JNO ERROl ; GO TO ERR ROUTINE IF OF NOT SET XOR AH.AH ISETAH=O f076 9E 323 324 325 SAHF E077 7634 326 JBE ERROl ; GO TO ERR ROUTINE IF CF ON E074 32E4 i CLEAR SF. Cf. ZF. ANtI Pf ; OR TO TO ERR ROUTINE IF ZF ON 327 E079 7832 328 JS ERROl ; GO TO ERR ROUTINE IF SF ON E07B 7A30 329 JP ERROl ; GO TO ERR ROUTINE IF PF ON f070 9F 330 LAHF E07E 6105 331 MOV CL,S I LOAD tNT REG WITH SHIFT CNT E060 02EC 332 SHR AH,CL ; SHIFT 'AF' INTO CARRY BIT POS E082 7229 333 334 335 336 Je E084 00E4 E086 702:5 337 i----- 338 E08B F9 339 340 341 Eoec 342 ED86 B8FFFF LOAD F LAG IMAGE TO AH ERROl ; GO TO ERR ROUTINE IF ON SHL AH,l I CHECK THAT 'OF' IS CLEAR JO ERROl ; GO TO ERR ROUTINE IF ON READ/WRITE THE 8088 GENERAL AND SEGMENTATION REGISTERS WITH ALL ONE'S AND ZEROES'S. MOV AX.OFFFFH I SETUP ONE'S PATTERN IN AX I WRITE PATTERN TO ALL REGS TSTlA STC C8: Eoac 8E06 343 HOV DS.AX EoeE 8coe 344 HOV BX.OS E090 SEC3 345 MOV ES.BX E092 eCCI CX,ES 346 MOV E094 SED! 347 HOV sS,ex E096 8e02: 348 HOV DX.5S E096 8BE2 349 350 HOV SP,DX E09.4. 8BEt MOV BP,SP E09C BBfS 351 HOV SI.BP E09E SBFE HOV DI.SI JNC C9 AX.DI I XQR JNZ ERROl I NO - GO TO ERR ROUTINE EDA7 EBE3 352 353 354 355 356 357 EOA9 358 EOA9 DBC7 359 EDAB 7401 360 361 ERROl: 362 1-------------------------------------------------------- EOAO 7307 EOA2 33C7 EO.6.4 7507 fOA6 Fe EDAD F4 A-6 I PATTERN HAKE IT THRU ALL REGS CLC JHP C8 OR JZ AX.DI C9: System BIOS I HLT C10 TsnA I ZERO PATTERN MAKE IT THRU? I YES - GO TO NEXT TEST I HALT SYSTEM LaC OBJ LINE SOURCE 363 364 ROS CHECKSUM TEST I I DESCRIPTION A CHECKSUM IS DONE FOR THE 8K ROS HOOUlE 36' 366 EOAE CONTAINING POD ANO BIOS. 367 1-------------------------------------------------------- 366 CIa: ; ZERO IN .l.l ALREADY 369 OUT OAOH,AL I 371 OUT 63H,AL I INITIALZE DMA PAGE REG 372 MOV OX.30SH EOAE E6AO 370 EOBO E683 EOBZ BA0803 EOB5 EE 373 OUT OX,AL DISABLE Nt1I INTERRUPTS I DISABLE COLOR VIDEO EOB6 FEeD 374 INC Al EOB8 8288 37' I10V Cl,DBBH EOBA EE 376 OUT OX.At I DISABLE B/W VIDEO,EN HIGH RES EOBB 8099 377 MOV AL.99H I EOBO E663 376 OUT tHO_PORT,AL I WRITE 8255 tHO/MODE REG EOSF BOFt 379 MOV SET 8255 A.e-INPUT .S-OUTPUT AL,OFtH ; DISABLE PARITY CHECKERS AND EOCI E661 360 OUT PORT_B,AL I Eoe3 8CC8 361 MOV AX,es ; SETUP SS SEG REG EOt5 8EOD 382 MOV 55,AX Eoe7 8E08 383 MOV OS,AX 384 Eoe9 B7EO 38' 386 EOCB 6C16EO 387 EDCE E9780B 388 EOOI 389 EOOI 750.4. 390 391 I SET UP QATA SEG TO POINT TO ASSUME SS:CODE MOV BH.OEOH ; SETIJP STARTING ROS ADDR (EOOOO) MOV SP,OFFSET Cl I SETUP RETURN ADDRESS JMP ROS_CHECKSUM JNE ERROl ell: I HALT SYSTEM IF ERROR 1---------------------------------------------------------------82:37 DHA INITIALIZATION CHANNEL REGISTER TEST I DESCRIPTION VERIFY THAT TINER 1 FUNCTIONS OK. IomITEI'REAO THE CURRENT ADDRESS AND WORD 394 DISABLE THE 8237 DHA CONTROLLER. 39' 396 COUNT REGISTERS fOR ALL CHANNELS. 397 START DHA FOR MEMORY REFRESH. 396 RON ADDRESS I 392 393 GATE SNS SWS,CASS MOTOR OFF INITIALIZE AND 1---------------------------------------------------------------- E003 8004 399 MOV AL,04 EOD5 E608 400 OUT OMAoe,Al ; DISABLE DHA CONTROLLER 401 402 ; ----- VERIFY THAT TIMER 1. FUNCTIONS OK 403 E007 6054 404 MOV Al.54H E009 E643 40' 406 OUT TIMER+3.AL EOOS 8ACI MaV AL,CL OUT TIMER+l,AL EODO E641 407 EODF 408 EODF 8040 C12: I SEl TINER I, LSB,MOOE 2: I SET INITIAL TIMER CNT TO 0 I TIMERl_BITS_DN 409 MaV EOEI E643 410 OUT TIHER+3.AL Eon 80FBFF 411 CMP BL.OFFH I YES - SEE IF ALL BITS GO OFF EOE6 7407 412 JE C13 ; TIMERl_BITS_OFF EOE8 E441 413 IN AL, TIMER+1 I READ TIMER 1 COUNT EOEA OAD8 414 OR 8L,AL ; ALL BITS ON IN TIMER EOEC E2Fl lOOP C12 EOEE ,4 41' 416 EOEF 417 EOEF 8AC3 418 EOFl 2BC9 EOF3 E641 EOF5 421 EOF5 8040 422 AL.40H HlT I LATCH TIMER 1 COUNT ; TIHERI_BITS_ON I C13: TIMER 1 FAILURE. HALT SYS I TIHERl_BITS_OFF MaV AL,BL 419 SUB CX,CX 420 OUT TIMER+l.AL MOV AL,40H TIMER+3.AL C14: I SET TIMER 1 CNT I TIMER_LOOP EOF7 E643 423 OUT EOF9 90 424 NOP EOFA 90 425 NOP EOFB E441 426 I LATCH TIMER 1 COUNT I DELAY FOR TIMER IN AL, TIMER+l EOFO 2208 427 AND BL,AL EOFF 7403 426 JZ EIOI E2F2 429 LOOP C1' C14 EI03 F4 430 HlT I READ TIMER 1 COUNT I GO TO WRAP_DHA_REG ; TIMER_LOOP I TIMER ERROR - HALT SYSTEH 431 432 1----- INITIALIZE TIHER 1 TO REFRESH HEMORY 433 EI04 434 EI04 B012 435 MOV AL.18 I EI06 E641 436 OUT TIMER+l,AL ; WRITE TIMER 1 CNT REG EI06 E600 437 OUT DMA+ODH,AL ; SEND MASTER CLEAR TO DMA CIS: I WRAP_DHA_REG SETUP DIVISOR FOR REFRESH 438 System BIOS A-7 LaC OBJ LINE SOURCE 439 1----- WRAP OHA CH~ELS ADDRESS AND COUNT REGISTERS 440 EIOA BOFF EIOC 441 EIOC 8A08 44> 44, HOY At,OFFH ;0 WRITE PATTERN FF TO ALL REGS HOY I SAVE PATTERN FOR COMPARE C16: flOE 8AFS 444 MOY BL,Al BH,AL E110 890800 44S HOY eX,6 I SETUP lOOP tNT E113 l8D2 44. sue oX,OX ; SETUP 110 PORT AOCR OF REG (0000) EllS 447 EllS EE 448 OX,Al ; WRITE PATTERN TO REG, LSB £116 50 449 PUSH AX E1l7 EE 450 OUT DX.AL El18 880101 451 HOY E1l8 EC 4,. IN EUC EllE EllF E121 8AEO 453 MOY EC 3806 7401 454 IN 455 C"P AX.OIOIH AL,OX AH,Al AL,DX aX,AX 45. J' HLT e17: OUT C18 I MSB OF 16 BIT REG ; AX TO ANOTHER PAT BEFORE RD ; READ 16-BIT DHA CH REG, LSB ; SAVE lSB OF 16-BIT REG I READ "5B OF OMA CH REG I PATTERN READ AS WRITTEN? I YES - CHECK NEXT REG E123 F4 457 £124 E124 42 458 I NO - HALT THE SYSTEM INC OX E125 E2EE 4.0 LOOP C17 I SET I/O PORT TO NEXT CH REG ; WRITE PATTERN TO NEXT REG E127 FEtD 4.1 INC AL I SET PATTERN TO 0 £129 74El 4.' JZ C1. I WRITE TO CH.t.t+-IEl REGS C18: 459 I NXT_DMA_CH 463 4.4 ;----- INITIALIZE AND START OMA FOR MEMORY REFRESH. 4.5 E128 8EOB 4 •• HOY OS,BX E120 SEC3 4.7 HOY ES,6X ASSUHE os: .1.650. ES:ABSO 4.8 ; SET UP ABSO INTO as AtIl ES 4.9 El2:F BOFF 470 MOY At.OFFH E131 E601 471 OUT DHA+l,At E133 50 472 PUSH AX E134 E601 l SET CNT OF 64K FOR RAM REFRESH 473 OUT DMA+l.AL E136 B20B 474 HOY DL,OBH E138 BOS8 475 HOY At.058H J SET DHA MOOE,CH O.READ,AUTOINT E13A EE 47. OUT OX,AL I WRITE OMA MODE REG El3B BOOO 477 MOV AL.O ; ENABLE DMA CONTROLLER E130 £608 478 DMA+8.AL ; E13F 50 479 PUSH AX E140 E60A 480 OUT DHA+I0.AL El42 B103 481 MOY CL.3 E144 8041 El46 48' 483 El46 EE 484 E147 FECO 485 E149 E2FB 48. 487 OUT HOY AL,41H OUT DX.AL I OX=0006 S~TUP OMA CQMHAHD REG ; ENABLE CHANNEL 0 FOR REFRESH 1 SET HODE FOR CHANNE L 1 CI8A: INC AL LOOP CIBA I POINT TO NEXT CHANNEL 488 1- - - - - -- - --- --- - - - - -- -- - - - -------- --- -- - ------ --- ----- -- -- -- -- -.BASE 16K REAOIWRITE STORAGE TEST I 48. I DESCRIPTION 4'0 491 WRITEIREAD/vERIFY DATA PATTERNS FF.55.AA,Ol. AND 00 49' INITIALIZE THE B259 INTERRUPT CONTROLLER CHIP FOR 4'3 494 TO 1ST 16K OF STORAGE. VERIFY STORAGE ADDRESSABILITY. CHECKING MANUFACTURING TEST 2 MODE. ; ----------.----_._---- .. ---------------------------------------- 495 49. j----- DETERMINE MEMORY SIZE AND FILL MEMORY WITH DATA 497 E14B BA1302 498 HOY E14E B001 4'9 500 HOY AL.OlH OUT DX.Al ElSI BS2E72:04 E150 EE DX,0213H 1 ENABLE EXPANSION BOX 501 HOY BP ,DATA_WORD{ OFFSET RESET_F LAG] J SAVE 'RESET_flAG' IN SP E155 BIFD3412 50, C"P BP.1234H ; WARM START? E159 740A 503 CIBB ; BYPASS STG TST. ElSB BC41F090 504 J" HOY E15f E986fE 505 JMP STGT5T E162 50. J' HLT CIBS SUB CI.DI E162 7401 507 E164 f4 508 E165 509 E165 2BFF 510 5P.OFF5ET C2 C24: ; PROCEED IF 5TGTST OK ; HALT IF NOT CIBS: E167 E460 511 IN AL,PORT_A I DETERMINE BASE RAM SIZE E169 240C 5" 513 AND AL,OCH I ISOLATE RAM SIZE SWS E168 0404 ADD AL, 4 I CALCULATE MEMORY SIZE E16D BlOC 514 MOY CL, 12 A-8 System BIOS LOC OBJ LINE E16F 03£0 515 SOURCE SHL AX. CL EI7l 88C& 516 HOV ex. E173 Fe E174 517 518 OLD E174 AA E175 E2FD 51' 520 fl77 892E7204 521 522 523 524 El7B SOFa El7D E661 AX , SET DIR FLAG TO INtR C19: SIOSB lOOP HOV ; FILL BASE RAM WITH DATA ; LOOP TIL ALL ZERO C19 OATA_WORO[OFFSET RESETJLAGJ.BP 1----- DETERMINE 10 CHANNEL RAM SIZE 525 MOV AL,OF8H 52. 527 OUT PORT_B,AL , ENABLE SWITCH 5 ; READ SWITCHES 528 IN AND AL,PORT_C El81 2401 AL.OOOOOOOIB ; ISOLATE SWITCH 5 E183 BlOC 52. MOV CL,l20 E17F E462 ROL AX,CL EI87 BOFt 5Jl HOV AL,OFCH E189 E661 532 OUT PORT_B,AL E 188 E462: 533 IN AL,PORT_C E185 03CO EleD 240F 530 AND I DISABLE SW. 5 AL,OFH fIeF OAC4 534 535 OR AL,AH ; COMBINE SWITCH VALUES fI9l BAD8 536 HOV BL,AL ; SAVE E193 6420 537 53B MOV AH,32 EI95 F6E4 E197 A31504 E19A 7418 53' 540 , CALC. LENGTH HUL AH HOV DATA_WORD I OFFSET IO_RAM_SIZE I,AX JZ 021 E19C BADOIO 541 HOV DX,IOOOH E19F BAED 542 543 544 545 546 547 548 MOV AH,AL MOV AL,O MOV ES,OX EIAI BODO EtAJ EtA] 8EC2 ElAS 890080 flAB 2BFF ElAA F3 ,SAVE IT , SEGMENT FOR I/O RAM C20: FILL..IO: HOV eX.BOOOH SUB 01,01 REP STOSB FILL 32K BYTES ElAB AA ElAC 81C20008 54' ADO OX,BOOH ElBO FEes 550 DEC BL E182 75EF 551 JNZ 020 ; NEXT SEGMENT VALUE 552 553 ;---------------------------------------------------------------INITIALIZE THE 8259 INTERRUPT CONTROLLER CHIP EIB4 554 555 C21: i ------------------------------------------ ---------------------- EIB4 8013 55. ElB6 E&20 557 OUT INTAOO,AL EIB8 B008 558 HOV AL,8 ElBA E621 55' 5.0 561 5.2 563 OUT INTAOl,AL HOV AL,9 OLT INTAOl,AL SUB AX,AX I POINT ES TO BEGIN HOV ES,AX ; EISC 8009 ElSE E621 EICO 28tO EIC2 BEtD HOV AL,13H ; ICWI - EDGE, SNGL, ICW4 I SETUP ICW2 - INT TYPE 8 (8-F I ; SETUP ICW4 - eUFFRO,8086 MODE OF RIW STORAGE 564 ; --------------------------------------------------------------------------- 565 CHECK FOR MAWFACTURING TEST 2 TO LOAD TEST PROGRAMS FROM KEYBOARD.: 566 567 ; --------------------------------------------------------------------------- 568 ; ----- SETUP STACK SEG AND SP EIC4 B83000 56' 570 ; GET STACK VALUE 571 MOV HOV AX,STACK EIC7 8EOO S5,AX I EIC9 BCOOOI 572 MOV SP. OFFSET TOS ; STACK IS READY TO GO Elee BIFD3412 573 OHP BP,1234H ; RESETJLAG SET? ElDO 7425 I YES - SKIP MFG TEST SET THE STACK UP 574 JE 025 fl02 2BFF 575 SUB 01,01 EI04 BEDF 576 HOV OS, 01 flD6 682400 577 HOV ex, EI09 C70747FF 57B 57' 580 MOV INC INC WORD PTR {BXl,OFFSET 011 ; SET UP KB INTERRUPT EIDO 43 flOE 43 24H BX ax flOF BeOF 581 MOV [BXI,CS E1El E85F04 5B2 CALL KBD_RESET EIE4 eDfB65 5B3 CMP BL,065H ; IS THIS MANUFACTURING TEST 2? EIE7 750E 5B. JNZ C25 ; JUMP IF NOT NAN. TEST EIE9 BUF 585 MOV DL,255 I READ IN TEST PROGRAM ElEB 58. flEe E86204 587 CALL SP _TEST flEE BAC3 588 MOV AL.Bl ElFO AA 58. STOSS ; READ IN KB RESET CODE TO Bl C22: System BIOS A-9 LOC OBJ LINE EIFl FECA 590 591 592 593 Eln 75F6 EIFS COlE EIF7 SOURCE DEC OL JNZ CZ< I JUMP IF NOT DONE YET INT lEH I SET IHTERRUPT TYPE 62 ADDRESS F8H C25: 594 595 ;----- SET UP THE BIOS INTERRUPT VECTORS TO TEMP INTERRUPT 596 597 598 EIF7 892000 ElFA 2BFF ElFC 599 600 ElFC B847FF EIFF AB CX.32. j sue 01,01 I fIRST INTERRUPT LOCATOIN HeV AX,OFFSET 011 , MOVE ADoR OF INTR PROC TO TBL AX.CS , GET ADDR OF INTR PROC SEG D3 j 601 602 HOV E202 AB 603 STOSW E203 E2F7 604 605 E200 ecce 606 E205 C7060800C3E2 E20B C706140054FF E211 C70662:DOOOF6 STOSW LOOP HOV NMI_PTR,OFFSET NMI_INT NMI INTERRUPT j HOV IHTS_PTR,OFFSET PRINT_SCREEN HOV BASIC]TR+2.,OF600H ; PRINT SCREEN ; SEGMENT FOR CASSETTE BASIC 1------- - - - -- --- - -- - - - - ------- ------- - - --- - --- ---- - ---- --- -- ----- 613 614 VECTBLO 1----- SET UP OTllER INTERRUPTS AS NECESSARY 607 608 609 610 611 612 FILL ALL 32 INTERRUPTS HOV 03: 8259 INTERRUPT CPHTROLlER TEST ; DESCRIPTION 615 REAOIWRITE THE INTERRUPT MASK REGISTER IIMR} WITH ALL 616 ONES AND ZEROES. ENABLE SYSTEM INTERRUPTS. 617 INTERRUPTS OFF. CHECK FOR HOT INTERRUPTS (UNEXPECTEDI. 618 MASK DEVICE: : ,---------------------------------------------------------------- 619 62.0 ;----- TEST THE IMR REGISTER E224 EE 621 622 623 624 625 626 627 628 629 OUT DX,AL E225 EC 630 IN AL,OX ; READ II1R E226 0401 631 AOO AL.I ; ALL 111R BIT ON? E228 7500 632 JNZ 06 ; NO - GO TO ERR ROUTINE E217 8A2:IOO E2lA BODO EHC EE E2:10 EC EllE DACO E220 7515 E222 BOFF POINT INTR. CHIP AODR. 21 DX.OO21H j HOV AL.O J SET IHR TO ZERO OUT OX,Al HOV AL,OX j OR AL.AL ; INR JNZ 06 j HOV AL.OFFH I DISABLE DEVICE INTERRUPTS ; WRITE TO II'fR IN READ IHR = O? GO TO ERR ROUTINE IF HOT 0 633 634 j----- CHECK FOR HOT INTERRUPTS 635 636 E22:A 32E4 E22C FB E220 2BC9 E22F E22F E2FE [231 E231 E2FE E233 0.4.E4 E235 7408 637 638 639 640 641 642 643 644 645 E23A E89203 646 647 648 649 E230 FA 650 E23E F4 651 652 E237 En7 BAOIOI ;----- INTERRUPTS ARE MASKED OFF. CX,CX ; WAIT 1 SEC FOR ANY INTRS THAT LOOP 04 , LOOP 05 AH,AH j CLEAR AH REG ; ENABLtI EXTERNAL INTERRUPTS 04: MIGHT OCCUR 05: OR AH,AH , DID ANY INTERRUPTS OCCUR? JZ 07 ; NO - GO TO NEXT TEST HeV DX.I01H j CAll ERR_BEEP ; GO TO BEEP SUBROUTINE 06: BEEP SPEAKER IF ERROR CLI , HALT THE SYSTEM HLT I - ----- - - - - ---- - -- - - - ----- ----- ---- -- - ----- ------ 8253 TIMER CHECKOUT 653 654 CHECK THAT NO INTERRUPTS OCCUR. XOR STI SUB ; DESCRIPTION 655 VERIFY THAT THE SYSTEM TIMER (0) 656 DOESH' T COUNT TOO FAST OR TOO SLOW. 657 1------------------------------------------------ E23F 658 07: E2.3F BOFE 659 HOV AL.OFEH ; MASK ALL INTRS EXCEPT lVl 0 E2.41 EE 660 O\JT DX,Al I WRITE THE 82.59 IHR E242 BOlO 661 HOV AL,OOOIOOOOB J SEl TIM 0, LSB. NOOE O. BINARY E244 E643 002 OUT TIM_CTL,AL I WRITE TIMER CONTROL MODE REG E2:46 B91600 663 tIOV CX,16H , SET PGM LOOP CNT E2:49 8ACI 664 NOV Al,CL J SET TIMER 0 CHT REG E2:4B E640 665 OUT TIMERO,Al J WR:j:TE TIMER 0 CNT REG A-lO System BIOS LOC OBJ LINE SOURCE E240 666 667 668 08: E240 FbC4FF E250 7504 E2:52 E2F9 E2:54 EBEI E2:56 E256 9112 E2:58 BOFF E25A E640 E2se e8FEOO E25F EE E2:60 E260 F6C4FF E263 7502: E2:65 E2F9 E267 IE E268 BF4000 E2:68 DE E26C If E2:60 BE03FF90 E2:71 891000 E2:74 BOFF E2:76 EE E2:77 B036 E2:79 E643 E2:78 BODO E2:7D E640 E2:7F E2:7F AS E2:80 47 E2:81 47 E2:82 E2:FB E284 E640 E286 IF E287 E8B903 669 670 671 672 E295 E460 E297 24FF E299 750E E298 FE061Z04 E29F C7062:0006DE6 E2:A5 BOFE E2A7 E621 E2A9 E2A9 BOCC E2AB E661 E2AF B400 E2Bl A31004 I WRITE TIMER 0 CNT REG "OV OUT TEST AH.OFFH JHZ 06 lOOP 010 ; SETUP ADDR TO INTR AREA CS , SETUP ADDR OF VECTOR TABLE OS SI,OFFSET VECTDR_TABlE+l6 I START WITH VIDEO ENTRY CX,I6 AL,OFFH MOV OlIT OX,AL MOV AL,36H ; SEL TIM O,LSB,I1SB,MODE 3 OUT TIHER+3,AL ; WRITE TIMER MODE REG "OV OUT AL,O I DISABLE ALL DEVICE INTERRUPTS TIMER,AL • WRITE LSB TO TIMER 0 REG 01 01 ; MOVE PAST SEGMENT POINTER EIA: f HOVE VECTOR TABLE TO RAM MOVSW INC INC 703 704 LOOP ElA OUT POP TIMER,AL I WRITE I1SB TO TIMER 0 REG OS I RECOVER DATA SEG POINTER ;----- SETUP TIMER 0 TO BLINK LED IF MANUFACTURING TEST MODE 708 709 CAll KBD_RESET I SEND SOFTWARE RESET TO KEYBRO C"P JE BL,OAAH I SCAN CODE • AA' RETURNED? E6 ; YES - CONTINUE (NON HFG HOOE) "OV OUT AL.3CH I EN KBD. SET KBD CLK LINE LOW PORT_B.AL ; WRITE 8255 PORT B NOP NOP 71' 716 717 71& 719 720 721 722 723 724 725 726 I SAVE POINTER TO DATA AREA OS 01,OFFSET VIDEO_INT ;----- SETUP TIMER 0 TO MODE 3 701 702 70' 706 707 , DID TIMER 0 INTERRUPT OCCUR? J YES - TIMER CNTING TOO FAST, ERR I WAIT FOR ItrrR FOR SPECIFIED TIME 1----- ESTABLISH BIOS SUBROUTINE CALL INTERRUPT VECTORS 69. 696 697 69& 699 700 OX.At 010: 692 693 694 IN AL,PORT_A AtIll AL,OFFH JNZ INC MOV E2 MOV OUT I WAS A BIT CLOCKED IN? I YES - CONTINUE (NON HFG MODE) DATA_AREA[OFFSET MFG_TSTJ ; ELSE SET SW FOR MFG TEST HOOE INT_ADDR.OFFSET BLINK.....INT I SETUP TIMER INTR TO BLINK LED Al,OFEH ; ENABLE TIMER INTERRUPT INTAOl,AL £2:: 1 JUHPER_NOT_IN: "OV OUT AL.DCCK ; RESET THE KEYBOARD PORT_B,AL ;-------------------------------------------------------INITIALIZE AND START CRT CONTROllER (6845) TEST VIDEO REAO/WRITE STORAGE. ; DESCRIPTION 731 732 RESET THE VIDEO ENABLE SIGNAL. 733 734 735 REAOIWRITE DATA PATTERNS TO STG. CHECK STG 736 737 738 E2B4 2430 739 740 741 E256 7529 742 E2:B4 I SET PGM LOOP eNT At,OFFH TlHERO,AL AX,OFEH "OV MOV 7" ,,& E2AD E460 CL,lS 68& 689 690 691 "9 730 E2AD HOV "OV OUT PlSH 719 E294 90 J"P I ! 1070 HOV INTAOl,At Al,OB6H E4Sf £643 1071 1072 HOV TIMER+3,Al AX,1235 OUT I DISABLE TINER INTERRUPTS ; SEL TIM 2, LSB, MSB. MD 3 ; WRITE 8253 CMDIMODE REG £494 £642 £496 SAC4 1073 OUT TINER+2.Al ; SET TIMER 2 CNT FOR 1000 USEC , WRITE TIMER 2 COUNTER REG 1074 MOV Al.AH ; WRITE NSB £498 £642 1075 O\JT TIMER+2.AL E491 880304 1076 1077 ;----- READ CASSETTE INPUT 1078 £462 2410 A26800 £80514 1079 IN AL,PORT_C I READ VALUE OF CASS IN BIT 1080 AND AL.IOH ; ISOLATE FROM OTHER BITS 1081 MaV LAST_VAl.Al 1082 CALL READ.HALF.BIT E4A4 £60214 1083 CALL READ.HALF _BIT E4A7 f30C £449 61FB400S 1084 Jexz .8 10B5 eMP BX.NA),-PERIOD E4AD 730E> 1086 JNe .8 £494 E49C £49£ E4Al E4AF BIFBI004 1087 eMP BX.MIN_PERIOD E483 7307 1088 JHe ROM.SCAN E4S5- 1089 E4S5 BE39Ff90 1090 MaV SI.OFFSET F2 CAS_ERR ; CASSETTE WRAP FAILED CAll P.MSG ; GO PRINT ERROR MSG £489 ESFED! I GO TO NEXT TEST IF OK F8: 1091 I 1092 1- ------ - - ------ ----- - ------------ -.- - -- - -- - - - - - - -.- - -- - ---- - - - -- -- ------ 1093 CHECK FOR OPTIONAL ROM fROM C8000->F4000 IN 2K INCREMENTS 1094 (A VALID tKIDULE HAS '55"'" IN THE fIRST 2 LOCATIONS, LENGTH 1095 INDICATOR {LENGTH/512) IN THE 3RD LOCATION AND TEST/INIT. 1096 CDOE STARTING IN THE 4TH LOCATION.) 1097 ;------------------------------------------------------------------------ E4BC 1096 ROM_SCAN: E4BC BAOOt8 1099 MOV E48f 1100 ROM.SCAN_1 : E48F BED ... 1101 MOV DS,DX OX,OC800H ; SET BEGINNING ADDRESS 1102 SUB BX,BX E4C3 6B07 1103 MOV AX.[BX) ; GET 1ST WORD FROI1 NODULE £4t5 30SSA-' E4C8 7505 1104 eMP AX,OAASSH I 1105 JHZ NEXT_ROM J PROCEED TO NEXT ROM IF NOT E4CA £88701 1106 CAll ROM_CHECK ; GO 00 CHECKSUM AND CALL E4eD £804 E4CF 1107 JMP SHORT ARE_WE_DONE ; CHECK FOR EICI OF RDt1 SPACE E4CF 81C28000 1109 OX,ooaOH I POINT TO NEXT 2K ADDRESS E403 1110 E4Cl 2BOB E403 81FAOOF6 1108 1 SET BX=OOOO = TO ID WORD? NEXT_RDM: ADO ARE_WE_DONE: 1111 eMP DX,OF600H ; AT F6000 YET? E4D7 7C£6 1112 JL RON.SCAN_l ; GO CHECK ANOTHER ADD. If NOT E409 £801"'0 1113 JMP BASE_ROM_CHK J GO CHECK BASIC ROM 1115 1114 ; -----------------------------------------------ROS CHECKSUM I I 1116 ; DESCRIPTION 1117 A CHECKSUM IS DDNE FOR THE 4 RDS 1118 MODULES CONTAINING BASIC CODE 1119 ------------------------------------------------ E40e 1120 ; BASE_ROM_CHK: E40e 1121 E4: E40t ZBOB 1122 SUB BX,BX E4DE BEDA 1123 HOV DS,OX E'tEO £86907 1124 CAll ROS_CHECKSU1 A-16 System BIOS J SETUP STARTING ROS ADDR f CHECK ROS LOC OBJ E4E3 7403 LINE E4E5 E82103 1125 1126 E4E8 1127 E4E8 80C60, E4EB 80FEFE E4EE 75Et E4FO IF SOURCE 112.8 1129 1130 1131 1132 1133 1134 ; I CONTINUE IF OK I POST ERROR I POINT TO NEXT 8K HOCDULE ADD DH.02H CMP OH,OFEH JNZ E4 I PDP OS ; RECOVER DATA SEG PTR YES - CONTINUE DISKETTE ATTACHMENT TEST I DESCRIPTION CHECK IF IPL DISKETTE DRIVE IS ATTACHED TO SYSTEM. IF ATTACHED, 1136 1137 tHO TO FOC AND CHECK STATUS. COMPLETE SYSTEM INITIALIZATION 1138 THEN PASS CONTROL TO THE BOOT LOADER PROGRAM. VERIFY STATUS OF NEe FOC AFTER A RESET. ISSUE A RECAL AND SEEK ------------------------------------------------------------------------ 1139 ; F9: E4F4 ABOI 1140 1141 114Z E4F6 750A 1143 E4F8 e03ElZOOOl 1144 E4FD 7530 1145 E4F1 MIOOO E5 ROM_ERR ------------------------------------------------------------------------ I 1135 E4Fl JE CALL E5: E4FF E959FB 1146 E502 E50Z E4Z1 1147 1148 E504 Z4BF E506 E621 MOV AL,BYTE PTR EQUIPJUG TEST AL,OIH ; IPL DISKETTE DRIVE AnCH? JHZ flO ; NO -SKIP THIS TEST CMP MFG_TST,l ; I1ANUFACTURING TEST MODE? JNE F15A ; NO - GO TO BOOT LOADER I GET SENSE SWS INFO JMP START ; YES - LOOP POWER-ON-DlAGS IN AL,INTAOI ; DISK_TEST 1149 AND AL,OBFH ; ENABLE DISKETTE INTERRUPTS 1150 OUT INTA01,AL FlO: E508 B400 1151 MOV AH,O ; RESET NEC FOC E50A BA04 115Z MDV OL,AH I (POINT TO DISKETTE I E50C C013 1153 INT 13H ; VERIFY STATUS AFTER RESET E50E 72:Z1 1154 JC F13 1155 1156 ; ----- TURN DRIVE 0 MOTOR ON 1157 E510 BAF203 1158 ; GET ADDR OF FDC CARD 1159 MDV pUSH DX,03F2H E513 52 E514 BOlC 1160 MOV OX AL,ICH ; TURN MOTOR ON, EN DMA/INT E516 EE E517 2BC9 1161 1162 !XJT ,.., DX,AL CX,CX E519 1163 LOOP F11 LOOP F12 E519 E2FE 1164 E518 1165 E51B E2FE 1166 F11: I SAVE lT ; WRITE FOC CONTROL REG I MOTOR_WAlT: F12: I WAlT FOR 1 SECotm ; MOTOR_WAIT 1 : E51D 3302 1167 XOR OX,DX ; SELECT DRIVE 0 ESIF 6501 1168 MOV CH,I I SE LEtT TRACK 1 E521 88163EOO 1169 MOV SEEK_STATUS,DL E525 E85509 1170 CALL SEEK I RECALIBRATE DISKETTE E528 72:07 1171 JC ; GO TO ERR SUBROUTINE IF ERR E52A 8522 1172 MOV Fl' CH,34 E52C E84E09 E52F 7307 1173 tALL 1174 JNC SEEK Fl4 I SEEK TO TRACK 34 ; OK, TURN MOTOR OFF E531 1175 ; SELECT TRACK 34 ; DSK_ERR: FB: E531 BEEAFF90 1176 MOV SI,OFFSET F3 ; GET ADOR OF MSG E535 E88201 1177 CALL P_MSG ; GO PRINT ERROR HSG 1178 1179 1----- TURN DRIVE 0 MOTOR OFF 1180 E536 E538 BOOC 1181 AL.OCH I ORO_OFF: ; TURN DRIVE 0 MOTOR OFF OX I RECOVER FDC CTL ADDRESS OX.Al F14: 1182 E53A SA 1183 NOV PDP E538 EE 1184 OUT 1185 1186 1----- SETUP PRINTER AND RS232 BASE ADDRESSES IF DEVICE ATTACHED 1187 FlSA: E53C 1168 E53C BEIEOO 1189 MDV 51. OFFSET KB_BUFFER E53F 89361AQQ 1190 1191 MOV MOV BUFFER_HEAD ,51 BUFFER_STARl,SI I DEFAULT TO STAt.ilARD BUFFER J (3;: BYTES LONG) E543 89361COO E547 89368000 1192 MOV E548 83C6Z0 1193 ADD 51,32 E54E 89366200 1194 MDV BUFFER_Et-I>.SI E552 E421 1195 IN Al,INTAOl E554 24FC 1196 E556 E621 E556 B03OE690 1197 1198 Esse 2BF6 1199 ESSE 1200 1201 ESSE 2£885600 AND I SETUP KEYBOARD PARAMETERS BUFFER_TAIL.SI AL,OFCH OUT INTA01,AL MDV SUB BP,OFFSET F4 MDV DX,CS:[BP] 1 Et-IABLE TIMER AND KBD INTS I PRT_SRC_TBL 51,51 ; PRT_BASE: F16: I GET PRINTER BASE ADDR System BIOS A-17 LaC OBJ LINE SOURCE E562 BOAA 1202 HOV Al,OAAH E564 EE 12:03 OUT PUSH IN POP DX.AL £565 52 CHP JHE Al,OAAH J DATA PATIERH SAME F17 • NO - CHECK NEXT PRT CD HOV PRINTER_BASE[ 51) .OX ; YES - STORE PRT BASE ADOR INC INC SI SI ; INCREMENT TO NEXT WORD E566 EC 1204 12:05 £567 SA 12:06 E568 3CAA 1207 £561. 7505 1208 ES6C a95408 1209 1210 E56F 46 E570 46 1211 1212 E571 E571 45 E573 81FD43E6 £577 75E5 E579 ZBDS E57E EC E57f ABFa E561 7506 I READ PORT A I NO_STORE: INC INC CHP JHE SUB HOV 1216 1219 1220 ES7S SAFA03 I WRITE DATA TO PORT A ox f17: 12:13 1214 1215 1216 1217 E572 45 OX AL,DX BP ; POINT TO NEXT BASE ADDR BP BP,OFFSET F4E Fl. , I ALL POSSIBLE ADDRS CHECKED? eX,ex , DX,3FAH I CHECK IF RS232 CD 1 AntH? IN TEST JHZ Al,DX ; READ INTI? 10 REG HOV INC INC RS232_BASE[BX J .3F8H PRT_BASE POINTER TO R5232 TABLE AL,OFaH Fl8 E583 C707F803 1221 1222 E587 43 1223 E568 43 1224 E589 1225 E569 8602 1226 MOV OH,02H E58B EC 1227 IN AL,OX ; READ INTERRUPT 10 REG E56C A6F6 1226 TEST AL.OF6H E56E 7506 1229 Fl. , £590 C707F602 1230 JHZ HOV RS232_BASE( BX] ,2F8H ; SETUP RS232 CO 12 E594 43 1231 E595 43 1232 INC IHC BX BX ; SETUP RS232 CD 11 AODR BX BX F18: I CHECK IF RS232 CO 2 ATTCH (AT 2FAI BASE_END 1233 1234 ;----- SET UP EQUIP FLAG TO INDICATE NUMBER OF PRINTERS AND RSC!3C! CARDS 1235 ; BASE_END: E596 1236 E596 8BC6 1237 HOV AX.SI E596 B103 1236 HOV 000 CL,3 ; SHIFT COUNT AL.eL ; ROTATE RIGHT 3 POSITIONS AL,BL E59A 02ca 1239 E59C OAC3 1240 E59E A21100 1241 F!9: E5Al B201 1242 E5A3 EC 1243 OR HOV HOV IN E5A4 A80F 1244 TEST AL.OFH E5A6 7505 1245 E5A8 800Ell0010 1246 JNZ 00 BYTE PTR EQUIP_FLAG+l.16 1247 E5AO ; 51 HAS 2* NUMBER OF RS232 ; OR IN THE PRINTER COUNT BYTE PTR EQUIP_FLAG+l.,u ; STORE AS SECOND BYTE OL.OIH ; DX=201 AL.OX FlO I NO_GAME_CARO flO: 1248 1249 ESAD ,. ;----- SET DEFAULT TIMEOUT VALUES FOR PRINTER At.I) RS232 1250 1251 PUSH E5AE 07 1252 E5AF BF7800 1253 E5B2 681414 1254 POP MOV HOV E565 AB 1255 STOSW E586 AB 1256 STOSW E587 B60101 1257 MOV E5BA AB 1256 STOSW ESBB A6 1259 STOSW OS ES OI.OFFSET PRINT_TIM_OUT AX,1414H ; PRINTER DEFAULTS (COUNT=20) AX,OIDIH ; RS232 OEFAULTS=OI 1260 U~61 ;----- ENABLE NHI INTERRUPTS 1262 , , , 1264 HOV OUT AL , 60H ESBE E6AO ESCO 803E120001 1265 CMP MFG_TST,1 JE HOV DX,l CALL EIU'_BEEP ; BEEP 1 SHORT TONE IHT 19M , , E5BC 8080 1263 E5C5 7406 1266 E5C7 BAOI00 1267 E5CA E60200 1268 1269 ESCD 1270 ESCO C019 1271 OAOH,AL F21 F21: ENABLE NHI INTERRUPTS MFG MODE? LOAP_BOOT_STRAP LOAD_BOOT_STRAP: BOOTSTRAP 1272 1273 1274 1275 1276 1277 1278 A-I8 ;-------------------------------------------------------INITIAL RELIABILITY TEST -- SUBROUTINES ;-------------------------------------------------------ASSUME CS:CODE,DS:DATA. ; --- --------------------------------------- -------------------; SUBROUTINES FOR POWER ON DIAGNOSTICS System BIOS LOC OBJ LINE SOURCE THIS PROCEDURE WILL ISSUE ONE LONG TONE (3 SECS) AI«) ONE OR 1279 12:80 MORE SHORT TONES 11 SEC) TO INDICATE A FAIllRE ON THE Pl.ANAR BOARD. A BAD RAM MODULE, OR A PROBLEI1 WInt THE CRT. 1281 1282 I ENTRY PARAMETERS: OH = Dt = NUt1BER HUMBER OF LONG TONES TO BEEP 1263 1284 12:85 I---------~-------------------------------------------------------------- ESC' 1286 ERR_BEEP E5CF 9C £500 FA 1267 12:88 PUSH' ClI ESDI IE 12:89 £502 E86919 1290 1291 PUSH CALL E50S OAF6 E507 7418 1292 E509 1293 £509 B106 1294 1295 ESOB £62500 ESDE E2FE E5EO FEtE 1296 1297 £5E2 75F5 1298 E5E4 803E120001 1299 PROC OF SHORT TONES TO BEEP NEAR I SAVE FLAGS I DISABLE SYSTEM INTERRUPTS DR OS DDS DH,DH J SAVE OS REG CONTENTS I ANY LONG ONES TO BEEP JZ G3 ; NO. DO THE SHORT ONES I LONG_BEEP: MaV Bl.b I COUNTER FOR BEEPS CALL BEEP I 00 THE BEEP lOOP G2 ; DELAY BETWEEN BEEPS DEC JHZ CMP JNE OH J ... NY HORE TO DO G1 I DO IT HFG_TST,1 I MFG TEST MODE? Gl: G2: ESE9 7506 1300 G3 I YES - CONTINUE BEEPING SPEAKER ESEB BOCD 1301 MOV Al.OCDH I STOP BLIt-I ?' ,-1.0.-1.' •• -1 E944 FF E945 7C5A584356424£ 4D3C3E3F E950 FF E951 00 E952 FF E953 20 E95<+ FF ;----- UC TABLE SCAN E955 1942 1943 E955 54 1944 DB 84,85,86,87.88,89,90 1945 DB 91,92.93 K 12 LABEl BYTE E956 S5 E957 56 E958 57 E959 58 E95A 59 E958 SA E<;ISC 58 E950 5C E95E 50 1946 ;----- AlT TABLE SCAN E95F 1947 K13 E95F 68 1948 DB 104,105,106,107,108 1949 DB 109,110,111,112,113 LABEL BYTE E960 69 E961 6.1. £962 68 E963 be E964 60 E965 bE E966 6F E967 70 E968 71 1950 ;----- t-ruM STATE TABLE E969 1951 Kl' E969 37363920343536 1952 LABEL BYTE DB '789-456+1230. ' 2B313233302E 1953 ; ----- BASE CASE TABLE E976 1954 K15 E976 47 1955 DB 71,72,73,-1,75,-1,77 1956 DB -1,79,80,81,82,83 LABEL BYTE £977 48 E978 49 E979 FF E97A 4B Ens FF E97C 40 E97D fF EnE 4F E97F 50 E980 51 E981 52 E982 53 1957 1958 ; ----- KEYBOARD INTERRUPT ROUTINE 1959 E987 1960 E987 1961 £987 FB 1962 sn E988 50 1963 PUSH ORG KB_INT PROC OE987H FAR ; ALLOW FURTHER INTERRUPTS AX E989 53 1964 PUSH BX E98A 51 1965 PUSH E988 52 1966 PUSH ex ox E<;I8C 56 1967 PUSH E98D 57 1966 PUSH E98E IE 1969 PUSH SI OI OS E98F 06 1970 PUSH ES E990 Fe 1971 ClO E991 EaAA15 1972 CALL DOS E994 E460 1973 IN AL,KB_DATA ; READ IN THE CHARACTER £996 50 1974 PUSH AX ; SAVE IT E997 E461 1975 E999 8AEO 1976 IN MOV AH,AL ; SAVE VALUE E99B OC80 1977 OR AL,80H I RESET BIT FOR KEYBOARD ~ AL,KB_CTL FORWARD DIRECTION ; GET THE CONTROL PORT System BIOS A-29 LINE LOC OSJ SOURCE E990 E661 1976 E99F 66EO 1979 XCHG AH,AL I GET BACK ORIGINAL CONTROL E9Al E661 1980 OUT KB_CTL,AL ; KB HAS BEEN RESET f9A3 58 1981 POP AX ; RECOVER SCAN CODE E9A4 8AED 1982 HOV AH tAL I SAVE SCAN CODE IN AH ALSO OUT KB_CTl,AL 1983 1984 ; ----- TEST FOR OVERRUN SCAN CODE FROM KEYBOARD 1985 E9A6 3tFF 1986 CMP Al.OFFH ; IS THIS AN DVE'RRUN CHAR E9A8 7503 1987 JNZ KI6 I NO, TEST FOR SHIFT KEY f9AA E97A02 1988 JMP K62 ; BUFFERJULl_BEEP 1989 1990 ;----- TEST FOR SHIFT KEYS 1991 f9AO 19n f9AO 247F 1993 AND Al.07FH E9Af DE 1994 PUSH CS E9BO 07 1995 POP ES ; ESTABLISH ADDRESS OF SHIFT TABLE E9Bl Bf7EE8 1996 HOV DI.OFFSET K6 I E984 890800 1997 MOV CX,K6l E9B7 F2 1998 REPNE StASB 1 LOOK THROUGH THE TABLE FOR A MATtH E989 8AC4 1999 MOV Al,AH ; RECOVER SCAN CODE E9BS 7403 2000 JE KI7 I JUHP I F MATCH FOUND f9BD E96500 2001 JMP K25 ; IF NO MATCH, THEN SHIFT NOT FOUND K16: ; TEST_SHIFT ; TURN OFF THE BREAK BIT SHIFT KEY TABLE LENGTH E9B8 AE 2002 2003 ;----- SHIFT KEY FOUND 2004 Kl7: ; ADJUST PTR TO SCAN CODE MTCH E9CO 81EF7FE8 2005 SUB DI,OFFSET K6+1 E9C4 2E6AA586E8 2006 MOV AH,CS:K7!oIl E9C9 ABBD 2007 TEST AL,80H ; TEST FOR BREAK KEY E9CB 7551 2008 JNZ K23 ; BREAK_SHIFT_FOUND ; GET MASK INTO AH 2009 2010 ;----- SHIFT MAKE FOUND, DETERMINE SET OR TOGGLE 2011 E9CD BOFCIO CMP 2012 E900 7307 2013 JAE KIa ; IF SCROLL SHIFT OR ABOVE. TOGGLE KEY 2014 2015 ;----- PLAIN SHIFT KEY, SET SHIFT ON 2016 E902 08261700 E906 E98000 2017 O. ; TURN ON SHIFT BIT 2018 JMP ; INTERRUPT_RETURN 2019 2020 1----- TOGGLED SHIFT KEY, TEST FOR 1ST MAKE OR NOT 2021 K18: ; SHIFT-TOGGLE '909 2022 E909 F606170004 2023 TEST KBJLAG. CTl_SHIFT E9DE 7565 2024 JNZ K25 ; JUMP IF CTl STATE E9EO 3C52 2025 E9E2 7522 2026 JNZ K22 ; JUMP IF NOT INSERT KEY E9E4 F60617Q008 2027 TEST KBJLAG. All_SHIFT ; CHECK FOR ALTERNATE SHIFT E9E9 755A 2028 JNZ K25 ; JUMP IF ALTERNATE SHIFT TEST ; CHECK CTl SHIFT STATE I CHECK FOR INSERT KEY E9EB F60b170020 2029 KBJLAG. NUN_STATE ; CHECK FOR BASE STATE E9FO 7500 2030 JNZ K21 ; JUMP IF NUH LOCK IS ON E9F2 F606170003 2031 TEST KBJLAG, E9F7 7400 2032 JZ K22 ; JUMP IF BASE STATE K19: LEFT_SHIFT+ RIGHT_SHIFT 2033 E9F? 2034 K20: E9F9 863052 2035 MOV AX. 5230H ; PUT OUT AN ASCII ZERO E9Ft E90601 2036 JMP K57 E9FF 2037 ; BUFFERJILl ; HIGHT BE NUMERIC E9FF F606170DOJ 2038 K20 ; JUMP NUMERIC, NOT INSERT K21 : TEST JZ 2039 fAD4 74F3 ; NUMERIC ZERO. NOT INSERT KEY 2040 EA06 2041 EA06 84261800 2042 ; SHIFT TOGGLE KEY HIT; PROCESS IT K22: ; IS KEY ALREADY DEPRESSED fADA 7540 2043 JNZ K26 ; JUMP I f KEY ALREADY DEPRESSED fADe 08261800 2044 O. KB_FlAG_l.AH ; INDICATE THAT THE KEY IS DEPRESSED EAlO 30261700 2045 XO. KB_FlAG.AH EA14 3C52 2046 CMP AL,IHS_KEY ; TEST FOR 1ST HAKE OF INSERT KEY EA16 7541 2047 JNE K26 ; JUHP IF NOT INSERT KEY EA16 880052 2048 MOV AX , INSJEY*256 ; SET SCAN CODE INTO AH. 0 INTO AL EAIB E98701 2049 JMP K57 J PUT INTO OUTPUT BUFfER ; TOGGLE THE SHIFT STATE 2050 2051 ; ----- BREAK SHIFT FOUND 2052 fAIE A-30 2053 K23: System BIOS ; BREAK-SHIFT-FOUND LaC OBJ LINE SOURCE fAIE SOFClO 2054 eMP AH,SCROll_SHIFT EA21 731A 2:055 JAE K2' EA23 F6D4 2056 NOT AH KB_FlAG.AH 2057 AND EA29 3eB8 2058 eMP Al,AlT_KEY+80H EAlB 752C ,059 JHE K26 EA25 20261700 IS THIS A TOGGLE KEY YES. HANDLE BREAK TOGGLE I INVERT MASK ; TURN OFF SHIfT BIT IS THIS ALTERNATE SHIFT RelEASE ; INTERRUPT_RETURN 2060 2061 2062 .----- ALTERNATE SHIFT KEY RELEASED. GET THE VALUE INTO BUFFER fAZD A01900 Z063 MOV AL.ALI_INPUT EA30 B400 2064 MOV AH,D ; SCAN CODE OF 0 EA32 88261900 2065 MOV ALT_INPUT,AH ; ZERO OUT THE FIELD WAS THE INPUT=O EA36 3COO 2066 eMP Al,O £A38 741F Z067 JE K26 EA3A E9AI01 2068 JMP K58 EA30 2069 EA30 F604 2070 EA3F 20261800 £A43 EB14 K24: ; INTERRUPT_RETURN ; IT WASH' T. SO PUT IN BUFFER ; BREAK-TOGGLE INVERT MASK NOT AH 2071 AND KB_FLAG_l.AH INDICATE NO LONGER DEPRESSED 2:072 JMP SHORT K26 INTERRUPT_RETURN 2073 2074 .----- TEST FOR HOLD STATE 2075 EMS 2076 ; tiD-SHIFT-FOUND K25: EA45 3C80 2077 eMP AL.80H EA47 7310 2078 JAE K26 ; TEST FOR BREAK KEY NOTHING FOR BREAK CHARS FROM HERE ON EA49 F606180008 2079 TEST KBJLAG_I.HOLO_STATE ARE WE IN HOLD STATE EME 7417 2080 JZ K28 BRANCH AROUND TEST IF HOT EA50 3C45 2081 eMP AL.NUt1_KEY EA52 7405 2082 EA54 a0261800F7 2083 EA59 2084 JE K26 ANO KB_FLAG_l.NOT HOLD_STATE CAN I T END HOLD ON NUH....LOCK ; TURN OFF THE HOLD STATE BIT K26: INTERRUPT-RETURN I TURN OFF INTERRUPTS EA59 FA 2085 eLI EA5A B020 2086 MOV AL.Eor EA5C E620 2087 OUT 020H,AL ENO OF INTERRUPT COMNAND ; SEND COMMAND TO INT CONTROL PORT ; EASE 2088 EASE 07 2089 POP ES EASF IF 2090 K27: POP DS EA60 SF 2091 POP 01 EA61 5E 2092 POP S1 EM2 SA 2093 POP OX EM3 59 2094 POP ex EA64 5B 2095 POP 8X EMS 58 2096 PDP AX EA66 CF 2097 IRET INTERRUPT -R ETURN-NO- EOI RESTORE STATE RETURN. INTERRUPTS BACK ON 2098 WITH FLAG CHANGE 2099 2100 ;----- HOT IN HOLD STATE. TEST fOR SPECIAL CHARS 2101 EA67 2102 EM7 F606170008 2103 K28: EA6C 7503 2104 JNZ K29 l JUMP IF ALTERNATE SHIFT EME E99100 2105 JMP K38 ; JUMP IF NOT ALTERNATE ; NO-HOLD-STATE TEST KBJLAG.ALT_SHIFT I ARE WE IN ALTERNATE SHIFT 2106 2107 1----- TEST FOR RESET KEY SEQUENCE (CTl ALT DEL> 2108 EA71 2109 K29: EA7l F606170004 2110 TEST KBJLAG.CTl_SHIFT ; ARE (olE IN CONTROL SHIFT ALSO EA76 7433 2111 JZ K31 ; NO_RESET EA78 3C53 2112 eMP AL.DELJEY 1 SHIFT STATE IS THERE. TEST KEY EA7A 752F 2113 JNE K31 ; NO_RESET l TEST-RESET 2114 2115 1----- CTL-ALT-DEL HAS BEEN FOUND, DO I/O CLEANUP 2116 EA7C C70672003412 2117 MOV RESET_FLAG. 1234H ; SET FLAG FOR RESET FUNCTION EA82: EA5BEOOOFO 2118 JMP RESET l JUMP TO POWER ON DIAGNOSTICS 2119 2120 ;----- ALT-INPUT-TABLE EA87 2121 K30 LABEL BYTE EA87 52 2122 08 82.79,80.81.75.76.77 2123 08 71.72.73 EA88 4F EA89 50 EA8A 51 EA8S 4B EA8C 4C EA80 40 EA8E 47 I 10 NUMBERS ON KEYPAD EA8F 48 System BIOS A-31 LINE LOC OBJ SOURCE EA90 49 2124 2125 fA9l 10 fA92 11 ;----- SUPER-SHIFT-TABLE DB 16.l7,18.19,20.21.22,23 ; A-Z TYPEWRITER CHARS EA93 12 EA94 13 EA95 14 EA96 15 EA97 16 EA98 17 E.6.99 18 2126 DB 24,25,30,31,32.33.34.35 2127 DB 36,37,38,44,45,46,47,48 2128 DB 49.50 EA9A 19 EA9B IE EA9C IF EA9D 20 EA9E 21 EA9F ZZ: EAAO 23 EAAl 24 fAA2: 25 fAA] 26 EAA4 2C EAA5 20 EAM 2E EAA7 2F EAA8 30 EAA9 31 EAAA 32 2129 2130 ;----- IN ALTERNATE SHIFT. RESET NOT FOUND EAA8 2131 2132 K31: EAAS 3C39 2133 EAAD 7505 EAAF B020 EASl E92101 2136 ; NO-RESET CHP Al,S7 2134 JHE K32 ; NOT THERE 2135 HDV AL, ' ; SET SPACE CHAR JHP K57 ; BUFFERJILL ; TEST FOR SPACE KEY 2137 2138 ; ----- LOOK FOR KEY PAD ENTRY 2139 EAB4 8F87EA 2140 2141 fAS7 890AOO fABA F2 EAB4 K32: ; ALT-KEY-PAD HDV OI,OFFSET K30 ; All-INPUT-TABLE 2142 HOV CX,10 I LOOK FOR ENTRY USING KEYPAD 2143 REPNE SCASB ; LOOK FOR MATCH ; NO_AlTJEYPAD EABS AE JHE KJ3 EABE SlEF88EA 2145 SUB DI,OFFSET K30+1 ; 01 NOW HAS ENTRY VALUE EAt:;: A01900 2146 HOV AL,ALT_INPUT ; GET THE CURRENT BYTE EAtS 840A 2147 MOV AH.IO ; MULTIPLY BY 10 EAt7 F6E4 2148 MUL AH EAC9 03C7 2149 ADD AX.DI ; ADO IN THE LATEST ENTRY EAce A21900 2150 HDV ALT_INPUT,Al ; STORE IT AWAY fACE E689 2151 JMP "b ; THROW AWAY THAT KEYSTROKE 2144 EABC 7512 2152 2153 ;----- LOOK FOR SUPERSHIFT ENTRY 2154 fAOO fAOO C606190000 2155 K33: I NO-ALT-KEYPAO ; ZERO ANY PREVIOUS ENTRY INTO INPUT fADS B9lAOO 2156 2157 MOV CX.26 fA08 F2 2158 REPNE SCASB ; 01. ES ALREADY POINTING ; LOOK FOR MATCH IN ALPHABET EA09 AE fADA 7505 2159 JHE 'l4 I NOT FOUND, FUNCTION KEY OR OTHER fAOC 8000 2160 HOV AL,O ; ASCII CODE OF ZERO fADE E9F400 Z161 JMP K57 ; PUT IT IN THE BUFFER 2162 2163 1----- LOOK FOR TOP ROW OF ALTERNATE SHIFT 2164 2165 fAEl K34: ; ALT-TOP-ROW EAfI 3C02 2166 CMP AL.Z noe 2167 JB K35 ; KEY WITH 'I' ON IT ; NOT ONE OF INTERESTING KEYS EAES 3COE 2168 CHP AL.14 ; IS IT IN THE REGION EAE7 7308 2169 JAE K35 I EAE9 80C476 2170 ADD AH,I18 AlT-FUNCTION ; CONVERT PSUEDO SCAN COOE TO RANGE EAft BODO 2171 HOV AL,O ; INDICATE AS SUCH EAEE E9E400 2172 2173 2174 JMP K57 ; BUFFERJILL EAn ;----- TRANSLATE ALTERNATE SHIFT PSEUDO SCAN CODES 2175 A-32 System BIOS LOC OBJ LINE SOURCE EAn 2176 EAFl 3e36 2177 EAF3 7303 2178 EAF5 2179 EAF5 E961FF 2180 EAFa 2181 EAFa 3(47 2182 eMP Al.7l ; IN KEYPAD REGION EAFA 73F9 2183 JAE K3. ; IF SO. IGNORE 2:184 MOV BX,OFFSET K13 ; ALI SHIFT PSEUDO SCAN TABLE 2185 JMP i<.:....5 I TRANSLATE THAT EAFC BB5FE9 EAFF E'HBOI K35: ; ALI-FUNCTION I TEST FOR IN TABLE JAE AL.59 ",7 ; AL T -CONTINUE JMP K2. ; IGNORE THE KEY eMP K36: ; CLOSE-RETURN K37: ; Al T -CONTINUE 2186 2187 ;----- NOT IN Al"'!:::~NATE SHIFT 2186 fB02 EBOC F60617DOO4 2189 2190 EB07 7458 2191 K38: I NOT-All-SHIFT TEST KBJLAG.CTL_SHIFT ; ARE WE IN CONTROL SHIFT JZ K44 ; NOT -eTL-SHIFT 2192 2193 ; ----- CONTROL SHIFT, TEST SPECIAL CHARACTERS 2194 ; ----- TEST FOR BREAK AND PAUSE KEYS 2195 E809 3C46 2196 eMP Al,SCROLL]EY fBOB 7518 2197 JHE K39 ; NO-BREAK ; RESET BUFFER TO EMPTY EBOD 861E8000 2198 MOV BX I BUFFER_START EBll 891ElAOO 2199 MOV BUFFER_HEAD,BX ; TEST FOR BREAK EB15 89lEICOO 2200 MOV BUFFER_TAIL.BX EB19 C606710080 2201 MOV BIOS_BREAK,80H EB1E C[HB 2202 INT IBH EB20 2BCO 2203 SUB AX,AX ; PUT OUT DUMMY CHARACTER EB22 E9BOOO 2204 JMP K57 ; BUFFERJIll E825 2205 EB25 3C45 2206 eMP Al.NUH_KEY EB27 7521 2207 JHE K41 ; NO-PAUSE EB29 800El80008 2208 OR KBJlAG_l.HOlD_STATE ; TURN ON THE HOLD FLAG K39: ; TURN ON BIOS_BREAK BIT ; BREAK INTERRUPT VECTOR ; NO-BREAK ; LOOK FOR PAUSE KEY EB2E B020 2209 MOV Al.EOI ; END OF INTERRUPT TO CONTROL PORT EB30 E620 2210 OUT 020H.Al ; ALLOW FVRTHER KEYSTROKE INTS 2211 2212 ;----- DURING PAUSE INTERVAL. TURN CRT BACK ON 2213 EB32 803E490007 2214 eMP CRT_MODE ,7 ; IS THIS BLACK AND WHITE CARD E837 7407 2215 JE K40 ; YES. NOTHING TO DO EB39 BA0803 2216 MOV OX.0308H ; PORT FOR COLOR CARD EB3C A06500 2217 MOV ALICRT_MODE_SEl ; GET THE VALUE OF THE CURRENT MODE EB3F EE 2218 OUT DX.AL EB40 2219 EB40 F6061BOOOB EB45 75F9 2220 2221 JHZ K40 EB47 E914FF 2222 JMP K27 EB4A 2223 SET THE CRT MODE. SO THAT CRT IS ON K40: PAUSE-LOOP TEST KBJLAG_l,HOLD_STATE K41 : , , LOOP UNTIL FLAG TURNED OFF INT ERRUPT_R ETURN_ NO_ EOI ; NO-PAUSE 2224 2225 ;----- TEST SPECIAL CASE KEY 55 2226 EMA 3C37 2227 eMP AL.55 EB4C 7506 222B JHE K42 I NOT-KEY-55 EB4E B80012: 2229 MOV AX.l14*256 I START/STOP PRINTING SWITCH EBSI E98100 2230 JMP K57 ; BUFFERJIlL 2231 2232 1----- SET UP TO TRANSLATE CONTROL SHIFT 2233 EB54 2234 EB54 BB8EE8 2235 MOV BX,OFFSET K8 2236 eMP AL,59 EBS7 3C3B K42: ; NOT-KEY-55 2237 I SET UP TO TJ;!AHSLATE tTL ; IS IT IN TABLE I CTL-TABLE-TRANSLATE EB59 12:76 2238 JB K5. I YES. GO TRANSLATE CHAR EBSB 2239 EBSB BBC8E8 2240 MOV BX,oFFSET K9 I CTL TABLE SCAN EB5E E9BCOO 2241 JMP K63 I TRANSLATE_SCAN K43: ; CTL-TABLE-TRANSLATE 2242 2243 ; ----- NOT IN CONTROL SHIFT 2244 EB61 2245 EB61 3C47 2246 K44: I NOT-CTL-SHIFT eMP ,U.71 I TEST FOR KEYPAD REGION EB63 732:C 2247 JAE K4B EB65 Fb06170003 2248 TEST KBJ LAG , LEFT_SHIFT+RIGHT_SHIFT EB6A 745A 2249 JZ K54 ; HANDLE KEYPAD REGION ; TEST FOR SHIFT STATE 2250 2251 1----- UPPER CASE. HANDLE SPECIAL CASES 2252 System BIOS A-33 LOCOBJ LINE EB6C 3eOF 2253 SOURCE CHP Al.lS I BACK TAB KEY fB6E 7505 2254 JHE .OS ; NOT-SACK-TAB E870 88000F 2255 HOV AX.lS*Z56 ; SET PSEUDO SCAN CODE fB73 E660 2256 JHP SHORT K57 E875 2257 E875 3e37 2258 CHP EB77 7509 2259 JHE Al.s5 .0. 2260 2261 K45: ; BUFFER_FILL ; NOT-SACK-TAB ; PIHHT SCREEN KEY ; NOT-PRINT-SCREEN ;----- ISSUE INTERRUPT TO INDICATE PRINT SCREEN FUNCTION 2262 E879 B020 2263 HOV AL.EO! I END OF CURRENT INTERRUPT EB7B E620 2264 OUT 020H ,AL ; EB7C COOS 2265 IHT SH ; ISSUE PRINT SCREEN INTERRUPT EB7F E90CFE JHP ." SO FURTHER THINGS CAN HAPPEN EB82 2266 2267 EBB2 3e38 2268 CHP AL.59 ; FUNCTION KEYS E584 7206 2269 2270 JB '07 ; NOT-UPPER-FUNCTION EBa6 8855E9 HOV eX.OFFSET K12 ; UPPER CASE PSEUDO SCAN CODES EB89 E99100 2271 JHP K63 ; TRANSLATE_SCAN EBSC 2272 EB8C BBIBE9 2273 HOV BX.OFFSET Kll ; POINT TO UPPER CASE TABLE EBaF f840 2274 JHP SHORT K56 ; OK. TRANSLATE THE CHAR K46: K47: I GO BACK WITHOUT EOI OCCURRING ; NOT-PRINT-SCREEN ; NOT -UPPER-FUNCTION 2275 2276 ;----- KEYPAD KEYS. MUST TEST HUM LOCK FOR DETERMINATION 2277 E891 2278 fB9l F60617002Q 2279 TEST KBJLAG.NUM_STATE EB96 7520 22M JHZ .52 fB98 F606170003 2281 TEST KBJLAG.LEFT_SHIFT+RIGHT_SHIFT EB90 7520 2282 JHZ '53 K48: ; KEYPAD-REGION ; ARE WE IN NUM_LOCK ; TEST FOR SURE ; ARE WE IN SHIFT STATE ; IF SHIFTED. REAllY NUM STATE 2263 2284 1----- BASE CASE FOR KEYPAD 2285 EB9F 2286 K49: ; BASE-CASE EB9F 3C4A 2267 CHP AL.74 fBAI 740B 2268 JE .SO EBA3 3C4E 2289 CHP AL.76 EBA5 740C 2290 JE '51 EBA7 2C47 2291 SUB AL.7l ; CONVERT ORIGIN EBA9 B876E9 2292 HOV BX.OFFSET K15 ; BASE CASE TABLE EBAC fB7l 2293 JHP SHORT K64 ; CONVERT TO PSEUDO SCAN EBAE 2294 EBAE B8ZD4A 2295 HOV AX.74*256+'-' ; MINUS EBBI EB22 2296 JHP SHORT K57 ; BUFFER_FILL EBB3 2297 EBB3 B62B4E 2296 HOV AX.78*256+'+' ; PLUS 2299 JHP SHORT K57 ; BUFFERJIlL EBB6 EBID ; SPECIAL CASE FOR A COUPLE OF KEYS ; MINUS K50: K51: 2300 2301 ;----- MIGHT BE NUN LOCK. TEST SHIFT STATUS 2302 EBB6 2303 EBBB F606170003 2304 K52: ; ALMOST-NUN-STATE TEST KBJLAG.LEFT_SHIFT+RIGHT_SHIFT EBBD 75EO 2305 JHZ .09 EBBF 2306 EBBF 2C46 2307 SUB AL.70 ; CONVERT ORIGIN EBCI BB69E9 2308 MOV BX,OFFSET K14 ; NUM STATE TABLE EBC4 EBOB 2309 JMP SHORT K56 ; TRANSLATE_CHAR K53: ; SHIFTED TEMP OUT OF NUM STATE ; REALLYJIUN_STATE 2310 2311 ; ----- PLAIN OLD LOWER CASE 2312 EBC6 2313 K54: I NOT-SHIFT EBC6 3C3B 2314 CHP AL,59 EBCB 7204 2315 JB .55 ; TEST FOR FUNCTION KEYS ; NOT-LOWER-FUNCTION EBCA BOOO 2316 HOV Al.O ; SCAN CODE IN AH ALREADY EBCC EB07 2317 JHP SHORT K57 ; BUFFER_FILL EBCE 2318 EBCE BBEIE6 2319 HOV BX.OFFSET KID K55: ; NOT-LOWER-FUNCTION ; LC TABLE 2320 2321 ; ----- TRANSLATE THE CHARACTER 2322 EB01 2323 EBOI FEC6 2324 DEC AL I CONVERT ORIGIN EBD3 ZED7 2325 XLAT CS:K11 ; CONVERT THE SCAN CODE TO ASCII K56: ; TRANSLATE-CHAR 2326 2327 1----- PUT CHARACTER INTO BUFFER 2326 E80S A-34 2329 K57: System BIOS I BUFFER-FILL LOC OBJ LINE SOURCE 2330 2331 eMP EB07 741F JE .H.-l 059 ; IS THIS AN IGNORE CHAR ; YES. DO NOTHING WITH IT E609 BOFCFF 2:332 eMP AH.-l ; LOOK FOR -1 PSEUDO SCAN EBDC 74lA 2333 JE 059 J NEAFCINTERRUPT_RETURN EBDS 3eFF 2334 2335 1----- HANDLE THE CAPS LOCK PROBLE" 2336 EBDE 2.337 EBDE F606170040 2338 2339 2340 EBn 742:0 2341 I BUfFER-FIlL-HaTEST K58: TEST KB]LAG,CAPS_STATE I ARE WE IN CAPS LOCK STATE JZ 061 I SKIP IF NOT 1----- IN CAPS lOCK STATE 2342 EBES f606170003 EBEA 740F TEST 2343 2344 JZ KBJLAG.lEFT_SHIFT+RIGHT_SHIFT I TEST FOR SHIFT STATE I IF NOT SHIFT I CONVERT LOWER TO UPPER 060 2345 234& ; ----- COHVERT ANY UPPER CASE TO LOWER CASE 2347 eMP AL, 'A' 061 ; FIND OUT IF ALPHABETIC EBEC 3C41 2346 EBEE 7215 2349 Je EBFO 3C5A 2350 eMP EBF2 7711 2351 JA AL.'Z' 061 EBF4 0420 2352 I CONVERT TO LOWER CASE 2353 ADD JMP AL. 'a'-'A' EBF6 EeOD SHORT K61 ; NOT_CAPS_STATE EBFa 2:354 EBfa E95EFE 2355 JMP 026 I INTERRUPT_RETURN K59: ; NOT_tAPS_STATE ; NOT_CAPS_STATE ; NEAR-INTERIWPT-RETURN 2356 2:357 ;----- CONVERT ANY LOWER CASE TO UPPER CASE 2358 K60: LOWER-TO-UPPER EBFB 2359 EBFB 3C61 2:360 eMP AL, '.,.' i FIND OUT IF ALPHABETIC EBFD 7206 2361 JB 061 ; NOT_CAPS_STATE EBFF 3C7A 2362 eMP AL, 'z' ECOI 7702: 2363 JA 061 EC03 2C20 2364 SUB AL. '.,.'-'A' EC05 2365 j ; NOT_CAPS_STATE ; CONVERT TO UPPER CASE ; NOT -CAPS-STATE K61: EC05 8BIEICOO 2366 MOV BX ,BUFFER_TAIL EC09 SBn 2367 MOV SI,BX ECOB E863FC 2368 CALL 04 ; ADVANCE tHE TAIL ECOE 3BIElAOO 2369 eMP BX,BUFFER_HEAD ; HAS THE BUFFER WRAPPED AROUND EC12 7413 2370 JE 062 ; BUFFERJULL_BEEP EC14 8904 2371 MOV [SIl,AX j EC16 891EICOO 2372: MOV BUFFER_TAIL,BX ; MOVE THE POINTER UP ECIA E93CFE 2373 JMP 026 ; INTERRUPT_RETURN I GET THE END POINTER TO TIlE BUFFER ; SAVE TIlE VALUE STORE THE VALUE 2:374 ~375 j----- TRANSLATE SCAN FOR PSEUDO SCAN CODES 2376 ECIO 2377 ECID 2C3B 2378 ECIF 2379 K63: I TRANSLATE-SCAN CONVERT ORIGIN TO FUNCTION KEYS SUB AL.59 CS:K9 ; CTL TABLE SCAN K64: j ; TRANSLATE-SCAN-ORGO ECIF 2ED7 2:380 XLAT EC2l SAEO 2381 MOV AH,AL j EC23 BODO 2362 MOV AL,O I ZERO ASCII CODE 057 ; PUT IT INTO THE BUFFER EC25 EBAE JMP 2383 PUT VALUE INTO AH 2384 2385 KB_INT ENDP 2386 2:387 j----- BUFFER IS FULL, SOUND TIlE BEEPER 2388 ; BUFFER-FULL-BEEP EC27 2389 K62: EC27 B020 2390 MOV EC29 E620 2391 EC2:B BB8000 2392 EC2E E461 2393 AL,EOI j OUT 20H ,AL I SEtID COMMAND TO INT CONTROL PORT MOV BX,oaOH ; NUMBER OF CYCLES FOR 1/12 SECOND TONE END OF INTERRUPT COMMAHD IN AL.KB_CTL ; GET CONTROL INFORMATION PUSH AX I SAVE ; BEEP-CYCLE AND Al,OFCH ; TURN OFF TIMER GATE Atil SPEAKER DATA EC30 50 2394 EC31 2.395 EC31 24FC 2396 ECB E661 2:397 OUT KB_CTl,AL ; OUTPUT TO CONTROL EC35 B94BOO 2398 MOV CX.48H ; HALF CYCLE TIME FOR TONE Ee38 2399 EC38 E2:FE 2400 lOOP 066 ; SPEAKER OFF EC3A OC02 2401 OR Al,2 ; TURN ON SPEAKER BIT EC3C E661 2402 OUT KB_CTl,Al ; OUTPUT TO CONTROL EC3E B94BOO 2403 MOV CX,48H I SET UP COUNT EC41 2404 067 ex ; ANOTHER HALF CYCLE K65: K66: K67: EC41 E2FE 2405 LODP EC43 46 2:406 DEC I TOTU TIME COUNT System BIOS A-35 LOC OBJ LINE SOURCE EC44 75E8 2407 K65 ; DO ANOTHER CYCLE Et46 58 2408 pop AX I RECOVER CONTROL Et47 E661 2409 OUT KB_CTL,AL J OUTPUT THE CONTROL EC49 E91ZFE 2410 JNP .27 JNZ 2411 2412 2413 ROS CHECKSUH SUBROUTINE ; ---------------------------------------NEAR ; NEXT_ROS_MODUlE PROt eX,BIn NOV i NUMBER OF BYTES TO ADO EC4C 2414 ReS_CHECKSUM EC4C 890020 EC4F 2415 2416 ROS_CHECKsur"CCNT: EC4F 32CO 2417 EC51 2418 EC51 0207 XOR ; ENTRY FOR OPTIONAL ROS TEST AL.Al e26: Al,DS:(BX] 2419 AOO EC53 43 2420 INC BX I POINT TO NEXT BYTE EC54 EZFB 2421 LOOP I EC56 DAca 2422 OR C26 AL,AL EC58 C3 2423 RET 2424 ROS_CHECKSUM ADO All BYTES IN RDS MODULE I SUM = O? 'NOP 2425 2426 2427 INT 13 -------------------------------------------------------------; DISKETTE 110 j-- nus 2428 2429 INTERFACE PROVIDES ACCESS TO THE 5 1/4" DISKETTE DRIVES INPUT (AH )=0 2430 RESET DISKETTE SYSTEM HARD RESET TO NEC, PREPARE COMMAND, RECAL REQUIRED 2431 2432 ON ALL DRIVES (AH)=l 2433 READ THE STATUS OF THE SYSTEM INTO (AU DISKETTE_STATUS FROM LAST OPERATION IS USED 2434 2435 2436 ; REGISTERS FOR READIWRITE/VERIfY/FORMAT 2437 (OU - DRIVE HUMBER (0-3 ALLOWED, VALUE CHECKED) 2438 (DH) - HEAD NUMBER (0-1 ALLOWED, NOT VALUE CHECKEO) 2439 (CH) - TRACK NUMBER (0-39, NOT VALUE CHECKED) 2440 (CLl - SECTOR NU~IBER (1-8. NOT VALUE CHECKED. 2441 HOT USED FOR FORMAll 2442 (ALI - NUMBER OF SECTORS ( MAX = 8, NOT VALUE CHECKED. NOT USED; 2443 FOR FORMATI 2444 (ES:BX) - ADDRESS OF BUFFER ( HOT REQUIRED FOR VERIFY) 2445 2446 (AH 1=2 READ THE DESIRED SECTORS INTO MEMORY 2447 {AH )=3 WRITE THE DESIRED SECTORS FROM MEMORY 2448 (AH )=4 VERIFY THE DESIRED SECTORS 2449 (AH )=5 FORMAT THE DESIRED TRACK 2450 FOR THE FORMAT OPERATION. THE BUFFER POINTER (ES,BXI 2451 MUST POINT TO THE COLLECTION OF DESIRED ADDRESS FIELDS 2452 FOR THE TRACK. EACH FI'HD IS COMPOSED OF 4 BYTES, 2453 (C,H,R,NI, WHERE C = TRACK NUMBER. H=HEAD HUMBER, 2454 R = SECTOR HUMBER. N= NUMBER OF BYTES PER SECTOR 2455 100=128, 01=256, 02=512, 03=10241. 'THERE MUST BE ONE 2456 ENTRY FOR EVERY SECTOR ON THE TRACK. 2457 IS USED TO FINO THE REQUESTED SECTOR DURING READ/wRITE 2458 THIS INFORMATION ACCESS. 2:459 2460 ; DATA VARIABLE -- DISK_POINTER 2461 2462 DOUBLE WORD POINTER TO THE CURRENT SET OF DISKETTE PARAMETERS I OUTPIJT 2463 AH = STATUS OF OPERATION 2:464 STATUS BITS ARE DEFINED IN THE EQUATES FOR 2465 DISKETTE_STATUS VARIABLE IN THE DATA SEGMENT OF THIS 2466 MODULE. 2467 CY = 0 SUCCESSFUL OPERATION (AH=O ON RETURNI 2468 CY = 1 FAILED OPERATION (AH HAS ERROR REASON) 2469 FOR READ/WRITEIVERIFY DS,BX,DX,CH,Cl PRESERVED 2470 2471 AL = NUMBER OF SECTORS ACTUALLY READ ***** 2472 NOTE: 2473 2474 2475 THE OPERATION. ON READ ACCESSES. NO MOTOR START DELAY 2476 IS TAKEN, SO THAT THREE RETRIES ARE REQUIRED ON READS 2477 TO ENSURE THAT THE PROBLEM IS NOT DUE TO MOTOR 2478 2479 2480 START-UP. 1-----------------------------------------------------------------------ASSUME E(59 2481 ORG EC59 2482 OISKETTE_IO EC59 FB 2483 STI A-36 AL MAY NOT BE CORRECT IF TIME OUT ERROR OCCURS IF AN ERROR IS REPORTED BY THE DISKETTE CODE. THE APPROPRIATE ACTION IS TO RESET THE DISKETTE. THEN RETRY: System BIOS CS:CODE,DS:DATA,ES:DATA OEC59H PROC FAR ; INTERRUPTS BACK ON LaC OBJ LINE SOURCE ECSA 53 2484 PUSH 2485 PUSH ECSC IE 2486 PUSH ex ex os I SAVE ADDRESS EC5B 51 Eeso 56 2487 PUSH Sl I SAVE All REGISTERS DURING OPERATION 01 I SAVE SEGMENT REGISTER VALUE ECSf 57 2488 PUSH ECSF 55 2469 2490 PUSH 8P Et60 52 PUSH ox EC6l 8BEt 2491 NOV BP,SP EC63 f8D812 2492 CALL DDS EC66 f8lCOO 2493 CALL Jl I CALL THE REST TO ENSURE OS RESTORED fC69 880400 ECbC EaFOOI 2494 HOV BX,4 I GET THE MOTOR WAIT PARAMETER 2495 CALL GET_PARM fe6 F 88264000 fen I SET UP POINTER TO HEAD PAR" SET THE TIMER COUNT FOR THE MOTOR 2496 NOV MOTDR_COUNT.AH I 2497 MOV AH.DISKETTE_STATUS I GET STATUS OF OPERATION fe77 80FCOl 2498 CMP AH.l ; SET THE CARRY FLAG TO INDICATE Ee7A F5 811.264100 ; SUCCESS OR FAILtmE 2499 CMC Ee7B SA 2500 POP OX EC7t 50 2501 POP BP EC7D SF 2502 POP 01 Ee7E Sf 2503 POP 51 Ee7F IF 2504 POP EcaD 59 2505 POP os cx EC81 58 2506 POP ex I RECOVER ADDRESS EC82 CA020D 2507 RET 2 ; THROW AWAY SAVED FLAGS 2508 ; RESTORE ALL REGISTERS ENIlP 2509 2510 EC85 Jl PROC NEAR SAVE I EC85 SAFO 2511 HOV DH,Al I EC87 8026)F007F 2512 AND MOTOR_STATUS,07FH I INDICATE A READ OPERATION SECTORS IN DH ; AH=O ECat OAE4 2513 OR AH,AH ECBE 7427 2514 JZ DISK_RESET Ee90 FEte 2515 DEC AH fen. DISK_STATUS ; AH=l 2516 JZ EC94 C606410000 2517 MOV DISKETTE_STATUS,O ; RESET THE STATUS INDICATOR Ee99 BOFA04 2518 CMP DL.4 I TEST FOR DRIVE IN 0-3 RANGE Ee9C 7313 2519 JAE ; ERROR IF ABOVE EC9E FEte 2520 DEC J3 AH J2 I 7473 ECAO 7469 2521 JZ ECA2 FEee 2522 DEC EeM 7503 2523 JHZ ECAb E99500 2524 EtA9 2525 ; AH=2 ; AH=3 TEST_DISK_VERF JMP J2: ; TEST_DISK_VERF ; AH=4 EtA9 fEee 2526 DEC AH ECAB 7467 2527 JZ OIS~VERF ECAD FEte 2528 DEC AH ECAF 7467 2529 JZ DISKJORMAT ECBl 2530 ECBl C606410001 2531 HOV QISKETTE_STATUS,BAD_CMQ; ERROR CODE. NO SECTORS TRANSFERRED ECB6 C3 RET 2532: 2533 I AH=5 J3: Jl ; UNDEFINED OPERATION ENOP 2534 2535 ;----- RESET THE DISKETTE SYSTEM 2536 ECB7 2537 DISK_RESET PROC NEAR ECB7 BAf203 2538 EeBA FA 2539 MOV CLI ECBB A03FOD 2540 HOV AL,MOTOR_STATUS ; WHICH MOTOR IS ON ECBE 8104 2541 MOV CL,4 ; SH 1FT COUNT Eceo 02EO 2542 SAL AL,Cl ; MOVE MOTOR VALUE TO HIGH NYBBlE ECC2 11.620 2543 2544 TEST JNZ AL, 20H J5 ; SE LECT CORRESPONDING DRIVE ECt4 7S0C ECC6 A840 2545 TEST AL. 40H Ecca 7506 2546 JNZ J4 DX,03F2H ; ADAPTER CONTROL PORT ; NO INTERRUPTS ECCA 11.880 2547 TEST AL. aOH Ecce 7406 2548 JZ J6 ECCE FEeD 2549 INC AL Eeoo 2550 EeDO FEtO 2551 INC AL fC02 2552 fC02 FEtO 2553 INC AL ECD4 2554 ECD4 OC06 2555 J JlR1P IF MOTOR ONE IS ON I JUf1P IF MOTOR TWO IS ON ; JUMP IF MOTOR ZERO IS ON J4: J5: J6: AL,a I TURN ON INTERRUPT ENABLE fCob EE 2556 OUT OX,AL I RESET THE ADAPTER ECD7 C6063EOOOO 2557 MOV SEEK_STArus,O ; SET RECAL REQUIRED ON ALL DRIVES Eeoc C606410000 2558 MOV DISKETTE_STATUS. 0 ; SET OK STATUS fOR DISKETTE ftEI OC04 feB EE 2559 OR AL,4 ; TURN OFf RESET 2560 oor DX,.t,L ; TURN OFF THE RESET OR System BIOS A-37 LOC OBJ LINE ECE4 FB feES E82A02 SOURCE 2561 STI 2562 CAll ; REENABlE THE INTERRUPTS CHK_STAT_2 I DO SENSE INTERRUPT STATUS ; 2563 FOLLOWING RESET 2564 MOV EtEB 3etO 2565 eMP AL,OCOH ; TEST FOR DRIVE READY TRANSITION ECEO 7406 2566 JZ J7 ; EVERYTHING OK ECEF 800E410020 2567 OR DISKETTE_STATUS,8AD_NEC I SET ERROR CODE ECF4 C3 2568 EtEs ,0,04200 I IGNORE ERROR RETURN AND 00 OWN TEST RET 2569 2570 ;----- SEND SPECIFY COMMAND TO NEt 2571 J7: ; DRIVE_READY ECF5 2572 ECFS 8403 2573 feF7 E84701 2574 EeFA B80100 2575 ECFa E86eDl 2576 CALL GET_PARM ; EDOO 6B0300 2577 MOV 6X.3 ; SECOND BYTE PARM IN BLOCK E003 E86601 2578 CALL GET]ARM ; ED06 2579 Eo06 C3 2580 2581 AH,03H ; SPECIFY COMMAND CALL NEC_OUTPUT ; OUTPUT THE CONMAND MOV BX,I ; FIRST BYTE PARM IN BLOCK MOV J8: TO THE NEC CONTROLLER TO THE NEC CONTROLLER ; RESET_RET ; RETURN TO CALLER RET DISK_RESET ENOP 2582 2583 ; ----- DISKETTE STATUS ROUTINE 2584 ED07 2585 ED07 ,0,04100 2586 MOV mOA C3 2587 RET PROC NEAR A L, DISKETTE_STATUS ENOP 2588 2589 2590 ; ----- DISKETTE READ 2591 EDOB 2592 EO DB B046 2593 EOOD 2594 EO 00 E8B801 DISK_READ PROt NEAR MOV Al,046H 2595 CALL DNA_SETUP j EOIO 84E6 2596 MOV AH,OE6H ; SET UP PO CONNANO FOR NEC CONTROLLER E012 E836 2597 JMP SHORT IUCOPN I GO 00 THE OPERATION 2598 I READ COMMAND FOR DMA J9: ; DISK_READ_CONT DISK_READ SET UP THE DMA ENDP 2599 2600 j----- DISKETTE VERIFY 2601 E014 2602 E014 8042 2603 ED16 EBFS 2604 2605 DISK_VERF PROC NEAR MOV AL,042H I VERIFY COMMAND FOR oMA JMP J9 ; DO AS IF DISK READ DISK_VERF ENOP 2606 2607 ;----- DISKETTE FORMAT 2608 DISK_FORNAT PROt NEAR ED18 2609 ED18 a00E3F0080 2610 OR MOTOR_STATUS,80H I INDICATE WRITE OPERATION EOlD 804,0, 2611 MOV Al,04AH ; WILL WRITE TO THE DISKETTE [OIF E8A601 2612 CALL DHA_SETUP ; SET UP THE DMA f022 8440 2613 MOV AH.04DH ; ESTABLISH THE FORMAT COMMAND EO.24 EB24 2614 JMP SHORT RlrCOPN ; 00 THE OPERATION f026 2615 f026 BB0700 2616 MOV BX.7 ; GET THE E029 E84001 2617 CAll GET_PARM ; E02e 880900 2618 MOV BX.9 ; GET THE ED2F £63,0,01 2619 CALL GET_PARM ; E032 aBOFCD 2620 MOV BX,15 ; GET THE j I CONTINUATION OF RICOPN FOR FHT JiO: BYTES/SECTOR VALUE TO NEC SECTORS/TRACK VALUE TO NEC GAP LENGTH VALUE TO NEC E035 £83401 2621 CALL GET_PARM E038 B81100 2622 MOV BX.17 ; GET THE FILLER BYTE E038 E9A800 2623 JMP J16 ; 2624 DISK_FORMAT TO THE CONTROLLER ENDP 2625 2626 1----- DISKETTE WRITE ROUTINE 2627 E03£ 2628 ED3E 800E3FOQ80 2629 E043 804,0, 2630 E045 E88001 2631 E048 84C5 2632 2633 PROC NEAR j MOV AL.04AH CAll DMA_SETUP HOV AH,OCSH DISK_WRITE INDICATE WRITE OPERATION ; DMA WRITE COMMAND ; NEC COMMAND TO WRITE TO DISKETTE EHOP 2634 2635 j----- ALLOW WRITE ROUTINE TO FALL nITO RlrCOPN 2636 2637 A-38 j ---------------------------------------------------------------- System BIOS LOC OBJ LINE 2638 SOURCE ; RW_OPN 2639 THIS ROUTINE PERFORMS THE READIWRITE/vERIFY OPERATION ED4A 2640 2641 ; ---------------------------------------------------------------- ED4A 7308 2642 JNe J11 ED4C C606410009 2643 MOV DISKETTE_STATUS,DHA_BOUNOARY E051 BODO 2644 NOV AL,O E053 C3 2645 E054 2646 E054 50 2647 RW_OPN PROC NEAR RET ; TEST FOR DHA ERROR ; SET ERROR ; NO SECTORS TRANSfERRED I RETURN TO MAIN ROUTINE Jll: PUSH AX I SAVE TIlE COHMAND 2648 2649 ; ----- TURN ON THE MOTOR ANO SELECT TIlE DRIVE 2650 f055 51 2651 PUSH CX ; SAVE THE TIS PARHS E056 8ACA 2652 MOV Cl,Ol ; GET DRIVE NUMBER AS SHIFT COUNT EOSS BOOI 2653 MOV Al,l ED SA 02EO 2654 SAL AL,CL E05C FA 2655 eLI MASK fOR DETERMINING HOTOR BIT SHIFT THE MASK BIT I NO INTERRUPTS WHILE DETERMINING HOTOR STATUS 2656 EDSO C6064000FF 2657 MOV MOTOR_COUNT ,OFFH E062 84063FOO 2658 TEST Al,MOTOR_STATUS JNZ ; SET LARGE COUNT DURING OPERATION TEST THAT MOTOR FOR OPERATlNG If RUNNING, SKIP THE WAIT J14 E06b 7531 2659 E068 80263fOOFO 2660 AND MOTOR_STATUS,OFOH f06D 08063FOO 2661 OR MOTOR_STATUS,Al I E071 FB TURN OFF All MOTOR BITS TURN ON THE CURRENT MOTOR INTERRUPTS BACK ON 2662 STI E072 BOlO 2663 NOV Al,lOH ; MASK BIT E074 o2EO 2664 SAL AL,Cl ; DEVElOP BIT MASK FOR MOTOR ENABLE f076 DAC2 2665 OR AL,DL ; GET DRIVE SELECT BITS IN E078 ceDe 2666 OR AL,OCH ; NO RESET, ENABLE DMA/INT f07A 52 2667 PUSH OX ; SAVE REG E07B BAF203 2666 MOV OX,03F2H ; CONTROL PORT ADDRESS f07E EE 2669 OUT OX,Al POP OX ED7F SA 2670 I RECOVER REGISTERS 2671 2672 ;----- WAIT FOR MOTOR IF WRITE OPERATION 2673 E080 F6063F0080 2674 TEST MOTOR_STATUS,60H E085 7412 2675 JZ J14 ; NO, CONTINUE WITHOUT WAIT IS THIS A WRITE ED87 861400 2676 MOV BX,20 ; GET THE MOTOR WAIT EDBA EBOFOD 2677 CAll GET_PARM ; E08D OAE4 2678 OR AH,AH I EoaF 2679 ED8F 7408 2680 JZ J14 ; EXIT WITH TIME EXPIRED ED91 28C9 2681 SUB ex,cx ; SET UP 1/8 SECOND LOOP TINE E093 2682 E093 E2FE 2683 lOOP J13 ; WAIT FOR THE REQUIRED TlME ED95 FEee 2684 DEC AH ; DECREMENT TINE VALUE E097 fBF6 2665 JMP J12 E099 2666 E099 FB 2667 STI 2666 POP ED9A 59 J12: PARAMETER TEST FOR NO WAIT I TEST_WAIT_TINE J13: J14: ; ARE WE DONE YET I MOTOR_RUNNING ; INTERRUPTS BACK ON FOR BYPASS WAIT ex 2689 2690 ;----- 00 THE SEEK OPERATION 2691 ; HOVE TO CORRECT TRACK ED9B fBOFOO 2692 E09E 58 2693 POP AX ; RECOVER COMMAND ED9F SAFe 2694 MOV BH,AH ; SAVE COMMAND IN BH CAll SEEK 2695 MOV OH,O ; SET NO SECTORS READ IN CASE OF ERROR fOAl 7248 2696 JC J17 ; I f ERROR, THEN EXIT AFTER MOTOR OFF EDAS BEFOED90 2697 MOV SI,OfFSET J17 2698 PUSH SI EOAI B600 EDA9 56 ; DUMMY RETURN ON STACK FOR NEC_OUTPUT SO THAT IT WIll RETURN TO MOTOR OFF ; 2699 LOCATION 2700 2701 ;----- SEND OUT THE PARAMETERS TO THE CONTROLLER 2702 EDAA E89400 2703 CALL NEC_OUTPUT ; OUTPUT THE OPERATION COMMAND EOAD SA660l 2704 MOV AH,EBP+IJ ; GET THE CURRENT HEAD NUMBER EDBO 00E4 SAL SAl AH.l AH,l I MOVE IT TO BIT 2 EDBl 00E4 2705 2706 EDB4 80E404 2707 AND AH,4 ; ISOLATE THAT BIT EOB7 OAfl 2708 OR AH,DL ; OR IN THE DRIVE HUMBER EDB9 E88500 2709 CAll NEC_OUTPUT 2710 2711 ;----- TEST FOR FORMAT COMMAND 2712 fDBC 80FF4D 2713 eMP BH ,04DH ; IS THIS A FORMAT OPERATION fOSF 7503 2714 JNE J15 ; NO. CONTINUE WITH R/W/V System BIOS A-39 LaC OBJ LINE SOURCE JHP EDtl E962FF EDe4 EDC4 8AES 2715 2716 2717 EDt6 E87800 2718 CALL NEe_OUTPUT EDC9 8A6601 2719 tIDy AH,IBP+l] EDCC E87200 EDeF 8AEJ 2720 2721 CALL NEC_OUTPUT HOV EDDI f86DOO 2722 2723 CALL NEC_OUTPUT HOY BX.7 EDD4 880700 fDE9 E88000 2724 272.5 2726 2727 2728 2729 2730 2731 EDEC 5£ 2732 EOD? E89200 EDDA 880900 fOOD E88COO EDEO BBOBOO EDE] E88600 EDE6 BeaDOD EDE9 J10 my I CYLINDER NlII1BER AH.CL I HEAD Nl.Jt'EER fROM STACK I SECTOR HI.l1BER I BYTES/SECTOR PARH fROI1 BLOCK CALL GET_PARH ; MOV BX.9 CALL GET_PARH I EDT PARM fROI1 BLOCK ; TO THE NEC MOV BX.ll I GAP LENGTH PARM fROH BLOCK CALL GET_PARH ; tIOV Bx.n J DTL PARM fRotI BLOCK JI6; TO THE NEC TO THE NEC I RioCOPNJINISH I POP SI TO THE NEC ; CAN NOW DISCARD THAT DUtItIY ; 2733 2734 2735 I I f SO. HANDLE SPECIAL J15: RETURN ADDRESS 1----- LET THE OPERATION HAPPEN '7>6 EOED f84301 2737 EDFO 2138 fOFO 7245 EDF! E87401 EDFS 723F 2739 JC J21 ; LOOK fOR ERROR 2740 CALL RESULTS ; GET THE NEC STATUS 2741 JC J20 ; LOOK fOR ERROR I WAlT fOR THE INTERRUPT J17: I MOTOR_Off 2742 2743 1----- CHECK THE RESULTS RETURNED BY THE CONTROLLER 2744 EDF7 FC 2745 CLO fDFS 8E4200 2746 MDY SI.OFFSET NEC_STATUS ; POINT TO STATUS FIElD EDF8 At 2747 Loos NEC_STATUS I GET 5TO EOFt 24tO 2748 AND AL.OCOH I TEST FOR ~HAL TERMINATION EDFE 7438 2749 JZ J22 I OPN_OK EEOD 3e40 2750 tMP AL.040H ; TEST FOR ABNORMAL TERMINATION EE02 7529 2751 JNZ J!8 ; NOT ABNORMAL, BAD NEt I SET THE CORRECT DIRECTION 2752 2753 1----- ABNORt1AL TERMINATION. FItIJ OUT WHY 2754 EE04 At 2755 Loos NEt_STATUS i GET STl fEDS ODED 2756 SAL AL.l ; TEST FOR EDT FDUm fED7 8404 2757 IIOY £E09 7224 2758 J19 AL.I fEOD ODED 2759 2760 JC SAL I RWJAlL EEDB ODED AL.I I TEST FOR CRC ERROR fEDF 8410 2761 SAL HOY AH.BAD_CRC EEl! 7ZIC 2762 JC J19 I RWJAIl EE13 ODED 2763 SAL AL.! ; TEST FOR DMA OVERRUN EElS 6408 2764 HOY AH,8AD_OtIA EE17 7216 2765 JC J19 E£19 ODED 2766 SAL AL •• EEIB ODED 2767 SAL AL.! EEID EEIF fEZ! fEU 840lt 720E ODED 8403 2768 HOY AH, RECORD_NOTJND 2769 JC J19 2770 SAL HOY .U.l 277! Ef25 72:08 2772 JC J19 ; RN_FAIL I TEST HISSING ADDRESS HARK AH,WRITE_PROTECT 2773 SAL AL,I EE29 8402- 2774 my AH.BAO_ADDR_HARK EE2B 7202 2775 JC J19 fE27 ODED I RWJAlL ; TEST FOR RECORD NOT fOlNJ ; RWJAlL ; TEST FOR WRITE_PROTECT ; RWJAIl 2776 2777 ;----- NEC tlJST HAVE fAILED 2778 J18: EE2D 2779 EE2D 8420 2780 fE2F EEZF 08264100 EE33 f87801 2782 OR DISKETTE_STATUS,AH '2783 CALL NUteTRANS 2781 1 RN-FAIL J19; 2784 EE36 C3 2785 EE37 EE37 E82fOl 2786 2787 CALL EE3" C3 2788 RET RET ; RETURN TO CALLER I RN_ERR_RES J21: RESULTS 2789 2790 ,----- OPERATION WAS SUCCESSFUL 2791 A-40 System BIOS ; HOW MANY WERE REALLY TRANSFERRED I RN_ERR J20: EE36 I FLUSH THE RESULTS BUFFER LOC OBJ EE3B LINE 2792 SOURCE J22: EE3B E87001 2793 CALL NUM_TRANS I HOW MANY GOT MOVED EE3E 32E4 2794 XOR AH,AH I NO ERRORS EE40 C3 2795 2797 2798 RET ; -----------------------------------------------------------------------; NEC_OUTPUT 2799 THIS ROUTINE SENDS A BYTE TO THE NEC CONTROLLER AFTER TESTING 2800 FOR CORRECT DIRECTION AND CONTROLLER READY THIS ROUTINE WILL 2801 TIME OUT IF THE BYTE IS NOT ACCEPTED WITHIN A REASONABLE 2802 AMOUNT Of TIME, SETTING THE DISKETTE STATUS ON COMPLETION. 2803 INPUT 2804 2805 (AH) 2806 CY =0 SUCCESS 2807 CY = 1 FAILURE -- DISKETTE STATUS UPDATED 2808 IF A FAILURE HAS OCCURRED, THE RETt.lRN IS MADE ONE LEVEl : 2809 HIGHER THAN THE CALLER OF NEC_OUTPUT. 2810 THIS REMOVES THE REQUIREMENT OF TESTING AFTER EVERY 2811 2812 EE41 BYTE TO BE OUTPUT ; OUTPUT 2813 2814 CALL OF NEC_OUTPUT. (All DESTROYED J-----------------------------------------------------------------------NEC_OUTPUT PROC EE41 52: 2815 PUSH OX EE42 51 2816 PUSH ex NEAR ; SAVE REGISTERS EE43 BAF403 2817 MOY DX,03F4H EE46 33C9 2818 XOR CX,CX ; COUNT FOR TIME OUT EE48 2819 EE48 EC 2820 IN AL,DX ; GET STATUS EE49 A840 ; STATUS PORT J23: 2821 TEST AL,040H ; TEST DIRECTION BIT EE4B 740C 2822 JZ J25 ; DIRECTION OK EE4D E2F9 2823 LOOP J23 EE4F 2824 EE4F 800E410080 2825 OR DISKETTE_STATUS, TIME_OUT EE54 59 2826 J24: POP ex ; TIME_ERROR POP OX EE56 58 2828 POP AX EE57 F9 2829 STe EE58 C3 2830 RET EE55 5A 2827 I SET ERROR CODE AND RESTORE REGS I DISCARD THE RETURN ADDRESS ; INDICATE ERROR TO CALLER EE59 2831 EE59 33C9 2832 J25: XOR ex,cx ; RESET THE COUNT EE5B 2833 EE5B EC 2834 IN AL,OX I GET THE STATUS EE5C AB80 2835 TEST AL,oaOH ; IS IT READY EE5E 7504 2836 JNZ J27 ; YES. GO OUTPUT EE60 E2F9 2837 LOOP J26 I COUNT DOWN AND TRY AGAIN EE62 EBEB 2838 JMP J24 ; ERROR CONDITION J26: EE64 2839 EE64 8AC4 2840 MOY AL,AH ; GET BYTE TO OUTPUT EE66 B2F5 2841 MOY DL,OF5H ; DATA PORT (3F5) EE68 EE 2842 OUT OX,AL ; OUTPUT THE BYTE EE69 59 2843 POP ex I RECOVER REGISTERS EE6A SA 2844 POP OX EE6B C3 2845 RET 2846 J27: I NEC_OUTPUT OUTPUT ; CY = 0 FROM TEST INSTRUCTION ENDP 2847 j------------------------------------------------------------------------ 2848 I GET _PARM 2849 THIS ROUTINE FETCHES THE INDEXED POINTER FROM THE DISK_BASE 2850 BLOCK POINTED AT BY THE DATA VARIABLE DISK]OINTER. A BYTE FROM: 2851 THAT TABLE 15 THEN MOVED INTO AH. THE INDEX Of THAT BYTE BEING THE PARM IN BX 2852 2853 ; ENTRY -- 2854 BX = INDEX OF BYTE TO BE FETCHED * 2: 2855 IF THE LOW BIT OF BX IS ON, THE BYTE IS IMMEDIATELY OUTPUT 2856 TO THE NEC CONTROLLER 2857 2858 I EXIT -- AH = THAT BYTE FROM BLOCK EE6C 2859 2860 EE6C IE 2861 as ; SAVE SEGMENT EE60 2BCO 2862 SUB AX , J,Y.. ; ZERO TO AX EE6F 8ED8 2863 HOY OS,AX 2864 ASSUME oS:ABSO i -----------------------------------------------------------------------GET_PARM PRDC NEAR PUSH EE7l C5367800 2865 lOS SI,DISK_POINTER POINT TO BLOCK EE75 DlEB 2866 2867 SHR BX,I DIVIDE BX BY 2. AND SET FUG EE77 8A20 2868 MOY AH,rSI+BX] GET THE WORD FOR EXIT System BIOS A-41 LOC OBJ EE79 iF LINE SOURCE 2869 POP OS 2870 ASSUME DS:OATA EE7A nt5 2871 JC NEt_OUTPUT EE7t C3 2872 ; IF FLAG SET. OUTPUT TO CONTROLLER I RETURN TO CALLER ENDP 2873 2874 2875 I RESTORE SEGMENT ; -----------------------------------------------------------------------; SEEK 2876 THIS ROUTINE WILL MOVE THE HEAD ON THE NAMED DRIVE TO THE 2877 NAMED TRACK. 2878 2879 2880 IOU 2881 2882 IF THE DRIVE HAS NOT BEEN ACCESSED SINCE THE DRIVE RESET COHMAND WAS ISSUED, THE DRIVE WILL BE RECALIBRATED. , INPUT (CH) = DRIVE = TRACK TO SEEK ON TO SEEK TO ; OUTPUT 2883 CY = 2884 CY =1 2885 (AX) 0 SUCCESS FAILURE -- DISKETIE_STATUS SET ACCORDINGLY DESTROYED EE70 2886 2887 Ef70 B001 2888 ;-----------------------------------------------------------------------SEEK PROC NEAR AL,1 ; ESTABLISH MASK FOR RECAL TEST EE7F 51 2889 PUSH ex ; SAVE INPUT VALUES EESO SACA 2890 MOY CL,DL I GET DRIVE VALUE INTO CL EEe2 Olto 2691 ROL AL,CL ; SHIFT IT BY THE DRIVE VALUE EE84 59 2692 POP ex ; RECOVER TRACK VALUE fE85 84063EOO 2893 TEST AL,SEEK_STATUS I EE89 7513 2694 JNZ JZ. I NO_RECAl SEEK_STATUS,.A.L ; TURN ON THE NO RECA L BIT IN FLAG ; RECAlIBRATE COHMAND MOY EEBB 08063EOO 2895 OR EESF 8407 2896 MaY AH,07H EE91 EBADFF 2697 CALL NEC_OUTPUT EE94 8AE2- 2898 MOY AH,Dl TEST FOR RECAL REQUIRED EE96 E8ASFF 2899 CALL NEC_OUTPUT EE99 E87600 2900 CAll CHK_STAT_2 ; GET THE IHTERUPT AND SEHSE INT STATUS EE9C 7229 2901 Je J3Z ; SEEK_ERROR ; OUTPUT THE DRIVE NUMBER 2902 2903 ;----- DRIVE IS IN SYNCH WITH CONTROLLElh SEEK TO TRACK 2904 EE9E 290S J2S: EE9E B40F 2906 MaY AH,OFH EEAD E89EFF 2907 CALL NEC_OUTPUT EEA! 6AE2 2908 MOY AH,DL ; SEEK COMMAND TO NEC I DRIVE NUMBER EEAS E899FF 2909 CALL NEC_OUTPUT EEAa 8AE5 2910 MOY AH,CH EEAA E894Ff 2911 CALL NEC_OUTPUT EEAD E86200 2912 CALL CHK_STAT_2 ; TRACK HUMBER ; GET ENDING INTERRUPT AND ; 2913 SENSE STATUS 2914 2915 ;----- WAIT FOR HEAD SETTLE 2916 ; SAVE STATUS FLAGS EESO 9C 2917 PUSHF fEB 1 BB1200 2918 MOY eX,ls EEB4 E8B5FF 2919 CALL GET_PARN HB7 51 2920 PUSH ex HBB HBB B92602 2921 ; GET HEAO SETILE PARAMETER i SAVE REGISTER I HEA.D_SETIlE J29: 2922 MOY CX,S50 ; 1 MS LOOP fEBB OAE4 2923 OR AH.AH I TEST FOR TINE EXPIRED fEBO 7406 2924 JZ J31 EEBF 2925 EEBF E2FE 292:6 lOOP J30 EECI FEte 2927 OEe AH i DECREMENT THE COUNT EEt3 EBF3 2928 JMP JZ9 ; 00 IT SOME MORE EEtS EEtS 59 2929 POP ex ; RECOVER STATE EEC6 90 2931 EEt7 2932 EEt7 C3 2933 J30; ; DELAY FOR 1 MS J31 : 2930 POPF J32: ; SEEK_ERROR ; RETURN TO CALLER RET 2934 SEEK 2935 ; ------------------------------------------------------------------------ 2936 ; DNA_SETUP 2937 2938 THIS ROUTINE SETS UP THE DNA FOR READ!WRITE/vERIFY OPERATIONS. ; INPUT 2939 (AU 2940 2941 ENDP = MODE BYTE FOR THE DNA (ES:8X) - ADDRESS TO READ!WRITE THE DATA ; OUTPUT 2942 (AX) DESTROYED 2:943 EEce 2944 EEte 51 2945 A-42 DMA_SETUP System BIOS PUSH PROC ex NEAR I SAVE THE REGISTER LOC OBJ LINE SOURCE EEC9 FA 2946 ell EECA E60C 2947 OUT EEce 50 2948 PUSH AX EEeD 58 2949 POP AX , NO MORE INTERFNIl SPFC':TFY RYTF MOTOR_WAIT ; WAIT AFTER OPH TIL MOTOR OFF LABEL BYTE 11001111B I SRT=C, HD UNLOAD=OF - EFC9 25 3191 DB EFeA 02 3192 DB EFCB 08 3193 DB EFCC ZA 3194 DB 02AH ; GAP LENGTH EFce FF 3195 DB OFFH ; Dll EFeE 50 1ST SPECIFY BYTE ; 512 BYTES/SECTOR ; EDT ( LAST SECTOR ON TRACK I 3196 DB OSOH ; GAP LENGTH FOR FORMAT EfCf F6 3197 DB OF6H ; FILL BYTE FOR FORMAT EFDO 19 3198 DB 25 ; HEAD SETTLE TIME (MILLISECONDS) EFOI 04 3199 DB 4 ; MOTOR START TIME (1/8 SECONDS) 3200 3201 ;--- 1HT 17 ------------------------------------------------------------- 3202 ; PRINTER_IO 3203 3204 nilS ROUTINE PROVIOES COI1I1lJNICATION WITH THE PRINTER INPUT 3205 (AH1=O PRINT THE CHARACTER IN (All ON RETURN, AH=1 IF CHARACTER COULD NOT BE PRINTED 3206 (TINE OUT I. OTHER BITS SET AS ON NORMAL STATUS CALL 3207 3208 (AHI=l INITIALIZE THE PRINTER PORT RETURNS WITH IAH) SET WITH PRINTER STATUS 3209 3210 (AHI=2 READ THE PRINTER STATUS INTO I AH I 3211 7 6 4 2-1 3212 I I I I I I I I I 1_ 3213 3214 I_TIME OUT : UNUSED 1 = I/O ERROR 1 = SELECTED I 3215 0 1 = OUT OF PAPER 3216 3217 1 = ACKNOWLEDGE 3218 1 = NOT BUSY 3219 3220 (OXI = PRINTER 3221 TO BE USED (0,1.21 CORRESPONDING TO ACTUAL VALUES IN PRINTER_BASE AREA 3222 3223 ; DATA AREA PRINTER_BASE CONTAINS THE BASE ADDRESS OF THE PRINTER 3224 ; CAROlS) AVAILABLE (LOCATED AT BEGINNING OF DATA SEGMENT. 3225 ; 408H ABSOLUTE. 3 WORDS) 3226 3227 1 DATA AREA PRINT_TIN_OUT (BYTE) MAY BE CHANGED TO CAUSE DIFFERENT 3228 ; TIME-OUT WAITS. DEFAUlT=20 322'i1 3230 ; REGISTERS 3231 3232 AH IS MODIFIED ALL OTHERS UNCHANGED ;-----------------------------------------------------------------------ASSUME 3233 ORG CS:COOE ,DS:DATA EFOZ 3234 EFOZ 3235 EFOZ fB 3236 STI EFD3 IE 3237 PUSH OS EFD4 52 3238 PUSH OX EFOS 56 3239 PUSH SI HOb 51 3240 EF07 53 3241 PUSH BX EFDB E8630F 3242 CALL DDS HOB BBF:?: PRINTER_IO PUSH OEFD2H PROC FAR INTERRUPTS BACK ON SAVE SEGMENT ex 3243 MOV SI,OX ; GET PRINTER PARM EFDD 8A5e78 3244 MOV BL,PRINT TIM Ol1T[SIJ fFEO 01E6 3245 SHL 51,1 ; LOAD TIME -OUT PARM I WORD OFFSET INTO TABLE EFEZ 685408 3246 MOV ox, PRINTER_BASEl 51 J ; GET BASE ADDRESS FOR PRINTER CARD EFES OB02 3247 OR OX,OX ; TEST OX FOR ZERO, ; 3248 INDICATING NO PRINTER EFE7 740C 3249 JZ Bl ; RETURN EFE9 OAE4 3250 OR AH,AH ; TEST FOR (AHI=O fFEB 740E 3251 JZ B2 ; PRINT_Al fEte 3252 DEC AH ; TEST FOR (AH)=1 EFEf 743f 3253 JZ 88 EfED A-46 System BIOS LOC OBJ LINE SOURCE EFF 1 FECC 3254 DEC AH I TEST FOR (AH) =2 EFF3 7428 3255 JZ OS ; PRINTER STATUS EFF5 3256 EFFS 58 Bl: ; RETURN pop OX EFF6 59 3257 3258 POP ex EFF7 SE 3259 POP SI ; RECOVER REGISTERS EFFS SA 3260 POP ox J RECOVER REGISTERS EFF9 IF 3261 POP os EFFA Cf 3262 IRET 3263 3264 ; ------ PRINT THE CHARACTER IN (AU 32:65 EHS 32:66 EFFB 50 32:67 PUSH AX ; SAVE VALUE TO PRINT EFFe EE 3268 OUT OX,AL I OUTPUT CHAR TO PORT EFFO 42 32:69 IHC OX I POINT TO STATUS PORT EFFE 32:70 EFFE ZBC9 3271 SUB eX,ex 82:: 83: FOOO 3272: FOOD EC FOOl BAED F003 ABBD 3273 IN AL,OX ; GET STATUS 32:74 MOV AH.AL ; STATUS TO AH ALSO 3275 TEST AL.SOH ; IS THE PRINTER CURRENTLY BUSY F005 750E 3276 JNZ 84 ; OULSTROBE F007 E2F7 32:77 LOOP 83_1 ; TRY AGAIN F009 FEeB 3278 DEC BL ; DROP LOOP COUNT F006 75Fl 3279 JNZ B3 ; GO TILL TIMEOUT ENDS FOOD 80CCOI 3280 OR AHol i SET ERROR FLAG FOlD 80E4F9 32:81 AND AH,OF9H i TURN OF F THE OTHER BITS F013 EBB 32:82: JMP SHORT 87 ; RETURN WITH ERROR FLAG SET F015 32:83 F015 BODO 32:84 MOV AL,OOH ; SET THE STROBE HIGH FOl742 32:85 tHC ox ; STROBE IS BIT 0 OF PORT C OF 8255 F018 EE 32:86 OUT OX,AL F019 BOOC 32:87 MOV AL,OCH FO 18 EE 3288 OUT OX,AL FDIC 58 3289 POP AX 84: ; OUT_STROBE ; SET THE STROBE LOW ; RECOVER THE OUTPUT CHAR 3290 3291 j------ PRINTER STATUS 32:92 FOlD 3293 FO 10 50 3294 FOIE 32:95 FOIE 865408 3296 85: PUSH AX NOV DX.PRINTER_BASE[ 51 J I SAVE AL REG B6: F021 42 32:97 INC OX F022 EC 32:98 3299 IH NOV AL,OX F023 BAEO F025 60E4F8 3300 AHD AH.OF8H F028 3301 F026 SA 3302: POP OX ; RECOVER AL REG F029 BAC2 3303 MOV AL,DL ; GET CHARACTER INTO AL F02B 80F448 3304 XOR AH.48H i FLIP A COUPLE OF BITS F02E EBes 3305 JMP 01 ; RETURN FROM ROUTINE ; GET PRINTER STATUS AH.AL 87: ; TURN OFF UNUSED BITS i STATUS_SET 3306 3307 ; ------ INITIALIZE THE PRINTER PORT 3308 B8: F030 3309 F030 50 3310 AX I F031 42 3311 INC OX ; POINT TO OUTPUT PORT F032 42 3312 INC OX F033 B008 3313 3314 MOV AL,8 F035 EE OUT OX.AL F036 B8E803 3315 NOV AX.IOOO F039 3316 F039 48 3317 DEC AX Fa3A 75FO 3318 3319 JHZ 09 F03e BOOC PUSH B9: 3321 F03F EBOD 3322 F041 62El 3323 3324 3325 ; SET INIT LINE lOW ; INIT_lOOP MOV AL.OCH OUT OX.AL ; LOOP FOR RESET TO TAKE ; NO INTERRUPTS. NON AUTO LF. ; 3320 F03E EE SAVE AL HIIT HIGH O. ENDP C2 OW C24 J RETURN ADDRESS FOR DUMMY STACK 3326 3327 ;--- INT 10 ------------------------------------------------------------- 3328 ; VIDEO_IO 3329 THESE ROUTINES PROVIDE THE CRT INTERFACE 3330 THE FOLLOWING FUNCTIONS ARE PROVIDED: System BIOS A-47 LOC OBJ LINE SOURCE 3331 IAHI=O SET MODE (All CONTAINS MODE VALUE 3332 (AU=O 40X2:5 Bioi (POWER ON DEFAULT) 3333 3334 3335 (AU=l 40X25 COLOR 3336 3337 3338 3339 GRAPHICS MODES 3340 CRT MODE=7 BOX25 BLW CARD I USED INTERNAL TO VIDEO ONL Yl (Al )=2: BOX2:5 Bioi {Al )=3 eOX25 COLOR (AL )=4 32:0X200 Bioi 640XlOO Bioi *** 3341 320XlOO COLOR {All:::5 (All=6 NOTE Bioi MODES OPERATE SAME AS COLOR MODES. BUT COLOR BURST IS NOT ENABLED 3342 3343 (AH)=l SET CURSOR TYPE (CH 1:;: 3344 3345 BITS 4-0 = START LINE FOR CURSOR ** ** 3346 (CLl = (AH ) =2 SET CURSOR POSITION (BH I (-'H)=3 = READ CURSOR POSITION ON EXIT (oH,DLl (AH )=4 READ LIGHT PEN POSlnON (AH I = 0 -- LIGHT PEN SWITCH NOT DOWN/NOT TRIGGERED (AH I = 1 -- VALID LIGHT PEN VALUE IN REGISTERS (DH.DLl = ROW , COLUMN OF CHARACTER LP POSN (CHI = RASTER LINE (0-199) 3362 (BX) = PIXEl COLUMN (0-319,6391 IAHJ=5 SelECT ACTIVE DISPLAY PAGE (VALID ONLY FOR ALPHA MODESI (AHI=6 SCROLL ACTIVE PAGE UP 3364 {ALl=NEW PAGE VAL (0-7 FOR MODES OU, 0-3 FOR MODES 2&31: (All = NUNBER OF LINES, INPUT LINES BLANKED AT BOTTOM OF WINDOW 3368 3369 (CH,Cll = ROW,COLUNN OF UPPER LEFT CORNER OF SCROLL 3370 (OH,Dll = ROW,COLUMN OF LOWER RIGHT CORNER OF SCROLL 3371 3372 3373 3374 AL = 0 MEANS BLANK ENTIRE WINDOW (BH I = ATTRIBUTE TO BE USED ON BLANK LINE {AH 1=7 SCROLL ACTIVE PAGE DOWN tAll = NUMBER OF LINES, INPUT LINES BLANKED AT TOP OF WINDOW 3375 AL = 0 MEANS BLANK ENTIRE WINDOW 3376 {CH.CLl = ROW.COLUMN OF UPPER LEFT CORNER OF SCROLL 3377 3378 3379 {DH.OLl = ROW.COLUNN OF LOWER RIGHT CORNER OF SCROLL (BHI = ATTRIBUTE TO BE USED ON BLANK LINE 3380 CHARACTER HANDLING ROUTINES 3381 3382 (AH I = 8 READ ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION 3383 3384 3385 3386 3387 3388 (BHI = DISPLAY PAGE fVALID FOR ALPHA HODES ONLYI ON EXIT: (All = CHAR READ (AHI = ATTRIBUTE OF CHARACTER READ (ALPHA HODES ONLYI (AH) = 9 WRITE ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION (BHI = DISPLAY PAGE (VALID FOR ALPHA MODES ONLY) 3389 (CX) = COUNT OF CHARACTERS TO WRITE 3390 (AL I = CHAR TO WRITE 3391 (BU = ATTRIBUTE OF CHARACTER (ALPHA )/COLOR OF CHAR 3392 3393 3394 3395 3396 3397 3398 3399 (GRAPHICS I SEE NOTE ON WRITE DOT FOR BIT 7 OF BL = 1. (AH) = 10 WRITE CHARACTER ONLY AT CURRENT CURSOR POSITION CBHI = DISPLAY PAGE (VALlO FOR ALPHA MODES ONLY) (CX I = COUNT OF CHARACTERS TO WRITE I AL J = CHAR TO WRITE FOR READ/WRITE CHARACTER INTERFACE WHILE IN GRAPHICS MODE. llIE CHARACTERS ARE FORMED FROM A CHARACTER GENERATOR IMAGE 3400 MAINTAINED IN THE SYSTEM ROM. 3401 ARE CONTAINED THERE. 3402 CHARS. THE USER MUST INITIALIZE THE POINTER AT ONLY THE 1ST 12:8 CHARS TO REAO/wRITE THE SECOND 128 3403 INTERRUPT 1FH (LOCATION 0007CH) TO POINT TO THE lK BYTE 3404 TABLE CONTAINING THE COOE POINTS FOR THE SECOND 3405 3406 3407 A-48 ROW,COLUMN OF CURRENT CURSOR ON EXIT: 3358 3359 3360 3361 3365 3366 3367 = (CH,CLl = CURSOR MODE CURRENTLY SET 3357 3363 (0,0) IS UPPER LEFT PAGE NUMBER (MUST BE 0 FOR GRAPHICS HODES) (BHI = PAGE NltIBER (MUST BE 0 FOR GRAPHICS NODES) 3353 3354 3355 3356 BITS 4-0 = END LINE FOR CURSOR (DH,DLl = ROW,COLUMN 3350 3351 3352: SETTING BIT 5 OR 6 WILL CAUSE ERRATIC BLINKING OR NO CURSOR AT ALL 3347 3348 3349 HARDWARE WILL ALWAYS CAUSE BLIN System BIOS 12:8 CHARS (128-255l. FOR WRITE CHARACTER INTERFACE IN GRAPHICS MODE, THE REPLICATION : FACTOR CONTAINED IN (CXI ON ENTRY WILL PRODUCE VALID LOC OBJ LINE SOURCE 3408 3409 3410 RESULTS ONLY FOR CHARACTERS CONTAINED ON THE SAME ROW. CONTINUATION TO SUCCEEDING LINES WILL NOT PRODUCE CORRECtlY. 3411 3412 GRAPHICS INTERFACE 3413 (AH) = 11 SET COLOR PALETTE 3414 IBH) = 3415 (BLI = COLOR PALETTE COLOR 10 BEING SET (0-127) VALUE TO BE USED WITH THAT COLOR 10 3416 NOTE: FOR THE CURRENT COLOR CARD, THIS ENTRY POINT 3417 HAS MEANING ONLY FOR 320X200 GRAPHICS. 3418 COLOR ID 3419 COLOR ID =0 SElECTS THE BACKGROUND COLOR (O-ISI: =1 SELECTS THE PALETTE TO BE USED: 3420 o = GREEN( 1 JlRED( 2 IIYELLOW(31 3421 1 3422 3423 = CYAN! I I/MAGEHTA(2)IWHITE(31 IN 40X2S OR 80X25 ALPHA MODES. THE VALUE SET FOR PALETTE COLOR 0 INDICATES THE 3424 BORDER COLOR TO BE USED (VALUES 0-31, 3425 WHERE 16-31 SELECT THE HIGH INTENSITY 3426 BACKGROUND SET. (AH) 3427 = 12 WRITE DOT 3428 (OX 1 3429 (CX I 3430 (All = ROW = = NUMBER COLUMN NUMBER COLOR VALUE = 1, 3431 IF BIT 7 OF AL 3432 EXCLUSIVE OR '0 WITH THE CURRENT CONTENTS OF 3433 THEN THE COLOR VALUE IS THE DOT fAH) 3434 = 13 3435 REAO DOT (OX) = ROW NUMBER 3436 (CX) = COLUMN HUMBER 3437 (AL) RETURNS THE DOT REAO 3438 3439 ; ASCII TELETYPE ROUTINE FOR OUTPUT 3440 3441 (AH) = 14 WRITE TELETYPE TO ACTIVE PAGE 3442 (Al} 3443 (Bll 3444 = CHAR TO WRITE = FOREGROUND COLOR IN GRAPHICS MODE NOTE -- SCREEN WIDTH IS CONTROLLED BY PREVIOUS MODE SET : 3445 3446 (AH) = 15 CURRENT VIDEO STATE 3447 RETURNS THE CURRENT VIDEO STATE 3448 (All 3449 (AHI = NUMBER OF CHARACTER COLUMNS ON SCREEN 3450 (BHI = MODE = CURRENTlY SET ( SEE AH=O FOR EXPLANATION) CURRENT ACTIVE DISPLAY PAGE 3451 3452 CS.SS,OS,ES,BX,CX.DX PRESERVED DURING CALL 3453 3454 3455 ALL OTHERS DESTROYED ;-----------------------------------------------------------------------ASSUME CS :CODE ,OS:DATA. ES:VIDEO_RAM F045 3456 F045 3457 F045 FCFO 3458 F047 tOFl 3459 F049 EEF 1 3460 F04B 39F2 3461 F04D 9CF7 3462 F04F 17F2 3463 ACT_DISP_PAGE 3464 OW DW OFFSET 9HZ OFFSET SCROLL_UP F053 38F3 3465 ow OFFSET SCROLL_DOWN FOS1 ORG OF045H LABEL WORD OW OW OW DW DW OFFSET SET_MODE OFFSET SET_CTYPE OFFSET SET_CPOS OFFSET READ_CURSOR OFFSET REAO_LPEN Ml I TABLE OF ROUTINES WITHIN VIDEO 110 FOSS 74F3 3466 DW OFFSET READ_AC_CURRENT F057 B9F3 3467 WRITE_At_CURRENT 3468 ow ow OffSET F059 Een OFFSET WRITE_C_CURREHT FOSB 4EF2 3469 DW OFFSET SET_COLOR F05D 2FF4 3470 ow OFFSET WRITE_DOT F05F lEF4 3471 DW OffSET READ_~OT FObl laF7 3472 ow OFFSET WRITE_TTY f063 NFl 3473 DW OFFSET VIDEO_STATE EQU $-Ml 0020 3474 MIL 3475 ORG OF065H FObS 3476 FObS 3477 FObS FB 3478 STI f066 Fe 3479 ClO F067 06 3480 PUSH ES F06e IE 3481 PUSH OS F069 52 3482 PUSH FObA 51 3483 PUSH ox ex FObB 53 3484 PUSH BX PROC VIDEO_IO NEAR ; INTERRUPTS BACK ON ; SET DIRECTION FORWARD j SAVE SEGMENT REGISTERS System BIOS A-49 LOC OBJ LINE F06t 56 SOURCE 3485 3486 F06D 57 F06E 50 F071 32:E4 F077 30Z000 3489 3490 3491 3492 F07A 7204 F07t 58 F073 DIED F075 SBFO SI PUSH DI AX ; SAVE AX VALUE HDV AL.AH XDR AH,AH AX.l ; GET INTO LOW BYTE ; ZERO TO HIGH BYTE PUSH 3487 3488 f06F 8'&'C4 PUSH SAL ; *2 FOR TABLE LOOKUP 51.AX AX,Mll ; PUT INTO 51 FOR BRANCH CHP 3493 JB HZ ; BRANCH AROUND BRANCH 3494 POP AX ; THROW AWAY THE PARAMETER JHP VIDEO_RETURN ; DO NOTHING IF NOT IN RANGE DDS HOV ; TEST FOR WITHIN RANGE F07D E94501 3495 Foeo 3496 Foao EBBBDE 3497 CALL F083 880068 3498 HOV AX,OB800H ; SEGMENT FOR COLOR CARD F086 883EI000 3499 HOV FOBA 81E73000 3500 AHD OI,EQUIPJlAG OI,30H I ; IS SETTING FOR Bioi CARD? HZ: F08E 83FF30 3501 CMP Dl,30H F091 7502 3502 JHE H3 ; GET EQUIPMENT SETTING ISOLATE CRT SWITCHES HOV AH,OBOH ; SEGMENT FOR BW CARD MeV ES,AX I SET UP TO POINT AT VIDEO RAM AREAS 3506 POP AX I RECOVER VALUE 3507 HOV AH,CRT_HODE ; GET CURRENT MODE INTO AH 3508 JHP WORD PTR CS: [SI+OFFSET MIl F093 B48D 3503 F095 3504 F09S 8Eeo 3505 F097 58 F098 8A264900 F09C 2EFFA445FO H3: 3509 VIOEO_lO 3510 ;-------------------------------------------------------- 3511 I SET_MODE 3512 THIS ROUTINE INITIALIZES THE ATTACHMENT TO 3513 THE SELECTED MODE. 3514 (ALI = MODE SELECTED (RANGE 0-91 i OUTPUT 3517 3518 THE SCREEN IS BLANKED. INPUT 3515 3516 ENOP NOHE 1-------------------------------------------------------- 3519 3520 .----- TABLES FOR USE IN SETTING OF MODE 3521 FOA4 3522 ORG FDA4 3523 VIDEO_PARMS 3524 ;----- INlT_TABlE 3525 DB 38H ,28H .ZCH .0AH.lFH ,6,19H 3526 DB lCH.2,7,6.7 3527 DB 0,0,0,0 FOA4 38 OFOA4H LABEL BYTE • SET UP FOR 40XZS FDA5 28 FOA6 20 FOA7 OA FOA8 IF FOA9 06 FOAA 19 FOAB Ie FOAC 02 FOAD 07 FOAE 06 FOAF 07 Foeo 00 FOBI 00 FOB2 00 FOB3 00 0010 3528 "4 EQU $-VIDEO_PARHS 3530 DB 7lH.50H ,5AH ,OAH, IFH ,6, 19H 3531 DB lCH,2,7.6.7 3532 DB 0.0.0,0 DB 38H, 28H,2DH. OAH. 7FH,6.64H 3529 FOB4 71 ; SET UP FOR 80X2S FOBS 50 FOS6 SA FOB7 OA FOB8 IF FOB9 06 FOBA 19 FOBB lC FOBC 02 FOBD 07 FOBE 06 FOBF 07 FOCO 00 FOCI 00 FOC2 00 FOC3 00 3533 FOC4 38 3534 FOC5 28 A-50 System BIOS ; SET UP FOR GRAPHICS LOC OBJ LINE SOURCE FOCb 20 FOC7 DA. Face 7F FOC9 06 FOCA 64 Face 70 3535 DB 70H,2.1,6,7 3536 DB 0,0,0,0 3537 3538 DB 61H,50H.52H .OFH.19H.6, 19H 3539 DB 19H.2 .DOH .OSH ,OCH 3540 DB 0.0,0,0 Foce 02 FOCO 01 FOCE 06 foeF 07 FOOD 00 FOOl 00 F002 00 FOOl 00 FOD4 61 J SET UP fOR 80X25 B&W CARD fODS SO FOD6 52 FOD7 OF FOD8 19 FOD9 06 FOCA 19 FODS 19 FOOt 02: FOOD 00 FODE 08 FOOF DC FOED 00 FOE I 00 FOE2 00 FOE3 00 3541 FOE4 3542 rOf4 0008 FOe6 0010 3543 3544 3545 FOE8 0040 FOEA 0040 3546 3547 3548 3549 FOEC 3550 3551 FOEt 28 M5 LABEL WORD OW 2048 ; 40X2:5 ow ow ow 4096 ; 80X25 16384 16364 j ; TABLE Of REGEN LENGTHS GRAPHICS ; ----- COLUMNS M6 LABEL BYTE DB 40 .40 ,80.80 ,40,40.80.60 FOED 28 FOEE 50 FOEF 50 FOFO 28 FOF 1 28 FOF2 50 fOF3 SO 3552 3553 3554 ;----- C_REG_TAB FOF4 3555 H7 FOF4 2C 3556 LABEL BYTE DB 2~.2~.20H.2~.UH.2EH.IEH.2~ I TABLE OF HOOf SETS FOF5 28 FOF6 20 FOF7 29 FOF8 2A FOF9 2£ FOFA lE FOFB 29 3557 FOFC 3558 FOFC 13A0403 3559 tfOV OX.0304H ; ADDRESS OF COLOR CARD FOFF 8300 3560 HOV BL.O ; HODE SET FOR COLOR CARD FlOl 63FF30 3561 CH" DI.30H ; IS BW CARD INSTALLED FI04 7506 3562 JHE HB Fl06 B007 3563 tfOV AL.7 ; INDICATE BW CARD HODE FI08 B2B4 3564 HOV DL.OB4H I ADDRESS OF BW CARD (3B4) FIOA FEC3 3565 INC Bl I HaDE SET FOR BW CARD FlOC 3566 PROC SET_HOOE NEAR ; OK WITIf COLOR M8: FlOC 6AEO 3567 HOV AH.Al ; SAVE MODE IN AH FlOE A24900 3568 HOV CRT_MOOE.AL I SAVE IN GLOBAL VARIABLE FIll 69166300 3569 HOV ADDR_6845.DX F1l5 IE 3570 PUSH OS j F1l6 50 3571 ruSH AX I SAVE HODE FIl7 52 3572 ruSH OX I SAVE tJUTPUT PORT VALUE ; SAVE ADDRESS OF BASE SAVE POINTER TO DATA SEGMENT System BIOS A-51 LOC OBJ LINE SOURCE F1l8 83C204 3573 ADD OX.4 ; POINT TO CONTROL REGISTER FUB 6AC3 3574 3575 HOV AL,al ; GET MODE SET FOR CARD FllD EE OUT Ox.AL I RESET VIDEO FIlE 5A 3576 FllF 26CO FllI 8E08 3577 SUB AX,AX ; -SET UP FOR ABSO SEGMENT 3578 HOV OS.AX I ESTABLISH VECTOR TABLE ADDRESSING 3579 ASSUME OS: ABSO Fl23 C5IE7400 3580 3581 LOS BX.PARM_PTR POP AX FIl7 58 3582 3583 3584 Flza 891000 F12B BOFCOl FIlE Fl3a FI3l FI3S POP 1210 0309 aOFt04 7209 OX ; BACK TO BASE REGISTER ; GET POINTER TO VIDEO PARMS ; RECOVER PARMS ASSUME OS:CODE HOV CX,M4 I tHP AH,2 ) DETERMINE WHICH ONE TO USE H. ; MODE IS 0 OR 1 ex.cx j 3585 3586 Jt 3587 3588 tHP ADD Jt ADD LENGTH OF EACH ROW OF TABLE MOVE TO NEXT ROW OF INIT TABLE AH.4 H. I MODE IS 2 OR 3 ex.cx FI37 0309 3589 F139 eOFC07 3590 tHP F 13C 7202 3591 Jt H. ; MODE IS 4.5. OR 6 F13E 0309 3592 ADD BX,CX j i MOVE TO GRAPHICS ROW OF INIT_TABLE AH.7 MOVE TO Bioi CARD ROW OF INIT_TABLE 3593 3594 j----- BX POINTS TO CORRECT ROW OF INITIALIZATION TABLE 3595 M9: F140 3596 Fl40 50 3597 PUSH AX F141 32E4 3598 XOR AH ,AH 3599 j SAVE MODE IN AH j AH WILL SERVE AS REGISTER HUMeER DURING LOOP i 3600 3601 j----- LOOP THROUGH TABLE. OUTPUTTIING REG ADDRESS. THEN VALUE FROM TABLE 3602 MID: Fl43 F143 8At4 3603 3604 HOV AL.AH F145 EE 3605 OUT DX,AL F14& 42 3606 INC OX i Fl47 FEt4 3607 INC AH I NEXT REGISTER VALUE F149 BA07 3608 MOV AL,IBXl ; GET TABLE VALUE I INIT LOOP i GET 6845 REGISTER NUMBER POINT TO OAT A PORT F14B EE 3609 OUT DX.AL ; OUT TO CHIP F14C 43 3610 INC ex ; '-lEXT IN TA.BLF. F14D 4A 3611 DEC ox j F14E E2F3 3612 LOOP MIO ; 00 THE WHOLE TABLE FISO 58 3613 POP AX ; GET MODE BACK FIst IF 3614 POP OS ; RECOVER SEGMENT VALUE 3615 ASSUME DS:DATA BACK TO POINTER REGISTER 3616 3617 j ----- FILL REGEN AREA WITH BLANK 3618 F152 33FF 3619 XDR 01,01 j FIS4 893E4EOO 3620 HOV CRT_START,DI ; START ADDRESS SAVED IN GLOBAL I SET PAGE VALUE SET UP POINTER FOR REGEN F158 C606620000 3621 HOV ACTIVE_PAGE ,0 f 150 690020 3622 MOV CX,SIn j NUMBER OF WORDS IN COLOR CARD Fl6C aoFt04 3623 tHP AH,4 j TEST FOR GRAPHICS FIB 720B 3624 Jt Hl2 ; NO_GRAPHICS_INIT Fl6S eOFC07 3625 j tHP AH,7 Fl6e 7404 3626 JE H11 I BW_CARD_INIT Fl6A 33CO 3627 XOR AX,AX j FILL FOR GRAPHICS MODE Fl6C EB05 3628 JHP SHORT M13 j CLEAR_BUFFER Fl6E 3629 Fl6E 8508 FI7a 3630 HOV CH,OSH ; BUFFER SIZE ON BW CARD HDV AX,' I FILL CHAR FOR ALPHA .EP STOSW Mll: MI2: F170 682007 3631 3632 FI73 3633 M13: FI73 F3 3634 TEST FOR BW CARD ; BW_CARD_INIT ; NO_GRAPHICS_INIT '+7*256 ; CLEAR_BUFFER j FILL THE REGEN BUFFER WITH BLANKS F174 AS 3635 3636 i----- ENABLE VIDEO AND CORRECT PORT SETIING 3637 FI7S C70660000706 3638 HOV FI7S A04900 3639 HOV Fi7E 32E4 3640 XD. AH,AH I FleD BBFO 3641 HOV SI,AX ; TABLE POINTER. INOEXED BY MOOE FI82 66166300 3642 HOV OX.AOOR_6845 I PREPARE TO OUTPUT TO ADD OX,4 I ; 3643 Fl8b 83C204 3644 SET CURRENT CURSOR MODE ; GET THE MODE INTO AX REGISTER VIDEO ENABLE PORT Fl89 2E8A84F4FO 3645 HOV AL,CS:[SI+OFFSET M7] FISE EE FieF A26500 3646 OUT DX,AL ; SET VIDEO ENABLE PORT 3647 HOV CRT_MODE_SET,AL ; SAVE THAT VALUE 36'8 A-52 System BIOS LOC OBJ LINE SOURCE 3649 1----- DETERMINE NUMBER OF COlutlNS, BOTH FOR ENTIRE DISPLAY 3650 1----- AND THE NllHBER TO BE USED FOR TTY INTERFACE 3651 F 192 2E8A84ECFO 3652 MaV Al,CS:[SI + OFFSET M6J F197 32:E4 3653 XOR Fl99 A,34.6.00 3654 HOV AH,AH CRT_eOls,AX I NUHBER OF COLUMNS IN TliIS SCREEN 3655 3656 1----- SET CURSOR POSITIONS 3657 F19C 81£60EOO 3658 AND 5I.OEH FlAO 2ESB8CE4FO 3659 HOV CX.CS:ISI + OFFSET MS] , LENGTH TO CLEAR FIAS 890E4COO 3660 HOV CRT_LEN.CX j SAVE LENGTH OF CRT -- NOT USED FOR BW FlA9 890800 FlAt BF5000 3661 3662 HOV CX.8 I CLEAR ALL CURSOR POSITIONS HOV DI.OFFSET CURSOR_POSN FlAF IE fleD 07 3663 3664 PUSH OS POP ES F IB1 33CO FIB3 F3 FIB4 AB 3665 3666 XOR AX,AX REP STOSW I WORD OFFSET INTO CLEAR LENGTH TABLE I ESTABLISH SEGMENT ADDRESSING j FILL WITH ZEROES 3667 3668 1----- SET UP OVERSCAN REGISTER 3669 FIBS 42 3670 INC OX j SET OVERSCAN PORT TO A DEFAULT FIBb B030 3671 HOV AL.30H j VALUE OF 30H FOR ALL MOOES 3672: EXCEPT 640X200 j CHP CRT_MOOE.6 ; SEE IF THE MODE IS 640X200 BW JNZ HOV HI" AL.3FH ; IF IT IS 640X200. THEN PUT IN 3FH 3677 OUT DX.Al j 3678 HOV CRT_PALETTE,AL ; SAVE THE VALUE FOR FUTURE USE flB8 803E490006 FIBD 7502 3673 FIBF B03F 3675 FlCl 3676 FIel EE F It2 A26600 3674 IF IT ISNT 640X200. THEN GOTO REGULAR M14: OUTPUT THE CORRECT VALUE TO 309 PORT 3679 3680 j----- NORMAL RETURN FROM ALL VIDEO RETURNS 3681 FltS FICS SF 3682 VIDEO_RETURN: 3683 POP DI FlC6 SE 3684 POP SI FIC7 58 3685 POP BX HIS: FICS 3686 Flce 59 3687 POP CX FlC9 SA 3688 POP OX FICA IF 3689 POP OS Flce 07 Flee CF 3690 POP ES I VIOEO_RETURN_C 3691 j IRET RECOVER SEGMENTS ; ALL DONE 3692 SET_MOOE 3693 3694 ; ---------------------------------------------------------------j SET_CTYPE ENDP 3695 THIS ROUTINE SETS THE CURSOR VALUE 3696 3697 j 3698 ; OUTPUT j INPUT 3699 (CXI HAS CURSOR VALUE CH-START LINE. CL-STOP LINE NONE j----------------------------------------------..----------------- FlCD 3700 3701 FlCD 640.6. 3702 HOV AH.IO I 6845 REGISTER FOR CURSOR SET FIeF 890E6000 FI03 E80200 FID6 EBED 3703 HOV CURSOR_HODE.CX ; SAVE IN OATA AREA 3704 CALL HI6 I OUTPUT CX REG 3705 3706 JMP VIDEO_RETURN 3707 SET_CTYPE j----- PROC NEAR THIS ROUTINE OUTPUTS THE CX REGISTER TO THE 6645 REGS NAMED IN AH 3708 Floe 3709 Floe 88166300 flOC 8AC4 3710 HOY DX.ADOR_6645 I 3711 HOV AL.AH j GET VALUE FIDE EE 3712 OUT DX.At j REGISTER SET FlOF 42 3713 3714 OX j DATA REGISTER FlED 8AC5 HOV AL.CH ; DATA FIE2 EE 3715 OUT OX.AL OX .At.AH N16: INC Fln 4A 3716 DEC FIE4 8At4 FIE6 FEtD FlEe EE 3717 HOV FIE9 42 3716 INC AL 3719 OUT OX.AL 3720 INC OX HOV AL.CL FlEt EE 3722 OUT OX.AL FlED C3 3723 RET FlEA 8AC1 3721 3724 SET_CTYPE ADDRESS REGISTER I POINT TO OTHER DATA REGISTER j SET FOR SECOND REGISTER ; SECOND DATA VALUE I ALL DONE ENDP System BIOS A-53 LOC OBJ LINE SOURCE 3725 1------------------------------------------------ 3726 ; SET_CPOS 3727 THIS ROUTINE SETS THE CURRENT CURSOR 3728 3729 POSITION TO THE NEW X-V VALUES PASSED ; INPUT 3730 OX - ROW,COLUt1N OF NEW CURSOR 3731 3732 BH - DISPLAY PAGE OF CURSOR ; OUTPUT 3733 CURSOR IS SET AT 6845 IF DISPLAY PAGE 3734 IS CURRENT DISPLAY 3735 ; --------------- --------------------------------- FlEE 3736 SET_CPOS FlEE 8ACF 3737 MOV CL.BH FIFO 32EO 3738 XOR CH,CH ; ESTABLISH LOOP COUNT FIFe! FIF4 FIF6 FIF9 FIFO 3739 SAL CX.l ; WORD OffSET 3740 MOV SI,CX , USE IHDEX REGISTER 3741 MOV [SI+OFFSET CURSOR_POSN1,DX 3742 CMP ACTIVE_PAGE .BH 3743 JHZ M17 DIEI 88Fl 895450 383E6200 7505 FIFf 8BC2 3744 flOl E80200 3745 F204 3746 Fl04 EBBF NEAR SAVE THE POINTER i , SET_CPOS_RETURN MOV AX,DX ; GET ROW/COLUMN TO AX CALL M18 ; CURSOR_SET MI7: 3747 3748 PROC I SET _CPOS_RETURN VIDEO_RETURN JMP ENOP SET_CPOS 3749 3750 ,----- SET CURSOR POSITION. AX HAS ROW/COLUHN FOR CURSOR 3751 fZOb 3752 FlOb E87COO 3753 CAll POSITION Fl09 88C8 3754 MOV CX,AX flOB 030E4EOO 3755 ADO CX,CRT_START ; ADD IN THE START ADDR FOR THIS PAGE M18 PROC NEAR ; DETERMINE LOCATION IN REGEN BUFFER F20F DIF9 3756 SAR CX,l ; DIVIDE BY 2 FOR CHAR ONLY COUNT Flll 840E 3757 MOV AH,14 ; REGISTER NUMBER FOR CURSOR FZ13 EBC2FF 3758 CALL M16 ; OUTPUT THE VALUE TO THE 6845 F216 C3 3759 RET 3760 MI8 3761 ; ---------- ------------------------------------------------------ 3762 ; ACT_DISP_PAGE 3763 THIS ROUTINE SETS THE ACTIVE DISPLAY PAGE, ALLOWING THE 3764 FULL USE OF THE RAM SET ASIDE FOR THE VIDEO ATTACHMENT 3765 INPUT 3766 3767 ENOP AL HAS THE NEW ACTIVE DISPLAY PAGE ; OUTPUT 3768 THE 6845 IS RESET TO DISPLAY THAT PAGE 376 <;I ; -------------- --- --------------------- -------------------------- fl17 3770 ACT_DISP_PAGE fl17 A26200 3771 MOV ACTIVE_PAGE.AL I SAVE ACTIVE PAGE VALUE fZu' 880E4COO 37TZ. MOV CX,CRT_LEN ; GET SAVED LENGTH OF REGEN BUFFER F21E 98 3773 CBW F21F 50 3774 PUSH AX ; S.a.VE PAGE V.a.LUE f220 f7Et 3775 HUL ex 1 DISPLAY PAGE TIMES REGEN LENGTH F2ll A34EOO 3776 ; SAVE START ADDRESS FOR ?ROC NEAR ; CONVERT AL TO WORD MOV CRT_START .AX F225 88C8 3778 MOV CX.AX ; START ADDRESS TO CX F227 DIF9 3779 SAR CX,1 i DIVIDE BY 2 FOR 6845 HANDLING F229 B40C 3780 3777 ; LATER REQUIREMENTS ; 6845 REGISTER FOR START ADDRESS MOV AH.12 F22B EBAAFF 3781 CALL MI6 FZ2E 58 3782 POP ax ; RECOVER PAGE VALUE BX.I ; *2 FOR WORD OFFSET F22F DID fZ31 884750 3783 SAL 3784 MOV AX,[BX + OFFSET CURSOR_POSH] F234 E8CFFF 3785 CAll HI8 F237 EBec 3786 JMP SHORT VIDEO_RETURN 3788 3789 GET CURSOR FOR THIS PAGE ;---------------------------------------------------------------; READ_CURSOR 3790 THIS ROUTINE READS THE CURRENT CURSOR VALUE FROM THE 3791 6845. FORMATS IT. AND SENDS IT BACK TO THE CALLER INPUT 3792 3793 3794 BH - PAGE OF CURSOR I OUTPUT ox - 3795 3796 fZ39 3797 3798 F239 8AOF 3799 ROW, COLUHN OF THE CURRENT CURSOR POSITION CX - CURRENT CURSOR MODE ; ---------------------------------------------------------------READ_CURSOR PROC NEAR MOV BL,BH FZ38 32FF 3800 XOR BH,BH FZ3D DIE3 3801 SAL BX.l A-54 j ; SET THE CURSOR POSITION System BIOS j WORD OFFSET LaC OBJ LINE SOURCE F2:3F 885750 3802: MDV F242 8BOE6000 3803 MOV eX,CURSOR_MODE F2:46 SF 3804 pop 01 F247 SE 3805 POP SI OX,(BX-tOFFSET CURSOR_POSNI F2:48 58 3806 POP BX FZ49 58 3807 POP AX F24A 58 3808 3809 POP AX F2:4B If POP OS F2:4C 07 3810 POP ES F2:40 CF 3811 rRET 3812 3813 READ_CURSOR 3814 ; SET COLOR I DISCARD SAVED ex AND ox ENDP ;----------------------------------------------------------- ____________ _ 3815 THIS ROUTINE WIll ESTABLISH THE BACKGROUND COLOR. THE OVERSCAN 3816 COLOR. AND THE FOREGROUND COLOR SET fOR MEDIUM RESOLUTION 3817 3818 GRAPHICS INPUT 3819 (BH ) HAS COLOR ID 3820 IF BH=O, THE BACKGROUND COLOR VALUE IS SET 3821 FROM THE LOW BITS OF BL (0-31 ) 3822 IF BH=I, THE PALETTE SELECTION IS MADE 3823 BASED ON THE LOW BIT OF BL: 3824 O=GREEN. RED. YELLOW FOR COLORS 1.2.3 3625 l=BLUE. CYAN. MAGENTA FOR COLORS 1.2:.3 3826 3827 (BLl HAS THE COLOR VALUE TO BE USED ; OUTPUT 3828 THE COLOR SelECTION IS UPDATED F24E 3829 3630 F2:4E 88166300 3831 MOV DX.ADDR_o84S j F2:52 83e205 3832 ADD OX.S ; OVERSCAN PORT F255 A066DO 3833 MOV AL.CRT_PALETTE ; GET THE CURRENT PALETTE VALUE 3834 OR BH.BH ; IS THIS COLOR 01 3835 JHZ M20 i OUTPUT COLOR I F258 DAFF F2:5A 750E i ------------------------------------------------------------------------ SET_COLOR PROC NEAR 1/0 PORT FOR PALETTE 3836 3637 j----- HANDLE COLOR 0 BY SETTING THE BACKGROUND COLOR 3838 F25C 24EO 3839 AND AL,OEOH ; TURN OFF LOW 5 BITS OF CURRENT F25E 80E31F 3840 AND BL.OIFH ; TURN OfF HIGH 3 BITS OF INPUT VALUE Fl61 OAt3 3841 OR AL.BL ; PUT VALUE INTO REGISTER Fl6] 3842 M19: ; OUTPUT THE PALETTE Fl63 EE 3643 OUT aX.AL i OUTPUT COLOR SELECTION TO 309 PORT F264 Alb6DO 3844 MOV CRT_PALETTE.AL ; SAVE THE COLOR VALUE Flo? E95BFF 3845 JMP VIDEO_RETtmN 3846 3647 1----- HANDLE COLOR 1 BY SELECTING THE PALETTE TO BE USED 3848 F26A 3649 Fl6A 24DF 3850 AND AL,ODFH ; TURN OFF PALETTE SELECT BIT F20C DOEB 3851 M20: SHR BLo! ; TEST THE LOW ORDER BIT OF Bl FloE 73F3 3852 JNC M19 F270 OC20 3853 OR AL,20H ; TURN ON PA LEnE SelECT BIT F272 EBEF 3654 JMP M19 iGOOOIT ; ALREADY DONE 3855 SET_COLOR 3856 3857 ; ---- - -- - - - - ---- - - -- - ------- - - - ------ ----- -- - - - -; VIDEO STATE ENOP 3858 RETURNS THE CURRENT VIDEO STATE IN AX 3859 AH = NUMBER OF COLUMNS ON THE SCREEN 3860 3861 AL = CURRENT VIDEO MODE BH = CURRENT ACTIVE PAGE 3862 1------------------------------------------------ F274 3863 VIDEO_STATE PROC NEAR F2:74 8A264AOO 3864 MOV AH,BYTE PTR CRT_COLS ; GET NUMBER OF COLUMNS F2:78 A04900 3865 MOV AL,CRT_MODE ; CURRENT MODE F27B 8A3E62:DO 3866 MOV BH, ACTIVE_PAGE ; GET CURRENT ACTIVE PAGE F27F SF 3867 POP 01 1 RECOVER REGISTERS F2:80 5E 3868 POP SI F28l 59 3869 POP CX j Fla2 E943FF 3870 JMP M15 ; RETURN TO CALLER 3871 VIDEO_STATE 3872 3873 ; POSITION j-------------------------------------------------------- 3874 THIS SERVICE ROUTINE CALCULATES THE REGEN 3875 3876 BUFFER ADDRESS OF A CHARACTER IN THE ALPHA MODE ; INPUT AX 3877 3878 DISCARD SAVED BX ENDP = ROW, COLUMN POSITION ; OUTPUT System BIOS A-55 LINE LaC OBJ SOURCE 3879 AX = OFFSET OF CHAR POSITION IN REGEN BUFFER 3880 I - - - - - -- - ---- - -- - ---- - - - - --- - - --- ---------- --- - - ------- -- F285 3881 POSITION F285 53 3882 PUSH BX Flab 8B06 3883 MOV BX,AX FlBB 8AC4 3884 MOV AL,AH ; ROWS TO AL FlBA F6264AOO 3885 MUL BYTE PTR CRT_COLS ; DETERMINE BYTES TO ROW FleE 32FF 3886 XOR BH,BH f290 03e3 3887 ADO AX,BX ; ADO IN COLUMN VALUE F29Z DIED 3888 SAL AX,1 ;* F294 58 F295 (3 3889 POP BX NEAR ; SAVE REGISTER 2 FOR ATTRIBUTE BYTES RET 3890 3891 POSITION 3892 1-------------------------------------------------------- 3893 ENDP ; SCROLL UP 3694 THIS ROUTINE MOVES A BLOCK OF CHARACTERS UP 3895 ON THE SCREEN 3896 INPUT 3900 (OX) 3901 (BHI 3902 (OS) = = = = = = :903 (ES I = REGEN 3897 (AH I 3898 (All 3899 (CX I 3904 3905 3906 3908 CURRENT CRT MODE NUMBER OF ROWS TO SCROLL ROW/COLUMN OF UPPER LEFT CORNER ROW/COLUMN OF LOWER RIGHT CORNER ATTRIBUTE TO BE USED ON BLANKED LINE DATA SEGMENT BUFFER SEGMENT ; OUTPUT NONE -- THE REGEN BUFFER IS MODIFIED ;-------------------------------------------------------ASSUME 3907 ,.96 PROC SCROLL_UP CS:CODE,DS:OATA,ES:DATA PROC NEAR F296 8A08 3909 MOV BL,AL ; SAVE LINE COUNT IN BL F298 SOFt04 3910 CMP AH.4 ; TEST FOR GRAPHICS MODE F29B 7208 3911 JC Nl ; HANDLE SEPARATELY ; TEST FOR BW CARD F290 aOFCOl 3912 CMP AH.7 FlAD 7403 Fl"2 E9FOOl 3913 JE Nl 3914 JMP GRAPHICS_UP FZAS 3915 F2AS 53 3916 PUSH BX FlA6 8BCl 3917 MOV AX,CX FlAB £83700 3918 CALL SCROll_POSITION ; DO SETUP FOR SCROLL FlAB 7431 3919 JZ N7 I BLANKJIELD F2AD 03FO 3920 ADD SI.AX ; FROM ADDRESS F2AF 8AE6 3921 MOV AH,DH I ; FlBl ZAn 3922 SUB AH.BL ; ; ROWS TO BE MOVED F2B3 3923 F2B3 E872:00 3924 CALL NI0 I MOVE ONE ROW FlBb OlF5 3925 ADD SI.BP Nl: ; UP_CONTINUE ; SAVE FILL ATTRIBUTE IN BH ; UPPER LEFT POSITION N2: ROWS IN BLOCK ; ROW_LOOP FlBa 03FD 3926 ADO FlBA FEee 3927 DEC AH ; COUNT OF LINES TO MOVE FlBt 75F5 FlBE FlBE 58 F2BF B020 FlCI 3928 JNZ N2 j 3930 POP AX I RECOVER ATTRIBUTE IN AH 3931 MOV AL. ; FILL WITH BLANKS Flel E86000 3933 CALL NIl ; CLEAR THE ROW Fle4 03FO 3934 ADD OI,SP ; POINT TO NEXT LINE Flt6 FEte Flca 75F7 3935 DEC BL j 3936 JNZ N4 ; CLEAR_LOOP F2eA 3937 FleA EB7l0e 3938 CALL DDS FleD 803E490007 3939 CMP CRT_MODE. 7 fl02 7407 3940 JE N6 Fl04 A06500 3941 MOV AL,CRT_MODE_SET ; GET THE VALUE OF THE MODE SET Fl07 BA0803 3942 MOV DX.03D8H I ALWAYS SET COLOR CARD PORT FlOA EE 3943 OUT DX,AL 3929 OI,SP ; POINT TO NEXT LINE IN BLOCK ; CLEAR_LOOP 3932 FlOB 3944 F2DB E9E7FE 3945 ROW_LOOP N3: j COUNTER OF LINES TO SCROLL SCROLL_END ; IS THIS THE BLACK AND WHITE CARD ; IF SO. SKIP THE MODE RESET N6: JMP N7: HOE 3946 F2DE 8ADE 3947 MOV BL,OH ; GET ROW COUNT FlED EBoC 3948 JMP N3 ; GO CLEAR THAT AREA 3949 ; BLANKJIELD SCROLL_UP ENIlP 3950 3951 ;----- HANDLE COMMON SCROLL SET UP HERE 3952 FlEZ 3953 F2EZ 803E490002 3954 CMP CRT_MODE.2 I TEST FOR SPECIAL CASE HERE F2E7 7218 3955 JB N9 ; HAVE TO HANDLE 80X25 SEPARATELY A-56 SCROLL_POSITION PROC System BIOS NEAR LOC OBJ FZE9 B03E490003 F2EE 7711 LINE SOURCE 3956 3957 CHP CRT_HOOE,3 N. JA 3958 3959 1----- SOX25 COLOR CARD SCROLL 3960 FHO 52 3961 PUSH OX FZFl BADA03 3962 3963 HOV DX,30AH F2F4 50 PUSH AX F2F5 3964 ; GUARANTEED TO BE COLOR CARD HERE ; WAH_DISP_ENABLE H6: F2F5 EC 3965 IH AL,OX I GET PORT f2F6 A808 3966 TEST AL,e I WAIT FOR VERTICAL RETRACE F2F8 74FB 3967 JZ H8 ; WAIT_DISP_ENABLE fZfA B025 3966 HOV AL,25H F2FC B208 3969 NOV Dl,008H ; DX=3D8 F2FE EE 3970 OUT OX.AL F2FF 58 3971 POP AX ; TURN OFF VIDEO ; DURING VERTICAL RETRACE F300 SA 3972: POP OX F30l F304 03064EOO 3973 3974 3975 FlOB 8BF8 FlOA BBfO F30C 2B01 3978 F30l E881FF H9: ; CONVERT TO REGEN POINTER CALL POSITION ADO AX ,CRT_START 3976 HOV DI,AX ; TO ADDRESS FOR SCROLL 3977 HOV SI.AX DX,CX I FROM ADDRESS FOR SCROLL I OFFSET OF ACTIVE PAGE ; OX = #ROWS, ;-COLS IN BLOCK F30E FEC6 3979 INC OH F310 FEC2 3980 INC Ol nl2 32ED 3981 XOR CH,CH ; SET HIGH BYTE OF cOUNT TO ZERO F314 8B2E4AOO 3982 HOV BP,CRT_COLS ; GET NUMBER Of COLUMNS IN DISPLAY F318 03ED 3983 ADO BP,BP ; TIMES 2 FOR ATTRIBUTE BYTE F31A 8AC3 ; GET LINE COUNT ) INCREHENT FOR 0 ORIGIN 3984 HOV AL,BL F31C F6264AOO 3985 HUl BYTE PTR CRT_COLS ; DETERMmE OFFSET TO FROM ADDRESS F320 03CO 3986 ADO AX,AX n22 06 3967 PUSH ES , F323 IF 3988 POP OS I F324 80FBOO 3989 CMP BL,O ; 0 SCROLL MEANS BLANK FIELD F327 C3 3990 3991 ; *2 FOR ATTRIBUTE BYTE RET ESTABLISH ADDRESSING TO REGEN BUFFER FOR BOTH POINTERS ; RETURN WITH FLAGS SET SCROll_POSITION ENOP 3992 3993 ;----- MOVE_ROW 3994 F328 3995 PROC NEAR F328 8ACA 3996 MOV CL,DL F32A 56 3997 PUSH 51 n2B 57 3998 PUSH 01 ; SAVE START ADDRESS F32C F3 3999 REP HOVSW ; MOVE mAT LINE ON SCREEN POP 01 51 ; RECOVER ADDRESSES Hl0 ; GET. OF COLS TO MOVE F32D A5 F32E 5F 4000 F32F SE 4001 POP F330 C3 4002 RET 4003 Hl0 ENDP 4004 4005 j----- CLEAR_ROW 4006 F331 4007 H11 PROC NEAR F331 8ACA 4008 HOV CL,DL F333 57 4009 PUSH 01 F334 F3 4010 REP STOSW F336 SF 4011 POP 01 F337 C3 4012 I GET. COLlR1NS TO CLEAR ; STORE THE FILL CHARACTER F335 A6 RET 4013 H11 4014 ; ; SCROll_DOWN 4015 4016 THIS ROUTINE MOVES mE CHARACTERS WITHIN A 4017 DEFINED BLOCK DOWN ON THE SCREEN, FILLING THE 4018 4019 TOP LINES WITH A DEFINED CHARACTER ; INPUT 4020 (AH) 4021 (AU 4022 (CX) 4023 (OX) 4024 (BH) 4025 (OS) 4026 4027 4026 F338 ENDP -------------------------------------------------------- (ES I = CURRENT CRT HOOE = NUMBER OF LINES TO SCROLL = UPPER LEFT CORNER OF REGION = LOWER RIGHT CORNER OF REGION = FILL CHARACTER = DATA SEGMENT = REGEN SEGMENT ; OUTPUT NONE -- SCREEN IS SCROllED 4029 ;-------------------------------------------------------- 4030 SCROLl....DOWH PPDC NEAR System BIOS A-57 LOC OBJ LINE F338 FD F339 BAD8 4031 F338 eOFCOlt 4033 F33£ 72:08 40144035 SOURCE STO tIOV CMP JC CMP JE JMP 4032 F340 BOFC07 F34~ 7403 F345 £9A601 F348 4036 4037 F348 53 4039 F349 BBC2 4040 HOV f348 £894Ff 4041 4042: CAll 4038 F34£ 7420 F350 28FO 4043 4044 4045 4046 F352 8.£6 F354 2AE3 F35b F356 ESCFfF I DIRECTION FOR SCROLL DMI JUNE CiX..NT TO Bt I TEST FOR GRAPHICS SL.AL AH,4 HI. AH,7 HI. GRAPHICS_DCJIoI4 I TEST FOR BW CARD I CONTINUE OQIIII NI2:: PUSH JZ SUB BX AX,OX I SAVE ATTRIBUTE IN BIt SCROLL"..POSITION HI. 51 ,A)( AH,DH ; GET REGEN LOCATION ~ LOWER RIGHT CORNER SUB AH.BL J 51 IS FROf1 ADDRESS ; GET TOTAL I ROWS I cOUNT TO HOVE IN SCROLL HID I I10VE ONE ROW I10V N13: F359 2BFS 4048 CALL SUB F358 2BFD 4049 SUB DI,BP F350 FEee 4050 f35F 75F5 4051 DEC JHZ AH H13 '361 4052 F3&1 58 F362 B020 4053 PDP HOV AX AL,' I RECOYER ATTRIBUTE IN AH '364 F364 fBCAFF 4055 4056 I CLEAR ONE ROW 4057 DI.BP I GO TO NEXT ROW F369 FECB 4058 F36B 75F7 4059 CALL SUB DEC JHZ JMP H11 F367 2BFD BL.DH 4041 H14: 4054 H15: F36D E95AFF 4060 F370 F370 8ADE 4061 F372 EBED 4063 MDV JMP 4064 SCROlL..DOWN 4066 BL HIS HS I SCROl'--.END N16: 4062 4065 SI,BP Hl' ENDP ;-------------------------------------..-----------------, READ_AC_CURRENT , 4067 THIS ROUTINE READS THE ATTRIBUTE AN) CHARACTER 4068 AT THE CURRENT CURSOR POSITIoN Am REruRNS THEM : 4069 I 4070 4071 ,INPUT TO THE CALLER (AH J = CURRENT = DISPLAY CRT MODE 4072 (BH) 4073 IDS) = 4074 I ES) = REGEN (AU = CHAR READ = ATTRIBUTE 4075 4078 » SEGMENT ;OUTPUT 4076 4077 PAGE ( ALPHA MODES ONLY DATA SEGMENT I AH I READ ;-------------------------------------------------------A~SI.R1E 4079 F374 4080 F374 80FC04 4081 F377 7208 4082 F379 80FC07 4083 F37C 7403 4084 F37E E9A802 4085 '381 4086 F381 E8UOO F364 SBF3 4087 CALL 4088 MDV CS:CODE .DS: DATA, ES :OATA READ_AC_CURRENT PROC CMP JC CMP JE JMP NEAR AH,4 PI AH,7 PI , IS THIS GRAPHICS ; IS THIS BW CARD GRAPHICS_READ PI: 1 READ_AC_CONTIt«lE FINO_POSITION SI.BX 1 ESTABLISH ADDRESSiNG IN SI 4089 4090 1----- WAIT FOR HORIZONTAL RETRACE 4091 F386 88166300 4092 miv DX.ADDR_6845 F38A 83C206 4093 ADD DX.6 i POINT AT STATUS PORT F38D 06 4094 PUSH F38E IF 4095 POP ES OS I GET SEGMENT FOR QUIIZK ACCESS F38F F38F EC 4096 4097 IH AL,DX F390 A801 4098 TEST AL.1 F392 75FB 4099 P' F394 FA 4100 JHZ CLI P2: J GET BASE ADDRESS 1 WAIT FOR RETRACE LOW l GET STATUS o o IS HCAl RETRACE LOW WAIT UNTIL IT IS ; NO MORE INTERRUPTS F395 4101 F395 EC 410. IN AL.OX 1 GET STATUS F396 A801 4103 TEST AL.1 j F398 74FB 4104 JZ P3 1 WAIT F39A AD 4105 LODSW F39B E927FE 4106 JMP 4107 A-58 P3: j VIDEO_RETURN READ_At_CURRENT EN)P System BIOS WAIT FOR RETRACE HIGH IS IT HIGH ~TIL IT IS I GET THE CHAR/ATTR LOC OBJ LINE SOURCE 4108 F39E 4109 PROC FIND_POSITION F39E SACf 4110 "OV CL,BH F3AO 32EO 4111 XOR CH,CH F3A2 8BF 1 4112 4113 4114 4115 MOV F3A4 01E6 F3A6 884450 F3A9 3308 nAB E306 F3AO 4116 4117 NEAR J DISPLAY PAGE TO SI,CX I MOVE TO SI FOR INDEX SAL 51.1 I ,. 2 FOR WORD OFFSET MOV AX,(SI+ OFFSET ClmSOR_POSNI XOR aX.BX ; SET START ADDRESS TO ZERO JCXZ P5 ; NO_PAGE P4; ; GET ROW/COLUMN OF ntAT PAGE ; PAGE_LOOP F3B3 E8CFFE 4118 4119 4120 4121 nB6 0308 4122 F368 C3 412:3 412:4 FIND_POSITION 4125 ; ------------------------------------------------ 412:6 ; WRITE_AC_CURRENT F3AO 031E4COO FlBI E,FA F3B3 ADD I LENGTH OF BUFFER LOOP 1'5: I NO_PAGE CALL POSITION ; DETERMINE LOCATION IN REGEN ADD BX,AX ; ADD TO START OF REGEN RET 412:7 4128 412:9 ENOl' THIS ROUTINE WRITES THE ATTRIBUTE AND CHARACTER AT THE CURRENT CURSOR POSITION 4130 INPUT (AH 1 :: CURRENT CRT MODE 4131 4132 (BH) :: DISPLAY PAGE 4133 {CXI :: COUNT OF CHARACTERS TO WRITE 4134 (All :: CHAR TO WRITE 4135 (Bll :: ATTRIBUTE OF CHAR TO WRITE 4136 (DSI :: DATA SEGMENT 4137 4138 4139 4140 ex (ESI :: REGEN SEGMENT ; OUTPUT NONE j-----------------------------------------------PROt NEAR F3B9 4141 F3B9 80FC04 CMP A,H,4 JC P6 CMP AH,7 F3Cl 7403 4142: 4143 4144 4145 JE P6 F3C3 £96201 4146 JMP GRAPHICS_WRITE nC6 4147 4148 4149 MeV AH,BL I GET ATTRIBUTE TO AH PUSH AX I SAVE ON STACK ; SAVE WRITE COUNT F3et 7208 F3BE 80FC07 F3C6 8AE3 F3ee 50 WRITE_At_CURRENT I IS THIS GRAPHICS ; IS THIS BW CARD P6: I I,~IHTE_AC_CONTINUE PUSH CX F3eA ESPIFF 4151 CALL nco SBFe MeV FHID_POSITION DI,BX j POP CX ; WRITE COUNT POP BX ; CHARACTER IN BX REG F3C9 51 4150 F3CF 59 4152: 4153 F300 58 4154 nOl 4155 P7: ADDRESS TO 01 REGISTER I WRITE_LOOP 4156 4157 ;----- WAIT FOR HORIZONTAL RETRACE 4158 F30l 88166300 4159 F30S 83C206 4160 F30B 4161 MOV DX.ADDR_6845 ; GET BASE ADDRESS ADD DX.6 ; POINT AT STATUS PORT PB: F30e EC 4162 IN TEST F30B 7SFB 4163 4164 Al.OX Al.1 ; GET STATUS F3D9 1.801 JHZ P. I WAIT UNTI L IT IS F30C FA 4165 nOE nOE EC 4166 ; IS IT LOW I NO MORE INTERRUPTS ClI P9: 4167 IN AL,DX ; GET STATUS F30F 1.801 4168 TEST AL,l I IS IT HIGH nEl 74FB 4169 JZ P9 ; WAIT UNTIL IT IS F3E3 8BC3 4170 MOV AX,BX I RECOVER THE CHAR/ATTR F3ES AB 4171 STOSW F3E6 FB STI F3E7 E2E8 4172 4173 LOOP P7 F3E9 E9D9fD 4174 JMP VIDEO_RETURN 4175 ; PUT THE CHAR/ATTR ; INTERRUPTS BACK ON WRITE_AC_CURRENT I AS MANY TIMES AS REQUESTED ENDP 4176 ; ------------------------------------------------ 4177 I WRITE_C_CURRENT 4178 THIS ROUTINE WRITES THE CHARACTER AT 4179 THE CURRENT CURSOR POSITION. ATTRIBUTE 4iso UNCHANGED 4181 ; INPUT 4182 (AH I :: CURRENT CRT MODE 4183 (BHl :: DISPLAY PAGE 4184 (CXl :: COUNT OF CHARACTERS TO ~ITE System BIOS A-59 LOC OBJ LINE SOURCE 4185 I All 4186 (OS) 4187 I E51 4188 F3Ee 60FC04 F3Ef 7208 F3Fl 8~FC07 4190 4191 4192 4195 F3F6 £97FOI 4196 4197 F3F9 F3F9 SO f3FA 51 F3FB EBAOfF F3F£ aSFB NONE 4201 4202 F401 58 4203 F402 4204 CMP JC CMP JE JMP AH,4 I IS THIS GRAPHICS pUSH PUSH AX CX CALL FIND_POSITION MOV POP POP OI,BX I ADDRESS TO 01 CX BX I WRITE COUNT Pl. AH,7 I IS THIS BN CARD PlO GRAPHICS_WRITE P10: 4198 4199 4200 F400 59 SEGMENT ; -- ---- -- - -- - --- - -- ----- ---- - - ------------- -- --.WRITE_C_CURRENT PROC NEAR 4193 4194 F3F4 7403 TO WRITE SEGMENT = REGEN ; OUTPUT 4189 F3Ee = CHAR = DATA I SAVE ON STACK I SAVE WRITE COUNT I BL HAS CHAR TO WRITE Pll: I WRITE_LOOP 4205 4206 4207 ; ----- WAIT FOR HORIZONTAL RETRACE MOV OX , ADOR_6845 ADD DX,6 i 4211 IN AL,DX I GET STATtJS F40A A801 42:12 TEST AL,l ; IS IT LOW F40C 75F8 JNZ CLI P .. F40£ FA 4213 421'. F40F 4215: F40F EC 4216 IN AL,DX ; GET STATUS F410 A801 4217 TEST Al,l ; IS IT HIGH F412 74F8 4218 P13 I WAIT UNTIL IT IS F414 8AC3 4219 JZ MOV Al,Bl I RECOVER CHAR F416 AA 422:0 STOSB F417 FB 422:1 STI F416 47 F419 E2£7 4222 INC 4223 LOOP OI Pll F418 E9A7FD 4224 JMP VIDEO_RETURN F402 88166300 4208 f406 83C206 F'409 4209 4210 f'l.09 EC ; GET BASE ADDRESS POINT AT STATUS PORT P12: I WAIT UNTIL IT IS i NO MORE INTERRUPTS Pl3: ; PUT THE CHAR/ATTR I INTERRUPTS BACK ON J BlR1P POINTER PAST ATIRIBUTE ; .1.5 MANY TIMES AS REQUESTED 4225 WRITE_C_CllRRENT ENDP 4226 422:7 ; ---------------------------------------------------------------; READ DOT -- WRITE DOT THESE ROUTINES WILL WRITE A DOT, OR READ THE DOT AT 4228 4229 TliE INDICATED LOCATION 4230 I ENTRY -- 4231 4232 OX = CX = COLUMN 4233 AL = DOT VALUE TO WRITE (1,2 OR 4 BITS DEPENDING ON MODE, 4234 ROW (0-199) (THE ACTUAL VALUE DEPENDS ON THE MODE) ( 0-639) ( THE VALUES ARE NOT RANGE CHECKED ) REQ'D FOR WRITE DOT ONLY, RIGHT JUSTIFIED) BIT 7 OF AL=l INDICATES XOR THE VALUE INTO THE LOCATION : 4235 4236 OS = 4237 ES = REGEN DATA SEGMENT SEGMENT 4238 4239 ; EXIT 4240 4241 ,----- --- -- --------------------------- ----- ------ -- - ------------- AL 4242 F41£ F41E £83100 4243 = DOT ASSUME CS:COOE,DS:DATA,ES:DATA R3 AL,ES:[SII PRoe READ_DOT 4244 VALUE READ, RIGHT JUSTIFIED, READ ONLY NEAR ; DETERMINE BYTE POSITION OF DOT F"+21 268A04 4245 CALL MOV F424 22C4 4246 Am Al,AH I MASK OFF THE OTHER BITS IN THE BYTE F426 OlEO 4247 SHL AL,Cl I lEFT JUSTIFY THE VALUE F428 BACE 4248 HOV CL,DH I GET NUMBER OF BITS IN RESULT f42A 02eo 4249 ROL Al,Cl I RIGHT JUSTIFY THE RESULT F42C E9%FD 4250 JMP VIDEO_RETt.RN I RETURN FROH VIDEO 10 4251 I GET THE BYTE ENDP 4252 F42F 4253 F42F 50 42:54 PUSIt AX I SAVE F430 50 4255 PUSH AX J F431 EBIEDD 4256 F434 02£8 4257 CALL SHR R3 AL,CL I DETERMINE BYTE POSITION OF THE DOT I SHIFT TO SET UP THE BITS FOR OUTPUT F436 22C4 4256 AND Al,AH I STRIP OFF THE OTHER BITS F438 268AOC 4259 HOY Cl,ES:[SIJ ; GET THE CURRENT BYTE F438 58 4260 POP F43C F6C380 4261 TEST BX BL,80H ; RECOVER XOR FLAG ; IS IT ON A-60 WRITE_DOT System BIOS PROC NEAR ~OT VALUE TWICE LOC OBJ LINE SOURCE 4262 4263 02 ; YES. XOR THE DOT F441 F6D4 NOT AH , SET THE MASK TO REMOVE THE F443 22ce 4264 ANO el.AH F445 OAel F447 4265 OR AL.CL F447 268804 4267 F44A 58 4266 POP AX f44B E977FD 4269 JMP YIDEO_RETURN F44E 4270 F44E 32Cl 4271 XOO F450 EBFS 4272 JMP ., F43F 7500 4266 JHZ Rl: I INDICATED BITS ; OR IN THE NEW VALUE OF THOSE BITS 1 F !NISH_OOT MOV Es:[srl,AL R2:: , RESTORE THE BYTE IN MEMORY ; RETURN FROt1 VIDEO ID I XOR_DOT EXCLUSIVE OR THE DOTS Al.Cl I FINISH UP THE WRITING 4273 WRITE_DOT 4274 4275 4276 ; ------------------------------------------ -------------; THIS SUBROUTINE DETERMINES THE REGEN BYTE LOCATION 4277 4278 ; OF THE INDICATED ROW COLUMN VALUE IN GRAPHICS MODE. ENTRY -OX = ROW VALUE (0-199) 4279 4260 4281 CX = COLUMN VALUE (0-639) EXIT -SI = OFFSET INTO REGEN BUFFER FOR BYTE OF INTEREST 4263 Cl = = 4284 DH =# 4282 F452 4285 4286 F452 53 4287 F453 SO 4286 ENOP AH MASK TO STRIP OFF THE BITS OF INTEREST BITS TO SHIFT TO RIGHT JUSTIFY THE MASK IN AH BITS IN RESULT ; -------------------------------------------------------PROC NEAR 03 ; SAVE BX DURING OPERATION PUSH BX PUSH AX ; WILL SAVE AL DURING OPERATION 4289 4290 ; ----- DETERMINE 1ST BYTE IN IOICATEO ROW BY NULTIPL YING ROW VALUE BY 40 4291 1----- ( lOW BIT OF ROW DETERMINES EVEN/ODD, 80 BYTES/ROW F454 B028 4292 4293 MaV AL,40 F456 52 4294 PUSH F457 BOE2FE 4295 ANO OX OL,OFEH I STRIP OFF ODD/EVEN BIT F45A f6E2 4296 MUL DL ; AX HAS ADDRESS OF 1ST BYTE , 4297 i SAVE ROW VALUE OF INDICATED ROW F45C 5A 4298 POP OX ; RECOVER IT F450 F6ClOI 4299 TEST DL.t ; TEST FOR EVEN/ODD F460 7403 4300 F462 050020 4301 F465 4302 F465 SBFO 4303 F467 58 4304 POP AX j F468 8BOl 4305 MOV OX,CX 1 COLUMN VALUE TO OX J2 ADO '4 AX,2000H R4: I JlJMp IF EVEN ROW I OFFSET TO LOCATION OF 000 ROWS I EVEN_ROW MOV SI,AX ; MOVE POINTER TO SI RECOVER AL VALUE 4306 4307 4308 4309 4310 j----- ; SET UP THE REGISTERS ACCORDING TO THE MODE 4311 CH 4312 CL 4313 BL 4314 BH 4315 4316 DETERMINE GRAPHICS MOOE CURRENTLY IN EFFECT i ---------------------------------------------------------------- = = = = MASK FOR LOW OF COLUMN ADDRESS ( 7/3 FOR HIGHIHED RES) # OF ADDRESS BITS IN COLUMN VALUE ( 312 FOR HIM) MASK TO SELECT BITS FROM POINTED BYTE (80H/COH FOR HIM) NUHBER OF VALID BITS IN POINTED BYTE ( 112 FOR H/M) 1---------------------------------------------------------------- F46A BBC002 4317 MOV BX.2COH F460 690203 4318 MOV CX,302H F470 603E490006 4319 CMP CRT_MODE.6 F475 7206 4320 JC .S F477 BB8001 4321 MOV BX,180H F47A 690307 4322 MaV CX,703H ; SET PARMS FOR MED RES i HANDLE IF MED ARES 1 SET PARMS FOR HIGH RES 4323 4324 j----- DETERMINE BIT OFFSET IN BYTE FROM COLUMN MASK 4325 F47D F47D 2lEA 4326 R5: ANO 4327 CH.oL i AODRESS OF PEL WIntIN BYTE TO CH 4328 4329 1----- DETERMINE BYTE OFFSET FOR THIS LOCATION IN COLUMN 4330 4331 433Z SH. OX,CL i F481 03F2 AOO SI,DX J INCREMENT THE POINTER F483 BAF7 4333 MaV DH,BH j F47F D3EA SHIFT BY CORRECT AMOUNT GET THE # OF BITS IN RESULT TO DH 4334 4335 ;----- tlULTIPLY BH (VALID BITS IN BYTEI BY CH (BIT OFFSET) 4336 F485 2AC9 4337 F487 4338 SUB CL.CL ; ZERO INTO STORAGE LOCATION R6: System BIOS A-61 SOURCE LINE LOC OBJ I lEFT JUSTIFY THE VALUE U.I F487 00C6 4339 4340 F489 02tO 4341 ADO CL,CH ; ADD IN THE BIT OFFSET VALUE F48B HeF 4342: DEC BH ; LOOP CONTROL F48D 75F8 4343 ROR IN AL (FOR WRITE) I J ON EXIT. CL HAS SHIFT COUNT JHZ R' F48F 8AE3 4345 MOV AH,BL ; GET MASK TO AH F491 D2EC 4346 SHR AH,Cl ; MOVE THE MASK TO CORRECT LOCATION F493 58 4347 POP BX I RECOVER REG F494 C3 4348 4349 RET 4344 4350 4351 ; RETURN WITH EVERYTHING SET UP ENDP R3 ; ---------------------------------------------------------------SCROLL UP j 4352 4353 TO RESTORE BITS I THIS ROUTINE SCROLLS UP THE INFORMATION ON THE CRT ; ENTRY 4354 CH.eL = UPPER LEFT CORNER OF REGION TO SCROLL 4355 OH.DL = LOWER RIGHT CORNER OF REGION TO SCROLL 4356 BOTH OF THE ABOVE ARE IN CHARACTER POSITIONS 4357 BH = FILL VALUE FOR BLANKED LINES 4358 AL = # LINES TO SCROLL I AL=O MEANS BLANK THE ENTIRE 4359 FIElD) 4360 OS = DATA SEGMENT 4361 ES = REGEN SEGMENT 4362 4363 EXIT NOTHING. THE SCREEN IS SCROLLED 4364 ; ------- - ------------------ ------------------- ------------------- F495 4365 GRAPHICS_UP F495 8ADe 4366 MOV BL,AL ; SAVE LINE COUNT IN BL F497 BSCI 4367 MOV AX.CX ; GET UPPER LEFT POSITION INTO AX REG PROC NEAR 4368 4369 j----- 4370 ; ----- ADDRESS RETURNED IS MULTIPLIED BY 2 FROM CORRECT VALUE USE CHARACTER SUBROUTINE FOR POSITIONING 4371 F499 E86902 4372 F49C B8fe 4373 MOV DI.AX ; SAVE RESULT AS DESTINATION ADDRESS 4374 4375 j----- DETERMINE SIZE OF WINDOW 4376 F49E 2BOI 4377 SUB DX,CX F4AO 81t20101 4378 ADO DX,IOIH ; AOJUST VALUES F4A4 00E6 4379 SAL OH,I ; MULTIPLY 11 ROWS BY 4 SAL OH,1 j SINCE 8 VERT DOTS/CHAR 4380 4381 F4A6 00E6 AND EVEN/ODD ROWS 4382 4383 ;----- DETERMINE CRT MODE 4384 F4A8 803E490006 4385 eMP ; TEST FOR MEDIUM RES f4AD 7304 4386 JHe ; FIND_SOURCE 4387 4388 ; ----- MEDIUM RES UP 4389 F4AF 00E2 4390 SAL F4Bl 01E7 4391 SAL Old 01 tl ; 11 COllJMNS * 2. SINCE 2 BYTES/CHAR ; OFFSET *2 SINCE 2 BYTES/CHAR 4392 4393 j----- DETERMINE THE SO\.JRCE ADDRESS IN THE BUFFER 4394 F4B3 4395 F4B3 06 4396 PUSH ES F4B4 IF 4397 POP OS F4B5 2:AEO 4398 SUB CH.CH ; ZERO TO HIGH OF COUNT REG F4B7 DOE3 4399 SAL Bl.l j F4B9 DOE3 4400 SAL BL.l F4BB 742:0 4401 JZ R11 F4BD BAC) 4402 MOV Al.Bl ; GET NUMBER OF LINES IN AL F4BF 8450 4403 MOV AH.80 ; 80 BYTESIROW R7: ; FINO_SOI../RCE I GET SEGMENTS BOTH POINTING TO REGEN MULTIPLY NUMBER OF LINES BY 4 ; IF ZERO. THEN BLANK ENTIRE FIELD F4Cl F6E4 4404 MUL AH I DETERMINE OFFSET TO SOURCE F4C3 BBF7 4405 MOV SI,DI F4C5 03FO 4406 ADO SI.AX , F4C7 8AE6 4407 MOV AH.DH ; NUMBER OF ROWS IN FIELD F4C9 ZAn 4408 SUB AH.BL ; DETERMINE NUMBER TO HOVE I SET UP SOURCE AOD IN OFFSET TO IT 4409 4410 1----- lOOP THROUGH. MOVING ONE ROW AT A TIME. BOTH EVEN AND ODD FIELDS 4411 F4CB 4412 F4CB E88000 4413 CALL IH 7 ; MOVE ONE ROW F4CE 81EEBOIF 4414 SUB SI. 2000H-80 I MOVE TO NEXT ROW F402: 81EFBOIF 4415 SUB DI.2000H-80 A-62 R8: System BIOS LOC OBJ F4D6 FEee F408 75Fl LINE SOURCE 4416 4417 4416 4419 .H R. DEC JNZ J----- j NUteER OF ROWS TO HOVE ; CONTINUE TILL ALL MOVED FILL IN TlfE VACATED LINE(S) 4420 F4DA 4421 F4DA BAC7 4422 F40C 4423 R9: HOV Al.BH • CLEAR_ENTRY ; ATTRIBUTE TO FIll WIlli RIO: RIB ; CLEAR TlIAT ROW F40F 8lEFBOIF 4425 SUB DI.20DCH-BO ; POINT TO NEXT LINE F4E3 FEte 4426 DEC BL ; NUMBER OF LINES TO FILL F4DC E88800 4424 CALL F4E5 7SF5 4427 JHZ RIO F4E7 E908Ft 4428 JMP VIDEO_RETURN ; CLEAR_LOOP ; EVERYTHING DONE F4EA 4429 4430 HOV Bl.OH ; BLANKJIELD i SET BLANK COlNT TO F4EA 8ADE Rll: ; 4431 F4EC EBEe R. 4432 4433 4434 4435 EHOP ; - - - - - - - - ------- - - ----- -- - ---------------- -- - - - -- -- -- ---- - - - - - --; SCROLL DOWN 4436 4437 EVERYTHING IN fIELD ; CLEAR TliE fIELD THIS ROUTINE SCROLLS 0010I-I TliE INfORMATION ON THE CRT ENTRY 4438 CH,CL '" UPPER lEFT CORNER OF REGION TO SCROll 4439 DH.Dl = LOWER RIGHT CORNER OF REGION TO SCROLL 4440 BOTH OF THE ABOVE ARE IN CHARACTER POSITIONS 4441 BH = FILL VALUE FOR BLANKED LINES 4442 AL = • 4443 4444 OS = DATA SEGMENT 4445 4446 LINES TO SCROLL (AL=O MEANS BlANK THE ENTIRE FIELD I ES = REGEN SEGMENT ; EXIT 4447 NOTHING. THE SCREEN IS SCROLLED 4448 ; ---------------------------------------------------------------- F4EE 4449 GRAPHICS_DOWN f4EE FO 4450 STD F4EF BADe 4451 MOV BL.AL ; SAVE LINE COUNT IN BL 4452 HOV AX.DX ; GET LOWER RIGHT POSITION INTO AX REG F4F 1 8Be2 PROC NEAR ; SET DIRECTION 4453 4454 ; ----- USE CHARACTER SUBROUTINE FOR POSITIONING 4455 ;----- ADDRESS RETURNED IS MULTIPLIED BY 2 FROH CORRECT VALUE 4456 F4F3 E80F02 F4F6 8BFe 4457 4458 HOV OI.AX I SAVE RESULT AS DESTINATION ADDRESS 4459 4460 ; ----- DETERMINE SIZE OF WINDOW 4461 F4F8 2:BOl 4462 SUB OX.CX r4FA 81C20101 4463 ADD DX,10lH ; ADJUST VALUES f4FE 00E6 4464 SAL DH.I ; MULTIPLY. ROWS BY 4 SAL DH.1 ; 4465 F500 00E6 SINCE 8 VERT DOTS/CHAR 4466 AND EVEN/ODD ROWS 4467 4468 4469 ;----- DETERMINE CRT HOOE F502 803E490006 4470 CHP ; TEST FOR HEDIlI1 RES F507 7305 4471 JNC ; FItI)_~CE_O~ 4472 4473 ;----- MEDIUM RES DOWN 4474 F509 00E2 4475 SAL OLd 4476 F50B DIE7 F50D 47 ; • COLlJ'flS ; * 2. SINCE 2 BYTES/CHAR (OFFSET OK I 4477 SAL 01.1 ; OFFSET *2 SINCE 2 BYTES/CHAR 4478 INC 01 ; POINT TO LAST BYTE 4479 4480 ; ----- DETERMINE THE SOURCE ADDRESS IN THE BUFFER 4481 F50E 4482 R12: ; f50E 06 4483 PUSH ES FSOF IF 4484 POP OS SUB FIND_SOURCE_D~ ; BOTH SEGHENTS TO REGEN F510 UEO 4485 CH.CH ; ZERO TO HIGH OF COUNT REG F512 81C7FOOO 4486 ADD 01.240 ; POINT TO LAST ROW OF PIXE LS F516 Don 4487 SAL BLol ; ttULTIPlY NUMBER OF LINES BY 4 F518 Don f5lA 742:E 4488 SAL BL.I 4489 JZ R,. i IF ZERO. TliEN BUNK ENTIRE FIELD F5lC 8AC3 4490 HOV AL.Bt i GET NUt1BER OF LINES IN AL F51E 8450 4491 HOV AN.80 ; 80 BYTES/ROW F52:0 F6E4 4492 "'L AN J DETERMINE OFFSET TO SOURCE System BIOS A-63 LOC OBJ LINE SOURCE FS22 SBF7 4493 F524 2BFO 4494 SUB F526 8AE6 4495 MOV F528 2AE3 4496 4497 4498 SI,OI SI,AX AH,DH AH.Bl MOV SUB I SET UP SOURCE I SUBTRACT THE OFFSET I NUNBER OF ROWS IN FIELD I DETERMINE NUMBER TO MOVE ;----- lOOP THROUGH, HOVING ONE ROW AT A TIME, BOTH EVEN AND 000 FIELDS 4499 R13: F52A 4500 F52A E82100 4501 CAll "7 F52D 81EE5020 450Z SUB 51.2000H+80 F531 SlEF5020 4503 SUB DI,2000H-teO F535 FEee 4504 DEC AH F537 75Fl 4505 4506 4507 J ROW_lOOP_DOWN ; MOVE ONE ROW I MOVE TO NEXT ROW ; HUMBER OF ROWS TO HOVE ." JHZ I CONTINUE TILL ALL HOVED j----- FILL IN THE VACATED LINEIS) 4508 F539 4509 F539 8AC7 4510 F53B 4511 F53B £82900 4512 R14: I CLEAR_ENTRY_DOWN MOV Al,BH CALL "8 ; ATTRIBUTE TO FILL WITH R15: ; CLEAR_lOOP_DOWN ; CLEAR A ROW FS3E 81EF5020 4513 SUB DI.2000H+80 ; POINT TO NEXT LIHE FS42 FECB 4514 DEC BL ; NUNBER OF LINES TO FILL F544 75FS 4515 JHZ R'S I CLEAR_lOOP_DOWN F546 FC 4516 CLD F547 E918FC 4517 JHP VIDEO_REn.JI:;!N ; EVERYTHING DONE F54A 4518 F54A SADE 4519 MOV BL.DH ; SET BLANK COUNT TO JHP R'4 I CLEAR THE FIELD ; RESET THE DIRECTION FLAG R16: ; BlANKJIELO_DOWN 4520 F54C EBES ; 4521 452:2: GRAPHICS_DOWN EVERYTHING IN FIElD ENDP 452:3 4524 1----- ROUTINE TO MOVE ONE ROW OF INFORNATION 4525 F54E 4526 PRDC NEAR F54E 8AC,., 4527 MOV CL.Ol F550 56 4528 PUSH F551 57 4529 PUSH 51 01 ; SAVE POINTERS F552 F3 4530 REP MOVSB ; NOVE THE EVEN FIElD 01 51 R'7 ; NUMBER OF BYTES IN THE ROW F553 A4 FS54 SF 4531 POP F555 5E 4532 PDP F556 81C600Z0 4533 ADD SI.ZOOOH F55,., 81C70020 4534 ADD OI.ZOOOH F55E 5b 4535 PUSH 51 F55F 57 453b PUSH 01 ; SAVE THE POINTERS F560 8ACA 4537 HOV CL.OL ; COUNT BACK F562 F3 4538 REP Novse ; MOVE THE ODD FIELD F564 SF 4539 PDP F565 5E 4540 POP 01 51 ; POINTERS BACK F5b6 C3 4541 RET I POINT TO THE ODD FIELD F5b3 A4 4542 .17 ; RETURN TO CAlLER ENDP 4543 4544 ; ----- CLEAR A SINGLE ROW 4545 F567 4546 ""DC NEAR F567 8ACA 4547 HDV Cl.OL I NUMBER OF BYTES IN FIELD F569 57 4548 PUSH 01 ; SAVE POINTER F56,., F3 4549 REP STOSB ; STORE THE NEW VALUE F56C SF 4550 POP 01 ; POINTER BACK F56D 81C70020 4551 ADD oI.2000H ; POINT TO ODD fIELD f571 57 4552 PUSH 01 f57Z 8ACA 4553 HOV CL.OL f574 F3 "8 F56B AA 4554 REP STOSS F576 SF 4555 POP 01 F577 C3 4556 FILL THE ODD fIlELo F575 AA 4557 RET "8 ;---------------------------------------------------------------- 4559 ; GRAPHICS WRITE 4560 THIS ROUTINE WRITES THE ASCII CHARACTER TO THE 4561 CURRENT POSITION ON THE SCREEN. 4562 ; ENTRY 4563 At 4564 BL 4565 A-64 I REn.JI:;!N TO CAlLER ENDP 4558 System BIOS = CHARACTER TO WRITE = COLOR ATTRIBUTE TO BE USED FOR fOREGROUND COLOR IF BIT 7 IS SET. THE CHAR IS XOR '0 INTO THE REGEN LaC OBJ LINE SOURCE BUFFER (0 IS USED FOR THE BACKGROlrnD COLOR I 4566 4567 ex = NUMBER 4568 OS = DATA 4569 ES = 4570 OF CHARS TO WRITE SEGMENT REGEN SEGMENT ; EXIT NOTHING IS RETURNED 4571 4572 4573 ; GRAPHICS READ 4574 THIS ROUTINE READS THE ASCII CHARACTER AT THE CURRENT 4575 CURSOR POSITION ON THE SCREEN BY MATCHING THE DOTS ON THE SCREEN TO THE CHARACTER GENERATOR CODE POINTS 4576 4577 ; ENTRY NONE 4578 4579 ( 0 IS ASSUMED AS THE BACKGROUND COLOR ; EXIT AL 4580 = CHARACTER READ AT THAT POSITION (0 RETURNED IF NONE FOUND) 4581 4582 4583 FOR BOTH ROUTINES, THE IMAGES USED TO FORM CHARS ARE 4584 I 4585 I CONTAINED IN ROM FOR THE 1ST 128 CHARS. TO ACCESS CHARS IN THE SECOND HALF, THE USER MUST INITIALIZE THE VECTOR AT 4586 INTERRUPT IFH (LOCATION 0007CH J TO POINT TO THE USER 4587 SUPPLIED TABLE OF GRAPHIC IMAGES (8XS BOXES). 4588 FAILURE TO DO SO WILL CAUSE IN STRANGE RESULTS 4589 4590 ASSUME F578 4591 GRAPHICS_WRITE F57S 6400 4592 MOV CS:COOE,OS:DATA.ES:oATA AH ,0 ; ZERO TO HIGH OF CODE POINT F57A 50 4593 PUSH AX I SAVE CODE POINT VALUE PROC NEAR 4594 4595 1----- DETERMINE POSITION IN REGEN BUFFER TO PUT CODE POINTS 4596 F57B E88401 4597 CALL S26 I FIND LOCATION IN REGEN BUFFER F57E S8F8 4598 NOV oI.AX ; REGEN POINTER IN or 4599 4600 ;----- DETERMINE REGION TO GET CODE POINTS FROM 4601 F580 58 4602 pop AX ; RECOVER CODE POINT F581 3eso 4603 4604 OMP AL.SOH I IS IT IN SECOND HAlF JAE SI ; YES F583 7306 4605 4606 1----- IMAGE IS IN FIRST HALF. CONTAINED IN ROM 4607 f585 BE6EF ... 4608 HOV 5I.DFA6EH F588 OE 4609 PUSH CS f589 EBOF 4610 JMP SHORT 52: ; SAVE SEGMENT ON STACK 4611 4612 ;----- IMAGE IS IN SECOND HALF, IN USER RAM 4613 51: F588 4614 F58B 2.C80 4615 SUB AL,SDH ; ZERO ORIGIN FOR SECOND HALF F580 1 E 4616 4617 PUSH DS ; SAVE DATA POINTER SUB SI,SI 4618 MOV oS,SI 4619 ASSUME oS:AB50 F58E 2BF6 F590 BEOE ; EXTEND_CHAR ; ESTABLISH VECTOR ADDRESSING F592 C5367eoo 4620 lDS SI,EXT_PTR ; GET THE OFFSET OF THE TABLE FS96 eCDA 4621 MOV OX,OS ; GET THE SEGMENT OF THE TABLE 4622 ASSUME DS:oATA F598 IF 4623 POP DS I RECOVER DATA SEGMENT F599 52 4624 4625 4626 PUSH DX ; SAVE TABLE SEGMENT ON STACK F59A 4628 ;----- DETERMINE GRAPHICS HOOE IN OPERATION 4627 I DETERMINE_MODE S2: f59A DIED 4629 SAL AX,! ; MULTIPLY CODE POIHT FS9C DIED 4630 SAL AX,! ; F59E 0 lEO 4631 SAL AX,l F5AO 03FO 4632 ADD SI,AX FSA2 e03E490006 4633 OMP CRT_MODE ,6 FSA7 IF 4634 4635 4636 POP DS j JO S7 ; TEST fOR MEDIUM RESOLUTION MODE F5AS 7Z2C 4637 VALUE BY 8 I 51 HAS OFFSET OF DESIRED CODES RECOVER TABLE POINTER SEGMENT ;----- HIGH RESOLUTION MODE 4638 ; HIGH_CHAR 53: FSAA 4639 fSAA 57 4640 PUSH PUSH 01 51 ; SAVE REGEN POINTER 4641 HOV oH,4 I NUMBER OF TIMES THROUGH LOOP F5AB 56 FSAC 8604 .... ; SAVE CODE POItITER System BIOS A-65 LINE LOC OBJ 4643 F5AE "44 F5AE AC SOURCE 54. LOOse TEST BL,SDH JHZ 56 F582 7516 lt6lt5 4646 F584 AA 4647 STOSB f585 At F586 4648 LOOSS F5AF F6C380 4649 I GET BYTE FROH CODE POINTS I SHOULD WE USE THE FUNCTION I TO PUT CHAR IN I STORE IN REGEN BUfFER 55' 4650 . .51 ADD ES:[DI+2DDOH-IJ,AL bI , 79 F5BE FEtE 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 46624663 4664 4665 DEC OH JNZ 54 PDP pop 51 OI I RECOVER REGEN POINTER INC Ot ; POINT TO NEXT CHAR POSITION LOOP 53 ~ MORE CHARS TO WRITE FSCO 75Et FSC2 5£ f5C3 FSC4 F5C5 F5C7 SF 47 E2£3 E9FBFB FSCA fStA 263205 F5CD AA FSCE At FSCF 263285FFIF F5D4 fBED 4666 .... HOY ; STORE IN SECCHJ HAlF I MOVE TO NEXT ROW IN REGEN I DONE WITH LOOP FSB6 268885FFlF FSBB 83C74F JHP 56; XOR Al,ES:[DIJ STOS8 loosB XOR JHP I EXClUSIVj: OR WITH CURRENT ; STORE THE CODE POINT ; AGAIN FOR Al,ES: 101+2000H-11 55 DO~ FIELD J BACK TO HAINSTREAH ;----- ttEDIlJ1 RESOLUTION WRITE 4667 F~6 F5De DIE7 F5DA £8Dl00 FSDD 4670 FSDD 57 4673 4674 4675 4671 4672 FSDE 56 F5Df 8604 4676 4677 F5El F5El At FSE! E8DEOa F5£5 23C3 F5£7 F6C280 F5E'" 7407 FSEF 26324501 F5F3 F5F6 26864501 FSf" At F5fS E8C500 F5FE 2.le3 F603 740A F605 2632 ...5002:0 F60 ... 2632850120 F60F F60F 2688AS0020 F614 2688650120 F61C FEtE F61E 7SCI F620 5£ F621 SF F622 47 F623 47 F624 £287 F626 E99CFB CAll 519 I SAVE HIGH COLOR BIT OFFSET*2 SINCE 2 BYTEs/CHAR j ; EXPAND BL TO FULL WORD OF COLOR I MED_CHAR 58: DI ; SAVE REGEN POINTER PUSH 51 ; SAVE THE CODE POINTER i10V OH.4 ; NUMBER OF LOOPS PUSH 59: Loose I GET CODE POINT 521 J DOUBLE UP ALL THE BITS AND AX,BX ; CONvERT THEM TO FOREGRotHJ 4681 4682 TEST Dt,eOH ; IS THIS XOR FUNCTION JZ 510 ; NO. STORE IT IN AS IT IS 4683 XOR XOR AH.~S:[DI1 ; DO FUNCTION WITH HALF AL,ES:[DI+ll ; J STORE FIRST BYTE COLOR ( 0 BACK ) ; AND WITH OTHER HALF SID: 4686 4687 ttOV t10V ES:[OIJ.AH ES:[OI+1J ••U 4688 4689 LODse CAll AND TEST 521 AX,8X Dl,80H J CONVERT TO COLOR I AGAIN, IS THIS XOR FUNCTION JZ 511 ; NO. JUST STORE TME VALUES XOR AH,ES:[OI+2:000H1 J FUNCTION WITH FIRST HALF XOR AL,ES:[OI+2001HJ J At«) WITH SECOND HALF 4690 4691 F600 F6C280 CL.St 01,1 CALL 4685 FSn 268825 HOY SAL 4678 4679 4680 .... F5EC 263225 F619 83C750 57: 4669 F506 8AD3 4692 4693 4694 4695 ; STORE SECOND BYTE I GET CODE POINT Sl1: 4696 4697 HOY ES: (OI+2000Hl,AH HOV ES:loI+2000H+ll,Al J STORE IN SECOND PORTION OF BUFFER ADD 01,80 ; POINT TO NEXT LOCATION DEC DH S9 SI ; KEEP GOING 01 ; RECOVER REGEN POINTER 4698 4699 4700 4701 4702 pop pop 4703 4704 INC DI INc DI 4705 4706 4707 LOOP S8 JNz J RECOVER CODE PONTER J POINT TO NEXT CHAR POSITION ; MORE TO tRITE JHP GRAPHICS_~iTE ENDP j----':"'------------------- 4706 4709 I GRAPHICS READ F629 4710 4711 J .. ----------------------GRAPHICS_READ PROt NEAR F629 £80600 4712 CALL F62C 88FO 4713 I10V S26 SI,AX I SAVE IN SI F62.£ 83Eeoe 4714 4715 4716 4717 4718 SUB SP,8 ; AlLOCATE SPACE MOV BP,SP F631 8BEt I 1----- DETERMINE GRAPHICS HODES 4719 A-66 I CONVERTED TO OFFSET IN REGEN System BIOS to SAVE THE READ CODE POINT J POINTER TO SAVE AREA LaC OBJ LINE SOURCE F631 &03E490006 4720 CHP F638 06 4721 PUSH ES F639 IF 4722 POP OS I POINT TO REGEN SEGMENT 4723 JC 513 J MEOIUtt RESOLUTION F63A nu 4724 4725 J----- HIGH RESOLUTION READ 4726 4727 1----- GET VALUES FROM REGEN BUFFER AND CONVERT TO CODE POINT 4728 F63C 8604 4729 F63E 4730 4731 F63E 6,6,04 MOV OH,4 MOV AL.ISI ; NUttBER OF PASSES 512: J I GET FIRST BYTE AREA 4732 4133 HOV [BP),AL ; SAVE IN STORAGE F643 45 INC BP I NEXT LOCATION F644 6A840020 4734 HOV Al,[SI+2000Hl I GET LOWER REGION BYTE F648 884600 4735 MOV (BP),AL ; ADJUST AND STORE F64B 4S 4736 INC BP F64C 63C650 4737 ADO 51.80 J POINTER INTO REGEN F64F FEtE 4738 DEC DH ; LOOP CONTROL F651 75E6 4739 JNZ ; DO IT SOME MORE f653 E81790 4740 512 515 F640 884600 JMP I GO MATCH THE SAVED CODE POINTS 4741 F656 F656 01E6 4742 ;----- MEDIUH RESOLUTION READ 4743 4744 513: F658 5604 4745 4746 F65A 4747 F65A E88800 SAL 51,1 I MOV OH,4 ; NUMBER OF PASSES I GET PAIR BYTES FROM REGEN OFFSET*2 SINCE 2 BYTES/CHAR 514: CALL 523 F650 81t60020 4750 ADD 51, 2000H ; GO TO LOWER REGION F661 E88100 4751 CALL 523 ; GET THIS PAIR INTO SAVE ; ADJUST POINTER BACK INTO UPPER 4748 i 4749 F664 81EEBOlf 4752 SUB 51, 2000H-80 f668 FECE 4753 DEC OH F66A 75EE 4754 4755 4756 JNZ 514 INTO SINGLE SAVE ; KEEP GOING UNTIL ALL 8 DONE ;----- SAVE AREA HAS CHARACTER IN IT. HATCH IT 4757 FMC 4758 F66C BF6EFA90 4759 f670 DE 4760 F671 07 4761 POP ES I CODE POINTS IN CS F672 83E008 4762 SUB BP,8 ; ADJUST POINTER TO BEGINNING SI,BP 515: ; FIND_CHAR MOV PUSH DI.OFFSET CRT_CHAR_GEN J ESTABLISH ADDRESSING CS 4763 OF SAVE AREA f675 BBFS 4764 MOV F677 Fe 4765 CLO F678 BODO 4766 F67A 4767 MOV ENSURE DIRECTION Al,O I CURRENT CODE POINT BEING MATCHED SI6: F67A 16 4768 PUSH 55 ; ESTABLISH ADDRESSING TO STACK f67B IF 47&9 POP DS ; F,OR THE STRING COMPARE F67C BA8000 4770 MaV OX,128 ; NUMBER TO TEST AGAINST PUsH 51 I SAVE SAVE AREA POINTER 517: F67F 4771 F67F 56 4772 F680 57 4773 PUSH DI ; SAVE CODE POINTER F661 890800 4774 MOV CX,8 I NUMBER OF BYTES TO HATCH F684 F3 4775 REPE CMPSB I COMPARE THE 8 BYTES F68b SF 4776 POP 01 I RECOVER THE POINTERS 51 F685 A6 f687 SE 4777 POP F686 741E 4778 JZ 518 ; IF ZERO FLAG SET, THEN MATCH OCCURRED F66A FEtD 4779 INC AL I NO MATCH, MOVE ON TO NEXT fMC 63C706 4780 ADO DI,8 F68F 4A 4781 DEC ox I F690 75EO 4782 JHZ 517 ; DO ALL OF THEM ; NEXT CODE POINT LOOP CONTROL 4783 4784 ;----- CHAR NOT MATCHED, MIGHT BE IN USER SUPPLIED SECOND HALF 4785 F692 3COO 4786 CMP Al,O ; Al <> 0 IF ONLY IS" HALF SCANNED F694 7412 4787 J' 518 I IF = 0, F696 2BCO 4788 SUB AX,AX F696 6E06 4789 HOV 4790 ASSutlE as: ABSO F69A C43E7COO 4791 LES DI,EXT_Pl'R ; GET POINTER OS,AX THEN ALL HAS BEEN SCANNED ; ESTABLISH ADDRESSING TO VECTOR F69E 8ceo 4792 HOV AX,ES , SEE IF THE POINTER REAllY EXISTS f6AO OBC7 4793 OR AX,OI ; IF ALL 0, THEN DOESN'T EXIST F6A2 7404 4794 JZ 518 ; NO SENSE LOOKING F6A4 B080 4795 MOV Al,128 I ORIGIN FOR SECotI) HALF System BIOS A-67 LOC OBJ FbA6 EBOZ LINE SOURCE 4796 JMP 51. 4797 ASSUME DS:DATA J GO BACK AND TRY FOR IT 4798 4799 ;----- CHARACTER IS FOUND ( Al=D IF NOT FOUND I 4600 F6A8 4801 F6A8 83C408 4802 ADO SP.8 ; READJUST THE STACK. THROW AWAY SAVE F6AB E917FB 4803 JMP VIDEO_RETURN ; ALL DONE S18: 4804 GRAPHICS_READ 4805 ; -------------------------------------------------------- 4806 EXPAND_MED_COLOR THIS ROUTINE EXPANDS THE LOW 2: BITS IN Bl TO 4807 4808 FILL THE ENTIRE BX REGISTER 4809 ENTRY 4810 4811 ENDP BL = COLOR TO BE USED ( BX = COLOR TO BE USED ( 8 REPLICATIONS OF THE LOW 2 BITS ) ; EXIT 4812 2 COLOR BITS J 4813 4814 i -------------------------------------------------------- 519 FbAE 4815 PROC NEAR F6AE 60E303 4816 AND BL.3 i ISOLATE THE COLOR BITS F6BI 8AC3 4817 MOV AL,BL ; COPY TO AL ex ; SAVE REGISTER MOV CX.3 ; HUMBER OF TIMES TO DO THIS F6B3 51 F6B4 690300 4819 f6B7 4820 F6B7 ODED S20: 4821 SAL F6B9 ODED 4822 SAL AL,1 ; F6BB OA08 4823 OR BL.AL ; ANOTHER COLOR VERSION INTO BL FbBD E2F8 4824 LOOP 520 ; FILL ALL OF BL F6BF SAFB 4825 HOV BH.BL F6CI 59 4826 POP ex FoC2 C3 AL,1 RET LEFT SHIFT BY 2 FILL UPPER PORTION j ; REGISTER BACK ALL DONE j ENDP 4828 S19 4829 j --------------- -------------------------- --- ------------ 4830 EXPAND_BYTE 4831 THIS ROUTINE TAKES THE BYTE IN AL AND DOUBLES 4832 ALL OF THE BITS, TURNING THE 8 BITS INTO 16 BITS. THE RESULT IS LEFT IN AX 4833 4634 j-------------------------------------------------------- F6e} 4835 521 PROC NEAR F6e3 52 4836 PUSH ox F6C4 51 4837 PUSH ex F6es 53 4638 PUSH BX I SAVE REGISTERS F6C6 lBOZ 4839 SUB OX,OX ; RESULT REGISTER Foes 690100 4840 MOV CX,1 j F6eB 4841 F6te SBD8 4842 MOV BX,AX i BASE INTO TEMP F6CD 2309 4843 AND BX,CX ; USE MASK TO EXTRACT A BIT F6CF OB03 4844 OR oX,ex ; PUT IHTD RESULT REGISTER F601 DIED 4845 5HL AX,! F603 olEl 4846 SHL CX,1 ; SHIFT BASE ANa MASK BY 1 F6DS 8808 4847 MOV BX,AX ; BASE TO TEMP F607 2309 4848 AND BX,CX ; EXTRACT THE SAME BIT F609 0603 4849 OR OX,BX i f6DS olEl 4850 5HL CX,l ; SHIFT ONLY MASK NOW, 4851 MASK REGISTER I PUT INTO RESULT MOVING TO NEXT BASE FoOD 73Et 4652 JNe 522 ; USE MASK BIT COMING OVT TO TERMINATE F6DF 8BC2 4853 MOV AX,OX ; RESULT TO PARM REGISTER f6El 58 4854 POP BX F6E2 59 4855 POP ex f6B SA 4856 POP ox F6E4 C3 4857 RET I ALL DONE 4858 S21 4859 ; -------------------------------------------------------- 4860 ENDP j MED_READ_BYTE 4861 THIS ROUTINE WILL TAKE 2 BYTES FROM THE REGEN 4862 BUFFER, COMPARE AGAINST THE CURRENT FOREGROUND 4863 COLOR, AND PLACE THE CORRESPONDING ON/OFF SIT 4864 PATTERN INTO THE CURRENT POSITION IN THE SAVE 4865 ; 4866 j AREA ENTRY 4867 51,05 4868 ex = SP = 4869 4870 j 4872 = POINTER TO REGEN AREA OF INTEREST EXPANDED FOREGROUND COLOR POINTER TO SAVE AREA EXIT 4871 A-68 ; RECOVER REGISTERS SP IS INCREMENT AFTER SAVE i - --- - - - - - --- -- --- -- - -- ----- -- - - - - - -- ----- ---- --- ----- --- System BIOS LaC OBJ LINE F6ES 4873 SOURCE S23 NEAR AH,[SIJ GET FIRST BYTE MOV AL,ISI+lJ GET SECOND BYTE MaV eX,oeOOOH PROC F6ES 6A24 4874 F6E7 8A4401 4875 F6EA 8900CO 4876 F6ED 8200 4877 MOV altO F6EF 4878 F6EF 65CI F6FI Fa F6F2 7401 4879 TEST 4880 CLC 4881 JZ F6F4 F9 488Z MOV 2: BIT MASK TO TEST THE ENTRIES ; RESULT REGISTER 524: AX,ex l ; IF ZERO, IT IS BACKGROUND STC 525: IS THIS SECTION BACKGROI..NJ? ; C LEAR CARRY IN HOPES THAT IT IS 52. I WASN'T, SO SET CARRY F6FS 0002 4883 RCL QL,l F6F? 01E9 4884 SHR eX,I FbF9 DlE9 4885 SHR eX.I ; HOVE THE HASK TO THE RIGHT BY 2: BITS F6FB 73F2 4886 JNt S24 ; DO IT AGAIN IF MASK DIDN'T FALL OUT F6FD 885600 4887 MOV [BP1,DL ; STORE RESULT IN SAVE AREA noD 45 nOl C3 4888 INC BP ; ADJUST POINTER 4889 RET ; HOVE THAT BIT INTO THE RESULT ; ALL DONE ENOP 4890 S23 4891 4892 I - --- - - - - - - - - - - - - - ----------------- -------- - - - --; V4_POSITION 4893 THIS ROUTINE TAKES THE CURSOR POSITION 4894 CONTAINED IN THE MEMORY LOCATION. AND 4895 CONVERTS IT INTO AN OFFSET INTO THE 4896 REGEN BUFFER, ASSIMING ONE BYTE/cHAR. 4897 FOR MEDIUM RESOLUTION GRAPHICS, 4898 4899 THE NUMBER MUST BE DOUBLED. ENTRY 4900 NO REGISTERS, MEMORY LOCATION 4901 490Z CURSOR_POSH IS USED ; EXIT 4903 4904 AX CONTAINS OFFSET INTO REGEN BUFFER ; ---------------------------- ___________________ _ F702 4905 526 F702 10.15000 4906 F105 4907 F705 53 4908 PUSH BX F10b 8808 4909 MOV BX,AX ; SAVE A COPY OF ClRRENT F70S 8AC4 4910 MOV AL.AH ; GET ROWS TO AL F70A f6264AOO 4911 MUL BYTE PTR CIH_COLS ; MULTIPLY BY BYTES/COLIJI'fl F70E DIED 4912 SHL AX 01 ; MULTIPLY F710 DIED 4913 SHL AX,! F712 2AFF 4914 SUB BH,BH PROC NEAR MOV AX,CURSOR_POSN GRAPH_POSH LABEL ; GET CURRENT CURSOR NEAR , SAVE REGISTER * C~SOR 4 SINCE 4 ROWS/BYTE ; ISOLATE COLlJtt>.I VALUE F714 03C3 4915 AOO AX,BX ; DETERMINE OFFSET F716 58 4916 POP BX , RECOVER POINTER F717 C3 4917 4918 526 491 9 ; - - - - ---- -- ------- - - - - - - - - - -- --- - ---------------------------------------- RET ENDP ; ALL DONE 4921 THIS INTERFACE PROVIDES A TELETYPE LIKE INTERFACE TO T1iE VIDEO 492Z CARD. WE INPUT CHARACTER IS WRITTEN TO WE CURRENT CURSOR 4923 POSITION. AND THE CURSOR IS MOVED TO THE NEXT POSITION. I f THE 4924 CURSOR LEAVES THE LAST COLUMN OF THE FIELD, THE COLUHN IS SET 4925 TO ZERO, AND THE ROW VALUE IS INCREMENTED. IF THE ROW VALUE 4926 LEAVES THE FIELD, THE CURSOR IS PLACED ON THE LAST ROW. FIRST 4927 COLUMN, AND THE ENTIRE SCREEN IS SCROLLED UP ONE LINE. t&iEN 4928 THE SCREEN IS SCROLLED UP. THE ATTRIBUTE FOR FILLING THE NEWLY 4929 BLANKED LINE IS READ FROM THE CURSOR POSITION ON THE PREVIOUS 4930 LINE BEFORE THE SCROLL, IN CHARACTER MODE. IN GRAPHICS ttODE. 4931 THE 0 COLOR IS USED. 4932 ; ENTRY 4933 (AH) ; CURRENT CRT MOOE 4934 {All = CHARACTER TO BE WRITTEN 4935 NOTE THAT BACK SPACE, CAR RET, BElL AJ.IJ LINE FEED ARE HANllED 4936 AS COHMAHDS RATHER THAN AS DISPLAYABLE GRAPHICS 4937 (Bll 4938 4939 4940 4941 4942 = FOREGROUND COLOR FOR CHAR WRITE IF CURRENTLY IN A GRAPHICS MODE ; EXIT ALL REGISTERS SAVED I - -- ---------- --- - - - - - - - - - - - ---------- - ---------------------------------- ASSUME CS:CODE,DS:DATA F7la 4943 F718 50 4944 PUSH F719 50 4945 PUSH F7U 8403 4946 MOV AH,3 F71C 8A3E6200 4947 I10V SH.ACTIVE_PAGE ; GET THE CURRENT ACTIVE PAGE F720 COlO 4948 , READ THE CURRENT CURSOR 4'" INT pop lOH F72:2 58 AX ; RECOVER OtAR WRITE_TIV PROC NEAR AX AX ; SAVE REGISTERS , SAVE CHAR TO WRITE POSITION System BIOS A-69 LOC OBJ LINE SOURCE 4950 4951 ; ----- OX NOW HAS THE CURRENT CURSOR POSITION 4952- F723 3e08 CHP AL.a I IS IT A BACKSPACE F7ZS 7452 4953 4954 JE U8 ; BACK_SPACE F727 3COO 4955 CHP AL,OOH I IS IT CARRIAGE RETURN F729 7457 U' ; CAR_RET 4956 JE F72B 3eOA 4957 CMP AL,OAH I IS IT A LINE FEED F720 7457 4958 JE UIO I F12F 3C07 4959 4960 CHP Al,07H JE U11 I IS IT A BELL ; BELL F731 745A LINE3EED 4961 4962- ;----- WRITE THE CHAR TO THE SCREEN 4963 4964 F733 640.60 4965 NOV AH,10 F735 B90100 4966 4967 MOV eX.l ; WRITE CHAR ONLY ; ONLY ONE CHAR INT 10M ; WRITE THE CHAR F738 COlO 4968 4969 1----- POSITION THE CURSOR FOR NEXT CHAR 4970 F73A FEel 4971 INC F73C 3AI64.6oOO 4972 CMP Dl.BYTE PTR CRT_COLS ; TEST FOR COLUMN OVERFLOW F740 7533 4973 JNZ U7 ; SET_CURSOR F742 8200 4974 MOV OL.O ; COLUMN FOR CURSOR F744 SOFEl6 F747 752.60 4975 CMP OH,24 4976 JNZ U. DC J SET_CURSOR_INC 4977 4978 ; ----- SCROLL REQUIRED 4979 F749 4980 F749 B402 4981 MOV AH ,2 F74B COlO 4982 INT 10M U1: j SET THE CURSOR 4983 4984 j----- DETERMINE VALUE TO FILL WITH DURING SCROLL 4985 F74D A04900 498b NOV F7s0 3C04 4987 CMP AL,4 F752 7206 4988 JC U2 CMP AL.7 F754 3C07 4989 F7s6 B700 4990 F758 7506 4991 F75A 4992 AL,CRT_MODE I GET THE CURRENT MODE j READ-CURSOR FILL WITH BACKGROUND MOV BH,O j JNE U3 ; SCROll-UP U2: ; READ-CURSOR F75A B408 4993 F75C COlO 4994 INT 10M j F75E 8AFe 4995 MOV BH,AH I STORE IN BH F7bO 4996 F760 B80106 4997 HOV AX,60lH j F763 2BC9 4998 SUB eX,ex ; UPPER LEFT CORNER F7bS B618 4999 MOV DH,24 F767 8A164AOO 5000 MOV DL,BYTE PTR CRT_COLS F768 FEeA 5001 DEC DC F76D 5002 F7bD COlO 5003 1NT 10M F7bF 5004 MOV AH.8 U3: READ CHAR/ATTR .l.T C~RENT CURSOR ; SCROLL-UP U4: us: SCROLL ONE LINE LOWER RIGHT ROW ; LOWER RIGHT COLUMN j VIDEO-CALL-RETURN j SCROLL UP THE SCREEN j TTY-RETURN F76F 58 5005 POP AX j RESTORE THE CHARACTER F770 E952FA 5006 JMP VIDEO_RETURN j RETURN TO CALLER F773 5007 F773 FEC6 5008 INC OM F775 5009 F775 B402 5010 NOV AH,2 F777 EBF4 SOIl JMP U4 U6: I SET-CURSOR-INC U7: j NEXT ROW ; SET -CURSOR j ESTABLISH THE NEW CURSOR 5012 5013 j ----- BACK SPACE FOUND 5014 F779 5015 F779 80FAOO 5016 CMP DL,O I ALREADY AT END OF LINE F77C 74F7 5017 JE U7 I SET_CURSOR F77E FECA 5018 DEC DC I NO -- JUST HOVE IT BACK F780 EBF3 5019 JMP U7 I SET_CURSOR U8: 5020 5021 j----- CARRIAGE RETURN FOUND 5022 F782 5023 F782 B200 5024 F784 EBEF 5025 U9: 5026 A-70 System BIOS "OV JMP DL,O ; MOVE TO FIRST COLUMN U7 ; SET_CURSOR LOC OBJ LINE 5027 SOURCE ;----- LINE FEED FOUND 5028 F78b 5029 F78b BOFElS 5030 Uto: I BOTTOM Of SCREEN DH.24 CMP F789 75£8 5031 JNE U6 , F7aB EBBC 5032 JMP Ul ; NO. JUST SET THE CLJi;!SOR YES. SCROLL THE SCREEN 5033 5034 ; ----- Bell FOUNtl 5035 Ull: F7eD 5036 F78D 8302 5037 MOV F78f £871EE 5038 CALL BEEP ; SOUND THE POD BELL F792 EBOB 5039 JMP US ; TTY_RETURN I SET UP COlMT FOR 8EEP BL.G 5040 5041 ; ------- -------- ------------------------------------------------- 5042 LIGHT PEN 5043 THIS ROUTINE TESTS THE LIGHT PEN SWITCH AND THE LIGHT 5044 PEN TRIGGER. IF BOTH ARE SET, THE LOCATION OF THE LIGHT: 5045 PEN IS DETERMINED. OTHERWISE. A RETURN WITH NO 5046 5047 INFORMATION IS MADE. ; ON EXIT 5048 (AH I = 0 IF (AH) = 5049 NO LIGHT PEN INFORMATION IS AVAILABLE BX.CX.DX ARE DESTROYED 5050 5051 1 IF LIGHT PEN IS AVAILABLE (DH,oLl 5052 POSITION = RASTER 5054 (BX) = 5057 5058 5059 POSITION BEST GUESS AT PIXEL HORIZONTAL POSITION: 1---------------------------------------------------------------- 5056 F794 ROW,COLUMN OF CURRENT LIGHT PEN (CH) 5055 f794 03 = 5053 ASSUME j----VI CS:COOE.DS:OATA SUBTRACT_TABLE LABEL BYTE DB F795 03 f796 05 F797 05 F798 03 F799 03 F79A 03 F79B 04 5060 F79C PROC NEAR 5061 5062 ;----- WAIT FOR LIGHT PEN TO BE DEPRESSED 5063 F79C 8400 F79E 88166300 5064 5065 NOV I10V AH,D OX.ADOR_6845 F7A2 83C206 5066 ADD DX.6 ; POINT TO STATUS REGISTER F7A5 EC 5067 IN AL.DX ; GET STATUS REGISTER F7Ab A804 5068 TEST AL.4 ; TEST LIGHT PEN SWITCH F7A8 757£ 5069 JHZ V6 ; NOT SET. RETURN I SET NO LIGHT PEN RETURN CODE ; GET BASE ADDRESS OF 6845 5070 5071 ;----- NOW TEST FOR LIGHT PEN TRIGGER 5072 F7AA A802 5073 TEST AL,2 ; TEST LIGHT PEN TRIGGER F7AC 7503 5074 JNZ V7A ; RETURN WITHOUT RESETTING TRIGGER 5075 JMP V7 F7AE £98100 5076 5077 ;----- TIHGGER HAS BEEN SET I READ THE VALUE IN 5078 'lBl F7Bl 8410 5079 5080 V7A: MDV AH.16 ; LI~HT PEN REGISTERS ON 6845 5081 5082 ; ----- INPUT REGS POINTED TO BY AH. AND CONVERT TO ROW COLUMN IN OX 5083 F7B3 88166300 5084 MDV ox .ADDR_6645 F7B7 6AC4 5085 MDV AL,AH ; REGISTER TO READ f7B9 EE 5086 OUT DX.AL ) SET IT UP F7eA 42 5087 INC ox I DATA REGISTER ; GET THE VALUE ; ADDRESS REGISTER FOR 6845 f7BB EC 5088 IN AL.DX F7Be 8A£8 5089 MOV CH.AL ; SAVE IN CX F7BE 4A 5090 DEC ox ; ADDRESS REGISTER F7BF FEC4 5091 INC AH net 5092 MOV AL.AH 5093 OUT DX.AL 8AC4 F7C3 EE I SECOND DATA REGISTER INC ox F7C5 EC 5095 IN AL.DX I GET SECOND DATA VALUE F7C6 8A£5 S096 I10V AH.CH I AX HAS INPUT VALUE F7C4 42 5094 I POINT TO DATA REGISTER System BIOS A-71 LOC OBJ LINE SOURCE 5097 5098 ;----- AX HAS THE VALUE READ IN FROM THE 6845 5099 nCB 8AIE4900 5100 MaV Bl.CRT_HOoE F7CC 2AFF 5101 SUB F7eE ZE8A9F94F7 F703 2&3 5102 5103 MaV SUB BH,BH BL.CS:Vl[BX] AX,BX F70S 861E4EOO 5104 MOV ex. CRT_START F7D9 DlEB 5105 SH' SUB BX,l JNS V, AX,AX F1DB 2BC3 5106 F1DO 7902 5107 5108 5109 F70F 2BCO 5110 5111 5112 F7El F7El 8103 SUB j----- I MODE VALUE TO ex I DETERNINE AMOUNT TO SUBTRACT ; TAKE IT AWAY Ax,ex ; IF POSITIVE, DETERMINE MODE I <0 PLAYS AS 0 DETERMINE NODE OF OPERATION V2: I DETERMINE_HODE 5113 5114 MOV CMP CRT_MODE ,4 ; DETERMINE IF GRAPHICS OR ALPHA JB V4 I ALPHA_PEN F7EA 803E490007 5115 5116 CMP CRT_MODE.7 F7EF 7423 5117 JE V4 F7E3 803E490004 F7EB 722A CL,3 ; SET *8 SHIFT COUNT i ALPHA_PEN 5118 5119 ; ----- GRAPHICS MODE 5120 F7Fl 8228 F7F3 F6FZ 5121 MOV DL.40 ; OIVISOR FOR GRAPHICS 5122 OIV OL ; DETERMINE ROW( AL) AND COLlJMN( AH) 5123 ; AL RANGE 0-99, AH RANGE 0-39 5124 5125 ; ----- DETERMINE GRAPHIC ROW POSITION 5126 F7F5 8AE8 5127 CH,AL ; SAVE ROW VALUE IN CH F7F7 02EO 5128 ADD CH,CH ; *2 FOR EVEN/ODD FIELD F7F9 8ADC 5129 MOV BL,AH ; COLUMN VALUE TO BX F7FB 2AFF 5130 SUB BH,BH F7FD 803E490006 5131 CMP CRT_MODE,6 ; DETERMINE MEDIUM OR HIGH RES F802 7504 5132 JHE V, I NOT_HIGH_RES MaV CL,4 ; SHIFT VALUE FOR HIGH RES SAL AH.l 1 COLUMN VALUE TIMES 2 FOR HIGH RES F804 BI04 5133 FM6 DOE4 5134 Faoa 5135 F80S D3E3 5136 MaV V3: ; NULTIPL Y BY 8 FOR MEDIUM RES I NOT_HIGH_RES SHL BX,CL ; MULTIPLY *16 FOR HIGH RES 5137 5138 1----- DETERMINE ALPHA CHAR POSITION 5139 F80A 8A04 5140 HOV DL,AH ; COLUt1H VALUE FOR RETURN FSOC 8AFO 5141 MaV DH,AL ; ROW VALUE F80E DOEE 5142 SH, DH,l ; OIVIDE BY 4 F810 DOEE 5143 SHR DH,l F812 EBI2 5144 JMP SHORT V5 FOR VALUE IN 0-24 RANGE LIGHT _PEN_RETURN_SET 5145 5146 1----- ALPHA MODE ON LIGHT PEN 5147 F814 5148 F814 F6364AOO 5149 OIV BYTE PTR CRT_COLS F818 8AFO 5150 MOV DH,AL ; ROWS TO DH F81A 8AD4 5151 MOV OL,AH I COLS TO DL V4: I ALPHA_PEN ; DETERMINE ROW,COLUMN VALUE FalC 02EO 5152 SAL AL,CL ; MUL TIPL Y ROWS * a F8tE 8AE8 5153 MOV CH,AL 1 GET RASTER VALUE TO RETURN REG F8Z0 8ADC 5154 MOV BL,AH I COLUMN VALUE XO, BH,BH SAL BX,CL F822 32FF 5155 F824 D3E3 S156 F626 5157 F8l6 B401 VS: 5158 TO ex LIGHT_PEN_RETURN_SET HOV All. 1 Fa28 5159 Fa28 52 5160 PUSH OX F829 88166300 5161 MOV DX,ADDR_6a45 ; GET BASE ADDRESS F82D a3C207 5162 ADD OX.7 ; POINT TO RESET PARM F830 EE 5163 OUT DX,AL ; ADDRESS. NOT DATA, IS IMPORTANT POP OX ; RECOVER VALUE V6: f831 SA 5164 F832 5165 Fa32 SF 5166 PDP 01 F833 5E 5167 POP SI Fa34 IF 5168 POP OS V7: ; RETURN_NO_RESET F835 IF 5169 POP OS FS36 IF 5170 POP OS F837 IF 5172 PDP OS F838 07 5173 POP ES 5171 A-72 System BIOS INDICATE EVERTHING SET , LIGHT_PEN_RETURN ; SAVE RETURN VALUE (IN CASE) I DISCARD SAVED 8X,ex,Ox LOC OBJ F!39 Cf LINE SOURCE IRET 5174 5175 READ_lPEN EHOP 5176 5177 ;--- INT 12 ------------------------------------------------------------- 5176 ; MENORY_SIZE_DET 5179 THIS ROUTINE DETERMINES THE AMOUNT OF t'lEHORY IN THE SYSTEM 5180 AS REPRESENTED BY THE SIolITCHES ON TlfE PLANAR. 5181 SYSTEM HAY NOT BE ABLE TO USE lID MEMORY UNLESS THERE IS A FULL: 5182 COMPLEMENT OF 64K BYTES ON THE PLANAR. 5183 NOTE THAT THE ; INPUT 5184 NO REGISTERS 5185 THE HEMORY_SIZE VARIABLE IS SET DURING POWER ON DIAGNOSTICS 5186 ACCORDING TO THE FOLLOWING HARDWARE ASSUMPTIONS: 51a7 PORT 60 BITS 3.2 = 00 - 16K BASE RAM 51as 01 - 5189 10 - 4BK BASE RAM 5190 11 - 64K BASE RAM 5191 PORT 62 BITS 3-0 INDICATE AMOUNT OF I/O RAM IN 32K INCREMENTS E.G •• 0000 - NO RAM IN 110 CHANNEL 5192 5193 5194 0010 - 64K RAM IN I/O CHANNEL. ETC. ; OUTPUT 5195 5196 5197 32K BASE RAM (AX) :: NUMBER OF CONTIGUOUS IK BLOCKS OF HEMORY ; -----------------------------------------------------------------------ASSUME CS:COOE ,OS:OATA F841 5196 ORG F841 5199 HEHORY_SIZE_OET PROC F841 FB 5200 STI F84Z IE 5201 PUSH OS F843 EBF806 5202 CALL DDS OF841H FAR ; INTERRUPTS BACK ON ; SAVE SEGMENT F846 AI1300 5203 MOV AX ,MEMORY_SIZE ; GET VALUE f849 IF 5204 POP OS i F84A CF 5205 IRET RECOVER SEGMENT ; RETlmN TO CALLER 5207 5206 5209 ;--- INT 11 ----------------------------------------------------; EQUIPMENT DETERMINATION 5210 THIS ROUTINE ATTEMPTS TO DETERHINE WHAT OPTIONAL 5211 5212 5213 DEVICES ARE ATTACHED TO THE SYSTEM. ; INPUT NO REGISTERS 5214 THE EQUIPJLAG VARIABLE IS SET DURING THE POWER ON 5215 DIAGNOSTICS USING THE FOLLOWING HARDWARE ASStR1PTIONS: 5216 PORT 60 5217 PORT 3fA = INTERRUPT 10 REGISTER OF 8250 5218 5219 PORT 378 = OUTPUT PORT Of PRINTER -- 8255 PORT THAT 52:20 5221 = LOW ORDER BYTE OF EQUPMENT BITS 7-3 ARE ALWAYS 0 CAN BE READ AS WELL AS WRITTEN ; OUTPUT 5222 (AX) IS SET, BIT SIGNIFICANT. TO INDICATE ATTACHED I/O 5223 BIT 15.14 ::: NUMBER OF PRINTERS ATTACHED 5224 BIT 13 HOT USED 5225 BIT 12 = GAME I/O ATTACHED 5226 BIT 11.10.9 ::: t-U1BER OF RS232 CARDS ATTACHED 5227 BIT 8 UNUSED 5228 BIT 7.6 = NUMBER OF DISKETTE DRIVES 00=1. 01=2. 10=3. 11=4 ONLY IF BIT 0 = 1 5229 5230 5231 BIT 5.4 = INITIAL VIDEO HOOE 00 - UNUSED 5232 01 - 40X25 BW USING COLOR CARD 5233 10 - 80X25 BW USING COLOR CARD 11 - 60X25 BW USING BW CARD 5234 5235 BIT 3.2 = PLANAR RAM SIZE (OO=16K,01=32K,10=48K.ll=6410 5236 BIT 1 NOT USED 5237 BIT 0 :: IPl FROM DISKETTE -- THIS BIT It«IICATES THAT 5238 5239 5240 5241 5242 THERE ARE DISKETTE DRIVES ON THE SYSTEH NO OTHER REGISTERS AFFECTED ;---------------------------------------------------------------ASSUME CS :CODE .DS:OATA ORG Of840H f840 5243 F840 5244 F84D FB 5245 ST! F84E IE 5246 PUSH DS F84F E8Ee06 5247 CALL DDS F852 AllOOO 5248 MOV AX,EQUIP _FLAG ; GET THE CURRENT SETTINGS F655 IF 5249 POP DS ; RECOVER SEGMENT 5250 IRET F856 CF EQUIPMENT PROC FAR ; INTERRUPTS BACK ON ; SAVE SEGMENT RESISTER ; RETURN TO CALLER System BIOS A-73 LINE LOC OBJ 5251 SOURCE EQUIPMENT EtIlP 52:52 52:53 ;--- INT 15 ------------------------------------------- _________ _ 5254 ; CASSETIE 110 5256 (AH) =0 =1 52:57 (AH I = 2: 52:55 (AH) 5256 TURN CASSETTE MOTOR OFF READ 1 OR MORE 256 BYTE BLOCKS FRON CASSETTE (ex I = CO\.JHT = POINTER I ES,BX) 5262 (OXI = COUNT 5263 (tY) =0 =1 5264 TO LAST BYTE READ + 1 OF BYTES ACTUALLY READ IF NO ERROR OCCURRED IF ERROR OCCURRED I AH 1 :;: ERROR RETURN IF I CV) = 1 5265 5266 = 5267 = 02 5268 = 5269 I AH 1 = 01 IF CRC ERROR WAS DETECTED IF DATA TRANSITIONS ARE LOST 04 IF NO DATA WAS FOUND 3 WRITE 1 OR MORE 256 BYTE BLOCKS TO CASSETTE 5270 IES,BXI 5271 (CX) = = POINTER TO DATA BUFFER COUNT OF BYTES TO WRITE ; ON EXIT 5273 I EX,BXI 5274 (eX) = = POINTER TO LAST BYTE WRITTEN + 1 0 (AH) = ANY OTHER THAN ABOVE VALUES CAUSES ICY 1= 1 5275 AND (AH 1= 80 TO BE RETURNED I INVALID COMMAND). 5276 5277 5278 TO DATA. BUFFER OF BYTES TO READ ; ON EXIT 5261 5272 = POINTER (ES,BXI 5259 5260 TURN CASSETTE HOTOR ON ;---------------------------------------------------------------ASSUME as : DATA. ES: NOTHING. SS: NOTHING ,CS: CODE f859 F859 5279 ORG 5280 CASSETTE_IO F859 FB 5281 STI FaSA IE 5282 PUSH OS F858 £6E006 5283 CALL DDS FaSE 802671007F 5284 AND BIOS_BREAK. 7FH ; MAKE SURE BREAK FLAG IS OFF F863 E80400 5285 CALL loll ; F866 IF 5286 POP OS F667 CA02:00 5287 RET ,eo. 5288 CASSETTE_IO ENDP 5289 loll NEAR 5290 5291 ; - -- - - - - - --- - - -- - --------------- -- --- ----- - - -- -- - -- ---- -PURPOSE: PROC OF859H PROC FAR ; INTERRUPTS BACK ON ; ESTABLISH ADDRESSING TO DATA C~SSETTE_IO_CONT ; INTERRUPT RETURN TO CALL APPROPRIATE IWUTINE DEPENDING ON REG AH 5292 5293 AH 5294 5295 5296 ROUTINE ; -------------------------------------------------------HOTOR ON 5297 HOTOR OFF 5298 READ CASSETTE BLOCK 5299 5300 WRITE CASSETTE BLOCK , , , ; - - - - ------ - -- -- - -------- -- - - - -- - - - ---- ------- -- - -------TURN ON MOTOR? OR AH.AH Fe6 .. OAElt 5301 FMC 7413 5302 JZ MOTOR_ON F86E FEte 5303 DEC AH Fa70 7418 5304 JZ MOTOR_OFF F672 FEte 5305 DEC AH F874 74l.A. 5306 JZ READ_BLOCK Fe76 FEte 5307 DEC AH F878 7503 5308 JNZ W2 Fe7A. E92401 5309 JMP WRITE_BLOCK F87D 5310 1012: Fa7D 8480 5311 F87F f9 5312 STC fa8D C3 5313 RET 5314 ,sal MOV WI 5315 5316 5317 5319 5320 WRITE CASSETTE BLOCK? NOT_OEF~NEO , , , ERROR. UNDEFINED OPERATION I ERROR FLAG YES. DO IT COMMAND NOT DEFINED ENDP PROC NEAR -----------------------------------TO TURN ON CASSETTE MOTOR ; ---------------------------------------; READ CASSETTE OlTTPUT AL.PORT_B IN AL,NOT oaH ; CLEAR BIT TO TURN ON MOTOR PORT_B.AL ; WRITE IT OUT 5324 SUB AH.AH ; CLEAR AH 5325 RET 5322 5323 Fa87 2AE4 A-74 YES. 00 IT AND 5321 FaBS E661 F8a" YES. DO IT READ CASSETTE BLOCK? OUT F88l 24F7 F885 F889 C3 YES. DO IT TURN OFF MOTOR? ; ---; PlIRPOSE: 5316 F8BI E461 AH. paOH , , , , , 1013: 5326 MOTOR_ON EHllP 5327 MOTOR_OFF PROC System BIOS NEAR LaC OBJ LINE SOURCE 53,8 i - - - -. - .------ - -- -.---------- - - -- -------- 5329 I PURPOSE: 5330 TO TURN CASSETTE MOTOR OFF 1----------------------------.----------- F88A E461 5331 5332 FesC oeoe 5333 OR AL,PORT.B Al,08H F88E ESFS 5334 JMP W3 5335 5336 MOTOR_OFF ENOP F890 READ_BLOCK PROC 5337 I - - - - - -- -- - -. - - - - - - --.-.----- - ------ ------ ----.-- -- -- ------ -- - - -- IN NEAR PURPOSE: 5338 5339 5340 5341 ; READ CASSETTE OUTPUT ; SET BIT TO TURN OFF ; ~ITE IT. CLEAR ERROR. RETURN TO READ 1 OR MORE 256 BYTE BLOCKS FROM CASSETTE I ON ENTRY: ES IS SEGMENT FOR MEMORY BUFFER (fOR COMPACT CODE I 5342 5343 ex POINTS TO START OF MEMORY BUFFER 5344 ex CONTAINS MJt1BER OF BYTES TO READ 5345 J ON EXIT: 5346 5347 5348 ex ex POINTS 1 BYTE PAST LAST BYTE PUT IN MEM CONTAINS DECREMENTED BYTE COUNT OX CONTAINS HUHBER OF BYTES ACTUALLY READ 5349 5350 CARRY FLAG IS CLEAR IF NO ERROR DETECTED 5351 5352 CARRY flAG IS SET IF CRC ERROR DETECTED ; --_._--------------------------.--._---------------------------- F890 53 5353 PUSH F891 51 5354 PUSH CX ; SAVE CX F892: 56 5355 PUSH I 5AVE 51 Fe93 BE0700 5356 Fe96 E8BFOI 5357 51 51. 7 BEGIN_OP F899 5351;1 F899 E462 5359 5360 IN AND AL.PORT_C AL.OlOH ; GET INTIAL VALUE F89B 2:410 F890 A26BOO 5361 MOV LAST_VAL.AL I SAVE IN LOC LAST_VAL FSAO BA7A3F 5362 Mav DX.16250 ; • OF TRANSITIONS TO LOOK FOR FaA3 5363 F8A3 F6067100S0 5364 TEST BIOS_BREAK. 80H FaAS 7503 5365 JHZ W.A MOV CALL BX ; SAVE BX ; SET UP RETRY COUNT FOR LEADER I BEGIN BY STARTING MOTOR W4: ; SEARCH FOR LEADER ; MASK OFF EXTRANEOUS BITS W5: ; WAIT_FOR_EDGE ; CHECK FOR BREAK KEY ; JUT1P IF NO BREAK KEY 5366 FaAA 5367 F8AA 4A 5368 F8AB 7503 5369 I JUT1P IF BREAK KEY HIT W6: aEC DX JNZ W7 JMP W17 ; JUT1P IF NO LEADER FOl.H) CALL READ_HALF_BIT ; IGNORE FIRST EDGE JCXZ ws I JUMP IF NO EDGE DETECTED MOV DX.0378H ; CHECK FOR HALF BITS ; JUT1P IF BEGINNING OF LEADER FSAD W6A: 5370 F8AD E98400 5371 F880 F6BO E8C600 5372 5373 F8B3 nEE 5374 FBB5 BA7803 5375 FSBS B90002: 5376 MeV CX.200H ; MUST HAVE AT LEAST THIS ttANY ONE SIZE ; PULSES BEFORE CHCKNG FOR SYNC BIT (0) IN AL, 021H I INTERRUPT MASK REGISTER OR AL.l ; DISABLE TIMER INTERRUPTS OUT 02:IH. AL TEST BIOS_BREAK. SOH I CHECK FOR BREAK KEY W7: 5377 F8BB E42:1 5378 F8BD OCOI 5379 F8BF E621 5380 FaCI 5381 F8CI F606710080 5382: F5C6 756C 5383 W17 ; JUT1P IF BREAK KEY HIT F8C8 51 5364 PUSH CX ; SAVE REG CX F5C9 E8ADOO 5385 CALL F8CC OBC9 53136 ; GET PULSE W~DTH ; CHECK FOR TRANSITION FaCE 59 5387 OR pop READ_HALF _BIT CX, CX CX ; RESTORE ONE BIT COUNTER F8CF 74C8 5388 JZ W4 I JUMP IF NO TRANSITION FeDI 3BD3 5389 CMP OX,BX I CHECK PULSE WIDTH F8D3 n04 5390 JCXZ W9 I IF CX=O THEN WE CAN LOOK W6: ; SEARCH-LOR JNZ I FOR SYNC BIT (0) 5391 FaD5 73CZ 5392 JNC W4 F8D7 f2E8 5393 LOOP W8 I JUMP IF ZERO BIT (NOT GOOO LEADER) F809 5394 ; DEC CX AND READ ANOTHER HALF ONE BIT ; FIND-SYNC FaD9 nE6 5395 JC W8 I JUMP IF ONE BIT (STILL LEADER) W9: 5396 5397 ;----- A SYHCH BIT HAS BEEN FOUND. READ SYN CHARACTER: 5398 F8DB £89BOO 5399 CALL READ_HALF _BIT ; SKIP OTHER HALF OF SYNC BIT 10 J FeDE E86AOO 5400 CALL F8EI 3C16 5401 CMP READ_BYTE AL, 16H ; SYNCHRONIZA lION FeE3 7549 5402: JNE WI. ; JUMP IF BAD LEADER FOUND. ; READ SYN BYTE CHARACTE~ 5403 5404 ;----. GOOD CRe so READ DATA BLOCK(S) System BIOS A-75 LINE LOC OBJ SOURCE 5405 FeES SE 5406 POP 51 FaE6 59 5407 pOP ex FaE7 58 5408 POP BX I RESTORE REGS 5409 1---------------------------------------------------------------- 5410 ; READ 1 OR MORE 256 BYTE BLOCKS FROM CASSETTE 5411 5412 I ON ENTRY: 5413 ES IS SEGMENT FOR MEMORY BUFFER (FOR COMPACT CODE) ex 5414 5415 5416 BX POINTS 1 BYTE PAST LAST BYTE PUT IN MEM 5417 5418 5419 5420 POINTS TO START OF MEMORY BUFFER CX CONTAINS NUMBER OF BYTES TO READ I ON EXIT: CX CONTAINS DECREMENTED BYTE COUNT OX CONTAINS NUMBER OF BYTES ACTUALLY READ 1---------------------------------------------------------------PUSH CX ; SAVE BYTE cout·n feE8 51 5421 F8E9 5422 F8E9 C7Q66900FFFF 5424 MOV CRC_REG,OFFFFH FeEF BMOOI 5425 MOV DX,256 FeF2 5426 FeF2 F606710080 5427 TEST BIOS_BREAK. 80H ; CHECK FOR BREAK KEY FaF7 7523 5428 W13 I ; COME HERE BEFORE EACH IoUO: I 256 BYTE BLOCK IS READ 5423 1411: I INIT CRC REG ; SET OX TO DATA BLOCK SIZE I RO_BLK JUMP IF BREAK KEY HIT f8F9 E84FOO 5429 CALL READ_BYTE ; READ BYTE FROM CASSETTE FaFC 721E 5430 JC 10113 j faFE nos 5431 JCXZ 10112 ; IF WE'VE ALREADY REACHED MOV ES:tBX),AL ; STORE DATA BYTE AT BYTE PTR CY SET INDICATES NO DATA TRANSITIONS ; END OF MEMORY BUFFER 5432 5433 ; SKIP REST OF BLOCK f900 268807 5434 F903 43 5435 INC BX ; INC BUFFER PTR F904 49 5436 DEC ex ; DEC BYTE COUNTER f905 5437 DEC OX 10112: ; 5438 F905 4A F906 7FEA ; 5439 LOOP UNTIL DATA BLOCK HAS BEEN READ FROM CASSETTE. ; DEC BLOCK CNT 5440 JG 1411 j RD_BLK f908 E84000 5441 CALL READ_BYTE I NOW READ TWO CRC BYTES F90B E83000 5442 CALL READ_BYTE F90E 2AE4 5443 SUB AH.AH ; CLEAR AH f910 813E69000FID 5444 CMP CRC_REG, !.DOFH I IS THE CRC CORRECT F916 7506 5445 JNE 10114 ; IF NOT EQUAL CRe IS BAD Fna 5446 JCXZ 1415 I IF BYTE COUNT IS ZERO nOb 5447 I 5449 f91C 5450 JMP "" MOV AH,OlH INC AH 1413: 5452 5453 F91E 5454 f91E FEC4 5455 ; STILL HaRE. SO READ ANOTHER BLOCK ; HISSING-DATA ; NO DATA TRANSITIONS SO 5451 f91C 8401 THEN WE HAVE READ ENOUGH ; SO WE WIL L EXIT 5448 F9U, EBCD ; SET AH=02 TO INDICATE I DATA TIMEOUT 1414: ; BAO-CRe 5456 ; EXIT EARLY ON ERROR ; SET AH=Ol TO INDICATE CRe ERROR Fno 5457 Fno SA F921 2BOI 5458 POP ox ; CAl'.CULATE COUNT OF 5459 SUB OX.CX ; DATA BYTES Acru.6.lLY READ PUSH AX ; SAVE AX (RET CODE) 10115: ; RO-BLK-EX 5460 ; RETURN COUNT IN REG OX F923 50 5461 F924 F6C490 5462 TEST AH. 90H j F927 7513 5463 JNZ 10118 ; JUMP IF ERROR DETECTED F929 ESlFOD 5464 CALL READ_BYTE j Fnc ESCE 5465 F92E 5466 F92E 4E 5467 F92F 7403 5468 F931 E965FF 5469 F934 5470 CHECK FOR ERRORS READ TRAILER JHP SHORT 10118 ; SKIP TO TURN OFF MOTOR DEC 51 ; CHECK RETRIES JZ W17 ; JUMP IF TOO MANY RETRIES JMP W4 ; JUMP IF HOT TOO MANY RETRIES 1416: j Wl7: j BAD-LEADER NO VALID DATA FOUND 5471 5472 ;----- NO DATA FROM CASSETTE ERROR, I.E. TIMEOUT 5473 f934 SE F935 59 5474 pop SI I RESTORE REGS 5475 POP CX I RESTORE REGS F936 58 5476 POP BX f937 ZBDl 5477 SUB OX.OX I F939 8404 5478 MOV AH.04H ; TIME OUT ERROR {NO LEADER l f938 50 5479 PUSH AX F93C 5480 A-76 IU8: System BIOS ZERO HUMBER OF BYTES READ I HOT-OFF LOC OSJ LINE SOURCE IH ; RE_ENABLE lNTERRUPTS F93C E421 5481 F93E 24FE 5482 AND Al. 021H Al. OfFH- 1 F940 E&21 5463 OUT 021H. AL F942 E845FF 5484 CALL MOTOR_OFf I TURN OF F MOTOR F945 56 5485 5486 5487 POP eMP AX AH,OlH I SET CARRY IF ERROR (AH>Q) F946 60FCOl F949 F5 f94A C3 I RESTORE RETURN CODE eMC ; FINISHED RET 5488 5489 READ_BLOCK 5490 5491 i ---------------------------------------- ; PURPOSE: 5492 5493 ENDP TO READ A BYTE FROM CASSETTE ; ON EXIT 5494 REG AL CONTAINS READ DATA BYTE 5495 i ---------------------------------------- F94B 5'1-96 READ_BYTE F94B S3 5497 PUSH BX f94C 51 5'1-98 PUSH ex F940 BI08 5499 MOY CL,8H i F94F 5500 f94F 51 5501 PUSH ex ; SAVE CX 5502 5503 PROC NEAR 10119: ; SAVE REGS BX.CX SET BIT COUNTER FOR 8 BITS ; BYTE-ASH ; ---------- ---------------------; READ DATA BIT FROH CASSETTE 550'1- f950 E82600 F953 E3l0 5505 CALL READ_HALF _BIT ; READ ONE PULSE 5506 JCXZ W21 ; PUSH BX ; SAVE 1ST HALF BIT'S ; READ COMPLEMENTARY PULSE IF CX=O THEN TIMEOUT ; BECAUSE OF NO DATA TRANSITIONS 5507 F955 S3 5508 ; PULSE WIDTH I IN BX) 5509 F956 E82000 5510 CAll READ_HALF _BIT F959 58 5511 POP AX ; COMPUTE DATA BIT F95A nI9 5512 JCXZ W21 ; IF CX=O THEN TIMEOUT DUE TO ; NO DATA TRANSITIONS 5513 F95C 0308 5514 ADD BX,AX I f95E 81FBF006 5515 eMP BX. 06FOH ; CHECK FOR ZERO BIT F962 F5 5516 eMC PERIOD ; CARRY IS SET IF ONE BIT F963 <;IF 5517 lAHF f964 59 5518 POP ; SAVE CARRY IN AH ex ; RESTORE CX 5519 i 5520 I NOTE: MS BIT OF BYTE IS READ FIRST. REG CH IS SHIFTED lEFT WITH 5521 I 5522 CARRY BEING INSERTED INTO LS 5523 BIT OF CH. i 5524 AFTER ALL 8 BITS HAVE BEEN READ. THE MS BIT OF THE DATA BYTE 5525 5526 F965 0005 WIll BE IN THE MS BIT OF REG CH ReL 5527 CH.I ; ROTATE REG CH LEFT WITH CARRY TO 5528 LS BIT OF REG CH ; RESTORE CARRY FOR CRC ROUTINE F967 9E 5529 SAHF F968 E80900 5530 CALL CRC_GEN ; GENERATE CRC FOR BIT F96B FEet;! 5531 DEC CL ; JHZ W19 ; BYTE_ASH MOY AL.CH 5533 F%F 8ACS 5534 f971 Fa F972 5535 F972 59 5537 POP CX F973 58 5538 POP OX F974 C3 5539 RET f975 5540 f975 59 5541 POP F976 F9 5542 STC F977 EBf9 5536 55'1-3 LOOP TILL ALL 8 BITS OF DATA ; ASSEMBLED IN REG CH 5532 F96D 75EO ; RETURN DATA BYTE IN REG AL eLe 10120: ; RO-BYT-EX ; RESTORE REGS CX,BX ; FINISHED W21: ; NO-DATA ex i RESTORE CX ; INDICATE ERROR JMP W20 I NO_BYT_EX ENDP 5544 READ_BYTE 5545 ;------------------------------------------------ 5546 ; PURPOSE: 5547 5548 5549 5550 5551 TO COMPUTE TIME TILL NEXT DATA TRANSITION (EDGE) i ON ENTRY: EDGE_CNT CONTAINS LAST EDGE COUNT ; ON EXIT: 5552 AX CONTAINS OlD LAST EDGE CO\.JHT 5553 ex 5554 CONTAINS PULSE WIDTH (HALF BIT) • -- ----- - ----------- ---- ---- ----- ------ ---------- F979 F979 6%400 5555 5556 MOV F97C 8A266800 5557 MOY CX. 100 ; SET TIME TO WAIT FOR BIT ; GET PRESENT INPUT VALUE System BIOS A-77 LINE LOC OBJ F9ao SOURCE ; RD-H-BIT 5556 F980 E462 5559 f982: 2410 5560 IN AND Al,OlOH ; MASK OFF EXTRANEOUS BITS F984 3AC4 5561 CNP Al,AH I SAME AS BEFORE? F986 ElFa 5562 LaOPE W22 ; f988 11.26600 5563 MOV LAST_VAl,AL ; UPDATE LAST_VAL WITH NEW VALUE ; INPUT DATA BIT LOOP TILL IT CHANGES F98B BOOO 5564 HOV AL,a ; READ TIMER'S COUNTER COMMAND F980 E643 5565 OUT TIM_CTL,Al ; F98F 881E6700 5566 NOV eX,EDGE_eNT ; BX GETS LAST EDGE COUNT F993 E440 5567 AL. TIHERO AH,AL Al, TINERO ; GET LS BYTE F995 8AEO 5568 IN MOV F997 E440 5569 IN LATCH COUNTER ; SAVE IN AH ; GET MS BYTE f999 86e4 5570 XCHG AL,AH ; XCHG AL,AH F99B 2608 5571 SUB eX,AX ; SET BX EQUAL TO HALF BIT PERIOD f99D A36700 5572 HOV EDGE_CNT ,AX ; UPDATE EDGE COUNT; F9AO C3 RET 5573 5574 READ_HALF _BIT 5575 5576 ; ---------------------------------------------------------------PURPOSE 5577 WRITE 1 OR MORE 256 BYTE BLOCKS TO CASSETTE. 5578 5579 ENDP THE DATA IS PADDED TO FILL OUT THE LAST 256 BYTE BLOCK. ; ON ENTRY: 5580 BX POINTS TO MEMORY BUFFER ADDRESS 5581 CX CONTAINS NUMBER OF BYTES TO WRITE 5582 • ON EXIT: 5583 ex 5584 CX IS ZERO POINTS 1 BYTE PAST LAST BYTE WRITTEN TO CASSETTE 5585 f9Al 5586 PROC F9Al 53 5587 PUSH BX f9A2 51 5588 PUSH CX NEAR F9A3 E461 5589 IN AL,PORT_B F9A5 24FD 5590 AND AL,NOT 02H F9A7 DeDI 5591 OR AL, OlH F9A9 E661 5592 OUT PORT_B,AL f9AB BOB6 5593 HOV AL,OB6H F9AO E643 5594 OUT TIM_CTL,AL F9AF EaMOO 5595 CALL BEGIN_a? ; DISABLE SPEAKER ; ENABLE TIMER ; SET UP TIMER -- MODE 3 SQUARE WAVE ; START MOTOR AND DELAY f9B2 68A004 5596 MOV AX,l184 ; SET NORMAL BIT SIZE F9B5 E88500 5597 CALL 10131 ; SET_TIMER F9B8 690008 5598 MOV CX, 0800H ; SET CX FOR lEADER BYTE COUNT f9BB 5599 F9BB F9 5600 STe F9BC E86800 5601 CALL WRITE_BIT F9BF E2FA 5602 lOOP 10123 10123: ; WRITE LEADER ; WRITE ONE BITS F9Cl fa 5603 eLe F9C2 E86200 5604 CAll F9C5 59 5605 POP ex f9Cb 56 5606 5607 POP HOV BX F9C7 B016 f9C9 E84400 ; LOOP 'TIL lEADER IS WRITTEN ; WRITE SYNC BIT (0) WRITE_BIT AL, ; RESTORE REGS CX ,BX 16H ; WRITE SYN CHARACTER 5608 5609 5610 ; --------- ---------------------------- ------------ ---------- ----; PURPOSE 5611 5612 WRITE 1 OR MORE 256 BYTE BLOCKS TO CASSETTE I ON ENTRY: 5613 BX POINTS TO MEMORY BUFFER ADDRESS 5614 5615 CONTAINS NUMBER OF BYTES TO WRITE ; ON EXIT: 5616 BX POINTS 1 BYTE PAST lAST BYTE WRITTEN TO CASSETTE 5617 CX IS ZERO 5618 ; ------- ----------- ------------ ------------ ---------- ------- ----- f9CC 5619 WR_BLOCK: F9CC C70669DOFFFF 5620 HOV CRC_REG,OFFFFH f9D2 BAOOOI 5621 HOV DX,256 ; FOR 256 BYTES F9D5 5622 F9D5 268M7 5623 MOV AL,ES:[BX] ; READ BYTE FROM HEM F9Q8 E83500 5624 CAll WRITE_BYTE ; WRITE IT TO CASSETTE ; UNLESS CX=O, ADVANCE PTRS & DEC COUNT F90B noz 10124: ; WR-BLK 5625 JCXZ 10125 F9DD 43 5626 INC BX f9DE 49 5627 DEC CX f9Df 5628 F90F 4A 5629 F9EO 7FF5 5630 10125: 5631 5632 5633 ; INC BUFFER POINTER ; DEC BYTE COUNTER ; SKIP-AOV DEC ox ; DEC BLOCK CNT JG "24 ; lOOP TIll 256 BYTE BLOCK ; IS WRITTEN TO TAPE ; - --------------------------------------------------------------; WRITE CRe 5634 A-78 ; INIT CRC System BIOS WRITE l'S COMPLEMENT OF CRC REG TO CASSETTE LOC OBJ LINE SOURCE 5635 5636 5637 f9E2 A16900 WHICH IS CHECKED FOR CORRECTNESS WHEN THE BLOCK IS READ : ; REG AX IS MODIFIED 1------------------------------------------------------_________ _ 5638 MOV AX,CRC_REG NOT AX ; FOR I' 5 COMPLEMENT 5639 F9E5 F700 I WRITE THE ONE'S COMPLEMENT OF THE ; 5640 TWO BYTE CRC TO TAPE f9E7 50 5641 PUSH AX ; SAVE IT f9E6 86EO 5642 XCHG AH,AL ; WRITE MS BYTE FIRST F9EA E82300 5643 CALL WRITE_BYTE I WRITE IT POP AX ; GET IT BACK CALL WRITE_BYTE I NOW WRITE LS BYTE OR ex,cx ; IS BYTE COUNT EXHAUSTED? JNZ WR_BLoeK ; JUMP IF NOT DONE YET PUSH ex HOV ex, 32 F9ED 58 5644 F9EE E8lFOO 5645 F9F 1 OBC9 F9F3 7507 5646 5647 f9F5 51 5648 F9F6 Bnooo 5649 F9F9 5650 F9F9 F9 5651 ; SAVE REG CX ; WRITE OUT TRAILER BITS 10126: ; TRAI L - LOOP STC f9FA E82AOO 5652 CAll WRITE_BIT F9FD EZFA 5653 LOOP 10126 ; WRITE UNTIL TRAILER WRITTEN F9Ff 59 5654 POP CX ; RESTORE REG CX AL, OBOH ; TURN TIHER2 OFF FAOO BOBO 5655 HOV FADZ E643 5656 OUT FA04680100 5657 MOV AX, 1 FAD7 E83300 5658 CAll 10131 FADA EB70FE 5659 CALL MOTOR_OFF FAOD 28CO 5660 SUB AX,AX FAOF C3 SET_TIMER I RET 5661 TURN MOTOR OFF NO ERRORS REPORTED ON WRITE OP FINISHED 5662 ENOP 5663 5664 ; -------------------------------; WRITE A BYTE TO CASSETTE. 5665 ; BYTE TO WRITE IS IN REG AL. 5666 FAID 5667 FAID 51 5668 FAll 50 5669 PUSH AX FAl2 8AE8 5670 MOV CH,AL ; AL=BYTE TO WRITE. HOV CL,8 ; FOR 8 DATA BITS IN BYTE. PROC PUSH NEAR CX I SAVE REGS CX,AX 5671 FAl4 B106 (MS BIT WRITTEN FIRSTi 5672 5673 NOTE: TWO EDGES PER BIT W27: fAl6 5674 FA16 0005 5675 RCl FAIS 9C 5676 PUSHF I CH,I DISASSEMBLE THE DATA BIT I ROTATE HS BIT INTO CARRY ; SAVE FLAGS. NOTE: DATA BIT IS IN CARRY 5677 FA19 E80BOO 5678 F Ale 90 5679 ; WRITE DATA BIT POPf ; RESTORE CARRY FOR CRC CALC FAID E82400 5680 CAll FAZO FEC9 5681 DEC Cl I LOOP TIll All 8 BITS DONE FAZZ 75F2 5682 JNZ 10127 ; JUHP IF NOT DONE YET FA24 58 5683 POP AX ; RESTORE REGS AX,ex FA25 59 5684 POP CX FA26 C3 5685 RET ; WE ARE FINISHED 5686 5687 5688 ; COMPUTE CRC ON DATA BIT CRC_GEN ENOP ; ----------------------------------------- --------------PURPOSE: 5689 TO WRITE A DATA BIT TO CASSETTE 5690 CARRY FLAG CONTAINS DATA BIT 5691 I.E. IF SET DATA BIT IS A ONE 5692 IF CLEAR DATA BIT IS A ZERO 5693 5694 NOTE: TWO EDGES ARE WRITTEN PER BIT 5695 ONE BIT 5696 HAS 500 USEC BETWEEN EDGES FOR A 1000 USEC PERIOD (1 MIlLISEC) 5697 ZERO BIT HAS 250 USEC BETWEEN EDGES 5698 5699 5700 5701 FAZ7 FOR A 500 USEC PERIOD (.5 MIllISEC) ; CARRY flAG IS DATA BIT ; --------- ______________________________________________ _ 5702 PROC NEAR 5703 1 ASSUME IT'S A 'I' FAZ7 B8AO04 5704 HOV FAZA 1203 5705 JC fAze 685002 5706 MOV fA2F 5707 FAZf 50 5708 FA30 5709 FA30 E462 FA32 2420 AX,1l84 ",. AX,592 W28! I SET AX TO NOMINAL ONE SIZE ; JUMP IF ONE BIT ; NO, SET TO NOMINAL ZERO SIZE ; WRITE-BIT-AX PUSH AX 5710 IN Al,PORT_C 5711 AND Al,020H ; WRITE BIT WITH PERIOD EQ TO VALUE AX 10129: INPUT TIHER_ 0 OUTPUT System BIOS A-79 LaC OBJ FA34 74FA FA36 FA36 £462 FA38 242:0 FA3A 7SFA LINE 5712 5713 5714 5715 5716 SOURCE JZ W29 ; LOOP TIll HIGH IH Al.PORT_C I NOW 1oI"'!T TILL TIMER' 5 OUTPUT IS LOW 1<130: AHO AL.020H JHZ W30 POP AX I FOR NEXT DATA BIT ; RESTORE PERIOD COUNT i SET LOW BYTE OF TIMER 2 ; RELOAD TIMER WITH PERIOO 5717 5718 FA3C 58 5719 FA30 5720 10131: j SET TIMER fA3D E642 5721 OUT 042H. AL FA3F 8AC4 5722 MOV AL. AH FA41 E642 5723 FA43 C3 OUT 5724 042H, AL ; SET HIGH BYTE OF TIMER ~ RET 5725 WRITE_BIT EHOP 5726 57<:7 j -------- ---------------------------------------UPDATE CRC REGISTER WITH NEXT DATA BIT 5728 CRC IS USED TO DETECT READ ERRORS 5729 ASSUMES DATA BIT IS IN CARRY 5730 5731 FA44 5732 5733 5734 FA44 U6900 5735 REG AX IS MODIFIED flAGS ARE MODIFIED 1-----------------------------------------------CRC_GEN PROC MOV NEAR AX ,CRC_REG ; THE FOLLOWING INSTUCTIONS 5736 5737 ; WILL SET THE OVERFLOW FLAG 5738 ; IF CARRY AND MS BIT OF CRC 5739 ; ARE UNEQUAL AX,! FAit7 DIDS 5740 FA49 DIDO 5741 R'R Rn FA4S Fa 574~ ele FA4C 7104 5743 JNO W3Z AX,GaIOH AX,l ; CLEAR CARRY ; SKIP IF NO OVERFLOW 5744 ; IF DATA BIT XORED WITH ; 5745 FA4E 351008 5746 XOR FAS1 F9 5747 STe FA52 5748 FA52 DIDO 5749 CRe REG BIT 15 IS ONE i THEN XOR CRC REG WITH 08GIH ; SET CARRY W32: Rel AX,I FA54 ...36900 5751 MOV CRC_REG,AX ; ROTATE CARRY (DATA BIll FA57 C3 5752 5753 RET 5750 ; INTO CRC REG CRC_GEN ; UPDATE CRC_REG j FINISHED EHOP 5754 fAsa 5755 FAsa E826FE 5756 CALL FAS8 8342 5757 MOV BEGIN_OP PROC HEAR jDElAY FOR TAPE DRIVE iTO GET UP TO SPEED 5758 fASD 5759 FASO 890007 5760 MOV CX,700H lOOP W,. FA62 FEte 5762 DEC Bl 5763 JHZ W33 FA66 C3 5764 5761 5765 (112 SEC) 10133: FA64 7SF7 FAbO E2FE I START TAPE ANO DElAY ; TURN ON MOTOR MOTOR_ON BL,42H 10134: ; INNER LOOP= APPROX. 10 HIlLISEC RET BEGIN_OP ENDP 5766 fA67 20323031 5767 El DB ' 201',13,10 fA68 00 FA6C OA 5768 5769 5770 FA6E FA6E 5771 5772 5773 j----------------------------------------------------------------------CHARACTER GENERATOR GRAPHICS FOR 320X200 AND 640X200 GRAPHICS j----------------------------------------------------------------------ORG CRT_CHAR_GEH OFA6EH LABEL BYTE 5774 5775 DB OOOH.OOOH.GOOH,OOOH,OOOH,OOOH,OOOH,OOOH I o_00 DB 07EH,081H,OA5H,081H,OBDH,099H,081H,07EH ; 0_01 FA86 6CFEFEFE7C361000 5776 5771 DB DB 07EH,OFFH,OOBH,OFFH,OC3H,OE7H.OFFH.07EH ; 0_02 06CH,OFEH,OFEH,OFEH,07CH.038H.OIOH.OOOH ; 0_03 fASE l0387CFE7C381000 5778 DB OlOH.036H.07CH.OFEH,07CH,036H,OI0H.OOOH I o_04 FA96 387C38FEFE7C387C 5779 DB 036H.07CH.036H,OFEH,OFEH,07CH,036H.07CH I o_05 FA9E lOl0387CFE7C387C 5780 DB OlOH.OIOH,036H.07CH,OFEH,07CH.036H,07CH I o_06 5781 fA6E 0000000000000000 FA76 7E81A581BD99817E FA7E 7EFFOBFFC3E7FF7E DB OOOH,OOOH,018H,03CH,03CH.018H,OOOH,OOOH ; 0_o7 FAAE FFFFE7C3C3E7FFFF 5782 DB OFFH.OFFH,OE7H.OC3H.OC3H,OE7H.OFFH.OFFH ; 0_08 FAB6 003C664242663COO 5783 DB 000H,03CH,066H,04ZH,04ZH,066H,03CH.OOOH ; 0_09 fAA6 0000183C3C180000 fASE FFC399BDBD99C3FF 5784 DB OFFH.OC3H,099H,OBDH,OBDH,099H,OC3H,OFFH FAC6 OF070F7DCCCCCC78 5785 DB OOFH,007H.OOFH.07DH.OCCH.OCCH.OCCH.078H I 0_08 fACE 3(.b666663C187E1a 5786 DB 03CH.066H.066H,066H.03CH,018H,07£H,OI8H I D_OC A-80 System BIOS j O_OA LOC OBJ LINE SOURCE FADb 3F333F303070FOEO 5787 DB 03FH,033H.03FH.030H.030H,070H.OFOH.OEOH I O_OD FADE 7F637f636367E6CO 5788 DB 07FH.Ob3H,07FH.063H,063H.067H,OE6H.OCOH ; D_OE FAE6 995A3CE7E73C5A99 5789 DB FAEE 80EOF8FEF8E08000 5790 DB 080H.OEOH,OF8H.OFEH.OF8H.OEOH.080H,OOOH ; 0_10 FAF6 020E3EFEJEOE0200 5791 DB 002H.00EH,03EH.OFEH,03EH,OOEH,002H,OOOH ; 0_11 FAFE 183C7E18187E3C18 5792 DB 018H,03CH,07EH,018H,OlBH,07EH,03CH,018H ; 0_12 FBD6 6666666666006600 099H.05AH.03CH.OE7H.0E7H.03CH.05AH.099H ; O_OF 5793 DB 066H.066H.066H.066H,066H,OOOH,066H.OOOH ; 0_13 FeDE 7FDBDB7BIBIBIBOO 5794 DB 07FH.ODBH.ODBH.07BH,OlBH.OIBH.OIBH.OOOH ; 0_14 FBlb 3E63386C6C38CC78 5795 DB 03EH,063H,038H,ObCH,06CH,038H,OCCH,078H ; 0_15 fBtE 000000007E7E7EDO 5796 DB 000H,OOOH,OOOH.OOOH,07EH.07EH,07EH,OOOH ; 0_16 FB26 183C7E187E3C18Ff 5797 DB 018H,03CH,07EH.018;i.07EH,03cH,OI8H,OFFH ; 0_17 FB2E 183C7E1818181800 5798 DB 018H.03CH,07EH.OIBH,018H.018H.OIBH.OOOH ; O_IB FB36 181818187E3C1800 5799 DB 018H.018H.018H,018H,07EH,03CH,018H,OOOH ; 0_19 FB3E 00180CFEOC180000 5800 DB 000H.018H.00CH.OFEH.00CH.018H,OOOH,OOOH ; O_lA FB46 003060FE6030000D 5801 DB OOOH,030H.060H,OFEH,060H.030H,ODOH.OOOH J O_IB FB4E QOOOCQCOCOFEOOOO 5802 DB OOOH.OOOH,OCOH.OCOH,OCOH,OFEH,OOOH,OOOH I D_IC fB56 Q02466FF66Z40000 5803 DB 000H.024H.066H.OFFH.06bH,02:4H,OOOH,OOOH ; 0_10 FBSE 00183C7EFFFFOOOQ 5804 DB 000H.018H,03CH,07EH,OFFH.OFFH.OOOH.000H ; O_IE FB66 QOFFFF7E3ClBOOOO 5805 DB OOOH.OFFH.OFFH.07EH.03CH,OI8H,000H,OOOH ; D_IF FB6E 0000000000000000 5806 DB OOOH,OOOH.OOOH,OOOH.OOOH.OOOH,OOOH,OOOH ; SP 0_20 FB76 3078783030003000 5807 DB fB7E 6C6C6COOOOOOOOOO 5808 DB 06CH.06CH,06CH.000H.OOOH.000H,OOOH.OOOH ; " 0_22: FB86 6C6CfE6CFE6C6COD 5809 DB 06CH,06CH.OFEH,06CH.OFEH,06CH.06CH.OOOH I 10_23 F88E 307CC0780CF83000 5810 DB 030H,07CH.OCOH.078H.00CH.OF8H,030H.000H ; $; 0_2:4 FB96 OOC6CC183066C600 5811 DB OOOH,OC6H,OCCH,018H.030H,066H,OC6H.OOOH ; PER CENT D_2:5 FB9E 386C38760CCC7600 5812 DB 038H.06tH,038H.076H.00CH,OCCH.076H.000H ; & 0_2:6 030H,078H.07BH.030H,030H.OOOH,030H.OOOH ; ! 0_2:1 FBA6 6060COOOOOOOOOOO 5813 DB FBAE 1830606060301800 5814 DB 018H,030H,060H,060H,060H,030H.018H,OOOH ; ( 0_28 FBB6 6030181818306000 5815 DB Q60H.030H,018H.018H.018H.030H,060H,OOOH I J 0_29 FBBE 00663CFF3C660000 5816 DB OOOH,066H,03CH,OFFH,03CH.066H.OOOH,OOOH ; * FBe6 003030FC30300000 5817 DB OOOH ,030H, 030H, OFCH .030H,030H, OOOH, OOOH ; + 0_2B FBCE 0000000000303060 5818 DB OOOH. OOOH. OOOH ,OOOH ,OOOH. 030H. 030H. 060H ; FBD6 OOOOOOFCOOOOOOOO 060H,060H.OCOH.000H.OOOH,OOOH,OOOH,000H • 0_27 0_2A , D_2C 5819 DB OOOH,OOOH,OOOH,OFCH,OOOH.OOOH,OOOH,OOOH ; - 0_20 FBDE 0000000000303000 5820 DB OOOH ,OOOH. OOOH ,OOOH ,OOOH ,030H. 030H, OOOH ; FBE6 060C1830bOC08000 5821 DB 006H.00CH.018H.030H.060H.OCOH,080H.OOOH I /O_2:F FBEE 7CC6CEDEF6E67COO 5822 DB 07CH.OC6H,OCEH,00EH,OFbH,OE6H,07CH.OOOH ; 0 D_30 FBF6 307030303030FCOO • 0_2E 030H,070H,030H,030H,030H,030H,OFCH,OOOH ; 1 0_31 5823 DB FBFE 78CCOC3860CCFCOO 5824 DB 078H.OCCH,OOCH.038H.060H,OCCH,OFCH,OOOH ; 2: 0_32: FC06 78CCOC380CCC7800 5825 DB 078H,OCCH.OOCH,038H,OOCH,OCCH,078H,000H ; 3 0_33 FCOE lC3C6CCCFEOClEOO 5826 DB OlCH.03CH.06CH,OCCH,OFEH,OOCH.OIEH,OOOH ; 4 D_34 FCIb FCCOF80COCCC7800 5827 DB OFCH,OCOH,OF8H.00CH.00CH.OCCH.07BH,OOOH ; 5 0_35 FCtE 38MCOF8CCCC7800 5828 DB 038H.060H.OCOH.OF8H.OCCH,OCCH,078H,OOOH ; 6 0_36 FC26 FCCCOC1830303000 5829 DB OFCH,OCCH.00CH,OIBH,030H.030H.030H.OOOH ; 70_37 078H.OCCH.OCCH,078H.OCCH.OCCH.078H,OOOH ; 8 0_38 FC2E 78CCCC78CCCC7800 5830 DB FC3b 78CCCC7COC187000 5831 DB 078H,OCCH,OCCH,07CH.00CH.018H,070H,OOOH ; 9 0_39 fC3E 0030300000303000 5832 DB 000H,030H,030H,OOOH.OOOH,030H.030H.OOOH ; : 0_3A FC46 0030300000303060 5833 DB 000H.030H.030H.OOOH.OOOH,030H,030H,060H ; I FC4E 183060C060301800 5834 DB 018H,030H,060H,OCOH,OMH,030H.OIBH,OOOH ; < 0_3C FC5b OOOOFCOOOOFCOOOO 5835 DB OOOH, OOOH. OFCH .OOOH .OOOH ,OFCH,OOOH ,OOOH ; FC5E 6030180C18306000 5836 DB 060H.030H.018H.OOCH,018H.030H,060H,OOOH ; > 0_3E FC66 78CCOC1830003000 5837 DB 078H.OCCH.00CH,018H.030H,OOOH,030H,OOOH ; ? 0_3F 0_3B = 0_30 FCbE 7CC6DEDEOEC07800 5838 DB 07CH.OC6H,ODEH,ODEH.ODEH,OCOH.078H.000H ; ill 0_40 Ft76 3078CCtCFCCCCtOO 5839 DB 030H,078H,OCCH,OCCH.OFCH.OCCH.OCCH,OOOH ; A 0_41 FC7E FC66667C6666FCOO 5840 DB OFCH.066H,066H,07CH,06bH,Ob6H.OFCH,OOOH ; B D_42 FC86 3C66COCOC0663COO 5841 DB 03CH.066H,OCOH.OCOH,OCOH.066H.03CH.000H I C 0_43 FceE F86C66b6666CF800 5842 DB OF8H.06CH.066H.066H.066H.06CH.Of8H,ODOH ; D 0_44 FC9b FE6268786862FEOO 5843 DB OFEH.062H.068H,078H,068H,062:H,OFEH,OOOH I E 0_45 FC9E FE6268786860FOOO 5844 DB OFEH,062H.068H,078H,06BH.ObOH.OFOH.OOOH ; F 0_46 fCA6 3C66COCOCE663EOO 5845 DB 03CH.066H.OCOH.OCOH.OCEH,066H,03EH,OOOH ; G D_47 fCAE CCCCCCFCCCCCCCOO 5846 DB OCCH.OCCH.OCCH.OFCH.OCCH,OCCH,OCCH,OOOH ; H 0_48 FCB6 7830303030307800 5847 DB 078H.030H,030H,030H,030H,030H,078H.OOOH ; 10_49 fCBE t EOCOCOCCCCC7800 5848 DB FCC6 E6666C786C66E600 5849 DB OE6H,066H,06CH,07BH.ObCH.066H.OE6H.OOOH ; K 0_46 FCCE F060606062b6FEOO 5850 DB OFOH.060H,060H.060H,06ZH,066H,OFEH,OOOH ; L D_4C FC06 c6EEfEFED6C6CbOO 5851 DB OC6H,OEEH,OFEH,OFEH,006H.OC6H.OC6H.ODOH I M 0_40 OlEH,OOCH,OOCH.OOCH.OCCH,OCCtl,078H.000H ; J 0_4. FCDE C6E6F6DECECbC600 5852 DB OC6H,OE6H,OFbH.00EH.OCEH,OC6H,OC6H.OOOH ; N 0_4E FCE6 386CC6C6C66C3800 5a53 DB 038H,06CH,OC6H,OC6H.OC6H,06CH,038H,OOOH ; OO_4F FCEE fC66667C6060FOOO 5854 DB OFCH,066H,06bH,07CH,060H.060H.OFOH.000H ; P D_50 FCF6 78CCCCCCOC781COO 5855 DB 078H,OCCH,OCCH,OtCH,ODCH.078H,OlCH.OOOH J Q 0_51 FCFE FC66667C6C66E600 5856 DB OFCH,066H,066H,07CH,06CH.066H.OE6H,OOCH r R 0_52 FD06 78CCE0701CCC7800 5857 DB 078H.OCCH,OEOH.070H.OICH,OCCH,078H,OOOH ; SO_53 FDOE FCB4303030307800 5858 DB OFCH,OB4H,030H,030H,030H,030H,07BH.OOOH ; T D_54 FD16 cccccccccctCFCOO 5859 DB OCCH.OCCH.OCCH,OCCH.OCCH,OCCH,OFCH.OOOH ; U 0_55 FOI E CCCCCCCCCC783000 5860 DB OCCH.OCCH,OtCH,OCCH,OCCH.078H,030H.OOOH ; V 0_56 FD2b C6C6C606FEEECbOO 5861 DB OC6H.OC6H,OC6H,006H.OFEH,OEEH,OC6H,OOOH ; W D_57 F02E C6C66C38386CC600 5862 DB OC6H,OC6H,06CH,03BH,03BH.ObCH.OC6H,OOOH ; X 0_5B F036 CCCCCC7830307800 5663 DB OCCH.OCCH,OCCH,078H,030H,Q1.0H,078H,OOOH 1 Y D_sq System BIOS A-81 LOC OBJ LINE SOURCE FD3E FECb8C1832bbFEOO 5864 DB FD46 7860606060607800 5865 DB 078H.060H.060H.P60H.060H.060H.078H.OOOH ; [ 0_5B FD4E C06030180C060200 5866 DB OCOH,060H,030H,016H,OOCH,006H,002H,oOOH • BACKSLASH O_SC OFEH.OC6H.08tH.018H,Ol2H,066H,OFEH.000H • Z 0_5A FD56 7818181818187800 5867 DB 07BH,OI8H,018H.018H.018H,OlBH,078H.OOOH ; FD5E 10386CC600000000 5868 DB 010H,038H,06CH,OC6H,OOOH.000H.OOOH,OOOH I CIRt\.n1FI-EX 0_5E F066 OOOOOOOOOOQOOOfF 5869 DB OOOH, OOOH, OOOH ,OOOH .OOOH ,OOOH. OOOH .OFFH I _ 0_5F FD6E 3030180000000000 5870 DB OlOH,030H,018H,OOCH,OOOH,000H.OOOH.OOOH ; F076 0000780C7CCC7600 5871 DB OOOH.OOOH.078H,OOCH,07CH,OCCH,076H.000H ; LOWER CASE A o_61 F07E E060607C66660COO 5872 DB OEOH.060H.060H.07CH.066H,066H.ODCH,OOOH ; L.C. B D_62 FDe6 000078CCCOCC7800 5873 DB OOOH.000H.078H,OCCH,OCOH,OCCH,078H.000H ; L.t. C o_63 FU8E lCOCOC7CCCCC760Q 5874 DB 01tH,oOCH.00CH,07CH,OCtH,OCCH.076H.OOOH ; L.C. D 0_64 FD96 000078CCFCC07800 5875 DB OOOH.000H.078H.OCCH,OFCH.OCOH,078H.000H FDI:ilE 386C60F06060FOOO 5876 DB 038H.06CH,060H.OFOH.060H,060H.OFOH.000H ; L.C. F D_66 FUM 000076CCCC7COCF6 5877 DB OOOH.OOOH.076H,OttH,OCCH,07CH,OOCH.OF8H J L.C. G o_67 FDAE E0606C766666E600 5878 DB OEOH,060H,06CH.076H.066H.066H.OE6H.OOOH ; L.C. H 0_68 FDB6 3000703030307800 5879 DB 030H,OOOH,070H,030H,030H,030H,078H,OOOH ; L.C. I o_69 FUBE OCOOOCOCOCCCCC78 5880 DB OOCH,OOOH,OOCH,OOCH,OOtH,OCCH,OCCH,078H Foe6 E060666C786CE600 5881 DB OEOH.060H.066H,06CH.078H,06CH,OE6H,OOOH I l.C. K 0_6B FDCE 7030303030307800 5882 DB 070H,030H,030H,030H.030H.030H,078H,OOOH L.t. l D_6C FOD6 OOOOCCFEFED6CbOO j ] o_50 , D_60 L.C. E o_65 L.C. J 0_6A DB OOOH,OOOH,OCCH,OFEH,OFEH,OD6H,OC6H,OOOH L.C. M o_60 FDDE OOOOF8CCCCCCCCOO 5884 DB 000H,OOOH,OF8H,OCCH.OCCH.OCCH,OCCH,OOOH L.C. N 0_6E FDE6 000078CCCCCC7800 5885 DB 000H.000H,078H,OCCH.OCCH,OCCH,078H,OOOH • L.C. FDEE 00000C66667C60FO 5886 DB 000H,OOOH,ODCH.066H,066H,07CH,060H,OFOH I L.C. P o_70 FDFb 000076CCCC7COCIE 5887 DB 000H,OOOH,076H,OCCH,OCCH,07CH.OOCH,OlEH L.C. Q 0_71 FOFE OOOOOC766660FOOO 000H,OOOH,ODCH.076H.066H,060H.OFOH,OOOH L.C. R 0_72 5883 a O_~F 5888 DB FEat:. 00007CC0780CF800 5889 DB 000H.000H.07CH,OCOH,078H,OOCH.OF8H,OOOH ; L.C. S 0_73 HOE 10307C3030341800 5890 DB OIOH,030H,07CH,030H,030H,034H,018H,000H ; L.C. T FE 16 OOOOCCCCCCCC7600 000H,OOOH,OCCH,OCCH,OCCH.OCCH,076H,OOOH • L.C. U o_75 5891 DB FEIE 0000CCCCCC783000 o_74 5892 DB 000H,OOOH,OCCH,OCCH,OCCH,078H,030H,OOOH ; L.C. V 0_76 FE26 OOOOC6D6FEFE6COO 5893 DB 000H.OOOH,OC6H,006H,OFEH,OFEH,06CH,OOOH FEZE OOOOC66C386CC600 5894 DB OOOH,OOOH,OC6H,06CH,03SH,06CH.OC6H,OOOH FE36 0000CCCCCC7COCF8 5895 DB 000H,OOOH,OCCH,OCCH,OCCH,07CH,OOCH,OF8H L.C. Y 0_79 FEJE 0000FC983064FCOO 5896 DB 000H.OOOH,OFCH,098H.030H,064H,OFCH,OOOH L.C. Z 0_7A FE46 lC3030E030301COO 5897 DB 0ICH,030H,0'30H,OEOH,030H,030H,OICH,000H {0_7B FE4E 1818180018181800 5898 DB 018H,OI8H,018H,OOOH,OI8H,018H,018H,OOOH I FE56 E030301C3030EOOO 5899 DB OEOH.030H,030H,OlCH,030H,030H,OEOH,OOOH } 0_70 FE5E 76DCOOOOOOOOOOOO 5900 DB 076H,OOCH,OOOH.OOOH,OOOH,OOOH,OOOH,OOOH ; TILDE D_7E FE66 0010386CC6C6FEOO 5901 DB 000H,010H,038H,06CH,OC6H,OC6H,OFEH,OOOH I DELTA D_7F L.C. W 0_77 L.C. X ° 78 D_7C 5902 5903 5904 ; --- INT lA --------------------------------------------; TIME_OF _DAY 5905 ; THIS ROUTINE AllOWS THE CLOCK TO BE SET/READ 5906 5907 ; INPUT 5908 (AH) = 0 REAO THE ClJ);!RENT ClOCK SETTING 5909 RETlJ);!NS CX 5910 OX 5911 AL 5912 (AHI 5915 LOW PORTION OF COUNT 0 IF TIMER HAS NOT PASSED 5916 <>0 IF ON ANOTHER OAY SET THE ClJ);!RENT CLOCK =1 CX OX = = HIGH PORTION OF COUNT lOW PORTION OF COUNT ; NOTE: COUNTS OCCUR AT THE RATE OF 5918 5919 5920 HIGH PORTION OF COUNT 24 HOURS SINCE LAST READ 5913 5914 5917 = = = 1193180/65536 COUNTS/SEC (OR ABOUT 18.2 PER SEcmm -- SEE EQUATES BELOl.oII ; ---------- _____________________________________________ _ 5921 ASSUME CS :CODE ,DS:OATA FE6E 5922 ORG FE6E 592:3 TIME_OF _DAY FE6E FB 592:4 ST! FE6F IE 5925 PUSH OS FE70 E8CBOO 5926 CALL DDS FE73 OAE4 5927 DR AH,AH ; AH=O OFE6EH PROt FAR ; INTERRUPTS BACK ON ; SAVE SEGMENT FE75 7407 5928 JZ T2 ; REAO_TIME FE77 FECC 5929 DEC A" ; AH=l FE79 7416 5930 JZ T3 FE7S 5931 FE7B FB 5932 ST! FE7C IF 5933 POP TI: ; TOO_RETURN OS FE70 CF 5934 FE7E 5935 FE7E FA 5936 FE7F A07000 5937 MOV AL, TIMER_On FE82 C606700000 5938 MOV TIMER_OFL.O FE87 880E6EOO 5939 MOV CX, TIMER_HIGH FE8B 88166COO 5940 MOV ox, TIMER_lOW A-82 IRET ; RECOVER SEGMENT ; RETURN TO CALLER T2: System BIOS ; SET_TIME ; INTERRUPTS BACK ON ; READ_TIME CLl ; NO TIMER INTERRUPTS WHILE READING • GET OVERFLOW. Am RESET THE FLAG LOC OBJ LINE SOURCE JMP FE8F EBEA 5941 FE91 5942 FE91 FA 5943 ClI FE92 89166COO 5944 MeV ; TOO_RETURN T1 T3: • SET_TIME ; NO INTERRUPTS WHILE WRITING TIMER_LOW.OX ; SeT THE TIME FE96 690E6EOO 5945 MeV TIMER_HIGH.ex FE9A C606700000 5946 MOV TIMER_OFLtO J RESET OVERFLOW FE9F EBDA 5947 JMP T1 ; TOO_RETURN 5948 TIME_OF _DAY ENDP 5949 5950 ; --- -- - - - - --------------- -- -- ----- -------- ----- -- -------- 5951 I THIS ROUTINE HANDLES THE TIMER INTERRUPT FROM 5952 CHANNEl 0 OF THE 82:53 TIMER. INPUT FREQUENCY 5953 IS 1.19316 MHZ AND THE DIVISOR IS 65536. RESULTING 5954 IN APPROX. 18.2 INTERRUPTS EVERY SECOND. 5955 5956 ; 11iE INTERRUPT HANDLER MAINTAINS A COUNT OF INTERRUPTS: 5957 I SINCE POWER ON TIME. WHICH MAY BE USED TO ESTABLISH 5958 • TINE OF DAY. 5959 I THE INTERRUPT HANDLER ALSO DECREMENTS THE MOTOR CONTROL COUNT OF THE DISKETTE, AND WHEN IT EXPIRES, 5960 5961 ; WILL TURN OFF THE DISKETTE MOTOR, AND RESET THE 5962 ; MOTOR RUNNING flAGS. 5963 ; THE INTERRUPT HANDLER WILL ALSO INVOKE A USER ROUTINE 5964 THROUGH INTERRUPT lCH AT EVERY TIME TICK. 11iE USER 5965 ; MUST CODE A ROUTINE AND PLACE THE CORRECT ADDRESS IN : 5966 ; THE VECTOR TABLE. 5967 ; -------------------------------------------------------- FEAS 5966 FEAS 5969 FEAS FB 5970 STI ORG FEA6 IE 5971 PUSH FEA7 50 5972 PUSH TIMER_INT OFEASH PROC FAR INTERRUPTS BACK ON OS AX HAB 52 5973 PUSH OX FEA9 E89200 5974 CALL DDS FEAC FF066COO 5975 INC TIMER_lOW FEBO 7504 5976 JHZ T4 FEBl FF066EOO 5977 INC TIMER_HIGH j ; SAVE MACHINE STATE INCREMENT TIME INCREMENT HIGH WORD OF TIME T4: FEB6 5978 FEBb 833E6EOOI8 5979 CMP TIMER_HIGH, 0 18H ; FEBB 7515 5980 JHZ T5 I DISKETTE_CTl FEBD 813E6C008000 5981 CMP TINER_LOW,OBOH FEC3 750D 5982 JHZ T5 TEST FOR COUNT EQUALING 2:4 HOI.JRS 5983 5984 ;------ TIMER HAS GONE 24 HOURS 5985 SUB AX,AX FEe7 A36EOO 5987 MaV TIMER_HIGH ,AX FEeA A36eoo 5988 MOV TIMER_LOW,AX FEtD C606700001 5989 MOV TIMER_OFL,l FEes 2:6CO 5986 5990 5991 ; ------ TEST FOR DISKETTE TIME OUT 5992 FED:?: 5993 T5: FED:?: FEOE4000 5994 DEC FE06 7508 5995 JHZ T6 I RETURN IF COUNT NOT OUT FED8 8D:?:63FOOFO 5996 AND MOTOR_COUNT MOTOR_STATUS,OFOH I TURN OFF MOTOR RUNNING BITS FEOO BCOC 5997 MOV AL,OCH FEDF BAF2:03 5998 MOV DX.03F2H FEE2 EE 5999 OUT DX,AL T6: FEE3 6000 FEE3 C01C 6001 IHT lCH FEES BI)2:0 6002: MOV AL,EOI FEE7 E620 6003 OLT 020H.AL FEE9 SA 6004 POP OX FEEA 58 6005 POP AX FEEB IF 6006 POP OS FEEC CF 6007 IRET 6008 FOC CTl PORT I TURN OFF THE MOTOR I TIMER_RET: I TRANSFER CONTROL TO A USER ROUTINE ; END OF INTERRUPT TO 82:59 ; RESET MACHINE STATE ; RETURN FROM INTERRUPT TIMER_INT ENDP F3B '1801',13,10 6009 FEED 31383031 6010 DB FEF1 00 FEF2 OA 6011 6012 6013 ; ---------------------------------------------------------------THESE ARE THE VECTORS WHICH ARE MOVED INTO 6014 THE 8086 INTERRUPT AREA DURING POWER ON. 6015 ONLY THE OFFSETS ARE DISPLAYED HERE. CODE SEGMENT System BIOS A-83 LINE LOC OBJ 6016 6017 SOURCE WIll BE ADDED FOR All OF THEM. EXCEPT WHERE NOTED 1------·--------------------------------------------------------ASSUME 6018 ORG CS:CODE FEF3 6019 FEF3 6020 FEf3 ASFE 6021 OW OFFSET TIMER_tNT OFFSET VECTOR_TABLE fEFS 87E9 6022 FEf7 00E6 6023 OW OW FEF9 00E6 6024 FEFB DDE6 6025 FEFO DOH 6026 FEFF 57EF OFEF3H LABEL WORD KB_nrr ; VECTOR TABLE FOR HOVE TO INTERRUPTS INTERRUPT 6 I INTERRUPT 9 OFfSET D_EOI ; INTERRUPT A OW OffSET D_EOl ; INTERRUPT B OW OFFSET D_EOl ; INTERRUPT C OW OFFSET D_EOI i 6027 OW OffSET DISK_INT ; INTERRUPT E FfOI 00E6 INTERRUPT D 6028 OW OFFSET D_EOI ; INTERRUPT F fFO} 65FD 6029 OW OFFSET VIDEO_IO ; INTERRUPT 10H FF05 4DF8 6030 OFFSET EQUIPMENT INTERRUPT I1H FF07 41F6 6031 OW OW OFFSET MEMORY_SIZE_OET INTERRUPT 12H FF09 59EC 6032: OW OFFSET OISKETTE_IO FFOB 39E7 6033 OW OFFSET RS232_IO INTERRUPT 14H HOD 59F8 6034 OW OffSET CASSETTE_IO INTERRUPT ISH HOF 2EE8 6035 OW OFFSET KEYBOARD_IO INTERRUPT 16H FF 11 C2EF 6036 INTERRUPT 13H 'W OFFSET PRINTER_IO INTERRUPT 17H 6038 OW OOOOOH INTERRUPT ISH 6039 OW OF600H OW OFFSET BOOT_STRAP INTERRUPT 19H 6037 FFl3 0000 MUST BE INSERTED INTO TABLE LATER 6040 FFIS FlE6 6041 FFI76EFE 6042: OW TIME_OF _DAY INTERRUPT IAH -- TIME OF DAY FF19 53FF 6043 ~UMMY_RETURN INTERRUPT ISH -- KEYBOARD BREAK AOOR FFIB 53FF FflO A4FO 6044 'W OW DUNMY_RETURN INTERRUPT lC -- TIMER BREAK ADDR 6045 OW VIDEO_PARMS INTERRUPT 10 -- VIDEO PARAMETERS FFIF C7EF 6046 OW OFFSET DISK_BASE INTERRUPT IE -- DISK PARMS FfZl OO~O INTERRUPT IF -- POINTER TO VIDEO EXT OW 6047 6048 FF23 504152:49545920 6049 02 OB 'PARITY CHECK I ' ,13,10 6050 F1 OB , 301',13,10 OB '131' ,13,10 43484543482031 FF31 00 FF32 0.6. FF33 20333031 FF37 00 FF38 OA FF39 313331 6051 FF3C 00 FF3D OA 6052 FF3E 6053 PROC NEAR FF3E 50 6054 PUSH AX FF3F B84000 6055 MOV AX.DATA FF42 8E08 6056 MOV OS,AX ; SET DATA SEGMENT FF44 58 6057 POP AX ; RESTORE AX FF45 C3 6058 RET 6059 6060 6061 OOS DOS ENOP 1-------------------------------------------------------- 6062 6063 ; SAVE AX TEMPORARY INTERRUPT SERVICE ROUTINE ; -------------------------------------------------------- ORG OFf47H PROt NEAR MOV AH,I FF47 6064 FF47 fF47 8401 FF49 50 6065 6067 PUSH AX , SAVE REG AX CONTENTS FF4A BOFF 6068 MOV AL,OFfH I MASK ALL INTERRUPTS Off FF4C E621 6069 OUT INTAOl,AL FF4E B020 6070 MOV AL,EO! FFSO E620 6071 OUT INTAOO,AL FFS2 58 6072 POP AX FFS3 6073 FFS3 CF 6074 011 6066 6075 DUMMY_RETURN: ; RESTORE REG AX CONTENTS ; NEED IRET FOR VECTOR TA.BLE IRET 011 ENDP 6076 6077 ;-- INT 5 --------------------------------------------------------------- 6078 THIS LOGIC WILL BE INVOKED BY INTERRUPT 05H TO PRINT THE 6079 SCREEN. THE CURSOR POSITION AT THE TIME THIS ROUTINE IS INVOKED 6080 WILL BE SAVED AND RESTORED UPON COMPLETION. THE ROUTINE IS 6081 'PRINT SCREEN' KEY IS DEPRESSED DURING THE TIME THIS ROUTINE 6083 IS PRINTING IT WILL BE IGNORED. 6084 ADDRESS 50:0 CONTAINS THE STATUS OF THE PRINT SCREEN: 6085 A-84 INTENDED TO RUN WITH INTERRUPTS ENABLED. IF A SUBSEQUENT 6082 System BIOS LOC OBJ LINE SOURCE 50:0 6086 =0 6087 6088 A SUCCESSFUL OPERATION. 6089 =1 PRINT SCREEN IS IN PROGRESS 6090 =2:55 ERROR ENCOUNTERED DURING PRINTING 6091 ;-----------------------------------------------------------------------ASSUME es:eOOE.OS:XXOATA FF54 60n 6093 FF54 6094 FF54 FB 6095 STI FFS5 IE 609b PUSH OS FF5b 50 6097 PUSH AX FFS7 53 6098 PUSH BX FF58 51 6099 6100 6101 6102: FF59 52 FF5A 885000 FF5D 8E08 EITHER PRINT SCREEN HAS NOT BEEN CALLED OR UPON RETURN FROM A CALL THIS INDICATES ORG PRINT_SCREEN OFF54H PRoe FAR ; MUST RUN WITH INTERRUPTS ENABLED ; MUST USE 50:0 FOR DATA AREA STORAGE I WILL USE THIS LATER FOR CURSOR LIMITS PUSH CX PUSH OX ; WILL HOLD Ct..IRRENT Ct..IRSOR POSITION MOV AX .XXDATA I HEX 50 NOV OS.AX 6103 6104 CMP STATUS_BYTE. 1 JZ EXIT FF6b e006000001 6105 MOV STATUS_BYTE, 1 ; INDICATE PRINT NOW IN PROGRESS FF6B B40F 6l0b MOV AH.15 ; WILL REQUEST THE CURRENT SCREEN MODE FF6D COlO 6107 INT 10H FFSF 803EOOOOOI FF64 745F I SEE IF PRINT ALREADY IN PROGRESS I JUMP IF PRINT ALREADY IN PROGRESS [ALl=t1ODE 6108 [AH1=NlIt1BER COLl.It1NS/LINE 6109 6110 tBHJ=VISUAL PAGE ; ---------------------------------------------------------------- 6111 AT THIS POINT WE KNOW THE COLt.n1NS/LINE ARE IN [AX 1 AND THE PAGE IF APPLICABLE IS IN IBH I. THE STACK 611l 6113 6114 HAS DS,A.X.8X,CX.OX PUSHED. [All HAS VIDEO MODE ; ---------------------------------------------------------------- [ex J FF6F BAce 6115 MOV CL.AH ; WILL MAKE USE OF FF71 8519 6116 6117 MOV CH,l5 ; CONTROL ROW & COLUMNS FF73 E85500 CALL CRlF I CARRIAGE RETURN LINE FEED ROUTINE FF76 51 REGISTER TO 6118 PUSH ex FF77 9403 6119 MOV AH , 3 ; WILL NOW READ THE CURSOR. FF79 COlO 6110 WT 10H I AND PRESERVE THE POSITION ; SAVE SCREEN BOUNDS FF7B 59 6111 POP CX ; RECALL SCREEN BOUNDS FF7C 52 61Zl PUSH OX ; RECALL {BHI=YISUAL PAGE FF7D 3302 61Z3 XOR OX.OX ; WILL SET CURSOR POSITION TO 6 Il4 THE LOOP FROM PRIlO TO THE INSTRUCTION PRIOR TO PRIZO 61Z6 IS THE lOOP TO READ EACH CURSOR POSITION FROM THE 6127 FF7F [o.OJ ; -------- -- ----- - ---- - - - -- ---- ------ ---- - -- - - - - - -- - - ---------- --- 61Z5 SCREEN AND PRINT. 61 Z8 ; ---------------------------------------------------------------- 6129 PRIlO: FF7F 6402: 6130 HOV AH,Z I TO INDICATE CURSOR SET REQUEST FFSt COlO 6131 INT IOH ; NEW CURSOR POSITION ESTABLISHED FFS3 6408 6132 HOV AH.8 FFSS COlO 6133 INT IOH ; CHARACTER NOW IN [ALI FFS7 OACO 6134 OR AL.AL I SEE IF VALID CHAR FF89 7502: 6135 JNZ PRII5 ; JUMP IF YALIO CHAR FF6B B020 6136 HOV AL, • ; MAKE A BlANK FF80 6137 FFao 52 ; TO INDICATE READ CHARACTER FRII5: ; SAYE CURSOR POSITION 6138 PUSH OX FFeE HO, 6139 XOR DX.OX ; INDICATE PRINTER 1 FF90 32E4 6140 XOR AH.AH I TO INDICATE PRINT CHAR IN [ALI FF92 C017 6141 INT 17H ; PRINT THE CHARACTER FF94 SA 6142 POP OX ; RECALL CURSOR POSITION fF95 F6C42:5 6143 TEST AH. Z5H I TEST FOR PRINTER ERROR FF9S 7521 6144 JNZ ERRIO ; JUMP IF ERROR DETECTED FF9A FEtl 6145 INC DL ; ADVANCE TO NEXT COLUMN FF9C 3ACA 6146 CMP CL,OL ; SEE IF AT END OF LINE FF9E 75DF 6147 JNZ PRIlO ; IF NOT PROCEED FFM 3202 HAl 8AE2 6148 XOR DL,DL ; BACK TO COLUMN 0 6149 MaY AH,DL I {AH]=O FFA4 52: 6150 PUSH OX ; SAVE NEW CURSOR POSITION FFAS E82300 6151 CALL CRLF ; LINE FEED CARRIAGE RETURN fFA8 SA ; RECALL CURSOR POSITION HAD 7500 615l 6153 6154 6155 FFAF 6156 FFA9 FEC6 FFAB 3AEE POP OX INC DH ; ADVANCE TO NEXT LINE eHP CH.DH ; FINISHED? JNZ PRIlO ; IF NOT CONTINUE PRIZO: FFAF SA 6157 POP OX ; RECALL CURSOR POSITION FF80 6402 6158 HOV AH.2 I TO INDICATE CURSOR SET REQUEST FFS2: COlO INT IOH I CURSOR POSITION RESTORED FFB4 C606000000 6159 6160 FFB9 EBM 6161 FFBe 6162 HOV STATUS_BYTE ,0 JHP SHORT EXIT INDICATE FINISHED ; EXIT THE ROUTINE ERRI0: System BIOS A-85 LOC OBJ LINE SOURCE FFeB SA 6163 POP OX I GET CURSOR POSITION FFBt 8402 6164 HOV AH,Z I TO REQUEST CURSOR SET FFBE COlO 6165 INT 10H ; CURSOR POSITION RESTOf;!ED FFeD 6166 6167 ERRZO: HOV STATUS_BYTE,OffH I INDICATE ERROR EXIT: OX ; RESTORE ALL THE REGISTERS USED FFC7 58 6166 6169 6170 6171 FFee 58 61n PDP AX FFC9 1 F 6173 POP 05 FFCA CF 6174 IRET 6175 PRINT_SCREEN FFeo C6060000FF FFC5 FFCS 5.1. FFC6 59 POP POP ex PDP BX ENlJP 6176 6177 1------ CARRIAGE RETURN, LINE FEED SUBROUTINE 6178 FFCB 6179 PROt NEAR FFee 3302 6180 XOR OX,OX FFeD 32E4 6181 XOR AH,AH CRLF FFCF BOOA FFOI C017 6183 6184 FFD3 32E4 I PRINTER 0 ; WILL NOW SEND INITIAL IF,CR ; 6182 TO PRINTER HDV AL,12Q ; LF INT 17H ; SEND THE LINE FEED 6185 XOR AH ,AH ; NOW FOR THE CR FFD5 BODO 6186 HOV AL.t5Q ; CR FF07 C017 6187 INT 17H ; SENO THE CARRIAGE RETURN FFD9 C3 6186 6189 RET CRlF ENDP 6191 Dl DB 'PARITY CHECK 2' ,13,10 61n FJ DB '601',13,10 CODE ENlJ5 6190 FFOA 50415249545920 434845434B2032 FFE8 00 FFE<;I OA FFEA 363031 FFEO 00 FFEE OA 6193 6194 6195 6198 -------------------------------POWER ON RESET VECTOR ; ----------- ------------- -- ------ 6199 VECTOR 6196 6197 ; SEGMENT AT OFFFFH 6200 6201 ; ----- POWER ON RESET 6202 0000 EA5BEOQOFO 6203 JHP RESET DB '10/27/82 ' 6204 0005 31302F3Z372F38 6205 32 6206 VECTOR 6207 A-86 System BIOS ENlJ5 END I RELEASE MARKER LOC OBJ LINE SOURCE $TITLEf FIXED DISK BIOS fOR IBH DISK CONl'RDlLER I J-- tHT 13 -----------.------------------------------------------ ; FIXED DISK 110 INTERFACE TillS INTERFACE PROVIDES ACCESS TO 5 1/4" FIXED DISKS THROUGH THE IBH FIXED DISK CONTROLLER. 10 11 1- --- - ---------------- ----- - ---- ----- - ------- - -- -- --- ----- ------- 1Z , ---- - - ------------ -- - ----- ---- - -- - - - -- ------- - - - - --- -- --- --- ---- 13 THE 14 SOFTWARE INTERRUPTS ONLY. BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH ANY ADDRESSES PRESENT IN 15 THE LISTINGS 16 HOT FOR 17 ABSOLUTE 18 VIOLATE THE STRUCTURE AND DESIGN OF BIOS. 19 2. . 21 ARE INCLUDED REFERENCE. ONLY FOR COMPLETENESS. APPLICATIONS WHICH ADDRESSES WITHIN THE REFERENCE CODE SEGMENT 1- -- - - ------------- - - - - -- - - ------- - -- ---------- -- ---------------; INPUT (AH = HEX VALUE) 22 (AHI=OO RESET DISK (DL = 80H.81H) / DISKETTE 24 (AHI=Ol READ TltE STATUS OF THE LAST DISK OPERATION INTO (AU NOTE: DL < 80H - DISKETTE 25 Dl > BOH - DISK 26 (AIO=02: READ THE DESIRED SECTORS INTO MEMORY 27 28 IAHI=03 WRITE THE DESIRED SECTORS fROt1 MEMORY 2. 3. IAH)=05 FORMAT THE DESIRED TRACK UH 1=04 VERIFY THE DESIRED SECTORS I AH 1=06 FORMAT THE DESIRED TRACK AND SET BAD SECTOR FLAGS 31 32 33 34 I AH )=07 FORHAT THE DRIVE STARTING AT THE DESIRED TRACK (AH )=08 RETURN THE C~RENT DRIVE PARAMETERS 3S I AH )=09 INITIALIZE DRIVE PAIR CHARACTERISTICS 36 37 38 I AH )=OA READ LONG 3' NOTE: READ AND WRITE LONG ENCOI1PASS 512 • 4 BYTES ECC INTERRUPT 41 POINTS TO DATA BLOCK (AH)=OB IoRITE LONG 4. (AH )=OC SEEK 41 (AHI=OD ALTERNATE DISK RESET (SEE Dl) 42 43 44 (AH )=OE READ SECTOR BUFFER 46 47 UH 1=11 RECALIBRATE . (AH )=DF WRITE SECTOR BUFFER. IRECO\"I1ENDED PRACTICE BEFORE FORMATTING) IAHI=10 TEST DRIVE READY (AH 1=12 CONTROLLER RAM DIAGNOSTIC (AH )=13 DRIVE DIAGNOSTIC 48 4. 5. (AH )=14 CONTROLLER INTERNAL DIAGNOSTIC 51 52 REGISTERS USED fOR FIXED DISK OPERATIONS 53 (DLI DRIVE HUt1BER (BOH-B7H FOR DISK, VALUE CHECKED) 54 (DH) HEAD NUMBER 10-7 AllOWED. NOT VAlUE CHECKED) 55 IC!"!J CYlINDER HUMBER (0-1023. NOT VALUE CHECKEDHSEE ell 56 tcU SECTOR tM1BER (1-17, HOT VALUE CHECKED) - 57 58 NOTE: HIGH 2: BITS OF CYLINDER NUt1BER ARE PLACED 5'6. IN THE HIGH 2 BITS OF THE CL REGISTER 110 BITS TOTAL) 61 62 (ALI - FOR READ/WRITE LONG 1-79tO 63 (INTERLEAVE VALUE FOR FORHAT 1-1601 64 (ES:BXI - 65 ADDRESS OF BUFFER FOR READS AND WRITES, (NOT REQUIRED FOR VERIFY) 66 J 67 I OUTPUT 65 NU1BER OF SECTORS (MAXlMUt1 POSSIBLE RANGE 1-80H. AH = STATUS OF CURRENT OPERATION 69 STATUS BITS ARE DEfINED IN THE EQUATES BELOW 70 CY = 0 SUCCESSFUL OPERATION (AH=O ON RETURN) 71 CY = 1 FAILED OPERATION (AH HAS ERROR REASON) NOTE: ERROR llH 72 73 74 INDICATES THAT THE DATA READ HAD A RECOVERABLE ERROR WHICH WAS CORRECTED BY THE ECC AlGORITHH. mE DATA 75 IS PROBABLY GOOD. 76 ERROR TO ALLOW THE CONTROLLING PROGRAM A CHANCE TO DECIDE 17 FOR ITSELF. THE HOWEVER THE BIOS ROUTINE IHDICATES AN ERROR HAY NOT RECUR IF THE OUA IS Fixed Disk BIOS A-87 LOC OBJ LINE SOURCE REWRITTEN. (ALI CONTAINS THE BlMST LENGTH. 78 7. IF DRIVE PARAMETERS WERE REQUESTED. 80 81 82 DL = NUt'BER DH CH Cl = 83 8. S. 8S = = 87 OF CONSECUTIVE ACKNOWLEDGING DRIVES ATTACHED «0-2) (CONTROLLER CARD ZERO TAlLY ONLY) tlAXltruM USEABLE VALUE FOR HEAD HUt1BER ttAXltu1 USEABLE VALUE FOR CYLINDER NUt'BER I1A.XII'M1 USEABLE VALUE FOR SECTOR NlI1BER AND CYLINDER NIA1BER HIGH BITS 00 8. REGISTERS WILL BE PRESERVED EXCEPT WHEN THEY ARE USED TO RETURN ., IHFORI1ATION • •0 HOTE; IF AN ERROR IS REPORTED BY THE DISK CODE. THE APPROPRIATE 'i2 93 DOFF ooee 00&0 0040 0020 0011 0010 OOOB 0009 0007 0005 0004 GOOl 0001 ACTION IS TO RESET THE DISK. THEN RETRY TIlE OPERATION. . 95 1------- --------- ------- ----------------- - -- ----- ---- ---- - --- ------- -- --- .7 SENSEJAIL EOU OFFH I SENSE '0 UNDEF _ERR EQU OBBH I tklDEFItIED ERROR OCCURRED TIME_OUT EQU OOH I ATTACHMENT fAILED TO RESPOf-() BAD_SEEK EQU .. •• lDO 101 102 103 10' I OPERATIot~ FAILED BAD_CNTLR EQU 'DH 2DH J SEEK OPERATIOH fAILED J COHlROLLER HAS FAILED DATA_CORRECTED EQU 11H I ECC CORRECTED DATA ERROR BAD_ECC EQU lOH I BAD ECC ON DISK READ BAD_TRACK EQU DBH ; BAD TRACK FLAG DETECTED Et'" Et'" DOH I AHEMPT TO DttA ACROSS 64K BOUtmARY' lOS DMA_BOUNDARY 10' 107 100 D7H I DRIVE PARAMETER ACTIVITY' fAILED BAD_RESET EQU OSH I RESET FAILED RECORD_NOTJHD EOU D'H I REQUESTED SECTOR HOT FOl/tI) BAD_ADDR_MARK EQU D2H I ADDRESS MARK NOT FOUND BAD_CtI) EOII DlH ; BAD tOt1t1AtlD PASSED TO DISK 110 10. 110 INIT_FAIl 111 112 J ----------------------------------.----- 113 INTERRUPT Atm S1'ATUS AREAS 114 ,---------------------------------------- 11S 11. cumlY' SEGMENT AT 0 DO. 0034- 117 0034 118 HDISK_INT LABEl. Qolte "' DRG_VECTOR LABEl 120 OQ4e 122 123 12. 12S 0078 0078 0100 0100 0104 0104 7COO 7COD DO. BOOT_VEC DISKETTE_PARM DO. 1£. DISK_VECTOR 127 128 HF_TBL_VEt DO. 13D 131 DDbt DObe 1111 0072 0072: 1111 11 ?? 11 11 BOOT_LOCN I DISK ItHERRUPT VECTOR OWORO ; BOOTSTRAP ItnERRUPT VECTOR 19H*4 DWORD I DISKETTE PARAMETERS lEH*4 LABEL aWORD I HEW DISKETTE INTERRUPT VECTOR 0401i*4 LABEL DWORD I FIXED DISK PARAMETER VECTOR 041H*4 LABel DO. DWORD 13H~ LABEL DO. 1£. 0042 0042 0042 (7 11) 0074 0074 0075 0076 0077 OR. 121 0064 0064 I FIXED DISK ItITERRUPT VECTOR ODH*4- DWORD 7COOH LABel I BOOTSTRAP LOADER VECTOR FAR OUt1HY ENDS 132 133 DATA SEGMENT AT 401i 13' 13S CND_BLOCK '2H LABEL BYTE HD_ERROR DB 7 DUP(?) 13. 137 130 OR. DO. TIMER_lOW OR. 13' ,.0 ,., RESET_FLAG 142 OR. ,.3 14. CONTROL_BYTE "S PORT_OFF .. ,,.7 ,.0 0" HF _tu'1 DATA ENDS CODE SEGMENT I TIMER lOW WORD 72H OW DISK_STATUS I OVERLAYS DISKETTE STATUS 06CH I 1234H IF KEYBOARD RESET UNDERWAY 74H DB DB DB DB ; FIXED DISK STATUS BYTE I tWIT OF FIXED DISK DRIVES ; ConTROL BYTE DRIVE OPTIONS I PORT OFFSET 14' 150 J ________ w 151 I HARDWARE SPECIFIC VALUES ------------ ------- ----------- ----- ----- ------- 152 153 154 I - CONTROllER 110 PORT > WHEN READ FROM: A-88 Fixed Disk BIOS LOC OBJ LINE SOURCE 155 HF _PORT+D - READ DATA (FRDtt CONTROLLER TO CPU) 156 HF _PORT+l - READ CONTROLLER HARDWARE STATUS 151 I CONTROLLER TO CPU) 158 HF _PORT.! - READ CONFIGlRATIOH SWITCHES 159 HF _PORT+3 - NOT USED > NItEN WRITTEN TO! 160 161 HF _PORT+O - WRITE DATA (fROt1 CPU TO CONTROLLER) 162 HF _PORHl - CONTROLLER RESET 163 HF _PORT.! - GENERATE CONTROLLER SELECT PULSE 164 HF _PORT+3 - WRITE PATTERN TO DI1A AN) INTERRUPT 165 I •• MASK REGISTER 167 I •• J - - - --------- - -- - -- ----- -- -- ------ --- - - - .--- -- -- - -- - --- -- 0'32.0 I •• HF _PORT 0008 17. 171 172 173 174 RI_BUSY 17' 17. 177 17. DHA.READ 0004 0002 0001 0047 004S 0000 0062 RI_BUS Rl_IOMODE EOU EOU EOU EOU EOU OMA.HIGH EOU EOU EOU EOU I •• TST_ROY_CHO EQU I., ,.3 ,.4 RECAL_CI"I) EQU SENSE_CHO EQU fHTDRV_CHD EQU CHK_TRK_CHD EQU I •• I •• fNTTRK.CMD FMTBAD_CHD EQU , READ_tND EQU WRITE_CHO EQU DHA_WRITE DHA 0320H I DISK PORT 000010008 000001008 000000108 I DISK PORT 1 BUSY BIT COHMAND/DATA BIT HOOE BIT 00000001B REQUEST BIT I CHAN-IEl 3 1047H) 01000111B 01001011B I CHANNEL 3 I04BHI I DHA ADDRESS I PORT FOR HIGH it BITS OF DttA o 082H 17' 0000 0001 0003 0004 ODDS 0006 0007 0006 ,., .... ,.7 EQU OOOB , SEEK.CHO EQU Dooe I •• INIT_DRV_CND EQU DODD DOOE '" I.' ,.3 ,.4 RD_ECC_CND EQU WR_8UFF _CHD EQU RAM.DIAG_Ctl) EQU EQU CNTLR_DIAG_CMD EQU ODES '" ". CHK_ORV_CMD RD.LONG_CI1D 00E6 I •• WR_LONG_CND 0020 INT_CT~PORT 0020 '" ,,., EOI 0008 2" 2.3 0002 2" OOOA OOOF ODED DOn OOE4 ,.7 .. RD_BUFF _CMD EQU OOOOOOOOB 00000001B 000000118 I CNTLR READY (DOH) RECAL 101H) 00000100B 000001018 DRIVE (04HI SENSE (OlH) T CHK 105HI TRACK (MHI BAD (07H) 00000110B 000001118 000010008 READ 000010108 000010118 000011008 (OSHI WRITE 10AHI SEEK IMIT (OBH I (OCH) BURST I DOH) 000011018 000011108 BUFFR (OEH) BUFFR (OFH) 000011118 111000008 RAM IEOH) (ElH) CMTLR IE4H) DRV EQU 111000118 111001008 111001018 RLONG IE5H) EQU 111001108 WLONG IE6H) EQU EQU 20" J 8259 CONTROL PORT ; END OF INTERRUPT CotIMAND 20" EOU EOU 2 •• ••• 0000 0000 55 0001 AA 0002 10 "7 2 •• ••• 21' ASSUME CS:CODE ORG DB OH 055H DB OAAM DB loa I GENERIC BIOS HEADER 211 212 213 21. ; - ----- --- --------------- --- -- --------- - - --- - ------- --- -- - - -----I FIXED DISK 110 SETUP 215 216 I 217 21 9 220 ESTABLISH TRANSfER VECTORS FOR TH!: FIXED DISK PERFORM POWER ON DIAGNOSTICS SHOULD AN ERROR OCCUR A "1701" MESSAGE IS DISPLAYED 21. 0003 0003 EBIE 0005 35303030303539 2D284329434F50 - 1------------- - ---------------.-•• -.--------------- - - -- ------- --- .21 .22 223 PROC FAR SHORT L3 '5000059 (CJCOPYRIGHT IBM 1962' J COPYRIGHT NOTICE 59524947485420 20494240203139 3832 0023 224 0023 2BCD 22. 22. 0025 8E08 227 l3: ASSUNE DS:DUHMY SUB /Of..,/lY. Hav DS,AX J ZERO Fixed Disk BIOS A-89 LOC OBJ LINE 0027 FA "8 CLI 0028 A14COO "9 I GET DISKETTE VECTOR 230 231 HOV HOV AX,WORD PTR ORG,:..VECTOR 0028 AlOOOI WORD PTR OISK_VECTOR,AX I INTO INT 40H MOV AX,WORD PTR ORG_VECTOR+2 HOV HOV WORD PTR OISK_ VECTOR+2, AX i HOISK HANDLER HOV HOV WORD PTR ORG_ VECTOR .. Z ,CS 002E A14EOO 0031 A30201 2" 0034 C7064C005602 233 OOJA 8CO[(.[00 234 DOJE B86007 235 23. 0041 A33400 SOURCE WORD I"TR ORG_VECTOR, OFFSET DISK_IO AX, OFFSET liD_lilT I HDISK INTERRUPT MOV WORD PTR HDISK_INT ,AX 237 238 HOV WORD PTR HDISK_INHZ ,CS 0048 C7066400860 I HOV WORD PTR BOOT_VEC,OFFSET BOOT_STRAP 004E 8CO[6600 239 WORD PTR Boor_VEC"Z,CS 0052 C70b0401E703 240 HOV HOV 0058 8eOE0601 201 242 243 HOV STI WORD PTR HF _TBL_VEC .. Z,CS 0044 8eOnbOQ Dose FB 0050 884000 0060 8E08 0062 C606740000 0067 C606750000 OObC C606430000 0071 C606770000 244 245 ASSUI'IE 24. 247 248 249 250 WORD PTR Hr _TBL_VEC,OFFSET FD_TBL ; BOOTSTRAP I PARAMETER TBL OS:OATA HOV AX.DATA MOV OS.AX MOV DISK_StATUS.O ; RESET THE STATUS INOICATOR I ESTABLISH SEGMENT MOV ttF_NUM.O ; ZERO COUNT OF DRIVES HOV CND_BLOCK"l.O ; DRIVE ZERO. SET VALUE IN BLOCK MOV PORT_OFF.O I ~IOI/ CX,25H I RETRY COUNT I RESET CotlTROLtER ZERO CARD OFFSET 251 0076 892:500 252 0079 253 0079 E8F200 254 255 CALL HD_RESET_l 007e 7305 JHC L7 DOlE E2F9 25. LOOP L4 0080 [9aFDO 257 0083 258 259 0083 890100 HOV HOV 2.0 0089 880012 2'1 262 HOV con 2.3 INT Btl DOSE 7303 264 265 JNC P7 JHP ERROR_EX 0090 E9AFOO 0093 2•• 0093 880014 267 0096 con 0098 7303 TRY RESET AGAIN eX,I 0086 8A8000 OOBe i JHP L7: DX.80H AX,I20011 ; CONTROLLER DIAGNOSTICS P7: 268 HOV INT AX.14001i Jt~C P9 JHP ERROR_EX I CotlTROLLER DIAGNOSTICS 13H G09A [9.4.500 269 270 "'10 271 0090 C7066COOOOOO 272 00A3 AI7200 273 MOV AX,RESETJLAG 00A6 303412 00A9 7506 274 CHP AX,123411 275 JIIE P8 00A8 (7066C009.4.01 27. tlOV TIt'iER_LOW.410D I SI<:IP WAlT ON RESET 00B1 277 278 279 ; TIMER OOBI [42:1 DOB3 24fE 00B5 [621 00B7 0087 E88400 D08A n07 OOBe 680010 COBF con 00C1 730B 00C3 OOC3 A16eDO OOC6 30BEOI 00C9 72Ee Dace [87590 DaCE P9: HOV TIMER_LOW.O I ZERO TIMER I KEYBOARO REseT P8: III AL,021H AlID AL,GFEIl I ENABLE TIt1ER 280 281 OUT 021H,AL ; START lIMER 282 CALL tiO_RESET_I ; RESET CONTROLLER 283 284 JC PIO MOV AX.IOOOH 285 WT 13B 28. 287 288 Jtle P2 PIa: HOV J. 289 290 291 OOCE 890100 292 293 0001 BMODO 294 ; READY CMP AX.4460 I ~5 SECONDS JHP P2: ~IOV CX.I HOV OX .80H 110V AX.ll DOH INT 131l 295 0004 B80011 0007 con 29. 297 0009 7267 298 JC ERROO_EX HOV AX.OQOOH con 300 301 INT 131i ODED 7260 302 JC ERROR_EX HOV AX.OC80011 ; RECALIBRATE 299 OODB B80009 OODE ; SET DRIVE PARAMETERS 303 00E2 B800C8 304 A-90 Fixed Disk BIOS I DMA TO BUFF ER LOC OBJ LINE 00E5 8EtO 305 30. 307 308 00E7 2BDB DOn 88000F OOEt COll OOEE 7252 OOfO FE067500 OOF4 BA1302 DOH BODO OOF9 EE OOFA 8A2103 OOFD EC OOFE 240F 0100 leOF 0102 7406 0104 C7066CQOA401 OlOA 010A 8A1302 0100 BOFF OIOF EE 0110 890100 0113 BA6100 0116 0116 ZBCO 0118 CDll OllA 7240 Olle B800ll OllF CDll 0121 730B 0123 AlbeDO 01Z6 30BEOI 0129 72EB 012B EB2F90 30' 310 311 312 313 314 315 31. 317 318 31. 320 321 322 323 324 325 32. 327 328 32' 36~ 015C FA 36. 367 368 36. 370 371 372 373 374 0J33 7227 0135 FE067500 0139 81FA8100 0130 7310 013F 42 0140 EBD4 0142 0142 BDOFOO 0145 2BCO 0147 88FO 0149 89060090 0140 8700 014F Ol4F 2E8A846801 0154 B40E 0156 COlO 0158 46 0159 E2F4 0150 E421 015F OCOI 0161 E621 0163 FB 0164 E8A500 0167 CB 0168 31373031 INC Hf_HUM HOV HOV OUT DX,21lH I EXPANSION BOX I TURN BOX OFF nov AL,O DX.AL DX.321H ; TEST IF CONTROLLER J ••• IS IN THE SYSTEM WIT AX.OfOOII IN AL,DX ANO AL,OFH CHP AL,OfH BOl( ON HOY HOY OUT I WRITE SECTOR BUFFER ; DRIVE ZERO RESPONDED TII1ER_LOW,420D J CotrTROlLER IS IN SYSTEH UNIT DX,213H ; EXPANSION BOX "l,OFFH DX,Al ; TURN 80X ON ex,. I MOV HOY DX,081H sue AX.AX INT JC POD_DOHE ATTEMPT NEXT DRIVES Pl: I RESET 13N HOv AX,01100H INT JHe MOV CMP JB JHP 33' 337 336 DISC 0131 tDl3 13" ERROR_EX I SET SEGtt~NT ES,AX aX,ex BOX_ON: no nl 0158 F9 012E 880009 I10V SUB I10V INT JC J' HOY 332 333 334 335 33' 340 341 342 343 344 345 34. 347 348 34. 350 351 352 353 354 355 35. 357 358 35. 360 361 362 3.3 364 OlZE SOURCE J RECAL 13" P5 AX. TIMER_LOW AX,446D 25 SECONDS P3 POD_DONE P5: HOV INT JC ;-~--- AX,0900H I INITIALIZE CHARACTERISTICS 13N !tIC POO_DONE HF _HUH eHP OX, r eOH + S_MAXJILE - JA' INC JHP POD_DONE ; TALLY ANOTHER DRIVE 1) OX P3 POD ERROR ERROR_EX: MOV SUB HOV HOV HOY SP.OFH ; POD ERROR FLAG AX,AX 5I,AX CX,F17L ; MESSAGE CHARACTER CalM BH.O I PAGE ZERO Al,CS:Fl71SII I GET BYTE OUT_CH: HOV MOY ItIT INC lOOP STC AH.140 I VIDEO OUT 10H SI I DISPLAY CHARACTER OUT_CH I DO MORE ClI IN Al.021H ; BE SURE TIMER IS DISABLED OR AL,OlH I NEXT CHAR POD_DONE: OUT STI 021H.AL CAll DSBL RET Fl7 .B '1701' ,ODH,OAH Fixed Disk BIOS A-91 LINE LOC OBJ SOURCE Olbt 00 0160 0'\ 0006 375 F17l EOU $-F17 37. 016F 52 377 378 379 0170 Fe 3.0 016E 016E SI HD_RESET_I PUSH PUSH NEAR PROt ex ox ; SAVE REGISTER I CLEAR CARR'( CLC MOV eX,OIDOH CALL PORT_I 384 OUT DX,Al 385 CAll PORT_l EC 2402 38. IN ANIl AL,DX ; C!lEeK STATUS 387 AL,2 I ERROR BIT 7403 388 JZ R3 E2F2 389 LOOP L. 0171 890001 381 0174 382 0174 E80706 383 0177 EE 0178 Ee,030b 0178 Ol7t Ol7E 0160 0182 F9 390 01133 J9l 0183 5A. 392 393 POP ox 0184 59 POP CX 0185 Cl 394 RET 395 I RETRY COlJt.lT L6: ; RESET CARD STC R3: HD_RESET_l ENDP DISK_SETUP ENOP , RESTORE REGISTER 39. :97 398 399 ,----- INT 19 -----------------------------------------".--------- 400 401 1 INTERRUPT 19 BOOT STRAP LOADER 402 403 THE fIXED DISK BIOS REPLACES THE !IlrERRUrT 19 404 BOOT STRAP VECTOR IHTH A POINTER 10 THIS Boor RUUHNE 405 RESET THE DEFAULT DISK ANO DISKETTE PARAMETER VECTOOS WILL BE ATTEMPrED FROM 406 THE BOOT BLOCK TO BE READ IN 407 CYLINDER 0 SECTOR 1 OF THE DEVICE. 408 THE BOOTSTRAP SEQUENCE IS: 409 ;;> 410 ATTEMPT TO LOAD FROM THE DISKETTE INTO THE BOOT LOCATION (0000:7COO) ANO TRAtlSFER cmUROl THERE > If THE DISKETTE FAILS THE FIXED DISK IS TRIED FOR A. 411 412 VALID BOOTSTRAP BLOCK. A VALID BOOT BLOCK ON THE 413 055H OAAH FIXED DISK CONSISTS OF THE BYTES 414 AS THE LAST TWO BYTES OF TIlE BLOCK 415 > IF THE ABOVE FAILS CONTROL IS PASSED TO RESIDENT BASIC 41. 417 1----------- --- -------------------------- ------ ------------------ 418 0186 419 420 ASSUME OS: DUt1MY I ES:OUNMY 0166 28CO 4" SUll AX,AX MaV OS,AX BOOT_STRAP: 422 0188 8E08 I ESTABLI511 SEGMENT 423 4Z4 ;----- RESET PARAME1ER VECTORS 4ZS 018A FA. 42. 0188 C7060401E703 427 CLI MaV WORD PTR HF_TBL_VEC. OFFSET FO_TBL I~ORD 0191 8eOf0601 428 HOV 0195 C70678000102 429 MOV WORD PTR DISKETTE_PARH, OFFSET DISKETTE_TBl 0198 8COE7... 00 430 MOV HORD PTR DISKETTE_PARM.Z, CS 019F FB PTF! HF _TBl_VEC.Z. CS srr 431 432 433 ;----- ATTEMPT BOOTSTRAP FROM DISKETTE DIAD 890300 434 435 MOV CX,3 I SET RETRY COUNT 01A3 43. 01A3 51 437 PUSH CX I SAVE RETRY COUNT OlA4 2BOl 438 SUll DX,OX ; DRIVE ZERO I RESET THE DISKETTE HI: ; IPl_SYSTEM OlA6 28CO 439 SUll AX,AX 01A8 tOl3 440 INT IlH ; FILE 10 CAll OlAA nOF OlAe B80102 441 JC H2 I IF ERJ;!OR. TRY AGAIN 442 443 444 HOV AX,02:01H I READ IN THE SINGLE SECTOR OlAF 2B02 SUB OX,DX 01Bl 8EC2 445 tlOV ES,DX 0183 BB007e 446 HOV BX.OFFSET BOOT_LOCN ; ESTABLISH SEGMENT 447 0186 890100 448 MOV C)(tl I SECTOR 1. TRACK 0 0189 COB 449 INT 13H I FILE 10 CAll A·92 Fixed Disk BIOS LOC OBJ LINE SOURCE POP ex I RECOVER RETRY COUNT 451 JtlC H4 I CF SET BY UNSUCCESSFUL READ OIBE sOFeae 452 CNP "H.80H I IF TIME OUT. NO RETRY 01e1 740"' 4" 454 JZ H5 ; TRY fIXED DISK 01C3 EZOE LOOP HI I 00 IT FOR RETRY TINES 01C5 E80690 455 JNP H5 01C8 456 01C6 EA007tOOOO 457 OlBB 59 450 OIBC 730", HZ: I UNABLE TO IFL FROM THE DISKETTE H4: I IPL WAS SUCCESSFUL JMP 458 459 1----- ATTEMPT BOOTSTRAP FROM FIXED DISK 460 H5: OlCo 461 Oleo 2BCO 462 SUB AX.AX OleF 2:B02 463 SUB OX.OX con 464 rur 0101 0103 890300 0106 0106 51 465 466 467 "M MOV eX.3 PUSH ex H6: I RESET DISKETTE ; SET RETRY COUNT I IPL_SYSTEM I SAVE RETRY COUNT 0107 BASCDD 468 MOV ox.ooaOH I FIXED DISK ZERO OIDA ZBCD SUB AX,AX J RESET THE FIXEO DISK UIT 13" ; FILE 10 CALL OlOE 7212 469 470 471 H7 I IF ERROR. TRY AGAIN DIED B80102 472 MOV AX.0201H J READ IN THE SIt«iLE SECTOR 01E3 ZBDS SUB BX,ex 01E5 8EC3 473 474 Oloe COB JC MOV ES,BX 0lE7 BB007e 475 MOV BX.OFFSET BOOT_LOCH OlEA 8A6000 476 MOV OX,eOH DIED 890100 477 MOV CX.l I SECTOR 1. TRACK 0 DIFO COB 4i8 INT 13H I FILE 10 CALL I RECOVER RETRY COUNT I TO THE BOOT LOCATION i DIF2 S9 479 POP ex DIF3 7208 OIFS AIFE7D 480 JC 481 NOV H8 AX,wmw FTR BOOT_lOCN+SIOD DIFe 3D55AA 482 CMP AX,OAA,55H DIFB 74CB 483 Jl. H4 LOOP H6 DIFD 484 DIFD H07 485 H7: DRIVE NUtlOER I TEST FOR GENERIC BOOT BLOCK H6: i DO IT fOR RETRY TIMES 486 487 1------ UNABLE TO IPL FROM THE DISKETTE OR FIXED DISK 488 OlFf C018 489 IBN I RESIDENT BASIC DB 110011118 I SIH=C, HD UNLOAD:::OF - 1ST SPEC BYTE DB 2 INT 490 0201 491 0201 Cf 493 0202 02 494 0203 25 495 496 DB 25H DISKETTE_TBl: 492 0204 02: 0205 08 DB I HD LOAD:::l, HOOE:::DMA - i WAIT AFTER DFN TIL HOTOR OFF 2ND SPEC BYTE ; 512 BYTES PER SECTOR 497 DB 0206 2.4. 498 DB 0207 FF 499 DB 02.4.H OFFH I OTL 0206 50 DB 050H , GAP LENGTH FOR FORMAT 0209 F6 500 501 DB OF6H 020A 19 502 DB 25 020B 04 503 DB i EDT (LAST seCTOR ON TRACK) I GAP LENGTH I FILL BYTE FOR FORMAT I HEAD SETTLE TIME (MILLISECONDS I ; MOTOR START TIME 11/8 SECOND I 504 505 ;----- MAKE SURE TliAT All HOUSEKEEPING IS DONE BEfORE EXIT 506 Oloe ozoe PROC NEAR 508 ASSUME DS: OAT A 509 PUSH OS 507 IE DSBL 0200 884000 510 NOV AXtOAT.&. 0210 8ED6 511 MOV OS,AX 0212 8A267700 0216 SO 513 514 0217 C606770000 515 516 OZlt E86905 OZlF 2ACO 0221 EE I SAVE SEGMENT 512 MOV PUSH AX i SAVE OFFSET 517 CALL 518 519 SUB OUT PORT_l Al,Al OX,AL , RESET INT IOMA MASK 0222 C606770004 52. MOV PORT_OFF .4" 0227 E85E05 521 CALL PORT_l 02:2A 2ACO 522 SUB AL,AL OllC EE 523 OUT aX,AL 022.0 (606770008 524 MOV PORT_OFf,aH 02:32 E85305 525 CAlL PORT_3 02:35 2ACO 526 SUB Al.AL ; RESET !HT10NA MASK Fixed Disk BIOS A-93 LaC OBJ LINE 0237 EE 527 528 0238 C606770DOC 0230 E84605 SOURCE MOV OUT DX,Al PORT_OFf , OCH CALL PORT_3 0240 2ACO 529 530 SUB AL.AL 0242 EE 531 OUT DX.Al 0243 B007 532 HOV Al,07H 0245 E60 .... 533 OUT OMA+! 0 I AL 0247 fA. 0246 E4Zl 534 ell 535 53. OR Al,OZIH Al,OZOH OUT 02.1H,AL 024A De20 024C E621 IH 537 538 024£ FB 024F 58 J RESET !NT IOMA MASK I SET DMA MODE TO ; DISABLE INTERRUPT 5 I ENABLE INTERRUPTS POP I RESTORE OFFSET MOV 0254 IF 0255 C3 542 RET ; RESTORE SEGMENT 543 OS8L 544 545 1-------------- ------------ - ---- --------- 546 547 DISABLE I DISABLE INTERRUPTS STI 539 540 541 0250 88267700 ; RESET INT/DHA MASK EHOP FIXED DISK BIOS ENTRY POINT 1--------------------- -------- ----------- 548 0256 54' 550 AssurlE DS:HOTHING,ES:NOTHIUG 0256 eOF A80 551 CHP OL.BOH I TEST FOR FIXED DISK DRIVE 0259 7305 552 553 554 555 JAE HARD_DISK ; YES. HAtIDLE HERE INT 40H ; DISKETTE HANOLER 0258 C040 0250 0250 (A0200 0260 RET 55. 557 558 559 0260 FB 0261 OAE4 0263 7509 5.0 0265 C040 5.1 5.2 5.3 504 0267 2AE4 0269 BOFA81 D2bt 77EF 026E 5.5 5 •• 507 5.8 5.9 026E aOftOe 0271 7503 0,73 E9l.l.01 0276 0276 53 ASSUNE , BACK TO CALLER DS:DAU STI OR JtlZ INT ; ENABLE ItHEPRUPTS AH,AH AJ SUB 40" AH.AH eMP DL'(80H + S_MAX_FIlE - JA eMP AH,08 JHZ A2 JMP PUSH ex ex ox PUSH as PUSH 027A 06 PUSH ES 0278 56 575 PUSH S1 Ol7t 57 570 577 578 PUSH 01 0270 £86AOO 0280 50 579 580 PUSH AX CALL QSBl 0281 E888FF PUSH 0287 6E08 0289 58 028A 6"267400 MOV AX,DATA tIOV OS.AX POP AX 585 58. 587 588 MOV POP 01 POP S1 0294 07 589 590 POP 0295 IF 591 POP OS 0296 SA 592 POP OX 0297 59 593 594 595 028E SOFCDI 0291 F5 0292 SF 029] 5£ 0298 58 0299 CA0200 I SAVE REGISTERS DURING OPERATION I PERFORM THE OPERATION 581 582 583 584 0284 864000 I GET PAPAMETERS IS .. SPECIAL CASE .&.2: 570 571 572 573 574 0277 51 0276 52 0279 1£ I RESET NEC WIlEN AH=O 11 eMP I BE SURE DISABLES OCCURRED I ESTABLISH SEGMENT ; GET STATUS FROM OPERATION ,6,H.l el1C I SET THE CARRY FLAG TO INDICATE I SUCCESS 00 FAILURE I RESTORE REGISTERS ES POP ex POP 8X RET 2 I THROW AWAY SAVED FLAGS 597 0290 D29C 3803 029[ 4003 02AO 5603 02A2 6003 020'.4 6AD3 A-94 598 M1 LABEL WORD I OW DISK_RESET I OOOH DW RETUIHCSTATUS I OOIH 601 OW DISK_READ .02 .03 I 002:H OW DISK_WIBlE I 003H ow DISK_VERF I 004H 59' .00 Fixed Disk BIOS F~CTION TRANSFER TABLE LOC OSJ LINE DZAb 7203 02AE 2704 60' 60S 606 607 608 0280 eFO'!- 60. 02A8 7903 02AA 8003 02At ]003 02B2 0004 610 0284 f204 611 0286 3803 02B8 F904 61' 613 02BA 0705 614 OZBC 1505 OlBE 1C05 615 616 02tO 2305 617 02e2 ZAOS 618 02C4 3105 61. ooa SOURCE 620 H1L OW fMT_TRK I 005H OW FMT_BAO I 006H ow ow ow ow ow ow ow ow ow ow ow ow ow ow FMT_ORV , 007H BAD_COMMAND I OOSH IHIT_DRV I 009H RD_LONG I OOAH WR_LONG I OOBH DISK_SEEK I OOCH DISK_RESET I RD_BUFF I OOEH WR_BUFF I OOFH TST_ROV I OIOH HDISK_RECAL I 011H RAM_DIAG OOOH I 012H ; 013H ; 014H EQ" 621 02e6 6" SETUP _A PROC NEAR 6" 02t6 C606740000 62. 02C8 51 6" I RESET THE STATUS INDICATOR PUSH CX J SAVE CX 626 627 ;----- CALCULATE THE PORT OFFSET 628 02ec 8AEA. 629 HOV CH,OL 02eE 80CAOI 630 OR DL,l 0201 FEeA 631 DEC OL DL,l 6" SIlL 0205 88167700 633 HOV 0209 8AD5 HOV AHO 02E8 59 634 63S 636 637 638 63. 640 641 02E9 C3 64' RET 0203 DOE2 0208 80E201 OlOE 8105 02EO 02E2 02E2 OAD6 02E4 88164300 HOV SHL CL,S OL,CL J SHIFT COUNT I DRIVE NI..It1BER {O,lI DL,DH I HEAD tU1BER NOV CND_BLOCK+l,DL pop ex NOV AX,DATA OS,AX DHO 58 HOV POP DlFl aOFCOI 650 eHP AH,OIH OlF4 7503 651 652 JHZ .4 02E8 884000 02f6 E85590 02F9 OlF9 80EA80 02fC BOfMa 02FF 732F 0301 E8C2FF 0304 FEC9 0306 C606420000 0308 880E4400 OJOF 882E4500 0313 A24600 0316 A01600 PUSH AX I ESTABLISH SEGMENT ; RET~N AX STATUS JHP RETURN_STATUS SUB OL ,80H J CONVERT DRIVE NUMBER TO 0 BASED RANGE eHP OL,MAXJIlE J LEGAL DRIVE TEST JAE BA~_COMMAND 653 654 655 656 657 658 659 A4: 660 ; ----- SET UP COMMAND BLOCK 661 662 663 664 665 666 667 ; RESTORE DL OL,l 648 64. 02EA 50 OHE 8ED8 ; GEtIERATE OFFSET ; STORE OFFSET DL,eH 644 64S 646 647 02EA J SAVE Dl DEC ; SECTORS 0-16 FOR CONTROLLER NOV MOV CHO_BLOCK+2,CL I SECTOR AND HIGH 2 BITS C'l'LItIDER I CYlINDER NOV CMD_BLoeK+3,CH HOV CHO_BLOCK ... 4,AL J INTER LEAVE I MOV AL,CQtffROl_BYTE ; CONTROL BYTE (STEP OPTION I BLOCK COUNT 0319 A24700 668 HOV CHO_BLOCK+5,AL ollt SO PUSH AX I SAVE AX HOV AL,AH I GET INTO LOW BYTE 031F 32E4 669 670 671 XOR Ali,AH ; ZERO HIGli BYTE 0321 DIED 6n SAL AX,1 I *2 FOR TABLE LOOKUP 0323 BBFO 673 674 675 MaV SI,AX CMP AX,MIL ; TEST WITHIN RANGE pop AX , RESTORE AX JHB BAD_COMMAND JHP WORD PTR CS: [SI ... OFFSET HI J 0310 8AC4 0325 302.4.00 0328 56 0329 7305 0328 2:EFFA49C02 676 677 0330 678 0330 C606740001 67. DISK_STATUS ,8AO_Cf1O 0335 BOOO 680 AL,O ; PUT INTO SI FOR BR.A.HCH ; COHM.A.t.() ERROR Fixed Disk BIOS A-95 LINE LOC OBJ 0337 Cl SOURCE RET 681 682 DISK_IO_CONT ENOP 683 664 665 666 ; -----------------------------------------------RESET THE DISK SYSTEM (AH = OOOH) J------------------------------------------------ 687 o:na 688 0338 E84304 033C E83F04 689 69. 691 033F EC 692 0340 2402 693 694 695 033B EE 0342 7406 0344 C606740005 0149 C3 696 6?7 698 034A 034" E9OAOO 699 700 701 0340 ... 07400 0350 C606740000 0355 C3 PORT_l OUT OX.Al , ISSUE RESET CALL PORT_l I CONTROllER HARDWARE STATUS IN MID AL,DX ; GET STATUS AL,2 ; ERROR BIT JZ OR! HOV DISK_STATUS, BAD_RESET RET DRI: JHP DISK_RESET MOV FRoe NEAR AL,DISK_STATUS ; OBTAIN PREVIOUS STATUS ; RESET STATUS HOV RET 709 710 RETURN_STATUS 711 ; ---------------------- ------- ------------------DISK READ ROUTINE PRoe 715 HOV 0356 C60b420008 716 717 0350 E9E501 718 JHP 723 724 725 72. 727 126 729 730 731 732 733 (AH = 002H) NEAR 1 MOOE BYTE FOR OMA READ AL,OHA_READ MOV [NDP 719 720 721 722 ENOP 1--------------------- -------- ----------- -------- 0356 B047 0367 E9DBOl 'NOP RETURN_STATUS 706 707 708 0356 0360 B048 • SET THE DRIVE PARAMETERS INIT_DRV 704 705 713 714 0362 C60642000A ; RESET PORT 1-----------------------------------------------DISK STATUS ROlJTINE (AH = OOIH) ,-------------------- ---------------------------- 712 0360 NEAR PROt CALL 703 7" 0340 DISK_RESET ; --------------- -- --- ------------------- --------DISK WRITE ROUTINE (AH = 003H) 1-----------------------------------------------PROC NEAR MOV AL ,DNA_WRITE HOV CMO_BLOCK-tO ,WRITE_cm I HOoE BYTE fOR DMA. WRITE JHP ;-----------------------------------------------DISK VERIfY (AH = 004H) ; --- ---------------------- ----------------------- 734 036A 735 036A C606420005 736 MOV 036F E9C401 737 JMP PROC 738 NEAR 'IIDP 739 740 741 742 0372 743 744 0372 C606420006 745 0377 EBOC 746 1-------- ---------------------------------------FORMATTIHG 1 FORMAT TRACK JHP 747 748 FMT_TRK ENDP 0379 749 FHT_BAD PROC 0379 C6, " ... 20007 750 037E EB05 751 752 753 0380 0380 C606420004 SHORT (AH = OOSH) FMT_CONT NEAR MOV CMD_B LOCK. FMTBAD_CMD JHP SHORT = ~ FORMAT BAD TRACK (AH ~ FORMAT DRIVE = OQ7H) 006H) FMT_CotlT FMT_BAD ENDP 754 755 FMT _DRV PROC 756 FNT_ORV ENOP MOV 757 A-96 (AH = OOSH 006H 007H I ;------------------------------------------------ Fixed Disk BIOS NEAR (AH LaC OBJ LINE SOURCE 0385 AL,CMO_BLOCK-t, 0385 ... 04400 759 MOV 0388 24CO 760 761 AND Al.llOOOOOOB HOV CI'Il_BLOCK.Z,AL JHP NOHA_OP" 038A A24400 0380 E9A601 76. 763 764 765 766 I ZERO OUT SECTOR FIELD 1-----------------------------------------------GET PARAMETERS (AH = 8) 1------------------------------------------------ 767 0390 766 769 0390 IE 770 PUSH 0391 06 77l PUSH ES 0392 53 772 PUSH BX 0393 2BtO 77' 775 776 0390 GET_PARM_N GET_PARM LABEL p,oc as NEAR FA, J GET DRIVE PARAMETERS J SAVE REGISTERS 773 0395 8E08 0397 C41E0401 ASSUME DS: DUtfHY SUB AX,AX "OV OS.AX I ESTABLISH ADDRESSING 777 776 779 LES BX.HF _TBL_VEe ASSUME 0398 884000 MOV 05:0.6.1" AX.DATA 039E 8EDe 760 MOV OS,AX I ESTABLISH SEGNENT 781 03,.1..0 8OEA80 782 763 SUB Ol.aOH CMP Dl,MAX_FILE OJA6 732F 78. 765 JAE O' OlAS E8tBFF 766 CALL SETUP _A SW2_0FFS 03A3 80FA08 ; TEST WITHIN RANGE 767 768 CALL 03AE 7227 769 JC G, 03BO 0308 790 791 ADO eX,AX 03B2 268B07 792 HOV AX,ES:[BX] 793 SUB AX.2 03A6 EBOFO] 0385 200200 ; MAX NUt!BER OF CYLIt4)ERS I ADJUST FOR O-N ; AND RESERVE LAST TRACK 79. 03B6 8Af8 CH,AL 795 796 MOV 03BA 250a03 AtlD AX,0300H 03BO OlEB 797 SH' AX,I OlBF DIE8 796 SH' AX,l I HIGH nlO BITS OF 03el oell 799 OR Al,OllH 03e3 8AC8 600 MOV CL,AL 03es 268A7702 MOV DH,ES:[BXJ[l] ; HEADS 03C9 FEtE 801 80. 603 DEC DH I O-N RANGE 03te 8.60167500 80. "OV SUB Ol,HF _HUM ; DR IVE COUNT POP BX OleF 2BCO 605 0301 806 0301 58 607 608 809 0302 07 0303 IF I SECTORS AX.AX G5: POP ES POP os ; RESTORE REGISTERS RET 0307 810 811 0307 C606740007 612 HOV DISK_STATUS ,INITJAIl OlOC 6407 8" HOV 030E U.CO 81' SUB AH,INIT_FAIL AL,AL 03D4 CA0200 03EO 2B02 64: 815 SUB OX,OX 03E2 2Be9 816 S,", CX,CX 03E4 F9 8" STC 03E5 EBEA 818 JHP 819 8" 821 , OPERATION FAILED I SET ERROR fLAG OS ENDP GET_PARM 1-------------------------------------------------------- 822 • INITIALIZE DRIVE CHARACTERISTICS 824 i 6" en fIXED DISK PARAMETER TABLE 825 826 I - THE TABLE IS COMPOSED OF A BLOCK DEFINED AS: 827 626 (I WORD) - MAXIt1Ut1 NUMBER Of CYLINDERS 8.9 630 (1 WORD I - STARTING REDUCED WRITE CURRENT 831 (1 WOF1D I - STARTING WRITE PRECOMPENSATION CYl 8" 8" .,. 83. (1 BYTE) - HAXlt1Ut1 ~ER OF HEADS cn (1 BYTE I - MAXlt1Ut1 ECC OAT A BURST LENGTH (1 BYTE I - CONTROL BYTE (DRIVE STEP OPTION) BIT 7 DISABLE DISK-ACCESS RETRIES : BIT 6 DISABLE ECC RETRIES Fixed Disk BIOS A-97 LINE LOC OBJ SOURCE BHS 5-] ZERO 8l' 8" 8'8 BITS 2-0 DRIVE OPTION BYTE) - STAHDARD TIME OUT VALUE (SEE BELOW) (l 6" 8" 11 BYTE) - TIME OUT VAlUE FOR FORMAT DRIVE 11 BYTE I - TIME OUT VALUE FOR CHECK DRIVE (4 BYTES I 840 - RESERVED FOR FUTURE USE 842 84' 84. 84. - TO DYNAMICALLY DEFINE A SET OF PARAMETERS BUIlO A TABLE OF VALUES At-Il PLACE TliE CORRESPOUDIHG VECTOR INTO INTERRUPT 41. 8" 847 8.8 849 NOTE: THE DEFAULT TABLE 15 VECTORED IN FOR 8" AN INTERRUPT 19H (BOOTSTRAP I 8., 852 , 853 I ON TIfE CARD SWITCH SETTINGS 8.4 8 •• 8 •• 8.7 8.8 8 •• 8.0 DRIVE 0 DRIVE 1 ON : -1- -2- I -3- -4-: Off 6., 6.' 6.3 TRANSLATION TABLE 8 •• 8 •• 1/3 : 214 : TABLE ENTRY 6 •• 6.7 •• 8 8.' 870 ON ON ON Off Off Off Off ON 8" 672 1-----------------------------------------------------__ _ 8n 03E7 8,. OlE7 32.01 876 877 678 67. .7. 03E9 02- 03EA 3201 .80 .81 03EC 0000 ••• GlEE 08 OlEF 00 1----- DRIVE TYPE 00 ow OW 03060 020 03060 OW 00000 oli O.H DB 853 DB 0011 Q3FO DC 884 DB OCH I STAUOARO 03Fl B4 8.5 DB 86. OMH I FORHAT DRIVE 03f, 28 DB 028H ; CHECK DRIVE 03f] 00000000 887 888 869 D. 0.0,0,0 1----- DRIVE TYPE 01 690 03F7 7701 ow 8n 8" DB OBO 03FA 7701 8" Ow 03750 03FC 0000 8.4 DH 00000 03FE DB 03FF 05 8 •• 8 •• DB O.H 0400 DC 897 DB OCH I STAtlDARD OttO I 84 0402 28 0403 00000000 8.8 DB OB4H 1 FORHAT DRIVE 8 •• DB 028H ; CHECK DRIVE .00 DB 0,0,0,0 03F9 08 .01 902 0407 3201 0409 06 04QA 8000 040C 0001 040E DB 040F 05 0410 DC 0411 84 A-98 .03 .04 .0.'0' .0. .07 .08 "0 .11 08 03750 OBH 1----- DRIVE TYPE 02 ow 03060 DB 0.0 ow Olzeo OW 02560 DB OBH DB B5H 08 OtH I STAt.JDARD DB 064H I FORMAT DRIVE Fixed Disk BIOS LOC OBJ LINE 0412 28 .12 DB 0413 00000000 '13 DB 0417 3201 91. 915 91. 917 0419 04 041A 3201 041C 0000 041E DB 041F 05 0420 DC 0421 Bit 0422 28 0423 00000000 0427 SOURCE J CHECK DRIVE 1----- DRIVE TYPE 0] .,. OW .,. ... .., .,. ... ." ." ........, ." ... ... 026H 0,0,0,0 "0 OW 03060 00000 OW DB '21 .22 'SH DB OSH DB 'CH I STANDARD DB OB4H DB 028H I FORMAT DRIVE I CHECK DRIVE D. 0,0.0,0 .25 92. 927 03060 DB IHIl_DRY PROC NEAR 92. 0427 C60642000C 042C C606430000 0431 E81000 0434 nOD . .7 1----- DO DRIVE ZERO MOV CMD_BLOCK"O. INIT_DRY_tHD MOV tHO_BLOCK+l,O CALL INIT_DRV_R JC INIT_DRY_OUT 1----- DO DRIVE ONE "6 0436 C60642000C 0438 (6064)0020 0440 E80100 0443 0443 C3 0444 0444 2ACO 0446 E81901 0449 7301 0448 C] 044C 044C 11:: 0440 28CO 044F SEOS 0451 C41E0401 0455 If 0456 £83403 0459 7257 9., .41 942 94> 944 .45 '4. 947 .46 94. '55 95. 957 .58 .5. %. 045B 0308 9'1 962 0450 BfOlOO 9" 9.4 '.5 9., 0460 E85FOO 0463 7240 CHD_BLOCK+D .INlT_DRV_CI'1D MeV CMD_BlOCK+l.OOlOOOOOB INIT_DRY_R CALL INIT_DRY_OUT: RET INIT_DRY ENOP INIT_DRV..;,R ... 951 .52 95> .5. MOV ES:COOE AL,AL CALL COMMA,., JHe .1 NEAR 81: PUSH OS ASSlIt1E DS:Out1NY SUB AX,AX MOV OS,AX LES BX, HF _ TBL_VEt POP OS ASSlR1E DS:OATA CALL JC ., AOD BX,AX MOV CAll JC ., 01,1 INIT_ORV_S MOV .71 CAll lNIT_ORV_S 046B 7245 '12 JC B' 0460 8FD200 9n 974 975 MOV 01,2 CAll JC ., MOV 01,4 0473 7230 0475 8F0400 0478 E84700 0478 7235 0470 BF030D 0480 E83FOD 97' 977 976 .7. '8' .61 962 0483 7220 96' .64 0485 8F0600 'B' 9Sb 0486 E83700 0488 7225 987 966 I ESTABLISH SEGMENT I RESTORE SEGMENT 1----- SEI-IJ DRIVE PARAMHERS MOST SIGNIfICANT BYTE FIRST 97. 0470 E64FOO I S.6.VE SEGMENT SW2_DFFS 0466 E85700 0465 BFODDO I ISSUE THE COMMAND RET •• 7 •• 6 ••• PRoe ASSUHE SUB 01,0 1NIT_DRV_S CAll INIT_DRV_S JC B' MOV 01,3 CALL ., Jt IH1T_DRV_S MCV 01,6 CAll ., JC INIT_DRV_S Fixed Disk BIOS A-99 LaC OBJ LINE SOURCE ... ......", ....., .8' 0480 BF05DO 0490 E8HOO 0493 7210 0495 BFQ700 0498 E82700 0498 7H5 0490 BroeDO 04AO 268.4.01 04A3 A27600 MOV .91 IHIT_DRV_S JC BJ MOV CALL 01.7 UllT_DRV_S JC BJ MOV 01,8 MOV MOV AL,ES:[BX + OIl CONTROL_BYTE tAL SUB CX,CX •• 5 ••8 ••• 01,5 CALL 10DD I DRIVE STEP OPTION 1001 04.&.6 26C9 1002 04A8 1003 1004 04A8 E80302: 04A8 EC 85: - CALL PORT I IN Al,OX 04AC Aeo, 1005 1006 TEST Al,Rl_ IOManE 04AE 7509 1007 JtlZ B. 0480 E2F6 1008 lOOP B5 0482 MOV DISK_STATUS. IHIT_FAIl 0488 C3 1009 1010 1011 1012- 0489 1014 0489 E8850, 1015 CALL PORT_D 04BC EC IN Al,DX 0480 2402- 1016 1017 AND AL.2 a4Br 75Fl 1018 JNZ B3 04Cl CJ 1019 RET 0482: C606740007 0467 f9 I STATUS INPUT MOOE I OPERATIQH FAILED , MASK ERROR BIT 83: STC RET lOll 66: 1020 1021 ASSUME INIT_DRV_R ES:NOTHING ENOP 10<:2 102:3 1----- SEHD ll-IE BYTE OUT TO THE CONTROLLER 1024 04C2: 1025 04C2 E8C501 1026 CALL Ho_WAIT_REQ 04C5 7207 1027 Je 01 04C7 E8A702 IIIIT_DRV_S PROC NEAR 1028 CALL 04CA 2b8AOI 102:9 MOV AL.ES:{8X + OIl 04CO EE 1030 OUT DX,AL 04CE 1031 04CE C3 1032 1033 PORT_O Dl: RET UHT_DRV_S EHOP 1034 1035 103b 1037 ;---------------------------------------READ LONG IAH = OAH, ;---------------------------------------- 1038 04CF 1039 04CF E81900 1040 CALL CHK_LONG 0402: 72bB 1041 JC G8 0404 CbOb42:00E5 1042 MOV CMD_BLOCK+O, RD_LONG_Ctll 0409 B047 1043 MOV AL,ONA_READ 040B EBb8 1044 JMP SHORT 1045 RO_LONG PROC RD_LOHG NEAR DHA_OPN EHOP 1046 1047 1-------- -- ------- ----- ------ ------------ 1048 1049 tAH ,. OBH) WRITE LONG 1---------------------------------------- 1050 0400 1051 04Do E80BOO 1052 CALL C~IK 04EO 7250 1053 JC G8 04E2 Cb064200Eb 1054 1055 'lOY MOV CMD_BLOCK+ O. WR_LONG_CMO 04E7 6048 JMP SHORT 04E9 E85A WR_LOHG 1056 1057 PROe ""_ LONG HEAR - LONG AL.oMA_WRITE OMA_OPN ENOP 1058 04EB 1059 CHK_LOHG PROC HEAR 04E8 A04600 lObO MOV AL,CI1O_BlOCK+4 04EE 3ceo lObi CtlP AL.080H 04FO FS 10b2: 04F 1 C3 1063 1064 eMe RET CHK_LONG 1065 A-tOO Fixed Disk BIOS EtIDP lOC OBJ LINE 1066 1067 1068 SOURCE 1---------------------------------------SEEK (AH = OCH) 1---------------------------------------- 1069 04F2 1070 04F2 C60642000B 1071 CMO_BlOCK.SEEK_Ctl) 1072 SHORT 1073 ENDP 04F7 EB3D DISfCSEEK PROC NEAR tl)11A_DPH 1074 04F9 04F9 C60642000E 1075 1076 1-------- ---------------------------------------- 1077 1078 1079 ; ------------------------------------------------ READ SECTOR BUFFER 1080 1081 NOV 0503 8047 1082 HOV 0505 EBlE 1083 JMP 04FE C606460001 = OEH) IAH CMD_BlOCK.J-4,l I ONLY ONE BLOCK 1085 1086 1087 1------------------------------------------------ 1068 f------------------------------------------------ WRITE SECTOR BUFFER = OFH) IAH 1069 0507 1090 0507 C60642DCOF 1091 osoe WR_BUFF PROC NEAR 1092 MOV 0511 B048 1093 HOV AL.DMA_WRITE 0513 E630 1094 JMP SHORT C606460001 1095 ; ONLY ONE BLOCK CHD_BLOCK+4.1 OMA_OPN WR_BUF F EHOP 1096 1097 1096 ;-----------------------------------------------TEST DISK READY (Aft OlOHI 1099 1-- ---------------------------------------------- = 1100 OS15 1101 0515 C606420000 OSIA EBIA 1103 1102 1105 1106 1107 i ------------------------------------------------ 1106 ; ------------------------------------------------ RECALIBRATE (AH = 011H) 1109 051C 1110 HDISK_RECAl OSlC C606420001 1111 1112 MOV CtID_BLOCK .RECAl_CMD JMP SHORT 0521 EBl3 PROC HEAR NDMA_OPN ENDP 1113 1114 1115 1116 ; -------------------------------------------------------- 111"1 J -------------------------------------------------------- 0523 1116 1119 0523 C6064200EO 1120 0528 EBOC 1121 CONTROLLER RAM DIAGNOSTICS PROC IAH = 012HI HEAR CMD_BlOCK+O ,RAI''-DIAG_CMD JMP 1122 SHORT t-IlHA_OPN ENDP 1123 1124 1------------------------------------------------ 1125 1126 DRIVE DIAGNOSTICS (AH = 013H) J ------------------------------------------------ 1127 0524 1126 0524 C6064200E3 1129 052f EB05 1130 CHK_DRV PRot NEAR HOV CMD_BLOCK+O .CHK_ORV_CMD 1132 1133 1134 i ---------------------------------------------------------- 1135 ,---------------------------------------------------------- CONTROLLER INTERNAL DIAGNOSTICS I AH = 014H) 1136 0531 0531 t60642:00£4 1137 1138 CNTLR_DIAG 1139 CHTLR_DIAG MOV PROC NEAR CND_BLOCK + O. CHTlR_DIAG_CMD EtilP 1140 Fixed Disk BIOS A-IOI LINE LOC OBJ 1141 1142 1143 SOURCE J ------- ------------------------------------------------SUPPORT ROUTINES 1-------------------------------------------------------- 1144 0536 1145 0536 8002 1146 HOV 0538 £82700 1147 CALL 0538 7221 1148 JC G11 0530 £B16 1149 IN" SHORT COMMAtI) ISSUE THE COtt1At-aJ G3 68: 053F 1150 053F C606740009 1151 MOV 0544 C3 usz RET 0545 1153 0545 E85701 1154 CALL OHA_SETUP 0548 72f5 1155 JC G8 ..u.03H 054 ... B003 1156 MOV 054C f81300 1157 CAll CDt1MAUO 054F nOD 1156 1159 1160 JC GIl HOV AL,03H OUT OMAHO,AL 0551 BODl 0553 E60A 63: 0558 E8A.4.01 1161 1162 1163 1164 1165 055E 1166 G11: OSSE E83800 1167 0561 C3 1168 0555 0555 E421 0557 240F 0559 [621 I SET UP fOR DNA OPERATION I ISSUE THE COHHAND I INITIALIZE THE DISK CHANNEL AL,021H ANO Al,OOFH OUT 021H,AL CAll WAIT_IHT RET 1169 1170 1171 ; ------ ---------- -- ---------- ---------------- -----------I COMHAHD 1172 1173 THIS ROUTINE OUTPUTS THE COMMAN!) BLOCK ; INPUT 1174 AL = CONTROLLER DHA/INTERRUPT REGISTER HASK 1175 0566 EE 1176 1177 1178 1179 1180 1181 0569 E81C02 1182 0562 0562 8E4200 0565 E81B02 1---------------- ------ --------- -------- ----------------COMt1AI'IJ PROC MOV UEAR SI.OFFSET CND_BLOCK CALL PORT_2 OUT DX,Al CALL PORT_3 1183 1184 OUT OX,AL 0560 28C9 SUB CX,CX 056F E80C02 1185 CALL PORT_l 0572 1186 1187 056C EE 0572. EC 0573 ,40F AL,DX I CONTROLLER SELECT PULSE I WAIT COiA'lT I GET STATUS AHD Al,OfH CH" JE Al,Rl_BVSY OR Rl_BUS OR Rl_REQ 0579 E2F7 1188 1189 1190 1191 0578 C606740080 lin NOV 0580 f9 1193 1194 1195 RET 0575 3eoo 0577 7409 0581 C3 0582 Cl lOOP STC 1 ERROR RETURN ClD 0583 890600 1196 1I97 058& 1198 0586 [8E601 1199 0589 At 12.00 LOOSB 05SA. EE OUT OX,AL ; OUT IT GOES lOOP CM3 I 00 MORE 0560 E8EEOI 1201 1202 1201 1204 CALL PORT_I I 0590 EC 1205 IN AL,OX 0591 AMI 1206 TEST AL,Rl_REQ 0593 7406 1207 1208 JZ CM7 0595 C606740020 059,A, F9 1209 STC 0562 Fe 0588 E2F9 NOV CX,6 CALL PORT_O I BYTE COUNT CH1: I GET TilE HEXT COHMAND BYTE STATUS NOV 0598 1210 eM7: 0596 C3 1211 1212 COMMAND EHOP RET 1211 1214 1------------------------------------------------ 1215 SENSE STATUS BYTES 1216 1217 A·I02 I BYTE 0 Fixed Disk BIOS LOC OBJ LINE SOURCE BIT BIT BITS 5-4 BITS 3-0 1218 1219 122.0 1221 ADDRESS VALID. WHEN SET SPARE I SET TO lERO ERROR TYPE ERROR CODE 1222 1223 I BYTE 1 1224 BITS 7-6 1225 BIT lERD DRIVE 10-11 1226 BITS 4-0 HEAD tu'BER 1227 12:28 1229 I BYTE 2 1230 BITS 7-5 CYLlNDER HIGH BITS '+-0 SECTOR MJt1BER BITS 7-0. CYlINDER lOW 1231 1232 I BYTE 3 1233 1234 059C 1235 1- - -.-.- - ------ ----- ------ -- ----- --- ------ ------- 1236 1237 ERROR_CHK PROC HEAR 12:38 ASSlI1E ES:DATA OSA3 C3 1242 HOV OR JHZ RET Al.DISK_STATUS 05.1.1 7501 1239 1240 1241 059C ... 07400 059F OACO 05.1.4 1243 1244 1----- PERFORM SENSE STATUS 1245 12:46 G21: 05A7 8EtO 1248 05"9 28tO 05"B 88F8 12:49 05AO C606420003 1251 0582 2ACO 1252 HOV HOV !Ml HOV HOV SUB 05Aft 884000 05B4 E8ABFF 1247 12:50 I CHECK IF THERE WAS AN ERROR AL,AL 021 AX.DATA ES,AX ; ESTABLISH SEGMENT AX,AX Dl,AX CtIJ_BlOCK+O.SENSE_CtIJ .U,AL 12:S3 CALL COt1MAND I 15SUE SENSE STATUS CotI1AND 05B7 7223 12:54 I CANNOT RECOVER 1255 JC HOV SENSE_ABCRT 0589 B90400 CX,it 05BC 1Z56 05BC E8CBOO 1257 CALL 05BF 7220 12:58 JC 05CI E8AD01 1259 CALL QSCit EC 1260 OSCS 26884542 1261 OSC9 47 1262 IN HOV INC DI OSC'" E8B101 1263 CAll PORT_l G22: ... liD_WAlT_REq PORT_O AL.DX ES:HD_ERROR[DI J,AL oseD E2ED 1264 LOOP 022 OSCF E8B800 1265 CAll HV_WAlT_REQ 05D2 720D 1266 JC 05D4 E89AOl 1267 CAll PORT_O 05D7 EC 1268 IN AL.OX 0508 A802 1269 OSDA 740F 1270 05DC 1271 05DC C6067400FF 1272 05El 1273 05El F9 1274 05E2 C3 1275 1276 I STORE AWAY SENSE BYTES 0. . TEST AL,2 JZ STAT_ERR SENSE_ABORT: HOV DISK_STArus.SEHSE]AIL &24: STC RET ERROR_CHK Et > Shift Cyan Yellow High Intensity 3F 63 ? ? Shift Cyan White High Intensity 40 64 @ @ Shift Red Black Normal 41 65 A A Note 4 Red Blue Underline 42 66 B B Note 4 Red Green Normal 43 67 C C Note 4 Red Cyan Normal 44 68 D D Note 4 Red Red Normal 45 69 E E Note 4 Red Magenta Normal 46 70 F F Note 4 Red Brown Normal 47 71 G G Note 4 Red Light Grey Normal 48 72 H H Note 4 Red Dark Grey High Intensity 49 73 I I Note 4 Red Light Blue High Intensity Underline 4A 74 J J Note 4 Red Light Green High Intensity Shift Of Characters, Keystrokes, and Colors C-3 As Text Attributes Value As Characters Hex Dec Symbol Keystrokes Color/Graphics Monitor Adapter IBM Monochrome Display Modes Background Foreground Adapter 4B 75 K K Note 4 Red Light Cyan High Intensity 4C 76 L L Note 4 Red Light Red High Intensity 4D 77 M M Note 4 Red Light Magenta High Intensity 4E 78 N N Note 4 Red Yellow High Intensity 4F 79 0 0 Note 4 Red White High Intensity 50 80 P P Note 4 Magenta Black Normal 51 81 Q Q Note 4 Magenta Blue Underline 52 82 R R Note 4 Magenta Green Normal 53 83 S S Note 4 Magenta Cyan Normal 54 84 T T Note 4 Magenta Red Normal 55 85 U U Note 4 Magenta Magenta Normal 56 86 V V Note 4 Magenta Brown Normal 57 87 W W Note 4 Magenta Light Grey Normal 58 88 X X Note 4 Magenta Dark Grey High Intensity 59 89 Y Y Note 4 Magenta Light Blue High Intensity Underline 5A 90 Z Z Note 4 Magenta Light Green High Intensity 5B 91 [ [ Magenta Light Cyan High Intensity 5C 92 \ \ Magenta Light Red High Intensity 5D 93 1 1 Magenta Light Magenta High Intensity 5E 94 A A Shift Magenta Yellow High Intensity 5F 95 - - Shift Magenta White High Intensity 60 96 Yellow Black Normal 61 97 a a Note 5 Yellow Blue Underline 62 98 b b Note 5 Yellow Green Normal 63 99 c c Note 5 Yellow Cyan Normal 64 100 d d Note 5 Yellow Red Normal 65 101 e e Note 5 Yellow Magenta Normal 66 102 f f Note 5 Yellow Brown Normal C-4 Of Characters, Keystrokes, and Colors As Text Attributes Value As Characters Hex Dec Symbol Keystrokes IBM Monochrome Display Adapter Modes Background Foreground Color/Graphics Monitor Adapter 67 103 g g Note 5 Yellow Light Grey Normal 68 104 h h Note 5 Yellow Dark Grey High Intensity 69 105 i i Note 5 Yellow Light Blue High Intensity Underline 6A 106 j j Note 5 Yellow Light Green High Intensity 6B 107 k k Note 5 Yellow Light Cyan High Intensity 6C 108 I I Note 5 Yellow Light Red High Intensity 6D 109 m m Note 5 Yellow Light Magenta High Intensity 6E 110 n n Note 5 Yellow Yellow High Intensity 6F 111 0 0 Note 5 Yellow White High Intensity 70 112 p p Note 5 White Black Reverse Video 71 113 q q Note 5 White Blue Underline 72 114 r r Note 5 White Green Normal 73 115 s s Note 5 White Cyan Normal 74 116 f f Note 5 White Red Normal Magenta Normal 75 117 u u Note 5 White 76 118 v v Note 5 White Brown Normal 77 119 w w Note 5 White Light Grey Normal 78 120 x x Note 5 White Dark Grey Reverse Video 79 121 y y Note 5 White Light Blue High Intensity Underline 7A 122 z z Note 5 White Light Green High Intensity 123 { { Shift White Light Cyan High Intensity 7C 124 I I I I Shift White Light Red High Intensity 7D 125 l l Shift White Light Magenta High Intensity 7E 126 ~ ~ Shift White Yellow High Intensity White White High Intensity 7B 7F 127 /:;. Ctrl - Of Characters, Keystrokes, and Colors C-S As Text Attributes Value As Characters Hex Dec Symbol Keystrokes IBM Monochrome Display Adapter Modes Background Foreground Color / Graphics Monitor Adapter 80 to FF Hex are Flashing in both Color & IBM Monochrome * * * * * * * * 80 128 c;: Alt 128 Note 6 Black Black Non-Display 81 129 U Alt 129 Note 6 Black Blue Underline 82 130 e Alt 130 Note 6 Black Green Normal 83 131 Ii Alt 131 Note 6 Black Cyan Normal 84 132 ii Alt 132 Note 6 Black Red Normal 85 133 Alt 133 Note 6 Black Magenta Normal 86 134 a a Alt 134 Note 6 Black Brown Normal 87 135 c; Alt 135 Note 6 Black Light Grey Normal 88 136 Alt 136 Note 6 Black Dark Grey Non-Display 89 137 e e Alt 137 Note 6 Black Light Blue High Intensity Underline 8A 138 e Alt 138 Note 6 Black Light Green High Intensity 8B 139 'I Alt 139 Note 6 Black Light Cyan High Intensity 8C 140 1 Alt 140 Note 6 Black Light Red High Intensity 8D 141 i Alt 141 Note 6 Black Light Magenta High Intensity 8E 142 A Alt 142 Note 6 Black Yellow High Intensity 8F 143 A Alt 143 Note 6 Black White High Intensity 90 144 E Alt 144 Note 6 Blue Black Normal 91 145 ae Alt 145 Note 6 Blue Blue Underline 92 146 AE Alt 146 Note 6 Blue Green Normal 93 147 6 Alt 147 Note 6 Blue Cyan Normal 94 148 ii Alt 148 Note 6 Blue Red Normal 95 149 b Alt 149 Note 6 Blue Magenta Normal 96 150 Q Alt 150 Note 6 Blue Brown Normal 97 151 U Alt 151 Note 6 Blue Light Grey Normal 98 152 Y Alt 152 Note 6 Blue Dark Grey High Intensity 99 153 ii Alt 153 Note 6 Blue Light Blue High Intensity Underline 9A 154 U Alt 154 Note 6 Blue Light Green High Intensity C-6 Of Characters, Keystrokes, and Colors As Text Attributes Value As Characters Hex Dec Symbol 9B 155 Keystrokes IBM Monochrome Display Modes Background Foreground Adapter Color / Graphics Monitor Adapter ¢ Alt 155 Note 6 Blue Light Cyan High Intensity 9C 156 £ Alt 156 Note 6 Blue Light Red High Intensity 9D 157 ¥ Alt 157 Note 6 Blue Light Magenta High Intensity 9E 158 Pt Alt 158 Note 6 Blue Yellow High Intensity 9F 159 J Alt 159 Note 6 Blue White High Intensity AO 160 a Alt 160 Note 6 Green Black Normal A1 161 f Alt 161 Note 6 Green Blue Underline A2 162 6 Alt 162 Note 6 Green Green Normal A3 163 U Alt 163 Note 6 Green Cyan Normal A4 164 Ii Alt 164 Note 6 Green Red Normal A5 165 N Alt 165 Note 6 Green Magenta Normal A6 166 i!. Alt 166 Note 6 Green Brown Normal A7 167 .£ Alt 167 Note 6 Green Light Grey Normal A8 168 t. Alt 168 Note 6 Green Dark Grey High Intensity A9 169 r- Alt 169 Note 6 Green Light Blue High Intensity Underline AA 170 -, Alt 170 Note 6 Green Light Green High Intensity AB 171 Y, Alt 171 Note 6 Green Light Cyan High Intensity AC 172 Y, Alt 172 Note 6 Green Light Red High Intensity AD 173 i Alt 173 Note 6 Green Light Magenta High Intensity AE 174 Note 6 Green Yellow High Intensity 175 « » Alt 174 AF Alt 175 Note 6 Green White H ig h Intensity Alt 176 Note 6 Cyan Black Normal BO 176 ----- Bl 177 i Alt 177 Note 6 Cyan Blue Underline B2 178 I Alt 178 Note 6 Cyan Green Normal B3 179 Alt 179 Note 6 Cyan Cyan Normal B4 180 - Alt 180 Note 6 Cyan Red Normal B5 181 Alt 181 Note 6 Cyan Magenta Normal B6 == 182 ----l Alt 182 Note 6 Cyan Brown Normal Of Characters, Keystrokes, and Colors C-7 As Text Attributes Value As Characters Hex Dec Symbol Keystrokes Color / Graphics Monitor Adapter IBM Monochrome Display Modes Background Foreground Adapter B7 183 --n Alt 183 Note 6 Cyan Light Grey Normal B8 184 ==i Alt 184 Note 6 Cyan Dark Grey H ig h Intensity B9 185 .-l Alt 185 Note 6 Cyan Light Blue High Intensity Underline Alt 186 Note 6 Cyan Light Green High Intensity Alt 187 Note 6 Cyan Light Cyan High Intensity Alt 188 Note 6 Cyan Light Red High Intensity Alt 189 Note 6 Cyan Light Magenta High Intensity I BA 186 BB 187 BC 188 BD 189 ===il ==::!J ~ BE 190 P Alt 190 Note 6 Cyan Yellow High Intensity BF 191 II Alt 191 Note 6 Cyan White High Intensity CO 192 L- Alt 192 Note 6 Red Black Normal I Alt 193 Note 6 Red Blue Underline Alt 194 Note 6 Red Green Normal Alt 195 Note 6 Red Cyan Normal C1 193 C2 194 C3 195 C4 196 Alt 196 Note 6 Red Red Normal C5 197 Alt 197 Note 6 Red Magenta Normal C6 198 Alt 198 Note 6 Red Brown Normal C7 199 Alt 199 Note 6 Red Light Grey Normal Alt 200 Note 6 Red Dark Grey High Intensity Alt 201 Note 6 Red Light Blue High Intensity Underline ---.J L CA 202 Alt 202 Note 6 Red Light Green High Intensity CB Alt 203 Note 6 Red Light Cyan High Intensity Alt 204 Note 6 Red Light Red High Intensity Alt 205 Note 6 Red Light Magenta High Intensity Alt 206 Note 6 Red Yellow High Intensity Alt 207 Note 6 Red White High Intensity Alt 208 Note 6 Magenta Black Normal C8 200 C9 201 203 CC 204 ~ == Jr'-== Ii -----, r - I~ CD 205 CE 206 CF 207 DO 208 C-8 ~~ 1 Of Characters, Keystrokes, and Colors As Text Attributes Value As Characters Hex IDec Symbol '~y~"v~~~ IBM Monochrome Display Adapter Modes Background Foreground 6 1209 D2 210 Color/Graphics Monitor Adapter i Mag' Alt 210 Note 6 Magenta 211 LL- Alt 211 Note 6 Magenta D4 1212 t:::::: Alt 212 Note 6 Magel D5 213 F Alt 213 Note 6 Magenta Magenta D6 214 r- Alt 214 Note 6 Magenta Brown D7 215 Alt 215 Note 6 Magenta Light Grey Normal Alt 216 Note 6 Magenta Dark Grey High Intensity Alt 217 Note 6 Magenta Light Blue High Intensity Underline DA 218 Alt 218 Note 6 Magenta Light Green H ig h Intensity 1219 219 6 .igl Cyal High Intensity DC 220 Alt 220 Note 6 Magenta Light Red High Intensity DD 221 Alt 221 Note 6 Magenta Light Magenta High Intensity DE Alt 222 Note 6 Magenta Yellow High Intensity D3 II I D8 216 D9 217 Green Normal Cyan Normal Normal f-- 222 1ge1 DF 223 Alt 223 Note 6 Ma! White High II EO 224 O! Alt 224 Note 6 Yellow Black Normal 225 f3 Alt 225 6 Yellow Blue Underline 226 r Alt 226 Note 6 Yellow Green Normal Cyan NOI 2: Alt 228 Note 6 Yellow Red Normal E5 1229 Alt 229 Note 6 Yellow Mag' E6 1230 AI 230 Note 6 Yellow Brown NOr! E2 E3 1227 E4 228 6 msity II rmal E7 231 T Alt 231 Note 6 E8 232 1> Alt 232 Note 6 Yellow Dark Grey High Intensity E9 233 e Alt 233 Note 6 Yellow Light Blue High Intensity Underline EA 234 n Alt 234 Note 6 Yellow Light Green High Intensity EB 0 Alt 235 Note 6 Yellow Light Cyan High Intensity 235 Of Characters, Keystrokes, and Colors C-9 As Text Attributes Value As Characters Hex Dec Symbol EC 236 ED 237 00 Keystrokes Alt 236 IBM Monochrome Display Adapter Modes Background Foreground Color / Graphics Monitor Adapter Note 6 Yellow Light Red High Intensity Light Magenta High Intensity 15 F ~ ... • -¢; ... / C-12 , < ? • A B C D E F G H I J K L M N 0 5 6 7 p , P Q a q R b r S c s T d t U e u V f v W g W X h x • Y 1. y Z J z [ k { "'- I ] m } I I 1\ n ~ - 0 L:,. Of Characters, Keystrokes, and Colors Character Set (80-FF) Quick. Reference DECIMAL VALUE • • ~!~luMtL 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 HEXA 128 144 160 176 192 208 224 240 9 8 A B , .. <; E a, ... •• U ce 1 ~~~ , , e IE 0, I 1\ a 01\ u a,•• 0,•• n a 0 N= 1\ a u, a 0 C I " """" " 0 ~ U 1\ •• 8 9 9 10 A 11 B •• 12 c 13 0 1, £ 14 E 15 F ~ ---t ¢ 1 ¥ A A Pt f' ~ :1 ~ d f-L r-- ,U 0 « bd ~ » n r ~ F a y r- Q 0 ~ 1 lL + - r-' > 1T -< T 11 e y•• G e,•• 0 I d •• e U -, 8 II b ~ - ex --- (J - F E 0 J - .. ,......",., ,......",., 0 e • n 0 00 • -r n cJ> 2 E I n BLANK 'FF' Of Characters, Keystrokes, and Colors C-13 Notes: C-14 Of Characters, Keystrokes, and Colors APPENDIX D: LOGIC DIAGRAMS System Board (16/64K) .............................. D-2 System Board (64/256K) ............................ D-12 Keyboard - Type 1 ................................. D-22 Keyboard - Type 2 ................................. D-24 Expansion Board ................................... D-25 Extender Card ..................................... D-26 Receiver Card ..................................... D-29 Printer ............................................ D-32 Printer Adapter .................................... D-35 Monochrome Display Adapter ....................... D-36 Color/Graphics Monitor Adapter ..................... D-46 Color Display ...................................... D-52 Monochrome Display ............................... D-54 5-1/4 Inch Diskette Drive Adapter ................... D-55 5-1/4 Inch Diskette Drive - Type 1 ................... D-59 5-1/4 Inch Diskette Drive - Type 2 ................... D-62 Fixed Disk Drive Adapter ........................... D-64 Fixed Disk Drive - Type 1 ................ . . . . . . . . .. D-70 Fixed Disk Drive - Type 2 .......................... D-73 32K Memory Expansion Option ...................... D-76 64K Memory Expansion Option ...................... D-79 64/256K Memory Expansion Option .................. D-82 Game Control Adapter .............................. D-86 Prototype Card .................................... D-87 Asynchronous Communications Adapter ............... D-88 Binary Synchronous Communications Adapter .......... D-89 SDLC Communications Adapter ..................... D-91 Logic Diagrams D-l ~~~~ ;:;:;:;: ~~ ....;....; ~~ !£i!£i p ~ §~~~ o .... '0 ........ Q) Q) ..r::. en ~ ~ ~ D-2 ,.,. I~~ I;) ~I~ < §£:i oc Logic Diagrams N '" ,;. :; Ii I~ ~ ; Ii 'S ~ §:§: ;;: ;:j " " ~~ ~I:::l 1>l1;;;1~lg ::::.::::.::::.::::. - Ii ~ ;;: " I; ~ [il - - ~ ~ ! [il ::;: ~ .: ~ - 'S I~ ~I~I .: ~ Ii §[ " §:ff '" Ii .. . ;;: ;;: §[ ~ ~ ::l Ii §[ - Logic Diagrams D-3 ,. !!~§s ;r: !ff!!H:H!!ff@ !2:!2:!2:EE !!!!2: Ef:: ii i II ;i~~ ;;: ;;: ~ g ~~B~5 ~ I~ ~ § ~flE~~eE IIIIII '\ '\ '-- I~ !l '-- '\ '\ ~ = "= = "~J ~~ ~\~ '1: ~ '1: "'\ - ; ~~ .s. iii '" "iE- ~l=~ 1["' zl<: ~;:- >--= == 8 ,. ;;; c :! ~=~ It"' ~ l' ~ l' ~ ~ >0 !il = = ~ ;; iii I~ -N~i J _ ~ u ~ N COlI = c ~ ~ Ci = = ~~ ~N ~ ~cmu - ~l~ ~ !! S ~ ~s ~ e!ff ;;: ;;: e e ~ <0 .... -- " ~["' ~ l' ~ ; ~ ~ >0] _ co 01 ." o !Xl E QI ... "~cmu ::J~~~ -N "lj;I- =1 ~ ~ £ ~ ~ CD .... :~I:lm ---l-=~ -- g[",~l'~l'~:e >0 ",~l' ~l' ~:e >0 5~~ 4~= =oemu _ NI~I I- ~ 1 ~~~ =T~ = I ecce Ii ~~=:=: ;;: 0-4 Logic Diagrams :~ ... "'C ~ I" I" I" I" l- L---- l<:~ 1"1"- Of ~ = II ..c: ~ L.:::::==, L1----<,\ 1>- >--- ~",~l'il'~:e>o QI QI '\ '\ '\ '\ I" =~= -- - -- - -- ... M 1"-1>-1"- IE ~~ ........o o '\ ~~5!l~ I - " ~~~ ~ .'\ ~ ~= Cc -- i ;r: C - II; ;! !ff~ ;;: Ii ~~~< ~cc\:!;\~\;I~ c::>c:>c:::>c:::.c::>==<=> c:;> _ ~ I~;"~ ~ ~~ <'? ~ ---- §~cccccccd~ ro;~~I;~~I;;;~ ~I~~: O_N<":> .... " ' l Q .... c:;> ~~ ~><~~SSSS ...o ....o ""...
en ~ ~ co ... II II :!~:l8 1;!g;I~I~lili [~~~~ !HHHl1H'i~~ 'ili ~eee ff~~~§ee~ ~~ 111111 ~~~~= eeeeeeee 111111111111111111 Logic Diagrams D-5 1111111 111111 5 if L ~ ; r§=~a;:!ai§:; r I I :~;;:~~::~~<~~:i::i~~ o .- ~ Ll'l ....o ... .J::. rt _x §>< ill ~~ Q) Q) ~ - z~ en -~ ['l ['l ['l ~ ~ ~ ~ ~~~['l -- ~- x J,., ~WJ~~ ~[~»~i~ ~~ ..... ~ cc ~~ "-------L- t - N~~~=""':=-T=L" ~~I~~ ~I ~ ««~«CClt:lS -~~~~~-~"r-L ::::l 1i'ilrlllll~I~Ii'l ::!l!"";,~::l; ~; gc~g;,g:g~::; §§:§:§:ffi2 =:=:~=:=:=:~~ =:=:=:=:=:=::=:=: Logic Diagrams -~ -~ ~=====~== ~l ~ ;;;!; ....J «« ~ S N~ ~~ Ii " C<: ICO C ,.~~ 'i-~~1!:i 5 I'Ti Ii ---- E I E4'~--------~'~E -6 mE z.n ~ ~~ Ern :! !r;:::~C---;; ..:;;-n- - - - - - - - " - , ~! ""n II i!> !2" :~~:i;1~S B::::::::: BE ------ ~:;;.:c:!:t:! ~ iii ;;;; I! Ii I~e ff 1111 ~ fii?i Logic Diagrams D-7 .iJJ] c .- '0 ..... ... eLl eLl .r:. ~ . "'0 <0 o co E ... eLl en > (I) ~ ~ co .- -IIIIIII D-8 I111I1 Logic Diagrams ;c - §: ~ ~ ~ §: II Ei 'l ~~ !E ..,o~o i ~ I "" ~ [] ""'" ~ o~ :i& 0 .... 0- ... ig~ ..c: ~~s ill 0 CO ~,..~ := c ~ ....... 0 3I:ffiz ~~~ Q) Q) ~ ...ca "C 0 III E ... Q) ;;; en > (I) ::c: ~ ~ ... CO ~ I~ ~ ~ 111111 1~1~1~:!:i !H~ll!l~Hl~~ ~ ~ §: ;f = := i! i£ !1'f!2§:!!iei£~::2!2:e§:§: §: I; '" Logic Diagrams D-9 ~ - ,.~~ 0 0 0 01" !ll _ 0N ii;c ~I~, y~ " ;~~ - ~~ e-- I' § ~ "I ~I~~ "' § ~g~~gg",~~" gldSI~~';:; ,,~,,=,,~!"~ ~'r ;;; .,..oc...J if--'S!:c> I' c is - .19 -i is ~ ~~ ~ """"''' -N-~-~~i J,,~ I ~~ c ~ j!ii'itiH'~1i'H~ ~ii' ~iiliil~ ~ §~ ~ -.. ,% :!~~:::" N - "-LL ~ - Tl,. ~ ~ :'" ~- - ---- ~I HUbHtl ~U o-~ D-IO lJlllL Logic Diagrams ~..:>- ~I~=ttrrt ~~!~~!~~ I' ~=" [1) [II [II [II [II [II [II 111 [1) AI 02 A3 [2[ 110 CONNECTOR FROM BOARD IafS~ IIIQ2 ['03 [II 111 BDI~'OI COMPONENT SIDE OF IIIQ4 [1) .29 BD4 B25 B24 B23 J5 B22 "05 O2B B21 IIIQ6 [II [II [II .03 '02 A31 '3D '28 A22 111 [II .14 Al5 Al6 ----m---m- [1) A17 [II [II • 18 Al9 ------m' iOJi MEMII [1) MEMW [1) lOW CLK .sc TIC '" J2 J3 J4 A27 025 A24 .23 [1) [51 [41 [41 [41 9 [~ '" Al3 [1) .01 I/DCNCK I/OCHIDY RESERVED [1) [II [II II. CONNECTOR I62PII] JI AI' BD8 [II [11 [51 [II [41 [51 [21 (') .... .." .. .DO 'DO AD, '06 '06 AD4 'B AI. All [II .... o JJ. .., D6 D7 AD [1) ~ D5 [II 111 [II [II III [II 111 [II !JQ DO 01 D2 '3 D4 IROl O.CKI DACK3 AlE 01101 OR02 UIIQ3 [41 [41 [41 I a X1pu;}ddV A31 r---------PWRGDDD PI POWER .21 .20 Al9 AlB CONN. Ir:I ----m- POWER GOOD KEY +12VDC . -12VDC -------mI " --AI -svnc B141 --ai3 -----ail ~J BI1 P2 B201 ----alii --m .11 ---... ----ai'7 B15 B28 ~.O~[L CAPS ARE 8.2~ TANTALUM ON THIS PACE. rn o 831 15 CONNECTORS TOTAL] BI AESETDRV-BI9 DACKO DAm 1/0 CARD FACES JI BIB BOG B16 -- 16/64K System Board (Sheet 10 of 10) +5vnc II] S' S' e:!!£ !£ iil'~---;;; o ....o ...... CIl CIl .l: ~ ... "t:I '"o !Xl ...E CIl ~ ~ !.C LO N -.. ;g ! In l[ ~~ ~ 0-12 !~ I " Logic Diagrams I~ Ii " ~4~ ~ ~ d Logic Diagrams D-13 ~ :t §: 2: ! iii ....o ....o ... M C1) C1) .I: CI) "C .... ctl o co ...E C1) £ ~ <0 It) N "'"'- ~ ~~ S !£!£ §: D-14 1! ;:;I!!il~ ---- e~ §: ~=== " Logic Diagrams II cc " -- I; ;[ . - c c Iii; :Ii §:~ ;[ c 111111111111111111 Logic Diagrams D-15 IIIIIII 0-16 IIIIII ~c~~:t~:l:;;;; l'ieeE!ee :/:/;'''':>!i!i!il C::; =:=:=:===:=:E: i2fitifififi Logic Diagrams :::::::==f:l:f 2i;;~:;l:!;:g:g:; ::::::::E== i !! ~~~i ---- i E E-·-----E J~ I ill i§ ~ J J ~ f;j ~ ~ I ""6£" .. ~'~ ~ EgnX I I 0>" It" ;:; iii ! N N N ""£t" tt. I _ ~_St'n I ~ ~I~ lX)lt9WVII - ill]; I ! LSnX ...; .".Q ;;5 g J ~ ;; "". ~I~ "OX IX...... 11= .~ ~ ~ .... .., ..... _ f~~~~~~~ lI/~ i~· '''.y~~·~f~ ., ' ., " "' . aC!iI!Uii:~ ~;i;i;!i /' - ~~. I!- ---- - - N IlEIHI:!!i!l!iSli ~ ::::=: :::=:::!2: --- - e~ ~E!: . :!:::----:;lEE IE ~ ~N ~ I~ ~~ 3!~~ -- c iii i - f-- ::Icc ..- :Il:;l:'!:>:: ~N=§~=:i:l ~~==!I..., c .... c c e c c e ceCil'" :C:i!~~cc~ I "n ~ ~ ....... liit~l - ::l:ll:;l:'!:>:: 1:1= ,I ~ ~ EH5~lii":!:I::I:!::::; il I~ lii :!:I :I:::E lEa: ::l = I . ;;;,g g -~ 1,~ I 090X .!. CD I agnX emu"" ....... c:I:a::- l 1:Ut'tljJJ ~ rr- I. ~N I::; I ; ;; "r::8~lii:C:!:I::I:!::::; ~ ~ .."X N" --~ I :: ~Irl ,~m' ~I~ .."X g~ ~ I = i~ ~ ~~ ~""~::l ::u~::Je"" .... § _~,.N II ~::c:!~;::~ ;;: :::::::::=::::: ~ "" -"4,. :;~~S~;;:C;~ c ::=::::::::=:=:§: ~-~ ~ =5 ~~ i !'! ~ Ii !'! 1~15 §:~ Logic Diagrams 0-17 o IIIIIII 0-18 IIIIII Logic Diagrams 1 - ! - ;0 ;0 iii ~ 0: !:i 'l ~~ .::0 ~ .... ~o 0 ! ~ ... C I [] ,...., := ON ~ O~~ ~.-~ ~!l8 c ~ ill n~ ~ 0 CO .... G) G) ..c ~ ... "'C (Q 0 III E G) ~~ " .... '" > en ~ CO It) N ....... .;t CO 111111 :s 1=~ ~ = ;0 1 rl;OI!l,.:cg"IlIB1!I!ii!!~ ! ! ~ ......... ,... ... ..c ............ ~ ~ ; 12 !!ifi2!!i!i!!!!:!i!!!i2:!!!!i!i!! ;0 I~ .. Logic Diagrams D-19 ~---------J.," ",I I ;; o.... ....o .... 0') Q.l Q.l .r:. en f"L--======t:;1_." §~ Q .... a "0 .... C'CS o al E ~ '"> en ~ co LO N --(b D-20 Logic Diagrams o ....o ....o... Ql Ql ..c:: en . "'C ca o III E ... Ql £~ CO It) --;:z; N Logic Diagrams D-21 ill ;ij ~ .,,::; ~ !l if:.-u~ ;) ~~ ~;lS C$~ f-11"1 ~~ D:! 0: If : ;) ;;;;:;:! "~ 1 N ....o ~ "! " :! ~ '" ~ * iii Q) c. ~ I . "'C ca o >- ..c Q) ~ D-22 Logic Diagrams s ;0 13 if ~ ~ 5" ~ ~ i!l EEr-~~~ __________ I~~~§ ~ ~ ____ ~~" ~ ___ : ~I' , -) N .... o N .... .r:. ~ i:IIOI "g 0.. ~ I ... "'C "g «I o > c ~ if .c ~ !ol ~ c i~ ~:i W • >--11. §~ ~ ~ ~ ~ ~ ~ ! ! r r i !1 ~ ~ ~ s i!. i ~ Logic Diagrams D-23 ~I J c '" 'f g 'f tJ 1 '0 .- ... c I ~~ Q) Q) := .c:: ~ ~ ~ ('oj Q) ~ ~ "::l II;; 0. ~ "::l ~ := " Ii I::> :=1"1 < ")::L '-----+-------1IH1. D-24 Logic Diagrams I HfT--- ....... ~f tru ......o ~r t:1tJ .s::. ~t; C1> C1> ~ ~r~ f.-it" ~~ ... "'C CO o al r:: o ';;; c: l:l x w I I J I I I Logic Diagrams 0-25 M o '§';5 ... ~. Ql "C r:: Ql +" X W r------,'" "'= : 1 ~: I, 1 ~ 1 I, 1 L __ = '" r ----..,: O__---"'N'---..jf+f-t-j_l_< : ....._-I'_"-++H-1~ .1 ~----i",-'--1f+H 1 : .....~-J"--+-I~ rB" : ,~ L ____ J .- ...... ~~ " I 2i~ g1"ii""i'>"';;; MM'''';;;i''>MM ~'i: 'i:~!i: 'i:!i: ~e!":.eee !:!!:!~~~~~ Logic Diagrams D-27 tj • N 00 f_. n tj i' rn ISHT 21 1I0CHCK ISNT 2J I/OCHRDY (SHT 2J (SHT ~ (SHT ~ (SNT ~ (SH ~ (SH ~ (SH ~ (SHT ~ (SHT ij (SHT ~ ADI AID '1111 .111 ... A07 RESERVED B11B IR02 lR03 1004 lROS lROB IRQ7 12& 12' 123 122 121 DRQI I1R02 DR03 '111 A06 .04 A03 A02 131 A30 BIB A2t1 B11B 121 127 .2& '2& 12. B" 1211 801 810 831 AD AI A2 13 (SHTll (SNTII (SHTI) (SHT II ... (SHT I) (8IITI) AI. AI! A13 A14 Al5 (SHTII (S.TII (SHTII (SHTII (SHTII (SHTII (SHTII (SHTI' )SNT IT (SNT 11 A15 A14 Al3 Al2 A17 AlB Al9 (SHT~ (SHT~ (SHT~ (SHT~ .23 ... 04 D5 DB D1 (SHTII (SHTII (SHTII (SHTII (SHTII (SHTII (SHTII (SHTII 00 D1 02 03 .22 121 A20 Al9 Al8 A17 '" BI' 813 812 811 120 127 8112 819 Bl7 82& 815 828 A6 AI AI AI 'ID .11 AI. ... ilif iiiW ii!MlI )SHTII (SHTII (SHT II (SHTII (SHTII (BHTII (SHTI) )SHT II (SHT II (SHTI, (SHTII (SHT II (SHTI) (SHT II (SHTII (8HT1) )SHT I) (SHT1) (SHTII )SHT I) (SHTII (SHT II (SH711 (SHT~ (SNT121 (SHT 11 MEMW (SNT~ Cll( TIC RESET (SHT~ (SHT~ (SHT~ (SHT~ (SHTII ISHT~ (SHT~ (SHT2.11 mKIi )SHT2.11 ffiiIT (SHT ij DOCK2 nm .LE (SH12.11 (SHT~ (SHTII )SHT~ (SH7~ )SHT~ (SHTI) (SHTI) (SHTij ,... B-SHELL TYPE CONIECTOR H ~ ~ u " ED7 (8HT2.11 '1111 (S'72.11 ED5 ED4 ISHT2.1J (SHT 2.11 !AlB EAI8 !A11 EA16 7 8 £A15 11 EAI4 !A13 Ell2 !All !AID !A9 ~ a ~ II '1111 (SHTII ~ E1R02 E1R03 E1R04 !lR05 EIROB !lR07 (SNT ~ ,.. EA1 EA. !A5 ,.. EA3 EA2 EAI EAO !Imli mm mm - EOACK3 rnMii !1m IiDIi EALE EeLK ET/C nmi' ~ U 11 22 ~ Y 12 n a AD M u U U I "" "15 • ~ I .• a 2& 23 2 H (8KT2.1) (SNT~ (SH72) (SHT~ ISIIT2I (SHT2) EI/OCHRDYISNT!) I1irniCI{ (SHT ~ ERESERVEG ,SHT21 E ORO! (SHT 21 'OR02 (SNT~ '0103 (SHT 2) !1111 (SNT~ 18 "MIL' (SNT 2) » -~ M 2& U 2& 5 U H 8 AI Y 1111 II D2 Extender Card (Sheet 3 of 3) (SHT 11 (SHT I) EDI '02 ID 11 9 CARD EDGE TAIS '03 lM'M.lH 'X'.(SHTII ;! C» ~ ~ ~COClClClC"::::"'><::>~ ~+J-.I.-j..j....I~~ ~:~-,' M .... o ...... C1> C1> ..I: en ... ... "'C ca U C1> > "(j3 t.l C1> CC Logic Diagrams D-29 -------- ~!i!i a!i ~!i!i i! ;; ~:g II 8~~ ~ _:;i 0 ~i ~ ~ ... Q) > "a:; tJ Q) a: .; ~ ~Olct {" - 'I' - e D- 30 Logic Diagrams "" ct ; " a " ct " -- . "'" ::" ".::" 'n::" L..·::" '~::~ ",...., ~ rU -, I l____~..; ,",it! !ill ~ '" .. ,~ ! " ... CI) > "~~ F~f& .~ .. CI) a: ~I' ~ ; " I ~ Logic Diagrams 0-31 Ixa. I. 13 "' .. .. " 11 H5 ID . CM CM CIIS 7 ~ .r--- ~ 7..-- ~ ,,..-.. 1M " I ~ 5r--- IDr- HI " .r--- ar--- , RI R ,~ .. .~ 5~ .C 7~ AD HI III eM 20 .,• RIO 132 ID ,. 3 15 11 17 '5 eM 18 0-32 ,~ 11 11111 R4 ~c:Lg:L~ " ED 0.0111 15K II VT • BIStr- " " . 15 11 17 .. - lO 0.0111 -f DADBOI 3rf"D+:Oll C. er+* : C. " 5rf-* Clit: 23 I {vID ~II ~ 1'0" '-; . I ,1 !... I I I I lO5 c. ...I ~13 Oil .. 'I" ...... ~17MI, ....,,, 2 AUDl-24 " D ,. ~ D.' Ii~ ,, -'" ., "'l lD. :J ssm. 014 LFO AUDI.2.] ~ f~111 25 LFI LFe " I O!ll LFA I!II ~;13 5W ~I 1"'017 13 5W ,rf*'.,, art* ,, ,1 L IC' RI' I!II DID 3 ' 01. 1.21 A 85277H +C. O.Olp "- B2D ID ....,,, ILF I• om oft II 20 Dl3 17430 "~ " "'---".1,....,c""l- - el15 111 11 I V., T (016 '"'W SOL L----: SOL ... ., IIA, .~ ILF H IS2015K Vee LF C G, I, [" Dl5 555 "015 CMU eli 13 iQ • .~ ... ....,..,.~ HI Z1I4 ••ow ~8V+ I LF LF 0 H DI UK 1I.2-3~ • H6 Z1I3 lII7 UK ...ow LF A Clii ~ n ...ow CI5 H5 res • v, W le. r' if 1~II r~ H12-8 .A " ~ H• *~DI' '5 CM 19 ~ 1 .."' .Am ~ ~ ~ ~ 100 17 DC De lID _ 1~· ~ ~ * HEAD AIIOI·2414 lIIl H25C·l ATD TRIllER Hl(U) ~ !2. ..... 01 .,..-.. H7 " 11152771 •• ,-3r--- OJ aID :-l T 10,. 16V mE=~"t=================================: ala lEo Logic Diagrams OPE 18 Printer (Sheet 1 of 2) !O\ :: /~ -\ Al 094 llLIL R38 2.2K 184B1 8 7C c~.r- 1500P :~""'~'3 2 7C 7C 2E I. ~tl~lO~C" T 4700P '~E ~ 8 137 PeD 21 38 PCI PAD 22 23, 1 24 2 25 3 4 2fi 27 5 28 6 14J 15 CNS 16 pea PC2 7 11 18BI BI55 '5V !}N4 RMfi.9 C12 101' .......:.:40'-_ _...,20 ~r v.. 6 v.. S R26 C 6MHZ~ 21 &7 I" .......,.tXI CRI 13 12J IB CN5 22 X2 -2 10K RIO M 1.2K 10 P17~,~~-4~~8-- '~°___ir-------, " 6 DBD Vee PIO 27 CRB 8~9 Vee 24 GND O.Olp 8039 12 ':" Vpp 233U2716 1181 #2 'S '24 21 ~f ~ 20 DE AD 1 2 3 4 5 6 7 8 9 IDes 8 7 6 5 4 3 2 I 23 22 9 18 910" 13 14 IS 16" ,VCCDO 1 2 3 4 5 6 7 B.Ol 12 ':" 24'~_L.9:.l.:':J0 Vee 00 I DE p20 O.Olp 1 2 3 4 ~ 6 7 B 9 1011 B 1 6 5 4 J 2 123221918 12 GND AD I 2 2 3 4 5 6 7 All _~~O 27161281 DE 3 4 5 6 7 0 9 10 Ce liliTsls R3I 43212322,918 945121311 CK A 0 COl'" l~~~5 'I ClR QA QBQC60f 9 512~3 4 CK ABC 0 l~2~~5 ClR 357 /2 1113351 6 05 IJ6 UI lS361 i3AI Gill 6A 68QC60 2 710 IS 91113 '01 2 3 4 !I 1 2 7 lOIS 2 4 J 5 lS367 14AI 4 10 2 3 4 P11 28 CRO 5 12 6112 GI p.' !31 ~ ISY P13 12 14 2 4 6 10 15 +5 ~VOO R18 12K 21 22 23 ,.- CR8 19 s~ 10 5~ H32 ~').4_--',f~---......!..,11'o.J 8:- 29 f:~t 7D~ " Pl6 8 12 i>.,.--~--------------c lFC ~ 7E 60 6 ,4 4 70 0-"2-4--------------0lFO $lt():-;,,---+------------- 7E=----'--"--+_--' Vl2 CN4 13 78 1127 ~~ L-________________________________________________________ ~~---- -----------------oi 1S' " Gl \~~lP~~_;lI~NE~l~P~l~P----~II~.,~'~W------------------------------------~1 OROWN BLACK Printer (Sheet 2 of 2) Logic Diagrams D-33/D-34 .... ....'0... Q) Q) .c (I) ... $ .: Q: ~ ~ ~~~ en = . . \D'" }::l'S. _ ilHli :0 i;il Logic Diagrams 0-35 ~ ~~~ '" iii ~ : : :l !! ~!!~ N N;;- ;;r;;r :- : i iiii i ii ~" ~" ~~ ~ ::: !i1 :! :; :! ::! c c c c C C C c ? r' '" ~ ~ ~ ,.,. .- ~ ::: = ~ ';;;0" ; '" '" -.~ -. ~ > eo 0.. '" C Q) E ~ ..c: 0 0 c: 0 2: lHl iii;;;", '~" ~~ ~.r-E . ~~ ~ W" D-36 Logic Diagrams ~~~ ;;; ;;;; 6~6 ~ ;.'"riO ; '"riO tH:~~g ~tB~E ~~~~ ~~~~ ~ ~ i ~I~I~I=I ~I~I~I=I ~ I€€€€;; I ~€€€~ ~I~ "~<:l ;::l::!:;:::'1.iI!>I::l :: 11~ ~:;;:~~::::~~<~~I~I~: ~ l~~ tt~1ttr[rrt ~=~~ ~~~~ ~~~~ ~~ IIIII~ ~ V ~ I V " V -~€€€ '7;i~tF ;; - ;; ~1~"~<:l:::::1::1:;::: '1.i1!>1:l ~ !ttl:tl-mr~ ~ l::l VJ It~~ IIII ~"~<:l ....o Ie'-- ....o N .... 1;;1 ~;~; ~j;~ (~ :::::1::1:;:::'1.i jliJ ,'.im ~iJi~" ,' IIIII <'-+- ~tS= ~ ~ ~ s ~ ~ ~:c~~:::~~<~~I~I~ ~ u 111 ll-T § ; ~ ;::! ~ ... CIl 0. ~'" ~r;;, ~::::~:::i41~::::~~:::i I~:: re;;~r I' -~~-~~- _N_~~_~~~ CIl CIl .c -~~t ~f ~~~~ > '" tn'(ii;r.>>n ~~~~ ~~~~ "5. en I;~i is CIl E I· ...o .c t.l o c: o 2 ~Il-~-~=~~ ~ ~ :;;l'l~ ~c~~:::~~:c~~~ i :E:E:E:E:E:E:E:E:E::E; ill g;;~g~:g:g::;:; ~~~~gJg;n;;:;~ ~~5i~ ~~:1~ !~~~ ~ ...I~I~Ir5~~ L---1I' == = '" '" '" iO = - - '" - '" - '" - - - '" iO ~ '" ~ a ;:!;~ gj""~ - " , ~;; iO " '" ~i roo !>~~ . -1~C=f= 'f " - Logic Diagrams D-37 o >SV r I ~ 00 J1o-~---+--~ ~U.PER (SNT 11 +RESET +JUMPfR t-----~~------~--------------------05 n~~~ffi~~~~ff=~~~=~~---------_CERO. t"'" o .... o (JQ rl-J.++-h~~~!..I-U:t==::::::lfu2') (') JJ. 9 ""I til (SHT1) (SNT 4,5) (SHT 10) (SHT 5) SII (SliT 101 -WE (SliT 2,8) (SliT II·RESET --~+---------~w::t::==Lt (8NT lj·MEMW ---,,=0-+-------.; +CACS CC[K (SHT 21 1::i:1 +CCLK =-CPU MSEl ·celK [SliT 5.101 (SliT 21 (8I1T4) ->ti845C~E ~~S~~======~ll ·XACK TESTOSC:===+==+===!j (SKT 7J -HRES +XACK (SliT 6) +10 READY (SliT 1) [SKT 2J HA3 [SliT ZI VSYlle ~~§~~~§§~~~~~~~~~J I [SHT2)HSYNC ISNT 3] + CCLK ------,..; .5VI-.....~~C:J Monochrome Display Adapter (Sheet 3 of 10) DOTCLK (SliT 7.101 RoMAll [SliT 10) -elR VIDEO (SliT 5.7.101 ·CURSOR OlY [8KT 5) ·DlSPU OLl (SliT 7) +OISPEN OLY (SliT 7) +CURSOII OlY (SliT 51 +HSYNC OLY [SliT 4.71 +VSYNC DU [SHT 5.7) .'" _ ~ "~ ... ... ... ~ !i; ; ~ il~;~ ~ .... f; !! m c a i;j m m m " ~ ;! l:::~:; ,~ ;!:a::~ !5 -~-~-~~ 'I' o ........o <:t ..... C1) C1) ..c: (I) ... C1) ..... a. CI:I ~ >CI:I is. In i5 C1) E ~ ..c: u o c: ~ ~ -- -- ~ ~~ ~~ . -~ !i; ~ -- ~!! ~ ~~ ~ ~ ~ ~~ ~ " ~ ." Logic Diagrams D-39 i= ;a '" ~ - i= ;;;- '" ~~ ~ " ~ ~ ;! ~g 0 '" .... N iN' ~~--~ ~-lll[[[[ ,-- J( .......o o l )l )l ) ... CD G> G> ..c:: ~ ... G> 0. <0 ~ >- c.'" '" is N N _ _ _ _ "' .... E o ..c:: ... u o c: ~ ~ ~~ ~ Logic Diagrams D-41 • ;.'" ill ~ ~ -... 0 0 r-. '"'" ... ...'"0.. ca .c ~ ~ >- C_ J ;g "'C "L, - -- ca a. " is'" >- ~ ~ ~ '" E E ~ .c tJ 0 r:: 0 2 " ~ :J- - ~ N~ - ~ ;;0;;0«> ~~~ D-42 ~ ~ S~ ~ '" . " " -n ~ ,. -, '" - Logic Diagrams '" " "'" g ~ ill 'l' ~~ ~ ~ '" '" '" " ~~~ " ~ ~ ~ 0 '" '" ~~ - - " '" ~ " u ~ ~ -" " ~ ii: ~ ~ ~ ~ -IHI' ~~f,~ - -jHi' ;g" ~L-t ~ - --+---< ...o..... o CO .... G.> G.> .J:. ~ ... G.> '5. ro ~ >ro Q. 15'" G.> E o ..cu o !: o ::2 IIIIII Logic Diagrams D-43 ~ 1i! i: iii ill iii illl i!.1 ~ ....o ..o en .... CI> CI> l<3 l<3 ~J ~4ih .s::. ~ ... ~ a. co "0 « > co C. en i5 CI> E ...o .s::. c..I o c: o 2: ~ co _ .......... o.n <0 ~ iO '" .... ~ iO iO '" "'" '" "'" ~ ~ '" Logic Diagrams :I'~~ ~~~~ !'! '" '" ~ ~ 0-44 ~ ':' ~ '" iO iO '" '" - ~ ~ ., iO iO iO ~ ~ '" ~ iO '" ....o... o ~I ~ ~ " ~ c ~ N ~~~ ;5 c ~ ....... z ~~~~~ u...t!:>~ - -- - j - ~~ '" ~L,I' ....o... CIl CIl .r:. ~ .... ~ 0- '----< eo "C ~ ~I :IE -- ~ g 5 - -- - - ~ ~ II) g;g:g:g::; is g ::;",,1 ~::;~~~~~; ~:;;:;;;! ~ eo is.. .n..,. "" N ~~~ ~N~ CIl E E .r:. t.l o c: ~ N ~ ~'" ~ - -- 11-' , 'Tm:ITI'( " N N N N ~ ~ ~ N '" '" '" '" Logic Diagrams D-45 iiiiiii = = == = = == i Ii .. . . III II Z l!I Ii !i~~~ ; ",~,i~ -.... CD o .. ....o ·2 DIlIIIZ8l!1~~~ D~II:Gl!I~~~ - --- ~ - - ~ ~I~- .~ .s::. Q. I'CI g.. iiiiii ;i;i;:;; !1l~ gD~=ZI!l!IS=ml~w~~~ ~ D-46 Logic Diagrams i!I o 8 ~--~5~ 1!iI-''''''>~>DG .... ~~~ U; " ~ 5= ~ 'm 0J' <;>'f';' ~~~~2 5 ..li = " <;; If",,- ~ ~ ii:a;~~=:gijd 1 L ,::::' .1 11 :rm Jf L~ - ~ " ~: dS 'I~~;i;;;~ ~. "- -.• ~~ ~~ ~-~~ ~ ~ " ~ ~ ~ Logic Diagrams 0-47 ... ........ ...; ... ...; .......... ~ ~~~~ ~~~~ ~ 8&a.i ~Nia +++- +qo .......... ~~ ~ ~ ~ ~ ~ , ~ 5= ~ ;:; ~ !l! '~"' !i~~ !i!i~ 51 ~ g !IIO~ ~" ¥~ ~ i ;i~ Of -.... ~ i:;:li:;:j~ C?O?G? ~ i'i ~ -f ... ...Co o :2: '" !:! .s:. Cl. ~ --... C!' o 8 ~~~ ~l =~~ ,,'r,; _ 5~ m", I N_C> 0-48 Logic Diagrams ~ 1'1'1' -:' ==~ = N~'" ~; lii ~~~ lii lii lii ili ~ ~ :::i ili ili ili lii '! ... ;~ lii ;; lii g iii ii ~= ~~ ~~ ~ l' ~ ~~ ~~~ ".. ~ ~ . ~ "~ ~~ u_ ':' 'I' i;;a o:;:'IIi" '~" ll;;a iii :~= ~~; ~~ . 'f'f lit, ~ t "'?IIi" . ~;~:: ~~ co .... o "'..." CIl CIl ~ en . CIl E- .'"o "'C CI> ..r:: ~ ... ~~ ~~~ ~~ ~~ ... CI> Q. co ~ o '--------, .!:: c: o ~5~~ =uuQ... ~~ .... N<'>_ ..... §~~~ ••t<.~ ~ en .!::! ..r:: Q. ~ -Co!) '\' (5 8 _~c;~s.~gg ~~ -~SC!;:g:g~d MT="J"'r-~ • N ~ - ~ ~ ~~ "~ " "" • 1 ~ ~ ~ ~ " ~ D-50 Logic Diagrams ~--~- COOCOOCOO""COO~!3: ~ ~ ~ 1); ~ ~ 'f :;! ..; ""COON ~ -----i~i~i iii~~~i~ ~ ~1~;~~~~~~~~~~~~~~~~~~ "" ~ ~i~ ~ : ~ " U) ....o ... U) CIl CIl ~ ~ ... ... CIl Q. CQ ~ ... o .~ t: o ::2: N .... <0 OD o IF = I 5. .I.CWIIIIIIGINFDRMATION PUSE= BLACK/BROnWIRE I L__ l~~E_J "fUTRAl- WHITE/BLUE WIRE GROUND = 6RUII ""0 YELLOW WIRE Tn ~"ASf WIRE MUST GO TO THE FUSED SIDE OF TflANSFORME IM~ORTA"T, t;; ~ ~~~~;~~~~~~~~¥7~9~~~~9~~ c " "i i!1~ " " C " ~l ~ L--... ca "C ,if l§, ,-lH ~ ::~:~I~,~jk j~ IT~g=s:~ :~ g~ :1 ~i ~ ~'----------'Jf ~I /7, ~ ~~ l ~ I !!~ ; "'" ~~ - , .wi g",~gW :gg~l ;; .. N L,...~~~,....;;' -: 5i~~. ~~~ :.--~~! ; ~ g=sa~~l!iO;~~ N_ ~;;' -- ~~ ~~~!fHiil~ ~ D-56 Logic Diagrams -:'1 ~ ~ = ~r ::::> ~~~ '\' '=~~ = d ~L -' § N s w -, E D-58 - ~ ~ ;1 < ~ ~ ~ -w-I ~ c N ~H~5 § 1 ~ I L __ ~ § n ~L, =GL-.~ ~I i'i , ~ :1 ~ - - ;l~':i" ~~t- ~ :: ; ~~ ~ ~~ ~ >< ; N - H= '~~~ -, ..,. -~~ ~ 1li § ~ " ~ te N N :~I' ;1 +l2V -,., TP10 III ,PO b .... (JQ • I 116.1 JI J2 .1 .. SIDE ONE .5V (') o ;. II (JQ "1 a ~ ., .- 11] I • I ~l 11 -:LS14 NW,,2 1I 'I WRITE I ~ ~~~____~5~~~'________~ DATA o I Ul 1.0 a x!pu;JddV 11K ., 6NOI31"'" !! 2F 'PI 150 • ~ 5-1/4 Inch Diskette Drive Type 1 (Sheet 1 of 3) ., '26,C30. '38,1'311 '-' ,., " .. GND o. 0'1 o ~ o (JQ INDEX! SECTOR PHOTO ASSY (;' o-, ~ .., ~ 3 til J1 DIRECTION 1181 UTEPI 20 I 3Lf. 51 '+:r "I 462 NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTORS ARE IN OHMS. 1/4 W, 5%, 2. ALL CAPS ARE IN tkO. 3. ALL DIODES ARE IN 4446. 4. ALL TRANSISTORS MPM ARE 2n4124 iii PNP ARE 2..4125. 5-1/4 Inch Diskette Drive Type 1 (Sheet 2 of 3) ~~ ~ .... ) I I - ~ + "" ~ ::;;:; ~~ ~~ ~ ~~ y~~ ~ I M ....o ... M Q) Q) ..c: ~ Q) Q. ~ Q) > C ::: Q) Q) ~ '" is ..c: (,) c: N ) Logic Diagrams D-61 ,r------------,, r"'""--1~---, r-~n : :~ ~ ~l~~ ~l '~l ~l~~ ~i ~ Lt~", ;g ~ N ~j'~~ +" ~i:!' -"0 N .- ... CIl CIl .c ~ N CIl Co ~ CIl > ";: Cl ~CIl ~ '" C "fis::: ~ .til D-62 Logic Diagrams N ....0 ... N ~ ~ .J:. ~ N ~ a. > I~ :::;~ > C ".: ~::! ...... ~ ~ ~ en C .J:. U ..: ...Ih ~ ~T ~ ~ ~~i Logic Diagrams ~1 0-63 . Ql Em ~ .:: Ql C ~ CIJ i5 "C Ql X u:: ::;:: ""' ..... C"> ... "' C 'i: ~ is'" 'C (II )( ~ Logic Diagrams 0-65 i ~ ::l ::l i't ~ t;: ~ iii! !i T ill ~ cC ~:;;: Ie (l) '0 ... M Q) Q) ..c: CI) ... Q) Em ~ Q) > ";: o .:t:V> i5 "C Q) )( ~ 0-66 Logic Diagrams ....co0 "'..." Q) Q) J: .... ~ Q) Co (0 "t:I "i:: " ~:; ~ ,. "'f ~ :::; ~~ to ....o ... LO Q) Q) .j; en ......a. Q) ";: o .:.: is'" "t:I Q) X u:: 0-68 Logic Diagrams !H!iii =!illl ~ " cc ....o CC ....go "' :.l~ i go .r:. ~ ~ "- go ....Q. " <0 "'C ~ go > ";: C ~ II> C "'C go X u:: I " I :;; ~ ~ 17 " ~ i " ~ . ii ill g ci '" ill Logic Diagrams D-69 M .... 0 ....... Q) Q) .c: ~ .... Q) 0.. > IQ) > ";: 0 ..10: 0'" "C Q) X u::: +~(!H 0-70 Logic Diagrams ~ ;; ~J +!!~ M ....0 ... N Q.) Q.) ~ ~ ... "'~ ~: Q.) Co >- IQ.) > ';: C .lo: " ~ 1<\ is'" 'tl Q.) ,~ u.. ii i~ , Logic Diagrams D-71 "..~ "..~ i£ i£ -... M Gil! 0 M Q) Q) .s:. ~ ... Q) Q. > IQ) > ''::: C ~ ". i5 "C Q) >< u:: 0-72 Logic Diagrams ~~~ B~~ ~fiij t:i!: 5~ ~~ M .... o C1> > ';: C .!JI! II> o '0 C1> X u::: Logic Diagrams D-73 (I) Co > I(I) .~ c5 ..:.:: en is ~ "C (I) x u:: 5 ~ ~ ~ "i . ~ ~ g ~~~~ ;;:;;:a::;;: D-74 . a ~ ~ ~ ~ Logic Diagrams . "~ ~ ~ ~~ ~ " ~ . M .... 0 ... M ~ ~ .s::: ~ N ~ Co ~ ~ .:: 0 ~ is'" "0 ~ )( if i.i: :,; "' ~ Logic Diagrams D-75 - ~~ §: '" '" I; f:ll:i ~ I~ NN '" II ;! ~~ \'il = M .... o ~ 0; 'I -~"~:l- - =!! ~ - ~:: U'" c:ci"" ~-- iil,"~g; I .... ... ~EM m= ,. c~ '? <-< "".:c ~"" ~ ~ ~ .s::. ~-~ - ~ M " Lj ~ L--- N M ~ ~~ ~I-- -M- - --.'N ~ ~~ ~I ~~~~ ~~~~ ;! - o c~u" Tl~" ~ ;;;; "';:; a. o c: 1- -,II o L-- ~"lU ~~ < c < c< c: ~ ~~ - - -~~ ~ - ~ = ~!';l ~~~I I <~U ;! _ N M ~ "lill1,l ~ ~t~,. a. '" -- w o>E ~ lL - ~ M ,. " ;;; '" ;;; ~--~ ~ ~ D-76 Logic Diagrams x ~ ,. eeeee c: g 1~ ~I ~~~~ ~ ~~ ~ = "Vi I!'" i '" §: ~ \'il N M ~ f; ;:1 I ;, ~c ;, ~g M .... o ... N Q) Q) :~~ ~OOWWVIILX)l9L "';;:I~ "<~!;I:;::I:i!I" - r. ~ c: §~ ~ DOWWVII!X)491 ~~I~ "<~":;::I:i!I" ~~~( ~ ~~~~ ~C+-+----+,,, o '';::; c. o c: o 'U; c: Ol c. )( w o>E Q) 2: ~ N M ~ g;;;;~g;:g;:g~6 r; ~~ M "'-~'" e:, ~ I; lili I~I~ c:; Me;;' - !!:.~ ~::;::;;;:~~~~~ ~~ c:;- ~--~ ~ ::;~~~~ O;;; !! ;;:;; ~--~ Logic Diagrams 0-77 -M o M ~ ~l ~~f-< Ii! i === == '\' ~ HNO:J 1903 OIlV:! ! if ~ o ,. ~ " . '"'" ..c: ~ c: o "';::; Co o c: ~ :il ". ~ ~I .... o !l ";;; c: (C :! y "" "" !'J :: Co ~ " i'l >< W > o E '" ~ ~ I~ N M ~ -' L -'L " ~ II y" " [l .., f-<~r-- y y I:l rHh-~r. " ~r. rJ 0-78 Logic Diagrams N __- - - - - - - - - - - - - - - - - - _ N ~ f!! ~ I~ I~ I~ I~ liil~ I ...o M ... CI) CI) .l: ~ I: o ".;::; c. o I: - o "iii I: ca C. x ~ W - ...o> E CI) 2 ~ - N ~ ~ ~ ~T- ~ :1-'-:.. :'\!' :,\:.,,~~\ ~ cg c ;;; 1 ------- " " " ' . . , . . . , .... c::><;n :c;:c ;; ;; ;; ;; c;:; '" CO> ~---~ II'" " Logic Diagrams D-79 I~- .. i=i= =~ I I .. 1 .. :;; :;; ~I ~ g: :ia; :iai ;0'" caz ~~ S cae ~'" ~ 9 iii C""YQ ....... CI CI o,.=.p - ~~~ ~~ 5 ~ ~~=N N~;; I' ~ I~~= :;~ " ~ ,---- ~ ~ ~~ ~Sl~ L. M ....0 N .... Q) Q) .I: c\y~.1l~c~~~~~. ~~~~ -~ ~~~c~~~~~~ ~ "~ ~~~I~ll~l~ " ~ ~ C M 0 '';::; c. 0 - c: 0 'iii c IU ~~ L=t 8 ~ 2: ~ ~~ ~'t L- ...0>- 1>--- ~r~~~ ~~N~i ~ "08~ :5 ~ '-,---------> ~~ " C. X m~I ;: ~~~ ~ >-~~;! .... :; ..... ;:!~~~~t:!!i~::;~"""", ~ c""~:e;:!!i~:::::V.II"" Nlltl=I9"I" -~I-NiI1"'l=i"il."1'" _11Hlll llill I_ ~ f- ' ---H'-- I§ Ii I; ">---H--M ...... o M .... Q) Q) ..l:: !!! s::: I o 'E- "DO 190J .." o il...jf-.!>-H-'fl s::: o 'r;; s::: ca Q. i'i04I--...Jf--!l X W !l.,I-->-lf--i'i >...o E Q) :2: ,'H I-- >-l f-- " co iHI--...j f-- il ~ ~ HI--~H; ;; ...jl--~ f-- " fl...jl--~ f-- to ;$ ...JI--f-if--!l 1l...J1--...Jf--::l iHh...Jh1'l Logic Diagrams D-S1 '" '" c ~ I; ., ., N& ~~ I~ I~ liiil~ ., ~ I~ ., '" ~ I~ I~ N '";; " I~ ...."'o" ....... a> a> .J: ~ c: o 'E- o c: o 'u; c: ca C. x w > ...o E a> 2: ~ co It) --;g N D-82 Logic Diagrams " ""1 "I~ij - 1 - _.. uruw - - ~ ~ Logic Diagrams D-83 L g ;;- !!I a :!; :!l !l ;;oT g ~ . !!I a ;g :!l !l ;;0 <:t '+- o [ L ~ .. I ;; g ~ l! I ;; ~ I I ;; ~ 'il ~ I ;; ~ ~ '" '1i "~ i~::!~!i!:CI;o .... e:! .... _~ao ~ .c ~ I I ;; ~ ;; t: I ;; ;; L !:I .. ~ I ;; ~ I ~~ CI) ;; I ;; r: ...., M ~ gj 1 c. ~ o t: I o .;;; I ;; g ....o t: ;; ~§ oo~ lili!~:C:C:1::!~!i!:CI;o - --- I ]7 '" C. X W ...o>- E CI) :2: ~ u;) It) -N ;;::: 1111111 D-84 Logic Diagrams II I II I ~ 'I' He: ~f-, H~ f-H-'" ..,1f-"ll- ..,tf-"lt- Hf-, f-"lt- ..,tf-"lt- ..,1f-"ll- ..,tr-- < W . >o E r-- "11 r--Bl5ii " 814 813 A31 7 ill 33 ~ lOW I :, :~ "2 'EN ." A28 A27 A?~ 22'E1A HI He !!!..!IT..!!..fzo 2Kn Hl15 EIA RlS 14 RlS 32 :! A5 .Ill SIG GNO'7 ',l LS30 '5' -ENABLE -;~~1ft:ir I~ 1 A23 +RE~~ ~~ ~:i: 12 -Rev Cl RET RECEIVE DATA Asynchronous Communications Adapter (Sheet 1 of 1) L-_~ N ....'0... Q) Q) ..c: ~ ... ... Q) Co ro -c ~ U> c:: o ".:; ro tJ "2: ::I E E o u U> ::I . :e. ~i,:B'~ ~~ , o c:: o... ..c: tJ c:: 6i ...>-ro c:: iXi Logic Diagrams D-89 .,. c: o 0';:::; fl 0c: :::l E E 8.,. :::l o c: ~ .r:. t.l c: > en ...> o:J ~~~~~~rn 5 D-90 Logic Diagrams c: ii5 ; e tL i![i --::: : .... el Q I h .... s~~~~s I Ie ~= a~~; ~g; ~ IH~t Ie Q Q ~Ii:i ~~ ~1 ...... c e l l c -:::- Q= iff f!'~ >l! :l " I ~fflr~ ~ ifI c.:IU t;~ r1 ~i::~~~:i L-- Ii ~ ;~~~ I- I e Ie e IQ I N "fol "fol .............. ~~ ,J ,J ,J ,J r---, N~ I ~~ ~~ ,J :;; l" 1I il'lf:! lil'lf:! il'liii~iiilil'liiij il'lf:! ,J e " !i! .. ~ ill~ 1:::;~!2~ ~CL.CL.""'''''' ~~ ::: t ~= c.:I Cl: z .... 1.1:0 Ii! ~~l" c :C0l!:1!:j .................... N .... o Q~te~ ~ .......... "'j'! ~18. ., ~ e i~ :;~ ~ U) Vol c.:I ~li!i1l :;~ g~ t: I J h Q s~~Q ~ ; ;1 r~l o .';:; iii 0.125 + _. 005 (3.175 ± .127) = iii '" to 00 Copper Pad ~ (To Ground) Switch Block 1 I~DD~~DDDD I Switch Block 2 I~~~~~~QQQ I (JQ v.> 32K Total Memory System Board Switches Switch Block 1 I~DDQ~DDDD I Switch Block 2 I~~~~~~QQQ I 48K Total Memory 1 System Board Switches -- --- - Switch Block 1 2 3 4 5 6 7 8 mD~~DDDD 1 Switch Block 2 2 3 4 5 6 7 B ;~~~~~~~~ --- 64K Total Memory 1 System Board Switches Switch Block 1 2 3 4 5 6 7 1 6 mD~~DDDD Switch Block 2 2 3 4 5 6 7 B ;~~~~~~~~ 96K Total Memory 32K + (64K on System Board) System Board Switches Switch Block 1 I~ODQQDDOD I 64/256K Option Card Switches I Switch Block 2 64K Option Card Switches I~Q~~~~QQ_~ 32K Option Card Switches I~~~~Q~~~~ I 1 - 32K option r.tl ~, ..... (') ::r r.tl ~ :::: 5' (JQ rI> 91.0 D X!pU~ddV o - 128K Total Memory 64K + (64K on System Board) I o rJ} ~ ~. System Board Switches Switch Block 1 I~DDQQDDDD I Switch Block 2 ~~Q~~~QQQ t:r' rJ} 64/256K Option Card Switches (1) ~ 5· 32K Option Card Switches I~~~~Q~QQQ I OQ [Il 64K Option Card Switches 1 - 64/256K option with 64K installed 1~~~~Q~~~~ I 1 - 64K option I~~~~Q~~~~ I I~~~~QQ~~~ I 2 - 32K options - -- l60K Total Memory 96K + (64K on System Board) System Board Switches I~DD~QDDDD Switch Block 1 64/256K Option Card Switches 1 - 64/256K option with 64K installed 1 - 32K option I Switch Block 2 64K Option Card Switches I 32K Option Card Switches I~~~Q~~~~~ 1 I;~~~Q~QQQ I l;~~~Q~~~~ I 1 - 64K option 1 - 32K option I~QQ~~~QQQ I~~~Q~~~~~ I I;~~~Q~~~~ I Vl - I;~~~QQ~~~ I 3 - 32K options :.E ..... ( ') I~~~Q~~~~~ 1 t:r' Vl ~ :::: iJ' I:Il o I D x!pu~ddV o - 192K Total Memory 128K + (64K on System Board) I N til .... .... ~ System Board Switches () I _S~itch Block 1 ~DDQQOODO ::r 64/256K Option Card Switches til (I) ~ 5' (JQ ~ 1 . 64/256K option with 64K option installed 1 . 64K option I~~~~Q~QQQ I 64K Option Card Switches ~~~Q~~~~Ql 32K Option Card Switches If~~Q~~~~~ I I;~~Q~~~~~ j ~~~Q~Q~~~J I~~~~Q~QQQ I I;~~~Q~~~~ I 1 . 64K option 2 . 32K options 1 . 64/256K option with 128K installed Switch Block 2 li~~~Q~~~~ I I~~~Q~~~~~ I 2 . 64K options 1 . 64/256K option with 64K installed 2 . 32K options 1 I;~~~QQ~QQ I I;~~Q~~~~~ I If~~Q~Q~~~ I 224K Total Memory 160K + (64K on System Board) 1 System Board Switches 1 - 64/256K option with 64K installed 1 - 64K option 1 - 32K option Switch Block 1 mOQQOOOO tZl () ="':::: s· 1 - 64/256K option with 128K installed 1 - 32K option 2 34 S 6 7 64K Option Card Switches 32K Option Card Switches l;~~~Q~QQOJ l;~~Q~~~~~J I;~~QQ~~~~ l;~~~Q~~~~J ~~~Q~~~~~ I I;~~~QQ~QQJ tZl (JQ t;IJ o I tH D X!pU;)ddy 8 ;~~~~~~~~ 64/256K Option Card Switches 2 - 64K options 1 - 32K option :i. ..... Switch Block 2 I;~~QQ~~~~J I;~~QQ~~~~J o - 256K Total Memory 192K + (64K on System Board) I .j:;o. CIl ~ System Board Switches ..... n CIl ~ 5' I~DOQQDDDD I I Switch Block 2 64K Option Card Switches 1 - 64/256K option with 192K installed I;~~~QQQ~Q I 1 - 64/256K option with 128K installed 1 - 64K option I;~~~QQ~QQ I I;~~QQ~~~~ I I;~~~Q~QQQ I I;~~Q~~~~~ I I;~~QQ~~~~ I (JQ [Il Switch Block 1 64/256K Option Card Switches ::r ::+ I 1 - 64/256K option with 64K installed 2 - 64K options 32K Option Card Switches , I I I I;~~~Q~~~~ I I;~~Q~~~~~ I I;~~QQ~~~~ I 3 - 64K options 1 - 64/256K option: with 128K installed 2 - 32K options I;~QQ~~QQQ I I;~~~QQ~QQ j i I;~~QQ~~~~ I I;~~QQQ~~~ I 288K Total Memory 224K + (64K on System Board) 1 System Board Switches 2 3 4 5 6 a 7 mD~~DDDD Switch Block 1 ---- ----- 1 - 64/256K option with 128K installed 1 - 64K option 1 - 32K option -_.. -- --- - L-. _ _ _ .. ____ __ ___ _ I;~~QQ~~~~ I - -- \I'.l ~ ~. t:r' \I'.l ('!) :::: s· (JCl (Il - 32K Option Card Switches I;~Q~~~~~~ I I;~~~QQ~QQ I - _ ... - - - - 64K Option Card Switches I;~~~QQQ~Q I 1 - 64/256K option with 192K installed 1 - 32K option I;~QQ~~QQQ ----- 64/256K Option Card Switches ~- Switch Block 2 o I VI D X!pU;}ddV I;~Q~~~~~~ I -- I o - 320K Total Memory 256K + (64K on System Board) I 0'1 Vl ~ System Board Switches ~. Switch Block 1 I~DDQQDDDD I Switch Block 2 I;~~~Q~QQQJ I ::r' Vl 64K Option Card Switches 64/256K Option Card Switches ~ :::: S· (JQ 1 - 64/256K option with 128K installed 2 - 64K options I~~~~QQ~QQ I l~~~~Q~~~~ I I;~Q~~~~~~ I 1 - 64/256K option with 192K installed 1 - 64K option I~~~~QQQ~Q I I;~Q~~~~~~ I 1 - 64/256K option with 192K installed 2 - 32K options I;~~~QQQ~Q I 1 - 64/256K option with 256K installed I;~~~QQQQ~ I (Il 32K Option Card Switches I I I;~Q~~~~~~ I I;~Q~~Q~~~ I I - - - ----- _ _ _ _ ~I 352K Total Memory 288K + (64K on System Board) System Board Switches Switch Block 1 GDD~QOODO I 64/256K Option Card Switches 1 - 64/256K option with 192K installed 1 - 64K option 1 - 32K option l1~~~QQQ~QJ 1 - 64/256K option with 256K installed 1 - 32K option l;~~~QQQQ~ J CZl . =CZl ~ ..... ~ ('1) :::: S· (JQ ~ -9 - .l D X!pU;}ddV Switch Block 2 64K Option Card Switches 11~Q~~~~~~ I;~~~Q~QQQ I 32K Option Card Switches I~~Q~Q~~~~ I I;~Q~Q~~~~ I I o. 00 Vl ~ .... f) 384K Total Memory 320K + (64K on System Board) -- _ .. ----_ .. _ - - --------- 1 System Board Switches Switch Block 1 - ... - --- :2 3 5 6 7 8 mD~~DDDD 1:2345678 Switch Block 2 ~~~~~~~~~ ---- =- 64/256K Option Card Switches Vl Q :::: .... ::s 0Cl rIl 4 1 - 64/256K option with 192K installed 2 - 64K options 1 - 64/256K option with 256K installed 1 - 64/256K option with 64K installed I~~~~QQQ~Q I 64K Option Card Switches 32K Option Card Switches I~~Q~~~~~~ I I~~Q~Q~~~~ I I;~~~QQQQ~ I I;~~~Q~~O~ I 1 - 64/256K option with 256K installed 1 - 64K option I~~~~QQQQ~ I 1 - 64/256K option with 256K installed 2 - 32K options I~~~~QQQQ~ I I~~Q~Q~~~~ I I~~Q~Q~~~~ I 1;~Q~QQ~~~ I , 416K Total Memory 352K + (64K on System Board) System Board Switches Switch Block 1 I~ODQQOOOO I 64/256K Option Card Switches 1 - 64/256K option with 256K installed 1 - 64/256K option with 64K installed 1 - 32K option C/:l :;;..... ..... 1 - 64/256K option with 256K installed 1 - 64K option 1 - 32K option 64K Option Card Switches I;~~~QQQQ~ I I;~~~QQQQ~ =- C/:l ~ ..... ..... s· (JQ til <;1 \0 D X!pU~ddV l~QQ~Q~QQQ I 32K Option Card Switches I;~QQ~~~~~ I I~~Q~Q~QQQ I ~ - Switch Block 2 I;~Q~Q~~~~ I I;~QO~~~~~ I o 448K Total Memory 384K + (64K on System Board) I N o Vl ~ System Board Switches ~. =.... Vl Switch Block 1 ~DDQQDDDO 64/256K Option Card Switches ~ ~ = (JQ ~ 1 - 64/256K option with 256K installed 1 - 64/256K option with 64K installed 1 - 64K option 1 - 641256K option with 256K installed 2 - 64K options 1 - 64/256K option with 256K installed 1 - 64/256K option with 128K installed rl~~~QQQQ~ I r~~Q~Q~QQQ l rl~~~QQQQ~l 11~~~QQQQ~ I 11Q~~QQ~QQ 1 1 Switch Block 2 64K Option Card Switches 11~QQ~~~~~l 11~Q~Q~~~~l 11~QQ~~~~~l 2 3 4 5 6 7 8 ~~~~~~~~~ 32K Option Card Switches 480K Total Memory 416K + (64K on System Board) System Board Switches Switch Block 1 I~DD~QOOOO I 64/256K Option Card Switches 1 - 64/256K option with 256K installed 1 - 64/256K option with 128K installed 1 - 32K option I;~~~QQQQ~ I I;~Q~QQ~QQ I til §. ..... (') t:r' til ('I) :::: s· (JQ !;Il 9N - D X!pUJddV Switch Block 2 64K Option Card Switches I~Q~QQ~QQQ I 32K Option Card Switches I;~Q~Q~~~~ I o 512K Total Memory 448K + (64K on System Board) I N N r.Il ~ ~. 1 System Board Switches Switch Block 1 2 3 4 5 6 7 8 ;DD~~DDDD 1 Switch Block 2 2 3 4 5 6 7 8 m~~~~~~~ ::r r.Il 64/256K Option Card Switches ~ ::+ 5· (JQ v.I 1 - 64/256K option with 256K installed 1 - 64/256K option with 128K installed 1 - 64K option 1 - 64/256K option with 256K installed 1 - 64/256K option with 192K installed r~~~~QQQQ~ I I~~Q~QQOWJ 64K Option Card Switches 64K Option Card Switches I~~QQQ~~~~l I~~~~QQOQ~ I I~~Q~QQQ~O I - - - - - _ .. _ - - - _ .. _ - - - 544K Total Memory 480K + (64K on System Board) System Board Switches Switch Block 1 I~DDQQDDDDJ 64/256K Option Card Switches 1 - 64/256K option with 256K installed 1 - 64/256K option with 192K installed 1 - 32K option I~~~~QQQQ~ I I;~Q~QQQ~Q I Switch Block 2 64K Option Card Switches I;QQQQ~QQQ I 32K Option Card Switches [;Q~~~~~~~ I - - - - - - _.. - til ~ .... ( ') t:T' til ('t> :::: s· OQ tI> o N ~ D X!pU~ddV 576K Total Memory 512K + (64K on System Board) 9N "'" Vl ~ g. System Board Switches Switch Block 1 IrDOQQOODO I Switch Block 2 ~O~~QQQQ I ::r' Vl 64/256K Option Card Switches ~ ~ 5· (JQ Vl 1 - 64/256K option with 256K installed 1 - 64/256K option with 192K installed 1 - 64K option 2 - 64/256K option with 256K installed I~~~~QQQQ~ I I;~Q~QQQ~Q I I~~~~QQQQ~ I I;~~~QQQQ~ I - -- 64K Option Card Switches I~Q~~~~~~~ I 32K Option Card Switches 544K System Board Switches 60aK Total Memory + (64K on System Board) Switch Block 1 I;ODQ~DDDD I 64K Option Card Switches 64/256K Option Card Switches 2 - 64/256K option with 256K installed 1 - 32K option Switch Block 2 I;~~~~QQQ~ I I;~~~~QQ~Q I 32K Option Card Switches I;Q~~Q~~~~ I I;~Q~~QQQ~ I - CIl ~. .... n :r CIl ~ ~ 5' (JQ ~ 9N Ul D X!pU;}ddV ------- o 640K Total Memory 576K + (64K on System Board) I N 0'\ CI:l ~. System Board Switches Switch Block 1 ~DDQQDDDD I Switch Block 2 ~~Q~~QQQQ ( ') ::r CI:l 64/256K Option Card Switches ~ :::: 64K Option Card Switches 5' 0Cl (/l 2 - 64/256K option with 256K installed 1 - 64K option I~~~~QQQQ~ I I~~Q~QQQQ~ I 2 - 64/256K option with 256K installed 1 - 64/256K option with 64K installed I~~~~QQQQ~J I;~Q~QQQQ~ I I;Q~~Q~QQQ I I;Q~~Q~~~~ I 32K Option Card Switches Extender Card Switch Settings System Memory Extender Card Switch Block Memory Segment 16K to 64K 11 ~~~~ 1 96K to 128K 11 ~~~~ 2 160K to 192K 11 ~ ~ ~ ~I 3 224K to 256K 11 ~~~D 4 288K to 320K 352K to 384K ~ ~ ~I 11 D ~ ~ DI \1 D 6 416K to 448K II D ~ 480K to 512K 11 ~~~D 8 544K to 576K 11 ~~~~ 9 ~I~~~DI A 608K to 640K ~~ 5 7 Switch Settings G-27 Notes: G-28 Switch Settings Switch Settings (64KB-256KB CPU) System Board Switch Settings ...................... System Board Switch Settings .................... 5-1/4" Diskette Drives Switch Settings ............ Display Type Switch Settings .................... Math Coprocessor Switch Settings ................ G-31 G-31 G-32 G-32 G-32 Memory Option Switch Settings .................... 64K Total Memory ........................... 128K Total Memory ........................... 192K Total Memory ........................... 256K Total Memory ........................... 288K Total Memory ........................... 320K Total Memory ........................... 352K Total Memory ........................... 384K Total Memory ........................... 416K Total Memory ........................... 448K Total Memory ........................... 480K Total Memory ........................... 512K Total Memory ........................... 544K Total Memory ........................... 576K Total Memory ........................... 608K Total Memory ........................... 640K Total Memory ........................... G-34 G-34 G-34 G-34 G-34 G-35 G-36 G-37 G-38 G-39 G-40 G-41 G-42 G-43 G-44 G-45 G-46 Extender Card Switch Settings ...................... G-47 Switch Settings G-29 Notes: G- 30 Switch Settings Switch Setting Charts System Board Switches WARNING: Before you change any switch settings, make a note of how the switches are presently set. Switch Block 1 ~DDDDDDDD Switch Function 1,7,8 2 3,4 5,6 Number of 5-1/4 inch diskette drives installed Math Coprocessor System board memory switches Type( s) of display( s) connected Switch Block 2 Switch Function 1,2,3,4,5 6,7,8 Amount of memory options installed Always in the Off position Switch Settings G-31 Number of 5-1/4 Inch Diskette Drives Installed Switch Block 1 Switch Block 2 0- Drives ~~DDDDD~~ ~DDDDDQQQ 1 - Drive ~~DDDDD~~ ~DDDDDQQQ 2 - Drives ~QDDDDDQ~ lDDDDDQQQ Type(s) of display(s) connected WARNING: If an IBM Monochrome Display is connected to your system. Switch Block 1, switches 5 and 6, must always be Off. Damage to your display can result with any other switch settings. Switch Block 1 Switch Block 2 IBM Monochrome Display (or IBM Monochrome Display plus another display) Switch Block 1 Switch Block 2 Color Display (Do not use if an IBM Monochrome Display is connected) 1 2 3 4 5 6 7 8 mDDD~~DD 1 2 3 4 5 6 7 8 mDDD~~DD 1 2 3 4 " 6 7 8 40x25 Mode 1 2 3 4 5 6 7 8 80x25 Mode mDDDD~~~ mDDDD~~~ Note: The 40x25 mode means there will be 40 characters across the screen and 25 lines down the screen. The 80x25 mode means there will be 80 characters across the screen and 25 lines down the screen. The 80x25 mode, when used with home televisions and various displays, can cause loss of character quality. G-32 Switch Settings Math Coprocessor Switch Block 1 Switch Block 2 With Math Coprocessor ~D ~ 000000 ~DDDDDQQQ Without Math Coprocessor ~DQDDDDDD ~DDDDDQQQ Switch Settings G-33 o Memory Switch Settings I ~ (64KB-256KB CPU) System Board .j::o. I.f.l ~ .... ..... n =- I.f.l 64K Total Memory System Board Switches I~DOQQDDDD I Switch Block 1 til ;:::: Switch Block 2 1~~~~~~Q~Q I s· (JQ U':l 128K Total Memory 1 2 :3 4 5 6 7 - 1 8 mD~~DDDD Switch Block 1 System Board Switches Switch Block 2 2 3 4 5 6 7 8 ~~~~~~~~~ ----- 192K Total Memory System Board Switches -- ---- Switch Block 1 -- 1;00 QQ0000I Switch Block 2 I;~~Q~~QQQ I Switch Block 2 I;~QQ~~QQQ I -- 256K Total Memory System Board Switches Switch Block 1 I;DoQQOOoOJ 288K Total Memory 32K + (256K on System Board) System Board Switches Switch Block 1 I~DDQQDDDD I 64/256K Option Card Switches Switch Block 2 64K Option Card Switches I~QQQ~~QQQ I 32K Option Card Switches l~~Q~~~~~~J 1 - 32K option I.f.l ~ g. ::r' I.f.l ~ :::: 5· (JQ tI.> o I (H VI D X!puaddV I I J 320K Total Memory 64K + (256K on System Board) <;) w 0'1 til System Board Switches ~ Switch Block 1 l~ODQQDDDDJ Switch Block 2 ~~~~Q~QQQ I ~. :::r' 64/256K Option Card Switches til ~ :::: s· (JQ 1 - 64/256K option with 64K installed ~ 1 - 64K option 2 - 32K options 64K Option Card Switches 32K Option Card Switches I~~Q~~~QQQ I I;~Q~~~~~~ I ~~Q~~~~~~J I~~Q~~Q~~~ I 352K Total Memory 96K + (256K on System Board) System Board Switches Switch Block 1 ImoQQoDDDJ 64f256K Option Card Switches 1 - 64f256K option with 64K installed 1 - 32K option Switch Block 2 64K Option Card Switches 32K Option Card Switches I;~Q~Q~~~~ I I;~Q~~~QQQ I I;~Q~~~~~~J 1 - 64K option 1 - 32K option I;Q~~Q~QQQ I I;~Q~Q~~~~ I I;~Q~~~~~~ I til ~. ( ') ::r I;~Q~~Q~~~ I 3 - 32K options I;~Q~Q~~~~ I til ~ :::: s· (JQ rJl o I I.H -...J D X!pU;JddV II , o 384K Total Memory 128K + (256K on System Board) I <.H 00 til System Board Switches ~ .... ..... I Switch Block 1 ~ODQ~OODO_ l Switch Block 2 I~~~~]~Q~ (') ::r 64/256K Option Card Switches til 64K Option Card Switches 32K Option Card Switches ~ :=: s· (JQ 1 - 64/256K option with 64K option installed 1 - 64K option (I> I;~Q~~~QQQ I I;~Q~~~~~~ I I~~Q~Q~~~~ I 2 - 64K options 1 - 64/256K option with 64K installed 2 - 32K options I~~Q~Q~~~~I I;~Q~QQ~~~ I 1;~Q~~~QQQ I I;~Q~~~~~~ I 1 - 64K option 2 - 32K options 1 - 64/256K option with 128K installed I~~Q~Q~~~~ I I;~Q~~Q~QQ I I~~Q~Q~~~~ I I;~Q~QQ~~~ I 416K Total Memory 160K + (256K on System Boardl System Board Switches I~DDQQDDDD I Switch Block 1 64/256K Option Card Switches 1 - 64/256K option with 64K installed 1 - 64K option 1 - 32K option l;~Q~~~QQQ I ~ .... ..... (") 1 - 64/256K option with 128K installed 1 - 32K option 32K Option Card Switches I;~Q~Q~~~~ I I;~QQ~~~~~ I I~~Q~Q~~~~ I I~~Q~~Q~QQ I ::r' ~ ..... ..... (D s· (JQ rIl o I W \0 D X!pU~ddV I~QQ~Q~QQQ I 64K Option Card Switches I~~Q~~~~~~ I 2 - 64K options 1 - 32K option ~ Switch Block 2 l;~QQ~~~~~ I ~~QQ~~~~~J o ~ o System Board Switches CJ) ~. .... t:r CJ) :::: 1 - 64/256K option with 192K installed ~ 1 - 64/256K option with 128K installed 1 - 64K option 5' (JQ Switch Block 1 I~ODQQDDDD I 64/256K Option Card Switches n ~ I 448K Total Memory 192K + (256K on System Board) 1 - 64/256K option with 64K installed 2 - 64K options I~~Q~~QQ~QI I~~Q~~Q~QQ I I;~Q~~~QQQ I Switch Block 2 64K Option Card Switches I~~~QQ~QQQ I 32K Option Card Switches I;~QQ~~~~~ I I;~Q~Q~~~~ I I;~QQ~~~~~ I l;~Q~~~~~~ I I;~Q~Q~~~~ I I;~QQ~~~~~ I 3 - 64K options 1 - 64/256K option with 128 installed 2 - 32K options I I~~Q~~Q~QQ I I;~QQ~~~~~ I I;~QQ~Q~~~ I ~-- - 480K Total Memory 224K + (256K on System Board) System Board Switches -- - - - _ .. _- Switch Block 1 I~DDQQDDDD I I~Q~QQ~QQQ I - 64/256K Option Card Switches 1 - 64/256K option with 192K installed 1 - 32K option I~~Q~~QQ~Q I 1 - 64/256K option with 128K installed 1 - 64K option 1 - 32K option I~~Q~~Q~QQ I CIl :i, ..... (') ::r' CIl ~ ..... ..... 5' (JQ Vl o - Switch Block 2 ~ D X!pU;)ddy 64K Option Card Switches 32K Option Card Switches I~~QQQ~~~~ I I~~QQ~~~~~ I I~~QQQ~~~~ I o 512K Total Memory 256K + (256K on System Boardl I .j::o. N Vl ~ System Board Switches Switch Block 1 l~DDQQDDDD I Switch Block 2 11~QQQ~QQQ I ~. ::r' Vl 64/256K Option Card Switches ~ :::: S· 64K Option Card Switches 1 - 64/256K option with 128K installed 2 - 64K options 11~Q~~Q~QQ I l1~QQ~~~~~J 11~QQQ~~~~ I 1 - 64/256K option with 192K installed 1 - 64K option I~~Q~~QQ~Q I ~~QQQ~~~~ I 1 - 64/256K option with 192K installed 2 - 32K options I~~Q~~QQ~Q I 1 - 64/256K option with 256K installed l~~Q~~QQQ~ I (JQ rn 32K Option Card Switches I~~QQQ~~~~ I 11~QQQQ~~~ 544K Total Memory 288K + (256K on System Board I System Board Switches Switch Block 1 I~DDQQDDDD I Switch Block 2 I~~QQQ~QQQ I 64/256K Option Card Switches 64K Option Card Switches 32K Option Card Switches 1 - 64/256K option with 192K installed 1 - 64K option 1 - 32K option I~~Q~~QQ~Q I I;~QQQ~~~~ I I;Q~~~~~~~ I 1 - 64/256K option with 256K installed 1 - 32K option ~~Q~~QQQ~ I CI.l . ~ ..... (') ::r CI.l ..... ..... ~ s· (fQ rIl o,i. w D X!pU~ddV I~Q~~~~~~~ I 576K Total Memory 320K + (256K on System Board) Q J;.. ~ 1 System Board Switches til ~ ~. I Switch Block 1 2 J 4 5 6 7 8 ;oD~~DDDD ::r' 64/256K Option til Card Switches I Switch Block 2 64K Option Card Switches ~~~~~QQ~Q -l 32K Option Card Switches ~ ::+ s· (JQ '" 1 - 64/256K option with 192K installed 2 - 64K options 1 - 64/256K option with 256K installed 1 - 64/256K option with 64K installed - 1~~Q~~QQ~Q I I~Q~~~~QQQ I 1;~Q~~OQQ~ I 1 - 64/256K option with 256K installed 2 - 32K options I~~Q~~QQQ~ I --_._- -- - I~Q~~~~~~~ I l~~Q~~OQQ~ I 1 - 64/256K option with 256K installed 1 - 64K option - 1~~QQQ~~~~ I I~Q~~~~~~~ J I~Q~~~~~~~ I~Q~~~O~~~ J - 608K Total Memory 352K + (256K on System Board) System Board Switches Switch Block 1 I~ODQQOODO I 64/256K Option Card Switches 1 - 64/256K option with 256K installed 1 - 64/256K option with 64K installed 1 - 32K option Vl ~. 1 - 64/256K option with 256K installed 1 - 64K option 1 - 32K option - - - - - - _.. - - - - Switch Block 2 64K Option Card Switches I~~Q~~QQQ~ I 32K Option Card Switches l;Q~~Q~~~~ I I;Q~~~~QQQ I I~~Q~~QQQ~ I - I~~~~~QQQQ I I;Q~~~~~~~ I - ~ ('l ::r' Vl ~ ~ S· (JQ '" o ,i:.. til D X!pU;}ddV - - - - - - I;Q~~Q~~~~ o 640K Total Memory 384K + (256K on System Board) ~ 0\ CI.l - - - - - _ .. _ System Board Switches ~. ..... n :T Switch Block 1 liDOQQODDD I 64/256K Option Card Switches CI.l (1) - - - _.. Switch Block 2 64K Option Card Switches ::+ ---- --- l;~Q~~QQQQ I 32K Option Card Switches I I :r (JQ t:Il ---- 1 - 64/256K option with 256K installed 1 - 64/256K option with 64K installed 1 - 64K option 1 - 64/256K option with 256K installed 2 - 64K options 1 - 64/256K option with 256K installed 1 - 64/256K option with 128K installed I;~Q~~QQQ~ I I;Q~~~~QQQ I I;~Q~~QQQ~ I I;~Q~~QQQ~ I I;Q~~~Q~QQ I I;Q~~Q~~~~ I I;Q~~~~~~~J I;Q~~Q~~~~ I ! Extender Card Switch Settings System Memory Extender Card Switch Block Memory Segment 16K to 64K r~~~~1 1 96K to 128K r~~~~1 2 160K to 192K r~~~~1 3 224K to 256K r~~~~1 4 288K to 320K 1~~~~1 5 352K to 384K 1~~~~1 6 416K to 448K 1~~~~1 7 480K to 512K r~~~~1 8 544K to 576K r~~~~1 9 608K to 640K r~D~~1 A Switch Settings G-47 Notes: G-48 Switch Settings GLOSSARY J.Ls: Microsecond. adapter: An auxiliary system or unit used to extend the operation of another system. address bus: One or more conductors used to carry the binarycoded address from the microprocessor throughout the rest of the system. all points addressable (APA): A mode in which all points on a displayable image can be controlled by the user. alpanumeric (A/N): Pertaining to a character set that contains letters, digits, and usually other characters, such as punctuation marks. Synonymous with alphanumeric. American Standard Code for Information Interchange (ASCII): The standard code, using a coded character set consisting of 7-bit coded characters (8 bits including parity check), used for information interchange among data processing systems, data communication systems and associated equipment. The ASCII set consists of control characters and graphic characters. A/N: Alphanumeric. analog: (1) pertaining to data in the form of continuously variable physical quantities. (2) Contrast with digital. AND: A logic operator having the property that if P is a statement, Q is a statement, R is a statement, ... ,then the AND of P, Q, R, .. .is true if all statements are true, false if any statement is false. APA: All points addressable. Glossary H-l ASCII: American Standard Code for Information Interchange. assembler: A computer program used to assemble. Synonymous with assembly program. asynchronous communications: A communication mode in which each single byte of data is synchronized, usually by the addition of start/stop bits. BASIC: Beginner's all-purpose symbolic instruction code. basic input/output system (BIOS): Provides the device level control of the major I/O devices in a computer system, which provides an operational interface to the system and relieves the programmer from concern over hardware device characteristics. baud: (1) A unit of signaling speed equal to the number of discrete conditions or signal events per second. For example, one baud equals one-half dot cycle per second in Morse code, one bit per second in a train of binary signals, and one 3-bit value per second in a train of signals each of which can assume one of eight different states. (2) In asynchronous transmission, the unit of modulation rate corresponding to one unit of interval per second; that is, if the duration of the unit interval is 20 milliseconds, the modulation rate is 50 baud. BCC: Block-check character. beginner's all-purpose symbolic instruction code (BASIC): A programming language with a small repertoire of commands and a simple syntax, primarily designed for numerical application. binary: (1) Pertaining to a selection, choice, or condition that has two possible values or states. (2) Pertaining to a fixed radix numeration system having a radix of two. binary digit: (1) In binary notation, either of the characters 0 or 1. (2) Synonymous with bit. binary notation: Any notation that uses two different characters, usually the binary digits 0 and 1. H-2 Glossary binary synchronous communications (BSC): A standardized procedure, using a set of control characters and control character sequences for synchronous transmission of binary.:.coded data between stations. BIOS: Basic input/output system. bit: In binary notation, either of the characters 0 or 1. bits per second (bps): A unit of measurement representing the number of discrete binary digits which can be transmitted by a device in one second. block-check character (BCC): In cyclic redundancy checking, a character that is transmitted by the sender after each message block and is compared with a block-check character computed by the receiver to determine if the transmission was successful. boolean operation: (1) Any operation in which each of the operands and the result take one of two values~ (2) An operation that follows the rules of boolean algebra. bootstrap: A technique or device designed to bring itself into a desired state by means of its own action; that is, a machine routine whose first few instructions are sufficient to bring the rest of itself into the computer from an input device. bps: Bits per second. BSC: Binary synchronous communications. buffer: (1) An area of storage that is temporarily reserved for use in performing an input/output operation, into which data is read or from which data is written. Synonymous with I/O area. (2) A portion of storage for temporarily holding input or output data. bus: One or more conductors used for transmitting signals or power. byte: (1) A binary character operated upon as a unit and usually shorter than a computer word. (2) The representation of a character. Glossary H-3 CAS: Column address strobe. cathode ray tube (CRT): A vacuum tube display in which a beam of electrons can be controlled to form alphanumeric characters or symbols on a luminescent screen, for example by use of a dot matrix. cathode ray tube display (CRT display): (1) A device that presents data in visual form by means of controlled electron beams. (2) The data display produced by the device as in (1). CCITT: Comite Consultatif International Telegrafique et Telephonique. central processing unit (CPU): A functional unit that consists of one or more processors and all or part of internal storage. channel: A path along which signals can be sent; for example, data channel or I/O channel. characters per second (cps): A standard unit of measurement for printer output. code: (1) A set of unambiguous rules specifying the manner in which data may be represented in a discrete form. Synonymous with coding scheme. (2) A set of items, such as abbreviations, representing the members of another set. (3) Loosely, one or more computer programs, or part of a computer program. (4) To represent data or a computer program in a symbolic form that can be accepted by a data processor. column address strobe (CAS): A signal that latches the column addresses in a memory chip. Comite Consultatif International Telegrafique et Telephonique (CCITT): Consultative Committee on International Telegraphy and Telephony. computer: A functional unit that can perform substantial computation, including numerous arithmetic operations, or logic operations; without intervention by a human operator during the run. H-4 Glossary configuration: (1) The arrangement of a computer system or network as defined by the nature, number, and the chief characteristics of its functional units. More specifically, the term configuration may refer to a hardware configuration or a software configuration. (2) The devices and programs that make up a system, subsystem, or network. conjunction: (1) The boolean operation whose result has the boolean value 1 if, and only if, each operand has the boolean value 1. (2) Synonymous with AND operation. contiguous: (1) Touching or joining at the edge or boundary. (2) Adjacent. CPS: Characters per second. CPU: Central processing unit. CRC: Cyclic redundancy check. CRT: Cathode ray tube. CRT display: Cathode ray tube display. CTS: Clear to send. Associated with modem control. cyclic redundancy check (CRC): (1) A redundancy check in which the check key is generated by a cyclic algorithm. (2) A system of error checking performed at both the sending and receiving station after a block-check character has been accumulated. cylinder: (1) The set of all tracks with the same nominal distance from the axis about which the disk rotates. (2) The tracks of a disk storage device that can be accessed without repositioning the access mechanism. daisy-chained cable: A type of cable that has two or more connectors attached in series. data: (1) A representation offacts, concepts, or instructions in a formalized manner suitable for communication, interpretation, or processing by humans or automatic means. (2) Any representations, such as characters or analog quantities, to which meaning is, or might be assigned. Glossary H-5 decoupling capacitor: A capacitor that provides a lowimpedance path to ground to prevent common coupling between states of a circuit. Deutsche Industrie Norm (DIN): (1) German Industrial Norm. (2) The committee that sets German dimension standards. digit: (1) A graphic character that represents an integer, for example, one of the characters 0 to 9. (2) A symbol that represents one of the non-negative integers smaller than the radix. For example, in decimal notation, a digit is one of the characters from 0 to 9. digital: (1) Pertaining to data in the form of digits. (2) Contrast with analog. DIN: Deutsche Industrie Norm. DIN connector: One of the connectors specified by the DIN standardization committee. DIP: Dual in-line package. direct memory access (DMA): A method oftransferring data between main storage and I/O devices that does not require processor intervention. disk: Loosely, a magnetic disk unit. diskette: A thin, flexible magnetic disk and a semi-rigid protective jacket, in which the disk is permanently enclosed. Synonymous with flexible disk. D MA: Direct memory access. DSR: Data set ready. Associated with modem control. DTR: Data terminal ready. Associated with modem control. dual in-line package (DIP): A widely used container for an integrated circuit. DIPs are pins usually in two parallel rows. These pins are spaced 1/ 10 inch apart and come in different configurations ranging from 14-pin to 40-pin configurations. H-6 Glossary EBCDIC: Extended binary-coded decimal interchange code. ECC: Error checking and correction. edge connector: A terminal block with a number of contacts attached to the edge of a printed circuit board to facilitate plugging into a foundation circuit. EIA: Electronic Industries Association. EIA/CCITI: Electronics Industries Association/Consultative Committee on International Telegraphy and Telephony. end-of-text-character (ETX): A transmission control character used to terminate text. end-of-transmission character (EOT): A transmission control character used to indicate the conclusion of a transmission, which may have included one or more texts and any associated message headings. EOT: End-of-transmission character. EPROM: Erasable programmable read-only memory. erasable programmable read-only memory (EPROM): A storage device whose contents can be changed by electrical means. EPROM information is not destroyed when power is removed. error checking and correction (ECC): The detection and correction of all single-bit, double-bit, and some multiple-bit errors. ETX: End-of-text character. extended binary-coded decimal interchange code (EBCDIC): A set of 256 characters, each represented by eight bits. flexible disk: Synonym for diskette. firmware: Memory chips with integrated programs already incorporated on the chip. Glossary H-7 gate: (1) A device or circuit that has no output until it is triggered into operation by one or more enabling signals, or until an input signal exceeds a predetermined threshold amplitude. (2) A signal that triggers the passage of other signals through a circuit. graphic: A symbol produced by a process such as handwriting, drawing, or printing. hertz (Hz): A unit offrequency equal to one cycle per second. hex: Abbreviation for hexadecimal. hexadecimal: Pertaining to a selection, choice, or condition that has 16 possible values or states. These values or states usually contain 10 digits and 6 letters, A through F. Hexadecimal digits are equivalent to a power of 16. high-order position: The leftmost position in a string of characters. Hz: Hertz. interface: A device that alters or converts actual electrical signals between distinct devices, programs, or systems. k: An abbreviation for the prefix kilo; that is, 1,000 in decimal notation. K: When referring to storage capacity, 2 to the tenth power; 1,024 in decimal notation. KB: Kilobyte; 1,024 bytes. kHz: A unit of frequency equal to 1,000 hertz. kilo (k): One thousand. latch: (1) A feedback loop in symmetrical digital circuits used to maintain a state. (2) A simple logic-circuit storage element comprising two gates as a unit. LED: Light-emitting diode. H-8 Glossary light-emitting diode (LED): A semi-conductor chip that gives off visible or infrared light when activated. low-order position: The rightmost position in a string of characters. m: (1) Milli; one thousand or thousandth part. (2) Meter. M: Mega; 1,000,000 in decimal notation. When referring to storage capacity, 2 to the twentieth power; 1,048,576 in decimal notation. rnA: Milliampere. machine language: (1) A language that is used directly by a machine. (2) Another term for computer instruction code. main storage: A storage device in which the access time is effectively independent of the location of the data. MB: Megabyte, 1,048,576 bytes. mega (M): 10 to the sixth power, 1,000,000 in decimal notation. When referring to storage capacity, 2 to the twentieth power, 1,048,576 in decimal notation. megabyte (MB): 1,048,576 bytes. megahertz (MHz): A unit of measure offrequency. 1 megahertz equals 1,000,000 hertz. MFM: Modified frequency modulation. MHz: Megahertz. microprocessor: An integrated circuit that accepts coded instructions for execution; the instructions may be entered, integrated, or stored internally. microsecond (p,s): One-millionth of a second. milli (m): One thousand or one thousandth. milliampere (rnA): One thousandth of an ampere. Glossary H-9 millisecond (ms): One thousandth of a second. mnemonic: A symbol chosen to assist the human memory; for example, an abbreviation such a "mpy" for "multiply." mode: (1) A method of operation; for example, the binary mode, the interpretive mode, the alphanumeric mode. (2) The most frequency value in the statistical sense. modem: (Modulator-Demodulator) A device that converts serial (bit by bit) digital signals from a business machine (or data terminal equipment) to analog signals which are suitable for transmission in a telephone network. The inverse function is also performed by the modem on reception of analog signals. modified frequency modulation (MFM): The process of varying the amplitude and frequency of the "write" signal. MFM pertains to the number of bytes of storage that can be stored on the recording media. The number of bytes is twice the number contained in the same unit area of recording media at single density. modulo check: A calculation performed on values entered into a system. This calculation is designed to detect errors. monitor: (1) A device that observes and verifies the operation of a data processing system and indicates any specific departure from the norm. (2) A television type display, such as the IBM Monochrome Display. (3) Software or hardware that observes, supervises, controls, or verifies the operations of a system. ms: Millisecond; one thousandth of a second. multiplexer: A device capable of interleaving the events of two or more activities, or capable of distributing the events of an interleaved sequence to the respective activities. NAND: A logic operator having the property that if P is a statement, Q is a statement, R is a statement, ... ,then the NAND of P,Q,R, .. .is true if at least one statement is false, false if all statements are true. nanosecond (ns): One-thousandth-millionth of a second. H-I0 Glossary nonconjunction: The dyadic boolean operation the result of which has the boolean value 0 if, and only if, each operand has the boolean value 1. non-return-to-zero inverted (NRZI): A transmission encoding method in which the data terminal equipment changes the signal to the opposite state to send a binary 0 and leaves it in the same state to send a binary 1. NOR: A logic operator having the property that if P is a statement, Q is a statement, R is a statement, ... ,then the NOR of P,Q,R, .. .is true if all statements are false, false if at least one statement is true. NOT: A logical operator having the property that if P is a statement, then the NOT of P is true if P is false, false if P is true. NRZI: Non-return-to-zero inverted. ns: Nanosecond; one-thousandth-millionth of a second. operating system: Software that controls the execution of programs; an operating system may provide services such as resource allocation, scheduling, input/output control, and data management. OR: A logic operator having the property that if P is a statement, Q is a statement, R is a statement, ... ,then the OR of P,Q,R, .. .is true if at least one statement is true, false if all statements are false. output: Pertaining to a device, process, or channel involved in an output process, or to the data or states involved in an output process. output process: (1) The process that consists of the delivery of data from a data processing system, or from any part of it. (2) The return of information from a data processing system to an end user, including the translation of data from a machine language to a language that the end user can understand. overcurrent: A current of higher than specified strength. overvoltage: A voltage of higher than specified value. Glossary H-ll parallel: (1) Pertaining to the concurrent or simultaneous operation of two or more devices, or to the concurrent performance of two or more activities. (2) Pertaining to the concurrent or simultaneous occurrence of two or more related activities in multiple devices or channels. (3) Pertaining to the simultaneity of two or more processes. (4) Pertaining to the simultaneous processing of the individual parts of a whole, such as the bits of a character and the characters of a word, using separate facilities for the various parts. (5) Contrast with serial. PEL: Picture element. personal computer: A small home or business computer that has a processor and keyboard that can be connected to a television or some other monitor. An optional printer is usually available. picture element (PEL): (1) The smallest displayable unit on a display. (2) Synonymous with pixel, PEL. pinout: A diagram of functioning pins on a pinboard. pixel: Picture element. polling: (1) Interrogation of devices for purposes such as to avoid contention, to determine operational status, or to determine readiness to send or receive data. (2) The process whereby stations are invited, one at a time, to transmit. port: An access point for data entry or exit. printed circuit board: A piece of material, usually fiberglass, that contains a layer of conductive material, usually metal. Miniature electronic components on the fiberglass transmit electronic signals through the board by way of the metal layers. program: (1) A series of actions designed to achieve a certain result. (2) A series of instructions telling the computer how to handle a problem or task. (3) To design, write, and test computer programs. programming language: (1) An artificial language established for expressing computer programs. (2) A set of characters and rules, with meanings assigned prior to their use, for writing computer programs. H-12 Glossary PROM: Programmable read-only memory. propagation delay: The time necessary for a signal to travel from one point on a circuit to another. radix: (1) In a radix numeration system, the positive integer by which the weight of the digit place is multiplied to obtain the weight of the digit place with the next higher weight; for example, in the decimal numeration system, the radix of each digit place is 10. (2) Another term for base. radix numeration system: A positional representation system in which the ratio of the weight of anyone digit place to the weight of the digit place with the next lower weight is a positive integer. The permissible values of the character in any digit place range from zero to one less than the radix of the digit place. RAS: Row address strobe. RGBI: Red-green-blue-intensity. read-only memory (ROM): A storage device whose contents cannot be modified, except by a particular user, or when operating under particular conditions; for example, a storage device in which writing is prevented by a lockout. read/write memory: A storage device whose contents can be modified. red-green-blue-intensity (RGBI): The description of a directdrive color monitor which accepts red, green, blue, and intensity signal inputs. register: (1) A storage device, having a specified storage capacity such as a bit, a byte, or a computer word, and usually intended for a special purpose. (2) On a calculator, a storage :levice in which specific data is stored. RF modulator: The device used to convert the composite video ;ignal to the antenna level input of a home TV. ROM: Read-only memory. Glossary H-13 ROM/BIOS: The ROM resident basic input/output system, which provides the device level control ofthe major I/O devices in the computer system. row address strobe (RAS): A signal that latches the row addresses in a memory chip. RS-232C: The standard set by the EIA for communications between computers and external equipment. RTS: Request to send. Associated with modem control. run: A single continuous performance of a computer program or routine. scan line: The use of a cathode beam to test the cathode ray tube of a display used with a personal computer. schematic: The description, usually in diagram form, of the logical and physical structure of an entire data base according to a conceptual model. SDLC: Synchronous Data Link Control. sector: That part of a track or band on a magnetic drum, a magnetic disk, or a disk pack that can be accessed by the magnetic heads in the course of a predetermined rotational displacement of the particular device. serdes: Serializer/deserializer. serial: (1) Pertaining to the sequential performance of two or more activities in a single device. In English, the modifiers serial and parallel usually refer to devices, as opposed to sequential and consecutive, which refer to processes. (2) Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. (3) Pertaining to the sequential processing of the individual parts of a whole, such as the bits of a character or the characters of a word, using the same facilities for successive parts. (4) Contrast with parallel. sink: A device or circuit into which current drains. H-14 Glossary software: (1) Computer programs, procedures, rules, and possibly associated documentation concerned with the operation of a data processing system. (2) Contrast with hardware. source: The origin of a signal or electrical energy. source circuit: (1) Generator circuit. (2) Control with sink. SS: Start-stop transmission. start bit: Synonym for start signal. start-of-text character (STX): A transmission control character that precedes a text and may be used to terminate the message heading. start signal: (1) A signal to a receiving mechanism to get ready to receive data or perform a function. (2) In a start-stop system, a signal preceding a character or block that prepares the receiving device for the reception of the code elements. Synonymous with start bit. start-stop (SS) transmission: Asynchronous transmission such that a group of signals representing a character is preceded by a start signal and followed by a stop signal. (2) Asynchronous transmission in which a group of bits is preceded by a start bit that prepares the receiving mechanism for the reception and registration of a character and is followed by at least one stop bit that enables the receiving mechanism to come to an idle condition pending the reception of the next character. stop bit: Synonym for stop signal. stop signal: (1) A signal to a receiving mechanism to wait for the next signal. (2) In a start-stop system, a signal following a character or block that prepares the receiving device for the reception of a subsequent character or block. Synonymous with stop bit. strobe: (1) An instrument used to determine the exact speed of circular or cyclic movement. (2) A flashing signal displaying an exact event. STX: Start-of-text character. Glossary H -15 Synchronous Data Link Control (SLDC): A protocol for the management of data transfer over a data communications link. synchronous transmission: Data transmission in which the sending and receiving devices are operating continuously at the same frequency and are maintained, by means of correction, in a desired phase relationship. text: In ASCII and data communication, a sequence of characters treated as an entity if preceded and terminated by one STX and one ETX transmission control, respectively. track: (1) The path or one of the set of paths, parallel to the reference edge on a data medium, associated with a single reading or writing component as the data medium moves past the component. (2) The portion of a moving data medium such as a drum, tape, or disk, that is accessible to a given reading head position. transistor-transistor logic (TIL): A circuit in which the multiple-diode cluster of the diode-transistor logic circuit has been replaced by a multiple-emitter transistor. TIL: Transistor-transistor logic. TX Data: Transmit data. Associated with modem control. External connections of the RS-232C asynchronous communications adapter interface. video: Computer data or graphics displayed on a cathode ray tube, monitor or display. write precompensation: The varying of the timing of the head current from the outer tracks to the inner tracks of the diskette to keep a constant write signal. H-16 Glossary BIBLIOGRAPHY Intel Corporation. The 8086 Family User's Manual This manual introduces the 8086 family of microcomputing components and serves as a reference in system design and implementation. Intel Corporation. 8086/8087/8088 Macro Assembly Reference Manualfor 8088/8085 Based Development System This manual describes the 8086/8087/8088 Macro Assembly Language, and is intended for use by persons who are familiar with assembly language. Intel Corporation.Component Data Catalog This book describes Intel components and their technical specifications. Motorola, Inc.The Complete Microcomputer Data Library. This book describes Motorola components and their technical specificaitons. National Semiconductor Corporation. INS 8250 Asynchronous Communications Element. This book documents physical and operating characteristics of the INS 8250. Bibliography 1-1 Notes: 1-2 Bibliography INDEX A A/N mode (alphanumeric mode) 1-131 AO-AI9 (Address Bits 0 to 19), I/O channel 1-18 adapter card with ROM 2-10 adapter, asynchronous communication 1-223 binary synchronous communication 1-251 color/graphics monitor 1-131 diskette drive 1-159 fixed disk drive 1-187 game control 1-211 monochrome display and printer 1-129 printer 1-117 synchronous data link control 1-271 Address Bits 0 to 19 (AO-AI9), I/O channel 1-131 Address Bits (asynchronous communication) 1-225 Address Enable (AEN), I/O channel 1-22 Address Latch Enable (ALE), I/O channel 1-20 address map, I/O 1-10 AEN (Address Enable), I/O channel 1-22 ALE (Address Latch Enable), I/O channel 1-20 all points addressable mode 1-129, 1-132 alphanumeric mode, 1-136 high resolution 1-137 low resolution 1-137 alt (keyboard extended code) 2-15 APA mode (all points addressable mode) 1-131, 1-132 asynchronous communications adapter, 1-223 adapter address jumper module 1-249 address bits 1~ 225 block diagram 1-224 connector specifications 1-250 current loop interface 1-227 divisor latch least significant bit 1-237 divisor latch most significant bit 1-238 I/O decode 1-225 INS8250 functional pin description 1-229 INS8250 input signals 1-229 INS8250 input/output signals 1-233 INS8250 output signals 1-232 interface descriptions 1-226 interface format jumper module 1-249 Index J-l interrupt control functions 1-237 interrupt enable register 1-243 interrupt identification register 1-240 interrupts 1-226 line control register 1-235 line status register 1-239 modem control register 1-244 modem status register 1-246 modes of operation 1-224 programmable baud rate generator 1-237 programming considerations 1-234 receiver buffer register 1-247 reset functions 1-230 transmitter holding register 1-248 voltage interchange information 1-228 attributes, character (see character attributes) B BASIC reserved interrupts 2-7 BASIC, DEF SEG 2-8 reserved interrupt 2-7 screen editor keyboard functions 2-20 workspace variables 2-8 baud rate generator 1-237 bell (printer) 1-102 bibliography 1-1 binary synchronous communications adapter, 1-251 8251A programming procedures 1-262 8251A universal synchronous/asynchronous receiver/transmitter 1-252 8253-5 programmable interval timer 1-257 8255A-5 programmable peripheral interface 1-256 block diagram 1-252 command instruction format 1-264 connector information 1-269 data bus buffer 1-253 interface signal information 1-266 interrupt information 1-268 mode instruction definition 1-263 read/write control logic 1-253 receive 1-258 J-2 Index receiver buffer 1-255 receiver control 1-255 status read definition 1-265 transmit 1-265 transmitter buffer 1-254 transmitter control 1-255 typical programming sequence 1-259 BIOS, cassette logic (see cassette logic BIOS) fixed disk ROM A-87 memory map 2-9 parameter passing 2-3 software interrupt listing 2-4 system ROM A-2 use of 2-2 bisync communications (see binary synchronous communications) block diagram 8251A universal synchronous/asynchronous receiver/transmitter 1-252 8273 SDLC protocol controller 1-272 asynchronous communications adapter 1-224 cassette circuits 1-29 color/graphics monitor adapter 1-134 coprocessor 1-37 diskette drive adapter 1-160 expansion board 1-80 extender card 1-87 fixed disk drive adapter 1-188 game control adapter 1-211 keyboard interface 1-75 monochrome display adapter 1-124 printer adapter 1-118 prototype card 1-218 receiver card 1-89 speaker drive system 1-24 synchronous data link control adapter 1-271 system 1-2 break (keyboard extended code) 2-17 BSC adapter (see binary synchronous communications) Index J-3 c cable communications adapter 1-301 expansion unit 1-79 printer 1-91 cancel (printer) 1-103 cancel ignore paper end (printer) 1-103 cancel skip perforation (printer) 1-109 caps lock (keyboard extended code) 2-16 card dimensions and specifications E-4 card, dimensions and specifications E-4 extender 1-85 prototype 1-217 receiver 1-88 carriage return (printer) 1-102 cassette circuit block diagram motor control 1-30 read hardware 1-29 write hardware 1-29 cassette interface, 1-28 connector specifications 1-31 cassette logic, BIOS 2-21 cassette read 2-23 cassette write 2-22 data record architecture 2-24 data record components 2-24 error recovery 2-24 interrupt 2-21 software algorithms 2-28 cassette read 2-23 cassette ROM BIOS 2-21 cassette write 2-22 CCITT, F-l standards F-l character attributes color/graphics monitor adapter 1-140 monochrome display adapter 1-140 character codes keyboard 2-11 J-4 Index character set, graphics printer (set 1) 1-113 graphics printer (set 2) 1-115 matrix printer 1-111 quick reference C-12 clear printer buffer (printer) 1-110 CLK (system clock), I/O channel 1-19 color display 1-157 operating characteristics 1-157 specifications E-2 color select register 1-149 color/graphics monitor adapter 1-131 6845 register description 1-148 alphanumeric mode 1-136 alphanumeric mode (high-resolution) 1-144 alphanumeric mode (low-resolution) 1-142 block diagram 1-134 character attributes 1-140 color-select register 1-149 composite connector specifications 1-155 connector specifications 1-156 direct-drive connector specifications 1-155 display buffer basic operation 1-145 graphics mode 1-141 graphics mode (high resolution) 1-144 graphics mode (low resolution) 1-142 graphic mode (medium resolution) 1-142 light pen connector specifications 1-156 major components 1-135 memory requirements 1-154 mode control and status register 1-149 mode register summary 1-152 mode select register 1-151 programming considerations 1-147 RF modulator connector specifications 1-156 sequence of events 1-153 status register 1-153 summary of available colors 1-146 colors, summary of available 1-146 command status register 0 1-172 command status register 1 1-173 command status register 2 1-174 command status register 3 1-175 Index J-5 command summary, diskette drive adapter 1-166 fixed disk drive adapter 1-195 communications adapter cable 1-301 connector specifications 1-302 communications F-l establishing a link F-3 component diagram, system board 1-7 compressed (printer) 1-103 compressed off (printer) 1-103 connector specifications, asynchronous communications adapter 1-250 binary synchronous communications 1-269 cassette interface 1-31 color/graphics monitor adapter 1-155 communications adapter cable 1-302 diskette drive adapter (external) 1-182 diskette drive adapter (internal) 1-181 game control adapter 1-216 keyboard interface 1-78 monochrome display adapter 1-128 printer adapter 1-122 synchronous data link control adapter 1-299 connectors, power supply (system unit) 1-26 power supply (expansion unit) 1-83 considerations, programming (see programming considerations) control byte, fixed disk drive adapter 1-194 control codes, printer 1-10 1 control/read/write logic 1-274 coprocessor, (see math coprocessor) ctrl (keyboard extended code) 2-15 current loop interface 1-227 D DO-D7 (data bits 0 to 7), I/O channel 1-18 DACKO-DACK3 (DMA Acknowledge 0 to 3), I/O channel 1-21 Data Bits 0 to 7 (DO-D7), I/O channel 1-18 data flow, system board 1-8 J-6 Index data record architecture, cassette 2-24 data record components, cassette 2-24 data register 1-193 data transfer mode register 1-288 DEF SEG (default segment workspace) 2-8 default workspace segment (DEF SEG) 2-8 diagram, block (see block diagram) digital output register 1-161 diskette drive adapter 1-159 adapter input 1-179 adapter output 1-178 block diagram 1-160 command status register 0 1-172 command status register 1 1-173 command status register 2 1-174 command status register 3 1-175 command summary 1-166 connector specifications (external) 1-182 connector specifications (internal) 1-181 digital-output register 1-161 DPC registers 1-174 drive A and B interface 1-178 drive constants 1-176 FDC constants 1-176 floppy disk controller 1-162 functional description 1-161 programming considerations 1-164 programming summary 1-175 symbol descriptions 1-164 system I/O channel interface 1-176 diskette drive, 1-183 electrical specifications 1-184 mechanical specifications 1-184 switch settings G-1 diskettes 1-1 85 display adapter type switch settings G-1 display, color 1-157 monochrome 1-123 divisor latch, least significant bit 1-237 most significant bit 1-238 DMA Acknowledge 0 to 3 (DACKO-DACK3), I/O channel 1-21 Index J-7 DMA Request 1 to 3 (DRQI-DRQ3), I/O channel 1-21 DOS reserved interrupts 2-9 DOS, keyboard functions 2-21 reserved interrupts 2-9 double strike (printer) 1-106 double strike off (printer) 1-107 double width (printer) 1-99, 1-103 double width off (printer) 1-103 DPC registers 1-175 DRQI-DRQ3 (DMA Request 1 to 3), I/O channel 1-21 E EIA, F-l standards F-l emphasized (printer) 1-106 emphasized off (printer) 1-106 error recovery, cassette 2-24 escape (printer) 1-104 establishing a communications link F-3 expansion board, 1-79 block diagram 1-80 expansion channel 1-81 expansion unit, 1-79 cable 1-79 expansion board 1-79 expansion channel 1-81 extender card 1-85 interface information 1-90 power supply 1-83 power supply connectors 1-83 receiver card 1-88 specifications E-2 extender card, 1-85 block diagram 1-87 programming considerations 1-86 switch settings G-l J-8 Index F FABS 1-44 FADD 1-43 FBLD 1-45 FBSTP 1-46 FCHS 1-46 FCLEX/FNCLEX 1-46 FCOM 1-47 FCOMP 1-47 FCOMPP 1-48 FDECSTP 1-48 FDISI/FNDISI 1-48 FDIV 1-49 FDIVR 1-50 FENI/FNENI 1-51 FFREE 1-51 FICOM 1-51 FICOMP 1-52 FILD 1-52 FINCSTP 1-52 FINIT/FNINIT 1-53 FIST 1-54 FISTP 1-54 fixed disk controller 1-185 fixed disk drive 1-201 fixed disk drive adapter 1-185 block diagram 1-186 command summary 1-193 control byte 1-192 data register 1-191 fixed disk controller 1-185 interface specifications 1-200 programming considerations 1-187 programming summary 1-197 ROM BIOS listing A-87 sense bytes 1-187 status register 1-187 system I/O channel interface 1-198 fixed disk drive, 1-201 electrical specifications 1-202 mechanical specifications 1-202 Index J-9 fixed disk ROM BIOS A-87 FLD 1-55 FLDCW 1-55 FLDENV 1-56 FLDLG2 1-56 FLDLN2 1-56 FLDL2E 1-57 FLDL2T 1-57 FLDPI 1-57 FLDZ 1-58 FLDI 1-58 floppy disk controller 1-160 FMUL 1-59 FNOP 1-60 FPATAN 1-60 FPREM 1-60 FPTAN 1-61 FRNDINT 1-61 FRSTOR 1-61 form feed (printer) 1-102 FSAVE/FNSAVE 1-62 FSCALE 1-62 FSQRT 1-62 FST 1-63 FSTCW/FNSTCW 1-63 FSTENV/FNSTENV 1-64 FSTP 1-64 FSTSW/FNSTSW 1-65 FSUB 1-65 FSUBR 1-66 FTST 1-67 FWAIT 1-68 FXAM 1-68 FXCH 1-69 FXTRACT 1-70 FYL2X 1-70 FYL2XPI 1-71 F2XMl 1-71 G game control adapter, 1-211 block diagram 1-211 connector specifications 1-216 J-I0 Index functional description 1-212 I/O channel description 1-213 interface description 1-214 joy stick schematic diagram 1-215 glossary, H-l graphics mode, 1-141 high resolution 1-144 low resolution 1-142 medium resolution 1-142 H hardware interrupt listing 1-11 home head (printer) 1-105 horizontal tab (printer) 1-102 I I/O address map 1-10 I/O bit map, 8255A 1-12 I/O CH CK (I/O Channel Check), I/O channel 1-20 I/O CH RDY (I/O Channel Ready), I/O channel 1-20 I/O Channel Check (I/O CH CK), I/O channel 1-20 I/O channel interface, diskette drive adapter 1-176 fixed disk drive adapter 1-187 prototype card 1-217 I/O Channel Ready (I/O CH RDY), I/O channel 1-20 I/O channel, 1-17 -I/O Channel Check (I/O CH CK) 1-20 -I/O Read Command (lOR) 1-20 -I/O Write Command (lOW) 1-21 Address Bits 0 to 19 (AO-AI9) 1-20 Address Enable (AEN) 1-21 Address Latch Enable (ALE) 1-20 Data Bits 0 to 7 (DO-D7) 1-20 description 1-20 diagram 1-18 DMA Request 1 to 3 (DRQI-DRQ3) 1-21 I/O Channel Ready (I/O CH RDY) 1-20 Interrupt Request 2 to 7 (IRQ2-IRQ7) 1-20 Memory Read Command (MEMR) 1-21 Index J-11 Memory Write Command (MEMW) 1-21 Oscillator (OSC) 1-19 Reset Drive (RESET DRV) 1-20 System Clock (CLK) 1-20 Terminal Count (T/C) 1-22 I/O Read Command (lOR), I/O channel 1-21 I/O Write Command (IOW),I/O channel 1-21 IBM 10MB Fixed Disk Drive 1-201 IBM 5-1/4" Diskette Drive 1-183 IBM 5-1/4" Diskette Drive Adapter 1-159 IBM 80 CPS Graphics Printer 1-91 IBM 80 CPS Matrix Printer 1-91 IBM 80 CPS Printers 1-91 IBM Asynchronous Communications Adapter 1-223 IBM Binary Synchronous Communications Adapter 1-251 IBM Color Display 1-157 IBM Color/Graphics Monitor Adapter 1-131 IBM Communicatons Adapter Cable 1-301 IBM Fixed Disk Drive Adapter 1-187 IBM Game Control Adapter 1-211 IBM Memory Expansion Options 1-205 IBM Monochrome Display and Printer Adapter 1-223 IBM Monochrome Display 1-129 IBM Personal Computer Math Coprocessor 1-33 IBM Printer Adapter 1-117 IBM Prototype Card 1-215 IBM Synchronous Data Link Controller Adapter 1-271 ignore paper end (printer) 1-104 INS8250, (see National Semiconductor INS8250) Intel 8088 microprocessor, arithmetic B-7 conditional transfer operations B-14 control transfer B-ll data transfer B-5 hardware interrupt listing 1-8 instruction set index B-18 instruction set matrix B-16 logic B-9 memory segmentation model B-4 operand summary B-15 processor control B-15 register model B-2 J-12 Index second instruction byte summary B-3 segment override prefix B-4 software interrupt listing 2-4 string manipulation B-I0 use of segment override B-4 Intel 8253-5 Programmable Interval Timer (see synchronous data link control communications adapter) Intel 8255A Programmable Peripheral Interface I/O bit map 1-12 Intel 8255A-5 Programmable Peripheral Interface (see synchronous data link control communications adapter) Intel 8273 SDLC Protocol Controller (see synchronous data link control communications adapter) block diagram 1-273 interrupt enable register 1-243 interrupt identification register 1-243 interrupt listing, 8088 hardware 1-11 8088 software 2-4 Interrupt Request 1 to 7 (IRQ2-IRQ7), I/O channel 1-20 interrupts, 8088 hardware 1-11 8088 software 2-4 asynchronous communications adapter 1-223 BASIC reserved 2-7 DOS reserved 2-21 special 2-7 lOR (I/O Read Command), I/O channel 1-20 lOW (I/O Write Command), I/O channel 1-21 IRQ2-IRQ7 (Interrupt Request 2 to 7), I/O channel 1-20 J joy stick, positions 1-221 schematic diagram 1-215 jumper module, asynchronous communications adapter 1-249 Index J-13 K keyboard extended codes, alt 2-15 break 2-16 caps lock 2-16 ctrl 2-15 pause 2-17 print screen 2-17 scroll lock 2-16 shift 2-15 shift key priorities 2-16 shift states 2-15 system reset 2-16 keyboard 1-73 BASIC screen editor special functions 2-20 character codes 2-11 commonly used functions 2-18 diagram 1-76 DOS special functions 2-20 encoding 2-11 extended functions 2-14 interface block diagram 1-75 interface connector specifications 1-78 scan codes 1-77 specifications E-l L light pen connector specifications 1-156 line control register 1-235 line feed (printer) 1-102 line status register 1-239 logic diagrams D-l M math coprocessor 1-33 block diagram 1-37 control unit 1-37 control word 1-40 J-14 Index data types 1-34 exception pointers 1-41 FABS 1-44 FADD 1-44 FBLD 1-45 FBSTP 1-46 FCHS 1-46 FCLEX/FNCLEX 1-46 FCOM 1-47 FCOMP 1-47 FCOMPP 1-48 FDECSTP 1-48 FDISI/FNDISI 1-48 FDIV 1-49 FDIVR 1-50 FENI/FNENI 1-51 FFREE 1-51 FICOM 1-51 FICOMP 1-52 FILD 1-52 FINCSTP 1-52 FINIT/FNINIT 1-53 FIST 1-54 FISTP 1-54 FLD 1-55 FLDCW 1-55 FLDENV 1-56 FLDLG2 1-56 FLDLN2 1-56 FLDL2E 1-57 FLDL2T 1-57 FLDPI 1-57 FLDZ 1-58 FLDI 1-58 FMUL 1-59 FNOP 1-60 FPATAN 1-60 FPREM 1-60 FPTAN 1-61 FRND INT 1-61 FRS TOR 1-61 Index J-15 FSAVE/FNSAVE 1-62 FSCALE 1-62 FSQRT 1-62 FST 1-63 FSTCW/FNSTCW 1-63 FSTENV/FNSTENV 1-64 FSTP 1-64 FSTSW/FNSTSW 1-65 FSUB 1-65 FSUBR 1-66 FTST 1-67 FWAIT 1-68 FXAM 1-68 FXCH 1-69 FXTRACT 1-70 FYL2X 1-70 FYL2XPI 1-71 F2XMl 1-71 hardware interface 1-35 instruction set 1-43 interconnection 1-36 number system 1-42 programming interface 1-34 register stack 1-38 status word 1-39 tag word 1-41 memory expansion options, 1-205 DIP module start address 1-208 memory module description 1-206 memory module pin configuration 1-207 memory option switch settings G-l R/W memory operating characteristics 1-206 switch-configurable start address 1-208 memory locations, reserved 2-8 memory map, BIOS 2-9 system 1-13 Memory Read Command (MEMR), I/O channel 1-21 memory switch settings, G-l extender card G-I memory options G-l system board G-l J-16 Index Memory Write Command (MEMW), I/O channel 1-21 (MEMR) Memory Read Command, I/O channel 1-21 (MEMW) Memory Write Command, I/O channel 1-21 microprocessor (see Intel 8088 microprocessor) mode control and status register 1-149 mode select register 1-151 modem control register 1-244 modem status register 1-246 monochrome display 1-129 monochrome display and printer adapter 1-123 monochrome display adapter 1-123 6845 CRT control port 1-127 6845 CRT status port 1-127 block diagram 1-124 character attributes 1-138 connector specifications 1-128 I/O address and bit map 1-127 programming considerations 1-125 monochrome display, 1-129 operating characteristics 1-129 specifications E-3 Motorola 6845 CRT Controller, (see color/graphics monitor adapter) (see monochrome display adapter) N National Semiconductor INS8250 Asynchronous (see asynchronous communications adapter) functional pin description 1-229 input signals 1-229 input/output signals 1-233 output signals 1-232 null (printer) 1-102 o one bit delay mode register 1-289 operating mode register 1-289 OSC (oscillator) 1-19 Oscillator (OSC), I/O channel 1-19 over-voltage/over-current (expansion unit) 1-84 over-voltage/over-current (system unit) 1-27 Index J-17 p parameter passing (ROM BIOS) 2-3 pause (keyboard extended code) 2-17 power good signal (expansion unit) 1-84 power good signal (system unit) 1-27 power supply (expansion unit) 1-82 connectors 1-83 input requirements 1-82 over-voltage/current protection 1-84 pin assignments 1-83 power good signal 1-83 Vac output 1-82 Vdc output 1-82 power supply (system unit) 1-23 connectors and pin assignments 1-26 input requirements 1-24 over-voltage/current protection 1-27 pin assignments 1-26 power good signal 1-27 Vac output 1-25 Vdc output 1-25 print screen (keyboard extended code) 2-17 printer adapter, 1-117 block diagram 1-118 connector specifications 1-122 programming considerations 1-119 printer control codes, 1-101 1I8-inch line feeding 1-104 1920 bit-image graphics mode 1-110 480 bit-image graphics mode 1-107 7!7 2-inch line feeding 1-104 960 bit-image graphics mode 1-109 960 bit-image graphics mode normal speed 1-110 bell 1-102 cancel 1-103 cancel ignore paper end 1-105 cancel skip perforation 1-109 carriage return 1-102 clear printer buffer 1-110 compressed 1-103 compressed off 1-103 double strike 1-106 double strike off 1-107 double width 1-103, 1-110 J-18 Index double width off 1-103 emphasized 1-106 emphasized off 1-106 escape 1-103 form feed 1-102 home head 1-105 horizontal tab 1-102 ignore paper end 1-104 line feed 1-102 null 1-102 printer deselected 1-103 printer selected 1-103 select character set 1 1-104 select character set 2 1-104 set horizontal tab stops 1-106 set lines per page 1-106 set skip perforation 1-109 set variable line feeding 1-105, 1-107 set vertical tabs 1-105 starts variable line feeding 1-105 subscript/superscript 1-109 subscript/superscript off 1-109 underline 1-104 unidirectional printing 1-109 vertical tab 1-102 printer deselected (printer) 1-103 printer selected (printer) 1-103 printer, 1-91 additional specifications 1-93 cable 1-91 connector pin assignment 1-97 control codes 1-101 graphic character set 1 1-113 graphic character set 2 1-115 interface signal descriptions 1-96 matrix character set 1-111 modes 1-100 parallel interface 1-96 parallel interface timirtg diagram 1-96 specifications 1-92, E-3 switch locations 1-94 switch settings 1-94 processor (see Intel 8088 micrprocessor) programmable baud rate generator 1-237 Index J-19 programming considerations, asynchronous communications adapter 1-234 binary synchronous communications adapter 1-259 color/graphics monitor adapter 1-131 diskette drive adapter 1-159 extender card 1-86 fixed disk drive adapter 1-187 monochrome display adapter 1-123 printer adapter 1-123 receiver card 1-88 SDLC adapter 1-281 prototype card, 1-217 block diagram 1-218 external interface 1-222 I/O channel interface 1-219 layout 1-219 system loading and power limitations 1-221 Q quick reference, character set C-12 R receiver buffer register 1-24 7 receiver card, 1-88 block diagram 1-89 programming considerations 1-86 register, 6845 description (color/graphic adapter) 1-146 color select (color/graphic adapter) 1-147 command status 0 (diskette drive adapter) 1-172 command status 1 (diskette drive adapter) 1-173 command status 2 (diskette drive adapter) 1-174 command status 3 (diskette drive adapter) 1-175 data (fixed disk drive adapter) 1-192 data transfer mode (SDLC) 1-288 digital output (diskette drive adapter) 1-161 DPC (diskette drive adapter) 1-175 interrupt enable (asynchronous communications) 1-243 interrupt identification (asynchronous communications) 1-241 line control (asynchronous communications) 1-234 line status (asynchronous communications) 1-239 mode control and status (color/graphics) 1-149 J-20 Index mode select ( color/graphics) 1-151 modem control (asynchronous communications) 1-244 modem status (asynchronous communications) 1-246 one-bit delay mode (SDLC) 1-289 operating mode (SDLC) 1-286 receiver buffer (asynchronous communications) 1-247 serial I/O mode (SDLC) 1-288 status (color/graphics) 1-153 status (fixed disk drive adapter) 1-187 transmitter holding (asynchronous communications) 1-248 reserved interrupts, BASIC and DOS 2-7 reserved memory locations 2-7 Reset Drive (RESET DRV), I/O channel 1-19 RESET DRV (Reset Drive), I/O channel 1-19 RF modulator connector specifications 1-156 ROM BIOS, 2-2 Cassette A-74 Fixed Disk A-87 System A-2 ROM, adapter cards with 2-10 RS-232C, interface standards F-2 s scan codes, keyboard 1-77 scroll lock (keyboard extended code) 2-16 SDLC (see synchronous data link control) select character set 1 (printer) 1-104 select character set 2 (printer) 1-104 sense bytes, fixed disk drive adapter 1-189 serial I/O mode register 1-288 set horizontal tab stops (printer) 1-106 set lines per page (printer) 1-106 set skip perforation (printer) 1-109 set variable line feeding (printer) 1-105, 1-107 set vertical tabs (printer) 1-105 shift (keyboard extended code) 2-15 shift key priorities (keyboard code) 2-16 shift states (keyboard extended code) 2-15 software interrupt listing 2-4 speaker connector 1-23 speaker drive system 1-23 speaker interface 1-23 Index J-21 specifications, 80 CPS printers E-3 color display E-2 expansion unit E-2 keyboard E-l monochrome display E-3 printer 1-92 printer (additional) 1-93 system unit E-l stack area 2-7 starts variable line feeding (printer) 1-104 status register, color/graphics monitor adapter 1-154 fixed disk drive adapter 1-189 synchronous data link control adapter 1-282 sUbscript/ superscript (printer) 1-109 subscript/superscript off (printer) 1-109 switch settings, G-l diskette drive G-l display adapter type G-l extender card G-l memory options G-l printer 1-91 system board G-l system board memory G-l synchronous data link control communications adapter, 1-271 8253-5 interval timer control word 1-285 8253-5 progammable interval timer 1-281 8255A-5 port A assignments 1-280 8255A-5 port B assignments 1-280 8255A-5 port C assignments 1-281 8255A-5 programmable peripheral interface 1-280 8273 command phase flow chart 1-292 8273 commands 1-291 8273 control/read/write registers 1-275 8273 data interfaces 1-276 8273 elements of data transfer interface 1-276 8273 mode register commands 1-288 8273 modem control block 1-277 8273 modem control port A 1-277 8273 modem control port B 1-278 8273 modem interface 1-277 8273 protocol controller operations 1-271 8273 protocol controller structure 1-273 8273 register selection 1-274 8273 SDLC protocol controller block diagram 1-273 J-22 Index 8273 transmit/receiver timing 1-279 block diagram 1-271 command phase 1-290 connector specifications 1-299 control/read/write logic 1-274 data transfer mode register 1-288 device addresses 1-297 execution phase 1-293 general receive 1-294 initialization/configuration commands 1-286 initializing the SDLC adapter 1-283 interface information 1-298 interrupt information 1-297 one bit delay code register 1-289 operating mode register 1-286 partial byte received codes 1-296 processor interface 1-274 programming considerations 1-281 protocol control module features 1-272 protocol controller operations 1-272 result code summary 1-296 result phase 1-291 selective receive 1-295 serial data timing block 1-279 serial I/O mode register 1-288 status register format 1-282 transmit 1-294 system block diagram 1-2 system board, 1-3 component diagram 1-7 data flow 1-8 R/W memory operating characteristics 1-202 switch settings G-l System Clock (CLK), I/O channel 1-19 system memory map 1-13 system reset (keyboard extended code) 2-16 system ROM BIOS A-2 system unit, 1-3 cassette interface 1-31 I/O channel 1-17 I/O channel diagram 1-18 keyboard interface 1-78 power supply 1-23 speaker interface 1-22 specifications E-l system board 1-3 Index J-23 T T/C (Terminal Count), I/O channel 1-22 transmitter holding register 1-248 u underline (printer) 1-104 unidirectional printer (printer) 1-109 v Vac output, expansion unit 1-82 system unit 1-25 Vdc output, expansion unit 1-82 system unit 1-25 vectors with special meanings 2-5 vertical tab (printer) 1-102 voltage interchange, asynchronous communications adapter 1-228 Numerics 1/8 inch line feeding (printer) 1-104 1920 bit-image graphics mode (printer) 1-110 480 bit-image graphics mode (printer) 1-107 6845, (see color/graphics monitor adapter) (see monochrome display adapter) 7/72 inch line feeding (printer) 1-104 8088, (see Intel 8088 microprocessor) 8250, (see asynchronous communications adapter) 8253-5, (see synchronous data link control adapter) 8255A 1-12 8255A-5, (see synchronous data link control adapter) 8273, (see synchronous data link control adapter) 960 bit-image graphics mode (printer) 1-109 960 bit-image graphics mode normal speed (printer) 1-110 J-24 Index ------- ---------- - ------_.- The Personal Computer fIardvvare Library Product Comment Form TECHNICAL REFERENCE 1502234 Your comments assist us in improving our products. IBM may use and distribute any of the information you supply in anyvvay it believes appropriate vvithout incurring any obligation vvhatever. You may, of course, continue to use the information you supply. For prompt resolution to questions regarding set up, operation, program support, and nevv program literature, contact the Authorized IBM Personal Computer Dealer in your area. Comments: If you vvish a reply, provide your name and address in this space. Name _____________________ Address _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ City Zip Code _ _ _ _ __ State ____________ 111111 NO POSTAGE NECESSARY IF MAILED IN THE UNITED STATES BUSINESS REPLY MAIL FIRST CLASS PERMIT NO. 123 BOCA RATON, FLORIDA 33432 POSTAGE WILL BE PAID BY ADDRESSEE IBM PERSONAL COMPUTER SALES & SERVICE P.O. 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FLORIDA 33432 POSTAGE WILL BE PAID BY ADDRESSEE IBM PERSONAL COMPUTER SALES & SERVICE P.O. BOX 1328-C BOCA RATON, FLORIDA 33432 a1a4 PIO:::! aldelS lOU Op aseald ade.l -------- ---_.--- ------------ The Personal Computer fIardvvare Library Product Comment Form TECHNICAL REFERENCE 1502234 Your comments assist us in improving our products. IBM may use and distribute any of the information you supply in anyvvay it believes appropriate vvithout incurring any obligation vvhatever. You may, of course, continue to use the information you supply. For prompt resolution to questions regarding set up, operation, program support, and nevv program literature, contact the Authorized IBM Personal Computer Dealer in your area. Comments: If you vvish a reply, provide yourname and address in this space. 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