1502237_PC_XT_Technical_Reference_Apr83 1502237 PC XT Technical Reference Apr83

User Manual: 1502237_PC_XT_Technical_Reference_Apr83

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LIMITED WARRANTY
The International Business Machines Corporation warrants this IBM Personal
Computer Product to be in good working order for a period of 90 days from the
date of purchase from IBM or an authorized IBM Personal Computer dealer.
Should this Product fail to be in good working order at any time during this
90-day warranty period, IBM wilL at its option, repair or replace this Product
at no additional charge except as set forth below. Repair parts and replacement
Products will be furnished on an exchange basis and will be either reconditioned
or new. All replaced parts and Products become the property of IBM. This
limited warranty does not include service to repair damage to the Product
resulting from accident, disaster, misuse. abuse, or non-IBM modification of
the Product.
Limited Warranty service may be obtained by delivering the Product during the
90-day warranty period to an authorized IBM Personal Computer dealer or IBM
Service Center and providing proof of purchase date. If this Product is delivered
by mail, you agree to insure the Product or assume the risk of loss or damage in
transit, to prepay shipping charges to thc warranty service location and to use the
original shipping container or equivalent. Contact an authorized IBM Personal
Computer dealer or write to IBM Personal Computer. Sales and Service, P.O.
Box I328-W, Boca Raton, Florida 33432. for further information.
ALL EXPRESS AND IMPLIED WARRANTIES FOR THIS PRODUCT
INCLUDING THE WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE, ARE LIMITED IN DURATION TO A
PERIOD OF 90 DAYS FROM THE DATE OF PURCHASE, AND NO
WARRANTIES, WHETHER EXPRESS OR IMPLIED, WILL APPLY AFTER
THIS PERIOD. SOME STATES DO NOT ALLOW LIMITATIONS ON HOW
LONG AN IMPLIED WARRANTY LASTS. SO THE ABOVE LIMIT ATIONS
MA Y NOT APPLY TO YOu.
IF THIS PRODUCT IS NOT IN GOOD WORKING ORDER AS WARRANTED
ABOVE, YOUR SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT
AS PROVIDED ABOVE. IN NO EVENT WILL IBM BE LIABLE TO YOU FOR
ANY DAMAGES, INCLUDING ANY LOST PROFITS, LOST SAVINGS OR
OTHER INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF
THE USE OF OR INABILITY TO USE SUCH PRODUCT, EVEN IF IBM OR
AN AUTHORIZED IBM PERSONAL COMPUTER DEALER HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, OR FOR ANY
CLAIM BY ANY OTHER PARTY.
SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMIT A TION OF
INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR CONSUMER
PRODUCTS, SO THE ABOVE LIMITATIONS OR EXCLUSIONS MAY NOT
APPLY TO YOU.
THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS, AND YOU MAY
ALSO HAVE OTHER RIGHTS WHICH MAY VARY FROM STATE TO ST ATE.

------ ----- ----

--_.-

Personal Computer XT
Hardware Reference
Library

Technical
Reference

FEDERAL COMMUNICATIONS COMMISSION

RADIO FREQUENCY INTERFERENCE
STATEMENT

W ARNIN G:

This equipment has been certified to comply with
the limits for a Class B computing device,
pursuant to Subpart J of Part 15 of FCC rules,
Only peripherals (computer input/output devices,
terminals, printers, etc.) certified to comply with
the Class B limits may be attached to this
computer. Operation with non-certified
peripherals is likely to result in interference to
radio and TV reception.

Notice: As sold by the manufacturer, the IBM Prototype Card
does not require certification under the FCC's rules for Class B
devices. The user is responsible for any interference to radio or TV
reception which may be caused by a user-modified prototype card.
CAUTION:

This product is equipped with a UL-listed and
CSA-certified plug for the user's safety. It is to be
used in conjunction with a properly grounded
115 Vac receptacle to avoid electrical shock.

Revised Edition (April 1983)
Changes are periodically made to the information herein; these changes will be
incorporated in new editions of this publication.
Products are not stocked at the address below. Requests for copies of this product and for
technical information about the system should be made to your authorized IBM Personal
Computer dealer.
A Reader's Comment Form is provided at the back of this publication. If this form has
been removed, address comments to: IBM Corp., Personal Computer, P.O. Box 1328-C,
Boca Raton, Florida 33432. IBM may use or distribute any of the information you supply
in any way it believes appropriate without incurring any obligations whatever.
©

Copyright International Business Machines Corporation, 1981, 1982, 1983

PREFACE

The IBM Personal Computer XT Technical Reference manual
describes the hardware design and provides interface information
for the IBM Personal Computer XT. This publication also has
information about the basic input/output system (BIOS) and
programming support.
The information in this publication is both introductory and for
reference, and is intended for hardware and software designers,
programmers, engineers, and interested persons who need to
understand the design and operation of the computer.
You should be familiar with the use of the Personal Computer
XT, and you should understand the concepts of computer
architecture and programming.
This manual has two sections:
"Section 1: Hardware" describes each functional part of the
system. This section also has specifications for power, timing, and
interface. Programming considerations are supported by coding
tables, command codes, and registers.
"Section 2: ROM BIOS and System Usage" describes the basic
input/output system and its use. This section also contains the
software interrupt listing, a BIOS memory map, descriptions of
vectors with special meanings, and a set of low memory maps. In
addition, keyboard encoding and usage is discussed.
The publication has seven appendixes:
Appendix A:
Appendix B:
Appendix C:
Appendix D:
Appendix E:
Appendix F:
Appendix G:

ROM BIOS Listings
8088 Assembly Instruction Set Reference
Of Characters, Keystrokes, and Color
Logic Diagrams
Specifications
Communications
Switch Settings

A glossary and bibliography are included.

iii

Prerequisite Publication:

Guide to Operations for the IBM Personal Computer XT
Part Number 6936810
Suggested Reading:

BASIC for the IBM Personal Computer
Part Number 6025010
Disk Operating System (DOS) for the IBM Personal Computer
Part Number 6024061
Hardware Maintenance and Service for the IBM Personal
Computer XT
Part Number 6936809
MACRO Assembler for the IBM Personal Computer
Part Number 6024002
Related publications are listed in the bibliography.

iv

TABLE OF CONTENTS

Section 1: Hardware
IBM Personal Computer XT System Unit .............
IBM Personal Computer Math Coprocesser ............
IBM Keyboard ....................................
IBM Expansion Unit ...............................
IBM SO CPS Printers ..............................
IBM Printer Adapter ...............................
IBM Monochrome Display and Printer Adapter ........
IBM Monochrome Display ..........................
IBM Color/Graphics Display Adapter ................
IBM Color Display ................................
IBM 5-W' Diskette Drive Adapter ...................
IBM 5-W' Diskette Drive ...........................
Diskettes .........................................
IBM Fixed Disk Drive Adapter ......................
IBM 10MB Fixed Disk Drive .......................
IBM Memory Expansion Options ....................
IBM Game Control Adapter .........................
IBM Prototype Card ...............................
IBM Asynchronous Communications Adapter. . . . . . . . ..
IBM Binary Synchronous Communications Adapter .....
IBM Synchronous Data Link Control (SDLC)
Communication Adapter ..........................
IBM Communications Adapter Cable .................

1-3
1-25
1-65
1-71
I-S1
1-107
1-113
1-121
1-123
1-149
1-151
1-175
1-177
1-179
1-195
1-197
1-203
1-209
1-215
1-245
1-265
1-295

Section 2:ROM BIOS and System Usage
ROM BIOS ....................................... 2-2
Keyboard Encoding and Usage ...................... 2-11

Appendix A: ROM BIOS Listings .............. A-I
System BIOS ..................................... A-2
Fixed Disk BIOS .................................. A-S5

Appendix B: 8088 Assembly Instruction
Set Reference ................................. B-1
v

Appendix C: Of Characters, Keystrokes,
and Colors .................................... C-l
Appendix D: Logic Diagrams ................... D-l
System Board .....................................
Type 1 Keyboard .................................
Type 2 Keyboard .................................
Expansion Board ..................................
Extender Card ....................................
Receiver Card ....................................
Printer ...........................................
Printer Adapter ...................................
Monochrome Display Adapter ......................
Color/Graphics Monitor Adapter ....................
Color Display ....................................
Monochrome Display ..............................
5-Y

> 6 6N

Ln~'--

+ (9 (9 +
'<:j""MN"-"
C

c r:: c

0::0::0::0::

u
,,-0-0-0
-0 § §

>

>

0

0

N

LO'-""'"-

+(9(9+

V" M" C"\I" -""
C C C c

0::0::0::0::

~ \kh{



B
u
>
0C:

'"

'"c

0

u

'"Q)
t:
-"


Ci
.<:

u

C

0

0

:::!: St;;

.n

8u

Q)

c

e: U
~

Q)

....0
U
e:

0

c..

...
'"
s
'
"
> 0 0
(J)eD c..
E
.... "E

Q)

e:
-"
e:

0

Ci u
-0

Q)

...

Q)

x S

LL

0

c..

CD
....

B
u
~

e: c

:J 0

E':

"
1;;

>

s0
Q)

Ulc..

Power Supply and Connectors

System Unit 1-23

Over-Voltage/Over-Current Protection
Voltage Nominal Vac

110

Type Protection
Fuse

Rating Amps

5

Power On/Off Cycle: When the supply is turned off for a
minimum of 1.0 second, and then turned on, the power-good
signal will be regenerated.
The power-good signal indicates that there is adequate power to
continue processing. If the power goes below the specified levels,
the power-good signal triggers a system shutdown.
This signal is the logical AND of the dc output-voltage sense
signal and the ac input voltage fail signal. This signal is
TTL-compatible up-level for normal operation or down-level for
fault conditions. The ac fail signal causes power-good to go to a
down-level when any output voltage falls below the regulation
limits.
The dc output-voltage sense signal holds the power-good signal at
a down level (during power-on) until all output voltages have
reached their respective minimum sense levels. The power-good
signal has a tum-on delay of at least 100 ms but no greater than
500ms.
The sense levels of the dc outputs are:
Output
(Vdc)

+5
-5
+12
-12

1-24

Minimum
(Vdc)

+4.5
-4.3
+10.8
-10.2

System Unit

Sense Voltage Nominal
(Vdc)

+5.0
-5.0
+12.0
-12.0

Maximum
(Vdc)

+5.5
-5.5
+13.2
-13.2

IBM Personal Computer Math
Coprocessor

The IBM Personal Computer Math Coprocessor enables the IBM
Personal Computer to perform high speed arithmetic, logarithmic
functions, and trigonometric operations with extreme accuracy.
The coprocessor works in parallel with the processor. The parallel
operation decreases operation time by allowing the coprocessor to
do mathematical calculations while the processor continues to do
other functions.
The first five bits of every instruction opcode for the coprocessor
are identical (11011 binary). When the processor and the
coprocessor see this instruction opcode, the processor calculates
the address, of any variables in memory, while the coprocessor
checks the instruction. The coprocessor will then take the memory
address from the processor if necessary. To access locations in
memory, the coprocessor takes the local bus from the processor
when the processor finishes its current instruction. When the
coprocessor is finished with the memory transfer, it returns the
local bus to the processor.
The IBM Math Coprocessor works with seven numeric data types
divided into the three classes listed below.
•

Binary integers (3 types)

•

Decimal integers (1 type)

•

Real numbers (3 types)

Coprocessor

1-25

Programming Interface
The coprocessor extends the data types, registers, and instructions
to the processor.
The coprocessor has eight 80-bit registers which provide the
equivalent capacity of 40 16-bit registers found in the processor.
This register space allows constants and temporary re.sults to be
held in registers during calculations, thus reducing memory access
and improving speed as well as bus availability. The register space
can be used as a stack or as a fixed register set. When used as a
stack, only the top two stack elements are operated on: when used
as a fixed register set, all registers are operated on. The Figure
below shows representations of large and small numbers in each
data type.
Data Type

Bits

Word Integer
Sh ort Integer
Long Integer
Packed Oecimal
Short Real*
Long Real*
Temporary Real

16
32
64
80
32
64
80

Significant
Digits (Decimal)
4
9
18
18
6-7
15-16
19

Approximate Range (decimal)
·32,768 source
ST 

..

E

~
:>-

CI)

r

2Z2

Data latch
and Disable
Circuits

EXT DISABLE
00-07

-

C")

'III ~

co

::0
::0
~

~

~

Data
Buffer

T

-DlR ENABLE

----

Extender Card Block Diagram

1-76 Expansion Unit

L

Bus Direction
and Enable fControl

----

Receiver Card
The receiver card is a four-plane card that fits in expansion slot 8
of the expansion unit. The receiver card redrives the I/O channel
to provide sufficient power for additional options and to avoid
capacitive effects. Directional control logic is contained on the
receiver card to resolve contention and direct data flow on the I/O
channel. Steering signals are transmitted back over the expansion
cable for use on the extender card.

Receiver Card Programming Considerations
Several registers associated with the expansion option are
programmable and readable for diagnostic purposes. The
following figure indicates the locations and functions of the
registers on the receiver card.

Location

Function

Memory FXXXX(*)
Port 214
Port 214
Port 215
Port 215
(*) Example:

Write to memory to latch address bits
Write to latch data bus bits (DO - 07)
Read data bus bits (DO - D7)
Read high-order address bits (A8 - A 15)
Read low-order address bits (AD - A7)

Write to memory location F123:4=OO
Read Port 215 =12
Read Port 216 =34

(All values in hex)

The expansion unit is automatically enabled upon power-up. The
expansion unit and the system unit will be written to, if the
expansion unit is not disabled when writing to FXXXX. However,
the system unit and the expansion unit are read back separately.

Expansion Unit

1-77

,....--

,....--

Control
Bus
Buffer

Control Bus

'l//

~

~

....

=

00-07

[

0:
0:

=

'/.

Bus Direction
and Enable
Control

-

L

'""

><
~

Data
Bus
Buffer

1jl

c·

:::I

U
0:

C"">

~

:::I

~

~

N

<0

Z

...

Data latch
Circuit

-y

..

..

~~
~
AO·A19
'7

Address
Buffer

"---

~

~
Control Signal

r///

'----

Receiver Card Block Diagram

1-78

1/0 Address
Decode

rz

Expansion Unit

Expansion Unit Interface Information
The extender card and receiver card rear-panel connectors are the
same. Pin and signal assignments for the extender and receiver
cards are shown below.

21
42
62
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

\@ ................... @]J.1
@ • • • • • • • • • • • • • • • • • • • @
@ • • • • • • • • • • • • • • • • • • @

Signal
+E IRQ6
+E DRQ2
+E DIR
+E ENABLE
+E ClK
-E MEM IN EXP
+E A17
+E A16
+EA5
-E OACKO
+E A15
+E All
+EA10
+EA9
+E Al
+EA3
-E OACKl
+E A4
-E OACK2
-E lOW
+E A13

Pin
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

Signal
+E D5
+E DRQl
+E DRQ3
RESERVED
+E ALE
+E T/C
+E RESET
+EAEN
+E A19
+E A14
+E A12
+E A18
-E MEMR
-E MEMW
+EAO
-E OACK3
+EA6
-E lOR
+EA8
+EA2
+EA7

Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62

22
43

Signal
+E IRQ7
+E D6
+E I/O CH RDY
+E IRQ3
+E D7
+E 01
-E I/O CH CK
+E IRQ2
+E 00
+E 02
+E 04
+E IRQ5
+E IRQ4
+E 03
GND
GNO
GND
GNO
GND
GND

E = Extended

Connector Specifications

Expansion Unit

1-79

Notes:

1-80

Expansion Unit

IBM 80 CPS Printers

The IBM 80 CPS (characters-per-second) Printers are
self-powered, stand-alone, tabletop units. They attach to the
system unit through a parallel signal cable, 6 feet in length. The
units obtain ac power from a standard wall outlet (120 Vac). The
printers are 80 cps, bidirectional, wire-matrix devices. They print
characters in a 9 by 9 dot matrix with a 9-wire head. They can
print in a compressed mode of 132 characters per line, in a
standard mode of 80 characters per line, in a double width,
compressed mode of 66 characters per line, and in a double width
mode of 40 characters per line. The printers can print double-size
characters and double-strike characters. The printers print the
standard ASCII, 96-character, uppercase and lowercase character
sets. A printer without an extended character set also has a set of
64 special block graphic characters.
The IBM 80 CPS Graphics Printer has additional capabilities
including: an extended character set for international languages,
subscript, superscript, an underline mode, and programmable
graphics.
The printers can also accept commands setting the line-feed
control desired for the application. They attach to the system unit
through the printer adapter or the combination monochrome
display and printer adapter. The cable is a 25-lead shielded cable
with a 25-pin D-shell connector at the system unit end, and a
36-pin connector at the printer end.

Printers

1·81

(1 )
(2)
(3)
(4)
(5)
(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

Print Method:
Print Speed:
Print Direction:
Number of Pins in Head:
Line Spacing:
Pri nti ng Characteristics
Matrix:
Character Set:
Graphic Character:
Printing Sizes

Normal:
Double Width:
Compressed:
Double Width-Compressed:
Media Handling:
Paper Feed:
Paper Width Range:
Copies:

Paper Path:
Interfaces:
Standard:
Inked Ribbon:
Color:
Type:
Life Expecta ncy:
Environmental Conditions
Operating Temperature Range:
Operating Humidity:
Power Requirement:
Voltage:
Current:
Power Consumption:
Physical Characteristics:
Height:
Width:
Depth:
Weight:

Printer Specifications

1-82

Printers

Serial-impact dot matrix
80 cps
Bidirectional with logical seeking
9
1/16 inch (4.23 mm) or programmable
9x9
Full 96-character ASCII with descenders
plus 9 international characters/symbols.
See "Additional Printer Specifications"

Characters
per inch
10

5
16.5
8.25

Maximum
characters
per inch
80
40
132
66

Adjustable sprocket pin feed
4 inch (101.6 mm) to 10 inch (254 mm)
One original plus two carbon copies (total
thickness not to exceed 0.012 inch (0.3 mm)).
Minimum paper thickness is 0.0025 inch
(0.064 mm).
Rear
Parallel 8-bit
Data and Control Lines
Black
Cartridge
3 million characters

41 to 95° F (5 to 35° C)
10 to 80% non-condensing
120 Vac, 60 Hz
1 A maximum
100 VA maximum
4.2 inches (107 mm)
14.7 inches (374 mm)
12.0 inches (305 mm)
12 pounds (5.5 kg)

(6)

(6)

Printing Characteristics:
IBM 80 CPS Matrix Printer
Graphics
IBM 80 CPS Graphics Printer
Printing Characteristics:
Extra Character Set.

64 block characters.

Set 1
Additional ASCII numbers 160 to 175
contain European characters. Numbers 176
to 223 contain graphic characters .. Numbers
224 to 239 contain selected Greek
characters. Numbers 240 to 255 contain
math and extra symbols.
Set 2
The difference in set 2 are ASCII numbers 3,
4, 5, 6, and 21. ASCII numbers 128 to 175
contain European characters.

Graphics
(7)

There are 20 block characters and
programmable graphics.

Printing Sizes:

Subscript:
Superscript:

Characters
per inch
10
10

Maximum
characters
per line
80
80

Additional Printer Specifications

Printers

1-83

Setting the DIP Switches
There are two DIP switches on the control circuit board. In order
to satisfy the user's specific requirements, desired control modes
are selectable by the DIP switches. The functions of the switches
and their preset conditions at the time of shipment are as shown in
the following figures.
DIP Switch 2

DIP Switch 1

Location of Printer DIP Switches
Switch
Number

Function

On

Off

Factory-Set
Condition

1-1

Not Applicable

-

-

On

1-2

CR

Print Only

Print &
Line Feed

On

1-3

Buffer Full

Print Only

Print &
Line Feed

Off

1-4

Cancel Code

Invalid

Valid

Off

1-5

Delete Code

Invalid

Valid

On

1-6

Error

Sounds

Does Not
Sound

On

1-7

Character Generator
(Graphic Pattern Select)

NA

Graphic
Patterns
Select

Off

1-8

SLCT IN Signal Fixed
Internally

Fixed

Not Fixed

On

Functions and Conditions of DIP Switch 1 (Matrix)

1-84

Printers

Switch
Number

Function

On

Factory-Set
Condition

Off

2-1

Not Applicable

On

2-2

Not Applicable

On

2-3

Auto Feed XT Signal

2-4

Coding Table Select

Fixed
Internally

Not Fixed
Internally

Off

Standard

Off

N.A.

Functions and Conditions of DIP Switch 2 (Matrix)

Switch
Number

Function

On

Factory-Set
Condition

Off

1 -1

Not Applicable

-

-

On

1-2

CR

Print Only

Print &
Line Feed

On

1-3

Buffer Full

Print Only

Print &
Line Feed

Off

1-4

Cancel Code

Invalid

Valid

Off

1-5

Not Applicable

-

-

On

1-6

Error Buzzer

Sound

Does Not
Sound

On

1-7

Character Generator

Set 2

Set 1

Off

1-8

SLCT IN Signal

Fixed
Internally

Not Fixed
Internally

On

Functions and Conditions of DIP Switch 1 (Graphics)

Switch
Number

Function

On

Factory-Set
Condition

Off

2-1

Form Length

12 Inches

11 Inches

Off

2-2

Line Spacing

1/8 Inch

1/6 Inch

Off

2-3

Auto Feed XT Signal

Fixed
Internally

Not Fixed
Internally

Off

2-4

1 Inch Skip Over Perforation

Valid

Not Valid

Off

Functions and Conditions of DIP Switch 2 (Graphics)

Printers

1-85

Parallel Interface Description
Specifications:
•

Data transfer rate: 1000 cps (maximum)

•

Synchronization: By externally-supplied STROBE pulses.

•

Handshaking ACKNLG or BUSY signals.

•

Logic level: Input data and all interface control signals are
compatible with the TTL level.

Connector: Plug: 57-30360 (Amphenol)
Connector pin assignment and descriptions of respective interface
signals are provided on the following pages.
Data transfer sequence:
BUSY--""
ACKNLG
0.5 fJS (Minimum)

DATA--~

STROBE

---f---.

0.5 fJS (Minimum)
0.5 fJS (Minimum)

Parallel Interface Timing Diagram

1-86

Printers

Signal
Pin No.

Return
Pin. No.

Signal

Direction

Description

1

19

STROBE

In

STROBE pulse to read
data in. Pulse width must
be more than 0.5 f.1S at
receiving terminal. The
signal level is normally
·'high"; read-in of delta is
performed at the "low"
level of this signal.

2
3
4
5
6
7
8
9

20
21
22
23
24
25
26
27

DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA

In
In
In
In
In
In
In
In

These signals represent
information of th e 1st to
8th bits of parallel data
respectively. Each signal
is at "high" level when
data is logical "1" and
"low" when logical "0."

10

28

ACKNLG

Out

Approximately 5 f.1S pulse;
"low" indicates that data
has been received and
the printer is ready to
accept other data.

11

29

BUSY

Out

A "high" signal indicates
that the printer cannot
receive data. The signal
becomes "high" in the
following cases:
1. During data entry.
2. During printing
operation.
3. In "offline" state.
4. During printer error
status.

1
2
3
4
5
6
7
8

Connector Pin Assignment and Descriptions of Interface Signals (Part 1 of 3)

Printers

1-87

Signal
Pin No.

Return
Pin No.

Signal

Direction

Description

12

30

PE

Out

A "high" signal indicates
that the printer is out of
paper.

13

-

SLCT

Out

This signal indicates that
the printer is in the
selected state.

14

-

AUTO
FEED XT

In

With this signal being at
"low" level, the paper is
automatically fed one line
after printing. (The signal
level can be fixed to
"low" with DIP SW pin
2-3 provided on the
control circuit board.)

15

-

NC

Not used.

16

-

OV

Logic GND level.

17

-

CHASSISGND

-

Printer chassis GND. In
the printer, the chassis
GND and the logic GND
are isolated from each
other.

18

-

NC

-

Not used.

19-30

-

GND

-

"Twisted- Pair Return"
signal; GND level.

31

-

INT

In

When the level of this
signal becomes "low" the
printer controller is reset
to its initial state and the
print buffer is cleared.
This signal is normally at
"high" level, and its
pulse width must be
more than 50 f.lS at the
receiving terminal.

Connector Pin Assignment and Descriptions of Interface Signals (Part 2 of 3)

1-88

Printers

Signal
Pin No.

Return
Pin No.

32

Signal

Direction
Out

The level of this signal
becomes "low" when the
printer is in "Paper End"
state, "Offline" state and
"Error" state.
Same as with pin
numbers 19 to 30.

33

-

GND

-

34

-

NC

-

35

36

Description

ERROR

Not used.
Pulled up to +5 Vdc
through 4.7 k-ohms
resistance.

-

SLCTIN

In

Data entry to the pri nter
is possible only when the
level of this signal is
"low". (Internal fixing can
be carried out with DIP
SW 1 -8. The condition at
the time of shipment is
set "low" for this signaL)

Notes: 1. "Direction" refers to the direction of signal flow as viewed from
the printer.
2. "Return" denotes "Twisted-Pair Return" and is to be connected at
signal-ground level.
When wiring the interface, be sure to use a twisted-pair cable for
each signal and never fail to complete connection on the return
side. To prevent noise effectively, these cables should be shielded
and connected to the chassis of the system unit and printer,
respectively.
3. All interface conditions are based on TTL level. Both the rise and
fall times of each signal must be less than 0.2 j1S.
4. Data transfer must not be carried out by ignoring the ACKNLG or
BUSY signal. (Data transfer to this printer can be carried out only
after confirming the ACKNLG signal or when the level of the
BUSY signal is "low.")

Connector Pin Assignment and Descriptions of Interface Signals (Part 3 of 3)

Printers

1-89

Printer Modes for the IBM 80 CPS
Printers
The IBM 80 CPS Graphics Printer can use any of the
combinations listed below, and the print mode can be changed at
any place within a line.
The IBM 80 CPS Matrix Printer cannot use the Subscript,
Superscript, or Underline print modes. The Double Width print
mode will affect the entire line with the matrix printer.
The allowed combinations of print modes that can be selected are
listed in the following table. Modes can be selected and combined
if they are in the same vertical column.
Printer Modes
Normal
Compressed
Emphasized
Double Strike
Subscript
Superscript
Double Width
Underline

1-90

Printers

X

X

X

X
X

X
X X
X
X

X

X
X
X

X

X
X

X
X
X
X

X
X

X
X

X
X
X

X
X

X
X

X

X
X
X

Printer Control Codes
On the following pages you will find complete codes for printer
characters, controls, and graphics. You may want to keep them
handy for future reference. The printer codes are listed in ASCII
decimal numeric order (from NUL which is 0 to DEL which is
127). The examples given in the Printer Function descriptions are
written in the BASIC language. The "input" description is given
when more information is needed for programming considerations.
ASCII decimal values for the printer control codes can be found
under "Printer Character Sets."
The descriptions that follow assume that the printer DIP switches
have not been changed from their factory settings.

Printers

1·91

Printer
Code

Printer Function

NUL

Null
Used with ESC B and ESC D as a list terminator. NUL is also used
with other printer control codes to select options (for example,
ESC S).
Example:
LPRINT CHR$ (0);

BEL

Bell
Sounds the printer buzzer for 1 second.
Example:
LPRINT CHR$ (7);

HT

Horizontal Tab
Tabs to the next horizontal tap stop. Tab stops are set with ESC D.
No tab stops are set when the printer is powered on. (Graphics
Printer sets a tab stop every 8 columns when powered on.)
Example:
LPRINT CHR$ (9);

LF

Line Feed
Spaces the paper up one line. Line spacing is 1 16-inch unless
reset by ESC A. ESC 0, ESC 1, ESC 2 or ESC 3.
Example:
LPRINT CHR$(1 0);

VT

Vertical Tab
Spaces the paper to the next vertical tab position. (Graphics Printer
does not allow vertical tabs to be set; therefore, the VT code is
treated as LF.)
Example:
LPRINT CHR$ (11);

FF

Form Feed
Advances the paper to the top of the next page.
Note: The location of the paper, when the printer is powered on,
determines the top of the page. The next top of page is 11
inches from that position. ESC C can be used to change the
page length.
Example:
LPRINT CHR$ (12);

CR

Carriage Return
Ends the line that the printer is on and prints the data remaining in
the printer buffer. (No Line Feed operation takes place.)
Note: IBM Personal Computer BASIC adds a Line Feed unless
128 is added [for example, CHR$ (141 )).
Example:
LPRINTCHR$ (13);

1-92

Printers

Printer
Code

Printer Function

so

Shift Out (Double Width)
Changes the printer to the Double Width print mode.
Note: A Carriage Return. Line Feed or DC4 cancels Double Width
print mode.
Example:
LPRINT CHR$(14);

SI

Shift In (Compressed)
Changes the printer to the Compressed Character print mode.
Example:
LPRINT CHR$(15);

DC1

Device Control 1 (Printer Selected)
(Graphics Printer ignores DC1)
Printer accepts data from the system unit. Printer DIP switch 1-8
must be set to the Off pOSition.
Example:
LPRINT CHR$(17);

DC2

Device Control 2 (Compressed Off)
Stops printing in the Compressed print mode.
Example:
LPRINT CHR(18);

DC3

Device Control 3 (Printer Deselected)
(Graphics Printer ignores DC3)
Printer does not accept data from the system unit. The system unit
must have the printer select line low. and DIP switch 1-8 must be in
the Off position.
Example:
LPRINT CHR$(19);

DC4

Device Control 4 (Double Width Off)
Stops printing in the Double Width print mode.
Example:
LPRINT CHR$(20);

CAN

Cancel
Clears the printer buffer. Control codes. except SO. remain in effect.
Example:
LPRINT CHR$ (24);

ESC

Escape
Lets the printer know that the next data sent is a printer command.
(See the following list of commands.)
Example:
LPRINT CHR$(27);

Printers

1-93

Printer
Code

Printer Function

ESC-

Escape Minus (Underline)
Format: ESC -;n;
(Graphics Printer only)
ESC - followed by a 1, prints all of the following data with an
underline.
ESC - followed by a 0 (zero), cancels the Underline print mode.
Example:
LPRINT CHRS(27);CHRS(45);CHRS(1);

ESCO

Escape Zero (1 18-lnch Line Feeding)
Changes paper feeding to 1/8 inch.
Example:
LPRINT CHRS(27);CHRS(48);

ESC 1

Escape One (7 n2-lnch Line Feeding)
Changes paper feed to 7/72 inch.
Example:
LPRINT CHRS(27);CHRS(49);

ESC2

Escape Two (Starts Variable Line Feeding)
ESC 2 is an execution command for ESC A. If no ESC A command
has been given, line feeding returns to 1/6-inch.
Example:
LPRINT CHRS(27);CHRS(50);

ESC3

Escape Three (Variable Line Feeding)
Format: ESC 3;n;
(Graphics Printer only)
Changes the paper feeding to n/216-inch. The example below sets
the paper feeding to 54/216 (1/4) inch. The value of n must be
between 1 and 255.
Example:
LPRINT CHRS(27);CHRS(51 );CHRS(54);

ESC 6

Escape Six (Select Character Set 2)
(Graphics Printer only)
Selects character set 2. (See "Printer Character Set 2. ")
Example:
LPRINT CHRS(27);CHRS(54);

ESC7

Escape Seven (Select Character Set 1.)
(Graphics Printer only)
Selects character set 1. (See "Printer Character Set 1. ")
Character set 1 is selected when the printer is powered on or reset.
Example:
LPRINT CHRS(27);CHR$(55);

ESC8

Escape Eight (Ignore Paper End)
Allows the printer to print to the end of the paper. The printer
ignores the Paper End switch.
Example:
LPRINT CHRS(27);CHRS(56);

1-94

Printers

Printer
Code

Printer Function

ESC 9

Escape Nine (Cancel Ignore Paper End)
Cancels the Ignore Paper End command. ESC 9 is selected when
the pri nter is powered on or reset.
Example:
LPRINT CHR$(27);CHR$(57);

ESC <

Escape Less Than (Home Head)
(Graphics Printer only)
The print head Will return to the left margin to print the line
following ESC <. This will occur for one line only.
Example:
LPRINT CHR$(27);CHR$(60);

ESCA

Escape A (Sets Variable Line Feeding)
Format: ESC A;n;
Escape A sets the line-feed to n/72-inch. The example below tells
the printer to set line feeding to 24/72-inch. ESC 2 must be sent to
the printer before the line feeding will change. For example, ESC
A;24 (text) ESC 2 (text). The text following ESC A;24 will space at
the previously set line-feed increments. The text following ESC 2
will be printed with new line-feed increments of 24/72-inch. Any
increment between 1/72 and 85/72 may be used.
Example:
LPRINT CHR$(27);CHR$(65);CHR$(24);CHR$(27);CHR$(50);

ESC B

Escape B (Set Vertical Tabs)
Format: ESC B;n, ;n 2 ; ... n k ;NUL;
(Graphics Printer ignores ESC B)
Sets vertical tab stop positions. Up to 64 vertical tab stop positions
are recognized by the printer. The n's, in the format above, are used
to indicate tab stop positions. Tab stop numbers must be received in
ascending numeric order. The tab stop numbers will not become
valid until the NUL code is entered. Once vertical tab stops are
established, they will be valid until new tab stops are specified. (If
the printer is reset or powered Off, set tab stops are cleared.) If no
tab stop is set, the Vertical Tab command behaves as a Line Feed
command. ESC B followed only by NUL will cancel tab stops. The
form length must be set by the ESC C command prior to setting
tabs.
Example:
LPRINT CHR$(27);CHR$(66);CHR$( 1O);CHR$(20);CHR$(40);CHR$(O);

Printers

1-95

Printer
Code
ESCC

Printer Function
Escape C (Set Lines per Page)
Format: ESC C;n;
Sets the page length. The ESC C command must have a value
following it to specify the length of page desired. (Maximum form
length for the printer is 127 lines.)
The example below sets the page length to 55 lines. The printer
defaults to 66 lines per page when powered on or reset.
Example:
LPRINT CHR$(27);CHR$(67);CHR$(55);
Escape C (Set Inches per Page)
Format: ESC C;n;m;
(Graphics Printer only)
Escape C sets the length of the page in inches. This command
requires a value of 0 (zero) for n, and a value between 1 and 22 for
m.
Example:
LPRINT CHR$(27);CHR$(67);CHR$(0);CHR$(12);

ESCD

Escape D (Set Horizontal Tab Stops)
Format: ESC D;n,;n 2 ; ... n k ;NUL;
Sets the horizontal tab stop positions. The example below shows
the horizontal tab stop positions set at printer column positions of
10,20, and 40. They are followed by CHR$(O), the NUL code. They
must also be in ascending numeric order as shown. Tab stops can
be set between 1 and 80. When in the Compressed print mode, tab
stops can be set up to 132.
The maximum number of tabs that can be set is 112. The Graphics
Printer can have a maximum of 28 tab stops. The HT (CHR$(9)) is
used to execute a tab operation.
Example:
LPRINT CHR$(27);CHR$(68);CHR$( 10)CHR$(20)CHR$(40);CHR$(0);

ESC E

Escape E (Emphasized)
Changes the printer to the Emphasized print mode. The speed of the
printer is reduced to half speed during the Emphasized print mode.
Example:
LPRINT CHR$(27);CHR$(69);

ESC F

Escape F (Emphasized Off)
Stops printing in the Emphasized print mode.
Example:
LPRINT CHR$(27);CHR$(70);

ESCG

Escape G (Double Strike)
Changes the printer to the Double Strike print mode. The paper is
spaced 1/216 of an inch before the second pass of the print head.
Example:
LPRINT CHR$(271;CHR$(71);

1-96

Printers

Printer
Code
ESC H

Printer Function
Escape H (Double Strike Off)
Stops printing in the Double Strike mode.
Example:
LPRINT CHR$(27);CHR$(72);

ESC J

Escape J (Set Variable Line Feeding)
Format: ESC J;n;
(Graphics Printer only)
When ESC J is sent to the printer. the paper will feed in increments
of n/216 of an inch. The value of n must be between 1 and 255.
The example below gives a line feed of 50/216-inch. ESC J is
canceled after the line feed takes place.
Example:
LPRINT CHR$(27);CHR$(74);CHR$(50);

ESC K

Escape K (480 Bit-Image Graphics Mode)
Format ESC K;n,;n 2 ;v,;v2 ; ... v k;
(Graphics Printer only)
Changes from the Text mode to the Bit-Image Graphics mode. n,
and n 2 are one byte. which specify the number of bit-image data
bytes to be transferred. v, through vk are the bytes of the bit-image
data. The number of bit-image data bytes (k) is equal to n, +256n 2
and cannot exceed 480 bytes. At every horizontal position. each
byte can print up to 8 vertical dots. Bit-image data may be mixed
with text data on the same line.
Note:

Assign values to n, and n 2 as follows:
n, represents values from 0 - 255.
n 2 represents values from 0 - 1 x 256.

MSB is most significant bit and LSB is least significant bit.

MSB

LSB

15
2

14
2

13
12
11
10
222
2
2

9

8

L

n,
MSB

LSB

7
2

6
2

3

4

5

2

2

2

o

2
2

2

2

Printers

1-97

Data sent to the printer.
Text (20 characters)

Bit-image data

In text mode, 20 characters in text mode correspond to 120 bit-image
positions (20 x 6 = 120). The printable portion left in Bit-Image mode is 360
dot positions (480 ~ 120 = 360).
Data sent to the printer.

Data A IESC Kin,
Text
data

I

I n I Data B I Data C I ESC I Kin, I n I Data 0

Length of
data

2

2

I ~~t~ge I
data

~---------480

Text
data

I

Length of
data

I ~~t~ge
data

bit-image dot positions _ _ _ _ _ _ _ _~I

Example:
TYPE B:GRAPH.TXT
1 'OPEN PRINTER IN RANDOM MODE WITH LENGTH OF 255
2 OPEN "LPTl:" AS #1
3 WIDTH "LPTl :",255
4 PRINT #1 ,CHRS(13);CHR$(1 0);
5 SLASH$=CHRS(l )+CHR$(02)+CHRS(04)+CHR$(08)
6 SLASHS=SLASHS+CHRS(16)+CHR$(32)+CHRS(64)+CHRS(128)+CHR$(0)
7 GAP$=CHRS(O)+CHR$(O)+CHR$(O)
8 NDOTS=480
9 'ESC K N1 N2
10 PRINT #1 ,CHR$(27);"K";CHR$(NDOTS MOD 256);CHR$(FIX (NDOTS1256));
11 ' SEND NDOTS NUMBER OF BIT IMAGE BYTES
12 FOR 1=1 TO NDOTS/ 12 'NUMBER OF SLASHES TO PRINT USING
GRAPHICS
13 PRINT #1 ,SLASH$;GAP$;
14 NEXT I
15 CLOSE
16 END
This example will give you a row of slashes printed in the 480 Bit-Image mode.

1-98

Printers

Printer
Code
ESC L

Printer Function
Escape L (960 Bit-Image Graphics Mode)
Format: ESC L;n,;n 2 ;v,;v2 ; ... v k,
(Graphics Printer only)
Changes from the Text mode to the Bit-Image Graphics mode. The
input is similar to ESC K. The 960 Bit-Image mode prints al half the
speed of the 4BO Bit-Image Graphics mode, but can produce a
denser graphic image. The number of bytes of bit-image Data (k) is
n, + 256n 2 but cannot exceed 960. n, is in the range of 0 to 255.

ESC N

Escape N (Set Skip Perforation)
Format ESC N;n;
(Graphics Printer only)
Sets the Skip Perforation function. The number following ESC N
sets the value for the number of lines of Skip Perforation. The
example shows a 12-line skip perforation. This will print 54 lines
and feed the paper 12 lines. The value of n must be between 1 and
127. ESC N must be reset anytime the page length (ESC C) is
changed.
Example:
CHR$(27);CHR$(7B);CHR$(12);

ESC 0

Escape 0 (Cancel Skip Perforation)
(Graphics Printer only)
Cancels the Skip Perforation function.
Example:
LPRINT CHR$(27);CHR$(79);

ESC S

Escape S (Subscript/Superscript)
Format: ESC S;n;
(Graphics Printer only)
Changes the printer to the Subscript print mode when ESC S is
followed by a 1, as in the example below. When ESC S is followed
by a 0 (zero), the printer will print in the Superscript print mode.
Example:
LPRINT CHR$(27);CHR$(83);CHR$(1);

ESC T

Escape T (Subscript/Superscript Off)
(Graphics Printer only)
The printer stops printing in the Subscript or Superscript print
mode.
Example:
LPRINT CHR$(27);CHR$(84);

ESC U

Escape U (Unidirectional Printing)
Format: ESC U;n;
(Graphics Printer only)
The printer will print from left to right following the input of ESC
U; 1. When ESC U is followed by a 0 (zero). the left to right printing
operation is canceled. The Unidirectional print mode (ESC U)
ensures a more accurate print-start position for better print quality.
Example:
LPRINT CHR$(27);CHR$(85);CHR$(1);

Printers

1-99

Printer
Code
ESCW

Printer Function
Escape W (Double Width)
Format: ESC W;n;
(Graphics Printer only)
Changes the printer to the Double Width print mode when ESC W is
followed by a 1. This mode is not canceled by a line-feed operation
and must be canceled with ESC W followed by a 0 (zero).
Example:
LPRINT CHR$(27);CHR$(87);CHR$(1);

ESCY

Escape Y (960 Bit-Image Graphics Mode Normal Speed)
Format: ESC Y n,;n 2 ;v,;v 2 ; ... vk ;
(Graphics Printer only)
Changes from the Text mode to the 960 Bit-Image Graphics mode.
The printer prints at normal speed during this operation and cannot
print dots on consecutive dot positions. The input of data is similar to
ESC L.

ESC Z

Escape Z (1920 Bit-Image Graphics Mode)
Format: ESC Z;n,;n 2 ;v,;v2 ; ... v k ;
(Graphics Printer only)
Changes from the Text mode to the 1920 Bit-Image Graphics mode.
The input is similar to the other Bit-Image Graphics modes. ESC Z
can print only every third dot position.

DEL

Delete (Clear Printer Buffer)
(Graphics Printer ignores DEL)
Clears the printer buffer. Control codes, except SO, still remain in
effect. DIP switch 1-5 must be in the Off position.
Example:
LPRINT CHR$(127);

1-100

Printers

o

1

234

5

6

7

8

9

INULI I I I I IBELI I I
I~: I~ I~: ~: H:1"I~+~ D~ I
IDrAl I ICANI I
I~I"I: ~I~I;; ;'I~ :"
I;I~I: :1: ~ ~ ;I~ ;
HT

20

21

22

23

24

25

26

27

28

29

58

59

esc

50

51

52

53

54

121314 516

I~I: ;

55

56

7 8

57

91: ;

;1; ~I; ~I~ ~

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

IFIGH IIJ KllMlrulo
IplQ
ulvwlxlv
IzI[ \ I] -I' I I I
Idle fig il kl'H
R S T

a b c

A

h

108

109

j

I~I~ ';I~'~ ':I'~"

:1:1:1

I': I'~ I': I'[' ';' I'J I': I~;LI~~"LI "" I
Matrix Printer Character Set (Part 1 of 2)

Printers

1-101

00000808BO
8888088880
0080080000
O~~~~~~~~~
~~9~~ ~~~~
~ '" ", ~~~~~~~

~ ~~~~~~~
~~~~i~~~~~
210

211

212

213

214

215

216

217

216

219

~=~~~~~~~~

i'" illDDDDDD
Matrix Printer Character Set (Part 2 of 2)

1-102

Printers

Graphics Printer Character Set 1 (Part 1 of 2)

Printers

1-103

.., x ){ I• « » :::1 : ~~
::: I:
~::

~

Graphics Printer Character Set 1 (Part 2 of 2)

1-104

Printers

,.::.....

'--

Graphics Printer Character Set 2 (Part 1 of 2)

Printers

1-105

130

131

132

e a a

133

134

,

0

a a

135

136

137

138

~

e e e

., ~ X' I• « » :::···1-I: ~~
::: I:
~

Graphics Printer Character Set 2 (Part 2 of 2)

1-106

Printers

139

I

r!:-;;-

IBM Printer Adapter

The printer adapter is specifically designed to attach printers with
a parallel port interface, but it can be used as a general
input/output port for any device or application that matches its
input/output capabilities. It has 12 TTL-buffer output points,
which are latched and can be written and read under program
control using the processor In or Out instruction. The adapter also
has five steady-state input points that may be read using the
processor's In instructions.
In addition, one input can also be used to create a processor
interrupt. This interrupt can be enabled and disabled under
program control. Reset from the power-on circuit is also ORed
with a program output point, allowing a device to receive a
power-on reset when the processor is reset.
The input/output signals are made available at the back of the
adapter through a right-angled, PCB-mounted, 25-pin, D-shell
connector. This connector protrudes through the rear panel of the
system or expansion unit, where a cable may be attached.
When this adapter is used to attach a printer, data or printer
commands are loaded into an 8-bit, latched, output port, and the
strobe line is activated, writing data to the printer. The program
then may read the input ports for printer status indicating when
the next character can be written, or it may use the interrupt line
to indicate "not busy" to the software.
The output ports may also be read at the card's interface for
diagnostic loop functions. This allows faults to be isolated
between the adapter and the attaching device.
This same function is also part of the combination IBM
Monochrome Display and Printer Adapter. A block diagram of
the printer adapter is on the next page.

Printer Adapter

1-107

8
Data Latch

Bus Buffer

8

~

r-t'

. ; Transceiver

r

-

25-Pin
D-Shell
Connector

8

,.....

Enable

Clock

8

DIR

mJ

Read
Data

----+
AEN

Write Data
Write Control
Read Status
Read
~ontrol

Command
Decoder

Control
Latch

Bus
Buffers

4

Enable

..... Clock

5

~

5

Enable
-po

Reset

Printer Adapter Block Diagram

1-108

Printer Adapter

~

~

Clear

~

O.C.
Drivers
,.....~

SLCTIN
STROBE
AUTO
FDXT
INIT
ERROR
SLCT
PE
ACK
BUSY

Programming Considerations
The printer adapter responds to five I/O instructions: two output
and three input. The output instructions transfer data into 2
latches whose outputs are presented on pins of a 25-pin D-shell
connector.
Two of the three input instructions allow the processor to read
back the contents of the two latches. The third allows the
processsor to read the real time status of a group of pins on the
connector.
A description of each instruction follows.
IBM Monochrome Display &
Printer Adapter
Output to address hex 3BC
Bit 7
Pin 9

I

Bit 6
Pin 8

I Bit 5 I

Bit 4

Pin 7

Pin 6

Printer Adapter
Output to address hex 378
Bit 3
Pin 5

I

Bit 2
Pin 4

I

Bit 1
Pin 3

I

Bit 0
Pin 2

The instruction captures data from the data bus and is present on
the respective pins. These pins are each capable of sourcing
2.6 rnA and sinking 24 rnA.
It is essential that the external device not try to pull these lines to
ground.

Printer Adapter

1·109

IBM Monochrome Display &
Printer Adapter

Printer Adapter

Output to address hex 3BE

Output to address hex 37A

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IRQ
Enable

Pin 17

Pin 16

Pin 14

Pin 1

This instruction causes the latch to capture the five least
significant bits of the data bus. The four least significant bits
present their outputs, or inverted versions of their outputs, to the
respective pins shown above. If bit 4 is written as 1, the card will
interrupt the processor on the condition that pin 10 transitions
high to low.
These pins are driven by open collector drivers pulled to +5 Vdc
through 4.7 k-ohm resistors. They can each sink approximately
7 rnA and maintain 0.8 volts down-level.
IBM Monochrome Display &
Printer Adapter

Printer Adapter

Input from address Hex 3BC

Input from address hex 378

This command presents the processor with data present on the
pins associated with the out to hex 3BC. This should normally
reflect the exact value that was last written to hex 3BC. If an
external device should be driving data on these pins (in violation
of usage groundrules) at the time of an input, this data will be
ORed with the latch contents.

1-110

Printer Adapter

IBM Monochrome Display &
Printer Adapter

Printer Adapter

Input from address hex 3BD

Input from address hex 379

This command presents realtime status to the processor from the
pins as follows.

IBM Monochrome Display &
Printer Adapter

Printer Adapter

Input from address hex 3BE

Input from address hex 37A

This instruction causes the data present on pins 1, 14, 15, 17, and
the IRQ bit to read by the processor. In the absence of external
drive applied to these pins, data read by the processor will exactly
match data last written to hex 3BE in the same bit positions. Note
that data bits 0-2 are not included. If external drivers are dotted
to these pins, that data will be ORed with data applied to the pins
by the hex 3BE latch.
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IRQ
Enable

P1ii"T'7

Pin 16

Pli'i14

Pin 1

Por=O

Por=l

Por=O

Por=l

Por=l

These pins assume the states shown after a reset from the
processor.

Printer Adapter

1-111

25-Pin D-Shell
Connector

Rear Panel

0

•

14

•
•
• •
25
Connector

0

Note: All outputs are software-generated.
and all inputs are real-time signals
(not latched).
At Standard TTL levels
Signal

Adapter

Name

Pin Number

~Strobe

Printer

1

'1

+Data Bit 0

2

+Data Bit 1

3

+Data Bit 2

4

+Data Bit 3

5

+Data Bit 4

6

+Data Bit 5

7

+Data Bit 6

8

+Data Bit 7

9

Printer

~

10

Adapte

Acknowledge

+Busy

"

11

'--'

+P.End (out of paper) "
+Select~

13

~Auto

14

~

Feed

Error

~

15

~

~ Initialize Printer

"v

16

Select Input

17

Ground

18-25

Connector Specifications

1-112

12

Printer Adapter

IBM Monochrome Display and
Printer Adapter

This chapter has two functions. The first is to provide the
interface to the IBM Monochrome Display. The second provides
a parallel interface for the IBM CPS Printer. This second function
is fully discussed in the "IBM Printer Adapter" section.
The monitor adapter is designed around the Motorola 6845 CRT
controller module. There are 4K bytes of static memory on the
adapter which is used for the display buffer. This buffer has two
ports and may be accessed directly by the processor. No parity is
provided on the display buffer.
Two bytes are fetched from the display buffer in 553 ns, providing
a data rate of 1.8M bytes/second.
The monitor adapter supports 256 different character codes. An
8K-byte character generator contains the fonts for the character
codes. The characters, values, and screen characteristics are given
in "Appendix C: Of Characters, Keystrokes, and Color."
This monitor adapter, when used with a display containing P39
phosphor, will not support a light pen.
Where possible, only one low-power Schottky (LS) load is
present on any I/O slot. Some of the address bus lines have two
LS loads. No signal has more than two LS loads.
Characteristics of the monitor adapter are listed below:
•

80 by 25 screen

•

Direct-drive output

•

9 by 14 character box

•

7 by 9 character

•

18 kHz monitor

•

Character attributes
Monochrome Adapter

1-113

(12)

Processo r
Address
(11 )

.

Memory
Address
~ Multiplexer

Processo r
Data

Data
Bus
Gating
BDO-7

-

-

(10)

(10) •

2K Memory
Character
Code

2K Memory
Attribute

(8)
(8)

Character
Clock

(8)

Octal
Latch

MA

I

Lt-o
AO
Chip
Select
Timing
Signals

---

--.

RA

L_l- . J

•

Attribute
Decode

Character
Generator

(4)
MC6845
CRTC

'.

DOTCLK

Shift
Register

I

1

Serial Dots

r

Octal
Latch

Video
Process
Logic

.

HSYNC, VSYNC, CURSOR, DISPEN
Character
Clock

J
~
Monitor
Direct Drive
Outputs

IBM Monochrome Adapter Block Diagram

1-114

Monochrome Adapter

Programming Considerations
The following table summarizes the 6845 internal data registers,
their functions, and their parameters. For the IBM Monochrome
Display, the values must be programmed into the 6845 to ensure
proper initialization of the device.

Register
Number
RO
R1
R2
R3
R4
R5
R6
R7
RS
R9
R10
R11
R12
R13
R14
R15
R16
R17

Register
File

Program
Unit

Horizontal Total
Horizontal Displayed
Horizontal Sync Position
Horizontal Sync Width
Vertical Total
Vertical Total Adjust
Vertical Displayed
Vertical Sync Position
Interlace Mode
Maximum Scan Line
Address
Cursor Start
Cursor End
Start Address (HI
Start Address (LI
Cursor (HI
Cursor (LI
Reserved
Reserved

Characters
Characters
Characters
Characters
Character Rows
Scan Line
Character Row
Character Row

-------Scan Line
Scan Line
Scan Line

IBM Monochrome
Display
(Address in hexl
61
50
52
F

19
6
19
19
02
D
B

---------------

C
00
00
00
00

--------

--

--------

--

--------

--------

To ensure proper initialization, the first command issued to the
attachment must be to send to CRT control port 1 (hex 3B8), a
hex 01, to set the high-resolution mode. If this bit is not set, then
the processor access to the monochrome adapter must never
occur. If the high-resolution bit is not set, the processor will stop
running.
System configurations that have both an IBM Monochrome
Display Adapter and Printer Adapter, and an IBM
Color/Graphics Monitor Adapter, must ensure that both adapters
are properly initialized after a power-on reset. Damage to either
display may occur if not properly initialized.

Monochrome Adapter

1-115

The IBM Monochrome Display and Printer Adapter supports 256
different character codes. In the character set are alphanumerics
and block graphics. Each character in the display buffer has a
corresponding character attribute. The character code must be an
even address, and the attribute code must be an odd address in the
display buffer.
7

5

6

4

o

2

3

Character Code
Even Address (M)

7

5

6

BL

I

3

4

o

2

R

G

I

B

I I I

Attribute Code
Odd Address (M+1)

Foreground
Intensity
Background
Blink

The adapter decodes the character attribute byte as defined above.
The blink and intensity bits may be combined with the foreground
and background bits to further enhance the character attribute
functions listed below.
Background
R G B

0 0 0
0 0 0
0 0 0
1 1 1

1-116

Foreground
R G B

0
0
1
0

0 0
0 1
1 1
0 0

Monochrome Adapter

Function
Non- Display
Underline
White Character/Black Background
Reverse Video

The 4K display buffer supports one screen of 25 rows of 80
characters, plus a character attribute for each display character.
The starting address of the buffer is hex BOOOO. The display
buffer can be read from using DMA; however, at least one
wait-state will be inserted by the processor. The duration of the
wait-state will vary, because the processor/monitor access is
synchronized with the character clock on this adapter.
Interrupt level 7 is used on the parallel interface. Interrupts can be
enabled or disabled through the printer control port. The interrupt
is a high-level active signal.
The figure below breaks down the functions of the I/O address
decode for the adapter. The I/O address decode is from hex 3BO
through hex 3BF. The bit assignment for each I/O address
follows:
1/0 Register
Address

Function

380
381
382
383
384*
385*
3B6
3B7
3B8
3B9
3BA
3BB
3BC
3BD
3BE
3BF

Not Used
Not Used
Not Used
Not Used
6845 Index Register
6845 Data Register
Not Used
Not Used
CRT Control Port 1
Reserved
CRT Status Port
Reserved
Parallel Data Port
Printer Status Port
Printer Control Port
Not Used

*The 6845 Index and Data Registers are
used to program the CRT controller to
interface the high-resolution IBM
Monochrome Display.

I/O Address and Bit Map

Monochrome Adapter

1-117

Bit
Number

Function
+High Resolution Mode
Not Used
Not Used
+Video Enable
Not Used
+Enable Blink
Not Used

0
1

2
3
4

5
6,7

6845 CRT Control Port 1 (Hex 388)

Bit
Number

0
1

2
3

Function
+Horizontal Drive
Reserved
Reserved
+Black/White Video

6845 CRT Status Port (Hex 38A)

1-118

Monochrome Adapter

Rear Panel
9-Pin
Monochrome
Display
Connector

6
9

Connector

At Standard TTL Levels

IBM
Monochrome
Display

Note:

Ground

1

Ground

2
Not Used

3

Not Used

4

Not Used

5

+Intensity

6

+Video

7

+Horizontal

8

-Vertical

9

IBM
Monochrome
Display and
Printer Adapter

Signal voltages are 0.0 to 0.6 Vdc at down level and +2.4 to 3.5
Vdc at high level.

Connector Specifications

Monochrome Adapter

1-119

Notes:

1-120 Monochrome Adapter

IBM Monochrome Display

The high-resolution IBM Monochrome Display attaches to the
system unit through two cables approximately 3 feet (914
millimeters) in length. One cable is a signal cable that contains the
direct drive interface from the IBM Monochrome Display and
Printer Adapter.
The second cable provides ac power to the display from the
system unit. This allows the system-unit power switch to also
control the display unit. An additional benefit is a reduction in the
requirements for wall outlets to power the system. The display
contains an 11-~ inch (283 millimeters), diagonal 90° deflection
CRT. The CRT and analog circuits are packaged in an enclosure
so the display may either sit on top of the system unit or on a
nearby tabletop or desk. The unit has both brightness and contrast
adjustment controls on the front surface that are easily accessible
to the operator.

Monochrome Display

1-121

Operating Characteristics
Screen
•

High-persistence green phosphor (P 39).

•

Etched surface to reduce glare.

•

Size is 80 characters by 25 lines.

•

Character box is 9 dots wide by 14 dots high.

Video Signal
•

Maximum bandwidth of 16.257 MHz.

Vertical Drive
•

Screen refreshed at 50 Hz with 350 lines of vertical resolution
and 720 lines of horizontal resolution.

Horizontal Drive
•

Positive-level, TTL-compatibility at a frequency of
18.432 kHz.

1·122

Monochrome Display

IBM Color/Graphics Monitor
Adapter

The IBM Color/Graphics Monitor Adapter is designed to attach
to the IBM Color Display, to a variety of television-frequency
monitors, or to home television sets (user-supplied RF modulator
is required for home television sets). The adapter is capable of
operating in black-and-white or color. It provides three video
interfaces: a composite-video port, a direct-drive port, and a
connection interface for driving a user-supplied RF modulator. In
addition, a light pen interface is provided.
The adapter has two basic modes of operation: alphanumeric
(AIN) and all-points-addressable graphics (APA). Additional
modes are available within the AIN and APA modes. In the AIN
mode, the display can be operated in either a 40-column by
25-row mode for a low-resolution monitor or home television, or
in an 80-column by 25-row mode for high-resolution monitors. In
both modes, characters are defined in an 8-wide by 8-high
character box and are 7-wide by 7-high, with one line of
descender for lowercase characters. Both uppercase and lowercase
characters are supported in all modes.
The character attributes of reverse video, blinking, and
highlighting are available in the black-and-white mode. In the
color mode, sixteen foreground and eight background colors are
available for each character. In addition, blinking on a
per-character basis is available.
The monitor adapter contains 16K bytes of storage. As an
example, a 40-column by 25-row display screen uses 1000 bytes
to store character information, and 1000 bytes to store
attribute/color information. This would mean that up to eight
display screens can be stored in the adapter memory. Similarly, in
an 80-column by 25-row mode, four display screens may be
stored in the adapter. The entire 16K bytes of storage on the
display adapter are directly addressable by the processor, which
allows maximum software flexibility in managing the screen.

Color Graphics Adapter

1-123

In A/N color modes, it is also possible to select the color of the
screen's border. One of sixteen colors can be selected.
In the APA mode, there are two resolutions available: a
medium-resolution color graphics mode (320 PELs by 200 rows)
and a high-resolution black-and-white graphics mode (640 PELs
by 200 rows). In the medium-resolution mode, each picture
element (PEL) may have one of four colors. The background
color (color 0) may be any of the 16 possible colors. The
remaining three colors come from one of the two
software-selectable palettes. One palette contains green/red/
brown; the other contains cyan/magenta/white.
The high-resolution mode is available only in black-and-white
because the entire 16K bytes of storage in the adapter is used to
define the on or off state of the PELs.
The adapter operates in noninterlace mode at either 7 or 14 MHz,
depending on the mode of operation selected.
In the A/N mode, characters are formed from a ROM character
generator. The character generator contains dot patterns for 256
different characters. The character set contains the following
major groupings of characters:
•

16 special characters for game support

•

15 characters for word-processing editing support

•

96 characters for the standard ASCII graphics set

•

48 characters for foreign-language support

•

48 characters for business block-graphics support (allowing
drawing of charts, boxes, and tables using single and double
lines)

•

16 selected Greek characters

•

15 selected scientific-notation characters

1-124

Color Graphics Adapter

The color/graphics monitor adapter function is packaged on a
single card. The direct-drive and composite-video ports are
right-angle mounted connectors on the adapter, and extend
through the rear panel of the unit. The direct-drive video port is a
9-pin D-shell female connector. The composite-video port is a
standard female phono-jack.
The display adapter is implemented using a Motorola 6845 CRT
controller device. This adapter is highly programmable with
respect to raster and character parameters. Therefore, many
additional modes are possible with clever programming of the
adapter.
.
A block diagram of the color/graphics adapter is on the following
page.

Color Graphics Adapter

1-125

-I

N
C/'I

Display
.... Buffer
(16K Bytes)

Address

Processo
Address

Latch

Input
Buffer

L..

Processol Data

~.

.

(")

o
0'
..,

o..,
..g
e:

r--

.
Processor
Data

~

6845
CRT

(')
[I>

>
Q.

1-+

Address
Latch

I--

Data
Latch

--r

4

Output
Latch

f---

Data
Latch

t

..

Graphics
Serializer

,.

,-----to

~

"0

.....
f!l

..,

Character
Generator
ROM

~

4

r--------.

Alpha
Serializer

~ R
Color
Encoder

1--+ G
~
~

f----J

Palette/
Overscan

Mode
Control

Timing
Generator
& Control

Color/Graphics Monitor Adapter Block Diagram

B

Horizontal
Vertical

L
--.-

Composite
Color
Generator

~

Descriptions of Major Components
Motorola 6845 CRT Controller
This device provides the necessary interface to drive a raster-scan
CRT.

Mode Set Register
This is a general-purpose, programmable, I/O register. It has I/O
ports that may be individually programmed. Its function in this
attachment is to provide mode selection and color selection in the
medium-resolution color-graphics mode.

Display Buffer
The display buffer resides in the processor-address space, starting
at address hex B8000. It provides 16K bytes of dynamic
read/write memory. A dual-ported implementation allows the
processor and the graphics control unit to access the buffer. The
processor and the CRT control unit have equal access to this
buffer during all modes of operation, except in the high-resolution
alphanumeric mode. In this mode, only the processor should
access this buffer during the horizontal-retrace intervals. While
the processor may write to the required buffer at any time, a small
amount of display interference will result if this does not occur
during the horizontal-retrace intervals.

Character Generator
This attachment utilizes a ROM character generator. It consists of
8K bytes of storage that cannot be read from or written to under
software control. This is a general-purpose ROM character
generator with three different character fonts. Two character fonts
are used on the color/graphics adapter: a 7-high by 7-wide
double-dot font and a 5-wide by 7-high single-dot font. The font is
selected by a jumper (P3). The single-dot font is selected by
inserting the jumper; the double-dot font is selected by removing
the jumper.
Color Graphics Adapter

1-127

Timing Generator
This generator produces the timing signals used by the 6845 CRT
controller and by the dynamic memory. It also resolves the
processor/graphic controller contentions for accessing the display
buffer.

Composite Color Generator
This generator produces base band video color information.

Alphanumeric Mode
Every display-character position in the alphanumeric mode is
defmed by two bytes in the regen buffer (a part of the monitor
adapter), not the system memory. Both the color/graphics and the
monochrome display adapter use the following 2-byte
character/attribute format.
Attribute Byte

Display-Character Code Byte

17

6

5

4

3

2

1

7

0

6

5

4

3

2

1

01

The functions of the attribute byte are defined by the following
table:
Attribute Function

Attribute Byte

7

8

5

4

3

2

1

0

B

R

G

B

I

R

G

B

FG
Normal
Reverse Video
Nondisplay (Black)
Nondisplay (White)

B
B
B
B

Background

0

0

0

1

1

1

0

0

0

1

1

1

I = Highlighted Foreground (Character)
B = Blinking Foreground (Character)

1-128

Color Graphics Adapter

Foreground
I
I
I
I

1
0
0
1

i

1

0
0

0
0
1

1

The attribute byte definitions are:
7 6 543 2 1 0

\ B\ R G B \1\ R G B \

I

11-----..

Foreground Color
Intensity
Background Color
Blinking

In the alphanumeric mode, the display mode can be operated in
either a low-resolution mode or a high-resolution mode.
The low-resolution alphanumeric mode has the following features:
•

Supports home color televisions or low-resolution monitors

•

Displays up to 25 rows of 40 characters each

•

ROM character generator that contains dot patterns for a
maximum of 256 different characters

•

Requires 2,000 bytes of read/write memory (on the adapter)

•

Character box is 8-high by 8-wide

•

Two jumper-controlled character fonts are available:
5-wide by 7-high single-dot character font with one descender
7-wide by 7-high double-dot character font with one descender

•

One character attribute for each character

Color Graphics Adapter

1-129

The high-resolution alphanumeric mode has the following
features:
•

Supports the IBM Color Display or other color monitor with
direct-drive input capability

•

Supports a black-and-white composite-video monitor

•

Displays up to 25 rows of 80 characters each

•

ROM displays generator that contains dot patterns for a
maximum of 256 different characters

•

Requires 4,000 bytes ofread/write memory (on the adapter)

•

Character box is 8-high by 8-wide

•

Two jumper-controlled character fonts are available:
5-wide by 7-high single-dot character font with one descender
7-wide by 7-high double-dot character font with one descender

•

One character attribute for each character

Monochrome vs Color/Graphics
Character Attributes
Foreground and background colors are defined by the attribute
byte of each character, whether using the IBM Monochrome
Display and Printer Adapter or the IBM Color/Graphics Monitor
Adapter. The following table describes the colors for each
adapter:

7 6

Attribute Byte
5 4 3 2

1 0

B R G B I R G B
FG Background Foreground
B
B
B
B

0 0 0
1 1 1
0 0 0
1 1 1

1-130

I
I
I
I

1 1 1
0 0 0
0 0 0
1 1 1

Monochrome
Display Adapter

Color/Graphics
Monitor Adapter

Background
Color

Character
Color

Background
Color

Character
Color

Black
White
Black
White

White
Black
Black
White

Black
White
Black
White

White
Black
Black
White

Color Graphics Adapter

The monochrome display adapter will produce white characters
on a white background with any other code. The color/graphics
adapter will change foreground and background colors according
to the color value selected. The color values for the various red,
green, blue, and intensity bit settings are given in the table below.
R

G

B

I

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0
1
1

0

1
1
1
1
1
1
1

0
1

1
1
1
1
1
1
1
1

Color
Black
Blue
Green
Cyan
Red
Magenta
Brown
White
Gray
Light Blue
Light Green
Light Cyan
Light Red
Light Magenta
Yellow
White (High Intensity)

Code written with an underline attribute for the IBM
Monochrome Display, when executed on a color/graphics monitor
adapter, will result in a blue character where the underline
attribute is encountered. Also, code written on a color/graphics
monitor adapter with blue characters will be displayed as white
characters on a black background, with a white underline on the
IBM Monochrome Display.
Remember that not all monitors recognize the intensity (I) bit.

Color Graphics Adapter

1-131

Graphics Mode
The IBM Color/Graphics Monitor Adapter has three modes
available within the graphics mode. They are low-resolution color
graphics, medium-resolution color graphics, and high-resolution
color graphics. However, only medium- and high-resolution
graphics are supported in ROM. The following table summarizes
the three modes.
Horizontal
(PELs)

Vertical
(Rows)

Number of Colors Available
(Includes Background Color)

Low Resolution

160

100

16 (Includes black-and-white)

Medium
Resolution

320

200

4
1
1
1

High Resolution

640

200

Black-and-white only

Colors Total
of 16 for Background and
of Green, Red, or Brown or
of Cyan, Magenta, or White

Low-Resolution Color-Graphics Mode
The low-resolution mode supports home television or color
monitors. This mode is not supported in ROM. It has the
following features:
•

Contains a maximum of 100 rows of 160 PELs, with each
PEL being 2-high by 2-wide

•

Specifies 1 of 16 colors for each PEL by the I, R, G, and
B bits

•

Requires 16,000 bytes of read/write memory (on the adapter)

•

Uses memory-mapped graphics

1-132

Color Graphics Adapter

Medium-Resolution Color-Graphics Mode
The medium-resolution mode supports home televisions or color
monitors. It has the following features:
•

Contains a maximum of 200 rows of 320 PELs, with each
PEL being 1-high by 1-wide

•

Preselects one of four colors for each PEL

•

Requires 16,000 bytes ofread/write memory (on the adapter)

•

Uses memory-mapped graphics

•

Formats 4 PELs per byte in the following manner:
7

6

5

4

3

2

C1

CO

C1

CO

C1

CO

First
Display
PEL

•

Second
Display
PEL

Third
Display
PEL

o
C1

CO

Fourth
Display
PEL

Organizes graphics storage in two banks of 8,000 bytes, using
the following format:

Memory
Address
(in hex)

Function

B8000
Even Scans
(0,2,4, ... 198)
8,000 bytes
B9F3F
Not Used

BAOOO
Odd Scans
(1,3,5 ... 199)
8,000 Bytes
BBF3F
Not Used
BBFFF

Address hex B8000 contains PEL instruction for the upper-left
corner of the display area.
Color Graphics Adapter

1-133

•

Color selection is determined by the following logic:
C1

co

Function

0

0

Dot takes on the color of 1 of 16 preselected background colors

0

1

Selects first color of preselected Color Set 1 or Color Set 2

1

0

Selects second color of preselected Color Set 1 or Color Set 2

1

1

Selects third color of preselected Color Set 1 or Color Set 2

Cl and CO will select 4 of 16 preselected colors. This
color selection (palette) is pre loaded in an I/O port.
The two colors are:
Color Set 1

Color Set 2

Color 1 is Green
Color 2 is Red
Color 3 is Brown

Color 1 is Cyan
Color 2 is Magenta
Color 3 is White

The background colors are the same basic 8 colors as defined
for low-resolution graphics, plus 8 alternate intensities defined
by the intensity bit, for a total of 16 colors, including black
and white.

1-134

Color Graphics Adapter

High-Resolution Black-and-White Graphics
Mode
The high-resolution mode supports color monitors. This mode has
the following features:
•

Contains a maximum of 200 rows of 640 PELs, with each
PEL being I-high by I-wide.

•

Supports black-and-white mode only.

•

Requires 16,000 bytes ofread/write memory (on the adapter).

•

Addressing and mapping procedures are the same as
medium-resolution color graphics, but the data format is
different. In this mode, each bit in memory is mapped to a
PEL on the screen.

•

Formats 8 PELs per byte in the following manner:

l71s1514J31211101
First Display PEL

J

Second Display PEL
Third Display PEL
Fourth Display PEL
Fifth Display PEL
Sixth Display PEL
Seventh Display PEL
Eighth Display PEL

Color Graphics Adapter

1-135

Description of Basic Operations
In the alphanumeric mode, the adapter fetches character and
attribute information from its display buffer. The starting address
of the display buffer is programmable through the 6845, but it
must be an even address. The character codes and attributes are
then displayed according to their relative positions in the buffer.
Memory
Address
(in hex)

Display Buffer

B8000
(Even)
Starting
Address

Character Code A
B8001
Attribute A
B8002

(Example of a 40 by 25 Screen)
Character Code B

B8003

AB

Attribute B

X
B87CE
Character Code X
Last
Address

Video Screen

B87CF
Attribute X

The processor and the display control unit have equal access to
the display buffer during all the operating modes, except the
high-resolution alphanumeric mode. During this mode, the
processor should access the display buffer during the vertical
retrace time. If it does not, the display will be affected with
random patterns as the processor is using the display buffer. In the
alphanumeric mode, the characters are displayed from a prestored
ROM character generator that contains the dot patterns of all the
displayable characters.
In the graphics mode, the displayed dots and colors (up to 16K
bytes) are also fetched from the display buffer. The bit
configuration for each graphics mode is explained in "Graphics
Mode."

1-136 Color Graphics Adapter

I

R

G

B

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0

0
0
1
1
0
0
1
1
0
0
1
1
0

0
1
0
1
0
1
0
1
0
1
0
1

Note:

0
1
1
1
1

0
1
1

0
1
0
1

Color
Black
Blue
Green
Cyan
Red
Magenta
Brown
White
Gray
Light Blue
Light Green
Light Cyan
Light Red
Light Magenta
Yellow
High Intensity White

"I" provides extra luminance (brightness) to
each available shade. This results in the
light colors listed above, except for
monitors that do not recognize the "I" bit.

Summary of Available Colors

Programming Considerations
Programming the 6845 CRT Controller
The 6845 has 19 accessible internal registers, which are used to
define and control a raster-scan CRT display. One of these
registers, the Index register, is actually used as a pointer to the
other 18 registers. It is a write-only register, which is loaded from
the processor by executing an 'out' instruction to I/O address hex
3D4. The five least significant bits of the I/O bus are loaded into
the Index register.
In order to load any of the other 18 registers, the Index register is
first loaded with the necessary pointer; then the Data Register is
loaded with the information to be placed in the selected register.
The Data Register is loaded from the processor by executing an
Out instruction to I/O address hex 3D5.
The following table defines the values that must be loaded into the
6845 CRT Controller registers to control the different modes of
operation supported by the attachment:
Color Graphics Adapter 1-137

Address
Register

Register
Number

0

RO

1

Register
Type

40 by 25
Alphanumeric

80 by 25
Alphanumeric

Graphic
Modes

Units

lID

Horizontal
Total

Character

Write
Only

38

71

38

R1

Horizontal
Displayed

Character

Write
Only

28

50

28

2

R2

Horizontal
Sync Position

Character

Write
Only

2D

5A

2D

3

R3

Horizontal
Sync Width

Character

Write
Only

OA

OA

OA

4

R4

Vertical Total

Character
Row

Write
Only

1F

1F

7F

5

R5

Vertical Total
Adjust

Scan
Line

Write
Only

06

06

06

6

R6

Vertical
Displayed

Character
Row

Write
Only

19

19

64

7

R7

Vertical
Sync Position

Character
Row

Write
Only

1C

1C

70

8

R8

Interlace
Mode

-

Write
Only

02

02

02

9

R9

Maximum
Scan line
Address

Scan
Line

Write
Only

07

07

01

A

R10

Cursor Start

Scan
Line

Write
Only

06

06

06

B

R11

Cursor End

Scan
Line

Write
Only

07

07

07

C

R12

Start
Address (H)

-

Write
Only

00

00

00

D

R13

Start
Address (L)

-

Write
Only

00

00

00

E

R14

Cursor
Address (H)

-

Read!
Write

XX

XX

XX

F

R15

Cursor
Address (L)

-

Read!
Write

XX

XX

XX

10

R16

light Pen (H)

-

Read
Only

XX

XX

XX

11

R17

Light Pen (L)

-

Read
Only

XX

XX

XX

Note: Ail register values are given in hexadecimal

6845 Register Description

1-138 Color Graphics Adapter

Programming the Mode Control and Status
Register
The following I/O devices are defined on the color/graphics
adapter.
Hex
Address

A9 A8 A7 A6 A5 A4 A3 A2 Al AD

Function of Register

3D8
3D9

1

1

1

1

0

1

1

0

0

1

1

1

1

0

1

1

0

0

0
1

3DA

1

1

1

1

0

1

1

0

1

0

Status Register (D1)

3DB

1

1

1

1

0

1

1

0

1

1

Clear Light Pen Latch

3DC

1

1

1

1

0

1

1

1

0

0

Preset Light Pen Latch

3D4
3D5
3DO
3D1

1

1

1

1

0

1

0

Z

Z

0

6845 Index Register

Mode Control Register (DO)
Color Select Register (DO)

1

1

1

1

0

1

0

Z

Z

1

6845 Data Register

1

1

1

1

0

1

0

Z

Z

0

6845 Registers

1

1

1

1

0

1

0

Z

Z

1

6845 Registers

Z = don't care condition

Color Graphics Adapter

1-139

Color-Select Register
This is a 6-bit output-only register (cannot be read). Its I/O
address is hex 3D9, and it can be written to by using the 8088
I/O Out command.
Bit 0

Selects B (Blue) Border Color in 40 x 25 Alphanumeric Mode
Selects B (Blue) Background Color in 320 x 200 Graphics Mode
Selects B (Blue) Foreground Color in 640 x 200 Graphics Mode

Bit 1

Selects G (Green) Border Color in 40 x 25 Alphanumeric Mode
Selects G (Green) Background Color in 320 x 200 Graphics Mode
Selects G (Green) Foreground Color in 640 x 200 Graphics Mode

Bit 2

Selects R (Red) Border Color in 40 x 25 Alphanumeric Mode
Selects R (Red) Background Color in 320 x 200 Graphics Mode
Selects R (Red) Foreground Color in 640 x 200 Graphics Mode

Bit 3

Selects I (Intensified) Border Color in 40 x 25 Alphanumeric Mode
Selects I (Intensified) Background Color in 320 x 200 Graphics Mode
Selects I (Intensified) Foreground Color in 640 x 200 Graphics Mode

Bit 4

Selects Alternate. Intensified Set of Colors in Graphics Mode
Selects Background Colors in the Alphanumeric Mode

Bit 5

Selects Active Color Set in 320 x 200 Graphics Mode

Bit 6

Not Used

Bit 7

Not Used

Bits 0, 1, 2, 3 These bits select the screen's border color in the
40 x 25 alphanumeric mode. They select the
screen's background color (CO-Cl) in the
medium-resolution (320 by 200) color-graphics
mode.
Bits 4

This bit, when set, will select an alternate,
intensified set of colors. Selects background colors
in the alphanumeric mode.

Bit 5

This bit is only used in the medium-resolution
(320 by 200) color-graphics mode. It is used to
select the active set of screen colors for the
display.

1-140

Color Graphics Adapter

When bit 5 is set to 1, colors are determined as follows:
C1

co

Set Selected

0
0
1
1

0
1
0
1

Background (Defined by bits 0-3 of port hex 309)
Cyan
Magenta
White

When bit 5 is set to 0, colors are determined as follows:
C1

co

Set Selected

0
0
1
1

0
1
0
1

Background (Defined by bits 0-3 of port hex 309)
Green
Red
Brown

Mode-Select Register
This is a 6-bit output-only register (cannot be read). Its I/O
address is hex 3D8, and it can be written to using the 8088 I/O
Out command.
The following is a description of the register's functions:
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

80 x 25 Alphanumeric Mode
Graphics Select
Black/White Select
Enable Video Signal
High-Resolution (640 x 200) Black/White Mode
Change Background Intensity to Blink Bit
Not Used
Not Used

Color Graphics Adapter 1-141

Bit 0

A 1 selects 80 by 25 alphanumeric mode
A 0 selects 40 by 25 alphanumeric mode

Bit 1

A 1 selects 320 by 200 graphics mode
A 0 selects alphanumeric mode

Bit 2

A 1 selects black-and-white mode
A 0 selects color mode

Bit 3

A 1 enables the video signal at certain times when modes
are being changed. The video signal should be disabled
when changing modes.

Bit 4

A 1 selects the high-resolution (640 by 200)
black-and-white graphics mode. One color of 8 can be
selected on direct-drive sets in this mode by using register
hex 3D9.

Bit 5

When on, this bit will change the character background
intensity to the blinking attribute function for
alphanumeric modes. When the high-order attribute bit is
not selected, 16 background colors (or intensified colors)
are available. For normal operation, this bit should be set
to 1 to allow the blinking function.

1-142

Color Graphics Adapter

Mode Register Summary
Bits

0

1

2

3

4

5

a

a

1

1

0

1

40 x 25 Alphanumeric Black-and-White

0

0

0

1

40 x 25 Alphanumeric Color

0

1

1

a
a

1

1

1

80 x 25 Alphanumeric Black-and-White

1

0

0

1

0

1

80 x 25 Alphanumeric Color

0

1

1

1

0

z

320 x 200 Black-and-White Graphics

0

1

0

1

0

z

320 x 200 Color Graphics

0

1

1

1

1

z

640 x 200 Black-and-White Graphics

Ud=:
1

-

:

Enable Blink Attribute

-

640 x 200 Black-and-White

L -_ _ _ _ _ _ _--.~
L -_ _ _ _ _ _ _ _ _ _

Enable Video Signal
Select Black-and-White Mode
Select 320 x 200 Graphics

" - - - - - - - - - - - - - 80 x 25 Alphanumeric Select

z = don't care condition
Note:

The low-resolution (160 by 100) mode requires special programming and is
set up as the 40 by 25 alphanumeric mode.

Status Register
The status register is a 4-bit read-only register. Its I/O address is
hex 3DA, and it can be read using the 8088 I/O In instruction.
The following is a description of the register functions:
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

Display Enable
Light-Pen Trigger Set
Light-Pen Switch Made
Vertical Sync
Not Used
Not Used
Not Used
Not Used

Color Graphics Adapter

1-143

Bit 0

This bit, when active, indicates that a regen buffer memory
access can be made without interfering with the display.

Bit 1

This bit, when active, indicates that a positive-going edge
from the light-pen has set the light pen's trigger. This
trigger is reset upon power-on and may also be cleared by
performing an I/O Out command to hex address 3DB. No
specific data setting is required; the action is
address-activated.

Bit 2

The light-pen switch status is reflected in this status bit.
The switch is not latched or debounced. A 0 indicates
that the switch is on.

Bit 3

This bit, when active, indicates that the raster is in a
vertical retrace mode. This is a good time to perform
screen-buffer updating.

Sequence of Events for Changing Modes
1. Determine the mode of operation.
2. Reset 'video enable' bit in mode-select register.
3. Program 6845 to select mode.
4. Program mode/color select registers including re-enabling
video.

1-144

Color Graphics Adapter

Memory Requirements
The memory used by this adapter is self-contained. It consists of
16K bytes of memory without parity. This memory is used as
both a display buffer for alphanumeric data and as a bit map for
graphics data. The regen buffer's address starts at hex B8000.
Read/Write Memory
Address Space (in hex)
01000
System
Read/Write
Memory

AOOOO

B8000
Display Buffer
(16K Bytes)

128K Reserved
Regen Area

BCOOO

CODOO

Color Graphics Adapter

1-145

Rear Panel
25-Pin D-Shel\
Connector

o
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•

25

•
•

•
•
•

14

o
At Standard TTL Levels

IBM Color D isplay
or other Dire ct-Drive
Monitor

Ground

1

Ground

2

Red

3

Green

4

Blue

5

Intensity

6

Reserved

7

Horizontal Drive

8
9

Vertical Drive

Color/G raphics
Direct-D rive
Adapter

Composite Phono Jack
Hookup to Monitor

Composite Video Signal of
Approximately 1.5 Volts
Video
Monitor

Peak to Peak Amplitude

1

Chassis Ground

2

Connector Specifications (Part 1 of 21

1-146

Color Graphics Adapter

Color/G raphics
Composi te Jack

P2 (6-Pin Berg Strip)
for Light-Pen

P1 (4-Pin Berg Strip)
for RF Modulator

Color / Graphics
Adapter

RF
Mo dulator

+12 Volts

1

(key) Not Used

2

Composite Video Output

3

Logic Ground

4

Color/G raphics
Adapter

RF Modulator Interface

Lig ht
Pe n

- Light Pen Input

1

(key) Not Used

2

- Light Pen Switch

3

Chassis Ground

4

+5 Volts

5

+12 Volts

6

Color/ Graphics
Adapter

Light Pen Interface

Connector Specifications (Part 2 of 2)

Color Graphics Adapter

1-147

Notes:

1-148

Color Graphics Adapter

IBM Color Display

The IBM Color Display attaches to the system unit by a signal
cable that is approximately 5 feet (1.5 meters) in length. This
signal cable provides a direct-drive interface from the IBM
Color/Graphics Monitor Adapter.
A second cable provides ac power to the display from a standard
wall outlet. The display has its own power control and indicator.
The display will accept either 120-volt 60-Hz, or 220-volt 50-Hz
power. The power supply in the display automatically switches to
match the applied power.
The display has a 13-inch (340 millimeters) CRT. The CRT and
analog circuits are packaged in an enclosure so the display may sit
either on top of the system unit or on a nearby tabletop or desk.
Front panel controls and indicators include: Power-On control,
Power~On indicator, Brightness and Contrast controls. Two
additional rear.,.panel controls are the Vertical Hold and Vertical
Size controls.

Color Display

1-149

Operating Characteristics
Screen
•

High contrast (black) screen.

•

Displays up to 16 colors, when used with the IBM
Color/Graphics Monitor Adapter.

•

Characters defined in an 8-high by 8-wide matrix.

Video Signal
•

Maximum video bandwidth of 14 MHz.

•

Red, green, and blue video signals and intensity are all
independent.

Vertical Drive
•

Screen refreshed at 60 Hz with 200 vertical lines of
resolution.

Horizontal Drive
•

Positive-level, TTL-compatibility, at a frequency of
15.75 kHz.

1·150 Color Display

IBM 5-1/4" Diskette Drive Adapter

The 5-1/4 inch diskette drive adapter fits into one of the
expansion slots in the system unit. It attaches to one or two
diskette drives through an internal, daisy-chained flat cable that
connects to one end of the drive adapter. The adapter has a
connector at the other end that extends through the rear panel of
the system unit. This connector has signals for two additional
external diskette drives; thus, the 5-1/4 inch diskette drive adapter
can attach four 5-1/4 inch drives - two internal and two external.
The adapter is designed for double-density, MFM-coded, diskette
drives and uses write precompensation with an analog phase-lock
loop for clock and data recovery. The adapter is a general-purpose
device using the NEe }.LPD765 compatible controller. Therefore,
the diskette drive parameters are programmable. In addition, the
attachment supports the diskette drive's write-protect feature. The
adapter is butTered on the I/O bus and uses the system board's
direct memory access (DMA) for record data transfers. An
interrupt level is also used to indicate when an operation is
complete and that a status condition requires processor attention.
In general, the 5-1/4 inch diskette drive adapter presents a
high-level command interface to software I/O drivers. A block
diagram ofthe 5-1/4 inch diskette drive adapter is on the
following page.

Diskette Adapter

1-151

-,

"'1

Clock
and
Timing
Circuit

VI

N

o-.

~

,.

.-

~

::::

I"-

Data
VCO SYNC-= Separator
.... STD.DATA
..... Data Windoll\<

>
0.
~

'0
.....
~

~ Buffer !'v-

......

r'

Write Data

~

Write
Data

~

""I

r--c>

I ..

1

'"~

Write
Precompensate
Circuit

NEC
Floppy
Disk
Controller

....

Read Data

<}-

J' ...... -"

Step
Direction
Write Enable
Head Select
Index

l/'"
l/'"

....-

rr

Write Protect

-"''-J

Track 0

~

r"

iRes~t
~
INTR.

(

Digital
Control
Port

Drive A Motor On

'l

Decoder

-B
-C
f--D
I-- B
I--C
I--D

~r - -

r--

~

rr

-{>

~

Drive A Select

l/""

J.-I-

5-1/4 Inch Diskette Drive Adapter Block Diagram

...-1

I-

Functional Description
From a programming point of view, this attachment consists of an
8-bit digital-output register in parallel with an NEe ,uPD765 or
equivalent floppy disk controller (FDe).
In the following description, drive numbers 0, 1, 2, and 3 are
equivalent to drives A, B, e, and D.

Digital-Output Register
The digital-output register (DOR) is an output-only register used
to control drive motors, drive selection, and feature enable. All
bits are cleared by the I/O interface reset line. The bits have the
following functions:
Bits 0 and 1

These bits are decoded by the hardware to
select one drive if its motor is on:
Bit

0

Drive

o 0

o (A)

1
1 0
1 1

1 (B)
2 (e)
3 (D)

I

o
Bit 2

The FDe is held reset when this bit is clear.
It must be set by the program to enable the
FDe.

Bit 3

This bit allows the FDe interrupt and DMA
requests to be gated onto the I/O interface. If
this bit is cleared, the interrupt and DMA
request I/O interface drivers are disabled.

Bits 4, 5, 6, and 7

These bits control, respectively, the motors of
drives 0, 1,2 (A, B, e), and 3 (D). If a bit is
clear, the associated motor is off, and the
drive cannot be selected.

Diskette Adapter

1-153

Floppy Disk Controller
The floppy disk controller (FDC) contains two registers that may
be accessed by the main system processor: a status register and a
data register. The 8-bit main status register contains the status
information of the FDC and may be accessed at any time. The
8-bit data register (actually consisting of several registers in a
stack with only one register presented to the data bus at a time)
stores data, commands, parameters, and provides floppy disk
drive (FDD) status information. Data bytes are read from or
written to the data register in order to program or obtain results
after a particular command. The main status register may only be
read and is used to facilitate the transfer of data between the
processor and FDC.
The bits in the main status register (hex 34F) are defined as
follows:
Bit
Number

Name

Symbol

DBO

FDD A Busy

DAB

FDD number 0 is in the Seek mode.

Description

DB'

FDD B Busy

DBB

FDD number' is in the Seek mode.

DB2

FDD C Busy

DCB

FDD number 2 is in the Seek mode.

DB3

FDD D Busy

DDB

FDD number 3 is in the Seek mode.

DB4

FDC Busy

CB

A read or write command is in process.

DB5

Non-DMA
Mode

NDM

The FDC is in the non-DMA mode.

DB6

Data Input!
Output

DIO

Indicates direction of data transfer
between FDC and processor. If DIO =
",", then transfer is from FDC data
register to the processor. If DIO = "0",
then transfer is from the processor to
the FDC data register.

DB7

Request for
Master

ROM

Indicates data register is ready to send
or receive data to or from the processor.
Both bits DIO and ROM should be used
to perform the handshaking functions of
··ready" and "direction" to the
processor.

1-154 Diskette Adapter

The FDC is capable of performing 15 different commands. Each
command is initiated by a multi-byte transfer from the processor,
and the result after execution of the command may also be a
multi-byte transfer back to the processor. Because of this
multi-byte interchange of information between the FDC and the
processor, it is convenient to consider each command as
consisting of three phases:

Command Phase
The FDC receives all information required to perform a particular
operation from the processor.

Execution Phase
The FDC performs the operation it was instructed to do.

Result Phase
After completion of the operation, status and other housekeeping
information is made available to the processor.

Diskette Adapter

1-155

Programming Considerations
The following tables define the symbols used in the command
summary, which follows.
Symbol

Name

Description

AO

Address Line 0

AO controls selection of main status
register (AO = 0) or data register (AO = 1).

C

Cylinder Number

C stands for the current/selected cylinder
(track) number of the medium.

D

Data

D sta nds for the data pattern that is going
to be written into a sector.

D7-DO

Data Bus

8-bit data bus, where 07 stands for a
most significant bit, and DO stands for a
least significant bit.

DTL

Data Length

When N is defined as 00, DTL stands for
the data length that users are going to
read from or write to the sector.

EOT

End of Track

EOT stands for the final sector number on
a cylinder.

GPL

Gap Length

GPL stands for the length of gap 3
(spacing between sectors excluding VCO
sync field).

H

Head Address

H stands for head number 0 or 1, as
specified in ID field.

HD

Head

HD stands for a selected head number 0
or 1. (H = HD in all command words.)

HLT

Head Load Time

HL T stands for the head load time in the
FDD (4 to 512 ms in 4-ms increments).

HUT

Head Unload Time

HUT stands for the head unload time after
a read or write operation has occurred (0
to 480 ms in 32-ms increments).

MF

FM or MFM Mode

If MF is low, FM mode is selected; if it is
high, MFM mode is selected only if MFM
is implemented.

MT

Multi- Track

If MT is high, a multi-track operation is to
be performed. (A cylinder under both HDO
and HD1 will be read or written.)

N

Number

N stands for the number of data bytes
written in a sector.

Symbol Descriptions (Part 1 of 2)

1-156

Diskette Adapter

Symbol

Name

Description

NCN

New Cylinder
Number

NCN stands for a new cylinder number,
which is going to be reached as a result
of the seek operation. (Desired position of
the head.)

ND

Non-DMA Mode

ND stands for operation in the non-DMA
mode.

PCN

Present Cylinder
Number

PCN stands for cylinder number at the
completion of sense-interrupt-status
command indicating the position of the
head at present time.

R

Record

R stands for the sector number, which
will be read or written.

R/W

Read/Write

R/W stands for either read (R) or write
(W)signal.

SC

Sector

SC indicates the number of sectors per
cylinder.

SK

Skip

SK stands for skip deleted-data address
mark.

SRT

Step Rate Time

SRT stands for the stepping rate for the
FDD (2 to 32 ms in 2-ms increments).

STO
ST 1
ST 2
ST 3

Status
Status
Status
Status

ST 0-3 stand for one of four registers that
store the status information after a
command has been executed. This
information is available during the result
phase after command execution. These
registers should not be confused with the
main status register (selected by AO =0).
ST 0-3 may be read only after a command
has been executed and contain
information relevant to that particular
command.

STP

Scan Test

During a scan operation, if STP =1, the
data in contiguous sectors is compared
byte-by-byte with data sent from the
processor (or DMA), and if STP =2, then
alternate sectors are read and compared.

usa,

Unit Select

US stands for a selected drive number
encoded the same as bits 0 and 1 of the
digital output register (DOR).

US1

0
1
2
3

Symbol Descriptions (Part 2 of 2)

Diskette Adapter

1-157

Command Summary
In the following table, 0 indicates "logical 0" for that bit, 1 means
"logical 1," and X means "don't care."
Oata Bus
R/W

Phase
Command

W

W

w
W
W
W
W
W
W

07 06 05 04 03 02 01 00

, ,

Read Data
MT MF SK 0
a
a
X
X
X
X
X HD US, usa
C
H
R
N
EDT
GPL
DTL

Execution

R
R
R
R
R
R
R

Result

Command

W
W

w
W
W
W
W
W
W

STa
ST'
ST 2
C
H
R
N

, ,

Read Deleted Data
MT MF SK 0
a
a
X
X HD US1 usa
X
X
X
C
H
R
N
EDT
GPL
DTL

Execution

Result

1-158

R
R
R
R
R
R
R

Diskette Adapter

STa
ST'
ST 2
C
H
R
N

Remarks
Command Codes
Sector ID information
prior to command
execution.

Data tra nsfer
between the FDD
and main system.
Status information
after command
execution.
Sector 10 information
after command
execution.

Command Codes
Sector ID information
prior to command
execution.

Data tra nsfer
between the FDD
and main system.
Status information
after command
execution.
Sector ID information
after command
execution.

Data Bus
Phase

R/W 07 06 05 04 03 02 01

DO

Remarks

Write Data
Command

W
W
W
W
W
W
W
W
W

MT MF
X
X

0

0

0

X

X

X

1
1
0
HD US1 USC

C
H
R
N
EOT
GPL
DTL

Sector ID information
to command
execution.

Execution

Result

R
R
R
R
R
R
R

Command

W
W
W
W
W
W
W
W
W

Write Deleted Data
0
0
1
1
0
0
X
X
X HD US1 USC
C
H
R
N
EOT
GPL
DTL

Execution

Result

R
R
R
R
R
R
R

Data tra nsfer
between the main
system and FDD.
Status information
after command
execution.
Sector ID information
after command
execution.

STO
ST 1
ST 2
C
H
R
N
MT MF
X
X

STO
ST 1
ST 2
C
H
R
N

Command Codes

Command Codes
Sector ID information
prior to command
execution.

Data transfer
between FDD and
main system.
Status ID information
after command
execution.
Sector ID information
after command
execution.

Diskette Adapter

1-159

Oata Bus

R/W 07 06 05 04 03 02 D1

Phase
Command

W
W

0
X

MF

X

w
W
W
W
W
W
W

Read a Track
1
SK 0
0
0
X
X
X HO US1
C
H
R
N
EDT
GPL
OTL

00

0

R
R
R
R
R
R
R

Command

W
W

Sector 10 information
prior to command
execution.

Data tra nsfer
between the FOO
and main system.
FOC reads all of
cylinder's contents
from index hole to
EDT.
Status information
after command
execution.
Sector 10 information
after command
execution.

STO
ST 1
ST 2
C
H
R
N

0
X

MF

X

0
X

Read 10
1
0

X

X

Execution

Result

1-160

R
R
R
R
R
R
R

Diskette Adapter

STO
ST 1
ST 2
C
H
R
N

Command Codes

usa

Execution

Result

Remarks

0
1
HO US1

0

Command Codes

usa
The first correct 10
information on the
cylinder is stored in
data register.
Status information
after command
execution.
Sector 10 information
during execution
phase.

Oata Bus
Phase
Command

R/W 07 06

W
W

a
X

MF
X

w
W
W
W

05 04 03 02 01 00

, ,

Format a Track
a
a
a
a
X
X
X HO US, usa
N
SC
GPL
0

Execution
Result

Command

R
R
R
R
R
R
R

W
W

w

W
W
W
W
W
W

STa
ST'
ST 2
C
H
R
N
MT MF
X
X

SK
X

,

Scan Equal
a
a
a
X
X HO US, usa
C
H
R
N
EOT
GPL
STP

Execution

Result

R
R
R
R
R
R
R

STa
ST'
ST 2

C
H
R
N

Remarks
Command Codes
Bytes/Sector
Sector /T rack
Gap 3
filler byte.
FOC formats an
entire cylinder.
Status information
after command
execution.
In this case, the 10
information has no
meaning.

Command Codes
Sector 10 information
prior to command
execution.

Data compared
between the FOO
and the main system.
Status information
after command
execution.
Sector 10 information
after Command
execution.

Diskette Adapter

1-161

Oata Bus
R/W 07 06 05 04 03 02 01

Phase

Command

W
W
W
W
W
W
W
W
W

Scan Low or Equal
MT MF SK 1
1
0
0
X
HD USl
X X X
X
C
H
R
N
EOT
GPL
STP

00
1

R
R
R
R
R
R
R

Command

W
W
W
W
W
W
W
W
W

Sector ID information
prior to command
execution.

Execution

Result

1-162

Data compared
between the FDD
and main system.
Status information
after command
execution.
Sector 10 information
after command
execution.

STO
ST 1
ST 2
C
H
R
N
Scan High or Equal
MT MF SK
1
1
1
0
X
X X
X X HD USl
C
H
R
N
EOT
GPL
STP

R
R
R
R
R
R
R

Diskette Adapter

STO
ST 1
ST 2
C
H
R
N

Command Codes

usa

Execution

Result

Remarks

1

Command Codes

usa
Sector ID information
prior to command
execution.

Data compared
between the FDD
and main system.
Status information
after command
execution.
Sector 10 information
after command
execution.

Data Bus
Phase
Command

R/W

W
W

07 06 05 04 03 02 01 DO
a

0

X

X

Recalibrate
1
0
0
X X
X 0

a

1
1
USl usa

Execution
No Result
Phase

Remarks
Command Codes
Head retracted to
track a

Sense I nterrupt Status
0
1
a
a
a
STO
PCN

Command
Result

W

Command

W
W
W

a
a
0
-SRT
---HLT

W
W

a

a

X

X

a

a

R
R

Specify
a
a

0

Command Codes
Status information at
the end of seek
operation about the
FOC
Command Codes

a
HUTNO

No Result
Phase
Command
Result

R

Command

W
W

w

Sense Drive Status
1
a
a
a
0
0
X X
X HO USl usa
ST 3

a

a

a

Seek
1
0

X

X

X

X

X

Command Codes
Status information
about FOO.
Command Codes

HO USl usa

NCN

Execution

Head is positioned
over proper cylinder
on diskette.

No Result
Phase
Command

W

Invalid
Invalid Codes

Result

R

STa

Invalid command
codes (NoOp - FOC
goes into standy
state).
STO = 80.

Diskette Adapter 1-163

No.

Bit
Name

Symbol

07

Description
07 =Oand 06 =0
Normal termination of command (NT).
Command was completed and properly
executed.
07 = 0 and 06 = 1
Abnormal termination of comma nd (AT).
Execution of command was started, but
was not successfully completed.
07 = 1 and 06 = 0
Invalid command issue (I C). Command
that was issued was never started.
07 = 1 and 06 = 1
Abnormal termination because, during
command execution, the ready signal
from FOO changed state.

Interrupt
Code

IC

05

Seek End

SE

When the FOC completes the seek
command, this flag is set to 1 (high).

04

Equipment
Check

EC

If a fault signal is received from the
FOO, or if the track 0 signal fails to occur
after 77 step pulses (recalibrate
command), then this flag is set.

03

Not Ready

NR

When the FOO is in the not-ready state
and a read or write command is issued.
this flag is set. If a read or write command
is issued to side 1 of a single-sided drive,
then this flag is set.

D2

Head Address

HO

This flag is used to indicate the state of
the head at interrupt.

01
00

Un it Select 1
Unit Select 0

US 1
US 0

These flags are used to indicate a drive
unit number at interrupt.

06

Command Status Register 0

1-164

Diskette Adapter

Bit
No.
D7

Name

Symbol

End of
Cylinder

EN

Description
When the FDC tries to access a sector
beyond the final sector of a cylinder, this
flag is set.
Not used. This bit is always 0 (low).

D6
D5

Data Error

DE

When the FDC detects a CRC error in
either the ID field or the data field, this
flag is set.

D4

Over Run

OR

If the FDC is not serviced by the main
system during data transfers within a
certain time interval, this flag is set.
Not used. This bit is always 0 (low).

D3
D2

No Data

ND

During execution of a read data, write
deleted data, or scan command, if the
FDC ca nnot find the sector specified in
the ID register, this flag is set. During
execution of the read ID command, if the
FDC cannot read the ID field without an
error, then this flag is set. During the
execution of the read a cylinder
command, if the starting sector cannot be
found, then this flag is set.

D1

Not Writable

NW

During execution of a write data, write
deleted data, or format-a-cylinder
command, if the FDe detects a
write-protect signal from the FDD, then
this flag is set.

DO

Missing
Address
Mark

MA

If the FDC cannot detect the ID address
mark, this flag is set. Also, at the same
time, the MD (missing address mark in
the data field) of status register 2 is set.

Command Status Register 1

Diskette Adapter

1-165

Bit
Name

No.

Symbol

Description

D7

-

-

Not used. This bit is always 0 (low).

D6

Control Mark

CM

During execution of the read data or scan
command, if the FDC encounters a sector
that contains a deleted data address
mark, this flag is set.

D5

Data Error in
Data Field

DD

If the FDC detects a CRC error in the data,
then this flag is set.

D4

Wrong
Cylinder

WC

This bit is related to the ND bit, and when
the contents of C on the medium are
different from that stored in the ID
register, this flag is set.

D3

Scan Equal
Hit

SH

During execution of the scan command, if
the condition of "equal" is satisfied, this
flag is set.

D2

Scan Not
Satisfied

SN

During execution of the scan command,
if the FDC cannot find a sector on the
cylinder that meets the condition, then
this flag is set.

D1

Bad Cylinder

BC

This bit is related to the ND bit, and when
the contents of C on the medium are
different from that stored in the ID
register, and the contents of C is FF, then
this flag is set.

DO

Missing
Address Mark
in Data Field

MD

When data is read from the medium, if
the FDC cannot find a data address mark
or deleted data address mark, then this
flag is set.

Command Status Register 2

1-166

Diskette Adapter

Bit
Name

No.

Description

Symbol

D7

Fault

FT

This bit is the status of the fault signal
from the FDD.

D6

Write
Protected

WP

Th is bit is the status of the
write· protected signal from the FDD.

D5

Ready

RY

This bit is the status of the ready signal
from the FDD.

D4

Track

TO

This bit is the status of the track
from the FDD.

D3

Two Side

TS

Th is bit is the status of the two-side
signal from the FDD.

D2

Head Address

HD

This bit is the status of the side-select
signal from the FDD.

D1

Unit Select 1

US 1

This bit is the status of the unit-select-1
signal from the FDD.

DO

Unit Select

a

usa

This bit is the status of the unit-select-O
signal from the FDD.

a

a signal

Command Status Register 3

Programming Summary
FDC Data Register

1/0 Address Hex 3F5

FDC Main Status Register

1/0 Address Hex 3F4

Digital Output Register

1/0 Address Hex 3F2

Bit

a
1
2

3
4
5
6
7

Drive
00: DR #A 10: DR #C
Select
01 : DR #B 11 : DR #D
Not FDC Reset
Enable INT & DMA Requests
Drive A Motor Enable
Drive B Motor Enable
Drive C Motor Enable
Drive D Motor Enable

All bits cleared with channel reset.

ope

Registers

Diskette Adapter

1-167

FDC Constants (in hex)
N:
SC:
HUT:
SRT:

02
08
F
C

GPL Format: 05
GPLRIW:
2A
HLT:
01
(6 ms track-to-track)

Drive Constants
Head Load
Head Settle
Motor Start

35 ms
15 ms
250ms

Comments
•

Head loads with drive select, wait HD load before R/W.

•

Following access, wait HD settle time before R/W.

•

Drive motors should be off when not in use. Only A or Band
CorD may run simultaneously. Wait motor start time before
R/W.

•

Motor must be on for drive to be selected.

•

Data errors can occur while using a home television as the
system display. Locating the TV too close to the diskette area
can cause this to occur. To correct the problem, move the TV
away from, or to the opposite side of the system unit.

System I/O Channel Interface
All signals are TTL-compatible:
Most Positive Up Level
Least Positive Up Level
Most Positive Down Level
Least Positive Down Level

1-168

Diskette Adapter

5.5
2.7
0.5
-0.5

Vdc
Vdc
Vdc
Vdc

The following lines are used by this adapter.
+ DO-7

(Bidirectional, load: 1 74LS, driver: 74LS 3-state).
These eight lines form a bus by which all commands,
status, and data are transferred. Bit 0 is the low-order
bit.

+AO-9

(Adapter input, load: 174LS)
These ten lines form an address bus by which a
register is selected to receive or supply the byte
transferred through lines DO-7. Bit 0 is the low-order
bit.

+AEN

(Adapter input, load: 1 74LS)
The content of lines AO-9 is ignored if this line is
active.

-lOW

(Adapter input, load: 1 74LS)
The content of lines DO-7 is stored in the register
addressed by lines AO-9 or DACK2 at the trailing
edge of this signal.

-lOR

(Adapter input, load: 1 74LS)
The content of the register addressed by lines AO-9
or DACK2 is gated onto lines DO-7 when this line is
active.

-DACK2 (Adapter input, load: 274LS)
This line being active degates output DRQ2, selects
the FDC data register as the source/destination of
bus DO-7, and indirectly gates T /C to IRQ6.
+T/C

(Adapter input, load: 4 74LS)
This line and DACK2 being active indicates that the
byte of data for which the DMA count was initialized
is now being transferred.

+RESET

(Adapter input, load: 1 74LS)
An up level aborts any operation in process and
clears the digital output register (DaR).

Diskette Adapter

1-169

+DRQ2

(Adapter output, driver: 74LS 3-state)
This line is made active when the attachment is ready
to transfer a byte of data to or from main storage.
The line is made inactive by DACK2 becoming
active or an I/O read of the FDC data register.

+IRQ6

(Adapter output, driver: 74LS 3-state)
This line is made active when the FDC has
completed an operation. It results in an interrupt to a
routine which should examine the FDC result bytes
to reset the line and determine the ending condition.

Drive A and B Interface
All signals are TTL-compatible:
Most Positive Up Level
Least Positive Up Level
Most Positive Down Level
Least Positive Down Level

5.5 Vdc
2.4 Vdc
0.4 Vdc
-0.5 Vdc

All adapter outputs are driven by open-collector gates. The
drive(s) must provide termination networks to Vcc (except motor
enable, which has a 2000-ohm resistor to Vcc).
Each adapter input is terminated with a ISO-ohm resistor to Vcc.

Adapter Outputs
-Drive Select A and B

1-170

Diskette Adapter

(Driver: 7438)
These two lines are used by drives A
and B to degate all drivers to the
adapter and receivers from the
attachment (except motor enable) when
the line associated with a drive is
inactive.

-Motor Enable A and B (Driver: 7438)
The drive associated with each of these
lines must control its spindle motor
such that it starts when the line
becomes active and stops when the line
becomes inactive.
-Step

(Driver: 7438)
The selected drive moves the
read/write head one cylinder in or out
per the direction line for each pulse
present on this line.

-Direction

(Driver: 7438)
F or each recognized pulse of the step
line, the read/write head moves one
cylinder toward the spindle if this line
is active, and away from the spindle if
inactive.

-Head Select

(Driver: 7438)
Head 1 (upper head) will be selected
when this line is active (low).

-Write Data

(Driver: 7438)
F or each inactive to active transition of
this line while write enable is active,
the selected drive causes a flux change
to be stored on the diskette.

-Write Enable

(Driver: 7438)
The drive disables write current in the
head unless this line is active.

Diskette Adapter

1-171

Adapter Inputs
-Index

The selected drive supplies one pulse
per diskette revolution on this line.

- Write Protect

The selected drive makes this line
active if a write-protected diskette is
mounted in the drive.

-Track 0

The selected drive makes this line
active if the read/write head is over
track O.

-Read Data

The selected drive supplies a pulse on
this line for each flux change
encountered on the diskette.

1-172

Diskette Adapter

34-Pin Keyed
Edge Connector

Component
Side
Note: Lands 1-33 (odd numbers) are on the back of the
board. Lands 2-34 (even numbers) are on the front. or
component side.

-

At Standard TTL Levels

Land
Number

Ground-Odd Numbers

1-33

Unused

2.4.6

Index
Motor Enable A

Dis kette
On ves

8
10

Drive Select B

12

Drive Select A

14

Motor Enable B

16

Direction (Stepper Motor)

18

Step Pulse

20

Write Data

22

Write Enable

24

Track 0

26

Write Protect

28

Read Data

3()

Select Head 1

32

Unused

34

-

r--

Driv e
Ada pter

'---

Connector Specifications (Part 1 of 2)

Diskette Adapter

1-173

37-Pin
D-Shell
Connector

Rear Panel

o
20

c.
.cO
c~ c Q

cc

•
•
•
• •
37

0

-

Ex ternal
Dr ives

At Standard TTL Levels

Pin
Number

Unused

1-5

Index

6

Motor Enable C

7

Drive Select D

8

Drive Select C

9

Motor Enable D

10

Direction (Stepper Motor)

11

Step Pulse

12

Write Data

13

Write Enable

14

Track 0

15

Write Protect

16

Read Data

17

Select Head 1

18

Ground

20-37

Connector Specifications (Part 2 of 2)

1-174 Diskette Adapter

r-

Drive
Adap ter

' -

IBM 5-1/4" Diskette Drive

The system unit has space and power for one or two 5-1/4 inch
diskette drives. A drive can be single-sided or double-sided with
40 tracks for each side, is fully self-contained, and consists of a
spindle drive system, a read positioning system, and a
read/write/erase system.
The diskette drive uses modified frequency modulation (MFM) to
read and write digital data, with a track-to-track access time of 6
milliseconds.
To load a diskette, the operator raises the latch at the front of the
diskette drive and inserts the diskette into the slot. Plastic guides
in the slot ensure the diskette is in the correct position. Closing the
latch centers the diskette and clamps it to the drive hub. After 250
milliseconds, the servo-controlled dc drive motor starts and drives
the hub at a constant speed of 300 rpm. The head positioning
system, which consists of a 4-phase stepper-motor and band
assembly with its associated electronics, moves the magnetic head
so it comes in contact with the desired track of the diskette. The
stepper-motor and band assembly uses one-step rotation to cause
a one-track linear movement of the magnetic head. No operator
intervention is required during normal operation. During a write
operation, a 0.013-inch (0.33 millimeter) data track is recorded,
then tunnel-erased to 0.012 inch (0.030 millimeter). If the diskette
is write-protected, a write-protect sensor disables the drive's
circuitry, and an appropriate signal is sent to the interface.
Data is read from the diskette by the data-recovery circuitry,
which consists of a low-level read amplifier, diiferentiator,
zero-crossing detector, and digitizing circuits. All data decoding is
done by an adapter card.
The diskette drive also has the following sensor systems:
1. The track 00 switch, which senses when the head/carriage
assembly is at track 00.

Diskette Drive

1-175

2. The index sensor, which consists of an LED light source and
phototransistor. This sensor is positioned so that when an
index hole is detected, a digital signal is generated.
3. The write-protect sensor disables the diskette drive's
electronics whenever a write-protect tab is applied to the
diskette.
For interface information, refer to "IBM 5-1/4" Diskette Drive
Adapter" earlier in this section.
Media

Industry-compatible 5-1/4 inch diskette

Tracks per inch

48

Number of tracks

40

Dimensions
Height
Width
Depth
Weight

3.38
5.87
8.00
4.50

Temperature
(Exclusive of media)
Operating
Non operating

50 0 F to 11 2 0 F (10 0 C to 44 0 C)
-40 0 F to 140 0 F (-40 0 C to 60 0 C)

Relative humidity
(Exclusive of media)
Operating
Non operating

20% to 80% (non condensing)
5% to 95% (non condensing)

Seek Time

6 ms track-to-track

Head Settling Time

15 ms (last track addressed)

Error Rate

1 per 109 (recoverable)
1 per 10 '2 (non recoverable)
1 per 106 (seeks)

Head Life

20,000 hours (normal use)

Media Life

3.0 x 106 passes per track

Disk Speed

300 rpm +/- 1.5% (long term)

Instantaneous Speed Variation

+/- 3.0%

Start/Stop Time

250 rns (maximum)

Transfer Rate

250K bits/sec

Recording Mode

MFM

Power

+12 Vdc +/- 0.6 V, 900 rnA average
+5 Vdc +/- 0.25 V, 600 mA average

Mechanical and Electrical Specifications

1-176

Diskette Drive

inches (85.85 mm)
inches (149.1 0 mrn)
inches (203.2 mrn)
pounds (2.04 kg)

Diskettes

The IBM 5-1/4" Diskette Drive uses a standard 5.25-inch
(133.4-millimeter) diskette. For programming considerations,
single-sided, double-density, soft-sectored diskettes are used for
single-sided drives. Double-sided drives use double-sided,
double-density, soft-sectored diskettes. The figure below is a
simplified drawing of the diskette used with the diskette drive.
This recording medium is a flexible magnetic disk enclosed in a
protective jacket. The protected disk, free to rotate within the
jacket, is continuously cleaned by the soft fabric lining of the
jacket during normal operation. Read/write/erase head access is
made through an opening in the jacket. Openings for the drive hub
and diskette index hole are also provided.

__ I

0.140 Inch
0.25 ± 0.01 Inch
mm)-ll-f6.30 ± 0.25 mm)

(~.56
I
1

J -..:-

I

---0,
I

@

m
~5.25Inch_'

, - ( 1 3 3 . 4 millf'l

I

.r:;

Oxide Coated
Mylar Disk

Sealed
Protective
Jacket

.............

"\ \

E

gE

: : It)

I

5.25 Inch

66 1(133.4mm)
+1 +1

o ~
co CD
·co

liner

/

/

I

Me
Head
Aperture

Recording Medium

Diskettes

1-177

Notes:

1-178

Diskettes

IBM Fixed Disk Drive Adapter

The fixed disk drive adapter attaches to one or two fixed disk
drive units, through an internal daisy-chained flat cable
(data/control cable). Each system supports a maximum of one
fixed disk drive adapter and two fixed disk drives.
The adapter is buffered on the I/O bus and uses the system board
direct memory access (DMA) for record data transfers. An
interrupt level also is used to indicate operation completion and
status conditions that require processor attention.
The fixed disk drive adapter provides automatic II-bit burst error
detection and correction in the form of 32-bit error checking and
correction (ECC).
The device level control for the fixed disk drive adapter is
contained on a ROM module on the adapter. A listing of this
device level control can be found in "Appendix A: ROM BIOS
Listings. "
WARNING:

The last cylinder on the fixed disk drive is
reserved for diagnostic use. Diagnostic write
tests will destroy any data on this cylinder.

Fixed Disk Controller
The disk controller has two registers that may be accessed by the
main system processor: a status register and a data register. The
8-bit status register contains the status information of the disk
controller, and can be accessed at any time. The 8-bit data
register (actually consisting of several registers in a stack with
only one register presented to the data bus) stores data,
commands, parameters, and provides the disk controller's status
information. Data bytes are read from, or written to the data
register in order to program or obtain the results after a particular
command. The status register is a read-only register, and is used
to help the transfer of data between the processor and the disk
controller. The controller-select pulse is generated by writing to
port address hex 322.
Fixed Disk Adapter

1-179

.

.....
.....

00

o

'"Ij

><.

(1)

Serializer I
Deserializer

0..

oen_.

J2

~

>
0..

Data
Separator

Serdes
ECC

~

"0
.....

1/0

(1)

'"l

Edge
Connector
Data Bus
DB7-DBO'

Control

r---"""-....,

Sector
Buffer

8-Bit
Processor

Fixed Disk Drive Adapter Block Diagram

TO
} Drives

Programming Considerations
Status Register
At the end of all commands from the system board, the disk
controller returns a completion status byte back to the system
boarq. This byte informs the system unit if an error occurred
during the execution of the command. The following shows the
format of this byte.

o

6

5

4

3

2

o

d

o

o

o

e

o

Bits 0, 1, 2, 3, 4, 6, 7

These bits are set to zero.

Bit 1

When set, this bit shows an error has
occurred during command execution.

Bit 5

This bit shows the logical unit number of
the drive.

If the interrupts are enabled, the controller sends an interrupt
when it is ready to transfer the status byte. Busy from the disk
controller is unasserted when the byte is transferred to complete
the command.

Sense Bytes
If the status register receives an error (bit 1 is set), then the disk
controller requests four bytes of sense data. The format for the
four bytes is as follows:
7

6

5

Byte 0

Address
Valid

0

Error Type

Byte 1

0

0

d

Bits

Byte 2
Byte 3

Cylinder High

4

2

3

I

1

0

Error Code
Head Number

Sector Number
Cylinder Low

Remarks
d = drive

Fixed Disk Adapter

1-181

Byte 0

Bits 0, 1,2,3

Error code.

Byte 0

Bits 4, 5

Error type.

Byte 0

Bit 6

Set to 0 (spare).

Byte 0

Bit 7

The address valid bit. Set only when
the previous command required a disk
address, in which case it is returned
as a 1; otherwise, it is a O.

The following disk controller tables list the error types and error
codes found in byte 0:
Error Type
Bits

1-182

Error Code

5 4

3

2 1 0

0

0

0

0

0

0

The controller did not detect any error
during the execution of the previous
operation.

0

0

0

0

0

1

The controller did not detect an index signal
from the drive.

0

0

0

0

1 0

The controller did not get a seek-complete
signal from the drive after a seek operation
(for all non-buffered step seeks).

0

0

0

0

1

1

The controller detected a write fault from
the drive during the last operation.

0

0

0

1 0

0

After the controller selected the drive, the
drive did not respond with a ready signal.

0

0

0

1 0

1

0

0

0

1

0

0

0

1

1

1

Not used.

0

0

1 0

0

0

The drive is still seeking. This status is
reported by the Test Drive Ready command
for an overlap seek condition when the
drive has not completed the seek. No
time-out is measured by the controller for
the seek to complete.

1 0

Fixed Disk Adapter

Description

Not used.
After stepping the maximum number of
cylinders, the controller did not receive the
track 00 signa I from the drive.

Error Type
Bits

Error Code

5 4

3 2

1 0

0

1

0 0

0 0

0

1

0 0 0

0

1

0 0

Description
ID Read Error: The controller detected an
ECC error in the target ID field on the disk.

1

Data Error: The controller detected an
uncorrectable ECC error in the target sector
during a read operation.

1 0

Address Mark: The controller did not d'etect
the target address mark (AM) on the disk.

0

1

0 0

1

0

1

0

1

0 0

Sector Not Found: The controller found the
correct cylinder and head, but not the
target sector.

0

1

0

1

0

Seek Error: The cyli nder or head address
(either or both) did not compare with the
expected target address as a resu It of a
seek.

1

1

Not used.

0

1

0

1

1 0

Not used.

0

1

0

1

1

Not used.

0

1

1 0

0 0

Correctable Data Error: The controller
detected a correctable ECC error in the
target field.

0

1

1

0

0 1

Bad Track: The controller detected a bad
track flag during the last operation. No
retries are attempted on this error.

1

Fixed Disk Adapter

1-183

Error Type
Bits

1-184

2

Description

5

4

3

1

a

a a a a

Invalid Command: The controller has
received an invalid command from the
system unit.

1

a

0

a a

Illegal Disk Address: The controller
detected an address that is beyond the
maximum range.

Error Type
Bits

Error Code

1

0

1

Error Code
Description

5 4

3

1

1

a a a a

RAM Error: The controller detected a data
error during the RAM sector-buffer
diagnostic test.

1

1

a a a

1

Program Memory Checksum Error: During
this internal diagnostic test, the controller
detected a program-memory checksum
error.

1

1

a a

a

ECC Polynominal Error: During the
controller's internal diagnostic tests, the
hardware ECC generator failed its test.

2

1 0

1

Fixed Disk Adapter

Data Register
The processor specifies the operation by sending the 6-byte device
control block (DCB) to the controller. The figure below shows the
composition of the DCB, and defines the bytes that make up the
DCB.

Bits
Byte 0
Byte 1
Byte 2

7

6

5

Command Class
0

I

0

Cylinder High

d

4

I
I

2

3

1

0

Opcode
Head Number
Sector Number

Byte 3

Cylinder Low

Byte 4

Interleave or Block Count

Byte 5

Control Field

Byte 0 - Bits 7, 6, and 5 identify the class of the command.
Bits 4 through 0 contain the Opcode command.
Byte 1 - Bit 5 identifies the drive number.
Bits 4 through 0 contain the disk head number to be
selected.
Bits 6 and 7 are not used.
Byte 2 - Bits 6 and 7 contain the two most significant bits of the
cylinder number.
Bits 0 through 5 contain the sector number.
Byte 3 - Bits 0 through 7 are the eight least significant bits of the
cylinder number.
Byte 4 - Bits 0 through 7 specify the interleave or block count.
Byte 5 - Bits 0 through 7 contain the control field.

Fixed Disk Adapter

1-185

Control Byte
Byte 5 is the control field of the DCB and allows the user to select
options for several types of disk drives. The format of this byte is
as follows:
Bits

7

6

5

4

3

2

a

0

0

0

s

0
s

s

Remarks
r = retries
s = step option
a = retry option on data ECC
error

Bit 7

Disables the four retries by the controller on all
disk-access commands. Set this bit only during the
evaluation of the performance of a disk drive.

Bit 6

If set to 0 during read commands, a reread is
attempted when an ECC error occurs. If no error
occurs during reread, the command will complete
with no error status. If this bit is set to 1, no reread is
attempted.

Bits 5, 4, 3 Set to O.
Bits 2, 1, 0 These bits define the type of drive and select the step
option. See the following figure.
Bits

1-186

2. 1. 0
0

0

0

This drive is not specified and defaults to 3 milliseconds per
step.

0

0

1

0

1 0

0

1

N/A
N/A
N/A

1

1 0 0

200 microseconds per step.

1 0

70 microseconds per step (specified by BIOS).

1

1

1 0

3 milliseconds per step.

1

1

3 milliseconds per step.

1

Fixed Disk Adapter

Command Summary
Command

Remarks

Data Control Block

Test Drive

Bit

7 6 5 4 3 2 1 0

Ready

Byte 0

0

(Class 0,

Byte 1

0

0

010 0 0
0 dlx x x

0 0
x

x

Opcode 00)

= drive (0 or
x = don't care
d

1)

Bytes 2, 3,4, 5

= don't

care

= drive (0 or 1)
= don't care
r = retries
s = Step Option
Bytes 2, 3, 4 = don't

Recalibrate

Bit

7 6 5 4 3 2 1 0

d

(Class 0,

Byte 0

0

1

x

Opcode 01)

Byte 1
Byte 5

0

0

0

010 0
0 dlx x

x

x

x

r

0

s

s

s

0

0

0 0

care
Reserved

This Opcode is not

(Class 0,

used.

Opcode 02)
Request Sense

Bit

7 6 5 4 3 2 1 0

Status

Byte 0

0

(Class 0,

Byte 1

0

0

010 0
0 d x x

I

0

1

1

x

x

x

= drive (0 or 1 )
= don't care
Bytes 2, 3,4,5 = don't

d
x

care

Opcode 03)
Format Drive

Bit

7 6 5 4 3 2 1 0

(Class 0,

Byte 0

0

0

Opcode 04)

Byte 1

0

0

Byte 2

01 0 0 1 0 0
d I Head Number
10 0 0 0 0 0
Cylinder Low

ch

Byte 3
Byte 4

0

Byte 5

r

Ready Verify

Bit

7 6 5 4 3 2 1 0

(Class 0,

Byte 0

0

0

Opcode 05)

Byte 1

0

0

Byte 2

0 01 Interleave
0 0 0 0 s s s

ch

01 0 0 1 0 1
d Head Number

I

I

Sector Number

= drive (0 or 1 )
= retries
s = step option
ch = cylinder high
d
r

Interleave: 1 to 16
for 512-byte sectors

= drive (0 or 1 )
r = retries
s = step option
a = retry option on

d

Byte 3

Cylinder Low

data ECC

Byte 4

Block Count

ch

ByteS

r

a 0

0

0

s

s

= cylinder high

s

Fixed Disk Adapter

1-187

Command

Data Control Block

Format Track

Bit

7

(Class 0,

Byte

Opcode 06)

Byte 1

a a
a a

Byte 2

ch

a

6

4

5

2

Remarks

a
a

1

a

1 1
010
d Head Number

I

Ia

Byte 3

3

0

0

0 0 0

0

Byte 5

r

a 01 Interleave
0 0 0 0 s s s
6

Format Bad

Bit

7

4

3

2

1 0

Track

Byte 0

0 0

01 0

0

1

1

(Class 0,

Byte 1

0 0

d

Opcode 07)

Byte 2

5

1

I Head Number

ch 10 0 0 0 0
Cylinder Low

Byte 3

7 6 5 4 3 2 1 0
0 0 01 0 1 0 0 a
0 0 d Head Number

Bit

Opcode 08)

Byte 1

s

Interleave: 1 to 16

s

I

Byte 2

I

ch

Byte 3
Byte 5

Interleave

a a

Sector Number

0 0

a

0

s

d = drive (0 or 1 )
r = retries
a = retry option on
data ECC error

Cylinder Low
r

r = retries
s = step option

for 512-byte sectors

r

01
0

d = drive (0 or 1)

s

0 0

a

Interleave: 1 to 16
for 512-byte sectors

ch = cylinder high

Byte 5

Byte 0

ch =cylinder high

0

Byte 4

Read

r = retries
s = step option

Cylinder Low

Byte 4

(Class 0,

d = drive (0 or 1 )

s = step option
s

s

ch =cylinder high

Reserved

This Opcode is not

(Class 0,

used

(Opcode 09)
Write

Bit

7

(Class 0,

Byte 0

0 0

6

01 0

Opcode aA)

Byte 1

0 0

d

Byte 2

ch

I

Byte 3

4

3

2

1 0

1 0
1

0

I Head Number

Block Count

0 0

r

7 6 5 4 3 2 1 0
0 0 01 0 1 0 1 1
0 0 d I Head Number

Seek

Bit
Byte

Opcode OB)

Byte 1

a

r = retries
s = step option
ch = cylinder high

Sector Number

Byte 5

(Class 0,

d = drive (0 or 1 )

Cylinder Low

Byte 4
0

0

s

s

a

0 0 0
ch 10
Cylinder Low

Byte 2
Byte 3

1-188

5

s

0

r = retries
s = step option
x = don't care
ch = cylinder high

Byte 4

x

x

x

x

x

x

x

x

Byte 5

r

0 0

a

0

s

s

s

Fixed Disk Adapter

d = drive (0 or 1 )

Command

Remarks

Data Control Block

Initialize

4

Drive

0

3

2
0

0

Bytes 1, 2, 3,4,5 =

0

don't care

Characteristics*
(Class 0,
Opcode OC)
Read ECC Burst

4

Error Length

0

3

2

0

Bytes 1, 2, 3,4,5 =
don't care

0

(Class 0,
Opcode OD)
Read Data from

4

Sector Buffer

0

3

2

0

Bytes 1, 2, 3, 4, 5 =

0

don't care

(Class 0,
Opcode OE)
Write Data to

4

Sector Buffer

0

3

2

0

Bytes 1, 2, 3, 4, 5 =
don't care

(Class 0,
Ope ode OF)
RAM

4

3

2

1 0

Bytes 1, 2, 3, 4, 5 =

Diagnostic

0

0

0

0

don't care

0

(Class 7,
Opcode 00)
Reserved

This Opcode is not

(Class 7,

used

Opcode 01)
Reserved

This Opcode is not

(Class 7,

used

Opcode 02)
*Initialize Drive Characteristics: The DCB must be followed by eight additional bytes.
Maximum number of cylinders

(2 bytes)

Maximum number of heads

(1 byte)

Start reduced write current cylinder

(2 bytes)

Start write precompensation cylinder

(2 bytes)

Maximum ECC data burst length

(1 byte)

Fixed Disk Adapter

1-189

Command

Remarks

Data Control Block

2
0

Drive

Bit

7

6 5 4

Diagnostic

Byte 0

1

1

1 10 0

(Class 7,

Byte 1

0

0

d

Opcode 03)

Byte 2

x

x

x x
x x x x

Byte 3

x

x

x

x

Byte 4
Byte 5

x x x x x
r 0 0 0 0

Controller

Bit

7

6 5 4

Internal

Byte 0

1

1

1 10

Read Long*

Bit

7

6 5 4

(Class 7,

Byte 0

1

1

3

Ix

1

0

d - drive (0 or 1 )

1

1

s = step option

x x

r = retries

x

x

x = don't care

x

x

x

x

x

x

s

s

s

3

2

1

0

1 0

0
0

don't care

3

2

1

0

d = (0 or 1)

1 10 0

1

0

1

x

Bytes 1, 2, 3, 4, 5 =

Diagnostics
(Class 7,
Opcode 04)

Opcode 05)

Byte 1

0 0

Byte 2

ch

J

d

I Head Number

ch =cylinder high

Sector Number

Cylinder Low

Byte 3
Byte 4

Block Count

Byte 5

r

0 0 0 0

s

s

2

1

Write Long**

Bit

7

6 5 4

(Class 7,

Byte 0

1

1

Opcode 06)

Byte 1

0 0

Byte 2

ch

3

1 10 0
d

I

Byte 3

s

0
1 1 0

I Head Number

Sector Number

Block Count
r

0

0 0 0

s

s

s

*Returns 512 bytes plus 4 bytes of ECC data per sector.
**Requires 512 bytes plus 4 bytes of ECC data per sector.

1-190

Fixed Disk Adapter

d = drive (0 or 1)
s = step option
r = retries
ch = cylinder high

Cylinder Low

Byte 4
Byte 5

s = step option
r = retries

Programming Summary
The two least-significant bits of the address bus are sent to the
system board's I/O port decoder, which has two sections. One
section is enabled by the I/O read signal (- lOR) and the other by
the I/O write signal (-lOW). The result is a total of four
read/write ports assigned to the disk controller board.
The address enable signal (AEN) is asserted by the system board
when DMA is controlling data transfer. When AEN is asserted,
the I/O port decoder is disabled.
The following figure is a table of the four read/write ports:
R/W

Port Address

Function

Read
Write

320
320

Read data (from controller to system unit).
Write data (from system unit to controller).

Read
Write

321
321

Read controller hardware status.
Controller reset.

Read
Write

322
322

Reserved.
Generate controller-select pulse.

Read
Write

323
323

Not used.
Write pattern to DMA and interrupt mask
register.

Fixed Disk Adapter

1-191

System I/O Channel Interface
The following lines are used by the disk controller:
AO-AI9

Positive true 20-bit address. The least-significant 10
bits contain the I/O address within the range of hex
320 to hex 323 when an I/O read or write is
executed by the system unit. The full 20 bits are
decoded to address the read-only storage (ROS)
between the addresses of hex C8000 and C9FFF.

DO-D7

Positive 8-bit data bus over which data and status
information is passed between the system board and
the controller.

lOR

Negative true signal that is asserted when the system
board reads status or data from the controller under
either programmed I/O or DMA control.

lOW

Negative true signal that is asserted when the system
board sends a command or data to the controller
under either programmed I/O or DMA control.

AEN

Positive true signal that is asserted when the DMA in
the system board is generating the I/O Read (- lOR)
or I/O Write (- lOW) signals and has control of the
address and data buses.

RESET

Positive true signal that forces the disk controller to
its initial power-up condition.

IRQ 5

Positive true interrupt request signal that is asserted
by the controller when enabled to interrupt the
system board on the return ending status byte from
the controller.

DRQ 3

Positive true DMA-request signal that is asserted by
the controller when data is available for transfer to or
from the controller under DMA control. This signal
remains active until the system board's DMA
channel activates the DMA-acknowledge signal
(-DACK 3) in response.

DACK 3

This signal is true when negative, and is generated by
the system board DMA channel in response to a
DMA request (DRQ 3).

1-192

Fixed Disk Adapter

Pin 34 _ _

~--;

Pin 20
Pin 1
Pin 2

Pin 1
Signal
Ground - Odd Numbers
Reserved
-Reduced Write Current
-Write Gate
-Seek Complete
-Track 00
Disk
Drive
Connector

J1

-Write Fault
-Head Select 2 0
-Head Select 21
-Index
-Ready
-Step
-Drive Select 1
-Drive Select 2
-Direction In

Position 5 has No Pin
(for Cable Orientation)
Pin Number

1-33
4,16,30,32
2
6
8
10
12
14
18
20
22
24
26
28
34

Signal

Pin Number

Ground

2,4,6,8,12,16,20
1
3, 7
9, 10, 5 (No Pin)
11
13
14
15
17
18
19

Drive Select
Reserved
Spare

oisk
orive

Ground

Connector
J 2 or J3

-MFM Write Data

MFM Write Data
Ground
MFM Read Data
-MFM Read Data
Ground

Disk
Drive
Connector

J1

Disk
Adapter
Connecto
J2 or J3

Fixed Disk Adapter Interface Specifications

Fixed Disk Adapter

1-193

Notes:

1-194

Fixed Disk Adapter

IBM 10MB Fixed Disk Drive

The disk drive is a random-access storage device that uses two
non-removable 5-1/4 inch disks for storage. Each disk surface
employs one movable head to service 306 cylinders. The total
formatted capacity of the four heads and surfaces is 10 megabytes
(1 7 sectors per track with 512 bytes per sector and a total of
1224 tracks).
An impact-resistant enclosure provides mechanical and
contamination protection for the heads, actuator, and disks. A
self-contained recirculating system supplies clean air through a
0.3-micron filter. Thermal isolation of the stepper and spindle
motor assemblies from the disk enclosure results in a very low
temperature rise within the enclosure. This isolation provides a
greater off-track margin and the ability to perform read and write
operations immediately after power-up with no thermal
stabilization delay.

Fixed Disk Drive

1-195

Media

Rigid media disk

Number of Tracks

1224

Track Density

345 tracks per inch

Dimensions
Height
Width
Depth
Weight

3.25 inches (8255 mm)
5.75 inches (146.05 mm)
8.0 inches (203.2 mm)
4.6 Ib (208 kg)

Temperature
Operating
Non operating

40°F to 122°F (4°C to 50°C)
-40°F to 140°F (-40°C to 60°C)

Relative Hu midity
Operating
Maximum Wet Bulb

8% to 80% (non condensing)
78° F (26° C)

Shock
Operating
Non operating

10 Gs
20 Gs

Access Time

3 ms track-to-track

Average Latency

8.33 ms

Error Rates
Soft Read Errors
Hard Read Errors
Seek Errors

1 per 10 10 bits read
1 per 10 12 bits read
1 per 106 seeks

Design Life

5 years (8,000 hours MTF)

Disk Speed

3600 rpm ±1 %

Transfer Rate

5.0 M bits/sec

Recording Mode

MFM

Power

+12 Vdc ± 5% 1.8 A (4.5 A maximum)
+5 Vdc == 5% 0.7 A (1.0 A maximum)

Maximum Ripple

1% with equivalent resistive load

Mechanical and Electrical Specifications

1-196

Fixed Disk Drive

IBM Memory Expansion Options

Three memory expansion options and a memory module kit are
available for the IBM Personal Computer XT. They are the
32KB, 64KB, and 64/256KB Memory Expansion Options and
the 64KB Memory Module Kit. The base system has a standard
128K of RAM on the system board. One or two memory module
kits can be added, providing the system board with 192K or 256K
of RAM. The base 64/256K option has a standard 64K of RAM.
One, two, or three 64K memory module kits may be added,
providing the 64/256K option with 128K, 192K, or 256K of
RAM. A maximum of 256K or RAM can be installed on the
system board as modules without using any of the system unit
expansion slots or expansion options. The system board must be
populated to the maximum 256K of RAM before any memory
expansion options can be installed.
An expansion option must be configured to reside at a sequential
32K or 64K memory address boundary within the system address
space. This is done by setting DIP switches on the option.
The 32K and 64K options both use 16K by 1 bit memory
modules, while the 64/256K option uses 64K by 1 bit memory
modules. On the 32K and 64/256K options, 16-pin
industry-standard parts are used. On the 64K option, stacked
modules are used resulting in a 32K by 1 bit, 18-pin module. This
allows the 32K and 64K options to have approximately the same
physical size.
All memory expansion options are parity checked. If a parity
error is detected, a latch is set and an I/O channel check line is
activated, indicating an error to the processor.
In addition to the memory modules, the memory expansion
options contain the following circuits: bus buffering, dynamic
memory timing generation, address multiplexing, and card-select
decode logic.
Dynamic-memory refresh timing and address generation are
functions that are performed on the system board and made
available in the I/O channel for all devices.
Memory Expansion Options

1-197

To allow the system to address 32K, 64K, or 64/256K memory
expansion options, refer to "Appendix G: Switch Settings" for the
proper memory expansion option switch settings.

Operating Characteristics
The system board operates at a frequency of 4.77 MHz, which
results in a clock cycle of 210 ns.
Normally four clock cycles are required for a bus cycle so that an
840-ns memory cycle time is achieved. Memory-write and
memory-read cycles both take four clock cycles, or 840 ns.
General specifications for memory used on all cards are:
16K by 1 Bit

32K by 1 Bit

64K by 1 Bit

Access

250 ns

250 ns

200 ns

Cycle

410 ns

410 ns

345 ns

Memory Module Description
Both the 32K and the 64K options contain 18 dynamic memory
modules. The 32K memory expansion option utilizes 16K by 1
bit modules, and the 64K memory expansion option utilizes 32K
by 1 bit modules.
The 64/256K option has four banks of 9 pluggable sockets. Each
bank will accept a 64K memory module kit, consisting of 9 (64K
by 1) modules. The kits must be installed sequentially into banks
1, 2, and 3. The base 64/256K option comes with modules
installed in bank 0, providing 64K of memory. One, two, or three
64K bits may be added, upgrading the option to 128K, 192K, or
256K of memory.

1-198

Memory Expansion Options

The 16K by 1 and the 32K by 1 modules require three voltage
levels: +5 Vdc, -5 Vdc, and + 12 Vdc. The 64K by 1 modules
require only one voltage level of + 5 Vdc. All three memory
modules require 128 refresh cycles every 2 ns. Absolute
maximum access times are:
16K by 1 Bit

32K by 1 Bit

64K by 1 Bit

From RAS

250 ns

250 ns

200 ns

From

CAS

165 ns

165 ns

115 ns

Pin

16K by 1 Bit Module
(used on 32K option)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

-5 Vdc
Data In**
-Write
-RAS
AO
A2
A1
+12 Vdc
+5 Vdc
A5
A4
A3
A6
Data Out*'
-CAS
GND

*
*

32K by 1 Bit Module
(used on 64K option)
-5 Vdc
Data In*'
-Write
-RAS 0
-RAS 1
AO
A2
A1
+12 Vdc
+5 Vdc
A5
A4
A3
A6
Data Out"
-CAS 1
-CAS 0
GND

64K by 1 Bit Module
(used on 64/256K option)
N/C

Data In'''
-Write
-RAS
AO
A2
A1
+5 Vdc
A7
A5
A4
A3
A6
Data Out'"
-CAS
GND

.
*

*16K by 1 and 64K by 1 bit modules have 16 pins.
**Data In and Data Out are tied together (three-state bus).
**'Data In and Data Out are tied together on Data Bits 0-7 (three-state bus).

Memory Module Pin Configuration

Memory Expansion Options

1-199

Switch-Configurable Start Address
Each card has a small DIP module, that contains eight switches.
The switches are used to set the card start address as follows:
Number
1
2
3
4
5
6
7
8

32K and 64K Options
ON: A 19=0; OFF:
ON: A18=0; OFF:
ON: A 17=0; OFF:
ON: A 16=0; OFF:
ON: A 15=0; OFF:
Not used
Not used
Used only in 64K

A 19=1
A18=1
A 17=1
A 16=1
A 15=1 *

RAM Card*

64/256K Options
ON:A19=0; OFF:A19=1
ON: A18=0; OFF: A18=1
ON: A17=0; OFF: A17=1
ON: A16=0; OFF: A16=1
ON: Select 64K
ON Select 128K
ON: Select 192K
ON: Select 256K

*Switch 8 may be set on the 64K memory expansion option to use only half the
memory on the card (that is, 32K). If switch 8 is on, all 64K is accessible. If
switch 8 is off, address bit A 15 (as set by switch 5) is used to determine which
32K are accessible, and the 64K option behaves as a 32K option.

DIP Module Start Address

Memory Option Switch Settings
Switch settings for all memory expansion options are located in
"Appendix G: Switch Settings."

1-200

Memory Expansion Options

The following method can be used to determine the switch settings for the 32K
memory expansion option.
Starting Address = xxxK
=Decimal value
32K

IxxxK

Convert decimal value to binary
Bit ....... .4
Bit value ... 16

3
8

2
4

2

0
1

Switch

I;' , ,. )0001
bit

.....- - - - 0
.....- - - - - - 2 (off = logical 1)

L..-------3
L.-._ _ _ _ _ _ _ 4

The following method can be used to determine the switch settings for the 64K
memory expansion option.
Starting Address = xxxK
=Decimal value
64K

IxxxK

Convert decimal value to binary
Bit ........ 3
Bit value ... 8

2
4

1
2

0
1

Switch

bit

'------0
' - - - - - - - - - 2 (off = logical 1)

L.-._ _ _ _ _ _ _

3

Memory Expansion Options

1-201

The following method can be used to determine the switch settings for the
64/256K memory expansion option.
Starting Address = xxxK
=Decimal value
64K

/xxxK

Convert decimal value to binary
Bit ........ 3
Bit value ... 8

2
4

1
2

0
1

Switch

Amount of memory
installed on option
~--256K

' - - - - - 192K (on = logical 1)
~----128K

64K
bit

'-------0
L..._ _ _ _ _ _ _

2 (off = logical 1)

~-------3

1-202

Memory Expansion Options

IBM Game Control Adapter

The game control adapter allows up to four paddles or two joy
sticks to be attached to the system. This card fits into one of the
system board's or expansion board's expansion slots. The game
control interface cable attaches to the rear of the adapter. In
addition, four inputs for switches are provided. Paddle and joy
stick positions are determined by changing resistive values sent to
the adapter. The adapter plus system software converts the
present resistive value to a relative paddle or joy stick position.
On receipt of an output signal, four timing circuits are started. By
determining the time required for the circuit to time-out (a
function of the resistance), the paddle position can be determined.
This adapter could be used as a general purpose I/O card with
four analog (resistive) inputs plus four digital input points.
A9-A o

10

'\/

AEN

..

I

..

Instruction
Decode

r

10W
10R

-..

....
..

-

r

f4....

Data Bus
Buffer/
Driver

8

•

A

Resistive Input

K....

I

4

r---

Typical Frequency
833 Hz

07-00
A

Convert
Resistance
Digital
Pulse

A

K.

4

V'r-...

'

...

Digital Inputs

I

4

Game Control Adapter Block Diagram

Game Control Adapter

1-203

Functional Description
Address Decode
The select on the game control adapter is generated by two
74LS138s as an address decoder. AEN must be inactive while
the address is hex 201 in order to generate the select. The select
allows a write to fire the one-shots or read to give the values of the
trigger buttons and one-shot outputs.

Data Bus Buffer/Driver
The data bus is buffered by a 74LS244 buffer/driver. For an In
from address hex 201, the game control adapter will drive the data
bus; at all other times, the buffer is left in the high impedance
state.

Trigger Buttons
The trigger button inputs are read by an In from address hex 201.
A trigger button is on each joy stick or paddle. These values are
seen on data bits 7 through 4. These buttons default to an open
state and are read as 1. When a button is pressed, it is read as O.
Software should be aware that these buttons are not debounced in
hardware.

Joy Stick Positions
The joy stick position is indicated by a potentiometer for each
coordinate. Each potentiometer has a range from 0 to 100 k-ohms
that varies the time constant for each of the four one-shots. As this
time constant is set at different values, the output of the one-shot
will be of varying durations.
All four one-shots are fired at once by an Out to address hex 201.
All four one-shot outputs will go true after the fire pulse and will
remain high for varying times depending on where each
potentiometer is set.
These four one-shot outputs are read by an In from address hex
201 and are seen on data bits 3 through O.
1-204

Game Control Adapter

I/O Channel Description
A9-AO:

Address lines 9 through 0 are used
to address the game control adapter.

D7-DO:

Data lines 7 through 0 are the data
bus.

IOR,IOW:

I/O read and I/O write are used
when reading from or writing to an
adapter (In, Out).

AEN:

When active, the adapter must be
inactive and the data bus driver
inactive.

+5 Vdc:

Power for the game control adapter.

GND:

Common ground.

AI9-AlO:

Unused.

MEMR,MEMW:

Unused.

DACKO-DACK3:

Unused.

IRQ7-IRQ2:

Unused.

DRQ3-DRQ1:

Unused.

ALE, TIC:

Unused.

CLK,OSC:

Unused.

I/O CHCK:

Unused.

I/O CHRDY:

Unused.

RESETDRV:

Unused.

-5 Vdc,

+ 12 Vdc, -12 Vdc:

Unused.

Game Control Adapter

1-205

Interface Description
The game control adapter has eight input lines, four of which are
digital inputs and 4 of which are resistive inputs. The inputs are
read with one In from address hex 201.
The four digital inputs each have a 1 k-ohm pullup resistor to
+5 Vdc. With no drives on these inputs, a 1 is read. For a 0
reading, the inputs must be pulled to ground.
The four resistive pullups, measured to +5 Vdc, will be converted
to a digital pulse with a duration proportional to the resistive load,
according to the following equation:
Time = 24.2 fLsec

+ 0.011 (r) fLsec

The user must first begin the conversation by an Out to address
hex 201. An In from address hex 201 will show the digital pulse
go high and remain high for the duration according to the
resistance value. All four bits (bit 3-bit 0) function in the same
manner; their digital pulse will all go high simultaneously and will
reset independently according to the input resistance value.
Bit 7

Bit 6

I

Bit 5

I

Bit 4

Bit 3

Bit 2

Digital Inputs

I

Bit 1

I

Bit

a

Resistive Inputs

The typical input to the game control adapter is a set of joy sticks
or game paddles.
The joy sticks will typically be a set of two (A and B). These will
have one or two buttons each with two variable resistances each,
with a range from 0 to 100 k-ohms. One variable resistance will
indicate the X-coordinate and the other variable resistance will
indicate the Y-coordinate. This should be attached to give the
following input data:
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

B-#2
B-#1
A-#2
A-#1
B-Y
Button Button Button Button Coordinate

1-206

Game Control Adapter

a

Bit 2

Bit 1

Bit

B-X
Coordinate

A-Y
Coordinate

A-X
Coordinate

The game paddles will have a set of two (A and B) or four (A, B,
C, and D) paddles. These will have one button each and one
variable resistance each, with a range of a to 100 k-ohms. This
should be attached to give the following input data:
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

D

C

B

A

D

Button Button Button Button Coordinate

Bit 2

Bit 1

Bit 0

C

B

A

Coordinate

Coordinate

Coordinate

Refer to "Joy Stick Schematic Diagram" for attaching game
controllers.
15-Pin Male D-Shell
Connector

Joy Sticl< B

,----

--- --- -

I

-- ----, ,
....

----,
/-

Joy Stick A

r---------------.
X-Coordinate

I 9

X-Coordinate

J r-Button

I.

J
,

V -Coordinate
I
I
I
I

,
I

L _____________ JI

112

5

I.

6

1 13

'.

114

I

I.

115
\

'--

•
•
7

•
8

•

V -Coordinate

,I
,
I
IL _____________ .J

-----"."

Note: Potentiometer for X- and V-Coordinates has a range of 0
to 100 k-ohms. Button is normally open; closed when
pressed.

Joy Stick Schematic Diagram

Game Control Adapter

1-207

Rear Panel
15-Pin D-Shell
Connector

o
9

•
5

o

At Standard TTL Levels
Voltage

External
Devices

+5Vdc

1

Button 4

2

Position 0

3

Ground

4

Ground

5

Position 1

6

Button 5

7

+5Vdc

8
9

+5Vdc
Button 6

10

Position 2

11

Ground

12

Position 3

13

Button 7

14

+5Vdc

15

Connector Specifications

1-208

Adapter
Pin No.

Game Control Adapter

Game Co ntrol
Adapter

IBM Prototype Card

The prototype card is 4.2 inches (106.7 millimeters) high by 13.2
inches (335.3 millimeters) long and plugs into an expansion unit
or system unit expansion slot. All system control signals and
voltage requirements are provided through a 2 by 31 position
card-edge tab.
The card contains a voltage bus (+ 5 Vdc) and a ground bus (0
Vdc). Each bus borders the card, with the voltage bus on the back
(pin side) and the ground bus on the front (component side). A
system interface design is also provided on the prototype card.
The prototype card can also accommodate a D-shell connector if
it is needed. The connector size can range from a 9 to a 37
position connector.
Note: Install all components on the component side of the
prototype card. The total width of the card including components
should not exceed 0.500 inch (12.7 millimeters). If these
specifications are not met, components on the prototype card may
touch other cards plugged into adjacent slots.

Prototype Card

1-209

8

Bit 0-7 Data Bus

Data Bus

Bus Direction

Buffer
Transceiver

E1
E3
8 E4
~---I-J E6

1/0 ReadlWrite
Memory ReadlWrite
Spare-E18
Buffered
Address
lines

Address Bit 0
Address Bit 2

Address Bit 3
Address Bit 9

E2
Address
Buffer

Address Enable

E5

6
1---1------11/0 Address ~a-~ E11
~+-----fDecode Logic

-1/0 Decode
(Hex 300 - 31 F Inclusive)

Prototype Card Block Diagram

1-210

Prototype Card

l

Buffered
Data Bus E1 0

I/O Channel Interface
The prototype card has two layers screened onto it (one on the
front and one on the back). It also has 3,909 plated through-holes
that are 0.040 inch (10.1 millimeters) in size and have a 0.060
inch (1.52 millimeters) pad, which is located on a 0.10 inch (2.54
millimeters) grid. There are 37 plated through-holes that are
0.048 inch (1.22 millimeters) in size. These holes are located at
the rear of the card (viewed as if installed in the machine). These
37 holes are used for a 9 to 37 position D-shell connector. The
card also has 5 holes that are 0.125 inch (3.18 millimeters) in
size. One hold is located just above the two rows of D-shell
connector holes, and the other four are located in the corners of
the board (one in each corner).

Prototype Card Layout
The component side has the ground bus [0.05 inch (1.27
millimeters) wide] screened on it and card-edge tabs that are
labeled Al through A31.

2~l
D-Shell Connector
Pin Positions

!

Card-Edge Tabs

Hole for Option
Retaining Bracket

Component Side

Prototype Card

1-211

The component side also has a silk screen printed on it that is
used as a component guide for the I/O interface.

Component Side

The pin side has a +5 Vdc bus [0.05 inch (1.27 millimeters)
wide] screened onto it and card-edge tabs that are labeled B 1
through B31.
Hole for Option
Retaining Bracket

+5 Vdc Bus

D-Shell Connector
Pin Positions
Hole for Option
Retaining Bracket

Pin Side

1-212

Prototype Card

Card-Edge Tabs

Each card-edged tab is connected to a plated through-hole by a
0.012-inch (0.3-millimeter) land. There are three ground tabs
connected to the ground bus by three 0.0 12-inch (0.3 millimeter)
lands. Also, there are two +5 Vdc tabs connected to the voltage
bus by two 0.012-inch (0.3 millimeter) lands.
For additional interfacing information, refer to "I/O Channel
Description" and "I/O Channel Diagram" in this manual. Also,
the "Prototype Card Interface Logic Diagram" is in Appendix D
of this manual. If the recommended interface logic is used, the list
of TTL type numbers listed below will help you select the
necessary components.
Component

TTL Number

Description

U1

74LS245

U2,U5

74LS244

Octal Buffers Line Driver/Line Receivers

U4

74LS04

Hex Inverters

U3

74LS08

Quadruple 2 - Input
Positive - AND Gate

U6

74LS02

Quadruple 2 - Input
Positive - NOR Gate

U7

74LS21

Dual 4 - Input
Positive - AND Gate

Octal Bus Transceiver

C1

10.0 /iF Tantalum Capacitor

C2,C3,C4

0.047 /iF Ceramic Capacitor

System Loading and Power Limitations
Because of the number of options that may be installed in the
system, the I/O bus loading should be limited to one Schottky
TTL load. If the interface circuitry on the card is used, then this
requirement is met.
Refer to the power supply information in this manual for the
power limitations to be observed.

Prototype Card

1-213

Prototype Card External Interface
If a connector is required for the card function, then you should
purchase one of the recommended connectors (manufactured by
Amp) or equivalent listed below:
Connector Size
9-pin
9-pin
15-pin
15-pin
25-pin
25-pin
37-pin
37-pin

D-shell
D-shell
D-shell
D-shell
D-shell
D-shell
D-shell
D-shell

(Male)
(Female)
(Male)
(Female)
(Male)
(Female)
(Male)
(Female)

Part Number (Amp)
205865-1
205866-1
205867-1
205868-1
205857-1
205858-1
205859-1
205860-1

The following example shows a 15-pin, D-shell, female connector
attached to a prototype card.

Option Retaining
Bracket

---

8

---

~
•
•• ••
• •
• ••
• •
• •
~
0

9

15

15-Pin D-Shell
Female
Connector

Component Side

1-214

Prototype Card

IBM Asynchronous
Communications Adapter

The asynchronous communications adapter system control signals
and voltage requirements are provided through a 2 by 31 position
card edge tab. Two jumper modules are provided on the adapter.
One jumper module selects either RS-232C or current-loop
operation. The other jumper module selects one of two addresses
for the adapter, so two adapters may be used in one system.
The adapter is fully programmable and supports asynchronous
communications only. It will add and remove start bits, stop bits,
and parity bits. A programmable baud rate generator allows
operation from 50 baud to 9600 baud. Five, six, seven or eight bit
characters with 1, 1-1/2, or 2 stop bits are supported. A fully
prioritized interrupt system controls transmit, receive, error, line
status and data set interrupts. Diagnostic capabilities provide
loopback functions of transmit/receive and input/output signals.
The heart of the adapter is a INS8250 LSI chip or functional
equivalent. Features in addition to those listed above are:
•

Full double buffering eliminates need for precise
synchronization.

•

Independent receiver clock input.

•

Modem control functions: clear to send (CTS), request to
send (RTS), data set ready (DSR), data terminal ready
(DTR), ring indicator (RI), and carrier detect.

•

False-start bit detection.

•

Line-break generation and detection.

All communications protocol is a function of the system
microcode and must be loaded before the adapter is operational.
All pacing of the interface and control signal status must be
handled by the system software. The following figure is a block
diagram of the asynchronous communications adapter.
Asynchronous Adapter

1-215

Address Bus

Chip
Select

Address
Decode
Data Bus
Interrupt

8250

4 - - - - - - - . . . : . - - - - - - - 1 Asynchronous
Communications

t - - - - . ! Element

A

25-Pin D-Shell
Connector

Asynchronous Communications Adapter Block Diagram

Modes of Operation
The different modes of operation are selected by programming the
8250 asynchronous communications element. This is done by
selecting the I/O address (hex 3F8 to 3FF primary, and hex 2F8
to 2FF secondary) and writing data out to the card_ Address bits
AO, AI, and A2 select the different registers that define the modes
of operation_ Also, the divisor latch access bit (bit 7) of the line
control register is used to select certain registers_

1-216

Asynchronous Adapter

1/0 Decode (in Hex)
Primary
Alternate
Adapter
Adapter

TX Buffer
RX Buffer
Divisor Latch LSB
Divisor Latch MSB
Interrupt Enable Register
Interrupt Identification Registers
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register

2F8
2F8
2F8
2F9
2F9
3FA
2FB
2FC
2FD
2FE

3F8
3F8
3F8
3F9
3F9
3FA
3FB
3FC
3FD
3FE

DLAB State

Register Selected

DLAB=O (Write)
DLAB=O (Read)
DLAB=1
DLAB=1

I/O Decodes

Hex Address 3FB to 3FF and 2FB to 2FF
A9

AS

A7

A6

1

1/0

1

1

AS A4
1

1

DLAB

Register

0

0

Receive Buffer (read),
Transmit
Holding Reg. (write)

0

1

0

Interrupt Enable

0

1

0

x

Interrupt Identification

0

1

1

x

Line Control

1

0

0

x

Modem Control

1

0

1

x

Line Status

1

1

0

x

Modem Status

1

1

1

x

None

0

0

0

1

Divisor Latch (LSB)

0

0

1

1

Divisor Latch (MSB)

A3 A2
1

A1

AO

x

x

x

0

0

0

Note: Bit 8 will be logical 1 for the adapter designated as primary or a logical 0 for
the adapter designated as alternate (as defined by the address jumper
module on the adapter).
A2, A1 and AO bits are "don't cares" and are used to select the different
register of the communications chip.

Address Bits

Asynchronous Adapter

1-217

Interrupts
One interrupt line is provided to the system. This interrupt is
IRQ4 for a primary adapter or IRQ 3 for an alternate adapter, and
is positive active. To allow the communications card to send
interrupts to the system, bit 3 of the modem control register must
be set to 1 (high). At this point, any interrupts allowed by the
interrupt enable register will cause an interrupt.
The data format will be as follows:
DO

Transmit
Data Marking

D1

02

D7

Start
Bit

Data bit 0 is the first bit to be transmitted or received. The
adapter automatically inserts the start bit, the correct parity bit if
programmed to do so, and the stop bit (1, 1-1/2, or 2 depending
on the command in the line-control register).

Interface Description
The communications adapter provides an EIA RS-232C-like
interface. One 25-pin D-shell, male type connector is provided to
attach various peripheral devices. In addition, a current loop
interface is also located in this same connector. A jumper block is
provided to manually select either the voltage interface, or the
current loop interface.
The current loop interface is provided to attach certain printers
provided by IBM that use this particular type of interface.
Pin
Pin
Pin
Pin

18 + receive current loop data
25 - receive current loop return
9 + transmit current loop return
11 - transmit current loop data

1-218

Asynchronous Adapter

t

+5Vdc

I

Transmit Circuit

I

49.9 QIom

~A,!~_m________-.. Pin 9

Tx Data----~vvv-

.. Pin 11

+5 Vdc

I

Receive Circuit

5.6 k·Ohm
OPTO Isolator

Pin 18 ....- - t -...

Pin 25

.-X)---

Rx Data

+---+-...1
+5Vdc

Current Loop Interface

The voltage interface is a serial interface. It supports certain data
and control signals, as listed below.
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 20
Pin 22

Transmitted Data
Received Data
Request to Send
Clear to Send
Data Set Ready
Signal Ground
Carrier Detect
Data Terminal Ready
Ring Indicator

The adapter converts these signals to/from TTL levels to EIA
voltage levels. These signals are sampled or generated by the
communications control chip. These signals can then be sensed by
the system software to determine the state of the interface or
peripheral device.

Asynchronous Adapter

1-219

Voltage Interchange Information
Binary State

Signal Condition

Interface
Control Function

Positive Voltage =

Binary (0)

= Spacing

=On

Negative Voltage =

Binary (1)

= Marking

=Off

Interchange Voltage

Invalid Levels
+15Vdc _ _ _ _ _ _ _ _ _ _ _ _ _
On Function
+3Vdc _ _ _ _ _ _ _ _ _ _ _ _ _
OVdc

Invalid Levels
-3Vdc _ _ _ _ _ _ _ _ _ _ _ _ _
Off Function
-15Vdc _ _ _ _ _ _ _ _ _ _ _ _
Invalid Levels

The signal will be considered in the "marking" condition when the
voltage on the interchange circuit, measured at the interface point,
is more negative than - 3 Vdc with respect to signal ground. The
signal will be considered in the "spacing" condition when the
voltage is more positive than +3 Vdc with respect to signal
ground. The region between +3 Vdc and -3 Vdc is defined as the
transition region, and considered an invalid level. The voltage that
is more negative than -15 Vdc or more positive than + 15 Vdc
will also be considered an invalid level.
During the transmission of data, the "marking" condition will be
used to denote the binary state" 1" and "spacing" condition will
be used to denote the binary state "0."
For interface control circuits, the function is "on" when the
voltage is more positive than +3 Vdc with respect to signal ground
and is "off" when the voltage is more negative than -3 Vdc with
respect to signal ground.

1- 220

Asynchronous Adapter

INS8250 Functional Pin Description
The following describes the function of all INS8250 input/output
pins. Some of these descriptions reference internal circuits.
Note: In the following descriptions, a low represents a logical 0
(0 Vdc nominal) and a high represents a logical 1 (+ 2.4 Vdc
nominal).

Input Signals
Chip Select (CSO, CSl, CS2), Pins 12-14: When CSO and
CSI are high and CS2 is low, the chip is selected. Chip selection
is complete when the decoded chip select signal is latched with an
active (low) address strobe (ADS) input. This enables
communications between the INS8250 and the processor.
Data Input Strobe (DISTR, DISTR) Pins 22 and 21: When
DISTR is high or DISTR is low while the chip is selected, allows
the processor to read status information or data from a selected
register of the INS8250.
Note: Only an active DISTR or DISTR input is required to
transfer data from the INS8250 during a read operation.
Therefore, tie either the DISTR input permanently low or the
DISTR input permanently high, if not used.
Data Output Strobe (DOSTR, DOSTR), Pins 19 and
18: When DOSTR is high or DOSTR is low while the chip is
selected, allows the processor to write data or control words into a
selected register of the INS8250.
Note: Only an active DOSTR or DOSTR input is required to
transfer data to the INS8250 during a write operation. Therefore,
tie either the DOSTR input permanently low or the DOSTR input
permanently high, if not used.
Address Strobe (ADS), Pin 25: When low, provides latching
for the register select (AO, AI, A2) and chip select (CSO, CSI,
CS2) signals.

Asynchronous Adapter

1-221

Note: An active ADS input is required when the register select
(AO, AI, A2) signals are not stable for the duration of a read or
write operation. If not required, tie the ADS input permanently
low.
Register Select (AO, AI, A2), Pins 26-28: These three inputs
are used during a read or write operation to select an INS8250
register to read from or write to as indicated in the table below.
Note that the state of the divisor latch access bit (DLAB), which
is the most significant bit of the line control register, affects the
selection of certain INS8250 registers. The DLAB must be set
high by the system software to access the baud generator divisor
latches.
A2

A1

AO

Register

a

a

a

a

Receiver Buffer (Read), Transmitter
Holding Register (Write)

a

a

1

Interrupt Enable

1

a

Interrupt Identification (Read Only)

X

a
a
a

1

1

Li ne Control

X

1

Modem Control

1

a
a

a

X

1

Line Status

X

1

1

a

Modem Status

X

1

1

1

None

1

a
a

a
a

a

Divisor Latch (Least Significant Bit)

1

Divisor Latch (Most Significant Bit)

DLAB

X

1

Master Reset (MR), Pin 35: When high, clears all the registers
(except the receiver buffer, transmitter holding, and divisor
latches), and the control logic of the INS8250. Also, the state of
various output signals (SOUT, INTRPT, OUT 1, OUT 2, RTS,
DTR) are affected by an active MR input. Refer to the
"Asynchronous Communications Reset Functions" table.
Receiver Clock (RCLK), Pin 9: This input is the 16 x baud
rate clock for the receiver section of the chip.
Serial Input (SIN), Pin 10: Serial data input from the
communications link (peripheral device, modem, or data set).

1-222

Asynchronous Adapter

Clear to Send (CTS), Pin 36: The CTS signal is a modem
control function input whose condition can be tested by the
processor by reading bit 4 (CTS) of the modem status register. Bit
o (DCTS) of the modem status register indicates whether the CTS
input has changed state since the previous reading of the modem
status register.
Note: Whenever the CTS bit of the modem status register
changes state, an interrupt is generated if the modem status
interrupt is enabled.
Data Set Ready (DSR), Pin 37: When low, indicates that the
modem or data set is ready to establish the communications
link and transfer data with the INS8250. The DSR signal is a
modem-control function input whose condition can be tested by
the processor by reading bit 5 (DSR) of the modem status register.
Bit 1 (DDSR) of the modem status register indicates whether the
DSR input has changed since the previous reading of the modem
status register.
Note: Whenever the DSR bit ofthe modem status register
changes state, an interrupt is generated if the modem status
interrupt is enabled.
Received Line Signal Detect (RLSD), Pin 38: When low,
indicates that the data carrier had been detected by the modem or
data set. The RLSD signal is a modem-control function input
whose condition can be tested by the processor by reading bit 7
(RLSD) of the modem status register. Bit 3 (DRLSD) of the
modem status register indicates whether the RLSD input has
changed state since the previous reading of the modem status
register.
Note: Whenever the RLSD bit of the modem status register
changes state, an interrupt is generated if the modem status
interrupt is enabled.

Asynchronous Adapter

1-223

Ring Indicator (RI), Pin 39: When low, indicates that a
telephone ringing signal has been received by the modem or data
set. The RI signal is a modem-control function input whose
conditon can be tested by the processor by reading bit 6 (RI) of
the modem status register. Bit 2 (TERI) of the modem status
register indicates whether the RI input has changed from a low to
high state since the previous reading of the modem status register.
Note: Whenever the RI bit of the modem status register changes
from a high to a low state, an interrupt is generated if the modem
status register interrupt is enabled.
VCC, Pin 40: +5 Vdc supply.
VSS, Pin 20: Ground (0 Vdc) reference.

Output Signals
Data Terminal Ready (DTR), Pin 33: When low, informs the
modem or data set that the INS8250 is ready to communicate.
The DTR output signal can be set to an active low by
programming bit 0 (DTR) of the modem control register to a high
level. The DTR signal is set high upon a master reset operation.
Request to Send (RTS), Pin 32: When low, informs the modem
or data set that the INS8250 is ready to transmit data. The RTS
output signal can be set to an active low by programming bit 1
(RTS) of the modem control register. The RTS signal is set high
upon a master reset operation.
Output 1 (OUT 1), Pin 34: User-designated output that can be
set to an active low by programming bit 2 (OUT 1) of the modem
control register to a high level. The OUT 1 signal is set high upon
a master reset operation.
Output 2 (OUT 2), Pin 31: User-designated output that can be
set to an active low by programming bit 3 (OUT 2) of the modem
control register to a high level. The OUT 2 signal is set high upon
a master reset operation.

1-224

Asynchronous Adapter

Chip Select Out (CSOUT), Pin 24: When high, indicates that
the chip has been selected by active CSO, CSl, and CS2 inputs.
No data transfer can be initiated until the CSOUT signal is a
logical 1.
Driver Disable (DDIS), Pin 23: Goes low whenever the
processor is reading data from the INS8250. A high-level DDIS
output can be used to disable an external transceiver (if used
between the processor and INS8250 on the D7-DO data bus) at
all times, except when the processor is reading data.
Baud Out (BAUDOUT), Pin 15: 16 x clock signal for the
transmitter section of the INS8250. The clock rate is equal to the
main reference oscillator frequency divided by the specified
divisor in the baud generator divisor latches. The BAUDOUT
may also be used for the receiver section by typing this output to
the RCLK input of the chip.
Interrupt (INTRPT), Pin 30: Goes high whenever anyone of
the following interrupt types has an active high condition and is
enabled through the IER: receiver error flag, received data
available, transmitter holding register empty, or modem status.
The INTRPT signal is reset low upon the appropriate interrupt
service or a master reset operation.
Serial Output (SOUT), Pin 11: Composite serial data output to
the communications link (peripheral, modem, or data set). The
SOUT signal is set to the marking (logical 1) state upon a master
reset operation.

Input/Output Signals
Data Bus (D7-DO), Pins 1-8: This bus comprises eight tri-state
input/output lines. The bus provides bidirectional communications
between the INS8250 and the processor. Data, control words,
and status information are transferred through the D7-DO data
bus.
External Clock Input/Output (XTALl, XTAL2), Pins 16 and
17: These two pins connect the main timing reference (crystal or
signal clock) to the INS8250.

Asynchronous Adapter

1-225

Programming Considerations
The INS8250 has a number of accessible registers. The system
programmer may access or control any of the INS8250 registers
through the processor. These registers are used to control
INS8250 operations and to transmit and receive data. A table
listing and description of the accessible registers follows.
RegisterISignal

Reset Control

Reset State

Interrupt Enable Register

Master Reset

All Bits Low (0-3 Forced and
4-7 Perma nent)

Interrupt Identification
Register

Master Reset

Bit 0 is High, Bits 1 and 2 Low
Bits 3- 7 are Permanently Low

Line Control Register

Master Reset

All Bits Low

Modem Control Register

Master Reset

All Bits Low

Line Status Register

Master Reset

Except Bits 5 and 6 are High

Modem Status Register

Master Reset

Bits 0-3 Low
Bits 4- 7 - Input Signal

SOUT

Master Reset

High

INTRPT (RCVR Errors)

Read LSR/MR

Low

INTRPT (RCVR Data Ready)

Read RBR/MR

Low

INTRPT (RCVR Data Ready)

Read IIRI
Write THR/MR

Low

INTRPT (Modem Status
Changes)

Read MSR/MR

Low

OUT2

Master Reset

High

RTS

Master Reset

High

DTR

Master Reset

High

OUT 1

Master Reset

High

Asynchronous Communications Reset Functions

1-226

Asynchronous Adapter

Line-Control Register
The system programmer specifies the format of the asynchronous
data communications exchange through the line-control register.
In addition to controlling the format, the programmer may retrieve
the contents of the line-control register for inspection. This feature
simplifies system programming and eliminates the need for
separate storage in system memory of the line characteristics. The
contents of the line-control register are indicated and described
below.
B~

7

6

5

4

3

2

1

II

I:
0

L...-_ _ _ _.....

'----------l~
L...-_ _ _ _ _ _ _.....
L...-_ _ _ _ _ _ _ _ _

~

Woed L,""h 5,1,,, BI, 0 IWL501
Word Length Select Bit 1 (WLS1)
Number of Stop Bits (STB)
Parity Enable (PEN)
Even Parity Select (EPS)
Stick Parity
Set Break

' - - - - - - - - - - - - - Divisor Latch Access Bit (DLAB)

Line-Control Register (LCR)

Bits 0 and 1: These two bits specify the number of bits in each
transmitted or received serial character. The encoding of bits 0
and 1 is as follows:
Bit 1

BitO

0
0

0

1
1

0

1
1

Word Length
5
6
7
8

Bits
Bits
Bits
Bits

Asynchronous Adapter

1-227

Bit 2: This bit specifies the number of stop bits in each
transmitted or received serial character. If bit 2 is a logical 0, one
stop bit is generated or checked in the transmit or receive data,
respectively. If bit 2 is logical 1 when a 5-bit word length is
selected through bits 0 and I, 1-1/2 stop bits are generated or
checked. If bit 2 is logical 1 when either a 6-, 7-, or 8-bit word
length is selected, two stop bits are generated or checked.
Bit 3: This bit is the parity enable bit. When bit 3 is a logical 1,
a parity bit is generated (transmit data) or checked (receive data)
between the last data word bit and stop bit of the serial data. (The
parity bit is used to produce an even or odd number of 1 's when
the data word bits and the parity bit are summed.)
Bit 4: This bit is the even parity select bit. When bit 3 is a
logical 1 and bit 4 is a logical 0, an odd number of logical 1's is
transmitted or checked in the data word bits and parity bit. When
bit 3 is a logical 1 and bit 4 is a logical 1, an even number of bits
is transmitted or checked.
Bit 5: This bit is the stick parity bit. When bit 3 is a logical 1
and bit 5 is a logical 1, the parity bit is transmitted and then
detected by the receiver as a logical 0 if bit 4 is a logical 1, or as a
logical 1 if bit 4 is a logical O.
Bit 6: This bit is the set break control bit. When bit 6 is a logical
1, the serial output (SOUT) is forced to the spacing (logical 0)
state and remains there regardless of other transmitter activity.
The set break is disabled by setting bit 6 to a logical O. This
feature enables the processor to alert a terminal in a computer
communications system.
Bit 7: This bit is the divisor latch access bit (DLAB). It must be
set high (logical 1) to access the divisor latches of the baud rate
generator during a read or write operation. It must be set low
(logical 0) to access the receiver buffer, the transmitter holding
register, or the interrupt enable register.

1-228

Asynchronous Adapter

Programmable Baud Rate Generator
The INS8250 contains a programmable baud rate generator that
is capable of taking the clock input (1.8432 MHz) and dividing it
by any divisor from 1 to (2 16-1). The output frequency of the
baud generator is 16 x the baud rate [divisor # = (frequency
input)/(baud rate x 16)]. Two 8-bit latches store the divisor in a
16-bit binary format. These divisor latches must be loaded during
initialization in order to ensure desired operation of the baud rate
generator. Upon loading either of the divisor latches, a 16-bit
baud counter is immediately loaded. This prevents long counts on
initial load.

Hex Address 3F8 DLAB = 1
Bit

7

6

5

4

3

2

I

1_:

o

IL--=:

1..-_ _ _ _ _ _ _ _

L -_ _ _ _ _ _ _ _

~

B;10
Bit1
Bit 2
Bit 3
Bit 4

1..-_ _ _ _ _ _ _ _ _ _. . .

Bit 5

'--------------~

Bit 6
Bit 7

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _

~

Divisor Latch Least Significant Bit (DLL)

Asynchronous Adapter

1·229

Hex Address 3F9 DLAB
Bit

7

6

=

5

1
4

3

2

o
Bit 8
Bit 9

1..-_________

Bit 10
Bit 11

1..------------_...

Bit 13

Bit 12
' - - - - - - - - - - - - - - - _ Bit 14
' - - - - - - - - - - - - - - - - - - Bit 15

Divisor Latch Most Significant Bit (DLM)

The following figure illustrates the use of the baud rate generator
with a frequency of 1.8432 MHz. For baud rates of 9600 and
below, the error obtained is minimal.
Note: The maximum operating frequency of the baud generator
is 3.1 MHz. In no case should the data rate be greater than 9600
baud.
Desired
Baud
Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600

Divisor Used
to Generate
16x Clock
(Decimal)
(Hex)
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12

Baud Rate at 1.843 MHz

1-230 Asynchronous Adapter

900
600
417
359
300
180

OCO

Percent Error
Difference Between
Desired and Actual
-

0.026
0.058
-

-

060
040
03A
030
020
018
010

-

OOC

-

-

0.69
-

-

Line Status Register
This 8-bit register provides status information on the processor
concerning the data transfer. The contents of the line status
register are indicated and described below:

Hex Address 3FD
Bit

7

6

5

4

3

2

I I

I:

o

D,," R"dy (DR)
Overrun Error (OR)
Parity Error (PE)

' - - - - - - - - Framing Error (FE)
L.-_ _ _ _ _ _ _ _~ Break Interrupt (BI)
L--_ _ _ _ _ _ _ _ _ _. .

Transmitter Holding
Register Empty
(THRE)

'--------------~

Tx Shift Register
Empty (TSRE)

' - - - - - - - - - - - - - - - -. . =0

Line Status Register (LSR)

Bit 0: This bit is the receiver data ready (DR) indicator. Bit 0 is
set to a logical 1 whenever a complete incoming character has
been received and transferred into the receiver buffer register. Bit
o may be reset to a logical 0 either by the processor reading the
data in the receiver buffer register or by writing a logical 0 into it
from the processor.
Bit 1: This bit is the overrun error (OE) indicator. Bit 1
indicates that data in the reciever buffer register was not read by
the processor before the next character was transferred into the
receiver buffer register, thereby destroying the previous character.
The OE indicator is reset whenever the processor reads the
contents of the line status register.
Bit 2: This bit is the parity error (PE) indicator. Bit 2 indicates
that the received data character does not have the correct even or
odd parity, as selected by the even parity-select bit. The PE bit is
set to a logical 1 upon detection of a parity error and is reset to a
logical 0 whenever the processor reads the contents of the line
status register.
Asynchronous Adapter

1-231

Bit 3: This bit is the framing error (FE) indicator. Bit 3
indicates that the received character did not have a valid stop bit.
Bit 3 is set to a logical 1 whenever the stop bit following the last
data bit or parity is detected as a zero bit (spacing level).
Bit 4: This bit is the break interrupt (BI) indicator. Bit 4 is set to
a logical 1 whenever the received data input is held in the spacing
(logical 0) state for longer than a full word transmission time (that
is, the total time of start bit + data bits + parity +stop bits).
Note: Bits 1 through 4 are the error conditions that produce a
receiver line status interrupt whenever any of the corresponding
conditions are detected.
Bit 5: This bit is the transmitter holding register empty (THRE)
indicator. Bit 5 indicates that the INS8250 is ready to accept a
new character for transmission. In addition, this bit causes the
INS8250 to issue an interrupt to the processor when the transmit
holding register empty interrupt enable is set high. The THRE bit
is set to a logical 1 when a character is transferred from the
transmitter holding register into the transmitter shift register. The
bit is reset to logical 0 concurrently with the loading of the
transmitter holding register by the processor.
Bit 6: This bit is the transmitter shift register empty (TSRE)
indicator. Bit 6 is set to a logical 1 whenever the transmitter shift
register is idle. It is reset to logical 0 upon a data transfer from the
transmitter holding register to the transmitter shift register. Bit 6 is
a read-only bit.
Bit 7:

This bit is permanently set to logical O.

Interrupt Identification Register
The INS8250 has an on-chip interrupt capability that allows for
complete flexibility in interfacing to all the popular
microprocessors presently available. In order to provide minimum
software overhead during data character transfers, the INS8250
prioritizes interrupts into four levels: receiver line status (priority
1), received data ready (priority 2), transmitter holding register
empty (priority 3), and modem status (priority 4).

1-232

Asynchronous Adapter

Information indicating that a prioritized interrupt is pending and
the type of prioritized interrupt is stored in the interrupt
identification register. Refer to the "Interrupt Control
Functions" table. The interrupt identification register (IIR), when
addressed during chip-select time, freezes the highest priority
interrupt pending, and no other interrupts are acknowledged until
that particular interrupt is serviced by the processor. The contents
of the IIR are indicated and described below.

Hex Address 3FA
Bit

7

6

5

o

432

II

I~
\ 0 '""""p""d,,"
If
Interrupt
10 Bit (0)

Interrupt 10 Bit (1 )

=0
'---------- =

'-----------~ =
L--_ _ _ _ _ _ _ _.._. =
L..-_ _ _ _ _ _ _ _ _ _.._. =

0
0
0
0

Interrupt Identification Register (/I R)

Bit 0: This bit can be used in either a hard-wired prioritized or
polled environment to indicate whether an interrupt is pending and
the IIR contents may be used as a pointer to the appropriate
interrupt service routine When bit 0 is a logical 1, no interrupt is
pending and polling (if used) is continued.
Bits 1 and 2: These two bits of the IIR are used to identify the
highest priority interrupt pending as indicated in the "Interrupt
Control Functions" table.
Bits 3 through 7:

These five bits of the IIR are always logical O.

Asynchronous Adapter

1-233

Interrupt 10
Register
Bit 2

Interrupt Set and Reset Functions

Bit 1 BitO

Priority
Level

Interrupt
Type

Interrupt
Source

Interrupt
Reset Control

0

0

1

1

1

0

Highest

Receiver
Line Status

1

0

0

Second

Received
Receiver
Data Available Data Available

Reading the
Receiver Buffer
Register

0

1

0

Third

Transmitter
Holding
Register
Empty

Transmitter
Holding
Register
Empty

Reading the IIR
Register (if
source of
interrupt)
or
Writing into the
Transmitter
Holding Register

0

0

0

Fourth

Modem
Status

Clear to Send
or
Data Set Ready
or
Ring Indicator
or
Received Line
Signal Direct

Reading the
Modem Status
Register

None

Interrupt Control Functions

1-234 Asynchronous Adapter

None
Overrun Error
or
Parity Error
or
Framing Error
or
Break Interrupt

Reading the
Line Status
Register

Interrupt Enable Register
This eight-bit register enables the four types of interrupt of the
INS8250 to separately activate the chip interrupt (INTRPT)
output signal. It is possible to totally disable the interrupt system
by resetting bits 0 through 3 of the interrupt enable register.
Similarly, by setting the appropriate bits of this register to a
logical 1, selected interrupts can be enabled. Disabling the
interrupt system inhibits the interrupt identification register and
the active (high) INTRPT output from the chip. All other system
functions operate in their normal manner, including the setting of
the line status and modem status registers. The contents of the
interrupt enable register are indicated and described below:
Hex Address 3F9 DLAB = 0
Bit

7

6

5

4

3

o

2

I

L: ~
1

'''hi'

D",

Ava ilable Interrupt

1..-___
L..-_ _ _ _~

1 = Enable Tx Holding Register
Empty Interrupt
1 = Enable Receive line
Status Interrupt
1 = Enable Modem Status
Interrupt

1..------- == 00

L..-_ _ _ _ _ _ _. . .

L -_ _ _ _ _ _ _ _ _ =
L..-_ _ _ _ _ _ _ _ _ _ _

0

= 0

Interrupt Enable Register (JERI

Bit 0: This bit enables the received data available interrupt when
set to logical 1.
Bit 1: This bit enables the transmitter holding register empty
interrupt when set to logical 1.
Bit 2: This bit enables the receiver line status interrupt when set
to logical 1.

Asynchronous Adapter

1-235

Bit 3: This bit enables the modem status interrupt when set to
logical 1.
Bits 4 through 7:

These four bits are always logical O.

Modem Control Register
This eight-bit register controls the interface with the modem or
data set (or peripheral device emulating a modem). The contents
of the modem control register are indicated and described below:
Hex Address 3FC
Bit

76543

2

II I

o

L~

D""eem'",' ""dy(DTR(

Request to Send (RTS)

Out 1
Out 2
' - - - - - - - - Loop
L...-_ _ _ _ _ _ _ _ _ =

'---------~ =

0
0

'------------~ =

0

Modem Control Register (MCR)

Bit 0: This bit controls the data terminal ready (DTR) output.
When bit 0 is set to logical 1, the DTR output is forced to a
logical O. When bit 0 is reset to a logical 0, the DTR output is
forced to a logical 1.
Note: The DIR output of the INS8250 may be applied to an
EIA inverting line driver (such as the DS1488) to obtain the
proper polarity input at the succeeding modem or data set.
Bit 1: This bit controls the request to send (RTS) output. Bit 1
affects the RTS output in a manner identical to that described
above for bit O.

1-236

Asynchronous Adapter

Bit 2: This bit controls the output 1 (OUT 1) signal, which is an
auxiliary user-designated output. Bit 2 affects the OUT 1 output
in a manner identical to that described above for bit O.
Bit 3: This bit controls the output 2 (OUT 2) signal, which is an
auxiliary user-designated output. Bit 3 affects the OUT 2 output
in a manner identical to that described above for bit O.
Bit 4: This bit provides a loopback feature for diagnostic testing
of the INS8250. When bit 4 is set to logical 1, the following
occurs: the transmitter serial output (SOUT) is set to the marking
(logical 1) state; the receiver serial input (SIN) is disconnected;
the output of the transmitter shift register is "looped back" into
the receiver shift register input; the four modem control inputs
(CTS, DRS, RLSD, and RI) are disconnected; and the four
modem control outputs (DTR, RTS, OUT I, and OUT 2) are
internally connected to the four modem control inputs. In the
diagnostic mode, data that is transmitted is immediately received.
This feature allows the processor to verify the transmit- and
receive-data paths of the INS8250.
In the diagnostic mode, the receiver and transmitter interrupts are
fully operational. The modem control interrupts are also
operational but the interrupts' sources are now the lower four bits
of the modem control register instead of the four modem control
inputs. The interrupts are still controlled by the interrupt enable
register.
The INS8250 interrupt system can be tested by writing into the
lower four bits of the modem status register. Setting any of these
bits to a logical 1 generates the appropriate interrupt (if enabled).
The resetting of these interrupts is the same as in normal
INS8250 operation. To return to normal operation, the registers
must be reprogrammed for normal operation and then bit 4 of the
modem control register must be reset to logical O.
Bits 5 through 7:

These bits are permanently set to logical O.

Asynchronous Adapter

1-237

Modem Status Register
This eight-bit register provides the current state of the control
lines from the modem (or peripheral device) to the processor. In
addition to this current-state information, four bits of the modem
status register provide change information. These bits are set to a
logical 1 whenever a control input from the modem changes state.
They are reset to logical 0 whenever the processor reads the
modem status register.
The content of the modem status register are indicated and
described below:
Hex Address 3FE
Bit

7

6

5

432

a

I Ii: 0"" c,,,""

S'"d(DCTS,

Delta Data Set Ready (DDSR)

L..-_ _ _ _ _ _

Trailing Edge Ring
Indicator (TERI)
Delta Rx Line Signal
Detect (DRLSD)

' - - - - - - - -... Clear to Send (CTS)
' - - - - - - - - - _ Data Set Ready (DSR)
Ring Indicator (RI)

L..-_ _ _ _ _ _ _ _ _ _

L..-_ _ _ _ _ _ _ _ _ _ _

Receive Line Signal
Detect (RLSD)

Modem Status Register (MSR)

1-238

Asynchronous Adapter

Bit 0: This bit is the delta clear to send (DCTS) indicator. Bit 0
indicates that the CTS input to the chip has changed state since
the last time it was read by the processor.
Bit 1: This bit is the delta data set ready (DDSR) indicator. Bit
1 indicates that the DRS input to the chip has changed since the
last time it was read by the processor.
Bit 2: This bit is the trailing edge of ring indicator (TERI)
detector. Bit 2 indicates that the RI input to the chip has changed
from an on (logical 1) to an off (logical 0) condition.
Bit 3: This bit is the delta received line signal detector
(DRLSD) indicator. Bit 3 indicates that the RLSD input to the
chip has changed state.
Note: Whenever bit 0, 1, 2, or 3 is set to a logical 1, a modem
status interrupt is generated.
Bit 4: This bit is the complement of the clear to send (CTS)
input. If bit 4 (LOOP) of the MCR is set to a logical 1, this is
equivalent to RTS in the MCR.
Bit 5: This bit is the complement of the data set ready (DSR)
input. If bit 4 of the MCR is set to a logical 1, this bit is
equivalent to DTR in the MCR.
Bit 6: This bit is the complement of the ring indicator (RI) input.
If bit 4 of the MCR is set to a logical 1, this bit is equivalent to
OUT 1 in the MCR.
Bit 7: This bit is the complement of the received line signal
detect (RLSD) input. If bit 4 of the MCR is set to a logical 1, this
bit is equivalent to OUT 2 of the MCR.

Asynchronous Adapter

1-239

Receiver Buffer Register
The receiver buffer register contains the received character as
defined below:
Hex Address 3F8
Bit

7

6

DLAB = 0

Read Only

543

o

2

~

I ~
~

Data BitO
DataBitl
Data Bit 2
Data Bit 3

1---------1..-

Data Bit 4

' - - - - - - - - -.... Data Bit 5
' - - - - - - - - - - - - . . . . Data Bit 6

'---------------i..-

Data Bit 7

Receiver Buffer Register (RBR)

Bit 0 is the least significant bit and is the first bit serially received.

1-240

Asynchronous Adapter

Transmitter Holding Register
The transmitter holding register contains the character to be
serially transmitted and is defined below:

Hex Address 3F8
Bit

7

6

DLAB =

5

a

Write Only

432

a

I~
~: ~:~: ::~~
~
Data Bit2

Data Bit 3
Data Bit 4

'------------'~

Data Bit 5

' - - - - - - - - - - - - - Data Bit 6
' - - - - - - - - - - - - - - Data Bit 7

Transmitter Holding Register (THR)

Bit 0 is the least significant bit and is the first bit serially
transmitted.

Asynchronous Adapter

1-241

Selecting the Interface Format and
Adapter Address
The voltage or current loop interface and adapter address are
selected by plugging the programmed shunt modules with the
locator dots up or down. See the figure below for the
configurations.
Module Position
for Primary Asynchronous
Adapter

Module Position
for Alternate Asynchronous
Adapter

D
D

D

o
Asynchronous
Com m u n i ca ti 0 n s L1.U.L.U.J.J..Lu;<'l..U..1.L.U.J.J..LL.1..J.Jc.Lf-L.J..U..u.J
Adapter

Current loop
Interface
Dot Down

1-242

Asynchronous Adapter

Voltage Interface
Dot Up

Rear Panel
25-Pin D-Shell

•

25

•
•
•
•
•
•
•
•
•
•

4

•

o

At Standard RS-232C Levels
(With Exception of Current Loops)
Description

Pin

NC

1

Transmitted Data

2

Received Data

3

Request to Send

4

Clear to Send

5

Data Set Ready

6

Signal Ground

7

Received Line Signal Detector

8

+Transmit Current Loop Data
NC

External
Device

Note:

9
10

-Transmit Current Loop Data

11

NC

12

NC

13

NC

14

NC

15

NC

16

NC

17

+Receive Current Loop Data

18

NC

19

Data Terminal Ready

20

NC

21

Ring Indicator

22

NC

23

NC

24

-Receive Current Loop Return

25

Asynchr onous
Commun ications
Adapter
(RS-232 C)

To avoid inducing voltage surges on interchange circuits. signals from
interchange circuits shall not be used to drive inductive devices. such
as relay coils.

Connector Specifications

Asynchronous Adapter 1-243

Notes:

1- 244 Asynchronous Adapter

Binary Synchronous
Communications Adapter

The binary synchronous communications (BSC) adapter is a
4-inch high by 7 .5-inch wide card that provides an
RS232C-compatible communication interface for the IBM
Personal Computer. All system control, voltage, and data signals
are provided through a 2- by 3 I-position card-edge tab. External
interface is in the form of EIA drivers and receivers connected to
an RS232C, standard 25-pin, D-shell connector.
The adapter is programmed by communication software to
operate in binary synchronous mode. Maximum transmission rate
is 9600 bits per second (bps). The heart of the adapter is an
Intel 825lA Universal Synchronous/Asynchronous
Receiver/Transmitter (USART). An Intel 8255A-5
programmable peripheral interface (PPI) is also used for an
expanded modem interface, and an Intel 8253-5 programmable
interval timer provides time-outs and generates interrupts.
The following is a block diagram of the BSe adapter.

TIMER
EIA
Drivers/
Receivers
-

8253
Syste m
Bus

'
i
I

I

I

I

I

I
I

I

Data
Bus

F:z

rl

'//,

Z

Control

~

I

I I
I I
I
L.J

-

I

~l

I
I
I

"
'//,'///);

BSC Adapter Block Diagram

I

Programmable
Peripheral
Interface
---

I
I

I

I
I

I
I
I
I

I
I

L.J

f---f-- '---

>-=

%

I

USART

i8251A

I

Address ~

Data

Comm unication
Equip ment

8255A5

Bse Adapter

1-245

Functional Description
8251A Universal Synchronous/Asynchronous
Receiver/Transmitter
The 8251A operational characteristics are programmed by the
system unit's software, and it can support virtually any form of
synchronous data technique currently in use. In the configuration
being described, the 8251A is used for IBM's binary synchronous
communications (BSC) protocol in half-duplex mode.
Operation of the 8251 A is started by programming the
communications format, then entering commands to tell the
8251A what operation is to be performed. In addition, the 8251A
can pass device status to the system unit by doing a Status Read
operation. The sequence of events to accomplish this are mode
instruction, command instruction, and status read. Mode
instruction must follow a master reset operation. Commands can
be issued in the data block at any time during operation of the
8251A.
A block diagram of the 8251A follows:

TxD

TxRDY
TxE
TxC

RxD

INTERNAL
DATA BUS

8251A Block Diagram

1-246

BSC Adapter

RxRDY
RxC
SYNDET

Data Bus Buffer
The system unit's data bus interfaces the 8251A through the data
bus buffer. Data is transferred or received by the buffer upon
execution of input or output instructions from the system unit.
Control words, command words, and status information are also
transferred through the data bus buffer.

Read/Write Control Logic
The read/write control logic controls the transfer of information
between the system unit and the 8251A. It consists of pins
designated as RESET, CLK, WR, RD, C/D, and CS.
RESET: The Reset pin is gated by Port B, bit 4 of the 8255,
and performs a master reset of the 8251 A. The minimum reset
pulse width is 6 clock cycles. Clock-cycle duration is determined
by the oscillator speed of the processor.
CLK (Clock): The clock generates internal device timing. No
external inputs or outputs are referenced to CLK. The input is the
system board's bus clock of 4.77 MHz.
WR (Write): An input to WR informs the 8251A that the
system unit is writing data or control words to it. The input is the
WR signal from the system-unit bus.
RD (Read): An input to RD informs the 8251A that the
processing unit is reading data or status information from it. The
input is the RD signal from the system-unit bus.

c/n (Control/Data): An input on this pin, in conjunction with
the WR and RD inputs, informs the 8251A that the word on the
data bus is either a data character, a control word, or status
information. The input is the low-order address bit from the
system board's address bus.
CS (Chip Select): A low on the input selects the 8251A. No
reading or writing will occur unless the device is selected. An
input is decoded at the adapter from the address information on
the system-unit bus.

BSC Adapter

1-247

Modem Control
The 8251A has the following input and output control signals
which are used to interface the transmission equipment selected
by the user.
DSR (Data Set Ready): The DSR input port is a
general-purpose, I-bit, inverting input port. The 8251 A can test
its condition with a Status Read operation.
CTS (Clear to Send): A low on this input enables the 8251 A
to transfer serial data if the TxEnable bit in the command byte is
set to 1. If either a TxEnable off or CTS off condition occurs
while the transmitter is in operation, the transmitter will send all
the data in the USART that was written prior to the TxDisable
command, before shutting down.
DTR (Data Terminal Ready): The DTR output port is a
general-purpose, I-bit, inverting output port. It can be set low by
programming the appropriate bit in the command instruction
word.
RTS (Request to Send): The RTS output signal is a
general-purpose, I-bit, inverting output port. It can be set low by
programming the appropriate bit in the Command Instruction
word.

Transmitter Buffer
The transmitter buffer accepts parallel data from the data-bus
buffer, converts it to a serial bit stream, and inserts the
appropriate characters or bits for the BSC protocol. The output
from the transmit buffer is a composite serial stream of data on the
falling edge of Transmit Clock. The transmitter will begin
transferring data upon being enabled, if CTS = 0 (active). The
transmit data (TxD) line will be set in the marking state upon
receipt of a master reset, or when transmit enable/CTS is off and
the transmitter is empty (TxEmpty).

1-248

BSC Adapter

Transmitter Control
Transmitter Control manages all activities associated with the
transfer of serial data. It accepts and issues the following signals,
both externally and internally, to accomplish this function:
TxRDY (Transmitter Ready): This output signals the system
unit that the transmitter is ready to accept a data character. The
TxRDY output pin is used as an interrupt to the system unit
(Level 4) and is masked by turning off Transmit Enable. TxRDY
is automatically reset by the leading edge of a WR input signal
when a data character is loaded from the system unit.
TxE (Transmitter Empty):
register input.

This signal is used only as a status

TxC (Transmit Clock): The Transmit Clock controls the rate
at which the character is to be transmitted. In synchronous mode,
the bit-per-second rate is equal to the TxC frequency. The falling
edge of TxC shifts the serial data out of the 8251A.

Receiver Buffer
The receiver accepts serial data, converts it to parallel format,
checks for bits or characters that are unique to the communication
technique, and sends an "assembled" character to the system unit.
Serial data input is received on the RxD (Receive Data) pin, and
is clocked in on the rising edge of RxC (Receive Clock).

Receiver Control
This control manages all receiver-related activites. The
parity-toggle and parity-error flip-flop circuits are used for
parity-error detection, and set the corresponding status bit.

BSC Adapter

1-249

RxRDY (Receiver Ready): This output indicates that the
8251A has a character that is ready to be received by the system
unit. RxRDY is connected to the interrupt structure of the system
unit (Interrupt Level 3). With Receive Enable off, RxRDY is
masked and held in the reset mode. To set RxRDY, the receiver
must be enabled, and a character must finish assembly and be
transferred to the data output register. Failure to read the received
character from the RxRDY output register before the assembly of
the next Rx Data character will set an overrun-condition error,
and the previous character will be lost.
RxC (Receiver Clock): The receiver clock controls the rate at
which the character is to be received. The bit rate is equal to the
actual frequency of RxC.
SYNDET (Synchronization Detect): This pin is used for
synchronization detection and may be used as either input or
output, programmable through the control word. It is reset to
output-mode-low upon reset. When used as an output (internal
synchronization mode), the SYNDET pin will go to 1 to indicate
that the 8251A has found the synchronization character in the
receive mode. If the 8251 A is programmed to use double
synchronization characters (bisynchronization, as in this
application), the SYNDET pin will go to 1 in the middle of the
last bit of the second synchronization character. SYNDET is
automatically reset for a Status Read operation.

8255A-5 Programmable Peripheral Interface
The 8255A-5 is used on the BSC adapter to provide an expanded
modem interface and for internal gating and control functions. It
has three 8-bit ports, which are defined by the system during
initialization of the adapter. All levels are considered plus active
unless otherwise indicated. A detailed description of the ports is in
"Programming Considerations" in this section.

1-250

BSC Adapter

8253-5 Programmable Interval Timer
The 8253-5 is driven by a divided-by-two system-clock signal. Its
outputs are used as clocking signals and to generate inactivity
timeout interrupts. These level 4 interrupts occur when either of
the timers reaches its programmed terminal counts. The 8253-5
has the following outputs:
Timer 0:

Not used for synchronous-mode operation.

Timer 1:

Connected to port A, bit 7 of the 8255 and Interrupt
Level 4.

Timer 2:

Connected to port A, bit 6 of the 8255 and Interrupt
Level 4.

Operation
The complete functional definition of the BSC adapter is
programmed by the system software. Initialization and control
words are sent out by the system to initialize the adapter and
program the communications format in which it operates. Once
programmed, the BSC Adapter is ready to perform its
communication functions.

Transmit
In synchronous transmission, the TxD output is continuously at a
mark level until the system sends its first character, which is a
synchronization character to the 8251A. When the CTS line goes
on, the first character is serially transmitted. All bits are shifted
out on the falling edge of TxC. When the 8251A is ready to
receive another character from the system for transmission, it
raises TxRDY, which causes a level-4 interrupt.

BSC Adapter

1-251

Once transmission has started, the data stream at the TxD output
must continue at the TxC rate. If the system does not provide the
8251A with a data character before the 8251A transmit buffers
become empty, the synchronization characters will be
automatically inserted in the TxD data stream. In this case, the
TxE bit in the status register is raised high to signal that the
8251A is empty and that synchronization characters are being
sent out. (Note that this TxE bit is in the status register, and is not
the TxE pin on the 8251A). TxE does not go low when SYNC is
being shifted out. The TxE status bit is internally reset by a data
character being written to the 8251A.

Receive
In synchronous reception, the 8251A will achieve character
synchronization, because the hardware design of the BSC adapter
is intended for internal synchronization. Therefore, the SYNDET
pin on the 8251A is not connected to the adapter circuits. For
internal synchronization, the Enter Hunt command should be
included in the first command instruction word written. Data on
the RxD pin is then sampled in on the rising edge of RxC. The
content of the RxD buffer is compared at every bit boundary with
the first SYNC character until a match occurs. Because the
8251A has been programmed for two synchronization characters
(bisynchronization), the next received character is also compared.
When both SYNC characters have been detected, the 8251A
ends the hunt mode and is in character synchronization. The
SYNDET bit in the status register (not the SYNDET pin) is then
set high, and is reset automatically by a Status Read.
Once synchronization has occurred, the 8251A begins to
assemble received data bytes. When a character is assembled and
ready to be transferred to memory from the 8251A, it raises
RxRDY, causing an interrupt level 3 to the system.
If the system has not fetched a pevious character by the time

another received character is assembled (and an interrupt-level 3
issued by the adapter), the old character will be overwritten, and
the overrun error flag will be raised. All error flags can be reset by
an error reset operation.

1-252

BSC Adapter

Programming Considerations
Before starting data transmission or reception, the BSC adapter
is programmed by the system unit to define control and gating
ports, timer functions and counts, and the communication
environment in which it is to operate.

Typical Programming Sequence
The 8255A-5 programmable peripheral interface (PPI) is
initialized for the proper mode by selecting address hex 3A3 and
writing the control word. This defines port A as an input, port B
as an output for modern control and gating, and port C for 4-bit
input and 4-bit output. The bit descriptions for the 8255A-5 are
shown in the following figures. Using an output to port C, the
adapter is then set to wrap mode, disallow interrupts, and gate
external clocks (address=3A2H, data=ODH). The adapter is
now isolated from the communication interface, and initialization
continues.
Through bit 4 of 8255 Port B, the 8251A reset pin is brought
high, held, then dropped. This resets the internal registers of the
8251A.

BSC Adapter

1-253

Address: hex 3AO for BSe
hex 380 for Alternate BSe

8255 Port A Assignments
Input Port

Bit

7

6543210

I 1_1~_4.~~: Ei~::~n~n~~~:~~~~~Xr~~ ~~::J~~erface

III

I

-

:

0 = Clear-to-Send is on from Interface
Oscillating = Receive Clock Active
1 =TxROY Active
L -_ _ _ _ _ _ _ _ _ _ _ _ 1 = Timer 2 Output Active
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1 = Timer 1 Output Active
L-_ _ _ _ _ _ _ _

Address: hex 3A 1 for BSe
hex 381 for Alternate BSe

8255 Port B Assignments
Output Port

Bit

7

6

5

4

3

I

o

2

I

I ~ 0 ~ T"," "" 0,. """,IR.. '0'0"",

0= Turn on Select Standby
0= Turn on Test
1 = Not Used
1 = Reset 8251A
L.._ _ _ _ _ _ _ _ _ _ _ 1 = Gate Timer 2
L.._ _ _ _ _ _ _ _ _ _ __._ 1 = Gate Timer 1
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ 1 = Gate Timers 1 and 2 to Interrupt Level 4

8255 Port

Bit

7

6

e

Address: hex 3A2 for BSe
hex 382 for Alternate BSe

Assignments

4

3

2

1

0

I L....
I I I __-_:L

.

__

-

L-_ _ _ _ _ _

L _________

L

I -_ _ _ _ _ _ _ _ ___+_
L _ _ _ _ _ _ _ _ _ _ _.....
______________

1 = Gate Internal Clock IOutput Bit)
1 = Gate External Clock IOutput Bit)
1 = Electronic Wrap IOutput Bit)
0 = Enable Timer 1 and 2, Interrupt 6 and
Receive Interrupt 3
Oscillating = Receive Data Iinput Bit)
Oscillating = Timer 0 Output Iinput Bit)
0 = Test Indicate Active IInput Bit)
0 = BSC Adapter

The 8253-5 programmable interval timer is used in the
synchronous mode to provide inactivity time-outs to interrupt the
system unit after a preselected period of time has elapsed from the
start of a communication operation. Counter 0 is not used for
synchronous operation. Counters 1 and 2 are connected to
interrupt-level 4, and are programmed to terminal-count values,
which will provide the desired time delay before a level-4 interrupt
is generated. These interrupts will indicate to the system software
that a predetermined period of time has elapsed without a TxRDY
(level 4) or RxRDY (level 3) interrupt being sent to the system
unit.
1-254

BSC Adapter

The modes for each counter are programmed by selecting each
timer-register address and writing the correct control word for
counter operation to the adapter. The mode for counters 1 and 2 is
set to O. The terminal-count values are loaded using control-word
bits D4 and D5 to select "load." The 8253-5 Control Word
format is shown in the following chart.

Address hex 3A7

Control Word Format
07

06

I SC1 I

sca

03

05

04

RL1

RLOI M21 Ml I MO I BCO\

I I

02

01

DO

Definition of Control
SC - Select Counter:
SCl

SCO

a

0

Select Cou nter

0

1

Select Counter 1

1

a

Select Counter 2

1

1

Illegal

a

RL - Read/Load:
RL1

RLO

0

a

Counter Latching operation

1

a

Read/Load most significant byte only

a

1

Read/Load least significant byte only

1

1

Read/Load least significant byte first,
then most significant byte

M - Mode:
M2
I

Ml

MO

IaIaI

a

Mode

a

I

Terminal Count
Interrupt

BCD:

a

Binary Counter 16-bits

1

Binary Coded Decimal (BCD) Counter
(4 Decades)

8253-5 Control Word Format

BSC Adapter

1-255

8251A Programming Procedures
After the support devices on the BSC adapter are programmed,
the 8251A is loaded with a set of control words that define the
communication environment. The control words are split into two
formats, mode instruction, and command instruction.
Both the mode and command instructions must conform to a
specified sequence for proper device operation. The mode
instruction must be inserted immediately after a reset operation,
before using the 8251A for data communications. The required
synchronization characters for the defined communication
technique are next loaded into the 8251A (usually hex 32 for
BSC). All control words written to the 8251A after the mode
instruction will load the command instruction. Command
instructions can be written to the 8251A at any time in the data
block anytime during the operation of the 8251A. To return to the
mode instruction format, the master reset bit in the command
instruction word can be set to start an internal reset operation
which automatically places the 8251A back into the mode
instruction format. Command instructions must follow the mode
instructions or synchronization characters.
The following diagram is a typical data block, showing the mode
instruction and command instruction.
3A9

c/o = 1

Mode Instruction 1

3A9

c/o = 1

SYNC Character 1

3A9

c/o = 1

SYNC Character 2

3AG

c/o = 1

Command Instruction

3AB

c/o = 0

3A9

c/o =1

3AB

c/o =0

3A9

c/o = 1

It

Data

Command Instruction

Data

"

Command Instruction

Typical Data Block

1-256

BSC Adapter

II

Mode Instruction Definition
The mode instruction defines the general operational
characteristics of the 8251A. It follows a reset operation (internal
or external). Once the mode instruction has been written to the
8251A by the system unit, synchronization characters or
command instructions may be written to the device.
The following figure shows the format for the mode instruction.
Address: Hex 3A9 for BSe
Hex 389 for Alternate BSe

Mode Instruction Format

Bit

7

6

5

4

3

[I

2

I

l-y
1

0

No>
01
Not U""AlM,,
Used (Always 0)
Character Length Bit - - - Character Length Bit - - - 1 ~ ~,i',

,..bl.

1 ; Even Parity
1; SYNDET is an Input
0; Double SYNC Character

I

- - .,
- 1
I
0

1

1

Bit 0

Not used; always 0

Bit 1

Not used; always 0

1
0
1

5 Bits
6 Bits
7 Bits
8 Bits

Bit 2 and These two bits are used together to define the character
Bit 3
length. With 0 and 1 as inputs on bits 2 and 3,
character lengths of 5,6, 7, and 8 bits can be
established, as shown in the preceding figure.
Bit 4

In the synchronous mode, parity is enabled from this
bit. A 1 on this bit sets parity enable.

Bit 5

The parity generation/check is set from this bit. For
BSC, even parity is used by having bit 5 = 1.

Bit 6

External synchronization is set by this bit. A 1 on this
bit establishes synchronization detection as an input.

Bit 7

This bit establishes the mode of character
synchronization. A 0 is set on this bit to give double
character synchronization.
BSC Adapter 1-257

Command-Instruction Format
The command-instruction format defines a status word that is
used to control the actual operation of the 8251A. Once the mode
instruction has been written to the 8251A, and SYNC characters
loaded, all further "Control Writes" to I/O address hex 3A9 or
hex 389 will load a command instruction.
Data is transferred by accessing two I/O ports on the 8251A,
ports 3A8 and 388. A byte of data can be read from port 3A8 and
can be written to port 388.
Address: Hex 3A9 for SSC
Hex 389 for Alternate

Bit

7

6

5

I

4

I

3

I

2

I

1

sse
0

~

Transmit Enable
Data Terminal Ready
Receive Enable
Send Break Character
Error Reset
Request to Send
Internal Reset
Enter Hunt Mode

Command Instruction Format

Bit 0

The Transmit Enable bit sets the function of the 8251A
to either enabled (1) or disabled (0).

Bit 1

The Data Terminal Ready bit, when set to 1 will force
the data terminal output to O. This is a one-bit inverting
output port.

Bit 2

The Receive Enable bit sets the function to either
enable the bit (1), or to disable the bit (0).

Bit 3

The Send Break Character bit is set to 0 for normal
BSC operation.

Bit 4

The Error Reset bit is set to 1 to reset error flags from
the command instruction.

Bit 5

A 1 on the Request to Send bit will set the output to O.
This is a one-bit inverting output port.

1-258

BSC Adapter

Bit 6

The Internal Reset bit when set to 1 returns the 8251A
to mode-instruction format.

Bit 7

The Enter Hunt bit is set to 1 for BSC to enable a
search for synchronization characters.

Status Read Definition
In telecommunication systems, the status of the active device must
often be checked to determine if errors or other conditions have
occurred that require the processor's attention. The 8251A has a
status read facility that allows the system software to read the
status of the device at anytime during the functional operation. A
normal read command is issued by the processor with 1/0 address
hex 3A9 for BSC, and hex 389 for Alternate BSC to perform a
status read operation.
The format for a status read word is shown in the figure below.
Some of the bits in the status read format have the same meanings
as external output pins so the 8251A can be used in a completely
polled environment or in an interrupt-driven environment.

Address: Hex 3A9 for BSe
Hex 389 for Alternate BSC
-

Bit

0
1
2

~

RxRDY

~

TxEmpty

3

~

Parity Error (PE Flag On when a Parity Error Occurs)

4

~

Overrun Error (OE Flag On when Overrun Error Occurs)

5

~

Framing Error (Not Used for Synchronous Communications)

6

.. SYNDET

7

~

.

TxRDY (See Note Below)

Data Set Ready (I ndicates that DSR is at 0 Level)

Note: TxRDY status bit does not have the same meaning as the 8251A
TxRDY output pin. The former is not conditioned by CTS and TxEnable.
The latter is conditioned by both CTS and TxEnable.

Status Read Format

BSC Adapter

1-259

Bit 0

See the Note in the preceding figure.

Bit 1

An output on this bit means a character is ready to be
received by the computer's 8088 microprocessor.

Bit 2

A 1 on this bit indicates the 8251A has no characters to
transmit.

Bit 3

The Parity Error bit sets a flag when errors are
detected. It is reset by the error reset in the command
instruction.

Bit 4

This bit sets a flag when the computers 8088
microprocessor does not read a character before another
one is presented. The 8251A operation is not inhibited
by this flag, but the overrun character will be lost.

Bit 5

Not used

Bit 6

SYNDET goes to 1 when the synchronization character
is found in receive mode. For BSC, SYNDET goes
high in the middle of the last bit of the second
synchronization character.

Bit 7

The Data Set Ready bit is a one bit inverting input. It
is used to check modem conditions, such as data-set
ready.

Interface Signal Information
The BSC adapter conforms to interface signal levels standardized
by the Electronics Industry Association (EIA) RS232C Standard.
These levels are shown in the following figure.
Additional lines, not standardized by the EIA, are pins 11, 18,
and 25 on the interface connector. These lines are designated as
Select Standby, Test, and Test Indicate. Select Standby is used to
support the switched network backup facility of a modem that
provides this option. Test and Test Indicate support a modem
wrap function on modems that are designated for
business-machine, controlled-modem wraps.

1-260

BSC Adapter

Driver

EIA RS232C/CCITT V24·V28 Signal Levels

+15 Vdc
~

Active/Data

0

+5 Vdc
+5 Vdc
Invalid Level
·5 Vdc
·5 Vdc
I nactive/ Data

~

1

·15 Vdc

Receiver

EIA RS232C/CCITT V24·V28 Signal Levels

+25 Vdc
Active/Data

~

0

+3 Vdc
+3 Vdc
Invalid Level
·3 Vdc
·3 Vdc

I nactive/Data

~

1

·25 Vdc

Interface Voltage Levels

BSC Adapter

1-261

Interrupt Information
Interrupt Level 4:

Transmitter Ready
Counter 1
Counter 2

Interrupt Level 3:

Receiver Ready

The following chart is a device address summary for the primary
and alternate modes of the binary synchronous communications
adapter.

Hex Address
Device

Register Name

Function

Primary

Alternate

3AO
3A1
3A2
3A3

380
381
382
383

8255
8255
8255
8255

Port A Data
Port B Data
Port C Data
Mode Set

I nternal/External Sensing
External Modem Interface
I nternal Control
8255 Mode Initialization

3A4
3A4
3A5
3A5
3A6
3A6
3A7

384
384
385
385
386
386
387

8253
8253
8253
8253
8253
8253
8253

Counter 0 LSB
Counter 0 MSB
Counter 1 LSB
Counter 1 MSB
Counter 2 LSB
Counter 2 MSB
Mode Register

Not Used in Synch Mode
Not Used in Synch Mode
I nactivity Time-Outs
I nactivity Time-Outs
I nactivity Time-Outs
I nactivity Time-Outs
8253 Mode Set

3A8
3A9

388
389

8251
8251

Data Select
Command/Status

Data
Mode/Command
USART Status

Device Address Summary

1-262

BSC Adapter

Rear Panel
25-Pin D-Shell

CI

• •
•
•

•
•
•
•
•
•
•
•

CI •
.CI 0

CI~

Cl

Q

25

•
•
•
•
•
•
•
•

•
•
•

•

14

0
Signal Name -

Description

No Connection

External
Device

Pin
1

Transmitted Data

2

Received Data

3

Request to Send

4

Clear to Send

5

Data Set Ready

6

Signal Ground

7

Received Line Signal Detector

8

No Connection

9

No Connection

10

Select Standby*

11

No Connection

12

No Connection

13

No Connection

14

Transmitter Signal Element Timing

15

No Connection

16

Receiver Signal Element Timing

17

Test (IBM Modems Only)*

18

No Connection

19

Data Terminal Ready

20

No Connection

21

Ring Indicator

22

Data Signal Rate Selector

23

No Connection

24

Test Indicate (IBM Modems Only)*

25

Binary
Synchron ous
Communi cations
Adapter

*Not standardized by EIA (Electronics Industry Association).

Connector Specifications

BSC Adapter

1-263

Notes:

1-264

BSC Adapter

IBM Synchronous Data Link Control
(SDLC) Communications Adapter

The SDLC communications adapter system control, voltage, and
data signals are provided through a 2 by 31 position card edge
tab. Modem interface is in the form of EIA drivers and receivers
connecting to an RS232C standard 25-pin, D-shell, male
connector.
The adapter is programmed by communications software to
operate in a half-duplex synchronous mode. Maximum
transmission rate is 9600 bits per second, as generated by the
attached modem or other data communication equipment.
The SDLC adapter utilizes an Intel 8273 SDLC protocol
controller and an Intel 8255A-5 programmable peripheral
interface for an expanded external modem interface. An Intel
8253 programmable interval timer is also provided to generate
timing and interrupt signals. Internal test loop capability is
provided for diagnostic purposes.
The figure below is a block diagram of the SDLC communications
adapter.
....."'
...IIS255A- 5
Data .f4---=D,....a-t;;;.a-=--=--..,
Bus
Buffer

EIA
Drivers
Receivers

System
Bus

Address

Address
Decode
logic

DeE

Modem

Status
Change
logic

SDLC Communications Adapter Block Diagram

SDLC Adapter

1-265

The 8273 SDLC protocol control module has the following key
features:
•

Automatic frame check sequence generation and checking.

•

Automatic zero bit insertion and deletion.

•

TTL compatibility.

•

Dual internal processor architecture, allowing frame level
command structure and control of data channel with minimal
system processor intervention.

The 8273 SDLC protocol controller operations, whether
transmission, reception, or port read, are each comprised of three
phases:
Command Commands and/or parameters for the required
operation are issued by the processor.
Execution

Executes the command, manages the data link, and
may transfer data to or from memory utilizing direct
memory access (DMA), thus freezing the processor
except for minimal interruptions.

Result

Returns the outcome of the command by returning
interrupt results.

Support of the controller operational phases is through internal
registers and control blocks ofthe 8273 controller.

1-266

SDLC Adapter

8273 Protocol Controller Structure
The 8273 module consists of two major interfaces: the processor
interface and the modem interface. A block diagram of the 8273
protocol controller module follows.
Registers
Txl/R

Command

Rxl/R

Parameter

Reset

Status
Result

Data
Bus
Buffer

DB07

TxD
TxC

TxD RQ . - - - - - - - - ,

DPiI
0-0-- 32 x ClK

TxDACK----~

RxDRQ-----.

t - - -..

RxDACK-----,

D-o--CTS

RxlNT
RD
WR

PB'4

Control
logic

TxlNT

RTS

.......---CD
Read
Write
DMA
Control
logic

A,

r~'----,.-- RxD

RESET

0---- RxC
CS-----'
ClK-----~

L..-_ _ _

FLAG DET

Internal Data Bus - Processor Interface

Modem Interface

8273 SDLC Protocol Control Block Diagram

SDLC Adapter

1-267

Processor Interface
The processor interface consists of four major blocks: the
control/read/write logic (C/R/W), internal registers, data transfer
logic, and data bus buffers.

Control/Read/Write Logic
The control/read/write logic is used by the processor to issue
commands to the 8273. Once the 8273 receives and executes a
command, it returns the results using the C/R/W logic. The logic
is supported by seven registers which are addressed by AO, AI,
RD, and WR, in addition to CS. AO and Al are the two
low-order bits of the adapter address-byte. RD and WR are the
processor read and write signals present on the system control
bus. CS is the chip select, also decoded by the adapter address
logic. The table below shows the address of each register using the
C/R/W logic.
Address Inputs

Control Inputs

AO

Al

CS

WR

RD

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
0
0
0
0
0
0
0

0
1
0
1
0
1
0
1

1
0
1
0
1
0
1
0

Register

Command
Status
Parameter
Result
Reset
Txl/R
None
Rxl/R

8273 SDLC Protocol Controller Register Selection

1-268

SDLC Adapter

8273 Control/ReadlWrite Registers
Command

Operations are initialized by writing the
appropriate command byte into this register.

Status

This register provides the general status of
the 8273. The status register supplies the
processor/adapter handshaking necessary
during various phases of the 8273 operation.

Parameter

Additional information that is required to
process the command is written into this
register. Some commands require more than
one parameter.

Immediate Result
(Result)

Commands that execute immediately
produce a result byte in this register, to be
read by the processor.

Transmit Interrupt
Results (TxI/R)

Results of trans.mit operations are passed to
the processor from this register. This result
generates an interrupt to the processor when
the result becomes available.

Receiver Interrupt
Results (Rx/I/R)

Results of receive operations are passed to
the processor from this register. This result
generates an interrupt to the processor when
the result becomes available.

Reset

This register provides a software reset
function for the 8273.

The other elements of the C/R/W logic are the interrupt lines
(RxINT and TxINT). Interrupt priorities are listed in the
"Interrupt Information" table in this section. These lines signal
the processor that either the transmitter or the receiver requires
service (results should be read from the appropriate register), or a
data transfer is required. The status of each interrupt line is also
reflected by a bit in the status register, so non-interrupt driven
operation is. also possible by the communication software
examining these bits periodically.

SDLe Adapter

1-269

Data Interfaces
The 8273 supports two independent data interfaces through the
data transfer logic: received data and transmitted data. These
interfaces are programmable for either DMA or non-DMA data
transfers. Speeds below 9600 bits-per-second mayor may not
require DMA, depending on the task load and interrupt response
time of the processor. The processor DMA controller is used for
management of DMA data transfer timing and addressing. The
8273 handles the transfer requests and actual counts of data-block
lengths. DMA level 1 is used to transmit and receive data
transfers. Dual DMA support is not provided.

Elements of Data Transfer Interface
TxDRQ/RxDRQ

This line requests a DMA to or from
memory and is asserted by the 8273.

TxDACK/RxDACK This line notifies the 8273 that a request
has been granted and provides access to
data regions. This line is returned by the
DMA controller (DACK 1 on the system
unit control bus is connected to
TxDACK/RxDACK on the 8273).
RD (Read)

This line indicates data is to be read from
the 8273 and placed in memory. It is
controlled by the processor DMA
controller.

WR (Write)

This line indicates if data is to be written to
the 8273 from memory and is controlled
by the processor DMA controller.

To request a DMA transfer, the 8273 raises the DMA request
line. Once the DMA controller obtains control of the system bus,
it notifies the 8273 that the DRQ is granted by returning DACK,
and WR or RD, for a transmit or receive operation, respectively.
The DACK and WR or RD signals transfer data between the
8273 and memory, independent of the 8273 chip-select pin (CS).
This "hard select" of data into the transmitter or out of the
receiver alleviates the need for the normal transmit and receive
data registers, addressed by a combination of address lines, CS,
and WRorRD.
1-270

SDLC Adapter

Modem Interface
The modem interface of the 8273 consists of two major blocks:
the modem control block and the serial data timing block.

Modem Control Block
The modem control block provides both dedicated and
user-defined modem control function. EIA inverting drivers and
receivers are used to convert TTL levels to EIA levels.
Port A is a modem control input port. Bits PAO and PAl have
dedicated functions.
8273 Port A (Modem Control Input Port)
Bit PA

7

6

543

2

o
PAO Clear to Send
PA 1 Ca rrier Detect
PA2 Data Set Ready
PA3 CTS Change

L---'----'_ _ _ _ _ _ _ _ _

PA4 DSR Change
Not Used

Bit PAO

This bit reflects the logical state of the clear to
send (CTS) pin. The 8273 waits until CTS is
active before it starts transmitting a frame. If
CTS goes inactive while transmitting, the frame
is aborted and the processor is interrupted. A
CTS failure will be indicated in the appropriate
interrupt-result register.

Bit PAl

This bit reflects the logical state of the carrier
detect pin (CD). CD must be active in
sufficient time for reception of a frame's
address field. If CD is lost (goes inactive) while
receiving a frame, an interrupt is generated with
a CD failure result.

Bit PA2

This bit is a sense bit for data set ready (DSR).

Bit PA3

This bit is a sense bit to detect a change in
CTS.
SDLC Adapter 1-271

Bit PA4

This bit is a sense bit to detect a change in data
set ready.

Bits PAS to P A 7 These bits are not used and each is read as a 1
for a read port A command.
Port B is a modem control output port. Bits PBO and PBS are
dedicated function pins.

8273 Port B (Modem Control Output Port)
Bit PB

7

6

5

4

3

2

0

II I~
L~

PB1 . Reserved

L...-_ _ _ _ _ _

PB3 . Reserved
PB4 - Reserved

PBO - R"",. to S,nd

PB2 . Data Terminal Ready

L -_ _ _ _ _ _ _~

PB5· Flag Detect

L...-_ _ _ _ _ _ _ _~

PB6 . Not Used

L...-_ _ _ _ _ _ _ _ _ _ _ _

PB7 . Not Used

Bit PBO This bit represents the logical state of request to send
(RTS). This function is handled automatically by the
8273.
Bit PB 1 Reserved.
Bit PB2

Used for data terminal ready.

Bit PB3

Reserved.

Bit PB4 Reserved.
Bit PBS

This bit reflects the state of the flag detect pin. This pin
is activated whenever an active receiver sees a flag
character.

Bit PB6 Not used.
Bit PB7

1-272

Not used.

SDLC Adapter

Serial Data Timing Block
The serial data timing block is comprised of two sections: the
serial data logic and the digital phase locked loop (DPLL).
Elements of the serial data logic section are the data pins TxD
(transmitted data output) and RxD (received data input), and the
respective clocks. The leading edge of TxC generates new
transmitted data and the trailing edge of RxC is used to capture
the received data. The figure below shows the timing for these
signals.

RxC---"

RxD

8273 SOLC Protocol Controller Transmit/Receive Timing

The digital phase locked loop provided on the 8273 controller
module is utilized to capture looped data in proper
synchronization during wrap operations performed by diagnostics.

SDLC Adapter

1-273

8255A-5 Programmable Peripheral
Interface
The 8255A-5 contains three eight bit ports. Descriptions of each
bit of these ports are as follows:
8255A-5 Port A Assignments'
Bit

7

6 5 4

3

2

Hex Address 380

1 0

~

0= Ring Indicator is on from Interface

o = Data Carrier Detect is on from Interface
Oscillating = Transmit Clock Active
0= Clear to Send is on from Interface
Oscillating = Receive Clock Active

1 = Modem Status Changed
1 = Timer 2 Output Active
1 = Timer 1 Output Active
*Port A is defined as an input port

8255A-5 Port B Assignments'
Bit

7

6 5 4

3

2

Hex Address 381

1 0

~

0= Turn On Data Signal Rate Select at
Modem Interface
0= Turn On Select Standby at Modem
Interface
0= Turn On Test

1 = Reset Modem Status Changed Logic
1 = Reset 8273
1 = Gate Timer 2
1 = Gate Timer 1

1 = Enable Level 4 Interrupt
*Port B is defined as an output port

1-274

SDLC Adapter

8255A-5 Port C Assignments*
Bit

7

6

5 4 3

2

Hex Address 382

1 0

III ~

1

~

G". I "W",I Clock

,0",,", .;,'

1 = Gate External Clock (Output Bit)
1 = Electronic Wrap (Output Bit)
0= Gate Interrupts 3 and 4 (Output Bit)
Oscillating = Receive Data (Input Bit)
Oscillating = Timer 0 Output (Input bit)
0= Test Indicate Active (Input Bit)
Not Used

*Port C is defined for internal control and gating functions. It has three input
and four output bits. The four output bits are defined during initialization, but
only three are used.

8253-5 Programmable Interval Timer
The 8253-5 is driven by a processor clock signal divided by two_
It has the following output:
Timer a Programmed to generate a square wave signal, used as
an input to timer 2_ Also connected to 8253 port C,
bit 5_
Timer 1 Connected to 8255 port A, bit 7, and interrupt level 4.
Timer 2 Connected to 8255 port A, bit 6, and interrupt level 4.

Programming Considerations
The software aspects of the 8273 involve the communication of
both commands from the processor to the 8273 and the return of
results of those commands from the 8273 to the processor. Due to
the internal processor architecture of the 8273, this system
unit/8273 communication is basically a form of interprocessor
communication, and must be considered when programming for
the SDLC communications adapter.

SDLC Adapter

1-275

The protocol for this interprocessor communication is
implemented through use of handshaking supplied in the 8273
status register. The bit definitions of this register are shown below.
8273 Status Register Format
Bit

7

6

5

4

3

2

Hex Address 388

1 0

III

~ T"RA
I ~ T,INT R,,"" Av.;I.bI,
RxlRA 1 RxlNT Result Available
=

TxlNT 1 = Tx Interrupt
L...-_ _ _ _ _

RxlNT 1 = Rx Interrupt
CRBF 1 = Command Result Buffer Full

' - - - - - - - - CPBF 1 = Command Parameter Buffer Full
' - - - - - - - - - CBF 1 = Command Buffer Full
' - - - - - - - - - CBSY 1 = Command Busy

Bit 0

This bit is the transmitter interrupt result available
(TxIRA) bit. This bit is set when the 8273 places an
interrupt-result byte in the TxI/R register, and reset
when the processor reads the TxI/R register.

Bit 1

This bit is the receiver interrupt result available
(RxIRA) bit. It is the corresponding result-available bit
for the receiver. It is set when the 8273 places an
interrupt-result byte in the RxI/R register and reset
when the processor reads the register.

Bit 2

This bit is the transmitter interrupt (TxINT) bit and
reflects the state of the TxINT pin. TxINT is set by the
8273 whenever the transmitter needs servicing, and
reset when the processor reads the result or performs
the data transfer.

1-276

SDLC Adapter

Bit 3

This bit is the receiver interrupt (RxINT) bit and is
identical to the TxINT, except action is initiated based
on receiver interrupt-sources.

Bit 4

This bit is the command result buffer full (CRBF) bit.
It is set when the 8273 places a result from an
immediate-type command in the result register, and
reset when the processor reads the result or pelforms
the data transfer.

Bit 5

This bit is the command parameter buffer full (CPBF)
bit and indicates that the parameter register contains a
parameter. It is set when the processor deposits a
parameter in the parameter register, and reset when the
8273 accepts the parameter.

Bit 6

This bit is the command buffer full (CBF) bit and, when
set, it indicates that a byte is present in the command
register. This bit is normally not used.

Bit 7

This bit is the command busy (CBSY) bit and indicates
when the 8273 is in the command phase. It is set when
the processor writes a command into the command
register, starting the command phase. It is reset when
the last parameter is deposited in the parameter register
and accepted by the 8273, completing the command
phase.

SDLC Adapter

1-277

Initializing the Adapter (Typical Sequence)
Before initialization ofthe 8273 protocol controller, the support
devices on the card must be initialized to the proper modes of
operation.
Configuration of the 8255A-5 programmable peripheral interface
is accomplished by selecting the mode-set address for the 8255
(see the "SDLC Communications Adapter Device Addresses"
table later in this section) and writing the appropriate control word
to the device (hex 98) to set ports A, B, and C to the modes
described previously in this section.
Next, a bit pattern is output to port C which disallows interrupts,
sets wrap mode on, and gates the external clock pins (address =
hex 382, data = hex OD). The adapter is now isolated from the
communications interface.
Using bit 4 of port B, the 8273 reset line is brought high, held and
then dropped. This resets the internal registers of the 8273.
The 8253-5's counter 1 and 2 terminal-count values are now set
to values which will provide the desired time delay before a level
4 interrupt is generated. These interrupts may be used to indicate
to the communication software that a pre-determined period of
time has elapsed without a result interrupt (interrupt level 3).
The terminal count-values for these counters are set for any time
delay which the programmer requires. Counter 0 is also set at this
time to mode 3 (generates square wave signal, used to drive
counter 2 input).
To setup the counter modes, the address for the 8253 counter
mode register is selected (see the "SDLC Communications
Adapter Device Addresses" table, later in this section), and the
control word for each individual counter is written to the device
separately. The control-word format and bit definitions for the
8253 are shown below. Note that the two most-significant bits of
the control word select each individual counter, and each counter
mode is defined separately.
Once the support devices have been initialized to the proper
modes and the 8273 has been reset, the 8273 protocol controller
is ready to be configured for the operating mode that defines the
communications environment in which it will be used.
1-278

SDLC Adapter

Control Word Format
D7

I

SC1

D6

I

sca

D4

D5

I

RL 1

I

RLa

D3

I

M2

D,

D2

I

M1

I

Ma

Do

1

BCD

I

Definitions of Control
SC - Select Counter:
SC1

sca

a

a

Select Counter a

a

1

Select Counter 1

1

a

Select Counter 2

1

1

Illegal

RL - Read/Load:
RL 1

RLO

a

a

Counter Latching operation

1

a

Read/Load most significant byte (MSB)

a

1

Read/Load least significant byte (LSB)

1

1

Read/Load least significant byte first,
then most significant byte.

M - Mode:
M2

M1

Ma

Mode

a

a

a

Mode a

a

a

1

Mode 1

X

1

a

Mode 2

X

1

1

Mode 3

1

a

a

Mode 4

1

a

1

Mode 5

BCD:
a

Binary Counter 16-bits

1

Binary Coded Decimal (BCD) Counter (4 Decades)

8253-5 Programmable Interval Timer Control Word

SDLC Adapter

1-279

Initialization/Configuration Commands
The initialization/configuration commands manipulate internal
registers of the 8273, which define operating modes. After chip
reset, the 8273 defaults to all l's in the mode registers. The
initialization/configuration commands either set or reset specified
bits in the registers depending on the type of command. One
parameter is required with the commands. The parameter is
actually the bit pattern (mask) used by the set or reset command
to manipulate the register bits.
Set commands perform a logical OR operation of the parameter
(mask) of the internal register. This mask contains l's where
register bits are to be set. Zero (O's) in the mask cause no change
to the corresponding register bit.
Reset commands perform a logical AND operation of the
parameter (mask) and internal register. The mask 0 is reset to
register bit, and 1 to cause no change.
The following are descriptions of each bit of the operating, serial
I/O, one-bit delay, and data transfer mode registers.

Operating Mode Register
8273 Operating Mode Register Format
Bit

7

6

5 4

3

2

1 0

~
~

III

1

~ Flog ","om Mod,

1 = Two Preframe Sync Characters
1 = Buffered Mode

L -_ _ _~

1 = Enable Early Tx Interrupt
1 = EOP Interrupt Enable

' - - - - - -.... 1 = HDLC Abort Enable
Not Used

L..-_ _ _ _ _. . . .

' - - - - - - - -.... Not Used

1-280

SDLC Adapter

Bit 0

If bit 0 is set to aI, flags are sent immediately if the
transmitter was idle when the bit was set. If a transmit
or transmit-transparent command was active, flags are
sent immediately after transmit completion. This mode
is ignored if loop transmit is active or the one-bit-delay
mode register is set for one-bit delay. If bit 0 is reset (to
0), the transmitter sends idles on the next character
boundary if idle or, after transmission is complete, if the
transmitter was active at bit-O reset time.

Bit 1

If bit 1 is set to aI, the 8273 sends two characters
before the first flag of a frame. These characters are hex
00 ifNRZI is set or hex 55 ifNRZI is not set. (See
"Seriall!O Mode Register," for NRZI encoding mode
format.)

Bit 2

If bit 2 is set to aI, the 8273 buffers the first two bytes
of a received frame (the bytes are not passed to
memory). Resetting this bit (to 0) causes these bytes to
be passed to and from memory.

Bit 3

This bit indicates to the 8273 when to generate an
end-of-frame interrupt. If bit 3 is set, an early interrupt
is generated when the last data character has been
passed to the 8273. Ifthe processor responds to the
early interrupt with another transmit command before
the final flag is sent, the final-flag interrupt will not be
generated and a new frame will begin when the current
frame is complete. Thus, frames may be sent separated
by a single flag. A reset condition causes an interrupt to
be generated only following a final flag.

Bit 4

This is the EOP-interrupt-mode function and is not used
on the SDLC communications adapter. This bit should
always be in the reset condition.

Bit 5

This bit is always reset for SDLC operation, which
causes the 8273 protocol controller to recognize eight
ones (0 1 1 1 1 1 1 1 1) as an abort character.

SDLC Adapter

1-281

Serial I/O Mode Register
8273 Serial 1/0 Mode Register Format
Bit

7

6

5 4

3

2

1 0

~

I L.. 1
L----:. 1
1

=

NRZI Mode

=

Clock Loopback

= Data

Loopback

Not Used
' - - - - - - Not Used
Not Used
1...-_ _ _ _ _ _ Not Used
1...-_ _ _ _......

' - - - - - - - -__ Not Used

Bit 0

Set to 1, this bit specifies NRZI encoding and decoding.
Resetting this bit specifies that transmit and receive
data be treated as a normal positive-logic bit stream.

Bit 1

When bit 1 is set to 1, the transmit clock is internally
routed to the receive-clock circuitry. It is normally used
with the loopback bit (bit 2). The reset condition causes
the transmit and receive clocks to be routed to their
respective 8273 I/O pins.

Bit 2

When bit 2 is set, the transmitted data is internally
routed to the received data circuitry. The reset
condition causes the transmitted and received data to be
routed to their respective 8273 I/O pins.

Data Transfer Mode Register
8273 Data Transfer Mode Register Format
Bit

7

6

5 4

3

2

1 0

IIIIIII ~

1 = Interrupt Data Transfers
_·L.-·I...-I·L.-·L.-·L.-·L.-_a Not Used

L..

1-282

SDLC Adapter

When the data transfer mode register is set, the 8273 protocol
controller will interrupt when data bytes are required for
transmission, or are available from a reception. If a transmit or
receive interrupt occurs and the status register indicates that there
is no transmit or receive interrupt result, the interrupt is a transmit
or receive data request, respectively. Reset of this register causes
DMA requests to be performed with no interrupts to the
processor.

One- Bit Delay Mode Register
8273 One-Bit Delay Mode Register Format
Bit

7

6 5 4

III

3 2

1

I I I I

.

a

I:
-

Not Used
1 = One-Bit Delay Enable

When one-bit delay is set, the 8273 retransmits the received data
stream one-bit delayed. Reset of this bit stops the one-bit delay
mode.
The table below is a summary of all set and reset commands
associated with the 8273 mode registers. The set or reset mask
used to define individual bits is treated as a single parameter. No
result or interrupt is generated by the 8273 after execution of
these commands.

Command

Hex
Code

Parameter

One-Bit Delay Mode

Set
Reset

A4
64

Set Mask
Reset Mask

Data Transfer Mode

Set
Reset

97
57

Set Mask
Reset Mask

Operating Mode

Set
Reset

91
51

Set Mask
Reset Mask

Serial liD Mode

Set
Reset

AO
60

Set Mask
Reset Mask

Register

8273 SOLC Protocol Controller Mode Register Commands

SDLC Adapter

1-283

Command Phase
Although the 8273 is a full duplex device, there is only one
command register. Thus, the command register must be used for
only one command sequence at a time and the transmitter and
receiver may never be simultaneously in a command phase.
The system software starts the command phase by selecting the
8273 command register address and writing a command byte into
the register. The following table lists command and parameter
information for the 8273 protocol controller. If further information
is required by the 8273 prior to execution of the command, the
system software must write this information into the parameter
register.

1-284

SDLC Adapter

Command Description

Command
(Hex)

Parameter

Results

Result
Port

Completion
Interrupt

Set One-Bit Delay

A4

Set Mask

None

-

No
No

Reset One-Bit Delay

64

Reset Mask

None

-

Set Data Transfer
Mode

97

Set Mask

None

-

No

Reset Data Transfer
Mode

57

Reset Mask

None

-

No

Set Operating Mode

91

Set Mask

None

-

No
No

Reset Operating Mode

51

Reset Mask

None

-

Set Serial 110 Mode

AO

Set Mask

None

-

No

Reset Serial 110 Mode

60

Reset Mask

None

-

No

General Receive

CO

BO,B1

RIC,RO,R1,
A,C

RXIIR

Yes

Selective Receive

C1

BO, B1, A1,
A2

RIC,RO,R1,
A,C

RXIIR

Yes

Receive Disable

C5

None

None

-

No

Transmit Frame

C8

LO,L1,A,C

TIC

TXIIR

Yes

Transmit Transparent

C9

LO,L1

TIC

TXIIR

Yes

Abort Transmit Frame

CC

None

TIC

TXIIR

Yes

Abort Transmit
Transparent

CD

None

TIC

TXIIR

Yes

Read Port A

22

None

Port Value

Result

No

Read Port B

23

None

Port Value

Result

No

Set Port B Bit

A3

Set Mask

None

-

No

63

Reset Mask

None

-

No

Reset Port B Bit

8273 Command Summary Key
80
81

A

-

C

-

RXIIR
TXIIR
RO
Rl
RIC
TIC

-

LO
11
Al
A2

Least significant byte of the receiver buffer length.
Most significant byte of the receiver buffer length.
Least significant byte of the Tx frame length.
Most significant byte of the Tx frame length.
Receive frame address match field one.
Receive frame address match field two.
Address field of received frame. If non-buffered mode is specified, this
result is not provided.
Control field of received frame. If non-buffered mode is specified, this
result is not provided.
Receive interrupt result register.
Transmit interrupt result register.
Least significant byte of the length of the frame received.
Most significant byte of the length of the frame received.
Receiver interrupt result code.
Transmitter interrupt result code.

8273 SDLC Protocol Controller Commands

SDLC Adapter

1-285

A flowchart of the command phase is shown below. Handshaking
of the command and parameter bytes is accomplished by the
CBSY and CPBF bits of the status register. A command may not
be written if the 8273 is busy (CBSY = 1). The original command
will be overwritten if a second command is issued while
CBSY = 1. The flowchart also indicates a parameter buffer full
check. The processor must wait until CPBF = 0 before writing a
parameter to the parameter register. Previous parameters are
overwritten and lost if a parameter is written while CPBF = 1.

No

End of Command Phase

8273 SOLC Protocol Controller Command Phase Flowchart

1-286

SDLC Adapter

Execution Phase
During the execution phase, the operation specified by the
command phase is performed. IfDMA is utilized for data
transfers, no processor involvement is required.
For interrupt-driven transfers the 8273 raises the appropriate INT
pin (TxINT or RxINT). When the processor responds to the
interrupt, it must determine the cause by examining the status
register and the associated IRA (interrupt result available) bit of
the status register. If IRA = 0, the interrupt is a data transfer
request. If IRA = 1, an operation is complete and the associated
interrupt result register must be read to determine completion
status.

Result Phase
During the result phase, the 8273 notifies the processor of the
outcome of a command execution. This phase is initiated by
either a successful completion or error detection during execution.
Some commands such as reading or writing the I/O ports provide
immediate results. These results are made available to the
processor in the 8273 result register. Presence of a valid
immediate result is indicated by the CRBF (command result
buffer full) bit of the status register.
Non-immediate results deal with the transmitter and receiver.
These results are provided in the TxIlR (transmit interrupt result)
or Rxl/R (receiver interrupt result) registers, respectively. The
8273 notifies the processor that a result is available with the
TxlRA and RxlRA bits of the status register. Results consist of
one-byte result interrupt code indicating the condition for the
interrupt and, if required, one or more bytes supplying additional
information. The "Result Code Summary" table later in this
section provides information on the format and decode of the
transmitter and receiver results.
The following are typical frame transmit and receive sequences.
These examples assume DMA is utilized for data transfer
operations.

SDLC Adapter 1-287

Transmit
Before a frame can be transmitted, the DMA controller is
supplied, by the communication software, the starting address for
the desired information field. The 8273 is then commanded to
transmit a frame (by issuing a transmit frame command).
After a command, but before transmission begins, the 8273 needs
some more information (parameters). Four parameters are
required for the transmit frame command; the frame address field
byte, the frame control field byte, and two bytes which are the
least significant and most significant bytes of the information field
byte length. Once all four parameters are loaded, the 8273 makes
RTS (request to send) active and waits for CTS (clear to send) to
go active from the modern interface. Once CTS is active, the 8273
starts the frame transmission. While the 8273 is transmitting the
opening flag, address field, and control field, it starts making
transmitter DMA requests. These requests continue at character
(byte) boundaries until the pre-loaded number of bytes of
information field have been transmitted. At this point, the requests
stop, the FCS (frame check sequence) and closing flag are
transmitted, and the TxINT line is raised, signaling the processor
the frame transmission is complete and the result should be read.
Note that after the initial command and parameter loading, no
processor intervention was required (since DMA is used for data
transfers) until the entire frame was transmitted.

General Receive
Receiver operation is very similar. Like the initial transmit
sequence, the processor's DMA controller is loaded with a
starting address for a receive data buffer and the 8273 is
commanded to receive. Unlike the transmitter, there are two
different receive commands; a general receive, where all received
frames are transferred to memory, and selective receive, where
only frames having an address field matching one of two
preprogrammed 8273 address fields are transferred to memory.

1-288

SDLC Adapter

(This example covers a general receive operation.) After the
receive command, two parameters are required before the receiver
becomes active; the least significant and most significant bytes of
the receiver buffer length. Once these bytes are loaded, the
receiver is active and the processor may return to other tasks. The
next frame appearing at the receiver input is transferred to
memory using receiver DMA requests. When the closing flag is
received, the 8273 checks the PCS and raises its RxINT line. The
processor can then read the results, which indicate if the frame
was error-free or not. (If the received frame had been longer than
the pre-loaded buffer length, the processor would have been
notified of that occurrence earlier with a receiver error interrupt).
Like the transmit example, after the initial command, the
processor is free for other tasks until a frame is completely
received.

Selective Receive
In selective receive, two parameters (AI and A2) are required in
addition to those for general receive. These parameters are two
address match bytes. When commanded to selective receive, the
8273 passes to memory or the processor only those frames having
an address field matching either Al or A2. This command is
usually used for secondary stations with A I designating the
secondary address and A2 being the "all parties" address. If only
one match byte is needed, A 1 and A2 should be equal. As in
general receive, the 8273 counts the incoming data bytes and
interrupts the processor if the received frame is larger than the
preset receive buffer length.

SDLC Adapter

1-289

Result Code Summary
Hex Code
T
r
a
n
s
m
i

Result

Status After Interrupt

OC
OD
OE
OF
10

Early Transmit Interrupt
Frame Transmit Complete
DMA Underrun
Clear to Send Error
Abort Complete

Transmitter Active
Idle or Flags
Abort
Abort
Idle or Flags

XO
Xl
03
04
05
06
07
08
09
OA
OB

A 1 Match or General Receive
A2 Match
CRC Error
Abort Detected
Idle Detected
EOP Detected
Frame Less Than 32 Bits
DMA Overrun
Memory Buffer Overflow
Carrier Detect Failure
Receiver Interrupt Overrun

Active
Active
Active
Active
Disabled
Disabled
Active
Disabled
Disabled
Disabled
Disabled

t

R
e
c
e
i
v
e

Note: X decodes to number of bits in partial byte received.

The first two codes in the receive result code table result from the
error free reception of a frame. Since SDLC allows frames of
arbitrary length (> 32 bits), the high order bits of the receive result
report the number of valid received bits in the last received
information field byte. The chart below shows the decode of this
receive result bit.
X

Bits Received in Last Byte

E
0

All Eight Bits of Last Byte
BitO Only
Bitl-BitO
Bit2-BitO
Bit3-BitO
Bit4-BitO
Bit5-BitO
Bit6-BitO

8
4
C
2
A
6

1-290

SDLC Adapter

Address and Interrupt Information
The following tables provide address and interrupt information for
the SDLC adapter:
Hex Code
380
381
382
383
384
384
385
385
386
386
387
388
389
38A
38B
38C

Device

Register Name

8255
8255
8255
8255
8253
8253
8253
8253
8253
8253
8253
8273
8273
8273
8273
8273

Port A Data
Port B Data
Port C Data
Mode Set
Counter 0 LSB
Counter 0 MSB
Counter 1 LSB
Counter 1 MSB
Counter 2 LSB
Counter 2 MSB
Mode Register
Comma nd/Status
Parameter /Result
Transmit INT Status
Receive INT Status
Data

Function
Internal/External Sensing
External Modem Interface
Internal Control
8255 Mode Initialization
Square Wave Generator
Square Wave Generator
Inactivity Time-Outs
Inactivity Time-Outs
Inactivity Time-Outs
Inactivity Time-Outs
8253 Mode Set
Out=Command In=Status
Out=Parameter In=Status
DMA/INT
DMA/INT
DPC (Direct Program Control)

SD LC Communications Adapter Device Addresses

Interrupt Level 3

Transmit/Receive Interrupt

Interrupt Level 4

Timer 1 Interrupt
Timer 2 Interrupt
Clear to Send Changed
Data Set Ready Changed

DMA Level One is used for Transmit and Receive

Interrupt Information

SDLC Adapter

1-291

Interface Information
The SDLC communications adapter conforms to interface signal
levels standardized by the Electronics Industries Association
RC-232C Standard. These levels are shown in the figure below.
Additional lines used but not standardized by EIA are pins 11,
18, and 25. These lines are designated as select standby, test and
test indicate, respectively. Select Standby is used to support the
switched network backup facility of a modem providing this
option. Test and test indicate support a modem wrap function on
modems which are designed for business machine controlled
modem wraps. Two jumpers on the adapter (PI and P2) are used
to connect test and test indicate to the interface, if required (see
Appendix D for these jumpers).

+25VdC

+15VdC~

+5Vdc

~

Active Level: Data = 0

+3 Vdc

Invalid Level
-5Vdc

~

-15VdC~

1-292

C
C

Receivers

Drivers

SDLC Adapter

3 VdC

Inactive Level: Data = 1

-25 Vdc

Rear Panel
25-Pin D-Shell
Connector

•
•
•
•
•
• ••
•
•
• •

25

14

0
Signal Name -

Description

No Connection

External
Device

Pin
1

Transmitted Data

2

Received Data

3

Request to Send

4

Clear to Send

5

Data Set Ready

6

Signal Ground

7

Received Line Signal Detector

8

No Connection

9

No Connection

10

Select Standby'

11

No Connection

12

No Connection

13

No Connection

14

Transmitter Signal Element Timing

15

No Connection

16

Receiver Signal Element Timing

17

Test (IBM Modems Only)'

18

No Connection

19

Data Terminal Ready

20

No Connection

21

Ring Indicator

22

Data Signal Rate Selector

23

No Connection

24

Test Indicate (IBM Modems Only)'

25

Synchro nous
Data Lin k
Control
Commun ications
Adapter

'Not standardized by EIA (Electronics Industry Association).

Connector Specifications

SDLC Adapter

1-293

Notes:

1-294

SDLC Adapter

IBM Communications Adapter Cable

The IBM Communications Adapter Cable is a ten foot cable for
connection of an IBM communications adapter to a modem or
other RC-232C DCE (data communications equipment). It is
fully shielded and provides a high quality, low noise channel for
interface between the communications adapter and DCE.
The connector ends are 25-pin D-shell connectors. All pin
connections conform with the EIA RS-232C standard. In
addition, connection is provided on pins 11, 18 and 25. These
pins are designated as select standby, test and test indicate,
respectively, on some modems. Select standby is used to support
the switched network backup facility, if applicable. Test and test
indicate support a modem wrap function on modems designed for
business machine controlled modem wraps.

Communications Cable

1-295

The IBM Communications Adapter Cable connects the following
pins on the 25-pin D-shell connectors.
14

14

Communications
Adapter
Connector

13

Modem
Connector

25

25

Communications
Adapter Connector
Pin #
NC

Name

1
2

2
3
4
5

Outer Cable Shield
Transmitted Data
Received Data
Request to Send
Clear to Send

3

6
7
8

Data Set Ready
Signal Ground (Inner Lead Shields)
Received Line Signal Detector

6
7
8

NC
NC

11

15

Select Standby

Transmitter Signal Element Timing

15

Receiver Signal Element Timing
Test

17
18

NC

NC

20

NC
Data Terminal Ready

20

Ring Indicator
Data Signal Rate Selector

22
23

Test Indicate

25

NC

22
23

NC

NC

25

11
NC
NC
NC

NC

17
18

4
5

NC
NC

NC
NC
NC

NC

Connector Specifications

1-296

Modem
Connector
Pin #

Communications Cable

13

SECTION 2: ROM BIOS AND
SYSTEM USAGE

ROM BIOS ........................................ 2-2
Keyboard Encoding and Usage ....................... 2-11

ROM BIOS

2-1

ROM BIOS

The basic input/output system (BIOS) resides in ROM on the
system board and provides device level control for the major I/O
devices in the system. Additional ROM modules may be located
on option adapters to provide device level control for that option
adapter. BIOS routines enable the assembly language programmer
to perform block (disk and diskette) or character-level I/O
operations without concern for device address and operating
characteristics. System services, such as time-of-day and memory
size determination, are provided by the BIOS.
The goal is to provide an operational interface to the system and
relieve the programmer of the concern about the characteristics of
hardware devices. The BIOS interface insulates the user from the
hardware, thus allowing new devices to be added to the system,
yet retaining the BIOS level interface to the device. In this
manner, user programs become transparent to hardware
modifications and enhancements.
The IBM Personal Computer MACRO Assembler manual and
the IBM Personal Computer Disk Operating System (DOS)
manual provide useful programming information related to this
section. A complete listing of the BIOS is given in Appendix A.

Use of BIOS
Access to BIOS is through the 8088 software interrupts. Each
BIOS entry point is available through its own interrupt, which can
be found in the "8088 Software Interrupt Listing."
The software interrupts, hex 10 through hex lA, each access a
different BIOS routine. For example, to determine the amount of
memory available in the system,
INT 12H
will invoke the BIOS routine for determining memory size and
will return the value to the caller.

2-2

ROM BIOS

Parameter Passing
All parameters passed to and from the BIOS routines go through
the 8088 registers. The prolog of each BIOS function indicates the
registers used on the call and the return. For the memory size
example, no parameters are passed. The memory size, in lK byte
increments, is returned in the AX register.
If a BIOS function has several possible operations, the AH
register is used at input to indicate the desired operation. For
example, to set the time of day, the following code is required:
MOV AH,l
MOV CX,HIG~_COUNT
MOV DX,LOW _COUNT
INT lAH

;function is to set time of day.
;establish the current time.
;set the time.

To read the time of day:
MOV AH,O
INT

lAH

;function is to read time of
day.
;read the timer.

Generally, the BIOS routines save all registers except for AX and
the flags. Other registers are modified on return only if they are
returning a value to the caller. The exact register usage can be
seen in the prolog of each BIOS function.

ROM BIOS

2·3

Address
(Hex)
0-3
4-7
8-B
C-F
10-13
14-17
18-1 B
1 D-1 F
20-23
24-27
28-2B
2C-2F
30-33
34-37
38-3B
3C-3F
40-43
44-47
48-4B
4C-4F
50-53
54-57
58-5B
5C-5F
60-63
64-67
68-6B
6C-6F
70-73
74-77
78-7B
7C-7F

Interrupt
Number
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F

Name
Divide by Zero
Single Step
Nonmaskable
Breakpoint
Overflow
Pri nt Screen
Reserved
Reserved
Time of Day
Keyboard
Reserved
Communications
Communications
Disk
Diskette
Pri nter
Video
Equipment Check
Memory
Diskette/Disk
Communications
Cassette
Keyboard
Pri nter
Resident BASIC
Bootstrap
Time of Day
Keyboard Break
Timer Tick
Video Initialization
Diskette Parameters
Video Graphics Chars

8088 Software Interrupt Listing

2-4

ROM BIOS

BIOS Entry
D11
D11
NMI INT
D11
D11
PRINT_SCREEN
D11
D11
TIMERJNT
KBJNT
D11
D11
D11
D11
DISKJNT
D11
VIDEO_IO
EQUIPMENT
MEMORY_SIZE_DETERMINE
DISKETIEJO
RS232_IO
CASSETIEJO
KEYBOARD_IO
PRINTERJO
F600:0000
BOOT_STRAP
TIME_OF_DAY
DUMMY_RETURN
DUMMY_RETURN
VIDEO]ARMS
DISK_BASE
0

-

Vectors with Special Meanings
Interrupt Hex I B - Keyboard Break Address
This vector points to the code to be exercised when the Ctrl and
Break keys are pressed on the keyboard. The vector is invoked
while responding to the keyboard interrupt, and control should be
returned through an lRET instruction. The power-on routines
initialize this vector to point to an IRE T instruction, so that
nothing will occur when the Ctrl and Break keys are pressed
unless the application program sets a different value.
Control may be retained by this routine, with the following
problems. The Break may have occurred during interrupt
processing, so that one or more End of Interrupt commands must
be sent to the 8259 controller. Also, all I/O devices should be
reset in case an operation was underway at that time.

Interrupt Hex

Ie - Timer Tick

This vector points to the code to be executed on every systemclock tick. This vector is invoked while responding to the timer
interrupt, and control should be returned through an IRE T
instruction. The power-on routines initialize this vector to point to
an lRET instruction, so that nothing will occur unless the
application modifies the pointer. It is the responsibility of the
application to save and restore all registers that will be modified.

Interrupt Hex ID - Video Parameters
This vector points to a data region containing the parameters
required for the initialization of the 6845 on the video card. Note
that there are four separate tables, and all four must be
reproduced if all modes of operation are to be supported. The
power-on routines initialize this vector to point to the parameters
contained in the ROM video routines.

ROM BIOS

2-5

Interrupt Hex 1E - Diskette Parameters
This vector points to a data region containing the parameters
required for the diskette drive. The power-on routines initialize the
vector to point to the parameters contained in the ROM diskette
routine. These default parameters represent the specified values
for any IBM drives attached to the machine. Changing this
parameter block may be necessary to reflect the specifications of
the other drives attached.

Interrupt Hex IF - Graphics Character Extensions
When operating in the graphics modes of the IBM Color/Graphics
Monitor Adapter (320 by 200 or 640 by 200), the read/write
character interface will form the character from the ASCII code
point, using a set of dot patterns. The dot patterns for the first 128
code points are contained in ROM. To access the second 128
code points, this vector must be established to point at a table of
up to 1K bytes, where each code point is represented by eight
bytes of graphic information. At power-on, this vector is
initialized to 000:0, and it is the responsibility of the user to
change this vector if the additional code points are required.

Interrupt Hex 40 - Reserved
When an IBM Fixed Disk Drive Adapter is installed, the BIOS
routines use interrupt hex 40 to revector the diskette pointer.

Interrupt Hex 41 - Fixed Disk Parameters
This vector points to a data region containing the parameters
required for the fixed disk drive. The power-on routines initialize
the vector to point to the parameters contained in the ROM disk
routine. These default parameters represent the specified values
for any IBM Fixed Disk Drives attached to the machine.
Changing this parameter block may be necessary to reflect the
specifications of the other fixed disk drives attached.

2-6

ROM BIOS

Other Read/Write Memory Usage
The IBM BIOS routines use 256 bytes of memory starting at
absolute hex 400 to hex 4FF. Locations hex 400 to 407 contain
the base addresses of any RS-232C cards attached to the system.
Locations hex 408 to 40F contain the base addresses of the
printer adapter.
Memory locations hex 300 to 3FF are used as a stack area during
the power-on initialization, and bootstrap, when control is passed
to it from power-on. If the user desires the stack in a different
area, the area must be set by the application.
Address
(Hex)

Interrupt
(Hex)

80-83
84-87
88-8B
8C-8F
90-93
94-97
98-9B
9C-9F
AO-FF
100-17F
180-19F
1AO-1 FF
200-217
218-3C3

20
21
22
23
24
25
26
27
28-3F
40-5F
60-67
68-7F
80-85
86-FO

3C4-3FF

F1-FF

Function
DOS Program Terminate
DOS Function Call
DOS Terminate Address
DOS Ctrl Break Exit Address
DOS Fata I Error Vector
DOS Absolute Disk Read
DOS Absolute Disk Write
DOS Terminate, Fix In Storage
Reserved for DOS
Reserved
Reserved for User Software Interrupts
Not Used
Reserved by BASIC
Used by BASIC Interpreter while BASIC is
running
Not Used

BASIC and DOS Reserved Interrupts

ROM BIOS

2-7

Address
(Hex)
400-48F
490-4EF
4FO-4FF

Mode

Function

ROM BIOS

See BIOS Listing
Reserved
Reserved as Intra-Application
Communication Area for any application
Reserved for DOS and BASIC
Print Screen Status Flag Store
O-Print Screen Not Active or Successful
Print Screen Operation
1 -Print Screen In Progress
255-Error Encountered during Print Screen
Operation
Single Drive Mode Status Byte
BASIC's Segment Address Store
Clock Interrupt Vector Segment: Offset Store
Break Key Interrupt Vector Segment: Offset
Store
Disk Error Interrupt Vector Segment: Offset
Store

500-5FF
500

DOS

504
510-511
512-515
516-519

DOS
BASIC
BASIC
BASIC

51 A-51 D

BASIC

Reserved Memory Locations

If you do DEF SEG (Default workspace segment):

Line number of current line being executed
Line number of last error
Offset into segment of start of program text
Offset into segment of start of variables
(end of program text 1-1)
Keyboard buffer contents
if O-no characters in buffer
if 1 -characters in buffer
Character color in graphics mode
Set to 1, 2, or 3 to get text in colors 1 to 3.
Do not set to O.
(Default = 3)
Example
100 Print

)
100

PEEK (&H2E)

+

L

I

Hex 64

H

I

BASIC Workspace Variables

2-8

ROM BIOS

256*PEEK (&H2F)

Hex 00

I

Offset
(Hex Value)

Length

2E
347
30
358

2
2
2
2

6A

1

4E

1

Starting Address in Hex

00000

BIOS
Interrupt
Vectors

00080

Available
Interrupt
Vectors

00400

BIOS
Data
Area

00500

User
Read/Write
Memory

caooo

Disk
Adapter

FOOOO

Read
Only
Memory

FEOOO

BIOS
Program
Area

BIOS Memory Map

BIOS Programming Hints
The BIOS code is invoked through software interrupts. The
programmer should not "hard code" BIOS addresses into
applications. The internal workings and absolute addresses within
BIOS are subject to change without notice.
If an error is reported by the disk or diskette code, you should
reset the drive adapter and retry the operation. A specified
number of retries should be required on diskette reads to ensure
the problem is not due to motor start-up.

When altering I/O port bit values, the programmer should change
only those bits which are necessary to the current task. Upon
completion, the programmer should restore the original
environment. Failure to adhere to this practice may be
incompatible with present and future applications.

ROM BIOS

2-9

Adapter Cards with System-Accessible
ROM Modules
The ROM BIOS provides a facility to integrate adapter cards with
on board ROM code into the system. During the POST, interrupt
vectors are established for the BIOS calls. After the default
vectors are in place, a scan for additional ROM modules takes
place. At this point, a ROM routine on the adapter card may gain
control. The routine may establish or intercept interrupt vectors to
hook themselves into the system.
The absolute addresses hex C8000 through hex F4000 are
scanned in 2K blocks in search of a valid adapter card ROM.
A valid ROM is defined as follows:
Byte 0:
Byte 1:
Byte 2:

Hex 55
HexAA
A length indicator representing the number of 512 byte
blocks in the ROM (length/512).
A checksum is also done to test the integrity of the
ROM module. Each byte in the defined ROM is
summed modulo hex 100. This sum must be 0 for
the module to be deemed valid.

When the POST identifies a valid ROM, it does a far call to byte
3 of the ROM (which should be executable code). The adapter
card may now perform its power-on initialization tasks. The feature
ROM should return control to the BIOS routines by executing a
far return.

2·10

ROM BIOS

Keyboard Encoding and Usage

Encoding
The keyboard routine provided by IBM in the ROM BIOS is
responsible for converting the keyboard scan codes into what will
be termed "Extended ASCII."
Extended ASCII encompasses one-byte character codes with
possible values of 0 to 255, an extended code for certain extended
keyboard functions, and functions handled within the keyboard
routine or through interrupts.

Character Codes
The following character codes are passed through the BIOS
keyboard routine to the system or application program. A "-1"
means the combination is suppressed in the keyboard routine. The
codes are returned in AL. See Appendix C for the exact codes.
Also, see "Keyboard Scan Code Diagram" in Section 1.
Key
Number
1
2
3
4
5

6
7
8

9
10
11
12
13
14
15
16
17

Base Case

Upper Case
Esc
!
@
#

Ctrl

Esc
-1
Nul (000) Note 1
-1
$
-1
-1
%
1\
RS(030)
6
-1
7
&
-1
8
*
(
-1
9
)
-1
0
US(031 )
=
+
-1
Del (127)
Backspace (008) Backspace (008)
-1
I-(Note 1)
-1(009)
Q
DCl (017)
q
ETB (023)
w
W
Esc
1
2
3
4
5

Alt
-1
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
Note
-1
-1
Note
Note

1
1
1
1
1
1
1
1
1
1
1
1

1
1

Character Codes (Part 1 of 3)

Keyboard Encoding

2-11

Key
Number
18
19
20
21
22
23
24
25
26
27
28
29 Ctrl
30
31
32
33
34
35
36
37
38
39
40
41
42 Shift
43
44
45
46
47
48
49
50
51
52
53
54 Shift
55
56 Alt
57
58
Caps Lock
59
60
61
62
63
64

Base Case

Upper Case

Ctrl

Alt

E
R
T
Y
U
I
0
P

ENO (005)
DC2 (018)
DC4 (020)
EM (025)
NAK (021)
HT (009)
SI (015)
DLE (016)
Esc (027)
GS (029
LF (010)
-1
SOH (001)
DC3 (019)
EOT (004)
ACK (006)
BEL (007)
BS (008)
LF (010)
VT (011)
FF (012)
-1
-1
-1
-1
FS (028)
SUB (026)
CAN (024)
ETX (003)
SYN (022)
STX (002)
SO (014)
CR (013)
-1
-1
-1
-1
(Note 1)
-1
SP
-1

Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
-1
-1
-1
-1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
-1
-1
-1
-1
-1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
-1
-1
-1
-1
-1
-1
SP
-1

e
r
t

Y
u
i

a
p
[

1

1

l

CR
-1
a
s
d
f

CR
-1
A
S
D
F
G
H

9
h
j

J

k
I

K
L
"
~

-1

-1
I
I

\
z

Z
X
C
V
B
N
M

x
c
v

b
n
m

<
>
7

/
-1
*
-1
SP
-1
Nul
Nul
Nul
Nul
Nul
Nul

(Note
(Note
(Note
(Note
(Note
(Note

-1
(Note 2)
-1
SP
-1
1)
1)
1)
1)
1)
1)

Nul
Nul
Nul
Nul
Nul
Nul

Character Codes (Part 2 of 3)

2-12

Keyboard Encoding

(Note
(Note
(Note
(Note
(Note
(Note

1)
1)
1)
1)
1)
1)

Nul
Nul
Nul
Nul
Nul
Nul

(Note
(Note
(Note
(Note
(Note
(Note

1)
1)
1)
1)
1)
1)

Nul
Nul
Nul
Nul
Nul
Nul

(Note
(Note
(Note
(Note
(Note
(Note

1)
1)
1)
1)
1)
1)

Key
Number

65
66
67
68
69 Num lock
70
Scroll lock

Base Case

Upper Case

Nul
Nul
Nul
Nul

Nul
Nul
Nul
Nul

(Note
(Note
(Note
(Note
-1
-1

1)
1)
1)
1)

(Note
(Note
(Note
(Note
-1
-1

Ctrl

Alt

Nul (Note 1)
Nul (Note 1)
Nul (Note 1)
Nul (Note 1)
Pause (Note 2)
Break (Note 2)

1)

1)
1)

1)

Nul
Nul
Nul
Nul

(Note
(Note
(Note
(Note
-1
-1

1)

1)
1)
1)

Notes: 1. Refer to "Extended Codes" in this section.
2. Refer to "Special Handling" in this section.

Character Codes (Part 3 of 3)

Keys 71 to 83 have meaning only in base case, in Num Lock (or
shifted) states, or in Ctrl state. It should be noted that the shift key
temporarily reverses the current Num Lock state.
Key

Num

Number

lock

71

7

72

8

73

9

Base Case
Home (Note 1)

t

Ait

-1

Ctrl
Clear Screen

(Note 1)

-1

-1

Page Up (Note 1)

-1

Top of Text and Home

74

-

- - - --- -- - -- - -- - --- - --

-1

-1

75

4

--(Note 1)

-1

Reverse Word (Note 1)

76

5

-1

-1

-1

77

6

-(Note 1)

-1

Advance Word (Note 1)

78

+

+

-1

-1

79

1

End (Note 1)

-1

Erase to EOl (Note 1)

80

2

(Note 1)

-1

-1

,

81

3

Page Down (Note 1 )

-1

Erase to EOS (Note 1)

82

0

Ins

-1

-1

83

Del (Notes 1,2)

Note 2 Note 2

Notes: 1 . Refer to "Extended Codes" in this section.

2. Refer to "Special Handling" in this section.

Keyboard Encoding

2-13

Extended Codes
Extended Functions
F or certain functions that cannot be represented in the standard
ASCII code, an extended code is used. A character code of 000
(Nul) is returned in AL. This indicates that the system or
application program should examine a second code that will
indicate the actual function. Usually, but not always, this second
code is the scan code of the primary key that was pressed. This
code is returned in AH.

Function

Second Code
3
15
16-25
30-38
44-50
59-68
71

72
73
75
77
79
80
81
82
83
84-93
94-103
104-113
114
115
116
117
118
119
120-131
132

-

Nul Character

Alt Q, W, E, R, T, Y, U, I, 0, P
AltA, S, 0, F, G, H, J, K, l
AltZ, X, C, V, B, N, M
F1 to F1 0 Function Keys Base Case
Home

t

---

Page Up and Home Cursor

End

t

Page Down and Home Cursor
Ins (Insert)
Del (Delete)
F11 to F20 (Upper Case F1 to F1 0)
F21 to F30 (Ctrl F1 to F1 0)
F31 to F40 (Alt F1 to F1 0)
Ctrl PrtSc (Start/Stop Echo to Printer)
Ctrl-(Reverse Word)
Ctrl-(Advance Word)
Ctrl End[Erase to End of Line (EOl)]
Ctrl PgDn [Erase to End of Screen (EOS)]
Ctrl Home (Clear Screen and Home)
Alt 1,2,3,4,5,6,7,8,9,0, -, = (Keys 2-13)
Ctrl PgUp (Top 25 Lines of Text and Home Cursor)

Keyboard Extended Functions

2-14

Keyboard Encoding

Shift States
Most shift states are handled within the keyboard routine,
transparent to the system or application program. In any case, the
current set of active shift states are available by calling an entry
point in the ROM keyboard routine. The following keys result in
altered shift states:

Shift
This key temporarily shifts keys 2-13,15-27,30-41,43-53,55,
and 59-68 to upper case (base case ifin Caps Lock state). Also,
the Shift key temporarily reverses the Num Lock or non-Num-Lock
state of keys 71-73, 75, 77, and 79-83.

Ctrl
This key temporarily shifts keys 3, 7, 12, 14, 16-28, 30-38,43-50,
55,59-71,73,75,77,79, and 81 to the Ctrl state. Also, the Ctrl
key is used with the Alt and Del keys to cause the "system reset"
function, with the Scroll Lock key to cause the "break" function,
and with the Num Lock key to cause the "pause" function. The
system reset, break, and pause functions are described in "Special
Handling" on the following pages.

Alt
This key temporarily shifts keys 2-13,16-25,30-38,44-50, and
59-68 to the Alt state. Also, the Alt key is used with the Ctrl and
Del keys to cause the "system reset" function described in
"Special Handling" on the following pages.

°

The Alt key has another use. This key allows the user to enter any
character code from to 255 into the system from the keyboard.
The user holds down the Alt key and types the decimal value of
the characters desired using the numeric keypad (keys 71-73,
75-77, and 79-82). The Alt key is then released. If more than
three digits are typed, a modulo-256 result is created. These three
digits are interpreted as a character code and are transmitted
through the keyboard routine to the system or application
program. Alt is handled internal to the keyboard routine.
Keyboard Encoding

2-15

Caps Lock
This key shifts keys 16-25, 30-38, and 44-50 to upper case. A
second depression of the Caps Lock key reverses the action. Caps
Lock is handled internal to the keyboard routine.

Scroll Lock
This key is interpreted by appropriate application programs as
indicating use of the cursor-control keys should cause windowing
over the text rather than cursor movement. A second depression
of the Scroll Lock key reverses the action. The keyboard routine
simply records the current shift state of the Scroll Lock key. It is
the responsibility of the system or application program to perform
the function.

Shift Key Priorities and Combinations
If combinations of the Alt, Ctrl, and Shift keys are pressed and
only one is valid, the precedence is as follows: the Alt key is first,
the Ctrl key is second, and the Shift key is third. The only valid
combination is Alt and Ctrl, which is used in the "system reset"
function.

Special Handling
System Reset
The combination of the Alt, Ctrl, and Del keys will result in the
keyboard routine initiating the equivalent of a "system reset" or
"reboot." System reset is handled internal to the keyboard.

Break
The combination of the Ctrl and Break keys will result in the
keyboard routine signaling interrupt hex lA. Also, the extended
characters CAL = hex 00, AH = hex 00) will be returned.
2-16

Keyboard Encoding

Pause
The combination of the Ctrl and Num Lock keys will cause the
keyboard interrupt routine to loop, waiting for any key except the
Num Lock key to be pressed. This provides a system- or
application-transparent method of temporarily suspending list,
print, and so on, and then resuming the operation. The "unpause"
key is thrown away. Pause is handled internal to the keyboard
routine.

Print Screen
The combination of the Shift and PrtSc (key 55) keys will result
in an interrupt invoking the print screen routine. This routine
works in the alphanumeric or graphics mode, with unrecognizable
characters printing as blanks.

Other Characteristics
The keyboard routine does its own buffering. The keyboard buffer
is large enough to support a fast typist. However, if a key is
entered when the buffer is full, the key will be ignored and the
"bell" will be sounded.
Also, the keyboard routine suppresses the typematic action of the
following keys: Ctrl, Shift, Alt, Num Lock, Scroll Lock, Caps
Lock, and Ins.

Keyboard Encoding

2-17

Keyboard Usage
This section is intended to outline a set of guidelines of key usage
when performing commonly used functions.
Function

Key(s)

Comment

Home Cursor

Home

Editors; word processors

Return to outermost menu

Home

Menu driven applications

t

Move cursor up
Page up, scroll backwards 25
lines and home
Move cursor left
Move cursor right
Scroll to end of text
Place cursor at end of line

PgUp

-

- - Key 75

End

~

Move cursor down
Page down, scroll forward
25 lines and home

Full screen editor, word processor
Editors; word processors
Text, command entry
Text, command entry
Editors; word processors
Full screen editor, word processor

Pg Dn

Editors; word processors

Start/Stop insert text at
cursor, shift text right in buffer

Ins

Text, command entry

Delete character at cursor

Del

Text, command entry

- - Key 14

Text, command entry

Destructive backspace
Tab forward

--t

Text entry

Tab reverse

14-

Text entry

Clear screen and home

Ctrl Home

t
J

Scroll up
Scroll down
Scroll left
Scroll right
Delete from cursor to EOL
Exit/Escape

In scroll lock mode
In scroll lock mode

---

Text, command entry

Esc

Editor, 1 level of menu, and so on

Ctrl End

Start/Stop Echo screen to
printer

Ctrl PrtSc
(Key 55)

Delete from cursor to EOS
Advance word

Ctrl PgDn
Ctrl

Reverse word

Ctrl

Window Right

Ctrl

Window Left

Ctrl

Enter insert mode

Command entry

---

Ins

In scroll lock mode
In scroll lock mode

Any time
Text, command entry
Text entry
Text entry
When text is too wide to fit screen
When text is too wide to fit screen
Line editor

Keyboard· Commonly Used Functions (Part 1 of 2)

2-18

Keyboard Encoding

Function
Exit insert mode
Cancel current line

Key(s)

Comment

Ins

Line editor

Esc

Command entry, text entry

Suspend system (pause)

Ctrl
Num Lock

Stop list, stop program, and so on
Resumes on any key

Break interrupt

Ctrl Break

Interrupt current process

System reset
Top of document and home
cursor
Sta ndard function keys
Secondary function keys

Alt Ctrl
Del
Ctrl PgUp
Fl-Fl0

Reboot
Editors, word processors
Primary function keys

Shift Fl-Fl0 Extra fu nction keys if lOa re not
Ctrl Fl-Fl0 sufficient
Alt Fl-Fl 0

Extra function keys

Alt Keys
2-13
(1-9,0,-,=)

Extra function keys

Alt A-Z

Used when templates are put
along top of keyboard
Used when function starts with
same letter as one of the alpha
keys

Keyboard - Commonly Used Functions (Part 2 of 2)

Keyboard Encoding 2-19

Function
Carriage return
Line feed
Bell
Home
Cursor up
Cursor down
Cursor left
Cursor right
Advance one word
Reverse one word
Insert
Delete
Clear screen
Freeze output
Tab advance
Stop execution (break)
Delete current line
Delete to end of line
Position cursor to end of line

Key

-J

Ctrl -J
Ctrl G
Home

~t

-- -

Ctrl
Ctrl
Ins
Del
Ctrl Home
Ctrl Num Lock
---I
Ctrl Break
Esc
Ctrl End
End

DOS Special Functions

Function
Suspend
Echo to printer
Stop echo to pri nter
Exit current function (break)
Backspace
Line feed
Cancel line
Copy character
Copy until match
Copy remaining
Skip character
Skip until match
Enter insert mode
Exit insert mode
Make new line the template
String separator in REPLACE
End of file in keyboard input

Key
Ctrl Num Lock
Ctrl PrtSc
(Key 55 any case)
Ctrl PrtSc
(Key 55 any case)
Ctrl
Break
..- Key 14
Ctrl...J
Esc
F1 o r F2
F3
Del
F4
Ins
Ins
F5
F6
F6

BASIC Screen Editor Special Fun~tions

2-20

Keyboard Encoding

APPENDIX A: ROM BIOS
LISTINGS

Page

Line
Number

.
.
.
.
.
.

A-2
A-2
A-2
A-2
A-5
A-20

12
35
67
76
239
1408

.
.
.
.
.

A-21
A-24
A-34
A-44
A-46

1461
1706
2303
3078
3203

.
.
.
.
.

A-71
A-71
A-77
A-79
A-81

5052
5083
5496
5630
5821

Fixed Disk I/O Interface ................ A-84
Boot Strap Loader ...................... A-89

1
399

System ROM BIOS
Equates ..............................
8088 Interrupt Locations ...............
Stack ................................
Data Areas ...........................
Power-On Self-Test ....................
Boot Strap Loader .....................
I/O Support
Asynchronous Communications
(RS-232C) .........................
Keyboard ..........................
Diskette ............................
Printer .............................
Display ............................
System Configuration Analysis
Memory Size Determination ..........
Equipment Determination .............
Graphics Character Generator ...........
Time of Day ..........................
Print Screen ..........................

Fixed Disk ROM BIOS

System BIOS

A-I

LOC OBJ

LINE

SOURCE
$TITLEIBIOS FOR THE IBN PERSQHAL COMPUTER xTl

1 -- --------- ---- ---- ----- ----- -- ----------. ----------------- -----

THE

BrOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH

SOFTWARE INTERRUPTS ONLY.
THE LISTINGS
NOT FOR

REFERENCE.

ABSOlUTE

ADDRESSES

VIOLATE THE

10

11
12
13

PORT_A

EOU

PORT_B

17

PORT_C

00b3

18

,.

CNO_PORT

EOU
EOU
EOU

INTAOO

"
"

INTAOl

23

0040

24

0001

25

0008

2.

OMA08

0000

27

0540

28

"

30

KBD_IN

31

KBOINT

0040
0043

0410
OObO

0002
0060
0061

21

THE

COMPLETENESS.
REFERENCE

CODE

SEGMENT

ANO DESIGN OF BIOS.

EQUATES

"

0021
0020

WITllIN

------------------- -------- -------------

I.

0020

ONLY FOR

APPLICATIQHS WHICH

• ----- ----- - -------- - - ----- - ---- ------ --;

00b2

15

STRUC~E

ANY ADDRESSES PRESENT IN

i ---------- --------------------------- - ---- ---- --- ---- - ----- -- ---

OObl

OObO

ARE INCLUDED

.,H

.OH

; 8255 PORT A ADOR

.2H
.3H

; 8255 FORT C ADDR

EOU

ZOH

; 8259 PORT

21H

i

TIM_eTL

EOU
EOU
EQU
EOU

TIMERO

EOU

THINT

EOU
EOU
EOU

01

; TIMER 0 INH! RECVD tuSK

00

I DNA STATUS REG PORT ADDR

00

; DMA CH. 0 ADDR. REG PORT ADDR

MAX_PERIO~

EOU

540H

MIN_PERIOD

EOU
EOU

410H
.OH

EOU
EOU
EOU

02
.OH

Eor
TIMER

OMA

i

8255 FORT B AODR

8259 PORT

ZOH
.OH
.3H
,OH

; 8253 TIMER CONTROL PORT ADDR
; 8253 TIMER/CNTER 0 PORT AODR

; KEYBOARD DATA IN ADDR PORT
I KEYBOARD INTR MASK

32

KB_DATA

"3.

KB_CTL

35

,--- ------ --- ------ ---------------- ------

.,H

i KEYBOARD SCAN CODE PORT
; CONTROL BITS FOR KEYBOARD SENSE DATA

36

B088 INTERRUPT LOCATIONS

37

1----------------------- - -- ---------- - ---

3.
39

ABSO

SEGMENT AT 0

0000

.0

oooe

"42

ORG

03

ORG

0008

0014
0014

.5
•7

.8

••50

0074

51

0060

52

0060

53

0078

5.

0078

55

007C

0400
0400
0400

0500
0500
7COO
7COO

ORG

ORG

BYTE
WORD

5*'

.-.

LABEL

••

0040
0074

007C

LABEL

••

0020

0020
0020
0040

LABEL

2*.

WORD

LABEL

WORD

LABEL

DwaRD

lOHII4
LABEL

WORD

IDH*4
LABEL

OR.

DWDRD

5.

DRG

OlFH*4

ORG

400H

INTERRUPT 1 EH

I

5.

DATA_AREA

LABEL

BYTE

DATA_WORD

LABEL

WORD

••
65

••

ORG
HFG_ TEST_RTN
DRG
BOOT_LOCN
ABSO

I ABSOLUTE LOCATION OF DATA SEGMENT

0500H
LABEL

FAR

7eOOH
LABEL

FAR

ENDS

67

• ---- ---------- ---- --------- ___ --- ______________ _

6e.

; STACK -- USED DURING INITIALIZATION ONLY

69

i ------ --- ------------------------------ ________ _

70
71

STACK

0000 1128

0100

SEGMEIH AT 30H
OW

128 DUPI? J

,",ORO

73

TOS

LABEL

74

STACK

ENDS

75

76

1----------------------------------------

77

A-2

LOCATION OF POINTER

I POINTER TO EXTENSION

60

.2
.3

ENTRY POINT FOR CASSETIE BASIC

WORD

01EH!'i4

57
5.

.,

; POINTER TO VIDEO PARMS

18H*4
LABEL

System BIOS

ROM BIOS DATA AREAS

LOC OBJ

LINE
78

SOURCE
;

-- --------------------------------------

7'

eo

DATA

81

RS232_BASE

DW

4 DUP!?)

;

0008 (4

82

PRIHTER_BASE

DW

4 OUP!?)

I ADDRESSES OF PRINTERS

0010 ????

83

EG/UIPJLAG

0012 ?1

84

MFG_TST

OW
OB

I IHITIALIZA lION flAG

????
0015 ??
0016 ??

85

MEMORY_SIZE

OW

I MEMORY SIZE IN K BYTES

8.

HFG_ERR_FLAG

DB

I SCRATCHPAD FOR MANUFACTlJIUNG

DB

I ERROR CODES

0000 (4

SEGMENT AT 40H
ADDRESSES Of RSZ32: ADAPTERS

????

....

0013

87

; INSTALLED HA.RDWARE

8B
8'
.0

1----------- -------------- -- ---------- --KEYBOARD DATA AREAS

------ -- -- ---------------------------

91
92
0017 ??

"
••

KBJlAG

DB

.4
OS

0050

0040
0020

.7
98

••

1----- SHIFT FLAG EQUATES WITHIN KB_FUG
INS_STATE
CAPS_STATE
HUM_STATE

SCROll_STATE

I INSERT STATE IS ACTIVE

EOU
EQU

8DH
4DH

I CAPS LOCK STATE HAS BEEN TOGGLED

EOU
EOU
EOU
EOU

20H

I tU1 LOCK STATE HAS BEEN TOGGLED

0010

lDO

0008

101

ALT_SHIFT

0004

102

eTL_SHIFT

0002

103

LEFT_SHIFT

0001

lD4

RIGHT_SHIFT

EOU
EOU

IOH

; SCROLL LOCK STATE HAS BEEN TOGGLED

OSH

I ALTERNATE SHIFT KEY DEPRESSED

D4H

; CONTROL SHIFT KEY DEPRESSED

D2H

I

D1H

; RIGHT SHIFT KEY DEPRESSED

LEFT SHIFT KEY DEPRESSED

105

??

; SECOND eYTE OF KEYBOARD STArus

KBJLAG_l

DB

0080

ID8

INS_SHIFT

INSERT KEY IS DEPRESSED

ID'
110

CAPS_SHIFT

80H
40H

;

0040

;

CAPS LOCK KEY IS DEPRESSED

20H

; NUt1 LOCK KEY IS DEPRESSED

SCROLL_SHIFT

EOU
EOU
EOU
EQU

IOH

I SCROLL LOCK KEY IS DEPRESSED

HOLD_STATE

EOU

08H

I SUSPEND KEY HAS BEEN TOGGLED

114

AlT_INPUT

DB

j

0018

lD6
107

OOZO
0010
0008

III
112

WN_SHIFT

113

??
001A ????
ODIC ????

115

BUFFER_HEAD

OW

I POINTER TO HEAD OF KEYBOARD BUFFER

11.

BUFFER_TAIL

OW

I

POINTER TO TAIL OF KEYBOARD BUFFER

ODIE (16

117

KB_BUFFER

OW

i

ROOM fOR IS ENTRIES

116

KB_BUFFER_EI'O

0019

16 DUP(?)

STORAGE FOR ALTERNATE KEYPAD ENTRY

....
DOlE

LABEL

WORD

11'

"0

1------ HEAD

0045

"2

'"

HUt1JEY

OD . .

"3

SCROLL_KEY

0036
0010
OOlA

OOZA
0036
0052
0053

"4

ALT_KEY

"5

CTlJEY

".
127

LEFT]EY

"8

RIGHT_KEY

12.

INS]EY

130

DEL_KEY

131

.9

; SCAN CODE FOR HUMBER LOCK

7D

I SCROLL LOCK KEY

56

; ALTERNATE SHIfT KEY SCAN CODE

2.

I SCAN CODE fOR CONTROL KEY

56

I SCAN CODE FOR SHIFT LOCK
SCAN CODE FOR lEFT SHIFT

42

j

54

I SCAN CODE FOR RIGHT SHIFT

82

; SCAN CODE fOR INSERT KEY
; SCAN CODE FOR DELETE KEY

B3

134
135

SEEK....SnTUS

133

??

EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU

INDICATES THAT THE BUFFER IS EI1PTY

---------------------------- -----------DISKETTE DATA AREAS
; --------------------- -------------------

132

OOlE

CAPS_KEY

= TAIL

;

DB

I DRIVE RECALIBRATION STATUS

= DRIVE

3-0 NEEDS RECAl

13.

; BIT 3-0

137

I BHORE NEXT SEEK IF BIT IS

=0

136
0080
003F

??

13'
140

INT_FlAG
HOTOR_STATUS

EOU
DB

080H

; INTERRUPT OCCURRENCE FLAG
I HOTOR STATUS

141

I BIT 3-D

142

I

143
144

;

= DRIve

3-0 IS CURRENTLY

RUNNING
BIT 7

= CURRENT

OPERATION IS A WRITE.

REQUIRES DEu'Y

145
0040 ??
0025

146

HOTOR_COUNT

147

MOTOR_WAIT

DB
EQU

I TIME OUT COUNTER FOR DRIVE TURN OFF

37

; .2 SECS OF COUNTS FOR HOTOR TURN OFF

148

System BIOS

A-3

LOC OBJ
0041 ??
0080
0040
0020
0010
0009
000&

0004
0003

0002
0001
0042 17

..

LINE
14.

SOURCE
DISKETIE_STAlUS DB

I RETlIRN CODE 51 .... TIJS BYTE

150

TIME_OUT

EQU

60H

151
152

BAD_SEEK

E..,

40H

I SEEK OPERATION FAILED

BAD_NEC

E..,

; NEC CONTROLLER HAS FAILED

153
154

BAD_CRC

20H
10H

OHA_BOUNDARY

EQU

ATTEMPT TO OMA ACROSS 64K BOl.lt«)ARY

BAD_DMA

E..,

O'H
.6H

j

155
156
157

j

DHA OVERRUN ON OPERATION

RECORD_HOTJND

EOU

'4H

I REQUESTED SECTOR NOT FOLtm

~ITE_PROTECT

EQU

156

BAD_AOOR_HARK

EOU

j

I BAD COMMAND PASSED TO DISKETTE I/O

j

IS'
I ••

,.,

EOU

j

j

.3H

BAD_tHO

EOU

OZH
OIH

NEC_STATUS

DB

7 DUP(?)

ATTACHMENT FAILED TO RESPOt&J

BAD CRe ON DISKETTE READ

; WRITE ATTEMPTED ON

~ITE

PROT DISK

ADDRESS MARK NOT FOUND

STATUS BYTES FROM NEC

,.2
163

; ----------------- ------------- ----------

164

VIDEO DISPLAY DATA AREA.

165

1--------------- ------------------------C~RENT

I ••

CRT_HOOE

DB

I

167

,.6

CRT_COlS

ow

CRT_LEN

OW

,

LENGTH OF REGEN IN BHES

16.
170

CRT_START

ow
ow

j

STARTING ADDRESS IN REGEN BUFFER

0050 (6

0060 ????

171

CURSOR_HODE

ow

j

006t ??

172

ACTIVE_PAGE

DB

; CURRENT PAGE BEING DISPLAYED

0063 ????

173
174
175
17.

AOOR_6845

ow

j

8ASE ADORESS FOR ACTIVE DISPLAY CARD

CRT_MODE_SET

DB

i

CURRENT SETTING OF THE 3X8 REGISTER

CRT_PALETTE

DB

; CURRENT PAlETTE SETTING COLOR CARD

0049 11
004.\

????

004C ?'?'??
004E ????

0065 ??
006b ??

177

CURSOR_POSN

CRT HODE

; NUMBER OF COLUMNS ON SCREEN

8 DUP{?)

; CURSOR FOR EACH OF UP TO 8 PAGES

CURRENT CURSOR MODE SETTING

;----------------------------------------

176

POST DATA AREA.

179

i ----------------------------------------

0067 n'??

ISO

IO_ROM_INlT

161

IO_ROM_SEG

ow
ow

I PNTR TO OPTIONAL 110 ROM INIT ROUTINE

0069 ????
0068 ??

162

INTRJLAG

DB

; FLAG TO INDICATE AN INTERRUPT HAPPEND

; POINTER TO IO ROM SEGMENT

163
184

i ----------------------- -----------------

185

006C ????

TIMER DATA. AREA

166

; ----- -----------------------------------

167

TIMER - LOW

LOW WORD OF TIMEI<' COllHT

,.6

'W

I

006E ????

TIMER_HIGH

ow

; HIGH WORD OF TIMER COUNT

0070 ??

16.

TIMER_OFL

DB

'"

J COUNTS_SEC

EOU

191

J COUNTS_MIN

EOU

16
1092:

192

,.3

,

COUNTS_HOUR

E,,"

65543

COUNTS_DAY

EOU

1573040

195

1---------- -------- --------- ---------- ---

"4

196

197
0071 ??

0072 ????

=

1600BOH

SYSTEH DATA AREA
i ----------------------------- -----------

,.6
,.9

BIOS_BREAK

DB

I BIT 7=1 IF BREAK KEY HAS BEEN HIT

RESETJLAG

ow

I WORD=lZ34H IF KEYBOARD RESET UNDERWAY

200

i --------------------------- -------------

201

2.02.

0074 ????
0076 ????

; TIMER HAS ROLLED OVER SINCE lAST READ

FIXED DISK DATA AREAS

; ------------ ------ --------- --- ----------

ow
ow

203
204
205

1------------ ------------------------------ ------------

2.06

PRINTEI<' ANO RS232 TIME-OUT VARIABLES

207
2.6

i ---------- --------------------------------------------

0078 (4

007C (4

20'

40UP(?)

0080 ????
0082 ????

4DUP(?1

210
HI

; --------------------------- -------------

212
213

; ------------------ --------- -------------

ADDITIONAL KEYBOAI<'D DATA AREA
BUFFER_STAI<'T

OW

214

BUFFER_END

DW

215

DATA

216

1----------------------------------------

217
218

A-4

Et-mS
EXTRA DATA AREA

; ----------------------------------------

System BIOS

LOC OBJ

0000 ??

LINE

SOURCE

".

XXDATA

221

XXDATA

'"

222

0000 (16364

YIDEO DISPLAY BUFFER

224

1---------------------___ ---------- ------

Z25

VIDEO_RAM

SEGMENT AT DeaDaH

ZZ6

REGEN

LASE L

BYTE

ZZ7

REGENW

LABEl

WORD

DB

16384 DUP(?)

"8
zz.

230
231

ENDS

1--------------------____ ------------___ _

232

ROM RESIDENT COOE
,------------------- ____________________ •

233

COOE

0000 (57344

EOOO 31353031353132

DB

ENDS

1----------------------------------------

223

0000
0000

SEGMENT AT SOH

STATUS_BYTE

Zl'
Zl6

SEGMENT AT OFOOOH
DB

57344 DUP(? I

DB

'1501512 eOPR. IBM 1981'

; FILL LOWEST 56K

I COPYRIGHT NOTICE

20434FS0522E20

49424020313938

"

"7
"8

2:39

1---------------------------------------________ _

240
241

INITIAL RELIABILITY TESTS -- PHASE 1
; ------------------------- ______________________ _

242

'"3
'44
245

ASSL/J"IE

246
247
248
E016 07EO

E018 7EEl

CS:COOE .SS:CODE, ES:ABSO ,os :OATA

1-----------------------________________ _
DATA DEFINITIONS
i ---------------------------------------_

Z4,

el

250

ez

ow
ow

I RETURN ADDRESS

I RETURN ADDRESS FOR DUMMY STACK

'51
fCU. 204B42204F48
E020 00

252

FlB

, KB 01<',13

DB

1 KB FOR MEMORY SIZE

253
254

i -------.-------------------------------------------------------------

255

LOAD A BLOCK OF TEST CODE THROUGH THE KEYBOARD PORT

256

F~

257

THIS ROUTINE WILL lOAD A TEST (I'IAX lENGTH=FAFFH) THROUGH

258

THE KEYBOARD PORT. CODE WILL BE LOADED AT LOCATION

259

I1ANUFACTUING TEST.

260

DODO: 0500. AFTER LOADING, CotITROL WILL BE TRANSFERED
TO LOCATION 0000:0500. STACK WIll BE lOCATED JUST BELOW

261

THE TEST CODE. THIS ROUTINE ASSut1ES THAT THE FRIST 2:
BYTES TRANSFER ED CONTAIN THE COUNT OF BYTES TO BE LOADED

262
263
264

{BYTE I=COUtIT LOW. BYTE 2=COUNT HI.)
1---------------------------------------------------------------------

Z65

266

1----- FIRST, GET THE COUNT

Z67

fOU

feu

'68
ESHlA

E024 SAFB

E026 E80ElA

MF6_Boon

26.

CAll

SP_TEST

Z70
Z71
27Z

MOV

SH.al

CALL

SP_TEST
CH.Bl

'73

MOV
MOV

f02D Fe::

Z74

E02E FA

Z7.

elD
ell

E029 BAfB
E02B BACF

Cl,BH

I GET COlM" lOW
I SAVE IT
; GET COUNT HI
.I ex tiOW HAS COUNT

I SET DIlL FLAG TO INCRIHENT

Z76
Z77

MOV
I10V

DI.OSOOH

I SET TARGET OFFSET (05=0000)

f032 BOFD

278

OUT

Al.ofDH
INTAOl,Al

I UNt1ASK 'VB INTERRUPT

E034 E621

Z7.

I10V
OUT
MOV

AL,OA.H

.I SEND READ INT. REQUEST REG. CHD

DX,blH

I SET UP PORT B ADDRESS

I10V

BX,4CCCH

I CONTROL BITS FOR PORT B

MOV

AH,02H

I K/B REqUEST PEt-ilING MASK

EOlF BFOOOS

E036 aOOA

E038 E620

E03A 8"6100
f03D B8CC4C

'.0
2.,

2.,

INTAOO,Al

E040 8402
[042

,"3

E042 BAC!

285

HOV

Al,Sl

'86

OUT

DX,Al

E044

~E

Z84

1ST:
I TOGGLE K/B CLOCK

System BIOS A-5

LDC DBJ

LINE

E04-S SAC7

,
,..

SOURCE

..

E047 EE

f048 4"
E049

,a7

MOV

Al.BH

2.0

OUT
OEe

ox

,.1
2.,

E049 E420

f048 22C4
f040 74FA
E04F EC
E050 AA

AL,lNTAoa

Al,AH

; KB REQUEST PENDING?

JZ

TST!

; LOOP TILL DATA PRESENT

IN

AL.DX

STOSB

E052 E2EE

207

; GET IRR REG

IN

ANO

20S

29.

I POINT OX AT AODR. 60 (KB DATA)

TSTl:

20'
204

E051 42

OX.Al

l GET OA.TA

1 STORE IT

INC

ox

; POINT OX BACK AT PORT B (61)

LOOP

TST

;

LOOP TILL ALL BYTES READ

2 ••

E054 E"00050000

2.0

JMP

; FAR JUMP TO CODE THAT WAS JUST

3D.

I

301
302:
303
304

; ------------ ---------------------------8088 PROCESSOR TEST
~

DESCRIPTION
VERIFY 6088 FLAGS, REGISTERS

305

306
307
30.

AND CONDITIONAL JUMPS
; ------ -- ---- -- -- ------ --- ------ -- - -- ---ASSUME

CS: CODE ,OS; NOTHING. ES :NOTHING .SS:NOTHING

E056

300

ORG

OE05BH

Eose

310

RESET

LABEL

FAR

'11

START:

CLI

E056 FA

EOSC B4D5
EOSE 9E

LOADED

312

MOV

313

SAHF

i

DISABLE INTERRUPTS

AH.005H

; SET SF. CF. ZF. AND AF FLAGS ON

314

JNC

ERROl

; GO TO ERR ROUTINE IF CF NOT SET

f061 754A

31S

JNZ

ERROl

; GO TO ERR ROUTINE IF ZF NOT SET

E063 7648

31.
317
31.
31.

JNP

ERROl

; GO TO ERR ROUTINE IF PF HOT SET

JNS

ERROl

; GO TO ERR ROUTINE IF SF NOT SET

LAHF
MOV

CL,S

; LOAD CNT REG WIlli SHIFT CNT

fObA OlEC

320

SHR

AH,CL

; SHIFT Af INTO CARRY BIT POS

f06C 733F

321

JNC

ERROl

; GO TO ERR ROUTINE IF AF NOT SET

HOV

AL.40H
AL.l

; SETUP FOR TESTING

ERROl

I GO TO ERR ROUTINE IF OF HOT SET

EOSF 734C

f065 7946
fD67 9F

f068 BI05

32.

E06E 8040
E070 ODED

E072 7139

'"

SHt

324

JNO

E074 32E4

32S

XOR

32.

SAHF

f076 9E

E077 7634

327
32.

".
"I

E078 7A30
E07D 9F

f07E B105

AH.AH

; SET AH ::: 0

JBE

ERRO 1

; GO TO ERR ROUTINE IF CF ON

JS

ERROl

i

JP

ERROl

; GO TO ERR ROUTINE IF PF ON

i CLEAR SF. CF, ZF. AND PF

;

LOAD F LAG IMAGE TO AH

n.s

i

LOAD CNT REG WITH SHIFT CNT

SHR

AH ,CL

; SHIFT

334

JC

ERROl

; GO TO ERR ROUTINE IF ON

33S

SHL

AH,I

i CHECK TtlAT

JO

ERROl

; GO TO ERR ROUTINE IF OH

332
333

E082 7229
E084 DOEct

LAHF

GO TO ERR ROUTINE IF SF ON

Mav

ED8D 02EC

33.

E086 70::':5

; SET THE OF FLAG ON

; GO TO ERR ROUTINE IF ZF ON

32.

E079 7832-

; LOAD FLAG IMAGE TO AH

AF' INTO CARRY BIT pas
OF' IS CLEAR

337
338

f088 B8FFFF

E086 F9

WITH ALL ONE'S AHO ZEROES'S.

'40
341

I10V

AX.OFFFFH

I SEruP ONE'S PATTERN IN AX

MaV

OS.AX

; WRITE PATTERN TO ALL REGS

344

MaV

BX,DS

'4S

I10V

ES,BX

MOV

CX,ES

MaV

SS,CX

Eoac 8E08

'42
343

EOSE eCCB
E090 8EC3

EOn 8CCI
E094 8E01

;----- REAO/WRITE THE 8088 GENERAL AND SEGMENTATION REGISTERS

339

5TC
C8:

'4.
347

E098 8BE2:

348
340

I10V

SP,OX

E09A 8BEe

35.

MOV

BP,SP

MOV

SI,BP

MOV

DI,SI

E096 8C02

E09C BaFS

MOV

OX,SS

f09E SBFE

351
352

fOAO 7307

'53

JNC

EOA2: 33e7

354

XOR

AX.DI

I PATTERN MAKE IT THRU ALL REGS

EOA4 7507

35S

JNZ

ERROl

I NO - GO TO ERR ROUTINE

EOA6 Fa

35.

EOA7 fBEl

'57

EOA9

358
35.

C9:

36'

ERROl:

362

i -------- --------------------------------

[OA9 OBC7
EDAB 7401

EOAD F4

'.0

i

TsnA

eLe

363

A-6

C9

System BIOS

JMP

C8

OR

AX,DI

JZ

CIO

I TSTU

HLT
ROS CHECKSUM TEST I

I ZERO PATTERN MAKE IT THRU,?
I YES - 60 TO NEXT TEST
; HALT SYSTEM

LINE

SOURCE
J DESCRIPTION
A CHECKSUH IS DnNE FOR mE 8K
ROS HOOULE CONTAINING POD .tJ.I)
BIOS.

E082: BADSn

3••
36S
3••
3.7
368
36.
370
371
37.
371

£OB5 EE

'70

OUT

E086 FEeo
[OBA EE

37.
37.
377

Eoee 8089

"8

INC
HOV
OUT
HOV

LOC OBJ

EOAE
EOAE EUO
EOBO E683

E088 82M

EoeD £663

EOBF BOAS
EOCI E661

EOC3 B001
EOtS £660

EOC1 Btn
EOC9 eEOO

EOCB SEDS,

;

-- --------------------------------------

CIO:
OUT

OAOH,AL

CUT

831ItAL
DX,3118H
DX,AL

MOV

..

,".

CUT

3.1
3.2
,.3
3••

I ZERO IN AL ALREADY
I DISABLE tf11 INTERRUP:rs
I IHITIALZE DHA PAGE REG.
I DISABLE COLOR VIDEO

AL
DL.DBSH

DX,Al

I DISABLE BIN VIDEO. EN HIGH RES
; SET 8255 FOR B I A=OUT, C=IN

AL.89H

CI1D_PORT,AL

HOV

AL,lOlOOlOlB

CUT

PORT_B.AL

HOV

AL.OIH
PORT_A.Al

I <><><><><><><><><><><><>

Ax.es

I SETUP 5S seG REG

I ENABLE PARITY CHECKERS AND

..

; PULL KB CLOCK HI, TRI-STATE

I KEYBOARD INPUTS. ENABLE HIGH

,

I BAt« OF SIoIITCHE5->PORT C(o-3)

386
3.7
3••
3••

CUT
tIOV
HOV
HOV

DS,AX

391

CLD
ASSUf1E
MOV
MOV
JMP
JNE

SS:CODE
BX,OEOOOH
SP.OFFSET Cl
ROS_CHECKSU1
ERROl

I <><><>CHECKPOINT 1<><><>

55.AX
i SET UP DATA SEG TO POINT TO

39.
EOCD FC
EOCE
EODl
E004
E007

BBOOEO
BC16EO
E91B18
7504

....
....
....•••,,
•••
3"
3'3

,
,
,.,
,
,
3••

•• 1

•••

Cll:

J ROM ADDRESS
I SET DIRECTION FLAG TO INC.

I SETUP STARTING RDS ADDR
; SETUP RETURN ADDRESS
; HALT SYSTEM IF ERRDR

1------------ ---- -- ------------------------ ------- -- -- --8237 DMA INI:TIALIZATION CH.u..!EL REGISTER TEST
i DESCRIPTION
DISABLE THE 8237 DttA CONTROLLER. VERIFY THAT
TII1ER 1 FlJiCTIONS OK. WRITEIREAD THE CLJ;!RENT
"'DDRESS ,AND WORD COUNT REGISTERS FOR AlL
CHA!+IELS. INITIALIZE AtIJ START OHA FOR MEMORY
REFRESH •
j ---- - - -- -- --- ---- -- -- -- - ----- ------------- --------------

4 ••

•• 7
[009
Eooa
EOOO
EODF

B002
£660
8004
E608

EOEl
EOEl
EOE5
EO£7
EO£9
EOE9
EOE8
EOED
EOFO

B054
E643
SACI
E641

EOF2
[OF4
£OF6
EOFS
EOF9
EOF9
EOFe
EOFD'
(OFF
(OFF
ElOl
n03
E104
E105
EI07
EI09

E"l
0...08
E2Fl
F4

B040
E643
eOFBFF
7407

eAC3
2BC9
£641
B040
E643
90
90
£441
2208
7403

•••
•••

j-----

DISABLE DMA CONTROLLER
HOY

.1.

OUT

'11
.1.
413
.1.

tIOV
CUT

i-----

'1'
.1.
'17
.1.
.1.

...
...
...•••

OUT
HOV
OUT
CHP
JE
IN
OR
LOOP

423
4.4

.27

."
."

tIOV

4"
.3.
'3'
43.

......
4"
4. .

CUT

t

AL.CL
TII1ER+l.AL

I SET INITIAl TIMER CNT TO 0

AL,40H
TlI1ER+3 .... L
Bl.OFFH

tl3
"'l,TIHER+l
IL.AL

tl'

HCT

.....

tI(

I SEL TII'IER 1.lSB.t1ODE

C13:

431

I DISABLE DtIA CONTROLLER

AL • .54H
TII1ER+3,AL

C12~

'21

...•••

VERIFY THAT TIMER 1 FlJIICTIONS
HOV
CUT
HOV

I <><><><><><><><><><><><>
, <><><>CHECKPOINT 2<><><>

AL,oZH
PORT_A.AL
AL.04
DMAOS.AL

AL.Bt
CX,CX
TIMER+l,AL

C11t:

I TlI1ERl_BITS_ON
I LATCH TlHER 1 CotIIT
; YES - SEE IF ALL BITS GO OFF
i TIHERl_BITS_OFF
J READ TIMER 1 CCMMT
1 ALL BITS ON IN TII1ER!
I TlI1ER!l_BITS_ON
I TIMER 1 FAILURE, HALT SYS
I TIKERl_BITS_DFF
J SET TIMER 1 CNT

J TIKER_LOOP

I10V
CUT
NOP
NOP
IN
ANa
JZ

AL.Q.OH
TIHER+3 "t,L

i

UTCH TIMER 1 COUNT

1 DELAY FOR TIMER
Al.TIMER+!
BL.AL

J READ TIMER 1 COUNT

tl.

i WRAP_DHA..R!EG

System BIOS A-7

LOC OBJ

LINE

SOURCE

HOB E2F2

441

lOOP

E100 F4

442

HLT

C14

I

TIMER_LOOP

I HALT SYSTEM

443
444

;----- INITIALIZE TIMER 1 TO REFRESH MEMORY

445
flOE B003

446

NOV

AL,03H

i

EllO E660

447
448

OUT

PORT_A,AL

i

El12 E600

44.

OUT

ONA+DOH .Al

CI5:

<><><><><><><><><><>
<><><>CHECKPOINT 3<><><>

I WRAP _DNA_REG
i SEND MASTER CLEAR TO DNA

450
451

; ----- WRAP DNA CHANNELS ADDRESS ANO COUNT REGISTERS

452
E114 BOFf

453

f116 SACS
EllS SAF8

454

t16:

455

EllA 890800

456

EllD 8AOOOO
El20 EE

'57
45.

El21 50

459

CI7:

NOV

AL,OfFH

i

NOV

BL,Al

i SAVE PATTERN FOR COMPARE

MOV

BH,AL

NOV

ex,s

NOV

aX.OM

I SETUP I/O PORT ADOR OF REG

OUT
PUSH

OX,Al
AX

I SATlSIFY 8237 110 TIMINGS

El22 EE

.60

OUT

aX,AL

E123 eOOl

461

NOV

Al,OlH

El2S EC

'62
463

IN

Al,DX

El26 8AEO

WRITE PATTERH FF TO ALL REGS

NOV

J SETUP LOOP CNT
i WRITE PATTERN TO REG

I

LSB

NS8 OF 16 BIT REG
At. TO ANOTHER PAT BEFORE RO
I READ I6-BIT DIiA CH REG. L5B

AH.AL

SAVE LSB OF lo-BIT REG

E128 EC

464

IN

AL,OX

; READ MSB OF OMA CH REG

£129 3B08

465

CH"

eX,AX

; PATTERN READ AS WRITTEN?

El2B 7401

466

JE

C18

El20 F4

467

El2E

4.8

E12E 42

46.

INC

OX

; SET I/O PORT TO NEXT CH REG

E12F E2EF

470

lOOP

C17

; WRITE PATTERN TO NEXT REG

E131 FEtO

471

INC

AL

; SET PATTERN TO 0

.n

JZ

C16

I WRITE TO CHANNEL REGS

E133 74El

HLT

J YES - CHECK NEXT REG

; NO - HALT THE SYSTEI1

CIS:

; NXT_OHA_CH

.73
• 74

;----- INITIALIZE AND START OI1A FOR I1EMORY REFRESH .

475

oS,ex

E135 eEes

476

MOV

El37 8EC3

477

NOV

ES,BX

47.

ASSUME

DS:ABSO, ES :ABSO

El39 BOFF

47.

MOV

.l.l,OFFH

EI3B E601

480

OUT

OMA+I,Al

EnD 50

.81

PUSH

AX

EI3E E601

OUT

1 5ET UP ABSO INTO OS AND ES

I SET CNT OF 64K FOR REFRESH

CNA+I,Al

E140 BOS8

'82
463

NOV

Al,058H

I SET OMA MODE,CH Q,RD.,AUOTINT

EI42 E60B

464

OUT

DI1A+OBH,AL

; WRITE DMA MODE REG

El44 BODO

4B5

NOV

AL,O

I ENABLE DMA CONTROLLER

El46 8AE8

466

NOV

CH,AL

; SET COUNT HIGH:::OO

El48 E608

467

OUT

DMA+8,AL

; SETUP 011A COMMAND REG

E14A 50

488

PUSH

AX

El4B E60A

4 ••

I ENABLE OMA CH 0

490

OUT
NOV

CMA+I0,Al

E140 8012

Al.18

; START TIMER 1

491

OUT

TIMEIHl,AL

492

NOV

Al,41H

OUT

OHA+OBH.AL

..,

E14F E641
Elsl B041
EI53 E60B

•• 4

; SET MODE FOR CHANNEL I

PUSH

AX

ElS6 £408

4.5

IH

AL,OMA ... 08

I GET DNA STATUS

ElSa 2410

49.

AHO

AL,OOOlOOOOB
C18C

,

El55 50

EISA 7401

4.7

JZ

EISC F4

4 ••

HLT

•••

E150 8042

else:

HOV

Al.42H

{IT SHOULD'T BEl

, SET MODE FOR CHAt-tNEl 2

OMA+OBH,AL

500

OUT

E161 8043

501

NOV

AL.43H

El63 f608

502

OUT

DMA+OBH.AL

E1SF E60B

J IS TIMER REQUEST THERE?

I HALT SYS.(HOT TIMER 1 OUTPUll

I SET MODE FOR CHAICHECKPOINT 4<><><>

SUB

CX,CX

; BASE RAM FAILURE -

; SAVE FAILING BIT PATTERN

<><><><><><><><><><><><>
HANG

LOOP

C24B

; flIPPING BETWEEN 04 A.ND

XCHG

BL,AL

I FAILING BIT PATTERN

JMP

C24A

E18E

531

E18E 2BCO

532

SUB

AX,AX

; MAKE AX=DOOO

£190 F3

533

REP

STOSW

I STORE 6K WORDS OF DODO

OATA_WORD[OFFSET RESET]LAGJ,BX ;. RESTORE RESET flAG

£191 A6
HOW_BIG:

fl92

53.

fIn 891£72:04

535

HOV

£196 BAO004

53.
537

HOV

DX,0400H

; SET POINTER TO JUST>16KB

HOV

eX,16

; BASIC COUNT OF 16K
; SET SEG_ REG_

£199 B81000
fl9C
E19C 8EC2

".

FILL_lOOP:

53.

HOV

ES,DX

£19£ 2BFF

540

SUB

01,01

£IAO 8855.6.A

541

HOV

AX.OAA5SH

; TEST PATTERN

flA3 88C8

54'
543

HOV
HOV

eX.AX

;. SAVE PATTERN

ES: [01 I,AX

j

SEND PATTERN TO MEM_

544
545

HOV

AL,OFH

I

PUT SOMETHING IN Al

flAA 268B05

HOV

AX,ES:[OIl

; GET PATTERN

ElAD 33Cl
ElAF 7511

54.
547

XOR

AX.CX

; COMPARE PATTERNS

JHZ

HOW_BIG_Et--Il

;. GO END IF NO COMPARE

£IBl 890020

54.
54.

HOV

CX,2000H

; SET COUNT FOR 8K WORDS

REP

STaSio!

I FILL 8K WORDS

ElBb 81C20004

550

DX.400H

ElBA 83C310

551

ADD
ADD

BX,16

; BlR1P COUNT BY 16K8

CHP

OH,OAOH

; TOP OF RAM AREA YET?

JHZ

FILL_LOOP

EIA5 268905
flAB BOOF

ElB4 F3
f185 AB

EIBD BOFEAD

5"

EICO 750A

553
554
555
55.

£ltZ
EIC2 891£1304

557

POINT TO NEXT 16KB BLOCK
(AOOOO)

HOW_BIG_END :

HOV

;. SA.VE MEHORY SIZE

; ----- SETUP STACK SEG AND SP

55.
E It6 B83000
ElC9 8EoO

flce 8COODl

559
5.0

5.,

562

AX.STACK

, GET STACK VALUE

HOV

SS,A.X

, SET THE STACK UP

HOV

SP.OFFSET TOS

I STACK 15 REAOY TO GO

1-------- ------------------------------------------- ----INITIALIZE THE 8259 INTERRUPT CONTROLLER CHIP

563

flCE 6013

HOV

564

;. --------- ---------- --- ----- ------------------------ -----

565

C25:

HOV

AL.13H

f100 E620

5 ••

OUT

INnOD ,AL

£102 8008

5.7

HOV

AL.e:

flDft £621
E106 B009

568

OUT

INTA01.,l,l

HOV

AL.9

EIDB £621
fIDA BOFF
EIOC E621

5.'

; ICWI - EDGE, SNGL, leW,.

I SETUP lCIoI2 .- INT TYPE 8 (8-F)

; SETUP lew. - BUFFRD ,8066 HOOE

570

OUT

INTAOl,AL

571

HOV

Al,OFFH

; MASK AlL INTS. OFF

5n

OUT

INTAOl.AL

; (VIDEO ROUTINE ENABLES INTS.I

573
574

;----- SET UP THE INTERRUPT VECTORS TO TEMP INTERRUPT

575

flOE IE

576

PUSH

OS

fIDF B92000

577

MOV

eX,32

; FILL ALL 32 INTERRUPTS

E1E2 2BFF

57'
579
5.0

SUB
HOV

01.01

; FIRST INTERRUPT LOCATION

EStDl

; SET ES=OOOO ALSO

MOV

AX,OFFSET 011

• MOVE ADDR OF INTR !'ROC TO TBL

Ax.es

I GET AODR OF INTR PROC SEG

03

i VECTBLO

£1£4 8EC7

fl£6 8823FF
EIE9 AB

EIEA ecce
EIEe As
ElED ElF7

5.'
5.,

5'3
584
585
586

03:

STOSW

NOV
STOSW
LOOP

;----- ESTABLISH BIOS SUBROUTINE CALL INTERRUPT VECTORS

5.7

ElEF BF4000
EIF2 DE
EIFJ IF
EIF4

ecoe

ElF6 BE03FF90

58'
58'
5.0

5.,

5.,

MOV

DI.OFFSET VIDEO_INT

PUSH

es

POP

os

; SETUP ADOR Of VECTOR TABLE

MaV

AX,OS

I SET AX=SEGHENT

HOV

5I.OFFSET VECTOR_TABlE+16

; SETUP ADDR TO INTR AR EA

; START WITH VIDEO ENTRY

System BIOS

A-9

LOC OBJ

LINE

Elf A B91000

593

ElFD AS

5.4

SOURCE
HOV
03":

CX,16

HOVSW

; MOVE VECTOR TABLE TO RAM

EIFE 47

>95

INC

01

EIFF 47

5.6

INC

01

E200 EZfB

5?7

LOOP

D3.A.

598

; ----------- ---- ------------- - - ------------------

599
600

; SKIP SEGHENT POINTER

DETERMINE CONFIGURATION AND MFG. MODE
; ------ --- ------- --------- --- ------------- -------

601

E202 IF

POP

OS

PUSH

OS

; RECOVER DATA SEG

IN

AL.PORT~C

; GET SWITCH INFO

AND

AL.OOOOlllIB

; ISOLATE SWITCHES

HOV

AH,AL

; SAVE

b07

HOV

ALolOIOllOiB

; ENABLE OTHER BANK OF SHS.

608

OUT

PORT~B.AL

EZOE 90

b09

NOP

[204 E462

b"
b03
604

E206 2.40F

b05

E208 8AEO

60b

E20A BOAD

HOC E661

EZ:03 IE

ElOF E462

blO

IN

E211 8104

bll

MOY

Cl.4

E213 02eo

612
6\3

ROl

.U.Cl

; ROTATE TO HIGH NIBBLE

ANO

ALollllOOOOB

; ISOLATE

OR

AL.AH

; COMBINE WITH OTHER BANK

E219 2AE4

614
b15

SUB

AH.AH

ElIB .0.31004

b16

MOY

OATA_WORO[OFFSET EQUIPJLAGJ,AX ; SAVE SWITCH INFO

E215 24FO
E217 OAC4

fZlE 6099

617

HOV

H20 E663

bl8
619

OUT

CHO_PORT ,AL

E222 E80518

CALL

KBD_RESET

E225 80FBAA

6"

CHP

BL.OAAH

E228 7418

6"

JE

Eb

E22.A 80FB65

6"

eMP

BL,06SH

E2.20 7503-

623

JNE

03B

JMP

MfG_BOOT

E22F E9EfFD

6"

E232 B038

62:5

HOV

AL.36H

E234 E661

6,6

OUT

PORT_B.AL

E2.36 90

6"
628

HOP

E237 90

03B:

Al.99H

; KEYBOARD PRESENT?

I

LOAD HFG. TEST REQUEST?
GO TO BOOTSTRAP IF SO

HOP

E238 [460

6,.

E23A 24FF

630

ANO

AL.OFFH

EZ3C 7504

631

JNZ

E6

E2.3E FE061204

; SEE IF HfG. JUMPER IN

IN

6"

AL.PORT_A
; WAS OAT.A LINE GROUNDED
; SET MANUFACTURING TEST FLAG

DATA_AREA( OFFSET MFG_TST 1

b"
634

; ----- ----. ---- ------------- ----- ------ ---- -- -------- - ---

635

INITIALIZE AND START CRT CONTROLLER (6645)

636
637

TEST VIDEO READ/WRITE STORAGE.
; DESCRIPTION

636

RESET THE VIDEO ENABLE SIGNAL.
~5.

6J9

SELECT ALPHAHUNERIC MODE. 40 •

640

READ/WRITE DATA PATTERNS TO STG. CHECK STG

641
64~

B & W.

ADDRESSABIlITY.
ERROR :;" 1 LONG AND 2: SHORT BEEPS

643

; -- -- ------ -- -- ----- -------- _. --------------- --- ---- -----

E242

644

E6:

E242 .0.11004

645
646

MOV

AL.30H

E248 .0.31004

6.7
648

MOV
MOV

DATA_WORD[OFFSET EQUIP]LAGI.AX

E246 2AE4

64.

SUB

AH.AH

E24D COlO

650
651

INT

10"

E24f B020

HOV

AL.2:0H

E245 50

E246 B030

PUSH

AX,DATA_WORD (OFfSET EQUIP JLAG 1 I GET SENSE SWITCH INFO
AX

; SAVE IT

, SEti) INIT TO BIW CARD

E251 A31004

652

HOV

E254 2AE4

653

SUB

AH.AH

[256 COlO

654

INT

LOH

E25e 58

Ezse 2430

655
656
657
658

'NIl

AL.30H

; ISOLATE VIDEO SWS

ElSE 750.0.

65'

JHZ

E7

I VIDEO SWS SET TO O?

E260 BF400Q

660

MOV

DI.OFFSET VIDEO_INT

I SET INT lOH TO DUt1t1Y

E2.63 C7054BFF

661

MOV

IDIJ,OFFSET OUtV1Y_RETURN

E267 E9AOOO

662

JHP

E26A

663
b64
665

E259 A31004

E26A 3e30
Ezoe 7408
E26E FEC4

E270 3(20
E272 7502-

E274 8403

A-tO

; AND INIT COLOR CARD

POP

AX

MOV

DATA_WORD(OFFSET EQUIP_FLAG1.AX ; RESTORE IT

I RECOVER REAL SWITCH INFO
I AND CONTINUE

, RETURN IF NO VIDEO CARD
i BYPASS VIDEO TEST

E7:

666
667
668
66.

System BIOS

eHP

Al.30H

I B/It! CARD ATTACHED?

JE

E8

I YES -

SET MODE FOR BIW CARD

INC

AH

eHP

AL,

JHE

E8

I NO - SET MODE FOR 40X25

MOV

AH , 3

I SET HOOE fOR

; SET COLOR MODE FOR COLOR CO
~OH

; 80X25 MODE SELECTED?

aoxts

LaC OBJ

SOURCE

LINE

fa:

; SET_HOOE:

XCHG

AH.AL

PUSH

AX

672

SUB

AH.AH

, INITIALIZE TO ALPHANI.R1ERIC 110

673

INT

10H

; CAll VIDEO_IO

£270 56

674

POP

AX

, RESTORE VIDEO SENSE SWS IN AH

EHE 50

675
676

PUSH

AX

I RESolVE VALUE

E27F B9D060

I10V

Bx.oeOOOH

E282: SABaOl

677

HOV

DX.3BSH

; BEG VIDEO RAM ADOR B/W CD
; MODE REG FOR B/w

E285 890008

678
679

HOV

CX,Z046

; RAM WORD CNT FOR 6/W CO

E288 8001

MOV

Al.1

I SET MODE FOR Bioi CARD

ElBA BOFCJO

680

CNP

AH.30H

, B/W VIDEO CARD ATTACHED?

E2.76 50

670
671

E279 2,0,£4

E278 COlO

EZ7, 86r:O

I SAVE VIDEO MODE ON STACK

E280 7409

681

JE

£9

;

E26F B788

MOV

BH.088H

; BEG VIDEO RAM ADDR COLOR CO

MOV

OX.308H

; MODE REG FOR COLOR CD

E294 6520

68'
683
684

MOV

CH,20H

j

E296 FEte

685

OfC

Al

; SET HODE TD 0 FOR COLOR CD

OUT

OX.AL

J DISABLE VIDEO FOR COLOR CD

eMP

OATA_WORO[OFFSET RESETJUGJ,I2:34H ; POD INlT BY KIID RESET?

E291 8,0,0603

E298

686

E298 EE

.87

E299 813E72043412
E29F 8EC3

E2AI 7407
f2A3 8EDB

f2A5 Efle7Dl

£2A8 7546

E9:

.8.

RAM WORD CtIT FOR COLOR CD

; TEST_VIDEO_STS:

6.9

HOV

ES.BX

; POINT ES TO VIDEO RAH STS

6'0
691

JE

E10

I

.,

MOV

OS,BX

, POINT OS TO VIDEO RAM STG

.93

CAll

STGTST_CNT

; GO TEST VIDEO R/W STG

6.4

JNE

E17

; RIN 5TG FAILURE .. BEEP SPK

.

695
696

ASSUHE

YES - SKIP VIDEO RAM TEST

DS:NOntING,ES:NOTHING

; ---- --- ---------------------------------- ------SETUP VIDEO DATA ON SCREEN FOR VIDEO

697
696

LINE TEST.
; DESCRIPTION

699

ENABLE VIDEO SIGNAL At.[! SET HOOE.

700

f2A ...

YES - GO TEST VIDEO STG

DISPLAY A HOOIZONTAL BAR ON SCREEN.

----------------------------------------- -------

701

;

702

EIO:

AX

, GET VIDEO SENSE SWS (AH)

flAB 50

704

PUSH

AX

; SAVE IT

EZAC 6400

705

HOV

AH.O

; ENABLE VIDEO AND SET MOOE

E2AE COlO

70.

INT

10H

, VIDEO

707

HOV

AX,7020H

I

SHORT EIDA

E2AA 58

703

E260 682070

POP

~T

BLANKS IN REVERSE VIDEO

70.
709
710
E253 EBII

711

JMP

E2C3

712

ORG

OE2:C3H

E2C3 E99915

713

JMP

NHI_INT

SUB

01.01

; SETUP STARTING LOC

MOV

CX,40

; NO. OF BLANKS TO DISPLAY

REP

STOSIo!

I WRITE VIDEO STORAGE

714

E2(6
E2:C6 2BFF

E2C8 892800
E2CB F3

715
71.
717
718

EI0A:

719

1---- --- ---------------------------------

E2ee AS
720

72: 1

CRT INTERFACE LINES TEST

; DESCRIPTION

12Z

SENSE ON/OFF TRANSITION OF THE

123

VIDEO ENA.BlE AND HORIZONTAL

724

SYNC LINES.

725
726
727

POP

AX

PUSH

AX

I SAVE IT

E2CF 80FC30

728

CMP

AH,30H

I B/N CARD ATTACHED"?

E202 BABA03

72.

I10V

DX.03BAH

I SETUP ADOR OF Bioi STATUS PORT

EzeD 58

EleE 50

E205 7403

no

E207 SADA03

731

HOA

n2

E2DA 8408

733
734

fZOC
EZOC 26e9

JE

Ell

NOV

OX.03[)AH

Ell:
MOV

...H.8

SUB

ex,cx

IN

Al,DX

I GET VIDEO SENSE SW INFO

; YES - GO TEST LINES
; COLOR CARD IS ATTACHED
I

LIHE_TST:

j

READ CRT STATUS PORT

Ell:

EZOE EC

735
736
737

E20F 22C4

738

AND

Al,AH

I CHECK VIoEO/HORZ LINE

HEI 7504

73.

JHZ

E14

; ITS ON - CHECK If IT GOES OFF

E2E3 E2:F9

740

LOOP

E13

; LOOP TI Ll ON OR TIMEOUT

E2f5 E609

741

JMP

SHOOT E17

I GO PRINT ERROR HSG

E2f7

74'

EZE7 2:6C9

743

.LOI

ex.cx

IN

AL.oX

E2DE

E2E9

744

E2E9 EC

745

Ell:

E14:

E15:
I

READ CRT STATUS PORT

System BIOS

A-II

LaC OBJ

LINE

ElEA 2:2.C4

74.

AND

AL.AH

; CHECK VIDEOIHORl LINE

E2fC 7411

747
748

JZ

E16

I ITS ON - CHECK NEXT LINE

ElEE ElF9

LOOP

El5

E2FO

74.

E2fO IF

750

ElFl IE
EHZ C606150006

751

PUSH

OS

752

MOV

DS:MFG_ERRJlAG,06H

MOV

DX,102H

CALL

ERR_BEEP

SOURCE

; lOOP IF OFF TILL IT GOES ON

E17:

I CRT_ERR:
PDP

OS

E2F7 BA0201

,.3

E2FA E8DB16

754

E2FO EB06

755
75.

JMP

SHORT E 18

E2FF

E2FF BI03

757

HOV

CL.3

nOI DlEC
£303 7507

758

SH'

AH.Cl

75.

JHZ

El2

nos

nos

7.0
7.1

58

EJoe COlO

7.'
7.3

noA.

764

noll. BACOCO

nOb 8400

; < >< >< >(RT ERR CHKPT.

j

; NXT_LINE:

E16:

; GET N[XT BIT TO CHECK

I

GO CHECK HORIZONTAL LINE

i DISPLAY_CURSOR:

E18:
POP

AX

I GET VIDEO SENSE SWS I AH)

MOV

"H.D

; SET MODE AND DISPLAY CURSOR

IHT

IOH

; CALL VIDEO I/O PROCEDURE

MOV

OX,oeaDOH

nOD

765
76.

nOD 8ED.&.

7.7

MOV

os.ox

E30F 260B

768

SUB

BX,BX

nIl 8801

7.'

MaV

AX,leX]

ElBA:

i

GET FIRST Z LOCATIONS

n13 53

770

PUSH

ax

E314 56

771

POP

ex

I LET BUS SETTLE

DIS 3055"A

77'
773

CMP

AX, O.t.AS5H

; PRESENT?

JNl

El8B

j

CALL

RON_CHECK

; GO SCAN MODULE

JMP

SHORT EIBC

E31F 81(25000

77'
775
77.
777

E323

778

E323 81FAOOC8

nIB 7505

nlA £8361&
E3lD £B04
EllF

E327 7CE4

06< >< >< >

GO BEEP SPEAKER

NO? GO LOOK FOR OTHER MODULES

E188:

ADD

OX,0080H

j

77.
780
781

eMP

OX,OC800H

; TOP OF VIDEO ROM AREA YET?

JL

El8A

i

782

8259 INTERRUPT CONTROLLER TEST

78l

POINT TO NEXT 2K BLOCK

ElBC:

i

GO SCAN FOR ANOTHER MODULE

DESCRIPTION

784

READ/WRITE THE INTERRUPT MASK REGISTER (IMR I

785

Wlnl ALL ONES AND ZEROES. ENABLE SYSTEM

766

INTERRUPTS.

767

MASK DEVICE INTERRUPTS OFF. CHECK

FOR HOT INTERRUPTS I UNEXPECTED).

786

----- -------------- ----- -- -- - --- -------- - ----------

76.

ASS\Jt1E

os: A8S0

790

POP

OS

791
792

i----- TEST THE INR REGISTEI.!

794
795
796
797
798

e21A:

,.3
EJU C606150405

E3ZF BOOO
El31 E6Zl
E333 £421

MOV

MOV

79'

AL,O

OUT

INTAOl,AL

IH

AL,ImAOl

j

<><><><><><><><><><><><>

i

<><><>CHECKPDINT 5<><><>

j

SET IHR TO ZERO

i

READ IHR

= O?

£335 OACO

800

OR

AL,Al

j

E337 7518

801

JHZ

D.

; GO TO ERR ROUTINE IF NOT 0

E339 BaFF

80.

MOV

AL.OFFH

j

EHB E621

803
80.
80S

OUT

INTAOl,AL

j

WRITE TO II1R

IH

AL,INTAQI

j

READ It1R

E33F 0401

ADO

AL,l

j

ALL INR BIT ON?

E341 7511

80.

IN'

O.

j

NO -

E33D E421

807
808

j -----

CHECK FOO HOT INTERRUPTS

j-----

INTERRUPTS ARE MASKED OFF.

IMR

DISABLE DEVICE INTERRUPTS

GO TO ERR ROUTINE

80.
810

CHECK THAT NO INTERRUPTS OCCUR.

811
81Z

MOV

n46 FB

813

STI

E347 2BC9

81'
815
81.

SUB

cX,CX

j

LOOP

04

I MIGHT OCCUR

n43 "26B04

E349
E349 E2FE

DATA_AREA(OFFSET INTRJLAG1.AL

; CLEAR INTERRUPT FLAG

; ENABLE EXTERNAL INTERRUPTS
WAIT 1 SEC FOR ANY INTRS mAT

04:

05:

E348 E2FE

817
818

lOOP

D5

B40 803£680400

81'

eMP

OATA_AREA(OFFSET IHTR_FlAG1,OOH

£352 7409

8"

JZ

07

I NO - GO TO NEXT TEST

MOV

51 ,OffSET EO

; DISPLAY 101 ERROR

E34B

£354

821

E354 BEFFF890

8"

A-12

j

010 ANY INTERRUPTS OCCUR?

06:

System BIOS

LOC OBJ

LINE

E3S6 E84E16

623

E356 FA

624

Else F4

6'5
826

SOURCE

eLI
HlT

827

828

I HALT THE SYSTEM

; - ----------------------- -- ------- -- - '-- - - -- --------

8253 TIMER CHECKOUT

; DESCRIPTION

829

VERIFY THAT THE SYSTEM TIMER (0) DOESN'T COUHT

830

TOO FAST OR TOO SLOW.

831
E35D

632

E350 C606150402

6ll

; ~~--------------- --------- ------ ---------- -------------07:
MOV
I <><><>

634
635

; TIMER CHECKPOINT 121

E3b2 BOFf

636

E364 E621
E366 8010

637

MaY
OUT

636

E3b8 E643

Al,OFEH

I MASK ALL INTRS EXCEPT lVl 0

INTAOl,AL
AL,OOOIOOOOB

I WRITE THE 8259 IMR

MOY

639

OUT

TIM_CTL.Al

ElbA 891600
E'360 8ACI

640

MOV

CX,16H

641

E 36F E640

642

MaY
OUT

AL,Cl
TIMERO,AL

E371
E371 F606660401

643
644
645

E376 7504
E376 Ei!:F7

64.
647

E37A fB08

646

E37C

08:
TEST

OATA_AREA[OFFSET IHTRJlAG1,OlH

JHZ

D9

LOOP

08

JMP

D6

E37C BlOC

NOV

Cl,12

E37E BOFF

.51

MOV

E380 E640

65'
653

OUT

AL.OFFH
TIMERO,AL

E382 C606680400

65'

E389 E621

ass

El8B

65.

E38B F6066B0401

657
656
659

E390 7St2

E392 ElF7

6.0
861

6.'

; DID TIMER 0 INTERRUPT OCCLR?
; YES - CHECK TIMER OP FOR SLOW TIME

I WAIT FOR INTR FOR SPECIFIED TIME
I TIMER 0 INTR DIDN T OCCUR
ERR

09:

649
650

E387 SOFE

I SE l TIM O. lSB, MODE 0, BINARY
I ~ITE TIMER CONTROL MODf REG
I SET PGM lOOP CNT
; SET TIMER 0 CNT REG
; WRITE TIMER 0 CNT REG

NOV
NOY
OUT

SET PGM lOOP CNT
I WRITE TIMER 0 CNT REG

DATA_AREAl OFFSET INTR]LAGJ.O

AL,OFEH
INTAOl,Al

I RESET IHTR RECEIVED FLAG
a INTERRUTS

; REENABLE TINER

010:
TEST
JNZ
lOOP

DATA_AREA[ OFFSET IHTRJ LAG I. OIH I DID TINER 0 INTERRUPT OCCUR?
; YES - TIMER CNTIHG TOO FAST, ERR

06
010

; WAIT FOR INTR FOR SPECIfIED TIME

;----- SETUP TIMER 0 TO MODE 3

E394 BOFF

6.3

MQY

Al.OFFH

E396 E621

664

OUT

I SEL TIM O,lSB,MSB,t100E 3
; WRITE TIMER MODE REG

E398 8036

865

NOY

INTA01.Al
Al,36H

E39A E643
E39C BOOO

666
667

OUT

TIHER+3.AL

MaY
OUT
OUT

Al.O
TIMER,Al

E39E E640
E3AO E640

666
669
870
871
872:

E3A2 8099

KEYBOARD TEST
; DESCRIPTION

RESET THE KEYBOARD AHa CHECK THAT SCAN

874
875

CODE AA' IS RETURNED TO THE CPU.
CHECK FOR STUCK KEYS.
; -------------------------~---------------------TSTl2:
Al,99H
HOY
I SET 8255 HOOE A,C=IN B=ooT
CMD_PORT,Al
OUT

f3A6 401004

676
679
860

E3A9 2401

661

DAB 7431
E3AD 803E120401

66'
663

E382 742A

66'

E3B4 E87316

665

J'
CAll

DB7 E31E

666

JCXZ

E389 8049

687

MOV

E3A4 E663

; WRlTE lSB TO TIMER 0 REG
; WRITE I1SB TO TIMER 0 REG

1------------------------------------------------

873

876
677

E3A2

TIHER.Al

I DISABLE A.LL DEVICE INTERRUPTS

NOY
AND
JZ
eMP

Al.DATA_AREA[OFFSET EQUIPJLAGJ
Al.OI
J TEST CHAMBER?
.7
I BYPASS IF SO
DATA_AREAr OFFSET MfG_ TST 1,1
; MANUFACTURING TEST ttODE?
F7
YES - SKIP KEYBOARD TEST
KBD_RESET
1 ISSUE RESET TO KEYBRD
f6
J PRINT ERR MSG IF NO INTERRUPT
ENABLE KE)'BOARO
AL.49H

ElBB E661

668

OUT

DBC SOFBAA

669

eMP

Bl.OAAH

i SCAN CODE AS EXPECTED,?

nco

690

JHE

F6

J NO - DISPLAY ERROR MSG

7515

691
892

; ----- CHECK FOR STUCK KEYS

693

EX2 Boca

f3e8 E661

69.
695
8.6
697

EX" 28C9
f3ee

699

E3C4 E661

nCb 8048

696

MOV
OUT
NOY
OUT

Al,OCBH
PORT_B,Al
Al,46H

sue

cX,ex

; ClR KBD, SET ClK LINE HIGH
1 ENABLE KBD,CLK IN NEXT BYTE

PORT_B,Al

F!i:

System BIOS A-13

LINE

LOC OBJ

...'01
...,,,
...
..,
.,.

Elee E2FE

ElCE £460
£3DO XOO

SOURCE

E3D2 740'"
E304 E88415
£307

.. 5

E3D7 8£4CEC90

.. 7
. .8

E30B £6CB15

E3DE

f30E IE

E3DF ZBCO

~

~IlE

IN

FS
"'L.KBD_IN

I CHECK FOR STUCK KEYS

CHP

AL,O

I SCAN CODE

JE

F7

~

lOOP

.. 2

DELAY FDR A

=

01

YES - CONTINUE TESTING

CALL

XPC_BYTE

I CONVERT ANJ PRINT

HOV

SI,OfFSET Fl

I GET "5G ADDA

CALL

E_HSG

f

F6:
PRINT I1SG ON SCREEN

j ---~ - - - - - - - - - - . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

SETUP HARDWARE INT. VECTOR TABLE

91.

1------------------------------------------------

'11

F7:

912

PUSH

'13

SUB

OS

AX,AX

HOV

ES,AX

915

HOV

eX,OB

I GET VECTOR tNT

CS

I SETUP OS SEG REG

ElE7 IF

91'
917

PUSH

pop

OS

£3E8 BEF3FE90

.. 8

HOV

SI,OFFSET VECTOR.TABLE

f3EC 8F2000

.19

HOY

DI,OFFSET INT.PTR

ElE1 6EtO

ElE3 890600
£3£6 DE

'2'
.21

ElEF
E3EF AS
£3FO 47
£3F2 £2F8

INC
INC

'24
.25

.2.

ElF4 IF

'27
.28

£3F5 C7D6DB005FF8

E3FB C7061400S4fF
E401 C706620000F6

E"OC 750 ...
£40E C70670003CF9

01
01

LOOP

F7'

POP

OS

SKIP OVER SEGMENT

i

i ----- SET UP OTHER INTERRUPTS ....S NECESSARY

.2'

HOV

93.
931
932
933

£407 803E120401

£416 E621

HOVSW

'22
.23

E3Fl 47

£414 BOfE

F7A:

NI1I.PTR,OFFSET NHI.INT

; NHI INTERRUPT

HOV

INT5.PTR ,OFFSET PRINT.SCREEN

HOV

BASIC.PTR+2,OF600H

I PRINT SCREEN

SEGHENT FOR CASSETTE BASIC

i

;----- SETUP TIMER 0 TO BLINK LED IF I1ANUFACTURING TEST MODE

93.
935

eMP

DATA.AREA[OFFSET HFG_TSTl,OlH

JNZ
HOY

WORD PRT( ICH-4I,OFFSET BlINIClNT; SETUP TIttER INTR TO SLIt« LED

938

HOY

AL,OFEH

93'

OUT

INTAOl,A.L

,'"
937

...
941

CHECK TO SEE IF EXPANSION BOX PRESENT - IF INSTAllED,

TEST DATA AN) ADDRESS BUSES TO I/O BOX

943
944

...

.,

947

I ENABLE TIMER INTERRUPT

; EXPANSION I/O BOX TEST

942

945

J HFG. TEST HODE?

EXP_IO

ERROR='180l'

1---------------------------------------------------------------j-----

DETERMINE IF BOX IS PRESENT

948

£418
£418 BAI002

I (CARD WAS ENABLED EARLIERI

EXP.10:

95.

HOV

OX,02l0H

; CONTROL PORT ADDRESS

HOV

AX,5555H

J SET DATA PATTERN

OUT

DX,AL

£41F 8001

.51
'52
.53

HOV

AL,OIH

; HAKE AL DIFFERENT

£421 EC

'54

IN

AL.OX

; RECOVER DATA

£422 3AC4

955

E"IB 885555
£41E EE

CHP

AL,AH

; REPLY?

£424 7544

os.

JHE

j

NO RESPONSE, GO TO NEXT TEST

£426 F7DD

957

NOT

El'
AX

j

HAKE DA TA=AAAA

.5.,..

OUT

DX,AL

HOV

AL.OlH

IN

AL.OX

CHP

AL,AH

'.2

JNE

El.

£428 EE

£429 BOOI
£42B EC
E4at 3AC4

£42£ 753A

'58

,.,

...'.5

J RECOVER DATA

..3

£430
£430 B50100
£433 BA1502

£436 B91000
£439

..
'.7

,

.,

i ----- CHECK ADDRESS BUS

EXPZ:

968

97.

HOV

BX,DOOlH

HOV

DX.0215H

; LOAD HI ADDR. REG ADDRESS

HOV

CX,0016

J GO ACROSS 16 BITS

CS:(BXI,AL

J WRITE ADDRESS FOOOO+BX
J READ ADOR. HIGH

EXP):

£439 2£8807

'71

I10V

E43C 90

'72
973

NOP
IH

AL.DX

97'
975

eMP

AL,BH

JHE

EXP.ERR

J GO ERROR IF ttISCQt1PARE

'7'

INC

DX

j

E43D EC
£43E 3AC7

£440 7521
£442 42

A-14

System BIOS

OX=Z16H (ADDR. lOW REG)

SOURCE

LOC OBJ

LINE

E443 EC

977

IN

AL.DX

E444 3AC3

CNP

Al.BL

JHE

EXP_ERR

E448 4A

978
979
980

DEC

OX

; OX BACK TO ,lSH

£449 DIEl

981

SHL

8X.1

E448 ElEt

98'
9a3

LOOP

EX?3

,

E446 751B

98'
985

E4SZ 4A

986
987
9a8

£453

.89

E453 8AEO

E440 690800

I COMPARE TO lOW A.DDRESS

lOOP TILL 'I' WALKS ACROSS BX

;----- CHECK DATA BUS

MOV

eX.OODB

I DO 8 TIMES

NOV

AL,O!

OEC

OX

; MAKE OX=2.14H IDATA BUS REG)

990
991

NOV

AH.A.l
QX,Al

; SAVE DATA. BUS VALUE

£456 BOOI

992

NOV

E4sa EC

IN

E459 3,A,C4

993
99.

E458 7506

995

JHE

SHORT EXP_ERR

£450 ODED

SHL

AL,I

; FORM NEW DATA PATTERN

lOOP

EXP4

;

E461 feD7

996
997
998

JMP

SHORT E19

; GO ON TO NEXT TEST

E463

999

MDV

5I.OFFSET F3C

CAll

E_MSG

E450 BODI

E455 EE

E45F ElF,

E463 BEOFF990

1000

E467 E83Fl5

1001

1002:

EXP4:

OUT

CMP

AL,A.H

I SEND VALUE TO REG
; RETRIVE VAL.UE FROM REG
; = TO SAVED VALUE

LOOP TILL BIT WALKS ACROSS AL

EX?_ERR:

J ---------- --- -------------- •. ----------------------------

ADDITIONAL REAO/WRITE STORAGE TEST

1003
1004

AL.OlH
AL,DX

; DESCRIPTION

1005

WIHTE!J;!EAD DATA PATTERNS TO ANY READ/WRITE

1006

STORAGE AFTER THE FIRST 32:K.

1007
1008

--------------------------------------------------------

1009
E46A

1010

E46A E8EC15

1011

STORAGE

ADDRESSABILITY IS CHECKED.

;

ASSUME

OS:DATA

CALL

DDS

E19:

E460 IE

1012

PUSH

OS

E46E

1013

E46E 813E72003412

1014

CMP

RESETJLAG,1234H

I WARN START?

E474 7503

1015

JHE

E20A

I CONTINUE TEST IF NOT

E476 E99FOO

1016

JMP

ROM_SCAN

; GO TO NEXT ROUTINE IF SO

E479

1017

E479 681000

1018

MOV

AX.16

• STARTING

E47C EB28

1019

JMP

SHORT PRT_srz

J POST MESSAGE

E47E

1020

E47E 8BIEl300

HO:

HOA:

.A.m.

OF MEMORY OK

E206:

1021

MOV

ex. MEMORY_SIZE

I GET MEM. SIZE WORD

E482 83E8IO

1022

SUB

ex. Ie.

; 1ST 16K ALREADY DONE

E485 8104

1023

MOV

Cl.04H

E487 03EB

1024

SH.

BX.CL

; DIVIDE BY 16

E489 8Bce

1025

MOV

ex.ex

I SAVE COUNT OF 16K BLOCKS

E488 6BOO04

1026

MOV

BX.0400H

I SET PTR. TO RAM SEGMEHT:>16K

E48E

1027

E48E 8EOB

1028

HOV

OS.BX

J SET SEG. REG

E490 8EC3

1029

NOV

ES.BX

E492 81C30004

1030

ADD

8X.0400H

E496 52

1031

PUSH

OX

E497 51

1032

PUSH

CX

E498 53

1033

PUSH

ex

E499 50

1034

PUSH

AX

E49A 890020

E21:

; POINT TO NEXT 16K
; SAVE WORK REGS

1035

MOV

cx.zoaOH

£49D E8CFOl

1036

CALL

STGTST_CNT

E4AO 754C

1037

JHZ

EllA

I GO PRINT ERROR

POP

AX

; RECOVER TESTED HEM tM1EIER

ADD

.lX,16

E4A2 58

1038

E4A3 051000

1039

E4,6,6

1040

E4.6.6 50

; SET COUNT FOR 8K WORDS

PRT_SIZ:

1041

PUSH

E4A7 BBOAOO

1042

MOV

eX.10

; SET UP FOR DECIMAL CONVERT

E4AA 890300

1043

MOV

CX.3

AX
J OF 3 NIBBLES

E4AD

1044

E4AD 3302

1045

XO.

E4AF F7F3

1046

DIV

ex

E481 80CA30

1047

Dl.30H

; MAKE INTO ASCII

E484 52

1048

OR
PUSH

OX

, SAVE

E4B5 E2F6

1049

LOOP

DECIMAL_LOOP

£4B7 890300

1050

MOV

CX,3

E4BA

1051

DECIMAL_lOOP:

OX.OX
, DIVIDE BY 10

PRT_DEC_ LOOP:

E4BA 58

1052

pop

E4BB E80EI4

1053

CALL

AX
PRT_HEX

I RECOVER A NUMBER

System BIOS A-IS

LaC OBJ

LINE

SOURCE

1054

E46E HFA.

1055

MOV

CX,7

E4C3 BEIAEO

1056

MOV

51,OFF5ET F3B

E4Cb

1057

E4eo 890700

Al,CS: lSI

E4C6 2ESA04

1058

E4C9 46

1059

INC

S1

E4eA E8CF14

1060

CAll

PR!_HEX

[4CD ElF7

PRINT '

KB OK'

J

LOOP

KB_lOOP

E4CF 58

1062

POP

AX

; RECOVER WORK REGS

£400 3CI000

1063
1064
1065

CMP

AX , 16

; FIRST PASS,?

JE
POP

6X

1066

1061

E403 74A9

E405 56

E20B

POP

ex

[407 SA

1~67

POP

ox

£408 E264

1068

LOOP

E2l

E4DA. BOOA

1069

HOV

Al,10

£406 S9

E4DC E8BD14

CALL

1070

lOOP TILL ALL MEM. CHECKED
LINE FEED

PRT_HEX

1071

1072

1----- DMA Teo SHOULD BE ON BY NOW - SEE IF IT IS

1073
E40F [408

1074

E4E1 2:401

1075

AHO

E4E1 7533

1076

JHZ

£4E; IF

1077

POP

[4E6 C606150003

1078

MOV

E4EB E966FE

1079

JMP

AL,DMA+08H
AL,OOOOOOOIB

I Teo STATUS BIT ON?
I GO ON WITH NEXT TEST IF OK

os
; <:><:><><><><><><><><><><><>
06

; POST 101 ERROR M56 AND HALT

1080
1081

1----- PRINT FAILING ADDRESS AND XOR'EO PATTERN IF DATA COMPARE ERI(oR

1062

E4EE 8AE8

EZIA:

MOV

CH,AL

; SAVE FAILING BIT PATTERN

MOV

AL,n

; CARR AGE

CALL

PRT_HEX

1086

MOV

AL.lo

E4FO BOOO

1063
1084

E4FZ f8A714

1085

E4F5 BOOA

E4F7 E8A214

RETUR~

1087

CALL

E4FA 58

1088

POP

AX

; RECOVER AMT. OF GOOD MEM.

E4-FB 83C406

1089

ADO

513,6

; BALANCE STACK

E4FE eCOA

1090

MOV

DX,ns

; GET FAILING SEGMENT

E500 IF

1091

POP

as

PRT _HEX

ESDI IE

Ion

PUSH

OS

E502 A,31300

1093
1094

HeV

MEMORY_SIZE.AX

i

LOAD MEM. SIZE WORD TO SHOW

; HOW MUCH MEM. WORKING
; <><><><><><><><><><><><><>

Es05 88361500

1095

[509 ESCEIA

1096
1097

CALL

I <><>CHECKPOINTS 08->"0<><>
PRT_SEG

; PRINT IT

ESOC BACS

1098

MOV

Al,CH

I GET FAILING BIT PATTERN

ESOE E87A14

1099

CALL

XPC_BYTE

i

CONVERT AND PRINT CODE

E511 BE04F990

1100

MOV

51 ,OFFSET El

I

sETUP ADDRESS OF ERROR MS6

E515 E89114

; PRINT ERROR M5G

1101

1102:

i ---- ---- - - ---------- --- -- -- --------- - -- ---- ------------ ---------

1103

I CHECK FOR OPTIONAL ROM FROM C8000->F4000 IN ZK BLOCKS

1104

fA VALID MODULE HAS '5SAA' IN THE FIRST 2 LOCATIONS,

1105

LEHGTH INDICATOR (LENGTH/S121 IN THE 3D LOCATION AHO

1106
1107

TEST/INIT. COOE STARTING IN THE 4TH LOCATION.)
; ---------------------------------------------- ------ ------------

E518 BAooce

1108
1109

NOV

E51B

1110

ROH_SCAN_l:

E51B BEDA

1111

MOV

E518

ox.ocaOOH

I SET BEGINNING ADDRESS

OS,QX

ESlo 2BDB

1112

SUB

BX,BX

; SET BX=OOOO

ESIF 8B07

1113
1114

HOV

AX, [BX]

; GET 1ST WORD FRON MODULE

[521 53

PUSH

BX

£522 56

1115

POP

BX

; BUS SETTlING

E523 3055A.'"

1116

eM?

AX, OAA55H

; = TO

E526 7506

1117

JNZ

NEXT_ROM

I PROCEED TO NEXT ROM IF NOT

E528 [82814

111a

CALL

ROM_CHECK

; GO CHECK OUT MODULE

E528 E80590

1119

JMP

ARE_WE_DONE

I CHECK FOR END OF RON SPACE

E52:E

ADD

OX. OOBOH

I POINT TO NEX'f 2K ADDRESS

£532 61FAOOF6

1120
1121
1122
1123

eMP

ox. OF600H

£536 7eE3

11Z4

JL

ROH_SC ... N....1

I GO CHECK ANOTHER ADO. IF NOT

£538 E60190

llzS

JMP

BASE_ROM_CHK

; GO CHECK BASIC ROM

ES2E 81C28DOO
E532:

1126

;

10 WORD?

I AT F6000 YEn

----- ------------------------------------------------------- -------- ----

112:7

I A CHECKSUM IS DONE FOR THE 4 ROS MODULES CONTAINING BASIC CODE

1--------------------- -- ----- ------------------ ---- ----------------------

[536

l1Z8
1129

E538 6404

1130

A-16

BASE_ROH_CHK:

System BIOS

MaV

AH,4

I NO. OF ROS MODULES TO CHECK

LOC OBJ

..'"

LINE
1131

SOURCE
E4:

£530 2608

1132

SUB

E53F 8EDA

1133

MOV

ex ,ex
os.ox

~

1134

SETUP STARTING ROS AOOR

I CHECK RQS

[541 E8AE13

1135

CALL

ROS_CHECKSUH

E544 7403

1136

JE

E5

CONTINUE IF OK

E546 f88201

1137

CALL

ROM_ERR

POST ERROR

E549

1138

£5:

E549 81C20002

1139

ADD

OX,OZOCH

I POINT TO HEXT 8K HODULE

E540 FEte

1140

DEC

AH

; ANY HORE TO DO?

E54F 75ft

1l<1l

JNZ

1142

; YES - CONTINUE

J - ----------- ---------------------------- ------------------------

1143
1144

,4

DISKETTE ATTACHMENT TEST
; DESCRIPTION

1145

CHECK IF IPl DISKETTE DRIVE IS ATTACHED TO SYSTEM.

1146

ATTACHED, VERIFY STATUS OF NEC FOC AFTER A RESET. ISSUE:

1147

A RECAl ANO SEEK

1148

CI'l)

IF

TO FDC A.HO CHECK STATUS. CONPLETE

SYSTEM INlTULIZATlON THEN PA.SS CONTROL TO THE BOOT

1149

LOADER PROGRAM.

[551

1150
1151

• ---------------------------------------------- ------------------

£551 IF

1152

POP

OS

E552 MIDDD

1153

MOV

AL,BYTE PTR EQUIPJLAG

; DISKETTE PRESENT?

E555 2:401

1154

AND

AL,OIH

; NO - BYPASS DISKETTE TEST

E557 74'3E

1155

JZ

Fl5

FlO:

E559

1156

E559 E421

1157

IN

AL, INTAOl

E558 NSF

1158

AND

Al.OBfH

E550 E621

1159

OUT

INTAOI.AL

I

EttABLE DISKETTE INTERRUPTS

E55F 8400

1160

MOV

AH.O

; RESET NEC Foe

E561 8A04

1161

HOV

OL,AH

; SET FOR DRIVE 0

con

1162

INT

13H

; VERIFY STATUS AFTER RESET

1163

TEST

AH.OFFH

; STATUS OK?

1164

JNZ

Fl3

J NO -

ES63

E565 f6C4FF
E568 7520

1165
1166

Foe

FAILED

; - --- TURN DRIVE 0 MOTOR ON

1167

E56,6, SAFlO]

1168

MOV

DX.03F:2H

; GET ADOR OF FOC CARD

E56D BOlt

1169

MOV

Al.ICH

; TURN MOTOR ON, EN DNA/INT

E56F EE

1170

OUT

Ox,AL

; WRITE FOC CONTROL REG

E570 26C9

1171

SUB

ex.cx

E572

1172

E572 E2FE

1173

E574

1174

E574 E2FE

1175

E576 3302

1176

XOR

OX,OX

; SELECT DRIVE 0

E578 B501

1177

HOV

CH,I

; SELECT TRACK 1

E57A 88163EOO

1178

HOV

SEEK_STATUS,Dl

E57E fBFcoe

1179

CALL

SEEK

; RECAlIBIlATE DISKETTE

E581 1207

1180

JC

F13

; GO TO ERR SUBROUTINE IF ERR

E583 6522

HOV

eH,34

; SELECT TRACK 34

E585 E8F5DB

1181
1182

CALL

SEEK

; SE EK TO TRACK 31+

E588 7307

1183

E58A

1184

ES8A 6E52EC90

1185

ESSE E81814

1186

Fll:
LOOP

F11

LOOP

F12

I WAIT FOR 1 SECOND

JNC

F14

; OK, nrRN MOTOR OFF

MOV

51 ,OFFSET F3

J GET ADOR OF MSG

CAll

E_MSG

; GO PRINT ERROR MSG

F13:

I OSK_ERR:

1187
1188

;----- TURN DRIVE 0 HOTDR OFF

1189
E591

1190

E591 BoDe

1191

MOV

AL.OCH

i TURN DRIVE 0 HOTOR OFF

E593 BAF203

1192

MaV

DX,03F2H

; FoC tTL ADDRESS

E596 EE

1193

OUT

OX.AL

; ORO_OFF:

1194
1195

; ----- SETUP PRINTER AND R5232 BASE ADDRESSES IF DEVICE ATTACHED

1196.
[597

1197

F1S:

E597 C606660000

1198

MOV

INTRJlA.G.OOH

; SET STRAY INTERRUPT FLAG

E59C 8EIEOO

1199

MDV

SI.OFFSET KB_BUFFER

; SETUP KEYBOARD PARAHETERS

E59F 89361AOO

1200

MOV

E5A3 8936ICOO

1201

MOV

BUFfER_TAIL,S!

E5A7 89368000

1202

MOV

BUFFER_START .51

= 00

BUFFER_HEAD ,51

E5AB 83C620

1203

ESAE 89368200

1204

ADD
MOV

BUFFER_EI'I),SI

E582 BF7S0D

1205

MOV

DI,OFFSET PRINT_TIM_OUT ;SET DEFAULT PRINTER TIMEOUT

ES65 IE

1206-

PUSH

OS

E586 07

1207

POP

ES

51.32

.OEFAUlT BUFFER OF 32 BYTES

System BIOS A-I7

LOC OBJ

LINE

SOURCE

ES67 681414

120a

HOV

ES6A AB

1209

STOSW

Esse AS

STOSW

ESSC B80101

1210
1211

MOV

ESBf AB

1212

STOSW

£5eo AS

STOSW

IH

Al,IHT"'OI

AND

AL.OFCH

ESC5 E6Zl

1213
1214
1215
1216

OUT

INTAOl .... l

ESC7 83FDOO

1211

CMP

BP.OOOOH

ESCA 7419

1218
1219

E5Cl £421
E5C3 24fC

AX,1414H

) OI;FAUL T=20

AX,OlOlH

;RS232 DEFAUlT=OI

MOV

OX.2

CALL

ERR_BEEP

E502 8E09£890

1222

MOV

SI.0FFSET

E506 E8F1l3

1223

CAll

P_MSG

E509

1224
1225

MOV

AH.OO

IH6
1221

INT

16H

CHP

AH,36H

E508 CD16
E500 BOFtlB

E5EO 75F7

ep=

• 2 SHORT BEEPS (ERROR)

no

;

LOAD ERROR MSG

; WAIT FOR 'Fl' KEY

1228

JHE

ERR_WAIT

ESE2 EBOE9D

1229

JHP

FlSA

; BYPASS ERROR

E5E5

1230

ESES 803£120001

1231

eMP

MFG_TST ,I

I MFG HODE

ESE A 7406

1232
1233

JE

FI5A

; BYPASS BEEP

ESEC BMIDO

HOV

OX,l

;

CALL

ERR_BEEP

MOV

AL,BYTE PTR eqUIP_FLAG

; GET SWITCHES

E5EF E8E6n

1234

ESF2 AOI000

1235

F15A:

NON-ZERO

(ERROR HAPPENED J

) CONTINUE IF NO ERROH

JE

1220
1221

E509 8400

i CHECK FOR
;

E5CF E80614

Esec 8A0200

I ENABLE TIHER AND KB INTS

I SHORT BEEP (NO ERRORS)

ESFS 2401

1236

AHO

AL,OOOOOOOlB

;

ESF7 7503

1231

JHZ

F15B

; CONTINUE WITH BRING-UP

ESF9 E95FfA

1238

JHP

START

ESFC 2AE4

1239

SUB

AH,AH

ESFE A04900

1240

HOV

AL,CRT_MODE

£601 COlO

1241

IHT

IOH

f603

1242

f603 BDA3F990

1243

MOV

BP,OFfSET F4

£607 BEOOOO

F158:

'LOOP POST' SWITCH ON

I CLEAR SCREEN

FISC:

1244

HOV

SI,O

£60A

1245

£60A 2E865600

MOV

DX.CS:(BPl

; GET PRINTER BASE ADaR

EbOE BOA"

1246
1247

MOV

AL.OAAH

; WRITE DATA TO PORT A

E610 EE

1248

OUT

DX.Al

£611 IE

1249

PUSH

OS

HI2 EC

1250

IN

AL,DX

F16:

PRT_BASE:

EOI3 IF

1251

POP

OS

E614 JeAA

1252

CM?

Al,OAAH

£616 7505

1253

JNE

E616 895408

1254

HOV

PRINTER_BASE[ 51

£618 46

1255

INC

SI

EblC 46

INC

SI

£610

1256
1257

f61D 45

1258

; BUS SETTlEING
; READ PORT A
I DATA PATTERN SAME

Fl7

; NO -

J ,OX

; YES -

CHECK NEXT PRT CD

STORE PRT BASE AODR

; INCREMENT TO NEXT WORD

F17:
INC

B.

E61E 45

1259

IHC

BP

E6lF 81FOA9F9

1260

CHP

SP,OFFSET f4E

E623 75£5

1261

JNE

fl6

i

E625 B60000

1262

HOV

BX,O

; POINTER TO RS232 TABLE

E628 SAFA03

1263

MOV

DX,3fAH

; CHECK IF RS232 CO 1 ATICH?

E628 EC

1204

AL.DX

; REAO INTR ID REG

E6le MFS

1265

TEST

AL,OF8H

£62E 7506

1266

JHZ

F18

f630 C707FaD}

IN

HOV

1267

RS232_BASE[ BX 1, 3f8H

£634 43

1268

INC

BX

E635 43

1269

INC

BX

£636

1270

; POINT TO NEXT BASE ADOR

; AlL POSSIBLE ADDRS CHECKED?
PRT_BASE

; SETUP RS2.32. CD I I AoDR

Fl8:

£636 BAFA02

1271

HOV

DX.2FAH

£639 EC

IN

AL.DX

E63A MFa

1272
1273

TEST

AL,OFaH

Et.3e 7506

1274

JNZ

fl9

J BASE_END

E63E C7Q7FaD2

; SETUP RS232 CO 12

1275

HOV

RS232_BASE[BX1,2F8H

E642: 43

1276

IHC

BX

E643 43

1277

INC

ax

1278
1279
1281)
£644
E644 8Bt6

i-----

1281
1282

I CHECK IF RS232 CO 2. AHCH
; READ INTERRUPT 10 REG

SET UP EqUIP FLAG TO INDICATE HUMBER OF PRINTERS AHO RS232 CARDS

1283

HOV
HOV

; SI HAS 2* NUMBER OF RS232

E646 BI03
E648 02e8

1284

ROR

• ROTATE RIGHT 3 POSITIQtiS

A-I8

System BIOS

; SHIFT COUNT

LaC OBJ
EMA OAC3

E64e ",1100
EMF BAOI0,
£652 Ee

LINE

SOURCE

...

1285
1286
1287
lZB8

I OR IN THE PRINTER COUNT

BYTE PTR EQUIP_FLAG+l.Al

MOV

DX,20tH

IN

,H,DX

£653 90

1289

NOP

£654 90
£655 90

1290

NOP

1291
1292
1,93

NOP

£658 7505
EbSA 800E110010

1294

E65F

1295

E656 A80F

,U,BL

NOV

I STORE AS SECDI'IJ BYTE

TEST

AL,OFH

JNZ

I NO_GAME_CARD
F20
BYTE PTR EQUIPJLAG+l.l6

OR

F20:

; NO_GAME_CARD:

1296
1297

; ----- ENABLE NMI INTERRUPTS

1298
E65F £461

1299

IN

AL,PORT_B

E661 DC 30

1300

OR

AL.30H

£663 E661

1301

OUT

PORT_B,Al

E665 24CF

1302

AND

Al.OCFH

£667 E661

1303

OUT

PORT_B.AL

£669 B080

1304

NOV

Al.SOH

E66B £6AO

1305

OUT

OAOH,AL

£660

1306

E66D C019

1307
1308

; RESET CHECK ENABLES

j

ENAslE HNI INTERRUPTS

; LOAD_BooT_STRAP;

F21 :

I GO TO THE BOOT LOADER

19H

INT

1309

1----------------------------------------------------------------

1310

; THIS SUBROUTINE PERFORMS A READ/WRITE STORAGE TEST ON A BLOCK :
OF STORAGE.

1311
1312
1313

ENTRY REQUIREMENTS:
ES '" ADDRESS OF STORAGE SEGMEHT BEING TESTED

1314

OS ;

1315

CX

1316

=

ADDRESS OF STORAGE SEGMEHT BEING TESTED
WORD COUNT OF STORAGE BLOCK TO 8E TESTED

EXIT PARAMETERS:
ZERO FLAG; 0 IF STORAGE ERROR (DATA COMPARE OR PARITY

1317
1318

CHECK.

1319

BIT PATTERN OF THE EXPECTED DATA PATTERN VS THE ACTUAL
DATA READ.

132:0

1321
132:2
1323
E66F

1324

E66F FC

1325

AL=O DENOTES A PARITY CHECK. ELSE AL=-XOR I ED

; AX,BX,CX,DX,DI. AND 51 ARE ALL DESTROYED.

;---------------------------------------------------------------STGTST_CHT

PROC

NEAR
; SET aIR FLAG TO INCREMENT

ClO

E670 2BFF

1326

SUB

01,01

E672 28tO

1327

SUB

AX.AX

i SETUP FOR O-:>Ff PATIERN TEST

E674

1328

E674 8805

132:9

MOV

IOI1.AL

I ON FIRST BYTE

1330

MOV

£676 8ACS

) SET DI=OFFSET 0 REl TO ES REG

C2_1:
AL.lDI]

E678 32:C4

1331

XOR

AL.AH

; O.K.?

E67A 7540

1332

JNZ

C7

i 60 ERROR IF NOT

E67C FEC4

INC

A>!
AL.AH

£67E 8AC4

1333
1334

E680 75F2:

1335

JNZ

C2_1

,

E682 8809

1336

MOV

ax.ex

I SAVE WORD COUNT OF BLOCK TO TEST

E684 DIEl

1337

SHl

E686 B8AAAA

1338

MOV

AX.OAAAAH

I GET INITIAL DATA PATTERN TO WRITE

E689 BA55FF

1339

MOV

OX.OFF55H

I SETUP OTHER DATA PATTERNS TO USE

1340

REP

STOSI.!

; FILL STORAGE LOCATIONS IN BLOCK

1341

IN

AL.PORT_B

E68C F3

MOV

BX.1

LOOP TILL WRAP THROUGH FF

; CONVERT TO A BYTE COUNT

E680 AB
E68E E461
E690 OC30

1342

OR

AL,OOllOOOOB

E692 E661

1343

OUT

PORT_S.AL

E694 90

1344

NOP

£695 24CF

134S

AND

AL,llOOllllB

E697 E661

1346

OUT

PORT_8.AL
DI

E699

1347

I TOGGLE PARITY CHECK LATCHES

C3:

E699 4F

1348

OEC

E69A FD

1349

STO

I POINT TO LAST BYTE JUST WRITTEN

E698

1350

E698 BBF7

1351

MOV

SI.DI

E69D BBCB

1352

NOV

ex.ax

j

E69f

1353

E69F AC

1354

lOD58

E6AO 32C4

1355

XOR

AL.AH

; READ OLD TEST BYTE FRON
I DATA READ AS EXPECTED ?

E6AZ 7525

l356

JNE

C7

I NO - GO TO ERROR ROUTINE

E6A4 8AC2

1357

MOV

Al.DL

I GET NEXT DATA PATTERN TO WRITE

E6A6 All.

1358

STOSS

E6-'7 EZF6

1359

lOOP

; SET oIR FLAG TO GO BACKWARDS

C4:

CSt

i INITIALIZE DESTINATION POINTER

SETUP BYTE COUNT FOR LOOP
INNER TEST LOOP
STORAG~

[51 JE6A.0 32

; WRITE INTO lOC JUST READ [DI J+
C5

; DECREHWT BYTE CDl..tfr AN) lOOP

CX

1360
E6"9 22:E4
E6AB 7416

1361

AND

AH.AH

; Et-IJING ZERO PATTERN WRITTEN TO ST& ?

136Z

JZ

C6X

I YES - RETURN TO CAllER WITH AL=O

System BIOS

A-19

LINE

LaC OBJ

SOURCE

£6"'0 8AEO

1363

HOV

AH.Al

; seTUP NEW VALUE fOR COMPARE

E6AF 86H

1364

XCHG

OH.DL

; MOVE NEXT DATA PATTERN TO OL

E6Bl 22E4

1365

AND

AH.AH

; READING ZERO PATTERN THIS PASS?

E6B3 7504

1366

JNZ

C6

; CONTINUE TEST SEQUENCE TILL ZERO DATA

E6BS 8.0..04

1367

MOV

DL.AH

; ELSE SET ZERO FOi;l END READ PATTERN

JMP

C3

E667 EBED

1368

E6B9

1369

E669 Fe

1370

i

AND HAKE FINAL BACKWARDS PASS

C6:
; SET OIR FLAG TO GO FORWARD

CLD

EbBA 47

1371

INC

01

I SET POINTER TO BEG lOCA lION

E6BB 74DE

1372

JZ

C4

; REAO/Wf(ITE FORWARD IN STG

EbBD 4F

1373

DEC

01

[bBE 6AOI00

1374

NOV

DX,OOOOIH

i

E6el E806

1375

JNP

C3

; READ/WRITE BACKWARD IN STG

E6e3

; ADJUST POINTER
SETUP 01 FOR PARITY BIT AND 00 FOR END

Cf,X:

E6e3 E462

1376
1377

1M

AL,PORT_C

I DID A PARITY ERROR OCCUR ?

E6C5 24eo

1378

AND

Al,OCOH

I ZERO FLAG WILL BE OFF PARITY ERROR

E6C7 BODO

1379

NOV

AL.OOOH

; AL=Q DATA COMPARE OK

E6C9

1380

EOe9 rc

1381

E6CA C3

C7:
CLD

; SET DIRECTION FLAG TO INC

RET

1382
1383

STGTST_CNT

,"up

1384

; ------------------------------- -------------------------- --------------

1385

;

PRINT ADDRESS AND ERROR MESSAGE FOR ROM CHECKSUM ERRORS

1386

; -- --- - - -- - - - ---- ----- ---- - - - - - - ------ ----------- -- - -- -- - - - -- -- ----- --- ---

EbCB

1387

RON_ERR PROC

NEAR

Ebee. 52

1388

PUSH

Ebce 50

1389

PUSH

AX

EbCD BCDA

1390

HOV

DX,OS

; GET .'.OORESS POINTER

E6CF 2688361500

1391

HOV

ES:MFG_ERR_FLAG.DH

; <><><>

CMP

DX.OC800H

; CRT CARD IN ERROR?

JL

ROM_ERR_BEEP

; GIVE CRT CARD FAIL BEEP

CALL

PRT_SEG

; PRINT SEGEMENT IN ERROR

HOV

SI.OFFSET F3A

I DISPLAY ERROR HSG

CALL

E_MSG

; <><><>CHECKPOINTS CO->F4<>

1392
1393
1394
1395

E604 81FAOOC8
E6D8 7eOD

EbOA. EBFDIS
HOD BEOAF99Q

E6E4 58

1396
1397
1398
1399

POP

AX

f6ES SA

1400

pop

OX

E6E6 C3

1401

RET

E6El E8C512
E6E4

; S"VE POINTER

OX

ROM_ERR_END :

E6E7

1402

E6E7 BAOZO 1

1403

MOV

OX.OI02H

EbEA E8E612

1404

CALL

ERR_BEEP

E6EO ESfS

1405

JMP

SHORT ROM_ERR_END

ROM_ERR_BEEP;
i

BEEP 1 LONG. 2 SHORT

1407
1408

j---

1409

i

INT 19 ---------------------------------------------

BOOT STRAP LOADER

1410

TRACK D. SECTOR I IS READ INTO TIlE

1411

BOOT LOCATION (SEGMENT 0, OFFSET 7COO)

1412

ANO COHTROl IS TRANSFERRED THERE.

1413
1414

IF THERE IS A HAROWARE ERROR CONTROL IS

1415

1416

TlliEN AN ERROR
OCCURRED.
RETURN THE CQf1MO PORT STATUS IN (AX)
AH CONTAINS THE LINE STATUS
BIT 7 ::: TIME OUT
BIT 6 : TRANS SHIFT REGISTER EMPTY
BIT 5 == TRAN HOLDING REGISTER EMPTY
SIT 4 = BREAK DETECT
BIT 3 ::: FRAMING ERROR
BIT Z = PARITY ERROR
BIT 1 : OVERRUN ERROR
BIT 0 : DATA READY
AL CONTAINS THE HOD EM STATUS
BIT 7 : RECEIVED LINE SIGNAL DETECT
BIT 6 ::: RING INDICATOR
BIT 5 == OATA SET READy
BIT 4 = CLEAR TO SEt-iD
BIT 3 ::: DELTA RECEIVE LINE SIGNAL DETECT
BIT Z
TRAILING EDGE RING DETECTOR
BIT 1 = DELTA DATA SET READY
BIT 0 = DELTA CLEAR TO SEND

=

lOX) = PARAMETER INDICATING WHICH RS232 CARD (O.l ALLOWEO)

System BIOS A-21

LaC OBJ

LINE

SOURCE

1517
151a

, DATA AREA RS23,_BASE CONTAINS THE BASE ADDRESS OF THE 8250 ON THE

1519

CARD LOCATION 40GH CONTAINS UP TO 4 RS232 ADDREsses POSSIBLE

1520

DATA. AREA LABEL RS232_ TII'COUT (BYTE I CONTAINS OUTER lOOP COUNT

1521

1522

VALUE FOR TIMEOUT (OEFAUlT=l)

; OUTPUT

1523

AX MODIFIED ACCORDING TO PAR!15 OF CALL

1524

1525
152:6

E729

1527

E729

15;:a

E729 1704

1529

Ens 0003

1530

E720 8001

1531

E72:F CODa

1532:

E731 6000

All OTHERS UNCHANGED

; - ------- --- - - -------- --------- ---- ------ -- ---------- -- ---------- -- -----ASSUME CS:COOE.D5:0ATA

Al

1534

1535

E737 DeaD

1536

OE72:9H

LABEL

WORD

ow
ow
ow
ow
ow
ow
ow
ow

1533

E733 3000
E73S 1800

ORG

; TABLE OF INIT VALUES

1047

110 BAUD

768

150

384

; 300

192

I 600

96

I 12:00

46

I

24

; 4800

12

; 9600

2400

1537
E739

PROC

1538

fAR

1539
1540

;----- VECTOR TO APPROPRIATE ROUTINE

1541

(739 Fe

1542

STI

EnA IE

1543

PUSH

DS

E73B S2

1544

PUSH

OX

INTERRUPTS BACK ON

PUSH

51

E73D 57

1540

PUSH

01

E73E 51

1547

PUSH

E73C 56

1545

SAVE SEGMENT

1548

PUSH

ex
ex

E740 aBF2

1549

MOV

51 ,ox

E742 aBFA

1550

MOV

DI,OX

E744 DIE6

1551

SHl

E746 EBlon
E7 49 SB14

1552
1553
1554

CALL

ODS

MOV

DX.RSZ32_BASE[SII

OR

OX,OX

i

E740 7413

1555

JZ

A3

; RETURN

E74F OAE4

1556

OR

AH.AH

; TEST FOR (AH ):::0

E73F 53

E74B 0602

51.1

i

RSZ32 VALUE TO 51

; WORD OFFSET
; GET BASE ADDRESS
TEST FOR 0 BASE ADDRESS

E751 741t>

1557

JZ

A4

; CDI1M\..IN INIT

E753 FEte

1558

DEC

AH

; TEST FOR (AH1=1

E755 7445

1559

JZ

AS

, SEND AL

E757 FEee

1560

DEC

AH

; TEST FOR (AH )=2

E759 746,1,

1561

JZ

A12

; RECEIVE INTO AL
; TEST FOR (AH )::3

ElS6

1562

E756 FEee

1563

DEC

AH

E750 750l
E7SF (98300

1564

A2:
JNZ

A3

1565

f762

1566

f762 58

1567

JMP

Al8

pop

BX

A3:

; COMMUNICATION STATUS
; RETURN FROM RS232

ex

f763 S9

1568

POP

E764 SF

1569

POP

01

E765 Sf

1570

POP

SI

E7b6 SA

1571

POP

OX

f767 IF

157Z

POP

OS

E768 CF

1573

IRET

; RETURN TO CALLER. NO ACTION

1574

1575

;----- INITIALIZE THE COHMUNICATIONS PORT

1576
A4:

E769

1577

E769 8AEO

1578

E76B 63C203

1579

"DV
ADD

OX.3

E76E 6080

1560

NOV

AL.60H

E770 EE

1561

OUT

OX,Al

AH.Al

; SAVE WIT PARMS IN AH
; POINT TO 8250 CONTROL REGISTER

; SET OLAB=l

158Z
1583

;----- DETERHINE BAUO RATE DIVISOR

1584

NOV

OL,AH

E773 6104

1586

MOV

CL,4

E775 02e2

1587

ROL

OL.CL

E777 alE20Eoo

1586

ANO

OX,OEH

E77S BF29E7

1589

NOV

OI,OFFSET Al

; BASE OF TABLE

OI.DX

I PUT INTO INDEX REGISTER

E771 SAD4

1565

E77E 03FA

1590

AOO

Elea 8614
E782 42
E783 2E6A4501

1591

MOV

1592
1593

we

Ox

NOV

AL.eS:[OIhl

A-22

System BIOS

I GET PARMS TO DL

I ISOLATE THEM

; POINT TO HIGH ORDER OF OIVISOR
; GET HIGH ORDER OF OIVISOR

LaC OBJ
E7B7 EE

LINE

SOURCE
OUT

aX.AL

£788 4A

1595

DEC

OX

£789 2E8A05

1594

MeV
OUT

AL.Sc:[aIl

I SET MS OF DIY TO 0

I GET LOW ORDER OF DIYISOR

aX.AL

I SET LOW OF DIVISOR

ADD
MV

AL,AH

I GET PARMS BACK

AL.OIFH

i

aX,Al

J LINE CONTROL TO 8 BITS

[790 BAC4

1596
1597
1598
1599

E792 24lF

1600

E794 EE

1601

AND
OUT

E795 44

1602

DEC

E796 4A

1603
1604

DEC

MOV

AL.O

1605
1606

OUT
JMP

aX.AL

; INTERRUPT ENABLES ALL OFF

SHORT A16

; COM_STATUS

E78C EE

nBD 83C203

£197 BOOO

E799 EE
E79A E649

OX,3
STRIP OFF THE BAUD BITS

OX
OX

1607

1606

;----- SEND CHARACTER IN {AU OVER COMMO LINE

1609
E79C

e79C 50

1610
1611

AS:

PUSH

AX

; SAVE CHAR TO SEND

E790 83C204

1612

ADD

DX.4

J MODEM CONTROL REGISTER

E1AO B003

HOV

AL.3

j

OUT

OX,Al

; DATA TERMINAl READY, REQUEST TO SEND

INC

DX

; MooEH STATUS REGISTER

E744 42

1613
1614
1615
1616

INC

OX

E7AS 8730

1617

HOV

BH.30H

E7A7 E84800

1616
1619

CAll

WAITJOR_STATUS

; ARE BOTH TRUE

JE

A.

; YES, READY TO TRANSMIT CHAR

E7A2 fE
E7A3 42

f7U 7408

DTR AND RTS

I DATA SET READY & CLEAR TO SEND

E7AC

162:0

ElAC 59

1621

pop

cx

ElAD 6ACI

1622

MOV

AL.CL

I RELOAa DATA BYTE

E7AF

1623

E7AF 80CC60

1624

OR

AH .SOH

; INDICATE TIME OUT

E782 EBAE
E7B4

1625
1626

E764 4A

1627

E7BS

1626

E765 8720

1629
1630

E7B7 E83800
E7BA 75FO

1631

E7BC

1632

nec

IHEADS

A7:

AS:
JMP

A3

; RETURN

DEC

OX

I

NOV

BH.20H

I 15 TRANSMITTER READY

CALL

WAIT]OR_STATUS

I

JNZ

A7

; RETURN WITH TIME OUT SET

A9:

; CLEAR_TO_SEND
LINE STATUS REGISTER

AID:

All:

1633

TEST FOR TRANSMITTER READY

; OUT_CHAR
SUB

OX.s

; DATA PORT

E76F 59

1634

POP

CX

; RECOVER IN CX TEMPORARILY

E7eo BACl

1635
1636
1637

MOV

AL.CL

OUT

aX.AL

; HOYE CHAR TO AL FOR OUT. STATUS IN Nt
; OUTPUT CHARACTER

JMe

A3

; RETURN

E7C2 EE

E7C3 EB9D

1638
1639
1640

1----- RECEIVE CHARACTER FROM COMMa LINE

E7C5

IMI

",12:

E7CS 83C204

1642

E7ea 6001
E7CA EE

1643
1644
1645
1646
1647
1648
1649
1650
1651

E7eB 42

Elee 42

nco
nco

87ZD

E7CF EB2000
E702 7508
E704

E7D4 4A
E705

nos

6701

E7D7 E81800

ElOA 7503
ElOC
ElOC aOE41E
E?OF 8814

nEl EC
E7E2 E97DFF

1652
1653
1654
1655

1656
1657

ADO

1663

I MODEM CONTROL REGISTER

ALot
OX.AL

INC

; MODEM STATUS REGISTER

INC

OX
OX

HOV

BH,20H

I

CALL

WAIT_FaR_STATUS

t TEST FOR DSR

JNZ

AS

; RETURN WITH ERROR
i

WAlT_DSR_END

DEC

OX

j

LINE STATUS REGISTER

11011

SH.l

; RECEIVE BUFFER FULL

CALL

WAITJOR_STATUS

; TEST F()I;! REC. BUFF. FULL

JNZ

A6

AND

AH.OOOl1110B

DATA TERMINAL READY

i

; NAIT_DSR

AU:

A15:

DATA SET READY

A16:

A17:

1658
1659
1660
1661
1662

DX,4

MOV
OUT

GET_CH.4.R

j

TEST FOR ERR CONDITIONS ON RECV CHAR

; DATA PORT

MOV

J-----

I SET TIME OUT ERROR
;

IN

AL.OX

I GET CHARACTER FROH LINE

JMP

A3

i

RETURN

Cot1\10 PORT STATUS ROUTINE

1664
A18:

E7ES 8814

1665
1666

MOV

OX ,RS232_BASE [SI J

E7E7 63C205

1667

ADD

ElEA EC

1668
lb69

IN

OX.S
AL,OX

MeV

AH.AL

; CONTROL PORT
; GET LINE CONTROL STATUS
I PUT IN AH FOR RETURN

16070

INC

OX

I POINT TO MODEM STATUS REGISTER

E7E5

ElEe BAED
ElED 42

System BIOS A-23

LINE

LOC OBJ

SOURCE

ElEE EC

1611

IN

E7EF E970FF

1672

JMP

; GET MODEM CONTROL STATUS

AL,DX
A3

i RETURN

1673

; ------- --- -- -- --------- ---- -------------

1674

; WAIT FOR STATUS ROUTINE

1675

;

1676

; ENTRY:

1677

BH=STATIJS BITIS) TO LOOK FOR.

1678

DX=ADOR. OF STATUS REG

1679

; EXIT:

1680

ZERO FLAG ON

1681

ZERO FLAG OFF = TIMEOUT.

1682

= STATUS FOUND

AH=LAST STATUS READ

1683
E7F,

1684

E7F2 BAS07C

1685

E7F5

1686

ElFS 26C9

1687

Elf7

E7FA 22C7

1688
1689
1690
1691

ElFC 3AC7

1692

E7f7 EC
EYF8 8AEO

WAIT_FOR_STATUS PROC

,

NEAR

MOV

BL ,RSZ32_TIH_OUTIOI 1

sue

CX,cx

IN

Al,DX

MOV

AH,AL

ANIl

AL,BH

I

CMP

AL,BH

; EXACTLY

LOAD OUTER LOOP COUNT

WFSO:
WFSl:
; GET STATUS
; HOVE TO AH
ISOLATE BITS TO TEST

=

TO MASK

E7FE 7408

1693

JE

WFS_END

; RETURN WITH ZERO f LAG ON

EBOO E2F5

1694

LOOP

WFSI

; TRY AGAIN

E802 FEee

1695

DEC

BL

E804 75Ef

1696
1697

JHZ

WFSO

DR

BH,BH

E806 OAFF

1698

E808

1699

E808 C3

1700

I

SET ZERO FLAG OFF

WFS_END:
RET

1701

WAITJOR_STATUS WOP

1702:

ENDP

1703
E809 45525Z4FS22EZO

1704

'3D

DB

'HmOR. (RESUME

= Fl

KEY)',13,10

; ERROR PROMPT

28524553554045
20302022463122
2045455929
E623 00

Ea24 01
1705

1706

1---- INT 16 ------------------------------------------------------------

1707

I KEYBOARD 110

1708
1709

THESE ROUTINES PROVIDE KEYBOARD SUPPORT
i

INPUT

1710

(AH )=0

1711
1712

(AHl=l

READ THE NEXT ASCII CHARACTER STRUCK FROM THE KEYBOARD
RETURN THE RESULT IN (All, SCAN CODE IN (AH)
SET THE Z FLAG TO INDICATE IF AN ASCII CHARACTER IS

1713

AVAILABLE TO BE READ.

1714

(ZF )=1 -- NO CODE AVAILABLE

1715

(Zf )=0 -- COOE IS AVAILABLE

1716
1717

IF ZF = 0, THE NEXT CHARACTER IN THE BUFFER TO BE READ
IS IN AX. AND THE ENTRY REMAINS IN THE BUFFER
(AH )=2

1718

1719
1720
1721

1722
1723
1724

RETURN THE CURRENT SHIFT STATUS IN AL REGISTER
THE BIT SETIINGS FOR THIS CODE ARE INDICATED IN THE
THE EQUATES FOR KBJLAG

; OUTPUT
AS NOTED ABOVE. ONl'fAX ANO FLAGS CHANGED
ALL REGISTERS PRESERVEO

;------------------------------------------------------------------------

1725

ASSUME

CS ;CODE ,OS: DATA
OfS2EH

E82E

1726

D'G

Ea2E

1727

KEYBOARD_IO

f82E FB

1728

ST!

E8lF IE

PUSH

os

i

SAVE CURRENT OS

E830 53

1729
1730

PUSH

BX

j

SAVE BX TEMPORARILY

E831 E82512

1731

CALL

DDS

E834 OAE4

1732

DR

AH,AH

I AH=O

E836 740A

1733

JZ

1734

DEC

"

I ASCII_READ

E838 FEee
E83A 741E

JZ

E83C FEee

1735
1736

E61E 7426

1737

E840 EelC

1738

1739
1740

PROC

FAR

I INTERRUPTS BACK ON

AH

; AH=l

.2

I ASCII_STATUS

DEC

AI!

I AH=2

JZ

K3

I SHIFT_STATUS

JMP

SHORT INTIO_ENO

I EXIT

;----- READ THE KEY TO FIGURE OUT WHAT TO DO

1741
E842

A-24

1742

Kl:

System BIOS

I ASCII REA.[)

LOC OBJ

LINE

SOURCE
INTE~~UPTS

E842 FB

1743

STI

•

E843 90

NOP

; AllOW AN

E844 FA

1744
1745

E845 861EI.100

1746

MOV

E849 3alElCOO

1747

BACK ON DURING lOOP

INTER~UPT

TO OCCIA'!

J INTE~~UPTS

eLI

aX. BUFFER_HEAD

BACK OFF
I GET POINTER TO HEAD OF BUFFER

eMP

ex,BUFFER_TAIL

[840 74F3

1748

JZ

Kl

• TEST END Of BUFFER
, LOOP UNTI l SOMETHING IN BUFFER

E84f 6B07

1749

HOV

AX.raX)

; GET SCAN COOE At-I) ASCII COOE

E851 E81DOO

1750
1751

CALL

K4

; MOVE POINTER TO NEXT POSITION

[654 891EI.1DO

MOV

E858 E614

1752

JMP

aUFFER_HEAO.8X
5HO~T INTlO_END

; STORE VALUE IN VARIABLE
; RETURN

1753

1754

;----- ASCII STATUS

1755
E85A

K2:

E856 eBIElAOO

1756
1757
1758

E85F 381E1COO

1759

E863 a607

1760

[865 FB

1761

STI

E866 58

1762

POP

BX

E867 If

1763

E668 CA0200

1764
1765

'OP
OET

os

f85A FA

1766

8X.BUFFER_HE.t.D

I INTERRUPTS OFF
; GET HEAD POINTER

eMP

BX.BUFfE~_TAIL

; IF EQUAL (Z=l) THEN NOTHING THERE

MeV

AX.IBXJ

eLI
MOV

j-----

; INTERRUPTS BACK ON
; RECOVER REGISTER

,

J RECOVER SEGMENT
; THROW AWAY FLAGS

SHIFT STATUS

1767
K3:

E86B

1768

E86B A01700

1769

E8bE

1770

Ea6E 58
E86F If

1772

POP

E870 CF

1773

I~ET

MOV

1771

1774

AL.KBJlAG

; GET THE SHIFT STATUS FLAGS

BX

; RECOVER REGISTER
; RECOVER REGISTERS

OS

I RETl/RN TO CALLER
ENOP

1775

1776

;----- INCREMENT A BUFFER

POINTE~

1777

Ea7l

1778

[a7l 43

1779

K4

PROt

NEA~

INC

BX
BX
BX.BUffER_ENO

E872 43

1780

INC

E873 381E8200

1781

CMP

f877 7504

1782

JNE

£879 681E8000

1783

HOV

E87D

1784

EalD C3

1785
1786

"5

; MOVE TO NEXT WORD IN LIST

I AT END OF BUFFER?
; NO. CONTINUE

BX.BUFFER_STA~T

; YES. RESET TO BUFFER BEGINNING

K5:

RET
K4

ENOP

1787
1788

1----- TABLE OF SHIFT KEYS AND MASK VALUES

1789

[elE

1790

LABEL

BYTE

[e7E 52
[elf 3A

1791

DB

INS_KEY

1792:

DB

1793

OB

K6

; INSERT KEY

E88D 45
E881 46
E882 38

E883 10
[884 lA

E885 36
0006

1794

K6L

1795
1796

EI'"

;----- SHIFT_MASK_TABLE

1797
179~

<7

E886 &0

179'9

LABEL
DB

EB87 40

1800

DB

1801

OB

E886

BYTE
INS_SHIFT

; INSERT MODE SHIFT

E888 20

[889 10
EMA 08

ESSS 04
EBBC 02

E860 01
1802

IS03

;----- SCAN CODE TABLES

1804
E8BE 18

1805

"8

DB

27. -1. O. -1.-1.-1. 30 ,-I

fB8F FF
E890 00

[891 FF
[992 FF

System BIOS

A-25

LOC OBJ

LINE

SOURCE

E893 FF

E894 IE
E895 Ff

E896 FF

1806

DB

-1.-1.-1,31,-1,127.-1,17

1807

DB

2l, 5,18.20.25,21.9,15

1808

DB

16.27,29,10,-1,1,19

1S09

DB

4,6,7.8.10,11.12,-1.-1

1810

DB

-1.-1.2.8,26.24.3.22.2.

1811

DB

14,13,-1.-1, -1.-1.-1.-1

E897 FF
E898 FF

E899 IF
f89.6. FF

E698 7F
E89C FF

E890 11
E89E 17

E89F 05
E8AO 12

f8Al 14
E8A2 19

f8A3 15
E8A4 09
E8A5 OF

f8A6 10
fSA7 IB
E8A8 10
f8A9 OA
fSAA FF

E8A8 01

faAC 13
EBAD 04
fBAE 06

fBAF 07

E6BO 08
E881 OA
f882 DB
E8B3 DC

ES64 FF
EBBS FF
EBBb FF

E6B7 FF

E8B8 Ie
E8B9 lA
EBBA 18

EBBB 03
EBBC 16
EBBD

oz

EBBE DE
f8BF 00

E8CO fF
EBCl fF

f6t2 FF
E8C3 FF
E8C4 FF

Eees FF
E8C6 ZO

DB

181z

' ,-I

E8C7 ff
;----- eTl TABLE SCAN

E8C8

1813
1814

EaC8 Sf

1815

DB

94,95.96,97.96,99.100,101

1816

DB

102..103, -1. -1.119. -1.132..-1

1817

DB

115,-1.116.-1.117.-1,118.-1

K'

LABEL

BYTE

EaC9 SF
EBtA 60

E6CB 61

Eace 62
f8CO 63

fSCE 64
EeeF 65
E8DO 66

E8Dl 67
EeD2. FF
E803 FF
E804 77
E805 FF
E806 84
E807 FF
E8D8 T!

E809 FF
EaDA 74
E80B FF
E80C 75
E8DO FF

A-26

System BIOS

LOC OBJ
l~£

LINE

SOURCE

76

ESDF FF
E8EO FF

E8El
E8El 1B

1818

DB

1819

i ----- lC TABLE

182:0
1821

010

LABEl

-1

BYTE
DB

OISH. '1234567890-= I • DSH. 09H

1822:

DB

'qwertyuiop{ J' .COH,-I. 'udfghjkl;' .027H

1823

DB

60H. -1.seH •• zxcvbtw • • 1' .-1. '* .• -1. '

DB

-1

EBEl 3132:3334353637
3839302030
EBEE 08
EeEF 09

fBfO 71776572747975
696F705B5D
E8FC 00

EBFO FF
E8FE 6173646667686,4

686e38
E908 27

E909 60
E90A FF
E90B 5C
E90t 7A786376626E60
:;>C2E2F

E916 FF
E917 2A

E9lS FF
E9l9 20
E91A FF

182:4
1825

; ----- UC TABLE

E918

1826

K11

E9lB IB

1827

DB

27. ' !Oill& I .37 .05EH, • &*( 1_ +' .08H,0

1828

DB

'QWERTYUIOP{}' .OoH. -1. 'ASOFGHJKL:'"

1829

DB

07EH. -1 •• I ZXCVBHH<:>? , .-1,0.-1. '

LABEL

BYTE

E91C 21402324
E92:0 25

E921 Sf
E9Z2 262:A28295F28

E928 08
E929 00

EnA 51574552:545955
494F507870
E936 00

E937 fF
£938 4153444647484.1.

4B4ClA22:
E943 7E

, .-1

E944 FF
E94S 7C5A584356424E
4D3C3E3F
E950 FF
E951 00
E952 FF
E953

zo

E954 FF
1830

; ----- UC TABLE SCAN

E955

1831

Oil

E955 54

1832

DB

84 ,85,86 .87.8~h89, 90

1633

DB

91.92.93

LABEL

BYTE

E956 55
E957 56
E956 57
E959 58
E9SA. 59
E95B SA
E95C 58
E950 5C
E95E 50
1834

;----- A.lT TABLE SCAN

E95F

1835

013

E95F 66

1836

DB

104.105.106,107,106

18~7

DB

109,110,111.112.113

LABEL

BYTE

£960 69
E961 6A
E962 6B
E963 6C

£%460
E965 6E
E966 6F
E967 70
E968 71

1636

E96'

1639

j-----

01.

HUH STATE TABLE

LABEL

BYTE

System BIOS

A-27

LINE

LOC OBJ
E969 3738392D343536
28313233302'£

E976 47

Da

1840

1641
1842
1843

E976

SOURCE
, 789-456+11:30.

I

; ----- BASE CASE TABLE
K15

LABEL

BYTE

Da

71.72,73.-1.75.-1.77

Da

-1.79,80,81.82.83

E977 48
E978 49
E979 FF
E97A 46

E978 FF
E97C 40

E97D fF

1844

E97E 4F
E97F 50
E980 51
E981 52
E982 53

1645
1846
1647

;----- KEYBOARD INTERRUPT ROUTINE
ORG

OE987H

""DC
STI

FAR

E987 FB

1848
1849
1850

E988 50

1651

PUSH

AX

E9B9 53

185:::
1653
1854

PUSH

ax
ex
ox

PUSH

E980 57

1855
1856

E98E IE

1857

E98F Db

1858

PUSH

E990 Fe

1859

eLD
DDS

E987
E987

E98A 51
E988 52
E98C 56

KB_INT

PUSH
PUSH

I AlLOW FUIHHER INTERRUPTS

PUSH

51
DI

PUSH

os
ES
; FORWARD DIRECTION

E991 E8C510

1860

CALL

E994 E460

1861

IN

AL.KB_DATA

; READ IN TIlE CHARACTER

E996 50

186:::

PUSH

AX

j

SAVE IT

E997 E461

1863

IN

AL.KB_eil

j

GET THE CONTROL PORT

E999 8AEO

1664

MOV

AH.AL

• SAVE VALUE

E998 OC60

1865

OR

AL.80H

I RESET BIT FOR KEYBOARD

E99D E661

1866

OUT

KB_CTl,AL

E99F 86EO

XCHG

AH.A.L

E9Al E661

1667
1868

OUT

KB_CTl.AL

; KB HAS BEEN RESET

E9A3 58

1669

POP

AX

I RECOVER SCAN CODE

HOV

AH.Al

; SAVE SCAN CODE IN AH AlSO

1670

E9A4 6AEO

; GET BACK ORIGINAL CONTROL

1871
1872:

; ----- TEST FOR OVERRUN SCAN CODE FROM KEYBOARD

1873
E9A6 3CFF

1874

eMP

AL.OfFH

j

IS THIS AN OVERRUN CHAR

E9A6 7503

1875

JHZ

K16

j

NO. TEST FOR SHIFT KEY

E9AA E97A02

1876

JMP

K.2

I BUFFERJUlL_BEEP

1877

1878

;----- TEST FOR SHIFT KEYS

1879

E9AO

1680

E9AD 247F

1881

ANO

E9AF DE

1882

PUSH

es

E9BO 07

1883
1884

POP

ES

MOV

DI.OFFSET K6

E9B4 B90800

HI85

HOV

CX.K6L

E987 F2

1886

REPHE

SCASS

; lOOK THROUGH THE TABLE FOR A MATCH

E989 8AC4

1887

MOV

AL.AH

; RECOVER SCAN CODE

E9SB 7403

1888

JE

K17

; JUMP IF MATCH FOUN[)

E'ilBD E9S500

1889

JMP

K25

; IF NO MATCH. THEN SHIFT NOT FOUND

E981 BnEEa

K16 :

I TEST_SHIFT

AL.07FH

; TURN OFF THE BREAK BIT
; ESTABLISH ADDRESS OF SHIFT TABLE
; SHIFT KEY TABLE
LENGTH

E9B6 AE

1890
1891

;----- SHIFT KEY FOUND

1892
E9CO 81EF7FE8

1693

SUS

DI.OFFSET K6+1

E9C4 2E6AA586E8

1894

MOV

AH.CS:K7(DII

j

E9C9 ABBO

1895
1896

TEST

,H.80H

I TEST FOR BREAK KEY

JNZ

K23

; BREAK_SHIFTJQUND

E'ilCe 7551

K17:

; ADJUST PTR TO SCAN CODE MiCH

GET MASK

nno

AH

1897

1698

j-----

SHIFT MAKE FOUND. DETERMINE SET OR TOGGLE

1899

E9CD aOFCIO
HOD 7307

1900

eMP

AH.SCROLL_SHIFT

1901

JAE

K18

1902

1903

A-28

1----- PLAIN SHIFT KEY, SET SHIFT ON

System BIOS

j

IF SCROLL SHIFT OR ABOVE. TOGGLE KEY

LOC OBJ

E9D2 08261700
£9D6 £98000

LINE

DO

KB_FLAG.AH

1906

JMP

K2.

1907
1908
1909
E909
E909 F60617QOO4

1910
1911

E9DE 7565
E9EO 3C52
E9E2 75Z2

;----- TOGGLED SHIFT KEY. TEST FOR 1ST MAKE OR NOT

KI8:

J

SHIFT~TOGGLE

KB_FLAG. eTL_SHIFT

I CHECK eTL SHIFT STATE

1912

JHZ

K25

i

1913

CMP

AL. INS_KEY

1914

JHZ

K22
KBJLAG. ALl_SHIFT

1915

E9E9 755A
E9FO 7500

1916
1917
1918

E9F2 F606170003
E9F7 7400

1919
1920

E9F9

1921
1922

E9F9 683052

J Tl.RN ON SHIFT BIT
J INTERRUPT_RETURN

TEST

£9E4 F606170008

E9EB F606170020

SOURCE

1904
1905

E9FC E90601

1923
1924

E9FF
E9FF F606170003

1925
1926

EA04 74F3

192:7

TEST

JHZ
K19:

TEST

K25
KBJLAG, "AJt,-STATE

JHZ

K21

TEST

KB_FLAG.

JZ

K22

JlI1P IF eTl STATE
; CHECK FOR INSERT KEY
J JlR1P IF HOT INSERT KE'f
I CHECK FOR AL TERHATE SHIFT
I JUMP IF ALTERNATE SHIFT
I CHECK FOR BASE STATE
I JUMP IF NUM LOCK IS ON

LEFT_SHIFT+ RIGHT_SHIFT

K20:

j

JlR1P IF BASE STATE

; tuMERIC ZERO. NOT INSERT KEY
MII.

2:511
2:512

1----- ALLOW WRITE ROUTINE TO FALL INTO RW_OPN

2:513
2514

1----------------------------------------------------------------

2515

I RI,COPN

2516

I

THIS ROUTINE PERFORMS THE READIWRITE/VERIFY OPERATION

2:517

1----------------------------------------------------------------

f04A

2518

RW_OPH

E04A 730a

2519

E04C C606410009

2520

DISKETTf_STATUS.DMA_BOUNOARY

E051 BODO

252:1

.ROC
JNe
HOV
MOV
RET
PUSH

AX

E053 C3

2522

E054

2523

E054 50

2524

NEAR

J11
AL.O

; TEST FOR DMA ERROR
I SET ERROR

i NO SECTORS TRANSFERRED
I RETURN TO MAIN ROUTINE

Jll:

i DO_RW_OPN
I SAVE THE COI1HAND

2525
2526

; ----- TURN ON THE I1OTOR ANO SElECT THE DRIVE

252:7
EOSS 51

2528

PUSH

ex

I SAVE THE T/S PARMS

E056 eACA

2529

HOV

CL.DL

I GET DRIVE HUMBER AS SHIFT COUNT

E058 BOOI

2530

MOV

ALol

E05A D2EO

2531

SAL

Al,CL

E05C FA

2:532:

eLI

j

MASK FOR DETERMINING HOTOR BIT

j

SHIFT THE MASK BIT

I NO INTERRUPTS WHILE DETERMINING

2533

I

MOTOR STATUS

E050 C6064000FF

2534

MOV

HOTOR_COUNT I OFFH

j

E062 84063FOO

2535

TEST

AL,HOTPR_STATUS

I TEST THAT MOTOR FOR OPERATING

E066 7531

2536

Jl'

I IF

SET LARGE COUNT

D~ING

OPERATION

E068 a0263FOOFO

2:537

...,

I1OTOR_STATUS , OFOH

ED6D 08063FOO

2538

OR

I1OTOR_STATUS.Al

i TURN OFF ALL MOTOR BITS
I TURN ON THE CLRRENT HOTDR

E07l FB

2539

STI

Eon BOlO

2540

MOV

Al,IDH

; MASK BIT

E074 02EO

2541

SAL

Al.Cl

; DEVELOP BIT HASK FOR HOTOR ENABLE

E076 OAC2

2542

Al.OL

I GET DRIVE SE LECT BITS IN

neoc

E078

JHZ

OR

R~ING,

SKIP THE WAIT

I INTERRUPTS BACK ON

2543

OR

Al.OCH

J NO RESET. ENABLE DHA/INT

ED7A S.2

2544

PUSH

OX

I SAVE REG

E07B BAF203

2545

HOV

DX.03F2H

; CONTROL PORT ADDRESS

ED7E EE

2546

OUT

DX,Al

ED7F SA

2547

PO.

ox

; RECOVER REGISTERS

2:546
2549

;----- WAIT FOR MOTOR IF WRITE OPERATION

2550
E060 F6063Fooao

2551

TEST

MOTOR_SUTUS.60H

; IS ntIS A WRITE

ED85 7412

2552

I NO I CONTINUE WITHOUT WAn

2553

JZ
MOV

J1'

E087 8B1400

BX.2:0

EDaA E80FOO

2554

CALL

tiET_P...RM

I

EC80 OAE4

2:555

OR

AH.AH

; TEST FOR NO WAIT

EDSF

2556

J1Z:

J GET THE HOTOR WAIT

PARAMETER

I TEST_WAIl_TINE

eOSF 7408

2557

JZ

Jl'

I EXIT WITH TIHE EXPIRED

ED91 2&9

2558

SUB

cx.cx

I SET UP 118 SECOND LOOP TIME

£093

2559

ED93 E2FE

2560

LOO.

J13

• WAIT FOR THE REQUIRED TIME

J13:

System BIOS

A-37

LOC OBJ
E095 FEte

LINE

SOURCE

2561

DEC

AH

JHP

J12

£097 EBF6

2562

E099

2563

[099 FB

2564

STI

ED9A 59

2565

pcp

J14:

I DECREMENT TIME VALUE
I ARE WE DONE YET
I MOTOR_RUNNING
~

INTERRUPTS BACK ON FOR BYPASS WAIT

CX

2566
2567

;----- DO THE SEEK OPERATION

2568

ED9B EBOFOO

2569

E09E 58

2570

POP

AX

I RECOVER COMMAHO

E09F 8AFe

2571

HOV

BH.AH

j

fOAl B600

2sn

HOV

DH.O

; SET NO SECTORS READ IN CASE OF ERROR

EOA3 72.48

2573

JC

J17

; IF ERROR. THEN EXIT AFTER MOTOR OFF

EDAS BEFOED90

2574

HOV

5I.OFFSET J17

; DUMMY RETURN ON STACK fOR NEt_OUTPUT

EDA.9 56

2575

PUSH

S1

,

CALL

SEEK

2576

; MOVE TO CORRECT TRACK
SAVE COMMAND IN 8H

SO THAT IT WILL RETlIRN TO MOTOR OFF
LOCATION

2577
Z578

,----- SEND OUT THE PARAMETERS TO THE CONTROLLER

2579

2sao

CALL

NEC_OUTPUT

EDAD 8,6.6601

2581

HOV

AH.[BP+l1

; GET THE CURRENT HEAD NUMBER

EOBO 00E4

2582

SAL

AH.1

; MOVE IT TO BIT 2

EOB2 DOE4

2583

SAL

AH.l

E064 80E404

2584-

AND

AH.4

I ISOLATE THAT BIT

EOB7 OAE2

2.585

OR

AH.DL

; OR IN THE DRIVE HUMBER

EOM E88500

2586

CALL

NEC~OUTPUT

EDAA £89400

; OUTPUT THE OPERATION COMMAND

2587
2586

;----- TEST FOR FORMAT COMMAND

2.589
EDBC 80FF4D

2590

CHP

SH ,04DH

; IS THIS A FORMAT OPERATION

EDBF 7503

2591

JNE

J1S

i

EDCl E962FF

2592

JHP

J10

i IF SO, HANDLE SPECIAL

EOC4

2593

EDC4 8AES

2594

HOV

AH.CH

I CYLINDER NUtlBER

EDC6 E87800

2595

CALL

NEC_OUTPUT

EDC9 8,0.,6601

2596

MOV

AH,[BP+ll

EDCC E87200

2597

CALL

NEC_OUTPUT

NO. CONTINUE WITH R/W/v

JIS:

; HEAD NUMBER fROM STACK

EoeF BAEI

2598

HOV

AH,CL

EoDl E&6000

2599

CALL

NEC_OUTPUT

ED04 880700

2600

HOV

ex.7

; SECTOR NUl1BER

ED07 Esnoo

2601

CALL

GET_PARM

EDDA BB0900

260i?:

HOV

BX.9

j

EOoo E86COO

2603

CALL

GET_PARM

I

; BYTES/SECTOR PARM FROM BLOCK
TO THE NEC
EOT PARM FROM BLOCK
TO THE NEe

ED EO 880600

2.604

HOV

eX.!l

EDE3 E88600

2605

CALL

GET_PARM

,

EDE6 e60000

2606

HOV

ax.n

; DlL PARM FROM BLOCK

EOE9

2607

J16:

; GAP LENGTH PARM FROM BLOCK
TO THE NEC

; RIoI_OPNJINISH

EOE9 E68000

2608

CALL

GET_PARI1

EDEC 5E

2609

POP

S1

2610

,

TO THE NEt

; CAN NOW DISCARD THAT DlR1MY

,

RETURN ADDRESS

2611
2612

LET THE OPERATION HAPPEN

2613
CALL

WAIT_INT

; WAIT FOR THE INTERRUPT

EDFO

2615

EDFO 7245

2616

JC

J21

,

EDF2 E87401

2617

CALL

RESULTS

I GET THE NEC STATUS

EOF5 723F

2618

JC

J20

EDED E84301

2614

; MOTOR_OFF

J17:

,

LOOK FOR ERROR
LOOK FOR ERROR

2619
2620

i ----- CHECK THE RESULTS RETURNED 6Y THE CONTROLLER

2621
; SET THE CORRECT DIRECTION

EOF7 FC

2622

CLD

EOF8 BE4200

2623

HOV

SI,OFFSET NEC_STATUS

; POINT TO STATUS FIELD
; GET 5TO

EOFB Ae

2624

LaDS

NEC_STATUS

EOFC 24CO

2625

AND

AL.OCOH

JZ

J22

; OPH_OK

CHP

AL,040H

I TEST FOR ABNORMAL TERMINATION

JNZ

J16

I NOT ABNORMAL, BAD NEC

EOFE 743B

2626

HOO 3C40

2627

EE02 7529

2628

i

TEST FOR HORMAL TERI1IHATION

2629
2630

1----- ABNORMAL TERMINATION. FIND OUT WHY

2631
EE04 At

NEe_STATUS

; GET STl

HOS DO EO

2633

SAL

A.L,l

; TEST FOR EDT FOUHD

EE07 B404

2634

HOV

AH.RECORD_NOT]t.O

2632

LDOS

EE09 7224

2635

JC

J19

EEOB OOEO

2636

SAL

AL.I

EEOD DOEO

2637

SAL

AL,!

A-38

System BIOS

; RW]AlL
I TEST FOR CRt ERROR

lOC OBJ

LINE

SOURCE

EEOF 8410

2638

EEll niC

2639

Je

J1.

EEl3 ODED

2640
2641
2642
2643
2644

SAL

Al.!

EElS B408

EE17 7216
£E19 ODED

EEIB OOEO
EE10 8404

EElF nOE

AH ,BAD_CRe

HOV

2645
2646

I RW_FUl
I TEST fOR DMA OYERRlM

HOV

AH.BAD_DHA

Je

J1'

SAL

Al.l

I RW]An

SAL

Al.1
AH,RECORD_.HOTJt«l

I TEST FOR RECORD HOT FIXH)

HOV
Je

J1'

; RW]AIL

SAL

Al,!

HOV

AH. WRITE_PROTECT

j

TEST fOR NRITE_PRDTECT

EE25 7208

2647
2646
2649

Je

J1.

I

RN..FAIl.

EE27 ODED

2650

SAL

Al.I

; TEST MISSING ADDRESS HARK

EE29 B402

2bS1

HOV

AH. BAD_ADDR_HARK

Je

J1.

EE21 ODED

EE23 8403

EE2B 1202

2652

I RW]AIL

2653
2654

j----- NEe t1UST HAYE FAILED

2655
EElD

2656

Ef20 8420

2657

EElF

2658

EE2f 0&264100
E03 f87601

2659

I RW-NEC-FAIL

JIB:
HOV

AH.BAD_NEe

""

DISKETTE_STATUS,AM

I RN-FAIL

J19:

2660

2661
2662

JeD:

(;E36 C3

EE3?

2663

J21:

EEl7 E82FOI

2664

CALL

EE3,4 Cl

2665

OET

EE36

tAA1_TRANS

CALL

; HOW MANY WERE REALLY TRANSFERRED

I IU'CERR
; RET!A:!N TO CAlLER

OET

; RIII_ERR_RES
; FLUSH THE RESULTS BUFFER

RESULTS

2666
2667

;----- OPERATION WAS SUCCESSFUL

2666
~

EE3B

2669

EDB E87001

2670

CALL

NUH_TRANS

; HOW MANY GOT MOVED

EE3E 32E4

2671

J22:
XOO

AH.AH

; NO ERRORS

OPtCOK

EE40 C3

2672

RET
ENOP

2673

RI'COPN

2674

;
; NEe_OUTPUT
THIS ROUTINE SENDS A BYTE TO THE NEe CONTROLLER AFTER TESTING

2675
2676

------------------------------------------------------------------------

2677

FOR CORRECT DIRECTION At«) CONTROLLER READY THIS ROUTINE WILL

2678

TIME OUT IF THE BYTE IS NOT ACCEPTED WITHIN A REASONABLE

2679

AMOUNT OF TIME. SETTING THE DISKETTE STATUS ON COMPLETION.

2680

INPUT
(AH)

2681
2682

BYTE TO BE OUTPlIT

; OUTPUT

2663

CY

=0

SUCCESS

2664

CY

=

FAILURE -- DISKETTE STATUS UPDATED

1

2665

IF A FAILURE HAS OCCURRED. THE RETURN IS HADE ONE LEVEl :

2666

HIGHER THAN THE CALLER OF NEe_OUTPUT.

2687

THIS REMOYES THE REQUIREMENT OF TESTING AFTER EYERY

2668

CALL OF NEC_OUTPUT.

2669

(AL) DESTROYED

;------------------------------------------------------------------------

Ef41

2690
2691

EE41 52

2692

PUSH

OX

Ef42 51

2693

PUSH

ex

EE43 BAF403

2694

HOY

DX.03F4H

; STATUS PORT

EE46 33C9

2695

X""

cx.cx

I COUNT FOR TIME OUT

EE48

2696

EE46 EC

2697

IN

AL.DX

EE49 A840

2698

TEST

A.L~040H

; TEST DIRECTION BIT

EE4B 740C
EE40 E2Ft

2699
2700

JZ

J2S

I DIRECTION OK

lOOP

JU

EE4F

2701

EE4F 600E410060

2702

OR

DISKETTE_ST;'TUS, TIME_OUT

EES4 S9

2703

POP

ex

EE55 5A

2704

POP

OX

; SET ERROR CODE "NO RESTORE REGS

EE56 58

2705

POP

AX

; DISCARD THE RETURN ADORESS

EE57 F9

2706

STe

EE56 C3

2707

OET

EE59

2708

EE59 33C9

2709

EE5B

2710

EE5B EC:

2711

EESt A860

2712

TEST

A.L.060H

; IS IT READY

EESE 7504

2713

JHZ

JZ7

I YES. GO OUTPUT

EE60 E2F9

2714

LOOP

J26

I COLNT DOWN ANO TRY AGAIN

NEC_OtJTPlIT

PROC

NEAR
J SAYE REGISTERS

J23:
; GET STA.TUS

; TIME_ERROR

J24:

; INDICATE ERROR TO CALLER

J25:
XOO

Cx.cx

IN

AL.DX

; RESET THE COlWT

J26:
j

GET THE STATUS

System BIOS

A-39

LOC OBJ

LINE

EE62 EBE8

2715

EE64

2716

EE64 SA-Cit

EE66 62F5

2717
2718

EE68 EE

2719

EE69 59
EE6A SA

2720
2721

EE65 C3

2722

SOURCE
JMP

I ERROR CONO lTION

J24

J27:

; OUTPUT
MOV

I GET BYTE TO OUTPUT
I DATA PORT DFS)

Al..AH

MOV

OL.OFSH

OUT
pop

DX.AL
ex

POP

ox

I OUTPUT niE BYTE

I RECOVER REGISTERS

RET

I CY

=

0 FROH TEST INSTRUCTION

2723

NEe_OUTPUT

2724
2725
2.726

I --------------- ------------------- ------------------------------ -------I GET_PARt1
THIS ROUTINE fETCHES THE INDEXED POINTER FROM THE DISK_BASE

2727

BLOCK POINTED AT BY THE DATA VARIABLE DISK_POINTER. A BYTE FROM:

THU TABLE IS THEN I10VED INTO AH I THE INDEX OF THAT BYTE BEING

2726
2729
2730

ENDP

THE PARM IN BX
I

ENTRY --

ax = INDEX

2731

*

2732

OF BYTE TO BE FETCHED
2
IF THE LOW BIT OF BX IS ON, THE BYTE IS I/'I1EDIATELY OUTPUT

2733

TO THE NEe CONTROLLER

2734
2735

I

EXIT -AH

=

THAT BYTE FROM BLOCK

2736

,------------------------------------------------------------------------

EE6C
EE6C IE

2737

GET _PARM

2736

PUSH

OS

I SAVE SEGMENT

EE60 2BCO

2739

SUB

AX,AX

; ZERO TO AX

Ef6F 8E08

274t.
2741

MeV

DS,AX

ASSUME

DS:ABSO

EE71 C5367600

2742

LDS

2743

SHR

SI ,DIS~POINTER
BX,l

; POINT TO BLOCK

EE75 DIES

MeV

AH,[SI+BX)

; 6ET THE WORD

PROC

NEAR

fE77 6A20

2745

EE79 iF

2746

EE7,\ 72C5

EE7e C3

I DIVIDE

ex

BY 2, AND SET FLAG

I FOR EXIT

2744
POP

OS

I RESTORE SEGMENT

2747

ASSUME

DS:DATA

2748

Je

NEC_OUTPUT

RET

2749

; IF FLAG SET. OUTPUT TO CONTROLLER
I RETURN TO CALLER

2750
2751

GET_PARM
ENOP
1------------------------------------------------------------------------

2752

I SEEK

2753
2754

THIS ROUTINE WILL MOVE THE HEAD ON THE NAMED DRIVE TO THE
NAMED TRACK. IF THE DRIVE HAS NOT BEEN ACCESSED SINCE TliE

2:755

DRIVE RESET Cot1I'\ANtl WAS ISSUED, THE DRIVE WILL BE RECALIBRATED.

2756

I INPUT

2:757
2758

I

2:759
2760

I OUTPUT

lOll

!::

(CH)

= TRACK

DRIVE TO SEEK ON
TO SEEK TO

CY ::: 0 SUCCESS

2:761

CY

2.762

(AX) DESTROYED

!::

1 FAILURE -- DISKETTE_STATUS SET ACCORDINGLY

EE70

2763
2764

EE7D B001

2765

;-----.-----------------------------------------------------------------PRoe
SEEK
NEAR
MeV

EE7F 51

2:766

PUSH

ex

i

fE80 BACA

2767

MOV

CL,al

; GET DRIVE VALUE INTO CL

fE82 Oleo
Ef84 59

2:768

ROl

AL,CL

2769

pop

ex

; RECOVER TRACK VALUE

fE6S 84063EOO

2:770

TEST

AL.SEEK_STATUS

; TEST FOR RECAL REQUIRED

EE89 7513

2771

JHZ

AL,l

; ESTABLISH MASK FOR RECAL TEST

i

SAVE INPUT VALUES
SHIFT IT BY THE DRIVE VALUE

2:772

OR

J2.
SEEK_STATUS,AL

; NO_RECAL

EEBB 06063EOO
EESF 6407

2773

MOV

AH,07H

I RECALIBRATE COt1l1AND

E£91 E8ADFF

2774

CAlL

NEC_OUTPUT

; TURN ON THE NO RECAL BIT IN FLAG

EE94 BAH

2775

MOV

AH.OL

EE96 E8A8FF

2:776

CALL

NEC_OUTPUT

I OUTPUT THE DRIVE NUNBER

EE99 E87600

2777

CALL

CHK_STAT_2

EE9C 1229

2778

JC

J32

I GET THE INTERUPT AND SENSE INT STATUS
, SEEK_ERROR

Z779
2780

1----- DRIVE IS IN SYHCH WITH CONTROllER
J2:8:

EE9E

2781
2:78Z

EE9E B40F

2783

MOV

AH.OFH

EfAO E89EFF

2:784

CALL

NEC_OUTPlIT

27&5

MOV

AH.DL

EEAS E899FF

2786

CALL

NEC_OUTPUT

EfAS 6.6.E5

2787

MOV

AH.CH

fEAA E894FF

2:786

CAll

NEC_OUTPUT

EEAD E66200

2789

CALL

CHK_STAT_2

EEA3 BAH

2:790

Z791

A-40

System BIOS

I

SEEK TO TRACK

I SEEK Cot1t1AND TO NEC
I DRIVE NUMBER
I TRACK NUHBER
I GET ENDING INTERRUPT AND
;

SENSE STATUS

lOC OSJ

LINE
2:792
2793

SOURCE
; ----- WAIT FOR HEAD SETTLE

EEBD 9C

2794

PUSHF

EEBI BB1200

2795

HOV

BX.18

EEB4 E8B5FF

2796

CAL.l

GET_PARM

fEB7 51

2797

PUSH

CX

fE68

2798

I SAVE STATUS FLAGS
I GET HEAD SETTLE PARMETER
I SAVE REGISTER

J29:

; HEAD_SETTLE

1 HS lOOP

EEBS 892602

2799

MOV

tX,5S0

j

HBB OAE4

2800

OR

AH,AH

; TEST FOR TIME EXPIRED

EEBD 7406

2601

JZ

JlI
J30

J30:

EESF

Z802

EESF E2FE

2803

LOOP

EECI FEee

2804

DEC

AH

; DECREMENT THE CottfT

fEtl fBF3

2805

JHP

J29

; DO IT SOHE HORE

POP

ex

2806

EEtS
fEtS S9

2807

EEC6 90

2808

HC7

2809

EEt7 C3

J31:

o

RECOVER STATE

POPF
J32;

I SEEK_ERROR

RET

2610
2811

I DELAY FOR 1 ttS

SEEK

; RETURN TO CALLER

ENilP

2812

;-------------------------------------------------------------.----------

2813

; DHA_SETUP

2814
2815

THIS ROUTINE SETS UP THE OHA FOR READIWRITE/VERIFY OPERATIONS.
; INPUT

2816

(All

2817
2818

BYTE FOR THE DNA.

(AX) DESTROYED

2819
2820

= MODE

rES:BX) - ADDRESS TO READ/WRITE THE DATA
, OUTPUT

------------------------------------------------------------------------

;:
DNA_SETUP

EEC8

2821

EEce 51

2822

PUSH

EEC9 FA

282:3

CLI

EECA fbOC

2624

alIT

DHA+12.At

EECC 50

2625

PUSH

AX

EECD 58

2:82:6

POP

AX

EECE EbOB

DMA+ll.At

PROC

HEAR

CX

;. SAVE TIfE REGISTER
I NO MORE nrrERIWPTS
;. SET THE FIRST/lAST f / f

2:827

OUT

EEOO 6CCO

2828

HOV

AX,ES

;. GET THE ES VALUE

EED2 BI04

2829

HOV

Cl.4

; SHIFT COUNT

EE04 OKO

2830

ROL

AX,CL

EE06 8AE8

2631

I10V

CH.AL

;. GET HIGHEST NYBLE OF ES TO CH

EED8 24FO

2832

AND

At,OFOH

i ZERO THE LOW NYBBlE fROH SEGHEKT

EEDA 03e3

Ax.ax

; TEST FOR CARRY fROM ADDITION

i

OUTPUT THE HOOE BYTE

;. ROTATE LEFT

2:833

ADO

EEOC 7302

2834

JHe

J3l

EEDE FECS

2635

INC

eH

;. CARRY MEANS HIGH 4 BITS tlJST BE INC

EEEO

2836

EEEO 50

2837

PUSH

AX

; SAVE START ADDRESS

EEEI E604

J33:

Z638

OUT

DMA+4.Al

EEE3 8AC,,-

Z639

MOV

AL.AH

EEES E604

2840

OUT

DMA+4.AL

EEE7 8ACS

Z641

HOV

EEE9 240F

Z84Z

AHa

At.OFH

EEEB E681

Z843

OUT

081H"U

Al,CH

;. OUTPUT LOW ADDRESS
;: OUTPUT HIGH ADDRESS
; GET HIGH 4 BITS
; OUTPUT THE HIGH 4 BITS TO
;

2844

THE pAGE REGISTER

2645
2:846

i -----

DETERMINE COUHT

2:647
EEED 8AE6

2:848

I10V

AH.OH

EEEF 2ACO

2849

sua

At.AL

,

EEFI DIE8

2850

SHR

AX,1

;. SECTORS .. 128 INTO AX

EEF3 50

2851

PUSH

AX

MOV

EEF4 00060(1

;. NUtlBER OF SECTORS
TIMES 256 IUTO AX

2853

CALL

"""

; GET TliE BYTES/SECTOR PAR"

EEf7 E872FF
EEFA 8ACC

2854

I10V

CL,AH

, USE AS SHIFT CCIlR« (0=128. l=ZS6 ETC)

EEfC 58

2855

POP

AX

EEfO 03EO

2856

SHL

AX.CL

EEFf 48

2857

DEC

AX

J -I FOR DHA VAlUE

EfOO 50

2858

PUSH

AX

; SAVE COUNT VALUE

EFOt E605

; lOW BYTE OF COLtlT

2852

GET~PAJ!11

2859

OUT

DHA+S.AL

Ef03 8AC4

266.

I10V

AL.AH

EF05 E605

.861

OUT

DMA+5 ••U

~

nJLTIPLY BY CORRECT AI1DlIfT

; HIGH BYTE Of COltIT

Ef07 F8

2862

STI

H08 59

2863

POP

CX

o

; INTERRUPTS 8ACK ON
RECOVER COl.lfT VAlUE

EF09 58

2864

POP

AX

I RECOVER ADDRESS VALUE

HOA 03Cl

2865

ADO

AX.CX

; ADD. TEST FOR 64K OVERFLOW

EFOC 59

2866

POP

CX

j

EFOD B002

2667

MOV

Al.2

; HOOE FOR 8237

eyof E60.&.

2868

OUT

Df1A+IO.A.l

; INITIALIZE THE DISIEX
J

*

CURSOP~POSNJ

P4:

; LEt-lGTH OF BUFFER

PS:

• NO_PAGE

RET
FIt-I)_PQSITIQN

ENOP

------------------------------- ----------- ------

;

4002

; WFHTE_AC_CLlRRENT

4003

THIS ROUTINE WRITES THE ATTRIBlTTE

4004

AND CHARACTER AT THE CURRENT CURSOR

4005

POSITION
; INPUT

4007

(AH) ::: CURRENT CRT MODE

4(108

ISH) ::: DISPLAY PAGE

4009

I CX I ::: COUNT OF CHARACTERS TO WRITE

4010

IAU ::: CHAR TO WRITE

4011

(BL I ::: ATTRIBUTE OF CHAR TO WRITE

4012

IDS) ::: DATA SEGHENT

4013

I fS) ::: REGEN SEGMENT

4014

; GET ROW/COLUMN OF THU PAGE

; PAGE_LOOP

4001

4006

Z FOR WORD OFFSET

; OUTPUT

4015

NONE

4016

;------------------------------------------------

F3B9

4017

wrHTE~AC~CURRENT

F3B9 60FC04

4018

FlBC 72:06

4019

CH"
Je

F3BE 60FC07

4020

eHP

AH.7

F3Cl 7403

4021

JE

P.

AN.'

""DC

NEAR
I IS -THIS GRAPHICS

P.

I IS THIS BW CARD

F3C3 E9B201

4022

JMP

GRAPHICS_WRITE

F3C6

4023

F3C6 6AEl

4024

HOV

AH,BL

I GET ATTRIBUTE TO AH

Fle8 50

4025

PUSH

AX

I SAVE ON STACK

F1C9 51
F3eA E8DIFF

4026
4027

PUSH
CALL

ex
FIND_POSITION

; SAVE WRITE COUNT

flCD 8BFB

4028

HOV

DI.BX

I ADDRESS TO DI REGISTER

nCF S9

4029

POP

CX

I WRITE COUNT

F3DO 58

4030

POP

.X

I CHARACTER IN BX REG

P6:

; WRITE_AC_CONTINUE

System BIOS A-57

LOC OBJ

LINE
4031

nDl

SOURCE
P7:

4032

4033

j-----

WAIl FOR HORIZONTAL RETRACE

4034

F30l 8B166300

4035

MDV

DX.ADDR_6845

; GET BASE ADDRESS

nos

4036

.00

DX.6

I POINT AT STATUS PORT

83C206

4037

F30B

P8:

Floe EC

4038

IN

AL.DX

; GET STATUS

no';!

A80l

4039

TEST

Al.l

; IS IT LOW

nOB 75FB

4040
4041

JNZ

P6

F30C FA

; WA.IT UNTI L IT IS
I NO MORE INTERRUPTS

CLI

P9:

flOE
nOE EC

4042

4043

IN

Al,DX

; GET STATUS

F3DF A801

4044

TEST

Al,l

I IS IT HIGH

F3El 74FB

4045

JZ

P9

F3E3 BBel

4046

MOV

Ax.ax

F3E5 AS

4047

STQSW

F3E6 FB

4048

STI

F3E7 E2E8

4049

LOOP

P7

F3E9 E9D9fD

4050

JMP

VIDEO_RETURN

4051

; WAIT lINTI L IT IS
I RECOVER THE CHAR/ATTR
I PUT THE CHAR/ATTR
I INTERRUPTS BACK ON
A.S MANY TIMES AS REQUESTED

i

IoIRITE_AC_CLmRENT

ENDP

4052

; ---------------------------- ----------- ---------

4053

I WRITE_C_CURRENT

4054

THIS ROUTINE WRITES THE CHARACTER AT

4055

THE CURRENT CURSOR POSITION. A.TTRIBUTE

405&

UNCHANGED

4057

INPUT

4058

(AH 1

4059

(BH )

=
=

CURRENT CRT MOOE
DISPLAY PAGE

(CX l

= COUNT

'to&1

(ALI

= CHA.R

40&2

(DSI

=
=

40&0

4063
4064

(ES)

4066
4007

flEe 80FC04

4068

F3EF 7208

4069

F3Fl 80FC07

4070

F3F4 7403

4071

F3F6 E97FDl

4012

F3F9

4073

F3F9 50

4074

REGEN SEGMENT

; OUTPUT

4065
F3Ee

OF CHARA.CTERS TO ioIRITE
TO WRITE

DATA. SEGMENT

NONE
;-----------------------------------------------AH.4

C"P
JC

IS THIS GRAPHICS

PIO

C"P
JE

AH.7

IS THIS Bioi CARD

J"P

GRAPHICS_WRITE

PIO

..

PIO:
PUSH

; SAVE ON ST,l..CK

F3FA 51

4075

PUSH

CX

F3FB E8AOFF

4076

CALL

FIND_POSITION
OI,BX

SAVE WRITE COUNT

F3FE BBFB

4077

MOV

F400 59

4078

POP

CX

; WRITE COUNT

F401 58

4079

POP

6X

j

F402

40ao
4081

Pll:

4082

j-----

ADDRESS TO 01
BL HAS CHAR TO WRITE
WRITE_LOOP

WAIT FOR HORIZONTAL RETRACE

4083

F402 88166300

4064

F406 83C206

4065

F409

4086

HOV

ox • AODR_6845

I GET BASE ,l..ODRESS

.00

OX.Eo

I POINT AT STATUS PORT

P12:

F409 EC

4067

IN

AL.OX

I GET STATUS

F40A A801

40e8

TEST

AL.l

• IS IT LOW

F40C 75FB

4089

F40E FA

4090

J"Z
CLI

PlZ

F40F

4091

F40F EC

4092

IN

AL.DX

F41D A801

4093

TEST

AL.I

; WAIT UNTI L IT IS
I NO MORE INTERRUPTS

P13:
; GET STATUS
; IS IT HIGH

f412 74fB

4094

JZ

P13

• WAIT UNTIL IT IS

F414 8AC3

4095

MOV

AL.BL

I RECOVER CHAR

F416 AA

4096

STOSB

F417 FB

4097

STI

F418 47

4098

INC

01

F419 E2E7

4099

lOOP

Pll

F41B E9A7FD

4100

JMP

VIDEO_RETURN

4101

I INTERRUPTS BACK ON
; BUMP POINTER PAST ATTRIBUTE

,

AS MANY TIMES AS REQUESTED

WRITE_C_CURRENT ENDP

4102

; --------------------------- --- ---- ---- --------------------------

4103

; READ DOT

-- WRITE DOT

4104

THESE ROUTINES WILL WRITE A DOT. OR READ THE DOT AT

4105

THE INDICATED LOCATION

4106

EHTRY --

4107

A-58

I PUT THE CHAR/ATTR

System BIOS

OX

=

ROW (0-199)

(THE ACTUAL VAlUE DEPENDS QH THE MODE 1

LOC OBJ

LINE

SOURCE

4108

ex ::

4109

At. :: DOT VALUE TO WRITE (1.2 OR

COLUMN ( 0-6391 ( THE VALUES ARE HOT RANGE CHECKED)

'+

BITS DEPEf'«lING ON HOOE,

4110

REQ'D FOR WRITE DOT ONLY. RIGHT JUSTIFIED)

4111

BIT 7 OF AL=l INDICATES XOR TliE VALUE INTO THE LOCATIOH :

4112

os ::

4113

E5 :: REGEN SEGMENT

DATA SEGMENT

4114
4115

• EXIT

4116

4117

At.

= DOT

VALUE READ. RIGHT JUSTIFIED. READ ONLY

; ----------------------------------------------------------------

4118

ASSUI1E

CS;CODE.CS:OATA.ES:DATA

F41E

4119

F41E E83100

4120

CALL

R3

F421 268A.04

4121

MOV

AL.ES:lsIl

; GET TIlE BYTE

F424 22C4

4122

AND

AL,AH

) MASK OFF THE OTHER BITS IN TliE BYTE

READ_DOT

PROC

NEAR
, DETERMINE BYTE POSITION OF DOT

F426 02:EO

4123

SHl

Al.Cl

F428 BAtE

4124

NOV

CL.DH

I GET NUMBER OF BITS IN RESULT

F42:A D2eo

4125

ROl

AL.CL

j

412f>

JMP

VIDEO_RETLIRN

; RETlmN FRDM VIDEO 10

F42C E996FO

4127

I LEFT JUSTIFY THE VALUE

RIGHT JUSTIFY THE RESULT

ENIlP

4128
F42F

4129

F42:f SO

4130

PUSH

F430 50

4131

PUSH

WRITE_DOT

F431 E81EOO

4132

CALL

f434 OlES

4133

SHR

F436 22C4

4134
4135

ANII

F438 268AOC

F43B 56

4136

F43C F6C380

PROC

HEAR

"'"
""

I SAVE DOT V.t.LUE

;

TWICE

R3

i DETERMINE BYTE POSITION OF THE DOT

I SHIFT TO SET UP THE BITS FOR OlFTPUT

MOV

AL.CL
Al,AH
CL,ES:[SI I

POP

ax

; RECOVER XOR FLAG

4137

TEST

BL.80H

iISITON

F43f 7500

4138

JNZ

4139

NOT

R'AH

; YES. XOR THE DOT

F441 FbD't
F443 22C(

4140

AND

CL.AH

F445 OACI

4141

OR

Al,CL

F447

4142

f447 268804

4143
4144

MOV

ES:[SIJ,AL

; RESTORE THE BYTE IN HE/'fORY

F44A 58

POP

F448 E977FD

4145

JMP

""

; RETURN FROM VIDEO 10

Rl;

I STRIP OFF THE OTHER BITS

; GET THE CURRENT BYTE

I SET THE MASK TO REMOVE THE
j

INDICATED BITS

I OR IN THE NEW VALUE OF THOSE BITS
I FINISH_DOT

VIDEO_RETURN

F44E

4146

F44E 32Cl

4147

XOR

AL,CL

I EXCLUSIVE OR THE DOTS

F450 EBFS

4148

JMP

Rl

i

R2:

FINISH UP THE IoIOIITlHG

4149

WRITE_DOT

4150

1-------------- -------- ----------------------------------

4151

; THIS SUBROUTINE DETERMINES THE REGEN 8YTE LOCATION

4152

I OF THE INDICATED ROW COLUt1N VALUE IN GRAPHICS t1ODE.

4153

ENDP

ENTRY --

4154

OX

=

CX

= COUJrtN

ROW VALUE (0-199)

4155

I

4156

I EXIT --

VALUE (0-639)

51

= OFfSET

4158

AH

=

4159

CL == BITS TO SHIFT TO RIGHT JUSTIFY THE NASK IN AH

4157

F45Z

; XOR_DOT

4160
4161

I

4162

R3

F452: 53

4163

F453 50

4164

INTO REGEN 8UFFER FOR BYTE OF INTEREST

MASK TO STRIP OFF THE BITS OF INTEREST

DH == I BITS IN RESULT
PRoe

NEA.R

PUSH
pUSH

BX

; SAVE BX DURING OPERATION

AX

; WIll SAVE Al DURING OPERATION

4165

416f>
4167

; ----- DETERMINE 1ST BYTE IN IDICATED ROW 8Y HUL TIPL YING ROW VAlUE BY 40
j----- ( lOW BIT OF ROW DETERMINES EVEN/ODD, 60 BYTES/ROW

4168
F454 602.8

4169

MOV

Al.40

F456 52

4170

PUSH

ox

F457 BOE2FE

4171

ANO

DL.OFEH

• STRIP OFF OOD/EVEN BIT

F45A F6E2:

4172:

HUl

Dl

; AX HAS ADDRESS OF 1ST BYTE

4173
F45C SA

F450 F6C2:01

4174
4175

F460 7403

4176

F462: 05002:0

4177

F465

4178

F465 BBFO

4179

F467 58

4180

F468 88D1

4181
4182
4183

; SAVE ROW VALUE

;

OX

I RECOVER IT

CL.l

I TEST FOR EVEN/ODD

JZ

ADD

••

AX,2000H

R"i;

I JlJf1P IF EVEN ROW

; OFFSET TO LOCA.TION OF 000 ROWS
; EVEN_ROW

51.AX

; HOVE POINTER TO SI

POP

AX

I RECOVER AL VALUE

I10V

DX,ex

I COll.ltfl VALUE TO

MOV

J-----

OF INDICATED ROW

POP

TEST

ox

DETERMINE GRAPHICS HODE CURRENTLY IN EFFECT

4184

System BIOS A-59

LINE

LOC OBJ

4185

SOURCE
,--- - -------------------------------------------- ----------------

4186

; SET UP THE REGISTERS ACCORDING TO TIiE MODE

4187

I

CH

4188

CL

4189

BL

4190
4191

8M

= MASK FOR LOW Of COllJ1N ADDRESS ( 713 FOR HIGHIHED RES)
= • Of ADDRESS BITS IN COLUMN VALUE I 3/2 FOR HIM)
= MASK TO SELECT BITS fROH POINTED BYTE (80H/COM fOR HIM I
= HUMBER OF VAllO BITS IN POINTED BYTE ( lIZ FOR HIM)

; ---------- ---------------- --------------------------------------

4192

BX,leaH

F4ftA BBC002

401H

MOV

F46D 890203

4194

MOV

CX.302H

F470 803E490006

4195

eMP

CRT_MOOE.6

F475 7206

41%

JC

OS

4197

MOV

BX,180H

4198

MOV

eX.703H

F477 BB8001
F47A 890307

j

SET PARMS FOR MED RES

; HAHOLE IF MED ARES
; SET PAlms FOR HIGH RES

4199
42.00

; ----- DETERMINE BIT OFFSET IN BYTE FROM COLUMN H.6.SK

42.01

420Z

'47D

R5:

42.03

F47D Z2EA

.NO

; ADDRESS OF PEL WITHIN BYTE TO CH

CH.DL

4204

4205

j-----

DETERMINE BYTE OFFSET FOR TtlIS LOCATION IN COLUMN

4206

I SHIFT BY CORPIECT AMOUNT

F47F OlEA.

4207

SHR

DX,CL

F481 D3F2.

4208

ADO

51,OX

; INCREMENT THE POINTER

4209

MOV

DH,BH

; GET THE ,

F483 8AF7

OF BITS IN RESULT TO DH

4210
4211

;----- MULTIPLY BH (VALID BITS IN BYTE) BY CH IBIT OFFSET)

4212.

F465 2AC9

4213

F487

4214

F487 DoC8

42.15

SUB

CL,CL

; ZERO INTO STORAGE LOCATION

ROR

AL.l

;
;

4216

LEFT JUSTIFY THE VALUE
IN Al {FOR WRITE I

F489 02CO

4217

.00

CL,CH

; ADD IN THE BIT OFFSET VALUE

F488 FEef

4218

OEC

BH

j

F480 7SF8

4219

LOOP CONTROL

ONZ

R.

F48F 8AE3

4221

HOV

AH,BL

; GET HASK TO .6.H

F491 D2EC

4222

SHR

AH,CL

; MOVE THE HASK TO CORRECT LOCATION

F493 58

4223

pcp

BX

; RECOVER REG

F494 C3

422:4

RET

i ON EXIT, Cl HAS SHIFT COUNT

;

4220

42.2:5

R3

j

TO RESTORE BITS

RETURN WITH EVERYTHING SET UP

ENDP

422ft

; --- -------------- -------- ------ --------- ------------------------

422:7

; SCROLL UP

4228
4229

TIns ROUTINE SCROLLS UP THE INFORMATION ON THE CRT
; ENTRY

4230

CH,Cl

=

423l

DH ,Ol

= lOWER

BH

4233
42:34

RIGHT CORNER OF REGION TO SCROLL

VALUE FOR BLANKED LINES

LINES TO SCROLL (Al=O MEANS BLANK THE ENTIRE

FIElD)

4236
4237

DS

= DATA

ES

= REGEN

SEGMENT
SEGMENT

EXIT
NOTHING, THE SCREEN IS SCROLLED

42:39
4240

= FIll

Al = "

4,35

4238

UPPER LEFT CORNER OF REGION TO StROLL

BOrn OF THE ABOVE ARE IN CHARACTER POSITIONS

4232

j - ---------------------- ------------- ---- ---- --------- -----------

F495

4241

PROC

F495 8A06

4242

BL,Al

• SAVE LINE COUNT IN BL

F497 8BCl

NEAR

4243

AX,CX

; GET UPPER lEFT POSITION INTO AX REG

4244
4245

; ----- USE CHARACTER SUBROUTINE FOR POSITIONING

42:46

;----- ADDRESS RETURNED IS MULTIPLIED BY 2 FROM CORRECT VAlUE

42:47

F499 £66902

4248

F4<,JC BBF6

4249

HOV

DI,AX

; SAVE RESULT AS DESTINATION ADDRESS

4250
4251

1----- DETERMINE SIZE OF WIHDOW

4252

F49E 2B01

SUB

42:53

OX,CX

F4AO 61C20101

4254

AOO

OX,lOIH

• ADJUST VALUES

F4A4 00E6

4255

SAL

DH.I

; MULTIPLY. ROWS BY "

SAl

DH,I

;

4256

F4.A.6 OOE6

SINCE 8 VERT DOTS/CHAR

4257

ANO EVEN/ODD ROWS

4258
4259

j-----

DETERMINE CRT HODE

4260

F4AB 803E490006

A-60

4261

System BIOS

eMP

; TEST FOR MEDIIJ'I RES

LOC OBJ
f4AD 7304

LINE

SOURCE
JHe

4262

R7

4263

4264

1----- MEDII.J1 RES UP

'4265

*

F4AF DOE2

4266

SAL

J • COLUMNS

F481 DIE7

4267
4268
4269

SAL

I OFFSET *2 SINCE 2 BYTES/CHAR

2:. SINCE 2: BYTES/CHAR

1----- DETERMINE THE SOURCE ADDRESS IN THE BUFFER

4270

I FIND_SOURCE

R7:

F4B3

4271

F4B3 Db

4272
4273

PUSH
pop

OS

4274
4275

sue

CH.CH

SAL

BL.l

F4B9 DOE3

42:76

SAL

BL.l

F4BB 742:0

4277

RIl

I If ZERO. THEN BLANK ENTIRE FIELD

F46D 8AC3

AL.BL

J GET Nt..tIBER OF LINES IN AL

MOV

Aft.eo:

; 80 BYTES/ROW

F4tl f6E4

4278
4279
4280

JZ
MOV
MUL

F4e3 BSF7

4261

MOV

F4es 03FO

4282

ADD

AH
Sl,DI
SI,AX

,

F4e7 8AE6

4283
4284

MOV

F4B4 IF
f4SS 2AED
F4S7 DOE]

F4BF 8450

F4C9 2AE3

ES

J GET SEGMENTS BOTH POINTING TO REGEN

AH.DH
AM.aL

sue

I ZERO TO HIGH OF COUNT REG
; tRJL TIPL Y NUt1BER OF LINES BY 4

; DETERMINE OFfSET TO SOURCE
J SET UP SOURCE

ADD IN OFFSET TO IT

J tM1BER OF ROWS IN FIELD

; DETERMINE NUMBER TO HOVE

4285
4286

1----- LOOP THROUGH. MOVING ONE ROW AT A TIME. BOTH EVEN AND ODD FIELDS

4287

F4te

4Z68

F4te E88000

F4CE BIEEBOlF

4289
4290

CALL
SUB

SI.20DOH-BO

F4D2 81EFBOIF

4291

sue

DI.20DOH-80

F4D6 FEee

429Z
4293
4294

DEC

AH

F4DS 75Fl

F40A

4295
4296
4297

F4DA 8AC7

4296

F4DC

4299
4300
4301

F4ec E88800

F40F 81EFBOIF
F4E3 FEee
F4E5 75FS
F4E7 E90BFC
F4EA
F4EA BADE

R17

R9:

J CLEAR_ENTRY

HOV

AL.BH

J ATTRIBUTE TO FILL WITH

CALL
SUB

R18
01. ZOOOH-BO
BL

; CLEAR THAT ROW

RIO:

OEC

JHZ

4308
4309

JNP

HOV

BL.DH

J SET BLANK COUNT TO

R.

I CLEAR THE FIELD

R11:

J

---- ------------------------------- -- ---------.----- -- ---------

;
; SCROLL DOWN

4313

; ENTRY

THIS ROUTINE SCROllS DOWN THE INFORMATION ON THE CRT
CH.CL '" UPPER LEFT CORNER OF REGION TO SCROLL
DH.DL
LOWER RIGHT CORNER OF REGION TO SCROLL

=

4315
4316

BOTH OF THE ABOVE .... RE IN CHARACTER POSITIONS
BH = FILL VALUE FOR BLANKED LINES
AL = I LINES TO SCROLL (AL::o-Q MEANS BLANK TliE ENTIRE

4317
431B

4319

FIELD I
OS
ES

NOTHING. THE SCREEN IS SCROLLED

F4EE fO

4326
43Z7

MOV

F4Fl 8BC2

43Z6

MOV

F4F3 f60FOZ

4331
4332
4333

F4F6 BBFS

4334
4335
4336

F4F8 ZeDl

4337
4338

SEGMENT

= REGEN SEGMENT

; ---------------------------------------------------------------GRAPHICS_DOIol>l
PROC
NEAR
, SET DIRECTION
STO

F4EF 8A08

4329
433D

= DATA

; EXIT

43Z3

43Ztt
4325

EVERYTHING IN FIELD

ENDP

4314

F4EE

I EVERYTHING DONE
J BLANKJIELD

4310
4311
4312

4320
4321
43Z2

; POINT TO NEXT LINE
; NUMBER OF LINES TO FILL
; CLEAR_LOOP

R10
VIDEO_RETURN

4307
F4EC fBEC

; HOVE TO NEXT ROW

J NUMBER OF ROWS TO HOVE
I CONTINUE TILL ALL HaVED

••

JNZ

I HOVE ONE ROW

; ----- FILL IN THE VACATED LINE( S I

4302
4303
4304
4305
4306

; ROW_LOOP

R8:

J-----

BL.AL
AX.DX

; SAVE LINE COUNT IN BL
I GET LOWER RIGHT POSITION INTO AX REG

USE CHARACTER SUBROUTINE FOR POSITIONING

,----- ADDRESS RETl.II;!NED IS MULTIPLIED BY 2 FROM CORRECT VALUE

ItOV

DI.AX

J SAVE RESULT AS DESTINATION ADDRESS

;----- DETERMINE SIZE OF WINDOW

SUB

OX.CX

System BIOS

A-61

LINE

LOC OBJ

SOURCE

f4FA 81C20101

4339

ADD

F4fE OOE6

4340

SAL

DX.IOIH
OH,I

SAL

DH.l

4341

4342
4343

FSOD 00E6

4344

j -----

I ADJUST VALUES
; MULTIPLY. ROWS 5Y 4

,
,

SINCE 8 VERT DOTS/CHAR
At«)

EVEN/ODD ROWS

DETERMINE CRT MODE

4345
F502 803E490006

4346

eMP

CRT_MOOE .6

, TEST FOR HEDIUH RES

f507 7305

4347

.lHe

R12

; FIND_SOURCE_DOWN

4348

4349

J ----- MEDIUM RES DOWN

4350

F509 00E2

4351

F50B DIE7

4353

F50D 47

Dl.I

; I COLUMNS
2:. SINCE
2: BYTES/CHAR (OffSET OK I

SAL

01.1
01

I OFFSET *2 SINCE 2: BYTES/CHAR

INC

435'"
4355
4356

*

SAL

4352

,

; POINT TO LAST BYTE

; ----- DETERMINE THE SOURCE ADDRESS IN THE BUffER

4357

R12:

F50E

4358

FSOE 06

4359

PUSH

ES

J FIND_SOURCE_DOWN
J BOTH SEGMENTS TO REGEN

F50F IF

4360

POP

OS

F510 ZAEO

4361

SUB

CH,CH

I ZERO TO HIGH OF

FS12 81C7FOOO

4362

ADD

D1,240

; POINT TO LAST ROW OF PIXELS

F516 DOn

; MULTIPl Y NUMBER OF LINES BY 4

CO~T

REG

4363

SAL

FSIB Don

4364

SAL

F51A 742E

4365

JZ

F51C eAC]

4366

Mav

Bl.l
BL.l
R,.
Al,BL

FSIE 8450

4367

HOV

AH,eo

I 80 BYTES/ROW
; DETERMINE OFFSET TO SOURCE

i

IF ZERO. THEN BLANK ENTIRE fIELD

; GET HUMBER OF LINES IN At

F5Z0 F6E4

4368

NUL

F522 88F7

4369

Mav

AH
SI,O!

F524 2BFO

4370

SUB

51.AX

F526 8AE6

4371

Mav

AH,DH

i

SUB

AH,eL

; DETERMINE NUMBER TO MOVE

F528

un

4372

; SET UP SOURCE

,

SUBTRACT THE OFFSET
NUMBER OF ROWS IN FIELD

4373
4374

; ----- lOOP THROUGH. MOVING ONE ROW AT A TIME. BOTH EVEN AND ODD FIELDS

4375

Rl3:

F52A

4376

F5ZA E82100

4377

CALL

F52D 81EE5020

4378

SUB

R'7
51.20ooH+80

F531 BIEF5020

4379

SUB

DI,2000H+80

F535 FEee

4380

DEC

AN

; NUMBER Of ROWS TO I10VE

F537 75Fl

4381

JHZ

""

; CONTINUE Tl LL All MOVED

i ROW_lOOP _DOWN

4382

4383

I MOVE ONE ROW
; MOVE TO NEXT ROW

;----- FILL IN THE VACATED LINE{S)

4364

F539

4385

F539 8AC7

4386

F53B

4387

F536 E82900

4388

R14:

; CLEAR_ENTRY_DOWN

HOV

AL.BH

; ATTRIBUTE TO FILL WITH

CALL

RIC

; CLEAR A ROW

R15:

i CLHR_LOOP _DOWN

F53E 81EF5020

4369

SUB

DI.2000H+80

• POINT TO NEXT LINE

F542 FECB

4390

DEC

6L

; NUMBER OF LINES TO FILL

F544 75F5

4391

JHZ

R'5

F546 Fe

4392

CLO

F547 E976FC

4393

JMP

VIDEO_RET~H

F54A

4394

HOV

.,.

F54A MOE

RI6:

4395

JMP

4397
4398

; EVERYTHING DONE
; 6L....NKJIELO_DOWN

4396
FS4C E6E6

; CLEAR_LOOP_DOWN
; RESET THE DIRECTION FLAG

GRAPHICS_DOWN

Bt.DH

; SET BLANK COUNT TO EVERYTHING

,
i

IN FIELD
CLEAR THE FIELD

ENDP

4399
4400

;----- ROUTINE TO MOVE ONE ROW Of INFORMATION

4401
FS4E

4402

PRoe

NEA.R

FS4E 8ACA

4403

Mav

CL.Ol

F550 56

440.

PUSH

51

F551 57

4405

PUSH

01

; SAVE POINTERS

F552 F3

4406

REP

Movse

~

F554 SF

4407

PDP

F555 5E

4408

POP

01
51

F556 81C60020

4409

ADD

5I.2000H

F5SA 81C70020

4410

ADD

OI.2000H

F55E 56

4411

PUSH

F55F 57

4412

PUSH

51
01

i SA.VE THE POINTERS

FS60 8ACA

4413

MOV

(l.Ol

i COUNT BACK

F562 F3

4414

REP

Hovse

; HOVE THE 000 FIE LD

R'7

; NUHBER OF BYTES IN THE ROW

MOVE THE EVEN FIELD

F553 A4

A-62

System BIOS

; POINT TO THE ODD FIELD

LaC OBJ

LINE

SOURCE

F563 A4
F564 SF

4415

pop

FS65 SE

4416
4417

POP
RET

4416

ENDP

F5b6 C3

"17

01
SI

J POINTERS BACK

RETURN TO CALLER

i

4419
4420

1----- CLEAR A SINGLE ROW

4421
R18

PRoe

NEAR

MOV

Cl,OL

;: NUteER OF B'f'TES IN FIELD

PUSH

01

i

51058

; STORE THE NEW VALUE

'5<>7

4422

F567 8AC.
F5b? 57

4423
4424

F:S6A F3

4425

REP

4426
4427

POP

ADD

SAVE POINTER

f56B A.A

r571 57

4428

F572 BACA

4429

MOV

01
DI.2000H
01
CL.Ol

F574 F3

4430

REP

5T058

rS76 SF

4431

POP

01

F577 C3

4432
4433

Rl8

4434

; ----------------------------------------------------------------

4435

• GRAPHICS WRITE

F56C SF

F56D 81C70020

PUSH

POINTER SACK

; POINT TO OOD FIELD

fILL THE ODD FIlELD

F57S AA

RET

; RETURN TO CALLER

ENOP

4436

THIS ROUTINE WRITES THE ASCII CHARACTER TO THE

4437

CURRENT POSITION ON THE SCREEN.

4438

ENTRY

4439

.u :;:

4440

BL :;:: COLOR ATTRIBt1TE TO BE USED fOR FOOEGROIAI) COLOR

CHARACTER TO WRITE

IF BIT 7 IS SET. THE CHAR IS XOR' 0 INTO THE REGEN

4441
4442

BUFFER (0 IS USED FOR THE BACKGROUND COLOR)

4444

ex '; NUMBER OF CHARS
OS = DATA SEGMENT

4445

ES

4443

4446

f

=

TO WRITE

REGEN SEGMENT

EXIT

4447

NOTHING IS RETURNED

4448
4449

; GRAPHICS READ

4450

THIS ROUtINE READS THE ASCII CHARACTER AT THE cURRENT

4451

CURSOR POSITION ON lltE SCREEN BY MATCHING THE DOTS ON

4452

THE SCREEN TO THE CHARACTER GENERATOR COOE POINTS

4453

ENTRY

4454
4455

HONE

( 0 IS ASSl.It1ED AS THE BACKGROlW COLOR

I EXIT

.u :;:

4456
4457

CHARACTER READ AT THAT POSITION (0 RETURNED IF
NONE FOUND I

4458
4459

FOR BOTH ROUTINES. THE IMAGES USED TO FORI't CHARS ARE

4460

CONTAINED IN ROH FOR THE 1ST 128 CHARS.

4461

IN THE SECOND HALF I THE USER I'IUST INITIALIZE THE VECTOR AT

4462:

I

TO ACCESS CHARS

INTERRUPT lFH (LOCATION OQ07CHJ TO POINT TO THE USER

4463

SUPPLIED TABLE OF GRAPHIC IHAGES (6X8 BOXES).

4464

FAILURE TO DO

so

WILL CAUSE IN STRANGE RESULTS

4465
4466

; -- - - - -- - -- - - ------ --- -- ---- - - ---------- ----- - - - ----- - - --- -- ----ASSLtlE CS:CODE,DS:DATA,ES:OATA

F57a

4..7

GRAPHICS_WRITE

F57S 8400

4468

HOV

AH,O

I ZERO TO HIGH OF CODE POINT

F57A 50

4469

PUSH

IV<

I SAVE CODE POINT VALUE

PROC

NEAR

4lt70
4471

;----- DETERMINE POSITION IN REGEN BUfFER TO PUT

cooe

POINTS

4472

F57S E8MOl

4473

FS7E 88F8

4474

CALL

526

HOV

OI,AX

FIND LOCATION IN REGEN BUFFER
I REGEN POINTER IN ot

I

4475
4476

;----- DETERMINE REGION TO GET CODE POINTS FROM

4477

4478

POP

AX

I RECOVER CODE POINT

F5S1 3e60

447.

CM"

ALI80H

I IS IT IN SECOND HALF

F58] 7306

4480

JAE

Sl

I YES

F580 58

4481
4482

f58S BE6EFA

44.'

;----- IMAGE IS IN FIRST HAlF, CONTAINED IN ROM
HOV

SI.OFA6EH

F5B8 DE

4485

PUSH

CS

F589 EBOF

4486

JHP

SHORT 52

4484

; SAVE SEGMENT ON STACK

4487
4488

;----- IMAGE IS IN SECOND HALF. IN USER RA.N

System BIOS A-63

LOC OBJ

LINE

SOURCE

4489

4490

FS8B

51:

i EXTEND_CHAR

F58B 2C80

4491

SUB

Al,8DH

i ZERO ORIGIN FOR SECOND HAlF

F58D IE

4492

PUSH

DS

I SAVE DATA POINTER

F58E 2BF6

4493

SUB

51,SI

F590 aECE

4494

MOV

DS,SI

4495

ASSUHE

DS:ABSO

F5'n: C5367COO

449&

LOS

51,EXT_PTR

I GET THE OFFSET OF THE TABLE

F596 aCOA

4497

MOV

OX.OS

j

GET THE SEGMENT OF THE TABLE

4498

ASSUME

DS:DATA

4499
4500

POP

DS

j

RECOVER DATA SEGMENT

PUSH

DX

; SAVE TABLE SEGMENT ON ST.t.CK

FS9B IF
F599 52

4501
4502

I ESTABLISH VECTOR ADDRESSING

i ----- DETERHINE GRAPHICS HODE IN OPERATION

4503

; DETERHINE_MODE

52:

F59A

4504

F59A OlEO

4505

SAL

F59C DIED

F59E OlEO

4506
4507

FSAO 03FO

AX.!

I MUl TIPL Y CODE POINT

SAL

AX.1

I

SAL

AX.l

4508

ADD

51.AX

FSA2 803£490006

4509

CMP

F5A7 IF

4510

POP

OS

I RECOVER TABLE POINTER SEGMENT

F5A8 722C

4511

JC

57

I TEST FOR MEDIUM RESOLUTION MODE

VALUE BY

a

I 51 HAS OFFSET OF DESIRED CODES

CRT_MODE .6

4512
4513

;----- HIGH RESOLUTION HODE

4514
F5AA

4515

F5AA 57

4516

PUSH

DI

I SAVE REGEN POINTER

FSAB 56

4517

P1.iSH

SI

I SAVE CODE POINTER

MOV

DH,4

; NUMBER OF TIMES THROUGH LOOP

FSAC B604

4518

F5AE

4519

F5A.E At

4520

53:

I HIGH_CHAR

54:
LooSB

; GET BYTE FROM CODE POINTS

F5AF F6C380

4521

TEST

BL,80H

; SHOULD WE USE THE FUNCTION

F5B2 7516

4522

JHZ

56

I

FSB4 A.A.

4523

STOSB

F5B5 AC

452:4

LODSB

F5B6

4525

TO PUT CHAR IN

I STORE IN REGEN BUFFER

55:

MOV

F5B6 268885FFIF

4526

F5B8 83C74F

452:7

AOO

01.79

i

F5BE FECE

4528

OEC

DH

; DONE WITH LOOP

FSCO 75EC

4529

JNZ

S4

FSC2 Sf

4S30

pop

51

F5C3 SF

4531

POP

DI

I RECOVER REGEN POINTER

F5C4 47

4532:

INC

01

I POINT TO NEXT CHAR POSITION

F5C5 E2E3

4S33

LOOP

S3

I MORE CHARS TO WRITE

FSC7 E9FBFB

4534

JMP

VIDEO_RETLRN

FSCA

4S3S

F5CA 2:632:0S

4536

XOR

AL,ES:(OIl

FSCD AA

4537

STOSB

FSCE AC

4538

LooSB

FSCF 2.63285FFIF

4S39

XOO

AL,ES: (OI+2000H-l)

JMP

55

FS04 EBEO

ES:(OI+ZOOOH-l] ,AL

; STORE IN SECOND HALF
MOVE TO NEXT ROW IN REGEN

56:

4540

I EXCLUSIVE OR WITH CURRENT
; STORE THE CODE POINT
; AGAIN fOR ODD FIelD
I BACK TO MAINSTREAM

4541
4542

; ----- MEDIUM RESOLUTION WRITE

4543
F5D6

4544

F50f:, 8A03

4545

S7:

MOV

F508 DIE?

4546

SAL

01,1

; OFFSET*2 SINCE 2 BYTES/CHAR

F50A E80100

4547

CALL

Sl9

; EXPAND BL TO FULL WORD Of COLOR

FSDO

4548

• MED_RES_WRITE
DL,BL.

; SAVE HIGH COLOR BIT

58:

; HED_CHAR

F500 57

4549

pUSH

DI

; SAVE REGEN POINTER

FSDE 56

4550

PUSH

SI

I SAVE THE CODE POINTER

f5DF B604

4551

MeV

OH,4

I NUMBER OF lOOPS

S9:

FSEI

4552

F5El AC

4553

LOOSB

FSE2: ESOEOO

4554

CALL

S2l

I DOUBLE UP ALL THE BITS

FSES 23C3

4555

AND

Ax.ex

,

; GET CODE POINT

• CONVERT THEM TO FOREGROUND

4556

COLOR ( o BACK )

FSE7 F6C280

4557

TE5T

DL,80H

; IS THIS XOR FlmCTION

F5EA 7407

4558

JZ

SlD

; NO. STORE IT IN A.S IT IS

FSEC 263225

4559

XOR

AH,ES:IDIl

FSEF 26324501

4560

xc.

Al.ES: 101+1

F5F3

4561

F5F3

268&2~

FSF6 26884501

4563

MeV
MOV

F5FA AC

4564

LOO 58

F5FB E8C500

4565

CALL

A-64

i

J

DO FUNCTION WITH HALF

I AND WITH OTHER HA.LF

S10:

4562

System BIOS

ES:IDIJ.AH
ES:[DI+iJ.AL

I STORE FIRST BYTE

f STORE SECOND BYTE
; GET CODE POINT

S2l

LOC OBJ

LINE

SOURCE
; CONVERT TO COLOR
I AGAIN. IS THIS XOR FUNCTION

F5FE 23C3

4566-

AND

AX,BX

f600 F6C280

4567

TEST

DL,60H

F603 740A

4568

JZ

f6D5 2632A50020
F60A 2632850120

4569
4570

XOR
X,",

511
AH. ES: [DI+2000H I
Al. ES: [OI+2001H)

F60F

4571

F60F 2686ASOO20

4572:

I10V

fS: [DI+2DOOH ,AH I

F614 2688650120

4573
4574

, NO. JUST STORE THE VALUES

I FUNCTION WITH FIRST HALF
j

ANO WITH SECOND HALF

511:
MOV

ES: (OI+2000H+ll,.ll

5 STORE IN SECOND PORTION OF BUFFER

ADO

01,80

J POINT TO NEXT lOCA TICH

4575
4576

DEC

OH

JNZ

F620 5f

4577

POP

F6Zl SF

4578
4579

POP

59
51
01
01'

F61983(750

F61C FEtE

F61E 75Cl

F622 47
F623 47
F624 E2B7
F626 E99CFB

4580

INC
INC

4561

LOOP

4562

JHP

4583

GRAPHICS_WRITE

4564
4585

;
; GRAPHICS READ

4566

; ------

F629

4587

GRAPHICS_READ

F629 E8D600

4588

CALL

F6ZC 8BFO

4589

HOV

F6ZE S3EeD8

4590

Sill

I f!:HP GOING
I RECOVER CODE PONTER
I RECOVER REGEN POINTER
I POINT TO NEXT CHAR POSITION

01
; t10RE TO WRITE

58
VIDEO_RETURN
ENDP

------------------------------- -------- --

...

PROC

NEAR
I CONVERTED TO OFFSET IN REGEN

SI.AX

j

SP.8

; ALLOCATE SPACE TO SA.VE THE
;

4591
F631 8BEt

4592

I10V

SAVE IN SI
READ CODE POINT

, POINTER TO SAVE AREA

BP.SP

4593
4594

;----- DETERMINE GRAPHICS MODES

4595
F633 803£490006

4596

CHP

F638 06

4597

PUSH

ES

F639 IF

4598

POP

OS

; POINT TO REGEN SEGMENT

F63A nlA

4599

JC

513

j

CRT_HOllE .6

MEOIlIt RESOLUTION

4600
4601

;----- HIGH RESOLUTION RUD

4602
4603

;----- GET VALUES FROM REGEN BUFFER

AN)

CONVERT TO CODE POINT

4604
F63C 6604

4605

F63E

4606

F63E

HOV

DH.4

i tU'fBER OF PA.SSES

SIZ:

4607

HOV

Al,{SI]

I GET FIRST BYTE

F640 884600

4608

MOV

IBP] ,,U

; SAVE IN STORAGE AREA

F643 45

4609

INC

BP

• NEXT LOCATION

F644 8A8400Z0

4610

I10V

Al.lsI-tZOOOHI

; GET LOWER REGION BYTE

F648 884600

4611

HOV

(BPI,AL

; ADJUST JKl STORE

F64B 45

....

f64C 83t650
f64F FECE
F6;1 7SEB
F653 E81790

INC

461Z

4613
4615
4616

BP

ADD

51.80

DEC

DH

I

JNZ

512

; DO IT SOME HaRE

I POINTER INTO REGEN

JMP

SIS

I GO MATCH THE SAVED CODE POINTS

LOOP CONTROL

4617
4618

1----- MEOIUH RESOLUTION READ

4619
F656

462:0

F656 OlE6

46,1

SAL

51.1

1 OFF5ET*2 SINCE 2 BYTES/cHAR

F658 B60,,"

4622

513:

HOV

DH,4

, NUI1BER OF PASSES

F6SA

4623

CAll

523

ADO

5I.2000H

; GO TO LOWER REGION

CALL

; ADJUST POINTER BACK INTO UPPER

J MED_RES_READ

514:

F6SA E88800

4624

F650 81C60020

46Z6

F661 E88100

4627

F664 81EEBOIF

4628

SUS

523
SI. ZOOOH-80

F668 FEeE

4629

DEC

OH

F66A 7SEE

4630

JNZ

51'

46,5

i

I

GET PAIR BYTES FROM REGEN
INTO SINGLE SAVE

; GET THIS PAIR INTO SAVE

; KEEP GOING UNTIL ALL 8 DONE

4631
4632

; ----- SAVE AREA. HAS CHARACTER IN IT. HATCH IT

4633
F66C

4634

F66t BF6EFA90

4635

515:

j

HOV

PUSH

OI.OFFSET CRT_CHAR_GEN

FIND_CHAR

1 ESTABLISH ADDRESSING

F670 DE

4636

F671 07

4637

POP

ES

; COOE POINTS IN CS

F672 B3EDOS

4638

SUB

BP.8

I

HOV

SI.BP

CS

4639

I

F675 8BF5

4640

F677 Fe

4641

CLO

F678 BODO

4642

I10V

A~JUST

POINTER TO BEGINNING

OF SAVE AREA.

; ENSURE DIRECTION
Al.O

; CWREHT CODE POINT BEING MATCHED

System BIOS A-65

LOC OBJ

LINE

SOURCE
516:

F67A

4643

f67A 16-

4644

55

I ESTABLISH ADDRESSING TO STACK

F67B IF
ft.7e 6"8000

4645

pop

OS

; FOR THE STRING COMPARE

4646

MOV

OX.126

; NUMBER TO TEST AGAINST

F67F

4647

PUSH

517:

F67F 56

4648

PUSH

SI

I SAVE SAVE AREA POINTER

F6BO 57

4649

PUSH

DI

I SAVE CODE POINTER

F6BI 890800

4650

MOV

ex.s

; t-M1BER OF BYTES TO MATCH

F6B4 F3

4651

REPE

CMPS8

I COMPARE THE 8 BYTES

F68S Ab

F686 SF

4652

pop

F687 SE

465l

POP

SI

F688 741E

4654

JZ

518

; RECOVER THE POINTERS

DI

I IF ZERO FLAG SET. THEN MATCH OCCURRED

Fb8A FEtO

4655

INC

AL

i HO MATCH, HOVE ON TO HEXT

F68C 83C706

4656

AOD

01.8

I NEXT CODE POINT

Fb8f 4"

4657

DEC

OX

I LOOP CONTROL

f690 75EO

4658

JNZ

S17

I DO All OF THEN

4659
4660

;----- CHAR NOT MATCHED, HIGHT BE IN USER SUPPLIED SECOHD HALF

4661

F6n leOO

4662

CMP

AL,O

i Al <> 0 IF ONLY 1ST HAlF SCANNED

ft.?'" 7412

466l

JE

518

I IF :; 0, THEN All HAS BEEN SCANNED

Fb96 28tO

4664

sua

AX,AX

F6098 8E08

4665

MOV

DS,AX

4666

ASSUME

DS:ABSO

4667

LE5

DI,EXT_PTR

Fl.?A C43E7COO

aceo

ESTABLISH ADDRESSING TO VECTOR
; GET POINTER

4668

MOV

F6AO OBC7

4669

OR

AX.DI

i

F6A2 7404

4670

JZ

S18

; He SENSE LOOKING

F6A4 B080

4671

MOV

Alol28

I ORIGIN FOR SECOND HALF

fbA6 EBDZ.

4672

JMP

510

J,

4673

ASSUME

DS:DATA

F69E

AX.ES

; SEE IF THE POINTER REALLY EXISTS
IF ALL 0, THEN DeESH' T EXIST

GO BACK AND TRY fOR IT

4674
4675

i-----

CHARACTER IS FOUND ( AL:;O IF NOT FOUND )

4676
fbA6
F6AB 63C408

F6AB E917FB

4677

S18:

ADO

4678

I READJUST THE STACK, THROW AWAY SAVE

SP.8

; All DONE

JMP

4679

4680

GRAPHICS_READ

4681

;--------------------------------------------------------

4682

; EXPAND_HED_COLOR
THIS ROUTINE EXPANDS THE LOW 2: BITS IN BL TO

4683

46M

FILL THE ENTIRE ax REGISTER

4685

ENTRY

4686
4687

BL
i

COLOR TO BE USED (

LOW 2 BITS I

ex :; COLOR TO BE USED ( 8 REPLICATIONS OF THE

4689
4690
4691

=

EXIT

468a

F6AE

ENDP

2: COLOR BITS )
; ---- ------------------------------------------ ---------519
PROC
NEAR

F6AE 80E303

4692:

AND

Bl,3

; ISOLATE THE COLOR BITS

f6Bl 8AO

4693

MOV

AL.BL

; COPY TO AL

F6B3 51

4694

PUSH

CX

; SAVE REGISTER

MOV

CX,3

I NUMBER OF TIHES TO DO THIS

F684 890300

4695

f6B7

4696

FbB7 OOEO

S20:

4697

SAL

F6B9 OOEO

4698

SAL

AL.l

; LEFT SHIFT BY 2

F6BS OAD8

4699

OR

BL,AL

; ANOTHER COLOR VERSION INTO BL

F6BO E2F8

4700

LOOP

S20

; FILL ALL OF BL

F6BF BAFB

4701

MOV

SH.BL

I FILL UPPER PORTION

Ft.Cl 59

4702

POP

CX

I REGISTER BACK

Fue2 C3

4703

AL,l

; ALL DONE

RET

4704

S19

470S

1-- -- --- ------------------------ ------------------------

4706

I EXPAI'Il_BYTE

4707

ENDP

THIS ROUTINE TAKES THE BYTE IN Al AND DOUBLES

4708

ALL OF THE BITS. TURNING THE 8 BITS INTO

4709

16 BITS. THE RESULT IS LEFT IN AX

4710

;--------------------------------------------------------

Ft.C3

4711

521

F6C] 52
Ft.C4 51

PRDC

NEAR

4712:

PUSH

OX

4713

PUSH

CX

F6es 53

4714

PUSH

BX

F6C6 280l

4715

F6C8 890100

4716

F6CB

4717

F6CB 8808

4718

A-66

I SAVE REGISTERS

SUB

OX.DX

; RESULT REGISTER

MDV

ex.!

I MASK REGISTER

MOV

BX.AX

I BASE INTO TEttP

52:2::

System BIOS

LOC OBJ

LINE

SOURCE

Ft.CD U09

4719

ANIl

F6CF OB03

47Z0

OR

.,1L

eX,ex
oX,ex

I USE ttASK TO EXTRACT .. BIT
; PUT INTO RESULT REGISTER

AX,.

P6DI DlEO
r6D3 OlEl

472:1
4722
4723

SIll
I10V

CX,1

F6D5 8808

eX,AX

J BASE TO TEMP

F6D7 2309

4724
4725
4726

.NO
OR
SHl

eX,ex
oX,ax
ex.!

I PUT INTO RESULT

522

F609 OB03

F6DS DIEl

I SHIFT BASE ANJ I1ASK 8Y 1

I EXTRACT THE SAME BIT
; SHIFT ONLY MASK NON.

,

4727
F6DO 73Et

4728

JNC

FbDF 8BI;C:

47Z9

MOV

AX.OX

F6El 5B
F6E2 59

4730

pop
pop

ex
DX

4731

F6E3 SA

4732:

POP

F6E4 C3

4733

.ET

4734

521

MOVING TO NEXT BASE

I USE HASK BIT COMING OUT TO TERtUNATE
I RESULT TO PARI1 REGISTER

BX

I RECOVER REGISTERS
j

ALL DONE

ENDP

----- - -- ------------------------------------------------

4735

;

4736

I HED_READ_BYTE

THIS ROUTINE lULL TAKE 2: BYTES FROM THE REGEN

4737
4738

BUFFER. CQHPARE AGA.INST THE

4739
4740

PA.TTERN INTO THE CURRENT POSITION IN THE SAVE

4741

ENTRY

4741

SI.OS ::: POINTER TO REGEN AREA OF INTEREST
BX

4744
4745

BP

474B
4749

F6ES 8"24
F6E7 811.4401
F6EA B900CO

4752

F6ED 8200

4753

= EXPANDED fDREGROlJt-I) COLOR
= POINTER TO SAVE AREA

I EXIT

4747
f6E5

FOREGROUND

AREA

4742:

4746

C~RENT

COLOR. AND PLACE THE CORRESPONDING otVOFF BIT

BP IS INCREMENT AFTER SAVE

1--------------------------------------------------------

sa

PRoe

NEAR

4750

MOV

AH,[SI]

4751

MOV
MOV

AL.[SI+I J

• GET FIRST BYTE
; GET SECOND BYTE

eX,OCOOOH

; 2 BIT I1ASK TO TEST THE ENTRIES

"OV

OL,O

; RESULT REGISTER

F6EF

4754

F6EF 8SCI

4755

TEST

AX,CX

I IS THIS SECTION BACKGRoutI)?

F6Fl F8

4756

ele

F6F2 7401

4757

JZ

F6F4 F9

4758

F6F5 0002

4759

524:

F6F7 01E9

4760

F6F9 01E9

4761

F6FB 73FZ

4762

JNt

F6FD 885600

4763

F700 45

4764

F701 C3

4765

"OV
INC
RET

sa

; WASN'T, SO SET CARRY
; MOVE THAT BIT INTO THE RESULT

OLd
CXd

I HOVE THE MASK TO THE RIGHT BY 2: BITS

524
[SP]'OL

; DO IT AGA.IN IF HASK DIDN'T FA.LL OUT

eX,l

; STORE RESULT IN SAVE AREA

BP

t ADJUST POINTER

• ALL DONE

ENOP

---- -- ------- --------- - --- - ---------------------

4767

;

4768

; V4_POSlTION

4769

I IF ZERO. IT IS BACKGRO\H)

5ye
525:

Rel
5H.
5H.

4766

; CLEAR CARRY IN HOPES TlfAT IT IS

52S

,

THIS ROUTINE TAKES THE CURSOR POSITION

4770

CONTAINED IN THE MEHOAY LOCATION. AND

4771

CotNERTS IT INTO AN OFFSET INTO THE

4772

REGEN BUFFER, ASSUMING ONE BYTE/CHAR.

477:J

FOR MEOIUN RESOlllTION GRAPHICS.

4774

THE tuMBER MUST BE DOUBLED.

4775

; ENTRY

4776

NO REGISTERS. tfEHORY LOCATION

4777
477&

CURSOR_POSH IS USED
; EXIT

4779

AX CONTAINS OFfSET INTO REGEN BUFFER

4780

;-------~----------------------------------------

4781
478Z

52.

F702 A15000
F70S

4783

GRAPH_POSH

F705 53

4784

H02

F706 8808

4765

F70B BAC4

4786

F70A F6264AOO

4787

F70E DIEO

4788

f710 OlEO

4789

F712 ZAFF

4790

F714 03e3
F716 5a

4791
4792

F717 C3

4793
4794

.ROC
HOV

AX,CUR5OR_POSH
LABEL

; GET CURRENT CIMSOR

NEAR

PUSH
MOV
MOV

BX
8X,AX

AL.A.H

; GET ROWS TO AL

"Ul
SHl
SHl

BYTE PTR CRT_COLS

; MULTIPLY BY BYTES/COLlI'IN

AX.l
AX.!

J MULTIPLY

SUB
ADD

SH,SH

; ISOLATE COLUMN VAlUE

Ax.BX

pop

ox

• DETERMINE OFFSET
i RECOVER POINTER
; ALL DONE

RET
52.

NEAR

J SAVE REGISTER

; SAVE A COPY Of CURRENT CURSOR

*

4 SINCE 4 ROWS/BYTE

EIilP

System BIOS A-67

LOC OBJ

LINE

4795
4796

4797
4798

SOURCE

1-------------------------------------------------· ------.--------------; WRITE.TTY
THIS INTERFACE PROVIDES A TELETYPE LIKE INTERFACE TO THl: VIDEO
CARD. THE INPUT CHARACTER IS ~ITTEN TO THE CURRENT CURSOR
POSITION. AND TIlE CURSOR IS MOVED TO THE NEXT POSITION. IF THE
CURSOR LEAVES THE LAST COL~ OF THE FIELD, THE COLUHH IS SET

4799
4800

4801

TO ZERO. AND THE ROW VAlUE IS INCREMENTED. IF THE ROW VALUE

4802

LEAVES THE FIELD. THE CURSOR IS PLACED ON THE LAST ROW, FIRST
COLUMN. AND THE ENTIRE SCREEN IS SCROLLED UP ONE LINE. ItIiEN
THE SCREEN IS SCROLLED up, THE ATTRIBUTE fOR FILLING THE NEWLY

4803
4804

BLANKED LINE IS READ FROM THE CURSOR POSITION ON THE PREVIOUS
LINE BEFORE TliE SCROLL, IN CHARACTER MODE. iN G~APHICS MODE,

4805
4806

THE 0 COLOR IS USED.

4807
4808

ENTRY
(AH)

4810

(All :: CHARACTER TO BE WRITTEN

NOTE THAT BACK SPACE. CAR RET, BEll AND LINE FEED ARE HANDLED

4811

AS COMMANDS RATHER TI-lAN AS DISPLAYABLE GRAPHICS
(BLl :: FOREGROUND COLOR FOR CHAR WRITE IF CURRENTLY IN A

4612

4611

GRAPHICS MODE

4814

4615

; EXIT
ALL REGISTERS SAVED

4816
4817

;-----------------------------------------------------------------------ASSUME

4816

F7la

= CURRENT CRT f100E

4809

CS:COOE .05:DAT'"

F718 50

4619
4820

WRITE.TTY
PUSH

AX

; SAVE REGISTERS

F719 50

4821

PUSH

AX

; SAVE CHAR TO WRITE

F71A 8403

4822

AM,3

F71C 8A3E6200

482:3

BH .ACTIVE.PAGE

; GET THE CURRENT ACTIVE PAGE

Fno COlO

4820+

MOV
MOV
INT

10H

F722 58

482:5

pop

AX

; READ THE CURRENT CURSOR POSITION
; RECOVER CHA.R

PROC

NEAR

482:6

4827

1----- OX NOW HAS THE CURRENT CURSOR POSITION

4828

F723 X08

482:9

eMP

AL.6

1 IS IT .l BACKSPACE

F725 7452:

4830

JE

U8

I

F727 3eOD

4831

eMP

AL,DDH

BACI<.SPACE
; IS IT CARRIAGE RETURN

F729 7457

4832

JE

U9

I CAR.RET

FnB XOA.

4833
4634

eMP

Al,DAH

; IS IT A LINE FEED

F72D 7457

JE

U10

I

F72F 3C07

4835

eMP

AL.D7H

I IS IT A BElL

F731 745A

4636

JE

Ull

I BELL

LINEJEED

4837
4838

; ----- WRITE THE CHAR TO THE SCREEN

4639
4840
F733 840A.

4641

I10V

AH.ID

; WRITE CHAR ONLY

F735 690100

4842

MOV

CX.l

I ONLY ONE CHAR

F738 COlO

4843

INT

10H

; WRITE THE CHAR

4844

4645

; ----- POSITION THE CURSOR FOR NEXT CHAR

4846
F73A FEe2:

4847

INC

Ol

TEST FOR COLUMN OVERFLOW

f73C 3AI64AOO

4848

'MP

OL,BYTE PTR CRT_COLS

I

F740 7533

4649

JNZ

U7

; SET_CURSOR

F742 B200

4850

HOV

4651

eMP

CL.O
DH,Z4

; COLUMN FOR CURSOR

F744 SGFEIS
F747 752:A

4852

JNZ

U6

; SET.CURSOR.INC

4853
4854

; ----- SCROLL REQUIRED

4855

F749

4856

F749 6402

4657
4856

F74B COlO

Ul:
HOV

AH.2

INT

10H

; SET THE CURSOR

4859

4860

;----- DETERMINE VALUE TO FILL WITH DURING SCROLL

4861
F740 A04900

4862

MOV

'+863

eMP

Al.CRT.MOOE
AL,4

; GET THE CURRENT MODE

F75D 3e04

JC

U,

; READ-CURSOR

F752 7206

4864

F754 3C07

4865

eMP

AL.7

F756 B700

4866

MOV

BH.o

f758 7506

4867

JNE

UJ

F75A

4866

f75A. 8408

4869

F75C COlO

4870

F7Sf BAFe

4871

1'"760

4872

A-68

U2:
MOV

U3:

System BIOS

J FILL WITH BACKGROl.H)

; SCROLL-UP
I

READ-CURSOR

AH.8

INT

10H

NOV

6H,AH

; READ CHAR/ATTR AT CURRENT CURSOR
) STORE IN BH
I SCROLL-UP

LOC OBJ
n60 eaOl06
F763 ,Be9

LINE

SOURCE

487'

""V

AX.60tH

j

SCROll ONE lINE

4874

SUB

cX,CX

j

UPPER LEFT CORNER

I LOWER RIGHT ROW
J lOWER RIGHT COLUMN

F765 8618

4675

MOV

DH,24

F767 8.t.164AOO

4676
4677

"OV
DEC

OL.BYTE PTR CRT_COlS

F76B FEe..

IHT

10H

f?60

4876

F76D CDIO

4879

f76F

4880

F76F 58

4882

4863

F775 8402
F777 EBF4

POP

AX
VIDEO_RETURN

J"P

I RESTORE THE CHARACTER

I RETURN TO CALLER
I SET-CLRSOR-IHC

INC

DH

"OV
J"P

AH,2

j

U7:

4887
4868
4889

I SCROLL UP THE SCREEN
I nV-RETURN

U6:

46e4
4885

4."

I VIDEO-CALL-RETURN

U4'
U5:

4881

F770 E952FA
F773
F773 FEC6
f775

DL

HEXT ROW

J SET-CURSOR

I ESTABLISH THE NEW CURSOR

U4

;----- 8J,CK SPACE FOUH!)

4890

us:

f779

4891

f779 SOFADO

4892

C"P

Dl.o

f77C 74F7

4893

JE

U7

; SET_CURSOR

F77!;: FECA

4894

DEC

DL

I NO -- JUST HOVE IT BACK

J"P

U7

1 SET_CURSOR

F7eD EBF3

4895

I ALREADY AT Et() OF LINE

4896

F78t
F7et 8200
F784 EBEF

4897

1----- CARRIAGE RETURN FOUND

4898
4899

U9:

4900
4901
4902
4903

"OV

OL,O

; MOVE TO FIRST COll..t1H

JMP

U7

1 SET_CURSOR

; ----- LINE FEED FOUND

4904

F7a6

4905

U10:
i BOTTOH OF SCREEN

F7ab BOFEla

4906

C"P

DH.24

F789 75E6

4907
4908

JHE

U6

; YES, SCROLL THE SCREEN

JMP

Ul

J NO, JUST SET THE CURSOR

F7aa EBBC

4909
4910

;----- BEll FOlH)

4911

F7eD

4912

U11:

F760 B302

4913

HOV

F78F E67602

4914

CALL

F792 fBDB

4915
4916

4917
4918

SET UP COUNT FOR BEEP

BL.2

i

BEEP

J SOUND THE POD Bell

US

J TTY_RETURN

EHOP
J ---------------------------------------------------------------• LIGHT PEN

4919

THIS ROUTINE TESTS THE LIGHT PEN SWITCH ANO THE LIGHT

4920

PEN TRIGGER. IF 80TH ARE SET, THE LOCATION OF THE LIGHT:

4921

PEN IS DETERMINED. OTHERWISE. A RElURN WITH NO

49a
4923

INFORMATION IS HADE.
; ON EXIT

4925

(AH) = 0 IF NO LIGHT PEN INFORMATION IS AVAILABLE
ex.ex,DX ARE DESTROYED

4926

(AH)

4924

=

1 IF LIGHT PEN IS AVAILABLE

(OH,OU

4927
4928
4930

4931

= ROW.COLUMN

OF CURRENT LIGHT PEN

POSITION

4929

(CH)

= RASTER

POSITION

(ex) = BEST GUESS AT PIXEL HORIZONTAL POSITION :
1----------------------------------------------------------------

4932

ASSUHE

4933

j-----

F794

4934

VI

F794 03

4935

CS:CODE,OS:DATA

SUBTRACT_TABLE

LABEL

8YTE

08

3,3.5.5.3,3,3,4 ,

F795 03
F796 05

F797 05
F79B 03
F799 03
F79A 03

F79B Oct
F79C

PRot

4936

NEAR

4937
4936

1----- WAIT FOR LIGHT PEN TO BE DEPRESSED

4939
J SET NO LIGHT PEN RETURN CODE

4941

MOV
MOV

AH,O

F79E 88166300

DX.ADDR_6845

, GET BASE ADDRESS OF 6845

F7A2 83(:206

4942

ADD

DX.6

I POINT TO STATUS REGISTER

F79C 6400

4940

System BIOS

A-69

LINE

LOC OBJ

SOURCE
IN

FlA.5 EC

4943

FlAb A804

4944

.TE5T

F7A8 757E

4945

JNZ

4946
4947

AL.DX

I GET STATUS REGISTER

AL.4

; TEST LIGHT PEN SWITCH

V6

j

troT SET. RETURN

;----- NOlo! TEST FOR LIGHT PEN TRIGGER

4948

F7AA AaDZ

4949

TEST

AL t 2

F7AC 7503

4950

JNZ

V7A

F7U £98100

4951

JM"

V7

TEST LIGHT PEN TRIGGER
RETURN WITHOUT RESETTING TRIGGER

4952

4953

; ----- TRIGGER HAS BEEN SET. READ THE VALUE IN

4954

4955
4956

F7B1

F761 6410

V7A:

MOV

AH.16

I

LIGHT PEN REGISTERS ON 6845

4957
4958

• ----- INPUT REGS POINTED TO BY AH. AND CONVERT TO ROW COLUMN IN OX

4959
4960

tfOV

DX.ADDR_6845

I ADDRESS REGISTER FOR 6845

F787 SAC4

4~61

MOV

.... L,AH

; REGISTER TO READ

F789 EE

4962

OUT

DX.AL

; SET IT UP

F7BA 42

4963

INC

OX

F7BB EC

4964

IN

Al,OX

I GET THE VALUE

F7BC BAEe

4965

MOV

CH.AL

; SAVE IN CX

F763 88166300

4966

F7BE 4A

4967

DEC
INC

OX

F7BF FEC4

F7el 8AC4

4968

MOV

AL,AH

F7C3 EE

; DATA REGISTER

; ADDRESS REGISTER

AH

; SECOND DATA REGISTER

4969

OUT

OX.Al

F7C4 42

4970

INC

OX

F7e5 EC

4971

IN

AL,DX

• GET SECOND DATA VALUE

F7C6 8AE5

4972

MOV

AH,CH

• AX HAS INPUT VALUE

; POINT TO DATA REGISTER

4973

4974

; ----- AX HAS THE VAlUE READ IN FRaN THE 6845

4975

f7e8 8AIE4900

4976

MOV

F7ee ZAFF

4977

SUB

BH,SH

; HODE VALUE TO 6X

F7eE 2E8A.9F94F7

4978

MOV

ElL,CS:Vl[BX)

; DETERMINE AMOUNT TO SUBTRACT

F7D3 28C3

4979

sue

AX.SX

• TAKE IT AWAY

F7DS 881E4EOO

49e.0

I10V

ex, CRT_START

F7D9 DlEB

4981

SH.

Bl<,l

F70B 2Be3

4982

SUB

AX.BX

F7DD 7902

4983

JNS

v.

; IF POSITIVE. DETERtlINE MODE

F70F 25CO

4984

SUB

AX,AX

; <0 PLAYS AS 0

BL.CRT_MOOE

4985
4986

;----- DETERMINE MODE OF OPERATION

4987
;

OETERMINE~HOOE

F7El BI03

4989

MOV

CL.3

i

SET *8 SHIFT COUNT

F7E3 803E490004

4990

eM"

CIH_MOOE,4

; DETERMINE IF GRAPHICS OR AlPHA

V4

; ALPHA_PEN

F7Et

4988

V2:

F7E8 nZA

4991

JB

F7EA 803E490007

4992

eM"

CRT_MODE ,7

F7EF 7423

4993

JE

V4

F7Fl 6228

4996
4997

MOV

DL,40

; DIVISOR FOR GRAPHICS

F7F3 F6F2

4998

DIV

OL

; DETERMINE ROW( AL I AHO COLUMtH AH I

4994
4995

j-----

GRAPHICS MODE

,

4999

AL RANGE 0-99. AH RANGE 0-39

5000
5001

;----- DETERMINE GRAPHIC ROW POSITION

5002

F7F5 SAEe.

5003

MOV

CH.AL

j

SAVE ROW VALUE IN CH

F7F7 02EO

5004

ADD

CH,CH

J *2 FOR EVEN/ODD FIELD

F7F9 BADe

5005

MOV

Bl,AH

I COLUNN VALUE TO BX

5006

SUB

BH.BH

F7FO 803E490006

5007

eM"

CRT_MOOE,6

i

Fe02 7504

5008

JNE

V3

; NOT_HIGH_RES

FaD4 B104

5009

I10V

CL,4

J SHIFT VALUE FOR HIGH RES

Fa06 DOE4

5010
5011
5012:

SAL

AH,l

SHL

BX,CL

F7F8 2AFF

FaDS

FaDe D3E3

V3:

I MULTIPLY BY 8 FOR MEDIlR1 RES
DETERMINE MEDIUM OR HIGH RES

I COLI.Jt'I.l VALUE TIMES 2 FOR HIGH RES
; NOT_HIGH_RES
I MULTIPLY *16 FOR HIGH RES

5013
5014

,----- DETERMINE ALPHA CHAR POSITION

5015
faDA BAD4

5016

MOV

DL,AH

I COLUMN YALUE FOR RETURN

FaDe SAFO

5017

tfOV

OH.Al

FaDE DOEE

5018

SH.

OH,l

I ROW VALUE
I DIVIDE BY 4

Fel0 DOEE

5019

SH.

DH,l

I

A-70

System BIOS

FOR VALUE IN 0-2:4 RANIE

LOC OBJ
'812 EIU:

LINE

SOURCE

5020

I LIGHT_PEN_RETlIm..SET

SHORT Y5

J"P

5021

ALPHA HODE ON LIGHT PEN

5022
5023

i -----

Fel~

502'"

V4:

F814 F6364A.OO

5025

DIY

BYTE PTR CRT_COLS

F818 8AFO
FalA &AD4

502:6
5027

I10Y
ItOY

OH.AL
DLtAH

F8lC DUO
FalE SAEe

502:8

SAL

AL.CL

J COLS TO DL
I tlJLTlPLY ROWS • 8

5029

CH,AL

I GET RASTER VA.WE TO RETURN REG

F820 BADe

5030

ItOY
MDY

BL.A.H

J COlU1N VALUE

F822 32Ff

5031

XOII

BH,BH

F824 D3E3

5032

SAL

BX,Cl

F82:6

VS:

F826 BltOl

5033
50 ..

F828

5035

Vb:

F82852.

....

F829
F82D
F830
F8ll
f832:
F832
F833
F834
F835
F836
F837

88166300
8let07
EE

5A
SF
5E

I

;'LPH~PEN

I DETERttJNE RDW,CDLtHI VALUE
I ROWS TO OH

ax

TO

LIGHT_PEN..RETI.RN_SET
II'IJICATE EVERTHltG SET

ItOY

",1

5036

PUSM

OX

I LlGHT_PEtLRETURH
J SAVE RETURN VALUE 'IN CASE}

5037

MDY
ADD

OX. ADDR_6845

I 6ET BASE ADDRESS

OX.7

I POINT TO RESET PAR"

5039

OUT

I ADDRESS. NOT oA.TA, IS lHPORTANT

PDP

DX.AL
OX

PDP

01

5040
5041
5042:

J RECOVER VALUE

V7;

; RETURN_NO_RESET

5043
5044

POP

SI

IF

5045

POP
POP

OS

IF

IF

J DISCARD SAVED ax.CX.DX

OS
OS

IF

5046
5047

PDP
pop

OS

F838 07

5048

pop

n

F839 CF

5049
5050

j

IRET
READ_lPEN

ENlP

5051

5052

i--- INT 12 -------------------------------------------------------------

5053

; "EMORY_SIZE_DET

5DSilt
5055

I

THIS ROUTINE DETERMINES THE AI1Ot.IIT OF MEMORY IN THE SYSTE"
AS REPRESENTED BY THE SWITCHES ON THE PLAHAR.

5056

NOTE THAT THE

SYSTEM I1AV NOT BE ABLE TO USE I/O tlEHORY tNLESS THERE IS A FUll ;

5057

I

5058

I INPUT

COI1PlEt'lENT OF 64K BYTES ON THE PLAHAR.

5059

NO REGISTERS

5060
5061
5062

THE I1£MORY_SIZE VARIABLE IS SET DURING POWER ON DIAGNOSTICS
ACCORDING TO THE FOllOWING HARDNARE ASSUI1PTIONS:
PORT 60 BITS 3,2 :; 00 - 16K BASE RAM

5063

01 - 32K BASE RAH

5064
5065

10 - 46K BASE RAM

5066
5067

PORT 62 8ITS

11 - 64K BASE RAH
IN)ICATE AI10lIfr OF liD RAM IN 32K INCREMENTS

3-~

E.G •• 0000 - NO RAM IN

110 CHANNEL

0010 - 641( RAM IN I/O CHAI+IEL. ETC.

5068
5069
5070

I

SO 71
5072

; ---- - -- ----- ------- -- -.--- ----- -- ---------------------------- - ---------ASSUHf CS:CODE.DS:DATA.

F841
F841

5073

DRG
OF841H
MEttDRY.SIZE.DET PROC

F841 FB

5075

sn

F842 IE

5076

PUSH

OS
DDS

5074

, OUTPUT

(AX)

= NUtlBER

OF CONTIGUOUS lK BLOCKS OF ttEtIORy

FAR
;, INTERRUPTS BACK ON
j

SAVE SEGMENT

F843 E81302

5011

CALL

F846 A11300

5078

HOY

i GET

FM9 IF
FM. CF

5079
5080

PDP

I

5081

VALUE
RECOVER SEGI1ENT
I RETURN TO CALLER

IRET
MEMORY.SIZE.DET

ENDP

50ez

5083

1--- INT II -----------.-----------------------------------------

5084

, EQUIPMENT DETERI'lINATlOH

5085

THJS ROUTINE ATTEttPTS TO DETERnINE IliAT OPTIONAL

5086
5087

DEVICES ARE ATTACHED TO THE SYSTEM.
~

INPUT

5088

NO REGJSTERS

5089
5090

THE EQUIP.FLAG VARIABLE IS SET DURING THE POWER ON
DIAGNOSTICS USING l1IE FOLLOWING HARDWARE ASSU1PTIDNS:
PORT 60 = LOW ORDER BYTE OF EQUPMENT

5091
5092
5093

PORT 3FA

5094

PORT 378

PORT THAT

CAN BE READ AS WELL AS WRITTEN

5D95

5096

= INTERRUPT ID REGISTER OF 8250
= OUTPUT PORT OF PRINTER -- 8255

BITS 7-3 ARE ALWAYS 0

I OUTPUT

System BIOS A-71

LOC OBJ

LINE

SOURCE

5097

(AX) IS SET, BIT SIGNIFICANT, TO INDICATE ATTACHED 110

5099

BIT 13 NOT USED

5100
5101
5102

BIT 11,10,9

5.""

aIT 15,14

= SA"E

BIT 12

BIT

a

= M.ItIBER

1/0 ATTACHED

= tu1BER

BIT 7.6

= IUIIER

5104
5105
5106

BIT 5.4

= INITIAL

OF DISKETTE DRIVES
00=1, 01=2, 10=3, 11=4 ONLY
VIDEO J10DE
aD - l.NUSED
01 - 40X25 BW USING
10 - BOXIS BW USING
11 - BOXIS BW USING

5107
5108

Sla,
5110

BIT 3,2

5Ul
SU2
5113
5114

BIT 1 NOT USED

II

IF BIT 0

=I

COLOR CARD
COLOR CARD
aN CARD

PLANAR RAf1 SIZE IOO=16K,Dl=3ZK.lO=If8K,1l=6IfK)

= IPL

FRal1 DISKETTE -- THIS BIT INDICATES THAT

THERE ARE DISKETTE DRIVES ON THE SYSTEM

5115

5116
5117

OF R8232 CARDS ATTACHED

LtfUSED

5103

BIT 0

OF PRINTERS ATTACHED

NO OTHER REGISTERS AFFECTED

1------ --.. --------- --- -- -- .. - --.... - ..... - ------- ---- -------------- ---'SSUHE CS:CODE,DS:DATA.

F84D

5U8

F84D

5119

F840 FB
F8ltE IE

5120

STl

5121

I'US!t

fMF EBD70e
F852 All000
F855 IF

5122

CALL

5123
512ft

ItOV

DS
DDS
AX,EQUIP_FLA6

pop

DS

F856 CF

5125
5126

IRET

ORO

OFMOH

EQUIPMENT

'AR

PROC

I INTERRUPTS BACK ON

E~IPI1EMT

i SAVE SEGI1ENT REGISTER

I GET THE CURRENT SETTINGS
I RECOVER SEGMENT
I RETl.RH TO CALLER

E""P

5127
5128
5129

1--- INT 15 ------------------------------------------------------------DUJ1KY CASSE"E 10 ROUTINE-RETURNS 'INVALIO tHO' IF THE ROUTINE IS z

IS EVER CALLED BY ACCIDENT (AH=86H, CARRY FUG=ll

5130

'85'

f859
Fes9 f9
,asA BIt86
f8SC CAGIOG

5131
5132

i ------ ----------- .. - ------ .. --- ------ ------- ---- -- ----------- -----.. ------0F859H

5133

CASSETTE_IO

513"+

STe

DR.

5135

ItQV

5136

RET

5137

CASSETTE_ID

5138
5139
5140

..R

PROC

i CARRY INDICATOR=1

AH.86H

•,,,,,p

1---------------------------------------------------------------; NON-tuSKABLE INTERRUPT ROUTINE:

THIS ROUTINE WILL PRINT A PARITY CHECK 1 OR 2 I1ESSAGE :

5141
5142

AND ATTEMPT TO FIND THE STORAGE LOCATIOH CONTAINING THE

5143

BAD PARITY.

IF FOUND. THE SEGMENT ADDRESS WILL BE

IF NO PARITY ERROR CAN BE FDUHD (INTERI1ITTANT :

5144

PRINTED.

5145

READ PROBLEtU !?!?1<-WILl BE PRINTED

~ERE

THE ADDRESS

5146

WtlJLD NORttALLY GO.

51ft7

IF ADDRESS IN ERRCII IS IN THE 110 EXPANSION ICDC , THE
ADDRESS WILL BE FOLLOWED BY A '( E)'

5148
5149

f

IF IN SYSTEI1 UNIT,

A '(S)' WILL FOLLOW THE ADDRESS

5150

F85F

1-----------------------------------------------------__________ _

5151

Nt1~INT

PROC

NEAR

5152

ASSlR1E

DS:DATA

F85F 50

5153

PUSH

AX

F860 £462

5154

IN

Al.PCRT_C

F862 ASCO

515S

TEST

AL,OCOH

F864 7503

5156

,

5157

JHZ
JH"

.10

fS69 BA4000

5159

I10V

DX,DATA
DS,OX

...

F866 E98700

5158

; SAVE ORIG CONTENTS OF AX
I PARITY CHECK1

HHI_l
I NO, EXIT FROM ROUTINE

NHI_l:

f86C SEDA

5160

F86E BE 15F990

5161

HOV
ItOV

51 ,OFFSET 01

I ADOR QF ERROR MSG

F872 A840

5162

TEST

AL,40H

I I/O PARITY CHECK

F874 7504

5163

JHZ

013

I DISPLAY ERROR IiSG

F876 8£25F990
f87A
F87A 8400
F87C AQ4900

5164

ItOV

51.0FFSET D2

I I1UST BE PLANAR

5166

HOY

AH.O

I INIT AtI:I SET ttODE FOR VIDEO

5167

HOY
INT

ALICRT_MODE

5168

IOH

J CALL VIDEO_IO PROCEDURE

5169

CALL

p_1ISG

I PRINT ERROR t1SG

f87F tolD
F881 E84601

5165

5170
5171
5172

F884 8000

A-72

D13:

i----- SEE

5171

System BIOS

IF LOCATION 'mAT CAUSEO PARITY CHECK CAN BE FOUND

J DllUlLE TRAP

LOC OBJ

LINE

SOURCE
OACH,AL

FM6 E6 ... 0

5174

F88S £461

5175

IN

AL.PORT_B

F8SA oe30

5176

OR
OUT

FeaE 24CF

5177
5178

F890 E661

5179

OUT

AL.OOI10000B
PORT_B.U
AL.ll001111B
PORT_B,Al

Fan 861 E1300
F896 Fe

5180

HOV

8X,ME/1ORY_SIZE

; GET MEMORY SIZE WORD

5161

eLD

F897 2802

5182

SUB

OX,OX

, POINT DX AT START OF HEN

F899

5183

F899 aEDA.

5184
5185

F8St E661

F89B 8EC2
f89D 890040

F8AO 2BF6

5'86
5187

F8A2 F3

5168
5189

OUT

AND

I TOGGLE PARITY CHECK ENABLES

; SET OIR FLAG TO INCRIMENT

NMI_LOOP:
MOV

OS,OX

HOV

ES,DX

MOV

CX,4000H

SUB

SI,SI

J SET FOR 16KB SCAN
j:

SET 51 TO BE REALlIVE TO

; START OF fS
REP

loose

IN

AL,PORT_C

i

f8A6 24CO

5190
5191

AN!)

F8A8 7512

5192

JNZ

AL.IIOOOOOOB
PRT_NMI

; GO PRINT ADDRESS IF IT DID

DX,0400H

I POINT TO NEXT 16K BLOCK

; READ 16KB OF MEMORY

FaA] At
F8A4 E462

5193

ACO

FeAE 83E810

5194

SUB

ex.16D

FaBl 75E6

5195

JHZ

NHI_LOOP

FeAA 61C20004

F8B3 BEJ5F990

5196

HOV

51'( OFFSET

F8B7 E8100l

5197

C.t.Ll

P_HSG

f8BA FA

5198

eLI

f88S F4

HlT

F8SC

5199
5200

F8BC BCD.t.

5201

MOV

FBBE E81907

5202
5203

CAll

PRT_SEG

F8CI BA1302

MOV

OX.0213H

F8C4 BOOO

5204

HOV

D~.t.1

SEE IF PARITY CHECK HAPPENED

, PRINT ROW OF ????? IF P.t.RITY
; CHECK COULD NOT BE RE-CREATED
; HALT SYSTEM

PRT_tI1I:
OX.DS
i

PRINT SEGHEHT v .... LUE

; DISABLE EXPANSION BOX

F8C6 EE

5205

OUT

FBt7 B026

5206

MOV

AL.OO
OX.AL
AL.'( ,

F8C9 E6DOOO

5207

CALL

Pin_HEX

Face B85AAS

5208

HOV

AX.OAS5AH

FSCF 89ca

5209

MOV

CX.AX

FaDl 2808

5210

SUB

eX.8X

F8D3 8907
F8D5 90

5211

HOV

lexl.AX

5212

NtP

FBD6 90

5213

NOP

FaD7 8B07

5214

MOV

AX,[BX)

; HAD THE ERROR

F8D9 3BCl

5215

eHP

AX,CX

; IS IT THERE?

faDB 7407

5216

JE

SYS_BOX_ERR

, YES- MUST BE SYS IJUT

F80D 8045

5217

HOV

Al.'E'

; NO-MUST BE IN EXP. BOX

F8DF E8BAOO

5218

CAll

PRT_HEX

FeE2 E805

5219

JMP

SHORT HlT_NMI

FBE4

5220

FBE4 8053

5221

F8E6 f68300

5222

F6E9

5223

F8E9 8029

5224

F8Es E8AEOO

5225

F6EE FA.

5226

ell

F8EF F4

522:7

HlT

MeV

AL, '5'

CALL

PRT_HEX

HOV

AL.' )'

CALL

PRT_HEX
I HALT SYSTEM

D14:

5228

F6FO 58

52:29

POP

52:30

IRET

5231

NMI_INT ENDP

5234

; WRITE A WORD TO SEGMENT rnA T

HLT_HMI:

F8Fl CF

5233

AX

i RESTORE ORIG CONTENTS OF AX

.-------- -------------------------------

RDS CHECKSUM SUBROUTINE

52:35

j----------------------------------------

F6F2

5236

ROS_CHECKSUM

F8F2 890020

5237

FeF5

5238

F8F5 32CO

5239

FeF7

5240

(CAN'T WRITE TO MEHI

SYS_BOX_ERR:

F6FO

5232:

,

MeV

PROC

NEAR

eX,Bl92

ROS_CHECKSUH_CNT:

XOR

A.L,AL

; NEXT_ROS_r'lODULE
; HUMBER OF BYTES TO ADD
; ENTRY FOR OPTIONAL ROS TEST

C26:

f8F7 0207

52:41

ADO

.U,DS:[BX]

F6F9 43

5242:

INC

BX

o POINT TO NEXT BYTE

F6FA E2FB

S243

LOOP

eo.

j

F8FC OACO

52:44

OR

Al,AL

; SUN = 01

F8FE C3

5245
5246
5247
5248
52:49

ADD ALL BYTES IN ROS I10DULE

RET

ROS_CHECKSlJt1
;

ENDP

-------------_.-. ----. ---- ---- - --------HESSAGE AREA. FOR POST

J - - ---- - -- - - - - - -- ---- - ----- -- - -- --- ------

System BIOS A·73

LaC OBJ

LINE

F8FF 313031

SOURCE

5250

EO

DB

'101'.13010

, SYSTEM BOARD ERROR

5251

El

DB

• 201' ,13.10

I MEMORY ERROR

5252

nA

DB

'ROM',n.IO

• ROM CHECKSUM ERROR

5253

no

DB

'1801' ,13.10

5254

01

DB

'PARITY CHECK 2' .13.10

5255

D2

DB

'PARITY CHECK l' .13,10

5256

D2A

DB

'??'?1?',13.10

F90Z 00
F90J 0",

F904 20323031
F90S 00
F909 0"'
F90A 524F4D

F90D 00

F90E OA

F90F 31383031

EXPANSION IO BOX ERROR

F913 00
f914 OA

f915 50415249545920
43484543452032
F923 00
F9Z4

o.

F925 504152:49545920

434&4543482031
F933 00

F934 0"
F935 3F3F3F3F3F
F93A 00
F93B OA
5257

5258

; ----------------------- -- ---- ------------------------ - --------- --- ------ ---

5259

BlIHK lEO PROCEDURE FOR MFG RUN-IN TESTS

IF lEO IS ON. TURN IT OFF. IF OFF. TURN ON.

5260
5261

j---------------------------------------------------------------------------

5262
F93C

5263

f93C FB

5264

F93D SO

ASSln1E
BLINK_INT

OS:O,6.TA
PROC

NEAR

sn

5265
5266

PUSH

AX

; SAVE AX REG CONTENTS

F93E [461

rH

Al.PORT_B

; READ CURRENT VAL OF PORT B

F940 8AEO

5267

MOV

AH.Al

F942 FoOD

5268

NOT

AL

F944 2440

5269

AND

Al,OlOOOOOOB

I

ISOLATE CONTROL BIT

F946 60E4Bf

5270

AND

AH.IOIlllllB

j

MASK OUT OF ORIGINAL VAl

F949 OAC4

5271

OR

AL.AH

; OR NEW CONTROL BIT IN

F948 Eb61

5272

OUT

PORT_S.AL

F94D 5020

5273

MOV

AL.EOI

f94F f620

5274

OUT

INTAOO .AL

F951 58

5275

POP

AX

F9S2 CF

5276
5277

; FLIP All BITS

; RESTORE AX REG

IRET
BLINK_INT

ENOP

5278
5279

-- ------- ---- - ---- - - ---- --- --- ----- ----- -- -- -----

5280

THIS ROUTINE CHECKSUMS OPTIONAL ROM MODULES AND

5281
5282

IF CHECKSUH IS OK, CALLS nUT/TEST CODE IN MODULE
; -- --- - ------------------- ------------------ -------------

F953

5283

PROC

f953 884000

"84

AX. DATA

F956 8Eeo

5285

F956 2AE4

5286

NEAR

I POINT ES TO DATA ....RE ....

ES.AX
SUB

.6.H.AH

; ZERO OUT AH

F95A 8A4702

5287

MOV

.... L.[BX+zl

I GET LENGTH INDICATOR

F95D BI09

5288

MOV

CL.09H

; MULTIPLY BY 512

F95F 03EO

5289

SHL

AX.Cl

f961 8eca
F%351

5290
5291

PUSH

CX

I SAVE COUNT

F964 890400

5292

MOY

CX.4

I ADJUST

F967 03E8

5293
5294

SHR

AX.CL

F969 0300

ADD

DX.AX

F96B 59

52:95

POP

CX

; RETIUVE COUNT

ROS_CHECKSUH_CNT

I 00 CHECKSUM

HOV

CX.AX

; SET COUtH

; SET POINTER TO NEXT MODULE

F96C E886FF

5296

CALL

F96F 7406

5297

JZ

F971 E857EO

5298

CALL

ROM_ERR

; POST CHECKSUM ERROR

F974 EB1490

5299

Jt1P

ROH_CHECK_EHD

; AND EXIT

F977
F977 52
F978 26C70667000300

5300
5301

PUSH

OX

I S,AVE POINTER

5302

HOV

ES: IO_ROM_INIT. 0003H

LOAD OFFSET

F97F 268ClE6900

5303

MOY

ES: IO_ROI'CSEG ,OS

LOAD SEGMENT

F984 26FFlE6700

CALL

DWORD PTR ES:IO_ROM_INIT

F989 SA

5304
5305

POP

OX

f'98A

5306

F'98A C3

5307

5308
5309

A-74

System BIOS

I CALL INIT ./TEST ROUTINE

I RETURN TO CALLER

RET
ENDP

LaC OBJ

LINE

SOURCE

5310

J ------------------- -----------------------------

5311

; CONVERT AND PRINT ASCII CODE
At MUST CONTAIN NUtlBER TO BE CONVERTED. :

5312
5313

AX AND

ax

DESTROYED.

5314

1------------------------------------------------

F98B

5315

XPC_BYTE

F98e 50

5316
5317

PUSH

AX

I SAVE FOR LOW NIBBLE DISPLAY

F96C 8104

ItOV

CL.4

i SHIFT COUNT

f98E 02E8

5318

SHR

AL.CL

1 MYBBlE SWAP

F990 E80300

5319

CALL

XLAT_PR

I DO THE HIGH NIBBLE DISPLAY

F991 58
f994 240F

5320

pop

AX

I RECOVER THE NIBBLE

5321

AND

AL.OFH

I

NEAR

I

AL.O~OH

I ADD FIRST CONVERSION FACTOR

PROC

NEAR

5322
f"996

532:3

F996 0490

5324

F998 27

5325
5326
5327

F99C

5328

F99C B40E

5329

F998 27

F999 1440

ISOLATE TO LOW NIBBLE

I FALL INTO LOW NIBBLE CONVERSIOH

XLAT_PR PRot

ADD
DAA
ADC

Al.,040H

I ADD COt-lVERSION AI'I> ADJUST LOW NIBBLE

DAA

I ADJUST HIGH NIBBLE TO ASCHI RANGE

HEAR

PRT_HEX PROC

F99E B700

5330

F9AO COlO

5331

MOV
MOV
IHT

F9A2 C3

5332:

RET

CONVERT OO-OF TO ASCII CHARACTER

I ADJUST FOR tM1ERIC ANI) ALPHA RANGE

AH.14

J DISPLAY CHARACTER IN Al

BH~O

IOH

5333

PRT_HEX ENDP

5334

XLAT_PR EHOP

5335

XPC_BYTE

ENDP

5336
F9A.3

5337

F9,6,3 BC03

5338
5339

F9A5 7803

F9A7 7802

5340

F9.\9

5341
5>42

F.

LA.BEL

WORD

DW

36CH

DW

F'E

• PRINTER SOURCE TABLE

378H

DW

278H

lABEL

WORD

5343

i--------------------------------------------------------

5344

i THIS SlI5ROUTINE WILL PRINT A MESSAGE ON THE DISPLAY

5345
5346

I ENTRY REQUIREMENTS:
Sl

= OFFSETCADDRESSJ

5348

ex

=

5349

MAXIt1UM MESSAGE LENGTH IS 36 CHARACTERS

5347

MESSAGE BYTE

OF MESSAGE BUFFER

CO~T

5350

1--------------------------------------------------------

F9A9

5351

E_HSG

PROC

NEAR

F9A9 BBEE

5352

MOV

BP,SI

f SET BP NON-ZERO TO F LAG ERR

F9AB E8ICOO

5353

CALL

P_MSG

1 PRINT MESSAGE

F9AE IE

5354

PUSH

F9AF EBA700

DS
DDS

5355

CALL

F9BZ AOI000

5356

MOV

F985 2401

5357

F967 750F

5358

F969

5359

F989 FA

5360

eLI
HOV
OUT

F9BA B069

5361

F9BC E663

5362

f9BE BOB5

5363

F9CO E661

5364

F9C2: A01500

5365

F9C5 E660

5366

F9C7 F4

5367

F9C8

5368

F9C8 IF

5369

F9C9 C3

5370

....,

"'L.OIH

1 SHITCH ON?

JHZ

G12

j

AL.BYTE PTR EQUIPJLAG

i YES •

MOV
OUT

AL.I000010IB

I DISABLE KB

HOV
OUT

AL.MFG_ERRJLAG

1 RECOVER ERROR ItI)ICATOR

PORT_.... AL

HlT

I SET INTO 8255 REG
1 HALT SVS

G12:

POP

5371

E_MSG

RET
EHOP

,,"oe

5372
5373

P_MSG

5374

GIZA:

F9CA 2E8A04

5375
5376
5377

HOV

AL.eS:ISIJ

ItIC
PUSH

51
AX

5378

CALL

F902 58

5379

POP

F9D3 3eOA

5380

F905 7!iF3

5381

CMP
JHE

F907 C]

538Z
5383

HALT SYSTEI'1

AL.89H
CND_PORT.AL

F9CA

F9CF ESCAfF

NO - RETURN

MFG_HALT:

f9CA

f9CD 46
F9CE 50

1 lOOf'IHALT ON ERROR

P_MSG

HEAR

AX
"'L,lO
612A

PUT CHAR IN At
POINT TO NEXT CHAR
I SAVE PRINT CHAR
I RECOVER PRINT CHAR
; HAS IT LINE FEED?
; NO,KEEr PRINTING STRING

RET
nllP

5384
5385
5386
5387
53a8

1-----------------------------------------------INITIAL RELIABILITY TEST -- SUBROUTINES
1------------------------------------------------

i

ASSUHE

CS:COOE,OS:OATA

System BIOS A-75

LINE

LOC OBJ

5369

SOURCE
• ----------- ------------ ------------ -------------

5390

5391

SUBROUTINES FOR POWER ON DIAGNOSTICS

1------------------------------------------------------------------------

5392

THIS PROCEDURE WILL ISSUE ONE LONG TONE (3 SECS) AND ONE OR

5393

MOOE SHORT TONES (1 SEC) TO UIlICATE A fAILURE ON THE PLANAR

5394

BOARD, A BAD RAM MODULE, OR A PROBLEM WITH THE CRT.

5395

; ENTRY PARAMETERS:

DH ;; tM1BER OF LONG TONES TO BEEP

5396
5397
5398

Dl = HlIt1BER OF SHORT TONES TO BEEP.
1-------- -------------------------------------------------- --------------

530;19

F9D8
F9D8 9C

5400

PUSHF

F9D9 FA

5401

CLI

F9DA IE

5402

PUSH

F9DB £87800

; SAVE FLAGS

DISABLE SYSTEM INTERRUPTS

i

I SAVE OS REG CONTENTS

OS

5403

CALL

ODS

F9DE DAFb

5404

OR

DH,DH

; ANY LONG ONES TO BEEP

F9EO 7414

JZ

G3

; NO, DO THE SHORT ONES

F9EZ 8306

5405
5406
5407

F9E4 f82100

5408

F9EZ

;

61:
BL,6

I COUNTER FOR BEEPS

CALL

BEEP

; DO THE BEEP

G2:

F9E7

5409

F9E7 E2FE

5410

LOOP

G2

F9E9 FEeE

5411

DEC

DH

DElAY BETWEEN BEEPS
ANY MORE TO DO

I DO IT

F9EB 75F5

5412

JNZ

61

F9ED 803EIZ0001

5413

CHP

MFG_ TST ,1

F9F, 7502

5414

JNE

63

F9F4 EBC3

5415
5416

F9F6

LONG_BEEP:

MOV

MFG TEST MODE?
YES - CONTINUE BEEPING SPEAKER
STOP BLINKING LED
I

SHORT_BEEP:

NOV

BL,I

COUNTER FOR A SHORT BEEP

CALL

BEEP

00 THE SOUHO

LOOP

G4

i

DEC

DL

1

f9F8 E80DOO

5417
5418

F9FB

5419

F9FB E2:FE

F9FD FEeA

5420
54,1

F9FF 7SFS

5422

JHZ

63

00 SOME MORE

lOOP

G5

LONG DELAY BEFORE RETURN

F9F6 8301

FAal
FMl E,FE

5423

FAD3

5425

FAD3 E2FE

5426

G4:
~ONE

WITH SHORTS

65:

5424

66:
LOOP

66

FADS IF

5427

POP

os

FA06 90

5428

POPF

5429

RET

FAD7 C3

DelAY BETWEEN BEEPS

I RESTORE ORIG CONTENTS OF OS
; RESTORE FLAGS TO OIUG SETTINGS

; RETURN TO CALLER
ENOP

5430
5431
5432

;----- ROUTINE TO SOUND BEEPER

5433
FAD8 8086

5434
5-435

MDV

AL,lOllOliUB

; SEL TIM 2.LSB,I1SB,BINARY

FADA £643

>436

OUT

TIHER+3,AL

, WRITE THE TIMER HOOE REG

FADe B83305

5437

MOV

AX,533H

J DIVISOR FOR 1000 HZ

FAOF £642

5438

OUT

TlHER+2,AL

I WRITE TIMER 2 CNT -

fAll 8AC4
FAl3 E642

5439

"DV

AL.AH

OUT

TIMER+2,AL

FADe

BEEP

5440

PROC

HEAR

LSB

• WR ITE TIMER 2 CNT - MS8

FAlS £461

5441

IH

AL,PORT_B

; GET CURRENT SETTING OF PORT

FAl7 8AEO

S44Z

MOV

AH.AL

; SAVE THAT SETTIHGH

FA19 OC03

S443

00

FAlS E661

5444

OUT

FAlD 28e9

5445

SUB

cX,ex

FAIF

5446
5447
5446

LOOP

G7

J DELAY BEFORE TURNING OFF

DEC

BL

; OELAY CNT EXPIREO,?

FA-IF E2FE
FA21 FEee

; TURN SPEAKER ON
; SET CNT TO WAIT 500 MS

G7;

5449

JNZ

67

; HO - CONTINUE BEEPING SPK

FA2S 8AC4

5450

MOV

AL,A.H

; RECOVER VALUE OF PORT

FA27 E661

5451

OUT

FA29 C3

5452

FAll 7SFA

5453

; RETURN TO CALLER

RET
BEEP

ENOP

5454

5455

FA2A

1------------------------------------------------------------------------

5456

THIS PROCEDURE WILL SEND A SOFTWARE RESET TO TIlE KEYBOARD.

5457

SCAN CODE

'AA' SHOULD BE RETURNED TO THE CPU.

5458

1------------------------------------------------------------------------

5459

KBD_RESET

5460

ASSUME

PROt

NEAR

OS: ABSO

; SET KBD CLK LINE LOW
I WRITE 8255 PORT B

fA2A BODe

5461

"OV

AL,DSH

FA2e E661

5462

FAZE 89562:9

5463

OUT
MOV

CX,10582

1 HOLD KBO CLK LOW FOR 20 HS

FA31

5464
5465

LOOP

G8

J lOOP FOR 20 MS

FBI E2FE

A-76

PORT_B,AL

68:

System BIOS

LOC OBJ

LINE

SOURCE
HOV

FAl3 Boce

5466

fAJS E661

5467

FAl7

5468

FA37 8048

5469

FA39 E661

5470

OUT

P(}RIT_B.U

FA3B BOFD

5471

HOV

AL,OFDH

I ENABLE KEYBOARD INTERRUPTS

FA1D E621
FAlf C606660400

5472

OUT

INTAOt .... t

I WRITE 6259 IHR

5473

MOV

DATA_AREA[OFFSET INTR_FLAGI

fA44 FB

5474

STI

FA45 2BC9

5475

, SET CLK. ENABLE LINES HIGH

OUT
) ENnn FOR MAt-lJF...CTlRING TEST 2
~ SET KBD CLK HIGH. EHABLE lOW

SP_TEST:

MOV

AL,4eH

I RESET INTERRUPT INDICATOR

I ENABLE INTERRUPTS

SUB

CX,CX

fA47

5476

FA47 Fb066BD4D2:

5477

TEST

DATA_AREA[OFFSET 1NT RJLt.Gl,02H ; DID J. KEYBOARD IHTR

FA4C 7502

5478

JNZ

GIO

; YES - READ SC...N CODE RETUrNED

FA4E E2F7

5479

LOOP

G9

I NO - LOOP TILL TIMEOUT

FASO

5460

f SETUP INTERRUPT TIMEOUT CNT

GI0:

fA50 E460

5461

FAS2 BADS

5482

MOV

BL,Al

fA54 Boce
FAS6 E661

5483

HOV

AL,DCSH

5464

OUT

PORT_B.Al

FASS C3

54&S

RET

FA59

5486

FA59 50

5486

acetin

I READ KEYBOARD SCAN CODE

IN

; SAVE SCAN COOE JUST READ
I CLEAR KEYBOARD

I RE~N TO C"'LLER

KBD_RESET

ENDP

DDS

NEAR

5467
PROC

5489

PUSH

fASA 884000

5490

110V

AX,OAT.4.

FASO SEOS

5491

HOV

DS,AX

I

FASF 58

5492

POP

AX

I RESTORE A.X

FAbO C3

5493
5ct94

I SAVE AX

A}(

SET SEGMENT

RET
DDS

ENOP

5495
5496
5497
5498
FA6E

5499

FA6E

5500

1-----------------------------------------------------------------------CHARACTER GEHERATOR GRAPHICS FOR 320X200 ..tJ.Il 640X200 GRAPHICS
1-----------------------------------------------------------------------ORG
CRT_CHAR_GEN

OFAbEH
LABel

BYTE

oooooooooooaoooo

5501

DB

OOOH, OOOH,eOOH, ooaH, OOOH, OOOH, OOOH, OOOH ; o_o0

FA76 7E81A581B099817E

5502

DB

07EH,081H,O"'5H,061H,OBOH,099H,061H,07EH I 0_o1

FA6E

FA.7E 7EFFDBFFC3E7FF7E

5503

DB

07EH,OFFH,OOBH,OFFH,OC3H,OE7H.OFFH.07EH J D_02

FASE> 6CFEFEFE7C381000

5504

DB

06CH,OFEH,OFEH,OFEH,07CH,036H.DI0H.OOOH ; 0_03

FA8E l0187CFE7C3elOOD

5505

DB

010H,038H,07CH.OFEH.07CH,038H,OI0H,OOOH ; D_04

FA96 387C18FEFE7C387C

5506

DB

038H,07CH.038H,OFEH,OFEH,07CH,038H,07CH ; D_05

FA9E lOl0367CFE7C387C

5507

DB

OlOH,DIOH.03eH.07CH.OFEH.07CH.03BH.07CH I D_06

FUb 0000183C3C180000

5506

DB

OOOH,OOOH,OI8H.03CH,03CH,OI8H,OOOH.OOOH ; o_o7

FAAE FFFFE7C3C3E7FFFF

5509

DB

OFFH,OFFH,OE7H,OC3H,OC3H,OE7H,OFFH,OFFH ; D_08

FAS6 003C664242:663COO

5510

DB

OOOH,D3CH.066H.042H,042:H,066H.03CH,oODH ; o_09

FABE FFC399BOBD99C1FF

5511

DB

OFFH,OC3H,099H.OBDH.DBOH,099H,OC3H.OFFH I 0_0'"

FAC6 OF07DF7DCCCCCC78

5512

DB

OOFH,007H,OOFH.07DH,OCCH.OCCH,OCCH.1l78H 10_DB

FACE 3C6666663C187E16

5513

DB

03CH,066H,066H,066H,03CH.OlSH,07EH.OIBH

FADb 3F333F303070FOEO

5514

DB

03FH,033H.03FH,030H,030H.070H.OFOH,OEOH ; D_OD

fADE 7F637F636367E6CO

5515

DB

07fH,063H,07FH.063H,063H.067H.OE6H,OCOH

FAE6 99SA,3CE7E73C5A99

5516

DB

099H,05AH.03CH.OE7H,OE7H.03CH,05AH.099H ; D_Of

fAEE 80EOF8FEF8EOeOOO

5517

DB

060H,OEOH,OF8H.OFEH,OFBH,OEOH,080H,OOOH ; o_10

FAF6 020E3EFE3EOE0200

5518

DB

002H,OOEH.03EH.OFEH.03EH,OOEH,0021-1.000H ; 0_11

FAFE 183C7E18187E1C18

5519

DB

018H,03CH.07EH.OIBH,Dl8H,07EH,03CH.016H J. o_12

FB06 6666666666006600

5520

DB

066H,066H,066H.066H,066H.ODOH,066H.DOOH ; 0_13

j

j

D_OC
D_OE

FBDE 7FDBDB7BIBIBIBOO

5521

DB

07FH,00BH.ODBH.07BH.OIBH,OlBH,OlBH,OOOH J 0_14

FB16 lE63386C6C36CC78

5522

DB

03EH,063H,038H.06CH,06CH,036H.OCCH,078H ; o_15

FBIE OD0000007E7E7EOO

5523

DB

OOOH,OOOH.OOOH.OOOH,07EH.07EH,07EH.OOOH J 0_16

FB26 IB3C7E187E3C18FF

5524

DB

016H,03CH,07EH.Ol8H,07EH,03CH,DIBH.OFFH l 0_17

FB2E 183C7El81B181aoo

552:5

DB

018H,03CH.07EH.018H,018H.OIBH,018H.OOOH ; D_16

F836 181818187E3C1800

552:6

DB

018H,OI8H,OIBH.016H,07EH,03CH.OIBH.OOOH J 0_19

FB3E 00160CFEOC160000

5527

DB

000H,018H.OOCH,OFEH,OOCH.018H.000H.OOOH ; 0_lA.

FB46 003060FE60300000

5528

DB

OOOH.030H.06DH.OFEH.06DH.030H,OOOH,OODH ; 0_18

F84E QOOOCOCOCOFEOOOO

5529

DB

OOOH,OOOH,OCOH,OCOH,OCOH.OFEH,OOOH.OOOH J O_IC

F856 002466FF66240000

5530

DB

000H.024H,066H.OFFH.066H,024H.OOOH,000H ; D_ID

Fa5E 00183C7£FFFFOOOO

5531

DB

000H.016H.03CH,07EH,OFFH.OFFH.OOOH,OOOH ; O_IE

FB66 00FFFF7E3CI80DDD

5532

DB

OOOH.OFFH,OFFH.07EH,OJClhOl6H.OOOH.OOOH 10_IF

FB6E OOOOOOOOOOODOOOO

5533

DB

OOOH,OOOH.OOOH.OOOH.OOOH,OOOH.OOOH.OOOH ; SP D30

F876 3078783030003000

5534

DB

030H.078H,076H.030H,030H.OOOH,030H,OOOH ; ! 0_2:1

FB7E 6C6C6COOOOOOOOOO

5535

DB

06CH.06CH,06CH,000H.OOOH,OOOH,OOOH.OOOH

~

.. D_ZZ

F866 6C6CFE6CFE6C6COO

5536

DB

06CH.06CH.OFEH,06CH.OFEH.06CH,06CH.OOOH

j

•

FBBE 307CC0780CF83000

5537

DB

030H.07CH.OCOH.078H.DOCH,OF6H,030H.000H I $ 0_24

FB96 00C6CC183066C600

5538

DB

OOOH.OC6H.OCCH,018H.030H,066H,OC6H,OOOH , PER CENT D_25

o_23

F89E 386C38760CCC7600

5539

DB

Q38H.06CH,038H.076H.ODCH.OCCH.076H,OOOH ; & o_26

FBA6 6060COOOOOOOOOOO

5540

DB

060H.060H.OCOH.000H.000H,OOOH.OOOH.OOOH

FBAE 1830606060301800

5541

DB

016H,030H,060H.060H,060H,030H.018fI.000H ; ( 0_2B

FBB6 6030181B16306000

5542:

DB

060H.030H.OlathOI8H.016H,030H,060H.OOOH

• 0_2:7
) D_2:9

System BIOS

A-77

LOC OBJ

LINE

SOURCE
000H.06bH,03CH.OFFH.Q3CH.066H.00QH,OOOH ;

0_2A

FBBE 00663CFF3C66oaoo

5543

DB

FBC6 003030FC30300000

5544

DB

000H,030H.030H.OFCH.030H,030H.000H.0,Q~H

feCE 0000000000303060

5545

DB

000H.000H.000H,OOOH,OOOH.030H.030H.ObOH I • D_2C

If

I + 0_2B

FBD6 OOOOOOFCOOOOOOOO

5546

DB

OOOH.OOOH.OOOH,OFCH.OOOH.OOOH.OOOH,OOOH I - o_20

FBDE 0000000000303000

5547

DB

000H.000H,000H.000H.000H.030H.030H,000H ;

FBE6 060C183060C08000

5548

DB

006H,OOCH,OI8H.030H,060H,OCOH,080H.000H I I D_2F

FeEE 7CC6CEDEF6E67COO

5549

DB

07CH,OC6H.OCEH.ODEH,OF6H.OE6H,07tH.OOOH I 0 D_30

FBFo 307030303030FCOD

5550

DB

030H.070H.030H.030H.030H.030H.OFCH.000H I 1 0_31

FeFE 78CCOC3860CCFCOO

5551
5552

De
De

078H,OCCH,00CH.038H,060H.OCCH.OFCH.000H ; 2 o_32

FeOb 78CCOC380CCC7800

FeOE lC3C6CCCFEOClEOO

5553

De

01CH,03CH,06CH.OCCH,OFEH,OOCH,OIEH,000H ; 4 o_34

Fel6 FCCOFBOCOCCC7800

5.5.54

DB

OFCH.OCOH.OF8H,OOCH.00CH.OCCH.078I-hOOOH ; 5 o_35

FelE 3860COF8CCCC7600

5555

De

038H,060H,OCOH,OF8H.OCCH,OCCH.078H.000H ; 6 o_36

FeZ6 FCCCOC1830303000

5556

DB

OFCH,OCCH.OoCH.018H.030H,030H,030H,OOOH ; 7 0_37

FC2E 78CCCC78CCCC7aOO

5557

DB

078H.OCCH.OCCH.076H,OCCH,OCCH.076H,OOOH ; 8 o_38

Fe36 76CCCC7COC187000

5558

DB

078H.OCCH.OCCH.07CH.00CH,OI8H.070H.OOOH ; 9 o_39

Fe3E 0030300000303000

5559

DB

000H.030ii,030H,OOOH.000H.030H,030H.OOOH I

: D_3A.

FC46 0030300000303060

5560

DB

000H.030H.030H.000H,OOOH.030H,030H,060H ;

; 0_38

FC4E 183060C060301800

5561

DB

018H,030H,060H.OCOH.060H.030H,OI6H.000H • < D_X

FC56 QOOOFCOQOOFCOOOO

• D_2E

078H.OCCH,OOCH.038H.OOCH.OCCH.078H.000H ; 3 o_33

=

5562

DB

OOOH,OOOH.OFCH,OOOH,OOOH.OFCH.OOOH.OOOH ;

FeSE 6030180C18306000

5563

DB

060H.030H,OI6H,ooCH,OI8H,030H,060H,000H ; > 0_3E

FC6b 78CCOC1630003000

5564

DB

078H.OCCH,OOCH,OI8H.030H,OOOH,030H.000H ; ? 0_3F

FC6E 7CC6DEOEDEC07800

5565

DB

Fe76 307&CCCCFCCCCCOO

5566

DB

030H,078H,OCCH.OCCH,OFCH,OCCH.OCCH.000H ; A D_41

Fe7E Feb66b lC6666FCOO

5567

DB

OFCH,066H.066H,07CH.066H,066H.OFCH.000H I B D_42:

07CH.OC6H,OOEH,OOEH,OOEH,OCOH,078H,OOOH i

~

o_30

o_40

FeS6 3C66COCO(;0663COO

5566

DB

03CH.066H.OCOH.OCOH.OCOH,066H.03CH,000H ; C 0_43-

FeSE F86C6666666CF800

5569

DB

OF8H,06CH,066H.066H.066H,06CH,OF8H,OOOH ; 00_44

FC96 FE62687B6862FEOO

5570

DB

OFEH.062H.068H,078H,068H,062H.OFEH.000H I E D_45

FC9E FE6268786860Fooa

5571

DB

OFEH.06~H.068H.078H.068H.060H,OFOH,OOOH

FCA.6 3C66COCOCE663EOO

5572

DB

03CH,066H,OCOH.OCOH,OCEH,066H,03EH,OOOH ; G 0_47

FCAE eeeeeeFccceceeoo

5573

DB

OCCH.OCCH,OCCH.OFCH,OCCH.OCCH.OCCH,OOOH ; H D_48

DB

078H.030H,030H.030H.030H.030H.078H,OOOH ; 10_49

; F o_46

FeSE> 7830303030307800

5574

FeBe lEococoeeece7800

5575

DB

OlEH.00CH,OOCH,OOCH.OCCH.OCCH.078H,OOOH ; J 0_4A.

Fee6 E6666C786C66E600

5576

DB

OE6H.066H.06eH,078H.06CH,066H,oE6H.000H i K 0_4B

FetE F06060606266FEOO

5577

DB

OFOH.060H.060H.060H,062H,066H,OFEH.000H ; l D_4C

FCD6 C6EEFEFED6C6C600

5576

FceE C6E6F6DECEC6C600

5579

De
De

OC6H,OE6H.OF6H.OOEH.OCEH.OC6H.OC6H,OOOH ; N 0_4E

FCE6 386CC6C6C66C3800

0(6H,OEEH.OFEH.OFEH,006H,OC6H.OC6H,OOOH ; M o_40

5580

DB

038H.06CH,OC6H,OC6H,OC6H,06CH.038H,OOOH ; 0 D_4F

feEE FC66667C6060FOOO

5581

DB

OFCH.066H,066H.07CH,060H,060H.OFOH,OOOH ; PO_50

FCF6 78CCCCCCOC781COO

5582

DB

078H.OCCH,OCCH.OCCH.OOCH.078H.OICH,000H ; Q o_51

FCFE FC66667C6C66E600

5583

DB

OFCH.066H,066H.07CH,06CH.066H.OE6H,OOOH i R o_52

F006 78CCE0701CCC7800

5584

DB

078H,OCCH.OEOH.070H,OlCH,OCCH.078H,OOOH ; 5 0_53

FOOE FCB4303030307800

5585

DB

OFCH,OB4H.030H.030H.030H.030H.078H.OOOH ; TO_54

FOl6 ccCCCCCtCCCCFCOO

5586

DB

OCCH,OCCH,OCCH.oeCH.OCCH.OCCH.OFCH,OOOH I

FOIE cccceCCCCC783000

5587

DB

OCCH.OCCH,OCCH,OCCH,OCCH.078H.030H,OOOH ; V o_56

F026 C6C6C606FEEEC600

u

0_55

5588

DB

OC6H,OC6H.OC6H,006H.OFEH,OEEH,OC6H,OOOH ; W 0_57

F02E C6C66C38386CC600

5589

DB

OC6H,OC6H.06CH.038H.03SH,ObCH,OC6H,OOOH • X o_58

FOlt! CCCCCC7830307800

5590

DB

OCCH.OCCH,OCCH.078H,030H,030H,078H,OOOH • YO_59
OFEH.OC6H,08CH,OlBH,032H,066H,OFEH.000H I Z 0_5A

F03E FEC68Cla3266FEOO

5591

DB

F046 7860606060607800

5592

DB

078H,060H.060H,060H.060H,060H.078H.OOOH J [ o_58

F04E C060301aOC060200

5593

DB

OCOH,060H,030H.OI8H.a.oCH,006H,002H.000H I BACKSLASH D_5C

DB

078H,Ol8H.018H.OIBH,018H,OIBH.078H.000H J I 0_50

F056 7818181818187800

5594

F05E 10386CC600000000

5595

DB

010H.038H,06CH.OC6H,OOOH.000H.000H,OOOH I CIRCUHFLEX 0_5E

F066 OOOOOOOQOOOOOOFF

5596

DB

OOOH.OOOH,OOOH,OOOH,OOOH.OOOH,OOOH.OFFH I _ 0_5F

F06E 3030180000000000

5597

DB

F076 0000780C7(CC7600

5598

DB

000H,000H.078H,OOCH.07CH,OCCH.076H,OOOH ; LOWER CASE A 0_61

F07E £060607C66660COO

5599

DB

OEOH,060H,060H.07CH.066H.066H.00CH,OOOH ; L.C. B 0_62

F086 000078CCCOCC7800

5600

DB

OOOH.OOOH,078H.OCCH.OCOH.OCCH,078H,OOOH I L.C. C o_63

FoaE lCOCOC7CCCCC7600

5601

DB

01CH,00CH,OOCH,07CH.OCCH,OCCH.076H.OOOH J loC. 0 0_64

F096 00007BCCFCC07800

5602

DB

000H.OOOH,078H.OCCH.OFCH,OCOH.078H,OOOH ; loC. E 0_65

F09E 386C60F06060FOOO

5603

DB

038H.06CH,060H,OFOH.060H,060H,OFOH.000H ; L.C. F 0_66

030H. 030H ,018H. OOOH, OOOH, OOOH. OOOH, OOOH ;

• o_60

FDA6 000076CCCC7COCF8

5604

DB

OOOH,OOOH.076H.oeCH,OCCH,07CH,00CH.OF8H ; loC. G 0_67

FOAE E0606C766666E600

5605

DB

OEOH,060H.06CH.076H,066H,066H.OE6H.000H I L.C. H 0_68

FOB6 3000703030307800

5606

DB

030H,OOOH.070H.030H.010H.030H,078H,OOOH ; L.C. I 0_69

FOBE OCOOOCOCOCCCCC78

5607

DB

OOCH.000H.00CH.OOCH,00CH.OCCH,OCCH,078H ; L.C. J 0_6A.

FOC6 E060666(786CE600

5608

DB

OEOH.060H,066H.06CH.078H,06CH.OE6H,OOOH ; L.C. K 0_66

FOCE 7030301030307800

5609

DB

070H.030H.030H.030H.030H,030H.078H,000H ; loC. L 0_6e

FOD6 OOOOCeFEFE06C600

5610

DO

OOOH.OOOH.OCCH.OFEH,OFEH.006H,OC6H.OOOH i loC. H o_60

faDE OOOOF8CCCCCCCCOO

5611

DB

OOOH.OOOH,OF8H.OCCH.OCCH.OCCH,OCCH,OOOH ; L.C. N 0_6E

FOE6 000078CCCCCC7600

5612

DB

000H,OOOH,078H,OCCH.OCCH.OCCH.078H,OOOH I L.C. OO_6F

FDEE 00000C66667C60FO

5613

DB

000H,OOOH.ODCH.066H,066H.07CH.060H.OFOH

FDF6 000076CCCC7COCIE

5614

DB

OOOH,OOOH.076H.OCCH,OCCH.07CH,OOCH,01EH I L.C. Q 0_71

FOFE OOOOOC766660FOOO

5615

DB

OOOH,OOOH,ODCH.076H,066H,060H.OFOH,OOOH I L.C. iii o_72

FE06 00007CC0780CF800

5616

DB

000H,OOOH.07CH,OCOH,078H.00CH.OF6H.OOOH I L.C. S D_73

HOE 10307C3030341800

5617

DB

010lt,030H.07CH.030H.030H,034H,018H,OOOH

FE16 0000CCCCCCCC7600

5618

DB

OOOH.000H.OCCH,OCCH.OCCH,OCCH,076H.000H I L.e. U o_75

FEIE 0000CCCCCC783000

5619

DB

OOOH,OOOH.OCCH,OCCH,OCCH.078H.010H,OOOH I L.e. Y o_76

A-78

System BIOS

L.C. P o_70

L.C. T o_74

lOC OBJ

LINE

SOURCE

F£26 DOODC6D6FEFE6CQO

5620

08

FE2:E 0000C66C386CC600

5621
5622

08

OOOH,OOOH.OC6H,06CH,038H.06CH.OC6H.OOOH ; L.C. X D_78

08

OOOH.OODH.DCCH,DCCH.OCCH,07CH,DOCH,DFaH I L.C. Y D_79

08

ODOH.OaOH,OFCH,D96H,030H.064H.OFCH.OOOH I L.c. Z D_7A

DB
DB
DB
DB
DB

DICH.030H.030H.OEDH.030H.030H,01CH,OOOH I ( 0_78
01athOlaH,0l8ti,OOOH,OI8H,018H.0l8lI,OOOH I I D_7C
OfOH.030H.030H,OltH.030H.030H.OEOH,OOOH I ) D_7D

FEl6 OOOOCCCCCC7COCf&
FElf 0000FC'983064FCOO

FE46 lC3030£030301COO

5623
5624

FE4E 1818180018181800

5625

FE56 E030301C3030£000

.. 2.

FESE 760COOOOOOOOOOOO

. . 27

fE66 DO l0386CC6C6FEOO

..2.

DDDH,OOOH.DC6H.OD6H.OFEH,OFEH,06CH,DQOH I l.C ... D_77

076H.ODCH.OOOH.OOOH.OOOH.OODH.OOOH,OOOH I TILDE 0_7E
OOOH,OlOH,038H,06CH,DC6H,OC6H.OFEH.OOOH I DELTA D_7F

562.
5630
5631

5--- INT 1. ---~---------------------~--------~-~-------; TIME.OF_DAY

5632

5

5633

I

5634

; INPUT

5635

THIS ROUTINE ALLOWS THE CLOCK TO 8E SET /READ

(AH)

=0

READ THE CURRENT CLOCK SETTING

5637

RETURNS CX
DX

5638

AL

5636

5639

=HIGH PORTION OF COUNT
= LOW PORTION Of COUNT
= 0 IF TIHER HAS NOT PASSED

24 HOURS SINCE lAST READ

5640

<>0 IF ON ANOTHER DAY

5641

(A") = 1

5642

CX

5643
5644

OX

= HIGH PORTION OF COUNT
= LOW PORTION OF COlIfT

; NOTE: COUNTS OCCUR AT TH£ RATE OF

5645

1193180/65536 COUNTS/sEC

5646
5647
5648

SET THE CURRENT CLOCK

(OR ABO\JT 18.2 PER SECOND -- SEE EQU;'TES BELOW)

5- -- -.- -- -------------------------- -------- - -- -------- --ASSlR'IE CS:CODE.DS:DATA

FE6£

5649

00.

FE6£

5650

TIME_OF _DAY

FE6E F8

5651

STI

FE6F IE

5652

PUSH

OS

FE70 E8E6F8

5653

CALL

DDS

FE73 OAE4

5654

OR

AH,AH

OFE6EH
PRDC

FAR
; INTERRUPTS BACK ON
j

SAVE SEGHENT

; AH=O

5655

JZ

TZ

j

FE77 FEte

5656

DEC

AH

; AH=1

FE79 7416

5657

JZ

T'

; SET.TIME

FE1B

5658

FE1B F8

5659

FE7C IF

5660

STI
pop

DS

FE7S 7407

FE7D CF

5661

FE7f

5662

FE7E F;'

5663

FE7F ;'07000

5664

FE82 C606700000

5665

TI:

RE;'D_TIHE

J TOD_RETURN

I INTERRUPTS BACK ON
j

IRET

RECOVER SEGHENT

1 RElUlN TO CALLER

T2:

; READ.TIHE

ell
I1D'I
ItDV

I NO TIHER INTERRUPTS IoItILE READING
Al,TIMER_OFL
TIHER_OFL.O

FE87 880E6EOO

5666

MOV

ex. TIMER_HIGH

fE8B 88166COO

5667

ItDV

FE8F EBEA

5668

JHP

OX, TIMER. LOW
TI

FE91
FE91 FA

5669
5670

T3:

I GET OVERFLOW. At«) RESET TlIE FlAS

; TDD_RETLJiN
J SET_TIME

eLI

5 NO INTERRUPTS MULE WRITING

FE92 89166COO

5671

HOY

TIMER_LOW.DX

FE96 890£6EOO

5672

HOY

TIMER_HIGH

FE9;' C6067000DO

5673

HOY

TIMER_OFL.O

I SET THE TIHE
I RESET OVERFLOW

FE9F EBDA

56 74

JHP

TI

I TOD_RETURN

5675
5676

TIME_OF_DAY

5677
5678

; ----- - ----- ---- --- ------------------------ -------------I THIS ROUTINE HAt-I)LES THE TIMER INTERRUPT FROI1

5679

ENJP

CHANNEL 0 OF THE 8253 TIMER. INPUT FREQUENCY

IS 1.19318 MHZ AND THE DIVISOR IS 65536, RESULTING

5680
5681

I

5682

I

5683

; THE INTERRUPT

IN APPROX. 18.2 INTERRUPTS EVERY SECOND.
H~LER

HAINTAINS A COUNT OF INTERRUPTS :

5684

J

SINCE POWER ON TIME. NiICH HAY 8E USED TO ESTABLISH

5685

1

TIHE OF DAY.

5686

; THE INTERRUPT HANDLER ALSO DECREMENTS THE HDTOR

5687

;

5688

I

WIll TURN OFF THE DISKETTE HOTOR, AN) RESET THE

5689

;

HOTOR RUNNING FLAGS.

CONTROL CCUIT OF TItE DISKETTE, AND WHEN IT EXPIRES,

5690

; THE INTERRUPT HANDLER WILL ALSO INVOKE A USER ROUTINE:

5691

I

THROUGH INTERRUPT 1CH AT EVERY TIME TICK.

5692

J

tlJST CODE A ROUTINE ;.tII PLACE THE CORRECT ADDRESS IN :

I

THE VECTOR TABLE.

5693
5694

FE"
FE. .

.ex

THE USER

:

1--------------------------------------------------------

5695

OFEASH

5696

PRDC

FAA

System BIOS A-79

LINE

LOC OBJ

SOURCE

FEAS FB

5697

STI

FEA& IE

5698

PUSH

FEA7 50

5699

PUSH

I INTERRUPTS BACK ON
OS

AX

FEA6 52.

5700

PUSH

OX

I SAVE MACHINE STATE

FEA9 EBAOFB

5701
5702
5703

CALL

DDS
TIMER_LOW

JNZ

T4

5704

INC

TIMER_HIGH

, INCREMENT TIME
,

CMP

TIMER_HIGH. DI8H

FEAt FF066COO

FEBO 7504
FEBl FF066EOD
FEB6

FEBb 833E6EOO18

FEBS 7515

FEBD 813E6C008000
FEe3 7500

5705
5706

INC

J TEST_DAY

INCREMENT HIGH WORD OF TIME

,

14:

JNZ

T5

5707
5708

CMP

TIMER_LOW.OaOH

5709

JNZ

T5

TEST_DAY

) TEST FOR COUNT EQUALING !4 HOURS
i

DISKETTE_CTL

I

DISKETTE_eTl

5710

5711
5712

; ------ TItiER HAS GONE 24 HOURS

FECS 2.BCO

5713

SUB

FEt7 A36EOO

5114
5715

MDV

AX ,AX
TIMER_HIGH. AX

FEe;. ,6.36COO

fECD C606700001

5716

"OV
MOV

TIHER_OFL,I

TIMER_LOIol,AX

5717
5718

i ------ TEST FOR DISKETTE TIME OUT

5719

FEDl

5720

FEDZ FEOE4000

5121

I DISKETTE_eTL

T5:
DEC

JNZ

HOTOR_COUNT

T.

I RETURN IF COUNT HOT OUT

5723

AND

MOTOR_STATUS.OFOH

1 TURN OFF HOTOR RUNNING SITS

FEDD BoDe

5724

AL.OtH

FEDF BAF203

5725

"OV
HOV

DX.03F2H

,

OUT

OX.Al

1 TURN OFF THE HOTOR

5722

FE06 750B
FEOS

S02~3FOOFO

FEE2 EE

572~

FEE3

5727

16:

FDC eTl PORT

1 TIMER_RET:

FEE3 CDIC

572S

INT

5729

HOV

'tH
Al,EOI

TRANSFER CONTROL TO A USER ROUTINE

FEES BOZO
FEE7 E620

5730

OUT

020H.AL

END OF INTERRUPT TO 8259

FEE9 SA

5731

POP

OX

FEEA 58

5732

POP

AX

FEEB IF

5733

POP

OS

FEEC CF

5734
5735

j

RESET MACHINE STUE

; RETURN FROH INTERRUPT

IRET
TIMER_lIoIT

ENDP

5736
5737
5738

1------- -- --------------- -----------------------; THESE ARE THE VECTORS WHICH ARE MOVED INTO

5739

I THE 8086 INTERRUPT AREA. DURING POWER ON.

5740

i ONLY THE OFFSETS ARE DISPLAYED HERE. CODE

5741

; SEGMENT WILL BE ADDED FOR ALL OF THEM. EXCEPT:

5742

; WHERE NOTED.

5743

1------------------------ ------ ------------------

5744

ASSUME

CS:CODE

ORG

OfEF3H

FEF3

5745

FEF3

5746

FEF3 ASFE

5747

OW

OFFSET TIHER_INT

FEF5 87E9

5748

OW

OFFSET

KB_INT

FEF7 23FF

5749

OW

OFFSET

FEF9 23FF

011
011
011
011

VECTOR_TAB LE

LABEL

WORD

5750

OW

OFFSET

FEFB 23FF

5751
5752

FEFF 57EF

5753

F,FOI 23FF

5754

FF03 65FO

5755

FFOS 40F8

5756

ow
ow
ow
ow
ow
ow

OFFSET

FEFO 23FF

FF07 4IF8

5757

OW

OFFSET HEHDRY_SIZE_OET

FFO~

59EC

5758

OffSET DISKETTE_IO

FFOB 39E7

5759

OFFSET

I VECTOR T.6.BLE FOR HOVE TO INTERRUPTS

,

1 INTERRUPT B
INTERRUPT C
INTERRUPT 0

OFFSET DISK_INT
OFFSET

011

INTERRUPT &
INTERRUPT 9

I INTERRUPT A

INTERRUPT E
I INTERRUPT F

OFFSET VIDEO_IO

INTERRUPT 10H

OFFSET EQUIPMENT

INTERRUPT 11H
• INTER!;!UPT 12H

5760

ow
ow
ow

CASSETTE_IO

; INTERRUPT 15H( FORMER CASSETTE 10 I

FFOF !!EE6

5761

OW

OffSET KEYBOARD_IO

• INTERRUPT 16H

FFll 02EF

5762

ow

OFFSET PRINTER_IO

ow
ow

OOOOOH

FFOO 59F8

INTERRUPT 13H

OFFSET RS232_ID

1 INTERRUPT 14H

INTERRUPT 17H

5763
Ff13 0000

5764
5765

OF600H

; INTERRUPT 18H

,

MUST BE INSERTED INTO TABLE LATER

5766
Ff15 F2E6

5767

FFI7 6EFE

5766

ow
ow

OFFSET BOOT_STRAP

INTERRUPT 19H

TIHE_OF _DAY

I INTERRUPT lAH -- TINE OF 0Al'

FF19 4BFF

57~9

OW

DUMMY_RETURN

FFIB 4BFF

5770

0"

DUMMY_RETURN

INTERRUPT IBH -- KEYBO.6.RD BREAK ADDR

rFlD A4FO

5771

ow

VIDEO_PARHS

FFIF C7Ef

5772:

OW

OFFSET DISK_BASE

,
,

FF21 0000

5773

OW

0

I INTERRUPT IF -- POINTER TO VIDEO EXT

A-SO

System BIOS

INTERRUPT IC -- TIHER BREAK ADDR

I INTERRUPT 10 -- VIDEO PARAMETERS
INTERRUPT IE -- DISK PARHS

LOC OBJ

LINE

SOURCE

5774
5775
5776
5777

FF23
FFZ3 IE
FF24 52

; ~ -- -- - -- --- ---- -- -- --- - - -- -- ------- ------- --- - - -- ------; TEMPORARY INTERRUPT SERVICE ROUTINE
1. nus ROUTINE IS AlSO LEFT IN PLACE AFTER THE :

5778

POWER ON DIAGNOSTICS TO SERVICE UNUSED

5779
5760

INTERRUPT VECTORS. LOCATION 'INTRJLAG' WILL
CONTAIN EITHER: 1. LEVEL Of HARDWARE INT. THAT

5761

CAUSED CODE TO BE EXEC.

5782

2. 'FF' FOR NOH-HARDWARE INTERUPTS THAT WAS

5783
5764
5785
5786
5787
5768
5789

EXECUTED ACCIDENTLY.
011

ASS\J'1E

NEAR
DS:DATA

PUSH

OS

PROC

PUSH

OX

; SAVE REG AX CONTENTS

PUSH

AX

CALL

DDS

MDV

FF2B E620

5790
5791
5792

Al.OBH
INTAOO,Al

FF2D 90

5793

NOP

FF2E £420

5794
5795
5796

MOV

ff25 50
FF26 EB30FB
FF2.9 BOOB

fF30 BAED
FF32 OAe4
FF34 7504

FF36 64FF
FF38 EBOA

FF3A

FFlA f421

FFX OAC4
FF3E f621
FF40 80020
FF42 E620

FF44

5799
5600
5801
5802
5803
5804
5805
5806

FF49 SA

FF4A IF

5810

FF4S

5811
5812
5813

FF48 58

FF4S CF

IN
DR

5797
5798

5607
5808
5809

FF44 88266800

OUT

JNZ
MDV
JMP

I READ IH-SERVICE REG
(FIND OUT WHAT LEVEL BEING

;

I SERVICED)

AL.INTAOO
AH.Al
AL.AH
HW_INT
AH,OFFH
SHORT SET_INTR_FlJ.G

i GET LEVEL
; SAVE IT
; DO? (NO HARDWARE ISR ACTIVE)

I SET fLAG TO ff IF NON-HOWARE

HW_INT:
IN

OR
OUT
MOV

OUT

Al,INTAOl
Al.AH
INTAOl.,u
Al,Eor
INTAOQ,Al

I GET MASK VALUE
; HASK OFF lVl BEING SERVICED

SET_INTRJlAG:
MOV

INTR_FLAG.AH

pop

AX

POP

OX

POP

OS

DUI1t1Y_RETURN:
IRET
ENDP
011

• SET FLAG
; RESTORE REG AX CONTENTS

; HEED IRET FOR VECTOR TABLE

5814

FFS3
FFS3 Cf

5815
5816

; -----------------------------------------------; DUHMY RETURN FOR ADDRESS COt1PATlBILITY

5817
5818
5819

i -----------------------------------------------O'G

OFFS3H

IRET

5820
5821
5822:

;-- IHT 5 --------------------------------------------------------------THIS LOGIC WIll BE INVOKED BY INTERRUPT OSH TO PRINT THE

5823
5824

S8ze

SCREEN. THE CURSOR POSITION AT THE TIME THIS ROUTINE IS INVOKED:
WILL BE SAVED AND RESTORED UPON COMPLETION. ntE ROUTINE IS
INTENDED TO RUN WITH INTERRUPTS ENABLED. IF A SUBSEQUENT
• PRINT SCREEN' KEY IS DEPRESSED DURING THE TIME THIS ROUTINE
IS PRINTING IT WILL BE IGNORED.
ADDRESS 50:0 CONTAINS ntE STAnIS OF THE PRINT SCREEN:

5829
5830

50:0

5825
5826
582:7

=0

5831
5832
5633

=1

5834

=255

EITHER PRINT SCREEN HAS HOT BEEN CALLED
OR UPON RETURN FROM A CALL THIS INDICATES
A SUCCESSFUL OPERATION.
PRINT SCREEN IS IN PROGRESS
ERROR ENCOUNTERED DtRING PRINTING

5835
5836
5837

1---- --- - - - -- - --- -- -- - - - - - --- - -- - ------ ------------------- -- ____ --_ - ____ _

PRINT_SCREEN

FF54 FB

5838
5839

FF550 IE

5840

PUSH

OS

FF56 50

5841

PUSH

AX

FF54

FF54

ASSUME
ORG

CS:CODE.DS:XXDATA
OFF54H

PROC

FAR

ST!

I I1UST Rlki WITH INTERRUPTS ENABLED

FFS7 53

5842

PUSH

OX

FF58 51

5843
5844

PUSH

ex

FF59 52

PUSH

OX

FF5A 885000

5845

HOV

AX,XXDATA.

FF5D 8ED8

sa46

MOV

OS,AX

FF5F 803EOOOOOI

5647

CMP

FF64 745F

5848

JZ

FF66 C606000001

5849

MOV

STATUS_BYTE,l
EXIT
STATUS_BYTE,l

FF68 B40F

5850

HOV

AH.15

I t1lJST USE 50: 0 FOR DATIl. AREA. STORAGE

I WIll USE THIS LATER FOR CUlSOR UtlITS
; WI Ll HOLD CUi!RENT Ct.RSOR POSITION
• HEX 50
I SEE If PRINT ALREADY IN PROGRESS
I JUl'1P IF PRINT ALREADY IN PROGRESS
I It.oICATE PRINT NOW IN PROGRESS
; WILL REQUEST THE CURRENT SCREEN HOOE

System BIOS

A-Sl

LINE

LOC OSJ

SOURCE
INT

5651
5852

fFt.O COlO

lAll::HODE

10H

[AH ):::NUt1BER COLUMNS/LINE

5853
5854

[BH J=VISUAl PAGE
j ----------------------------------------------------------------

585S

AT THIS POINT WE KNOW THE COllJl1HS/lINE ARE IN

5656
5857

(Axl AND THE PAGE IF APPLICABLE IS IN ISH). THE STACK
HAS OS,A)(,BX,CX,DX PUSHED. (AJ HAS VIDEO HOOE

1----------------------------------------------------------------

FF6F 8Ace

5858
5859

FF71 8519

5860

HOV
MOV

CH,25

FF73 E85500

5861

CALL

CRLF

i CARRIAGE RETURN LINE FEED ROUTINE

FF76 51

5862
5863

CX
AH,3

I SAVE SCREEN BOUNDS

fF77 6403
FF79 COlO

PUSH
MOV

I WI\L NOW READ THE CURSOR.

CL,AH

I WILL MAKE USE OF I CX) REGISTER TO

; CONTROL ROW & COLUNNS

5864

INT

10H

I AND PRESERVE ntE POSITION

FF75 59

5865

FF7C 52

5866

POP
PUSH

CX
OX

I RECALL [BH );;VISUAL PAGE

XOR

OX.OX

; WILL SET CURSOR POSITION TO [0.01

FF7D 3302

5867
5868

; RECALL SCREEN BOUNDS

; ------- --------------------- ----------------------------- -------

5869
5670

THE LOOP FROM PRllO TO THE INSTRUCTION PRIOR TO PRI20
IS THE LOOP TO READ EACH CURSOR POSITION FROM THE

5871

SCREEN AND PRINT.

FF7F

5872
5873

,---------------------------------------------------------------PRllO:

fF7F 8402

5874

AH.2:

, TO INDICATE CURSOR SET REQUEST

fF81 COlO

5875

INT

IOH

1

H83 6408

5876

MOV

AH,8

I

FFBS COlO

5877

INT

10H

I CHARACTER NOW IN [AL)

FF87 OACO

5878

OR

FF89 7502.

san

JHZ

AL.AL
PRIlS

I JUMP IF VALID CHAR

fFBB B020

seeo

MOV

Al. '

; MAKE A BLANK

FFeD

5881

FfeD 52

5882

freE 3302
Ff90 32E4
FFn COll

5883
5884

PUSH
XOR

OX
DX,DX

MOV

NEW CURSOR POSITION ESTABLISHED
TO INDICATE READ CHARACTER

; SEE If VALID CHAR

PRIlS:

AH.AH

ff94 5A

5....

XOR
INT
pop

; SAVE CURSOR POSITIOH
; INDICATE PRINTER 1
; TO INDICATE PRINT CHAR IN [AU

17H
DX

; PRINT THE CHARACTER
; RECALL CURSOR POSITION

FF95 F6C425

5887

TEST

AH. 25H

; TEST fOR PRINTER ERROR

FF98 7521

5886

JNZ

ERRlO

JUMP IF ERROR DETECTED

FF9A FEel

5889

DL
n.OL
PRIlO
OL.DL
AH,DL

; ADVANCE TO NEXT COLlJt1N
I SEE IF AT ENO OF LINE
; IF NOT PROCEED

.....

FF9C 3ACA

5890

FF9E 75DF

5891

HAD 3202

5892

FFA2 8AE2:

5893

INC
CNP
JNZ
XOR
MOV

FFA4 52

5894

PUSH

ox

i

FFAS E8noo

5895

FFAS 5A

CA.LL
POP

CRLF

5896

OX

; LINE FEED CARRIAGE RETURN
; RECALL CURSOR POSITION

; BACK TO COLUMN 0
{AH1;;0
SAVE NEW CooSOR POSITION

51398

INC
CHP

DH
CH,OH

; ADVANCE TO NEXT LINE

fFAB 3AEE
FFAO 7500

5899

JNZ

PIUlO

; IF NOT CONTINUE

FFAF

5900

FFAF SA

5901

POP

FFBD 6402

5902
5903
5904

MOV

DX
AH,2

; RECALL CURSOR POSITION
; TO INDICATE CURSOR SET REQUEST

IDH
STATUS_SHE.D
SHORT EXIT

; CURSOR POSITION RESTORED
; INDICATE FINISHED

OX

I

51397

FF"9 FEe6

FFB2 COlO
FFB4 C606000000

5905
5906

FFB9 EBOA
FFBB

FINISHED'?

PRI2.0:

INT
MOV

JMP

; EXIT THE ROUTINE

ERRlO:

FFBB 5A

5907

pop

FFBC B402.

5908

MOV

AH,2

GET CURSOR POSITION
; TO REQUEST CURSOR SET

INT

IDH

; CooSOR POSITION RESTORED

FFBE COlO

5909

FFCO

5910

FFeD C6060000FF

5911

FFCS

5912

ERR20 :
; INDICATE ERROR

HOV
EXIT:

FfCS 5A

5913

pop

fFCb S9

59Ft

POP

FFC7 56

5915

FFee 58

5916

POP
POP

FFC9 IF

5917

POP

FFCA CF

5918
5919

IRET
PRINT_SCREEN

ox
ex
ox

; RESTORE ALL THE REGISTERS USED

AX
OS

ENDP

592.0

592.1

;------ CARRIAGE RET1JRN. LINE FEED SUBROUTINE

592.2
CR LF

PROC

fFce

5923

FFee 3302

5924

xaR

FfeD 32E4

5925

XOR

NEAR
i PRINTER 0
; WILL NOW SEND INITIAl IF ,CR

TO PRINTER

592:6

FFCF BOOA

A-82

5927

System BIOS

Mav

AL.12Q

,LF

LOC OBJ

LINE

SOURCE
1NT

FFD3 32:E4

5929

XOR

1'"
AH,AH

FFDS BOOD

5930

MOV

AL,15Q

; SEND THE LINE FEED
; NOW FOR THE CR
; CR

FFD7 COIl

5931

1NT

17"

; SEND THE CARRIAGE RETURN

FFOI COil

FF09 t3

5926

RET

5932

5933

CRLF

ENDP

5934

5935

1---------------------------------------------------------------

5936

PRINT A SEGMENT VALUE TO LOOK LIKE" 20 BIT ADDRESS

5937

OX truST CONTAIN SEGMENT VALUE TO BE PRINTED

5938

; - - - -- - --- - - - -- -- -- -- -------- - --- - - -- - - --- -- --- ----- - - - ---.-----

PRT_SfG PROC

FFOA

5939

FfOA 6,6,C6

5940

ItOV

Al,DH

FFoe E8ACF9

5941

CALL

XPC_BYTE

FFDF 8AC2

5942

HOV

Al,OL

FFEl E8A7F9

CALL

XPC_BYTE

HOV

AL.· O'

FFE9 B020

5943
594.
5945
5946

MOV

Al, '

FFEB E8AEF9

5947

CALL

PRT_HEX

FFEE C3

5948

RET

FFE4 B030
FFE6 E883F9

5949

CAll

NE....
;GET HSB
jLSB
I PRINT A. '0

PRT_HEX

;SPACE

PRT_SEG ENOP

5950
5951

COOE

ENIlS

5952
5953

; --------------------------------

5954

5955
5956

POWER ON RESET VECTOR

; ------------------ - ------------VECTOR

SEGMENT AT OFFFFH

5957
5958

0000 EASBEOOOFO

5959
5960

0005 31312:F30382F38

5962

j----- POWER ON RESET
JHp

RESET

DB

'11106/82'

5961

"

5963

5964

VECTOR

; RELEASE MARKER

ENDS
END

System BIOS A-83

LOC OBJ

LINE

SOURCE
$TITlE( FIXED DISK I3JOS FOR IBM DISK CONTROLLER)
i-- INT 13 ------------------------------------------------------

FIXED DISK I/O INTERfACE

nus INTERFACE PROVIDES ACCESS TO 5 1/4" FIXED DISKS
THROUGH THE IBM FIXED DISK CONTROLLER.
9

10
11

;----------------------------------------------------------------

12
13

1--------- ------------------------------------------------------THE BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH

14

SOfTWARE INTERRUPTS ONt Y.

15

THE LISTINGS

16

NOT FOR

17

ABSOLUTE

18

VIOLATE THE STRUCTURE AND DESIGN OF BIOS.

19
2.
21

ANY ADDRESSES PRESENT IN

ARE INCLUDED

REFERENCE.

ONLY FOR

COMPLETENESS.

APPLICATIONS WHICH

ADDRESSES

WITHIN

THE

REFERENCE

CODE

SEGMENT

; ---------------------------------------------------------------INPUT

I AH = HEX VALUE 1

22

23
24

,.
25

27

26
29
3.
31
32

n

UJO=OO RESET DISK (DL = 80H.81HI /DISKETIE
(AH)=ol READ THE STATUS OF THE LAST DISK OPERATION INTO (ALI
HOTE: DL < 80H - DISKETIe
DL ;. 80H - DISK
(AHI=02 READ THE DESIRED SECTORS INTO MEMORY
(AHI=03 WRITE THE DESIRED SECTORS FROM MEMORY
IIlHJ=04 VERIFY THE DESIRED SECTORS
tA.HJ=DS
(.6.HI=06
(AHI=07
(AHI=08

FORMAT
FORMAT
FORMAT
RETURN

THE
lliE
THE
THE

DESIRED TRACK
DESIRED TRACK AND SET BAD SECTOR FLAGS
DRIVE STARTING AT THE DESIRED TRACK
CURRENT DRIVE PARAMETERS

34
35

3.

(A.HI=09 INITIALIZE DRIVE PAIR CHARACTERISTICS

3.

INHRRUPT 41 POINTS TO DATA BLOCK
(.6.H)=OA READ LONG
(AHI=OB WRITE LONG

39
4.

NOTE: READ AND WRITE LONG ENCOMPASS 512 + 4 BYTES ECC
(AHI=OC SEEK

41

44

IAH)=OD ALTERNATE DISK RESET (SEE DU
(AHI=OE READ SECTOR BUFFER
(AH)=OF WRITE SECTOR BUFFER.
(RECOMMENDED PRACTICE BEFORE FQRMATIINGI

45

(AHI=10 TEST DRIVE READY

46

IAHI=l1 RECAllBRATE
(AH)=12 CONTROLLER RAM DIAGNOSTIC
IAH)=n DRIVE DIAGNOSTIC

37

42
43

47

4.
49
5.
51

(AH 1=14 CONTROLLER INTERNAL DIAGNOSTIC
REGISTERS USED FOR FIXED DISK OPERATIONS

52
(OU
(oH)
{CHI
ICLI

.,.

53

55

5.

-

DRIVE NUt1BER
HEAD HUMBER
CYlINDER NUt1BER
SECTOR NUI1BER

160H-87H FOR DISK. VALUE CHECKED)
(0-7 ALLOWED, NOT VALUE CHECKED)
(0-1023. NOT VALUE CHECKED)(SEE CLI
tl-17. HOT VALUE CHECKED)

57

NOTE: HIGH 2 BITS OF CYLINDER NUMBER ARE PLACED

58

IN THE HIGH 2 BITS OF THE CL REGISTER

59

••.,

(ALI

.3

6Z

(INTERLEAVE VA.LUE FOR FORMAT 1-160)
(ES:BXI -

•4

65

••

67
66
69
70
71

(10 BITS TOTAU
NUMBER OF SECTORS (MAXIMUM POSSIBLE RANGE 1-80H.
FOR READ/WRITE LONG 1-79HI

ADDRESS OF BUFFER FOR READS ANO WRITES •
(NOT REQUIRED FOR VERIfY 1

; OUTPI.1T
AH = STATUS Of CURRENT OPERATION
STATUS BITS ARE DEFINED IN THE EQUATES BELOW
CY = 0 SUCCESSFUL OPERATION (AH=O ON RETURN)
CY

=

1

FAILED OPERATION (AH HAS ERROR REASON)

72

n

NOTE:

74
75

7.
77

A-84

Fixed Disk BIOS

ERROR llH INDICATES THAT THE DATA READ HAD A RECOVERABLE
ERROR WHICH ..,A5 CORRECTED BY THE ECC ALGORITHM. THE DATA
IS PROBABLY GOOD.
HOWEVER THE BIOS ROUTINE INDICATES AN
ERROR TO ALLOW THE CONTROLLING PROGRAM A CHANCE TO DECIDE
FOR ITSELF. THE ERROR HAY NOT RECUR IF THE OATA IS

LOC OBJ

LINE

SOURCE
REWRITTEN. (Al) CONTAINS TliE BURST LENGTH.

78

7'

80

IF DRIVE PARAMETERS WERE REQUESTED,

81

OL

82

= I«Jt1BER

83

OF CONSECUTIVE ACKNOWLEDGING DRIYES ATTACHED (0-2)
(CONTROLLER CARD ZERO TALLY ONLY)

84

DH :: tu.XlttJt1 USEABLE VALUE FOR HEAD NUMBER

85

eH :: MAXltn.n1 USEABLE VALUE FOR CYlINDER NlR1BER
Cl :: HAXII'1\JN USEABLE VALUE FOR SECTOR NllI1BER
ANO CYLINDER t-M'IBER HIGH BITS

8.
87

eea_
_0

REGISTERS WILL BE PRESERVED EXCEPT IoIiEN THEY ARE USED TO RETURN

91
92

NOTE; IF AN

INFORMATION.

93

E!;!~OR

IS REPORTED BY THe DISK CODE. THE APPROPRIATE

ACTION IS TO RESET niE DISK. THEN RETRY TliE OPERATION.

94

95

;------------------------------------------------------------------------

-.9'

UNOEF _ERR

9.
OOFF
OOBS

0060

97

SENSEJAIL
TIME_OUT

0040

100

0020

oooe

101
102
103
104

0009

105

DMA_BOUNDARY

0007

10.

INITJAIl

0005

107

BAD_RESET

0004

108

RECORD_NOTJHD

0002

109

BAD_ADDR_MARK

0001

110

BAD_CMO

0011

0010

BAD_SEEK
BAD_CNTLR
DATA_CORRECTED
BAD_ECC
BAD_TRACK

EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU

OFFH

I SENSE OPERATION FAILED

OBBH

I UNDEFINED ERROR OCCURRED

80H

; ATTACHMENT FAILED TO RESPOND

40H

; SEEK OPERATION FAILED

20H

I CONTROLLER HAS FAILED

11H

I ECC CORRECTED DATA ERROR

lOH

I BAD ECC ON DISK REAO

08H

J BAD TRACK FLAG DETECTED

09H

; ATTEMPT TO DHA ACROSS 64K BOUNDARY

07H

; DRIVE PARAMETER ACTIVITY FAILED

05H

I RESET FAILED

04H
02H

; REQUESTED SECTOR NOT FOUND
I ADDRESS HARK NOT FOUND

OlH

I BAD COt1tlAND PASSED TO DIS!( I/O

111

112

; ----------------------------------------

113

INTERRUPT AND STATUS AREAS

114

; ----------------------------------------

115
11.

0034

117

0034

118

D04C

11_

004C
0064
0064

121

120

DUI'nY

SEGMENT AT 0

DR.
HDISK_INT

DR.
ORG_VECTOR

OR.

122
123

BOOT_VEe

0078
0078

124

DISKETTE_PARH

0100

125

OR.

0100
0104
0104

12.

DISK_VECTOR

127
128
12_

DR.

7C00
7COO

130
131

LABEL

HF _TBl_VEt

OR.
BOOT_LOCN

DWORD
I DISK INTERRUPT VECTOR

13H*4
LABEL

DWORD
I BOOTSTRAP INTERRUPT VECTOR

19H*4
LABEL

DR.

; FIXED DISK IHTERRUPT VECTOR

00H*4

DWORD
I DISKETTE PARAMETERS

I£H*4
LABEL

DWORD
; HEW DISKETIE INTERRUPT VECTOR

040H*4
LABel

DWORD
; FIXED DISK PARAMETER VECTOR

041H*4
LABEl

DWORD
; BOOTSTRAP LOADER VECTOR

7COOH

LABEl

FAR

0 ....'

ENOS

DATA

SEGMENT AT 40H

0042
0042 (7 ??)

133
134
135

CHO_BLOCK

LABEl

BYTE

13.

HD_ERROR

DB

7 DUPI?)

006C

137

006C 1111

138

TIMER_LOW

0072

139
140

RESET]LAG

132
0042

0072: ???'?
0074

0074 11
0075 ??
0076 ??

0077 ?1

DR.

DR.

OIl.

141

DR.

142

4'H
; OVERLAYS DISKETIE STATUS

06CH

OW

; TIMER LOW WORD

72H

OW

; 1234H IF kEYBOARD RESET lHJERWAY

74H

DISK_STATUS

.8

; FIXED DISK STATUS BYTE

143

HF _NUN
CDHTROL_BYTE

DB
DB
DB

; COUNT OF FIXED DISK DRIVES

14.
145
14.

DATA

ENOS

147
148

COOE

SEGMENT

PORT_OFF

; CONTROL BYTE DRIVE OPTIOHS

; PORT OFFSET

14_

150

1--------------------------------------------------------

151

I HARDWARE SPECIFIC VALUES

152
153

CONTROLLER 110 PORT

154

> WHEN READ FROM:

Fixed Disk BIOS

A-85

LINE

LOC OBJ

SOURCE
CO~OlLER

155

HF _PORT+O - READ DATA (FROH

156

HF _PORT+l - READ CONTROLLER HARDWARE STATUS

157

TO CPU)

(CONTROLLER TO CPU I

158

HF]ORT+2: - READ CONFIGURATION SWITCHES

159

HF _PORT+3 - NOT USED

>

160

WHEN WRITTEN TO:

161

HF_PORT+O - WRITE DATA (FROM CPU TO CONTROLLER)

162

HF PORT-tl - COHTROLLER RESET

163

HF _PORT+:?: - CENERUE CONTROLLER SElECT PULSE

164

HF_PORT+3 - WRITE PATTERN TO DHA AND INTERRUPT

165

MASK REGISTER

166

0320

167
168
16.

Hf _PORT

0320H

; DISK PORT

0006

17'

RI_BUSY

EQU

000010008

; DISK PORT 1 BUSY BIT

0004-

171

RI_BUS

EOU

000001008

COt1t1ANO/OATA BIT

000,

172

RI_IONODE

EQU

000000108

NODE BIT

0001

173

Rl_REQ

EQU

00000001B

0000

17'
175
176
177

0082

178

0047
0046

; -------------------------------------------------------EOU

DMA_READ

EQU

OM_WRITE

EOU

OMA

EOU

DHA_HIGH

EOU

010001118

REQUEST BIT
; CHANNEl 3 (047H)
3 (048H)

010010118

; CHAHNE l

082H

; PORT FOR HIGH 4 BITS OF DNA

•

; DMA ADDRESS

17.

0000

18.
181

TST_RDY_tl1D

EOU

000000008

I CNTLR READY (OOHI

0001

RECAL_CHO

EQU

000000018

RECAL (OIHI

0003

18Z

SENSE_CHO

EOU

000000118

SENSE (03H I

0004

183

fMTDRV_Ct1D

EOU

000001008

DRIVE (04H I

ODDS

184

CHK_TRK_CtIJ

EOU

00000101B

T CHK (05HI

0006

185

FMTTRK_CMD

EOU

000001108

TRACK (06HI

0007

186
187
188

EOU

000001118

BAD

(07H)

READ_tND

EOU

000010008

READ

(08H)

DODA

WRITE_CHO

EQU

000010108

WRITE (DAHl

0008

FMTBAD_CMD

OOOB

18.

SEEK_CHO

EOU

000010118

SEEK

I OBH)

DaDe

19.

INIT_DRV_CMO

EOU

000011008

INlT

(OCHI

0000

191

RD_ECt_tND

EQU

000011018

BURST (DOH I

19Z

RO_BUFf _CMD

EOU

000011108

BUFFR I OEH)

WR_BUFf _ CHO

EOU

000011118

BUFfR I OFH I

RAH_OIAG_CMU

EQU

11100000B

RAM

IEOHI

ODE3

193
1.4
195

CHK_DRV_Ct1O

EQU

111000118

DRV

(E3H)

00E4

1.6

CNTLR_OIAG_CI1D

EQU

111001008

CNTLR (E4H I

RD_lONG_CMD

EOU

111001018

RlOHG ([5HI

WR_lONG_CMD

EOU

111001108

WlONG I E6H I

DOOE
DOOF
ODED

ODES

198

00E6

I"
0020

zoo

INT_CTl_PORT

EOU

Z.H

; 8259 CONTROL PORT

0020

ZD1

EO!

EOU

Z.H

; END OF INTERRUPT COMNAND

20Z
0008

ZD3

MAX_FILE

EQU

0002

zoo

S_NAXJIlE

EOU

Z.5
206

ASSUME

CS:CODE

0000

ZD7

ORG

OH

0000 55

Z.8

DB

055H

0001 AA

20'
Zl.

DB

OAAH

DB

160

0002 10

Zll

; GENERIC BIOS HEADER

212

1----------------------------------------------------------------

213

; FIXED DISK I/O SETUP

Z14
215

ESTABLISH TRANSFER VECTORS FOR THE FIXED DISK

216

PERfORM POWER ON DIAGNOSTICS

217

SHOULD AN ERROR OCCUR A "1701" MESSAGE IS DISPLAYED

218
219

,----------------------------------------------------------------

Z20
0003

0003 EBIE
0005 35303030303539

ZZl
ZZZ

PROC

FAR

JM"

SHORT

L3

223

DB

'5000059 I C lCOPYRIGHT

IBM 1982'

j

COPYRIGHT NOTICE

2.02:84329434FSO

5952.494748542:0
2.04942:402.03139
3832
002:3

0023 2:BCO
0025 6ED8

A-86

ZZ4
ZZ5
ZZ6
ZZ7

l3:
ASSlII1E

DS:Dutf"'IY

SUB

AX.AX

NOV

DS,AX

Fixed Disk BIOS

I ZERO

LOC OBJ
002:7 FA

LINE

...

SOURCE

".

CLI

MOV

AX,WORD PTR ORG_VECTOR

I GET DISKEnE VECTOR

I10V

WORD PTR DISK_VECTOR,AX

J

HOV

AX,WORD

0031 A30Z01

ZlO
ZlI
Zl'

HOY

WORD PTR OISK_VECTOR+2.AX

0034 C7064C005602

'33

MOV

NORD PTR ORG_ VECTOR,

003A 8COE4EOO

'34
'35

HOV
MOV

WORD PTR ORG_ VECTOR+2 .CS

0028 A14COO

0028 A30001
002E Al4EOO

003E B86007
0041 A33400
0044 BCOE3600

NORD PTA HDISK_INT.AY.

WORD PTR
WORD PTR
WORD PTR

MOV

WORD PTR HF_TBl_VEC+2.CS

'38

0050 684000
0060 8E08
0062 C6D6740000
0067 C606750000
DObe C606430000

0071 C606770000

'40
'41

,.,

, HDISK HAtI)lER

HDISK

J

I10V
ttOV
HOY
MOV
MOV

'3'

0058 seOE060l

AX, OFFSET HD_INT

'36

004E 8COE6600

Dose Fe

OFfSET DISICIO

'37

0048 C70664008601
0052 C7060401E703

INTO INT 40H

PTR DRG_VECTOR+2

INTERRUPT

HDISK_INT+Z,CS
BOOT_VEC.OFFSET BOOT_STRAP

I BOOTSTRAP

eOOT_YEC+2.CS

WORD PTR HF_TBL_VEC,OFFSET FD_TBl

I

PARAMETER

TBl

STI

'43
'44

ASSUME

'45

MOV

AX.DATA

MOV

OS.AX

MOV

OISK_STATUS,O

I RESET THE STArus INDICATOR

MOV

HF _NUM,O

j

ZERO COUNT OF DRIVES

MOV

CMD_BLOCK+l.O

I

DRIVE

MOV

PORT_OFF .0

; ZERO CARD OFfSET
; RETRY COUNT

'4.
'47
'4.
,4'
'50

OS:DATA
I ESTABLISH SEGI1ENT

ZERO. SET

VALUE IN BLOCK

'51

'5'
'53

MOV

CX.25H

0079
0079 E8F2QO

254

CALL

HD_RESET_l

'55

JHC

L7

LOOP

L4

0076 892500

OOlC 7305
DOlE E2F9

0080 E9BFOO

0083
0083 890100
0086 8A6000
0089 B80012
OOBt COB

008E 7303

'5.

'.1
,.,

'.3
'.4

..

0096 COB

2 ••

0098 7303

2 ••

009A E9A500

270
271

0090

l7:

'.0

,'.5
,.7

HOV

CX.l

MOV

ox.aOH

MOV

AX.1200H

lNT

13"

JNC

P7

JMP

ERROR_EX

HOV
'NT
JNC

1'"
ERROR_EX

MOV

TIMER_LOW. 0

HOV

AX,RESET]LAG

CHP

AX,lZ34H

; KEYBOARD RESET

IN

AL,021H

I TIMER

AI<)

Al,OFEH
021H , Al

; ENABLE TIMER

273
274

00A9 7506

'75
27.

MOV

,77
27.

00B3 24FE
00B5 E62:1

00B7
00S7 E86400
DOSA 7207
OOBe 880010

DOBF COB

00C1 7308
00C3
00C3 A16eoo

00C6 30BEOI
OOC9 72Et
Dace E87590

DaCE
DaCE 890100

0001 BA8000

0004 680011
0007 COl3
0009 7267
0006 B80009

OUT

,.4
,'.5

JC

PIO

MOV

AX,HlOOH

INT

13H

JNC

P2

MOV

AX. TIMER_lOW

CMP

AX.446D

I 25 SECONDS

JHP
P2:
CX,!

..
..

MOV

OX,80H

HOV
lNT

AX,llaOH

JC

ERROR_EX

I RECALIBRATE

13"

300
301

HOY

AX.0900H

INT

1'"

ODED 7260

30'
303

JC

ERROR_EX

00E2 BaOOtS

304

MOV

AX.ocaOCH

OOOE C013

I READY

J8

MOV

,
,.7
,
,..

; START TIMER

PI0:

"0
,92

, SKIP WAIT ON RESET

I RESET CONTROLLER

,.3

..,.1..
,'.3..
'.5

ZERO TIMER

P6:

27'

,
,

I

JNE

'.0
'.1
,.,

..
,.7

J COIfTROLLER DIAGNOSTICS

P.

JMP

00A3 AI7200
00A6 303412

0081 E42:1

AX.1400H

P9:

,72

0061

; CONTROLLER DIAGNOSTICS

P7:

0090 C7066COOOOOO

OOA8 C7066C009AOI

I RESET CONTROLLER
I TRY RESET AGAIN

JMP

'57

".
'5'

0093
0093 880014

0090 E9AFOO

lit:

I SET DRIVE PARAI1ETERS

i

Ot1A TO BUFFER

Fixed Disk BIOS

A-87

LaC OBJ

LINE

00E5 SEeD
00E7 2508
00E9 B8000F

OOEe COB
OOEE 7252

SOURCE

30.
306

I10V

ES,AX

sue

eX.BX

307
308

MOV
INT
Je

AX.OFODH

INC

HF _NUN

MOV
MOV
OUT
I10V
IN

DX.2:13H

I EXPANSION BOX

ALtO
DX,AL
OX,32lH

; nJRN BOX OFF
, TEST If CONTROLLER

AL.OX

I

30'

I SET SEGI1ENT

I WRITE SECTOR BUFFER

BH
ERROR_EX

310

OOF4 8A1302

311
31>
313

OOF7 BODO

31.

OOF9 EE

31'
310

DOFO FE067500

OOFA 8A2:103

OOFO EC
DO FE 240F

317
318

ANO

AL,OFH

0100 3eOF

31.
320
321

CM'
JE
MOV

AL.OFH

0102: 740b

0104 C7066(:00A401
OlOA
0100 BOFF

OIOF EE
OllO 890100
0113 8A8100

I CONTROLLER

I EXPANSION BOX

324
325

OX.At

; TURN BOX ON

320
327
328

MOV
MOV

eX.l

I

AX,AX

330

SUB

OIIC e80011
alIF COl3

333
334

0121 730B

335

0123 A16COO

33.

INT
JC
MOV
INT
JNC
MOV

'"

0126 306E01

AL,OFFH

AX,01100H

AX. TIMER_LOW
AX,4460

CM'
JB

P3

012B EB2.F90

33.

JM'

POD_DONE

012E

340

012E 880009

341

0131 con

0135 FE067500

342
343
344

0139 81FA8100

34.

0140 EBD4

'40
347
348

0142

34'
350
351
352

0142 BDOFOO

353

0145 2BCO

354
355
356

OBF 4.2

0147 8BFO
0149 89060090

357
358

0140 B700

O14F
014F 2E8AS46801
0154 MOE
0156 COlO
0158 46

0156 F9
DISC

"OV
INT
JC
INC
eM'
JA'
INC
JM'

0150 E421

AX,0900H

; INITIALIZE CHARACTERISTICS

13H
POD_DONE

HF _HUM

I TAllY ANOTHER DRIVE

DX.(80H + S_MA)CFILE -

1)

POD_DONE

OX
P3

; ----- POD ERROR

MOV
SUB

BP,OFH

"OV
MOV

SI.AX
CX,F17L

; MESSAGE CHAR .... CTER COl.INT

"OV

BH,O

; PAGE ZERO

"OV
MOV
INT
INe

AL.CS:Fl71SIJ
AH,140

• VIDEO OUT

10H
51

o

; t-IEXT CHAR

lOOP

OUT_CH

; DO MORE

ClI
IN

H,02lH

; BE SURE TIMER IS DISABLED

I

POD ERROR FLAG

AX.AX

OUT_CH:
~

GET BYTE

DISPLAY CHARACTER

STe
POD_DONE:

015F OCOI

308

OR

AL.OlH

0161 E621

OUT

021H.AL

0163 FB

36'
no

0164 E8ASOO

371

CALL

sn

,12

0167 CB

2.5 SECONDS

ERROR_EX:

35'
360
361

'0'
36.
367

DISC FA

I

P5:

36'
363
364

0159 E2F4

, RECAL

13H
P5

338

0130 7310

I RESET

13H
POD_DONE

0129 72EB

0133 7227

ATTEMPT NEXT DRIVES

OX,081H

P3:

011A 72.40

0118 C013

IS IN SYSTEM U't1T

TIMER_LOW.420D

BOX_ON:

"1
332

0116 28CO

BOX_ON

Ox.213H

32'

011b

• .• IS IN THE SYSTEM ltIIT

MOV
MOV
OUT

322
323

DIOA 8A1302

I DRIVE ZERO RESPONDED

DSBL

RET

n3
0168 31373031

37.

F17

DB

01701' ,OOH,OAH

375
n6
377

FI7L

,qt1

$-Fl1

01be 00
0160 OA
0006

Ol6E
016E 51
016F 52

A-88

376
37.

HO_RESET_l

PUSH
PUSH

Fixed Disk BIOS

PRDC

CX
OX

NEAR
I SAVE REGISTER

LOC OBJ

LINE

0170 Fe

380
301
382
383
30.
305
30.
307
3.0
389

0171 890001
0174
0174 E80706

0177 EE
0178 E80306
0178 EC

OI7t 2402

Ol7E 7403
0180 ElF2
0182 F9
0183
0183 5A

0184 59
0185 C3

39'
391
392
393
394
395
396
397
390
399

•••

SOURCE
CLC

0186
0186 26CO
0188 8ED8

016A FA
018S C7060401E703
0191 acOE0601
0195 C70676000102
0198 SCOE7AOO
019F FB

417
410
419
42.
4Z1
4Z.
423
424
425

01.1.0 890300
01A3
o tA3 51
QUA 2B02

01.1..6 2BCO
01.1..8 COl3
01.1..1. 720F
OlAC B80102
OlAf 2B02
OIBI 8EC2
01B3 BBOO7C
01B6 890100
OIB9 COl3
OIB8 59
OISC 730A
01BE eOFtao
OlCl 740A
OIC3 HOE
01C5 EB0690
DIce

JZ

PORT_l
OX,AL
PORT_l
At,OX
AL.Z
.3

lOOP

L'

ANO

; RETRY COlfIT

J RESET CARD

I CHECK STATUS

; ERROR BIT

STC

R3:

pop
pop

OX

i RESTORE REGISTER

CX

RET
HD_RESET_l

ENDP

DISK_SET1JP

ENDP

j----- INT 19 --------------------------------------------------INTERRUPT 19 BOOT STRAP LOADER

THE FIXED DISK aros REPLACES THE INTERRUPT 19
BOOT STRAP VECTOR WITH A POINTER TO THIS BOOT ROUTINE
RESET THE DEFAULT DISK AND DISKETTE PARAMETER VECTORS

-

J
J

THE BOOT BLOCK to BE READ IN WIll BE ATTEMPTED FROH
CYLINDER 0 SECTOR 1 OF THE DEVICE.
lltE BOOTSTRAP SEQUENCE IS:

> ATTEMPT TO lO'&'O fROM THE DISKETTE INTO THE BOOT
LOCATION (OOOQ:7COQ) At-ro

~ANSFER

COtfIROl THERE

> IF THE DISKEnE FAILS THE FIXED DISK IS TRIED FOR A
VALID BOOTSTRAP SLOCK. A VALID BOOT BLOCK ON THE
FIXED DISK CONSISTS OF THE BYTES

055H OAAH

AS ntE

LAST TWO BYTES OF THE BLOCK

> IF THE ABOVE FAILS CONTROL IS PASSED TO RESIDENT BASIC
;

----------------------------------------------------------------

BOOT_S~AP:

ASSUHE

DS: DUMMY, ES: DUMMY

SUB

AX,AX

Mav

DS~AX

; ESTABLISH SEGMENT

;----- RESET PARAMETER VECTORS

43.
431
432

434
435
436
437
430
439
44.
441
442
443
444
445
446
447
448
449
45.
451
452
453
454
455
456

CAll

IN

42'
427
428
429

'33

CX,OlOOH

OUT
CAll

40!

4'2
403
4.4
405
4.6
4.7
4.0
4.9
41.
411
412
413
41.
415
416

; CLEAR CARRY

rrov

L6:

CLI
MOV

WORD PTR HF _TBL_VEt. OFFSET FD_TBl

Mav

WORD

MOV

WORD PTR DISKETIE_PARH, OFFSET DISKETTE_TBL

I10V

WORD PTR DISKETTE_PARI1+2. cs

p~

HF _TBl_VEt+2, CS

STI

;----- ATTEMPT BOOTSTRAP FRDtI DISKETTE
HOV

ex.!

PUSH

CX

I SAVE RETRY COl.IIT

SUB

OX,DX

1 DRIVE ZERO

SUB

AX.AX

J RESET THE DISKETTE

INT
JC

13M
H2

; IF ERROR, TRY AGAIN

I10V

AX,0201H

j

SUB

OX.OX

HI:

H2.

i

Mav

ES.OX

I10V

BX,OFFSET BOOT_LOCN

I10V

CX.l

IPL_SYSTEM

; FILE 10 CAll
READ IN THE SINGLE SECTtIR

J ESTABLISH SEGf'lEHT

I SECTOR I. TRACK 0

IIIT

13H

I FILE 10 CALL

pop

CX

; RECOVER RETRY COUHT

JNO

H4

I CF SET BY ~CESSFUL READ

C11P

AH.SOH

; IF TIME OUT. NO RETRY

JZ

H5
HI
HS

; TRY FIXED DISK

lOOP
JMP

H4:

; SET RETRY tQlJfT

; DO IT FOR RETRY TIMES
; UNABLE TO IPL FRCH THE DIstC.ETTE
; IPL WAS SUCCESSFUL

Fixed Disk BIOS

A-89

LOC GBJ

LINE

SOURCE

01C8 EAOO7COOOO

457
456
459

;----- ATTEMPT BOOTSTRAP FROM FIXED DISK

460
461

H5:

Oleo

Oleo zeco

JHP

BOOT_LOCH

462
463

SUB

AX ,AX

SUB

OX,OX

464
465

INT
MOV

13H
CX.3

I SET RETRY COUNT

PUSH

ex

I SAVE RETRY COUNT

HOV

OX.OOSOH

I FIXEO DISK ZERO

SUB
INT

AX ,AX

; RESET THE FIXED DISK

13H

I FILE 10 CAll

JC
HOV

H7
AX,ClOlH

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DISI

>

Shift

Cyan

Yellow

High Intensity

3F

63

?

?

Shift

Cyan

White

High Intensity

40

64

@

@

Shift

Red

Black

Normal

41

65

A

A

Note 4

Red

Blue

Underline

42

66

B

B

Note 4

Red

Green

Normal

43

67

C

C

Note 4

Red

Cyan

Normal

44

68

D

D

Note 4

Red

Red

Normal

45

69

E

E

Note 4

Red

Magenta

Normal

46

70

F

F

Note 4

Red

Brown

Normal

47

71

G

G

Note 4

Red

Light Grey

Normal

48

72

H

H

Note 4

Red

Dark Grey

High Intensity

49

73

I

I

Note 4

Red

Light Blue

High Intensity
Underline

4A

74

J

J

Note 4

Red

Light Green

High Intensity

Of Characters, Keystrokes, and Colors

C-3

As Text Attributes

Value

Color/Graphics
Monitor Adapter

As Characters

Hex Dec Symbol

Keystrokes

IBM

Modes Background Foreground

Monochrome
Display
Adapter

4B

75

K

K

Note 4

Red

Light Cyan

High Intensity

4C

76

L

L

Note 4

Red

Light Red

High Intensity

4D

77

M

M

Note 4

Red

Light
Magenta

High Intensity

4E

78

N

N

Note 4

Red

Yellow

High Intensity

4F

79

0

0

Note 4

Red

White

High Intensity

50

80

P

P

Note 4

Magenta

Black

Normal

51

81

Q

Q

Note 4

Magenta

Blue

Underline

52

82

R

R

Note 4

Magenta

Green

Normal

53

83

S

S

Note 4

Magenta

Cyan

Normal

54

84

T

T

Note 4

Magenta

Red

Normal

55

85

U

U

Note 4

Magenta

Magenta

Normal

56

86

V

V

Note 4

Magenta

Brown

Normal

57

87

W

W

Note 4

Magenta

Light Grey

Normal

58

88

X

X

Note 4

Magenta

Dark Grey

High Intensity

59

89

Y

Y

Note 4

Magenta

Light Blue

High Intensity
Underline

5A

90

Z

Z

Note 4

Magenta

Light Green

High Intensity

5B

91

[

[

Magenta

Light Cyan

High Intensity

5C

92

\

\

Magenta

Light Red

High Intensity

5D

93

1

1

Magenta

Light
Magenta

High Intensity

5E

94

A

5F

95

-

60

96

61

97

a

a

62

98

b

b

"-

Shift

Magenta

Yellow

High Intensity

-

Shift

Magenta

White

High Intensity

Yellow

Black

Normal

Note 5

Yellow

Blue

Underline

Note 5

Yellow

Green

Normal
Normal

63

99

c

c

Note 5

Yellow

Cyan

64

100

d

d

Note 5

Yellow

Red

Normal

65

101

e

e

Note 5

Yellow

Magenta

Normal

66

102

f

f

Note 5

Yellow

Brown

Normal

C-4

Of Characters, Keystrokes, and Colors

As Text Attributes

Value

As Characters

Hex Dec Symbol

Keystrokes

Color/Graphics
Monitor Adapter

IBM
Monochrome
Display
Adapter
Modes Background Foreground

67

103

g

g

Note 5

Yellow

Light Grey

Normal

68

104

h

h

Note 5

Yellow

Dark Grey

High Intensity

69

105

i

i

Note 5

Yellow

Light Blue

High Intensity
Underline

6A

106

j

j

Note 5

Yellow

Light Green

High Intensity

6B

107

k

k

Note 5

Yellow

Light Cyan

High Intensity

6C

108

I

I

Note 5

Yellow

Light Red

High Intensity

60

109

m

m

Note 5

Yellow

Light
Magenta

High Intensity

6E

110

n

n

Note 5

Yellow

Yellow

High Intensity

6F

111

a

a

Note 5

Yellow

White

High Intensity

70

112

p

p

Note 5

White

Black

Reverse Video

71

113

q

q

Note 5

White

Blue

Underline

72

114

r

r

Note 5

White

Green

Normal

73

115

s

s

Note 5

White

Cyan

Normal

74

116

f

f

Note 5

White

Red

Normal

Magenta

Normal

75

117

u

u

Note 5

White

76

118

v

v

Note 5

White

Brown

Normal

77

119

w

w

Note 5

White

Light Grey

Normal

78

120

x

x

Note 5

White

Dark Grey

Reverse Video
High Intensity
Underline

121

Y

Y

Note 5

White

Light Blue

7A 122

z

z

Note 5

White

Light Green

High Intensity

123

{

{

Shift

White

Light Cyan

High Intensity

7C

124

I
I

I
I

Shift

White

Light Red

High Intensity

7D

125

I

I

Shift

White

Light
Magenta

High Intensity

7E

126

-

-

Shift

White

Yellow

High Intensity

7F

127

.6.

Ctrl -

White

White

High Intensity

79

7B

Of Characters, Keystrokes, and Colors C-5

As Text Attributes

Value

As Characters

Hex Dec Symbol

....

Keystrokes

IBM
Monochrome
Display
Modes Background Foreground
Adapter
Color/Graphics
Monitor Adapter

BO to FF Hex are Flashing in both Color & IBM Monochrome· • • •

C;

Alt 128

Note 6

Black

Black

Non-Display

129

U

Alt 129

Note 6

Black

Blue

Underline

130

Alt 130

Note 6

Black

Green

Normal

Alt 131

Note 6

Black

Cyan

Normal

132

e
a
a

Alt 132

Note 6

Black

Red

Normal

85

133

a

Alt 133

Note 6

Black

Magenta

Normal

86

134

fI

Alt 134

Note 6

Black

Brown

Normal

87

135

C

Alt 135

Note 6

Black

Light Grey

Normal

88

136

Alt 136

Note 6

Black

Dark Grey

Non-Display

89

137

e
e

Alt 137

Note 6

Black

Light Blue

High Intensity
Underline

8A

138

e

Alt 138

Note 6

Black

Light Green

High Intensity

8B

139

"

Alt 139

Note 6

Black

Light Cyan

High Intensity

8C

140

i

Alt 140

Note 6

Black

Light Red

High Intensity

80

141

1

Alt 141

Note 6

Black

Light
Magenta

High Intensity

8E

142

A

Alt 142

Note 6

Black

Yellow

High Intensity

8F

143

A

Alt 143

Note 6

Black

White

High Intensity

90

144

~

Alt 144

Note 6

Blue

Black

Normal

91

145

ae

Alt 145

Note 6

Blue

Blue

Underline

92

146

I>E.

Alt 146

Note 6

Blue

Green

Normal

93

147

6

Alt 147

Note 6

Blue

Cyan

Normal

94

148

0

Alt 148

Note 6

Blue

Red

Normal

80

128

81
82
83

131

84

95

149

b

Alt 149

Note 6

Blue

Magenta

Normal

96

150

U

Alt 150

Note 6

Blue

Brown

Normal

97

151

U

Alt 151

Note 6

Blue

Light Grey

Normal

98

152

Y

Alt 152

Note 6

Blue

Dark Grey

High Intensity

99

153

6

Alt 153

Note 6

Blue

Light Blue

High Intensity
Underline

9A

154

u

Alt 154

Note 6

Blue

Light Green

High Intensity

C-6

Of Characters, Keystrokes, and Colors

As Text Attributes

Value

As Characters

Hex Dec Symbol
9B 155

Keystrokes

IBM
Monochrome
Display
Adapter
Modes Background Foreground
Color/Graphics
Monitor Adapter

¢

Alt 155

Note 6

Blue

Light Cyan

High Intensity

9C 156

£

Alt 156

Note 6

Blue

Light Red

Hig h Intensity

9D 157

¥

Alt 157

Note 6

Blue

Light
Magenta

High Intensity

9E

158

Pt

Alt 158

Note 6

Blue

Yellow

High Intensity

9F

159

Note 6

Blue

White

High Intensity

AO 160

f
a

Alt 159
Alt 160

Note 6

Green

Black

Normal

A1

161

i

Alt 161

Note 6

Green

Blue

Underline

A2

162

6

Alt 162

Note 6

Green

Green

Normal

A3

163

U

Alt 163

Note 6

Green

Cyan

Normal

A4 164

II

Alt 164

Note 6

Green

Red

Normal

A5

165

iii

Alt 165

Note 6

Green

Magenta

Normal

A6 166

.!!

Alt 166

Note 6

Green

Brown

Normal

A7 167

£

Alt 167

Note 6

Green

Light Grey

Normal

A8 168

l

Alt 168

Note 6

Green

Dark Grey

High Intensity

169

r-

Alt 169

Note 6

Green

Light Blue

High Intensity
Underline

AA 170

----,

Alt 170

Note 6

Green

Light Green

High Intensity

AB 171

V,

Alt 171

Note 6

Green

Light Cyan

High Intensity

AC 172

A9

V-

Alt 172

Note 6

Green

Light Red

High Intensity

AD 173

i

Alt 173

Note 6

Green

Light
Magenta

High Intensity

AE 174

«
»

Alt 174

Note 6

Green

Yellow

High Intensity

Alt 175

Note 6

Green

White

High Intensity

Alt 176

Note 6

Cyan

Black

Normal

AF

175

80 176
177

I

Alt 177

Note 6

Cyan

Blue

Underline

B2 178

I

Alt 178

Note 6

Cyan

Green

Normal

B3 179

Alt 179

Note 6

Cyan

Cyan

Normal

B4 180 f--

Alt 180

Note 6

Cyan

Red

Normal

~

Alt 181

Note 6

Cyan

Magenta

Normal

B6 182 f-I

Alt 182

Note 6

Cyan

Brown

Normal

Bl

B5 181

Of Characters, Keystrokes, and Colors C-7

As Text Attributes

As Characters

Value

Hex Dec Symbol
B7

183

B8

184

B9

185

III
R

f--J

Keystrokes

Color /Graphics
Monitor Adapter

IBM
Monochrome
Display
Adapter
Modes Background Foreground

Alt 183

Note 6

Cyan

Light Grey

Normal

Alt 184

Note 6

Cyan

Dark Grey

High Intensity

Alt 185

Note 6

Cyan

Light Blue

High Intensity
Underline

Alt 186

Note 6

Cyan

Light Green

High Intensity

Alt 187

Note 6

Cyan

Light Cyan

High Intensity

Alt 188

Note 6

Cyan

Light Red

High Intensity

Note 6

Cyan

Light
Magenta

High Intensity

II
BA 186
BB 187
BC 188
BD 189

BE

190

BF

191

CO 192

hl
~

WJ
P
h
L-

Alt 189

Alt 190

Note 6

Cyan

Yellow

High Intensity

Alt 191

Note 6

Cyan

White

High Intensity

Alt 192

Note 6

Red

Black

Normal

Cl

193

Alt 193

Note 6

Red

Blue

Underline

C2

194

Alt 194

Note 6

Red

Green

Normal

C3

195

Alt 195

Note 6

Red

Cyan

Normal

C4

196

Alt 196

Note 6

Red

Red

Normal

C5

197

Alt 197

Note 6

Red

Magenta

Normal

C6

198

Alt 198

Note 6

Red

Brown

Normal

C7

199

Alt 199

Note 6

Red

Light Grey

Normal

C8

200

Alt 200

Note 6

Red

Dark Grey

High Intensity

C9

201

Alt 201

Note 6

Red

Light Blue

High Intensity
Underline

CA 202 - - I L -

Alt 202

Note 6

Red

Light Green

High Intensity

CB 203 ---, r--

Alt 203

Note 6

Red

Light Cyan

High Intensity

I;:::

Alt 204

Note 6

Red

Light Red

High Intensity

Alt 205

Note 6

Red

Light
Magenta

High Intensity

Alt 206

Note 6

Red

Yellow

High Intensity

Alt 207

Note 6

Red

White

High Intensity

Alt 208

Note 6

Magenta

Black

Normal

CC

204

t===

IfL==

Ii

CD 205

CE

206

CF

207

DO 208

C-8

~~
I

Of Characters, Keystrokes, and Colors

As Text Attributes

Value
-Hex Dec

Color / Graphics
Monitor Adapter

As Characters

Isyn;bOl

Ii:

,~,

,u

".~

Modes IrD~
.... '

209
02 210

IBM
Monochrome
Display
Adapter
'lI. uollld l:oregrou'1(f

6

lagenta

Alt 210

Note 6

Magenta

03 211

u::=

Alt 211

Note 6

04 212

t=

Alt 212

Note 6

05 2

F=

Alt 213

i
Green

Normal

Magenta

Cyan

Normal

Magenta

Red

Normal

6

Magenta

Magenta

Normal

214

Note 6

Magenta

Brown

Alt 215

Note 6

Magenta

Light Grey

Normal

Alt 216

Note 6

Magenta

Oark Grey

High Intensity

Alt 217

Note 6

Magenta

Light Blue

High Intensity
Underline

OA 218

Alt 218

Note 6

Magenta

Light Green

High Intensity

OB 1219

219

6

Magenta

TT

06 214

~

I

07 215
08 216
09 217
I--

Cyan

Hig

Inte

i

OC 220

Alt 220

Note 6

Magenta

Light Red

High Intensity

00 221

Alt 221

Note 6

Magenta

Light
Magenta

High Intensity

OE 222

Alt 222

Note 6

Magenta

Yellow

High Intensity

OF

Alt 223

6

2

6

223

EO 1224
E1

225

{3

E2

226

['

E3 1227
E4 1228

~

E5 1229
E6

230

Il

E7 1231

Alt 225

Note 6

Alt 226

Note 6

Alt 227

6

Alt 228

Note 6

Alt 229

N

'te

Mage

High I

I

mal

Yellow

Blue

Underline

Yellow

Green

Normal

Iy

Cyan

Yellow

Red

Normal

6

I Yellow

Ma

Nor

Yellow

Alt 230

Note 6

Alt 231

N

6 1 Yellow

,ity

31

Brown

Normal

Light Grey

N

E8

232



Alt 232

Note 6

Yellow

Dark Grey

High Intensity

E9

233

IJ

Alt 233

Note 6

Yellow

Light Blue

High Intensity
Underline

EA 234

n

Alt 234

Note 6

Yellow

Light Green

High Intensity

EB

0

Alt 235

Note 6

Yellow

Light Cyan

High Intensity

235

Of Characters, Keystrokes, and Colors

C-9

As Text Attributes

Value

As Characters

Hex Dec Symbol
EC

Keystrokes

Color/Graphics
Monitor Adapter

IBM
Monochrome
Display
Modes Background Foreground
Adapter

236

00

Alt 236

Note 6

Yellow

Light Red

High Intensity

ED 237

q,

Alt 237

Note 6

Yellow

Light
Magenta

High Intensity

EE

238

<

Alt 238

Note 6

Yellow

Yellow

High Intensity

EF

239

n

Alt 239

Note 6

Yellow

White

High Intensity

FO

240

-

Alt 240

Note 6

White

Black

Reverse Video

F1

241

±

Alt 241

Note 6

White

Blue

Underline

F2

242

:2

Alt 242

Note 6

White

Green

Normal

F3

243

S

Alt 243

Note 6

White

Cyan

Normal

r

F4

244

F5

245

Alt 244

Note 6

White

Red

Normal

Alt 245

Note 6

White

Magenta

Normal

F6

246

Alt 246

Note 6

White

Brown

Normal

F7

247

=

Alt 247

Note 6

White

Light Grey

Normal

F8

248

0

Alt 248

Note 6

White

Dark Grey

Reverse Video

F9

249

•

Alt 249

Note 6

White

Light Blue

High Intensity
Underline

FA

250

Note 6

White

Light Green

High Intensity

251

•
V-

Ait 250

FB

Alt 251

Note 6

White

Light Cyan

H ig h Intensity

Fe

252

."

Alt 252

Note 6

White

Light Red

High Intensity

FD

253

2

Alt 253

Note 6

White

Light
Magenta

High Intensity

FE

254

Alt 254

Note 6

White

Yellow

High Intensity

FF

255

Alt 255

Note 6

White

White

High Intensity

C-IO

J

•

BLANK

Of Characters, Keystrokes, and Colors

NOTE 1

Asterisk (*) can easily be keyed using two methods:
1) hit the Pr'. Sc key or 2) in shift mode hit the

[§] key.
NOTE 2

I

I

Period (.) can easily be keyed using two methods:
1) hit theW key or 2) in shift or Num Lock

I

mode hit the D~II key.
NOTE 3

Numeric characters (0-9) can easily be keyed
using two methods: 1) hit the numeric keys on the
top row of the typewriter portion of the keyboa rd
or 2) in shift or Num Lock mode hit the numeric
keys in the 10-key pad portion of the keyboard.

NOTE 4

Upper case alphabetic characters (A-Z) can easily
be keyed in two modes: 1) in shift mode the
appropriate alphabetic key or 2) in Caps Lock
mode hit the appropriate alphabetic key

NOTE 5

Lower case alphabetic characters (a-z) can easily
be keyed in two modes: 1) in "normal" mode hit
the appropriate key or 2) in Caps Lock
combined with shift mode hit the appropriate alphabetic
key.

NOTE 6

The 3 digits after the Alt key must be typed from
the numeric key pad (keys 71-73,75-77,79-82).
Character codes 000 through 255 can be entered in
this fashion. (With Caps Lock activated, character
codes 97 through 122 will display upper case
rather than lower case alphabetic characters.)

Of Characters, Keystrokes, and Colors

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Of Characters, Keystrokes, and Colors C-13

Notes:

C-14

Of Characters, Keystrokes, and Colors

APPENDIX D: LOGIC DIAGRAMS

System Board ......................................
Keyboard - Type 1 .................................
Keyboard - Type 2 .................................
Expansion Board ...................................
Extender Card .....................................
Receiver Card .....................................
Printer ............................................
Printer Adapter ....................................
Monochrome Display Adapter .......................
Color/Graphics Monitor Adapter .....................
Color Display ......................................
Monochrome Display ...............................
5-1/4 Inch Diskette Drive Adapter ...................
5-1/4 Inch Diskette Drive - Type 1 ...................
5-1/4 Inch Diskette Drive - Type 2 ...................
Fixed Disk Drive Adapter ...........................
Fixed Disk Drive - Type 1 ..........................
Fixed Disk Drive - Type 2 ..........................
32K Memory Expansion Option ......................
64K Memory Expansion Option ......................
64/256K Memory Expansion Option ..................
Game Control Adapter ..............................
Prototype Card ....................................
Asynchronous Communications Adapter ...............
Binary Synchronous Communications Adapter ..........
SDLC Communications Adapter .....................

Logic Diagrams

D-2
D-12
D-14
D-15
D-16
D-19
D-22
D-25
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D-49
D-52
D-54
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APPENDIX E: SPECIFICATIONS

System Unit
Size:
Length--19.6 in (500 mm)
Depth--16.1 in (410 mm)
Height--5.5 in (142 mm)
Weight:
32 lb (14.5 kb)
Power Cables:
Length--6 ft (1. 83m)
Size--18 AWG
Environment:
Air Temperature
System ON, 60° to 90° F (15.6° to 32.2° C)
System OFF, 50° to 110° F (l0° to 43° C)
Humidity
System ON, 8% to 80%
System OFF, 20% to 80%
Heat Output:
717 BTU/hr
Noise Level:
49.5 dB(a) (System unit with monochrome display and
expansion unit attached.)
Electrical:
Nominal--120 Vac
Minimum--104 Vac
Maximum--127 Vac

Keyboard
Size:
Length--19.6 in (500 mm)
Depth--7.87 in (200 mm)
Height--2.2 in (57 mm)
Weight:
6.5 lb (2.9 kg)

Specifications

E·l

Color Display
Size:
Length--1S.4 in (392 mm)
Depth--1S.6 in (407 mm)
Height--11. 7 in (297 mm)
Weight:
26 lb (11.8 kg)
Heat Output:
240 BTU/hr
Power Cables:
Length--6 ft (1.83 m)
Size--18 AWG
Signal Cable:
Length--S ft (1.5 m)
Size--22 A WG

Expansion Unit
Size:
Length--19.6 in (SOO mm)
Depth--16.1 in (410 mm)
Height--S.S in (142 mm)
Weight:
33 lb (14.9 kg)
Power Cables:
Length--6 ft (1. 83m)
Size--18 AWG
Signal Cable:
Length--3.28 ft (1 m)
Size--22 A WG
Environment:
Air Temperature
System ON, 60° to 90° F (15.6° to 32.2° C)
System OFF, 50° to 110° F (10° to 43° C)
Humidity
System ON, 8% to 80%
System OFF, 20% to 80%
Heat Output:
717 BTU/hr
Electrical:
Nominal--120 Vac
Minimum--104 Vac
Maximum--127 Vac
E-2

Specifications

Monochrome Display
Size:
Length--14.9 in (380 mm)
Depth--13.7 in (350 mm)
Height--11 in (280 mm)
Weight:
17.3 lb (7.9 kg)
Heat Output:
325 BTU/hr
Power Cable:
Length--3 ft (.914 m)
Size--18 AWG
Signal Cable:
Length--4 ft (1.22 m)
Size--22 A WG

80 CPS Printers
Size:
Length--15.7 in (400 mm)
Depth--14.5 in (370 mm)
Height--4.3 in (110 mm)
Weight:
12.91b (5.9 kg)
Power Cable:
Length--6 ft (1.83 mm)
Size--18 A WG
Signal Cable:
Length--6 ft (1.83 m)
Size--22 A WG
Heat Output:
341 BTU/hr (maximum)
Electrical:
Nominal--120 Vac
Minimum--104 Vac
Maximum--127 Vac

Specifications

E-3

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1 - 32K option
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128K + (256K on System Board)

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224K + (256K on System Board)

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288K + (256K on System Board)

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GLOSSARY

J.Ls: Microsecond.

adapter: An auxiliary system or unit used to extend the operation
of another system.
address bus: One or more conductors used to carry the binarycoded address from the microprocessor throughout the rest of the
system.

all points addressable (APA): A mode in which all points on a
displayable image can be controlled by the user.
alpanumeric (A/N): Pertaining to a character set that contains
letters, digits, and usually other characters, such as punctuation
marks. Synonymous with alphanumeric.
American Standard Code for Information Interchange
(ASCII): The standard code, using a coded character set
consisting of 7-bit coded characters (8 bits including parity
check), used for information interchange among data processing
systems, data communication systems and associated equipment.
The ASCII set consists of control characters and graphic
characters.
A/N: Alphanumeric.
analog: (1) pertaining to data in the form of continuously variable
physical quantities. (2) Contrast with digital.
AND: A logic operator having the property that if P is a
statement, Q is a statement, R is a statement, ... ,then the AND of
P, Q, R, .. .is true if all statements are true, false if any statement is
false.
APA: All points addressable.
ASCII: American Standard Code for Information Interchange.

Glossary H-I

assembler: A computer program used to assemble. Synonymous
with assembly program.
asynchronous communications: A communication mode in
which each single byte of data is synchronized, usually by the
addition of start/stop bits.
BASIC: Beginner's all-purpose symbolic instruction code.
basic input/output system (BIOS): Provides the device level
control of the major I/O devices in a computer system, which
provides an operational interface to the system and relieves the
programmer from concern over hardware device characteristics.
baud: (1) A unit of signaling speed equal to the number of
discrete conditions or signal events per second. For example, one
baud equals one-half dot cycle per second in Morse code, one bit
per second in a train of binary signals, and one 3-bit value per
second in a train of signals each of which can assume one of eight
different states. (2) In asynchronous transmission, the unit of
modulation rate corresponding to one unit of interval per second;
that is, if the duration of the unit interval is 20 milliseconds, the
modulation rate is 50 baud.
BCC: Block-check character.
beginner's all-purpose symbolic instruction code (BASIC): A
programming language with a small repertoire of commands and a
simple syntax, primarily designed for numerical application.
binary: (1) Pertaining to a selection, choice, or condition that has
two possible values or states. (2) Pertaining to a fixed radix
numeration system having a radix of two.
binary digit: (1) In binary notation, either of the characters 0 or
1. (2) Synonymous with bit.
binary notation: Any notation that uses two different characters,
usually the binary digits 0 and 1.
binary synchronous communications (BSC): A standardized
procedure, using a set of control characters and control character
sequences for synchronous transmission of binary-coded data
between stations.
H-2

Glossary

BIOS: Basic input/output system.
bit: In binary notation, either of the characters 0 or 1.
bits per second (bps): A unit of measurement representing the
number of discrete binary digits which can be transmitted by a
device in one second.
block-check character (BCC): In cyclic redundancy checking, a
character that is transmitted by the sender after each message
block and is compared with a block-check character computed by
the receiver to determine if the transmission was successful.
boolean operation: (1) Any operation in which each of the
operands and the result take one of two values. (2) An operation
that follows the rules of boolean algebra.
bootstrap: A technique or device designed to bring itself into a
desired state by means of its own action; that is, a machine routine
whose first few instructions are sufficient to bring the rest of itself
into the computer from an input device.
bps: Bits per second.
BSC: Binary synchronous communications.
buffer: (1) An area of storage that is temporarily reserved for use
in performing an input/output operation, into which data is read or
from which data is written. Synonymous with I/O area. (2) A
portion of storage for temporarily holding input or output data.
bus: One or more conductors used for transmitting signals or
power.
byte: (1) A binary character operated upon as a unit and usually
shorter than a computer word. (2) The representation of a
character.
CAS: Column address strobe.
cathode ray tube (CRT): A vacuum tube display in which a
beam of electrons can be controlled to form alphanumeric
characters or symbols on a luminescent screen, for example by
use of a dot matrix.
Glossary H-3

cathode ray tube display (CRT display): (1) A device that
presents data in visual form by means of controlled electron
beams. (2) The data display produced by the device as in (1).
CCITT: Comite Consultatif International Telegrafique et
Telephonique.
central processing unit (CPU): A functional unit that consists
of one or more processors and all or part of internal storage.
channel: A path along which signals can be sent; for example,
data channel or I/O channel.
characters per second (cps): A standard unit of measurement
for printer output.
code: (I) A set of unambiguous rules specifying the manner in
which data may be represented in a discrete form. Synonymous
with coding scheme. (2) A set of items, such as abbreviations,
representing the members of another set. (3) Loosely, one or more
computer programs, or part of a computer program. (4) To
represent data or a computer program in a symbolic form that can
be accepted by a data processor.
column address strobe (CAS): A signal that latches the column
addresses in a memory chip.
Comite Consultatif International Telegrafique et Telephonique
(CCITT): Consultative Committee on International Telegraphy
and Telephony.
computer: A functional unit that can perform substantial
computation, including numerous arithmetic operations, or logic
operations, without intervention by a human operator during the
run.
configuration: (1) The arrangement of a computer system or
network as defined by the nature, number, and the chief
characteristics of its functional units. More specifically, the term
configuration may refer to a hardware configuration or a software
configuration. (2) The devices and programs that make up a
system, subsystem, or network.

H-4

Glossary

conjunction: (1) The boolean operation whose result has the
boolean value 1 if, and only if, each operand has the boolean
value 1. (2) Synonymous with AND operation.
contiguous: (1) Touching or joining at the edge or boundary.
(2) Adjacent.
CPS: Characters per second.
CPU: Central processing unit.
CRC: Cyclic redundancy check.
CRT: Cathode ray tube.
CRT display: Cathode ray tube display.
CTS: Clear to send. Associated with modem control.
cyclic redundancy check (CRC): (1) A redundancy check in
which the check key is generated by a cyclic algorithm. (2) A
system of error checking performed at both the sending and
receiving station after a block-check character has been
accumulated.
cylinder: (1) The set of all tracks with the same nominal distance
from the axis about which the disk rotates. (2) The tracks of a
disk storage device that can be accessed without repositioning the
access mechanism.
daisy-chained cable: A type of cable that has two or more
connectors attached in series.
data: (1) A representation of facts, concepts, or instructions in a
formalized manner suitable for communication, interpretation, or
processing by humans or automatic means. (2) Any
representations, such as characters or analog quantities, to which
meaning is, or might be assigned.
decoupling capacitor: A capacitor that provides a lowimpedance path to ground to prevent common coupling between
states of a circuit.
Deutsche Industrie Norm (DIN): (1) German Industrial
Norm. (2) The committee that sets German dimension standards.
Glossary

H-5

digit: (1) A graphic character that represents an integer, for
example, one of the characters 0 to 9. (2) A symbol that
represents one of the non-negative integers smaller than the radix.
For example, in decimal notation, a digit is one of the characters
from 0 to 9.
digital: (1) Pertaining to data in the form of digits. (2) Contrast
with analog.
DIN: Deutsche Industrie Norm.
DIN connector: One of the connectors specified by the DIN
standardization committee.
DIP: Dual in-line package.
direct memory access (D MA): A method of transferring data
between main storage and I/O devices that does not require
processor intervention.
disk: Loosely, a magnetic disk unit.
diskette: A thin, flexible magnetic disk and a semi-rigid
protective jacket, in which the disk is permanently enclosed.
Synonymous with flexible disk.
DMA: Direct memory access.
DSR: Data set ready. Associated with modem control.
DTR: Data terminal ready. Associated with modem control.
dual in-line package (DIP): A widely used container for an
integrated circuit. DIPs are pins usually in two parallel rows.
These pins are spaced 1/10 inch apart and come in different
configurations ranging from 14-pin to 40-pin configurations.
EBCDIC: Extended binary-coded decimal interchange code.
ECC: Error checking and correction.
edge connector: A terminal block with a number of contacts
attached to the edge of a printed circuit board to facilitate plugging
into a foundation circuit.

H-6

Glossary

EIA: Electronic Industries Association.
EIA/CCITT: Electronics Industries Association/Consultative
Committee on International Telegraphy and Telephony.
end-of-text-character (ETX): A transmission control character
used to terminate text.
end-of-transmission character (EOT): A transmission control
character used to indicate the conclusion of a transmission,
which may have included one or more texts and any associated
message headings.
EOT: End-of-transmission character.
EPROM: Erasable programmable read-only memory.
erasable programmable read-only memory (EPROM): A
storage device whose contents can be changed by electrical
means. EPROM information is not destroyed when power is
removed.
error checking and correction (ECC): The detection and
correction of all single-bit, double-bit, and some mUltiple-bit
errors.
ETX: End-of-text character.
extended binary-coded decimal interchange code
(EBCDIC): A set of 256 characters, each represented by eight
bits.
flexible disk: Synonym for diskette.
firmware: Memory chips with integrated programs already
incorporated on the chip.
gate: (1) A device or circuit that has no output until it is triggered
into operation by one or more enabling signals, or until an input
signal exceeds a predetermined threshold amplitude. (2) A signal
that triggers the passage of other signals through a circuit.
graphic: A symbol produced by a process such as handwriting,
drawing, or printing.
Glossary H-7

hertz (Hz): A unit of frequency equal to one cycle per second.
hex: Abbreviation for hexadecimal.
hexadecimal: Pertaining to a selection, choice, or condition that
has 16 possible values or states. These values or states usually
contain 10 digits and 6 letters, A through F. Hexadecimal digits
are equivalent to a power of 16.
high-order position: The leftmost position in a string of
characters.
Hz: Hertz.
interface: A device that alters or converts actual electrical signals
between distinct devices, programs, or systems.
k: An abbreviation for the prefix kilo; that is, 1,000 in decimal
notation.
K: When referring to storage capacity, 2 to the tenth power;
1,024 in decimal notation.
KB: Kilobyte; 1,024 bytes.
kHz: A unit of frequency equal to 1,000 hertz.
kilo (k): One thousand.
latch: (1) A feedback loop in symmetrical digital circuits used to
maintain a state. (2) A simple logic-circuit storage element
comprising two gates as a unit.
LED: Light-emitting diode.
light-emitting diode (LED): A semi-conductor chip that gives
off visible or infrared light when activated.
low-order position: The rightmost position in a string of
characters.
m: (1) Milli; one thousand or thousandth part. (2) Meter.

H-8

Glossary

M: Mega; 1,000,000 in decimal notation. When referring to
storage capacity, 2 to the twentieth power; 1,048,576 in decimal
notation.

rnA: Milliampere.
machine language: (1) A language that is used directly by a
machine. (2) Another term for computer instruction code.
main storage: A storage device in which the access time is
effectively independent of the location of the data.
MB: Megabyte, 1,048,576 bytes.
mega (M): 10 to the sixth power, 1,000,000 in decimal notation.
When referring to storage capacity, 2 to the twentieth power,
1,048,576 in decimal notation.
megabyte (MB): 1,048,576 bytes.
megahertz (MHz): A unit of measure of frequency. 1 megahertz
equals 1,000,000 hertz.
MFM: Modified frequency modulation.
MHz: Megahertz.
microprocessor: An integrated circuit that accepts coded
instructions for execution; the instructions may be entered,
integrated, or stored internally.
microsecond (Jls): One-millionth of a second.
milli (m): One thousand or one thousandth.
milliampere (rnA): One thousandth of an ampere.
millisecond (ms): One thousandth of a second.
mnemonic: A symbol chosen to assist the human memory; for
example, an abbreviation such a "mpy" for "mUltiply."
mode: (1) A method of operation; for example, the binary mode,
the interpretive mode, the alphanumeric mode. (2) The most
frequent value in the statistical sense.
Glossary

H-9

modem: (Modulator-Demodulator) A device that converts serial
(bit by bit) digital signals from a business machine (or data
terminal equipment) to analog signals which are suitable for
transmission in a telephone network. The inverse function is also
performed by the modem on reception of analog signals.
modified frequency modulation (MFM): The process of
varying the amplitude and frequency of the "write" signal. MFM
pertains to the number of bytes of storage that can be stored on
the recording media. The number of bytes is twice the number
contained in the same unit area of recording media at single
density.
modulo check: A calculation performed on values entered into a
system. This calculation is designed to detect errors.
monitor: (1) A device that observes and verifies the operation of
a data processing system and indicates any specific departure
from the norm. (2) A television type display, such as the IBM
Monochrome Display. (3) Software or hardware that observes,
supervises, controls, or verifies the operations of a system.
ms: Millisecond; one thousandth of a second.
multiplexer: A device capable of interleaving the events of two or
more activities, or capable of distributing the events of an
interleaved sequence to the respective activities.
NAND: A logic operator having the property that if P is a
statement, Q is a statement, R is a statement, ... ,then the NAND
of P ,Q,R, .. .is true if at least one statement is false, false if all
statements are true.
nanosecond (ns): One-thousandth-millionth of a second.
nonconjunction: The dyadic boolean operation the result of
which has the boolean value 0 if, and only if, each operand has
the boolean value 1.
non-return-to-zero inverted (NRZI): A transmission encoding
method in which the data terminal equipment changes the signal
to the opposite state to send a binary 0 and leaves it in the same
state to send a binary 1.

H -10 Glossary

NOR: A logic operator having the property that if P is a
statement, Q is a statement, R is a statement, ... ,then the NOR of
P,Q,R, .. .is true if all statements are false, false if at least one
statement is true.
NOT: A logical operator having the property that if P is a
statement, then the NOT of P is true if P is false, false if P is true.
NRZI: Non-return-to-zero inverted.
ns: Nanosecond; one-thousandth-millionth of a second.
operating system: Software that controls the execution of
programs; an operating system may provide services such as
resource allocation, scheduling, input/output control, and data
management.
OR: A logic operator having the property that if P is a statement,
Q is a statement, R is a statement, ... ,then the OR of P ,Q,R, .. .is
true if at least one statement is true, false if all statements are
false.
output: Pertaining to a device, process, or channel involved in an
output process, or to the data or states involved in an output
process.
output process: (1) The process that consists of the delivery of
data from a data processing system, or from any part of it. (2) The
return of information from a data processing system to an end
user, including the translation of data from a machine language
to a language that the end user can understand.
overcurrent: A current of higher than specified strength.
overvoltage: A voltage of higher than specified value.
parallel: (1) Pertaining to the concurrent or simultaneous
operation of two or more devices, or to the concurrent
performance of two or more activities. (2) Pertaining to the
concurrent or simultaneous occurrence of two or more related
activities in multiple devices or channels. (3) Pertaining to the
simultaneity of two or more processes. (4) Pertaining to the
simultaneous processing of the individual parts of a whole, such as
the bits of a character and the characters of a word, using separate
facilities for the various parts. (5) Contrast with serial.
Glossary

H-11

PEL: Picture element.
personal computer: A small home or business computer that has
a processor and keyboard that can be connected to a television or
some other monitor. An optional printer is usually available.
picture element (PEL): (1) The smallest displayable unit on a
display. (2) Synonymous with pixel, PEL.
pinout: A diagram of functioning pins on a pinboard.
pixel: Picture element.
polling: (1) Interrogation of devices for purposes such as to avoid
contention, to determine operational status, or to determine
readiness to send or receive data. (2) The process whereby
stations are invited, one at a time, to transmit.
port: An access point for data entry or exit.
printed circuit board: A piece of material, usually fiberglass,
that contains a layer of conductive material, usually metal.
Miniature electronic components on the fiberglass transmit
electronic signals through the board by way of the metal layers.
program: (1) A series of actions designed to achieve a certain
result. (2) A series of instructions telling the computer how to
handle a problem or task. (3) To design, write, and test computer
programs.
programming language: (1) An artificial language established
for expressing computer programs. (2) A set of characters and
rules, with meanings assigned prior to their use, for writing
computer programs.
PROM: Programmable read-only memory.
propagation delay: The time necessary for a signal to travel from
one point on a circuit to another.
radix: (1) In a radix numeration system, the positive integer by
which the weight of the digit place is multiplied to obtain the
weight of the digit place with the next higher weight; for example,
in the decimal numeration system, the radix of each digit place is
10. (2) Another term for base.
H-12

Glossary

radix numeration system: A positional representation system in
which the ratio of the weight of anyone digit place to the weight
of the digit place with the next lower weight is a positive integer.
The permissible values of the character in any digit place range
from zero to one less than the radix of the digit place.
RAS: Row address strobe.
RGBI: Red-green-blue-intensity.
read-only memory (ROM): A storage device whose contents
cannot be modified, except by a particular user, or when operating
under particular conditions; for example, a storage device in which
writing is prevented by a lockout.
read/write memory: A storage device whose contents can be
modified.
red-green-blue-intensity (RGBI): The description of a directdrive color monitor which accepts red, green, blue, and intensity
signal inputs.
register: (1) A storage device, having a specified storage
capacity such as a bit, a byte, or a computer word, and usually
intended for a special purpose. (2) On a calculator, a storage
device in which specific data is stored.
RF modulator: The device used to convert the composite video
signal to the antenna level input of a home TV.
ROM: Read-only memory.
ROM/BIOS: The ROM resident basic input/output system,
which provides the device level control of the major I/O devices in
the computer system.
row address strobe (RAS): A signal that latches the row
addresses in a memory chip.
RS-232C: The standard set by the EIA for communications
between computers and external equipment.
RTS: Request to send. Associated with modem control.
run: A single continuous performance of a computer program
or routine.
Glossary H-13

scan line: The use of a cathode beam to test the cathode ray tube
of a display used with a personal computer.
schematic: The description, usually in diagram form, of the
logical and physical structure of an entire data base according to a
conceptual model.
SDLC: Synchronous Data Link Control.
sector: That part of a track or band on a magnetic drum, a
magnetic disk, or a disk pack that can be accessed by the magnetic
heads in the course of a predetermined rotational displacement of
the particular device.
serdes: Serializer/deserializer.
serial: (1) Pertaining to the sequential performance of two or
more activities in a single device. In English, the modifiers serial
and parallel usually refer to devices, as opposed to sequential and
consecutive, which refer to processes. (2) Pertaining to the
sequential or consecutive occurrence of two or more related
activities in a single device or channel. (3) Pertaining to the
sequential processing of the individual parts of a whole, such as
the bits of a character or the characters of a word, using the same
facilities for successive parts. (4) Contrast with parallel.
sink: A device or circuit into which current drains.
software: (1) Computer programs, procedures, rules, and
possibly associated documentation concerned with the operation
of a data processing system. (2) Contrast with hardware.
source: The origin of a signal or electrical energy.
source circuit: (1) Generator circuit. (2) Control with sink.
SS: Start-stop transmission.
start bit: Synonym for start signal.
start-of-text character (STX): A transmission control character
that precedes a text and may be used to terminate the message
heading.

H-14

Glossary

start signal: (1) A signal to a receiving mechanism to get ready
to receive data or perform a function. (2) In a start-stop system, a
signal preceding a character or block that prepares the receiving
device for the reception of the code elements. Synonymous with
start bit.
start-stop (SS) transmission: Asynchronous transmission such
that a group of signals representing a character is preceded by a
start signal and followed by a stop signal. (2) Asynchronous
transmission in which a group of bits is preceded by a start bit that
prepares the receiving mechanism for the reception and
registration of a character and is followed by at least one stop bit
that enables the receiving mechanism to come to an idle condition
pending the reception of the next character.
stop bit: Synonym for stop signal.
stop signal: (1) A signal to a receiving mechanism to wait for the
next signal. (2) In a start-stop system, a signal following a
character or block that prepares the receiving device for the
reception of a subsequent character or block. Synonymous with
stop bit.
strobe: (1) An instrument used to determine the exact speed of
circular or cyclic movement. (2) A flashing signal displaying an
exact event.
STX: Start-of-text character.
Synchronous Data Link Control (SLDC): A protocol for the
management of data transfer over a data communications link.
synchronous transmission: Data transmission in which the
sending and receiving devices are operating continuously at the
same frequency and are maintained, by means of correction, in a
desired phase relationship.
text: In ASCII and data communication, a sequence of characters
treated as an entity if preceded and terminated by one STX and
one ETX transmission control, respectively.

Glossary

H-IS

track: (1) The path or one of the set of paths, parallel to the
reference edge on a data medium, associated with a single reading
or writing component as the data medium moves past the
component. (2) The portion of a moving data medium such as a
drum, tape, or disk, that is accessible to a given reading head
position.
transistor-transistor logic (TTL): A circuit in which the
multiple-diode cluster of the diode-transistor logic circuit has been
replaced by a multiple-emitter transistor.
TIL: Transistor-transistor logic.
TX Data: Transmit data. Associated with modem control.
External connections of the RS-232C asynchronous
communications adapter interface.
video: Computer data or graphics displayed on a cathode ray
tube, monitor or display.
write precompensation: The varying of the timing of the head
current from the outer tracks to the inner tracks of the diskette to
keep a constant write signal.

H-16

Glossary

BIBLIOGRAPHY

Intel Corporation. The 8086 Family User's Manual
This manual introduces the 8086 family of microcomputing
components and serves as a reference in system design and
implementation.
Intel Corporation. 8086/8087/8088 Macro Assembly Reference
Manualfor 8088/8085 Based Development System
This manual describes the 8086/8087/8088 Macro Assembly
Language, and is intended for use by persons who are familiar
with assembly language.
Intel Corporation. Component Data Catalog
This book describes Intel components and their technical
specifications.
Motorola, Inc. The Complete Microcomputer Data Library.
This book describes Motorola components and their technical
specificaitons.
National Semiconductor Corporation. INS 8250 Asynchronous
Communications Element. This book documents physical and
operating characteristics of the INS 8250.

Bibliography 1-1

Notes:

1-2 Bibliography

INDEX

A
A/N mode (alphanumeric mode) 1-123
AO-AI9 (Address Bits 0 to 19), I/O channel 1-15
adapter card with ROM 2-10
adapter,
asynchronous communication 1-215
binary synchronous communication 1-245
color/graphics monitor 1-123
diskette drive 1-151
fixed disk drive 1-179
game control 1-203
monochrome display and printer 1-115
printer 1-113
synchronous data link control 1-265
Address Bits 0 to 19 (AO-AI9), I/O channel 1-15
address bits (asynchronous communication) 1-217
Address Enable (AEN), I/O channel 1-18
Address Latch Enable (ALE), I/O channel 1-15
address map, I/O 1-8
AEN (Address Enable), I/O channel 1-18
ALE (Address Latch Enable), I/O channel 1-15
all points addressable mode 1-129, 1-123
alphanumeric mode, 1-128
high resolution 1-135
low resolution 1-132
alt (keyboard extended code) 2-15
AP A mode (all points addressable mode) 1-124
asynchronous communications adapter, 1-215
adapter address jumper module 1-242
address bits 1-217
block diagram 1-216
connector specifications 1-243
current loop interface 1-219
divisor latch least significant bit 1-229
divisor latch most significant bit 1-230
I/O decode 1-217
INS8250 functional pin description 1-221
INS8250 input signals 1-221
INS8250 input/output signals 1-225
Index

J-l

INS8250 output signals 1-224
interface descriptions 1-218
interface format jumper module 1-242
interrupt control functions 1-234
interrupt enable register 1-235
interrupt identification register 1-233
interrupts 1-218
line control register 1-227
line status register 1-231
modem control register 1-236
modem status register 1-238
modes of operation 1-216
programmable baud rate generator 1-229
programming considerations 1-226
receiver buffer register 1-240
reset functions 1-226
transmitter holding register 1-241
voltage interchange information 1-220
attributes, character
(see character attributes)

B
BASIC reserved interrupts 2-7
BASIC,
DEF SEG 2-8
reserved interrupt 2-7
screen editor keyboard functions 2-20
workspace variables 2-8
baud rate generator 1-231
bell (printer) 1-92
bibliography 1-1
binary synchronous communications adapter, 1-245
8252A programming procedures 1-257
8252A universal synchronous/asynchronous
receiver/transmitter 1-241
8253-5 programmable interval timer 1-251
8255A-5 programmable peripheral interface 1-251
block diagram 1-246
command instruction format 1-258
connector information 1-257
data bus buffer 1-247
interface signal information 1-260
interrupt information 1-262
mode instruction definition 1-257

J-2

Index

read/write control logic 1-247
receive 1-252
receiver buffer 1-249
receiver control 1-249
status read definition 1-259
transmit 1-251
transmitter buffer 1-248
transmitter control 1-249
typical programming sequence 1-253
BIOS,
fixed disk ROM A-84
memory map 2-9
parameter passing 2-3
software interrupt listing 2-4
system ROM A-2
use of 2-2
bisync communications
(see binary synchronous communications adapter)
block diagram
8252A universal synchronous/asynchronous
receiver/transmitter 1-246
8273 SDLC protocol controller 1-267
asynchronous communications adapter 1-215
color/graphics monitor adapter 1-125
coprocessor 1-25
diskette drive adapter 1-151
expansion board 1-71
extender card 1-74
fixed disk drive adapter 1-179
game control adapter 1-203
keyboard interface 1-67
monochrome display adapter 1-114
printer adapter 1-108
prototype card 1-118
receiver card 1-77
speaker drive system 1-20
synchronous data link control adapter 1-265
system 1-2
break (keyboard extended code) 2-14
BSC adapter
(see binary synchronous communications)

Index J-3

c
cable
communications adapter 1-285
expansion unit 1-171
printer 1-81
cancel (printer) 1-93
cancel ignore paper end (printer) 1-95
cancel skip perforation (printer) 1-99
caps lock (keyboard extended code) 2-16
card dimensions and specifications E-4
card selected 1-19
CARD SLCTD (card selected), I/O channel 1-19
card,
dimensions and specifications E-4
extender 1-74
prototype 1-209
receiver 1-77
carriage return (printer) 1-92
CCITT, F-l
standards F-l
character attributes
color/graphics monitor adapter 1-130
monochrome display adapter 1-130
character codes
keyboard 2-11
character set,
graphics printer (set 1) 1-10 3
graphics printer (set 2) 1-105
matrix printer 1-101
quick reference C-12
clear printer buffer (printer) 1-100
CLK (system clock), I/O channel 1-16
color display 1-149
operating characteristics 1-150
specifications E-2
color select register 1-141
color/graphics monitor adapter 1-123
6845 register description 1-136
alphanumeric mode 1-127
alphanumeric mode (high-resolution) 1-128
alphanumeric mode (low-resolution) 1-128
block diagram 1-126
character attributes 1-130
color-select register 1-141
composite connector specifications 1-146
J-4

Index

connector specifications 1-146
direct-drive connector specifications 1-146
display buffer basic operation 1-127
graphics mode 1-132
graphics mode (high resolution) 1-135
graphics mode (low resolution) 1-132
graphic mode (medium resolution) 1-133
light pen connector specifications 1-147
major components 1-126
memory requirements 1-145
mode control and status register 1-143
mode register summary 1-143
mode select register 1-141
programming considerations 1-137
RF modulator connector specifications 1-147
sequence of events 1-144
status register 1-143
summary of available color 1-135
colors, summary of available 1-137
command status register 0 1-164
command status register 1 1-165
command status register 2 1-166
command status register 3 1-167
command summary,
diskette drive adapter 1-151
fixed disk drive adapter 1-179
communications adapter cable 1-285
connector specifications 1-286
communications F-l
establishing a link F-3
component diagram,
system board 1-13
compressed (printer) 1-93
compressed off (printer) 1-93
connector specifications,
asynchronous communications adapter 1-215
binary synchronous communications 1-245
color/graphics monitor adapter 1-147
communications adapter cable 1-286
diskette drive adapter (external) 1-174
diskette drive adapter (internal) 1-1 73
game control adapter 1-203
keyboard interface 1-67
monochrome display adapter 1-115
printer adapter 1-81
synchronous data link control adapter 1-293

Index J-5

connectors,
power supply (system unit) 1-21
consideration, programming
(see programming considerations)
control byte, fixed disk drive adapter 1-186
control codes, printer 1-91
control/read/write logic 1-268
coprocessor,
(see math coprocessor)
ctrl (keyboard extended code) 2-13
current loop interface 1-219

D
DO-D7 (data bits 0 to 7), I/O channel 1-16
DACKO-DACK3 (DMA Acknowledge 0 to 3), I/O channel 1-18
Data Bits 0 to 7 (DO-D7), I/O channel 1-16
data flow,
system board 1-6
data register 1-185
data transfer mode register 1-282
DEF SEG (default segment workspace) 2-8
default workspace segment (DEF SEG) 2-8
diagram, block (see block diagram)
digital output register 1-153
diskette drive adapter 1-151
adapter input 1-1 71
adapter output 1-170
block diagram 1-152
command status register 0 1-164
command status register 1 1-165
command status register 2 1-166
command status register 3 1-167
command summary 1-158
connector specifications (external) 1-174
connector specifications (internal) 1-173
digital-output register 1-153
DPC registers 1-167
drive A and B interface 1-170
drive constants 1-168
FDC constants 1-168
floppy disk controller 1-154
functional description 1-153
programming considerations 1-156
programming summary 1-167
symbol descriptions 1-156
system I/O channel interface 1-168
J-6

Index

diskette drive, 1-175
electrical specifications 1-176
mechanical specifications 1-176
switch settings G-l
diskettes 1-177
display adapter type switch settings G-l
display,
color 1-149
monochrome 1-121
divisor latch,
least significant bit 1-229
most significant bit 1-230
DMA Acknowledge 0 to 3 (DACKO-DACK3),
I/O channel 1-18
DMA Request 1 to 3 (DRQI-DRQ3), I/O channel 1-18
DOS reserved interrupts 2-7
DOS,
keyboard functions 2-20
reserved interrupts 2-7
double strike (printer) 1-96
double strike off (printer) 1-96
double width (printer) 1-93
double width off (printer) 1-93
DPC registers 1-167
DRQI-DRQ3 (DMA Request 1 to 3), I/O channel 1-18

E
EIA, F-l
standards F-l
emphasized (printer) 1-96
emphasized off (printer) 1-96
escape (printer) 1-93
establishing a communications link F-3
expansion board, 1-71
block diagram 1-72
expansion channel 1-73
expansion unit, 1-71
cable 1-71
expansion board 1-71
expansion channel 1-73
extender card 1-74
interface information 1-79
power supply 1-71
receiver card 1-77
specifications E-2
Index

J-7

extender card, 1-74
block diagram 1-76
programming considerations 1-75
switch settings G-l

F
FABS (coprocessor) 1-36
F ADD (coprocessor) 1-36
FBLD (coprocessor) 1-37
FBSTP (coprocessor) 1-37
FCHS (coprocessor) 1-38
FCLEX/FNCLEX (coprocessor) 1-38
FCOM (coprocessor) 1-38
FCOMP (coprocessor) 1-39
FCOMPP (coprocessor) 1-39
FDECSTP (coprocessor) 1-40
FDISI/FNDISI (coprocessor) 1-40
FDIV (coprocessor) 1-41
FDIVR (coprocessor) 1-42
FENI/FNENI (coprocessor) 1-43
FFREE (coprocessor) 1-43
FICOM (coprocessor) 1-43
FICOMP (coprocessor) 1-44
FILD (coprocessor) 1-44
FINCSTP (coprocessor) 1-44
FINIT/FNINIT (coprocessor) 1-45
FIST (coprocessor) 1-46
FISTP (coprocessor) 1-46
fixed disk controller 1-179
fixed disk drive 1-195
fixed disk drive adapter 1-179
block diagram 1-180
command summary 1-187
control byte 1-186
data register 1-185
fixed disk controller 1-179
interface specifications 1-193
programming considerations 1-181
programming summary 1-191
ROM BIOS listing A-84
sense bytes 1-181
status register 1-181
system I/O channel interface 1-192

J-8

Index

fixed disk drive, 1-195
electrical specifications 1-196
mechanical specifications 1-196
fixed disk ROM BIOS A-84
FLD (coprocessor) 1-47
FLDCW (coprocessor) 1-47
FLDENV (coprocessor) 1-48
FLDLG2 (coprocessor) 1-48
FLDLN2 (coprocessor) 1-48
FLDL2E (coprocessor) 1-49
FLDL2T (coprocessor) 1-49
FLDPI (coprocessor) 1-49
FLDZ (coprocessor) 1-50
FLDI (coprocessor) 1-50
floppy disk controller 1-154
form feed (printer) 1-92
FMVL 1-51
FNOP 1-52
FPATAN 1-52
FPREM 1-52
FPTAN 1-53
FRNDINT 1-53
FRSTOR 1-53
FSAVE/FNSAVE (coprocessor) 1-54
FSCALE (coprocessor) 1-54
FSQRT (coprocessor) 1-55
FST (coprocessor) 1-55
FSTCW/FNSTCW (coprocessor) 1-56
FSTENV/FNSTENV (coprocessor) 1-56
FSTP (coprocessor) 1-57
FSTSW/FNSTSW (coprocessor) 1-57
FS VB ( coprocessor) 1-58
FSVBR (coprocessor) 1-59
FTST (coprocessor) 1-60
FWAIT (coprocessor) 1-60
FXAM (coprocessor) 1-61
FXCH (coprocessor) 1-62
FXTRACT (coprocessor) 1-62
FYL2X (coprocessor) 1-63
FYL2XPI (coprocessor) 1-63
F2XMl (coprocessor) 1-64

Index J-9

G
game control adapter, 1-203
block diagram 1-203
connector specifications 1-208
functional description 1-204
I/O channel description 1-205
interface description 1-206
joy stick schematic diagram 1-207
glossary, H-l
graphics mode, 1-123
high resolution 1-124
low resolution 1-123
medium resolution 1-124

H
hardware interrupt listing 1-9
home head (printer) 1-95
horizontal tab (printer) 1-92

I
I/O address map 1-8
I/O bit map, 8255A 1-10
I/O CH CK (I/O Channel Check), I/O channel 1-17
I/O CH RDY (I/O Channel Ready), I/O channel 1-17
I/O Channel Check (I/O CH CK), I/O channel 1-17
I/O channel interface,
diskette drive adapter 1-168
fixed disk drive adapter 1-192
prototype card 1-211
I/O Channel Ready (I/O CH RDY), I/O channel 1-17
I/O channel, 1-14
-I/O Channel Check (I/O CH CK) 1-17
-I/O Read Command (lOR) 1-17
-I/O Write Command (lOW) 1-17
Address Bits 0 to 19 (AO-A19) 1-16
Address Enable (AEN) 1-18
Address Latch Enable (ALE) 1-16
Data Bits 0 to 7 (DO-D7) 1-16
description 1-16
diagram 1-15
DMA Request 1 to 3 (DRQI-DRQ3) 1-18
I/O Channel Ready (I/O CH RDY) 1-17
J-I0

Index

Interrupt Request 2 to 7 (lRQ2-IRQ7) 1-17
Memory Read Command (MEMR) 1-18
Memory Write Command (MEMW) 1-18
Oscillator (OSC) 1-16
Reset Drive (RESET DRV) 1-16
System Clock (CLK) 1-16
Terminal Count (T/C) 1-18
I/O Read Command (lOR), I/O channel 1-17
I/O Write Command (lOW), I/O channel 1-17
IBM 10MB Fixed Disk Drive 1-195
IBM 5-1/4" Diskette Drive 1-175
IBM 5-1/4" Diskette Drive Adapter 1-151
IBM 80 CPS Graphics Printer 1-81
IBM 80 CPS Matrix Printer 1-81
IBM 80 CPS Printers 1-81
IBM Asynchronous Communications Adapter 1-215
IBM Binary Synchronous Communications Adapter 1-245
IBM Color Display 1-149
IBM Color/Graphics Monitor Adapter 1-123
IBM Communicatons Adapter Cable 1-295
IBM Fixed Disk Drive Adapter 1-179
IBM Game Control Adapter 1-203
IBM Memory Expansion Options 1-197
IBM Monochrome Display and Printer Adapter 1-113
IBM Monochrome Display 1-121
IBM Personal Computer Math Coprocessor 1-25
IBM Printer Adapter 1-107
IBM Prototype Card 1-209
IBM Synchronous Data Link Controller Adapter 1-265
ignore paper end (printer) 1-94
INS8250,
(see National Semiconductor INS8250)
Intel 8088 microprocessor,
arithmetic B-7
conditional transfer operations B-14
control transfer B-l1
data transfer B-5
hardware interrupt listing 1-8
instruction set index B-18
instruction set matrix B-16
logic B-9
memory segmentation model B-4
operand summary B-3
processor control B-14
register model B-2

Index J-ll

second instruction byte summary B-3
segment override prefix B-4
software interrupt listing 2-4
string manipulation B-ll
use of segment override B-4
Intel 8253-5 Programmable Interval Timer
(see synchronous data link control communications adapter)
Intel 8255A Programmable Peripheral Interface
I/O bit map 1-10
Intel 8255A-5 Programmable Peripheral Interface
(see synchronous data link control communications adapter)
Intel 8273 SDLC Protocol Controller
(see synchronous data link control communications adapter)
block diagram 1-265
interrupt enable register 1-235
interrupt identification register 1-233
interrupt listing,
8088 hardware 1-9
8088 software 2-4
Interrupt Request 2 to 7 (IRQ2-IRQ7), I/O channel 1-17
interrupts,
8088 hardware 1-9
8088 software 2-4
asynchronous communications adapter 1-215
BASIC reserved 2-7
DOS reserved 2-7
special 2-5
lOR (I/O Read Command), I/O channel 1-17
lOW (I/O Write Command), I/O channel 1-17
IRQ2-IRQ7 (Interrupt Request 2 to 7), I/O channel 1-17

J
joy stick,
positions 1-204
schematic diagram 1-207
jumper module, asynchronous communications adapter 1-242

K
keyboard extended codes,
alt 2-15
break 2-16
caps lock 2-16
ctrl 2-15
J-12

Index

pause 2-17
print screen 2-17
scroll lock 2-16
shift 2-15
shift key priorities 2-16
shift states 2-15
system reset 2-16
keyboard 1-65
BASIC screen editor special functions 2-20
character codes 2-11
commonly used functions 2-18
diagram 1-68
DOS special functions 2-20
encoding 2-11
extended functions 2-14
interface block diagram 1-70
interface connector specifications 1-70
scan codes 1-69
specifications E-l

L
light pen connector specifications 1-147
line control register 1-227
line feed (printer) 1-92
line status register 1-223
logic diagrams D-l

M
math coprocessor 1-25
block diagram 1-29
control unit 1-29
control word 1-32
data types 1-26
exception pointers 1-33
FABS 1-36
FADD 1-36
FBLD 1-37
FBSTP 1-37
FCHS 1-38
FCLEX/FNCLEX 1-38
FCOM 1-38
FCOMP 1-39
FCOMPP 1-39
FDECSTP 1-40
Index J-13

FDISIjFNDISI 1-40
FDIV 1-41
FDIVR 1-42
FENI/FNENI 1-43
FFREE 1-43
FICOM 1-43
FICOMP 1-44
FILD 1-44
FINCSTP 1-44
FINIT/FNINIT 1-45
FIST 1-46
FISTP 1-46
FLD 1-47
FLDCW 1-47
FLDENV 1-48
FLDLG2 1-48
FLDLN2 1-48
FLDL2E 1-49
FLDL2T 1-49
FLDPI 1-49
FLDZ 1-50
FLDI 1-50
FMUL 1-51
FNOP 1-52
FPATAN 1-52
FPREM 1-52
FPTAN 1-53
FRNDINT 1-53
FRSTOR 1-53
FSAVE/FNSAVE 1-54
FSCALE 1-54
FSQRT 1-55
FST 1-55
FSTCW/FNSTCW 1-56
FSTENV/FNSTENV 1-56
FSTP 1-57
FSTSW/FNSTSW 1-57
FSUB 1-58
FSUBR 1-59
FTST 1-60
FWAIT 1-60
FXAM 1-61
FXCH 1-62
FXTRACT 1-62
FYL2X 1-63
FYL2XPI 1-63
F2XMl 1-64
J-14

Index

hardware interface 1-27
instruction set 1-35
interconnection 1-28
number system 1-34
programming interface 1-26
register stack 1-30
status word 1-31
tag word 1-33
memory expansion options, 1-197
DIP module start address 1-201
memory module description 1-198
memory module pin configuration 1-199
memory option switch settings G-l
R/W memory operating characteristics 1-198
switch-configurable start address 1-200
memory locations,
reserved 2-8
memory map,
BIOS 2-9
system 1-11
Memory Read Command (MEMR), I/O channel 1-18
memory switch settings, G-l
extender card G-1
memory options G-l
system board G-1
Memory Write Command (MEMW), I/O channel 1-18
(MEMR) Memory Read Command, I/O channel 1-18
(MEMW) Memory Write Command, I/O channel 1-18
microprocessor (see Intel 8088 microprocessor)
mode control and status register 1-139
mode select register 1-141
modem control register 1-236
modem status register 1-238
monochrome display 1-121
monochrome display and printer adapter 1-113
monochrome display adapter 1-115
6845 CRT control port 1-118
6845 CRT status port 1-118
block diagram 1-114
character attributes 1-117
connector specifications 1-119
I/O address and bit map 1-117
programming considerations 1-115
monochrome display, 1-121
operating characteristics 1-122
specifications E-3
Index J-15

Motorola 6845 CRT Controller,
(see color/graphics monitor adapter)
(see monochrome display adapter)

N
National Semiconductor INS8250 Asynchronous
(see asynchronous communications adapter)
functional pin description 1-221
input signals 1-221
input/output signals 1-225
output signals 1-224
null (printer) 1-92

o
one bit delay mode register 1-283
operating mode register 1-280
OSC (oscillator) 1-16
Oscillator (OSC), I/O channel 1-16

p
parameter passing (ROM BIOS) 2-3
pause (keyboard extended code) 2-17
power good signal 1-24
power supply 1-21
connectors 1-23
input requirements 1-22
over-voltage/current protection 1-24
pin assignments 1-23
power good signal 1-24
Vac output 1-22
Vdc output 1-22
print screen (keyboard extended code) 2-17
printer adapter, 1-107
block diagram 1-108
connector specifications 1-111
programming considerations 1-109
printer control codes, 1-91
1I8-inch line feeding 1-94
1920 bit-image graphics mode 1-10 1
480 bit-image graphics mode 1-97
7/72-inch line feeding 1-94
960 bit-image graphics mode 1-99
J-16

Index

960 bit-image graphics mode normal speed 1-100
bell 1-92
cancel 1-93
cancel ignore paper end 1-95
cancel skip perforation 1-99
carriage return 1-92
clear printer buffer 1-100
compressed 1-93
compressed off 1-93
double strike 1-96
double strike off 1-97
double width 1-99, 1-93
double width off 1-93
emphasized 1-96
emphasized off 1-96
escape 1-93
form feed 1-92
home head 1-91
horizontal tab 1-92
ignore paper end 1-94
line feed 1-92
null 1-92
printer deselected 1-93
printer selected 1-93
select character set 1 1-94
select character set 2 1-94
set horizontal tab stops 1-96
set lines per page 1-96
set skip perforation 1-99
set variable line feeding 1-97
set vertical tabs 1-95
starts variable line feeding 1-94
subscript/superscript 1-99
subscript/ superscript off 1-99
underline 1-94
unidirectional printing 1-99
vertical tab 1-92
printer deselected (printer) 1-93
printer selected (printer) 1-93
printer, 1-81
additional specifications 1-83
cable 1-81
connector pin assignment 1-87
control codes 1-91
graphic character set 1 1-103
graphic character set 2 1-105
interface signal descriptions 1-87
Index J-17

matrix character set 1-101
modes 1-90
parallel interface 1-86
parallel interface timing diagram 1-86
specifications 1-82, E-3
switch locations 1-84
switch settings 1-84
processor (see Intel 8088 micrprocessor)
programmable baud rate generator 1-229
programming considerations,
asynchronous communications adapter 1-226
binary synchronous communications adapter 1-253
color/graphics monitor adapter 1-137
diskette drive adapter 1-151
extender card 1-74
fixed disk drive adapter 1-179
monochrome display adapter 1-115
printer adapter 1-109
receiver card 1-77
SDLC adapter 1-275
prototype card, 1-209
block diagram 1-210
external interface 1-213
I/O channel interface 1-211
layout 1-211
system loading and power limitations 1-213

Q
quick reference, character set C-12

R
receiver buffer register 1-249
receiver card, 1-77
block diagram 1-78
programming considerations 1-77

J-18

Index

register,
6845 description ( color/graphic adapter) 1-13 9
color select (color/ graphic adapter) 1-140
command status 0 (diskette drive adapter) 1-167
command status 1 (diskette drive adapter) 1-168
command status 2 (diskette drive adapter) 1-169
command status 3 (diskette drive adapter) 1-170
data (fixed disk drive adapter) 1-185
data transfer mode (SDLC) 1-272
digital output (diskette drive adapter) 1-153
DPC (diskette drive adapter) 1-167
interrupt enable (asynchronous communications) 1-235
interrupt identification (asynchronous communications) 1-235
line control (asynchronous communications) 1-227
line status (asynchronous communications) 1-231
mode control and status (color/graphics) 1-139
mode select ( color/graphics) 1-141
modem control (asynchronous communications) 1-236
modem status (asynchronous communications) 1-238
one-bit delay mode (SDLC) 1-283
operating mode (SDLC) 1-280
receiver buffer (asynchronous communications) 1-240
serial I/O mode (SDLC) 1-282
status ( color/graphics) 1-143
status (fixed disk drive adapter) 1-181
transmitter holding (asynchronous communications) 1-241
reserved interrupts,
BASIC and DOS 2-7
reserved memory locations 2-7
Reset Drive (RESET DRV), I/O channel 1-16
RESET DRV (Reset Drive), I/O channel 1-16
RF modulator connector specifications 1-147
ROM BIOS, 2-2
Fixed Disk A-84
System A-2
ROM, adapter cards with 2-10
RS-232C,
interface standards F-2

Index

J-19

s
scan codes,
keyboard 1-65
scroll lock (keyboard extended code) 2-14
SDLC (see synchronous data link control)
select character set 1 (printer) 1-94
select character set 2 (printer) 1-94
sense bytes, fixed disk drive adapter 1-181
serial I/O mode register 1-282
set horizontal tab stops (printer) 1-96
set lines per page (printer) 1-96
set skip perforation (printer) 1-99
set variable line feeding (printer) 1-95, 1-97
set vertical tabs (printer) 1-95
shift (keyboard extended code) 2-13
shift key priorities (keyboard code) 2-14
shift states (keyboard extended code) 2-13
software interrupt listing 2-4
speaker connector 1-20
speaker drive system 1-20
speaker interface 1-20
specifications,
80 CPS printers E-3
color display E-2
expansion unit E-2
keyboard E-1
monochrome display E-3
printer 1-82
printer (additional) 1-83
system unit E-1
stack area 2-7
starts variable line feeding (printer) 1-94
status register, 1-137
color/graphics monitor adapter 1-143
fixed disk drive adapter 1-181
synchronous data link control adapter 1-276
subscript/ superscript (printer) 1-99
subscript/ superscript off (printer) 1-99
switch settings, G-l
diskette drive G-1
display adapter type G-l
extender card G-1
memory options G-1
printer 1-84

J-20

Index

system board G-l
system board memory G-l
synchronous data link control communications adapter, 1-265
8253-5 interval timer control word 1-279
8253-5 progammable interval timer 1-275
8255A-5 port A assignments 1-274
8255A-5 port B assignments 1-274
8255A-5 port C assignments 1-275
8255A-5 programmable peripheral interface 1-274
8273 command phase flow chart 1-286
8273 commands 1-285
8273 control/read/write registers 1-269
8273 data interfaces 1-270
8273 elements of data transfer interface 1-270
8273 mode register commands 1-283
8273 modem control block 1-271
8273 modem control port A 1-271
8273 modem control port B 1-272
8273 modem interface 1-271
8273 protocol controller operations 1-266
8273 protocol controller structure 1-267
8273 register selection 1-268
8273 SDLC protocol controller block diagram 1-257
8273 transmit/receiver timing 1-283
block diagram 1-265
command phase 1-284
connector specifications 1-293
control/read/write logic 1-268
data transfer mode register 1-282
device addresses 1-291
execution phase 1-287
general receive 1-288
initialization/configuration commands 1-280
initializing the SDLC adapter 1-278
interface information 1-292
interrupt information 1-291
one bit delay code register 1-283
operating mode register 1-290
partial byte received codes 1-290
processor interface 1-268
programming considerations 1-275
protocol control module features 1-266
protocol controller operations 1-266
result code summary 1-290
result phase 1-287

Index J-21

selective receive 1-289
serial data timing block 1-273
serial I/O mode register 1-282
status register format 1-276
transmit 1-288
system block diagram 1-2
system board, 1-3
component diagram 1-13
data flow 1-6
R/W memory operating characteristics 1-198
switch settings G-l
System Clock (CLK), I/O channel 1-16
system memory map 1-12
system reset (keyboard extended code) 2-16
system ROM BIOS A-2
system unit, 1-3
I/O channel 1-14
I/O channel diagram 1-15
keyboard interface 1-67
power supply 1-21
speaker interface 1-20
specifications E-l
system board 1-3

T
T/C (Terminal Count), I/O channel 1-19
transmitter holding register 1-241

u
underline (printer) 1-94
unidirectional printer (printer) 1-99

J-22

Index

v
Vac output,
system unit 1-22
Vdc output,
system unit 1-22
vectors with special meanings 2-5
vertical tab (printer) 1-92
voltage interchange,
asynchronous communications adapter 1-215

Numerics
1/8 inch line feeding (printer) 1-94
1920 bit-image graphics mode (printer) 1-100
480 bit-image graphics mode (printer) 1-97
6845,
(see color/graphics monitor adapter)
(see monochrome display adapter)
7/72 inch line feeding (printer) 1-94
8088,
(see Intel 8088 microprocessor) 1-4
8250,
(see asynchronous communications adapter)
8253-5,
(see synchronous data link control adapter)
8255A 1-10
8255A-5,
(see synchronous data link control adapter)
8273,
(see synchronous data link control adapter)
960 bit-image graphics mode (printer) 1-99
960 bit-image graphics mode normal speed (printer) 1-100

Index J-23

Notes:

J-24

Index

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continue to use the information you supply.
Please do not use this form for technical questions
regarding the IBM Personal Computer or programs for
the IBM Personal Computer, or for requests for
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