TM990/100M Users Guide Mar80 1602001 9701_TM990_100M_Users_Guide_Mar80 9701 TM990 100M

User Manual: 1602001-9701_TM990_100M_Users_Guide_Mar80

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The Engineering Staff of

~ .0 Di•~""'...

TEXAS INSTRUMENTS INCORPORATED
Semiconductor Group

-.

'

I\

TM 990/101M
MICROCOMPUTER
USER'S
GUIDE

MARCH 1980

TEXAS INSTRUMENTS
IN C ORPORATED

o

This manual contains the following revisions:
Date
02/ 18/80

Revision Change
(From - to)
C to D

ECN Number
454310

•

IMPORTANT NOTICES
Texas Instruments reserves the right to make changes at any time
in order to improve design and to supply the best product possible.
TI cannot assume any responsibility for any circuits shown or
represent that tbey are free from patent infringement.

Copyright© 1980

TEXAS INSTRUMENTS INCORPORATED
•

TABLE OF CONTENTS

TITLE

SECTION
1.

2.

3.

PAGE

INTRODUCTION
1.1
General . . . . . .
1.2
Manual Organization
1.3
Product Index . . .
1.4
Board Characteristics
1.5
General Specifications
1.6
Reference Documents .
1.7
Glossary . . . . . . .

1-1
1-4
1-4
1-5
1-5
1-6
1-6

INSTALLATION AND OPERATION OF TM990/101M-1
2.1
General . • . . . .
2 .2
Required Equipment . . . .
2.2 .1 Power Supply . . . .
2.2.2 Terminals and Cables
2.2.3 Power Cable/Chassis
2.2.4 Parallel I/O Connector
2.2.5 Miscellaneous Equipment
Unpacking . . . . . . . . . . .
2. 3
2.4
Power and Terminal Hookup . . .
2.4.1 Power Supply Connections
2 . 4.2 Terminal Hookup . . . . .
2.4.3 Five-Switch DIP and Status LED .
2.5
Operation . . . . . .
2.5.1 Verification . •
2.5.2 Power-Up/Reset
2.6
Sample Programs . . .
2.6.1 Sample Program 1
2.6.2 Sample Program 2
2.7
Debug Checklist .
TIBUG INTERACTIVE DEBUG MONITOR
3.1
General
.
. .. .
3.2
TIBUG Commands . . . . .
3.2.1 Execute Under Breakpoint (B)
3.2.2 CRU Inspect/Change (C) .
3.2.3 Dump Memory to Cassette/Paper Tape
3.2.4 Execute Command (E) . . . .
3.2.5 Find Command (F) .
. .. .
3.2.6 Hexadecimal Arithmetic (H) •
3.2.7 Load Memory from Cassette or Paper
3.2.8 Memory Inspect/Change, Memory Dump
3.2.9 Inspect/Change User WP, PC, and ST
3.2.10 Execute in Single Setp Mode (S)
3.2. 11 TI 733 ASR Baud Rate (T) . . . . .
3.2.12 Inspect/Change User Workspace (W)

iii

2-1
2-1
2-1
2-1
2-2
2- 2
2-2

2-2
2- 2
2- 3
2- 5
2-8
2-8
2-8
2-8
2- 8
2-8
2-10
2-10

(D)

Tape (L)
(M) . . .
Registers (R)

3- 1
3-1
3-3
3-4
3-5
3-8
3- 8
3-9
3-9
3-10
3-11
3-12
3-13
3-1 3

TABLE OF CONTENTS (Continued)
SECTION

TITLE
3.3

3.4

4.

5.

User Accessible Utilities .
. .....•...... .
3.3.1 Write One Hexadecimal Character to Terminal (XOP 8)
3.3.2 Read Hexadecimal Word from Terminal (XOP 9)
3.3.3 Write Four Hexadecimal Characters to Terminal (XOP 10).
3.3.4 Echo Character (XOP 11) . . . . . . . . .
3.3.5 Write One Character to Terminal (XOP 12)
3.3.6 Read One Character from Terminal (XOP 13)
3.3.7 Write MEssage to Terminal (XOP 14) . .
TIBUG Error Message . . . . . . • . • . . .

TM990/101M INSTRUCTION EXECUTION
4.1
General . . . . . .
4.2
User Memory . . . . .
4 .3
Hardware Registers
4.3.1 Program Counter (PC)
4.3.2 Workspace Pointer (WP)
4.3.3 Status register (ST)
4.4
Software Registers . . . . . . . . .
4.5
Instruction Formats and Addressing Modes
4.5.1 Direct Register Addressing (T=00 2 ) . .
4.5.2 Indirect Register Addressing (T=01 2 ). .
4.5.3 Indirect Register Autoincrement Addressing (T=11 2 ).
4.5.4 Symbolic Memory Addressing, Indexed (T=10 2 ) . . . .
4.5 .5 Symbolic Memory Addressing, Indexed (T=10 2 )
4.5.6 Immediate Addressing . . . . . . .
4.5.7 Program Counter Relative Addressing
4.6
Instructions . . . . . . .
4 .6 .1 Format 1 Instructions .
4.6.2 Format 2 Instructions . •
4.6.3 Format 3/9 Instructions •
4.6.4 Format 4 (CRU Multibit) Instructions
4.6.5 Format 5 (Shift) Instructions . . . .
4.6.6 Format 6 Instructions . . . . . . . .
4.6.7 Format 7 (RTWP, Control) Instructions
4.6.8 Format 8 (Immediate, Internal Register
Load/Store) Instructions
4. 6.9 Format 9 (XOP) Instructions . . • . . .
PROGRAMMING
5.1
General . . . . . . . • . .
5.2
Programming Considerations
5.2.1 Program Organization
5.2.2 Executing TM990/100M Programs on the TM990/101M
5.2.3 Required Use of RAM in Programs .
5.3
Programming Environment .
5.3.1 Hardware Registers • • • .
5.3.2 Address Space
.....
5.3.3 Vectors (Interrupt and XOP)
5.3.4 Workspace Registers .
iv

PAG~

3-14
3- 15
3-15
3-16
3-17
3-17
3-17
3-17
3-18
4-1
4-1
4-1
4-1
4-2
4-2

4-4
4-7
4-8
4-8
4-11
4-1
4-1.

4-13
4-13

4-14
4-18
4-20
4-22
4-24
4-25
4-27
4-29
4-31
4-33
5-1
5-3
5-3
5-3
5-3
5-4
5-4
5-5
5-5
5-6

TABLE OF CONTENTS (Continued)
SECTION

TITLE
5.4

6.

.

,

PAGE

Linking Instructions . . • . .
5.4.1 Branch Instruction (B)
5.4.2 Branch and Link (BL). .
• .
5.4.3 Branch and Load Workspace Pointer (BLWP).
5 . 4. 4 Return with Workspace Pointer (RTWP).
5.4.5 Extended Operation (XOP) . .
5.4.6 Linked-Lists . . • . . . . .
Communications Register Unit (CRU)
5.5
5.5.1 CRU Addressing
5.5.2 CRU Timing . . . . .
5 .5 . 3 CRU Instructions
5 .6
Dynamically Relocatable Code
5.7
Programming Hints
. • . .
5.8
Interfacing with TIBUG . . .
5.8.1 Program Entry and Exit
5.8.2 I/O Using Monitor XOP's
5.9
Interrupts and XOPs . . . . . . .
5.9.1 Interrupt and XOP Linking Areas
5 .9. 2 TMS 9901 Interval Timer Interrupt Program
5.9 . 3 Example of Programming Timer Interrupts for
TMS 9901 and TMS 9902 • . . . .
5. 10 Move Block Following Passing of Parameters
5. 11 Block Compare Subrouti ne •
5. 12 Unit ID DIP-Switch . . •
5.13 CRU Addressable LED
5. 14 Using Main and Auxiliary TMS 9902's for I/0

5- 32
5- 50
5- 51
5- 52
5-52
5- 52

THEORY OF OPERATION
6 .1
General
.. .•
6.2
Power Specifications
6.3
System Structure
6.4
System Buses . . .
6 .4.1 Address Bus
6.4 . 2 Data Bus . •
6.4.3 CRU Bus
6.4.4 Control Bus .
6.5
System Clock . . .
6.6
Central Processing Unit
6.7
Reset/Load Logic .
6 . 7.1 Reset Function
6.7.2 Load Function .
6.7 . 3 Reset and Load Filtering
6 .7.4 CLRCRU Signal .
6 .8
External Instructions . . . .
6.9
Address Decoding . . . . . . .
6.9 .1 Memory Address Decoding
6.9.2 CRU Select . . . . . .

6-1
6-1
6- 4
6-4
6-4
6-4
6-4
6- 6
6-7
6- 8
6- 10
6-1 0
6-13
6-14
6-14
6-1 4
6-1 5
6-1 5
6-1 9

v

5-6
5-6
5-7
5-8
5-9
5-9
5-10
5-10
5-13
5-14
5-14
5-19
5-21
5-21
5- 21
5-22
5-24
5-24
5-30

TABLE OF CONTENTS (Continued)
SECTION

TITLE
6. 10

6. 11
6. 12
6.13

6. 14
6. 15
6. 16

6. 17
6. 18
6. 19
1.

Memory Timing Signals .
6. 10. 1 Ready
6. 10. 2 Wait .
6 . 10 . 3 MEMCYC
Read-Only Memory
Random-Access Memory
Buffer Control . . • •
6.13.1 Address and Data Buffers . .
6.13.2 Control Buffers
6.13.3 HOLD, HOLDA, and OMA.
Interrupt Structure . . . . .
Parallel I/O and System Timer • .
6. 15. 1 Parallel I/O . . .
6. 15.2 System Timer • . . .
Main Communications Port
6.16.1 EIA Interface
6.16.? TTY Interface • . • •
6.16.3 Multidrop Interface
Auxiliary Communications Port
Unit ID Switch
Status Indicator

OPTIONS
7. 1 General . . . . . . . . . •
7.2
On-Board Memory Expansion . .
7.2.1 EPROM Expansion
1. 2.2 RAM Expansion
Slow EPROM . . . . . . .
1.3
7.4
Serial Communication Interrupt
7.5
RS-232-C/TTY/Multidrop Interfaces (Main Port, P2) .
7.5.1 TTY Interface
7.5.2 RS-232-C Interface .
7.5.3 Multidrop Interface.
7.6
External System Reset/Load.
Remote Communications .
7.7
7.8
Memory Map Change . • • . .
1.9 TM 990/402 Line-by-Line Assembler
7. 10 TM 990/301 Microterminal
7. 11 OEM Chassis . . . . . . . . . . .

vi

PAGE.
6-26
6-26
6-27
6-27
6-27
6-28
6-28
6-30
6-30
6-31
6-31
6-32
6-34
6-34
6-35
6-35
6-36
6-37
6-38
6-39
6-39
7-1
7-1
7-1
7-6
7-7
1-1

1-1
7-7
1-1

7-8
7-1 2
7-12
7-12
7-12
7-12
7-13

TABLE OF CONTENTS (Continued)
TITLE

SECTION

8.

APPLICATIONS
8.1
General
8.2
Off-Board RAM
8.3
Off-Board TMS 9901.
8.4
Off-Board Eight-Bit I/O Port .
8.5
Extra RS-232-C Terminal Port.
8 .6
Direct Memory Access (DMA) Applicati ons
8.6.1 DMA System Timing . . .
8.6.2 Memory Cycle Timing . .
8.6.3 DMA System Guidelines. . .
.
8.6.4 Multiple-Device Direct Memory Access Controller
8.7
EIA Serial Port Applications.
8.7.1 Cable Pin Assignments.
8.7.2 Modem (Data Set) Interface Signal Definitions.

APPENDICES
A
B
C
D
E
F
G
H
I
J
K

WIRING TELETYPE MODEL 3320/5JE FOR TM 990/101M
EIA RS- 232-C CABLING
ASCII CODE
BINARY, DECIMAL, AND HEXADECIMAL NUMBERING
PARTS LIST
SCHEMA TI CS
990 OBJECT CODE FORMAT
CHASSIS INTERFACE CONNECTOR (P1) SIGNAL ASSIGNMENTS
TM 990/301 MICROTERMINAL
CRU INSTRUCTION AND ADDRESSING EXAMPLES USING TMS 9901
EXAMPLE PROGRAMS

INDEX

vii/viii

PAGE
8- 1
8-1
8-1
8-1
8- 6
8-7
8-7
8-11
8-11
8-12
8-17
8-17
8-19

LIST OF ILLUSTRATIONS
FIGURE

TITLE

PAGE

1-1
1-2
1- 3

TM 990 / 101M Major Components . . . . . . . . . •
TM 990/101M Dimensions and Component Placement
Main and Expansion EPROM and RAM

1-2
1-3
1-5

2-1
2- 2
2-3
2-4
2-5

Power Supply Hookup . . . .
TM 990/101M Board In TM 990/510 Chassis
74 3 KSR Terminal Hookup . . . . . . . .
Connector P2 Connected to RS-232- Device (Model 733 ASR)
Connector P2 Connected to TTY Device

2-4
2- 5
2- 6
2- 6

3-1
3-2
3-3

Memory Requirements For TIBUG
CRU Bits Inspected By C Command
Tape Tabs

3- 2
3-4

4-1
4-2
4-3
4-4
4-5
4-6
4-7

Memory Map
Status Register
Workspace Example
TM 990/101M Instruction Formats
Direct Register Addressing Example
Indirect Register Addressing Example
Indirect Register Autoincrement Addressing Example
Direct Memory Addressing Example . . . . .
Direct Memory Addressing, Indexed Example
BLWP Example
. . . .
XOP Example

4-2
4- 3
4-6
4-7
4-9
4- 10
4-1 0
4-1 2
4-1 3
4- 30
4- 35

Sour ce Listing
Example of Separate Programs Joined By Branches
t o Absolute Addresses . . . . .
. . . .
Linked List Example . . . .
CRU Address In Regi s ter 12 vs. Addres s Bus Li nes
TMS 9900 CRU Interface Timing
LDCR I nstruction . . . .
STCR Instruction . . . . . . . .
Addition of Displacement and R12 Contents
to Drive CRU Bit Address .
Example of Program With Coding Added to Make
it Relocatable . . . . . . . .
Examples of Non Self-Relocating Code and
Self-Relocating Code . . .
Interrupt Sequence
. . . . . .
Six-Word Interrupt Linking Area
Seven-Word XOP Interrupt Linking Area

5- 2

4-8
4-9
4-10
4-11
5-1
5-2

5- 3
5-4
5-5
5-6
5-7
5-8
5-9

5-10
5-11
5-12
5-13

ix

2-1

3- 1

5- 7
5- 11
5- 13
5-1 5
5- 16
5-1 7

5-18
5- 19
5-20
5- 26
5-27
5-29

LIST OF ILLUSTRATIONS (Continued)
FIGURE
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-22
5-23

TITLE

PAGE

Enabling and Triggering TMS 9901 Interval Timer
Example of Code to Run TMS 990 1 Interval Timer
Example Program Using Timer Interrupts 3 and 4
Move Block of Bytes Example Subroutine
Compare Blocks of Bytes Example Subroutine
Reading the DIP Switch . . . . . . . . . .
Coding Example t o Ascertain System Configuration
Through DIP Switch Settings • . . . • .
Coding Example to Blink L.E.D. On and Off . .
Example Proglram to Converse Through Main and
Auxiliary TMS 9902's

6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16

TM 990/101M Block Diagram
Crystal-Controlled Operation
TMS 9900 Pin Functions
TMS 9900 Data and Address Flow
TMS 9900 CPU Flowchart
RESET and LOAD Logic
TM 990/101M Memory Addressing .
Memory Address Decode PROM
Decoding Circuitry for CRU I/O Addresses
TMS 9900 Memory Bus Timing
Read-Only Memory
Random Access Memory
TMS 9901
Serial I/O Port EIA Interface
Serial I/O Port TTY Interface
Multidrop Interface .

7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12

Jumper Placement
Memory and Capacitor Placement
Memory Expansion Maps . • . . .
. . . .
Four Interrupt-Causing Conditions at TMS 9902
Multidrop System . . . . . . . . . . . .
Multidrop Cabling . . . . . . . . . . . .
Master-Slave Full Duplex Multidrop System
Half-Duplex Multidrop System
Line-By-Line Assembler Output .
TM 990/301 Microterminal
TM 990/510 OEM Chassis . • • .
OEM Chassis Backplane Schematic

x

. 5-31
. 5-33
5-38
5-50
5-51
. . 5-53
. 5-54
5- 55

5-57
..
• • •
. . .
.
..

.
.
. • •
.
.
.

6-2
6-8
6-9
6-11
6-12
6-13
6-16
6-18
6-20
6-26
6-28
6-29
6-33
6-35
6-36
6-37

. . 7-2
7-3
. 7-6
.• 7-8
7-9
7-9
7-10
. 7-11
7-14
7-15
. 7-1 6
. 7-17

LIST OF ILLUSTRATIONS (Continued)
FIGURE
8-1
8-2
8-3
8-4
8-5
8-6

8-7
8- 8
8-9
8-10
8-11
8-1 2
8-13

8-1 4

TITLE
Major Components Used in I/O . . . .
Off-Board Memory
Circuitry to Add TMS 9901 Off-Board
8-Bit 9905/06 Port
RS-232-C Port
DMA Bus Control
CPU HOLD and HOLDA Timing
DMA System Timing
Memory Cycle Timing
DMA System Block Diagram
DMA Device Controller
DMA Controller . . . .
DMA Controller Timing
Cable Connections . . .

xi/xii

PAGE
8- 2
8-3
8- 4
8-5
8-6
8-8

8- 9
8-10
8-12
8-13
8- 13
8- 14
8-1 6
8-17

"

LIST OF TABLES

(
TITLE

TABLE

PAGE

1-1

TM 990/101M Configurations .

1-4

2 -1

Board Jumper Positions as Shipped

2- 3

3-1

3- 1
3- 3

3-3
3-4

TIBUG Commands . . . .
Command Syntax Conventions
User Accessible Utilities
TIBUG Error Messages

3-18

4-1
4-2
4-3
4-4

Status bits
Instruction
Instruction
Instruction

Affected by Instructions
Description Terms
Set, Alphabetical Index
Set, Numerical Index . .

4-5
4-14
4-15
4-17

5-1

5- 1
5- 6

5-6
5-7

Assembler Directives Used in Examples
Register Reserved Application
TM 990/101M Predefined CRU Addresses
Preprogrammed Interrupt and User XOP Trap Vectors
Interrupt and User XOP Linking Area
Interrupt Example Program Description
ASRFLAG Values . . . . . . . . . . . .

6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6- 9
6-10

Device Supply Voltage Pin Assignment s
Bus Signals . . . . .
Control Bus Functions
External Instructions
TM 990/10 1 CRU Map . .
Implicit Decoded CRU Bit Addresses .
On-Board Device CRU Address
Data Buffers
Interrupt Characteristics
Dedicated Interrupt Description

7-1
7- 2
7-3
7-4
7- 8

Master Jumper Table . . . . . .
Jumper Pins by Board Dash Number (Factory Installation)
Slow EPROM Table . . . . . .
Multidrop Jumper Table . . .
Half-Duplex Multidrop System

7-4
7- 5
7-7
7- 10
7- 11

8-1
8-2
8- 3
8- 4

103/113 Data Set Cable
202/212 Data Set Cable
201 Data Set Cable .
Data Terminal Cable

8-18
8-18
8-1 9

3-2

5-2
5-3
5-4

5- 5

3- 14

5 - 12

5- 24
5- 25
5- 35
5- 60
6- 3
6- 5
6- 6
6-14
6- 21

6- 25
6- 25
6- 30
6- 31
6-31

8- 17

xiii

•

SECTION 1
INTRODUCTION

~

1.1 GENERAL
The Texas Instruments TM 990/101M is a self-contained microcomputer on a single
printed-circuit board. The board's component side is shown in Figure 1-1, which also
highlights major features and components. Figure 1-2 shows board dimensions. This
microcomputer board contains features found on computer systems of much larger size,
including a central pr oc essing unit (CPU) with hardware multiply and divide,
programmable serial and parallel I/O lines, external interrupts, and a debug-monitor
to assist the programmer in program development and execution. Other features include:
•

TMS 9900 microprocessor based system: the microprocessor with the minicomputer instruction set - software compatible with other members of the 990
family .

•

1K x 16 bits of TMS 4045 random-access memory (RAM) expandable on-board to
2K x 16 bits.

•

1K x 16 bits of TMS 2708 erasable programmable read-only memory (EPROM), expandable on-board to 2K x 16 bits. Simple jumper modifications enable substitution of the larger TMS 2716 EPROM's (16K bits each) for the smaller
TMS 2708's (8K bits each) . Four TMS 2716's permit EPROM expansion to 4K x 16
bits.
NOTE
Three board configurations are available. The characteristics
of each configuration are explained in paragraph 1.3.

•

Buffered address, data, and control lines for off-board memory and I/O expansion; full OMA capabilities are provided by the buffer controllers.

•

3 MHz crystal-controlled clock .

•

One 16-bit parallel I/O port, each bit is individually programmable.

•

Modified EIA RS-232-C serial I/O interface, capable of communication to both
EIA-compatible terminals and popular modems (data sets).

•

A local serial I/O port, with interfaces for an EIA terminal and either a
Teletype (TTY) or a twisted-pair balanced- line multidrop system (interface
choices are detailed in paragraph 1.3).

•

Three programmable interval timers.

•

17 prioritized interrupts, including RESET and LOAD functions. Interrupt 6
is level triggered (active LOW) and edge-triggered (either polarity) and
latched on-board.

•

A directly addressable five-position DIP switch and an addressable light
emitting diode (LED) for custom system applications.

•

PROM memory decoder permits easy reassignment of memory map configuration;
see Figure 1-3 for memory map of the standard board .

1-1

TMS 9902 FOR MAIN PORT--- - - - TMS 9902 FOR AUXILIARY

5 SWITCH l.D. DIP

PORT ---~

PARALLEL 1/0 PORT (P4)

RESET SWITCH S1

E.D.

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3:

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'°
'°
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I§
3:
3:
Pl
:......
0
'1

()

0

s
'O
0

·~

I~

CONNECTOR Pl
' - - - - - - T I M 9904 CLOCK DRIVER
' - - - - - - - - - - - 4 8 MHz CRYSTAL
~

RAM SOCKETS
\

EPROM SOCKETS

74S287 MEMORY DECODE PROM

~---ADDRESS AND DATA BUFFERS
4

•

T MS 9 900

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u u__ ~~

TI~:= o=·:o~cfo· u: ~ u~ ·~·
~~- -~ o~ ff· o, U:!o.
::

Ill

0

r_}

~

I)

I

~-,l

I

c~ I

~-----------

Figure 1-2 .

TM

I

•~'

f 0 l

fl~ I

I

1,

I

~ •

7.5 INCHES -------------~

9901_1Q1~._Dimensions

1-3

and Component Placement

1.2 MANUAL ORGANIZATION
Section 1 covers board specifications and characteristics . A glossary in par agraph 1.7
explains terms used throughout the manual.
Section 2 explains how to install, power-up, and operate the TM 990/10 1 microcomputer
with the addition of a data terminal, power supplies, and appropriate connec t ors.
Section 3 explains how to communicate with the TM 990/ 101M using the TIBUG monitor.
This versatile monitor, complete ~lth supervisor calls and operator communication
commands, facilitates the development and execution of software.
Section 4 d escribes the instruction set of the TM 990/101M, giving examples of each
class of instructions and providing some explanation of the TMS 9900 architecture .
Section 5 explains basic programming procedures for the microcomputer, giving an
explanation of the programming environment and hardware-dependent features. Numerou s
program examples are included for utilizing the various facilities of the TM 990/101M.
Section 6 is a basic theory of operation, explaining the hardware design configuration
and circuitry. This section provides explanations of the bus structure , the co ntrol
logic , and the various subsystems which make up the microcomputer.
Section 7 describes various options available for the microcomput er, both those
supplied on-board and those which Texas Instruments offers for off-board expansion of
the system.
Section 8 features various hardware applications which can be built using the TM
990/101M.
1.3 PRODUCT INDEX
The TM 990/101M microcomputer is avai lable in three different configurations, which
are specified by a "dash number" appended to the product name; e . g . , TM 990/101M-1.
These configurations are listed in Table 1-1. A memory map is shown in Figure 1-3.

Table 1-1.

TM 990/101M
Dash No.
-1

-2

-3

TM 990/101M Configurations
Main Serial Port
Option (EIA
Terminal
I/F Stand)

EPROM
Socketed
2 TMS
(1K x
2 TMS
(2K x
4 TMS
(4K x

2708
16)
2716
16)
2716
16)

Program

RAM

TIBUG Monitor
Blank
Blank

1-4

4 TMS
(1K x
4 TMS
(1K x
8 TMS
(2K x

4045
16)
4045
16)
4045
16)

TTY
Multidrop
TTY

•

MAIN EPROM 0

07F F
OFFF
EXPANSION
EPROM

EXPANSION
RAM

TM 990/ lOlM
MAIN RAM

'EPROM' s programmed w ith TIBUG m onitor.

Figure 1-3.

Main And Expansion EPROM and RAM

1.4 BOARD CHARACTERISTICS
Figure 1-1 shows the major portions and components of the microcomputer. The system
bus connector is P1, which is a 100-pin (50 each side) PC board edge connector spaced
on 0.125 inch centers. Connector P2 is the main serial port and P3 is the RS-232-C
auxiliary serial port. Both connectors are standard 25-position female jacks used in
RS-232-C communications. The parallel I/O port is PC board edge connector P4, which
has 40 pins (20 each side) spaced on 0.1-inch centers.
Figure 1-2 shows the PC board silkscreen markings which detail the various components
on the board; also included are the board dimensions and tolerances.
1.5

GENERAL SPECIFICATIONS
Power Consumption
TM 990/101M-1
TM 990/101M-2

+5 v
TYP MAX
1.8 2.6
1. 8 2.6

+12 v
TYP MAX
0.30 0.50
0.30 0.50

-12 v
TYP MAX
0.25 o.4o
0.25 o.4o

Clock Rate: 3 MHz
Baud Rates (set by TIBUG): 110, 300, 600, 1200, 2400, 4800, 9600, 19200

1-5

Memory Size: The microcomputer is shipped with:
RAM:
Four TMS 4045 (1K x 4 bits each)
EPROM:
Two TMS 2708 (1K x 8 bits each), preprogrammed with TIBUG.
Total capacity is:
RAM:
Eight TMS 4045's (1K x 4 bits each)
EPROM:
Four TMS 2708 1 s (1K x 8 bits each)
or
Four TMS 2716's (2K x 8 bits each)
Board Dimensions: See Figure 1-2
Parallel I/O Port (P4): One 16-bit port, uses TMS 9901 programmable systems interface
Serial I/O Port (P2 and P3): Two asynchronous ports:
Main port (P2) has two interfaces: RS-232-C answer mode and either a TTY or a
balanced-line differential multidrop interface.
Auxiliary port (P3) meets RS-232-C specification interface, capable
of either originate or answer mode.
Both serial ports use TMS 9902 asynchronous communication controllers, but the
Auxiliary Port wi ll readily accept the TMS 9903 synchronous communication
controller. Simply plug in the TMS 9903 for synchronous systems.
1.6 REFERENCE DOCUMENTS
The following documents provide supplementary information for the TM 990/101M user's
manual.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

TMS 9900 Microprocessor Data Manual
TMS 9901 Programmable Systems Interface Data Manual
TMS 9902 Asynchronous Communication Controller Data Manual
TMS 9903 Synchronous Communication Controller Data Manual
TMS 990 Computer, TMS 9900 Microprocessor Assembly Language Programmer's
Guide (P/N 943441-9701)
TM 990/301 Microterminal
TM 990/401 TIBUG Monitor Listing
TM 990/402 Line-by-Line Assembler User's Guide
TM 990/402L Line-by-Line Assembler Listing
TM 990/502 Cable Assembly (RS-232-C)
TM 990/503 Cable Assembly (TI Terminal 743 or 745)
TM 990/504 Cable Assembly (Teletype)
TM 990/506 Cable Assembly (Modem cable for /101 board)
TM 990/510 Card Chassis
TM 990/511 Extender Board User's Guide
TM 990/512 Prototyping Board User's Guide

1.7 GLOSSARY
The following are definitions of terms used with the TM 990/101M. Applicable areas in
this manual are in parentheses.
Absolute Address: The actual memory address in quantity of bytes. Memory addressing is
usually represented in hexadecimal from 000016 to FFFF16 for the TM 990/101M.
Alphanumeric Character: Letters, numbers, and associated symbols.
ASCII Code: A seven-bit code used to represent alphanumeric characters and control
(Appendix C).
1-6

Assembler: Program that translates assembly language source statements into object
code.
Assembly Language: Mnemonics which can be interpreted by an assembler and translated
into an object program (paragraph 4.6).
Bit: The smallest part of a word; it has a value of either a 1 or 0.
Breakpoint: Memory address where a program is intentionally halted. This is a program
d'e bugging tool.
Byte: Eight bits or half a word.
Carry: A carry occurs when the most-significant bit is carried out in an arithmetic
operation (i.e., result cannot be contained in only 16 bits), (paragraph 4.3.3.4).
Central Processing Unit (CPU): The "heart" of the computer: responsibilities include
instruction access and interpretation, arithmetic functions, I/O memory access. The
TMS 9900 is the CPU of the 'IM 990/101M.
~:

Dot-like paper particles

resul~ing

from the punching of paper tape.

Command Scanner: A given set of instructions in the TIBUG monitor which takes the
user's input from the terminal and searches a table for the proper code to execute.
Context Switch: Change in program execution environment, includes new program counter
(PC) value and new workspace area.
CRU (Communications Register Unit): The TMS 9900's general purpose, command-driven
input/output interface. The CRU provides up to 4096 directly addressable input and
output bits (paragraph 4.8).
Effective Address: Memory address value resulting from interpretation of an
instruction operand, required for execution of that instruction.
EPROM: See Read Only Memory.
Hexadecimal: Numerical notation in the base 16 (Appendix D) .
Immediate Addressin : An immediate or absolute value (16-bits) is part of the
instruction second word of instruction).
Indexed Addressing: The effective address is the sum of the contents of an index
register and an absolute (or symbolic) address (paragraph 4.5.3.5).
Indirect Addressing: The effective address is the contents of a register (paragraph
4.5.3.2).
Interrupt: Context switch in which new workspace pointer (WP) and program counter (PC)
values are obtained from one of 16 interrupt traps in memory addresses 0000 16 to
003E 16 (paragraph 4.9).
I/O: The input/output lines are the signals which connect an external device to the
d'ata lines of the TMS 9990.

1-7

Least Significant Bit (LSB): Bit having the smallest value (samllest power of base 2);
represented by the right-most bit.
Link: The process by which two or more object code modules are combined into one, with
cross-referenced label address locations being resolved.
Load: Transfer control to operating system using the equivalent of a BLWP instructior

~ectors in upper memory (FFFC 15 and FFFE 15). See Reset.

Loader: Program that places one or more absolute or relocatable object programs into
memory (Appendix G).
Machine Language: Binary code that can be interpreted by the CPU (Table 4-4).
Monitor: A program that assists in the real-time aspects of program execution such as
operator command interpretation and supervisor call execution. Sometimes called
supervisor (Section 3).
Most Significant Bit (MSB): Bit having the most value; the left-most bit representing
the highest power of base 2. This bit is often used to show sign with a 1 indicating
negative and a 0 indicating positive.
Object Program: The hexadecimal interpretations of source code output by an assembler
program. This is the code executed when loaded into memory.
One's Complement: Binary representation of a number in which the negative of the
number is the complement or inverse of the positive number (all ones become zeroes,
vice versa). The MSB is one for negative numbers and zero for positive. Two
representations exist for zero: all ones or all zeroes.
Op Code: Binary operation code interpreted by the CPU to execute the instruction
(paragraph 4.5.1).
Overflow: An overflow occurs when the result of an arithmetic operation cannot be
represented in two's complement (i.e . , in 15 bits plus sign bit), (paragraph 4.3.3.5).
Parity: Means for checking validity of a series of bits, usually a byte. Odd parity
means an odd number of one bits; even parity means an even number of one bits. A
parity bit is set to make all bytes conform to the selected parity. If the parity is
not as anticipated, an error flag can be set by software. The parity jump instruction
can be used to determine parity (paragraph 4.3.3.6).
PC Board: (Printed Circuit Board) a copper-coated fiberglass or phenolic board on
which areas of copper are selectively etched away, leaving conductor paths forming a
circuit. Various other processes such as soldermasking and silkscreen markings are
added to higher quality PC boards.
Program Counter (PC): Hardware register that points to the next instruction to be
executed or next word to be interpreted (paragraph 4.3.1).
~:

See Read Only Memory.

Random Access Memory (RAM): Memory that can be written to as well as read from (vs.
ROH).
Read Only Memory (ROM): Memory that can only be read from (can't change contents).
Some can be prograrmned (PROM) using a PROM burner. Some PROM's can be erased (EPROM's)
by exposure to ultraviolet light.

1-8

Reset£ Transfer control to operating system using the equivalent of a BLWP instruction
to vectors in lower memory ( 000016 and 000215). See Load.
Source Program: Programs written in mnemonics that can be translated into machine
language (by an assembler).
Status Register (ST): Hardware register that reflects the outcome of a previous
instruction and the current interrupt mask (paragraph 4.3.3).
Supervisor: See Monitor
Utilities: A unique set of instructions used by differnt parts of the program to
perform the same function. In the case of TIBUG, the utilities are the I/0 XOP's
(paragraph 3.3).
Word: Sixteen bits or two bytes.
Workspace Register Area: Sixteen words, designated registers 0 to 15, located in RAM
for use by the executing program (paragraph 4.4).
Workspace Pointer (WP): Hardware register that contains the memory address of the
beginning (register o) of the workspace area (paragraph 4 . 3.2) .

•

1-9

"

SECTION 2
INST·ALLATION AND OPERATION OF TM 990/101M-1
2. 1 GENERAL
This section explains procedures for unpacking and setting up the TM 990/101M board
for operation. This section assumes (1) the TIBUG monitor is resident on EPROM's as
initially shipped from the factory, and (2) that a terminal suitable for connection to
the main communications port is used with the proper cable assembly.
CAUTION
Be sure that the correct cable assembly is used with
your data terminal. For teletypewriters (TTY), refer to
Appendix A. For RS-232-C compatible terminals, refer to
Appendix B for the signal configuration used by the
main I/O port. Most RS-232-C compatible terminals, such
as a Lear Siegler ADM-1, will require the TM 990/502
cable, or equivalent. A TI 743 or 745 must use a TM
990/503 cable, or equivalent because of the connector
on the terminal end of the cable. A TI 733 requires the
use of a TM 990/50~ cable, or equivalent. Many RS-232-C
compatible te('1ni nals come with their own cables, and
thererore will probably work with no problem.
2.2 REQUIRED EQUIPMENT
The basic equipment required, along with appropriate options, is explained in the
following paragraphs .
2 . 2.1 POWER SUPPLY
A power supply capable of meeting at least the following specification is required:
Voltage
+5 v
-12 v
+12 v

•

Regulation

Current

3%
3%
3%

1.8 A
0.3 A
0.4 A

A heavier duty supply is recommended, if possible, especially for supplying
voltage .

the +5

2.2.2 TERMINALS AND CABLES
A 25-pin RS-232 male plug, type DB25P, is required. Ready made cables are available
from TI: see Appendix A or B.
•

RS-232-C compatible terminal, including ti1e TI 733 (using its own cable):
see Appendix B to verify cabling you already have, or for" i'l -'>t'"'•Jc ti ons to
make a custom cable.

•

TI 743/745: see Appendix B for special cabling required
usually come with the correct cable).

•

Teletype Model 3320/5JE (for TM 990/101M-1 and -3 microcomputer boards
only): see Appendix A for required modifications for 20 mA neutral
current-loop operation and proper cable connections.

2-1

(these terminals

2.2.3 POWER CABLE/CHASSIS
Use of a TM 990/510 OEM chassis greatly facilitates operation and setup. Alternately,
one of the following 100-pin, 0.125 inch (center-to-center) PCB edge connectors may be
used to interface with connector P1, such as with wire-wrap models:
•
•
•
•

TI H321150
Amphenol 225-804-50
Viking 3VH50/9CND5
Elco 00-6064-100-061-001.

2.2.4 PARALLEL I/O CONNECTOR
If the P4 parallel I/O port is used, a ribbon cable with a 40-pin, 0.1-inch center
spacing PCB edge connector is needed. (The TIBUG monitor does not use the parallel
port in its normal processing.) Wire-wrap connector examples are as follows:
e
•
2.2.5
•
•

TI H311120
Viking 3VH20/IJND5.
MISCELLANEOUS EQUIPMENT
Volt-ohmmeter to measure completed/open connections and to verify power supply voltages and connections.
If any custom connections are required, a soldering iron (25-45 watt), rosin
core solder, and wire are needed. Suggested wire sizes are 18 AWG insulated
stranded wire for power connections, 24 AWG insulated stranded wire for I/O
connections.

2.3 UNPACKING
Lift the TM 990/101M board from its carton and remove the protective wrapping. Check
the board for shipping damage . If any damage is found, notify your TI distributor.
Verify that at least the following items are included:
•
TM 990/101 User's Guide (this manual)
e
TM 990/401 TIBUG Monitor Listing
•
Data Manuals for the TMS 9900, TMS 9901, and TMS 9902
2.4 POWER AND TERMINAL HOOKUP
These procedures assume that the TIBUG monitor is resident in the required address
space (000016 to 07FF16), and that a terminal and cable of the proper type to match
the intended serial interface (TTY, EIA, multidrop) is also employed .
Check the board and verify that the jumper configuration is as described in Table 2-1.
Table 7-1 (in Section 7, Options) further defines jumper configurations.

2-2

Table 2-1.

Board Jumper Positions As Shipped

Stake Pins Used

Proper Connection & Description

[nterrupt 4 source
Interrupt 5 source
Slow EPROM
2708/2716 Memory Map
EPROM Enable
HI/LO Memory Map
EIA Connector Ground
Microterminal +5-V
Microterminal +12 V
Microterminal -12 V
Main EPROM TYPE
Expansion EPROM type
Teletype

E1,E2,E3
E4,E5,E6
E7,E8,E53
E9,E10,E11
E12,E13,E14
E15,E16,E17
E18,E19
E20,E21
E22,E23
E24,E25
E26 through E30
E31 through E35
E36,E37

EIA/MD receive select
Multidrop Termination

E38,E39,E40
E41 through E52

E1 to E2 - pin 18, connector P1
E4 to E5 - pin 17, connector P1
EB to E53 - No WAIT state
E10 to E11 - Use TMS 2708's
E13 to E14 - On-board EPROM
E16 to E17 - EPROM low, RAM high
E18 to E19* - pin 1 of P3 grounded*
Shipped installed on -0001,3 only*
Shipped installed on -0001,3 only*
Shipped installed on -0001,3 only*
E27 to E28, E29 to E30 - TMS 2708's
E32 to E33, E34 to E35 - TMS 2708's
Shipped removed. On -0001,3 only,
if using a TTY, borrow a Microterminal jumper plug for use here.
E39 to E40 - EIA (and TTY) receive
Shipped installed on -0002 only*

Resistors and Duplex Select
P3 Port Terminal/Modem

E54,E55,E56

E54 to E55 - Terminal Use*

Function

*Jumper connection is not relevant for TIBUG operation with an RS-232-C or TTY
terminal.
CAUTION
Be very careful to apply correct voltage levels to the
TM 990/101M. Texas Instruments assumes no responsibility
for damage caused by improper wiring or voltage
application by the user.
2 . 4.1 POWER SUPPLY CONNECTIONS
Figure 2-1 shows how the power supply is connected to the TM 990/101M through
connector P1, using a 100-pin edge connector. Be careful to use the correct pins as
numbered on the board; these pin numbers may not correspond to the numbers on the
particular edge connector used. Check connections with an ohmmeter before applying
power if there is any doubt about the quality or location of a connection.
The table in Figure 2-1 shows suggested color coding for the power supply plugs . To
prevent incorrect connection, label the top side of the edge connector "TOP" and the
bottom "TURN OVER".
Figure 2-2 shows how to correctly place the TM 990/101M in the TM 990/510 card
chassis. Slot 1 of the chassis is reserved for the microcomputer because termination
resistors for the control bus signals are at the opposite end of the backplane,
according to transmission line concepts. Slide the microcomputer into the slot,
following the guides . Be sure the P1 connector is correctly aligned~in the socket on
the backplane, then gently but firmly push the board edge into th~· edge connector
socket.

2-3

TM99/101M

o>
Z

ID

C> +

2 4

>>
NN

P1 CONNECTOR
(TOPI

10

20

30

40

50

......
I +

60

70

74 76

80

90

100

OODDDDDDDDODDDDDDDDDDDDDOODOODDDDDODOOODDDOOODODOD
EDGE CONNECTOR

BANANA PLUGS _ _ _ _ _ _ _ _...,..
(

SUGGEST COLOR CODING)
THESE AS PER TABLE

VOLTAGE

P1 PIN•

SUGGESTED PLUG COLORS

+5V

3,4,97,98

RED

+12V

75, 76

BLUE

-12V

73,74

GREEN

GND

1, 2, 99, 100

BLACK

*ON BOARD, ODD-NUMBERED PADS ARE DIRECTLY BENEATH EVEN-NUMBERED PADS.
A0001417

Figure 2-1.

Power Supply Hookup

2-4

+12 0
+5 0

..

GNO 0

-12 0

Figure 2-2 .

TM 990/101M Board In TM 990/510 Chassis

Looking on the backside of the backplane, find the connections for each of the supply
voltages and connect them to the power supply.
CAUTION
BEFORE connecting the power supply to the microcomputer,
use a volt-ohmmeter to verify that correct voltages are
present at the power supply. After verification, switch
the power supply OFF, and then make the connections to
the chassis as shown in Figure 2-2.

'

2.4.2 TERMINAL HOOKUP
Figure 2-3 shows how the TM 990/101M is connected to the TI 743 KSR terminal through
connector P2. DE15S connector attaches to the terminal; a DB25P connector attached to
P2 on the board. A table of point-to-point connections between the connectors are
shown in the figure. Figure 2-4 shows a RS-232 terminal (e . g., TI 733), and Figure 2-5
shows a TTY.
All terminals connected to the microcomputer will have a similar hookup procedure and
point-to-point configuration. For the differences between terminal cables, see
Appendixes A and B. Terminals for communication directly with TIBUG must be connected
to the main communications port (connector P2) at the corner of the board.

2-5

DB25P

DE15S

T0743 DATA
TERMINAL

TOP2 ON

TM9901101M
4 CONDUCTOR CABLE, 24 AWG
INSULATED STRANDED WIRE

CONNECTIONS
PIN ON DE15S

PIN ON DB25P

13

2

XMIT

12

3

RECV

SIGNAL

11

8

DCD

1

7

GND

A0001418

Figure 2-3 .

743 KSR Terminal Hookup

rr~1Cf

c te: 1~1
c:c C:C

Figure 2-4.

Connector P2 Connected to RS-232-C Device (Model 733 ASR)

2-6

Figure 2-5.

Connector P2 Connected to TTY Device

The jumper mark ed EIA / MD, pins E38-E40, should be in the EIA position, pins E39 t o
E40, at all times unless the multidr op interface is us ed. If c onnecting a RS - 23 2
terminal, remove the TTY jumper at E36- E37, if connecting a Teletype termina l, t hen
insert the TTY jumper at E36-E37 .
The TIBUG monitor operates the local I/O port at one of the following baud r a tes:
110, 300, 600, 1200, 2400, 4800, 9600 or 19200 baud.
There is a 200 ms delay following a carriage return for all baud rates at or below
1200 baud. The delay allows for printhead travel .

•

The TMS 9902 asynchronous communication controller is initialized by TIBUG f or a
seven-bit ASCII character, even parity, and two stop bits (for compatibility with al l
terminals). At the terminal, set the baud rate of the terminal to one of t he above
speeds.
TIBUG also uses conversational mode full-duplex communicati on. Set the communications
mode of your terminal to FULL DUPLEX, and set the OFF/ON LINE swi tch to ON LINE, o r
the functional equivalents.

2-7

2.4.3 FIVE-SWITCH DIP AND STATUS LED
A five-switch DIP and a programmable LED are accessed through the Communications
Register Unit (CRU) . Programming these is further explained in subsections 5.7 and 5.8
respectively.
2.5

OPERATION

2.5 .1 VERIFICATION
Verify the followi ng conditions before applying power:
•
•
•
•
2 . 5.2

Power connected to correct pins on P1 connector.
Terminal cable between P2 connector (NOT P3) and terminal.
Jumpers in correct positions (see Table 2-1).
Baud rate and communications mode are correctly set at the terminal;
terminal is ON LINE.
POWER-UP/RESET

a.

Apply power to the board and the data terminal.

b.

Activate the RESET switch near the corner of the microcomputer board
(see Figure 1-1). This activates the TIBUG monitor.

c.

Press t he "A" key on the terminal (it may be more convenient to press the
carriage return key instead; this is also acceptable ) . TIBUG measures the
time of the start bit and determines the baud rate. A carriage return time
delay of 200 ms will be provided for all baud rates at or slower than 1200
baud.

d.

TIBUG prints the TIBUG banner message and, on a new line , a question mark.
This is a request to input a command to the TIBUG command scanner . Commands
ar e explained in detail in Section 3 , and the assembly language is described
in Section 4.
NOTE
If control is lost during operation, return control to
the TIBUG monitor by repeating steps b, c, and d.

2.6 SAMPLE PROGRAMS
The following sample programs can be used immediately to test the microcomputer board.
Other sample programs that can be loaded and executed are provided in Figures 5-1 5
(interrupt timer message) and 5 - 22 (L.E.D. blink). Appendix K co ntain s example
programs that demonstrate microcomputer performance.
2.6.1 SAMPLE PROGRAM 1
The following sample program can be input using the TIBUG "M" command (paragraph
3 . 2 .8 ) , "R" command (paragraph 3.2.9) , and "E" command (paragraph 3 . 2.4) .
a.

Enter the M command with a hexadecimal memory address of

2- 8

FEOOl6 ·

b.

Enter the following values into memory, typing the new values then using the
space bar as described in paragraph 3.2.8.
Location

Enter Value

FEOO
FE02
FE04
FE06
FE08
FEOA
FEOC

2FAO
FE08
0460
0080
4849
ODOA
0700

Assembly Language
XOP

@

FE08, 14

PRINT MSG

B

@

0080

GO TO TIBUG

TEXT 'HI'
DATA ODOA
DATA 0700

MESSAGE
CR/LF
BELL/END

Exit the M command with a ca£riage return after entering the last value
above. The monitor will print a question mark.
c.

Use the R command to set the address value 'FEOO" into the P register (program counter) .

d.

Use the E command to execute the program.

e.

The message 'HI' will print on the printer, followed by a carriage return,
line feed, and a bell. Your terminal printout should resemble the following:
TI BUG

~· EV.

?M FEOO
FE 0 O=I1:::: 0 0
FE 02=6:3 0 0
FE 04= 0:3:=: 1
FE06=23D2
FE 08= 03 0 0
FEOA=03C2
FEOC=7:300

Ft
2FFtO

FE0:3
04E·O

0080
4::349

OD OA

0700

?R
t.•J=FFC6

F'=01FtC
·? E HI

FEOO

•
You can re-execute your program by repeating steps c. and d.

2-9

2 .6. 2 SAMPLE PROGRAM 2
Using steps 1 to 5 in paragraph 2.6.1 above, enter and executa the following program
which has been assembled by the optional TM 990/402 line- by-line assembler .
,..: i=. th! .:. F H 11
c F'
FE (12 FE o::·
F E I) 4 1) 4 ':• I) E· J!

FEOe
FEU ::..

f 10:: : i-1
4 ~: 4F

l'

~ E:_ 1_1 :. •

l 4

1:1 I ..: i-1

f1_Cir H3F>-iT l_iL>i Ti rJti- .

1'J •_: ~

c c ry:;F!-4r·1 1.i[Jf:·f . !

4E47
FEOC ':0241
FEOE 5 455

FE1·18

FE l O 4C41
FE 12 544·:;.

FE 14 4F4E
F E 1 .;. 5 ;. 2 E
FE i:::; 2 o:.·:;.
FE 18 4F': 5
F E 1 c ·:. 2 2 I)
1

f'E l E 5052
FE2fl 4F47
~ E22
FE2 4
FE2t::.
fT ,:=·:::
FE-. 2H

': 2 41
4fl20
'57 4F
0

:.c.·-tf:

':· ::: 2 1

FE2C

11 ,~ 1 :1 ~·

+

f1~~1).'

H : 2E

117 111_1

+

1·17 n (I

You can re-execute your program by repeating c . and d. in paragraph 2 . 6 .1 above.
2.7 DEBUG CHECKLIST
If the microcomputer does not respond correctly, turn the power OFF. Do not turn the
power ON again until you are reasonably s ure the problem has been found. The following
i s a checklist of points to verify.
•

Check POWER circuits:
Proper power supply voltages and current capacity .
Proper connections from the power supply to the P1 edge connecto r .
Check pin numbers on P1. Check plug positions at your power supply.
Look for short circuits. Look for broken connections . ~a ke ~1 1r e boa rd
is seated in chassis or edge connector socket correctly. Be certain
that the edge connector socket (if used) is not upside down.

e

Check TERMINAL circuits:
Proper cable hookup to P2 connector, and to terminal . Verify wi t h data
in Appendixes A and B. One of the most common errors is that the terminal cable is not plugged in .
Check for power at the terminal . This is another c ommon err or - t he
terminal is not turned ON .
Terminal is ON LINE mode, or equivalent .
Terminal is in FULL DUPLEX mode, or equivalent. If the terminal is in
HALF DUPLEX mode, it will print everything you type t wice , or it may
print garbage when you type. Put the terminal in FULL DUPLEX mode.
2-10

EIA/MD jumper in EIA position (E30).
Check BAUD RATE of terminal - it must be 110, 300, 600 , 1200, 2400,
4800, 9600, or 19200 BAUD.
•

Check jumper plug positions against Table 2-1.

•

Be sure TIBUG EPROM's are in place correctly (U42 and U44) .

....e

Check all socketed parts for correctly inserted pins. Be sure there aren't
any bent under or twisted pins. Check pin 1 location.

If nothing happens, feel the components for excessive heat. Be careful as burns may
occur if a defeetive component is found. If the cause of inoperation cannot be found,
turn power OFF and call your TI distributor. Before calling, though, please be sure
that your power supply, terminal, and all connectors (use a volt-ohmmeter) are
working properly .

2-11

SECTION 3
TIBUG INTERACTIVE DEBUG MONITOR
1. 1 GENERAL
fIBUG is a debug monitor which provides an interactive interface between the user and
the TM 990/101M. It is supplied by the factory on assembly TM 990/101M-1 only and is
available as an option, supplied on two 2708 EPROM's.
TIBUG occupies EPROM memory space from memory address (M.A.) 008016 as shown in Figure
3-1. TIBUG uses f ou r workspaces in 40 words of RAM memory. Also in this reserved RAM
area are the restart vectors which initialize the monitor following single step
execution of instructions .
The TIBUG monitor provides seven software routines that accomplish special tasks.
These routines, . called in user programs by the XOP machine instruction, perform tasks
such as writing characters to a terminal. XOP utility instructions are discussed in
detail in paragraph 3.3.
All communication with TIBUG is through a 20 mA current loop or RS-232-C device. TIBUG
is initialized as follows:
•

Press the RESET pushbutton (Figure 1-2). The monitor is called up through
interrupt trap O.

•

Enter the character 'A' at the terminal. TIBUG uses this input to measure
the width of the start bit and set the TMS 9902 Asynchronous Communication
Controller (ACC) to the correct baud rate.

•

TIBUG prints an initialization message on the terminal. On the next line it
prints a question mark indicating that the command scanner is available to
interpret terminal inputs.

•

Enter one of the commands as explained in paragraph 3.2.

3.2 TIBUG COMMANDS
TIBUG commands are listed in Table 3-1.
Table 3-1.
INPUT
B

c
D
E
F
H
L
M
R

s
T

w

TIBUG Commands
RESULTS

Execute under Breakpoint
CR U Inspect/Change
Dump Memory to Cassette/Paper Tape
Execute
Find Word/ Byte in Memory
Hex Arithmetic
Load Memory from Cassette/Paper Tape
Memory Inspect/Change
Inspect/Change User WP , PC . and ST Registers
Execute i n Step Mode
1200 Baud Terminal
Inspect/Change Current User Workspace

3-1

PARAGRAPH
3.2. 1
3.2.2
3 .2.3
3 2. 4
325
3.2.6
3.2.7
3.2.B
3 2.9
3 .2. 10
3.2 11
3 2.12

MEMORY
ADDRESS
0000

•
INTERRUPT VECTOR (RESET)

TIBUG EPROM AREA

INTERRUPT VECTORS 1TO15
0040
0048

XOP VECTOR 2 TO 7

0060

XOP VECTORS 8 TO 15
MONITOR UTILITIES

007E
0080

USER EPROM AREA

XOP VECTORS 0 AND 1

TIBUG EPROM AREA
USER EPROM AREA

TIBUG EPROM AREA
TIBUG MONITOR

07FE

FFBO

MONITOR
WORKSPACES

RESTART VECTORS

{

FFFC
FFFE

Figure 3-1.

WP

'II

TIBUG RAM AREA

PC

Minimum Memory Requirements for TIBUG

3-2

Conventions us ed to define command syntax i n thi s paragraph are listed in Table 3- 2.
Table 3-2.

Command Syntax Conventions

CONVEN TION
SYMBOL

EXPLANATION

1----- - - 1 - - -- - - - - -- - - - -- - - - -- - - - -- - - ---·----- - - - - ------!

<>
I I

Items •n b .. supplied by ihP user The :p1111 ... •n1n rhe anglo h• ck,.t<
. :

Op t ion,1 '"'"'

are
1

May l.Je includ ed or

om111~tl

·~ J

yCfl•'• 1c •r•r>n

.11 t h e use• s d 1sc11>11,Jn l1e1ns nnt 1nclucieo . n bracl-c t'

rf'quuptJ

One of severa l o pllo na l it e ms must tic c ho>en .
C.irrrage R" turn
Spac e Bar

LF
A or Rn

Lone F  c(CR) >
3.2 . 1.2 Description
This command is used to execute instructions from one memory address to another (the
stopping address is the breakpoint). When e xe cution is complete , WP, PC, and ST
register contents are displayed and control is returned back to the monitor command
scanner. Program execution begins at the address in the PC (set by us ing the R
command) . Execution terminates at the addres s specified in the B command, and a banner
is ou t put showing the contents of the hardware WP, PC, and ST ..registers in that order.

r

f

The address s pecified mu s t be in RAM and must be the address of the firs t word of an
instruction . The breakpoi nt is controlled by a software i nterrupt, XOP 15 , wh i ch is
executed wh en program executi on is at the breakpoint address .
If no address is specified, the B command defaults to an E command, where execution
continues with no halting point specified.
3-3

EXAMPLE:
:ff FC Ot.

BP

3.2 . 2

FC

FFBt:1

l)t:i

CRU INSPECT/CHANGE (C)

3.2.2.1
C <..

Syntax
CRU  ,

< count >< (CR) >

3. 2.2 . 2 Description
The Communication Register Unit (CRU) input bits are displayed right justified in a
16-bit hexadecimal representation. CRU addresses of the displayed bits will be:
from " CRU Software Base Address"
to "CRU Software Base Address" + 2(Count) - 2
" CRU Software Base Address" is the contents of register 12, bits 0 to 15, as used
by the CRU i nstructions (paragraph 5.5). Up to 16 CRU bits may be displayed.
Following display of the sensed CRU input bits, corresponding CRU output bits at
that address may be specified by keying in a desired hexadecimal pattern of 1 to 16
bits, right justified. A carriage return following data display forces a return to
the command scanner . A minus sign (-) or a space causes the same CRU input bits to
be d i splayed again. Defaults are 0000 16 for "Software Base Address" and 0 (count
of 16) for "Count" (the latter is a hexadecimal value of 0 to F with 0 indicating a
decimal 16 bits).
The CRU inspect/change command displays from 1 to 16 CRU bits, right justified.
The command syntax includes the CRU software base address and the number of CRU
bits to be displayed. The CRU software base address is the 16-bit contents of R12
as explained in paragraph 5.5 (vs. the "CRU hardware base address" on bits 3 to 14
of R12); thu s , the user mus t use 2 X CRU hardware base address. This is shown in
Figure 3-2 where 100 16 is specified in the command to display values beginning with
CRU bit 80 16.

? c 100,7
0100= 007F

VALUE DISPLA YED

0

2

3

4

5

6

7

8

9

10 11

12 13 14

> oo7F
7 BITS
REQUESTED

Z ERO Fl LLED

80 CRU BIT

81
82

83

84
85
---~~~~~~~~

Figure 3-2.

86

CRU Bits Inspected By C Command

3-4

EXAMPLES:
(1) Examine eight CRU input bits. CRU software base address is 20 15.
C l_I •

; I-

:::

(11)21 1=(11_t F F - CARRIAGE RETURN ENTERED

(2) Set value of eight CRU output bits at CRU software base address 2016i
new value i s 02 15 .

c 1_1 • :::

;C
1) l_I

(3)

/,--;~- CHANGE OOFF TO 0002

c 1) =I 11_1 F F

2 FOLLOWED

av CARRIAGE

RETURN

Check changes in CRU input bit 0.
;(

I) • :=:

=

1J 1J l_l 1_11
(I I) I) I.I= l_I I) IJ 1
(I (1(1 (I= ( I (I I) 1

1) I) I)

=~

OO= 1_1001

(11)

I) (1 (I (I= (1 I) ( I 1
( 11) (I ( I= 1) 11 (1 1 -

(4)

2-

=~

MINUS SIGN ENTERED

- - CARRIAGE RETURN ENTERED

Check to see if the TMS 9901 is in the interrupt mode (zero) or clock mode
(one);
; :_
(I

l

1 I.I l_I
( I (l=>F"-FFE

-

- - ZERO IN LSB INDICATES INTERRUPT MODE

(5) Check the contents of the I / 0 ports on the TMS 9901 (bits 1 to 14 ) .

3.2.3

;c

120 ·E

0 12

i_I

=(1 0 1) E.

DUMP MEMORY TO CASSETTE/PAPER TAPE (D)

3.2.3.1

Syntax
/MONITOR PROMPT

D 

< stop address > '

 {

IDT = < name ><

>

NOTE
The termination given after IDT is a space bar. A carriage
return or some other termination will cause the instruction
to function incorrectly.

3-5

3.2 .3. 2 Description
Memory is dumped from " start address" to "stop address ." "Entry address" is the
address in memory where it is desired to begin program execution. After entering a
space or comma following the entry address, the monitor responds with an "IDT=" prompt
asking for an input of up to eight characters that will identify the program. This
program ID will be output. When the program is loaded into memory using the TIBUG
loader, code will be dumped as non-relocatable data in 990 object record format with
absolute load ( "start address") and entry addresses specified. When loading this code
once more, the LOAD will occur at the start address specified in the D instruction. If
a user specifies a starting address while loading the object code previously dumped,
the loader will ignore the user's input and load at the starting address specified
during the 'D' command. Object record format is explained in Appendix G.
After entering the D command, the monitor will respond with "READY YIN" and wait for a
Y keyboard entry indicating that the receiving device is ready. This allows the user
to verify switch settings, etc., before proceeding with the dump.
3 . 2.3.3 Dump to Cassette Example
The terminal is assumed to be a Texas Instruments 733 ASR or equivalent. The terminal
must have automatic device control (ADC). This means that the terminal recognizes the
four tape control characters DC1, DC2, DC3, and DC4.
The following procedure is carried out prior to answering the "READY Y/N" query
(Figure 3-3):
(1)

Load a cassette in the left (No. 1) transport on the 733 ASR.

(2)

Place the transport in the "RECORD" mode.

(3)

Rewind the cassette.

(4)

Load the cassette. If the cassette does not load, it may be write protected.
The write protect hole is on the bottom right side of the cassette (Figure
3-4) . Cover it with the tab provided with the cassette. Now repeat steps 1
through 4.

(5)

The KEYBOARD, PLAYBACK, RECORD, and PRINTER LOCAL/OFF/LINE s witches must be
in the LINE position.

(6)

Place the TAPE FORMAT s witch in the LINE position.

(7)

Answer the "READY YIN" query with a "Y"; the "Y" will not be echoed.

3-6

, . . - -- - C ASSETTE 1

. . - --

CASSETTE 2

--~

B
B~

R ECOH O LO NTR t .
~· . -

fAi:.I

r

...

i •
_

•WO

'~ HAAA ( TfR

'~



0

~~~
~ ~

~ l I Il l ~

tJ:lctQR

STOP

0

q' "

TA P( FORMAT

I

I

I

~

UNl:

I

I

C FF

LOC Al

KE 'V8QA q 0

I

PLA.V8AC"-

811 1

Figure 3-3.

/'"'

~=Al

..,.,"'"

·' "'•

e. RASE

OH

~

PAINTtq

BIT 8

733 ASR Module Assembly (Upper Unit) Switch Panel

I AP( St'I(- .J P

0

0
Side I

\\ Rll E ! AS fl) R SHH 2
~Alff

I AB r(lR SIDE I

Figure 3-4.

3-7

Tape Tabs

3.2.3.4 Dump to Paper Tape
The terminal is assumed to be an ASR 33 teletypewriter. The following steps should be
completed carefully to avoid punching stray characters:
(1)

Enter the command as described in paragraph 3.2.3.1. Do not answer the
"READY YIN" query yet.

(2)

Change the teletype mode from ON LINE to LOCAL.

(3)

Turn on the paper tape punch and press the RUBOUT key several times, placing
RUBOUTS at the beginning of the tape for correct-reading/program-loading.

(4 )

Turn of f the paper tape punch, and reset the teletype mode to LINE. (This is
necessary to prevent punching stray characters).

(5)

Turn on the punch and answer the "READY YIN" query wi th "Y". The Y will not
be echoed .

(6)

Punching will begin. Each file is followed by 60 rubout characters. When
these characters appear (identified by the constant punching of all holes)
the punch must be turned off.

3.2. 4
3.2.4.1

EXECUTE COMMAND (E)
Syntax

E

3. 2 .4 . 2 Description
The E command causes task execution to begin at current values in the Workspace
Poin ter and Program Counter .
Example:
3.2.5
3.2.5.1

E

FIND COMMAND (F)
Syntax
F < start address > l

t< stop address > {

I< value > l (CR )

3.2 . 5.2 Description
The cont e nts of memory locations from "start address" to "stop address" are compared
to "value". The memory addresses whose contents equal "value" are printed out. Default
value for start address is O. The default for "stop address" is 0. The default for
"value" is O.
If th e t erminat ion character of "value" is a minus sign, the search will be from
"start address" to "stop address" for the right byte in "value". If the termination
character i s a carriage return, the search will be a word mode search .

3-8

EXAMPLE:
7F

1) •

0 oo.:.

2 0 F FF F

- - - - CARRIAGE RETURN ENTERED

01) (I(
(I 0 1 2

(1 1) 16
7 F I)

21) FF - - - - - - MINUS SIGN ENTERED

(1(1(16

(11)(1;-'
(1 (11)(
(1 (11) [1
01)1 2
I) (1 1 ::::

0 0 1t::.
7

(I 01

3. 2.6

HEXADECIMAL ARITHMETIC (H )

3.2 . 6.1

Syntax

H < number 1 > {

.< number 2 >< (CR) >

3. 2 . 6 . 2 Description
The sum and difference of two hexadecimal numbers are output.
EXAMPLE:
7 H 2 (I (I , 1 (I (I
H 1 + H 2 =11 ;: l_I u

3 . 2.7

CARRIAGE RETURN ENTERED

H 1 - H.::: =u 1 '-' I.I

LOAD MEMORY FROM CASSETTE OR PAPER TAPE (L)

3.2 . 7.1

Syntax

L < bias >< (CR ) >

3. 2 . 1.2 Description
Data in 990 object record format (defined in Appendix G) is loaded from paper tape or
cassette into memory. Bias is the relocation bias (starting address i n RAM). Its
default is 0 16 . Both relocatable and absolute data may be loaded into memory with the
L command . After the data is loaded, the module identifier (see tag 0 in Appendix G)
is printed on the next line.
3. 2.1 . 3 Loading From Texas Instruments 733 ASR Terminal Cassette
The 733 ASR must be equipped with automatic device control (ADC). The f oll owing
procedure is carried out prior to executing the L command:
(1)

Insert the cassette in one of the two transports on the 733 ASR
in Figure 3-2) .

(2)

Place the transport in the playback mode.

3- 9

~cassette

1

(3)

Rewind the cassette.

( 4)

Load the cassette.

(5)

Set the KEYBOARD, PLAYBACK, RECORD, and PRINTER LOCAL /L{NP. switches to LINE .

(6)

Set the TAPE FORMAT switch to LINE.

(7)

Loading will be at 1200 baud.

Execute the L command.
3.2.7.4 Loading From Paper Tape (ASR33 Teletype)
Prior to executing the L command, place the paper tape in the reader and position the
tape so the reader mechanism is in the null field prior to the file to be loaded.
Enter the l oad command. If the ASR33 has ADC (automatic device control), the reader
will begin to read from the tape. If the ASR33 does not have ADC, turn on the reader,
and loading will begin.
Each file is terminated with 60 rubouts. When the reader reaches this area of the
tape, turn it off. The loader will then pass oontrol to the command scanner .
The user program counter (P) is loaded with the entry address if a 1 tag or a 2 tag is
found on the tape.
EXAMPLE:
'L
I) I) I) ( 1 - - - -F' ~· D1:; ~· t=H·l

3.2.8

CARRIAGE RETURN ENTERED
PROGRAM ID FROM TAPE

MEMORY INSPECT/CHANGE, MEMORY DUMP (M)

3.2.8 . 1 Syntax
•
Memory Inspect/Change Syntax
M < s tart address > ~ ·' ;< star addre~s ~.< (CR) >

•

Memory Dump Syntax
M < address >< (CR) >

3.2 . 8.2 Description
Memory inspect/change "opens" a memory location, displays it, and gives the option of
changing the data in the location. The termination chara cter causes the following:
•

If a carriage return, control is returned to the command scanner.

•

If a space, the next memory location is opened and displayed.

•

If a minus sign, the previous memory location is opened and displayed.

If a hexadecimal value is entered before the termination character, the displayed
memory location is updated to the value entered.
3- 10

Memory dump address directs a display of memory contents from "start address" to
"stop address". Each line of output consists of the address of the first data word
output followed by eight data words. Memory dump can be terminated at any time by
typing any character on the keyboard.
(

EXAMPLF.S :
(1)

? M FE I) I)
FEOO=FFOF
FE 02= (I 012
FE 04= 0311
FE 02=FFFF
FE 04= er:;: 11
FE 06= (I 032

CARRIAGE RETURN ENTERED

FFFF - -

NEW CONTENTS ENTERED
MINUS SIGN ENTERED
NEW CONTENTS

EEAA-

CARRAGE RETURN ENTERED

(2)

;:o
002o=ou20
"C M 20

f1(1 ::: O= 1_11) (1

3.2.9

0030

oouu

oon5

l

UUiU

UDO(I

UOOO

UU~4

INSPECT/CHANGE USER WP, PC, AND ST REGISTERS (R)

3.2.9.1

Syntax
R < (C R) >

3. 2 .9.2 Description
The user workspace pointer (WP), program counter (PC), and status register (ST) are
inspected and changed with the R command. The output letters WP, PC, and ST identify
the values of the three principal hardware registers passed to the TMS 9900
microprocessor when a B, E, or S command is entered. WP points to the workspace
register area, PC points to the next instruction to be executed (Program Counter), and
ST is the Status Register contents.
The termination character causes the following:
•

A carriage return causes control to return to the command scanner.

•

A space causes the next register to be opened.

Order of display is W, P, S.

3-11

EXAMPLES:
( 1)
7

F:

Iii= (I (12 l_I

1 (I 0 -

SPACE ENTERED

F'= 1_11) (I (I

2 Cl ( 1

CARRIAGE RETURN ENTERED

-

(2)
-;:·F'
Iii= l~I ~ 1~1 1:1 : - - 7...--- SPACE ENTERED

F'= IJC: 1_11_1 •-- --'·
: =I) I) 1·1 ( 1 - - --

3 .2.10
3.2.10.1

-

SPACE OR CARRIAGE RETURN ENTERED

EXECUTE IN SINGLE STEP MODE (S)
Syntax

s
3 . 2. 10. 2 Description
Each time the S command is entered, a s ingle instruction i s executed at the address in
the Program Counter, then the contents of the Program Counter, Workspace Poin ter, and
Status Registe r (after execution) are printed out. Successive instructions can be
executed by repeated S commands. Essentially, this command e xe c ut es one in struction
then returns control t o the monitor.

EXAMPLE:
-;:·F·

l.1l=FFC6
F'=FE!O
:·= 26 (IA

? s.

~/

FE fl f1 \
- - '

FFC6
FFC6
FFC6
FFC6

~

SPACES ENTERED
WORKSPACE POINTER

~ PROGRAM COUNTER
FE (12__......, :::t=. OA-- STATUS REGISTER
FE04
86 0A
FE o:::
:::6 0A
:::60A
FEOC

NOTE
Incorrect results are obt ai ned when the S c ommand
causes execution of an XOP instr uction (see paragraph
4.6.9) in a user program. To avoid this problem, use
the B command (breakpoint) to the XOP vectors to
execute any XOP ' s in a program (ra ther than the S
command) with the ap propri ate XOP parame ter
previously loaded into R11 of the XOP workspace.

3-12

3.2.11

TI 733 ASR BAUD RATE (T)

3.2.11.1

Syntax

T
3.2~11.2
Description
The T command is used to alert TIBUG that the terminal being used is a 1200 baud
terminal which is not a Texas Instruments' 733 ASR (e.g., a 1200 baud CRT). To revoke
the T command, enter it again.

3.2.11.3 Use
T is used only when operating with a true 1200 baud peripheral device . Note that T is
never used when operating at other baud rates.
In TIBUG the baud rate is set by measuring the width of the character 'A' input from a
terminal. When an 'A' of 1200 baud width is measured, TIBUG is set up to automatically
insert three nulls for every character output to the terminal. These nulls are
inserted to allow correct operation of the TM 990/101M with Texas Instruments 733ASR
data terminals.
3.2.12

INSPECT/CHANGE USER WORKSPACE (W)

3.2.12.1

Syntax

W [REGISTER NUMBER] < (CR) >

3.2.12.2 Description
The W command is used to display the contents of all workspace registers or display
one register at a time while allowing the user to change the register contents. The
workspace begins at the address given by the Workspace Pointer.
The W command, followed by a carriage return, causes the contents of the entire
workspace to be printed. Control is then passed to the command scanner.
The W command followed by a register number in hexadecimal and a carriage return
causes the display of the specified register's contents. The user may then enter a new
value into the register by entering a hexadecimal value. The following are termination
characters whether or not a new value is entered:
•

A space causes display of the next register.

•

A minus sign causes display of the previous register.

•

A carriage return gives control to the command scanner .

EXAMPLES:
( 1)
7 111 - -- - - - - - CARRIAGE RETURN ENTERED

F:O=F'?42
P:::=FAAO

F' 1 =(I (1:34

F"?= :::.:.I) (I

F'2=FA2A
f<·A= OE Ht·

F' :::= U 02 U
Pf:= 0 0 01)

3-13

fN=F.E:SE
f<:C= 01C0

P5= oo·::i:::
F'D= 0 0:::4

F.'6= 1 ;: (I (I
F:'E==FA3 0

F?== 1.1084
F-:F ==C.6 0 0

(2)
·;·1.1.I 2 - - - - - - - C A R R I A G E RETURN ENTERED

R2= 02:=:4
F::3= 0 01 I:
R4= 16 o:=:
F.:5=0460
F.:6=F:=: (I (I

:~:456 ~

: : ::F ISPACE ENTERED
(I

CARRIAGE RETURN ENTERED

3.3 USER ACCESSIBLE UTILITIES
TIBUG contains seven utility subroutines that perform I/O functions as listed in Table
3-3. These subroutines are called through the XOP (extended operation) assembly
language instruction . This instruction is covered in detail in paragraph 4.6.9. In
addition, locations for XOP's 0 and 1 contain vectors for utilities that drive the TM
990/301 microterminal, and XOP 15 is used by the monitor for the breakpoint facility.
Table 3-3.

XOP

I

User Accessible Utilities

FUNCTION

8

Write 1 Hexadecimal Character to Terminal
Read Hexadecimal Word from Terminal
Write 4 Hexadecimal Characters to T erm inal
Echo Character
Write 1 Cha;acter to Terminal
Read 1 Character from Terminal
Write Message to Terminal

9
10
11

12
13
14

I

PARAGRAPH

3 3.1
3 .3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7

NOTE
All characters are in ASC II code.

1.

NOTES
Initially, TIBUG will conduct I/O through the TMS
9902 connected to connector P2: in this mode,
0080 15 is in TIBUG's R12 located at memory addr es s
(M.A.) FFDE 15. To change this configuration, change
the contents of M.A. FFDE 16 before executing the
I/O XOP . For example, to use the auxiliary TMS 9902
at P3, change M.A. FFDE 16 contents to 0180 16 . CRU
programming is discussed in paragraph 5 .5.

2.

The write character XOP (XOP 12) activates the
REQUEST TO SEND signal of the TMS 9902 . This signal
is never deactivated by TIBUG so that modems may be
used.

3.

Most o f the XOP format examples herein use a
register for the source address, however, all XOP's
can also use a symbolic memory address or any of
the addressing forms available for the XOP instruction.

3-14

3.3.1

WRITE ONE HEXADECIMAL CHARACTER TO TERMINAL (XOP 8)
Format:

XOP

Rn,8

The least significant four bits of user register Rn are converted to their ASCII coded
hexadecimal equivalent (0 to F) and output on the terminal. Control returns to the
instruction following the extended operation .
EXAMPLE:

~

Assume user register 5 contains 203c 16 . The assembly language (A.L.) and machine
language (M.L.) values are shown below.

A .L .

XOP

RS,8

0

2

SEND 4 LSS'S OF RS TO TERMINAL

3

4

5

6

7

8

9

10

11

12

13

14

15

ML. l~~~~o~~~o~~~-,-'~,~-o~~o~-o~l_o~~o·~'~o~-1~~0~-!~J

> 2E05

Terminal Output : C

3.3.2

READ HEXADECIMAL WORD FROM TERMINAL (XOP 9)
Format:

XOP
DATA

Rn,9
NULL

DATA

ERROR

(NEXT INSTRUCTION )

ADDRESS OF CON TINUED EXECUTION IF
NULL IS ENTERED
ADDRESS OF CO NTINUED EXECUTION IF
NON HEX NO ENTERED
EXECUTION CONTINUED HERE IF VA LI D HEX
NUMBER AND TERMINATOR ENTERED

Binary representation of the last four hexadecimal digits input from the terminal is
accumulated in user register Rn. The termination character is returned in register
Rn+1. Valid termination characters are space, minus, comma, and a carriage return.
Return to the calling task is as follows:
•

If a valid termination character is the only input, return is to the memory
address contained in the next word foll owing the XOP instruction (NULL
above).

3-15

•

If a non-hexadecimal character or an invalid termination character is input,
control returns to the memory address contained in the second word following
the XOP instruction (ERROR above).

•

If a hexadecimal string followed by a valid termination character is input,
control returns to tile word following the DATA ERROR statement above.

EXAMPLE
A. l.

M . L.
M.A .

XOP

R6,9

READ HEXADECIMAL WORD INTO R6

DATA

'• FfCO

RETURN ADDRESS, IF NO NUMBER

DATA

, FFC6

0
FFBO 0

1
0

2
1

RETUR N ADDRESS, IF ERROR
4
1

3
0

5
1

6
1

8
0

7

0

9
1

FFB2 1
FFB4 1

10
0

11
0

12
0

13
1

14
1

0

0

0

0

0

0

0

? I 111,

1

0

0

ri

c· u

0

f.

, · i,

If the valid hexadecimal character string 12C is input from the terminal foll owed by a
ca rriage return, control returns to memory address (M.A.) FFB6 16 with register G
containing 012c 16 and regi s ter 7 containing ODOo 16 .
If the hexadecimal character string 12C is input from the terminal followed by an
ASCII plus (+) sign, control returns to location FFC6 16 . Registers 6 and 7 are
returned to the calling program without being altered. "+" is an invalid termination
character.
If the only input from the terminal is a carriage return, register 6 is r e turned
unaltered while register 7 contains 0000 16 . Control is returned to address FFC0 16 .

3.3.3 WRITE FOUR HEXADECIMAL CHARACTERS TO TERMINAL (XOP 10)
Format:

XOP

Rn, 10

The four-digit hexadecimal representation of the contents of user register Rn is
output to the terminal. Control returns to the instruction following the XOP ca ll.
EXAMPLE:
Assume r egister 1 contains 2C46 16.
A.L.

XOP

R1, 10

WRITE HEX NUMBER

0

2

3

4

5

6

7

8

9

10

11

12

13

14

15
· 2E81

Terminal Output: 2C46

3-16

1.3.4

ECHO CHARACTER (XOP 11)

Format :

XOP

Rn, 11

This is a combination of XOP's 13 (read character) and 12 (write character). A
character in ASCII code is read from the terminal, placed in the left byte of Rn, then
written (echoed back) to the terminal. Control returns to the instruction following
the XOP after a character is read and written . By using a code to determine a
character string termination, a series of characters can be echoed and stored at a
particular address :

CLR
LI
XO P
Cl
JEQ
MOVB
JMP

3. 3.5

R2
Al, > FEOO
R2. 11
R2, -..... 0000

$•6
R2 , 'R 1+
s 10

CLEAR R2
SET STORAGE ADDRESS
ECHO USING R2
WAS CHARACTER A CR7
YES. EXll ROUTINE
NO. MOVE CHAR TO STORAGE
REPEAT XOP

WRITE ONE CHARACTER TO TERMINAL (XOP 12)

Format :

XOP

Rn, 12

The ASCII character in the left byte of user register Rn is output to the terminal.
The right byte of Rn is ignored. Control is returned to the instruction following the
call.

3.3.6

READ ONE CHARACTER FROM TERMINAL (XOP 13)
Format:

XOP

Rn, 13

The ASCII representation of the character input from the terminal is placed in the
left byte of user register Rn. The right byte of register Rn is zeroed. When this
utility is called, control is returned to the instruction following the call only
after a character is input.

3 .3.7

WRITE MESSAGE TO TERMINAL (XOP 14)
Format:

XOP

@MESSAGE, 14

MESSAGE is the symbolic address of the first character of the ASCII character string
to be output. The string must be terminated with a byte containing binary zeroes.
After the character string is output, control is returned to the first instruction
following the call.

3-17

Assuming the following program:
MEMORY
ADDRESS

OPCODE

(Hex)

(Hex)

FEOO
FE02
FE04

2FAO
FEEO

XOP

FEEO
FEE2
FEE4

5445
5354
00

TEXT 'TEST'

A .L. MNEMONIC

@> FEE0,14

BYTE 0

During the executio n of this XOP, the character string 'TEST' is output on the
terminal and control is then returned to the instruction at location FE04 16 . TEXT is
an assembler directive to transcribe characters into ASCII code.
3.4 TIBUG ERROR MESSAGES
Several error messages have been included in the TIBUG monitor to alert the user to
incorrect operation. In the event of an error, the word 'ERROR' is output followed by
a single digit representing the error number.
Table 3-4 outlines the possible error conditions.
Table 3-4.

TIBUG Error Messages

ERROR

CONDITION

0

Invalid tag detected by the loa der.
Checksum error detected by the loader
Invalid termonatoon c haoacter detected.
Null input fie ld detected by the dump routine.
Invalid command entered.

1

2
3
4

In the event of errors 0 or 1, the program load process is terminated . If the program
is being input from a 733 ASR, possible causes of the errors are a faulty cassette

tape or dirty read heads in the tape transport. If the terminal device is an ASR33,
chad may be caught in a punched hole in the paper tape. In either case repeat the load
procedure.
In the event of error 2, the command is terminated. Reissue the command and parameters
with a valid termination character.
Error 3 is the result of the user inputting a null field for either the start address,
stop address, or the entry address to the dump routine. It also occurs if the ending
address is less than the beginning address. The dump command is terminated. To correct
the error, reissue the dump command and input all necessary parameters.

3-18

SECTION 4
TM 990/101M INSTRUCTION EXECUTION

,
4. 1 GENERAL
This section covers the instruction set used with the TM 990/101M including assembly
language and machine language. This instruction set is compatible with other members
of the 990 family.
Other topics include:
•

Hardware and software registers (paragraphs 4.3 and 4.4).

•

CRU addressing (paragraph 4.7)

•

Interrupts (paragraph 4.10)

The TM 990/101M microcomputer is designed for use by a variety of users with varying
technical backgrounds and available support equipment. Because a TM 990/101M user has
the capability of writing his programs in machine language and entering them into
memory using the TIBUG monitor, emphasis is on binary/hexadecimal representations of
assembly language statements. The assembly language described herein can be assembled
on a 990 family assembler. If an assembler is used, this section assumes that the user
will be aware of all prerequisites for using the particular assembler .
It is also presumed that all users learning this instruction set have a working
knowledge in :

l

•

ASCII coded character set (described in Appendix C) .

•

Decimal / hexadecimal, binary number system (described in Appendix D).

Further information on the 990 assembly language is provided in the Model 990
Com uter/TMS 9900 Microprocessor Assembl Lan ua e Pro rammer's Guide (PIN
9 3 1-9701 .
4.2 USER MEMORY
Figure 4-1 shows the user RAM space in memory available for execution of user
programs . Note that the memory address value is the number of bytes beginning at 0000;
thus, all word addresses are even values from 0000 to FFFE 16 .
Programs in EPROM's can be read by the processor and executed; however, EPROM memory
cannot be modified (written to). Therefore, workspace register areas are in RAM wher e
their values can be modified. Restart vectors and TIBUG workspaces utilize the last 40
words of RAM memory space as shown in Figure 4-1.

~

'r

4.3 HARDWARE REGISTERS
The TM 990/101M uses three major hardware registers in executing the instruction set:
Program Counter (PC), Workspace Pointer (WP), and Status Register (ST).
4.3.1 PROGRAM COUNTER (PC)
This register contains the memory address of the next instruction to be executed.
After an instruction image is read in for interpretation by the processor, the PC is
incremented by two so that it "points" to the next sequential memory word.

4-1

BYTE 0000

i=

BYTE 0001

MEMORY
ADDRESS

) INTERRUPT VECTORS

OCMO

XOP VECTORS

DEDICAT ED
MEMORY

007E

rOIO

TIBUG
MONITOR

07FE
0800
EPROM
TMS 2708
1KX16

FEA
........
INTERRUPT

OFFE
1000

AND XOP LINK AREA
........

FFAE

'

FFBO
FFF -.,,,---~~~~.,.._~~~~~---J

-

•
•

........

•

......

'

........

.......

EFFE
FOOO
........

......

'
.......

-..... .......

RAM
.......

-

....... .......

-..... .......

USER
AVAILABLE
RAM

....... ......

.......

.......

-..... -.....

.........

FIRST
1024
WORD
EPROM

EPROM
TMS 2708
1KX16

F7FE

TMS4045
1K X 16

.......

'

FBOO

....... .......

SECOND

l 1024

WORD

\ EPROM•

l
)

l
\

MEMORY
EXPANSION

SECOND
1024
WORD
RAM•

RAM

FIRST

TMS4045

1024
WORD

1K X 16 ' .....
-----------

RAM

FFFE

RESERVED 40 WORDS FOR
TIBUG MONITOR WORKSPACE
FILES AND RESET VECTORS
AT FFFC AND FFFE

NOT SUPPLI ED WITH
TM 990/101M-1 OR -2

DEDICATED MEMORY
ADDRESS (HEX)

PURPOSE

0000-00JF

Vectors for interrupts 0 (RESTART) to 15

0040-0047

Vectors for XOP's 0 and 1 (Microterminal 1/0)

0048-005F

V ect ors for XO P's 2 to 8 (Programmed by User)

0060-007F

Vectors for XOP's 8 t o 15 (TI BUG u t il ities)

0080-07FF

TIB UG monitor

FEA8-FFAF

Interrupt and XOP l i nking area

FFBO-FFFB

Four overlapping monitor work spaces

FFFC-FFFF

Restart (l oad) vectors
BOARD MEMORY M AP

ADDRESS (HEX)

MEMORY TYPE

ENABLE SIGNAL

0000-07FF"

ROM (2708)

ROM1

0000-0FFP

ROM (27 16)

ROM1

Main EPROM, blank TMS 27 16

0800-0FFF •

ROM (2708)

ROM2

Expansion EPROM
Expansion EPRO M, blank TMS 2716

COMM ENT
TIBUG monitor area

1000-1FFF "

ROM (2716)

ROM2

FOOO-F7FF

RAM (4045)

RAM2

Expansion R A M

F800·FFFF

RAM (4045)

RAM 1

Standard RAM

•EPA OM p airs (e.g. , U42, U44 and U43, U45) m ust be o f the same type - both TMS 2708's or both TMS 2716's. The
two EPAOMpair s, main and expa nsion, may be of different type if the appropriate jumper settings are made. T his
situation means selecting t he 27 16 m emory m ap jumper option.

Figure 4-1.
4-2

Memory Map

4.3.2 WORKSPACE POINTER (WP)
This register contains the memory address of the register file currently being used by
the program under execution. This workspac e consists of 16 contiguous memory words
designated registers 0 to 15. The WP points to register 0. Paragraph 4.4 explains a
workspace in detail.
4 .3.3 STATUS REGISTER (ST)
The Status Register contains relevant information on preceding instructions and
current interrupt level. Included are:
•

Results of logical and two's complement comparisons (many instructions automatically compare the results to zero).

•

Carry and overflow.

•

Odd parity found (byte instructions only).

•

XOP being executed.

•

Lowest priority interrupt level that will be currently recognized by the
processor.

The Status Register is shown in Figure 4-2.

0

L>
l '
A ,,
EO
C

A>

2

3

4

5

6

EO

C

OV

OP

)(

LOGICALLYGREATERTHAN
ARITHMETICALLY GREATER THAN
EQUAL
CARRY

8

7

9

10

11

12

13

14

15

INTERRUPT MASK
OV
OP
X

OVERFLOW
ODD PARITY
XOP BEING EXECUTED

A0001421

Figure 4-2.

Status Register

4.3 . 3.1 Logical Greater Than
This bit contains the result of a comparison of words or bytes as unsigned binary
numbers. 'f hus the most significant bit (MSB) does not indicate a pos iti ve or negative
sign . fhe MSB of words being logically compared represents 2 15 (32,768), and the MSB
of bytes being logically compared represents 27 (128) .
4.3.3. 2 Arithmetic Greater Than
The arithmetic greater than bit contains the result of a comparison of words or bytes
as two's complement numbers. In this comparison , the MSB of words or byt es being
compared represents the sign of the number, zero for positive, or one for negative.

4-3

4.3.3.3 Equal
The equal bit is set when the words or bytes being compared are equal.
4.3.3.4 Carry
The carry bit is set by a carry out of the MSB of a word or byte (sign bit)
during arithmetic operations. The carry bit is used by the shift operations to
store the value of the last bit shifted out of the workspace register being
shifted.
4.3.3.5 Overflow
The overflow bit is set when the result of an arithmetic operation is too
large or too small to be correctly represented in two's complement
larithmetic) representation. In addition operations, overflow is set when the
MSB's of the operands are equal and the MSB of the result is not equal to the
MSB of tne destination operand. In subtraction oper a tions, the overflow bit is
set when the MSB's of the operands are not equal, and the MSB of the result is
not equal to the MSB of the destination operand. For a divide operation, the
overflow bit is set when the most significant sixteen bits of the dividend (a
32-bit value) are greater than or equal to the divisor. For an arithmetic left
shift, the overflow bit is set if the MSB of the workspace register being
shifted changes value. For the absolute value and negate instructions, the
overflow bit is set when the source operand is the ma ximu m negative value,
800016·
4.3.3.6 Odd Parity
The odd parity bit is set in byte operations when the parity o f the result is
odd, and is reset when the parity is even . The parity of a byte is odd when
the number of bits having a value of one is odd; when the number of blts
having a value of one is even, the parity of the byte is even .
4.3.3.7 Extended Operation
The extended operation bit of the Status Register is set to one when a
software implemented extended operation (XOP) is initiated .
4.3.3.8 Status Bit Summary
Table 4-1 lists the instruction set and the stat us bits affected by each
instruction.
4.4 SOFTWARE REGISTERS
Registers used by programs are contained in memory. This speeds up contextswitch time because the content of only one register (WP hardware register)
needs to be saved instead of the entire register file. The WP, PC, and ST
register contents are saved in a context switch .
A workspace is a contiguous 16 word area; its memory location can be
designated by placing a value in the WP register through software or a
keyboard monitor command . A program can use one or several workspace areas,
depending upon register requirements .
More than three-fourths of the instructions can address the workspace register
file; all si1ift instructions and most immediate operand instructions us e
workspace registers exclusively .
Figure 4-3 is an example of a workspace file in high-order memory (RAM) . A
workspace in ROM would be ineffective since it could not be written into. Note
that several registers are used by particular instructions.

4-4

Table 4-1.

MNEMONIC
A
AB
ABS
Al
ANDI
B
BL
BLWP

c
CB
Cl
CLR

r

•

L'

x
x
x
x
x

x
x
x

coc
czc

-

DEC
DECT
DIV
IDLE
INC
INCT
INV
JEO
JGT
JH
JHE
JL
JL E
JLT
JMP
JNC
JNE
JNO
JOC
JOP

x
x

IA '

x
x
x
x
x

-

-

-

-

-

-

x
x
x
x
x
-

x
x
x

x
x
x

-

-

x
x

-

x
x
x
x

-

x
x
x

x
x
x

-

-

-

-

-

-

-

c
I

-

-

ea

-

-

x
x
x

I

Status Bits Affected by Instructions

-

-

-

-

x
x
x
x

-

I ov
x
x
x
x

-

-

I OP

Ix

x

-

-

-

-

-

x

-

-

-

-

-

-

x
x

x
x
x

-

x
x

-

--

-

-

x
x

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

MNEMONIC
LDCR
LI
LIMI
LREX
LWPI
MOV
MOVB
MPY
NEG
ORI
RSET
RTWP

s
SB
SBO
SBZ
SETO
SLA

soc
SOCB
SRA
SAC
SAL
STCR
STST
STWP
SWPB

-

szc

-

SZCB
TB

-

-

-

-

L --. I A '

I EQ

c

-

I

I OP

-

-

-

-

-

x
x

-

-

-

x
x

x
x

x
x

-

-

x

x
x

x
x

x
x

-

x
-

-

-

-

-

-

x
x
x
-

x
x
x
x
x
x
x

-

-

-

x

x
x
x

-

-

-

-

-

-

-

x
x
x
x
x
x
x

x
x
x
x
x
x
x

-

-

-

x
x

x
x

x
x
x

x

-

-

2

2

XOP
XOR

2

2

x

x

-

2
2

x

1

-

-

-

-

x
x
x

x

x

x
x

x

x

-

-

x
x
x

-

-

x

ov

x
x

-

x
x

I

x

-

x

-

-

-

x

I

-

-

-

-

x

-

-

-

-

-

-

x

-

-

-

-

-

-

x

-

-

-

-

-

-

-

1

-

-

-

-

-

-

2
2

2
2

2

2

-

2

-

2
-

-

x

-

-

NOTES
When dn LDCR or STCR 1nstruct1on transfers eight bits or less, the OP bit is set or reset as on byte 111structrons. Otherwise these
onstructrons do not af feet the OP bot.
2. The X 1nstruct1on does not affect any status bot. the 1nstruct1on executed by the X rnstruct ron sets status bits normally for that
1nstru ct1on. When an XOP 1nstructron rs implemented by software, the XOP brt rs set, and the subroutine sets status bots normally .

•

4-5

WP REGISTER

FCOO

MEMORY
ADDRESS
(HEXAOECIMALJ

..

12

I

FCOO

15
SHIFT
COUNT

RO

FC02

R 1

FC04

R2

FC06

R 3

FC08

R4

FCOA

R5

FCOC

R6

l'COE

R7

FC10

RB

FC12

R9

FC14

R 10

FC16

R 11

FC18

R 12

FC1A

R 13

FC1C

R14

FC1E

R 15

I

A0001422

Figure 4-3.

Workspace Example

4-6

l

l
l

l
~

BITS 12-15 USED BY
SHIFT INSTRUCTIONS

USED BY XOP'S ANO BRANCH RETURN
USED IN CRU ADDRESSING

USED IN CONTEXT
SWITCHING lXOP.
BLWP. RTWPJ

,.

4.5

INSTRUCTION FORMATS AND ADDRESSING MODES

Th e instructions used by the TM 990/101M are contained in 16-bit memory words and
require one, two, or three words for full definition. The first word (or the single
word) of an instruction will describe the purpose of the instruction while the
succeeding one or two words will be numbers that are referenced by the initial
instruction word. A word describing an instruction is interpreted by the Central
Processing Unit (CPU) by decoding the various fields within the 16 bits. These fields
are shown in Figure 4-4 for the 9900 instruction set which is also categorized into
nine instruction formats ~s shown in the figure.
In order to construct instructions in machine language, the programmer must have a
knowledge of the fields and formats of the instructions. This knowledge is often very
important in debugging operations because it allows the programmer to change bits
within an instruction in order to solve an execution problem.

t

The fields within an instruction word contain the following information (see Figure

4-4):
•

FORMAT

1

Op code which identifies the desired operation to be accomplished when this
instruction is executed.

0

f0 T

OP CODE

2
3
4

OP CODE
OP CODE
OP CODE

8
9

5

6

-----

E- OPCO~

-+ -

01

_I

WR

c

___[

11

12

14

13

SR
Ts
SIGNED DISPLACEMENT

I

Ts

SR

Ts

SR

c

R
Ts

OP CODE
OP CODE

N
OR

Ts

~I

SR

B
To

DESTINATION ADDRESS TYPE"

DR

DESTINATION REGISTER

Ts

SOURCE ADDRESS TYPE'

5R

SOURCE REGISTER

c

CRU TRANSFER COUNT OR SHIFT COUNT

R

REGISTER

N

NOT U SED

ADDRESS MODE TYPE
DIRECT REGISTER
INDIRECT REGI STER
PROGRAM COUNTER RELATIVE, NOT INDEXED (SR OR DR = 0)

10
11

{ PROGRAM COUNTER RELATIVE+ INDEX REGISTER (SR OR DR> OI
INDIRECT REGI STER . AUTOINCREMENT REGISTER

A0001423

Figure 4-4.

TM 990/101M Instruction Formats

4-7

GENERAL USE

15

-=i

-~

SR
NOT USED
--_ _R_ _

OPERATION CODE
BYTE INDI CATOR (1 BYTE)

•To OR Ts
()()

10

9

OR

To

OP CODE

..

8

7

OP CODE
OP CODE

5
6
7

4

3

2

_J

I

AAllHMETIC
JUMP
LOGICAL
CRU
SH IFT
PROGRAM
CONTHOL
IMMEOI /\ TE
MPV 01\1 XOP

•

B code which identifies whether the instruction will affect a full 16-bit
word in memory or an 8-bit byte. A one indicates a byte will be addressed,
while a zero indicates a word will be addressed.

•

T fields identified by TD for the destination T field and TS for the source
T field . The T field is a two-bit code which identifies which of five different a ddres s ing modes will be used (direc t register, indirect register,
memory address, memory address indexed, and indirect register autoincremente d). These mode s are described in detail in paragraphs 4. 5 .1 through
4.5.5. The source T field is the code for the source address a nd the destination T field is the code for the destination address. As shown in Figure
4-4, only five instruction formats use a T field.

•

Source and destination reg i s ter fields which contain t he number of the
r egister affected (0 through 15).

•

Displacement fields that contain a bias to be added to the program counter
in program counter relative addressing. This form of addressing is further
described in paragra ph 4.5 . 7 .

•

Fields that contain counts for i ndica ting the number of bits that will be
s hift ed in a shift instruction or the number of Communica tion Reg iste r Unit
(CRU) bits that will be addressed in a CRU instruc tion.

4 . 5 .1 DIRECT REGISTER ADDRESSING (T:00 2 )
In dir ect register addressing, execut ion involves data contained within one of the 16
workspace registers . In the first example in Figure 4-5, both the source and destination opera nd s are registers as noted in the assembly language example at the top of
the figure. Both T fields contain 00 2 to denote direct register addressing and their
associated register fields contain the binary value of the number of the register
affected. The 11 0 2 in the op code-field identifies this instruction as a mov e
instruction . Since the B field contai ns a zero , the data moved will be the full 16
bits of the register (a byte instruction addr essing a register would address the left
byte of the register). The instruction s pecifies moving the contents of register 1 to
register 4, thus cha nging the contents of register 4 to the same value as in register
1. Note that the assembly language statement is constructed so that the sour ce
register is the first item in the operand whil e the destina tion register is the second
i t e m in th e operand. This order is r e versed in the machine language cons truction with
the destination register a nd its T fie ld first a nd the source register and its T field
second .
4.5.2 INDIRECT REGISTER ADDRESSING (T=01 2 )
In indirect register addressing, the r egiste r does not contai n the data to be affected
by the instruction; instead, the regi s ter contains the address withi n memory of where
that data is stored. For example , the instruction in Figure 4-6 s pecifies t o move th e
contents of register 1 to the ad dress whi ch is contained in register 4 ( i ndirect
register 4). Instead of moving the value in r egi s ter 1 t o register 4 as was the c ase
in Figur e 4-5, the CPU must fi rst read in the 16-bit value in register 4 a nd use that
value as a memory address at which location the contents of regis ter 1 will be stored.
In the e xa mple, register 4 contains the value FD00 16. Thi s instruc t ion stores the
value in register 1 into memory address (M.A.) FD00 15 .
Indirect register addressing is s pecified in assembly language sourc e code by
preceding the register number with an asterisk(*). For example,
A *R1,*R2
mean s
to add the contents of the memory address in register 1 to the contents of the memory
addres s in register 2 , leaving the s um i n the memory address containe d i n regis ter 2.

4-8

In direct register addressing, the contents of a register are addres s ed. In indirect
register addressing, the CPU goes to the register to find out what memory location t o
address. This form of addressing is especially suited for r e peating an instruction
while accessing successive memory addre sses. For example, if you wished to add a
series of numbers in 100 consecutive memory locations, you could place the address of
the first number in a register, and exe cute an add indirect through that register,
causing the contents of the first memory address ( s ource operand) to be added to
another register or memory address (destination operand). Then you could increment the
contents of the register containing the address of the number, loop back to the add
instruction, and repeat the add, only this time you will be adding the contents of the
next memory address to the accumulator (destination operand). This way a whole string
of data can be summed using a minimum of instructions . Of course, you would have to
include control instructions that would signal when the entire list of 100 addresses
have been added, but there are obvious advantages in speed of operation, better
utilization of memory space, and ease in programming.

EXAMPLE 1

ASSEMBLY LANGUAGE:

MOV

MOVE THE CONTENTS OF R1 (SOU RC[) TO R4 (DESTINATION)

R1 ,R4

SOURCE OPE

RAN~~

DESTINATION OPERAND

MA CHINE LANGUA GE
0

2

3

I

4 S

T CODE FOR
DIRECT REGISTER
/

REGISTER4
-

~""'6--7...A..

9' ttJ 11 --; 2

8

---~
1_7)
_0_._o
_ .l._o__o__.l_o___o ~ro-

li.___
1

OP CODE

B

13

A ....
1_4___1..._5,

_o_l o_ o _o_

Ts

DR

To

T CODE FOR
DIRECT REGISTER
REGISTER 1

1J

-:- c101

SR

M.A .
RO

FCOO
FC02

Al

FC04

R2

FC06

R3

FCOB

R4

FCO.A

R5

PLACE Al BINARY
IMAGE IN R4

EXAMPLE 2

A SSEMBLY LANGUAGE:

A

R4,R10

ADD THE CONTENTS OF R4 (SOURCE) AND RlO (DESTINATION)

MACHINE LANGUAGE:
2

0

I

1

0
Of' CODE

1

3

I I
0

B

4

5

0

0
To

I

6

7

8

9

1

0

1

0

DR

I

10

11

0

0
Ts

12

I

13

0

14

15

0

0

SR

A0001424

Figure 4-5.

Di'rect Register
·
Addressing Example

4-9

I>

A284

ASSEMBLY LANGUAGE:

MOV

R1 ,•R4

MOVE THE CONTENTS OF RI (SOURCE) TO ADDRESS IN R4 (DESTINATION)

MACHINE LANGUAGE:
2

0

3

4

5

7

6

8

9

10

11

12

13

14

15

_1_ _ _o___._j_o____._j_0_ _1_..._
j _o_ _ _o_ _o~j~o--o~j_
o __
o __
o -~
1 j >eso1

._I

OPCODE

To

B

OR

SR

Ts

M.A .
FCOO

RO

FC02

R1

FC04

R2

FC06

R3

FCOB

R4

FCOA

RS

PLACE Rl BINARY
F 0 00

IMAGE IN MA FD001s
(INDIRECT R4)

FOOD
F D02

A0001425

Figure 4-6.

Indirect Register Addressing Example

A SSEMBLY LANGUAGE

MO V

R1 ,.. R4 1

MOVE THE CONTENTS OF RI TO ADDRESS CONTAINED IN R4,
INCREMENT ADDRESS BY 2

MACHINE LANGUA GE
0

~

1

2

3

4

5

0

I I

1

1

OP CODE

0

B

6

I

7

0

To

8

9

0

0

I

10

11

0

0

Ts

DR

BEFORE

~

0000

0000

FFOO

FF02

AAAA

0000

I

12

13

14

0

0

0

15

SR

M.A.
FCOO

RO

FC02

Al

FC04

R2

FC06

RJ

FCOB

R4

FFOO

A0001 427

Figure 4-7.

Indirect Register Autoincrement Addressing Example

4-10

,;. COOl

4.5.3 INDIRECT REGISTER AUTOINCREMENT ADDRESSING (T: 11 2 )
Indirect register autoincrement addressing is the same as indirect register addressing
(paragraph 4.5.2) except for an additional feature - automatic incrementation of the
register. This saves the requirement of adding an increment (by one or two)
instruction to increment the register being used in the indirect mode. The increment
will be a value of one for byte instructions (e.g., add byte or AB) or a value of t wo
for full word instructions (e.g., add word or A)

f

In assembly language , the register number is preceded by an asterisk (*) and followed
by a plus sign (+) as shown in Figure 4- 7. Note in the figure that the contents of
register 4 was incremented by two since the instruction was a move word (vs . byte)
instruction. If the example used a move byte instruction, the contents of the register
would be incremented by one so that successive bytes would be addressed (the 16-bit
word addresses in memory are always even numbers or multiples of two since each
contains two bytes). Bytes are also addressed by various instructions of the 990
instruction set.
Note that only a register can contain the indirect address .
4.5.4 SYMBOLIC MEMORY ADDRESSING, NOT INDEXED (T=10 2 )
This mode does not use a register as an addre ss or as a container of an address.
Instead , the address is a 16-bit value stored in the second or third word of the
instruction . The SR or DR fields will be a ll zeroes as shown for the destination
register field in the first example of Figure 4- 8. When the T field contains 102 . the
CPU retrieves the contents of the next memory location and uses these contents as the
effective address . In assembly language, a s ymbolic address is preceded by an at sign
(@) to differentiate a numerical memory address from a register number. All
alphanumeric labels must be preceded by an @ sign; numerical values preceded by an @
sign will be assembled as an absolute address (the TM 990/402 Line-By - Line Assembler
does not recognize alphanumeric symbols but does recognize absolute memory addres ses).

l

I

In the second example in Figure 4-8, both the source and destination operands are
symbolic memory addresses . In this case, the source add ress is the first word
following the instruction and the destination is the second word following the
instruction in machine language .
4.5.5 SYMBOLIC MEMORY ADDRESSING , INDEXED (T: 10 2 )
Note that the T field for indexed as well as non-indexed symbolic addressing is the
same <10 2 ). In order to differentiate between the two different modes, the associated
SR or DR field is interrogated; if this field is all zeroes (0000 2 ), non-indexed
addressing is specified; if the SR or DR field is grea ter than zero, indexing is
specified and the non- zero value is the index r egister number . As a result, register 0
cannot be used as an index register .
In assembly language , the symbolic address is followed by the number of the index
regi ster in parentheses. In the example in Figure 4-9, the source operand is
non-indexed symbolic memory addressing while the de stination operand is indexed
symbolic memory addressing . In this case , the destination effective address is the sum
of the FF02 16 value in the source memory address word plus the value in the index
register (0004 16 ). The effective address i n this case is FF06 16 as shown by the
addition in the left part of the figure.
Note that only symbolic addressing can be indexed.

4-11

EXAMPLE 1

ASSEMBLY LANGUAGE:

MDV

Rl ,@> FFOO

MOVE THE CONTENTS OF RI TO ADDRESS >FFOO
NOTE

The

>

si gn indic ates hexi dec1mal re prese ntat ion .

MACHINE LANGUAGE:
OPCODE
0
1st WORD

B
2

3

4

5

0

I I

1

0

0

Ts

DR

To

I

6

7

8

9

0

0

0

0

0

0

2nd WORD

I

SR

10

11

0

0

0

0

I

12

13

14

0

0

0

0

0

0

15
'- C801

0

' · FFOO

M.A.
RO
Rl
R2
PLACE RI BINARY
IMAGE IN
F EF E

MA > FFOO

F FOO

EX AMPLE 2

ASSEMBL Y LANGUAGE.

MDV

@> FFOA,@> FF08

MOVE THE CONTENTS OF > FFOA TO >FF08

MACHINE LANGUA GE:
OPCODE
0

B

Ts

DR

To

2

3

4

5

6

7

8

9

0

0

0

o

1st WORD

1

1

o

IoI

1

o

2nd WORD

1

1

1

1

1

1

1

1

0

3rd WORD

1

1

1

1

1

1

1

1

0

I

BEFORE

M.A.
FF08
FFOA
A0001428

Figure 4-8.

tEfil

~

10

I

SR
11

12

13

14

15

1

o 1 o

0

0

0

> C820

0

0

0

1

0

1

0

> FFOA (SOURCE)

0

0

0

1

0

0

0

> ff08 (DESTINATION)

AFTER

~

s

Direct Memory Addressing Example

4-12

ASSEMBLY LANGUAGE.

MOV

@>FFOO,@>FF02(Rl)

MOVE THE CONTENT S OF > FFOO TO > FF02 +RI CONTENTS

MACHINE LANGUAGE:

To

B

OP CODE
0

Ts

DR

2

3

4

5

I

6

7

8

9

0

0

0

1

SR

10

11

1

0

12

I

13

14

15

0

0

0

-C860

·FFOO (SOURCE )

1

1

o

I I
0

1

o

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

0

I

BEFORE

AFTER

0004

0004

0

---

>FF02 IDESTINATIONI

M .A .

RO
Al
R2

-

\

>FF02 ID)
0004 IR 11
>FF06
..._

~

\

\

\

FFOO

FFEE

FFEE

FF02

0000
0000
0000

0000
0000

FF04

......._______F F06

FFEE

A 00014 29

Figure 4-9.

Direct Memory Addressing , Indexed Exampl e

4 .5 . 6 IMMEDIATE ADDRESSING
This mode allows an absolute value to be specified as an operand; this value is used
in connection with a register contents or is loaded into the WP or the Sta tus Register
interrupt mask. Examples are shown below:
LI

R 2. 10 0

LO AD 100 INTO RE G I STER 2

Cl

R8,

COMPARE RB CON T ENTS TO > 100, RES U L TS IN ST

L WPI

100

> 3COO

SET WP TO MA > 3COO

4.5.7 PROGRAM COUNTER RELATIVE ADDRESSING
This mode allows a change in Program Counter contents, either an uncondi t ional change
or a change conditional on Status Register contents. Examples are shown below:
JM P

S •6

JUMP T O LOC AT I ON , 6 BYTES FORWARD

JMP

THERE

JUMP TO LOCATI ON L A BE L LED THER E

JEQ

S•4

IF ST EQ BI T

JMP

> 3E26

JUMP TOM A '> 3E26 IL INE ·BY ·LI N E ASS EMB L ER ONLY )

1 . JUMP 4 BYTES (M A• 4 1

The dollar symbol ($) means "from this address"; thus , $+6 means "this address plus 6
bytes."

4-13

4.6 INSTRUCTIONS
Table 4-2 lists terms used in describing the instructions of the TM 990 / 101M . Table
4-3 is an alphabetical list of instructions. Table 4-4 is a numerical list of
instructions by op code. Examples are shown in both assembly language (A.L.) and
machine language (M.L.). The greater-than sign (">)indicates hexadecimal.

Table 4-2.

Instruction Description Terms

TERM

DEFINITION

DR
DA

By l e indicator ( 1 - byte, 0 = word)
Bil count
Destination address register
Destinatio n address

I OP
LSB(n)

Immediate operand
Least significant (right most) b11 of (n)

M .A .

Memory Address

MSB (n)
N

Most significant Heft most) b11 o f (n)
Don't care

PC
Result
SR
SA

Program counter
Result o f opera ti on performed by instruct ion
Sou rce address register
Source address

ST
STn
To
Ts

Sta tus register
B it n o f sta tu s register
Destination address m odifier
Source address modifier

WR or R
WRn or Rn
(n)
a- b

Workspace register
Wurk space register n
Contents of n
a 1s transferred to b

(a) - b

Contents of a is t ransferred to be
Absolute value of n
Arithmetic addition
Arithmetic subtracti on

B

c

ln l
~

ANO
OR

Logical ANO
Logica l OR
Logical exc lusi ve OR
Logical complement of n
Hexadecimal value

G
n

>

4-14

- -- -ASSEMBLY
LANGUAGE
MNEMONIC

MACHINE
LANGUAGE
OP CODE

A
AB
ABS
Al
ANDI

AOOO
BOOO
0740
0220
0240

6
8
8

B
BL
BLWP

0440
0680
0400
8000
9000

6
6
6
1
1

0280
03CO
03AO
04CO
2000

8
7

2400
0600
0640
3COO
0340

3
6
6
9
7

c
CB
Cl
CKOF
CKON
CLR

.::=
I
_.
\Jl

coc
czc
DE C
DECT
DIV
IDLE

FORMAT
1
1

STATUS REG .
BITS
AFFECTED
04
0·5
02
0·4
0·2

RESULT
COMPARED
TO ZERO

x
x
x
x
x

02
0 2,5

INC
INCT
I NV
JEQ
JGT

0580
05CO
0540
1300
1500

6
6
6
2
2

JH
JHE
JL
JLE
JLT

lBOO
1400
lAOO
1200
1100

2
2
2
2
2

JMP
JNC
JNE
JNO
JOC

1000
1700
1600
1900
180 0

2
2
2
2
2

2
2
0 ·4
0·4
4

x
x

0·4
0-4
().2

-

PARAGRAPH

Add (w ord)
Add (by1e)
Absolute Value
Add Immed iate
AND Immedia te

46 1
4.6 .1
4.6.6
4.6 8
4 .6 8

Branch
Branch and Link (Rl l l
Branch , New Wor kspace Pointer
Compare (word)
Compar e (byte)

466
466
4 6.6
46 1
4.6 1

Compare lmmed1 a1 e
Use1 Defined
User Def ined
Clea r Operand
Compare Oles Cori espond1ng

4 6 .8
46 7
4.6 7
4.6.6
4.6 .3

Compare Zer oe~ Correspo nding
Decrement (by one)
Decrement (by two)
Divide
Computer Idle

4.6 .3
4 .6 6
4.6 6
4.6.3
4.6 .7

Increment (by one)
I ncrement (by two)
Invert (One's Complemen t )
Jump Equal (ST2 ~ 11
Jump Greater Than IST 1 ~ 1 ) , Arithmetic

4.6.6
4.6.6
4.6.6
4.6.2
4 6 .2

Jump
Jump
Jum p
Jump
Jump

High ISTO 1 and ST2=01. Logica l
High or Equal (STO or ST2 ~ 1) , Logical
Low (STO and ST2 ~0I , Logical
Low or Equal (STO=O or ST2= 1) , Logical
Less Than (ST 1 and ST2 - 0I , Arithmetic

4.62
4.6.2
4 .6 .2
4 6 .2
4 6 .2

Jump
Jump
Jump
Jump
Jump

Uncond itional
No Carry (ST3 ~ 01
N o t Equal I ST2 ~ Q)
No Overflow IST4 ~ 0)
On Carry (ST3 - 1 I

46 2
46 2
46 2
462
46 2

>--3
Ill
O"
f--'
(!)

.::=
I

w
H

02

7

6
3

INSTRUCTION

x
x
x

::i
(/J

cT
'"l

s:::

()

cT
I-'·

0
::l

{/)
(!)

cT

:t>
f--'

'O
::J"
Ill
O'
(!)

cT
I-'·
()

Ill

f--'

H

::i
0.
(!)

x

ASSEMBLY
LANGUAGE
MNEMONIC

02EO
0000
3800
0500

8
1
1
9
6

0260
0360
0380
6000
7000

8
7
7
1
1

0·2
12· 15
().15
0·4
().5

2
2
6
5

-

soc

1000
1EOO
0700
OA OO
EOOO

1

0·4
().2

SOCB
SRA
SAC
SAL
STCR

FOOO
0800
OBOO
0900
3400

1
5
5
5
4

0·2.5
0·3
0·3
0·3
0·2,5

STST
STWP
SWPB

02CO
02AO
06CO
4000
5000

8
8
6
1
1

-

1FOO
0480
2COO
2800

2
6
9
3

2

OR I
RSET
RTWP

s
.....

°'

-

2
4
8
8
7

LWPI
MOV
MOVB
MPY
NEG

I

FORMAT

STATUS REG .
BITS
AFFECTED

lCOO
3000
0200
0300
03EO

JO P
LDCR
LI
LIMI
LREX

.l:'

MACHINE
LANGUAGE
OP CODE

SB
SBO
SBZ
SETO
SLA

szc
SZCB
TB

x
XOP
XOR

cooo

0· 2.5

-

RESULT
COMPARED
TO ZERO

().2

Load Immedia te to Workspace Pointer
Move (word)
Move (byte)
Mu ltiply
Negate (Two's Complement)

4.6.8
4.6 .1
4.6 .1
4 6 .3
4.6 .6

OR Immediate
Reset AU
Return from Context Switch
Subtract (word)
Subtract (byte)

4.6.8
4.6 7
4.6 7
4.6 . 1
4.6. 1

Set CRU Bit to One
Set CRU Bit to Zero
Set Ones
Shift Left Arithmetic
Set Ones Corresponding (word)

4.6 2
4.6 .2
4.6 .6
4.6 .5
4 .6. 1

Set Ones Correspond ing (byte)
Sh ift Right (sign ex tended)
Shift Right Circular
Shift R ight Logical
Store From CRU

4 .6.1
4 .6 .5
4 .6.5
4 .6 .5
4 .6.4

x

Store Status Register
Store Workspace Po inter
Swap Bytes
Set Zeroes Corresponding (word)
Set Zeroes Corresponding (byte)

4 .6.8
4 .6 8
4.6 .6
4.6.1
4 .6 .1

x

Test CRU Bit
Execute
Extended Operation
Exclusive OR

4.6 .2
4.6 .6
4.6.9
4 .6 .3

x
x

x
x
x
x
x
x

-

x
x
x
x
x
x
x

x

6
().2

~

4.6.2
4 .6.4
4 .6 .8
4 6.8
4.6.7

-

0·2
0 ·2,5

PARAGRAPH

Jump Odd Parity (ST5 ~ 1 I
Load CRU
Load Immediate
Load I nterrupt Mask Immediate
Load and Execute

12· 15
12· 15
0·2
0·2,5

INSTRUCTION

Ill

O'

......
CD

.l:'

I

w
H

::s

.,

CQ

~

c:
Q

~
......

0

::s
en
CD

~

:z:,.

......

l'O

::r
Ill

O'

CD

~
......

Q

Ill

......

H

::s

0.
CD

><

("")

0

::s
Q

......

c:

0.
CD
0.

Table 4-4 .

Instruction Set, Numerical Index

MACHINE
LANGUAGE
OP CODE
(HEXA DECIMAL)

ASSEMBLY
LANGUAGE
MNEMONIC

0200
0220
0240
0260
0280

Al
ANDI
ORI
Cl

Load Immediate
Add Immediate
And Immediate
Or Immediate
Compare Immediate

8
8
8
8
8

0-2
0-4
0-2
0-2
0-2

02AO
02CO
02EO
0300
0340

STWP
STST
LWPI
LIMI
IDLE

Store WP
Store ST
Load WP Immediate
Load Int. Mask
Idle

8
8
8
8
7

-

0360
0380
03AO
03CO
03EO

RSET
RTWP
CKON
CKOF
LREX

Reset AU
Return from Context Sw.
User Defined
User Defined
Load & Execute

7
7
7
7
7

12-15
0-15

0400
0440
0480
04CO
0500

BLWP
B
CLR
NEG

Branch ; New WP
Branch
Execute
Clear to Zeroes
Negate to Ones

6
6
6
6
6

-

0540
0580
05CO
0600
0640

INV
INC
INCT
DEC
DECT

Invert
Increment by 1
Increment by 2
Decrement by 1
Decrement by 2

6
6
6
6
6

0-2
0-4
0-4
0-4
0-4

0680
06CO
0700
0740
0800

BL
SWPB
SETO
ABS
SRA

Branch and Link
Swap Bytes
Set to Ones
Absolute Value
Shift Right Arithmetic

6
6
6
6
5

-

0900
OAOO
OBOO
1000
1100

SAL
SLA
SAC
JMP
JLT

Shift Right Logical
Shift Left Arithmetic
Shift Right Circular
Unconditional Jump
Jump on Less Than

5
5
5
2
2

0-3
0-4
0-3

1200
1300
1400
1500
1600

JLE
JEQ
JHE
JGT
JNE

Jump o n
Jump on
Jump on
Jump on
Jump on

2
2
2
2
2

-

1700
1800
1900
1AOO
1800

JNC
JOC
JNO
JL
JH

Jump on No Carry
Jump on Carry
Jump on No Overflow
Jump on Low
Jump on High

2
2
2
2
2

1COO
1000
1 EOO
!FOO
2000

JOP
SBO
SB Z
TB

Jump o n Odd Paroty
Set CRU Bits t o Ones
Set CRU Bits t o Zeroes
Test CRU Bit
Compare Ones Corresponding

2
2
2
2

u

x

coc

INSTRUCTION

Less Than or Equal
Equal
High or Equal
Greater Than
Not Equal

4-17

FORMAT

3

STATUS BITS
AFFECTED

12-15

-

-

().2

0-2
0-3

-

-

-

-

-

-

2
2

Table 4-4.

MACHINE
LANGUAGE
OP CODE
(HEXADECIMAL

Instruction Set, Numerical Index (Concluded)

ASSEMBLY
LANGUAGE
MNEMONIC

2400
2800
2COO
3000
3400

czc

38CO
3COO
4000
5000
6000

MPV
D IV

INSTRUCTION

X OR
X OP
LOCR
STCR

szc
SZCB

s

7000
8000
9000
AOOO
BOOO

SB

c
CB
A
AB

cooo

MOV
MOVB

0000
EOOO
FOOO

soc
socs

FORMAT

STATUS BITS
AFFECTED

Compare Zeroes Corr esponding
Exclusive Or
Ex tended Operation
Load CRU
Store CRU

3
3
9
4
4

Multiply
0 1v1de
Set Ze: oes Corresponding (Word)
Set Ze1oes Co rresponding (Byte)
Subtrac t Word

9
9
1
1
1

4
0 2
0 2, 5
04

Subtract Byte
Compare Word
Compare Byte
Add Word
Add Byte

1

0 -5

1
1
1
1

02
0 2.5

Move Word
Move Byte
Set Ones Corresponding (Word)
Set Ones Correspond ing (Byte)

1

0-2
0·2,5
02
0 2 .5

2
0-2

6
0 2.5
0 2,5

04
05

1

1
1

4.6.1 FORMAT 1 INSTRUCTIONS
These are dual operand instructions with multiple addressing modes for source and
destinati on operands.
GENERAL FORMAT:
2

0
OP CODE

3

4

5

To

6

7

8
DR

9

10

11

Ts

12

13

14

15

SR

If B = 1, the operands are bytes and the operand addresses are byte addresses. If B
O, the operands are words and the operand addresses are word addresses.

4-18

=

MNEMONIC

OP CO DE

0

2

A

1 0

AB

1

0

1

c

1

0

0

B

r

MEANING

3

STATUS

TOO

AFFEC T E D

I

Arid

0

RESULT
COMPARED

Add hytes

I

Co mpare

0

B ITS

l)ESCRIPTION

Yes

04

ISAl•!DAI

Yes

0·5

ISAl•IOAI • IDAI

No

0-2

Compa re (SAi to IDA I

· IOA)

tnI

appropriate status hots
CB

1

0

0

1

0

0

0

1

'

Compare bytes

No

Move

Yes

0·2

ISA ) 'IDAI

Move bytes
Subtract

Yes
Yes

0 ·2,5
0 -4

(SA) - IOAI
IDA) - (SA ) _. IDA)

CompJ•e ISAI to IOAI .ond SPt

0·2.5

appropriate status h•ts

r.1ov

..

l\1Cv8

1

c;

0

1
1

SB

0

1

0
1

50C

0

SOCb

1

1

c;zc

()

1

Q

0

szrg

0

1

0

I

II
I

Subtract hytes

Yes

0·5

Set ones co rrespontt. ng

Yes

0 ·2

Set ones corresoondrng bytes

Yes

0 ·2,5

IDA) OR (SA ) -- IOAI

Set teroes correspondong

Yes

0 -2

IDA I AND (SA i - IOA)

Set 1eroes correspondonq hy tes

Yes

0 ·2.5

IDAI AND ISA) - IOA)

WAI - (SA) - IDAJ
OR ISA l
!DAI

(DA)

EXAMPLES

( 1)

ASSEMBLY LANGUAGE:

A

@> 100,R2

ADD CONTENTS OF MA > 100 & R2, SUM IN R2

MACHINE LANGUAGE:
2

0

0
0

(2)

0

0

3

4

5

6

7

0

0

0

0

0

0

0

0

0

8

9

10

0
0

0

0

11

12

13

14

15

0

0

0

0

0

~AOAO

0

0

0

0

0

>0100

15

ASSEMBLY LANGUAGE:

CB

R1 ,R2

COMPARE BYTE Rl TO R2, SET ST

MACHINE LANGUAGE:
0

2
0

0

3

4

5

6

7

0

0

0

0

8

9

10

,,

12

13

14

0

0

0

0

0

0

NOTE
In byte instruction des1gnat1ng a register, the left byte ts used. In the above
example, t he left byte 18 MSB's) of R 1 is compared to the left byre of R 2,
and the ST set to the results.

4-19

>9081

4.6.2

FORMAT 2 INSTRUCTIONS

4.6.2.1 Jump Instructions
Jump instructions cause the PC to be loaded with the value (PC +2 (signe d
displacement)) if bits of the Status Register are at specified values . Otherwise, no
operation occurs and the next instruction is executed since the PC was incremented by
two and now points to the next instruction . The signed displacement field is a word
(not byte) count to be added to PC. Thus, the jump instruction has a range of -128 to
127 words (-256 to 254 bytes) from the memory address fol lowi ng the jump instruction.
No ST bits are affected by a jump instruction.

GENERAL FORMAT:

0

3

2

4

5

6

7

8

OPCODE

MNEMONIC

- -

10

11

13

14

·-

0

1 2

J

4

5

6

7

JEQ

0

0

0

1 0

0

1

I

JGT

0 0

0

1 0

JH

0 0

0

1

JHE

0 0

0

1 0

MEANING

ST CONDITION TO CHANGE PC

Jump equal

ST2

I
1

1 0

1

Jump greater than

STl

0

1

1

J ump high

STO = 1 and ST2

1 0

0

Jump high or equal

STO

Jump low

STO = 0 anc1 ST2

Jump low or equal

STO = 0 or ST2

JL

0 0

0

I

1 0

1

JLE

0

0

0

1

0

1 0

JLT

0

0

0

1

0 0

JMP

0

0

0

1 0

JNC

0

0

0

1

JNE

0

0

0

1

JNO

0

0

0

1

JOC

0

0

0

1

JOP

0

0

0

1

0

12

0

0

1

Jump less than

STl

Jump u ncondrtro nal

unco nd 111o nal

0 and ST2

0 0

0

1

1

0

1

1 0

Jump not equal

ST2

~

0

1 0

0

1

Jump no overfl o w

ST4

~

0

1

0

0

0

Jump o n carry

STJ - 1

1

1 0

0

Ju mp odd pamy

Jump no carry

I

I

-

J

0

1 o r ST2 " t

0

1

15

SIGNED DISPLACEMENT (WORDSI

OP CODE

I

9

0
1

0

STJ = 0

ST 5

~

1

In assembly language, $ in the operand indicates "at this instruction". Essentially
JMP $ causes an unconditional loop to the same instruction l ocation , and JMP $+2 is
essen tially a no-op ($+2 means "here plus two bytes"). Note that the number following
the $ is a byte count while displacement in machine language is in words.

4-20

EXAMPLES:
EXAMPLES

( 1J

ASSEMBLY LANGUAGE.

JEO

S+4

IF EO BIT SET. SKIP 1 INSTRUCTION

MA CHINE LANGUAGE.
0
0

3

2

0

5

4

7

6

_ o_ _ _ _o_ _o_ _ _

8

±

10

9
0

12

13

14

15

__
o __o_ _o___
o __o_ _,___,j

~~
TO-~_::)

PC POINTS

11

·1301

IF STATUS REGISTER BIT 2 "' 1
SKIP NEXT INSTRUCTION

The above instruction continues execution 4 bytes (2 words) from the instruction
location or, in other words, two bytes (one word) from the Program Counter value
(incremented by 2 and now pointing to next instruction while JEQ executes). Thus, the
signed displacement of 1 word (2 bytes) is the value to be added to the PC.

(2)

ASSEMBLY LANGUAGE.

$

JMP

REMAIN AT THIS LOCATION

MACHINE LANGUAGE:
0

I

0

2

0

0

3

4

5

6

7

0

0

0

0

PC-1 WORD

8

I

9

10

11

PC POINTS TO

13

14

- ,

1

JMP $

12

15

~

; lOFF

CONTINUOUS LOOP
TO JMP $

I> FF = - 1 WORDI

This causes an unconditional loop back to one word less than the Program Counter value
(PC+ FF = PC-1 word). The Status Register is not checked . A JMP $+2 means "go to the
next instruction" and has a displacement of zero (a no-op). No-ops can substitute for
deleted code or can be used for timing purposes.
4 . 6.2.2 CRU Single-Bit Instructions
These instructions test or set values at the Communications Register Unit (CRU). The
CRU bit is selected by the CRU address in bits 3 to 14 of register 12 plus the signed
displacement value. The selected bit is set to a one or zero, or it is tested and the
bit value placed in equal bit (2) of the Status Register. The signed displacemertt has
a value of -128 to 127.
NOTE
CRU addressing is discussed in detail in paragraph 5.5. CRU multibit
instructions are defined in paragraph 4.6.4.
4-21

3

2

0

7

6

10

9

8

--1L

__o_P_co_o_E__
0 1 2 3 4 5 6 7

SBO

0 0 0 I 1 1

SB/

0 0 0

TB

0 0 0

I

14

13

15

STATUS

I

MEANING

BITS

DESCRIPTION

AFFECTED

---

t IHI to one

Set the selected C R U OU tPU t b it 10 1
Set the selected CRU output IHI to 0

1111 to Lero

1 1

12

11

SIGNED DISPLACEMENT

OP CODE

General Format :

MNEMONIC

5

4

If the selected CHU input hit

2

St ll1t

1. set ST 2

EXAMPLE

R12, BITS 3 TO 14 = > 100

ASSEMBLY LANGUAGE:

SBO

4

SET CRU ADDRESS > 104 TO ONE

MACHINE LANGUAGE:
2

0

0

4.6.3

4

3

5

0

0

0

7

6

8

9

10

11

12

0

0

0

0

0

13

14

15

0

0

> 1D04

FORMAT 3/9 INSTRUCTIONS

These are dual operand instructions with multiple addressing modes for the source
operand, and workspace register addressing for the destination. The MPY and DIV
instructions are termed format 9 but both use the same format as format 3. The XOP
instruction is covered in paragraph 4.6.g.
0

Gen•M Format:

2

3

OPCODE

4

5

I

6

7

8

9

10

DR (REGISTER ONL YI J

11

12

13

15

SR

Ts

RESULT
STATUS
COMPARED
BITS
TO 0
AFFECTED

14

MNEMONI C

OPCODE
01 2345

coc

001 000

Compare ones
corresponding

No

2

Tnt to RI to determine 1f l ' s are in each
bit pasit1on where 1 's are 1n (SAi . If so,
set ST2.

czc

001001

Compare zeros
corr espondmg

No

2

Test (OR) to determine 11 O's are in each
bit pos1t 1on where 1 's are in (SA ). If so,
set ST2.

XOR

00 101 0

E•clusive OR

Yes

(). 2

(ORI

MPV

00 1110

Multiply

No

DIV

001111

0 1v1de

No

MEANING

DESCRIPTION

$

ISA) _. IORI

Multiply unsigned IORl by unsigned
(SA) and place unsigned 32·b11 product
in OR (most s1gn1f1cant) and OR + 1
(least s19n1f1cantl If WR 15 is OR . the
n'"t word in memory a fter WR15 will
be used for the least sign1f1can t half of
1he pro d ucl
4

If unsigned (SA) os less 1ha n or equal to

unsigned (ORI , perlorm no operation
and set ST4 01herwise dovode unsigned
(ORI and IORI by unsigned (SA i .
Quotient - (OR I. re main<.Jer .... (OR 11).
If OR 15. the ne.i word on memo1y
after WR 15 woll be use FEOO

@> FEOO,R5

MACHINE LANGUAGE:
2

0

0

3

4

0

5
1

7

6

Io
1

0

BEFORE
M .A . > FEOO

8

9

0

1

0

0

I

10

11

1

0

0

0

I

12

13

14

15

0

0

0

0

0

0

0

0

AFTER

0005

R5

0000

0003

R6

00 11

0002

4-23

-

- - REMAINDER

'>3060

I

· FEOO

The unsigned 32-bit value in the destination register and destination register +1 is
divided by the source operand value. The result is placed in the destination register.
The remaindewr is placed in the destination register +1.

(3)

ASSEMBLY LANGUAGE:

coc

R10,R11

ONES IN RlO ALSO IN Rl 1?

MACHINE LANGUAGE:
0

I

2

0

0

3

4

0

0

5

I

0

6

7

1

0

8

9

I

1

10

11

0

0

12

13

1

0

I

14

15
0

>22CA

Locate all binary ones in the source operand. If the destination operand also has ones
in these positions, set the equal flag in the Status Register; otherwise, reset this
flag. The following sets the equal flag:

0

2

RlO

0

5

4

3
0

Rll

6

0

7

8

9

10

11

0

0

0

0

1

1

0

0

12

13

14

15

0

0

0

0

0

I

S.. EO bit in Status R...... to 1.

4.6.4

> AAOC
> EFCO

FORMAT 4 (CRU MULTIBIT) INSTRUCTIONS
0

Gen.al Format :[

2

3

OP CODE

4

5

6

8

7

9

c

'--~~~~~~~~~~---''----~~~~~~-'--

10

11

Ts

12

13

SR

14

15

~

The C field specifies the number of bits to be transferred. If C = O, 16 bits will be
transferred. The CRU base register (WR 12, bits 3 through 14) defines the starting CRU
bit address. The bits are transferred serially and the CHU address is incremented with
each bit transfer, although the contents of WR 12 are not affected. Ts and SR provide
multiple mode addressing capability for the source operand. If 8 or fewer bits are
transferred (C = 1 through 8), the source address is a byte address. If 9 or more bits
are transferred (C = O, 9 through 15), the source address is a word (even number)
address. If the source is addressed in the workspace register indirect autoincrement
mode, the workspace register is incremented by 1 if C = 1 through 8, and is
incremented by 2 otherwise.

NOTE
CRU addressing is discussed in detail in paragraph 5.5. CRU single bit
instructions are defined in paragraph 4.6.2.2.
4-24

MNEMONIC

RESULT

OPCODE

MEANING

0 1 2 3 4 5

0 0 1 1 0 0

LDC R

STATUS

COMPARED

BITS

TO 0

AFFECTED

Load communcat1on

DESCRIPTION

0 ·2.5 t

Yes

Begin ning w11h LSB o f (SA i. t ransfe r t he

register

specified num ber of bi t s from (S A) to
t he CR U.

0 0 1 1 0 1

S TCR

Store commun ca11on

0 -2 .st

Ye s

Beginning w ith LSB o f (SA ). tran sfer t he

register

spec1f1 ed number of b1 1s from the CRU 10
(SA i. l oad unf ille d b 11 p cs1t1on s wit h 0.
1 ST5

is a ffec t ed onl y if 1 "- C

~

8.

EXAMPLE

ASSEMBLY LANGUAGE:

LDCR

@> FE00,8

LOAD 8 BITS ON CRU FROM M.A. > FEOO

MACHINE LANGUAGE:
0

3

2

I'

0

4

5

0

o

I

1

7

8

9

10

11

12

13

14

15

0

0

o 1

1

o

Io

0

0

0

>3220

0

0

0

0

0

0

0

0

0

>FEOO

NOTE
CRU addressing is discussed in detail in paragraph 5,5,

4.6.5 FORMAT 5 (SHIFT) INSTRUCTIONS
These instructions shift (left, right, or circular) the bit patterns in a workspace
register. The last bit value shifted out is placed in the carry bit (3) of the Status
Register. If the SLA instruction causes a one to be shi fted into the sign bit, the ST
overflow bit (4) is set. The C field contains the number of bits to shift.
0
Geneul Format:

2

3

4

5

6

7

8

10

9

c

OP CODE

11

12

13

14
R

If C = O, bits 12 through 15 of RO contain the shift count. If C
through 15 of WRO = O, the shift count is 16.

4-25

15

=0

and bits 12

RESULT

Of' CODE

MNEMONIC

0

4 5 6 7

2 3

1

1 0

0 0 0 0

SLA

MEANING

0

1

STATUS
DESCRIPTION

COMPARED

BITS

TOO

AFFECTED

Yes

0-4

Shi ft left arithmetic

Shift

IAI

left. Fill vacated bit

positions with 0.
1 0

0 0 0 0

SRA

Shift right arithmetic

0 0

0-3

Yes

Shift

IRI right.

Fill vacated bit

positions with origin.I MSB of (Al.

0 0 0 0

SAC

0

1

1

0-3

Yes

Shilt right circular

1

Shift

IA)

right. Shift previous LSB

into MSB.
1 0

0 0 0 0

SAL

0

Shift right logical

1

0 -J

Yes

Shift

IRI right. Fill v11e11ted bit

positions with O's.
EXAMPLES

(1)

ASSEMBLY LANGUAGE:

SHIFT Al RIGHT 2 POSITIONS, CARRY SIGN

Rl,2

SRA

MACHINE LANGUAGE:
0
0

0

Al BEFORE

I

0

0
'<

3

0

0

2

3

0

0

4

4

5

6

7

8

9

10

11

12

13

14

15

0

0

0

0

0

1

0

0

0

0

1

5

6

7

8

9

10

11

12

13

14

15

0

0

0

0

1

1

'''

''

·;

R1 AFTER

(2)

2

0

0

',

''

'

0

0

0

0

0

13

>8FOF

1
'<

>0841

''
'

>E3C3

SIGN BIT CARRIED IN

ASSEMBLY LANGUAGE:

R5,4

SAC

CIRCULAR SHIFT AS 4 POSITIONS

MACHINE LANGUAGE:
2

3

0

0

0

2

3

0

c:::: _____

0

0

0
[ 0

RS BEFORE

0

0

4

4

---

RSAFTER C-~

5

6

7

0

0

0

5

6

7

0

0

I

8

9

10

11

12

0

1

0

0

0

8

9

10

11

12

0

0

0

0

0

0

-- ---- -- -- ---I =..

0

0

0

0

1

4-26

15
>0845

0

13

:_ 1

--- --

0

14

0

14

•

15
:>090F

-;-E;. .

(3) ASSEMBL Y LANGUA GE ·

SLA

SHIFT COUNT IN RO

R1 ,0

SHIFT COUNT

0

RO

2

3

0

0

4

5

R1 IBEFOREI

6

7

0

0

8

9

10

11

0

0

/

A

12

13

0

0

'

14

15

·CCC3

1

R1 IAFTERI

1

0

0

0

I

~

VACATED BITS ZERO FILLED

4.6.6 FORMAT 6 INSTRUCTIONS
These are single operand instructions.
4

3

2

0

5

6

7

8

10

9

11

12

13

14

15

SR

The Ts and S fields provide multiple mode addressing capability for the source operand.

MNEMONIC

RESULT

OPCODE
0 1 2 3 4 5 6 7 8 9

MEANING

STATUS

COMPARED

BITS

TOO

AFFECTED

DESCRIPTION

B

0 0 0 0 0 1 0 0 0

B•nnch

No

SA

BL

0 0 0 0 0 1

Br,mch Jncl link

No

IPCI -+ (Rl 11 ; SA ---. (PC)

BLWP

0 0 0 0 0

B1,1nch .ind load

No

(SA) -+(WP) ; (SA+2) -+(PC );

0 1 0
0 0 0 0

IPCJ

(old WP) · lnew WR J3l

WU• ksp dCP po1nlPr

(old PC) - I new WR 14J.
lold ST) ·(new WR 15)
the 1n1e,.uµ1 1npu1 l lNTREOI "1101
tPstc

I

ISAl,

I

ISAI' 2 ·ISA)

!

1111~

0 1h1u 7

ISA)• 1 · ISAI
(SA) - 1 · ISA I
ISA> - 2 • I SAI
EJiCt'CUIP thp 1ns11uc11on .11

1

SA

•<>p.•nd is compsed to z...o fOI' wttint the st•tus bit li.e ., before execution).

tu

additional memory words fo r the execute instruction are required to define the operands of the instruction lo cated at SA , these
words w;11 be accessed from PC and the PC will be updated accordingly. The 1n1truction acquisition signal (IAQ) will not be true
when the TMS 9900 accesses the instruction at SA . Status bits are affected in the normal manner for the instruction executed.

NOTE
Jumps, branches, and XOP's are compared in Table 4-5.

4-27

EXAMPLES

(1)

ASSEMBLY LANGUAGE:

B

*R2

BRANCH TO M.A. IN R2

MACHINE LANGUAGE:
0

2

3

5

4

6

F

R2

7

8

0

0

10

9

(2)

12

13

14

15

0

F-B~~-·-R-2~---f~
NEXT INSTR.

M.A. >FOOO

11

~

F

0

0

IAFTERI

0

PC

ASSEMBLY LANGUAGE:

BL

@> FFOO

BRANCH TO M.A. > FFOO, SAVE OLD PC VALUE (AFTER EXECUTION) IN All

MACHINE LANGUAGE:
0
0

2

3

4

0

0

0

5

6

7

1

0

8

0
0

1·
F

c

F

0

0

,.,fC04

> FFOO

10

I

0

11

1

13

14

15

0

0

0

0

0

0

0

0

l

0

0

12

0

>04AO

I

> FFOO

4

0

BL@ > FFOO
F

9

NEXT INSTR .

PC

)

IF

F

0

(AFTER I

0

TO RETURN
EXECUTE
B •R11
B •R11

(3)

ASSEMBLY LANGUAGE:

BLWP

@> FOOO

BRANCH, GET NEW WORKSPACE AREA

MACHINE LANGUAGE:
0
0
1--

0

2

3

0

0

4

,-

0
1

5

6

7

0

0
-

0

8

9

0

0

0

0

r

4-28

10

J_
0

11

12

13

14

15

0

0

0

0

0

>0420

0

0

0

0

0

>FOOD

This context switch pr ovides a new workspace register file and stores return values in
the new workspace. See Figure 4- 10 . The operand (> FDOO above) is the M.A. of a
two-wor d t ransfer vector, the first word the new WP value, the second word the new PC
value .
BLWP@ >F DOO

M.A .>FCOO

BRANCH WITH NEW WORKSPACE

N

RO

,..

r

J.

>FC80

CALLING PROGRAM

J.

BLWP@ > FOOO

BEFORE BLWP OCCURS
WP

FCOO

TRANSFER{

> FOOO

VECTORS

FF 00 (NEW WP)

PC

F F 2 0 (NEW PC I

ST

<\\
>FFOO

RO

I\

p
OCCURS
F F 0 0

WP

F F 2 0

PC

N
R ETUR N

F C 0 0 = (OLD WP)

R 13

VALUES

F C 8 4 = (OLD PC)

R14

OLD ST CONTENTS

R1 5

:-FF20

>-

ST

NEW EX ECUTI ON A REA

NEXT INSTR .

R TWP

"
A0001430

RTWP RETU R NS EXECUTION TO CAL LING
PROGRAM STARTING AT M.A. >FC84

Figure 4-10.

BLWP Example

Essentially, the RTWP instruction ls a ""~i~•l • 'n t .) the next instruction that follows the
BLWP instruction (i.e. , RTWP is a return f rom a BLWP context switch, similar to the B
*R11 return from a BL instruction). BLWP provides the necessary values in registers
13, 14, and 15 (see Figure 4- 10.

4-29

Table 4-5.

MNEMONIC

I

I

PARAGRAPH

JMP

Comparison of Jumps , Branches, XOP's

DEFINITION SUMMARY
One·word instruction, destination restric ted to + 127 , - 128 words from Program

4.6 . 2

Counter value.

B

4 .6. 6

Two·word instructio n. branch to any memory location .

BL

4.6 .6

Same as B w i th PC return address in A 11.

BLWP

4.6.7

Same as B with new wor kspace: old WP, PC and ST conten ts (return vt>ctors) are on
new R1 3, R 14. R15 .

XOP

4.6.7

Same as B LWP with address o f para m erer (source operand) in new R 11. S1x teEn XOP
vectors ou tside program in M A. 40 1 6 to 7E 1 6 ; can be coiled by any proyrarn

4.6 .9

FORMAT 7 (RTWP, CONTROL) I NSTRUCTIONS
0

2

3

4

5

6

7

8

9

10

11

15

14

N

OPCODE

Geneo-al Format :

13

12

External instructions cause the three most-significant address l ines (AO through A2)
to be set to the levels described in the table below and cause the CRUCLK line to be
pulsed, allowing external control functions to be interpreted during CRUCLK at AO, Al,
and A2. The RSET instruction resets the I/0 lines on the TMS 9901 to input lines; the
TMS 9902 is not affected . RSET also clears the interrupt mask in the Status Register.
The LREX instruction causes a delayed load interrupt, delayed by two IAQ cycles after
LREX execution. The lo~d operation gives control to the moni tor. ~ote, that although
included here because of its for mat, the RTWP instruction is not classified as an
external instruction because it does not affect the address lines or CRUCLK.

CK'5'F' and CKON can be used by monitoring pins 9 and 10 respectively of U25. See sheet 2
of the schematics in Appendix F.
ADDRESS

STATUS
MNEMONIC

IDLE

OPCODE

- 012345678910
00000011010

MEANING

BITS

AOA1 A 2

AFFECTED

-

Idle

aus•

DESCRIPTION

Suspend TMS 9900

L

H L

L

H H

instruction execution unto!

--

an interrupt , LOAD, or

-RESET
- occurs
R SET

000000110 11

Reset 1/ 0 & SR

C KOF

00000011110

User defined

C KON

000000 111 01

User de f ined

LRE X

0000001 11 1 1

Load on terrupt

RTWP

000 0 0011100

Retur n from

12- 15

0 -+ST12 thru ST15

---

H H L

---

H L

Control to TIBUG
0 - 15

IR1 3) - (WP)
(R1 4) - ( PC)

Subroutone

(R 15) - .(ST)

·T hese output s fr om the TM S 9900 go to a SN74LS138 as shown in Figure 5 ·6

4-30

H

H H H

ASSEMBLY LANGUAGE.

RTWP

RETURN FROM CONTEXT SWITCH

MACHI N E LA NGUAGE.

I.
'

0
0

0

2

3

4

5

0

0

0

0

RTWP

8

7

6

9

10

11

12

13

14

15

0

0

0

0

0

0

0

>0380

RETURN TO PREVIOUS WP IR13), PC IR14), ST (R15) VALUES

R13

F C 0 0

R14

F C 8 4

AFTER

R15

STATUS

F C 0 0

WP

FC84

PC

STATUS

ST

RTWP

M .A . >FF40

EXECUTION BEGINS AT M .A . >FC84
WITH RO AT M .A . ">FCOO.

4.6.8

FORMAT 8 (IMMEDIATE, INTERNAL REGISTER LOAD/ STORE) INSTRUCTIONS

4 . 6.8.1

Immed iate Register Instructions

0
Gener al form.it

3

2

4

E_~

5

8

7

6

9

10

11

I

OP CO D E
IOP

14

13

12

R

N

-----

--

15

~

---~-

..

M N EM ON IC

OP CODE

R ES U LT
~

0 1 2 3 4 5 6 7 8 9 10

I

M E AN ING

COMPAR ED
TO 0

STATUS
D ESC RIPTION

BI TS
A F FEC T ED

-~

Al

0 0 0 0 0 0 1 0 0 0

Adrt 1mmP· t1.11e

Yps

04

(RI

ANDI

0 0 0 0 0 0 1 0 0 1 0

AND 1mmt•cti.ttt

Yes

02

(R) AND IOP -+(RI

Cl

0 0 0 0 0 0 1 0 1 0

Cu mpa r.-

YPs

02

Compare (R ) to t OP and set

1
0

I

IOP -+ ( R I

appro pria te s1a1us b ir s

1mmed1utt~

LI

0 0 0 0 0 0 1 0 0 0 0

Load 1mm ed1,J1e

YPS

02

IO P - t RI

O RI

000 0 0 01 0 0 l

OR 1mmed 1dte

Yes

02

(R ) OR IOP - (Rl

AND l ogic -

0 .1. 1 0

0

1

OR l ogic :

0 + 1, 1

I

0

1

O·O = 0

1 t 1

1 ·1 = 1

0+ 0=0

4-31

~

1

4.6.8.2

Internal Register Load Immediate Instructions
2

0

4

3

General format :

7

6

5

8

10

9

11

12

13

14

15

N

OP CO D E
IOP

OP CODE
MNEMONIC

1 2 3

0

0 0

LWPI
LIMI

0

0

0
0

0

4

5

6 7 8 9

0

0

1 0

0

0

0

1

1

1

I

0

MEANING

10

0

DESCRIPTION

-

1

l oJd w ur k spJcc poin ter 1mmed 1.11e

IOP • (WPI . nu ST l 111 s .i ft ec tPrl

0

LC>.1<11ntto! rr up t m ,1sk

IOP , hr t s 12 t hru 15 · ST12
th ru S T1 5

4 . 6 . 8.3

Internal Register Store Instructions
2

0

4

3

5

Genefal format .

7

6

9

8

10

11

12

14

13

IN

OP CO DE

15

R

NO ST BITS ARE AFFECTED.
OP CODE

MNEMONIC

0

1

STST

0

0

0 0

ST WP

0

0

0

0

2

8

9 10

0 0

1 0

1

1

0

Store

s 1 ,11 l1~

0 0

1 0

1 0

I

Stu• P

wor k sp~ce

5

I

MEANING

6 7

4

3

reqrster

-

po1 n 1er

-

DESCRIPTION

l

IST I

• ( A)

IWP ) · (A)

·-

E XAMPLES

( 1J

A SSEMBLY LANGUA GE:

Al

R2,> FF

ADO > FF TO CONTENTS OF R2

MA CHINE LANGUAGE:
0
0

0

2

3

0

0

4

5

0

0

6

7

8

9

0

0

0

10

,--0

0

0

0

0

0

0

0

11

12

13

14

15

·1-3
1

1

1

1

..-0222

' OOFF

..
BEFORE

Io o o F

R2

(2)

AFTER

0 1 0 E

A SSEMBLY LANGUA GE:

Cl

R2,> lOE

COMPARE R2 TO ,.,.JOE

MA CHINE LANGUAGE:
0

p.=

0
0

2

3

0

0

0

0

r

R2 contains " after " results

4

5

0

0

0

0

6

7

8

0
0

0

9

10

11

12

13

0

0

0

0

0

0

0

0

14

15

d
0

I > IOE) of instruction on Example ( 1 I above; thus the ST equal bit becomes set .

4-32

..-0282
-OlOE

(3)

ASSEMBLY LANGUA GE

LWPI

,FCOO

WP SET AT

·FCOO (M.A. OF RO)

MACHINE LANG UA GE.
0

F. "
(4)

2

3

4

5

0

0

0

0

6

7

9

8

0

0

10
1

0

0

0

I

0

11

12

13

14

0

0

0

0

0

0

0

0

15

:J

-02EO

·F COO

ASSEMBLY LANGUAGE:

STWP

R2

STORE WP CONTENTS IN R2

MACHINE LANGUAGE:
0

I

0

0

2

3

4

5

0

0

0

0

6

7

8

0

9

10

11

0

0

I

12

13

0

0

14

15
0

I

>02A2

This places the M.A. of RO in a workspace register,

4.6.9 FORMAT 9 (XOP) INSTRUCTIONS
Other f ormat 9 i nstru c tions (MPY, DIV) are explained in paragraph 4. 6 .3 (format 3).

0

General Format :

0

2
0

3

4

0

5

6

7

8

D IXOP NUMBER)

9

10

11

12

Ts

13

14

15

SA

The TS and SR fields prov i de multiple mode addressing c apab i l it y for the s ource
opera nd. When the XOP is executed, ST6 is set and the f ollowing transfers occur:

(40 , (l

I

4 0) - (WP)

(42 10 + 40 ) - (PC)

Fir st vec t or at 40 1 b
Each vec tor uses 4 bytes (2 wo rds)

SA - (new R l 1)
(old WP) - (new W R 1 3)
(o ld PC) - (new W R 14)
(old ST) · (new W R 15)

The TMS 9900 does no t test interrupt requ e s t (I NTREQ) upon c ompletion of t he XOP
instruction .

4-33

An XOP is a means of calling one of 16 subtasks available for use by any executing
task. The EPROM memory area between M.A. 40 16 and 7E 16 is reserved for the transfer
vectors of XOP' s 0 to 15 (see Figure 4-1). Each XOP vector consists of two words, the
first a WP value , the second a PC value, defining the workspace pointer and entry
point for a new subtask. These values are placed in their respective hardware
registers when the XOP is executed.
The old WP, PC, and ST values (of the XOP calling task) are stored (like the BLWP
i nstruction) in the new workspace, registers 13, 14, and 15. Return to the calling
r outine is through the RTWP instruction. Also stored, in the new R11, is the M.A. of
the source operand. This allows passing a parameter to the new subtask, such as the
memory address of a string of values to be processed by the XOP-called routine. Figure
4-11 depicts calling an XOP to process a table of data; the data begin s at M.A.
FFOo 16 . This XOP example uses XOP vectors that point directly to the XOP service
routine WP and PC. The TM 990/101M comes with interrupt and XOP vectors pointing to
linking areas that point to the service routine. The use of these linking areas is
explained in subsection 5.9.
XOP's o, 1 and 8 to 15 are used by the TIBUG monitor, calling softwar e routines
(supervisor calls) as requested by tasks. This user-accessible software performs tasks
such as write to terminal, convert binary to hex ASCII, etc. These monitor XOP's are
discussed in Section 3 . 3. XOP vectors 2 through 7 are programmed wi th memory vector
values, but reserved for the user. See Section 5.9 for an explanation of the
Interrupt/XOP linking area.

4-34

ASSEMBLY LANGUAGE:

XOP

@>FF00,4

MACHINE LANGUAGE:
0

I

0

t

2

3

0

4

0

5
1

1

6

I

7

0

1

>0050

VECTORS

0

0

0

0

10

I
0

11

12

13

14

15

0

0

0

0

0

0

0

0

0

0

0

WP

AFTER

XOP

0

PC

F C 0 0

WP

F C 2 0

PC

N

ST

F

c

~

0 0

F C 2 0

> oos2

9

XOP

\.

XOP

8

j

>2020
>FFOO

\

1
~

> 001e

<

1

,).

CALLING INSTR .

XOP @>FF00.4

' ,).

\.

> FCOO

•

RO

'~

•

'\
F F 0 0

t

R l l - - - - PASSED PAR AMETER (SOURCE OPERAND)
R12

''

XOP4

OLD WP

R13

PROGRAM

OLD PC

R14

OLD SR

R15

1ST INSTR.

> FC20

\
RTWP

TABLE OF
VALUES TO
BE PROCESSED

l

TO CALLIN G TASK

,

'~
•

I

RETURN VE CT ORS

'

\

~

> FFOO

NOTE
THIS EXAMPLED oes NOT use THE XOP
LINKING AREAS E XPLAINED IN SUBSECTION
5.9. THIS XOP EXAMPLE PRESUMES THE XOP
VECTORS HAVE 8 EENPROGRAMMEDINTO
MEMORY (M.A. 0050
AND 0052 ) BY THE
16
16
USER.

A0001431

Figure 4-11.

4-35

XOP Example

SECTION 5
PROGRAMMING
5.1 GENERAL
This section is designed to familiarize the user with programming the TM 990/101M.
Explanations about the programming environment, using TIBUG XOP's, supporting special
features of the hardware, and certain programming practices are included. Programs are
provided as examples for the user to analyze and fol low, and possibly combi ne into
the user's system. This section is divided into, roughly, two areas: the first part
gives background information on the programming environment and shows suggested coding
practices for a variety of situations, and the second part gives specific program
examples using special features of the hardware.
For clarity, source listing examples in this section use assembler directives
recognized by larger assemblers but not recognized by the TM 990/402 Line-By- Line
Assembler (LBLA) . These directives are not explained in the section on the 990
instruction set (Section 4), but are explained in detail in the Model 990 Computer,
TMS 9900 Microprocessor As sembly Language Programmer's Guide. A synopsis of their
definitions is included here. These directives are explained in Table 5-1.

Table 5- 1.
Label

Opcode

AAAA

Meaning

Operand

AORG

xxxx

Assemble code that follows so that it is loaded
beginning at M.A. XXXX. This is similar to the
absolute load (slash) request of the LBLA .

DATA

yyyy

Place the value YYYY in this location (if preceded by the greater-than sign ( ) the quantity
is a hexadecimal representation) .

DATA

LABEL

If LABEL represents a memory address, the memory
address value is placed at this location aligned
on an even address (word boundary) .
Signifies end of program for assembler.

END

,,

Assembler Directives Used In Examples

EQU

BBBB

Wherever the symbol AAAA is found, substitute the
value BBBB .

IDT

'NAME '

Program will be identified by NAME .

TEXT

'ABCD123'

The ASCII value of the specified character string
is assembled in successive bytes.

5-1

I

SOURCE STATEMENT NO.
RELATIVE ADDRESS
OBJECT CODE (ASSEMBLED SOURCE)
LABEL FIELD

Ir

I

/ ;
(1••f: '

(lrY-·11

;1Jf1 :.

.-.. 1»:·=·•1

;'1•. '.:/-.

.-,

n;" ·-::-':

on r:1~·

1

..-)()·-.:·,'';

; r-··r,:~:

.. -;,-; ;·1·

()(_.·,1:;

1 , ,

,::

• .. ·:_ -

.1,.: 1

::i:, :'

-....1 ·

··;o~ .- ·~'7

_;.1

··:-·1i°;

,,-

:·..·.·.··, ............ 1.;r·,
' 1•

'lj :'

I'

I

/OPCODE
!OPERAND

1: 1 F;
L. [

J.

CL.EAR FOR DECIM()L TO HE X RllUTI

7 ., c •:::Pf.'IRM

PROMPT ME::::::AOE'.3

I )

,,

··

I f '1•"1F"I

COMMENT FIELO

.

·=-·. --·

FI Vf F'ROMPl :;:;

l ]

·-I , Cl f::l·Jf-'+4

REGISTER 2 ()DDRESS

l·!R I f

{~ 7

PROMPT LI SER FUR T 1 ME
GET Il'IPUT
l\!ULL, ERFiOH r:TN !l[rR

HF :< [ 0

ntnt.

r~E>'. T ., r:rmOFi

\l~L l.I F

DECIMAL CHnRS TO Bl NnRY

,1

'-------~-------_..__ASSEMBLED OBJECT SHOWS RELATIVE

ADDRESS OF "NEXT" AT 004A16

Figure 5-1. Source Listing

Figure 5- 1 is part of a source listing used in thi s sec tion, as assembled by Tl's
TXMIRA assembler. Unless specified otherwise by directive, the TXMIRA assembler will
begin ass e mbling code relative to memory address 0000 16 (second column) . When
resolving an address for an instruction, as shown at the bottom of the fi gu re, the
instruction address operator is the same as the relative address in column two of the
listing . Thus, for the label NEXT, the address 004A 16 is assembled which is the
relative address within the listing. This is useful when de terar.ining such addresses as
the destination of a labelled BLWP i ns truction. Note that the Line-By-Line Asse mbl er
does not use label led addressing, but assembles the absolute address given.

5-2

5.2

PROGRAMMING CONSIDERATIONS

5.2.1 PROGRAM ORGANIZATION
Programs should be organized into two major areas:
•

Procedure area of executable code and data constants (never modified )

•

Data area of program data and work areas whose contents will be modified.

The executable code and constant data section can be debugged as a separate entity,
and then programmed into EPROM. The work area can be placed at any other address in
RAM, and that address does not have to be contiguous with the program code area, and
can even be dynamically allocated by a Get Memory supervisor call of some kind. Even
if the program parts are loaded and executed together, the organization and debug ease
are enhanced.
In this programming section, all example programs are coded, with one exception, in
this manner . The only work area is the register set, which is arbitrarily fixed to a
RAM address. The one exception, the Two-Terminal routine, is coded to reside entirely
in RAM because the workspace is a part of the contiguous extent of code. This method
of coding is used in RAM-intensi~e systems because the operating system need not
manage workspaces as might be necessary in a system with very little RAM.
5.2.2 EXECUTING TM 990/100M PROGRAMS ON THE TM 990/101M
Programs developed on the TM 990/100M board use a different interrupt and XOP trap
configuration than the TM 990/101M. This must be taken into consideration when
executing programs on the TM 990/101M that were developed for running on TM
990/lOOM. On the TM 990/lOOM, interrupt vectors are programmed into PROM for INT3 and
INT4 (vectors FF68 15 and FF88 15 for INT3 and FFAC 15 and FFAC 15 for INT4). This allows
immediate use of these interrupt traps such as with the TMS 9901 and TMS 9902 interval
timers . XOP vectors on the TM 990/100M are programmed for XOP's 0, 1 and 8 to 15 for
use by TIBUG. User XOP's (XOP 2-7) are not programmed.
On the TM 990/101M board, however, all interrupt and XOP vectors are programmed , and
the linking scheme in RAM is different . Consult the interrupt linking section
(paragraph 5 .9) for the scheme used. The TM 990 /100M scheme is described in the User's
Guide for that microcomputer .

..

5.2.3 REQUIRED USE OF RAM IN PROGRAMS
All memory locations that will be written to must be in RAM- type memory (this is
important to consider when the program is to be programmed into ROM). Areas-t o be
located in RAM include all registers as well as the destination operands of format 1
instructions and the source operands of most format 6 instructions .
For example, in the following source lines :
MOV
CLR
ABS
INCT

s

@>0700, @">FCOO
@ >FCOO
@>FCOO
@ > FCOO
R1 ,@> FCOO

MOVE DATA
CLEAR MEMORY ADDRESS
SET TO ABSOLUTE VALUE
INCREMENT BY TWO
(>FCOO) - R1 , ANSWER IN >FCOO

the address FCoo 16 will be written to; thus, it has to be in RAM .

5-3

5.3 PROGRAMMING ENVIRONMENT
The programming environment of a computer is loosely defined as the set of conditions
imposed on a programmer by either or both the hardware and systems software, but it is
also the facilities available to the programmer because of the design of the hardware
and software. The environment in which a program resides usually determines how that
program is coded. This section gives explanations of the majo r areas o f the TM
990/101M design from a programmer' s point of view. Note all program examples given are
for a full assembler (e.g., PXRASM, TXMIRA, or SDSMAC vs. the Line-By-Line Assembler)
so that labels can be used for reader comprehension.
5.3.1 HARDWARE REGISTERS
The TMS 9900 family of processors are designed around a memory-to-memory architecture
philosophy; consequently, the only hardware registers inside the processor affecting
the programmer are the Workspace Pointer (WP) register, the Program Counter (PC)
register and the Status (ST) register. There are no accumulators or general purpose
registers which reside physically inside the microprocessor. All manipulations of data
are accomplished by using these three registers as described below.
5.3.1.1 Workspace Pointer (WP) Register
The Workspace Pointer is a register which holds the address of a sixteen word area in
memory; this memory area serves as a general purpose register set. A memory area is
designated as a workspace or general purpose register set by loading the address of
the first word (register O) of the 16-word space into the WP register. Thus the
programmer's register set is in memory, and can be referred to with register
addressing, or if the WP value is known, with memory addressing. The registers are
simply a data area in a program with the special privileges usually given to processor
registers. This approach has several advantages for the programmer.
1.

Register save areas need no longer be kept in programs, since the actual
program registers are already in memory, and are maintained by the hardware
during program linking by the use of a special class of instructions.

2.

Program debugging is greatly heightened since the registers of
able program remain intact in memory during debugging. The debug
its own set of registers, in memory, and there is no question
many program modules has tampered with the processor registers ,
program in question can have its own registers.

3.

Recursive, re-entrant, and ROM resident code is much easier to write since
program calls are handled by special instructions, and new workspace areas,
linked together by the hardware, are available for use at each program call.

4.

Linked-list structuring of workspaces is automatically done by the hardware,
reducing system software overhead.

5.

Very fast interrupt handling is possible since only three processor registers (WP, PC, ST) are stored by the hardware during the inte r rupt (instead
of a whole register set) usually by a software instruction or routine.

a questionmonitor has
of which of
since each

5.3.1.2 Program Counter (PC) Register
The Program Counter (PC) register holds the address of the next instruction to be
executed by the processor. As such, it is no different than the PC in any other
processor and is incremented while fetching instructions unless modified by a program
branch or jump, or during an interrupt sequence.

5-4

5.3.1.3 Status (ST) Register
The Status Register holds the processor status and is the only one of the three
processor registers which has nothing to do with memory, directly . It is divided into
two parts: the status bits, which are set to reflect the attributes of data being
handled by the proces sor, and the interrupt mask, which governs the priority structure
of i nterrupt processing. The ST is organized as shown in Figure 4-2.
5.3.2 ADDRESS SPACE
The TMS 9900 microprocessor addresses 65,536 (64K) bytes (8-bits each). Although the
data bus is 16 bits wi de, and the instruction set is mainly word (16-bits) oriented,
the basic unit of address is a byte. The actual memory architecture is 32,768 (32K)
words of two bytes each, and byte processing is accomplished within the processor
afte r fetching a wo r d f rom memo r y . Because the instruction set is mainly
arithmet ically oriented, and usually operates on 16- bit words, it is probably best to
view the address space as a collection of words, each containing, usually for I/O
purposes, two bytes.
NOTE
This subsection covers the interrupt and XOP environments
in general; programming of interrupts and XOPs is covered
in detail in subsection 5.9.
5.3 . 3 VECTORS (INTERRUPT AND XOP)
Interrupt and XOP vectors are located beginning with address 000016 and extend through
007F16· The first half, addresses 000016 through 003F15, contain the interrupt
vectors . There are 16 prioritized interrupts. Level 0 is the highest priority, with a
vector pair at 000016 and 000216 · Level 15 is the lowest priority, with its vector
pair at 003C16 a nd 003E16· Level 0 interrupt is synonomous with the RESET function. A
vector pair consists of a workspace pointer and a program counter, both values
identifying the interrupt program environment.
Before an interrupt can occur, the processor must recognize it as having an equal or
higher priority than the interrupt mask in the Status Register. After a valid
interrupt has occurred the interrupt vector values are retrieved from memory, and the
hardware equivalent of a BLWP instruct ion takes place.
There is one additional vector pair, at FFFC16 and FFFE15, for the LOAD function. When
signaled, this interrupt always occurs and cannot be disabled by the Status Register
interrupt mask. Note also that RESET being level zero, cannot be disabled, since it s
Status Register priority value of zero is always equal to or higher than any value in
the interrupt mask field.
The XOP vectors work in a similar manner. Vector location begins at 004016 and extend
through 007F16· These vectors are triggered by execution of the XOP instruction, wi th
a number from 0 to 15. There is no prioritizing; these are software-triggered
i nterrupts, and XOP service routines may freely execute other XOP's. One additional
event happens during the vector action: the source operand of the XOP instruction is
evaluated as an address and placed in the~ Workspace Register 11. This provides a
parameter to the XOP routine.
The TIBUG monitor uses several XOP's for I/O service from the terminal; some of these
are available for the user as explained in subsection 3.3 . In addition, the programmer
may wish to program interrupt and XOP vectors for special functions.

5-5

5.3.4 WORKSPACE REGISTERS
The actual workspace registers, in memory, provide general working areas for a
.Program. Some registers can also be used for special purposes; these are listed in
Table 5-2.
Table 5-2 .

Register Reserved Application

Register

Application

O:

Bits 12-15 (least significant half-byte) provide the shift count for
shift instructions coded to refer to this register. This register cannot be used for indexed addressing.

11 :

Holds return address following execution of a BL instruction. During XOP service routine, it holds resolved memory address of argument
in XOP instruction.

12:

CRU Base Address .

13:

During BLWP, RTWP, interrupts, and XOP's: holds old WP contents .

14:

During BLWP, RTWP , interrupts, and XOP's: holds old PC contents.

15:

During BLWP, RTWP, interrupts, and XOP's: holds old ST contents.

In general, then, registers 1 to 10 are avai lable for unrestricted use , although the
programmer can use the reserved registers for other purposes, if proper consideration
is given.
One advantage of the workspace concept is that one program can request an almost
unlimited number of register sets, or, alternatively, every little module in a program
system can have at least one set of its own registers. Programs are us ually written to
take advantage of the benefits associated with program operands in registers.
5. 4 LINKING INSTRUCTIONS
These are of vital interest to a programmer for they answer the all important question
of how to get in and out of a program. These instructions are:
•
B (paragraph 5 .4.1)
Branch
•
BL (paragraph 5.4.2)
Branch with return link in R11
•
BLWP (paragraph 5 .4.3)
Branch, new workspace, return link in R13 to R15
•
RTWP (paragraph 5 .4.4)
Return, use vectors in R13 and R14
•
XOP (paragraph 5. 4.5)
Branch, new workspace, vectors in low memory
5.4.1 BRANCH INSTRUCTION (8)
Though not normally considered a program linking instruction, the branch instruction
can be us ed to link to programs in a known location, such as TIBUG. Since the
Workspace Pointer is not affected by the instruction, program systems using thi s
convention usually delegate the responsibility for establishing workspaces to each
program. Thus we may have branches to various programs as shown in Figure 5-2. Note
that each program sets up i ts own WP (LWPI instruction). The AORG and EQU directives
are explained in paragraph 5.1.

5-6

PGMB
PGMC
PGMA

*PGMA PROGRAM
AORG
EQU
EQU
LWPI

@PGMB _ /

B

B

*PGMC PROGRAM
AORG
EQU
PGMA
PGMB
EQU
PGMC
LWPI

@PGMC_/

B

>1000
>0800
>OAOO
>FF50
@PGMA

@>0080

B

Figure 5-2 .

*PGMB PROGRAM
AORG >OAOO
EQU >0800
PGMA
PGMC
EQU >1000
PGMB
LWPI >FF70

>0800
>OAOO
>1000
>FF90

Example of Separate Programs Joined By Branches to Absolute Addresses

5.4.2 BRANCH AND LINK (BL)
The BL instruction is designed mainly for the calling of subprograms
means of returning back to the calling program. Since the processor
of the next instruction in register 11 (it effectively transfers the
branching, the return path is established . To return (using the same
execute a B *R11 (or RT instruction).

with a convenient
puts the address
PC to R11) before
workspace) simply

Note, though, that only one level of subroutine call is possible if only one workspace
area is used, unless register 11 is saved by the first subroutine wishing to branch
and link to a second subroutine.
CALLING PROGRAM
BL
@FEOO

______,,

FEOO

FIRST LINK
LI
R6,47

FDOO

R11,R1~

SECOND LINK
CI

R5,22

!

MOV
BL @>FDOO

B

*Rl 1

~

The BL subroutine can include XOP instructions to provide special services needed to
accomplish the subroutine function, as in the following example:
CALLING PROGRAM
RDNUM
BL @RDNUM

SUBROUTINE
R1, 13
Rl ,?3000
RDNUM
R1, > 3900
RDNUM
R1, 12
• 11

XOP
CI
JL
CI
JH
XOP
B

5-7

READ A CHARACTER
IS IT BELOW A ZERO?
YES, GO BACK
IS IT ABOVE A NINE?
YES, GO BACK
ECHO THE CHARACTER
RETURN

The very simple routine shown above reads a character from the terminal and checks for
a decimal digit 0-9. If the character is acceptable, it is echoed back to the
terminal, and then control is returned to the calling program. If the character is
unacceptable, the routine drops it and requests another; the bad character is not
echoed to show the user that another character must be typed.

5.4.3 BRANCH AND LOAD WORKSPACE POINTER (BLWP)
This is the most sophisticated linking instruction in that it causes a complete
program environment change (context switch), and automatically links the old workspace
to the new, also preserving the old processor status. As such, it behaves in the same
way as the interrupt sequence or XOP sequence, and it is therefore possible to vector
to an interrupt or XOP service routine without actually causing an interrupt or
executing an XOP. For example, executing a BLWP @O will vector to the RESET interrupt
handler, which if TIBUG is resident, causes the user to set the baud rate and start
TIBUG again.
Since the TMS 9900 is a linked-list rather than a stack machine, those used to a stack
for systems programming may need some readjustment, but the superior flexibility of
linked-lists is simplified by the fact that the programmer can move nodes around,
whereas in a stack, the nodes are fixed in Last-In First-Out (LIFO) order. The
transition is made painlessly since the hardware completes program linking with the
execution of one instruction, and very little effort is required on the part of the
programmer.
There are two immediate possibilities to discuss in using the BLWP instruction. For
simple subroutine linking, the following is an example :
CALLING PROGRAM

SUBROUTINE

ENTRY
BLWP @SUBA

PCSUBA

DATA WPSUBA
DATA PCSUBA

WPSUBA

ENTRY POINT
RTWP

SUBA

Note the double word vector pointed to by the BLWP operand, the values WPSUBA and
PCSUBA. These two DATA statements provide the memory addresses of these vectors. The
latter (PCSUBA) is the entry point, and is well defined. However , the WP value is
shown here without a definition. This raises a fundamental question: if there are many
programs operating together, suc h as TIBUG, possibly a user-written monitor, and a
collection of application programs and subroutines, who is responsible for managing
the workspaces? If each individual program is responsible, then the following
definition would be added to the above subroutine:
WPSUBA

EQU

Note this defines WPSUBA as M.A. FF70 16 and ties down one area of memory to the
subroutine; thus, no other program in the system can call this subroutine without
chancing some conflict by using the same workspace. Thus, it is reserved for one
subroutine.

5-8

~

A s econd approach is to code a value which is designated as a common workspace for
whoever is in control at the time. In the EQU statement above, the value could be, by
agreement, the common workspace. This implies that there are now two entities - the
reserved workspace, which must be carefully mapped out ahead of time so there is no
overlap, and the common workspace, of which there may be one or more, and whose status
is such that any program can use it, but if control leaves that program, then that
workspace is no longer considered needed, and thus can be used by another program.
Note the previous discussion assumes that the program code is in EPROM. If the code is
to be executed from RAM, then writing the program is simple; put the workspace at the
end of the program as a data area.
In either case, the user is responsible for partitioning his memory such that
workspaces do not overlap or interfere with TIBUG or the XOP's defined by TIBUG, along
with any user defined workspaces.
5.4.4 RETURN WITH WORKSPACE POINTER (RTWP)
The RTWP instruction can be used to both return from a program, and to link to a
program. Since the instruction reloads the processor WP, PC, ST registers from
workspace registers 13, 14, and 15, then the contents of these registers governs where
control will go. If those registers were initialized by a BLWP instruction, then the
action can be seen as a return, but if special values are placed in these registers,
the action can be viewed as a subroutine call. Actually, program calls are not
limited to a nesting structure, as in stack architectures, but are generalized so that
chains and even rings may be formed. The TIBUG monitor uses the RTWP instruction in
this manner. Using the "R" command, the user fills TIBUG's registers 13, 14, and 15.
Using the "E" command causes TIBUG to execute a RTWP instruction using the values in
these registers.
Since the RTWP does not affect the new workspace at all, there is no way for the
called program to return to the caller unless the caller had initialized the new
workspace registers before executing the RTWP. This type of program transfer is thus
in a "forward" direction only, and is usually suitable only for a monitor program in a
fixed location such as TIBUG .
5.4.5 EXTENDED OPERATION (XOP)
The XOP instruction works almost like a BLWP instruction, except that the address
containing the double-word vector area is between 004016 and 007F16, and is selected
by an argument of from 0 to 15, and that the new workspace register 11 is initialized
with the fully resolved address of the first operand of the XOP instruction. This
means that if the operand is a register, the actual memory address is computed and
placed in the new register 11.
The XOP instruction is meant as a "supervisor call" or special function operation. As
such, a programmer might wish to implement routines which perform some standard
process such as a character string search or setting the system timer, on the next
page.

5-9

CALLING PROGRAM

LI
XOP

RO, 11719
R0,2

*AT M.A.
*AT M.A.

0048:
004A:

*AT M.A.

10AE:
ENTRY

XOP TRAPS AND SUBROUTINE
FF903 TIMER ROUTINE WP
10AE3 TIMER ROUTINE PC
IDT
MOV
LI
SLA
ORI
LDCR
SBZ
SBO
RTWP

'TIMER'
•11,11
12' > 0100
11 ' 1
11 ' 1
11 '15
0

3

XOP 2
VECTORS
GET VALUE
ADDRESS 9901
SHIFT CLOCK COUNT
SET CLOCK MODE
START CLOCK
SET INTERRUPT MODE
ENABLE INT3 MASK

The main program requests 11719 clock counts, which is a desired time of 0.25 second.
This number is found by taking the system clock frequency, dividing it by 64 to find
the timer frequency, then reciprocating that to give the timer interval, then dividing
the desired time delay by the timer interval to find the clock counter value. It is
assumed here that XOP 2 is available for this function. The timer routine translates
the request and starts the system timer. One quarter second later, an interrupt
through INT3 will be generated.
TIBUG supplies definitions for XOPs O, 1, and 8 through 15, leaving 2 through 7
available for the user. XOP's 2 through 7 are programmed according to a scheme
described in subsection 5.9.
5.4.6 LINKED-LISTS
A linked list is a data organization where a collection of related data, called a
node, contains information which links it to other nodes. The prime example here is a
workspace register set, it contains sixteen words of data. If there are many
workspaces present at one time connected by BLWP instructions, then every register 13
contains the address of the previous workspace, forming a linked list. At the same
time, the BLWP also places the previous program counter value in register 14,
providing a means of returning back to the previous program environment.
For example, the E or execute TIBUG command uses the RTWP instruction to begin program
execution at the WP, PC, and ST values in current registers 13, 14, and 15. The R or
register inspect/change TIBUG command can be used to set up these registers prior to
the execute command. In the example in Figure 5-3, program PGMA is executed using the
TIBUG E command; it later gives control to program PGMB using the BLWP command. In
doing so, the processor forges links back to PGMA by placing return WP, PC, and ST
values in registers 13, 14, and 15 of PGMB. Likewise, PGMB branches to PGMC with
return links to PGMB forged into R13 to R15 of PGMC. Each can return to the previous
program by executing an RTWP instruction, and the processor can travel up the linked
list until PGMA is reached again.
5.5 COMMUNICATIONS REGISTER UNIT (CRU)
Input and output is mainly done on the TM 990/101M using the Communications Register
Unit or CRU. This is a separate hardware structure with its own data and control
lines. Thus the TMS 9900 microprocessor has one address bus, but two sets of control
and data busses. One set, the memory set, has a 16-bit parallel bidirectional data bus
and three control lines, MEMEN, OBIN, and WE.
The other set the CRU I/O set, uses two lines, one line for input (CRUIN), and one for
output (CRUOUT). There is one control line, CRUCLK, used to strobe a bit being output
on CRUOUT . A bit being input on CRUIN has no strobe and is simply sampled by the
microprocessor at its discretion.
5-10

CRU devices are run on one phase of the system clocks, and therefore, the rate of data
transfer on the CRUIN line is a function of the system clock. Since the CPU also uses
this system clock, it will sample the CRUIN line at a rate that is a function of the
system clock when doing a CRU read operation (executing a CRU read instruction - STCR
or TB).

PGMA
CALL PGMB

BLWP

R13-15

PGMB
BLWP

CALL
PGMC
RTWP

R13-15

RETURN
LINKS TO
PGMA

PGMC

RTWP
RETURN
LINKS TO
PGMB

R13-15

Figure 5-3. Linked List Example

5-11

Thus, the CRU data group consists of three lines - CRUIN, CRUOUT, and CRUCLK . The
address bus supplies CRU addresses as well as memory addresses; which operation being
performed is determined by the presence of the proper control signals. Memory
operations use address bits 0 through 14 externally, bit 15 is used inside the
microprocessor for byte operations. CRU operations, however, use only bits 3 through
14; bits O, 1, and 2 are set to zero, and bit 15 of an address is totally ignored.
When CRU instructions are executed, data is written or read through the CRUOUT or
CRUIN pins, respectively, of the TMS 9900 to or from designated devices addressed
via the address bus of the microprocessor.
The CRU software base address is maintained in register 12 (bits O to 15) of the
workspace register area. Only bits 3 to 14 of the register are interpreted by the CPU
for the CRU address, and this 12-bit value is called the CRU hardware base address .
When the displacement is added to the hardware base address, the result is the CRU bit
address further explained in paragraph 5 . 5.1.
The CRU address is maintained in register 12 of the workspace register area. Only bits
3 through 14 of the register are interpreted by the CPU for the desired CRU address,
and this 12-bit value is called the CRU bit address.
TM 990/101M devices driven off of the CRU interface include the TMS 9901 parallel
interface and the TMS 9902 serial interface, which are accessed through the CRU
addresses noted in Table 5-3. This table also lists the functions of the other CRU
addresses which can be used for on-board or off-board I/O use. Addressing the TMS 9901
and TMS 9902 for use as interval timers is explained, along with programming examples,
in subsections 5.9 .3 and 5.9 . 4. Further detailed informati on on these two devices can
be obtained from their respective data manuals.
Table 5-3.

TM 990/101M Predefined CRU Addresses
CRU Hardware
Bas e Address
(R12, bi ts 3-14)

Function

CRU Software
Base Address
(R12, bits 3-14)

0000
0020
0040
0050
0080
0090
OOA6

Status L.E . D
Unit I.D. Switch
TMS 9902, Main I/0 (Lower Half)
TMS 9902, Main I/O (Upper Half )
TMS 9901 Interrupt Mask, Sys tem Timer
TMS 9901 Parallel I/O
RESET Interrupt 6
TMS 9902, Auxiliary I/O (Lower Half)
TMS 9902, Auxiliary I/O (Upper Half)
RS-232 Handshaking Signals
Offboard CHU

ooco
OODO
OOEO
0100

0000
0040
0080
OOAO
0100
0120
014C
0180
01AO
01CO
0200

NOTES
1.

Besides theexamples used herein, Appendix J contains examples
of the various CRU instructions programmed to drive the on-board
TMS 9901 or monitor signals to the TMS 9901.

2.

The CRU software base address is equal to 2X the hardware base
address, or the hardware base address is 1/2 the software base
address.
5-12

-

5.5.1

CRU ADDRESSING

The CRU software base address is contained in the 16 bits of register 12 .
From the CRU softwa r e base address, the processor is able to determine the CRU
hardware base address and t~e resulting CRU bit address. These concepts are
illustrated in Figure 5-4 .
5.5.1 . 1 CRU Addr ess
The CRU bit address i s the address that will be placed on the address bus at
the beginning of a CRU instruction. This is the address bus value that ,
when decoded by hardware attached to the address bus, will enable the device
so that it can be driven by the CRU 1/0 and clock l ines.
The CRU bit
address is the sum of the displacement value of the CRU instruction
(displacement applies to single- bit instructions TB, SBO, and SBZ only) and
the CRU hardware base address in bits 3 to 14 of R12 . Note that the sign
bit of the eight- bit di splacemen t is extended to the left and added as part of
the address. The r esulting CRU hardware bi t address is then placed on address
lines A3 to A14 ; address lines AO to A3 will always be zeroes i n CRU
instruction exec ution.
5 . 5. 1. 2 CRU Hardwa r e Base Address
The CRU hardware base address is the value in bits 3 to 14 of R1 2 . For
instructions that do not specify a displacement (LDCR and STCR do not ) , the
CRU hardware base ad dress is the same as the first CRU bit address (see
above) . An important aspect of the CRU hardware base address is that it does
not use the least significant bit of register 12 (bit 15); this bit is ignor ed
i n der iving the CRU bit address .
5 . 5.1 . 3 CRU Software Base Address
The CRU software base address is the entire 16-bit contents of R1 2 . In
essence, this is the CRU hardware base address divided by t wo . Bits O, 1 ,
2, and 15 of the CRU software base addr e ss are i gnored in deriving the CRU
hardware base address and the CRU bit address .

(CONTENTS OF R 12)

CRU SOFTWAR E BAS E ADDRESS

_.........._

~

t
R12

I

0

0

~

0

____....,_
ZE ROES

Al

A4

AS

A6

0

0

0

0

A7

AB

A9

A 10

A 11

A 12

A13

0

0

0

0

0

0

'---

ADDR ESS
At 4 - - - LINES
0

0

../

~

I

+

IGNOR E

CRU HARDWAR E BASE ADDRESS
SIGN
EXTENDED
0

0

0

0

0

0

0

0

0

0

0

----'---

ALL Z EROES FO R
CRU OPER AT IONS

0

1

0

0

0

0

0

0

0

0

~

0

+ D ISPLACEMEN T"

0

../

CRU BIT ADDRESS

'The d isplacement added to the C RU h ardware base address is a signed e ight-bit value,
with sign extended, used only w hen executing one of th e single-bi t CRU instruct ions
(TB , SBO, and SBZI.

FI GURE 5- 4 .

CRU BASE AND BIT ADDRESSES

5-1 3

Because bit 15 of R12 is not used, some confusion can result in programming.
Instead of loading the CRU address in bits 0 to 15 of register 12 (e.g., LI
R12,>80 to address the TMS 9901 at CRU address 80 15), the programmer must
shift the base address value one bit to the left so that it is in bits 3 to 14
instead of in bits 4 to 15. Several programming methods can be used to ensure
this correct placement, and all of the following examples place the TMS
9901 bit address of 80 15 correctly in R12.
LI
LI

R12,>100
or
R12,>80*2

or
LI R12 ,>80
SLA R12, 1

PLACES >80 IN BITS 3 TO 14
MULTIPLY BASE ADDRESS BY 2 (NOT RECOGNIZED BY LINE-BYLINE ASSEMBLER)
BASE ADDRESS IN BITS 4 TO 15
SHIFT BASE ADDRESS ONE BIT TO THE LEFT

From a programming standpoint, it may be best to view addressing of the CRU
through the entire 16 bits of R1 2. In this context, blocks of a maximum of 16
CRU bits can be addressed, and in order to address an adjacent 16-bit block, a
value of 002015, must be added or subtracted from R12. For example, with R12
co ntaining 0000 1 5, CRU bits 0 to F 15 can be addressed. By adding 0020 15 to
R12, CRU bits 10 15 to 1F16 can be addresses, etc .
5.5.2 CRU Timing
CRU timing is shown in Figure 5-5. Timing phases (¢1 to .¢4) are shown at the
top of the figure. The CRU address is valid on the address bus beginning at
the start of of ¢2, and stays valid for eight timing phases (two clock
cycles). At the start of the next ¢2 phase, CRUCLK at the TMS 9900 goes high
for two phases to provide timing for CRUOUT sampling. Note that for LDCR and
STCR instructions, the address bus is incremented for each data bit to be
output or input . For input operations, the address is placed on the address
bus at the beginning of phase ~2, and the input is sampled between phases ~4
and .¢1.

5.5.3 CRU Instructions
The five instructions that program the CRU interface are:
•

LDCR

Place the CRU hardware base address on address lines A3 to A14.
Load from memory a pattern of 1 to 16 bits and serially
transmit this pattern through the CRUOUT pin of of the TMS
9900. Increment the address on A3 to A14 after each CRUOUT
transmission.
Place the CRU hardware base address on lines A3 to A14. Store
into memory a pattern of 1 to 16 bits obtained serially at the
CRUIN pin of the TMS 9900. Increment the address on A3 to A14
after each CRUIN sampling.

•

STCR

e

SBO

Place the CRU hardware base address plus the instruction's
signed displacement on address lines A3 to A14. Send a logical
one through the CRUOUT pin of the TMS 9900.

•

SBZ

Place the CRU hardware base address plus the instruction's
signed displacement on address lines A3 to A14. Send a logical
zero through the CRUOUT pin of the TMS 9900.

e

TB

Place the CRU hardware base address plus the instruction's
signed displacement on address lines A3 to A14. Sample the
5-14 .

•

GROIN pin of the TMS 9900 and place the bit read into ST2, the
Equal Bit of the Status register.
NOTE
Examples of single- and multi-bit CRU instruction execution using
the TMS 9901 are presented graphically in Appendix J.
5,5,3,1 CRU Multibit Instruction
The two multibit instructions, LDCR and STCR, address the CRU devices by
placing bits 3 through 14 (hardware base address) of R12 on address lines A3
through A14. AO, Al, and A2 are set to zero for all CRU operations. The first
operand is the source field address and the second operand is the number of
bits in the operation.
If the length is coded as from 1 through 8 bits, only the left byte of the
source or recei ving field takes part in the operation, and bits are shifted in
or out from the least significant bit of that left byte. Thus a LDCR R2, 1
outputs bit 7 of R2 to the CRU at the address derived from register 12. An
STCR R5,2 would receive two bits of data serially and insert them into bit 7
and then bit 6 of register 5. The CRU address lines are automatically
incremented to address each new CRU bit, until the required number of bits are
transferred. In an STCR instruction, unused bits of the byte or word are
zeroed.
In this last example, bits 0-5 are zeroed, the right byte is
unaffected.

¢2

,PJ

I
I

I
I
I
AO AIS

UNKNOWN

IX

I

CRUCLK

CRU B IT ADDR ESS n

I

UNKNOWN

~
I

~

...::> -...
~

=

- ~

C RUIN

Ix:

I

I

I

I

I

I

CRUOUT

CRU ADDRESS n. t

I

~~~~1~~~r-l
I

ix

I

CRU DATA OUT n

I

:x

:;. .,___ __,

I

ll.__~1~~---J:1--~-+-~~~~+-~~

CRU DATA OUT n • 1

I
I

y

:;,___

-f'

I
I

~o?~1f~~E~Jo:xl"O'l7l"!~~OOOl:'10\r""fCRU OUTPUT

CRU INPUT

FIGURE 5-5. TMS 9900 CRU INTERFACE TIMING
5-15.

An LDCR loads the CRU devi ce serially from memory over CRUOUT timed by CRUCLK. An STCR
stores data into memory obtained serially through CRUIN from the addressed CRU device .
Figures 5-6 and 5-7 show this operation graphically. The TMS 9901 i s used in the
example as the CRU device because it most simply shows the bit transfers involved.

LI

Rl 2,> 200

LDCR
0
0

0

LOAD CRU BASE ADDRESS > 100 IN BITS 3 TO 14 OF R12

R5,6

6 BITS TO CRU

2

3

4

5

6

7

0

0

0

0

1

0

8

9

10

11

0

0

0

0

I

0

0

0

0

0

0

0

0

1

1

0

0

0

RS

0

0

0

1

1

7

8

..___
I 1_ _ .1__._
I o____._

13

14

15

1

1

0

0

'-020C

0

0

0

0

-0200

0

1

0

1

' ·3185

I

1

2

----~I----~0~1__.__
[ _
o

--

r

I

12

0
0

r

0

0

0

0

I

1 ___.___[_o ...__
J o__._J_ 1 __.____
J _1

15

..__1___._
J _ 1 _,__
[ ___..
o I
0 • CRU Address > 100

IGNORE

2

3

4
5 • CRU Address ',105
6

7

8
9

A
B

c
D
E
F

8 BITS OR LESS - BYTE ADDRESS

AOOOl

10

9 BITS OR MORE - WORD ADDRESS

11

NOTE: EXAMPLES OF CRU INSTRUCTIONS ADDRESSING THE

12

434 TMS 9901 ARE SHOWN IN APPENDIX J.

Figure 5-6.

LDCR Instruction

5--1-6

I
LI

R12,> 120*2

STCR

R4, 10

0

LOAD CRU BASE ADDRESS > 120 IN BITS 3 TO 14 OF R12
10 BITS FROM CRU TO R4

2

3

4

5

6

7

8

9

10

11

0

0

0

0

1

0

0

0

0

o

0

1

0

0

1

0

0

0

,

0
0

0

0

0

0

0

•

0

0

1

1

0

1

0

0
R4

0

j

1

0

1

0

I

I

6
0

0

0

0

12

I
I

13

14

15

0

0

>020C

1

,

0

0

0

0

>0240

0

1

0

0

>3684

15

0
0 -CR U Address >120

ZERO FILL
UNUSED LEFT-SIDE BITS

1

2
3
4

5

6

7
8
9 -<:RU Address >129
A

NOTES:
8 BITS OR LESS - BYTE ADDRESS
9 BITS OR MORE - WORD ADDRESS
THE MULTIPLICATION IN THE DESTINATION OPERAND !> 120*2)
IS NOT RECOGNIZED BY THE TM 990/402 LINE-BY-LINE ASSEMBLER.
THIS MULTIPLICATION IS AN EXAMPLE OF THE RELATIONSHIP OF
THE CONTENTS OF THE CRU BASE ADDRESS TO THE CONTENTS
OF REGISTER 12. EXAMPLES OF CRU INSTRUCTIONS ADDRESSING THE
TMS 9901 ARE SHOWN IN APPENDIX J.

Figure 5-7. STCR Instruction

5-17

B

c
D

E
F

10

5.5.3.2 CRU Single-Bit Instructions
The three single-bit instructions are SBZ (set bit to zero), SBO (set bit to one), and
TB (test bit). The first two are output instructions, and the last one is an input
instruction. All three instructions have only one operand, which is assembled into an
eight-bit signed displacement to be added to the CRU hardware base address to provide
the CHU bit address. The SBZ instruction sets the addressed bit to zero (zero on
CRUOUT), and the SBO instruction sets the addressed bit to one (one on CRUOUT). The TB
instruction reads the logical value on the CRUIN line and places this value in bit 2
(EQ) of the status register; the test can be proven by using the JEQ or JNE
instructions.
The operand value is treated as a signed, eight-bit number, and thus has a range of
values of -128 to +127. This number is added to the CRU hardware base address derived
from bits 3 to 14 of R12, and the result is placed on the address lines. This process
is illustrated in Figure 5-8.
Notice that after execution of a TB instruction, a JEQ instruction will cause a jump
if the logic value on CRUIN was a one, and JNE will cause a jump if the logic value
was a zero.

SOFTWARE BASE ADDRESS
HARDWARE BASE ADDRESS
0

1

2

x

x

x

3

4

6

5

8

7

9

10

11

8

0

'

0

2

I

0

v

4

3

5

.1

+

9

10

11

12

15

x

13

14

I

W12

15
SIGNED
DISPLACEMENT

7

BITS SIGN
EXTENDED

I I I

14

I I I I

,,~,

1

13

I

DON'T CARE

0

12

6

u
7

8

9

10

11

I I .1 I I

12

13

14

I I

ADDRESS BUS

I

SET TO ZERO
FOR ALL CRU
OPERATIONS

Figure 5-8 .

EFFECTIVE CRU BIT ADDRESS

Addition Of Displacement And R12 Contents To Drive CRU Bit Address

5-18

5.6 DYNAMICALLY RELOCATABLE CODE
Most programs written for the TM 990/101M will contain references in memory. These
references are given by means of a symbolic name preceded by an at (@) sign. Examples
are @>FEOO (M.A . FE0016 1 recognized by the LBLA) or @SUM (recognized by a
symbol-reading assembler, not the LBLA).
For example, a short program, located at M. A. 090016 to 090F16 , adds t wo memory
addresses then branches to the monitor:
M.A.
0900
0904
0908
090C
090E

MOV
A
B
DATA
DATA

@>090C,R1
@>090E,R1
@>0080
100
200

MOVE VALUE AT M.A. 090C TO R1
ADD VALUE AT M.A . 090E TO R1 (R1:ANSW)
RETURN TO MONITOR
FIRST NUMBER
SECOND NUMBER

In this program, a number in EPROM is moved to a register in RAM, and another number
in EPROM is added to that register (the destination of an add must be in RAM in order
for the sum to be written into it). If it is desired to move this entire program to
another address (such as to RAM for debugging purposes to allow data changes as
desired), then the locations in the code must be changed to reflect the new addresses.
For example, to relocate the above example to start at address FC0015 1 each of the
addresses of the numbers must be changed before the program can execute; otherwise,
the program will try to access numbers in M.A. 090C16 and 090E16 when they have been
relocated to M.A. FCOC16 and FCOE16 respectively .
For a variety of reasons, it may be advantageous to have code that is
"self-relocating," that is, it can be relocated anywhere in memo ry and execute
correctly. Such "position-independent" or "dynamic-relocating" code is of great
advantage when the code is programmed into EPROM. In this manner, the EPROMs can be
installed in any socket, responding to any address, and the program will still execute
correctely. Such programs are possible with the TM 990/101M by merely beginning the
program with the code segment shown below (register 10 i s used i n th e following
examples). Thereafter, memory addresses can be indexed, relative to t he beginning of
the program (using R10 at the index register, in this case ) . This c ode i s shown in
Figure 5-9.

Base
Reg.
Setup

Reloeatable
Program

M.A.
0000
0004
0008
OOOA
OOOE
0012
0014
0018

OPCODE/OPERANDS
LWPI
FEOO
LI
R10,START
JEQ
RELOC
CLR
R10
JMP
STARTX
RELOC
LI
R10,>045B
BL
R10
RELOCX AI
R11,START-RELOCX
MOV
R11,R10

COMMENTS
RO AT M.A. FEOO
LOOK AT START ADDR.
IF NOT BIASED, NEED RELOCATING
LOADER HAS BIAS, CLEAR BASE REG.
GO TO PROGRAM
B *R11 OPCODE IN R10
PC VALUE TO R11
PC-10 =PROGRAM START
PROGRAM START TO R10

001E
0012
0016
001A
001C

STARTX MOV
A
B
DATA
DATA

MOVE FIRST NUMBER TO R1
ADD 20 NO. TO R1, ANSW IN R1
RETURN TO MONITOR
FIRST NUMBER
SECOND NUMBER

oooc

I

START

Fi sure 5-9.

@>001A(R10),R1
@>001C(R10),R2
@>0080
100
200

Exam21e Of Prosram With Co dins Added to Make it Relocatable

5-19

This coding first sets up a program base register which computes the address of the
beginning of the program. This is accomplished by:
•

establishing the beginning workspace register address with LWPI

•

placing the opcode for the instruction B *R11 in the designated index
register address (R10 above)

•

execute a branch and link to R10; this places the address of the next instruction following BL R10 into register 11; a branch to R10 means a return
indirect through R11

•

compute the beginning address of the program by subtracting 1016 from the
address in register 11.

•

move this beginning address to R10, allowing R11 to be further used as a
linking register.

•

Index all future relocatable addresses using R10.

There are several considerations. Absolute addresses (e . g., beginning of monitor at
008016) need not be indexed, and other types of memory indexing should consider the
contents of the base register; it may be necessary to add the contents of the base
register to another indexing register. Also, an immediate load of an address into a
register will require that the base address in the index register be added to the
register also . For example:
LI
A

R2, >0980
R10,R2

ADDRESS OF VALUES IN R2
ADD BASE ADDRESS

Figure 5-10 is an example of a program that searches a table of numbers for a value.
The example is shown in both relocatable and in non-relocatable code, for comparison.
Symbolic addressing is used.

*NON SELF-RELOCATING
iNO BASE REGISTER USED
LI
R3,TABLE POINT TO TABLE

*

*REMAINDER OF CODE NOT
MOV @COUNT,R2
SEARCH C
R1.,*R3+
JEQ FOUND
DEC R2
JNE SEARCH
COUNT
TABLE

INDEXED
GET COUNT
(R1) IN TABLE?
YES
NO, DEC COUNTER
LOOK AGAIN

DATA 6
DATA 12,15,59,62,73,92
Figure 5-10.

*SELF-RELOCATING
*R10 IS BASE REGISTER
LI R3, TABLE
A R10,R3
*REMAINDER OF CODE INDEXED
MOV @COUNT(R10),R2
SEARCH C R1,*R3+
JEQ FOUND
DEC R2
JNE SEARCH
COUNT
TABLE

POINT TO TABLE
ADD BASE REG.
GET COUNT
(R1) IN TABLE?
YES
NO, DEC COUNTER
LOOK AGAIN

DATA 6
DATA 12,15,59,62,73,92

Examples of Non Self-Relocating Code and
Self-Relocating Code

5-20

Great care must be taken with B, BL, and BLWP. If linking to other modules is needed,
these modules must be part of a system which is linked together by the linker program
(e.g., TXLINK on the FS990 system), and all modules must be coded as self-relocating.
When programming the EPROM's, the code must be loaded such that the address START has
the value~' i.e. The code must appear biased at location 0000 16 .
5.7 PROGRAMMING HINTS
In any programming environment there are several ways to accomplish a task. Table 5-4
contains alternate coding practices; some have an advantage over conventional coding.

Table 5-4.

CONVENTIONAL
CODE

PURPOSE
Compare Register Contents to
Increment A Register by 4

Alternate Programming Conventions

o

CI
RX,O
INCT RX
INCT RX

Access old workspace
registers
Swap two registers
Clear a register

MOV
MOV
MOV
CLR
CLR

RX,RHOLD
RY,RX
RHOLD,RY
RX
RX

ALTERNATE
CODE

ALTERNATE CODE
ADVANTAGE

MOV

c

RX,RX
*RX+,*RX+

Saves one word
Saves one word

MOV

@N (R13), R1

XOR
XOR
XOR
XOR
SUB

RX,RY
RY,RX
RX,RY
RX,RX
RX,RX

N is twice the
number of the
old register
wanted
Saves a register: "RHOLD"
Not needed
(None)
(None)

5.8 INTERFACING WITH TIBUG
The TIBUG monitor provides a starting point for the programmer to consider when
looking for program examples. The monitor contains some basic user facilities, and the
user will probably enter and exit programs through TIBUG.
5.8.1 PROGRAM ENTRY AND EXIT
To execute a program under TIBUG, use the "R" and "E" commands as explained in Section
3 of this manual.
Exit from a program to TIBUG can be through:
B @>0080
TIBUG will print the prompting question mark. Note that the power-up initialization
routine is not entered; instead, control goes directly to TIBUG's command scanner.

5-21

I/0 USING MONITOR XOP's

5.8.2

5.8.2.1 Character I/O
Four XOP's deal specifically with character I/O:

•
•

•
•

Echo Character
Write Character
Read Character
Write Message

XOP
XOP
XOP
XOP

11
12
13
14

The echo XOP (11) is a read character XOP (13) followed by a write character XOP (12).
The following code reads in a character from a terminal. If an A or E is found, the
character is writen back to the terminal and program execution continues; otherwise,
the program loops back waiting for another keyboard entry.
GETCHR

OK

XOP
CI
JEQ
CI
JEQ
JMP
XOP

READ CHARACTER
COMPARE R1 to ASCII "A II
IF "A" FOUND JUMP
COMPARE R1 TO ASCII "E"
IF "E" FOUND, JUMP
RETURN TO READ ANOTHER CHARACTER
WRITE CHARACTER AS ECHO

R1, 13
R1 , >4 100
OK
R1 ,>4500
OK
GETCHR
R1, 12

XOP 14 causes a string of characters to be written to the terminal. Characters are
written until a byte of all zeroes is found.
XOP 13 reads one character and stores it into the left byte of a work; the right byte
is zero fi lled. The previous coding example could also have been completed with the
following:
OK

XOP

R1, 14

Instructions are written in uninterrupted form; thus, messages should be grouped in a
block separated from the continuous executable code. Each message must be delimited by
a byte of all zeroes:
**MESSAGES
CRLF
BYTE
LF
BYTE
MSG1
TEXT
BYTE
MSG2
TEXT
BYTE
MSG3
TEXT
BYTE
MSG4
TEXT
BYTE
MSG5
TEXT
BYTE

>OD
>OA,>00
'BEGIN PGMA'
0

'END PGMA'
0

'#ERRORS (IN HEX):'
0

'ERROR EXP VALUE='
0

',RCV VALUE='
0

5-22

Note in the preceding example, that if it is desired to send a carriage return and a
line feed, use the following: XOP @CRLF,14. But if only a line feed is wanted, use :
XOP @LF, 14.
5.8.2.2 Hexadecimal I/0
Three XOP's handle hexadecimal numbers.

•
•
•

Write one hexadecimal character
Read a four-digit hexadecimal word
Write four hexadecimal characters

XOP 8
XOP 9
XOP 10

Using the message block in paragraph 5.8.2.1, an example code segment might be:
*ERROR ROUTINE
ERROR
XOP
XOP
XOP
XOP
XOP
XOP

@MSG4, 14
R1, 10
@MSG5, 14
R2, 10
@CRLF, 14
@LF, 14

START ERROR LINE
PRINT CORRECT EXPECTED VALUE
MORE ERROR LINE
PRINT ERRORED RCV VALUE
DO CARRIAGE RETURN/LINE FEED
ONE MORE LF FOR DOUBLE SPACE

XOP 8 is actually called four times by XOP 10, after positioning the next digit to be
written into the least significant four bits of the work register.
The following shows how to input values to a program by asking for inputs from the
terminal.
GET
OK
NULL
ERROR
DEFMSG
ERRMSG

XOP
DATA
A
JMP
LI
XOP
JMP
XOP
JMP
TEXT
BYTE
TEXT
BYTE

R4,9
NULL,ERROR
R3,R4

CALL TO GET HEX # ROUTINE
NO INPUT/BAD INPUT ADDRESSES
ADD OLD NUMBER IN
CONTINUE PROGRAM
LOAD DEFAULT VALUE
PRINT DEFAULT MESSAGE

xxx

R4,>3AF1
@DEFMSG, 14
OK
@ERRMSG,14
GET

PRINT ERROR MSG
TRY AGAIN

'DEFAULT USED'
0
'ERROR: USE 0-9, A-F ONLY'
0

Note that the XOP 9 routine stores only the last four digits typed before the
termination character (delimiter) is typed . This means if a wrong number is entered,
continue typing until four correct digits are entered; then type a delimiter (space,
carriage return, or minus sign). Typing fewer than four digits total (but at least one
digit) causes leading zeroes to be inserted. Typing only a delimiter gives control to
the first address following the XOP, and typing an illegal character at any time
causes control to go to the address specified in the second word following the XOP
call.

5-23

5.9

INTERRUPTS AND XOPS

5.9.1 INTERRUPT AND XOP LINKING AREAS
When an interrupt or XOP instruction is executed, program control is passed to WP and
PC vectors located in lower memory. In t errupt vectors are contained in M.A. 0000 16 to
003F 16 ; and XOP vectors are contained in M.A. 0040 16 to 007F 16 . User-available
i nterrupt and XOP vectors are preprogrammed in the EPROM chip with WP and PC values
that allow the user to implement interrupt service routines (I SR's ) and XOP service
routines (XSR's). This includes programming an intermediate linking area as well as
the ISR or XSR code.
When an interrupt or XOP is exec ut ed, it first passes control to the vector s which
point to the linking area. The linking area dire cts execution to th e actual !SR or
XSR. The linking areas are shown in Table 5-5. The linking area is designed to leave
as much space free as possible when not using all the interrupts. That is , the most
frequently used areas are butted up against TIBUG area, the least frequently used
areas extend downward into RAM.
Return fr om the ISR or XSR is through return vectors in R13, R14, and R15 at the ISR
or XSR workspace and at the linking area workspace.
How to program these linking areas is explained in the following paragraphs.
NOTE
Interrupts 3 and 4 are used by the timers at the TMS
9901 and TMS 9902 respectively.

Table 5-4.

Preprogrammed Interrupt And User XOP Trap Vectors
VECTORS

VECTORS
M.A.
0000
0004
0008

oooc

0010
0014
0018
001A
0020
0024
0028
002C
0030
0034
0038
003C

Int.
INTO
INT1
INT2
INT3
INT4
INT5
INT6
~NT7

INT8
INT9
INT10
INT11
INT1 2
INT13
INT14
INT15

WP

PC

M.A.

XOP

WP

PC

TIBUG
FF5A
FF4E
FF8A
FF7E
FF72
FF66
FEEE
FEE2
FED6
FECA
FEBE
FEB2
FEA6
FE9A
FE8E

TIBUG
FF7A
FF6E
FFAA
FF9E
FF9 2
FF86
FFOE
FF02
FEF6
FEEA
FEDE
FED2
FEC6
FEBA
FEAE

0048
004C
0050
0054
0058
005C

XOP2
XOP3
XOP4
XOP 5
XOP6
XOP7

FF48
FF3A
FF2C
FF1E
FF10
FF02

FF5A
FF4C
FF3E
FF30
FF22
FF14

5-24

Table 5-5.

M. A.

0-1

2-3

4-5

INT1 5
INT13
INT12
INT11
INT9
INT8
INT7
XOP7
XOP5
XOP4
XOP3
XOP2
INT2
INT6
INT5
INT4

INT15
INT13
INT12
INT11
INT9
INT8
INT7
XOP6
XOP5
XOP4
XOP3
XOP2
INT2
INT6
INT5
INT4

INT14
INT13
INT12
INT10
INT9
INT8
XOP7
XOP6
XOP5
XOP4
XOP3
XOP2
INT1
INT6
INT5
INT3

I

FET90
FEAO
FEBO
FECO
FEDO
FEEO
FEFO
FFOO
FF10
FF20
FF30
FF40
FF50
FF60
FF70
FF80
FF90
FFAO
FFBOI
FFFB

I nter rupt and User XOP Linki ng Areas
BYTE
6-7
8-9
USER RAM AREA
INT15
INT14
INT13
INT11
INT10
INT9
INT7
XOP7
XOP6
XOP5
XOP4
XOP3
INT2
INTl
INT6
INT4
IN'f3

INT14
INT13
INT12
INT10
INT9
INT8
XOP7
XOP6
XOP5
XOP4
XOP3
XOP2
INT1
INT6
INT5
INT3

A-B

C-D

E-F

INT15
INT14
INT13
INTl 1
INT10
INT9
INT7
XOP7
XOP6
XOP5
XOP4
XOP2
INT2
INT1
INT6
INT4
INT3

INT15
INT14
INT12
INT11
INT10
INT8
INT7
XOP7
XOP6
XOP5
XOP3
XOP2
INT2
INT1
INT5
INT4
INT3

INT15
INT14
INT12
INT11
INT10
INT8
INT7
XOP7
XOP6
XOP4
XOP3
XOP2
INT2
INT1
INT5
INT4
INT3

TIBUG WORKSPACE

5.9.1.1 Interrupt Linking Areas
When one of the programmable interrupts (INT1 to INT15) is executed, it traps to an
interrupt linking area in RAM. Each linking area consists of s ix words (12 bytes) as
shown in Figures 5-11 and 5-12. The first three words contain the last three registers
of the called interrupt vector workspace (R13, R14, and R15), and the second three
words, located at the interrupt vector PC address, are intended to be programmed by
the user to contain code for a BLWP instruction, a second word for the BLWP
des tina.~ion address, and an RTWP instructi on code (all three words to be entered by
the user). When the ISR is completed, control returns to this linking area where the
return values (to the interrupted program) are loaded into the linking area's three
registers (R13 to R15), then the BLWP instruction (at the PC vector address) is
executed using the M.A. provided by the user (the BLWP instruction consists of two
words, the BLWP operator and the destination address; the destination address points
to a two-word area also programmed by the user).
Return from the interrupt service r outine is through the RTWP instruction (routine's
last instruction). This places the (previous) WP and PC values at the time of the BLWP
instruction (in the six-word linking area) into the WP and PC registers. Thus, the
RTWP code that follows the BLWP instruction will now be executed, causing a second
return routine to occur, this time to the interrupted program using the return values
in R13, R14, and R15 of the interrupt link area. This is shown graphically in Figure
5-11 .

5-25

INTERRUPT NO. 1
RECOGNIZED

M.A. 0000

0002
0004
0006

I

• -- - - FIRST REGISTER
IN WORKSPACE

RO

FF5A

7

WP
PC
FF5A
FF7A

&WORD INTERRUPT LINK AREA

~-R_1_3_1_o_L_D_w_P_l___.
{

Rl4 (OLD PC)

LERRUPT
VECTOR S IN
EPROM

R 13 FF5A
R1 4 FF7E
R15 !O LD ST)

zzzz
INTERRUPTED
PROGRAM

••
•

RTWP

INTERR UPT SERVICE ROUTINE

1,2
3.4

INTERRUPT EXECUTION TRAPS TO 6-WO RD INTERR UPT LINK AREA.
BLWP EXECUTED TO 2-WORD VECTORS TO INTERRUPT SERVI CE ROUTINE ( ISR)

5

RTWP FROM ISR TRAPS BACK TO 6-WORD LINK AREA .

6

RTWP FROM LIN K AREA RETURNS BACK T O INTERR UPTED PROGRAM .

~

= LI NKAGE PROGRAMMED BY USER

Figure 5-11.

Interrupt Sequence

5-26

Each interrupt linking area is set up so that it can be programmed in this manner. In
summary, each six-word linking area can be programmed as follows:
•·

Determine the location of the linking area as shown by the WP and PC vectors
in Table 5-4.

•

The PC vector will point to the last three words of the six-word area. The
user must program these three words respectively with 0420 16 for a BLWP instruction, the address (BLWP operand) of the 2-word vector pointing to the
interrupt service routine, and 0380 16 for an RTWP instruction as shown in
Figure 5-12.

•

At the vector address for the BLWP operand, place the WP and PC values
respectively of the interrupt handler.

EXAMPLE USING INT1 LINKING AREA (WP = FF5A. PC = FF7A)

M .A .

(ACTUAL ADDRESS OF RO OF INTERR UPT V ECTOR

FF5 A

WP)

•
•
•

TO BE
PROGRAMMED
BY USER

FF 74

R13 (OLD WP)

FF 76

R14 (OLD PC)

FF 78

R15 (OLD STI

FF7 A

0420 (BLWP)

l

FF7

c

FF7 E

xx xx

)

INT1 VECTOR PC ADDRESS !CONTAINS BLWPI
-

0380 (RTWPI

USED TO SAVE RETURN V ALU ES (TO
INTERRUPTED PROGRAM)

~

ADDRESS OF 2 - WORD VECTOR POINTING TO
WP AND PC VALUES OF ISR
RETURN PC VALUE IN ISR POINTS TO THIS
RTWP INSTR .

NOTE
· DO NOT USE RO-R12 OF THE LINKING AREA WORKSPACE,
BECAUSE THE OVERLAPPING STRUCTURE WILL DESTROY
THE CONTENTS OF A LINKING AREA FOR ANOTHER INTERRUPT OR XOP.

Figure 5-12.

Six-Word Interrupt Linking Area

5-27

Example coding to program the linkage to the interrupt service routine for INT1 is as
follows:
*PROGRAM POINTER TO INT1
AORG
>FF7A
DATA
>0420
DATA
>FAOO
DATA
>0380

SERVICE ROUTINE FOLLOWING BLWP INSTRUCTION
INT1 PC VECTOR ADDRESS
HEX VALUE OF BLWP OP CODE
LOCATION OF 2-WORD VECTORS TO ISR (EXAMPLE)
HEX VALUE OF RTWP OP CODE

*PROGRAM POINTER TO 2-WORD VECTORS TO INTERRUPT SERVICE ROUTINE (EXAMPLE)
AORG
>FAOO
WP OF INTERRUPT SERVICE ROUTINE (EXAMPLE)
DATA
:>FBOO
DATA
>FA04
PC OF INTERRUPT SERVICE ROUTINE (EXAMPLE)
*INT1 ISR FOLLOWS (BEGINS AT M.A.

FA04)

The interrupt service routine which begins at M. A. FA04 16 will terminate with an RTWP
instruction.
5.9.1.2 XOP Linking Area
The XOP linking area contains seven words (14 bytes), of which the first two and the
fourth words must be programmed by the user. Each XOP vector pair contains the pointer
to the new WP (in the first word) and a pointer to the new PC (in the second word)
which points to the first instruction to be executed.
In the seven-word XOP linking area, the first word is the destination of the XOP PC
vector. The last three words are the final three registers (R13, R14, and R15) of the
linking area workspace which will contain the return vectors back to the program that
called the XOP. The third word of the seven-word area is R11, which contai ns the
parameter being passed to the XOP service routine. This is shown in Figure 5-13.
For example, when XOP2 is executed, the PC vector points to the BLWP
at M.A. FF5A 16 in Figure 5-13. This executes, transferring
preprogrammed WP and PC values at the address in the next word
Figure 5-13). To obtain the parameter passed to R11 of the vector WP
Figure 5-13), use the following code in the XOP service routine:
t-K)V *R14+,R1

instruction shown
control to the
(YYYY as shown in
(M.A . FF5E 15 in

MOVE PARAMETER TO R1

This moves the parameter to R1 from the old R11 (the old PC value in R14 was pointing
to this address following the BLWP instruction immediately above it, effectively to
R11), and increments the XOP service routine PC value in its R14 to the RTWP
instruction at M. A. FF60 15. Thus an RTWP return from the XOP service routine will
branch back to the RTWP instruction at FF60 15 which returns control back to the
instruction following the XOP .

5-28

EXAMPLE USING XOP 2 LINKll\/G AREA !WP

FF 48 , PC

M A

FF5A)

(ACTUAL ADDRESS OF RO OF XOP2
VECT OR WPI

FF 48

•
•
•
-

0420 (BLWP)

FF5 A
TO BE
PROGRAMMED
BY USER

[

FF5 c

YYYY

FF5 E

Rl 1 IPARAMETERI

FF60

0380 IRTWPI

FF6 2

R13 (0LDWPI

FF6 4

R 14 (OLD PCI

FF 6 6

Rl5 IOLD STI

Figure 5-1 3.

~

XOP2 VECTOR PC POINTS TO HERE
POINTS TO XSR WP & PC VECTORS

14--· -

-

XOP SOURCE ADDA PARAMETER
RTWP BACK TO CALLING PROGRAM

l

USED TO SAVE RETURN VALUES
ITO INTERRUPTED PROGRAM)

Seven-Word XOP Interrupt Linking Area

In summary, the seven-word XOP linking a rea can be programmed as follows :
•

Determine the value of the PC vector for the XOP as shown in Table 5-4.

•

The PC value will point to the first word of the seven-word linkage area .
The user must program three of the first four words of this area
respectively with 0420 16 for a BLWP instruction, the address of the two-word
vector that points to the XOP service routine, ignore the third word, and
0380 16 for an RTWP instruction in the fourth word .

•

At the address of the BLWP destination in the second word, place the WP and
PC values respectively to the XOP service routine.

5-29

An example of coding to program the XOP linkage for XOP 2 as shown in Figure 5-13 i:
as follows:
*PROGRAM POINTER TO XOP SERVICE ROUTINE AT XOP2 LINK AREA
AORG
>FF5A
XOP2 PC VECTOR ADDRESS
DATA
>0420
HEX VALUE OF BLWP CODE
DATA
>FAOO
LOCATION OF 2-WORD VECTORS TO XSR (EXAMPLE)
IGNORE
DATA
0
HEX VALUE OF RTWP CODE
DATA
>0380
*PROGRAM POINTER TO 2-WORD VECTORS TO XOP2 SERVICE ROUTINE (EXAMPLE)
AORG
>FAOO
LOCATION OF VECTORS
DATA
>FBOO
WP OF XOP SERVICE ROUTINE (EXAMPLE)
DATA
>FA04
PC OF XOP SERVICE ROUTINE (EXAMPLE
*XSR CODE FOLLOWS (BEGINS AT M.A.

FA04)

At the XOP service routine, the following code uses the PC return value (i~ R14 of the
XOP service routine workspace) to obtain the parameter in R11 (in the link area) a~
well as set the r et urn PC value in R14 (in the XOP service routine workspace) to the
RTWP in the link area:
MOV

*R14+,R1

MOVE OLD R11 CONTENTS TO Rl OF XOP SERVICE ROUTINE

Now R14 points to the RTWP ins truction in the link area. The last instruction in the
XOP service routine is RTWP. RTWP execution causes a return to the link area wher e a
second RTWP executes, returning control to the next instruction following the XOP.
5.9 . 2 TMS 9901 INTERVAL TIMER INTERRUPT PROGRAM
A detailed discussion of the TMS 9901 interval timer can be found in the TMS 990 1 dat
manual. There are several possible sequences of coding that can program and enab le th~
interrupt 3 i nterval timer, and s ince the timer has a maximum per iod of 349
milliseconds before issuing an interrupt , the programmer must decide whether to set
the interval period in the calling program or in the code handling the interrupt. If
the interrupt period desired is longer than 349 milliseconds, then it may be
advantageous to reset the timer in the interrupt subroutine which also triggers the
interrupt and returns control back to the interrupted program. In any case, the timer
must be initially set and triggered following the general sequence below:
1.

Set the CRU address of the TMS 9901 in bits 3 to 14 of R12.

2.

Set up the interrupt 3 linking area.

3.

Enable the c l ock interrupt at the TMS 9901 (interrupt 3).

4.

Set the Status Register interrupt mask to a value of 3 or greater.

5.

Set a register to the value of the interval desired (bits 1 to 14) with bit
15 se t to one to enable the clock as shown in Figure 5-14. This figure shows
the code and a representation of the CRU for setting a time of 250 milliseconds and for setting the TMS 9901 to the clock mode. The first bit
serially brought in on the CRU will be a value of one in bit 15 of the
register whi ch sets the TMS 9901 to the clock mode; successive bits (1 to
14) then set the clock interval value. The final bit brought in triggers the
timer.

5-30

6.

When the interrupt occurs, the interrupt handler must reset the
the TMS 9901 before returning to the interrupted program .

i~terrupt

.,
LI

0
R1

N

CRU ADDRESS OF TMS 990 1 12 x > so= > 1001

A12, > 100

LI

Al, >seaF

CLOCK, >2DC7 COUNTS, AND SET CLOCK MODE BIT

LDCFI

R1. 16

SET CLOCK VALUE AT CLOCK REGISTER

2
0

3

..

5
0

8

7

8

9
0

10
0

11
0

12

13

14

15
> sasF

CAU

TMS 9901

ADDA

ASSIGNMENT

1 • CLOCK MODE

CLK1 TO CLK14 • > 2DC7 • 11. 719

80

11,719/46,875Hz • 250MS

81

CLKl

82

CLK2

•
•
•
SE
SF

NOTE:
THE FIRST SERIAL INPUT FROM CRU IA ONE IN BIT 15 OF Rll SETS CLOCK MODE.
LAST INPUT TO CLOCK REGISTER ICLK1 TO CLK141 STARTS THE CLOCK .
0

A0001436

Figure 5-14.

Enabling and Triggering TMS 9901 Interval Timer

5-31

CLK14

at

The clock decrements the value set in step 5 at the rate of o/64 (approximately 46,875
Hz with a 3 MHz clock) . The maximum interval reg ister value of all ones in 14 bits
(16,383) takes approximately 349 milliseconds to decrement to zero.
The code in Figure 5-15 is an example of a code to set up and call the TMS 9901
interval timer and also the code of the interrupt handling subroutine . Note that the
calling program first clears the counting register (RO) of the interrupt workspace.
Then it sets up the interrupt masks at the TMS 9901 and TMS 9900 after setting the TMS
9901 address i n R12. Then the calling program sets an initial value in the timer
register (CLK1 to CLK 14 as shown in the TMS 9901 data manual) . Because the desired
output on the terminal is a message every 15 seconds, a minimum interval is set in the
calling program while the interrupt handler is responsible for setting the time and
clearing the interrupt after it occurs . The handler keeps a count of the intervals to
determine the 15 seconds.
At the bottom of the figure is the interrupt linking area. Since all the code in this
figure is loaded as if at absolute memory address values (using the AORG assembler
directive) data statements are used here at the appropriate memory address. This
program can be loaded and executed by placing the machine-language assembler output
in the third column at the address shown in the second column. Then execute with the
program start a t M.A. FD0016·
The TMS 9901 can also be used as an event timer by starting the counter at the
beginning of an interval and reading the counter after the event has occurred. To read
the current value in the counter, the TMS 9901 must be taken out of the clock mode and
put into the interrupt mode for at least 21 .4 usec (1 TMS 9901 clock period). After
that, putting the 9901 back into clock mode and reading the clock/int mask bits gives
the current clock value (elapsed bit count divided by 46,875 equals elapsed time in
seconds).
5.9.3 EXAMPLE OF PROGRAMMING TIMER INTERRUPTS FOR TMS 9901 AND TMS 9902
This subsection explains how to use the interrupt vector scheme to program the TMS
9901 a nd TMS 9902 timers. These timers use , respectively, interrupts 3 and 4 to trap
to interrupt service routines following timer countdown.
The progr a m described in the following paragraphs is an example that does the
following:
•

Initializes the interrupt linking areas for the TMS 9901 and TMS 9902 timers
(interrupts 3 and 4 respectively).

•

Loads the timers with interval values.

•

Triggers the timers which cause interrupts when the countdown is complete .

•

Contains interrupt service routines (ISR's) which execute when interrupts 3
or 4 are executed.

•

Provides modules that perform hexadecimal-to-decimal conversions and
decimal-to-hexadecimal conversions.

The individual modules of this program are summarized in Table 5- 6. Please read these
descriptions before continuing . The listing of this example program is provided in
Figure 5-16, sheets 1 to 12.

5-32

TIMER

TXMIRA

0001
0002
0003
0004
0005
0006
0007
0008

I

~

000'?

,

•

e-

0010
0011
0012
0013
0014
0015
0016
0017
0000
001 s
0001
oooc
001'?
0020
0021
0022
0023 FDOO
0024 FDOO 02EO
FD02 FD20
0025 FD04 04EO
F006 FE60
0026 FD08 020(:
FDOA 0100
0027 FDOC 1EOO
0028 FDOE 1D03
0029 FD 10 0300
FD12 0003
0030 FD14 0201
FD16 (1003
0031 FD18 33Cl
0032 FDlA 10FF
0033
0034
00:35
0036 FEOO
0037 FEOO FE60
0038 FE02 FE04
003'? FE04 0 :300
FE06 00(1(1
0040 FEOB 0280
FEOA 00:3C
0041 FEOC 130B
0042 FEOE 0580
0043 FE10 020C
FE12 0 100
004'1 FE14 0201
FE16 5B9F
0045 FE18 33C1

Figure 5-15.

**

936227

09:08:10

122178

PAGE 0001

* * PROGRAM
* * *CAUSES
* * AN* INTERRUPT
* * * THROUGH
* * * INT3
* * *
** THIS

*
*
*

*

EVERY 15 SECONDS USING THE INTERVAL TIMER IN THE
TMS 9901. THE AORG DIRECTIVE CAUSES THE CODE TO BE
ASSEMBLED BY THE TXMIRA ASSEMBLER BEGINNING AT THE
ADDRESS SPECIFIED (SAME ns SLASH COMMAND ON THE
LINE-BY-LINE ASSEMBLER>. THIS PROGRAM CAN BE EXECUTED BY LOADING THE PROGRAM WITH THE TIBUG "M"
COMMAND AND EXECUTING WITH THE "E" COMMAND AT PC
ADDRESS >FDOO. LOAD OBJECT IN THIRD COLUMN OF
THIS LISTING AT nDDRESS IN 2D COLUMN. J.WALSH

*

* * IDT* *" TIMER
* *'. * * * * * * * * * * *

*
*
*
*
*

* REGI STER
*
*RO
EC!U
Rl
R12

**
*

*
~

EOUATE:=;
(I

EOU
EOU

1
12

PROGRAM CALLING THE INTERRUPT
AORG :>FDOO
LWPI >FD20

BEGIN ASSEMBLY AT M.A. >FDOO
DEFINE WORKSPACE ADDRESS

CLR

@>FEC.0

CLEAR INTERRUPT REG 0

LI

R12, >0100

9901 CRU ADDRESS IN R12

SBZ 0
:3BO 3
LIMI 3
Rl, 3

LI

LDCR Rl, 15
._IMP $

*
*
*

** *
*
*
*
*
*
*
*
*

9 901 TO INTERRUPT MODE
ENABLE INTERRUPT 3
ENABLE INT3 AT TMS 9900
2 ONES TO TMS 9901

ENABLE CLOCK AT 9901
LOOP HERE, WAIT FOR INTERRUPT

INTERRUPT SUBROUTINE
AORG
DATA
DATA
LIMI

>FEOO
>FE60
>FE04
0

BEGIN ASSEMBLY AT M.A. >FEOO
BLWP WP VECTOR FOR INT
BLWP PC VECTOR FOR INT
DISABLE INTERRUPTS

CI

R0,60

COUNT

,JH~

LI

>FE24
RO
R12, } 100

YES, PRINT MESSAGF
NO, INCREMENT COUNTER
9901 CRU ADDRESS

LI

Rl, >5B9F

C LOC~

INC

LDCR R1, 15

=

60 =

1~

SECONDS?

COUNT OF 11, 719

APPLY COUNT, START COUNTER

Example of Code to Run TMS 9901 Interval Timer (Sheet 1 of 2)

5- 33

TXMIRA

TIMER

FE1A 1EOO
0047 FElC 1[103
0048 FE1E 0300
FE20 000:3
0049 FE22 0380
0050 FE24 2FAO
FE26 FE2E
0051 FE28 04CO
0052 FE2A 0460
FE2C FE04
0053 FE2E
31
FE2F
35
FE30
20
FE31
53
FE32
45
4:3
FE33
FE34
4F
4E
FE35
FE36
44
FE37
53
FE38
20
FE39
48
FE3A
41
56
FE38
FE3C
45
FE3 D
20
FE3E
45
4C
FE3F
41
FE40
FE41
50
FE42
53
FE4:3
45
FE44
44
2E
FE45
0054 FE46 0707
FE48 0707
0055 FE4A
00
0056
0057
0058
0059 FFAA
0060 FFAA 0420
0061 FFAC FEOO
0062 FFAE 0380
0063
004~.

9 :36227

**

09: 08: 1(I

122178

PAGE 0002

SBZ 0
SBO :3
LIMI 'J
~·

':>'901 TO INTERRUPT MODE
CLEAR INTERRUPT AFTER EXECUTE[1
RESET INT MAS~< (H TM ~; 9900

RTWF'
XOP @:>FE2E,14

RETURN TO CALL ING PROGRAM
WRITE ME:::::3AGE

CLR

RESET TIMER COUNT
BEGIN AT INTERRUPT START

B

RO
@>FE04

TEXT / 15 SECOND:3 HAVE Elf\F'SED. ···

*

*
*

DATA :>0707,}0707

BELLS

BYTE 0

END OF MESSAGE DELIMITER

INTERRUPT LI NK AREA PROGRAMMING
AORG
DATA
DATA
DATA
END

)·FFAA
)0420
>FEOO
::>0380

BEGIN ASSEMBLY AT M.A. >FFAA
BLWP INSTRUCTION CODE
BLWP VECTORS LOCATION
RTWP I NSTRlJCT I ON CODE

0000 ERRORS

NOTE:

As an ex ercise, the user can load and execute this code : (1) load t he machine code values shown
in column 3 into the memory locat ion s shown in column 2, or (2) reassemble : if the L i ne-Byline Assembler (LBLA) is used, substitute the slash command for th e AORG directive and follow
the DATA and TEXT statement conventions for the LBLA. Execute using the E TIBUG command.

Figure 5-15.

Example of Code to Run TMS 9901 Interval Timer (Sheet 2 of 2)

5-34

Table 5-6. Interrupt Example Program Description

I

Module

Sheet Number
of Figure 5-16

Program Description
This module sets up the interrupt linkage
areas for interrupts 3 and 4, loads vectors
pointing to Module REALCK for interrupt 3
and to Module KYBDSC for interrupt 4. This
is the first program called, and it calls
Module User Start.

Interrupt Link

User Start

2 to 4

"User Start" routine; th is
the general user control
contains mainline code to
calls KYINIT before starting

Timer, TMS 9901

5

This module sets TMS 9901 timer to specified
value, starts countdown (countdown
completion causes interrupt through
interrupt level 3) .

Timer, TMS 9902

6

This module sets TMS 9902 timer of local I/O
port to specified value, starts countdown
(countdown completion causes inter rupt
through interrupt 4).

Real Time Clock ISR

7 and 8

This Real-Time Clock routine is the
Interrupt Service Routine (ISR) for
interrupt 3. It accumulates counts at
one- fifth second intervals to keep a real
time clock count; time values are
initialized by User Start.

Keyboard Initialization

8

This module initializes I/O buffer for
keyboard input .

Keyboard Scan ISR

9 and 10

This is the Keyboard Scan Routine ISR for
interrupt 4. It polls the keyboard unit for
a new character, and then puts the character
in buffer. Backspace and delete monitoring
is provided.

Hex/Decimal Conversions

11 and 12

These modules convert decimal numbers to
hexadecimal equivalents (sheet 11) and
hexadecimal numbers to decimal equivalents
(sheet 12) .

5-35

is the start of
progr am . This
the timers, and
the time rs.

5.9 . 3.1 Interrupt Linking Area Set-Up (Figure 5-16, Sheet 1)
This module sets up the interrupt linking areas that point to the two interrupt
service routines for the timers in the TMS 9901 and TMS 9902. The workspace for this
module is the space just below the INT3 and INT4 linking areas. Since this example
uses only interrupts 3 and 4, the linking areas for interrupts 1, 2, and 5 through 15
are free space .
5.9.3.2 User Start Program (Figure 5-16, Sheets 2 , 3 , 4)
This module organizes the other modules into a user program. It sets up control
functions and calls other modules in a prescribed sequence. This program receives
control after the interrupt linking areas are initialized as described in paragra ph
5.9.2.1. It then sets the timing values for the TMS 9901 timer and begins the
countdown by a BLWP @TIME01. It also calls the keyboard initialization module (BLWP
@KYINIT) which calls the TMS 9902 set and execute module (BLWP @TIME02).
NOTE
This User Start Program is for example purposes, and is
intended only as a vehicle to demonstrate usage of the
following subroutine modules.
5.9.3 . 3 TMS 9901 Timer Set Routine (Figure 5-16, Sheet 5)
This module sets and executes the interval timer of the TMS 9901. The calling routine
specifies the number of 21.333-microsecond periods (at 3 MHz) to be counted by loading
its own register 0. The TIME01 routine then picks this number (limited to 14 bits) by
indirect addressing through R13 ( return WP value =RO). It shifts it while in R9,
supplies the correct control bit (bit 0 = 1 by ORing), starts the timer (LDCR
instruction) and enables the interrupt. Control returns to the calling program, which
will be interrupted by the timer interrupt when the count reaches zero. The calling
sequence to the timer set routine is:
LI
BLWP

R0,9375
@TIME01

1/5TH SECOND INTERVALS
SET TIMER

The interrupt service routine for interrupt 3 is in paragraph 5 .9.3. 5 .
5.9.3 .4 TMS 9902 Timer Set Routine (Figure 5-16, Sheet 6)
This module sets and executes interval timer of the TMS 9902. The calling routine
specifies (in its own register 0) the number of 64 microsecond periods (at 3 MHz, with
the TMS 9902's CLK4M control bit zeroed) to be counted before generating the
interrupt. This routine then picks this number up (through WP return value in R13, old
RO), puts it in the left byte of R9, sets the LDIR (Load Interval Register) flag to
enable loading of the timer value, resets LDCTRL (Load Control Register) to bypass
loading the control register, loads the timer which begins the count, and then enables
interrupt 4 on the TMS 9901. Notice that the user must have a jumper plug between pins
E2 and E3 for an interrupt to occur. Control returns to the calling program which will
be interrupted by the timer some tim e later (called I SR described in paragraph
5.9 .3.6).

5-36

,

5.9.3 . 5 TMS 9901 24 - Hour Real-Time Clock Service Routine (Figure 5- 16, Sheet 7)
In this module, the TMS 9901 timer is used as a real time clock; an interrupt occurs
every fifth of a second and a fractions counter is updated. The calling program
initially sets the second- interval counter (R1) to 5. Every five counts, the seconds
counter is updated; every sixty seconds the minutes counter is updated, etc. Note that
since the initial period (one-fifth second) is long, the execution time of this
service routine is trivial from a system throughput standpoint. Note also that because
this timer is associated with interrupt 3, it has higher priority than the TMS 9902
timer, which will be used for miscellaneous timing purposes in this example. This
ensures the integrity of the real time clock recording the elapsed time from system
initialization.
5 . 9 . 3.6 TMS 9902 Used To Poll Keyboard Service Routine (Figure 5-16, Sheets 9 and 10)
In this module, the TMS 9902 timer is being used as a general purpose delay timer. The
service routine samples an ASCII encoded keyboard's output , and if a set time has
elapsed and a strobe change occurred, it reads the character. The time delay and
strobe change ensure a new character has been sent from the keyboard . The strobe for
any one character is assumed to last longer than the interval set in the timer for
scanning, and a flag is used in the software to simulate an edge - triggered data
capture condition. The ASCII encoded keyboard is assumed to be connected to the TMS
9901 through connector P4.
When the strobe goes from high to low, data is read, and the flag turned on. Only when
the strobe goes high again is the flag reset and a new character can be received.
5.9 . 3.7 Decimal To Hexadecimal Conversion (Figure 5-16, Sheet 11)
This module is a sample decimal-to hexadecimal-conversion routine. The calling program
places the least significant four digits in its register O, and the most significant
(fifth) digit is right-justified in its register 1. A BLWP @DECHEX instruction gives
control to the conversion routine.
The called routine isolates each decimal digit and uses it to index a loop which adds
the proper place value ( 10,100,1000, etc.) to the result register . As each digit is
isolated, a table pointer is bumped through the decimal powers. The resultant
hexadecimal number is returned to the caller routine's register 0. The caller's
register 1 is not disturbed.
5 . 9.3 . 8 Hexadecimal To Decimal Conversion (Fi gure 5- 16 , Sheet 12)
This module is a sample hexadecimal to decimal conversion routine . The calling routine
places the hexadecimal number in its own register O, then performs a BLWP @HEXDEC. The
converted result is placed back in the caller's register 0 (through address in R13),
with a fifth digit (most significant) in register 1 of the calling program. Both
registers in the calling program are always altered.
The routine repeatedly divides the number by 10, and collects the remainders. These
remainders, properly collected by the shift and SOC instructions, form the decimal
number.

5-37

TX MIRA
t)(H)

?36227

IDT

t

(11) (>:2

**
· TE'3T ·

~----- ------ --- -- ----------------- - ------------ ----------

0003
0004
0005

*
*
*

(J r)O(:.

0( 07
1

<)(H):;::
OOr)•;:-1

001 (I
0011

0012
001 3 0 1)00

02EO

-·--

I NTERR UPT LINKING nREA INIT i nL IZ ATION ROUTINE.
THI':: F:OUTJNE INITIAL.I ZE·:. THE INTERRUPT LIN•'. INC,
nREA IN HIGH RAM FOR INTERRUPTS 3 nND 4 .
A "BLWP" IN'.::TRUC:TION I'.::: BUIL.L ~JITH THE
ADDRESS OF THE PARTICU~ AR INTERRUPT SERVICE
ROUTINE WHICH WILL THEN RECEIVE CONTROL
WHEN THE INTERRUPT IS ACTIVnTED. TO COMPLETE
THE RETURN PATH, A "RTWP" IN:=:TRUCTION I :=:
BUILT IN RAM ALSO.

*
*
*
*
*----------------------------------------------------------ENTRY

LWPI >FF78

GET WORKSPACE

LIM!

CUT OFF INTERR UPTS

0002 FF?:=:
(>(l

14

(>(H)/j
<)(H)(:,

0300

00 15

*

(H) 1 (:,

4j.

0017

(H)r">:;:: C060

qo 1 :=:

(J(l(l(

(H)t)A

00 1 ·;1 0010 020::::

LI

3, > 04-20

1. orrn

4

PC F'TF:

B L~JP

OPCODE

LI

5, INT 3VC

ADDR OF 9·:101 TIMER F:OUT INE

LI

l·., J NT 4VC

r1DDR OF

0 14::: ..

OlA::::···
~

1)02/=,
0027

(>02S
00 2·;1 0020 cc4·3
oo::::o 002:2 CC45
003 1 002'1 CC44

00:::::::::
00:::::::: 0026 c:c:?.:3
00:::: 4 002::: cc::::6

00::::7

CiET INT

LOA[t RTVJP OPCODE

0205

0025

0 036

@:··0 1:> 1 2, 2

o ::::=:o

002::::
002'1

00::::5 002A

MOV

0 4 2 1)
0'.:'!0 4

(>01 c (1.2(>(:.
001E

THE FOLLOWING CODE LOAD:=: THE RECiU:.TERt· WITH THE
PROPER VALUES FOR INITIALIZING THE RAM AREA .
MOV @>OOOE,1
GET INT 3 PC PTR

OOOE

COfl(>
OOOE (H) 12

001 ·2
0020 0014
001 6
0021 001:::
001()

0

0(1(>(!

*
*
*
*
*

cc~::: '!·

002C (l :::oo
002E 0004

*

TIMER F·n1.1T I l'JE

THE FOL. LO~JIN O CODE TAf.

006(>

**

(H) 'l '3

••

936227

004'l
0045
0046
0047
004:::
004 '?
0050
0051
0052
0053
0054

~

·----------------------------------------------------------*
THIS MAIN ROUTINE RECEIVES CONTROL AFTER
*
THE INTERRUPT LINKING AREA IS INITIALIZED.
*
IT CALLS THE KEYBOARD INITIALIZATION
*
ROUTJNE. AND STARTS BOTH TIMERS GOING.
•
IT THEN INTERROGATES THE NEW-LINE FLAG
*
AND "[II::wo:3E:::;" OF THE u::::ER DATA BY

(H)55

005,:.

~------- -------- -------------------------------- - -- ---------

0061
0062
006::::
(>064
0065
0066

0067
006:3
0069
0070
0071
0072
0073
0074
0075
0076
0077
0078 0030
00:32
0079 0034
oo:::o 00:36
0081
0082
0083
0084
0085
0086

FF 1 :::
FEF'3
FF:::::::
FF7:3
FF58

*KYBDWP

Ef.!U
fFF1 -:::
>FEF3

KEYBOARD ROUTINE WOR~ S PACE
l FF :~:8

>FF78
>FF58

XOP DEFINITIONS
DXOF'
DXOP
DXOP
DXOP

READ. 11
WRIT, 14
HEXI ,9
HEXO. 10

READ ONE CHARACTER
WRITE A :3TRING
HEX # INPUT
HEX tt OUTPUT

ENTRY POINT
LWPI CU::WP

CLOCK REGS FOR INITIALIZATION

CLR
LI

1
7,Cl1)9·3 005E
0094 0060
0062

0095 0064
0066
0096 (>(>(:.::::
006A
0097 006C
006E
009:::: 0070
0072
009';-J 0074
007 6
0100 0078
007A
007C
0101 007E
0 1 02 00:30
0082

0100-·
0227
1(:.F:3
2F97
2EC9
2FAO
0100 ·'
0200
249F
04 20
0104 ...
0201

0005
02EO
FF58
042 0

PAGE OOO::::

MOV O, •·::1+
\.JRIT @CRLF

PUT VllLUE IN CLOCt< REG I STER·:;
DO CARRIAGE RETURN I LINE FEED

AI

7 , 12

NEXT PROMPT IN TABLE

DEC
,.JNE
WRIT
READ
WRIT

·=-

*7

9
@CRLF

ONE LE::;::; TO 00
GO Bn c~ IF NOT DONE
READY, GET SET. GO !
USER RESPONSE ST11RT3 CLOCI<
NEW LINE

LI

0 ,9375

ONE-FIFTH ::=:ECOND I NTERVAL:3

oooc
0608

**

.-.
LOOF' 1

BLWP @Tl MEO 1

::;;ET TIMER

LI

INTERRUPTS I SECOND

1, 5

LWP I MA I NR1J

NOW USE THIS ROUTINE ' S REGS

BLWP @t:'. YINIT

STnRT SCANNING KEYBOnRD

MOV

@KYBDWP,@KYBDWP

LOO~

.JEQ
C

~JAI

NOT COMPLETE LINE YET
TI ME REC!UE::::T?

01 ::H ·"

C820

WAIT

FFt::::
FF18
1 ::::FC
:3:320

T

@l TR I NG·::: r-!Clt·J HEAD I Ni:;:;::

oo::::A o 1oo ·"
0105 oo:=:c
008E
01 06 0090
0107 0092
0094
01 o:::: 0091.:.
0098
0109 009A
OO'?C
0110 009E
0 11 1 OOAO
0112 OOA2
OOA4
011 :::: OOA6
0114 OOA:::
OOAA
0115 OOAC
OOAE
011 (:. OOBO
0117 0082
0118 0084
0119 OOB6
OOBS

2F AO
FEF3
1 OF::::
0207 TIME
OOBC ".
020:3
0005
0209

\.JA IT
7, Cl<:F'ARM

LI
LI

-ti OF ITEM::;
?, cu:::wP+4

CLOCK REGISTERS 2,3,4,5,(:.

FF3C

WRIT *7
MOV •9+ ,0
BLWP @HEXDEr

PRINT HEADINC;
GET TIME PARM FRnM CLOCK
CONVERT BINARY TO DECIMAL

HEXO 0
WRIT @CRLF

PRINT TIME
FINJ·::H LINE

0227
OOOC

AI

NE XT HE?lDING

0608

DEC ::;:
.JNE LOOP 2
.JMP l-Jr\ IT
WRIT @CRLF

2F97

LOOP2

C039

0420
0252 ·'
2E80
2F~O

0100 "

16F5
10El

2FAO ERROR
0100 ·'

Figure 5-16.

7,12

ONE LE·:;~; TO GO
GO BACK IF NOT DOt·IE
DONE, GO \.Jr\ IT
DO CR I LF

Example Program Using Timer Interrupts 3 and 4 (Sheet 3 of 12)

5-40

TX MIRA

TE:::n

"

01 20
0121
0122
012:3
0124
0125
0126
0127
0128
0129
0130
0131
01 ::::2
013:;:
0134
0135
0136
01:37

936227
._IMF'

OOBA 1oc-;:

OOBC
OOC7
OOC8
0003
(10[14
OODF
OOEO
OOEB
OOEC
OOF7
OOFE:
OOFD
OOFE
0100
0101
0102

5 :3

*
*
*
CKF'ARM

00
4[1
(le)

4c·
·-·
00
44
00
~9

00

47
00
54

TI

OD

CRLF

():=!:

**

05: :22

122 17:=:

F'()GE 000'1

LOCtF't

[IATA CON:=:TANT'::
TEXT
BYTE
TEXT
BYTE
TEXT
BYTE
TEXT
BYTE
TEXT
BYTE
TEXT
BYTE
TEXT
BYTE

~

' ·::ECOND3
(I

...

"' MINUTE
0

·' HOUR
0
.·· D()Y NUMBER
0

··' YEAR
0
·' (;(I

°7'

·'

,,

0
' Tl ,.
>O, ) A, O

OA
00

Figure 5-16.

Example Program Using Timer Interrupts 3 and 4 (Sheet 4 of 12)

5-41

TXMIRA
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148 0104
0106
0149 o1 or:::
010A
0150 010C
0151 OtOE
0110
0152 0112
0153 0114
01 l.6
0154 0118
0155 01 lA
015{:. 011C
0157 011E
0120
015:::: 0122

936227

**

o::::: 05: 22

122/78

PAGE 0005

·----------------------------------------------------------*
*
*
*
*
*
*

TMS 9901 TIMER SET ROUTINE
THI S ROUTINE SETS THE INTERVAL TIMER ON THE TMSQ901
WITH A VALUE PASSED BY THE CALLING PROGRAM. THE
VALUE PASSED IS SIMPLY AN INTEGER COUNT OF THE
NUMBER OF 21.333 MICROSECOND PERIODS DESIRED. THI S
ROUTINE TAKES CARE OF LOADING THE TIMER REGI STER
PROPERLY, AND ENABLING THE TIMER INTERRUPT.

·----------------------------------------------------------DATA >FF78.ENT01

FF7:=: TI ME01
o 1oa ···
o::::oo ENTOl
0000
C25D
020C
0100
OA19
0269
0001

LIM!

0

TUR~

MOV
LI

•1::::, 9

GET TIMER VALUE
ADDRE:3S 9901

SLA
ORI

12, :>0100

OFF INTERRUPTS

SHIFT CLOCK COUNT
:3ET CLOCK MODE

9, 1
9, 1

lEOO
l DO :~:

LDCR 9 , 15
:=:BZ 0
:=:Bo ::

o::::oo

LIM! 4

:=:TART CLOCI<
INTERRUPT MODE
ENABLE I NT 3 REG! MA:=.f :
TURN INTERRUPTS BACK ON

RTWP

RETURN TO CALLER

3 ::::c:·?

0004

o::::::::o

Figure 5-16.

Example Program Using Timer Interrupts 3 and 4 (Sheet 5 of 12 )

5-42

TEST
0160
016 1
0162
0163
0164
0165
0166
0167

TXMIRA

936227

**

122/ 78

PAGE 0006

*-----------------·------------------------------------------

*
*
*
*
*

012~

FF78

0126
0168 0128
012A
0169 012C
0170 0 12E
0171 0130
0132
0172 0134
0173 0136
0174 0138
0175 013A
0176 013C
0177 013E
0178 0140
0179 0142
0144
0180 0146

0300
0000
C25D
ObC9
020C
0080
!DOD
lEOE
3209
1Dl4
OAlC
1EOO
1D04
0300
0004
0380

TMS 9902 INTERVAL TIMER SET ROUTINE
THIS PROGRnM SETS THE INTERVAL TINER OF THE TMS 990~
USING THE VALUE PASSED BY THE CALLING PROGRnM.
THE PROGRAM LOADS THE VALUE PROPERLY nND ENnBLES
THE APPROPRIATE INTERRUPT .

*-----------------------------------------------------------

TIME02 DATA >FF78.ENT02

0128 ~

Figure 5-16 .

ENT02

LIMI 0

CUT OFF INTERRUPTS

MOV *1 3.9
SWPB Q
LI
12, ) 0080

GET TIMER VnLUE
PUT IN LEFT BYTE FOR LDCR
POINT TO 9902

SBO
SBZ
LDCR
SBO
SLA
SBZ

20
12 . 1
0
SW 4
LIMI 4

SE T LD IR TO LOAD VALUE
RESET LDCTRL, BYPASS C0NTROL R
LOAD TIMER, BEGIN COUNT
SET TIMENB FOR INTERRUPT
POINT TO 9901
SET INTERRUPT MODE
ENABLE INT 4 MASK
GIVE BACK INTERRUPTS

RTWP

RETURN

13
14
9,8

Example Program Using Timer Interrupts 3 and 4 (Sheet 6 of 12)

5- 43

TEST

TX MI RA

0182
0183
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194 0148
014A
0195 014C
014E
0196 0150
0197 0152
0198 0154
0199 0 156
0200
0201 0158
015A
0202 015C
0203 015E
0 160
0204 0162
0205
0206 0 164
0207 0166
0208 0 168
0 16A
0209 0 16C
02 10
02 11 0 16E
02 12 0 170
02 13 0172
0 17 4
02 14 0 176
02 15
02 16 0 178
02 17 0 17A
0 17C
02 18 0 17E
02 19
0 180
0 182

936227

**

08 : 05 : 22

122/78

PAGE 0007

*-----------------------------------------------------------*
TMS 9901 REAL TIME CLOCK ROUTINE
*
THIS ROUTINE I S ACTIVATED WHEN THE TMS 9901
*
*
*
**
*
*
*

FF38

INTERV~L TIMER COUNTS DOWN TO ZERO, cnusING
INTERRUPT 3 . THI S ROUTINE COUNTS THE NUMBER
OF ONE-FIFTH SECOND INTERVALS OCCURRING AND
UPDnTES THE nPPROPRIATE COUNTER. AT THE END
OF A SECOND, THE MINUTE COUNTER IS CHECVED,
AND UPDATED IF NECESSARY . THI S PROCEDURE IS
REPEATED FOR EnCH SUCCESSIVELY LARGER TIME
UNIT, UP TO A YEAR. LEAP YEARS DON ' T COUNT.

·----------------------------------------------------------INT3VC DATA CLKWP,IN3PC

014C~

020C
0 100
lEOO
1D03
0601
1615
020 1
0005
0582
0282
003C
160F
04C2
0583
0283
003C
160A
04C3
0584
0284
00 18
1605
0585
0285
0 16E
160 1
0586
0380

Figure 5-16.

12, >0 100

POINT TO 9901

IN3PC

LI

INTERRUPT MODE
ACKNOWLEDGE INTERRUPT
DOCK FRACTION COUNTER
NOT DONE WITH A SECOND YET

*

SBZ 0
SBO
DEC 1
JNE RETURN
NEW SECOND
1.5
LI
I NC
CI

AD D ONE SECOND TO CLOCK
60 SECONDS YET?

~
~

NEW SECOND COUNTDOWN

~

k

2.60

RETURN
NEW MI NUTE
CLR L
INC 3
3.60
CI

NO, GO RETURN

J~

*

*

*

NEW MINUTE: CLEAR SECONDS
ADD ONE MINUTE
60 MINUTES YET?

~

JNE
NEW
CLR
INC
CI

RE TUR N
HOUR

JNE

RETURN
DAY

~w

INC
CI

NO, RETURN
NEW HOUR : CLEAR MINUTES
ADD ONE HOUR
MIDN IGHT YET?

~

~

4
4 ,24

NO

c

ADD ONE DAY
END OF YEAR?

~

5.366

JNE RETURN
NEW YEAR
*
INC 6
RETURN RT WP

NO , RETURN

Example Program Using Timer Interrupts 3 and 4 (Sheet 7 of 12)

5-44

TEST

TXMIRA

**

08:05:22

122 / 78

PAGE 0008

*------------------------------------------------------------

0223
0224

*
*
*
*
*
*

o~~e

~'~

0226
0227
0228
0229
0230
0231
0232 0184
0186
0233 0188
018A
0234 OlSC
018E
0235 0190
0236 0192
0237 0194
0238 0196
0239 0198
0240 019A
0241 019C
0242 01 9 E
OlAO
0243 01A2
01A4
0244 01A6

936227

*
*-----------------------------------------------------------

FF18 KYI NIT
0138 '
0209 KYE NT
0025
0208
FEF3
04F8 LOOP
0609
16 FD
04C2
04C3
04CO
04Cl
0200
OODO
0420
0124 '
0380

Figure 5-16.

KEYBOARD INITIALIZATION ROUTINE
THIS ROUTINE INITIALIZES THE WORK AREA IJSED BY THE
KEYBOARD SCANNING ROUTINE WHEN THE TMS 9902 TIMER
TIMES OUT. THE TMS 9902 TIMER IS DEDICATED TO TIMING
THE INTERVAL BETWEEN KEYBOARD SCANS. IT IS SET
IN THIS ROUTINE, AND THE KEYBOARD CHARACTER BUFFER
. IS CLEARED OUT, AS WELL AS THE APPROPRIATE FLAGS RESE
DATA KYBDWP,KYENT

LI

9,37

# WORDS IN BUFFER

LI

8.KYBUF

KEYBOARD INPUT BUFFER

CLR
DEC
JNE
CLR
CLR

•8+
9
LOOP

WIPE TWO BYTES OUT
# OF WORDS LEFT
GO BACK
CLEAR INDEX PTR: NEW LINE
CLEAR ST ROBE FLAG
CL EAR NEW-LINE FL AG
CLEAR DATA AREA
75 SCANS I SECOND

2
~

~

c~

0

CLR
LI

0.208

1

BLWP @TIME02

GO START TIMER

RTWP

DONE

Example Program Using Timer Interrupts 3 and 4 (Sheet 8 of 12)

5-45

TE·:.T

TXMIRA

936227

*~

-«- ------ ---- -- -· --·----- ---···--- -------------------- --------- -----------*
~EYBOARD scnNNING ROUT IN E
*
TH I ·::: ROUT J NF. ·::.cr,w:: {\N ~r::::c 1 I - FNC Ctf lf-TI f L YBOtiF'fl
'ICONNECTED ['lRECfLY T 1·1 THE F'r-'1Rr'tLLEI _ l / r) PnR T , F'·1.
•
1 / 0 [-11T':C: 0-7 r'1RE f\::::CII L1f\T{L /:11\ifl £<1T ::: 13 r:l'l

 STROBE .
TH I·.:; F:nUT l l\!E l ·:.: ENTEREfl ~JHFN -r HE I Nl EF:Vfll. TI nER
,~
HI THE TM ·~: ·;1·;11y;:: TI ME·.:: OUT. THE I N TE'1;·p1JF'T I ::
*
f\Oo'NCtl JLEDC£[1 , MW THE ':::Tr'tTE. (1F THE ·.:.TROBE rL {';1:,
1·::: ::::EN·:;E [I. 1F F·F:EVIOU:.::LY Il'H-l CTIVE r,r-,m f\J(il.J :'1CTI\IE
f\ NEl-J CH(IR()CTE R f-1()•;:: {\F'F'Er'tRED ON THE I / 0 F'CIF'T,
*
l.JHlCH 1:::. F:E AD IMMEDI ATELY. IF THE ·:nw1BE 1·:::.
*
INf\CTIVF, OR I F PREVIOUSLY ACTIVE nND STIL L nCTIVE,
*
THEN rHE I / 0 p1)RT r ::. IC·NORED . WHEN A NEl..-1 CHr1R(1CTER
*
I ::: F:EA[I, THE ';::TROBE FL J.\C, I·;:: ·:.ET, {)Nlt I·~: RE·.:.!:· T
*
ONLY AFTER THE STROBE G O~S INACT I VE .
r H{)RArTERS ARF COLLECTED IN THE VFYBOnRfl BUFFER
AND l·JHEN A C('IF:R I Af'1E RETURN I ·;:. I NF'IJ r , (1R l·IHEN
THF BUFF~R JS F ULL , THE NEW- LINE F l nG IS SET.
3
I f 1S ASSUMED THERE IS~ ROUTINE SOMEWHFRE
~
l>JH J CH I ~-l=· r'EC T':. THE Nr::W--l I NE FL()C;' (\N[I u·::E::::
4
THE COLLEC TE D DATA FOR SOME PURPOSE .
INT4VC [!{)TA t YB DWP ,IN~F'C
•

.0.

() ·~··5 ·~:

0254

0

o.-~55

*

')2r_:i(:,

*

n2s:=:
I) ::::5·::-1

o:.::·t'.:.o
026 1
0262
n.:-:63
O.::"t'.:Jl

*
*
*

021~.5

(1.?6(:.
0267
0.26:.:: OlN:: FFl:.::
01.AA ntAC
() ;2(:::1

r)270 0 1AC
•) lAE
t) ',27 1 0180
o.-:7::::
i)27:~: 0 1 B:.::·
01B4
018(:.
( 1 27 4
0275 01 B:.::
027(:. OlBA
0277 01 BC
027:.:: 01BE
0:::79 O lCO

o·:::oc
oo:::::ci
1[114

02:.::6
02:::7
02:: ::;::
')2::::9

i:r2·:11)
(1 :~ ·:11

0292

SBO
2n
ADDF:E·.:::;. T HE TM:.:. ·-;·:10 1,
LI
1:::: } (l 1 :20
MDV
JEQ
TB
.JNE
CLR

l ·:::011l FO:.::
16 17

04C:;:
1(> 1 5

1 FOE:
1:::: 1 ::::
070::::
::::t.01
024 1
7FOO
02::: 1

THE TM·.::
12, :. •)1):::0

f'.)DD F:E·:.·~:

I_ I

I

coc::::

1

o 1 c~::
01C4
0 1C6
0 1 c::::
OlCA
01CC
01CE
01 DO
01[12
01[14
0 1 [I(:.
0 1 [I:.::
r) 1 DA
0 1 DC
0 1 DE
01EO

..,.

020C
0 120

c2:.::o

02:::::i
(>2::::2
0 2:.::::::
02:.::4
<) 2:=:5

*I N41-'C

*·::CAl\l

3 13

SCAN
8
GU BAO
3
~ MP
GOBACK
STROBE F LAG WA S RE SET,
TB
8
JEQ
GOBnCK
SETO 3
STCR 1. 8
ANDI 1 ,)7FOO

TUF\r·I OFF I f\HERF\l IF'T
PO I NT TO ·;:-r;:-10::;·
RESET INTERRUPT
AND POLL THE t EYBOrcF'D ·::T1',Tll·:.
F'{IFi(\LLEL I I (I ·:1 -=-•o 1
CHECK STROBE FLA~
RESET : SCAN ~EYBOr't R D
LOQ~ {)T STROBE
·:.TI LL LOW FROM LA:.:.T ( H()R
HIGH: flONE WITH OLD CHnR
SINCE NO CHAR , RETURN
SO SCAN KEYBOARD
LOOK AT STROBE
HIGH: NO CHAR YET
SET STROBE FLnG, NEW CHAR
GRAB BYTE FROM KEYBOARD
STR 1P PARIT Y BIT
BA C ~.:: ·:::PACE ?

o:=:oo
1 :::OD
02::: 1
7 FOO
1::.:: oc
[!:::::::: 1
FEF :::
0~~::::2

0 2:.::2

Figure 5-16.

.JEQ
CI

B·::
1. > 7 FO O

C;O [10 BAC:t::S PACE
DELETE LI NE?

.JEQ
[1EL
MOVB 1, @VYBIJF(2)

i30 [1ELETE LI NE
PUT CHAR IN BUFFER

INC
CI

CHnR PTR TO NXT LOC
END OF BUFFER?

·-:·
2.72

Example Program Using Timer Interrupts 3 and 4 (Sheet 9 of 12)

5-46

TXMIRA
0 1E2
01E4
02'?4 01E6
01 Ef::
0295 OlEA
02'?6 OlEC
0297
02·;13 OlEE
029':1 OlFO
0300 01F2
0301 01F4
0302
0303 01F&.
01F:3
OlFA
0304 OlFC
(1:305 OlFE
029~:

0200

0202
0306 0204
o:~:07 020(:.
03(Jf:: 020:::

Figure 5-16.

936227

**

o:=:: C>5: 22

122/78

F'AOE 00 10

004:=:
.JEO
CI

1 ~:0:::

0281
0000
1 :~:0:3

0:380
0602
1OFD
04C2
10C6
D8AO
0208 '"
FEF:3
(>582

LINE
1 >ODOO
I

YES, FORGE LINE DONE
Cr'.'.\RRIAGE RETURN -;.

,.JEC! LINEX
YE'.=:, SET END-OF-LINE
GO BACK RHJF'
DONE
:::F'ECI AL CHARACTER HllN[tL I NC. ROUTINE'.3
*B·~
DEC 2
MOVE INDEX BACf<
·=._IMF' GOBACV
DEL
CLR .-,....
CLEAR INDEX
.._IMF' RETURN
BUFFER OVERFLOW HANDLING ROUTINE
*
LINE
MOVB @CRX,@KYBUFC2>
FCtRCE 
LINEX

INC 2
MOVB @CRX+1,@KYBUF(2)

BUMP POINTER FOR NULL BYTE
NULL OIJT END OF LINE

CR

SETO 0
._IMF' F:ETURN
DATA >ODOO

TURN LINE FLA[; (tN

[l:=:AO
020~1 -'

FEF3
0700
108[1
ODOO

CRX

Example Program Using Timer Interrupts 3 and 4 (Sheet 10 of 12)

5-47

TEST

TXMIRA

0310
0311
0312
0313 020A
020C
0314 020E
0315 0210
0316 0212
0317 0214
0216
0318 0218
021A
0319 021C
0320 021E
0321 0220
0322 0222
0224
0323 0226
0324 0228
0325 022A
0 :3 26 022C
0327 022E
0323 0230
0329 0232
0330 0234
0331 oz::6

936227

**

os:os:22

122/78

PAGE 0011

*----------------------------------------------------------*
DECIMAL TO HEXADECIMAL CONVERSION ROUTINE
*----------------------------------------------------------DECHEX DATA >FF78,DECH1

FF78
020E ·'
C03D DECH1
COSD
0640
0202
0004
0203
0243 "
04C4
C173 DECH2
C180
0246
OOOF
C186
1303
A105 DECH3
0606

16FD
0940
0602
16F4
0241
023:3 OOOF
0332 023A 1304
0333 023C C 15:3
0334 023E A105
0335 0240 0601
0336 0242 16FD
0337 0244 C744
0338 0246 0380
0339 0248 0001
024A OOOA
024C 0064

DECH4

MOV
MOV
DECT
LI

*13+,o
•13, 1
2.4

GET 4 LSD "S
GET l MSD
RESTORE OLD WP
SET UP COUNTER

LI

3,MULT

ADDRESS OF MULTIPLY TABLE

CLR
MOV

4

CLEAR SUM
GET MULTIPLIER
COPY OVER INPUT
STRIP WANTED DIGIT

MOV

6,6
DECH4

1 ':•
~·

•3+,5
MOV 0,6
ANDI 6,}F

.JEG!

A

5~4

DEC

6

...INE

DECH3
0.4

~3 RL

IS NEW DIGIT ZERO ?
YES, SKIP ADDITIONS
ADD INTO SUM
DECREMENT COUNTER
IF NOT DONE, JUMP BACK
MOVE NEXT DIGIT OVER
DECREMENT DIGIT COUNTER
IF NOT ALL DIGITS , JUMP
LOOK AT MSD ONLY

DEC
DECH2
ANDI 1 » F
.JNE

IF ZERO, EX IT
GET 10 K VALUE
ADD IT ON
A
DEC 1
DECREMENT THE COUNTER
,JNE
IF NOT ZERO, JUMP
DECH5
MOV 4.•13
PUT DATA IN OLD REGS.
RTWP
RETURN
DATA 1.10.100,1000. 10000
,.JEQ

MOV

DECH5

DECH6
MULT

DECH6
•3.5
5,4

024E 03E8

0250 2710

Figure 5-16 .

Example Program Using Timer Interrupts 3 and 4 (Sheet 11 of 12)

5-48

TEST

TXMIRA

0:341
0342
0:343
0344 0252
0254
0345 0256
0346 0258
0347 025A
025C
0348 025E
0260
0349 0262
0:350 0264

r

PAGE 001..2

122/78

*----------------------------------------------------------HEXADECIMAL TO DECIMAL CONVERSION ROUTINE
*-----------------------------------------------------------

FF78 HEXDEC DATA
0256 ·'
COBD HEXD1 MOV
04CO
CLR
0204
LI
0004
0205
LI
OOOA
OB40 HEXD2 SRC
C082
MOV
130C
,.JEQ
COC2
MOV
04C2
CLR
3C85
DIV

0266
0268
02t.A
026C

0355

026E E003
0270 0604
0272
0274
027f:..
0278

16F7
0840
(:042
C741
027A 064[1
027C C740

027E
0280
0282
0284

**

*

0351
0352
0353
0:354

0:356
0357
0358
0359
0360
0361
0362
0363
0364
0365
0366
0367
0 :3 68
0369
0370
0371

936227

0380
0840
0604

soc

HEXD4

HEXD3

16FD
02E:6 10F7

**
*

DEC
.JNE
SRC
MOV
MOV
DECT
MOV
RTWP
SRC
DEC
.JNE
'-IMP

>FF78.HEXD1

4,4

GET HEX VALUE
CLEAR RETURN VALUE
~;ET UP COUNTER

5, 1 (I

DIVISOR IS 10

0,4
2.2
HEXD3
2 .3
2
5.2
~:. 0

MAKE ROOM FOR NEW DATA
IS QUOTIENT > 0 ?
I F NO .JUMP
SET UP FOR NEXT DIVIDE
CLEAR UPPER HALF OF DOUBLEWORD
DIVIDE BY 10
PUT NEW DATA IN 0
DECREMENT COUNTER
IF NOT DONE, JUMP BACK
MOVE DATA OVER 1 NIBBLE
SET UP MSD
PUT DATA IN CALLER REG.1
OLD WP ADDRESS
PUT DATA IN CALLER REG.O
EXIT
MOVE DATA OVER
DECREMENT COUNTER
IF NOT DONE, CONTINUE SHIFTING
GO XFER DATA AND EXIT

*13+,2
0

I

4

HEXD2
0,4
2.1
1.*13
13
01*13

0,4
4
HEX D3
HEXD4

PROGRAM END
END

0000 ERRORS

•

Figure 5-16.

Example Program Using Timer Interrupts 3 and 4 (Sheet 12 of 12)

5-49

5-10 MOVE BLOCK FOLLOWING PASSING OF PARAMETERS
The coding in Figure 5-17 is an example of a called subroutine that will mov e a block
o f data from one location to another. The three parameters of (1) move-from address,
(2) move-to address, and (3) length of block are provided to the subrout i ne either
through registers 0 to 2, or by the three words following the calling program's BLWP
insruction, or by a combination of both. The block move subroutine first interrogates
the words following the calling program ' s BLWP instruction; if a zero is found, it
looks in a register for the parameter. In Figure 5-17, the calling program provides
the move-from and block length parameters in registers, and the move-to parameter in
the second word following the BLWP instruction.

LI
LI
BLWP
DATA
DATA
DATA
(a)

MVBLK
MVBLK1

MVBLK2
MVBLK3
MVBLK4

(b)

MOVE -FROM ADDRESS
MOVE 125 BYTES
BRANCH TO SUBROUTINE
MOVE-FROM ADDR IN RO
MOVE-TO ADDRESS
BYTE COUNT IN R2

RO,>F100
R2, 125
@MVBLK
0
>-F200
0

Calling Program

DATA
MOV
MOV
JNE
MOV
MOV
JNE
MOV
MOV
JNE
MOV
MOVB
DEC
JNE
MOV
RTWP

.:>FF90,MVBLK1
13' 12
* 14+' 1
MVBLK2
* 13+' 1
*14+,2
MVBLK3
*13+,2
*14+,3
MVBLK4
*13,3
*1+,*2+
3
MVBLK4
12' 13

WP, PC OF SUBROUTINE
SAVE WP
GET "FROM" ADR
NON-ZERO: PARM IN-LINE
PICK UP FROM REG INSTEAD
GET "TO" ADR
PARM IN IN-LINE CODE
GET FROM REGS
GET LENGTH
IN-LINE PARM
GET FROM REGS
MOVE BYTE
ONE LESS TO GO
NOT DONE YET
RESTORE WP
RETURN TO CALLING PROGRAM

Move Block Subroutine

Figure 5-17 .

Move Block of Bytes Example Subroutine

5-50

5.11 BLOCK COMPARE SUBROUTINE
Figure 5-18 shows a sample block-compare subroutine which accepts three parameters
from the calling program, in the same manner as the block-move subroutine (paragraph
5.10.1). This compare subroutine inspects two strings, comparing successive bytes
until an unequal byte is found or until the specified string length is exhausted. The
Status Register bits in register 15 are updated accordingly, and the subroutine
returns to the calling routine with the altered status bits, which may be used
immediately for conditional jumps.
The sample calling program is at the top of Figure 5-18. Note that the conditional
jumps follow directly after the calling code, so the calling program simply compares
(through the subroutine) and jumps, in the normal programming manner.

LI
LI
BLWP
DATA
DATA
DATA
JLE
JGT
(a)

CMBLK
CMBLK1

CMBLK2
CMBLK3

..

CMBLK4

CMBLK5

(b)

RO,>F100
R1 ,>F200
@CMBLK
0
0
100
$+10

FIRST BLOCK START ADDRESS
SECOND BLOCK START ADDRESS
BRANCH TO SUBROUTINE
START ADDR. IN RO (1ST BLOCK)
START ADDR. IN R1 (2ND BLOCK)
COMPARE 100 BYTES
IF LESS THAN OR EQUAL, JUMP
IF GREATER THAN, JUMP

Calling Program

DATA
MOV
MOV
JNE
MOV
MOV
JNE
MOV
MOV
JNE
MOV
CB
JNE
DEC
JNE
STST
RTWP

>FF90,CMBLK1
13' 12
* 14+' 1
CMBLK2
* 13+' 1
*14+,2
CMBLK3
*13+,2
*14+,3
CMBLK4
*13,3
*1+,*2+
CMBLK5
3
CMBLK4
15

WP, PC OF SUBROUTINE
SAVE WP
GET "A" ADR
GET IN CALLER REG
GET "B" ADDR
GET FROM IN CALLER REG
GET LENGTH
GET FROM REG
LOOK AT STRINGS
FOUND UNEQUAL
ONE LESS BYTE
STILL MORE TO LOOK AT
STORE FINAL STATUS
RETURN TO CALLING PROGRAM

Compare Block Subroutine
Figure 5-18.

Compare Blocks of Bytes Example Subroutine

5-51

5.12 UNIT ID DIP-SWITCH
The Unit ID switch is a very versatile piece of hardware. The practical uses of this
small device are limited only by the imagination. The proper way to read the switch
settings is shown in Figure 5-19 .
One exampl e use of the switch is in a multidrop environment where each
communications line is assigned an ID number through the settings on the
same software can be used in all the boards in the system, instead
maintain up to 32 separate copies, each unique only in an I.D . field.
shows an example program segment in a communications routine.

board on the
switch. The
of having to
Figure 5-20

Another example for use is in systems configuration. Whereas the main communications
port (P2) is designed for use specifically for a terminal, the auxiliary
communications port (P3) is a general purpose RS-232 port and can be connected to
modems, serial line printers, device interfaces s uch as cassette or floppy disk
controllers, etc., as well as terminals. The switch can be set to indicate the nature
and baud rate of the device attached to the remote port. Figure 5-21 shows a program
segment example.
5.13 CRU ADDRESSABLE LED
The light-emitting diode (LED ) DS1 on the TM 990/101M is addressable through the CRU
at software base address 0000 15. Writing a zero t o the LED turns it on and writing a
one turns it off. Figure 5-22 shows a sample routine to blink the LED on and off once
a second, using the TMS 9901 timer. The LED is on for one-quarter second and off for
three-quarters of a second.
5.14 CRU ADDRESSABLE LED
The TIBUG XOP routines (XOP 8 to 14) are written to accomplish input and output
through a TMS 9902. When the TIBUG monitor is entered, the address for all 1/0
is directed to the main TMS 9902 (through connector P2). Any time a user program
branches back into TIBUG at address 0080 15 or when a RESET function is activated, the
CRU address is set to the main TMS 9902. However, a user program may use all of the
above-mentioned XOP calls to program any TMS 9902 in the system by first moving the
software base address of the desired TMS 9902 into R12 of the 1/0 routines; this
register is located at M.A. FFDEi6· In other words, move the software base address
for the TMS 9902 (board addresses shown in Table 5-3) into memory address FFDE 1 5.
Figure 5-23 is an example where both serial I/O ports of the TM 990/101M are activated
for conversation to each other. Two terminals are assumed to be connected, one to each
port, and the operators may type messages to each other. This principle can be
expanded to support any of a number of TMS 9902-controlled serial I/O ports. (A
variety of custom line interfaces may be used with a TMS 9902.)
The write c haracter XOP servi·c e routine first ensures that the Request-to-Sent signal
is active. This signal is not deactivated by TIBUG so that modem users will retain
their data carrier. If a modem user wishes to drop the data carrier, the affected TMS
9902 must be addressed by the user program, and then the Request-to-Send signal is
deactivated through the CHU.
Only the main TMS 9902, at CHU software base address 0080 15 is initialized by TIBUG;
other TMS 9902 's in a system must be initialized by the user. Note the f irst portion
of the example program in Figure 5-23. Part of TIBUG's initialization is to sense the
baud rate of the attached terminal. If the baud rate is 110, 300, or 12 00 baud, then
the XOP routine wai ts 200 milliseconds after transmitting a ca rri age return. In
addition, 1200 baud causes every character transmitted to be f ollo wed by 25
milliseconds of delay time . Only at 2400 and 9600 baud are charac ters transmitted
without delays.

5-5 2

..

For 110, 300, and 1200 baud, the monitor ASRFLAG is set to one to cause a wait state
following writing of a carriage return. If the TIBUG I/O XOP routines are used for
other I/O ports, the state of the monitor's ASRFLAG will also govern delay loops used
by the Write Character XOP. The user should then swap out the contents of the ASRFLAG
(memory address FFF4 16 ) with one of the three values of ASRFLAG as listed in Table
5-7.

SWITCH 5 LSB WHEN READ ~--

--.

SET TO ON , ZERO READ (GROUNDED)

1

2

3

4

0
N

0
F
F
SET TO OFF . ONE
SWITCH 1 MSB WHEN READ

RE A D--~

NOTE
If all five switch settings are stored (using CRU),
switch 1 would be the MSB and switch 5 would be the LSB.
For example, if switch 1 was set to OFF, and the others
set to ON, storage of the five settings would be
represented by 10 16 or 10000 2 . Code to store the switch
contents in register 0 is shown below:
*READING THE DIP SWITCH
CLR
RO
LI
R12 ,>40
STCR
R0,5

CLEAR HOLDING AREA
DIP SWITCH ADDRESS
SWITCH VALUES IN REGISTER 0

Figure 5-19.

Reading the DIP Switch

5-53

~

*

MULTIDROP SYSTEM WITH DIP SWITCH
REGISTER 1 CONTAINS DESIRED ID VALUE
CLR RO
CLEAR HOLDING AREn
LI
R12 .>40
DIP SWITCH ADDRESS
:::TCF FW, ~_::;
C
RO,Rl
.JEC! PROCE:::

SWIT CH VALUES IN REG. 0
IS MESSAGE FOR ME?
YES. GO PROCESS IT

BLWP @C LRBUF

NO,

CL.EAR Bl..IFFEr7\

RHJF'

Figure 5-20.

*

Example Code The Check Board ID at DIP Switch
for Multidrop Environment

SYSTEMS CONFIGURATION EXAMPLE
CLR RO
CLEAR HOLDING AREn
LI
R1'2, >4 0
DI p :;:;i..n TCH CF:IJ rlDDRE:::::::
:3TCR R0,5
LI

Rl ,> 1 0

czc

Rl , RO

,.JNE

NOTUZD

~:RL

Rl, 1
Rl, RO

czc
.JEG!

TERMNL..

:::RL

RL 1

czc
.JEO
SRL

czc

.JEG!
::::RL

czc
.JEO
XOP

R1, RO
MODEM
R1. 1
R1 ,RO
IODEV
Rl, 1
F:l, RO

PRNTR
@SYSERR,14

*

SWITCH vnLUES IN REG. 0
LOAD "1 " BIT FOR t.ir1LL I MG ciJMr:·r,
I S REMOTE PORT USED?
NO , ,_llJMP OUT OF ROIJT I NE
SET TO >08 FOR CHECK
ID2: IS TERMIN~L CONNECTED?
YE::::, I [1:3 , I D4 ., IDS c. BAUD Rr:TE
NO, SET TO >04 FOR CHECK
ID3: MODEM CONNECTED?
YES, ID4, ID5 ~ MODEM TYPE
NO, SET TO >02 TO CHECK ID~
ID4: t/O DEVICE CONTROLLER?
YES, 105, 1 ~ TAPE, 0 = FLOPP Y
NO , SET TO >01 TO CHECK ID4
ID5: SERIAL LINE PRINTER?
YE::::
NO, PRINT ERROR MESSAGE
BECAUSE WRONG SWITCH SETTINGS

Figure 5-21.

Coding Example to Ascertain System Configuration
Through DIP Switch Settings

5-54

BLINK

TXMIRA

**

I[IT

0001
0002

*

*
*
*
*

0003
0004
0005
00Ct6
0007
0008
0009
0010
0011
0012
001:3
0014
0015
001~.

936227

*
*
*
*
*
*
**

*
**

FCOO

0017
0018 FCOO
FC02
0019 FC04
FC06
0020 FCOE:
FCOA
0021 FCOC
0022 FCOE
FC10
0023 FC1 2
0024 FC14
FC16
0025 FCl::'.:
0026
0027 FClA
FClC
0028 FClE
FC20
002'? FC22
FC24
0030 FC26
FC2:3
00:::: 1 FC2A
FC2C
0032 FC2E
0033 FC:30
0034 FC:32
00:35 FC34
0036 FC36
FC:3:3
00::::7 FC::::A

02EO
FFOO
(:(1(:.0

OOOE
0202
0420
CC42
0202
FDOO
CC42
0202
0380
C442

o::::oo
0000
020(:
0 100
020::::
(1:300
0204
0:300
0205
000:3
3104
:30:33
04CC
1[100

**

16:02:28

121178

PAGE 0001

" BLINK ·'

*THIS *PROGRAM
* * SETS*

* * * * * * * * *
UP THE INTERRUPT LINKING AREA AND THE
TIMER AT THE TMS 9901 . IT EXECUTES THE TIMER. WHEN THE
THE TIMER COUNTS DOWN, AN INTERRUPT IS EXECU TED THROUGH
INTERRUPT TRAP 3 WHICH TRANSFERS CONTROL TO THE ISR AT
THE BOTTOM OF THIS LISTING. THE CALLING PROGRAM ANU I SR
USE THE SAME WORKSPACE C>FFOO>. THIS PROGRAM IS CODED
AT ABSOLUTE ADDRESSES USING THE AORG ASSEMBLER DIRECTIVE
THUS, IT CAN BE CODED USING THE LINE-BY-LINE ASSEMBLER
WITH THE SLASH COMMAND USED INSTEAD OF THE AORG COMMAND.

*

*

*

*

*

*

*

*

*

*

*

CALLING PROGRAM
AORG >FCOO
SET UP INT3 LINKING AREA
LWPI >FFOO

BEGIN CODE AT M.A. >FCOO
WORKSPACE ADDR 

MOV

@} OOOE,1

INT3 PC VECTOR TO Rl

LI

2,>04 20

PLACE BLWP MACH. CODE IN R2

MOV
LI

2,*1+
2. >FDOO

MOVE BLWP CODE TO LINK AREA
nDDRESS OF VECTORS TO ISR

MOV
LI

2,• 1+
2, > O :~:::::o

MOVE VECTOR ADDR TO LIN~ nREA
PLACE RTWP MACHINE CODE IN R3

MOV 2,• 1
MOVE RTWP TO LINV AREn
LOAD AND EXECUTE TIMER AT TMS 990 1
LIM! 0
DI SABLE INTERRUPTS
LI

12.>0100

TMS 9'?01 CRU ADDRESS

LI

3,

:> 0~:00

CLOC¥ MODE, COUNT

LI

4,

>o::::oo

INTERRUPT MODE, ENnBLE INT3

LI

5,, ·3

~

1

INITIALI ZE TIMER COUNTER

LDCR 4,4
LDCR :3 , 2
CLR 12

o::::oo

LIM! 3

ENABLE INT3 AT 9901
STnRT CLOCK AT 990 1
POINT TO L . E.D.
TURN L.E.D. OFF
ENABLE INT~: AT TM·::~ 9900

(l(H):3
lOFF

,_IMP

WAIT HERE FOR INTERRUPT

Figure 5-22.

'.380

0

$

Coding Example to Blink L. E.D. On and OFF (Sheet 1 of 2)

5-55

TXMIRA

BLINI<

0039
0040
0041
0042 FDOO
0043 FDOO FFOO
FD02 FD04
0044 FD04 0300
FD06 0000
0045 FD08 020C
FDOA 0100
0046 FDOC lDO::::
0047 FDOE 0209
FD 10 3 D09
0048 FD12 OA19
0049 FD14 0269
FD16 0001
0050 FD18 33(:9
005 1 FD1A lEOO
0052 FD1C 04CC
0053 FD1E 0605
0054
0055 FD20 C145
0056 FD22 1606
0057 FD24 1EOO
0058 FD2(:. 0205
FD28 0003
0059 FD2A 0300
FD2C 0003
0060 FD2E ·03so
0061 FD:30 1000
0(1(:.2 FD32 o::::oo
FD34 0003
006:::: FD36 o::::::::o
0064
0000

NOTE :

*
*
*

936227

**

1 2 1 /7:"3

PnGE (lf)02

INTERRUPT '=:EF:VI CE ROUTINE

**

AOR(; >FDOO
DATA >FFOO, ) FD04

BEGIN CODE nT M.A. >FDOO
lo-JP , PC OF I 3F:

LIM!

0

DISABLE INTERRUPTS

LI

12 ,)0100

TMS 990 1 CRU ADDRESS

SBO
LI

:3

CLEAR INTERRUPT AT 9901
1/4 SECOND COUNT FOR TMS 990 1

SU\

9, 1

ORI

9, 1

9, 15625

SHIFT CLOCK COUNT
:?.ET CLOC~< MODE

LDCR 9, 15
START CLOCK
SBZ 0
SE T INTERRUPT MODE AT 9901
CLR 12
L.E . D. CRU ADDRESS
DEC 5
DECREMENT COUNTER
SET L. E. rf. TO ON OR OFF '=:TfHU'=:
REG . 5 "= ZERO?
MOV 515
NO, TURN OFF L.E.D .
.JNE > Frc~:o
YES, TURN ON L.E . D.
SBZ (l
5, :;:
RELOAD INTERRUPT COUNT
LI
LIMI :3

ENABLE I NT::::

RTWP
SBO 0
·-:LIMI ·-·

RETURN TO PROGRAM
TURN OFF L.E.D
ENABLE INT3

RTWP
END

RETURN TO PROGRAM

ERRO R~:

As an exMcise, the user can load and execute this code :
( 11 load the machine code values shown in column 3 into
the memory locations shown in column 2, or (2) reassemble;
if the Line-By-Line A-'>I... (LBLAI is used, substitute the
slash command for the AORG directive and follow the
DATA and TEXT statement conventions for the LBLA. Ex·
acute using the E TIBUG command.

Figure 5-22 .

Coding Example to Blink L.E.D. On and Off (Sheet 2 of 2)

5-56

TWOTRM
0001
0002
0003
0004
0005
0006
0007
0008
000'?
0010
0011
0012
0013
0014
0015
0016
0017
0018
001'?
0020
0021
0022
002:3 0000
0002
0024 0004
0006
0025
0026 000:::
0027 OOOA
0028 oooc
OOOE
0029 0010
0030 0012
0031 0014
0032 0016
0033 0018
0034 001A
0035 001C
00:36 001E
0037 0020
0022
0038
003'?
0040 0024
0041 0026
0042 0028
0043 002A
0044 002(:
0045 002E
0046 0030
00:3 2
0047 0034
0048 0036
0049 0038

TXMIRA

936227
IDT

**

08:11:39

122/78

PAGE 0001

~ TWOTRM ~

*----------------------------------------------------------*
TWO TERMINAL PROGRAM EXAMPLE

*
*
*
*
*
*
*

*
*
*
*
*
*
*

*
*
**

02EO

THIS ROUTINE INITIALIZES THE AUXILIARY I/O PORT
OF THE TM990/101M MICROCOMPUTER. BOTH SERIAL
PORTS ARE THEN USED IN A CONVERSATIONAL MODE
WITH EACH OTHER. THE PROCEDURE IS TO INSPECT
THE RECEIVE BUFFER BIT IN THE ADDRESSED TMS9902
TO SEE IF A CHARACTER HAS BEEN ASSEMBLED
IN THE UART. IF SO, IT IS ECHOED TO THE
ORIGINATING TERMINAL, AND THEN TRANSMITTED
TO THE OTHER TERMINAL. THEN THE OTHER
TERMINAL IS INSPECTED FOR A CHARACTER, ETC.
THE POINTS TO NOTE ARE:
1> THE AUXILIARY TMS9902 MUST BE INITIALIZED.
2> THE OLD "ASR"-FLAG MUST BE SAVED,
AND A NEW ONE DETERMINED FOR THE
NEW TERMINAL .
3) EVERY WRITE OPERATION CONSISTS OF
MOVING THE DESIRED ADDRESS TO TIBUG,
AND MOVING THE DESIRED "ASR"-FLAG TO TIBUG.

·----------------------------------------------------------LWP I REGS
USE SPARE SPACE AT END OF PROG

oocc ·'
020C
0180

LI

1D1F *
1000
3220
OOB6·"
lEO[I
04CO
04C2
1FOF T::HSP
13FE
0580 ~3PLOOP
1FOF
16F[I
0201
OOA2 ·'

INITIALIZE AUXILIARY SERIAL PORT
SBO 31
RESET UART
NOP
RESET TIMING DELAY
LDCR @CTL,:3
LOAD CONTROL CHARACTER
SBZ
CLR
CLR
TB
,.JEQ
INC
TB
._INE
LI

12. >0 180

13
0

-,
.....

15
TS TSP
0

15
SPLOOP
1. TABLE

AUXILIARY PORT ADDRESS

BYPASS INTERVAL REGISTER
BAUD RATE LOOP COUNTER
ASR FLAG FOR THIS PORT
LOOI< AT RIN
WAIT FOR USER TO TYPE SOMETHIN
UP BAUD LOOP COUNTER
RIN NOW HAS A SPACE:
DROP OUT ON A MARK
BAUD RATE TABLE

*
*

8C40
1202
05C1
lOFC
3811

C051
0281
OlAO
1103
1 (:.0:3
0702

NOW INSPECT BAUD RATE TABLE FOR A LOOP
COUNT WHICH MATCHES, THEN LOAD BAUD RATE.
BDLOOP f"
0.•1+
LOOK AT ATBLE LOOP COUNT
.JLE MATCH
IF <: OR == WE HAVE A MATCH
INCT 1
SKIP BAD BAUD RATE, NEXT LOOP
.JMP BDLOOP
LOOK AT NEXT LOOP COUNT
MATCH LDCR •1. 12
LOAD BAUD RATE CONTROL VALUE
MOV •1·1
GET VALUE ITSELF
1,>01AO
1200 BAUD ?
CI
,JLT HIRATE
.JNE BEGIN
-,
SETO .....

NO, HIGHER BAUD RATE
NO, LOWER BAUD RATE
SET LOCAL ASR FLAG

Figure 5-23. Example Program to Converse Through
Main and Auxiliary TMS 9902's (Sheet 1 of 3)
5-57

TWOTRM

TXMIRA

936227

**

1):3: 11: 39

122/78

PAGE 0002

JMP BEGIN
AND PRINT BEGIN MESSAGE
MARK NO  DELAY
0051 003C 0582 HIRATE INC 2
*
THE AUXILIARY PORT IS NOW UP. PRINT GREETING.
0052
AUX. PORT ADR. TO TIBUG
0053 00'.3E C:320 BEGIN MOV @X180,@XOPCRU
0040 OOAO·'
0042 FFOE
MDV @A:=:RFLG, ;:::
SAVE MAIN PORT ASR-FLAG
0054 0044 COEO
0046 FFF4
0055 004s c::.:02
MOV 2,@ASRFLG
AUX. PORT ASR-FLAG
004A FFF4
XOP O, 13
READ BY OLD !NIT. CHAR.
0056 004C 2F40
XOP @BGNM:::G , 14
0057 004E 2FAO
PRINT BEGIN MESSAGE
0050 OOB7 ·'
MOV @XBO . @XOPCRU
MAIN PORT ADR TO TIBUG
0058 0052 C820
0054 OO'?E ·'
0056 FFDE
MOV 3,@ASRFLG
MAIN PORT ASR-FLAG
0059 0058 c:::o:.::
OOSA FFF4
XOP @BGNMSG , 14
0060 005C 2FA'O
PRINT BEGIN MESSAGE HERE, TOO
005E 0087 ,.
0061
THIS IS THE MAIN LOOP.
*
0062
FIRS T ADDRESS MAIN PORT, THEN THE AUXILIARY PORT
*
0063 0060 C320 LOOP
MOV @XB0,12
ADDRESS FOR MAIN PORT
0062 009E ·'
0064 0064 1F15
TB
21
CHARACTER TYPED HERE ?
,.JNE NEXT
0065 0066 1608
NO, TRY OTHER PORT
0066 (1(168 c::.:oc
MOV 12,@XOPCRU
YES, GIVE ADDRESS TO TIBUG
006A FFDE
0067 006(: (:803
MDV 3, @A:=:RFLG
MOVE A:=:R-FLAG
006E FFF4
001S8 0070 2ECO
XOP C» 11
REnD / ECHO CHAR TO ORIGINATING
MOV @X180,@XOPCRU
AUXILIARY PORT ADDRESS
006'? 0072 C820
007 4 OOAO ·'
0076 FFDE
0010 oo7s c:=:o2
MOV 2, @A:=:RFLG
AUXILinRY PORT ASR-FLAG
007A FFF4
0071 007C 2FOO
XOP 0,12
WRITE CHARACTER TO OTHER TERM!
0072 007E C320 NEXT
MOV @X180,12
ADDRESS FOR AUXILIARY PORT
0080 OOAO ,.
0073 0082 1F15
TB
21
CHARACTER TYPED HERE ?
0074 0084 16ED
JNE LOOP
NO, TRY MAIN PORT
0075 008c, C80C
MDV 12,@XOPCRU
YES, GIVE ADDRESS TO TlBUG
0088 FFDE
0076 008A C802
MOV 2.@ASRFLG
MOVE ASR-FLAG
008C FFF4
XOP 0,11
0077 008E 2ECO
READ/ECHO CHAR TO ORIGINATING
0078 0090 C820
MOV @X80,@XOPCRU
MAIN PORT ADDRESS
0092 009E ·'
0094 FFDE
0079 0096 C803
MOV 3.@ASRFLG
MAIN PORT ASR-FLAG
00'?8 FFF4
0080 009A 2FOO
XOP 0.12
WRITE CHARACTER TO MAIN TERMIN
0081 009C 10E1
JMP LOOP
0082
0050 00::'.:A 1001

*-----------------------------------------------------------

Fi ure 5-23 . Example Pro ram to Converse Throu h
Main and Auxiliary TMS 9902's (Sheet 2 of 3

5-58

TWOTRM

0083
0084
0085 009E 0080
0086 OOAO 0180
0087
FFF4
0088
FFDE
0089 OOA2 0010
OOA4 00:34
0090 OOA6 0040
OOA8 OODO
0091 OOAA 0070
OOAC 01AO
0092 OOAE 0200
0080 0400
0093 0082 0400
0084 0638
(1094 OOB6
62
0095 0087
OD
OOB8
OA
0096 0089
42
0097 OOC8
OD
00(:9
OA
OOCA
00
0098 oocc 0000
OOCE 0000
OODO (l(l(l(l
0002 0000
0004 0000
0006 0000
OOD8 0000
OODA 0000
OODC 0000
OODE 0000
OOEO 0000
OOE2 0000
OOE4 0000
OOE6 0000
OOE8 0000
OOEA 0000
0099

•~
•

I

TXMIRA

...

I

t
r

9 :36227

*
*X80
X180
ASRFLG
XOPCRU
TABLE

**

08: 11 : :39

122/78

PAGE

(l(H):3

DATA AREA
>0080
:>0180
>FFF4
>FFDE
>10,>34

MAIN PORT
AUXILIARY
TI BUG ASR
TI BUG XOP
9600 BAUD

DATA } 40,}DO

2400 BAUD

DATA :>7C» >lAO

1200 BAUfl

DATA )·20(1, )-4[10

300 BAUD

DATA >400.>638

110 BAUD

DATA
DATA
EQU
EQU
DATA

BYTE >62
CTL
BrJNMSG BYTE }OD, >OA

R12 BA~; E ADDRESS
PORT R12 BASE ADORES
FLAG ADDRESS
R12 ADDRESS

9902 CONTROL

TEXT ·' BEGIN OPERATION ·'
BYTE >OD,>OA.>OO
REGS DATA

o.o.o.o,o.o,o,o,o.o.o,o.o.o.o.o

END

0000 ERRORS
'·

Converse Through
Sheet 3 of 3

Main and Auxiliary

5-59

Table 5-7.
ASRFLAG
Value*

ASRFLAG Values

Description/Recommendations

Recommended Baud Rate

Positive No .

2400, 9600

No delays. Use for CRT's, modems.

Zero

110' 300

Carriage Return Delay only. Use for hard copy
terminals .

1200

Carriage Return and Character padding delays.
Use with "T" command if terminal is not a
TI 733.

Negative No.

.

*ASRFLAG located in RAM at M.A. FFF4 16

5-60

SECTION 6
THEORY OF OPERATION
6. 1 GENERAL
This section presents the theory of operation of the TM 990/101M microcomputer.
Information in the following manuals can be used to supplement material in this
section:
•

TMS 9900 Microprocessor Data Manual

•

TMS 9901 Programmable Systems Interface Data Manual

•

TMS 9902 Asynchronous Communications Controller Data Manual

•

TTL Data Book, Second Edition

•

Bipolar Microcomputer Components Data Book

•

The MOS Memory Data Book.

Figure 6-1 shows a block diagram of the TM 990/101M, highlighting the four major
buses:
•

Address bus

•

Control bus

•

Data bus

•

Communications register unit (CRU) bus

In normal operation the TMS 9900 microprocessor commands the address bus and most of
the control bus; the data bus is bidirectional, driven by both the microprocessor and
the memory devices. The two-line CRU bus is not bidirectional; the serial output line
is microprocessor driven and the serial input line is driven by the CRU device.
The major features of the TM 990/101M microcomputer board are the clock driver, the
microprocessor, the TMS 9901, the two TMS 9902 ' s and peripheral circuitry, the
bidirectional and normal backplane buffers, the EPROM, the RAM, the additional CRU
devices, and the miscellaneous signals. These features are discussed in the fol l owing
paragraphs of this section .
6 . 2 POWER SPECIFICATIONS
Approximate power values required by the TM 990/101M-1 are listed in the following
table:
Current
-12V

+5V

+12V

Watts

Typical

0.2A

1.8A

0.25A

15.0W

Maximum

0.35A

2.5A

0.3A

19.7W

6-1

•

~

'

MEMORY
AD RESS
DECODE

2 K BYTE
TMS

J,

4046'1

y

v-

I

.J711

TMS
2708
/ 2716

TMS
2708
/ 2716

l.-1\
IV

L/\

r-v

Ill

::l

~

f

"'- ' 0

f

cc

!Z ,___

c:

]\

0

"l
Cl>

"'
I
_.

u

MEMORY
CONTROL

48MHz

TIM
9904

1-3

3:

,____

--

~1-i

.

1

/'2'11111

,

3M Hz
CLOCK

ld

r---I R.SEi

~

TMS
2708

~

n

TMS
2708
/ 2716

r-v

/2716

BUFFER
CONTROL

lfour)

A

v
I-'•
JQ

-v

4046'1

v

(four>

J

"%]

,_....

A--

2 K BYTE
TMS

•

16
DATA BUS

,2708

Vt

I\

,.2711

~

y

DATA
BUFFERS

~

••
ADDRESS
BUFFERS

n

)

I'\)

I~

v!

L

CRU BUS

......

LOAD
._____

-

0

RESET
/ LREX

Q

.I

+

-

INTERRUPTS

t::I

I-'·

INT1· 1NT15

Ill

14

TMS
9901

/

)q

"l
Ill

s

~

CRU
ADDRESS
DECODE

3:
o:l

~

.., ~

~

15

,

0_.

6+

EDGE
TRIGGER
LOGIC

CJ

TMS
9902

Ml~.

CNTL

h

r-

-

L

cc

...u0

...z

SERIAL
PORT
A

z

0

u
~

"'
MICROTER- 1 - - MINAL

;-

.....__

TMS

9902
/ 9903
1/ 9

RS·232
, TERMINAL

HTTYor
ULTIDROP

INT6

7

~I

RS·ZI!
TERMINAL

Lcc

SHARED 1/0

I

~

DEDICATED 1/ 0

EDGE CONNECTOR
PARALLEL PORT

r-f

•

I
L.E. D.

"
0

"'
>

/"-::...

!

TMS
9900

0

...u

Ill

lJ I •

MISC.
CONTROL .

~

v

"'zz

..."'

l.O

"'I

u

MISC
CONTROL
SIGNAL
•nd
CRU
BUFFERS

:E

""
lC

r--v

cc
0
....

--"

~

CONTROL BUS
ADDRESS BUS

~

'

DTR

DIP
SWITCH

l-

...0u
"'zz
0

u
<(

iii
'--

SERIAL
PORT
B

Ill

The supply - 5V is derived on the board by the UA7905 regulator from the -1 2V line
supplied from off board. The - 5V supply is used primarily by the TMS 9900
microprocessor and the TMS 2708/2716 EPROM's for back-biasing the substrate, and by
the multidrop interface as a supply voltage. The -12V supply is used for the EIA line
drivers as well as for supplying the voltage to the - 5V regulator.
The +12V supply is used by the TMS 9900 microprocessor and the TMS 2708/2716 EPROM's
as the main voltage supply since these are MOS parts. The +12V also is used for the
EIA line drivers.
All integrated circuits on the board, except the EIA line drivers, use the +5V supply,
and because of the heavy load this voltage is not derived by an on-board regulator but
must be supplied from off the board . The MOS parts use this supply for TTL
compatibility, and, in fact, the TMS 9901, 9902, 9903, and 4045 use only this voltage
for supply since they contain internal charge pumps, eliminating the need for - 5 or
+12V in their operation.
Table 6-1 lists the pin assignments of each integrated circuit for the supply voltages
each uses .

Table 6-1.

Device
TMS 9900
TMS 9901
TMS 9902
TMS 9902/03 socket
TMS 9904
TMS 4045
TMS 2708/2716
74LS241, 74LS245
75188
75189
75154
75107
75112
74LS138, 153, 251 , 259; 74S287
74LSXX

Device Supply Voltage Pin Assignments

-12V

SUPPLY VOLTAGES TO PIN NUMBER
GND
+5V
- 5V
1

21
1

13
11

26 , 40
16
9
9
3 , 10
9
12
10
7

2,59
40
18
20
20
18
24
20

1

14
15
14
14
16
14

8
7

7

8
7

6-3

+12V
27

13
19
14

6.3 SYSTEM STRUCTURE
The block diagram in Figure 6-1 shows the system structure of the TM 990/101M
microcomputer board. The microcomputer design centers around five buses: power,
control, address, data, and CRU . The major blocks of the system are the processor, the
miscellaneous control signals, address decoding, on-board memory, the TMS 9901, and
two TMS 9902 serial ports, and the miscellaneous CRU devices.
Functionally, these major blocks represent the processing, memory and 1/0 portions of
the microcomputer.
Throughout the remainder of this section, each block's function is discussed, grouping
the explanations into three categories: processing, memory, and 1/0. The first subject
is the buses since the buses tie all the blocks together.
The power bus is explained in paragraph 6 . 2 above, so the following paragraph deals
with the remaining buses.
6.4 SYSTEM BUSES
The four major buses are subdivided by function in Table 6-2. By referring to the
schematics in Appendix G, each random logic line as well as the bus lines can all be
traced. All bus signals appear on connector P1.
6.4.1 ADDRESS BUS
The 16-line address bus consists of lines AO through A15. Only 15 of these, AO through
A14, are normally used for addressing memory. Memory access deals with a 16-bit word,
and A1 5 , the byte address bit, is not brought out of the TMS 9900 since byte
operations are handled by fetching a 16-bit word into the processor, and modifying the
addressed byte, rewriting the 16-bit word back to memory if necessary. Therefore, A15
appears only on connector P1 and is grounded to show a zero off-board, thereby
fetching words on even address boundaries.
On the board the address lines are routed to the address decoding PROM which, with
MEMEN, selects on-board memory if the address presented lies within the limits of the
memory map programmed into the PROM.
Lines AO, A1, and A2 also are routed to the 74LS138 external instruction decoder
where, upon a CRUCLK pulse, the state of the address lines determines whether a CRU
operation (AO, A1, A2 = 0) or an external instruction is occurring. This leaves A3
through A14 for CRU addressing; A3 through A14 are routed to the I/O decode logic and
the CRU devices.
6 . 4.2 DATA BUS
The data bus consists of 16 bidirectional lines which are routed from the processor to
the on-board memory and to the bidirectional buffers for off-board use . DO is the most
significant bit, and D15 is the least significant bit .
6 . 4.3 CRU BUS
The three lines in the CRU bus are CRUIN, CRUOUT, and CRUCLK. Whenever
present on the address bus and MEMEN is not also active,
a CRU
assumed. Note that even if some CRU device responds to the address
changes value or is in any way invalid, no harm is done because the data
CRUlN by the addressed device will be i gnored by the processor. Since
will poll CRUIN only when required, CRU address decoding is simplified .

6-4

II'

an address is
operation is
bus while it
presented to
the processor

Table 6-2.

Functional Device Connections

Signal

c

Bus Signals

Address Bus
AO' A1 I A2
A3, A4
A5, A6, A7, AB, A9
A10, A11 , A12
A13, A14
(A15.B)

Address decode PROM, external instruction decode
Address decode PROM, CRU decode logic, TMS 2716 EPROM
CRU decode logic, all memory devices
All memory devices, TMS 9901 , TMS 9902/3, one 74LS251
All memory devices, TMS 9901 , TMS 9902/3, both 74LS251's
Byte indicator : always zero, off- board signal onl~

Data Bus
D0- 07
DB- 015

Most significant byte, 1 EPROM/byte, 2 TMS 4045/byte
Least significant byte, 1 EPROM/byte, 2 TMS 4045/byte

CRU Bus
CRUIN
CRUOUT
CRUCLKB

CRU input line , TMS 9901, TMS 9902/3, 74LS251 (TIM9905)
CRU output line, TMS 9901, TMS 9902/3 74LS259 (TIM9906)
CRU clock, TMS 9901, TMS 9902/3, 74LS251 (TIM9905) I
74LS259 (TIM9906 ), Edge- triggered logic

Control Bus

HEMEN
DBIN
WE

MEMCYC
READY

Memory
Memory
Memory
Memory
Memory

control:
control:
control:
control:
control:

address decode PROM
RAM decode logic, data bus buffer control
RAM decode logic , all TMS 4045 RAM's
off- board only
slow EPROM logic, off-board WAIT state

Auxiliary Control

¢1, ¢3
.EXTCLK . B, CIT. B
~.B , RESTART.B,
RST, LUII5, IORST.B
INT1-INT6
INT7-INT15
HOLD, HOLDA
IAQ

Clock : TMS 9901, TMS 9902/3 , RESET/LOAD logic
Clock: off- board only
RESET/LOAD logic, TMS 9900, TMS 9901
Interrupt Control: dedicated TMS 9901
Interrupt Control: shared I/O, TMS 9901
Address, Data, Memory Control for DMA: TMS 9900
Miscellaneous: TMS 9QOO

6- 5

When an address is present on the address bus and MEMEN is not active and if AO, A1,
and A2 are all zero, the CRUCLK pulse is gated through the external instruction
decoder, and any data on CRUOUT is strobed into the addressed CRU device. This is a
CRU output operation, and it is distinct from an input operation in that CRUCLK is
active during output; whereas, it is inactive upon input.
As mentioned above , CRU input is achieved by the processor asserting an address while
keeping the MEMEN signal inactive , and then polling CRUIN at the appropriate time .

6.4.4 CONTROL BUS
This bus is not as homogenous as the other buses; therefore it is divided into groups
as shown in Table 6-2. Table 6- 3 gives a brief explanation of each function.

Table 6- 3.
Signal

Active State

Control Bus Functions
Group

Purpose

MEMEN (memory enable)

Low

Memory

Enables memory devices, address
on address bus is for memory

DBIN (data bus input)

Higb

Memory

Shows state of processor's data
bus: high is input to processor, low is output.

WE (write enable)

Low

Memory

Strobe to memory devices for
writi ng data to memory.

MEMCYC (memory cycle)

Low

Memory

Indicates beginning and end of
one memory cycle. For successive memory cycles, MEMEN can
be active continuously, MEMCYC
goes inactive between each
separate memory cycle.

READY

High

Memory

Indicates memory is ready with
read data on next clock, or has
disposed of data on write
cycle . Wait states are generated by pulling this line low.

WAIT

High

Memory

Acknowledges that memory is not
ready, indicating a wait state.

Low

Processor
Activity

Requests processor to give up
control of address, data buses
and MEMEN, WE, and DBIN.

High

Processor
AC'tivity

Acknowledges that processor has
given up control of buses given
above , and has suspended
activity.

HOLDA

6- 6

Table 6-3.
Signal

r.

Active State

Control Bus Functions (Concluded )
Group

Purpose

Low

Clock

TTL level clocks

EXTCLK.B

Low

Clock

External TTL clock input to
TIM 9904.

CLK.B

Low

Clock

Output of internal oscillator of
TIM 9904.

PRES . B

Low

Reset/Load

Causes reset interrupt

RST

Low

Reset/Load

Reset interrupt input, TMS 9900

Low

Reset/Load

External instruction, causes IORST
I/O reset to TMS 9901's. Does not
cause reset interrupt

Low

IOiiD

RESTART.B

Low
Low

Reset/Load
Reset/Load

Causes load function delayed by two
IAQ or idle pulses. (LOAD is name
of external instruction and load
function pulse)

INT

Low

Interrupt

Request for interrupt to TMS 9901

High

Miscellaneous Signifies this memory cycle to be
an instruction fetch.

IAQ

1- 15

6.5. SYSTEM CLOCK
The system clock is generated by a crystal and tank circuit tuned to 16 times the
desired system frequency. This network is attached to the TIM 9904 clock driver, which
counts down the input signal from the tank and crystal into four non-overlapping clock
phases at MOS signal levels for the TMS 9900. The inverse of these phases is output to
TTL levels for the remainder of the system .
Also on the TIM 9904, the reset function is latched and synchronously presented to the
TMS 9900; this ensures synchronization with the correct phase .
The crystal is a third overtone series/parallel- resonant crystal, set in an HC-18U
bolder (see Figure 6-?) .
The TTL clocks are routed to the RESET/LOAD and MEMCYC logic, as well as to the
P1 - connector and the TMS 9901 and TMS 9902/9903 ' s .

r:

CAUTION

l

I f pins 11 and 12 of the TMS 9904 (¢1 and ¢2) are shorted, the device wil l overheat and go i nto thermal runaway almost instantly.

6-7

XTAL 1
QUARTZ
CRYSTAL

CJ

18

, .,,

R

11>1

2

XT A L 2

19

'LS362

11

~TIM99041

TANK 1
O.l3µH

12

CLOCK
DRIVER

18 pF
TANK2

8
9

~;J

R

9

TMS9900
MICROPROCESSOR

Q3
28

•:A

R

o4

2

OSCI N

25

R = 10H

17

ct.7 K .n

8

20
Vee
~

+sv

Figure 6- 2.

+12V

Crystal-Controlled Operation

6.6 CENTRAL PROCESSING UNIT
The TMS 9900 microprocessor is the central processing unit (CPU) for the TM 990/101M.
The responsibilities of the CPU include :
•

Memory, CRU and general bus control

•

Instruction acquisition and interpretation

•

Timing of most control signals and data

•

General system initialization.

Figure 6-3 groups the TMS 9900 pins by function . The address bus addresses memory and
the CRU devices, and provides the codes for the external instructions. The data bus
carries all memory data, including instruction code as well as program data ~nd
addresses. Interrupt requests are encoded as a binary number by the TMS 9901 for
presentation to the TMS 9900 microprocessor.
Memory operations are initiated by placing an address on the address lines along with
MEMEN, OBIN , and eventually, WE. If the memory cycle is an instruction fetch, IAQ goes
active also. READY is sampled and the memory cycle is ended one clock cycle after
READY is active .

6-8

RESET

6

LOAD

GOES TO
{
RESET/LOAD
LOGIC

4_
7

-

41

IMSBI DO

-

TMS 9900

Dl

-

43

D2

IAO

D3

&t 5

-

62_
CONTROL BUS GOES
3

-

TO MEMORY DECODER,
MEMORY, EXPANSION
BUFFERS.

-

61
63

04

HOLDA

05

READY

06

-

WAIT

07

-

-WE
--MEMEN

D8

OBIN

DlO

-

09

!

,._9

7'i -

01

D12

o2

013

o3

014

-

-

47
48
49

-

-

--

-

51

.

54

55
56

04

-

50

1;."l

-

-

45

52

011
8_

-

44

46

')Q

-

FROM SYSTEM CLOCK

-

HOLD

42

DATA BUS GOES TO
MEMORY, EXPANSION
BUFFERS

--

--

D15
24

31

eRUIN

'In

60

(MSBI AO

eRUOUT

Al

e RUeLK

A2

23
22
;..

21

36
FROM TMS 9901

35

INTERRUPT CONTROL

34
33

A3

--INTREO

32

-

-

20
A4

19

teO

AS

1e1

A6

le2

A7

18

A8

IC3

17

16
15

A9
1

- 5V
+5V
+-12V

-

2

Ts9
27

26

Vee

A10

Vee

All

Vee

A12

Vss

A14

--

-

13

--

11
A13

-

14

12

Voo

-

10

-

Vss

l 40
]_'

Figure 6-3.

TMS 9900 Pin Functions

6-9

ADDRESS BUS GOES TO
MEMORY ANO 1/0 DECODER,
MEMORY, EXPANSION
BUFFERS, TMS 9901.
TMS 9902, WIRE ·WRAP AREA.

CRU operations are initiated by placing an address on the address bus. CRUIN is
sampled for an input operation; otherwise it is ignored, and for an output operation
the datum is placed on CRUOUT and strobed with CRUCLK. Aside from I/O purposes, CRU
operations also program the operation of such devices as the TMS 9901, 9902, and 9903 .
Figures 6 - 4 and 6 - 5 show the data flow and operational flowchart of the
microprocessor. Figure 6-6 shows the decoding of the external instructions. For more
information , refer to the TMS 9900 Microprocessor Data Manual.
6.7 RESET/LOAD LOGIC
After the clock and the CRU, the next block most clos~associated with microcomputer
operation is the random logic dealing with RESET and LOAD. This block initializes the
system and is also used to return control to TIBUG when using single- step operation
(refer to Figure 6-6).
6.7.1 RESET FUNCTION
The RESET pushbutton feeds a latch formed from back-coupled inverters for debouncing.
The PRES.B signal f'rom connector P1 joins the RESET pushbutton signal in a Schmitt
trigger gate to assure that multiple reset pulses due to noise or bounce do not affect
the microcomputer . After being inverted again, the reset signal is routed to the TIM
9904 which then synchronizes it with ¢3 and then presents the signal to the
microprocessor.
The RESET signal also goes to two flip-flops which generate the IORST signal, which
clears TMS 9901's and any other devices attached to it off-board. This IORST signal is
also generated by the external instruction RSET, but it is important to realize that
the RSET instruction in a program generates only IORST and not a full RESET interrupt.
IORST can be active for up to two o3 clock periods.
Reset causes the following to occur:
•

Clears 1/0 devices on IORST line (on board TMS 9901)

•

Inhibits memory write and CRU operations

•

Sets TMS 9900 status register interrupt mask to

•

Processor traps to vectors at

0000 and

0000

0002

Reset is caused by:
•

Actuating the RESET switch on the PC board

•

Setting tbe PRES.B signal to a logic ZERO state on connector P1 .

6- 10

iNfREO

ICO IC3
AO - A14

INTfRRUPT
REGISTER

MEMORY
ADDRESS
REGISTE R

Tl
12
PROl'ORA M COUNTE R

CONTROL
ROM

l'llOR KSPACF REl'OISTER

l
()

N
T
R
0
L

HOCi5

n

f\

HO LOA

COAD

l\L II

wr

READY
"IA ll
Mmn;
OBIN
Rf SET

CONT ROL
LOGIC

11\0

CRUC:L I<

(f> l

- '1>4
~••If

'

I OllM l f 1-l
~·" 1.-r.r 1111111

Ill 1;" IT 11

....
DO 01!>

Figure 6-4 .

l'IWIN

TMS 9900 Data and Address Flow

6-11

CRUOUT

INSTRUCTION
ACQUISITION
RESET SIGNAL
CAUSES IMMEDIATE
ENTRY HERE

INSTRUCTION

y
y

GET RESET VECTOR
!WP ANO PCI
FROM LOCATION 0 , 2
STORE PREV IOUS PC ,

y

WP. ANO ST IN NEW
WORKSPACE. SET
INTERRUPT MASK
(ST12- STl 51 ~ o

N
y

N

GET LOAD VECTOR
(WP AND PCI FROM
LOCATION FFFC 16,
FFFE 16

GET INTERRUPT LEVEL

STORE PR EV IOUS PC,

VECTOR IWf' ANO l'CI

WP. ANO S f IN NEW

STORE PREVIOUS PC,

WORKSPACE . SET

WP. ANO ST IN NEW

INTERRUPT MASK

WORKSPACE. SE T
INTER RUPT MASK (ST12
- ST 151 TO LEVEL -1

IST12

ST 151 , 0

Figure 6-5.

TMS 9900 CPU Flowchart

6-12

·~"
.~

I~

D Clfl

0

1------1

D CLA O

t--t----1 n

ClR O

«

l•lS IJ2

l4 LSl4

·~V

PRU 8

LK

Pt !M

!Ill .

-

II

0

0

LOAD

-

- --'

·~V

--.--,

r-·

ELEClROL VllC

L~

,

L_

w

_ -'VI,.,,._+---

CL K

•W

' IK
114

p

14lS7•

IJ

O CLR O t - - - - - - i I' Cl.A O 1-"'""
A.._,T_ _ _ __

II

_

1oorr soano
14LS74

__ _ J

LK

.,.

p

10

l 4LSIO

o

0

RSTt
TO ON ~OARD
110

114 ¥1

14LSOI
---~

I

j

I JU

ELECrROL YltC

L~

II

__ _ J

.---+- - -M
"'-'E'-M=EN'-------ID

PA

O

o

0

c~

•II

O
74LS14

14LS14

16
t-----~
"-------ICK

CLA

ClR

o

0

Fl'l01114 PROCHSO,_
CtACUll

Figure 6- 6 .

RESET and LOAD Logic

6 . 7.2 LOAD FUNCTION
The LOAD function is triggered by either activating RESTART.B or executing the
external instruction LREX. Both of these are combined in the same way the RESET
function is. The first flip - flop presents the LOAD request to the second, and the
second and third flip-flops count two IAQ or IDLE pulses and then present the LOAD
function request to the microprocessor. The second flip- flop clears the first one so
that only one LOAD is generated even though, for instance, the RESTART.B signal may be
continuously active.
RESET overrides LOAD because a RESET signal clears the LOAD flip - flops. This is
important when both requests occur simultaneously .
Load causes the following to occur:
•

LOAD function is delayed two instructions (IAQ) or idle pulses (IDLE), then
triggered

6- 13

•

Processor traps to vectors at M.A.

~FFFC

and >FFFE

Load is caused by the following if RESET is inactive:
•

Executing the software instruction LREX

•

Setting RESTART.B to logic ZERO state on connector P1.

6 . 7 . 3 RESET AND LOAD FILTERING
Installing a 39 microfarad capacitor at C18 will debounce the "'P'R"E'S.B signal. This
would be adequate for manual actuation by an SPST pushbutton to ground.
A 39 microfarad capacitor at C23 debounces the RESTART.B signal, suitable f or
connection to a manually actuated switch in the same way as above.
These capacitors are user options, and these values are suggested values .
6.7. 4 CLRCRU SIGNAL
The CLRCRU (clear CRU) signal is a power-up IORST which resets the edge- triggered
interrupt 6, the status LED, and remote serial port Data Terminal Ready signal . The
status LED is lighted and Data Terminal Ready is inactive.
6.8 EXTERNAL INSTRUCTIONS
The so-called external instructions are those which, when executed by the process or,
cause address lines AO, A1, and A2 to be set to a state, and CRUCLK to become active.
The instructions and descriptions are listed in Table 6-4.

Table 6-4 .

External Instructions

Opcode

AO

A1

A2

IDLE

0340

0

1

0

Suspends processor until RESET, LOAD,
or interrupt occur

RSET

0360

0

1

1

Zeroes TMS 9900 interrupt mask,
generates IORST

CKON

03AO

1

0

1

Not used on TM 990/101M

CKOF

03CO

1

1

0

Not used on TM 990/101M

LREX

03EO

1

1

1

Causes LOAD, delayed by two IAQ or
IDLE pulses

I nstruction

Description

6-1 4

The CKON and CKOF instructions are used by other 990-family systems to control the
system timer. On the TM 990/101M the system timer is incorporated into the TMS 9901;
hence, these instructions are not used.
The RSET instruction generates the IORST signal to clear all I/O devices (on board TMS
9901) attached to it~ It also clears out the status register interrupt mask, which
allows only a RESET interrupt or a LOAD function to be granted.
The LREX instruction causes a LOAD function request to be presented to the processor
after two IAQ or IDLE pulses. This means that the LOAD function occurs after two
instructions are executed following the LREX. TIBUG uses this function to do single
step by executing the LREX, a RTWP to the user, then one user instruction. The LOAD
function becomes active and vectors back to TIBUG, which then prints the processor
register.-s.
IDLE causes the processor to suspend operation; it is, in essence, a HALT instruction.
An interrupt or LOAD terminates the idle state.
In all cases, note that AO, A1 , and A2 are nonzero values so that these instructions
are differentiated from a CRU output operation.

6.9 ADDRESS DECODING
This subsection explains address decoding for both memory and CRU I/O along with their
memory maps. The memory address map configurations are shown in Figure 6- 7.
6.9.1

MEMORY ADDRESS DECODING

6.9.1.1 Memory Address Decoding PROM
The memory map is programmed in a 74S287 PROM as shown in Figure 6-8. The PROM is a
256 x 4 bit memory, and each four-bit word (D04 to D01) is used to determine memory to
be enabled . The most significant bit of the PROM word, D04, is tbe RAM enable control
line. Programming a ZERO on D04 will cause RAM to become active. Since there are two
banks of RAM on the board and since there is no room on the PROM to decode the two
banks separately, each bank is enabled by the state of address line A4. Therefore, all
RAM is decoded by the PROM as a complete block and cannot be separated.
The next two bits of the PROM word (D03 and D02) enable each EPROM bank separately and
directly. EPROM ' s are enabled by programming a zero .
The least significant bit of the PROM word (D01) is a negative- logic "OR" of the other
three bits of the PROM word. If any of the other three bits are zero, this bit must be
zero also. This signal indicates to data bus buffer control whether memory addressed
is on- board or off-board; a zero state indicates on-board memory .

6- 15

0000
'"Z]

......
~

0800

"'l
Cl>

1000

~

.°'

EPROM 1
tTMS 2708)
EPROM 2
ITMS 2708)

0000
07FE
OFFE

0800
OFFE

1000

EPROM 1
TMS2708
EPROM 1
TM S 2708

°'I
°'
~

I~....

3:
3:
(l)
8
0

"S

EFFE
RAM2
TMS 4045

F800

RAM 1
TMS 4045

'<
:i:Q.
Q.

"'l

(l)
(/.I
(/.I

......

F800

RAM 1
TMS 4045

F7FE
FFFE

a) 2K EPAOM (2708's)

2K RAM

RAM 2
TMS 4045

.__

lFFE

FFFE

RAM 2
TMS 4045

F800

RAM 1
TMS 4045

2K RAM

NOTES

:;$

1. All acldresses on hexadecimal.
2 . EPROM solectoon 1n eac h bank 1s a iumper option

FOOO

RAM 2
TMS 4045

F800

RAM 1
T M S 4045

F7FE
FFFE

c) 3K EPROM (2708 & 2716 )

2K RAM

1FFE

EFF E

EFFE
FOOO

F7FE

17FE

OFF -BOARD
M EMORY

OFF·BOARD
MEMORY

b) 4K EPROM (2708's )

EPROM 2
TMS 2 708

2000

EFFE

FOOO

OFFE
EPROM 2
TMS 2708

1800

2000
OFF ·BOARO
MEMORY

FOOO

OFFE
1000

1FFE

l.O
l.O

EPROril 1

H .1S 2 7 16

EPROM 2
TMS 2716

2000

"""3
3:

0000
07FE

1000
EPROM 2
TMS 2716

OFF ·BOARD
MEMORY

I
--.1

0000
EPROM 1
TMS 2716

F7FE
FFFE

d) 3K EPROM (2708 & 27161
2K RAM

The memory address decoding PROM is enabled by MEMEN when active low, and the lower
five input bits are the most significant bits of the 3ddress bus (AO to A4). The PROM
thus selects memory in blocks of 1K words . The upper three address bits of the PROM
have jumper options to choose between TMS 2708's and TMS 2716 ' s and to select-or
deselect on-board EPROM, and to configure the memory map either with EPROM in low
addresses and RAM in high addresses, or RAM low and EPROM high. There are thus eight
different address maps in the PROM controlled by the three jumpers (23 = 8). Each
address map consists of 32 four - hit words, showing the state of each lK word block in
memory.
When MEMEN is inactive , the PROM is disabled.
6.9.1 .2 EPROM Selection
There are two basic memory maps for the EPROM - one for the TMS 2708 1 s and the other
for TMS 2716 ' s. These correspond to cases (a) and (b) of Figure 6- 7. Each bank of
EPROM actually consists of two EPROM devices, one for bits 0 to 7 of the addressed
word, and the other for bits 8- 15. Beginning addresses are shown to the left of the
figure; ending addresses are shown to the right. Each EPROM bank is separate and can
be programmed into any location by reprogramming the address decode PROM.
Case (c) and (d) of the memory map in Figure 6-7 show what happens if the jumper is
configured to "2716" position, and TMS 2708 1 s ace used. Case (c) shows that if a word
at address 0000 is accessed, that same word can be read at 0800. Likewise, both 0002
and 0802 will address the same word, etc.
On the board, the jumper next to the EPROM's selects the proper pin configuration for
the particular EPROM in use. Note that address line A4 is routed to the EPROM when the
jumper is in the " 2716" position.
To deselect, or ignore , on - board EPROM, move the EPROM select jumper to connect pin
E12 to E13. This causes on-board EPROM sockets to disappear completely from the memory
map.

6.9.1.3 RAM Selection
The RAM is treated as one block, since it is decoded with only one output line from
the address decode PROM, There are four RAM ' s per bank and two banks in the block. The
selection of a specific bank of RAM is decided by the state of address line A4.
Selection is accomplished by the gate array shown in Figure 6- 8, Each RAM select is
set up by the PROM and A4, and becomes valid when WE goes low for a write, or OBIN
goes high for a read. Note that DBIN will assert at the same time MEMEN goes low
during a read cycle, reference Figure 6-10, but WE will not assert until some time
after MEMEN goes to 0. The user should be aware that a chip select will not occur
during a write cycle until after WE drops. This is to prevent fast RAMs, which sample
WE as soon as they are selected, from sampling WE before it goes low during a write
cycle.
At this point, the second jumper option becomes meaningful. This option selects where
EPROM and RAM appear in the memory map. In the normal "RAM HI" position, the RAM bank
address begins at F00016 and EPROM begins at 000016 · Moving the jumper plug to the
alternate position causes " 2708 " EPROMs to be at F00016 ( 11 2716 11 EPROM ' s begin at
E00015), and RAM to be at 000016·

6- 17

A4

WE
R23
4 IK

E11

-- (

OBIN

15

"'

-

v

1: 10

0

N
0
0

E9

....

E17

GAT E ARRAY

~

0

r0
~

(

270812716
El6
E15

UJ
....J
uJ
(/)

(/)

a:

w
~
:i=
=i
....,

U19
ADG

EPROMSEL

2

AO

3

E1 4

(

ADH

RAM HI

<{

::E
ru

15

f13
E12

Al

4

A2

7

A3

6

A4

5

ADF

0 04

ADE

003

ADD

002

AOC

001

9

RAM

10

ROM 2

11

ROM1

12

ONBOARDMEM

ADB
ADA
S2
14

-

MEMEN

745287
PROM

TABLE A . ADDRESS IN/ DATA OUT
ADDRESS
INPUT
ADH TO
ADA (LSB )
00
20
40
60
80
AO

co
eo

MAP
0
2

3
4

5
6
7

PROM OUTPUT (4 BITS EACH)
66FF
66FF
F FFF
CCAA
66FF
66FF
F FFF
CAFF

FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF

FFFF
F FFF
FFFF
FFFF
FFFF
FFFF
F FFF
FFFF

FFFF
FFFF
F FFF
FFFF
F FFF

FFFF
FFFF
FFFF

HFF
FFFF
FFFF
FFF F
FFFF
FFFF
FFFF
FFFF

FFFF
FFFF
FFF F
FFFF
FFFF
FFFF
FFFF
FFFF

FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF

TABLE B. MAP CONF IGURATION (SET BY JUMPERS)

MAP O =
Map 1 =
Map 2 =
M ap 3 =
M ap 4 =
Maµ 5
Map 6 c
Map 7 :

=

2708 OR
2716 USED?

LOW OR
HIGH RAM?

TMS 2716
TMS 2716
TMS 2716
TMS 2716
TMS 2708
TMS 270 8
TMS 2708
TMS 2708

Low RAM
Low RAM
High RAM
High RAM
Low RAM
Low RAM
High RAM
High RAM

Figure 6-8.

READ EPROM 7
No EPR OM
High EPROM
No EPROM
Low EPROM
No EPROM
Hi gh EPROM
No EPROM
Low EPROM

Memory Address Decode PROM

6-18

FFFF
CCAA
FF66
FF66
FFFF
FFCA
FF66
FF66

6.9.1.4 Memory Mapping
The memory map can be changed by the user substituting another user programmed PROM
in the address decoder socket. (The 743287 PROM's are available from your Texas
Instruments distributor.) Using the guidelines in paragraph 6.9 . 1 1 the user can
produce many different memory maps. In general, if active output is desired for any
particular input combination, the bit code is set to zero . Starting at the initial
input address to the PROM, the outpu~ states desired are determined. ADA is th~
least-significant address input, and ADH is the most - significant. D01 is the least
significant output bit 1 and 004 is the most- significant .
CAUTION
When planning a memory map , or when using any memory
off- board (such as a TM 990/201 or TM 990/206 memory
board), the memory devices on the TM 990/101M board must
not overlap in address space either with each other or
with devices off- board. On- board memory devices MUST be
mapped into unique locations , and no other off- board
devices may respond to addresses intended for any
on-board memory device.
The 745287 PROM's are field - programmable, fusible-link devices . The PROM ' s are
delivered in a state of all binary ONE ' s . By blowing a fuse link during programming, n
ZERO is programmed . Once a bit is programmed as ZERO, there is no way to restore the
bit to a ONE. Be careful to program the device completelyj partially programmed
devices have been known to have random bits revert back to the O~E state because the
fuse link was not blown completely .
MSB and LSB conventions are those used by the 990 - family systems hardware and software
for PROM and EPROM programming.
6.9.2 CRU SELECT
The CRU I/0 decoding is done by a gate array and a 74LS138 decoder as shown in Figure
6- 9. Address lines A3 through A9 are decoded, providing eight on-board select lines ,
each line addressing a block of 32 CRU bits. These select lines, ISELO through ISEL7,
go to the various on- board CRO devices, with the exception of the ISEL3 line which is
reserved for future use. The INTCRU/EXTCRU line is defined by the upper four address
bits (A3 -A6 ) and MEMEN ; the line activates the 74LS138 decoder and deactivates the
74LS241 buffer with CRUIN.B and CRUOUT.B when an on- board CRU address is asserted. At
all other times the buffer is enabled, and the on- board decoder is disabled, allowing
some off-board CRU device to respond. Because of this manner of decoding, overlapping
CRU addresses off-board will be ignored if they are mapped into on - board CRU space.
On - board CRU address space thus is reserved; and because there is no PROM, the CRU
address map cannot be changed.

6- 19

ME MEN
A3

3

A4

2

A5

8

AG

9
74LS02

INT CRU1EXTCRU

U52

6
4

--

5
A7

3

AB

2

A9

G1

'( 1

G2A

Y2

G2B

Y3

c

v4

B

YS

A
~

/ 4L S 138

15

ISELO

14

ISEL 1

13

ISEL2

12

tSEL3

11

ISEL4

10

ISEL5

9

ISEL6
ISEL?

7

J 8 D[CODER

SIGNAL

ENAl:lll:S

ISELO
ISELI
ISE L2

l l: D C11uJ1t
DIP Sw11ch
Md1n fMS 9902 11'21

ISEL3

Nol

ISEL4
ISEL5
ISELG
ISEL 7

TMS 990 1
RESE r E

v

A 44
4 7K

-Jvl

I 26

'

.......--...

<)

1 ~·

I)

t ?8

E27

E:11

1:-29

l~OMI ·

-A5

'22

A6

13

A7

1

AS

2

M

J

A lO

4

A ll

5

A 12

6

A9

1

Al4

8

2:>

A6

23

DO

A/

1

1/

16

DI

All

2

16

U9

IS

02

All

3

15

D IU

14

03

Aln

4

14

0 11

lJ

04

A11

!>

13

[J 1'2

11

11

08

A6

AS

07
U44

A4

A 13

A!1

18
A8
Al

06
05

AJ

04

A"1

OJ

Al

18

U4 :1

05

A1 7

G

11

OIJ

06

., 13

7

10

0 14

9

DI

A1 4

8

9

Il l !>

01

TMS 7708 12716

rMS ?.708 '2 116

c

)

E::J2

EJI

,,,..--...

,,.,--...
(

c

E33

lJ4

>

R45

oJ!>l

A4

4 , ....
A

-::"

A5

?2

:?O

Ao

A6

23

18

A6

A7
AS

2

A!!
V dr1

16

01

"'
AB

2

1!>

02

1\9

3

14

4

~·

03

~

13

04

Al I

A12

6

11

O!>

A17

10

l.J6

AIJ

9

U7

~

AH
A 14

8

"

14

18

U 43

c;

8

TMS 27(18 ' 7716

Figure 6-11.

20

23

00

A11

TMS 2 108/71 16

Read-On ly Memory
6- 28

A

VVY

HOM2

17

AIU

A 10

OR

10

02

AD

-:w

20

17

DB

16

09

15

010

14

011

l:J

012

11

OIJ

10

1•1 4

9

Olo

"
AS

1S

AS

1S

A7

17

AS

1

A9

1/0 4

AS

1/03

A7

2

AlO

3

All

4

A12

7

A13

6

A14

s

AS

DO

AS

15

11

OS

AS

1S

12

na

12

01

13

02

A7

17

13

010

14

03

A8

1

14

011

1/02

A6
A9

11

1/01

.

U36

A4
A3
A2
Al

cs

8

AO

WE

10
.__

A9

2

A10

3

A 11

4

A12

7

A13

6

8

A14

s

- 10

TMS 404S

WE·

U34

TMS 404S

RAM2·

AS

15

11

04

AS

15

A6

16

12

05

AS

16

12

013

17

13

01 4

14

01S,

A7

17

13

06

A7

A8

1

14

07,

A8

1

A9

2

A10

3

A9

2

A10

3

A11

U30

4

A 11

4

A12

7

A12

7

A13

s

A14

5

11

U28

8

A13

6

s

10

A14

5

10

TMS 4045

TMS 4045

Figure 6-1 2.

Random Access Memory

6- 29

012

6.13.1 ADDRESS AND DATA BUFFERS
The address buffers consist of two 74LS245 octal
bus transceivers. The address lines
normally flow off-board. Upon a HOLDA signal, the direction reverses, allowing a OMA
controller to input an address onto the board for disposition by the address decoder
section. Address and data buffers are shown on sheet 3 of the schematics (Appendix F,
page F-3).
The same devices are used as the data bus buffers. Direction data flow, however, is
governed by the 74LS153 decoder using the states of ONBDMEM and HOLDA (listed in Table
6-8 ) .

Table 6-8.

BOLDA
Low
Low
High
High

ONBDMEN
Low
High

Low
High

Data Buffers
Data Flow
(READ)
(WRITE)

Bus Command
OBIN
Low
High
DBIN

On-board
Off-board
On-board
Off- board

Off- board
Off-board
On-board
On-board

Operation
Normal off-board
Normal on-board
DMA off-board
DMA on-board

Note that during normal off-board operation, the direction is as expected. During
normal on-board operation, the direction of data flow is always off-board so that
off- board data will not interfere with the on-board operation. This also permits an
external logic system to monitor on-board activities for debugging purposes. For
example, illegal op codes can be caught by monitoring the data bus during IAQ time .
Followin~ the same logic, data flow is always on-board during an off-board DMA
operation so that no interference occurs . Finally, on- board DMA requires that the
buffers be in a state opposite that normally expected since the controller is
off-board.
6 .13.2 CONTROL BUFFERS
Three types of enabling are used on control line buffers: HOLDA, CRU, and always
enabled. The lines that are always enabled are those whose source .is always on- board,
such as the clocks, IAQ, IORST, CRUCLK, and HOLDA.
The
the
are
and

second type, the CRU signals, are governed by the INTCRU/EXTCRU signal derived by
CRU address decoder (see paragraph 6.9.2). Normally enabled, CRUIN.B and CRUOOT.B
disabled for on-board operation to prevent possible interference during address
CRU data stabilization.

The third type of control buffer is the _!ype directly affected by CPU or DMA
operations: the memory contr ol signals MEMEN, WE, and OBIN. Normally enabled flo wing
off-board, these lines reverse direction when flowing on- board for DMA operations so
that the OMA controller can command on- board memory. These lines are keyed on the
state of HOLDA.

6-30

6.13.4 HOLD, HOLDA, and OMA
When an off- board direct memory access controller (DMAC) wishes to initiate operation,
it asserts a low state onto the HOLD line. After finishing the current memory cycle ,
the microprocessor responds by floating its address, data, MEMEN, DBIN, and WE lines,
and then forces HOLDA (HOLD acknowledge) high.
The DMAC is now free to use the system buses to transfer data directly in and out of
memory as it wishes. For a more detailed discussion of DMA operations, refer to
Section 8 of the manual, Applications.

6 . 14 INTERRUPT STRUCTURE
The TM 990/101M provides total of 17 in terrupts. The characteristics of each are
listed in Table 6-9.

Table 6-9 .

Interrupt Characteristics

Interrupt

Types

RESET

Dedicated

No

Yes

1-5

Dedicated

Yes

Yes

6

Dedicated

Yes

Yes

7-15

Shared 1/0

Yes

Yes

LOAD

Dedicated

No

No

Prioritized

Maskable

Characteristics
INT 0, resets I/O,
TMS 9900 mask
Level triggered, all
defined*
Level or edgetriggered*
Level- triggered,
undefined
Level triggered, will
always occur unless
locked out by a RESET

*Definitions in Table 6-10

Table6-10.

Dedicated Interrupt Description

Interrupt
Level
1
2

3
4

5
6

Purpose
Power ~ail interrupt, brought out on OEM chassis
Reserved for future use
System timer: TMS 9901
Main I/O port: TMS 9902
Auxiliary I/O port: TMS 9902/03
External device - edge (positive or negative) triggered or level
sensitive.

6-31

All interrupts except RESET and LOAD are processed by the TMS 9901 Programmable
Systems Interface device. This device handles both parallel I/O and interrupt
requests . Because of the pinout limitation on the package, the TMS 9901 must share
INT7 through INT15 (interrupt requests 7 through 15) with the parallel I/O lines P15
through P7, respectively. This reverse arrangement provides contiguous I/O and
interrupt lines if some of the shared lines are used for interrupts and others for I/O
(see Figure 6-13).
The basic operation of the interrupt facility must be initialized by the
microprocessor through the CRU. The 15-bit interrupt mask is set under program control
to allow interrupt requests by writing a ONE state into those mask register positions.
The mask bits that contain ZERO will not honor interrupt requests. Note that the
condition of the processor's Status Register priority mask is irrelevant if the TMS
9901's Interrupt Mask Register is a ZERO for a particular interrupt: the request will
not even be presented to the processor.
When one or more interrupt requests are presented on the INT1 to INT15 lines, only
those whose corresponding mask bits are ONE are considered. The highest priority
request present is encoded onto lines ICO through IC3 , and INTREQ becomes active
(low).
The TMS 9900 receives the coded request and compares its value to the interrupt mask
in its status register. If equal or higher priority, (a lower interrupt number) the
interrupt is honored, the mask is set to one less than the current interrupt number,
and the vector process begins. Note that level 0 is the highest priority, and cannot
be masked out since it is a number that is always equal to or lower than any number
which can be in the mask register of the processor . The lowest priority is 15 .
There is extra logic for INT6 to be triggered either in the normal manner by
presenting a low level to Pl pin 20, or in an edge- triggered manner. A low-to-high
transition should be presented to P4-8, and a high-to-low transition on P4-6. These
edge-triggered signals are converted to level-sensitive signals, and are latched by a
pair of flip-flops. The interrupt request line can be set inactive by the interruptservice routine by writing a bit, either a ONE or a ZERO, to CRU bit address OOA6
(R12 base address 014C15). These flip-flops are automatically cleared by the CLRCRU
signal.
6.15 PARALLEL I/O AND SYSTEM TIMER
The TMS 9901 provides sixteen lines of parallel I/O . The TM 990/101M user can read or
write to any single bit of this parallel port because it is under CRU control. For
example, eight bits can be used for output at the same time the eight other bits are
used for input. This allows applications such as scanning a custom keyboard for input,
or outputting multiplexed signals to a seven-segment display device; all under program
control. A timer is also integrated into this device .

6-32

• 5V
I

,>
,>
~

iNi'RE'O

11

ICO

15

IC1

14

IC2

13

I C3

12

I OR Sf

1

J

10

CRUI N

4

CRUOUT

2

)

>

TMS9901

iNr'REQ
ICO

INTI
INTZ

IC1

INT3

IC2

INT4

. .> ;. >

~

'>

(.

:>All 10 k n

17

INTI

18

INTZ

9

INT3

8

iNT4
INT5
INT6

re

P1 · 16

El
Pl 18
E2
E3

-----:25

P1-13
Pl-15

~~

011-

Nf-

~a:

a>ON
(/)C..c..

:Eu.
f-0

Pl -18

ICJ

l"NTs

7

RSTI

INT6

6

( : E4
E5

t

-

s

AlO

39

All

36

A12

35

AlJ

25

A14

24

•SV

CRU IN

iNTs1P14

CRUOUT

INT9/ P13

32

e RUeLK

i"Nf'1iilP12

l-

l

cr

!NT11/P11

'iC

INT12/P10

"1

52

INT13/P9
INT14/P9

S3

INT15/P7

S4

Pti

Vee

P5

40
16

I
34

33

CRUCLKG 3
I SEL4·

INT7/P15

GNO

P4
PJ
P2
Pl
PO

-

31

T

JO

T

29

T
'28

1
27

T
23

1
19

P1 ·7
P4-34
P1 -10
P4-32
P1 ·9
P4-30
Pl 12

1'4· 28
P1 -11
P4-26
Pl- 14
p4.24
P4-12

20
P4-10
21
P4-18
22

P4-16

26

P4-14

37

P4-22

38
,>

,

.>
> '>

..

P4-20

: : .> >>

A0001 4 SO

•5V

Figure 6-1 3.

6-33

TMS 9901

.

)r

.

,>

> '>

··~ff"
z

Pl -6
P4-40
P1 ·5
P4-38
P1-8
p4.36

> ALL 10kn

0

a:

:Eo 8lo...,

011- (/)c..c..
a:z
:E ...
u._ fo-0

-

EDGE TRIGGER
LOGIC

P1 ·20_ _ J
P4-6

P4-8

r

J

6.15.1 PARALLEL I/O
Lines PO through P6 are dedicated I/0 lines , wh ile P7 through P15 are shared with
INT15 through INT7, respectively. When a user system is configured, it must be decided
how to allocate these shared lines between interrupts and I/O. When written to, each
parallel line remains in the same state until written to again. The parallel 1/0 lines
are initialized by resetting the 9901. This may be done in 3 ways; by
(1)

Activating the RESET switch or pulling PRESET.B to 0

(2)

executing a RSET inst ruction

(3)

Putting the TMS 9901 in the clock mode and then writing a 0 to CRU bit 15
(refer to Table 1, TMS 9901 manual). Instructions to accomplish this for the
TMS 9901 on the /101M CPU board are :
LI
SBO
SBZ

R12 , >100
0

15

After initialization of the 9901, all I/O lines are in the input mode, and aJl I/O
lines are pulled high. Writing to a specific CRU bit programs that bit as an output ,
and that bit will remain an output until the TMS 9901 is initialized again.
6.15.2
SYSTEM TIMER
The TMS 9901 has an internal real time clock which may be used as an interval timer by
the user. It is a decrementer which generates an interrup t when it decrements to 0 . To
load a value into the 9901 clock register on the 101 board, the user must:
(1)

put the 9901 in the clock mode by writing a 1 to the control bit (CRU bit O)

(2)

load a 14-bit count value into the counter register (CRU bits 1 through 14)

The counter will start decrementing the counter register value immediately after it is
loaded at a rate of 0/64. For a 101 running at 3 MHz, this computes to a decrement
every 2 1. 33 microseconds (rounded off). Writing all ones to the counter register gives
the maximum time interval of 349.525 milliseconds (rounded off value). An example of
loading and starting the timer is:

LI

R12, >100

LDCR

R1, 15

Rl contains the 14-bit timer value, plus a one in the least significant bit pos1tion.
This least significant one gets loaded first and puts the TMS 9901 in the clock mode.
If the least significant bit is a O, the user will be loading the TMS 9901 interrupt
mask register instead of the counter register. Refer to the TMS 9901 manual for more
details.
When the TMS 9901 timer decrements to 0, a. level 3 ( INT3) interrupt is generated. For
this interrupt to cause a context switch , the 990 1 must be in the interrupt mode (CRU
bit 0 = 0), the INT3 mask bit must be 1 (CRU bit 3 = 1), and the TMS 9900 interrupt
mask must be set to accept a level 3 or higher priority interrupt (LIMI 3). Cnde to do
this would look like the following:

6-34

LI
SBZ
SBO
LIMI

R12,>100
0
3
3

SET CRU BASE ADDRESS OF 9901 ON 101
PUT 9901 INTO INTERRUPT MODE
ENABLE INT3
SET 9900 INTERRUPT MASK FOR LEVEL 3
OR HIGHER PRIORITY INTERRUPT.

After the interrupt has occurred and a context switch has taken place, the user should
disable the timer interrupt at the 9901 by writing a 0 to CRU bit 3. This will prevent
INT3 from occurring during the Interrupt Service Routine and possibly cause an
infinite loop to the Interrupt Service Routine. Several items of interest regarding
the 9901 timer are

•

••

(1)

after decrementing to O, the timer reloads itself with the start value and
starts decrementing again

(2)

when the 9901 timer is being utilized, it generates INT3. Any signals on the
INT3 pin (pin 9) of the 9901 are ignored.

(3)

if the timer is used for measuring elapsed time or as an event counter, the
contents of the counter register must be read. To do this, the 9901 must be
put in the interrupt mode (CRU bit 0 = 0) for at least 21 .33 microseconds,
then placed back in the clock mode (CRU bit 0 = 1) and CRU bits 1- 14 are
read.

(4)

to stop the timer, the 9901 must be put in the clock mode and the counter
register (CRU bits 1- 14) must be loaded with zeroes.

6 . 16 MAIN COMMUNICATIONS PORT
The main communications serial I/O port (P2) has two options, depending on the "dash
number" ordered by the customer. (Refer to paragraph 1.3, "Product Index, " to
determine whether the Teletype (TTY) or multidrop (MD) interface circuitry is included
on this serial port.) The main I/O port uses the TMS 9902 Asynchronous Communications
Controller and is intended for operation with either the "console device" or ma s ter
terminal for the TM 990/101M user, or with an automated control device using the
multidrop interface. For detailed operation instructions for the TMS 9902, refer to
the data manual for this device. When pin E2 is connected via jumper to pin E3, the
INT pin of U46 is connected to the INT4 pin of the TMS 9901. The TMS 9902 will
generate an interrupt on 4 separate conditions, and so if the 9902 at P2 does generate
an interrupt, it will appear as INT4.
6.16.1 EIA INTERFACE
The EIA interface consists of 75188 line drivers and 75189A line receivers. The
receive-data line goes to P3-2 and the transmit-data line to P3-3. This configuration
forms a port suitable for connection to an RS-232-C compatible terminal. A dataterminal-ready (DTR) signal is supplied as an input for handshaking use with a device
requiring it. Request-to-send RTS) and clear-to-send (CTS) signals are tied together
and brought out to P2-8, which functions as the data-carrier-detect (DCD) signal to
the terminal.

6-35

A 14

10

A13

11

A 12

1?

All

13

A ID

14

CRUCLKG

15

CRUOUT

8

CRUIN

4

93

16

ISEL2

17

•5V

TO I NT4 0N 9901

INT

S4
S3

XOUT

S2

HTS

S1

CT S

so

DSR

CRUCLK

R IN

2

XOUT

5

RTS

TTY OUTPUT

6

• EIA ( •bVI

7
3
LOCOCO

P2 8

CRUOUT
CRUIN

¢

LOCO TR

CE

E38

18

P2 20

MU L T I DROP R ECE IVER INP UT

Vee
9

-

GND
TMS 9 902

Figure 6-14.

E39

(

EI A & TTY I N PU T
E40

Serial I/O Port EIA Interface

6.16.2 TTY INTERFACE
A t r ansistor and 560-ohm resistor form the transmit loop for the 20-rnA current loop,
TTY interface. The transistor conducts current while the line driver connected t o its
base is at a mark state. As the line driver goes to the space state , the posi tive
voltage output is clamped to ground through the signal diode on the transistor base,
thereby turning off the transistor and the current loop (refer to Figure 6-1 5).
The receive circuit consists of a line receiver whi ch monitors the receive loop formed
by the TTY transmit circuitry and the tw o s up ply resistors. The values of these
resistors is such that during a mark state, th e input to the l i ne receiver is held
very close to - 12 volts. When the TTY transmit circuitry cuts the loop, the rece iver
input is pulled up to +1 2 by the 2 . 7 kohm resistor .
Note th at the TTY jumper must be in place so that the line receiver can monitor the
l oop voltage . An EIA terminal shoul d not be connected when the TTY jumper is in place.

6-36

12

~

,J

.,

TTY RCV RTN

.,

P2 23

tl2 v

RIN
E39

v

LOCRCD

E37

E40

0

t36

I

TTY RCV

.

P2 18

I .' V

xour

Tl'r' XMl fHN

TTY XMT
TMS 9902
•5

v

P2 25

)N:/90!JA
1N91 4B

Figure 6-15.

Serial I/O Port TTY Interface

6-16.3 MULTIDROP INTERFACE
The multidrop interface (Figure 6-16) may be used for board- to- board communications
over long distances. Generally, on ly a twisted pair line is required between the
boards. One pair is necessary for transmitting, and another pair for receiving when in
full duplex mode. Connecting the two half-duplex jumpers will loop the transmitter
back to the receiver for test or half-duplex applications and only one pair is then
required.
More than two boards may be linked together, each one is just "dropped" in place,
hence the term multidrop. If more than two boards are used, the boards not at the
extreme ends of the twisted pair line (i.e., those "dropped in the middle") are
considered nonterminating boards, and the termination resistor jumper plugs should be
removed to prevent standing wave patterns which might occur, mostly at the higher baud
rates. The two boards at the extremes of the line, regardless of whether additional
boards exist in between, should have these resistor jumper plugs installed. Refer to
Section 7, Options, for jumper configuration information.

6-37

~IU l

TIDH OP
RH.EIVEH
INPU T

/blO/
I NPU$11

IA

I\

INPUI l

lh

·~

'"

r1 y

~

11\jP llT

V1 <.

-=-

5

V<.;C

-=-

·~

·A

-=-

l1f\/l.J

HIN

' '•V ~

P/ .'3

EbO,.---.,.. E49
f 4/

-=sv ~
E52 ..---...

E48 (

E51
I 43

-=,,, 11.'

xour
2~

11 rs

2(.

i IS

-

P~

~

r"}

i!J

P~1

74

I ll

I 44
uurPUI I

n

OU TPUSH

'Y

VL<" •

rMS 9907

D

w
!J

V( I

IC

I/

i ;NtJ

I'

-

-:-

Fie;ure 6-1 6 .

rffl":"
·~

v

" \

Multi droE Interface

The multidrop system, also called t he Eri vate wire inter face , uses a dual set, twisted
pair wiring, with operation of t hese lines i n an unbal anced , di fferential mode . As
such, it is a differential line driver/receiver pair which offers higher current drive
capability and the noise-free advantages of a balanced line .
6 . 17 AUXILIARY COMMUNICATIONS PORT
The auxiliary RS-232-C compatible port logic is shown in sheet 6 of the Schematics
(Appendix F). All signals for RS-232-C operation are provided. Both terminal and modem
communication can be used by proper programming and cable assemblies. Devices such as
terminals, modems, and serial line printers, such as the TI 810, all can be attached
to this port. Using a TMS 9902, communications are asynchronous. By substituting a TMS
9903 Synchronous Communications Controller, for example, 1200-baud synchronous modems
can be used.
This port uses a modified EIA-standard co n fig u ration for direct use with
RS-232-C-compatible terminal s. Signals required by modems are brought out to spare pin
positions, which are then rearranged in the special modem cable, the TM 990/506 cable
assembly, to the positions required by the modem .

6-38

•

All TMS 9902/9903 signa ls are brought out to line drivers or receivers. Port. P3 may be
configured as either a modem or EIA type interface in the following manner :

•

(1)

If E54 and E55 are jumpered together (terminal position), the RTS and CTS
signals from the TMS 9902/9903 are tied together to form DCD (Data Carrier
Detect). The DCD signal is brought out to P3- 8. In this configuration, the
P3 port appears as a modem to the terminal device. If the user wishes to
send characters to a terminal device through the P3 port, he must first make
the RTS signal to the terminal go low. This is done by writing a 1 to CRU
bit 16 of the 9902. By making RTS go to O, the user is also pulling CTS to
O, whit~ is the same as asserting DCD. DCD will then be available for
terminal5 requiring that signal for communications.

(2)

If E55 and E56 are jumpered together (modem position), RTS and CTS are
distinct signals, both of which are brought out to P3. In this
configuration, the P3 port looks like a terminal to the modem connected to
P3.

•
"

Provisions are made also for Data-Terminal-Ready (P3-21) and Data-Set-Ready (P3-1 9)
and Ring Indicator (P3- 22) . These three signals are CRU-addressable, outside the range
of the TMS 9902/03. DTR is a latched output and the other two are inputs. Use of all
signals provided can result in a completely automated communications system. Section
8, App lications, describes se veral examples for the use of this port, and gives the
modem cable configuration as well.
The TMS 9902/9903 at Port P3 can be configured to generate an interrupt at the TMS
9901 by connecting E5 to E6 with the INT5 jumper. If the TMS 9902 is configured in
this manner and does generate an interrupt, the interrupt will appear at the TMS 9901
as INT5. Refer to the TMS 9902 or 9903 data manuals for proper interrupt-causing
conditions.

•

6.18 UNIT ID SWITCH
The ID s witch is a set of five SPST switches mounted in a DIP packing and connected to
a 74LS251 CRU device. Each switch position corresponds to one CRU bit and, in the open
or OFF position, represents a logic ONE state. Closing a switch to ground produces a
logic ZERO state. Five switches can be set to provide 32 unique codes.

•
r

..

.

The DIP switch has many applications. Used to pass information to a program, it can
function as a "programmer's front panel". Automatic communications sys terns may have
the same software in EPROM for every board in the system: the polling ID for each
board is set uniquely in the DIP switch. Alternately, it can be used to pass baud rate
and device type information about the auxiliary port to the service programs. The us es
for fixing system configuration in the switch, and having one set of standard
software, is limited only by the imagination.
6 .19 STATUS INDICATOR
The status indicator is a CRU-addressable light emitting diode (LED). Writing a ZERO
to CRU address 000016 causes the LED to light; wr iting a ONE, turns off the LED.
Uses for this feature are again limited only by the imagination. Initialization
software can turn it off once initialization is complete. A system error can cause the
LED to come on. Test software can blink the LED during execution.
The CLRCRU signal turns the LED ON upon power-up.

6-39

SECTION 7
OPTIONS
7. 1 GENERAL
This section explains the various options available to the user of the TM 990/101M.
These options include:
e

Use of TMS 2716 EPROM's (2K x 8 bits each) instead of TMS 2708 EPROM's (1K
x 8 bits each)

•

On-board expansion of EPROM and RAM

•

Asynchronous serial interrupt from one or both of the TMS 9902's

•

RS - 232 - C/TTY/Multidrop interfaces with the Local Serial Port

•

Use of slow access time EPROM's by insertion of one WAIT state.

•

Use of TM 990/30 1 Microterminal

•

External switch actuation of a RESET or RESTART signal

•

Power-up RESET or LOAD

•

Memory Map change by reprogramming of the PROM

e

Line-by-Line Assembler in EPROM.

Figures 7-1 and 7-2 show board locations applicable to this section. Table 7-1 is a
summary of jumpers and capacitors used with these options.
7.2

ON-BOARD MEMORY EXPANSION

7. 2 .1 EPROM EXPANSION
EPROM memory can be expanded on-board in two ways.
•

Add two more TMS 2708 EPROM chips ( 1K x 8 bits each) , for a total of four,
to provide an additional 1K words of memory.

•

Use two or four TMS 27 16 EPROM chips (2K x 8 bits each) to provide 2K or 4K
words of memory.

Figure 7-3 shows placement of EPROM chips and corresponding memory addresses (in
bytes). The board silkscreen designators identify the necessary jumper placement at
E9/E10/E11, E26-E30, and E31-E35.
NOTE
Check the jumper placements on your board against Table
7-2 for proper configuration of your board.
In general, for TMS 2708 use, jumpers are placed as shown in line 1 of Table 7-2; for
TMS 2716, they are placed as shown in line 2. These jumpers switch the chip enable and
A4 signals as required for the memory device used. Location of RAM and EPROM in
opposite ends of memory can be reversed by jumpering E16 to E15 (instead of E16-E17);
this starts RAM at M.A. 0000 15 and EPROM starts in upper memory. In addition, EPROM
7-1

E15i E16
RAM IN LOW
MEMORY
EPROM IN HIGH

E7/E8
ONE WAIT
STATE FOR
ON -BOARD
EPROM

E8/ E53
NO WAIT
STATE FOR
ON-BOARD
EPROM ·

E13 / E14
SELECTS
ON-BOARD
EPROM·

E54/ E55
SELECT PORT p3
FOR USE WI TH
A TERMINAL •

E20/ E21. E22/E23; E24/ E25
POWER TO TM 990,'301
MICROTERMINAL ••

E55/ E56
SELECT PIN P3 FOR
USE WITH A MODEM

I
.

.. •E 4 3/ E44
MULTI DROP
INTERFACE

E12/E13
DESELECTS
ON-BOARD
EPROM

HALF DUPLEX
SE LECTORS
E47/ E48

"%]

I-'·
)q

CONNECTS
MULTI DROP
INTERFACE
TO TM S 9902
E38i E 39

c:
'1

(1)

-.:i
I

.-..J

I
N

E9/E10
SELECTS
2716 MODE
ADDRESS MAP

ENABLES
TTY INTER ·
FACE
E36.'E37

~

c:

8

'O
(1)

'"l

SELECTS
2708 MOD E
ADDRESS MAP•
E1o : E11

'"'d

......
Ill
Q

CD

8

CD
::i
cT

U43, U45
ARE
TMS 2708

U 43, U45 ARE
TMS 2716
E31 / E32
E 33 ' E34

CONNECTS INT 5 TO P1 .17•
E4/ E5
CONNECTS
INT4TOP1 - 1B •
E1 / E2

NOTES ·

CONNECTS INT4 TD
MAIN TMS 9902
E21E3

"THIS POSITION IS THE NORMAL POSITION ON ALL BO AR DS
.. NORMAL POSITION FOR -1 AND -3 BOARDS ALSO •
... NORMAL POS ITION FOR -2 BOARDS ALSO .

'II

E39/E4o•
CONNECTS
EIA AND TTY
INTERFACE
TO TMS 9902

"'

lL
lL

lL
lL

u.

u.

D

"',...D
N

0

ID
D

"'
D

0

,..."' IN

"'

"'

u.
u.
,...

0
D
D

D

co
0
.....
N

I-

"'

0

0
0

u.

Figure 7-2.

Memory and Capacitor Placement

7-3

u.

D

"'~ I"' "'

0

~o

I-

D
D
0
0

0

"'

lL
lL

D
D
D
D

Table 7-1.
No.
Pins Staked

Master Jumper Table

Pins Connected
Together

Function When Connected

E1-E2

Connects INT 4 to pin 18 of P1 edge connector

E2-E3

Connects INT4 to TMS 9902 of LOCAL I/O port

E4-E5

Connects INT5 to pin 17 of P1 edge connector

E5-E6

Connects INT5 to TMS 9902 of REMOTE I/O port

E7-E8

Causes 1 WAIT state when on-board EPROM is
accessed

E8-E53

Causes no WAIT state: memory cycles are full
speed

E9-E10

Selects memory map for TMS 2716 EPROM's

E10-E11

Selects memory map for TMS 2708 EPROM's

E12-E13

On-board EPROM is disabled from memory map

E13-E14

On-board EPROM is enabled into memory map

E15-E16

EPROM at high addresses, RAM in low

E16-E17

EPROM at low addresses, RAM in high

2

E18-E19

Pin 1 of P3 is connected to GROUND

2

E20-E21

Microterminal: +5 volts to P2-14

2

E22-E23

Microterminal power: +12 volts to P2-12

2

E24-E25

Microterminal power: -12 volts to P2-13

5

E27-E28; E29-E30

Main EPROM is TMS 2708

E26-E27; E28-E29

Main EPROM is TMS 2716

E32-E33 ;_ E34-E35

Expansion EPROM is TMS 2708

E31-E32; E33-E34

Expansion EPROM is TMS 2716

2•

E36-E37

Teletype ·terminal connected to P2

3

E38-E39

Multidrop Interface in use with LOCAL I/O port

E39-E40

EIA or TTY interface in use with LOCAL I/O
port

3

3

3

3

3

3

5

7-4

Table 7-1.
No.
Pins Staked

Pins Connected
Together

2 each**

E41-E42,E45-E46
E49-E50,E51-E52

Multidrop termination resistors connected

2 each**

E43-E44, E47-E48

Multidrop Half Duplex operation enabled

E54-E55

Connects TMS 9902 RTS to CTS for port P3 to
communicate with an EIA compatible terminal.

E55-E56

Connects TMS 9902 CTS to port P3 directly for
communication with an EIA modem.

3

•

Master Jumper Table (Concluded)

Function When Connected

*On TM 990/101M-1 and -3 only
**On TM 990/101M-2 only

Table 7-2.
Board
Dash No.

Jumper Pins by Board Dash Number (Factory Installation)
Jumper Installation at
Factory (Positions)

Positions Staked

-1' - 3

E1-E40, E53-E56

E1-E2
E4-E5 E10-E11 E13-E14
E16-E17 E18-E19 E20-E21 E22-E23
E24-E25 E27-E28 E29-E30 E32-E33
E34-E35 E39-E40 E8-E53 E54-E55

-2

E1-E35, E38-E56

E1-E2
E4-E5 E10-E11 E13-E14
E16-E17 E18-E19 E27-E28 E29-E30
E32-E33 E34-E35 E39-E40 E41-E42
E43-E44 E45-E46 E47-E48 E49-E50
E51-E52 E8-E53 E54-E55

7-5

can be disabled from the memory map {in effect, it no longer exists) using jumper
E12-E13 (jumper placement E13-E14 enables it onto the memory map).
7.2.2 RAM EXPANSION
Four additional TMS 4045-2 RAM chips can be added as shown in Figure 7-3. This will
provide an additional 1K words of RAM. Location of RAM and EPROM at opposite ends of
memory can be reversed by jumpering E16 to E15 {instead of E16-E17); this will place
RAM starting at M.A. 0000 16 and EPROM starting in upper memory.

M.A.
(HEXI

M.A.
(HEXI

JUMPERS

0000
2 TMS2708'S
(1K XS EACH)

E10/E11
E13/E14
E27/E28
E29/E30

BANK2
2TMS2708'S
(1K X 8 EACH)

E10/E11
E13/E14
E32/E33
E341E36

BANK 1
U42,U44

0800
U43, U45

JUMPERS

0000
I

BANK 1
2 TMS2716'S
(2K X 8 EACH)
U42, U44

E9/E10
E26/E27
E28/E29

(EXPANSION)

Of FE
1000

BANK2
2 TMS2716'S
(2K X 8 EACH)
U43,U45

E9/E10
E31/E32
E33/E34

(EXPANSION)

1FFE ...__ _ _ _ ___.

(A) EPROM EXPANSION

M.A.
(HEXI

FOOO
U28, U30, U34, U36

BANK2
(EXPANSION)

F800
U29, U31, U35, U37

BANK 1
FFEE-._ _ _ _ ___.

TMS4045
(EACH 1K X 4 WITH
. 4 IN EACH BANK. TOTAL
EXPANSION TO 2K X 16
BITS)

I

(Bl RAM EXPANSION

Fi gure 7-3 .

Memory Expansion Maps

7-6

7.3 SLOW EPROM
Slow EPROM's can be used with the TM 990/101M by using a jumper between pins E7 and
E8. This connects WAIT to READY when on-board EPROM is addressed. Refer to Table 7-3.

Table 7-3.
System Speed
3
3
3
3

MHz
MHz
MHz
MHz

EPROM Type
TMS
TMS
TMS
TMS

2708
2708
2716
2716

Slow EPROM Table

Access Time
450
650
450
650

Jumper E7-E8

ns
ns
ns
ns

E8-E53
Installed

Installed
Installed
Installed

7.4 SERIAL COMMUNICATION INTERRUPT
Either or both serial ports (TMS 9902's) can be interrupt driven.
•

Main Communications Port (EIA/TTY/MD) at P2: interrupt 4.

•

Auxiliary Communications Port (EIA) at P3: interrupt 5 .

As shown in Figure 7-4, any of four conditions at either TMS 9902 can cause an
interrupt condition (change in data set mode, character received, character
transmitted, or TMS 9902 timer counted down to zero). An interrupt service routine can
check the TMS 9902 bits through the CRU to establish cause of the interrupt, then take
appropriate action. Further information is available in the TMS 9902 Asynchronous
Controller Data Manual.
7.5

RS-232-C/TTY/MULTIDROP INTERFACES (MAIN PORT, P2)

7.5.1 TTY INTERFACE
Appendix A covers cabling for a Teletype Mode l 3320/ 5JE . To use this terminal (20 mA
current loop), connect pins E36 and E37 with a jumper plug .
CAUTION
Verify correct voltage levels at connector P2 before
attaching a teletypewriter type terminal.
r

Connect the cable to the terminal and t o the mi crocomputer board. The EIA/MD jumper
plug must be connected between pins E39 and E40.
7.5.2 RS-232-C INTERFACE
Appendix B covers cabling for an RS-2 32-C compatible terminal. To use this type of
terminal, disconnect the TTY jumper and make sure the EIA/MD jumper is in the EIA
position. Connect the cable to the t erminal and to the microcomputer board.

7-7

INTERRUPT
CAUSING

9902
CRU

CONDITION

fill.

DSCH
DATA SET CHANGE {

DSC INT

DSCENB

RBRL
RECEIVE BUFFER {
LOADED, ENABLED

RBINT

RIENB

XBRE
TRANSMIT BUFFER {
EMPTY

XBINT

XIENB

16

17

TIMELP
TIMER ELAPSED {

TIMENB

TO INT4 OR INT5 AT
E2/E3

A0001459

PIN INSTALLATIONS TO ENABLE INTERRUPTS:
- INTERRUPT 4: E2/E3
- INTERRUPT 5 : E5/E6

Figure 7-4.

Four Interrupt-Causing Conditions At TMS 9902

7.5.3 MULTIDROP INTERFACE
Figure 7-5 shows the multidrop interface in use with a system of TM 990/100-series
microcomputer boards. The two boards at the extreme ends of the lines are considered
"terminating" boards; wh ereas , the boards in the middle a r e non-terminat i ng.
Half-duplex operation requires one twisted-pair line (i.e., two wires), and
full-duplex operation requires two twisted pairs (i.e., four wires). Refer to Figure
7-6 for cabling.
Table 7-4 shows the jumper configurat ion for the various configurations . As an
example, a common system requirement is for a full duplex board-to-board communication
between only two boards. This requirement is fulfilled by the jumper configuration
shown on line 4 of the table.
7.5.3.1 Full Duplex Master-Slave
This communications setup is used when there is only one master station and several
slave stations. The system setup is shown in Figure 7-7. The advantage of this
approach is that one station is in command and control of communication is thus
centralized, and also each master-slave communication is full duplex. The half duplex
jumpers are removed .

7-8

'

TWISTED
PAIR
CAB LING
(SEE FIGURE 7-6)

TERMINATING
BOARDS

Figure 7-5.

Multidrop System

'
t

•

P2

P2

OUTPUSH

24

24

OUTPUSH

OUTPULL

25

25

OUTPULL

IN PUSH
INPULL

23
18

23
18

INPUSH
INPULL

NOTE: ALWAYS CONNECT A "PUSH" LINE TO A "PUSH"
LINE AND A " PULL" LINE TO A "PULL" LINE

Figure 7-6.

Multidrop Cabling

7-9

Table 7-4.

Multidrop Jumper Table
Remove

Install

Mode

Half Duplex , non-terminating

E43-E44, E47-E48

E41-E42, E45-E46,
E49-E50, E51-E52

Full Duplex, non-terminating

None

All E41-E52

Half Duplex, terminating

All E41-E52

None

Full Duplex, terminating

E41-E42, E45-E46,
E49-E50, E51-E52

E43-E44, E47-E48

All

E38-E39

24
25

24

24

24

25

25

25

23

23

23

23

18

18

18

18

18

MASTER

SLAV El

SLAVE2

SLAVE3

SLAVE"N"

OUT

24
25

0 0 0
23
IN

N

N
I.Cl

' FE OC ~ 14
FE OC
'.,.'• :~: - - --

0460 B

CHANGE MEMORY ADDRESS

- - --

SYNTAX ERROR

~ > 0080

/ FE OC
434F :J;coni::;F:ATULAT I
4E47
5241
5455
4C41
5449
4F4E

CHANGE MEMORY ADDRESS
or·~ ::: .

\ 'DUF: F'F:o1;;F:AM 1•.10F:v ~: ! - - - - --

5 :~: 2E

2059
4F55
5220
5052
4F47
5241
4D20
574F
524B
5 3 21
0707 + >0707
07 00 + > 07 00

Figure 7-9.

Line-By-Line Assembler Output

7-14

-

TEXT sTATEMENT

(

--------··----·
---Figure 7-10.

TM 990/301 Microterminal

7-15

BACKPLANE

0 .40I

1

0
0

J [
5.0

0

)

(

LJ

CJ CJ LJ
CJ [ZJ CJ
~ CJ CJ
!
J c
)

NOTES :
1 . DIMENSIONS IN INCHES
2 . DISTANCE BETWEEN SLOTS
IS 1 INCH
3. ALL DIMENSIONS ± 0 .010.

Figure 7-11.

TM 990/510 OEM Chassis

7-16

."' .

I'.

£

"
1:
~

.. ..

H

..,~

•

~

>

~

I" I"
a kJ la
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Ir.

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)ll

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b

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la lg la

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r.

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~

~

II

I
I 1

i

1

I

I

~j"
eJ,
"

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''<.,.

~

k

"
~

rat

r&1

··R ..·~. . g

......

oB

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-

,----

"'
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x
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-r :~ .~1
•

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iiiii':f lJ

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17¥71 4

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a

_,

t11 t:rN r

NOTE : BACKPLANE PIN ASSIGNMENTS LISTED
IN TABLE H-1 (APPENDIX H).

TERMINAL STRIP
IN BAC I( OF CHASSIS

Figure 7-12.

OEM Chassis Backplane Schematic

7-17

i .... 1
I
~

i:ia.

lL

Jo' J;l

... - I

j' ',

~

I

r .•
>.PP, >

., "" ..

'C

~·

~

,

.,

\

-I

~

I<

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~

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x x

~

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I

I

"

_J__ __ ~:~

0

SECTION 8
APPLICATIONS
8.1 GENERAL
This section covers various methods of com.~unicating to applications hardware external
to the TM 990/101M. Figure 8-1 shows board locations applicable to this section.
8.2 OFF-BOARD RAM
Figure 8-2 shows a logic diagram for adding additional RAM off-board. The buffers are
controlled by the same logic that is used on board the TM 990/101M. The dual
flip-fl o ps are used to generate one wait state whenever the memory is enabled. The
74LS155 decodes the five most significant address lines. The AO and A1 lines select
~his memory board, and A2, A3 and A4 select one of six banks of expansion RAM . The
outputs of the 74LS155 select 1K word banks, starting with the 1Y1 output, whic h
corresponds to an address range of E800 15 to EFFF 15. Lines 1Y2 and 1Y3 are not used
since they respond to the address range of Fooo 16 to FFFF 15, which are on- board the TM
990/101M. Additional 1K word banks connec t to 1YO, and so on up to 2YO, which responds
to the lowest address in this application, C000 15.
Alternatively, if the user wishes to address eight banks of RAM on this memory board,
using 1Y2 and 1Y3, then the on-board memory can be moved to BOOo 16 to BFFF 16 , or some
o th e r addre ss, by reprogramming the Memory Address Decoder PROM on board the TM
991/101M.
7he 74LS08 bringing ¢1B onto the memory board is used to buffer the system bus , in
keeping with the practice that only one LS load per board should appear for a system
bus signal. It may easily be omitted. The two 7438's with pull- up resistors attached
are used instead of a 74LS04 and 74LSOO to keep down the parts count .
8.3 OFF-BOARD TMS 9901
Figure 8-3 shows the wiring of an off-board TMS 9901 at the CRU bit address OFE0 16 .
Only the programmable I/0 section is used; the clock and interrupt section is ignored.
The R12 bit address is 1FC0 15.
Connection is made through the system bus, P1. The CRUIN, CRUOUT, and CRUCLKB signals
are gated by the 1G signal. Chip enable is performed by one 74LS30 . Other addresses
are not so easy to decode; the use of the various decode chips would enable a bank of
TMS 9901's.
8.4 OFF-BOARD EIGHT-BIT I/0 PORT
Figure 8-4 shows the wiring of an I /O port with separate 8-bit inputs and outputs. The
input is a 74LS251 selector, also known as a TIM 9905 . The output is an addressable
latch array, a 74LS259 (or a TIM 9906). Address decoding is done by random logic, and
the R12 CRU address is 0200 16 . Note that MEMEN is not used in actress decoding, so this
circuit is active even during memory cycles . Again this does no harm since CRUCLKB is
inactive and CRUIN is ignored by the processor.

8-1

TMS 9902 FOR MAIN PORT P2
TMS 9902 FOR AUXILIARY PORT P3

'">l

I-'·
()Q

c:

"'3
Cl>
00
I
_..

.

3:
Ill
c......
0
"'3

00
I

I\)

I~
'O

0

::s
Cl>
::s

cT

(/)

c(/)
Cl>

0.
I-'•

::l
H

.......
0

~

~

74LS74

(

READY90 7 4LSOB

,.-_.. ___.. :>--

LSOO

22

·x

POINT
TOALLPIN 10'5 OF TMS 4045's

I

j ~~K L
•S

..----.. J

v

IB - 2
4
OBIN B B2 MEMEN BBQ ~

74LS243

~

HOLDAB

LS02

'D-~>--------~--....,

¢j' B
ol B

? 4 7K
•;w

S

7• 3B

A 74LS1SJ

~
10
7438
9
B

r

Al

}-1S 2C

Y-

B
•S --..-- !CJ
L IC7
l !Cl

TO ADD l
}YO 10
2Yl t -- - - - <.HI P
11
~EL ECTS
1Y2t - - - 7y3,_1_2_ _ _
ON 1K WORD
lYo._7_ __ _ BLO~KS

A0~8

A2

'11c

A3
A4

3 B
13

lYl ._6_ _ _ ____,

5

•v3

•~---------~ A

~.__---..,__. 1co

'----.J

74LS155

01S B

4B

0148
013 B
D 17 B

47
46
45

0 11 B

44

D 10 B
09 B

43
42

DB B

41

- 2
-----2

1B

4

16
lS

-----S

-

6

B
9

- -G

07 B

40

06 B
05 B

39
38

-----2

--2

-

37

36 ~
35 ___}_

01B

__!!
33~

74LS245

A14 0

71

A 13 B

70

A 12 B
All B

69
68

AlO B

67

A9 B

66

ABB

6S

-

-

13

A6

16

12

A/

17

11

AS

16
IS
14

A1 4

A13

18
17

74LS245

AS

16

A6
Al

lS
14

AB

7

13

B

12

A6

lf

A7

17

AS
A9
AlO

j .~
0[ 12
1'

DI

-

8

s-

6

Al2
A13

6

A14

s

08
09

13
010
t1-- --1
4
01 1
t -- - -

T'llS

3

4045

10

W-

A 11

"*"

1S
16
17

·~1_ _ _ ____,,__...

64

A6 B
AS B

63
62

A4 B
AJ B

SO

A2 B

S9-,

13

AlB

SB

12

AO B

57

2

DI

0[ t-:-~--~-:'1

A9

TMS

AlO
Al l

4045 "'

A13
A1 4

14

07

10

'WI:

··~

A12

Al B

6
5

-s - B

lB

-----1
4
5

17
16
15
74 LS2 45

8
9

14

11

-G
19

15

WC

"

-

G

-

TMS
4045

AS

~ 11~-------~

4

----S

O[

DO
01
02
14
03
t -- - - -

12

DIR t---~ 1

61

2
3

DI

11
12
13

All

lS
17

11

3

19

A9
A10
A 12

DIR 1 - --

2

5
6

15

13

34

19

AS

~ ll~------11---1----.

4

04 B

14

OIRl-----..1

2

03 B
02 B
DOB

74LS245

7

19

+5

17

J.

DIR

I~'-----~

Figure 8-2.

Off-Board Memory

8- 3

AS

15

A6
Al

16
17

01D[

AS
A9

T "~S

AlO

40 45 -

A12
AlJ
A1 4

11

6

___

12 01 3
13 01 4
,__
t--1-4----,0- 1'1
§

W-

A ll

LSOO

1v2 ~.----+--1~-}-­

10

_
WE

>
,

74LS367

I
30
87

eRUIN.B

I

3

2

eRUOUT .B

I

4

5

e RUeLK .B

I
I

6

7

IORST.B

10

9

3.e

I

12

11

MEMEN.B

I

14

13

88
24
80

'

'

I

I

I

'
;;:
a:

0
....

I

u

w

z
z

u
~-

8
0

01
62

O>
O>

63

"'~

64

'

65

67
68
69

I

I
I

r
I

71

fI

I

1

Rs T 1

PO

Pl

so

P2

•SV

I

39

GNO

I

36

G ND

I

·-

35

I

A6 .B

I
I
I
I

A7.B
A8.B

AS .B

74LS367

2

3
5

40
.---

7

16

10

9

I

12

11

I
I

14

13

I

iG

I

_}----

2

3

A10.B

I

4

5

A l l.B

I

6

7

A12.B

I

10

9

A13.B

I
I

12

11

iG

S4

P6

Vee

P7

~
,lL_

GNO

PS

2___

P9

d!..__

I

-

2f.

L_

to

~

S 11ol1s

L I ST OF MATERIALS
PART

OTY

4
1

3

14 · PIN DIP SOCKET'
16 · PIN DIP SOCKET'
40 · PIN DIP SOCKET
74LS367
7 4LS04
7 4LS30
Tl\llS 990 1

'AN O 'IYIRE · 'IYRA P PINS A S R EQUI R E D

Fi gure 8-3 .

Circui try To Add TMS 9901 Off-Board

8-4

26
22
......_
21
,_____

P4

13

14

I
I

-

37
......_

PS

74LS367

I

4

38

SJ

~

L

P3

J
I---

S2

74LS30

iG

A9 .B

A14.B

24

6

.LJ

St

25

~

4

I

I

70

11

0

I
I
66

EE

~ eRUeLK eRUIN
10

I

I

ic

eRUOUT

I

A4.B
I

TMS9901
2

+SV

A3.B

I

15

I

I

0

2(;

LS04
1V2

~

PlO

~

Pl 1

.lQ__

P12

J.2_ _

P13

,E.__

P1 4

..ll--

P15

~

(

74LS259

74LS04
CRUCLK B

A12

3

A13

2

A1 4
A3

CRUOUT B

A4

13
14

A5

IORST B

15

c

00

B

01

A

02

D

03

4
5
6
7

04 9
10
05
11
06
12
07

G

CLR

A7
A8
A9

8

16

AlO

lOKn

All

r---------

-

I
I

74LS251

I

A6

A12

9

A13

10

A1 4

11

CRUIN B

5
7

I

4

c

DO

B

Dl

A

D2 2

y

DJ

s

D4

3

15

D5 14
13
D6
12
D7
16

8

-

Figure 8-4.

8-Bit 9905/06 Port

8-5

L

- -,
I
I

- - - - - -

-

I
_J

+5

8.5 EXTRA RS-232-C TERMINAL PORT
Figure 8-5 shows a diagram of a serial I/O port suitable for most RS-232-C terminals .
.The handshaking signals used are DATA CARRIER DETECT, which is generated from the
REQUEST-TO-SEND tied back to CLEAR-TO-SEND on the TMS 9902, and DATA TERMINAL READY,
which is brought into the TMS 9902 for program interrogation. The two 3 .3K resistors
supply a "fake" CLEAR-TO-SEND and DATA-SET-READY to those terminals requiring them.
Since only half of the packages are used on the 75188 and 75189 devices , another TMS
9902 may be added for an additional serial port. The R1 2 CRU address is 1FC016·

f

+-5

CRUCLK .B

CRUOUT.B

8

2

XOUT

15

5

RTS

16

6

CTS

A 10

14

A4

A11

13

AS

A12

12

A 13

11

A1 4

10

A8
A9

INT

4

AJ

A7

3.JK

CRUCLK. B

93 B

74LS30

C:

TMS 9902
CRUIN.B

17

12

+5

7

DSR

3

RIN

cs

A6
18

+5

-

+-5

75188 pin 1 · 12, ptn 7 = GND. pin 14
75 189: pin 7 = GND , pin 14 = +5

Figure 8-5.

9

= + 12

RS-232-C Port

8-6

~----- 3

u------ 8
1---- - - - -

20

2

8.6

DIRECT MEMORY ACCESS (DMA) APPLICATIONS (FIGURES 8-6 AND 8-7)
The microcomputer controls CRU-based I/O transfers between the memory and peripheral
devices. Data must pass through the CPU during these program-driven I/O transfers, and
the CPU may need to be synchronized with the I/O device by interrupts or status-bit
polling .

Some I/O devices, such as disk units, transfer large amounts of data to or from
memory. Program driven I/O can result in relatively large response times, high program
overhead, or complex programming techniques . Consequently, direct memory access (DMA)
is used to permit the I/0 device to transfer data to or from memory without CPU
intervention. DMA can provide faster I/O response time and higher system throughput,
especially for block data transfers. The DMA control circuitry is somewhat more
expensive and complex than the economical CRU I/O circuitry and should therefore be
used only when required.
Microcomputer direct memory access occurs in block and cycle stealing modes, using the
CPU hold capability. The I/O device drives HOLD active (low) when a DMA transfer needs
to occur. At the beginning of the next available non-memory cycle, the CPU enters the
hold state and raises HOLDA to acknowledge the hold request. The maximum latency time
between the hold request and the hold acknowledge is equal to three clock cycles plus
three memory cycles. The minimum latency time is equal to one clock cycle. A 3-MHz
system with no wait cycles has a maximum hold latency of nine clock cycles or 3
microseconds and a minimum hold latency of one clock cycle or 333 nanoseconds.
When HOLDA goes high, the CPU address bus, data bus, DBIN, MEMEN, and WE are held in
the high-impedance state to allow the I/O device to use the memory bus. The I/O device
must then generate the proper address, data, and control signals and the proper timing
to transfer data to or from the memory as shown in Figure 8-6. Thus the DMA device has
control of the memory bus when the CPU enters the hold state (HOLDA= 1), and may
perform memory accesses without intervention by the microprocessor. Because the lines
shown in Figure 8- 6 go into high impedance when HOLDA= 1, the DMA controller must
drive these signals to the proper levels . The I/O device can use the memory bus for
one transfer (cycle- stealing mode) or for multiple transfers (block mode). At the end
of the DMA transfer, the I/O device releases HOLD and normal CPU operation proceerts.
TMS 9900 HOLD and HOLDA timing are shown in Figure 8-7.
8.6.1 DMA SYSTEM TIMING (FIGURE 8-8)
The Direct Memory Access (DMA) process can be divided into three distinct phases
(shown in Figure 8-8):
•

Acquisition of memory control from the system.

•

Memory control by the DMA device, and

•

Release of memory control to the system.

In systems with multiple DMA devices, the memory control phase can be shared by the
devices on a priority basis; however, the acquisi tion and r~lease phases must remain
distinct in that the release phase must end before another acquisition phase beings.
This is necessary to avoid any memory access conflict resulting from the hold
acknowledge signal (HOLDA) delay which occurs when the hold signal (HOLD) is released.

8-7

CRU

A0-A 14

/

0 0 -0 15
'"']

MEMEN

f-'·

)q

c:

OB IN

ct>

WE

"l
CD

I
O'I

CD

I

CD

I~
til

MEMORY

WA IT
RE ADY
MICRO COM PUTER

HcITi5

REQUEST

c:
en

(")

0

:::3

cT

'1
0
,.....

HO LDA

GRANT

IT ~ rr Ii Ii Ii
ADDRESS

DATA

MEM'EN

DBIN

DMA3~TATECONTRO L

DMA CONTROLLER

~

WE

OMA CC

--- ---r
:.:: LU

u....1
....I>-

Ou

-

' - -~(
- -

..

"'
~ I~
0

Figure 8-7.

CPU

z
al

0

>-

0

<(
LU

cc

HOLD and HOLDA Timing

8- 9

ACQUISITION
MIN 1 CLOCK
MAX 9+3W CLOCKS

•I

I•

I

I

91
(FROM CPU I

MEMORY CONTROL
I

I--

MEMORY
READ

I

__L

MEMORY WRITE
(1 WAIT STATE)

I

I

J_

RELEASE
REASSERTING HOLD
DURI NG THIS PERIOD
NOT RECOMME NDED

J
I

I

c3
(FROM CPU!
AR (n)
(FROM 110 0Ev1 cE1

H'C5i]f

v z 11

,I
1

I

(TO CPU)
HOLDA

I

t-'·

( FR~Ul

I

..,c

AG in)
(TO 1/0 DE VI CE)
MEMEN
(TO SYSTEM)

"%'.!
)q

CD
Q)

I

.

(TO SYSTEM)

0

(TO SYSTEM)

i5MAc:c

Q)

Q)

I
__.
0

~
(/)

<
en

~

CD

a

>-3

WE

OBIN
(FROM 1/ 0 DEVICE )

a

t-'·

I

1 ..,v~z-z...--.z-z-z~11---------------I

I

I

--------------

I

I

I

I

I

I

1

I

I

I

I

I

I

I

I

.--------------

o

I

HI 2

I

I

I

Hl ·Z

I

I

HI 2

I

'

1

I
I

I

I
Hl -2
I
I

H12

1

L - . . - - - -H
_1_2_ _ _ _ _ _ __

I

~----H....;l....;2;___ _ _ _ __

1

I
I
r _____H_1_.z_ _ _ _ _ __

I

Hl-2

I

11

Hl -2

fl------~----------...J1

(TO/ FROM 1/ 0 DEVICE

1

(F

I

1

AO·A 14
(FROM l/ ODEVICE)
DO·D15

t-'·

::;,

I

I
t - - - - - -H.;.:.1...:2;___ _ _ _ __
r-~~~...:....::.~~~~~-

HI Z

R~~~e~TEM/ z z zz zI zzz z z z z z z z zI z /1

v zz>zz1 e z 11 v z z>z z z z z zz z z z z z zz

STARTO
MEMENQ
RELEASEQ

I
I

I

I

I

I

I

I

,.--------------......,

II

I

;,......
I _ _ __

I
I

I
I

I

MFIRSTO
MW A I TO
MLASTO

I

___

,_

The acquisition of memory control from the system begins when the HOLD signal is
asserted by the OMA device. This signal is driven by an open-collector circuit and
· must be synchronized to the trailing edge of clock phase one (¢1). The acquisition
phase ends at the first trailing edge of o1 following the receipt of HOLDA . Round-trip
timing delays between the DMA device and the CPU must be considered during device
controller design .
The control of memory by the OMA device begins at the completion of the acquisition
and continues for as many memory cycles as required. The device controller must
provide the memory cycle timing signals MEMEN, OBIN, WE, and DMACC (TM 990 bus signal)
as well as the memory address and data signals . The memory cycle timing must duplicate
the microcomputer memory cycle timing with respect to minimum setup and hold times and
also to synchronization to o1 and o3 clocks. The device controller must monitor the
READY signal and wait as required by the memory. The device controller must not
require unnecessary wait states (wait states not required by the microcomputer)
because of device controller setup timing; however, the device controller can delay
the start of a memory cycle to allow setup time for the OBIN, DATA, and address
signals.
The release of memory control to the system begins when HOLD is released by the DMA
device and is complete when the CPU releases HOLDA . Since the CPU requires two ¢1
clock cycles for the release of HOLDA, resumption of memory access during the release
phase can cause a memory access conflict when the OMA device responds to HOLDA just
prior to HOLDA being released . This conflict will cause loss of data and possibly
modification of random memory locations.
8 . 6 . 2 MEMORY CYCLE TIMING (FIGURE 8-9)
As shown in Figure 8 - 9, a memory cycle consists of two states, MFIRSTQ and MLASTQ,
plus wait states MWAITQ as required by memory. Each state is one o1 clock cycle long .
If additional OBIN, data or address setup time is required, a setup state can be
inserted before the MFIRSTQ state . The MLASTQ states marks the end of a memory cycle .
Read data will be stable at the end of MLASTQ. The control signals MEMEN and HOLD
which are static during a memory cycle are allowed to change at the end of MLASTQ. In
a mult ichanne l-OMA contro l ler, t he device access granted signals are allowed to change
at the end of MLASTQ.
8 . 6. 3
1.

OMA SYSTEM GUI DELINES
OMA and CPU memory cycle timing should be identical .

2.

OMA memory cycles can include memory-dependent wait sta tes.

3.

OMA devices must not require memory to i ns ert wait states.

4.

OMA devices mus t a l low HOLDA to drop after rel easing HOLD pr i or to r ea sser t i ng HOLD .

5.

Three-stat e bus conflicts must be avoided .

6.

Multiple OMA devices must not attempt simul t aneous memory a ccess .

7.

Sufficient da ta and addres s setup times prior t o WE must be mai ntained .

8.

Most OMA device timi ng problems will occur at the first and last memory acc esses a nd at device to devi ce changeover i n systems with mult i ple devi ces.

8-11

I
I

n

NORMAL
MEMORY
CYC LE

n

MEMORY CYCLE
WITH l WAIT ST ATE

n

I

n

n

I

I
I

I

I

n

n

MEMORY CYCLE
WI TH SETUP ST A TE

n

n

I

I

n

I

\? 3

MSETUPO

MFIRSTO

MLASTO

Figure 8-9.

Memory Cycle Timing

8.6.4 MULTIPLE-DEVICE DIRECT MEMORY ACCESS CONTROLLER
This section outlines the design of an eight-device, priority-access controller for
the direct memory access system shown in Figure 8-10. The controller accepts access
requests from the device controllers, acquires memory from the CPU, grants memory
access to the highest-priority device switching from device to device as required, and
generates all necessary memory cycle timing signals .
The OMA controller interfaces with the device controllers (shown in Figure 8-11)
through a DMA control bus consisting of access request (ARO through AR7), access
granted (AGO through AG7), and memory cycle complete (MCOMP) signals. To access memory
a controller asserts access request and waits for access granted. The controller then
drives the address bus (AO through A15), and the data bus (DO through D15) as
required, and t h e DBIN signal . The MCOMP signal indicates that the memory cycle will
be complete and read data will be stable on the data bus at the trailing edge of the
o1 cl ock. A device can request multiple memory cycles by continuously asserting access
request . Access request is released during the first clock cycle of the last required
memory cycle.

8-12

OMA CONTROL BUS

I
I

l

I
I

I

OMA
DEVICE

OMA

OMA
DEVICE

OMA
CONTROLLER

I

I

DEVICE

SYSTEM BUS

CPU

MEMORY

Figure 8-10.

..

OM A CO NTROL
BUSTO
OMA CO NTROLLER

{

DMA System Block Diagram

{

AO thru A 15
OBIN
I NTn

MCOMP
DEVICE
CON TROLLER

- - -ARO thru AR7
OMA CONTROL
BUSTO
NEXT DEVICE

DOthruD15
,____
-

-ARO thru AR7
- AGO t h ru AG7

-

-

_ CRUOUT
CRUC LK

AGO thru AG7

- -MCOMP

Figur e 8-11.

CRU IN

91
IORST

DMA Device Controller

8-13

:
-

SYSTEM
BUS

The DMA controller (shown in Figure 8-12) provides memory access control, memory cycle
,timing, and priority-based access of memory by the device controllers. Access requests
a re synchronized to system clock, then prioritized using a priority encoder followed
by a decoder. The priority encoder also provides the signal DMAR which indicates if
any device is requesting access. Memory access is granted to the highest-priority
device when HOLDA is received from the CPU and at the end of each memory cycle. This
is done by loading a register with the decoder outputs . If no device is requesting
access, the decoder is disabled and the register is loaded thus disabling all access
grant~d signals. Loading of the register is inhibited from the time HOLD is released
by the DMA controller until HOLDA is released by the CPU in order to avoid an access
conflict between the DMA and the CPU due to the HOLDA response time.

ARO thru AR7

8

'

'

REG
(74LS374}

- -AROQ thru AR7Q

,, •

1

8

HOLD

--MEMEN
-

PRIORITY
ENCODER
(74 148)

WE
OMAR

DMACC

-

DMOUT
OMA CONTRO L
BUS TO
DEVICE
CON TR OLLERS

,,

CONTROL
LOGIC

3

DMIN
HOLDA
OB IN

DECODER
(74LS138}

. READY

q;f

~

'q53

. TqjfST

8

I;

'

REG
(74LS374}

-

-

-- ,
-AGO thru AG7

-

ACCLK

8

MC~P

Figure 8-12.

DMA Controller

8-14

SYSTEM
BUS

The DMA controller timing with priority contention is shown in Figure 8-13 . The logic
equations for the DMA controller are:

•

DMAR

=

AROQ

STARTQJ

=

DMARQ

•

MEMENQ e RELEASEQ

STARTQK

=

HOLDA

STARTQ

MEMENQJ

=

HOLDA

•
•

MEMENQK

=

DMARQ

RELEASEQJ

=

DMARQ

RELEASEQK

=

HOLDA

HOLD

=

DMAR • RELEASEQ

MFIRSTQD

=

HOLDA e STARTQ

MWAITQ 0

=

MFIRSTQ • READY

+

MWAITQ • READY

MLASTQD

=

MFIRSTQ

+

MWAITQ e READY

=

OBIN • MFIRSTQ

DMACC

=

MFIRSTQ

ACGATE

=

HOLDA e STARTQ

ACCLK

=

ACGATE •

MCOMP

=

MLASTQ

+

AR1Q +

•
•
•

+

STARTQ

= STARTQ

MLASTQ
MLASTQ

= MEMENQ

RELEASEQ

+

+

STARTQ

+

MEMENQ

DMAR e MLASTQ

+

READY

+

AR7Q

WEQ

MWAITQ

MWAITQ

+

MLASTQ

¢1

where signals ending with the letter Q are flip-flop outputs and signals with
subscripts are the corresponding flip-flop inputs. All flip-flops are
code-triggered on the trailing edge of ~1 except WEQ (¢1 leading edge).

8-15

w

u

>
w
a

0

w

u

>
w
a

... ... I~ ~
M

I~



011 1011
011 1100
011 1101
011 1110

JE

n

110 1101
110 1110

?

011 1111

3f

0

110 1111

6E'
6F

@

100 0000
100 0001

40
41

p

A

111 0000
111 0001

70
71

8

100 0010

c

100 0011
100 0100

42
43

s

111 0010
111 0011

44
45

72
73
74

u

~

Ii

47

w

<

D
E
F

G
H
I
J
K

L
M
N

0

100 0101
100 0110
100 0111
100 1000
100 1001
100 1010
100 1011
100 1100

38
JC

I
m

30

q

r
t

48
49
4A
48

100 1101

4C
40

100 1110
100 1111

4E
4F

75
76

"

111 1000
111 1001

78
79

l

111 1010
111 1011
111 1100
111 1101

7A
78

{
I
I

J

C-2

111 0100
111 0101

6C
60

111 0110
111 0111

y

•American S1andards lns111u1e Pub41ca11on X3 4 . 1968

110 1011
1101100

111 1110

77

1C
70
7E

APPENDIX 0
BINARY. DECIMAL AND HEXADECIMAL NUMBERING

0 -1 GENERAL
This appendix covers numbering systems to three bases (2, 10, and 16) which are used
throughout this manual.

0 -2 POSITIVE NUMBERS
0-2.1 DECIMAL (BASE 10). When a numerical quantity is viewed from right to left, the rightmost digit represents the base number to the exponent 0. The next digit represents the base
number to the exponent 1, the next to the exponent 2. then exponent 3, etc. For example, using
the base 1O (decimal):
106 105 1o4

X,

X

1o3

X X.

102

101

1oO

X

X

X

or

, ,000 ,000
100,000

!

I , o.ooo

' t

1000

x. xx x

100 10

x

x

1

x

For example. 75,264 can be broken down as follows ·
75, 264
L 4 x 1 0" 4 x 1
6 x 10

1 6 x 10

2 x 10~

2 x 100

5 x 103 5>e1000
7 x 10'

7 x 10.000

D-1

4

60
200
5000
+70CX>0
7526410

D-2.2 BINARY (BASE 2). As base 10 numbers use ten digits, base 2 numbers use only 0 and
1. When viewed from right to left, they each represent the number 2 to the powers 0, 1, 2, etc.,
respectively as shown befow:

-fa

215
(32,768) • • •

x

z4

i3

21

2'l

(64) (32) (16) (8)

(2)

( 1)

x

x

••• x

25

x

x x

For example, 11011 2 can be translated into base 10 as follows:

1

0

t~1
L.. '° ~ .• .~ ,
x 21 = 1 x 2 =

_ _ _ _ _.... , x 22 .. 0 x 4

2

=

0

- - - - - - - 1 x 2 3 = 1x8 =

8

,___ __ _ _ _ _ _1 x

z4

= 1 )( 16 = +16

or 11011 2 equals 2710.

Binary is the language of the digital computer. For example, to place the decimal quantity 23
(23111) into a 16-bit memory cell, set the bits to the following:
15

0

which is 1

+ 2 + 4 + 16 "' 2310.

D-2.3 HEXADECIMAL (BASE 16). Whereas binary uses two digits and decimal uses ten
digits, hexadecimal uses 16 (0 to 9, A, B, C, 0, E, and F).
.

.

The lelt•s A through Fare used to represent the decimal numbers 10 through 15 as shown on
the fonowing page.

D-2

N,,

N ,~

N iu

N 1&

0

0
1

8
9
10
11

8
9

1
2

2

3
4

•

3
4

5

5

6
7

6
7

A

B

c

12
13

D
E
F

14
15

When viewed from right to left, each digit in a hexadecimal number is a multiplier of 16 to the
powers 0, 1. 2. 3, etc., as shown below:

For example, 7 B A

5 16

7

163

152

151

150

(4096)

(256)

116)

(1)

x

x

x

x

can be translated into base 10 as follows:

B

A

5

T "L 5 x , so =

sx ,

L _10 X 151 = lOX16
, 1 x 152 = 11
7

x

163 = 7

5
160

x 256

2 816

x 4096

28672
31 65310

or 7 BA

5 1i.

equals 31 ,653 111.

Because it would be awkward to write out 16-digit binary numbers to show the contents of a
16-bit memory word, hexadecimal is used instead. Thus
003E16 or

> 003E ( > indicates hexadecimal)

1s used instead of
0000 0000 0011 1110:

to represent 6210 as computed below:

0-3

BASE 2

t

BASE 10

6

l_Sx20
, x 21
1 x 22
1 x 2-1
, x i4
x 25

0

t_

~2X 11/l

2

6

x

2

101

60

4
6210

8

16
32

BASE 16

6210

3

E16

~14X
3

x

160

14

15 l

48
6210

Note that separating the 16 binary bits into four-bit parts facilitates recognition and t ranslation
into hexadecimal.
0000

•
0

0000

0011

+
+
0
3

or

c

7

1100

0111

~

•

B

+

1011

1111 2

Table 0 - 1 is a conversion chart for converting decimal to hexadecimal and vice versa. Table D-2
shows binary, decimal and hexadecimal equivalents for numbers 0 to 15. Note that Table D-1 is
divided into four parts. each part representing four of the 16-bits of a memory cell or word (bits
Oto 15 with bit 0 being the most significant bit (MSB) and bit 15 being the least significant bit
(LSB). Note that the MSB is on the left and represents the highest power of 2 and the LSB on the
right represents the 0 power of 2 (2° 1). As eJCPlained later, the MSB can also be used to signify
number polarity (+ or - ).

NOTE
To convert a binary number to decimal or hexadecimal, convert
the positive binary value as described in Section 0-4.

D-4

TABLE D- 1. HEXADECIMAUDECIMAL CONVERSION CHART

MSB

LSB
163

BITS

0

1

2

16
3

4

5

HEX

DEC

HEX

0
1
2
3
4
5
6
7
8
9
A

0
4 096
8 192
12 288
16 384
20 480
24 576
28 672
32 768
36 864
40 960
45 056
49 152
53 248
57 344
61 440

0
1
2
3

B

c
D
E
F

161

2

6

7

DEC
0
256
512
768
1 024
1 280
1 536
1 792
2 048
2 304
2 560
2 816
3 072
3 328
3 584
3 840

4

5
6
7
8
9
A
B

c
D

E
F

8
HEX
0
1
2
3
4
5
6
7

8
9
A
8

c
D

E
F

7

8

16°
11

DEC
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240

12 13 14
HEX

DEC

0
1
2
3

0
1
2
3
4
5
6
7
8
9
10

4

5
6

7
8
9
A
B

c

D
E
F

15

tl
12
13
14
15

I
To convert a number from hexadecimal. add the decimal equivalents for each hexadecimal
digit. For example, 7A8216 would equal in decimal 28.672 + 2.560 + 128 + 2. To convert
hexadecimal to decimal. find the nearest decimal number in the above table less than or equal
to the number being converted. Set down the hexadecimal equivalent then subtract this
number from the nearest decimal number. Using the remainder(s). repeat this process. For
example:

31 ,362111 700016 + 269010
2,69010 A001~ + 1 3010
130w 801 6 + 21 0
2111 2 1 ~

7000
AOO
80
2
7A82 16

--

0-5

TABLE D -2. BINARY, DECIMAL. AND HEXADECIMAL EQUIVALENTS

BINARY
(N2)

DECIMAL
(N10)

HEXADECIMAL
(N 16)

{)()()()

0
1
2
3
4

0
1
2
3
4

5

5

6
7

6
7
8
9

0001
0010
0011
0100
0101
0110
0111

1000

8

1001
1010
1011
1100
1 101
1110
1111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11 110
11111
100000

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

A

B

c
D

E
F
10
11
12
13
14

15
16

17
18
19

lA
18
1C
10
1E
1F
20

30
31
32

0 -6

D-3 ADDING ANO SUBTRACTING BINARY
Adding and subtracting in binary uses the same conventions for decimal: carrying over in
addition and borrowing in subtraction.
Basically,

1

0
+ 1

t

10

-

1

10

~}
+ 1

(the carry. 1, 1s carried to the left)

01

11

0 (from above)

+ 1

+

1

Lcarry

0 + 1 carry

1

11 }

= 0 + 1 carry

carry 1 + 1

1~

--=..!. (

Borrow the 1

0111 '

+

100

( 1 is borrowed from
top leftl

0 + carry 1

11

1 }

,

~

11-o + o = o
carry 1 + carry 1

..

0-7

1
~ 0110

l 0~1:

1

101
10__;-

D -4 POSITIVE/ NEGATIVE CONVERSION (BINARY). To compute the negative equivalent
of a positive binary or hexadecimal number, or interpret a binary or hexadecimal negative
number (determine its positive equivalent) use the two's complement of the binary number.

NOTE
To convert a binary number to decimal. convert the positive binary
value (not the negative binary value) and add the sign .
Two's complementing a binary number includes two simple steps:
a.

Obtain one's complement of the number (1 's become O's, O's becomes 1 's) (invert
bits).

b.

Add 1 to the one's complement.

For example , with the MSB (left -most bit) being a sign bit:

101

Invert

000

+ 1

Add 1

+ 1 Add 1
001

Invert

001

Invert

010

+ 1

Add 1

+ 1

Invert

{+ 12)

This can be expanded to 16-bit positive numbers:

(=39F6 15l

0011'

1001

1111

0110

(39F615

1100

0110

0000

1001

Invert

+1
(=C60A15)

1100

0110

~SIGN

0000

+ 14,838101

Add 1

1010

(C60A15

- 14,838101 Two's Complement

BIT(- )

And to 16-bit negative numbers:

(=C60A15l

1100

0110

0000

1010

(C60A15

0011

1001

1111

0101

Invert

+l
{=39F615)

0011

L

1001

1111

0110

14,838101

Add 1
(39F6 15

s1GN B IT(+l

0 ·8

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+ 14,838101 Two's Complement

APPENDIX E
PARTS LIST
Table E-1.
Symbol

Parts For all Dash Numbers

Description
Capacitor, 0.047

C1-C8, C11 ,

-0001

pF

-0002

- 0003

x

x

x

C13- C17,
C19-C22, C24
C26-C39, C41-C44
C9, C12, C25, C40

Capacitor, 22 mFd

x

x

x

C10

Capacitor, 18 pFd

x

x

x

C45-C48

Capacitor 0.047 mFd, 10%

x

x

x

CR1, CR2

Diode, IN5333B

CR3

Diode, IN914B

DS1

Diode (L.E.D., CM 4-43)

x

E1 - E40, E53-E56

Pin, Jumper (BE! 75481 - 002)

x

E1 - E35, E38 - E56

Pin, Jumper (BE! 75481-002)

All Jumpers

Plug, Jumper (BE! 65474- 004,
R 530153- 002)

x

x

x

L1

Coil, RF , 033 µH

x

x

x

P2, P3

Connector, 25 pin (AMP 206584- 2)

x

x

x

Q1

Transistor, PNP

x

Resistor, 4.7K ohm

x

x

x

R3, R12

Resistor, 2.2K ohm

x

x

x

R6

Resistor, 1. 0K ohm

x

x

x

Resistor, 10.0 ohm

x

lC

x

R13, R16, R17

Resistor, 2 .2 ohm

x

x

x

R18, R24, R25

Resistor, 68.0 ohm

x

x

x

R1 ,

R2 , R4 , R5 , R7 ,

x
x
x

x
x

x

x

RB, R11 , R23, R26,
R44, R45

R9 , R10 ' R14

I

R15

E-1

Table E-1.

Parts For All Dash Numbers (Continued)

Symbol

Description

R19, R21, R39

Resistor, 330 ohm, 1/4

R34, R40, R41, R43

Resistor, 330 ohm, 1/4

R20, R22

Resistor, 220 ohm

x

x

x

R27

Resistor. 3.9K ohm

x

x

x

R28

Resistor, 2.7K ohm

x

x

R29

Resistor, 330 ohm, 1/2 w

x

x

R30

Resistor 33K ohm

x

x

R31-R33, R42

Resistor, 27K ohm

R35, R36, R46, R47

Resistor, 3.3K ohm

x

R37

Resistor, 3.3K ohm

x

x

R38

Resistor, 560 ohm

x

x

S1

Switch, toggle

x

x

x

S2

Switch, 5 position DIP

x

x

x

U1

IC, TMS 9901

x

x

x

x

x

x

(]2'

ua

Resistor, 10 . 0K ohms

w
w

-0001

-0002

-0003

x

x

x

x

x

pkg.

x

x

U3, U26, U32

IC, SN74LS241N, Line Drivers

x

x

x

U4, U18

Network, SN74LS08N

x

x

x

U5, U6, U10 , U17, U20

Network, SN74LS74N

x

x

x

U7, U27

Network, SN74LS04N

x

x

x

U9, U39

Network, SN74LS251

x

x

x

U11

Network, SN74LS132N

x

x

x

U12

Network, SN74LS14N

x

x

.)(

U13, U14 1 U22, U23

IC, SN74LS245N,
Octal Buffer

x

x

x

E-2

Table E-1.
Symbol

Parts For All Dash Numbers (Continued)
Description

- 0001

- 0002

-0003

U15

TMS 9900

x

x

x

U16

TIM 9904, clock driver

x

x

x

019

PROM, 74S287, memory decode

x

x

x

U21

Network, SN74LS02N

x

x

x

U24

Network, SN74LS153N

x

x

x

U25, U52

Network, SN74LS138N

x

x

x

U28, U30, U34, U36

TMS 4045 1024 x 4 RAM

U29, U31, U35, U37

TMS 4045 1024 x 4 RAM

x

x

U33, U49

IC, SN75188N, Line Drivers

x

x

x

U38

Network, SN74LS10N

x

x

x

U40 I 041

Network, SN75189AN

x

x

x

U42

TMS 2708, EPROM, TI BUG
byte 1

x

TMS 2708, EPROM, TIBUG
byte O

x

U44
U42, U44

TMS 2716, 2048 x 8 EPROM

U42-U45

TMS 2716, 2048 x 8 EPROM

U46, U47

TMS 9902 Asynchronous
Communication Controller

x

x
:<

x

x

x

U48

IC, SN75112N

U50

Network, SN74LSOON

x

x

x

U51

IC, SN74LS259N, low power
Schottky

x

x

x

U53

Network, SN75154N

x

x

x

U54

Network, SN751074N,
Interface

x

E- 3

x

Table E-1.
Symbol

Parts For All Dash Numbers (Concluded)
Description

- 0001

- 0002

-0003

IC, UA 7905C/MC 7905CP ,
Voltage Regulator

x

x

x

XU1

Socket, 40 pin

x

x

x

XU15

Socket , 64 pin

x

x

x

XU16, XU47

Socket , 20 pin

x

x

x

XU19

Socket, 16 pin

x

x

x

XU28-XU31, XU34-XU37
XU46

Socket, 18 pin

x

x

x

XU42 - XU45

Socket, 24 pin

x

x

x

x

x

x

VR1

Xl

Crystal, 48 MHz,
3rd overtone, 5%, HC-18U

8- 4

APPENDIX F
SCHEMATICS

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0034 IZ.•"1:28'
001.2 0096 1 0(11.
001l 0098
LOOP
001.4 0098 O:iH
009A 12:i4
001.~ 009<: 0244
0EJ9E FEED
001.6 00A0 DC:84
0017 130R2 020"3
f.10A4 555'5
0018 00A6 Cl305
130A8 0026'
0019

12

ANDI 4, >FEED
LI

4 · •2+
5 .. )5~55

MOV

5 , @TABLE

M0'./8

END

NO ERRORS

0 0 ORA !: AMPLE
H II 11(1 (IC (I (11)..;. c fll)t:A B 0 0 (J (•H 1111·.:.H r . 04 ( c r : 0 41" (If: I II I 11 to..:,':· [· I°.:: OO?F 20 ftF
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SAMPLE
00 , 00 00
08:14:23
~ D:M8 C ~ -15 278 ••

FIGURE G -2. SOURCE CODE AND CORRESPONDING OBJECT CODE

I
r

G-b

II ll IJ
1_11.1 I)

APPENDIX H
Pl , P2, AND P4 PIN ASSIGNMENTS

TABLE H- 1. CHASSIS INTERFACE CONNECTOR (P1 ) SIGNAL ASSIGNMENTS

P1
PIN
33
34
35
36
37
38
39
40
41
42
43

44
45
46
47
48
57
58
59
60
61
62
63
64
65
66
67
68
69
70

SIGNAL

Pl
PIN

00.B
01 .B
02.B
03.B
04.B
05.B
06.B
07.B
08.B
09.B
010.8
011 .B
012.B
013.B
014.B
015 .B
AO.B
Al.B
A2.B
A3.B
A4.B
AS .B
A6.B
A7.B
A8.B
A9.B
A10.8
A11 .B
A12 .B
A13.B

71
72
22
24
92
86
82
26
80
84
78
90
87
30
29
19
94
88
16
13
15
18
17
20
6
5
8
7
10
9

SIGNAL
A14 .B
Al5 .B
.0'1 .B
.03.B
HOLO.B
HOLOA.B
OBIN .B
CLK.B
MEMEN.B
MEMCYC.B
WE.8
REAOY.B
CRUCLK.8
CRUOUT.B
CRUIN.8
IAO.B
~. B

IORST.B
iNfl.B
fITTTB
iNl'J.B
fNT4.B
INTS".B
INT6.B
INT7.B
ffrnr.B
i'NT§:B
INT10.B
INT11 .B
INT12.B

H· 1

P1
PIN

SIGNAL

12
11
14
28
3
4
97
98
75
76
73
74
1
2
21
23
25
27
31
77
79
81
83
85
89
91
99
100
93

INT13.B
INT14.B
INT15.B
EXTCLK.8
+ SV
+ sv
+ sv
+ SV
+12V
+ 12V
- 12V
-12V
GNO
GNO
GNO
GNO
GNO
GNO
GND
GND
GNO
GNO
GND
GND
GNO
GND
GND
GNO
RESTART.B

I

'

I

TABLE H-2. SERIAL 1/0 INTERFACE (P2) PIN ASSIGNMENTS

P2

PIN

SIGNAL

DESCRIPTION

1

GND

7

GNO

3

RS232 XMT

RS232 Seria l Data Out

2

RS232 RCV

RS232 Serial Data In

5

CTS

Clear to Send
(3.JKn pull-up to + 12 V)

6

DSR

Data Set Ready
(3 .3KO pull -up to + 12 V)

8

DCD

Carrier Detect

20

DTR

Data Term inal Ready

18,23

TTY XMT

TIY Receive Loop/ Private
Wi re Receive Pair

24,25

TTY RCV

TIY Transm it Loop/ Private
Wire Transm it Pair

17

ACV CLK

Receive Clock

15

XMT CLK

Transmit Clock

12•

+12 v

Jumper Option for M icroterminal

13•

- 12 v

Jumper Option for Microterminal

14*

+5 v

Jumper Option for Microterminal

16

RESTART

Invokes the Load
Interrupt to the TMS 9900 CPU

'Wheri using the Micro terminal. these voltages are 1umpered to the corresoond•ng 01n in connector P2 Else. the voltaqes are not cnnn1.tctert

H-2

TABLE H.3 SER I AL 1/0 INTERFACE (P3) PIN ASSIGNMENTS

P3 PIN

1
7
2

3
5
6
8

16
19
20

L

21
15

17

22

SI GNAL

--

OPTIONAL GND
GNO
RS232 RCV
RS232 XMT
CTS-Terminal
DSR-Terminal
DCD-Terminal
CTS-Modem
DSR-Modem
DTR-Terminal
DCD-Modem
DTR-Modem
SCT
SCR
RI

D ESCRI PTION

GROUND IF JUMPER AT E18, E19
GROUND
RS232 Serial Data In
RS232 Serial Data Out
Terminal Clear to Send (3.3 k!1 pull-up to + 12 V)
Terminal Data Set Ready (3.3 k!1 pull-up to +12 V)
Terminal Data Carrier Detect
(activated by TMS 9902 Request to Send)
Modem Clear to Send•
Modem Data Set Ready•
Terminal Data Terminal Ready
Modem Data Carrier Detect•
Modem Data Terminal Ready•
Synchronous Transmit Clock
Synchronous Receive Clock
Ring Indicator

J

--

·used with TM 990/ 506 Modem Cable Only.

I
r

H-3

TABLE H-4. PARA L LEL 1/0 INTERFACE (P4) SIGNAL ASSIGNMENT

P4 PIN
20
22
14
16
18
10
12
24
26
28
30
32

34
36
38
40
7
8

P4 PIN

SIGNAL
PO
P1
P2
P3
P4
PS
P6
INT15 or P7
iNTT4 or PB
INT13 or P9
INT12 or PlO
INT11 or P11
INT10 or P12
1N1'9 or P13
INT8 or P14
mi1 or P15
GND
POSITIVE EDGE TRIGGER INT6

17
15
13
11
9
39
37
35
33
31
29
27
25
23
21
19
1
2
3

4

5
6

H-4

SIGNAL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+12
- 12
+5
SPARE
GND
NEGATIVE EDGE TRIGG ER INT6

v
v
v

APPENDIX I
TM 990/301 MICROTERMINAL
1.1

GENERAL
The Texas Instruments Mic1oterminal offers all of the features of a minicomputer front panel at reduced cost
The Microterminal, intanded primarily to support the Texas Instruments TM 990/1.XXM microcomputers. al
lows the user to do the following:
•

Read from ROM or re ad/write to RAM

•

Enter/display Program Counter

•

Execute user program in free running mode or in single instruction mode

•

Halt user program execution

•

Enter/ display Status Register

•

Enter/ display Workspace
microprocessor)

•

Enter/display CRU data (this term is unique to the Texas Instruments 9900 microprocessor)

•

Convert hexadecimal quantity to signed decimal quantity

•

Convert signed decimal quantity to hexadecimal quantity

Pointer (this term is unique to the Texas Instruments 9900

1.2 SPECIFICATIONS

r
1.3

•

Power Aequ irements
+12V (±3%), 50 mA
- 12V (±3%). 50 mA
+5V (±3%), 150 mA

•
•

Operating Temperature : O" C to 50° C {+32'' to +t22° F)

•

Shock : Withstand 2 toot vertical drop

Operat ing Humidity : 0 to 95 percent. non·condensing

INSTALLATION AND STARTUP
To install the Microterminal onto a TM 990/ 1XX microcomputer. do the following ;
•

Attach jumpers to :
On TM 990/ lOOM. J13, Jl4, and J15, and set J7 to EIA position
On TM 990/ 101M . E20-E21, E22-E23, and E24-E25
On TM 990/ 180M: J4, J5, and J6, and set J13 to EIA position.

•

Attach the EIA cable from the Microterminal to connector P2 . Signals between the Microterm1nal
and the microcomputer are lasted as in Table t.

•

To initialize the system, actuate the microcomputer RESET switch , then press the m1crotermtnal
[CLAlkev.
NOTE
If the user has installed the oprtonal filter capacitor on the RESTART input, this
capacitor must be removed for proper operation (e.g., if CS is installed on the
TM 990/100M o r TM 990/1 BOM microcomputer, this capacitor must be
removed).

1-1

..

FIGURE 1-1. TM 990/301 MICROTERMINAL

TABLE 1-1. EIA CABLE SIGNALS
Interface
Signal

EIA Connector

Pin

~T TM 990/100M/180M/101M
P2 Pin
Signal

2

TERMINAL DATA OUT

- 2

3

TERMINAL DATA IN

- 3

RS232 XMT

7

GND

-7

GND

12

+12V

- 12

+12V

13

- 12V

- 13

- 12V

14

+ 5V

- 14

+ 5V

- 16

RESTART

16

HALT

1-2

RS232 RCV

CAUTION
Before attaching the M1crotermi nal to a power source, verify voltage
levels between ground and EIA connector pins 12, 13, and 14
at connector P2 on the board. Voltage should not exceed values 1n
Table 1-1.

1.4
1.4.1

KEY DEFINITIONS
DATA KEYS
Clear Key - Depressing this key blanks display, Initializes and sends in itialization message (ASCII code
for A and ASCII code for ZI to host microcomputer.
He.xadecimal Data Keys - Depressing any one of these keys shifts that value mto the rifllt·hand display
digit. All digits already in the data display are left shifted. For all operations other than decimal to
hexadecimal conversion, the fourth digit from the rif/lt is shifted off the end of the right-hand display
field when a data key 1s depressed. For a decimal to hexadecimal conversion, the fifth display digit from
the rif/lt. rather th an the fourth, 1s shifted off the end of the data field.

1.4 .2

INSTRUCTION EXECUTION

~

IRUNI
1,4.3

Pressing this key while a program is runnmg (run displ11yed) will halt pr0!7am execution The address of
the next instruction will be displayed in the four left ·hand display d igits, and the contents of that
address wi ll be d isplayed in the fou r rifllt hand d igits. Pressing ttiis key while the program is halted, will
execute a single 1nstruc t1on using the values in the Workspace Poi nter (WP), Program Counter (PC) , and
Stat us Register (ST), and the displays will be updated to the next memory address and contents at that
address
Pressing this key initiates program execution at the current values m the WP. PC: run is displayed in the
thr ee right-hand display digits.

ARITHMETIC

I H -DI

The s1yned hexadecimal data r.ontamed in the four r 1ght·hand display digits is converted ta signed
decimal data No te that the four th d1sn lay d igit from the right IS th e sign bit ( 1
negative). The
convN\1on l1m115 are minus 32. 76810 (8000161 to plus 32. 767 (7FFF15I. Two H-D key depressions are
1 equ11 ed The sequence is
1
2
J

Dt·111css IH - DI
Entrr data via hex datd key depressions.
Dt•pre•ss jH
Tlw 1ernl1s of the convcr~1on are d1sptayrd In the fiv e right hand d1splJy

·DJ .

chy1ts

[IT:::]]

Thi· d"rtmal llJt;i co11 ta1111'd 111 th1· 111/f• 11ql11 hand d1~ploy digits is converted to hex;idec1mal Tlw
Jrt· tilt' samr
lrn hr·' OOFF

CLEAR WORKSPACE REGISTER 0
INCREMENT WORKSPACE REGISTER 0
CHECK FOR COUNT 255

JNE
JMP

$-6
$-0

JUMP TO INC RO IF NOT DONE
STAY HERE WHEN FINISHED

KEY ENTRIES

DISPLAY

Clear Display

Depress

jCLA)

Enter PC Value

Depress

[£ZJ [fil (QJ rg

IFeool

Enter 1n10 PC

Depress

I EPC I

IFEool

Display PC

Depress

IDPCI

IFEool

Enter ST Value

Depress

[IJ@]@]@l

120001

Enter into ST

Depress

!EST

I

120001

Display ST

Depress

IDST!

120001

Enter WP Value

Depress

@] (Fl- j@J@J

jFFool

Enter Into WP

Depress

!ewPI

IF Fool

Display WP

Depress

lowPI

jFFool

Enter MA Value

Of' press

0~121@1

IFeooJ

Enter Into MA

Depre's

!EMAi

jFEajxxxxl

Enter CLR 0 Opcode

Depress

@] @]@]@]

IFEool 04col

Enter data,
increment MA

0Ppress

IEMDll

jF E02]xxxxl

Enter INC 0 Opcode

Depress

@] ~~@]

IFE02lossol

Enter Data,
Increment MA

Oep11·~~

IEMOI]

[ff04[maj

()1'1111·~'

@]~~@]

IFE04jo28ol

DrorP~\

I f.MOll

fFE06lxxxxl

En ter C l Opcode
Enter Data,
Increment MA

KEY
Enter Cl
Immediate Operand
Enter Data,
Increment MA
Enter JNE $·6
Opcode
Enter Data,
Increment MA
Enter
JMP $-0 Opcode
Enter Data,
Increment MA

EN TRI E~

!;)!SPLAY

0Ppress

@]@] ~~

Depress

jEMDll

Depress

ITJ~[EJ(g

Depress

IEMOij

IFEoslooF FI
IF Eoalxxxx I
IFEDBl16FC I
IFED~ I

Depress

ID&J~[J

jFEOAj lOFFI

Depress

IEMDll

jFEOC!xxxx)

)()(XX

The progtam has now been entered into RAM. Since the PC, ST and WP values have been previously set. the
pro!Jam can be executed in single step mode by depressing the H/S key.
DISPLAY
(AFTER)

EXECUTES
INSTRUCTION

INC

AO

lH/Sj

lFE02losao I
IFE04I0280 I
jF E08j16FC I

Cl

RO,> OOFF

jH/Sj

IFE02!05ao I

JNE $- 6

Oi:?press

I HIS!

Depress

!HtSj

Depress
Depress

CLA RO

This cycle will continue until RO reaches the count of 255 at which point the program will continuously
execute at location FEOA15 because it is a jump to itself.
To verify this, depress :

DI SPLAY

j run

J

The program should now be "looping to self" at location FEOAt6· To verify this, depress :

I H/ S I

IFEoJgloFF

I

Now examine the memory location corresponding to Register 0.
Depress
Depress

fI] [[] @) []]

!FEOAIFFOO

I

lFFOO looFFI

This illustrates that FF1s did become the final contents of WPO. Note that, when the program was being
entered into RAM, !EMO 11 was used rather than EMO! because of the rather desirable feature of automatic
address incrementing. The advantage of using I EMDj is that the actual contents o f the addressed memory
location are displayed after key depression (echoed back after be 1nq entered).

I

1·6

1.5.2

EXAMPLE 2, HEXADECIMAL TO DECIMAL CONVERSIONS
Convert 8000 16 to a decimal number

Depress

I CLR I

Depress

I H-DI

Depress

m [QJ w w

Depress

I H-DI

laooo I
- 312168

I

Convert 0020 16 to a decimal number
Depress

I CLA I

Depress

I H-"'D I

Depress

[II@]

Depress

I H-..D I

1.5.3

EXAMPLE 3, DECIMAL TO HEXADECIMAL CONVERSIONS
Convert 45 10 to he><

Depress

ICLRI

Depress

ID-HI

Depress

[3][!]

Depress

ID-HI

Convert - 1024
Depress
Depress
Depress
Depress

1.5.4

10

45

I

11024

I

IFCOO

I

to hex

I CLR I
I D_,.H I

I Ft- I IT1 [Q] OJ
Io-HI

w

-

EXAMPLE 4, ENTER VALUE ON CRU

Send a bit pattern to the CRU at CRU address (bits 3 to l4 of R 12) OE016 with a bit count of 9 containing a
·
value of 5 (0000001Ol2).

1·7

Depress

lc LR I

Depress

[I] @] []] @]

Depress

f DCRUJ

I9oEolvvvvl

Depress

[QJ @] @] [ill

j 9oEolooo5 I

Depress

!ECRU

l90EO

I

I

YYYY indicates value at the current CRU address. No1e that alDCAUloperation is always required to

specify bit count/CRU address.

1.5.5 EXAMPLE 5. ENTER, VERIFY VALUE AT MEMORY ADDRESS
E.nter 0040 16 1nto locatt0n F E20 and verify that i1 got there.

I

Depress

jCLR

Depress

[j ®

Depress

IEMAJ

IFE20lxxXJC I

Depress

@] @]

I FE2op040 I

Depress

lEMDI

l FE20p040 I

jFE2ol

_ The contents of address FE20 are verified by an echo of data from memory to display following the
pressing of~ If it is desired to view and enter data at address FE22, depresslEMOJ

1·8

APPENDIX J
CRU INSTRUCTION AND ADDRESSING EXAMPLES USING TMS 9901
The following figures 1 J-1 to J-6, are examples of addressing the TMS 9901 through
the CRU, pointing out in graphic form:
•

External I/O in parallel tmultibit) and serial (single bit) forms,

•

The relationship betweeo the CRU bits addressed and the bits in the source
operand of the S'fCR instructions,

•

The relationship between the CRU bit addressed and the displacement in
single-bit instructions.

The TMS 9901 occupies 32 bit positions of CRU space with the low 16 bits at CRU
software base address 0100 16 and the high 16 bits at CRU software base address 012016·
To access the low 16 bits of the TMS 9901 through the CRU, load 0100 into register 12 .
The high 16 bits at CRU software base address 0120 15 are the parallel I/O bits, shown
in the accompanying figures . These may be set, reset, or read in any order or in any
combination of 1 to 16 bits . Since CRU operations are serial, data from the
microprocessor (either serial or parallel) is transmitted serially to the TMS 9901,
which outputs it in parallel. Likewise, during input, data present at the TMS 9901 I/O
pins (in parallel) is shifted serially to the microprocessor using the CRU. It is
necessary only to load register 12 with 0120 16 and use either the LDCR or STCR
instructions . Bear in mind that the CRU operations of 1 to 8 bits affect the left byte
(more significant half) of a word (registers take up a full memory word).
The lower 16 bits of the TMS 9901 at CRU software base address 0100 16 are used for
control of interrupts and the timer function, and to restore the I/O lines to the
input mode with output buffers disabled and floating. Interrupt requests are presented
to the TMS 9901, each on its own line, and are compared against an internal mask. If
the internal interrupt mask allows, the particular interrupt request is encoded into
TMS 9901 output lines ICO to IC3 (going to interrupt input lines ICO to IC3 at the
TMS 9900) as explained on page 6 of the TMS 9900 data manual and page 8 of the TMS
9901 data manual. The TMS 9901 also pulls the INTREQ- line low on interrupt requests
(not during RESET), which goes to INTREQ- at the TMS 9900.

J-1

(1)

ASSEMBLY LANGUAGE:
LI
LDCR

(2)

R1 2 , >0120
RO, 15

SOURCE ADDRESS IN MEMORY:

7 8

3 4

0

11

12

ROLSB

15

...-------.

0

RO :

0

,

0

0

0

(LSB of RO)

1

PO
Pl
P2
P3
P4
PS

I

Ignored

(3)

R12: 1o

0

0

0

I I

0

0

0

0

0

0

0

0

0

0

I Ignored
Bit 15

Ignored

0

0

0

0

0

1

0

0

0

0

0

Ao------~------------~-~--------------

0

A14

L~~~~~~~-.-~~~~~~~~

DECODE

PIO
Pl l
P12
P13
P14
P15

0

Figure J- 1.

LDCR Word Execution To TMS 9901

J-2

TMS9901

PJS STATE REMAINS UNCHANGED

ADDRESS LINES

1

0

110
------"'--11-i

1

0

pg

ADDRESS

0

0

0

SELECT

0

;

PG
P7
PS

ADDRESSING :
Address lines at operation start

I

1

1

0

(1)

ASSEMBLY LANGUAGE :
R12, > 0128

LI
LDCR

R2,2

PO

(2)

SOURCE ADDRESS IN MEMORY:
0

I

•

Pl

R2

11

7 8

3 4

0

P2

0

0

0

12

P3
P4
P5
P6

15

0

0

-

TWO BITS TRANSFERRED

I

LEFT BYTE USED

P7

P8
pg

P10

Pl 1

(3)

P12

ADDRESSING :

I

R12: 1

0

0

0

0

0

0

0

0 0

0

ol

P13
P14
P15

Bit 15
Ignored

Ignored I

ADDRESS
SELECT
0

0

0 0 0

0 0

1

0 0

0

0

0 0

1/0

DECODE

Ao -------------------------------------- A14
ADDRESS LINES

Figure J-2.

LDCR Byte Execution To TMS 9901

J-3

0

(1)

ASSEMBLY LANGUAGE :
LI
STCR

(2)

R12, >120
R3,11

SOURCE ADDRESS IN MEMORY :

34

0

R3:

1 0

1

0 0 0

0

0

11 12

78

0

0

0

0

0

0

0

+5

15

1

0

0

1

Before

1

0

O

0

After

PO
Pl
P2
P3
P4
P5
P6
P7

ZEROED

(3)

ADDRESSING:

PS
pg

Address lines at operation start

PlO
P11

R12:

1~1- ·~-o~~-o_'_o~-o~-o~~-o~o~~-o~'-o~-o-~o~-0--'r-Bit
15
Ignored

I

1/0

,=i_,
0

0

0

P12
P13
P14
P15

ADDRESS
SELECT

Ignored

ZEROES -

v

DECODE

0

0

0

0

1

0

0

Ao -------------------------------------- A14

I

ADDRESS LINES

Figure J-3.

STCR Word Execution To TMS 9901

J-4

TMS 9901

-

(1)

ASSEMBLY LANGUAGE:
R12, ::> 120
Rl ,6

LI

STCR

(2)

SOURCE ADDRESS IN MEMORY :

0

R1

1,

PO
Pl

3 4

7

8

0

0

0

0

0

Be.fore

0

0

0

0

0

After

1

0

0

0

0

0

0

ZEROED

12

15

P2

P3
P4
PS
P6

UNCHANGED

P7

PS
pg

(3)

I

PIO

ADDRESSING:

R12 :1o
Ignored

0

0

0I 0

O

O

~II

r
0

0

0

0

0

0

0

1

I

0

0

l
0

0

I

0

0

0

0

Pll
P12
P13
P14
P15

IIgnored
Bit 15
-

0

0

0

0

0

--~'----i

1/0
DECODE

ADDRESS LINES

Figure J - 4.

ADDRESS
SELECT

STCR Byte Execution To TMS 9901

J- 5

TMS 9901

+-5

v

(1)

( 2)

ASSEMBLY LANGUAGE:
LI

R12,>140

TB

-3

ADDRESSING:
R12

I

O

O

O

O O

o

O

1

O

1

0

9901

I

.__~~~~~~~~~~~~~~--'!

ignored----'

TMS

Bit 15
O O O O O O __ is
1

ignored
Displacement
Added to Addr~ss

~ -3

sign extend

pg

PlO
P11
P12
P13
P14
P15

ZEROES--~

I

0

0

0

I

0

0

0

0

0

0

0

1-~

ADDRESS
SELECT

ADDRESS LINES
1/0

(3)

DECODE

STATUS REGISTER:
BIT NO . 0

EQUAL _
BIT

3

15

______,/

NOTE
If a JEQ (jump on equal) instruction follo ws a TB
instruction, a 'I found will cause a jump, and a 0 found
will not cause a jump (1 = EQUAL state).

Figure J-5 .

Test CRU Bit At TMS 9901

J-6

P1
P2
P3
P4
P5
P6
P7
PB

•
(1)

ASSEMBLY LANGUAGE:
LI
SBZ

\'

R12,> 0120
7

PO
Pl
P2
PJ
P4
PS
P6
P7
( 2)

ADDRESS ING:

PS
pg

R12

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

I Ignored
Bit 15

PlO
Pl 1
P12
P13
P14
P15

Ignored---'

I

'

+

0

0

0

+ -.- +7 Displacement

Added to Address
ADDRESS

Sign extend

SELECT

,000,0000

0

0

110
DECODER

0

ZEROES _ ___,

Figure J - 6.

Set CRU Bit At TMS 9901

J- 7

ZERO

APPENDIX K
EXAMPLE PROGRAMS

,
.,

K. 1

MASTERMIND GAME

K. 2

HI-LO GAME

•

APPENDIX K
EXAMPLE PROGRAMS
This appendix contains listings of programs that can be loaded into memory or
reassembled into memory for demonstration or entertainment purposes. These
listings are commented to provide ancillary data and explain the individual
programming techniques. Assembly listing format is as follows:

, - - - - - -ASSEMBLED OBJECT CODE (HEXADECIMAL)

OP CODE MNEMONIC
OPERAND
COMMENT FIELD

1J(l2C'/

FEOO 02EO

·:;TART

FE02 FF 9/:.
(l(l ::o FE04 0200
FE06 OOOA
(lfl3j fE 1:>8 ( 1 4C9
00::::2 FEOA 04C{'i
O(r::3 FEC1C o::·oc

FE1)E
(Jt):3':;

1~

FElO '2F()O
FE1 2 FEr1r.i

s~r

WORKSPACE POINTER

LI

RO, 10

RO~

CLR

n·~

R9 - NO. OF TRIES
R10 = NO . OF TRIES
TMS 9902 CRU ADDR .

CLR R 10
R12,>8C>
L1

oo:::o

00'3'1

U.JPI WSP

7

CtUTPUT OPENING ME·:;::;Af,'";E
XOP @ME'.381 ~ 14

~--F ULL-LINE

MULTIPLIER

OPEN ING MESSr.GE

COMMENT BEGINS WITH ASTERISK

ADDRESS OF LABEL MESS1 IS M.A. FEDA 16

K-1

T~NS

The code can be reassembled and loaded with the L TIBUG comma nd, OP the change
memory command (M) can be used to insert assembled object code at the memory
addresses shown in the listing (beginning at FEoo
program start). The
assembled object code is listed in column 3 of the isting, opposite th e
corresponding memory address in column 2. It is important that the programs be
entered at the addresses noted, or that proper consideration be given t o th e
labelled addresses which have been assembled into absolute addresses relati ve t o
the beginning of the program (address f'E00 16). This consideration is import a nt
when entering the code using the enter memory (M) command with program start not
at address FE00 16.

16 ,

If the code i s to be loaded beginn i ng at an address other than FE00 16 a s a
programstartaddress, i t must berefigured to the new program bias. For example , i f
the program was to be loaded beginning at FC00 16, labelled addresses must be
decreased by 200 16 (FE00 16 - FC00 16 ~ 200 16). Note that jump instructions c r ea t e
a d i splacement va l ue and not a memory address; thus, jump instructions usi ng
labels are not affected by a new program start address.
At the back of each listing is a cross-reference of labels and number of the
s ource statement i n which they are used (column one of the listing contai ns
source statement numbers).
If the Line-By-Line Assembler (LBLA) is used, an absolute address must be
substituted for l abelled addresses. These hexadecimal va lues are in t he fi r st
column of the cross-reference table of labels.

K- 2

K. 1

MASTERMIND GAME

The printout of this game in execution (below) illustrates game rules and
objective. The program generates a five - digit number . To win, you must deduct which
five digits make up the number, and their correct order. Only digits 1 to 8 are
used . After each guess, the program prints the letters X and 0 for each correct
digit entered. In addition, each X indicates a digit is in the correct column . You
are given only 12 tries to win .

r·1Ft:TEPMHW •• GUE·s·s r-HH·mn r-l=l-:3 12 TP.IE ·s

YO U GET X FOP A MATCH, 0 FOP A HIT
1..11111

2 .. 12222
?. • • : : : 1 ·3 ::::: ;:
4 • • 41
4 •• 44144
5 •• 55415
t. • . t.4166
? . . 46177

;:<
0
0
-

- - - - - - --CONTROL-H CAUSES ENTRY TO BE IGNORED, ALLOWS ENTRY REPEAT

;:.m
DO

:.;:,m
ODDO

1. . 11111

3 • • 2 3 3 ~: ·:::

.:-. ...:.O

4 . . 32434

s •• 25353

DOD
:,-: ; -,: =-mo

6 ••

- - - - -- - - - --

- - C R RESTARTS PROGRAM

f1A ~ TEPM ttrn •• GUE:s:s t·jf-it·H·H-J t·j= 1-t: 12 TP I ES

·,·ou GET

~-:

FOP A MATCH, 0 FDR A HIT

1. . 11111

DD
4 .. 32444
5 . • ,3425':!

>::OD
. -- - -- - -- -ESC KEY RETURNS CONTROL TO MONITOR

K-3

.

... . . .

' ,.. ,
I, C ·.· ,

;

( •(;•)1,.
(l(l(•::::

l-

(l(J(l 11

i'

()(1(15

~~

(l(i06
(J ()(l/

-:~

0008

·~

~'

*

000·;1
0011)
( l (l l 1
·~·, ri 12

-.~~
,,

(lt)l "3

~~

1)0 1 ·1

"._

1-1r11 r.;

..::..

l)I)

16
l7
00 1:3

iJ.

( 10

~;.

~i

~

1)1)'2(_i

-!t-

( 1<) j

~~

00::.:· 1

R(I

1~11) .23

( l (H) l

FU

(;1):/·1

r_,oo :~~

FC:

Cl(l2'3
01)2,_:.

1:i(1(i::)

R·:·...
R•1·

(11)27

OOO·l
•)(!( 15

(l(i"2E:

0006

(l(l:29

00Ci7
(H)():'.::

(! 1):;;: ~I

fJ(l(l9

1)(1 ~:~-:-::

OOOA

oo·:::::::

(lt)l) B
t)(H)(

1)1:>34

1yy:::c::;
()()~:1=.,

(l(>f•[I

·-

EO U
EC!IJ
EC:!U
EC!U

El7!1.1

1)04~

"'' I.

_

~·

·'1
r·

'

CONTAINS nsr11

,~.

(':l•tiHE·:::::..

or }" . ·~:

0
~'.

( I .• ·::-

E'UF FE F:

•:,•

r::f'IN[l('ll'1 Ml).

(~F: f-·:t'YY

t :C1J1m · '::.:~:.

L7.0U

r-r.Nr.•u1·1 w'.

>FEOu

{"

~,

·:-EE:T1

1
c:· :;: t•)1; ;
I · {)·~~T 01_11
Hr.f-::r-.1.: I H.; l'l()f-'
i . Ot1D r-·, T M. A. ···1=t(11 )
r.i·::;C(J

c

~:

F'F'. Ct(F [ll_IF;E t 1RE(.\ nF F.XF Cl.IT t1~?.LE CODE
l'-

::::T {\RT

001.l :::: F-EOO 02EO
FE02 FED 1~.
( 11)111.J FEC1 <.'J '.:::F (10
FE 01~. FFOC

>: OP

t~R UL..f. ":. ,

:L ll

PH I l\IT F:l.JLl· ·-:;

MO(l"i

PEO:::: :?FAO
FE OA FF7 ·::-~
(H)/l 7 FE" 01." 011 co

XOF'

(~(: F'l_F '

CLR

Rn

()(14:.:: FE• )E C(1 •1o::-i

MOI/

F·~i

(l(l11 (:.

·:.·:.

FC1l.I
EC!U

+-

*-!'

J.
OO'l2

(if-():::i7

(I(!,~

, •<= , ~1 .11 . ·=· :.r:·::.

r\(.)N [!W1 t•J!'J. ,·11:.:i;:(,y nDDF.::r::::;·::·1-·;

1'\0Rf~

~

N1:1.

E f~!U

FE( •O

00:::: ·~1

~-

r:f':NDCrM t·lt 1.
r;·{'tHDuM f..li).

EC!U

Rl.(,
F:.1. l
Rl.2
.-.
Rt -.

1)(;1j.1)

~'

·-

F C•U
FOi.i
Et)U

R::::
R-=1

{~

4•

0

RS
Rt.
FO

0(1:3:::

~7

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11

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l

F:·· l

~

l _.. 1_,l JE·: .:::£:. ':'..
r=·1J r NT':. 1 (1 F;(·1MU1Jt1 i"'1F'f;-(,y

t_ IJ l.ll'ff·;:..
I

t

f· I

-

r:r.;-:·

! 1i''f:.; TEFM I 1.. Lr

oo·.:.c

.. ·· 1 • 1 -' '\ MI CFr -'' CtrlF'U ., 1::.F:

-.'i

("!-! ':""

F~J.::::

01 -:··:::

FE J ri

c :?r::

r)1f.~/.:.

• 1 : 1 ~ .:::

(1_1

1~E

t r 11 , , T

"-'i 1 i-::.

Ll

(·, .f

pl J F: :.~
~: 3 . :::::·:' 1

t·iC1 1/

F.; ~. r-,· 1 J

MF'Y

FE 1 C ,-,.:; ~ :::
FE 1 E BOf C

·::F'L

[IT c, IT·:.
F ::: . 5

(1B

FL~·,F::::

n.--J r ,·.-·'- •. 1 •
i'.:·u r

l·10l/B E :::· . "-·F' 1 ·r
(
Fl , F: I 1:1
...il.
Mt'; 1 (i

)•.•'.3':1 FE.2(· DC>1 .:·
•:i•:i.-:.1) FE2 ;.· :;:::2::: l
FF.: ·:~·!

I

r t"H·fft1~1M

'• 1: t il.l'3E

1

')•:11;. 1

r-111l 'F 1 o

t1( 1 •··
i)L'(•:~

FE1.2 i)1FD
·.··)~ ::: FE 1 '1
;.::=::~:p
r)(i'3'1 FE 11;. 0:22 ..::

('i(1i:;-

r ,

1

•:11_1-:;2 FE l \:1

onr::•.:.

t 1: .ltlliE

- r OMF't.J rF r:t1Hf10t1

1

(1o)':; 1

1 tcF'-::0

1 i.i

:~. ii •

1--, .1 ''-·l-

i

...

-'":Ori ;".r-·Pt, r

! 7':::1 ~ •:if-' f- t•!L• i_ + LI ·11
'..10 Ut-lfll .:1 Fi: 111

ff

(1(\r~ . ,2

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1::•):=:7
;:11)71 FE.Lrr (1.'! F2
r)(>72 FE:'21:: i:··76 Fc:·:.:2 0'1-Cl

iv.::: ]

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C107 :, rE ;-:~.:: F 1):::· 1
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F:O., Fe::·
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F:-1 , F' l

r=··rr;:

1_11_1n.·1.1

r
r r

r;

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1 ~
1
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11 1 ·:, \",1 ,=. _;= F I
1:1 ( i-. 1

Rl

:= ,-,C-8 F: 1 , FL
JE:.1 ·1
l'l1Y2l)

:=-u r

f'IF: 1

1-1,:.1 E { ': Y i l TI J ,-, ). T ·=.·

P 2 . ·:-..• -;· '

n·.. : T

FE3E -:;:o·::r)
MO.: i

(1(1:::··2
00~-:: :;.:

FE ·1
FE·~

I

•J :2c.2
2 ·20·::1)

1)

n:=:-1 FE'l 11 c-:::o:.?
FE4(:. FEF·1
n..-:1:::::i:; rE11::: ::·F P;.J
FE·1r, FEF2

F'UT

( 1

K- 5

"fi'! F+:J.I !T £!l_WTEF:

r·

T · ·.

MMIND
TXMIR~
036227 ~~
00 : ~5:i8
M0STERMIND FOR THE TM 990/lXX MI CROCOMPUTER

FE ·1 C ( :;;:·t;•c-.01·1'.::;· 1 FC.4 E ( ' i)<17
fV)·~:::.;: F E'::.Cl ,-; .2•)2
• 1

0 ·~1 .:-)

Ff:·:J~.:

*

LI

F:9 , p;:;;
Rl, Rl
H2, lNF·UT

CLF<

F: 1 ·:::

xor

R~.13

MCtl/
MO'.,-'

F~n.NDOM

l\IUME-iEF\ (:DDR

J. ~ i f. ·::

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..

INDEX

f

INDEX
Addition of Displacement and R12 Contents to Drive CHU Bit Address .
Address and Data Buffers •••••••••• •••• • ••••• ••.•••• .••••...••• •• •••
Address Bus ....••.•. . . •..... .. ...••.. • .. . •.....•. • ..• . ......••.•••.
Address Decoding . . ....... . . .. .. ... . ... . ........ . . • •......... . ......
Address Space • . • • . •.•..•.•.••.• . .....•....•.•• ....••.••. •.• ..•.• •••

APPLICATIONS .. ........ ... . . ........... , •... . ........... . .....••..•..
ASCII CODE ........ .. ... . ...... ... ... . .. ......... • . , • . ..............
ASRFLAG Values •. .•..••.. . ....•..... . . . .....• •. ...• • ••. .• .. ••.•• • .•.

Ass em bl er Di rec t i ves Used in Examples • . ••• • • ••••••• • .. • •• • •••••• •••
Auxiliary Co!lllllun ica tions Port ••.••••• . •• • ••• . . . • . • . ... . • . .••.••••••
BINARY, DECIMAL, AND HEXADECIMAL NUMBERING ••••••••••.• • •• ••• .• •••••
Block Compare Subroutine ••••• • •••••.••• • ••.••..• • ••• • • •• ••• • .••• •••
BLWP Example •• ••..•.•••.•..•.• . . .. .... . ..•.• •.. .•.... .... .. • . • . . ••.

Board Character is tics •••. •. •• ••• •• . ..•• . .•• • •••••• . .• • •••.••••• • •••
Board Jump er Positions as Sh ipped •• •.•• ••• • • ••. ••••• ••.•• • • • .. •.•• .
Branch and Link (BL) •• • ••••••••• . ••• • •• • ••.••••••• ••••.••.••.•.•. • •
Branch and Load Workspace Pointer ( BLWP) •••••••••• •••. ••••••••• • • • •
Branch Instructions (B) • .. . • ••••.•••.••••..•.•.•••• •• . . ••••• . •• • •••

Buffer Control ........... . .... . .... .... . . . ....... . .............. .. .
Bus Signals .. .. . . .. ..... .. ..................... ........ ............ .
Cable, 103/113 Data Set • •• ••••••. ••• ••••••.••.••• •. • •••..• •••••••••
Cable, 201 Data Set •..•.•.. . •..•..•.....••.. • ..••••.•..••.• • •••••••
Cable, 202/212 Data Set • •.. • •• •• •••••• .•••. •• •.•.••. •..••.••. ..•.••
Cable Pin Assignments •••••.••••••• ••• •.• • •• • • . • • ••• ... ..• . .•••• • .••

Cable Connections ..... . ....... .. .... ... . .. . . ......... . . . . . ........ .
Central Processing Unit •••.•.•••.•.... . .•• •. .. . •••••. . .. .• •• .•• •• ••
CHASSIS INTERFACE CONNECTOR (Pl) SIGNAL ASSIGNMENTS •• • ••• •• ••••••••
Circuitry to Add TMS 1:1901 Off - Board • •• . •••• ••••. ••••••.• .• •.••••• ••
CLRCRU Signal . .•.. •. . • •..•..•. • •. . • . • .. ....•• ..••.• • .••. ••.. .••.•. .
Coding Example to Ascertain System Configuration Through DIP Switch
Coding Example to Blink L . E. D. On and 0 ff. .... . .. ................ ..
Command Syntax Conventions • . ••• • ••••••••• •• ••. • ••••...••• •. .•••••• •
Communications Register Unit ( CRU) ••••••••••.. • ••••••••••• •• • • • . •. •
Compare Blocks of Bytes Example Subroutine . . . .•••. •• .•• • • • • • ••• •• •.
Connector P2 Connected to RS- 232- C Device (Model 733 ASR) ••.•••.••.
Connector P2 Connected to TTY Device • ••• • •• •.• ••• . ••••••••••••.••.•

Control Buffers ................. ...... . . ... ....... . . . .. . ...... .... .
Control Bus Functions •.•••••••••• . ••. •••••• .•• • •• • • .. ••• •• . •••. • •••

Control Bus . . ..... ... .. . ...... . ...... .. ... ..... ..... .... ... ..... .. .
CPU HOLD and HOLDA Timing • •• •••••••• • •.•••••••••••. .• ..•••••••.• ..•
CRU Addressable LED ••••••••••• •••••.•••••.. •. . •• •••••• •••• • ••••••••
CRU Addressing • .. ......••.• ... •..••..•. . • ....•.•.... .•..... . •...• . •
CRU Bus • .••. • ••..••..•.••••..•.. .. .....••...•..•• • · • • • · • • · · • • • • • · • •

CRU Inspect/Change ( C) • • ••• . •• ••• • • . • ••••.••••••••• •••• •...• •••• .•.
CRU Base and Bit Addresses •• • •••••• •• • ••• . •••••• •••• •••• • •• ••••••.•
CHU Bits I nspected by C Command •• ••• •• •••.••••• . ••••.•••• . •••••••••
CRU INSTRUCTION AND ADDRESSING EXAMPLES USING TMS 9901 ••• •• ••••••••
CRU Instructions •••• ••••••• ••• .• •• .•. ••... •••• • . • . •. • •••..• . •.••• • •
CRU Sel ect .... •.. ... ...... ... ... ...... ... . .. . ................ ... . . . .
CRU Timing .... ... .. ........•.• . ........................ ......... ...
Crystal - Controlled Operation •• •• ••.••• •• • ••. •••••••••••••.••.••••••

Data Buffers ... . ........ . .... . ... .. .. . . . . ...... . . . .. .. .. . .. .. .. .. . .
Data Bus ......... .................... . ........... . ......... . . . .... .
Data Terminal Cable •••••••.••• • • . •. •••••.•• •• • ••. , ••••••. • •• ••••.••

Debug Checklist .......... . .................... ..... ..... . ......... .

INDEX-1

(f) 5-18
6- 30
6- 4
6 - 15
5- 5
Section 8
Appendix c
(T) 5- 60
(T) 5- 1
6- 38
Appendix D
5- 51
( F) 4-30
1- 5
(T) 2-3
5·-7
5- 8
5- 6
6-28
(T) 6-5
(T) 8- 17
(T) 8-18
(T) 8-18
8 - 17
(F) 8-17
6- 8
Appendix H
(F) 8- 4
6- 14
5- 54
(f) 5- 55
(T) 3- 3
5- 10
(F) 5- 51
(F) 2-6
( F) 2- 7
6- 30
(T) 6- 6
6- 6
( F )8 -9
5- 52
5- 13
6- 4
3- 4
(F) 5- 13
( F) 3- 4
Appendix J
5- 14
6-1 9
5 - 14
(F) 6-8
( T) 6- 30
6-4
(T) 8-19
2- 10

I NDEX (CONTINUED)
Decoding Circuitry f or CRU I/O Address es .. . .. . ..... . • . . • • . • • . • . . • . .
Ded ica ted I nterrup t Descri pt i on . • • • . .. . • • •. •• • . • •• . .• • . •.. • •. • . ....
Device Supply Voltage Pi n Ass i gnments •••• •• . .. . . .• •••. . . • . .• . •. • • • .
Di rect Memory Access (OMA) Applications .• . ••. . .•••. . . . • • • . . .• . ..•• .
Di r ect Register Addressing (T = 002) .• . • . •. •. . • .. ... . .•• . •.. . . . .• ..
Direct Regis ter Addressing Example . . . • . . . . . . • . . . . • . . • • • • . . • • . . . • . • .
Direct Memor y Addressing Example . • . •. • ••.• •.. . . . . . . . .. . ... . . . . . . . . .
Direct Memory Addressing , I ndexed Example •• . •. • • .. . • . •. • • . •. • • . • .. .

(F)
(T)
( T)
8- 7
4-8
( F)
(F)
(F)

6- 20
6- 31
6- 3

4- 9
4-12
4-13
DMA Bus Cont r ol . . . .. .. . . • . .• ... • •• . .. . . . . • •••.•• . .• .• •••• • . . . • .• ... (F) 8-8
DMA Con t ro l l e r. . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( F ) 8- 14

DMA Controller Timing .. • .• .. . . • . . • . ..• . • . ••.. . • . • •. .. . . . . . . . ..• . . . •
OMA Device Controller • ... .• . . .. .. . .. . .. . .•... • .• •• •.. .. •.•.. . .•... .
OMA System Biock Diagram . . .... .• • •......• • • ... . .. .. .• .... . .••. . • . .•
OMA System Guidelines . . •... . .... . . . .....• • .• . • .. .• . ...• •. • ..... . ...
OMA System Timing .. . .. . •..• .. . . ... .. . • . . . . • . • . ... . . . .. . .• . ..• .. • . ..
DMA System Timing .. .. . . ... . . . . • • . . . . . • . . • • . . . • . . • . . . • • . . . . . . • . . . . . •
Dump Memory to Cassette /Paper Ta pe (0 ) . ••.• ••• .• .. .. . . . • .. .•. • •... •
Dynamicall y Relocatable Code ••..• . ...• ••. • . •.. . . • • ... . . . . . ...... .• •
Echo Character (XOP 11) •. . .. .. •. .. • . . ...• •.. .•. .• • . .•. . .. . . . . .. . . ..
EIA Inter face . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EIA RS-232- C CABLING .. . . . . . • . . . . . . . . . • • . . . • • • . . . . . . . . . . . . . • • . . . . . • •
EIA Serial Port Applications . •...• . . . • • .. . • • . ••... . .•• • . . ••.. . . ....
Enabling and Tr iggering TMS 990 1 I nter va l Timer ..••. . • . . . . . .• .• . . • .

( F) 8-16
(F) 8-13
(F) 8-13
8- 11
8- 7
( F) 8-10
3-5
5-19
3- 17
6- 35
Appendix B
8-17
(F) 5-31

EPROM Expansion ..•..•.•... . ...... • • . . •.. . .•.•. . . .. .•. . . . . • • .. •..•.. 7 - 1

Example of Code to Run TMS 9901 Interval Timer • .. .. • .•. . .. . •.•.....
Example of Programming Timer Interrupts for TMS 9901 and TMS 9902 •.
Example of Program With Coding Added to Make it Relocatable • . .. . .. .
Example of Separate Programs Joined by Branches to Abs . Addrresses .
Example Program to Converse Through Main/ Aux . TMS 9902 ' s ..•. . . . .. . .
Example Program Using Timer I nterrupts 3 and 4 ..•..•• . . . .. • .• .. ..•.
EXAMPLE PROGRAMS . .• • ••. • .• . • • . . •. . .••. . .••• •. . . .. • .. .• • • ••. • . .. . . • .
Examples of Non Self-Relocating Code/Self - Relocating Code . . .. .. • .. .
Execute Command ( EJ ••• • •• • •• •• • • • • •• • •• ••• ••• • • • • ••• •• •• ••• •••• ••• •
Execute in Single Step Mode (S) .. . .. . ..•. •• ...•.•.••• . . • • . .• . ... . . .
Execute Under Breakpoint (8) •• • •••.• . •• • . • • • ••• • • •• ••• ••• • •. • . •• •••
Executing TM 9'.10/lOOM Pr ograms on the TM 990/ 101M ..... . . .. .• . . . . •.•
Extended Op eration (XOP) . • ••. . . ..... . . •. • .•• ..•.•. . • ••• • . . ... ..... .
External Instruc t ions . . . . . .• . .. . .•... . •• • .• •. . • .• . • .. . . . , .. . .• .. . •.
External Instructions •. . . •..• ... .• ... • .. .. . • .. .. .•... .. .. . •..••....
External System Reset/Load •.. .. .. . . .. ..• •• •. . ..• . .. •. . . .. . .... . .. . .
Extr a RS-232 - C Terminal Port ..• . .• . .. ••• •••• .. . . . • ..•.• • . . .. .•. . • • .
Find Command (F) .• .•. . .• .. ••• .. . .• . .. • • ..• .. . • ... ... ... • . .• . . . . . . . .

Five-Switch DIP and Statu s LED ..... . •.. • •• •. . • .. . •• .. . •• ..... . .....
F'ormat 1 I ns tructions . • . .•• • .. .. .. . . . •. . .. ••.. • .•.. . .. . . . . • . ..... . .
Format 2 Instr uctions . • . •. ...... • . • • .. •• • • •.. • .• . • •.... • .•... .• . . . .
Format 3/9 Ins true tions . . • . • . • • . . • . . . • . • • • . . . . . . . . • . . . . . . . . . . . . . . . .
Format 4 ( C.:RU Multi bit) Ins true tions . • • . • • • . • . . • • • . . . • • . • . . . . . . . • . .
Format 5 (Shift) Instructions . ...• . . . • ..• .... . .. . . • . ..• • . •. .. . • . .••
Format 6 Ins true t ions . . . . . . . • . . • . . . . • • . . • • . . . . • . • • . . . . • • • . . . . . . . . . •
Format 7 ( RTWP, Cont r ol) Ins tr uc t ions •. •... .••.•••. . .• • .• • •..•.. . .. •
Format 8 ( Immediate , I nt ernal Regis t er Load/Stor e) I nstructions . •• •
Format 9 (XOP) I nstruc t ions •.• . • . . .... . •.••. . • •. . . • . • • • ..•. . • • . .•.•
Four Interrupt- Causing Condi tions at TMS 9902 •..• • ..• . . •• • . • • . . . .. .
General Specifications .• . . •. . • . •.•.• . • • ••• • • .. • • • . . . . •. • • ••• • • •.. . .
Gene r al , I n troduction . . • •.. .......• • •. ...• . . . . • ... .. •• • •• • • • . . • • . • •
I NDEX-2

(F) 5- 33
5- 32
(F) 5-19
(F) 5-7
(F) 5- 57
(F) 5-38
Appendix K
(F) 5-20
3-8
3- 12
3- 3
5-3
5-9
6- 14
(T) 6-14
7 - 12
8- 6
3-8
2- 8
4-1 8
4- 20
4- 22
4- 24
4- 25
4- 27
4- 29
4-31
4- 33
(F) 7-8
1- 5
1- 1

INDEX (CONTINUED)

ii

General, Installation and Ope ra tion of the TM 990/101M .•.• • .....• ••
General, TIBUG Interactive Debug Monitor •..•.•...••.•••....•.• .. ••.
General, TM 990/101M Instruction Execution •• • ..•••• ••. •. . ....•..•••
General, Prograrmning. • • . • . . • . . . . . . . • . • . . . • • • • • . • • • • • • . . • • • • • • • . • • • •
General , Theory of Operation •....• • • . .• ..• ••••.••.••• ..• • •••• . . •• ••
General, Options.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General , Applications . •••.•••.•.••..•...•••••. ...• •• •• •.•••• ..•.• ••
Glossary . . • . • • . • . • • . . . . . . • . . • . • . . . • • . • • . . • • • • • • • • . . • . • • • . • • • . • . • . • •
Half- Duplex Mult1drop System • ••. •. ...• ••• • •••• ..••..•••••...••..••.
Half-Duplex Multidrop System •. •..• ...•....•••.. ... •• ••.•.• •. •. ..•..
Hardware Registers . • • . . . • . • . • • . • . • • • . • • • • • • • • • . . • . . • . . . • . • . • . . • . • • •
Hardware Registers •.•.•••.•••..•...•... . . •..... ••• • . ••. . .•..•. . .•. .
Hexadecimal Arithmetic ( H) ..••.•.•••. • • . •••• •• .•• ........•. • •.•.•••
HOLD , HOLDA, and OMA •••. .. . . . .•••. • . . • .•.•• •• ••.• • .•• .. .•• . .•• •.••.
I/0 Using Monitor XOP' s ....... . . . . . • . • . . • • • • • • . • • • • • . . • . . . • . . . . . . • .
Immediate Addressing .•......•••• • •••.••••••.••.•• •. •• .. •..•••.. . ...
Implicit Decoded CRU Bit Addresses.. .. • . . . . . . .. . . . . .. .. . .. .. . . . . • • .
Indirect Register Addressing (T = 01 2 ) ........................ .....
Indirect Register Addressing Example .. . . . • .. .. • . • • .. • .. • .. • . • . • . • ..
Indirect Register Autoincrement Addressing Example . •••.•.•.•..•..••
Indirect Register Autoincrement Addressing (T = 112) .•••••....••••.
Inspect/Change User Workspace (W) •••• •• • •••.• •.. ••.••.. .•• ..... . •.•
Inspect/Change User WP, PC, and ST Registers (R) . ••••..••••.... . ••.
INSTALLATION AND OPERATION OF THE TM 990/101M-1 ••••.• . ... . .•• . .•••
Instruction Description Terms ••••.•• .• •.••••••••••• • .. .•. •. . ••.....
Instruction Formats and Addressing Modes •.•• • ••..•.• • •••••. . •••.•••
Instruction Set, Alphabetical Index .. ..............................
Instruction Set, Numerical Index ••...•..•.•••.. . . . . . .. .. ••. . •...•••
Ins true tions . • • • . • • • • • • • • • . . • • • • • . • • . • • . • • • • • • • • • • • • • • • • • • . • • • . • • • .
Instructions ... . .. . .. .............. . .......... . .. . .. ..... ..........
Interfacing with TIBUG • •.• . •••••••.•......••. • ••• • .•••..••.••••.•.•
Interrupt and User XOP Linking Area . • • • • • • • . • • . . • • . • . . . . • • . . . • . . . . .
Interrupt and XOP Linking Areas •••.••. .• ••• • ••..•••••..•••..•.•.•••
Interrupts and XOP ' s .•••• . •••.••...••.• . .. . • .. . .. . •• .. ...••.•...••.
Interrupt Characteristics .• . •••••.••.••.•• . • ••..••.•••.••• ..• • •.•••
Interrupt Example Program Description. ..... . .......................
Interrupt Sequence • • . •••••••••••••••••••••••••••••••••••••... . . .. .•
Interrupt Structure • . •••.•••• ..•.. .• .• . .. •••••• . ••••••..•.......• • .
INTRODUCTION. . • . . . • . . . . • . . . • • • • . • • • • . . • . • • • • . . . . . • • . . . . . • . . . . . • . • • •
Jumper Pins by Board Dash Number (Factory Installation) • ..• ........
Jumper Placement ... . ........ . . ... ..... ....... ............... . .... ..
LDCR Instruction •••••.•••••••.• •••• •.••••••• . •••• .••.•. • ..... • .. • •.
Line- by- Line Assembler Output ••.••••••••.•••••••••••••....••••.•..•
Linked Li st Example. • . • • . . • • . . • • . • • . . • • . • • • • . . . • . • • • • . . . • • . . • • . . . • .
Linked- Lists ............. . ........................ . . . ........ . .....
Linking Instructions ••••.•••••.•.••••••••.••••.••••••• .• •. . .••• . .••
Load Function ......... .......... . ... .. ... . ....... . .. ........... .. ..
Load Memory From Cassette or Paper Tape (L) •.• • . .••.••• • ••• .• ••••••
Main and Expansion EPROM and RAM ••••• •.•.••.....•.•••..•....•..• .••
Main Communications Port •.••..•...•••.••.•.•..••••....• . •••.•••.•..
Major Components Used in I/O •.••.•• • .•..••.••••.•••• •• •••• • .•••••••
Manual Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Jumper Table •• ••.•.•••••..•.••••••••••• •••..•• ....• ..•• . ••••
Master-Slave Full Duplex Multidrop System •••••...•••••.•••••• ..... •

2- 1
3- 1
4- 1
5- 1
6-1
7-1
8- 1
1-6
(F) 7-11
(T) 7- 11
4- 1
5- 4
3- 9
6- 31
5- 22
4- 13
( T) 6- 25
4-8
( F) 4- 10
(F) 4-10
4- 10
3- 13
3- 11
Section 2
(T) 4-14
4- 7
(T) 4-15
(T) 4- 17
4- 14
4- 31
5- 21
( T) 5-25
5- 24
5- 24
(T) 6- 31
( T) 5- 35
(F) 5- 26
6- 31
Sec ti on
(T) 7- 5
(F) 7 - 2
( F ) 5- 16
(F) 7 - 14
( F ) 5- 11
5-10
5- 6
6-13
3- 9
(F) 1- 5
6-35
(F) 8 - 2
1- 4
(T) 7-4
(F) 7- 10

MEMCYC. • • . • • • • • • . • • • • • • . . • • • • • • • . . • • . • • • . • • • • • . • • • • • • • • . . • • • • • • • • • • 6- 27

INDEX-3

INDEX (CONTINUED)
Memory Address Decode PROM •.•
Memory Address Decoding • .. . ..
Memory and Capacitor Placement •••.
Memory Cycle Timing . . . .
Memory Cycle Timing .••• •
Memory Expansion Maps ..
Memory Inspect/Change, Memory Dump ( M) ••
Memory Map .•••. .•• .
Memory Map Change.
Memory Requirements for TIBUG . .
Memory Timing Signals . ••.•.•.••
Miscellaneous Equipment ••• . .•.•..
Modem (Data Set) Interface Signal Definitions • .
Move Block Following Passing of Parameters . .
Move Block of Bytes Example Subroutine.
Multidrop Cabling • . ..•.... .
Multidrop Interface . •••.•.
Multi drop Interface .•
Multidrop Jumper Tab le .•
Multidrop System ....•. .
Multiple-Device Direct Memory Access Controll er .•
Multidrop Inter face ............... .
OEM Chassis • •..••.............•.••
OEM Chassis Backplane Schematic •..
Off-Board Eight-Bit I/O Port.
Off-Board Memory .•.•..••.•.••
Off- Board RAM ....•
Off-Board TMS 9901
On-Board Device CRU Address.
On-Board Memory Expansion.
Opera ti on .••••••.•••••...•
OPTIONS •...• . .• . .....•..• . •.
Parallel I/O and System Timer .
Parallel I/O Connector •... . •• .
Parallel I/O.
PARTS LIST . . .
Preprogrammed Interrupt and User XOP Trap Vectors •.
Port, 8-Bit 9905/06 .•....•.
Power and Terminal Hookup.
Power Cable/Chassis ..
Power Specifications .•• • •...
Power Supply Connections ..
Power Supply . . . .••. .
Power Supply Hookup.
Power- Up/Reset •.•• •.
Product Index • ••...•...••••••••.
Program Counter (PC) •.•... . • . ...
Program Counter Relative Addressing •.. ••
Program Entry and Exit .•• •• •• .
Program Organization ..••....
Programming Considerations •.••••.••..
Programming Environment •. •..•.•• . ....
Programming Hints •..
PROGRAMMING ••.
RAM Expansion •.

(F) 6-18
6-15
(F) 7-3
8-11
(F) 8-12
( F) 7-6
3-10
(F) 4-2
7-1 2

...

(F) 3-2

...

INDEX-4

.... ..
......

6- 26
2- 2
8-19
5-50
( F) 5-50
( F) 7-9
(F) 6-37
7- 8
( T) 7-10
( F) 7-9
8- 12
6- 37
7-13
(F) 7-17
8-1
( F) 8-3
8-1
8-1
( T) 6-25
7-1
2- 8
Section 7
6- 32
2- 2
6-34
Appendix E
( T) 5-21.1
( F) 8-5
2-2
2-2
6-1
2-3
2-1
( F) 2-4
2-8
1-4
4-1
4-13
5-21
5-3
5- 3
5-4
5- 21
Section 5
7-6

INDEX (CONTINUED )
Random Access Memory •. • .. • • .. .•.. •. .. . .•....
Random Access Memory • •.. . . •. . .. .. ... ...... •.
Read Hexadecimal Word from Terminal (XOP 9).
Read One Character from Terminal (XOP 13) ••
Read-Only Memory • • .. .. ..•
Read-Only Memory . • . • ...
Reading the DIP Switch .
Ready • ••• .•• • . , .••• • .. .

Reference Documents •• • •
Register Reserved Applications . •
Remote Communications ..
Required Equipment .•.•.
Required Use of RAM in Programs •.
Reset and Load Filtering .••• .•
RESET and LOAD Logic ..
Reset Function •. .
Reset/Load Logic.
Return with Workspace Pointer (RTWP) .•
RS-232-C Interface .. .. . .
RS-232-C Port • .. • • • ... . • •
RS-232- C/TTY/Multidrop Interfaces (Main Port, P2) ••
Sample Program 1 . • .
Sample Program 2 ••.
Sample Programs .••.
SCHEMATICS .. • • .• .• •
Serial Communication Interrupt .••
Serial I/O Port EIA Interface.
Serial I/O Port TTY Interface .
Seven-Word Interrupt Linking Area.
Six- Word Interrupt Linking Area ..•
Slow EPROM Table . • .
Slow EPROM • . . •. •••
Software Registers.
Source Listing ..• • •
Status Bits Affected by Instruction •.
Status Indicator . • . . .
Status Register (ST) .
Status Register .•
STCR Instruction .
Symbolic Memory Addressing, Indexed (T = 102).
Symbolic Memory Addressing, Not Indexed (T = 102) .
System Buses . .
System Clock ••
System Structure .
System Timer ••
Tape Tabs ••• .•
Terminal Hookup •. • .
Terminals and Cables •••. .. .. •
Terminal Hookup, 743 KSR •.•• •.
THEORY OF OPERATION • .•• •• •• . .
TI 733 ASR Baud Rate (T) •. •••
TIBUG Commands .••
TIBUG Colllllands •••••
TI BUG Error Messages .•.
TIBUG Error Messages •.
INDEX-5

..... .

(F) 6- 29
6- 28
3- 15
3- 17
(F) 6- 28
6-27
(F) 5-53
6-26
1-6
(T) 5- 6
7- 12
2- 1
5-3
6- 14
(F) 6-13
6- 10
6- 10
5-9
7- 7
(F) 8-6
7- 7
2- 8
2- 10
2- 8
Appendix F
7- 7
( F) 6-35
(F) 6- 36
(F) 5- 29
(F) 5- 27
(T) 7- 7
7- 7
4-4
(F) 5- 2
(T) 4-5
6- 39
4- 2
(F) 4- 3
(F) 5- 17
4-1 1
4-11
6- 4
6- 7
6-4
6- 34
( F) 3- 7
2-5
2- 1
( F) 2- 6
Section 6.
3- 13
( T) 3-1
3-1
(T) 3- 18
3-18

INDEX (CONCLUDED)
TIBUG INTERACTIVE DEBUG MONITOR •••
TM 990 OBJECT CODE FORMAT •••.••
TM 990/101 CRU Map • • ••••.•••••••
TM 990/101M Block Diagram •.•••.
TM 990/101M Board in TM 990/510 Chassis.
TM 990/101M Configurations ..•.•••.••••••••••••••
TM 990/10 1M Dimensions and Component Placement.
TM 990/101M INSTRUCTION EXECUTION ..• •
TM 990/101M Instruction Formats ••••••
TM 990/101M Major Components .••••••••
TM 990/101M Memory Addressing • • •• ••••
TM 990/101M Predefined CHU Addresses ••
TM 990/301 Microterminal ..•••••..
TM 990/301 Microtermioal .
TM 990/301 MICROTERMINAL.
TM 990/402 Line-By-Line Assembler •.••
.
TM 990/510 OEM Chassis •••••••
TMS 9900 CPU Flowchart •..•.•.
TMS 9900 CRU Interface Timing ••
TMS 9900 Data and Address Flow ••
TMS 9900 Memory Bus Timing ••
TMS 9900 Pin Functions ••
TMS 990 1 .••.••.••..••...
TMS 9901 Internal Timer Interrupt Program •••
TTY Interface •••
TTY Inter face •.•
Unit ID DIP- Switch ••. ••••• •••.•
Unit ID Switch ••
Unpacking •••.••.
User Accessible Utilities ••
User Accessible Utilities ••••••••••••••

.. ........ ...

...... .

....

...

User Memory • ••• • .••..••.......•..•. . •... ••. •..••.. .

Using Main and Auxiliary TMS 9902's for 1/0 ••
Vectors (Interrupt and XOP) ••••
Verification •• • •••••.
Wait • . .... •• .

WIRING TELETYPE MODEL 3320/SJE FOR TM 990/10 1M •..
Workspace Example .•..•••.•...••
Workspace Pointer (WP) ••..••.•.
Workspace Registers .•••• • ••.•••
Write Four Hexadecimal Characters to Terminal (XOP 10) •.•••
Write Message to Terminal (XOP 14) ••.•• •••• ••.
Write One Character to Terminal ( XOP 12) ......
Write One Hexadecimal Character to Terminal (XOP 8) •••••

...

....

XOP Example . •••..•.•••••••.••.••••••••••• •••••• •••.•••••.•.••

INDEX-6

Section 3
Appendix G
(T) 6-21
(F) 6- 2
(F) 2-5
( T) 1-4
(F) 1-3
Section 4
(F) 4-7
(F) 1-2
(F) 6-16
(T) 5- 12
(F) 7-15
7-12
Appendix I
7-12
(F) 7-16
(F) 6-12
(F) 5-15
(F) 6-11
(F) 6-26
( F) 6-9
(F) 6-33
5-30
6-36
7-7
5-52
6-39
2- 2
3-14
( T) 3-14
4-1
5- 52
5-5
2- 8
6-27
Appendix A
( F) 4-6
4-2
5-6
3-1 6
3-17

3-17
3- 15
(F) 4-35

T M 990/ 101 1\1 MI CROCOMPUTER
USER RESPONSE SHEET

It 1s O\Jr desire to provide our customers wi th the besr documentation possible. After using this manual. please
complete this sheet and mail it. postpaid, to us. Your comments wilt be given every consideration.
1.

Is the manual well organized? Yes _ _ _ No ___ Comments : - - - - - - - - -- - - - - - --

2.

Is text clearly presented and adequately illustrated? Yes _

No

Comments: _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ __ _ __ _

3.

What subject matter could be expanded or clanfied? __

4.

Is the instruction set adequately covered? Yes _ _ No _ __

Comments: --~

5.

Do you wish more data that would clarify an instruction? Yes ___

No _ __

Comments :---------------------~

6.

Do you wish more data to ciJrify an application? Yes _ _ _ No _ _ __

Comments: - - - -- - - - - -

7.

Please explain the application intended for your board :

School Course _ _ __

Home _ __

Evaluation _ _ __

OEM Application _ _ __

Other _ _ __

If OEM Application, please describe: - - - - -- - - - - - - - - - - - - - - - - - - - - - - - --

8.

Other comments concerning the TM 990/ 101M and this manual : - -- - - - - - -- - - - - - - -

Name : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
Address _ _ _ _ _ _ _ _ _ _ _ _.. _ _ _ _ _ _ _ __

State _ _ _ _ _ __ _

ZIP _ _ __ _

School (if applicable) _ _ _ _ _ _ _ _ _ _ _ _ __ _

Major - - - - - - - --

Year _ _ _ _ __

REV . D

FOLD

FIRST CLASS

Permit No. 6189
Houston, Texas

BUSINESS AEPL V MAIL

No postage necessary 11 mailed 1n the United States

Poet- -

be peld by

TEXAS INSTRUMENTS INCORPORATED
SEMICONDUCTOR GROUP
P.O. BOX 1443

HOUSTON, TEXAS 77001

ATTENTION: MICROCOMPUTER PRODUCTS DEPARTMENT

MIS 6750, COMMERCE PARK
FOl.O

-,

•

..

..

~TEXAS INSTRUMENTS
~

MP337 REV. D
1602001-9701

INCORPORATEO

Semiconductor Group
Post Office Box 1443 Houston, Texas 77001

Prlnted In U.S.A.



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Title                           : TM990/100M Users Guide Mar80
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Subject                         : 1602001-9701 TI TM990/101M
Page Count                      : 322