162G_System_Support_1_User_Manual_Nov81 162G System Support 1 User Manual Nov81

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162G_System_Support_1_User_Manual_Nov81 162G_System_Support_1_User_Manual_Nov81

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TABLE OF CONTENTS

HOW TO CONFIGURE YOUR SYSTEM SUPPORT 1 IN UNDER 5 MINUTES,
WITHOUT READING THE MANUAL
• • ••
Other options and jumpers • • • • •
Important note about system memory

5
6
6

ABOUT SYSTEM SUPPORT
Technical overview •

7
7

CONFIGURING THE SYSTEM SUPPORT 1
Setting I/O address
Setting memory address • •
Other memory options •
• • • • • • • •
Disabling the memory • •
Global/extended address selection
Phantom* response options • • • •
Battery back-up for CMOS RAM • •
Wait states

•••••••••••

9
9
10
11

11
11

12
12
12

Using higher speed 9511A or 9512 •
Interrupt jumpers and options
Using a 9511 or 9512 with interrupts
Interval timer options • • • • • • •
Configuring the serial channel • • • •
Other miscellaneous hardware options
Connecting the battery • • • •
Mounting the battery holder
Replacing the battery
• • • • •
I/O port map • • • • • • • •

15
15
16
17
18
18
18
19

PROGRAMMING CONSIDERATIONS FOR THE SYSTEM SUPPORT 1
Power-up initialization
• • • •
Programming the serial channel
UART initialization • • • • • • • • • •
Sample UART program • • • • •
Programming the real time clock
• • • •
Clock programming sequence • • • •
Sample clock program • • • • • •
• • • •
Programming the interrupt controllers
Important note about using DDT to debug interrupts
"INTEL 8259A Programmable Interrupt Controller".
Initializing the 8259A • • • • • • • • • • •
Routine for initializing master/slave 8259As
Disabling the 8259As • • • • • • • • • • • •
Programming the interval timer. • • • • •
• ••••
"INTEL 8253/8253-5 Programmable Interval Timer".
Programming the 9511 or 9512 math processor
••••
"INTEL 8231 Arithmetic Processing Unit"
"INTEL 8232 Floating Point Processing Unit"

20
20
20
25
25
26
28
29
35
35
36
56
56
57
58
59
66
69
75

13
13

3

.. . . . . . . . . . . . .. .. . . .....
. . ". . . . . . . .

THEORY OF OPERATION -:
Address dE!code .' ••
ROM/RAM Citcuitry
Interrupt controllers
Interval timer • •
Serial channel • • • • •
Math chip

Real-time clock/caiendar •
Power~fail driver
Wait state generator,
Data bus •
HARDWARE SECTION
Parts list • • •
Component layout
Logic diagram
INDEX

• • • • •

••••••••••••••••

• • • •
• • • •

• • • • • • • • • • •••
• • • • •
• • • •

8~

84
84
86'
86
86
87
87
87
88
89
89
90
91

.

.. . . .

• • • • • • • • • • • .' • • • • • • • • • • • • • • •

CUSTOMER SERVICE/LIMITED WARRANTY INFORMATION

83

• • • • • • •

95
96

-------------------------- DISCLAIMER -------------------------Godbout Electronics makes no representations or warranties with
respect to the contents hereof and specifically disclaims any
implied warranties of merchantability or fitness for any
particular purpose. Further, Godbout Electronics reserves the
right to 'revise this publication and to make any changes from
time to time in the content hereof without obligation of Godbout
Electronics
______ M________________________________
to notify any person of such
~ ______________
revision or changes.
_________ _
This document was proofread with the aid of SpellGuard
from ISA, Menlo Park, CA.

4

TM

.;,.,

' '

HOW TO COllll'IG1J1lK YOUR SystEM SUPPOKr I
IN UNDER 5 MINUTES, WITHOUT READING THE MANUAL

This section is for those of you that can't wait long enough to read the
manual t~ find out i f your System Support I board works. I I STRONGLY RECOMMEND
THAT !Q!LRELAx, AND READ THE MANUAL!!! If, after reading and following the
directions in this section, your board appears not to function, DON'T CALL!!!
READ THE MANUAL FIRST!!!
SWITCHES
DIP SWITCH 1 - is located near the right hand edge of the PC board and is used
to select the number of wait states, and various memory options.
;position
1
2
3
4

Labeled
W8
W4
W2
Wl

5

RDI

6

XA

7
8

PHD
PHE

How to Set It
OFF
OFF
OFF
ON i f you have a 4 MHz or greater CPU,
otherwise, OFF.
OFF if you are using the RAM/ROM,
ON otherwise.
ON i f you are not using extended
addressing, OFF otherwise.
ON
OFF

DIP SWITCH 2 - is located between U32 and U33 and is used to set the extended
address that the ROM/RAM responds to. If you are not using extended addressing
or the ROM/RAM then turn all switch positions of Dip Switch 2 OFF. Otherwise
they are set according to the following table:
Position
1
2
3
4
5
6
7
8

Address Bit
A23
A22
A21
A20
Al9
Al8
A17
Al6

·· · · ·· · · ··
·· · · ·· ··· ··· ·· ··
· · · · ·· · · ·
· ·· · ·· ·· ··

·

ON
OFF

"0"

"I"

DIP SWITCH 3 - is located between U35 and U36 and is used to set the address of
the I/O.ports and the ROM/RAM. Positions I through 4 are used to set the
ROM/RAM address. If you are not using the ROM/RAM·. then turn positions 1 through
4 OFF.
If you are. using the ROM/RAM then they· are set. according to the
following table:
.
.
.
Position
Address Bit
1
• • • • • A15
2 • • • • •
Al4
• Al3
3 • • • • •
4 •
• • • • • A12

••.• 1.

ON
OFF

"0"

= "I"

5

Positions 5 through 8 are used to set the address of the I/O ports. To set
them for the CompuPro standard (block of ports at 50 hex) then set the switches
as shown in the following table:
Position
5

How to Set It
• ON

6
7 •

• • • • OFF

8 •

OFF

ON

OTHER OPTIONS AND JUMPERS

Insert a dip shunt in locations J2 and J8. J2 is located at the top of the
board between the serial connector and U2. J8 is located at the bottom left-.
hand side of the board between U30 and U31.
Connect the battery cable by plugging it onto J3 (which is located near the
top right-hand side of the board just to the right of the regulator). The
connector is polarized but make sure the red wire is towards the left.
If you are using the System Support 1 with our CPU 8085/88 board or any
other 8085/8088/8086 type board, then install the shorting plug at jumper J13 so
that the pins labeled "8" and "c" are connected together (shorting plug will be
left of center).
If you are using the System Support 1 with our CPU Z or any other Z-80 or
8080 type CPU board (like an old 1M SAl CPU), then install the shorting plug at
jumper J13 so that the pins labeled "z" and "c" are connected together (shorting
plug will be right of center).
J13 is located at the bottom right hand corner of the PC board.
IMPORTANT NOTE ABOUT SYSTEM MEMORY

When using the System Support 1 with its on-board interrupt controllers, and
you are using an 8080 or Z-80 CPU, it is important that all your system memory
respond (become disabled) to the S-100 PHANTOM* signal which is on bus pin 67.
Therefore you must configure all your system memory to respond to PHANTOM*.

6

ABOUT THE SYSTEM SUPPORT 1
Congratulations on your purchase of the System Support 1 board - a multifunction module designed specifically for full electrical and mechanical
compatibility with the IEEE 696/S-100 Bus standard.
The S-100 bus is the
professional level choice for commercial, industrial and scientific applications.
This bus provides for ready expansion and modification as the state of
the art improves. We believe that this board, along with the rest of the
CompuPro family, is one of the best boards available for the S-100 Bus.
The System Support 1 board combines many of the most often desired "extras"
in an S-100 computer system. Most of these features don't take up enough board
space to justify an entire board devoted to performing specifically that
function.
For example, if every function that is performed by the System
Support were put on a separate board, it would take up 7 slots! By integrating
all these functions into one multi-function board, we have conserved slots,
power, and cost.
This board provides the system with sophisticated control of bus interrupts,
3 independent interval timers, a "real time" clock/calendar that provides BCD
hours/minutes/seconds /month/day/year with battery backup, a full RS-232 serial
channel which includes full handshaking, space for 4K of RAM or EPROM with
provision for battery back-up for 2K of CMOS RAM, provision for adding a high
performance math processor to increase system throughput, and generation of the
new S-100 signal PWRFAIL*.
No other S-100 board has been so packed with features at such a reasonable
cost as the System Support 1, and that makes it proud to be another member of
the CompuPro family.
Thank you for choosing a CompuPro product •••• welcome to the family of
satisfied computer users.
TECHNICAL OVERVIEW

The System Support 1 provides the system with the following functions:
(1) Two sophisticated LSI interrupt controllers.
These handle the eight
vectored interrupts from the S-100 Bus, as well as 7 interrupts generated onboard. Thus, the on-board interrupt sources do not use up any of the S-100 bus
interrupt pins. The interrupt controllers provide sophisticated control of
interrupt's priority, fully independent masking, and vectors to a service
routine table that may be located virtually anywhere in memory. The interrupt
controllers can function in an 8080/8085/Z-80 enVironment, as well as the
8088/86 environment.
(2) Three independent interval timers.
These are 16 bit counters that can be
written to, read from, and can cause interrupts. They are clocked by a 2 MHz
source, but prOVision has been made to allow external clock inputs, or the
counters may be cascaded for longer counts. A gate input is provided for each
counter to allow timing of external events. The counters can operate in one of
six modes: Interrupt on Terminal Count, Programmable One-Shot, Rate Generator,
Square Wave Generator, Software Triggered Strobe and Hardware Triggered Strobe.
(3) A full RS-232 serial channel.
This serial channel provides features like:
Full modem and handshaking control lines, master/slave jumper options, fully
software programmable UART features such as parity, word length and baud rate,
and provision to run in an interrupt driven mode. The baud rates are crystal
controlled.

7

(4) A real time clock/calendar with battery back"'up. Our real time clock keeps
"real time"; hours, minutes etc. Our clock is not just an interrupt every few
milliseconds that requires processor .overhead to actually keep:track·of the time
and date. (But you could use the int'erval timers ,to.d.o that!) Included ,a:re
features like 12 or 2,4.hour format, hour/minute/second /month/day/year/day-::-ofweek indication, individually accessible digits, BCD format, battery back-::-up
with' a' battery life of more than one year, and crystal controlled time-bas,e.
(5) Sockets for 4K of RAM or EPROM. You can use two 2716 type EPROMs or two of
the new ''byte-wide'' RAMs or one of each. Provision is made to power one of the
sockets from the clock battery if desired for use with theijitachi 611,6 C~OS ,RAM
chip. The power consumption from the battery is so low that the data will be
retained for over one year, and that includes running the clock. 'rhemem.ory
space is addressable on any 4K boundary via a dip-::-switch, and may also~espond
to the full 24 bits of IEEE extended addressing.
The extended address is also
selectable by a dip-switch. The, memory may also respond to the PHANTOM* sign;;!l;
it may appear or disappear:when PHANTOM* is asserted. The, PHANTOM* polarity is
selected by a dip-switch. The memory may be disabled with a dip-switch.
(6) A socket for a 9511A or 9512 LSI math processor. This chip is not provided
with the standard boardsincg the price/performance tradeoff may not be
justified in all systems. But if you really need, the higher system throughput,
the chips are available from us, or you may add your own. In any case, ~he
capability for later expansion is provided, should your need arise.
Provision
has been made for either math chip, whichever you prefer. ,The math, chip can run
in an interrupt driven mode; which allows the math functions to occur in
parallel with other processing on the bus.
The math chips currentiy run at 2
MHz, but provision has been made for an on-board crystal oscillator so that you
can use the faster versions of these chips. Buying a math processor all by
itself on a separate S-100' board usually costs more than the price of an entire
System Support' 1.
(7) Implementation of the 8-100 Bus Signal PWRFAIL*. This signal does not meet
the exact spec as' defined by the new IEEE 696/8-100 Standard,
but is asserted
well before the regulators drop out of regulation. This allows thousands of
instructions to be executed before the system crashes. Couple this with the
battery back-up RAM capability and now you have a useful power-fail system that
will allow you to recover in an orderly fashion.
Provision is made on-board to
jumper the PWRFAIL* line to the NMI*·line.
(8) The System Support 1 takes upa block of 16 I/O ports and is addressable on
any 16 port boundary. Provision is made to generate one, two, four or eight
wait states to 'insure operation with the fastest of processors.
This board was
designed for full compliance with the IEEE .696/S-100 'specifications to insure
complete compatibility for today and the future.
For a more, complete discussion of the actual implementation of these
features, refer to the Theory Of Operation section of this manual.
By now- you : can see 'that the, Systea Support 1 is the perfect addition. to any
S-100 syS'tem, but, when coupled .,w,i,th one .ofour C.PUs, can make a complete sY!;ltem
with 'just two boards 1 ,·Many long hours o,f thought .andrevision went in.to this
pr-oduct, andw'e atCompuProare conf.ident that it will prOvide years of solid
service. We sincerely hope that you will enjoy it.

8

CONFIGURING THE SYSTEM SUPPORT 1
The System Support 1 occupies a group of 16 I/O ports, and 4K of memory
space, if the memory is to be used. The I/O ports can reside on any 16 port
boundary and the memory on any 4K byte boundary. Both addresses are set with
Switch 3.
Switch 3 is located in between U35 and U36 in the lower row of chips and is
marked "ROM/I/O ADDR".
SETTDiG THE I/O ADDRESS

The I/O address is set by Switch 3, positions 5 through 8.
corresponds to a particular address bit:
SWITCH 3

Position
Position
Position
Position

5
6
7
8

·
·

• • •
•
•
• •

Address
Address
Address
Address

Bit
Bit
Bit
Bit

Each switch position

7
6
5
4

When a switch is "ON", that matches a "0" bit on the corresponding address
line. When a switch is "OFF", that matches a "1" bit on the corresponding
address line.
The following table shows all possible I/O addresses that the System Support 1
can reside at, and the associated switch settings.
SWITCH 3
5

I/O Address

Switch Position
6
7

8

------------------------------------------------------00 (hex)
10

-')

20
30
40
50
60
70
80
90
AO
BO
CO
DO
EO
FO

·
·
·

·
···

·
··
·
··

· ·· ···
·
·
·
···
· · ··

-ON-ON-ON-ON-ON-ON-ON-ON-OFF-OFF-OFF-OFF-OFF-OFF-OFF-OFF-

-ON-ON-ON-ON-OFF-OFF-OFF-OFF
-ON-ON-ON-ON-OFF-OFF-OFF-OFF-

-ON-ON-OFF-OFF-ON-ON-OFF-OFF-ON-ON-OFF-OFF-ON-ON-OFF-OFF-

-ON-OFF-ON-OFF-ON-OFF- <-ON-OFF-ON-OFF-ON-OFF-ON-OFF-ON-OFF-

The "standard" port block that we have assigned to the System Support 1 is
the block at 50 hex. All of the software provided by CompuPro and other vendors
will assume that you have the board addressed to this block. To set the System
Support 1 to block 50 hex, set switch positions 5=ON, 6=OFF, 7=ON, and 8=OFF.

9

SETTING THE MEMORY ADDRESS
The System Support 1 has a 4K block of EPROM or RAM. This memory may reside
at any 4K byte boundary in the system. The address of the block is set by two
switches: part of Switch 3 and all of Switch 2. Switch 3 is used to set which
block in the 64K "page" that the memory uses, and Switch 2 is used to select
which of the 256 possible 64K "pages" (corresponding to the new address lines
A16-23) is to be used.
The 4K block address within the 64K page is set by Switch 3, positions 1
through 4. Switch 3 is located in between U35 and U36 in the lower row of chips
and is marked ''ROM/I/O ADDR".
Each of the four switch positions correspond to a particular address bit:
SWITCH 3

Position
Position
Position
Position

1
2
3
4

Address Bit 15
· Address
Bit 14
. . . . . · Address Bit
13
. . . · Address Bit 12

.

When a switch is "ON", that matches a "0" bit on the corresponding address
line.
When a switch is "OFF", that matches a "1" bit on the corresponding
address line.
The following table shows all possible 4K byte boundaries that the memory may
start at, and the associated switch settings:
SWITCH 3
Switch Position
Memory Address
0000 (hex)
1000
2000
3000
4000
5000
6000
7000
8000
9000
AOOO
BOOO
COOO
DOOO
EOOO
FOOO

··
·
·
·

~

·
··
··
··
··

· ··
·· . . · ··
··
· · ··
·
·· · ··

1

2

3

4

-ON-ON-ON-ON-ON-ON-ON-ON-OFF-OFF-OFF-OFF-OFF-OFF-OFF-OFF-

-ON-ON-ON-ON-OFF-OFF-OFF-OFF
-ON-ON-ON-ON-OFF-OFF-OFF-OFF-

-ON-ON-OFF-OFF-ON-ON-OFF-OFF-ON-ON-OFF-OFF-ON-ON-OFF-OFF-

-ON-OFF-ON-OFF-ON-OFF-ON-OFF-ON-OFF-ON-OFF-ON-OFF-ON-OFF-

~

NOTE: U 16 occupies the upper 2K of the 4K address space and U 17 occupies the
lower 2K of address space. For example, if the memory were addressed at FOOO
hex then U17would reside at FOOO to F7FF and U16 would reside at F800 to FFFF.

- ....- . - - - - . - - - - - - - - - - - - - c - - - - - - - - - - - - - - - - - - - -..- - - - - - - - - - -

The "extended address" that the memory responds to is set with Switch 2.
Switch 2 is located between U32 and U33 in the lower row of chips.
Each switch position corresponds to a particular address bit (see following):

10

SWITCH 2

.Position
Position
Position
Position
Position
Position
Position
Position

1
2
3

·
·

4
5

6
7
8

··

··
. . . ·· ··

Address
Address
Address
Address
Address
Address
Address
Address

Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit

23
22
21
20
-l9

18
17
16

When a switch is "ON", that matches a "0" bit on the corresponding address
line. When a switch is "OFF", that matches a "1" on the corresponding address
line.
If you don't want the memory to respond to the extended address bits, see
the section below on "Global/Extended Address Selec~ion".
OTHER MEMORY OPTIONS

Most of the other memory options are selected with part of Switch 1.
1 is located just to the right of U22.

Switch

First is a quick chart of the memory options associated with Switch 1, then
we will give you a more detailed description of each of the switch's functions.
SWITCH 1 -

Switch
Position

Labeled

5
6
7
8

RDI
XA
PHD
PHE

Function
ON
ON
ON
ON

to
to
to
to

disable memory.
disable extended addressing.
allow PHANTOM* to disable memory.
allow PHANTOM* to enable memory.

DISABLING THE MEMORY
Position 5 of Switch 1 is used to entirely disable the memory space on the
System Support 1. This will mainly be used if you don't wish to use any onboard memory at all.
To disable the on-board memory entirely, turn position 5 of Switch 1 ON. If
you don't want the on-board memory space to be disabled (if you're going to use
some kind of memory), turn position 5 of Switch 1 OFF.
GLOBAL/EXTENDED ADDRESS SELECTION
Position 6 of Switch 1 is used to determine whether or not the memory
responds to the lower 16 address bits and ignores the upper 8 address bits, or
responds to the entire 24 address bits.
When the memory ignores the upper 8 address bits, it will appear in each 64K
page. This is called "global" memory. If you have a processor card that is only
capable of generating 16 address bits, then you will want to use the memory as
globaL
If you want the memory to respond to the full 24 address bits, turn position
6 of switch 1 OFF. If you want the memory to be global, then turn position 6 of
Switch 1 ON.
Note that if you want the memory to respond to the extended address, you
will have to set Switch 2 to the proper extended address. See the above section
"Setting the Memory Address" for information on how to set Switch 2.

11

PHANTOM* RESPONSE OPTIONS
Positions 7 and a are used to determine how the memory on the System Support
1 responds to the S-100 Bus signal PHANTOM*. The memory can respond in one .of
three ways when PHANTOM* is asserted on the bus. The memory may ignore the
PHANTOM* signal entirely, may become disabled or may become enabled.
If you want the memory to ignore the PHANTOM* signal, leave both position 7
and position a of Switch 1 OFF.
If you want the memory to become disabled (disappear) when PHANTOM* is
asserted, then turn position 7 ON and position a OFF. Th~~_~~~e mo~oft:.n
desired setting.
--rf-you-wiint the memory to be enabled only when PHANTOM* is asserted, then
turn position 7 OFF and position a ON.
NEVER turn both positions 7 and a ON at the same time!
BATTERY BACK-UP FOR CMOS RAM
If you are using the Hitachi HM6116 CMOS RAM chip in location U17 and wish
to have it powered by the clock ba t tery on power-down, then you will need to
install a 1N914 type diode at location D3, (just below U4 and US near the top of
the board).
If you obtained the HM6116 from us, we have provided the diode along with
the RAM chip. Be sure to install the diode with the banded end facing towards
the left. Take care not to create any solder bridges between adjacent traces
when soldering in the diode, and use a temperature controlled soldering iron (or
be sure it's less than 40 watts).
If you ever decide to use an EPROM in that socket, be sure to remove the
diode, otherwise the clock battery will be drained excessively (and who needs to
battery back-up an EPROM?). If you wish to use the RAM in that location but
don't care whether its contents are retained on power-down, then you may leave
the diode out and reduce the current drain on the clock battery.
WAIT STATES
The Systea Support 1 has circuitry that enables it to generate one, two,
four or eight wait states. This will mostly be used in systems where the
processor is running at a very high speed. In this industry it has always been
the case that the speed of the CPU chips increases years before the speed of the
LSI peripheral chips. Since th~ System Support 1 makes extensive use of these
LSI peripheral chip_, it may be necessary to add wait states to aLl accesses
. made to the board.
Part of Switch S1 is used to add wait states to all accesses made to the
board. S1 is located just to the right of U22 at the right hand edge of the
board. Positions 1 through 4 of S1 are used to select the number of wait states
to be generated according to the following table:
Number of
Wait States
None
1
2
4
a

1 (Wa)
-OFF-OFF-OFF...,OFF-ON-

Switch Position
2(W4)
3(W2)
-OFF-OFF-OFF-OFF-OFF-ON...,ON-ON-ON-ON-

4(W1 )
-OFF-ON-ON...,ON-ON-

NOTE: These wait states affect the entire board, 1/0 ports and memory accesses.

12

USING A HIGHER SPEED 9511A OR 9512
As supplied, the System Support 1 is designed to use either a 9511A or 9512
math processor chip running at 2 MHz. This is the lowest cost version of these
" chips. The 2 MHz clock is taken from 5-100 Bus pin 49 'which is sp.ecified by the
S-100 Standard to be a 2 MHz clock signal.
But we have made a provision for using an on-board crystal oscillator
instead of the 2 MHz signal from the S-100 Bus. This was done primarily for two
reasons: .
1. Some users may desire to use the higher speed (3 and 4 MHz) versions
of the 9511A or 9512.
2. Some of the older S-100 systems may not have the 2 MHz clock signal
available on pin 49.
If your requirements fit a~y of the above, then you will want to install the
. extra crystal required for theon-board oscillator.
This is crystal Xl and is located just to the right of U11 at the left-hand
edge of the board. Note that this crysta·l should be twice the frequency that
you require. If you are using a standard speed 9511A or 9512 (2 MHz) but there
is no 2 MHz' clock on pin 49, then Xl should be a 4 MHz crystal.
If you are
using a 3 MHz 951lA or 9512 then Xl should be 6 MHz. I f you are using a 4 MHz
version then Xl should be 8 MHz. A proper crystal is available from CompuPro.
Be sure t·o specify a frequency of twice the operating speed of your math. chip.
You will also need to install a jumper at location J5 (located upwards and
to the right of Xl) and also cut a trace at J5. If you are using the on-board
oscillator option, then you must cut the trace connecting the two pads in the
"B" block of J5. This trace is located on the back (solder) side of the PC
board. Use an XACTO knife and be extremely careful· not to damage any other
traces.
Then you will need to install a jumper between the two pads in the "A"
block of J5.
If you are not using a higher speed 9511A or 9512, or you have 2 MHz.on pin
49 in your system, or if you are not using a math processor at all, then do
nothing with J5 or install no crystal at Xl.
INTERRUPT JUMPERS AND OPTIONS
IHPORTABT NOTE ABOUT USING THE Oli-BOARD INTERRUPT COIiTROLLERS: The System
Support l's interrupt system has been designed to work with 8080/8085/Z-80/8088
CPUs. In order to account for an idiosyncracy in the 8080 and Z-80 CPUs, the
interrupt circuitry asserts the S-100 bus signal PHANTOM* which is on bus pin
67. Therefore it is necessary to configure all your system memory to be disabled when PHANTOM* is asserted (if you are using a Z-80 or 80.80 CPU). For a
discussion about why this is necessary, see the Theory of Operation section of
this manual. Note that the memory on the System Support 1 will always be
disabled when the interrupt circuitry requires, regardless of how you have set
the PHD and PHE switches.
JUMPER J13 - is located at the lower right hand corner of the PC board, and it
is used to select how the System Support 1 treats interrupt acknowledge cycles
depending on what type of CPU you are running.
If you are using the System Support 1 with· our CPU 8085/88 board or any
other 8085/8088/8086 type board, then install the shorting plug at J13 so that
the pins labeled "8" and "c" are connected together (shorting plug is left of
center).

13

If you are using the System Support 1 with our CPU Z or any other Z-80 or
8080 type of CPU (such as an old IMSAI CPU), then install the shorting plug at
J13 so that the pins labeled "z" and "c" are connect:ed together (shorting plug
is right of center).
The interrupt structure of the System Support 1 has been designed to be both
easy to use and at the same time very flexible.
There are two interrupt
controllers on the board; one is the "master" and the other is the "slave". The
two interrupt controllers look at 15 different interrupt sources. Eight of
these come from the S-100 Vectored Interrupt lines and seven interrupts may be
generated from various sources on the board itself.
In general, the master interrupt controller's "interrupt request" inputs
have a higher priority than those of the slave interrupt controller. The master
looks at seven of the S-100 Bus Vectored Interrupts (VIO-6*) and the slave looks
at the eighth vectored interrupt and seven interrupt sources that are generated
on the System Support 1. This is the "standard" ·configuration, but through the
use of dip headers and jumpers, almost any configuration is possible. For
example, if an interrupt controller already exists in your system, the on-board
interrupts may be jumpered to any of the S-100 vectored interrupt lines. This
means that the interrupting capability of the various board functions are not
lost even though you are not using the on-board interrupt controllers. Or some
interrupts may be handled on board and some off board, or an on-board interrupt
may be given a higher priority by jumpering it to an S-100 interrupt line which
is responded to by the master.
To allow the System Support 1 to be easily configured, a "standard" set of
interrupt assignments may be selected by merely plugging in a dip-shunt in one
location, (J8), and leaving J7 open.
If you- don't want a standard configuration, you may custom program these jumper areas with dip-headers instead of the
shunts. If the shunt is plugged into location J8 and location J7 is left open
then the board's interrupt configuration, (see the following figure):

S-100
Vectored
Interrupts

VIO*
VIl*
VI2*
VI3*
VI4*
VI5*
VI6*
VI7*

>------IIRQ
>------IIRQ
>------IIRQ
>------IIRQ
>------IIRQ
>------IIRQ
>------IIRQ
>--1 I-IIRQ

OINT
1
2
3
4
5·
6
7

1---->S-100 INT* line.
1
1
1
8259AMASTER
(U15 )
1
1
1
1

1 1 -------------1 1

On-Board
1 1-------1 <----slave interrupt output
Interrupts
1
1
I---IIRQO
TIMERO OUT>------IIRQl
TIMERI OUT>------IIRQ2
TIMER2 OUT>------IIRQ3
8259A SLAVE
9511 SVRQ >------IIRQ4
(U14 )
9511 END >------IIRQ5
2651 TxRDY>------IIRQ6
2651 RxRDY>------IIRQ7

14

If you wish to "scramble-wire" the interrupts, all interrupt sources and
destinations appear at jumpers J7 and J8. They may be jumpered in any conceivable configuration by using dip-headers. The interrupts appear at these jumpers
as shown in the following diagrams:
Sources

Destinations
J7

9512 ERROR>------116
9511 END >------115
9511 SVRQ >------114
TlMER20UT>------113
TIMER1 OUT>------112
TlMERO OUT>------111
2651 TxRDy>------110
2651 RxRDy>------19

11----->S-100
21----->S-100
31----->S-100
41----->S-100
51----->S-100
61----->S-1.00
71----->S-100
81----->S-100

VI7*
VI6*
VI5*
VI4*
VI3*
VI2*
VI1*
VIO*

91----->SLAVE
101----->SLAVE
111----->SLAVE
121----->SLAVE
131----->SLAVE
141----->SLAVE
151----->SLAVE
161----->SLAVE

IRQO
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7

J8
S-100 VI7*>------18
TlMERO OUT>------17
TIMER1 OUT>------16
TlMER2 OUT>------15
9512 SVRQ >------14
9512 END >------13
2651 TxRDy>------12
2651 RxRDy>------11

USING A 9511 OR 9512 WITH INTERRUPTS
The "END" interrupt from the 9511 or 9512 is not actually connected directly
to J7 and J8 as is shown above. This is because the polarity of the END signal
is different between the 9511 and the 9512. J6 is used to select the appropriate polarity for this signal depending on which math processor you are USing.
If you are using a 9511A then install a jumper in the "A" block at J6. If
you are using a 9512 then install a jumper in the "B" block at J6.
If you are using either math chip but are not running it "interrupt driven",
then you do not need to install any jumper at J6.
Also note that the "ERROR" output from the 9512 (9511A does not have this
output) is not available at both J7 and J8 as the other math chip outputs are.
The ERROR signal is only available at J7.
INTERVAL TIMER OPTIONS
The three interval timers on the System Support 1 ar~ implemented with an
8253 Ie. It contains three independent timer sections. Each section has a clock
input, gate input and timer output. These 9 inputs and outputs appear at J4 so
that the different sections may be cascaded for longer time delays or so that

15

the signals may be connected to external devices.
the connections at J4:
J4

The fbllowing diagram shows

INVERTED TIMER 0 OUTPUT<-----
1
161----~------>TIMER 0 OUTPUT
INVERTED TIMER 1 OUTPUT<-----12
151---~------->TIMER 1 OUTPUT
INVERTED TIMER 2 OUTPUT<-----13
141----------->TIMER 2 OUTPUT
TIMER 0 CLOCK INPUT>-----.... ~--14------131-------------<2 MHz SOURCE
TIMER 1 CLOCK INPUT>-----~---15------121-------------<2 MHz SOURCE
TIMER 2 CLOCK INPUT>---------16------11 1---:"'---------<2 MHz SOURCE
TIMER 0 GATE INPUT>----------17
101-------------NO CONNECTION
TIMER 1 GATE INPUT>--------~-18
91-------------11
161------13
RxD<------12
151------12
RTS>------13
141------15
26 Pin Transition Connector
CTS<------14
131------14 I
and 25 Pin DB-25 Connector
DSR<------15
121------1201
DTR>------16
111------16 I
DCD<------17
101------18 I
+12 V------18
9 1-- I
11 I------GND
------I
17 I------GND

I

~12V-----------------1

TxD
RTS
DSR
DCD

= Transmitted

Data
Request To Send
Data Set Ready
Data Carrier Detect

RxD
CTS
DTR
GND

= Received

Data
Clear To Send
Data Terminal Ready
Ground

DIAGRAM OF J2-J1-SERIAL SIGNAL RELATIONSHIPS
Setting the baud rate, stop bits, parity and other UART parameters is done
in software and will be covered in a later section called "Programming The
Serial Channel".
OTIIER. MlSCKJ..LAflEOUS BARDIlAJlE OPTIONS

Use of pSTVAL* - The System Support 1 uses the new S-100 Signal pSTVAL* that
appears on S-100 Bus pin 25.
If you are using a CPU from CompuPro (or any
other CPU that meets the IEEE/696 standard), then this signal will be generated
by the CPU and you need not worry about this next jumper.
If you are using an older generation CPU board that does not generate
pSTVAL*, then you will need to make a small modification to the System Support
1. Proceed as follows:
Locate J11. It is located near the edge connector in approximately the
center of the board. J11 has three pads labeled A, C and B. If you look on the
back (solder) side of the board you will notice that there is a small trace
connecting pad B to pad C. Using an XACTO knife, carefully cut this trace.
Take care not to damage any other traces on the PC board. Then install a jumper
between pads A and C. That completes this modification.
Use of SLAVE CLll* Instead of RESET* - The S-100 signal SLAVE CLR* (bus pin 54)
is specifically designated for clearing slave devices (the System Support 1 is a
slave device). However, it is usually more convenient in most systems to use
RESET* instead of SLAVE CLR*. The System Support 1 is currently wired to use
RESET* to clear the various circuits on the board. Provision has been made to
use SLAVE CLR* instead of RESET* if you so desire.
To do this, locate J9 and J12. J9 is a single jumper pad located at the
bottom left-hand corner of the board just above the edge connector fingers. J12
is also located at the bottom of the board just above the edge connector

17

fingers, but near the center of the board.
J12 has two pads that are connected
together by a trace on the back (solder) side of the board. This trace must be
cut with anXACTO knife. Be sure not to damage any other traces. Then, using a
length of insulated wire (such as wire-wrap wire), install a jumper between the
pad of J9 and the left'-most pad of J12 (the one closest to the "C"). This will
cause the circuitry on the board to be cleared in response to POC* and 8LAVE
CLR*.

PVH.FAIL* and BHI* - .The System Support 1 generates the 8-100 PWRFAIL* signal
which is used to indicate that a loss of power is. imminent. You will usually
want this signal to cause a non-maskable interrupt (NMI*) to the CPU.
The CPU
can then save any data it deems relevant. Provision has been made to jumper the
PWRFAIL* signal to the NMI* line on the 8-100 Bus. Thus both PWRFAIL~ andNMI*
would be asserted low about 15 milliseconds before the regulators in the system
drift out of regulation. (The exact time will depend on your system's power
supply and loading.)
If you desire to have the PWRFAIL* signal cause an NMI*, then install a
jumper at location J10. J10 is located at the bottom left hand side of the
board, just above the edge .connector fingers.
If you don't care about the
PWRFAIL* signal, then you need not do anything with J 10.
As an option,the PWRFAIL* signal is available at the right-most pad of JiO.
It could conceivably be hooked to any other 8-100 interrupt pin via a header at
J7. It should be mentioned, however, that this would not bea good practice
because any of the other interrupts could be "masked" at the time of power
failure, thus defeating the purpose of the PWRFAIL* signal.
CONNECTING THE BATTERY
The battery connector supplied with the System Support 1 is semi-polarized
so that it should only plug onto J3 easily in one direction. To double check,
the red wire which connects to the + side of the battery should correspond to
the + marking on the board.
If you .desire to use a different battery than the one supplied (for example
three 1.5 volt penlight cells in series for longer battery life) then you should
take care to keep the polarities correct. The circuitry on the System Support 1
is protected from reverse polarity so no damage will occur if the battery is
reversed, but the board won~t function properly.
The battery is shipped already plugged into its holder, but should it become
necessary to remove it, be sure to orient the + end of the .battery to correspond
to the + stamped in battery holder.
HOUIiiITDfG THE BATTEB.Y HOLDER.

The battery holder is intended to be mounted outside the computer enclosure.
This is because batteries, although sealed, under some conditions can still
leak, outgas or otherwise do nasty things to the sensitive components and
contacts inside your computer. Therefore, we strongly recommend that the
battery be mounted outside the computer enclosure and not inside.
REPLACING THE BATTERY
The 4.5 volt alkaline battery that is supplied with the System Support 1
should last approximately 1.5 years with normal use. However, to insure that a
loss of time or memory data does not occur due to battery failure, we recommend
that the battery be replaced once every year. The battery can be replaced while

18

the system power is on, so that operation of the clock or memory data will not
be lost, (unless of course you get a power failure at the exact instant that you
remove the battery).
The type of battery used is a Mallory PX21 or Eveready 523. Replacement
batteries are available from us or possibly your local dealer. You can probably
also obtain this battery from a photo store or possibly a "drug" store with a
well stocked photo department. This battery is also used in some smoke alarms,
so you may also find it in a well stocked hardware store.
If you plan to keep a replacement battery handy, be aware that the average
shelf life .of an alkaline battery is two years. This can be extended significantly by storing the battery in a refrigerator. Before using a battery that
has' been stored in the refrigerator, allow it to come up to room temperature and
make sure that there is no moisture present on any of the contacts.

IHPORTAST ROTE: Please do not use anything other than an alkaline battery.
Mercury cells may seem like a good choice for this application, but they do not
fare too well under the light load presented by the System Support 1. CarbonZinc cells can leak, causing damage to the computer (usually irreparable). Nic:ads will not be recharged by the board's circuitry. Also note that using any
battery other than the ones specified will void your warranty.
I/O PORr MAP
The System Support 1 uses a block of 16 I/O port addresses. This block may
begin at ani L6 por~ boundary. Each of the I/O ports performs a specific
function and each will always appear at an address that is relative to the base
address.
The following chart shows the I/O port's relative positions, and
their actual address when the System Support 1 is addressed to the block at 50H
(CompuPro standard address).
Port Function

Relative Position

Address

----------------------------------------------------------------Master 8259A lower port (AO=O)
Master 8259A upper port (AO=l)
Slave 8259A lower port (AO=O)
Slave 8259A upper port (AO=l)
Timer/Counter 0
Timer/Cciunter 1
hmer/Counter i
Timer/Counter Control Register
9511A/9512 Data Port
9511A/9512 Command Port
Clock/Calendar Command Port
Clock/Calendar Data Port
2651 Data Register
2651 Status Register
2651 Mode Registers
2651 Command Register

Base+ 0
Base+ 1
Base+ 2
Base+ 3
Base+ 4
Base+ 5
Base+ 6
Base+ 7
Base+ 8
Base+ 9
Base+10
Base+11
Base+12
Base+13
Base+.14
Ba,se+15

dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec
dec

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex.

50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
'5E
5F

hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex
hex

19

PROGRAMMING CONSIDERATIONS FOR THE SYSTEM SUPPORT 1
The following section of this manual will discuss some of the.software
considerations that will be necessary to use this board. We will provide you
·with a few actual programs, but these programs are presented as either examples
or for testing purposes and are not necessarily the best way to do something.
The listings were prepared using the standard CP/M assembler (ASM.COM) and
sometimes assume a CP/M system (like. for I/O calls).
First we will discuss the power-up initialization of the System Support 1
and then we will discuss the programming considerations for the various
functions of the board.
POWER-UP INITIALIZATION
When you turn on your system, the first thing that usually happens is to
boot in the disk operating system or execute some kind of program stored in ROM.
Somewhere at the beginning of these programs is usually some code to initialize
the system. This may do things like set the stack pointer, clear some registers
and send a set of initial parameters to I/O peripherals. This latter example is
what needs to be done with the System Support 1.
To be specific, the interrupt controllers must be set up with all the data
it takes to get them to respond correctly in your system (like masking unused
interrupts, setting priority levels, setting the interrupt vector address etc.);
the serial channel parameters must be set (like the baud rate, word length
etc.); the interval timer modes must be set (if they are used) and so on.
How your board is to be set up on power-up is dependent soley on your system
requirements. Therefore, we will not attempt to give every possible example of
how the board may be initialized. Instead, the following sections will discuss
the various sections of the System Support 1 in detail and you will have to
derive the initialization parameters from that data. The software examples will
all contain some kind of initialization routine, but they will probably not be
the same for your system.
PROGRAHMDlG THE SERIAL CIWIINEL
The serial channel on the System Support 1 is implemented with a 2651 type
DART from either National Semiconductor or Signetics. Several of the DART
parameters and channel control functions are programmed by writing into or
reading from certain registers in the 2651. They are:
1.
2.
3.
4.
5.
6.
7.

The baud rate.
The word length.
Whether or not a parity bit is generated.
Whether the parity is even or odd (if generated).
The number of stop .bits.
Enabling and disabling the transmitter and receiver.
Setting and testing the RS-232 handshake lines.

In addition, the normal status indications and
also handled through the DART's registers.
A table of the various registers and where they
follows. (The port addresses assume that the System
CompuPro "standard" port block; see the sections on
the I/O port map for more information.)

20

data transfer functions are
appear in the I/O port map
Support 1 is set up to the
setting the I/O address and

"READ" or. "INPUT" Ports
Port Address

sc hex
SD hex
SE hex
SF hex

UART Register Function
Data Port, read received data word.
Status Port, read UART status info.
Mode Registers, read current UART mode.
Command Register, read current command.
"WRITE" or "OUTPUT" Ports

SC
SD
SE
SF

hex
hex
hex
hex

Data port, write word to be transmitted.
not used
Mode registers, write mode bytes.
Command register, write command to UART.

Data Registers
The UART data registers are straight-forward in their operation.
You write
a byte to the data register when you want to transmit that byte to an external
serial device and you read the byte in the data register to receive a byte from
an external serial device. The UART will automatically add the proper start and
stop bits when transmitting and will remove them when receiving.
Status Register
The status register is used to determine the current state of the UART.
Each bit of the status register has a different meaning depending on whether it
is high or low.
(High means a logic one or high level and low means.a logic
zero or low level.) The following table describes the meaning of the status
bits:
Bit 0 - TxRDY:
When low indicates that the transmitter is currently busy and
you should wait before sending another character.
When high indicates that the
transmitter is not busy and is ready to accept a new character for sending.
Bit 1 - RxRDY: When low indicates that there is no character waiting to be
read. When high indicates that a character has been received and should be read.
Bit 2 - TxEMT/DSCHG:
When high indicates that either the DCD or DSR lines have
changed, or that the transmitter shift register is empty.
When low indicates
that none of the above are true. Note:
Unless you really need this status
indication, just ignore this bit.
Bit 3 ." PE: When high indicates that a parity error has .occurred.
indicates that no parity error has occurred.

When low

Bit 4 - Overrun: When high indicates that an overrun has occurred. When low
indicates that an overrun has not occurred. An overrun can occur if you failed
to read the data word before another one arrives.
Bit S - FE: When high indicates that a framing error has occurred. When low
indicates that no framing error has occurred. A framing error occurs when no
stop bit has been received. This can happen if the line was interrupted or the
baud rate is incorrect or any number of other data errors are detected.

21

Bit 6 - Data Carrier Detect: When high indicates that the DCD line is low.
When low indicates that the DCD line is high.
Bit 7 - Data Set Ready: When high indicates that the DSR line is low.
indicates that the DSR line is high.

When low

Hode llegisters
When bringing up the UART, its two mode registers must be set with various
bit patterns that will determine the operating modes. There are two registers,
however they occupy only one I/O port address. This is accomplished with
internal sequencing logic that allows you to write the first register (Mode
Register 1) and then the second register (Mode Register 2). It is important to
write to Mode Register 1 first.
The meanings of the various bits in the mode registers are described below:
Mode Register 1
Bits 0 and 1 - Mode and baud rate factor: For proper operation of the UART in
the System Support I, bit 0 should be low (a logic zero) and bit 1 should be
high (a logic one). This sets up the UART for asynchronous operation with a 16X
baud rate.
Bits 2 and 3 - Chara~ter Length: These two bits are used to determine the
length of the characters that will be sent and received, according to the
following table:
Character Length
Bit 3
Bit 2
5 bits
o
0
o
1
6 bits
1
0
7 bits
1
1
8 bits
The most often used character length will be 8 bits, so bits 2 and 3 will
normally both be high.
Bit 4 - Parity Control: When bit 4 is low then no parity bit will be generated.
When bit 4 is high then a parity bit will be generated.
Bit 5 - Parity Type: When bit 5 is low then the parity generated will be odd.
If bit 5 is high then the parity generated will be even. If bit 4 (the Parity
Control bit) is low (meaning no parity is generated) then bit 5 is insign1£ic·ant.
Bits 6 and 7 - Stop Bit Length: These two bits are used to determine the number
of stop bits that are sent according to the following table:
Bit 7
0
0
1
1

Bit 6
0
1
0
1

Number of Stop Bits
Invalid
1 stop bit
1 1/2 stop bits
2 stop bits

The most often used configuration is two stop bits, so both bits 6 and
7 would normally be high.

22

The following example shows mode register 1 set up for 8 bit characters, no
parity and 2 stop bits:
Bit

7

6

11111

1

o

5

4

xl

0111111101

= HIGH

3

1

2

x

o = LOW

= DON'T CARE

Use the following area to write in the bit pattern for mode register 1 that
best suits the needs of your system:
Bit

6

7

5

3

4

o

1

2

1

I 0 I

Mode Register 1
Mode Register 2
Bits 0, I, 2 and 3 ~ Baud Rate Selection: These four bits are used to determine
what baud rate will be generated by the UART (and therefore what baud rate the
UART will run at) according to the following table:
Bit 3

Bit 2

Bit 1

Bit 0

0
0
0
0
0
0
0
0
1

0
0

0
0
1
1
0
0
1

0
1
0
1
0
1
0
1
0
1
0

0

0
1
1
1
1
0
0
0
0

1

1
1
1

1

0
0
1

1

1

1

1
1

1
1

1

1

0
0
1

0
1
0

1

1

Baud Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

Bits 4, 5, 6, and 7: For proper UART operation in the System Support I, these
four bits should always be written in the following pattern:
Bit 7

Bit 6

Bit 5

Bit 4

0

1

1

1

The following example shows mode register 2 set up for 9600 baud:
Bit

6

7

5

4

2

3

1

0

---------------------------------------I 0 I 1 I

1

I

1

I

1

I

1

I 1 I 0 I

---------------------------------------1

= HIGH

o=

LOW

23

Use the following area to write in the bit pattern for mode register 2 that
best suits the needs of your system:

Bit

7

I

0

5

6

I

1

I

1

3

4

I

1

2

1

o

I

Mode Register 2
That completes the description of the Mode Registers. Remember that you must
always write both mode registers, with Mode Register 1 first.

Command Regis ter
The Command Register is used to enable and disable the receiver and/or
transmitter, force a "break" condition, reset the error flags and control the
state of the RTS and DTR outputs.
Bit 0 - Transmit Control: When bit 0 is high the transmitter section of the
UART is enabled. When bit 0 is low the transmitter is disabled. Normally this
bit should be high.
Bit 1 - Data Terminal Ready: When bit 1 is high the DTR output is forced to a
low state. When bit 1 is low the DTR output is forced to a high state.
Bit 2 - Receive Control: When bit 2 is high the receiver section of the UART is
enabled; When bit 2 is low the receiver is disabled.
Normally this bit should
be high.
Bit 3 - Force Break:
When bit 3 is high a break condition is forced.
When bit
3 is low, normal operation occurs. A break conditi'on is when the serial data
output line is forced to the marking state.
Bit 4 - Reset Error:
When bit 4 is high the error flags in the status register
are reset. When bit 4 is low then normal operation occurs.
Bit 5 - Request To Send: When bit 5 is high the RTS output is forced to a low
state.
When bit 5 is low the RTS output is forced to a high state.
Bits 6 and 7:
(a logic 0).

For proper operation of the UART, these bits should always be low

The following example shows the command register set up for RTS and DTR low,
the force break and reset error functions set for normal operation and both the
receiver and transmitter enabled:

Bit

7

5

6

4

3

2

1

o

10101110101111111
1

24

= HIGH

o = LOW

Use the following area to write in the bit pattern for the command register
that best suits the needs of your system:
Bit

7

6

4

5

3

1

2

o

I 0 I 0 I
Command Register
This completes our discussion of the various registers inside the UART and
what their functions are.
UART Initialization
When bringing up the UART, the following sequence of events must occur:
1.
2.
3.
4.

Set Mode Register 1
Set Mode Register 2
Set Command Register
Begin normal UART operation

SAMPLE UART PROGRAM
The following program can be used to test the UART. It first initializes
the UART and then reads charac ters and echoes them. If a CONTROL C is typed,
control returns to CP/M (or you may patch it for any other monitor or software
you are using).
TEST PROGRAM FOR THE 2651 DART
SETS UP THE UART FOR 9600 BAUD (INTERNALLY GEN)
8 BIT CHARACTERS, 2 STOP BITS, NO PARITY, RTS
LOW, DTR LOW, AND THEN ECHOES CHARACTERS
;assumes System Support 1 is addressed to 50 hex (CompuPro Standard)
;for different addresses, change "BASE" in equates
0050

BASE

EQU

50H

005C
005D
005E
005F
0001

DATA
STATUS
MODE
CMND
TBE

EQU
EQU
EQU
EQU
EQU

BASE+OCH
BASE+ODH
BASE+OEH
BASE+OFH
01H

0002

RDA

EQU

02H

0000
0003

CPM
CNTLC

EQU
EQU

OOOOH
03H

0100

ORG

100H

0100 3EEE
0102 D35E

INIT: MVI
OUT

A,1l101110B
MODE

;base address of System
Support 1
;UART data register
;UART status register
;UART mode registers
;UART command register
;transmitter buffer empty
status bit
;receiver data available
status bit
;CP/M restart address
;control C

;data for mode register 1
;send it

25

0104
0106
0108
010A

3E7E
D35E
3E27
D35F

MVI
OUT
MVI
OUT

010C
010E
0110
0113

DB5D
GETCHR: IN
E602
ANI
CAOCOI
JZ
DB5C
IN

A,01l11110B
MODE
A,00100111B
CMND

;data
;send
;data
;send

STATUS
RDA
GETCHR
DATA

;read the status register
;mask out all bits but RDA
;if it's not high, loop
;must be high so read the
data
.;strip off parity bit
;was it a control C?
;yes, jump to CP/M
;otherwise ••••

0115 E67F
0117 FE03
0119 CAOOOO

ANI
CPI
JZ

7FH
CNTLC
CPM

OllC F5

PUSH

PSW

011D
011F
0121
0124

DB5D
SNDCHR: IN
E601
ANI
CAIDOI
JZ
Fl
POP

0125 D35C
0127 C30COl

OUT
JMP

STATUS
TBE
SNDCHR
PSW
DATA
GETCHR

for mode register 2
it
for command register
it

;save the character on the
stack
;read the status register
;mask out all bits but TBE
;if it's not high, loop
;must be high, get
character back
;and send it
;then repeat whole thing

PROGRAMMING THE REAL TIME CLOCK
The real time clock (or time-of-day clock) is implemented with the OKI
MSM5832 clock chip. This CMOS IC takes care of all of the time and date housekeeping functions, relieving the CPU of this overhead. All that we need do is
set the time and date into the chip once and it will take care of the rest for
us. Whenever we want to know what time it is, we simply read the time from the
chip.
The time and date information is available as BCD digits and any digit may
be read randomly. There are four data lines that contain the digit information.
These four lines appear as the lower four bits of the byte read at the clock
data port. The upper four bits are always zero. (This allows easy conversion
to ASCII by simply adding in 30H, or allows for easy digit packing.)
There is a command byte that is written to select whether a read or write
operation is taking place and select which digit we want to operate on. There
is also a bit that will stop the clock's counting to ensure error free reads and
writes. The bit assignments and functions of the command port are as follows:
Bit 7: Unused.
Bit 6 - Hold: When this bit is high, the clock's counters will be inhibited.
This line must be high for all write operations and may be optionally high for
read operations. If this line is kept high for more than one second then the
time will be affected.
Bit 5 - Write: When this bit is high the data at the data register will be
written into the selected digit address.
Bit 4 - Read: When this bit is high the clock data port will contain the data
from the selected digit.

26

Bits 3, 2, 1 and 0 - Digit Select: These four bits are used to select which
digit to read or write according to the following table:
Bit 3

Bit 2

Bit 1

Bit 0

0
0
0
0
0
0
0
0
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1

0
0
1
1
0
0
1
1
0
0
1
1
0

0
1
0
1
0
1
0
1
0
1

0
1
0

Digit Function
Seconds 1 Digit
Seconds 10 Digit
Minutes 1 Digit
Minutes 10 Digit
Hours 1 Digit
Hours 10 Digit *
Day of Week Digit
Days 1 Digit
Days 10 Digit II
Months 1 Digit
Months 10 Digit
Years 1 Digit
Years 10 Digit

* The hours 10 digit is also used for AM/PM indication and mode setting and 24
hour mode setting.
II
The days 10 digit is also used to select either 28 or 29 days in month 2
(Leap Year in February).
NOTE: Both seconds digits are not settable to anything but zeroes.
Any value
that you try to write to them will be ignored and instead they will be set to
zero. This is an idiosyncracy of the MSM 5832 clock chip.
Clock Data Register
The data register is used to transfer digit data to and from the clock.
Operation is very straightforward - after setting up the command register all
that need be done is to read from or write to the data register.
(The exact
sequence will be covered later.)
The actual data that is written to or read from this register is usually in
the form of one BCD digit.
A BCD digit is in the range of 0 to 9 and is
contained in the lower order nibble.
The upper nibble is always zero on reads
and is 'don't care' on writes.
There are two exceptions to the above.
They
concern the Hours 10 digit and the days 10 digit.
The lower two bits of the Hours 10 digit and the Days 10 digit are the only
ones that convey any digit information.
The next two bits are used to convey
other kinds of information. Only two bits are needed for these two digits since
two bits can represent the numbers 0 through 3.
The hours 10 digit will never
go beyond 2 (in the 24 hour mode) and the days 10 digit will never go beyond 3.
The upper two bits of the low order nibble in the hours 10 digit are used to
select the 12 or 24 hour modes and to indicate AM or PM i f the 12 hour mode is
selected.
The following table illustrates the significance of the bits:
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0

"0" for 12 hour format, "1" for 24 hour format.
"0" for AM, "1" for PM (in 12 hour format).
Always zero in 12 hour format, otherwise MSB of digit
in 24 hour format.
LSB of digit in either format.

27

Bit 2 of the days 10 digit is used to tell the clock whether to put 28 or 29
days in February (leap year bit).
If bit 3 is set to a one, then February will
have 29 days.
After the 29th day in February, the bit will be reset to a zero.
If the bit is reset to a zero (either internally or externally by the program)
then February will only contain 28 days.

NOTE:
All these extra bits must be set properly when programming the time and
date information, and they must be masked in software when reading the digit
data" (or first interpreted as in the case of the AM/PM bit).
NOTE:
Both seconds digits are not settable to anything but zeroes.
Any value
that you try to write to them will be ignored and instead they will be set to
zero. This is an idiosyncracy of the M5M 5832 clock chip.
CLOCK PROGRAMMING SEQUENCE

The clock must be written and read in a specific sequence of
sequence for writing the digits is:

events.

1.

Write a 40H to the command register to set the hold bit high.

2.

Write the digit address in the lower four bits of the command
register with the hold bit set high and the read and write bits low.

3.

Write the data to be written to the data register.

4.

Write the digit address in the lower four bits of the command
register with the hold and write bits set high and the read bit low.

5.

Write the digit address in the lower four bits of the command
register with the hold bit set high and the read and write bits low.

6.

Repeat steps 2 through 5 for the remaining digits.

7.

Write all zeroes to the command register to set the hold bit low
start the clock going.

The

and

The sequence for reading the digits is:
1.

Write the digit address in the lower four bits with the read bit set
high and the hold and write bits low (see note).

2.

Read the digit from the data register.

3.

Repeat steps 1 and 2 for any remaining digits (if you want to
continually read one digit then you do not have to keep rewriting the
command register).

4.

Write all zeroes to the command register.

NOTE: Optionally the Hold bit may be set high to ensure error free reads but if
the hold bit is set high then the clock will stop counting.
The time will not
be affected unless the hold bit is high for longer than one second. So if you
are continually scanning one digit, keeping the hold bit high continually would
stop counting. If you are only reading the clock once a second or at some other

28

comparatively slow rate, then it would be a good idea to set the hold bit. This
will insure that you don't read a digit just as it is changing, causing an
erroneous time to be reported.
SAMPLE CLOCK PROGRAM
The following program will allow you to test the clock as well as show the
basic idea in reading and writing from it.
The program allows you to set the
time and date, print the time just once, print the time continually or return to
the operating system.
When entering the time and date information, all input is checked for a
valid digit, but erroneously typed digits cannot be corrected.
Also note that
you must type in all 12 digits (including leading zeroes) to cause the information to be correctly entered into the clock.
If. you make a mistake, type a
return and try the whole sequence again.
If the time is printing continuously,
typing a CNTL C will get you back to CP/M.
The program selects the 24 hour mode and assumes it is not a leap year.
TEST ROUTINES FOR THE SYSTEM SUPPORT 1 REAL TIME CLOCK
jthis program assumes that the System Support 1 is addressed
jto the block of ports at 50H, to change to a different address,
jchange BASE in equates.
0050
005A
005B
0005
0010
0020
0040

BASE
CLKCMD
CLKDATA
BDOS
READ
WRITE
HOLD

EQU
EQU
EQU
EQU
EQU
EQU
EQU

0100

ORG

100H

50H
BASE+lO
BASE+11
0005H
lOR
20H
40H

jBASE PORT ADDRESS
jCLOCK COMMAND PORT
jCLOCK DATA PORT
;BDOS CALL ADDRESS
jREAD BIT PATTERN
jWRITE BIT PATTERN (+HOLD)
jHOLD BIT PATTERN

;this is the main loop that prints the sign-on message, decides
;what command has been entered and executes that particular routine.
0100
0103
0106
0109
OlOC
OlOE
0111
0113
0116
0118
OllB
OllD
0120
0123
0126

314804
117202
CD6A02
CD3B02
FE58
CAOOOO
FE53
CA2901
FE50
CAI002
FE43
CA1C02
116703
CD6A02
C30301

START

LXI
LXI
CALL
CALL
CPI
JZ

CPI
JZ

CPI
JZ

CPI
JZ

LXI
CALL
JMP

SP, STACK
D,SIGNON
PMSG
GET CHAR
'X'
OOOOH
'S'
SETTIME
'P'
PTIME
'C'
FOREVER
D,ERROR
PMSG
START

;SET THE STACK POINTER
;PRINT SIGNON MESSAGE
;PRINT IT
;GET COMMAND CHARACTER
;IF X
;THEN RESTART SYSTEM
; IF S
; THEN SET TIME
;IF P
;THEN PRINT THE TIl1E
;IF C
;THEN PRINT TIME FOREVER
;NONE OF THE ABOVE
;PRINT ERROR MESSAGE
;AND TRY AGAIN

;this routine sets up HL to point to a table to receive the digits

29

;to be written to the clock. DE contains the pointer to the table
;of address values that correspond to the desired digit. The table
;is organized in the proper order for reading and writing. The
;routine gets the digits from the console and puts them into memory
;and then writes them to the clock.

CALL

GETTIME

012C 211C04

LXI

H,DTABLE

012F 111004
0132 060D

LXI
MVI

D,ATABLE
B,13

0134
0136
0138
0139

MVI
OUT
DCR
JNZ

A,HOLD
CLKCMD

013C 3EOO
013E D35A
0140 llF603

MVI
OUT
LXI

A,O
CLKCMD
D,TIMEIS

0143
0146
0149
014C
014D
014E
014F
0152
0153
0154

CALL
CALL
JMP
MOV
MOV
LDAX
CALL
INX
INX

PMSG
CLKPRNT
START
A,M
C,A
H
D

JMP

SETI

0129 CD5701

3E40
D35A
05
C24COI

CD6A02
CDC701
C30301
7E
4F
lA
CD9301
23
13
C33801

SETTIME

SETI

HERE

B

HERE

D

WRTDGT

;GET THE DATE AND TIME
DATA
;H GETS DIGIT TABLE
ADDRESS
;D GETS ADDRESS TABLE
;NUMBER OF DIGITS TO
WRITE +1
;SET HOLD BIT
;AND WRITE IT OUT
;DECREMENT DIGIT COUNT
;SKIP THIS NEXT BIT IF NOT
DONE
;CLEAR A
;CLEAR HOLD BIT
;SHOW THAT THE TIME IS
NOW:
;WHATEVER
;PRINT THE STUFF
;WE'RE DONE
;GET THE DIGIT INTO A
;AND PUT IT IN C
;GET THE COMMAND IN A
;WRITE THE DIGIT
; NEXT
;AND NEXT
;AND CONTINUE

;this is the routine that gets the digits from the console and
;stores them into memory at the address pointed to by HL.

0157
015A
015D
0160
0163
0165
0168
016A

llA303
CD6A02
211C04
CD8201
FEOD
CA6FOI
E60F
77

016B 23
016C
016F
0172
0175
0178
017A
017B
017D

30

C36001
I1D503
CD6A02
CD8201
FEOD
C8
E60F
77

GETTIME
GET 1

LXI
CALL
LXI
CALL
CPI
JZ
ANI
MOV

M,A

INX

H

JMP

GET 1
D,ASKDATE
PMSG
GETNUMB
ODH

GETDATE LXI
CALL
GET 2
CALL
CPI

D,ASKTIME
PMSG
H,DTABLE
GET NUMB
ODH
GETDATE

OFH

RZ

ANI
MOV

OFH
M,A

;PROMPT TIME INPUT
;ADDRESS TO PUT DIGITS
;GET DIGIT
;IS IT A CR?
;YES, GET THE DATE
;CONVERT TO BCD
; OTHERWISE , PUT THE DIGIT
IN MEMORY
;INCRill1ENT THE TABLE
ADDRESS
;GET THE NEXT DIGIT

;IS IT A CR?
; YES, RETURN
;CONVERT TO BCD
;PUT DIGIT IN MEMORY

017E 23
017F C37501

INX
JMP

H

GET2

;this routine gets a character from the console, and checks the
;input for either a carriage return or a valid aigit between 0-9
;will not return until a CR or valid digit is typed.
0182
0185
0187
0188
018A
018D
018F
0192

CD3B02
FEOD
C8
FE30
DA8201
FE3A
D28201
C9

GETNUMB CALL
CPI
RZ
CPI
JC
CPI
JNC
RET

GETCHAR
ODH
'0'
GETNUMB
' 9'+1
GJ!;TNUMB

;this routine writes the digit to
;see if it's the hours or days 10
;and leap year bits accordingly.
;digit address in A and the digit
0193
0194
0196
0198

F5
C640
D35A
FE45

019A
019D
019E
OlAO
01A3
01A5
OlA8
01A9

C2A301
79
C608
C3AFOl
FE48
C2AEOl
79
E603

OlAB
OlAE
OlAF
OlBl
OlB2

C3AFOl
79
D35B
Fl
C660

01B4
01B6
01B8
OlBA

D35A
D620
D35A
C9

WRTDGT PUSH
ADI
OUT
CPI

WRTI

MOV
ANI
JMP
MOV
OUT
POP
ADI

WRT3
A,C
CLKDATA
PSW
WRITE+HOLD

OUT
SUI
OUT
RET

CLKCMD
WRITE
CLKCMD

JNZ

WRT2
WRT3

PSW
HOLD
CLKCMD
5+HOLD
WRTI
A,C
08H
WRT3
8+HOLD
WRT2
A,C
03H

JNZ

MOV
ADI
JMP
CPI

;GET A CHARACTER
; IS IT A CR?

the clock, and checks to
digit and sets the 24 hour
This routine is called with
to be written in C.
jSAVE THE COMMAND
;ADD IN THE HOLD BIT
;AND OUTPUT IT
;WAS IT THE HOURS 10
DIGIT?
jNO
jOTHERWISE GET THE DIGIT
jAND SET 24 HOUR MODE
jWAS IT THE DAYS 10 DIGIT
jNO
jOTHERWISE GET THE DIGIT
jAND SET NON-LEAP YEAR
MODE
;PUT THE DIGIT IN A
;AND OUTPUT IT
;GET THE COMMAND BACK
jADD IN THE WRITE AND HOLD
BITS
;SEND IT OUT
;CLEAR THE WRITE BIT
;AND SEND IT
jNOW WE'RE DONE

;this routine reads a digit from the clock and masks the leap year
jand AM/PM/24 hour mode bits. This routine is called with the digit
;address in A and returns with the digit value in A
OlBB
OlBD
OlBF
OlCl
01C3

C610
D35A
FE15
DB5B
CO

RDDGT

ADI
OUT
CPI
IN
RNZ

READ
CLKCMD
05H+READ
CLKDATA

jADD IN THE READ BIT
;AND OUTPUT IT
;WAS IT THE HOURS 10 DIGIT
;GET THE DIGIT
;IF IT WASN'T, WE'RE DONE

31

0lC4 D60a

SUI

0lC6 C9

RET

oaH

;IF IT WAS, THEN KILL 24
. HOUR BIT
;AND THEN RETURN

; this routine prints the current time and date once and return.s
; (complete with colons and slashes)
01C7 211004

CLKPRNT· LXI

H,ATABLE

OICA CDFBOI .

CALL

PRINTWO

OICD
OlCF
01D2
OlD5
01D7
OIDA
OlDD
OlDF
0lE2
01E4
01E7
OlEA
OlEC
OlEF
01F2
0lF4
01F7
OIFA

MVI
CALL
CALL
MVI
CALL
CALL
MVI
CALL
MVI
CALL
CALL
MVI
CALL
CALL
MVI
CALL
CALL
RET

A'·'
,
PCHAR
PRINTWO
A'·'
,
PCHAR
PRINTWO
A,' ,
PCHAR
A, ' , .
PCHAR
PRINTWO
A, , /'
PCHAR
PRINTWO
A,'/'
PCHAR
PRINTWO

3E3A
CD5602
CDFBOI
3E3A
CD5602
CDFBOl
3E20
CD5602
3E20
CD5602
CDFBOl
3E2F
CD5602
CDFBOl
3E2F
CD5602
CDFBOl
C9

.

.

; GET THE TABLE ADDRESS.
IN HL
;PRINT THE FIRST TWO
DIGITS
;PRINT THE NEXT TWO DIGITS ,
;PRINT THE NEXT TWO DIGITS
;PRINT TWO SPACES
;PRINT TWO MORE DIGITS
;PRINT A SLASH

;PRINT THE LAST TWO DIGITS
;WE'RE DONE

;this routine prints two digits from the clock. It is called with
;the digit address of the first digit in HL. Exits with HL pointing
;to the address of the next two digits.·
OlFB 7E
OIFC
OIFF
0201
0204
0205
0206
0209
020B
020E
020F

PRINTWO MOV

CDBBOl
C630
CD5602
23
7E
CDBBOI
C630
CD5602
23
C9

CALL
ADI
CALL
INX
MOV
CALL
ADI
CALL
INX
RET

A,M
RDDGT
30H
PCHAR
H

.A,M
RDDGT
30H
PCHAR
H

;GET THE ADDRESS FROM
TABLE
;READ THE DIGIT
;CONVERT TO ASCII
;AND PRINT IT
;INCREMENT THE POINTER
;GET THE NEXT. ADDRESS

;this routine prints the time once and jumps back to the main loop
0210 llF603
0213 CD6A02
0216 CDC701
0219 C3030l

32

PTIME

LXI
CALL
CALL

D,TIMEIS
PMSG
CLKPRNT

JMP

START

;PRINT "THE TIME IS

-"

; AND PRINT THE TIME AND
DATE
;AND RESTART

;this routine prints the time forever (unless a CNTL C is typed)
;it continually reads the seconds 1 digit and waits for it to
;change before printing the time.

021C 3EOA
021E CD5602
0221 3EOD
0223 CD5602
0226 CDC701
0229 3EOO
022B CDBBOl
022E 47
022F 3EOO
0231CDBBOl
0234 B8

FOREVER MVI
CALL
FORl
MVI
CALL
CALL
MVI
CALL
MOV
FOR2
MVI
CALL
CMP

0235 CA2F02
0238 C32l02

JZ
JMP

A,OAH
PCHAR
A,ODH
PCHAR
CLKPRNT
A,O
RDDGT
B,A
A,O
RDDGT
B
FOR2
FORl

;LINE FEED
;SEND IT
;CARRIAGE RETURN
;SEND IT
;PRINT THE TIME
;ADDRESS OF SECONDS DIGIT
;READ THE SECONDS DIGIT
;SAVE IT IN B
;READ IT AGAIN
;COMPARE IT TO THE ONE WE
JUST READ
;LOOP IF IT'S THE SAME
;OTHERWISE PRINT IT AGAIN

;CP/M CALLS AND UTILITIES
;this routine gets a character from the console, converts it to
;uppercase, strips off the parity and checks for CNTL C

023B
023C
023E
0241
0242

E5
OE01
CD0500
El
FE6l

0244
0247
0249
024C
024E
0250
0252
0255

DA4E02
FE7B
D24E02
E65F
E67F
FE03
CAOOOO
C9

GET CHAR

SKIP

PUSH
MVI
CALL
POP
CPI

H

JC
CPI
JNC
ANI
ANI
CPI
JZ
RET

SKIP

C,Ol
BDOS

;SAVE HL
;CHARACTER IN FUNCTION

H

'a'

;RANGE CHECK FOR UPPER
CASE
; CONVERSION

'z'+l

SKIP
5FH
7FH
03H
OOOOH

;CONVERT TO UPPER CASE
;AND STRIP PARITY
;IS IT A CNTL C?
;YES, RESTART SYSTEM
;OTHERWISE WE'RE DONE

;this routine prints a character on the console and checks
;to see if any characters were entered while printing.

0256
0257
0258
025A
025B
025E
0260

D5
SF
OE02
E5
CD0500
OEOB
CD0500

0263
0264
0265
0266

El
Dl
B7
C43B02

PCHAR

PUSH
MOV
MVI
PUSH
CALL
MVI
CALL

D
E,A
C,02H
H
BDOS
C,OBH
BDOS

POP
POP
ORA
CNZ

H
D
A
GETCHAR

;SAVE D REGISTER
;CHARACTER TO PRINT IN E
;CHARACTER OUT FUNCTION
;SAVE HL
;CONSOLE STATUS CHECK
;SEE IF A CHARACTER WAS
TYPED
;SET THE FLAGS
;IF A CHARACTER WAS TYPED,
GO GET IT

33

0269 C9

;OR RETURN

RET

;this routine prints the string pointed to by DE until a $ is
;encountered. Should be called with DE pointing to start of string.
026A
026B
026D
0270
0271

E5
OE09
CD0500
El
C9

PMSG

PUSH
MVI
CALL
POP
RET

H

C,09H
BDOS

;PSTRING FUNCTION

H

;MESSAGES
U272 ODOAODOA54SIGNON DB
0296 5359535445
02AA 504C454153

DB
DB

02D6 53202D2053
02Fl 50202D2050
0313 43202D2043

DB
DB
DB

033D 58202D2045
035B ODOA434F4D

DB
DB

0367 ODOA544841ERROR

DB

038F ODOA504C45

DB

ODH,OAH,ODH,OAH,'TIME AND DATE TEST
ROUTINES FOR '
'SYSTEM SUPPORT l',ODH,OAH,ODH,OAH
'PLEASE TYPE ONE OF THE FOLLOWING
COMMANDS:',ODH,OAH
's - SET THE TIME AND DATE',ODH,OAH
'P - PRINT THE TIME AND DATE ONCE' ,ODH,OAH
'c - CONTINUOUSLY PRINT THE TIME AND
DATE',ODH,OAH
'X - EXIT TO OPERATING SYSTEM',ODH,OAH
ODH,OAH,'COMMAND: $'
ODH,OAH,'THAT WAS NOT ONE OF THE ABOVE
COMMANDS'
ODH,OAH,'PLEASE TRY AGAIN $'

03A3 ODOA574841ASKTIME

DB

ODH,OAH,'WHAT IS THE TIME?
(24 HOUR FORMAT - HH:MM:SS) $'

03D5 ODOA574841ASKDATE

DB

ODH,OAH,'WHAT IS THE DATE?

03F6 ODOA544845TIMEIS DB

(MM/DD/YY) $'

ODH,OAH,'THE TIME AND DATE ARE: $'

;DIGIT ADDRESS TABLE
; this table contains the "address" values that are sent in the
;command byte in the following order: Hours 10, Hours 1, Min 10,
;Min 1, Sec 10, Sec 1, Month 10, Month 1, Days 10, Days 1, Years 10
;Years 1.
0410 0504030201ATABLE DB

5,4,3,2,1,0,OAH,9,8,7,OCH,OBH

;this is the area which gets the digits as they are entered from the
;console.
041C

DTABLE DS

12

;this is the area for the stack
0428

DS
STACK

34

32

;FOR 16 LEVEL STACK

PROGRAMMING THE INTERRUPT CONTROLLERS
The two interrupt controllers used on the System Support 1 are the 8259A
from either Intel or NEC. This chip is very versatile and has many operating
modes. Rather than try to explain them all to you, we have chosen to reprint
several pages from Inte~s AP-59 application note on using the 8259A.
Thid is
excellently wrjtten by Robin Jigour.
The specific hardware implementation of the two 8259As on the System Support
1 is a master/slave arrangement with 7 of the master's interrupt inputs and one
of the slave's hooked up to the S-100 vectored interrupt lines. The 7 remaining
interrupt inputs to the slave are connected to the on-board interrupt sources.
The interrupt output from the slave is connected to the eighth interrupt input
of the master. This is shown in more detail in the section entitled "Interrupt
Jumpers and Options" in the hardware configuration section of this manual.
The interrupt controllers take up four I/O port addresses (two for each).
Tile exact port addresses will depend on how you have the board addressed, but
their relative addresses are shown in the I/O Port Map section of this manual.
The reprint below should explain everything you want to know about the 8259A
and how to program it. After the reprint we will give you a sample program that
can be used to initialize the interrupt controllers.

IMPORTANT NOTE ABOUT USING DDT TO DEBUG INTERRUPTS
When using DDT under CP/M to debug interrupt routines, you should be aware
that when DDT is invoked and after a "G" command is issued, DDT will enable
interrupts. This can be catastrophic because your program will not have control
over when interrupts are enabled or disabled.
Tnere is only one practical solution to the problem and that is to modify
DDT to not enable interrupts.
To modify DDT so that it will not enable
interrupts, perform the following steps:
1. Make sure the computer's power is
off and remove the System Support 1 from the system. 2. Power the system back
up and type the following (things you type are underlined, things the computer
types are not):

A>DDT DDT.COM (return)
DDT VERS n.n
NEXT PC
1400 0100
-SABO (return)
OABO FB 00 (return)
OAB1 C9 ~ (return)
-S102X (return)
102X FB 00 (return)
102X 2A ~ (return)

Where X=2 for DDT 2.0 and below
and X=8 for DDT 2.2

-~C

A>SAVE

12.

DDT .COM ere turn)

35

INTRODUCTION

The Intel 8259A is a Programmable Interrupt Controller
(PIC) designed for use in real-time interrupt driven
microcomputer systems. The 8259A, manages eight
levels of interrupts and has built-in features for expansion up to 64 levels with additional 8259A's. Its versatile
design allows it to be used within MCS-80, MCS-85,
MCS-86, and MCS-88 microcomputer systems. Being
fully programmable, the 8259A provides a wide variety of
modes and commands to tailor 8259A interrupt processing for the specific needs of the user. These modes and
commands control a number of interrupt oriented func·
tlons such as interrupt priority selection and masking of
interrupts. The 8259A programming may be dynamically
changed by the software at any time, thus allowing complete interrupt control throughout program execution.
The 8259A is an enhanced, fully compatible revision of
its predecessor, the 8259. This means the 8259A can use
all hardware and software originally designed for the
8259 without any changes. Furthermore, it provides additional modes that increase its flexibility in MCS-80
and MCS-85 systems and allow .it to work in MCS-86 and
MCS-88 systems. These modes are:
•
•
•
•
•

MCS-86/88 Mode
Automatic End of Interrupt Mode
Level Triggered Mode
Special Fully Nested Mode
Buffered Mode

Each of these are covered in depth further in this application note.
This application note was written to explain completely
how to use the 8259A within MCS-80, MCS-85, MCS-86,
and MCS-88 microcomputer systems. It is divided into
five sections. The first section, "Concepts", explains
the concepts of interrupts and presents an overview of
how the 8259A works with each microcomputer syste'm
mentioned above. The second section, "Functional
Block Diagram", describes the internal functions of the
8259A in block diagram form and provides a detailed
functional description of each device pin. "Operation of
the 8259A", the third section, explains in depth the
operation and use of each of the 8259A modes and commands. For clarity of explanation, this section doesn't
make reference to the actual programming of the 8259A.
Instead, all programming is covered in the fourth section, "Programming the 8259A". This section expiains
how to program the 8259A .with the modes and commands mentioned in the previous section.
The reader should note that some of the terminology
used throughout this application note may differ
slightly from existing data sheets. This is done to better
. clarify and explain the operation and programming of
the 8259A.

1_ CONCEPTS

36

In microcomputer systems there is usually a need for
the processor to communicate with various Input/Out·
put (110) devices such as keyboards. displays. sensors.
and other peripherals. From the system viewpoint. the
processor should spend as little time as possible servic·
ing the peripherals since the time required for these 110
chores .directly affects the amount of time available for

other tasks. In other words, the system should be
designed so that I/O servicing has little or no effect on
the total system throughput. There are two basic
methods of handling the 110 chores in a system: status
polling and interrupt servicing.
The status poll method of I/O servicing essentially in·
volves having the processor "ask" each peripheral If it
needs servicing by testing the peripheral's status line. If
the peripheral requires service, th~ processor branches
to the appropriate service routine; if not, the processor
continues with the main program. Clearly, there are
several problems in implementing such an approach.
First, how often a peripheral is polled is an important
constraint. Some idea of the "frequency·oj·service"
required by each peripheral must be known and any soft·
ware written for the system must accommodate this
time dependence by "scheduling" when a device is
polled. Second, there will obviously be times when a
device is polled t!)at is not ready for service, wasting the
processor time that it took to do the poll. And other
times, a ready device would have to wait until the processor "makes its rounds" before it could be serviced,
slowing down the peripheral.
Other. problems arise when certain peripherals are more
important than others. The only way to implement the
"priority" of devices is to poll the high priority devices
more frequently than lower priority ones. It may even be
necessary to poll the high priority devices while in a low
priority device service routine. It is easy to see that the
polled approach can be inefficient both time·wise and
software-wise. Overall, the polled method of 110 servic·
ing can have a detrimental effect on system throughput,
thus limiting the tasks that can be performed by the
processor.
A more desirable approach in most systems would allow
the processor to be executing its main p'rogram and only
stop to service the I/O when told to do so by the 110
itself. This is called the interrupt service method. In
effect, the deviCe would asynchronously signal the proc·
essor when it required service. The processor would
finish its current instruction and then vector to the
service routine for the device requesting service. Once
the service routine is complete, the processor would
resume exactly where it left off. USing the interrupt ser·
vice method, no processor time is spent testing devices,
scheduling is not needed, and priority schemes are
readily implemented. It is easy to see that, using the in·
terrupt service approach, system throughput would ill'
crease, allowing more tasks to be handled by the
processor.
However, to implement the interrupt service method
between processor and peripherals. additional hardware
is usually required. This is because, after Interrupting
the processor, the device must supply information for
vectoring program execution. Depending on the proc·
essor used, this can be accomplished by the deVice tak·
ing control 01 the data bus and "Jamming'" an Instruc·
tion(s) onto it. The instruction(s) then vectors the pro·
gram to the proper service routine. This of course reo
quires additional con!rol logic for each interrupt reo
questing device. Yet the implementation so far is only in
the most basic form. What if certain peripherals are to

1.1 MCS·80™_8259A OVERVIEW
be of higher priority than others? What if certain inter·
rupts must be disabled while others are to be enabled?
The possible variations go on, but they all add up to one
theme; to provide greater flexibility using the interrupt
service method, hardware requirements increase.
So, we're caught in the middle. The status poll method
is a less desirable way of servicing 1/0 in terms of
throughput, but its hardware requirements are minimal.
On the other hand, the interrupt service method is most
desirable in terms of flexibility and throughput, but
additional hardware is required.
The perfect situation would be to have the flexibility and
throughput of the interrupt method in an implementa·
tion with minimal hardware requirements. The 8259A
Programmable Interrupt Controller (PIC) makes this all
possible.
The 8259A Programmable Interrupt Controller (PIC) was
designed to function as an overall manager of an inter·
rupt driven system. No additional hardware is required.
The 8259A alone can handle eight prioritized interrupt
levels, controlling the complete interface between pe·
ripherals and' processor. Additional 8259A's can be
"cascaded" to increase the number of interrupt levels
processed. A wide variety of modes and commands for
programming the 8259A give it enough flexibility for
almost any interrupt controlled structure. Thus, the
8259A is the feasible answer to handling 110 servicing in
microcomputer systems.
Now, before explaining exactly how to use the 8259A,
let's go over interrupt structures of the MCS·80, MCS·85,
MCS·86, and MCS·88 systems, and how they interact
with the 8259A. Figure 1 shows a block diagram of the
8259A interfacing with a standard system bus. This may
prove useful as reference throughout the rest of the
"Concepts" section.

,
INTERRUPT

I,

In an MCS·aO-8259A interrupt configuration, as in
Figure 2, a device may cause an interrupt by pulling one
of the 8259A's interrupt request pins (IRO-IR7) high. If
the 8259A accepts the interrupt request (this depends
on its programmed condition), the 8259A's INT (inter·
rupt) pin will go high, driving the 8080A's INT pin high.
The 8080A can receive an interrupt request any time,
since its INT input is asynchronous. The 8080A, how·
ever, doesn't always have to acknowledge an interrupt
request immediately. It can accept or disregard reo
quests. under software control using the EI (Enable Inter·
rupt) or DI (Disable Interrupt) instructions. These in·
structions either set or reset an internal interrupt enable
flip·flop. The output of this flip·flop controls the state of
the INTE (interrupt Enabled) pin. Upon reset, the 8080A
interrupts are 'disabled, making INTE low.
At the end of each instruction cycle, the 8080A exam·
ines the state of its INT pin. If an interrupt request is
present and interru pts are enabled, the 8080A enters an
interrupt machine cycle. During the interrupt machine
cycle the 8080A resets the internal interrupt Mable flip·
flop, disabling further interrupts until an EI instruction
is executed. Unlike normal machine cycles, the interrupt
machine cycle doesn't increment the program counter.
This ensures that the 8080A can return to the pre·
interrupt program location after the interrupt is com·
pleted. The 8080A then issues an INTA (Interrupt
Acknowledge) pulse via the 8228 System Controller Bus
Driver. This INTA pulse signals the 8259A that the 8080A
is honoring the request and is ready to process the inter·
rupt.
The 8259A can now vector program execution to the cor·
responding service routine. This is done during a se·
quence of the three INTA pulses from the 8080A via the
8228. Upon receiving the first INTA pulse the 8259A
places the opcode for a CALL instruction on the data
bus. This causes the contents of the program counter to
be pushed onto the stack. In addition, the CALL instruc·
tion causes two more INTA pulses to be issued, allow·,
ing the 8259A to place onto the data bus the starting
address of the corresponding service routine. This
address is called the interrupt·vector address. The lower
8 bits (LSB) of the interrupt,vector address are released
during the second INTA pulse and the upper 8 bits
(MSB) during the third INTA pulse. Once this sequence
is completed, program execution then vectors to the
service routine at the interrupt·vector address.
If the same registers are used by both the main program
and the interrupt service routine, their contents should
be saved when entering the service routine. This in·
cludes the Program Status Word (PSW) which consists
of the accumulator and flags. The best way to do this is
to "PUSH" each register used onto the stack. The ser·
vice routine can then "POP" each register off the stack
in the reverse order when it is completed. This prevents
any ambiguous operation when returning to the main
program.

REQUESTS

Flgu,. 1. 8259A Intertlce to Standard System BUI

Once the service routine is completed, the main
program may be re·entered by using a normal RET
(Return) instruction. This will "POP" the original con·

37

tents of the program counter back off' the stack to
resume program execution where it left off. Note, that
because Interrupts are disabled during the interrupt
acknowledge sequence, the EI instruction must be
executed either during the service routine or the main
program before further interrupts can be processed.
For additional information on the 8080A interrupt structure and operation, refer to the MCS.:aO User's Manual.

1.3 MCS~88/88TM-8259A OVERVIEW
Operation, of an MCS-86/88-8259A configuration has
basic'slmllarltles of the MCS-80/85-8259Aconfigurations. That is, a device can cause an interrupt by pulling
one of the,8259A's interrupt request pins (IRO-IR7) high.
If the 8259A honors the request, its INT pin will go high,
driving the 8086/8088's INTR pin high. Like the 8080A
and 8085A, the INTR pin of the 8086/8088 is asynchro·
nous, thus it can receive an interrupt any time. The
8086/8088 can also accept or disregard requests on
INTR under software control using the STI (Set Interrupt)
or CLI (Clear Interrupt) instructions. These instructions
set or clear the interrupt-enabled flag IF. Upon
8086/8088.reset, the IF flag is cleared, disabling external
interrupts on ,INTR. Beside the INTR pin, the 8086/8088
p,rovides'an NMI (Non-Maskable Interrupt) pin. The NMI
functions similar, to th,e 8085A's TRAP; it can't be dis·
abled or masked. NMI has higher priority than INTR.
, Although there are some basic similarities, the actual
processing of interrupts with an 8086/8088 is different
than an 8080A or 8085A. When an interrupt request is
present and interrupts are enabled, the 8086/8088 enters
its interrupt acknowledge machi,ne cycle. The interrupt
acknowledge machine cycle pushes the flag registers
onto the stack (as in a PUSHF instruction). It then clears
the IF flaQ which disables interrupts. The contents of
both the code segment and the instruction pOinter are
then also pushed onto the stack. Thus, the stack retains
Ihe pre-interrupt flag status and pre-interrupt program
location which are used to return from the service
routine. The 8086/8088 then issues the first of two INTA
pulses which signal the 8259A that the 8086/8088 has
honored its interrupt request. If the 8086/8088 is used in
Its "MIN Mode" the INTA signal is available from the
8086/8088 on its INTA pin. If the 8086/8088 is used in the
"MAX Mode" the INTA signal rs available via the 8288
Bus Controller INTA pin. Additionally, in the "MAX
Mode" the 8086/8088 LOCK pin goes low during the in·
terrupt acknowledge sequence. The LOCK signal can be
used to indicate to other system bus masters not to gain
control of the system bus during the interrupt acknowl·
edge sequence. A "HOLD" request won't be honored
while LOCK is low.
The 8259A is now ready to vector program execution to
the corresponding service routine. This is done during
the sequence of the two INTA pulses issued by the 8086/
8088. Unlike operation with the 8080A or 8085A, the
8259A doesn't place a CALL instruction and the starting
address of the service routine on the data bus. Instead,
the first INTA pulse is used only to signal the 8259A of
the honored request. The second INTA pulse causes the
8259A to place a single interrupt-vector byte onto the

38

data bus. Not used as a direct address, this interruptvector byte pertains to one of 256 interrupt "types" supported by the 8086/8088 memory. Program execution is
vectored to the corresponding service routine by the
contents of a specified interrupt type.
All 256 interrupt types are located in absolute memory
locations 0 through 3FFH which make up the 80861
8088's Interrupt-vector table. Each type in the interrupt·
vector table requires 4 bytes of memory and stores a
'code segment address and an instruction pointer ad·
dress. Figure 5 shows a block diagram of the interruptvector table. Locations 0 through 3FFH should be
reserved for the interrupt-vector table alone. Furthermore, memory locations 00 through 7FH (types 0-31) are
reserved for use by Intel Corporation for Intel hardware
and software products. To maintain compatibility with
present and future Iontel products, these locations
should not be used.

~

3FFH

INTERRUPT TYPE 255

3FCH
3FBH

INTERRUPT TYPE 254

·•
•

3FBH

BH

INTERRUPT TYPE 2
BH

7H
INTERRUPT TYPE 1
4H
INTERRUPT TYPE 0

3H

OH

Figure 5. 8086/8088 Interrupt Vector Table

When the 8086/8088 receives an Interrupt·vector byte
from the 8259A. it multiplies its value by four to acqUire
the address of the interrupt type, For example. If the
interrupt·vector byte specifies type 128 (80H), the vee·
tored address in 8086/8088 memory is 4 x 80H. which
equals 200H. Program execution is then vectored 10 the
service routine whose address is specified by the code
segment and instruction pOinter values within type 128
located at 200H. To show how this is done. let's assume
interrupt type 128 is to vector data to 8086/8088 memory
location 2FF5FH. Figure 6 shows two possible ways to
set values of the code segment and instruction pointer
for vectoring to location 2FF5FH. Address generation
by the code segment and instruction ppinter is ac·
complished by an offset (they overlap). Of the total
20·bit address capability, the code segment can desig.
nate the upper 16 bits, the instruction pointer can
designate the lower 16 bits.

CSIMSB)

,FFH
,FEH

2FH
FOH
OOH
SFH

CSILSB)
IPIMSB)
IPILSB)

'FDH
,FCH

IPIMSB)
IPILSB)

Beside external interrupt generation from the INTR pin,
the 8086/8088 is also able to invoke interrupts QY soft·
ware. Three interrupt instructions are provided: INT. INT
(Type ~), anq, IN:rO.INT is a two byte instruction. the sec·
ond byte selecis the interrupt type. INT (Type 3) is a one
byte instruction which selects interrupt Type 3. INTO is
a conditional one byte interrupt instruction which
selects interrupt Type 4 if the OF flag (trap on overflow)
is set. All the software interrupts vector program execu·
tion as the hardware interrupts do.

TYPE '28

-

,

,
,

FFH
FEH
FOH
FCH

20H
OOH
FFH
SFH

CSIMSB)
CSILSB)

changes in the service routine. Note especially that this
includes the state of the IF flag, thus interrupts are reo
enabled automatically when returning from the service
•
routine.

,

TYPE '28

~

For further information on 8086/8088 interrupt operation
and internal interrupt structure refer to the MeS·86
User's Manual and the 8086 System Design application
note.

Figure 6. Two Example. 01 B086/8088 Interrupt Type 128 Vectoring
to Location 2FF5FH

When entering an interrupt service routine, those regis·
ters that are mutually used between the main program
and service routine should be saved. The best way to do
this is to "'PUSH" each register used onto the stack im·
mediately. The service routine can then "POP" each
register off the stack in the same order when it is com·
pleted.

2. 8259A.FUNCTIONAL BLOCK DIAGRA,.,

A block diagram of the 8259A is shown In .Figure 7. As
can be seen from this figure, the 8259A consists of eight
major blocks: the Interrupt Request Register (lRR), the
In·Servlce Register (lSR), the Interrupt Mask Register
(IMR), the Priority Resolver (PR), the cascade buffer/
comparator, the data bus buffer, and logic blocks for
control and read/write. We'll first go over the blocks
directly related to Interrupt handling, the IRR, ISR, IMR,
PR, and the control logic. The remaining functional
blocks are then discussed.

Once the service routine is completed the main program
may be re·entered by using a IRET (Interrupt Return) in·
struction; The IRET instruction will pop the pre·interrupt
instruction pOinter. code segment and flags off the
stack. Thus the main program will resume where it was
interrupted with the same flag status regardless of

PIN CONFIGURATION

cs

BLOCK DIAGRAM

Vee

iiii
iiD

~
)NTA

0,

)R7

D.

IRa

~

IRS

D.

IR4

0,

IR3

D2

IR2

D,

IRl

0"

IRO

CAS 0

INT

CAS 1

~/EII

GND

CAS 2

DATA

PIN NAMES

cs-----'

DATA BUS InDIRECTiONALI

Viii

._-..

A.

READ INPUT

--------_.

WRITE INPUT
·CoMMAND SELECT ADl:iRESS

CS
CHIP SELECT
CAS1.CASO-cASc;';A;;;D"'EC;LT.IN"'E""S-!;II/ElI

SLAVE PROGRAM/ENABLE BUFFER

INT

INTERRUPT OUTPUT
INTERRUPT ACKNOWLEDGE INPUT
INTERRUPT REOUEST INPUTS

IRO·IR7

CONTROL LOGIC

aus

BUFFER

CASO -

•

CAS1 ..

CASCADE
•
aUF FER'
• COM'ARATOR

I
i
_...J

CAS2 ....

'INTERNAL

aus

FlQure 7. 8259A Block DiaGram and Pin ConllQuration

39

2.1 INTERRUPT REGISTERS AND CONTROL LOGIC
Basically. interrupt requests are handled by three "cas·
caded" registers: the Interrupt Request Register (lRR) is
use to store all the interrupt levels requesting service;
the In·Service Register (ISR) stores all the levels which
are being serviced; and the Interrupt Mask Register
(IMR) stores the bits of the interrupt lines to be masked.
The Priority Resolver (PR) looks at the IRR, ISR and IMR,
and determines whether an INT should be issued by the
the control logic to the processor.

When the IR input is in an inactive state (LOW), the edge
sense latch is set. If edge sensitive triggering is
selected, the "a" output of the edge sense latch will
arm the input gate to the request latch. This input gate
will be disarmed after the IR input goes active (HIGH)
and the interrupt request has been acknowledged. This
disables the input from generating any further inter·
rupts until it has returned low to re-arm the edge sense
latch. If level sensitive triggering is selected, the "a"
output of the edge sense latch is rendered useless. This
means the level of the IR input is in complete control of
interrupt generation; the input won't be disarmed once
acknowledged.

Figure 8 shows conceptually how the Interrupt Request
(IR) input handles an interrupt request and how the
various interrupt registers interact. The figure repre·
sents one of eight "daisy·chained'· priority cells, one for
each IR input.

When an interrupt occurs on the IR input, it propagates
through the request I~tch and to the PR (assuming the
input isn't masked). The PR looks at the incoming requests and the currently in-service interrupts to ascer.tain whether an interrupt should be issued to the processor. Let's assume that the request is the only one incoming and no requests are presently in service. The PR
then causes the control logic to pull the INT line to the
processor high.

The best way to explain the operation of the priority cell
is to go through the sequence of internal events that
happen when an interrupt request occurs. However.
first, notice that the input circuitry of the priority cell
allows for both level sensitive and edge sensitive IR in·
puts. Deciding which method to use is dependent on the
particular application and will be discussed in more
detail later.

LTIM BIT

TO OTHER PRIORITY CELLS

O_EDGE

elA ISA

1_lEVEl

ISA 81T

j
-t--t---~~--.., SET 'SR

PRIORITY
RESOLVER
CONTROL

LOGIC

NON·
MASKED
REO

'R --~~-+-----L~

MCSIOII5 {

'NTA~

MODE

FREEZE

MC~~ {

'N14

FREEZE

(LJl-f

Ie
,~

~NOTES
1. MASTER CLEAR ACTIVE ONLY DURING leW1
2. FREEZE/IS ACTIVE DURING INTiI AND POLL SEQUENCES ONLY
3. TAUTH TABLE FOR D·LATCH

C
1

o

I I
0

01
X

Q

or
On-1

I

OPERATION
FOLLOW

HOLD

FIgure 8. Priority Cell

When the processor honors the INT pulse, it sends a sequence of INTA pulses to the 8259A (three for 8080A/
8085A, two for 8086/8088). During this sequence the
state of the request latch is frozen (note the INTA-freeze
request timing diagram). Priority is again resolved by the
PR to determine the appropriate interrupt vectoring
which is conveyed to the processor via the data bus.

40

Immediately after the interrupt acknowledge sequence,
the PR sets the corresponding bit in the ISR which
simultaneously clears the edge sense latch, if edge sensitive triggering is used, clearing the edge sense latch
also. disarms the request latch. This inhibits the
posSIbility of a still active IR input from propagating
through the priority cell. The IR input must return to an

inactive state, setting the edge sense latch, before
another interrupt request can be recognized. If level sen·
sitive triggering is used, however, clearing the edge
sense latch has no affect on the request latch. The state
of the request latch is entirely dependent upon the IR in·
put level. Another interrupt will be generated immedi·
ately if the IR level is left active after its ISR bit has been
reset. An ISR bit gets reset with an End·of·lnterrupt (EOI)
command issued in the service routine. End·of·
interrupts will be covered in more detail later.

CASO- 12,13, 1/0 Cascade Lines: The CAS lines form a
CAS2
15
private 8259A bus to control a multiple 8259A structure. These pins are
outputs for a master 8259A and in·
puts for a slave 8259A.
SP/EN

16

I/O Slave Program/Enable Buffer: This is
a dual function pin. When in the buffered mode it can be used as an output to control buffer transceivers
(EN). When not in the buffered mode
it is used as an input to designate a
master (SJ5 = 1) or slave (SP = 0).

INT

17

0 Inte'rrupt: This pin goes high when-

2.2 OTHER FUNCTIONAL BLOCKS
Data Bus Buffer
This three'state, bidirectional 8·bit buffer is used to in·
terface the 8259A to the processor system data bus (via
OBO-OB7). Control words, status information, and
interrupt·vector data are transferred through the data
bus buff.er.

ever a valid interrupt request is as·
serted. It is used to interrupt the
CPU, thus it is connected to the
CPU's interrupt pin.
IROIR7

18-25

ReadlWrlte Control Logie
The function of this block is to control the programming
of the 8259A by accepting OUTput commands from the
processor. It also controls the releasing of status onto
the data bus by accepting INput commands from the
processor. The initialization and operation command
word registers which store the various control formats
are located in this block. The RO, ii'W\, AO, and CS
pins are used to control access to this block by the
processor.
Cascade BufferlComparator
As mentioned earlier, multiple 8259A's can be combined
to expand the number of interrupt levels. A master·slave
relationship of cascaded 8259A's is used for the expan·
sian. The SP/EN and the CASO-2 pins are used for oper·
ation of this block. The cascading of 8259A's is covered
in depth in the "Operation of the 8259A" section of this
application note.

AO

I Interrupt Requests: Asynchronous inputs. An interrupt r-equest can be
generated by raising an IR input (low
to high) and holding it high until it is
acknowledged (edge triggered mode),
or just by a high level on an IR input
(level triggered mode).

26

Interrupt Acknowledge: This pin is
used to enable 8259A interrupt-vector
data onto the data bus. This is done
by a sequence of interrupt acknowledge pulses issued by the CPU.

27

AD Address Line: This pin acts in conjunction with the CS, WR, and RO
pins. It is used by the 8259A to decipher between various command
words the CPU writes and status the
CPU wishes to read. It is typically
connected to the CPU AO address
line (Al for 8086/8088).

3. OPERATION OF THE 8259A
2.3 PIN FUNCTIONS
Name

Pin" 1/0 Function

Vce

28

+ 5V supply

GNO

14

Ground
Chip Select: A Iowan this pin enables RO and WR communication be·
tween the CPU and the 8259A. INTA
functions are independent of CS.

CS

WR

2

Write: A Iowan this pin when CS is
low enables the 8259A to accept
command words from the CPU.

RO

3

Read: A low on this pin when CS is
low enables the 8259A to release
status onto the data bus for the CPU.

07-00 4-11 1/0 Bidirectional Data Bus: Control,
status and interrupt·vector information is transferred via this bus.
.

Interrupt operation of the 8259A falls under five main
categories: vectoring, priorities, triggering, status, and
cascading. Each of these categories use various modes
and commands. This section will explain the operation
of these modes and commands. For clarity of explanation, however, the actual programming of the 8259A isn't
covered in this section but in "Programming the 8259A".
Appendix A is provided as a cross reference between
these two sections.

3.1 INTERRUPT VECTORING
Each IR input of the 8259A has an individual interrupt·
vector address in memory associated with it. Oesigna·
tion of each address depends upon the initial program·
ming of the 8259A. As srated earlier, the interrupt
sequence and addressing of an MCS-80 and MCS·85
system differs from that of an MCS-86 and MCS·88
system. Thus, the 8259A must be initially programmed
in either a MCS·80/85 or MCS·86/88 mode of operation to
insure the correct interrupt vectoring.

41

MC8-8OI85™ Mode
When programmed .in the MCS-80/85 mode, the 8259A
should only be used within an 8080A or an 8085A
system. In this mode the 8080A/8085Awlll handle inter·
rupts in the format described in the "MCS-80-'-8259A or
MCS-85-8259A Overviews."
Upon interrupt request in the MCS-80/85 mode, the
8259A will output to the d~ta bus the opcode for a CALL
Instruction and the address of the desired routine. This
is in response to a .sequence of three INTA pulses
issued by the 8080A/8085A after the 8259A has raised
INT high.
.
,

Th(l MS'B of the interrupt.vector address is placed on the
data bus during the third INTA pulse. Contents of the
third interrupt·vector byte is shown in Figure 9C.
A. FIRST INTERRUPT VECTOR BYTE. MCS8OI85 MODE

07

05

1M

D2

03

01

DO

~I_'________0____0____________0____1-"'

CALL CODE

B. SECOND INTERRUPT VECTOR BYTE. MCSIO/85 MODE

The first INTA pulse to the 8259A enables the CALL
opcode "CD H" onto thl! data bus. It also resolves IR pri·
orltles and effects operation in ~he casc;ade mode,
which will be covered later. Contents of the first
interrupt·vector byte are sh'own In Figure 9~.

III

During the second and third INTA pulses; the 8259A
conveys a 16·bit Interrupt·vector address to the 8080Al
8D85A. The interrupt·vector addresses for all eight levels
are selected when initially programming the 8259A.
However, only one address is needed for programming.
Interrupt·vector addressils of IRO-IR7 are automatically
set at equally spaced Intervals, based on the one pro·
grammed address. Address intervals are user definable
to 4 or 8 bytes apart. If the service routine for a device Is
short It may be possible to fit the entire routine within
an 8·byte interval. Usually, though, the service routines
require more than 8 bytes: So, a 4·byte interval is used to
store a Jump (JMP) instruction which directs the 8080A1
8085A to the appropriate routine. The 8·byte int9rval
maintains compatibility with current, 8080A/80fl5A
Restart (RST) instruction software, while the 4·byte in·
terval is best for a compact jump table. If the 4·byte in·
terval is selected, then the 8259A will automatically
insert bits AO-A4. This leaves A5-A15 to be pro·
grammed by the user. If the 8·byte interval is selected,
the 8259A will automatically insert bits AO-A5. This
leaves only A6-A15 to be programmed by the user.

•3

The LSB of the interrupt·vector address is placed on the
data bus during the second INTA pulse. Figure 9B
shows the contents of the second interrupt·vector byte
for both 4 and 8·byte intervals.

De

D7
7

A7

De
AI

I

A7

AI

S

A7

AI
AI

A7
A7

os

11IWWI.4
1M
03

02

01

DO

AS
AS
AS
ASI

1

1

1

0

1

1

0

1

0
0

0
0
0

0

0
0
0

AS
AS
AS
AS

0
0
0
0

1

1

1

0

0
0

0

I,

1

o.

0
0
0
0

0
0
0
0

DO
0

2

A7

1

A7

AI
AI
AI

0

A7

AI

De
AI

05

1M

03

1

1

1

AI
AI
A6

1

1

0

02
0
0

1

0

1

il

1

0

0

1

0

A7

0
0
0
0

1

0

AI
AI
AI
A6

1

1

07
A7
A7
A7
A7
A7
A7
' A7

0
0

0

0
0
0
0
0

01
0
0
0
0
0
0
0
0

03

02

01

DO

All

AIO

AS

A8

Int_I_.

III
7
I
S

•3
2

1

1

0
0
0
0
0

o'
0

C. THIRD INTERRUPT VECTOR BYTE. MCS8OI15 MODE

07

De

05

AIS

AI.

A13

AI2

Flflure.. lA-C. Interrupt·Vector 8yte. lor 8258A, MCS 80/85 M....

MCSo88I88TM Mode
When programmed in the MCS-86/88 mode, the 8259A
should only be used within an MCS·86 or MCS-88
system. In this mode, the 8086/8088 will handle inter·
rupts in the format described earlier in the "8259A8086/8088 Overview".
Upon Interrupt In the MCS-86/88 mode, the 8259A will
output a Single Interrupt·vector~ to the data bus.
This is in response to only two INTA pulses issued by
the 8086/8088 after the 8259.1. jlas p.ised INT high.
The first INTA pulse is used only fe,r set·up purposes in·
ternal to the 8259A. As in tha MCS-80/85 mode, this set·
up Includes priority resoluliun and cascade mode oper:
atlons which will be covered luter. Unlike the MCS·80/85
mode, no CALL opcode is placed on the data bus.

42

The second INTA pulse is used to' enable the single
interrupt·vector byte onto the data bus. The 8086/8088
uses this interrupt·vector byte to select one of 256 inter·
rupt "types" in 808618088 memory. Interrupt type selec·
tlon for all eight IR levels is made when initially programming the 8259A. However, reference to only one in·
terrupt type is needed for programming. The upper 5 bits
of the Interrupt vector byte are user definable. The lower
3 bits are automatically inserted by the 8259A depend·
Ing upon the IR level.
Contents of the interrupt·vector byte for 8086/8088 type
selection is put on the data bus during the second INTA
'
pulse and is shown in Figure 10.

routine in service. This ISR bit remains set until an EOI
(End·Of·lnterrupt) command is issued to the 8259A.
EOI's will be explained in greater detail shortly.
D7

D8

D5

D4

D3

D2

D1

DO

IR7

T7

T8

TS

T4

T3

1

1

1

0

IR8

T7

T8

TS

T4

T3

1

1

,IRS

T7

T8

TS

T4

T3

1

0

1

IR4

T7

T8

TS

T4

T3

1

0

0

IR3

T7

T8

TS

T4

T3

0

1

1

IR2

T7

T8

TS

T4

T3

0

1

0

IRI

T7

T8

TS

T4

T3

0

0

1

IRO

T7

T8

TS

T4

T3

0

0

'0

3.2 INTERRUPT PRIORITIES
A variety of modes and commands are available for con·
trolling interrupt priorities of the 8259A. All of them are
programmable, that is, they may be changed dynamic·
ally under software control. With these modes and com·
mands, many possibilities are conceivable, giving the
user enough versatility for almost any interrupt con·
trolled application.
Fully Nested Mode
The fully nested mode of operation is a general purpose
priority mode. This mode supports a multilevel·interrupt
structure in which priority order of all eight IR inputs are
arranged from highest to lowest.
Unless otherwise programmed, the fully nested mode is
entered by default upon initialization. At this time, IRO is
assigned the highest priority through IR7 the lowest.
The fully nested mode, however, is not confined to, this
IR structure alone. Once past initialization, other IR in·
puts can be assigned highest priority also, keeping the
multilevel·interrupt structure of the fully nested mode.
Figure 11A-C shows some variations of the priority
structures in the fully nested mode.
IA LEVELS
PAIOAITY

IA7 IAI lAS IA4 IA3 IA2 IAl lAO
76543210

IA LEVELS
PAIOAITY

IA7 IAI lAS IA4 IA3 IA2 IAl lAO
43"2'0765

Figure 12 illustrates the correct usage of interrupt
related instructions' and the interaction ef interrupt
levels in the fully nested mode.
Assuming the IR priority assignment for the example in
Figure 12 is IRO the highest through IR7 the lowest. the
sequence is as follows. During the main program, IR3
makes a request. Since interrupts are enabled, the
microprocessor is vectored to the IR3 service routine.
During the IR3 routine, IR1 asserts a request. Since IR1
has higher priority than IR3, an interrupt is generated.
However, it is not acknowledged because the microprocessor disabled interrupts in response to the IR3 in·
terrupt. The IR1 interrupt is not acknowledged until the
"Enable Interrupts" instruction is executed. Thus the
IR3 routine has a "protected" section of code over
which no interrupts (except non·maskable) are allowed.
The IR1 routine has no such "protected" section since
an "Enable Interrupts" instruction is the first one in its
service routine. Note that in this example the IR1 request must stay high until it is acknowledged. This is
covered in more depth in the "Interrupt Triggering"
section.

----,.a

MfIRIIR! iiia, iA3 1M2 IN1
PAIOAITY~6
. C5 4 3

IA LEVELS

In the fully nested mOde, while an ISR bit is set, all fur·
ther requests of the same or lower priority are inhibited
from generating im interrupt to the microprocessor. A
higher priority request, though, can generate an inter·
rupt, thus vectoring program execution to its service
routine. Interrupts are oniy acknowledged, however, if
the microprocessor has previousiy executed an "Enable
Interrupts" instruction. This is because the interrupt
request pin on the microprocessor gets disabled automatically after acknowledgement of any interrupi. The
assembly language instructions used to enable inter·
rupts are "EI" for 8080Al8085A and "STI" for 808618088.
Interrupts can be disabled by using the instruction "01"
for 8080Al 8085A and "CLI" for 808618088. Whel) a
routine is completed a "return" instruction is executed,
"RET" for 8080Af8085A and "IRET" for 808618088.

IRD

I

2,

Fleu" 11. A-C. Som. Varlallona 01 Priority Structu.. ln tM
Fully N..led Mode

Further explanation of the fully nested mode, in this
section, is linked with information of general 8259A in·
terrupt operations. This is done to ease explanation to
the user in both areas.
In general, when an interrupt is acknowledged, the
highest priority request is determined from the IRR (In·
terrupt Request Register). The interrupt vector is then
placed on the data bus. In addition, the corresponding
bit in the ISR (In·Service Register) is set to deSignate the

43

What is happening to the ISA register? While in the main
program, no ISA bits are set since there aren't any inter·
rupts in service. When the IA3 interrupt is acknowl·
edged, the ISA3 bit is set. When the IA1 interrupt is
acknowledged, both the ISA1 and the ISA3 bits are set,
indicating that neither routine is complete. At this time,
only lAO could generate an interrupt since it is the only
input with a higher priority than those previously in ser·
vice. To terminate the IA1 routine, the routine must
inform the 8259A that it is complete by resetting its ISA
bit. It does this by executing an EOI command. A
"return" instruction then transfers execution back to
the IA3 routine. This allows IAO-IA2 to interrupt the IA3
routine again, since ISA3 is the highest ISA bit set. No
further interrupts occur in the example so the EOI com·
mand resets ISA3 and the "return" instruction causes
the main program to resume at its pre·interrupt location,
ending the example.
A single 8259A is essentially always in the fully nested
mode unless certain programming conditions disturb it.
The following programming conditions can cause the
8259A to go out of the high to low priority structure of
the fully nested mode.
• The automatic EOI mode
• The special mask mode
• A slave with a master not in the special fully nested
mode
These modes will be covered in more detail later,
however, they are mentioned now so the user can be
aware of them. As long as these program conditions
aren't inacted, the fully nested mode remains undis·
turbed.
End of Interrupt
Upon completion of an interrupt service routine the
8259A needs to be notified so its ISA can be updated.
This is done to keep track of which interrupt levels are in
the process of being serviced and their relative priori·
ties. Three different End·Of·lnterrupt (EO I) formats are
available for the user. These are: the non·specific EOI
command, the specific EOI command, and the auto·
matic EOI Mode. Selection of which EOI to use is depen·
dent upon the interrupt operations the user wishes to
perform.
Non·Speclflc EOI Command
A non·specific EOI command sent from the microproc·
essor lets the 8259A know when a service routine has
been completed, without specification of its exact inter·
rupt level. The 8259A automatically determines the inter·
rupt level and resets the correct bit in the ISA.
To take advantage of the non·specific EOI the 8259A
must be in a mode of operation in which it can predeter·
mine in·service routine levels. For this reason the non·
specific EOI command should only be used when the
most recent level acknowledged and serviced is always
the highest priority level. When the 8259A receives a
non·specific EOI command, it simply resets the highest
priority ISA bit, thus confirming to the 8259A that the
highest priority routine of the routines in service is
finished.

44

The main advantage of using the non·specific EOI com·
mand is that IA level specification isn't necessary as in
the "Specific EOI Command", covered shortly.
However, speCial consideration should be taken when
deciding to use the non·specific EOL Here are two pro·
gram conditions in which it is best not used:
• Using the set priority command within an interrupt
service routine.
• Using a special mask mode.
These conditions are covefed in more detail in their own
sections. but are listed here for the users reference.
Specific EOI Command
A specific EOI command sent from the microprocessor
lets the 8259A know when a service routine of a particu·
lar interrupt level is completed. Unlike a non·specific
EOI command, which automatically resets the highest
priority ISA bit, a specific EOI command specifies an
exact ISA bit to be reset. One of the eight IA levels of the
8259A can be specified in the command.
The reason the specific EOI command is needed, is to
reset the ISA bit of a completed service routine when·
ever the 8259A isn't able to automatically determine it.
An example of this type of situation might be it. the
priorities of the interrupt levels were changed during an
interrupt routine ("Specific Aotation"). In this case, if
any other routines were in service at the same time, a
non·specific EOI might reset the wrong ISA bit. Thus the
specific EOI command is the best bet in this case, or for
that matter, any time in which confusion of interrupt
priorities may exist. The specific EOI command can be
used in all conditions of 8259A operation, including
those that prohibit non·specific EOI command usage.

Automatic EOI Mode
When programmed in the automatic EOI mode, the
microprocessor n'o longer needs to issue a command to
notify the 8259A it has completed an interrupt routine.
The 825.9A accomplishes this by performing a non·
specific EOI automatically at the trailing edge of the last
INTA pulse (third pulse in MCS·80/85, second in
MCS·86).
The obvious advantage of the automatic EOI mode over
the other EOI command is no command has to be
issued. In general, this simplifies programming and
lowers code requirements within interrupt routines.
However, special consideration sh.ould be taken when
deciding to use the automatic EOI mode because it
disturbs the fully nested mode. In the automatic EOI
mode the ISA bit of a routine in service is reset right
after it's acknowledged, thus leaving no designation in
the ISA that a sevice routine is being executed. If any in·
terrupt request occurs during this time (and interrupts
are enabled) It will get serviced regardless of its priority,
low or high. The problem of "over nesting" may also
happen In this situation. "Over nesting" is when an IA
Input keeps interrupting its own routine, resulting in un·
necessary stack pushes which could iill the stack in a
worst case condition. This is not usually a desired form
of operation I

So what good is the automatic EOI mode with problems
like those just covered? Well, again, like the other EOls,
selection is dependent upon the application. If interrupts are controlled at a predetermined rate, so as not to
cause the problems mentioned above, the automatic
EOI mode works perfect just the way it is. However, if interrupts happen sporadically at an indeterminate rate,
the automatic EOI mode should only be used under the
following guideline:
• When using the automatic EOI mode with an indeterminate interrupt rate, the microprocessor should
keep its interrupt request input disabled during
execution of service routines.

A

ISR STATUS
PRIORITY

I±B
765

157 158 ISS 154 153 152 151 ISO
I
0 0 0 0
4 3 2 I
0

I

LOWES! PRIORITY

B

ISR STATUS
PRIORITY

1

1

HIGHEST PRIORITY

157 156 ISS 154 153 152 151 ISO
I
0 0 0 0 0 0
2 I
0 7 6 5 4 3

I0

~

HIGHEST PRIORITY

BEFORE
COMMAND

I

AFTER
COMMAND

I

LOWEST PRIORITY

Figure 13. A-B. Rotate on Non·spaclllc EOI Command Example

By doing this, higher priority interrupt levels will be serviced only after the completion of a routine in service.
This guideline restores the fully nested structure in
regards to the IRR; however, a routine in-service can't be
interrupted.

Automatic Rotation -

Equal Priority

Automatic rotation of priorities serves in applications
where the interrupting devices are of equal priority,
such as communications channels. The concept is that
once a peripheral is serviced, all other equal priority
peripherals should be given a chance to be serviced
before the original peripheral is serviced again. This is
accomplished by automatically assigning a peripheral
the lowest priority after being serviced Thus, in worst
case, the device would have to wait until all other
devices are serviced before being serviced again.
There are two methods of accomplishing automatic
rotation. One is used in conjunction with the nonspecific EOI, "rotate on non-specific EOI command".
The other is used with the automatic EOI mode, "rotate
in automatic EOI mode".

Rotate In Automatic EOI Mode
The rotate in automatic EOI mode works much like the
rotate on non-specific EOI command. The main differ·
ence is that priority rotation is done automatically after
the last INTA pulse of an interrupt request. To enter or
exit this mode a rotate·in·automatic·EOI set command
and rotate·in·automatic·EOI clear command is provided.
After that, no commands are needed as with the normal
automatic EOI mode. However, it must be remembered,
when using any form of the automatic EOI mode, spe·
cial consideration should be taken. Thus, the guideline
for the automatic EOI mode also stands for the rotate in
automatic EOI mode.
Specific Rotation -

Specific Priority

Specific rotation gives the user versatile capabilities in
interrupt controlled operations. It serves in those ap·
plications in which a specific device's interrupt priority
must be altered. As opposed to automatic rotation
which automatically sets priorities, specific rotation is
completely user controlled. That is, the user selects
which interrupt level is to receive lowest or highest
priority. This can be done during the main program or
within interrupt routines. Two specific rotation com·
mands are available to the user, the "set priority com·
mand" and the "rotate on specific EOI command."

Rotate on Non-Specific EOI Command

Sat Priority Command

When the rotate on non·specific EOI command is
issued, the highest ISR bit is reset as in a normal non·
specific EOI command. After it's reset though, the cor·
responding IA level is assigned lowest priority. Other IA
priorities rotate to conform to the fully nested mode
based on the newly assigned low priority

The set priority command allows the programmer to
assign an IR level the lowest priority. All other interrupt
levels will conform to the fully nested mode based on
the newly assigned low priority.

Figures 13A and B show how the rotate on non·specific
EOI command effects the interrupt priorities. Let's
assume the IA priorities were assigned with lAO the
highest and IR7 the lowest, as in 13A. IRS and IA4 are
already in service but neither is completed. B~ing the
higher priority routine, IA4 is necessarily the routine
being executed. During the IA4 routine a rotate on non·
specific EOI command is executed. When this' happens,
bit 4 in the ISA is reset. IR4 then becomes the lowest
priority and IA5 becomes the highest as in 13B.

An example of how the set priority command works is
shown In Figures 14A and 14B. These figures show the
status of the ISA and the relative priorities of the Inter·
rupt levels before and after the set priority command.
Two interrupt routines are shown to be in service in
Figure 14A. Since IA2 is the highest priority, it is
necessarily the routine being executed. During the IR2
routine, priorities are altered so that IR5 is the highest.
This is done simply by issuing the set priority command
to the 8259A. In this case, the command specifies IA4 as
being the lowest priority. The result of this set priority
command is shown in Figure 14B. Even though IA7 now

45

Int.rrupt M.sklng
has higher priority than IR2, it won't be acknowledged
, until the IR2 routine is finished (via EOI). This is because
priorities are only resolved upon an interrupt request or
an interrupt acknowledge sequence. If a higher priority
request occurs during the IR2 routine, then priorities are
resolved and the highest will be acknowledged.

A

ISR STATUS
PRIORITY

157 158 ISS IS~ 153 152 151 ISO
1 0 0 0 0
,
0 01 BEFORE
7 6 5 4 3 2 , =yJ COMMAND

I

1

LOWEST PRIORITY

B

ISR STATUS
PRIORITY

1

HIGHEST PRIORITY

° 0l

IS7 156 ISS IS4 IS3 IS2 lSI ISO
I,
0 0 0 0 ,
7"'s-S 4 3

rr::-r----o ~t

HIGHEST PRIORITY

AFTER
COMMAND

I
LOWEST PRIORITY

Figure 14. A-B. Set PrlDrity CDmmlnd EXlmpl1

Disabling or enabling interrupts can be done by other
means than just controlling, the microprocessor's inter·
rupt request pin. The 8259A has an IMR (Interrupt Mask
Register) which enhances interrupt control capabilities.
Rather than all interrupts being disabled or enabled at
the same time, the IMR allows individual IR masking.
The IMR is an 8·bit register, bits 0-7 directly correspond
to IRO-IR7. Any IR input can be masked by writing to the
IMR and setting the appropriate bit. Likewise, any IR in·
put can be enabled by clearing the correct IMR bit.
There are various uses for masking off individual IR in·
puts. One example is when a portion of a main routine
wishes only to be interrupted by specific interrupts.
Another might be disabling higher priority interrupts for
a portion of a lower priority service routine. The possi·
bilities are many.
When an interrupt occurs while its IMR bit is set, it isn't
necessarily forgotten. For, as stated earlier, the IMR
acts only on the output of the IRR. Even with an IR input
masked it is still possible to set the IRR. Thus, when
resetting an IMR, if its IRR bit is set it will then generate
an interrupt. This is providing, of course, that other
priority factors are taken into consideration and the IR
request remains active. If the IR request is removed
before the IMR is reset, no interrupt will be acknowl·
edged.

Specl., Mask Mod.

When completing a service routine in which the set
priority command is used, the correct EOI must be
issued. The non·specific EOI command shouldn't be
used in the same routine as a set priority command.
This is because the non·specific EOI command resets
the highest ISR bit, which, when using the set priority
command, is not always the most recent routine in ser·
vice. The automatic EOI mode, on the other hand, can be
used with the set priority command. This is because it
automatically performs a non·specific EOI before the
set priority command can be issued. The specific EOI
command is the best bet in most cases when using the
set priority command within a routine. By resetting the
specifiC ISR bit of a routine being completed, confusion
is eliminated.

Rot.t. on Sp.clflc EOI Comm.nd
The rotate on specific EOI command is literally a com·
bination of the set priority command and the specific
EOI command. Like·the set priority command, a speci·
fied IR level is assigned lowest priority. Like the specific
EOI command, a specified level will be reset in the ISR.
Thus the rotate on specific EOI command accomplishes
both tasks in only one command.

46

If It Is not necessary to change IR priorities prior to the
end of an interrupt routine, then this command is advan·
tageous. For an EOI command must be executed any·
way (unless in the automatic EOI mode), so why not do
both at the same time?

In various cases, it may be deSirable to enable interrupts
of a lower priority than the routine in service. Or, in other
words, allow lower priority devices to generate inter·
rupts. However, in the fully nested mode, all IR levels of
priority below the routine in service are inhibited, So
what can be done to enable them?
Well, one method could be using an EOI command
before the actual completion of a routine in service, But
beware, doing this may cause an "over nesting" prob·
lem, similar to in the automatic EOI mode, In addition,
resetting an ISR bit is irreversible by software control,
so lower priority IR levels could only be later disabled by
setting the IMR.
A much better solution is the special mask mode. Work·
ing in conjunction' with the IMR, the special mask mode
enables interrupts from all levels except the level in ser·
vice. This is done by masking the level that is in service
and then issuing the special mask mode command.
Once the special mask mode is set, it remains in effect
until reset.
Figure 15 shows how to enable lower priority interrupts
by using the Special Mask Mode (SMM). Assume that
IRO has highest priority when the main program is inter·
rupted by IR4, In the IR4 service routine an enable inteJ'
rupt instruction is executed, This, only allows higher
priority interrupt requests to interrupt IR4 in the normal
fully nested mode. Further in the IR4 routine, bit 4 of the
IMR is masked and the special mask mode is entered.
Priority operation is no longer in the fully nested mode,
All interrupt levels are enabled except for IR4. To leave
the special mask mode, the sequence is executed in
reverse.

Level Triggered Mode

MAIN PROGRAM

EI OR STI

IR4 SERVICE
ROUTINE
IR4_
EI OR STI

IRO-3 ENABLED
IR4-7 DISABLED

MASK IR4

SET SMM

IRO-3. 5-7 ENABLED
IR4 DISABLED

RESET SMM

IRO-3 ENABLED
IR4-7 DISABLED

EOI

Precautions must be taken when exiting an interrupt
service routine which has used the special mask mode.
A non-specific EOI command can't be used when in the
special mask mode. This is because a non-specific
won't clear an ISR bit of an interrupt which is masked
when in the special mask mode. In fact, the bit will appear invisible. If the special mask mode is cleared
before an EOI command is issued a non-specific EOI
command can be used. This could be the case in the example shown in Figure 15, but, to avoid any confusion
it's best to use the specific EOI whenever using the
special mask mode.
It must be remembered that the special mask mode applies to all masked levels when set. Take, for instance.
IR1 interrupting IR4 in the previous example. If this happened while in the special mask mode, and the IR1
routine masked itself, all interrupts would be enabled
except IR1 and IR4 which are masked.

3_3 INTERRUPT TRIGGERING
There are two classical ways of sensing an active interrupt request: a level sensitive input or an edge sensitive
input. The 8259A gives the user the capability for either
method with the edge triggered mode and the level triggered mode. Selection of one of these interrupt triggering methods is done during the programmed initialization of the 8259A.

When in the level triggered mode the 8259A will recognize any active (high) level on an IR input as an interrupt
request. If the IR input remains active after an EOI command has been issued (resetting its ISR bit), another interrupt will be generated. This is providing of course, the
processor INT pi8 is enabled_ Unless repetitious interrupt generation is desired, the IR input must be brought
to an inactive state before an EOI command is issued in
its service routine. However, it must not go inactive so
soon that it disobeys the necessary timing requirements shown in Figure 16. Note that the request on the
IR input must remain until after the falling edge of the
first INTA pulse. If on ant..!!!..input, the request goes
inactive before the first INTA pulse, the 8259A will
respond as if IR? was active. In any design in which
there's a possibility of this happening, the IR? default
feature can be used as a safeguard. This can be accomplished by using the IR? routine as a "clean-up routine"
which might recheck the 8259A status or merely return
program execution to its pre-interrupt location.
Depending upon the particular design and application,
the level triggered mode has a number of uses. For one,
it provides for repetitious interrupt generation. This is
useful in cases when a service routine needs to be continually executed until the interrupt request goes inactive. Another possible advantage of the level triggered
mode is it allows for "wire-OR'ed" interrupt requests.
That is, a number of interrupt requests using the same
IR input. This can't be done in the edge triggered mode,
for if a device makes an interrupt request while the IR input is high (from another request), its transition will be
"shadowed". Thus the 8259A won't recognize further. interrupt requests because its IR input is already high.
Note that when a "wire-OR'ed" scheme is used, the actual requesting device has to be determined by the software in the service routine.
Caution should be taken when using the automatic EOI
mode and the level triggered mode together. Since in
the automatic EOI mode an EOI is automatically performed at the end of the interrupt acknowledge sequerice, if the processor enables interrupts while an IR
input is still high, an interrupt will occur immediately. To
avoid this situation interrupts should be kept disabled
until the end of the service routine or until the IR input
returns low.

Edge Triggered Mode

When in the edge triggered mode, the 8259A will only
recognize interrupts if generated by an inactive (low) to
active (high) transition on an IR input. The edge triggered mode incorporates an edge lockout method of
operation_ This means that after the rising edge of an
interrupt request and the acknowledgement of the request, the positive level of the IR input won't generate
further interrupts on this level. The user needn't worry
about quiCkly removing the request after acknowledgement in fear of generating further interrupts as might be
the case in the level triggered mode. Before another interrupt can be generated the IR input must return to the
inactive state.

47

IR

-+-.J

INT _ _ _ _

INTA-----+-----~
8080/8085

LATCH"
ARMED

EARLIEST IR
CAN BE REMOVED

'EDGE TRIGGERED MODE ONLY

LATCH"
ARMED

Figure 16. IR Triggering Timing Requirement.

Referring back to Figure 16, the timing requirements for
interrupt triggering is shown. Like the level triggered
mode, in the edge triggered mode the request on the IR
input must remain active until after the falling edge of
the first INTA pulse for that particular interrupt. Unlike
the level triggered mode, though, after the interrupt
request is acknowledged its IRR latch is disarmed. Only
after the IR input goes inactive will the IRR latch again
become armed. making it ready to receive another inter·
rupt request (in the level triggered mode, the IRR la'tch is
always armed). Because of the way the edge triggered
mode functions, it is best to use a positive level with a
negative pulse to trigger the IR requests. With this type
of input, the trailing edge of the pulse causes the inter·
rupt and the maintained positive level meets the neces·
sary timing requirements (remaining high until after the
interrupt acknowledge occurs). Note that the IR7 default
feature mentioned in the "level triggered mode" section
also works for the edge triggered mode.
Depending upon the particular design and application,
the edge triggered mode has various uses. Because of
its edge lockout operation, it is best used in those
applications where repetitious interrupt generation isn't
desired. It is also very useful in systems where the inter·
rupt request is a pulse (this should be in the form of a
negative pulse to the 8259A). Another possible advan·
tage is that it can be used with the automatic EOI mode
without the cautions in the level triggered mode. Over·
all, in most cases, the edge triggered mode simplifies
operation for the user, since the duration of the interrupt
request at a positive level is not usually a factor.
3.4 INTERRUPT STATUS

By means of software control, the user can interrogate
the status of the 8259A. This allows the reading of the
internal interrupt registers, which may prove useful for
interrupt control during service routines. It also pro·
vides for a modified status poll method of device moni·
toring, by using the poll command. This makes the
status of the internal IR inputs available to the user via
software control. The poll command offers an alterna·
tive to the interrupt vector method, especially for those
cases when more than 64 interrupts are needed.

48

Reading Interrupt Registers
The contents 01- each 6·bit interrupt register, IRR, ISR,
and IMR, can be read to update the user's program on
the present status of the 8259A. This can be a versatile
tool in the decision making process of a service routine,
giving the user more control over interrupt operations.
Before delving into the actual process of reading the
registers, let's briefly review their general descriptions:
IRR (Interrupt
Request Reqister)

Specifies all interrupt levels reo
questing service.

ISR (In·Service
Register)

Specifies all interrupt levels
which are being serviced.

IMR (Interrupt
Mask Register)

Specifies all interrupt levels that
are masked.

To read the contents of the IRR or ISR, the user must
first issue the appropriate read register command (read
IRR or read ISR) to the 8259A. Then by applying a RD
pulse to the 8259A (an INput instruction), the contents
of. the desired register can be acquired. There is no need
to issue a read register command every time the IRR or
ISR is to be read. Once a read register command is
received by the 8259A, it "remembers" which register
has been selected. Thus, all that is necessary to read
the contents· of the same register more than once is the
RD pulse and the correct addressing (AO = 0, explained
in ':Programming the 8259A"). Upon initialization, the
selection of registers defaults to the IRR. Some caution
should be taken when using the read register command
in a system that supports several levels of interrupts. If
the higher priority routine causes an interrupt betwe6n
the read register command and the actual input of the
register contents, there's no guarantee that the same
register will be selected when it returns. Thus it is best
in such cases to disable interrupts during the operation.
Reading the contents of the IMR is different than read·
Ing the IRR or ISR. A read register command is not
necessary when reading the IMR. This is because the
IMR can be addressed directly for both reading and
writing. Thus all that the 8259A requires for reading the
IMR is a RD pulse and the correct addressing (AO= 1,
explained in "Programming the 8259A").

Poll Command
As mentioned towards the beginning of this application
note, there are two methods of servicing peripherals:
status polling and interrupt servicing. For most applications the interrupt service method is best. This is
because it requires the least amount of CPU time, thus
increasing system throughput. However, for certain applications, the status poll method may be desirable.
For this reason, tne 8259A supports polling operations
with the poll command. As opposed to the conventional
method of polling, the poll command offers improved
device servicing and increased throughput. Rather than
having the processor poll each peripheral in order to
find the actual device requiring service, the processor
polls the 8259A. This allows the use of all the previously
mentioned priority modes and commands. Additionally,
both polled and interrupt methods can be used within
the same program.
To use the poll command the processor must first have
its interrupt request pin disabled. Once the poll com·
mand is issued, the 8259A will treat the next (CS quali·
fied) RD pulse issued to it (an INput instruction) as an interrupt acknowledge. It will then set the appropriate bit
in the ISR, if there was an interrupt request, and enable a
special word onto the data bus. This word shows
whether an interrupt request has occurred and the
highest priority level requesting service. Figure 17
shows the contents of the "poll word" which is read by
the processor. Bits WO-W2 convey the binary code of
the highest priority level requesting service. Bit I desig'
nates whether or not an interrupt request is present. If
an interrupt request is present, bit I will equal 1. If there
isn't an interrupt request at all, bit I will equal 0 and bits
WO-W2 will be set to ones. Service to the requesting
device is achieved by software decoding the poll word
and branching to the appropriate service routine. Each
time tne 8259A is to be polled, the poll command must
be written before reading the poll word.

The poll command is useful in various situations. For in·
stance, it's a good alternative when memory is very
limited, because an interrupt-vector table isn't needed.
Another use for the poll command is when more than 64
interrupt levels are needed (64 is the limit when cascading 8259's). The only limit of interrupts using the poll
command is the number of 8259's that can be addressed
in a particular s'tstem. Still another application of the
poll command might be when the INT or INTA Signals
are not available. This might be the case in a large
system where a processor on one card needs to use an
8259A on a different card. In this instanc~, the poll command is the only way to monijor the interrupt devices
and slill take advantage of the 8259A's prioritizing
features. For those cases when the 8259A is using the
poll command only and not the interrupt method, each
8259A must receive an initialization sequence (interrupt
vector). This must be done even though the interrupt
vector features of the 8259A are not used. In this case,
the interrupt vector specified in the initialization
sequence could be a "fake".

-

~
-

-

-W2W1WO

WO·W2 = BINARY CODE OF HIGHEST
PRIORITY LEVEL REQUESTING SERVICE
1=1 IF AN INTERRUPT OCCURREO

Figure 17. Poll Word

3.5 INTERRUPT CASCADING
As mentioned earlier, more than one 8259A can be used
to expand the priority interrupt scheme to up to 64 levels
without additional hardware. This method for expanded
interrupt capability is called "cascading". The 8259A
supports cascading operations with the cascade mode.
Additionally, the special fully nested mode and the buffered mode are available for increased flexibility when
cascading 8259A's in certain applications.
Cascade Mode
When programmed in the cascade mode, basic operation consists of one 8259A acting as a master to the
others which are serving as slaves. Figure 18 shows a
system containing a master and two slaves, providing a
total of 22 interrupt levels.
A specific hardware set-up is required to establish
operation in the cascade mode. With Figure 18 as a reference, note that the master is deSignated by a high on
the SPJEN pin, while the SP/EN pins of the slaves are
grounded (thiS can also be done by software, see buf·
fered mode). Additionally, the INT output pin of each
slave is connected to an IR input pin of the master. The
CASO-2 pins for all 8259A's are paralleled. These pins
act as outputs when the 8259A is a master and as inputs
for the slaves. Serving as a private 8259A bus, they control which slave has control of the system bus for inter·
rupt vectoring operation with the processor. All other
pins are connected as in normal operation (each 8259A
receives an INTA pulse).
Besides hardware set·up requirements, all 8259A's must
be software programmed to work in the cascade mode.
Programming the cascade mode is done during the in·
itialization of each 8259A. The 8259A that is selected as
master must receive specification during its initialization as to which of its IR· inputs are connected to a
slave's INT pin. Each slave 8259A, on the other hand,
must be designated during its initialization with an 10 (0
through 7) corresponding to which of the master's IR inputs its INT pin is connected to. This is all necessary so
the CASO-2 pins of the masters will be able to address
each individual slave. Note that as in normal operation,
each 8259A must also be initialized to give its 1(-1 inputs
a unique interrupt vector. More detail on the [',ecessary
programming of the cascade mode is explained in "Pro·
gramming the 8259A".
Now, with background information on both hardware
and software for the cascade mode, let's go over the

49

ADDRESS BUS (161

1

CONTROL BUS

INT REO

\

DATA BUS (8)

---

- .--

--

---

-

-

--I-

I

I -I--

--

I -I--

---

\----

I -I--

~

'0

CS

DO·7

iNTA

INT
CASO

8259A .
SLAVE A

CASt

1-

CAS2

1-

~rn7

6

GrO r

III r r II

7

I

6

5

5

4

4

3

3

2

2

1

1

0

0

'0

CS

I-

I-

00·7

i'N'fA

INT
CASO

8259A
SLAVE B

CAS 1
CAS2

~rn7

G!O

•

5

4

5

4

3

2

1

0

I 1• 1 I!I! 1
7

0

CS
CASO

'0

CAS 1

00·7

INTA

INT

8259A
MASTER

CAS2

~mM7M6

M5 M4 M3 M2 Ml MO

LLl.11

I
INTERRUPT REQUESTS

5

4

I 11

3 2

1

0

I

Figure 18. C.sc.ded 8259A'S 22 Interrupt Le.ets

sequence of events that occur during a valid interrupt
request from a slave. Suppose a slave IR input has
received an interrupt request. Assuming this request is
higher priority than other requests and in·service levels
on the slave, the slave's INT pin is driven high. This
signals the master of the request by causing an interrupt request on a deSignated IR pin of the master. Again,
assuming that this request to the master is higher priori·
ty than other master requests arid in-service levels
(possibly froin other slaves), the master's INT pin is
pulled high, interrupting the processor.
The interrupt acknowledge sequence appears to the
processor the same as the non-cascading interrupt
acknowledge sequence; however, it's different among
the 8259A's. The first INTA pulse is used by all the
8259A's for internal set-up purposes and, If in the
808018085 mode, the master will place the CALL opcode
on the data bus. The first INTA pulse also signals the
master to place the requesting slave's 10 code on the
CAS lines. This turns control over to the slave for the
rest of the interrupt acknowledge sequence, plaCing the
appropriate pre· programmed interrupt vector on the
data bus, completing the interrupt request.
During the interrupt acknowledge sequence, the cor·
responding ISR bit .of both the master and the slave get
set. This means two.EOI commands must be issued (if
not in theautomatlc EOI mode), one for the master and
one for the slave.
Special conSideration should be taken when mixed
interrupt requests are assigned to a master 8259A; that
is, when some of the master's IR inputs are used for
slave interrupt requests and some are used for individ·
ualinterrupt requests. In this type of structure, the
master's IRO must not be used for. a slave. This is
because when an IR input that isn't initialized as a slave
receives an interrupt request, the CASO-2 lines won'j be
activated, thus staying in the default condition addressing for IRO (slave IRO). If a slave is connected to the
master's IRO when a non-slave interrupt occurs on
another master IR input, erroneous conditions may

50

result. Thus IRO should be the last choice when assign·
ing slaves to IR inputs.
Special Fully Nested Mode
Depending on the application, changes in the nested
structure of the cascade mode may be desired, This is
because the nested structure of a slave 8259A' differs
from that of the normal full1 nested mode. In the cas'
cade mode, if a slave receives a higher priority interrupt
request than one which is inservice (through the same
slave), it won't be recognized by the master. This is
because the master's ISR bit is set, ignoring all requests
of equal or lower priority. Thus, in this case, the higher
priority slave interrupt won't be serviced until after the
master's ISR bit is reset by an EOI command. This is
most likely after the completion of the lower priority
routine.
If the user wishes to have a truly fully nested structure
within a slave 8259A, the special fully nested mode
should be used. The special fully nested mode is programmed in the master only. This is done during the
master's" initialization. In this mode the master will
ignore only those interrupt requests of lower priority
than the set ISR bit and will respond to all requests of
equal or higher priority. Thus if a slave receives a higher
priority request than one in service, it will be recognized.
To insure proper interrupt operation when using the
special fully nested mode, the software must determine
if any other slave interrupts are still in service before
issuing an EOI command to the master. This is done by
resetting the appropriate slave ISR bit. with an EOI and
then reading its ISA. If 11)8 ISR contains all zeros. there
aren't any other interrupts from the slave in service and
an EOI command can be sent to the master. If; the ISR
isn't all zeros, an EOI command shouldn't be sent to the
master. Clearing the master's ISR bit with an EOI command while there are still slave interrupts in service
would allow lower priority interrupts to be recognized at
the master. An example of this process is shown in the
second application in the "Applications Examples" section.

4. PROGRAMMING THE 8259A
Programming the 8259A is accomplished by using two
types of command words: Initialization Command
Words (ICWs) and Operational Command Words
(OCWs). All the modes and commands explained in the
previous section, "Operation of the 8259A", .are pro·
grammable using the ICWs and OCWs (see Appendix A
for cross reference). The ICWs are issued from the proc·
essor in a sequential format and are used to set·up the
8259A in an initial state of operation. The OCWs are
issued as needed to vary and control 8259A operation.
Both ICWs and OCWs are sent by the processor to the
8259A via the data bus (8259A CS = 0, WR = 0). The
8259A distinguishes between the different ICWs and
OCWs by the state of its AO pin (controlled by processor
addressing), the sequence they're issued in (ICWs only),
and some dedicated bits among the ICWs and OCWs.
Those bits which are dedicated are indicated so by fixed
values (0 or 1) in the corresponding ICW or OCW pro·
gramming formats which are covered shortly. Note,
when issuing either ICWs or OCWs, the interrupt
request pin of the processor should be disabled.

The ICW programming format, Figure 21, shows bit
designation and a short definition of each ICW. With the
ICW format as reference, the functions of each ICW will
now be explained individually.

NO (SNGL. 1)

4.1 INITIALIZATION COMMAND WORDS (lCWs)
Before normal operation can begin, each 8259A in a
system must be initialized by a sequence of two to four
programming bytes called ICWs (Initialization Com·
mand Words). The ICWs are used to set·up the neces·
sary conditions and modes for proper 8259A operation.
Figure 20 shows the initialization flow of the 8259A.
Both ICW1 and ICW2 must be issued for any form of
8259A operation. However, ICW3 and ICW4 are used
only if designated so in ICW1. Determining the neces·
sity and use of each ICW is covered shortly in individual
groupings. Note that, once intialized, if any program·
ming changes within the leWs are to be made, the entire
ICW sequence must be reprogrammed, not just an indio
viduallCW.
Certain internal set·up conditions occur automatically
within the 8259A after the first ICW has been issued.

NO (IC4=O)

Figure 20. 1"lllan.. llo" Flow

InlllallZ8tlon Command Word Format
'CW'

These are:

1 ICWCNUOEO
O' NO ICWUII(EOEO

A. Sequencer logic is set to accept the remain ng ICWs
as designated in ICW1.

I'SINOlE

o • CASCADE "<'IOOE

B. The ISR (In·Service Register) and IMR (Interrupt Mask
Register) are both cleared.

CALL INTERVAL
1· INTERVAL OF ..

C. The special mask mode is reset.

o·

.foITERVAL OF'

D. The rotate in automatic EOI mode flip·flop is cleared.
E. The IAR (Interrupt Request Register) is selected for
the read register command.
F. If the IC4 bitequals 0 in ICW1, all functions in ICW4
are cleared; 8080/8085 mode is selected by default.
G. The fully nested mode is entered with an initial prior·
ity assignment of IRa highest through IR7 lowest.

'CW'

H. The edge sense latch of each IR priority cell is
cleared, thus requiring a low to high transition to
generate an interrupt (edge triggered mode effected
only).

51

ICWl ,MASH III DIVICI)

ADI:

The ADI bit is used to specify the address in·
terval for the MCS-80/85 mode. If a 4-byte ,ad·
dress interval is to be used, ADI must equal 1.
For an 8-byte address interval, ADI must equal
O. The state of ADI is ignored when the 8259A
is in the MCS·86/88 mode.

LTIM:

The LTIM bit is used to select between the two
IR input triggering modes. If LTIM = 1, the level
triggered mode is selected. If LTIM = 0, the
edge triggered mode is selected.

I" I""'U' HAS" SL .. YI
'" I~UT OOISNaT HAVI
"SL"VI

~

~

,

ICWllSt
~

"vi

~

DIVIC('
~

~

~

~

I I I I .,I I I '".1 ,oj '".J
,

L

H : ,

0

,

... ,

0

,

,

0

0

0

o ,

SIAvl .0'

,,,

o
o

I
\)

0

,

0

,

,,
, , ,

0

>,lie Slit> 88 MIHJl

MrSIiO

I

n

W,~l()l}£

"lITO (01
~OHMAl

(Ill

---_._-_.....
NOTE 1
SLAVE 10 IS EOUAL TO THE CORRESPONDING MASTER lR INPUT

I

SOMe OF THE TERMINOLOGY USED MAY DIFFER SLIGHTLY FROM EXISTING 8251A
DATA SHEETS. TtflS IS DONE TO BETTER CLARIFY AND EXPLAIN THE PROGRAM·
MING OF THE 8258A, THE OPERATIONAL RESULTS REMAIN THE SAME.
i

i

Figure 21. Inltlallzallon Command Word. (ICWS, Programming Format

leW1 and ICW2
Issuing ICW1 and ICW2 is the minimum amount of pro·
gramming needed for any type of 8259A operation. The
majority of bits within these two ICWs are used to desig·
nate the interrupt vector starting address. The remain·
ing bits serve various purposes. Description of the ICW1
and ICW2 bits is as follows:

IC4:

SNGL:

52

The IC4 bit is used to designate to the 8259A
whether or not ICW4 will be issued. If any of
the ICW4 operations are to be used, ICW4
must equal 1. If they aren't used, then ICW4
needn't be issued and IC4 can equal O. Note
that if IC4 = 0, the 8259A will assume operation
in the MCS-80/85 mode.

The SNGL bit is used to designate whether or
not the 8259A is to be used alone or in the cas·
cade mode. If the cascade mode is desired,
SNGL must equal O. In doing this, the 8259A
will accept ICW3 for further cascade mode pro·
gramming. If the 8259A is to be used as the
Single 8259A within a system, the SNGL bit
must equal 1; ICW3 won't be accepted.

A5-A15: The A5-A15 bits are used to select the inter·
rupt vector address when in the MCS·80/85
mode. There are two programming formats
that can be used to dp this. Which one is im·
plemented depends upon the selected address
interval (AD I). If ADI is set for the 4-byte inter·
val, then the 8259A will automatically insert
AO-A4 (AO, A1=0 and A2, A3, A4=IRO-7).
Thus A5-A15 must be user selected by pro·
gramming the A5-A 15 bits with the desired ad·
dress. If ADI is set for the 8-byte interval, then
AO-A5 are automatically inserted (AO, A 1,
A2 = 0 and A3, A4, A5 = IRO-7). This leaves
A6-A15 to be selected by programming the
A6-A 15 bits with the desired address. The
state of bit 5 is ignored in the latter format.

T3-T7:

The T3-T7 bits are used to select the interrupt
type when the MCS-86/88 mode is used. The
programming of T3-T7 selects the upper 5
bits. The lower 3 bits are automatically in·
serted, corresponding to the IR level causing
the interrupt. The state of bits A5-A 10 will be
ignored when in the· MCS·86/88 mode. Estab·
lishing the actual memory address of the inter·
rupt is shown in Figure 22.

("I ,.1 T~ I,.1 'II
I

'

I
I

'
I

I

-~::EE:",~:~'~v~:

~

I

I

I

I

r-...J

r---'

-

(,,1,.1 T, I,.1 'I! T11', I Tol ,
'

::O::oo""....

EDI

~..Eu~~r.:;~~.I~L~~:~~"'TED'" I2S1AI
CO"PLETE 1OMI1OiI1NUtII."'UP' TYPE

10 10 10 I01"IT,ITs!,.1 Tllr,l T,! Tol 0 I01_~Er~~:~p~DrD.,~~S'~~:E~1OM

Flour. 22. Elt.blllhing M.mory Addr... d' 8088Iaoaa Int.rrupt Type

ICW3
The 8259A will only accept ICW3 if programmed in the
cascade mode (ICW1, SNGL = 0). ICW3 is used for
specific programming within the cascade mode. Bit
definition of ICW3 differs depending on whether the
8259A is a master or a slave. Definition of the ICW3 bits
is as follows:
SO-7
(Master):

IDO-102
(Slave):

If the 8259A is a master (either when the
SP/EN pin is tied high or in the buffered
mode when MIS = 1 in ICW4), ICW3 bit definition is SO-7, corresponding to "slave 0-7".
These bits are used to establish which IA inputs have slaves connected to them. A 1
designates a slave, a a no slave. For exam·
pie, if a slave was connected to IA3, the S3
bit should be set to a 1. (SO) should be last
choice for slave designation.
If the 8259A is a slave (either when the SP/EN
pin is low or in the buffered mode when
MIS = a in ICW4), ICW3 bit definition is used
to establish its individual identity. The 10
code of a particular slave must correspond
to the number of the masters IA input it is
connected to. For example, if a slave was
connected to I A6 of the master, the slaves
IDO-2 bits should be set to 100 = 0, 101 = 1,
andID2=1.

ICW4
The 8259A will only accept ICW4 if it was selected in
ICW1 (bit IC4 = 1). Various modes are offered by using
ICW4. Bit definition of ICW4 is as follows:
"PM:

The "PM bit allows for selection of either the
MCS·80/85 or MCS·86/88 mode. If set as a 1 the
MCS-86/88 mode is selected, if a 0, the
MCS-80/85 mode is selected.

AEOI:

The AEOI bit is used to select the automatic
end of interrupt mode. If AEOI = 1, the
automatic end of interrupt mode is selected. If
AEOI = 0, it isn't selected; thus an EOI command must be used during a service routine.

MIS:

The MIS bit is used in conjunction with the buf·
fered mode. If in the buffered mode, MIS
defines whether the 8259A is a master or a
slave. When MIS is set to a 1, the 8259A
operates as the master; when MIS is 0, it
operates as a slave: If not programmed in the
buffered mode, the state of the MIS bit is
ignored.

BUF:

The BUF bit is used to designate operation in
the buffered mode, thus controlling the use of
the SP/EN pin. If BUF is set to a 1, the buffered
mode is programmed and SP/EN is used as a
transceiver enable output. If BUF is 0, the buf·
fered mode isn't programmed and SP/EN is
used for masterlslave selection. Note if ICW4
i.sn't programmed, SP/EN is used for masterl
slave selection.

SFNM:

The SFNM bit designates selection of the
special fully nested mode which is used in
conjunction with the cascade mode. Only the
master should be programmed in the special
fully nested mode to assure a truly fully nested
structure among the slave IA inputs. If SFNM
is set to a 1, the special fully nested mode is
selected; if SFNM is 0, it is not selected.

4.2 OPERATIONAL COMMAND WORD (OCWs)
Once initialized by the ICWs, the 8259A will most likely
be operating in the fully nested mode. At this point,
operation can be further controlled or modified by the
use of OCWs (Operation Command Words). Three
OCWs are available for programming various modes and
commands. Unlike the ICWs, the OCWs needn't be in
any type of sequential order. Aather, they are issued by
the processor as needed within a program.
Figure 23, the OCW programming format, shows the bit
designation and short definition of each OCW. With the
OCW format as reference, the functions of each OCW
will be explained individually.
OCW1
OCW1 is used solely for 8259A masking operations. It
provides a direct link to the IMA (Interrupt Mask Aegis·
ter). The processor can write to or read from the IMA via
OCW1. The OCW1 bit definition is as follows:
MO-M7: The MO-M7 bits are used to control the mask·
ing of IA inputs. If an M bit is set to a 1, it will
mask' the corresponding IA input. A a clears
the mask, thus enabling the IA input. These
bits convey the same meaning when being
read by the processor for status update.
OCW2
OCW2 is used for end of interrupt, automatic rotation,
and specific rotation operations. Associated commands
and modes of these operations (with the exception of
AEOI initialization), are selected using the bits of OCW2
in a combined fashion. Selection of a command or
mode should be made with the corresponding table for
OCW2 in the OCW programming format (Figure 20),
rather than on a bit by bit basis. However, for com·
pleteness of explanation, bit definition of OCW2 is as
follows:
LO-L2:

The .LO-L2 bits are used to designate an inter·
rupt level (0-7) to be acted upon for the operation selected by the EOI, SL, and A bits of
OCW2. The level designated will either be
used to reset a specific ISA bit or to set a
specific priority. The LO-L2 bits are enabled or
disabled by the SL bit.

EOI:

The EOI bit is used for all end of interrupt com·
mands (not automatic end of interrupt mode).
If set to a 1, a form of an end of interrupt com·
mand will be executed depending on the state
of the SL and A bits. If EOI is 0, an end of inter·
rupt command won't be executed.

53

OCW3
OCW3 is used to issue various modes and commands to
the 8259A. There are two main categories of operation
associated with OCW3: interrupt status and interrupt
masking. Bit definition of OCW3 is as follows:

0<>0<'
~

~

0,

o~

~

0,

01

~

Uj

RIS:

The RIS bit is used to select the ISR or IRR for
the read register command. If RIS is set to 1,
ISR is selected. If RIS is 0, IRR is selected. The
state of the RIS is only honored if the RR bit is
a 1.

RR:

The RR bit is used to execute the read register
command. If RR is set to aI, the read register
command is issued and the state of RIS determines the register to be read. If RR is 0, the
read register cosnmand isn't issued.

P:

The P bit is used to issue the poll command. If
P is set to aI, the poll command is issued. If it
is 0, the poll command isn't issued. The poll
command will override a read register command if set simultaneously.

SMM:

The SMM bit is used to set the speCial mask
mode. If SMM is set to a 1, the special mask
mode is selected. If it is 0, it is not selected.
The state of the SMM bit is only honored if it is
enabled by the ESMM bit.

ESMM:

The ESMM bit is used to enable or disable the
effect of the SMM bit. If ESMM is set to aI,
SMM is enabled. If ESMM is 0, SMM is disabled. This bit is useful to prevent interference
of mode and command selections in OCW3.

new1

l

r

1~
11!..J

NO .. ·.Q.c,"c EOI Com,;,aM
• Sp,Clf,C EOI Comm,"Cl

END OF INTERRUPT

ROI,'a 0 .. NOII·Spec,l,c EOI Com.... M
Rot". III Auroml',e EOI Mod. (SET)
Ro"" III A"'o ...,,,e EO! Mod. (CLEAR)

AUTOM ... TIC ROT A TlON

'Ro'I" all Sp'C,IIC EOI Comm.nd
• s,l P"o"" Commend
No OP'""OIl
'LO L2

SPECIFIC ROT A TlON

"'e uSld

0<>0<'

I'-I 1"··1-1' 1' 1. 1--1"" I

J

C.... ,

..

I l_

. .

READ REQISTER COMMAND

, I

• r

lIO()AC"C»o

"'AO

,.1",.

IHAO

0 .....' "

0 .... ' - '
l1t!,u,u

ii1j"uLSi

I
I

,,11,(.

I

I ... POLL COMMAND

o ..

NO POLL COMMAND

·· 1I . .
...

.te .• , ... sa WOOl

IWOAC"OJo

~iOF- THE TERMINOlOGV USED MAY

DIFFER

IUln
If'tCtA,

..,

_CI.,
OU'

SLIGHTLY FROM eXlsTINGI2sIA

!~~~~ SHEETS. THIS IS DONE TO BETTER CLARIFY AND EXPLAIN THE PROGRAM·

I MINQ OF T~~ ~2~9A. TH~ OPERATIONAL RESULT.S AE~AI~ _T~_E SAM_~:.. _ _ _ _ _

Figure 23. Operellonal Command Words (OCWs) Programming Forml'

SL:

The SL bit is used to select a specific level for
a given operation. If SL is set to aI, the LO-L2
bits are enabled. The operation selected by the
EOI and R bits will be executed on the
specified interrupt level. If SL is 0, the LO-L2
bits are disabled.

R:

The R bit is used to control all 8259A rotation
operations. If the R bit is set to aI, a form of
priority rotation will be executed depending on
the state of SL and EOI bits. If R is 0, rotation
won't be executed.

54

SUMMARY OF 825t1A INSTRUCTION SET
Ina•••

Mnemonic

O,..e'lon DIIacrtplion

o
o
o
o

A7
A7

A8
A8

A5
A5

o

A8
A8
A6

A5
A5

000
,

,

0

0

o

A7
A7
A7

0

o

o
o

A7
A7

A8
A8

,
,

0
0

o

AS

0
0
0

0
0

A6
A6
A6
A8

A5
A5
A5
A5

.,

ICW'

A

2
3

ICW'
ICW'

B
C

4
5·

ICW'
ICW'

0
E

8'
7

ICW'
ICW'

F
G

8

ICW'

H

o

A7

9

!CW,

o

'0
"

ICW'

o

A7
A7
A7
A7
A7
A7
A7
A7

A8
A6
A6
A8

0
0
0
0

12

ICW'
ICW'

'3
'4
'5

ICW'
ICW'
ICW'

'8

ICW'

17

ICW2
ICW3
ICW3
ICW4

'8
'9
20
2'
22
23
24
.25

26
27
28

29
30
3'
32
33
34

35
38
37
38
39
40
4.

42
43
44

45

48
47
48
48
50

5.
52
53
54
55

56
57

58
59
~o

61

ICW4.
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
OCW'
OCW2
OCW2
OCW2
OCW2
OCW2
OCW2
OCW2
OCW3
OCW3

K

L.
M
N

0
P

o
o

o
o
o
o

A'5 A'4
57 58

M
5
A

55

000
000
0, 0
0

B
C

o

0

0

000
000
000
000
000
000
o 0 0
o 0 0
000
o 0 0
o 0
o 0 0
o 0 0
000
000
000

0
E
F
G
H
J
K

M
N

0
P
NA
NB
NC
NO
NE
NF
NG
NH
NI
NJ
NK
NL
NM
NN
NO
NP
E
5E
RE
R5E
R
CR
RS
P
RIS

A13

o
o

0

0

0

0

,

,

.

,

,

0

A'O
52

•
0

o

o
o
o
0

o
o
o

o
o
o
o
o
o
o
o

o

M7

Me

M5

O'

o
o

o

,

o

M,

MO

0

0

0

0

0

o

0

0

L2

L.

LO

o

0

0

0

o

l2

L'

LO

000
000
0
o l2

0
0

o
o

LI

LO

0

o

0

o
,
0

0

0

0

0
0
0
0
0

Byle , Inlli.llzal,on

Formal ~ 4. lingl•• edge Irlggered
Formal = 4, oingl•• le.el trlgg.red
Form.l_ 4, no' Ilngl., edge trloo.red

ICW4 Required

Forme' = 4, nol olngle. I••el Irloo.red
Formel_ 8, olngl •• edge Irlgo.red

=

Forme' 8. lingle. le.el ,rlggered
Form.1 = 8, nol olnole. edge I"ooered

master

No action. redundant

Non·bullered mode. no AEOI. 8088/8086
Non·bullered mode. AEOI. MC5·80/8S
Non·bullered mode. AEOI. 8086/8068
Bullered
Bullered
Bullered
Bullered
Bullered

mode.
mode.
mode,
mode,
mode,

slave. no AEOI, MC5·60/8S
slave, no AEOI, 8088 f 8088
slave, AEOI, MC5·8Q/8S
slave, AEOI, 6088/8088
master, no AEOI, MC5·80/8S

Bullered mode, master, no AEOI, 6086/8088
Bullered mode, master, AEOI, MCS'80/8S
Bullerlld mode, master AEOI, 8086, 8068
Fully nested mode, MCS'80, non bullered, no AEOI

}

i

lew.. , NB tnrough lew .. NO are Idenllcal 10

ICW~ B Ihrough ICW4 0 w,lh Ihe add,llon

01

Fully Nesled Mode
Fully Nesled Mode, MCS·SO/8S. non'lIullered, no AEOI

ICW4 NF Ihrough ICW4 NP Ire Idenllcal 10
ICW4 F Ihrough ICW4 P wllh Ihe addilion of
Fully Nesled Mode

,

M2

0

single. level triggered

o
,.
M3

,

= 8.

=8, nol Ilngl•• edga I"gg.red
=8. nol Iingla. la.al Irlggered

o

M4

o
,

•
o
•
o

o
o

0

000
000
0

o

,
o
, ,

000
000

0

Formal

Formal
Formal

o

o
o

o

0

o
'0

o

Formal = 8. single. edge triggered

Non·bullered mode. no AEOI, 8086/8088
Non·bullered mode. AEOI. MCS'80/8S
Non·bullered mode. AEOI. 8086/8068

,
,
,
, o o
, , ,

o
o
o
o

Required

Byte 3 initialization - slave
No action, redundant

• •

o

single. level triggered
nol single. edge triggered

Forma. :I 8. not single, '1... 11 triggered

,

0
0

single. edge triggered

Format -: 4, not single. leyel Irtgr';ued

lew..

Byte 2 initialization
Byte 3 initialization -

AS

SO
0
52 5' SO
o 000 0
00001
000
0
000
•
,
o 0
0
0
o 0
o
o 0
o
o 0 •
o
0
o o
0
o 0
0
o
o
o ,
0
0
o o

0

o

,

A9
51

No

o

0
000
000
o 0 0
0

0

000
o 0
AU A"
54 53

I

Byte 1 Initialization

}

0
,

00'

o

o

Formal

,

o
,

Format

0

0
0
0
000

o

= 4,
= 4,
Format = 4.

0

o

0

0

o

Load mask register, read mask register
Non'lpecific EOI
Specific EOI, LO-L;! code of IS FF to be reset
Rotate on Non·Specific EOI
Rotale on 5peci'ic EOI LO-L2 code of line
ROlate in Auto EOI (.et)
Rotate in AulO EOI (clear)
Set Priority Command
Poll mode
R•• d IS register

55

INITIALIZING THE 82595
The following program can be used to initialize the 8259As as they are
implemented on the System Support 1.
This program sets up the master 8259A to have the following characteristics:
1CW4 is needed, cascade mode, address interval of 4, level triggered mode,
vector starting address of 200H, IR7 input has a slave, 8085 mode, normal endof-interrupt mode, non-buffered mode, special fully nested mode, all interrupts
enabled, non-polled mode, and rotate priority on non-specific end-of-interrupt
command.
The slave 8259A is set up to have the following characteristics: ICW4 is
needed, cascade mode, address interval of 4, level triggered mode, vector
starting address of 220H, slave ID of 7, 8085 mode, normal end-of-interrupt
mode, non-buffered mode, special fully nested mode, all interrupts enabled, nonpolled mode, and rotate priority on non-specific end-of-interrupt command.
Note that Intel advises that using the automatic end-of-interrupt mode in a
master/slave environment is not recommended.

ROUTINE FOR INITIALIZING MASTER AND SLAVE 8259As
ON THE SYSTEM SUPPORT 1
;this program assumes that the System Support 1 is addressed
;at 50H (CompuPro standard), for different addresses change
;BASE in equates.
0050
0050
0051
0052
0053

BASE
I1PRTO
HPRT1
SPRTO
SPRT1

EQU 50H
EQU BASE
EQU BASE+l
EQU BASE+2
EQU BASE+3

0100

ORG

100H

;starting address of board
;lower master port (AO=O)
,;upper master port (AO=l)
;lower slave port (AO=O)
;upper slave port (AO=l)

;this routine initializes the master 8259A
0100 3E1D
0102 D350
0104 3E02
0106
0108
010A
OlOC
010E
0110

56

IN IT

MVI
OUT

MVI

A,OOOl1101B
HPRTO
A,02H

D351
3E80
D351
3E10
D351
3EOO

OUT
HVI
OUT
HVI
OUT
HVI

MPRT1
A,10000000B
MPRT 1
A,00010000B
MPRT 1

0112 D351
0114 3EAO

OUT
HVI

MPRT1
A,10100000B

0116 D350
0118 3E08
011A D350

OUT
HVI
OUT

i1PRTO
A, 0000 1 OOOB
MPRTO

A,O

;ICW 1
;send it
;upper byte of address
interval
;send i t
;IR7 has a slave
;send it
;ICW4
;send it
;clear all mask bits
(OCW 1)
;send it
;rotate on non-specific
E01
;send it
;OCW3
;send it

;this routine initializes the slave 8259A
Olle 3E3D
allE D352
0120 3E02

i1VI
OUT
MVI

A,00111101B
SPRTO
A,02H

0122
0124
0126
0128
012A
012C

D353
3EO?
D353
3E10
D353
3EOO

OUT
HVI
OUT
MVI
OUT
UVI

SPRT1
A,07H
SPRTl
A,00010000B
SPRTl
A,O

012E D353
0130 3EAO

OUT
MVI

SPRTl
A,10100000B

0132 D352
0134 3E08
0136 D352

OUT
MVI
OUT

SPRTO
A,OOOOlOOOB
SPRTO

;ICW1
;send it
;upper byte of address
interval
;slave ID
;ICW4
;clear all mask bits
(OCWI)
;rotate on non-specific
EOI
;OCW3

;now on to other processing

DISABLING THE 8259A'S
To disable the two 8259As on the System Support 1, perform the following
operations:
1) Unplug IC U28 from its socket. Bend pin 12 of Ie U28 out from the
package at about a 45 degree angle and re-install it in its socket,
making sure that the bent out pin makes no contact with any other IC
pin.
2) Unplug IC U46 from its socket. Bend pin 8 of IC U46 out from the
package at about a 45 degree angle and re-install it in its socket,
making sure that the bent out pin makes no contact with any other IC
pin.
3) On the solder side of the PC board, connect a jumper between pin 4
of IC U44 and pin 14 of the same IC (+5 Vdc). If any misunderstanding
exists concerning these instructions, please send back the board
concerned to CompuPro. A charge of $40.00 will be assigned to any
board whose owner wishes to disable interrupts but who does not understand these instructions. A minimum charge of $40.00 will be assigned
to any board returned to CompuPro whose owner either misunderstands
these instructions or fails to implement them properly.

57

PROGRAMMING THE INTERVAL TIMERS.

The interval timers on. the System Support 1 areimplement~d with the 8253
chip (originally produced by Intel, but may be supplied by others). As with the
8259A, rather than repeat a lot of information, we have chosen to reprint a
section of tne data sheet on the 8253. It should give you all the information
you need to program the part, and it fully explains the part's various operating
modes.
The various inputs and outputs of the 8253 appear at J4 which is
intended for connecting these inputs and outputs to the outside world and for
cascading sections. (See the section called "Interval Timer Options," in the
hardware configuration section of this manual for more detailed information.)
The interval timer's outputs also appear at J7 and J8 for connection to the
interrupt controllers and to the S-100 bus vectored interrupt lines. See the
section called "Interrupt Jumpers and Options" in the hardware configuration
section of this manual for more information. One comment is in order here: The
hardware configuration of the interval timers on the System Support 1 is
designed so that the "Interrupt on Terminal Count" mode of the 8253 is taken
advantage of, and this mode is recommended when using the timers to cause
interrupts.
Repriht from the Intel data sheet follows:

That completes the section on Programming Considerations.

58

8253/8253·5
PROGRAMMABLE INTERVAL TIMER

PIN CONFIGURATION
0,

"'e-I'

0,

WR

0,

RO

0,

CS

0,

A,

0,

AO
ClK 2

0,
DO
ClK 0

OuT 2

OUT 0

eLK 1

GATE 2

GATE 0

GATE 1

GND

BLOCK DIAGRAM

elK 0
GATEe
OUT 0

RD---od

cut

1

GATE ,
AO--OUT 1

OUTl

cs-----.J
PIN NAMES
01 Do
elK N
GATE N

ClK 2
CONTROL
WORD
REGISTER

DATA BUS i8 BITI
COUNTER CLOCK INPUTS

OUT N

COUNHA GAT£ INPUTS
COUNTE R OUTPUTS

RD
WR

WRIl[ COMMAND OR OAT A

GATE 2
OUT 2

Rr AD C.OUNTI:.R

CS

CHI? Sf l f:CT

A A

COUNTfR StLECT

Vee

·50 VOL 15

GND

(iROUNO

FUNCTIONAL DESCRIPTION
General
The 8253 is a programmable interval timer/counter
s!)ecifically designed for use with the Intel" Microcomputer systems. Its function is that of a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
The 8253 solves one of the most common problems in any
microcomputer system. the generation of accurate time
delays under software control. Instead of setting up timing
loops in systems software. the programmer configures the
8253 to match his requirements. initializes one of the
counters of the 8253 with the desired quantity. then upon
command the 8253 will count out the delay and interrupt
the CPU when it has completed its tasks. It is easy to see
that the software overhead is minimal and that multiple
delays can easily be maintained by assignment of priority
levels.

Other counter/timer functions that are non-delay in
nature but also common to most microcomputers can be
implemented with the 8253.
•
•
•
•.
•
•

Programmable Rate Generator
Event Counter
Binary Rate Multiplier
Real Time Clock
Digital One-Shot
Complex Motor Controller

Da.a Bus Buffer
This 3-state. bi-directional. 8-bit buffer is used to interface
the 8253 to the system data bus. Data is transmitted or
received by the buffer upon execution of INput or OUTput
CPU instructions. The Data Bus Buffer has three- basic
functions.
1. Programming the MODES of the 8253.
2. Loading the count registers.
3. Reading the count values.

59

Read/Write Logic
The Read/Write Logic accepts inputs from the system bus
and in turn generates control signals for overall device
operation. It is enabled or disabled by CS so that no
·operation can occur to change the function unless the
device has been selected by the system logic.

RD (Read)
A "Iow" on this input informs the 8253 that the CPU IS
inputting data in the form of a counters value.

WR (Write)
A "Iow" on this Input informs the 8253 that the CPU IS
outputting data In the form of mode Information or loading
counters.

AO,A1
These inputs are normally connected to the address bus.
Their function is to select one of the three counters to be
operated on and to address the control word register for
mode selection.

CS (Chip Select)
A "Iow" on this in'put enables the 8253. No reading or
writing will occur unless the device is selected. The CS
input has no effect upon the actual operation of the
counters.

, - ....... -

CS

RD

WR

AI

Ao

...

0

1

0

0

0

Load Counter No. 0

0

1

0

0

1

Load Counter No.1

0

1

0

1

0

Load Counter No.2

0

1

0

1

1

Write Mode Word
Read Counter No. 0
-t --Read
- Counter
-..---No.1
..

0

0

1... -

0
----.

0

0

0---

1

0
..-.,

1

'-'-

-~-

~

.+. _ ._ . _----- _. . _----

Counter No.2
.. --..-o .... t: -Read
----.-----

0

0

1

1

0

0

1

1

X

1 _.
X

0

1

1 __ L...._
X_

t---

.

i

X

1

--_ .. -

X
_...X .. -

No·Operation
3·State
---_
.... _---- ._-.---~

Disable 3·State
No·Operation' 3·State

Control Word Register
The Control Word Register is selected when AO, A 1 are 11.
It then accepts information from the data bus buffer and
stores it in a register. The information stored in this
register controls the operational MODE of each counter,
selection of binary or BCD counting and the loading of
each count register.
The Control Word Register can only be written into; no
read operation of its contents is available.

Counter #0, Counter #1, Counter #2
ClK 0

DATA
GATED

BUS
BUFFER

aUTO

liD
WiI
At,

ClK I
READ;

WRITE
lOGIC

GATE I
OUT I

AI

cs
CLK 2

CONTROL
WORD
REGISTER

COUNTER

'2

GATE 2
OUT 2

INTERNAL BUS /

Figure 1. Block Diagram Showing Data Bus Buffer and
Read/Write Logic Functions

60

These three functional blocks are identical in operation so
only a single Counter will be described. Each Counter
consists of a single, 16-bit, pre-setlable, DOWN counter.
The counter can operate in either binary or BCD and its
input, gate and output are configured by the selection' of
MODES stored in the Control Word Register.
The counters are fully independent and each can have
separate Mode configuration and counting operation,
binary or BCD. Also, there are special features in the
control word that handle the loading of the count value so
that software overhead can be minimized for these
functions.
The reading of the contents of each counter is available to
the programmer with simple READ operations for event
counting applications and special commands and logic
are included in the 8253 so that the contents of each
counter can be read "on the fly" without having to inhibit
the clock input.

OPERATIONAL DESCRIPTION
General

-

elK 0

!»oTA

GATED

BUFFER

l1li
ill!

OUT 0

ClK I

READI

IIfRITE

-'9

GATE I

LOGIC
OUT I

A,

a
CLK2
GATE 2
OUT 2

The complete functional definition of the 8253 IS
programmed by the systems software. A set of control
words must be sent out by the CPU to initialize each
counter of the 8253 with the desired MODE and quantity
information. These control words program the MODE.
Loading sequence and selection of binary or BCD
counting.
Once programmed. the 8253 is ready to perform whatever
timing tasks it is assigned to accomplish
The aCtual counting operation of each counter IS
completely independent and additional logic is provided
on-chip so that the usual problems associated with
efficient monitoring and management of external.
asynchronous events or rates to the microcomputer
system have been eliminated.

Programming the 8253
All of the MODES for each counter are programmeo by the
systems software by simple 1/0 operations.
Each counter of the 8253 is individually programmed by
writing a control word into the Control Word Register
(AO. Al

11)

0

Control Word Format

SCl

SCO

RLO

RLl

Ml

01

Do

MO

BCD

Figure 2. Block Diagram Showing Control Word
Register and Counter Functions

Definition of Control
SC - Select Counter:
SC1

SCQ

0
0
1
1

0
1
0
1

I

ADDRESS BUS 1161

CONTROL BUS

RL -

Select Counter 0
Select Counter 1
Select Counter 2
Illegal

Read/Load:

_ _-_._._-----,

RLl

RLO

0

0

Count er Latching operation (see
READ !WRITE Procedure Section)

1

0

Read! ~~a_d. most :~nificant by~..-~n~y9
Load least significant byte only.
Read!
..

..

. ---.------4

11

0

1

1

1

....

_

Read! Load least significant byte 'lrst, .
then most significant byte.
.
--- _. ".- _. -..

Figure 3. 8253 System Inlerface

61

M M2

MODE:
M1

MO

0

0

0

Mode 0

0

0

1

Mode 1

X

1

0

Mode 2

f-

--

X

1

1

Mode 3

1

0

0

Mode 4

1

0

1

Mode 5

BCD:

o

Binary Counter IS-bits
Binary Coded Decimal (BCD) Counter
(4 Decades)

Counter Loading
The count register is not loaded until the count value is
written (one or -two bytes, depending on the mode
selected by the RL bits), followed by a rising edge and a
falling edge of the clock. Any read of the counter prior to
that falling clock edge may yield invalid data.
MODE Definition
MODE 0: Interrupt on Terminal Count. The output will
be initially low after the mode set operation. After the
count is loaded into the selected count register, the output will remain low and the counter will count. When terminal count is reached the output will go high and remain high until the selected count register is reloaded
with the mode or a new count is loaded. The counter
continues to decrement after terminal count has been
reached.
Rewriting a counter register during counting results in
the following:
(1) Write. 1st byte stops the current counting.
(2) Write 2nd byte starts the new count.
MODE 1: Programmable One·Shot. The output will go
low on the count following the rising edge of the gate input.
The output will go high on the terminal count. If a new
count value is loaded while the output IS low it will not
affect the duration of the one-shot pulse until the succeeding trigger. The current count can be read at any
time without affecting the .one-shot pulse.
The one·shot is retriggerable, hence the output Wilt remain low for the full count after any riSing edge of the
gate input.

62

MODE 2: Rate Generator. Divide by N'counter: The out·
put will be low for one period of the input clock. The
period from one output pulse to the next equals the
number of input counts in the count register:' If the
count register is reloaded between output pulses the
present period will not be affected, but the subsequent
period will reflect the new value.
The gate input, when low, will force the output high.
When the gate input goes high, the counter will start
from the initial count. Thus, the gate input can be used
to synchronize the counter.
When this mode is set, the output will remain high until
after the count register is loaded. The output then can
also be synchronized by software.
MODE 3: Square Wave Rate Generator.Similar to MODE
2 except that the output will remain high until one half
the count has been completed (for even numbers) and
go low for the other half of the count. This is accomplished by decrementing the counter by two on the failing edge of each clock pulse. When the counterreaches
terminal count, the state of the output is changed and
the counter is reloaded with the full count and the whole
process is repeated.
If the count is odd and the output is high, the first clock
pulse (after the count is loaded) decrements the count
by 1. Subsequent clock pulses decrement the clock by
2. After timeout, the output goes low and the full count
is reloaded. The first clock pulse (following the reload)
decrements the counter by 3. Subsequent clock pulses
decrement the count by 2 until timeout. Then the whole
process is repeated. In this way, if the count is Odd. the
output will be high for (N + 1)/2 counts and low for
(N - 1)/2 counts.

MODE 4: Software Triggered Strobe. After the mode is
set, the output will be high. When the count is loaded,
the counter will begin counting: On terminal count, the
output will go low for one input clock period, then will
go high again.
If the count register is reloaded between output pulses
the present period will not be affected, but the subse·
quent period will. reflect the new value. The count will be
inhibited while the gate input is low. Reloading the
counter register will restart counting beginning with the
new number.

MODE 5: Hardware Triggered Strobe. The counter will
start counting after the riSing edge of the trigger input
and will go low for one clock period when the terminal
count is reached. The counter is retriggerable. The output will not go low until the full count after the rising
edge of any trigger.

8253 READIWRITE PROCEDURE
Write Operations
The systems software must program each counter of the
8253 with the mode and quantity desired. The programmer must write out to the 8253 a MODE control word and
the programmed number of count register bytes (lor 2)
prior to actually using the selected counter.
The actual order of the programming is quite flexible.
Writing out of the MODE control word can be in any
sequence of counter selection. e.g .. counter #0 does not
have to be first or counter #2 last. Each counter's MODE
control word register has a separate address so that its
loading is completely sequence independent. (SCO. SC1)
The loading of the Count Register with the actual count
value. however. must be done in exactly the sequence
programmed in the MODE control w()rd (RLO. RL 1). This
loading oi the counter's count register is still sequence
independent like the MODE control word loading. but
when a selected count register is to be loaded it must be
loaded with the number of bytes programmed in the
MODE control word (RLO. RL 1). The one or two bytes to
be loaded In the count register do not have to follOW the
associated MODE control word. They can be programmed
at any time following the MODE control word loading as
long as the correct number of bytes is loaded in order.
All counters 'are down counters. Thus. the value loaded
into the count register will actllally be dEcrernented.
Loading all zeroes into a count register will result in the
maximum count (2'·for Binary or 10'for BCD). In MODE 0
the new count will not restart until the load has been
completed. It will accept one of two bytes depending on
how the MODE control words (RLO. RL 1) are programmed. Then proceed with the restart operation.
MODE Control Word
Counter n
LSB

Count Register byte
Counter n

MSB

Count Register byte
Counter n

Note: Format shown is a simple example of loading the 8253 and
does not imply that it is the only format that can be used.

Figure 6. PrQgrammlng Format

Count Register Byte
Counter 1

0

1

Count Register Byte
Counter 1

0

1

LSB

Count Register Byte
Counter 2

1

0

No. 7

MSB

Count Register Byte
Counter 2

1

0

No.8

LSB

0

0

No. 9

MSB

0

0

No.4

LSB

No.5

MSB

No.6

Count Register Byte
Counter 0
Count Register Byte
Counter 0

Note: The exclusive addresses of each counter's count register make
the task of programming the 8253 a very simple matter. and
maximum effective use of the device will result if this feature
is fully utilized.

Figure 7.. Alternate Programming Formats

Read Operations
In most counter applications it becomes necessary to read
the value of the count in progress and make a
computational decision based on this. quantity. Event
counters are probably the most common application that
uses this function. The 8253 contains logic that Will allow
the programmer to easily read the contents of any of the
three counters without disturbing the actual count In
progress.
There are two methods that the programmer can use to
read the value of the counters. The first method Involves
the use of simple I/O read operations of the selected
counter. By controlling the AO. A 1 inputs to the 8253 the
programmer can select the counter to be read (remember
that no read operation of the mode register IS allowed AO.
Al-11). The only requirement with thiS method is that In
order to assure a stable count reading the actual operation
of the selected counter must be inhibited either by
controlling the Gate input or by external logic that inhibits
the clock input. The contents of the counter selected Will
be available as follows:
first 1/0 Read contains the least Significant byte (LSB)

Al

AO

No.1

MODE Control Word
Counter 0

1

1

No.2

MODE Control Word
Counter 1

1

1

No.3

MODE Control Word
Counter 2

1

1

second I/O Read contains the most SignifIcant byte
(MSB)
Due to the Internal logiC of the 8253 It IS absolutely
necessary to complete the entire reading procedure If two
bytes are programmed to be. read then two bytes !!l!:!!! be
read before any loading WR command can be sent to the
same counter

63

~

Sialus

Modes

0

Low

MODE 2: Rate Generator

Or Going
Rising

Low

High

Disables

EnC'lblps

counting

CllllntHlq

CLOCK

11 InitiatE'S

3

2

0131
OUTPUT (n ,. 3)

alter next CIOC ....

RESET

11 Dlsable~

counting
21 Sets output
Immediately

4

OUTPUT

counllnq

21 Resets output

InltliHps

Enilblf'~

COIJnllnq

C()IJnllnq

~L

r-----

___

high

11 Disables

counting
21 Sets output

Ifll'la'p~

E ndblp~

("Ollntlnq

Llluntlnq

MODE 3: Square Wave Generator
CLOCK

ImmedlBlply

high
OUTPUT (n

4

Disables

Enables

counting

counting

= 41

OUTPUT (n = 5)

InitiatE'S

counting

Figure 4. Gate Pin Operations Summary
MODE 4: Software Triggered Strobe

MODE 0: Interrupt on Terminal Count
CLOCK
;

I
LOAOn~r-------------

WR"n

o
I

OUTPUT !INTERRUPTI

I~n-:

(n"'4)

I

I

,

GATE

o

OUTPUT

------~----~~----~

'
WAm~
,
,
GATE

IIL-Jr-"----5

OUTPUT !INTERRUPTI

4

Im'51L-~~~~----7---~
A

MODE 5: Hardware Triggered Strobe
MODE 1: Programmable One·Shot

CLOCK
GATE

----.I
4

OUTPut In

TRIGGER
OUTPUT

----.r•
-----,j_~~~-I---------

41

GATE

0

--~~--~L-Jr--------

~
3

In" 4)

OUTPUT In

4

:I

4,

TRIGGER~

•

OUTPUT

3

2

3

-----,i_:.......:......::.....:.....:_~j'-----

Flgu,.. 5. 8253 Timing DI.gr.ma

64

'I

1

0

LJ

Read Operation Chart
Al

AO

RD

0

0

0

0

1

0

Read Counter No.1

1

0

0

Read Counter No.2

1

1

0

Illegal

Read Counter No. 0

Reading While Counting
In order for the programmer 10 read the conlenls of any
counter without effecting or disturbing the counting
operation the 8253 has special Internal logiC that can be
accessed uSing simple WR commands to the MODE
register BaSically. when the programmer wishes to read
the contents of a selected counter "on the fly he loads the
MODE register with a speCial code which latches the
present count value Into a storage register so that ItS
contents contain an accurate. stable quantity The
programmer then Issues a normal read command to the
selected counter and the contents of the latched register IS
available

MODE Register for Latching Count
AO, A1

= 11
DO

x

se 1.Seo -

speCify counter to be latched

05.04

00 deSignates counter latching operation

X

don't care

The same limitation applies to this mode of reading the
counter as the previous method. That is, it is mandatory
to complete the entire read operation as programmed.
This command has no effect on the counter's mode.

65

PBOGlWUUNG THE 9511 OIl 9512 HATH PROCESSOR.

The System Support 1 can accommodate either a 9511A or 9512 type math
processor from AMD or INTEL (these chips are provided only as an option). For
the hardware differences between these chips see the section of this manual
entitled theory of Operation.
Though the 9511 and 9512 chips are not software compatible as far as their
representation of numbers, they may be accessed through the same I/O ports~ The
two ports occupied by these chips are:
9511/12 PORT FUNCTION
1: The DATA port
2: The COMMAND port

I/O ADDRESS
Base+8
Base+9

It is worth noting that these chips have a stack structure that must be
kept under very tight control. The stack will become misaligned if, for example, too few or too many bytes of a result are read after a calculation. Once
the stack is misaligned, there is no signal instruction that will reset it. The
only way to re-a1ign the stack through software is to read or write sufficient
bytes to restore it. The quickest and surest way to re-a1ign the math processor
stack is to reset the system.
The user should not attempt to program these chips without a data sheet
(see pages 70-81).
The program below can be used to verify the proper operation of the System
Support 1 with either a 9511A or a 9512. The program, written to run under
CP/M, simply requests the math processor under test to' add two numbers from a
table and then compares the res~lt with a known correct result from another
table. The program can be assembled to test the 9511A or the 9512 by changing
the EQU pseudo-opcode after MP9511 or MP9512 to 'TRUE~ for the desired processor
and 'FALSE' for the other.
;test routine for 9511 or 9512
FFFF
0000

TRUE
FALSE

EQU
EQU

OFFFFH
NOT TRUE

0005
0009
OOOA
OOOA
DODD
0050
0058
0059

BOOS
PSTRING
RCON
CR
LF
BASE
DREG:
CREG:
;
MP9511
MP9512

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

5
9H
OAH
OAR
ODH
SOH
BASE+8
~ASE+9

;prints string in de register
;reads string to memory at de
;carriage return
;line feed
;System Support I/O base
;math chip data register
;math chip command register

EQU
EQU

TRUE
FALSE

;set test chip to true
;set other chip to false

ORG

lOOH

;start of program code

FFFF
0000
0100

66

0100 31ADOl

LXI

SP,STACK

IF

MP9511

;initialize stack

;test routine for 9511
0103 114401
0106 OE09
0108 CD0500

START:

LXI
MVI
CALL

D, GREET 11
C,PSTRING
BDOS

;write contents of tbll to 9511
010B
010E
0110
0111
0112
0113
0115
0118
011A

217BOl
OE04
7E
D358
23
OD
CEI001
3E6C
D359

TEST 1:

LXI
MVI
MOV
OUT
INX
DCR
JNZ
MVI
OUT

H,TBLl
C,4
A,M
DREG
H

C

TESTl
A,6CH
CREG

;length of table into reg c
;byte from table into reg a
;output byte from table to 9511
;increment pointer into table
;decrement table count
;if zero input data done
;single precision add (SADD)
;give command to 9511

;compare 9511 answer with known correct answer in tb12
011C
011E
0121
0123
0124
0127
0128
0129
012C
012E
0131
0133
0136

OE02
217FOl
DB58
BE
C23901
23
OD
C22101
DB59
117501
OE09
CD0500
C30000

MVI
COMPl:

LXI
IN
CMP
JNZ
INX
DCR
JNZ
IN
LXI
MVI
CALL
JMP

C,2
HCTBL2
DREG
M

ERROR
H

C

COMPl
CREG
D,OKMSG
C,PSTRING
BDOS

o

;length of table into reg c
;hl reg points to table 2
;input data from 9511
;match with known result
;error if no match
;else update pointer into table
;decrement counter
;if not zero compare next byte
;check status and throwaway
;set up ok message
;print it
;test passed-- return to CP/M

ENDIF
IF

MP9512

;

;test routine for 9512
START:

LXI
MVI
CALL

G,GREET12
C,PSTRING
BDOS

;

;write contents of tb12 to 9512
LXI

MVI
TEST2:

MOV
OUT

H,TBL3
C,8
A,M
DREG

;length of table into reg c
;byte from table into reg a
;output byte from table to 9512

67

INX
DCR
JNZ
MVI
OUT

R

C

TEST2

A,l
CREG

;increment pointer into table
;decrement table count
;if zero input data done
;single precision add (SADD)
;give command to 9512

;compare 9512 answer with known correct answer in tb14

COMP2:

MVI
LXI
IN
CMP
JNZ
INX
DCR
JNZ
IN
LXI
MVI
CALL

COMP2
CREG
D,OKMSG
C,PSTRING
BDOS

JMP

o

;test passed-- return to CP/M

LXI
MVI
CALL

D,ERRMSG
C,PSTRING
BDOS

;set up error message
;print it

JMP

o

;return to CP/M

C,R
H,TBL1
DREG
M

ERROR
R

C

;length of table into reg c
;hl reg points to table 2
;input data from 9512
;match with known result
;error if no match
;else update pointer into table
;decrement cou~ter
;if not zero compare next byte
;check status and throwaway
;set up ok message
;print it

END IF
0139
Ol3C
Ol3E
0141

116C01
OE09
CD0500
C30000

ERROR:

;messages
;

0144 OAOD39531GREET11:
0158 OAOD39531GREETI2:

DB

CR,LF,'9511 TEST BEGUN',CR,LF,'$'
CR,LF,'9512 TEST BEGUN',CR,LF,'$'

016C AOD0455252ERRMSG:
0175 OAOD4F4B200KMSG:

DB
DB

CR,LF,'ERROR','$'
CR,LF,'OK','$'

,

DB

;

;tables of data and results to test 9511 and 9512
017B 00300040
017F 7000

;9511 tables
TBLl:
DB
TBL2:
DB

00,30H,00,40H
70R,00

;

;9512 tables
0181 0000803FOOTBL3:
DB
0189 40000000 TBL4:
DB

00,00,80H,3FH,00,00,80H,3FH
40H,00,00,00

018D

32

DS
. STACK:

68

; 16 LEVEL STACK

8231 A
ARITHMETIC PROCESSING UNIT
Fixed Point Single and Double
• Precision
(16/32 Bit)
Floating Point Single Precision
• (32 Bit)

with MCS·SO and
• Compatible
MCS·S5™ Microprocessor Families
Direct Memory Access or
• Programmed
1/0 Data Transfers

Binary Data Formats
• Add,
Subtract, Multiply and Divide

• End of Execution Signal

• Trigonometric and Inverse
• Trigonometric Functions
Roots, Logarithms,
• Square
Exponentiation
Float to Fixed and Fixed to Float
• Conversions
• Stack Oriented Operand Storage

Tl1

General Purpose S·Bit Data Bus
• Interface

24 Pin Package
• Standard
+
12 Volt and + 5 Volt Power
• Supplies
• Advanced N·Channel Silicon Gate
HMOS Technology

The Intel~ 8231A Arithmetic Processing Unit (APU) is a monolithic HMOS LSI device that provides high performance fixed
and floating point arithmetic and floating point trigonometric operations. It may be used to enhance the mathematical
capability of a wide variety of processor-oriented systems. Chebyshev polynomials are used in the implementation of the
APU algorithms.
All transfers, including operand, result, status and command information, take place over an 8-bit bidirectional data bus.
Operands are pushed onto an internal stack and commands are issued to perform operations on the data in the stack.
Results are then available to be retrieved from the stack.
Transfers to and from the APU may be handled by the associated processor using conventional programmed 1/0, or may be
handled by a direct memory access controller for improved performance. Upon completion of each command, the APU
issues an end of execution signal that may be used as an interrupt by the CPU to help coordinate program execution.
In January 1981 Intel will be converting from 8231 to 8231A. The 8231A provides enhancements overthe 8231 to allow use
in both asynchronous and synchronous systems.

Figure 1. Block Diagram

Figure 2. Pin Configuration

69

inter

8231A
Table 1. Pin Description
--

Pin
Symbol No. Type

Name and Function

Vcc

2

Power: +5 Volt power supply.

Voo

16

Power: + 12 Volt power supply.

ClK

23

I

Clock: An external, TTL compatible,
timing source is applied to the ClK pin.

RESET

22

I

Reaet: The active high reset signal provides initialization for the chip. RESET
also terminates any operation in progress. RESET clears the status register
and places the 8231A into the idle state.
Stack contents and command registers
are not aUected (5 clock cycles).

CS

18

I

Chip Select: CS is an active low input
signal which selects the 8231A and enables communication with the data bus.

Ao

21

I

Address: In conjunction with the RD
and WR signals, the Ao control line establishes the type of communication
that is to be performed with the 8231A as
shown below:

5

0

Ao

RD

WR

Function

0
0
1
1

1
0
1
0

0
1
0
1

Enter data byte into stack
Read data byte from stack
Enter command
Read status

20

I

Read: This active low input indicates
that data or status is to be read from the
8231A if CS is low.

WR

19

I

Write: This active low input indicates
that data or a command is to be written
into the 8231" if CS is low.

EACK

3

I

End of Execution: This active low input
clears the end of execution output signal (rnlJ). If EACK is tied low, the END
output will be a pulse that is one clock
period wide.

SVACK

4

I

Service Request: This active low input
clears the service request output
(SVREQ).

24

0

End:. This active low, open-drain output
indicates that execution of the previously entered command is complete. It
can be used as an interrupt request and
is cleared by EACK, RESET' or any read
or write access to the 8231.

Name and Function

Service Request: This active high out·
put signal indicates that command
execution is complete and that post
execution service was requested in the
previous command byte. It is cleared by

SVACK. the next command output to the
device, or by RESET.
READY

17

0

Ready: This active high output indio
cates that the 8231 A is able to accept
communication with the data bus. When
an attempt is made to read data, write
data or to enter a new command while
the 8231A is executing a command,
READY goes low until execution of the
current command is complete (See
READY Operation, p. 5).

DBODB7

8·
15

1/0

Data BU5: These eight bidirectional
lines provide for transfer of commands,
status and data between the 8231A and
the CPU. The 8231A can drive the data
bus only when CS and RD are low.

~-

RD

END

SVREQ

Ground.

1

Vss

Pin
Symbol No. Type

-

COMMAND STRUCTURE
Each command enterpd into the8231A consists of a single
8-bit byte having the format illustrated below:

Bits 0·4 select the operation to be performed as shown
in the table. Bits 5·6 select the data format appropriate
to the selected operation. If bit 5 is aI, a fixed point data
format is specified. If bit 5 is a 0, floating point format is
specified. Bit 6 selects the precision of the data to be
operated upon by fixed point commands only (if bit
5= 0, bit 6 must be 0), If bit 6 is aI, single·precision
(16·bit) operands are assumed. If bit 6 is a 0, double·
preciSion (32-bit) operands are indicated, Results are
undefined for all illegal combinations of bits in the com·
mand byte, Bit 7 indicates whether a service request is
to be issued after the command is executed, If bit 7 is a
I, the service request output (SVREQ) will go high at the
conclusion of the command and will remain high until
reset by a low level on the service acknowledge pin
(SVACK) or until completion of execution of the suc·
ceeding command where service request (bit 7) is 0,
Each command issued to the 8231A requests post execution service based upon the state of bit 7 in the command
byte. When bit 7 is a 0, SVREQ remains low.

AFN-012518

70

8231A
Table 2. 32-Blt Floating Point Instructions
Inl.ructlon

Ol.crtptlon

Slock Content.I' 1

HU C1l
Cod.

Slotu. FI.gal'l
Affected

After EXKution
A

B

C

D

ACOS

Inverse Cosine of A

0

6

R

U

U

U

·S, Z, E

ASIN

Inverse Sine of A

0

5

R

U

U

U

S, Z, E

ATAN

Inverse Tangent of A

0

7

R

B

U

U

S, Z

CHSF

Sign Change of A

t

5

R

B

C

0

S, Z

COS

Cosine of A (radians)

0

3

R

B

U

U

S, Z

EXP

I;t'\

rune lion

0

A

R 9

U

U

S, Z, E

FADD

Add A and B

1

0

R

C

0

U

S, Z, E

FDIV

Divide B by A

1

3

R

C

0

U

S, Z, E

FLTD

32·BIt Integer to Floating Point Conversion

1

C

R

B

C

U

S,Z

FLTS

16·81t Integer to Floating Point Conversion

1

0

R

B

C

U

S, Z

FMUL

Multiply A and B

1

2

R

C

0

U

S,Z, E

FSUB

Subtract A from B

1

1

R

C

0

U

S, Z, E

LOG

Common Logarithm (bese 10) of A

0

B

R

B

U

U

S,Z, E
S, Z, E

LN

Natural Logarithm of A

0

9

R

B

U

U

POPF

Stack Pop

1

B

B

C

0

A

S, Z

PTDF

Stack Push

1

7

A

A

B

C

S, Z

PUPI

Push n onto Stack

1

A

R

A

B

C

S,Z

PWR

eA Power Function

0

B

R

C

U

U

S, Z, E

StN

Sine of A (radians)

0

2

R

B

U

U

S, Z

SORT

Square Root of A

0

1

R

B

C

U

S,Z, E

TAN

Tangent of A (radians)

0

4

R

B

U

U

S, Z, E

XCHF

Exchange A and B

1

9

B

A

C

0

S,Z

Table 3 32-Blt Integer Instructions
Instruction

Description

StIck Contentsl ' l
After Execution
A B C D

He.(1 )
Cod.

Slotu. Flog.I')
Affected

CHSD

Sign Change of A

3

4

R

B

C

0

S, Z, 0

DADO

Add A and B

2

C

R

C

0

A

S,Z, C, E

DDIV

Divide B by A

2

F

R

C

0

U

S, Z, E

DMUL

Multiply A and B (R = lower 32·bits)

2

E

R

C

0

U

S, Z, 0

DMUU

Multiply A and B (R - upper 32·bits)

3

6

R

C

0

U

S, Z, 0

DSUB

Subtract A from B

2

0

R

C

0

A

S, Z, C, 0

FIXD

Floating Point to Integer Conversion

1

E

R

B

C

U

S, Z, 0

POPD

Stack Pop

3

B

B

C

0

A

S, Z

PTOD

Stack Push

3

7

A

A

B

C

S, Z

XCHD

Exchange A and B

3

9

B

A

C

0

S, Z

Table 4. 16-Blt Integer Instructions
Instruction

Description

He.(1 )
Code

Stick Con'lnta(3)
After Execution
Au AL Bu BL Cu CL Du DL

Slotu. Ftog.I' 1
Affected
S, Z, 0

CHSS

Change Sign of Au

7

4

R AL Bu BL Cu CL Du DL

FIXS

Floating Point to Integer Conversion

1

F

R Bu BL Cu CL U

POPS

Stack Pop

7

B

AL Bu BL Cu CL Du DL Au

S,Z

PTOS

Stack Push

7

7

Au Au AL Bu BL Cu CL Du

S,Z

SADD

Add Au and AL

6

C

R

S, Z, C, E

SDIV

Divide AL by Au

6

F

R Bu BL Cu CL Du DL U

S, Z, E

SMUL

Multiply AL by Au (R = lower 16·bits)

6

E

R Bu BL Cu CL Du DL U

S, Z, E

SMUU

Multiply AL by Au (R - upper 16·bits)

7

6

R Bu BL Cu CL Du DL U

S, Z, E

SSUB

Su~tract

Au from AL

6

0

R Bu BL Cu CL Du DL Au

S, Z, C, E

XCHS

Exchange Au and AL

7

9

AL Au Bu BL Cu CL Du DL

S, Z

NOP

No Operation

0

0

Au AL Bu BL Cu CL Du DL

U

U

Bu BL Cu CL Du DL Au

S,Z,O

Not••: 1. In the hex code column. SVREQ IS a O.
2. The stack initially is composed of four 32·bit numbers (A, B. C. 0). A is equivalent to Top Of Stack (TOS) and B is Next On Stack (NOS). Upon
completion of a command the stack is composed of: the result (A); undefined (U); or the initial contents (A. B. C. or D).
3. The stack initially is composed of eight 16·bit numbers (Au. A L• Bu. B L• Cu. C LI Du. Dd. Au is the TOS and AL Is NOS. Upon completion of a
command the stack Is composed of: the result (A); undefined (U); or the initial contents (Au. A L• Bu. B L•· .. ).
4. Nomenclature: Sign (S); Zero (Z); Overflow (0); Carry (C); Error Code Field (E).
AFN.()12518

71

intJ

8231A

DATA FORMATS
The 8231A arlfhmetic processing unit handles operands
In both fixed point and floating point formats. Fixed
point opdrands may be represented in either single
(16·blt operands) or double precision (32·blt operands),
and are always represented as binary, two's comple·
ment values.
SINGLE PRECISION FIXED POINT FORMAT

I

VALUE

51 I I I I I I I I I I I I I I

~I

31

value

=mantissa x 2exponent

For example, the value 100.5 expressed in this form is
0.1100 1001 x 27. The decimal equivalent of this value
may be computed by summing the components (powers
of two) of the mantissa and then multiplying by the ex,·
ponent as shown below:
value = (2 -1 + 2- 2 + 2 - 5 + 2 ~ 8) X 27

0

~

I

I

The 8231A is a binary arithmetic processor and requires
that floating point data be represented by a fractional
mantissa value between .5 E\nd 1 multiplied by 2 raised
to an appropriate power. This is expressed as follows:

=0.5 + 0.25 + 0.03125 + 0.00290625) x128

DOUBLE PRECISION FIXED POINT FORMAT
VALUE

II I I II I I I I I I I I I I I I I I I I I I I I I I I J0

= 0.78515625 x 128
= 100.5

I

The sign (positive or negative) of the operand is located
in. the most significant bit (MSB). Positive values are
represented by a sign bit of zero (S 0). Negative values
are represented by the two's complement of the carre·
sponding positive value with a sign bit equal.to 1 (S 1).
The range of values that may be accommodated by each
of these formats is - 32,768 to + 32,767 for single preci·
sian and -2,147,483,648 to +2,147,483,647 for double
precision.

=

=

Floating point binary values are represented in a format
that permits arithmetic to be performed in a fashion
analogous to operations with decimal values expressed
In scientific notation.

FLOATING POINT FORMAT
The format for floating point values in the 8231A is given
below. The mantissa is expressed as a 24·bit (fractional)
value; the exponent is expressed as a two's complement
7·blt value having a range of - 64 to .+ 63. The most
significant bit is the sign of the mantissa (0 positive,
1 = negative), for a total of 32 bits. The binary point is
assumed to be to the left of the most significant man·
tissa bit (bit 23). All floating point data values must be
normalized. Bit 23 must be equal to 1, except for the
value zero, which is represented by all zeros.

=

I

EXPONEN'

~Iil

3'~

I

MANnsSA

IIIII IIIIIIIIIIIIIIIIIIIIIII
2423

I

0

The range of values that can be represented in this for·
mat is ± (2.7 x 10 - 20 to 9.2 X 10 18) and zero.
In the decimal system, data may be expressed as values
between 0 and 10 times 10 raised to a power that effec·
tlvely shifts the Implied decimal point right or left the
number of places necessary to express the result in can·
ventlonal form (e.g., 47,572.8). The value·portion of the
data is called the mantissa. The exponent may be either
negative or positive.
The concept of floating point notation has both a gain
and a loss associated with it. The gain is the ability to
represent the significant digits of data with values span·
ning a large dynamic range limited only by the capacity
of the exponent field. For example, In decimal notation
if the exponent field is two digits wide, and the mantissa
Is five digits, a range of values (positive or negative)
from 1.0000 x 10 - 99 to 9.9999 x 10 + 99 can be accom·
modated. The loss. is that only the significant digits of
the value can be represented. Thus there is no distinc·
tion in this representation between the values 123451
and 123452, for example, since each would be ex·
pressed as: 1.2345x 105. The sixth digit has been
discarded. In most applications where the dynamic
range of values to be represented is large, the loss of
significance, and hence accuracy of results, is a minor
consideration. For greater precision a fixed point format
could be chosen, <\Ithough with a loss of potential
dynamic range.
.

72

FUNCTIONAL DESCRIPTION
STACK.CONTROL
The user interface to the 8231A includes access to an 8
level 16·bit wide data stack. Since single precision fixed
point operands are 16·bits in length, eight such values
may be maintained in the stack. When using double
precision fixed point or floating point formats four
values may .be stored. The stack in these two configura·
tions can be visualized as shown below:
82'S
81
T OA
Ali 1

NOS

I

TOS
NOS

•• A3.3
••

., .,Al
A2

---32---16-

Data are written onto the stack, eight bits at a time, in
the order shown (A 1, A2, A3, ... ). Data are removed from
the stack in reverse byte order (A4, A3, A2 ... ). Data
should be entered onto the .stack in multiples of the
number of bytes appropriate to the chosen data format.

AFN-012S18

inter

·S231A

DATA ENTRY
bata entry Is accomplished by bringing the chip select
(05), the command/data line (Ao!, and WR low, as shown
In the timing diagram. The entry of each new data word
"pushes down" the previously entered data and places
the new byte on the top of stack (TOS). Data on the bot·
tom of the stack prior to a stack entry are lost.

DATA REMOVAL
Data are removed from the stack. in the 8231A by bringing
chip select (CSi, command/daia (Ao!, and 1m low as
shown In the timing diagram. The removal of each data
word redefines TOS so that the next successive byte to
be removed becomes TOS. Dat.a removed from the stack
rotates to the bottom of the stack.

4. The 8231 A is not busy, and a data entry has been requested. READY will be pulled low for the length of
time required to ascertain If the preceding data byte,
If any, has been written to the stack, If so READY will
Immediately go high. If not, READY will remain low
until the interface latch Is free and will then go hlgh_
5. When a status read has been requested, READY will
be pulled low for the length of time necessary to
transfer the status to the Interface latch, and will
then be raised to permit completion· of the status
read. Status may be read whether or not the 8231A is
busy.
When READY goes low, the APU expects the bus control signals present at the time to remain stable until
READY goes high.

COMMAND ENTRY

DEVICE STATUS

After the appropriate number of bytes of data have been
entered onto the stack, a command may be issued to
perform an operation on that data: Commands which require two operands for execution (e.g., add) operate on
the TOS and NOS values. Single operand commands
operate only on the TOS.
Commands are issued to the 8231A by bringing the chip
select (CS) line low, command data (Ao!line high, and
WR line low as Indicated by the timing diagram. After a
command Is Issued, the CPU can continue execution of
its program concurrently with the 8231A cpmmand
execution.

Device status Is provided by means of an Internal status
register whose format is shown below:

COMMAND COMPLETION
The 8231A signals the completion of each command execution by lowering the End Execution line (END).
Simultaneously, the busy bit In the status register Is
cleared and the Service Request bit of the command
register is checked. If it is a "1" the service request output level (SVREQ) Is raised. END is cleared on receipt of
an active low End Acknowledge (EACK) pulse. Similarly,
the service request line is cleared by recognition of an
active low Service Acknowledge (SVACK) pulse.

READY OPERATION
An active high ready (READY) is provided. This line is
high in its quiescent state and is pulled low by the 8231A
under the following conditions:
1. A previously Initiated operation Is in progress (device
busy) and Command Entry has been attempted. In
this case, the READY line will be pulled low and remain low until completion of the current command
execution. It will then go high, permitting entry of the
new command.
2. A previously initiated operation Is in progress and
stack access has been attempted. In this case, the
READY line will be pulled low, will remain In that
state until execution Is complete, and will then be
raised to permit completion of the stack access.
·3. The 8231A is not busy, and data removal has been requested. READY will be pulled low for the length of
. time necessary to transfer the byte from the top of
stack to the interface latch, and will then go high,
Indicating availability of tl1e data.

I

BUSY

SIGN

I

ZERO

I

t=-t

ERROR CODE

-·--1 I
CARRY

II

BUSY: Indicates that 8231 A is currently executing a command (1 = Busy)
SIGN: Indicates that the value on the top of stack Is
negative (1 = Negative)
ZERO: Indicates that the value on the top of stack Is
zero (1 = Value is zero)
ERROR CODE: This field contains an Indication of the
validity of the result of the last operation. The error codes are:
0000 - No error
1000 - Divide by zero
0100 - Square root or log of negative number
1100 - Argument of Inverse sine, cosine, or
eX too large
XX10 - Underflow
XX01 - Overflow
CARRY: Previous operation resulted in carry or borrow
from most significant bit. (1 = Carry/Borrow,
0= No Carry/No Borrow.)
If the BUSY bit In the status register Is a one, the other
status bits are not defined; if zero, indicating not busy,
the operation Is complete and the other status bits are
defined as .given above.

READ STATUS
The 8231 A status register can be read by the CPU at any
time (whether an operation Is In ·progress or not) by
bringing the chip select (05) low, the command/data line
(Ao! high, and lowering RD. The status register Is then
gated onto the data bus and may be Input by the CPU.

EXECUTION TIMES
Timing for execution of the 8231A command set is contained below. All times are given in terms of clock
cycles. Where substantial variation of execution times
AFN.()1251B

73

inter

8231 A

Is possible, Ihe minimum and maximum values are
quoted; otherwise, typical values are given. Variations
are data dependent.
Total execution times may require allowances for
operand transfer Into the APU, command execution, and
result retrieval from the APU. Except for command exe·

cutlon, these times will be heavily influenced by the
nature of the data, the control interface used, the speed
of memory, the CPU used, the priority allotted to DMA
and Interrupt operations, the size and number of
operands to be transferred, and the use of chained
calculations, etc.

Table 5. Command ExecutlonTlmea
Command
Mnemonic

Clock
Cycle.

Commend
Mnemonic

Clock
Cycle.

Commend
Mnemonic

Clock
Cycle.

SADD
SSUB
SMUL
SMUU
SDIV
DADO
DSUB
DMUL
DMUU
DDIV
FIXS
FIXD
FLTS
FLTD

17
30
84·94
8().98
84·94
21
38
194·210
182·218
208
92·216
100-346
98·186
98·378

FADD
FSUB
FMUL

54·368
7()'370
146·168

LN
EXP
PWR

4298·6956
3794·4878
8290·12032

FDIV
SORT
SIN
COS

154·184
4464
4118

NOP
CHSS
CHSD
CHSF

4
23
27
18

TAN
ASIN
ACOS
ATAN
LOG

5754
7668
7734
6006
4474·7132

PTOS
PTOD
PTOF
POPS
POPD

16
20
20
10
12

800

Commend
Mnemonic
pdPF
.. :XCHS
XCHD
XCHF
PUPI

Clock
Cycle.
I

12
'.18.
26
26
16

DERIVED FUNCTION DISCUSSION
Computer approximations of transcendental functions
are often based on some form of polynomial equation,
such as:
(1·1)

Tn(X) = 2X[Tn-1(X»)- Tn- 2(X); n .. 2

(1,7)

The primary shortcoming of an approximation In this
form Is that It typically exhibits \fery large errors when
the magnitude of IXI is large, although the errors are
small when IXI is small. With polynomials in this form,
the error distribution Is markedly uneven over any
arbitrary Interval.

Common logarithms are computed by multiplication
of the natural logarithm by the conversion factor
0.43429448 and the error function is thereiore the same
as that for natural logarithm. The power function Is
realized by combination of natural log and exponential
functions according to the equation:

A set of approximating functions exists that not only
minimizes the maximum error but also provides an even
distribution of errors within the selected data represen·
tation interval. These are known as Chebyshev Poly·
nomials and are are based upon cosine functions. These
functions are defined as follows:

The error for the power function is a combination of that
for the logarithm and exponential functions.

Tn(X) = Cos n9; where n =0,1,2 ...
9=COS-1X

(1·2)

The various terms of the Chebyshev series can be com·
puted as shown below:
To(X) = Cos (0, 9)= Cos (0)= 1
T1(X)= Cos (COS-1X)= X
T2(X) = Cos 29= 2Cos 2 9-1 = 2COS2(COS-1X)- 1
= 2X2_1

74

In general, the next term In the Chebyshev series can be
recursively derived from the previous term as follows:

(1·4)
(1·5)
(1·6)

Each of the derived functions Is an approximation of the
true function. Thus the result of a derived function will
have an error. The absolute error is the difference be·
tween the function's result and the true result. A more
useful measure of the function's error is relative error
(absolute error/true result). This gives a measurement of
the significant digits of algorithm accuracy. For the
derived functions except LN, LOG, and PWR the relative
error Is typically 4x 10- 7• For PWR the relative error Is
the summation of the EXP and LN errors, 7x 10- 7• For
LN and LOG, the absolute error Is 2 x 10 -7.

AFN-01251B

8232
FLOATING POINT PROCESSING UNIT
• Compatible with Proposed IEEE For·
mat and Existing Intel Floating point
Standard
• Single (32·Bit) and Double (64·Bit)
Precision Capability
• Add, Subtract, Multiply and Divide
Functions

• Standard 24·Pin Package
• 12V and 5V Power Supplies
• Compatible with MCS·SOTM, MCS·S5™
and MCS·S6™ Microprocessor Families
• Error Interrupt
• Direct Memory Access or Programmed
1/0 Data Transfers

• Stack Oriented Operand Storage

• End of Execution Signal

• General Purpose S·Bit Data Bus Inter·
face

• Advanced N·Channel Silicon Gate
HMOS Technology

The Intel'" 8232 is a high performance floating·point processor unit (FPU). It provides single precision (32·bit) and
double precision (54·bit) add, subtract, multiply and divide operations. The 8232's floating point arithmetic is a subset
of the proposed IEEE standard. It can be easily interfaced to enhance the computational capabilities of the host
microprocessor.
The operand, result, status and command information transfers take place over an 8·bit bidirectional data bus. Oper·
ands are pushed onto an internal stack by the host processor and a command is issued to perform an operation on the
data stack. The results of the operation are available to the host processor from the stack.
Information transfers between the 8232 and the host processor can be handled by using programmed I/O or direct
memory access techniques. After completing an operation, the 8232 activates an "end of execution" signal that can
be used to interrupt the host processor.

V"

END

vee

m

"'""

W1l

SVACK

AD

"

ERROR

WR

EACtI

READY

RESET

CBO·DBl

END

SVREQ

SVACi<:

ERROR

Figure 1. Block Diagram

Figure 2. Pin Configuration

75

8232

Table 1. Pin Description
Symbol Pin No.

Type

Name and Description

Vee

2

Voo

16

Vss

1

ClK

23

I

CLOCK: An external timing source can·
nected to the elK input provides the
necessary clocking.

RESET

22

I

RESET: A HI.GH level on this Input causes
Initialization. Reset terminates any operation In progress, and clears the status
register to zero. The Internal stack pointer
Is Initialized and the contents of the stack
may be affected. After a reset the END
output, the ERROR output and the SVREO
output will be LOW. For proper Inltlallza·
tlon, RESET must be HIGH for at least five
CLK periods following stable power
supply voltages and stable clock.

CS

18

I

CHIP. SELECT: Input must be LOW to ac·

Symbol Pin No.

POWER SUPPLY: +5V power supply

Type

19

WRITE: A LOW level on this input is used
to transfer information from the data bus
into an internal location. The
must be
LOW to accomplish the write operation.
Ao determines which In.!!!nal location is
to be written. see Ac, CS input descriptions and write timin'g diagram .for details.

POWER SUPPLY: + 12V power supply

as

complish any read or write operation to
the 8232.
To perform a write operation, appropriate
data is presented on. OBO through DB7
lines, appropriate logic level on the Ao In·
put and the ~ Input 15 made LOW. When·
everWRand R1i inputs are both HIGH and
CS Is LOW, READY goes LOW. However,
actual writing into the 8232 cannot start
until WR Is made LOW. After initiating the
write operation by the HIGH to LOW tran·
sltlon on the WR Input, the READY output
will go HIGH, Indicating the write opera·
tlon has been acknowledged. The WR input can go HIGH after READY goes HIGH.
The data lines, the Ao input and the CSln·
put can change when appropriate hold
time requirements are satisfied. See write
timing diagram for details.
To perform a read operation an appropriate
logic level I. established on the Ao Input
and CS Is made LOW. The READY output
goes lOW because WR and AD inputs are
HIGH. The read operation does not start
until the 1m Input goes LOW. READY will
go HIGH Indicating that read operation Is
complete and the required Information Is
available on the DBO through DB7 line •.
This Information will remain on the data
lines as long as AD Is LOW. The Ali input
can return HIGH anytime after READY
goes HIGH. The CS Input and Ao input can
ohange anytime after RD returns HIGH.
See read timing diagram for detailS. If the
CS Is tied LOW permanently, READY will
remain LOW until the next 8232 read or
write access.

Ao

21

I

ADDRESS: The Ao Input together with the
AD and WR 'Inputs determines the type of
transfer to be performed on the data bus
as follows:

Ao
0
0
1
1

76

RD WR
1

0

0

1

1

0

0

1

Function
Enter data byte into stack
Read data byte from stack
Enter command
Read status

D~scrlptlon

READ: A LOW level 01"1 this input is used
to read information from an Internal
location and gate that Information onto
the data bus. The CS Input must be LOW
to accomplish the read operation. The Ao
input determines what internal location Is
to be read. See Ac, CS input descriptions
and read timing diagram for det.lls. lithe
END output was HIGH, performing any
read operation will make the END output
go LOW after the HIGH to LOW transition
of the RD input (assuming CS Is LOW). II
'th's ERROR output was HIGH, performing
a status register read operation will make
the ERROR output LOW. This will happen
after the HIGH to LOW transition of the
1m" Input (assuming CS Is LOW).

GROUND

WR

Name and

20

If the END output was HIGH, performing
any write operation will make the END
output go LOW after the LOW to HIGH
tranSition of the WR Input (assuming CS is
LOW).
EACK

END ACKNOWLEDGE: When LOW,
make. the END output go LOW. As men·
tloned earlier, HIGH on the END output
Signals completion of a command execution. The END signal Is derived from an
Internal fllp·flop which Is clocked at the
completion of a command. This flip-flop is
clocked to the reset state when EACK is
LOW. Consequently, it EACK is tied LOW,
the END output will be a pulse that Is
approximately one ClK period wide.

SVACK

SERVICE ACKNOWLEDGE: A LOW level
on this Input clears SVREO. lithe SVACK
input 15 permanently tied LOW, II will
conflict with the internal setting of the
SVREQ output. Thus, the SVREQ
Indication cannot be relied upon If the
SVACK Is tied LOW.
.

END

24

o

END OF EXECUTION: A HIGH on this
output Indicates that execution of the
current command is complete. This output
will be cleared LOW by activating the
EACK input LOW or performing any read
or write operation or device Initialization
using RESET. II EACK is tied LOW, the
END output will be a pulse (see EACK
description),
Reading the status register while a com·
mand execution Is In progress Is allowed.
However, any read or write operation
clears the flip-flop thafgenerates the END
output. Thus, such continuous reading
could conflict with Internal logic setting of
the ENDflip·flop at the end of command
execution.

AFN-01283C

inter

8232

Table 1. Pin Description (Continued)
Symbol Pin No.
SVREQ

ERROR

Typo

Namo and Doscrlpllon

o

SERVICE REQUEST: A HIGH on this out·
put Indicates completion of a command.
In this sense this output Is the same as the
END output. However. the SVREQ output
will go HIGH at the completion of a
command only when the Service Requast
Enabla bit was satta 1. Tha SVREQ can ba
claarad. (I.e.. go LOW) by activating the
SVACK Input LOW or Inillallzing the
device using the RESET. Also. the SVREQ
wlil be aulomallcally cleared after
complellon 01 any command that has the
service request bit as O.

o

Symbol Pin No.
READY

17

Typo

o

tions with the 8232. If the WR and m;
Inpuls are both HIGH. tho READY output
goes LOW with the CS input In anticipation of a Iransaction. If WR goas LOW to
Initiate a write transaction with proper

signals established on the DBO-DB7. Ao
InpulS, Ihe READY will raturn HIGH
Indicating that tho writo operation has
been accomplished. The WR can bQ made

HIGH after this event. On the ather hand. if
a read operallon Is daslred, the Rii Input Is
made LOW after activating
LOW and
establishing proper Ao input. (The READY
will go LOW In response to Cs going
LOW.) The READY will return HIGH,

as

indicating completion of read. The AD can

overflow and exponent underflow. The

return HfGH after this event. II should be

ERROR output Is cfeared LOW on a status
roglsler read operation or upon RESET.

cutlon Is In progress. However, It should

be nolad Ihal raadlng tha status raglslar
claars Iha ERRQR output. Thus. raadlng
Iha slalus reglstar whlla a command
execution Is In progress may'result In an
Inla'nal conflici with Iha ERROR output.

READY: Output is a handshake signal used
while performing read or write transae·

ERROR: Output goes HIGH to Indicate that
the current command execution resulted
In an error condition. The error conditions
are: attempt to divide by zero. exponent

The ERROR output Is derlvad lrom the
error blls In Ihe slalus register. Thase
arror biiS will be updatad Intarnally at an
appropriate time during a command exe·
cullan. Thus. ERROR oulpul going HIGH
may nol col nelda with Iha complation of a
command. Raadlng of tha stalus ·reglslar
can be performed while a command exe·

Namo and Doscrlption

noted that a read or write operation can be
Initiated without any regard to whether a
command execution is in progress or not.
Proper device operation Is as~ured by

obeying the READY output indication as
described.

DBODB7

8-15

I/O

DATA BUS: Bidirectional lines are used to
transfer command, status and operand
information between the device and the
host processor. DBa is the least signifi·
cant and DB7 Is the most significant bit
position. HIGH on a data bus line corre·

sponds to 1 and LOW corresponds to O.
When pushing operands on the stack
using the data bus, the least significant

byte must bo pushed first and the most
significant byte last. When popping the
stack to read the result of an operation,
the most significant byte will be available
on the dala bus Ilrst and the least slg.
nlficant byte will be the last. Moreover, for
pushing operands and popping results,
the number of transactions must be equal
to the proper number of bytes appropriate
for the chosen format., Otherwise, the

Internal byte pOinter will not be aligned
properly. The single precision format
requires 4 bytes and double precision
format requires 8 bytes.

FUNCTIONAL DESCRIPTION
Major functional units of the 8232 are shown In the
block diagram. The 8232 employs a microprogram con·
trolled stack oriented architecture with H·blt wide data
paths.
The Arithmetic Unit receives one of Its operands from
the Operand Stack. This stack Is an eight word by H·blt
two portmemory with last In-first out (LIFO) attributes.
The second operand to the Arithmetic Unit Is supplied
by the Internal 17·blt bus. In addition to supplying the
. second operand, this bidirectional bus also carries the
results from the output of the Arithmetic Unit when
required. Writing Into the Operand Stack takes place

from this Internal 17·blt bus when required. Also con·
nected to this bus are the Constant ROM and Working
Registers. The ROM provides the required constants to
perform the mathematical operations while the Working
Registers provide storage for the Intermediate values
during command execution.
Communication between the external world and the
8232 takes place on eight bidirectional input/output
lines, DBO through DB7 (Data Bus). These signals are
gated to the Internal 8·bit bus through appropriate inter·
face and buffer circuitry. Multiplexing facilities exist for
bidirectional communication between the internal eight
AFN·Ol263C

77

infel'

8232

and 17-blt buses. The Status Register and Command
Register are also located on the 8-blt bus.
The 8232 operations are 'controlled by the microprogram
contained In the Control ROM. The Program Counter
supplies the microprogram addresses and can be partially loaded from the Command Register. Associated
with the Program Counter Is the Subroutine Stack where
return addresses are held during subroutine calls In the
microprogram. The Microinstruction Register holds the
current microinstruction being executed. The register
facilitates plpelined microprogram execution. The
Instruction Decode logic generates various Internal control signals needed for the 8232 operation.
The Interface Control logic receives several external Inputs and provides handshake related outputs to facilitate InterfaCing the 8232 to microprocessors.

Operands are always entered into the stack least significant byte first and most significant byte last. The following procedure must be followed to enter operands into
the stack:

Command Format

1. The lower significant operand byte Is established on
the DBO-DB7 lines.

The operation of the 8232 Is controlled from the host
processor by Issuing Instructions called commands.
The command format Is shown below.

2. A LOW Is established on the Ao input to specify that
data Is to be entered into the stack.

OPCODE

I

I

The command consists of 8 bits; the least significant 7
bits specify the operation to be performed as detailed In
Table 1. The most significant bit Is the Service Request
Enable bit. This bit must be a 1 If SVREQ Is to go HIGH
at the end of executing a command.
The commands fall Into three categories: single precision arithmetic, double precision arithmetic and data
manipulation. There are four arithmetic operations that
can be performed with single precision (32-bit) or double
precision (64-blt) floating-point numbers: add, subtract,
multiply and divide. These operations require two operands. The 8232 assumes that these operands are
located In the Internal stack as Top of Stack (TOS) and
Next on Stack (NOS). The result will always be returned
to the previous' NOS which becomes the new TOS.
Results from an operation are of the same precision and
format as the operands. The results will be rounded to
preserve the accuracy. The actual data formats and
rounding procedures are described In a later section. In
addition to the arithmetic operations, the 8232 Implements eight data manipulating operations. These
include changing the sign of a double or single
precision operand located In TOS, exchanging single
preciSion operands located at TOS and NOS, as well as
pushing and popping single or double precision
operands. See also the sections on status register and
operand formats.
The execution times of the commands are all data
dependent. Table 3 shows one example of each command execution time.

78

Operand Entry
The 8232 commands operate on the operands located at
the TOS and NOS. Results are returned to the stack at
NOS and then popped to TOS. The operands required for
the 8232 are one of two formats - single precision
floating-point (4 bytes) or double precision floatingpoint (8 bytes). The result of an operation has the same
format as the operands. In other words, operations
using single precision quantities always result In a
single precision result, while operations Involving
double precision quantities will result in double
precision result.

3. The CS Input Is made LOW. Whenever the WR and RD
Inputs are HIGH, the READY output will follow the CS
input. Thus, READY output will become LOW.
4. After appropriate set up time (see timing diagrams),
the WR Input is made LOW.
5. Sometime after this event, READY will return HIGH to
indicate that the write operation has been aCknowledged.
6. Any time after the READY output goes HIGH, the WR
Input can be made HIGH. The DBO-DB7, Ao and CS
inputs can change after appropriate hold time requirements are satisfied (see timing diagrams).
The above procedure must be repeated until all bytes of
the operand are pushed into the stack. It should be
noted that for single precision operands 4 bytes should
be pushed and 8 bytes must be pushed for double precision. Not pushing all the bytes of a quantity will result
In byte pointer misalignment.
The 8232 stack can accommodate four single precision
quantities or two double precision quantities. Pushing
more quantities than the capacity of the stack will result
In loss of data which is usual with any LIFO stack.
The stack can be visualized as shown below:
TOS-

AA

NOS-

B4

I

A3

I

I

A2

I

B.

B3

I

AI
Bl

~

_32_

T08_1

AI

A7

NOS ....

88

B7

::=::1:

A2

B.

:: If

14

AFN-01263C

8232

Table 2. 8232 Command Set
Single Precision Instructions

Description

Instruction

Hox l
Code

Stack Contents 2
Alter Execution
A B C D

Status Flags
Aflected 4

SADD

Add A and 8

01

R

C

D

U

S,Z, U, V

SSU8

Subtract A from 8

02

R

C

D

U

S,Z, U, V

·SMUL

Multiply A by 8

03

R

C

D

U

S,Z, U, V

SDIV

04

R

C

D

U

S, Z, U, V, D

CHSS

Divide 8 by A. If A exponent = 0,
then R= 8.
Change sign of A5

05

R

8

C

D

S,Z

PTOS

Push stack 5

06

A·

A

8

C

S,Z

POPS

Pop stack

07

8

C

D

A

S,Z

XCHS

Exchange

08

8

A

C

D

S,Z

Double Precision Instructions

Instruction

Description

Hex l
Code

Stack Contents 3
Alter Execution
A B

Status Flags
Aflected 4

DADD

Add A and 8

29

R

U

S,Z, U, V

DSU8

Subtract A from 8

2A

R

U

S,Z, U, V

DMUL

Multiply A by 8

28

R

U

S,Z, U, V

DDIV

Divide 8 by A. If A= 0,
then R= 8.

2C

R

U

S,Z,U, V,D

CHSD

Change sign of A5

2D

R

8

S,Z

PTOD

Push stack 5

2E

A·

A

S,Z

POPD

Pop stack

2F

8

A

S,Z

CLR

CLR status

00

A

8

Noloa:
1. In the hex code column, SVREQ bit is a O.

2. The slack Initially Is composed of four 32·bit numbers (A, B, C, D). A Is equivalent to Top Of Stack (TOS) and B is Next on Stack (NOS). Upon com·
pletlon of a command the stack Is composed of: the result (Al; undefined (U); or the Initial contents (A,B,C, or 0).
3. The stack initially Is composed of two 64·blt numbers (A, B). A is equivalent to Top Of Stack (TOS) and B is Next On Stack (NOS). Upon completion
of a command the stack is composed of: the result (Rl; undefined (U); or the initial contents (A, B).
4. Any status blt(s) not affected are set to O. Nomenclature: Sign (5); Zero (Z); Exponent Underflow (U); Exponent Overflow (V); Divide Exception (D).
5. If the exponent field of A is zero, A or A· will be zero.

AFN-01263C

79

8232

Table 3., Execution Times
Command

TOS

SADD
SSUB
SMUL
SDIV
CHSS
PTOS
POPS
XCHS
CHSD
PTOD
POPD
CLR
DADO
DSUB
DMUL
DDIV

3F800000
3F800000
40400000
3F800000
3F800000
3F800000
3F800000
3F800000
3FFOOOOO 00000000
3FFOOOOO 00000000
3FFOOOOO 00000000
3FFOOOOO 00000000
3FFOOOOO OAOOOOOO
3FFOOOOO AOOOOOOO
BFF80000 00000000
BFF80000 00000000

NOS

Result
40000000
00000000
40900000
3FOOOOOO
BF800000

3F800000
3F800000
3 FCOOOOO
40000000

40000000
-

3FFOOOOO
3FFOOOOO
3FF80000
3FF80000

BFFOOOOO 00000000
00000000
00000000
00000000
00000000

3FFOOOOO OAOOOOOO
' 3FFOOOOO AOOOOOOO
C002000000000000
BFFOOOOO 00000000

Clock Periods
58
,56
198
228
10
16
14
26
24
40
26
4
578
578
1748
4560

Not.: TOS, NOS and result are In hexadecimal; clock period Is In decimal.

Command Initiation
After properly positioning the required operands in the
stack, a command may be issued. The procedure for
initiating a command execution is the same as that
described above for operand entry, except that the Ao
input is HIGH.
An attempt to issue a new command while the current
command execution is in progress Is allowed. Under
these circumstances, the READY output will not go
HIGH until the current command execution is com·
pleted.

Removing the Results
Result from an operation will be available at the TOS.
Results can be transferred from the stack to the data
bus by reading the stack.
When the stack is'read for results, the most significant
byte is available first and the least significant byte last.
A result Is always of the same precision as tile operands
that produced It. Thus, when the result Is taken from the
stack, the total number of bytes popped out should be
appropriate with the precision - single precision
results are 4 bytes and double precision results are 8
bytes. The following procedure must be used for read·
Ing the result from the stack:
1. A LOW is established on the Ao Input.
2. The CS Input is madeLOW. When WR and RD inputs
are both HIGH, the READY output follows the CS
input, thus READY will be LOW.
3. After appropriate set up time (see .liming diagrams),
the RD input Is made LOW.

4. Sometime after this, READY will return HIGH, indio
cating that the data is available on the DBO-DB7
lines. This data will.remain on the DBO-DB7 lines as
long as the RD input remains LOW.
5. Any time after READY goes HIGH, the RD Input can
, return HIGH to complete the transaction.
6. The CS and Ao inputs can change after appropriate
hold time requirements are satisfied (see timing dla·
gram).
7. Repeat this procedure until all bytes appropriate for
the precision of the result are popped out.'
Reading of the stack does not alter its data; it only adjusts the byte pointer. Note data must be removed ,in
even byte multiples to avoid a byte pointer misalignment. If more data is popped than the capacity of the
, stack, the internal byte pointer will wrap around and
older data will be read again, consistent with the LIFO
stack.

Reading Status Register
The 8232 status register can be read without any regard
to whether a command is in progress or not. The only
implication that has to be considered is the effect this
might have on the END and ERROR outputs discussed
in the signal descriptions.
The following procedure must be followed, to accomplish status register reading:
1. Establish HIGH on the Ao input.
2. Establish LOW on the CS input. Whenever WR and
AD inputs are HIGH, READY will follow the CS input.
Thus, READY will go LOW.
3. After appropriate set up time (see timing diagram),
RD is made LOW.
AFN.()t263C

80

8232

4. Sometime after the HIGH to LOW transition of RD,
READY will become HIGH, Indicating that status reg·
Ister contents are available on the DBO-DB7 lines.
These lines will contain this Information as long as
m:ils LOW.

Bit 7 Busy. When 1, this bit indicates the 8232 Is in the
process of executing a command. It will become
zero after the command execution Is complete.
All other status register bits are valid when the Busy bit
Is zero.

5. The AD Input can be returned HIGH any time after
READY goes HIGH.
6. The Ao Input and CS Input can change after satisfying
appropriate hold time requirements (see timing
diagram).

Data Formats

Status Register

The 8232 handles floatlng'polnt quantities in two differ·
ent formats - single precision and double preCision.
These formats are the same as those used by Intel in
other products and those proposed by the IEEE Sub·
committee on floating point arithmetic.

The 8232 contains an 8·blt status register with the
following format:

The single precision quantities are 32 bits long, as
shown below:

.r
I I
All the bits are Initialized to zero upon reset. Also,
executing a CLR (Clear Status) command will result In
all zero status register bits. A zero In bit 7 Indicates that
the 8232 Is not busy and a new command may be
Initiated. As soon as a new command Is Issued, bit 7
becomes 1 to Indicate the device Is busy and remains 1
until the command execution Is complete, at which time
It will become O. As soon as a new command Is Issued,
status register bits 0-6 are cleared to zero. The status
bits will be set as required during the command execution. Hence, as long as bit 7 Is 1, the remainder of thE'
status register bit Indications should not be relied upon
unless the ERROR occurs. The following Is a detailed
status bit description.
Bit 0 Reserved.
Bit 1 Exponent overflow (V). When 1, this bit Indicates
that the result exponent Is more positive than
+ 127 ( + 1023). The exponent Is "wrapped" Into the
negative exponent range, skipping the end values.
Bit 2 Exponent Underflow (U). When 1, this bit Indicates
that the result exponent Is more negative than
-126 ( -1022). The exponent Is "wrapped" Into the
positive range by the number of underflow bits,
skipping -127 (-1023) and + 128 (+ 1024).
Bit 3 Divide Exception (D). When 1, this bit Indicates
that an attempt to divide by zero Is made. Cleared
to zero otherwise.
Bit 4 Reserved.
Bit 5 Zero (Z). When 1, this bit indicates that the result
returned to TOS after a command is zero. Cleared
to zero otherwise.
Bit 6 Sign (S). When 1, this bit Indicates that ihe result
returned to TOS Is negative. Cleared to zero other·
wise.

S

E

31

30

I
23

I

IMPLIED BIT

M
2·

22

Bit 31:
S

=Sign of the mantissa. One represents negative and 0
represents positive.

Bits 23-30:
E

=These 8 bits represent a biased exponent. The bias
Is 27 - 1 =127.

Bits 0-22:
M

=23·blt mantissa. Together with the sign bit, the man·
tlssa represents a signed fraction In sign·magnl·
tude notation. There Is an Implied 1 beyond the
most significant bit (bit 22) of the. mantissa. In other
words, the mantissa Is assumed to be a 24·bit nor·
mallzed quantity and the most significant bit, which
will always be a 1 due to normalization, Is Implied.
The 8232 restores this Implied bit internally before
performing arithmetic, normalizes the result and
strips the Implied bit before returning the results to
the external data bus. The binary point is between
the Implied bit and bit 22 of the mantissa.

The quantity N represented by the above notation is
BIAS

_ r
[

BINARY POINT

N = (_ l)s 2 E- 12' -1) (l.M)

Provided E;60 (reserved for 0) or all 1's (Illegal). The
approximate decimal range for this format is
:!: 1.17 x 10- 38 to :!: 3.40 x 1038 The format supports 7
significant decimal digits.

AFN.Q1263C

81

8232

A double precision quantity consists of the mantissa
sign bit, an 11·blt biased exponent (E), and a 52·blt man·
tlssa (M). The bias for double precision quantities Is
2'0 _1. The double precision format Is Illustrated below.

+

I

5

63

E

IMPLIED BIT

I

I

62

52

M
'1

51

B1I83:
S = Sign of the mantissa. One represents negative and 0
represents positive.

Rounding
One of the main objectives In choosing 'the 8232's Intell
IEEE proposed floating point arithmetic was to provide
maximum accuracy with no anomalies. This means that
a mathematically unsophlstlcatljd user will not be
"surprised" by some of the results. It Is probably
possible for a sophisticated user to obtain reliable
results from almost any 'floating point arithmetic.
However, In that case there will be an additional burden
on the software.
' '
" '
The best example of what might be called the 8232's
"safety factor" Is the Inclusion of guard 'bits for
rounding.' The absence of guard bits leads tei the
problem demonstrated by the following four·blt multi·
plication:

Bits 52-82:
.1111X2°
.1000x2 '

E = These 11 bits represent a biased exponent. The bias
Is 2'0 -1 = 1023.

.01111000x2 '
Bits 0-51:
M = 52·blt mantissa. Together with the sign bit the man·
tlssa represents a signed fraction In slgn·magnl·
tude notation. There Is an Implied 1 beyond the
most significant bit (bit 51) of the mantissa. In other
words, the mantissa Is assumed to be a 53·blt nor·
mallzed quantity and the most significant bit, which
will always be a 1 due to normalization, is Implied.
The 8232 restores this Implied bit Internally before
performing arithmetic, normalizes the result and
strips the Implied bit before returning the result to
the external data bus. The binary point Is between
the Implied bit and bit 51 of the mantissa.
The quantity N represented by the above notation Is

r- BIAS

.-L.

r

BINARV POINT

N = (_l)s 2 E _(2 'O _1) (l.M)

Provided E .;. 0 (reserved for 0) or all 1s (Illegal). The
approximate decimal range Is ±2.22 x 10- 308 to ±1.80
x 10308 • The format supports 16 significant decimal
digits.

Since the last four bits are lost, the normalized result Is:
.1110x2°
and the Identify function Is not valid. In the past this
problem has been avoided (hopefully) by relying on
excess preCision.
Instead the 8232 uses a form of rounding known as
"round to even." There are other types of rounding
provided for In the proposed IEI=E standard, but "round
to even," an unbiased rounding scheme, Is required.
"Round to even" comes Into play when a result Is
exactly halfway between two floating point numbers. In
this case the arithmetic produces the "even" number,
the one whose last mantissa bit Is zero. The 8232 uses
three additional bits-the Guard bit (G), the Rounding
bit (R), and the "Sticky" bit (S)-to do the rounding.
These are bits which hold data shifted out (right) of the
accumulator. Rounding Is carried out by the following
rules, as shown In the following figure, after the result is
normalized.

The following are some examples of single precision
floating point representations:

Bit
G

elftIIJ
FloaUno

82

Dlclnuol

S

E

M

0

0

0

0

0000 OOOOH

Point

1

0

127

0

3F80 OOOOH

-1

1

127

0

BF80 OOOOH

255

0

.9922

437F OOOOH

n

0

134
128

.5708

4049 OFDBH

0
0
0
0
1
1
1
1

R
0

S

Rule
No Round

0
1
1

0
1
0
1

0

0

Round to Even

0

1
0
1

Round Up

1
1

Round Down

AF~'263C

THEORY OF OPERATION
This section will explain how the circuitry on the System Support 1 works.
We will "walk" you through the schematic, and deal with circuits by function.
We will not spend too much time explaining all of the various hardware features
and options available because this information is covered thoroughly in the
section entitled "Configuring the System Support 1".
Please refer to that
section to find out what these circuits are supposed to do, and how to select
the options. This section will deal only with how they operate and will assume
you already know what they're supposed to do.

ADDRESS DECODE
There are three separate address decoder circuits on the System Support 1.
One is for the 1/0 ports, one is for the 4K block of memory address space in a
64K page, and the last determines which 64K page out of the 256 possible.
The 1/0 port decoder is comprised of U35 (a 74LS136) and U19 (a 74LS138).
Half the inputs to U35 are connected to address lines A4-A7. The other half are
connected to four positions of Switch 3. The outputs of U35 are tied together.
When the address at the inputs matches the setting of the switches all the
outputs will be high indicating that the particular block of 16 addresses has
been addressed. This output is connected to the Gl input of U19. The G2B input
of U19 is connected to the output of U25 (a 74LS02).
The inputs to this section
of U25 are connected to the sINP and sOUT signals on the S-100 bus. The output
of U25 will then be low any time there is an input or output cycle occurring.
Therefore the output of U35 and the output of U25 form the enable signals
for the one-of-eight decoder - U19. U19's outputs will only be allowed to be
active when an 1/0 cycle is occurring to the selected block of 16 1/0 addresses.
The address inputs to U19 are connected to address bits A3-Al.
Therefore each
of the outputs of U19 will be active for two 1/0 addresses. Most of the chips
on the System Support 1 use two 1/0 ports so the output then becomes the 'chip
select' signal for that IC. For example the YO output of U19 becomes ICNTA*
which is the chip select for the master interrupt controller. The timer and
UART require four ports, so two of the outputs of Ul9 are combined with AND
gates to make their chip selects.
The address for the memory on the S~stem Support 1 is selected by two
address decoders.
One selects the 64K page that the memory resides in and the
other selects which 4K block in the 64K page.
The "extended address" decoder (the one that determines the 64K page) is
implemented with a 25LS2521 octal comparator (U32) and Switch S2. Half the
inputs to U32 are connected to address bits A16-A23 and the other half are
connected to S2.
When the addresses match the switch settings then the output
of U32will go low. This output is connected to one input of U33 (a NAND gate).
The other input to U33 is connected to one position of Switch SI - XA. When
this switch is closed, the output of U33 will be forced high and the output of
U32 will be effectively ignored.
This causes the rest of the decoder logic to
ignore the extended address decode and makes the memory space "global" which
means it appears in every 64K page. If the XA switch is open then the output of
U32 will be allowed to pass through U33 (with inversion).
The decoder that determines which 4K block in the 64K page is implemented
with U36 (a 74LS136) and four positions of S3.
Half the inputs to U36 are
connected to the address bits Al2-A15 and the other half are connected to the
switches. When the address matches the switch settings the outputs of U36 will
be high signifying that the desired 4K block has been addressed.

83

ThiS output is connected to one input of another section··of U33. Another
input·to U33'comes'from the' extend.ed.address .decoder we discl,lssed previously
(the o.utpu.t of another section of U.33). Another input is ·the PHANTOt-l* signal
from the . S-100 bus that i.s either inverted or not inverted. by U26 depending on
how. S.1~7 .and Sl'":B are set. If .both .switche!,! are. open, th!'!o this line',w:ill:be
pulled up by a resistor . (R17) and PHANTOM* .will b!'! ignored. I f Sl-7. is closed
and S1-8 is open, the PHANTOM* signal will by-pass U26 and b!'! conn!'!ct!'!d t~ the
input of U33. This will caus!'! th!'! memory to be disabled wh!'!n PHANTOM* goes ,low
(the low forc!'!s th!'!output of 033 high and cauSeS the other input!'! t~be
ignored). If Sl..,6 is closed and Sl-7 i,s opet)., the PHANTOM~signaL wiP be
invert!'!d by U26 and. then cOllnected to the ·input o.f U33.· . T.his will cause' the
memory to .be disabled until PHANTOM* goes low. when it will be enabled .(if the
addresses are co·rrect). ,·The last input .to U33 .is from pi'n 6 of U25 .that goes
low when an I/O cycle is ,occurring. This. keeps the memory from being. selected
during I/O cycles.
, .
. '.
'.,
.
Th'e. output of U33 is the signal ROM*and goes low to .s:i,gnify. that an address
to the memory space on the board has occurred.
.
If Sl-5 (RDI)is closed, the outputs of U36 wil,l.be held low and.therefore
the memory space w.ill be disabled permanently (because ROl't* will never. p!'!
allowed to go low).

ROH/RAH CIRCUITRY

The signal ROM* is low when, the two memory address decoders and the ... PHANTOM*
signal are active as described above. This signal is applied to one .input of
two sections of, U1B. The other inputs to U18 are the 'inverted and non..,inverted
All fromtheS.-l00 bus. The outputs of U1B w.ill' go low depending on the state
of All which selects one or the. other of the' two RAM/ROM locations. The upper
RAM/ROM (U16) has its chip enable tied directly .to one output of U1B •. The lower
RAM/ROM (U1.7.) has .its chip enable first inverted. by U45 and then goes throl,lgh
the transistor )'bu~fer" created by R16, RB and Q2. This provides isolat;l.on ~rom
the output of U1B because excessive current would be drawn through U18's output
stage when VCC is lost. Resistor R22 pulls .up U17's chip enable to th.e battery
.s u p p l y . . . ,
Power for U17 is normally provided through Q3 until power is . los t .then the
battery takes· over. Removing D3 from the circuit will prevent the battery from
supplying power. if a high current ROM or RAM. is .used in U17 •.
The output enable for the RAM/ROM is a fllnction of sMEMR, RD* and PHANT*~
If sMEMR and' PHANT* are.high and RD*·goes low, the output of the selected memory
chip will be enabled. The :PHANT*signal is generated. by the Interrupt· Circuit,ry
and ensures that. the·memory does not respond during aninterruptacknowl,dge
cycle,- .regardless of .the setting ofPHE I1-ndPHD.
, The' write' strobe ·for the. RAM is the MWRITE signal with inv.ersion byU24. ·;tf
. ROM is used,- the VPP pin. will be high during memory reads, which is correct~
. IRrElUlUPT· CONTROLLERS

The· System. Support l.uses: the. B259A .. interrupt controller which is designed
to work wit,h either BOB5-or BOBB/B6 type CPUs. An internal mode bit w:hich is
set in the sofi:·ware,initializa:tion routine' determines. which type of processor is
to be used. "
'.' :
However, a problem exists when using the B259As with BOBO or Z-BO CPUs •.
This is because the B259A issues CALL instructions as the interrupt response.

84

CALL instructions' are three bytes long; so three interrupt acknowledge cycles
are needed t6 read the whole instruction out of the 8259A.
The 8085 will
'provide the three necessary interrupt acknowledge cycles, but the' 8080 and Z-8o
. doe not.
These CPUs only expect to see a one byte instruction (usually a
REST'ART).· What they do in response to the CALL is to fetch the CALL opcode as
i f it were an INTA cycle~ but then try to get the next two bytes as i f it were. a
memory read. Natu'rally we had to provide some circuitry to get around this
problem.
The output of flip-flop U44b will only go high when p5TVAL* goes low during
pSYNC, which signifies that the status lines on the S-lOo bus are valid.
This
signal is applied to one input each of two sections of U46.When sINTA goes
high and this "status valid" signal goes high, pin 8 of U46 will go low which
will cause the inverting output ofU44a to' go low. This s:l,gnal is ACK*. ACK* is
connected to. one input of OR gate U18 • . The other input to U18 is thepHLDA
signal from the S-lOo Bus. This allows DMA requests from the bus to temporarily
sus'pend interrupt, acknowledge cycles. This can happen because the. interrupt
acknowledge response from the 8259A is a CALL instruction and DMAreql,lests are
honored after Ml cycles, which in this case would be after· the first byte of the
CALL opcode. The output of U18 becomes the PHANT* signal wh:l,ch is used,to
disable the System Support l's memory during interrupt acknowledge cyclei
(regardless of the setting of the PHD andPHE switches. This signal also
represents the fact that an interrupt acknowledge cycle is occurring and is
applied to one input to U20 that generates the master board select. signal that
is used to enable the board's output buffers. This signal is also applied to
ori~ input of U21 that is used to·force two wait state. during interrupt
acknowledge cycles to insure that a proper response is always sent in even the
fastast of systems. This PHANT* signal is inverted by a section ofU24 and
becomes 'the PHNTM signal which is in turn applied to U28which inverts again and
drives the PHANTOM* line on the 5-100 bus. This signal also goes to one input
of NAND gateU27. Tha other input to the NAND gate is the pDBIN signal from the
bbs. The output of the NAND gate becomes the INTA* signal which goes to the
interrupt controllers which is used by them to gate the response onto the data
bus.'
Flip flop U44a will remain set until one of two events occur, depending on
how jumper J13 is set. One input to U25 is the pHLDA signal from the 5-100 bus
which is used to disqualify the other input duringDMA cycles. This prevents
U44a from being cleared by any cycles that a DMA device may run on the bus
(since the interrupt acknowledge cycle may be interrupted in mid-stream). The
other input to U25 is selected by J13. In the 8085/8088/8086 mode (8 connected
tdC), this input is the sINTA signal from the S-loo bus which means .that U44a
.' will be cleared on any cycle that is not an interrupt acknowledge cycle and not
aDMA cycle when statUs is valid. In the Z-8o/808o mode (Z connected to C),
this input is the SWO* signal from the 5-100 bus. This will'clear U44a on the
first write cycle following the interrupt acknowledge cycle that is not a DMA
cycle. In a Z-8o or 8080 system this will be thestackpash .that normally
follows the .CALL instruction (which is the interrupt response).
The 8259As are enabled for reading and writing to their registers by the
ICNTA* and ICNTB* signals from U19. The RD* and WR* signals enable reading and
writing respectively.
Pin 16 (the master/slave programming pin).of .U15 is t,ied high.through R21
and that programs UIS to be the master. Pin 16' of U14. is tied low making it the
slave.
The three cascade bus pins (12,'13 and. 15) are connected together. The
825gAs communicate over this bus to maintain the master/slave relationship and
priorities.

85

INTERVAL TIMERS
The interval timers on the System Support 1 are implemented with the 8253
programmable interval timer IC.
The TIMER* signal from U21 is used to enable
the 8253 for reading and writing with the RD* and WR* signals.
The CLOCK and GATE inputs and the timer outputs are all present at J4 so
that they may be interconnected to perform a variety of functions. The timer
outputs are buffered and inverted by U10 so that any polarity is available.
The
timer outputs also appear at the interrupt controller option jumpers J7 and J8
for causing interrupts.
The GATE inputs are pulled up with resistors so that timers do not randomly
become disabled and nothing need be done with these inputs in most cases.
See
the chart in the reprint from the 8253 data' sheet to determine the effect of the
GATE input on the various timer modes.
The CLOCK inputs are normally tied to the 2 Mhz clock signal on pin 49 of
the S-100bus (after being buffered by Ull), but they may be "cut and jumpered"
at J4 to allow cascading of timer sections or use of external clocks. Make sure
any external signal brought in at J4 is a TTL level only!

SERIAL CHANNEL
The UART used on the System Support 1 is the 2651 type that has an internal
baud rate generator and latches for the RS-232 handshake lines.
The master clock is provided from the crystal oscillator comprised of two
inverters from U45 and crystal X2.
The frequency is 5.068 Mhz.
The R/W and CE inputs to the UART do not have the same meaning as one has
come to expect from these type of LSI parts (such as all the others on the
board).
Instead, the R/W signal is a status signal telling the UART which
direction the data bus should be in, and the CE input is the combination chip
enable and data strobe. The R/W line is tied to SOUT from the S-100 bus since
SOUT will be high for I/O writes and low for I/O reads. The RD*, WR* and UART
signals are combined with two sections of U46 to form the CE signal.
The RS-232 inputs and output are level shifted with 1489 and 1488 RS-232
receiver and driver ICs. They may be configured for either master or slave mode
by either a dip-shunt or dip-header at J2.
The TxRDY and RxRDY signals are inverted by two sections of U31 and go to
the interrupt circuitry for running the UART in an interrupt driven mode.

MATH CHIP
The System Support 1 can accept either the 9511A or 9512 type math processors from AMD or Intel.
(Intel's numbers are 8231 and 8232 respectively).
The chip is enabled by the 9511* signal from U19 and is read or written with
the RD* and WR* signals.
The standard 9511A or 9512 runs from a 2 Mhz clock which is provided from
the 5-100 bus CLOCK signal on pin 49. But ru~D makes 3 Mhz parts and Intel makes
4 Mhz parts, so provision has been made for an on-board oscillator to allow
higher clock frequencies than 2 Mhz. This is formed by two sections of U11 and
crystal Xl.
Xl is not supplied with the board. The output of the oscillator is
divided by two by flip-flop U8. Thus the crystal used must be twice the desired
frequency.
This was done because 6 Mhz crystals are easier to find than 3 Mhz
crystals (and they're smaller!). J5 is used to determine which clock source
drives the math chip.

86

The PAUSE output is used to cause the CPU to wait if the math chip needs
more time to get data ready, cannot accept a command just now and other reasons.
This is inverted by U11 and re-inverted by U28 and connected to the ROY line on
the S-100 bus.
The END and SVRQ outputs are brought into the interrupt structure so that
the math chip can be run in an interrupt driven mode.
The ERROR signal is only
available on the 9512 (8232) and the END polarity is different between the two
types of math chips. J6 is used to correct for the polarity difference.
REAL-TIME CLOCK/CALENDAR

The real time clock is implemented with the OKI MSM5832 clock chip. This is
a CMOS chip and is therefore much slower (in terms of access time) than the NMOS
components. Therefore it requires special interface circuitry.
The command and data lines are latched by U40 and U42 to keep them. stable
longer than the CPU would normally assert such signals.
The CLK* and WR*
signals are combined by a section of U25 to form a write strobe for the latches.
The appropriate latch is selected by AO and U26 and U27.
Whenever the command latch is written into, a 6 microsecond wait state is
generated by U43a and U28. Whenever the HOLD bit is set high, a 150 microsecond
wait state is generated by U43b and U28.
This causes the CPU to slow down
automatically for the clock chip rather than have to bother with wait loops in
software.
The clock data is read by the occurrence of CLK* and RD* at the inputs of
U25. This causes the outputs of U42 to be tri-stated and the outputs of U39 to
be enabled. This assumes the READ bit is set high.
The master clock for the clock chip is provided by crystal X3 (a 32.768 Khz
watch crystal), C12 and C11. C12 may be adjusted to vary the frequency of the
oscillator which will determine the accuracy of the clock.
The clock's chip select (CS) input is held high by Q3 until the +8 volt
supply drops down to about 7 volts which will drive the CS input low. This
inhibits glitches at the command inputs from affecting the time.
At the same
time Q5 will no longer provide power to the clock, but will allow the battery to
power the clock through D4.
POWER-FAIL DRIVER
The same circuit that pulls CS low on the clock (described above) is also
used to implement the PWRFAIL* line on the S-100 bus (pin 13). When the +8 volt
supply drops to about 7 volts then Q4 will turn off and R28 will pull the input
of U31 high. This will be inverted by U31 and becomes the PWRFAIL* signal.
PWRFAIL* will go low about 15 milliseconds before the regulators in the
system drop out of regulation. The exact time will depend on your system's
power supply and the loading on it.
The PWRFAIL* signal may be jumpered to the NMI* line (bus pin 12) with
jumper J10.
WAIT STATE GENERATOR
The System Support 1 has the ability to insert 0, 1, 2, 4, or 8 wait states
into every access to the board. The number of wait states inserted is dependent
on the setting of Switch Sl, positions 1-4. But there are also some instances
when wait states are automatically inserted regardless of how Sl is set.
Two wait states are automatically inserted every time an access to the math
chip occurs. This is because the PAUSE output of the 9511 (8231) comes out too

87

late to cause a wait state. Therefore we cause two wait states to be inserted
just in case, and if the 9511 needs more, its PAUSE line.will remain asserted,
extending the wait state further.
Two wait states are automatically inserted on every interI'upt acknowledge
cycle for added margin in responding to interrupts.
In addition, the clock circuitry can also ca~se wait s~ates, but that
circuitry has been covered in the section on the clock.
Here's how the wait state generator works: All of the various "chip select"
signals, ROM* and the "interrupt acknowledge" signal (labeled PHANT*) are
combined by U20, an eight input NAND gate. The output of U20 will be high any
time an access to the board is made, and is connected to one input of a section
of U27. The other input is connected to pSYNC from the S-100 bus. The output
of U27 will go low when there is aboard select and a pSYNC, and is tied to the
SHIFT/LOAD input of U22. This causes ~he data prese~t at its parallel data
inputs to be loaded into the register.
If no switches are closed and it's not an access to the 9511 or an INTA,
then the data will be all ones. The QH output will immediately be set to
whatever is present at the H input (inverted). In this case, a one is present
so a zero will appear at the QH output which will be inverted by U28 leaving the
RDY line high. No wait state will be generated.
If switch 4 (W 1) is closed, the data present at H would be a zero (through
U21) and therefore a high would be present at the QH output when SHIFT/LOAD goes
low. This will cause the RDY line to be low and a wait state will be started.
When pSYNC returns low the SHIFT/LOAD input will be high so the clock can now
shift the data through the register. Since the G input was high, a low will
appear at the QH output after the falling edge of the next clock, ending the
wait state.
You can see that the more zeroes that are loaded into the register, the more
wait states will be generated. The 9511* and,PHANT* signals are combined by a
section of U21. Two further sections AND this signal with the SI-4 and SI-3 (WI
and W2) which makes these two switches appear to be closed if an access to the
9511 or an INTA occurs.
This causes the automatic wait state generation
described above.

DATA BUS
The System Support 1 uses a bi-directional data bus on the board because
most of the peripheral chips also use a bi-directional data bus.
This is
implemented with U37 and U38, two tri:-state buffers.
The RD* signal is generated when any access to the board is made and pDBIN
is high. RD* is applied to the tri-state control of U38 which drives the S-100
Data Input Bus and the inverted RD* signal is applied to the tri-state control
of U37 which controls the flow of data from the S-100 Data Output Bus into the
board.
So when RD* is low, U37 will be disabled and U38 will be enabled causing the
internal data bus to be driven onto the S-100 data lines. When RD* is high U38
will be disabled so the board will not drive the S-100 data bus and U37 will be
enabled causing the data from the S-100 data bus to present on the internal data
bus.
Data is always driven into the board unless a board read occurs which causes
the data to be driven out from the board. Data will not be inadvertently
written into the stuff on the board because all write strobes a qualified by the
chip selects (either by the chip itself or on-board logic).
That completes the Theory of Operation Section.

88

PARTS

LIST

INTEGRATED CIRCUIT5 (Note:
the following parts may
have letter suffixes and prefixes along with the key
numbers given below.)
(4)
(1)

(4)
(3)
(1)
(1)

(1)
(1)

(2)
(1)
(1)

(1)
(1)
(1)

(2)
(1)

(1)
(3)
(1)

(1)
(1)
(1)

(1)
(1)
(2)
(1)

(2)
(1)
(1)

74L500
quad 2 input NAND
(U6,26,27,46)
(U25 )
quad 2 input NOR
74L502
74L504
hex inverter
(U 10, 11 , 24, 45 )
(U28,30,31)
hex inverter O.C.
74L506
74L508
(U21 )
quad 2 input AND
(U33 )
dual 4 input NAND
74L520
74L530
eight input NAND
(U20)
(U18)
quad 2 input OR
74L532
74L574
(U8,U44)
dual D flip-flop
(U19 )
one-of-eight decoder
74L5l38
74L5165
8 bit shift register
(U22 )
(U42 )
quad latch tri-state
74L5 17 3
74L5221
dual one-shot
(U43)
octal bus buffer
(U38 )
74L5244
74L5266
quad XNOR O.C.
(U35,36)
74L5273
(U40)
octal latch
7 4L5.36 7
hex bus buffer
(U23)
81L595/97 octal non-inverting buffer (U34,37,39)
81L896/98 octal inverting buffer
(U29 )
(U32)
25L52521
octal comparator
1488
R8-232 driver
(U4)
(U3 )
R5-232 receiver
1489
M5M5832
OKI Clock Chip
(U41 )
(U 12)
Programmable Interval Timer
8253
8259A
Interrupt Controller
(U14,15)
(U5 )
2651/61
Programmable UART
7805
+5 volt regulator
(U 1,7)
(U9 )
7812
+12 volt regulator
7912
-12 volt regulator
(U2)

OTHER ELECTRICAL COMPONENT5
(1)
(2)
(3)
(2)
(1)
(1)
(4)
(4)
(1)

Zener Diode 1N751A
5ignal Diode 1N941 or sim.
Transistor NPN 2N3904
Transistor PNP 2N3906
Crystal 5.0688 Mhz
Crystal 32.768 Khz
39 mfd tantalum capacitor
6.8 mfd tantalum capacitor
4.7 mfd tantalum capacitor

(D 1)

(D2, 4)
(Q2-4)

(Q1,5)
(X2)
(X3)

(Cl,2,5,6)
(C3,4,7,8)
(C15)

89

(2)
(1)
(1)
(1)
(1)
(26)
(1)
(1)
(5)
(5)
(3)
(8)
(1)
(1)
(5)
(1)
(5)

.01 mfd disc capacitor
(C9,10)
.01 mfd mylar capacitor
(C14 )
.001 mfd mylar capacitor
(C13 )
22 pfd disc capacitor
(Cll )
9-35 pfd trimmer capacitor
(C12)
bypass, disc capacitor
180 ohm resistor
(R3)
(Rl )
560 ohm resistor
lK ohm resistor
(R2,18,19,23,24)
1.5K ohm resistor
(R22, 27-30,33)
2.2K ohm resistor
(R8,16,38)
4.7K ohm resistor
(RI0-13,15,20,21,26)
6.8K ohm resistor
(R9)
8.2K ohm resistor
(R14)
10K ohm resistor
(R4-7,36)
20K ohm resistor
(R37)
4.7 or 5.1K ohm SIP resisitor
(R17,31,32,34,35)

MECHANICAL COMPONENTS
circuit board
(46) low profile sockets
(3)
8 position DIP switches
(1)
26 pin transition connector
(1) 2 pin Molex connector
(2)
8 position DIP shunts
(2)
8 position DIP headers
(2) heat sinks
(4) sets 6-32 hardware
(2)
card ejectors
(1)
battery holder
(1) battery Mallory PX-21 or Eveready 523
(1) User's manual
(1) Assembly manual (if unkit)
(1)

(S 1-3)
(Jl)
(J3)

The following components are not supplied by CompuPro
unless ordered separately. U13,U16,U17,Xl,D3, and R25.

90

COMPONENT LAYOUT

co

......

U31

25LS2521

19

R31

R11

o

XA

46

U33

SYSTEM SUPPORT 1

45

COMPUPRO division GODBOUT ELECTRONICS

162G
Page 1 of 3

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92

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----..1

5.06St+lz

4 PHANTOM
67

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U38

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U43b-1O

Dl
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95

2 WRITE

RD"

READ
, A3

M
Al
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XT

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U41

OKI
MSM5832

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32.768
WATCH CRYSTAL

U27-6

7

10K
03

UNUSED GATES

02

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011

>
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GND

13
U26-8

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©1981

94

INDEX OF CONTENTS
About System Support 1 •
Address Decoder, Theory
Address Selection
I/O
Memory • • • •
Extended, Memory • • • • • • • • ••
Battery,
Connec t ing • • • • •
Holder, Mounting ••
Replacement
Clock (see Real Time Clock)
Configuration (Hardware)
Quick Reference • • • • • • •
Full Reference •
I/O Port Map • • • •
Interrupt,
Controller, Disabling
Con-troller, General
Jumpers and Options
Programming • . • • • • • • • •
Theory of Operation • • • • • •
Using with DDT • • • • • • • • • • • • •
Using with Math Chip • • • • • •
Interval Timers,
General
Jumpers and Options
Pr.ogramming
•••••••
Theory of Operation • • • • •
Logic Diagram •• e· • • • • . • • • • • • • •
Math _Processor,
G:eneral • • • • • •
Programming
• • • • •
Theory of Operation
Using Higher Speed • • •
Using with Interrupts • • • • • • • • •

co
en

7
83
9

9
11
18
18
18

5
9

19
57
13,36
13
35
84
35

15
15,59
15
58
86

91
69,75
66
86
13

15

Memory,
Address Selection • • • • • • •
Battery Backup. •
• ••••
Global/Extended Address
PHANTOM* Response
Theory of Operation
•••••
Parts List • • . . • • •
Parts Placement Diagram
••••••
PHANTOM* Response Options
Programming Considerations (also see under
individual functions) • • • • •
DDT, use of • • • • •
Power-up Initialization
pSTVAL*, use of
PWRFAIL*
Jumpering to NMI* • • • • •
Theory of Operation
Real-Time-Clock
Programming
Theory of Operation
RESET* vs SLAVE CLR* ••
RS-232 Channel (see Serial Channel)
Serial Channel
General
Jumpers and Options
Programming
Theory of Operation
SLAVE CLR* vs. RESET*
Technical Overview • • •
• • • • •
Theory of Operation (also see under
individual sections) • • • • • •
Vectored Interrupts (see Interrupts)
Wait States,
Selection
Theory of Operation • • • • • •

10
12
11
12
84

89
90
12
20
35
20

17
17
87
26

87
17
16
16
20
86

17
7

83

12

87

CUSTOMER SERVICE INFORMATION
Our paramount concern is that you be satisfied with any Godbout
CompuPro product. If this product fails to operate properly, it may be
returned to us for service; see warranty information below.
If you need further information feel free to write us at:

P.O. Box 2355, Oakland Airport, CA 94614.
When writing, please be as specific as possible concerning the nature
of your query. We maintain a 24 hour a day phone for taking orders,
(415) 562-0636. If you have any problems or questions which cannot
be handled by mai I, this number can be used to connect you with our
technical people ONLY during normal business hours (10am-5pm
Pacific Time). We cannot return calls or accept collect calls.

LIMITED WARRANTY INFORMATION

/

Godbout Electronics will repair or replace, at our option, any parts
found to be defective in either materials or workmanship for a period of 1
year from date of invoice. Defective parts MUST be returned for
replacement.
If a defective part causes a Godbout Electronics product to operate
improperly during the 1 year warranty period, we will service it free
(original owner only) if delivered and shipped at owner's expense to and
from Godbout Electronics. If improper operation is due to an error or
errors on the part of the purchaser, there may-be a repair
charge. Purchaser will be notified if this charge exceeds $50.00.
We are not responsible for damage caused by the use of solder intended for purposes other than electronic equipment construction,
fai lure to follow printed instructions, misuse or abuse, unauthorized
modifications, use of our products in applications other than those intended by Godbout Electronics, theft, fire, or accidents.
Return to purchaser of a fully functioning unit meeting all advertised
specifications in effect as of date of purchase is considered to be comple~~ fulfillment of all warranty obligations assumed by Godbout
Electronics. This warranty covers only products marketed by Godbout
Electronics and does not cover other equipment used in conjunction
with said products. We are not responsible for incidental or consequential damages.
Prices and specifications are subject to change without notice, owing
to the volatile nature and pricing structure of the electronics industry.

"System Support I" is a trademark of w.J. Godbout.
"8086 FAMILY USER'S MANUAL" October 1979, pages Al37 through
A157, Copyright 1979, Intel Corporation. "PERIPHERAL DESIGN
HANDBOOK" August 1980, pages 1-61 through 1-68, Copyright
1980, Intel Corporation. "COMPONENT DATA CATALOG" January
1981, pages 8-21 through 8-26, and pages 8-31 through 8-38,
Copyright 1981, Intel Corporation.
Reprinted by permission
of Intel Corporation.
Contents of this booklet Copyright 1981 by Godbout Electronics. All
rights reserved.
We encourage quotation for the purposes of product
review i f source is credited.
Printed in U.S.A.
COMPUPRO

division

GODBOUT ELECTRONICS

BOX

2355. OAKLAND AIRPORT. CA 94614



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