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No. 16
Proceedings of the
EASTERN JOINT COMPUTER CONFERENCE
December 1-3, 1959
Boston, Massachusetts
Sponsors:
THE INSTITUTE OF RADIO ENGINEERS
Professional Group on Electronic Computers
THE AMERICAN INSTITUTE OF ELECTRICAL ENGINEERS
Committee on Computing Devices
THE ASSOCIATION FOR COMPUTING MACHINERY
Printed in the United States of America
Price $3.00
ADDITIONAL COPIES
Additional copies may be purchased from the following sponsoring societies at $3.00 per copy. Checks should be made payable
to anyone of the following societies:
INSTITUTE OF RADIO ENGINEERS
1 East 79th Street, New York 21, N. Y.
AMERICAN INSTITUTE OF ELECTRICAL ENGINEERS
33 West 39th Street, New York 18, N. Y.
ASSOCIATION FOR COMPUTING MACHINERY
2 East 63rd Street, New York 21, N. Y.
COPIES OF PRIOR PUBLICATIONS
Copies of publications issued in connection with the prior Joint
Computer Conferences listed below may also be purchased from
the above societies.
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CONFERENCE
Eastern
Eastern
Western
Eastern
Western
Eastern
Western
Eastern
Western
Eastern
Western
Eastern
Western
Eastern
Western
LOCATION
Philadelphia
New York City
Los Angeles
Washington
Los Angeles
Philadelphia
Los Angeles
Boston
San Francisco
New York City
Los Angeles
Washington
Los Angeles
Philadelphia
San Francisco
Dec.
Dec.
Feb.
Dec.
Feb.
Dec.
Mar.
Nov.
Feb.
Dec.
Feb.
Dec.
May
Dec.
Mar.
DATE
10-12, 1951
10-12, 1952
4-6,1953
8-10, 1953
11-12, 1954
8-10, 1954
1-3,1955
7 -9, 1955
7 -9, 1956
10-12, 1956
26-28, 1957
9-13, 1957
6 -8,1958
3 -5,1958
3 -- 5, 1959
Copyright © 1959
THE NATIONAL JOINT COMPUTER COMMITTEE
No. 16
PROCEEDINGS OF THE
EASTERN 'JOINT COMPUTER CONFERENCE
PAPERS PRESENTED AT
THE JOINT IRE-AIEE-ACM COMPUTER CONFERENCE
BOSTON, MASSACHUSETTS, DECEMBER 1-3, 1959
Sponsors
THE INSTITUTE OF RADIO ENGINEERS
ProFessional Group on Electronic Computers
THE AMERICAN INSTITUTE OF ELECTRICAL ENGINEERS
Committee on Computing Devices
THE ASSOCIATION FOR COMPUTING MACHINERY
Published by
THE 1959 EASTERN JOINT COMPUTER CONFERENCE
FOR
THE NATIONAL JOINT COMPUTER COMMITTEE
2
195,9 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
NATIONAL JOINT COMPUTER COMMITTEE
Chairman
Vjce-Chairman
Harry H. Goode
Department of Electrical Engineering
University of Michigan
Ann Arbor, Michigan
Paul Armer
The RAND Corporation
Santa Monica, California
Secretary-T~easurer
Margaret R. Fox
National Bureau of Standards
Department of Commerce
Washington, D. C.
IRE Representatives
AlEE Representatives
Werner Buchholz
Product Development Laboratory
IBM Corporation
Poughkeepsie, New York
R. R. Johnson
Computer La.boratory
General Electric Company
Phoenix, Arizona
R. D. Elbourn
National Bureau of Standards
Department of Commerce
Washington, D. C.
Claude A. R. Kagan
Engineering Research Center
Western Electric Company, Inc.
Princeton, New Jersey
Harry H. Goode
Department of Electrical Engineering
University of Michigan
Ann Arbor, Michigan
Stanley Rogers
Convair Division
General Dynamics Corporation
San Diego, California
Willis H. Ware
The RAND Corporation
Santa Monica. California
Morris Rubinoff
Moore School of Engineering
University of Pennsylvania
Philadelphia, Pennsylvania
ACM Representatives
Paul Armer
The RAND Corporation
Santa Monica. California
J. D. Madden
System Development Corporation
Santa Monica, California
H. R. J. Grosch
Corporation for Economic & Industrial Research
Los Angeles, California
F. M. Verzuh
Massachusetts Institute of Technology
Cambridge, Massachusetts
Ex-Officio Representatives
R. W. Hamming (ACM)
Bell Telephone Laboratories
Murray Hill, New Jersey
Richard O. Endres (IRE)
Rese Engineering, Incorporated
Philadelphia, Pennsylvania
Reuben A. Imm (AlEE)
IBM Corporation
Rochester, Minnesota
Headquarters Representatives
Jack Moshman CACM)
Corporation for Economic & Industrial Research
Arlington, Virginia
L. G. Cumming
The Institute of Radio Engineers
New York. New York
R. S. Gardner
American Institute of Electrical Engineers
33 West 39th Street
New York, New York
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
3
TABLE OF CONTENTS
Foreword ............................................................................ Frank E. Heart, Conference Chairman
Page
5
Award for the Best Presentation of a Technical Paper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Computers of the Future ....................................................................................... Rex Rice
8
Negative-Resistance Elements as Digital Computer Components .. , .......................................... Morton H. Lewin
15
Deposited Magnetic Films as Logic Elements .................. " ............... . A. Franck, G. F. Marette and B. I. Parsegyan
28
Solid-State Microwave High Speed Computers ............................................................ Jan A. Rajchman
38
The Engineering Design of the Stretch Computer. . . . . . . . . . . . . .. . .............................................. Erich Bloch
48
Design of Univac-LARC System: I. .. ........ . ...................... J. P. Eckert, J. C. Chu, A. B.o Tonik and W. F. Schmitt
59
Design of Univac-LARC System: II ............................................... H. Lukojf, L. M. Spandorfer and F. F. Lee
66
Arithmetic and Control Techniques in a Multiprogram Computer ............ " .. . N. Lourie, H. Schrimpf, R. Reach and W. Kahn
75
The Virtual Memory in the STRETCH Computer ................................................. J. Cocke and H. G. Kolsky
82
A Combined Analog-Digital Differential Analyzer ....................................................... Harold K. Skramstad
94
The System Organization of MOBIDIC B ................................................................. Stanley K. Chao
101
A Universal Computer Capable of Executing an Arbitrary Number of Sub-Programs Simultaneously ................. John Holland
108
The Multi-Sequence Computer as a Communications Tool. ........... " .......................... " ............ J. N. Ackley
114
Realization of Boolean Polynomials Based on Incidence Matrices ....................... . S. Okada, Y. Moriwaki and K. P. Young
120
Applications of Boolean Matrices to the Analysis of Flow Diagrams ........................................... Reese T. Prosser
133
SIMCOM - The Simulator Compiler .................................................................. Thomas G. Sanborn
139
Unusual Techniques Employed in Heat Transfer Programs ......................... . D. J. Campbell and Mrs. D. B. Vollenweider
143
The Automatic Transcription of Machine Shorthand ........................................................... Gerard Salton
148
Critical-Path Planning and Scheduling ................................................... . J. E. Kelley, Jr., and M. R. Walker
160
The Automatic Digital Computer as an Aid in Medical Diagnosis ....................... . C. B. Crumb, Jr., and C. E. Rupe, M.D.
174
An Advanced Magnetic Tape System for Data Processing ................................................ Richard B. Lawrance
181
A High Speed, Small Size Magnetic Drum Memory Unit
for Subminiature Digital Computers ............................... . M. May, G. P. Miller, R. A. Howard and G. A. Shifrin
190
Temperature Compensation for a Core Memory. . . . . . . . . . . . . . . . . . . . . . . . .. . A. H. Ashley, E. U. Cohler and W. S. Humphrey, Jr.
200
Use of a Computer to Design Character Recognition Logic ... , ................................................... R. J. Evey
205
A Self-Organizing Binary System ....................................................................... Richard L. Mattson
212
Alpha-Numeric Character Recognition Using Local Operations ................................................... J. S. Bomba 218
Pattern Recognition and Reading by Machine ............................................... W. W. Bledsoe and I. Browning
225
Discussion of Problems in Pattern Recognition ............ , ..
233
A Computer Analytic Method for Solving Differential Equations ............................................... Leo Hellerman
238
Normalized Floating-Point Arithmetic with an Index of Significance ............................ H. L. Gray and C. Harrison, Jr.
244
Determination of Optimum Production Tolerances by Analog Simulation .......................... R. B. McGhee and A. Levine 249
The Crossed-Film Cryotron and Its Application to Digital Computer Circuits ... V. L. Newhouse, J. W. Bremer and H. H. Edwards
255
4
1959 PROCEEDINGS OF THE EASTERN JOINT. COMPUTER CONFERENCE
EASTERN JOINT COMPUTER CONFERENCE COMMITTEE
Chairman. . . . . . . . . . . .
Program Committee ...
Frank E. Heart, MIT Lincoln Laboratory
. Jean H. Felker, Chairman, Bell Telephone Laboratories
Robert A. Kudlich, Vice Chairman, AC Spark Plug Division
Mandalay Grems, IBM Corporation
Ben M. Gurley, Digital Equipment Corporation
John W. Haanstra, IBM Corporation
Marvin Jacoby, Sperry Rand Corporation
W. J. Poppelbaum, rniversity of Illinois
Publications . .
Harlan E. Anderson, Chairman, Digital Equipment Corporation
John L. Atwood, Digital Equipment Corporation
Richard L. Best, Digital Equipment Corporation
William Hosier, Sylvania Electric Products, Inc.
Lawrence R. Jeffery, The MITRE Corporation
Local Arrangements. .
Harrison \V. Fuller, Chairman, Laboratory for Electronics
Philip R. Bagley, Yice Chairman, The MITRE Corporation
Finance
David L. Bailey, The MITRE Corporation
Henry E. Frachtman, The MITRE Corporation
Hotel '. . . . . .
S. Paul Blumenthal, Laboratory for Electronics
Alfred E. Ventola, Jr., Laboratory for Electronics
Publicity and Printing.
Douglas T. Ross, Massachusetts Institute of Technology
George D. Wood, Jr., Massachusetts Institute of Technology
Robert Kramer, Massachusetts Institute of Technology
Registration. . . . .
Robert Pearson, Laboratory for Electronics
Henry L. Schmitz, Jr., IBM Corporation
Trips ..
Rollin P. Mayer, The MITRE Corporation
Alexander Vanderburgh, MIT Lincoln Laboratory
Hospitality.
Arthur D. Hughes, The National Company
Frederic W. Spearin, The National Company
Exhibits.
Howard I. Cohen, Sylvania Electric Products, Inc.
Exhibits Management..
John Leslie Whitlock Associates, Arlington, Virginia
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
5
Foreword
For some time it has been customary to hear complaints about the limited value of large technical
conferences. Despite this fact, I represent a group of
people who have worked assiduously to arrange this
affair. And over 2,300 people have expended considerable effort to attend. It is interesting to inquire
seriously as to the reason for so much effort. There
are, of course, a number of very cynical answers.
However, I would like to offer a less cynical one.
Perhaps it is only a convenient rationalization1 but
I still find the computer field an exciting and stimulating domain. The excitement about the computer
arises in much the same way as the excitement about
atomic energy; one may almost feel the changes being
produced in society. For an applied scientist or engineer, it is usually the applications which lend to a
discipline an aura of excitement. Well, then, I believe
that many of us are here because of a continued enthusiasm in the possibilities of the computer. The
number and importance of the potential applications
are still increasing more rapidly than the onset of
general boredom.
In the tiny span of years from the first to the ninth
EJCC, we have been witness to a wholesale change
in the techniques of scientific computation, witness to
a revolution in business data handling, and witness to
the use of computers for real time control of weapons
systems, industrial plants and space vehicles. Surely
these events are exciting enough to partially justify
our large conferences.
And yet I believe that the most important applications of the computer have not yet been realized.
Certainly computer inroads in the business world and
the industrial plant have only just begun. However,
for me, the most exciting applications are those which
th~eaten to affect all aspects of human progress. I
would like to point toward two such potentially
pervasive applications - two impending applications
that excite me considerably.
The first is the application of the computer in
studying and copying the characteristics of biological
systems. This is a doubly potent use of a computer,
involving useful feedback, because real gains in
understanding biological systems might lead to better
computer systems. The first steps in this direction
have already been taken. Computers are being used
for analysis of electroencephalograph data and will
be used to study many other types of clinical data.
Computers have been used to permit construction
and study of models of neuron assemblages. A whole
gamut of pattern recognition techniques is undergoing intensive investigation. People are trying to
learn about learning. (Actually, even if we don't get
very far, we will have the harmless fun of constructing more and better maze-solving programs and
chess-playing programs while trying.)
The second application may be characterized as
the library problem. I think that the proper way to
measure the importance of this application is to
think of it as a new way for people to tap the accumulated knowledge of the recent and distant past.
.The printing press was one such new way to tap the
experience of the past, but now there are difficulties.
The large number of printed books and journals, the
existence of important scientific communities separated by language barriers and the inadequacies of
our present retrieval techniques have seriously
restricted our ability to connect pertinent information
to pertinent researchers.
The pace of scientific progress might well take a
large jump if, upon receiving a new project, a researcher might receive a graded synthesis of all
human experience on that subject from the local
library computer. Similarly, a lawyer, faced with a
new case, would surely like to receive a relevanceordered listing of all applicable court experience, and
a doctor might be willing to trade clinical data and
careful reporting in return for ordered estimates of
diagnosis. In its present form, the technical journal
itself may be facing its last few decades. The library
computer concept is quite powerful, and it may some
day be expedient for an author to send a new technical paper only to the library, without the continued
expenditure of quite so much paper.
So, I don't think the excitement is dying out; I
think it is increasing, and I expect that computer
conferences will be of interest and value for some
time to come.
FRANK
E.
HEART
Conference Chairman
6
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
LIST OF EXHIBITORS
Aeronutronic Division, Ford Motor Company
AMP, Inc.
Ampex Corporation
AN elex Corporation
Autonetics Division, North American Aviation, Inc.
Bel Air Industries, Inc.
Bendix Computer Division
Benson-Lehner Corporation
Bryant Computer Products Division
Burroughs Corporation, ElectroData Division
C-E-I-R, Inc.
C & K Components, Inc.
C. P. Clare & Company
Computer Control Company, Inc.
Di/An Controls, Inc.
Digital Equipment Corporation
Digitronics Corporation
Elco Corporation
Electro-Measurements, Inc.
Electronic Associates, Inc.
Engineered Electronics Company
Fairchild Publications, Inc.
Fairchild Semiconductor Corporation
Ferranti Electric, Inc..
General Ceramics Corporation
Gene.cal Electric Company, Light Military Electronics Department
G P S Instrument Company
Harford Metal Products, Inc.
Harvey-Wells Electronics, Inc.
Instrument Specialties Company, Inc.
Intellectronics Laboratories, Ramo Wooldridge Division, Thompson Ramo Wooldridge, Inc.
International Business Machines Corporation
Laboratory for Electronics, Inc.
Librascope, Inc.
Micro Switch Division, Minneapolis-Honeywell Regulator Company
Minneapolis-Honeywell Regulator Company, DAT Amatic Division
Minnesota Mining and Manufacturing Company
The National Cash Register Company
Packard Bell Computer Corporation
George A. Philbrick Researches, Inc.
Philco Corporation, Government and Industrial
Division
Potter Instrument Company, Inc.
Radio Corporation of America
Reeves Soundcraft Corporation
Remington Rand Univac Division, Sperry Rand
Corporation
Rese Engineering, Inc.
Royal McBee Corporation
Sprague Electric Company
Stromberg-Carlson - San Diego
Sylvania Electronic Systems Division, Sylvania
Electric Products, Inc.
Tally Register Corporation
Telemeter Magnetics, Inc.
Teletype Corporation
F. D. Thompson Publications, Inc.
Union Switch & Signal Division, Westinghouse Air
Brake Company
Wang Laboratories, Inc.
Washington Aluminum Co., Inc.
John Wiley & Sons, Inc.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
Award for the Best Presentation
of a Technical Paper
In recognition of the fact that technical programs
are sometimes marred by careless or obtuse presentation of papers, the Eastern Joint Computer
Conference Committee decided to emphasize the
importance of a good oral presentation by making
an award of $;300 for the best presentation at the
Conference of a paper describing significant work
in the computer field.
Awarded to
DR. HAROLD
Dr. Harold K. Skramstad was
born in Tacoma, Washington, in
1908. He received a B.S. degree from the College of Puget
Sound and a Ph. D. in physics
from the University of Washington. He has been with the National Bureau of Standards since
1935 and is presently Assistant
Chief for Systems, Data Processing Systems Division.
He worked in the field of aerodynamics until World War II,
when he turned his efforts to
guided missiles. He was a pioneer
in this field, playing a key role in
the development of the "BAT"
missile. He was responsible for
the development of one of the
first flight simulator facilities.
He is an Associate Fellow of the
Institute of Aeronautical Science
and a Senior Member of the Institute of Radio Engineers. He
also served as a member of the
Air Force "Advisory Board on
Simulation," and he was first
chairman of the Eastern Simulation Council.
K.
SKRAMSTAD
National Bureau of Standards
Washington, D.C.
for his presentation of a paper entitled:
"A Combined Analog-Digital Differential
Analyzer"
An analog-digital differential analyzer has been
designed which combines the analog advantages
of high speed and continuous representation of
variables with the digital capability of high precision and dynamic range. I t is based on representing dependent variables by two quantities, a
digital number representing the more significant
part and an electrical voltage representing the
less significant part. As in the electronic analog
computer, time is the independent variable.
The design of components required to build a
computer of this combined type, such as integrators and multipliers, are given, and examples
of how the solution of a few elementary differential equations would be carried out are presented.
7
8
1959 PROCEEDINGS OF THE EASTER}·l JOINT COMPUTER CONFERENCE
Computers of the Future
REX RICEt
combination of logical elements interconnected and
timed to perform major operational sequences in a
HIS PAPER considers the advances required in
data processor. One of our future objectives is to
many related technologies to revolutionize the
create major digital system functions in one continuconstruction and use of digital data processing
ous, automated manufacturing sequence.
systems. In the following discussion we are particularly concerned with the radical change in fabrication
FUTURE METHODS
technology and wish to analyze the effect that this
change will have on our methods of computer design
A possible future method for producing major sysand specification.
tem functions such as complete working storage
registers, process units, memory arrays, etc., is illusPRESENT METHODS
trated in Fig. 2. We envision this manufacturing line
The manufacturing techniques used in the elec- as a set of printing presses through which a conveyor
tronic portion of today's digital data processing sys- system passes. Substrate material is placed on the
tems are illustrated in Fig. 1. The active devices are conveyor and proceeds through the line. At each
stage one pattern of interconnections, insulation, or
active material is printed on the substrate. As required, bake ovens, etc., may be strategically placed.
Here, devices are standard by virtue of the materials
used. These materials are applied by a standardized
method to produce active elements, interconnections,
insulation, etc., in batches. The plates, inserted in
each press, are made in an automatic machine which
develops the appropriate layout under equation control for major system segments.
INTRODUCTION
T
I~ (B I~ I~ I~ iJ
BULK MAT'L
Fig. I-Present method.
standardized in these systems. Circuit standardization
is established at what may be defined as the Boolean
function level. Circuits for AND, OR, Invert, Latch,
Trigger, etc., are standardized individually. The
pluggable packaging usually combines several circuits, either of the same type or in selected groups.
A major system function such as a complete working
storage register and all its controls, an arithmetic
processing unit and its controls, etc., is obtained by
assembling a group of circuit packages on a panel and
interconnecting the circuit packages with individual
wires. At the time the individual circuits and packages are designed and optimized, very little information is available regarding their specific employ~nt
in systems functions.
A digital "system function" may be defined as a
tIBM Research Laboratory, Poughkeepsie, N. Y.
Fig. 2-A future method.
The figure illustrating future methods is only diagrammatic. The manufacturing method chosen will
probably depend on the basic component technology
and may be different for each type of component.
Before complete automation is realized it will be necessary to manufacture active elements separately and
to rely on automatic testing and insertion. The field
will be dynamic and the illustration indicates a trend,
not a specific technique.
Rice: Computers of the Future
Illustrative Example of a System Function
A serial-by-digit, decimal adder is used to illustrate
a system function as shown in Fig. 3. This represents
a portion of an arithmetic processing unit. The digital
code assumed is a decimal "one out of ten" representation, chosen because decimal matrix addition is
well understood. Other examples or codes would have
served equally well.
9
output line 1. The carry condition is remembered for
later use. Let us now consider circuits for the matrix'
in more detail.
Matrix Utilizing Individual, Standardized Boolean
Circuits
The circuit in Fig. 4 is a Boolean standardized twoway AND circuit with one transistor, four resistors,
and various internal interconnections. Several outputs may be wired together to form an appropriate
OR circuit. A two-way circuit is chosen, since for our
purposes in the addition matrix a three- or four-way
AND circuit has no advantage.
A
B
9
o
o
INPUT
DRIVE
MATRIX
FIRST HAlF ADO
DECIMAL
1
CONTROLS
AND DELAY
1
SECOND HAlF ADD.
O£CK A~ DRIVE
c
ADDITION - SERIAL BY DIGIT
Fig. 3-Illustrative example of a system function.
In this function a pair of decimal digits enters a
process unit at A and B and the added result is obtained at the output. A matrix, to be described in
detail, performs the first half-addition. Other elements provide input drive, output carry detection
recombination, and the second half addition. It i~
also necessary to store the presence or absence of a
carry, so that as succeeding pairs of digits are processed, the second half-addition circuit may be activated. Let it be assumed by way of example that A
equals 5 and B equals 6, as emphasized with heavy
marked lines. In the matrix the 5 on the vertical axis
together with a 6 on the horizontal axis activates an
AND circuit which places an output on the eleventh
diagonal. After passing through the carry detection
element, the eleventh diagonal is recombined with the
~
I
I----__t"--_--.. OUT
--~
Fig. 4-Standard "and-inverter" circuit (TRL).
'-----II
'--------------18
Fig. 5--Matrix utilizing standardized "Boolean" circuits.
A ten by ten matrix of these AND circuits is illustrated in Fig. 5. For clarity, the internal circuit connections and devices have been omitted. In the
matrix, addition is accomplished by the coincidence
of current on any pair of lines such as A = 5 and
B = 6. When the AND circuit at this intersection is
active, its output is placed on the eleventh diagonal.
For packaging purposes the designer has the choice
of packaging several AND circuits on a single pluggable unit. When the circuits were optimized, only
the two-way AND logic together with the output
loading conditions were known.
Let us now reexamine this same matrix from a system rather than a circuit viewpoint (Fig. 6). In this
specific matrix element only one AND circuit in the
A = 5 column and the B = 6 row is "on." This is a
system consideration and was not known at the time
the Boolean AND circuit was optimized. The vertical
column A = 5 will now be considered as a single
element.
System-Tailored Circuits
A circuit which is tailored to this system function
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
10
A
o
c
L...-_ _
II
The" B" entries are connected to the emitters of the
ten transistors in each of the ten circuits. The collectors are connected to the output lines, which are
functionally equivalent to diagonals in the previous
matrix. Note the identical configuration of the wiring
to the inputs of all ten matrix columns. The outputs
of each "system AND" circuit are connected in a
pattern which drops down to the next output line for
each successive group. Thus, to add 5 to the number
entering B the sixth AND circuit is activated. The
number 6 on the B entry is moved down five units on
the output, giving a sum of 11. Although the number
of transistors required in both matrix examples remains the same, the passive elements are eliminated
and the packaging pattern for both interconnections
and devices is drastically improved.
A
L~====================18
Fig. 6-Matrix utilizing standardized "Boolean" circuits.
is illustrated in Fig. 7. For convenience, transistors
have been shown, although other devices such as relays, tubes, cryogenic devices, etc., could have been
used. The input A supplies current to a common control which go.es to all the bases of the ten transistors.
Since only one line on the B input to the emitters is
active at any instant, only one transistor will be conducting. Let us now examine the addition matrix
utilizing this "system tailored" circuit.
5
cp
!
6Q)-
--II
Fig. 7-System tailored circuit (CS).
Matrix Utilizing System-Function Circuits
The complete matrix is again shown in Fig. 8, this
time utilizing ten of the system-function circuits. The
"A" entries on the vertical axis go directly to the
common control connections of the ten AND circuits.
Fig. 8-Matrix utilizing "system function" circuits.
In the illustration the solid lines represent a layer
of interconnections on the front of a printed substrate
and the broken lines, a second layer' on the rear.
Connections through the substrate are indicated by
dots. Inasmuch as ten system-function circuits are
used, ten component packages consisting of active
elements only may be mounted on a single substrate
that contains the complete interconnection wiring.
A computer may be described as "a bunch of wires
connected by active elements." This second method
of matrix design underscores that definition. Three
important features become apparent in this example.
First, careful attention to system-function circuits
will lead to logical layouts that are much easier to
express algebraically for equation-controlled manufacturing. Second, the amount of packaging and interconnections, and the number of elements involved can
be reduced over present methods. Third, new systemfunction device specifications will emerge.
System-Tailored Devices
The previous discussion presented an example in
which circuits and system-function logic were combined using standard transistors. Present active devices are individual elements packaged separately, as
shown in Fig. 9. The connections between the active
and passive elements are generally made by individual wires, although more recent systems use printed
wiring for circuit packages.
11
Rice: Computers of the Future
PRESENT
One of our major objectives is to reach the future
system illustrated here. Let us now consider some of
the more important work to be done to make this
possible.
o INDIVIDUAL ACTIVE ELEMENTS
o WIRED INTERCONNECTIONS
DIGITAL DATA PROCESSING
ApPROXIMATE RELATIVE COSTS
EARLY GENERATION
o MULTI-ELEMENT "SYSTEM TAILORED" UNITS
o PRINTED OR ETCHED INTERCONNECTIONS
LATER-FILMS
o BATCH-BULK TECHNIOUES MERGING ACTIVE DEVICES
AND INTERCONNECTIONS
PROBLEM____4___+ SOLUTION
FUTURE - MICROMINIATURIZATION
o SMALLEST ELECTRONIC ELEMENT IS TOTAL SYSTEM
Fig. 9-Devices "system tailored."
In an early generation, multi-element systemtailored devices will be available. In addition, a much
greater proportion of the interconnections will be
etched and printed. Multi-element miniaturized components have been made available in small quantities
by American Bosch Arma, the Diamond Ordnance
Fuze Laboratory, Hughes Aircraft, RCA, Texas Instruments, and others. Programs in molecular electronics to permit the use of plating and vacuumdeposition processes are also receiving attention.
Much of this work is for military applications but will
probably be available for commercial use in the near
future.
The production of interconnections and active elements in one continuous manufacturing process will
occur with the introduction of films, either thick or
thin, into systems. At this time, semiautomatic
methods of manufacture will be mandatory. Here it
is obvious that separate considerations of system
functions, circuits, and devices may no longer exist.
Magnetic coupling is used to accomplish switching in
thin film cryogenic systems and speeds are very high.
One suspects that nature also provides a medium
speed and cost arrangement if we are clever enough
to detect it.
Further in the future we may anticipate true microminiaturized systems constructed from automatic,
computer-controlled processes utilizing bulk materials. The late Professor Dudley Buck has defined a
microminiature computer as: "A computer on a scale
which could never be looked at in an optical microscope." In this technology, the cost of active elements
will approximate the cost of interconnections. Logical
designers may enjoy the luxury of utilizing thousands
of active elements to perform logical functions of a
complex nature.
The bar graph (Fig. 10, Line 1) shows the approximate relative costs of processing data in presently
available commercial general-purpose digital systems. Problem preparation and programming costs
are generally accepted as being approximately half
of the total. The remaining costs may be .divided
into two major items: electronic main-frame costs
and electromechanical peripheral-equipment costs.
The percentages vary from system to system, but
are essentially as follows: The cost of main-frame
electronics varies between 15 and 25 percent of the
total, and includes the main random access storage,
the arithmetic and logic unit, and controls. In the
main-frame, the switching devices cost approximately
one-third and the packaging (which includes circuit
cards, panels, interconnections, frames, display,
covers, etc.), approximately two thirds. The cost of
the electromechanical portion of a system may vary
between 25 and 35 percent of the total and may be
divided into two parts. The first is bulk storage involving mechanical motion. This part includes tapes,
discs, drums, etc., and their attendant electronic
equipment. The second part is the input-output
equipment, including communication devices.
TRANSLATION
(PROBLEM TO MACHINE)
ELECTRONIC ELECTRQ-MECH.
(MAIN FRAME)
(PERIPHERAL)
PRESENT
GENERAL PURPOSE SYSTEMS
NEXT GENERATION
SYSTEM ORIENTED CIRCUITS
MACRO-INSTRUCTIONS
AND PACKAGES
2ND GENERATION
SYSTEM ORIENTED MULTI-ELEMENT
DEVICES
EQUATION SPECIFIED
INTERCONNECfIONS
SPEDAL PUlPOSE
3RD GENERATION
PHYSlCALLY MERGED DEVICES
AND INTERCONNECTIONS
FUTURE
MICROMINIATURllATION
~ LANGUAGE-MACHINE LANGUAGE
Present Generation
General-purpose systems predominate at the present time. This is probably due to the relatively high
cost of research and development coupled with long
design and manufacturing lead-times for initial production. Instructions usually include an operation,
one or two addresses, and a few special control bits.
The instruction code at the machine language level
is relatively "micro" due to the general-purpose
requirement and for other reasons not covered here.
12
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
System specification normally starts with a market
analysis so that a potential product may be defined.
Performance, storage volume, input-output equipment, etc., are established at this time. Available
standard circuits and packages are considered during
the specification of system logic. Outputs from the
system design are block diagrams, or equations, or
both. At this stage we do not know where each device
or circuit will be placed, nor the length of interconnections.
In programming, present generation machines use
autocoders to translate from problem language into
machine language. The autocoders, in many instances,
involve execution time and occupy storage space.
This combination of autocoders and machine language is the result of the programmer's desire to have
a machine language different from the one technology
is able to economically provide.
Devices used in present systems, both active and
passive, are individually manufactured by semiautomated methods. This allows individual testing, selection, and replacement in the event of malfunction.
The circuits are Boolean optimized and the minor
packaging assemblages usually include several elementary functions. Recent trends as evidenced in
machines like the Philco TRANSAC, are toward the
inclusion of more Boolean-type circuits on each pluggable element. Interconnections are a mixture of
printed cards and hand inserted wires and cables.
The major mechanical design of a system starts
when logical specification and Boolean standardized
circuits are available. With this information, the
active and inactive elements may be located and
packaged. For the first time, lead lengths become
accurately known. The output from mechanical design is generally a complete set of blueprints which
go to the manufacturing engineering groups.
In the peripheral equipment area the bulk storage
usually involves magnetics and includes much mechanical equipment. Access to data in this type of
storage is either serial-by-bit or serial-by-character.
The input-output equipment is essentially mechanical, taking data from a keyboard to a buffer storage
and, later, taking data from a buffer to a printer to
produce hard copy.
Servicing is usually done by a combination of electrical tests and diagnostic programs. It involves
locating the defective active or passive elements and
substituting new pluggable cards.
The specification and design of present systems is
thus essentially a serial process in which most major
elements are individually standardized and then
assembled to make a system. The design feedback
loops, while many, have rather high impedance.
Next Generation
The next generation as illustrated by the bar
in Fig. 10, Line 2, may be characterized mainly by
system-oriented design and manufacturing techniques.
Commercial machines will probably remain generalpurpose in nature.
The bars illustrating approximate relative cost on
this and succeeding generations does not necessarily
indicate that the cost of an equivalent advanced
machine will be reduced. The length of the bars represents the relative proportionate cost for each of the
major elements in a system for a particular generation. Past experience has shown that as more powerful techniques become available we solve larger
problems; therefore, we have an option of obtaining
more computing for our millions or reduced costs for
the same amount of processing. This is obviously a
designer's choice and will be adjusted to suit requirements as he specifies a particular system.
A major change will occur in the specification of
systems. Logic and circuits will be merged to produce
new system function circuits utilizing standard devices. The physical location of components, the interconnection lengths and paths, and layout of the
package will be specified as an integral part of logic.
To attain these objectives a new "system-function
algebra" is necessary. This algebra, which will begin
with the logical Boolean expressions, must be enriched to include the active and passive device characteristics, the physical location of all components,
the interconnection paths and lengths, and timing.
Programming in this generation will be done with
more powerful macro-type instructions. Machine
language instructions will approximate the level
typified by coding systems such as FORTRAN.
Relatively speaking, more hardware will be in the
instruction controls with the objective of making
programming easy and fast.
Improved single-function devices and some use of
multifunction devices may be anticipated.
A maj or change in packaging as well as in logiccircuit specification will occur in this generation.
Complete system functions will be packaged on one
replaceable element. Interconnections will be etched,
printed, evaporated, or batch produced by other
automated techniques. Manufacturing equipment,
methods, and mechanical design techniques must
undergo the appropriate changes.
Service will be accomplished by locating and replacing malfunctioning major system functions. If the
individual devices are expensive, they may be replaced at a testing and service center so that the
system function may be returned to stock. If not,
the whole unit may be discarded. Extensive built-in
checking and automatic program diagnosis will be
included. The logic of the machine will require more
redundancy for checking and diagnostic purposes.
The next generation of systems thus involves major
improvements in logical design and packaging. New
devices or other research items are not necessarily
required.
Rice: Computers of the Future
Second Generation
Two major changes characterize the second generation systems. (Fig. 10, Line 3). First, system-tailored
multi-element devices will be used extensively. This
will influence mechanical design, packaging, and
manufacturing equipment. Secondly, special-purpose
machine systems to solve classes of problems will be
made on the same manufacturing line. The logical
specification of these machines will be generated by
computers utilizing system-function algebra. Extensions of the algebra will control the manufacturing
setup. This combination will drastically reduce design
and production lead times and cost of the product.
The availability of special-purpose systems will
ease programming difficulties through the use of
application-tailored languages to solve related classes
of problems.
System-function design techniques and devices will
be applied to bulk storage. For input-output, electronics will replace mechanical equipment wherever
possible.
Noon-line service will be performed since the
machine will be able to select alternate logical paths
in the event of a malfunction. At inspection periods,
previously-flagged defective system elements will be
removed and replaced.
Third Generation
13
Future Generation
We may envision a few aspects of future generations now (Fig. 10, Line 5). True rtu~crominiatur
ization meeting Professor Buck's definition will be
realized. Self-organizing systems will become possible
due to microminaturization and better understanding
of the logic involved. The use of self-organizing systems to find optimum solutions to problems will allow
us to synthesize more economical, special-purpose
systems for on-line use.
For programming, we may anticipate that machine
language will approximate or equal human language
if we have progressed properly to this point and if we
use self-organizing systems appropriately. A major
change in input-output techniques is required. Voice
and pattern recognition, and vastly improved display
and printing systems are needed.
In this generation, service will be accomplished by
throwing the whole computer away.
In summary, to progress from the present day data
processing capabilities to more desirable future systems, we require greatly increased logical capabilities,
vast amounts of storage, improved input-output
methods and more speed. All these elements tend to
require microminiaturization, batch-bulk processing,
automated logical synthesis, and equation-controlled
manufacturing. Consequently, both speed and system
cost require and benefit from this revolution.
The true revolution begins in the third generation.
(Fig. 10, Line 4). Here, device, package, and interconnections are inseparably merged. Major system
functions will be produced from bulk materials in
computer-controlled continuous manufacturing processes. Techniques such as vacuum deposition,
electron-beam writing, spraying, printing, etc., will
be utilized, depending on device technology chosen
relative to the speed and cost range desired. The use
of three-dimensional connections will alter packaging concepts. Miniaturization for complete systems
FUTURE COMPUTER
"ELECTRONICS"
may now be realized. This miniaturization will allow
dramatic increases in the number of active elements
STANDARDIZED ON.
o
a vailable for both logic and storage.
o
o
The availability of vast amounts of homogeneous
storage with internal logical capabilities will drasticOBTAINING.
o
ally alter programming methods. In particular,
o
built-in symbolic addressing will eliminate the inRESULTING IN'
o
efficient and tedious housekeeping associated with
o
present-day machines. Coupled wit~ special-purpose
Fig. ll-Future computer "electronics."
instruction sets, this will allow machine language to
approximate problem language.
CONCLUSION
The input-output equipment will now be reduced
Future computers (Fig. 11) will be standardized as
to that which is used to communicate with humans or
follows:
from machine to machine, since bulk storage is now
merged with the main frame.
1. Interconnections and active devices will be made
Service will be simple because automatic error
in a continuous process from bulk raw materials to
detection and correction by the machine will allow
finished product.
continuous operation. Defective elements will be 2. The device, circuit, and interconnection techreplaced at the next service period.
nology will merge.
EJ----,
EQUATIONS
BULK RAW MATERIALS
MERGED DEVICES AND INTERCONNECTIONS
SYSTEM FUNCTION ALGEBRA
o MANUFACTURING METHODS-COMPUTER CONTROLLED
EFFICIENT SPEaAL PURPOSE SYSTEMS
PRODUCED RAPIDLY AND ECONOMICALLY
MORE BRAINPOWER ON DEFINING PROBLEMS
CHEAPER PROBLEM SCLUTION
14
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
3. System-function algebra will be used to specify all
aspects of design.
4. Completely automated, computer-controlled manuf acturing methods will be used.
From these techniques we will obtain efficient
special-purpose digital data processing systems. They
will be produced economically with short design and
construction lead-times through complete automation. This will result in more brain power being
devoted to discovering and defining new problems,
and in their cheap, efficient solution.
DISCUSSION
J. H. Felker: (AT&T) I would like to hear you complete the job of
prophecy, Mr. Rice, and give us some idea of the timetable you envision for these first, second, third (and) fourth generation machines.
Mr. Rice: I have given that question considerable thought. We are
working on the next generation right now in many research laboratories. The universities are probably ahead in some respects in their
thinking on research in this area. It is not necessarily true that each
generation requires the specific items at the same time as shown in
the paper. If we develop microminiature computer devices ahead of
new programming techniques, they may be utilized early. I suspect,
and this is a personal observation, that the first models of microminiature computers are ten years off and the other items for the
next generation are scattered from three to five years away in
production. This is a guess on my part.
Mr. Felker: Thank you. With the three year period it takes to design
and get production of the conventional computer, how can you anticipate anything as drastically different from what we do today as
your microminiature computer in only ten years? Where are the
people and the knowledge that will permit this in ten years?
Mr. Rice: I agree that the ten years is probably on the optimistic
side. However, you will note that the methods of specification for
what I call the "algebra" of these systems includes the device characteristics and the physical layout. This implies that much of our
early work is in development of a new "system function algebra."
Once this algebra is automated, the design of new systems will be
done rapidly, and we will be less dependent on present day design
techniques.
H. Richmond (System Development Corp.): What is meant by
"machine language is approximately problem language"? What is
done in this case if a new variable is needed and your hardware is
built?
Mr. Rice: We have to recognize in our future designs that problem
language is not static. In other words, FORTRAN, if I may use
that example, has already proven that we need extensions. Therefore, I think the computer designers - and I happen to be one who
believes this - must design control sections which admit that programming language is dynamic. We should be able to incorporate
new instructions without going back and completely rewiring. There
is much research work to be done on the type of control situation
implied. I, for one, am very anxious and excited about working in
this area.
J. Feitler (J BM): What about analog-computer logic with digital-
computer hardware with many arithmetic elements (100 to 1000-plus
arithmetic elements) using microminiature components at "3rd
generation level"?
L. B. Harris (GE): How do you propose to implement self-checking of
system functions, that is, to pin-point the trouble?
Mr. Rice: Much work is being done on this subject in various research
and development laboratories. I think we have to reanalyze where
we want to spot errors. For example, in the talk a complete arithmetic process unit is shown as a single system function. I purposely
chose the one-out-of-ten code in this example, because it is possible
to put a single check device at the far end of the system. If more than
one pulse arrives, there is trouble. If less than one pulse arrives, there
is trouble. If only one pulse arrives, I would assume it is correct,
because the logical paths do not cross. Much research remains to be
done in this vrea, so I don't have a complete answer. I believe we
should analyze how small or how large an element should be when we
look for trouble. We should probably diagnose trouble in major elements rather than at the Boolean circuit level. We should also
examine our need for a single code throughout a complete system.
That is to say, do we need the same bit code in the processing element that we need in bulk storage. There are many ways of tackling
the problem, and I think we will have to look to future generations
for the complete answer.
C. H. Propster (GE): What reason do we have to think a self-organizing
computer will ever be produced?
Mr. Rice: Perhaps you are in a better position to answer this question
than I am. I believe that two things are necessary before self organizing systems are more tl>an (if I may use the expression loosely) ideas:
First, we have to really understand what we want to do in the system
to make it self-organizing. This is the lof!;ical consideration. Secondly,
it is fairly obvious it will take lots of components, so we have to
develop the manufacturing techniques to produce large numbers of
components economically. Whether or not we will get to the most
blue-sky systems is hard to predict, and I will shy away from that.
I think that manifestations of self-organizing systems are possible,
and that they will be developed.
P. J. Scola (GE): On the throw-away computer, what will the inputoutput wiring look like? Will there be any input-output?
Mr. Rice: This is a very difficult question to answer, even in an hour
and a half. At all stages in the future. we will need communications
from humans to the machine. We hope that voice recognition will
allow us to get from a human to the machine language. In the throwaway portion, I am specifically referring to the electronic elements of
the computer: that which we now know as the main frame. In particular, the capacity of the bulk storage associated with the main
frame is drastically increased. This will reduce the peripheral equipment such as tape, discs and so forth. So in effect we will be throwing
that section of I/O away. The concept of throwing away is also hard
for me to accept. However, I ask myself how are we going to repair
microminiature devices; and I come up with the answer that we had
better make them cheap enough so we can throw them away.
F. Panch: Would you care to speculate on what kind of computers
might be in use twenty to forty years from now?
Mr. Rice: Frankly, I ,have trouble envisioning what I call future
computers. I think that the major changes beyond these generations
will be in new uses for computing systems. If we can make computer
language approximate human language, or at least equal problem
language, the challenge will be in what we do with the system and
in making the systems cheaper so we can use them more frequently.
R. J. Brousseau (U of C): In saying that computer language should
approach problem language' in future computers, are you suggesting
that the computer hardware should accomplish the functions now
being borne by present automatic programs, such as mn~monic
instructions, symbolic memory names?
Mr. Rice: The answer to that question, in terms of generalities, is yes.
Mr. Rice: I am not certain that I fully understand the implication First we need better devices to go into memory so we may perform
of analog-digital computer hardware. If you mean we are working on . logic in the memory itself. At a time when this technique is sufficiently
separate portions of the problem in parallel, using the accuracyob- advanced, we may expect that instead of "addressing," we can tell
tained by digital techniques, I think there are existing machines the memory to find a particular field of data by specifying the "tag"
showing this tendency. Assuming that we can assemble thesE: systems inherent in the data. There are several other logical techniques which
to solve the classes of problems we have to solve, this is an interesting may be used for symbolic look-up. The extent to which designers can
area for development. As to the 3rd generation I don't think I would do this is dependent on the person specifying the problem. He must
hazard a guess.
establish a set of rules that is fixed.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
15
Negative-Resistance Elements as Digital Computer
Components*
MORTON H. LEWINt
ploying negative-resistance devices as the active
switching elements. The requirement of no memory
N DETERMINING the maximum repetition rate
dictates either monos table operation of the negativeof .a g~ven sw~tching circuit, the response of the
resistance elements or bistable operation with a
sWItchIng deVIce and the effect of other circuit
built-in reset to eliminate storage. (The possibility
parameters (including stray elements) must be taken
of combinational circuits composed of sequential subinto account. Although the switching speed is ulticircuits is ignored on the grounds that such complimately limited by the device, in many cases one
cated circuits will reduce the maximum speed of the
never reaches this theoretical lllaximum because cirsystem.)
cuit limitations play the dominant role. To solve this
For the case of monostable operation, if one reproblem, one is forced to devise extremely simple cirmoves
anyone of the negative-resistance elements
cuits with few components in order to minimize the
the
circuit, measures the static V-I characterfrom
effect of stray reactance. The use of two-terminal
isticseenlookinginto
the rest of the circuit from its two
negative-resistance elements allows one to do this.
terminals
and
then
superimposes
this on the negativeShockley and Mason! have proposed that the ultiresistance
characteristic,
there
is
always only one
mate high-speed semiconductor amplifying device is
stable
intersection,
for
all
input
combinations.
For an
a two-terminal negative-resistance element. They
all-passive
circuit,
such
as
a
conventional
diode
gate,
reason that, since the speed of semiconductor comone
intersection
(operating
point)
is
assured.
Assume
ponents is basically limited by the transit time of
carriers, the physical dimensions of devices operating that this measured characteristic can be approxiin the highest frequency ranges must be extremely mated by a straight loadline, in the region of interest
small. In the limit, fabrication problems dictate two- (A design to insure monostability is feasible only if
terminal active elements, where only one dimension this characteristic is "well-behaved" (i.e., monotonic)
in the region where it intersects the negative-resistneed be small.
This paper is first concerned with the general ance characteristic.) This leads to a simple situation
problem of using two-terminal negative-resistance which can be directly analyzed.
Typical voltage-controlled and current-controlled
devices as the only active switching elements in a
digital system. Specific circuits are then discussed negative-resistance characteristics are shown in Fig.
using a particular voltage-controlled negative-resist~ la. The two states for each device are most convenance device as an example. Much of this treatment iently chosen as operation in the two positive-resistcan be adapted to other negative-resistance elements. ance regions on both sides of the negative-resistance
region. Thus, for a voltage-controlled element, the
state is defined by the voltage across the device, and
GAIN
for a current-controlled element by the current
A combinational switching circuit is defined as a through it. Under the conditions described above, the
circuit whose outputs depend only on the present in- circuits to be analyzed become those shown in Fig. lb.
puts. This is to be distinguished from a sequential The combination of R and the power source represwitching circuit in which the outputs depend not sents the Thevenin equivalent of the linearized measonly on the present inputs but also on the past his- ured characteristic.
tory of inputs. Thus, a combinational circuit, by
Monostable operation can be achieved in two ways
definition, has no memory.
as indicated by the load-lines in Fig. la. In the first
Consider a system of combinational circuits em- case, labeled "I", R < Rn min for the voltage-controlled element and R > Rn max for the current-controlled
element, where Rn = I dV/ dI I in the negative
* This work was supported by the Bureau of Ships, U. S. Navy,
resistance region. In the second case, labeled "II", R
under Contract NObsr 77523 with RCA. It is the basis of a dissertation to be submitted in partial fulfillment of the requirements
does not satisfy this inequality but the power supply
for the Ph.D. degree at Princeton University, Princeton, N. J.
values
are chosen to result in one intersection. Thus,
t RCA Laboratories, Princeton, N. J.,and Department of Elecfor case I monos table operation results regardless of
trical Engineering, Princeton University, Princeton, N. J.
the power supply parameters (assuming no reactance),
1 w: Shoc~ey and W. P. Mason, "Dissected Amplifiers Using
while for case II the power supply values must be
NegatIve ResIStance," Journal of Applied Physics, Vol. 25, No.5,
p. 677; May 1954.
chosen to avoid bistable operation.
INTRODUCTION
I
16
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
VOLTAGE-CONTROLLED
CURRENT-CONTROLLED
Fig. l-(a) Load-lines for monostable operation. (b) Equivalent circuits. (c) Load and signal source included. (d) Addition of reactive
element.
A DC-coupled system with no reactive elements
will be assumed. The output terminals and equivalent
load resistance RL are shown in Fig. lc. Input signal
sources are also included. R L represents the load furnished by other gate circuits in the net. Rl represents
the contribution to R of the internal parameters of
the circuit under consideration. The series or parallel
combination of Rl and R L, as appropriate, yields R.
For the voltage controlled case, RL can vary from ex>
to some minimum value and for the current-controlled
case, from 0 to some maximum value. The fact that
R L varies as indicated is a direct result of the twoterminal nature of all components. For example, an
examination of the possible configurations using voltage-controlled elements reveals that, in general, the
output current from a stage in a given state depends
on the states of the circuits being driven.
The values of Rl and 18 or VB must be chosen to
assure monostability for all loads. Thus, they must
be chosen such that only one intersection (of the
type shown in Fig. la) occurs for RL = ex> in the
voltage-controlled case and RL = 0 in the currentcontrolled case. If these conditions are satisfied,
monostable operation is assured for all R L.
Recall that any reactance in the circuit is assumed
negligibly small. For case I, looking into the circuit
from the output terminals, the load resistor RL sees
a net positive resistance for all voltage-current conditions. Hence, there is no possibility that an increment
of energy delivered to the load will be greater than
that supplied by the signal source, for any value of
R L • For case II, assuming a rectangular signal pulse
which raises the load-line sufficiently to cause the
operating point to switch to the other positiveresistance region, a simple calculation 2 reveals that
the input energy is at least as great as the output
energy. Thus, the requirement of monostability, in
the absence of adequate reactance, leads to a circuit
which has no gain.
If one now allows the use of appropriate reactive
elements (i.e., capacitance in parallel with the current-controlled device and inductance in series with
the voltage-controlled device), as shown in Fig. ld,
gain can be achieved. Note that the added reactance
cannot simply be greater than zero but must be
greater than a certain minimum established by stray
elements and the properties of the negative-resistance
device. (For an AC-coupled system, the reactive coupling elements must also be taken into account.) In
this case the gain ariRes from the fact that energy
stored in the reactive element is delivered to the load
when the negative-resistance device is triggered by a
small signal. Such circuits have been treated in the
literature3,4.5. It is shown there that the recovery
time associated with the reactance is a factor which
limits the maximum repetition rate of the circuit.
Bistable-with-reset operation allows one to achieve
gain without the use of reactive elements. Since the
furnishing of a reset signal may be considered to be
an additional function of the power supply, effectively a time-varying power source is now being considered. One possible arrangement is to let the power
supply (current or voltage) deliver a continuous
train of rectangular pulses, such that during each
pulse (excitation) the negative-resistance device can
go to either one of its two states, depending on input
conditions. The "reset" is then the termination of
the excitation pulse. It can be seen that such a power
supply also serves as a master clock. If one now calculates 6 the transition and recovery times for such a
system and compares this to the system with DC
power supplies and reactive elements, it is evident
that the former scheme has the higher maximum
repetition rate.
DIRECTIONALITY
Another fundamental problem is concerned with
making the system unilateral. For example, since the
negative-resistance element is a two-terminal device,
when one terminal is grounded, the other must act as
both the input terminal and the output terminal.
One must therefore provide some means to dictate
the direction of flow of information in the system (i.e.,
to make a circuit directional, so that a signal propa2
See Appendix.
3 B. G. Farley, "Dynamics of Transistor Negative Resistance
Circuits," Proc. IRE, Vol. 40, pp. 1497-1508; Nov. 1952.
4 A. E. Anderson, "Transistors in Switching Circuits," Proc. IRE,
Vol. 40, pp. 1541-1558; Nov. 1952.
Ii
A. W. Lo et aI., "Transistor Electronics"; Prentice Hall, 1955.
6
See Appendix.
Lewin: Negative-Resistance Elements as Components
17
gates Jrom input to output). Some possible techniques
for achieving directionality include use of passive
elements such as Hall-effect couplers or gyrators, use
of non-linear interstage coupling elements such as
conventional diodes, synthesis of three-terminal circuit configurations with some unilateral properties,
and separation of input and output functions in time
using a time-varying power supply. Some of these
techniques, as applied to circuits involving voltagecontrolled elements, are discussed in more detail following the treatment of basic logic circuits.
one phase, drives other circuits powered by the next
phase and is driven by still other circuits powered by
the previous phase. The excitation pulses overlap in
time such that information propagates between two
stages during the period when both are energized
simultaneously. Considering the block B in Fig. 2b,
one can see that the beginning of its supply pulse,
T 1 , corresponds to an "input" region and the end of
the pulse, T 2 , to an "output" region. The three-phase
arrangement shown is characterized by the fact that
there is always a group of circuits in the de-energized
condition at any given moment. As a result, in many
cases spurious signals are prevented from propagatPOWER SUPPLY
ing. The similarity between this scheme and the
Assuming the bistable-with-reset mode of operamultiphase clock systems used in conventional mation, with the momentary removal of power supply
chines is only superficial. Here the clock source is also
excitation as the method of resetting, the waveform
the power supply.
shown in Fig. 2a represents an acceptable source
waveform. The sequence of operations performed by
GENERALIZED ANALYSIS
each stage is th~n as follows: having been reset, a
given circuit is energized to an initial state. If the
Load-curves
combination of inputs presented to it is favorable, it
Consider a two-terminal "black-box" A whose
will switch to its other state. The state of the circuit
is then detected by the next stages. Finally, the cir- static V, I characteristic is given by either I A = gl(V A)
cuit is reset, energized again and ready to receive a or V A = /1(1.1). The box may simply hold a single
negative-resistance element or may include a more
new combination of inputs.
complicated arrangement of elements whose composite two-terminal V, I characteristic is given by the
above equations. /1 (or gl) may be any continuous
SOURCE:
function and is not single-valued in both V and I if
(0)
there are any negative-resistance regions. Now consider a second two-terminal "black-box" B whose
static V,1 characteristic is given by either I B =
g2(V B) or VB = /2(1 B). This will correspond to the
CPA
I
I
device which determines the load-curve. If g2(V B) =
rTrJ
ITI~
V B/R (i.e., /2(1 B) = I BR), then the device is the reR, ~entioned before, and the load-curve is a
sistor
CPs
straight load-line. In general, however, both Jl and /2
IT2~
are non-linear, negative-resistance characteristics.
The
two cases of interest are the following configuraCPc
tions:
(b)
(a) A constan t-vol tage source V across the series
Fig. 2-(a) Power supply waveform.
combination
of elements A and B.
(b) Three-phase power source.
(b) A constant-current source 18 feeding the
If the entire system is powered from the same parallel combination of elements A and B.
source, all circuits are reset simultaneously. The
energizing pulses must then be wide enough to allow The pertinent equations are:
signals to propagate from the inputs of the system to
Case (a)
Case (b)
its outputs, so that the repetjtion rate is limited by
V 4 = VB
IA = IB
the longest signal propagation time expected. To increase the repetition rate, the system is broken up
VS=VA+VB
Is = lA + IB
into small groups of gates such that each group is
[1]
VA =Jl(I A)
lA = gl(V A)
reset immediately after it has performed its function.
[2]
VA = Vs - /2(I A)
lA =I s -g2 (V A)
A sequence of resets is then required in order that information will continue to propagate and will not be The equilibrium points or quiescent operating points
erased. These requirements can be satisfied by a for a circuit are determined by the intersection points
multiphase power supply such as, for example, the of the two curves [11 and [2]. In either case, curvE,
three-phase waveform shown in Fig. 2b. Using this [1] is the characteristic of A and curve [2] is the loadmethod, a given gate or group of gates is powered by curve determined by the power supply and the
~RI
~A I
~B I I
~cb
I
c
I
8
18
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
characteristic of B. For case (a), the load-curve is the
image of B's V, I characteristic reflected through the
current axis, translated in the positive voltage direction a distance V s. For case (b), the load curve is the
image of B's V, I characteristic reflected through the
voltage axis, translated in the positive current direction a distance Is. The only stable operating points
are those determined by the intersection of two
positive-resistance regions.
Composite Characteristics
The determination of the composite V, I characteristic of two or more two-terminal elements, given
their individual characteristics, is important in the
analysis of negative-resistance circuits. To graphically obtain the composite characteristic from the
individual curves, one follows these simple rules;
(1) For two elements in series, each point of the
composite curve with coordinates V 11 II is obtained
by choosing any II and letting VI = V Al + V'B1 ,
where V Al is the voltage across element A at the
current II and V Bl is the voltage across element B
at the current II' Thus, one adds the voltages across
the individual elements at the same current.
(2) For two elements in parallel, each point of the
composite curve with coordinates V 11 II is obtained
by choosing any VIand letting II = I Al + I B}, where
I A 1 is the current through element A at the voltage
V 1 and I Bl is the current through element B at the
voltage VI' Thus, one adds the currents through the
individual elements at the same voltage.
TUNNEL DIODE
The remainder of this discussion is concerned with
one particular voltage-controlled negative-resistance
element. Similar or "dual" treatment can be given to
current-controlled devices.
The device to be considered was first reported by
EsakF and has since been investigated by others 8.
Since the phenomenon responsible for the unique
characteristics of the device is the tunneling phenomenon predicted by quantum mechanics, the device has been called the tunnel diode. It holds
promise of being an extremely fast element. Units
with time constants of a fraction of a millimicrosecond have been fabricated. Preliminary tests verify
that the device is capable of very high speed operation.
For the purposes of this analysis, the V, I characteristic of the tunnel diode will be assumed. Descriptions of the physical operation of the device are given
by EsakF and Sommers 8 •
The static voltage-current V, I characteristic for a
typical germanium unit is shown in Fig. 3. Typical
values for the critical points are indicated. The inverse slope Ro of each positive resistance region is of
the order of a few ohms.
I'fl
v
I
rTUNNEL
\
r
STATE "0"
Vi
I
(330mv)
'"
(450mv)
V
Fig. 3-Tunnel diode static characteristic. (Number indicated for typical Germanium unit.)
Since the tunnel'diode is such a low impedance element, it is not practical to assume that a constant
voltage source is available to supply power to many
units. In view of the fact that the source impedance
of any realizable voltage source will be of the order
of that of its load, it is more practical to assume that
the power to individual units is supplied from current
sources. In cases where a voltage source is desired,
an individual auxiliary device for each circuit is
necessary to simulate it. (This is demonstrated later.)
Therefore, in line with previous discussions, a threephase square-wave current source as shown in
Fig. 2b will be assumed.
THRESHOLD GATE
Consider the circuit shown in Fig. 4. Assume the
input terminals are connected to output terminals of
other similar circuits. As long as the tunnel diode D
is in the 0 (low voltage) state, the current into D, in
addition to Is, is approximately M(VI - Vo)/R,
where M is the number of driver units which are in
the 1 (high voltage) state and Is, VI and Vo are defined in Fig. 3. D will switch to the 1 state only if
Is + M(VI - Vo)/R > 1 the high threshold current at which the resistance becomes negative. Once
it has switched to the 1 state, it will remain there
even though the current into D is substantially less
than Is (corresponding to loading), as is evident
from an examination of the characteristic. Thus, the
circuit is capable of logical gain, since it can now
furnish a number of output current increments
(V I - V 9) / R to the next stages. The output of the
threshold gate, then, is 1 only if the total number of
0 ,
7 L. Esaki, "New Phenomenon in Narrow Germanium p-n Junctions," Phys. Rev. vol. 109, p. 603; Jan. 1958.
8 H. S. Sommers, Jr., "Tunnel Diodes as High-Frequency Devices," Proc. IRE, p. 1201; July, 1959.
K. K. N. Chang, "Low-Noise Tunnel Diode Amplifier," Proc.
IRE, p. 1268; July 1959.
Chang, Nelson, et a1.;'Tunnel Diodes for Low Noise Amplification," Proc. IRE WESCON, Aug. 1959.
Aarons, Holonyak, et a1., "Germanium and Silicon Tunnel
Diodes-Design, Operation and Application," Proc. IRE WESCON,
Aug. 1959.
DIODE
SYMBOL
Lewin: Negative-Resistance Elements as Components
1 inputs is greater than or equal to some integer T.
I s is adjusted to result in the correct logical function
(i.e., the correct T). For an OR gate, T is one; for an
AND gate, T equals the number of inputs; to generate
the CARRY output in a full adder, for example, the
number of inputs is three and T equals two, etc. The
circuit must be reset back to the operating point
below the threshold in order to be able to perform
its function again.
R
INPU~
I J L CURRENT
R
o
~~b~~E
OUTPUT
{
R
Fig. 4-Single-ended threshold gate.
It is evident that the merit of this circuit depends
primarily on the uniformity of diode characteristics
and the power supply tolerances involved. The maximum variations in 1 0 , Is, VIand Vo dictate the minimum current increments for reliable switching.
Advances in fabrication techniques have already resulted in high yields of diodes matched well enough
that a reliable logic system involving such circuits
appears readily realizable.
Is
.•.•.•,....-LOAD CURVE
(a)
R
Fig. 5--(a) Characteristic of two tunnel diodes in series and load-curve formed by D3 and Is. (b) Bistable operation. (c) Balanced
threshold gate.
The operation of the "single-ended" threshold gate,
described above, relies on the accurate determination
of the operating point on the negative-resistance
characteristic. A balanced or symmetrical circuit
offers advantages in many applications. Consider the
series combination of two tunnel diodes. Their com-
19
posi te characteristic is shown by the solid curve in
Fig. 5a. If a voltage V~ is applied across the series
combination, it is possible for the circuit to exist in
either of two states (i.e., one diode in the high voltage
state and the other in the low-voltage state and vice
versa). This is depicted in Fig. 5b where D2 and VI
determine the load-curve across the characteristic of
D 1 • If the voltage V 1 is applied as a pulse as is done
in the proposed system, one can determine to which
state the circuit goes by a small signal at the junction of D1 and D 29. This can be explained by noting
tha t during the rise of the pulse, the current through
D1 and D2 builds up to the point where both are very
near the crest of the hill. The small current into the
junction is sufficient to deterrnine which diode breaks
down. Thus if this current is positive, D1 goes to the
1 state and if it is negative D2 goes to the 1 state and
and D1 is forced to the 0 state.
The difficulty in obtaining a constant-voltage pulse
source to drive a large number of such low impedance
circuits has already been mentioned. However, the
tunnel diode has another important property in that
it can simulate a low impedance voltage source, of
magnitude V 1, if the current through it is greater
than 1o, the high threshold current. This property
is utilized to arrive at the final form of the balanced
circuit, shown in Fig. 5c. As is shown in Fig. 5a, the
dotted load-curve formed by D3 and 18 intersects the
characteristic of the series combination of Dl and
D2 at the appropriate point, if Is is large enough. The
circuit is now powered by the more realizable current
source.
The logical functions OR, AND and THRESHOLD are
achieved by requiring that the current into the junction be positive only when at least one, all or some
of the inputs are 1 's, depending on the function desired. This requires a reference current or bias as
shown. The source of this reference current can be
another tunnel diode again acting as a voltage
reference.
From the above description one can see that the
bfl,lanced circuit has several advantages over the
single-ended scheme. First, the sensitivity of the circuit depends only on the matching of the two negative-resistance elements and not on the exact values
of the critical points of the characteristic. Second, the
sensitivity is virtually independent of reasonable
power supply variations.
INVERTER
The composite characteristic of a tunnel diode Dl
in series with a resistance Rl is shown by the solid
curve in Fig. 6a. R1 is chosen to be approximately
R N , the magnitude of the linear approximation to the
negative-resistance (see Fig. 3). Suppose points a and
b were the only stable points for the circuit (corre9
This scheme was suggested by A. Lo.
20
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
I
Is
v
(a)
TELEVATED
OUTPUT
R2
R
INPUT oJV\""""",,,~.,4,-_
o-AN......---+--o ~8~~~f
(b)
(e)
(d)
Fig. 6-(a) Characteristic of tunnel diode and resistor in series and
l~a?-curves fo~~ed by D2 and Is. (b) Inverter circuit. (c) ProVISIOn for obtammg elevated output. (d) Composite characteristic
of DI, D2 and RI.
sponding approximately to a voltage VI applied
across the series combination). Taking the voltage
across the resistor as the output voltage we have that
point a yield as 1 output (high voltage ~ high current
through the resistor) and b yields a 0 output (low
voltage; low current through the resistor). Thus if
the circuit is always at a with an 0 input and at b w'ith
a 1 input, it would realize the inversion function.
To make?, and b the only stable operating points,
one can agaIn use another tunnel diode D2 to simulate a voltage source. The inverter circuit is then as
shown in Fig. 6b, and the intersections of the dashed
load-curve determined by D2 and Is with the composite characteristic of DI and Rl in series are shown
in Fig. 6a. To clarify the operation further, one can
plot the composite V, I characteristic of the entire
configuration of D 1 , D2 and R l • It is shown in Fig. 6d.
The horizontal (constant-current) load-line formed
by Is is indicated.
Since the voltage at point x (Fig. 6b) is high for
both operating points, one must include some provision for adding a constant to the normal output
voltage levels of the driver tunnel diode, in order that
a "I" driver output can furnish the current necessary
to bring the inverter over the a-hill to b. This can
be accomplished for a single-ended gate by the addition of a resistor R2 to the circuit, as shown in Fig. 6c.
The voltage of terminal T (during excitation) is
greater than the normal output voltage by a constant
amount I'sR2' assuming negligible loading at T. By
adjusting R2 so that the 0 output voltage is approximately VI, the 1 output voltage is then approximately 2V 1, and the required operation can be
achieved.
Assuming the pulse excitation scheme described
before, the operation of the inverter is now clear.
Whenever the circuit is excited and the input is a 0,
the inverter moves to point a, stays there, and the
output is a 1. If the input is a 1, there is sufficient
current input to bring the inverter over the hill in
the characteristic to point b and the output is a· O.
Note that for this latter case the output waveform
will show a transient high voltage before reaching
the low voltage 0 output. The next stage must therefore be powered by the next phase so that it is only
interested in the voltage level at the end of the pulse
(i.e., the "output function" region). For that case
such operation is satisfactory.
Note that the height of the a-hill in Fig. 6d depends on the value of R I • By adjusting 18 to lie sufficiently below the crest of this hill and driving the
circuit from a number of "elevated" outputs, one
can obtain the logical function of a threshold gate
whose output is inverted (i.e., NOT, OR-NOT, AND-NOT,
etc.).
UNILATERALIZATION
Unilateral operation can be defined as operation in
which signals can propagate in one direction only.
This is required to insure that spurious signals are
not generated in the system. The most obvious way
to insure unidirectional operation is to use normal
diode rectifiers as coupling elements. Current between stages can then flow only in one direction.
Other methods are possible in which the coupling between stages is resistive. For example, considering the
inverter circuit driven by an elevated output, one
can see that when the input to the inverter is 0 there
is essentially no current in the coupling r~sistor.
When the input is 1, there is a relatively high current
in the coupling resistor. Thus, again, the current in
the co.upling resi~t?r flows only in one direction. By
reverSIng the pOSItIOns of RI and DI (Fig. 6), so that
the output is taken across the tunnel diode, one has
a threshold gate with this unilateral property. Another unilateralization method is associated with the
ability of the power supply to separate input and output functions in time. This scheme is effective for the
balanced type of threshold gate. The circuit is receptive to an input signal only during a 'very short time
(i.e., the rise time of the power supply pulse), after
which it "locks" into one state or the other.
MULTILEVEL CIRCUITS
Consider the inverter configuration (Fig. 6b) in
which Is is reduced so that a third stable operating
pojnt c exists. This is indicated by the dotted curves
in Fig. 6 (a) and (d). Note that point c yields a 0
output. Assume that RI has been reduced sufficiently
to make the height of the a-hill, in Fig. 6d, comparable with the height of the c-hill. Let the circuit have
two inputs, driven from the normal outputs of other
Lewin: Negative-Resistance Elements as Components
tunnel diodes. The circuit operates in the following
fashion: If the two inputs are both 0, c is a stable
point and each time the circuit is excited the output
is a o. If one of the inputs is a 1 while the other is
a 0, there is enough current input to make the circuit move over the first hill to point a where it is
stable and the output is a 1. When both inputs are
1, there is sufficient current input to make the circuit move over both hills to point b, and the output
is again o. Thus, the output is 1 only when the two
inputs are different. This is the EXCLUSIVE-OR
(modulo-2 sum) function.
BINARY DIGIT
(a) BI NARY 01 GIT o.I\IIiR'\r--~--:-4>----4----.
CARRY
21
where it is stable, and the output is a 1. When two
inputs are 1, the circuit moves over the first two hills
to point Ob and the output is again o. For three 1
inputs, the circuit moves over all three hills to point
1 b and the output is again 1. Thus we have
Number of 1 inputs
SUM output
o
o
1
1
2
o
3
1
This fulfills the SUM function of a full adder. To realize the CARRY function, one simply uses a threshold
gate, of the type described before, which has the
same three inputs and which gives a 1 output when
the number of 1 inputs is two or greater.
STORAGE
I
V
o.ri1J~D ~~PUT
o.W
0,
{c)
~------------------~v
Fig. 7-(a) SUM output circuit for full adder. (b) Determination
of operating points. (c) Composite characteristic.
One can als~ realize the SUM output for a full
adder using a slightly different configuration. Consider the circuit shown inFig. 7a. The operating points
can be found by plotting the load-curve, determined
by 18 and the characteristic of the series combination
of D2 and Ds (Fig. 5a), across the characteristic of
Dl in series with Rl (Fig. 6a). This situation is depicted in Fig. 7b. 18 is chosen so that there are four
stable intersections, labeled Oa, 1 a, Ob and 1 b. These
correspond to 0 and 1 outputs as explained before.
The composite V,I characteristic of the whole configuration of three tunnel diodes and the resistor is
shown in Fig. 7c. Note the four intersections with the
constant-current (horizontal) load-line 1 They are
also labeled appropriately.
There are three inputs corresponding to two binary
digits and the CARRY from the previous digit. The
circuit operates in the following manner: When all
three inputs are 0, each time the circuit is excited
it moves to point Oa and is stable there so that the
output is a o. When one of the inputs is a 1 while the
others are 0, there is enough input current that the
circuit moves over the first hill (Fig. 7c) to point 1a,
8•
Since any negative-resistance element can exist in
two stable states with the proper DC load-line, it is
possible to use such a device to store information.
The term "static storage" can be applied to this
situation (DC load-line), because the voltage or current level of the negative-resistance device is fixed
when it is storing a particular bit. This type of
storage might be used in the memory of a digital
computer.
Storage is also necessary in the logic section of a
computer. Here another means of storage, known as
"dynamic storage," is directly compatible with the
three-phase pulse-overlap system. Dynamic circuit
techniques are used in the SEAC and DYSEAC computers lO • The method involves the circulation of information around a closed loop, so that a circulating
pulse represents a 1 and no pulse circulating represents a o. In the original circuits using this technique,
the pulse is introduced at one end of a delay line. At
the other end it is amplified, reshaped and clocked
and is then returned to the delay-line input. The
delay-time is adjusted so that the pulse makes one
trip around the loop in one clock period.
Consider the circuit shown in Fig. 8. All blocks
under A are powered by phase A, all under B by
phase B, etc. The block with the arrow represents a
delay gate (one-input OR gate). This takes the place
of the delay-line. Because of the phase relationship
between the three power sources (see Fig. 2), it is
possible to close the loop as shown. The circulation
of a 1 or a 0 is thus made possible. The circuit has
built-in amplification, reshaping and clocking. The
particular circuit shown in Fig. 8 is a basic flip-flop,
there S is the "set to 1" input and R is the "reset to
0" input.
10 D. D. Elbourn and R. P. Witt, "Dynamic Circuit Techniques
Used in Seac and Dyseac," IRE Trans. on Electronic Computers,
pp. 2-9; March 1953.
22
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
input comes from a circuit powered by phase B,
the binary counter is considered powered by phase C
and the ou tpu t goes to a circuit powered by phase A.
EXPERIMENTAL VERIFICATION
In order to investigate the operation of tunnel
diode logic circuits in a small sub-system, one cell of
The basic flip-flop can be included in more com- a simple experimental arithmetic unit was constructed and tested. A block diagram of the cell is
plicated storage circuits. Fig. 9a shows a binary
the fundamental logic circounter and Fig. 10 shows one stage of a shift register. shown in Fig. 11. All of
cuits, including dynamic storage, are evident. The
Other circuits involving dynamic storage techniques
cell contains a storage loop, a full adder and auxiliary
are possible.
read-in and read-out gates for shifting right and left,
complementing the input from memory, and reading
ou t to memory.
Fig. 8-Dynamic flip-flop.
(0)
INPUT
o---1C~~~~lR ~ OUTPUT
(bl
Fig. 9-Dynamic binary counter.
OR
r
I
I
I
I
I
So----r--..,
B
LFIRST
I
STAGE ONLY
o--~~~j----j
LEGEND
CL = CLEAR
R = SHIFT RIGHT - READ SERIAL (NORMAL ORDER)
L = SHIFT LEFT -READ SERIAL (REVERSE ORDER)
P = WRITE PARALLEL
S = WRITE SERIAL
~i ~ ~~~~ALCEI~~~~UT
C~
=TRANSFER OUTPUT
CnR = SERIAL OUTPUT (NORMAL ORDER)
CIL = SERIAL OUTPUT (REVERSE ORDER)
NOTE
C-I
= Cn
Cn + 1 = C1
----4 c INHIBIT INPUT
S ALWAYS ACCOMPANIED BY CL AND R OR L
P ALWAYS ACCOMPANIED BY CL
Fig. lo-Shift register stage.
Note that no time need be lost in obtaining an
output from a dynamic circuit, even though the information stored is in the form of a circulating pulse.
For example, the binary counter of Fig. 9a may be
represented by a single block powered by the appropriate phase, as far as the in~ut and output terminals
are concerned. This is shown in Fig. 9b where the
Fig. ll-Block diagram of experimental unit.
The schematic diagram for the unit is given in
Fig. 12. Fig. 13 contains photos of the complete experimental circuit. The unit contains 27 tunnel
diodes. Resistive coupling is used throughout. It is
powered from a transistorized power supply which
delivers a three-phase, 1-mc, 10-volt square-wave.
This repetition rate was chosen to most easily demonstrate the fundamental principles involved. The inputs to the system are DC levels simulating the output voltages of the tunnel diode (i.e., 0 = 50 mv,
1 = 450 mv), with the correct internal impedance.
Typical waveshapes, taken across one of the diodes
in the storage loop, are shown in Fig. 14. (a) shows a
circulating 1, after the loop has been set and (b) shows
a circulating 0, after the loop has been reset. One can
also make the bit stored in the loop alternate between 0 and 1 as shown in (c). This is accomplished
by making AT = 1, so that the storage loop is cleared
and the SUM output of the full adder is gated into the
loop, by letting Ah = 1, so that one of the inputs to
the adder becomes the bit presently stored in the
loop, and by allowing anyone of the other inputs to
23
Lewin: Negative-Resistance Elements as Components
IK
VB
VB
S
IK
IK
IK
680
~
470
II<
470
Xj+1
Vc
IK
VA
~
6.2K
IK'='
tf
3.6K
160
I
AND
IK
yi-I
IK
-+-OXi
~-J\IV\r __
AND
560
Ar
Fig. l2-Schematic diagram of experimental circuit.
Fig. l3-Front and real' views of experimental cell.
(Tunnel diodes are mounted under finger contacts.)
24
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
the adder to equal 1 (i.e., either Ci or Ac or ti = 1),
so that the sum output becomes the complement of
the bit presently stored. Thus, each cycle the complement of the bit previously stored is read into the
loop and the stored bit alternates as shown.
The peak currents (1 of the tunnel diodes used
in the experimental cell range from 1.9 to 2.6 rna.
The capacity of each diode is of the order of 100,u,uf.
Peak-to-valley current ratios vary between 5 and 8.
The currents from the power supply to each of the
logic circuits were adjusted for proper operation.
Observed switching times (see Fig. 14d and e) are of
the order 50 m,us.
The experiment demonstrateb a number of important facts concerning tunnel diode logic circuits.
First, it demonstrates reliable operation of all fundamental logic circuits in a realistic system. These circuits include OR, AND, THRESHOLD, NOT and EXCLUSIVE-OR. Second, it demonstrates that such circuits
can supply logical gain. For example the OR gate in
the dynamic storage loop has a fan-in of 3 and a fanout of 5. The circuit contains two tunnel diodes in
cascade. Third, it demonstrates agreement between
rough estimates of switching time, based on the time
constant of the device (oapacity time magnitudes of
average negative resistance), and the actual switching
time.
ACKNOWLEDGMENTS
0 )
(a)
(b)
(c)
The author wishes to thank A. W. Lo, G. B.
Herzog, H. S. Sommers, Jr., J. C. Miller and A. G.
Samusenko of RCA Laboratories and Professors
E. J. McCluskey, Jr. and W. H. Surber, Jr. of
Princeton University for many interesting discussions
and helpful suggestions.
This work is part of a larger effort which is summarized in a paper by Dr. Jan Rajchman. l1
ApPENDIX
(d)
(e)
Fig. 14-Typical waveforms. (a) Circulating 1. (b) Circulating O.
(c) Alternating 1 and o. (d) Rise time. (e) Fall time. Time goes
from left to right. Vertical scales are 0.13 v/div with base-line at
bottom. Horizontal scales are 0.5tLs/div for (a), (b) and (c) and
20 m,us/div for (d) and (e).
I. DC power supplies, monostable operation, zero reactance, case II:
The voltage-controlled case will be considered.
Dual treatment can be given to the current-controlled
case. Referring to Fig. lc, in order to insure monostable operation for all R L , one must choose Is and
Rl such that only one intersection occurs for R L = co •
Assuming RL is very large, a particular limiting case
is shown by the solid load-line in Fig. 15. For a given
Is, the negative reciprocal of the slope is R 1max for
monostable operation. Then, for any finite R L, the
load-line changes as shown by the dashed line a. For
a square pulse of input current of magnitude ~i and
width ~t, we have that the energy; input = ~v di ~t,
where these values are depicted graphically in Fig. 15.
11 J. A. Raj ehman, "Solid State Microwave High Speed Computers," Proc. EJCC, this issue.
25
Lewin: Negative-Resistance Elements as Components
I
-Sl..OPE-1"R
siderably larger than that of circuit (2), and in addition, the path followed is no longer horizontal. 12
We wish to compare the recovery times (paths b
and d) of both circuits. Specifically, let us calculate
the time to go from point 1 to point 2 (path d). For
circuit (2) the rise time is approximately 2.2 RoC,
since the voltage follows a simple exponential with
an RoC time constant. For circuit (1), using Laplace
transform techniques, the transform of v is given by
Imax
(1)
v
Assuming that
~=6~1-6~2 S 6~
4
-------2. <
LC (_1__ !!:.)
Fig. I5-Graphical comparison of I:li and I:lV/RL.
I'-'
0.4 ,
(2)
The energy output is I:lv 2I:lt/R L. Thus, we must comRoC
L
pare I:lV/RL to I:li to determine which increment of
energy is greater. These are also found graphically in
which is equivalent to assuming that no oscillations
Fig. 15. An examination of the geometrical construcoccur, one finds that the roots of the characteristic
tions involved shows that if the conditions stated equation are approximately
above are satisfied, I:lV/RL :::; I:li for all R L. Therefore,
energy input? energy output.
R
1
SI = - L - L/Ro - RC
II. DC power supplies with reactance vs. pulse power
(3)
supply:
1
1
Again, the voltage-controlled case will be conS2 = - RoC + L/Ro - RC .
sidered. Comparison is being made between the two
circuits shown in Fig. 16. C is the sum of the stray
capacity plus the capacity inherent in the negative The approximate solution is therefore
resistance device. The path of operation looking into
the parallel combination of C and NR is assumed to
(4)
be approximately the dashed path shown in Fig. 16.
R
where
L
(5)
E
(I.)
(2.)
-I
SLOPE = Ro
An examination of this solution shows that the time
constant of the dominant exponential is always
greater than RoC for values of Land R consistant
with the approximation (2).
Thus circuit (1) has the lower maximum repetition
rate.
DISCUSSION
~(Vlt))= VIS)
Fig. I6-Comparison of monostable and bistable-with-reset
modes. Assumed path of operation.
This will be true, in the case of circuit (1), if L is
sufficiently large. Under these c,onditions, one can
assume that the transition times (paths a and c) are
comparable for the two circuits. If L is not large
enough, the transition time of circuit (1) can be con-
J. H. Felker (AT&T): What speed were you getting on the pulses
you showed and what were the valley and peak points of the negative resistance characteristics?
Mr. Lewin: The transistorized power supply delivered a three-phase
I-me square wave with rise and fall times of about 15 to 20 milliseconds. As I mentioned before, the tunnel diode switching times
(for the units used) were about 50 milliseconds, so that this was the
rise or fall time of the pulses shown. The tunnel diodes used were
early experimental ones with a nominal peak current at around
12 W. J. Cunningham, "Introduction to Non-Linear Analysis",
pp. 106-114; McGraw-Hill, 1958.
26
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
2 milliamps. The peaks varied almost plus or minus 20 per cent. The
valley points also varied such that peak-to-valley ratios were anywhere from about 5 to 8. The diodes could be considered as relatively "low speed" diodes.
R. A. Vaenel (BTL): Which do you consider the speed. limiting
parameters in tunnel diodes? Please distinguish between negative
portion of characteristic and positive portions.
Mr. Lewin: There are two physical processes to consider - tunneling and injection. These can be treated separately. Throughout the
reverse-bias region and well into the forward-bias region, tunneling
is the primary process taking place. This is a majority-carrier phenomenon and is therefore very fast; so that, for example, switching
from low voltage to high voltage ought to be quite good. For sufficient
forward-bias, that is from around the valley region to greater
forward-bias, injection takes over and the V,I characteristic follows
that of a normal forward-biased junction. This region is characterized
by parameters similar to those of any forward-biased junction.
Since the primary phenomenon is now a minority-carrier effect, it
should not be as fast. Note, however, that storage times for the
highly forward-biased tunnel diode can be very short because of the
extremely small lifetime of the stored minority carriers - due to
the very high doping.
The switching times naturally also depend on the external circuit
parameters. For example, in the circuits described here, we are
really interested in switching time from low voltage to high voltage.
The circuit is forced from high back to low by a strong reset signal.
Mr. Vaenel: Do you have available regular diodes to work in conjunction with tunnel diodes?
tics. These tunnel diodes will also be high-speed and, hopefully, lowcost units. Of course, you won't be able to simply pull out a transistor
from a circuit and plug-in a tunnel diode. The transistor is a unilateral device. The tunnel diode is not. I believe, though, that in
many applications, notably in the digital field, one can devise tunnel
diode logic circuits to replace transistor logic circuits and obtain,
for the same cost, a much higher speed.
G. E. Saltus (Bell Telephone Labs.): What was the total power dissipation in your experimental adder?
P. E. Stuckert (1 BM): Can you give an estimate of three-phase drive
power required by those circuits?
Mr. Lewin: The tunnel diodes in the system dissipate a very small
amount of power. Assuming a single 2-milliamp unit always in the
high voltage state when energized, we come l1:P with a power dissipation in the diode of less than half a milliwatt. However. for the system described in this paper, a relatively large amount of power was
dissipated in resistors establishing the current source. For example,
the source used was a 10-volt-peak square wave converted to a current square wave of about 2-milliamp peak. This gives a value of
approximately 10 milliwatts per stage dissipated in the cmrent
source resistor, and this is not necessarily excessive. It is, though, by
far the major power dissipation in the system. Now a source of about
3 volts peak would have been sufficient for a reasonable current
source. This reduces the power dissipated per stage to about 3 mill iwatts. Of course, the power dissipated per stage is directly proportional to the peak current of the tunnel diodes used, so that this could
rise appreciably for higher current tunnel diodes. Note that the
method used is not the only way to get a square wave of current.
For example, one could return the tunnel diodes through a small
capacitor to a triangular wave voltage source. This could also furnish the current square wave but without the relatively high dissipation of real power.
Mr. Lewin: I assume this means conventional diodes for use as coupling elements. This is the most obvious way of unilateralizing the
system - to couple with normal rectifiers so that currents can only
flow in one direction. The trouble one runs into here is that, for
tunnel diodes with sufficiently high peak current value, the forward N. F. Gianola (BTL): Over what ambient temperature range do
impedance of any conventional diode would be so high that, at the your matched diodes maintain sufficiently similar characteristics for
appropriate voltage drop (say 0.4 volts), the coupling diode could use in threshold circuits?
not conduct the desired current increment. In addition, if one were
to use conventional diodes as the only coupling elements, a small Mr. Lewin: This has not been fully determined yet. The part of the
change in this voltage drop would mean a relatively large change in tunnel-diode characteristic that is appreciably temperature dependcurrent increment - due to the nonlinearity of the coupling-diode ent is the injection or high voltage region. This is temperature
forward-characteristic. Since the system relies on fixed current in- sensitive in the same way that any conventional forward-biased diode
crements, this might not be tolerated. It is most advisable to use is sensitive. For a germanium unit at a given current, a typical
conventional diodes in series with resistors as coupling elements. number for the rate of reduction of the voltage in the high state is
Then, the diodes establish directionality while the resistors establish about I mv per degree (centigrade) rise in temperature. Most of the
the current increments. This type of coupling can only be used with tunneling region is essentially temperature independent, so that for
tunnel diodes with sufficiently low-peak current value. For example, some of the threshold circuits described, the threshold would not
in the system described in this paper, since 2 milliamp tunnel diodes change with temperature.
were used, one could easily have coupled with conventional diodes
and series resistors. For much higher current tunnel diodes, this R. Turner (Philco): Please describe your three-phase clock and
method of obtaining it?
may no longer be possible.
Mr. Vaenel: What type of stabiljzing means do you anticipate for Mr. Felker: The other questions have to do with the practicality of
generating high power that would be required in operating a very
high points?
large and complex computer system using these tunnel diodes.
Would you care to comment on the problem of supplying them
Mr. Lewin: I assume that this refers to the uniformity of tunnel having perhaps tens or thousands of tunnel diodes in them?
diode characteristics required. This is one of the main problems. As
you would expect, we require characteristics that are reasonably Mr. Lewin: First, to answer the question on the power supply used.
well-matched. By well-matched, I mean diodes whose essential The outputs were taken from three transistor binary counters, each
parameters are within ten per cent, and preferably five per cent, of driven by a 2-mc input. The clock for the power supply was a 2-mc
nominal values. Now in addition we require something of this order astable multivibrator. One counter was driven directly from this
or better on the power supply parameters. Of course, if we use a clock source. Each of the other two counters was driven by a monosquare-wave generator, this becomes a pretty tough job. However, stable circuit whose input was connected to the clock source. The
this is not the only way to do it. All we require is bistable..with-reset pulse width of the monostable circuit was adjusted to shift or delay
operation. The power requirements for this type of operation can be the output I-mc square wave by the appropriate amount with
furnished in many ways. We could have a well-controlled d-c supply respect to the output of the counter driven directly from the clock.
for the "holding power" unit, to establish the bistable operation, and This resulted in a three-phase square wave. It was simply a cona second reset source to supply the reset signal.
venient method of making the experiment.
N ow turning to future power supplies, this method may not be
L. Thayer (Food Machinery): Do you believe cost and reliability of
tunnel diodes will make them a possible replacement for transistors the best. As I mentioned before, one possibility for obtaining
bistable-with..reset operation is to use a d-c source plus a reset source
in computers?
which delivers a train of negative pulses. These reset pulses are not
Mr. Lewin: I think that eventually tunnel diodes will be fabricated critical with respect to width or amplitude. The magnitude of the
to quite accurate tolerances simply because, in the short time that pulses must only be greater than a certain minimum necessary for
people have been working with them, tremendous advances have reset. If you will recall the tunnel diode V,I characteristic, you see
been made toward realizing high yields of well-matched characteris- that for a larger reset pulse the diode is forced into the reverse-bias
Lewin: Negative-Resistance Elements as Components
region, and this is also a low voltage region so that such operation
is perfectly satisfactory.
Naturally, at the higher speeds we will require higher speed diodes.
At present, fabrication techniques are such that these can most
readily be furnished in large numbers by keeping the area of the
junction the same and just increasing the doping, resulting in a
much higher current diode with approximately the same capacity as
the "low speed" units. A large system would then require many
amperes from the power source, and this becomes a very serious
problem. Now hopefully, as the result of experiments now going on,
we will be able to use much lower current tunnel diodes with reduced area, and thus smaller capacity to obtain the same speed.
That is, by reducing the area of the junction and increasing the
impurity concentrations one can increase the speed of the tunnel
diode without changing its peak current value. Eventually, for
example, we may have a one milliamp tunnel diode which could
switch at the same speed of present 20 rna diodes. This would naturally appreciably reduce the magnitude of the problem of supplying
power to many units:
H. Hellerman (l BM): What sensitivity to noise may be expected
from these circuits, especially ground noise?
V. J. Sjerrino (Lincoln Lab.): Do you envision many problems of
noise triggering with the advent of larger, faster systems?
H. P. Peterson (Lincoln Lab.): Do you anticipate tunnel diodes with
a negative resistance region at higher voltages, like 5-10 volts, to
lessen noise problems?
Mr. Lewin: As far as the noise problem is concerned, I am really not
familiar with the measurements on the tunnel diode noise figures.
I do know that the primary noise source is shot noise associated
with the junction, the shot noise power being proportional to the
junction current. As you noticed on the scope pictures, the little
spikes on the waveforms were due to coupling to the other phases of
the power supply. From the pictures of the experimental set up, you
can see that this was a very crude breadboard 'model and no care
was taken to design for minimum crosstalk, etc. Much more careful
design with a good ground system would be needed at higher speeds.
Preliminary high speed tests in the millimicrosecond range indicate
as you would expect, that a very good ground system is required for
reliable operation. It is too early to more clearly define the design
requirements for very high-speed operation at this time.
To answer the question concerning tunnel diodes with larger voltage swings - work is now going on with materials other than germanium. Since the high voltage region of the tunnel diode characteristic is the same as that of a normal forward-biased junction, the
voltage of the high state depends on the material used. For germanium, this is at about 450 mv, for silicon about 700 mv, for gallium
arsenide about 900 mv, etc. Thus, in the future, tunnel diodes should
be available with various voltage swings. Since this forward voltage
drop must be less than the width of the forbidden gap of the material,
with present technology one cannot expect voltages as high as 5 to
27
10 volts.
G. A. Barnard (Ampex): What have you found to be the current
high-speed switching rates of circuits as those you have shown?
What speeds do you see within five years?
D. Baker (BTL): What is the expected maximum prf for resistive
coupled diode logic circuits? Approximately what value of power
supply regulation is required?
Mr. Lewin: As I mentioned before, the diodes that I used were 2-mapeak-current units with 100-#'#'f capacity, and these switched in about
50 m#,s. Experiments with 20-ma diodes with about the same capacity show switching times of about 4 or 5 m#,s. One can now extrapolate
to the kinds of diodes required for higher speed operation. Obviously,
keeping the same capacity and going to higher currents is not the
best way to achieve this. What we need are much lower capacity
units, and these are currently being developed. I really do not have
enough information to make any useful predictions about the future.
The power supply regulation problem has already been mentioned.
Using a d-c-plus-reset scheme, we would require a d-c source with an
output which did not vary by more than 5 per cent from the nominal
value. A more accurately controlled source would of course be
welcomed.
W. Lawrence (IBM): How does the tunnel diode's capacity vary
from its low to high state?
Mr. Lewin: I believe that the depletion layer capacity variation is
the same as that for any forward-biased abrupt junction. That is,
the capacity increases with forward-voltage. Normally, a value of
capacity is determined by measuring the maximum frequency of
oscillations when the diode is biased in the negative-resistance region.
This gives a value which, to a first approximation, may be attributed
to the whole of the forward-bias region of interest.
P. Smith (General Transistor): Have you done any work on threeterminal negative-resistance devices, and, if so, what speeds of operation were considered?
N. F. Gianola (BTL): Can a third control electrode be added?
Mr. Lewin: You are probably aware of the fact that, at the recent
Washington Electron Device Conference in November, a paper was
presented concerning experiments on replacing the emitter junction
of a transistor with a tunneling junction. I really cannot see how you
would be able to combine the tunneling action, which requires high
conductivity material (implying short lifetime of minority carriers),
with transistor action, which requires long lifetime of minority
carriers in the base region. But of course, I am not an expert on
fabrication of semiconductor components. I do know that work is
going on to consider the possibility of fabricating a three-terminal
device utilizing the tunnel principle. I think such a device would be
extremely useful, but I do not have any quick ideas on how to
make it.
28
' 1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
Deposited Magnetic Films as Logic Elements*
A FRANCKt, G. F. MARETTEt
T
AND
B. 1. PARSEGYANt
HE USE of thin magnetic films as storage elements is well known. Several papers on the subject
have appeared in the literature, particularly in
recent yearsl. Less emphasized, perhaps, is the use of
magnetic films as logic elements. The authors' study
in this area has revealed that film elements are both
flexible and versatile as logic devices.
This paper describes two modes of film-core operation, namely reversible-rotation and saturable-transformer action, as they pertain to a particular circuit.
Also described are certain principles of array logic.
These principles involve writing mUltiple copies of a
word in a film-core array. Then, by the proper
arrangement and selection of sense lines linking parts
of these copies, some desired result is obtained from
the array. This approach makes it possible to perform in one or two clock periods operations that have
previously required many clock periods. The application of magnetic films as logic elements is illustrated
by a scale-factoring device whose function is to find
the most significant digit in a binary word, shift that
word to the left until the most significant digit is in
a position immediately to the right of the position
reserved for the sign bit, and record the number of
places shifted in an auxiliary register. The methods
and advantages of accomplishing these operations
with deposited magnetic film-cores are given in detail
in the paper.
In some of the subsystem designs investigated,
where comparisons between film-element logic and its
conventional counterparts were made, definite reductions in both the required number of semiconductor
components and the operating time were observed.
For instance, throughout all of the designs, the use
of separate NOT elements was easily avoided by
appropriate wiring and biasing of film cores. Use of
separate OR elements may also be eliminated by
appropriate wiring between film elements. This
principle and the component savings it produces are
illustrated by the encoder that is described in this
paper (as part of the scale-factoring device). By
interconnecting film elements to form functional
logic arrays (such as the shift matrix described below),
great gains in speed of entire sequences may often be
realized. These logic advantages - together with
such properties as small size, high reliability, low
power requirements, relative insensitivity to environment, and low cost - make magnetic film elements
very desirable as logic devices.
* This work was carried out under the sponsorship of the Bureau
of Ships, U.S.N.
t Remington Rand Univac, St. Paul, Minn.
1 A list of references on this subject appears in an article by A. J.
Kolk and J. T. Doherty, "Thin Magnetic Films for Computer Applications," Datamation, vol. 5. pp. 8-12; September/October, 1959.
The"O" state of the film core, represented by the
magnetization vector Mo, is made to correspond to
the remanent state of the film core, MR. A bias field,
H B , transverse to Mo, corresponding to the logical
input x, rotates the vector M o throu~h an angle to a
LOGICAL PROPERTIES OF FILM ELEMENTS
This section introduces those logical properties of
film elements that are used in the scale-factoring
device. Specifically, these four ways of using the
logical properties of film elements are described:
a. AND logic using the reversible-rotation mode of
operation;
b. AND logic using the saturable-transformer mode
of operation;
c. Inverter logic using the saturable transformer
mode of operation;
d. Functional array logic.
AND Logic (Reversible-Rotation Mode)
Fig. 1 illustrates a method of obtaining AND logic
using a film element in the reversible-rotation mode
of operation. If inputs to such a film element are x
and y, respectively, then the output is xy, as shown.
DRIVE
FIELD
Ho - - - +
:
INPUT v
l,:"l-
-F-:SENSE LINE
OUTPUT xv
STATE OF FILM UPON
APPLICATION OF BIAS FIELD
•
STATE OF FILM UPON
APPLICATION OF DRIVE FIELD
CASE I
INPUT x= I
v=O
OUTPUT XY=O
Mo (= M R )
CASE 11
INPUT x= I
v=1
HB_
1"1l
OUTPUT xv=1
Fig.
I-AND
V·
i
M
logic (reversible-rotation mode).
Franck, Marette and Parsegyan: Deposited Magnetic Films as Logic Elements
position shown as MI' Subsequent application of a
drive field, H n , corresponding to a logical input y,
in a direction antiparallel to the vector Mo, further
rotates the vector M I, altering the state of the film
core to M'I' (In the reversible rotation mode of operation, application of bias field HB and drive field Hn
is time-sequenced so that the biasing precedes the
driving.) Change of the magnetization of the film
core from state MI to M'I induces a voltage on the
sense line, corresponding to a logical output of "I".
No output is obtained unless both the bias field HB
and the drive field Hn are present, as illustrated by
the vector diagrams in Fig. 1. Logically, then, the
output xy is "I" only if inputs x and yare both "I".
AND
BIAS FIELD HI
INPUT x
SENSE LINE
OUTPUT "NOT x "
DRIVE FIELD Ho
+---He
B
Ho_
------------~----------_H
Logic (Saturable-Transformer Mode)
Fig. 2 illustrates a method of obtaining AND logic
using the film cdre as a saturable transformer. In this
mode of operation, the film core is initially biased to
one of its remanent states of magnetization in the
hard direction. Its state is then caused to change or
not to change in a direction of high permeability,
depending upon certain control conditions.
BIAS FIELD Ha
INPUT x
SENSE LINE
OUTPUT XY
DRIVE FIELD Ho
INPUT Y
Ha_
B
------------~----------~H
NOTE: FILM INITIALLY BIASED
TO P2 STATE
2-AND
NOTE: FILM INITIALLY BIASED
TO PI STATE
Fig. 3-Inverter logic (saturable-transformer mode).
saturable-transformer mode of operation. The film
core shown in the figure is initially biased to the PI
state. (Means of effecting this bias are not shown in
the figure.) A bias field H B , corresponding to logical
input x, biases the film to the P 2 state. Application
of a drive field H n , in a direction opposite to the bias
field, then merely biases the film core toward Pl' It
is, however, not of sufficient strength to drive the
film core into the steep portion of the B-H curve.
Consequently no voltage is induced on the sense
winding; this corresponds to a NOT x logical output.
If, on the other hand, the bias field HB Were absent,
meaning a NOT x input, the film core would remain
in its original biased state at Pl. Application of a
drive field Hn would then induce a voltage on the
sense winding which would correspond to output x.
Functional-Array Logic
HO_
Fig.
29
logic (saturable-transformer mode)
Fig. 2 shows the film core as initially biased to the
P 2 state. (Means of effecting this initial bias are not
shown in the figure.) A bias field H B , corresponding to
logical input x, further biases the film core to state
Pl. Application of a drive field H n , corresponding to
logical input y, then causes a change in the state of the
film core. This change is in the steep region of the
B-H diagram, sO that an output voltage is induced
in the sense line. This voltage corresponds to a
logical output of x AND y. A "I" output is obtained
only if the bias field HB and the drive field Hn are
both present.
Inverter Logic (Saturable-Transformer Mode)
Fig. 3 shows a simple method of obtaining logical
inversion (i.e., negation) using a film CtOre in the
A very powerful feature of magnetic film elements
is their adaptability to a technique of logic described
as functional-array logic. Use of this technique results
in a great saving in time for many operations that
may be sequential in nature. An example of a sequential operation is a shifting operation where the total
time to shift a number is dependent upon the number
of shifts required. The accomplishment of shifting by
functional-array logic is explained in detail in this
paper. In general functional-array logic may be
thought of as an arrangement of information in an
array based upon an input word or bit configuration
for the purpose of accomplishing a specific logical
operation in one step.
In the preceding sections on the saturabletransformer and reversible-rotation modes of operation, the logic of the individual films was presented.
Because of their size, it is possible to assemble these
film elements in compact arrays and to bias and
drive many film elements simultaneously without
appreciable time delays or power losses. One such
arrangement is illustrated in Fig. 4, which is an
30
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
INPUT
BIAS
GENERATORS
HBJ I) ----+
I
o
DRIVERS
I
~
I
/
/
/
I
x
Fig. 4-(a) Film magnetization directions.
example extracted frorn one of the arrays to be
presented in a later section.
The function of this array is to sense for an information bit in a position within the input word. The input
word is contained in the input register R, and each of
the bias generators (Bo-B4) supplies a bias field to the
film element below it if the corresponding inputregister stage (Ro-R4' respectively) contains a "1".
This bias field rotates the magnetic vector to the "I"
position as indicated in Fig. 4(a). If a drive field HD
is applied to a film core thus rotated, an output is
indqced on a sense line linking that film core.
If driver Do is energized after the array is biased,
and there is a "I" in input register-stage R 4 , an output is obtained on the sense-line X. This simple arrangement could be used as a sign test. The other
drivers, DcD4, could also be initiated singly to determine whether input register stagesRa-Ro,respectively,
contain binary "1"s. Another way of using the same
functional array depends on initiating all drivers
simultaneously so that a "0" output indicates that
the input world is all "O"s. Various effects can be
produced with functional arrays by varying the wiring of the sense, drive, and bias lines. Applications of
two of these effects are discussed under "Circuit
Descriptions. "
CIRCUIT FUNCTIONS
The logical operation that will be described to
illustrate the utilization of magnetic film elements is
that of scale factoring of a data word. In certain
number representations this operation is also referred
(b) An example of functional-array logic.
to as "normalizing a number." In both scale factoring and normalizing, a binary word is examined to
determine the location of its most significant information bit. The entire word is shifted until this bit
is in the highest order non-sign position, and the
amount of this shift is stored in an auxiliary register.
If the word is given in a complement representation,
such as one's or two's complement, the operation is
referred to as the process of scale factoring. On the
other hand, if the word is represented in the sign and
magnitude form, the operation is referred to as
normalizing.
For the purposes of this description the one's complement representation is used. It follows that the
leftmost bit of a binary word is the sign bit; "1" for
negative numbers and "0" for positive numbers.
Therefore the most significant information bit is the
leftmost "0" for negative numbers and the leftmost
"1" for positive numbers.
CIRCUIT DESCRIPTIONS
The scale-factoring operation consists of three
separate operations that are first treated separately
in the description that follows and then integrated
into one unit in the last portion. The three operations
and the order in which they are presented are as
follows:
a. Location of highest-order information bit;
b. Shifting;
c. Encoding the amount of shift.
Franck, Marette and Parsegyan: Deposited
Location of Highest-Order I nformation Bit
In conventional logic circuits, the process of determining the location of the highest significant information bit of a binary word is a time-consuming operation ..The method normally used depends on shifting
the bInary word one position at a time in the direction
of most significance. After each shifting operation a
check is made for a difference between the sign bit a~d
the bit occupying the most significant position. If the
bits are alike, the word is shifted again and the check
repeated. The first time that the bits are found to be
unlike, the word is in its proper position. The amount
of shift that has been accomplished is then read from
a counter that has been counting the number of
shifts. The number of sequential steps and therefore
the time for this operation can be large, especially
where the word size is large and the highest order
information bit appears in one of the lower order
positions.
In the preliminary section on functional-array
logic, it was shown that logical operations could be
performed using functional arrays. An array of this
type is illustrated in Fig. 5; its function is to determine the most significant information bit in the word
"00010". The word is arranged in a 5 X 5 bit array
such that one row contains a negative copy of the
word and four rows contain positive copies of the
word. Sense lines SO-S3 are arranged in such a manner
that they couple one bit in the negative row and one
bit in each column to the left of that position. The
figure shows that one and only one sense line may
link bits that are all in the "0" state and that this
sense line has a direct relationship to the location of
the most significant information bit. The sense lines
to the left of this position will always link a bit in the
"I" state because of the negative row, and the sense
lines to the right will always link a bit in the "1"
state because of the column immediately below the
highest-order "0" in the negative row. In the example
of Figure 5, sense line S2 is the only sense line linking
bits that are all in the "0" state. This condition
dictates that a shift of two positions is required to
properly scale the number "00010". If the number
NEGATIVE ROW
I
r
So---eJ 0
o
o
o
o
o
o
Fig. 5--Functional array for determining
most significant information hit.
AIagnetic Films
as Logic Elements
31
had been "OOIXX", it could be shown by similar
~eans th~t sense line S 1 would be the only one linking
bIts all In the zero state, and the corresponding
scaling shift would be one.
A method of implementing this logic with film
elements is illustrated in Fig. 6. The number to be
scaled is located in the input register, stages Ro-R4'
If any stage of the input register contains a binary
"I", it will initiate one of the corresponding bias
generators Bo-B4' The function of the bias generators
is to supply a field transverse to the remanent state
of the films linked by its output line. This field is
represented by vectors HB (1) in Figs. 6(a) and 6(b).
~fter the films. in the array have' been appropriately
bIased by the bIas generators Bo-B4 and B p , the action
of which will be explained later, the film elements are
driven by drive generator D. This driver links all
films in the array and supplies a field that is antiparallel to the remanent state of the film cores but
not of sufficient magnitude to completely switch the
film core with no other applied fields. This field is
identified by vectors HD in Figs. 6(a) and 6(b).
Referring to Fig. 6(a) and 6(b), the effects of the
bias and drive fields are shown for the various rows
of films in the array. A permanent bias field - represented by vector HBP in Fig. 6(a) - is applied to all
film elements in the first or negative row of films
where it is desired that a negative copy of the word
be represented. This field has the effect of rotating
the magnetic state vector away from the remanent
direction of magnetization so that, without the application of another biasing field by one of the bias
generators Bo-B4, an output would be obtained on
sense lines linking these film elements when drive
field HD is applied. If a field is applied by one of the
bias generators, the magnetic state vector is rotated
back into alignment with the remanent direction, so
that no output is produced on sense lines linking these
film elements when drive field HD is applied. Therefore, in the first row, (1) no output is obtained on any
sense line that links a biased film element if there is a
"I" in the corresponding input register, and (2) an
output is obtained if there is a "0" in the input
register. Thus the action of the permanent bias generator Bp produces a negative copy of the input word
in the first row. Examination of Fig. 6(b) for the
remaining rows shows that the converse conditions
apply; i.e., a "0" output is obtained on a sense line
linking a film element associated with a register containing a "0", and a "1" output is obtained on a sense
line linking a film element associated with a register
containing a "1".
The array of Fig. 6 is arranged in the manner
described in the example of Fig. 5. A signal to indicate
the amount of shift required is obtained by the use
of inverters that terminate each sense line. Since only
one ~ense line will have zero signal induced on it, only
one Inverter will have an output signal. Because a zero
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
32
INPUT REGISTER
INFORMATION
PERMANENT BIAS
GENERATOR
H
(I)
~t(0
I
---+
I
Do
(a)
H
B
(I)
o +--
l~HO
02
O:s
(b)
(c)
GATING
SIGNAL
Fig. 6-(a) Film magnetization directions of Row 1 (negative row) for zero bias. (b) Film magnetization directions
zero bias. (c) Network for determining most significant information bit.
or null signal is used to the inverters, the inverters
are necessarily gated as indicated in Fig. 6.
Shifting
For shifting operations, it is also desirable to be
able to shift a word an arbitrary number of positions
in a time not dependent upon the number of positions
shifted. Here again functional arrays are readily
applicable. An array for accomplishing the leftshifting of a word two positions is illustrated in Fig. 7.
As in the example of Fig. 5, the word "00010" is used.
Five copies of the word are represented in the array,
and sense lines are diagonally drawn through the
array as shown in Fig. 7.
Shifting in this array is accomplished by transferring a selected row of bits via the sense lines to the
output register. In the example of Fig. 7, an openended left shift of two is obtained by selecting the
third row and transferring the bits via sense lines
S2, S3, and S4 to the output register. Similarly, other
shifts can be obtained from the same array by selecting other rows. If, for example, row 1 is selected, a
shift of zero is obtained; if row 5 is selected, a shift
of four is obtained.
The circuit of Fig. 8 illustrates a film-element array
OUTPUT
0_
Rows 2-5 for
REGISTER
o
o o
Fig. 7-Functional array for left-shifting a word.
for the execution of left shifts. The word to be shifted
is originally in the input register Rn-R4, and bias generators BoB4 are initiated if there is a "I" in the corresponding input register. The bias generators
supply a field transverse to the remanent magnetization direction. This field rotates the magnetic state
vector in each film element away from the remanent
direction so that a drive pulse applied antiparallel to
33
Franck, Marette and Parsegyan: Deposited Magnetic Films as Logic Elements
INPUT
REGISTER
BIAS
GENERATORS
•
o
I
/
/
I
1
/
(f)
a::
w
>
a::
o
....
LL
:r:
(f)
SENSE
LI NES
OUTPUT
REGISTER
Fig. 8-(a) Film magnetization directions. (b) Network for left-shifting operation.
the remanent direction produces an output on a sense this signal as a binary number. This requires a "oneline linking that film element. The bias field is repre- to-many" translation. An encoder is a device for
sented by vector HB (1) in Fig. 8(a), and the drive field accomplishing this result.
is represented by vector H Dt • To implement a shift
Physically, a signal representing the number is
of from zero to four in this array, one of the shift applied to the encoder input. The output from the
drivers, Do to D 4, respectively, is initiated, and the encoder then appears as one or mor.e signals, correcorresponding row of films is supplied with a" drive or sponding to the respective "I" bits of the binary
interrogation pulse. The sense lines linking the film representation of the given number. For example, the
elements in the interrogated row will have an output number "13" would be encoded as "1101" with
signal only where the film element linked is initially signals from the output of the encoder setting correbiased away from the remanent state. These sense- sponding stages 3, 2 and 0 of a four-bit encoder
line signals are coupled to the stages of the output register.
Fig. 9 shows a three-bit magnetic film encoder with
register and the resulting word is in its shifted
position.
its associated register. Inputs to the encoder are
shown as D I , D 2 , Da and D 4 , corresponding to shift
Encoding
counts of 1, 2, 3 and 4, respectively. (Note that only
In a preceding paragraph the amount of shift was one of these inputs is active at any given time.) The
determined by locating the position of the most output from the encoder appears in the scale-factor
significant bit in a word. This shift count appeared shift-count register, stages K 2 , K 1, Ko. Film elements
as a unique signal on one of the lines Do-Da, as shown Fo, FI and F2 act as AND gates operating in the
in Fig. 6. In many applications it is desirable to store saturable-transformer mode, as described previously.
34
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
SCALE
FACTOR
SHIFT
COUNT
REGISTER
Os r-~~--+-------~--~----~
~
---------'
05 -------------------~
0"~
B.
H
NOTE: ALL FILMS INITIALLY BIASED TO P2 STATE.
Fig. 9-Scale-factor shift-count encoder.
All three film cores are initially biased to the P 2 state.
The input lines are so wired that lines Dl, D2 and D4
link film elements F 0, F 1 and!!, 2, respectively, while
line D3 links both film elements F 0 and F 1. A field
H Di , corresponding to a Di input, biases the film
element (or elements) that it links to the PI state.
The drive generator Ds subsequently supplies a drive
field HDs to all the films. Any film element that is in
the PI state therefore produces an output signal on
its respective sense line. This output then sets the
corresponding scale-factor shift-count register stage
to "1".
In the example used to illustrate the scale-factoring
operation, where the shift count was 2, a field H D2 ,
corresponding to input D 2 , biases the film element Fl
to the PI state. Subsequent application of drive field
HDs then produces an output on the sense line of film
element F 1, and thereby sets scale-factor shift-count
register stage K 1 to "1". Film elements F 0 and F 2 do
not have outputs because their states are unaltered,
having remained at P 2. Consequently, the scale-factor
shift-count register reads "010", which is the binary
representation of 2.
COMBINED CIRCUIT OPERATION
Circuit Operation
Fig. 10 is a composite drawing incorporating the
circuit for determining the highest-order information
bit with the circuit required for shifting. Since both
of these arrays utilize the same mode of operation,
namely, reversible-rotation, it is possible to combine
them in the same array and use the same bias generators. Inspection of Figs. 6 and 8 reveals that certain
film elements in each array are not used in the performance of the logic operation. These unused film
elements are not included in the combined array of
Fig. 10.
The operation of the circuit is divided into two
major sequences: determination of the highest-order
information bit, and the shifting operation, with the
encoding being accomplished during the shifting
operation. After the array has been biased, the first
sequence. is initiated by driver D, which supplies a
drive field to the film elements in the highest-order
information-bit-determination portion of the array.
These film elements are linked by sense lines SI-S4.
These sense lines are coupled to the shift driver
inverters D o-D 3 • Since a zero output on one of the
sense lines is the required signal to the shift driver
inverter, these drivers must necessarily be gated. The
output of drivers Do-D3 is used to drive the film
elements in the shift array and encoding network.
The operation of the shift and encoding circuits is as
described above.
In the example of Fig. 5, a positive number is used
for illustration. If the same approach is applied to a
negative number, i.e., the complement in the first row
and the number itself in the remaining rows, there is
not a unique method of determining the location of
the highest-order information bit. If, however, the
negative number itself is placed in the first row and
its complement, or the positive copy, in the remaining
rows, the previous rules apply. It follows that some
form of gating between the input register stages and
the bias generators is necessary. Similarly, since the
information in the shift array is in its complement
form for negative numbers, some form of gating between the shift array and the output register is
necessary. The conditional complementer circuits
shown within the dotted line enclosures of Fig. 10
accomplish these gating functions.
If the number originally in the input register is
negative, R4 is "1", and the R or negative generator
drives the row of PI saturable-transformer film elements in both conditional-complementer networks.
These PI film elements act as AND inverters (i.e.,
Sheffer-stroke functions) in both networks and complement the information supplied to the bias generators for the array and again recomplement the
information from the array for the proper output
representation. If the number in the input register is
positiv,e, R4 is "0", and the R or positive generator
drives the P 2 row of film elements in the conditionalcomplementer networks. These film elements are
AND gates and allow the information to be transferred
35
Franck, Marette and Parsegyan: Deposited Magnetic Films as Logic Elements
INPUT
REGISTER
-~-
~
P2
I
POSITIVE
GEN
I
P,
; "If .'A~D
r
R
P2 BIASED FILMS
_
L _____ -::
P2
P,
HIt(n
TRIX
M : t L 1ST ROW
-
H~
I
_ _ _ _ _"='_ _ _ _ _ _
"='_ _ _ _ _ _':"_ _ _ _ _ _ =:...J
FILMS
!
FILM DIRECTIONS HD
FOR ZERO BIAS
(/)
0::
Do
W
t-
o::
w
>
~
0,
0::
W
>
~
0
t-
IL
~
r
(/)
0
t-
03
~
TO ENCODER
GATING SIGNAL
Fig. lo-Scale-factor network.
directly to the bias generators and output circuits.
The encoding network shown in Fig. 9 serves in
conjunction with the scale-factoring network of Fig.
10. The outputs of shift driver inverters D 1-D 3, which
drive the shift array, are also used as the inputs to the
encoding network. In this manner the amount of the
shift performed is recorded in the shift count register
at the same time that the shifted number is entered
into the output register.
Circuit Timing
A detailed timing sequence for the scale-factor
operation is presented in Table I. Included in the
table are approximate expressions that might be used
to determine execution times on the basis of word
length and other circuit parameters. The parameters
used are defined as follows:
M = word size in bits
T = transistor rise time
f = film, drive, bias, and sense line transmission
time
R = rise time of film element in saturable
trans~
former mode
From Table I the approximate expression for the
execution time of the scale-factor operation is
max. time = 4T
+ (4M + 5)1 + 2R
Assuming a transistor rise time T = 5 m#-,sec, filmelement transmission time 1 = 0.12 m#-,sec, filmelement rise time R = 1 m#-,sec, and a word size
M = 36 bits, the maximum shift time for the scalefactor operation would be 39.9 m#-,sec.
Circuit Components
The components required for the scale-factor operation, exclusive of the component requirements for the
design of the input register and the encoder, are as
follows:
36
1959 PROCEEDINGS OF THE EASTERN JOINT COMPVTER"VONFERENCE
TABLE I
SCALE-FACTOR TIMING SEQUENCE
Initiate Scale Factor Operation
Test sign
+
Locate Most Significant Bit
Store Shifted Word
,-
(Negligible)
Encoding
-
I
Initiate R
Initiate R
Generator (T) Generator (T)
Transmission time
(Mf) Initiate input transfer
Conditional complementer
Drive transmission time
Film element rise time
(2f)
(R)
Initiate bias generators
(T)
Bias transmission time (Mf
+ f)
(T)
Initiate scale-factor driver
Drive- and sense-transmission
(Mf)
time
(T)
Initiate inverter driver
Drive- and sense-transmission
Encoder bias transmission time
(Mf)
(maximum)
(Mf)
time
Amplifier
(T) Initiate read driver
Conditional complementer
Drive transmission time
FHm-element rise time
(2f)
(R)
1. Film elements
Input = 2M
Output = 2M
Matrix = M2 + M - 2
Total = M2
+ 5M -
2
2. Transistors
Bias Generators = M + 1
Inverter Drivers = M - 1
R & R Generators = 2
Amplifiers = M
Total
=
3M
+2
Table II presents the film-element and transistor
requirements for encoders of various sizes. For comparison purposes, the number of diodes that would be
required for conventional encoders of equivalent size
are shown. The input and output components are
omitted for both types of encoders.
Since film elements, unlike diode elements, permit
the use of more than one input per element, the filmelement encoder uses very few film-elements in comparison with the number of diodes in a diode encoder.
Furthermore, the only semiconductor devices required are one transistor for each output bit. The
number of diodes required for the larger diode
encoders would be greater because of the diode OR
(T)
Drive and sense transmission
circuit input limitation. For these encoders the
diodes would probably be arranged in a "tree" or
"pyramid" configuration, which would result in an
increased time requirement for the diode encoder.
Without the "pyramid" arrangement, the times for
the two encoders are approximately equal.
TABLE II
ENCODER COMPONENT REQUIREMENTS
Output
Word Size
(In Bits)
2
3
4
5
6
Film-Element Encoders
Diode Encoders
Film Elements
Required
Sensing
Transistors
Required
Diodes
Required
2
3
8
20
48
2
3
4
5
6
4
12
32
80
192
OTHER ApPLICATIONS
The illustration given in this paper utilizes a fivebit word in the one's complement number representation. The method applied, however, is not restricted
to this representation, this word size or the particular
application which has been described. With minor
modifications the device can be adapted to any
complement, sign and magnitude, or binary-coded
number representation. Devices to perform such
Franck, Marette and Parsegyan: Deposited Magnetic Films as Logic Elements
operations as locating the least significant information digit and shifting the word accordingly, or
locating a predetermined information digit within a
certain field or portion of a word can also be readily
designed.
Although this paper is concerned primarily with
the application of film-element logic and the design
of a specific logical device, the techniques described
have a much wider range of applicability. The authors
have investigated and designed a variety of logical
devices such as decoders, counters, accumulators,
and special-purpose devices.
ACKNOWLEDGMENT
For consultation on the physical properties of
magnetic film elements, the authors are indebted to
members of the Physics Department of Remington
Rand Univac (St. Paul), especially Dr. A. V. Pohm 2
and Dr. R. M. Sanders.
DISCUSSION
H. Aiken: I wonder if you would discuss a couple of points for me.
One, your primary approach to the logics was with the aid of the
matrix, so I am wondering what you have done to minimize the
number of elements, making further use of Boolean for this purpose.
And the second comment you can answer yes or no, have you any
attempt so far to build whole circuits with this technique in one fell
swoop to set up a standard?
Mr. Franck: As to the first question, no attempt was made to phrase
the logic in such Boolean form as to use minimization techniques. In
general, a'S can be noted for the device discussed, which uses the film
elements quite efficiently, these techniques would probably offer little
if any results in the way of reducing the number of components.
37
In respect to the second question, a design for a shifting matrix is
actually working. For obvious reasons, I cannot say too much about
it. In your sense of one fell swoop, one can say it essentially was so
done, i.e., a single evaporation placed films on a substrate, then
printed-wiring techniques were used for the wiring arrangement.
P. D. Goodman (Clevite Transistor): What switching speed can be
obtained with these devices? What current and voltage are required
for switching? How large is each element?
Mr. Franck: I might point out I am not trained as an electrical engineer but as a mathematician and obtained this type of information
from appropriate sources. I can give estimates. For full switching, the
speed is 250 millimicroseconds, whereas for rotational switching, it is
3 to 30 millimicroseconds. Input voltages of 10 volts and currents of
200 milliamperes have been used in the design of the shift array.
Typical sizes for the element range from 1 millimeter for circular
elements to 1 Y2 by 5 millimeters for rectangular elements. Output
voltages of 4 millivolts per turn have been measured for the shift
array.
G. A. Sellers (Bell Labs.): Please describe the physical characteristics
of a "thin film": size, etc., and how they are fabricated?
Mr. Franck: I am not sure whether you mean actual dimensions. I
think I have described this as essentially one millimeter. The thickness is 1 to 200 angstroms. Typical dimensions of films range from
1 to 4 millimeters. A few of 8 millimeter size have been used in experiments. The films have been deposited on thin cover-skip glass. Both
6-mil and 9-mil glass have been used. The methods of fabrication are
described in an article in the Physical Review by C. D. Olson and
A. V. Pohm.
R. Turner (Philco): What sort of switching speed is realized?
Mr. Franck: The speed for rotational switching is as fast as 3 millimicroseconds. For full switching, a qUluter microsecond is typical.
J. Jacoby (BTL): How are the leads, drive and sensing leads, physically associated with films?
Mr. Franck: Printed wire techniques are used.
L. Mintzer (Honeywell-DAT Amatic): Since these are passive elements,
the number of sense amplifiers is not negligible. Approximately how
many active elements in sense amplifiers?
Mr. Franck: In the shift array which has been designed, three
Now on the staff of the Department of Electrical Engineering, transistors have been used on the output of a given sense line for
Iowa State University, Ames, Iowa.
amplification.
2
1959 PROCEEDINGS OF TRJ!J EASTERN JOINT COMPUTER CONFERENCE
38
Solid-State Microwave High Speed Computers
JAN A. RAJCHMANt
PUMP(2fl
INTRODUCTION
(0)
T
HIS PAPER presents results of an effort aimed
at developing the principles and technology required to speed the rate of computers up to the
order of a thousand megacycles. The approach is
based on the use of two types of two-terminal semiconductor devices: the variable-capacity diode and
the tunnel diode, in combination with microwave
techniques for the couplings within the computer.
Both devices provide amplification of binary
signals by mechanisms depending on negative resistance. Their speed limitation is primarily due to
the capacity of the junction and internal series resistance and can be two orders of magnitude higher
than that of transistors which are limited by the
travel time of minority carriers. The variable-capacity diode can be used for computer logic in parametric
phase-locked oscillators according to concepts* described by Goto 1 and Von Neumann2 • The negative
resistance of the tunnel diode can provide amplification and gain directly. Both devices have only two
terminals, i.e. a single port for the input and output,
so that special methods are required to give direction
to information flow. These methods and the means
to perform the other necessary functions of storing
and gating signals are described in the following
sections.
PARAMETRIC PHASE-LOCKED SUB-HARMONIC
OSCILLATOR (PLO) COMPUTERS
Principle of Operation
Consider a tuned circuit composed of a fixed inductance and a capacity whose value depends on the
voltage across it (i.e. junction diode). Let the tuned
circuit be excited by a frequency 2f which is approximately equal to twice the resonant frequency of the
circuit. (Fig. 1) This excitation will tend to produce
oscillations at frequency f in the circuit, and oscillations will actually be sustained if the excitation is
sufficiently intense and the losses in the circuit are
sufficiently small. This effect is a special "degenerate"
case of a broad class of parametric excitation effects.
t R.C.A. Laboratories, Princeton, N. J.
(bl
-
gOUTPUT(fl
W
f\ 1\
1\
-- VVVVVVV\)
1\ 1\ 1\ "
(e)
iff
I
1\
~-"'=~~"t?---¥-----¥--I--I----l----J----I-""';' OUTPUT
lJ
Fig. I-Principle of parametric phase-locked oscillator.
The general theories of parametric oscillations, as
well as the particular theory of this degenerate case
have been reported by several authors3 ,4,5,6,7.
The reason for the build-up of oscillations can
readily be understood by a simple physical reasoning.
Let us assume that every time at which the capacity
has maximum charge, the value of the capacity is
reduced, as would be the case if the plates were pulled
apart. The work necessary to reduce the capacity
increases the energy stored in the condenser. The
value of the capacity is restored to its initial value
at the instant when the charge in the condenser is
zero. In this way a certain amount of energy is added
to the circuits at every half-cycle of the oscillation.
If this increase of energy is greater than the loss of
energy in the half-cycle due to damping in the circuit,
the amplitude of oscillations will grow. rt is easy to
see that this "pumping" of energy occurs at twice
the frequency of oscillations and therefore can sustain
an oscillation of either of two opposite phases. In the
actual case of a variable capacity diode, the change
of capacity is due to the voltage of the pump source
3 J. J. Stocker, "Nonlinear Vibrations in Mechanical and Electrical
Systems," Interscience Publishers, Inc., New York, 1950.
4 W. J. Cunningham, "Nonlinear Analysis," McGraw-Hill, New
York.
Ii K. L. Kotzebue, "A Semiconductor-Diode Parametric Amplifier
* R. L. Wigington, "A New Concept in Computing," Proc. IRE, at Microwave Frequencies," Stanf(ffd Electronic Laboratories TechVol. 47 - No.4, pp. 516-523, April 1959. (An account of J. von nical Report, No. 49, Nov. 1958.
Neumann ideas in footnote 2).
6 A. Uhlir, Jr., "The Potential of Semiconductor Diodes in High
1 Eichii Goto, "On the Application of Parametrically Excited NonFrequency Communications," Proc. IRE, Vol. 46, pp. 1099-1115.
linear Resonator," Denki Tsushin Gakkai-shi, Oct. 1955.
June 1958.
2 J. von Neumann "Nonlinear Capacitance or Inductance Switch7 J. M. Manley and R. E. Rowe, "Some General Properties of
ing, Amplifying, and Memory Organs," U. S. Patent 2,815,477, Dec. Nonlinear Elements - Part 1 - General Energy Relations," Proc.
IRE, Vol. 44, p. 904-913, July 1956.
3, 1957, assigned to IBM.
39
Rajchman: Solid-State Microwave High Speed Computers
applied to it instead of the mechanical work necessary
to pull the plates apart, but the effect is analogous.
The oscillations are sustained in either of two opposite phases which are locked to the phase of the
pump and can b e used to d eno t e " zero " and" one "
of a binary digit. The phase-locked-oscillator, PLO,
constitutes thus a storage cell. The steady-st~te
phase depends on the conditions under which oscillations start. If a small locking signal at the frequency
f is present in the tank, oscillations will build up in
the phase closest to the phase of the locking signal.
The input locking signal is thus "amplified." (Fig. 1.)
Logic can be performed by arraying the PLO'S in
three or more groups, which are separately activated
either by pump modulation or diode bias gating.
Every PLO is loosely coupled to PLO'S in other groups,
the pattern of couplings determining the logic task to
be performed. The groups are clocked in succession
with some overlap, i.e., a given clock is turned off after
the next one is turned on. This sequence causes information to flow in a given direction despite the
bilateral character of the PLO. A PLO will start at the
phase determined by the phase of the major~ty. of
oscillating PLO'S to which it is 30upled. The maJonty
decision can be exploited directly in many circuits
or can be reduced to "and" or "or" decisions by the
use of a reference signal on one input. For example,
with two inputs, and a reference in phase zero, the
output will be in phase 71" only when both inputs ~re
in phase 71". Negation is easily obtained by phase Inversion. In a typical example of logic circuit, Fig. 2,
each PLO may be connected to two inputs, two outputs and one reference, or to five other PLO'S. Consequently the input is at most one fifth of the output
of preceding PLO'S. Thus, a minimum "logic gain" of
five is required. In a simple shift register, Fig. 3,
minimum logic gain is two.
There is a certain increase of amplitude of oscillation at each cycle, which depends on the parametric
pumping, i.e., specific variation of capacity and power,
and on the losses of the circuit which are made up of
the useful loading and unavoidable circuit dissipations. To build up the amplitude by a factor
corresponding to practical logic gains, about 5 cycles
of oscillations or 10 pump cycles are required in
typical PLO'S. Therefore to obtain 1000 mc. informa-
)~
[
"6':
R
I
7
REFERENCE
PHASE
][
Fig. 2-PLO general logic.
m
w
Fig. 3-Shift register with three-phase pump system.
tion rates, i.e., phase switching in about 3 x 10-10 sec.,
pump frequencies of about 30 KMC or higher are
required.
Experimental Results
An experimental program ultimately aimed at
PLO computers pumped at frequencies of about 30
KMC resulted in the following:
A . Microwave Sub- Harmonic Oscillators
Microwave circuits obtained by photographic engraving of copper-clad insulating boards. k~own ~s
strip transmission lines, and point-contact dIOdes In
conventional microwave cartridges, were used for
PLO'S pumped at 4 KMC. A typical early configuration (Figs. 4 and 5) included: a 2 KMC quarter-wave
resonator with diode in shunt at one end, a 4 KMC
resonator bar isolating pump and oscillating circuit,
d-c return for optimum bias, and one or more loosely
coupled inputs and outputS. 8 ,9,IO,l1,12 Output-vs-input
power characteristics (Fig. 6) show broad operating
range, efficiencies of a few percent, and required pump
power levels of about 100 mw. Typical more recent
configurations utilize a series connected-gold-bonded
diode (Fig. 7) and multiple impedance-matched
antennas for coupling inputs and outputs. The characteristics (Fig. 8) show uniform couplings to various '
antennas, and broad operating regions.
8 W. R. Beam, D. J. Blattner and F. Sterzer, "Microwave Carrier
Techniques for High Speed Digital Comp';!ting," (Symposium on
Microwave Techniques for Computers, Washington, D. C., March 12,
1959) Trans. IRE on Electronic Computers, Sept. 1959.
9 F. Sterzer and D. Blattner, "Fast Microwave Logic Circuits,"
Proc. IRE National Convention, March 1959; also Proc. EJCC, Dec.
'3-5, 1958.
. .
.
10 F. Sterzer, "Microwave ParametrIc Sub-HarmOnIC OscIllatosr
for Digital Computing," Proc. IRE, July 1959.
11 F. Sterzer "RF Circuits Using Sub-Harmonic Oscillators,"
Proc. PGMIT National Symposium, Harvard University, Cambridge,
Mass., June 1959.
12 F. Sterzer and W. R. Beam, "Parametric Sub-Harmonic Oscillators," Digest of Technical Papers, Solid-State Circuits Conference,
Philadelphia, Pa., Feb. 1959.
40
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
DIELECTRIC
CRYSTAL DIODE
(MOUNTED ON OPPOSITE SIDE)
......
-W.r'r-+-~+-IN#r- OUTPUTS
Fig. 16--Tunnel diode bistable logic element
(single diode type).
PULSE
OR
~
OUTPUTS
AC
Fig. 17-Tunnel diode bistable logic element (symmetric type).
IN P U_T.JVIIII'v--<~MIIr-..:...:OUTPUT
v
Fig. I8-Tunnel diode monostable logic element.
with. a resistanc~ ?r resistance network (Fig. 16);
(2) bIstable, conSIstIng of two tunnel diodes in series
(Fig. 17) ; (3) monostable, using diodes in series with
inductances (Fig. 18).
(1) In the first bistable logic element, the single
port P is coupled resistively to a number of inputs
and outputs as well as to a source of current Is which
can be pulsed (Fig. 16). In the absence of Is the contributions of currents to the diode are so small that
its voltage is small on the "0" part of the chara,cteristic. The value of Is is so chosen that when the
activating pulse is applied, the total current will
either be smaller of greater than the maximum I
depending on the sum of the inputs, and therefore th~
voltage will remain small or will be switched abruptly
to the "1" part of the characteristic. This change of
voltage influences in turn other logic elements to
which it is coupled when these are activated. The
logic elements are in three or more groups which are
clocked by overlapping pulses, in a manner similar
to the PLO clocking. An experimental unit IS has been
made to demonstrate this type of logic. It contains a
storage l?op, a f.ull adder stage, means to shift right
~nd le~t Into regIsters, and other functions, including
InverSIOn. The unit contains 27 tunnel diodes with
18 M. H. Lewin, "Negative-Resistance Elements as DigitalComputer Components" (included in tbis volume of Proc. EJCC).
44
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
peak currents of 2 mao Observed switching times with
these early, relatively slow diodes were about 50
nanoseconds. The unit was driven by a three-phase
clock at 1 megacycle.
An alternative to the pulsed power supply for
energizing the bistable elements is the use of a DC
supply and resetting pulses. Any element of the network is set to state "I" directly according to the combined outputs of preceeding elements and is reset to
state "0" by a clocking pulse. Setting of the elements
of a group occurs immediately following resetting.
(2) In the second bistable type, the logic element
is made of two tunnel diodes in series (Fig. 17). To
these diodes is applied a voltage from an a.c. source,
(pulsed or sine-wave) of an amplitude sufficient for
one diode to be in the "I" state but insufficient for
both to be in that state. The polarity of a relatively
small input voltage applied to the mid-point is sufficient to determine which diode will trigger. This
triggering will cause a greater voltage swing of the
same polarity at that point and in effect will amplify
the input signal. Logic networks can be obtained by
arranging the logic elements in three or more groups
and resistively coupling the midpoints of the elements
of different groups. The pattern of connections determines the desired logic operations. The groups are
energized in succession by overlapping voltage waves
in a manner similar to the clocking of the PLO'S. A
particularly simple system is the use of a 3-phase
sine-wave power supply. Negation is obtained by inverting transformers. Practical obtainable logic gains
depend on matching of diodes in pairs rather than
general uniformity of diodes as in the single-diode
logic elements.
(3) Monostable logic elements are obtained with
a tunnel diode in series with an inductance biased to
a point P near the maximum of the characteristic
(Fig. 18). A relatively small voltage can trigger the
diode to the high state and thereby produce a relatively high voltage swing at the same point. Logic
networks can be obtained by resistive couplings between logic elements in a manner similar to bistable
elements. Resetting to the low state is produced automatically by the voltage induced in the inductance.
Asynchronous operation can thus be obtained. In an
experimental 7-stage delay chain, very uniform successive triggering was observed. Synchronous operation is possible also, by superimposing clocking pulses
on the inputs; but it appears that higher speeds are
realizable for a given logic gain in bistable circuits in
that mode of operation.
All three types of circuits utilize logic elements in
which the inputs and outputs are on the same single
terminal. To insure separation of input and output
functions, i.e., direction of information flow, several
methods are possible. In the above-described systems,
separation in time was used by multiple-phase
clocking, the inputs at anyone logic elements being
effective at a different time than the outputs. Directionality by electrical separation can be obtained
through the use of unidirectional couplings. Unfortunately, adequate rectifying diodes of speed comparable to that of the tunnel diodes are not available
at the present time. Directionality can be achieved
also by making the level of energy of successive logic
elements in a chain or the couplings between them
progressively weaker so as to insure that the setting
influence of the inputs dominates over the backflow
influence of the outputs.
The multiple-phase clocking is a simple solution
to the directionality problem and the key to the successful use of single-port two-terminal devices. An increase of speed can be realized if several logic steps
instead of a single one are made at each clock pulse.
This is possible by using a cascaded arrangement of
logic elements driving each other asynchronously. In
these circuits, means for directionality of information
flow other than clocking must be provided.
From the above considerations, it is evident that
simple logic circuits of complete generality can be
made from tunnel diodes~ The signals are direct pulses
and require no carrier. Energization can be either by
multiphase sine wave or pulsed ac or by a combination of dc and clocking pulses. Experimental circuits
have demonstrated general system flexibility. The
speed of the circuit can be very high. With early,
relatively slow experimental diodes having 2 ma
peaks, one-megacycle repetition rates were demonstrated; but switching times were short enough to
permit 10 megacycle rates. With newer, faster 20 ma
units, logic elements were switched in times permitting 100 megacycle rates. The speed capabilities of
tunnel diodes are still being increased dramatically
so that there is great promise for realizing logic circuits with 1000 megacycle rates.
Tunnel-Diode Memory
Random-access memories can be made using arrays
of tunnel diodes and promise to be very fast. Each
bit is stored by a current-driven tunnel diode having
two stable voltages (Fig. 19). Rowand column are
resistively coupled to each diode (Fig. 20). Any
selected diode can be set to one or the other state by
voltage pulses, of appropriate polarity and amplitude,
on the corresponding buses. The memory can be
organized for coincident-bit addressing requiring twoto-one selection discrimination or for word addressing
needing only three-to-one discrimination. The maxima and the minima of the characteristics provide
the necessary thresholds and are sufficiently uniform
to make possible either of these coincident write-in
systems.
Read-out is obtained by driving the selected element or elements to the high state "I" and observing
whether or not switching results. In a second following writing cycle the elements which have changed
Rajchman: Solid-State Microwave High Speed Computers
HOLD VOLTAGE
v
Fig. 19-Current coincident write-in.
Fig. 2Q--Tunnel diode memory array.
y
Fig. 21-Read out by sensing ringing.
state are restored by appropriate control of the writing circuits in a manner analogous to that used in
conventional core memories. The read-out signal can
be obtained by direct pick-up from a common circuit
resistively coupled to all elements. Read-out can be
obtained also through inductive or radiative pick-up
of high frequency which can be generated by the
selected diode in several ways. A resonant circuit,
which may be a simple stub at microwave frequencies,
is associated with each element. In one method, to
read, a write "0" is applied to the selected element
and thereby switches it or not. If there is switching
the relatively large voltage excursion through the
negative region of the characteristic shock excites the
tuned circuit and the resulting natural-frequency
oscillation is sensed on a circuit loosely coupled to all
elements (Fig. 21). In another method, selective
readout-addressing circuits impress signals at frequency 11 on the selected row bus and 12 on the
selected column bus. In the high state the curvature
of the voltage-current characteristic is about 4 times
greater than in the low state, producing a corresponding ratio c..! amplitudes of the beat-frequency 11 - 12
to which the elemental circuits are tuned.
Experiments with small arrays and array skeletons
have demonstrated (1) two-to-one coincident write-in
45
with reasonable tolerances of operation despite the
use of experimental diodes with relatively wide variations of characteristics. (2) adequate discrimination
direct read-out pulse signals with word addressing.
(3) inductive read-out signals of high discrimination
with ringing frequencies as high as 250 mc and beatfrequency of about 1 kmc with bit-coincident
addressing.
Drivers of tunnel-diode arrays must be able to supply pulses of relatively large power. The required
current is large because all parallel-connected halfselected elements load the selected lines, and the required voltage is large because the voltage of the
series current-regulating resistance must be several
times greater than the voltage swing of the diode.
Typically, hundreds of milliamperes and several volts
must be provided. It is unlikely that transistors will
be adequate to drive large arrays at high speed (although a line of an array was driven in less than 10- 8
sec.). The best promise for solving the driver problem
lies in the tunnel diode itself. Sufficient voltage can
be obtained by conne.cting a number of tunnel diodes
in series, and adequate current may be obtained by
using sufficiently high-current units. Such arrangements have been operated and appear adequate.
Tunnel-diode random-access Inemories offer at the
presen t time good promise and possibly the only
promise of achieving the cycle-time of 10- 8 seconds
necessary in a memory associated with 1000 megacycle rate logic: the tunnel diodes themselves are or
soon will be fast enough, and there does not seem to
be any insurmountable system problem. Experiments
to date have demonstrated the essential write-in and
read-out steps, and have indicated a solution for the
drivers. Furthermore, it appears that propagation
delays along addressing lines can be kept low enough
so as to be insignificant. This results chiefly from the
small size of the diode and of the resulting array.
CONCLUSIONS
Computer logic by microwave-carrier techniques
and the junction diode PLO has been demonstrated in
elementary subsystems operating at one hundred
megacycles, with single elements switching in times
corresponding to 300 megacycles. Microencapsulated
improved diodes promise to provide thousand megacycle rates with power supplied at 30 KMC or higher.
Computer logic by tunnel diodes, already demonstrated at low rates, promises to be possible at a
thousand megacycles. Sufficiently uniform diodes and
diodes capable of fractional nanesecond switching
have been made. Random-access memories with cycle
times of the order of 10 nanoseconds appear possible
using arrays of tunnel diodes. Tunnel-diode computers operate with direct pulses aI).d are powered
by DC, or AC at signal frequency, or both.
Two-terminal semiconductor devices thus provide
46
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
the manipulative elements required to gate, store,
and amplify binary signals in nanoseconds. Furthermore, simplicity, small size, and power dissipation
per element of tens of milliwatts permit packing of
10 or more elements per cubic inch. Therefore, reasonably comprehensive computers with several thousand logic elements and several tens of thousands of
memory elements can be made in a volume less than
two feet in diameter. 'Unavoidable delays due to signal propagation, of about Ys to V6 nanosecond per
inch in normal transmission lines, are thus kept at
about one nanosecond. This presents no serious difficulty in a "thousand megacycle" machine which can
be assumed to have elementary logic functions executed in about one nanosecond and a memory cycle
time of 10 nanoseconds.
We can, therefore, look forward to a new era of
billion-bit-per-second information-handling machines
which are likely to produce as large, if not larger, an
impact on the information processing art as was produced a decade ago by the introduction of present
million-bit-per-second machines.
ACKNOWLEDGMENTS
The work reported in this paper is the result of the
joint efforts of a number of scientists and engineers
of the Radio Corporation of America in its Laboratories, Electronic Data Processing, Tubes and SemiConductor and Materials Divisions. The author has
attempted to present a summary of their ideas and
experimental results. Detailed papers by various
authors have been published already and others are
following. The work was supported by government
contract NObsr-77523.
DISCUSSION
H. Aiken: I wonder if you would answer a question or two for me. I
was very much struck with your comment that you are now thinking
about weighted logics. This is a subject that would have enormous
implications all over the computer field. Would you say a few more
words about this subject for us?
Mr. Rajchman: We have under this project a study as to what we
could gain in a general way by weighted logic. This study at the
moment is incomplete, so I can't draw conclusions, other than the
fact that it isn't obvious whether all logical functions can be performed with the same amount of weighting and we are studying
which can and cannot be produced that way. There is also the
practical aspect of the problem that you don't want to have two
weights different from one another, because you introduce the
problem of accuracy of control. Since I have the microphone, I
should have mentioned that I was merely a spokesman for a large
project that RCA has, in which many divisions contributed; also
that many of the results have been reported in detail already, and
others will be reported in journals; also that the project was supported
by the Navy Bureau of Ships.
E. C. Johnson (Bendix): Would you summarize the relative potentials
of parametric diodes and tunnel diodes for high-speed logic?
Mr. Rajchman: I wish, and so do other people in our organization
that we had a completely clear answer to this. The fact of the matter
at the moment is that we have attained a higher logic-gain-speed
product with the variable-capacity diode than the tunnel-diode approach. On the other hand, the tunnel-diode approach is simpler in
actual organization; also, the rate at which we are making progress
in the field is very much higher than the rate we are making in the
other. So at the moment we just cannot answer the question fully.
This is as close as I can put it.
S. Rogers (Convair): Would you comment on the problem caused by
phase shifts in leads interconnecting microwave parametric logical
elements?
Mr. Rajchman: This, of course, is an important design consideration,
and circuits must be designed with the precise geometric location of
the elements fully marked, and must be put at distances such as to
correspond to the right fraction of the wave length or as artifices have
been produced to make them shorter, as the case may be.
J. Ronnally (Philco): Has asynchronous logic any hope with new
tunnel devices?
Mr. Rajchman: Yes, I believe this is possible. I didn't have time to go
into this, but it is possible to have several sets of logic performed by
tunnel diodes synchronously between clock pulses. In other words,
the clock pulses could in effect be slower than the elementary logical
calibration within the computer. I don't believe, I may be wrong,
that a complete synchronization would be practical. I believe the
composite system is more practical.
J.A.Githens (BTL): Please compare potentials of the two devices for
high-speed logic.
Mr. Rajchman: I am afraid I can't say any more.
S. Cohen (Raytheon): How critical is the phase stability of the pump
for the PLO?
Mr. Rajchman: It is, of course, critical; but I don't think there is any
practical difficulty in maintaining the phase.
V. J. Sferrino (Lincoln Lab.): Is there a parallel effort to develop
solid-state microwave power supplies?
Mr. Rajchman: I don't have any in that direction although we have
made some experiments trying to use the same tunnel diode as a
power supply for the phase oscillator. We have also made some circuits that are double, take two parts of power supply and then use
semiconductors to double.
Mr.Sferrino: What degree of difficulty do you envision in thedistribution of this power in a large system, regarding noise and time delay?
Mr. Rajchman: This, of course, is a very important aspect of the
high-speed computer. One thing has to be designed very carefully.
Light or electrical signals travel on the order of eight or seven inches
per millimicrosecond and if we deal with this, delays are important.
There are two broad ways to handle the problem. One, to make distributive devices such as the phase oscillator and take delay in your
stride as you plan the design in the first place; the other approach is
to make devices so very small as to make the delay negligible, hopefully. In the tunnel-diode, the second approach seems to be the more
opportune one. The actual solving of this fully I think has to await
the actual engineering of such a machine. I don't think one can solve
this problem without stopping to make one, and one has to make
the elemental functions themselves before one sees the problems in
assembling many of them into units.
D. R. Erb (/nstron Eng.): How is the eoincident-current memory reset?
Is it always destructive or is it possible to have non-destructive
read-out?
T.R.Finch (BTL): You and Mr. Lewin have mentioned low cost possibility of tunnel-diodes. What cost figures are you thinking of, and
what precision of control of parameters such as peak and valley
constants?
Mr. Rajchman: There is no problem. By coincident writing one can
bring the elements from the low state to the high, or high to low
state, depending on the linkage being positive or negative. One has
to resort to the usual rewriting scheme customarily employed in
memories.
Mr. Rajchman: This is always an embarrassing question when one
asks a research man who is optimistic by nature. The tunnel-diodes
are manufactured by two large companies in this country and cost
from $50 to $100 apiece, so that at the moment this isn't inexpensive.
On the other hand, the fundamental element it is made from is very
Rajchman: Solid-State Microwave High Speed Computers
simple and the processing control required to maintain the properties
is relatively simple, say to the making of a transistor. So I don't see
fundamentally why the device couldn't be made very simply. Now I
am not a production man, so I really can't say how to translate this
into dollars and cents but I wish I could, especially the latter!
47
techniques. The main difficulty is that after you obtain on a small
curve of 1 mil or less it is very low resistance. So we have tried many
techniques. I believe we have tried etching, but if you ask that
question specially, I am not sure.
R. Turner (Philco): What do you conceive as a phase detector, say
at 1000 mcs, to interpret phase-sensed outputs?
V. Vulcan (General Transistor): How do you prevent shunt loading of the tunnel-diode and consequent shift of its V-I characteristic in the direction of lower peak-to-valley current ratio?
Mr. Rajchman: I think this can be done by simply comparing this
with a continuous wave in amplitude modulation as shown in one of
the slides. If you wish to obtain a signal or pulse from this, you can
rectify it and feed it to other circuits. I will say that the general
problem of matching high-speed cricuitry to low-speed input-output
we have not looked into in great detail. Our aim was to find out
whether or not it was possible to operate at these rates, no matter
what the cost, and no matter what other problems were brought about.
Mr. Rajchman: If I understood the question correctly, the question
is whether the shunting due to the capacity of the diode presents a
certain shifting. The main penalty you have to pay for that is to have
two waits. That is to say, you have to wait for the current to change,
and then discharge the capacity. Unfortunately we see no other way
than waiting. This is precisely the speed at which the device would
work. This is the reason we are asking our semiconductor people to
make the capacity less.
R. A. Karend (BTL): Have you done any work in etching a tunneldiode memory on a semiconductor wafer?
D. G. O'Connor (GPE): At the high frequencies used, what crosstalk
problems have been encountered and what radiation loss?
Mr. Rajchman: I believe the answer is yes. I have a slight amount of
hedging, because we did use a number of techniques, including
etching, I believe, to obtain the dots. Generally, the diodes are made
by taking a fairly large crystal and producing the right impurities in
the surface and then making smaller dots out of it by a number of
Mr. Rajchman: In the case of the microwave solution and one or two
of the others it is a serious problem. Most of the work that we have
done recently is using printing with two ground plates, one on each
side. We haven't made high frequencies yet so we don't know this
for sure.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
48
The Engineering Design of the Stretch Computer
ERICH BLOCHt
INTRODUCTION
HE STRETCH Computer 1 project was started in
order to achieve two orders of magnitude of improvement in performance over the then existing
704. Although this computer, like the 704, is aimed
at scientific problems such as reactor design, hydrodynamics problems, partial differential equations etc.,
its instruction set and organization are such that it
can handle with ease data-processing problems normally associated with commercial applications, such
as processing of alphanumeric fields, sorting, and decimal arithmetic.
In order to achieve the stated goal of performance,
all factors that go into the computer design must
contribute towards the performance goal; this includes the instruction seV, the internal system organization, the data and instruction word length, and
auxiliary features such as status-monitoring devices,
the circuits, packaging, and component technology.
Noone of them by itself can give this hundred-fold
increase in speed; only by the combining and interacting of these contributing factors can this performance be obtained.
This paper reviews the engineering design of the
Stretch System with primary concentration on the
central computer as the main contributor to performmance. In it, these new techniques, devices, and instructions have been pushed to the limit set by the
present technology and, therefore, its analysis will
convey best the problems encountered and the solutions employed.
T
THE STRETCH SYSTEM
Early in the system design, it appeared evident
that a six-fold improvement in memory performance
and a ten-fold improvement in basic circuit speed
over the 704 was the best one could achieve. To meet
the proposed performance criteria, the system had to
be organized in such a way that it took advantage of
every possible overlap of systems function, multiplexing of the major portion of the system, processing
of operations simultaneously, and anticipation of occurrences, wherever possible. The system had to be
capable of making assumptions based on the probability that certain events might occur, and means had
t Data Systems Division, IBM, Poughkeepsie, N. Y.
1 S.W. Dunwell, "Design Objectives for the IBM Stretch Computer,"
EJCC Proc., p. 20, Dec. 1956.
2 W. Buchholz, "Selection of an Instruction Language," W JCC
Pmc., p. 128, May 1958.
to be provided to retrace the steps when the assumption proved to be wrong.
This simultaneity and multiplexing of operations
reflects itself in the Stretch System at all levels,
from overall systems organization to the cycle of
specific instructions. In the following description, this
will be discussed in more detail.
INSTRUCTION
MEMORIES
(1100 2 INTERl.£AVEO 1
OPERAND MEMORIES
(1100 4 INTERLEAVED 1
Fig. I-The Stretch system.
If one considers the Stretch System (Fig. 1) from
an overall point of view it becomes apparent that the
major parts of the system can operate simultaneously:
a. The 2-J.Lsec, 16,384-word core memories are selfcontained, with their own clocks, addressing
circuits, data registers and checking circuits.
The memories themselves are interleaved so that
the first two memories have their addresses distributed modulo 2 and the other four are interleaved modulo 4. The modulo-2-interleaved
memories are used primarily for instruction
storage; since, for high-performance instructions, halfword formats are used, the average
rate of obtaining instructions is one per Y2 J.Lsec.
Similarly, a 0.5-J.Lsec data-word rate is achieved
by the use of four modulo-4 organized memories.
The addressing of the memories and the transfer
of information from and to the memories by a
memory bus permits new addresses, information, or both to pass through the bus every
200 mJ.Lsec.
b. The simultaneously-operating Input/Output
units are linked with the memories and the computer through the Exchange, which, after initial
instruction by the computer, coordinates the
49
Bloch: Engineering Design of the Stretch Computer
starting of the I/O equipment, the checking and
error-correction of the information, the arrangement of the information into memory words,
and the fetching and storing of the information
from and to memory. All these functions are
executed without the use of the computer, so it
can in the meantime continue its data processing and computation.
c. The central computer processes and executes the
stored program. Here, now, the simultaneity and
multiplexing of functions has reached its
ultimate.
Before discussing the computer organization, a few
general features must be mentioned for completeness:
a. Word length: 64 bits plus eight bits for parity
checks and error-correction codes.
b. Memory capacity and addressing: A possible
256,000 words can be randomly addressed.
These storage positions are all in external memory, except for the 32 first addresses. These
positions consist of the internal registers (accumulators, time clocks, index registers).
c. The instructions are single-address instructions
with the exception of a number of special codes
that imply the second address explicitly.
The instruction set (Fig. 2) is generalized and
contains a full set for single- and double-precision floating-point arithmetic, and a full set for
variable-field-length integer arithmetic (binary
.and decimal). It also has a generalized set for
index modification and a branching set, as well
as a set of I/O instructions. All told, 765 different types of instructions are used in the system.
COMPUTER VOCABUlARY
INSTRUCTION
CATEGORY
ClASS
MODIFIER
VARIABLE FIELD
LENGTH ARITHMETIC
BINARY
DECIMAL
SIGNED
UNSIGNED
SAME SIGN
NEGATIVE SIGN
RADIX CONVERSION
NUMBER
INDEXING ARITHMETIC
BRANCHES
Of INSTR.
BIN/DEC
280
32
LOGIC CONNECTS
FLOATING POINT
ARITHMETIC
EXAMPLES
ADD (TO MEMORY)
LOAD/STORE
MPY
DIVIDE
CUMUlATIVE MPV
16 LOGIC STATEMENT
NORMALIZED
SAME SIGN
UNNORMALIZED OPPOSITE SIGN
NEGATIVE SIGN
NOISY MODE
ADD (SINGLE & DOUBLE)
LOAD/STORE
MPV/(SINGLE &DOUBLE)
DIV(WITH REMAINDER)
INTERCHANGE DIVIDE
CUMUlATIVE MPV
SQUARE ROO!'
DIRECT
IMMEDIATE
PROGRESSIVE
48
2010
043
UNCONDITIGIA
INDEXING
INDICATOR
} IF {~}
BIT
LEAVE BIT
INVERT BIT
68
TRANSMIT/SWAP
Vo INSTRUCTION
204
TOTAL
Fig. 2-The instruction set.
o
7
~~NG T
EXPONENT
o
INOEX
BYTE 6
~
BYTE 5 BYTE.. BYTE 3
~
§
~
Q
~
BYTE 2
BYTE I
~
~i~TS
~
n
63
71
MANTISSA (FRACTION I
101112
VALUE
WORD
23
=~ROI..I
DATA WORD AOR
28
46
Is~'&SI1
I 18
COUNT
25 28
I
REFill
46
Ip!~frv I
63
n
INSTRUCTION FORMATS
INTE'GER
=~NGI
ADDRESS
DIRECT
INDEX
~S:a>:~I
28
18
0
ADDRESS
I
~
:I lop I I
I
J
19
23
28
~
Fig. 3-Data word - and instruction word formats.
d. The instruction format (Fig. 3) makes use of
both half and full words; half words accommodate indexing and floating-point instructions (for
optimum performance these two sets of instructions use a rigid format), and full-word formats
are used by the variable-field-length instructions. Notice that the latter specifies the operand
field by the address of its left-most bit, the
length of the field, and the byte* size, as well as
the start,ing point (offset) of the implied operand
(accumulator). Both halves of the word are independently indexable .
e. A general monitoring device used for important
status triggers is called the Interrupt 3 System.
This system monitors the flip-flops which reflect
internal malfunctions, result significance (exponent range, mantissa zero, overflow, underflow), program errors (illegal instruction, protected memory area), and input/output conditions (unit not ready, etc.). The status of these
flip-flops can cause a break in the normal progression of the stored program for fix-up purposes. Their status is automatically interrogated
at all times.
THE STRETCH COMPUTER
SET 0
STORE INST CTR
INTEGER BYTE B BYTE 7
735
If one considers the internal organization of the
majority of computers that have been produced during the last eight years (and the 704 is a case in point) ,
the organization looks as shown in Fig. 4a. There
is a sequential flow of instructions into the computer,
and after due processing and execution, the next instruction is called from memory. Compare this with
* Byte: a generic term to denote the number of bits to be operated
on as a unit by a variable-field-length instruction.
3 F. P. Brooks, Jr., "A Program-Controlled Program Interruption
System," EJCC Proc., p. 128, Dec. 1957.
50
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
DATA WORD
!
INSTRUCTION
4 INSTRUCTIONS
4 DATA WORDS
Fig. 4--Comparison of Stretch and 704 organization.
Fig. 4b, showing the organization of Stretch, where
two instruction words and four operands can be
fetched simultaneously. In addition, the execution of
the instruction is done in parallel and simultaneously
wi th the described fetching functions.
All the units of the computer are loosely coupled
together, each one controlled by its own clock system which in turn is synchronized by a master
osciilator. This multiplexing of the units of the computer results in a large number of registers and
adders, since time-sharing of the major computer
organs is no longer possible. All in all, the computer
has 3,000 register positions and about 450 adder
positions.
Despite the multiplexing and simultaneous operation of successive instructions, the result appears as
if sequential step-by-step internal operation were
utilized. This has made the design of the interlocks
quite complex.
Data Flow
The data flow through the computer is shown in
Fig. 5 and is comparable to a pipeline whic~ in a
steady state (namely, once filled) has a large ?utput
rate no matter what its length. The same IS true
here; after start-up the execution of the instructions
Fig. 5-Stretch Computer - units and dataflow.
is fast and bears no relation at all to the stages it
must progress through.
The Memory Bus is the communication link between the memories on one side and the exchanges
and the computer on the other. It monitors the requests for storage to, or fetches from, memory, and
sets up a priority scheme. Since I/O units cannot
hold up their requests, the exchange will get highest
priority, followed by the computer. In th~ c?mputer
the instruction-fetch mechanism has prIOrIty over
the operand-fetch mechanism. All told, the memory
bus gets requests from and assigns priority to eight
different channels.
Since memory can be accessed from multiple
sources and once accessed it is on its own to complete
its cyc1~, a busy condition can exist. Here again, the
memory bus tests for busy conditions and delays the
requesting unit until memory is ready to be interrogated on data fetches. The.retur~ addre~s is rem~m
bered and the requesting umt reCeIves the InformatIon
when it becomes available. To accomplish this, from
the time information is requested the receiving data
register is in a reserved status.
Requests for stores and fetches can be processed
at a 200 m#,sec rate and the time, if no busy or
priority conditions exist, to return the word to the
requesting unit is 1.6 ~ec, a direct function of the
memory read-out time.
The Instruction Unit 4 is a computer of its own. It
has its own instruction set, its own small memory for
index word storage, and its own arithmetic unit.
During its operation as many as six instructions can
be at various stages of execution.
The Instruction Unit fetches the instruction words
from memory, it steps the instruction counter, and
performs the indexing of instructions and the initiation of data fetches. Mter a preliminary decoding of
the class of instruction, it recognizes its own instructions and executes indexing instructions. On branches,
oonditional or unconditional, the instruction unit executes these. In the case of conditional branches, it
makes the assumption that the branch will not be
successful.
This assumption and the availability of two fullword buffer registers keep the flow of instruction to
the computer continuous. Therefore, the rate of instructions entering the instruction unit is for all practical purposes independent of the memory cycle.
Since, for high speed instructions, half-word formats are used, four of these at anyone time can be
in buffer storage. As soon as the instruction unit
starts processing an instruction, it is removed from
the buffer, thus making room for the next memoryword access (Fig. 6). Incidentally, half-word instructions and full-word instructions can be intermixed
4 G. A. Blaauw, "Indexing and Control-Word Techniques," IBM
Journal, July 1959.
Bloch: Engineering Design of the Stretch Computer
MEMORY OUT BUS
LOOKAHEAD LOAD
UNES
CHECKER IN BUS
MEMORY AOORESS BUS
Fig. 6--Instruction unit.
within the same word, and therefore the latter can
cross a word boundary. This permits maximum packing of instructions in memory and also serves as a
facility for automatic program assemblers and compilers.
The adder path, index registers, and transfer bus
to look-ahead complete the instruction unit system
(Fig. 6). It should be noted that the index registers
are part of the instruction-unit data path, therefore
permitting fast access (no long transmission lines) to
an index word. There are 16 index words available
to the programmer. The index registers, consisting of
multi-aperture cores, are operated in a non-destructive fashion, since in a representative program, the
index word is used nine out of ten times without
modifying it. This permits fast operation under these
conditions, and additional time is only applied where
modification is involved.
After processing through the instruction unit, the
updated (indexed) instruction enters a level of the
Look-ahead (Fig. 5). Besides the instruction, all necessary information, its associated instruction counter
value, and certain tag information are also stored in
the same level. The operand, already requested by
the instruction unit, will enter this level directly and
will be checked and error-corrected while awaiting
transfer to the arithmetic units for execution.
An interlocked counter mechanism in the lookahead keeps its four levels in step, preventing out-ofsequence execution of instructions, even if all information for a succeeding one is available, before the
previous instruction has been started.
The pre-accessing of operands by the look-ahead
and of instructions by the instruction unit leads sometimes to embarassing positions, for which a fix-up
routine must be provided. Consider the program
51
and assume instruction (n) is in look-ahead, waiting
for execution. If (n + 2) now enters the look-ahead,
a reference to m cannot be made, since the data
stored in that position is subject to change by the
STORE instruction. The look-ahead must recognize
this and "forward" the result of instruction (n), when
received, to the level where (n + 2) is stored.
Another example is the case where the instruction
unit assumed that a conditional branch would not be
executed. This instruction is stored in look-ahead
and, when it is recognized that the branch was successful, all modifications of addressable registers
made by the instruction unit in the meantime must
be restored. Look-ahead in this case acts as a recovery
memory for this information. A similar condition
exists when interrupts occur due to arithmetic results.
The look-ahead here again has the data stored pertaining to registers which were modified erroneously
in the meantime. The restoring and recovery routines
described break into the instruction unit processing,
interrupting temporarily the flow of instruction and
their indexing.
The arithmetic units described later are slaves to
the look-ahead, receiving not only operands and instruction codes but also the start-execution signal.
Conversely, the arithmetic units signal to the lookahead the termination of an operation and, in the
case of "To Memory" operations, place into the lookahead the result word for transfer to the proper memory position. '
Arithmetic Units
l
(n)
(n + 1)
(n
+ 2)
STORE Accumulator m
LOAD R
ADD m
The design of the arithmetic units was established
along lines similar to the design of look-ahead and
the instruction unit. Every attempt was made to
speed up the execution of arithmetic operations by
multiplexing techniques and overlapping of the
algorithm, where mathematically permissible.
The arithmetic units, consisting of the Serial Unit
and the Parallel Unit, use the same arithmetic registers, namely a double-length accumulator (A,B)
consisting of 128 bits and a double-length operand
register (C,D) consisting of 128 bits. The reason for
the use of the same arithmetic registers is the fact
that at any time, a shift from floating-point to variable-field-length operation (or vice versa) can be made
by the program. Therefore, the result obtained by a
floating-point operation can serve as the starting
operand for a variable-field-length operation. The
chief reason for the double-length registers is the
definition of maximum field length to be 64 bits. The
field can start with any bit position, and therefore
can cross the word boundary.
The executions of floating-point mantissa operations and variable-field-length binary multiply and
divide operations are performed by the parallel unit,
whereas the floating-point exponent operation and
52
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
the variable-field-length binary and decimal add-type
operations are executed by the serial unit. The
square-root operation and the binary-to-decimal conversion algorithm are executed in unison by both
units. Salient features of the two units will now be
described.
The Serial Arithmetic U nit. ~ (Fig. 7) The serial
arithmetic consists of a switch matrix which can
extract 16 consecutive bits from A,B and C,D.These
16 bits then can be aligned in such a way that the
low-order bit of a field as specified by the instruction
is at the right end of the field. This wrap-around circuit then feeds into a carry-propagate adder, or, in
case of logical-connect instructions, into the logic
unit. At the adder output, a true complement unit
and a binary-to-decimal correction unit are used for
subtract and decimal operations. The inverse process
of extracting is used to insert the processed byte back
into the register without disturbing any neighboring
positions. Notice that in one clock cycle, the information is extracted, the arithmetic is performed
and the result inserted back into the registers. In
addition, the arithmetic information is checked by
parity checks on the switch matrices and by duplication and comparison of the arithmetic procedure in
a duplicate unit.
Fig. 8-Floating point arithmetic unit.
results in a delay time of 150 m,usec for 96-bit binarynumber additions. All additions and subtractions are
made in one's complement form with automatic endaround carry.
The shifter is capable of shifting up to 4 positions
to the right and up to 6 positions to the left. This
shifter arrangement takes care of the majority of
shifting operations encountered under normal operation. Where higher-order shifts are required, a successive operation is set up between the parallel unit
register and the shifter.
To expedite the execution of the mUltiply instruction, 12 bits of the multiplier are handled within one
cycle. This is accomplished by breaking the 12 bits
into groups of three bits each. The action is from
right to left and consists of decoding each group of
three bits. By observing the lowest-order bit of the
next higher group, a decision is made as to what
multiple of the multiplicand one must add to the partial product. Since only even mUltiples of the multiplicand are available, subtraction and addition of the
multiples can result. The following example will
elaborate this point: (MCD means multiplicand)
Groups
Fig. 7-Serial arithmetic unit.
n+4
n+3
xxO
011
n+2
n+l
Multiplier, 12 bit group
110
101
Octal value
n
010
Parallel Arithmetic Unit. The parallel arithmetic
3
2
6
5
unit (Fig. 8) is designed to execute floating-point
If two additions of multiples were permitted
operations with a maximum of efficiency. Since both
4 XMCD
6 XMCD
6 XMCD
2 XMCD
-IXMCD
-IXMCD
single- and double-precision arithmetic is performed,
the shifter and adder exist in a double-length format
Instead of subtracting 1 XMCD in n+l, subtract 8XMCD in n.
of 96 bits. This insures almost the same performance
4XMCD
6XMCD
6XMCD
2XMCD
-8XMCD
-8XMCD
for single- and double-precision arithmetic. The adder
Resulting ~ecoding
is of a carry-progapation type with look-ahead over
4XMCD
-2XMCD
6XMCD
-6XMCD
4 bits at a time to reduce the delay that normally results in a ripple-carry adder. This carry look-ahead The four multiple multiplicand groups and the partial
product of the previous cycle are now fed into carry5 F. P. Brooks, Jr. et al; "Processing Data in Bits and Pieces,"
Trans. IRE on Electronic Computers, June 1959.
save adders of the form,
53
Bloch: Engineering Design of the Stretch Computer
Sum S = A-v-B~C
Carry C' = AB + AC
There are four of these adders, two in parallel followed by two more in series (Fig. 8). The output of
Carry-Save Adder 4 then results in a double-rank
partial product, the product sum and the product
carry. For each cycle this is fed into Carry-Save
Adder 2, and, during the last cycle, into the carrypropagate adder, for accumulation of the carries.
Since no propagation of carries is required in the four
cycles, where multiple multiplicands are added, this
operation is fast and is the main contributor to the
fast multiply-time of Stretch.
The divide scheme 6 has a similarity to the multiply scheme. Multiples of the divisor are used,
namely, 3/2 X divisor, 3/4 X divisor and 1 X divisor.
This, plus shifting over strings of ones and zeros, results in the generation of the required 48 quotient
bits within thirteen machine cycles. Most machines
using a nonrestoring divide method require 48 cycles
for 48 quotient bits. The following example explains
this technique. This· scheme depends on the use of
normalized divisors:
DIVIDEND
DIVISOR
(DD) = 101000000000000
(DR) = 1100011
2's COMP DR (DR) = 0011101
3/4 DR
= 100101001
(a) Using skip over 1/0 only:
Step 1:
101000000000000
0011101
1101101
DIVIDEND
ADD DR
Remainder negative, 1st quotient bit = 0; shift one
position. Leading 1 indicates that next quotient
bit must be 1; QIQ2 = 01
Step 2:
011010000
1100011
10010111
REMAINDER
ADD DR
Overflow: Remainder positive and Qa = 1, leading
zero indicates Q4 = 0
Step 3:
1011100
0011101
1111001
Cycle 1:
Cycle 2:
Cycle 3:
+ BC.
REMAINDER
ADD DR
Negative remainder; Q5 = 0; leading l's indicate
Q6Q7QS = 111
N umber of quotient bits per cycle:
6 J. E. Robertson, "A New Class of Digital Division Methods,"
Trans. IRE on Electronic Computers, vol. EC-7, pp. 218-222; Sept.
1958.
01 = 2
10 = 2
0111 = 4
(b) The same problem with both skip over 1/0 and
3/4 - 3/2 complement:
Step 1:
101000000000000
0011101
11011010000
Same as before, QIQ2 = 01
Step 2:
100101001
111111001
Add 3/4 DR
This (by table look-up) indicates QaQ4Q5Q6Q7Qs =
100111
Quotient bits generated per cycle:
Cycle 1:
Cycle 2:
01 = 2
100111 = 6
In general, this method results in the generation of
3.7 quotient bits per subtraction. While the mantissa
operations of multiply and divide are performed by
the parallel unit, the serial arithmetic unit executes
the exponent arithmetic. Here again is a case where
overlap and simultaneity of operation is used to
special advantage.
3. Checking. The operation of the computer is
checked in its entirety and correction codes are employed where data transfers from memory and inputoutput units are involved. In particular, all information sent to memory has a correction code associated
with it, which is checked for accuracy on its way from
memory. If a single error is indicated, then correction
is made and the error is recorded via a maintenance
output device. Within the machine, all arithmetic
operations are checked, either by parity, duplication,
or a "casting out three" process. These checks are
overlapped with the execution of the next instruction.
4. Hardware Count. Fig. 9 shows the percentage of
transistors used in the various sections of the machine.
It becomes obvious that the parallel unit and the
instruction unit use the highest percentage of transistors. In case of the parallel unit this is due to the
extensive circuits for multiply and to the additional
hardware to achieve speed of up the divide scheme.
In the instruction unit, the controls consume the
majority of the transistors, because of the high multiplexed operation encountered.
5. Performance. The performance comparisons in
Fig. 10 show the increase in speed achieved, especially
in floating-point operations, over the 704. It should
be noted that for a large number of problems this
particular increase in all arithmetic speeds is almost
proportional to the performance increase of the prob-
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
54
UNIT
' OF TlANSISTOIS
~O!'TorAl
'OF flAMES
2
10,.
6.0
11,"
II',.
22.0
2
3-1/2
DATA'ATH
CONTIOlS
11,900
8,600
15.6
I
1-1/2
AlITH. IEGISTDS
10,000
5.9
10,000
8,"
10.5
1-1/2
I
32,,.
21.0
2-1/2
1/2
24,.
14.5
I
6,000
3.5
169,100
100.0
~CONTIOIS
INSTlUCTION UNIT
DATA 'ATH
CONTIOlS
LOOIC-AHfAD
I
SfllAL AllTH. UNIT
DATA'ATH
CONTIOIS
fL~T1NG " . UNIT
DATA'ATH
CONTIOlS
3,000
CHECKING
INTEnU" SYSTEM
TorAL
1/2
18
4,025
18,747
21 leW
DOUlLE CAIDS
SINGLE CARDS
POWER
Fig. 9-Component count.
OPERATION
I.
Fl~TlNG
11M
11M
11M
105
STRETCH
POINT
,!21M8
,!128
EXPONENT RANGE
MANTISSAIITS
FL~TINGADD
Fl~TlNG MI'Y
FL~TINGDIV
L~D~TOIE
2.
+2
+2
""21
4a
84 USEC
1.0
1.8
1.0
.6
204 USEC
216 USEC
24 USEC
USEC
USEC
USEC
USEC
IINAlYVAIIAll.E
FIELD LENGTH AlITH.
I T064
2.0 USEC
10.0 USEC
15.0 USEC
liT RANGE
i~~~TORE
16
liT
FIELD
DIVIDE
3.
DECIMAL
~
1 _ MEM CAPACITY
119 USEC
DIGIT RANGE
~ ADD
MI'Y
FOR
5
DIGITS
4.
199 USEC
4828 USEC
204 USEC
DIVIDE
LOAD/STORE
1 T021
USEC
USEC
USEC
3.2 USEC
3.S
40.0
65.0
cut-off of approximately 100 mc and for high-speed
operation must be kept out of saturation at all times.
This then explains why both the PNP and NPN version are used: mainly to avoid the problem of level
translation, which would be required due to the potential difference of the base and the collector. This difference is 6 volts, an optimum point for this device.
Fig. 11 shows the basic circuit configuration. It
consists of a current source, represented by the - 30
volt supply and resistor R. The functional operation
of the circuits consists of two possible paths represented by transistor A or C. Which path is chosen by
the current depends on the condition existing on base
A. If point A is positive with respect to ground by
0.4 volts, that particular transistor is cut off, making
the emitter of transistor C positive with respect to
the base and, therefore, making C conducting. The
current supplied by the current source (6 ma) will
then flow through transistor C to the load cpo Output
cp, then, is positive by 0.4 volts with respect to the
-6 volt reference. This indicates at cp the equivalent
function impressed on A. At the same time, 4> is negative with respect to the - 6 volt power supply by
0.4 volt, representing, therefore, the inverse of the
function impressed on A. Conversely if A is negative
with respect to the ground reference, transistor A is
the conducting one, keeping emitter C negative with
respect to its base. The current flows through transistor A, making ($ positive with respect to - 6 and cp
negative with respect to - 6. Again, the output of cp
reflects the function impressed on A, whereas 4> represents the inverse of the function.
If an additional transistor now is paralleled with
A, it becomes obvious that only if both bases A and
B are positive will output cp be positive and 4> neg a-
MISCELlANEOUS
SVMBOL
ERROR CORRECTION
CHECKING
WORD SIZE
NO
NO
36I1TS
NO
YES
YES
YES
64I1TS
--l::l-- t
A-i
B-o-.A'8
TRUTH
TABLE
Fig. l(}---Comparison of Stretch and 705/704 operation times.
lem as a whole, since the instruction execution-times
are overlapped to a great extent with the preparation
and fetching of instructions. Simulation of Stretch
programs on the 704 proved a performance of 100 X
704 speed in mesh-type calculations. Higher performance figures are achieved where double- or tripleprecision calculations are required.
A
I-i+"-B-'-_++,.-I • sA • B
-
+ - +
i·A-i
+'--1 sA+i
1---&..-11--......
,----,-.....:.:....--_---oIIHI
CIRCUIT
OIAGRAM
AN
-12
t---*-----otlA·BI
OUTPUT
Having . reviewed the systems organization of
Stretch, it is now of interest to discuss briefly the
components, circuits, and packaging techniques used
to implement the design.
The basic component used in Stretch is the highspeed drift transistor which exists in both an NPN
and a PNP version. This transistor has a frequency
~-5.2V
INPUT
CIRCUITS
MIN- MAX
SIGNAL
VOLTAGES
?l'ZZZZZZZ
t:! ~
REF
OV
~-.4V
~-.8V
~-UV
REF
-IV
f'777777
-6.4V
~-6.5V
CIRCUIT
RESPONSE
INPUT
Fig. ll-Current switching circuits (+AND).
Bloch: Engineering Design of the Stretch Computer
tive. If any or none of the bases A and B are positive,
then q, will be negative and 4> will be positive. In
other words, an AND function is obtained on output q,.
This principle, which is reflected in all the circuits,
is essentially the principle of current switching or
current steering.
Logical functions for the PNP circuits are, therefore, a + AND or - OR. Two outputs from each circuit
block are available: the AND function and the inverse
of the AND function.
A dual circuit exists for NPN transistors with input levels at -6 volts and output levels at ground.
This circuit will give the +OR or - AND function.
A thorough investigation of the systems design
showed that the circuits described so far are versatile
enough to be used throughout the system. However,
there are enough special cases (resulting from the
many data buses and registers throughout the
machine) that could use a distributor function or an
overriding function. This caused the design of a circuit which permitted great savings in space and transistors by adding a third voltage level. Fig. 12 shows
the PNP version of the third-level circuit.
Op
AN
A a
x
~iI)m
+ + + +
+
+ +
+
+
+
+
+
+ +
+
+
+
+
+
+
-
;'#~
:
-
-
-
-
SYliaOL
-
a
A
x
~CQ.
+ + + + + + + + +
+ + +
+
+ + +
+ +
+
+
-
-
+
+
-
+
+
-
+
+
+ +
TRUTH TABLES
~-~------~~--~
A
1-----<11_--0111
+30
inverse of input X. If, however, X is positive, then
the status of A and B will determine the function cp
and 4> implicitly. This demonstrates the overriding
function of input X.
Similarly, the NPN version (not shown) results in
the OR function of cp if input X is negative and in a
positive output at cp and ~, regardless of status A and
B, if X is positive. Again minimum and maximum
signal swings are shown in Fig. 12.
The speed of the circuits described so far depends
on the number of inputs and the number of circuits
driven from each load. The response of the circuit is
anywhere between 12 and 25 m}Lsec per logical step
with 18 to 20 m}Lsec average. The number of inputs
allowable per circuit is eight. The number of driven
circuits is three. Additional circuits are needed to
drive more than three bases and where current
switching circuits communicate over long lines, termination networks must be added to avoid reflections.
To improve the performance of the computer in
certain critical places, emitter-follower logic is used
as shown in Fig. 13. These circuits, having a gain less
than one, after a number of stages require the use of
current switching circuits as level setters and gain
devices. Both AND and OR circuits are available for
both a ground-level and a -6-level input. Change
from a - 6-level circuit to a ground-level circuit is
obtained by applying the appropriate power supply
levels. Due to the variations in inputs and driven
loads, the circuits must be designed so that the load
can vary over a wide range. This resulted in instability which had to be offset by the feedback capacitor
C shown in the circuit.
All functions needed in the computer can be implemented by the use of the aforementioned circuits,
:=0--..
OUTPUTS
INPUTS
A,a • x
IIIN -MAX
~AL
\IOUAGES
2'.lZ2Z:::
REF
X INPUT
ONLY
~
{B
CIRCUIT
~-5.6
6ND
A.a
ONLY
~-5.2V
-.4
-.8
-
55
- - - 6.0V
?ZZ2Z
=:.:
(ALL OUTPUTS I
B.
li
+ + +
TRUTH TABlES
-+-ANO
+ -
12
-20
CIRCUIT RESPONSE
-
-6V
+6V
CIRCUIT
DIAGRAM
AN
Fig. I2-Third level circuit.
If transistor X were eliminated, then transistors
A and B in conjunction with the reference transistor
C would work normally as a· current switching circuit,
in this case a + AND circuit. If transistor X is added
with the stipulation that the down level of X is more
negative than the lowest possible level of A or B, it
becomes apparent that when X is negative, the 'cUrrent will flow through that branch of the circuit in
preference to branch q, or 4>, regardless of inputs A
and B. Therefore, the output of q, and 4> will be negative, provided input X is negative. Output III is the
ON
1.21K
+6V
A+a
-6V
+6V
-6V
~:.:5
MIN-MAX
SIGNAL VOLTAGES
REF---GND
BEG. OF
CHAIN
CIRCUIT RESPONSE
~-6
~-1.0
~+l.1
~+~
GND
REF
~-;:;41
~
~HU'=m~_
Fig. I3-Emitter follower circuit.
56
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
including flip-flop operation, which is obtained by
tying a PNP current switch block and an NPN current switch block together with proper feedback.
PACKAGING
The circuits described in the last paragraph are packaged in two ways:
A circuit package using the smaller of the two
printed circuit boards shown in Fig. 14, called a
single card, contains AND or OR circuits. It should be
mentioned that the printed wiring is one-sided and
that besides the components and transistors, a rail is
added which permits the shorting or addition of certain loads depending on the use of the circuits. This
rail then has the effect of reducing the different types
of circuit boards in the machine. Twenty-four different boards are used and of these, two types reflect approximately 70'% of the total single card population.
Fig. I5-The backpanel.
Fig. 14-The circuit package.
Due to the large number of registers, adders, and
shifters used in the computer, it seems reasonable
that functional packages could be employed economically, because of wide usage. This results in the highdensity package also shown in Fig. 14, called a Double
Card, which has 4 times the capacity of a single card
and which has wiring on both sides of the board.
Furthermore, components are double-stacked; and
again, the rail is used to effect circuit variations due
to different applications. Eighteen double card types
are used in the system. Approximately 4,0'00 double
cards are used, housing 60% of the transistors. The
rest of the transistors are on approximately 18,00'0
single cards.
The cards, both single and double, are assembled
in gates, and two gates are assembled into a frame.
Fig. 15 shows the gate back-panel wiring, using wirewraps; and Figs. 16 and 17 the frame construction,
both in a closed and open version.
To achieve high performance, special emphasis
must be placed on keeping noise to a low level. This
required the use of a plane which overlies the whole
back panel, against which the intercircuit wiring is
laid. In addition, the power-supply distribution system must be of such a low impedance that extraneous
Fig. 16-The frame (closed).
Bloch: Engineering Design of the Stretch Computer
57
ACKNOWLEDGMENTS
The efforts and contributions of many people
have gone into the engineering design of the Stretch
computer. To mention all would be impossible. However, the following individuals and their groups were
responsible for the units indicated; Mr. R. T. Blosk
for the Instruction Unit, Mr. J. F. Dirac for the
Look-ahead Units, Messrs. J. A. Hipp and O. L.
MacSorley for the Arithmetic Units and Mr. L. O.
Ulfsparre for the Memory Bus. The Systems Development was under the guidance of Messrs. S. W.
Dunwell and R. E. Merwin.
DISCUSSION
H. Aiken: You have told us a great deal on schemes used to speed
up the computer. Now I wonder if you would spend a minute or
two telling us what gains you have made in system logic, or what
concessions you have had to make.
Fig. 17-The frame (extended).
noise cannot induce circuit malfunction. For this reason, a bus system, consisting of laminated copper
sheets, is used to distribute the power to each row of
card sockets. The wiring rules are such that singleconductor wire is used up to a maximum of 24",
twisted pair to a maximum of 36", unterminated coax
to a maximum of 60", and terminated coax to a maximum of 100 feet. The whole back-panel construction
and the application of single wire, twisted pair, or
coax are calculated by a computer program to minimize the noise on each circuit node.
The two gates of a frame are a sliding pair with the
power supply mounted on the sliding portion. All
connecting wires between frames are coax and arrayed in layers which are formed into a drape.
SUMMARY
The Stretch computer is an advanced scientific
computer with variable facilities for floating-point,
fixed-point, and variable-field-length arithmetic and
data-handling facilities.
The performance goal of 100 X 704 speed is
achieved by high-speed circuits, multiplexing, and
simultaneous-operation technique of instruction and
data-fetching, as well as overlap within the execution
units. This massive overlap and multiplexing results
in complicated recovery routines between the lookahead and instruction units. These units are described
in detail, as are the arithmetic units and significant
algorithms used in the floating point arithmtic.
A flexible set of circuits using a current-switching
technique with overriding-level facility is described,
as well as the packaging of circuits on printed cards.
The frame and gate concept is also shown. Performance figures and hardware count illustrate the size,
complexity, and performance of the system.
Mr. Bloch: The gains in system logic were in novel ways of performing high speed arithmetic, in the way multiplexing of operations was achieved, in the considerations necessary to interlock the
individual units of the computer, and in designing complex interrupt
and information-recovery networks.
C. W. Rosenthal (Bell Tel. Labs): With respect to your goal of increased speed over the 704, what portion do you attribute to faster
devices and what portion to organiZation changes? Can you separate
the effect of the individual organization changes?
Mr. Bloch: I think one order of magnitude of improvement is due
to faster devices and faster circuits. The other order of magnitude
of improvement is due to system organization, multiplexing and so
forth. As to your second question, overlapping techniques and lookahead contribute less than half to the performance; the remainder
is due to new schemes in the execution units.
D. Hammel (RCA): What is the full time required to execute a short
instruction such as an add instruction? Identify the various steps.
Mr. Bloch: This question is not so easy to answer. Because of the
computer organization which is extensively overlapped, the only
time that can be charged to the ADD operation is the execution time
in the arithmetic unit. For a Floating Add, which I assume you have
reference to, it amounts to the following: 30 per cent of the time
is spent to find out what the relative pre-shift of mantissas is. About
40 per cent of the time is spent in shifting and performing the actual
addition operation. The rest of the time, which is quite considerable,
is spent in doing sig:nificance tests on the results, such as exponent
ranges, zero operands, etc., and in checking and transfer of the informa tion over a bus.
V. Enstein (Brooks Research): Can you mention the general characteristics of the transistors used and the achieved switching speeds?
Mr. Bloch: To answer the transistor question first: it is a drift device
with a cutoff frequency of over a hundred megacycles and a forward
drop of about two-tenths of a volt. The gain is 20 at end of life and
the dissipation is 50 mw. Both PNP and NPN versions have the
same characteristics. As far as the circuit speed is concerned, it
varies from 12 to 25 millimicroseconds, depending on fan-in and
fan-out. The third-level circuit shown is slightly slower than the
normal current-switching circuits, due to larger level swings.
W. A. Cava (Philco): What programming procedures are necessary
to produce a minimum number of interruptions in the normal
sequence of operation?
Mr. Bloch: Some of the interrupt bits which trigger routines can be
inhibited by the programmer. Also, the definition of the interrupt
conditions is such that only extreme occurrences can bring them
into play. Therefore the frequency of interrupts should be small in
the majority of problems.
58
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
M. Lewin (RCA): What adjustments are required on the plug in
cards from the time they are wired up until they are ready to be
plugged in?
Mr. Bloch:The only adjustment you have to make to the cards is
the clipping of the rail. This changes the configuration logically, and
changes the circuit as far as load networks are concerned. This is
the only change that has t.o be made.
D. Neumann (Lincoln Lab.): Why do you assume a branch will not
take place? Use of programming loops usually has branches occurring
more often than not..
Mr. Bloch: This is quite an arbitrary decision. It could have been
done the other way. Once it is specified arbit.rarily, t.he programmer
is not better or worse off, whichever way it is defined.
Mr. Scola: How effective is it in detecting marginal transistors and
circuits?
Mr. Bloch: What you are doing in varying the voltages is checking
gain. characteristics as well as frequency response of the circuits.
By the way, each frame has its own built-in marginal-voltage supply.
G. E. Salt us (BTL): What is the approximate size of the central
processor? What total power dissipation is associated with the central processor?
Mr. Bloch: It dissipates 21 KW and is about 30 feet long by 6 feet
high by 5 feet deep.
W. Renwick (Plessey Co.): What is the present status of the
STRETCH Project?
D. H. Daggett (Convair): Would you please mention some of the
considerations involved in selecting input-output equipment of
sufficient speed to be compatible with the high processing speeds in
Stretch?
Mr. Bloch: Right now we are in the process of testing out the system
units and tying them together.
Mr. Bloch: The system organization is set up in such a way that
input-output equipment really does not interfere with the computation. The Exchange, which is an input-output computer, so to
speak, takes care of this. Therefore the speed of the input-output
devices is not such a consideration as it is in a machine where simultaneous operation is not possible. As far as input-output equipment
on the STRETCH computer is concerned, there was no great consideration for special input-output devices; rather, more effort was
put into a novel system organization.
Mr. Bloch: As you realize, STRETCH is designed under contract
with the Atomic Energy Commission. The delivery is scheduled for
May, 1960. As far as cost and commercial availability is concerned,
I would rather not answer this question. As I pointed out before,
right now it is strictly considered a one-shot affair under a development contraet.
G. A. Sellers (Bell Labs.): Are the speeds quoted statistical averages
- dependent on numbers - or absolute, - independent of numbers
operated upon?
Mr. Bloch: Yes, three are operating on Stretch, and two have been
supplied to a customer the other day as part of the first 7090's.
Many more are under assembly.
Mr. Bloch: Both. The multiply speed is worst-case. The floatingpoint-add speed depends on the number of pre- and post-shift cycles.
The shifter is capable of shifting six bits at a time, and experience
showed that within the six shifting cycles, 80 per cent of the numbers that are normally flowing through a computer can be handled.
D. Dickman (Los Alamos Lab.): What is the basic cycle time of the
computer?
A. Dowkont (Rand Corp.): When is the first delivery? What is the
cost? What is the commercial availability?
H. P. Peterson (Lincoln Lab.): Is there now a working, reliable,
2-microsecond 16K core memory?
Mr. Bloch: There is no such thing, since the individual units of the
computer operate asynchronously. However, each unit has a clock
which has a cycle anywhere between 200 and 300 millimicroseconds.
T. R. Finch (BTL): At one time I believe you employed a 72-microsecond store, but today you showed only a block of 2-microsecond
stores. Does this change result from improved system organization
or necessary change due to fast store problems or what?
J. Katz (GE): Are you coding in machine language or are compilers
or interpreters in use?
Mr. Bloch: I think from improved system organization. Let me mention, however, one item: I showed the 2-microsecond memories. Now
the instruction unit has a memory of its own of about 16 words, used
as index storage, and it runs at a speed which is comparable to the
speed of the instruction unit itself. In this application it has been
shown that for fast memories to be useful, they must be tightly
interwoven with the computer networks.
F. Mazziotti (IBM): How many instructions per second can your
machine perform in a typical scientific problem?
F. H. Tendrik (Bell Tel. Labs): What is the logical use of the circuit
with the "X" input?
Mr. Bloch: The circuit - third-level circuit - is an overriding function. Essentially what you can do is the following: The "X" input
can be assumed to be an information bit and then normal inputs A
and B might be mutually exclusive signals directing the information to one out of many registers. This is employed for shifters, readout matrices, gating and distributing functions.
S. DeMaio (ITT Lab.): What is the access time of the memory?
Mr. Bloch: About 1.6 microseconds. This includes bus transfer test
for busy and priority conditions, etc.
R. M. Horowitz (Lincoln Lab.): How much power is dissipated in
STRETCH?
Mr. Bloch: The whole STRETCH system dissipates about 70 KW.
P. J. Scola (GE): Do you use marginal checking?
Mr. Bloch: Yes.
Mr. Bloch: We are writing essentially two compiler-type programs.
One is written in STRETCH language; the other is writtf'n in 704
Fortran language.
Mr. Bloch: Well, I don't think I am able to answer this question
here. This depends obviously on what problem you are talking about
and what are the housekeeping functions you are performing during
the computation. I think if you look at the speeds shown before, you
can interpret this for yourself.
L. Clapp (Sylvania): To what extent, if any, have you used computer techniques in the processing of your design and production
data? If so, what computers were used for this program and how
extensive was the effort?
Mr. Bloch: We used computers quite extensively to process logic
pages, and also to compute the noise on each node of the back panel.
The back panel layout and routing was done by computers. Computers used were both 704 and 705 systems.
G. A. Barnard (Ampex): Were you to continue to extend the techniques expounded here, would you comment on the widening gap
between internal speeds and the load/unload speeds of input/output
equipment? What about pressures to speed up the in/out equipments
instead of merely using more of them?
Mr. Bloch: I don't think we are right now input-output limited,
because of the philosophy the system operates under. Also, ,~e have
made great advances in higher-speed and high-storage-capacity disks.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
59
Design of U nivac®- LARC System: I
J.
r.
ECKERT,t J. c. CHU,t A. B. TONIK,t
AND
W. F. SCHMITTt
T
HIS TALK is a progress report and in many
respects a final report on the U nivac® - LARC
system which has been developed by Remington
Rand Univac. It is a companion not only to another
talk on LARC design being given at this time but
with an earlier talk given three years ago to the
EJCC in New York. l
The talk three years ago described the objectives
of a system still in the design stage. This talk describes progress since then. In order to prepare for
this talk we have, of course, reviewed the one delivered three years ago. What we read was quite
interesting. We found that in one sense of the word
we have no progress to report. Fortunately in the
larger sense of the word we have great progress to
report. The area in which no progress, or more precisely no change, has been made deals with the design objectives of the LARC system. All of the goals
set up for the LARC system three years ago have
been very safely achieved. None of the speeds of
any of the operations in the LARC system have
been changed. Basic decimal-checked addition takes
exactly one microsecond as described three years ago.
Memory cycle times of both one microsecond and
four microseconds have been adhered to.
By a conservative design approach and by choosing existing components, we expected LARC to be
completed in 1958. Although we did use then existing components, modifications required to increase
reliability on some of the components, along with
the logical complexity of the system, delayed completion until 1959. If we had compromised our speed
or reliability objectives, the delay would have been
much shorter.
N ow we come to the point where great and for
computer engineering unusual progress can be reported. We have precisely met and proven the validity of our original goals on the world's fastest, most
versatile computing and data processing system as
described in our earlier published talk. Fig. 1 shows
a typical LARC system as it would appear in an
operating installation.
The original objective of the LARC system' was
to build a good system which pressed the limits of
the art while still maintaining balance between its
various elements. We feel a good system is one in
which everything involved is accomplished in a mant Remington-Rand Univac Div., Sperry-Rand Corp., Phila., Pa.
1 J. P. Eckert, "Univac-Larc, The Next Step in Computer Design,"
Proc., 1956 EJCC, (A lEE Special Publication T-I07) pp. 16-19.
Fig. I-A typical LARC system as it would appear
in an installation.
mer which is not only dependable but consistent in
the degree to which it presses the art at the time
the design is frozen. The talk of three years ago established the goals. We have now accomplished them
in the area of logic circuits,' high-speed memories,
input-output equipment, and most important of all
in overall system organization. Further, we have
established an automatic procedure for the prodigious record keeping required to carry out such a
design. The companion paper will discuss this point
further.
By a balanced system, we mean a system designed
to obtain the greatest work output for the costs involved. Since the problems faced by different users
vary, considerable flexibility of the input-output
equipment and the memory equipment of the computer system is required. In addition to providing
more flexibility in these areas than any other existing
system, the LARC system has the added flexibility of
enabling either one or two computing units to be included as part of the system to allow increased speed.
COMPUTERS AND PROCESSOR
A basic LARC system contains a Computer and a
Processor, each of which has most of the attributes
of a general purpose Computer but perform different
functions in the system. The primary function of the
Processor is the flexible, parallel, and coordinated
control of all input-output equipment and transfers
between this equipment and the memory system.
The Computer is designed to perform rapid arithmetic computation with a minimum of interference.
The two Computers in an expanded system (see
Fig. 2) can be programmed and controlled to solve
jointly a single problem; or each can solve inde-
60
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
, - - - - - - - - - CORE STORAGE - - - - - - - - - - .
COMPUTING
UNIT 1
14---~
t--t---t-------.I
COMPUTING
UNIT 2
PROCESSOR 1 - - - - 1
PAGE
RECORDER
SYNCH
Fig. 2-Block diagram of a LARC system.
multiplying digit and allows Il-by-ll digit products
to be formed in 8 microseconds. Floating-point multiplication of 9-by-9 digits also takes 8 microseconds
the extra time being used for normalizing. The di~
vision process is of fixed length, requiring 5 cycles or
2~ microseconds per quotient digit. It requires 28
mIcroseconds for a floating-point division or 32
microseconds for a fixed-point division.
The pulse code in LARC was carefully chosen to
yield a. ninety percent chance of a single digit superposition error being detected. Of course, since most
such errors occur on several digits, the chance of
not detecting such an error is remote. However
where a single digit must be transferred special
checking circuits are employed to reduce this possibility; or some special circumstance is noted which
makes the chance of detection far greater.
The names ~rocessor and Computer assigned to
the central unIts of the LARC are somewhat misleading. The entire LARC system may be considered
a data processor. What we call the Processor in the
LARC system contains a computer of its own in
a~dition to all of the circuits necessary to synchronIze the on-line equipment into the system. In designing the LARC system, we carefully avoided
incorporating any feature that would increase costs
unless it realized a much greater proportional increase in over-all speed and performance. On the
basis of this criterion alone, the incorporation of a
?omputer within the Processpr is justified, although
~t does. provid~ ~~her important benefits by way of
IncreasIng fleXIbIlIty and simplifying programming
and communication within the system. If the LARC
Computer were designed to perform the duties of
the Processor, it would require additional instructions and other facilities. In such a system, all of
the circuits devoted to synchronizing the on-line
equipment would still be required. In a typical
LARC system, about two-thirds of the Processor
consist of circuits exclusively involved in synchronizing on-line equipment. The Processor computer
represents the remaining one-third of the Processor
or about one-sixth of the equipment and cost of the
Computer and Processor combined. Considering also
the cost of the on-line equipment used in the system,
the incorporation of a computer in the Processor has
contributed between one-seventh and one-eighth to
the total cost and complexity of the LARC system.
The LARC Processor, however, may relieve the
Computer of half of the work load it would otherwise have to bear. We thus have achieved as much
as eight percent increase in speed for everyone percent increase in cost resulting from incorporating the
computer in the processor.
pendent problems. The Processor is designed to take
care of the input-output and other on-line equipment needs of both Computers and to do any necessary editing of the input-output data. If inputoutput demands are not excessive, it may also be
used to run various side routines such as sorting
and merging. It receives compact instructions from
t~e Computer and expands them by program to provIde the control, interlocking, and timing required
to operate simultaneously a large group of on-line
equipment. This function requires only limited
arithmetic ability.
To allow for simultaneous communication between
the various units (a necessity with the high degree
of parallel operation achieved) with a minimum of
switching circuitry, a time-slot system of inter-unit.
communication is used. Time-slotting of the elements of a computer system is quite new and is one
?f the fe.atures which has given LARC such a great
~ncr~ase In s~eed and flexibility without a correspondIng Increase In cost.
In LARC we sought to minimize the total amount
of electronic equipment by considering the logical
design as a whole, rather than seeking to optimize
the equipment required for each individual instruction. For example, there are many methods of performing multiplication which reduce the number of
individual addition operations required without expanding equipment requirements. We examined a
number of these multiplication methods and picked
the arrangement which required the minimum
amount of equipment, not just for multiplication
but .for all of the machine instructions, frequently
Since the programs for the Computer and ProcesmakIng compromises on some specific instruction.
A modified short-cut multiplication procedure was sor are stored in separate memories, debugging can
finally employed that requires only one addition per be done independently, so that the programming is
Eckert, Chu, Tonik, and Schmitt: Design of Univac-LARC System: I
usually made easier. Thus we have speeded up
LARC without overstepping the state of the art
either in circuits or in the demands put upon present
day programming technology.
STORAGE
61
2500-word modules. Since the Computers and the
Processor have access to the same storage, they can
control each others' instruction sequences as desired.
Nearly 100,000 12-digit words of ferrite-core storage
may be included in the system (6,000,000 bits of
core storage).
There are four levels of storage in the LARC system which differ in speed, capacity, and cost per
character.
The first level of storage operates on a one-microsecond cycle. It consists of a number of registers
that may be used interchangeably as accumulator
registers for storing operands and results or as index
(B) registers for storing constants used in addressing
operations. Up to 99 12-digit one-microsecond registers may be included in each Computer unit.
Fig. 4.
Fig. 3-A 10,000 word (600,000 hit) core memory unit.
The second level of storage is a ferrite-core storage
which has a read-write cycle of four microseconds.
Fig. 3 shows a 10,000-word (600,000 bit) core memory cabinet. It is accessible to both Computers and
the Processor. It serves as both the main storage and
buffer storage of the system and as a common communication link between the Computers and the
Processor. To increase the rate at which reference
may be made to the main storage, it is divided into
The third level of storage consists of movablehead magnetic drums. Fig. 4 shows a group of such
units. Data can be transferred between the main
storage and the drums over one of several simultaneous drum circuits at a data transfer rate of 500,000
decimal digits per second (2,500,000 bits per second).
A maximum of 72,000,000 digits of drum storage
(360,000,000 bits of drum storage) may be included
in a system. The drum units are capable of transferring information twenty times as fast as the
tape units, and match the high computing rates of
the LARC system. In addition they provide for
random access in a fraction of a second. Several
drum synchronizers are employed so that computation and printing can proceed in parallel with the
loading and unloading of drums to the tape units.
The moving-head drums themselves are designed
very conservatively. They rotate at 884 RPM. They
are recorded at 448 pulses to an inch and 29 channels to the inch. Several times this pulse rate and
channel density have been achieved in the laboratory on these drums. The magnetic heads which
move on a carriage along the top of the drums are
moved with moderate accelerations. This is possible
since the drums are used in pairs, first moving one
head while another head is reading and then alternating so that the synchronizer is never idle. This
arrangement allows a very conservative approach to
the mechanical problems and a fool-proof headmoving mechanism of simple and rugged design
driven by a servo motor. The drum assembly is
mounted in an air-tight enclosure. Inside air is circulated through special filters to colle.,t any dirt
particles. The design allows the units to be opened
62
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
for repair in a non-air-conditioned room. The magnetic heads fly on the hydrodynamically generated
air film generated by the rotating surface of the
drum. Fig. 5 shows a head flying on the surface of a
drum. No filtered high pressure air supply which
might direct contamination under the head is needed.
A simple mechanism lowers the head on the drum
without causing even momentary contact with the
drum. An electrical circuit detects any contact between head and drum and instantly retracts the head
if any contact occurs.
Fig. 5--A head flying on the surface of a drum.
Flying-head drum units have been life-tested for
well over a year's continuous operation to ensure
that their reliability is consistent with the reliability
of the solid-state circuit equipment. The order of
reliability achieved by these drums is believed to
exceed considerably that obtainable on tape or disc
equipment at this time.
Fig. 6 A group of UNIVAC tape units.
The fourth level of storage consists of magnetic
tape units which transfer data at 25,000 alphanumeric characters per second. Fig. 6 shows a group
of Univac tape units. The tape units provide for
input-output and long-term storage of data. LARC
presently uses medium-speed tape units which not
only have the advantage of being compatible with
other Univac systems and off-line input-output
equipment but have the advantage, due to moderate
pulse densities and moderate tape velocities, of being quite reliable. Faster tape units as they become
available may be used with the LARC. Tape speed
is not usually a limitation, however, since the bulk
of the input-output load has been taken off of the
tape units in the present LARC system by the
drum units.
ON-LINE EQUIPMENT
The on-line equipment includes, in addition to
the tapes and drums used for input-output and
intermediate storage:
1. An electronic page recorder, which employs a
cathode-ray tube and microfilm, as shown in
Fig. 7. It provides high-speed recording of output data. Sixty-four symbols are available for
tabulating and curve plotting. Plots are complete with titles, scales, and grid patterns.
While originally specified at 25,000 characters
per second, this has been changed to 20,000
characters per second to allow more accuracy
in the curve-plotting mode. Fig. 8 is a chart of
the units for a typical and for an expanded
LARC system.
2. Electro-mechanical line printers for multiplecopy printing of numerical characters at 720
lines per minute or printing of combined alphabetic and numeric characters at 600 lines per
minute. The synchronizers will provide signals
for printers operating up to 1200 lines per
minute.
3. A card reader for introducing data into the
system directly from punched cards.
Eckert, Chu, Tonik, and Schmitt: Design of Univac-LARC System,: I
EQU I PMEIIT IlAME
TYPICAl
EXPAIIDED
39
Magnet I C Core Storage Un I ts (2500 word 5 each)
MultIpurpose Fast Registers (per Co.puter)
63
26
99
12
~o
Processor
Dru .... read SynchronIzers
Dru.-wri te Synchron i zers
Tape Read-Wr i te Synchron i zers
Electron ic Page Recorder Synchron izer
High-Speed Printer Synchronizer
Card Reader Synchron izer
Console Printer Synchronizer
Tape Pos it ion ing Checker
2~
Magnetic Dru. Storage Units (250,000 words each)
Uniservo II Magnetic Tape Units
Electronic Page Recorders
.Fig. 9-An operating console to the left and an
engineering console to the right.
High-Speed Printers
High-Speed Card Readers
Control Consoles
lIullerlc Keyboards (one per Console)
Alphanulleric Console Printers (one per Console)
Fig. 8-Modular units of a typical and completely
expanded UNIVAC LARC system.
4. Console typewriter printers with an attached
paper-tape reader and punch.
The original design called for a Processor to contain a minimum of five "synchronizers" and a maximum of eight synchronizers as required for simultaneous operation of the various pieces of on-line
equipment. The capabilities of the LARC system
turned out to be such that in order to provide more
flexibility for customer requirements the minimum
was raised to seven and the maximum to fourteen.
The synchronizers in themselves have flexibility in
the pulse rate they can accept and this, along with
the concept of the Processor and the optional number of synchronizers that may be used, is one of the
more important features in obtaining the high speed
and flexibility of the LARC system.
LARC CONSOLES
the consoles is the ability to monitor the operations
of the computing unit in a unique way. The digital
display units and corresponding binary display units
may be connected to anyone of a number of key
points of the computing unit. Synchronizing equipment allows these registers to display at a particular
pulse time and program step selected by the engineer.
Various modes of operation, including an errordisplay mode for trapping both permanent and
'intermittent faults, greatly reduce trouble shooting
time. The console also includes all voltage-monitoring and alarm indicators for the various units, power
control for the system, marginal-checking controls,
and all necessary error and contingency indicators.
COMPLETE PARALLEL OPERATION
The designers of LARC realized that even with
automatic programming some programs must first
be written by hand; and further, that programming
must not be so difficult to understand that the people maintaining these machines cannot interpret the
situation when trying to locate a fault. For these
reasons, all of the parallel time-saving features built
into LARC were done in a way that would require
the minimum of planning on the part of the programmer and would be as similar as possible to his
present programming techniques. Therefore, in our
system design we have been consistent with the
straightforward electronic and mechnical designs
employed. Table I shows a list of the equipment in
simultaneous operation in a maximum LARC system.
Supervisory control of the LARC system is
achieved through the use of the LARC Operator's
Console and the LARC Engineer's Control Console.
Fig. 9 shows an operating console to the left and an
an engineering console to the right. The LARC
Operator's Console includes a decimal display unit,
an automatic typewriter, and an input keyboard.
This console is designed for the utmost simplicity
TABLE I
of operation and includes only the manual-intervenCOMPLETE PARALLEL OPERATION IN LARC
tion and start and stop buttons. Certain signals
from the on-line apparatus are also displayed where (A list of equipment in simultaneous operation in an
operator attention is required.
expanded LARC system)
The LARC Engineer's Control Console includes a
1. Input-output equipment
replica of the Operator's Console and in addition,
Read from 3 drum units
all necessary equipment for the monitoring and conWrite on 2 drum units
trol of all of the LARC units. A special feature of
54
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
Position drum head assemblies
Read from 2 tape units
Write on 2 tape units
Position a tape unit or check read a tape unit
Rewind all tape units as required
Print on 2 line printers
Record on electronic page recorder
Print on console printer
Read fast card reader
Operate decimal display unit
2. Computers
Compute on data by 2 computing units
Edit or compute on input-output data and
control on-line equipment by input-output
Processor
3. Operation of instructions in computing unit
Different parts of five consecutive instructions
are performed at once.
4. Decimal arithmetic
50-bit parallel self-checking arithmetic circuits
5. Automatic checking
During operation of instruction examine for
possibility of tracing, programmer making a
mistake, and computer making a mistake.
Without exception, we have obtained overall system speed without resorting to difficult programming tricks such as might require a knowledge of
the detailed timing of the machine and the setting
up of complicated interlaced patterns of data and
instructions. There are many examples of the point
we are trying to make here. The memory organization is one of the best examples. At the time the
LARC was conceived we decided to have a very fast
core memory (one-microsecond cycle time) in combination with a much larger somewhat slower core
memory (four-microsecond cycle time).
Our first thinking on how to use these two memories was to take all information out of the slower
memory and put it in the faster memory - instructions, operands, index numbers, etc. Computing
would then be carried out almost entirely from this
fast memory. When we were finished, a group of
operation results from the fast memory would be
returned to the slower memory. This idea led to all
kinds of difficulties. First, information must be taken
out of and put back into the smaller fast memory
both rapidly and frequently in most of the problems
studied. The large memory, being four times slower,
would have, to be separated into several parts so
that by a time-interlacing system it could keep pace
with the small memory. In turn the smaller, fast
memory would also have to be broken into at least
two or three parts so that parts could be loaded and
unloaded while another part was in use. In addition,
the fast memory could no longer be a hundred words
or less and still be effective. It would usually have to
be at least one thousand words. Even then, this
complicated process would not work on many problems where the nature of the information coming in
is such that one does not know for a few hundred
words ahead where his next instructions and data
are coming from. Since LARC is a very fast new
machine and will be used in problem areas which
have not been well investigated, we did not feel that
the introduction of such restrictions on the programming would be practical. Less is gained by this
arrangement than one might expect.
Instruction routines are frequently long enough
between transfer instructions that they might just
as well be taken from the slower memory, interlaced
in the same way as would be required to transfer to
the fast memory. Some small loss of time using only
the slower memory can occur when a transfer order
is encountered due to interruption of the interlace
pattern. A similar argument will often hold for
strings of data. Thus the faster memory, except for
accumulator and index registers, does not help the
speed situation much but would be a considerable
program complication. In LARC, however, to facilitate matters still further rather than purely timeslotting all of the memories together to get a high
speed flow of information, we have done this in such
a way that the interrelationship is automatic and
does not have to be programmed. Up to eight onehalf-microsecond subdivisions of the four-microsecond memory cycle are provided for time-slot
operation. The programmer does not have to plan
how to intermix information in order to achieve the
time-slotting necessary to match memory speeds to
the Computer. Because of the time-slot system, the
four-microsecond memory system looks almost like
a one-half-microsecond memory in an overall system
sense.
In this system it is possible for the Computer to
ask for information which is not yet available. This
is because the Computer receives orders ahead of
their execution time in order that circuits have time
to set up without delaying the operation. Since
LARC is to achieve its speed without the programmer's being required to give attention to timing
problems occasioned by parallel operation, special
circuits accommodate the situation when inconsistent
logical demands occur. These circuits very rarely
delay computation in actual operation.
When two computing units are used in a LARC
system, the common memory system allows either
separate operation of the units or, alternately, any
degree of interplay desired. A common memory system and certain common instructions provide the
means of interrelating operation. To handle the
priority problem involved in the parallel operation
of many different units, the memory units give pref-
Eckert, Chu, Tonik, and Schmitt: Design of Univac-LARC System: I
erence first to the input-output synchronizers, then
the Processor, and finally the computing unit.
One kind of parallelism not commonly thought of as
parallelism occurs with LARC's one-microsecond
decimal self-checking adder. Clearly, we could convert input data into binary form and checking could
be done by program. These extra operations take
additional time as well as additional programming
effort. In LARC's decimal-checking adder these
operations are effectively combined in parallel with
the arithmetic operation. A binary unchecked adder
would have to be considerably faster to equal the
speed of LARC's decimal-checking adder. The adder
is normally used as part of a sequence in which an
instruction is obtained and corrected as necessary by
an index register, operands are obtained, exponents
are sensed, numbers are shifted as necessary, the
sum is obtained, and finally the sum and new exponents are put in an arithmetic register. All of these
65
operations take place in a four-microsecond interval.
LARC does not expect the programmer to take
care of such timing and interlocking problems.
Parallelism has been obtained in a system that does
not reduce flexibility or require advanced programming technology.
We feel that LARC is a very important step forward in system design in that all of its units are in
balance both in regard to speed, reliability, and cost
for the present state of the art. Sufficient flexibility
has been designed so that as new auxiliary equipment
is developed, it can be effectively added to the
system. Univac I was a better-balanced system than
any other computer of its era. This statement has
never been challenged. The LARC system is similarly
well balanced.
DISCUSSION
See "Design of Univac-LARC System: II."
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
66
Design of U nivac®- LARC System: II
H. LUKOFFt, L. ,M. SPANDORFERt,
HE engineering design of the LARC solid-state
computer was a monumental challenge.
The initial job in the LARC development program
consisted of determining the type of circuitry and
logic that would meet the speed requirements, which
called for a decimal self-checking adder which could
add two II-digit numbers in 1 microsecond and
multiply them in 8 microseconds. The basic machine
timing was determined by the multiplication instruction' it requires 11 additions of partial products,
seve~al cycles devoted to the generation of multiples
of the multiplicand and a few more cycles for handling
signs and transfer of results to a register. Sixteen
operations have to be accomplished in 8 microsecond~;
thus the basic repetition rate is 2 megacycles or, In
other terms, information must be capable of entering
the arithmetic circuits every half microsecond.
We realized that the circuitry had to be faster than
anything then devised in order to meet thes~ speed
specifications. A program w~s set up .to ~on~Ider all
conceivable variations of solId-state CIrcuIts In order
to select the best circuit. Our definition of "best
circuit" was primarily based on a figure-of-merit
formula given in Fig. 1. The formula is based on the
following considerations: The more drives or output a
circuit has, the more logically useful it is. Similarly,
the more logical levels included within the circuitry,
the better it is. In particular, an AND/OR circuit is
logically more powerful than an OR circuit by itself.
AND
F. F. LEEt
+12
T
Figure of Merit
=
(Drives) (logic levels) (Repetition Rate)
(Transit Time) (Cost)
4534-RI
Fig. 1.
On the other hand, the greater the transit time
(electrical delay plus a portion of the rise ~ime) the
poorer the circuit. Also, the ~um~er of tImes the
circuit can be used per second IS an Important factor
that determines how many will be needed for a given
task. A circuit having a long recovery time, such as
a blocking oscillator, would be poor. Finally, the
lower the cost of the components, the greater the
figure of merit. Reliability is also reflected into the
figure of merit through the cost factor. In general,
the lower the cost, the fewer the components involved
and the greater the reliability. As a first approximation, all factors in the equation are assumed equally
weighted, but it should be remembered that low
tRemington-Rand Univac Div., Sperry-Rand Corp., Phila., Pa.
R3
CI
I NPUTS
[n--.....~'---+-.....JVV\r--4--+:-....~.........
--a OUTPUT
R4
RI
-It
-3
4530
Fig. 2-Baslc high-speed circuit.
transit time per logical level was what was wanted
most but not at too high a price for the amount of
equi;ment involved. If for some reason one factor is
considered more important than another it can have
a multiplier or exponent applied. On this basis the
circuit shown in Fig. 2 was selected. If the figure of
merit is normalized at 100 for the circuit selected, it
may be compared to others, such as the DCTL with
2.8 or the transistor-transformer combination having
a figure of merit of 4.1, or a circuit similar .to Fig. ?
with a feedback diode to prevent saturation. ThIS
latter combination produced a figure of merit of
52.5. The circuit in Fig. 2 is recognized as a basic
AND inverter or OR inverter circuit. The surfacebarrier transistor was selected for use with this basic
LARC cirCUIt because it was the only high-speed
transistor that was reliable and in mass production
at the time of circuit design.
Diodes are used to perform logical operations, and
transistors perform the negating and amplifying
function. The same diode network acts either as an
AND circuit or an OR circuit, depending upon the
polarity of the incoming signal. When use? as an
AND circuit, all inputs must be low (- 3v) In order
for the transistor to turn on. When used as an OR
circuit, any input going high (On) will act to turn
the transistor off. The transistor is operated into
saturation and at cutoff; therefore, the output swings
from - 3 to approximately 0 volts, and is directly
coupled to the next circuit. Effective switching occurs
during the first Y2 volt of the transition. The resistor
network Rl , R2 , and R3 provides the proper trans.
formation of DC levels to the base of the transIstor.
The capacitor, C 1, acts to ,supply extra current i~
initially turning the transistor either on or off. R4 IS
used to provide a minimum load on the circuit, to
limit the storage time of the transi .. tor, and also to
Lukojf, Spandorfer and Lee: Design of Univac-LARC System: II
provide current for discharging the stray capacitance.
The circuit is designed to accept a fan-in of as many
as 13 inputs and is capable of providing 3 full drives
output. However, with the use of mutual exclusion
(load sharing) it may fan out to several additional
places. The maximum output capacity allowed for
this circuit is 80 J.l.J.I.f.
. Now let us consider how the basic circuit is used
to perform logic in LARC. The circuits are used in
cascade, so that they form an AND/OR, AND/OR, etc.,
chain. Ideally, it would be desirable to continue in this
fashion. However, pulse timing becomes inaccurate
and therefore retiming must occur in certain places.
This is accomplished by means of the pulse-former
circuit shown in Fig. 3. This circuit permits a logical
operation to be performed at its input. The first
transistor stage operates a gating network which
then selects either a positive or negative timing pulse
(90 mJ.l.s. wide) to set or reset the following flip-flop
combination. The flip-flop can only be set or reset at
precisely-timed one-half microsecond intervals. A
chain of logic is depicted in Fig. 4. The sequence is
started when pulse-former 1 initiates a transition at
one of the timed intervals. The wavefront progresses
through the chain of AND JOR circuits where the
necessary logical operations take place. The maximum
transit time per circuit under worst-case conditions
is forty millimicroseconds. Allowing for 9 levels of
logic, the wavefront arrives at the timing gate of
the second pulse-former 360 millimicroseconds after
it leaves the firs.t pulse-former. Since the timing pulse
at the second pulse-former is scheduled to arrive in
500 millimicroseconds, the difference of 140 milli-tp
4531
Fig. 3-Pulseformer.
I
05 j-Lsec
f - - - - - - - - - 9 LEVELS
....
I ..
- - - - - - - - -..
t1
4532
Fig. 4-Logical chain.
67
microseconds is allowed for timing pulse jitter, pulseformer operation and safety factor. Under normal
operating conditions the average propagation time
of the signal has been found to be 20 millimicroseconds. Thus there is a very large factor of safety in
the circuit timing. The circuit transit time corresponds to 25 megacycles. If less than 6.6 levels of
logic are employed between pulse-formers, there is
the danger of the signal's propagating too fast and
arriving at the pulse-former before the previous
clock pulse has disappeared. To prevent this, it is
necessary to add sufficient delay elements to pad the
chain to minimum delay levels. Padding delay has
been required in fewer than 10 per cent of the logical
chains.
In addition to the basic logical circuit, the pulseformer, and the delay element already mentioned,
there are several other high-speed circuits. One is a
high-power amplifier capable of producing about 10
times as much current output as the basic circuit
which can therefore drive 32 basic circuits. However,
this circuit pays for its extra output by consuming 3
levels of delay. Another useful circuit is a scaled-down
basic circuit to operate at ~ the power level. Thus,
one of the basic circuits can drive 9 of the lower-level
circuits. The lower-level circuit, however, consumes
1.6 delay levels. The last useful high-speed element
is the high-power amplifier coupled with the pulse
former to form a high-power pulse-former.
The fact tha t LARC circuitry is clocked allows the
use of what is called the "pulse-envelope system," or
more familarly, "non-return-to-zero" (NRZ) logic.
If direct-coupled circuitry is used in asynchronous
circuits with NRZ logic, two difficulties appear.
Either the length of delay through all logical paths
must be predicted and be reasonably constant, or a
signal from a circuit must be derived to tell when the
logic in a chain has been completed. If the former
method is used in a parallel computer, there is no
advantage over the clocked system.
In the arithmetic circuits, for example, many
logical paths operate in parallel. Therefore, if a delay
element is to signal when the last of the data has
come through, it must have a delay equal to the
clock-pulse spacing in a synchronous machine. On
the other hand, if the signal itself is used to tell when
an operation is completed, there is the problem of
discriminating between a normal signal and the
"spikes" (switching transients). Thi8 is because a
gate with one input being turned on at the same time
another input is being turned off will, for a finite
signal rise-time, allow a spike to come through, as
shown in Figs. 5a and 5b.
N ow if a return-to-zero or regular pulse system is
used there is always a dead space between signals.
All signals return to zero during this dead interval
and avoid the spike problem. However, the speed at
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
68
INPUT A 0
TO GATE _ _
-~
INPUT B
TO GATE
GATE
OUTPUT
o
01)
o
-4l-----+-TRUE SIGNALS
I
OUTPUT FROM
CHAIN OF NRZ
LOGIC
1
TIMING
PULSES
PULSEFORMER
INPUT TO
NEXT CHAIN
4536
Fig. 5(a)-"Spike" formed due to overlap of gating signals. 5(b)Discrimination against "spikes" occurring in a NRZ system
using clocking methods.
which pulses can now be put through the circuit (for
equal rise and fall time) will be halved because of
twice the number of transistions. Since LARC transistor circuit delays are quite stable, less than a
two-to-one timing margin is allowed in the clocked
circuits. Thus the necessity of using return-to-zero
signals would decrease the data rate by more than
asynchronous operation would increase it.
Asynchronous operation not only requires more
equipment and has no apparent speed advantage, but
makes testing and maintenance more difficult, since
no definite points to trigger an oscilloscope can be
found: timing depends on actual circuit parameters
and the actual signals present.
A large number of logical configurations involving
adders, complementers, and other devices were
examined. Methods of multiplication and division
were chosen carefully, not just on the basis of speed,
but the circuits were examined to find out how many
drives an individual element need provide so that an
overall minimization of the speed through a chain of
these elements might be made. Since the product of
current gain times the band width for a given transistor is normally constant, it is possible to estimate
the delay through a network, given the nu~ber of
drives required at each level.
/
With a simple fan-out network, this optimum
occurs with three drives; however, there is no assurance that this is the optimum for an adder network.
Although it was suspected that the same limitations
were probably true in actual circuits, many circuits
were carefully laid out and it was shown that not
only were three drives adequate, but such an arrange-
ment provided the optimum speed. Further, the
current gain of the surface-barrier transistors is low
and made more drives undesirable. With high-speed
mesa transistors now becoming available, LARC
speeds could have been achieved with circuits that
allowed more drives. Thus fewer transistors would
be required in the circuit. Studies show that perhaps
15 per cent to 20 per cent of the transistors might be
eliminated in this way. Nevertheless, if the objective
is to obtain optimum speed out of the newer mesa
transistors,indirect-coupledcircuitry,useofthepresent
design based on three drives would still be applicable.
Since many, many thousands of high-speed circuits
are employed in the machine, it is obvious that the
packaging is an extremely important consideration;
otherwise wire lengths become too great and exceed
the 80 fJ.}.d circuit allowance. Also, crosstalk problems
could become severe with longer lead lengths. A
study and optimization program showed that it was
necessary to compromise at a maximum of ten circuits per printed-circuit card. This was a compromise
between achieving efficient packing densi ties and
minimizing the number of different card types. Larger
numbers of circuits per card provide higher packaging efficiencies because DC voltages and clock lines
utilize a smaller total number of backboard contacts.
A successful solution to the basic and conflicting
problems of circuit speed and capacitance and crosstalk minimization was largely achieved by tAe development of a special connector, which provided a large
number of connections with the smallest possible
backboard area. Fig. 6 is a photograph of a typical
LARC printed-circuit card. The connector which is
affixed to the end of the card has 42 through connections in it, in addition to the guide pins which also
carry through the ground connection. Connectors are
held to the printed circuit board by means of a metal
framework around the card, which also acts to eliminate any problems with card misalignment or
warpage. The back half of the card nearest the connector contains five circuits. The other half contains
five additional circuits. Test terminals are electrically
connected to the outputs of each one of the ten circuits. The seven basic circuits are used with different
configurations of input diodes. This results in a total
of 30 different types of high-speed cards. Spare diodes
and transistors are removed where not needed, for
economic reasons. Spare cards used for maintenance
Fig. 6.
LukoiJ, Spand,orjer 'and Lee: Design of Univac-LARC System: II
69
purposes have all diodes and transistors in place. Card
dimensions are approximately 3Y2" by 9". This shape
was chosen to obtain the necessary volume for housing the components. Female contacts are used on the
card connector so that there is no possibility of
damage which might occur if male contacts had been
used. The wires observed on the package serve the
function of providing connection between the floating female contacts and the printed circuit wiring.
Lower stray capacitances are also achieved and
input-output printed-circuit wire bottlenecking: is
reduced. The male connectors are packaged extremely close in the basic modules which go together
to form the backboard. Fig. 7 is a photograph of a
module backboard before wiring. The degree of packing efficiency is very high when it is realized that 88
per cent of the backboard wiring area is composed of
connectors. As a consequence of this, and the close
packing of contacts, there are over 6000 wire terminations per square foot. Reducing the backboard area
in this way has allowed the use of wires sufficiently
short so that no special line-driving elements are
necessary. It was necessary to leave small spaces
(30 mils) between connectors to permit a small
amount of air flow for cooling purposes. All wiring
on the backboard is done with taper pins. With this
high a wiring density, as shown in Fig. 8, it becomes
impractical to consider soldered or wire-wrapped
connections. The connectors are color coded to make
the job of terminal identification much easier for the
wiremen. Each terminal on the connector is bifurcated and appears as two taper-pin holes so that it
is possible to propagate the chains of wires without
using auxiliary tie-points. The wiring is extremely
dense and piles up to a depth of several inches over
most of the backboard. Throughout the development phases of the program, accessibility to the
backboard was a matter of gravest concern, since it
was impossible to accurately predict or simulate
actual backboard wiring buildup. We have since
installed many thousands of wiring changes and have
fully proven that the wiring technique is indeed
practical. We have developed new technology and
new tools for working with this new high wiring
density. Fig. 9 is a photograph of special tools, which
Fig. 7.
Fig. 9.
Fig. 8.
70
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
include long armed taper pin inserters and extractors,
pin point light sources, and a "Borescope," originally
developed for examining the inside of a gun barrel,
but proven effective for penetrating the mass of
backboard wire and giving the wiremen a close-up
view of the connector.
In order to reduce the congestion on the backboard, very fine steel-core copper wire was used with
a thin teflon insulation. The physical strength of size
30 steel-core wire is approximately equal to copper
wire of twice the cross sectional area. Reduction in
wire size not only helped to reduce congestion but
also produced a necessary reduction in the stray
wiring capacitance.
One of the more serious problems that could occur
with many thousands of transistor circuits operating
simultaneously is that of crosstalk and other noises
being coupled into the transistor circuits. Crosstalk
effects were calculated as much as was possible and
further experimentally checked in the laboratory.
To prevent crosstalk due to coupling between backboard wires, twisted pair is used for any wire lengths
greater than about nine inches. Although tests indicate that twice this length could be used under worst
tolerance conditions, approximately 23 per cent of the
backboard wires are twisted pair. The twisted pair is
composed of very fine steel-core teflon-insulated wires
with a capacitance of 8 to 9 M.d per foot. A network
of taper-pin ground straps is provided at each Y2-inch
interval over the entire backboard to form a ground
plane. The twisted-pair ground wires terminate at
these ground straps. All framework elements of the
module carrying ground currents are gold-plated so
that the contact resistance between abutting structural members is low and stable over a long period of
time, despite atmospheric conditions. Common coupling on the DC voltage lines is minimized by the use
of very wide strip transmission lines having extremely
low impedances. Strip transmission lines are mounted
in vertical columns behind the backboard. These lines
have an impedance in the region of 30 milliohms (.03
ohms). Timing-pulse signals to pulse-formers are also
a vailable on similar strip transmission lines.
Usually, three DC voltages are distributed to the
printed-circuit packages through the strip transmission lines. Up to 6 voltages are available for other
miscellaneous card types.
The task of laying out the backboard wiring and
positioning the various circuits in such a way as to
avoid too much wiring load on anyone circuit, as
well as the problem of keeping an inventory of all
circuit cards, would have been impractical had this
not been accomplished by processing the data on a
Univac® data-processing system. Thrity-five different
categories of information, as well as complete
production-wiring tables, were generated by the
Univac system to supply necessary information for
production, maintenance, manufacturing inventory,
and engineering test of LARC. For example, printouts were obtained on wires sorted by lengths,
potentially bad cases of stray capacity or crosstalk,
spare diode and circuit positions, ehecks on certain
types of logical errors, and general data vital for
testing and maintenance. All logical revisions which
were made during the test period were handled in
this automated and systematic manner.
The automated backboard program guaranteed
that wiring changes could be made without fear of
overlooking any of the myriad of details involved in
the change. Fig. 10 shows one page of a printout of
the backboard wiring table.
Solid-state power supplies are used throughout the
system. Each cabinet has its own set of power supplies and controls, so that lead lengths between card
library and power supply can be kept to a minimum.
The lead impedances between power supplies and the
card library are kept low by the use of bus bars with
electrolytic filter-capacitors distributed along the
length of the bars. The supplies are all voltageregulated, either by shunt transistor regulators
or, in the case of the very high current supplies,
transistor-driven magnetic amplifiers. The size, cost
and time of response of the power supplies have been
reduced by the use of 400-cycle 3-phase input power
derived from a motor-alternator set. The motoralternator also has the advantage of providing complete line isolation and will produce full putput even
though power line "dropouts" occur for as long as 3
seconds. The power supply design has proven extremely reliable, with voltage regulation much better
than the specified 2 per cent.
A major virtue of the circuitry, not found in many
high-speed computer circuits, is its adaptability to a
simple and effective marginal-checking system. Varying the collector-return voltage has proven to be an
effective way of determining the beta margins of the
circuit. Fig. 11 is an actual plot, showing how the
15
13
MIN
NEW
f3
11
MIN
DESIGN
9
f3
f3
7
FAILURE IN
COMPUTER
5
3
1
0
-1
-6
4533
Fig. ll-Circuit failure as a function of Vc c and {3.
71
LukojJ, SpandorJer and Lee: Design of Univac-LARC System: II
wIRING TABLE FOR LARC COMPUTING UNIT
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Fig. 10.
collector-return voltage may be varied to determine are composed of fast-switching tape-wound cores
the beta margin, which is perhaps one of the most having a read-regenerate or clear-write cycle of 1
variable and critical of the transistor parameters. microsecond. The fast-register core consists of 4
The extremely difficult problem of switching indi- wraps of Ys mil thick, >3'2 wide, 4-79 molybdenum
vidual portions of the very low-impedance voltage- permalloy tape on a 50-mil diameter stainless-steel
distribution system has been avoided by varying the bobbin and has a read, a write, and an output windvoltage over the whole unit rather than in a given ing. The register uses one core and diode per bit and
area. The location of a weak circuit is indicated is organized on a word-selected basis. As employed
logically, by error detecting circuits which are located in the Computing Unit, information write-in or readat strategic points throughout the logic of the out is done in 50-bit parallel form. Fig. 12 is a photomachine. Thus almost no equipment not already graph of a fast-register package. The cores and diodes
present for continuous checking is necessary to pro- are contained in the small rectangular boxes and are
vide very effective marginal checking. An overall
marginal check can be performed simply by flipping
a switch at the engineer's console while an engineering-test routine is being run on the unit. A
comprehensive voltage-monitoring system is used
to detect the fact that a particular power-supply
voltage is drifting out of tolerance. This fact causes
visual and audible indications ~efore a voltage drifts
far enough out of tolerance to cause actual errors. The
voltage monitor makes use of solid-state elements.
The Computing Unit and Processor are each supplied with a system of fast magnetic registers which
Fig. 12.
72
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
arranged in a 26 X 30 array. Two of these packages
are used to form 26 registers of 60-bit storage. More
of these packages may be plugged into the Computing
Unit to make available a maximum of 99 registers
that can be used interchangeably for indexing or
arithmetic operations.
To carry out the logical operations in parallel
fashion, large quantitites of circuits are required.
To present some idea of ,magnitude, a few of the
statistics will be listed: 8800 printed circuit cards
are used in the basic system, with approximately
3700 in the Computing Unit, 3200 in the Processor
and 1800 in the memory. This represents a total of
62,000 transistors in the entire typical system, with
approximately 57,000 of them being surface-barrier
transistors. 28,000 transistors are used in the Computing Unit alone. The number of logical diodes in
the system is approximately 2.8 times the number
of transistors. 75,000 wires are used on the backboard
of the Computing Unit.
With these large quantities of components used in
the system, it is quite obvious that reliability is a
major problem and, therefore, a big part of the
LARC development program was concerned with
component reliability. Many of the basic component
selections were made on the basis of reliability rather
than cost. All components used in the system were
subjected to extensive reliability tests. The resistors
used in the circuitry, for example, are of the 72 watt
size, even though circuit dissipation is in the milliwatt region. The 72 watt resistor available at the
start of the project proved to be much superior to
the smaller wattage sizes. A large engineering effort
was required to achieve the high reliability obtained
in the LARC printed-circuit card connector. The
contact pressures are accurately designed to be in the
4- to 6-ounce range per contact. The use of electropolishing and 200 micro-inches of gold permits the
connector to be withdrawn and inserted 400 times
while still retaining gold both on the male and female
contact area. This is an important point, in view of
the low voltage and current levels encountered. All
circuits are designed to work under worst-tolerance
conditions assuming 4 per cent variation in DC supply
voltages, a 3-per cent variation in the value of the
resistors, and the end-of-life transistor beta. Three
units of beta over the end-of-life beta required are
specified for new transistors. For example, for a
transistor driving 3 loads, an old-age beta of 9 is
required; a transistor with a beta of 12 minimum is
initially inserted in the circuit. Under nominal tolerance conditions, the circuit will function even if the
beta drops to 6. The most pessimistic calculations of
reliability have predicted a mean-error-free time of at
least 11 hours, which is 3 hours beyond that called for
by the specifications. Typical power requirements of
the system are 15 KV A of 400-cycle power for the
Computing Unit, 56 KV A for each memory unit, and
18 KVA for the Processor. The power factor is .5
because of the type of regulated power supplies employed. Most of this power is actually dissipated
within the power supplies.
Each unit of the system has its own cooling equipment built into the base of the unit. A heat exchange
and blower system circulate 75°F maximum-temperature air up the backboard and through the card
library; the air then returns through the front side
of the machine to the base area, thus forming a
closed-circuit path. The circuits will operate over a
much wider temperature range, but internal cooling
is used to guarantee long life and reliability. Operation is reliable over a room temperature range of 32
to 110°F.
The LARC system is being readied for the customer acceptance test. All units of th e system are
functioning. The Computing Unit, in conjunction
with the memory, has been running test routines for
many months. Although the overall long-term
reliability data on the system is not yet available,
preliminary information is very satisfactory. Runs
of about 12 hours have yielded one or no intermittent
errors. Fortunately, the very few failures encountered
thus far have been of the catastrophic variety, such
as open or shorted components (probably due to
abuse during testing) rather than a change in parameter value which leads to marginal opel'ation and
accompanying difficulty in isolation. It is extremely
gratifying that no circuit redesign of any sort has been
found necessary since the commencement of test.
This has led to an unusually rapid testing of the
overall system. The efforts put into very thorough
engineering beforehand have paid off handsomely.
Many people were involved in making the LARC
program a success, and it would be impossible to list
them all by name. Recognition must be granted to
all of them for their part in this major engineering
achievement.
DISCUSSION
S. Levine (Teleregister): What is the expected LARC reliability: i.e.,
mean free time to failure, fault location time, mean repair time of
main processor and sub-systems? What size of maintenance crew do
you expect to require for a typical installation operating 24 hours a
day, seven days a week?
Mr. Lukoff: Well, we have calculated the mean free error time using
reliability figures provided to us by our component engineering
groups and by Bell Telephone, RCA, and so on. The mean free error
time is predicted as at least 11 hours which is three hours beyond that
called for in the LARC contract specifications, which ask for an eighthour mean free error time.
Mr. Eckert: The few runs we have made so far are better than this
W~ have made a few runs of 12 hours during the course of system
testing, and it has actually been ~better than this. We haven't run
enough to know the ultimate mean free time to failure.
Mr. Lukoff: The repair time on a card would be, say, two minutes to
replace a diode or transistor. We have automatic package-checking
equipment that checks the package under dynamic operating conditions. It measures the transit time to within 3 millimicroseconds and
Lukojf, SpandorJer and Lee: Design oj Univac-LARC System: II
pretty well down to the component that has to be replaced. This can
be done very rapidly. We have a supply of spare parts the maintenance man is furnished with. He would, of cours~, replace the defective package in the machine with a good spare package and make the
repair on the bench.
We are presently in the process of developing and refining the
LARC maintenance procedures. However, we believe that maintenance will be easier than with any other machine we have built thus
far because of the packaging techniques, and because of the large
amount of checking which permits logical isolation of the circuit.
On the maintenance crew I would expect it to be of the same order
of magnitude as it is for any other computer in the field.
73
J. Katz (GE): How many wiring mistakes in the backboard were
traceable to malfunctions in the data processing program?
Mr. Lukoff: None.
Mr. Eckert: Most of the wiring errors we found in the backboard were
either production errors or due to logical design errors. There were
lots of errors, but there have been on every machine I have seen.
W. C. Mann (Westinghouse): About what percentage of the backboard connections are used?
Mr. Lukoff: It is very high. I don't remember the exact figure, but it
is in the order of 75 percent.
J. Capobianco (Hughes): What type of logic diode was used? What
are its transient specifications?
Mr. Eckert: As far as correcting errors, these logical errors, that is the
reason for the long handled tongs.
Mr. Lukoff: The diode is a point-contact diode selected for its high
speed capabilities. Also, the forward drop was an important consideration in the direct coupled circuitry. I don't remember the exact
specification for speed but it is a fast diode.
G. A. Sellers (Bell Labs.): Please repeat the characteristics of the
high-speed microfilm printer. Is it going to be commercially available?
Mr. Eckert: It is about two or three times faster than the usual runof-the-mill gold bonded diode. Actually we have two types of diodes,
gold bonded and plated tungsten. We have four or five different suppliers who could make such a diode. It is a better diode than the one
you go out and buy over the counter. It is one manufactured for well
under a dollar.
Mr. Eckert: Yes, it is commercially available. It prints at 20,000 characters a second. I think you can produce it on a polaroid, too, if you
want a single frame and print points at this speed. It could print at a
somewhat higher speed, but we didn't choose to. So it makes a good
plotter.
F. F. Jenny (IBM): How do you differentiate between errors in the
error detection system and the operational system?
V. Enstein (Brooks Research): What method of switching is used to Mr. Lukoff: The error detection circuits are not distinguished from
switch between the various drums? What significance is attached to the computer circuits proper. Nobody watches the watcher. A detected solid error is to be repaired regardless of source. We ignore the
the two different chairs for the operator and the engineer?
possibility of a double failure over a short time period and employ
Mr. Lukoff: Purely esthetic, in answer to the second question. In error generating routines periodically to check the operation of the
answer to the first, we use relay switching cabinets.
check circuitry. In some cases error insert switches have been proMr. Eckert: We have plenty of time to switch because you are really vided where input/output equipment is involved.
stripping one drum while you are reeling off the other.
Mr. Eckert: The machine doesn't necessarily stop when it makes an
Mrs. J. Schot (D. Taylor Model Basin): What is the maximum reli- error. It is rigged up so it can go into a routine and try something
able pulse density of the LARC tape units? In other words, is it pos- over with different conditions. After a certain number of times, it
finally stops. When you have an intermittent error the frequency may
sible to store two drum loads on one reel of tape?
become high enough that you want to service it.
Mr. Eckert: We are using standard Univac, which packs 250 to the
inch. We have experimental tape which goes much higher. As I said, T. Digan (IBM): How do you marginal check the 170,000 diodes?
we will put either these tape units or competitive tape units on the Mr. Lukoff: The diodes are marginally checked along with the rest of
machine to suit the customer.
the circuits. There is just one marginal check test of circuits, not
G. Neuman (Magnavox): With the large number of transistors used, able to find if the transistors are low or voltages are out of tolerance
what percentage of rejects did you have in construction?
or high drop in the diode or the diodes become slow.
Mr. Eckert: You see, we are satisfied to find out which group of circuits the fault is located in. Then we find out within three diodes or
Mr. Lukoff: We knew we would have about 6 percent rejection on two resistors which is bad. It is an overall clump test, so to speak.
transistors because we bought the complete line of transistors from
the manufacturer, and we knew some would not meet our specifica- Mr. Thomas (MH): What automatic programming systems are
available or planned for LARC? Do they include special features to
tions.
aid in the effective simultaneous use of the several computing units?
~fr. Eckert: We buy transistors to normal specifications and buy
everything on the line and then throw out about 6 percent due to low Mr. Lukoff: At the present time we are planning a complete assembly
current. Again this is no problem.
system and a 00mpiler system for LARC to use the argollanguage.
There will probably be more automatic program work done in the
D. Hammel (RCA): What are the possibilities of a third computer future although we can't say much about this at the moment.
operating in the LARC system?
T. Gilmer (ITT Federal): You have indicated an unusually short time
Mr. Eckert: That is easy. It is not designed for it. It doesn't have in test for LARC. Can you give an indication of the elapsed time
and the number of crews working?
enough time slots.
Mr. Eckert: About 10 percent, wasn't it?
P. J. Scola (GE): Do you use diagnostic programs? What percentage
of the faults do they find? Average time to locate fault?
}Jr. Lukoff: We can only partly answer by saying we definitely plan
to use diagnostic programs but have not had the opportunity to fully
explore th,eir potential in the computer yet.
Mr. Eckert: I suspect you could ask Mr. Tonik after the conference
session.
M. Sendrow (RCA): Is there any way of loading the drums from any
external media? If so, what media and how?
Mr. Eckert: Yes, they can be loaded from tape units, by punch cards,
card readers, through the core memory. You could, if you wanted,
from keyboards, but it would take all your life.
Mr. Lukoff: The processor unit, which was the last one to go into test,
has been in test for approximately five or six months, and it is just
about completed. I think this is very, very short for the number of
circuits involved and for the complexity of the machine.
Mr. Eckert: This is done on three shifts, and, of course, some shifts
are missed now and then for holidays and other reasons.
M. Relis (Curtiss-Wright): What transistor is used in the gateinverter?
Mr. Eckert: Philco surface barrier transistor, although it:differs in
that a slightly lower resistivity and a slightly different size of germanium is used. Other than that it is a regular SBT transistor.
74
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
G. E. Saltus (BTL): What maximum logical fan-out and fan-in are
allowed in the basic circuit?
Mr. Lukoff: A maximum of 13 fan-in for basic circuits and a fan-out
of 3 but more places are sometimes allowed because of load-sharing.
Mr. Eckert: You hook up to 10 in some cases, but it only drives 3 due
to mutual-exclusion. There are some places where you could get more
load by taking the dummy load transistor off. We do that only in
the memory.
P. W. Core (IBM): Can both arithmetic computers perform operations in the times quoted simultaneously?
J. E. Veal (RCA): What is the figure of merit of the diode-core
registers as compared to your figure of merit for other circuits in the
memories?
Mr. Eckert: We didn't design the core register by a figure of merit.
We considered several types, and this was the only type we knew
how to build. We knew of others, but the development time was long,
so they were thrown out.
Miss H. Bein (Philco): What do you mean by a LARC system with
2 computers? Would they be handling different programs and sharing
one memory and data processor?
Mr. Eckert: They would share one memory bank, but don't forget a
memory bank can have up to 39 functionally independent 2500-word
R. Adams (DAT Amatic): Are there any further requirements for other units in it.
than twisted pair for those over 9 inches? Specifically I am thinking Miss R. Pitche (Northeastern Univ. student): Do you use a parity bit?
of termination requirements or coaxial runs.
If so, how?
Mr. Eckert: Yes.
Mr. Lukoff: There are no terminations required within the main
units, but there is still a maximum length; that is, we must not
exceed the micro-microfared capacity units. You can't allow longer
wirelength for a circuit to drive or else it will take more than its
allotted delay level.
Mr. Eckert: Well, there are extensive uses of parity bits. They are on
the tape unit. The code is carefully chosen to cut down the errors.
There are parities all over the place.
Mr. Eckert: Actually we computed - we had to compute - everything twisted above 15. We actually twisted everything over 9 inches,
and it amounted to 30 percent of the wire.
Mr. Eckert: The number of time slots and the needs we saw.
E. Morenoff (RADC): What factors limit the number of computing
units to 2?
M. Lavel: Are there any tubes used in the LARC?
E. L. Lawler: Was the program for backboard wiring primarily for
record keeping or was some attempt made to optimize the location
of the packages and the interconnections between them?
Mr. Eckert: Yes, to get the fairly sizable clock powers. At the time
we designed there weren't suitable transistors, but they probably
exist now.
Mr. Eckert: For both of those and also the calculation of loads and
various other things. In· the inventory class alone there were 35
different types of lists needed.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
75
Arithmetic and Control Techniques in a
Multiprogram Computer
N. LOURIEt, H. SCHRIMPFt, R. REACHt, AND W. KAHNt
N THE DESIGN of a data processor for commercial applications, the designer is very often
striving for better machine performance for little
or no increase in cost. In the system design of the
Honeywell 800 transistorized data processing system, several design concepts were utilized to help
achieve this objective. One of these techniques involves the use of a small auxiliary memory to aid in
the control of the high speed central processor. A
second technique uses a new word organization that
results in a faster and less costly arithmetic element.
In a modern transistorized computer, the speeds
that are economically achievable in the central
processor are very often much higher than necessary
to keep up with peripheral devices. The concept of
time sharing the central processor among sevel'al
programs in order to utilize otherwise wasted time
then becomes attractive. In order to achieve this
time-sharing automatically without the use of
cumbersome supervisory routines, at least one
sequence counter per program is required. If a small
coincident current memory running out of phase
with the main memory were available, a relatively
liberal number of programs could easily be run
simultaneously by assigning these sequence counters
to this control memory. Also, since additional memory locations become economical, it is now simple to
assign each program two sequence counters for
greater flexibility. These are known as the sequence
and consequence counters. The Honeywell 800 has 8
pairs of sequence counters, thus allowing the simultaneous operation of eight independent programs.
I
TABLE 1
{
USE OF CONTROL MEMORY FOR SIMULTANEOUS PROGRAM
ORATION
Program
Sequence
Counter
Location
Cosequence
Counter
Location
1
2
00050
02090
00600
03002
3
0
4
5
6
7
8
0
2
34
66
98
130
162
194
226
3
35
67
99
131
163
195
227
0
0
0
0
0
0
0
0
0
0
To illustrate how this is performed, Table 1 shows a
possible state of the various counters. If, upon startt DATAmatic Division, Minneapolis-Honeywell Regulator Company, Newton, Mass.
ing, the first order is specified from the sequence
counter, 00050 will be read from location 2 of the
control memory, and the contents of 00050 in the
main memory will be read and performed as an
order. The sequence counter will then be incremented
by unity so that 00051 will be immediately reinserted
into address 2 of the cont~rol memory as the location
of the next order to be performed under control of
the sequence counter in program 1. If the previous
order in program 2 specified that the cosequence
counter was to be used to obtain the next order, the
contents of address 35 will then be read out of the
control memory and 03002 will then be used as a
main memory address to select the next order performed. Similarly the computer will then cyclicly
perform one order from each program. Some orders
that leave useful information in the eentral processor do not relinquish control to another program,
so that occasionally, several orders from one program
will occur before any orders from another program
are performed. The multiply order is an example of
an order that requires such treatment since there is
still a low order product that may be required after
the completion of the order. Because the control
memory is running simultaneously but out of phase
with the main memory, this multiple operation not
only is extremely flexible, but is performed without
loss of speed.
Each of the sequence and cosequence counters in
the Honeywell 800 has associated with it in the
control memory another register known as a history
register. Whenever a sequence or a cosequence counter
is modified because of a s~quence change, the associated history register is changed so that it contains
the address that the sequence or cosequence counter
would have contained if there were no sequence
change. With this feature available, the programmer
can easily sequence change into a subroutine and
then, at some later time, revert back to the main
routine. Table 2 gives a numerical example of this
use of a history register.
The same control memory can be extremely useful
for control of information to and from peripheral
devices and the main memory. Eight input registers
and eight output registers have been reserved in the
control memory for controlling the transfer of data
between peripheral devices and main memory. Each
of these control memory registers is uniquely associated with an input or output trunk. When an input
trunk signals that it has a word available, the central
76
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
TABLE 2
USE OF SEQUENCE HISTORY REGISTER TO RELOCATE AFTER
SUBROUTINE
Subroutine [
located
from 01200
to 01280
Sequence
Counter
Sequence
History
Register
00122
00123
01200
01201
00000
00000
00124
00124
01280
00124
00124
01281
processor is interrupted at the end of the next memory cycle. The buffer control register in the control
memory associated with this input trunk is read, and
the contents used to select a main memory address
into which the word from the input trunk can be inserted. The content of the buffer control register is
then incremented by unity and immediately placed
back into the same control memory location. Thus,
the next word from the same input trunk will be inserted into the next highest memory location. In the
case of a reverse tape read order, the content of the
control memory register is decremented by unity
prior to insertion back into the control memory so
that the information from tape will be in correct order
regardless of the direction of tape motion. Similarly,
words are delivered from the main memory to a
peripheral device in the case of a write order.
If more than one trunk is on demand at the same
time, a simple buffer traffic control system establishes
priority, and the trunks are processed one at a time.
After all input and output trunks are processed, the
machine control then reverts back to normal order
processIng.
To increase the average data rate from tape and
improve the utilization of tape space, it is desirable
to place more than one item on a block of tape. When
this is done, it would be desirable to be able to place
each individual item in a different section of the
memory. In order to accomplish this "distributed
reading or writing", a set of address locations that
will serve as the starting locations for each of the
consecutive items after the first item, is inserted into
the main memory. The starting location of this group
of beginning item addresses is placed into a control
memory address called a distributed item counter.
There is one distributed item counter for each input
trunk and each output trunk. As before, when a
block of information is read into the memory, the
initial item is placed into main memory locations as
specified by the associated buffer control register.
However, when a special bit configuration representing an end of item is sensed, the content of the main
memory location as specified by the distributed item
counter is read into the buffer control register, thus
creating a new starting address for the next item. The
distributed item counter is incremented by unity
prior to reinsertion into the control memory, to prepare for the next item. When this change of item
location occurs, one extra memory cycle is required
for all the associated housekeeping. Distributed
wri ting is performed in a similar manner.
A numerical example of the handling of a four-item
block is shown below:
Read Buffer Control Register contains
Distributed Read Item Counter contains
Main-Memory Address 0100 contains
Main Memory Address 00101 contains
Main Memory Address 00102 contains
01400
00100
01500
01600
01700
, With these constants located as shown, the first
item would be placed in consecutive memory address
locations starting with 01400, the second item starting with location 01500, the third item starting with
location 01600, and the fourth item starting with
01700.
Two locations in the control memory are reserved
for each of 'the eight programs to serve as counters
for such orders as multiply and multiple transfer
orders between groups of memory locations.
TO MANPULATIV!
SECTION
I
L - -_ _ _~~~~~
- --":--.TO MAHIPULATIV!
SECTION
Y:
L- _____________________ ..... _____ J
-31 s ns31
-255 s m $255
Fig. I-Control memory in a multiprogram computer.
The control memory also functions as an aid to
indexing addresses. Referring to Fig. 1, the base
address "y" is read out of one of 64 index registers,
eight of which are available for each of the eight programs. An eight-bit augmenter "m" specified by the
order is either added to or subtracted from this base
address to form the indexed address for the main
memory. The base address "y" is reinserted into the
control memory unmodified. One extra memory cycle
time may be required to perform an order if any of the
addresses in that order are indexed.
Indirect addressing is another feature that can
easily be accomplished by use of a control memory.
In this mode of operation, a number "x" is read from
Lourie, Schrimpf, Reach, and Kahn: Arithmetic and Control Techniques
a specified control memory location and used as an
address in the main memory. The number "X" is
incremented by a constant lin" prior to reinsertion
in the control memory, so that next time this control
memory content is used as a main memory address,
a different main memory location will be addressed.'
Thus, with one order it is possible to operate on a
whole series of main memory addresses without the
necessity for order modification.
The control memory also serves to store a constant
U that will give rise to an unprogrammed transfer of
control if special situations such as end of tape, addition overflow, or read error occur. When one of these
situations arises, the constant U is incremented by n,
and an unprogrammed transfer of control to address
U + n occurs. The constant lin" is a function of the
type of situation that calls for the unprogrammed
transfer of control. Since there is an unprogrammed
transfer register for each of the eight programs, eight
independent U constants can be stored.
A mask index register is available for each program, such that anyone of 64 mask constants can
be called out of main memory by using one of the
mask type orders and an incrementing constant.
A summary of the assignment of control memory
locations is shown below:
Address
o
1
2
3
4
5
6
7
8-15
16-27
Description
AU-CU Control Counter No.1
AU-CU Control Counter No. 2
Sequence Counter
Co-Sequence Counter
Sequence History Register
Co-Sequence History Register
Unprogrammed Transfer Register
Mask Index Register
Index Registers 0 through 7
General Purpose and Indirect
Addressing Registers
77
be capable of meeting the speed specifications with a
minimum of hardware. The format of the bits in the
arithmetic unit is an important factor in fulfilling
this objective. Various formats for a 48 bit word are
discussed below.
ADD AND SHIFT
A+B- B
USING 4 MC CLOCK, ADD TIME • 24 MICROSECONDS
<>
CLOCKED
"FLIP FLOP
~'GATE
r-:I
SMALL
U'DELAY
Fig. 2-48-bit serial accumulator.
Serial
A pictorial representation is shown in Fig. 2. In
this arrangement, as well as all others to follow, for
the sake of simplicity it is assumed that the A and
B operand each reside in a 48 bit flip-flop register,
each stage of which is capable of shifting. At the
completion of the addition, the sum will be located
in the B register. Since, the addition is taking place
only one bit at a time, a minimum of equipment is
required. However, in order to achieve a reasonably
fast add time, relatively high speed shifting flip-flops
would be required. For instance, with 4 MC flip-flops,
24 microseconds would be required for a complete
addition with end around carry.
These 28 locations are repeated 8 times so that
each of the eight programs has a unique set of these
registers.
In addition, there are eight each of the following
registers which are associated with input-output.
These registers are not uniquely associated with any
Parallel-Serial
program, but are available for convenient assignment
A pictorial representation of a 48-bit parallel-serial
to any program.
accumulator with 4 bits in parallel and 12 digits in
Description
Address
serial is shown in Fig. 3. Other geometries could be
Read Address Counter
28
used here, but this is a very important one, inasmuch
Distributed Read Address Counter as 4 bits in parallel can be used for a binary coded
29
Write Address Counter
30
decimal digit. Since the adder is now a 4-bit adder
Distributed Write Address
31
instead of a I-bit adder, more time will be required
Counter
to propagate carries, thus resulting in a slower inforWhen the computer designer initially considers the mation shifting rate than in the serial adder. Using
specifications of the arithmetic unit of a digital a 125 millimicrosecond carry propagation per stage
computer, one of the prime considerations is the and a 1.33 MC shifting rate, the add time will be 18
method of performing addition. A good design will microseconds, again including end around carry prop-
78
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
agation. The addition time is not too much faster than up techniques suggested previously are used, average
the example given in the serial adder, but the speed add times on the order of 1 to 2 microseconds are
requirement of the flip-flops is reduced.
feasible, but the increase in the number of logical
statements is substantial. The number of logical
statements required without these speed-up techniques is about 12 times as many as the parallel
serial adder since the full add logic is required for
each of the 48 stages.
Upon examining the requirements of the response
time of any adder stage in the parallel accumulator,
it is noted that although any stage is required to
propagate a carry in a short time, once that stage
has responded, it rests for the remainder of the carry
time, resulting in a very inefficient use of the inherent
speed available. If good speed-up techniques are
used, then this inefficiency is greatly reduced. This
observation then suggests that a parallel accumulator
without speed-up techniques is an extremely wasteful
device. It was this observation that led to the invention of the parallel-serial-parallel accumulator. The
parallel-serial-parallel accumulator is an efficient
extension of the parallel-serial accumulator which
results in speeds comparable with that of a parallel
accumulator with no speed-up techniques, but with
approximately one-fourth the number of logical
inputs to the logical expressions for the adder.
USING 1.35 MC CLOCK.
ADD TIME. 18 MICROSECONDS
A +B-B
Fig. 3-48-bit parallel serial accumulator. 4 bits
character in parallel, 12 characters in serial.
=
1
ADD
FULL
48 BIT
ADDER
USING CARRY PROPOGATE TIME
PER STAGE.
OF 125 X 10- 9 SECONDS
BINARY ADD TIME·
6
DECIMAL ADD TIME •
7.5 MICROSECONDS
MICROSECONDS
Fig. 4-48-bit parallel accumulator.
Parallel
When the ultimate in addition speed is required, a
complete parallel accumulator, as shown in Fig. 4,
is often used. To achieve the fullest speed advantages,
the carry propagation time should be completely
asynchronous. With no "carry hopping" or "end of
carry" sensing, an equivalent add time with the same
circuits and assumptions above would be 6 microseconds. If decimal add were included, another 1.5
microseconds would be required. Assuming the speed-
P arallel-Serial-Parallel
The parallel-serial-parallel arrangement described
here consists of three parallel 16-bit parallel-serial
registers, with the bits of a 4-bit character in parallel,
4 characters in serial. Each of the three 16-bit groupings is referred to as a major character. Major character 1 contains bits 0-15, major character 2 contains
bits 16-31, and major character 3 contains bits 3247. In 4 pulse times the sum within each major character is computed. Carries generated as a result of
these additions are then propagated and added into
the next major character in the next 4 pulse times.
At the end of these 8 pulse times, the probability
that the carries will be finished propagating and the
answer will be correct is 1 - 3 X 2- 17 = 0.999977.
Carry propagation completion can be sensed by
means of a three-leg buffer, and as much additional
time as necessary (8 pulse periods maximum) allowed
to complete the carry propagation.
Fig. 5 shows a 48-bit binary PSP accumulator
capable of either addition or subtraction. The
equations for this are shown below.
S
=
=
B.n =
Cn =
Pn =
CC n =
T 4n =
An
Subtract; S = Add
Addend
Initial augend and final result
Carry functions
Final sum functions
Character carry from each adder
Timing function every 4th clock time such
that T 4n CC n is the carry from the highest
Lourie, Schrimpf, Reach, and Kahn: Aritnmetic and Control Techniques
79
order minor character in each major
character.
Equation for Major Character 1 Adder
Co =
Cl =
C2 =
Ca =
cc
B12
=
Po
B la = PI
1
=
carry propagate time and 1.33 MC flip-flops is
approximately 6 microseconds.
This accumulator has been organized in such a
manner that decimal arithmetic using binary coded
decimal representation can be easily incorporated,
T 4n CC a + T 4n CC I
since each minor character is a binary coded decimal
CoBoj-SAoBo + SAoC o +SAoBo digit. To include decimal arithmetic two areas need
+ SAo Co
to be changed. The first is involved with rectification
Cl Bl + S Al Bl + S Al C l + S Al Bl of the binary sum where either the binary coded
decimal sum is greater than nine, or a major character
+ SAl Cl
carry was generated. This can easily be done by inC2 B2 + S A2 B2 + S A2 C2 + S A2 B2 serting the logic between B la and B 9, B 14 and B 10, and
Bu below.
+sLc2
CaB a _+ S A a B a
+ S Aa C a
+ S A a Ca + S Aa B a
Ao Bo Co + Ao Eo Co
+ AoBo Co
+ Ao Bo Co
= AlB 1 C1 + Al .81 01
+AlBlC l
+ AlB 1 01
=
-...B14 = P 2 = A2 B2 C2 + A2 B2 C2 + A2 B2 C2
+ A2 B2 C2
B 15 = P a
= Aa Ba Ca + Aa Ba Ca
+ AaBa Ca
+ Aa Ba Ca
D = Binary
D = Decimal
Bs = B12
B9
=
D B13 + CC I B 15 B13
+ D CC I B13
+ D B 15 B14 B la
B lO = D B14 + CC I B15 B14 + CC I B14 B13
+ D CC I B 15 B13 + D CC I B 15 B14 B13
Bll
-
-
.....
-
= D B15 + CC I B15 B14 B la
+ ce l B 15 B14 B la
+D
CC I B15 B14 B la
The above can be verified with a simple truth chart.
The
second area that needs change is the generaBi shifted into BiH
where 0 ~ i ~ 11
tion of inter-digit carries. This is accomplished by
Equations for the major character 2 adder are the adding a few terms to Co to take care of those cases
same with subscripts on An, B n, Cn increased by 16, where the decimal sum or difference is between 10
CC I substituted for CCa, and CC2 substituted for and 15.
CCI'
Co = T 4n CC a + T 4n CC I + T 4n D B 15 B14
Equations for the major character 3 adder are the
+ T 4n D B 15 B13 + T4n D B37 B36 +
same with subscripts on An, B n, Cn increased by 32,
+ T 4n D B37 B35
CC 2substituted for CCa, and CC asubstituted for CC1'
The average add time with 125 millimicrosecond
Fig. 5-48-bit binary parallel serial parallel accumulator.
80
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
"7" in the low order position of major character 3 is
added to form a 1 sum and a 1 carry, and, simultaneously, the "5" and "4" in the low order portion of
major character 2 is added to form a "9" with 0
carry indicated by the 09, and, similarly, 1 and 6 are
being added to form 0'7.
During the next pulse period, t2, (and through the
same addition circuits which produced the "tl"
addition) "2" plus "9" in major character 1, together
with the previous carry, "0''', forms the lIon the t2
line. Similarly "I" plus "8" plus "0" carry forms 09
and "7" plus "I" carry forms 09.
This process is repeated until the tl line of word
cycle 2. At this point, the carry from the high order
position of major character 1 is added to the low order
digit in the partial sum of major character 2. The
carry is then propagated as shown until the 3699 is
"corrected" to 3700'. Similarly, the 9991 formed in
major character 3 is corrected to 9992.
As seen in this example, the addition is completed
after 8 pulse periods.
Fig. 6-Logical organization for major character 1 of
parallel serial parallel accumulator.
PARALLEL-SERIAL - PARALLEL WITH VARIABLE CYCLE
The two corrections required the addition of only
230 diodes to the accumulator. No amplifiers were
added. The probability that the answer will be correct after 8 pulse times is 1 - 3/2000 = 0.9985. For
these cases, up to 9 more pulse times may be required
for the correct answer.
In addition to allowing a very economical method
of arithmetic, the PSP format allows other machine
simplifications over a parallel format. In particular,
it is possible to transmit a 48-bit word to remote portions of the machine by means of time sharing 12
lines, resulting in a decreased number of cable drivers.
It also allows the use of one flip-flop and 3 pulses of
delay line to store 4 bits of information in those cases
where the other 3 flip-flops are not required for manipulation reasons. A block diagram of type of
storage is shown in Fig. 7.
J
L;---,pp}---{------,pp}--.{-,pp
1.33 Me
CLOCK
Fig. 7-Use of one flip-flop and 3 pulses
of delay to store 4 hits.
Parallel-Serial-Parallel Arithmetic Example
Fig. 8 is an example illustrating two numbers being
added together in a parallel-serial-parallel adder.
The zeros immediately beneath the operands indicate
the initial state of the carry circuits at the beginning
of the addition. All of the numbers on a line with tl
indicate the computation being performed during the
first pulse period. The 11 indicates that the "4" and
MAJOR
MAJOR
MAJOR
CHARACTER CHARACTER CHARACTER
NO.3
NO.2
NO.1
937482153021
061754847396
o
o
Q
9
o
0
II
09
o i Jo 0 9" Jo
"9 + Q"6
+
1 3 Jo .L
9
t
tt
•
+
Q
.Q9
.Q.2."',
0
1
.Q.
.Q7
0
3
0
4"
.tot
Q
r
0
1 0
T 1 "0
9
07tl,T t 2 WORD
07
t3 CYCLE I
t4
,
tl--.--
.Q.4
t 2 WORD
t3ClCLE2
0
t4---L-
Fig. 8-Parallel-serial-parallel with variable cycle.
In summary, the parallel-serial-parallel format
provides a fast arithmetic speed at a relatively economic cost of logical circuitry. The addition of the
control memory to the system provides a wide range
of flexibility in order to achieve an efficient usage of
the computer.
The authors of this paper wish to extend credit to
all those at the Datamatic Division of Minneapolis
Honeywell Regulator Company, whose ideas contributed to the creation of this data processing machine.
DISCUSSION
M. RubinojJ: A criterion often used to measure the efficiency of a
computer design is computing per second per dollar. Can you comment on the efficiency of multiple operation for various types of
problems?
Mr. Lourie: The multiple independent program operation feature
costs remarkably little when integrated properly in the design of a
data processor. The amount of work which can be accomplished
per second - such work includes card reading, tape operations, etc.,
as well as actual computing - is, of course, increased tremendously
in a multi-programmed design, since these various operations are
being performed simultaneously rather than serially. This is especially so where the traffic control of the various programs is automatic
so that maximum use is made of each memory cycle of the machine.
I think, therefore, that it is obvious that the efficiency as measured
by your criterion is exceptional in a machine of this nature.
J. Gosden (Leo Computers): What are the major uses of the cosequence registers?
Lourie, Schrimpf, Reach, and Kahn: Arithmetic and Control Techniques
81
Mr. Lourie: The major uses of the co-sequence registers are to perform sub-routines without the use of "housekeeping" type orders.
available for computation. The maximum input/output rate is such
that no data would be lost.
M. S. Maxwell (US Naval Weapons Lab): What is the speed of the
central computer memory and control memory?
J. H. Hughes (American Mutual Liability): What happens when you
try to add, say, hexadecimal (15) plus (12)?
Mr. Lourie: Six microseconds complete cycle time for both memories.
Mr. Lourie: If any generalized binary configuration is to be added
to another binary configuration, the Binary Add order of the machine
should be used and will lead to a correct answer. The normal Decimal Add orders are used only for operations involving the binary
coded decimal code for digits 0-9.
J. Daniels (ISI): Are there provisions to prevent one program from
overwriting another in the main memory?
Mr. Lourie: An executive routine has been designed for use with all
H-800 installations. This routine automatically solves all problems
of interference with regard both to equipment and to memory space
allocations. Automatic assignment of memory locations is arranged'
for by this routine on a non-conflicting basis.
Miss E. Berezin (Teleregister): How is the 256 bit control register
loaded, particularly if one wished to start one program while others
were in operation?
Mr. Lourie: The loading routine would use one of thE' unused eight
sequence registers to load the control memory.
L. Clapp (Sylvania): Is there any possibility of losing information if
several output/input trunks are working simultaneously?
Mr. Lourie: The machine speed is such that it can simultaneously
handle eight input and eight output trunks, all of which occur to and
from magnetic tape mechanisms. There would be 16 trunks acting
simultaneously with approximately one-third of the computer time
B. Tasini (IBM): Can you comment on the debugging of problems
on a multi-programmed computer?
Mr. Lourie: Debugging is not very much more difficult on a multiprogram machine, since each program would be debugged independently, and then these programs would be run simultaneously.
P. Seaman (IBM): Is the program priority system and the I/O
priority system fixed, or can it be specified by the programmer?
Mr. Lourie: There is no priority with regard to programs. Rather
they are handled cyclicly in order.' If one program requires the
machine for a certain period of time, it can insert an order that will
shut off all other programs and then, at some later time, turn these
programs back on. The priority of peripheral equipment is fixed.
C. L. Foster (IBM): Is control memory addressable from main
memory?
Mr. Lourie: Yes.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
82
The Virtual Memory in the STRETCH Computer
JOHN COCKE
AND
HARWOOD G. KOLSKyt
ARLY in the planning of the STRETCH computer it was seen that by using the latest solid
state components in sophisticated circuits it
would be possible to increase the speed of floating
point arithmetic by almost two orders of magnitude
over that in existing computers. However, there
seemed to be no possibility of developing on the same
time-scale economically feasible large memories with
more than a factor of ten or perhaps twenty increase
in speed. As a result, the proposed system appeared
to be in danger of being seriously memory-access
limited.
Moreover, as the speed of the floating point operations increases, a larger and larger percentage of the
computer's time is spent on "parasitic operations",
i. e., operations whose only function is program control and data selection. It was obvious that a radically
new machine organization was necessary in order to
capitalize upon the possibilities opened up by the
high arithmetic speeds in the presence of relatively
slow memories.
At this time, a number of persons were considering
the possibility of a "look-ahead" device in which an
independent indexing arithmetic unit would prepare
the effective addresses of instructions and initiate
memory references to a multiplicity of memory boxes.
The data thus fetched would be held in high-speed
buffer registers until needed by the arithmetic unit.
This device would serve two desirable purposes: (1)
some of the parasitic operations would be done in
parallel and thus not delay the principal calculations,
and (2) several memory boxes could be running
simultaneously, giving the effect of higher memory
speed.
Since our original work on the virtual memory and
simulation in 1957-58, a large number of detailed
changes have been made in the actual hardware
design of STRETCH. These necessitated several
modifications in the simulation program to estimate
E
Fig\ I-Schematic of Stretch computer.
t International Business Machines Corporation, Poughkeepsie,
New York.
their effect on the overall system performance. In
this report we are omitting many of these changes for
expository reasons, since our purpose is to describe
the virtual memory and timing simulation concepts,
not to describe the STRETCH hardware exactly.
The result is that the system described below embodies a more general system than that found in the
simulator, which in turn is more general than that
found in the actual computer.
GENERAL DESCRIPTION OF THE SYSTEM
The major logically-independent blocks of the
STRETCH computer are shown in Fig. 1. Each of
the units pictured may be considered as operating
asynchronously. That is, each does its tasks as fast as
possible independently of the others. In theory, each
box could have its own clocking circuits and still
operate properly. In practice, for economy's sake they
are all timed by the same master oscillator, but this
does not destroy their logical independence.
The bus control unit serves as a routing agent
between the memories and the various data) processing units. If two or more units make a request simultaneously the control unit assigns priorities in the
following order: (1) High-speed Exchange, (2) Basic
Exchange, (3) Virtual Memory, and (4) Indexing
Arithmetic Unit.
The Indexing Arithmetic Unit fetches instructions,
performs all necessary indexing operations and sends
the instructions to be executed to the Virtual Memory.
The Virtual Memory fetches and receives the data
required by the instruction and holds this data until
the arithmetic unit is ready for it. The Virtual
Memory also performs all store operations. It holds
the data generated by the arithmetic unit or indexing arithmetic unit until the memory to which the
data must be sent is available. Thus the virtual
memory acts not only as a "look-ahead" for instructions to be fed to the arithmetic unit, but also acts as
a "look-behind" storage buffer.
The actual design of such a "look-ahead" device
posed a number of logical problems, particularly in
connection with conditional branches. However, a
machine organization of this complexity requires a
detailed timing analysis in order to determine the
value of adding hardware in the form of the virtual
memory. This is especially true since the sole function
of the virtual memory is to increase machine speed,
hy increasing the efficiency of other devices. It was
al:::,o felt that the timing analysis could not be made
on the basis of a few trivial examples (e.g. matrix
Cocke and Kolsky: Virtual Memory in the STRETCH Computer
multiply). Machine performance obtained in this
fashion can be extremely deceptive. Since a detailed
timing analysis of a computer of this complexity is
extremely tedious to carry out by hand, it became
clear that if the job were to be done, it would be
necessary to simulate the proposed machine on
another computer. This prompted us to write the
simulation program to be described later.
With the above general organization in mind, let
us discuss some of the logical problems posed by such
a system. The first problem is a result of the very
concept which enables us to obtain such great benefits from the stored program computer - the ability
to treat instructions as data. In a system such as we
have proposed there is a large amount of simultaneous
operation. For example, the indexing arithmetic unit
may be busy preparing an instruction before previous
instructions have been completed or even started by
the arithmetic unit. One of these previous instructions
may modify the instruction which is presently being
indexed. The virtual memory must recognize this
situation and allow the intervening instructions to be
completed before doing the modified instruction.
A similar problem exists with respect to ordinary
data. In order to operate several memories simultaneously, it is necessary to start obtaining data from
these memories before the preceding operations have
been completed. Yet, one of these operations may be
a store into one of the data locations. The virtual
memory must make provisions to insure that each
instruction obtains the most up-to-date data as
implied by the order of the program.
One of the novel features of the STRETCH computer is its elaborate interrupt system. Under this
system, whenever some unexpected occurrence arises,
the program will be interrupted and control will pass
to a special routine which is designed to take care
of the case in question, then return control to the
original program. In this situation the virtual memory
must have provisions to retain enough information so
that when an interrupt occurs we can resume the
computation exactly where we left off. It must be
able to recognize which of the changes that have been
made in advance are not desired and should be
obliterated, and which are exact solutions that must
be restored.
Another special case arises when a conditional
branch on arithmetic results occurs. Here we will not
know which of the two branches we should have taken
until the preceding instruction is executed. In the
case where the wrong path has been selected, the
virtual memory must be prepared to drop the in termediate results which have been computed and pick
up the correct branch in a way very similar to that
of an interrupt.
Summing up all these logical problems, we may
state that the fundamental rule for the virtual
memory is that it must make the asynchronous and
83
non-sequential computer give results identical to
those which would be obtained by performing the
program one instruction at a time in the order in
which they are written.
Definitions
Operations
Opera tions are considered to be of three types:
(1) Bring or Fetch Type -
All instructions requiring data to be transmitted from external
memory to the virtual memory.
(2) Store Type - Instructions requiring the
transmission of data from the virtual memory
to external memory or index memory.
(Note: We consider all indexing instructions
to be of the store type, although the store
may be to either external memory or index
memory.)
(3) Immediate Type - All operations not requiring data transmission.
Virtual Memory Quantities
(1) Virtual Memory -
(2)
(3)
(4)
(5)
(6)
(7)
(8)
A number of virtual
memory (or look-ahead) levels (numbered 0
to N - 1).
Level of Virtual Memory - A collection of
registers and control bits. The contents of the
jth level are shown in Fig. 2.
Instruction Address Register (1 i) - Contains
the address of the instruction currently in the
jth level.
Operation Code Register (OP i) - Contains
the operation to be performed by the arithmetic unit.
Store Bit (Si) - a one-bit trigger which
indicates the level, contains a store type
instruction.
Bring Bit (Bi) - A one-bit trigger which
indicates the level, contains a fetch type
instruction for which the data access has not
been started.
Forwarding Bit (F i) - A one-bit trigger
which indicates that the jth level must
transmit data to another level.
Forwarding Address (FA i) - A register which
contains the number of the level to which the
data must be sent if Fi is set.
V M LOCATION COUNTERS
COUNTER
COUNTER
COUNTER
COUNTER
I
2
3
4
INSTRUCTION FETCH
OATA FETCH
OATA STORE
ARITHMETIC UNIT
Fig. 2-Virtual memory -
contents of one level.
84
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
(3) Interlock three (13): C I = C 2 Similar to 1 2 ,
prevents a fetch from being initiated.
(4) Interlock four (14): C l = C4 Prevents the
arithmetic unit from executing an old instruction.
(5) Interlock five (15): CI = C 4 + N Prevents the
IA U from placing the next instruction into the
level indicated by C 1 because the instruction
there has not been executed yet.
Logic of the Virtual Memory
INTERLOCKS I4 AND 15 ARE AS SHOWN. THE OTHER INTERLOCKS
ARE DONE IN A SIMILAR MANNER
Fig. 3-Virtual memory interlocks.
(9) O. K. Bit (OK j )
A trigger which when set
indicates that the correct data for the instruction to be executed is present in the jth data
field.
(10) Data Field (D j ) - A register which contains
the operand data for the instruction.
(11) Data Address (DA J) - The operand data
address (already indexed by the IAU) for D j •
(12) Compare Bit (C j ) - A trigger which if not set
indicates the address in DA j should not be
included In any address comparisons being
made.
Counters
The virtual memory is controlled by a set of
counters which count mod(N), where N is the number
of virtual memory levels.
(1) Counter one (C I ) - Indicates the level into
which the next instruction may be placed.
(2) Counter two (C 2 - Indicates the level from
which the next bring type instruction may be
initiated.
(3) Counter three (C 3) - Indicates the level from
which the next store type instruction may be
initiated.
(4) Counter four (C 4) - Indicates the level from
which the arithmetic unit will get its next
operation and data.
There are two basic precepts which must be kept
in mind to understand the operation of the virtual
memory:
(1) The OK bit (0,1) being-set in the jth level indicates that the contents of D J is the correct
data called for by DA J • All operations will be
performed only under this. condition, and
logical decisions will be made in such a manner
as to make sure this is the case.
(2) Addresses can be compared by the IAU with
every DA J address simultaneously. DA j is not
used for any level which does not have its C j
bit set. If a comparison exists between a new
DA j being placed in the virtual memory and
an old DA k , the compare bit C k is turned off
and the address of level j is placed in F A k.
This insures a unique meaning for the comparison. If this were not done, another instruction address DAe might compare against two
levels and thus cause an ambiguity.
Instructi9n Fetch Logic
Fig. 4 is a flow diagram of the IAU Instruction
Fetch Procedure. The logic is as follows: If the IA U
is ready to fetch another instruction, it compares the
instruction address with all the DA /s of virtual
memory. If there is no comparison, the instruction
fetch is initiated. If there is a comparison, the IA U
Interlocks
The above counters must be interlocked in the
following manner to assure proper sequential operation of the computer (see Fig. 3:)
(1) Interlock one (II): C I = C3 + N Prevents
the IAU from placing the next operation into
the level indicated by CI because an unexecuted store is still in the level.
(2) Interlock two (1 2 ): C l = C 3 Prevents a store
from being initiated from the level indicated
by C 3 because the store has already been done.
YES
,
NO
Fig. 4-Instruction fetch procedure.
Cocke and Kolsky: Virtual Memory in the STRETCH Computer
must take its instruction from the virtual n1emory
provided the OK bit is set; otherwise, it must wait
until the OK bit is set.
Note: This procedure prevents the logical difficulty
mentioned earlier whicn would occur if the virtual
memory contained a store order into the instruction
presently being fetched.
For Example:
a
a
+
+
1
2
a+3
a
STORE Address a
LOAD M, i
ADD N, i
+
2 •
The store to a + 2 must be done in sequence or the
old value N would be used for the address instead of
the quantity being set by a.
Indexing Logic
Fig. 5 shows the flow for instruction indexing. After
determining that an instruction is ready to be indexed, the lAD tests whether or not the index value
is available. If it is, the indexing operation is started;
if not, the memory reference is started and the lAD
waits until the data returns before proceeding. If the
index-fetch has not been started, the lAD compares
the index address against all the data addresses in
virtual memory. If none compare, the index value is
fetched normally. If one does compare, the index
fetch is held up until the OK bit is set for the data.
This value from the virtual memory is then used for
indexing the instruction.
Fig. 5-Indexing procedure.
Logic of Putting Instructions in the Virtual Memory
(1) Figs. 6, 6A, 6B, 6C represent the logical flow
for putting instructions into the virtual
memory. If the indexing arithmetic unit has
an instruction prepared for the virtual memory, it may transmit the instruction into the
85
virtual memory if interlocks one and five do
not forbid it. These interlocks prohibit a new
instruction from destroying an old one which
has not been executed as yet, whether an
arithmetic operation (15) or an unexecuted
store (1 1), The handling of the instructions
varies depending on whether they are of the
bring type, store type, or immediate type.
(2) The bring type, as described in Fig. 6A, proceeds as follows: If the effective data address
of the instruction compares with the DA
address in some level, the instruction, its op
code, and effective data address are loaded
into the level marked by C 1. The compare bit
for level C 1 is set to one while the compare bit
for the compared-with level is set to zero. If
the OK bit in this compared-with level is set,
meaning that the data located there is correct,
the data is transmitted directly to the C I level
and its OK bit is also set. If the OK bit is not
set, we must tag the compared-with level by
setting its forwarding bit and by putting the
value of C I into its forwarding address; the
bring bjt for level C I is also set to zero since no
further data fetch is required.
If the effective data address does not compare
with any Virtual Memory level, the instruction is put directly into level C I , its OK bit is
set to zero, and its bring bit is set to one, indicating that a fetch must be started.
(3) Fig. 6B shows the store type procedure. If the
effective address of the instruction 'does not
compare with the DA address in some level,
the instruction is placed into the level marked
by CI . The store bit is set to one indicating
that a store will be required. The level's bring
bit and forwarding bit are set to zero; its
compare bit is set to one. If on the o~her hand
the addresses do compare, the same procedure
is followed; but in addition, the compare bit
in the level compared-with is set to zero so
that future comparisons will not use it.
The OK bit has not yet been set. It is set to
one if the operation is an index store and set
to zero if it is an ordinary store. For the ordinary store it is clear that the OK bit should be
zero since the data must come from the arithmetic unit after the preceding instruction is
executed.
As was mentioned in the definition previously
we treat all indexing instructions as store
type and place the new value of the indexed
quantity into the virtual memory. This is
done because the indexing arithmetic unit is
going ahead of the normal order of instruction
execution and an interruption may occur
before this indexing instruction should have
86
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
FROM FIGURE 6
IN THE C, LEVEL'
PUT THE INSTRUCTION A"DRESS IN lA, PUT THE
OP CODE IN OP, PUT THE DATA ADDRESS IN DA.
SET THE STORE BIT TO ONE, THE BRING BIT 10
ZERO, THE FORWARDING BIT TO ZERO, AND THE
COMPARE BIT TO ONE
Fig. 6-Procedure for placing instructions
into the virtual memory.
FROM FIGURE 6
Fig. 6(b)-Logical conditions for store type operations.
SET COMPARE BIT TO ONE IN CI
LEVEL AND TO ZERO IN COMPAREDWITH LEVEL
IN THE C, LEVEL PUT THE INSTRUCTION ADDRESS IN 1A PUT THE OP
COOE IN OP. PUT THE DATA ADDRESS IN DA SET THE BRING BIT,
THE STORE BIT, AND THE FORWARD-
IN THE Co LEVEL PUT THE INSTRUCTION ADDRESS IN 1A PUT THE OP CODE
IN OP PUT THE DATA ADDRESS IN DA
SET THE BRING BIT TO ONE SET THE
FORWARDING BIT, THE COMPARE BIT,
AND THE 0 K BIT TO ZERO
ING BIT TO ZERO
l
iS OK BIT SET IN
COMPARED-WITH LEVEL
I
NO
I
FROM IGURE 6
IN THE C, LEVEL
PUT THE INSTRUCTION ADDRESS IN lA, PUT
THE OP CODE IN OP PUT tHE DATA ADDRESS
INTO D (NOTE THIS) SET' O.K. BIT TO ONE.
SET FORWARDING BIT, THE BRING BIT,
AND STORE BIT TO ZERO seT THE COMPARE
BIT TO ZERO (NOTE)
!
I
YES
RETURN TO TOP OF FIGURE 6
Fig. 6(c)-Logical conditions for immediate type operations.
SET THE FORWARDING BIT TO ONE
AND PUT Co IN THE FORWARDING
ADDRESS OF THE COMPARED-WITH
LEVEL
SET THE 0 K BIT TO ZERO IN
THE Co LEVEL
SEND DATA FROM THE COMPAREDWITH LEVEL TO 0 OF LEVEL Co
SET 0 K BIT OF LEVEL C, TO
ONE
RETURN TO TOP OF FIGURE 6
Fig. 6(a)-Logical conditions for bring type operations.
been done. In this case, the old value of the
index is still in the index register. On the other
hand the indexing arithmetic unit compares
with the virtual memory and extracts the
most recent value of the index for indexing
succeeding instructions. The OK bit is set to
one since the appropriate data is in the above
level. Both the new and old index values must
be carried along to give logically correct conditions in the case of an interrupt. A situation
very similar to interrupt occurs in branches on
arithmetic results where the indexing arithmetic unit "guesses" which branch will be
taken and proceeds with fetching and processing the instructions on this branch, subject to
being wiped out if the guess proves to be
wrong. (See the discussion on "Wrong way
Branches" below.)
(4) Immediate type instructions are the simplest
type because they essentially carry their data
with them. Fig. 6C shows the logic in this case.
The instruction is placed in the virtual
memory level marked by C 1 , The address field
of the instruction is placed in the data field of
C 1 • The OK bit is set to one indicating the
data is present. The bring and store bits are
both set to zero. The compare bit is set to
zero since the DA address field has no meaning for immediate type ops. (The data address
of the last instruction which occupied this
level still remains in DA, so it has no relation
to the present D field. )
liS THE BUS FREE
I
YES
I
~
NU'T
Fig. 7-Data fetch procedure.
Cocke and Kolsky: Virtual Memory in the STRETCH Computer
87
Logic of Data Fetching
See Fig. 7: When an instruction of the bring type
has been placed in the virtual memory, the data required by the instruction in general will not be present
(unless a comparison exists as was described above)
and thus the data must be obtained from core storage. The fetch cannot be started if interlock 13 holds,
which means all the fetches corresponding to the
instructions presently in the virtual memory have
been started. If a fetch is possible, the bring bit at
level C2 indicates whether or not a fetch is necessary.
If necessary the fetch may be started if the memory
bus and memory unit corresponding to the data
address are not already being used. When the fetch is
started, the bring bit for level C2 is set to zero. The
counter C2 is then stepped forward to the next level.
Logic of Data Storing
Fig. 8 shows the Data Store Logic, which is very
similar to that for data fetching just described. The
only significant difference is that the OK bit must be
set before the operation can be started.
Fig. 9-Procedure for placing data into virtual memory.
Logic of Removing Instructions from the Virtual
Memory
In Fig. 10, we notice that as the arithmetic unit
completes an instruction it checks to see if the next
instruction in the virtual memory is ready to be executed (indicated by interlock 14). Note that the
operation may be an unconditional branch, a conditional branch, or an index type store, as well as a
normal bring or store type instruction involving the
accumulator. Fig. 10 shows only the cases which involve the universal accumulator. Instructions such as
the unconditional branches are merely ignored at this
point. They are carried along only to provide the data
for recovery in the event an interrupt occurs. The
execution of the conditional branches on arithmetic
results are described in the next section.
If the next instruction marked by counter C4 is
ready, it is fed into the arithmetic unit. If it is a store
Fig. 8-Data store procedure.
Logic for Placing Data into the Virtual Memory
In Fig. 9, we see the logical conditions which must
be satisfied by the data returning from memory
addressed to the virtual memory. The return address
which was supplied when the fetch was started selects
the level into which the data will be placed. The OK
bit is then set to one, indicating that the proper data is
in the level. The operation is complete at this point
unless the forwarding bit is set. In this case, the data
must be forwarded to the level designated by the
forwarding address. This procedure continues from
level to level as long as the data continues to arrive
into a level whose forwarding bit is set. This procedure
automatically supplies all operands present having
identical data addresses with the proper data, without
additional memory references.
Fig. lo--Procedure for removing instructions
from virtual memory.
88
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
type, the data is gated from the accumulator into the
data field of level C4 , and the OK bit is set to one. If
the forwarding bit of the level is set, a forwarding
procedure in this case is essential for the proper
logical operation of the computer, whereas in the
bring case it is a time-saver only.
If the instruction is not a store type, the arithmetic
unit must hold up until the OK bit for the level is set.
When the OK bit is set, the instruction is gated into
the arithmetic unit and executed.
Logic of Interrupt Procedure
ponents. This means that there are a large number of
logical steps being executed at anyone time in the
computer, each of them proceeding at its own rate.
To simulate this flow of many parallel continuous
operations, we have broken the continuous time
variable into finite time steps. The basic time step is
taken as 0.1 microsecond in the simulator.
By taking 0.1 microsecond as our quantum of time,
we are automatically setting the scale of the smallest
circuit entities which we will consider as being those
which accomplish complete functions in 0.1 microsecond or few multiples thereof. Thus, by using this
pholosophy, and considering many of the components
of the computer as "black boxes", we greatly simplify
the details which must be considered without introducing serious timing inaccuracies.
Our experience has indicated that more information was gained by making a large number of fast
parameter studies using different configurations and
programs than could have been obtained by a very
slow, detailed simulation of a few runs with more
precision per run. Even so, our time scale is too fine
to make serious input-output application studies.
These would require a simpler simulator having at
least a factor of 10 coarser basic time interval.
If for any cause an interrupt (or trap) from a special condition occurs, the instruction which is being
executed in the arithmetic unit is completed. However, the next instruction is not executed in spite of
the fact all the data preparation for it may have been
completed. The address in the I A (instruction address) field will serve as the value to reset the instruction counter if it is desired.
The Virtual Memory is initialized, i.e., set to the
starting conditions of an interrupt, with the exception that all store orders which have already received
data from the accumulators must be executed first.
If the interrupt is of such a nature that the normal
flow of instructions is not resumed, the procedure of
storing the modified values of the index registers in
the Virtual Memory gives logically correct results, Logic of the Simulator
i.e., the same as if the interrupt had occurred before
In the asynchronous organization of STRETCH
the indexing took place.
there can be many major components operating at
anyone time. To achieve this parallel effect in the
DESCRIPTION OF TIMING SIMULATION PROGRAM
simulator we essentially "hold time still" and scan
During the logical design of STRETCH it was the entire machine representation at each time step.
necessary to prove the value of the virtual memory Although every major block of the program is
concept and to assist in the selection of optimum traversed at each time step, if there is no activity
values of various system design parameters. Ex- required in a given block, only a few tests need be
amples of such parameters are: The number of made by the code.
n in this process it is determined that a given
memory boxes, interlace and allocation of memory
addresses, and numbers of virtual memory levels. logical unit should do an operation, the time interval
Also of interest were trade-off factors for speeds of required for the operation is obtained from a table of
constants. The speed of the various logical units can
indexing arithmetic unit, memories, etc.
In November 1957 the Timing Simulator (SIM-2) thus be changed parametrically by changing the
described here was written for the IBM 704. This values in the tables. A constant obtained from the
program attempted to answer such questions quan- tables is inserted into a memory location called the
titatively by simulating the time-wise operation of time counter for that unit. At each time step the
STRETCH on typical test programs coded in program reduces this counter by one until it reaches
zero. Thus, the fact that the counter is non-zero can
STRETCH language.
The basic logic of the 704 program follows the be used to indicate that the particular logical unit is
principles just described in the preceding section for busy and not available to service other requests.
the virtual memory. It should be stressed that tlie When the counter is zero the unit can consider a new
simulator is a timing simulator and does not execute input.
In addition to the time counters many of the
the instructions in an arithmetic sense. It traces the
time-wise progress of the instructions through the logical blocks contain other conditions or interlocks
components of the computer, observing all the inter- which affect the operation of the block. These condilocks and time delays necessary for correct representa- tions are stored in the program and tested before
action is undertaken.
tion of the behavior of the machine.
It is interesting to note that since the simulator
One of the fundamental concepts in the STRETCH
design is that of asynchronous operation of the com- simulates timing only, the sequence of instructions
Cocke and Kolsky: Virtual Memory in the STRETCH Computer
to bt executed must be furnished as a "string" with
all loops unwound. However, to make the computer
behave as it actually would, the loops must be furnished with "wrong way" paths given for the cases
where the computer would take such paths. Also one
must furniM more than enough information along
such paths since it is difficult to predict in advance
how far the computer will get down the wrong path
before it it called back.
Parameters are changed from one run to another
by use of control cards. The control cards are set up
in such a way that any number of parameters may be
changed between runs. Results are given either as
detailed timing charts or as summary listings for each
problem. The usual procedure has been to print only
summary results while making a series of parameter
studies. The detailed timing charts as printed on the
704 for most problems would be about 50 feet long
for each run. Since over 1000 cases have been run, it
is clear that only a few cases could be printed in full
detail. These are particularly useful in seeking the
causes of conflicts which slow the computer.
Results of P arameier Studies
When the simulator program was completed, we
undertook a series of studies in which the main
parameters describing the STRETCH system were
varied one or two at a time in order to get a measure
for the importance of different effec-ts. After this we
began to specialize the studies towards answering
specific questions in the STRETCH design.
~ ~~I~~~~~JI~=IT
[
3
4
5
6
7
B
9
10
I I
12
13
14
15
DECODE DPERAT IONS
VIRTUAL MEMORY
INDEXING ARITHMETIC UNIT
BUS FROM MEMORY
BUS TO MEMORY
1/ 0 REFERENCES TO MEMORY
V M STORE REFERENCES TO MEMORY
V M FETCH REFERENCES TO MEMORY
[A U REFERENCES TO MEMORY
INSTRUCTION FETCH REFERENCES TO MEMORY
COUNT-OOWN TIME
PRINT DETAILED LISTING
SUMMARIZE AND PRINT
Fig. ll-SIM -
2 simplified flow diagram.
The simplified flow diagram in Fig. 11, indicates
the order in which the subroutines for the various
logical units are executed at each time step. Using
the types of techniques just described above, the
logical subroutines simulate the action of the components of the computer such as the virtual memory,
arithmetic unit, etc.
SOME RESULTS OF THE SIMULATION STUDIES
89
The 2nd column, II, gives the number of the
instruction being indexed. The 4th column, AU,
gives the number of the instruction using the arithmetic unit. The next four columns represent the
instructions using the memory buses. The columns
labeled X- F-, and M- represent the index, fast, and
main memories. A string of X's in the columns represen ts the cycle time of the memory. The number
indicates the instruction using the memory and 'the
number of times which it is repeated gives the readou t time of the memory. The columns L- indicate
which instruction is located in the virtual memory
levels. The other columns are for details in analysis
and need not be considered here.
Five of the test problems used most frequently are
described below. Other test problems were used for
specific studies, but since the results were similar for
all problems of a given type, we gradually discontinued using them. The following were originally
selected as being typical of different classes of
problems.
(1) Mesh Problem - Part of an hydrodynamics
problem from Los Alamos. It contains a more
or less "average" mixture of instructions for
scientific problems: 85% floating point instructions, 14% index modification instructions, and
1% VFL. It is usually arithmetic unit limited.
(2) Monte Carlo Branching Problem - Part of an
actual Monte Carlo neutron diffusion code. It
represents a chain of logical decisions with very
little arithmetic in between. It contains 47%
floating point, 15% index modification instructions, and 36% branches of the indicator and
unconditional types. It is largely instructionaccess limited.
(3) Reactor Problem - The inner loop of a neutron
diffusion problem. It consists of 90% floating
point arithmetic (39% of which are multiplys)
and 10% index modification instructions. It is
almost entirely arithmetic unit limited.
(4) Computer Test Problem - The evaluation of a
polynominal using computed indices. It has
71 % floating point, 10% index modification,
6% VFL and 13% indicator branches. It is
usually arithmetic unit limited, but not for all
configurations.
(5) Simultaneous Equations - The inner loop of a
Fig. 12 shows examples of the type of output listmatrix inversion routine 67% floating point
ings given by the simulator. Fig. 12 is a piece of a long
and 33% index modification. Arithmetic and
timing chart with each line of printing representing
logic
are about equally important. It is limited
0.1 microsecond of time. The columns represent the
both
by arithmetic and instruction-access
various components of the computer. On the left and
speeds.
right are timing counts subdividing each microsecond. On the far right are conflict indicators (C on
the charts) and waiting indicators, W, which indicate Speed vs. Number of Levels of Virtual Memory
Fig. 13 shows the effect on computer performance
when interlocks prevent operations from proceeding.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
90
IS
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7 1
8
9 2
10 2
1 2
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
1
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
7
7
7
7
8
8
8
8
8
4
5
6
7
8
9
10
1
2
3
4
5
6
9
9
9
10
10
10
10
10
1
1
2
4
1
1
2
4
1
1
2
4
1
1
2
2
4
1
1
1
1
2
2
4
1
1
2
4
1
1
2
2
4
1
1
2
2
2
4
1
1
1
2
4
1
1
2
2
2
4
1
1
1
AU IF 1M OF OM Xl X2 F1 F2 F3 F4 M1 M2 M3 M4 M5 M6 M7 M8 L1 L2 1.3 lA L5 L6 L7 L8 FD MD Me
1
2
1
1
2
1
3
1
1
2
3
4
1
3
5
1
lX
3
6
lX
3
2
7
3
1X
1 8
3X IX
9
3X X
2 10
1
3X X
1
1
1
3X
2
X
3
3
2
X
3
4
1
5
6
2
1
7
8
1
2
9
1
1 10
x
1
1
1
1
2
2
5
2 1
1 3
5
4
2 1
2
x
2 1
5
2
5
2 1
5
1 6
5X
3 2 1
7
5X
3 2 1
2
8
5X
3
x
3 2 1
1 9
5X
3 2 1
10
X
3 2 1
2
1
5
4 3 2 1
X
4
7
1 2
5
4
7
4 3 2 1
!!
4
4
7
2
4 3 2 1
4
4 3 2 1
7
1 5
4X
7X
4 3 2 1
6
4X
7X
2
4 3 2 1
7
4X
7X
1 8
4 3 2 1
4X
7x
4 3 2 5
5
9
4X
x
4 3 2 5
2 10
5
7
X
4X
4 3 2 5
5
1
1
7
4X
4 3 2 5
5
2
4X
4 3 8 5
9
5
2
3
X
5
9
1 4
4 3 6 5
4
X 5X
9
4 3 6 5
4
5
x 5X
4 3 6 5
9
2
6
4
X 5X
9
4 3 6 5
1 7
4
X 5X
9X
4 7 6 5
7
8
9X
X 5X
4 7 6 5
2
7
9
9X
X 5X
x
4 7 6 5
7
1 10
9X
X 5X
4 7 6 5
7
1
X 5X
X
7
4 7 6 5
2
2
9
X X
X
4 7 6 5
7
1 3
9 5
7X
X X
11
4
8 7 6 5
6
X
X
7X
11
2
5
8 7 6 5
7X
5
X
1 6
11
8 7 6 5
5
7X
X
11
8 7 6 5
7
5
7X
X
11
2
8
8 7 6 5
5
7X
X
11
9
8 7 6 9
1
5
X
7X
1lX
8 7 6 9
10
5
X
7X
x
1lX
8 7 6 9
2
1
X
X
llX
1
2
7
8 7 6 9
X
X
6
11X
x
8 7 6 9
3
7
X
X
X
8 7 6 9
11
2
4
7 11
X
X
8 7 10 9
13
1 5
7
X
13
8 7 10 9
6
Fig. 12-Listing of simulator print-out.
w
ew
ew
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
w
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
ew
e
e
e
e
e
e
e
ew
e
e
e
e
91
Cocke and Kolsky: Virtual Memory in the STRETCH Computer
of varying the number of levels of virtual memory. Speed vs. Number of Main Memory Units
Curves for the Monte Carlo and Mesh Calculations
Fig. 14 shows how internal computer performance
with two sets of arithmetic and indexing arithmetic
varies with the total number of memory units for a
speeds are shown. The A U times given are averages particular problem. The entire calculation is assumed
for all operations.
to be contained in memory for all cases. The speed
gain from overlapping memories is quite apparent
from the graphs.
120
MESH CALC WITH
AU TIME 0.64,..
IAU TIME 0.6,..
110
120
100
100
90
70
I&J
",---_.....
~ 60
(/)
50
40
30
20
X
MESH SEPARATE
20/,5 INSTR MEM
90
80
o
MESH CALC WITH REGULAR
SEPARATE 0.61£5 FAST MEM
110
MESH CALC WITH
AU TIME 1.28,..
_ - - - - - - !AU TIME 1.4,..
/'
~
MONTE CARLO CALC
AUTIMEO.64,. ••
IAU TIME 0.6,..
MONTE CARLO CALC.
_ - - - - - - - - - - - AU TIME 1.28,..
_ -IAU TIME 1.4,..
°0~~~~~~~~6--~7~8~
NO. LEVELS OF LOOK-AHEAD
/~
~ 60
I&J
a.
(/) 50
40
30
~ MESH CALC
/
70
20
10
-~-
.......... - - - - .....
80
WITH DATA
AND INSTR SHARING SAME
2.o/,5 MAIN MEM BOXES
/
/
"
~
"
MONTE CARLO WITH REGULAR
SEPARATE 0.6,,5 FAST MEM
rMONTE CARLO SEPARATE
2.0/,5 INSTR. MEM
X~
- - - - - - - - - - - - - ' - M O N T E CARLO WITH DATA
AND INSTR SHARING SAME
2.0/,s MAIN MEM BOXES
10
2345678
NO MAIN MEMORY BOXES
Fig. I3-Computer speed vs. no. of levels of look-ahead registers;
4 main mems. 2.0 J.l.S; 2 fast mems. 0.6 J.l.S for two sets of arith.
speeds.
A number of interesting results are apparent from
these curves:
(1) There is a tremendous gain to be had in going
to the virtual memory organization. The point
for "0 levels" means that the arithmetic unit
is tied directly to the instruction preparation
unit, although simple Indexing-Execution overlap is still possible.
(2) The gain in performance goes up very rapidly
for the first two levels, then rises more slowly
for the rest of the range.
Fig. I4-Computer speed vs. number of main memory boxes:
4 level LA; 0.6 J.l.S I AU time; 0.64 J.l.S AU time.
The speed differential between having and not
having instructions separated from data arises from
delays in instruction fetches caused by the memory
units being busy with data. The size of this effect
varies from problem to problem, being less pronounced for problems which are arithmetic limited
and more for logical problems.
The X's on the graph show the effect of replacing
the 0.6 fLsec instruction memories by a pair of 2.0
fLsec memories. The resulting performanGe change is
small for the Mesh problem, which is arithmetic
limited, but large for the instruction-fetch limited
Monte Carlo problem.
(3) A large number of levels does the Monte Carlo Speed vs. Arithmetic Unit and 'Indexing Arithmetic
problem less good than the Mesh problem
Unit Times
because constant branching in the former
Although everyone realizes the importance of
spoils the flow of instructions. Notice that the
arithmetic
speed on overall computer performance,
curve for the Monte Carlo problem actually
it
was
not
until
the simulator results became available
decreases slightly beyond six levels. This phethat
the
true
importance
of the indexing arithmetic
nomenon is a result of memory conflicts caused
speeds
was
recognized.
Figs.
15 and 16 show a twoby extraneous memory references started by
parameter
family
of
curves
giving the computer
the computer running ahead on the wrong-way
speed
as
a
function
of
the
A
U
and
fA U times.
paths of branches.
Fig. 16, in which the arithmetic time is the abscissa,
(4) The computer performance on a given problem shows an interesting "saturation" effect where the
is clearly less for slower arithmetic speeds. computer performance is independent of A U speed
However, it is important to note that the below some critical value. Thus it makes no sense to
sensitivity of the performance is also less for strain A U speeds if the fA U is not improved to
slower arithmetic speeds. The virtual memory match. The curves in Fig. 15 show the same effect,
improves the performance in either case, but i.e., the fA U speed serves as a "ceiling" on perit is not a substitute for a fast arithmetic unit. formance beyond whi'ch the A U speed cannot pass.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
92
speed as long as its percent efficiency is reasonable
for a variety of problems. One will stop this process
when the overall performance gain no longer matches
the increase in hardware and complexity. Thus the
arithmetic unit efficiency is a by-product of this
design process, not the prime variable.
110
100
90
80
70
8
UJ
0..
tJl
60
50
MESH CALC
40
30
20
MONTE CARLO CALC
10
OL---~----~----L-
o
0.5
10
__
~
____- L__
20
15
25
INDEXING ARITHMETIC TIME (I'secl
(AVERAGE TIME TO INDEX ONE INSTRUCTION INCL DECODE
AND STORING MODIFIED ADDR)
Fig. 15-- Computer speed vs. indexing arith. times for various arithmetic unit times: 4 main mems. 2.0 fJ.S; 2 fast mems. 0.6 fJ.Si 4
levels of look-ahead.
120
110
100
90
80
70
0
UJ
UJ
0..
IAU-I.4I'S
~
60
tJl
50
.!.A~~~
40
_____
--
---
}
FOR MESH CALC
Speed vs. Concurrent Input-Output Activity
Because of the relative time scales of I/O activity
and the CPU processing speeds, the simulator cannot take account the availability or non-availability
of data from I/O on the program being run. However, we can observe the effect on the computation
of - the I/O devices operating at different rates
simultaneously with computing.
Using the STRETCH control word philosophy, it
is possible to have a number of input-output units
operating at the same time the Central Processing
Unit is running. The Basic Exchange can reach a
peak rate of 1 word every 10 microseconds. The high
speed disk normally operates at 1 word every 4
microseconds. Since the mechanical devices take
priority over the CPU in addressing memory, the
computation slows down because of memory-busy
conflicts.
Fig. 17 shows an example of how internal computing speed is slowed as the I/O word rates are varied
continuously. At the theoretical "choke off;' the I/O
devices take all the memory cycles available and stop
the calculat~on. Notice that this condition can never
arise for any I/O rates presently attainable.
o
FOR MONTE CARLO CALC
_~:..E~T~l"_I~!T~~~I~~_I~~~~~ _______________ _
I ___~4~M=EM=~~Y~UN~IT~S~---------
30
I
-10%
I
I
20
-20-/.
10
OL---~----~----L---~----~--
o
0.5
ID
1.5
2.0
2.5
AVERAGE ARITHMETIC TIME (I'sec)
(EXECUTION TIME FOR "AVERAGE" OPERATION)
8UJ -30-1.
,
, ,,-
--
2 MEMORY UNITS
..,:---------
____ _
1//
0..
tJl
Z
Fig. 16-Computer speed vs. arithmetic times for various indexing
arithmetic unit times: 4 main mems. 2.0 fJ.Si 2 fast mems. 0.6 fJ.Si
4 levels of look-ahead.
",
:
/
;:;-400/.
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C)
~
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:I:
,I
u-50"1.
I-
zUJ
IMEMORY~~--- _ - - -
---
u
Arithmetic Unit Efficiency
"",..-1---~-60-/.
,.
I
One fallacy which is frequently quoted is that the
,/
I
./
I
goal of improved computer organization is to increase
/
I
-70-/.
/
I
'(
I
the arithmetic unit efficiency. Actually there are two
/1
I
reasons why this is not the goal in itself. The first is
-80-1.
u.
" \.--HIGH SPEED l
u.
that arithmetic efficiency depends strongly on the
I I DISK RATE '-"BASIC EXCHANGE
0
,
I
~ PEAK RATE
UJ
mixture of arithmetic and logic in a given problem
-90"/. 0
,
I
I
:I:
I
I
FOR MONTE CARLO PROB
}>
so that a general purpose computer cannot hope to
I
I
I
I
-100%
give equally high percentage utility to all. The second
2
15
20
10
reason is that the simplest way to increase the arithWORD RATE-MICROSECONDS BETWEEN CONSECUTIVE WORDS
metic unit efficiency in any asynchronous case is to Fig. 17-Internal computing speed. Percentage reduction in speed
caused by input-output devices referencing memory at different
slow down the arithmetic unit.
rates while the calculation is proceeding.
The real goal in improved organization is maximum overall computer performance for minimum
A STRETCH system with only 1 or 2 memory
cost. One will tend to increase the arithmetic unit units has less performance than a larger one for three
.
I
~
Cocke and Kolsky: Virtual Memory in the STRETCH Computer
reasons: (1) The top speed of the system is reduced
by the loss of memory overlap, (2) it has a larger
I/O penalty when I/O is run concurrently with the
computation, and (3) the smaller amount of data
which can be held in the memory at one time increases
the amount of I/O activity needed to do the job.
Note, however, that increasing the memory size on a
computer of conventional organization only improves
the third area.
A Study of Branching on Arithmetic Results in Stretch
93
bit" which would permit the programmer to
specify which way he estimates each branch
will most likely go. However this would place
a considerable extra burden on the programmer
for the gains promised. (It also uses up many
valuable OP codes.)
(4) It is realized that there is a "feedback" in such
decisions because the way in which the machine
guesses the branches will influence future programmers to write their codes to take advantage of the speed gain. The result is that the
statistics of the future will be biased in favor
of the system chosen for the machine, and thus
"prove" that it was the right decision.
One penalty of the non-sequential preparation and
execution of instructions 'used in STRETCH is that
if there is a branch in the problem code it spoils the
smooth flow of instructions to the indexing arithmetic unit. Any branch in a program will cause some
ACKNOWLEDGMENT
delay, but the most serious ones are the branches on
The general idea of "look-ahead" was under conarithmetic results which cannot be detected by the
by many people in IBM before the authors
sideration
indexing arithmetic unit in advance.
became
involved.
What is represented here is a
There are two fundamental ways in which branches
realization
of
the
detailed
logic of look-ahead, similar
on arithmetic unit results can be handled by the
enough
to
STRETCH
for practical simulation
computer.
purposes. The actual precise detail of the logic as it
(1) The computer can stop the flow of instructions appears In the STRETCH computer represents, of
until the arithmetic unit has completed the course, the accomplIshments of many individuals in
preceding operation so that the result is the STRETCH project.
known, then fetch the next correct instruction.
DISCUSSION
This places a delay on every A U result branch
M. Rubinoff: What happens to the look-ahead process if a sequence
whether taken or not.
(2) The computer can "guess" which way the
branch is going to go before it is taken and
proceed with fetching and preparing the instructions along one path with the understanding that if the guess was wrong, these
instructions must be discarded and the correct
pa th taken instead.
A detailed series of simulator runs were made
to study this situation and to decide which way
STRETCH should be designed. Some of the general
observations were:
(1) The performance variation in a problem with
considerable arithmetic data branching can
vary by approximately ± 15% depending on
the way in which the branches are handled.
(2) Holding-up on every branch seems to be less
desirable than any of the guessing procedures.
Some time is lost whenever a branch is executed rather than proceeding to the next
instruction. Unless there is an unusual situation
which there is a very large probability that the
branch will always be taken, the least time will
be lost if one assumes that the branch is not
taken.
(3) The theoretically highest performance would
be obtained if each branch had an extra" guess
of branch instructions is programmed, such as in the binary selection
of one of many subroutines? An example is the selection of the desired
piece of a piece-wise function approximation.
Dr. Kolsky: If it is an unconditional branch then it takes a correct
path.
Mr. Rubinoff: These are conditional?
Dr. Kolsky: The machine makes the assumption that the branch is
not taken. If the path is not taken then the branch time is covered up.
M. S. Maxwell (US Naval Weapons Lab.): Discuss maintenance on
diagnostic programs to insure proper operation of virtual memory.
Dr. Kolsky: The STRETCH machine has as one of its unusual
features a part of the interrupt system capable of recording the status
of the machine at the instant the interrupt occurs, so that one gets a
"snapshot" of the machine as of that moment. This occurs so you do
not have to go back and duplicate the error by running the program
over and over again. I think you can see by the way the virtual
memory operates that it would be very difficult to duplicate the error
again. This feature, whereby a snapshot is made at the time of the
error occurs, enables the engineers to go over the records and determine exactly what it was that caused the failure. Of course, the
machine has a very elaborate checking mechanism as was described
by Erich Bloch in his paper yesterday.
J. Anderson (Burroughs): Is the addressing of STRETCH's main
memory sequential within a memory unit or sequential across several
memory units?
Dr. Kolsky: The Los Alamos machine has six memories. Two are
alternating and the other four are sequential across all four.
R. MacIntyre (Bausch & Lomb): Is the virtual memory addressable
in case of a branch?
Dr. Kolsky: No, it is completely unavailable to the programmer. You
can see that one would get into some rather tricky logical problems
if it could be addressed. We discussed this at length and one gets
into a terrible spider web of logical complications when one does that.
94
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
A Combined Analog-Digital Differential Analyzer
HAROLD K. SKRAMSTADt
problem be scaled so that the maximum value of all
dependent variables will not exceed unity. Let each
of the two dependent variables x and Y consist of a
digital part and an analog part, denoted by the subscripts D and A, respectively. Thus, we have:
INTRODUCTION
HE ELECTRONIC analog computer, although
very useful in solving many problems, and particularly useful in solving dynamic problems
described by differential equations, suffers from limitations of accuracy and dynamic range. The digital
x = XD + XA
(2)
differential analyzer, although capable of providing
Y = YD + YA
(3)
any required degree of accuracy or dynamic range,
1 t
is slow in operation and subject to possible instability
Y = YOD + YOA + T
(XD + xA)dt
(4)
of solution due to quantization and the use of finite
o
difference calculus in integration. By combining
Let us assume time to be divided into discrete equal
analog and digital techniques, it is possible to comintervals of duration I1t, and that the digital parts of
bine the analog advantages of high speed and conx and Y can change only at times which are integral
tinuous representation of variables with the digital
multiples of I1t. We may then write for the value of
capability of high precision and large dynamic range.
Y at a time t somewhere in the nth interval:
Dependent variables in such a combined system
are represented by two quantities, a digital number, Y = YOD + YOA
representing the more significant part, and an elec1 {; (xD),l1t + (XD)n t t - (n -l)l1t} + xAdt (5)
+T
trical voltage representing the less significant part.
o
As in the electronic analog computer, the independent
variable is always time. Let us consider what form where (XD)i is the value of XD during the ilk interval
some of the required computer components, such as I1t. Fig. 1 shows a curve of x as an arbitrary function
integrators and multipliers, would take in such a of t. The area under this curve from t = 0 to any
arbitrary t would equal yT in equation (5), assuming
combined system.
that the first two terms (YOD and YOA) on the right
INTEGRATOR
of equation (5) are zero. The first term in the brackAssume we wish to obtain the following:
eted expression, represented by area 1, is the integral
of the digital part of x up to the time (n - 1)l1t.
1
The
second term in the bracket expression, repre(1)
Y = Yo + T
xdt
sented by area 2, is the integral of the digital part
of x between (n - 1)l1t and t. The third term, reprewhere x and yare functions of the time, and T is sented by area 3, is the integral of the analog part
the "time constant" of the integration. As in the of x from t = 0 to t.
digital differential analyzer, it is necessary that the
Fig. 2 is a block diagram of an integrator unit. It
contains an input digital register XD, a digital register
R, two digital-to-analog converters, a conventional
AREIA 3~
analog integrator, a special resettable analog inte,/
~~
an analog summer, and a comparator unit.
grator,
p{ A~
I----The
register
YD shown on the far right of the figure is
t;. I~ ~
/ARI::A 2
/
the input register of the next component to which this
unit might be connected in solving a problem. E is the
~~
analog reference voltage supplied to the digital-to'On
analog converters, and 'X is the digital equivalent of the
reference voltage E, chosen for any given problem so
.1
'°1 X,02
as to provide the desired compromise between speed
of solution and precision, but subject to the limitation
that / dx/dt /max should not exceed a/l1t. The number
(n-I),
o 61 261 361
nAI
of digits required in the XD and R registers will deFig. I-Diagram of integration method.
pend upon the minimum value of a for which provision is to be made; the minimum value of a will be
one in the least significant digit of the XD register.
t National Bureau of Standards, Washington, D. C.
T
I
[n-l
It
-
-----
It ]
95
Skramstad: Combined Analog-Digital Differential Analyzer
CLOCK
PERIOD t. t
CLOCK
PERIOD t. t
to ilt / a, as can be seen from the following. Assume
that from time 0 up to a time t during the nth interval ilt, the comparator has caused N subtractions
of unity from the R register, and the addition of
N to the YD register. The contents of the R register at
this time is:
CLOCK
PERIOD 61
I
I
i
-----1
oC INCREMENTS
REG&ER
r---
'-,-......--,,....J
u
I
n-1
Li=l (XD).
R =
Va-IVI tV2tv3)
(10)
- N
and the value of YD is given by
=EYA
--.c
RESETTABLE
ANALOG INTEGRATOR
TIME CONSTANTzAt
= YOD
YD
+ Na
(11)
Substituting equations (6), (7), (8) and (10) into (9)
and solving for YA, we obtain:
ANALOG VOLTAGE
FROM OTHER UNITS
n-1
Y A = a i~ (X D) i - N a
Fig. 2-Integrator unit.
+ ~t (X D) n
{t - (n - 1)ilq
t
At the beginning of each ilt period, the values XD
and R are sampled and converted to analog voltages
which are held constant during the period, unaffected
by future changes in XD or R which occur during the
period. The value of XD is then algebraically added
to the R register. The voltage VI, which represents
that portion of the prior summation of (XD)i ilt which
is of analog magnitude is given during the nth interval
iltby:
(6)
The voltage V 2, which provides integration of the
current XD value within the nth interval ilt, and which
is reset to zero at the end of this interval, is given by:
+ YOA + ilt
~ fXAdt
(12)
Adding equations (11) and (12), we have
Y
= YD
+ YA
+ :t [X=:(XD)
= YOD
i
+ YOA
lit + (XD). {t - (n -1)lIt}
!
+
xAdt ] (13)
Equation (13) is seen to be identical to equation (5)
if T = ilt/a.
AOO Xo TO A
EACH INCREMENT
_~:<:!~~R~~~r:!.T~_
CLOCK
PERIOD M
CLOCK
PERIOD At
INY-O-- ;
FROM OTHER UNITS
I
(7)
L
The voltage V 3 , which results from the purely analog
integration of the continuously varying analog part
of x, is given by:
V3 = -EYOA - ~
a
ilt
J
EYA
a
= V = -(VI
lFPER
THRESHOLD
VOlJAGE
LOWER
THRESHOLD
VOLTAGE
t
EXAdt
a
(8)
o
These three voltages are added in the analog summer
to give voltage V. The analog part of the output of the
integrator is equal to:
-
E
+V +V
2
3)
:,:<:!,!C..R~~E~!:S__
FROM OTHER UNITS
:
CLOCK
PERIODAt
Fig. 3-Multiplier unit.
(9)
If, at any time during a period ilt, the voltage V at
the output of the analog summer exceeds a predetermined upper threshold, this is sensed by the comparator and, during the next ilt interval immediately
following the addition of XD to R, unity is subtracted
from the R register and the number a is added to
the input register of the following unit (YD in Fig. 2).
Conversely, if the voltage V falls below a predetermined lower threshold, unity is added to the R register
and the number a is subtracted from the input register
of the following unit.
The time constant T of this integrator unit is equal
MULTIPLIER
Let us now investigate the form taken by a combined analog-digital multiplier. Suppose we wish to
obtain the product z = xy. Assuming, as before, that
each variable consists of a digital part and an analog
part, we have:
= XDYD + XAYD + XDYA + x~ YA (14)
where the subscripts D and A signify the digital and
analog parts, respectively. Assume, as before, that
time is divided into equal intervals of duration ilt,
and that the digital parts XD and YD can change only
ZD
+ ZA
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
96
at times which are integral multiples of flt. Fig. 3 is
a block diagram of a multiplier unit. It has three
digital registers for XD, YD, and R, three digital-toanalog converters, an analog summer, an analog multiplier, and a comparator unit. As before, E is the analog reference voltage and a is the digital value of the
reference voltage E, chosen for any given problem so
as to provide the desired compromise between speed
of solution arid precision, subject to the condition that
nei ther I dx / dt Imax nor I dy / dt Imax should exceed a / flt.
At the beginning of each period flt, the values of
XD, YD, and R are sampled and converted to voltages
which are held constant during the period. If, during
the period, XD receives an increment (or decrement)
a from another unit, YD is added to (or subtracted
from) R; and if YD receives an increment (or decrement) a from another unit, XD is added to (or subtracted from) R. If both XD and YD change during flt,
the additions to R must either be done serially, using
the new XD or YD obtained after each addition to R,
for the next addition to R, or some other system must
be used to obtain a true digital product XDYD. The
quantity XDYD can contain twice as many digits as
XD or YD; the more significant part will be of digital
magnitude, and appear in ZD, the input register of the
following unit; and the less significant part will be of
analog magnitude, and remain in the R register. The
reference voltage E is applied to the digital-to-analog
converter connected to register R, producing an output voltage V 1 = ER; the input voltage yAE / a is
applied to the converter connected to the register XD
producing-an output voltage V 2 = EXDYA/a, and the
input voltage EXA/ a is applied to the converter connected to register YD producing an output voltage
V3 = EYDXA/ a. An analog multiplier is connected to
the two analog inputs EYA/ a and EXA/ a. Its output,
attenuated by a, produces a voltage V 4 = EXAYA/a.
An analog summer sums the voltages Vb V 2, V 3, and
V 4 to produce a voltage V equal to - EZA/ a.
During the next flt after the voltage V exceeds (or
falls below) predetermined threshold voltages, unity
is subtracted from (or added to) the R register and
the number a is added to (or subtracted from) the
input register of the following unit (ZD in Fig. 3).
It should be noted that for small values of a the
analog multiplier may be omitted, producing a maximum error of a. For values of a less than the resolution of the analog components, say .001 or less, this
error is negligible.
If one of the factors to be multiplied is a constant,
the equipment required is simplified, since only one
digital register needs to be capable of accepting increments, and the R register receives additions from
only one other register. If the factor is a purely digital quantity, one of the digital-to-analog converters
and the analog multiplier may be omitted.
SUMMING
Summing may most easily be done by permitting
each integrator or multiplier unit to accept digital
increments and analog voltages from several units.
For example, in the integrator of Fig. 2, if the ± a
increments from a number of other units are connected to its x D register, and if the sum of the increments put out by these units is N a during any period,
the increment in XD would equal N a. The analog outputs from the other units would each be connected
to an input summing resistor in the analog integrator.
In the case of the multiplier unit, if the ± a increments from a number of other units are connected
to its x register, and if the sum of the increments put
out by these units is N a, YD would be summed into
the R register N times. The analog outputs from the
other units would be connected to inputs of an analog
summer whose output would form the analog input
xAE / a to the multiplier.
SOLUTION OF SIMPLE DIFFERENTIAL EQUATIONS
r----------------
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----------------,
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IL
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___ _
_ _ _ _ ...JI
Examples of the operation of this proposed combined system can be seen from following in detail how
some simple differential equations would be solved.
Let us consider first the differential equation
x = -x
v
RESETTABLE
ANALOG
INTEGRATOR
(15)
Fig. 4 shows a block diagrarrl of how a single integrator unit with output fed back into its input
would solve this equation. The voltages Vl, V 2 , V 3 ,
and V are those defined in equations (6) to (9).
Differentiating equations (6) to (9), we obtain,
since V l = 0
.
EXD
flt
V =ANALOG
INVERTER
Fig. 4-Integrator used,to solve:
:i:
=
-x.
.
V3
(16)
From the interconnections of Fig. 4, the following
expression must hold:
97
Skramstad: Combined Analog-Digital Differential Analyzer
.
a
Va =-V
(17)
~t
r-----------------------
1
1
1
I
1
V will then be given by the following differential
equation:
I
L
(18)
Subject to the initial conditions that at t = 0,
= XOD, and - V = EXOA/ a the differential equation will have the following solution:
XD
RESETTABLE
ANAlOG
INTEGRATOR
V
= EXD _ E(XOD
a
+ XOA) e - Xi
t
(19)
a
aV
, ,
o
ANALOG
INVERTER
E
XD -
i '
(20)
4
4
3
3
3
0
4
-.2
1
.4
-
1
"'I'" ""
'" '"
I""
-v
2
2
2
2
- 3 -I
1
.3
,
I--
-
~
x
1--
.............
.............
...........
I'-....
x'
(21)
.........i"-
=
-x'
(22)
Fig. 6 shows a block diagram of how two integrator
units would be interconnected to solve these equations. The voltages V h V 2, Va, V are those defined
by equations (6) to (9), and occur in the integrator
containing x; the primed voltages are those which
occur in the integrator containing x'. Differentiating
~
~
Fig. 6-Two integrators interconnected
td solve:
= x, X = -x'.
Another example of the operation of the proposed
combined system is the solution of the following pair
of simple differential equations:
.......... ............. .......... ......... ........ ......... ......... ......... T
1----
""-r-...
'""'"
2
f--
.........
I
I
ANALOG
INTEGRATOR
-v'
and x will be given by
x =
ANALOG
SUMMER
RESETTABLE
ANALDG
INTEGRATOR
ANALDG
SUMMER
-
equations (6) to (9), we have, since V l
""Xo
"'xo+x;:::
I>-....
.2
...........
r-.....
xDE
=
V'l = 0:
•
V
= - - - Va
V'
= M:"-
(23)
~t
...................... r---.,
-- . -1--- -- - 01
---- . -
- - -- -
02 03 04 0 ' 06 07 0.8 09
10
11
12
13 14
t
Fig. 5-Time history of solution of
x=
-x.
Fig. 5 shows in detail the quantities that would
appear in the XD and R registers, the voltages VI, V 2 ,
Va, and V as functions of the time, using the following parameters:
E = 100 volts
XOD =
0.5
a
XOA
= 0.1
~t
xDE
The threshold values on V for initiating decrements
to the XD register and subtracting one from the R
register are plus and minus 50 volts. In this example,
since a = 0.1, the precision obtained in solving this
equation should be 10 times that which would be
obtained in solving this on a purely analog computer
with analog components of equivalent precision to
those of the combined system.
(24)
From the interconnections of Fig. 6, the following
expressions are seen to hold:
V· a
=
+ ~ta V'
(25)
V'a
=
-!::.. V
(26)
= 0.1 sec
= 0
V'a
~t
The quantities V and V' therefore will be given by
the following differential equations:
v
= xDE ~t
~ V'
(27)
~t
(28)
Subject to the condition that at t = 0,
XD
=
XOD,
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
98
= X'OD' V = x'oAE/a, - V' = xOAE/a; these
differential equations will have the following solution:
·X'D
V=
E,
- X D
-
a
+.3
')
at
+ -E(,
X OD + X OA COSa
~
+.2
E(
). at
+;
XOD + XOA SIn ~t
V'
E
= - XD a
E
- (XOD
a
+
XOA)
+.1
at
-.1
~
-.2
a
E
V'
-.3
-.4
= (XOD
+ E~ V
at
+ XOA) cos ~t
(X ,OD
' ~t
at
+ X 'OA) SIn
( X ' OD
+
')
COS
X OA
(31)
ot
~t
•
at
+ ( XOD + XOA ) SIn ~t
(32)
~u IlIt~~J'1.ILJUIUU'~UL,.N"'""-~ 1lr] H
-VIII
-I---+--+--+-+---+--+---+--+----I
COMPONENT REQUIREMENTS
~'~IJ'~~~'~I_1~~~~~~~~1w~m@~~
1
-+-,--+-1--+--+---1-f---t---- -
1-1
1--- --
-+--+--+---1
I
I
- v 3 t--*-::::-t--+--+---1-I---+--+--+----l7-"=tf------1r-t---+---i
A-I'-I'---..
//
Fig. 7-Time history of solution of
x'
= x, ~ = -x'.
Fig. 7 shows in detail the voltages which would
appear as a function of the time when solving the
above equation, using the following values of the
various parameters:
E
=
XOD =
As in the previous example, the threshold values
on V and V' for initiating positive or negative increments to the X'D or the XD register, are plus and minus
50 volts, respectively. Fig. 8 shows the results of
combining the digital and analog portions. The
stepped curves are the digital part only; the smooth
curves are the sum of the digital and analog parts. As
in the first example, the precision attained should be
10 times that which would be obtained solving these
equations on an analog computer with analog components of precision equivalent to those used in the
combined system.
-
~-L-1---Vz !
t
Fig. 8-Plot of x and x' as functions of time.
-
X' = X'D
VJ
(30)
and the quantities X and x' will be given by the following expressions:
X = XD -
\
0
cos -
E(,
' ) • at
+:;
X OD + X OA SIn ~t
L \1
(29)
100 volts
0.5
a =
XOA
0.1
=0
~t =
x' OD
=
0.1 sec
0
X' OA =
0
N ow a few words on the characteristics needed in
t he hardware to realize the above components. For
a maximum speed-precision product to be obtained,
the value of At should be as small as possible consistent with hardware limitations. The smaller ~t is
made, however, the greater the bandwidth required
in the operational amplifiers, since the analog voltages must be capable of a full scale voltage excursion
E during the time ~t. The digital-to-analog converters
should be capable of holding their output values
constant during each period of ~t and equal to its
value at the beginning of the period, and then rapidly
changing to its new value at the beginning of the
next period. In the case of the integrator, the necessary additions of XD to R, subtractions of ± 1 from
R, and incrementing the input registers of following
units and, in the case of the multiplier, the additions
of XD and YD to R, subtractions of ± 1 from R, and
incrementing the input registers of following units
must all be completed within the period At. In the
integrator unit, the resettable analog integrator
might well consist of two analog integrators with
switching between them so that each is used to integrate during alternate ~t periods while the other is
being reset.
Skramstad: Combined Analog-Digital Differential Analyzer
DISCUSSION AND CONCLUSIONS
There are a number of problems associated with
this combined system that have not yet been investigated. One of these, which this computer has in
common with both analog and digital differential
analyzers, is that of proper scaling so as to prevent
overflowing of the digital registers or saturation of
the analog integrators. Another is the choice of the
threshold voltages for the comparator units. It is
possible that the best value for both upper and lower
threshold voltages should be zero - requiring a positive or negative digital increment to be sent to the
next unit each ~t, depending upon the sign of the
voltage V. The problem of scaling and choice of
thresholds are interrelated. and it should be possible
to exercise some control over the overloading of
analog integrators by proper choice of the threshold
voltages.
The number of digits to be carried in the digital
registers depends, of course, on the minimum value
of a for which provision is to be made. In general,
the R registers should contain one more binary digit
than the other registers to prevent overflow under
conditions where a large XD of the same sign as R is
added to R.
For any particular problem, the value of a to be
chosen depends upon the particular compromise
between precision and speed of solution desired. As a
simple illustration, consider integration of the function x = A sin wt, and assume ~t equals .001 second,
a = .001, and A is 1. Since the maximum time rate
of change of this function Aw should not exceed a/ ~t,
the highest frequency representable at full-scale amplitude would be w = a/ A~t = 1 radian per second,
and the precision (assuming an analog resolution of
.001) would be one part in one million. If we chose
a = .1, the highest frequency representable at full
scale amplitude would be 100 radians per second, and
the precision would be one part in ten thousand.
The combined analog-digital differential analyzer
of the type described shows promise of overcoming
some of the limitations of present designs of differential analyzers which use purely analog or purely digital techniques. Also if analog components of sufficient
bandwidth are available, the precision-speed product
of this combined system should be greater than that
possible with a parallel digital differential analyzer
having equal length digital registers and equal iteration rate, by a factor dependent upon the resolution
of the analog components - perhaps a factor of one
thousand.
The greatest usefulness of the proposed system is
believed to be on problems where the precision required is of the order of 10 to 100 times that obtainable by analog methods, yet requiring the real-time
speed of analog methods. In this case, integrators and
multipliers of the combined system would contain
99
short digital registers and only moderate requirements would be put on the speed of switching circuits and the bandwidth of the analog components.
Work is under way at the National Bureau of
Standards to construct breadboards of two integrator
and two multiplier units, each capable of receiving
inputs from two other units. The digital registers
and digital-to-analog converters are being constructed from transistorized digital building block
packages developed at NBS, and the analog components from commercially available wide band
amplifiers. These units are planned to have 7 bit plus
sign input registers, 8 bit plus sign "R" registers, an
analog reference voltage of 10 volts, and operating
with a ~t of one millisecond.
Acknowledgment
The author wishes to acknowledge the assistance
of the Navy Bureau of Aeronautics in supporting the
construction of the breadboard units for evaluating
the proposed computer system.
DISCUSSION
M. Rubinoff: I note there is no analog to digital conversion in the
drawings. Is this true for the entire system?
Dr. Skramstad: This is true of the entire system. At no time do we
have to convert an analog voltage to a digital quantity. Going from
digital to analog is the easy way.to go.
Mr. Rubinoff: I believe you said something about - I hope I am
quoting you correctly - this system has 10 times the precision of an
analog computer. What does this mean, 10 times as many digits?
How does this compare with the DDA with greater precision?
Dr. Skramstad: The factor 10 applies only to the example shown; the
actual factor depends upon the value chosen for a. In the example
given, assume that 100 volts could be divided to a resolution of a
part in a thousand, say, so that you might say that a tenth of a volt
would represent, in a way, the least significant digit. Now in the
examples I showed, the analog voltages would go through this 100
volts 10 times as the variable goes from zero up to unity. The effective
resolution would thus be a part in 10,000.
D. Cohen (Airborne [nst. Lab.): Does the comparator have to be
more accurate than in the pure analog computer to achieve the 10
times resolution?
Dr. Skramstad: The comparator does not have to be precise; it only
detects that a theshold voltage has been exceeded sometime during
the interval.
Mr. Labin (AERO, France): Would the cooperation of a digital block
to the differential analyzer allow treatment of non-linear equations,
at least approximately?
Dr. Skramstad: I think it would. I have not had time to go into what
various non-linear components would be like in this system. I believe
non-linear components could be devised that would work with the
system.
N. Nesenoff (Republic Aviation): Could you indicate the percentage
of equipment saved by the combined analog-digital system when
compared to the equipment required by a purely digital system of
equal accuracy?
Dr. Skramstad: This would be a hard one to put a figure on. I think
the big advantage here is that you still have what you might call
real time speed capability for real time simulation of physical systems. As you all know, analog computers a.re very useful in real time
100
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
simulation of dynamic missile systems and aircraft systems, but often
there are a number of variables that have to be carried to higher
precision than the analog is capable. This system would allow you to
carry those variables in the combined systems where additional
precision is required.
tion of physical systems where the precision of the analog computer is
not quite great enough, and thus by the addition of short digital
registers and digital components to an analog system, it would be
able to handle these cases.
Mr. N eseno:ff: Did you ever build a computer of this type?
E.M.Ginsberg(BurroughsCorp.):Pleasecommentontheaccumblation
and propagation of errors due to tolerances in the two systems and
incurred by overlapping at different precision points.
Dr. Skramstad: No, this is just an idea. We are in the process of building up a breadboard to tryout the idea. We are planning a device
carrying 7 bits plus sign in the X register, 8 bits plus sign in the R
register, and voltage of 10 volts. I hope to be able to report how this
works at a later date.
Dr. Skramstad: Any errors due to drift in amplifiers in the analog
portion can affect only the precision of the analog part, and these
errors would be decreased in the overall solution by the factor Alpha.
F. Verzuh (MIT): Comment on the solution of general integration:
W = I/ K f udv where v = time using your device. (Chairman: I
think he is getting back to the fact that digital differential analysers
will work with any variable whereas the analog computer insists that
the independent variable in the integration is time.)
Dr. Skramstad: This is the limitation of this system, just as it is a
limitation of the electronic analog computer. You have to devise the
program in such a way as to associate time as the end variable.
Mr. Rubinoff: So it loses the advance that the digital has?
Dr. Skramstad: That is right. The multiplying device, however, is
working only in dependent variables. For problems not involving
integration, you are free of this limitation.
D. A. Bourne (IBM): Please summarize what you consider the most
important advantages of a hybrid computer.
Dr. Skramstad: Well, I think I just mentioned that in the answer to
another question. I think the greatest usefulness would be in simula-
Mr. Ginsberg: Please comment on any effect in slew time with this
system as compared to a DDA.
Mr. Rubino:ff: Slew time is the rate at which numbers can be changed
in the differential analyzer, which limits the simple DDA.
Dr. Skramstad: I think some of the same techniques used in DDA
would apply directly to thif3 computer. I would think it would be a
similar problem to that of the DDA.
K. Enslein (Brooks Research): How about the possibility of two
different Deltas, one coarse and one fine?
Dr. Skramstad: This is something I haven't considered as yet. It
might be worth looking into.
M. Tayyabkhan (Union Carbide): Would the use of floating point
arithmetic in the digital registers solve some of the scaling problems
of analog computers?
Dr. Skramstad: Well, now there is a possibility here. Again. this has
not been investigated so that I cannot give a definite answer to that
one.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
101
The System Organization of MOBIDIC B
STANLEY K. CHAnt
OBIDIC B is an all transistorized, militarized
computer mounted in a standard Army trailer.
It is a general-purpose, parallel, binary, synchronous, fixed point, and duplexed data processing
system.
It contains two basic processors, identical in characteristics and internally tied to the same system
transfer bus. Both processors share a common set of
input-output devices and each processor is capable
of operating on an independent program without
interference. They are also capable of duplex operations, allowing either processor to monitor and exert
control over the other.
In addition to the 8192-word high speed Core
Memory in each processor, there exists a 50 millionbit Mass Memory. This memory is treated as an
input-output device, addressable by in-out instructions. A Data Retrieval U nit is incorporated to
facilitate aata searching from the Magnetic Tape
and the Mass Memory. The control console is also
duplexed, containing two independent and identical
panels, one for each processor.
M
DATA equipment. Each of the two central processors
is a general-purpose computer. They can use any of
the input-output devices available and either processor can run separate programs without interference from the other. In addition, the two processors
can operate together and communicate with each
other through an in-out device such as a magnetic
tape. Either processor can use the other's core
memory through an input-output device. It is also
possible for either processor to monitor and exert
control on the other through the direct connections
between them.
SPECIAL REQUIREMENTS
There are 4 major requirements of a special nature
imposed on this computer. The first is that MOBIDIC
B is to be a duplexed data processing system. The
second requirement is that it must be compatible
with other MOBIDIC computers. Compatibility is
sought not only through instruction type and word
format, but also through the interchange ability of
input-output devices and the physical element-cards
and packages. Minimum equipment is another design
criterion. This is achieved by having all full-length
registers simulated in the core memory and also by
INTRODUCTION
mechanizing some of the infrequently used instrucThere are a number of large-scale, general-purpose, tions through automatic subroutines. Only two fullmobile digital computers being developed at Syl- length working registers are used within each procesvania!. They are known as the MOBIDIC family of sor. Data retrieval capability is the fourth of the
computers. MOBIDIC C and D are identical in special requirements. Data stored on either the
internal design to MOBIDIC A 2. They differ only in magnetic tape or the mass memory must be retrieved
peripheral equipment.
at full device speed. This continuous and speedy
MOBIDIC B is the second member in the MO- retrieval ability necessitated the incorporation of a
BIDIC family·. It will be used primarily in the field data retrieval unit together with the addition of
to meet the Army's data processing requirements, some special instructions.
and is to be installed in a standard 30 foot Army
trailer. MOBIDIC B contains all the instructions
INSTRUCTIONS AND WORD FORMAT
utilized in MOBIDIC A and also an additional 12
new instructions. To minimize equipment, some of Instructions
the instructions have been made subroutines which
There are 64 instructions in MOBIDIC B (Table
are initiated automatically.
1). They are classified into 3 categories, namely,
MOBIDIC B is a duplexed data processing system.. directly-mechanized instructions, subroutine instrucIt contains two identical central processors connected tions, and special instructions. There are a total of
to a common system transfer bus. Each central 40 directly mechanized instructions. In most cases,
processor has an individual real time system which the execution time has a variation of 2 p,S. The instrucprovides direct communication with external FIEL- tion LGM, for example, may sometimes be exe'cuted
in 36 p,S instead of the 38 p,S shown in Table'l. The
t Sylvania Electric Products, Inc., Needham, Massachusetts.
IJ. Terzian, "MOBIDIC Computer Series," THE SYLVANIA variation is due to the fact that the system bus is
time-shared by both processors. The system bus may
TECHNOLOGIST, Vol. XII, No.3, July, 1959, pp. 58-64.
or may not be available to the processor which is
2J. Tersian, "System Organization of MOBIDIC A," presented
at the 1957 WESCON Convention, August 20, 1957, San Francisco, executing the instruction that requires access to it at
that particular insta~t. The times given in Table' 1
California.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
102
TABLE I
MOBIDIC B INSTRUCTION REPERTOIRE
Op Code
Abbr.
Type
Time (fJ-s)
Instr. Description
Direct Sub Special
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
HLT
RPT
LGM
LGA
LGN
SEN
SNS
SNR
CLA
CAM
ADD
ADM
CLS
CSM
SUB
5MB
MLY
MLR
DVD
DVL
ADB
SBB
BSPL
BSPL
SHL
SLL
SHR
SRL
CYS
CYL
SLA
NRM
TRU
TRL
TRS
TRX
TRP
TRZ
TRN
TRC
STR
LOD
MOV
LDX
RPA
MSK
BSPL
TRY
BSPL
BSPL
BSPL
BSPL
BSPL
BSPL
SKP
BSP
RAN
RRV
ROK
SCH
WAN
WWA
WOK
RWD
24
D
R
-
38
38
36
28
28
28
36
36
44
44
36
36
44
44
88-774
88-786
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
R
R
R
R
-
30-66
46-118
30-66
S
S
D
D
D
R
-
30-66
D
R
-
30-66
D
28
R
D
R
R
R
-
-
26
26
26
D
D
D
R
-
34
36
36
D
D
D
-
R
R
R
-
S
-
38
D
S
S
S
S
S
S
-
30
30
30
30
30
30
30
30
30
30
D
D
D
D
D
D
D
D
D
D
Halt
Repeat
Logical multiply
Logical add
Logical negation
Sense
Sense and set
Sense and reset
Clear and add
Clear and add magnitude
Add
Add magnitude
Clear and subtract
Clear and subtract magnitude
Subtract
Subtract magnitude
Multiply
Multiply and round
Divide
Divide long
Add beta
Subtract beta
MOBIDIC B special
MOBIDIC B special
Shift left
Shift left long
Shift right
Shift right long
Cycle short
Cycle long
Shift left and logical add
Normalize
Transfer unconditional
Transfer & load PCS
Transfer to PCS
Transfer on index
Transfer on positive
Transfer on zero
Transfer on negative
Compare
Store
Load
Move
Load index
Replace address
Mask
MOBIDIC B special
Transfer on index B
MOBIDIC B special
MOBIDIC B special
MOBIDIC B special
MOBIDIC B special
MOBIDIC B special
MOBIDIC B special
Skip
Back space
Read alphanumeric
Read reverse
Read octal
Search
~rite alphanumeric
Rewrite alphanumeric
Write octal
Rewind
are maximum.
There are 15 subroutine instructions. These instructions are performed through subroutine programs,
which must be stored in memory and executed auto-
matically. As such, all instructions used in the program to execute the sub-routine instruction must be
of the mechanized type. Nine of the MOBIDIC B
OP codes are unassigned. They are available to perform any special subroutine operation that may be
required in a particular application. Whenever one
of these "special" instructions is decoded, operation
is automatically transferred to a unique location
from which the program is re-routed to the desired
subroutines.
According to their logical functions, the 64 instructions can be classified as follows: 16 arithmetic
operations, 17 sequencing and indexing, 10 inputoutput; 12 editing and data handling; and 9 special
purpose instructions.
Word-Format
The length of the MOBIDIC B word is 38 bits, the
length used in other MOBIDIC computers. 'I he word
format is illustrated in Fig. 1. Numerical data is
represented by a fixed point, magnitude and sign
conventions. Magnitude is registered in bits 1 to 36.
The binary point is understood to be placed between
bits 36 and 37. Bit 37 is used for sign of a number
stored and bit 38 is used as a parity check bit.
Alphanumeric data is represented in the same
manner as numeric data, except that the sign bit
is eliminated and the 36 pits are grouped into 6
alphanumeric characters. Since MOBIDIC uses a
weighted code, alphanumeric data can be sorted
without conversion to binary form by direct use of
the logical and arithmetic operations.
NUMERICAL DATA
PARITY
I
31
I
MAGNITUDE
SIGN
37
136
11
ALPHANUMERIC DATA
PARITY
SPARE
I
31
I
37
SIX ./N CHARACTERS
I
I
31
37
IN-OUT INSTRUCTIONS
PARITY
SPARE
I
31
I
37
1I
136
STANDARD INSTRUCTIONS
PARITY, SPARE
INDEX
REGISTER
OP CODE
136
3'1 ~
36
311
~
k
MAJOR
ADDRESS
28127 ~ 16115
WORD OR
BLOCK
0' CODE
1
y
MINOR
ADDRESS
DEVICE
ADDRESS
22121
I
a
1I
MAJOR
ADDRESS
16115
a
J
Fig. 1-MOBIDIC B word format.
A standard instruction word
parts:
IS
divided into 6
(1) Major Address (a): Bits 1 to 12 specify a
ffiemory address while bits 13 to 15 specify
which memory will be used. Since ma~y of
the internal MOBIDIC B registers are addressable, one of the eight configurations for
bits 13 to 15 represents internal register
addresses. The actual register addresses in
these cases are specified by bits 1 to 5.
(2) Minor Address ({3): Bits 16 through 27, the {3
bits, have several uses, depending on the
particular instruction being performed. They
may be loaded into or added to the contents
of an index register. The {3 bits, either alone
Chao: System Organization of MOBIDIG B
(3)
(4)
(5)
(6)
or in combination with 'Y may also be used
to specify a second address.
Index Register ('Y): Bits 28 to 30, 'Y bits, are
used primarily for indexing. They specify
which, if any, of the Index Registers are to
be used with the instruction. For some instructions, 'Y is used as part of a second
address.
OP Code: Bits 31 to 36 designate the instruction to be performed.
Spare: Bit 37 is a spare.
Parity: Bit 38 is the parity bit.
The format for input-output instructions is identical to that of standard instructions except for the
assignments made to bits 16 to 30, thej and k portions
of an in-out instruction. The j bits, 16 to 21, are used
to specify the particular input-out device addressed.
Sixty-three input-output devices may be handled in
this manner. The k bits, 22 to 30, are used to specify
the number of words or blocks to be processed.
OVERALL SYSTEM DESCRIPTION
The block diagram of the MOBIDIC B system is
given in Fig. 2. In it are shown: two identical computers (processor 1 and processor 2), two in-out
converters, a data retrieval unit, a mass memory
unit, two real time systems, and a family of in-out
devices. The two processors are fed by a common
system clock to facilitate system synchronization.
They are connected to a comon system transfer bus
and also share the same in-out system. The processors
can operate independently as separate computers or
can communicate with each other through magnetic
tape. It is possible for either of the two processors to
give a set of instructions which will read from 0::' write
into the memory of the other processor. It is also
possible for one processor to monitor the other
through the signal lines connecting them directly.
Furthermore it is possible for one processor to contrdl
and give commands to the other processor.
SYS BUS
====;;=====r=!:====~===::::::!:::;==:::::r=
1-0 BUS 1
103
devices including the mass memory unit. The converters are assigned to either of the two processors on
a first-come-first-serve basis. Since the two processors
are conneoted to a common system bus, it is entirely
possible that both may want to get on the system bus
at the same instant. To avert this uncertainty, the
system bus control circuit is used to continuously
assign the system bus to the processors alternately.
Each is given a 2 }J.S period to use it. Therefore, a
waiting period of 2}J.s may be required at an arbitrary
time. The danger of both processors trying to get to
the same converter is also avoided by the same control
circuit.
In addition to the standard family of MOBIDIC
in-out devices, the MOBIDIC B system includes a
50-million-bit memory which is also treated as an inout device. Data transfer to and from the mass
memory will be handled by the converter through the
in-out bus. The data in the mass memory is arranged
in blocks, separated by block start and block end
marks. The block number on each track is addressable. Both the track and block addresses must be
loaded into the mass memory control unit prior to
giving the write or read instruction. These addresses
are sent out from the processor through the converter,
similar to the manner by which the data is transf~rred.
The data retrieval unit is designed to assist the
open format search program. A retrieval program
examines the specified fields to determine whether or
not the search criteria are satisfied. Closed format
search can be accomplished entirely by programming
and does not require any auxiliary equipment.
The two real time systems enable the processors to
communicate with other data processing equipment
external to the MOBIDIC B system. Each has a
fixed assignment to serve one definite processor and
is not accessible to the other processor.
On the other hand, the balance of the entire inputoutput system does not have a fixed assignment.
Operating on a first-come-first-serve basis, it is
entirely possible for one processor to automatically
monopolize the use of both converters, the data
retrieval unit and a complement of devices. Without
a converter the other prucessor cannot reach any
device even if it is available. Under such a circumstance, the other processor would have no choice but
to wait for a converter to become available. In some
special cases, the other processor may have j'ust
received, through its own real time system, an urgent
request which requires data processing through the
service of a converter. Upon receiving such a request,
it is possible for the other processor to shorten the
in-out operation of the first processor, making the
converters available.
Fig. 2-MOBIDIC B system block diagram.
The converters serve as format control and synchronizing buffers. They are capable of handling all
BRIEF DESCRIPTION OF PROCESSOR
Since minimum equipment is a major design re-
104
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
quirement, most full length registers normally existing in other MOBIDIC Computers are stored as
locations in the memory. These reserved memory
locations are referred to as simulated registers.
Simulated registers include the accumulator, the
Q-register, the B-register, the program counter, the
program counter store, and seven index registers.
They can be addressed in exactly the same way as
their counterparts in other MOBIDIC computers.
As shown in Fig. 3, only two full-length physical
registers are used in each MOBIDIC B processor,
the memory register (MR) and the control Register
(CR). These registers and other essential parts in
the processor are described as follows:
Timer The timer, containing three counters, receives pulses from the system clock. The processor
executes instructions by proceeding through a sequence of events. Certain events, such as memory
operations, occur so frequently that a separate
counter TM is used to control these operations. The
execution of instructions requires several memory
operations. Counter TI indicates which of the several
memory operations is currently in progress. Finally,
if an input-output access to the central processor is
required, the instruction execution must be interrupted and a new sequence of events must start.
A third counter TB controls these input-output
processing operations.
Core Money Each processor of the MOBIDIC B
system is provided with two 4096-word core memories
with a read-write cycle of 8 J.l.S. It can be readily ~x
panded to 4 memories per processor when desired. It
can be ultimately expanded to 7 memories, totaling
28,384 words.
Memory Register The MR is directly connected
to the memory. It is a 38-bit register and is used
as the memory in-out register. The MR is also
used as an arithmetic register during execution of
the instructions.
Control Register The CR serves' primarily as a
37-bit arithmetic register corresponding to the accumulator in MOBIDIC. In addition, the first 15
bits of CR are also used as the memory address
register during initial access to the high-speed
memory.
Decoder Register This is a 6-bit register used to
store the instruction while it is being executed. Its
output ihterprets the instruction stored and energizes appropriate control lines to initiate execution
of the instruction specified.
Control The control unit contains the logical
circuits to control all of the detailed operations of
the computer.
Special Address Control The special address
control unit contains the decoders and control circuits to address the core memory locations which are
reserved for special registers of the processor and the
data retrieval unit. Among the registers specified by
Fig. 3-MOBIDIC B processor.
the special address control unit are most of the
simulated registers. The contents of these registers
can be transferred to the MR and then to the CR
whenever it is requested.
, T Counter The T Counter is a 7-stage counter
used in both shifting and mUltiplying operations.
System Clock The system clock provides standard
p and t pulses spaced one microsecond apart to the
entire system. There is a separate clock for each
processor. This makes the processors identical. One
system clock may be used to control the entire system
operation when the processors are working together,
depending upon which processor is in full control of
the program.
System Bus Control The system bus control circuits regulate and direct the flow of traffic between
the two in-out converters, the data retrieval unit,
and the two processors. These control circuits give
either processor access to the system bus.
INPUT-OUTPUT SYSTEM
A more detailed description of the various components in the In-Out system will now be given.
Reference should be made to Fig. 2.
In-Out Converter There are two in-out converters
in MOBIDIC B. They are used as buffers between
the input-output devices and the central processors.
They assemble data coming in from a device and put
it into MOBIDIC word format before transferring
it to the central processor. Conversely when data is
to be sent out to the device from the central processor,
the converters decompose the standard MOBIDIC
word and reassemble it into the proper format for the
particular device which is to receive it. In addition,
converters also have the function of synchronizing
the operation of the devices with that of the central
processor. In this way, the information transfer
-between the converter and the device can take place
quite independently from the operation of the central
processor. Internal computation is only interrupted
during access to the memory.
Data transfers between converters and processor
Chao: System Organization of MOBIDIC B
memories are handled on a "busy-bit" basis over the
system bus. As soon as a converter is selected the
processor will transfer the entire in-out instruction
to the converter. The processor subsequently goes on
to execute the next instruction and exerts no further
control over the converter. The converter, taking
upon itself to execute the instruction it has just received, proceeds to communicate with the device
addressed and sends out or receives data from
the device. When the converter is ready to send in
or to receive another word from the processor, it will
signal the processor by raising a busy-bit. Detecting
a busy-bit, the processor will interrupt its operation
and take care of the converter.
Real-Time System There are two identical real
time systems. Each system consists of an input
register, an output register and an input address
register. Each real time system is assigned to a
processor. These real time systems can be used to
provide the communication link between the two
central processors of a single MOBIDIC B system,
between two MOBIDIC B systems, between a
MOBIDIC Band MOBIDIC A computer or with
other FIELDATA computers and communication
equipment. In all cases except the last, the real time
output register in one real time system can be directly connected to the real time input register of
the other real time system. In the FIELDATA
application, a buffer unit may be required between
the real time system and the external equipment.
For example, a Kineplex is required when the
teletype communication equipment is connected to
MOBIDIC B.
Data Retrieval Unit The DRU is a special unit
designed to assist the data retrieval program from
the storage fiiles. It is connected to the system bus
as well as the in-out bus. It will examine all the data
being transferred from the magnetic tape (or mass
memory) to the converter. After extracting the desired portion, the data is then sent to the core memory
for further processing.
Mass Memory The mass memory is needed to
provide an exceptionally large data storage capability.
It consists of 8 magnetically coated discs, giving a
total of 16 usable disc sides. There are 4,096 tracks
on which the data can be stored. Storing is done in a
serial-serial manner which can be continuous from
one track to the next. Track switching is done automatically. There are two magnetically engraved
clock tracks, one at 150 KC bit rate and the other at
225 KC bit rate. The ma)timum random access time
of the mass memory is less than 0.25 seconds.
Magnetic Tapes A total of 8 magnetic tapes are
currently provided in MOBIDIC B. They could be
either the commercial FR-300 type or the militarized
type. They have 8 channels which incorporate a
parity error detection channel. The nominal tape
speed is 150 inches per second (reversible) with
105
approximate start and stop time of 1.5 ms. The
nominal character rate is 45 KC.
Flexowriter The Flexowriter is a special electric
typewriter that operates at a speed of 10 characters
per second. It can be used on- or off-line or as an
output device for producing hard copy or punched
paper tape.
Paper Tape Reader There are two photoelectric
paper tape readers, one being a 5-hole and the other
an 8-hole reader. These input devices have a nominal
reading rate of 270 characters per second.
Paper Tape Punch The two paper tape punches
include a 5-hole punch and an 8-hole punch; both are
directly adaptable to the reader. Both types prepare
punched paper tape at a nominal character rate of
100 per second.
DUPLEXING CAPABILITIES
The two MOBIDIC B processors are tied to a
common system bus and share a common set of inout equipment. It is beyond the scope of this paper
to give a detailed description of the entire duplexing
capabilities existing in MOBIDIC B. A separate
technical paper is to be published treating this subject
in greater detail. Briefly, there exists a set of control
lines connecting the two processors directly. Through
these lines the operating status of one processor can
be monitored by the other processor. Through these
control lines also, one processor can exert control and
give command to the other processor in a limited
manner. In particular, one processor can prevent the
other from coming to a complete halt condition, thus
keeping the other processor in a state of readiness to
accept information which may be transferred into it
from the first processor. Moreover, one processor can
restart the other after that processor has completed a
program. In addition, one processor can give an
input-output instruction which is to be executed by
the other processor. For example, one processor may
give a write instruction to have information contained
by the other processor written out onto a magnetic
tape. That same controlling processor can subsequently give a read instruction to have the same
information read from the magnetic tape back into
its own memory for immediate use. Thus one processor can effectively make use of the data stored in the
other processor's memory. Conversely, one processor
could give a set of instructions which will result in the
transformation of data from its memory into the
other processor. For this type of operation the programs in the two processors must be coordinated.
Some circuits are built into the MOBIDIC B system
to direct such traffic bwtween the processors and
avoid any uncertainty as to the direction of information flow between them.
Full utilization of the "built-in" duplexing capabilities of MOBIDIC B should provide a challenge to
the imagination and foresight of programmers. Many
106
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
programs could be written to take advantages of
these duplexing facilities. For example, one processor
could enter into a different program as a result of the
decisions made by the other processor. Also, one
processor could take over the other's task if it discQvered that the other processor was either overloaded
or'incapacitated.
processor to the in-out system are made only through
the memory register. Traffic coming in and out of the
memory as well as going to and from the in-out
system frequently create logical problems. Resolution of these logical problems results in a slight
reduction of computation speed.
The internal duplexing features introduced in
MOBIDIC B represent a new approach in the design
MARGINAL CHECK AND CONTROL CONSOLE
of a large scale, general purpose data processing
system. There will undoubtedly be many areas where
An automatic marginal checking system is incorsuch an approach is highly desirable from the standporated in MOBIDIC B. The checking circuit is so
point of reliability and economy.
designed that the bias voltage in each row of every
rack in the computer is modified by a predetermined
ACKNOWLEDGMENT
amount. While the bias voltage of the row is maintained at this changed value, a simple check program,
Many people have contributed to this project. In
which is stored in the computer, will be run through particular, Messrs. W. S. Humphrey, Jr., and J.
once. The result of this program can be observed, an Terzian, who have been directing the system and
error condition will be indicated by a pilot light on logical design effort on this project have made numerthe console. All rows are automatically tested in ous suggestions and contributed heavily towards the
succession in such a manner. It is possible to bypass original concept for this entire system. Mr. G.
some racks in the computer so that marginal voltages Rocheleau was instrumental in the detail design of
are not applied and checking is not performed on the central processor and the design of duplexing
them. This is necessary to enable one processor and capability in MOBIDIC B.
some associated input-output equipment to be in
continuous operation while the other processor is
DISCUSSION
undergoing test.
M. Rubino:fJ: Would you include simultaneous solution of the same
The control console for MOBIDIC is also duplexed. problem in what you mean by duplex operation?
It consists of two independent and identical consoles Mr. Chao: Yes I would. For instance, you can have two processors
assembled side by side. Each console is permanently operating simultaneously, each doing a part of the entire problem,
connected to one processor and thus communicates or you can have both processors operating on the same problem and
only with its assigned processor. For ease of operation, duplicating the computation for reason of reliability.
each control console is divided into 6 horizontal Mr. Rubino:fJ: You can make comparisons?
areas. At the very top of the console is located the Mr. Chao: Yes, you can make comparisons at the end. or any conmarginal check voltage control. Immediately below venient intermediate point. Note that a simple yes or no type of
could be made through the mutual monitoring facilities
this area is the control for the power to the computer. comparison
built into the hardware. For more elaborate comparison, data would
The master clock selector is also located in this area. have to be transfered over through the input-output device.
The display register is situated next in line, extending C. W.Einolf(IBM): Would you discuss mass memory more thoroughly?
completely across the console. This is a full length Is it a single disc or many? Is it Sylvania designed or built by others?
indicating light register which is used to display the Mr. Chao: The mass memory consists of eight large discs, 34Y2 inches
contents of any register or memory location selected in diameter. Both sides of the discs are used. There is a total of 4,096
by the operator. The area below holds the controls tracks. The recording and reading is done in serial track by track.
can consider the entire storage to be a looped spiral. In other
for the flip-flop and error detection. Directly beneath You
words the track sequence is continuous. If you go down to the 4,096th
are the controls for the insertion of manual instruc- track, for the next increment you will get number one track again.
tions. Initiation control for the computer such as Sylvania is collaborating with a contractor in the design of the mass
the contractor supplies the discs and we design the necessary
start, halt, and single pulse, are laid out in the bottom memory;
electronic circuits.
row on the control console.
Reitman (Teleregister): Can the MOBIDIC B system be extended
Inasmuch as the control consoles are assigned to J.
to 3 or 4 processors? If so, is there a limit?
their respective processors, operation of one console
Mr. Chao: The logical problems involved in duplexing are not trivial.
is entirely independent from the other. However, Extending
the number of processors beyond two and tying them all to
since the two consoles are located side by side, the the same system bus would be undoubtedly a little tougher. There
operator can easily observe the status of both proces- must be a limit somewhere. We have not yet investigated this limit.
sors, allowing convenient control of both processors G. Gaschnig (RCA): What is the speed of the core memory?
during duplex operations.
Mr. Chao: 8 microseconds read-write cycle.
CONCLUDING REMARKS
W. Towles (Martin Co.): What is the clock frequency and what type
of logic circuitry is used?
Since there are only two physical working registers
in each central processor, connections from the central
Mr. Chao: Clock frequency is 1 megacycle. The transistor inverter
logic is used.
Chao: System Organization of MOBIDIC B
Mr. Towles: Do the core memories operate reliably at the high temperatures required of a military computer?
Mr. Chao: Yes, it has to. This entire system is designed to meet
military specifications.
Mr. Rubinoff: Well, I think the question is which one?
Mr. Chao: Temperature compensation technique used in the memory
circuit will be discussed in a paper tomorrow.
S. Levine (Teleregister): What error checking facilities are included
and what is the expected undetected error rate of each processor?
Mr. Chao: The automatic error checking facility we have is the
parity bit error indication. This gives you single error detection.
Mr. Rubinoff: Any odd number?
Mr. Chao: Yes.
Mr. Rubinoff: What is the suspected undetected rate?
Mr. Chao: We haven't looked into that.
Mr. Levine: Is interlocking automatic or programmed when both
processors try to get to the same device?
Mr. Chao: They are automatically interlocked so that whichever
comes first will get it.
107
R.E. Warner (Ford Instrument): If processor No.2 determines that
processor No.1 is in error, how are you sure that processor No.2 is
itself not in error while processor No.1 is actually correct?
Mr. Chao: I think we shall have to rely on the statistics. This is a
double-error.
W. Buchholz (IBM): The numerical data word appears to have one
more bit. the sign, than any other word. How is this sign bit transferred to and from magnetic tape? Does the tape control have to
know whether a word is numerical or not?
Mr. Chao: The tape is controlled by the converter. In the case of
numerical data, the sign bit is taken out and composed into a character. Therefore, for interpret sign mode of operation, you have 7
characters instead of 6 for each MOBIDIC word.
E. B. Cohen (Auerbach Electronics): How are the built-in subroutines
constructed? How is return from these built-in subroutines effected?
M'r. Chao: The subroutine is written as program using the mechanized instructions. Whenever a subroutine instruction is encountered,
the accumulator and the program counter are automatically stored
by the logic circuit. They have to be saved because these two registers
are used in the subroutine. Subsequently, the logic circuit will automatically transfer the program into the correct subroutine. Upon
completion of the subroutine, all you have to do is to bring back
these registers and return to the main program.
108
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
A Universal Computer Capable of Executing an
Arbitrary Number of Sub-Programs Simultaneously*
JOHN HOLLANDt
INTRODUCTION
HIS PAPER describes a universal computer
capable of simultaneously executing an arbitrary
number of sub..programs, the number of such
sub-programs varying as a function of time under
program control or as directed by input to the
computer. Three features of the computer are:
T
(1) The structure of the computer is a 2-dimensional modular (or iterative) network so that,
if it were constructed, efficient use could be
made of the high element density and "template" techniques now being considered in
research on microminiature elements.
(2) Sub-programs can be spatially organized and
can act simultaneously, thus facilitating the
simulation or direct control of "highly-parallel"
systems with many points or parts interacting
simultaneously (e.g. magneto-hydrodynamic
problems or pattern recognition).
be considered as occurring In discrete steps, t = 0,
1,2, ....
Basically each module consists of a binary storage
register together with associated circuitry and some
auxiliary registers (see Fig. 1). At each time-step a
module may be either active or inactive. An active
module, in effect, interprets the number in its stora?e
register as an instruction and proceeds to execute It.
There is no restriction (other than the size of the
computer) on the number of active modules at any
given time. Ordinarily if a module M (i,j) at coordinates (i,j) is active at time-step t, then at time-step
t +1,M(i,j) returns to inactive status and its successor,
one of the four neighbors M (i + 1,j), M (i,j +1),
M (i -1 ,j), or M (i,j -1), becomes active. (The exceptions to this rule occur when the instruction in
the storage register of the active module specifies a
different course of action as, for example, when the
instruction is the equivalent of a transfer instruction).
I
I
(3) The computer's structure and behavior can,
with simple generalizations, be formulated in a
way that provides a formal basis for theoretical
study of automata with changing structure
(cf. the relation between Turing machines and
computable numbers).
The computer presented here is one example of a
broad class of universal computers which might be
called universal iterative circuits. This class can be
rigorously characterized and formally studied (the
characterization will be published in another paper).
The present formulation is intended as an abstra~t
prototype which, if current component research IS
successful, could lead to a practical computer.
I
M(I+ I, j)
i
"'---------~.-i-.-
---j-
--,"0
STORAGE REGISTER ~-+_--+
..
I
M (i ,j -I)
I
I
I
AUX. REGISTE RS
I
I
__l__ _
I
----1---
M(i,j+il
M(i-I,j)
i
I" --+
-
~
ACTION LINES
PATH LINES
Fig. I-A module.
GENERAL DESCRIPTION
The computer can be considered to be composed of
modules arranged in a 2-dimensional rectangular
grid; the computer is homogeneous (or iterative) in
the sense that each of the modules can be represented
by the same fixed logical network. The modules are
synchronously timed and time for the computer can
* Funds for this study were supplied to the Logic of Computerb
Group of the University of Michigan initially by the Air Force Office
of Scientific Research under Contract No. AFI8(603)-72 and later
through a National Science Foundation grant (G4790).
t University of Michigan, Ann Arbor, Michigan.
The successor is specified by bits 81, 82 in M(i,j)'s
storage register. If we ·define the line of successors of
a given module as the module itself, its successor, the
successor of the successor, etc., then a given subprogram in the computer will usually consist of the
line of successors of some module. Since several
modules can be active at the same time the computer
can in fact execute several sub-programs at once.
We have noted parenthetically that there are orders
which control the course of action - there are also
orders equivalent to store orders which can alter the
number (and hence the instruction) in a storage
109
Holland: Universal Simultaneous Sub-Program Computer
register. Therefore the number of sub-programs being
executed can be varied with time, and the variation
can be controlled by one or more sub-programs.
The action of a module during each time-step can
be divided into three successive phases:
(1) During phase one, the input phase, a module's
storage register can be set to any number supplied by
a source external to the computer.
(2) During phase two, an active module determines the location of the operand, the storage register
upon which its instruction is to operate. This the
module does by, in effect, opening a path (a sequence
of gates) to the operand. Phase two is called the pathbuilding phase.
(3) During phase three, the execution phase, the
active module interprets and executes the operation
coded in its storage register.
P
PATH-BUILDING
I
I
An active module determines the location of the
storage register upon which its instruction is to operate by, in effect, opening a path to it. The pathbuilding action depends upon two properties of
modules:
First, by setting bit p in its storage register equal
to 1, a module may be given special status which
marks it as a point of origination for paths; the
module is then called a P-module.
Secondly, each module has a neighbor, distinct
from its successor, designated as its predecessor by
bitsql, q2 in its storage register; the line of predecessors
of a given module M 0 is then defined as the sequence
of all modules [M o,M 1, ••• , M k, • • • ] such tliat, for
each k, Mk is the predecessor of M k- 1 and M k - 1 is the
successor of Mk (see Fig. 2). Note that the line of
predecessors may in extreme cases by infinitely long
or non-existent. The line of predecessors of an active
module ordinarily serves to link it with a P-module
(through a series of open gates). During the initial
part of phase two the path specification bits Yo, .•• , Yn
and d1 , d2 , in the storage register of an active module
M 0, are gated down its line of predecessors to the
nearest P-module (if any) along that line. The path
specification bits are then used by the P-module to
open a path to the operand (the storage register
addressed by the active module).
Each path must originate at a P-module and only
one path can originate at any given P-module. The
path originating at a P-module is gated by means of
a sequence of auxiliary registers called *-registers.
Each module possesses 4 *-registers and if the module
belongs to a path in direction (b 1 , b2 ) the appropriate
*-register, (b 1,b 2 )*, is turned on. When (bl,b 2 )* is on
it gates lines (to be described) from the module
M(i,j) to its neighbor M(i +bl,j +b 2 ) permitting certain signals coming into M(i,j) to be passed on to
M(i+b 1 , j +b 2 ) and vice-versa. Since each *-register
~
SUCCESSOR
PREDECESSOR
----
cr·O
~
..
ACTIVELY CONNECTED
0
LINE OF PREDECESSORS
Fig. 2-Lines of predecessors.
x
~- ---E3----'0
T
o
D
D
D
D
X
P
ACTIVE MODULE ("INSTRUCTION")
MODULE IN P-STATUS
T
PATH TERMINATION ("OPERAND")
A
MODULE IN A-STATUS ("ACCUMULATOR")
0
B--B
4(J
LINE OF PREDECESSORS
PATH
Fig. 3-Modules used in the execution of an instruction.
gates a separate set of lines, a module may (with
certain exceptions) belong to as many as four paths.
Once a *-register is turned on its stays on until
turned off; thus a path, once marked, persists until
erased.
The modules belonging to a given path can be
separated into sub-sequences called segments. Each
segment of the path is the result of the complete
phase two action of a single active module. A segment consists of y modules extending parallel to one
of the axes from some position (i,j) through positions
(i+b 1 ,j+b2 ), (i+2b 1 ,j+2b 2 ), • • • , (i;+(y-1)b 1,
j+(y-1)b 2 ), where b1 = ±1 or 0 and b2 = ±(l-\ol\);
the module at (i+yb 1, j+yb 2 ) will be called the
termination of the segment (note that the termination of the segment is not a member of the segment.)
The segments are ordered so that the first segment
constructed has as its initial module the P-module.
The kth segment constructed as part of the path has
as its initial module the termination of the k -1 th
segment. If the path consists of n segments, the termination of the nth segment (the last segment constructed) will be called the path termination (see
Fig. 3).
As noted, the path specification bits Yn, ... , Yo
and d 1 ,d2 are gated down the line of predecessors
from the storage register of the active module to
110
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
the nearest P-module at the start of phase two. If
Yn =0, bits Yn-l, ... , Yo and d 1 ,d 2 determine the
length and direction, respectively, of the new segment. The total number of digits Yn-l, ... , Yo equal
to 1 gives the length of the segment - if j of the
digits are equal to 1 then the segment will be j
modules long. The digits d1,d2 turn on and set an
auxiliary register, the direction ~egister, in the initial
module of the new segment. This gives the direction
b1,b 2 of the segment. The direction registers of- the
other modules belonging to the segment are all off,
bu t each of the modules belonging to the segment
(including the initial one) has its (b 1,b 2 )* register
turned on.
When Y n = 1, the final segment of the path originating at the P-module is erased. That is, the direction
register in the initial module of the last segment is
turned off and, as a consequence, all *-registers marking the last segment are turned off. If the path
consists of a single segment or none at all the effect
of Y n = 1 is to turn off the direction register in the
P-module thereby making the P-module the termination of the path. That is, in this latter case, the
path has no segments but it does have a termination
- the P module itself (note that the status of the
P-module is unchanged).
The following additional rules apply to paths:
(1) When a given module is the termination of
several paths and direction register on-pulses arrive
over more than one path at the same time, t, the
result is no action - the direction register is not
turned on and none of the paths is extended.
(2) Only one path can proceed through-a module
in which the direction register is on. Whenever the
direction register of a given'- module M is turned on
or given a new setting, any paths already running
through that module will now have it as their termination. Furthermore, for each such path, the
portion lying between M and the previous path
termination is at once erased - the *-registers and
direction registers marking that portion of the path
are turned off.
(3) No P-module can belong to any part of a path
other than its origin. If a path in the process of construction reaches a P-module then all constructipn
ceases and the P-module becomes the termination
of the path regardless of the value of digits Yn,Yn-l,
... ,Yo. Further extension of the path will not be
carried out unless the P-module's status is changed
(its p bit set to zero).
EXECUTION
Three modules play an important role during the
execution phase of an active module: the active
module itself holds the order code in bits i 1 ,i 2 ,i a of its
storage register; the storage register of the nearest
path termination contains the word to be operated
on (the operand); finally there must be a module
which serves as accumulator (see Fig. 3). In order to
serve as an accumulator, the storage register of a
module must first have bits (p,a) in it set to the value
(0,1), giving the module special status - A-module
status. (Note that this means a module in P-module
status, p = 1, cannot be an A-module). If M(i,j) is
an active module then the first A-module along its
line of predecessors serves as the accumulator. An
A-module serves, in effect, to terminate a line of
predecessors, since it can have no designated predecessor.
In the present formulation there are eight basic
orders:
(1) The arithmetic operation ADD. Execution of
ADD causes the number in the storage register at
the nearest path termination (the operand) to be
transferred to the nearest A-module and there added
to whatever number is in the storage register of the
A-module. (By using complements and iteration all
the arithmetic operations, such as subtraction and
multiplication, can be accomplished by means of this
operation) .
(2) The storage operation STORE. Execution of
STORE causes the number in the storage register of
the nearest A-module to be transferred to the storage
register at the operand.
(3) The transfer operation TRANSFER ON MINUS.
Execution of TRANSFER ON MINUS depends upon the
number in the storage register in the nearest Amodule. If Yn = 0 in this number then the active
module, after completing phase two, becomes inactive
and its successor becomes active. If Yn = 1 then the
module at the nearest path termination, rather than
the successor, becomes active.
(4) The index operation ITERATE SEGMENT. If
Yn = 0 in the nearest A-module, execution of ITERATE SEGMENT (upon completion of phase two) reduces the number in the A-module by 1 and the
active module remains active without causing its
successor to become active. If Yn = 1, then execution
of the order simply causes the successor to become
active and the active module inactive at the completion of phase one. This operation provides a convenient means of building long paths in a given
direction since, if N is the number in the nearest
A-module, the path-building phase of the active
module is iterated N times.
(5) SET REGISTERS causes the first 9 bits of the
number in the nearest A-module to be used to set
all 9 auxiliary registers at the nearest path termination, the jth register being set on if the jth bit is
a one. It is important that the SET REGISTERS order
can give the operand module active status by setting the appropriate auxiliary register. In this case
the active module gives rise to two active modules
on the next time-step, its successor and the operand
module. By this means one sub-program can initiate
activity in another.
Holland: Universal Simultaneous Sub-Program Computer
(6) RECORD REGISTERS causes the l::ltate of the
9 auxiliary registers at the nearest path termination to be recorded in the first 9 bits of the nearest
A-module (in the same order as used by the SET
REGISTERS instruction).
(7) No ORDER causes the execution phase to pass
without the execution of an order.
(8) STOP causes the active module to become inactive without passing on the activity to its successor
at the next time-step.
With the exception of the STOP, ITERATE SEGMENT,
and TRANSFER orders, the active module become s
inactive and its successor becomes active at the
conclusion of the execution of an order.
It is possible for a given active module to have no
nearest P-module (or A-module) for anyone of three
reasons: (1) the module does not have a line of
predecessors, (2) none of the modules along the line
of predecessors is currently designated a P-module
(or A-module), (3) there is no P-module along the
line of predecessors between the active module and
the nearest A-module. If there is no nearest Pmodule then there is neither path-building nor execution of instruction with respect to the active module
(regardless of the content of its storage register). If
there is no nearest A-module along the line of predecessors then the instruction of the active module is
not executed although the path-building phase will
be carried out (assuming a nearest P-module).
The following additional rules apply to active
modules and their action with respect to P-modules
and A-modules:
(1) If Mo belongs to the line of predecessors of M 1 ,
if the nearest P-module of M 0 is also the nearest
P-module of M 1, and if M 0 and M 1 are both active,
then the action of Mo proceeds normally but M 1 's
action is as if it had no nearest P-module.
(2) If Mo and Ml are situated as in rule (1) except
that they have the same nearest A-module, without
sharing the same P-module, then the action of Mo
proceeds normally but M 1 acts as if it were executing
a NO ORDER instruction.
(3) As mentioned earlier, a module can be given Amodule status by setting the pair of bits (p,a) to the
value (0,1). This turns on an auxiliary register in the
module, the A-register. At the same time the bits of
another auxiliary register pair, the (D 1,D 2-register,
are set to match the bits SI,S2 in the module's storage
register; i.e., when the A-register is on the (D 1 ,D 2 )register indicates the successor of the A-module.
Once a module is given A-module status it can be
returned to normal status only in one of two restricted
ways. The first way requires that a STORE order be
executed by an active module which has the given
A-module as its operand module (nearest path termination). Then, if bit ais 0 or bit p is 1 in the number
being stored, the A-module reverts to normal status
and the word in its storage register is that specified
111
by the STORE instruction. Otherwise the A-module
is unchanged, the STORE order not being executed.
The other way of returning an A-module to normal
status requires that the A-module receive external
input during phase one. The above restrictions prevent the A-module from changing status when numbers are placed in its storage register during the
normal course of its operation as an accumulator.
During the time a module is an A-module the bits in
its storage register are not interpreted in any way
except as the digits of a binary number.
(4) A module in A-module status can become
part of a path (or several paths) so long as it is
not to be the initial module of a path segment. In
this latter case the path-building action, which would
make the A-module the initial module of a segment,
is not carried out - the A-module remaining the
termination of the path.
(5) A given module can be acted upon simultaneously by 2, 3, or even 4 STORE instructions if it is
the termination of more than one path. Some provision must then be made to resolve conflicts when
the numbers being stored are not identical. In the
present formulation the conflict is resolved digit by
digit: a 1 is stored at bit j in the storage register if
and only if at least one of the incoming numbers has
a 1 at position j.
(6) When a STORE instruction changes the word
in the storage register of a module it is assumed that
this change does not take place until the completion
of phase three. Thus, for example, there is no conflict
when the STORE instruction of an active module
acts upon that module's own line of predecessors or,
for that matter, upon the module itself.
(7) If an active module has an A- or P-module as
successor then, at the next time-step, the successor of
the A- or P-module becomes active, rather than the
A- or P-module itself (unless, of course, the instruction
just executed specifies otherwise).
INPUT
During phase one, the initial phase of each timestep, a module's storage register can be set to any
arbitrarily chosen value and its auxiliary registers
to any desired condition. The numbers and conditions thus supplied are the computer's input.Although
the number in the storage register can be arbitrarily
changed at the beginning of each time-step, it need
not be; for many purposes the majority of modules
will receive input only during the first few moments
of time ("storing the program") or only at selected
times it,t 2 , • • • ("data input"). Of course, some
modules may have a new number for input at each
time-step; in this case the modules playa role similar
to the inputs to a sequential circuit.
SUMMARY OF ORGANIZATION AND SYMBOLS
As noted in the general description of section 2,
112
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
each module consists of a storage register plus some and the other n + 11 bits being arranged as indicated
auxiliary registers. The earlier discussions indicate with Yn-l being the high order bit and a being the low
order bit.
that the auxiliary registers required are:
COMMENT
(1) the E-register, a one-bit register which is on if
A universal machine in which the programs have a
spatial organization has several properties over and
above those usually associated with Turing machines
and their concrete counterparts. For example, cycles
in the program can actually be stored as cycles (of
successors) in the rectangular grid (see Fig. 5). This,
in effect, provides each cyclic sub-program with an
instruction address counter which counts modulo the
number of instructions in the sub-program (cf. an
index register which can be set to cycle modulo any
base number). Furthermore,· each sub-program can
be allotted a certain area in the grid and this allows
the spatial arrangement of the sub-programs to
match, for example, the structural organization of a
process which is being simulated - each subprogram
For formal purposes we can symbolize the state of a in this case directly simulating one of the components
given register, X, at coordinates (i,j) and time t by of the process.
the predicate X(i,j,t) = 1 if the given register is on at
Efficient programming of certain types of problem
time t.
will require techniques similar to those required for
asynchronous operation. That is, when several subprograms are operating simultaneously, each subprogram will from time to time require results from
other sub-programs, however these results will not in
general be available at just the time desired. In
problems like this, usually arising in the control or
simulation of "highly-parallel" systems with many
points or parts interacting simultaneously, the
programmer will employ many of the techniques of
the logical designer.
and only if the given module is active;
(2) the A-register, a one-bit register which is on if
and only if the given module is an A-module;
(3) the D-register, a one-bit register which is on if
and only if the given module is the initial module of
a path segment;
(4) the (DJ,D2)-register, a; register, with two bits
of storage, which indicates the direction (b 1 ,b 2 ) of a
segment if and only if the D-register is on and which
indicates the direction of the module's successor if
and only if the A-register is on.
(5) the (b ,b 2)*-registers; each is a one-bit register
which is on if and only if the given module is a
member of a path segment with direction (b 1,b 2 ).
--B---B---ED 0
Fig. 4-Control of module by storage register.
The storage register of each module in the present
formulation consists of n + 12 bits (see Fig. 4) labelled
in the following order:
bit number:
n +12 n +11 . . . 12 11 10 9 8 7 6 5 4 3 2 1
label:
The bits 81,82 and ql,q2 designate the successor and
predecessor, respectively, of the module. If bit p is 1
the module has P-module status. If the pair of bits
(p,a) are set to the value (0,1) as the result of input
or a STORE operation, the module has A-module
status. During the path-building phase bits Yn, ... ,
Yo and dI,d 2 in an active module are interpreted as
segment length and direction respectively. During
the execution phase bits i 1,i2,i 3 in an active module
are interpreted as the operation to be performed. The
word in the storage register of an A-module is treated
strictly as a binary number with Yn being the sign bit
0
D
I
o
I
[9--B--BP
MODULE IN P-STATUS
A
MODULE IN A - STATUS
-0 0
-G--G
LINE OF PREDECESSORS
PATH
Fig. 5---Two interacting subroutines.
Problems such as the one just discussed emphasize
the desirability of a computer formulation amenable
to theoretical investigation. The present formulation
is one example of a broad class of computers which
can be rigorously characterized and investigated by
abstract deductive techniques. Actually, the defini-
Holland: Universal Simultaneous Sub-Program Computer
tion of this class of computers comes as part of an
effort to provide a formal basis for the study of
growing automata. By considering the rectangular
grid to be infinite (or potentially infinite) in each of
its dimensions (in analogy to the infinite tape of a
Turing machine) many problems of automata theory
can be expressed in a formal framework similar to
that provided by Turing machines for problems of
computability. Thus, for example, models of various
processes can be stated as programs, or classes of
programs, for the machine and investigated both
directly and theoretically.
There are several variants of the formulation given
here which yield computers which are either more
flexible or have simpler modules. As a single instance,
the path-building procedure could be altered to make
branching paths possible; in this way the same subprogram could operate on several storage registers
simultaneously.
A final word about concrete realization of such a
computer: a partial rendering of the logical diagrams
for a module in the described computer indicates that
a module with a 40-bit storage register could be constructed with approximately 1000 basic elements. If
this is actually the case and if switching is accomplished with micromodular densities, say 108 elements
per cubic foot, then the basic portion of a computer
with 100,000 modules should be realizable within a
volume of a few cubic feet (exclusive of input-output
equipment, power supply, etc.).
DISCUSSION
M. Rubinoff: Would you expect this two-dimensional mondular
structure to have important significance for character recognition
and other aspects of "gestalt" or area vision?
Dr. Holland: I would hope so. This was part of the original intent in
constructing the computer. The hope was that it could operate on all
parts of the pattern at the same time. The computer is really a byproduct of research on what we call growing automata.
P. Rosenblatt (Teleregister): Since any module may be in P status
at some time, will not this "anywhere-to-anywhere" transmission
result in extremely large cost of gating when the number of modules
is large?
Dr. Holland: I think the point here is that any module may be in P
status; however, gating is from module to module, and you open these
gates in serial fashion as specified by the number in the storage
register of the active module. Since each module will have a fixed
number of gates controlling the path lines to its four neighbors, the
number of such gates is directly proportional to the number of
modules. Note that only one path can proceed from anyone P
module at any given time.
R. A. Kirsch (Nat'l Bureau of Standards): Why did you constrain the
machine to the two-dimensional rather than the multi-dimensional?
Dr. Holland: This was for purposes of exposition. As I say, this is one
example of a large class of machines and you can have any number of
dimensions in general. If you get beyond three dimensions you are
operating entirely in theory.
G. Richmond (Cornell Aero Lab.): Can paths be destroyed as well as
created?
Dr. Holland: Yes. I didn't mention this in the talk but if you set the
first bit in the storage register (labeled Yn) to one, in effect this says
113
that, when the path-building phase of that module is carried out, the
last segment of the path is to be erased. In other words, you pay no
attention to the rest of the bits Yn-i through yo; you simply erase
the last segment of the path.
L. R. Bowyer (Bell Labs.): Is only one module active at a time? How
does a path get formed through non-active modules'?
Dr. Holland: No, any number of modules may be active at the same
time. In fact, by means of interlocking conditions you can allow
modules along the same line of successors to be active. You recall
there was a square red line of successors in the last slide; it is even
possible for more than one module to be active in that red square.
The number of interlocking and override conditions is surprisingly
small. There are only 12 of them. The activity of a module has no
direct effect upon paths passing through it. If a module is active it
makes no difference as far as these paths are concerned. The path
lines are separate sets of lines that pass through modules. The opening of gates in the path lines are caused by active modules (via a
P-module) but the path doesn't have to pass through an active
module.
G. J. Moss (Naval Ordnance Lab.): Could you elaborate on the process
of reading data into the computer?
Dr. Holland: This is a part I haven't paid a great deal of attention to.
I would say this, that in general one would like to have some device
that could put data into any storage register of this modular arrangement at any time. This seems a little difficult from a practical viewpoint so it seems you would have to settle for some sort of scanning
technique to put data in at partiCUlar times. In order to make effective use of this computer in some communication system or pattern
recognition device you would certainly put data in at many modules
at many times; perhaps at each time-step during the input phase.
All data, has to go in during the input phase.
W. Buchholz (IBM): What happens if one module tries to create a
path that would have to cross an already existing path?
Dr. Holland: As long as it does this at a place which is different from
the termination of a segment this is all right. As I mentioned during
the talk, each segment of the path proceeds in a given direction
(parallel to one of the axes). Modules can have as many as four paths
running through them one to each of the four neighbors. These lines
are independent except at points where the paths turn. In other words,
at the termination of a segment where you add on a new piece you
may have a right angle turn. At this point you need a crossover
matrix from one path line to another. At this point an interlock
would prevent a second path going through. If you tried to build a
second path at this point nothing would happen.
T. Gilmer (ITT Federal): What is the function of the auxiliary storage? How do you deactivate a net once started?
Dr. Holland: I didn't go through this but I can give you an example.
I mentioned that if you have the a bit in the storage register equal
to one then the module is in A-module status. This means that during an ADD operation you might change the content of the storage
register in the A-module and change the a bit to a O. Then the module
would lo!'!e its A-module status. This you don't want. So one of the
auxiliary registers keeps the module in an A module status so that
changes in the contents of its storage register make no difference.
Other auxiliary registers perform functions that are similar.
L. Clapp (Sylvania): Would Mr. Holland care to comment on debugging, diagnostic and preventive maintenance techniques of this
computer?
Dr. Holland: The programming here would involve two kinds of
techniques. It would take quite a bit of the best of programming
techniques together with techniques of logical design. You may have
circumstances very similar to asynchronous operation, if the second
program has to wait for the first program to produce the data. A
programmer of this machine has to be a good programmer but also
has to be a good designer, too. In some cases, e.g. the solution of
two-dimensional differential equations, since you repeat the same
program over and over across the module, the debugging might be
simpler than in a single-sequence computer because you have no
lo~ical effort to put into a scanning program - the program structure would match the mesh structure.
114
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
The Multi-Sequence Computer as a
Communications Tool
J. N. ACKLEyt
HIS is a report on the merging of two fields: communication switching and computers. Recent advances in the computer art make it possible to
satisfy the ever increasing communication switching
requirements brought on, in part, by computers
themselves employed in centralized data processing
systems. Present record communication systems have
significant delays which are not primarily caused by
the transmission times but by the time required for
the operations in the communication message switching centers.
In the past, most communication has been from
human to human. Communication systems have become more complex and automated to meet the ever
increasing needs of commercial and military activities. We are faced with a revolution. Increasingly,
communication will be between humans and machines
and between machines and machines. This transition
will place more stringent requirements on accuracy,
reliability, and speed.
Present day electromechanical switching centers
are limited in their speed of operation due to their
electromechanical nature and due to limitations of
the transmission means, namely, teletype. Little error
detection and correction capability is presently found
in these systems.
Centralized data processing requires the error free
transmission of large volumes of data to a central
point. Usually, the communication with machines or
between machines involves little redundancy such as
that found in plain English. The computer, although
it can make validity checks on the data it receives,
cannot fill in missing letters or words as a human can.
Since the present electromechanical systems are
special purpose devices, all messages routed through
the system must adhere to a very rigid format. This
leads to difficulty when trying to integrate data
gathering devices and different types of computers
with different codes and formats. Military command
control systems, especially, require data inputs from
varied sources.
Stored program techniques could solve many of
these communications problems. A programmed
switching center could provide the error checking and
error correction procedures as required. It could be
programmed to translate from one code to another,
indeed, perhaps from one language to another. Vari0us speeds and code structures could easily be
accommodated.
T
t International Electric
Corporation, Paramus, New Jersey.
In addition to improving the features presently
found in some switching cente~s, stored program
techniques could be used to implement features which
are not practicable with electromechanical or special
purpose switching systems. A programmed switching
center could generate, receive and interpret service
messages to and from other machines or human operators. It could test and monitor all of the communication links and reroute messages if necessary to avoid
inoperative links. One of the biggest advantages of a
programmed switching center is its ability to be reprogrammed to account for changes in operational
procedures, routes and equipment.
One of the most important considerations in employing computer techniques to the communications
switching problem is the large number of input and
output channels required. Also, all channels must
operate simultaneously and independently. Military
practice requires that each message be forwarded as
far as possible whenever the communication link is
available. Thus, the communication switching center
must accept a message on each communication line
whenever the subscriber wishes to transmit.
For many years the bottleneck on efficient use of
computers and on the application of computers to
real-time systems has been the problem of integrating
input-output devices. Most input-output schemes
have involved a large amount of equipment external
to the central computer to provide for buffering and
control. Now that the versatility of the high speed
random access core memory has been fully appreciated, an almost limitless number of schemes is possible. Indeed, a single computer may use several
schemes to integrate various input-output devices.
INPUT
EXTERNAL
INTEGRATED
MEMORY
BUFFER
CONTROL
Fig. l-Input-Qutput classification.
In order to discuss the various schemes and compare their advantages and disadvantages, it is necessary to establish a classification system. There are
115
Ackley: Multi-Sequence 'Computer in Communications
four parameters, as shown in Fig. 1, which charac- the input-output transfers. However, in a system
terize an input-output scheme:
application which requires a large volume of inputoutput, a large percentage of the capacity of the maAssembly refers to the process of packaging or unchine would be tied up in the input-output transfers.
packaging information into definite size units. In
A typical communications switching center may
order to characterize the assembly (or the dishave 50 to 100 two-way communication lines. In
assembly) process, one must specify how and where
order to have a computer perform the functions of a
the transformation takes place among bits, characstore and forward switching center, it must have corters, words, records, and files.
responding numbers of input and output channels.
Buffer refers to the unit external to the central com- In addition, it must have a sufficient processing capacputer which holds information until it can be ity to determine distribution and optimum routing,
transferred. The buffer may also be involved in the priority, and to perform validity and parity checks if
assembly process. It is characterized by its capac- required. Not only must it provide for these large
ity, access time, and assembly features.
numbers of input and output channels, but all chanTransfer refers to the process of exchanging infor- nels must be capable of operating simultaneously.
mation with the integrated (addressable) memory Neither of the extreme systems described above is
of the central computer. The transfer is character- satisfactory for this type of operation. However, both
ized by the number of bits transferred in parallel. of these schemes can be made practical for this type
of application by multiplexing as shown in Table I.
Control refers to the process which determines the
TABLE I
sequence of operations of an input-output channel.
IN-OUT SYSTEMS FOR COMMUNICATION SWITCHING
In order to carry out the control function, control
words must be supplied to a control device. Typical
Assembly
Buffer
Transfer
Control
words that are usually involved in input-output
are:
1. Bits to
Character
Character
ExternalSelection code
Number of units of information to be transferred
Address in integrated memory at which the
transfer is to begin
Address in external device at which the transfer
is to begin
Location of next control word
Some or all of the control words are required for
any input-output transfer. The device which uses
these control words can be the central computer or a
separate input-output control device which provides
for the proper sequence of operations.
In designing a system, engineering compromises
must be made. Many combinations and permutations
of the above factors can be made. Each permutation
will have certain advantages and disadvantages
which must be weighed against the systeln application. For example, to take the extremes, a system can
be designed like the IBM 709 system which has an
external control device (the Data Synchronizer).
This device has a register for buffering and additional
registers for storing the control words. This system
requires only a core memory cycle for a transfer and
thus takes little time away from the central computer
during input-output transfers. However, this scheme
requires extensive hardware for the external control
device.
On the other hand, a system may be designed to
store all of the control words in integrated memory
and the central computer could supply the control.
Such a system would require a minimum of equipment external to the central computer for control of
character
external
2. Bits to
character
external
Character
break-in
multiplexed
interrupt or
mul tisequence
for special
cases.
Character
programmed
Central
computermultisequence
For example, the external control device can be multiplexed so that it may service a number of input and
output channels simultaneously. This also requires
that the central computer have a number of independent memory banks so that the transfer of the
control words from storage to the external control
device and back to integrated memory on each input
or output transfer will not saturate the system.
By multiplexing the central computer, it can be
used to handle a large number of communication
lines. A central computer can be made to time share
over a large number of channels by utilizing the multisequence configuration. 1 This configuration provides
a number of program counters and a system for
switching from one program counter to another, in
response to external stimuli.
In order to select the proper scheme, a detailed
study must be made of the particular communication
switching center requirements. The external control
scheme gives a higher capacity under certain conditions, but it requires more equipment. The study of
1 W. A. Clark, "The Lincoln TX-2 Computer Development";
J. W. Forgie, "The Lincoln TX-2 Input-Output System"; Proceed-
ings of the W,J. C. C., 1957.
116
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
the communication requirements must determine the
ratio of the number of core memory cycles required
for internal processing to the number of core memory
cycles required for input and output transfers. If this
ratio is sufficiently high, then the central computer
control scheme is to be preferred, since relieving the
central computer of the burden of input-output transfers would free only a relatively small percentage of
the system capacity. On the other hand, if this ratio
is low, then the external control scheme is to be preferred since a low ratio implies that the main function is that of input-out transfers.
In a system which requires utmost accuracy
achieved by the use of redundancy checks, and which
must automatically route and reroute messages to
account for communications outages and supply
other functions such as code translation; this ratio
may be in the order of 2 or 3 to 1. Thus, only a 33 to
50 percent increase of capacity is the maximum that
could be expected by utilizing an external control device and multiple access integrated memory - neglecting memory reference conflicts.
Another significant factor which affects total capacity of the system is the assembly process and the
capacity of the external buffer. Since most communication is based upon characters of five, six, seven or
eight bits, it is desirable to handle the assembly from
bit to character externally.
Systems have been proposed utilizing only a single
bit external buffer, with the assembly from bit to
character to word to message in integrated memory.
However, the capacity is severely reduced since now
a transfer must take place on each and every bit of
a message. Increasing the size of the external buffer
on the other hand increases the capacity, but at the
same time increases the amount of equipment. The
maximum buffer size to be considered is that of the
word length. Therefore a compromise must be reached
between the amount of equipment in the external
buffers and the capacity of the system. This compromise is influenced by the number of lines to be
terminated, by the speed of the circuitry available
to the programmed element, and by the nature of the
transmission system.
Those who have been through a computer development program will immediately ask, "Is it necessary
to design a special computer for the communication
switching system?" or, more generally phrased, "Can
a general purpose computer be utilized?" This question is not easily answered. The answer must be based
on a thorough study of the communication system
application. Surely, if the only job of the programmed
element is that of communication switching, then
there is no need for floating point or even multiply
or divide instructions in the instruction vocabulary.
Thus, simplifications can be made in the design of a
programmed element which is to be used solely for
communication. The specialized programmed ele-
ment can be optimized for communications.
On the other hand, if the computer is to be used for
both communications and computations, it may be
desirable to design an external control device which
can be adapted to a general purpose computer. However, the range of applicability of the general purpose
computer seems rather limited. If the computational
requirements are very great, it may be profitable to
employ the special purpose programmed element for
the communications switching center and also to act
as an input-output processor for a much larger data
processor. This philosophy is illustrated in the
STRETCH and LARC computers where a simple
input-output processor is used to relieve the complicated, high speed data processor of the simple routine
tasks associated with input and output editing. The
in-out processor can also be used to operate or schedule the operation of the larger data processing system
to achieve a much higher utilization of the data processor than would be possible with a human operator.
In selecting a computer or designing a computer
for communication system switching center application, consideration must be given to the peak and
average traffic rates. Generally, the utilization factor
of communication lines is approximately 0.1 to 0.2.
This surprisingly low figure is justified because of the
queueing problems which would ensue with a very
high utilization of any communication link. Assuming
a Poisson distribution of message arrivals, a utIlization factor approaching unity would result in a queue
approaching infinity. Therefore, to minimize the
queueing problems and to assure rapid transmission
of the message, the utilization factor is desirably
kept approximately at 0.2. The message processing
capacity of the switching center must also be designed
to exceed the average traffic load in order to eliminate
excessive queues of messages awaiting processing.
The use of a multisequence computer for a communication message switching center permits the
termination of a number of lines which would saturate the computer with input transfers if all lines
were operating at full capacity all of the time. The
internal and output processes can be assigned a lower
priority in the multi-sequence scheme and these operations suspended until the input peak passes. The
probability of such an occurence is extremely small.
Since it also is extremely rare that many of the communication lines would be simultaneously busy with
input traffic, additiollallines may be terminated with
the probability that the switching center would lose
an input character. In a completely automated system, this would be caught by the error detection and
correction system and cause only a slight delay in
transmission. The amount of excess message processing capacity required to reduce the processing queue
to satisfactory proportions depends upon the delays
permitted and upon the priority structure of the
messages.
Ackley : Multi-Sequence Computer in Communications
117
A programmed Traffic Control Center is currently signal is routed to the coder.
being fabricated at ITT Laboratories. This Traffic
Fig. 4 shows a typical input channel. When the
Control Center, which utilizes the multisequence strobe signal arrives at the coder it is converted into
technique, was undertaken as a study project in 1957 binary code. If the instruction that the .central comat the Laboratories and was then proposed by this puter is executing contains a break bit, the output
author as the solution to the communication message of the coder will be compared with the number in the
switching problem of the SAC Control System, sequence register. If they are not equal, a sequence
Project 465L, in July 1958. The system design re- of higher priority number has requested service.
sulted in a computer with several distinguishing de- Notice that the number in the sequence register opersign characteristics which make it peculiarly efficient ates a switch which selects the particular external
in handling communications. The central computer device to be used at any given time and routes control
is multiplexed by use of the multisequence technique. signals to the external device. The dismiss signal is
Separate memory units are provided to store 256 pro- issued whenever the present sequence has completed
gram counters and 256 index registers. One index all operations necessary to answer the service request.
register is associated with each sequence; thus, in This signal clears the service request flip-flop and
essence, 256 separate sequences may time-share the prepares it for receiving the next request for service
central computer. Each communication line is termi- from the external device.
nated by a simple character buffer and each buffer
has associated with it a service request flip-flop. As
data becomes available, the service request flip-flop
is set and competes for time on the central processing
NOT
EQUAL
unit. Each instruction has provision for a break-bit
or a dismiss-bit, as shown in Fig. 2, which when set
indicates that the present sequence may be interrupted in favor of a higher priority sequence or that
the present sequence may be dismissed, in which case
the service request flip-flop is cleared and the remainDISMISS
ing sequence with the highest priority is activated.
o
1 2
3
4
5 6
7
8
9
-TTop
10 11
12 13 14 15 16 17 18 19 2C 21 22 23 24 25 26 27 28 29 30 31
cODE
~,.-'--'-_-'----'---'-_~~_'_L_
IITI-[[IIII'IT-rrr-r~-~
.l_L.l .l.L
_
_._
.
__
.
L,
Fig. 4-Typical input channel.
Fig. 5 shows the registers involved in changing
sequences. If the number from the coder is found not
equal to the number in the sequence register and the
current instruction has a break or dismiss bit, a
change of sequence is called for. Since the control
must return eventually to the old sequence whenever
that particular channel requests service again, the
program counter must be stored for future reference.
Fig. 2-Instruction word.
TO CODER
PROGRAM
COUNTER
DISMISS 1+1
SERVICE
REQUEST 1_ 1
SERVICE
REQUEST1
MEMORY
I
SERVICE
REQUESTI~
I
Fig. 3-Service request scanner.
To take advantage of statistical averaging of the
inputs and outputs, an on-demand scanner (shown in
Fig. 3) does' not operate on a fixed cycle, but service
is requested immediately if no other channels are busy
at the same time. In order to incorporate devices of
different speeds, and to provide an orderly procedure
for servicing requests if more than one should arrive
at a time, the service request scanner operates on a
priority basis. A strobe signal proceeds from one
service request flip-flop to the next until the first one
which is set is encounter~d, at which point the strobe
Fig. 5-Registers involved in changing sequences.
Therefore, the first operation is a transfer of the
sequence number from the sequence register to the
program counter memory address register. The program counter is then stored at the location so speci-
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
118
fied. After the old program counter has been stored,
the new sequence number is read from the coder into
the sequence register and then to the program counter
memory address register. The stored program counter
stored at this location is now placed in the program
counter and the computer continues to take instructions specified by the program counter.
In order that each sequence may have its own index register, the contents of the sequence register are
transferred into the index memory address register
and the contents of the location so specified are used
for the indexing operation. Since the program counter
memory and the index memory are independent units
and can operate concurrently with the main integrated memory of the computer, changes of sequence
can take place without any loss of time, that is, an
instruction with a break or dismiss in one sequence
may be immediately followed by an instruction in
some other sequence.
Note that if the contents of the accumulator were
stored along with the contents of the program counter, we would truly have a multiplexed computer.
However, this feature was not necessary for the
communication switching center, but care must be
taken during programming in placing break and dismiss bits only at those points in a sequence where the
contents of the arithmetic unit are immaterial.
o
I
2
3
456
76
'
9 10 111213141516171819202122232425262726293031
Isloillclllllllllllllllllllllllllill
l
WOYRD
LOCATION
"-y-'J
' - - - - - - - - - R E P E A T MODE SELECTION
(REPEAT MODE I NCREMENTS INDEX
REGISTER AND INHIBITS ADVANCING
INDEX SELECTION
OF PROGRAM COUNTER UNTIL INDEX
(CAUSES ADDRESS
REGISTER REACHES ZERO)
MODIFICATION)
Fig. 7-Instruction word.
a check on parity and a check for a control character
are performed by common circuitry. If either condition prevails, it is indicated to the program by means
of a skip. Otherwise the input-output transfers are
handled by a single instruction in the repeat mode
with the dismiss-bit set. This causes the character
to be transferred, the index register to be incremented, and the present sequence dismissed in favor
of some other sequence. The message processing
sequence has the lowest priority and processes messages between transfers.
Ii
>=
V" at least for one K (K = 2 and 5).
(ii)
If any pair of vectors or covectors is in relationships
i and ii, the vector U is called "larger than" V, or
V is called "smaller than" U and is expressed as
U > V
or
U > V.
(iii)
The relation is called a "vector order relation" (covering, or inclusion). W has no order relation to U and
V. In general, a vector set forms a "partially ordered"
(semi-ordered) set.
If all possible K relay-loop vectors C/ are determined by odd number sums of C linearly independent relay-loop vectors C q", all W relay-loop
vectors generally form a semi-ordered vector set.
Because W vectors include all possible relay-loop
vectors, if there exists a multiple loop UK in these
vectors, its single loop part V" exists in the remaining
vectors, and this multiple loop vector UK is larger
than its single loop part V". Thus a multiple relayloop vector UK always possess a smaller relay-loop
vector V". This is an algebraic criterion that a relayloop vector is multiple. Therefore, the hecessity of
singleness of given short circuit conditions Cg" algebraically means the nonexistence of a smaller relayloop vector in all K dependent relay-loop vector CkK.
Dually, a multiple relay-cut-set covector singleness
of given open circuit conditions Bf K algebraically
means the nonexistence of a smaller relay-cut-set
covector in all H dependent relay-cut-set covectors
Bh K•
STATEMENT OF PROBLEMS
From the standard sum So, the prime implicant SI
and all other possible Boolean expressions Si, including their dual product expressions R o, R 1 , • • • R i , can
be algebraically obtained. Though a prime implicant
happens to be a monotone function, that is, of purely
unprimed literals or all primed literals, a minimum
network is often obtainable from its non-monotone
expression.
From the Boolean standpoint any S i is equivalent
to Ri for all values of i and j. However in topological
design, the simultaneous consideration of Si and Ri
is more convenient, especially for topological enumerations. In this case for each Si, if it has a corresponding network, the choice of R j of the same network is
desirable. For each Si, the corresponding R j is generally determined in this manner by examining
'whether the factors of R j form a minimum necessary
set of variables which should be zero in order that
the Si under consideration becomes zero. In Example 1,
Ri~ Si for all i.
However, in general the correspondence is not one
to one.
A necessary condition of realization of a standard
sum So or G terms by single contacts is that all linearly dependent relay-loops are included in the original sum. If a set of generating loop-vectors, C in
number, is realizable as a network, the above is also
the sufficient condition and there holds
(4)
Its proof is based on the exclusiveness of make and
break contact literals in all terms of So, on the odd
number in addition and on the non-existence of multiple loops. Dually for the standard product, there
holds
(3)
If the problem is given by short circuit conditions, for a realizable case.
one can start either from the standard sum (canonical
form) So or product Ro. Either is easily obtained
TOPOLOGIZATION
from the other. Generally there exist certain transA set of short circuit conditions of each of St:. is
formations ti of variables which keep the given sum
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
122
~
topologically a set of vectors Cg (i) in A (i) - dimenP1(i) ~ P(i) = Q(i) - 1
(9)
sional affine space expressing single relay-loops and
P1(i) + 1 ~ Q(i)
(5)
forms a branch-loop incidence matrix C/(i) of G(i)
rows and A(i) columns. Dually, a set of open circuits Especially, for a dual prime implicant R 1 ,
of each of -R i is topologically represented by a set of
P1(i) + 1 ~ Q(l)
(7)
covectors BIU) in A(j) - dimensional affine space
-+
expressing single relay-cut-sets and forms a cut-set The proof is based on the singleness of cut-sets, and
that P branches can form chords (links) of a cotree.
matrix BI,,(j) of F(j) rows and A (j) columns.
aO(i) - 1 = B(i) = rank (Bf,,(i» .
(11)
REALIZABILITY BY THE NUMBERS OF NODES,
Euler's relation
BRANCHES AND DEGREE OF FREEDOM
(13)
Each row of Cg" must be a single relay-loop. Then,
gIves
the number aO(i) of nodes must be equal to the "topoB~A-Q+1
(15)
~ogical length" of this loop, that is, the number of
1
a (i) of branches. Thus, the network must have at If this is not satisfied, there is no circuit for this Bf,,(i).
least a ° nodes which is equal to the maximum number
M=A-Q+1-B
(17)
E(i) of unities in a loop vector:
(6) gives the maximum permissible number of additional
aO(i) ~ E(i);
linearly independent "pseudocuts" , which are topologespecially for the prime implicant Sl,
ically single cut-sets but not Boolean cuts, by includ(S) ing make and break contacts of one relay or more in
aO(i) ~ E(l)
parallel. However, a general cut-set covector includThis is expressed also as
ing such pair-contacts is either a single relay-pseudoaO(i) - 1 ~ D(i) = E(i) - 1
(10) cut or a multiple cut-set, of which the included single
loop is not necessarily a pseudocut.
where D(i) is a topological distance of the terminals of
the relay branch, that is, the maximum number of
BASE VECTORS AND COVECTORS
variables (contacts) in a tie.
BY SEMI-DIAGONALIZATION
The rank C(i) of Cu" gives the degree of freedom P1(i):
P1(i) = C(i) = rank (C"g(i» .
(12)
Euler's relation
(14)
gives
C~A-E+1
(16)
If this is not satisfied, there does not exist a circuit
for this C0"( i).
(IS)
N=A-E+1-C
gives the maximum permissible number of additional
linearly independent "pseudoties", (which mean topological single loops but not Boolean ties by) including make and break contacts of one relay or more
in series. However, a relay-loop vector with unities
in pair contact components is a single relay-loop
pseudotie only when there are no smaller relay-loop
vectors. It is a multiple loop vector if there is a
smaller relay-loop vector. Dually, each row of Bf"
must be a single relay-cut-set covector. If the maximum number of contacts in each row of Bf" (which
can be regarded as a topological thickness of this
barrier between two terminals of the relay) is denoted
by P(i), and that of branches (which may be called
a topological width of the cut-set) is denoted by Q( i),
then there holds
The vector set Cu" defines an affine subspace of Cdimension. Its base vectors Cq" can be determined by
transforming Cu" into such a form that each row has
at least one unity which is the only one unity in its
column. If all rows acquire such unities, such Cq"
will be called a "semi-diagonalized" form. Further
transformation of the first square part of Cq" to a
unit matrix by adequate exchange of its rows and
columns is dispensable. The semi-diagonalization is
more easily done by a routine addition modulo 2 than
by multiplication of an inverse of a square part.
Then, all K linearly dependent vectors C/ are obtained from the base vectors Cq" by all odd number
sums. Ck " will be called "subties" in short. Dually,
base covectors Ba" and all H dependent cut-sets Bh"
can be determined. Bh" will be called" subcuts."
DETERMINATION OF CONNECTIONS
If the given vector set Cu" exactly coincides with
its base Cq" and all subties Ck ", that is, with W Cw ",
G = C +K = W,
(20)
then the remaining part is to realize the base Cq" as
a connection by its semi-diagonalization. If Cq" is not
realizable and N of Eq. 18 is a positive integer, there
is a possibility to realize it by the addition of pseudoties C n" up to N. C n" should not be smaller than
123
Okada, Moriwaki and Young: Realization of Boolean Polynomials
any of Cg and all subties generated by Cn and the
CqK should be either multiple loops or pseudoties. If
it is still nonrealizable, other Boolean expressions of
the same number of contacts should be calculated. If
all of them are unrealizable, only an increase of contacts enables realization. If some of the subties Ck K
are pseudoties and the rest are all included in C/, the
process is the same. Dually, if Bf K coincides with
BV K' that is, Ba K and B\ and
K,
K
t1t 2 = (Xy)
yx (xz)
ZX = (Xyz)
yzx
K
K
K
K
The group table is as follows.
TABLE I
THE GROUP TABLE
b
c name
y'z' l' Ro
2'
x'z'
x'y'
x'y'
0
0
0
1
1
0
5
1
1
2
3
2
3
4
5
2
2
4
3
3
5
4
0
5
4
3
1
0
2
5
2
3
1
4
4
4
2
3
1
5
0
5
5
3
1
2
0
4
K,
Example 116
Decimal expression of short circuit combinations:
4,2, 1, O.
prImes name
1
2
z'
y'
1. So = x
2
2
y
x'
z'
'--"
2
y'
z
3
'--" x'
4
y'
z'
3
,--"x'
1.3 1.3 1.3
a
t4 ,
t2t1 = (xz)
ZX (Xy)
yx = (Xyz)
zxy = t5 .
G9)
or BhK include some pseudocuts, then the realizability
of Ba is examined and if M of Eq. 17 is positive and
all sub cuts by Bm and Ba are either multiple-cuts
or pseudoties, the addition of Bm K may change Ba K
to a realizable one.
The above case is the simplest. In general, not all
of the subties Ck are included in the original Cg and
the rest of the subties CkK form multiple loops and
Boolean ties which are not included in C/o These
can give a new algebraic definition of the familial
"sneak paths". Subties CkK may include a "smaller
vector" than any vector of the given C/o Sneak paths
and such order relations should be eliminated either
by a change of i, of S t, or by an increase of contacts.
Dually, the algebraically defined "sneak barriers"
and smaller covectors in Bk K should be eliminated
either by a change of j of R j or by an increase of
contacts.
=
3'
x'z'
y'z'
4'
(x ,--"y , ,--"z')
(x' ,--"y,--"z')
(x' ,--"y' ,--"z)
(x' ,--"y' ,--"z')
The, combinations in Ro are identical with those in
So in this example.
2. The generators of the invariant transformations
are
yy' zz')
t1 = (xy) = ( XX'
yy' xx' zz' , t2 = (xz) .
All other elements tt are obtained from these two:
tIt 1 = to: unit element,
(yz) = t3 = tlt2t1 ,
= abc
,--"ab 1,-,ac2 '--" bc3
,--"a12 '--" b13 '--" c23
~]234
= Sl
,--"S2,-,S' 2'-'S" 2
,--"S 3 ,--"S' 3 ,--"k'f' 3
,--"S 0 •
All primed expressions are reduced to unprimed SI
by ti:
tIS' 2 = t 2S" 2 = S2,
t2S' 3 = t 3S" 3 = S3
Therefore it is sufficient to consider only SJi
3, 0) in further calculation.
1,-2,
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
124
TABLE II
8 1 = x' y'
'--" x'
z'
y' z'
'--"
82=
2
2
'--" x'
2
'--" x y' z'
z'
3
3
'--' x' y z'
3
'--" x'y'z
3
'--' x' y' z'
3
x4
1111
8 21
813
05
1211
8 22
813
x5
1121
t2 ~ 813
x5
111 2 ta
x3
1 11
8 11
x4
211
8 12
x4
121
t1 ~812
x4
11 2
t2 ~ 8 12
05
221
05
212
ta
122
~
Terms P
x' y' Z' Rll Q
1 3
Rl1 = (x' ,,--,y'
1 1
2
BfK = 1
(x'
,,--,z')
1 1 3
2
(
y' ,,--,z')
1 1 1 3
2
Bh K = .
2
12122
8 ao
x5
11 11 1
8 31
1
(subcut)
x: unrealizable
BfKCKq = Ifq
Bf
If pseudocu ts are added
CkK = 1
degree of freedom pI (R ll )
:. Branches:
S11 = x' y'
x'
"--'
a 1 (Rn)
z'
y' z'
= pI
~
+
factors D
2
2
2
P = Q - 1 = 2 = 3 - l.
aO - 1 ~ 2
+4
1
1 3
1 3
1 3
1
1
> Bh, Cg > Ck .
2x'
a
1
y'
1
z' S12
1
1
1
1
1
1
a'
1 , a' = a
+ 1.
The above C/ is the most general 2 contact case of
x' if a is regarded as an unknown (0 or 1), as is easily
proved.
- 1 =5.
x' y' z' S 1 E
1
C/ = 1
CKq = CqK.
0,
For S12, the corresponding C/ is given by
lx'
CK1
g
-
> B + 1 = 4.
~
This shows that there is no network which simultaneously satisfies BfK and C/o Also both the sub cut BhK
and subtie CK h have the order relation:
F = factors = 3, B = rank of BfK = 3.
P = maximum no. of terms = 2, Q = max. no. of
branches = P + 1 = 3.
nodes: aO(R ll ) = B + 1 = 4.
aO(R 11 )
131313 8 0
12
823
4. Rll and S11
2
8
823
~
0: realizable
2
3
3
'--" x y' z'
8 20
8 10
So = x y' z'
2
1222
222
2
'--" x' y z'
7
06
05
Sa = x' y'
2
y'
X'
D
D
D
D
1
222
D = max. no. of factors = 2,
E = max. no. of branches in loops = D + 1
G = no. of terms = 3, C = rank of C/ = 3.
1
=
3.
aO(Sn) - 1 ~ D = E - 1 = 2,
aO(Sn) ~ E = 3
Pl(SU) ~ C = 3
a1 (Sn) = pI + aO - 1 ~ 3 + 3 - 1 = 5.
Furthermore, though Rl corresponds to Sl, their incidence matrices do not form null-factors:
But G = C = 3.
Also the sub tie C 4 forms a sneak path. Hence, there
is no 4 contact realization in SI. In S2 obtained from
the C/ and CkK of S21 one gets a 1 = 5, aO ~ 4
pI ~ 2s. But G = C = 3. Furthermore, the subtie
C 4 forms a sneakpath. Hence, a single contact realization for S2 does not exist. Thus, there is no 4 contact
realization.
Cases of 5 Contacts
lx'
C/(SI3) = 1
a
CkK
1 = 6,
a
b'
= a'
aO
~
2x'
b
1
3.
Iy'
1
c
c'
:. pI
2y'
1
d'
~
z'
d
4.
1
1
S13
1
1
1
1
G = C = 3.
125
Okada, M oriwaki and Young: Realization of Boolean Polynomials
From R i , a O ~ B + 1 = 4 .
.'. pI = a 1 - a ° + 1 ~ 6 - 4
:. N = pI - C = 3 - 3 = O.
:. aO = a l - pI + 1 = 6 - 3
+1
= 3.
+1
= 4.
" Concerning the sub tie C4 , if a' = b' = c' = d' = 0 or
a = b = c = d = 1, then C4" = ..... 1 is smaller
than Cg' Hence, this is unrealizable .. The only other
possibility is that C4 expresses x' y'. Then
a' ,,-,b' = 1,
c' ,,-,d' = 1,
Fig. 1.
2x'
0
Sl3
or ab = cd = 0
G)
2y'
~
I x'
3
.
4
z
TABLE III
Case 1
2
3
2'
3'
l'
3"
3'"
4
a
b
c
d
0
0
1
0
0
0
0
1
1
0
1
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
1 -+ Case 2 by t I ,
o -+ Case 3 by t l .
1-+ Case 1, e.g. C 1 = C4 of case 1.
0-+ Case 3 by(ly', 2y') and tI,
1 -+ Case 3 by (lx', 2x').
0
lx' 2x'
1
1
C"g
-
Cl
C4 >
=
8 13
1
lx'
1 2x' (Fig. 1)
1 2y'
2
1
Fig. 3.
3
1
1
1
1
Case 1
ly' 2y' Z'
1
1
1
1
Fig. 2.
Fig. 4.
1
CI •
Case 3
:. C4 is a multiple loop.
The connection is obtained from Cg" by 'the ambit
method as shown in Fig. 1, because Cg" is already
semidiagonalized.
lx'
1
1
Cu"
Case 2
lx'
1
Cu"
Ck "
ly'
1
1
1
lx'
1
Cu"
2x'
1
1
2x'
ly'
2y'
1
1
3
2y'
Z'
8 13
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
ly'
2x'
2y'
1
1
3
Ck " = .
813
1
1
1
1
Z'
1
ly'
1
2
Z'
2y'
1
2x'
1
This gives a bridge of Fig. 3.
Case 4
813
lx'
2x'
2y'
1
Cu" = 1
1
1
1
1
1
1
1
1
1
1
1
Z' 8 13
ly'
1 lx'
1
2x'
1
1
1 1 1 1 2y'
2
3
1
Add CI to C2 in order to obtain semi-diagonalized Cq".
1
1
The circuit is obtained from semi-diagonalized Cu",
This yields another bridge of Fig. 4.
(see Fig. 2)
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
126
For S22, the following case is the most general form
of Co" based on is:
lx' 2x' y'
1
a
1
1
1
a'
1
X
C/
1
1
CkK
a
1
= 6,
a
O
~
4,
:. pI ~ 3.
Z'
S22
1
1
1
1
1
1
SI = W x' y z
,-"w' x y Z'
,-"W' x' y'
So = w x' y z
,-"W' x y Z'
,-"w' x' y' z
'-" W' x' y' Z'
16
1·3 1·3 2·2 2·2
11
R1 = (W,-"x,-"y')
(W'
,-"y )
(w'
"--,,Z)
(x' -,y )
(x'
"--,,Z')
G = C = 3.
C/ forms a pseudotie and it cannot be a multiple
loop.
N = pI - C = 3 - 3 = o.
Hence, there is no room of adding pseudoties.
This is semi-diagonalized to C/ by adding C 2 to Cs .
1
Cq,K
1
2x' y'
a
1
1
1
1
3
2
48
1
1
This generates 2 kinds of bridges as shown in Figs.
5 and 6. For S2S, the sub tie C 4 forms a sneak path xy'
or x. Hence, it is not realizable.
i1
_(wx x'w'WXw'x' yy y'y' z'ZZ')
= (wx)(zz') -
f for R t is long, only the dual prime implicant R1 is
given above.
4. The incidence matrix for S1 is
W
1
w'
1
1
CkK = 1
X
Fig. 6.
i
Example
217
1. The decimal expression of short circuit combinations is
11, 6, 1, 0 .
That of open circuits is
13, 12, 11, 10, 8., 7, 6, 5, 3, 2, 1, 0 .
Z'
Z
1
1
1
1
1
1
4
3
S1
1
1
1
1
1
1
5
6
1
E
5 W
5 x
4 y'
~0-L
~~
TABLE IV
1
2
4
3
5
6 Sum
1-5 1,2=4,3=5 1-5 1,2=4,3=5 1 =4,2=5,3 1-5
5
3
26
5
3
5
3
y'
The only sub tie C 4 is a single loop pseudotie. Furthermore C/ itself forms C/o Hence, if it is realizable, it
forms an answer. This C g K is already semidiagonalized
as seen in columns w, x, and y'. However, realization
of ambits in the order of dotted number proves that
this is not realizable as seen in Fig. 7. On the other
hand, the standard sum So is not realizable by single
contacts as easily seen from its subties or for the
reason explained in 3 (see eq. 4).
Application of L yields more networks and the total
number is gjven by Table IV. 16 ,18
Fig.
y
1
1
x'
1
1
2
a =I
Z
3. F = SI"--,,SO.
C(/
Fig 5.
1·2 1·2 2·1 1·1
2. The invariant transformation is only one:
lx'
z'
x
11
5·7 5·7 6·6 6·6
S22
1
1
1·2 1·2 2·1 1·1
4 IS
UNREALIZABLE
Fig. 7.
5.
aO ~
E(SI) = 5 .
pI = a1 -
5.
aO + 1 ~ 9 - 5
G=C=3.
N = pI - C
~
+
1 = 5.
5 - 3 = 2.
That is, an addition of pseudotie base vectors is possible, the maximum addition being 2.
Q(R 1) = 4,
pI ~ Q - 1 = 3 .
127
Okada, Moriwaki and Young: Realization of Boolean Polynomials
6. At first an addition of one pseudotie will be considered. In this case,
pI
aO
=
a
+ 1 = 4,
pI + 1 = 9 -
G
=
i
-
a1 = 9 ,
4
+1
1
CK
g
CnK
Ck K
t IC2
a
1.1
a' b' c'
= a' b' c
abc'
1
1
1
b
c-
1
1
1
1
1
1
e f
d
. . 1111
d' e f g' h' 1
d e' l' g' h 1
d' e' f' g h' 1
g
h
Case No.
=
1
2
6.
1
1
1
1
2
3
1
4
1 234
5xxx
6xx x
7x xx
8 x x x 8 = 2C-
3
4
23 •
TABLE V
tl -+ 9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
t1 -+ 10
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
e f
13
14
15
16
1
1
1
17
18
19
20
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
21
22
23
24
1
1
1
1
1
9b
25
26
27
28
-+9
-+10
lOa
1
1
1
1
1
1
1
1
1
9a
Case
29
30
31
32
1
-+ 13
1
1
1
1
1
1
1
1
1
1
1
lOb
1 1
1 1
1
1
33
34
35
36
t 1 -+ 12
-+10
t 1 -+ 15
-+ 12
12
The blank part is perfectly arbitrary.
(b) The pseudotie condition of C / algebraically
means that at least one pair of make and break contacts of one relay must both be unity. If this is
considered in the above combinations of values of
Ck \ all possible values are given as follows.
1
1 1
1 1
1 1
1 1
1 1
8
(a) Pseudo tie conditions of the subties Ck K.
1
1
1
1
1
1
1
7
=
1
9
10
11
12
6
1
1
1
1
1
1
e f
Ib
5
6
7
8
= C I , tICs = C 7 •
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
1
1
1
1
1a
The 8 components of the adding pseudotie form an
unknown quantity:
1
TABLE V1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
g
h
1
1
1
1
1
h
1
1
1
1
1
1
1
1
1
1
1
g
h
1
1
1
1
1
1
=
unr.
unr.
unr.
unr.
No.1
unr.
No.2
4
No.1 C 6
C6 < C 1
X C6 < C 2
X C6 < Cg
X
=
9
6 C6
No.2 C 6
4 C6
=
16
3 C6
2 C6
1 C6
1
1
1
1
1
1
1
1
g
h
1
1
1
1
1
1
1
1
a b
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 = 22
No.2 C 7
1
1
6 C7
1
No.1 C 7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
b
e f
1
1
1
a
b
1
1
1
41
42
43
44
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
37
38
39
40
13b
g
1
1
1
1
1
1
1
1
1
1
c
d
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
4
1
2
=
=
=
C7
C7
C7
C7
5
unr.
No.3
24
=
2
No.3 C 7
26 C 7
32
=
No.1 C s
26 C 8
No.3 C 8
19
=
=
21
No.4 C 6
urlr.
9
The ambit method can be applied to case la, lb, ...
and for each no., its subties CkK are listed in the following. Then, only 11 pseudoties are determined to
be linearly independent. 4 pseudoties are realizable
cases.
128
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
TABLE VII
Unrealizable Cases
1
2
4
6
7
8
Realizable Cases
1 1
1
No.1
1 1 1 1 1 1 1 1 1
1 1
1
1
1 1
1 1
4
6
7
8
1 1
1 1
1 1 1 1 1 1 1
1
1 1
1 1 1
1 1
1
No.2
4
6
7
8
1 1 1
1
1 1 1 1 1 1
1 1
1 1
1
1 1
1 1 1
No.3
4
6
7
8
1 1 1 1 1
1 1 1 1 1 1
1
1 1
1 1
1 1
1
1
No.4
6
4
6
7
8
1 1 1 1
1 1 1 1
1
1
1 1
1
1 1
1 1 1
1
1
26
4
6
7
8
1
1
3
4
43
4
6
7
8
4
6
7
8
1 1 1
1
1 1
1 1
1 1
1
1 1 1 1 1
4
6
7
8
1
1 1 1
1 1 1 1 1
1
1 1
1
1 1
1 1
1
1 1
4
6
7
8
1
1 1 1 1
1 1 1
1
1 1 1
1
1 l' . 1 1
1
1
1 1 1 1 1
4
6
7
8
1
1 1
1
1 1 1 1
1 1 1
1 1
1
1 1
C/ =
5
VALUE OF f
e =0
f=1 UNREALIZABLE
Fig. 9.
1
1 1 1
1
1 1
1 1
1 1 1 1 1 1
1
e =I
NO
2
1 1
Fig. 10.
1 1 1
1
1 1 1
1
1 1 1
1
1 1
1 1 1
1 1
ef =. .
= . 1
= 1 .
= 1 1
1
1 1
1 1
1 1
1
1 1
1
1 1 1
1 1 g h 1
x'
1
1
1 1
1
1
y' z Z' SI
1 g' h . w
. g h' 1 x
1
1 w'
1 1 g h 1 Y
2
Add Cs to C 2 , then add C 4
to C1 and C 2 •
345 1
~
~. w·
5.
•
Ck " = 4 1 1 1 1
Case 9b
a b
Only No. 26
1
No. 27 1
y
Fig.8.
Case Ib
1 1
1
1
111
1 1
1
1
1
ef 1 1 1
g h I g h =.
No.1
1
1 C6 < C1
1
1
C6 < C2
1
1 1 C6 < Cg
to No.1. C 6. All other 3
Hence, it is unrealizable.
6
g' h'
7
1 1 1 1 g' h
8 1 1
1 1 g h'
No. 9 of Case 6 is identical
are smaller than one of C/o
'
3 IS UNREALIZABLE
realizable No. 1
unrealizable as seen from Fig. 9
realizable No. 2
unrealizable as seen from Fig. 10
Case 6
3 is unrealizable independent of g and h as
seen from Fig. 8.
1
IS UNREALIZABLE
INDEPENDENT OF THE
1
1
1
1
Case la
1
NO I
are unknown.
y
w w'
z S'
1
1 1 1
1 1 1
1 1
1
1
1 1 1
1 1 a b' 1
1
1
1
1
1 1 1
. 1
111
a b .
111 a b
. 111
x'y y'z SI
1 1 . 1
1
1 w C/ =
1 1 e' f' 1 1 x
1 1 . 1
1 w' This is semi-diagonalized by 4 5
. e f l l l z' adding C 1 to Cs and C 4 to C 2 •
This is semi-diagonalized by
2 4 5 3
1
See Figs. 9 and 10.
adding Cs and C 4 to C 2.
3
2
x'
x
y'
z'
1
The ambit 5 is unrealizable for No. 26 as seen
from Fig. 11.
Okada, Moriwaki and Young: Realization of Boolean Polynomials
129
Case lb: ef = . . (Fig. 9, No.1)
1:
NO 26
0=0
a =I
(8 w w' x z') (w w' x x') x' 8 z'
= (8 w w' x z') (w w' x x') 8 x' z'
3:
(8 w' (w x z z') z) (w w' x x') 8 x' z'
= (8 w' z (w x z z')) (w w' x x') 8 x' z'
4:
(8 w' z (( w x y) y z z')) (w w' x x') 8 x' z'
4' :
(8 w' z (w x z z')) (( w x y) w' x' y) 8 x' z'
6
y
NO 27
2:
b =I
Fig. 11.
Q',Cir
(8 w w' x z') 8 w w' x z'
5 (possible only from 4) :
b =0
(8 w' z ((w x y) y z z')) (( w' x y') w x' y') 8 x' z'
(8 w' z) (w x' y') (y z z') (w x y) (w' x y') (8 x' z') .
NO 3
Fig. 12.
The coboundaries of the individual nodes are contained in the parenthesis.
Case lOa, No. 30, x, x', z and z' are semi-diagonalized
by adding C3 to C 1, C 4 to C3. (Fig. 10, No.2)
NO 4
1:
(8 x' z') 8 x' z'
Fig. 13.
2:
No. 27 is realizable and gives No. 3 of the solutions
as seen in Fig. 12.
The first two connections Nos. 1 and 2 of Figs. 10
and 12 do not change by the transformation t I • However, No.3 changes to No.4 of Fig. 13 by t I • C/ of
No.4 is obtained from C/ of No.3 by t I •
Case 13b
No. 43
1 1 1 1
1 1 1
1 1
1
1
1
C/ = . 1
111
. 1
1
w'
1
1
1
1 1
This is semi-diagonalized by
adding C4 to CI .
x x' y
8
1 1 1 1
. z
1
1
1 1 z'
1
1
1 y'
1
1 w
2 3 4 5
1
In Fig. 14, the ambit 4
is unrealizable.
~~,,@w'
Fig. 14.
The algebraic ambit-realization is as follows.
3:
4:
5:
(8 x' z') 8 x' (z' w x z) w x z
= (8 x' z') (w x z z') 8 w x x' Z
(8 x' z') ((w x z z') w x x' w') 8 z w'
(8 x' z') ((w y z' (x y z)) w w' x x') 8 w' z
= (8 x' z') (( (x y z) w y z') w w' x x') 8 w' z
(8 x' z')((((x y z) w y z') w x' y') w' x y') 8 w' z
(8 x' z') (w y z') (w' x y') (x y z) (w x' y') (8 w' z) .
130
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
7. The addition of 2 pseudoties in Sl.
C/-
-3>
C/
t
1
x
x
x
2
x
x
x
x
3
x
x
7
x
x
8
x
x
9
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5
3
4
5
6
x
x
x
x
4
1
2
10
11
12
13
14
15
16
1
a
m
1
1
1
1
b
n
c
d
p
q
1
a'
a'
a
m'
m'
m
l+a+m
a+m
a+m
l+a+m
b'
b'
b
n'
n'
n
b+n
1+~+n
l+b+n
b+n
1
1
c
c'
p'
p
p'
c+p
l+c+p
c+p
l+c+p
(2) The above 12 vectors C 4 , C5 and C k are not
smaller than any of the 3 original short circuit
relay-loop vectors CI, C 2 and Cs. These conditions are necessary for realization.
h
u
1
1
1
1
g'
g'
g
t'
t'
t
l+g+t
g+t
g+t
l+g+t
h'
h
h'
u'
u
u'
h+u
l+h+u
h+u
l+h+u
1
1
1
1
e
r
d'
d
d'
q'
q
q'
l+d+q
d+q
l+d+q
d+q
1
8
1
e
e'
e'
r
r'
r'
l+e+r
l+e+r
e+r
e+r
1
l'
l'
8
8'
8'
1+8
1+8
1+1+8
1+1+8
The base vectors C q K and the subties C k K must satisfy
the following conditions:
(1) Vectors C 4 and C5 are added and all subties C k
are either pseudoties or multiple loops.
g
t
1
1
1
c'
1
1
1
1
1
1
1
1
1
1
1
1
TABLE VIII
w
1
2
3
4
5
6
7
8
No. 3-4
26-4
No. 4-4
43-6
No. 2-4
6-4
No. 1-4
2-7
3-8
4-4
1-6
w'
x
x'
y
y'
z
Z'
81
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
t.
1
1
1
1
The minimum number of branches in a multiple
9
1
1
loop can be determined by the following reasoning.
10
1
1
The minimum number of branches in C/ is 4 (in
11
1
1
1
1
1
1
Cs). However, a pseudo tie can have only 3 branches
as in C4 of No.1 of Fig. 9. On the other hand, the Out of l1C2 = 55 combinations, it is not so difficult
minimum number of contact branches of a local loop to find all possible combinations for which the new
consisting only of contact branches is 2 as xy' 'jn 4 subties CIS - C16 satisfy the algebraic pseudotie
No. 3 of Fig. 12. Therefore, in this example, the condition. ClCS, CIC 6 and CsC 6 are the only possible
minimum number of total branches of a multiple combinations, and these build pseudoties at wx, wy'
loop is 4 + 2 = 6.
and xy', respectively:
Since the number of variables is 4, every multiple
loop has at least one pair of make and break con- wx, 1,3:
y
Z'SI
x
tacts of one relay, that is, all multiple loops will be
included in the subties Ck" if all vectors satisfying
111
1
1
1
1
w
algebraic pseudotie conditions are considered.
1 1
1 1
1 1 w'
111
1
In 6, all possible vectors satisfying the algebraic
y'
111
1
1
1
x'
1 1
1
pseudotie condition are already obtained for single
1
111
vectors. Therefore, if any pair of these vectors
1
111
1
1 1 1 Z
further satisfies the algebraic pseudotie condition for
C13 , C14 , C15 and C16 , and the resulting base vectors Semi-diagonalization:
2
4
3 1
Cq" are realizable, then a network of solution can be 1. Add Cl to C4 , C2 to Cs.
This is realized in Fig.
obtained. For this purpose, the following vectors
15 as No.5.
were chosen, one from each of 11 sets of the subties of 2. Add C4 to Cl and Cs.
Table VII.
3. Add C5 to Cl .
Okada, M oriwaki and Young: Realization of Boolean Polynomials
NO 5
Fig. 15.
Fig. 16.
The other two: wy': 1, 6 and xy': 3, 6 generate only
the networks of the same type. tl changes No.5 to
No.6 of Fig. 16. Thus, these 6 networks are the only
possible single contact realizations.
ACKNOWLEDGMENTS
This research was sponsored by the Office of
Scientific Research under Contract No. AF-18(600)1505.
The authors extend their thanks to Dr. E. F.
Moore, Dr. T. H. Crowley of B. T. L., N. J., and to
Dr. C. F. Hobbs of C. R. C., Mass., for their kind
information of recent publications.
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497-508 = ColI. W. 22-33 (briefly: 64(1845) 497-514 = ColI.
W. 1-22) Trans, IRE PGCT-5.1 (March 1958) 4-7.
[2J O. Veblen, "Analysis Situs (1916) Cambridge Colloqium,"
(1922, 2. ed. 1931) AMSCP. 5, 2.
[3J Gr. C. Moisil, "Sur la theorie algebrique de certains circuits
electriques, .J. de Math. pur et appl." 9.36 Fasc. 4(1957) 313-24
and many others.
[4J S. Okada, "On a Theory of Relay Circuits," lecture note at
Nippon Elec. Co. Tokyo (May 22, 1939) pp. 24 in Jap.
S. Okada, "Preliminaries on Network Theory," J.I.E. Com Eng.
Japan 27.12 (Dec. 1943) 9-22 in Jap.
M. Hanzawa, "Theory of Relay Networks," (18) Nichiden
Geppo 19.4 (April 1942) 10-7. in Jap.
T. Kojima, "Introduction of Automatic Exchange System,"
(1948) Kagaku-Shinkohsha, 239-241 in Jap.
S. Okada, "Topology Applied to Switching Circuits," Proc.
Symp. Information Networks, PIE (April 1954) 267-90. This
will be referred as O-tasc.
S. Okada, "A Topological Synthesis of Switching 2-Terminals,, ,
Res. Rep. R-756-59 (July 1959) MRI, PIE.
K. P. Young, "Analysis and Synthesis of 2-Terminal Contact
Networks by Algebraic Topology and Combinatorial Analysis,"
Master's Thesis. E. E. (Sept. 1959) in prep. as Res. Rep.
R-779-59, MRI, PIE. Also see R-790-59.
[5] L. Lund, "Koplings muligheter," Norsk Mat. Ttds. 31(1949) 9
S. Seshu, "On Electrical Circuits and Switching Circuits," Trans.
IRE PGCT-3 . 3 (Sept. 1956) 172-8.
131
J. P. Roth, "Combinatorial Topological Methods in the Synthesis of Switching Circuits," IBM Res. Rep. RC-11 (June 29,
1957) Poughkeepsie, N. Y.
J. P. Roth, "Algebraic Topological Methods for the Synthesis of
Switching System I," Trans. AMS. 88. 2 (July 1958) 301-26.
J. P. Roth, "Combinatorial Topological Methods in the Synthesis of Switching Circuits," Proc. Symp. Switching (April 2,
1957) in printing.
J. P. Roth, "Algebraic Topological Methods for the Synthesis
of Switching Systems, IV, Minimization of Singular Boolean
Trees," Meeting of AMS, Detroit, Michigan (Nov. 27-8, 1958).
O. Wing, "The Path Matrix and the Realization of its Associated
Graph," Doctor Thesis of Eng. Sc. (May 1959) Columbia Univ.
N.Y.
O. Wing and W. H. Kim, "The Path Matrix and Switching
Functions," J. Frankl. I. 268.4 (No. 1(06) (Oct. 1959) 251-69.
L. Lofgren, "Irredundant and Redundant Boolean Branch
Networks," Trans. IRE PGCT-6. Spec. Suppl. (May 1959)
158-75.
L. Lofgren, "Solution to the Realizability Problem for Irredundant Boolean Branch-Networks," J. Frankl. I. 268.5 (No.
1(07) (Nov. 1959) 352-77.
U. L. Vasilev, "Minimum Contact Networks for Boolean
Functions of Four Variables," Doklady Acad. Nauk. USSR
127.2 (June 1959) 242-5.
[6] R. Gould, "The Application of Graph Theory to the Synthesis of
Contact Networks," Ph. Doctor Thesis (May 1957) Harvard
Univ. Cambridge. Proc. Symp. Switching (April 3, 1957) Harvard Univ. in printing.
R. Gould, "Graphs and Vector Spaces," J .•"Math. Phys. 37.3
(Oct. 1958) 193-214.
R. Gould, "A Note on Contact Networks for Switching Functions of Four Variables," Trans. IRE PGEC-7.2 (Sept. 1958)
196-9.
[7] Staff of Compo Lab., "Synthesis of Electronic Computing and
Control Circuits," (1951) Annals of Compo Lab. 27, Harvard
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R. A. Higonnet arid R. A. Grea, "Logical Design of Electric
Circuits," (1958) McGraw Hill, N. Y. Orig. in French (1955)
Berger. Lerault, Paris.
[8] E. J. Dasher, "Semantics and Kirchhoff's Current Law," Proc.
IRE 47.6 (June 1959) 1158-9.
E. A. Guillemin, "How to Grow Your Own Trees from Given
Cut-Set or Tie-Set Matrices," Trans. IRE PGCT -6 Spec.
Suppl. (May 1959) 110-26.
R B. Ash and W. H. Kim, "On Realizability of a Circuit
Matrix," Trans. IRE PGCT-6.2 (June 1959) 219-23.
W. T. Tutte, "A Homotopy Theorem for Matroids," Trans.
AMS.88 (May 1958) 144-60, 161-74.
W. T. Tutte, "Matroids and Graphs," Trans. AMS. 90.3
(March 1959) 527-52.
L. Anslandet and H. M. Trent, "Incident Matrices and Linear
Graphs," J. Math. and Meeh. 8.5 (Sept. 1959) 827-35.
[9] S. Okada, "On the Fundamental Equations of the Networks,"
Nippon Elec. Com. Eng. 14 (Dec. 1938) 504-8, Tokyo.
[10] S. Okada, "Algebraic and Topological Foundations of Network
Synthesis"Proc. Symp. Mod. Network Synth. (April 13-5, 1955)
PIB 283-322.
S. Okada, and R. Onodera, "Theory of Interlinked Electromagnetic Networks and Fields in the Tensor Geometry of
Linear Space, et.," in K. Kondo, "Memoirs of the Unifying Study
of the Basic Problems in Eng. Sc. by Means of Geometry,"
Vol. 1 (1955) Gakujutsu Bunken Fukyu-kai, in Tokyo Kogyo
Daigaku, Oh-Okayama, Meguro-ku, Tokyo, 1-112.
S. Okada, "Network Topology in N-dimensional Geometry,"
lee. note at Columbia Univ. (Dec. 16, 1958) Mimeogr.
[11] H. Weyl, "Reparticion de Corriente en una red conductora,"
Rev. Mat. Hisp.-Amer. 5(1923) (1) 153-64 (3): 241-9.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
132
W. Cauer, "Synthesis of Linear Com. Networks," (2ed. 1958)
McGraw Hill, N. Y. p. 90-3.
[12] G. Kron, "~on-Riemamsian Dynamics of Rotating Electrical
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G. Kron, "Tensors for Circuits," (1959) Dover, N. Y. (This
includes a complete list of his publications.)
tions, which means determination of all possible connections would
take a long time. We are now doing research on this particular
program.
[13] = 4: O-tasc. 267, 275, 279.
G. G. Murray (RCA): Existing minimization methods are limited to
series-parallel nets. However, these methods are quite useful. The
method described in the present paper presumably gives a true minimum but is it a practical procedure? How many Boolean variables
can be handled?
[14] e.g. H. Whitney, "Geometric Integration Theory," (1957)
Princeton Math. 8. 21.
J. A. Schouten, "Ricci-Calculus" (1954) Springer, Berlin.
Mr. Okada: As soon as the number of variables increases, the juxtaposition of all possible Boolean functions is not so easy, but with a
computer will be possible.
[15] R. L. Ashenhurst, "A Method for Determining Functional
Invariance, Theory of Switching," Rep. BL-2, (April 1953)
Harvard Compo Lab.
S. Sharin (RCA): How can this method be used to advantage to
design code translators? Can the logic element used - relays, diode
circuitry, and so forth - be introduced as a factor in getting a
direct solution?
E. J. McCluskey, Jr., "Detection of Group Invariance or Total
Symmetry of a Boolean Function," B.S.T.J. 35.6 (Nov 1956),
1445-53. Mon. 2720.
[16]
=
Reference 7, Hig. 191, IV 2 •
[17]
=
Reference 7, Hig. 197, H21.
[18] See Reference 5, Vasilev.
DISCUSSION
H.G.Boehm(IBM): Can your method be programmed on a computer?
Mr. Okada: Yes, we are considering it, but as yet we have not made a
program of it. If the number of variables increases, calculations by
these computers seems to be the only possible method.
Mr. Boehm: How long would it take to prove Moore's table as
minimal?
Mr. Okada: I don't know. Unfortunately we could not finish. The
proof is not so difficult, but to exhaust all possible minimum solu-
Mr. Okada: As a general principle this principle is applicable for
design of any switching circuit. As I mentioned at the beginning this
method can also be used to design series-parallel connections.
K. Enslein (Brooks Research): How does this new method differ
from that which resulted in the Harvard tables?
Mr. Okada: According to my knowledge, the late Dr. Roderick
Gould gave the best results, especially in the improvement of Dr.
Moore's table. But Dr. Gould's method was not mathematically
rigorous, and in most cases he gave only one solution; but, as I showed,
all possible solutions can be given by our method. Our ambit method
of realizing connections from a cut-set matrix is the dual of Gould's
method of realization from loop matrices, which needs three kinds of
operations: parenthesis, brackets and braces. In our algebraic ambit
method, one kind of operation is sufficient as shown at the end of
Paragraph 6 of Example 2. Also, we gave the maximum permissible
number of pseudocuts or pseudoties which can be added, as shown
in Paragra.ph 5 of Example 2. Generally, we use tie-set matrices
and cut-set matricies simultaneously. We are planning to publish a
paper on the "ambit realization."
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
133
Applications of Boolean Matrices to the Analysis of
Flow Diagrams
REESE T. PROSSERt
INTRODUCTION
NY SERIOUS attempt at automatic programming of large-scale digital computing machines
must provide for some sort of analysis of program
structure. Questions concerning order of operations,
location and disposition of transfers, identification of
subroutines, internal consistency, redundancy and
equivalence, all involve a knowledge of the structure
of the program under study, and must be handled
effectively by any automatic programming system.
The structure of a program is usually determined
by detailed specifications describing the program, and
may usually be given a convenient geometric representation by means of flow diagrams. Ordinarily,
neither of these forms is immediately adaptable for
handling by machine, and for this purpose another
representation of the same information must be
found. Such a representation should certainly have
these properties:
(1) It should be easy to construct and reproduce.
(2) It should be adaptable to handling by machine.
(3) It should contain all of the information provided by the topology of the flow diagram.
A
THE CONNECTIVITY MATRIX
A representation which has all these properties may
be given by means of Boolean matrices. By a Boolean
matrix we mean a matrix whose entries consist entirely of O's and l's. The representation is constructed
as follows: Suppose we are given the structure of a
program, say in the form of a flow diagram consisting
of boxes, representing program operations, connected
by directed line segments, representing the program
flow. We are interested only in the structure, or connectivity, of this diagram, and not in the properties
of the individual boxes. We make no restrictions at
all on the connectivity and, in particular, branches
and loops of all kinds are admissible. We begin by
numbering the boxes of the diagram, say from 1 to n,
in any convenient manner whatever. For later convenience we adjoin to the diagram a box numbered 0
as the initial, or input, position and a box numbered
n + 1 as the final, or output, position of the diagram.
We next construct an (n + 2) X (n + 2) Boolean
matrix, A = (aij), called the connectivity matrix
* The work reported in this paper was performed at Lincoln
Laboratory, center for research operated by M.LT. with the joint
support of the U. S. Army, Navy and Air Force.
t Massachusetts Institute of Technology Lincoln Laboratory,
Lexington, Mass.
associated with the diagram, by stipulating that
a,j = 1 if the diagram contains a directed line segment leading directly from box i to box j, and aij = 0
otherwise. Thus a t1 = 1 if box i may be followed
immediately by box j in the program, and 0 otherwise.
It is evident that this matrix is easy to construct
and easy to handle. It is determined uniquely by the
diagram, up to a permutation of the entries due to a
renumbering of the boxes, and in turn it determines
the diagram, in the sense that the diagram may be
completely reconstructed from the matrix. Thus it
meets all of our requirements.
This idea is certainly not new. Boolean matrices
have been used extensively to study the connectivity
and orientation of graphs [7], [12]; networks [4], [6];
organization and group dynamics problems [8]; and
more generally, finite Markov processes [11]. Shannon [13] has pointed out that every flow diagram is
essentially a finite Markov process, so that we have
here a very special case of [11]. On the other hand it is
worth emphasizing how well this idea adapts itself to
program analysis. A similar attempt with a somewhat
different viewpoint appears in [14].
ANALYSIS
Certain elementary computations on the connectivity matrix yield detailed information on the
program flow. To show how this comes about, we
define a one-row matrix
ei = (0, 0, ... , 1, ... , 0)
with 1 in the ith place and O's elsewhere. Then, from
the definition of A, we see that the Inatrix product
eiA is a one-row matrix which has 1 in the jth column
if it is possible to proceed from box i to box j in one
step, and 0 otherwise. By repeating this argument,
we see that the product eiA 2 = (etA)A is a one-row
matrix whose jth column is 1 (or more) if it is possible
to proceed from box i to boxj in exactly two steps, and
o otherwise. A similar interpretation may evidently
be given to higher powers of A.
N ow A 2 need not be a Boolean matrix. But it is
clear that for our purpose we lose nothing if we replace
all non-zero entries in A2 with l's. This amounts to
multiplying A by A according to the following rule:
The Boolean product A v B oj the Boolean matrices A
and B is that Boolean matrix whose i-j entry is
Vk
Here v and
1\
(atk 1\
bkj )
denote the Boolean operations of max
134
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
and min, respectively. In the same spirit we define:
The Boolean sum A /I. B of the Boolean matrices A and
B is that matrix whose i-j entry is a~i v bii . Thus Boolean
sums and products of Boolean matrices are formed in
the same way as ordinary matrix sums and products,
except that + is replaced by v and X by /I..
N ow the way is clear for induction. Let A be the
connectivity matrix of a flow diagram, and define
Am = A m- 1/I. A = A /I. A /I. • • • • • • • • /I. A m times
Bm = Bm-1vA m =A 1 vA 2 v ........ vA m
Theorem 1
The i-j entry of Am is 1 if it is possible to proceed
from box i to box j in exactly m steps, and 0 otherwise. The i-j entry of Bm is 1 if it is possible to proceed
from box i to boxj in at most m steps, and 0 otherwise.
Proof: For m = 1, both statements reduce to definitions. Now suppos'e both statements hold for
m = r; and consider the case m = r + 1. The i-j
entry of Ar+l is just V k(cikAakl) where Ctk denotes the
i-k entry of A r • This is zero, unless for some k we
have Cik = aki = 1. But this means that it is possible to proceed from boxito boxkin exactlyrsteps,
and from box k to boxj inexactly one step. Thus the
i-j entry of Ar+l is 0 unless it is possible to proceed
from box i to box j in exactly r + 1 steps. The
second statement follows immediately from the first.
Theorem 2
The limit lim B m as m ~ en exists as a Boolean
matrix, which we denote by B. Moreover, we have
B = Bm for all m ~ p, where p is the length of the
longest open path in the diagram.
Proof: Since the entries of Bm are monotone increasing with m, it is clear that lim Bm as m ~ en exists
and forms a Boolean matrix. The second statement
follows from the observation that if it is possible
to proceed from box i to box j at all, it is possible
to do so along an open path (i.e., one containing
no loops), and hence in less than p + 1 steps. Thus
if the i-j entry of Bm is 1 for any m, it is 1 for m = p.
This means that Bm = Bp whenever m ~ p.
Theorem 3
The i-j entry of B is 1 if it is possible to proceed
from box i to box j in any number of steps, and 0
otherwise.
Proof: This follows immediately from the proof of
Theorem 2.
The matrix B is obviously computable by machine
from the matrix A, and since only Boolean operations
are involved, the time required for this computation
is not prohibitive even for fairly large n. On the other
hand, it follows from Theorem 3 that the matrix B
contains detailed information about the consistency
of the flow diagram. We cite some obvious examples:
(1) It is possible to get from the input to box i only
if bOi = 1. Thus if there are no spurious boxes,
the top row of B must contain all l's (except
for boo).
(2) It is possible to get from box i to the output
only if bi(n+l) = 1. Thus if there are no boxes
without exits, the last column of B must contain all l's (except for b(n+1) (n+l))'
(3) It is possible to get from box i to box i only if
bii = 1. Thus if there are no loops in the program, the main diagonal of B must contain all
O's. Boxes involved in loops are represented by
l's on this diagonal.
(4) After leaving box i, it is possible to go through
boxj only if bii = 1. Now if we alter box i then
only those boxes following box i in the program
will be affected. These boxes are represented
by l's in the ith row of B.
(5) If the matrix decomposes into relatively independent submatrices, then the program decomposes into relatively independent subprograms. Thus it may be possible to identify
natural subprograms directly from the form of
the matrix B.
EXAMPLES
The foregoing theory will be further illuminated by
application to concrete problems. As a first example
we choose a flow diagram containing an obvious inconsistency, and shovy how this inconsistency is
0
~
t
~
1
3
~
4
2
I
+
6
Fig. 1.
~t
,
5
II
Prosser:
Boolea~
135
Matrices in the Analysis of Flow Diagrams
00011
reflected in the matrix B. The diagram is shown in
00000
0 N
Fig. 1. Here the boxes are already numbered, in~l~d
00001
ing the input and output boxes. The connectIvIty
matrix for this diagram is a 7 X 7 matrix, whose where M = 11 and N = 011 This implies that
entries are
11
000
010 100 0
001
001 0000
boxes 1 and 2 and boxes 3, 4 and 5 form two indepen010 000 0
dent subprograms whose associated matrices are just
A
000011 0
M and N. (Of course, the simplicity of this decomposi000 000 1
tion is due to the particular scheme adopted for
000 0011
numbering the boxes.) This simple example serves to
000 000 0
illustrate the scope of the method.
Now Al = BI = A. Straightforward computation
This same method has an obvious application to
gives
the problem of debugging programs already compiled.
001 011 0
In this case the boxes are already numbered by the
0100000
sequential description of the program. Moreover, it is
001 0000
not necessary to draw the corresponding flow diaA2 = A AA
000 001 1
gram, since, except for transfers, each operation is
0000000
followed by the next in sequence. As a second example
000001 0
we take a typical SAP writeup of an IBM 704 pro0000000
gram, with no inconsistencies. (This program computes an array of 100 quantities Cij according to the
011 111 0
formula
011 000 0
011 000 0
A i - B j if i >
B 2 = B 1 V A 2 = 000 011. 1
CiJ = { Ai + B i if i ~ j
000 000 1
SAP Program
000 001 1
1. LXD 8
0000000
2. SXD 4
010 0011
3. CLA B1
001 0000
4. TXL 6
0100000
5. CHS
As = A 2 A A
000 001 0
6. ADD Al
0000000
000 001 0
7. STO C1
0000000
8. TXI
9
9. TXI 10
011 111 1
011 000 0
10. TNX 2
011 000 0
11. TXI 12
B s = B 2 V As = 000 011 1
12. TNX 2
000000 1
13. END
000 001 1
The
associated connectivity matrix can be written
0000000
down directly, and is simply
A glance at the diagram shows that all possible
010 000 000 000 0
paths (without repetition) can be traversed in at most
001 000 000 000 0
three steps, so that by Theorem 2, B = Bs. This can
000 100 000 000 0
be checked by computing B 4 , which is equal to Bs.
000 010000 000 0
From this matrix we verify immediately that all
000 001 000 000 0
(N ote that, except for
boxes are connected to the input (first row), but
000 000 100 000 0
transfer instructions,
boxes 1 and 2 are not connected to the output (last
A
000000 010 000 0
l' s appear only on the
column). Boxes 1,2, and 5 are involved in loops (main
super diagonal.)
000 000 001 000 0
diagonal). Moreover, if we delete the first row and
000 000 000 100 0
last column of B, then the remainder can be decom010000 000 010 0
posed into submatrices:
000 000 000 001 0
11 000
010 000 000 000 1
11 000
M 0
000 000 000 000 0
.i}
136
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
THE PRECEDENCE MATRIX
A further analysis of the structure of a program can
be made if information concerning the precedence relations in the program is available. If we know, for
example, that the output of box i is required for the
input of box j, then we know that the operation
represented by box i must precede that represented
by box j in the program sequence. Clearly this places
additional requirements on the internal connectivity
of the program.
The precedence relations may be incorporated into
our analysis through the introduction of a second
Boolean matrix C associated with the program, which
we call the precedence matrix, (cf. ll, 9]). It is constructed as follows. We number the boxes of the
diagram as in Section II, and stipulate that the i-j
entry Ci1 of C is to be 1 if the output of box i (or any
part of it) is required for the input of box j, and 0
otherwise. Clearly this matrix contains the precedence
relations in the same way that the matrix A contains
the connectivity relations of the program, and will
yield to a similar analysis. We observe here that the
two matrices are closely related, though they need
not be identical.
Proceeding as before, we define
Cm = Cm - 1 A C
Dm = Dm- 1 v Cm
D = lim Dm
m-+ co
and observe that the results of that section may be
translated immediately into the present situation. In
particular, the i-j entry of the matrix D is 1 if and
only if there is a chain of boxes in the diagram beginning with box i and ending with box j such that each
box in the chain must precede the next. Obvious
applications include the following:
(1) The precedence requirements are internally
consistent only if the diagram contains no
closed chain of boxes each of which must precede the next. This is the case only if no diaonal entry of D is 1. Thus we require that trace
D = 0 for this consistency (cf. [1]).
(2) In general, box j depends on box i only if
d ii = 1. Thus if box i is altered, this will affect
only those boxes whose entries in the ith row
of Dare 1.
(3) Occasionally it is desirable to reorder the
sequence of operations in some part of the
program. This is possible only if the precedence
requirements are not violated by the reordering. Thus box i may be interchanged with box
j in a chain of operations only if d ii = d ii = O.
Information of this kind is evidently useful in
optimizing flow diagrams for time or storage
requirements.
THE DOMINANCE MATRIX
In studying problems involving the reordering of
operations in a program, it is often useful to introduce a notion of dominance in the flow diagram,
defined as follows: We say box i dominates box j if
every path (leading from input to output through the
diagram) which passes through box j must also pass
through box i. Thus box i dominates box j if box j is
subordinate to box i in the program. It may happen
that two boxes dominate each other (in which case
we say they are equivalent), or that neither dominates the other (in which case we say they are indep·endent). The idea here, of course, is that reordering is
possible only among boxes which are equivalent in
this sense. Proceeding along these lines, we define a
third Boolean matrix E, called the dominance matrix,
by stipulating that the i-j entry eii of E is 1 if box i
dominates box i~ and 0 otherwise. It is clear that the
dominance matrix is determined by the connectivity
matrix, and can be produced from it by a suitable
scanning procedure. Applications include:
(1) Box i and box j may be interchanged, precedence requirements permitting, only if they are
equivalent. This is the case only if we have
eii = eii = 1.
(2) In preparing a program for a machine which
admits parallel operation, it is desirftble to
know which operations in the program may be
performed simultaneously. Two operations
may be performed simultaneously without
further investigation only if they are equivalent and subject to no precedence requirements,
i.e., only if d ii = d ii = 0 and eii = eji = 1.
(3) It is sometimes useful to know when two programs are equivalent in some sense. Anyeffective definition of equivalence requires a detailed knowledge of what happens at branch
points in the program (i.e., the transfer conditions). An interesting analysis of this problem
is summarized in [14], but does not seem readily
adaptable to machine handling. By requiring a
less effective definition of equivalence, we can
give here an effective criterion for determining
whether or not two programs are equivalent.
To be precise, let us agree that two programs,
containing the same operations subject to the
same precedence requirements, are equivalent, if,
for each path (leading from input to output)
through the first, there is a corresponding path
through the second passing through the same
operations. We do not require that the operations appear in the same sequence, or even that
they appear the same number of times, in t0t::,
paths. This definition, however, is sufficient for
most purposes, at least for programs containing
no loops; loops cannot be incorporated under
Prosser: Boolean Matrices in the Analysis of Flow Diagrams
so simple a scheme, and requIre special
consideration.
,
In terms of flow diagrams, the equivalence
criterion may be stated as follows. Two diagrams, made up of the same boxes subject to the
same precedence requirements, are equivalent
only if their dominance matrices are identical.
137
[2] I. M. Copi, "Matrix development of the calculus of relations",
Jour. Symbolic Logic, vol. 13, pp. 193-203; 1958.
[3] W. Feller, "An Introduction to Probability Theory and its
Applications," John Wiley and Sons, New York, N. Y., p. 350;
1957.
[4] F. Hohn and L. Schissler, "Boolean matrices and the design of
combinational relay switching circuits," Bell System Tech. Jour.,
vol. 34, pp. 177-202; 1955.
[5] M. Kac and J. C. Ward, "A combinatorial solution of the 2-
REMARKS
The essential point of our discussion is that the
entire analysis given here can be readily performed
on any (large-scale) digital computer. The feasability
of computing the derived matrices B, D, and E by
machine is assured for programs which are not too
large. A very crude estimate indicates that the time
required to compute B from A on the IBM 704 is of
the order of 10 n 3 cycles, where n is the number of
boxes in the diagram. In practice, this time may be
reduced considerably by combining into one box any
subroutine whose behavior is known. Thus for example it is advantageous to replace any chain of
boxes by a single box. Similarly, in analyzing program writeups it is sufficient to consider only transfer
operations. For instance, a reduced form of the
matrix A of our second example is:
A'
0100000
001 0000
010 100 0
0000100
010 001 0
0000000
where boxes 1 through 9 have been combined in a
single box.
Finally we remark that it is a straightforward
problem to construct a debugging routine which could
be used to analyze any program writeup whose
transfer instructions have constant addresses. Such a
routine would scan the writeup, enumerate the
transfer instructions, construct the connectivity and
dominance matrices from them, compute the derived
matrices and point out any errors detectable by these
methods. Thus the whole analysis becomes completely
automatic.
Various other applications of this analysis are
suggested by the results. By utilizing the evident
adaptability of these matrices to computer handling,
it is possible to construct automatic program analysis
schemes which would detect in proposed programs a
large class of common errors, isolate and identify key
subroutines and reorganize them in optimal equivalent
programs. Such a scheme is currently under investigation here at Lincoln Laboratory, MIT.
BIBLIOGRAPHY
[1] E. W. Barankin, "Precedence Matrices," Uni". of Chicago Management Sciences Research Project, Research Report no. 26;
December, 1953.
dimensional Ising model," Phys. Rev., vol. 88, pp. 1332-1337;
1952.
[6] G. Kron, "Tensor Analysis of Networks," John Wiley and Sons,
Inc., New York, N. Y.; 1939.
[7] S. Lefschetz, "Topology," Colloq. Publications Amer. Math.
Society, New York, N. Y.; 1930.
[8] R. D. Luce and A. D. Perry, "A Method of matrix analysis of
group structures," Psychometrika, vol. 14, pp. 95-116; 169-190;
1949.
[9] R. B. Marimont, "A new method of checking the consistency
of precedence matrices," Jour. Assoc. Compo Mach., vol. 6, pp.
164-171; April, 1959.
[10] J. Riordan, "An Introduction to Combinatorial Analysis,"
John Wiley and Sons, Inc., New York, N.Y.; 1958.
[11] D. Rosenblatt, "On the graph and asymptotic forms of finite
Boolean relation matrices and stochastic matrices," Naval Res.
Logist. Quart., vol. 4, pp. 151-167; 1957.
[12) H. Seifert and W. Threlfall, "Lehrbuch der Topologie, " ,
Chelsea, New York, N. Y.; 1947.
[13] C. Shannon and W. Weaver. "The Mathematical Theory of
Communication," Univ. of Illinois, Urbana, Ill.; 1949.
[14) Y. I. Yanov, "On matrix schemes," Dokl. Akad. Nauk. USSR,
vol. 113, pp. 39-42; 1957.
DISCUSSION
E. Fredkin (Bolt, Beranek and Newman): In the case of a closed subroutine used by more than one calling sequence, how do you represent the fact that, while many routines enter and many exit, the
subroutine box may return only to the calling routine?
Mr. Prosser: Problems of this kind, of course, are not handled at
all by this formalism. Nothing has been said about how you make
the decisions about where to go. I have deliberately avoided this.
Thus, the whole theory is a black box theory. Now actually in some
flow diagrams there are paths which you cannot follow at all, because the appropriate combination of logical requirements is never
satisfied. This formalism will not tell you that. The best it can do
is tell whether there is a path going from here to there, without
telling whether or hot the conditions for it are met.
Mr. Shapiro (Nat'l Institute Health): Given that your formalism
does not account for the nature of decision-making elements, what
is the definition of equivalence?
Mr. Prosser: Well, there is an interesting problem here. Let me say,
first of all, there is a study by the Russian mathematician, Yanov,
who has made a definition of equivalence which says, roughly speaking, that two programs are equivalent if they go through the same
boxes in the same order. That is, for each path through one program,
there is a path through the other one which does the same operations
in the same order. In order to prove statements like that, you have
to know something about how many times you go around loops, and
I have no way of counting this in the present formalism.
So the definition of equivalence which I'm using here must be
very weak. It would run something like this, and this is, in fact, the
precise statement to which I was referring: two diagrams are equivalent if, for every path through the first one, there is a path through
the second one which goes through the same boxes, not necessarily
138
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
in the same order and not necessarily the same number of times.
But they do the same things. You recognize that this definition is
quite weak unless you know something more about the number of
times you go around loops. Using this for a definition, then the
statement is that two diagrams are equivalent only if their dominance matrices are identical.
c. E. Dorrell (lBM): Do you have a program to compute F the
dominance matrix, and, if so, what is its running time?
'
Mr. Prosser: This is in the process of being put together. It should
take about the same running time.
Mr. Miller (MITRE): Do you have a way of automatically generating your first matrix?
H. D. Fnedman (Technical Operations): Since B is a geometric series
of powers of A, although in the Boolean sense, isn't there an analytic
method for obtaining B?
Mr. Prosser: You can do this in some cases, but not from a diagram. You can do it, for example, from an SAP write-up or from
certain other kinds of write-ups automatically, providing that certain restrictions are placed on the write-ups - that they not be
too complicated. As far as flow diagrams go, there is an obvious
problem here. If you work from a flow diagram, you have to try
somehow or other to get the diagram into the machine. We don't
really know how to do this effectively, but then we really haven't
studied the question. What we've done in actually running this experimentally is to take a typical flow diagram and try to draw
these matrices by hand. All you have to do is record the l's, of
course. I don't know how to do it automatically.
I would like to say, though, that this program which I refer to,
which computes the derived matrix B, we intend to submit to
SHARE, so it ought to be available to the computing world fairly
soon.
Mr. Posser: The question can be rephrased this way. Let BK be
the Kth step of the B matrix. How far out do you have to go before
you have reached the limit? As I have indicated already, there is a
number such that, beyond that, the BK'S are already constant and
are equal to the limiting matrix. How far out is it? Well, an upper
?ound is the length of the longest path through the diagram, which
IS alway~ less tha? the number of boxes in the diagram. Actually,
our routme doesn t compute B by the process which I showed on
the slide. If you look at the matrix A plus A square, and raise this
to high powers, it turns out that this process gives you B. Now for
a 5~ by 500 matrix, something like 2 9 powers is enough, so the
maXImum number of squarings required is something like nine.
So there is an upper bound which is not too big. The thing which
makes this feasible, of course, is that the matrices are all zero's and
one's. It is much easier to do matrix operations with them than
with the usual matrices with arbitrary entries.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
139
SIMCOM -The Simulator Compiler*
THOMAS G. SANBORNt
N MANY present-day activities involving the use
of digital computers, the need often arises to run
programs on a computer other than the one for
which they are written. For example, the computer
on which a program is intended to be run may exist
only as a proposed design, or it may be in some stage
of construction, or it may simply be at a remote location!. One solution to the problem posed by such a
situation is to prepare a program for an available
computer which, in effect, transforms the availablt
computer into the unavailable computer. Such a
transformation program is called a computer simula·
tion program, since it gives one computer the ability
to simulate another.
Because of the intricate logical relationships which
prevail in computers, the preparation of a simulation
program is time consuming and fraught with opportunity for error. Furthermore, changes in the specifications of the computer being simulated may
necessitate a major overhaul of the simulation
program. For these reasons a new programming
language and its associated compiler, SIMCOM
(standing for Simulator Compiler), are being developed to assist in the preparation and modification of
simulation programs which are to be run on the IBM
709.
It must be clearly understood that SIMCOM is
not, itself, a simulation program. It is a generating
program which accepts statements written in a specialized simulation-oriented source language, and
from these statements generates instructions in
SCAT language similar to those a human programmer
would write in preparing a simulation program.
The fundamental unit of SIMCOM coding is the
statement. Each statement is either a definition
of a component of the simulated computer or a description of some data manipulation or control function which occurs during the execution of instructions within the simulated computer. These two
kinds of statements are known, respectively, as
definition statements, and procedural statements. Related statements are grouped into paragraphs. SCAT
coding, including SCAT-type remarks, may be intermixed with the paragraphs should the SIMCOM
I
language prove inadequate for describing some involved procedure. The characters which may be used
to write statements include the upper-case Roman
letters, the decimal digits, and certain special characters. Combinations of alpha-numeric characters
are called symbols. The three uses of symbols are: 1)
to represent components of the simulated computer;
2) to identify locations within the simulation program; and 3) to denote integers. Every symbol,
unless it represents an integer,. must contain at least
one alphabetic character, and no symbol may be
iden tical to a word of the basic SIM CO M vocabulary.
A simulation program written in the SIMCOM
language consists of three parts: the "Machine
Definition;" the "Instruction Interpretation;" and
the "Panel Operation." These sections describe,
respectively, the static machine, the machine in
operation, and the effect of operator intervention.
The Machine Definition is given in six paragraphs
labeled "REGISTERS," "MEMORY," "INPUT," "OUTPUT," "KEYS," and "INDICATORS." Each definition
statement describes a machine component or cell,
giving its name, bit structure, and, if appropriate, its
address or range of addresses. For coding convenience,
a register may be defined as being synonymous with
part or all of another register. Furthermore, registers
can be defined which have no counterpart in the real
computer being simulated. No distinction is made by
SIM CO M between so-called primary and secondary
storage.
LOCAT.
I
6 8
TEXT
16
REGISTERS. MR(S 1-35). AC(S Q P 1-35).
PCR(35-0).
UAK(l4-0) SYN PCR(29-151.
DRUM(35-0)
MEM0RY. Cf/lRE(S,I-35) 0-4095.
16384 -32767.
72
INPUT. CAROlS 1-351.
f/lUTPUT. PRNTR(S 1-351.
KEYS. RESET. L0AD. START. MJI. MJ2. MSI. MS2.
INDICAT!2IRS. IlVFL!lW. I!lCK. DVCK. E!2ITA. RUN.
TRAP.
in9:l
• Presently being developed under a purchase order from Thompson Ramo Wooldridge, Inc., in support of their contract to supply
technical direction to the Automatic Data Processing Facility, U. S.
Army Electronic Proving Ground, Fort Huachuca, Arizona.
t Space Technology Laboratories, Inc.
1 For a description of the applications of SIMCOM anticipated by
USAEPG see: A. B. Crawford, "Automatic Data Processing in the
Tactical Field Army", Proceedings of the Western Joint Computer
Conference, pp. 187-189; San Francisco, March 1959.
Fig. 1-Simcom coding form showing typical definition paragraphs.
Fig. 1 shows examples of some typical definitions
selected from several well-known computers. This
figure also illustrates the basic requirements of the
form on which SIMCOM coding is to be written.
Some users may wish to use a form on which each
140
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
card column is marked since blank positions are
frequently essential in the language. Note that the
first line of each paragraph is indented to column
16 and that subsequent lines begin in column 8. The
compiler uses this convention to aid in distinguishing
between SIMCOM statements and SCAT instructions which may be included in the source code.
In all of the machine component definitions, the
symbols used to identify the various devices are quite
arbitrary, the only limitations being that they conform to the previously stated rules pertaining to
symbols, and that they do not conflict with the basic
vocabulary. The most common method of selecting
symbols will undoubtedly be to adopt those used by
the machine manufacturer in his manual since these
are usually highly mnemonic.
The Instruction Interpretation and Panel Operation sections of the simulation program are written
in terms of procedural statements. A procedural
statement consists of a primary operation together
with one or more operands called expressions, arranged to form a stylized sentence. Each primary
operation is denoted by one or more words from the
~)asic SIMCOM vocabulary. This vocabulary includes
'ords for transferring, clearing, complementing,
~ esting, comparing, and shifting arrays of bits in the
larious components of the simulated computer, plus
words which control the logical flow of the simulation program and the compilation process itself.
The expressions upon which the primary operation
act consist of symbols combined by means of secondary operations. These secondary operations include
(add), - (subtract), * (multiply) $ (indirect
address), and certain words of the basic vocabulary
which denote logical arithmetic and scaling. A symbol
in an expression may have bit designators appended
to it if only part of the component identified by the
symbol is to participate in the operation.
Fig. 2 shows a few paragraphs of procedural statements. In the figure the expressions are underscored
for emphasis but this would not be the normal practice on a coding form. Note that the first paragarph
bears a location symbol. In many instances, however,
cross references bel.ween paragraphs are implicit in
their relationship to vne another. Therefore, many
paragraphs will need no iocation symbols attached
to them.
The instruction interpretation section is the heart
of the source program. It will normally contain statements which describe the procurement of instructions
from the simulated computer's storage, followed by
statements which describe the effects of each instruction. The various instruction interpretations can
usually best be initiated by use of a "table look-up"
statement. Depending on the complexities of the
instructions and the associated timing, each instruction description may require as little as one simple
statement or as many as several paragraphs including,
+
perhaps, entries to subroutines and additional table
look-ups. Fig. 2 illustrates a simple example of this
technique.
LOCAT.
I
S 8
LIIl\lJP
IIlPER TABLE.
TEXT
IS
IC $ Till IR. IC + I Till IC.
72
L~K
UP IR(I-5) IN
CL\lJCK 4. EXECUTE LfIlIIJP.
TABLE.
\lJPER
O. IR(S-17) Tf/J IC. TURN RUN 0FF.
I
IR(S-17) Tf/J IC
2. IF f)VFL0W IS 0N TURN 0VFl0W 0FF.
IRIS-I7I
Till IC.
5. EXECUTE GET. EXECUTE SUBTRA.
CL!11SE.
u ..
Fig. 2-Typical procedural paragraphs showing instruction procurement and interpretation technique. "Expressions" underscored
for emphasis.
A "Table," as understood by SIMCOM, is an
ordered set of paragraph~ of procedural statements,
each paragraph being identified by an integer. The
table look-up operation provides a means for selecting
one of these paragraphs for execution, depending on
the value of the argument expression. If a paragraph
in a table does not terminate with an explicit transfer
of control to some other point in the simulation
program, then control returns to the statement
following the "LOOK UP ... " statement which
invoked the paragraph. Thus each paragraph in a
table is like a closed subroutine.
The panel operation section of the simulation program includes an interrogation of the status of each
console key and a description, written in SIMCOM
statements, of the behavior of the simulated computer
if the key has been activated.
It is not uncommon for certain keys on computer
consoles to be so constructed that they are turned
off as soon as the function which they perform has
been initiated. The programmer's statements must
include this action, if appropriate. Furthermore, in
some cases certain keys are inoperative unless other
keys or indicators are in a particular status. The
programmer must also provide this logic.
One of the most interesting features of the system is
the subroutine library. Subroutines are. stored in
the library in the SIMCOM language, except that
the symbols denoting the subroutine parameters are
replaced by variable symbols of a special kind. At
compilation time, as a subroutine is called from the
library, its special variable symbols are replaced by
the parameter symbols given in the library call
statement, and its location symbols are replaced
by arbitrary unique symbols. The subroutine is
then inserted into the source code where the SIMCOM decoder and instruction generator processes
141
Sanborn: SI MCDM - The Simulator Compiler
r
it in the same manner as any other set of SIMCOM
statements. This process is illustrated in Fig. 3.
THE SUBROUTINE IS ORIGINALLY CODED AS
A
+
ON-LINE
CARO
REAOER
SlMCOMOESIGNEO
CONTROL
CAROS
I
PROGRAMMERSIMCOM-GENERATEDI
WRITTEN, SIMCOM- COMPUTER OPERATOR
TRANSLATED
KEYS
+
"PANEL"
ROUTINE
- IREGISTERS
SUBR(lJUTINE ADD, A, C.
B T(IJ C. CL0SE.
- r-
~
THE LIBRARY MAINTENANCE ROUTINE WILL PLACE THE SUBROUTINE
IN
THE LIBRARY IN THE FORM
ADD
VI
+ B TIIJ V2. CLf/)SE.
AT A SUBSEQUENT COMPILATION,
ADD
2. DATA
709
>-CORE
A STATEMENT OF THE FORM
LIBRARY
WILL CAUSE THE SUBROUTINE
MEMORY
I. PROGRAM
ADD, P, Q.
TO BE INCORPORATED INTO THE PROGRAM AS
P ... B Tf/) Q.
CL(lJSE.
Fig. 3-Sample subroutine showing generalized variable technique.
A given subroutine may be called from the library
any number of times during one compilation and,
depending on the parameters listed in the library
call statement, each version may give rise to a different number of 709 instructions. Each version of a
subroutine called from the library is a "closed"
routine which can be executed from any point in the
simulation program.
The output from SIMCOM is a translation into
SCAT language of the source program. This includes
a direct expansion of the procedural statements, plus
certain pseudo operations for assigning storage and
certain utility routines whose necessity is only implied by the source language. These include routines
for loading the simulated computer, diagnostic output routines and, of fundamental importance, a
routine which allocates the simulated computer's
storage to the various 709 storage media. This storage management routine must partition oversize
words, should such have been defined, into the 36-bit
words of the 709, and shuttle simulated computer
storage to and from 709 tape units if it exceeds the
capacity of the 709 core storage. The endowment of
the compiler with the ability to generate efficient
storage management routines is the most challenging
problem facing the creators of SIMCOM.
Fig. 4 is a schematic representation showing the
allocation of the generated program to the various
parts of the 709. The heavily outlined areas indicate
the parts of the 709 used to represent the various
registers and storage of the simulated computer. The
remainder of the 709 contains the generated simulation program and its associated utility routines. The
arrows indicate the communication paths between
the various areas of the 709.
Because the SIMCOM output is in SCAT language, the compiler need not contain within itself an
assembly program, nor does it have to be able to
process the SCAT instructions included in the input
code other than to recognize them as SCAT in-
SIMCOM-GENERATED
STORAGE MANAGEMENT
ROUTINE
PROGRAMMER -WRITTEN,
SIMCOM- TRANSLATED
INSTRUCTION INTERPERTER
SIMCOM-GENERATED
INPUT -OUTPUT
SUPERVISOR
1
...t
SIMULATED
INPUT
VIA
729 TAPES
SIMULATED
OUTPUT
VIA
729 TAPES
ADDITIONAL
SIMULATED
MEMORY
ON 729 TAPES
Fig. 4-Allocation of elements of a Simcom-prepared
simulation program to 709 core and tapes.
structions. Most important, however, is the fact
that generation from SIMCOM statements to SCAT
instructions can be done during a single pass through
the source program. In addition to generating, SCAT
language instructions, the compiler transforms each
line of SIMCOM coding into a SCAT-type remark
(* in column 1) and inserts each paragraph into the
generated code immediately ahead of its SCAT language expansion. Thus each paragraph serves as
commentary to describe the function of the generated
SCAT instructions which follow.
The SIMCOM language is such that apparently
minor modifications to the input statements can
completely alter the character of the generated program. For example, a change in the definition of a
register of the simulated computer may cause SIMCOM to generate instructions to do multiple precision
arithmetic where single precision arithmetic was
formerly sufficient, or a change in word size in the
simulated ~omputer may cause SIMCOM to reorganize completely the simulated computer's storage in
the 709 core. Thus changes which could be made to a
machine-like language simulation program only by
completely rewriting the program can be incorporated
into a SIMCOM-written simulation program by a
simple re-compilation.
The SIM COM system will provide a means
whereby users who are not necessarily professional
programmers may prepare simulation programs for
binary computers in a language not unlike that used
by computer manufacturers in their manuals. There
seems to be no escaping the fact that the user will
need to be more than casually familiar with the
computer to be simulated before he can write an
adequate simulation program, even with SIMCOM.
142
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
DISCUSSION
P. Armer: Is your work far enough along so you can comment on two
things with respect to timing? One, let us say with a simulated
machine not too different from the 709 that didn't have to do with
double precision arithmetic. Could you give us some notions on the
efficiency time lapse?
Mr. Sanborn: Since we have not actually constructed any simulation
programs yet, I couldn't give you an answer from experience, but we
are optimistic that the simulation programs generated by SIMCOM
will be relatively efficient as compared to handwritten codes. I am
not sure it would be too efficient for a machine similar to the 709,
because it could not capitalize on the similarities of the machines.
Mr. Armer: In simulating a machine one would be interested in how
fast the program would run. Have you anything to solve this problem?
Mr. Sanborn: There are language statements for keeping track of
time; the clock statement we saw was one. One can, in writing down
the description of the instructions, also include information as to the
execution time - as a matter of fact, keep a running total of the
elapsed time in the computer. This may become particularly important where you have independent devices running and may want to
keep several clocks running in order to determine which unit is going
to run next and keep them in proper synchronization.
G.L.Foster(IBM): Do you assume the machine being simulated has a
fixed word length? Will SIMCOM handle variable word lengths as
on the 705?
Mr. Sanborn: I think it would if the registers are defined in terms of
smallest accessible storage. I question whether it would be practical,
but it would be possible.
execution time of the generated program.
R. J. Scott (Dept. of Defense): Could SIMCOM simulate a machine
with an automatic interrupt feature as is used on STRETCH?
Mr. Sanborn: I think if a machine has a feature like this, you must
write statements in the language which quite frequently enters the
panel operation section to test interrupt conditions.
I. Flures (Dunlop Assoc.): In debugging a program for a computer
to be simulated, how will the 709 indicate program faults or other
errors?
Mr. Sanborn: I am not sure that the 709 will indicate faults in the
program of the simulated computer. There are diagnostic facilities
in the generated program. For example, statements calling for certain
registers to be printed out. This may be diagnostic or it may be
results from the program running in the simulated computer.
R. W. Bemer (IBM): Does it simulate only binary machines?
Mr. Sanborn: Only binary machines in the sense that for any other
sort of machine one would have to define a representation of the
information in the computer in terms of binary digits.
Mr. Bemer: Does the syntax correspond to or use Gorn's microflow
chart technique?
Mr. Sanborn: I don't know, because I am not familiar with this
technique but I would guess not.
E. B. Shore (Pratt & Whitney): Can SIMCOM be used to compare
various computers on a benchmark program? How about multisequence computers?
Mr. Sanborn: I am not sure what is meant by benchmark pr.ogram.
R. Cornish (IBM): Is this program universal only with respect to the
particular family of computers?
Mr. Armer: Well, anyone can dream up a program and see how various
machines do on this same program.
Mr. Sanborn: No, I wouldn't say this. We tried to make it general for
binary computers with word sizes not greater than 72 bits.
Mr. Sanborn: SIMCOM would provide the means for constructing
the simulation program for trying out various computers. It bas in
itself no mechanism for evaluating these computers on the basis of
running the benchmark program.
Mr. Cornish: Approximately how many man years were involved?
Mr. Sanborn: I haven't checked the figures recently but I imagine
up to this time we have invested two man years.
D. J. Campbell- (AGT): How much machine time would be used in
a typical compilation?
Mr. SanbMn: I don't think I would want to predict this. I haven't
been at all concerned on compiling time. I have been concerned about
Mr. Armer: If I understood the question of the clocks, it would tell
you how long it would take each machine to run the particular
program.
Mr. Sanborn: Yes, the clocks would tell you running time but if you
wanted to get more involved information about the relative merits
of the computers this is beyond the scope of SIMCOM.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
143
Unusual Techniques Employed in
Heat Transfer Programs
D. J. CAMPBELLt AND D. B. VOLLENWEIDERt
PROGRAM for the IBM 704 to solve general
transient and steady state heat transfer problems
is described. The computer program was developed by Evendale Computations Operation in cooperation with the Jet Engine Department, General
Electric Company, Flight Propulsion Division. Jet
Engine Department personnel who were instrumental
in the formulation of the problem are Mr. William K.
Koffel and Dr. J. M. Botje. Dr. James T. Anderson,
of Michigan State University, acted as a consultant
and played a central role in the development of the
program. The method of solution permits the analysis
of problems with arbitrary geometry and several combined modes of heat transfer. To facilitate the description and solution of extensive and complicated
problems, many logical and computational techniques not usually applied to engineering calculations
are incorporated in the program.
The program yields the temperature distribution
at a maximum of 200 points in three-dimensions for
homogeneous or composite bodies. Heat transfer by
conduction, convection, surface flux, thermal radiation, both solid and gaseous, and internal heat generation is treated. One dimensional fluid flow in several
channels can be incorporated. The thermal properties
of the system may vary with temperature. Boundary
conditions and heat transfer rates for convective exchanges as well as surface flux rates and mass flow
rates may vary with time. Internal heat generation is
given either as a function of time or of temperature.
A
THERMAL
NON-SOURCE,SINK
CONDUCTION
STORAGE
FLUID HEAT TRANSFER
8 CONVECTION
CpV(To-TJ)= eW(Tf-TO)
6.T
+
f [An{Tn-TO~+
n=1
6.X n
ance equation that is written for each node is given
in Fig. 1. Note that T' indicates temperatures at the
beginning of a time interval. The radiation terms are
linearized by writing them as a radiation coefficient
times a first power temperature difference. The radiation coefficient is computed using the temperatures
at the beginning of the time interval, while the linear
temperature difference uses a given radiation source
temperature. The implicit form of heat balance equation is used in preference to the explicit form, because
the stability requirement for the explicit form places
a limit on the time increment which is restrictive for
large systems. The implicit form permits more freedom in the choice of time step. The accelerated
Gauss-Seidel method is used to solve the system of
heat balance equations for the n unknown temperatures. Gauss-Seidel is used in preference to other
methods because the convergence criterion for the
method is readily met for most applications and because there are a large number of zero elements in
the coefficient matrix.
One of the most interesting features of the program
is the method used for describing the geometry. Rectangular coordinate systems are not adequate to fully
describe the variety and intricacy of shapes commonly encountered in applications of the program.
INTERNAL HEAT
GENERATION
OoV
1
-K- + he
SURFACE
FLUX
3
+A; Of +
SOLID
RADIATION
3
~ 2:
1=1 5=1
GASEOUS
RADIATION
3
[o-A 1 FI {Th4_T04U +
f:
J=l
[o-A j Gj {E g T3 -
agT~
il
Fig. I-The general heat balance equation. To indicates the temperature at the beginning of a time interval. Linearized versions of
the radiation terms are actually programmed.
The method of solution for the temperature distribution is to divide the geometry into cells enclosing
nodes and to write heat balance equations (in finite
difference form) for each node. The general heat balt Flight Propulsion Laboratory Department, General Electric
Company, Cincinnati, Ohio.
Fig. 2-As an example of the method of dividing an object into cells,
the plate of a steam iron is shown. Note the irregular manner in
which the cell division has been made.
Instead, the geometry is divided into cells of any
shape or size, and the cells are given numbers to
identify them. Fig. 2 shows how the plate of a steam
Iron might be divided into cells. At most six faces
are defined for each cell, and the faces are labeled
by numbers from one to six. Fig. 3 illustrates the
numbering of faces of a cell. In order to write heat
balance equations, it is necessary at each cell to give
144
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
5
tion are used to increase the number of faces for the
cell that occupies the position in the center of the
drawing. Since the cells are assumed to have zero
volume and zero thickness, there are no thermal
storage terms and no thermal gradients across them.
Therefore, they will have no effect on the heat balance except to balance the cell in the center against
all of the surrounding cblls. These nodes increase the
effective number of faces of the central node from
six to eleven.
Fig. 3-Illustration of the convention for numbering
the faces of a cell.
the adjacent cell, if any, for every face through
which there is conduction. In the program, this is
done by giving the number of the cell adjacent to
each face. A convention with respect to adjoining
cells makes it unnecessary to give the number of the
face of the adjacent cell. The face common to two
adjacent cells is, of course, assigned a number in each
of the cells. As can be seen from Fig. 4, if a face is
labeled "I" for one of the cells, then it must be
labeled "3" for the other cell. Similarly, if the face
is labeled "2" in one cell, it must be labeled "4" in
the other, and if it is labeled face "5" in one cell, it
must be labeled face "6" of the other.
Fig. 5-Examples of irregular shapes that have
been divided into cells.
[L.::t~\\==:::::::!::::;::::::::::=;========-,t\\
~~3
\
\
\1"'"'
\
\
\
\
•
\
\
\
•
•
\
\
\
\
\
\
I
FACE I
FACE 3
I
•
.,,
I
,
I
I
I
I
I
•
•
•
I
I
I
I
I
'..........
t
FACE 2
I
+
FACE 3
t
FACE 4
t
FACE 5
Fig. 4-Illustration of the face numbering convention for adjacent
cells. The l1umbers assigned to a face of adjacent cells must be one
of the pairs (1, 3), (2, 4) or (5, 6).
Fig. 6-Illustration of a method for increasing the effective number
of faces of a cell. By including two 'zero volume' cells, the number
of faces of the long, innermost cell is increased to eleven.
Although this method of describing geometry may
seem awkward at first glance, it conveniently accommodates unusual patterns of cells and irregular surfaces. Fig. 5 shows some unusual shapes that may be
accommodated with this method of describing
geometry. It can be seen that cells need not have
six faces and can be highly irregular in shape. Any
faqe not needed for conduction exchanges may be
used to accommodate special effects. For example,
in Fig. 6, the two narrow cells exploded out of posi-
A symbol defining a table of thermal properties is
given for each cell in the system. These properties
are tabulated as functions of temperature. Given the
geometry description and the material symbol just
mentioned, sufficient information is available to
assemble the conductive heat transfer equations. In
describing the dimensions of a cell, a distinction is
made between "regular" and "irregular" cells. Regular cells are rectangular parallelepipeds, or linear
approximations thereof, and only height, width, and
Campbell and Vollenweider: Techniques in Heat Transfer Programs
depth of each cell are required as input. For irregular
cells, distances from each face to the node point, face
areas, and the cell volume must be specified. Physical
parameters and boundary conditions are given as
functions of time or of temperature. For example,
tables of adiabatic wall temperature and fluid film
coefficient are given, and the collection of tables is
assigned a symbol. The symbol defining the applicable tables of functions is entered for the proper face
of the cell which has a convective heat exchange. An
analogous method is used to indicate other modes of
heat transfer. That is, the functions are defined and
identified by a symbol, and the symbols are given at
each appropriate cell. Consequently, there are two
basic types of information for a cell. One gives the
dimensions of the cell and other geometric constants
such as configuration factors for thermal radiation.
Secondly, symbols are given to define the surrounding
geometry, to indicate the modes of heat transfer,
and to define the tables of values of the various
parameters.
From the symbols describing the cell configuration
and corresponding properties, the heat balance equations may be assembled for each time step,. However,
an assembly directly from symbols would require a
large number of sorting procedures on the basis of
node numbers and table symbols. To avoid searching
for information designated by symbols more than
once, a simple device is utilized in the program. Each
symbol is replaced by the machine address of the
initial memory location of the information defined
by the symbol at the beginning of the program,
before any temperature calculations are begun. The
searches that are undertaken automatically check
for completeness. If a table or node has not been
given, the search for the location of that table must
fail. When such a failure occurs, a comment is printed
giving the symbol of the missing table or node.
COL.
10
13
In.c lhc
CELL NO.9
1011
31sc
1
CELL NO. 13
4 1 so
16
19
22
25 28 31
·~1·0<.2'.
I
1 AA
361
I
1
1021
34 37 40 43 46 49
4n.c.4b.c. Sn.c. Sb.c. 6n.c 6hc. MAT. S.Cd.
5031
IA
I
16 1
1
31 1
~~~I
~9:,
631
2021
I
661
7 1
I
DMI
eM
Q
1
OMI
R
Fig. 7-An example of data describing the geometry of a problem.
The connection between cells number 9 and 13 is illustrated to
indicate the need for checking its consistency.
Further examination of the form of the input incicates that testing the cell connection information is
highly desirable. The method of describing geometry
requires that connection information for adjoining
cells must be given for the designated face of each
cell. This may be seen by examining Fig. 7, a facsimilie of the cell information input form. The entries
necessary to define a connection between cells 9 and
145
13 are indicated. If the connection is not indicated
for both cells, erroneous heat balance equations will
be generated, and the equations may yield results
that appear correct but are in error in the vicinity of
the inconsistency. Moreover, the volume of data
required for large problems encourages error in input.
Consequently, the program checks the consistency of
cell connections and makes many other tests for completeness of input data to recognize and identify
errors before the equations are assembled. The
machine time required for these completeness and
consistency tests is negligible when compared with
overall computing time.
It can be seen that the method for describing
arbitrary cell configurations does necessitate considerable pre-processing, searching, and testing of
input data. If the geometry were described by the
usual mesh or lattice point scheme, input for the
network could be organized by three-dimensional
arrays and could be assigned to ordered blocks of
machine storage. There would be a simple arithmetic
relationship between nodes and the corresponding
memory location of information pertaining to nodes.
However, if it is necessary to describe and analyze
arbitrary patterns of cells enclosing node points, a
simple arithmetic formula for computing the address
of the machine location of information for another
node from the address of a given node cannot in
general be established.
Having presented some of the interesting aspects
of the program, we would like to describe possible
extensions of the techniques and methods employed.
In the present program, input data is stored in fixed
sections of memory. Consequently, there are specified
limits for the maximum number of entries in a table,
the number of tables of a given variety, and the
maximum number of cells in the division of the
problem. These restrictions do not allow the available memory space to be used efficiently for many
problems. In a subsequent program, similar input is
stored in consecutive memory locations which are
computed as the data are read into memory. Since
sections of data are not assigned fixed storage locations, an economical means for finding specified
quantities is necessary to accomplish the processing
and testing of input data. Fig. 8 illustrates this
memory packing system. Each table begins with ~wo
symbols that are shown shaded in the figure. The
first symbol identifies the table and defines its type.
The second symbol indicates the length of the table.
The next table begins in the first unused memory
location after the preceding table. Thus, for each
table there is information which can be used to locfl.te
the next table. By allocating storage as the input
data are read into the machine, considerable flexibility in the type of problem acceptable to the program is achieved. There are no pre-assigned limits
on the maximum number of such quantities as nodes
146
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
or physical parameters. Only the total amount of
storage available for data limits the size and type of
problem that can be handled by the program. An
additional advantage to flexible input storage assignment is that the program can be run on a 704 with
any memory capacity. In one program this idea was
extended further by allowing tables of a particular
type to have one of several different formats of varying length. In this case, the next table could begin at
anyone of several alternate locations. To determine
the location of the next table, the symbols are defined
in such a manner that the binary representation of
these symbols are distinct from ordinary floatingpoint numbers. Thus, the table following a given
table is found by searching each of several alternate
locations for a word not in normal floating-point
format, that is, for the symbol defining the new table.
MEMORY PACKING SYSTEM FOR FUNCTION TABLES
Beef
A
3
8
4
I-
Isccl
I8CC~.
e
CH
1IIIIIIil l lili
6
• ;5
2
Fig. 8-Illustration of memory packing system. The shaded areas
indicate symboh> defining the type and length of a table. Each
table begins immediately after the preceding table.
Another extension of the transient heat transfer
program is to assign an order to the operation on
cells. At present, the heat balance equations are
assembled and solved in an arbitrary order. Certain
applications of the program to large classes of less
general problems suggest that methods be incorporated for computing quantities required as input
to the present program. A body with two horizontal
fluid passages is illustrated in Fig. 9. In some cases
it is desirable to make calculations in the order indicated by the arrows, regardless of the order of the
data within the computer. For example, the computation of weight flow and fluid film coefficients from
given inlet and outlet pressure for one-dimensional
fluid channels could be programmed. If the computer
were programmed to operate on the cells in each
channel in the direction of flow, calculation of such,
quantities as fluid film coefficient could be incorporated easily. A straight-forward method for constructing an order of operation on node information
is to recognize the desired order from the symbols
describing the problem and to store with information
END
Fig. 9-Illustration of assigning an order to program operatioh on
cells to accommodate specialized calculations or to increase the
rate of convergence.
for one cell the address of the location of the next cell
to be treated. In certain applications of the program
. . an order to the operation on cells can facil-'
aSSIgnIng
itate the solution of the system of equations. If an
order of rows of the matrix is known to yield faster
solution, this order can be used in applying the
Gauss-Seidel method. Moreover, ordering program
operation on cells provides a simple means for utilizing the symmetry of manyt'elements of the matrix.
The conduction-convection terms between two connected cells are symmetrical, and considerable computing time is saved if these terms are computed once
for each time step. One means for utilizing the
symmetry of coefficients is to order the assembly of
elements by increasing or decreasing machine address.
In conclusion, several interesting methods and
computational techniques are incorporated in the
transient heat transfer program to allow its application to a wide range of problems. The program has
been used to analyze large problems incorporating
unusual shapes and several combined modes of heat
transfer. The machine time and consequent cost
required for the solution of most problems is very
reasonable. For example, typical problems with 150
nodes and 100 transient time steps are run in about
ten minutes of 704 computer time. It is economical
to use the heat transfer program to solve extensive
problems and to obtain solutions that are considerably more adequate than those resulting from other
methods. Consequently, extensions and further application of the ideas used in the present program are
planned for the solution of other engineering problems.
DISCUSSION
J. Ricketts (AC Spark Plug): Where can detailed information concerning the heat transfer program be requested?
Mr. Campbell: Information can be obtained by writing to me. However, I am afraid that you cannot obtain the program, because a
large part of the information is company priority. I would be glad to
discuss this with you or tell you as much as I can, but unfortunately
the usual restrictions are hampering this exchange of ideas.
By ~he way, let me introduce Mrs. Vollenweider who is an expert
on a dIfferent part of the programs and is here to answer the questions
that I can't.
Campbell and Vollenweider: Techniques in Heat Transfer Programs
147
Mr. Ricketts: How long would a large problem take?
SHARE?
Mrs. Vollenweider: Large problems have been worked in ~pproxi
mately three minutes of computing time. One of the assets of the
program is its short running time.
Mrs. Vollenweider: Information on the solution methods we used is
available. However, the actual program is not available except to
other GE installations.
L. Hellerman (IBM): Breaking a solid into cells suggests G. Kron's
"tearing". Could you copnnent on this?
F. EngeJ (Westinghouse): What assumptions are made in arriving
at the difference approximations for the conduction terms considering the irregular geometry permitted?
Mr. Campbell: Neither of us know enough about this.
Mr. Hellerman: Has there been any thought of 'using your method
of geometric specification in the control of. machine tools?
Mrs. Vollenweider: Yes, and we are investigating this now.
JI..
T. Middleton (IBM): Will this program be available through
Mr. Campbell: The assumptions that are made in this case are, of
course, the assumptions one usually makes for a finite different mesh.
I believe it is clear that if you divide an object into cells in the same
manner that a flux plot would break such an object into cells you
have a better chance of getting reasonable answers. Our method does
allow you to do this if you are so inclined.
148
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
The Automatic Transcription of Machine Shorthand*
GERARD SALTONt
INTRODUCTION
HE RECOGNITION of digitalized speech signals
is an important data processing problem, still completely unsolved. In fact, speech is the basic input
to many data processing problems, and before any
processing can take place, the speech signals must first
be transformed into digital form, recognized, and
identified. Typical applications include: tlie processing of court testimony, the recording of data in medical practice, the handling of business correspondence,
and the monitoring of radio broadcasts.
In spite of the fact that considerable research has
been conducted within the past few years,i,2,3,4,5,6
the problems which arise in the recognition of speech
are not, as yet, close to solution. For this reason, it
must be expected that speech cannot in the near future be made available automatically as an input for
data processing purposes.
Since stenographers are trained to record spoken
information at high speed, it may be possible to solve
a substantial part of the problem of transforming
spoken jnformation into written form by using a stenographic transcript as machine input. Indeed, stenographic notes are written in standard form and rules
exist for transforming the phonemic stenograms into
the standard written language. Machine shorthand is
the most useful form of input in this connection, since
the problem of recognizing handwritten characters is
eliminated. Moreover, in machine shorthand, the
notes are furnished on a paper tape which may serve
as a direct input to a computer handling the translation process. A study of methods for transcribing machine shorthand is thus of interest from a practical
point of view to speed up the production of written
output, and also because it provides opportunities for
the analysis of both the written and the spoken
language.
T
THE STENOTYPE MACHINE
Most machine shorthand methods presently in use
are based on a machine developed by a shorthand reporter, W. S. Ireland/ in the beginning of this century. The machines resemble miniature typewriters
and are marketed under such names as "Stenotype" or
"Stenograph .. ,
The keyboard developed by Ireland comprises 22
keys and a numeral bar. As each key is depressed, a
character corresponding to that key is printed on a
* This study was supported in part by the National Science
Foundation.
t Computation Laboratory, Harvard University.
paper tape and a clutch driven roller advances the
tape. The various keys can be depressed either singly
or together; if depressed together, the corresponding
characters all print on the same line of the tape. During actual operation an average of five to six characters are thus written across the width of the tape in a
single stroke. Unlike an ordinary typewriter, the stenotype machine does not have a movable carriage;
therefore, the characters always print in the same
relative position on the tape when the corresponding
keys are depressed on the keyboard. The paper tape
folds into a pull-out tray at the rear of the device. The
keys are unmarked and writing is done entirely by
touch as in ordinary typewriting. A sample stenotype
tape is shown in Fig. 1.
AO EU
RPB
E
S K W R 0 EU
K
PB
0
U
E
0
T P
R
JOINT
P L
P
K
EASTERN
T
T
} COMPUTI;R
R
PB
E
PB
}
S
CONFE~ENCE
AO EU
Fig. I-Sample stenotype tape.
I
NUMERAL BAR
GJ GJ IT] ~
~ ~ [;J [TI GJ GJ
8GGG GGGGGG
[;]0 (;JQ
Fig. 2(a)-Stenotype keyboard.
I
2
3
4
SPACE
6
8
9
STKPWHRAO*EUFRPBLGTSDS
Fig. 2(b)-Printing order.
The standard stenotype keyboard is shown in Fig.
2(a) and the fixed printing -order is shown in Fig.
2(b). If the numeral bar is not depressed, the lower
149
Salton: Automatic Transcription of Machine Shorthand
case character shown on each key is written; if the
numeral bar is depressed, a decimal digit will print in
some instances while the lower case character is
printed unchanged in others. Thus for 12 of the 22
character positions across the width of the tape, the
character appearing on the tape is unique, while for
the remaining ten positions two possible characters
can be printed in each position.
The 16 different letters of the alphabet which can
be printed by means of the 22 keys are arranged in
three groups: a set of seven consonants on the lefthand side of the keyboard, a set of four vowels and an
asterisk in the middle, and a set of ten consonants on
the right hand side of the keyboard. In order to keep
the keyboard small and the fingering simple, ten letters of the alphabet are not provided at all and must
therefore be represented by others letters or combinations of letters.
Words are formed in stenotyping by merely juxtaposing the transcriptions of the individual phonemes.
Thus,
"one" is written WOPB (WON),
"queer" is written KWER,
and
"tax" is written TABGS (TAKS).
The Elimination of Strokes
Since only one vowel cluster can be printed on any
given line, it is in general not possible to write more
than one syllable per stroke. Thus, the word "interviewed" is written
EUPB = TER = SRUD
(IN = TER = VUD)
in three strokes, the equality sign denoting the separation of strokes.
Furthermore, because of the fixed order of the letBASIC RULES OF STENOTYPY
ters on the keyboard, some words require more than
one stroke even though only one vowel cluster is
Before describing the problems which arise in the
present. Thus it is necessary to use two strokes for
transcription of stenotypy, the basic rules of machine
words such as
shortland will be briefly reviewed. 8,9 While there exist
many variations of the basic theory,lO,ll resulting
TH = WART (TH = WART),
partly from the preferences of individual reporters
PWRAPB = FP
(BRAN = CH),
and stenographers, and partly from the desire to cope
and
with specialized subject matter and to increase re(GOL = F).
TKPWOL = F
porting speed, all such variations are based on a common set of rules. It is this standard theory which is Theoretically, at least two strokes should thus be required on the average to render a given English word
described here.
on a stenotype tape. In practice, however, the number
Consonant and Vowel System
of stenotype strokes is only slightly larger on the
In machine shorthand, consonants are generally average than the number of English words.
written according to sound. Of the 24 consonant
The reduction from the expected number of strokes
phonemes which are recognized in most English dia- to the actual number of strokes is achieved by a set
lects,12 22 can occur initially in English words and 21 of rules designed to save strokes. Seven principal
can occur finally. Direct representations are assigned rules are used to eliminate strokes:
on the stenotype keyboard for seven initial and for
(1) Special keyboard letter combinations are asnine final consonant phonemes. Special letter combisigned to some phoneme clusters such as loki
nations are used to represent those phonemes which
and In JI which would normally require more
are not available directly on the keyboard. The charthan one stroke .
. acter combinations actually used are assigned for ease
(2) Certain high frequency consonant clusters.endof fingering, rather than for economy in the number of
ing in "t" cannot be written in one stroke bekeys which must be depressed.
cause of the arrangement of the letters on the
The vowel system is more complicated in that!
keyboard
or because the required fingering
vowels are written partly according to spelling and
would
be
too
uncomfortable. For this reason
partly according to sound. A single vowel occurring in
omitted
in words ending in Istl,
final
T
is
a word is generally written in accordance with the
Ikst/, and Ikt/.
English spelling. Thus the phoneme 18hl is reproduced as the letter E in HER and as the letter U in
(3) Completely silent letters are treated as reBURN. A vowel cluster is generally transcribed as a
dundant and are therefore not written.
single vowel if only one vowel in the cluster is promi(4) An "unimportant" or "unaccented" vowel ocnently sounded. Thus one writes BOT for "bought"
curring in the middle of a word may be omitted
or "boat," and BET for "beat" and "beet." Some
if a stroke is thereby saved. Vowels which are
vowel clusters do not follow the general rule: for exnot essential to the understanding of a word
ample, the cluster "00" as in "book" is transcribed
are therefore generally not written. Thus,
AO, and the phoneme I;)j I as in "noise" is trans"easily" is written ES = HREU (ES = LI),
cribed OEU.
150
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
"believe" is written PWHREF (BLEV),
and
"commit" is written KPHEUT (KMIT).
(5) Special letter combinations are assigned to
some high frequency affixes. In particular, special combinations are assigned to the prefix"ex"
and to the suffixes "ing," "ity," "ment," "sion"
and "tion," and "ction."
(6) Special abbreviations are used to represent
about 300 high frequency words. These abbreviated forms can be used separately or as
part of longer derived words. For example:
TA stands for "take,"
but
PHEUS = TA (MIS = TA) stands for "mistake."
Similarly,
TKEU (DI) stands for "difficulty,"
but
TKEUS (DIS) stands for "difficulties."
(7) Certain phrases consisting of more than one
high-frequency word may be written in one
stroke by juxtaposing the corresponding abbreviations. Thus in a single stroke one writes
phrases such as
THAUFB
SWELS
-3>
-3>
that you have been,
(THA U F
B)
as well as,
(S WEL S)
and
KWR UR
-3>
why you are
(KWR UR).
THE PROBLEMS OF STENOTYPE TRANSLATION
A number of problems must be considered if a stenotype input text is to produce usable English output.
First of all, it is necessary to find procedures for
mechanizing the input of stenotype texts. Second,
methods must be sought for dealing with the large
number of multiple English correspondents which arE'
generated in the translation process. Finally, it is desirable to restitute correct English word forms for the
mutilated forms which are derived. These problems
will be dealt with in order.
The Input Problem
The paper tape prepared by the stenographer
should clearly be used as a direct input medium during an automatic transcription process. Two main
procedures are available for this purpose. The first
one consists in modifying the stenotype machine in
such a way that holes are punched into the tape between adjacent lines of printed information. The tape
can then be treated in the same manner as ordinary
punched paper tape; at the same time, the printed
information can still be read as before. The second
possible procedure consists in using the characters
printed on the tape directly, by means of some character recognition process. This second method requires no equipment modifications in the recording
device itself.
For the twelve character positions which are associated with a unique character it is sufficient to detect
a hole immediately above the given character position on the tape. The presence of the hole will indicate
the presence of the given character on the line printed
immediately below. Alternatively, in the character
recognition procedure it is sufficient to discriminate
between the presence and absence of a character in
the given character position. If a character is present,
it will then necessarily be that character which is
uniquely assigned to the given position on tape.
Each of the remaining ten character positions may
contain either of two different characters. The character recognition process must therefore recognize two
possible characters in each of these tape positions.
This is a relatively simple system in comparison with
many other recognition systems now operating, and
no insurmountable technological difficulties should
arise.
If a punched paper tape system is used, it is sufficient to detect the presence of decimal digits across
the tape by using one extra hole position. If the extra
position is punched, the characters on the line immediately below will be recognized as decimal digits
in all positions where a possible conflict exists. If the
extra hole position is left unpunched, only alphabetics
will be recognized. The required decoding equipment
is again extremely simple.
The Decoding of Abbreviations, Phrases, and Affixes
The number of abbreviated forms in general use is
relatively small, of the order of several hundred. It is
therefore possible to construct a table or dictionary of
these forms and to obtain the English correspondents
by a table look-up operation. In principle, the
table look-up operation presents no difficulties. In
practice, however, certain ambiguities may have to be
resolved. Indeed, many abbreviations have a number
of different correspondents in English and it is not
always easy to discriminate between them. For example, TPOR is an abbreviation for both "inform"
and "information"; similarly, W stands for both
"were" and "with."
The difficulty is often compounded by the fact that
many clusters may be abbreviated forms in some contexts, but not in others. Thus, the previously cited
TPOR is transliterated "FOR" and may, therefore,
correspond also to "four" and "for." Similarly, UL is
Salton: Automatic Transcription of Machine Shorthand
the abbreviated form for "you will" since U stands for
"you" and L stands for "will"; however, in-some contexts it may be translated as merely "ul" as, for example, in TPEBG = UL = EU (effectually).
Phrases are strings of abbreviated forms which may
be written in one stroke. The dictionary of abbreviations can be used for the decoding of phrases, provided each phrase is properly partitioned before the
table look-up operation. Consider as an example the
phrase URBGT. If it is partitioned U /RB/G/T the
table look-up operation will produce the correspondents
U ~you
RB
G
T
~
~
shall
go, gone
~it,
the
151
which cannot be resolved merely by syntactic analyses. Specifically, it is not possible to use English
syntax to distinguish "sport" from "export," or
"annex" from "annection."
Syntactic difficulties are generally easier to resolve
than semantic problems. The former can to some extent be handled by building a dictionary or table including grammatical designations. Some sequences of
grammatical forms will then be recognized as legitimate in English, while others will not. Semantic
ambiguities, on the other hand, must be resolved by
considering the subject matter being analyzed. This,
in turn, might be attempted by generating and later
identifying certain topic phrases or topic sentences
by means of frequency analyses of the stenotype
texts. 13 •14 While frequency studies are helpful in
analyzing semantic content, it is doubtful whether
all semantic problems can be easily eliminated.
and the most reasonable translation would be "you
The Transliteration of Stenotype Clusters and the
shall go the"; if, on the other hand, it is partitioned
Determination of Word Boundaries
UR/BGT, the look-up operations produce
One of the required steps in the automatic tranUR ~ you are, your
scription of stenotype texts is the substitution of
English letters for the stenotype clusters. For most
GBT ~ account
clusters, this step is mechanical, since the clusters corand the correct translation "your account" is then respond in general to a unique character in English.
obtained.
For example, PWEFP will be uniquely transformed
While each phrase can generally be partitioned in into "BECH" since the transformations
many different ways, a preferred partitioning method
PW~B,
can normally be found by storing certain phrases or
parts of phrases in the dictionary, and by using the
E~E,
stored information during the translation process.
and
The number of affixes in general use is small. HowFP~CH
ever, the decoding of affixes can present considerable
problems. In particular, a letter cluster denoting an are uniquely determined.
A few clusters, however, cannot be identified
affix may generally also stand for a normal word enduniquely
without use of the context. Thus SHR coring, or it may represent an abbreviated form. Conresponds
either
to "s1" or to "shr" and both translasider, for example, the letter G, denoting the suffix
tions
are
admissible
in some cases. For example,
"ing." It may be variously translated as "g," "ing,"
SHRED
might
correspond
to "shred" or "sled."
"go" or "gone," or it may be a part of a longer letter
Ambiguous
clusters
of
this
type are fortunately
cluster requiring still another translation.
rather
rare.
Furthermore, a certain amount of conflict is inThe transliteration procedure does not restitute
herent in the assignment of letter clusters to the various suffixes. Thus, the suffix "tion" is represented by missing letters nor restore the correct English spell"GS"; since G also stands for the suffix "ing," the ing. A first approach to this problem might be provided by the use of frequency tables for both stenoending GS can also be decoded as "ings."
In general, it is possible to distinguish three types type and English digrams and higher order strings.
of ambiguity resulting from the decoding process. These tables could be used to translate a given stenoFirst, the generation of improper English word forms type letter cluster into the corresponding English
as, for example, the translation of OFRGS by "offer- letter cluster with the highest frequency count. In
tion" instead of "offerings." This problem will be most cases, the correct English correspondent would
considered in the next section. The second is the gen- then be furnished.
In some cases, of course, the frequency tables would
eration of phrases which are made up of morphologically correct word forms, but are nevertheless syntac- not avail, since the most probable correspondent is
tically improper. Such syntactically incorrect phrases not always the correct correspondent. This is the case
would result, for example, from the replacement of particularly for those words which require more than
"issue" by "I shall you," or of "a chief" by "achieve." one stroke to be rendered on the stenotype tape. For
The last is the generation of semantic ambiguities example, words like
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
152
P A = SHEPBS (PA = SHENS)
~
patience
or
TABLE I
COMPARISON OF TRANSLATION PROBLEMS
EUPB = TKUS = TREUL (IN = DUS = TRIL)
~ industrial
cannot properly be generated only by a frequency
analysis of the individual strokes. Moreover, there
are many stenotype strokes which may legitimately
have more than one correspondent in English and in
general, frequency tables cannot be used to make a
choice among these correspondents. Consider, for
example,
. for {hire
HEUR standIng
h'Igh er,
. for {a cut
A = CUT standIng
t
acu e,
and
PWAR standing for{
~:~r
bare.
Only the last two words are legitimate homonyms in
English. The other pairs are artificial homonyms
which are created in stenotyping because the language
is less redundant than English.
Thus while digram and trigram frequency tables
would ~rove helpful in the restoration of English
word forms, accurate tables for longer strings of characters would almost certainly be required to solve
the problem for a large number of strokes. Adictionary
of high-frequency multistroke words could also be
used to good advantage in the recognition of word
boundaries. However, since it is often possible to
split English words into stenotype strokes in several
different ways, all possible forms of these multistroke
words would have to be listed in the dictionary.
To summarize, the problems raised by the transcription of machine shorthand are identical to problems encountered in the automatic translation of
languages with two important exceptions. In machine
shorthand, it is not necessary to change the word
order of the input text, or to alter a sentence by insertion or deletion of words; idiomatic expressions do
not therefore cause any difficulties. On the other hand,
in language translation it is not necessary to generate
correct word forms by altering the spelling of words,
or to recognize word boundaries. A compafison of the
various translation problems is shown in Table 1.
THE PRODUCTION OF PSEUDO-ENGLISH
As a first step in the analysis of machine shorthand,
computer routines were prepared for the production
of pseudo-English, that is, comprehensible, although
syntactically and semantically ambiguous English. In
many applications, such as the monitoring of radio
broadcasts or the use of machine shorthand in medical
practice, pseudo-English might be an acceptable form
of final output; in other applications, imperfect
Translation
Problem
Automatic
Translation
Stenotype
Transcription
Automatic input
V
V
Dictionary look-up
V
V
Elimination of
syntactic ambiguities
V
V
Elimination of
semantic ambiguities
v
v
Generation of correct
word forms
-
Recognition of word
boundaries
-
*
V
V
Restitution of correct
word order
V
--
Insertion and deletion
of words
V
-
* Limited to generation of correctly inflected forms.
English would be undesirable. However, even then,
pseudo-English is a useful intermediate OU\put since
it can be used to update the dictionaries, to refine the
partitioning methods, and to derive rules for syntactic analyses. Since English is inherently redundant,
understandable output sentences can be produced
with comparatively little difficulty.
A variety of methods are used to produce pseudoEnglish. The stenotype strokes are first partitioned
into "constituent" pieces using only the structure of
each stroke as the criterion. Two short dictionaries
are used to look up the correspondents of these constituents and to handle the transliteration process.
The word pieces are later reassembled into complete
English words or_ phrases.
No attempt is made to reduce ambiguity by making
a choice among many possible English correspondents. Thus, if a given stenotype stroke can reasonably
correspond to many different English letter clusters
or words, all correspondents will be listed, and the
reader is required to choose the most reasonable correspondent using the given context as a guide.
Similarly, the correct English spelling of words not
found in the dictionaries is not always restored. Instead, the abbreviated word form, excluding silent
letters and unaccented vowels, is used in the transcribed text. This reduces the aesthetic quality of the
output although comprehension is not generally impaired.
Analysis of Stenotype Stroke Forms
Depending on the classification of a given stroke,
153
Salton: Automatic Transcription of Machine Shorthand
one of five basic translation methods must be used to
transform it into the English equivalent.
(1) To decode abbreviations the complete stenotype
stroke must be looked-up in a dictionary of abbreviations; one or more correct English word
forms will then be determined for each abbreviation. For example,
T
--?>
the, it.
(2) Phrases must first be partitioned into two or
more components, and each component must
then be looked-up separately in a dictionary.
The juxtaposed English correspondents will
then represent the English phrase. For example
TPHAB
--?>
it may be,
T
--?>
it
PHA
--?>
may
B
--?>
be.
sInce
An analysis of stenotype phrases indicates that
many phrases can be translated correctly if
partitioned between the middle vowel string
and the final consonant string. The above example would then be partitioned into the components TPHA and B, and the English correspondents "it may" and "be" would be found
in the dictionary of abbreviations and phrases.
sInce
KHR
--?>
cl
RBG
--?>
rk.
It should be noted that many stenotype
clusters appear both in the dictionary of letter
clusters and in the dictionary of abbreviations.
However, the English correspondents are then
necessarily quite different. As an example, it
was seen that T is an abbreviation for "it" and
"the"; in the dictionary of letter clusters, the
correspondents are "t" and "th."
(5) Ordinary stenotype strokes which include a
suffix but are not stenutype abbreviations are
treated like the strokes of category (4), except
that they are partitioned into four parts before
look-up in the dictionary of letter clusters:
initial consonant string, middle vowel string,
final consonant string excepting the suffix, and
suffix. As an example,
TKPWEUFG
--?>
giving,
sInce
TKPW
EU
F
G
--?>
--?>
g
i
--?>
V
--?>
ing,
,
G being again the suffix corresponding to "ing.'
Since it is not clear a priori how a given stroke is to
be classified, every stroke is submitted to the procedure required for all five categories; a correct translation will then necessarily be determined for each
stroke. The strokes are first classified as belonging to
one of ten types. The stroke type depends only on
the combination of letter clusters which form the
stroke. Specifically, the stroke type indicates whether
WREUG --?> write-ing,
the corresponding stroke terminates in one of the
sInce
recognized suffixes and shows which combination of
WREU --?> write
initial cO\lsonant, middle vowel, and final consonant
G --?> ing.
strings constitutes the stroke. For example, stroke
Here WREU is the abbreviation for "write" type 0 represents strokes made up of a vowel string
only, while stroke type 2 represents strokes made up
and G is the suffix.
of an initial consonant string followed by a vowel
(4) Stenotype strokes which are not abbreviations string. Depending on the type, each stroke is then
or phrases are rendered in English by trans- partitioned into constituent parts. Eight stroke parts
forming the stenotype letter clusters into cor- including the complete stroke are recognized as shown
responding English letters. The transliteration in Table II. The English correspondents of the variprocedure uses a dictionary of stenotype letter ous parts are then looked-up in the dictionary of abclusters including many of the consonantal and breviations and phrases, and in the dictionary of letter
vowel patterns used in English. In order to use clusters. A third dictionary or table is required to
the dictionary of letter clusters, it is necessary
handle suffixes.
to partition each stenotype stroke into initial
After the table look-up operations, the English corconsonant string, middle vowel string, and final respondents of the stroke parts must be reassembled
consonant string. For example,
to form complete words or phrases. For example, to
form complete phrases (category (2) above) stroke
KHRERBG --?> cl-e-rk,
(3) Derivatives of abbreviations are first partitioned
to isolate the affix. The correspondent of the
complete stroke excluding the affix is then determined by dictionary look-up and the
English correspondent of the affix is added.
For example,
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
154
TABLE II
STENOTYPE STROKE PARTS
Code
W
Stroke Part
Complete stroke
C
Initial consonant string and middle vowel string
FIF2
Final consonant string
I
Initial consonant string
v
Vowel string
s
Complete stroke excluding suffix
A
Suffix
E
Final consonant string excluding suffix
parts C and F 1 must be reassembled; similarly, for
ordinary transliterated words (category (4)) parts I,
V and F 2 are reassembled. This will be explained
further in the description of the machine program.
•
•
•
•
•
•
•
•
SERIAL
NUMBER
001-00052000' 0F/
STENOTYPE
STROKE
I
ENGLISH
CORRESPONDENTS
0AVE
001-00053000 HAVE BEEN
•
FD
001-0(,054000 HAVE. HAD
Ii
FP
001-00055000 !OUCH
FPeT
001-00051>000 HAVEN'l
Fe
FPL.T
/
P
•
•
MARKINGS FOR
ENG. CORR
............. "
001-00057000 •
•
•
•
J
Fig. 3-Excerpt from dictionary of abbreviations and phrases.
•
•
•
•
•
•
•
•
•
•
AEU
005-00001000 "I
•
AO
005-00002000 ou
10
AU
005-00003000 "U
1 At
2 AL.
8G
005-0000'1000
1 KT
2 BING
15
8GS
005-00005000 X
1 KTS
2 BINGS
3 CTION II CTIOUS •
~
•
•
•
•
•
•
005-00001>000
1 KTH
2 KlTY
BGT
3 KATE
The Machine Program
•
The Univac I computer at the Harvard ComputaFig. 4-Excerpt from dictionary of stenotype letter clusters.
tion Laboratory was used for the production of the
pseudo-English output. In order to reduce the. proThe various steps used to produce pseudo-English
gramming load, it was desirable to make use of exist- are shown schematically in Fig. 5. Each box correing machine programs. In particular, it was found that sponds to one machine run. Only the partition promany programs originally written to handle various
phases of Russian to English automatic translation
could be used for the transcription of machine shorthand *. Some of these programs required small alterations; however, compared with the work required to
write new programs, the effort expended in making
the required changes was negligible.
In order to construct the two dictionaries, use was
made of existing stenotype manuals. The present dictionary of abbreviations includes about 700 stenotype
strokes arranged in alphabetical order, and approximately 2000 English correspondents. Punctuation
marks are identified by the letter P following the
stenotype cluster, and English correspondents by the
digits 1, 2, 3, and so on; a percent (%) sign is used for
the last correspondent. An excerpt frOln the dictionary
of abbreviations is shown in Fig. 3.
The dictionary of letter clusters includes only
DEPENDING ON WORD TYPE
clusters whose English correspondents are different
AND DICTIONARY INFORMATION
from the stenotype original. To construct this dicPARTS S-A, C-F,
I-Y-E-A AND 1- Y-F
tionary, lists of consonantal and vowel patterns used
in English were consulted; 15 about 100 letter clusters
REDUCE HOMOGRAPHIC ENTRIES
arranged in alphabetical order are included. An ex- TO SINGLE 30-WORD ITEMS FOR
EACH TEXT WORD AND ELIMCORRESPONDENT
cerpt from the dictionary of letter clusters is shown INATE
DUPLICATE CORRESPONin Fig. 4.
DENTS
* Several programs written originally by members of the Harvard
~T
~
Automatic Translation Project under sponsorship of the National
Science Foundation were used; the writer is indebted to Prof. A. G
Oettinger and to the other project members for having made these
programs available.
Fig. 5-Program for the production of pseudo-English.
Salton: Automatic Transcription of Machine Shorthand
gram and the assembly program shown by double
lines were newly programmed. *
The stenotype text to be translated is first transferred onto magnetic tape. Since equipment for automatic input does not exist at present, the operation is
manual. The text is typed like ordinary linear text
with spaces between stenotype strokes. English comments are placed between dollar ($) signs to conform
with the requirements of the existing programs. I6 No
special punctuation marks are used in stenotyping
except for a double asterisk to indicate a new paragraph. Instead, punctuation marks are denoted by
special letter clusters which are included in the dictionary of abbreviations. An excerpt of a linear input
text is reproduced in Fig. 6.
S STENOTYPE TEXT FROM ADVA~ClD STENOTYPE READER 5TARTINb AT
SOPPORTUNITYs
TUPBT
5EPGS
AP~
TP[UPBD5 OPBL
TH0S
HOF
•
•
/H~PP * S~EU:~UB~ ~t1F~~~~P\ T::~B/R~;EI R~~p.~~L \E~E\u
•
:;L
Tt1ASG
FR
KOPL
TOU
HR
Tf'~EFR
SREPORTING HINTSS
TPOR
RORT
G
•
•
•
B
Tl
5
•
PRrl'
us
•
•
T
FPLT
TIU«BGS
5
•
WARu
TO
THPEO
G T
PA
PFR
APB
T I'A
PER
L
TPORPL
A
PA~
TPHT
TRA
RIIGS
S'1UD
S KAR
5t1UO B
TPHER
E
TPHUF
ToT
SPER'
TO
EUPB
SHU"HLRG
UL
APB
PltlPL
PAD
5aELS
PHS
TPt1FL5 FPL T
THS
TOS
RED
5
PHA
PUT
TPH
TOT
k<'RT
ERS
SAF
KEPG
TPOR
lPB
TREU
START
0
n
TPHAPL
"PbS
PHRAS RBGS
TI<.AT
APB
TlUPL
•
Fig. 6-Sample section of linear Stenotype text.
•
•
•
•
•
•
•
•
PIOBG5
TPHT
TAOL5
EU
APB
5TPHFPlT
F
U
HREUF
HOU
TKOU
EPB
TAOl5
AOEU
PIOBG5
\IE
T
F
RBGS
Kope
TEUF
\>AS-048JOOOO FPLT
GAS-048~COOO RT
GAS-04870000 5TPHFPL T
GAS-01I0000 FPl T
,,05-05010000 OFPb
GAS-05030000 SHARP
~TpH
bA5-0'05COOO
(,AS-05070000
uAS-0509COOO
"A5-05"OOOO
bAS-05DOOOO
GA 5-\15'50000
GAS-0",70000
bA5-0S190000
"A5-05210000
"AS-052JOOOO
GA 5-0 5250000
T
TPHUR
T Au~
AOEU
OE
TAOL5
THEUG
F
5TRU6G
PHApBlG
WAFP
b.605-05270000 TPHE.U
*
GA5-0118110000
GA5-011860000
GA5-011880000
GA5-011900000
GA5-011920000
GA 5-0119110000
GA5-011960000
GA5-011980000
GAS-05000000
GA5-05020000
GA5-0501l0000
GA5-05060000
GA5-05080000
GA5-05 100000
GAS-05120000
GA5-05'"0000
GA5-05'60000
GA5-05 180000
GAS-05200000
GAS-05220000
GA5-052110000
GA5-05260000
GA5-05280000
•
•
•
•
•
•
•
•
Fig. 7-Itemized Stenotype text.
The itemize program 16 is used first to assign serial
numbers to the individual text words. Each text word
is transformed into a separate 5-word item. A part
of a linear input text is shown in itemized form in
Fig. 7. The four low-order digit positions of each
serial number, filled with zeros, are later modified
during the partitioning process.
The partitioning program uses the itemized text as
input and generates a variable number of 5-word
items for each input item. Each input stroke is first
partitioned into initial consonant, middle vowel and
final consonant strings, and a code representing the
stroke type is assigned to the complete stroke. A test
is also made for the presence of one of the ten recognized suffixes. If a suffix is found the proper suffix
number is assigned. The various stroke parts are then
recorded on one of two output tapes (the final consonant string F is actually recorded on both tapes).
The dictionary of abbreviations and phrases will be
searched during the dictionary look-up routine for the
* The partition and assembly programs were coded by Mr. Rodney
W. Thorpe, whose valuable assistance is gratefully acknowledged.
155
English correspondents of the stroke parts of tape 1,
while the dictionary of letter clusters is used for the
stroke parts of tape 2. For complete strokes (initial
consonant - middle vowel- final consonant clusters) with affix, four stroke parts (W, C, F, S) are recorded on tape 1 and four stroke parts (I, V, F, E)
are recorded on tape 2. If the stroke is truncated
(e.g., if the initial or the final consonant string is
missing) or if no affix is present, a smaller number of
stroke parts will be recorded out. All stroke parts are
recorded with a modified serial number to show the
stroke type and the stroke part represented by each
individual item.
The two tapes are now processed separately
through the same sequence of programs. The items
are first prepared for the dictionary look-up by an
alphabetic sort. The dictionary look-up routine will
then expand each 5-word item into a 3D-word item
and add to each stenotype input stroke the English
correspondents from the dictionary. The dictionary
of abbreviations is used for the items of tape ~, while
the dictionary .of letter clusters is used for tape 2.
For strokes not found in the dictionary, a dummy
3D-word item is generated. The 3D-word items are
finally sorted back into text order, using the new serial
number as a sorting key. The alphabetic sort and the
dictionary look-up programs were taken over unchanged from the "Continuous Dictionary Run" used
for Russian-English translation. I6
The next program is a two-way merge program using
the serial number as a key and tapes 1 and 2 as inputs. One merging pass is sufficient to transfer
3D-word items onto a single output tape. The merge
program used is one of the existing Univac system
routines. 17
The assembly program is now used to assemble
those 3D-word items which do not correspond to a
complete text word. Both the stroke type and the
dictionary information obtained during dictionary
look-up are used during the assembly phase to generate complete English correspondents. The stroke
type indicates whether it is necessary to add a suffix
to the English correspondents found in the dictionary and shows how many items are to be assembled
to form complete English correspondents. For example, if the original stroke consisted of an initial
consonant and a middle vowel string, the English correspondents of two items must generally be assembled; if a final consonant string was also present,
three items are normally assembled.
Up to five different types of assemblies are made,
For abbreviations, the English correspondents of the
W item are taken intact; for phrases, the correspondents of the C and F 1 items are assembled; for derivatives of abbreviations, the affix A is attached to the
correspondents of the S item; for ordinary strokes,
the correspondents of the I, V, and F2 items are
attached; finally, for ordinary strokes which include
all
156
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
a suffix, an affix A is attached to the correspondents
of the assembled I, V, E items. These five types of
assemblies are, however, not made for all strokes; the
dictionary information obtained during the look-up
operation is used to decide whether a given item is
to be assembled or not.
Specifically, if the W item is contained in the dictionary, then the correspondents which would nOlimally be generated by assembling the C-F, S-A, and
I-V-E-A items are already contained in the W item,
so that no need arises to assemble these other items.
Similarly, if C and Flare not both in the dictionary,
the C-F 1 item is not assembled since this item could
not then be an English phrase. Finally, if S-A is to
represent an abbreviation followed by a suffix, the
S item must have been found in the dictionary; the
S-A item is then assembled only under these conditions. The I-V-F2 item (and I-V-E-A item if different
from I-V-F2) is always assembled, even if one or more
of I, V, and F are not found in the dictionary. In that
case the English letter cluster is assumed to be identical with the stenotype letter cluster which is therefore assembled as part of the English correspondent.
Each assembled stenotype stroke is recorded out on
tape as a separate 30-word item.
Many stenotype dictionary entries have more than
one English correspondent. In order to avoid too
much fragmentation, special provisions are made during the assembly to write such multiple correspondents in parentheses. The reader must then choose one
correspondent form each set of correspondents shown
in parentheses. Consider, for exampl~, the following
sets of English correspondents:
I item: TH,
V item: 0,
F2 item: S, Z, ST.
The English correspondent of the assembled I-V-F2
item would be printed out
THO (S, Z, ST),
and the reader would normally choose the first correspondent between the parentheses to form THOS
(those). A second output tape to be used for research
purposes actually contains all correspondents "multiplied out."
At the end of the assembly each text word is represented by up to four 30-word items each including
the stenotype original, the serial number assigned by
the itemize routine, and the English correspondents.
An output sample from the assembly routine is shown
in Fig. 8.
I t is now necessary to bring together all English
correspondents belonging to a given stenotype stroke.
This is done by reducing the assembled 30-word items
corresponding to a given stroke to a single 30-word
item including all distinct English correspondents.
•
•
•
•
r
r
•
•
{:
•
•
US
I HI5
GAS.OU.''''2.1 15
GAS.OUI"!>211
.. AS
IS. Z' STI •
6AS.OU150,86 USE
6"5.00150,86 U
cs.
G"5.00860261 HAD
I, ST!
I OOkL"R CSI •
G"S.OUI6!>261 D
•
•
•
•
•
•
•
•
Fig. 8-Assembled Stenotype items.
The homograph package which was originally written to reduce all duplicate stem entries in the Russian
dictionary to a single entry was adapted for this
purpose. IS As part of the "homograph" elimination,
duplicate English correspondents which may have
been generated during the assembly are condensed
so that only distinct correspondents appear on the
output tape.
The output edit program of the Continuous Dictionary Run is now used to edit the condensed output of the previous program. Each English correspondent is assigned a 24-character position (two
Univac words), and up to five English correspondents
of a given stenotype word are printed one underneath
the other, thus making it easy to choose one correspondent for each stenotype word. An edited output
text is read from left to right like ordinary English
text. Multiple correspondents appearing one underntath the other are scanned, and the best correspondent is chosen.
The output edit program produces two outputs:
the "interlinear translation" which includes the stenotype original with each set of English correspondents,
and the "word-by-word translation" which omits the
stenotype original. Excerpts of these two types of output are shown ih Figs. 9 and 10, respectively.
For research purposes another edited output is prepared. This output is processed in such a way that a
separate item is created for each English correspondent. A program originally prepared to aid in syntactic
analysis and to correct the Harvard Automatic Dictionary Russian file is used. I9 An excerpt showing the
listing of all English correspondents is shown in
Fig. 11.
The several programs described above can be
transformed into a single program by automatically
reading into memory at the end of each step the program for the next step and by insuring that servo
assignments are not conflicting. A flowchart for such
a continuous run is shown in Fig. 12. Each box refers
to one of the programs previously described. The
programs marked CDR are part of the Continuous
Dictionary Run, while the programs marked CST are
on a Community Sequence Tape used for linguistic
analysis. The broken line between the inverse sort
and the alphabetic sort denotes that this set of pro-
·
·••
•
•
Salton: Automatic Transcription of Machine Shorthand
------------
---.-.---.--,
:::~ :~p:~. itT".
,"FOR".'l..
FOU.
fliT'"
IlAYE-r-:. ~-50_
-------------...,,0 @
sttlN&. "ar ..&t----!;~ T"'. 1"'"
.'t..
DEf'-----
• ------ ------ ____ e. -_ .. _.
IT
•
•
•
•
•
•
•
--- .. --_.-- .. --.----
____ e.
______
-
US
-~:-.z-.-n-,--_~5~~~._D_---~ ;N"U~~'"''["YH,
H15
AS
OO .. LAP IS'
'Uty . . .aTI.,
157
TAPES ALSO
USED
ITEMIZE
6
FPOGRAM ON SERVO
.. _ M OR
"l!,::
COR
PARTiTiON
•
NEW
•
•
3,4,5
I
•
I
..
6
Fig. 9-Edited interlinear translation.
ALPHABETIC SORT
COR
I
I
I
I
REMOVE TAPE FROM
SERVO 7; REPLACE
WITH BLANK. REMOVE
8~ REPLACE WITH
DICTIONARY.
LOOK-UP
·COR
I
SECOND TIME: PLACE
FIRST SORT OUTPUT
I
I
•• --=k~~,~~\-T"-.-"'-n.-h-..-...... ,......
•
•
•
C8 oST'--~:.7
E - - - ..
AM. l'
•
•
•
•
tfAVE
- ____
•
•
•
•
•
~::~:~lC"----~~ .tL~--
.tar.
1
.H£.N TOU
'HE. L[tTE.'"
•
1,2,3,5,6
I
I
I NVERSE SORT
MOO COR
IIo~O
•
•
•
•
•
•
•
....
}
FINDS
CORRESP
NUMBER
*
*
~
CoN&.¥ }
O"EL
O"AL
"
THOS}
T"OZ
T"05T
."0
1
.. OF
HOV
PAID
,.,
IT
T
TH
ITY
ATE
HAVE}
\
"
•"
2
} ·
P~1S }
pRIZ
~RIST
1
""I
\
,
2
··
\
2
TOTAL
NO OF
CORRESP
I
\
I
\
2
2
,,
3
\
2
a
\
2
2
I
..
"..
,,
3
STENOTYPE
STROKE
SERIAL
NUMBER
At'"
J.Pi>
TPEU",OWS
uP ilL
UP,,&.
c. AS-O/l06050,
opeL
THOS
TH05
THOS
HOF
HOF
HOF
"AEUD
T
T
T
T
T
T
PilEUS
PREU5
PREUS
GAS_C(l065503
GAS-C/l0758'9
GAS_O/l080503
6 AS-O(l085503
GA5-0/>085503
GA5-d/l0956,.
6A5_01\09568.
GA5-0(l095688
6AS_~1'I006011
6AI_I"(' I 056011
GAS-OO t 056011
GA5-01\ \ t 566.
GAI_,,(\ 120291
GAI_eoI2029\
6A5-0(\125291
6A5_011125291
6A5_011125291
GAS_OO 125191
GAS-CO 135688
GAS_eli 13:>6'8
GAS-O/l1356'.
SAVE; PLACE SECOND
PARTITION OUTPUT
ON 8.
TWO-WAY MERGE
UNIVAC ROUTINE
-.,I
ASSEMBLY
NEW
I
I
I
I
4
HOMOGRAPH PACK
MOO CST
Fig. IQ-Edited word-by-word translation.
ENGLISH
CORRESPONDENTS
ON 4.
FIRST TIME: REMOVE
SORT OUTPUT AND
IL ___________ -'
I
I
I
I
I
REMOVE 2 AND
REPLACE WITH
BLANK.
I
OUTPUT EDIT
COR
I
I
I
I
•
•
•
•
•
•
•
Fig. ll-Excerpt from complete list of English correspondents.
grams is used twice with different inputs and different dictionary tapes. Similarly, the broken line between the assembly program and the last box' on the
chart indicates the path for the second output of the
assembly program.
FUTURE RESEARCH
A number of methods for the improvement of the
English output have already been proposed. These
include, in particular, the use of digram and trigram
frequency counts of both stenotyping and English to
correct the spelling of the output, the inclusion of
grammatical information in the dictionaries to remove syntactic ambiguities, and a frequency analysis
of stenotype texts to be used in analyzing semantic
content.
As a first step, however, the outputs produced by
the present program can be used directly to update
the dictionaries by reducing the number of possible
English correspondents for each stenotype word. A
large amount of the ambiguity now existing because
of the nlultiplicity of correspondents might thus be
I
I
3,7
@-J'-__
C_ON_H_A_OI_C_---'~J
~ -!
MOD CST ! ~
\.J ~
FINAL OUTPUTS
Fig. 12-Continuous computer run for the
production of pseudo-English .
eliminated relatively easily. The more difficult problems of determining word boundaries, and analyzing
syntactic and semantic content of the context of a
given word can then be tackled at a later time.
A human post-editor first takes the English translation as given on one of the two prints furnished by
the output edit routine. 2Q ,21 The post-edited output
can then be used for two purposes: to determine
which of the several English correspondents listed in
the dictionary for each stenotype word were actually
used in obtaining the correct translation, and to determine which of the assembled items were chosen as
correct correspondents.
The first type of information can be used to weed
out from the dictionaries (especially the dictionary of
letter clusters) those correspondents which are not
believed to contribute to a correct English correspondent. Many stenotype strokes will be found to
have invariably the same English correspondent, and
no purpose is served by burdening the dictionaries
with unnecessary information.
The second type of information can be used to refine the partitioning and assembly rules. It is believed, for example, that the I-V-E-A item, when produced, might replace the I-V-F item. At the present
time both items are obtained. If this should be confirmed by the post-editing operation a large number
of correspondents would be eliminated.
158
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
An automatic system for feeding back information
obtained from the post-editor might be used to improve the translated output and also to correct the
dictionary by deleting or adding information. 22
REFERENCES
[1] K. H., Davis, R. Biddulph, and S. Balashek, "Automatic
Recognition of Spoken Digits, " Journal of the Acoustical Society
of America, Vol. 24 (1952), pp. 637-42.
[2] J. W. Forgie and G. W. Hughes, "A Real-Time Speech Input
System for a Digital Computer," Journal of the Acoustical
Society of America, Vol. 30 (1958), p. 668.
[3] D. B. Fry and P. Denes, "On Presenting the Output of a
Mechanical Speech Recognizer," Journal of the Acoustical Society
of America, Vol. 29 (1957) ,pp. 364-67.
[4] G. W. Hughes and M. Halle, "On the Recognition of Speech by
Machine," Proceedings of the International Conference on Information Processing, Paris (June 1959), to be published.
[5] H. F. Olson and H. Belar, "A Phonetic Typewriter," Journal of
the Acoustical Society of America, Vol. 28 (1956), pp. 1072-81.
[6] J. Wiren and H. L. Stubbs, "Electronic Binary Selection System
for Phoneme Classification," Journal of the Acoustical Society of
America, Vol. 28 (1956), pp. 1082-91.
[7] W. S. Ireland, "Stenotype Reporter," 3d ed., The Stenotype
Company, Indianapolis (1914).
[8] La Salle Extension University, "The Theory of Stenotypy,"
Chicago (1949).
[9] Stenographic Machines Inc., "Keyboard and Theory for Machine
Shorthand," Chicago (1957).
[10] B. H. Horne, "Stenotype-Stenograph Reporting Course," rev. ed., New York (1952).
A Complete
[11] Standard Theory Committee,' "Recommended Standard Practices, Abbreviations and Phrases in Machine Shorthand,"
Associated Stenotypists of America, 3d ed., (1957).
[12] H. A. Gleason, An Introduction to Descriptive Linguistics, Henry
Holt and Co. (1955).
[13] P. B. Baxendale, "Machine-made Index for Technical Literature - An Experiment," IBM Journal of Research and Development, Vol. 2, No.4 (October 1958).
[14] H. P. Luhn, "The Automatic Creation of Literature Abstracts,"
IBM Journal of Research and Development, Vol. 2, No.2 (April
1958).
[15] W. J. Plath, "The Relative Frequency of English Consonantal
Patterns," A. B. Honors Thesis, Harvard University, (March
1957).
[21] I. G. Mattingly, "Logical Post-editing," Mathematical Linguistics and Automatic Translation, Report No. NSF-3, Harvard
Computation Laboratory (August 1959).
[22] R. E. Jones, Jr., "A Feedback System for the Harvard Automatic Dictionary," Mathematical Linguistics and Automatic
Translation, Report No. NSF-3, Harvard Computation Laboratory (August 1959)'
DISCUSSION
Mr. Galli (IBM): Has any work been done on the resolution of
ambiguities, arising from the lack of an "end of word" indication?
Dr. Salton: We have not done any such work. However, there exist
machine shorthand systems, in particular a system known as Brevitype, where a slightly different keyboard is used, and an indication
appears on the tape when strokes are connected together. If a system
such as Brevitype is used, the problem of recognizing word boundaries
would be eliminated. In stentoyping this is not the case, and I suggested on the last slide that we might be able to make frequency
analyses of stenotype clusters; I intended to mean that we would go
across stroke boundaries and thus pick up certain combinations of
letters which might be written in separate strokes on the stenotype
machine, but would belong to the same English word. We hope to do
some work along this line.
E. H. Cabaniss (GE): Why not replace the paper tape with magnetic
or punched paper tape?
Dr. Salton: I imagine that the gentleman wants to know whether we
could replace the ordinary paper tape produced by the stenotype
machine by punched paper tape. This can indeed be done. I have
suggested in the written version of this paper two possibilities for
solving the input problem. One of them requires no alteration at all
in the stenotype machine and uses a character recognition scheme.
The character recognition problem is very simple in this case because
we have generally only one letter for each position across the tape, so
that when a character is detected in a given position. it is generally a
unique character. The other possibility would require certain modifications of the machine; in particular information could be punched
between adjacent lines of printed information. In general, I would like
to avoid changes in the present equipment.
Mr. Dittberner (IBM): You mention that vocal speech recognition
does not appear to be feasible in the foreseeable future. Is this foreseeable future compatible with the rosy future promised in the kilomegacycle era? Do you really feel so pessimistic about even recognizing one individual's voice - such as the operations executive?
Dr. Salton: I can answer the second question. I think that the word
boundary problems that arise are so severe that we cannot solve this
very soon. If we could train a speaker to speak very slowly in disconnected pieces, in such a way that individual syllables are detected,
the problem would be much easier; in a practical case, speech appears
as one continuous flow, and the problem is very difficult. There are
authorities in the field of speech analysis who may be more qualified
to answer.
[16] P. E. Jones, Jr., "The Continuous Dictionary Run," Mathematical Linguistics and A utomatic Translation, Report NSF-2,
Harvard Computation Laboratory (March 1959).
H. Freeman (Sperry Gyroscope): Your presentation was concerned
primarily with ordinary English. What problems arise when very
specialized technical terms are involved, such 3S stenotype records of
scientific papers?
[17] Richard Petonke, "2- 3- 4-Way General Merge," Univac System
Routines, Vol. 4, Remington Rand Univac.
Dr. Salton: For special copy, reporters use special abbreviations. These
special abbreviations must be included in the dictionary.
[18] William Bossert, "The Problem of Homographs in the Automatic Dictionary," Papers presented at the Seminar in Mathematical Linguistics, Vol. 4, Harvard University (Spring 1958).
D. E. Bachman (IBM): What, if any, shorthand abbreviations do
you use for plural forms of words and the past tense of words?
Dr. Salton: The past tense of verbs is written by adding a "D" in a
second stroke. For plurals, we don't use any abbreviation, only an
"S" added at the end.
[19] Orrin Frink, "Programs for Correcting the Harvard Automatic
Dictionary and for Syntactic Study, (Conhadic, Checkhadic,
Texthadic, and Freqhadic)," Mathematical Linguistics and
A utomatic Translation, Report NSF-2, Harvard Computation
Laboratory (March 1959).
D. A. Bourne (IBM): How difficult is it to learn the use of the machine as compared to Pitman shorthand, for example?
[20] V. E. Giuliano, "A Formula Finder for the Automatic Synthesis
of Translation Algorithms, " Mathematical Linguistics and
Automatic Translation, Report No. NSF.;.2, Harvard Computation Laboratory (March 1959).
Dr. Salton: It is very simple. I got into this subject without knowing
the stenotype system, and I learned all the letter combinations in
practically no time. However, the difficult thing is to attain speed.
A great deal of training is required to attain speed, and some reporters
Salton: Automatic Transcription of Machine Shorthand
will undergo training for several yaars. Some reporters attain speeds
of some 200 words or 220 words a minute. This takes a long time
certainly.,
K. Enslein (Brooks Research): Could one attach a tag to the stenotype word indicating "its grammatical character?
Dr. Salton: We can do this in the dictionary, but I can't see how you
can ask the reporter to add a grammatical indication on the tape
directly. However, we could ask a reporter to indicate when strokes
are connected together to form a single word. This would require one
additional key on the keyboard and would slow down the reporter
somewhat, but still appears feasible.
S. Pollack (Rand): What is the purpose of the serial number?
Dr. Salton: Before the strokes are looked up in the dictionary, they
are sorted first into dictionary, that is alphabetical, order. Later on,
we need to sort back into text order, using the serial number as a key.
The serial numbers are assigned during itemization using Serial N umber 1 for the first stroke, then 2, 3, 4, 5 to subsequent strokes, and so
on.
I. Rotkin (Diamond Ordnance Labs.): In order to use syntax, you must
159
be able to recognize the end of a sentence. How do you do this?
Dr. Salton: Punctuation marks are provided on the keyboard. FPLT,
for example, represents a period; therefore, there is no difficulty.
E. H. Goldman: How many magnetic tape passes are required in the
processing before output is ready for human editing?
Dr. Salton: There are quite a few passes involved in the dictionary
look-up procedure. Logically there are only the five passes shown on
the slide. However, because of machine limitations a lot of juggling
may be needed.
L. B. Harris (GE): Why are we using a stenotypist rather than a tape
recorder to record this meeting?
Dr. Salton: The fact is that the stenotypist has a great facility in
inserting things, deleting things, in dealing with a situation where the
speaker stops, or where the speaker makes an error, and so on. For
this reason, the stenotype transcript is frequently more useful than a
tape recorded transcript. When you report a conference, the participants frequently are particular about what appears in the proceedings. The stenotypist can handle this. Therefore, a stenotypist is often
much more useful than a tape recorder.
160
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
Critical-Path Planning and Scheduling
JAMES E. KELLEY, JR.t
INTRODUCTION AND SUMMARY
J
MONG the major problems facing technical management today are those involving the coordination of many diverse activities toward a common
goal. In a large engineering project, for example,
almost all the engineering and craft skills are involved as well as the functions represented by research, development, design, procurement, construction, vendors, fabricators and the customer. Management must devise plans which will tell with as
much accuracy as possible how the efforts of the
people representing these functions should be directed toward. the project's completion. In order to
devise such plans and implement them, management
must be able to collect pertinent information to
accomplish the following tasks:
(1) To form a basis for prediction and planning
(2) To evaluate alternative plans for accomplishing the objective
(3) To check progress against current plans and
objectives, and
(4) To form a basis for obtaining the facts so that
decisions can be made and the job can be done.
Many present project planning systems possess
deficiencies resulting from techniques inadequate for
dealing with complex projects. Generally, the several groups concerned with the work do their own
detailed planning and scheduling - largely independent from one another. These separate efforts
lead to lack of coordination. Further, it is traditional
in project work that detailed schedules be developed
frbm gross estimates of total requirements and
achievements based on past experience. The main
reason for this oversimplification stems from the inability of unaided human beings to cope with sheer
complexity. In consequence, many undesirable effects
may arise. Some important aspects of a project,
which should be taken into account at the outset,
may be ignored or unrecognized. As a result, much
confusion may arise during the course of the project.
When this happens, the management of the project
is left to the coordinators and expediters. In such
circumstances, management loses much of the control of a project and is never quite sure whether its
objectives are being attained properly.
Reconizing the deficiencies in traditional proJect planning and scheduling procedures, the Intet Mauchly Associates, Inc., Ambler, Pa.
AND
MORGAN R. WALKERt
grated Engineering Control Group (I. E. C.) of E. I.
duPont de Nemours & Co. proceeded to explore possible alternatives. It was felt that a high degree of
coordination could be obtained if the planning and
scheduling information of all project functions are
combined into a single master plan - a plan that
integrates all efforts toward a common objective.
The plan should point directly to the difficult and
significant activities - the problems of achieving the
objective. For example, the plan should form the
basis of a system for management by exception. That
is, within the framework of the rules laid down, it
should indicate the exceptions. Under such a system,
management need act only when deviations from the
plan occur.
The generation of such a coordinated master plan
requires the consideration of much more detailed
information at one time than heretofore contemplated in project work. In turn, a new approach to
the whole problem of planning and scheduling large
projects is required. In late 1956, I. E. C. initiated
a survey of the prospects for applying electronic
computers as an aid to coping with the complexities
of managing engineering projects. The following were
the questions of most pressing interest: To what
extent can a computer-oriented system be used:
(1) To prepare a master schedule for a project?
(2) To revise schedules to meet changing conditions in the "most" economical way?
(3) To keep management and the operating departments advised of project progress and
changes?
During the course of this survey outside help was
solicited. As part of their customer service, Remington Rand UNIVAC assigned the first author to the
job of providing some assistance. At the time the
second author represented duPont in this effort. The
result of our alliance is the subject of this essay.
We made a critical analysis of the traditional approach to planning and a study of the nature of
engineering projects. It quickly became apparent that
if a new approach were to be successful, some technique had to be used to describe the interrelationships among the many tasks that compose a project.
Further, the technique would have to be very simple
and rigorous in application, if humans were to cope
with the complexity of a project.
One of the difficulties in the traditional approach
is that planning and scheduling are carried on simultaneously. At one session, the planner and scheduler
Kelly and Walker: Critical-Path Planning and- Scheduling
consider - or attempt to consider - hundreds of
details of technology, sequence, duration times, calendar deliveries and completions, and cost. With the
planning and scheduling functions broken down in a
step by step manner, fruitless mental juggling might
be avoided and full advantage taken of the available
information.
Accordingly, the first step in building a model of
a project planning and scheduling system was to
separate the functions of planning from scheduling.
We defined planning as the act of stating what activities must occur in a project and in what order
these activities must take place. Only technology
and sequence were considered. Scheduling followed
planning and is defined as the act of producing project timetables in consideration of the plan and costs.
The next step was to formulate an abstract model
of an engineering project. The basic elements of a
project are activities or jobs: determination of specs,
blueprint preparation, pouring foundations, erecting
steel, etc. These activities are represented graphically
in the form of an arrow diagram which permits the
user to study the technological relations among them.
Cost and execution times are associated with each
activity in the project. These factors are combined
with the technological relations to produce optimal
direct cost schedules possessing varying completion
dates. As a result, management comes into possession
of a spectrum of possible schedules, each having an
engineered sequence, a known elapsed time span, a
known cost function, and a calendar fit. In the case
of R&D projects, one obtains "most probable"
schedules. From these schedules, management may
select a schedule which maximizes return on investment or some other objective criterion.
The technique that has been developed for doing
this planning and scheduling is called the CriticalPath Method. This name was selected because of
the central position that critical activities in a project play in the method. The Critical-Path Method
is a general interest from several aspects:
(1) It may be usea to solve a class of "practical"
business problems
(2) It requires the use of modern mathematics
(3) Large-scale computing equipment is required
for its full implementation
(4) It has been programmed for three computersUNIVAC I, 1103A and 1105 with a Census
Bureau configuration
(5) It has been put into practice
In what follows we will attempt to amplify these
points. We will describe various aspects of the mathematical model first. The mathematics involved will
be treated rather superficially, a detailed development being reserved for a separate paper. The second part of this essay will cover the experience and
161
results obtained from the use of the Critical-Path
Method.
PART
I:
ANALYSIS OF A PROJECT
1. Project Structure
Fundamental to the Critical-Path Method is the
basic representation of a project. It is characteristic
of all projects that all work must be performed in
some well-defined order. For example, in construction work, forms must be built before concrete can
be poured; in R&D work and product planning,
specs must be determined before drawings can be
made; in advertising, artwork must be made before
layouts can be done, etc.
These relations of order can be shown graphically.
Each job in the project is represented by an arrow
which depicts (1) the existence of the job, and (2)
the direction of time-flows from the tail to the head
of the arrow). The arrows then are interconnected
to show graphically the sequence in which the jobs
in the project must be performed. The result is a
topological representation of a project. Fig. 1 typifies the graphical form of a project.
1 .' 7
Fig. 1-Typical project diagram.
Several things should be noted. It is tacitly assumed that each job in a project is defined so that
it is fully completed before any of its successors can
begin. This is always possible to do. The junctions
where arrows meet are called events. These are points
in time when certain jobs are completed and others
must begin. In particular there are two distinguished
events, origin and terminus, respectively, with the
property that origin precedes and terminus follows
every event in the project.
Associated with each event, as a label, is a nonnegative integer. It is always possible to label events
such that the event at the head of an arrow always
has a larger label than the event at the tail. We
assume that events are always labeled in this fashion.
For a project, P, of n + 1 events, origin is given the
label 0 and terminus is given the label n.
The event labels are used to designate jobs as
162
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
follows: if an arrow connects event i to event j, work which has given planners several benefits:
then the associated job is called job (i, j).
During the course of constructing a project dia- . (1) It provides a disciplined basis for planning a
project.
gram, it is necessary to take into account a number
of things pertaining to the definition of each job.
(2) It provides a clear picture of the scope of a
Depending upon such factors as the purpose for
project that can be easily read and understood.
making the project analysis, the nature of the proj(3) It provides a vehicle for evaluating alternative
ect, and how much information is available, any
strategies and objectives.
given job may be defined in precise or very broad
(4) It tends to prevent the omission of jobs that
terms. Thus, a job may consist of simply typing a
naturally belong to the project.
report, or it might encompass all the development
work leading up to the report plus the typing. Some(5) In showing the interconnections among the
one concerned with planning the development work
jobs it pinpoints the responsibilities of the
should be interested in including the typing as a job
various operating departments involved.
in the project while those concerned with integrating
(6) It is an aid to refining the design of a project.
many small development projects would probably
(7) It is an excellent vehicle for training project
consider each such proje~t as an individual job.
personnel.
Further, in order to prepare for the scheduling
aspects of project work, it is necessary to consider
the environment of each job. For example, on the 2. Calendar Limits on Activities
surface it may be entirely feasible to put 10 men on
Having a diagram of a project is only the first step
a certain job. However, there may only be enough in analyzing a project. Now the plan must be put on
working space for five men at a time. This condition a timetable to obtain a schedule.
must be included in the job's definition. Again, it
In order to schedule a project, it is necessary to
ITlay technically be possible to perform two jobs con- assign elapsed time durations to each job. Depending
currently. However, one job may place a safety on the nature of the project this data may be known
hazard on the other. In consequence, the first job deterministically or non-deterministically. Another
must be forced to follow the second.
way to say this is that the duration of each job is a
Finally, the initiation of some jobs may depend random variable taken from an approximately known
on the delivery of certain items - materials, plans, distribution. The duration of a job is deterministic
authorization of funds, etc. Delivery restraints are when the variance of the distribution is small. Otherconsidered jobs, and they must be included in the wise it is non-deterministic.
project diagram. A similar situation occurs when
certain jobs must be completed by a certain time.
The Deterministic Case
Completion conditions on certain jobs also may be
handled, but in a more complicated fashion, by
On the basis of estimated elapsed times, we may
introducing arrows in the project diagram.
compute
approximations to the earliest and latest
Project diagrams of large projects, although quite
start
and
completion times for each job in a project.
complicated, can be constructed in a rather simple
This
information
is important not only for putting a
fashion. A diagram is built up by sections. Within
the
calendar,
but also for establishing
schedule
on
each section the task is accomplished one arrow at a
rigorous
limits
to
guide
operating
personnel. In effect,
time by asking and answering the following questions
it
tells
those
responsible
for
a
job
when
to start worryfor each job:
ing about a slippage and to report this fact to those
(1) What immediately precedes this job?
responsible far the progress of the project. In turn,
(2) What immediately follows this job?
when this information is combined with a knowledge
of
the project's topological structure, higher manage(3) What can be concurrent with this job?
ment can determine when and how to revise the
By continually back-checking, the chance of making schedule and who will be affected by the change. This
omissions is small. The individual sections then are kind of information is not determined accurately by
connected to form the complete project diagram. In traditional methods. What this information provides
this way, project~ involving up to 1600 jobs have is the basis for a system of management by exception.
Let us ~,ssume that ~he project, P, of n + 1 events,
been handled with'. relative ease.
starts
at relative time o. Relative to this starting
From a scientific viewpoint, the idea of diagramtirne
each
event in the project has an earliest time
ming the technological relations among the jobs in a
occurance.
Denote the earliest time for event i by
project is almost trivial. Such diagrams are used in
many engineering and mathematical applications. t/O) and the duration of job (i,j) by Yij. We may then
However, diagramming is an innovation in project compute the values of t~(O) inductively as follows:
Kelly and Walker: Critical-Path Planning and Scheduling
(1)
to(O) = 0
{ t/O) = max [Yt} +t/O) Ii .
92
10
20
10
25
40
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0
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0
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10
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20
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75
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20
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35
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68
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21
56
13
0
50
65
50
50
0
0
50
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20
35
23
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0
32
35
10
70
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AGE GROUP: Under 20
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20 - 40
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Over t:>5
»notional stress re la ted to Sx
PHYSI CAL EXAM:
Tender epif(astnum
36
Hypere5thesu w • n X 10- 8 volts
(1)
cJ> = maximum number of flux lines in
the head
n = number of turns on head
w = frequency in radians per second
This assumes that the readback signal is essentially
sinusoidal. The parameter cJ> will be less than the flux
lines remaining in the recorded dipoles after magnetization since not all the lines can be made to link
the head. It will be proportioned to track width. It
will be dependent on Br and He for the magnetic
coating.
For a thin magnet which is very wide, it can be
shown that
H = Ho - (2t/rrL) (B-H)
(2)
where
H0
applied field
H = effective magnetizing field
t = plating thickness
L = length of the recorded dipole
B = magnetic induction
Fig. 4(b)-Actual B-H loop for heat treated electroless nickel-cobalt.
drawn of slope determined by tiL which intersects
the B-H loop at the point of residual induction.
Fig. 4b shows a similar B-H loop for a heat-treated,
nickel-cobalt alloy chemically deposited by the
Brenner process. The squareness is not as good as
that obtained by electroplating, but it is expected
that this could be improved.
The B-H loops were taken on actual plated 272
inch diameter by 472 inch long stain steel cylinders
before they were mounted on the drum assembly.
(See Fig. 5 for photograph of the B-H tester.)
=
A nickel-cobalt plating having a coercive force of
320 oersteds and a saturation induction of about
6000 gauss was selected. The ratio tiL can be varied
so that a demagnetizing H just intersects the corner
of the B-H loop for the material. Since L is fixed by
the recording density, t is selected so that the residual
induction is near the maximum induction, thus taking advantage of the squareness of the hysteresjs
loop of the nickel-cobalt alloy. A greater thickness
would provide no greater residual flux because of
demagnetization, but would require a greater recording magnetomotive force and would magnetize more
slowly due to eddy current effects. Thus both magnetic plating material and its thickness can be optimized for the drum memory.
Fig. 4a shows an actual B-H loop of a nickel-cobalt
plated film to show the effect of thickness on the
residual induction due to demagnetization. A line is
~
00008' THICK PLATING
DEMAGNETIZING INTERCEPT
FOR 350 RECORDED POLES
PER INCH
Fig. 4(a)-Actual B-H loop for electroplated nickel-cobalt.
Fig. 5-B-H loop tester.
The B-H loops were taken by magnetizing the
plating axially in a solenoid whereas recording takes
place around the periphery of the drum. There was
some doubt as to whether or not anisotropic effects
would invalidate this measurement, and so several
disks were plated and tested along various axes in
the B-H tester. Very little change in B-H characteristics was noted as the direction of magnetization was
changed. The disks were purposely ground so that
the effect of grinding marks would be observed if they
set up an easy direction of magnetization.
DESIGN OF SUITABLE READ-RECORD HEADS
The design goals called for 350 bits per inch re-
May, Miller, Howard, and Shifrin: High Speed, Small Size Memory Unit
cording density and at least 30 tracks per inch.
Reading resolution of 350 Manchester cells per inch
requires coupling as much flux as is possible from a
0.0014-inch-long magnetic dipole into a magnetic
structure around which are wound a number of turns
of wire. Coupling much of the flux requires a head
gap of the order of 0.0004 inch and head to recording
surface spacing smaller than 0.0001 inch. However, a
compromise can be made which will cause a loss of
signal but not necessarily loss of operational margins.
Recording densities of more than 1000 bits per inch
have been obtained in systems using a single floating
head assembly. However, this usually is accomplished
wi th very closely spaced heads and wider tracks than
0.025 inch. In the interest of economy and development time a compromise which utilized many heads
mounted in a single air-floated pad was adopted. To
make the construction problem easier, a head-todrum spacing of 200-300 micro inches was adopted.
This limits a practical digital recording system to the
region of 500 recorded bits to the inch. In the present
system a recording density of 350 bits per inch is
used, but this does not represent the practical system limit. The floating pads holding about 27 heads
are of the order of 1.3 inches by 1.25 inches. Economies in space and cost are achieved by this mass
mounting method which at present requires the use
of recording densities of 500 bits per inch and less.
The problems of recording and reading will be discussed separately although it is highly desirable that
a compromise head be used which can both record
and read. Apart from economy it greatly relaxes
mechanical tolerance problems.
Fig. 6-Ideal geometry for recording 350 bits/inch.
Recording
Fig. 6 shows an idealized read-record head at its
pole face. If the resistivity of the pole pieces were
high so that eddy currents could be neglected, the
amp turns required for recording and the read signal
obtained per turn of the head winding could be quite
closely calculated. Such a head is most difficult to
make and the desirable spacing to the recording surface of 50 microinches or less is also most difficult to
obtain in multiple head assemblies. The performance
of the idealized head is of interest, however, for comparison with the compromise design which has been
presently adopted but which clearly could be improved. To determine the recording amp turns re-
193
quired, let the B-H loop (Fig. 4b) be assumed to be
the B-H loop for the recording surface. For the
0.00015-inch thick plating whose B-H loop is shown
on Fig. 4b assuming
L = 0.0014" (350 bits per inch Manchester recording)
It can be seen from Fig. 4b that 500 oersteds are required to saturate the magnetic plating at 6000 gauss.
From Equation (2) we find that
Ho
=
900 oersteds approximately for 500 oersteds
effective magnetizing force
Two parallel lines are shown on Fig. 4b, whose intersections with the B-H curve and H axis give the
residual flux density and the recording force required.
This gives a flux density after magnetization of 3200
gauss. If the curve of Fig. 4a were used, magnetizing
force of 600 oersteds would give a remnant density
of 5500 gauss. However, because the electroplated
coating is thinner (80 microinches versus 150 microinches), the remnant flux would be only 90 percent
of that obtained for the electroless plating.
The overriding consideration for selecting the electroless plating was its hardness and resistance to wear.
The remnant flux for a recorded dipole 0.0014 inch
long, 0.025 inch wide and 0.00015 inch thick would
be abo,ut 7.7 X 10- 2 lines for a flux density of 3,200
gauss.
About 2.5-amp turns must be provided for magnetizing the plating. In the ideal head (Fig. 6)
14.5 X 10-2 lines must be maintained across two gaps
in series to saturate the coating at 6,000 gauss. The
gap dimensions are 50 microinches in extent, 0.025
inch long and 0.0005 inch wide. This infers an average flux density in the air gap of 1,800 gauss, the
maintenance of which will take about 0.36-amp turns.
The maintenance of flux in a very small continuous
permalloy or ferrite circuit will take a negligible extra
number of amp turns.
In practice, sufficient amp turns must be provided
to generate a large number of fringing lines which
form closed circuits around the side of the l1ead and
under and over the recording surface. If the ideal..-'
head as drawn in Fig. 6 were made, 3-4 amp turns
would be sufficient for recording on the magnetic
coating specified.
In practice, allowance has been made for the fact
that the air gap may be 300 microinches instead of
50 microinches since this is much more readily
achieved in a multiple assembly holding 27 heads.
The best compromise for recording also includes making the silver shim gap larger than would appear idenl
for small head-to-drum spacings since the flux density
drops off rapidly in terms of the head gap dimension.
A practical though, not very efficient head would utilize 0.001 inch wide pole pieces with a 0.001 inch
wide silver shim. (See Fig. 7.) Such a head records
with 15-amp turns but gives a slightly greater read
194
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
0001"
SILVER
SHIM
00003" HEAD DRUM
SPACING
=~~~~=
RECORDED" MANCHESTER"
BITS AT 350 PER INCH
o 00015" MAGNETIC
COATING
Fig. 7-Practical geometry for recording.
signal using 30-amp turns. Since these figures are
large compared with the calculated 3-amp turns, it
is clear that recording efficiency was sacrificed in
order to make the head easier to fabricate and less
sensitive to spacing than the ideal head. This inefficiency becomes important only if the recording circUItry becomes large or impractical. A head made to
the dimensions shown on Fig. 7 has been driven at
546 kc with a silicon transistor circuit using 6 volts
on the collectors and 100 to 200 ma peak current.
Since this circuit is quite acceptable for a microminiature computer, recording efficiency can be sacrificed if this results in a net savings in manufacturing
cost. The practical geometry of Fig. 7 clearly looks
inefficient magnetically, but economy and ease of
manufacture are in its favor. The 0.01 inch long legs
are highly desirable for mechanical structure since
a clamp holds the permalloy against the silver shim.
The silver shim is wide for the size of the recorded
dipole, but head spacing is far less critical than if the
silver shim were closer to a more reasonable appearing dimension. Laminating the legs of the magnetic
structure will improve the performance since penetration of the magnetic field at 546 kc is about 10 percent into either side of the material (assuming nonsaturation) for the half amplitude point. In practice,
excess drive is used which causes the penetration to
be greater than the 10 percent mentioned above. The
penetration is greater because the permeability of the
material is lowered as it becomes saturated, resulting
in an increased speed of propagation in the saturated
region. The final choice of magnetic head is likely to
be a compromise between the schemes shown in Figs.
6 and 7. For practical reasons, the dimensions shown
in Fig. 7 make a good starting point for the development of a useful system.
The magnetic head structure is made of O.OOl-inch
permalloy rather than ferrite which would be too
hard to handle in sufficiently small sizes. Under less
than ideal conditions for recording, there are very
marked transients where recording starts and stops,
since some recording on a minor hysteresis loop takes
place under the full region of the magnetic head. As
recording density is increased without scaling down
the head gap and head-to-recording surface spacing,
this problem becomes more marked. For a chosen
minimum head-to-drum spacing, the useful recording
density can be greatly increased if the magnetic structure of the recording head is reduced to the smallest
dimensions possible so that its influence does not
appreciably extend beyond the recorded dipole. Care
must be taken in using legs of small cross sectional
area because there is not a large excess of flux over
the amount required to saturate the coating. Flux
leakage may prevent recording altogether unless the
over-all head structure is kept very small.
Design of Read Head
It was shown earlier that a 150-microinch thick
recording surface with the B-H loop characteristic of
Fig. 4b would have 7.7 X 10- 2 flux lines at the center
of a 0.025 inch wide recorded dipole. An ideal head
would intercept these lines (and even increase the
available flux by reducing the demagnetization). If
the flux change were sinusoidal (any other wave form
would give greater peak-to-peak volts) the read
signal would be
E = cf>w cos wt X 10- 8
where cf> is the total flux in the recorded magnetic
dipole and E = 2cf>w X 10- 8 peak-to-peak volts per
turnof the reading head. At 546 kc, which is the maximum frequency used, a signal approaching 5.2 mv
per turn could be expected from an idealized structure. With this ideal structure, it would be easy to
determine that resolving signals at a much higher
density would be possible and thus it would most
likely be used at a density where it would give much
less than the theoretical maximum signal. The magnetic head tested with the memory system described
falls far short in obtaining the maximum obtainable
signal at maximum density. In fact the presently
used heads develop a signal in the range of 12 mv
peak-to-peak at 546 kc as against a possible 780 mv
calculated for a 150-turn head. Reference to Fig. 7
indicates that unlike the situation in Fig. 6 where
more than half the flux would couple the head windings, only a small part of the flux will be useful in
generating a read signal. Calculation of the exact
magnetic flux coupling in this situation is most difficult, but a glance at a scale drawing makes the finding of 1/66 of the possible signal quite plausible. The
fact that the low output is tolerated is a compromise
between signal level, and economy and ease of manufacturing the heads. Since an excellent signal-to-noise
ratio and margins in clock pulse timing are obtained
in this situation, the compromise is quite tolerable.
At 273 kc, which represents the pattern 0 1 Olin
Manchester recording, the read signal obtained is
about 30 millivolts in comparison with a possible 390
millivolts if all the flux in the recorded poles interlinked the head winding. The loss of signal by a 13
to 1 ratio is explained by the presence of an air gap,
which provides a substantial reluctance in series with
the head structure, and also by the fact that the head
May, Miller, Howard, and Shifrin: High Speed, Small Size Memory Unit
195
35r---------------------------------------~
30
",25
~
o
>I
j20
i
Fig. lo-Partly assembled magnetic heads.
MECHANICAL DESIGN DETAILS
I
DENSITIES USED
---1
0~--------~7-~~~~~~~~~~------~
150
200
250
300
350 400 450500
BITS PER INCH MANCHESTER RECORDING
Fig. 8-Typical response for magnetic read-record head.
structure itself daes nat have a zero. reluctance. Fig. 8
shaws the respanse af the read head versus recarding
density and indicates that the head shawn in Fig. 7 is
being used beyand its aptimum density.
Fig. 3 shaws signals read by the head with clack
times indicated. As can be seen, the signals can be
interpreted with adequate reliability since there is no.
naise ar mistiming in evidence.
There is, af caurse, much raam far impravement af
the magnetic head; hawever, each improvement increases the difficulty af making the head and the increased cast must be balanced against the ecanamic
benefits af the impravement.
Construction of the Magnetic Head
Fig. 9 shaws the essential detail af the magnetic
head. In assembling these heads the lawer part is insulated and slipped into. an aluminum tube. The tube
is campressed farming a subassembly which can be
tested. The subassembly heads are clamped into. a
halder (Fig. 10) and fixed in place with a suitable
high temperature epaxy resin campaund. Twa such
assemblies are made with the heads staggered so. that
with the assemblies maunted 15 to. the inch a track
density af 30 per inch is achieved. The assemblies
are then maunted in the shaes.
150 TURNS
44 GAGE WIRE
Principle of Operation of Head Support Mechanism
A ratating drum maves a cansiderable valume af
air in its clase vicinity even thaugh the drum surface
is quite smaath by narmal standards. This phenamenan is due to. a baundary layer effect. That is, air
malecules which are immediately in cantact with the
drum tend to. adhere to. that surface. Due to. the
viscasity af the air, the air malecules immediately
abaut this initial layer are dragged alang and as the
distance ~ram the drum surface increases, the velacity
af the aIr malecules which are dragged alang decreases. With this cancept in mind, it is seen that if
a statianary surface which is curved to. match that
af the drum is held near the rotating drum surface
the air will be dragged between the twa surfaces:
Since the air will also. tend to. adhere to. the secand
surface, there will be a drag ar frictian farce as shawn
in Fig. 11. If this statianary surface is inclined to. the
drum surface so. that the space decreases in the directian af ratatian, the air which is dragged in is squeezed
into. a pragressively smaller space as is shawn schematically in Fig. 12. This squeezing effect is af caurse
a campressian pracess, and pressure farces narnlal to.
the twa surfaces develap. If this sec and surface is
held in place by a spring farce af praper magnitude it
will be held aff the drum to. a distance where the fl~id
Fig. 11- SchematIc view of drum with shoe in parallel position.
.001 SILVER
INSULATION
.001 PERMALLOY
TUBE CLAMP
Fig. 9-Essential details of the magnetic head.
Fig. 12-Schematic view OF drum with shoe at angle
to develop wedge of lubricant.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
196
pressure force equals the spring load force. When such
a condition exists, the layer of fluid which separates
the two surfaces is referred to as a hydrodynamic
lubricating film and such surfaces which react in this
manner are referred to as a self-acting bearing. In
the example given, air is used as the lubricating fluid;
however, any fluid, liquid, or gas which will adhere
to the bearing surfaces without causing damage will
perform in this manner.
The theoretical aspects of this phenomenon were
first proposed by O. Reynolds about 75 years ago,
and solutions of his equation for the incompressible
lubricating films have been well accepted in the literature on bearing lubrication. In recent years considerable attention has been directed toward the case of
the compressible or gas lubricating film for many
promising advantages such as chemical stability, extremely low friction, the maintenance of close clearance between moving parts, and the use of the ambient gas as a lubricant. The technology of the analysis of the bearing using a compressible fluid as a
lubricant as in the example (Fig. 12) is quite involved
and beyond the scope or purpose of this paper. Work
on this phase for use in the design of such bearings
for use in memory drums is in progress; and for the
technology the reader's attention is directed to the
list of references.
Propetties of Lubricating Film Supported Shoe
The lubricating film supported shoe possesses certain unique properties which make it a useful device
for the support of a recording head. The most important properties will be described below. For the purpose here, let us denote the angle between the drum
and shoe surfaces as the attack angle a, the edge
farthest from the drum surface as leading edge, and
the edge nearest the drum as the trailing edge. Drum
rotation is in the direction from the leading edge
towards the trailing edge.
The gas lubricating film is not only unique for its
thinness but also its high spring rate.
22
~20
;; 18 f------1r-
CONDITIONS. DRUM SURFACE SPEED -120 FT/SEC.
LUBRICANT - SEA LEVEL AIR
N
z
;;;
16~--t-
~ 14~--+
!
;:)
~
121----+10
~ 81----+------'~
4
1---------11-------1---3,,.
Fig. 13-Mean pressure
VS.
trailing edge to drum space.
Fig. 13 shows the typical relationship of the pressure force which can be developed under typical oper-
ating conditions. It will be noted that at the operating
conditions shown in the figure, a mean pressure of
1.5 psi gage at a trailing edge spacing of 400 microinches is obtained. As the trailing edge spacing is decreased, the mean pressure increases at a rapid rate
so that at a spacing of 200 microinches the mean
pressure has increased virtually four fold or inversely
with the square of the spacing. This characteristic is
most desirable from electrical and mechanical points
of view for recording drum applications. For any
fixed design as the load is increased the shoe and
hence recording head to drum spacing is decreased.
This is, of course, helpful to the electrical performance
as far as output signal is concerned. As a greater load
is applied to the shoe, the ratio of the applied load
to the weight or inertia of the shoe and its associated
mechanism is increased. When this ratio is increased,
the ability of the shoe to withstand accelerations and
run-out-irregularities of the drum is also increased.
In the case of the drum which is the subject of this
paper, the effective area of the shoe is 1.6 square
inches and its normal op~rating load is 10 pounds,
which gives a mean pressure of about 6 psi. The shoe
with recording heads in place has an effective weight
of about 1.5 ounces, and so the load-to-weight ratio
is slightly over 100. Since at this operating condition,
slight changes in the spacing result in a considerable
change in the lift force, there is available a large force
to restore the proper head to drum spacing. Let us
consider an example at the conditions cited above.
In a broad sense, since the curve shown in Fig. 13 is
one of a force vs displacement, the lubricating film
may be regarded as a spring of variable rate. If the
displacements are left small, the lubricating film may
be approximated by a linear spring and the slope of
the curve may be taken as the spring constant. For
the conditions cited above, this slope or linear spring
constant is about 100,000 pounds per inch for a show
of the given effective area. The spring rate of the
spring used to produce the load force would have to
be added to this ra te; however, since this spring
would have a rate of about 100 pounds per inch, it
is virtually insignificant in its effect on the natural
frequency of the system of forces acting on the show.
The spring rates of 100,000 pounds per inch acting on
the effective mass of the shoe give a resonant frequency of more than 3000 cycles per second. Thus it
follows that such a mechanism is quite capable of
withstanding accelerations of 10 g's up to 2000 cps
without seriously affecting the output electrical
signal.
Another unique property of the floating shoe is its
inherent stability. Fig. 14 shows a typical pressure
distribution between the trailing and leading edge of
the shoe. As the attack angle a is increased, the center
of pressure shifts towards the trailing edge, and similarly as the angle a is decreased the center of pressure
shifts to the leading edge. Let us fix a certain shoe
May, Miller, Howard, and Shifrin: High Speed, Small Size Memory Unit
POSITION
ON SHOE
Fig. I4-Typical pressure distribution
change in attack angle a.
VS.
geometry and allow the shoe to pivot about an axis at
the center of pressure and parallel to the drum surfaces. Now if the shoe is tipped so that the angle a
is increased, the center of pressure moves toward the
trailing edge. This action develops a turning moment
on the shoe. The turning moment is in the direction
required to return the shoe to the original position.
Similarly, when the shoe is tipped to an angle less
than the stable angle, a turning moment of opposite
sign develops to return the shoe to the original stable
position. From experience it has been found that the
system has sufficient damping to make it stable. Thus
it follows that the location of the pivot axis is not
critical, for the shoe will tend to seek a value of the
angle a so that the action line of the center of pressure will pass through the pivot axis.
Design Requirements
The design of a mechanism to make use of the
lubricating film supported shoe or for keeping a recording head in proper location with respect to the
drum recording surface requires careful attention to
the precision requirements of the mechanism. The development of a design framework which requires a
minimum of very precise parts which are amenable to
precision manufacturing techniques is necessary to the
successful execution of thetask. Itisnotonlynecessary
to have surfaces which are geometrically true, but it
is also required that the proper geometric relationship
between the various parts be accurately maintained.
The most important of these relationships is the alignment between the shoe and the drum. It is essential
that the center of curvature of the shoe be maintained
parallel to the axis of rotation of the drum. The limits
of accuracy required are dependent upon the particular design and the performance required. For the
design the out-of-parallelism is kept to les~ than 3
parts in 10,000. The other important requirement is
that the load on the shoe be uniformly distributed so
that tipping does not occur. As will be shown later,
the load on the shoe of the subject drum is applied at
two points. The difference between these forces is
kept to a value less than 7 percent. The tolerances
given above are those used in the design of the drum
197
with due allowance for possible manufacturing tolerance and also the expected deflections of the
mechanical parts.
Figs. 2, 15, and 16 show the drum in various stages
of assembly. It will be noted that the rotating portion
of the drum is set into a very rigid frame, and access
to the drum-recording surface is through appropriately located cutouts in this frame. A V-groove is
machined into the sides of this frame so that it is
accurately parallel to the axis of the drum. Guide
slots for radius arms are machined at precise right
angles to the V-groove. Each of the radius arms are
provided with polished sapphire pivot pins which are
cemented in place in an assembly fixture. The centerline distance between the pins is accurately maintained so that it is virtually the same for a given
pair of arms associated with a given shoe. One pin of
each arm operates in the V-groove of the frame,
while the other pin operates in a V-groove in the
shoe. The V-groove in the shoe is located in the line
of action of the center of pressure, and it is made accurately parallel to the axis of the cylindrical surface
of the shoe. To prevent smearing of the pole pieces of
the recording heads, the curvature of the shoe is
ground by means of a contoured abrasive wheel so
that the lay of the grinder marks is parallel to the
head gaps. Final finishing is done on a cylindrical
lapping tool which has a diameter 0.1 percent greater
than the drum. The load for the shoe is supplied by
the spring which is adjusted by a single centrally
located screw. By this means, equal forces are applied
to each side of the shoe. The load forces the pins to
seat in the V-grooves of the -shoe and frame and precisely locate the shoe with respect to the drum so that
the axis of the drum and shoe are parallel within the
extremely close limits previously cited.
Special consideration must be given to start and
stop conditions, for without sufficient drum speed the
lubricating wedge or film cannot develop and a high-
Fig. 15-Main frame.
198
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
friction condition will exist. To prevent this, it is
necessary to unload the shoe and lift it slightly off
the drum surface until sufficient speed for normal
operation is attained. For stopping the drum, the
procedure is reversed. There are basically two methods by which this may be accomplished. One method
involves removing the spring load until operating
speed is reached. The second method involves introducing lubricant under pressure through a very
small hole in the shoe into the space between the
shoe and drum. If sufficient lubricant (in the subject
drum it is air) is supplied, the shoe will be lifted off
the drum surface. After operating speed is reached,
this supply of air may be shut off and normal operation resumed. This latter method requires the use of
an air compressor, a fact which makes it somewhat
unattractive for airborne use. The first method is
used in this drum design. It will be noted that in
Fig. 16 the radius arms extend from the side of the
frame which has the V-groove to the opposite side.
Fig. 17-Typical pair of radius arms.
damage to the drum and shoe surface will occur. To
eliminate this possibility, one arm of each pair for a
given shoe is provided with a spring-loaded pin as
shown in Fig. 17. This pin is allowed to act upon the
side of a shoe to cause a small amount of friction
damping. Since the load at which the shoe is operated
is much higher than the weight of the shoe, this
damping friction does not affect the operation any
noticeable amount.
The main frame, as almost all other parts of the
drum assembly, is made of a precipitation-hardening
stainless steel. For the sake of rigidity and precision,
it is fabricated from one piece of stock and provided
with generous ribs.
REFERENCES
[lJ W. A. Gross. "A Gas Film Lubrication Study" Part I, "Some
Theoretical Analyses of Slider Bearings," I BM Journal of Research
and Development, vol. 3. No.3 (July 1959), pp. 237-255.
Fig. 16-Shoe and rad;us arms.
At this side of the frame, the ~nds of the arm can ride
on a simple eccentric cam which is operated by the
small gears. During normal operation, these ends of
the arms are free of the cam. For offspeed operation
the cam is rotated to a position where the ends of
the arms are lifted. Since the mechanism is extremely
rigid, a movement of less than one mil of the end of
the arm is sufficient to transfer the spring load from
the shoe to the cam. In this condition, the lubricating film between the drum and shoe must support
the weight of the shoe. Since the weight of the shoe is
very much less than the operating load, the resulting
friction is negligible. If the magnetic coating is very
durable, the slight contact between the shoe and
drum under these conditions is not serious and may
be eliminated completely by operating the drum with
the axis in a vertical position. When the shoe is in
this free condition, a state of instability may develop
if the cam is inadvertently set to lift the ends of the
arm too high. Should this condition develop, serious
[2J W. A. Michael. "A Gas Film Lubrication Study" Part II,
"Numerical Solution of the Reynolds Equation for Finite Slider
Bearings," IBM Journal of Research and Development, vol. 3, No.
3 (July 1959), pp. 256-259.
[3J R. K. Brunner, J. M. Harker, K. E. Haughton, and A. G. Osterlund. "A- Gas Film Lubrication Study" Part III, "Experimenta 1
Investigation of Pivoted Slider Bearings, ", IBM Journal of
Research and Development, vol. 3, No.3 (July 1959), pp. 260-274.
[4J D. D. Fuller. Theory and Practice of Lubrication for Engineers,
John Wiley and Sons. Inc. New York, N. Y. (1956).
[5J A. Kingsbury. "Experiments with an Air-Lubricated Journal"
Journal of the American Society of Naval Engineers, vol. 9 (1897),
pp. 267-292.
[6J J. S. Ausman and M. Wildman. "How to Design Hydrodynamic
Gas Bearings" Product Engineering, (25 November 1957) pp. 2128; 103-106.
[7J A. Brenner. Grace E. Riddell. U. S. Patent No. 2532283, (5
December 1950).
[8J A. Brenner, Grace E. Riddell. "Deposition of Nickel and Co baIt
by Chemical Reduction," Bureau of Standards Research Paper
No. RP 1835, vol. 39 (November 1947).
ADDENDUM
In the body of this paper, it has been stated. that as recording
density is increased without scaling down the head and drum coating
May, Miller, Howard, and Shifrin: High Speed, Small Size Memory Unit
geometry, recording on a minor hysteresis loop takes place under
the full region of the head. Since present conventional memory drum
design does not follow the practice of scaling down the entire recording geometry with increases of recording density, it would appear
appropriate to describe here two series of experiments which yield
data supporting the above statement.
In the first series of experiments, a recording geometry shown in
Fig. 7 in the body of this paper was used. It was found that for·a
given set of operating conditions there was an optimum head drive current for maximum output signal. This phenomenon can be explained
by the demagnetizing effect of the fringe flux upon the adjacent
dipoles, which is increased in strength by the increase in drive.
Saturation of the head pole pieces and drum coating can not be
the case because saturation would yield a limiting effect and not a
maximum point of operation.
In the second series of experiments, a typical small ferrite head
with pole pieces about 25 mils square was used which gave a head
length of slightly more than 50 mils. The head to drum spacing and
all other conditions were the same as in the first series of experiments
described above. At a recording density of 109 bits per inch, the output signal was about 40 millivolts and there was little or no tendency
to pattern sensitivity. When the recording frequency was increased
to give 350 bits per inch, the output fell to 6 millivolts and the pattern was distorted to the extent that errors would be caused in
reading it. It is believed that this pattern distortion and signal attenuation is due to an anticipation effect. That is to say that as each
dipole starts under the leading edge of the pole piece, some of its
flux passes into the pole piece and gives a read out signal. In these
experiments, it was possible to correlate exactly the output signal
wave form with the recorded bit length and the size of the pole piece.
In one case the drum was demagnetized and then a single 8 bit
pattern was written on it. Upon reading back, the entire pattern was
read three times: first as the leading edge of' the head pole point
passed over the dipoles, secondly with larger amplitude as the
dipoles passed under the gap, and once again as they left the trailing
edge of the pole piece.
In an actual computer application, if this anticipation effect occurs,
the true output signal may be so distorted that serious errors may
be introduced or the effectiveness of the system considerably reduced.
It appears that from a practical point of view for an adequate
design compromise for freedom from pattern sensitivity and signal
level output the head dimension measured in the direction of drum
rotation should not exceed the length of the recorded dipole by an
appreciable amount.
DISCUSSION
199
Mr. Howard: The drum is 2.5 inches in diameter; the sychronous
speed is 12,000; and actual speed, allowing for motor slippage, is
about 11,600. This gives a peripheral speed of about 120 feet per
second. The head inductance is 60 microhenries.
W. G. Dosse (MIT): What magnetic shielding do you have between
motor windings and drum and readers, or is stray motor flux not a
problem?
Mr. Howard: It would be a problem if you didn't take care of it.
The motor is surrounded by a magnetic shield, and the magnetic
recording material is plated on a separate sleeve which is shrunk on
the motor drum assembiy.
K. Enslein (Brooks Research): The storage density in your system is
approximately 2,500 bits per cubic inch. Could you discuss the relative advantages of magnetic cores and your drum for the application
at hand?
Mr. Howard: I am in no condition to do any mental computing up
here. But, as for comparing, you can get a cheaper bit stored on a
drum system than you can in a core. Of course, the disadvantage of
the drum is the access time. By suitably programming a fixed program and using circulating registers or revolvers to bring the words
up as required, you can cut this down. One of the main advantages
is the possibility of extending this concept to a system with extremely large capacity. I don't think that COfE'S could take the punishment that this thing will.
D. Roberts (Librascope): What air pressure range will the drum operate under? Is it pressurized?
Mr. Miller: A lot depends on the loading and hence spacing at which
the shoe is going to be operated. We have operated the unit up to a
pressure altitude of 30,000 ft. Since equipment like this should be
operated in a dust free atmosphere, we do not feel it is a great disadvantage to the design if it is kept in a pressurized container. When
it is finally installed, it will be in a pressurized box filled with some
inert and dry gas such as nitrogen.
P. Smith (Gen'l. Transistor): What keeps the shoe from the drum
before the drum gets up to speed.
Mr. Miller: The four small gears you saw in the slide are attached
to ends of eccentric cams. During the start operation, the cams are
rotated into a position in which the spring load is carried by the cam.
There is also a spring loaded pin in the arms to help keep the shoe
off the drum during the start operation. When the operating speed
is achieved, the cams are rotated and the spring load is transferred
to the shoe. During the first moment of starting there may be some
tendency for the shoe to contact the drum; however, sufficient lift
is developed at 500 rpm. To prevent damage during this early part
of the starting cycle, we have used a very durable hard electroless
plating of a nickel cobalt alloy.
W. N. Papian: I wonder if you could tell us what the status of the
project is right now?
J. Russell (University of Calif.): What is the peak to peak read signal
at your bjt density?
Mr. Howard: This was a research and development effort to determine the feasibility and the basic design requirements of a .drum of
this type. We have built several test models and the model shown,
which is in the form factor suitable for use in a micro-miniaturized
computer. At the present time, it is running and undergoing environmental tests. We are still working on it, and we believe it to
be a practical device. If our hopes materialize we shall wrap a computer around it.
Mr. Howard: 12 millivolts.
M. J. Haims (IBM): How was the head to drum spacing and angle
of attack measured?
Mr. Howard: It is very difficult to measure. The curve shown is for
calculated values and has been verified by laboratory measurements.
We have verified the general shape of the curve by at least two
methods. One method made use of electrical capacity between the
drum and small pads set into the shoe. The other method measured
the lift distance of the shoe off the drum surface by means of sensitive
dial gages and special electrical capacity probes.
D. Killen (Oliver Shepherd Industries): What is the peripheral speed
of the drum, and what is the head inductance?
G. G. C. Randa (IBM): What is resonant frequency of shoe and its
spring mechanism?
Mr. Miller: If you will recall what the curve of pressure vs. spacing
looks like, it is, of course, not linear and so does not really yield a
resonant frequency as such. If we consider only small displacements
and operate, in the 200 microinch range, we find that the spring constant is about 100,000 pounds per inch. Since the shoe and arms have
an effective weight of about one tenth of a pound, the resonant frequency would appear to be about 3000 cycles per second. With
induced vibrations up to 500 cycles per second no malfunction of
the shoe support mechanism seems to occur. However, at the
higher frequencies, say at 2000 cycles per second, malfunction is
impending and so some small amount of vibration isolation may be
required in the final installation if the supporting structure does
not attenuate these frequencies sufficiently.
P. Skelly (RCA Service): Are there any temperature controls used?
Mr. Howard: No, None at all.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
200
Temperature Compensation for a Core Memory
A. H. ASHLEYt, E.
u.
COHLERt AND W. S. HUMPHREY, JR.t
OR FIXED installation, it is often possible to
control the temperature of ferrite core memories
within narrow limits. However, in a small mobile
computer designed to operate over world-wide conditions, this control is not feasible because of the added
weight, volume, and cost encountered. A memory
designed for such application has been temperature
compensated by the use of temperature sensitive
components in the current sources to the X-Y drivers
and in the power supplies for the Z drivers. In addition, core derived strobing has provided peaking time
compensation for the sense amplifiers as changes in
transistor characteristics delay or advance drive
current. This compensation permits operation of an
8192 word 38-bit transistorized memory running at
an 8 microsecond cycle time in an ambient environment which may vary between -30°C and +55°C.
F
INTRODUCTION
Most computers use some form of temperature
control to maintain the operating temperature of the
ferrite cores within very close limits. This precaution
is required because of the sensitivity of the ferrite
material to ambient temperature variations. When
the environmental temperature goes up, the coercive
force will go gown and the material then loses some
of its squareness, consequently becoming more
disturb-sens~tive as shown in Fig. 1. Therefore, if the
proven satisfactory at +25°C will produce a ONE
about half as great as previously observed at normal
room temperature. Under this condition, there would
not be an output from a conventional sense amplifier.
Moreover, a fixed strobe would miss the peak signalto-noise time if the switching characteristics were
changed by such an amount.
TEMPERATURE CONTROL
The general solution to the temperature problem
has been to control the temperature within the
memory enclosure within a few degrees Centrigrade.
While at first this appears to be a simple solution to
the problem, it has proven unsatisfactory over a large
temperature range. To maintain the temperature at
95°C above the ambient (say at 65°C in a -30°C
ambient) it will be required to install a rather large
insulating oven complete with blowers and high
wattage heaters and provisions for creating turbulence
for proper mixing. When operating in conjunction
with accurate thermostatic equipment, it will suffer
from the inherent disadvantages of all mechanical
components. The reliability from such components
will result in degrees of magnitude lower than that of
the memory or the accompanying solid-state circuitry. Moreover, the cost of a good air thermostat is
considerably greater than that of the few electrical
components required to do the job.
64%
~
62%
~.
~.
::>
u. 58%
o
~
*-
~~
54%
50
20
40
60
Temperature ("C)
80
""
100
120
Fig. I-Percentage of full drive which will disturb
stored information vs. core temperature.
drive current is held constant while the temperature
rises, the cores switch faster, giving greater amplitude
to the output, and the cores are more sensitive to disturQance by the half-selecting drive pulses. The
reverse effect is observed as environmental temperature is lowered. Below O°C, the drive which has
t Sylvania Electric Products Inc., Needham, Massachusetts.
Temperature Compensating the Drive-Currents
Another alternative to control of the temperature
of the memory cores is control of the drive-current
amplitude. If the drive current is varied with temperature so that half selected cores are not disturbed but
the fully selected cores are properly driven for full
switching output, satisfactory operation is obtained.
From the memory cores of the type used in Sylvania's
MOBIDIC it was determined that drive-current
compensation aimed solely at maintaining constant
switching time resulted in a considerably lower output
signal amplitude at the low end of the temperature
range. Since the cores are less disturb-sensitive at
lower temperatures, it is feasible to compensate for
constant output-voltage-amplitude. The constant
amplitude compensation below 20°C minimizes sense
amplifier problems since no variation in strobe level
is. required. The overall compensation curve, shown
in Fig. 2, results in a constant core output below
20°C and constant switching time above that
temperature.
Ashley, Cohler and Humphrey: Core Memory Temperature Compensation
620
-20V
I
'\,
580
201
"I",
Constant Output
~ "-
~',
0 .........
I
Constant Switching Time
,
~
500
-40
= 50 mv
r....
---
- -
31.60
61.90
O",sec.
To Other
Sources
0
~
~
Ir----
1'0
60
20
-20
-
=1
80
_I
47.. f
VREF _ _
35_V_-t_-.t.
Fig. 3-Current source.
T_perature ("C)
Fig. 2-Core current required vs. temperature.
x -Y
Drive-Current Sources
The drive currents for the X-Y coordinates originate from high impedance current sources, each source
consisting of a power transistor connected in the
common base configuration. The high impedance is
required to maintain good current regulation under
varying load conditions. The circuit for the current
source is shown in Fig. 3. Current is supplied to the
emitter of the current-source transistor by a source
consisting of a reference voltage V REF applied across
a variable resistance network. The resistance is partially variable to compensate for initial differences in
transistor parameters. The reference voltage V REF is
common to all current sources in the X-Y circuitry.
Choice of Compensation Technique
The output current may be varied with temperature by one of two methods. Either the external
emitter resistors may have a positive temperature
coefficient, or the Voltage reference may have a
negative temperature coefficient. There are no positive temperature coefficient resistors available with
sufficient power capability for the first method. Even
if they were available they would not be very practcal
to use because of drive current tolerances. The latter
method is considerably better since it employs only
one temperature-sensitive network per memory and
uses readily available negative temperature coefficient
elements. Moreover, the common compensation assures that all drivers vary equally, thus minimizing
drive current tolerance problems.
V oltage Reference Design
Thermistors (negative temperature coefficient resistors) have a relatively low dissipation coefficient
(wattsjOC rise). It is, therefore, advisable to maintain a negligible dissipation within them in order to
have their resistance remain a function of true
ambient temperature without side effects from
internal heating. Consequently, ,the thermistor net-
-m
lK
2.21<
39O1l
390
7.870
82.50
1 5K
@~
lK
124K
+50V
-IOV
Fig. 4-Tempera ture compensated voltage reference (X-Y).
202
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
work is buffered by a power amplifier with a unity
voltage gain and a high input impedance, allowing
the use of current as low as 5 ma in the network.
The thermistor network and buffer amplifier are
shown in Fig. 4. Notice that the V REF is derived from
the - 20 volt supply as indicated in Fig. 3. This
means that variation in the - 20 volt supply will not
affect the current source accuracy. Two thermistors
are necessary to provide the proper compensation
characteristics over the entire temperature range. A
constant current of 5 ma through the 1k precision
resistor provides a constant drop of five volts. The
thermistor network with 5 rna through it will add a
voltage drop of 1.0 volt at +25°C, 2.2 volts at
- 30°C, and 0.52 volts at +55°C. The overall curve
between temperature end points is nearly linear,
(note that Fig. 2 is on an expanded scale) in great
part due to the constant five volts superimposed on
the temperature-sensitive voltage.
C~;:t
H7fRj 11YI I I 1114 I I
~~r.~
tf1:H I 11$fff r [JA LJJl
Fig. 5--Temperature compensated outputs.
Results Follow Theoretical Curve
The oscillographs in Fig. 5 were taken from an
experimental system consisting of transistor core
drivers and a memory core. The drive current varies
through the desired pattern, although the compensation at this time was slightly less than that shown in
Fig. 2. Even so, the ONE at - 30°C is within 10% of
the ONE'S at the other temperatures. A subsequent
slight revision of the thermistor network was made
to increase drive at the lower temperatures, resulting
in a higher output at the low end without affecting
the drive at other temperatures. The final compensation characteristic is as shown in Fig. 2.
Compensating the Z-Drive Current
The Z-drivers do not employ high impedance
transistorized current sources such as those used for
the X-Y drivers, because of less stringent current
tolerances. The current for each Z winding is determined by the power supply voltage across a fixed
resistance in series with the winding, as shown in
Fig. 6. In order to vary the current with temperature,
either the resistance or the total voltage across the
resistance must be varied. The first method was
impractical, because resistors with large positive
ten1perature coefficients are not available. To vary
the whole supply-voltage with temperature is not
practical due to complications in the power supply
design. To overcome these problems, one end of the
current determining resistance R1 was connected to
a fixed close-tolerance power supply (used elsewhere
in the memory) ; and the emitter of the output transistor, (Q3, Fig. 6), was returned to a temperature
sensitive supply V TEMP' This supply was designed to
vary from +0.5 volts at +.55C to +5.0 volts at
-30C. Because the maximum voltage swings up to
5 volts, considerably less power is involved in the
temperature sensitive control than if the entire 20
volt supply. were to vary from - 20 volts to - 25
volts, and the percentage variation is less critical.
Temperature Sensitive Emitter Supply
Because the thermistor network used in the X -Y
coordinate has a quasilinear resistance-temperature
characteristic, an identical network was used to derive
.4VQ-------r-----------,
-lOV
-4V
6412
z-
WINDING
SG225
-4 V
From Power
Supply
Fig. 6-Circuit for Z-driver.
Ashley, Cohler and Humphrey: Core Memory Temperature Compensation
-ISV
::10%
203
-''iJV
::.5%<>____._--,
I 5K
1/2W
'1%
-10 v
Fig. 7-Temperature controlled voltage source.
the emitter supply for the Z-drivers as shown in the effects can be observed in Fig. 5. The compensation
circuit of Fig. 7. A stage of inversion with a voltage for this variation is made completely and simply by
gain of 2 is interposed between the thermistor net- the use of a core-derived strobe pulse. The timework and the power amplifier in order to provide the discriminating-strobe is derived from a standard
proper phase and amplitude to the variation. The core receiving the same current as the selected cores
output is clamped to ground on the low end by the in the memory. That core is essentially wired to
transistor and to +5 volts ( +4.4 plus diode drop) on receive a full read and full write from the x and y
the high end by a diode. This clamping insures against drivers selected to supply the rest of the memory.
overvoltages on the Z-driver transistors. When none The output of the core is therefore a standard ONE
of the Z-drivers are in operation, 7.5 amps. are con- produced at the same time as all other ONE'S being
ducted to ground by the output transistor (Q5 of read out. This output is then properly shaped and
Fig. 7) of the V TEMP circuit. When Z-drivers are being suitably delayed to supply a strobe pulse for the
pulsed, the V TEMP output conducts the difference memory sense amplifiers. The block-schematic in
between 7.5 amps and the average Z-driver drain.
Fig. 8 gives the outline of the method employed.
Experimental results in a full memory show that
Compensation with Core-Derived Strobe
variations in the sense amplifier output of 0.8 microThe compensation of the drive currents still allows seconds may occur and are compensated by the coresome variation in the peaking time of the core output, derived strobing even when ZERO'S are larger than
even for perfect amplitude compensation. Moreover, ONE'S (under virgin-checkerboard test).
temperature affects the drive circuit delay. These
CONCLUSION
FIg. 8--Core-derived strobe system.
The operational limits of the memory were extended by the combination of core-derived strobing
and temperature compensated drive currents, as
shown in Fig. 9, which is a "shmoo" plot of temperature versus discrimination level limits of the sense
amplifiers. The smaller area with cross-hatching
shows the limit with core-derived strobe but without
temperature compensation; the larger encompassing
area shows extension of those limits by the temperature compensation. With neither core-derived strobing
nor temperature compensation, the limits are reached
at + IO°C and +45°C.
Because the MOBIDIC computer in which this
memory is being used is intended for battlefield
operations, provision is made for retention of the
information in the memory even after the computer
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
204
~
W. Lawrence, Jr. (IBM): How do you regulate against temperature
differences of memory locations receiving different interrogation
rates?
WITH CORE-DERIVED STROBE & NO COMPENSATION
..
& TEMPERATURE COMPENSATION
Mr. Ashley: I assume that refers to whether or not the core is being
self-heated by the application of the drive current. This particular
memory is not working at a high enough power and speed to cause
any appreciable heating, since the speed that is required is 8 microseconds cycle time. A total of 20 watts maximum occurs within the
enclosure for which we have capable blowers to ensure that the air
js circulated .
1 2
1 0
..
~
08
s. B. Yochelson (Goodyear Aircraft): Will you comment on the effects
of local heating in the plane, such as might occur if a particular core
is repeatedly interrogated?
..\'
~
~
06
Mr. Ashley: With the speed and power we have, we don't have that
problem. We don't need to drive the cores for the real fast switching
time that would require the high current. So the self-heating is rather
minimized.
04
02
-40
-30
-20
-10
+10
+20
+30
+40
+50
+60
Temperalu ... ("C)
Fig. 9-0pera tion Shmoo for sense amplifiers.
is shut down. Conceivably the information could be
read into the memory at one temperature and later
read out at another. Tests performed on the cores
showed no measurable difference between ONE'S
read out at a given temperature regardless of the
core's temperature when the information was stored
in it. Thus retention of memory is possible even if the
machine is shut down and restarted in a new and
widely different environment.
DISCUSSION
W. N. Papian: I wonder if you could give us a very rough estimate
of the percentage that has to be added as an increment to do this
compensation?
Mr. Ashley: The bjggest single item that has to be added is power
supply capability because we have to increase this drive. We are using
32 current sources, each a quarter of an amp at 20 volts, and we have
to have capability of power that the Z drivers might draw if the
whole 38 drew at once. This increases by 20 percent the power requirements. There is an unregulated power that is required of 9 or
10 per cent regulation of 100 watts to effect trus Z driver compensation, but beyond this the cost alone of the necessary additional parts
is very slight.
P. Barek (Lincoln Lab.): What is the variation in memory access and
rewrite cycle time as function of temperature?
Mr. Ashley: The access time actually doesn't change much because
we have a constant slope to the drive current. With increasing temperatures, although the circuit delay is more with a resultant later
start for the current, the rise time between 10 per cent and 90 per
cent of the current is faster. The two effects tend to cancel each other
in access time. Except for the change in delay in the sense amplifiers
and the external circuitry (registers, timing flip-flops, etc.) it is not
much different. I would guess maybe 0.2 microsecond slower at the
high i:,emperature than at minus 30° C.
J. R Veal (RCA): How much effect does low temperature have on
core switching times?
Mr. Ashley: It has a great effect on it but the idea of compensation
is to increase the drive current to overcome the effect.
G. N. West (IBM): What limitation do you impose on temperature
variation between write and read on a given core to eliminate distrub
on half select?
Mr. Ashley: To maintain the accurate write and read current? That
is in line with what has to be done for the inhibit drivers. The inhibit
current actually varies. Of course, the full select write current is kept
the same as the read because it is derived from the same voltage
reference. The inhibit current can vary as much as 8 to 10 per cent on
either side of the nominal value of the read for that temperature with
no harmful effect. Actually this is really conservative also, because I
think it could be 10 or 12 per cent without any great harm.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
205
Use of a Computer to Design
Character Recognition Logic
R. J. EVEYt
THE SYSTEM
T
HE IBlY,I 1210 Sorter/Reader recognizes char,acters printed in a specified location on paper
with magnetic ink. 1 A schematic diagram of the
machine system is given in Fig. 1. The characters
first come to a writing head which induces a magnetic
field in the special purpose ink with which the characters are written. Next this magnetic field is sensed
by a multi-channel reading head. The utput of the
reading head is a set of ten time-dependent voltage
waves.
Fig. I-System schema tic.
.......
...1."_2Ij
-.
4-1.....
I ......
lIO
[Ill-
,.
14
~ ..
~
B
1
10
:
X
:~!!:,W,~-,
.. !Y:!*W:I:IJ----1
x
xl,
xx
X
X
•
THE PROBLEM
2
I
:5Y----I
Fig. 2-Roll problem.
t International Business Machines Corporation, Poughkeepsie,
New York.
K. R. Eldredge, F. J. Kamphoefner, P. H. Wendt, "Automatic
Input for Business Data Processing Systems", Proceedings of Eastern
Joint Computer Conference (December 10-12, 1956), p. 69.
1
Actually (as Fig. 2 shows) there are thirty channels
in the reading head. However, every tenth channel
is "oR'ed" together (e.g., 1-11-21, 2-12-22, etc.) so
there are only ten outputs. These waveforms are
time-sampled and changed into binary pulses by the
quantizing circuits. The output of each quantizer is
seven bits of binary information per character. The
outputs of the ten quantizers (one per output channel
of the reading head) are stored in a 10 X 7 trigger
matrix.
The final section of the system is a set of 14 logical
circuits (one for each character of the ABA alphabeV)
made up of standard digital computer AND and OR
components. These circuits are driven directly by
the trigger matrix and operate in parallel. If a pattern
in the trigger matrix satisfies anyone of the logical
circuits (called logics in the sequel), the corresponding character trigger is set. Recognition occurs if one
and only one of these character triggers is set;
otherwise the pattern is rejected.
It was mentioned previously that the thirty channels in the reading head are OR' ed together in groups
of three. This means that the registration of the pattern in the matrix is unknown. So the system looks
for recognition ten times per pattern; that is, it tries
to recognize the pattern in the position in which it
first appears in the matrix. Then the whole pattern
is moved up one row at a time, wjth any bits in the
top row being brought down into the bottom row.
Thus each pattern really presents ten different patterns to the logics. Only after a pattern has "rolled"
through all ten positions are the fourteen charactertriggers examined for recognition or rejection.
This paper deals only with the design of the fourteen logics in this final part of the machine. It will
attempt to make clear the problems which we tried
to solve in this design and the methods we used to
develop these circuits.
The total number of different patterns possible in
a 70-bit matrix is 2 70 ; and the total number of logics
that can be designed for this input is 2270. The size of
these numbers requires that some simplification be
found to make the logical design tractable. Much of
the required simplification lies in the two-dimensional
2 Bank Management Commission: American Bankers Association,
"The Common Machine Language for Mechanized Check Hand.ing",
Bank Management Publication 147, Automation of Bank Operating
Procedure, 12 East 36 Street, N. Y. (April, 1959).
206
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
90rrela,tion of bits in the matrix; that is, most of the
logically possible patterns do not look anything like
a possible character pattern. We found that a basic
set of about 20 to 30 different patterns are obtained
90% of the time a given character is scanned. Almost
all of the rest of the time a pattern is obtained which
differs in one, two, or three bit positions from one of
the patterns in the basic set. If these noisy bit positions are treated as don't-care positions, logical combinations of the common logical characteristics of the
patterns in the basic set can be formed which will
recognize virtually all· the patterns obtained from
scanning a character. Noisy bit positions for a given
character account for over half the matrix, but this is
not serious because four bits actually overdetermine
the entire set of 14 characters.
The problem is thus reduced to that of finding the
stable combinations of bits for a given character. At
this point, however, we must consider the problem of
registration - a problem which is present in all
character recognition systems. Some are designed
from the point of view that this is the major problem
of character sensing and must be eliminated entirely;
that is, an attempt is made to design the system so
that once the first character is found there is no
further problem occasioned by registration. In the
1210 system, however, even after the character has
been scanned by the reading heads, the registration
of the pattern in the matrix is unknown. A solution
to the horizontal problem is the requirement that the
leading edge of the character be located in the righthand column of the matrix. The E13B font, with its
strong leading edges, is designed for this.
The problem of vertical registration reduces to the
"roll" problem, and the main problem here is that of
cross-recognition. A degraded two, for example, may
"roll" around to make a pretty good five (it should
be noted that in the 1210 system this situation would
result in a reject rather than a substitution, because
both the "two" and "five" character triggers would
be set). Part of the solution to this problem lies in the
fact that the normal pattern is only eight rows high.
Therefore, a condition which required at least one
blank row at the top or at the bottom of the matrix
was made a part of each logic. Once the pattern has
been restricted so that it can move only a few rows
vertically in the matrix and cannot roll completely
around, the problem of design of the logics has been
reduced to the required degree.
that is, if the edges of characters were not ragged,
there were no voids and no splatter, the magnetic
field induced was uniform over the whole character,
etc.
This set was generated by a program which we
called the Theoretical Shape Program (TSP). Details
of its operation can be found in Appendix 1. Letus say
briefly here that the input to the program was a coding of each ABA character into binary bits. Each bit
represented one square mil of ink. Hence, E13B
characters, which are nominally 117 mils high and
91 mills wide, were entered into the 704 in the form
of about 500 36-bit binary words (allowing for some
blank border). This "micro-matrix" was then
"scanned" by a program which simulated the
operation of the reading head and quantizers. The
output was a set of 10 X 7 "macromatrices" (i.e.,
simply a set of patterns for each character) which
were written directly onto 704 tape. The program
assumed that registration, variations of magnetic
density from character to character, timing across
the character, fringing of t~e magnetic field, printing
tolerances, etc. (see Appendix 1 for complete list of
parameters), cannot be held firm. Hence, these
"theoretical variables" were varied in the program
and used to generate a set of different patterns for
each character. This set was called the theoretical
shapes.
We resorted to experiment to get a feel for the less
systematic problems (such as voids). A hardware
model of the scanning and quantizing part of the
system was constructed and tied into an IBM 519
Reproducing Punch. This "print tester" scanned
single characters from checks run at 1210 SIR speed
and punched the resulting pattern into an IBM card.
A small sample (about 10,000 checks per character)
of printing chosen to cover the range of ABA printing
specifications 3 was scanned and punched into one
card per pattern. The resulting patterns (called "real
life" shapes) were transferred from cards to tape and
used to indicate the types of "noise" which might be
expected to degrade the theoretical shapes.
We now had two sets of patterns (each stored on
its own IBM 704 tape). Each of these was now reduced to a set which was composed of only the unique
shapes of the original. These patterns were now examined by a second 704 program called the Logic
Processing Program (LPP - see Appendix 2 for
complete details). This program accepted, as input,
logics (i.e., logic statements) punched into cards in a
SOLUTION
"Boolean" notation. It interpreted each logic and
stored it in core memory; then one pattern at a time
Theory
was read from tape and tested against the logic. If a
We assumed that the set of patterns to be recog- pattern which represented a two, say, were being
nized could be approximated by the union of two tested against a logic which was supposed to recogother sets of patterns which we could construct. The nize two's (self-test), and if the pattern was not
first of these would be the set of all admissible patterns assuming ideal printing and machine operation;
3 Bank Management Commission, op. cit.
Evey: Character Recognition "Logic Design
recognized by the "two" logic, but met a preset
number of conditions (see Appendix 2), the pattern
was printed. If it met the logic, that fact was simply
noted in summary tables printed at the end of a run.
If a two were being tested against a logic which was
supposed to recognize, say, fives (cross-test), the
criteria for printing the pattern or entering the tables
were nearly the reverse of those for self-testing.
Method of Designing Logics
With these tools at hand, the following method
was used to design the logics. A simple trial logic consisting of single black (1) or white (0) bits was tried
against the set of theoretical shapes for that character
(i.e., a self-test was run against theoretical shapes).
After several trials it is possible to determine a set of
10 to 15 positions consisting of single black bits inside
the character outline and single white bits close to the
character outline. It must be emphasized that it is
always a set of "sure bits" which is found. For different
criteria a different set will be found. For example, a
program was written which determined the maximal
set of sure bits for each theoretical character. However, in some cases, a more desirable set of sure bits
would be one which distinguished sharply a given
character from that character (or characters) which
looked the most like it. These "sure bits" were then
used as a trial logic for running a cross-test against the
rest of the theoretical shapes. The result of this run
would be a reduced set of "sure-bits", which were
useful in telling this character apart from the other
theoretical characters. Then these "useful sure-bits"
were used as conditions for a trial logic for the given
character.
First, this trial logic would be self-tested against
corresponding real-life shapes. Samples of real-life
shapes would not be recognized because of voids, inksplatter, skew, etc. By examining the tabulations and
patterns printed by LPP, the designer would attempt
to modify the single-bit trial logic by oR'ing a more
complex condition to the sure-bits which gave trouble.
This new logic would again be real-life self-tested.
After a number of trials, a logic would be obtained
which would recognize all of the real-life shapes the
designer felt were realistic. Then the logic was real-life
cross-tested and modified using· a similar procedure.
Here, however, the criterion for final acceptance
was that no character should be misrecognized by the
logic (this was due, of course, to the system's more
stringent requirements on substitutions than rejections). A flow-diagram of the above procedure is
shown in Fig. 3.
Several modifications of each logic would usually
have to be made at each step in the process before
the logic would be considered satisfactory. Sometimes
it was necessary to start from the very beginning with
a search for a new set of useful sure-bits. In all cases
a complete, transmissible record of the design of each
207
FIt«) USEFUL SURE BITS
FROM THEORETICAL SHAP£S
Fig. 3-Statement writing procedure.
trial logic, the results obtained in testing it against
the trial shapes, and the reasons for modification
existed in the summaries kept by LPP.
CONCLUSION
Only two other methods of designing logics of this
type are known to the author. One 9f these consists
of building hardware which allows the engineer to
shift wires in the model quickly (somewhat like IBM
plugboards for EAM equipment). In this way logics
can be wired directly into the machine and paper can
be fed through an actual model of the system. This
method has the advantage that the engineer knows
the logics are trying to recognize patterns which are
produced under field conditions. It has the great disadvantage that there are no records of patterns
successfully recognized by the logic. When a change
is made in logic wiring and a retest is run, the engineer
has no way of knowing whether the same patterns as
before are being presented to the logic. Hence, he has
no assurance that he is really comparing the new
logic against the old. The new logic may work better;
but it may be because it is seeing more easily recognizable patterns. This method of designing logics has
been tried at IBM and has not been as successful as
the subject method in either time, cost of logics, or
reliability. However, using the procedure described
in this paper, a set of statements for each of the
fourteen characters was developed with an expenditure of six man-months for the 704 programs (which
are of an exceedingly general nature and have been
used in whole or part for other applications) and two
man-months for the design of the logics. Further, it
was found that two different designers working
independently on the same statement tended to
produce logics that were equivalent in cost, performance, and the bit positions used (see Fig. 4).
The best proof of the method, however, lies in the
fact that the initial set of statements developed
through its use have been wired into models of the
208
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
o
0
000
o
I
Q)
..!l
~
r
t:K
0
8
1'0 0
o
7
8
(!)
\
6
o
0
o
0
~~
1(0
II
I IJ)
o
o
9
9
8
-r--
~
7
6
@(1)@ ~
FIELD
COLS
CD
1-6
~
~
~
~
7-12
14-15
17-18
20-21
23-24
(f)
(8)
26-27
29-30
~
35-37
Fig. 6-Parameter card for TSP.
up one mil in its relation to the channel and land
(dead space) and again scanned in accordance with
the same set of parameters. This process would continue until the character had rolled up to the position
in which its bottom edge just rested on the bottom
edge of the next higher channel. At this point it is
obvious that we would begin to see the same set of
patterns all over again. So another parameter card
would be read and this process repeated for that card.
This would continue until all the parameter cards for
a given character were read, at which point a new set
of character coding cards for the next character
would be read and the whole process repeated. This
process is illustrated in the simplified flow-chart of
the program shown in Fig. 7.
Fig. 7-TSP flow chart.
There was one parameter which does not appear in
a parameter card. That is the system of quantizing
used. This was varied by reprogramming. That part
of the program was made into a closed subroutine
and reprogrammed whenever the engineers changed
their quantizing circuits. About five different types
of quantizers were tried and they had so little in
210
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
common we felt this was better than attempting a
general program. It should be mentioned here that
after the program was used a couple of times, it was
so successful in simulating the scanning that the
engineers would try a new idea for quantizing here
before they would try it in hardware.
ApPENDIX 2 -
DETAILS OF LPP
The input to LPP consisted of two parts also. First,
of course, was a set of cards into which was punched
the logic to be tested. These were punched in this
manner:
The character for which the logic was written was
punched in column 1, (A, B, C, D being used for the
four special symbols of the ABA alphabet). The
number of conditions was punched in columns 2 and
3. A condition is a multistaged logical AND'ing and
oR'ing of trigger matrix bits which, when AND' ed with
other conditions, forms the logic for the given character. No assumption of minimal form is made, so
that the same logic may be decomposed in different
ways into conditions. For example, if A and Bare
two conditions, the total logic consists of A . Band
02 is the number of conditions. AB may be taken as
a condition and the total logic then has one condition.
Suppose A = C + D, then there are two conditions,
(C + D) . B; or the logic can be written BC + BD,
which is only one condition. Hence reference is most
easily made to a logic picture to see what was constituted as a condition. Fig. 8, which shows a simple
logic and what would be punched into the logic card,
may make this clear.
" +" for OR, a "," comma for AND, and the letter "S",
which also symbolized a logical OR but had a larger
scope than the plus sign. The numerals indicated that
a new condition was starting and told how many of
the sub conditions following it were to be satisfied (2
out of three for example). A subcondition is one bit
specified by the row and column location. If the bit
were to be a blank, a negative sign (X· over-punch)
was punched over the row.
NO
~
PREQ. TABLE
2 LOGIC
I
-Q.. .QJ
0
o
490 NCR
CHAR. 2
7
10
54
55
55
12 '
86
93
96
99
8
0
9
10
39
100
7
4
6
3
1""'1
2
7654321
I
I
I
'" •
I
I
I
, , ,
I
I
I
I
I
I
I
I
. .. .. ... .
II
II
I
I
I ..
I
I
I
I
•
I
I
I
I
I
I
44
486
CNML 2
9
.10
56
58
64
100
6
13
92
98
97
97
5
4
13
98
8
4
4
13
93
69
60
48
3
12
91
100 100
100
2
5
4
2
1
5
I
MFC
6
0
I-
0
_ _-.I
A
9
-"'."-
ANY TWO 0IIII- r---Y"",ES~_
Fig. 9-Logic processing program.
o
0
NO
.. I
Fig. 8-Simple logic.
Starting in column 4, a cycle of symbol-row-column
started and kept up until column 72 or until all the
logic was punched. If the logic had to extend over to a
second card the same sequence was used; that is,
character, total number of conditions, symbol, row,
column, etc., starting where one left off on the preceding card. The symbols used were numerals 1 to 9,
8
POS /
7
FREQ.
6
3
1 / 486.
Fig. lo-Frequency table (FT).
These cards were read by the program, interpreted,
and stored in memory. (See Fig. 9 for a flow-chart of
LPP.) Then the program read one character pattern
(the second element of input) from tape. This pattern
was tested against the logic. As we have said, if the
character were being tested against its own logic and
met all the conditions this was noted in a final summary table. Actually more was done with it. The
whole pattern was added, a bit at a time, into a
frequency table (Fig. 10). That is, this table kept track
of how many times the characters had bits in each
matrix position when considered in the roll position
in which they were recognized by the logic. Now, if
the pattern was not recognized, it was rolled through
all ten roll positions, and the program kept track of
the roll position in which it missed the fewest number
of conditions (or the first position in case of a tie).
Evey: Character Recognition Logic Design
A
CNML 2
CNMMAP
9
1 .1
2 LOGIC
CHAR. 2
1 1
CNMLXX
22
1 OHM /
1
POS
1
8
1
7
1
6
1
A
2
9
8
5
3 7
187
3
6
1 1 1
2
CONDITION 43
2 TIMES WAS THE
1
8 7
6
5 4 321
2 LOGIC
1000 NCR
CHAR. 2
MFC
3
100
66
66
66
9
33
66
33 100
8
100
7
66 100
6
33
33
66
66
66
33
33
5
4
••• 1037 TIMES WAS ONE
OF TWO CONDITIONS KEEPING
A 7 PATTERN
FROM SATISFYING THIS 2
LOGIC.
2
76
1104
1
1
144
87654
2
3
1
Fig. l'3-Condition-not-met map (CNMM).
OHM TABLE
CHAR. 0
1
CNN
66
33
33
3
0
33
66
33
2
1
1
1
2
60
87654321
3
25
CNML 2
A
33
ONE CONDITION
KEEPING A 7
PATTERN FROM
SATISFYING
THIS 2 LOGIC.
4
Fig. ll-Printed pattern (PRAT).
BPFT 1
CHAR. 7
2 LOGIC
4
040
*
992 NCR
1
1
27B515051528
211
2 LOGIC
2
3
4
CARD TOTAL
5
708
5
6
6482
8
7
9
A
B
C
D
1
5
17
48
1
2~
7 186
5 265
3 118
CNML 2
Fig. 12-Best position frequency table (BPFT).
Fig. 14-Summary.
Then the whole pattern would be printed out (these
printouts were called printed patterns, or PRAT's Fig. 11). Further, the pattern was added into a table
called a best position frequency table (Fig. 12). Further,
a table was made up of the conditions which were
missed. These were called condition-not-met-maps
(Fig. 13) and told the conditions which kept patterns from recognizing. If the pattern came within
one condition of recognition, the count was printed
on one line; but if it were two or more conditions
from recognition, the count was printed on a different
line.
As has been said previously, if a pattern were being
tested against a logic for a different character all the
above tables were entered but the criteria for entrance
were simply reversed. Further, entrance was made in
the tables for every roll position. In this way the
CNMM (condition-not-met-maps) told what conditions were actually keeping characters from
being recognized. All of these tables were printed at
the end of each character run. Only a final summary
table was printed at the end of the complete run
(Fig. 14). This told for each character how many
patterns came within 0 (i.e., complete) , 1, or 2
conditions of being met.
Complete control of entrance into each of the
summary tables and printing of the summaries was
maintained by using a combination of control cards
and sense switches. The control cards specified
whether or not a certain summary was to be kept
and, if so, gave a limit of conditions. If a pattern
missed recognition by more than this number of
conditions, the summary table for that character
was not entered. Then, as the program ran, the logic
designer could choose to see certain tables (or even
change the course of the program) by a selection of
sense-switch settings. In this way the program displayed only that data the designer thought would be
helpful at any given time.
212
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
A Self-Organizing Binary System*
RICHARD L. MATTSONt
INTRODUCTION
NY STIMULUS to a system such as described in
this paper can be coded into a binary representation. A character on a piece of paper can be
represented in binary form by dividing the paper into
many small squares and assigning a 1 to a square if
the character covers that square, and a 0 to the square
if the character does not cover it.
A voltage waveform can be coded into a binary
representation by quantizing the waveform in both
time and amplitude, and assigning a binary code to
each amplitude. In general, any data that are measurable can be coded into a binary representation with
no loss of information. One form of an interesting
logical system would be one which transformed this
block of binary data into a single binary decision.
For example, such a system would take the binary
representation of a character and transform it into a
binary decision (either it is an "A" or it is not an
"A"). Combinations of such devices could then be
used to make decisions of a higher order than binary.
The conventional method of designing such a system is to list in a table all possible combinations of
the binary inputs, and to assign the most probable
output value (decision) to each input combination.
This table of combinations with output values is then
reduced to a Boolean function which represents the
method by which the decision is to be determined.
This procedure will always yield the best possible
technique of making decisions.
However, this synthesis procedure has two major
disadvantages. First, the Boolean function is not
easily obtained when the number of binary variables
at the input is large. Second, even if the Boolean
function were determined, any change in the decision
process would require a repetition of the difficult
synthesis procedure in order to arrive at a new
Boolean function.
I t is the purpose of this paper to define a model for
a self-organizing logical system which determines, by
an iterative trial-and-error procedure, the proper
Boolean function for a process. This self-organizing
logical system is composed of two separate systems,
one a network of adjustable logical devices, the other
A
* Most of the work described in this report, including computer
simulation studies, was done at the Digital Systems and Components
Laboratory and the Computation Center, Massachusetts Institute
of Technology, under Navy BuShips Contract NObsr 72716. The
work was completed at Lockheed Missiles and Space Division,
Logical Design, as a part of the Lockheed General Research Program.
t Missile Systems Division, Lockheed Aircraft Corporation, Sunnyvale, Calif.
a system for determining what logical function
should be assigned to each device in the network.
Such a system is depicted schematically in Fig. 1.
INPUT
COMBINATIONS
DESIRED
OUTPUT
NETWORK
OUTPUT
PERFORMANCE NO OF SUCCESSES
NO OF TRIALS
Fig. I-Self-organizing logical system.
The adjusting system makes a sequence of adjustments in the network, each adjustment being determined by the performance of the network for the
previous adjustments, so that with the final adjustment the network realizes the desired Boolean
function.
AN ADJUSTABLE LOGICAL DEVICE
A logical device that can realize anyone of many
different logical functions by adjusting its internal
parameter values is shown schematically in Fig. 2.
CO~\~lTION
r---- - - - - - - - - ---. BINARY
I I - - - - ' - I__I WI
II'wl
: OUTPUT
12 ----'--1
:
I
I
I
In
Wn
IL
QUANTIZER
n'Wn
T
-I
I
I
_ _ _ _ _THRESHOLD
_ _ _ _ _ _ _ ..JI
Fig. 2-The adjustable logical device.
The inputs to this device are binary, + 1 and - 1.
The weights, Wi, are continuous real variables that
can assume either positive or negative values. The
threshold, T, is also a continuous real variable and
can be either positive or negative. The output of this
device is + 1 if
(1)
and - 1 if
(2)
+
The dividing condition between the output being
1 or - 1 is given by
n
T
+ "LItW
t
i=
= 0
(3)
Mattson: Self-Organizing Binary System
A geometric representation of the logical properties
of this device can be made by using the equation of
the dividing condition (Equation 3), and a binary
n-cube representation of the input space of the device.
For example, with three inputs to the model, the
dividing condition is
T
+
IlWl
+
I 2w2
+
I3w3 = 0
By plotting this plane in an 1 1 ,1 2 ,1 3 space, and
indicating various input combinations by points in
the space, the logical operation of the device can be
interpreted geometrically. That is, all points on one
side of the plane are mapped into a + 1 by the device,
and all points on the other side are mapped into a
- 1. A plot of the input space is shown in Fig. 3. In
an n-dimensional input space the dividing condition
specifies a hyperplane which separates the n-dimensional input space into two parts. It can easily be
shown that the W t values control the slope of the
hyperplane in the space, and the threshold, T, controls the position of the plane in the space.
~-- SEPARATING PLANE
,...~-- THIS INPUT COMBINATION
MAPPED AS +1,
THE OTHERS AS -I
Fig. 3-Three-variable input space.
By changing the w values and T, different mapping functions can be obtained. For example, with
this device one can obtain 14 different mapping
functions for two-input variables, 104 for three-input
variables, and approximately 1900 for four-input
variables. These different mapping functions are
termed "linearly separated" truth functions 2 • The
idea of passing a hyperplane through an n-dimensional
input space is important because it allows one to
visualize types of functions that can be generated by
the logical device. It is also useful for determining
the types of processes that the model would be best
suited to classify. For example, since the hyperplane
divides the input space into two regions, each of
which is a region of points unit-distant apart, the
logical device would be useful in classifying processes
in which one group of unit-distant points is separated
from another group of unit-distant points. An example of such a process is a single-error correcting
code where a legal n-bit word, and all combinations
unit-distant from this word, are to be mapped as the
legal word. Another possible use would be for character recognition where a legal character is to be
separated from all other characters. For this application each character and its variations must be repret
213
sentable as a group of closely connected points in the
input space, and each of these groups must be
separable from all the other groups. When this condition is met, a single logical device would be an
effective character classifier.
Another useful capability of the device is that of
assigning output values to input combinations that
have never been given to the device. For example, if
a small number of input combinations have been
given to the logical device and a hyperplane is placed
in the input space so as to map these combinations
correctly, then every point in the input space is
automatically assigned an output mapping by this
plane. This allows a mapping criterion to be established without being exposed to all possible input
combinations. In the case of character recognition,
where the number of possible variations of a legal
character is so large that it becomes impossible to
list all of them, a hyperplane could be situated in the
input space on the basis of a partial listing of variations, and the mapping of the other variations would
automatically be determined.
By interconnecting devices of this type, each one
realizing a different linearly separated function, and
feeding their outputs into an AND or OR device, any
logical function can be obtained. This is easily shown
since a single device of this type can realize the AND
or OR function of n-variables and any Boolean function can be written as a sum of products or product
of sums.
A network of adjustable logical devices can be
constructed by using as a basic element the device
shown in Fig. 2. By adjusting various weights and
thresholds in the network any logical function can
be realized. The remaining portion of this paper
describes methods of determining what sequence of
network adjustments should be made to obtain
convergence to a desired Boolean function.
ANALYSIS OF THE PERFORMANCE OF A
SINGLE LOGICAL DEVICE
Consider the input space of an n-variable logical
device. There will be 2n distinct points in this input
space, each one corresponding to a particular input
combination of the n-variables. Let these combinations be denoted as C l , C2 , • • • , Ck • • • , C2n. Each of
these input combinations has a probability, P(Ck), of
occuring at the input of the logical device. For each
input combination the desired output has a probability of being + 1, P(D k = + 1 I Ck ), and a probability of being - 1, P(D k = - 1 \ Ck ). If the input
combination Ck is mapped as a + 1 by the device,
then the probability that the output of the device
will agree with the desired output is
(4)
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
214
If Ck is mapped as a - 1 by the ,device, the
probability of agreement between the desired output
and the output of the logical device is
P 2 (A)
=
±
k=l
P(D k
=
+ 1 I Ck) + f
.=3
increasing T
P(D k
(5)
Since Ck must be mapped either as a + 1 or a -1,
then one of the two above equations is valid for the
probability of agreement for a fixed logical device,
~
and the other is not. Define a variable Xk so that
2n
Xk = 1 when Ck is mapped as a + 1 and is zero P 2n (A) = L P(D k = +1 I Ck) for Textremelypositive
k=l
otherwise, and a variable Xk which is + 1 when Ck is
as T is increased from negative to positive. In addimapped as a -1 and is zero otherwise. The probabiltion, if Po(A) < PI(A), then P(D 1 = -1 I C I ) <
ity of agreement for input Ck can then be written as
P(D 1 = + 1 I C 1) and C I should be mapped
as a + 1. By comparing PI(A) with P 2 (A) etc., it
can be shown that if the performance continuously
The total probability of agreement between the increases as T is increased, points in the input space
output of the logical device and the desired output are continuing to be mapped correctly as + 1. Whencan be obtained by summing the individual per- ever the performance decreases for increased T, that
formances of all the input combinations.
point should not be mapped as +1. From this result
it is possible to prove that if peA) increases monotonn
2
ically to a maximum (peak) value and decreases
peA) = L: [xkP(D k = +1 I Ck) + xkP(D 1c
k=l
(7) monotonically thereafter, then the mapping function
= -liCk)]
corresponding to T set ~t the peak is the best possible
The performance of the logical device is measured mapping function for that particular input space.
by the number of agreements divided by the number This is easily shown since, for T set at the peak, the
of trials. The expected value of this measurement is performance is
given by peA), and thus peA) is the expected
i
2n
performance of the logical device.
peA) = L P(Dk = +1 I Ck) + L P(D k = -11 C,,)
K=l
K=i+l
Earlier it was pointed out that the weights in the
and
for
each
1
:::;
k
:::;
i
logical device control the slope of the hyperplane in
the input space of the model, while the threshold
P(Dk = +1 I Ck) > P(D k = -1 I Ck)
controls the location of the plane in that space. Thus,
with the threshold set at an extremely negative value and for each i + 1 :::; k :::; 2n
the hyperplane will lie outside the binary n-cube in
P(D k = -1 I Ck) > P(D k = +1 I Ck)
that space, and all points in the input space will be
By using similar arguments it can be shown that·if
mapped as - 1. As T is increased in value the
there
exist m groups of + 1 points in the input space
hyperplane will pass through the binary n-cube,
that
are
separated from each other by a group of-1
changing the mapping of the points in space to + 1
points,
there
will be at least m peaks on the performuntil T is extremely positive and all points are
ance
curve.
A
sample performance curve vs. threshold
mapped as a + 1. With T extremely negative all
for
m
=
1
is
shown
in Fig. 4.
points in the input space are mapped as - 1 and
P(A)
Equation 7 becomes
2n
peA) =
L: P(D k = -1
k=l
PERFORMANCE
(8)
I Ck)
If the index k is arranged so that the sequence
k = 1, 2, 3, ... , 2n corresponds to the first, second,
... , 2n th point in the input space to have its mapping
changed to + 1 as T· is increased, then the performance will have the sequence of values.
2n
Po(A)
=
L: P(D k = -1
k=l
I
Ck)
for T extremely negative
2n
PI(A)
=
P(D I = +1 I C I ) +
L P(D k =
k=2
-1 I Ck)
T
Topt
THRESHOLD
Fig. 4-Performance curves with one peak.
Equation 7 gave the performance of the logical
device in terms of the performance for each input
combination. The index k was associated with the
sequence of points that change their mapping function as T is increased. When a given weight, Wi, is
changed, the hyperplane will rotate and another
sequence of points will change their mapping func-
Mattson: Self-Organizing Binary System
tion. Thus, the same results that applied for the
threshold can also be applied for each weight 'Of the
device, and a curve of the performance as a function
of W t can be plotted. Again it can be shown that as
the performance increases a group of points in the
input space is being correctly mapped, and as soon
as the performance decreases a point is being incorrectly mapped by the change in parameter of the
device.
(ff
~~~1:0F ~
POINTS
TO BE
MAPPED
AS +1
(2)
(3)
FIRST LOGICAL DEVICE
INPUT SPACE OF
SECOND LOGICAL DEVICE
(I)
DESIRED FUNCTION
Fig. 5--Synthesis with two logical devices.
The addition of other logical devices can be accomplished by letting each one adapt to a group of
separated points in the input space. For example,
consider the input space shown below. Here, since
there are separated groups in the input space, a single
logical device cannot realize the desired function.
However, a single logical device can realize the
function shown in Fig. 5-(2). If the performance
curve of this logical device is plotted against its
threshold it will have two peaks. One peak will
correspond to the function shown in Fig. 5-(2) and
this logical device should be adjusted to realize that
function. Every time the first logical device has an
output of + 1 the desired output of the second
logical device should be -1. This makes the input
space of the second logical device be as shown in
Fig. ,5-(3). Clearly this is a linearly separated function and can be realized by the second logical device.
By feeding the outputs of these two devices into an
OR function, the desired function is obtained. It can
be shown that the most difficult logical function t6
mechanize in this manner is the alternate symmetric
or even-odd functions. In .this case it requires 2 n - l
logical devices all feeding into an OR gate to realize
the function.
AN ADJUSTMENT PROCEDURE
Having related the performance of the device to
the change in parameter values, an adjustment
procedure can be devised for the adjusting system.
Briefly, the procedure is to start with a single logical
device and make a guess at initial values for weights
in the device. It has been demonstrated experimentally and justified mathematically that good
results are obtained if each weight is initially set to
the value of the cross-correlation between the particular input and the desired output. l This quantity
is computed from the equation
+1
Wk
=
+1
L: j=L: IiDjP(I
i=
-1
-1
i,
D}) = P(I k = D) - P(Ik = D)
215
For certain processes this initial setting is not the
best one to make; however, it is good for the types of
processes considered in the demonstrations. Then
vary the threshold from extremely negative to less
negative values and measure the performance for
each value of T. If the performance increases, increase T and measure the performance again. If the
performance decreases adjust the threshold back to
the peak. Then increase the weights one at a time
until a peak is obtained for each weight. The threshold and weights should be re-adjusted until any
change in any parameter causes a decrease in performance. At this point the hyperplane has a group
of points on one side that are correctly mapped, and
all points closest to the other side' of the plane require
the opposite mapping. Then T should be increased to
an extremely positive value and a measure of the
performance recorded for each value of T. If the
performance monotonically decreases for increasing
T then the single logical device with T set at the peak
realizes the desired truth function for the process. If
the performance curve has another peak as T is increased, then a single logical device cannot realize
the desired function, and other logical devices must
be added.
Because the adjusting. system obtains only a
measure of the peA) function, the measured performance may deviate from the theoretical performance. When this happens the performance curve will
not look like the one shown in Fig. 4, but rather will
have many small peaks and valleys as shown in Fig.
6. On this measured performance curve a slight
decrease in the measured performance may be due
to sample-size effects of measuring. Therefore confidence limits must be established by the adjusting
system to determine if the performance has actually
decreased, or if the decrease is due to measurement
errors. Thus, statements about the performance of
the logical system must be modified to include
confidence limits. As an example, with 95 percent
confidence the performance curve has only one peak
and therefore with 95 percent confidence the logical
system is realizing the best possible function for this
process.
PERFORMANCE
----+-A-·
T
THRESHOLD
Fig. 6-Measured performance curve.
The process of determining a peak on the performance curve can be speeded up by assuming a
slowly changing curve and by selectively sampling
the curve. Consider the curve shown in Fig. 7. This
216
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
curve is first sampled at n + 1 equally-spaced values
of T. Because the curve increases monotonically to
a peak and then decreases, one peak must be between the first and third sampling. The curve is then
sampled n times in this region. The peak must now
be between the second and sixth samples so the
curve is sampled n times in this region, and this
process is repeated until the peak has been determined. This process can be shown to converge
geometrically to the peak.
rIJIDJl:
FIRST SAMPLING
SECOND SAMPUNG
THIRD SAMP ING
Fig. 7-Successive sampling of the performance curve.
PATTERN RECOGNITION DEMONSTRATION 3,4
The devices and the adjusting system were simulated on the IBM 704 computer and four demonstrations of the self-organizing logical system were made.
Three of these were character-recognition problems
and one was waveform recognition. In the characterrecognition problems the network of logical devices
was to be adjusted until it realized an optimum truth
function for distinguishing one group of characters
from another group in the presence of noise. The
initial settings of the weights was the cross-correlation and in each demonstration this was a setting
which gave optimum performance. In each case the
noise-free characters were arranged in a fixed m X n
array of squares just large enough to contain the
characters. Noise was introduced into the characters
by selecting each of the squares in the array, one at
a time; the representation of each square was changed
with a probability, p, and was left unchanged with a
probability, 1 - p.
Demonstration 1: Recognize 5 and S; 25 Binary
Variables
In this problem the system was required to distinguish a 5 and a shifted 5 from an S and a shifted S
in the presence of noise. The noise-free and noisy
characters are shown in Fig. 8.
5
5
S
SHIFTED
NOISE-FREE CHARACTERS
5
5
SHIFTED
NOISY CHARACTERS
S
SHIFTED
S
SHIFTED
Fig. 8-Characters in Demonstration 1.
With 1.5 minutes of computer time, 2192 independent samples of noisy characters, and a single
logical device the 5's were distinguished from the S's
with 98 percent recognition. Because of the noise
this was the best possible theoretlcal performance
for this process. The performance curves were
sampled three times to determine the best setting of
the threshold. These curves are shown in Fig. 9.
Since the adjusting system used a confidence limit of
99.5 percent, it is 99.5 percent certain that the selforganizing system was realizing the best Boolean
function for this process.
AT ~ll~ ~~~CE
-.
+.
FIRST SAMPLING
-6
+6
SECOND SAMPLING
-e
+e
T
THIRD SAMPLING
Fig. 9-Sampling of performance curve, Demonstration 1.
Demonstration 2: Recognize 5, Sand 8; 49 Variables
In this problem the system was required to distinguish a 5 from an S and an 8 arranged in a 7 X 7
array. Noise was introduced in the same fashion as
in Demonstration 1. The noise-free and noisy characters are shown in Fig. 10.
•••
•••
5-+1
5-+1
S--I
8--1
NOISE-FREE CHARACTERS
S--I
NOISY CHARACTERS
8--1
Fig. lo-Characters in Demonstration 2.
It required 1.6 minutes of computer time, 1337
samples of noisy characters, and one 49-input logical
device to realize an optimum truth function for this
recognition problem. The sampled performance
curves for this process are shown in Fig. 11, and
again there was 99.5 percent certainty of realizing
the best possible Boolean function.
Demonstration 3: Recognize OF, AT, TO, and IN;
50 Variables
In this problem the system was required to distinguish the word OF from the words AT, TO, and IN
displayed in a 10 X 5 array. Noise was introduced
in the saIne manner as before. The noise-free and
noisy characters are shown in Fig. 12.
It required 1.1 minutes, 718 samples of noisy characters, and a single 50-input logical device to realize
Mattson: Self-Organizing Binary System
PERFORMANCE
IJIll
,I U
-4.0
-5.0 -20
217
AMPLITUDE
Il[
II,
-10
0
10 2.0
FIRST SAMPLING
50
40
11.11,
3.0
T
40
E
, ,I J ;:iTl"i I, ,
-40
-30 -20
-10
0
1.0
2.0
SECOND SAMPLING
3.0
, , , I,
-5.0
-2D
-20
50
II IfIll, ,
3D
20
I
10
T
4.0
WAVEFORM I
WITH NOISE
-10
0
10..20
FOURTH SAMPLIIlIG
50
OF--+H
AT---I
TO---I
NOISE-FREE CHARACTERS
AT---I
TO--I
NOISY CHARACTERS
WAVEfORM 2
WITH NOISE
TIME
(+11
TIME
(-II
Fig. 14-Waveforms, Demonstration 4.
:0 T
l1li111_ 1&1
OF--+I
40
30
Fig. ll-Sampling of performance curve, Demonstration 2.
IIIIHI
AMPLITUDE
40
-10
0
10
20
THIRD SAMPLING
PERFORMANCE
TIME
'T
117 PERCENT
PERfORMANCE
-40 -30
WAVEFORM 2
NOISE fREE
(-II
40
PERFORMANCE
-4.0
TIME
WAVEFORM I
NOISE FREE
1+11
AMPLITUDE
The self-organizing logical system required 0.9
minutes, 987 samples of noisy waveforms, and a
single 216-input logical device to distinguish the
waveforms with 100 percent recognition. A sampling
of the performance curve is shown in Fig. 15.
SECOND SAMPLING POINT PERFORMANCE
(FINAL VALUE I
100 PERCENT PERFORMANCE
1.0
IN---I
_______+--~~~~~~~~~~~-----------T
- 16
-!2
-e
-4
0
•
12
I.
Fig. 15--Sampling of performance curve, Demonstration 4.
IN---I
Fig. 12-Characters in Demonstration 3.
CONCLUSIONS
From the results obtained in the simulation studies,
it appears that this technique of self-organization
allows solution of many practical pattern-recognition
10
problems. These problems could take a varie,ty of
forms, from visual recognition to speech recognition,
and more complicated data reduction problems such
-12
-10
-.
-.
-4
-2
0
2
4
10
12
as binary predicting and filtering in the presence of
FIRST SAMPLING
noise. The time and amount of data required for the
Fig. 13-Sampling of performance curve, Demonstration 3.
system to "adapt" to a given arbitrary task seem to
the optimum function (100 percent recognition) for be within practical limits. It is not known what the
this problem. The single sampled performance curve equipment requirements would be for a general
self-organizing system, and a variety of more diffiiis shown in Fig. 13.
cult pattern-recognition problems are needed to
Demonstration 4: Recognition of Waveforms
determine the versatility of a "self-organizing"
The fourth demonstration problem for the self- logical system requiring many logical devices.
organizing logical system was to distinguish one
REFERENCES
waveform from a similar waveform in the presence
Analysis of an Adaptive System for
of noise. The two waveforms were quantized into 36 [lJ R. L. Mattson, The DesignS.and
M. Thesis, M.I.T., Course VI, June
Statitiscal Classification,
discr.ete instants of time and the amplitude at each
1959
instant was coded into a 6-bit binary code. Thus, the [2J Applied Mathematics and Statistical Laboratory, Unate Truth
binary representation of a waveform required the
Functions, by Robert McNaughton, Technical Report No.4,
Stanford University, Oct. 21, 1957.
combination of 216 binary bits. Noise was introduced
[3J
Computer Components and Systems Laboratory, An Adaptive
so that the greatest amount of noise appeared in the
Classifier, by R. L. Mattson, Quarterly Progress Report No.6,
least significant bits of the amplitude code, and the
Cambridge, M.LT., March 1959.
least amount of noise appeared in the most significant
[4J Computer Components and Systems Laboratory, An Adaptive
bits of the amplitude code. Examples of noise-free
Classifier, by R. L. Mattson, Quarterly Progress Report No.7,
Cambridge, M.LT., June 1959.
and noisy waveforms are shown in Fig. 14.
PERFORMANCE
100 PERCENT
PERfORMANCE
218
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
Alpha-Numeric Character Recognition
U sing Local Operations
J.
1.0
s.
BOMB.At
INTRODUCTION
T
HIS PAPER describes a demonstration of the
recognition of thirty-four alpha-numeric characters. The IBM 704 EDPM was used as a tool
to study the method which led to this demonstration.
The Generalized Scanner! was used as an input
transducer for this study.
The method of character recognition which was
used here is to extract from the character its "essential" features and then recognize it from these features. For this study such features as horizontal,
vertical, and slant straight lines, and intersections
of lines have been used.
These features have been extracted by means of
local operations. A local operation is a transformation
which produces a small section of a new pattern, or
field, from data in a corresponding small section of the
original pattern (Fig. 1). An entire pattern is transformed by considering all of the small sections, where
each section is considered independently. Here, the
pattern area was divided into a sixty by ninety array
of bits (i.e. either black or white spots) in order to
quantize the visual impression of a character. A typical local operation section would consist of fifteen bits.
LOCAL AREA
p 1-----1--------+_ Y
ORIGINAL
RESULT
Fig. I-Illustrated definition of a local operation. A "local area" is a
configuration of spots not necessarily square as drawn which is
examined by the program. The position P'J of the local area is
defined as the position of one particular spot in the configuration;
e.g., point P in figure 8 and Y'J is the spot which is made into a
"1" if the spots found in the local area indicate the presence of a
specific feature. Both P'J and Y'J have the same coordinates (i, j).
Since P'J scans all points in the original patterns, the resulting
pattern must contain the same number of points as does the
original.
In order to extract a specified feature, the whole
pattern is processed and the resulting pattern then is
blank unless the desired feature was present in the
original pattern.
t Bell
Jersey.
Telephone Laboratories, Incorporated, Murray Hill, New
\"'~///
12
7
4
2
I.
16
15
14
13
18
6
17
>< ~
20
19
8
9
21
iL
10
II
LINE
ENDS
22-38
Fig. 2-Features extracted by Feastract. Only features above the
dashed line were used for recognition. The numbers are to identify
the features for Fig. 12.
The procedure for recognition is as follows. First,
the characters are processed by a program which
reduces the noise in the field by the method of local
averaging 2 • In this method, the value of the majority
of spots in a three by three rectangular local area
dictates the value of the center spot in the new
pattern. This process is more effective if it is repeated
twice. Second, the line width is standardized. Since
the matrix granularity is such that a typical line
trace as written is always greater than four matrix
elements thick, a line-width standardizing operation
can extract the middle four matrix locations. Third:
the features as shown in Fig. 2 are extracted. These
are:
(a) straight lines which are horizontal and vertical,
and slant straight lines which are at ± 45
degrees, ± 30 degrees, and ± 60 degrees from
vertical:
(b) all four orientations of T - and L-intersections,
and
(c) selected orientations of V -intersections.
The local areas (as defined in Fig. 1) which are used
to extract these features, have the same shape as the
desired feature. There are seventeen different features
for which the original pattern is examined. In effect,
a complete pass is made through the pattern for each
feature and whenever a local area in the pattern
matches the interrogation local area, a mark is made
in a corresponding output matrix. This is done for
each of the seventeen different features, thus generat-
Bomba: Alpha-Numeric Character Recognition
6 0 - - -.......\
/
'
......
vary horizontally and vertically, from a mInImum
average of four matrix elements to a maximum average of ten matrix elements. The characters must
roughly be centered when they are less than twothirds full size, and must be reasonably free from tilt.
2.0
9o
219
INPUT METHODS
The visual impressions have been transferred into
the 704 by a manual and a machine method, both of
which are described below (see 2.2 and 2.3).
The visual image is first quantized by dividing the
pattern field into square elements and giving each
element a value of "0" or "I" depending on whether
the field is light or dark at that point. In this study
the character lines were dark on a light background,
Fig. 3-Division of pattern field. The field consists of a
60 x 90 array of bits.
and these character lines are represented by the bit
locations which are ones.
ing seventeen "new pattern fields." Fourth, these
The image, which then consists of "O"s and "1"s, is
fields are divided into nine equal rectangular areas stored in the computer in this binary matrix form.
(shown in Fig. 3). The prevalence of spots in certain
Each 60 element row of the matrix is split in half
areas is used to indicate the general position of the and each half is stored in the least 30 significant bits
feature (i.e. top or bottom) and its significance (i.e. of a 704 core word. The rows are in 90 consecutive
whether a straight line is long or short). Fifth, the pairs of storage locations.
recognition is done from the detection of the presence
of features. In most cases, it was only necessary to ask 2.01 Matrix Size
whether a given feature was extracted. However, with
A 60 X 90, 5400-element matrix was chosen
the limited variety of feature types which were used because:
in evaluating the method, it was necessary to ask
(1) It is large enough so that quantizing errors
further questions about a few features such as horishould be negligible.
zontal and vertical straight lines. The identification
was done with combinational logic. The logic was
(2) It is large enough so that the edges of the
extended to allow some variation in character styles.
pattern need not be covered by the local operation if the character is more or less centered
(thus, it was not necessary to program the
A B C D E F G
special cases which occur when the local area
is only partially present as would happen at
H
the field edge. As you will see later in the disJ K L M N
cussion of feature extraction (see Fig. 10),
since the largest local area used extends 7
p
Q R S
U
T
spots from the local area center, the effective
size of the matrix is thus 46 X 76.)
y
V W
(3) Its width will just fit the printer which we use
with the 704, (119 available type wheels are
used to print the pattern with every other one
2
3 4
6
5
7
printing a blank. The blanks are printed to
limit the distortion of the field which the
printer introduces because (a) in the original
8
9
0
quantization the matrix elements are square
whereas (b) on the printer the elements are
Fig. 4-Typical style of hand printed
block capital alphanumerics.
rectangles whose height to width ratio is 6 to 5
when the blanks are printed and 6 to 10 when
Hand printed, block capital letters and numbers of
they are not).
the style shown in Fig. 4 can be recognized by this
method. These are the letters "A" through "Z" and 2.2 Manual Procedure
the numberics "I" through "0"; a "one" and "I",
In order to test the programs and to try sample
and" zero" and "0", are not separately distinguished. characters before the Generalized Scanner l was
The characters may vary from full to one-half size finished, test patterns and characters were made up
vertically and horizontally. The line widths may on IBM cards.
a
x
Z
220
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
For test characters, first the true size characters
were drawn on translucent paper. They were then
made into viewgraphs which were enlarged by a slide
projector. The enlarged image was focused on a
60 X 90 rectilinear grid 1.50 X 2.25 feet. Thus, each
74/1 X 74" element could be marked if more than
half its area were black. IBM cards were then
punched from this grid. One card per row was used
with "ones" punched to correspond to black elements
and nothing punched for white elements. Special program test patterns were made by marking the large
grid.
2 .3 Machine Methods
With the advent of the Generalized Scanner it became possible to write the characters on opaque
paper and transcribe the scan results onto magnetic
tape which can be fed to the 704. This machine
method makes it possible to quickly and easily process a large number of characters.
3.0
CHARACTER PREPARATION BY LOCAL OPERATIONS
3.1 Noise Reduction
In order to allow as inputs to the feature extraction program, characters which have missing spots
within the line of the character, extra spots in the
field outside the line of the character, and fluctuations
along the edges of the character lines, the character
can be processed by a program which performs local
averaging 2• This program uses a local area, Fig. 5,
which is 3 X 3 rectangle. The criteria which are
applied for this local area are: (1) if there are five or
more "l"s in the nine possible spots and if the center
spot was a zero, then the center spot is changed to a
one. (2) If there are five or more" zeroes" and if the
center spot was a one then the center spot is changed
to a zero. (3) In all other cases, the center spot is
retained as it was in the original pattern. This process
works most satisfactorily if it is repeated two or three
times. That is, the original pattern is processed, then
the result of the first processing is used as an input
to the second process, etc. An example of the results
of reducing the noise by this method can be seen by
comparing a typical original pattern, Fig. 6, and the
resulting pattern (processed twice), Fig. 7.
Fig. 6-Unprocessed character "D' '.
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Fig. 7-Character "D" after local averaging twice.
Bomba: Alpha-Numeric Character Recognition
221
Other criteria for the 3 X 3 local area and a 5 X 5
local area with a variety of criteria were tested. The
3 X 3 local area and the criteria of the previous paragraph were found to be the most satisfactory of the
possibilities which were studied.
3 ..~ Line Width Standardization
The feature extraction program works best when
the characters have a uniform line width. Therefore,
a program was written to process characters with
line widths which vary from 4 to 10 spots and produce characters with standard line widths. This program will change the character lines to a uniform
average width of approximately 4 spots. The local
area which is used by this program is shown in Fig. 8.
Fig. 9-Character "D" after local averaging twice and thinning.
x
x
/+--;---r------r--+rB
x
x
x
x
x
Fig. 8-Local area for line width standardization-thinning
(11 x 11 array).
The criteria for this operation are that (1) a spot will
be a one only if the original spot were a one and the
difference between areas A and B and between areas
C and D in the local area was less than 4"or (2) the
difference between the number of spots in the areas
E and F and the areas G and H are less than 4. An
example of "thinning" the previously "denoised"
characters is shown in Fig. 9.
This program might be improved if we made the
actual radial distances in the local area all equal. (It
is obvious, Fig. 8, that five elements at 45 degrees
extend further from the center than do five elements
in a rectilinear direction).
4.0
Fig. 2 indicates which of the features are used and
which are not.
4.1 Local Area
The local area which is used for the feature extraction is shown in Fig. 10. This local area is actually a
combination of a number of local areas, each of
which might be used for a different local operation to
2
16
14
5r-+--+-+--t-+--+---i
13
12
FEATURE EXTRACTION
The crux of this method of character recognition
are the local operations which are performed by a program which is called Feastract. This program extracts
the features which are shown in Fig. 2. Because this
program was designed to study the method, it actually extracts more features than are used by the recognition procedure. The most useful features are the
long straight lines: horizontal, vertical, and slanted.
8
10
9
Fig. lo-Local area for Feastract. (1) Shaded areas are to distinquish
radii. (2)Matrix elements are only drawn in completely for one
quadrant. (3) The local area for a single feature would consist of
selected radii. Thus, for a horizontal line, radii 5 and 13 plus p
would be the local area.
222
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
extract a different feature. However, for purposes of ning manner. Whenever all spots in this local area
study, it was convenient to arrange a local area in are found to be "ones", a one is written in a buffer
the manner shown, a radial pattern which enabled image for the L-feature at the same coordinates which
me to vary both the criterion for extraction and the "p" has. Since the original pattern is not changed
shapes of the features which are found to be most during the above process, the entire operation could;
of course, be done in parallel.
suitable.
The same process can now be done for each feature
I t should be noted here that this local area, as
applied in this program, is used for local operations; which we wish to extract.
The result is a group of buffer images, one for each
however, if the number of points at which the local
area is used is limited to fewer than all points in the feature. Fig. 11 illustrates schematically some buffer
overall pattern, then this local area falls into the images which would be produced from the original
class of feature extraction methods which can be pattern. Each buffer image contains one feature.
After all of the spots in the original pattern have
called radial or polar scan methods 3• There is one significant difference, however, between the polar scans been examined and the results of the feature extracand this scan. That is, each radius in my local area is tion process stored in various pattern buffer images,
required to contain "a" spots (where "a" = the the program proceeds to examine each of these buffer
number of spots in the entire radius, or nearly all images, and it determines whether or not there were
spots to allow for some noise) whereas in the polar any spots corresponding to the given feature in each
scans each radius is only considered from the view- image. If a spot is found in a buffer image, the propoint of crossing a line. That is if any radius contains gram determines in which of nine areas the spot lies,
any spot, it is considered to have crossed the line for as shown in Fig. 3. A series of counters are used to
remember how many spots lie in each area of the
the polar scans.
field for the feature under question at the time. When
4.2 E:fJective Operation of Feastract Program
the buffer image for a given feature has been comIn order to clearly present the feature extraction pletely scanned and the number of spots in each area
process, the details of the Feastract program will be of the field have been recorded in the counters, then
omitted. Thus, we will discuss the feature extraction the result is transferred to the recognition program
and also printed out. The basic program was desi~ned
process.
Let us consider a specific feature as an example, so that it would handle up to 50 features.
Note that this feature extraction program does not
namely an L-intersection. The local area for an Lintersection consists of radii 1 and 13 and the spot consider the feature "closed loops" (as encountered
"p" as shown in Fig. 10. The spot "p" with its associ- in a well-formed B). Although closed loops can be
ated spots is moved over the pattern field in a scan- extracted with local operations4, they are not a necessary feature for recognition of the symbols which
were used here.
....
R
o
FI (-)
I
F2 (I)
4.3 Output from F eastract
Typical information which is transferred from
Feastract to the recognition program is shown in the
following list for one feature. This list consists of the identifying feature number and - the number
of spots for the given feature which were found in
each area of the field (Fig. 3).
Register
Contents
2
Feature Number
Top Right
27
Middle R,ight
78
24
Bottom Right
o
Top Middle
o
Middle Middle
o
Bottom Middle
Top Left
30
59
Middle Left
16
Bottom Left
ETC
Fig. ll-Original pattern (0) and buffer images (Fl, F2, etc.)
which result from feature extraction process.
These numbers resulted from the extraction of vertical lines (Feature Number = 2) for an H.
Bomba: Alpha-Numeric Character Recognition
4
H
T
L
40R 6
B
E
BR OR MR
R
P
F
0
3,4
M
U
N
K
I
Z
A
2 LONG
2
I LONG
6 TOP
6
5
BOT
G
C
3
A
7
8
I
6
LONG
G
9
8
5
5
Q
G
0
U
J
C
X
W
Y
U
v
Fig. 12-Recognition tree -logic diagram. The feature numbers at
each branch point are identified in Fig. 2. At each branch point
the upper branch is followed if the feature is present.
5.0
RECOGNITION FROM FEATURES
2.23
tern are eliminated. Second, a test is made to see if
there are horizontal features in the three top areas.
The same thing is repeated for the three middle areas
and then for the three bottom areas. The results are
stored in registers called TOP, MIDDL and BOTOM.
Third, it is then possible to say that if the TOP
register has the number three in it, there is a long
horizontal line at the top. When there is a number
one in it, then there is a short horizontal segment in
the top. Thus, the number and length of horizontal
lines can be determined for characters which have
the restrictions as indicated in Section 1.0.
The same procedure which was used for horizontal
lines can be applied to vertical lines. In this case, the
information is stored in registers called LEFT,
MIDLE and RIGHT.
There is also a subroutine to determine if there is,
for instance, only one horizontal line in the field.
The same procedure could be applied to slant lines.
However, for this particular recognition tree, it was
not found to be necessary to apply this type of preprocessing to other than horizontal and vertical lines.
5.2 Recognition
As indicated in Section 5.0, the recognition proceeds as a series of binary choices. The majority of
tests which were used to make these choices are the
following two:
(1) The presence of a feature is determined by
testing the computer memory location of the
feature number for non-zero. (See Section 4.3).
(2) The presence of a feature in one of the nine
field areas is likewise determined, except that,
in some cases, a minimum number of spots is
required in the test. The other tests which were
used are discussed in Section 5.1.
Recognition is accomplished by combinational
logic with the features as the input variables. Since
there is a two-way choice corresponding to the
When a terminal branch of the recognition tree is
presence or absence of each variable, the logic takes
reached,
the identified character is printed.
the form of a logical tree (Fig. 12). However, before
It
is
interesting
to note in Fig. 12 that a great many
the actual recognition takes place, certain preprocessmore
characters
result
from all of the tree branches
ing can be done on the features and their locations.
than just the 34 which we initially started with.
We thus have evidence from this tested recognition
5.1 Preprocessing
tree
that, even with the restricted input patterns
A series of subroutines were written to take the inwhich
we have used, redundancy has to be included
formation from Feastract and to partially interpret
in
the.
recognition logic. Some subtle variations in
this information to answer such questions as, "how
characters
have only become apparent when they
long is a horizontal line"? The detailed specification
were
encountered
in testing this recognition logic.
of said question would be, "does a horizontal line
cross three areas in a horizontal row in the field"?
6.0 EXTENSIONS OF THIS CHARACTER RECOGNITION
We can now consider more details of the answer to
ApPROACH
the above question. A general statement of the criThis character recognition approach, which I have
teria for answering the question is: "Horizontal lines
are considered to be long, if all three areas of the field described, has been used to actually recognize characin a horizontal row each contain more than two marks ters in order to show that it works. Here, in this feasiwhich were identified from horizontal feature sec- bility demonstration, only a few of the features which
tions." In other words, first, all those areas with only can be extracted with local operations have been
two marks indicated in the new or transformed pat- used. It seems clear that if the local area of Feastract
224
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
were used for other features which it can extract
(ends, curved segments), many of the restrictions
which have been here (Section 1) imposed on the characters could be removed. Along this same line, if other
local operations, such as concavities as described by
Unger,4 were included, the field would not have to be
divided and thus larger variations in the characters
could be admitted.
Unfortunately, there does not seem to be any good
orderly way to specify the most desirable features or
to specify the local area or local operation to extract
a given feature. Fortunately we can use the 704 to
test possibilities without the long process of building
hardware. Nevertheless this is still a trial and error
process.
Also, the logic for the recognition for this demonstration allows only limited variations in the characters. Although to the human being, characters of a
wide variety appear to be the same, very often these
characters are actually quite different from their feature viewpoint. Seriphs, slanted characters, and decorations tend to make the character into a different
symbol. Thus, in an identification procedure which
utilizes features, whether they be the normal features
as specified by a human being or some special parameters which are not normally recognized by human
beings, these various forms must be treated as separate symbols. The identification procedure could be
lengthened to allow other forms of characters to be
recognized.
Finally, unless self-organizing systems rapidly become a lot more sophisticated than they are now, any
machine which we build to recognize large alphabets
of characters of unspecified style will probably use a
combination of several recognition methods, along
with feedback to make more and more complicated
tests until there is a high enough probability that
there is a correct identification or a rejection.
7.0
CONCLUSIONS
It has been explained how features may be detected
to recognize certain isolated alpha-numeric characters
by using the local operations mentioned above.
Three sample alphabets were tested on an IBM 704,
and the characters in these alphabets were separately
recognized. With this limited amount of test data, it
was felt that any attempt to' specify allowable
signal-to-noise ratio, character distortion (such as
tilt) or a recognition error-rate would not be
meaningful.
Others4 ,5 have shown the power of using other local
operations for this same purpose. Only a few of the
many possible local operations have been investigated, and it seems likely that this approach will be
useful not only for character detection but also in
other areas of pattern recognition.
8.0
REFERENCES
[1] W. H. Highleyman and L. A. Kamentsky "A Generalized Scanner
for Pattern and Character Recognition Studies", PROC. W. J.
C. C., pp. 291-294, March 1959.
[2] G. P. Dineen "Programming Pattern Recognition", PROC. W·
J. C. C., pp. 94-100, 1955.
[3] T. L. Dimond "Devices for Reading Handwritten Characters",
PROC. E. J. C. C., pp. 232-237, 1957.
[4] S. H. Unger "Pattern Detection and Recognition", PROC.
I. R. E., vol. 47, pp. 1737-1752, October 1959.
[5] R. L. Grimsdale. et aI, "A System for the Automatic Recognition
of Patterns", PROC. I. E. E., vol. 106, Part B., No. 26, pp. 210221, March 1959.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
225
Pattern Recognition and Reading by Machine
w. w.
BLEDSOEt AND I. BROWNINGt
INTRODUCTION
ANY EFFORTS have been made to discriminate, categorize, and quantitate patterns, and
to reduce them into a usable machine language.
The results have ordinarily been methods or devices
with a high degree of specificity. For example, some
devices require a special type font; others can read
only one type font; still others require magnetic ink.
We have an interest in decision-making circuits
with the following qualities: (1) measurable high reliability in decision making, (2) either a high or a low
reliability input, and (3) possibly low reliability components. The high specifiGity of the devices and
methods mentioned above was felt to be a drawback
for our purposes. All of these approaches prove upon
inspection to center upon analysis of the specific
characteristics of patterns into parts, followed by a
synthesis of the whole from the parts. In these
studies, pattern recognition of the whole, that is,
Gestalt recognition, was chosen as a more fruitful
avenue of approach and as a satisfactory problem for
the initial phases of the over-all study.
In addition, we chose to concentrate upon the recognition of alphanumeric patterns, rather than upon
other pattern types, for the following reasons:
M
(1) Convenience. Results can be handled easily
since it is possible to use conventional printout equipment. Furthermore, we could exploit
our own familiarity with letters and words.
(2) Background. Research on alphanumeric pattern
recognition has been vigorously pursued, and
we were therefore able to make use of the relatively large literature on the subject.
(3) Usefulness. Success in our efforts would make
available a technique which society needs and
can use immediately, even though such a result
would be only a by-product of our over-all
study.
Because typewritten numbers were recognized
without error in the cases considered, the investigation quickly shifted to hand-blocked print and finally
handwritten script characters as displaying greater
complexity and increasing individual variability. In
this way ,the decision making powers of the system
were more fully challenged.
Since a numerical output is the inherent mode of
expression of a digital computer, our work was aimed
at developing a numerical score for each pattern ext Sandia Corporation, Albuquerque. New Mexico
amined. The basic method employed to obtain these
scores and to use them to identify each pattern
uniquely will be described in the following section.
Then various expansions and variations of the method
will be covered. Finally, a method of extending identification by contextual relationships will be described
briefly.
It may be mentioned at this point that this system
is highly general - that is:
(1) It handles all kinds of patterns with equal
facility.
(2) Because it does not depend upon absolute pattern-matching, it can identify a pattern which
is not exactly like, but only similar to, a pattern
it has previously learned.
(3) It does not depend significantly upon the location of a pattern on the photomosaic for identification.
(4) It is only partially dependent upon the orientation and magnitude of a pattern for identification.
It would also be well to mention the two major disadvantages of the system:
(1) When the learned patterns are quite variable,
the memory can be saturated, especially in certain cases.
(2) A very coarse mosaic, especially if it has inconstant photocell performance, produces images
of small letters which do not contain enough
information for recognition. See, for example,
the sixth character, an e, in Fig. 2b. The large
letters, however, do not present this problem.
However, both of these disadvantages can be at least
partially overcome; the first, by various techniques
to be described later; the second, by using a mosaic
with more photocells.
BASIC METHOD
Of prime importance in this method is the way in
which pattern discrimination is provided. The best
way to describe the process is by example.
We start with a 10 X 15 photocell mosaic (this size
being chosen because of immediate availability), the
elements of which are related to one another as 75
randomly chosen, exclusive pairs. Fig. 1a shows the
mosaic and two such randomly chosen pairs (1 1 12 and
2 12 2 )' Images, letters for example, projected on the
226
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
~
~
II
w/-;//.
1'" ~
""'-
ADDRESS
GROUP
*1
~.
'l/ Z
{
_._.
~__
10
01
00
~
D
~2
%~ ~ ~~
~ %~ ~
~ ~~ % ~
~ ~'
,
~v
%'
/
,
/;'/
~
~
r0r;:
21
~ ~~
/:
;;; v,
r
~ l//
'/
;/ ~~
r0
//;; '/ / /
'
,
~ ~DRESS
ADDRESS
GROUP
11'2
ill
10
01
{ 00
~"
10
~I
Fig. 1 (b)-The system learning the letter I in a central position.
Only two of the 75 pairs are shown.
IIJ.
Ill"
10
01
.... 1
D
ADDRESS
GROUP
I
10
GROUP
21
i"- --.
QQV
--~]
~.-
*2
D
~~
~
~ .!.L
~
~
~
""'~~~'-......~~~~.""''-.....
Fig. 1 (c)-The system learning the letter I in another position. Note
that the memory experience shown in the previous figure remains.
~~ ~~~
~ ~ %~ ~
~ ~ {0 ~ §:
~~ ~~~
-
II
~ ~ ~ 121 ~ 21
I
I
I.
----
12
11'1
v/. Z 'l/. v/. >...
~ 22
~
~
~v
l0 ~r;~
ADORESS
GROUP
""'~~~~~~~~~~
~
7:v
~%
~ %~
I
~0 ~;: Y-
22 ~h ~ ~~
V, 0,
~
f"..
I---l
~
~
~
~~
~
~
'l"h '/;;'l"h%
Fig. 1 (a)-The photomosiac and two of the randomly chosen photocell pairs. The four digital groups to the right are the four possible
sta tes of each photocell pair.
~
~
~
!..
~ 22
~~~
~~~~~~~~~~~
II
~
~~ ~ ~%
~~ ~ ~%
%~ ~
% [12
"'- ~2-'1
""'-
'l/ 'l/ '/: 'l/
~
'/Z 'l/ 'l/. '/.
121
V/
I
10
01
00
~~
~
~ ~ ~ ~Y-
'//
~0; ~ ~v.
t:0~ ~ ~v.
~ 12
12
~
~
~~ ~ ~v.
II
I
~ II .
- - ] ADDRESS
GROUP
~ 22
"'2
~
22
~
~ II
~
~
~
'l"/
~~ ~ ~
~
21 ~
~
~~ III ~~
'I
~ %%~ ~
~~~~
~ ~ ~ ~ .-> 1~2
~ •. '---1
~~~~ ~
~ ~~ ~ ~
I~ ~ ~ ~ ~ ~ 12
~ %~ % ~
0~ f% ~
'/:'/: 'l/ ;/h
ADDRESS
GROUP
.... 1
ADDRESS
GROUP
""2
{"
l2.~
~~
~
""'~~""'~~~~~~~
Fig. 1 (d)-The system learning the letter I in a third position. The
check marks to the right show all possible combinations of these
two photocell pairs for the letter I.
mosaic will produce characteristic patterns, examples When an image is on the mosaic, each pair of photoof which are shown in Figs. 2a and 2b as they appear cells (the members of which are ordered for this puron IBM cards. For computer convenience, the light pose) will represent the light values of the image as
values of an image on the mosaic are rendered in a a two-bit number. Each pair of photocells has therebinary system which treats dark as 1 and light as O. fore four possible states - 00, 01, 10, and 11.
- --
- ---- ----
=-==~;~-==
Fig. 2(a)-Hand-block print as it appears on IBM cards.
(Top-A, C, Ej Bottom-N, M, H.)
Fig. 2(b)-Handwritten script characters as they appear on
IBM cards. (Top - w, 1, OJ Bottom - s, r, e.)
227
Bledsoe and Browning: Pattern Recognition and Reading
In the memory matrix of the computer, a 36-bit
computer word is assigned to each state of each pair,
giving four words for each photocell pair or 300 computer words for the 75 pairs. Furthermore, each bit
position in the 36-bit computer words is assigned a
pattern nomenclature. The sequence used in our experiment was:
Position
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ... 35 36
Nomenclature
123456789
abc d
e ... y
z
This nomenclature sequence will hereafter be referred
to as an "alphabet."
In order to demonstrate how patterns are
"learned," we will use as an example the letter I.
First, a letter I is projected on the photocell mosaic
(Fig. 1b). Its image on the mosaic produces one of
the pair states (00, 10, 01, 11) for each of the pairs,
depending upon the amount of light falling on the
pair. Since all 75 pairs are involved, the resulting 75
states address 75 words in the memory matrix. For
each word addressed, a binary 1 is entered in the
nineteenth position, the position corresponding to the
letter being learned, I. Obviously, if the letter A were
being learned, a binary 1 would be entered in the
eleventh or A position, and so forth. The process described constitutes the learning of a single letter I,
but whole series of letter 1's, differing in shape or
position or both, can be learned. For example, Figs.
Ib, lc, and 1d show the same I being learned in different positions, while Fig. 3 shows a case in which
two G's have been learned.
~:.~~T~I--
1_2_3_4_56_7_8_9_A_B_CD_E_F_GH_I_JK_L_M_NO_P_Q_RS_T_U_V_W_xv_z
2ND
PAIR
01
10
I I I - -______~------------------
\~~~{
75TH~~1
PAIR
10
II
~--~--------~------------
Fig. 3-The m,emory matrix with the characters B, G, and 5
learned. Note that two G's have been learned.
Since not all the letter 1's will be in the same position as the first, some different computer words will
be addressed. That is to say, there is a degree of individual character variability. However, no letter I
or combination of 1's will normally address the same
75 computer words as, say, a letter A would. This is
a key point: the very shape of a character, such as the
letter I, forbids certain states for certain pairs. The
existence of these forbidden states lies at the heart of our
method, for without them the logic would saturate. In
sum, different patterns have different forbidden states
and consequently score differently.
Now, suppose that we have taught the logic several
alphabets, proceeding for each character as for the
letter I above. We can then identify a specific unlearned character, an A for example. A letter A is
"read" by imaging it on the photomosaic. Its image
will address the 75 computer words in the memory
matrix to correspond to the active states of the 75
pairs. Identification of the specific pattern in question is made by comparing the unknown image with
the previously learned characters. In practice this is
done in th-e following way:
(1) The binary l's in position one (the position
corresponding to .:.) are added up for all of the
75 computer words addressed by the unknown
pattern. The score obtained shows the similarityof the unknown pattern to the.:. pattern.
(2) The same process is repeated for the other 35
positions, with the result that 36 numerical
scores are obtained.
(3) These scores are compared by the computer,
and the highest score wins. That is, the unknown pattern is identified with the character
occupying the position scoring highest. If there
is a tie for highest score, the computer arbitrarily selects one of the highest scores as the
winner. Note that the highest score possible
is 75.
Fig. 4 shows an example of scoring for hand-block A
and T. Fig. 5 shows scoring for much more highly
variable patterns, namely, handwritten a and t.
It will be noted that if an image corresponding
exactly to the unknown image had been learned before by the matrix, a score of 75 would be made at that
position. Again, if by learning several similar patterns
(A's, for example), all of the pair states now being
addressed had been learned, a second 75 would be
made. However, in most cases, an unlearned char~c
ter will not make a perfect score. The degree of simi75
70
65
~
50
45
40
35
30
25
20
15
10
5
0
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
[I]
I II
II I
-123456789A8CDEFGHIJKLMNOPORSTUVWXYZ
O~~~~~~~~~~~~~~~~~~
Fig. 4-Comparative scores of hand-block letters-
228
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
75r---~--~~--"~~--------~----~
100
50
80
z
i=
Z
o
.t
25
75'
I
Z. 3 q.5 , 1
'" ~ "
860
u
IIJ
a::
.&
a::
IIJ
Q.
20
50
25
A
o
B
ALL 5
E
ALPHABETS
Fig. 5--Comparative scores of handwritten letters.
larity is measured by comparing the magnitude of
the various scores with a perfect score of 75. Discrimination is defined as the difference between the score
of the correct character and the next highest score.
It can be seen that what actually happens in this
process is that the images, both those learned and
those being read, are transformed into a new space
(the memory matrix) and are there compared for
identification.
Fig. 6-Comparisons of the percent recognized for hand-block print
read with different n-tuplings: n = 1 (hatched bars) and n= 2
(solid bars). Note that when all five alphabets are learned together
th~ percent for. n=2 improves. In other words, for n = 2, th~
abIh~y to read Improves with additional learning in the memory
matrIx.
100r-------------------------------~
-
{ - - - 5 ALPHABETS
80
z
Q
I-
~
ou
60
w
a::
I-
~40
u
------0
B
5CL
20
LOGIC EXPANSION AND MANIPULATION
I ALPHABET
MEMORY MATRIX CONTENT
0L---~----~----~-----4L---~L---~
PHOTOCELL n-TUPLES
Our studies and experiments moved outwards from
the basic method to include a variety of modifications Fig. !-C.omparison of percentage recognition of hand-block print
With dIfferent n-tuples. Five alphabets (labelled ABC D and
and variations. An attempt is made below to evaluE) are considered singly, and then together.
""
ate each variation in terms of its final effect. It should
be noted that the combination of two or more of the
methods to be described results in substantial in- follnd when the matrix is taught more than one position or more than one example of a pattern. The
creases in correct readings.
scores will improve if n = 2; for n = 1, they will not
improve and will probably deteriorate. Figs. 6 and 7
Different Photocell Groupings
In the examples cited, the photocells were grouped illustrate this characteristic with respect to five alphaas 'exclusive pairs. However, it is obviously possible bets learned separately and then in combination.
to use n-tuples in which n has any value from 1 to Marked improvement in the reading of this message,
150. Let us begin by comparing the system employ- which was written in hand-block print, was achieved
ing photocell pairing (n = 2) with a system in which when n = 2 rather than n = 1. For the five alphabets
n = 1. In the latter case, each individual photocell learned separately, the average percent of recogniaddresses only two computer words, since its possible tion with n = 1 was 56.12 percent; for n = 2, 54.01
states are 0 and 1. The difference in the behavior of percent. But for the same five alphabets learned tothe systems is striking. If we re-examine Figs. 1b, 1c, gether, the percentages are 46.42 for n = I, and 67.63
and 1d, we note that in learning several images of for n = 2. (See also Figs. 8a and 8b.)
Remembering that n can equal any number from 1
the letter I, with n = 1, every single photocell would
to
150, we can ask what effect is produced when
exhibit the values 1 and 0: this is so because the posihigher
n-tupling is used. The problem of pattern
tion of the letter I changes. In other words, unless
recognition
with a multi channelled system, such as
the image on the mosaic is held within narrow limits ,
the
one
simulated
for discussion here, has traditionthe memory loses most of its discrimination value
ally
been
approached
from one of the two extremes
with n = 1.
that
is,
n
=
1
or
n
= 150. Consider the formul~
We can say then, that position is very critical in
N
the case of n = 1, and that it has less importance for
Sn X - X C = L
n = 2. A direct consequence of this difference is
n
'
Bledsoe and Browning: Pattern Recognition and Reading
where
S = the number of operational states of the photocell. In the case being considered S = 2, for
the possible photocell states are 0 and l.
n = the parameter for n-tupling.
N = the number of photocells.
C = the number of categories of patterns learned
and read (36 in the previous examples).
L = the number of storage sites in the memory
matrix.
The factors held arbitrarily constant in our experiment were n = 2, N = 150, and C = 36. The traditional cases, as mentioned before, have involved
n = 1 and n = N = 150. But the former has been
shown to deteriorate or at least not to improve appreciably with learning. The latter, on the other hand, requires a prohibitively large memory matrix (36 X2 150 ,
using the same values as above), although its reading
ability would be perfect if enough learning experience
could be provided.
Let uS summarize concerning these two extreme
conditions. If n = 1, there are no forbidden combinations and therefore the memory will saturate with
the learning of successive characters which vary in
n: 5
o
W
N
i
229
size, area, shape, or position. Such a logic has, consequently, an extremely limited use. If n = 150,
saturation is impossible. But, even apart from the
impossibility of having 2 150 computer addresses available, images being read successfully would be restricted to exactly those that had been learned before. This logic, then, has even more severe limitations.
Our method avoids these several disadvantages by
concerning itself with intermediate values of n, values
which provide the learning advantages of a large exponential matrix but which retain a memory matrix
more comparable in size to the photomosaic matrix.
For example, with n = 2, the formula for the logic
used gives:
22 X 150 X 36 = 10 800
2
'
The number of bits in the memory matrix for the
simplest case of a system not position sensitive, under
these conditions, is therefore 10,800.
Let us introduce another quantity, M, which will
be the number of photocell n-tuples utilized in a given
experiment. While M will normally be given by N In,
larger M values can be obtained by non-exclusive
n-tupling of the photocells. We will have more to say
about the non-exclusive cases later.
In any event, it is obvious from the formula that a
larger memory matrix can be utilized if any of the
variables are increased. During the course of our
experiments, we used the following values:
n
= 1, 2, 3, 5, 8
M = 30, 50, 75, 150, 128, 256, 512, 1024
(J)
a:
w
ID
~
C = 10 and 36
o
Z
>W
..J
135711
135711
NO
OF
36
135711
CHARACTER
135711
ALPHABETS
Fig. 8(a)-Scores made on handwritten script letters, showing that
for larger values of n, larger amounts of learning are useful.
155
140
o
z
-- ,
/
."'.\ ~
~
.....
....I.········
/'
\
",.
.../;/.
~,,"
.
'.
--,
,
\.
"".'~,.
\..
~
..
o
~ 95
(/l
\ '..
'\
0:
1&.1
n"5
~''"'~n"3
'n02
~ 80
...J
65
..............., ....,.,.. ,.,
~L-----~IOO~----~20~0.-----~DO~----~400
LETTERS AND NUMBERS LEARNED
Fig. 8(b)-Material of Fig. 8(a) presented in different form.
The experimental data suggest that a greater amount
of logic produces better discrimination. The primary
effect of varying n is that as n increases, the percent
of recognition increases with increased learning (Figs.
7, 8a, and 8b). However, a balance must be preserved
among the various parameters in order to utilize to
best advantage a given amount of logic and to minimize computing time.
Non-exclusive n-tupling
Some experiments were made in which non-exclusive n-tupling was used for the photocells. The number of n-tuples (M) used could in these Cfases have
any value. Tables I and II show that non-exclusive
pairing resulted in some improvement in the percent
of characters recognized. But this improvement was
at the expense of more storage space and longer computing time. We feel that a larger gain in percent
recognized can be realized, for the same amount of
storage and same length of computing time, by increasing the number of photocells eN) and continuing
to use exclusive n-tuples. In other words, we see no
real advantages in non-exclusive grouping.
230
1959 PROCEEDINGS OF THE EASTERN JOIf{T COMPUTER CONFERENCE
TABLE I
PROGRESS IN READING HAND BLOCK PRINT
n-Tupling
Exclusive
Non- Alphabets
exclusive Lea.rned
1
5
1
3
2,3,5
2,3,5
2,3,5
2,3,5
3
2,3,5
2,~,5
1
1
5
3
2
3
1
4
1
1
1
Manipulation
Percent
Read
None
None
None
None
Probability
Distribution
None
Rotating Origin
Rotating Origin
Context
Context-Positioning
39-72
28-66
46
78
77-84
80-84
80-85
88-92
96
94-100
98-100
TABLE II
PROGRESS IN READING HANDWRITING
n-Tupling
NonAlphabets
Learned
Exclusive exclusive
Scores are obtained for each value, and the maximum
score made by a character in any of the positions is
chosen as the identifying score. This program involved a considerable amount of computer time, and
is of interest mainly in connection with the possibility
of simulating conditions for "servoing" the "eyeball."
Such a feedback system appears feasible, since effective score criteria were found.
In a variation of the positioning program, the
characters were all relocated by the computer to the
upper left hand corner Qf the rectangle. This positioning, combined with the rotating-origin program
just described, gives the maximum probability of reclaiming position-dependent data. This combination
provides the largest increases in effectiveness for the
n = 1 cases, those cases which we have seen are most
sensitive to position. Typical increases in percent
recognized for hand-block print with these techniques
are:
Original
Positioning
Rotating origin
89
84
80
90
72
88
Distribution Processing
A method of processing the data obtained from the
pattern scores was tried which was based on the enNone
26.14
1
1
tire scoring pattern rather than upon the maximum
None
30.68
1
3
25.00
score only. The principle involved becomes clear at
None
2
1
None
33.64
2
5
once if Fig. 5 is re-examined. Note that the sets of
None
34.55
5
5
scor-es with respect to the previously learned letters
Distribution
43.84
5
3
are quite different for a and t. These different values
None
24.55
5
5
are apparently consistent in their differences. For exPositioning
53.15
5
5
ample, t scores high for b, while a scores low for b,
11
None
50.00
5
and so forth.
Positioning
58.56
11
5
The procedure is first to teach the memory matrix
Rotating Origin
60.00
11
5
several
alphabets as a primary experience. Scores
94.32
Context-Positioning
11
5
made by one or more additional alphabets, constituting a secondary experience, are then averaged to give
Positioning
a score distribution typical of each character. An unknown
pattern is compared with the memory matrix
A procedure for pre-positioning characters for
in
the
usual
way to obtain its distribution of scores.
learning and reading by rotating an origin was atThis
distribution
is then compared with the typical
tempted and found to be profitable in special cases.
This rotating-origin technique is useful for digits and distributions and the one most similar to it is chosen.
for print, but will not work with handwritten script. For convenience, all of the scores were normalized,
That is to say, if a character or pattern is separate so that the sum of the scores in each distribution was
and distinct, it can have an origin rotated with re- one. Comparisons between two distributions were
spect to some reference. Handwriting (as contrasted made in these experiments by summing the absolute
with the separate handwritten characters which we values of the differences of the corresponding scores.
used) has continuity, and there is no obvious origin It might well prove useful to employ a correlation
from which to start. Some method for separating technique in which a sum is taken of the products of
handwriting into its components would be required corresponding scores, but this has not yet been tried.
As an example of results, in one case in which handbefore the origin of such components could be rotated
written script characters were being read (n = 5, 3
profitably.
For each character an origin is arbitrarily defined. alphabets learned), we found:
The character is then successively repositioned about
Undistributed 32.3% recognized
this origin in the following sequence of x, y values:
Distributed
45% recognized
0,0; 1,0; 1,1;0,,1; - 1,0; -1, -1; 0, -1; 1, -1; 2,0; etc.
Manipulation
Percent
Read
Bledsoe and Browning: Pattern Recognition and Reading
A final approach in this effort was to introduce ten
arbitrary shapes for the primary experience (Fig. 9).
IIIII
.1 •••
After these were taught to the memory matrix, three
alphabets were compared with the matrix to obtain
a ten-component distribution analogous to the 36component bar graph of Figs. 4 and 5. The three
ten-component distributions were averaged. New
alphabets could then be read by the distributioncomparison program. For handwritten script the results of this program were:
Undistributed
Ten-Component Distribution
32.3% recognized
51% recognized
This program was novel in that it involved two
steps of disorder; that is, two arbitrary operations random pairing and comparison with arbitrary configurations - were performed on patterns before
attempting to read order out of them. It is also important to note that by using only 10 shapes instead
of 36, a considerable saving in computer time is
realized.
Probability
The method of reading characters described previously utilizes a memory matrix which is taught by
a given set of experience patterns. Another method
was tried in which the contents·of several such memory matrices were averaged to obtain a "probability"
matrix which was then used as the memory matrix
in the reading phase. The memory matrices used in
CHOICE NUMBER
1
n
]I
m
12"
:lr
MEAN
CT
HANDWRITING
2
' 31%
27%
32%
35%
35%
32%
3.0
5
36%
33%
33%
37%
36%
35%
17
78.2%
772%
778%
80.1%
78.4%
1.0
HAND BLOCK PRINT:
2
-,
78.5'
the averaging can be taught by different sets of experience patterns. An interesting (but not very successful) special case is one in which each of the
matrices being averaged is taught only one alphabet
of experience patterns.
In the few cases tried with this method, the percent
of handwritten characters recognized was increased
as follows:
Original
Probability Matrix Used
Fig. 9-Arbitrary shapes which were taught to the system as a basic
distribution pattern for the subsequent reading of alphanumeric
handwritten characters. Each shape was learned in the position
shown and also in several positions resulting from lateral displacement.
Fig. lo--Percentages of recognition for five different
choices of random n-tupling.
231
28% recognized
52% recognized
Certain variations of this "probability" method
will undoubtedly yield some increase in percent
recognition.
Discrimination Criteria
The scores obtained for each pattern read by any
of the described methods lend themselves readily to
the establishment of discrimination criteria. That is,
if the standard of minimum margin is not met for a
given image, a secondary program can be evoked
which utilizes one of the higher (and probably slower)
logic treatments for higher resolution and/or discrimination. Such a program would give the computer a second, and "more careful look" at a pattern
which was not clearly recognized on the first trial.
Randomness
Since the elements of the photomosaic are related
to each other by randomly chosen n-tuples, it was
decided to test the sensitivity of reading ability to
changes in the particular organization used. The
random (actually pseudo-random) n-tuples were generated by the following program. First a random
permutation, k(I), k(2), ... , k(150) of the numbers 1, 2, 3, ... , 150 was generated. Then the elements of the mosaic EEl, E 2 , ••• , E 150 , were related
in this manner:
(Ek(l) , E k (2) , ••• , Ek(n) , (Ek(n+l) , ••• , E k (2n) , •••
~
(E k (150-n») , ••• , E k (150»).
The test was made by using five different randomly
chosen permutations to read the same set of patterns.
The results are shown in Fig. 10. Although admittedly the sample was rather limited, indications
are that the pereent recognized is fairly insensitive to
the variation, especially when the pre cent recognized
is high.
Context
Another method to extend the basic technique deserves special attention, for it produced the highest
percentage of correct readings. It is identification of
letters by word context, and it operates as follows:
1. Establish the length of an unknown word by
counting the number of characters between
spaces.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
232
.
7 I Cf a -t c t:l.ll.J.."
..J.
m.
..,
)IZ
()" ..p l1rned was increased?
tion. This is going to be a real problem on this. Very few people hand
print. The only ones I know are people who go to Radcliffe; they do Mr. Browning: In answer to the first question, it seems impossible
tend to hand print. This is as in speech recognition; in identifying that wth the present definition - which we had with 150 photocells
words you are aware that segmentation is the real primary problem. - that we could recognize the handwriting of different individuals.
After all, that number of photocells is approximately one-tenth of
M. Jacoby (Remington Rand): What is the spacing of the individual the number that a gnat has. If the number were greatly increased,
heads on the reading element?
we might well be able to distinguish the handwriting of different
individuals.
R. P. Niquette (Ramo-Wooldridge): What kind of character rates are
In answer to the second question. I would explain the percentage
to be expected from the system you described? Failure rates?
recognition increase as follows. If the memory matrix has learned
Mr. Evey: The area of the check that has to be read is about a half only one alphabet, any attempt to recognize an unknown character
inch across the bottom of the check. Actually in the IBM system will be essentially pattern-matching with a complete position sensithere are 30 tracks which cover this half inch and you get it down to tivity. If the memory-matri~ has learned a number of alphabets, the
10 tracks by tying every tenth track together, so you have three probability is increased that an unknown character will match a
tracks together. So you actually have a positioning problem in the similar pattern previously learned in this position. The novel feature
matrix. This is mentioned in the paper. I didn't want to take time to of our type of memory-matrix access is that the learning of a few
discuss this in the talk. So you have 30 tracks covering this half inch subsequent patterns does not destroy its memory of previously
and each track ends up about 17.5 thousandths wide. There is a dead learned patterns.
G. A. Barnard (Ampex): Please expand on the contextual positioning
aspect of your method.
238
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
A Computer Analytic Method for Solving
Differential Equations
LEO HELLERMANt
INTRODUCTION
I
N RECENT years, numeric analysis has been
claiming an increasing share of overall mathematical research activity. The reason for this is
apparently the need to have answers - numeric
answers - to problems of modern technology, along
with the development of the stored-program digital
computer for carrying through the computations of
numeric methods. But this emphasis on numbers is
also an indication of the attitude of problem solvers:
to use the computer, use numeric methods. And yet
these methods are not always adequate. It may be
more important to know how x depends on other
variables than to know that x = 3.
The inadequacy of numeric techniques for the solution of differential equations is highlighted by the
following engineering problem: In the design of a
transistor switching circuit for a high-speed computer, we wish to know the output-current level at
a particular time after the start of an input pulse.
This information is contained in the solution of a nonlinear differential equation, which can be solved very
nicely by numeric methods on a computer in, say,
ten minutes. In evaluating the reliability of this circuit with respect to component deviation and drift,
we want to know the statistical distribution of outputs. A simple method for finding this is synthetic
sampling, or monte carlo!; but at ten minutes per
solution, this may not be practical. However, monte
carlo is known to be practical in estimating distributions associated with analytic expressions. This suggests that we first obtain the analytic solution of the
differential equation, and then apply monte carlo to
the solution. The methods are compared schematically in Fig. 1.
(I)
NUMERIC METHOD
r
L
.
Jdata
01 f
Ldifferential equation! - . - - numeric $ u 101'1
.
J
-
(2) ANALYTIC METHOD
r
differential equation --+ [analytic SOlution} ---+-- numeric solution
~ata
J
Fig. l--Comparison of numeric and analytic methods of
solving a differential equation many times.
t Product Development Laboratory, Data Systems Div. IBM,
Poughkeepsie, N. Y.
1 L. Hellerman and M. P. Racite, "Reliability Techniques for Electronic Circuit Design" Trans. I.R.E. PGRQC, Sept. 1958, pp. 9-11).
In the numeric method ((1) in Fig. 1), we must
solve each case anew, starting with the data and
differential equation. In the analytic method ((2) in
Fig. 1), enough information is contained in the solution, so that we need solve the differential equation
only once, and evaluate the solution for each case.
Since a major portion of machine time is taken up
with solving differential equations, there may be
problems in which (1) is not practical and (2) is, provided (2) can be carried through by the computer.
The purpose of this paper is to call attention to a
basic principle of analytic technique on a stored-program digital computer, and to illustrate this principle
by a computer algorithm, and "address calculus,"
for finding solutions of ordinary differential equations
by analysis. We also describe the implementation of
this algorithm in an IBM 704 program. We see no
reason why the same technique might not be applied
to a host of other mathematical problems.
THE PRINCIPLE AND GENERAL ApPROACH
The principle of numeric computation in a storedprogram digital computer is well known: numbers are
represented by the contents of storage cells, and computation is accomplished by arithmetic manipulation
on these contents. Functions are represented by a
finite table of numeric values. The principle of analytic computation may be stated thus: algebraic
symbols are represented by the locations of storage
cells, and analysis is accomplished by manipulating
addresses. Functions are represented by machine programs. An algorithm for the analytic solution of a
problem is an assignment of the correspondence of
algebraic symbols with addresses, and a description
of the way the addresses are manipulated.
In the description of the following programs, in referring to the address of some location corresponding
to some symbol S, we will say "address S." Address
and symbol are equivalent, and we may use the symbol to designate the address. On the other hand
"address of S" refers to some other location and
address, say T, which has the address S as part of its
contents. Thus the address T may be the address of S.
Our approach to the analytic solution of ordinary
differential equations will be to develop the Taylor
series expansion of the solution. If the differential
equation is
y(k)(X) = f(x; y(O) (x) , ... , y(k-ll(X»
(1)
Hellerman: Solving Di,fferential Equations
then the formal solution is
y(x) = yeO)
+
y(l)(O)x
+
y(2) (0) x
2!
2
+...
(2)
where the yU) (0) for j = 0, ... , (k - 1) are assigned
initial values, and for j = k, k + 1, ... are determined
from f and the derivatives of f.
Thus the heart of the problem is to develop analytic differentiation on a computer. In this connection we mention the work of H. Kahrimanian2, and
the LISP Programming Systems. However, our approach is a bit different from both of these, being a
close parallel to differentiation "by hand". A recently
reviewed Soviet paper4 appears to contain material
quite similar to the work described here. The
SHARE routine PE PARD5 for differentiation and
partial differentiation of rational functions is a prototype of our present program. Recall that the function to be differentiated is, in the computer, a stored
program. PARD examines this program as a college
sophomore examines a function to be differentiated,
and when it finds it to be the sum of two parts, it
applies the rule: the derivative of a sum is the sum
of the derivatives. Or, if it finds a product, it uses
D(uv) = uDv + vDu, and similarly for other differentiable combinations. Eventually, the derivative of
a function is expressed in this way in terms of the
derivatives of constants and the independent variable, and the differentiation process is complete. The
problem in doing this on a computer is dping it in a
uniform and orderly way, so that the method may
be applied to arbitrary differentiable functions, and
so that the results of the differentiation of each term
can be combined in the end to one expression (program) for the derivative.
239
unary. Let the symbol a * b have this meaning: * is
a binary or unary operation. If * is binary it operates
on a and b; if unary it operates on a, and b is ignored.
Thus a * b may be, for example, a + b, a + b, a b , or
log a, or sin a. We will say a mathematical expression
is a finite dendrite if it is composed by a finite number
of binary and unary operations from a set of starting
terms. We call a starting term an elementary term, or
an end: it is not composed from other terms.
For example, consider the dendrite y = (x + a)b sin x. Its branching nature is shown in Fig. 2.
Fig. 2-The dendrite y = {x
+ a) b -
sin x.
The elementary terms are a, b, and x. The dendritic
terms are, besides y itself, (x + a)b, x + a, and sin x.
Note that the dendritic picture of y may serve as a
flow chart for a program for its computation. First x
is added to a, and the result is multiplied with b.
Then x is operated on by some sine routine, and the
result of this is combined by subtraction with (x + a)b
to give y. Thus a stored program for evaluating a
function is essentially a sequence of binary and unary
operations, starting with operations on elementary
terms. That is, a program is a dendrite.
Blocks of l's and 2's are a convenient notation for
the branches of a dendrite. If al . . • an is such a
block representing some dendritic term, (a, = 1 or 2),
then, from the definition, al •.•. an = al • • • anI *
al . • . an 2. The branch designations of the above
example are shown in Fig. 3.
THE DENDRITE NATURE OF FUNCTIONS
In this section, we examine a stored-program aspect of functions. Some notions will be defined which
will facilitate the description of the differentiation
algorithm.
A binary operation is an operation on two quantities. Addition, subtraction, multiplication, division
and exponentiation are binary. Unary operators operate on a single quantity. Exp, log, sin, and cos are
2 H. G. Kahrimanian, "Analytical Differentiation by a Digital
Computer," M. A. Thesis, Temple University, May 1953.
J. McCarthy, "Recursive Functions of Symbolic Expressions and
Their Computation by Machine" Quarterly Progress Report No. 53,
Rese8lrch Laboratory of Electronics, M.I.T., April 15, 1959.
4 L. V. Kantorovich, "On Carrying Out Numerical and Analytic
Calculations on Machines with, Programmed Control," I zv. Akad.
Nauk Armyan. SSR., Ser. Fiz.-Mat., Nauk 10 (1957), No.2, 3-16.
See review No. 4360 by J. W. Carr, III, in Mathematical Review,
June 1959.
5 M. R. Dispensa and L. Hellerman, "Differentiation and Partial
Differentiation of Rational Functions" P E PARD, SHARE distributed Program D2-445, March 18, 1958.
3
-{2 --~,
I
y
-{"
121
-{
122
Fig. 3-Branch designations for the dendrite
y = (x + a) b - sin x.
A set of branches of the form
where the last branch is an elementary term, will be
called a chain. All the chains of the example are
1,
1,
1,
2,
11
12,
12,
21
121
122
A finite dendrite has a finite number of chains.
THE DIFFERENTIATION ALGORITHM
Let us suppose we are given a y-program, that is,
a stored program for computing y. We wish to extend
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
240
this to a program for its derivative, a Dy-program, by independent variable, or an initial condition y(J) (0),
adding additional instructions. The block of storage j = 0, ... , (k - 1). Thus D(ll ... 11) = A n ... ll1
for the Dy-program will include the block for the is known, and we store this in L(ll ... 111).
y-program. Since y is a dendrite, y = 1 * 2 and
At this point we have traversed one chain of the
dendrite y. We may now examine the I-cells for some
(3) deferred differentiation instruction, and proceed with
where Al and A2 are functions determined by the the differentiation of this new term, until another end
operation * and the branches 1 and 2. That is, is reached. Continuing in this way, all chains will be
Aa = Aa (*, 1, 2) where a = 1,2. These functions are completed, for there are a finite number.
It is clear from (3) and (4) that Dy is simply the
specified in Table 1. It may happen that an Aa is the
number 0, or 1, or some function which is known to sum of all products of A's, where the subscripts of
exist in the y-program. This is the case for y = u + v the factors of each product range over a complete
and y = exp u, and in these cases it is unnecessary to chain. If A a1 ''' aj = C iJ , where i stands for the i-th
place any instructions in the block reserved for the chain, we may write
Dy-program. If an Aa is not of this type, say Aa =
k(i)
-u + v2 , then we do construct the program for this
(5)
Dy =.L: IT Cil CiZ ... Cij
i =1 j =1
function and place it in the first available locations
in the Dy-program block. Whether Aa is constructed where i ranges over the set of chains of y, s in numor not, we save the addresses A 1 and A z, in locations ber, and where Ctk(i) is the derivative of the end of
L(1) and L(2). Since we can only differentiate one the i-th chain.
term at a time, we also save the instruction to find
Thus the Dy-program is completed by construcD(2), in a location 1(2).
tion of a program for evaluating (5). This can be
done because the addresses A a1 ... an are at hand in
the locations L( al . • • an).
TABLE I
The algorithm as it stands requires excessive
storage. To differentiate any function composed with
n operations, we should allocate 2n locations for
I
u *'v
Al
A2
storing the addresses A a1 ... an' for there are as many
of these as n-blocks of l's and 2's. But consider the
v
1
1
U+ v
situation when the first chain has been completed.
-1
v
1
u-v
v
u
U'v
v
At that point we know
8
u+v
1 + v
u V , v constant
exp u
In u
sin u
cos u
VU V
-
1
exp u
1 + u
cos u
-sin u
-u + v2
V
0
0
0
0
0
v
0
0
0
0
Dy = AlAn . .. All .. . 1lA ll ... 111
+ AzD(2)
+ AIAlZD(12)
+ ...
+ AlAn ... All ... lAll ... 12D(11 ... 12)
(6)
We may now go on to find D(1). Suppose 1 is The addresses of the A's and D's are consecutive
cells in three blocks of storage, called the A I-block,
dendritic and 1 = 11 * 12. Then
Az-block, and I-block. The storage arrangement is
D(1) = AnD(11) + A 12 D(12)
shown schematically in Fig. 4. The lines in this figure
indicate the formation of the products in (6).
The functions A n and A lZ are constructed as A 1 and
A 2 , again by Table I, the addresses An and A lZ are
AI-Block:
AII ... '
II
11 ..• 11
11 ... 11'
ATA 1 " ' 1
1A
-A
stored in L(11) and L(12), and after storing the instruction to find D(12) in 1(12) we continue to find
A2 -Block: A2
AI2
... . AII ... 2
All ... 12
D(11).
,L
In general, if
D( al
••.
al . . .
an is dendritic, then
an) = A a1 ... anlD( al • . . a n1)
+ A a1 ... an2D(al ... an2)
I-Block:
(4)
The eoefficients are constructed if necessary, and the
addresses A a1 ... OIn+l stored in L(al ... an +l); the instruction to find D(al ... a n2) is saved in I(al . .. a n2);
then we go on to D(al ... a n1).
Eventually, since y is finite, we come to an elementary term, 11 ... 11. This will be a constant, the
0(2)
0(12)
...
0(11. .. 2)
0(11 ... 12)
Fig. 4-Contents of AI-Block, A 2-Block, and I-Block of storage,
at completion of a chain.
Instead of continuing by completing another chain,
construct the program for the product of terms of
the first chain just completed, and place this program in the Dy-block. Then the addresses All ... 11
and A 11 ... 111 are no longer needed. We may replace
A l1 ... 11 in L(11 ... 11) of the Arblock by A 11 ... 12
Hellerman: Solving Differential Equations
and proceed to find D(11 ... 12). The storage arrangement will now be as shown in Fig. 5.
.12 -
TABLE II
UP-DATING OF Dy-PROGRAM, At-BLOCK, A 2-BLOCK, AND I-BLOCK
0(11 ... 12)
Dy-Program
New Terms for
Construction of
Al and A2
Function
Code at
K= Location K
0(2)
0(11. .. 2)
o
Fig. 5-Contents of storage blocks after down-dating
of Fig. 4 arrangement.
The differentiation D(11 ... 12) may generate
further terms in the AI, A 2 , and I-blocks. Whenever
an end is reached, we form the product for the completed chain, replace unnecessary A I terms by their
corresponding A2 terms, and then continue with differentiation of the next term, indicated by the last
non-zero address in the I -block. This process of replacing terms no longer needed by terms of the next
chain to be completed will be called down-dating. U pdating refers to the process of adding new addresses to
the AI, A2 and I-blocks, upon examination of each
operation, as prescribed in Table I. These new addresses are stored in the appropriate blocks, and
nowhere else. Since two cells are required for the
storage of the A's from each operation, it is now only
necessary to allocate 2n storage cells for saving the
A's of any n-operation function.
AN IBM 704
PROGRAM
A main feature of our IBM 704 implementation of
the above algorithm is the pseudo-code used to
specify functions. The function A = B + C in 704
instructions would be
CLA
ADD
STO
241
PZE u, ,v
PON u" v
PTWu"v
PTHu"v L
L
UV
MONu" v L
L
L
exp u MZEu,,1
In u MZEu,,2 L
sin u MZEu,,8 L
cos u MZEu,,16 L
u +v
u-v
u 'V
u + v
Al
A2
I
None
1
v
1
-1
None
1
v
u
None
v
v
L
1) v
- (L
+O:MONv"MFLlt
+ 1: PTW K" L
0
0
0: PON v , , FLlt L+2
1: MON u , , L
2: PTW v, , L + 1
None
K
0
0
L
MON u , , MFLlt
0
0
L
MZE u, , 16
0
0
-L
MZEu,,8
0
0
+
+
+
+
tMFLl is the address of -1; FLl is the address of 1.
find Du. In the flow chart of Fig. 6 "new K" refers
to u.
The 704 flow chart is clarified by a description of
the roles played by certain blocks of storage.
(a) Constants block. All constants are given addresses of storage locations in this block.
(b) Initial conditions block. This contains the locations yU)(O), j ~ k - 1, as consecutive storage cells.
When an end y(i)(O), j < k - 1, is recognized, its
derivative is the address yU+l)(O).
(c) Variable of differentiation. This is a single
storage cell.
START
B
C
A
But we do not actually need B in the accumulator,
for we do not really intend to add numbers. The program is used only to recognize that Band Care
composed by the binary operation addition, to form
A. Thus a more compact code is possible, and desirable if the information we need is to be easily
available. The code we use for A = B + C is
A:PZEB" C
That is, location A contains the addresses Band C
in the address and decrement portion of the word,
and the prefix PZE is used to indicate that these are
composed with the binary operation of addition.
The code for other operations is shown in Table II.
Table II also shows the detailed 704 version of
Table I. When a function K = u * v is differentiated,
the construction of A I and A 2 and the updating of
certain blocks of storage is specified by this table.
After K = u * v is differentiated, the next step is to
DOWN DATE BLOCKS FOR All A2 •
and
I
AOD PROGRAM FOR F-BLOCK TO Dy-PROGRAM
Fig. 6-Flow chart for successive differentiation of
y(k)(X)
= f(x;
y(O) (x), ... ,y(k-l)(x»
2
242
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
(d) Function program block. This contains the sequence of pseudo-instructions defining the function
to be differentiated. The last pseudo-instruction is in
y(k)(O). New terms for the construction of Al and A 2 ,
as shown in Table II, are placed in the first available
locations following y(k)(O), as needed. The program of
pseudo instructions for formula (5) is also stored here,
when all its terms have been constructed.
(e) Derivative block, D. The derivative of the initial
condition y(k-l>(O) is y(k)(O), which is not an initial
condition but an address in the function program
block. The D-block cells contain addresses of y(j)(O),
j ~ k, stored in order, so that these may be treated
in a manner similar to initial conditions.
(I) AI-block, A 2-block, and Instruction block I. The
roles played by these blocks are as described in connection with Figs. 4 and 5. In up-dating we add new
terms as prescribed by Table II. In down-dating we
eliminate terms that are no longer needed.
(g) Factor block, F. This saves all completed nontrivial (no zero factors) Al chains. In transplanting
an A I chain into the F -block, all ones and minus ones
are boiled down to a single sign for the entire product.
All ones are omitted from the F -block, unless the
particular product contains nothing but a single one.
In the flow chart of the 704 program, K stands for
the address of some pseudo-order of the y-program
currently under examination. The program starts
with examination of the last K, y(k)(O). A tag bit in
K will indicate that Dy(k) has been found, and is in
the D-block, so that it need not be found over again
when constructing higher derivatives.
Differential
~
Equation. 01 sequence
of pseudo instructions
PROGRAM
Series
Taylor
Solution, al
.equence of
pseudo instructions
+
INTERPRETIVE
ROUTINE
l
Taylor
Series
Solution.
a. a
704 machine
program
~
ROUTINE + - - Numeric Data
~--~------------~--~
Dependence
of
solution on
selected
variable
Fig. 7-Data flow for solution of differential equation.
machine-language code, and to supply numeric data.
This is done by interpretive and output routines.
The flow of information is shown in Fig. 7.
An example of the solution of a differential equation, showing the kind of information that can be
obtained from these solutions, is showl'_ in Figs. 8:
9, and 10.
70
60
The series construction, which involves multIply50
ing each derivative by the appropriate power of
x - Xo and dividing by factorials, is straightforward,
and is not shown in the flow chart.
3 40
The Taylor series solution of the differential equa>tion which is finally obtained is in the form of a
sequence of pseudo-instructions. It is always possible
30
to convert these and print them on paper using
familiar mathematical symbols, but we do not do
this and will hardly ever want to. If a differential
20
equation is sufficiently complicated to warrant using
the program, the chances are that any significant information in the expression for the solution will be
10
hidden in its complexity. If w is some complicated
function of x, y, and z, W = f(x, y, z), and we want
to find out how w depends on x, it will do no good to
o ~
0.5
1.0
1.5
o
inspect the expression f. Instead, we picture w versus
x by evaluating f for a range of x values. Similarly,
x --+
if we wish to study w versus y, we evaluate f with a
Fig. 8-Eight terms of series solution of
range of y values. The point is, we need find the
~~ = if + x, y(O) = 1, a = 2.
program for f only once. We may then evaluate it
numerically as many times as we wish, illuminating
CONCLUSION
the dependence on any desired variables.
We have described an analytic method for finding
To evaluate the solution obtained, it is necessary
a
series
solution of ordinary differential equations on
to convert the pseudo-code program to a regular
t
I
/
/
V
/
Hellerman: Solving Differential Equations
50
t
=
30
20
10
V
o
50
/
40
./'
/
I
/
40
/
t
=
30
/
10
~
.9
.7
I
20
~
.5
1.1
1.3
1.5
~
=
ya
+ X, X
= 1, a = 2.
a stored-program digital computer. Note, however,
that the present IBM 704 program for implementing
this method has room for improvement. Indeed, in
the present program little attempt is made to simplify the generated derivative expression. This is a
severe waste of storage capacity, and unduly limits
the number of series terms that can be found. Further, the unsimplified expression, containing redundant and irrelevant terms, increases the machine
time for evaluating a solution. For this reason, we
cannot now obtain a significant estimate of the merit
of the analytic method in comparison to conventional numeric techniques.
The method should be useful in illuminating local
properties of solutions. It also appears to lend itself
to extending solutions by analytic continuation, but
this is a problem that has not yet been attacked.
Another needed improvement, if we are to handle
the differential equations of electrical engineering
V
/
/
/
V
o
1.4
1.0
'1(0)-.
Fig. 9-Eight terms of series solution of
dy
dx
243
1.8
2.2
2.6
3.0
EXPONENT. 0-+
Fig. lO-Eight terms of series solution of
dy
dx
= ya
+ x, y(O)
= 1, x =
1.
practice, is the capability of handling simultaneous
equations. The obvious modification to do this is to
provide a separate function program and D-block for
each differential equation of the system.
ACKNOWLEDGMENT
The research reported in this paper has been sponsored by the Electronics Research Directorate of the
Air Force Cambridge Research Center, Air Research
and Development Command, under contract AF
19 (604 )-4152.
The idea of using the computer to develop the
series solution of a differential equation occurred in
conversation with Ramon Alonzo.
The author also wishes to express his gratitude to
Albert G. Engelhardt for substantial help in the
planning and development of his work.
244
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
Normalized Floating-Point Arithmetic with
an Index of Significance
HERBERT L. GRAyt
AND
GENERAL REMARKS ON ERROR AND SIGNIFICANCE
T HAS BEEN frequently pointed out that the task
of determi~ing an error-bound. for the results of
a problem IS usually a long dIfficult calculation
which is avoided as much as possible by the pro~
grammer. The introduction of floating-point arithmetic in modern computers and the ever-growing use
of compilers makes the task of error analysis even
more difficult and its computation even less probable.
Clearly, a machine method is needed to automatically
calculate a bound forthe propagated and generated
error, given the initial error in the input and the
residual error due to approximating functions.
Two methods for doing this herein are called the
"normalized significance" and the "unnormalized
significance" methods. The "normalized significance"
method always keeps the floating-point number normalized and provides an index of significance. The
"unnormalized signific.ance" method does not normalize floating-point numbers and uses the count of
digits remaining after leading zeros as an indication
of their significance.
Before discussing these methods, we should like to
define what is meant by significance. If one says that
a digits of a number are significant, one means that
the error in the number is less than B-(a+n) where B
is the base and n is the number of leading zeros. In
the normalized system, n would be zero. In the unnormalized system, n would be the total number of
digits minus a, as there are no insignificant digits.
Thus, in the normalized method, as many digits as
possible of a number are retained, and its index determines the number of. digits which are significant·
in the unnormalized method, only the digits con~
sidered significant are retained.
Since the error in anyone' step of a calculation is
not usually a factor of the base, B, and a in either
system only allows adjustment to within a factor of
B, any set of arithmetic rules can have the desired
property only "on the average". The design of such
rules must rest upon general assumptions concerning
the statistics of computation; these rules may, therefore, not be valid in special situations.
NORMALIZED AND U NNORMALIZED
METHODS CONTRASTED
In the normalized method to be used with Argonne's arithmetic unit FLIP, each number is repre* Work performed under the auspices of the U. S. Atomic Energy
I
Commission.
t Argonne National Laboratory, Lemont, Ill.
CHARLES HARRISON, JR.t
resented .with base 2 by a triplet (X"Xp,Xi) where x/is
the fractIonal part of the number with Y2 ~ Ix/I < 1,
Xp is the associated power, and Xi is the index of
significance. Thus X = XI • 2xp , to Xi significant
fig~res. In addition and subtraction, the result has
an Index equal to the smaller of the two indices of the
operands. Whenever a fraction is down-scaled its index and power are increased; whenever a fra~tion is
up-scaled its index and power are reduced. In multiplication and division, the index of the result is the
smaller of the two indices; and even if the result needs
to be scaled to bring it into the normal range the
index is not changed.
'
The "unnormalized method" is very similar to the
one to be used by the University of Chicago in their
new computer.l Each number is represented by a
couplet (xj, xp), where 0 ~ I XI I < 1 and the number
of digits of x{ minus the number of leading zeros
equals Xi of the normalized scheme. Insignificant
digits are shifted off the register. In addition and subtraction, no scaling of the result is carried out, unless,
of course, its fraction is greater than or equal to
unity. In multiplication and division, the resultant
fraction is scaled so as to have the same number of
leading zeros as the operand with the fewer number
of significant figures.
In his error analysis of floating point procedures in
the Communications of the Association for Computing
Machinery 2, John W. Carr III points out that a normalized floating point procedure will always give a
better result than an unnormalized procedure. While
the normalized method will create less error, the loss
of possible significant digits due to the shorter register-length remaining when an index of significance is
used may outweigh this gain.
The logic for addition and subtraction, due to the
normalization which a result may require and the
handling of the index, are more complicated in the
normalized method. However, division and multiplication are much more complicated in the unnormalized system because of the shifting required to obtain
the correct number of leading zeros. Since the number
of additions and subtractions in a calculation is usually greater than the number of multiplications and
divisions, the unnormalized system might be a little
faster.
1 R. L. Ashenhurst, and N. Metropolis, "Unnormalized Floating
Point Arithmetic," Journal of the ACM, July, 1959, pp. 415-429.
2 Carr, John W. III, Error Analysis in Floating Point Arithmetic,
Communications of the ACM, May, 1959, pp. 10-15.
Gray and Harrison: Normalized Floating-Point Arithmetic
TYPICAL EXAMPLES
Following are some examples. Those numbered
with (a) use the Argonne method, while those numbered with (b) use the second method. The length of
the fractions is adjusted so that the register in each
scheme contains the same number of digits.
(1 a) (0.5782,6,3) + (0.1485,4,3): [Argonne scheme]
0.57820, 6, 3 Arithmetic register holds 1
more digit than storage.
+0.00148,6,5
Power and index adjusted.
0.5797, 6,3
Result rounded, smaller index
is used.
(1b) (0.00578, 8) + (0.00149, 6):
0.005780, 8
+0.000014, 8
0.00579,8
[Other scheme]
Register again holds one extra
digit.
Power adjusted.
(2a) (0.1397, 5, 4) - (0.9143, 4, 2):
0.13970, 5, 4
-0.09143,5, 3 Power and index adjusted.
0.04827, 5, 3 Smaller index used.
0.4827,4,2
N umber normalized.
(2b) (0.01397, 6) - (0.00091, 7):
0.001397, 7
-0.000910,7
0.00049, 7
Power adjusted.
Number rounded to 2 significant digits.
(Sa) (0.9143, 4, 2) + (0.1875, 4, 4):
0.9143,4,2
0.1875,4,4
1.1018,4, 2
0.1102,5,3
No power adjustment needed.
Fraction exceeds one.
Normalization and roundoff.
(Sb) (0.00091, 7) + (0.01875, 5):
0.000910,7
0.000187, 7
0.00110,7
Rounded to 3 figures.
245
[Rule: result always contains same number of
significant digits as the least significant operand.]
(5a) (0.5782, 6, 3) X (0.2485,4,4):
(0.5782, 6, 3) X (0.2485,4,4) = .14368270, 10, 3
= .1437,10,3
[Rounded]
(5b) (0.00578, 8) X (0.02485, 5):
(0.00578, 8) X (0.02485,5) = .0001436330, 13
= .00144,12
[Adjusted and rounded]
(6a) (0.5782, 6, 3) + (0.2485, 4, 4)
(0.5782, 6, 3) + (0.2485, 4, 4)
= 2.327605 ... , 2, 3
= 0.23p8, 3, 3
[N ormalized and rounded]
Index does not change after normalization.
Extra digit assumed to be no good (pessimistic
approach).
(6b) (0.00578,8) + (0.02485,5)
(0.00578,8) + (0.02485;5) = 0.2325955 ... ,3
= 0.00233, 5
[Adjusted and rounded]
Same rule holds for division as well as multiplication.
(7a) (0.2485, 4, 4) + (0.5782, 6, 3)
(0.2485, 4, 4) + (0.5782, 6, 3)
= 0.429782 ... , -2, 3
= 0.4298, - 2, 3
[Rounded]
(7b) (0.02485, 5) + (0.00578, 8)
(0.02485, 5) + (0.00578, 8) = 4.29930 ... , -3
= 0.00430,0
[Adjusted and rounded]
REMARKS ON SPECIAL CASES
In the test cases we have run so far using the Argonne
scheme the number of multiplications far exceeds the
(4a) (0.5782, 6, 3) X (0.1485,4,4):
number of divisions; this gives rise to optimistic in(0.5782, 6, 3) X (0.1485,4,4) = .08586270, 10, 3 dices, though none of the indices have been off by the
[Double-register product]
equivalent of more than one decimal place. In both
= .8586,9,3
systems, a special number exists which does not obey
[N ormalized and rounded]
the above rules. This number is zero and it follows
the following rules in both systems.
Index not changed. The digit which was shifted
X±O=X
into register was assumed to be good (optiX X 0 = 0
mistic approach).
o +X = 0
X + 0 is not attempted.
(4b) (0.00578, 8) X (0.01485, 5):
(0.00578, 8) X (0.01485, 5) = 0000858330, 13
If during the normalization process in the Argonne
= .00858, 11
scheme, the index of significance is about to become
246
1959 PROCEEDINGS OF TIlE EASTERN JOINT COMPUTER CONFERENCE
less than zero, then the shifting is stopped so that
the index remains at 'zero. Thus, at the end of this
operation, the fractional part of the number may be
less than one-half. This number, known as a relative
zero, obeys the same rules as any normalized number
during addition, subtraction and mUltiplication; but
division by this number, as with true zero, is not
attempted. Whenever the normalization is not completed, the Argonne machine will jump to a fixed
location in the memory and let the program decide
what is to be done about the number.
Relative zero may also be introduced as an input
number. In this case, the fraction is unnormalized,
but the index need not be zero. This number is used
in special operations such as finding the integral part
of another number, as follows:
0.4597,2,4
+0.0000,4,4
0.0045, 4, 4
0.4500, 2, 2
Adjust power (index at max.)
Normalization.
This type of relative zero is also used in operations
which convert from floating to fixed point. A relative
zero with an index not equal to zero can never be
generated by the floating-point unit.
The only other special number which may arise in
the second scheme is a number with zero significant
figures and thus a zero fraction. All operations with
this number except division follow the normal rules.
If a number in the Argonne scheme does not have
any associated error, it is said to be "totally represented". Such numbers are given a special index and
operated on in a slightly different way. As long as a
calculation uses only totally represented numbers,
the index of the result does not change even if normalization occurs. If, however, during a calculation any
non-zero digits of a number are shifted off, or if one
of the operands is not a totally represented number,
then computation of the index of the result reverts to
its normal form. For example:
(.4583, 2, TR)
- (.4329, 2, TR)
.0254,2, TR
.2540, 1, TR
(Totally represented)
Normalization.
(.4583; 2, TR)
+(.1497, 1, TR)
.4583,2, TR
.01497,2, TR Adjust power
Results rounded to 4 figures.
:4733,2,4
.4583,2, TR
-.4329,2,4
.0254,2,4
.2540, 1,3
Such a scheme helps to simplify floating-point-integer
arithmetic.
TESTS OF ARGONNE METHOD IN
REPRESENTATIVE PROBLEMS
To test the accuracy of the index in the floatingpoint scheme, we simulated FLIP with a GEORGE
program. We combined this program with some
GEORGE subroutines and compared the results obtained in this manner with those computed by other
means.
Characteristic Polynomial of a Matrix
First, let us consider the routine involving the
method of Leverrier for determining the coefficients
of the characteristic polynomial of a real-valued
square matrix.
Let Ai = roots of the characteristic polynomial of
our n X n matrix A.
Define Sk = trace (Ak)
k = 1, 2, ... , n
n
Sk =
L: a}7)
i=l
The characteristic equation is
An + C 1 An- 1 '+ C 2 An- 2 + ... + Cn-IA + C n = 0
where
-C I = Sl
-2C2 = SIC I
-3C3 = SlC 2
+ S2
+ S2C 1 + S3
The method requires the computation of A2, A3, ... ,
An and the corresponding SI, S2, S3, ... , Sn. There
are n 3 (n - 1) multiplications and n 3 (n - 1) +
n (n - 1) additions involved in these calculations.
Obviously, inaccuracies can be caused if n is very
large or the elements of A are too large.
We ran tests with our combined program using
four different matrices. In the first two cases tested,
the A's were of the tenth order and of the forms:
1
2
10
and
.!)
Not a totally represented number. In both cases CI = -SI and C2 = C3 = ... = C10 = o.
Index reverts to its normal form. We obtained exact results and the index indicated
this for each coefficient .
Gray and Harrison: Normalized Floating-Point Arithmetic
Next we tried a twelfth-order matrix of the form
4 -1
0
0 -1
0
0
0
0
0
0
0
-1
4 -1
0 -1
0
0
0
0
0
0
0
4 -1
o -1 0 0 0 0 0
0
0 -1
o -1 4 0 0 o -1 0 0 0 0
0
-1
4 -1
0
0
0
0
0
0
0
0
0
4 -1
0
0 -1
0 -1
0
0
0
0 -1
o -1 0 0 -1 4 -1 0 -1 0 0
0
o -1 0 o -1 4 0 0 -1 0
0
0
4 -1
0
0
0 -1
0
0
0
0
0
0
o -1 0 -1 4 -1 0
0
0
0
0
0
o -1 o -1 4 -1
0
0 0
0
0
0
o -1 4
0
0
0
0
0
0
0 0 0
Once again, we obtained exact results with the
corresponding correct indices. It was with this case
that we noticed the vast difference a change in
method made in the final results. We computed the
coefficients from the equation
If, however, we use the slightly different equation
we get different results. In fact, C12 is completely in
error and the index associated with it is zero. This
zero index means the number is worthless as a result.
The initial error was introduced in the computation of 11k, since non-terminating decimals like 1/3,
1/6, etc. cannot be exactly represented. The use of
these inexact numbers produced inexact coefficients.
The errors in both of these were propagated in the
calculations of subsequent coefficients. As a result,
C12 was completely in error.
The next matrix we used was a fifteenth order
matrix having all its elements equal to 1. Even though
the elements are not large, the size of n leads to some
very large intermediate results. For example, 8 15 =
1515 = 437,893,890,380,859,375. The coefficients, however, were more reasonable. In fact Cl = -81 and
C2 = Cg = ... = C15 = O. In this test we also found
complete agreement with the indexed results and
the known values for the coefficients.
I nversion of a Hilbert Matrix
Next we applied our program to Jordan's ~ethod
for. the inversion of Hilbert matrices of various orders.
Hilbert matrices are of the form
247
1
-
1
2
1
3
1
n
-
1
2
1
3
1
4
1
1
3
1
4
-
-
-
1
1
n n+l
-
n
+1
1
]
+2
5
n
1
1
2n - 1
n+2
Hilbert matrices are almost singular and as the size
of the order increases, the value of the determinant
rapidly approaches zero. Several matrices were inverted including a 12 X 12 which had a determinant
approximately equal to 10- 7 5. We compared the results we obtained with those computed by an inversion formula. g
The elements in our inverted matrices compared
favorably with those in the table of inverses for all
the orders tested. We were able to get 10- or II-digit
agreement in the elements of an inverted seventhorder Hilbert matrix and 6-or 7-digit agreement for a
10 X 10. The indices associated with these inverse
elements were either correct or one-digit optimistic.
This is about what we expected since we employ the
optimistic approach in our floating-point scheme.
It may be interesting to note that Jordan's method
on a floating-point machine produced inverses above
the 6th order that were completely in error. Also, our
GEORGE interpretive floating-point subroutine was
useless beyond a 7th -order Hilbert matrix. The primary difference in these cases is the number of digits
the machine can hold. However, the other two
schemes give no indication of the approximate accuracy of the results.
Evaluation of a Polynomial
A third test was performed with a subroutine
which evaluates a polynomial, with real or complex
coefficients, having real or complex roots. We inserted
known roots for certain 4th and 8 th degree polynomials
with real coefficients and noted the computed value
of the polynomial.
When the roots were real and exact, the computed
value of the polynomial was exactly zero. The same
thing was true when the roots were complex but with
exact real and imaginary parts. However, when the
3 I. Savage and E. Lukacs, "Tables of Inverses of Finite Segments
of. the Hilber~ Matrix" in Contributions to the Solution of Systems of
Lmear Equatwns and the Determination of Eigenvalues NBS Applied
Mathematics Series 39, p. 105-108, 1954.
'
248
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
roots were complex and at most one of the parts was For these cases, the index on the partial sums was
exact we get an evaluation of the polynomial which sometimes less than the maximum, but continued
is not exactly zero and has a zero index. Here, the summations caused it to increase up to the maximum
zero index meant the digits in the number were mean- allowed for non-totally-represented numbers.
ingless but the zeros preceding the first of these
Conclusions
digits were correct.
The tests we ran were considered fairly representaNumerical Integration
tive of the calculations involved in many problems.
Finally, we applied our program to a trapezoidal The fact that the index of significance was never
integration subroutine. We evaluated some simple in- more than one digit from its true value lends merit
tegrals between exact limits. If the results could be to the Argonne scheme. If some of the multiplications
represented exactly, we obtained exact results. When could have been replaced by divisions without inthe results could not be exactly represented we ob- creasing the errors, the index would have been even
tained numbers whose error was less than 5 X 10- 18 • closer to the true value.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
249
Determination of Optimum Production Tolerances
by Analog Simulation
R. B. McGHEEt
INTRODUCTION
T
HE ELECTRONIC analog computer has been
widely utilized in recent years to obtain optimum
parameter values for various types of control
systems. 1,2 The procedure usually followed is to determine a control-system configuration by simplified
analysis and then to program a computer in a realistic way, including all significant nonlinearities and
appropriate random input disturbances. Next, a performance criterion of some sort is selected for the
control system under study, and system parameters
(gains, time constants, etc.) are varied until an optimum system is obtained. At this point, simulation
activity usually ceases and is not resumed again unless the actual control system either cannot be constructed to obtain the desired parameter values or
else fails to attain the level of performance indicated
by the earlier simulation.
While this approach has produced many successful systems, it is the contention of the authors that
it is seriously deficient in one respect: the essentially
statistical nature of an actual system resulting from
a manufacturing process is completely ignored. The
representation of a control system as a differential
equation with known coefficients is not realistic. An
accurate simulation must effectively consider an ensemble of control systems, (i.e., a random differential equation) characterized by parameters with
common statistical properties. These statistical properties ordinarily take the form of production tolerances. Such tolerances must be considered concurrently with the search for optimum parameters if
the simulator is to provide a reliable evaluation of
the system performance.
The addition of random parameter values to a
control-system simulation not only allows a more
realistic determination of performance, but it also
permits a more systematic and organized assignment
of production tolerances. Conventionally, while the
mean values for parameters are selected primarily on
the basis of performance, the tolerances are selected
primarily on the basis of cost. These two indices are
somewhat at odds. For example, if cost were no
object, but the desire to maximize performance
AND
A. LEVINEt
dominated, then the ideal choice for each tolerance
would be zero. On the other hand, if one desired
simply to minimize cost per unit, infinite tolerances
(one hundred percent acceptance of production)
would be the proper policy. In the practical situation, a compromise between performance and cost
must be effected. This compromise is too often accomplished on the sometimes dubious basis of intuition and "engineering judgment." It is unfortunate
that such methods are used at a decision level so
vital to the ultimate performance and cost of a
product; more so, since the trade-off can be made
more objective through analog simulation. By using
a simulator to obtain performance as a function of
the tolerance assignment, one can choose tolerances
so as to maximize performance for a fixed cost or
minimize cost for a fixed performance. In statistical
terms, one can use the simulator to obtain optimum
values for both the mean (nominal value) and standard deviation (production tolerances) for each important parameter.
A first step in this direction has been taken by
R. C. Davis. 3 He postulated a linear dependence of
a system performance index on parameter variances
and obtained the necessary degradation coefficients
by regression analysis of an analog computer experiment in which parameters were varied randomly.
Although Davis did not explicitly mention cost, the
coefficients he derived were utilized in juggling tolerances in such a way as to ease manufacturing
difficulties without degrading performance. In principle, it would seem that these coefficients could be
used to derive the original tolerances in an optimum
manner. While Davis' method is probably the only
sensible one if one is restricted to real-time simulation, it will be demonstrated with a simple practical
example, that there are systems for which such a
linearization can lead to wholly erroneous and misleading conclusions. The following paragraphs describe an analog simulation technique leading to an
optimum tolerance-assignment which avoids the difficulties associated with an a priori assumption
concerning the form of the functional dependence of
performance on tolerances.
t Hughes Aircraft Co., Culver City, Calif.
C. L. Johnson, Analog Computer Techniques, pp. 45-64, McGrawHill, New York. 1956.
2 F. E. Nixon, Principles of Automatic Controls, pp. 287 to 305,
Prentice-Hall, Englewood Cliffs, N. J., 1953.
1
3 R. C. Davis, "A Statistical Method for Analyzing the Effects of
Missile Guidance System Tolerance on Hit Probability," Proc. Third
Exploratory Conference on 'Missile Model Design for Reliability
Prediction, White Sands Missile Range, pp. 85-96, April 1959.
250
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
PROPOSED TOLERANCE OPTIMIZATION TECHNIQU~
Computer are employed. 4 These computers are
capable of providing solutions at rates up to 50 cps
and can compute average performance indices simultaneously with solution of the differential equations
of the control system.
Determination of the Performance Function
In order to arrive at an optimum set of tolerances,
it is necessary first to determine the dependence of
the control-system performance index, PCQ), on the
tolerance vector Q. It is proposed that P(Q) be Determination of the Cost Function
determined by simulation according to the following
Once PC Q) is obtained, it is necessary to deterprocedure:
mine the dependence of the unit cost of the system,
C(Q), on the tolerance assignment. This is a diffi(1) Optimum nominal parameters are determined
cult problem which has long concerned manufacturin the usual way.
ing industries. It does not appear that analog simu(2) A tolerance vector, Q, whose components are lation can aid in the determination of C(Q). Neverthe standard deviations assigned to each para- theless, C( Q) is required in order to optimize Q, so
meter, is selected. This vector, together with it is therefore necessary to discuss the estimation of
the mean values determined in Step 1, is used costs sufficiently to indicate the difficulties to be
to adjust filters operating on a stationary noise expected and the general nature of the cost function.
source so as to obtain voltages having the
Among the factors to be taken into account in the
same mean and variance as the parameters determination of C(Q) are the raw cost per unit,
under investigatioh.
salvage value, maintenance costs resulting from tol(3) These voltages are fed to integrators as initial erances too wide or too narrow, lifetime, etc. Initial
conditions while the computer is in reset. Each estimation of C( Q) based on such considerations can
integrator in turn provides the input to a mul- probably best be accomplished by reference to mantiplier representing the value of the random ufacturing experience with previous products similar
coefficient in the simulation. When the com- to the one under consideration. As production proputer is placed in operate, the integrators ceeds, the original estimate may be refined on the
have no input. Thus, the value of the coeffi- basis of actual costs. In addition to the experience
cient is fixed during the solution of the differ- accumulated by various manufacturing organizaential equation, but random when the com- tions, considerable literature exists on the subject of
puter is in reset. This effectively simulates a cost estimation. 5,6
While the general problem is much too extensive
new production sample each time the comto treat here, one can observe from experience that
puter is placed in operate.
C(Q) is generally hyperbolic in nature. That is,
(4) A large number of runs is made with a fixed
reduction of any element of Q = (0"1, 0"2, • • • , 0" n) to
tolerance-vector. An average performancezero will result in infinite cost while minimum cost
index is obtained for the whole set of runs
is achieved by making all tolerances infinite.
(e.g., probability of hit for a missile system).
(5) The components of the tolerance vector are Optimization of the Tolerance Vector
varied in a systematic way, with a large numAfter PCQ) has been determined, the optimizaber of computer runs being made for each
tion of Q may be considered. The first step required
new set of tolerances.
is to select a criterion for optimization. An obvious
(6) The results are plotted with the aid of re- criterion is to optimize performance for a fixed cost.
gression anaiysis using a digital computer. An That is, on a surface of constant cost in the Q-space,
arbitrarily high order of polynomial fit may one seeks the point of maximum performance. On
be used if sufficient data is taken on the ana- the other hand, it might be more desirable to minilog computer.
mize cost for a fixed performance. lVlore complicated
optimization criteria are possible by specifying the
The enumerated steps lead to a representation of a
cost one is willing to accept as a function of persystem performance-function, P(Q), without an a
formance, etc.
priori assumption regarding the form of the funcAs more data becomes available, the estimate of
tional dependence of the system performance on
the cost function will change, thereby shifting the
parameter values.
It should be noted that step 5 may easily involve
hundreds of thousands of runs. For this reason, it
4 Johnson, OPe cit., pp. 222-232.
appears that the proposed sirnulation technique is
5 D. H. Evans, "Optimum Tolerance Assignment to Yield Minieconomically feasible only when high-speed analog mum Manufacturing Cost," Bell System Technical Journal, Vol. 37,
pp. 461-484, March 1958.
computers such as the GPS (General Purpose Simu6 E. W. Pike and T. R. Silverberg, "Assigning Tolerances for
lator Instruments Company) or Philbrick Repetitive Maximum Economy," Machine Design, Vol. 25, p. 139, Sept. 1953.
McGhee and Levine: Determination of Production Tolerances
251
optimum. However, the original performance func- mean values Ko and To and standard deviation O'K and
tion, P(Q), remains valid; so the apportionment of O'r respectively. The sample values were therefore
tolerances may be altered to a new optimum without obtained by low-pass filtering of noise generators,
using integrators which did not reset. Fig. 2 shows
further simulation.
the computer program used to randomly vary the
EXAMPLE
navigation gain, K, from run to run.
Description of Simulation
In order to establish the feasibility of the proposed
technique, a simulation of a hypothetical radarhoming missile was undertaken. Besides random
parameters, this simulation included random radar
tracking noise and a random missile-heading error at
launch. The performance ihdex selected was probability of hit, Ph as measured against an idealized strip
target. To limit the amount of data to be taken, only
two parameters were varied randomly. These parameters were the navigation gain, K, and the principal
missile filtering-time constant, r. The missile which
was simulated derived steering information from the
angular rate of the line of sight from missile to target,
so K is given by
K = steady-state missile turning-rate
(1)
line-of-sight angular rate
Fig. 1 is a functional block diagram of the missile
simulated.
NON-RESETTING
INTEGRATOR
BROADBAND
NOISE
No
= TWO-SIDED
LOW FREQUENCY SPRECTRAL
DENS ITY, VOLT 2/CPS •
9 = APPARENT LlNE-OF-SIGHT ANGLE
Fig. 2-Random variation of navigation gain.
~
0%
10%
20%
30%
0%
0.34
0.30
0.31
0.29
10%
0.30
0.31
0.29
0.29
20%
030
0.26
0.30
0.30
30%
0.24
0.22
0.28
0.27
aT
RADAR TRACKING NOISE
APP~RENT
TRUE LlNE- j ( +
OF-SIGHT +,-
0.24
:i:
0
I-
:J
1D
~
0
0::
a.
PERCENT- - -
t----
O"T= 20 PERCENV
~
O"T=30 PERCENT"'"
0.22
of experience gained in the optimization of nominal
values, the system designer might decide that an adequate model for the relationship between Ph and the
values of the parameters, K and T, is given by the
quadratic expression:
--------
Ph =
0.20
0.18 f - - -
O"T=STANDARD DEVIATION OF MISSILE PRINCIPAL TIME CONSTANT
I
0.16
014
10%
0%
20%
30%
STANDARD DEVIATION OF NAVIGATION GAIN CONSTANT,
'Yo
+ 'YI(K + 'Y12(T -
+
+
N ow since the values of K and T were independent in
this experiment (and very often in practice) the
average or expected value of Ph measured over the
ensemble of missiles is given by
ITK
Phve
Fig. 4-Dependence of probabili.ty of ?i~ on tolerance
assignment for a hommg mIssIle.
=
E(P h )
= 'Yo
+ 'YllE(K
-
KO)2
+ 'Y22E(T
-
To)2
(4)
where the symbol E denotes the expected value or
theoretical average resulting from repeated estimation of Ph. The other terms vanish because they have
zero expected value. Now, by definition, the ensemble
averages in the above expression are just the variances; Le.,
30%
E(K E( T -
so
o
+
Ko)
'Y2(T - TO)
'Yll(K - KO)2
To)(K - Ko)
'Y22(T - TO)2
(3)
10%
20%
30%
STANDARD DEVIATioN OF MISSILE PRINCIPAL TIME CONSTANT,
Fig. 5--0ptimization of tolerances for minimum cost or
maximum performance.
ITT
KO)2
=
Uf{2
= variance of K
(5)
TO)!~
=
UT 2
= variance of
(6)
T
(7)
This is the analytic origin of the common assumption
that performance depends linearly on the variances.
If one accepts this assumption, then all that is required is to perform an experiment, selecting many
values of the variables and recording the performance
index along with the values of the variables. Regression analysis is then accomplished on equation (3)
yielding the desired coefficients,. 'YO, 'Yll, an~ 'Y22.
While the above approach WIll succeed If the assumed model (3) is in fact correct, it has already
been shown that the resulting conclusion of linear
dependence of performance on parameter variances
cannot possibly describe the behavior of the example
at hand. The reason is that the effect of the terms
UI, U2, and U!U2 are absent from (7) whereas a regression analysis of the experimental results based on (2)
shows that U!U2 is in fact the most significant term.
This term represents interaction effects which are of
prime importance in this sY!3tem. The a~tual fina~cial
cost of ignoring this term could be conSIderable sI~ce
utilization of (7) would lead both to unnecessanly
tight tolerances on K and to degraded performance
when UT is large.
The process of deriving the effects of tolerances
from a model for performance-dependence on parameter values can be turned around. That is, if one
knows the, coefficients in an equation like (2),
straight lines on Fig. 4. Replotting with UK 2 as the
abscissa would show that linearization of the dependence of Ph on UK 2 and ui is also impossible. Further
examination of the figure reveals the remarkable fact
that the performance of this system can actually be
degraded by tightening tolerances. For example,
when UT = 30 percent, the probability of hit is decreased from .28 to .24 as the tolerance on UK is
reduced from 30 percent to 0 percent. This is quite at
odds with the widespread opinion that when tolerances are relaxed in one part of a system, they must
be tightened elsewhere to maintain the system performance. In the present example, this apparently
anamolous behavior results from a cancellation of
effects when K and T both vary widely from their
nominal values.
A more general and far reaching conclusion arising
from this example is concerned with the form of the
mathematical model selected to represent the dependence of the system-performance index on parameter values. In the more conventional approach to the
study of tolerances, one begins by assuming a specific Ph = ao + aIUK + a2UT + aUUK2 + W12UKUT + a22UT2 (2)
model for this dependence. 7 For example, on the basis then the effect of parameter values can be inferred
7 Evans, op. cit.
(though not uniquely). For example, if it were true
253
McGhee and Levine: Determination of Production Tolerances
that
Ph =aO+a'l! K-Ko \ + a'2\ T-TO \ + al1(K-Ko)2
+ a'12 I K - Ko II T - TO I + a22(T - TO)2 (8)
then (2) would follow and the coefficients in (8)
could be obtained from a regression on tolerances
such as was performed in the present example.
To summarize, in the light of the preceding discussion, it is maintained that one should in general reverse the usual approach to tolerance analysis by:
1. Performing a simulation with randomized co-
efficients as described in the section above on
Tolerance Optimization.
2. Derive the mathematical model for the system
from a regression analysis of the dependence of
system performance on the tolerance vector.
In this way, new insight can be obtained into the
relationship between performance and parameter
values, and serious errors in tolerance assignment can
be avoided.
the performance index, Ph, possess a binomial distribution, because they result from repeated trials of
the same experiment. One can therefore estimate the
variability of successive measurements of P h .9 It
turns out that if Ph is the true or theoretical probability of hit and Ph is the measured ratio of hits to
total firings, then
Ph =
i\
±
l/vn
(9)
n = total number of simulated firings
with probability .95 or better. Consequently, since
the data in Fig. 3 was obtained by making five hundred simulated firings per data point,
Ph =
i\
± 1/ V 500 ~ Ph ± .045
(10)
That is, we can have at least ninety-five percent confidence that the true Ph lies within ±.045 of the
values listed in Fig. 3.10 Utilization of quadratic regression (2) considerably improves the confidence we
may have in the final result of Fig. 3.
If one were to decide that a precision of ± .045
DESIGN OF EXPERIMENTS
with ninety-five percent confidence was required of
The Need for Experimental Design
every point, and furthermore, that m values of each
The experiment just described involved only two of k parameters must be considered, then for this
parameters. In a more realistic problem, it is likely example the total number of runs would be given by
that a much larger number of system parameters
n = 500 mk
(11)
would be considered in the assignment of optimum
tolerances. Utilization of the method presented in This number may be so large as to make a "brute
this paper leads to an alarming increase in the total force" determination of P(Q) impractical, even with
number of runs as the number of parameters increases a high speed computer. In such an event, some means
unless the experiment is carefully designed. The such as the experimental design described below must
problem of determining just how to take data so as be found for reducing this total.
to obtain the most information with a lIlinimum of
effort falls within the realm of statistical design of Factorial Design
experiment. This field is so extensive that it is neither
In the example treated in this paper, the data
possible nor desirable to consider it in detail in this points were taken at uniformly spaced points in a
paper. Fortunately, there are several excellent texts UK, UT space (Fig. 3). Fortunately, it is not necessary
on the subject which treat a variety of types of to take data at all of these points to determine a
experiment. 8
quadratic relationship between P(Q) and Q. One
While a general discussion of design of experiment type of design of experiment which allows fewer data
is not appropriate, there are two aspects of this field points to be considered is called "fractional factorial
which are particularily useful in experiments of the. design".n This design method involves a sequential
type discussed in this paper. In the first place, it is determination of the points at which observations
necessary to be able to estimate the total amount of should be made, and is particularly well suited to the
data required to define P(Q) before beginning the determination of P(Q). The total number of comexperiment. Secondly, in the event that this number puter runs may be drastically reduced, amounting
is too large, it is very desirable to have a means for possibly to several orders of magnitude in the total
reducing this total by a judicious choice of data effort required to define P(Q). While the complete
points in the tolerance-vector space. Both of these
problems are considered below in connection with the
9 P. G. Hoel, Introduction to Mathematical Statistics, John Wiley
present experiment.
and Sons, New York, Chapter 10, 1947.
Estimation of the Amount of Data
10 Methods also exist for the estimation of confidence intervals in
the event that the variables do not possess a binomial distribution.
In the missile simulated, the measured values of Ibid., Chapter 10.
8 W. G. Cochran and G. M. Cox, Experimental Designs, John
Wiley and Sons, New York, 1950.
11 J. S. Hunter, "Designing and Interpreting
Engineering, pp. 137-141, Sept. 1959.
Test~,"
Control
254
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
~
0%
30%
034
029
aT
0%
30%
024
0.27
Fig. 6-Measured probability of hit as a function of
parameter standard deviations.
theory is somewhat involved, Fig. 3 can be used to
illustrate the basic idea of fractional factorial design.
Referring to the experimental example, if one knew
the relative importance of the terms UK, UT, and UKUT
in determining P(Q), then a more intelligent selection of sampling points could be made. Now an estimate of the relative effects can be obtained by evaluting P(Q) only at the vertices of the table of Fig. 3.
Fig. 6 is an abbreviated table, obtained by using only
the four corners of the other table. The relative effect.
of each of the three terms above is obtained as follows:
(1) Estimated effect of UK = average of Ph over
column (2) - average Ph over column (1) =
(.29 + .27)/2 - (.34 + .24)/ = -.01
(2) Estimated effect of UT = average of Ph over row
(2) - average Ph over row (1) = (.24 + .27)/2
- (.34 - .29)/2 = -.06
(3) Estimated effect of UK(JT = average difference
of row (2) - average difference of row (1) =
(.27 - .24)/2 - (.29 - .34)/2 = .04
Thus it can be seen that the "interaction effect" of
is greater than the "main effect" due to UK
and nearly as great as the "main effect" due to UT'
While this result is obtained from only four data
points, it is (qualitatively) quite in accord with the
final result obtained by regression analysis (Fig. 4).
The significance of this test is simply that the UKUr
term cannot be dropped from the regression equation (2). There is, however, a possibility of dropping
the linear term UK. If this were done, then less data
would be required to estimate the remaining regression coefficients. A more sophisticated approach to
fractional factorial design must consider confidence
intervals and other effects to determine whether or
not a given term can be dropped from (2).
When a large number of parameter tolerances are
involved in Q, the dropping of even one term from
the regression equation may provide a considerable
saving in the simulation effort required to obtain
P (Q). Even if no terms can be dropped from the
regression equati.on, uniformly-spaced data points do
not provide the best grid for measurement of P(Q).
UKUr
Further development of fractional factorial design
provides a solution to the problem of determining the
optimum location for data points in the parametertolerance space.
SPECIAL SIMULATION CONSIDERATIONS
Correlation Between Successive Parameter Values
In order to simplify the analysis of data, it is desirable that successive values of parameters selected
from noise generators be uncorrelated. For noise
sources shaped by first-order filtering, the correlation
of output samples separated by time T is given by
(12)
where
T1
is the filter time constant. 12 Consequently,
Multiplexing of Noise Generators
In a problem of realistic complexity, a sizable
num ber of uncorrelated noise voltages are required
to provide parameter values. These voltages can be
obtained from a single noise generator by frequencymultiplexing techniques. Rice has shown 13 that an
ensemble of samples drawn from a Gaussian noise
generator can be described by a Fourier series with
un correlated random coefficients. Consequently, if
such a signal is passed through a bank of bandpass
filters, the correlation between filter outputs can be
made as small as desired by reducing the spectral
overlap of the filters sufficiently. In this process, the
correlation between successive samples from a single
filter must also be considered. This factor sets a
lower limit on the bandwidth of the individual filters.
High-Speed Data Processing
When solution rates are as high as the 50-cps capability of repetitive computers, data reduction must
be at least partially accomplished by the computer.
One such computer (GPS) has a probability-distribution analyser which automatically provides probability of hit. This means that there is no need to
process individual solutions off the computer. It appears that such an instrument or a related one is
essential in simulations where hundreds of thousands
of runs are required.
I
CONCLUSIONS
The role of simulation in the preliminary design of
control systems can be expanded to include selection
of optimum manufacturing tolerances. If a highspeed computer is available, one may abandon linear
models for the effect of varying tolerances and thereby
obtain a realistic method for performing the crucial
trade-off between cost and performance. A lesser
effort is apt to lead to false conclusions concerning
system performance.
12 J. L. Lawson and G. E. Uhlenbeck, Threshold Signals, p. 42'
McGraw-Hill, New York, 1950.
13 S. O. Rice, "Mathematica.l Analysis of Random Noise," Selected
Papers on Noise and Stochastic Processes, N. Wax, ed., pp. 157-161,
Dover Publications, New York, 1954.
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
255
The Crossed-Film Cryotron and Its Application
to Digital Computer Circtlits
V. L. NEWHOUSE,t J.
w. BR,EMERt
AND
H. H. EDWARDst
INTRODUCTION
SUPERCONDUCTIVE FILMS
HE NAME cryotron was applied by the late
.D. A. Buck to the superconductive relay which
he described. 1 Buck's cryotron consisted of a wire
of tantalum surrounded by a coil of niobium and was
operated at the boiling point of liquid helium at
atmospheric pressure. At this temperature the tantalum "gate" wire was only just superconducting.
By passing a sufficient current through the niobium
control coil, a magnetic field was created. which was
sufficient to transform the tantalum gate to its resistive state.
It was found by two of the authors that it is possible to produce the cryotron in a geometry suitable
for deposition on a fiat surface. 2 This will be referred
to as the crossed-film cryotron (CFC). The CFC
was first presented in public at the Electron Device
Research Conference at Ithaca in June 1959. Similar
devices were described at the same meeting by M. L.
Cohen, J. L. Miles, A. E. Slade and C. R. Smallman
of the A. D. Little Company, and by A. E. Brenneman
and R. de Lano of the IBM Research Center.
This· paper describes a crossed-film cryotron deposited on an insulated superconductor. This CFC
has a time constant of less than one microsecond and
is approximately one hundred times faster than the
original vacuum-deposited cryotron. 2 The d-c dissipation is less than 5 microwatts and the active area
of each element is approximately 5 X 10- 4 square
centimeters. These cryotrons and all their interconnecting circuitry can be vacuum deposited at one
and the same time in a few simple steps.
The cryotrons can be applied to both switching and
storage. Some experimental storage and shift-register
circuits are described, which demonstrate a circuit
property unique to superconductors. A shift-register
circuit is shown which is deposited in an area corresponding to 20,000 active elements per square foot.
Calculations are presented which show that with
this component density, a computer or memory co~
taining more than one million elements can be accommodated in a one-cubic-foot liquid helium container
using presently available refrigeration methods.
The devices to be described are made up of tin,
lead and insulator films only. Of these, only the tin
films change their state during operation. We can,
therefore, confine our attention mainly to tin films.
At temperatures below the so-called critical temperature Tc, tin and lead become superconducting. For
lead, Te = 7.2°K. For the tin films used, Te =
3.75°K. The devices described are operated at approximately 3.6°K. At this temperature, the tin
films can readily be switched from the superconducting to the normal (resistive) state, but the lead films
remain superconducting throughout.
Just as in the case of bulk materials, it is possible to
restore a superconductive film to the normal state by
the application of a magnetic field greater than the
so-called critical field He. The variation of He for
bulk tin is shown in the insert of Fig. 1.
T
t General Electric Company, Schenectady, N. Y.
1 D. A. Buck, "The Cryotron A Superconductive Computer
Component," Proc. I.R.E., Vol. 44, pp. 482-493, 1956.
2 V. L. Newhouse and J. W. Bremer, "High-Speed Superconductive
Switching Element Suitable for Two-Dimensional Fabrication,"
J.A.P., Vol. 30, p. 1458, Sept. 1959.
400
He OF BULK TIN
VS TEMPERATURE
T"K
Fig. I-Critical field of gate film as a function of temperature. Solid
line: measured directly. Points: calculated from cryotron characteristics and grid widths, using Eq. 4. Grid widths: ... 16 microns
(unshielded), 065 microns (shielded), 0 40 microns (shielded).
The main portion of Fig. 1 compares He of bulk tin
and He of a 0.3-micron-thick tin film. The film curve
was determined experimentally, with a uniform
magnetic field applied parallel to the film surface.
The data points shown in the figure are values of He
calculated from the electrical characteristics of
crossed-film cryotrons. These are discussed in connection with Eq. (4) below.
Fig. 1 shows .that He of the film is higher than for
the bulk material. It can be established on the basis
of thermodynamics 3 that if the film thickness is of the
same order of magnitude as, or less than, the penetra3 D. Shoenberg, Superconductivity, pp. in-174, 2nd edition,
Cambridge Univ. Press, 1952.
256
1959 PROCEEDINGS OF THE EASTERN JOINT COMPUTER CONFERENCE
tion depth, He varies inversely with film thickness.
The penetration depth is roughly equal to the thickness of the surface layer in which the current flows in
a bulk superconductor. For tin, the penetration
depth at absolute zero is approximately 5 X 10- 6
cm, but at temperatures close to T e , it is larger. At
3.6°K, a typical operating temperature for a crossedfilm cryotron, the penetration depth is about 0.1
mICron.
The variation of resistance with current for a 0.3micron tin film is shown in Fig. 2. By applying the
current in short pulses, it is possible to obtain the socalled isothermal transition shown in the broken
line. This curve is connected with the actual superconducting behavior of the film, and is reasonably
independent of other film characteristics, such as
resistivity, and of the substrate properties. If a
slowly-rising current is passed through a film, Joule
heating causes thermal ('propagation" of resistive
areas in the film.4 This behavior is shown in the solid
curve of Fig. 2, and is strongiy dependent on substrate thermal conductivity and on film resistivity.
10
0,8
0,6
_R_
R42
x
I
I
/ 4/L SEC PULSES
04
/
/
I
0,2
/
x
..,../x
00
FILM CURRENT -rno
Fig. 2-D-c and pulse current-induced transitions for 0.3 micron
thick, 4.05 mm wide tin film on sapphire substrate ....T = 0.08°K.
The current at which resistance first appears is
known as the critical current Ie. For thin films
Ie = ic W(Te - T) where W is the film width and T
the bath temperature, provided that Te - T« Te. 5
ie increases as film thickness increases and appears to
depend somewhat on heat treatment and film substrate. It has been found that ie is more than doubled
if the film in question is deposited on top of an
insulated lead "shield" plane.
The explanation of why a tin film which lies
adjacent to a lead shield plane has a higher critical
current than a similar tin film deposited on glass is
believed to be as follows: It can be shown 6 that a
film in the shape of a cylinder will carry twice as'
4 J. W. Bremer and V. L. Newhouse, "Thermal Propagation Effect
in Thin Superconducting Films," Phys. Rev. Letters, Vol. 1, p. 282,
1958.
{) J. W. Bremer and V. L. Newhouse, "On Current Transitions in
Superconductive Tin Films," Phys. Rev., to be published.
V. L. Ginzburg, "Critical Currents in Superconducting Films,"
Soviet Physics "Doklady," Vol. 3, p. 102, 1959.
6
much current as the same film unwrapped into a
flat plate. When current passes through a tin film
adjacent to a superconducting shield, surface currents are induced in the shield to prevent flux from
penetrating into it. It can be shown that these surface
currents double the field between the film and the
shield, and produce an approximately zero field on
the opposite side of the film. This field configuration
is the same as would occur if the tin film were in the
shape of a cylinder. It is to be expected, therefore,
that the critical current for a shielded flat film is
increased from the value for the unshielded flat film
to that for the cylinder.
The mathematical problems of calculating the surface currents induced in a superconducting surface
due to the presence of an external current-carrying
conductor are similar to the problems of calculating
the surface charge produced in a perfect conductor
due to an external charge. It is found that some of
the results of the "method of images" of electrostatics can be carried over to superconductors if an
electronic dipole is replaced by a magnetic dipole, and
a line of charge by a line of current. For a currentcarrying wire above a superconducting surface, for
instance, it can be shown that the net field outside
the surface is e'qual to the field of the original current plus that of an equal and opposite shielding
current which is the same distance behind the superconducting surface as the real current is in front.
This effect increases the field between the current and
the surface, but reduces it everywhere else. (It is
assumed that the maximum net field is less than the
critical field of the superconducting shield plane.) It
can be seen therefore that if it is desired to reduce
the effective inductance of a wire or length of film,
it is simply necessary to place a superconducting
plane with a high critical field in close proximity.
THE CROSSED-FILM CRYOTRON'
The basic structure of a crossed-film cryotron
(CFe) is shown in Fig. 3. If a sufficiently large current is passed through the "grid" film, the resulting
magnetic field produces a resistive channel across the
much wider tin "gate" film. The grid remains superTIN GATE
LEAD CONNECTORS
GLASS SUBSTRATE
LEAD GRID
'" Si 0 INSULATOR
Fig. 3-8tructure of crossed film cryotron. Typical dimensions: gate
film - 0.3 microns X 2 mm, Insulator - 0.4 microns, grid film
- 1 micron X 25 microns.
Newhouse, Bremer and Edwards: Crossed-Film Cryotron
400
I
GATE CURRENT
I
I
400
I
6Om~,/
300
.,
e
.....I
Z
LU
I
~ 200
I
<..>
I
I
I
GATE CURRENT /
0.91ma /
I
100
I
I
I
U')
:IE
::z::
o
a::
"v/
/
I
/
<..>
~
/
/
200.!.
<..>
z<[
/.
I
I
300
~
I
~
a::
I
100
I
-SHIELDED
---UNSHIELDED
40
60
GRID CURRENT - ma
Fig. 4--Comparison of electrical characteristics of unshielded and
shielded CFC. Shield insulation thickness = 4 microns. Grid
width - 30 microns, gate width - 2 mm, Tc - T = O.07°K.
257
to be expected, therefore, that the portion of the gate
film which can be made resistive by grid current action is that portion lying under the grid. The maximum calculated resistance of the shielded CFC is
shown dotted and is seen to be in fair agreement with
experimen t.
We will now show that the gain of the CFC i$
proportional to the ratio of the gate to the grid
widths. As mentioned abov
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