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Proceedings of the

EASTERN JOINT _COMPUTER CONFERENCE

December 13-15, 1960

New York, New York

Sponsors:
THE INSTITUTE OF RADIO' ENGINEERS
PrQfessional Group on Electronic Computers
THE AMERICAN INSTITUTE OF ELECTRICAL ENGINEERS
Committee on Computing Devices
THE ASSOCIATION FOR COMPUTING MACHINERY

Vol. 18

Price $300

PRIOR NJCC CONFERENCES

NUInber
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

Conference
Eastern
Eastern
Western
Eastern
Western
Eastern
Western
Eastern
Western
Eastern
Western
Eastern
Western
Eastern
Western
Eastern
Western

Location
Philadelphia
New York City
Los Angeles
Washington
Los Angeles
Philadelphia
Los Angeles
Boston
San Francisco
New York City
Los Angeles
Washington
Los Angeles
Philadelphia
San Francisco
Boston
San Francisco

Date
Dec. 10-12, 1951
Dec. 10-12, 1952
Dec. 4-6, 1953
Dec. 8-10, 1953
Feb. 11-12, 1954
Dec. 8-10, 1954
Mar. 1-3, 1955
Nov. 7-9, 1955
Feb. 7-9, 1956
Dec. 10-12, 1956
Feb. 26-28, 1957
Dec. 9-13, 1957
May 6-8, 1958
Dec. 3-5, 1958
Mar. 3-5, 1959
Dec. 1-3, 1959
M~y 3-5, 1960

PROCEEDINGS OF THE
EASTERN JOINT COMPUTER CONFERENCE

PAPERS PRESENTED AT
THE JOINT IRE-AIEE-ACM COMPUTER CONFERENCE
NEW YORK, N. Y., DECEMBER 13-15, 1960

Sponsors
THE INSTITUTE OF RADIO ENGINEERS

Professional Group on Electronic Computers
THE AMERICAN INSTITUTE OF ELECTRICAL ENGINEERS

Committee on Computing Devices
THE ASSOCIATION FOR COMPUTING MACHINERY

Published by
EASTERN JOINT COMPUTER CONFERENCE

National Joint Computer Committee

ADDITIONAL COPIES
Additional copies may be purchased from the following sponsoring
societies at $3.00 per copy. Checks should be made payable to anyone
of the following societies:
INSTITUTE OF RADIO ENGINEERS
1 East 79th Street, New York 21, N. Y.
AMERICAN INSTITUTE OF ELECTRICAL ENGINEERS
33 West 39th Street, New York 18, N. Y.
ASSOCIATION FOR COMPUTING MACHINERY
14 East 69th Street, New York 21, N. Y.

The ideas and opinions expressed herein are solely those of the authors, and are
not necessarily representative of, or endorsed by, the EJCC Committee or the
National Joint Computer Committee.

Manufactured in the U.S.A. by the Fifth Avenue Lithographic Associates, Inc., New York, N. Y.

Harry H. Goode
July 1, 1909-0ctober 30, 1960
Harry H. Goode, Professor of Electrical Engineering at the University of Michigan and a prominent leader in the activities of the
National Joint Computer Committee and several societies active in the
computer field, died in an automobile accident on the morning of October 30, 1960. His loss will be deeply felt by all who knew him through
his teaching, his frequent lecture appearances, &is- many publications,
his work in professional societies, his consulting activities, his stimulating participation in conferences, or directly through his warm friendship.
Professor Goode was born in New York City on July 1, 1909. He
received the B.S. degree in history from New York University in 1931,
and later earned the Bachelor of Chemical Engineering degree from Cooper Union in 1940
and the M.A. in Mathematics from Columbia University in 1945. His early professional work
was in statistics, and in 1941 he became Statistician-in-Charge for the New York City Department of Health. During the war years he was a research associate at Tufts College and worked
on applications of probability to war problems and also on the acoustic torpedo problem. From
1946 through 1949 he was on the staff of the Office of Naval Research at the Special Devices
Center, Sands Point, Long Island. Here he progressed through successive responsibilities to be
head of the Special Projects Branch. His work during this period was on flight control simulation and training, aircraft instrumentation, anti-submarine warfare, weapon system design, and
computer research. Through his O.N.R. work he was actively associated with such pioneering
computer projects as the Whirlwind computer at M.LT., the Cyclone computer built by Reeves
Instrument Company in New York, and the Typhoon computer built by R.C.A. Laboratories
for the Navy.
In 1950 he joined the Willow Run Research Center of the University of Michigan, serving
first as head of the Systems Analysis and Simulation Group, next as Chief Project Engineer,
and then as Director of the Center. Under his direction the Research Center carried forward
a broad program of research, including system design, computers, radar, infra-red, and acoustics,
and in the process doubled its size to 600 people. He guided the efforts of the Center through
problems in air defense and battle area surveillance, and was instrumental in establishing the
basis for the ground system for the Bomarc missile.
In 1954 he was appointed Professor of Electrical Engineering at the University of Michigan,
and in 1956 his wide range of interests brought a dual appointment as Professor of Electrical
Engineering and as Professor of Industrial Engineering. In 1958 he served for a year as Technical Director of the Systems Division of' the Bendix Corporation, maintaining a fractional
appointment in the University so that he could continue to teach his newly introduced course
on System Design. A little over a year ago he returned to full-time teaching and research
activities in the Department of Electrical Engineering.

iii

In addition to his wide range of services to the University of Michigan, Professor Goode
served as a consultant to industry and government, and was active in professional society affairs.
He brought to problems a keen insight and a rare ability for stripping away the non-essentials.
His advice was highly valued and widely sought. Among the firms for which he consulted
were the United Aircraft Corporation, the Bendix Corporation, the Auerbach Electronics Corporation, the DuPont Corporation, the Ford Motor Company, the Burroughs Corporation, the
Texas Company, and the Franklin Institute. He served the government on projects of the
National Bureau of Standards, the Post Office Department, the Air Force, and the House of
Representatives Appropriations Committee. For the Air Force, he was chairman of the W-117L
Committee on Advanced Reconnaisance; and for the House Committee, he served as a member
of the Study Group on Missile Reliability.
He served his profession as a member of the Administrative Committee of the IR.E. Professional Group on Electronic Computers from 1953 to 1956, as a member of the Computer
Advisory Committee of the Society of Automotive Engineers, and as a member of a subcommittee of the A.I.E.E. Committee on Feedback Controls. His most important service in this
area was as chairman of the National Joint Computer Committee of LR.E., A.I.E.E., and
A.C.M. In this latter role, he played an important part in the formation and formulation of
the charter of the International Federation of Information Processing Societies.
Professor Goode was a member of many societies - The Association for Computing
Machinery, the American Mathematical Society, the Mathematical Association of America,
and the Institute for Mathematical Statistics. He was a Fellow of the American Association
for the Advancement of Science and a senior member of the Institute of Radio Engineers. He
was also a member of Sigma Xi, Eta Kappa Nu, and Mu Alpha Omicron.
His many published papers touched upon statistics, simulation and modeling, vehicular
traffic control, and system design. His major published work is the book "System Engineering,"
of which he was senior author with R. E. Macho!. The book was an outgrowth of the very
successful and valuable course which he introduced at the University of Michigan under the
title, "Large Scale System Design."
Professor Goode's broad experience with computers and his participation in national computer functions led to his participation as one of the group of eight Americans who visited
Soviet computer establishments in 1959.
Our profession has lost one of its most outstanding members-a man of rare versatility,
talent, vigor, and vision.

FOREWORD
box office a diffe~ent picture emerges. Many of
these critics think that the primary benefit of
such a conference is the opportunity to meet ones
friends (or competitor s) in the halls and lobbie s
to exchange views and to pass on the latest inside information. At this conference we heeded
their advice and made an effort to assist this kind
of communication.

This volume contains the paper s presented
at the 1960 Eastern Joint Computer Conference
(the 'eighteenth Joint Computer Conference). In
order to make the Proceedings available at the
conference these pages were reproduced directly
from the authors' manuscripts by photo offset.
The papers which are presented here were
selected from among 130 that were submitted.
On the basis of 1, OOO .. word summaries Elmer
Kubie and his Program Committee selected
those which seemed of exceptional significance,
originality, timeliness and interest.

After each session there was a discussion
period of a new kind. There was some
space
available at the rear of the auditorium, and in
this space each speaker was stationed at a particular spot so that people could ask him questions.
These spots were to serve also as focal points
for the gathering of groups of people whose
interests were aroused by the paper s. Not only
could they talk to each other and to the speaker
but also they had the opportunity to form luncheon and dinner groups of people with congenial
interests.

A study of the records indicates that when
judged by the box office, the programs of the
EJCC seem to fill a need. The following graph
shows the attendance at recent meetings and
predicts the 1960 attendance from the known
growth in Boston, assuming that the growth in
New York would be at the same rate. The graph
also shows an alternate interpretation of the data
according to which there is no geographical effect
and really the situation is deteriorating. If the
first interpretation is correct, there is no hotel
in New York that can hold the EJCC. This is the
reason for the choice of the combination of the
Hotel New Yorker and the Manhattan Center
Auditorium. However, there is hope for a better
future since the projected Americana West Hotel
will be lar ge enough.

For nearly a year the committee member s
have worked with me on preparations for the
conference. I take this opportunity to thank them
for the many hour s of hard work and the lar ge
contribution they have made.

When the Joint Computer Conferences are
judged by the critics' notices rather than by the

Nathaniel Rochester
General Chairman

4,000
~
l,)

3,000

-- .... -

Philadelphia

-<
~
~

E-t
E-t

2,000

l,)
l,)

(Alternate
Pr edic tion)

Boston

to,

•

Washington
(Records Incomplete)
1,000
1955

1956

1958

1957

NATIONAL JOINT COMPUTER COMMITTEE

Chairman

Vice Chairman

Mr. H. H. Goode >!c
Department of Electrical Engineering
University of Michigan
Ann Arbor, Michigan

Dr. Morris Rubinoff
Moore School of Engineering
University of Pennsylvania
Philadelphia, Pennsylvania

Sec retary- T rea surer
Miss Margaret R. Fox
National Bureau of Standards
Department of Commerce
Connecticut Ave. & Van Ness St.
Washington 25, D. C.
AlEE Representatives

IRE Representatives
Mr. Harry H. Goode '60 - '61
Department of Electrical Engineering
University of Michigan
Ann Arbor, Michigan

Dr. Morris Rubinoff '60 - '61
Moore School of Engineering
University of Pennsylvania
Philadelphia, Pennsylvania

Mr. Frank E. Heart '60 - '61
Lincoln'Laboratories
Rm. B-283
Post Office Box 73
Lexington 73, Mass.

Mr. R. R. Johnson '60 -'61
Computation Laboratory
General Electric Co.
Phoenix, Arizona

Dr. Willis H. Ware '59 - '60
The RAND Corporation
1700 Main Street
Santa Monica, California

Mr. Claude A. R. Kagan '59 - '60
Engineering Research Center
Western Electric Company, Inc.
Box 900
Princeton, New Jersey

Dr. Werner Buchholz '59 - '60
IBM Product Dev. Laboratory
P.O. Box 390
Poughkeepsie, New York

Mr. Stanley Roger s '59 - '60
c/o Convair, Box 1950
Mail Zone 7-08
San Diego 12, California

ACM Representatives

Ex-Officio Representatives

Mr. Paul Armer '60 - '61
The RAND Corporation
1700 Main Street
Santa Monica, California

Dr. Harry D. Huskey
University of California
Department of Mathematics
Berkeley, California

Mr. Walter W. Carlson '60 - '61
Design Division
E.!. du Pont de Nemours
Wilmington 98, Delaware

Mr. R. A. Imm
International Business Machines
Corporation
Rochester, Minnesota

Mr. J. D. Madden '59 - '60
System Development Corp.
2500 Colorado Avenue
Santa Monica, California

Dr. Arnold A. Cohen
Remington Rand UNivAC
St. Paul 16. Minnesota

Dr. H. R. J. Grosch '59 - '60
415 East 52nd Street
New York, New York
Headquarters Representatives
Dr. J. Moshman
C.E.I.R.
1200 Jefferson Davis Highway
Arlington 2, Virginia

* Deceased

Mr. R. S. Gardner
Assistant Secretary
American Institute of Electrical
Engineers
33 West 39th Street
New York 18. New York

Mr. L. G. Cumming
Technical Secretary
The Institute of Radio Engineers
1 East 79th Street
New York 21, New York

EASTERN JOINT COMPUTER CONFERENCE COMMITTEE

General Chairman. • • • • • • •

• Nathaniel Rochester, IBM Corp.

Assistant to General Chairman

• Robert J • Haughey, IBM Corp.

Program

• Elmer Kubie, Chairman, Computer Usage Co.
Dr. Julius Aronosky, Socony Mobil Oil Co.
George R. Briggs, RCA Laboratories
Charles Doersam. Potter Instruments
Felix Kalin. International Telephone and Telegraph Co.
Roy Reach, Minneapolis-Honeywell Regulator Co.
Fred Warden, International Telephone and Telegraph Co.
Daniel M. McCracken

Publications • • • • • • • • • • • • • • Clem J. Rachel, Chairman, Remington Rand Univac,
Division of Sperry Rand Corp.
Noel K. Zakin. Remington Rand Univac, Division of Sperry
Rand Corp.
Richard T. Kanter; Remington Rand Univac, Division of
Sperry Rand Corp.
Publicity

• Jack Heaney, Chairman, Sylvania Electric Products, Inc.
James Lanigan, Sylvania Electric Products. Inc.

Exhibits

• Alan D. Meacham, Chairman, Gille Associates
Donald A. Boell, Gille Associates

Registration.
Hospitality

Hotel

• • • • • • . • • • • • • • • •

Jack Behr, Chairman, Packard Bell Computer Corp.
• Robert P. Fopeano, Chairman, Bendix Computer Division
of the Bendix Corp.
• Robert J. Williams, Chairman, IBM Corp.
W. W. Ward. IBM Corp.

Finance. • • • • • •

• A. I. Schott, Chairman, The National Cash Register Co.

Local Arrangements

• Benjamin W. Leavitt, Chairman, General Telephone &t
Electronics Laboratories
Allen L. Brown, New Canaan Research Center, Inc.

vii

TABLE OF CONTENTS
Page
"A Logical Machine for Measuring Problem Solving Ability"
by Charles R. Langmuir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

"A Method of Voice Communication With a Digital Computer"
by S. R. Petrick and H. M. Willett . . . . . . . . . . . . . . . ~ . . . . . . . . . . . . . .

"FILTER - - A Topological Pattern Separation Computer Program"
by Daphne Inne s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

,tRedundancy Exploitation in the Computer Solution of
Double-Crostics" by Edwin S. Spiegelthal. . . . . . . . . . . . . . . . . . . . . . . . . .

"A Computer for Weather Data Acquisition"
by Paul Meissner, James A. Cunningham and Claude A. Kettering ....

'tA Survey of Digital Methods for Radar Data Processing lt
by F. H. Krantz and W. D. Murray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

"Organization and Program of the BMEWS Checkout Data
Processor" by A. Eugene Miller and Max Goldman . . . . . . . . . . . . . . . . .

ItHigh Speed Data Transmission Systems"
by R. G. Matteson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Itparallel Computing With Vertical Data"
by William Shooman . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

III

"TABSOL -- A Fundamental Concept for Systems-Oriented
Languages" by T. F. Kavanagh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

117

3.3

ItTheory of Files It by Lionello Lombardi . . . . . . . . . . . . . . . . . . . . . . . . . . .

137

3.4

ItPolyphase Merge Sorting -- An Advanced Technique"
by R. L. Gilstad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

143

"The Use of A Binary Computer for Data Processing"
by Gomer H. Redmond and Dennis E. Mulvihill . . . . . . . . . . . . . . . . . . . .

149

"High Speed Printer and Plotter"
by Frank T. Innes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

153

itA Description of the IBM 7074 System"
by R. R. Bender, D. T. Doody and P. N. Stoughton . . . . . . . . . . . . . . . .

161

ItThe RCA 601 System Design"
by A. T. Ling and K. Kozar sky . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

173

1.1

1.2

1.3

1.4

2. 1

2.2

2. 3

2.4

3.1

3.2

3. 5

4.1

4.2

4.3

( Continued)

TABLE OF CONTENTS, continued
Page

4.4
4. 5

5. 1

5.2

5.3

5.4

5.5

6.1

6.2

6.3

6.4

6.5

"Associative Self-Sorting Mern.ory"
by Robert R. Seeber, Jr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

179

"UNIVAC - - RANDEX II - - Randorn. Access Data Storage Systern."
by G. J. Axel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

189

'tData Proces sing Techniques in Design Autorn.ation 't
by Dr. Williarn. L. Gordon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

205

"Irn.pact of Autorn.ation on Digital Corn.puter Design't
by W. A. Hannig and T. L. Mayes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

211

"Calculated Waveforrn.s for the Tunnel Diode
Locked-Pair Circuit" by H. R. Kaupp and D. R. Crosby ............ .

233

"On Iterative Factorization in Network Analysis by
Digital Corn.puter" by W. H. Kirn., C. V. Freirn.an,
D. H. Younger, and W. Mayeda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

241

"A Corn.puter-Controlled Dynarn.ic Servo Test Systern."
by V. A. Kaiser and J. L. Whittaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

255

"Hot- Wire Anern.orn.eter Paper Tape Reader ,t
by John H. Jory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

267

ItUse of a Digital/Analog Arlthrn.etic Unit Within a
Digital Corn.puter" by Donald Wortzrn.an . . . . . . . . . . . . . . . . . . . . . . . . . . . .

269

,tpB-250 -- A High Speed Serial General Purpose Corn.puter
Using Magnetostrictive Delay Line Storage"
by Robert Mark Beck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

283

liThe Instruction Unit of the Stretch Corn.puter"
by R. T. Blosk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

299

"The Printed Motor: A New Approach to Interrn.ittent
and Continuous Motion Devices in Data Processing
Equiprn.ent" by R. P. Burr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

325

LIST OF EXHIBITORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Back of Book

1
1.1

A LOGICAL MACHINE FOR MEASURING
PROBLEM SOLVING ABILITY

Charles R. Langmuir
The Psychological Corporation

Summary
The magnitude of costs incurred by assigning unsuccessful or even marginal personnel to
tasks involving EDP systems design and programming justifies a much greater effort in the selection of personnel than the use of conventional aptitude tests implies. A small desk-top
machine named the Logical Analysis Device is described, its logical organization is explained,
and its operation as a method of observing and
testing an individual's problem solving abilities is illustrated. Some comment describing
the wide variation of performance among several
hundred college graduates employed in various
professions is included but the principal emphasis is given to data pertaining to the performance characteristics of persons in computer
and data processing activities. The application
of the device is clearly indicated at the point
of evaluating final candidates for assignment to
tasks requiring a high order of logical and analytical talent.

*****
The talents, interests and aptitudes of individuals who become effective computer programmers are probably basically similar in all the
many varieties of EDP installations. In making
this statement, I do not mean to suggest that
all persons who are happy, successful, contributing workers in the computer profession are all
alike. Any such notion is patently absurd. I
do mean to indicate that there are certain essential characteristics which are common among
persons who are able to live peacefully, in comfort, and perhaps in joy, with modern computing
ma9hinery and the extraordinary variety of problems in which the machinery becomes involved. A
principal purpose of this paper will be the amplification of the idea in the opening sentence
including a statement of what the fundamental
characteristics of successful computer programming personnel are, and a description of a
method of observing, indeed, even measuring, an
individual's status with respect to these characteristic abilities.
When a computer installation is established
in a univerSity environment, individuals who
like this kind of thing seem to gather around it.
They simply gravitate to their center of attraction. After a time, and often quite a long time,
they either weed themselves out or they get into
a suitable orbit. To a less obvious degree, the
same kind of self-selection of computer person-

nel takes place in a scientific computing center,
including perhaps computer installations in industrial organizations which are primarily concerned with computing and data processing in the
so-called scientific categories.
In the business-type organization where the
computer installation is primarily concerned
with the processing of commercial paper work and
reports,the development of the personnel situation is somewhat different. There may be an initial surge of enthusiastic interest when the decision to install a computer is first announced,
but this is only superficially comparable with
the gravitation of personnel characteristic of
scientific institutions.
The difference between the university or
scientific-type installation and the commercial
or business-type installation becomes apparent
in examining the effects of the weeding-out process. In the business data processing operation,
weeding out of ineffective personnel is accompanied by much difficulty and all the pain that abnormal personnel readjustments call forth in business organizations. In addition to the organizational disruptions that occur, there are very
large dollar costs involved. These costs quickly
become great enough to justify the attention I
will suggest should be given to the initial selection of personnel.
When the personnel department calls you,
the supervisor, to announce that another candidate has appeared for the opening in the programmi,ng department, an important and costly decision is implied. When you hire your man for
training in this activity, you commit the organization to an investment not less than $5,000,
more likely $20,000 and perhaps a good deal more.
If, at the end of six, nine or twelve months,
you find your candidate is not going to make it,
the investment is a loss. If the man is marginal, a yet larger investment is required before
you will find out what the return may be.
Obviously then, if it is possible to identify the characteristics that are required for
successful accomplishment of the tasks involved
in utilizing a computer, it is economically important to employing organizations to know what
procedures ~an be effectively used. I shall focus my attention upon the characteristics I believe to be essential and shall present these
generally with an emphasis upon data proceSSing
rather than scientific computing. The abilities
I shall discuss are not those that involve spe-

2
1.1

cialized educational background and knowledge of
particular subjects such as college mathematics
or physical sciences. The academic background I
postulate as necessary is only that which we accept as the common heritage of the educated person in the modern world. On the basis of experimentally observed facts, we may have to reconsider the question whether certain intellectual
elements of importance in computer work are as
much a part of the common heritage as we would
like to believe.
What are these characteristics? First,
there is certainly some minimum ability to read.
Or to be more abstract, the ability to cope with
verbal notation. A second requisite is ability
to deal effectively with quantitative concepts
and numerical notation. It is certainly no detriment to a person to be able to handle literal
notation, but facility with algebraic manipulation is not included as essential. There is,
third, the ability to see relations, to see order in sequences, and perhaps the ability to enrich the understanding of details by seeing analogies and abstract classifications involving
order, symmetry and the permeation of common
characteristics in a background of seemingly independent elements.
During the last thirty or forty years, psychologists have developed efficient ways of testing individuals for their ability in these dimensions, particularly the first two, the ability
to read and the ability to handle numerical problems. It is, therefore, no problem to evaluate
applicants for computer programming opportunities
with respect to these abilities. We can certainly find out whether they can read well enough
to handle the language in a machine manual, and
we can find out if they are able to handle numbers in Simple arithmetic problems. The third
element, namely, the ability to see abstract relations, is not so well understood, but there
are tests available. The tests I speak of are
conventional paper and pencil instruments quite
widely available on the professional market and
well known in schools, colleges and employment
offices. One such test has been specifically
prepared by a computer manufacturer for use in
testing applicants for training as programmers.
Such tests have proved adequate for the initial elimination of candidates. They can be
economically used for screening among many applicants to eliminate those who are inadequate in
verbal or numerical reasoning abilities, and
probably to identify individuals whose verbal
ability reaches a high level but who have difficulty dealing with the abstract kind of content
or representations of a non-verbal character.
There is, however, abundant evidence that such
screening tests are not sufficient. Many individuals score above whatever cutting point we
may choose but still lack some crucial abilities
required for successful work in programming.
What are these crucial elements?
Certainly one is an acceptance of the idea

that systematic, logical, analytical processes
can converge on a solution to problems involving
complex logical relations especially in those
problems contaiping elements of dependent serial
order. A second crucial characteristic goes beyond the simple acceptance of analytical processes as a mode of problem solving but involves some
minimum power in utilizing analytical procedures.
Sufficient power is necessary to cope with a
multiplicity of elements and an ability not only
to analyze a problem into its elementary components but to synthesize the bits of information;
an ability to put the bits and pieces together
into a whole and to do so not by accident and not
by chance but with full understanding of the ultimately closed system.
There are, of course, other desirable abilities and traits of personality -- some that we
notice after the fact and that we have no success
whatever in forecasting. There are the individuals who simply get ideas. Things occur to them.
We do not see the mental machinery in operation
and we cannot find out much about it afterwards.
We call it intuitive creativity, and we are very
grateful for it when it occurs. But this rare
characteristic is out of reach, and I do not include it now within the domain of practical human engineering and certainly not in the incessant and mundane activity of routine personnel
selection.
It is possible, however, to obtain a quite
objective, very reliable estimate of a person's
ability to use logical methods in solving logical problems. The procedure involved presents
an individual with a logical problem, fully defined with respect to the rules of its logic;
one which is simple enough to comprehend in a
brief time interval, yet is complex enough to
represent a real challenge, and presented in a
form which makes observation of the performance
not only objective, but detailed in its step by
step development. By the simple device of presenting an individual with a sequence of several
problems graded in a series of increaSing complexity, we are able to observe both his characteristic preferences as shown by his choice of
problem solving procedures and his power in synthesizing final solutions to problems.

The Logical Analysis Device is a simple logical machine which can be used to observe objectively the performance of a person in'manipulating logical concepts and solving logical problems. The portion of the equipment of interest
is the operators display panel shown in Figure 1.
The operator is the person whose problem solving prowess is being tested. The examiner, who
must be a person qualified by experience and
training, presents an opening explanation with
demonstration. The full explanation requires
ten to fifteen minutes and incorporates a carefully organized demonstration with a practice exercise as part of the familiarization program.

3
1.1

The ~ic elements of a demonstration with
working equipment in real time cannot be simulated in any written material, but the following description does define the logical nature
of the problems and suggests, at least by implication, some of the dynamic elements that are revealed in individual performance records.
In the upper left corner of the display
panel, therel is an indicator light labeled TIME.
It is a cloci which shows the passage of time in
alternating intervals like day and night. The
light is on for three seconds and off for,three
seconds and then on again and so on continuously.
There are nine numbered lights arranged in a circle and one 'light in the center.
Next to each light in the circle, there is
a push button switch. ~Be switches are manual
inputs. Each switch has the effect of turning
on its associated light subject to an important
restriction. Each light is either a, day worker
or a night worker; it can be turned on at any
time during one or the other, but not both time
phases. When it is turned on, it will stay on
until the end of its active time phase. At the
end of its active phase, it will extinguiSh and
remain extinguished until it receives another
input signal.
The target light in the center has no associated manual input switch. It can be turned on
only as the consequence of some configuration of
the signal lights in the circle being on. Certain crucial information about the possibilities
is supplied by an information diagram. The arrows on the diagram link pairs of ·lights. The
existence of an arrow, as the one from light 3
to X, the target light, is information that
light 3 bas some effect on X. The relation is
not reversible,. i.e., in the example illustrated
the arrow from 1 to 8 states that 1 has an effect on 8 but 8 has no effect upon 1.
Any effect will occur at the end of the active time interval of the activated light and
will continue to hold through the following time
interval. For example, if the logical relation
is simple cause-effect, then turning on number 1
in its active period will cause number 8 to come
on in the following time interval. It is logically necessary that the lights at opposite
ends of any arrow be active in opposite time intervals.

There are three different logical relations
that may exist. The first is mentioned above-simple cause-effect - namely, turn this light on
and after a while the other light will come on,
and this one will go off. Obviously, any arrow
can be tested by experiment to find out if it
represents this effector relation.
A second relation is the combinor. If two
arrows converge on one light as 9 and 2 converge
on 1, neither one may be sufficient to turn on
1 but in combination they may. The existence of
this combining relation can be tested experi-

mentally, but the experimentation requires _a li ttle more planning and a little more logical sophistication-to be analytically complete than
does the simple try it and see experiment to
prove the simplest effector relation.
The third and last relation is the preventor. A light which has a preventor relation to
another negates the effects of any effector or
combinor relations upon the same light. The
fact that an arrow represents the preventor relation can be experimentally demonstrated but
planning and correctly executing the experiment
requires a greater logical precision than the
tests for the other relations. In the example
illustrated in Figure 1, lights 3 and 8 combine
to turn on the target but 3 and 8 and 7 do not
turn on the target. By such a sequence of
trials, we ascertain that 7 is a preventor and
the complete configuration necessary for turning on the target is 3 and 8 and not 7.
All the arrow relations can be investigated
and their specific nature, i.e., which one of
three, can be determined by experimental observation. In many cases the facts about a relation can be determined by logical deduction.
Hypotheses may be formulated on the basis of
partial information and tested.
Additional rules of the system are clarified, e.g., the existence of every relation in
a problem is represented by an arrow in its diagram; an arrow represents one and only one relation; when a light goes out the machine reverts
to its prior state and remembers nothing; and,
all problems are soluble. Thus, the logical
system is closed and completely defined. The
only facts the operator does not have explicitly defined in advance are the specific relations represented by the arrows.
After the system has been tully defined and
demonstrated, the7problem solving task is specified in three steps. First, find out what combination of lights turns on the target, i.e.,
investigate t~ arrows to the center. Second,
investigate the other arrows and thusdetermtDe
what relation each represents. Third, using the
information derived by logical deduction and experiment, synthesize a way of turning on the center light by some operations limited to the three
red buttons, numbered 4, 5, and 6 at the bottom
segment of the circle. Success on this last
step is the solution of' the problem. The operator, however, has complete freedom to choose
his method of procedure. He may skip over the
first steps as outlined if he wishes.
The operator works on the task in isolation
but he has immediate access to the examiner for
consultation; paper and pencil are supplied for
notetakingJ and he has a written summary of the
rules of the system for reference.
When the solution has been attained or after a suitable time if the problem is not
solved, the examiner interrupts the work and by

4
1.1

questioning ascertains the individual's comprehension of the logical structure of the problem.
In this quizzing process, the problem is reviewed in detail, and the effectiveness of the
back solution as a general method is demonstrated again.

Figure .2

If the problem was solved with explicit
clarity of understanding of the logical relations, the examiner presents a new problem of
greater complexity. If the problem was not
solved or was solved without evidence that the
logical structure was understood, a new problem
at the same level of complexity is presented.
This elaborate procedure is carried through
consistently and in as standardized a manner as
possible. The fUnction of the examiner is, in
fact, that of a non-directive instructo~ or demonstrator. The purpose of the carefUl and re-petitive instruction is to minimize and, if posSible, eliminate any bias in the evaluation of
the ultimate performance that might be caused by
accidental "sets" or rigidity in persisting with
an inappropriate initial choice of method. For
example, an individual who is interested in probability concepts may decide that an effective approach could ignore any analysiS of the information diagram as suggested by the examiner. The
solution involves only three switches, and he may
conclude that the possibilities are exhaustively
covered by a small number of experimental trials.
In such an instance, it is the task of the examiner to provide the operator with an easy opportunity to adopt a new approach. If an individual persists in using ineffective methods, we
are at least able to say that his rigidity is
no~ a consequence of lack of exposure to more effective procedures.

the logical structure. They are analogous to
noise in a circuit. They are indeed logical relations, they obey all the rules, but they are
irrelevant because they have no inputs other
than the manual switches. Thus, if an operator
makes a careful study of the information given
and applies the rules of the system, he will be
able to deduce that these three arrows can be
ignored.
Now look at Figure 3.
Figure 3

The whole process is demonstrated with the
problem represented in Figure 2. By experimental trial, the operator can discover that 9 and not
3 gives X. Light 3 is a preventor. In any order
that he chooses the operator can ascertain that
1 gives 3
2 gives 3 and 9
3 prevents X
4 gives 8
5 gives 3 and 9
6 gives 7
7 gives null result
8 gives null result
7 and 8 combine to give 9
9 gives X
Note the expreSSion "can ascertain." The operator has been shown effective methods, but this
fact does not mean that he will choose to use
them.
With this information which represents the
total logical structure of the problem, it is
easy to determine that the combination 4 and 6
will initiate a sequence of events that will
turn on the target light. Any attempt to use
light number 5 to activate 9 directly will set
up the preventor. Note also that the arrows from
lights 1 and 2 represent irrelevant elements in

The arrow diagram in this illustration is
the same as the one illustrated on the Display
Panel in Figure 1. The arrows in this diagram
are coded so that a Single solid line represents an effector, paired lines represent a combinor and crossed lines represent a preventor.
(This information is not supplied to the operator in actual practice. It represents the in-

5
1.1

formation he would be able to get by experiment
or deduction, or both.) The condition for the
target is clearly 8 and 3 and not 7. Byexamining the other information, it is readily seen
that light number 6 cannot be a part of the final sOlution. It provides a way of turning on
3 but it also turns on the preventor 7. Light
number 4 turns on 3 directly. We now ba'\l'e half
the solution, we need only to find out how to
turn on light number 8. By tracing the arrows
back, 8 to 1, and from 1 to the combinors 2 and
9, and from these lights back to light 5, we
see that the solution will involve the operation: turn on 5, wait, and turn on 4 at the
time 1 comes on.

Figure 4

Z-4

Z-3

Z-2

Z-1

ZERO

TIME

In actual experience with this problem, the
most usual first attempt at a solution involves
pressing buttons 4 and 5 simultaneously. The
result is not successful. The operator has to
become aware of the problem of phasing his operations on the lights. In the more complex
problems in the series, the operator has to get
similar, but more sophisticated insights. The
rules of the system are invariant, but the complexity of specific problems varies widely.
There are five levels of complexity in the
complete series of problems: the two demonstrated above which are used as learning exercises
and three levels beyond these.
It is an interesting demonstrable fact that
with such a simple logical structure it is possible to develop complexities sufficient to differentiate among college educated adults on an
ordered scale of 15 categories. The most difficult problem contains sufficient complexity to
provide ample opportunity to observe the methods
of work and the effective power of persons as
skilled in logical performance as top-notch programmers, logical designers, and systems analysts.
Almost every operator takes notes of some
kind. It is conceivable that some effects associated with the kind of notation system adopted
might introduce chance variation in the performance. The procedure~minimizes evaluation errors from this source by presenting a very powerful notation system to the operator after he has
had the experience of working the first two problems. The standardized system is shown as in
Figure 4. When in~tially written out, the arrows are undifferentiated. As information is
verified by experiment or deduction, the arrows
are coded. By logical analysis applied to this
convenient reorganization of the information diagram, it is possible to derive optimum sequences
of experiments that will converge on a solution.
Much repeated experience with the presentation of the notation system reveals a significant
finding. A large proportion of operators do not
make effective use of the recommended or any
other notation. Examiners get a strong impression that taking notes is some form of academic
"doodling," a kind of behavior that is approved

in the circumstances, whether effectively functional or not.
Evaluation of Performance
The LAD procedure incorporates a number of
elements of interest in psychometric technique.
The presentation is uniform, almost rigorously
standardized without being formally "canned."
The system strives to minimize the variability
of performance attributable to the examiner's
presentation. The individual's step by step performance is recorded by a remote printer. As a
consequence of this technique, the operator works
in isolation without any anxiety-inducing interactions resulting from the presence of an observer. The problems are real, logical structures and do not contain the tricky elements
characteristic of puzzles. The increasing complexity of the series of problems is achieved
without any change in the initially established
logical rules of the system. Parallel forms of
the problems at each level of complexity are
available. It is an interesting and important
fact that individual operators do not recognize
parallel form problems as logically identical,
even when they work them in succession. The
problems are specific configurations of a completely defined logical system. Successful solution of the problems is not dependent in any
way on substantive knowledge not within the experience of every educated adult.
The scoring of a completed problem-solving
session on LAD leads to a rating assigned on a
15 point scale from A+, A, A-, etc., down to E+,
E, and E-. This scale covers a range of performance from extremely powerful and efficient solutions to performances so ineffective that we are
unable to conceive of a performance that could be
demonstrably worse. The E rating indicates that

1.1
the operator was not able to achieve any success
with the least complex problem after 90 minutes
of repeated instruction and experience with parallel forms. The E- rating is reserved for operators who never catch on to the idea that one
light may be related to another. Such a record
occurs less than once in a thousand trials. The
entire E category, including E and E+ ratings,
represents very poor performance. About 4% of
our sample of employed adults fall in this category.
The first phase of the scoring procedure is
largely clerical. A count is made of the total
number of operations performed on each problem.
The total time worked on each problem is computed from the calibrated printed record. The
individual elements of the performance are serially numbered in the order in which they appeared in time. This standardized information abstracted from the original serial record is tabulated in an organized form that enables the examiner to see at a glance the basic elements of
the operator's record on each problem.

or better. The same statistical results describe
the comparison of ratings arrived at independently over an interval of a year or more. These
findings are important in considering the validity of the LAD procedure as a method of describing individuals. The examiners are able to reach
a scale of some kind of absolute judgment which
does not include individual bias and does not
drift with temporal effects over long or short
intervals. This happy result is not the normal
expectation in tasks that involve elements of
subjective judgment.
Experimental Results
Table 1 shows the results of scoring the performance records of 1109 adults employed in a
variety of occupations and 175 college students.
For simplicity, the subdivisions of the literal
categories have been grouped.
Table 1
Distribution of LAD Ratings
N=1284

These clerical procedures reduce considerably the amount of information a rater must consider, but the amount retained has proved to be
too formidable for any mathematical or mechanical
computation of a final score. The rater still
must consider the abstracted record and decide
on the basis of all the factors present which
point on the rating scale best describes the total performance. In addition to the highest
level of complexity successfully handled, and
the speed and the economy of effort in terms of
numbers of operations, the rater will consider
the approach to a major area. He will consider
whether the operator's approach is logically
sound. He will seek evidence that the operator
grasped the import of the results of his operations. Were all the major problem areas explored? Was the order in which they were explored logical? Were many repetitions required
before the operator planned his next experiment?
The possibility of answering such questions
about a person's problem solving efforts is a
unique aspect of the LAD performance record.
The ability of the rater is central to the
succesS of the system. The rater must be trained,
must be fairly logical himself, and must have had
enough experience with LAD procedure to apply the
generalizations about problem solving which are
contained in the ratings. It is an important,
experimentally observed, fact that the subjective
elements of the evaluation procedure are easily
maintained in statistical control. Different
examiners working independently in evaluating a
single series of performance records will, of
course, report different scores at least occasionally. The magnitude and variability of tneir
differences describes the reliability of the scoring process. In many hundreds of records, accumulated over a period of three years, the differences between raters exhibit a mean of zero and
a small variance. The correlation between pairs
of raters evaluating the same records will be .95

211

B
C

285
518
220
50

40
17
4

The typical or median value in the sample
is 8, equivalent to the letter category, C. The
variation within and between the sub groups that
comprise the total is large. The highest scoring group, a programming staff in an industrial
scientific computer department, obtained a median
score of 2, equivalent to an A rating. The lowest scoring groups obtain median scores of 11,
equivalent to a D rating.
These data provide background information
and nothing more. They describe the variation
we can expect to observe when we test people
with problems of this kind. They do not contain any evidence that performance in the miniscule problem solving situation is related to any
characteristics of people working in real life
situations. The possibility that important correlates may exist between behavior observed in
the test situation and behavior in the real
world is strongly suggested by the apparent similarities between reactions to difficulties in
LAD problems and behavior in the more complex
problems met in such real tasks as control engineering, designing logical circuitry, laboratory trouble shooting and computer programming.
In the LAD problems we-frequently observe
individuals who get "stuck in a rut." They exhibit a lack of flexibility that makes it very
difficult for them to abandon an ineffective approach. Other very typical difficulties include
overlooking side effects, miSinterpreting data,
abandoning systematic procedure under stress of
frustration, ignoring the outcome of experiments

7
1.1

which yield null results, jumping to conctusions
and assuming hypotheses are true, disregarding
alternate possibilities, forgetting or distorting
objectives, adopting a superficially logical but
actually absurd appr-oach, unnecessary or pointless repetition and preoccupation with redundant
or even random busy work. We have all observed
some of these characteristic barriers to optimum
performance in ourselves occaSionally and quite
frequently in others. These and other elements
in problem solving behavior frequently observed
in LAD testing are obvious analogies to actual
vocational tasks. Their existence provides a
rational basis for the hypothesis that behavior
exhibited by an operator's work with LAD exercises is an expression of stable, individual,
personal characteristics and that these characteristics which can be observed systematically in
the LAD procedure will also be characteristic
elements in the individual's working environment.
If the hypothesis is true, it should be possible
to find differences in LAD performance for groups
of people employed in real work which requires
dramatically different abilities even though it
is impossible to obtain reliable observation of
the important component elements in the individual's performance in the job.
Experimental data which meet the requirements
of dramatic difference in required abilities are
presented in Table 2.
Table 2
Comparison of Programmers
and Insurance Salesmen
X

Salesmen

Programmers

A
B
C
D
E

51
56
51
29

--1

190

4
19

Both groups are of comparable age. The
median programmer scores well up in the upper
half of the LAD scale (Md.n=B). The typical man
in the sales group scores in the lower half
(Md.n=DI- ) • Some individuals in each group have
certainly made a mistake in their commitment to
their vocational choice. If we were able to
identify them with assurance, the difference between the groups would be larger.
The difference between the groups is not a
Simple difference in problem solving power. A
detailed review of the records shows a striking
qualitative distinction in the procedures used
by most members of the sales group. There is a
popular conception that workers in tasks that
depend heavily upon inter-personal relations
utilize some special kin~ of logic--a peopleoriented as contrasted with a problem-oriented
thinking proceSs--sometimes thought of as intui-

tive and divergent as contrasted with objective,
logical and convergent. On LAD this different
mode of planning or decision-making procedure is
observed with great frequency among peopleoriented people as exemplified by sales representatives, including engineering sales, counseling psychologists and administrators in personnel management.
The typical performance of individuals in
this group is broadly described as non-analytic.
Almost everyone begins work on a LAD problem by
seeking, more or less systematically, the configuration of circle lights that activate the
target. We interpret the sequence of operations
involved in this phase of the task as an analytical informat.ion-seeking mode of attack. After
this basic elementary step has been accomplished,
the order of operations mayor may not be clearly
seen to be an orderly systematic extraction or
information which progressively reduces the number of unknown elements in the problem structure.
When this kind of logical sequence is observed,
we say the o~ator persisted in the analytic
mode _. However, such an obvious pattern may not
appear. In this case, we cannot classify the
mode of attack simply from knowled8e of the sequential order of the experimental operatiOns performed. The decision whether the mode is analytical or non-analytical depends upon the subsequent utilization of whatever information is
retrieved, and the operator's understanding of
the logical structure of the exercise at the end
of the working time. Non-analytical methods of
working LAD problems are accompanied by lack of
precision in identifying the structural elements
in the simpler problems and failure to achieve
solution at the more complex levels.

If the analogues between elements or LAD
performance and characteristic attributes seen
in programming skill are closely similar to aptitudes that are critical for c~ter work,
there should be an observable relation between
ratings of LAD performance and supervisor's ratings of the merit of individuals who have programming responsibility. The direct experimental
verification of the fact of such a relation is
not as simple a matter as it would seem at first
glance. Computer installations are young institutions. They differ widely in function,
type of data processed, administrative ~ganiza
tion, equipment, and experience with personnel.
There are no standards for evaluation of merit
on the job that are comparable from grOup to
group, and the typical group is too small to provide within itself evidence that is reliable in
the statistical sampling sense. Nevertheless,
it has proved possible to obtain some correlations between LAD ratings and supervisor's rank...
ings of individuals.
In five groups numbering 15 to 25 individuals in each, the correlation between the LAD
examiI1er's ranking and the supervisor's ranking
varied from .45 to .81. In two of these groups
the individuals were ranked a second time after
an interval of two years on the Job. In one of

8
1.1
these organizations, the correlation between the
supervisor's original ranking and his ranks assigned two years later was Rho=.50. The original and the follow-up correlations with LAD
ranks were .70 and .74. In the other group, the
original rankings supplied by a manufacturer's
instructor at the end of an extended training
program correlated .81 with LAD. The on-thejob ranking two years later correlated .80.
In four groups of smaller size varying from

6 to 8 members, similar correlations appear.
The typical values vary around Rho=.7. Higher
values may be expected in groups that range
widely from excellent to inferior. Lower values
are expected in homogeneous groups where the submarginal workmen have been eliminated. It has
also been found that correlations are higher in
groups where the ranking has been supplied by
supervisors who are themselves experienced working programmers.
The fact that the rank order evaluations of
performance on the job are not comparable across
groups makes any attempt to use the correlation
statistics in a practical regression equation
rather hazardous. On the other hand, correlation findings strongly support the view that the
LAD procedure could be used effectively in the
practical business of selecting the most promiSing among applicants and also for ascertaining
what proportion of an applicant group is likely
to meet some minimum standards of job performance
after training.

The first step in accomplishing this objective has been taken by establishing quite arbitrary, subjectively arrived at, specifications
of minimum acceptable LAD performance. After
analysis of the LAD record with special attention to the analytical elements characteristic
of the performance, we classify the individual
into one of four categories: 1. Highly recommended; 2. Recommended; 3. Marginal; and 4.
Not recommended. Stated in more elaborate language, the category Highly Recommended means
"This man will learn the computer rapidly. He
will not have difficulty or be confused by the
rigorous logical elements in understanding and
utilizing machine language and machine commands.
After formal instruction he will continue to
learn on the job from his senior colleagues and
from the day to day experience in office routine.
He will advance rapidly to assume independent responsibility for substantial programming tasks.
Most of the individuals who ultimately become
'creative programmers' will develop from this
category." The Recommended category means about
the same but with less rapid development, less
efficient de-bugging, less assurance of attaining
status of independent responsibility and less
likelihood of becoming an outstanding contributor to the organization.
Statements in this non-quantitative joboriented language are, of course, ambiguous to
some extent, but they seem to be meaningful to
supervisors responsible for computer operation.
However, it is extremely important to keep in

mind that such statements are forecasts of things
to come if appropriate training and opportunities
are made available. Since they are predictions,
they may be in error. Before the classification
of applicants can b~ acted upon automatically,
it is necessary to determine the truth value of
the statements.
It would be ideal to identify 1,000 persons
in each category, provide the programming opportunities, and then two or three years later count
heads and evaluate the work of the supervisors.
Real life circumstances do not make this experiment possible and the best approximation we ha~e
been able to achieve so far are less than definitive.
SUMMARY QE ~-UP RESULTS
Installation A
Report

LAD

Supervisor'~

1 disappointment, 5 achieved
independent responsibility
All good but surely not so good
as BR's
Do not get the idea

Installation B

1) slow but capable; 2) very
effective; 3) high powered;
4) top man in charge; 5) can't
get to know him
1) effective programmer, chief
debugger; 2) effective, flexible
Effective within limits and
under supervision
All comments negative or evasive
Installation C

All satisfactory. We decided
to take no chances.
Installation D

6
3

BR
R

All very
All good
the lIR's
Not much
to learn

effective
but not as good as
imagination and slow
new developments

Installation E
6

R
M

Estimates correct
1) marginal; 2) outstandingly
effective
Estimate correct
Installation F

3
5

3 outstanding, creative;
2 very good
2 outstanding, excellent; 7
good but not the best; 1 adequate; 1 mediocre
2 solidly good; 1 mediocre
2 mediocre; 3 poor programmer

9
1.1
The informality and non-comparability of
these supervisor's evaluations precludes the possibility of combining the results in a single
table of probabilities. The data do, nevertheless, suggest the magnitude of errors of two
kinds. Errors of the first kind occur when a
person who is predicted as Highly Recommended
proves to be a disappointment. This kind of
error for the Highly Recommended and Recommended
groups has occurred with small relative frequency.
Errors of the second kind, namely, discovering
excellent performance on the part of marginal
and not recommended candidates are less well
defined in the data possibly because there is

greater ambiguity and greater difference of
opinion and much reluctance connected with declaring disparaging evaluations.
Errors of the second kind, which reject a
candidate erroneously, are of much less economic
consequence to the employing organization,
whereas errors of the first kind involve losses
of important magnitude.
The writer concludes from the evidence so
far accumulated that the effort involved in using the LAD procedure results in a significant
economic pay-off.

Fig. 1. The Logical Analysis Device Operator's Display Panel

11
1.2

A METHOD OF VOIOE OOMMUNIOATION WITH A DIGITAL OOMPUTER
S. R. Petrick and

H. M. Willett

Air Force Cambridge Research Laboratories, AFRD
Bedford, Massaohusetts

Summary
A pattern recognition procedure for achieving
automatio identification of spoken words has been
developed and instrumented using an eighteen
channel voooder and a general purpose medium
soale oomputer, the AFCRL Cambridge Computer.
The process depends upon the representation of a
spoken word by a sequenoe of ootal digits whioh
describe the amount of instantaneous power in
eaoh of eighteen frequenoy bands at time intervals
of 1/50 second. Essentially, recognition is
aohieved by matohing suoh a digital representation
of a spoken word asainst a set of stored word
"masks", one for each wo-rd to be reoognized.
To develop such a set of masks (giving the
oomputer a particular vocabulary) the speaker
repeats a word several times. A mask is then
oomputed whioh optimizes a certain reoognition
parameter. The speaker must then type into the
oomputer the printed word he wishes associated
with his spoken word. This process oan then be
repeated to add other desired arbitrary words to
the oomputer's vooabulary. At present, using the
Cambridge Computer whioh has only 1600 magnetio
drum storage registers, this vooabulary is limited
for most purposes to 83 spoken words and requires
about one and one half seoonds per vooabulary
word for reoognition.
If the speaker's own voioe is used to
prepare masks of the words he wishes to be
reoognized, correct identifications are made
with almost 100 peroent aoouraoy. In other
oases the degree of success is highly dependent
upon the partioular individuals involved.
Other programs and prooedures which have
been tested, all dependent upon the basic word
reoognition faoility, inolude:
1.
The voioing of a word in one
language followed by its typewriter assooiation
in a seoond language, resulting in a orude word
for word maohine translator.
2.
A routine whioh enables a speaker
to say a sequenoe of words (from the set zero,
one, ••• , nine. plus, minus, times, braoket,
equals) whioh are followed by a print out of
the words spoken and the value of the expression
defined.
3.
A speaker reoognition program
whioh identifies the talker with appropriate

oomments as well as the word he spoke.
4.
An adaptive program whioh enables
the oomputer to automatically reorient itself to
a new speaker's voice.
Introduotion
The reoognition of digitalized speeoh
signals has reoeived oonsiderable attention in
recent years l,2,3,4,fi,6,7,8,9 for two good
reasons. First, many data processing problems
would be most oonveniently supplied with input
of a vocal nature. Examples are plentiful if
the vooal input-is sufficiently aocurate,
economioal, and general in application,1e., free
from limitations suoh as individual speaker
differences or i~bility to aooept oontinuous,
unsegmented speech. Applioation is, of oourse,
limited, if the vooal input does not meet the
previously specified qualifioations, but is not
necessarily precluded. This paper will present
the oapabilities and limitations of one possible
procedure for vocal oommunioation with a general
purpose digital oomputer, and it will be left for
the reader to supply the applioations, if any, of
interest to him which seem feasible.
A second explanation of the reoent interest
in speech pattern reoognition is that the
ourrent vogue fOr researoh in th& pattern
recognition area of artifioial intelligence
requires researoh vehioles. The ability to sort
unknown events or objects, eaoh described by a
set of numbers, into olasses or oategories defined
only by samples of their known members is basio
to maohine learning. Spoken word reoognition is
a partioularly good researoh vehiole in this field
beoause it can provide a wealth of useful data
for analysis and testing, because equipment exists
for producing digitalized speeoh, and because
there is a large relevant fund of knowledge in
the speeoh field whioh is of value.
Description of "EqUipment Used
On the Ohoioe of Input Data
Reoognition of any pattern by means of a
digital computer, whether arising from a speech
souroe, a printed page, or elsewhere, depends
upon finding a digital representation of eaoh
event whioh is to be considered. The digital
representation may oontain enough information
to synthesize an approximation of the original

12
1.2

event or objeot, or it may merely oonsist of
enough information to insure separation from
other members of the population with whioh we
are dealing. If we are interested in doing the
best possible job in a particular pattern
recognition applioation, the latter case is to
be preferred. Indeed, if we know or can
determine which charaoteristics to measure as
basic input data, the subsequent pattern
recognition prooedure can be made extremely
simple. In this case a short truth table is all
that is neoessary. This approaoh has been
applied, apparently very suooessfully, to
printed character recognitionlO , and it is also
being considered by several groups [or
application to speech reoognition. The truth
table approach, however, requires that the
pattern recognition be essentially done by
measuring equipment, carefully oonstructed to
solve & particular problem by ingenious human
designers. This approach is, therefore, not of
primary interest to researohers in pattern
recognition. However, for many praotical
applioations the best available measurements of
an object we wish ~o reco~ize will still
require truth tables of prohibitive size and
thus depend upon application of more sophisticated
pattern reoognition procedures. Speeoh
recognition seems to be one of these problems.
The data used in this study were of the
previously .entioned, highly redundant variety.
This is known because the digit stream of
numbers supplied to the computer have been
reassembled by a speech synthesizer into
intelligible speeoh. In faot, this equipment
about to be desoribed was oonstruoted as &
means of reduoed bandwidth voioe oommunication
with a human listener. The primary reason
these data were chosen is that they were
readily available. The degree of suooess of
the rather simple pattern reoognition method
of this paper on suoh redundant data would seem
to indioate a great promise tor rapid advanoement in oral communication with a digital
computer in the near future.
Speeoh Digitalizing Equipment
The first voooder was developed about
twenty years ago at Bell Telephone Laboratories
to investi~te improved methods of speech
transmission. In recent years, the military
servioes have sponsored oonsiderable reasearch
in speeoh bandwidth oOIllPresl.iOn..- in order to
squeeze more channels into the radi~ __spectrtlDl.
The voooder is basically a device which
converts spoken utteranoes to time - frequency
patterns of speotral energy. The particular
voooder used in this studl de~~~poses sound
energy into eighteen se~ents of the audiO
speotrum using a like number of bandpass
filters. 11,12 The output from eaoh of these
filters passes to a corresponding speotrum
analyzer whioh measures the power density of
the sound in its assigned frequenoy range.
The output from each speotrum analyzer is then

fed to an eleotronic time multiplexer whioh
samples the analyzer outputs at the rate of fifty
times per second. Eaoh of these magnitudes is
then converted into a three bit binary number.
It is thus seen that speech is converted to a
sequence of eighteen digit octal numbers at the
rate of fifty such numbers or speeoh "patterns"
per seoond. Figure 1 shows a block diagram of
this digitalizing equipment and ~igure 2 shows
a typical analog speech spectrograph and the
corresponding-digitalized speeoh patterns.
Digital Computer Usage
The patterns from the vocoder are read
directly into the AFCRL Cambridge Computer
through a real time data register. Each 1,"ittyfour bit patterh is deoomposed into 8ix nine
bit units whioh sequentially enter this ten bit
real time input register. The Cambridge
Computer is a 1600 word magnetio drum maohine,
a prototype of the Univao Solid State cromputer,
and its serial nature barely allow8 it to store
the input data as they arrive with no time
remaining for any simultaneous computation. It
is only possible to discard initial null patterns
and to count the number of patterns to be aooepted.
The limited storage of the Cambridge Computer
permits taking about fourteen seconds of speeoh
if storage is to be completely filled with data
or a lesser amount if data is to be processed
immediately.
In real time word recognition the speeob
input has been neoessarily limited to two seoonds
of speech during which an isolated word is to be
spoken. Upon storage of this data the oomputer
uses a set of empirioal" rules to determine the
boundaries of the digitalized spoken word,
eliminating extraneous baokground noise and
a~lowing for possible periods of silence within
a word. The data are next ~ime normlized so
that eaoh spoken,word is represented by a fixed
number of equally spaoed patterns. and the ootal
digits of these patterns are unpaoked and
oonverted to BOD d~gits. At this point the
computer is ready to use this digitalized version
of a spoken word tor either learning or
recognition.
Ope~ting Cha~cteristics

Of The System

The word recognition prooedure of this
paper oonsists of two modes, learning and
recognition. In the learning mode the speaker
pushes a button, initiating speech intake by the
computer, and speaks a word into tbe microphone.
After this procedure is repeated a predetermined
number of times, usually only onoe more, the
computer requests a type-in of the word which
has just been spoken. Following this labelling,
a mask or template is computed whioh cba~oterizes
this typed word. When this mask isaored in the
computer memory, the word it denotes is added to
the vooabulary of words which can be recognized.
After each mask is computed, the system is ready
for the next new word to be spoken.

13
1.2
When operating in the recognition mode with
a vocabulary comprised of previously computed
word masks, the talker asain pushes a button
and speaks his word. The computer identifies
and types this word, and the system is ready
to accept another spoken word. This recognition
is a~co~plished b~ selecting (us~ng the lis~_o£
stored masks) that word whose mask most closely
resembles the unknown word for which identifioation
is desired.

Alternatively, one could employ individual
thresholds for each mask, or a single
threshold for all masks, or perhaps a
combination of the above procedures. All of
these have been investigated, and some suffice
in one application but have disadvantages in
others. The procedure used in each application
will be inoluded in the discussion of that
a pplica tion.
Word Recognition Conclusions

Word Recognition Yethod Employed
The previous section used several phrases
including "which oharaoterizes this typed word"
and "most closely resembles" which must be
precisely explained. A number of ohoices could
be made as to how masks should be determined and
how they should be matched, and one cannot know
a priori which choices are best for the
application in question, digitalized word
recognition. The particular method used by the
authors which will be detailed below is only one
of many plausible alternatives. It would
admittedly not suffice for many pattern
recognition applications, but it has proved
useful in dealing with speech.
If we denote by Xij the i ~ speotral
comj)onent of the J th repetition of some word.
and if we denote by Yi the i th
speotral
component of a stored word mask, the criterion
ohosen for measurin~ the agreement_between
Xij and Yi is given by

C =

(L
1

L(Xi - Y i) Z

Xl Y i) /
i

If we sum over the various repetitions of that
word which are available for mask determining
purposes, and if we ask that the function
N

= (I

L Y i Xi j ) / L L( Y i-Xi j ) Z

1=1j=1

be maximized, we can find those mask oomponents
Yi which do this. The details of this
maximization will not be exhibited here, but
the desired components are given by
M
N
M
Yf = (.
X ij ) 2
X ij 2) /
~J = 1
i = 1 j = 1

M-

(L L

Ml.,(LX)2
i
1 j
1 ij

This mask is the desired optimal template in
the previously defined sense for use with
criterion C in effeoting a deoision procedure.
There are several reasonable decision
prooedures which could be used. In dealing
with a fixed vocabulary one oould oompute C
for each mask using an unknown word and then
ohoose the mask whioh produoed the largest C.

Results. Having specified the recognition
procedure to be used, the next question is, how
well does it work? Yore specifically, how well
does it work as a function of those parameters
at our disposal? These results were presented
orally13 at the Ootober meeting of the Acoustical
Society of America and they are currently being
assembled for written Qublication so merely the
highlights will be given here. Figure 3 shows
the effect of vary~ng the time normalization to
18, 9, 5, and 3 patterns per word. The restricted
vocabulary here consists of the -decimal digits
zero through ten, four samples were used in
computing each mask, the same speaker's voice
was used for both learning and recognition but
no utterance was so used for both, nine male
speakers are represented, all eighteen frequ~ncy
channels were retained, and the decision prooedure
was merely to select the decimal digit whose mask
produced the largest value of the previously
defined criterion C. The ratio of selection
indicated in figure 3 is the average ratio of the
vaiues of C for the best and next best words.
L _

Figure 4 shows the effect of ohannel merging
on word recognition. Adjacent channels were
averaged to give nine, six, and three frequency
channels for each of the time normalizations of
nine, five, and three patterns per word. The
other~pecifications as to vocabulary, etc. are
the same as already given for figure 3.
Figure 5 shows four typical oonfusion matrices
illustrating recognition of phonetically similar
words. The number n in a particular row and
column implies that the word in that column _s
s~oken and identified as the word in tha~ row
n times. One speaker was used throughout and
otherwise the specifications of the previous two
figures apply. Similar matrices exist ~or a
number of other frequency-time normalization
combinations and their principal results are
displayed in figure 6.
Summarizing briefly, very few recognition
errors are made if enough bits are retained and
if a single speaker is used both for mask making
and for subsequent recognition. If, however,
different individuals are used for learning and
recognition, the results are highly dependent
upon the individuals in question. Perro~rnanoe
varies from nearly perfect to consistently in
error for certain people and words. One solution
to this difficulty is to make up composite masks
from several good speakers. This has been found

14
1.2

to inorease performanoe but is not easily
meohanioally aooomplished sinoe a speaker may say
oertain words fine for the purpose of universal
recognition but say others quite ambiguously for
this purpose. Another solution is the adaptive
program to be described in the next section. It
will be seen, however, that this prooedure has
oertain limitations, and in these cases the
fastest way to insure good performanoe for a
partioular speaker's voioe is to make masks from
his voioe. Fortunately, this is easily acoomplished
for an arbitrary vocabulary by speaking directly
those words whose recognition is wanted.
Limitations.
In addition to the previously
enumerated accuracy limitations there are other
restrictions of the method of this paper which
should be carefully stated. One of these
concerns storage requirements. Using five
patterns per word and nine frequency channels,
six Cambridge Computer words of storage were
reserved for every desired vocabulary word.
Because of the Computer's limited storage, only
500 storage registers are available for mask
storage, limiting the computer vooabulary to 83
such vocabulary entries. The remaining Cambridge
Computer storage is used as follows: 200 registers
for the recognition program, 200 words of
temporary storage for the unknown input word and
100 registers for its time and tre~u~~c~ normalization, 200 storage registers for the real time data
input program, 200 registers for decoding the
scrambled input bits and converting them to BCD
characters, 100 registers for elimination of
coughs and background noise, and 100 registers
for storage of alphabetic responses.
Of course, if more storage were available,
input durations of more than two seconds would be
feasible, assuming real time recognition were not
possible on a word at a time basis. Words must
still, however, be spoken in isolation or else
continuous speech must be segmented into words.
Work on the segmentation problem is presently
under consideration by various groups.14
A final limitation that will be mentioned is
computation time required. This depends, of
course, upon the number of masks in storage.
Using the rather slow drum oomputer of this study
about one and one half seconds per stored
vocabulary word (5 patterns - 9 channels) are
required. This figure would be cut by a faotor
of about 100 if a computer of IBM 704 speed were
used. If we are satisfied with successive words
oocurring no faster than every n seconds, we
could then aohieve real time recognition on a
word at a time oontinuous basis for a vooabulary
of about 66n words.
Demonstration Programs
Basic Word Recogni1t>n Program.
It has been
seen that the basic recognition computer program
previously described allows one or more speakers
to build up a working arbitrary vooabulary with
a minimum of time and effort merely by speaking
each word into a microphone several times.

Initially, the oomputer requests the user to
type the number of patterns per word he wants
for time normalization and to also ~ype the
number of word repetitions to be used for the
computation of eaoh mask. When this information
has been supplied, the first word may be spoken.
Prooessing of each repetition of a word takes
about three seconds. Following the computer's
request for alphabetic labelling of a spoken
word, the mask and oorresponding alphabetics
are punched out on paper tape. The system is
then ready for the next word to be spoken. When
masks have been made for all desired vooabulary
words, recognition can proceed for those words.
The limited storage of the Cambridge Computer
necessitated separate programs for mask making
and subsequent reoognition. Aooordingly, to
proceed, the recognition program and desired
vooabulary must be read into the oomputer.
Channel merging, if desired, can be aooomplished
while the data are being entered into storage.
The deoision procedure used for this
demonstration program seleots a word immediately
provided the value of C i~masks produoes is
higher than a given absolute threshold. If no
decision is mad~ in this manner, the word whose
mask produced the highest C is seleoted
providing this value is greater than a lower
threshold. If the best choice is below this
minimal threshold, the computer requests that
the word be repeated asain. The thresholds
were empirically selected, and values were found
which produo~d very tew requests for word
repetitions and virtually no false identifications.
Language Translation Program.
In order to
effeot a orude word tor word translator from some
spoken language to a different written language
it is obviously only necessary to ohange the
alp~betics used for displaying_words reoognized.
This was done as a demonstration for the authors'
Laboratory Chief using the German decimal digits
null through zehn as spoken input and English
numerals for printed response. Suffioient
similarity was found between the German
pronunciation of the demonstratee and demonstrator,
whose voioe was used to produoe the masks, to
permit translation for both without error. This
exeroise was, of oourse, limited to a relatively
small sample Size, and while it may not prove
muoh about the effeotiveness of the word
reoognition prooedure of this paper, it would
seem at least to indicate that the author in
question's German pronunciation couldn't be too
bad.
Speaker Recognition Program.
It was observed
that the indices C obtained were oonsiderably
higher when the same individual was used for both
mask computation and subsequent recognizing. This
was exploited to effect speaker reoognition of
individuals speaking from a restricted vocabulary.
In one exercise nine male and seven female voioes
were used to produce masks for the words "one",
"two", and "three". Nine frequency channels,
five time samples per word, and four word
repetitions were used for each of the forty-eight

15
1.2
masks. Different word repetitions were utilized
for the recognition phase. ~ch of the sixteen
speakers spoke, "one", "two", and "three" several
times, and the choice of speaker and digit spoken
was made solely by selecting the largest value of
the index C. Figure 7 shows the results of this
study. The numbers in each box indicate the
sample size and percent of successful
identification.

= n/d from the mask whioh maximizes Q, we
should find that C approximates Q beoause
n/d =-= 11' / d
_ if nand dare clOSG
in value to nand d. This reasoning prompts
us to consider BQ, 0 < B < 1
as a
threshold against which C may be compared. The
other constant A was added to BQ strictly for
empirical reasons.

Encouraged by these results, a speaker
recognition program was written for demonstration
purposes, using the previous forty-eight word
masks. With this program an unknown speaker says
his word into the computer and obtains one of the
following types of responses: "That was John
Jones speaking the digit three; I don't know who
you are, stranger, but you spoke the digit two'
I don't have the slightest idea. who you are or'
what you said; speak more distinctly and repeat
your word again, please." The remaining
possibility, "I don't know what you said, John
JOnes, but I recognize you", is not currently
allowable but is under active consideration and
it appears to be feasible with at least a f~ir
degree of success.

If index C does not exceed any threshold
A + BQ. the best ohoioe of one, two, or three
is made for each speaker, and if at least p of
the speakers agree on the same choice, this digit
is seleoted and the speaker is assumed to be
someone not represented by a stored mask. If
less than p speakers agree upon the digit
spoken it is assumed that a word other than one,
two, or three was spoken. Finally, word repetition
is requested only when some probable source of
trouble is detected in the input program such as
improbable length of the spoken word.

The decision procedure used for the above
program is the following. Each of the
categories involving both a specific speaker
and spoken word are selected only if their
associated value of the criterion C exceeds a
threshold of the form A+ BQ where A and B a;re
constants and Q is a number associated with each
mask and computed at the same time as the mask.
This is actually the same maximal Q whioh was
previously defined. It can be shown that the
maximal value of Q is given by
Q =

2.(

K.J"M

-1 )

f f

M
X
) 2.
where K2.=
X/, /
ij
i::.1j=1
j i=l j
1
and this expression is the one which was used to
compute Q. The primary reason for using Q is
empirical, but it was suggested by the fol£owing
qualitative thinking: ,Q is of the form

~ (I

(n1 + n2. + ••• + n M ) / ('\ + d2. + ••• + ~)
and if each of the M word repetitions in the
sample are sufficiently similar, each nj
and
dj will not differ excessively from
n =

(M-

j~ 1

nj )/M

and

Under these assumptions we can approximate
by

MI d

or""lf

I d.

If we now compute a value of the criterion

Scope Display Program.
One of the
distinctive output features of the Cambridge
Computer is a large 19 inoh three color (red,
blue, green, and combinations thereof) scope
display unit. This was used to allow easy visual
scanning of spectral word representations. The
horizontal axis is the time axis and the vertioal
axis is used for frequency. At any interseotion
the color of the point denotes magnitude of
spectral energy with several color ooding ohoioes
available. Input may be either from punohed
paper tape or real time from the microphone. This
program was ~ound to be of value not only for
quickly insuring that all equipment involved is
working all right initially, but also for
diagnosing exoessive noise and obtaining useful
information about the structure of oertain digital
word representations. For example, in examining
the similar words bit and beat for one speaker it
was discovered that he inserted a prominant period
of silence before the final stop oonsonant in the
word beat but did not do so for the word bit. This
indicates machine separation of those two words
for that speaker was based on more than the phonetic
vowel difference between -e- and i
Arithmetic Expression Evaluation Program.
This program utilizes a vocabulary
consisting of the decimal digits zero through
nine and the operation symbols plus, minus,
times, bracket,and equals. The decision
procedure used is the same as that for the
previously described basio word reoognition
demonstration program.
In using this program the speaker makes up
a meaningful arithmetio expression from the
allowable input words. Each word is sequentially
recognized and symbolically stored until the word
"equals" is enoountered.
At this point the
expression is evaluated, multiplioation first
and then addition and subtraction in cases not
speoified with brackets. The entire expression
understood by the oomputer is then typed followed
by its computed value. Examples run on the

16
1.2

computer include:

2+2 [13-5]*6 -

4
48

123+456*3-2*[26-23]+35*[165-166]-4
1446

314*[1327-64*21]*[129*4+62*72*2-89*43]
+[43*2196]-17-[26-24*3+4]*[7-9] -29889219

Adaptive Reorientation Program.
While the
method of this paper was found to be very
successful when the same speaker's voice was
used for both mask computation and word
recognition, results are less consistently
successful when different voices are involved.
To eliminate this difficulty, two adaptive
programs were written, both designed to convert
a set of masks made from one speaker's voice to
a set corresponding more closely to a new speaker.
One of these programs requires the use of an
operator to make certain decisions and the other
program operates independently of an~ human
intervention. In both cases the masks of words
taken from one or a group of speakers constitute
the computer's vocabulary. An unknown speaker
then says a word which mayor may not be
represented in the vocabulary.
In the first case, the ratio of the highest
value of the agreement index C for this word to
the next highest C is taken, and this value,
R, is compared against a set of thresholds. If
R exceeds the hi2hest th~eshold. the comDuter
prints the recognized word and awaits the next
word. If R fails the highest but exceeds the
next lower threshold, the computer prints its
choice and asks the operator to indicate if this
choice is right or wrong. If the correct choice
is made, a fraction fl of the word is averaged
into the mask for that word. If, however, the
wrong choice is made, the operator types the
actual word spoken into the machine. The
computer then scans its vocabulary to see if that
word is represented. If the word is already on
the vocabulary list, a larger fraction f2' is
averaged into the mask. If, however, the word is
not found. it is added to the end of the
vocabulary, thus becoming the mask representation
of that word.

word be repeated. If a word is missed more than
once, the fraction of the word which is averaged
into the mask is increased. After n misses,
the computer either stops or, at the option of
the user, discards its earlier attempts and
replaces the mask by the last repetition of that
word.
The second learning program, as mentioned,
operates without human intervention. Again the
ratio R is computed from the two highest values
of the agreement index C. Similarly, if R
exceeds this program's highest threshold, no
adjustment is made. However~f R fails to
exceed the lower threshold, the word is rejected
and no adjustment is made. In any other case,
the fraction of the word to be averaged into the
masks is determined from the value of R obtained.
This fraction is taken to be 3/4 when R equals
the lower threshold and decreases linearly as a
function of R to zero when R equals the
higher threshold.
The results obtained from running both
adaptive programs seem to indicate that the
programs are of practical value as a means of
obtaining new masks only when the initial
agreement is substantial. With operator
intervention, of course, successful conversion
is always achieved. but if a minimum of human
participation is required, the making of new
masks from scratch is to be preferred. The
other adaptive program mayor may not converge
successfully to the new speaker's voice. One
approach which might improve the performance of
both programs involves the previously mentioned
use of composite masks made from several good
speakers.
As an example of a typical attempt to
convert from one speaker's (WO) voice to
another's (AP) and back without operator
assistance the following run is presented. A
mask for the single word "one", "two", and
"three" spoken by WO. The procedure here being
followed using taped input words is to repeat
the identical utterance if R lies between the
two thresholds. The two values chosen as
thresholds here were two and ten.
Step
1
2
3
4

5
6

If neither threshold is exceeded, the
computer asks the operator to identify the word.
Again the vocabulary list is scanned and the
proper mask, jf' found, is adJus ted by a still
larger fraction f 3 • Also, if the word is not
found, it is added to the vocabulary.
If the mask has been adjusted (i.e.,in any
case except the first where the highest threshold
has been exceeded), the computer asks that the

7
8
9

10
11
12
13
14
15
16
17

Speaker
AP
AP
AP
AP
AP
AP
WD
WD
WD
WD
WD

AP
AP
AP
AP
AP
AP

utterance
5
6

7
7
8
8
6
7
8
9

10
5
5
6
6

7
8

R
1.63
1.84
2.31
) 10
3.21
) 10
1.8
1.65
1.5
1.99
1.54
6.0
)10
5.72
)10
)10
)10

17
1.2

In steps 1 and 2 AP's utterances did not
produoe enough agreement with WO's "one" to
exoeed the threshold two. Accordingly no action
was taken. The next utterance (utterance seven
in step three), however, gave R = 2.31 causing
the first mask modification to be effected.
Repeating this same utterance now gave a value
of R in excess of the upper threshold (step 4).
Step 5 again modifies the mask. In steps 7
through 11 WO is speaking "one", but recognition
is too poor to oause any mask modification. in his
favor. In steps 12 through 17 AP's utterances
are again repeated until no more modification is
made.

D. B. Fry and P. Denes, "Experiments in
Mechanical Speech Recognition," Informtion
Theory (Butterworths Scientific Publications,
London, 1956), pp. 206-212.

D. B. Fry and P. Denes, "On Presenting the
Output of a Mechanical Speech Recognizer,"
Journal of the Acoustical Society of
America, V 1. 29 (1957), pp. 364-367.

G. W. Hughes and M. Halle, "On the
Recognition of Speech by Machine,"
Proceedings of the June 1959 International
Conference on Information Processing, Paris,
(Butterworths Scientific Publications,
London, 1960).

Conclusions
The method of this paper seems feasible
for those applications where words are spoken
in isolation by a speaker whose voice was used
to prepare msks. These masks may be made
rather easily and retained for each talker who
wishes to be able to communicate orally with
the computer. The limited storage capacity of
the Cambridge Computer restricted the size of
the vooabulary possible at anyone time.
However, the observed discrimination between
phonetically similar words seems to indicate
that words could be recognized from a larger
vocabulary. Use of a large scale computer and
a 500 word vocabulary is presently under
consideration.
Acknowledgments
The authors are grateful to C. P. Smith
and his group who developed the vocoder system
employed and operated this equipment whenever
speech data was taken. The scope disnlav
program and real time input program were
wrl~~en Dy F. H. CoOk, who also assisted in
designing input equipment necessary to read in
real time da ta •
References
1.

X.H. Davis, R. Biddulph, and S. Balashek,
"Automatic Recognition of Spoken Digits,"
Journal of the Acoustical Society of
Amerioa, Vol. 24 (1952), pp. 637-642 and
Communioation Theory (Butterworths
Scientific Publications, London, 1953),
pp. 433-441.

J. W. Forgie and G. W. Hughes, " A RealTime Speech Input System for a Digital
Computer," Journal of the Acoustical
Socieity of America, Vol. 30 (1958},p.668.

D. B. Fry and P. Denes, "Mechanical Speech
Recognition," Communication Theory
(Butterworths Scientific Publications,
London, 1953), pp. 426-432.

M. V. Ma~hews and P. Denes, "Spoken Digit
Recognition USing Time-Frequency Pattern
Matching," Journal of the Acoustical
Society of America, Vol. 32 (1960), p. 914.

H. F. Olson and H. Belar, itA Phonetic
Typewriter," Journal of the Acoustical
Society of America, Vol. 28 (1956) pp. 10721081.

G. Sebestyen, "Automatic Recognition of
Spoken Numerals," to be abstracted in
Journal of the Acoustical Society of
America, V 1. 32 (1960).

10. "The Voracious Eye", Time Magazine, Vol.
LXXVI No. 10, Sept. 5, 1960, pp. 69-70.
11. C. P. Smith, "Speech Data Reduction,"
AFCRC-TR-57-lll, ASTIA Document No.
AD117290, May 1957.
12. C. P. Smith, "An Approach to Speech
Bandwidth Compression," Proceedings of
Seminar on Speech Compression and ProceSSing,
AFCRC-TR-59-198, Vol. 2, Sept. 1959.
13. S. R Petrick and H. M. Willett, " Digital
Automatic Word Recognition Procedure," to
be abstracted in Journal of the Acoustical
Society of America, Vol. 32 (1960).
14. J. W. Forgie and C. Forgie, "Segmentation
Scheme for Use of a Speech Recognition
Computer Program," to be abstracted in
Journal of the Acoustical Society of
America, Vol. 32 (1960).

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1.2

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21
1.2

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lemented, the
new status of the puzzle is verified. What this
rather poorly chosen word connotes is a check of
each word in the puzz1e, wherein poor threeletter combinations and invalid short words are
noted disapprovingly, and good two-and threeletter combinations and full words receive due
reward, "gold stars" being marked down for theJl'

43
1.4

in a special record. I will have more to sfq
about these gold stars when I discuss the key
process of action scoring. After the gold stars
have been handed out. the program glances over
the puzzle to see if, perchance, all the characters have been filled in. If they have not, the
next stage of the decision process is initiated
by the re-entry of the program to the uppermost
box on the fLOW chart. The little boxes lying
off the path I have just beaten were discussed
earlier when I spoke of the negative actions open
to the program.
It is almost time to discuss ~he heart of
the Decision-Sequencer, namely, the scorlng
process and its associated verification process.
First, though, I should like to answer an objection which might be raised at about this pOint.
I am presumably claiming that my consistency
criterion allows me to rank finished DoubleCrostics as to their acceptability. This is
certainly implied by my use of a numerical score
which I compare with a threshold to determine
if a finished puzzle is acceptable. Why then, it
might be asked, do I not simply try all the combinations of the given definienda, and accept the
best scoring configuration as the solution, thus
rendering all this scoring and verification
folderoi nugatory? In fact, the objector might
add, if you would only guarantee that the correct
definiendum is included in every definienda list
then you could also dQ away with all your guesswork. Dropping now my role of Devil' s Advocate,
let me answer the second point by noting that,
in the bread and butter type problems which I'm
working towards, the analog of the correct
definiendum. is not, and cannot, always be included in the relevant list. As to the exhaustive approach suggested in the first part of the
objection, I have the law of exponential growth
on my side. For example, I shall presently show
you the solution process for a Double-Crostic
somewhat more challenging than the example I first
,showed.. There are only 18 definiens for this
puzzle, one of which had three definienda on its
list, the other 17 having only two definienda
each. This is a total of only 37 definienda,
but the number of combinations which I would have
to try in accordance with my critic's suggestion
is something over 393,000. In the particular
solution process I shall sketch later, 33 positive
actions were taken, four of which were incorrect
and were subsequently cancelled by four negative
actions. The total machine time for this solution process, including a detailed tape printout
at each stage, was about 30 seconds. There seem.q
then to be some point in employing to folderol
which we are about to discuss.
In the scoring process, an essentially qualitative value judgment is given quantitative
form. This is by no means equivaJ.ent to a transition from subjectivity to objectivity. The best
one can do is to minimize the area in which subjectivity operates and to limit the scope of its

activities in that area. In the concrete case
of Double-Crostic solution, subjectivity impinges
in two WfrJ'S on the scoring process: it affects
the choice of the factors deemed to be relevant,
and it enters into the assignment of relative
weights to those factors. In setting up the
earlier Decision-Sequencers, I allowed my intuition free plfq in both these directions. I
"felt" that the relevant factors, in scoring some
action for a given word, were the total length
of that word, the number of characters, already
f{lled in that word and the number of gold stars
already accumulated by that word. I then multiplied these numbers by seemingly "reasonable"
coefficients, as a function of the particular
type of action being scored, and then added a
fudging factor, again as a function of the type
of action. Oddly enough, I still managed to
solve some Double-Crostics this way. However,
having no coherent rationale for this scoring
scheme, I certainly had no clues as to how it
might be generalized so that I might apply it to
the problems in which I was really interested.
Furthermore, while I could applaud my intuition
when the program solved a Double-Crostic, I could
not explain the cases where the program failed.
I could, of course, blame my intuition, but
this would hardly have been constructive criticism. In the seventh, definitive, DecisionSequencer, the choice of relevant factors is
dictated by a coherent underlying philosophy,
and the assignment of weighting coefficients,
while still arbitrary to a certain extent, is
nonetheless constrained by considerations stemming from this same philosophy. I use the term
"philosophy" because the concepts are general
ones, and must be properly specialized so as to
apply to the given concrete case. I cannot pretend to you that the general philosophy has
been worked out fully. I shall therefore
restrict myself here to its specific application
to Double-Crostic Solution.
Viewed cold-bloodedly, a Double-Crostic is
seen to consist of two sets of hypothesis sets,
each Text word and each definiendum being considered a hypothesis. Initially, some of these
hypothesis sets may be vacuous, and the nonvacuous ones need not contain the correct entry.
It is assumed, rather vaguely, that an "adequate"
number of hypothesiS sets do contain the proper
entry. An acceptable final state will be one
where exactly one hypothesis will have been
chosen for each hypothesis set, where some reasonable proportion of the final hypotneses will
have occurred as initial hypotheses in their
respective hypothesis sets, and where each final
hypothesis will be a good English word. The
first reqUirement, of course, simply restates the
obvious fact that no "puzzle is conmlete that
does not have all its characters filled in. The
second requirement imposes the need for one of
the threshold values which I have previously
discussed. The third requirement can be phrased
somewhat more discursively as follows: only

44
1.4

some tiny percentage of Text words less than four
characters in length may not match up with dictionary entries; no definiendum may give rise to
too few good two-letter or too many poor threeletter combinations on the Text side of the
puzzle, while a similar constraint is imposed on
the Text words concerning their effect on.the
Definition side of the puzzle. A human puzzlesolver certainly imposes more constraints on
the final solution than those I have enumerated.
For instance, he would presumably reject a fourletter combination such as D E X C since no
English word contains this particular sequence
of letters. The Decision-Sequencer, however,
does not check for four-letter combinations, and
would find the two triples D E X and E X C to be
perfectly legitimate. Similarly, the machine
would not take exception to the phrase YOU
I S, although most Double-Crosticians might.
The point here is that what is redundancy for
the goose can be startling news to the gander.
It is in the verification portion of the Decision
Sequencer that redundancy factors are checked.
It is in the scoring portion that the decisions
are made which will tend to give the greatestfield of action to the verification process at
each step. That is, all other things being equal,
the scoring process will, or at any rate should,
present the verification process with the most new
two-and three-letter combinations, short words
and full words as possible. Sheer numbers alone
cannot be used. Two pairs of letters, for
instance, are not nearly as potent as two
triples. On the other hand, two triples are not
fifty times as potent as two pairs. Thus, while
the relative weights of these two factors can
be chosen somewhat arbitrarily, the range of
variation is not particularly great.
It should be clear that any scoring process
will automatically tend to fulfill the first
two requirements on the solution, since the
actions which are scored are all positive actions,
entailing the filling in of more characters, and
are all based on the use of hypotheses which
lie in the original hypothesis sets. The burden of meeting the third requirement, the one
specifying that the final result will be "good"
English, falls on the verification process
primarily. Apart from the final glance at the
puzzle in which the progrgm reassures itself that
the chosen hypotheses have been sufficiently
"fruitful", it is the verification section which
does the lion's share of "error" detecting. Thus,
if efficiency were not an operational requirement, the entire scoring pro.cess could be
replaced by a random number generator for the
selection of the next action to be implemented.
Efficiency, however, is a major requirement,
perhaps the major requirement. How, then, do we
construct an efficient scoring procedure? First,
as noted, earlier, we try to present the verification process with that action which, when
implemented, will provide the greatest sum of
weighted redundancy factors, everything else

being equal. Second, we analyze these other
things which may or may not be equal. One of
these things is the gold star count already
compiled by the relevant hypotheses. For
example, if several cammon characters of a given
definienda set had already been filled in,
leading to all sorts of nice two-and threeletter combinations on the Text side of the
puzzle, it would presumably be safer to guess one
of the definiendum of this set than to guess a
definiendum of another set which had thus far
been unproductive. Another cogent factor is the
length of the possibility list of each of the
contending hypothesis sets. The contention here
is that, all other things again being equal.
the shorter possibility list should be attacked
first. The reasoning here, as you will see, is
somewhat tenuous. Given two hypotheSiS sets,
one with two entries on its possibility list,
the other with three entries, we might argue as
follows. We do not know whether either list
contains the correct entry. Therefore, we might
just as well assume, for the sake of argument,
that the correct entry is contained on each list.
If we are fortunate enough to choose the correct
entry from the list we select, then it will have
made no difference which list we chose. If our
choice of entry is not correct, however, we can
hope that the verification process will cause
its erasure sooner or later. If we erase one
possibility from the two-entry list, we are
presumably left with the unique correct entry.
If, on the other hand, we erase one possibility
from the three-entry list, ve still have to
make a choice between the remaining entries.
To this argument we must add the consideration
that each positive action on one side of the
puzzle will entail a corresponding reduction in
the possibilities open to the hypotheSis sets on
the other side, since the numbers of partial
matches will, in general, be decreased. Thus,
the sooner a correct choice is made on the
Definition Side, the sooner will correct choices
be possible on the Text side, leading to more
correct choices on the Definition side, etc.
One final factor must be taken into account
in the scoring process. It is natural, and
probably correct, to assume that some kinds of
actions are inherently preferable to others.
Specifically, choosing a unique possibility, or
filling in common characters, would be preferred
to guessing a definiendum, no matter how JDBJlY
high-frequency characters it contained. Since
the correct definiendum is not necessarily
included in the original definienda list and
since, on the other side of the fence, the Text
dictionary is not complete, the first category of
actions can certainly not be considered as sure
things. This same uncertainty, of course, attaches
to the hypothesis set from which any guessed entry
is selected. It still seems reasonable, therefore, to give higher score to the relatively more
warranted actions.

45
1.4

The scoring process for a given action and
a given hypothesis set can now be summarized.
The puzzle is scanned t'o see what new redundancy
factors would be engendered by the action, and
each such factor is properly weighted. The sum
of all these weighted redundancy factors is then
suitably modified by the number of gold stars
already accumulated by the given hypothesis set,
the length of the set's possibility list, and a
warranty factor, which is a function of the type
of action being scored. In the case of the
action to seek common characters one slight additional modification is necessary. If an action
to guess a word of n unfilled characters is
made, then all n of-these characters will be
filled in by the action. On the other hand, an
action to seek common characters in a word with
n unfilled characters will lead to at most n-l
characters being filled in, and may result in no
characters at all being added. It is therefore
necessary to multiply the raw score for a common
character action by the expected proportion of
characters that will result. This proportion
can be determined empirically if intuition fails.
If I were to apply the philosophy underlying
Decision Sequencer 7 to some other problem area,
I would proceed about as follows. I would first
determine the hypothesis sets relevant to the
problem, together with the available means for
changing these hypothesis sets during the solution process. I would next decide on the actions
that could be ~aken in selecting one hypothesis
from a given set, and on the criteria for determining the a priori impossibility of a given
action at a given stage of the solution process.
Third, I would determine what redundancy factors
relating the hypotheses I would or could use,
and what relative importance I should attach
to each such factor. Finally, I would have to
decide on the stop rules, i.e., I would have
to specify when the solution process was to be
considered either successfully completed or
impossible to complete. I cannot, at tHis date,
report on whether this prescription has cured,
or killed, any patients, I hope to report the
former at some later date.
As a sort of appendix, I should like to
present a few selected moments from t~ree actual
solution processes. The first could not be
completed by the program. The second and
third could, which is the reason why I conclude
the paper with them. The next slide (Figure 5)
shows the puzzle status at a point when any
red-blooded American could finish it with his
left hand tied behind his back. Prior to this
point, the program had made four different bad
guesses which it was subsequently able to catch
and erase due to the exorbitant number of poor
three-letter combinations that had ensued. At
the point which now concerns us, the program
suffered from the paucity of lexical information
with which I provided it. The program was aware
of only one six-letter word which matched with

T R
H and was just unaware that the sixth
letter coUld have been, let alone should have
been, the letter S. It therefore completed
this word with its unique possibility,
T R P H Y. The program was unable to rectify
this particular error so that, after some thrashing about in which some earlier correct choices
were despairingly erased, the program ground
to a halt with the solution carried to the point
shown on the next slide (Figure 6). The Text
does have a certain piquancy, but it is undeniably incorrect. Two points are to be noted in
connection with this failure. This first is
that it could have been avoided had I taken
slightly greater pains in providing the program
with its basic lexical and grammatical lore.
The second point is that the solution process,
before being stalled, had proceeded extremely
rapidly. The definienda lists provided for
this solution process contained over 145,000
combinations. The correct status shown on the
previous slide had been arrived at after
seventeen positive decisions had been made,
including the four erroneous ones which had been
corrected prior to the point in question. I am
therefore not too discouraged by this particular
failure.

still, I find success particularly encouraging. The next slide (Figure 7) shows the
status of the target Double-Crostic just before
erasure of the fourth, and final, error made by
the program. As in the previous case, the
dictionary was inadequate, allowing the incorrect
unique partial match CON SUM E R to be filled
in, rather than the correct word
CON SID E R which was not included in the
dictionary. Fortunately, CON SUM E R gave
enough poor three-letter combinations on the
Definition side of the puzzle to warrant its
erasure. Since the erasure of any character
automatically leads to the erasure of all
characters to whose filling in the erroneous
character made some contribution, the erasure
of CON SUM E R led to the Significantly
stripped-down status shown in the next slide
(Figure 8). It was clear sailing from this
point on, however, so that fifteen decisions
later the final, and correct, puzzle status was
reached, as shown on the next slide (Figure 9).
Although the program remains oblivious to the
extra redundancy involved, the first letters of
the correct definienda here do spell out the
name of the author of the Text fragment and the
title of the source, to wit, the Memoirs of
Harry Truman (Volume I, page 189 to be exact).
If I may be forgiven for repeating myself, this
puzzle was solved by means of 29 correct decisions
and 4 incorrect ones which were subsequently
rectified.
In this particular solution process, the
verification section was particularly stern, in
that a definiendum would be erased if it
engendered only two poor three-letter cambina-

46
1.4

tions or just one inadmissible short text word.
Out of curiosity to see what, would happen if I
went to the other extreme, I disabled this
portion of the verification section completely,
thus allowing all triples and short words to be
considered admissible. This left the program,
as its sole error-detecting capability, its
facility for rejecting final configurations which
were not minimal.ly consistent. The next slide
(Figure 10) shows the final configurations which
were presented for inspection When the previous
Double-Crostic was used as a target. The fifth
time around the correct configuration was
presented and was accepted. As in the previous
case, four incorrect decisions had been made
here, but only 20 correct decisions had to be
made. I would not like to generalize on the
relative merits of the two forms of errordetection on the basis of such a minuscule
sample. I think it fair though to conclude, on
the basis of all the testing I have performed,
that the combination of redundancy factor
checking ~d cons:is tency inspection, taken in
conjunction with scoring by weighted sums of
redundancy factors, as modified by list length,
gold star count, warranty factor and expectancy factor, will provide effective deCision
sequencers in more urgent, if less entertaining,
problem areas than Double-Crostics. Time will
tell.

BorE: PermisSion to refer to Double-Crostics
granted by saturday~; permission to quote
from the Memoirs of Harry Truman granted by
Time, Incorporate~ - - - - -

47
1.4

FIGURE 1 -- Double-Crostic 1 (Original Status)

Definitions
In style

Common ailment

Concerning
Personal

Weakling

Asian spot

Text

IS "3 "7 14 -S
20

28 13

Happy time

5 16

48.
1.4

FIGURE 2 -- Double-Crostic 1 (Final status)
Definitions
A.

In style

D I
21 b

Common ailment

G 0 U T
22 ""4 10 15

Concerning

Personal

Weakling
Asian spot

D
29

20 2
G.

Happy time

E
23 27

IS 3
F.

"1 25

A
~

7 14 -g
2B 13

0 U T H
19 12 "5 IT>

Text

S
1A

H
2F

0 0 T
3E 4B 5G

T
H
S
I
15B IbG 17D l8E
D
E
A
H
2bA 27C 28F 29D

OK 7E

BE 9A

0
D
L
19G 20F 2lA.

U
S
T
1lA 12G 1314' 14E

lOB

22B

23C

24F

25G

1.4

FIGURE 3 -- Possible Positive Actions as a Function
of Word Parameters
Status of Word

Blank

Number of Entries

Text

Partially Filled
Def.

Text

Def.

Completely Filled
Text

Der.

on Possibility
List
Zero

One

Fill
Unique
Entry

More Than One

Seek
Common
Characters;
Guess

Fill
Unique
Entry

Seek
Common
Characters;

Guess (h-f
Word or
h-f characters).

Guess

~CJ1
~o

FIGURE 4 -- Decision Sequencer '7, Simplified Flow Chart

From Initial Pass

Score possible
actions; sort
by score.

,...

Fetch highest
scoring action.

Erase
~~

no more

Are erasures
called for?

"
Can It do

Try to implement
action.

Erase

'roo many
errors

\If

Verify puzzle
status.

Is puzzle
completely
filled?

Yes

Yes
No

HALT ....

51
1.4

FIGURE 5 -- Double Crostic 2, Intermediate status

Definitions
A.

COWBELL

HALVES

FODDER

T HI RD

TEETHE

HELMET

TRUANT

I.
S

- -

Text
WE

HOLD

EVIDENT
U A L.

H E S

THAT

TR
L

MEN

T 0

ARE

B E

C R

SELF
TED

52
1.4

FIGURE 6 -- Double Crostic 2, Final Status
Definitions
A.

COWBELL

HALVES

FODDER

THI R D

TEETHE

HELMET

'H.

TRUANT

0 0 N

EAYE

Text
WE

HOLD

EVIDENT
USUAL

THESE
THAT

TROPHY
OLD

MEN

T 0

ARE

B E

C R

SELF
TED

53
1.4

FIGURE 7 -- Double Crostic 3, First intermediate Status

Definitions
A.

HEGEMONY

ABACUS

RETCH

M D

R A BID

ETHICS

- --

TON I C

H.
I.

ANATHEMA

o. - - -

SIN

INITIATE

UTMOST

REVISIT

MNEMONIC

Text
I

CONSUMER

THE

o MIT

S E

IVITIE

METHODS
ON

AMERICA

N
E
I N

U S

THE

MERICAN
M

ITS

UNAM
DAY.

RICA

54
1.4

FIGURE 8 -- Double Crostic 3, Second Intermediate
Status
Definitions

HEGEMONY

ANATHEMA

ABACUS

- - --

RET C H

- - - -- - - --

------

SIN

I N

REVISIT

H.
I.

-- S
0
- --

- - -

MNEMONIC

-- E

Text
NS

THE

-- MER

-- R

THE

-- E

CAN

UNAM

RIC

I N

- ---

-- NG

HOD S

A Y.

55
1.4

FIGURE 9 -- Double Crostic 3, Final Status

Definitions
A.

HEGEMONY

ANATHEMA

ABACUS

NEED

RETCH

MIDDIES

RABID

ETHICS

YOUTH

MOUTH

TONIC

OCEAN

RESIN

INITIATE

UTMOST

REVISIT

MNEMONIC

SITE

Text
I

CONSIDER

UNAMERICAN
AMERICA

THE

METHODS

ACTIVITIES
IN

ITS

USED
BE

BY
THE

THE
MOST

DAY.

(Memoirs of Harry S. Truman, Volume I, ,page 189.)

HOUSE

COMMITTEE

UNAMERICAN

THING

ON
IN

56
1.4

FIGURE 10 -- Double Crostic

Four Final Configurations Successively Rejected

by the Consistency - Checking Section

I CONSIDIS TDE METHIDS USED EY THE HOISE CONMRTl'EE
ON UNAMORISAN ACTIVITIES CO RE TEE MOST EOAMERICAN
THINM IN TVERICA IN ITR NEN.

I CONSIDES THE MErr'HODS USED EY THE HOISE COMMR'Iil'EE
ON UNAMERISAN ACTIVITIES CO RE TEE MOST ENAMERICAN
THING IN TVERICA IN ITR NEY.

I CONSIDES THE METHODS USED EY THE HOISE COMMRIiI'EE
ON UNAMERICAN ACTIVITIES CO BE TEE MOST UNAMERICAN
THING IN TVERICA IN ITS NAY.

I CONSIDES THE METHODS USED EY THE HOUSE COMMRTTEE
ON UNAMERICAN ACTIVITIES TO BE THE MOST UNAMERICAN
THING IN TMERICA IN ITS NAY.

57
2.1
A COMPUTER FOR WEATHER DATA ACQUISITION
Paul Meissner, National Bureau of Standards, Washington, D. C.
James A. Cunningham, National Bureau of Standards, Washington, D. C.
Claude A. Kettering, U. S. Weather Bureau, Washington, D. C.
Summary
A need for improved reporting of weather
data has been brought about by the requirements
of modern, high-performance aircraft, together
with the advent of high-speed computers for use
in weather forecasting. Manual methods of
recording meteorological observations introduce
an undesirable time delay, increase the chance
of error, and limit the frequency of observations. A solution to this problem lies in the
use of automatic data processing equipment for
the recording, pre-processing, and transmission
of the information. Under the sponsorship of
the U. S. Weather Bureau, the National Bureau of
Standards has developed a specialized computer for
use as a research tool in exploring this concept.
Introduction
The National Bureau of Standards in cooperation with the U. S. Weather Bureau has developed
a specialized digital computer for use by the
Weather Bureau as a prototype in the development
of automatic weather stations. This computer
receives data from weather-sensing instruments
and processes these data through such functions
as sampling, comparing, selecting a maximum, and
arithmetic operations. The results operate local
and remote displays, and are transmitted via
teletypewriter to a central forecasting station
and to other airport weather stations. Values
of two quantities recently developed as aids to
air safety--runway visual range and approach
light contact height--are given by the machine
through automatic table look-up.
Increased use of weather reports by the
general public and the aviation industry, and
others, has placed a demand on the Government
to provide more frequent and more accurate
weather data from active airports and remote
locations. It has been obvious that this demand
could best be met by the development of automatic
meteorological equipment rather than by increasing
the number of observers. One can readily appreciate the advantages of having automatic weather
stations capable of operating unattended for long
periods. Such stations could be established in
regions not normally habitable, but which might
nevertheless be important from a meteorological
standpoint. Even at _naed s,taticas, the use of
automatic equipment offers many advantages.
Station personnel are freed from routine-observations, yet readings can be taken more frequently, with less chance for error, and
transmitted with less delay. A single eight-hour
shift might suffice for the personnel, at locations
now requiring continuous attendance. The United
States Weather Bureau has, therefore, supported
the development of automatic weather stations
since the end of World War II.

The first of these stations to be developed
and operated in service was used in the British
West Indies and transmitted a limited amount of
meteorological information to Miami, Florida, by
radio, during the hurricane season. As telemetering techniques were developed, it was
possible to increase the amount of data transmitted. Further development has provided
stations now in use, which transmit weather
observations on demand into the National Weather
Network.
These stations demonstrated the practicabi11ty of automation in collecting meteorological
data, but provided no computing capability and
insufficient versatility to meet changing
requirements of the meteorologist. In order to
provide a complete report automatically, certain
computing and decision-making capabilities are
required. These requirements, and those from
other Government Agencies, have led to a joint
project between the United States Weather Bureau
and the Data ProceSSing Systems Division of the
National Bureau of Standards, in which meteorologists and engineers have worked together to
develop an Automatic Meteorological Observing
System with both operational and research
capabilities. The present equipment, designated
AMOS IV, is built around a small, specially
designed general-purpose computer, to which have
been added the required input-output facilities.
Requirements of the Automatic Station
Consider the tasks which must be performed
by an automatic weather station. The station is
equipped with a number of weather-sensing instruments which furnish weather data, in a variety of
forms. Data from the instruments must be suitably
processed to obtain the desired information, and
this must be made available in the correct form
for display and transmission. It is necessary to
assemble the information, together with any
additional material, such as the station code
and remarks, in the correct format for several
different output messages. These messages, are
to be available for the teletypewriter transmission upon receipt of command signals.
In a few cases, instrument readings could be
sampled directly, converted to teletypewriter code,
and transmitted. However, in many cases, the
desired quantities are not suitably represented
by the instantaneous instrument readings. Hence,
varying amounts of processing are required. In
previous AMOS prototypes, the required intermediate
proceSSing has been achieved through the use of a
variety of separate devices. In some cases,
requirements have developed to the point where
computer-type equipment is required, although
individually the various instruments do not fully
utilize the circuit capabilities.

58
2.1
It became apparent that the overall hardware
could be reduced through the use of a central data
processor which could be t~e-shared by the various
instruments. The use of an internally-programmed
machine for this purpose greatly increases the
versatility of the automatic station, permitting
more sophisticated processing of data from all
instruments. The meteorologist is afforded the
opportunity to arrive at optimum data-processing
routines, comparing different procedures simultaneously, if desired. Changing requirements may
be met simply by preparing new programs; thus,
there is an inherent guard against obsolescence.
For illustrative purposes, a number of quantities of interest and the associated instruments
will be described, together with the form of output obtained and the processing required.
Transmissivity
Transmissivity of the atmosphere is measured
by a transmissometer. A horizontal beam of light
of known intensity is directed at a detector
several hundred feet away. The amount of light
received controls the pulse rate of an oscillator.
The pulse rate varies from nearly zero, for heavy
obscuration, to about 4000 pulses per minute with
a very clear atmosphere. A small background count
may be obtained with no light at all; by periodically turning off the source this background count
may be obtained and subtracted as a correction
factor. The transmissivity data is used in two
forms. For some uses it is expressed as a percentage of the maximum obtainable value. Thus, a
pulse rate of 3000 ppm would indicate a transmissivity of 3/4, or 75%. On the other hand, the
corresponding visibility in miles is not a linear
function and is different in the daytime than at
night. A pulse rate of 3000, for example, represents a visibility of 1.5 miles in the daytime
and 2.4 miles at night.
Wind Speed
Wind speed data is received from an
anemometer in the form of a pulse rate. The
anemometer produces 5 pulses per second for
each knot of wind speed. There are three quantities which we wish to derive from the pulse
rate; these are:
(1)
(2)
(3)

the peak one-second gust occurring
over the past ten minutes,
the one-minute average wind speed,
the ten-minute average wind speed,

Temperature
Temperature is measured by a bridge circuit
which is kept in balance by means of a servooperated slide wire. The servomechanism also
operates contacts, to furnish a read-out of three
decimal digits and sign. Each digit is represented by a contact closure on one of ten wires.
Temperature data is transmitted as read, and in
addition is used as a correction factor for certain
other data.
Pressure
Pressure is sensed by a mercurial barometer
which has a small magnetic float riding on the
top of the mercury column. A servomechanism
maintains the position of a sensing coil with
respect to the float, and operates contacts
s~ilar to those of the thermometer.
A readout of four decimal digits is obtained. Several
quantities are of interest in addition to the
current pressure. For aviation use an alt~eter
setting must be obtained. This can be obtained
electrically, by means of additional contacts,
but can also be handled by the computer via table
look-up or calculation. The pressure must be
converted to an equivalent sea-level value, and
this requires a temperature correction using two
temperature values spaced 12 hours apart.
Pressure tendency is another calculation and
consists of examining three values taken at hourly
intervals. From these a coded value for the trend
is obtained.
Cloud Height
Cloud height data is obtained from a ceilometer. A beam of light from a rotating searchlight is projected on the clouds and the amount
reflected is measured by a photocell. Cloud
height is obtained by triangulation, using the
distance between the searchlight and the detector,
together with the angle of the searchl ight when a
cloud signal is received. In order to obtain
cloud height automatically, it is necessary to use
two circuits, one which watches for peaks in the
photocell signal, while the other keeps track of
the searchlight angle. Whenever a cloud signal is
indicated by the photocell, the corresponding
angle is stored in a buffer register. Height can
be obtained from the angle by table look-up or
calculation. It is desirable to store a number
of cloud observations and scan the stored data to
answer such questions as the following:
(1)

These quantities are to be updated each
minute.
(2)

(3)

At what height was the predominant
cloud activity observed over the
past ten minutes? (This interval
should be programmable.)
What were the lowest and highest
levels at which a significant number
of cloud occurrences were observed?
(The number should be programmable.)
How many cloud observations occurred
below a specified critical height?
(This height should be programmable.)

59
2.1
Additional Instruments
Other instruments which may be included are
the following:
(1)
(2)
(3)
(4)

Sky cover detector, for the fraction
of sky obscured by clouds;
Photoswitch, for indicating background light level;
Weather vane, for wind direction;
Weather element detectors, for snow,
rain, hail, etc.

In addition, some quantities are set in as
manually operated switches, such as obscuration
type, whether snow or homogeneous fog; and, in
the case of airports, runway and approach light
settings.

l~is is a transcendental equation, and a
very fast computing speed is required because of
the iterative nature of the solution. The ALCH
value should be updated once· per minute. The
use of table look-up requires about 18 tables,
each having about 90 three-digit numbers. The
tables are determined more or less empirically,
and vary from one location to another. It was
concluded in the present case that table look-up
would be preferable, using magnetic drum storage
for these and other look-up tables. The RVR
determination is similar to that for ALCH, but
not quite so complex, in that only ground
conditions need be considered, and only a single
number need be prepared, rather than the two
probability levels required for ALCH. The RVR
determination uses the following inputs:

(1)
ALCH and RVR
Two quantities which have not been covered in
the discussion of individual instruments are
Approach Light Contact Height (ALCH) and Runway
Visual Range (RVR). These quantities are of
importance in landing aircraft under conditions
of reduced visibility, either because of ceiling
conditions, or ground obscuration. ALCH is the
height at which the approach lights will be
visible to the pilot. Actually, a high and low
value are displayed for ALCH, since there is a
statistical uncertainty to this kind of data.
The higher value is the height at which there is
a 20% probability of seeing the lights; the lower
value corresponds to a 90% probability. Since
the lights may be obscured either by clouds or by
the presence of fog or snow, a variety of inputs
, are required for the ALCH determination. The
inputs are;
(1)
(2)
(3)
(4)
(5)

cloud height data from the c'eilometer,
transmissivity, as indicated by the
transmissometer,
snow or homogeneous fog, as indicated
by an observer,
background illumination (day or night
conditions) from the photoswitch,
approach light intensity from the
approach light switch setting.

If either the transmissometer or the ceilometer indicate that limiting conditions may be
present, a determination of ALCH is made. If both
conditions are present, the results are compared
and the lowest value is displayed. The actual
determination can be mad~ either by table look-up
or by calculation. The equation, however, is based
on Allard's Law, which takes into account the
complex manner in which the human eye responds to
different light levels.

(2)

(3)

transmissivity,
background illumination (day or
night conditions),
runway light setting.

The expression for RVR, in terms of Allard's
Law is given below, for purposes of illustration:
V

C = 2! Log TR - Log Va
C is a constant based upon prevailing
conditions,
V is the desired RVR va1~e, and ranges
R
from 1000 feet to .6500 feet or greater,
~ is the transmissometer reading,
R is the transmissometer baseline
(generally 500 feet).
It can be seen that the above equation
cannot be solved explicitly for VR; hence, a
lengthy calculating procedure would be required.
For this reason, table look-up was chosen. About
9 tables are required for the RVR determination.
From a consideration of the various input
devices, it is possible to compile a list of
capabilities which are desirable in the input
portion of the automatic station. These would
include the following:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)

sampling,
counting,
averaging,
timing,
comparing,
analog-digital conversion,
peak-value detection,
contact senSing,
code conversion.

60
2.1
Many of these operations could be done either
by the input circuitry or by the data processor.
The choice is determined by the relative convenience, and the time available. It is desirable,
wherever possible, to receive data from the
instruments in the simplest possible form. This
simplifies the instrument and leaves the data
processing to be performed within the computer,
capitalizing on the advantages of digital operation.
It has been demonstrated repeatedly that the central
data processor portion of a computer complex is
much more reliable than the associated peripheral
equipment. Furthermore, the computer can be monitored, and repairs facilitated, through the use of
test and diagnostic routines, whereas the instruments are often difficult to check and to repair.
Description of the AMOS IV System
It can be seen that the machine needed for
the automatic weather station is highly specialized, with a number of unusual characteristics.
The salient features are listed below:
(1)
(2)
(3)

(4)

(5)

(6)

(7)
(8)

The machi~e must accommodate a number
of input devices, all furnishing data
continuously.
Extensive stored tables are needed for
empirically determined data which
varies from station to station.
A short word length is sufficient,
sinee the data comes primarily from
physical instruments; three digits and
sign appear sufficient, relying on
double-precision methods for those few
cases where needed.
A comparatively slow circuit speed is
acceptable, working in conjunction with
the magnetic drum, which rotates at a
moderate speed for long life ,and
reduced cost.
The machine needs only a limited
arithmetic capability, in view of the
extensive stored tables; it can perform
addition and subtraction, with other
operations available through programming.
The machine must transmit teletypewriter
messages at high and low speeds, independently of each other and of the data
processor.
Provision must be included for operating
local and remote displays.
The machine must concurrently process
input data, transmit teletypewriter
messages, and perform data processing.

For purposes of discussion the machine may be
analyzed in two sections: The 'input-output portion,
and the central processor. The input-output circuitry is concerned with collecting the instrument
outputs, pre-processing them where necessary, and
making the data available to the processor. This
portion also rec~ives data which the processor has
assembled in special output tracks and prepares the
appropriate teletypewriter messages. The input-

output circuitry is wired for specific tasks
although considerable latitude has been left
for modifications and additions. The central
processor is internally programmed and is controlled by an automatic typewriter which also
can be used as a form of display. A block
diagram of the AMOS IV system appears in Fig. 1.
Input from Instruments
The method of receiving input data from the
weather-sensing instruments is a compromise
between the use of separate pre-processing devices
and use of the central processor. In order to
avoid excessive interruption of the central
processor, varying amounts of circuitry have been
assembled, depending on the form of the input
data, to pre-digest the instrument signals for
most efficient use by the processor. Once the
data has been prepared in suitable form, generally
as contact closures or storage in flip-flop
registers, it is entered into the computer via an
input-data track on the magnetic drum. This track
is equipped with two heads~ one addressable by the
central processor and the other wired to the input
circuitry. Since the track can store 100 words,
there is an input capacity of 100 instrument readings, a quantity considerably in excess of present
requirements. The address of each word identifies
the reading, and the addresses therefore, are used
to callout the appropriate subroutines when new
data appears in the various word locations. The
input devices are sampled sequentially by means of
commutating pulses obtained from a decoding network attached to an address counter. It is
possible with this scheme to sample any instrument within 1/30 second of the time that a desired
reading is obtained. If readings were obtained
at the rate of 30 per second, however, the central
processor would quickly be overloaded; actually,
it is sufficient to sample most instruments a~
intervals of once per minute or longer. The ceilometer is the most frequent with readings at 6
second intervals.
'
In addition to an address counter and decoding network for obtaining commutating pulses,
the input circuit has a one-word shift register
which serves as a buffer be~een the inst~uments
and the input recording circuit. Data words from
sampled instruments are inserted in the register
by means of a parallel transfer, up to 13 bits at
a time (three decimal digits and sign). The
number representation need not be binary-coded
decimal, since the computer can perform code
conversion, if required.
Among the quantities requiring more
extensive pre-processing, the transmissometer is
illustrative. Here, a pulse rate of 0 to 4000
ppm is to be counted and expressed as a 3 digit
number. New values should be available once per
minute, so a one-minute time base 1s used. The
incoming pulses are shaped and passed through a
two-stage binary counter which reduces the rate

61
2.1
by a factor of four. Thus, the maximum (clear
atmosphere) pulse rate will yield a one-minute
count of 999, which can be expressed with one
data lvord. (A gating circuit inhibits counts
beyond 999 to prevent overflow, should a higher
counting rate inadvertently occur).
The end of a one-minute sampling interval
is indicated by a pulse from a timer which counts
drum revolutions, since the drum is driven by a
synchronous motor. Thus, the drum is always in
a known position, and there is a minimum of delay
in sampling the desired reading and transferring
it to the drum. The counter is inhibited during
the sampling and resetting interval. (One-third
millisecond is required for sampling, 20 microseconds for settling time after reset. No
significant information would be lost during
this short time).
Utilization of Input Data
Utilization of input data by the central
processor is handled by a "watchdog" routine.
Whenever a subroutine is completed, 'the processor
proceeds to scan the input channel, starting at
the beginning. Wilen an instrument~eading is
noted it is read into a register and the address
is noted. The address is keyed to a subroutine
which directs the handling of the new reading.
It may simply be placed in memory for future use,
or inserted into an output message channel. More
generally, however, there are several operations
including perhaps a few calculations. A key step
in the subroutine is the insertion of a nonsense
word which could never be a valid instrument
reading, and will be disregarded during the next
"watchdog" scan. This will permit the "watchdog"
routine to pick up the next succeeding instrument
reading in the input channel.
Teletypewriter Output
The teletypewriter out~uts involve the
buffering of data, which comes from the drum at
a high rate, dOlVU to the desired message speed.
In addition, data words must be reorganized into
teletypel~iter characters, ·including the addition
of start and stop pulses, and the generation of
space 'and sign characters. Two independent teletypewriter outputs are required, 'with different
codes and message formats. The low-speed output
is nominally 100 words per minute, while the highspeed output is in the range of 750 to 1500 'tvords
per minute. Several different message lengths are
required at the higher speed, requiring that the
circuitry be capable of skipping unwanted portions
of the message. Since the messages are to be
combinations of data prepared by the computer and
alphanumeric remarks and text inserted by hand,
several tracks have been allowed on the drum

for this information. Certain tracks,
addressable by the computer, contain the
numerical data. Other tracks may be written
into only from the automatic typewriter, and
are used for the remarks. These are all dualhead tracks, with one set of heads being used
to insert data, either from the processor or
the typewriter, while the other set is used to
read out the information.
The low speed circuitry is fairly straightforuard, since there are several drum revolutions
in the time required to transmit the contents of
one machine word. Thus, it is only necessary to
provide a one-word buffer register, which in turn
transfers its contents through an encoding matrix
to an output shift register. As soon as the
buffer register is empty, an address circuit
proceeds to watch for the next consecutive word
from the drum, which is then read into the buffer.
Each machine word, consisting of three decimal
digits and Sign, is transmitted as five characters:
sign, three digits, and space. Remarks are stored
as five-bit teletypewriter characters, two per
machine word.
The high-speed circuitry is complicated by
the fact that the contents of several machine
words are transmitted during a single drum
revolution. This was handled by spacing the
data around the drum so that the next word would
be available just as the last one was transmitted.
To assure synchronism between the teletypewriter
and the drum, a clock track on the drum is used
to furnish the teletypewriter pulses.
It can be seen that the various dual-head
tracks are the means by which simultaneous input,
output and data processing functions are performed. In order that these various heads may
handle data in a manner c9mpatible with the
central processor, it is necessary that each
pair of heads be equally spaced. A second set of
sync pulses, delayed by an amount equal to the
spacing bet~een heads, has been provided.
Data Processor Section
The data processor portion of the AMOS IV
system is constructed as a separate enti~y which
can be replaced at a later date, should a more
powerful computer be required. The processor is
built around a magnetic storage drum having 100
general storage channels and a number of dual head
registers. The general storage channels contain
stored instructions, subroutines, diagnos~ic
routines, and look-up tables. The dual-head
registers are used for the handling of input data
from instruments and for output information to the
displays and to the teletypewriter lines.

62
2.1
The processor uses a binary-coded decimal
number representation with a word length of three
decimal digits and sign. A parity bit is added
for a memory check, giving a word length of 14
bits. There are 100 words per channel, making
a total of 10,000 words, and this number can be
expanded to 20,000 through the use of additional
heads. The drum operates at a conservative rate
of 1800 RPM; non-return-to-zero recording is used,
with a recording density of 120 bits per inch.
Thus, the machine operates at a bit rate of 50 kc.
The computer is an internally programmed,
single-address machine with about 21 operations.
The operations are listed in Table I. The
operations have been grouped together and coded
according to function for convenience in programming. The operations are generally quite
similar to other small machines. The memory scan
operations (60, 64, 69) are specifically desiged
to optimize table look-up. Thus, table look-up
may be performed with fewer instructions and with
only one drum revolution. The index register
should be called an alternative addressing
method. When an address is placed in the index
register by one of the memory scan operations, it
will be transferred to the instruction register
only when a non-decimal combination of bits
appears in the word-select portion of the instruction register.
An instruction utilizes two consecutive
words from memory, providing six decimal digits
and two signs. This is shown in Fig. 2. Two
digits are required for channel identification
and two for the word location within a channel.
In order to allow for ease in the programming of
address modification, the word address uses
the first two digits of the first w'ord, while the
channel location uses the second t,~ digits of
the second word. The operation code is divided
between the two words, using the remaining two
digits and the included sign.

An automatic typewriter with punched paper
tape is used as the primary input-output means
for the processor. In addition to its use with
the processor, the typewriter may be used offline, for the preparation and verification of
punched paper tapes.

Construct;lon
The machine is constructed from a series of
transistorized building blocks previously
developed at the National Bureau of Standards.
Three factors were emphasized as the main
considerations in designing these packages:
reliability, cost, and versatility.
Reliability
(1)

The circuits are designed to permit
wide variations from the nominal
values of the characteristics and
parameters of the components.

(2)

The electrical outputs
of the packages can be
circuited to ground or
voltage supply without
of the components.

(3)

Pin-type connectors with high-pressure
contacts are used rather than printedcircuit edge-type connectors.

(4)

Signal swings are at least 6 volts,
with a collector supply of -12 volts.

(5)

All connectors have gold-plated pins.

(6)

All back panel wiring is by taper pins
for ease and convenience in making
external connections. Taper pins also
eliminate solder joints.

from most
shortto the negative
damage to any

Economy
The processor has three basic modes of
operation. The normal mode allows the machine
to automatically sequence through the instructions
until a halt code is encountered in the instruction register. The machine halts on any take-in
or print-out operation for which the sign of the
instruction is negative. A breakpoint mode is
used for program debugging or machine maintenance.
In this mode, the machine will halt for any
instruction having a negative sign. A singlestep mode of operation is included, and is used
primarily for machine diagnosis or program
debugging. In single-step operation the machine
performs a single operation and halts. A complete
operation consists of executing an instruction
and bringing the next instruction from memory.
All the registers and major portions of the machine
are displayed on an indicating panel.

(1)

"Entertainment"-type germanium
transistors are used throughout the
circuitry.

(2)

The wide tolerances permit using
unselected "off-the-shelf" components.
However, transistors and diodes are'
tested for open or short circuits before
assembly into the packages.

(3)

All connections, including those to the
connector, are made by dip-soldering the
board.

63
2.1
Versatility
(1)

Two triggering gates are included ,~ith
each flip-flop circuit to permit
connecting the package as either a
counter or a register ~lithout having
to use additional gates from some
other package.

(2)

The bases of the transistors on flipflop circuits are accessible at the
connector so that an unlimited number
of additional input gates can be
connected.

These packages have been in use over a
period of several years in a number of units of
laboratory equipment. The high reliability
which they have demonstrated has been very
gratifying.
Approximately 500 of these packages,
with an average of three transistors each, are
contained in the central processor portion,
with about 400 additional packages in the
input-output portion. The packages are contained in drawers which in turn are mounted on
slides, permitting practically all maintenance
to be accomplished from the front.
Conclusion
It should be emphasized that the Al10S IV
System is intended as a research tool for
exploring the use of automatic data processing
in the handling of weather data. Emphasis has
been placed on versatility, in view of constantly
changing meteorological requirements. It is
felt that the experience gained from the use of
a limited number of AMOS IV systems should permit
the formulation of much more realistic designs
and specifications for future automatic weather
stations based on the use of automatic data
processors.

64
2.1
T.ABL~

b}10S IV Data Processor Instructions

Code

Operation
Take in ten words from type\«iter starting with memory location a
Take in two words from typevlt'iter starting "lith memory location a

Take in full channel of words from typewriter into memory channel

Print or punch out ten words from memory starting \yith a

Print or punch

Print or punch out full channel of ''lords from memory channel

Read one word from memory location a

and place into A register.

Read one word from memory location a

and place into 13 register.

Take word from A register and place into memory location a

Take word from 13 register and place into memory location a

Add contents of A register to contents of memory location a ~ and place
answer into 13 register.
Subtract the contents of memory location a ~ from A register and place
answer into 13 register.
Shift contents of A register right 4 bits.

42
45

o~t

tvl0 words from memory starting ,.:ith a

If 13 = O~ jump to contents of a ~ for next instruction.
If overflow occurs, jump to contents of a ~ for next instruction.

If 13 < 0, jump to contents of a

Memory scan instructions.

for next instruction.

Contents of A register are compared '-lith vlords

in channel ~.
When (aA~) = (A), place a

64
69

in I register; stop at first occurrence.
A
When (a~) > (A), placeaA in I register; stop at first occurence.
Seek largest word in channel ~j place a portion of address in I register.

Transfer bits described in

Read out three words from memory starting with location a
display registers.

from register 13 to register A.
~

into output

•..........................................................................

•
••

,~~:~V : 1
"

••

'" I f f
f
f f

":,,,,~,
"',, " "

,,~~"";
'"

f
f

I I

I ~

,,:""/"

//" "/""

// /"

"/,~"

dJ ltJ
CEILOMETER

TO-A
TRANSMISSOMETER

ILLUMINATION

NOTE:
APPROACH LIGHTS
SETTING

CONCURRENT PROCESSING, INPUT, TELETYPEWRITER
OUTPUT, AND TYPEWRITER OPERATION.

Figure I. Block Diagram of AMOS IV With Approach Visibility Configuration

1\:)0\

~CJl

66
2.1

DATA WORD
14 BITS

-------------~-~--------~

-------- ----------

PARITY

10 2

10'

10°

SIGN

INSTRUCTION
TWO

CONSECUTIVE

DATA

WORDS

--------------- -----.......
WORD

CHA~NEL

OPERATION

_---'---_.--------...--.....
+

~~------~-~--~-----------------~--~------------DATA WORD
DATA WORD
AT ODD ADDRESS

Figure

Word

Format

the

EVEN

AMOS

ADDRESS

Computer.

67
2.2

A SURVEY OF DIGITAL METHODS FOR RADAR DATA PROCESSING
F. H. Krantz and W. D. Murray
Burroughs Laboratories
Paoli. Penna.

Summary

This paper reviews the growing number of
declassified techniques for automatic processing of radar data by digital means. Emphasis
is placed upon signal time-sampling and quantization. integration methods. rejection of stationary targets. radar trigger manipulation.
and treatment of radar beacon code data. These
techniques are discussed individually and are
also shown combined in a hypothetical radar
data processor design.

Introduction

Radar. a new technology of World War II.
has become an almost common part of our modern life but continues to be the subject of new
applications. new methodology and new techniques. In its first decade. the radar system
consisted of the radar itself. a cathode ray tube
display and a human operator. As the technology matured and radar targets gained new capability. the need for extracting more information from the radar signal at a more rapid rate
grew. Thus. in the past decade. the increased
performance of the radar has been accompanied
by the growth of the associated field of radar
data processing.
The first radar data processors used analog
techniques in an attempt to automatically reproduce those operations performed by the human.
More recently. the pressure for increased automation. coupled with the requirement for automatic communication of radar information over
long distances. has resulted in the introduction
of digital techniques for radar data processing.
It is the purpose of this paper to outline the
principles of digital radar data processing and
to demonstrate examples of application of digital
techniques to this field.
The expert in digital computer technology
will immediately recognize most of the digital
mechanizations and will observe that in radar

data processing these usual digital techniques
are applied. sometimes in completely different
form. to this new problem area. It should be
noted that most of the applications described
herein. while shown for the radar problem. are
equally applicable to other problems in extraction of information from a signal in presence of
noise. Typical are the fields of SONAR. infrared detection. magnetic detection and communications.

The Basic Radar Problem
In general terms. the radar data processing problem is one of information extraction;
that is. it is desired to extract from the radar
signal the maximum amount of real information
and at the same time to exclude extraneous information introduced by noise and other targetlike phenomena. For the purpose of the present
discussion. the Simplified pulse radar system
of figure 1 wilt be the vehicle to which radar
data processing is applied.
The pulse radar consists of a transmitter
which periodically transmits a burst of energy
of prescribed pulse duration at a prescribed
carrier frequency. This burst of energy will
strike targets and some portion will be returned
in the direction of the radar equipment. The
character of the returning signal will have been
modified by the addition of a doppler frequency
component proportional to target velocity.
The amplitude of the returned signal is a
function of effective cross sectional area of the
target. On successive radar returns this amplitude might vary due to changes in cross sectional area.
In addition to target returns there will be
returns due to clutter caused by precipitation.
by objects on the ground. and by such effects
as aurora. Each of these clutter-reproducing
objects will impose its own effective doppler
frequency on the signal and. in general. these
doppler frequencies are lower than those for

68
2.2

the usual real target. The real target is further
obliterated by effects of noise in the radar receiver or by interference generated by some
other electronic equipment, either hostile or
friendly. The noise and many of the interfering
signals have random frequency and amplitude
distributions, a characteristic frequently used
in radar data proceSSing for their elimination.
In the radar receiver the frequency of the
signal is reduced from that of the basic carrier
to some intermediate frequency by comparison
with a reference oscillator. Information on
amplitude of the returning signal (the envelope
of the IF signal) is presented at the output of an
amplitude detector as "normal" video. Range
of the target is represented as the time of occurrence of the pulse. Although much of the
radar data processing is applied to the normal
video signal, the phase information contained
in the IF is also useful in evaluation of target
velocity. We will not be concerned here with
the high frequency characteristics of the returning pulse which are used for more sophisticated forms of discrimination based on target
signature.
From the information received from the
radar equipment, it is necessary to extract
information on real targets. The general objective is to obtain through radar data processing the maximum sensitivity to weak targets
while maintaining a minimum rate of generation
of false targets. The characteristics of a real
target which are different from those of noise
and clutter are used in the processing of the
radar data. Among these are that a real target
will correlate in range pOSition and in radial
velocity from pulse to pulse during the time that
the radar illuminates the target, and that real
targets will, in general, have a greater doppler
velocity than will signals due to clutter.
Analog Detection Based on Signal Amplitude
In the early pulsed radar systems information was processed by presentation on a cathode
ray tube display to a human observer. The typical display will sweep an electron beam from
the center of the display at an angle equal to that
of the radar antenna at a uniform speed and at a
sweep repetition rate coincident with the radar
prf. The beam is intensity modulated so that
the light output on the surface of the display will
be proportional to amplitude of the raw video
signaL

A real target will appear at the same range
position for several successive radar pulses,
and thus, will appear as a short arc on the display. Random noise, which does not correlate
in range, will generally appear as isolated spots
randomly distributed over the surface of the
display. These separate characteristics of targets and noise are used to discriminate between
the two. In the simple radar system, the integration is performed in the memory of the human operator assisted by the relatively long
perSistence of the display phosphor. This
method is quite sufficient for the separation of
strong targets and weak noise, particularly
when the observers attention need only be devoted to one or two targets on the face of the
display.
Electronic techniques are sometimes used
to augment the integration process in a device
known as the video integrator. This device
consists of one or more delay lines, each adjusted to the radar pulse period. The outputs
of delay lines, each modified by a suitable
decay factor, are added and their sum is used
to intensity-modulate the PPI display. A typical video integrator is shown in figure 2. Although the video integrator increases the capability to discriminate between targets and
noise, its characteristics of essentially exponential decay are not completely matched to the
energy distribution across a radar beam width.
Thus, the optimum discrimination between target and noise signals is not obtained.
A typical display from a simple radar system is shown in figure 3. The problems of
extracting information on a large number of
targets to high accuracy in the presence of
noise are readily apparent, and the need for
more advanced processing techniques is demonstrated.
Digital Detection Based on Signal Amplitude
Digital methods for radar data proceSSing
start by quantizing the analog raw video Signal
in amplitude and range. As will be demonstrated
later, it is possible to quantize in amplitude to
as many as a-bits, but for Simplicity in demonstration of digital detection techniques, simple
I-bit encoding will be considered here. The
inputs to the quantizer (figure 4) are the raw
video from the radar receiver and a range timing reference generated by a digital clock. An
output pulse is transmitted whenever the input
signal is of amplitude larger than a fixed or
automatically adjusted threshold (clip level) at

69
2.2

the time of occurrence of a range reference
pulse.
The clip level is established by consideration of sensitivity required and false alarm rate
reduction pos sible through later statistical integration processes. For the typical groundbased~ long-range radar equipment~ the clip
level is established at an amplitude such that at
100/0 of the range timing pulses an output pulse
will be generated. This very low clip level~
permits detection of targets of very small radar
cross section at extremely long ranges. The
automatic adjustment of clip level based on long
time sampling of the quantizer output is used to
compensate for variations in gain of amplifiers
in the radar equipment and in the quantizer.
The range reference clock frequency selection is based on requirements for range accuracy
and range resolution in the radar. In order to
provide maximum sensitivity and maximum resolution consistent with duration of the radar
pulse, a range reference period equal to the
pulse duration is typical. Thus~ range resolution and accuracy of from 1/4 mile to several
miles are found in the usual systems.
Following the quantizing process statistical
detection is performed to eliminate signals due
to noise while retaining those caused by targets.
The simplest digital integrator, the exponential
detector shown in figure 5, operates exactly as
does the video integrator described above. In
each range increment a target history is maintained by adding the new signal (either 1 or 0)
to the sum of the previous signals multiplied by
a constant less than unity. The size of the constant is determined by azimuth reaolution and
target sensitivity objectives. When the sum
contained in a register exceeds a preselected
threshold~ detection criteria have been met and
an output indicates presence of a real target at
that range. This indication is maintained until
the "end target" threshold is greater than the
register sum. The growth of the signal output
of the exponential detector and the decay of
such output after the radar beam has passed
through the target for the case of a radar output
of square characteristics are also shown in figure 5. The non- symmetry of the output signal
and the mismatch with the radar beam make
this type automatic detector less than>optimum
in detection probability, noise rejection and
azimuth determination.
The more advanced sliding window detector
increases detection sensitivity and azimuth determining accuracy. In this detector demonstrated in figure 6, a record of target return is

maintained for each radar pulse through the
radar beam width. The outputs of each pulse
position of the record are summed and compared with a detection threshold and when this
threshold is exceeded, start of target is called.
At a later time when the sum of target histories in the radar beam width is less than the detection threshold, end of target is called. The
symmetry of the output of this device and the
match with the ideal radar beam are shown in
figure 6.
Although the sliding window detector offers
improved performance over the exponential detector. the equipment required in its implementation for a radar with many transmitted pulses
per beam width is Significantly larger.
In order to obtain performance approaching
that of the sliding window detector, with equipment more closely apprOximating the exponential detector, a new statistical detector known
as the moving sum detector has been deve loped.
In this detector ~ (figure 7) a feedback loop is
used to add the latest target amplitude to those
of previous targets as in the exponential detector but the decrement is taken as the average
amplitude over N main bangs. N may be as
long as the integrating period or may be less
in order to achieve maximum azimuth accuracy.
All of these automatic detectors require
the use of memory in order that target history
can be maintained. These memories are usually range-organized. That is, each range
interval is represented by a prescribed me mory word and at completion of proce ssing of a
detect ed target, the position in memory of such
detected target establishes its range. Although
ferrite core memories are also used~ the range
organized memory can be most easily demonstrated as implemented on a drum surface as
shown in figure 8. Here a number of individual
drum channels (or bits in each memory word)
are used for the data proceSSing function. The
drum rotation rate is automatically coupled to
the radar pulse repetition frequency; thus any
radar range is represented by one position (or
one word location) on the drum surface. A recirculating drum system with a positive erase
bar is usually used in this application.
History of target signals is maintained by
reading information from memory heads spaced
by one pulse period from the write heads by
writing back the previous history continuously
as new target signals are introduced. In the
sliding window detector~ for example, information read from detector channel No. 1 is written

70
2.2
back into detector channel No.2, from No. 2
into No.3, etc. Thus, at any instant of time,
information appearing under the read heads is
a target history for that range interval over the
prescribed number of previous radar pulses.

Azimuth Determination
To determine azimuth of detected targets a binary representation of antenna direction must be
maintained. Although this can be done using a
binary code wheel device in the antenna pedestal, it is more usual to have a pulse transducer,
with each pulse representing an increment of
antenna rotation, feed an azimuth counter which
is cleared to zero at the time the antenna passes
through a north reference position. Thus, the
azimuth counter maintains a continuous record
of antenna orientation. The detector operating
curves of figures 5, 6, 7 show that the center
of a target is represented by the average of the
azimuth at start of target and end of target corrected for some offset introduced by the detector.
A typical method for accomplishing azimuth
determination is to add one to a sum maintained
in the azimuth channels of the memory (figure
8) whenever the statistical detector output is
greater than the detection threshold in each
range increment. At "end of target" 1/2 of this
sum is subtracted from the number in the azimuth counter. The azimuth offset correction,
which is fixed for the statistical detector used,
is then applied to obtain an accurate digital representation of target azimuth. It is in this
process that the symmetry of the detector output is important in obtaining azimuth accuracy.
In the computation of target azimuth by the
method described above, information on target
strength or azimuthal extent is automatically
available. This target characteristic, known
also as "run length, " is of importance in separating real targets from targets produced by
clutter.
Target Buffer Memory
In cases where automatic communication of
target information is required, problems may
be imposed by bandwidth limitations of communications equipment. Since the data processor described thus far operates in real radar time, it
is possible for targets to be detected at a rate
much greater than the average rate over a radar

rotation. It is not economically practical to
build a communications system de signed to operate at the maximum rate and a queuing problem
is introduced. If a target buffer memory is included in the radar data processor, it is possible
to design the communications system with an information rate equivalent to the average target
detection rate and still minimize the los s of target information due to communication line saturation. This memory may be provided as a
part of the statistical detector memory wherein
target storage locations are included in each
range interval or through a separate buffer memory where targets are inserted as they are detected and are removed as space is available in
the communication facility. Although the first
method is wasteful of memory space in that a
large number of unneeded memory locations are
provided, it is efficient in a drum memory where
separate drum tracks are relatively inexpensive
when added to the basic drum required for the
detection and azimuth calculation process. In
the case of a ferrite core detector memory,
however, memory cost goes up more rapidly
with an increase in memory location requirements
and it is often more economical to add a small
independent random access buffer memory. For
a typical ground radar environment, where probability of loss of targets due to saturation must
be minimized, the radar data processor will include buffer memory for two targets per range
interval in the case of the first type of buffer or
will include 25 or 50 memory locations in the
case of the independent buffe r memory.
PRF Control

In many applications, devices are required
to selectively adjust the period between radar
triggers in order to achieve certain desirable
performance characteristics. Among the advantages obtained are interference rejection, extension of the basic radar range, and elimination of
loss in sensitivity in proceSSing of the target
doppler frequency shift. Each of these is briefly discussed below.
When a radar operates in the vicinity of
other similar radars, as frequently occurs in
military zones, it may happen that pulses from
a neighboring radar are received in one's own
radar and appear as point targets. When this
situation is particularly aggravated, dense
spirals are formed on the radar presentation
and considerable excess data is created. Periodic or random variation in the radar trigger
of one's own radar, when followed by range realignment and integration of the video, will

2.2

In a constant PRF radar the basic range of
the radar is limited by the distance whieh a
pulse can travel and return in the time between
radar triggers. By coding or otherwise manipulating the interpulse pe riods so as to achieve
various pulse separations. echoes from beyond
the basic range of the radar can be recognized
and detected without range ambiguity.

and cloud banks will give rise to a very large
number of returns which obscure the radar picture for the manual observer and create very
objectional quantities of excess data in automatic
data processing systems. (See figure 3.) A
variety of techniques have been studied which
have as their objective the elimination of these
clutter returns without degradation to the system
sensitivity for moving targets. Many of these
solutions have been only partially successful.

Various techniques for the elimination of
stationary objects while retaining mOving targets are totally dependent upon the doppler shift
in the echo from the moving object to carry out
the required discrimination. In a pulsed system
such as radar. however. targets traveling at a
speed such as to move one r-f wave length between pulses will be indistinguishable from stationary objects. Controlled variation of the
radar intra-pulse period will permit recognition
of moving targets under all conditions without
sacrifice in the ability to reject stationary objects and clutter.

An early technique having as its primary
objective the control of excess data utilized an
operator to manually map out the clutter areas.
One equipment for this purpose (shown in figure
10) consisted of a Plan-Position Indicator (PPI)
display over which was suspended a photomultiplier tube sensitive to the ultra-violet layer of
the PPI phosphor. Mapping is accomplished by
the application of an opaque inking fluid to the
clutter areas to be removed. Although this system was particularly simple to implement using
digital techniques, all true targets within the
map area were eliminated with the clutter.

In practice. the equipment needed for PRF
control and the subsequent manipulation of target data is particularly simple and straightforward when carried out with digital methods.
The Simplest technique for control of the intrapulse period is to make use of a feedback counter. Using this logical configuration to select
various delay lines to be inserted in the trigger
generation circuitry. a number of values of delay are readily obtained. A complete system is
shown in figure 9.

A second fairly straightforward technique
eliminates clutter on the basis of its lower relative
strength. One approach uses as a measure of
strength the instantaneous amplitude of the video
return and, by comparison with a preset reference level. rejects all signals of less than the
reference strength. The reference level is selected on the basis of empirical data to permit
strong point targets to be passed by the comparator circuit.

effectively eliminate this form of interference.

Methods for realignment of the radar echoes
in range for integration and other purposes depend upon the type of mem.ory employed. In
systems utilizing a magnetic core memory, no
special provisions need be made other than synchronizing the flow of data through the memory
to the radar trigger. Where the memory is a
magnetic drum. servoed to the average PRF.
the drum inertia prohibits rapid adjustment of
the drum speed to follow the changes in interpulse period so that complementary delay lines
in the receiver chain are needed to realign the
receiver video. The conversion of video to digital form prior to range realignment achieves a
number of desirable economies in the engineering of the complementary delays.

Clutter Rejection
In many radar installations the presence of
large distributed reflectors such as land masses

A second approach determines target strength
on the basis of number of returns received from
the target as the radar beam sweeps across it.
The returns are counted and on the basis of prior
statistical data, targets exhibiting too few or too
many hits are rejected, leaving only those targets
which have been previously shown to be point targets. This method requires the implementation
of counters in each range element. but this is particularly simple when implemented in conjunction
with the circuitry for azimuth estimation.
A third technique is essentially a refinement
of the one just previously mentioned in that total
number of hits received from a unit area are
counted and used to set the system sensitivity
level. By this means the detection level can be
made just slightly greater than the instantaneous
background so that all clutter is effectively eliminated. Targets in the clear or targets stronger
than the clutter background are accepted by the
system. This technique can be most easily implemented digitally as a part of any of the digital
sweep integrators previously described.

72
2.2

A fourth approach to clutter rejection and
the only one giving detection capability for targets weaker than the clutter utilizes the difference in velocity between clutter and targets to
achieve the required discrimination. This system. frequently called MOving Target Indication
or MTI, makes use of the doppler shift in the
reflected energy created by the moving target
and was until recently implemented by analog
techniques. Digital methods, however, have
been applied to this problem, resulting in elimination of bulky delay lines and achieving high
reliability, freedom from field adjustment, and
greater flexibility, while preserving equivalent
performance. Modifications of the digital technique can be made to measure radial velocity
on each detected target.

Encoders for these purposes can be designed to achieve an encoding capability of eight bits
in three to four microseconds. One encoder implementation which has proven successful depends
upon comparison of the analog video signal with
sixteen reference levels, subtraction of the largest number of integral levels possible from the
signal while maintaining a net positive balance
and a second comparison of the residue with a
second set of sixteen reference levels. This encoder has demonstrated the capability cited above
and is free from short and long term drifts and
environmental limitations.

The digital approach to MTI is shown in
figure 11. This Simplified diagram shows a
system for sensing either the x or y component
of the target vector, means for encoding this
quantity to a number of binary digits, a small
memory to delay this data one inter-pulse period,
and a digital subtractor; the purpose of the system is to compare successive values of the target amplitude or its components. MOving targets
will exhibit a periodic variation in their amplitude components at a frequency given by the
equation for doppler shift. These targets will,
therefore, produce a non-zero difference between successive echo amplitudes and in subsequent circuitry will produce a detectable data
processor output. Stationary targets having no
periodic variation in amplitude will produce a
theoretically zero output from the subtractor
and will, therefore, be eliminated from further
data processing. Systems of this general form
have the ability to detect moving targets whose
return echo strength is over 40 db weaker than
the surrounding clutter.

Air Defense and more recently air traffic
control are both heavily dependent upon means
auxiliary to the radar for the precise identification of targets. Toward this end there has been
very considerable development of cooperative
devices carried in aircraft which, when interrogated by a special transmitter associated with
the primary radar, respond with a distinctive
identifying code. Detection, verification and
interpretation of the received code train is most
successfully carried out through digital techniques.

Video Amplitude Encoding
Several special situations may occur in
radar data processing where high speed encoding of video amplitude to high accuracy is required. The digital MTI system previously described is one such case; other cases arise in
conjunction with stacked-beam radars which
measure range, azimuth and height on each detected target. The height output is conventionally an analog voltage which must be encoded
with great accuracy and high speed for further
data processing. Encoding may also be required
in those cases where only a few hits are available on each target, dictating maximum retention
of all amplitude information in the integration
process.

Beacon Code Detection

The principle digital components of this system, (called beacon or secondary radar), are
timing circuits to generate various special pulse
patterns for interrogation, and code-train processing circuits which a) eliminate spurious
replies; b) achieve correlation of the beacon data
with the radar echo from the same target; and
c) interpret the code train for parity errors and
for special codes used to indicate emergency,
special aircraft, etc. The beacon data processing system is typically composed of high fidelity
delay lines having a multiplicity of taps and conventional computer elements operating at relatively high speeds. (See figure 12.) Equipment
currently under development to meet the exacting
identification requirements of air traffic control
may have as many as one hundred thousand electronic components.
Complete System DeSign
A hypothetical radar and its data processing
system can be constructed to show the application
of digital techniques in a fairly standard application. The radar transmitter chain is shown in
figure 13. In this figure, the basic transmitter
pulse repetition frequency is determined in the

73
2.2

trigger pulse generator on the left. Delays
under the control of the PRF jitter network produce variations in radar inter-pulse period
which are predictable but which will not repeat
for an arbitrarily large number of radar trigger
periods. The jitter pulses are then applied to
a modulator which fires the final stage of the
radar transmitter producing pulses of high frequencyenergy. A beacon transmitter chain produces coded interrogation pulses for transmission by a second antenna mounted upon the primary radar.
The receiving and data processing systems
are shown in figures 14 and 15. At the upper
left the incoming radar information is divided
between two channels - one the so-called normal
channel and the other the MTI channeL In the
normal channel the radio frequency signal is
first converted to an intermediate frequency.
then to video. and then quantized to produce
standardized ONES or ZEROS depending upon
whether the target return is greater or less
than a reference level automatically set in the
digital quantizer. In the MTI channel the RF
information is converted to an intermediate
frequency. then applied to a phase detector
which has an an output either the x or y component of the target vector. This component is
encoded. delayed and applied to a digital subtraction network as previously described for
a digital MTI. The subtractor output is reduced
to a one-bit code and is then in all respects
identical to the output of the Normal quantizer.

beam-splitting logic which finds the center of the
set of returns received from a point target as it is
swept by the radar beam. The center is encoded
by gating an azimuth counter to achieve a digital
word for target azimuth. Range information on
the target is readily obtained from the memory
by gating a range counter on the basis of the pOSition of the target in the range-organized memory.
Information on target range and azimuth
taken from the prime radar and target identity taken
from the beacon response are passed with other
information on special target characteristics to
a buffer memory to await transmission to the
next user. The transmission media may be any
low bandwidth system of which ordfnary telephone
lines are typical. Digital words. one per target.
may be transmitted at rates in the order of 25 to
50 targets per second. Word-forming logic between the buffer store and the output section of
the data processor arranges the range. azimuth.
identity, and other information in prescribed
order, carries out parity checks and generates
the timing waveforms for actuation of the output
function.
Summary

In summary. a variety of digital techniques
have been very briefly described to indicate the
breadth of the application of digital methods to
radar data processing. While many specific
. techniques remain under military classification.
the general principles of digital implementation
Simultaneously with the reception of target
of data proceSSing functions are well understood
information from the prime radar. the response
of the target to beacon interrogation is also reand have in a number of instances given dramatic
proof of their high reliability. ease of maintenance.
ceived. After suitable demodulation from radio
and adaptability to modification and evolution. and
frequency through intermediate frequency to
in many cases provide functions and performance
video. the code train is standardized in ampliwhich have no counterpart in analog circuit techtude and timing. integrated to remove spurious
replies, checked for parity, and caused to pronology. It is anticipated that with an increase in
dependence on radar by both military and civil
duce a signal which is additively mixed with the
aviation. the number of installations of digital
radar video to achieve a high detection probability
data processors will increase many fold and that
at the integrator output. Suitable timing of the
beacon trigger with respect to the radar trigger
the art of digital processing of radar data will
insures registration of the radar return and
steadily advance toward the solution of many of
beacon response from the same target.
the complex problems still confronting the radar
designer.
As shown in figure 15, the Normal and MTI
signals are then gated on a range basis so that
the MTI signal is selected for short ranges where
clutter is prevalent and the normal video, exhibiting a slightly higher sensitivity, is selected
for the longer radar ranges. The resulting signal is then passed to the binary sweep integrator
which effectively eliminates false alarms produced by receiver noise and enhances system
sensitivity. The integrator output actuates a

74
2.2

RADAR
TRANSMITTER
AMPLITUDE
DETECTOR

RAW VIDEOS
TO
FURTHER DATA
PROCESSING

RECEIVER
PHASE
DETECTOR

ENVELOPE OF
TRANSMITTED PULSES"",
SIGNAL
STRENGTH

ENVELOPE OF
RECEIVED PULSE

~14---6
r l 4 - - - --

t--.....I
T

I 4 - - r-

-----..j.1

t----.-I

TIME

Fig.!. Basic Radar System.

VIDEO IN - - - - - - .

DELAY LINE

VIDEO OUT
VIDEO IN

(T)

1- k

Fig. 2. Simplified Video Sweep Integrator.

VIDEO OUT

75
2.2

Fig. 3. Typical PPI Display.

THRESHOLD

SAMPLE
AND
INTEGRATE

RADAR RECEIVER VIDEO
QUANTIZED VI DEO

QUANTIZER

RANGE TIMING

..1lJ1J1.JLIU"l

Fig. 4. Digital Quantizer for Radar Video.

2.2
THRESHOLD

.
QUANTIZ ~
OUTP UT

( Xi )

· Tf

L-

X~
16

DELAY
(T)

START TAR GET

~ COMPARATOR

ADD

END TARG ET

,~~

XiOl1

_11111111111111111111111111111111111111111111111111111I111I

nT
16

(n+m)T

TIME

---------------- - - - - - - - - - - - - - - - - - - - - - - - - - - THRESHOLD

TIME'

Fig. 5. 16-Hit Digital Sliding-Window Integrator.

J= l-15

QUANTIZER
OUTPUT

(Xd

I'---_....IWWIIIII

1I.u.wu.u1
III IIII l.u.wu.ulll
II II 11w.u.u.w1111ll111w.u.u.w1111ww.w.1II
11lll 1II.111W.LLLILIIIIIII_

TIME

16 - - - - - - - - - - - - - - - -

Si.

THRESHOLD

TIME

Fig. 6. 16-Hit Digital Sliding-Window Integrator.

51 = Xi +S(i-1)

-16

SN=
XJ
J= N -15

•

~--=

ADD
4• •

~ 4~

} Si

--..-

SUBTRACT ~

DELAY

~~~~·~~-1~~~'~

(T)

~ ~
·

SNT

STORAGE ~

I
Xi

---'

GATE

"~I---.....I

~--~.~--

1"""1

~IT--"""
NT

I11111111111111111111111111111111111111111111111111111III II

TIME

THRESHOLD (
----

41111111111 """" 1111'''"111'' "" 1111" 11111 11111111 11111111 II 111111111111 II 1111111111).

Fig. 7. 16-Hit Digital Moving Sum Integrator.

TIME

~--l

t-.:)--l

78
2.2

Fig. 8. Drum Memory for Radar Data Processing.
I

TRIGGER
PULSE
GENERATOR

SELECTABLE
RADAR
TRANSM ITTER
DELAY

I---

RADAR
RECEIVER

...

QUANTIZER ~

COMPLEMENTARY
DELAY
4

,
To

D~['A

PROCE SSING
JITTER
PROGRAMMER

Fig. 9. Digital J itter-Dejitter System.

79
2.2

Fig. 10. Manual Clutter Mapper.

VED~ DETECTOR
PHASE ~

RECEI
VIDE ~ Afy1~

FROM

ANALOG
-TODIGITAL
ENCODER

[
CORE
Ml:MORY
o LAY
(T)

REFERENCE 10.. pSC I LLATOR
Fig. 11. Digital MTI System.

---

~
~
~
~

III

".""

TPUT
SUBTRACTR ~

80
2.2

BRACKETS
./13 CODE BITS

illl

~
I

I
!

I
I
I

I
I

I
I
I

~
I
I

I
I

..
14----2O'3jJ~s- - - -....1

1+3-~
jJs

REPLY CODE

INTERROGATION PULSE
PATTERN
PULSE

~C>---1

BEACO
VIDEO
IN

S TAN

DELAY LINE (20.3jJs)

DARDIZE~
,

,•,,

~• COlBRACKET
NCI DENCE

• r

READ-OUT GATE

INTEGRATION

>--~

-~
~~

CODE >--~
~~
BIT
COMPARE =~
>--~

1<1

TO
FROM
MEMORY

~~
~~

Fig. 12. Elementary Beacon Data Processing System.

RADAR TRANSMITTER CHAIN
TRIGGER
PULSE
GENERATOR

r--+

VARIABLE
DELAY

MODULATOR

LU LU
TRANSMITTER---....

t
JITTER
CONTROL

- - - - - - - - - - - -....
--

TO
RECEIVER

SYNCHRONIZER

INTERROGATION

CODE
GENERATOR

,L
.......

BEACON TRANSMITTER CHAIN
TRIGGER
PULSE
GENERATOR

r--.

MODULATOR

r--. TRANSMITTER . . . - - - - - -

Fig. 13. Radar and Beacon Transmitter Systems.

NORMAL CHANNEL

2nd.
DETECTOR

1 sf.
DET

J.l

•
l-BIT
QUANTIZER

,DEJITTER

QUANTIZED
NORMAL
VIDEO

MTI CHANNEL
PHASE
DETECTOR

AID

E NC. I---T-v'41

DELAY
(T)

•

QUANTZD

SUBTRAClOR

1+ MTI

VIDEO

FROM
~ REFERENCE
TRANSMITTER
OSC.

FROM
JITTER CONTROL

1st.

2nd.

DET

DETECTOR

•

RADAR
- - BEACON
PULSE·
STANDARDIZER
L....
''-D-E-L-AY---'
LINE
BRACKET
COINC.

INTEG. I

CODE BITS

Fig. 14. Preliminary Video Processing.

•

• DETECTED

READ-OUT
GATE

BRACKETS
CODE
BITS

~CX)

r-." .....

~CX)
~~

BEACON
COD
BITS
TRIGGE

RANGE
OSCILLATOR

NORM L
MTI
BRACK

r.
..-....

RANGE
COUNTER

FROM_~

COUNTER

AZIMUTH
COUNTER

MIXER

....

.....

•

INTEGRATOR

DETECTOR

Ai: : BUFFER
EST. I STORE

....

WORD
FORMATION

~J
OUTPUT
TRANSMITTER

Fig. 15. Final Video Processing.

OUTPUT

83
2.3
ORGANIZATION AND PROGRAM
OF THE
BMEWS CHECKOUT DATA PROCESSOR
A. Eugene Miller
Senior Member, Technical Staff
Auerbach Electronics Corporation

Introduction
The Ballistic Missile Early Warning System
(BMEWS) Checkout Data Processor (CDP) is probably the first medium-size digital processor
to perform the real-time, on-line checkout of
an entire operational radar detection. and
processing system. This paper is the first to
describe the unique organization of the BMEWS
CDP and the unusual structure of its program.
It also states many of the detailed characteristics of the CDP. The Checkout Data Processor
has several modes of operation. As a point of
reference, the mode which inserts a "realistic"
sequence of events into BMEWS is focused upon
in the following discussion.
The CDP has two functional memories; one
for storing constants and instructions and one
for storing data. The means for jointly using
these two memories and still maintaining the
flexibility associated with single memory
machines is brought out. The features tailored
in the CDP for efficiently handling its problem
are emphasized. They include real-time program
interrupt signals and a complex Input-Output
System. This Input-Output System, as well as
communicating with over a dozen other digital
data handling devices, has more than 250
separate addresses.
The structure of the CDP program is the
other area focused upon by this paper. The
material covered describes the three separate
programs which run in an interwoven fashion.
This interweaving and the effect of the realtime program interrupts are brought out.

Max Goldman
Manager, Checkout, Monitoring,
and Electrical Integration, BMEWS
Radio Corporation of America

produce a report. Each report is transferred
to the missile impact predictor which stores
and correlates the various radar dat, take-off
reports. On the basis of these reports, the
missile impact predictor prepares various
reports such as a report containing the values
of the parameters associated with an observed
missile trajectory.
The CDP controls the insertion of a
simulated sequence of returns into the front
end of BMEWS. At the same time, the test tag
is issued to the appropriate radar data takeoff to indicate that the return is simulated.
The test tag remains with the data throughout
the system to differentiate test information
from real information. As the radar data
take-off correlates the simulated returns,
the report that is produced and sent to the
missile impact predictor, is also sent to the
CDP.
The missile impact predictor uses the
data take-off reports to produce reports of
its own. These reports are also sent to the
CDP.
Organization of the CDP
It is convenient to consider the CDP as
being composed of five major subsystems;
Wired-Core Memory, Coincident-Current Memory,
Arithmetic and Logic Unit, Input-Output
System, and Control System. A block diagram
of the CDP subsystems and their interrelation
is illustrated in figure 2.
Wired-Core Memory

This paper is the first comprehensive
public description of this major subsystem of
the Ballistic Missile Early Warning System.
Role of the CDP in the BMEWS
The BMEWS Checkout Data Processor has the
primary purpose of determining the operability
of BMEWS by inserting either test patterns or
a "realistic" sequence of events into the
system, and then evaluating the BMEWS on the
basis of its response.
Figure 1 illustrates the way the CDP fits
into the BMEWS. In the normal or real situation, a radar data take-off collects radar
returns on a target and assembles these to

The Wired-Core Memory, which is a form of
the Dimond ring translator, stores the program
and constants used by the CDP. It contains
4,096 storage locations. A Wired-Core Memory
was chosen for two reasons; namely, speed and
reliability. Figure 3 illustrates the instruction word format as it appears in WiredCore Memory. Since the CDP has two diverse
types of memories, the locations of each of the
types of memory are called by different names.
The Wired-Core Memory locations are called
"locations" and the Coincident-Current Memory
and input-output locations are referred to
as "addresses".

84
2.3
Bits XQ, X1t and X2 are used to specify the
operation modification. Four configurations of
XO, and Xl, and X2 are interpreted as follows:
when XQ is zero the operation is specified by
X3 through X7 with Xs through X19 specifying
the accompanying address or location. Bit X2
is the parity bit associated with X3 to X7.
Three other configurations of XQ, and Xl and
X2 when Xo is one specify an operation to be
performed with a constant. In these cases X4
to X21 are used to specify the constant. These
bits are actually transferred into the arithmetic unit as data.

Coincident-Current Memory. The Arithmetic and
togic Unit also directly sends information to
the Output System. The data derived from the
addressable inputs or sent to the addressable
outputs are used in essentially the same way
as data sent to and from the Coincident-Current
Memory. For example, one input address contains the azimuth position of one of the radars.
The contents of this address can be read into
the accumulator as though it were data from
the Coincident-Current Memory.

In the normal operations, i.e., when the
operation modifier indicates that X3 through X7
is to be interpreted as the operation and not
part of a constant, X20 through X22 are used l to
indicate which of the index registers are to
be used with the instruction. There are three
independently used index registers. There is
one exception to the above statement in which
X20 through X22 indicates a specific bit in the
accumulator which is to be tested.

The Coincident-Current Memory of the CDP
is composed of 1,024 addresses. This memory
has several functions. One of these functions
is to act as an input buffer for various realtime asynchronous input sources. There are
buffers for data reports from the radar data
take-offs and reports from the missile impact
predictor as well as information from an
input magnetic tape. Also, there is an output
buffer which is used to store information required in simulating RF returns. When a data
word is required by or available from an outside source, the program is interrupted for a
memory cycle during which time this data word
is removed from or stored in an allocated
address in the Coincident-Current Memory. The
interruption occurs without the knowledge of
the program.

One of the tailored features of the CDP is
concerned with performing table lookups of
constants stored in the Wired-Core Memory. The
sequence of instructions is initiated by a
normal instruction which performs two functions.
The first function is to store the location of
the next instruction in a fixed address of the
Coincident-Current Memory. The second function
is to jump to the address specified in the instruction itself. This address may be modified
by the various index registers. The jump leads
to an instruction which contains an operation
modification. This operation modification adds
the constant specified in the instruction into
the arithmetic unit and then control is transferred to the location specified by the fixed
address in Coincident-Current Memory. This
same technique can also be used to enter and
leave sub-routines as well as perform table
lookups.

Coincident-Current Memory

Other functions of the Coincident-Current
Memory include storing intermediate results
and control information developed and used
within the program. Also, the indirect address
feature and standard address feature previously
mentioned are facilitated by the use of
Coincident-Current Memory.
Input System

Arithmetic and Logic Unit

The Input System can be considered as composed of two diverse parts. There are demand
inputs which supply information such as the
radar position vector and console commands, and
asynchronous inputs which supply magnetic tape
information and system reports. Each separate
demand input is associated with a particular
address. As was stated previously, these
addresses can be read or acted upon in a normal
fashion. There are over lS0 addressable inputs which fall into 36 different classes of
information. The Input System has the facility
for communicating with well over a dozen other
digital data handling devices including a pair
of IBM 7090's.

The Arithmetic and Logic Unit contains an
accumulator and associated registers and control
circuits for carrying out addition, multiplication, subtraction, division, shifting, masking,
and so forth. This unit obtains input data by
directly addressing the Input System or via the

The asynchronous inputs are stored in the
Coincident-Current Memory by interrupting the
program control over the memory for single
read-write cycles. Beside information from
the input magnetic tape, the CDP receives, by
means of this Coincident-Current Memory

Another feature added to the instruction
repertoire to give desired flexibility in using
the Wired-Core Memory is an indirect jump. This
instruction, in Wired-Core Memory, specifies an
address in the Coincident-Current Memory which
contains the location in the Wired-Core Memory
to which control should be transferred. Thus,
variable linking can be accomplished by changing
the contents of the Coincident-Current Memory
address involved.

2.3
interrupt feature, 12 different types of mesages from other processors in the system with an
average of six to seven items per message type.

built-in priority system to handle simultaneous input-output requests as well as the
address control for storing the data.

Output System

Another feature, also previously mentioned,
is the incorporation of a timer in the Control
Unit to establish the sampling period for
measuring the variable frequency oscillator
outputs. This is a two-phase timer that
allows the sampling of the VFO output to take
place for a fixed period of time followed by a
period of time during which no sampling takes
place. This dead period is used by the program
to compute the necessary corrections and also
to apply new inputs to the VFO's.

The Output System has the same dicotomy as
the Input System. There are over 75 addressable
outputs which fall into about 15 classes. A
major portion of the Output System is associated with a target simulator which actually produces the simulated returns and accompanying
test tags. Figure 4 shows one of the target
generators of the target simulator. An output
address is associated with a digital-to-analog
converter (DACON) which is used to control the
amplitude of the desired output signal. Another DACON, which is loaded by the program,
controls a variable frequency oscillator (VFO).
The modulator controls the amplitude of the
output signals generated by the VFO. The range
value is placed into a counter by the program at
some time prior to the initiation of the radar
main bangle At the beginning (leading edge) of
the main bang, an oscillator is connected to
this counter providing an output at an appropriate time to simulate a return at the range
desired. This counter output lasts for the
duration of the desired return. As a result,
the output of the target generator is a pulse of
the correct amplitude and frequency at the desired time to simulate the return from a target
at the corresponding range. It is worth noting
at this point that the CDP acts as the controlling element in a feedback loop for the
variable frequency oscillator. The output of
the VFO is fed into a counter for a fixed period
of time. This average frequency is sampled by
the program to produce a new value to obtain the
desired frequency. The new value is placed into
the digital to analog converter which controls
the VFO. This subject will be discussed in a
later paragraph.
A summarizing fact which further indicates
the unusual complexity of the Input-Output
System is that there are more than 1,300 connections for the addressable inputs and outputs
alone.
Control Unit
The Control Unit, besides containing the
facilities usually associated with control
functions of internally stored program digital
computers, has five features used in interesting
ways. The first of these features, which was
mentioned previously, is the ability to recognize signals from the Input-Output System.
These signals indicate to the Control Unit that
a memory cycle is to be usurped for asynchronous
input-output reasons. The Control Unit has a
1. Reference to a radar main bang is confined
to the leading edge. Reference to an interpulse period is defined as the time between
successive main bangs.

One of the more highly tailored features
of the CDP is the three index registers and
their use. The discussion of these index registers is included in the Detailed Characteristic Section. Other features associated with
the Control Unit are the inclusion of a
special tag register and the presence of program interrupt signals which relate to the
occurrance of the radar main bang. These
features are discussed in the Programming
Section.
Detailed Characteristics
A binary numbering system is used in the
BMEWS CDP with a data word length of 18 bits
plus one bit for parity. Accessing an instruction from the Wired-Core Memory and
modifying the address by index registers requires four microseconds. There are two
memory accesses per instruction: one memory
access of the Wired-Core Memory for the instruction itself and another access from the
Coincident-Current Memory or input-output
address. In either case, 8.8 microseconds is
involved in the access and manipulation of
data for basic instructions. Therefore, an
instruction such as an addition requires 12.8,
microseconds to complete; including the instruction access and modification of the
address by index registers.
The CDP uses 27 out of the 32 possible
instructions facilitated by the five bits
of the operation code. There are also the
three operation modifications for use with
constants.
The.Wired-Core Memory contains 4,096 23-bit words. The Coincident-Current Memory
contains 1,024 - 19-bit words. Both memories
use a binary addressing system and all data
and instructions are addressable by words.
The CDP contains three index registers - a
three-bit register, a four-bit register and a
five-bit register. The contents of each of
these registers are logically added to the
address contained within the instruction.

86
2.3
There is no time penalty associated with the
use of the index registers. The index registers
mix into an address in the following fashion:
3 Bit Reg.

Bi~

Reg.

X9~~X14 X~5 X~IX17

XiS X19'

4 Bit Reg.
There are specific operations which use
indirect addressing only. There ~s no time
penalty associated with such operations, that is,
they require 12.8 microseconds to carry out.
The BMEWS CDP is capable of simultaneously
carrying out input operations while performing
arithmetic computations. For example, the
program performs a single instruction which is
a start-tape command. The program then ignores
the tape input operation, while performing
arithmetic operations, until an appropriate
time when an inspection of the tape input buffer
reveals the required information.
Information is stored on the input magnetic
tape as 6-bit characters plus a parity bit
(character parity is odd). There are 120
characters to a tape record: .IThree 6-bit characters are assembled by the Input System to
form one 18-bit CDP word. Thus, the input
magnetic tape buffer size (in Coincident-Current
Memory) is 40-CDP words. The Input System
supplies an entire word to Coincident-Current
Memory during each transfer operation. The
nominal tape reading speed is 15,000 characters
per second.
The output console printer is controlled
by a 40-bit buffer which is addressable by the
CDP. These 40-bits are composed of ten 4-bit
characters. The printer operates at twenty
10-character lines per second.
The clock rate of the CDP is 1.25 mega~
cycles. It contains about 8,000 transistors
and between 40,000 and 50,000 diodes. The
CDP is mechanized by NOR type transistor-diode
logic.
Structure of the CDP Program
The CDP program must carry out the func~
tions associated with several checkout modes.
Each of the modes is designed to evaluate the
BMEWS from a slightly different point-of-view.
Some modes insert "realistic" raids into the
BMEWS while other modes insert test patterns
into the BMEWS. The CDP program is composed
of three parts; the simulation program, the
evaluation program, and the executive program.
These programs are used in all of the checkout modes.
Each of the programs is composed ~f routines. The mode determines which routines of
each program are to be used for the processing.

Figure 5 illustrates the organization of the
CDP program. The processing proceeds from
the executive program to the simulation program and back to the executive progra~. From
the executive program the processing then
proceeds to the evaluation program. The
soli~'lines are used to indicate a programmed
connection between separate programs. The
dotted lines connecting the evaluation program
to ~he executive program signifies an automatic
transfer caused by the program interrupt
feature.
The program interrupt feature is best
explained in relation to figure 6 which illustrates the CDP program timing. At each radar
main bang the CDP program is interrupted and
control is transferred to the executive program. This interrupt should only occur during
the evaluation program. A special tag register, previously mentioned under the Control
Unit, carries an identification of the program
which is in proces~. The executive program
after the transfer of control has taken place,
caused by the program interrupt, inspects the
contents of the tag register to insure that
the interrupt occurred during the evaluation
program. The executive program stores the
interrupted state of the CDP when the interrupt
occurred, and then interprets the mode and sets
up various linkages required for the mode if a
mode change has occurred. Control is then
transferred to the appropriate simulation
routine.
When the scheduled simulation routines
have been completed, control is transferred
in a programmed fashion back to the executive
program. The executive program determines
where in the evaluation program to resume
processing and sets up the state of the CDP
for the resumption. The evaluation program
is then resumed. As will be seen shortly, the
evaluation program is essentially a non-ending
program so that it continues processing until
the next program interrupt signal.
The executive program coordinates the information flow between the simulation and
evaluation programs. The executive program
accomplishes this task by having its routines
perform such functions as determining the mode
and inspecting to see that the program interrupt signals are in the proper sequence,
connecting the proper simulation and evaluation
routines used in a given mode, and determining
the malfunction of the CDP by inspecting the
contents of error registers, etc.
The simulation program is composed of
routines which generate information defining
the signals to be injected into the system.
This information is used to control the
checkout target simulator which actually
creates the signals and sends them into the
front end of the BMEWS. The routines of the

2.3
simulation program are of such nature that they
must be completed by specified times in order to
be of use. Therefore, these routines are synchronized by the program interrupt signals.
The simulation program performs three
major functions. These are:
(1)

Determines the system status (connections between BMEWS major subsystems) ,

(2)

Controls the target simulator.

(3)

Prepares the values for the parameters
of anticipated messages for use by the
evaluation program.

The evaluation program processes the information received by the CDP from the BMEWS
in order to evaluate the operability of BMEWS.
There are also evaluation routines used to
organize information to be printed, out; this
infbrmation is pertinent to the evaluation of
the operability of BMEWS. Likewise, there is a
routine in the evaluation program for determining CDP failures. Evaluation routines, unlike the simulation routines, do not have to
be kept in step with events of each main bang
period, but must only meet time requirements
in the large. The evaluation program, once
started, continues from evaluation routine to
evaluation routine until interrupted by a
program interrupt signal.
The evaluation program is divided into
three priority classes of routines; routines
corresponding to a given mode of operation of
the first class precede those of the second
class which in turn precede those of the third
class within a main bang period. The highest
priority classes are always initiated in each
main bang period (or continued if it has been
interrupted, see below). This highest priority
class is initiated by the executive program
after program interrupt 1 (see figure 6). The
three sets of evaluation routines are called
Class I, Class II, and Class III with the
highest priority being Class I, the next priority Class II, and the lowest priority Class III.
Thus, the uninterrupted processing sequence
would have the Class I routines processing
all their applicable data, followed by the
Class II routines processing all their applicable data followed by the Class III routine.
The Class III routine (error detection routine)
is a non-ending routine, Le., the "end" of
the routine leads back to the beginning.
The CDP program is organized to begin the
processing of a given class of evaluation
routines at the point of interruption of the
interrupted routine of that class. If a given
evaluation process was not interrupted then
processing begins at the first routine of that
class.

Figure 5 illustrates the organization of
the three classes of the evaluation routines
in the CDP program. The possible returns to
the evaluation program are shown inside the
executive program. Note that there is a path
from each interrupt to the starting of the
Class I routines each main bang.
The evaluation program performs three
major functions. They are:
(1)

Process messages received from the
rest of BMEWS - using anticipated
values from the simulation program.

(2)

On the basis of (1) - turn on
appropriate console lamps and
pr!ntout appropriate information.

(3)

Check the operation of the CDP
itself.

The evaluation of system reports is
illustrated in figure 7. The evaluation
routine picks up the value for each of the
parameters in the received report and subtracts the corresponding anticipated value.
A new message is composed which contains the
message type, the target tag, the anticipated
value for each of the parameters and the
calculated difference between the received
value and this anticipated value. This new
message is a candidate for printout. The
criterion for printing the message is that
the deviation of the value for at least one
of the parameters is larger than the specified
tolerance. If all of the deviations are
within the specified bounds, normally, the
message is discarded. However, subject to a
switch setting on the console, all such printout candidates can be printed-out for the
purpose of data collection. An out of
tolerance deviation is marked appropriately
to identify this situation to the operator.

Summary
A program interrupt occurs at the beginning of the radar main bang (figure 8). This
interrupt causes the executive program to
store the state of the CDP and proceed into
the simulation program. The simulation
routines, which are carried out at this time,
control the variable frequency oscillators
of the target simulator and check to see that
the BMEWS status has remained stable. That
is, there has been no change in the way the
major subsystems of BMEWS have been linked
together. The completion of these two
routines returns the program to the evaluation
program by way of the executive program.
The evaluation program inspects the
Coincident-Current Memory for information
coming into the area reserved as system
report input buffers and, if information has

88
~3

been received, compares these reports with
anticipated reports also stored in the Coincident-Current Memory by the simulation program.
The evaluation program is eventually interrupted
by program interrupt 1. Console switches are
inspected to see that the CDP is still to remain
in the present mode or change modes. The
simulation program is then initiated.
The simulation routine which is carried out
at this time calculates the inputs required by
the target simulator at the end of this main
bang to simulate returns following the subsequent main bang. This calculation is based
upon the system status, the particular position
of the various beams, and target data which had
~reviously been stored in the CoincidentCurrent Memory by the magnetic tape portion of
the Input System. 'The simulation routine,
prior to start~ng its calculation, initiates
the reading of a record from the input magnetic
tape for use during the next inter-pulse period.
Data used in this inter-pulse peri04 had been
read in during the previous inter-pulse period.
The results of the calculation of this simulation routine are stored in Coincident-Current
Memory ready for transfer to the target simulator at an appropriate time.
The evaluation program is then re-entered
via the executive program. Here the executive
program restarts the Class I routines if they
had not just been interrupted. If they had
just been interrupted by program interrupt 1,
the interrupted situation is resumed. Again
the evaluation program continues until the
next program interrupt occurs. At this point,
the executive program leads to the simulation
routine that transfers the information previously calculated for the target simulator
into the target simulator.
The target simulator must be quies~ent
during the period of time that the program
transfers new parameter values into the range
counter. Therefore, the maximum range that
can be simulated is limited by the period of
time associated with this transfer. In
actuality, program interrupt 2 marks the end
of time when the target simulator is capable
of producing a simulated return during the
ma~b~.

Thus, each main bang, data taken from the
input magnetic tape during the previous main
bang and stored in Coincident-Current Memory
is used together with system information to
produce control information for the target
simulator. This information is transferred
into the target simulator at the end of the
main bang. During the next main bang, while
this same calculation prpcess is being repeated,
the target simulator inserts into the system,
if required, simulated RF returns and corresponding test tags. This process dontinues
main bang interval after main bang interval.

The radar data take off correlates the inserted signals and issues reports to the
missile impact predictor. These same reports
are shipped to the CDP and stored in the
appropriate area of the Coincident-Current
Memory. The evaluation program continues
to inspect this portion of the CoincidentCurrent Memory sensing for such reports.
When a report is received, it is evaluated
by using the anticipated report produced by
the simulation program. If an out of tolerance
situation is discovered, information is shipped
out to the operator by means of the printer.
Radar data take off reports are collected
by the missile impact predictor and used to
produce various other reports. These reports
are shipped to the CDP and stored in the
Coinc~dent-Current Memory.
In a similar
fashion, the Checkout Data Processor compares
these reports with anticipated reports
and indicates to the operator the result
of such processing. In this way, the Checkout
Data Processor using its equipment and its
program in an interwoven fashion, generates
simulated RF returns, injects these returns
into the front end of BMEWS, receives the
effect that these signals have on BMEWS,
and on the basis of these effects, evaluates
the operability of the overall system.
Finally, the checkout device, being a major
part of BMEWS, evaluates its own operability.

Radar
Data
Take Off
/
/

Missile
Impact
Predictor

x
/~'------~------"

Radar
Data
Take Off

Simulated
RF Return

CDP

Figure 1.

CDP in the BMEWS

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2.3

Wired-Core
Memory

r------I
I
I

I
I

Arithmetic
Logic
Unit

I r--- --I II

I '--------

CoincidentCurrent
Memory

I
I

I
I
I

L ___ _

Figure 2.

Input-Output System

Organization of the CDP

rG
T

Operation Parity

Operation

Address Modifiers

Address or Location

\
If

XO Xl X2 X3 ,X4 Xs X6 X7 Xs X9 XIO XII Xl2 Xl3 Xl 4 XIS Xl6 Xl7 XIS Xl 9 X20 X2 l,X 22
Constant

Operation Modification

Figure 3.

Parity for Constant

Wired Core Memory Word Format

~-.o

tAl"""

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Amplitude (A)

A
C

o
N

Frequency (f)

D
A

Modulator

o
N

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Average
Frequency

Range (R)

Counter

Figure 4.

Target Generator

Simulation
Program

JII'

..".

Executive
Program

11\

'1\

I
I

Class I
Routines

,......

Figure 5.

Class II
Routines

......

I
I

Class III
Routines

Evaluation
Program

Organization of the CDP Program

t-.:II,O

94
2.3

Radar Main
Bang

Executive
Program

Program
Interrupt

Simulation
Routine(s)

Executive
Program
Evaluation
Program
Executive
Program

1 - Program
Interrupt

Simulation
Routine(s)

Executive
Program
Evaluation
Program

2 - Program

Executive
Program

Interrupt

Simulation
Routine(s)

Radar Main
Bang

Figure 6.

Executive
Pro2ram
Evaluation
Program

o - Program
Interrupt

CDP Program Timing

2.3

Message Test
Target
Number (N)

Target
Number (N)

RDTO
Range

Range Rate

Signal

Anticipated
Report

Print Out
Candidate

yes . . . .

Print
Out

For any P?
No

\V
Discard
Message

Figure 7.

6A
EA

6R
Azimuth
AA
Elevation

Received
Report

N
RA
6~

Evaluation Process

SA
68

Executive
Program

Simulation
Routine(s)

Executive
Program

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97
2.4

HIGH-SPEED DATA TRANSMISSION SYSTEMS
R. G. Matteson
Stromberg-Carlson
a Division of General Dynamics Corporation
Rochester, New York
Introduction
For many years data and messages
have been transmitted from point to
point over slow speed data communication systems by telegraph. There is a
rapidly growing increase in the use of
centralized data processing equipment
in large corporations however, making
increasing demands upon existing data
communication systems. Development has
been carried out at Stromberg-Carlson
during the past few years toward increasing the capabilities. of the
standard telephone facility for the
transmission of data at higher speeds
and with greater reliability. It, is
felt that this equipment will have
widespread use in the business data
field, the scientific field, the automatic control field, and for military
data communication systems. Typical
components required for the transmission
of data ove~ tetephone lines at high
speed include input/output eqUipment,
buffer converters, modulatorldemodulators, and of course a transmission path.
Stromberg-Carlson has developed a
modulator/demodulator unit using a
unique modulation prinCiple specifically
designed for minimizing the effects of
the various types of distortion and
interference associated with wireline
systems. In addition, an installation
has been completed for the Convair
Division of General Dynamics Corporation which transmits data in the form
of punched card information over a
telephone line more than 200 miles long,
and records the information on magnetic
tape in a format compatable with IBM
704 programming.
Applications
Since the processing of data by
digital computers is becoming common
practice throughout many types of
endeavors, the applications for the
transmission of data at high speed
over standard telephone facilities

appears to be very wide spread. Some
of these areas will be discussed in the
following paragraphs.
Many corporations are facing a
decision today between large computers
at a central location in the corporation
or many small computers geographically
separated at the various divisions. If
a centralized computer facility is required for performing all the various
operations and data processing for a
corporation, the data must be transmitted from remote divisions of the corporation into the central data processing
center. For a moderate size corporation
this data can reach significant proportions and can only be transmitted by
air mail or many slow speed data transmission systems operating in parallel
at the present time. The availability
of equipment to transmit data at higher
speeds over telephone facilities which
are normally available for telephone
communications will assist in solving
the data handling problem. For the
cO,rporation which decides to use individual smaller computers at each division,
data transmission can still be of considerable benefit. For these corporations, high speed transmission of data
can mean faster reporting between divisions and the possibility of using remote computers if theJocal computer
becomes overloaded during peak operations.
Many corporations are looking towards automatic data collection, data
acquisition and transaction recording
systems to accelerate the over-all data
proce'ssing and reporting cycle. These
systems will be used for such things as
the compiling and accumulation of data
concerning job moves, stockroom transactions, job change~, inspection results
and attendance recording. This data may
be recorded for several manual input
units at an intermediate collection
point. The data must then be transmitted from this intermediate collection
point to a central collection agency

2.4

(Figure 1). For a sizeable corporation,
the amount of data transmitted into the
central recording facility will be considerable. Transmission must therefore
occupy a minimum of t~me in order to be,
able to submit all da~a from each of the
intermediate collection facilities, requiring high-speed transmission of data
over standard wireline facilities.
Some types of businesses such as
banks and insurance companies have
requirements for large data retrieval
systems. In this case, a central file
of information, upon receiving an
inquiry from a remote station, will
transmit the data requested in the inquiry. In this example, the amount of
data transmitted during the inquiry is
small, but the amount of data transmitted during the reply by the data
file may be large indeed depending upon
the particular application. In order to
satisfy a number Qf independent inquiries in a reasonable amount of time, data
will have to be transmitted at high
speed over wireline facilities.
For the solving of scientific problems, large scale computer facilities
are required in order to handle the more
complicated problems expected. For some
of the large computer facilities required, it is economically impossible to
duplicate a facility at remote corporation installations. In this case,
remote facilities can use a large scale
computer facility for the solution of
scientific problems by transmitting the
program and input data by high-speed
data transmission systems to the central
computer facility (Figure 2). The problem solution can then be transmitted
back to the originating site.
It is also occasionally possible to
break down a large problem into subproblems which can be worked independently by separate computer facilities.
In this case, various computers throughout a wide-spread corporation can be used
for solving parts of the same problem
by means of high-speed transmission of
data over telephone facilities.
The solutions to scientific problems transmitted over the high-speed
data transmission system can be tabulated, reported or plotted by the use of
direct on-line high-speed printing equipment.

For applications where digital
computers are useQ in the automatic
control of process or operating conditions, much data is transmitted between
the operating system and the computer
control system. In the case of process
control computers, the requirement is
for the transmission of measured values
of the operating system, the transmission of control signals to change the
operation of the system and the transmission of data to various indicators
allowing manual supervision of the
operation of the system.
Operation of organizations such as
gas and pipe lines, and railroads requires the transmission of operating
data over long distances. This data
can be economically transmitted at
high-speed over the same wire-line facilities normally used for voice communication.
Many requirements exist for the
transmission of considerable amounts
of data for military systems. Militarysystems such as the SAGE (semiautomatic ground environment) system for
the detection, tracking and interception
of enemy aircraft requires data to be
transmitted between acquisition sites,
control centers, and intercepter centers.
With the military striving for
higher speeds under tactical conditions,
automatid displays and even the computer
analysis of tactical situations provides
a requirement for the transmission of
digital data.
Logistic Systems such as the Air
Force COMLOGNET System will be used to
transmit a tremendous amount of data
concerning logistic information throughout the Air Force.
EqUipment ReqUirements
Any generalized Data Communication
System can be broken down into input/
output components, buffer converter components, modulator/demodulator components, and the transmission path (Figure 3).
The input/output eqUipment may
consist of punched tape, punched card,
or magnetiC tape readers, manual input

99 '
2.4

keyboards, FLEXOWRITER, or electric typewriter equipment. The input/output equipment can also consist of the buffer
storage portions of general purpose computer installations.
The buffer converter unit at the
transmitting terminal of a data transmission system must accept the data from
an input device, and transform this data
into the proper format for application
to the modulator unit. This may require
parallel to serial conversion, temporary storage, and level changing. The
buffer converter may also change the language of the data as in the case of card
to tape transmission. Also, it may be
required to add checking information to
the transmitted signals. At the receiving terminal of the Data Transmission
System the buffer converter must accept
the data from the demodulation unit and
convert it into the proper format for
recording on the output device used.
This operation may mean serial to parallel conversion, temporary storage, and
the generation of additional format information such as inter-record and interfile gaps normally required for preparing
magnetic tape for IBM computers.
Error circuitry is required at the
receiving terminal improving or at least
indicating the reliability of data transmission. Errors can be detected by checking vertical and horizontal parity bits
in the transmitted data, and indicating
these to the operator at the receiving
terminal. This gives a measure of transmission reliability but does nothing to
correct the matter. In the event of an
error circuitry can also be included to
cause automatic retransmission of the
previous block of data. Using this
techniq~e, the final received and recorded data will be more reliable by several
orders of magnitude than if automatic
retransmission were not used. Another
technique can be used which would correct
certain types of errors in the transmitted data at the receiving terminal without requiring retransmission. By storing
a complete block of data and checking
horizontal and vertical parity signals,
single bit errors in the transmitted
message can be corrected automatically.
Alternatively, if the information is destined for computer data processing, a
program can be incorporated into the
data processing routine to perform the
same function, thereby simplifying the
data transmission system.

The telephone line which wi~l transmit voice information satisfactorily will
not necessarily transmit data reliably;
for example, impulse noise of very short
duration may cause bits of information to
be changed, added or deleted in the data
being transmitted which could have serious
consequences in the business data applications. Similarl y, a frequency translation will have serious effects on some
types of data modulation techniques,
but will hardly be apparent during voice
transmission. Certain minimum requirements for line characteristics must be
satisfied depending on the type of modulation/demodulation equipment used in
the system.
Equipment Description
Data transmission equipment 'which
has been developed at Stromberg-Carlson
will be described as examples of the components mentioned in the preceeding sections.
A tape transmission terminal suitable for tape to card, card to t~pe, and
tape to tape systems is shown in Figure
4. A tape transport has been selected
for low cost, reliable operation. The
buffer converter is designed to accept
data from the tape transport, convert it
to a serial form, and provide control and
synchronization signals to the receiving
terminal. These and oth'er functions of
the buffer converter are shown in Figure
5. The end of the file is automatically
recognized by the buffer converter and the
tape transport is turned off. In the event
of an error recognized at the receiving
terminal, the retransmission signal is
recognized by the buffer converter and
the data record in error will be retransmitted by reversing the tape transport
and transmitting that record over again.
The receiving portion of the buffer
converter converts serial input data to
parallel data for recording on the receiver tape transport. The data is synchronized to the incoming data by resetting
the character bit counter with a start of
record character. End of record gaps
occurring on the transmitted tape will
also be placed on the receiving tape. At
the end of a file of data, the receiving
tape transport will be stopped.
A modulator/demodulator model SC301 is used to modulate the serial

100
2.4

train of data in a form for reliable
transmission on telephone facilities at
2400 bits per second. The SC-30l converts the input binary information to a
trinary form which then amplitude-modulates a subcarrier signal.' Advantages
of using a trinary, rather than binarY.
baseband signal in~lude the following~·2
(a)

Elimination of low frequency
components, reducing noise
bandwith and easing requirements for transmission circuit characteristics.

(b)

Constant average power level
in transmitted signal.

(c)

Permits use of bistable detector, rejecting noise impulses of one polarity.

At the receiving terminal, the
signal is demodulated and regenerated
to form the original binary information.
A free-running multivibrator is synchronized to the incoming data to provide a clock signal at the synchronous
rate of data transmission. A photograph
of th~ SC-301 in a separate cabinet is
SROwn in Figure 6.
A telephone handset is sunplied on
the front panel of the data
communication terminal for intercommunication capability. This enables the
operators to coordinate the transmission
of data at the beginning and the end of
the transmission. A self-test capability
allows the operators to check out the
transmission link before the start of
transmission. Amplitude and time delay
equalizers are also provided with the
terminal as required to compensate for
characteristics of. the telephone facility.
A card data transmission terminal
is shown in Figure 7. This unit can be
used to transmit data between itself and
another card terminal, a tape terminal,
or a computer input terminal. This terminal has been designed to read punched
cards at the rate of 100 cards per minute. The terminal is similar to the
tape transmission terminal described
above except for the addition of a card
buffer module. The card buffer will
store all of the data on one card as
received on a row by row basis. The
buffer will then feed the data character by character into the buffer converter, which then performs functions similar
to that performed by the tape terminal
buffer converter.

The third type of data transmission
terminal developed at Stromberg-Carlson
is for transmitting data from computer
to computer. This type terminal is
shown in Figure 8 and is exactly the
same as the card transmission terminal
except that the card reader and the
card buffer are not required. The
buffer converter accepts data from the
buffer storage unit of a computer exactly as it would from the card buffer
unit. At the receiving terminal, the
data is provided to the buffer storage
unit of the receiving computer.
Since the tape, card, and computer
data transmission terminals all have
standard outputs, they can be used interchangeably with each other to form
tape to tape, card to card, card to tape,
computer to computer, tape to computer,
etc. systems. A card to tape system
has been installed at the Convair Division of General Dynamics Corporation to
transmit data over a 200 mile telephone
line between Pomona, California and San
Diego, California. This system enables
Convair personnel in Pomona to utilize
an IBM 7043Camputer facility located in
San Diego..
In addition, an SC-3000
high speed communications printer can
be used directly on line at the receiving terminal to print out data.
A new type of tape transport is
being developed for use in specific
applications for data transmission and
data collection systems. This tape
transpor~ will operate in two modes, a
stepping, asynchronous mode or a continuous, synchronous mode. In the stepping mode, the transport can be used
with a FLEXOWR1TER, manual keyboard, slow
speed punched card device or other equipment operating asynchronously. In this
mode the unit can be used to record or
reproduce data character by character
for data recording, collection, and
acquisition applications. In the continuous mode, the transport can be used
as a substitute for the tape transport
discussed previously in connection with
the tape transmission terminal.
The transport can therefore be used
to store data asynchronously and accumulate it over a period of time. The
unit can then be rewound and used to
supply the data at high speeds into a
data transmission system. In this
application a telephone facility can be
used for voice communications most of
the time, since data can be transmitted
at high speed during a small portion of

101
2.4

the day. A block diagram of the tape
transport is shown in Figure 9.
Conclusion
The applications for data communication systems have been discussed.
Equipment requirements have been discussed and examples of equipment meeting.
those requirements which have been developed by Stromberg-Carlson have been described. A special tape transport has
been described which has been developed
to meet a particular requirement in data
transmission systems, where it is desired
to accumulate data at a slow asynchronous
rate and deliver it at a rapid, synchronout rate so as to obtain full time usage
of a telephone facility.
The general approach being taken at
Stromberg-Carlson in the development of
card to tape, tape to tape, and card
to card systems 1s to arrive at a complete line of components which can be
interconnected in flexible fashion to
meet a variety of requirements for
specific data transmission applications.
References:
1.

J. L. Wheeler, "High-Speed Digital
Data Transmission", IRE Fourth National Aero-Com Symposium, Rome, N.Y.,
October 22, 1955.

J. L. Wheeler, "Preparation, Transmission and Distribution of InformatiDn in an Automatic Data Communition System Utilizing Telephone Facilities", A:I:EE Empire District No.1,
1959 Spring Meeting, Syracuse, N. Y.,
April 29, 1959.

F. DaVid, C. J. Zarcone, R.L. Wolfr,
"Card-to-Magnetic-Tape Data System",
AlEE Conference Paper CP60-917, 1960
Summer General Meeting, June 21, 1960.

J. L. Wheeler, "Telephone Line Input
to an reM 704 Computer", IRE Sixth
Annual Communications Symposium, Utica,
N. Y., October 4, 1960.

102
2.4

WORK
STATION
A

WORK
STATION

STOCKROOM
A

INTERMEDIATE
COLLECTION
POINT

INSPECTION
STATION
A

TIMECLOCK

DATA COLLECTING SYSTEM

Fig. 1. Data Collecting System

COMPUTER
FACILITY

TEST
SITE
B

TEST
SITE

A
COMPUTER
INSTALLATION

TEST
SITE

ENGINEERING
LABORATORY

SCIENTIFIC DATA

Fig. 2. Scientific Data

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~~

Ir=

DATA TRANSMISSION TERMINAL
INPUT /
OUTPUT
DEVICE

.......

....

BUFFERCONVERTER

....

.......

MODULATOR /

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DEMODUL~ ..,
J

----------

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DE

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DATA TRANSMISSION TERMINAL
JULATOR /
JDULATOR

....

......

BUFFERCONVERTER

....
.....

......
...

L
GENERALIZED DATA COMMUNICATION SYSTEM

Fig. 3. Generalized Data Communication System

INPUT /
OUTPUT
DEVICE

.:J

105

2.4

Fig. 4. Tape Transmission Terminal

106
2.4

Buffer-Converter Functions

Receiving

Transmitting
Parallel/Serial Conversion

Serial/Parallel Conversion

Generate SOR & EOR Characters

Check Lateral &

Synchronize Data Transmission Rate
and Tape Transport

Generate Retransmission Signal in
Event of Errors

Detect End of File

Synchronize characters to incoming
Data

Cause Data Record to be Retransmitted Upon Receiptof Error
Signal from Receiver

Generate EOR Gap
Detect End of File

Provides Intercom Capability

Fig. S. Buffer-Converter Functions

Fig. 6. SC-301 Binary Data Transceiver

Longitudina~

Parity

lO7
2.4

Fig. 7. Card Transmission Terminal

108
2.4

Fig. 8. Computer Transmission Terminal'

109
2.4

.... DATA

......-

....

BUFFER

.....
~

.....

TAPE
~~

CONTINUOUS
DRIVE

CONTINUOUS
DRIVE
MODE

"
CLOCK

... DATA
.,.

.....

BUFFER

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AUTOMATIC
SPEED
CONTROL

.....

TAPE
~~

STEP-DRIVE
MODE
STEP COM MAND

.....

STEPPING
DRIVE

Fig. 9. Tape Transport Block Diagram

111
3.1

PARALLEL COMPUTING WITH VERI'ICAL DATA
William Shooman
System Development Corporation
Santa Monica, California

Summary
A novel technique called Vertical Data Processing (VDP) for the manipulation of data in digital
computers is presented. Multiple data are processed simultaneously one bit at a time using Boolean
operations. Many classes of problems appear adaptable to this technique.
A hypothetical VDP computer which embodies
both VDP and conventional techniques is proposed
and its advantages discussed.
Introduction
In the continuous quest for increasing the
speed of Electronic Data Processing Machines, two
distinct procedures are available. One is to
improve the hardware technology; the other is to
improve computer organization. This paper is concerned with the latter.
A novel technique for the simultaneous manipulation of multiple data in digital computers is
presented. This technique is called Vertical Data
Processing (VDP), in contrast to conventional
methods which will be referred to as Horizontal
Data Processing (HOP). Data organization for VDP
is described and a VDP machine defined. It is
shown that the time taken to perform VDP operations
is not a function of the number of numbers being
processed.

memory. These numbers are expressed in the computer by a mtrix of bits. In the usual matrix
(UM) each of the r numbers resides in one computer word, or row of the matrix. We have
investigated the advantages of expressing the
numbers by a matrix other than the UM; that is,
by the transpose of the UM (UM!'). In the UM!'
each number resides in a column of the matrix;
consequently, each of its bits is in a different
computer word. Since the computer has direct
access to computer words only, it is not possible
to obtain directly one of the r numbers. Instead
all r numbers are simultaneously processed one
bit at a time by means of the logical operations,
'and', 'not'} 'inclusive or', and 'exclusive or'.
It is clear that Boolean functions can be developed to perform the usual operations of conventional computers (a~ for example, has been done
for serial computers).
The VDP Machine
A VDP machine will now be defined as a
machine which has the hardware to perform computations directly by addressing the data orthogonally. A program simulating a VDP machine
which processes data in UM!' form was checked out
on the 709. The set of simulated instructions
included the arithmetic and logical operations
usual to HOP machines.~ The algorithm used for
the simulated add instruction is now shown.
Add Algorithm and Timing

A VDP machine which processes vertical data
is shown to have certain limitations which are
eliminated by a hypothetical computer design.
General specifications for the hypothetical
mchine (called the Orthogonal Computer) are
given. Descriptions and algorithms for several
VDP instructions (one of which is an add instruction) are given.
VDP logic is shown to be strikingly different
from that of HOP. Masks play the role of decision
functions with the result that there is virtually
no branching in VDP. VDP is applied to the follOWing specific problems; 1) an FICA computation,
2) finding the rank of a number in a sequence of
numbers, and 3) the translation of mnemonic operation codes to their mchine language representation. Time comparisons for VDP and HOP are made.
For these problems VDP ranges from 32 to 660 times
as fast as HOP. Finally a cost estimate for the
Orthogonal Computer is presented and some possible
input/output limitations are noted.

Given two sequences of numbers (A.) and (B.)
(1 S;

j ~

r), we want to compute the r sums S.
J

A. + B.. For the sake of simplicity we will asJ
J
surne that each number consists of precisely n
bits and is non-negative. Let (al j a 2 .••• a j)'
,
,J
n,
(b . b 2 .••• b .), and (s . sl .' •• s .) be
l,J
,J
n, J
0, J
,J
n, J
the binary representation of (A.), (B.), and (S.)
J

respectively. To compute Sj' we give an algorithm to compute si . (i = n, n-l, ••• l).
,J
Let
s.1,J. = a.1,J·0 (b i , j

i ,J.);

Data Organization for VDP
Suppose that we are given r numbers in

See Instruction List in Appendix.

c n,J.

= o·
J

112
3.1

Where CD stands for exclusive or and y. for
sive or.

It is clear that all r sums can be simultaneously computed using this algorithm, if r is
equal to or less than the bit length of the
computer word. In a VDP machine such an add is
executed in 3~ + 1 memory accesses. The number of
memory accesses is a function of n (bit length of
the numbers being processed) only; in particular,
it is not a function of r (the number of numbers).
This important property is inherent in all ~P instructions and will be the basis for a hypothetical
computer design.
Limitations of Data in UMT Form
One limitation of the simulated VDP machine
is that the number of numbers that can be simultaneously processed is restricted to the bit
length of the computer word. Another limitation
is that data must be input in either the UMT form
(that is, vertically) which creates some difficulty; or in UM form and then transposed. Also, data
undergoing VDP is not suitable for HOP be9ause of
the data organization, although it is clear that
some ope~tions can be more efficiently performed
in BDP (for example, suming two numbers). These
limtations can be eliminated by a new computer
design.
The Orthogonal Computer
Consider a hypothetical machine consisting of
a conventional (BDP) ,machine of wor(l length L,
with the added capability of being vertically
addressable in some limited region of memory;
specifically in K nonoverlapping blocks, each
block consisting of R consecutive memory registers.
The vertical addtessing is to be restricted so
that an addreasable column consists of precisely
R bits and is contained in one of the blocks. Consequently there are exactly~times L addressable
columns. The central processor is to contain a
number of vertical registers (each register containing R flip-flops) and VDP hardware relating
these registers to the K blocks. While a computation is being performed in some of the K blocks,
input-output (I/O) may be going on in other blo.cks.
If data are input to a subset of the K blocks in
UM form, processJ.ng in parallel by means of vertical addressing satisfies the definition for a VDP
machine. This machine will be referred to as the
Orthogonal Computer.
Timing for an Add in the Orthogonal Computer
Suppose we have two sequences of numbers (Ai)
and (B i ) (l S i ~ R), each number of bit length n
and non-negative, and we want to compute the'R
sums Si = ~i + Bi • Let (Ai) and (B i ) be in one
or more of the K blocks (depending on the ratio
of n to L) in UM form. Let (ai,l ai,2 ••• ai,n)'
(bi,l bi ,2·.· b i,n)' and (si,O si,l· •• si,n) be the
binary representation of (Ai)' (B i ), and (Si)

Using vertical addressing and the
indicated change in subscript notation, it is
clear that the simulated add algorithm presented
above can generate the R sums (S.) in a subset of
the K blocks. The number of mem5ry accesses is
still 3n + 1. In HOp, 8 times R memory accesses
are generally required to obtain the Si' Consequently, for this type of add instruction, ,with
R equal to (on the order of) 1000, the Orthogonal
Computer r~ges from 55 (n = 48) to 500 (n = 5)
times as fast as HDP. It is to be noted that both
the VDP and. HDP mode may be used on the same data
in the Orthogonal Computer since data are input
in UM
~espectively.

form.

VDP Logic
VDP and HOP differ strikingly in their overall logical flow. THERE IS ESSENTIALLY NO BRANCHING IN VDP. Let us consider· a,'branch point in an
HDP program. Suppose that r numbers (A ) 1 ~ i ~ r
are being processed. Let the branch point partition the r numbers into two classes Cl ~nd C ,
2
(k numbers in Cl and therefore r - k in C~ such
that if Ai is in Cl , then Ai is to be processed
by computation Tl , and similarly if Ai is in C2,
then Ai by T2 • Figure 1 shows the branch in HDP.
In HOP the question must be asked for each Ai and
correspondingly one of the computations Tl or T2
performed. Assuming that as many as r numbers can
be simultaneously processed by VDP, a method is
now described whereby only the results of computation Tl on the numbers in Cl and of T2 on the
numbers in C are obtained.
2
Masking
Whenever a bit is written in memory during
any VDP operation, the bit must pass through a
gate. A gate is represented by a zero or one.
A gate is open (allowing pass through) if its
representative is a one. If its representative
is a zero, the corresponding bit location in
memory is left undisturbed. A string of representatives (bi ) 1 ~ i ~ r is called a mask. At
that point in VDP corresponding to the branch
point in HDP, a mask is generated such that b
i
is a one, if and only if the answer to the question for Ai is yes. Tl is now performed on all
r numbers USing the mask, which represents r
gates (k of which are open). Consequently, only
results of Tl on numbers in C are written in
1
memory. The mask is then complemented, resulting in a mask of.r gates (r - k of which are
open) • This mask is used similarly in the T2
computation on all r numbers, so that only results
of T2 on numbers- in C are written. Figure 2
2
shows the sequence of VDP operations.

113
3.1

'Compare 2:.' Used to Compute Rank

'Compare' Description and Algorithm
A set of instructions called 'compare' plays
a significant role in VDP on various levels. A
description of 'compare >' and its algorithm is
now given.
We are given r + 1
sequence (Ai)l ~ i ~ r,
again suppose that each
Qf bit length n. Let C
in binary form.

Let C

numbers consisting of a
and a cons:tant C. We
number is non-negative and
and the (Ai) be represented

= Cl C2 ··.C n'

and Ai

= ai,l

ai,2 ••• ai,n(1 ~ i ~ r). Let C' =
where Ct is the least significant
'Compare >' is to generate r bits

Cl C2 •••.ct (t'Sn),
zero bit of C.
(b ), such that
i
b i is a one, if and only if Ai > C. To compute
the r bits, we give the algorithm to compute the
th
i
bit. Let b =
i
ai,l *1 {a1 ,2 *2 [ ••• (ai,t_l *t-l ai,t)···]}'
using C' as follows. If the j th bit of C' is a
zero (1 S; j ::. t-l), *. is interpreted as inclu..Jl
-sive or; if it is a one, *j is interpreted as and.
Since the data is address;d orthogonally, it is
clear that all b (l ~ i ~ r) can be generated
i
simultaneously, provided that r is not too large.
The .number of memory accesses needed to execute
'compare >' in a VDP machine is t + 1 (t is the
bit length of C').
'Compare>' Used as Mask Generator
The following example shows how 'compare >'
is used efficiently in generating masks to be used
as decision functions. Suppose that we are computing the FICA deductions in a payroll program.
For each payroll period, 3% of total income is
deducted and accumulated for FICA until the accumulated total is equal to $144. Let r accumulated totals and $143.99 play the respective
roles of the (Ai)l ~ i ~ rand C in the 'compare>'
algorithm above. A sequence of r bits is generath
ted such that the i
bit is a one if and only if
th
the i
accumulated total is greater than $143.99.
This sequence of bits is complemented and then
used as the mask in the incrementing computation.
Consequently, only those totals that are less
than $144 are incremented. $143.99 is represented by 14 bits, the least significant six of which
are ones. Therefore t = 8 for this 'compare >'
and we need 9 memory accesses in order to execute
the instruction. For this problem, each time
'compare >' is performed in VDP, r comparisons
would be necessary in HDP. About 6 memory accesses are generally needed to perform a comparison.
For this function, the Orthogonal Computer is
approximately 660 times as fast as HDP for
r

= R = 1000.

Another interesting use for 'compare' is
given by the following example. We are given a
sequence of r numbers (Ai)l ~ i ~ r, nonnegative and of bit length n. We want to find
the number (k) of numbers in (Ai) that are less
than a particular number Aj in the sequence.
This number k is frequently referred to as the
rank of Aj in the sequence (Ai). To obtain the
rank of A ., we let the (A.) and A. play the resJ
1
J
pective roles of the (Ai) and C in the 'compare >'
algorithm, with an exception. Let a a ••• a be
n
l 2
the binary representation of A.. Let A! =
<
J
J
a l a ••• a t (t - n), where at is the least Sig2
nificant one2 bit of A.. This change results in
J

a 'compare:?' rather than 'compare > ' . The
generated r bits are then complemented obtaining
r bits such that the ith bit is a one, if and
only if Ai < Aj • These r bits therefore consist
of exactly k one bits and r, - k zero bits. The
execution time for an instruction giving the
count of the number of one bits in a given register should be equivalent to about two memory
accesses. Consequently, the time to compute rank
in the hypothetical machine should be approximately
equivalent to t + 3 memory accesses. In HDP, if
the (Ai) are not sorted, r - i comparisons are
necessary to compute rank. Assuming that r = R =
1000, the Orthogonal Computer ranges from more
than 115 (t = 48) to about 635 (t = 5) times as,
fast as HDP in computing rank in an unsorted
sequence.
VDP Applied to Compilers
Every compiler has within it an assembly
process. Let us suppose that a given machine has
N operation (op) codes. Let R mnemonic instructions be in one of the K blocks of the Orthogonal
Computer. The assembler must translate the instruction list from the menemonic to machine language. The result should be R machine language
instructions in another of the K blocks. Let
O. (1 ~ j ~ N) be the binary representation of
J

the jth mnemonic op code.

For each j, we perform

'compare =', comparing OJ against all R op codes.
The j th 'compare =' generates a mask (b.) 1 ~ i ~ R ,
1

such that b is a one, if and only if the op code
i
of the i th mnemonic instruction is equal to 0 .•
J

Using the machine language representation of OJ
as a constant, we perform 'constant

ins~rt'

2In the 'compare >' algorithm, Ct of C' is the
least significant ~ bit of C.

114
3.1
all R op codes using the mask. The' constant
insert' instruction duplicates a constant, R
times in a given block. Consequently, because
of the masFo, only those op codes that are equal
to O. are translated to the machine language
J
representation of 0.. After N 'compare ::;:' and
J
N 'constant insert' are performed, each of the
R mnemonic op codes will have been translated into
its corresponding machine language repr~sentation.

Orthogonal Computer. If K were as small as 3
(with a reasopable R), there would be few problems
for which the machine would ~ be severe1y I/O
limited. Flexibility with which ~o combat the I/O
problem increases with increasing K, for fixed R;
so does the cost of the machine. As R increases,
VDP computing time remains constant, but 'I/O time
per block and the cost of the machine increases.
These are some of the considerations involved in
choosing R and K.

If the mnemonic op code consists of three
6-bit characters, and the corresponding machine
language representation requires twelve bits (for
example, the 7090), then the number of memory
accesses required in VDP for the op code translation is 32N. In HDP, a search j s performed in
a table of N op codes, with an approximate average
of log2N comparisons for each op code. Approxi-

Acknowledgements

mately 8(10g2N) +15 memory accesses are needed to
find and translate each op code. For N = 60, and
R = .1000, the Orthogonal Computer is about 32
times as fast as HDP.
storage Econornoc by Packing Data
We" order the K blocks of the Orthogonal Computer, and also the L columns in each block from
most to least significant bit. We now linearly
order all KL addressable columns by demanding that
the last column in any block (excepting the last
block) directly precede the first column of the
next block. We can now think of these KL columns
as a matrix of R rows and KL columns. Suppose
that we have t sequences of data to process
(Ar) (1 $ i ~ R; 1 S j ~ t). For each j, let nj
be the bit length of the data in (Ar)'
t

j=l

Let N

It is clear that no generality is lost

in VDP, if the t sequences are packed into any
consecutive N of the KL columns, provided that N
is not too large.

This paper is the outgrowth of an idea originally conceived by GeEald Fine of the System Development Corporation. To rrry knowledge, Mr. Fine was
the first to foresee the possibilities of organizing data vertically. He initiated the VDP project
at SDC a little over a year ago. Thomas N. Hibbard,
who was a member of the project interested me in
VDP. Mr. Hibbard also did some of the early development work. It is a pleasure to acknowledge rrry
indebtedness to these two individuals.
The author also wishes to thank the members
of the Staff of the Center for Research in System
Sciences at SDC for their general assistance; in
particular, J. N. A. Hawkins who consulted on the
cost and engineering aspects of the Orthogonal
Computer, and Richard Brouse, Donald P. Estavan,
and Seymour Ginsburg for their constructive criticism.
Appendix
The Orthogonal Computer Instruction
A typical instruction consists of an op code,
three addresses (Ai)' and three parameters (Pi)'
Pi specifies the bit length of the corresponding
operand at Ai' Each Ai refers to one of the KL
addressable columns, to one of several vertical
flip-flop registers, or to a specified horizontal
register of flip-flops, say, the HDP accumulator4.
Some of the instructions do not use all the fields.
Instruction List

Cost of Orthogonal Computer

Timing5

Arithmetic
Preliminary investigation has begun in estimating the cost of the additional capabilities of
the Orthogonal Computer. The results are now
presented.
1
A memory consisting of 2 5 core locations,
each of bit length 48, was arbitrarily assigned
to the HDP computer whicp was used as a base for
the Orthogonal Computer. The estimate is that an
additional 35% to 45% of the cost of the HDP computer would be incurred for R = 512 and K = 16.
I/O LimitationSS
Computing is so fast using VDP, that input/
output limitations may be an acute problem for the

Add
Add magnitude
Substract
Substract magnitude

SA computer is said to be I/O limited, if a significant portion of machine time is spent waiting (i.e., not computing), while input/output is
being performed.
4

The HDP accumulator holds the constant used in the
'compare' instructions; it also permits adding,
substracting, mUltiplying, and dividing the numbers of a block by a constant.
5The approximate number of memory accesses exclusive of those necessary to fetch the instruction.

115
3.1

Instruction List (continued)

VDP

Multiply
Multiply magnitude
Multiply and accumulate
Divide
Divide magnitude
Compare

Compare greater than
Compare equal
Compare equal to or greater
than

The larger of
P and P
2
l

GENERATE
MASK FOR YES

PERFORM Tl
USING MASK

Move column
Constant insert
Logical
And
Inclusive or
Exclusive or
One's complement
Count ones

2
2

COMPLEMENT
MASK

2
2
1

PERFORM T2
USING NEW MASK
FIGURE 2

HDP

CQUESTION
YES
1,

COMPUTATION
Tl

COMPUTATION
T2

FIGURE 1

117
3.2

TABSOL
A FUNDAMENTAL CONCEPT FOR SYSTEMS-ORIENTED LANGUAGES
T. F. Kavanagh
Manufacturing Service s
General Electric Company
New York, New York

Summary
Lack of efficient methods for thinking
-through and recording the logic of complex information systems has been a major obstacle
to the effective use of computers in manufacturing businesses. To supply this need, this
paper introduces and describes "decision
structure tables, " the essential element in
T ABSOL, a tabular systems -oriente.d language
developed in the General Electric Company.
Decision structure tables can be used to describe complicated, multi-variable, mu1tiresult decision systems. Various approaches
to the automatic computer soiution of structure
tables are presented. Some benefits which
have been observed in applying this language
concept are also discussed. Decision structure tables appear broadly applicable in information systems design~
In addition, they are of intere st because they revise many earlier notions on
problem formulation and systems analysis
technique. Decision structure tables will be
an available feature in GECOM, General
Electric's new General Compiler, which will
be first implemented on the GE 225.

Introduction
Progress in computers can be broadly divided into two categories. First there is
the work that essentially accepts computers
for what they are, and directs its energies toward further refinement of the original hardware, and operating technique. Research to
improve recording density on magnetic tape
would certainly fit this description. In the
second category are the efforts to advance by
developing new areas of application. This latter work is directed toward generalizing the
concepts and hardware, so that they apply to
an ever -increasing span of problems and situations. Obviously, both groups are vital; but
it was this second stimulus -- the desire to

expand the area of economic application -which motivated the research reported in this
paper. While the earliest beginnings can be
traced as far back as June, 1955, the primary
research effort started in November, 1957,
under the title of the Integrated Systems Project. Leadership was assigned to Production
Control Service, a component in General Electric's Manufacturing Services. The basic purpose of the Project was to probe the potential
for automating the flow of information and
material in an integrated business system.
Then, as now, computers were making
significant contributions in many areas. Unfortunately, one of these areas was not, as some
would have it, in the operation and control of
manufacturing businesses. Important advances
were made in specific applications such as order processing payroll, and inventory recordkeeping; but these represented only a smeU1 percentage of the total information processing and
decision-making in even the smallest manufacturing firm. Still these early successes were
very important. They developed confidence in
computer performance and reliability; but even
more, they encouraged systems engineers and
procedures perf!lonne1 to continue computer applications research. Similarly, management,
under growing foreign and domestic competition,
rising costs, and a seeming explosion in paperwork requirements, saw intuitively -- or perhaps
hopefully -- that computers offered a possible
approach to improved productivity, lower costs
and sharply reduced cycle times. It was in this
environment that the Integrated Systems Project
began a compreh.ensive study of the decisionmaking and the information and material processing required to transform customer orders
into finished products - - a major part of the
total business system for a manufacturing firm.
The Decision-Making Pr.ob1em
Once underway, it was soon apparent

118

3.2
that there was an enormous aInount of decisionmaking required to operate a business. Indeed,
the number and complexity of these decisions is
perhaps the most widely underestimated and Illisunderstood characteristic of industrial information systems today. Tens-of-thousands of elementary decisions are made in the typical manufacturing business each working day. All are
necessary to guide and control the many functional activities required to design products, purchase raw material, manufacture parts, assemble products, ship and bill orders, and so on.
The typical factory is a veritable beehive of decisions and decision-makers; for eXaInple:
"What size fuses shall we use on
this order for XY Z Company?" -a product engineer's decision.
"What is the time standard for
winding this armature coil? "a manufacturing engineer's
decision.
"What test voltages shall be
applied? 11 - - a quality control
planner's decision.
"What should be the delivery
promise on this customer IS
order? II - - a production control
planner I s decision.
"How much will this model cost. "_an accountant's decision.
This list of elementary day-to-day
decisions could be expanded to cover all business activities. If this were done, the list
would cover hundreds of sheets of paper before
each activity listed all the decisions for which
it was responsible. Moreover, some of these
decisions are repeated Inany tiInes each day for
various sets of conditions. In the end result,
one cannot help but be iInpressed with the multiplicity of these detailed choices and selections.
But more importantly, making these decisions
costs money, in many cases more money than
the direct labor required to make the product.
In addition, business performance is greatly
affected by the speed and accuracy with which
this decision-making is carried out.
Composing a detailed list of these
elementary business decisions is more than an
academic exercise. For one thing, such an
analysis of an actual operating business will
demonstrate conclusively that these elementary
decisions are handled quite rationally (which is
somewhat contrary to popular opinion.) One

must be careful not to be wsled by quick, superficial explanations which gloss over fundaInental
reasoning. In our present-day manual systems
which emphasize files of quick answers, the
logic behind the decision is often left unrecorded. As a result it is easy to lose contact with
their rational nature, and frequently we tend to
feel these decisions are substantially more intuitive than is actually the case. At times, some
persistent as well as penetrating analysis (often
through extensive interviewing of the operating
personnel presently on pte job) is required to
uncover the true paraIneters and relationships
on which operating decisions are really based.
This arduous work is more than justified, for it
e$'tablishes a sound conceptual foundation for
automation, and hence the practical application
of the concepts and techniques developed in this
paper. Thus, once it is established that these
operating decisions are rational, it should follow
that they can be structured in a consistent logical fraInework. Such a structure is presented
in this paper.
Operating vs. Planning Decisions
At this point let us define terIllinology
a little more precisely, and stress that we are
speaking about the detailed, elementary decisions
required to "operate" a business as opposed to
"planning" one. First, a decision in its simplest form consists of selecting o}1.e unique alternative froIn an allowed set of possible actions.
Operating decisions are defined in the context
of this paper as selecting the appropriate CO\lrse
of action in accordance with given problem conditions to operate the business successfully.
Operating decisions may be assumed to be made
under "conditions of certainty. II The solution
for a specific set of problem conditions will always be the same. Under these preIllises, the
action or outcome decided on can always be predicted. In a pragmatic sense, the decision-making process may be classed as "causal"; that is,
B may be said to follow from A. For eXaInple,
an engineerls decision to install fuses might
follow from a customer's requirement for independent circuit protection.
The relevant factors or parameters
affecting the decision can also be determined.
The relationship values are known. For example, in most homes, the current carrying
capacity of the house wiring is the only parameter value one needs to know to select an
appropria.te fuse. In an industrial application,
however, the values of at least three additional
parameter s a.re usualLy required: voltage, time
and type of fuse mounting. The strategy and the
alternate outcomes are known; that is, the per-

119
3.2
missible fuses are known. To continue the illustration' the fuse selection may be li:mited to
tho se carried in the stockroom; otherwise the
bounds of the operating decision system are exceeded and the decision-maker would appeal to
a higher authority.
To approach the analysis of operating
decisions from another viewpoint, it might be
compared to a linear progra:m:ming problem,
and as will become evident, a linear program.:ming solution might be considered as somewhat
of a mathematical bound for the class of decision-making systems under discussion.
These operating decisions are quite
apart from the planning decisions of a business.
The "planning", "ad:ministrative" , or "policy"
decisions in a business are basically those
prior commitments which per:mitted all the assumptions about operating decision systems in
the preceding paragraphs (1. e. certainty, causality, known relationships, etc.) Some exa:mples of planning decisions are:
"Shall fuses, circuit breakers, or
both be used on the product line?" - a product engineer's planning
decision.
"Should this group of parts be
made on the screw machine or
from die casting s ? 'I - - a manufacturing engineer I s planning
decision.
"Should this component be inspected
before or after the milling operation? "- - a quality control planning
decision.
"What rule shall be used to determine the correct order quantity?" - a production control planner IS
decision.
"What is an appropriate cost -ofmoney? "- - an accountant's planning decision.
The se are typical planning decisions
made in designing an operating decision system.
To make the distinction clear, consider the design engineer who is motivated by cost considerations to put fuses on the economy part of the
product line, while specifying circuit breakers
on more deluxe models. Or consider the production control planner who selects one of the
co:m:mon square root formulas for deter:mining
a11 order quantities. Once he puts this decision

rule in the operating system, order quantities
for every part will be deter:mined using this
square root formula with specific value s for
cost, lead ti:me, usage shelf life, etc., appropriate to the specific item being ordered.
Assu:ming the operating decision system is automatic, and this is the intention, the production
control planner need not make any order quantity deter:minations himself. Rather he will be
watching the measures of operating system performance (inventory level, number of shortages,
ordering costs, etc.) to see how well his decision rule is working. Incidentally, it1s worth
noting that the production control systems designer will be using a "cost-of-money" figure
supplied by accountants and an annual requirements figure projected by salesmen. Of course,
the objective of this fundam.ental decision analysis is to suggest a conceptual scheme which will
per:mit automating all the routine operating decision-ma.kir1.g required to direct a business,
thus permitting the engineers, planners, and
other technical advisors, to concentrate on doing a better job in design.
Specifying Decision Systems
But great difficulties still remain. As
already pointed out, operating decision systems
are invariably large and complex, containing
multi-variable, multi-result decision problems
with sequence of solution difficulties thrown in
on the side. One serious problem. which arises
qu.ickly is the actual developm.ent of the decision
logic itself. Num.erous techniques have been
proposed ranging from. precise, legalistic verbal statem.ents to com.plex m.athem.atical equations. Among the se however, it appear s that
m.atrix-type displays and flow charts are the
most common. The matrix-type displays
appear under a variety of nam.es: collation
charts, tabulated drawings,. standard time data
sheets, etc. For exam.ple, engineers have frequently used collation charts to show direct relationships between end-product catalog numbers
and component identification numbers. Typically, however, co11ation charts are a tabulation
of past decisions rather than a description of
the logic used to derive them.. Matrix-type displays often suffer from. redundancy and frequently become large and unwieldy as operating tools.
Similarly, they m.ake no allowance to sequential
decision-m.aking.
Flow charts handle this sequence problem. very nicely. This graphic m.ethod describes
a decision system. by the extensive use of sym.boIs for "m.apping" the various operations. A
variety of flow chart techniques are used in
factory methods and office procedures work.

120
3.2
They are particularly effective in relatively
straightforward, sequential decision chains but
run into difficulty when describing multi-variable, multi-result decision processes. As an
illustration, ·£low charts have been used extensively to docum.ent the detailed logic of computer programs; but some harried computer programming supervisor s still maintain that the
best way to transfer program knowledge is to
reprogram the job. The difficulty of interpreting someone else's flow charts is certainly one
of the major trials in today's computer technology.

In addition to these more popular tools
numerous other diagramm.ing or charting techniques have been useful in limited problem areas.
However, the basic problem remained: there
was really no effective, uniform method for
thinking about and specifying decision systems
as complex as those required to operate a business •. To help solve this problem, the Integrated Systems Project developed a new technique
which combines key characteristics of earlier
methods and adds some new features of its own.
This new technique is called the decision structure table. The balance of this paper will describe what decision structure tables are, how
they work, and the results of their use in
General Electric.
Structure Table Fundamentals
Structure tables provide a standard
method for unambiguously describing complex,
multi-variable, multi-result decision systems.
Thus, each structure table becomes a precise
statement of both the logical and quantitative
relationships supporting that particular elementary decision. It is written by the functional
specialist in terms of the criteria or parameters
affecting the decision and the various outcomes
which may result.
A structure table consists of a rectangular array of terms, or blocks, which is further
subdivided into four quadrants, as shown in
Figure 1. The vertical double line separates the
decision logic on the left from the result functions
or actions which appear on the right. The horizontal double line separates the structure table
column headings or parameters above from the
table values recorded in the horizontal rows below. Thus, the upper left quadrant becomes
decision logic column headings, and is used to
record, on a one per column basis, the names
of the parameters (P Oj ) effecting the decisions.
The lower left quadrant records test values (Pij)
on a one per row basis, which the decision para-

meter identified in the column heading may have
in a given problem situation. The upper right
hand quadrant records the names' of result functions or actions to be performed (R. Oj ) as a result of making the decision, once agiln on a one
per column basis. Similarly the lower right
quadrant shows the specific result values (rij)
which pertain, directly opposite the approprfate
set of decision parameter values. Thus, one
horizontal row completely and independently
describes all the values for one decision situation.
There is, of course, no limit to the
number of columns (decision parameters and
result functions) in any given structure table.
Even the degenerate case where the number of
de'cision parameters goes to zero is permissible. Also there is no limit on the number of
decision situations (rows). Thus, the dimensions (columns by rows) of any specific structure table are completely flexible, and are a
natural outgrowth of the specific decision being
described. A series of these structure tables
taken in combination is said to describe a decision system.
Rather than become further involved in
abstract notation, let's consider some actual
illustrations to develop an insight into the nature
of structure tables. For example, the oversimplified illustrative structure table in Figure
Z. states that an elementary decision on transportation from New York to Boston in the afternoon
is (according to the person'who developed the
decision logic) a function of three decision parameters: Weather, Plane Space, and Hotel Room.
Weather has only two value states, Fair or Foul;
Place Space is either OK or Sorry; and Hote-l-Room can be Open or Filled. In terms of resuIts, ~ or Traina;e-the only permissible
means of Transportation. Following the illustrative problem, we see by inspection that the
solution appear s in the second row. Therefore,
'Train is the correct value for Transportation,
Other Instructions are Cancel Plane, and this
is the End of the decision problem.
The intent of this simple structure
table is to provide a general solution to this
particular decision situation, and if the problem
of afternoon trips to Boston ever arises (and one
assumes that it frequently does), then an operating decision can quickly be made by supplying
the current value of Weather, Plane Space, and
Hotel Room, and, of cour se, solYing the structure table. Solving a structure table consists
of examining the specific values assigned the
decision parameters in the problem statement
and comparing or "testing" these values against

121
3.2
the sets of decision parameter values recorded
in the structure table rows. Testing proceeds
cohunn by column froIn the first decision paraIneter to the last (left to right) and thence row
by row (top to bottoIn). If all tests in a row are
satisfied, then the solution is said to be in that
row and the correct result values appear in the
same horizontal row directly opposite to the
right of the double line. When a test is not satisfied, the next condition row is examined.
When a particular structure table' has
been solved, it is often necessary to Inake Inore
decisions. To specify what decision is to be
Inade next. the last result colUInn of the structure table tnay be assigned as a director to provide a link. to the next structure table. Notice
the last row in the illustrative structure table
whlch specifies that-for any value of Weather,
with no Plane Space, and no Hotel ROOIn, the
decision-Inaker is directed to solve the next
structure table, Transportation, New York-Boston, a. In. - - which is another structure table
describing how to select a Ineans of transportation in the Inorning.
In a sitnilar fashion, the systeIns designer would use a whole systeIn of structure
tables to describe a Inore realistic operating
decision probleIn. He cOInpletely controls the
contents of each table, as well as its position in
the seque'nce of total probleIn solution. He Inay
decide to skip tables, or, if desired, he Inay resolve tables to achieve the effect of iteration.
In any event, the entire systeIn of tables, just
as each individual structure table, will be solved using specific decision parameter values appearing in the probleIn stateInent. In other
words, solving a set of structure tables consists
essentially in re-3.:pplying the systeIns designer's
operating decision logic.
Having cOInpleted this quick and very
siInpUfied introduction to structure tables, let
us now return to consider each structure table
eleInent in greater detail. This will provide a
deeper insight into the power of the structure
table technique, as well as a better understanding of how they are used to describe operating
decision systeIns. The illustrations are drawn
froIn actual operating decision probleIns.
Structure Table Tests
COInparisons· or tests between probleIn paraIneter values (pv) and decision paraIneter test values (tv) need not be siInple identities, such as those used in the previous illustration. Actually the prob1eIn parameter values
Inay be cOInpared to the decision test values in

anyone of the following ways in any structure
table block:
EQ

pv = tv

prob1eIn value is equal to
test value.

pv:> tv

probleIn value is greater
than te st value.

< tv

NEQ

GREQ

pv .) tv

problem value is greater
than or equal to test value.

LSEQ

problem value is less than
or equal to test value.

proble.IXl value is less
than test value.
probleIn value is not
equal to test value.

This broad selection of test types (or
relational operators as they are known technically) greatly increases the power of individual
structure tables and sharply reduces size. It
perIDits testing li.tnits or ranges of values -rather
than only discrete nUInbers. In Figure 3, TABLE
1000 uses several difference test types to bracket continuous and discontinuous intervals. Also
note in Figure 3, that the relational operator
may be placed in the test block immediately preceding the test value, or in the column heading
imm.ediately following the decision parameter
name. When this latter notation is used, the
relational operator in the column heading applies
to all test values appearing immediately below.
Test values are not li.tnited to spe<;i£ic
nUInbers on alphanumeric cOD;stants (indicated
by quotation tnarks); a test block may also refer
to the contents of any name. In this case of
cour se, the current contents of that named field
are compared to the problem parameter value
in accordance with the test type. For example,
TABLE 1005 in Figure 3 tests the current value
of INSUL~ TEMP against MAX- TEMP to Inake
certain that insulation temperature ratings are
satisfactory.
In addition to the se simple cOInparisons
it is also possible to formulate compound structure table blocks involving two decision parameters or test values using a relational or logical
operator.
The following logical operators tnay be
used:

first test value or the
second test value.

122
3.2
AND

pV AND pV

NOT

fir st problem value and
second problem value.

cates that the result value
appearing in (or named by)
the solution row is to be
assigned or placed in the
field named in the column
heading.

fir st test value and not
second test value.

Also the truth or falseness of a compound decision parameter or test value statement can be te sted with the symbols:

true

false

Lastly, any arithr.netic expression
may be used in place of a parameter name, and
complicated blocks involving several names and
operators are also permitted. Although in this
latter case, it is worth noting that the language
capability far surpasses any requirements experienced to date in formulating operating decision systems.
In writing structure tables, the situation often arises where, except for one or two
special situations, one course of action is adequate for all input values. The concept of an
"all other" row was introduced to avoid enumerating all possible logical combinations of the
decision parameter values. The "all other" concept can be verbalized as follows: "if no solution
has been found in the table th.us far, the solution
is in this last row regardless of the problem
values." While this greatly reduces table size,
it also implies that the problem was stated correctly and does indeed lie within the boundaries
of the decision system. The related concept of
"all" which appears in the Transportation: New
York-Boston, p. m. can be similarly verbalized:
Ilregardiess of the problem value proceed to the
next column." It was introduced so that a given
table need not contain all permissible states of
any given decision parameter and also to handle
the case where a test in a given column had no
significance. In all the above situations the appropriate structure table blocks are left blank
signifying no test.

IICALCULATE II -

which is implied by the use
of an equal sign after a name
appearing as a result value.
This indicates that the results
of the formula evaluation named in the structure table block
should be assigned to the field
named as the re sult function
in the column heading.
Actually this is not the only
way to perform calculations
as any arithmetic expression
may be used as a result value.

PERFORM -

which performs the data processing or arithmetic operations referred to in the label
appearing in the result value
block. When this is completed, the next result function
is executed.

GO -

links the structure table to
the label appearing in the
re sult value block. There
is no implied return in a
GO function.

Most of these result functions are illustrated in Figure 3 and Figure 4. In Figure 4,
for example, TABLE 2000 assigns the alphabetic
constant IIFLAT-STRIP" to ASSEMBLE. In the
first and third result columns, arithmetic expressions appear as result values. In TABLE 2005
the implied CALCULATE is used for formula
evaluation. TABLE 2005 also uses the PERFORM function to solve TABLE 2008 or carry
out some other data processing operations depending on the particular solution row. TABLE
2005 is linked by the GO operation to TABLE
2010, 2015, 2020.

Structure Table Results
Similarly structure table results are
not limited to assigning alphabetic constants or
numeric values to the result functions or actions
named in column heading s to the right of the
double line. Actually there are four result functions:
IIASSIGN" -

which is implied when a
named field appears as a
result function. This'indi-

TABLE 1005 in Figure 3 shows an
interesting use of the GO function. After the
winding has been specified in TABLE 1000,
assumedly on a lowest cost basis, the product
engineer evidently wants to check the insulation
temperature rating with the maximum expected
operating temperature. If the insulation temperature rating should turn out to be greater
everything is fine and the decision-maker proceeds to TABLE 1007. If not, first TYPE-N
and then TYPE-T insulation are specified to

123
3.2
supercede TYPE-F, thus getting progressively
higher insulation temperature rating s by redirecting the structure table to solve itself.
Frequently, a result function-or action
will not have a value for all rows. This is common when several result functions are determined by the same structure table. In this situation
the phrase "not exist" has been used in verbalizing and the structure table block is left blank.
The use of formulas as structure
table results can greatly reduce the size of the
table. As an illustration, suppose that a given
result function has twenty-six values (10, 12,
14 16, ... 60). Ostensibly, the structure table
to select the appropriate result value would have
twenty-six rows. This decision could be reduced
to one row by calculating the re sult value as
some function of the decision parameter as
shown in Figure 6. Obviously, all result relationships are not so conveniently proportional
but a surprising number of result functions can
be described with simple linear ~nd exponential
expressions. The curve fitting problem can be
greatly simplified by using structure table rows
to break the curve into convenient intervals that
can be represented by such simple mathematical
expressions.
Preambles and Postscripts
Each structure table is preceded by a
heading which identifies the table by number and
indicate s its dimensions in terms of decision
parameter columns, result function or action
columns, and value rows. Tables may be numbered from TABLE I to TABLE 9999999 and
allowance is made for up to 999 decision parameter or result functions. Provision is also
made for 999 condition rows.
Following the heading is a NOTE which
may contain any combination of alphabetic or
numeric characters. The NOTE may be used to
give the structure table an English name and
provide a verbal description of the decision being made. Subsequent to this any labels naming
expressions or arithmetic calculations referred
to by "CALCULATE" or PERFORM operators in
the body of the structure table may be defined.
For example, note the definition of TIME , v 1 and
TIME I\" 2 in TABLE 2005 of Figure 4. The structure table proper follows BEGIN.
If no solution row is found in the structure table proper, or if the structure table has
executed all results or taken all actions without
reaching a GO function then control is passed
to the area directly below the structure table.

Here are recorded any special instructions pertaining to that particular decision. Of particular
note is the situation where no solution row has
been found. Such a failure is regarded as an
"error." In certain types of decision systems,
this may be exactly what the systems designer
intended. However, error conditions most often
indicate a failure of the decision logic to c;ope
with a certain combination of input values. The
systems designer should set up to notify himself
whenever such an error occurs by designing an
error routine which will provide him with a
source language printout identifying the table
that failed and the problem being solved at the
time. With this problem printout and the source
language structure tables, the systems designer
has all the data he needs to trouble shoot the
system in his own terminology. Thus, each
structure table should be followed by the statement: IF NOT SOLVED GO
~--~~-------~~
In this way any structure table
failures will always be uncovered. Frequently, the situation
arises, as mentioned earlier, that regardless of
the solution row, the next structure table solved
is the same. In this case the statement:
GO
. may be written after or
below the preceding error statement, to serve
as a wUversallink to the next structure table.
The areas immediately preceding and
suc ceeding the structure table proper may also
be used for input-output, data movement, and
other data processing operations.
The Dictionary
The precise name and definition of
each decision parameter and result function are
recorded in a "dictionary. II This dictionary becomes an important planning document in the
systems engineerls work for it provides the
basic vocabulary for communicating throughout
the entire decision system. The dictionary
should note a parameterls minimum and maximum values, as well as describe how it behaves.
If the parameter is non -numeric in nature, the
dictionary should record and define its permissible states. Significantly, the systems engineer formulates both the structure table and the
dictionary using his own professional terminology.
The dictionary will also prove useful
in compiling and editing structure tables for
computer solution. It also follows that problems
presented to the resulting operating decision
system must also be stated in precisely the
same terms as the structure tables. To those
as yet uninitiated to the perversity of computers,
this may seem a simple matter; unfortunately,

124
3.2
it is not. Interestingly however, one of the
more promising application areas for structure
tables appears to be in stating the logic for compilers and edit programs.
Summary
The foregoing description of decision
structure tables is not meant to be a fully definitive language specification. The intention is to
introduce the reader to the decision structure
table concept and to discuss their characteristic s in sufficient detail to provide the reader with
enough understanding to evaluate their inherent
flexibility and application potential. Many additional features are available which aid in formulating concise, complete decision structure
table systems and also to facilitate input-output
operations, but the reader will find that the
fundamentals already described are adequate
for structuring most operating decision logic.

Automatic Solution of Structure
Table Systems
Decision structure tables have proven
to be an excellent method for analyzing or formulating the logic of complex industrial information
systems, but after taking such great care to precisely record each elementary decision in this
highly structured format, it is only natural to
speculate on the possibility of solving structure
tables automatically with an electronic computer.
Before plunging into the computer world, however, it is worth noting that some systems engineers have had very favorable experience using structure tables on a manual basis -- especially as a problem analysis technique, and also
in limited applications in manual clerical systems.
Numerous methods for solving structure tables automatically suggest themselves.
First, the tables could be coded by hand. Such
an approach would use structure table s as a direct substitute for flow charts. Actually this
really isn't as bad as it initially sounds. Many
benefits would accrue from making this precise
readable format the standard method for stating
decision logic. It also offers the possibility that
a series of macro -instructions could be developed, thereby permitting untrained personnel to
code tables without detailed knowledge of computers or programming. However, this approach
suffers some distinct disadvantages in comparison with the other alternatives outlined below.
Second, a generalized interpretive
program could be written to solve any structure

table. This offers the possibility of using a
translator to work directly from keypunched
structure tables without any manual detail coding. This approach makes economical use of
memory since the basic programming to solve
any table appears only once and the structure
table itself offers a compact statement of decision logic. This reduces the amount of reading
time required to bring the problem logic into the
computer. File maintenance via recompiling
structure table tapes also appears quick and
simple. However, interpretive programs usually run more slOWly; and this implies some
penalty in total machine running time.
A third approach would be to create a
structure table program generator in which an
object computer program would be generated
from the source structure tables. This approach
would provide faster computer running time s
for :maxi:mu:m efficiency. A generator progra:m
would probably require :more co:mplicated coding
than an interpretive translator. In addition, the
generated object program would not be as concise as the structure tables themselves. However, where co:mputer running tiIne is of paramount concern, this approach has considerable
appeal.
Because of the available ti:me and
:money, all the early efforts of the Integrated
Systems Project toward auto:matic structure
table solution were essentially interpretive. It
is interesting that a si:mple, yet adequate, tabular systems-oriented language could be provided in this way for so:mewhat less than a man
year's effort. Si:milarly work to date in the
area of formula calculations indicates that a
comprehensive syste:m of mathematical notation
like that required for scientific work is probably
not necessary in :many operating business decision systems. Initial efforts on the IBM 702.
were followed with experimental TABSOL languages for the IBM 305, IBM 650 and the IBM 704.
The se applications to different computer s represented more than simple extrapolations to different pieces of hardware. In each an effort was
:made to expand capabilities of the language. In
addition, the peculiarities of the equipment were
explored, since one great concern was to free
the user fro:m a programming syste:m usable on
one and only one computer. As you :might suspect' this wasn't always completely possible on
the smaller computers, lacking tape or core
:memories. Nevertheless, the most recent
Manufacturing Service effort on the IBM 650
produced a language with named fields, indexing, a two-address arithmetic, co:mpletely
generalized structure table for:mats, and considering the alphabetic restrictions of the

125
3.2
equipment, remarkably flexible output formats.
Although "these experimental languages
proved quite adequate, one could not help but
look toward the tremendous power of one of the
more conventional languages. For one thing.
the prospects for structure table application in
other problem areas brightened. and it seemed
reasonable that this power would be desirable in
future work. Further our own tabular systems
language development had brought us to the point
of direct competition with the major language
efforts already underway. Here General Electric's Computer Department entered on the
scene. The Computer Department was developing a new concept in compiler building for use
with General Electric computers. The first
version of this new General Compiler, called
GECOM, will be available to GE 225 users in
May, 1961. It is designed primarily around
COBOL, with some of the basic elements of
ALGOL. and is now to contain all of TABSOL.
To state the results of joining TABSOL with
GECOM simply, it places the power of a fullfledged language at the command of every structure table block. Within General Electric, we
obviously have a very high regard for the contribution of decision structure tables in information
systems design. Significantly, the same committees who developed COBOL are now actively
investigating tabular systems-oriented languages
as the language of the future. By drawing on the
CODASYL work and utilizing the extensive research and development experience already
available within General Electric, the Computer
Department expects that GECOM will provide
users with a system compatible with both the
present-day common business language, COBOL.
and also the tabular systems-oriented language,
TABSOL. Incidentally, the decision structure
tables appearing in Figures 3, 4 and 5 are written in conformance with GECOM specifications.

Applications of Structure Tables
As somewhat implied in the illustrations a substantial amount of experience has
been gained in applying structure tables to a
wide variety of operating decision-making problems over the past three years. But perhaps the
most interesting experience, at least from the
researcher's point of view, was the very research work which spawned decision structure
tables themselves. Earlier, it was mentioned
that the Integrated Systems Project undertook a
careful study of the essential information and
material processing required to directly transform customer order s into finished products.
For example, the product must be engineered

prior to shipment, but the payroll, though revered by all of us can well be done at some qther
time, out of the main flow of events. Using this
rough rule of thumb, the following activities
were studied (Figure 7): order editing, product
engineering, drafting, manufacturing methods,
and time standards, quality control. co st accounting, and production control. These activities account for a fairly substantial portion of
the business system. Normally, they would include 100% of the direct labor and 100% of the
direct material as well as about 50% of the overhead. All the production inventory investment
lies within the scope of this system and obvious1y most of the plant and equipment investment.
Fortunately, the inputs and outputs to this system are simple and well-defined: the customer
order comes in and the finished product goes out.
With this in mind, it was possible to treat all
activities within these bounds as one integrated,
goal-oriented operating decision system and
develop decision structure tables accordingly.
Working with a small product section in one of
the Company's Operating Components, a significant portion of the functional decision logic was
successfully structured. Further the resulting
structure tables were directly incorporated into
a computer-automated operating decision system
which transformed customer orders for a wide
variety of finished products directly into factory
operator instructions and punched paper tape to
instruct a numerically programmed machine
tool. This prototype system was demonstrated
to General Electric management in November.
1958. Starting at the beginning, (Figure 8) the
computer system edited the customer order and
using the product engineer's design strU'cture
tables, developed the product's component char-acteristics and dimensional details. These in
turn were used in the manufacturing engineer's
operation structure tables to develop manufacturing methods and determine time standards.
And so the flow of information cascaded down
through the various business functions computing the quality control procedures, the product
costs and the manufacturing schedules; eventually issuing shop paperwork and machine program tapes.
Since the completion of this work
further research and development of the structure table concept was conducted in a variety of
functional areas for different kinds of businesses
in General Electric: defense, industrial apparatus, and consumer-type products. In addition.
structure tables have been used in entirely different applications such as compilers. They
also appear to hold great promise in complex
computer simulation prog rams.

126
3.2
specialists and systems engineers.
Structure tables also go a long way
toward solving the difficult systems
documentation pro blelll.

Benefits of Structure Tables
As a result of these efforts, we have
COllle to believe that the decision structure table
is a fundalllental language concept which is
broadly applicable to lllany classes of information processing and decision-lllaking problellls.
They offer many benefits in learning, analyzing,
£orlllulating and recording the decision logic:

Structure tables force a logical,
step-by-step analysis of the decision.
First the parallleters affecting the
decision lllUSt be specified; then suitable results lllUSt be formulated. The
nature of the structure table array is
such that it forces consideration of
all logical alternatives, even though
all need not appear in the final table.
Similarly, the precise structure table
forlllat highlights illogical statements.
This simplifie s manual checking of
decision logic. The decision logic
emphasizes causal relationships and
constantly directs attention to the
reasons why results are different.
Personal design preferences can be
resolved and intelligent standardization can be fostered.
This is no lllean capability. Indeed,
it was very instructive to witness the
developlllent of methods and tillle
standards logic in parallel with the
development of the engineering logic
during the initial Integrated Systellls
Project study. Through analysis of
the decision structure tables written
by the various functional specialists,
everyone was able to achieve an insight into the product and the business
rarely obtained in so short a period
of tiIne. The facts of life in product
design, factory methods, and standardization were brought into the open
very rapidly.

Structure tables are ea$i1y understood
by hUlllans regardless of their functional background. This does not
iInply that anyone can design or create
new structure tables to describe a
particular decision-making activity;
but it does mean that the average
person, with the aid of a dictionary,
can readily understand someone
else's structure tables. Thus, structure tables form an excellent basis for
communication between functional

Structure table format is So simple
and straightforward that engineers,
planners, and other functional specialists can write structure tables
for their own decision-making problems with very little training and
practically no knowledge of computers or progralllm.ing. Given a few
ground rules, regarding formats and
dictionaries, the structure tables
written by these functional people
can be keypunched and used directly
in operating decision systems without ever being seen by a computer
programmer. This cuts computer
application costs as well as cycle
tiInes.

Structure table errors are reported
at the source language level, thus
permitting the £uD.ctional specialist
to debug without a knowledge of computer coding.

Structure tables solved automatically
in an electronic computer offer levels
of accuracy unequalled in manual
systellls. Note, however, that any
such mechanistic systellls lose that
tremendous ability of humans to
compensate for errors or discrepancies.

Structure tables are easy to maintain. Instead of changing all the
precalculated answers in all the
files, it is often only necessary to
change a single value in a single
table. For example, when changing
the material specified for a COlllpOnent part under current file reference systems, it would be necessary
to extract, modify and refile all
drawings and parts lists calling for
any variation of the component part.
U sing structure tables, it would only
be necessary to alter those structure
tables which specified the component
material.

SU1ll1llary

In closing, we recommend that the
reader demonstrate the effectiveness of decision

127
3.2
structure tables to himself by "structuring" a
few simple decisions. For example, write a
structure table which will enable your wife to
decide how to pack your suitcase of any business
trip. Perhaps a simple business decision such
as those mentioned earlier would provide a more
instructive example. The first structure tables
are usually difficult to write, because most of
us do not, as a general rule, probe deeply into
the logic supporting our decisions. However,
once this mental obstacle is overcome, "structuring" facility develops rapidly. If the reader
will take the time to "structure" a few decisions
and actually experience the deeper insight and
clarity which this technique provides, then decision structure tables need no apologist, they
will speak for themselves.

Acknowledgement
In contrast to most technical papers
which essentially document only the work of the
author, this discussion reports on the efforts of
over seventy-five General Electric men and
women. In particular, credit is due Mr. Burton
Grad, who though no longer with General Electric, was a principal originator of the decision
structure table concept. Mr. Malcolm C. Boggs,
Mr. Daniel F. Langenwalter, Mr. Herbert w.
Nidenberg, and Mr. Theodore E. Schultz representing Service Components and personnel from
some fifteen different Operating Components
within General Electric have contributed toward
bringing these ideas to their present state of
development and application. Acknowledgement
is also due Mr. Charles Katz of General Electric's Computer Department who was instrumental in joining T ABSOL and GECOM.

128
3.2

Decision
Structure Table

.•. a re ctangular
array of terms,
or blocks •..

. . • vertical
dou ble line ....

Results or
Functions

Decision
Logic

Column headings
... horizontal
double line •••
Table Values

.... structure
table
values •••

POI

POZ

Pll

P 12

PZl
P 31
P41

ROI

ROZ

R03

R04

P13

P2Z
P 32

PZ3
P33

P42

P43

r2l
r
31
r41

Figure 1

r22
r
32
r42

rZ3
r33

r24
r 34

r43

r44

129
3.2

Problem Statement:

Select Transportation, New York - Boston, p. m.
Weather: Foul
Plane Space: OK
Hotel Room: Open

Decision Structure Table:

Transportation, New York - Boston, p. m.

Weather

Plane
Space

Hotel
Room

Transportation

Fair

Open

Plane

Foul

Open

Train

Sorry

Open

Train

Filled

Sorry

Filled

Other InNext
structions Decision

End
Cancel
Plane

Solution:
If the value of Weather is Foul, and
the value of Plane Space is OK, 'and
the value of Hotel Room is Open,
Then
the value of Transportation is Train, and
the value of Other Instructions is Cancel Plane, and
the value of Next Decision is End.

Figure 2

End

NY -Bost.
a.m.
NY-Bost.
a. m.

•

r-Jo

TABLE 1000. DIMENSION C4 A5 RIO.
NOTE TABLE FOR DETERMINING DETAIL VARIABLE PART CHARACTERISTICS FOR A
LINE OF SENSING COILS IN ACCORDANCE WITH CUSTOMER END PRODUCT
SPECIFICA TIONS.
INSUL
BEGIN.
INSUL
UNITS EQ
VALUE
VALUE TURNS
RESIST
SERVICE E
GR 180
LS 450
2.6*TURNS "TYPE-F"
"MAMP"
"DC"
O. ~/I

"DC"
"DC"
"DC"
"DC"
.

"MVLT"
"MVLT"
"VOLT"
"VOLT"

"AC"

"WATT"

GREQ
GR
GREQ
GR

45
150
0.9
300

LSEQ 150
LSEQ 330
LSEQ 300
LSEQII00

26
13
60
120

.008
.002
.002
.. 002

1.84
0.46
39.0
137.0

"TYPE-F"
"TYPE-F"
"TYPE-F"
"TYPE-F"

150
150
150
150

230

• 002

150.0

"TYPE-N"

200

IF NOT SOLVED GO ERROR"'COIL.
MOVE "COPPER" TO MATERIAL.
GO TABLE 1005.
END TABLE 1000.
TABLE 1005. DIMENSION C2 A3 R3.
NOTE TABLE TO MAKE CERTAIN THAT INSULATION TEMPERATURE RATING EXCEEDS
MAXIMUM OPERATING TEMPERATURE.
BEGIN.
INSUL
MAX"" TEMP
INSUL
INSU·L"'-' TEMP
GO
LSEQ INSUL"-'TEMP
GR INSUlJvTEMP
"TYPE-F"
GR INSUL-vTEMP
I
"TYPE-N"
IF NOT SOLVED GO ERROR'VCOIL.
END TABLE 1005.

"TYPE-N"
"TYPE-T"

Figure 3

200
250

TABLE 1007
TABLE 1005
TABLE 1005

TABLE 2000. DIMENSION C3 A3 R4.
NOTE TABLE TO SPECIFY VARIABLE FACTORY OPERATION CHARACTERISTICS FOR THE
INITIAL SENSING COIL WINDING FROM PART CHARACTERISTICS.
BEGIN.
SUPPOR TN TYPE EQ

MATERIAL

EQI

TURNS

tlSTARTkW I

" TABED-HOLE"
"COPPER"
TURNS
LS 100
2
" FLAT-STRIP"
"COPPER"
GREQ
100
" FLAT-STRIP"
TURNS/2
"COPPER"
" FLAT-STRIP'I
"ALUMNM"
TURNS
IF NOT SOLVED GO ERROR"'-"COIL. GO TABLE 2005.
END TABLE 2000.

I FINISH..vW

ASSEMBLE

"FLAT-STRIP"
"FLAT-STRIP"
'12 FLT-STRP'I

TURNS-2
TURNS/2

TABLE 2005. DIMENSION C2 A3 R3.
NOTE TABLE TO CALCULATE TIME STANDARD FOR PREVIOUS OPERATION.
TIME~l = 125*DIA*TURNS.
TIME"'2 =' 1000*DIA/SQR T (TURNS).
BEGIN
__ ~_GO
TURNS
TURNS
PERFORM
nME
LS 15
TURNS + 0.88
TABLE 2010
SETUP
GREQ 15
LS 100
TABLE 2015
TIME~l =
SETUP
GREQ 100
TIME-v2 =
TABLE 2020
TABLE 2008
IF NOT SOLVED GO ERROR4ICOIL.
GO TABLE 2005.

Figure 4
wI-'

•

t--:) I-'

•
W
t-.Jt-.J

TABLE 1010. DIMENSION C2 Al R3.
NOTE COIL QUANTITY DETERMINATION.
BEGIN.
SERVICE EQ UNITS NEQ "WATTS" COII.rvQUAN
"AC"
"DC" OR flAC"
"DC"
IF NOT SOLVED GO
END TABLE 1010.

T
F
ERROR~COIL.

0
QUAN
2*QUAN
GO TABLE 1100.

TABLE 1500. DIMENSION C4 A3 RIO.
NOTE COIL LOAD DATA AND CYCLE TIMES.
BEGIN.
~ERVICE EQ
UNIT EQ
~CY EQ IINSP EQ
"AMPt)" UR "MAMPI'

"AC"

"WATT"

In C-O MLTT

'COML"

"DC"
2
"AMPS" OR "MAMP"
2
"DC"
"VOLT" OR "MVLT"
"DC"
"AMPS" OR "MAMP"
1
IF NOT SOLVED GO ERROR-vCOIL.
MIN..... DATE = TODAY + MIN..vCYCLE.
NORMNDATE = TODAY + NORM~CYCLE.
GO TABLE 1510.
END TABLE 1500.

"COML"
IIICOML"
"GOVT"

Figure 5

NORM-"'CYCLE IMIN4-CYCLEI COIL.-vLOAD
15
11
QUAN
15
11
2. 2*. QUAN
15
15
20

9
9

o. 9~c

QUAN
0.9* QUAN
1.4* QUAN

TABLE 1510. DIMENSION C2 A2 R3.
NOTE COIL PROMISE DATE DETERMINATION.
BEGIN.
COIL~LOAD

LSEQ
CUST DATE
CUM-vCAP (NORM.vDATE)1 GREQ NORM-1.IDATE
CUM.-vCAP (MIN"-'DATE)
GREQ MIN-vDATE
CUM""CAP (CUSTNDATE)
IF NOT SOLVED GO OVERLOAD.
END TABLE 1510.

Figure Sa

PRO:MISE
CUST"",DATE
CUST.iV DATE
CUST""DATE

GO
NORM""LOAD
RUSH....,LOAD
EMER~LOAD

W ......

•

[\.JW

134

3.2

1
2
3

·.
·.
·.

·
·
0

(2*p)

+ 10

o •

.0.

o
The use of form.ulas as structure table results can
greatly reduce structure table size, as shown by the si:mple
straight line expres sion above. Structure tables :may also be
used to partition cOIIlplicated curves into convenient seg:ments
as shown below.
0

- - - ---

II----i
!J

••

-- 1--=

-~ ~-- -- 1----~

1>3

Figure 6

m.x

+b
+c

135

3.2

PRESENT MAIN LINE SYSTEM

CUSTOMER ORDER

--------

REFERENCE

~.MO

EDIT

~ INFORMATION

____

~ PLANNING

J1%.

CARDS

PRODUCT COST
FILES

PLANNING
AND WAGE RATE

COST
~ DETERMINATION

~ ~INVENTORY

/~~

CARDS
W////////~

~ORDER
/"/'l FI LES

=~I'&', VENDOR
....

OPERATOR

MA:AL

Figure 7

~~~~&:~\~

MACHINES ~

136
3.2

INTEGRATED MAIN LINE SYSTEM

;z == ~

CUSTOMER ORDER

~------------~

ORDER TRANSLATION

TRANSLATION LOGIC

ORDER EDIT
PRODUCT DETAILS

PRODUCT DESIGN
STRUCTURE

METHODS AND
TIME STANDARDS

MANUFACTURING
OPERATION
STRUCTURE

QUALITY
PROCEDURES

QUALITY CONTROL
STRUCTURE

PRODUCT COSTS

COST STRUCTURE

I I

III

...

MAN, MACHINE AND
MATERIAL TIMING

MANUFACTURING
CONTROL STRUCTURE

VENDORS
SUPPLY
MATERIALS

MACHINES:
AUTOMATIC
OPERATOR RUN
• PARTS. SHIPMENT
• ASSEMBLIES • AUDIT

Figure 8

PROGRAM
~
TAPE
INSTRUCT .

137
3.3
THEORY OJ' !'ILES

Lionello Lombardi
University of California at Los Angeles

SUlJIDI8ry

The theor,r of files is a tool for the
logico-mathematical treatment of automatic nonnumerical data processing problems, such as
machine accounting, information retrieval and
mechanical translation of languages. The main
result which has been obtained sofar from the
application of the theory of files is the formulation of a Simple pattern to which the data
flow of any information processing procedure
conforms, regardless of how many files are involved. The flow of each file can be controlled
and coordinated with the flow of the other files
by means of five boolean parameters, called
'indicators' •
A specially designed Algebraic Business
Language exploits this result for the purpose
of programming digital data processing systems.
This paper also probes into the impact of the
theory of files upon the logical design of digital information processing systems.

velopment of suitable techniques, allowing the
adoption of reliable procedures and collapsing
the amount of work necessary for carrying
them out. We believe that this can be done,
and that the appropriate language for analy'ziDg
coordinated papervork can only be mathematics.
The purpose of the theor,y of files is to support this belief.
Today the theor,y of files, whose basic
definitions are stated inl, has been applied
only to investigation of a specific area of
paperwork control: the area of systems analysis,
namely of the analySis and definition of those
procedures which can be carried out by automatic data processing systems. The specific
problem of non-numerical data processing has
been emphasized, the main reason for this being
the Widely spread prejudice that this field
cannot possibly be approached scientifically.
Available Computer Languages

Introduction
The first step of any initiative yielding
to the scientific knowledge of a new field consists of the definition and development of a
language and of a notation able to describe the
phenomena which characterize such a field. In
particular, the adaptation and the adoption of
one specific language - the mathematical language - has been successfUl in several areas
where the need for a scientific investigation
existed.
That aspect of human activity which seems
to be growing the fastest (in such a way that
it sometimes threatens to minimize the importance of all the others) is the control of
paperwork. Paperwork is one of the most impressive products of civilized society; its relevance with respect to the other activities
swells with the progress of our econo.my and
technology in a way which is liable to jeopardize this progress itself. Paperwork is generally carried out by machines; however, the work
of organizing, coordinating, defining and describing it is still performed by humans. '!'he
proportion of the total available manpower that
it absorbs grows dangerously with the wealth
and sophistication of our SOCiety, '!'he phenomenon of paperwork control has reached the
stage where it should be investigated scientif- .
iCally, hope~ to repeat the success that
c~arable scientific approaches yielded when
they were applied to other fields, in terms of
promoting the knowledge, suggesting the de-

A wide selection of computer languages
designed with the aim of providing tools for
automatizing the programmer's work is available
today; however, it seems that none of these
languages can help the systems analyst. We
think that the main shortcoming of such languages (which range from Simple assemblers to
autocoders able to handle macros, and to such
languages as the IBM Commercial Translator,
COBOL,J'ACT, now-Matic or AIMACO), are all deSigned according to the ~attern that we called
'v. Nf!1llDIUlll Language' in : a v. Neumann language4 is a language in which a phenomenon is
described by means of a sequence of statements
divided in two categories - 'executable' statements and 'descriptive' statements - in such
a way that the statements of the first category can be put into a one-to-one correspondence
with a f'lowchart 5 of the procedure involved by
the phenomenon represented.
SUch a language can be used successfUlly
for describing l~outs of information supports
and sequences of actions, namely procedures
Unfortunately such l.a.ngua.gEB cannot possibly
provide for a synthetical and compact definition of the compound of logical conditions to
which ~ action is subjected, nor for the
synthesis of a coordinated flow of information.
lor instance, if we consider a language such as
COBOL and we try to use it for representing
integrated data proceSSing procedures, the follOwing shortComings come to light:
G•

138
3.3
(1)

(2)

Each statement has the form "IF condition
THEN action", vhere the action denotes a
sequence of steps and the condition denotes
a boolean expression. Nevertheless the
execution of the action is only apparently
fullY controlled by the condition, in the
sense that the value 'true t of the condition is necessar,y but not sutficient tor
the execution ot the action. Such execution
depends also upon the path ot the control
through the procedure description, i.e, on
the result ot several tests, same ot which
may have preceded by far the action in
. question. Since the possible path ot the
control are m;yriad.l then.. for determining the
circumstances under which a certain action
is to be executed, one should carefully
trace through all ot the procedure description. It is usually not practicallY teasible even to identify such circumstances,
nor to correlate an action to the original
input information. What is needed is a
language by which all of the conditions
affecting an action are compounded into a
unique statement: such a language aould not
possibly contain any control statements,
and consequentlY could not possibly be a
v. Neumann language.
Most documents are selt-explaining, as tar
as their patA between different procedures
is concerned. However, one ot the big
problems in systems analYsiS is the determination of when and under which circumstances a document is entered into or issued
trom a procedure. This Yell known problem
of efficientlY coordinating the data flow
becomes one of the main issues ot systems
a.nalysis whenever one vants to save computer time by increasing the degree of procedural parallelism. In COBOL, li~e in any
other v. Neumann language, the f'low of information can only be controlled by means
ot input-output statements, and by a proper
organization of the control statements, i. e,
by caretuJ..ly planning the flow of the machine control through the procedUre description. In such easy applications as
payroll, where the degree ot parallelism
cann6t possiblY be high, COBOL can be used
successfully. On the contrary, consider
applicatiOns in which, for the sake ot
saving computer time, several fUnctionally
independent procedures that relate only by
the tact that they operate on sets ot tiles
which are sorted with respect to the same
key- (1.e., they are equiordered), are run
in parallel: then the use ot such a language leads to long and exceedingly involved descriptions. Even in same conwaratively simple applications, where tor
exampleJ billing and accounts receivable (or
ordering and accounts payable) are run in
parallel, together with the updating of a
master tile and with the preparation ot
data to be used later by the management
(such as notes tor exceptional cases, re-

quested reports, or totals), COBOL can compare favorably to some of the available
autocoders as a programming language. However, it does not seem to be an appropriate
analysis language for such applications.
In cases vhere the degree of parallelism is
high and the data floy is complex, slich a
language should be discarded.

(3) Last and least, it appears that the use of
same type of kindergarten English, vhose
adoption seems to be due to the objectionable assumption that it is more readily
understood by top executives than any more
appropriate technical notation, is an obstacle to the use ot COBOL even as a programming language, because it yields comparativelY long procedure descriptions. However,
this last shortcoming is really irrelevant,
primarilY because it atfects COBOL onlY as
a programming language. Further this shortcoming can be removed easily tr0lll the language without a:ny major change in the logic
ot its translators. It has also been a
cammon experience ot individuals programming with COBOL that after a fey statements
one drops the English of the language and
uses abbreviations, especially for such
phrases as "IS GREATER THAN".
BaSic Ideas
In addition to the trend which finallY led
to COBOL, two independent ideas vere developed
in the past tew years. Both aimed at the creation of a system language suitable for describing non-arithmetic data processing procedures.
The first philosophy can be summarized as tollows: t We must algebrize the non-numerical procedures, in order to be able to applY to them 6
successful algebraic languages such as Fortran t
The other can be expressed in this vs:r: 'The
major problem in non-arithmetic data processing
is the one ot detining and COOrdinating the
data flow: betore ve can design a system language, we should discover and tormulate the
laws ot the data flow'.
The theory of f'iles is but a syntheSiS of
these two ideas: from a methodological standpoint the theory of files consists of expressing
and a.nalyzing algebraicallY the lays ot the data
flow.
'rhe starting point in the t'heory of :tiles
was the remark that if ve consider the merger
between two files ot records as a sum,while the
merger ot them with selection of all those records whose key is not present at least once in
both files as a product, then, under certain
circumstances, sets of equiordered files can be
reduced to boolean algebrae of files. In such
an algebra the most common file handling operations can be defined by simple algorithms: for
exampleJa k-~ sorting-by-merging procedure
(either tixed or variable length-sequence) is
represented as a recurrent summation of k files.

139
3.3

From a file-theoretical standpoint, a procedure is broken down into a sequence of PULSES,
at whose beginning new records are (logically)
entered, during which calculations are performed, and at whose end all the compl.etely
processed records are (logically) filed. Only
records whose keys all have the same value are
considered in a pulse. A sequence of pulses
during which all the records of all the files
involved in a procedure, whose keys equal a
certain constant, are processed, is called a
PHASE of the procedure.
!he language that we propose for describing procedures is the Algebraii BuSiness
LaDguage (ABL). It is described in , where the
basic concepts of the theory of files are defined mathematica.lly. In its siq>lest version,
an .A:BL procedure description consists of a
sequence of 'conditional. expressions', namely of
sets of executive orders ('actiOns') subject to
boolean expressions ( , conditions' ). 1'!lere are
no control statements, and the conditional expressions are to be considered sequentiaJJ.y8,
1. e., from the first to the last.

II can be accomplished si~ly by performing a
precedence analysis and a simplification of the
procedure deSCription. (Notice that this would
not be easy in a v. Neumann language).
In order to discuss point I, let us consider separately input-output.
Input. The pattern which maximizes the
input-parallelism is unique for arr:r phenomenon
of the kind we are considering. More preCisely,
it consists of the following:
1) No more than one record per each file
is entered during any: pulse.
2) Consistently vi th 1), a record belongi~
to any file 7 is entered as soon as it
is both logically available and all the
records pertaining to the current phase,
belonging to any one of the files which
precede 7 in the logical order, have
been entered.
3) A phase is over at the end of its pulse
during which the last record pertaining
to it is entered.
4) Logical input is only performed at the
beginning of the pulses.

Optimization.
Simplification. In each procedure, a LOGICAL ORDER ot the files involved must be given
by the anaJ..yst.
Definition 1: "Let us denote by DD the data
description of a given problem; then two procedures are 'DD - equivalent' if they both transform arty input organized according to DD into
the same output".
Definition 2: "A procedure P is called
DD - optimized' if, i1n the space {DD, p} of
all the procedures which are DD - equivalent to
P, P both
a) Max1:m:izes the parallelism of logical
input-output
b) Minimizes the amount of internal processing".
From an applicative standpoint, only' DD optimized procedures should be considered:
notice that the maximization of the parallelism
ot the physical input-output flow can be obtained only on the basis of a logical one whose
parallelism is maximized.
l(ow two pulses are

independent as
far as internal processing is concerned, and
two phases are alw~s independent as far as
input-output is concerned: consequently, in
order to DD - optimize a procedure, it is sufficient to
I) Ma.x1m1ze the parallelism of the logical
input-output within the pulse.
II) 1I1n1m1ze the amount of internal processing wi thin the phase.
alw~s

Since ABL is a sequential language, point

Since the input pattern is unique tor any
procedure of the type we consider, the analyst
is not burdened with the control of the input:
he can just forget about it. The only' ~ in
which the analyst using ABL can control input
is by designing the logical order of the files
properly.
ouput. Unlike input, which is :f'ulJ.:y
standardized and automatiC, output is entirely
and directly controlled by the analyst. In
fact, the conditions under which documents are
to be issued al~s depend upon the particular
phenomenon considered. Furthermore, the determination of these conditions can otten be
considered as the major single factor in the
representation of this phenomenon. Since it
is important to have these conditions compounded in a single synthetic expression tor
each output file, the output of each file is
controlled by a J'LOW CONTROL EXPRESSION, conSisting of the name of the file in question
followed by a boolean expression denoting the
condition under which a record of this file
is to be issued.
Indicators. The boolean variables used for
writing a procedure description (which are
compounded into boolean expressions in ABL,
while they consists of sets of parts of different statements in any v. Keumann language) may
have three origins:
a) They may be generated by comparison
between numeric, alphameric or boolean
entities.

140
3.3
b) They may be determinations of conditional variables.
c) They may be references to the current
configuration of the data now.
While no need arises for a special discussion of the conditions of the first two categories, we may point out that vhen any v. Neumann
language representation of a procedure is used,
such references are generated by means ot careful constructions and comparisons of keys. The
theory of files suggests that the layouts of the
keys of the files are given as part of the data
deSCriptiOns, and that the keys of the records
are constructed and related automatically to
each other as part of the I-~ operations: consequently, these operations are not under the
control ot the analyst. Since references to the
current status of the data flow are otten necessary for making decisions which condition the
phenomenon considere~'ABL must have a provision
for giving to the analyst complete information
about it. The configuration of the data flow
never changes during any pulse, and from a filetheoretical standpoint it can be fully characterized by stating the occurrence or omission of
five conditions for each one of the files involved. This can be done by means of INDICATORS,
five boolean variables per each file, whose value
never varies during any pulse.
Let us explain intuitively what each indicator of a file F stands for:
1) the 'EXISTENCE INDICATOR' of F denotes
the logical presence of a record of F.
2) The 'LEFT DERIVATIVE' and the 'RIGH'l'
DERIVATIVE' of F characterize those
records of F whose key has a value
which is dif:f'erent from the value of
the keys of all the preceding [foll~,
respectively] records of !'.
3) The 'INPtJ'lI - OUTPUT INDICATOR' of l'
by being "on" denotes those pulses
where a record of F is entered or issued.
4) The 'NON CONFOIOO:n INDICATOR' of F
characterizes those records of F which
are incomplete or non-conforming.
Four further indicators, which are CODDD.on
to all files, are available in each representation of a phenomenon for denoting its initiation and closure. No other information regarding the data flow is needed in any DD optimized procedure/in whose description the
indicators can be used without any distinction
from the other boolean variables.
The setting and resetting of the indicators (i.e., the 'indicator logic') is performed automatiCally according to the rules
stated inl (section 3), where the laws of the
automatic data flow control-in particular of
the input mechanism - are stated in terms of
relations between the indicators. The set of
values of the indicators in each pulse is a
synthesis of the data flow'control related to it,

and is obtained as a subproduct of the logical
operations involved by the input and output.
Though the analyst can neither set nor
-.reset any indicator, an indicator can be used
anywhere in the procedure description: in particular in the nov Control ExpreSSions.
Hardware and
Se~ential

~lementation

Languages

Like a mathematical synthesisot a physical
phenomenon can be stated by means of a sequence
of equations, so the theory of files allows one
to express a mathematical synthesis of a data
processing phenomenon in ABL by means ot a sequence ot condi tional expressions. In both
cases the sequence is considered fram the first
e~ation (or conditional expreSSion, respectively) to the last one. '.rhe flow control expressions are conditional expressions where the
action consists of issuing a record. Neither
the equations of an algorithm nor the conditional expressions of a non-arithmetic procedure
description are in a one-to-one correspondence
Wi th the steps of any path that a machine
con.trol would follow in order to carry them
out. Unlike any v. Neumann language, ABL is
'se~ntial' and.
asynchronous Wi th respect
to the ~ the procedures described are implemented. 0l1r study shows that languages having
this structure are generally more suitable than
v. Neumann languages for approaching data procESsing phenomena scientifically.

It one vants to utilize the theory of files
not just as a method of investigation but also
as a tool for the automation of systems analYs1s,
he must be able to develop mechanically sequential outlines into flow chart~ 1. e., into procedures. More precisely, one should be able to
transform the sequential representation of any
data processing phenomenon into a DD optimized
flow chart. Apparently this transformation
can quite easily be made because of the standard input scheme, and of the fact that each
conditional expression completely determines
one specific issue of the procedure, like the
presence of a record in an output file or the
value of a certain field of an output record,
etc. A difficulty arises when we consider the
interrelationship between the indicators of the
various files; for exampl~, the condition-part
of a certain conditional ~xpression, say EA.,
may depend upon the setting ot an indicator of
an output file whose records are filed under .
the control ot another :now Control ExpreSSion,
say EB, which comes af'ter EA in the sequential
description. Conse~ently, the sequence ot
operatiOns must be properly arranged in order
to avoid unnecessary look-aheads. Such rearrangements should not be performed by the
analYst, ·who should only be concerned With the
statement of the information processing effect
of the phenomenon, rather than With procedural
considerations or with any simplification of

141
3.3

the correlation among expressions. This simplification should be carried out by the machine,
together with the entry and removal of auxiliary
conditional expressions and with the optimization of the arithmetic for.mulae. This last
operation should not be bounded to the optimization of each single for.mula within itself, but
should consist of analyzing the relations between different expreSSions in order to avoid
unneeded repetitions. The study of Semapraxis
codifies the eflorts of analysists toward the
intelligent utilization of computers for such
machine simplifications. In particularlO by
Feldstein enunciates such details.
The ABL representation of a phenomenon can
also be mechanically checked against tautologies
and contradictions which may depend on an erroneous analysis of the phenomenon itself; for
instance, in the above example, if the phenomenon is coherently stated, EB should depend
neither directly nor indirectly on EA.
Special Devices.
Most stored program data processors are
provided with an operating system which includes efficient buffered input-output subroutines. Same data processors-the IBM 7070-74,
for example - have specific features (scatterread-gather-wri te, highly parallel memory bus,
block transmission with rearrangement, etc.)
which allow the programming of very efficient
I-¢ routines, including the necessary key logic.
In accordance with the adoption of same new
ideas in the design of machinery, (consider for
instance the non-arithmetic processor of the
IBM Harvest, Or the systems with a Fixed+Variable structure9 ) it is sometimes convenient to
wire such routines.l which become parts o;r modules
of the hardware.
When a system bas to carry out procedures
represented in ABL a similar alternative arises
for the indicator logic,which will be programmed for standard systems and built for more advanced and specialized ones.
A third case where the issue of a comparison between wired and programmed t giant commands' varies with the modernity and specialization of design of the basic hardware is related
to the handling of the compact and flexible
t table operations t with whose use ABL provides
the analyst (seel , section 2).
'rhe implementation of ABL is significantly
conditioned by the hardware considered: it
appears more difficult to carry it out for standard, strictly stored-program computers than for
more advanced ones. The generation of a program on the basis of an ABL representation is
more direct in the last case; we think that this
is due to the great deal of overlap among the
ideas which l~d the engineers to such advances
in systems design and those which yielded the
theory of files.

However, the indicator logic is new only
as a method. Most control statements and logical operations written by programmers using
COBOL or symbolic machine languages should be
considered as a clumsy, approximative and only
partially satisfactory replacement for a clean,
universal and fully automatic indicator logiC.
Let us conclude by pointing out that the
advantages of adopting sequential languages
does not seem to be bounded to the use of large
scale data processing systems. On the contraryl
such languages appear to be intimately related
to the nature of non-numerical data processing
phenomena, regardless of their implementation;
for example, a sequential language quite similar
to ABL proved to be well suited for representing
procedures to be carried out by very simple,
externally programmed data processors3.

'*The preparation of this paper was sponsored by the Office of Naval Research. Reproduction in whole or in part is per.mitted for any
purpose of the United States Government. The
author also wishes to express his gratitude to
M. Alan Feldstein for his help in the preparation of this paper.
References
1.

L. Lombardi, "Mathematical structure of NonArithmetic Data Processing Procedures"
(Forthcoming in J.A.C.M.).

L. Lombardi, "System Handling of Functional
Operators" (Forthcoming in J.A.C.M.) •

L. Lombardi, "Inexpensive Punched Card
Equipment" (Forthcoming.) •

H. Goldstine, J. v Neumann, "Planning and
Coding for an Electronic Digital Computer"
(LA.S., 1948).

IBM Staff', "Flow Charting and Block Diagramming TechniqueS' (c20-Bo08).

Notice that Fortran is also a "v. Neumann
language" •

seel , section

Another t sequential language twas conceived
independently of us by C. B. Tompkins with
the collaboration of M.A. Melkanoff and J.D.

SWift.

G. Estrin, "Organization of Computer Systems
- The Fixed plus Variable structure Computer"
(Proc. of the 1960 WJCC).

10. M.A. Feldstein, "Semapraxis" (Forthcoming~.

143
3.4

POLYPHASE MERGE SORTING -- AN ADVANCED TECHNIQUE
R. L. Gilstad
Minneapolis-Honeywell Regulator Company
Electronic Data Processing Division
Wellesley Hills, Massachusetts
The Challenge
Designers of generalized library sort
packages for the current and future generations
of computers are faced With the challenge of
developing new techniques that provide more
effective use of these computers. The major
concern in developing efficient sorting routines
in the past has been the internal sorting techniques, that is, the methods of manipulating the
data wi thin the memory of the computer. Precise
methods must, of course, be devised for each new
computer design but, due to the extensive effort
in this area in the past, few new internal sorting techniques have been introduced for, what
are in computer terms, generations.
Emphasis is now being given toward more
effective use of the tape drives used by a sort
routine. Progress toward this end was reported
in the paper "New Merge Sorting Techniques It ,
presented by B. K. Betz at the September 1959,
ACM Conference. The paper then presented
described in theory an advanced merging technique, originally called the !tN-lIt technique,
now a proven method better known as the Cascade
sorting technique.
The intention of this paper is to introduce
a new merging technique, polyphase sorting. The
following section describing the application of
the Cascade sorting technique is included to aid
in the understanding of the evolution of the
polyphase sorting technique and to prepare for
certain comparisons later in this paper between
the various sorting techniques. A complete study
of the changes in merge sorting would, of course,
include a description of the process that is
referred to in this paper as normal merge sorting and that has such names as two-w~ merge
sorting and three-w~ merge sorting. Because of
the extensive use of normal merge sorting techniques, this paper assumes a general understanding of them by those interested in this subject.
Cascade Sorting
The Cascade Merge Sort, available exclu~
sively in the Honeywell 800 automatic programming packages, is a two-segment program, the
first part of which is an internal sort that
creates strings of ordered items. The internal
sorting method that has proven to be most advantageous to Honeywell for generalized sort generators uses the "tag bin It concept which transfers
internally only a tag representing each item
stored in memory, instead of transferring the
entire item. Further, the "replacement" sorting

method is added, which creates strings of
ordered items substantially longer than the number of items stored in memory. This method, in
fact, provides strings averaging twice the number of items stored in memory for randomly
ordered input data and longer strings if any
pre-ordering exists in the input file.
The only real difference between the internal sort, hereafter called the pre-sort, for
Cascade sorting and normal sorting is the manner
of distributing the strings onto the work tapes
used by the sort. Normal merge sorts require
that the strings be distributed alternately on
two work tapes for a two-w~ merge sort, or on
three tapes for a three-way merge sort. The presort for a Cascade sort distributes the strings
of sorted records onto all but one of the work
tapes available to the sort. The ideal distribution at the completion of the pre-sort is such
that there are fewer strings on each succeeding
tape. The exact distribution is based on one of
several sequences, depending on the number of
tape drives being used. The sequence for the
three-tape sort is the Fibonacci sequence:

1,1,2,3,5,8,13,21•••••••• ,
while the sequence for a four-tape Cascade sort
is the sequence:

1,1,1,2,3,5,6,11,14,25,31••••••••
If the pre-sort for a four-tape Cascade sort
creates 14 strings, the distribution of strings
on the three work tapes would be six strings,
five strings, and three strings.
The determination of the distribution of
strings by the pre-sort can be in the form of a
pair of counters for each tape being used as an
output tape. One counter for each of the tapes
contains the ideal distribution for one merge
pass, while the second counter contains the total
number of actual strings written on each tape.
Strings are written onto each tape until the pair
of counters for that tape are equal. When all of
the counters are equal for one ideal distribution,
the ideal distribution counters are updated to the
values for an additional merge pass. The flow of
the distribution process and the use of the
counters is shown for the pre-sort for a fourtape Cascade sort in Figure I.
The second segment of the Cascade sort is a
merge sort, during which each pass over the file
begins with an N-1 ~ merge (where N is the
number of tapes available to the sort) that continues until the work tape with the least number

144
3.4

of strings is depleted. As each tape is depleted,
the way-merge is decreased by one until the pass
is concluded by a one-way merge (copying),
depleting what was the longest work tape.
Many methods for demonstrating the flow of
information through a merge sort have been developed and used, none of them to the satisfaction
of this writer. A picture does, however, replace
a thousand words, so a Cascade sort is pictured
in Figure II using numbers representing the number of strings on each tape at each step of the
sort.
The power of this sort technique is derived
from the fact that a larger percentage of the
file is merged during the most powerful waymerge than is merged during the later phases of
the pass; more specifically, for a four-tape
sort, 52% of the file is merged during the threeway merge, 36% is merged during the two-way merge
and only 12% of the file is involved in the copy
portion of the pass. A normal four-tape merge
sort is continually performing a two-way merge,
giving it a merging power of 2. The Cascade sort
for a like number of tape drives has a merging
power of 2.3. That is, it reduces the number of
total strings by a factor of 2.3 each pass.
A further advantage of the Cascade sort,
which is implied above, is that an odd as well as
an even number of tape drives, and as few as
three, can be used to full advantage.
The sort routines described above assume a
read-backward merge sort, which eliminates the
need for rewinding during the sort, but which
requires the copy portion of each pass in order
to reverse the order of the remaining strings on
the long work tape. (A read-backward sort must
switch the strings from ascending order to descending order on successive passes.) The same
Cascade method is available for a read-forward
merge, which must, of course, rewind certain
tapes during and between passes. This allows the
elimination of the copy portion of each pass, as
all of the strings are always in ascending
order. In order for a read-forward Cascade sort
to retain a time advantage over normal readforward merging, tape rewinding must be a faster
process than the tape reading process. All of
the comparisons between normal merging and
Cascade sorting involving rewinding are based on
the Honeywell 400, which has a 3 to 1 ratio of
rewind speed over reading speed.
Polyphase Sorting
Further advancement in the efficient use of
the tape drives used by a sort has developed
from the Cascade sort. This new sorting technique is called the polyphase sorting.
The polyphase sort, like most merge sorting
methods, is a two-segment program, a pre-sort
segment and a merge segment. Again the pre-sort
distributes the ordered strings onto all but one

of the available tapes, based upon one of several
sequences. The sequences for the various tape
drive configurations are as follows:
3-tape 1,i,2,3,5,8,13,21 ••.•••• (It is noted that
this is the same sequence as for a 3-tape
Cascade sort. Indeed, a .3-tape readforward Cascade sort is the same as a 3tape polyphase sort.)
4-tape 1,1,1,2,2,3,4,6,7,11,13,20,24 •••••••
5-tape 1,1,1,1,2,2,2,3,4,4,6,7,8,12,14,15 •••••••
6-tape 1,1,1,1,1,2,2,2,2,3,4,4,4,6,7,8,8,12,14,
15,16 ••••••••
During the merge segment of a polyphase sort,
a continuous N-l way merge is performed. At the
beginning of the polyphase merge segment, the N-l
way merge is performed until the tape with the
least number of strings is depleted. At this
point, instead of switching to an N-2 way merge
as in the Cascade sort, an N-l way merge is continued, merging additional strings from the tapes
not yet depleted, with strings from the tape just
created. Because this process is continued
throughout the merge, there is no point that can
be called a complete pass over the file. Instead,
there are a series of phases, wherein some strings
from a number of previous phases are merged
together.
The four-tape polyphase sort example in
Figure III shows the effect of this technique
through an entire sort. The numbers given in the
example represent the number of strings at each
of the various phases of the sort.
Comparing the Merges
The power of a polyphase sort is not easily
discernible or readily comparable to other sorting techniques, due to the fact that the phases
described above cannot be compared directly with
the passes of the other techniques. A normal
two-way merge sort, for example, processes the
entire file being sorted during each merge pass
and in so doing, reduces the number of strings
by one-half. Another way of stating this is that
during each merge pass the length of each string
is doubled. This is abbreviated by stating that
a two-way merge pass has a power of two. Each
step shown in the polyphase sort example processes
only a portion of the file. Therefore, while it
can be determined from the tables in Figure IV
that a four-tape polyphase sort has a power of
1.88 per step as compared with a power of 2.0 for
a normal sort using four tape drives, the polyphase is significantly faster because it processes only 62% of the file during each step as
compared to the 100% processed during each step
of a normal sort.
Figure I contains two tables which show the
total number of strings that are merged together
for the given number of steps of the merge sort

145
3.4

for four- and six-tape normal, Casoade, and polyphase sorting. The tables also give the peroentage of file prooessed for eaoh step (phase).
This peroentage is the average for a number of
phases in the case of polyphase sorting, the
speoifio values varying slightly from phase to
phase.
Further oomp1ications in the oomparison of
the power of the several sort teohniques include
the internal maohine speeds, the amount of simultaneous operation, whether the sort must ino1ude
tape rewinding, and if so, the relative rewinding
speed of the tape meohanism. Figure V relates
normal, Casoade, and polyphase sorting as performed on a oomputer capable of reading baokwards
and performing all prooessing at full tape speed.
The figures for the polyphase sort have been
equivalenoed to the same peroentage of file processed as for the normal and Casoade sorts.
Figure VI desoribes graphioally the relationship of the power of the three sorting teohniques. The graph shows the number of passes
over the file required to merge a given number of
strings together into one string with four tape
drives.
No attempt has ~en made to date to implement a read-backward polyphase sort. The delay
in doing so is caused by the neoessity to alternate asoending and descending strings on eaoh of
the work tapes during the pre-sort. This alternation of strings destroys the advantage of a
variable length string pre-sort whenever some
degree of pre-ordering exists in the input to the
sort routine. Pure random input data would be
sorted faster with a polyphase sort, but experienoe indicates pre-ordering to some extent
exists on the majority of files to be sorted.
Read-Forward Merging
Merge sort routines for oomputers that allow
only read-forward tape operations must rewind a
oertain percentage of the file between suoceeding
steps of the merge. A normal two-way merge, for
example, rewinds the entire file after each pass
of the merge, but, because the file is distributed
evenly on two tapes that can be rewound simultaneously, the rewind time for eaoh pass is onehalf of the time to rewind the entire file.
A read-forward Cascade sort rewinds a larger
percentage of the file eaoh pass than does a normal sort, but retains a time advantage beoause it
does not process the entire file eaoh pass. A
four-tape, read-baokwards Cascade sort performs a
three-way merge over 56% of the file, then must
rewind the newly created output tape and the
input tape that was depleted. The rewind of the
depleted input tape, which del~s the operation,
is over 19% of the file during the first pass.
The Cascade sort then performs a two-way merge of
34% of the file and rewinds the same percentage
of the file. The remaining 10% of the file on
the third tape becomes input to the next pass and

is not prooessed during the our rent pass. After
the three-way merge on the seoond and all suoceeding passes, the input tape to be rewound ino1udes
information used during the three-w~ merge and
two-way merge of the previous pass as well as
during the three-way merge of the ourrent pass.
This amounts to 56% of the file. Normally, therefore, the Cascade sort processes 90% of the file
and rewinds 90% of the file during eaoh merge
pass.
A read-forward polyphase sort rewinds the
same percentage of the file that it prooesses
each phase. A four-tape read-forward polyphase
sort processes and rewinds 62% of the file during
eaoh phase. As did the Casoade sort, the polyphase sort depends upon a faster rewinding process than merging process to maintain its full
advantage over normal sorting.
Conclusion
The two new merge sorting techniques pre- .
sented here are now working programs, proven to
be the tools for a more effioient computer operation. Cascade sorting provides the effioiency
for read-baokward operations. Polyphase sorting
provides the effioiency for read-forward operations and in the future oan provide the efficienoy for read-baokward operations in cases
where the file to be sorted has been determined
to be in random order.
There is one hardware prerequisite which
should be mentioned, whioh is neoessary to obtain
the full advantage of Casoade and polyphase sorting. If reading and writing are to be simultaneous, the sort must be able to read from one
tape and write on another in aQY oombination
involving the tapes used by the sort.
It is worth noting that improved approaohes
to the common, everyday oomputer problems are
still being found in an era where the emphasis is
on new uses for computers and new designs for
computer hardware.

146

3.4

Ideal Distribution Counters
(Total Number of Strings)

Distribution of Strings
(Successive String Numbers)

Tape A

Tape B

Tape C

Tape A

Tape B

Tape C

One merge pass

Two merge passes

4,5

Three merge passes

7,8,9

10,11,12

13,14

Four merge passes

15-22

23-28

29-31

Fig. 1. String Distribution for a Cascade Sort

Tape A

Tape B

Tape C

Tape D

Output from pre-sort

After three-way merge of 6 strings

(6)

After two-way merge of 5 strings

(5)

(6)

After copy of 3 strings

End of first pass

After

After two-way merge of 2 strings

(2)

After copy of 1 string

three-w~

merge of 3 strings

End of second pass
2

(1)

After two-way merge of 1 string

(1)

After copy of 1 string

After three-way merge of 1 string

End of third pass
1

After three-way merge of 1 string
End of sort

Note:

All numbers represent the number of strings on each tape at each
step_ The underlined numbers are the output at each step_
Fig. 2. Cascade Sorting.

147
3.4

Tape A

Tape" B

Tape C

After three-way merge of 7 strings

After three-way merge of 4 strings

7
3

l±

Tape D
Output of pre-sort
After three-way merge of 13

5 trings

After three-way merge of 2 strings
1

After three-way merge of 1 string
After three-way merge of 1 string

Fig. 3. Polyphase Sorting.

Table B -- Six-tape Sorts

Table A -- Four-tape Sorts
Steps
1
2
3
4
5
6
7
8
9
10
11
12

% of file
processed
per step

Normal

Cascade

Polyphase

2
4
8
16
32
64
128
256
,12
1024
2048
4096

3
6
14
31
70
157
353
793
1782
4004
8997
20,216

3
5
9
17
31
57
10,
193
3,5
653
1201
2209

100%

Steps
1
2
3
4
S
b

7
8

Normal

Cascade

Polyphase

3
9
27
81
243
729
2187
6561

15
,5
190
671
2353
8272
29,056

5
9
17
33
65
129
2,3
497

% of file
processed
per step

100%

55%

62%

Fig. 4. Number of Strings Merged.

Table of power of read-backward sorts with a tape limited operation.
Power of
Normal Sorting

Power of
Cascade Sorting

Power of
Polyphase Sorting

3 tapes

1.5

1.61

1.80

4 tapes

2.30

2.79

5 tapes

2.5

2.94

3.44

6 tapes

3.62

3.86

Number of Tapes
Used by Merge

Note:

The power of a sort, as used here, is the factor by whiCh
the number of strings decreases for each full read time
of the file being sorted.
Fig. S. Power of Three Sorting Techniques.

148

3.4

'lit
CD

0
W

(!)

0:
W

:E
C\I
rt)

C/)
(!)

0:
t-

0:
W

m
:E
:::>
Z

Fig. 6. Comparison of Three Sorting Techniques.

149

3.5
THE USE OF A BINARY COMPtJrER FOR DATA PROCESSING
By:

Gomer H. Redmond, Manager, Corporate Systems and
Procedures Department, Chrysler Corporation
Dennis E. Mulvihill, PH.D, Senior Consultant,
Touche, Ross, Bailey & Smart

Summary

On the other hand, the decimal mode machine
arguments center around the following:

Considerable discussion has been generated
concerning the use of binary computers for purely
data processing functions rather than decimally
oriented machines. The purpose of this paper is
to present a case for the use of binary machines
for data processing based on our experience at
Chrysler.
Based on experience gained by the Chrysler
Corporation, the paper discusses the need for
the establishment of a consistency of concept
for all phases of problem organization and
solution.
Specific advantages inherent in binary
machines are pointed out, along with some of the
pitfalls which would result if the consistency
of concept is not maintained.
In their treatment of this subject, the
authors also sound a warning to those concerned
with the development and use of generalized business oriented languages that certain abilities of
binary machines have not been exploited in these
programs.
In ~eir·conclusion, the authors state that
the abilities of binary-type machines will become
more indispensable as management techniques,
extant to~, become more sophisticated and
acceptable.

There is an unresolved controversy as aired
in past issues of the A.C.M. Communications,
journals, sympoSiums, conclaves, and sundry other
learned gatherings as to the superiority or inferiority of binary or decimal mode computers in a
data processing situation. Both have enjoyed
sufficient success in the field to warrant a further look at the controversy.
Let ~s examine some of the arguments offered
for each type of computer. The binary mode machine is said to have the following attributes:
1. Scaling ability allowing information
representation to be in any format;
2. Arithmetic circuitry is more efficient
in design and speed;

Compactness of data in memory;

Tape compression factor.

1. No transformation required between
internal and external representation;
2. Machine language is readily understood
by people;

3. Variable length fields are more advantageous to business-type problems.
The above points, from both sides, can be
well taken; however, the arguments have been
abstracted from the environment in which business data processing is being used, that is, the
productive use of data processing as a means to
efficient business management. This is the
arena where efficiencies and deficiencies of data
processing machines can be appraised.
The virtues (and vices) of decimal and
binary mode machines have been discussed since
man first im,plemented computer hardware, and the
argument will continue until the perfect machine,
whatever that might be, is developed and marketed.
I do not intend to discuss the theoretical
virtues of either type of computer. I will discuss the controversy in terms of Chrysler's experiences with both types. In the automobile
industry, Chrysler has pioneered in the use of
EDP. One of the first IBM 702' s was installed
in our Service Parts Center in 1954. Since then,
we have added seven IBM 650's, one UNIVAC I, one
UNIVAC File I, and two IBM 709's, one of which
has recently been replaced by an IBM 7090. In
addition, an H-Boo will be installed next spring
and four IBM 1401' s will be installed in the next
few months.
At Chrysler, data processing equipment is
selected on the basis of providing the best equipment for the systems in which it will perform.
And so it is with all practitioners in the field
of data processing. At some point in the game,
users must choose between the two modes, binary
or decimal. The success:f'u.1 outcome of their venture will depend on their effective use of the
equipment regardless of the mode inherent in the
selected hardware. It is to this effective use
that this paper is aimed, and, by our experience
at Chrysler, to prove that more effective use can
be made of' a binary-type computer for data processing applications of the magnitude of those on
the computer in Chrysler's Corporate Information
ProceSSing Center (C.I.P.C.).

ISO
3.5

Chrysler's 7090 installation, C.I.P.C., is
used primarily for business data processing, as
was its predecessor, the 709. Included in the
list of applications are the following major jobs:
Vendor Releasing
17,000 Item, Bi-Monthly;
Hourly Payroll
65,000 Employees, Weekly;
Production Reporting
20,000 Orders Daily;
Warranty Claims & Payments
100,000 Monthly.
We have operated C.I.P.C. for the past year and
one-half with the binary mode computer and will
continue to rely on this type of machine indefinitely.
Since our frame of reference is the 709/90,
our specific examples are in terms of these two
computers, but I believe much of what will be
said will apply to any binary-type machine of
this magnitude commercially available now or in
the future.
The earlier binary-type machines, of the
701/704 Vintage, could not be used efficiently as
data processors. There was a problem in the
translation of decimal data to biliary for internal processing and vice versa for output operations. Coupled with this, and really quite significant, is the fact that serially-organized
machines could not perform data transfer operations without interlocking the central processing
units. The desire for business-oriented systems
to share computers with their Engineering counterparts, along with other pressures, finally led
the various equipment manufacturers to equip
their newer binary machines with the ability to
perform I/O functions in parallel with internal
processing. It is, therefore, the binary-type
machine with the ability to perform I/O in parallel with internal processing that will be considered here.
In planning to use any large-scale computer
for data processing, it is important that sufficient study be performed in all phases of the
system design, programming and installation. In
planning the use of a large-scale binary machine
for data processing, it is very important, let
me say it again: very important, that a consistency of concept be formed early in the systemdesign phase and maintained throughout all phases
to problem solution.

This consistency of concept, if you will, is
to think in binary for a binary-mode computer. To
exploit the logical power of the binary-type
machines, binary techniques must be used. There
is a great danger in utilizing a binary-mode
computer by applying data processing problems
conceived in the decimal mode. Although with

their flexibility, binary machines can be used
in this manner, it is inconsistent with the organization and logiC inherent in the computer and
carries a penalty of more involved programming
and, in many cases, longer running times.
There is a natural tendency to use decimal
representation in record formats; if a binarytype computer is to be used the consistency of
concept should dictate that "abbreviated binary"
representation be established wherever possible.
For straight numeric representation this should
afford a thirty per cent improvement over decimal
representation.
Although the 709 and 7090 can perform data
conversion much more efficiently than earlier
binary machines, the time required to convert
from decimal to binary and back to decimal can
be significant in a large data processing application. Our payroll, in the next few months will
increase to over 100,000. An evaluation of the
desirable mode of representation for our payroll
master file indicated that there was a saving of
34 minutes on the 709 in each payroll run, if the
master file were binary rather than decimal.
.
The representation of information in binary
not only applies to magnetic tape and internal
operations but to other I/O media. The use of
binary-type data, external to the computer, can
be quite significant, where portions or all of a
standard tab card can be utilized in "Chinese
binary" type codings expanding the information
content of the card upwards to 12 times its normal alphameric capacity. At Chrysler, this characteristic of the binary mode machine has been
most significant in our production scheduling and
reporting system. As you may realize, there is
considerable amount of information that must be
coded for each automobile for production reporting. The many accessories and option combinations must be reported in order to accurately
record production. It would be a gross understatement to say that this information could not
be represented in Hollerith in a single punched
card. Using a binary representation we are able
to obtain a maximum of 340 option and accessory
codes in 34 columns of a single card. The balance
of the card in Hollerith gives us a total of 386
segments of information in a single card. This
ability of card stretching is not limited to
binary machines--but only recently has this ability been adapted to the decimal machines and then
at some added cost of hardware and programming
effort.
In many, if not all, data processing problems
conditional tests must be made prior to processing
input or output data. Binary coding techniques
allow single bits to operate as flags or indicators, and single words or strings of bits to
contain all of the necessary conditional flags to
efficiently operate on the problem at hand. In
the decimal machine this ability has been restricted to using individual characters which require
several bit positions f~~ a single flag. Quite

151
3.5

recently some decimal machines have allowed access to bits, but even now there is considerable
processing and programming effort involved. Bit
manipulation inherent in binary machines affords
the programmer with the ability to perform
Boolean algebra techniques which become significant in terms of economical use of memory, program simplification and job running times.
The bit manipulation ability of binary
machines permits the programmer and in effect the
program, to perform subtle logical tricks of
character, instruction and operation modification
in a minimum of time. This ability is particularly useful in housekeeping operations, table
construction, address modification and decisionmaking functions. Very significant gains have
been obtained in table construction in our Vendor
releasing and production reporting systems. The
original system for vendor releasing called for
a two dimens ional master file. One dimens ion in
parts number sequence and the "other" which was
part within major assembly sequence. Originally,
it was necessarY to sort one file to the order of
the other and then sort the extended output for
summarization and publication of the requirements.
At the present time, the forecast for all
assemblies is placed in memory in a variable
length table. This variable length table is controlled by a bit coded basic finder table. The
advantage in this case is the effective use of
memory in the binary mode machine. We know 9f no
decimal oriented memory that could handle this
table. The resultant saving on the 709 from this
change was a reduction of processing time from 7
hours to 65 minutes.
Related to the comparison of bJnary and
decimal modes of information representation is
the variable and fixed word length characteristics. The binary is typically fixed word oriented.
The decimal mode computer on the other hand has
been both variable and fixed word length. One
argument frequently offered for the decimal mode
computers has been in terms of those with a variable word length. Yet, the use of the term
"variable word length" with most of these machines
may be a misnomer. Many so-called variable word
length machines, operating character by character,
examined closely are nothing more than fixed wordlength machines operating with short "six-bit"
words. As a result, the argument on this point
is reduced to size-of-word not variable-versusfixed-word length.
The fixed word binary machine at first glance
does not have the address flexibility possessed by
variable word length machine. But our experience
with the 709 and 7090 proves otherwise, there are
in the 709/90 word four addressable segments; the
decrement, tag, address and prefix which facilitate packing and unpacking with a minimum cost in
instruction time. Most other binary mode machines,
I believe, have similiar abilities, along with
semi-automatic or automatic masking operations
and half-word logic.

There is no question that variability is a
desirable attribute in a computer, but only in
terms of bits not characters. Tbis value of
considering infor.mation in terms of bits is most
significant in dealing with indicative information.
I would agree that for the representation
of quantitative and indicative information in
most data processing applications 36 bits is too
large a word, but as stated above a "six-bit"
word is also too large.
Another powerful ability of the binary machine is its ease of accepting varying formats of
coded information. Anything which can be represented by bits can be handled by a binary machine.
Thus far, this has been limited because the input/
output devices attached to computers were oriented
toward the decimal type machine. This ability
becomes quite significant when communications
schemes link remote operating locations with a
variety of equipment to centralized data processors. Format restrictions, in the centralized
machines, would require that all equipment be
compatible as far as information structure. But
with the flexibility of bit coding, a binary
machine can be programmed to handle all forms of
bit coding. In some of the newer super-scale
systems this ability has been further developed
to allow the hardware to perform operatiOns in
the more popular coding formats, including binary,
octal, bcd, bch, telegraph 5, 6, 7 and 8 level
coding. The next generation machines will partake
of the flexibility now existent in present day
binary machines.
The measure of effectiveness for any computer
is to a large extent dependent upon the programmer, the program, the compiler and operational
system.
In the case of programmers , it is frequently
alleged that there is an aptitude difference between those operating on binary mode and those
on decimal mode machines. This allegation is
carried to the point that the type machine rather
than the type of problem is the major determinant
in the selection of programmers. Programmers, in
the Chrysler context, are those individuals responsible for translating business systems, which
are frequently lacking exact definition, to computer systems. At Chrysler, the work performed
in C.l.P.C. is business data processing, and
therefore, most of our programmers are business
systems oriented.' The presence or absence of
mathematical backgrounds in our programming staff
offers no correlation to the effectiveness of
resulting programs. One conclusion we have drawn
is that programmers first-machine-training has a
great deal of bearing on their success as programmers of binary-type machines. Programmers
originally trained on binary equipment tend to be
better able to adapt to any machine, whereas the
converse does not necessarily hold.
In the case of programming, much has been

152
3.5

said with regards to the increased effort required for binary-type machines over decimal machines.
Granted that instruction repetoires for the former
are usually more extensive than those of comparable decimal machines. The restrictiveness of the
instruction lists in decimal machines may necessitate more involved programming for large complex
business systems. On the other hand, microprogramming ability inherent in binary machines
allows a more precise ~pproach to the solution of
complex functions. We realize that subtleties in
binary techniques are not readily discernible to
the neophyte programmer, thus the learning curve
may be some'What longer, but the results are more
significant in terms of programming efficiency.

puts at Chrysler's disposal the means to a vastly
improved business management system.

Significant gains have been made in the
field of generalized compilers, both in the
scientific and commercial areas. We are heartened by the progress that has been made in the
compiler area to date, but are not placing our
programming effort "on-the-line" with these until
the specifications call for, where pOSSible, a
binary approach to problem solution. The user
must be wary of sacrificing program effectiveness
for programming efficiency.

In the Sales area, dealer order and retail
sales information which serves as input to our
Production Reporting and Scheduling application
will be edited, and condensed to serve as further
input to a sales forecasting system, which is now
in the simulation stage.

In the specific area of generalized business
compilers, we "WOuld like to sound a warning to
those of you with binary machines who hope to
utilize these to great advantage over your present
programming methods. It is apparent to us that,
to date, little effort has been expended in the
generalized compilers to sufficiently utilize
binary techniques which will provide efficient
programs such as we have conceived and implemented
in lower-level coding systems.

Included in Chrysler's programming standards,
are general rules which inhibit the use of generalized sub-routines where tailored routines
would better serve to improve program efficiency.
The use of true macro-generators which produce
effective routines is preferred over the library
call and copy type sub-routines.
It is apparent to us that the role of scientific computation in operations research projects
is dependent upon an inexpensive, well-structured,
data collection system, where data collection is
not the major objective but a planned by-product
of routine, clerical data processing applications.
Many companies have moved head-long into the
field of OperatiOns Research only to find that
specific information was not available or could
only be obtained at great cost. With the Corporate Information ProceSSing Center at Chrysler we
have centralized the flow of information on several major systems. Data is now available on the
personnel, production, sales and inventory system
in the same format and collected automatically
from the routine data processing operatiOns now
on the computer. In this respect the utilization
of these centrally located files for operation
research type analysis along with the proven
scientific capabllities of a binary type machine

Specifically, in the analytical area, Chrysler is currently supplying the Industrial Relations Dept • with personnel and payroll data on
the characteristics of the total hourly-rated
work force. This information was formerly collected on the basis of a 5i sample. Even with
lO~ of the data, with less time and effort necessary to prepare and compile the needed data for
our negotiatiOns it will be more efficient and
factual. The ease of retention and accessibility
of historical data also makes the application of
other OR projects in the personnel area feasible.

It is interesting to
collected as a by-product
Reporting application and
will be utilized as input
Programming system, tying
major applications now in
tions.

note that the data is
of the Produetion
the resultant forecasts
to our Production
together two of the
our centralized opera-

other OR projects currently under stud;y are
in the manufacturing area, concerned with man
assignment and assembly line balanCing, and in
the financial area where Cash budgeting and
Finance Company simulations are in the otting.
Both of these studies require extensive data
which has been extrapolated from current data
processing applications.
Although we have all played lip service to
the concepts of management by exception techniques, there is every reason to believe that the
data processing function will assume greater responsibilities in the area of management decision
and the requirement for large volumes of data output will decline. Furthermore, as data processing
applications move from the performance of routine
clerical functions to the integration of operations research type solutions of management problems, the computational and logical abilities of
binary machines will become more indispensable.

153
4.1
HIGH SPEED PRINTER AND PLOTTER
Frank T. Innes
Briggs Associates, Inc.
Norristown, Pennsylvania
Summary
The Model 1063 High Speed Printer
and Plotter is a magnetic tape fed device for high speed plotting up to 6000
points per second in ten simultaneous
plots, at the same time it prints annotations for grid lines and draws the
grid lines, all with the output paper
moving at 10 inches per second.

available digital modules are used in
the control logic areas. In the other
parts of the machine where circuits
are used by the hundreds special purpose modules were built. Worst case
design with extreme derating of components was employed in combination
with rather eclectic logic.

The machine may also be used
simply as a high speed printer. In
this mode, it can print 4000 lines per
minute with 100 characters per line.

Each circuit area was examined
from the point of view of least cost.
As a consequence, the machine is a
mixture of diode logic, diode-transistor logic, and resistor-transistor
logic.

Design Philosophy
General
The general design philosophy
for this machine was to produce a
highly flexible off-line device which
would minimize programming requirements and machine time for the
IBM 7090 computer which generally prepares the input tapes. Since it was
early recognized that the required
generality would require the machine
to have quite substantial high speed
printing capabilities, it was specified that the machine be capable of
operating simply as a printer. The
success with which this philosophy
has been implemented is indicated by
the fact that soon after delivery
the customer modified the machine to
accept tapes produced directly by
his analog-to-digital format conversion equipment without any computer
processing; thus it operates valuably as a semi-quick look recorder.
Likewise as a printer, it is used
on a routine basis to print tapes prepared for conventional IBM printing
equipment. The customer is now making
minor additions so that the machine
will perform binary to octal conversions; in general this will completely
eliminate such operations on the computer.
Detailed Design
The detailed design naturally
stressed reliability and ease of maintenance using readily available components. Since this machine was built
on a limited budget, cost was a very
important object also. Commercially-

Overall Logic
A very general block diagram of
the machine is shown in Figure 1.
There, it is apparent that the machine
is really two machines, having a
common input and output. When printing only is to be accomplished, only
the print section is used.
When annotated plotting is to be done, the
machine starts off as a printer, allowing the title block to be composed at
the programmer's discretion. When the
first record containing data points
occurs, then the machine switches control of printing to the plot section
where it remains until the graph in
question is complete. With this mode
of control, it is a simple matter to
coordinate the annotation data with
the grid lines_ If it is desired to
establish a time reference with a grid
line, the necessary command is placed
on the tape next to the appropriate
data point; if it is desired also to
annotate this line, then the alphameric data with a print command are
placed there also. The machine then
operates to route the data in such
fashion that the required alphameric
data is waiting for the print command
when it occurs.
Subject to minor
programming restrictions, all these
operations are done without interfering with the steady flow of data required for a time history plot.
Output Device
The output device for this
machine is a Hogan Laboratories Model
HPP-110 multiple stylus recorder.

154
4.1

This unit is a facsimile type recorder
wherein a mark can be made on moist
electrolytically-treated paper by
application of an appropriate current.
The HPP-IIO has 1024 writing styli
which press II-inch wide paper against
a reciprocating steel strip with paper
moving at five or ten inches/second.
In the process of plotting or printing
currents are applied through the styli
to the bar; the electrolytic process
involved removes metal from the bar
and leaves it in the paper; the duration and magnitude of this current are
such as to produce highly uniform.
elementary dots approximately one onehundredth inch in diameter. Wear on
the stylus assembly is abrasive only;
currently, about 30,000 feet of paper
have been proces~ed without degradation of marking capabilities.
Output Circuits
Requirements
The HPP-110 is provided with its
own direct-coupled power amplifiers
one each for the 1024 styli. It is
readily apparent that some means must
be supplied to provide signals of the
proper magnitude and duration for the
power amplifiers. Plotting requirements call for 1000 such circuits; detailed consideration of the logic revealed that separate printing circuits
must be supplied also in addition to
auxiliary inputs for drawing of grid
lines.
The specification of two paper
speeds also leads to two signal duration requi~ements.
Since the same
elementary dot must be produced at
either speed, provision had to be made
for inexpensive variable duration control, explicitly for 0.5 milliseconds
and for 1.0 milliseconds.
Circuits
The actual output circuit card is
shown in Figure 2. The basic element
is the NOR flip-flop with a 2-input
diode gate on-the set input. The
upper row of five units provides for
five out of the 1000 possible plot
points with the diode gate forming the
second level of a 1000 point binary
decoder.
The lower four units correspond
to the first four elements in the
seven styli that are used for a column
of printing: three corresponding units
on the next card provide a total of
seven, which gives the space dimension

to the 7xll space time matrix used to
form alphameric characters. The diode
gates on these flip-flops are used for
column selection in conjunction with a
column counter.
In the general case, the outputs
of two flip-flops are buffered together' to drive the power amplifier.
Other innuts to the diode buffer provide grid line drawing capabilities
under either tape or patchboard control.
Signals to energize particular
styli are of nominal ten-microsecond
duration, ~ither from the print
section character generator or from
the plot decoder.
Signals to de-energize are applied to the reset inputs.
In the case of printing, the column
counter selects a particular column
whose styli are energized depending
upon the state of the character generator. The flip-flops correspond1ng to
this column are then turned off by an
unconditional output from the column
counter fifty columns later; since the
column counter operates at either 50
or 100 kc, the required 0.5 or 1.0
millisecond durations are automatically generated.
A similar operation determines
the duration of the point to be plotted; however, this is done under
patchboard cont~ol since it may be
necessary to plot line segments rather
than elementary dots, particularly
when the plotting rate is low.
Plot Section
Plot data and associated control
characters are stored in small coincident current memory buffers from
whence information is transferred to
the plot section under control of the
plotting rate clock. Ten bits out of
the twelve possible in two IBM tape
frames are used to specify a point to
be plotted. The occurrence of a plotting rate clock pulse triggers the
readout of data from the memory, a
read cycle being required for each
tape frame.
If the two frames are
recognized as a data point, then the
ten bits are assembled in the plot
register from whence they are decoded
and used to set the appropriate output
flip-flop.
If a control character is
recognized, it is decoded and the
appropriate action taken; at the same
time another pair of memory read
cycles is initiated until a data point
is found.
If more than one plot is
programmed, the above process is re-

155
4.1
peated until the preset number o£ simultaneous data points has been extracted;
although "simultaneous" data points are
actually plotted at 20 microsecond intervals, the distance between such
points on the output graph (0.2 mils)
is naturally not distinguishable to the
naked eye.
As noted above, provision is made
so that various mark lengths can be
selected by the operator.
Likewise,
the operator must speci£y number o£
simultaneous plots and plotting rate.
Plotting rate capabilities vary £rom
1000 to about 16 points per second per
curve, allowing great latitude in expanding or contracting the time scale
with the same input tape and paper
speed.
Print Section
A block diagram o£ the print
section is shown in Figure 3: its
essential parts are the recirculating
bu£fer, the character generator, the
column counter and the trace counter.
The heart o£ this section is the
character generator which stores, in
wired £orm, the particular selection
o£ dots in the 7xll dot matrix corresponding to each o£ the 56 characters.
The character generator is divided
into eleven sections corresponding to
the eleven rows in the matrix; the
rows are selected by the trace counter
which advances one step £or each scan
o£ the column counter across all 100
columns. The recirculating bu££er is
synchronized with the column counter
to select, on the basis o£ the IBM
BCD codes stored therein, the proper
group o£ dots £rom the character generator £or each character on each trace.
Thus, during the £irst trace, the topmost portion o£ each character in each
column is placed on the paper with the
process repeating until the £ull character is printed.
Character generator outputs drive
all columns simultaneously with the
column counter being used to determine
the proper column.
Normally characters
are printed in succeeding columns
starting with the £irst, in the order
in which they appear on tape.
Column
counter outputs are, however, also
brought out to a patchboard where
characters may be rearranged in any
desired manner and where provision is
also made to repeat any character once.
This £acility makes it possible to
minimize BCD data on tape during plotting, space codes in e££ect being
supplied by the patchboard.

A special feature o£ the print
section lies in the brute £orce design
o£ the character generator, there being
one speci£ic diode corresponding to a
given dot in a given character. This
approach to the character generator
was the cheapest under the circumstances, but in combination with great
redundancy in the 7xll matrix character,
it has the merit that the loss o£ a
diode is scarcely noticeable even to
the close observer.
Input and Tape Organization

The tape is organized generally
in records, either straight BCD £or
printing only or combined BCD and
Binary £or annotated plotting. The
IBM 36-bit binary word is divided into
three l2-bit groups with 10 each required to speci£y a data point. Control characters are provided on the
tape and indicate how data is to be
interpreted and control its routing
either to plot or print input bu££ers.
A record may include up to 71 data
points and up to 100 BCD characters.
Tape operates at 150 inches per second
with 200 bits per inch.
Plot Section
Since the tape operates startstop in order to provide £lexibility
in the machine as regards paper speed
and plotting rate, then two bu££ers
must be supplied in the plot section
to guarantee the required steady flow
o£ data; in general, one is being
£illed while the other is being emptied.
Circuitry and logic would allow the
processing o£ 10,000 data points per
second; however, tape characteristics
and bu££er size limit the maximum to
about 6000.
Print Section
Two bu££eTs are also provided in
the print section in addition to the
recirculating bu££er discussed above.
1£ the machine were to operate simply
as a printer, these bu££ers would be
unnecessary.
Operation o£ the machine
as a printer-plotter with generality
and ease o£ programming appears to demand the presence o£ the two print input bu££ers: other arrangements were
considered and £ound to place severe
limitations either on the program or
on the per£ormance o£ the machine.

156
4.1
Reliability and Performance
Reliability of the machine has
been excellent. Precise statistics
are available only for a period of 300
hours.
During this period, there has
been but one component failure, a
transistor.
\Vhen the number of components is considered - 9000 transistors, 12,000 diodes, about 40,000
other components - this is quite a
good record.
Likewise, the performance has
been excellent; except for the transistor failure noted above, maintenance has been limited to the routine
care necessary to the proper performance of the tape transport and occasional adjustment of the recorder
mechanism.
Acknowledgments
I wish to acknowledge at this
time the contributions of G. Conklin,
R. Hench, R. Hibbs and C. Spindler of
the General Electric Company. Without their vision and support, this
machine would not have existed.

157

4.1

~ £:] ~
TAPE
'~A~---t CHECK
.~ ~
TIMING

BUFFER
~ INPUT

CONTROL

EVEN PRINT ~
BUFFER

ODD PlOT
BUFFER
....-IIfI~J'--.._

......

ODD PRINT
BUFFER ___---'1~liii0.'-------1

EVEN PLOT
BUFFER

r
PLOT

~REGISTER

~~1""""" CONTROL

MASTER ...__--.a.
,. CONTROL· CHARACTER-----.-~_....._.......
t
GENERATOR
PRINT
a
~ FORMAT
I

PLOT
CONTROL

____

PLOT
DECODER

PRINT DATA

ROUTING

I
STYLUS
PREAMP
I

MULTIPLE

STYLUS

RECORDER
Fig. 1. Block Diagram.

CONTROL

•~
c.n

2
PLOT
INFO

PLOT
DURATION

PLOT
INFO

3
PLOT
INFO

DOD

-0:1

4
PLOT
INFO

PLOT
INFO

r'41---t-I~-----t-l~----~I-t-----.!bt-----~-.f°_---..,
i

~
TYPE 1

L....&>

.lJ)

L.o

r2
I~

L3~2t23t3t-I~-~-27&--17t--28t--18t-~21---lt-'-3bt---20t-J
PRINT
OUTPUT
PRINT
OUTPUT
PRINT
OUTPUT
PRINT
OUTPUT
\ BY TEN}. OUTPUT
ALL STYLI ~ ' "
I
INFO
2
INFO
!
INFO
4
INFO
5
1
COLUMN
2
!
4
5
PRINT DURATION
ENABLE
Fig. 2. Output Circuit.

CLOCK
AND

.....
.....
-

......

CONTROL

RECIRULATING ..
14----~.------------------.
BUFFER
12

,..--I

•

__ 14

TRACE

DECODER

COUNTER 14

•
CHARACTER
GENERATOR

COLUMN COUNTER 14-

•
CHARACTER
77

GATES

II GROUPS OF 7

DECODER

TO COLUMN SELECTION
EITHER DIRECT OR
THROUGH FORMAT
~TCH BOARD

•

TO COLUMN OUTPUT FUPFLOPS OF 100 COLUMNS
Fig. 3. Print Section.

•

.......

CJ1

....... \0

160
4.1

161
4.2
A DESCRIPTION OF THE IBM 7074 SYSTEM
R. R. Bender, D. T. Doody, P. N. Stoughton
Product Development Laboratory, Data Systems Division
International Business Machines Corporation, Poughkeepsie, New York

Summary
A new data processing system, the IBM
7070 1 , was described at the 1958 Eastern Joint
Computer Conference. Recent progress has
resulted in the creation of an expanded family
of 7070 systems, exemplified by the announcement of the IBM 7074 system.
The 7074 represents a dramatic new approach to data processing system growth, and
is the second major step in the 7070 data system
family. It is not an entirely new system, but
rather an improvement within the 7070 framework. It enables a customer whose workload
has outgrown his 7070 equipment to upgrade his
system over a weekend, thus achieving multiplied performance without reprogramming and
without excessive disruption of his operation.

Thruput or job performance considers, in
addition to instruction-execution time, the time
expended in magnetic-tape input/output operations. A typical mix of commercial jobs--ineluding sorting, merging, high and low activityfile maintenance, and editing- -provides the
basis for this comparison.
Floating point performance is measured
on the basis of a typical group of arithmetic and
logical instructiohS encountered in many scientific problems. It is essentially a measure of
internal speed.
Functional Units
Physically, the 7070 family is made up of
the following functional units which are packaged
in IBM standard modular system (SMS) frames:

Specifically, the increased performance
is achieved by use of:
1. A new, high-performance arithmetic
and program unit called the 7104 high-speed
processor.
2. Improved-performance storage units,
the 7301 models 3 and 4, which operate on a
four-J.Lsec cycle instead of the six-J.Lsec cycle
used with the basic 7070.

These units are substituted for their counterparts in the 7070 system.
Compared to a two -channel 7070 system
using 729 IV tape drives, a 7074 of the same
configuration has the following performance
characteristics:
Internal performance on
commercial work

6 x 7070

Thruput or job performance
on commercial work

2 x 7070

Floating point performance
on scientific work

10 x 7070

Internal performance is a mea.-sure of instruction-execution time. It is measured on the
basis of the mix of instructions executed in a
group of programs considered typical of commercial applications.

7070
Arithmetic &
processing unit

7601
(2 modules)

High-speed
processor
Storage, 6 -J.Lsec

7074

7104

7301, 1 & 2

Storage, 4-J.Lsec

7301, 3 & 4

Core control and
power distribution

7602

Basic timing &
control

7600

T ape control unit

7604

Tape transports

729 II or IV

The 7601 arithmetic and processing unit
and the 7104 high-speed processor perform arithmetic, logical, and other stored-program operations under the control of a single -address type
of instruction. Some other features are: ninetynine indexing words; variable field length by the
use of field definition; automatic block transmission of data within core storage; automatic
priority processing; extensive checking; and
simultaneous read, write, and compute.

162
4.2
The 7301 storage units are available in
models of 5000 or 9990 words. They provide
parallel access to ten digits (one computer word)
at each storage reference.
The 1604 tape -control units provide for
transmission of data between tape storage units
and core storage. Two independent data channels can be provided by each 7604 unit.
The 729 tape transports are available in
two models. Model II can operate at data rates
of 15, 000 and 41,000 six-bit characters per
second. Model IV can operate at data rates of
22,000 and 62,500 six-bit characters per second.
Up to forty tape transports, in any combination
of models, are available on the system.

Some example s are:
7070

7074

One -digit true add

48 J.Lsec

10 J.Lsec

Ten-digit true add

72 J.Lsec

10 J.Lsec

924 J.Lsec

56 J.Lsec

Conditional branch

36 J.Lsec

6 J.Lsec

Unconditional branch

24 J.Lsec

4 J.Lsec

212 J.Lsec

16 J.Lsec

1019 J.Lsec

60 J.Lsec

Multiply (IO-digit
multiplier)

Floating add
Floating multiply

The above listing is by no means exhaustive.
Many other devices -- including punched-card
devices, printers, and manual inquiry stations -are also available.
These units are the building blocks of the
IBM 7070 family. Proper selection of processor,
memory, and tape drives provides the ability to
tailor a data processing system to a wider variety
of customer requirements (both commercial and
scientific) than ever before possible.
System Growth
The IBM 7074 system may be ordered directly from the factory, or it may be "grown"
from a 7070 in the customer's office. The necessary changes can be made by a team of field
engineers over a weekend.
Referring to Figure 1, the 7104 high-speed
processor is substituted for the two 7601 modules
which are removed and returned to the factory.
The 7301 storage unit is converted from a
six-J.Lsec cycle to a four-J.Lsec cycle by a change
to high-speed circuitry.
One slide, containing storage controls, is
removed from the 7602 core control unit and returned to the factory. New storage-control circuits are provided in the high-speed processor.
Program Compatibility
The 7104 high-speed processor uses the
same instruction set as the 7601, although it
processes individual instructions three to twenty
times faster.

Since the instruction formats are identical,
programs written for the 7070 may be used on
the 7074 without change. Furthermore, they
will operate at full efficiency on the 7074.
This compatibility is important for rapid
and simple change -over from 7070 to 7~74. In
addition, all 7074 customers -- newcomers as
well as those changing over from the 7070 -have at their disposal the entire 7070 program
library of the GUIDE organization, and IBM
applied programs for the 7070.
Processor Organization
The 7104 high-speed processor, like the
7601 'arithmetic and processing unit, operates
on the basis of a word of ten decimal digits and
sign. Coding is 2 of 5, so that a word consists
of 53 bits. Sign is plus, minus, or alpha and is
represented by three bits in 2 of 3 code. Alphanumeric information is represented by two decimal digits, so that an alphanumeric word contains
five characters, while a numeric word contains
ten digits.
When written on magnetic tape, an alphanumeric word fills five six-bit characters. Numeric words are written as ten six-bit characters
except that up to five high-order zeros are eliminated. This makes for very high tape efficiency.
The 7104 high-speed processor differs
from the 7601 arithmetic and processing unit in
that the 7601 performs arithmetic operations in
a serial-by-decimal-digit manner while the 7104
performs full-word parallel arithmetic.

163

4.2
In the 7601 (see Figure 2) each digit is
moved through the adder in one four-fJ.sec, cycle
and is stored back in the arithmetic register on
the following cycle, during which the next digit
is moved through the adder. A full ten-digit add
requires eleven cycles or 44 fJ.sec for completion
(assuming that recomplementing is not required).
To this must be added instruction and operand
access time as well as indexing time if required.
Total time for a ten-digit true add (not indexed)
is 72 fJ.Sec.
In the 7104 (see Figure 3) the full-word
adder cycle requires two fJ.sec for completion.
Instruction and operand access time results in
a total time of ten fJ.sec for the nonindexed add
instruction. This time is valid for any field
size up to ten digits. Thus, add speed has been
improved from three to seven times, depending
upon field size.
Items of interest are:

1. Skew registers which provide the functions of field control and shift.
2. Three accumulators which provide speed
in floating point operations.
3. Validity checking on all buses.
4. Complete program compatibility with
7070 (uses 7070 instruction set).
The information bl,ls is one computer -word
wide (ten decimal digits and sign 53 bits). The
address bus is four digits (20 bits) wide, and the
arithmetio buses are eleven decimal digits wide.

Circuits and Packaging
The high arithmetic speeds are made possible by the use of saturating -drift -transistor
NOR circuits. Packaging is accomplished. in a
new package known as the SMS twin card, which
provides over three times the density of logical
elements achieved in the 7601 processor of the
IBM 7070. This density permits the 7104 to
contain in one module all of the logic previously
packaged in two and one-half modules.
Figure 4 compares the new SMS twin card
with the SMS single card used in the 7601. Up
to .44 transistors may be packaged on one twin
card as compared to a maximum of eleven on the
single card. The use of NOR circuits further
increases the logical density in the SMS twincard system. Vertically mounted components
of the twin cards provide more efficient cooling.
The component tips are welded to the bronze

support clips at the upper end, and are soldered
to the printed wiring of the card at the lower end.
The bronze support clips contribute to cooling by
providing a heat -sink effect; these clips also provide an additional dimension of modularity for
automated production and for field repair of cards.
Support-clip sections can be stocked and card
repairs made in the field by replacement of clips,
thus contributing to more economical maintenance.
Figure 5 shows additional details of the SMS
twin card.
Cards are mounted in an IBM standard
modular system (SMS) frame, which contains
two slides, each composed of two pages. Each
page contains four chassis, each of which in turn
can contain 100 SMS twin cards.
Figure 6 shows an SMS sliding-gate module,
covered. One such module contains the 7104
high-speed processing unit, and measures 29 1/2
in. wide by 56 in. deep by 69 in. tall.
The sliding gates pullout toward the front
as shown in Figure 7.
Each gate opens into two pages in which
are mounted the SMS single or double cards. The
pages or gates are accessible for service from
both sides. Covers over the cards contain the
flow of cooling air.
Figure 8 depicts the organization of a page
or gate of the module. The four chassis, each
of which can contain 100 SMS double or 200 SMS
single cards and a number of edge connectors,
are shown from the rear or panel-wiring side.
It is the SMS system which makes possible
the modular growth from the 7070 to the 7074.
Replacement of one or more of these frames with
functionally similar units of higher performance
is possible without re -engineering every unit of
the system.

References

1. For a description of the IBM 7070,
see lIThe IBM 7070 Data Processing
System It presented by Robert W.
Avery, Stephen H. Blackford, and
James A. McDonnell at the Eastern
Joint Computer Conference, December 1958.

oj:>.

7070 SYSTEM

7600
TIMING

•
0\
t'V oj:>.

7602
POWER
DIST
CORE
CONTROL

7601 NO.1
7301
STORAGE
(6 p.sec)

7601 NO.2
7604
TAPE
CONTROL

A AND P
UNIT

CORE
CTRL

A AND P
UNIT

CONVERT

7600
TIMING

7602
POWER
DIST

7301
STORAGE
(4 posec)

...

7104
HIGH
SPEED
PROCESSOR
-

Fig. 1. System growth.

-----~

7604
TAPE
CONTROL

...

---

- --

RETURN
TO
FACTORY

FROM
FACTORY

INFORMATION

~ 10

BUS 10 DIGITS

A •

STORAGE

ARITHMETIC BUS 10 DIGITS
4 •

••

~ t

ARITH. REG.
INSTR. REG.

:CANNER

AUX. REG.

ACC. I

..
.....

.SINGLE!
DIGIT
ADDER
,

ADDRESS BUS 4 DIGITS

, r
ACC.2

~
....

ACC.3

ONE DIGIT
Fig. 2. 7070 information flow.

~I-'

•

~CJ1

I-'

•
0\
t-:l 0\

ARITHMETIC BUS II DIGITS
~

• J"

SKEW
ARITH. REG.I

AUX. REG. I II
~~

il
~~

10 DIG.

A~D~R

I REG.
~~

I I

ACC.2

SKEW

1r i r

kibl,l

IIII

eLJ
~

INFORMATION BUS 10 DIGITS
~~

TO STORAGE

I COUNTER

;!f

ADDRESS BUS 4 DIGITS

Fig. 3. 7074 information flow.

S BUS II DIGITS

ACC.3

• a

167

4.2

Fig. 4. SMS twin card and SMS single card.

168

4.2

Fig. S. SMS twin card detail.

169
4.2

Fig. 6. SMS functional module.

170

4.2

Fig. 7. SMS module with slide out.

171
4.2

Fig. 8. SMS module page - rear view.

173
4.3

THE RCA 601 SYSTEM DESIGN
A. T. Ling and K. Kozarsky

Electronic Data Processing Division
Radio Corporation of America
Camden, New Jersey

One of the differences found among computer systems is whether emphasis is on word orientation or on
character orientation. Pertinent design considerations
not only include memory depth, but also capability for
handling symbol-controlled operations and relative
speeds of word and character operations. Emphasis
placed on either word or character orientation tends
to dictate a principal area of effective application. An
important objective of the RCA 601 System is to perform efficiently over a very wide application base and
economically combine the speed of parallel word processing with the logical flexibility of variable character
operations.
The RCA 601 System is a generiC name which,
properly speaking, refers to a Class of systems. This
is due to a very generalized design approach which will
be illustrated by the system logic design description
of the RCA 601 System in the following discussion.
Specific elements have been selected from numerous
possibilities to constitute the presently offered product
line. The objective here is far from academic in that
this approach provides, first, an exceptional ability
for custom fitting of system elements for a specific
user. Second, it tends to delay the inevitable onset of
obsolescence by permitting rev lsion of systems elements to increase performance or modify the orientation of the system according to the contemporaryfashion in data processing.
These, of course, are supplementary to the common objective of commercially available systems, a
cost-to-performance ratio in conformity with the vintage of the hardware. The host of sagacious decisions
required in the selection of such appropriate components as tranSistors, packaging, and memory at optimum points of their cost vs. speed considerations,
will not be elaborated but can be assumed by the
reader.

THE RCA 601 SYSTEM

The RCA 601 System stresses a generalized system logic design in the computer. The main frame is
a fast processing unit which includes a 1. 5-microsecond memory. Its design features provisions for
uniting other system elements into an integrated system by means of standard interfaces. A unique modular packaging concept is used for these system elements
to allow efficient and flexible system combinations. A
system diagram is shown in Figure 1. The all-solidstate elements of the computer system include a main
frame processing llnit, memory units, an arithmetic
unit, and transfer channels. The main frame processing unit includes a 56-bit word memory module, a fast
basic arithmetic unit, an input-output control, and a
console transfer channel. Facilities for operating any

combination of other elements comprising a single system are provided by three channels - the memory
channel, the control channel, and the input-output
channel.

CONTROL
CHANNEL

HIGH SPEED
ARITHMETIC
UNIT

-----------,

I
I

ARITHMETIC
UNIT
MEMORY
MODULE

BASIC
CONTROL
UNIT
INPUT
OUTPUT
CONTROL

1..,-----

CONSOLE
TRANSFER
CHANNEL

I
I
I
I

I
I
I

________ J

MAIN FRAME

FIGURE 1. RCA 601 SYSTj:M DIAGRAM

Additional memory modules via the memory channel are available to operate as asynchronous, independent units. In the RCA 601 System, asynchronism
means that the occurrence of an event begins upon fulfillment of a set of machine status requirements, and
terminates as soon as its own requirements are fulfilled. A high-speed arithmetic unit can be added via
the control channel to comprise an expanded computer.
This unit operates at higher speeds than the main frame
arithmetic unit and performs full-word-binary and decimal-floating-point arithmetic.
Remaining elements consist of transfer channels
which are links to peripheral devices via the inputoutput channel. Peripheral devices are available in
card readers and punches, high-speed printers, paper
tape readers and punches, and magnetic tapes. Flexible combinations of these devices within very broad
constraints may be selected to operate on-line with the

174
4.3
system. Two sets of tape stations are native to the
RCA 601 System - providing the choice of 100-kc. or
180-kc. decimal digit nominal transfer rates.

ELEMENTARY OPERATION "TRANSFER"
TIME~

St.p I Sot Up (SI)

St.p 2 Control Bus (C,)
St.p 3 Data Transmission (01, Tt)

HARDWARE FEATURES

The generalized system logic design includes
unique features such as elementary operation mechanization, an asynchronous control system, a generalized
arithmetic unit transfer channel input-output control,
and an asynchronous memory system.
A unique feature of the 601 system is the manner
in which its instructions are implemented.. Instructions
are broken down into small component parts called
"elementary operations". A sequence of elementary
operations comstitutes the logical steps comprising a
machine instruction; thus, the elementary operation
corresponds to an instruction in much the same manner
as an instruction corresponds to a routine. Instructions
are performed by evoking these elementary operation
sequences and executing them one at a time. Thus, by
simply changing or adding elementary operation sequences,
the instruction complement may be added to or changed.
This open-ended design of instruction complement enables the customer to adopt new techniques in his computer operation as they are needed.
Asynchronism in operation timing is a convenient
tool for modular variability in which a configuration of
system elements is not fixed. The control system,
arithmetic unit, and data transmission employ this teclrnique. To illustrate this feature, let the succ'essive
elementary operations, "transfer" and "set", be considered. The "transfer" elementary operation calls
for the transfer of the information from one specified
register to another within the computer. The "set"
elementary operation transfers data from a memory
location into a specified register. As shown in an exaggerated form in Figure 2, the "transfer" operation
involves steps 1, 2, 3, and 4. The asynchronous aspect of the control system is illustrated between steps
1 and 2 and the occurrence of step 4. The "transfer"
elementary operation terminates just after the data
transmission (step 3) has started so that the next operation may begin. Thus, steps 5 and 6, which are the
set up and memory addressing for the next "set" operation, ~)Ver1ap with the relatively long transmission. The
asynchronous aspect of data transmission via the data
busses is indicated by steps 3, 6, and 8. There is a
unique detection circuit on the busses to detect echoes
from the receiver register and terminate the transfer
by the generation of a terminate pulse, T. In this way,
data transmission time depends on the physical configuration of the source and sinks involved. Note that
steps 6 and 3 overlap in time because separate busses
are involved; if the same bus is used then step 6 should
be interlocked to prevent its initiation until the T signal
is generated.
The RCA 601 System memory storage employs a
word format, even though the data format is extremely
flexible. The majority of data manipulation involves
logic with certain arithmetic properties. An efficient
and compact design is made by generalizing the basic
arithmetic unit to include data handling functions as
well as arithmetic operations. Operands that can be

ELEMENTARY OPERATION "SET"

StopS Sot Up (S:zl
St.p 6 Add,. .. Memory (A , T';

St.p 8 Doto Transmission (0], 13>
Stop 9 End(E2)

FIGURE 2. ILLUSTRATION OF ASYNCHRONOUS OPERATION ANO OVERLAP

manipulated may be in character, half-word, or word
format. Wired-in arithmetic operations include the
full range of add ,subtract ,multiply , multiply and accumulate, and divide, for fixed-point decimal operands
and for the majority of fixed-point binary operands.
By the addition of a high-speed arithmetic unit, basic
system speeds of certain operations are increased and
floating-point arithmetic is added to the instruction
complement. A further feature of the basic arithmetic
unit design is its built-in ability to accommodate variable size characters. Four different character sizes,
namely lengths of 3, 4, 6, and 8 bits, may be directly
addressed and manipulated. A character length register is used to deSignate the size of character in all
character operations. This register can be loaded
and re-Ioaded with appropriate deSignators during a
program by half-word set-register instructions. Operations other than character handling operations are
not affected by this register. The variable size character handling ability together with the general symbol
reoognition feature allows the RCA 601 System to handle a large variety of codes. A block diagram of the
basic arithmetic unit is shown in Figure 3. The adder
operation is an asynchronous circuit with respect to
carry propagation. That is, as soon as the carry
propagation subsides, the adder operation is terminated.
Peripheral devices in the RCA 601 System are
handled by control buffer packages called transfer
channels. These transfer channels work on-line with
the input-output control of the main frame by an. automatic instruction interrupt technique. The inputoutput channel is a general, standardized interface.
Thus, looking out from the input-output control, proper operation is maintained, regardless of the number
or the complement of the transfer channels in operation. This allows a generous flexibility in the makeup as well as the size of the input-output system. This
transfer channel concept, coupled with a general, allpurpose input-output instruction complement, makes
an efficient and economical way of coping with future
development of peripheral and custom devices. The
transfer channels are logically complete for independent and simultaneous operation with the main frame.
Additions of transfer channels mean potential additiqns
in amounts of simultaneity. The amount of simultaneity is automatically regulated by a built-in artificial,
simple calculation called speed-weight. The transfer

175
4.3
not to affect proper performance of these high-speed
circuits, wiring techniques become complex. Wire
lengths must be kept to a minimum. This is particularly true in the main frame processing unit. High
transistor packing density is specified in step with the
contemporary state of mechanical component packaging.
Despite preventative maintenance, computers occasionally become inoperative due to component or mechanical failure. Ready access directly to the internal construction means easier servicing with a minimum loss of
costly computer time. A basic requirement achieved in
the RCA 601 System package is that both the wiring side
and the plug-in side may be opened for serviCing without
affecting the operating status of the computer. Means
have been designed to make it easy to tap any point on
this wiring for observation.

FIGURf 3. BASIC ARITHMETIC UNIT BLOCK DIAGRAM

channel concept also makes it possible for the operating console to operate interpretively, and communi-.
cate with the computer without having to stop operatIOn.
A key feature in the RCA 601 System is the highspeed memory. Each 56-bit word is accessed in 0.9
microseconds and the complete address-read-write
cycle is l.5 microseconds. The memory operation is
logically controlled and asynchronous. Separate commands to operate the three memory logical steps (address, read-out, and write-in) are directed from the
control system. Thus, its operation is integrated
with the control system. Overlapped operation is possible when more than one module is present. Generally three modes of operation can be accomplished:
1. Address and read-out.

2. Address and write-in.
3. Address, read-out and write-in.
The design approach here is basically conservative. The application of commercially existing components and proven techniques to solve the problem of
this advanced equipment design have been used rather
than depending on the development of new compon~n~s.
The design objective was to make the cost competitive
with presently available memory systems that are up
to eight times slower. The design stresses were on
cost, reliability, and simplicity, taking into account
the expected maintenance problem. The storage elements used are magnetic cores. The core size chosen
has an I. D. of 18 mils; an O. D. of 30 mils, and a
thickness of 10 mils. This small size is chosen for
performance as well as for compactness of mechanical packaging. The circuit design simplifies the wiring complexity that is required in most magnetic core
memories.
The product design of high-speed computers
must deal with problems arising from multitudes of
short pulses with extremely fast rise times. In order

Transfer channels, additional memory units, and
future expansion units are packaged in modules which
are installed in universal racks. A unique channeljumper technique is used. These channel-jumper cables thread through the entire system in a manner illustrated in Figure 1.

PROGRAMMING FEATURES

One vogue in the majority of recently-announced
computing systems is the relative brevity of program
statement contrasted to systems currently in common
use. Factors contributing to these concise programs
include powerful, well-integrated order codes, complex address-modification capability, flexible addressing schemes and variable instruction length.
Provision for variable length data has been made
in early electronic machines and the similar motivations of efficient memory utilization and the elimination of "filler" material have extended this to include,
also, those bits, in memory, which direct the control
unit of the machine. In the RCA 601 System, "variable instruction length" means that instructions may
be either 1, 2, 3, or 4 half-words in length. 1 A unit
data length in the RCA 601 System is either a word
(or half-word) or a character. One of these, the halfword of 24 information bits, is the unit length for
instructions.
Generally an instruction half-word is an operation half-word that may have as many as three address
half-words appended to it. A distinction has to be
made between the number of addresses contained in an
instruction and the number of addresses utilized as an
integral part of the execution of an instruction. Each
instruction type utilizes a fixed number of these address registers, e. g., a MOVE will utilize two address
registers, MULTIPLY utilizes three, a DO instruction
utilizes none at all, etc., and frequently those are the
number of addresses written in that instruction. However, the address registers utilized by an instruction
have their contents augmented by one data-length unit.
This value of the address register is often the appropriate value of the register for the operation of the
next instruction. In particular, this occurs when the

1Input-output instructions are the exception to this
statement.

176
43

data of interest is stored in contiguous arrays in memory. In such a case, when an address register contains the desired value, then that address need not be
written in the program statement. Three bits termed
"assumed bits" in the operation half-word of an instruction specify whether or not address half-words
for each of three address registers are written following the operation half-word. Thus, a lesser or a
greater number of addresses than used by the instruction may be written. When fewer addresses are used,
the remaining addresses are said to be "assumed";
when additional addresses are used, they merelycause
the address registers to become loaded. The stepping
of the address registers in conjunction with assumed
addressing is really equivalent to automatic address
modification by unity, with, however, several advantages over address modifiers: no address modifiers
are used up for this purpose; no time is lost to accomplish the address modification; no space is required in
the program for the address; and no time is required
to access the address.
Another place in which explicit addresses are not
written occurs when the accumulator is being used in
arithmetic operations. Again three bits in the operation half-word specify whether any or all ofthe operands
refer to the contents of the accumulator. Thus, a single half-word suffices to instruct the accumulator to
double itself, an ADD instruction with all three addresses assumed, and the accumulator specified as
each of the operands. Figure 4 illustrates some of
these features.
A unique and substantial addressing flexibility is
incorporated in the address half-word. The 24-bits of
this half-word, shown in Figure 5, are divided as follows: an address part of 19 bits; 15 for addressing
215 words; a 16th to address half-words; and three
additional bits to address characters within the halfword. The 20th bit is used to designate indirect addressing. The four remaining bits are used to address
any of eight address modifiers.

24 BITS

m mrnm

ill

Increment

Address
Modifier

m························~

x ........................

xxx

mJ
xxx

(15)
Word Address
Indlrftl

Address

Haff·Word
Address

Choracter
Address
or
Control
Sits

of
Indirect
Addressmg

or
Address
Modlflcahon

FIGURE 5. ADDRESS HALF·WORD

Seven of the address modifiers are a full word in
length, where the left half-word is the value part applied to an address when selected, and the right halfword is an increment part selectively added to the
value part. This selectivity is gained by providing two
addresses for each address modifier, one of which
causes an automatic incrementing to take place. This
accounts for the generous use of four bits to select
eight address modifiers.
Applying both address modification and indirect
addressing to an address would normally require an
arbitrary order of precedence. However, in the RCA
601 System whenever an indirect address is specified,
it selects another half-word in which is contained
another address. Therefore, the three bits used for
character addressing in this case, might be superfluous, but are used instead for the following:
1. To defer application of the address modifier
with the indirect address to the direct address.
This can permit dual address modification
on the direct address.

2. To inhibit address modification on the direct
level.
3. To inhibit subsequent indirect addressing.
EX. h 1;-'

DO n

B. ASSUME!)

C' ASSUMED
IN CONSECUTIVE WORDS
ADD

A. ASSUMED

C ACCUMULATOR
TOTAL PROGRAM> THREE HALF·WORDS
DO n

C' ASSUMED

MULTI ACC Ju ASSUMED
B, ASSUMED
C' ACCUMULATOR
TDT AL PROGRAM> FOUR HALF·WORDS

DO n

A: ASSUMED

B' ASSUMED
C. ASSUMED

Figure 6 illustrates the possibilities with this
octal digit for the case of only a single level of indirect
addressing.
Indirect addressing and the flexible application
of address modifiers provide considerable facility in
working with address lists. Lists of addresses can
be generated by magnetic tape read instructions which
list the addresses of special symbols (designated by
the programmer) in memory, as well as the information itself. It is then possible to eliminate much data
movement by utilizing the address lists.

MUL TIPLV B' ACCUMULATOR

ACCUMULATOR

TOTAL PROGRAM> THREE HALF·WORDS

FIGURE 4. ASSUMED ADDRESSING AND STEPPING OF ADDRESS REGISTERS

Efficient data encoding is carried a step further
in the character handling capability ,of the RCA 601
System. It has been mentioned that four different
character sizes (lengths of 3,4, 6 and 8 bits) may be
directly addressed and manipulated. Thus, sequences
of decimal digits are normally handled in four-bit
characters, alphanumeric data in six bit characters,
etc., providing efficient tape and memory storage.

177

4.3

BITS OF ADDRESS HALF·WORD

_4_

-.!.. J! 1-

ADDRESS k

AMI

ADDRESS B:

NJ.2

ADDRESS B+(AMI):

AM3

where linkages between programs occur such as to
permit maintenance of input-output rates.
Figures 7 and 8 present a brief description of the
characteristics and representative times of the current
RCA 603 Computer in the RCA 601 System.

d PERMITS:
INDIRECT ADDRESS TO BE

1)B
OR 2) B+ (AMI)

DIRECT ADDRESS TO BE

I) C+ (AM2)

2) C+ (AM1)
3) C+ (NJ.I) + (AM2)
OR 1) D+ (AM3)
2) D+ (AMI)
3) D+ (AMI) + (AM3)

MEMORY MODULE SIZE

8192 WORDS, 56 BITS EACH
UP TO 4 MODULES

OPERATION TIMES·

MICROSECONDS

A + B-C, l·WORD
ACCl'MULATOR

6.6

+ B-ACCUMULATOR, I-WORD DECIMAL

3,2

A x B-C, l·WORD DECIMAL (NO ZEROS)

69.4

A -B, 10 WORDS

32.0

A-B,6 6-BIT CHARACTERS

15.1

A-B,6 4-BIT CHARACTERS

11.3

BRANCH

0.5

1.5 to 3.0*

INSTRUCTION ACCESS AND INTERPRETATION TIMES
FIGURE 6. CONTROL OF INDIRECT ADDRESSING AND ADDRESS MODIFICATION
ACCESS

2.5 to 7.0*

INDIRECT ADDRESSING

1.7

INDEXING

2.9 to 3.5*

INPUT·OUTPUT CONTROLS

The RCA 601 System features sets of indicators
to provide a parallel decision making ability concurrently with the running program. Conditions sensed
include: arithmetic underflow and overflow; error
conditions; unsuccessful scanning operation; result
positive, negative or zero; and a binary indicator specifying such information as whether a logical connective
yielded zero. A programmer-set mask is associated
with each indicator to permit or inhibit an automatic
branch whenever the condition is encountered. This
feature permits minimizing the length of repetitive
loops by eliminating, each time, expllcit senSing for
rare conditions.

UP TO 16 SIMULTANEOUS INPUT-OUTPUT OPERATIONS

* DEPENDS ON PROGRAM SEQUENCE

FIGURE 7. MAIN FRAME COMPUTER

CARDREAD

600 CARDS PER MINUTE

PUNCH

100 CARDS PER MINUTE

PAPER TAPE

When one of these automatic jumps does occur,
storing of relevant registers takes place automatically,
assuring ability to restore the status of the machine
whenever control is returned to the interrupted point.
In particular, one of the conditions which will cause
an automatic jump to occur is the termination of an
input-output operation. The format of an input-output
instruction differs from the rest of the order code, including up to 5 address half-words. One of these address half-words contains an address to which control
is to be transferred when the operation is complete.
This permits an effective multi-programming scheme,

READ

1000 CHARACTERS PER SECOND

PUNCH

300 CHARACTERS PER SECOND

PRINTER
120 CHARACURS PER LINE

600 LINES PER MINUTE

MAGNETIC TAPE
lS0-KC DECIMAL DIGIT RATE
100-KC DECIMAL DIGIT RATE
SO-KC DECIMAL DIGIT RATE

FIGURE S. PERIPHERAL DEVICES

179
4.4
ASSOCIATIVE SELF-SORTING MEMORY
Robert R. Seeber, Jr.
Product Development Laboratory, Data Systems Division
International Business Machines Corporation
Poughkeepsie, New York

Summary
A cryogenic associative memory is proposed
in which the status of a memory word is determined, with respect to an interrogating word,
on a high, low or equal basis. Thus the bracketing pair of words is determined, allowing the
interrogating word to be inserted between them,
a "dummy" register holding it temporarily. A
double-shuffle operation moves the other words
to make room for the new word in proper sequence.
Introduction
One of the major problems that occurs in the
use of a computer, particularly in business
uses, lies in the sorting of data. The importance of this problem can be judged on the
basis of the hundre~s of pages of description
of sorting routines that have been written.
Programs are in some cases many thousands
of instructions in length. Heretofore, the
attack on the sorting problem has been almost
entirely on the programming level. In this
paper is proposed a memory system organization to achieve sorting within the memory.
By the use of associative memory principles,
extended to facilitate sorting, a new approach
to sorting is developed. Words to be sorted
enter memory in random order but each is
placed within memory in its proper relationship to previously sorted words.
Associative Memory
Associative memory may be defined as memory in which a word of data is retrieved on the
basis of part or all of the data content of the
word. Words are stored in vacant registers
and subsequently are recovered not by naming
the location of a register but rather by naming
a portion of the word as an identifier. This
identifier or tag may in some cases be a portion added to the data word for the identification purpose. However, in the more general
case, which we call a fully associative memory, the data word can be retrieved by using
selected portions of the word itself as its identifier; in this case, the remaining portions are
masked out. Thus the knowledge of the exact

storage location in the physical sense may be
completely immaterial to the operation. A
more detailed explanation of a simple associative memory was given in an earlier paper. 1
Sorting with an Associative Memory
The use of an associative memory reduces
somewhat the need for sorting, particularly
in the case where sorting is used to provide
means for locating particular words by their
ordered identifier or argument, as is usual
in table look-up operations. Since an associative memory allows direct access by these
identifiers, sorting for these purposes is not
necessary. But for other purposes, particularly for sorting output lists, sorting is required. This may be done by an associative
memory by arranging to retrieve in order all
possible combinations of the given identifier.
For example, if we have a 3-decimal digit
identifier and want to retrieve 965 different
data words identified by this 3-digit code, we
can set up a counter to provide us with all
combinations running from 000 through 999
to act as identifiers for the 965 words. The
efficiency will be quite high, requiring 1000
retrieval tries to produce the actual 965 retrievals in order. However, this system
breaks down in the more frequent case of the
identifier not so densely. coded. For example,
a 10-decimal digit part number code may have
only a few thousand different parts which would
require 10 10 retrieval tries to recover in order.
Since sparsely populated codes seem to be the
more general rule, particularly in business
problems, a means for actually sorting the
words would be very desirable.
Proposed System
In a general associative memory a simultaneous comparison is made between an entry word
and all of the word registers in the memory to
determine the match or non-match status of
each word. This is done by providing comparison circuits between the entry register and
each of the word registers such that an equal
or unequal status is determined. This has
previously been done for the purpose of retrieving a matched word from memory. For

180
4.4

writing into memory in order, we now add the
requirement that these comparison circuits
be extended to provide a comparison indication on high, low or equal for each of the word
registers. This then will supply us with enough
information so that we can determine where
within a previously sorted sequence a newword
should be inserted. Additional registers called
dummy registers are supplied between each of
the word registers. This allows an incoming
word to be placed between the proper two words
in memory; then, by a double-shuffle transfer
cycle, the words in memory are shuffled to
ente r the new wo rd in to its prope r plac e.
Figure 1 is a block diagram showing this
arrangement. At the top there is an entry
register where data words are coming infrom
some other portion of the computing system.
Comparison circuits from this entry register
extend through all of the word registers and
each of the word registers supplies indication
as to whether it is low, high or equal to the
word in the entry register. From this information, the dummy register lying between
the two word registers which bracket the word
in the entry register can be selected and the
word then can be transferred from the entry
register to that dummy register. On this
same half cycle, all the words in word registers above the selected dummy register move
up to the respective dummy registers immediately above each of those word registers.
On the next half cycle, while a new word is
entering the entry register, the words in dummy registers move up to word registers immediately above those dummy registers, thus
leaving the words in memory again in word
registers in proper order including that word
just entered.
Means are provided for exiting one word from
dummy register 1, that is, the forward exit
register, as the memory fills up. That is, as
the memory fills up, earlier words are pushed
out the top. In this case, the echo register
retains the information of the word just exited.
Another mode of operation is provided so that
words coming in through the entry register
may be accepted in inversely sorted order.
In this case, as the registers fill up, words
are pushed out the bottom through the backward exit register; this inverse function may
be useful in handling partly sorted blocks of
words read backwards from a tape on which
data has first been stored in the normal forward order. This operation may reduce the
need for re-winding operations when tapes are
used in conjunction with this sorting memory.

Sorting Example
The chart of Figure 2 shows the successive
cycles of the operation of sorting 21 different
words of which the sorting identifiers are
shown on the entry line. It is assumed that
the memory for this example has 5 word registers, WI through W5, and 6 dummy registers,
Dl through D6. The two-digit identifier has a
bar over it when the word has just arrived at
the location so indicated. A code with no bar
indicates that the word is still present at that
location but has been moved elsewhere, i. e. ,
this is a "shadow" word. Where a bar appears
under an identifier, this indicates that the word
has not been moved on that cycle but has been
previously moved to that location.

Thus, it maybe seen in Figure 2 that the number 29 is placed in the entry register during
the A portion of cycle 1. During the B portion
of cycle 1, the number 29 is transferred to
dummy register W + 1. During the A part of
cycle 2, the number 1 is placed in the entry
register and the number 29 is transferred
from dummy register W + 1 into word register
W, where in this instance of illustration, W
equals 5. During the B part of the second
cycle, the 1 is transferred into dummy register W where W is equal to 5 in tJ:1is instance,
and the number 29 is transferred from dummy
register 6 into word register 5. Since the number 1 in the entry register was less than the
number 29, it will be observed that the number
1 was placed nearer the top of the column of
registers. During the A portion of cycle 3,
the number 44 is placed in the entry register,
the number 1 is transferred from dummy
register 5 to word register 4, and the number
29 remains in word register 5, the image being in dummy register 6. During the B portion
of cycle 3, the number 44 is moved into dummy
register 6 replacing the image 29, the number
29 is moved into dummy register 5 and the
number 1 is moved from word register 4 into
dummy register 4. The first three cycles have
illustrated the cases where the number in the
entry register was less than the numbers stored
in memory and the other instance where the word
in the entry register was greater than those
stored in memory. The next example of cycle
4 concerns merging a number among those previously stored.

In the A part of cycle 4, the number 10 is
placed in the entry register, 1 is moved to
word register 3, 29 is moved to word register
4, and 44 is moved to word register 5, thus

181
4.4
making available the vacated dummy registers.
During the B part of cycle 4, the number 10 is
inserted in dummy register 4 and the number
1 is moved from word register 3 into dummy
register 3. In this manner, a word is merged
with those in memory.
Cycle 7 illustrates the overflow of a word to
the output bus; cycle 11 illustrates the start of
another block of words at the end of memory.

Cryotron Circuits
When cryotron circuits are available, they
would appear to have ideal properties for such
a memory. It should be noted that in the selfsorting memory, as in other associative memories, there is a great deal of distributed logic.
The cryotron is a single element which can be
used for both storage and logical purposes.
An implementation of the self-sorting memory
in single-crossing, thin-film cryotrons is proposed. Cryotron circuits have previously been
described by Dudley Buck. 2 Here we use a
simplified symbolism, a gate being shown by a
semi-circle with its diameter lying along the
gate line and the corresponding control wire at
right angles to the gate wire and bisecting the
semi-circle. Figure 3 is the configuration
for a flip-flop with read-in and read-out circuits employing this symbol.

The top current source (denoted by a "+")
splits into two paths, only one of which is
superconductive at a time. If the left path is
conducting, the flip-flop is said to be "on" or
contain a "1 "; if the right path is conducting,
the flip-flop is "off" or contains a "0." The
feedback action of the flip-flop is accomplished
by the top or bottom c ryotron, depending on
whether the flip-flop contains a "0" or a "1."
If it contains a "Ill the left path of the flipflop is conducting. This current through the
lower cryotron control makes the right path
resistive and keeps the current flowing in the
left path. Similar action takes place at the
top cryotron when the right-hand path is conducting.
Assume that we have a 110" in the flip-flop,
and we want to change its state, that is, read
in a "1." We cause a current flow through
the control path of the "read-in 1" cryotron,
making that cryotron resistive. Since both
the right and left paths of the flip-flop are
now resistive, the current divides in half.
When the current through each path falls near

the half point, neither the upper nor the lower
feedback cryotron is resistive. This leaves
the "read-in 1" cryotron as the only resistive element, forcing all the current to flow
through the left-hand path and making the
lower cryotron resistive. The flip-flop has
now reached a stable state in the "111 or "on"
condition, and the "read-in 1" current can be
removed. Similarly, we can change back to
an "offll condition by applying a current
through the "read-in 011 cryotron.
The read-out is accomplished by completing
a circuit from the read-out current source
through one of the read-out cryotrons and to
the output device. If we assume that the flipflop is in the 110" state, current will be flowing through the right path and through the
control path of the "read-out 111 cryotron,
making that cryotron resistive. Current then
flows through the superconducting "read-outO"
cryotron gate to the output device, where a "0"
will be sensed. The circuit is similar through
the "read-out 1" cryotron when the flip-flop
contains a "1. 11

C ryotron Bit Po si tion
The heart of the memory system lies in the
data bIt position shown in Figure 4. In this
figure a portion of a data bit for word register
W -lis shown near the top of the figure and the
complementary portion for word register W is
shown near the bottom of the figure. In between is the flip-flop for the dummy register
lying between these two word registers. At
the top of the drawing there are provided readout and read-in circuits for going from or to
that word register to or from the dummy register immediately below. In the dummy register
flip-flops, there are shown corresponding readin and read-out circuits for transfer between
the dummy register and the word register above
or below it. There is also shown the select
circuit which provides for the storing in this
dummy register of a data word coming from the
entry register.
For word register W there are shown entry and
exit transfer circuits for coming from or going
to the dummy register above it. Next is amatch
circuit which controls the exit of data from this
word register when it is a matched register for
the read-out of data in the normal associative
manner. The last lines on the figure show the
equal, low and high matching circuit for determining the selection of the proper dummy register.

182
4.4
The vertical lines extending through m.em.ory
are the entry and exit busses for the "0" (on
the left of the bit) and for the "1" (on the right
of the bit)jalso the "0" and "1" com.pare lines
(on either side of the storage loops), carrying
the information from. the entry register to be
com.pared with the bit status. The no com.pare
line will carry current instead of either the
"0" of "1" line if this bit position is to be
m.asked out, thus forcing an equal com.parison
as far as this bit is concerned.
As an exam.ple of operation. assume that the
bit shown is the right-hand bit of the interrogating tag in a forward sorting operation.
Bits to the left have shown an equal status.
This bit is a "I" com.pared with a "0" in the
entry register. Current flowing into the com.paring circuit of this bit on the equal line,
frOID the left, will be blocked from. the three
upper com.paring lines and perm.itted to flow
through the bottom. line, thus onto the high line
into the control section of this word, as shown
in Figure 5. Assuming that this word, W, is
the first word in m.em.ory having the "high"
status, the control circuits will operate the
dum.m.y out line during the "A" half of cycle,
thus m.oving the word from. dumm.y register W
up to word register (W -1) com.pleting the pre ..
vious sort operation. During the second hall
cycle, "B," the word from. the entry register
\!ill be entered in dum.m.y register W preparatory to being m.oved into word register (W-1)

on the "A" half cycle of the next sort operation.
Figure 5 shows the circuits for operating the
entry and transfe!' circuits as controlled by
the high, low, and equal signals.
Conclusions
By extending the properties of an associative
m.em.ory, it is possible to secure a self-sorting
m.em.ory. The work thus far done is of a purely
system.s nature since the proper com.ponents are
not yet available. With a self-sorting m.em.ory,
program.m.ing can be m.aterially sim.plified and
the internal sorting procedure im.proved.
Acknowledgm.ents
The assistance of Arthur J. Scriver, Jr. is
gratefully acknowledged.
References

1. Cryogenic Associative Mem.ory by
Robert R. Seeber, Jr., National Conference
of the Association for Com.puting Machinery,
Milwaukee, Wisconsin, August, 1960.

2. The Cryotron -- A Superconductive Com.puter Com.ponent by D. A. Buck. Proceedings
of the IRE, April, 1956.

183

4.4

ENTRY REGISTER
ECHO EXIT REGISTER
DUMMY REGISTER I
(FORWARD EXIT REGISTER)
WORD REGISTER I
REGISTER 2
REGISTER 2
REGISTER 3
REGISTER 3
REGISTER 4
REGISTER 4

WORD REGISTER

ECHO EXIT REGISTER
Fig. 1. Memory System.

,p.. I-'
•
00
,p.."",

CYCLE
PART
ENTRY

A B A B

29 29 I

A B

A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B

- - 39 44
- 55 58
- 58 64
- 64 82
- 44 50
- 50 51- 51 55
-I I 10 10 -II 12 12 29 29 36
- 36 39
- 82 98- 98
- 58 64 64 82 82 98 98 22
- 39 44 44 50 50 51 51 55 55 58
-I I 10 10 -II -12" 12 29 29 36 36 39
- 44 50
-" 29 29 29 36
- 36 39
- 50 51- 51 55
- 55 58
- 58 64 64 82 82 98 98 22 22'
-I I 10
- 39 44
- 10 - II 29
-- -I I -10 10 -II " 29 29 29 29 36
36 39 39 44 44 50 50 51 51 55 55 58 58 64 64 82 82 98 98 22 22 23
"
- 82 22
- 22 22 22 23
- 36 36 36 39
- 55 58
- 23
-I I -10 10 -II II 29
- 29 36
- 50 51- 51 55
- 64 82
- 58 64
- 39 44- 44 50

44 44 10 10 II II 51 51 39 39 36 36 12 12 50 50 23 23 55 55 22 22 58 58 42 42 64 64 82 82 25 25 98 98 31 31 38 38

ECHO
EXIT (01)
WI
02
W2

-I

04
W4
05
W5
06

-I

10 10 -II II 29 29 36 36 36 36 39 39 44 44 50 50 51 51 55 55 58 58 64 64 82 82 22 22 22 22 23 23 25

10 10 I I II 29 29 39 39 39 39 39 39 44 44 50 50 51 51 55 55 58 58 22 22 22 22 22 22 23 23 23 23 25 25

-10 10 -II

29 29 39 39 ~9 39 39 39 44 44 50 50 51 51 55 55 58 58 22 22 22 22 22 22 23 23 23 23 25 25 31

I 29 29 29 29 29 29 44 44 44 44 44 44 44 44 50 50 51 51 55 55 22 22 22 22 23 23 23 23 23 23 25 25 25 25 31 31

- -- I 29 29 29 29 29 29 44 44 44 44 44 44 44 44 50 50 51 51 55 55 22 22 22 22 23 23 23 23 23 23 25 25 25 25 31 31 38
29 29 29 29 44 44 44 44 44 44 51 51 51 51 51 51 51 51 51 51 23 23 23 23 23 23 23 23 42 42 42 42 42 42 42 42 42 42 42 42
- - - - - -I

29 29 29 29 44 44 44 44 44 44 51 51 51 51 51 51 51 51 51 51 23 23 23 23 23 23 23 23 42 42 42 42 42 42 42 42 42 42 42 42 42

Fig. 2. Sorting Example.

J 1 J

- READ IN I

READ IN 0-

~
READ OUT 0-

+ READ IN CURRENT SOURCE

1 I

+ READ OUT CURRENT SOURCE
- READ OUT I

Fig. 3. Cryotron Flip-Flop.

""' .....

•

CX)

"'" c.n

186

4.4

DATA BIT
COMPARE
ENT-EXIT NO "I-I-. "
'0'
'0'
'I'
~

WORD

EXIT-ENT
III

J ,J

,,,.1/1\

1. ,

,
~

-!:

...

UP..

....

..... TRANSFER

....

DOWN

J.~

DUMMY
REGISTER

....

- -,
,
.v

~"J.. I~

....

...

-- DUMMY IN
----- DUMMY OUT

, J.. ,

.III

~.1

...

....

/,~
}I

WORD

....L

111\ _

---- SELECT
DOWN
---TRANSFER
-UP

..
II'!r.

T
11\

1.'

,--.l.

It\

....

11\ ~ t\

11\

11'\

I~
11\ 1

11\

---- MATCH
...
..... EQUAL
LOW

1 , ....

11\

, 1\-

....
,r "

,r"

- ..

""-..

Fig. 4. Data Bit.

HIGH

SWITCH
FOR BACK
" "
U...p

MATCH
NO
PREV
" PREV
" SELECT
NO
PREV
' PREV
"

EXIT(VAC BIT I)

T.S
I. ::i.
"
EXIT(VAC BIT I)
ON ,?,FF
'I

TRANSFER ...
DOWN
DUMMY IN -DUMMY OUT

---

SELECT

$Jl

:E!

I"'t

TRANSFER

:::0
CD
0;9,

1''\
J"

---

11\

DOWN
..

-..
UP

1--

...

~I\

-- '"

(')

o
::s

o
!'"'"'

J'''

LOW

,...

HIGH

...,

J I"

11\

....

1'1\

...

" I'

...

'" ~

, 'r

.....

11\

'" ,...

'" ,...
10..4

\..

11\

1'1\

-- ....
~

....,.

~
~

1'1'\

,'\

J .. V
1'''

-- +

T I"

1'\

11\

1'1'\

11\

I'\'

...

I"'t

11'\

C/l

--...--

11\

-- "

MATCH
EQUAL

11\
I' \.

J'I\

1 \.

TRIGGER
FOR BACK

~
~

--,~

,j::oot-'

•

,j::oo

-..]

189
~

RANDOM

UNIVAC· - RANDEX*II
~CESS DATA STORAGE SYSTEM
G. J. Axel

Remington Rand Univac
Division of Sperry Rand Corporation
Philadelphia. Pa.
SUMMARY
A random access drum file. having 198.6
million bits total storage capacity. a bit density of 650 pulses per inch, and 385 milliseconds average data access time. is described in
this paper.
Two flying-magnetic-recording-heads transfer data to and from the drum file unit. They
are self-supported. by a hydrodynamically generated air film. over two magnetically plated
drums (24 inches diameter and 44 inches long).
The heads. drums. and head-positioning servo are
enclosed in a sealed and pressurized chamber to
prevent their contamination by foreign material
normally found in the atmospheric air.
The text describes in detail:
(1)

The logic of operation and description
of the overall drum file.

(2)

Construction of the flying-heads.

(3)

Descriptions of the servo and mechanical adder, which position the flyingheads over selected addresses on the
drums.
INTRODUCTION

RANDEX*II, developed by Remington-Rand
Univac: is a mass storage. random access drum
file (See Figure 1), capable of being used with
anyone of a number of UNIVAC computing systems,
both present and future. It is presently designed for use with a biquinary (5, 4. 2. 1)
computing code. however. other codes can be
readily incorporated. Initial use of this drum
file will be on the UNIVAC·- Solid State Computer; ten drum files can be used on this computer in conjunction with a single drum control
unit.
The drum control: 1) decodes computer instructions for the drum file systems and issues
the commands to the drum file(s) to process
these instructions; 2) supplies d-c voltages to
the drum file system circuits; 3) provides the
data transfer medium between drum file(s) and
computer; and 4) functions as an off-line control for the mass storage drum file system.

* Trademark of the Sperry-Rand Corporation.

Historically. the RANDEX II drum file follows the development of the UNIVAC - LARCI and
RANDEX I drum files. All three units use the
hydrodynamically supported flying-magneticrecording-head principle, and magnetic plated
drums 24 inches in diameter. Whereas the LARC
drum file contains a drum 28 inches long. one
sequential head-positioning mechanism and a single flying-head, the RANDEX drum file contains
two drums 44 inches long, one random access headpositioning mechanism and an individually flyinghead for each drum.
The RANDEX I drum file was designed using
very conservative bit and track densities to
assure reliability of the initial design. Subsequent improvements in the head-positioning
mechanism, finishing and magnetic plating of the
large drums, magnetic recording elements of the
flying-heads, and recording techniques brought
about the development of the larger capacity
RANDEX II. Specifications for RANDEX II are
listed in the table of Figure 2.
DETAILED DESCRIPTION
The central element of the RANDEX drum file
is a pressurized dust free enclosure (See Figure
3), which contains the following; two individually driven magnetic plated drums mounted on
self-aligning roller bearings. and on which information is stored; the flying-heads used for
reading and writing; and a head-positioning
servo. A mechanical lever adder (discussed in
detail below). located on the lower right section of the drum file, is used for additional
head positioning. and is connected to the servo
by a mechanical linkage. Above the dust free
enclosure is an electronic deck on which the
RANDEX control panel is mounted. and within
which are located plug-in chassis and a transistor circuit card library (See Figure 4).
The dust free enclosure acts to keep foreign material away from the drums, flying-heads.
and servo components. The enclosure is pressurized by blower action with incoming air.
which is first filtered through a low-cost commerical filter to remove the largest percentage
of foreign m~terial, and then sent through a
special filter which removes particles as small
as 0.3 micron (approximately 0.00001 inches)
with 99.97 per cent efficiency. Air is continuously circulated within the enclosure. passed
over the servo motor for cooling. and then

190
4.5

re-circulated back through the above mentioned
special filter by another blower 1_ to assure permanent cleanliness. A window, which is part of
the sealed enclosure, allows the operation of the
drums, flying-heads, and servo to be observed
from the front of the drum file. Doors in the
rear section of the enclosure (See Figure 4) are
located behind each of the drums to permit access
to the drums recording surface for cleaning and
inspection purposes. Easily removable end-bells
on both sides 'of the enclosure (See Figures 3 and
5) permit access to the servo components and
flying-heads. Contamination of the clean air
within the enclosure is practically eliminated
by permitting only small access areas to exist
when inspection or maintenance of servo components and the flying-heads is desired. Clean
areas are not required for these functions. A
further guarantee of cleanliness when the endbells are removed is assured by the fact that air
flow is always out from the enclosure, due to internal pressurization.
Each drum consists of cast bronze end supports and a center support, upon which a 3/16
inch thick brass tube is shrunk. This assembly
is fixed to one end of a supporting steel shaft
and is permitted to float on the other end,
thereby allowing for differential expansion resulting from temperature changes during assembly
and operation. The drum is then machined on a
lathe to provide a concentric, smooth, and uniform surface over which the flying-head will
operate. Final steps in drum manufacture are NiCo magnetic plating, balancing, and testing for
both head flying characteristics and plating
quality.
Reading and writing of information on each
of these drums is performed by an individual
flying-head, which is supported over the drum
surface by a hydrodynamically generated air film
created by the rotating recording surface of the
drum. No external means are used to provide an
air film between the head and drum thereby avoiding unnecessary biasing of the head and possible
localized contamination effects of the head and
recording surfaces. Each head is gimbal-mounted
and has three degrees of freedom, so that it can
follow the drum surface and maintain a uniform
head-to-recording surface spacing. Upon command
a head lowering and raising mechanism lowers the
head into flying position over the drum recording
surface, without physical contact between head
and drum surfaces. An area is set aside on one
end of the drum for this function. Should it be
desired to raise the head or stop the drums, or
should some malfunction occur which may cause
the head to touch or approach the drum recording
surface closer than its established design spacing, the head raising mechanism will automatically lift the head away from the drum, regardless of location along the drum axis.
The two flying-heads are mounted on a common carriage (See Figures 5 and 6) that moves
along a rail (located between the two drums)

parallel to the recording surfaces. The carriage
is driven by a cable that passes over a capstan
on the shaft of a servomotor located in the left
end-bell (Figure 5). A servo-potentiometer,
located in the right end-bell (Figure 3) is connected to the carriage by a thin steel band.
The potentiometer is a part of a bridge network
in the servo pOSitioning logic and is the carriage position indicator. Mounted parallel to
the carriage rail is a movable notched rack (See
Figure 6), connected to the lever adder on the
right and biased against the lever adder by a
spring on the left. Anyone of its 20 pGai~ions
is determined by the output of the lever adder.
There are 100 accurately machined and uniformly
spaced teeth on the rack, whose shape can be
seen in Figure 6. When the carriage is in position, over a preselected notch of the rack, as
determined by the servo-potentiometer, a pawl is
extended from the carriage and moved against the
selected tooth. Therefore, by means of the
servo and the lever adder. the carriage can be
driven to anyone of 2000 discrete positions.
called tracks, along the drum's recording surfaces. The combination of two drums and two
heads then provides 4000 tracks of data per drum
file.
Servo and lever adder movements are performed
in parallel. Going to a new address may involve
servo and/or lever adder changes. When a servo
change is indicated, the carriage is withdrawn
from the tooth, the pawl is retracted from the
notch, and the carriage is moved to the newly
selected track where the pOSitioning cycle is
repeated. The lever adder moves the notched
rack to a new position, independent of the servo
change. However, servo positioning circuitry
must compensate for a lever adder movement. The
repositioning of either or both of these mechanisms results in a new track address.
The electronic deck assembly contains a
hinged transistor card library and four plug-in
chassis; namely, servo-amplifier, servo-amplifier power supply. address register, and control
chassis (See Figure 4). The transistor card
library houses plug-in cards, which contain
transistor circuits that are associated with
flying-head pOSitioning logic, read-write logic.
and malfunction logic. The servo amplifier
drives the control field of the servomotor; the
servo-amplifier power supply supplies the d-c
voltage required for the operation of the servoamplifier.
The address register contains a relay network. which functions as a combined digital to
analog converter and memory. It is used to decode and store the track address as it is received from the drum control unit. The control
chassis contains relays associated with flyinghead malfunction circuits, alarm circuits and
other logic circuits.
The RANDEX control panel, mounted on the
electronic deck assembly (See Figure 3), has

191
4.5

two sets of controls and indicators; one is for
the use of the operator, and the other for use in
maintenance. The operator's controls and indicators are located on the left front side of the
panel; while special maintenance controls and indicators are located on the right front side of
the panel, behind a normally closed access door
in the casework (See Figures 1 and 3). All controls to manually operate the drum file off-line
are provided on the operator's and maintenance
panels, although specific changes in track addressing, supply voltages and read-write instructions must be obtained from the drum control.
The carriage may be moved over the length of the
drum, to approximate track positions, by use of
a sweep control on the maintenance panel. A
break-in plug is provided on the electronic deck
to set new address selections in the address register relays from an external "black-box", if so
desired, although this is not considered standard
equipment.
Access doors are provided at strategic locations in the casework to permit easy access to
the transistor card library, plug-in chassis,
drum access doors, main power control box, and
maintenance panel, without having to remove entire panels.
LOGIC OF OPERATION
The starting of a multiple number of drum
files, associated with a particular drum control
unit, is sequenced, so that only one drum file
draws starting current at a time. The start command is sent to the first drum file through the
drum control unit. When that unit has started,
it supplies a start command to the next drum file.
This starting sequence continues until all drum
files have been started. Should any of the drum
files be turned off at its control panel or
switched to local operation by one of the maintenance controls, the start command is automatically bypassed to the next drum file. A drum
file set in this condition is labeled as offnormal and will not accept commands issued from
the drum control unit or computer.
As the drums in a file reach operating
speed, voltages are supplied, in a preselected
order, to the various control circuits and logic
elements. Automatic clearing of all circuits
and setting of logic elements as required prepares the machine for operation. The flyingheads carriage is automatically positioned over
a prescribed area, toward the left end of the
drums, where the heads are lowered to the flying
position. Once heads are in the flying state,
the carriage automatically moves to the address
stored in the address register; if no address exists in the register, the carriage moves to track
address 0000.
If all of the maintenance switches are in
the normal position, and if no other off-normal
condition exist, the control lines from the drum

control unit are automatically connected to the
drum file, and the file is then under command of
the control unit.
Instructions from the computer can now be
processed by the drum file system, or the drum
control unit can be operated from its control
panel for off-line operation of the drum file
system. Since each drum file has its own memory
for track address storage, it is possible to read
or write on one drum file, while the others, connected to the system, are executing address instructions set in their respective track address
memory. It is possible to issue a new track address instruction to successive drum files every
15 milliseconds. When the drum file completes
its positioning instruction, a unit-ready signal
is returned to the drum control unit, whereupon
the read or write circuits of the flying-magnetic-recording-head may be activated. A select
line determines whether information will be
transferred to or from either the bottom or top
drum.
ENGINEERING INTERESTS
A few of the components which might be of
further interest are: 1) the flying magnetic recording head construction; 2) the lever adder;
and 3) the servo circuits.
FLYING MAGNETIC RECORDING HEADS
Components and an assembly of the RANDEX II
flying head are shown in Figure 7. The head
body consists of two pieces of aluminum, fabricated to exacting dimensions. The surface of
each of these pieces, which after assembly become the flying face of the head. are faced with
tungsten-carbide. After the read-write coil,
erase coil and common I-piece are secured in
their respective cavities in the two aluminum
sections, these sections are bolted together,
with the joint located at the read-write coil
gap-line. The gap-lines on the read-write and
erase heads are spaced 0.020 inches apart.
Since the pivot axis location is very critical
to flying-head performance, bearing holes are
accurately machined at a prescribed location on
the sides of the head.
Using the bearing bores as a locating reference, the assembled head is then mounted in
a lapping fixture and the tungsten-carbide face
is lapped on a wheel, which gives the flying
face of the head a radius of curvature somewhat
larger than that of the drum. The lapped curvature on the head lies in the same plane as the
drum recording surface, and must be parallel to
the bearing axis.
After thorough cleaning and inspection,
terminal boards are added; wiring of the coils
is completed; caging cams, which retain the
head when in the non-flying position, are added;

192
4.5
and, finally, bearings are installed.
A complete inspection to check flying and
recording characteristics is then performed on
the head.

LEVER ADDER

A lever adder, removed from its container,
is shown in Figure 8. It is a mechanism which
provides, through linkages, additional head positioning by moving the servo-rack incremental distances within adjacent teeth. Throughout this
discussion it should be kept in mind that the biquinary (5, 4, 2, 1) computer code is used. In
addition, a 10 has been added to the lever adder
logic.
The lever adder used on RANDEX II is a mechanical adder which can position its output link
to anyone of 23 equally spaced positi~ns, designated here as 0 through 22. The output motion is
generated by strokes of five individual solenoids,
which drive through an arrangement of levers and
interconnecting links, as shown in Figure 9. All
solenoid links have identical stroke lengths,
however, the weighting introduced by the levers
and interconnecting links is such that each solenoid produces a different displacement in the
output. Specifically, in terms of output link
displacement, solenoid 1 produces 1/22 the total
output; solenoid 2, an output of 1/11; solenoid
3, an output of 2/11; solenoid 4, an output of
5/22; and solenoid 5, an output of 5/11. The
distance that the output moves between its zero
position, when none of the solenoids is energized,
and its 23 position, when all of the solenoids
are energized, is a summation of individual outputs.
In order to understand the manner in which
the weighting produces the required motion of the
output link, refer to Figure 9. and consider the
case in which solenoid 1 is energized and the
other four solenoids are de-energized. Solenoid
1 moves its end of the 3-lever a distance of 1
unit (equivalent to the solenoid stroke length).
The other end of the 3-lever remains stationary,
since solenoid 2 is de-energized~ Since the 3lever output link is 1/3 of the distance from the
stationary end to the moving end, it moves
1/3 x 1

= 1/3

unit. The 3-lever output link imparts this motion to its end of the l2-lever. The other end
of the l2-lever remains stationary, since it is
connected to the output link of the stationary
9-lever, which does not move because solenoids 3
and 4 remain de-energized. The output link of
the l2-lever is 1/4 of the distance from the stationary end to the moving end, therefore, the
output link moves 1/4 x 1/3 = 1/12 unit. The 12lever output link imparts this motion to its end
of the 22-lever. The other end of the 22-lever
remains stationary, because it is connected to

de-energized solenoid 5. Since the output link
of the 22-lever is 6/11 of the distance from the
s~ationary end to the moving end, it moves
6/11 x 1/12

= 1/22

unit. By a similar process of reasoning, it can
be verified that each of the other solenoids
introduces a motion corresponding to the 2, 4, 5
and 10 digit with which it is associated, divided
by 22.
In the RANDEX application only 20 of the 23
possible positions of the lever adder are used,
therefore, the total distance that the output
link is moved is only 19/22 of the solenoid stroke
length. Space must be left between position 19
of one tooth, and position zero of the next adjacent tooth to obtain equally spaced information
tracks at a density of 20 tracks per servo-rack
tooth. Total rack motion is then limited to
19/20 of the distance between adjacent servo-rack
teeth. A solenoid stroke length, equal to the
distance between adjacent teeth, was selected for
this design. Therefore, a differential pulley,
connected between the lever adder output link and
the servo-rack, is used to multiply the output
motion of the lever adder by a factor of 11/10.
In the example above, the servo rack moves
1/22 x 11/10

= 1/20

of the distance between adjacent teeth.
By varying the differential pulley ratio and
lever weights. other computer codes can be used
with the same basic lever ad~er assembly.
Primary features in the construction pf the
lever adder are the levers and dashpots, which
are located between the solenoids and output.
The levers are manufactured as segmented
circular discs (See Figure 10). Note that the
link (thin band with pin on end) wraps around a
circular portion of the lever to its point of
attachment to the lever. This is done to provide
constant spacing between links, simplify manufacturing, and reduce link stresses. Relative
positioning of the circular portions determines
the lever ratio.
As solenoids are energized and de-energized,
the associated dashpots control the acceleration
and deceleration of the rack and lever adder
system. To function properly, the entire lever
adder is put into, and kept in, a container filled with damping fluid. A series of holes toward each end of the cylindrical section of dashpots allows the passage of damping fluid into
and out of the cylinder.
Since upward and downward movements of the
dashpots piston are symetrical, only the downward movement will be discussed. The lever adder output is biased by spring tension on the
servo-rack. When a.solenoid is actuated, the

193

4.5
plunger pulls in rapidly. stretching an interconnecting spring between the dashpot piston and
plunger. as a result of the piston being restricted in its movement by the damping fluid in the
dashpot. The pull, exerted on the piston by the
spring. moves the piston which results in damping
fluid being forced out through the hole in the
wall of the dashpot. As the piston moves beyond
the midpoint of the stroke, it starts to cut-off
the openings, thereby reducing the escape area
for the damping fluid remaining in the cylinder.
Size and location of these holes control the piston acceleration and deceleration. Since the
servo-rack is connected to the dashpots through
links and levers. its motion is also controlled.
When the piston reaches the end of the stroke,
very little kinetic energy remains in the system,
and overshoot or jerk is virtually eliminated.
Bias springs. including the servo-rack spring.
move the dashpot pistons in the opposite direction as solenoids are deenergized.

amplitude signal, phased so that the carriage is
driven toward the addressed tooth. At the same
time, pawl control signals from the control logic
circuit cause the carriage pawl to be extended.
Thus, the pawl is driven ag~inst the addressed
tooth. The application of the reverse torque to
the servo amplifier input circuit is timed to
coincide with the peak amplitude of the reverse
torque voltage, thereby lowering the response
time of the servo. In addition, in order to alIowa period of undamped acceleration, the application of the velocity signal for damping to
the servo amplifier input circuit is delayed for
one cycle of the reverse torque voltage. The
velocity signal is then applied. resulting in a
reduction of the velocity at which the carriage
pawl is driven against the addressed tooth. The
reverse torque phase continues until a new servo
cycle is initiated.
REFERENCE

The servo cycle consists of a "forward
torque" phase, a "closed loop" phase, and a "re_
verse torque" phase.
During the forward torque phase. the servo
control logic connects the forward torque output
of the torque circuits transformer to the servo
amplifier. The phase of this fixed amplitude
signal is such that the carriage is driven to the
right, away from the tooth with which the carriage pawl is initially engaged. At the same
time, the holding signal is removed from the pawl
coil, and the pawl retracts by spring tension.
thereby clearing the teeth of the servo-rack.
The duration of the forward phase is timed by a
delay flop in the servo logic.
At the end of the forward torque phase, the
servo control logic begins the closed loop phase
by connecting the error signal from the servo
potentiometer arm to the servo amplifier. The
amplitude of this error signal is proportional
to the distance between the carriage position and
the new address position. The phase is dependent
upon the direction of the error. The carriage is
driven to the position midway between the addressed tooth and the next tooth to the right, at
which position the error signal is zero. In order
to prevent the carriage from excessively overshooting the required null position, a signal
proportional to the velocity of the carriage is
combined with the error signal. The error and
velocity signals are supplied to a "zero detector" circuit in the control logic, as well as to
the servo amplifier input circuit. When the error and velocity signals reach zero, the control
logic terminates the closed loop connections and
sets up the reverse torque connections.
In the reverse torque phase, the reverse torque output of the torque circuits transformer is
connected to the servo amplifier. This is a fixed

1 J. P. Eckert. J. C. Chu, A. B. Tonik,
W. F. Schmitt, "Design of UNIVAC~ -LARC System:
I," EJCC, Proceedings, 1959. p 61.

194
4.5

Fig. 1. RAND EX Drum File

195

4.5

STORAGE
TOTAL STORAGE
INFORMATION - UNIVAC
SOLID STATE COMPUTER

198.588 million bits
126.72 million bits
25.344 million digits

DRUM PARAMETERS
LENGTH
DIAMETER
SPEED
BIT DENSITY - USSC
BIT FREQUENCY - USSC
TRACKS PER DRUM
TRACKS PER INCH

44.0 in.
24.3125 in.
870 RPM
650 PPI
720 KC
2000
50

ACCESS-FLYING MAGNETIC HEAD
MINIMUM HEAD POSITIONING TIME
MEAN HEAD POSITIONING TIME
(ASSUMING RANDOM ADDRESSES)
MAXIMUM HEAD POSITIONING TIME
MEAN DRUM LATENCY TIME
MAXIMUM DRUM LATENCY TIME

125 millisec.
350
550
35
69

millisec.
millisec.
millisec.
millisec.

RECORDING
READ-WRITE ELEMENT WIDTH
ERASE ELEMENT WIDTH
HEAD TO DRUM CLEARANCE
HEAD POSITIONING TOLERANCE (PLUS - MINUS)

0.011 in.
0.019in.
0.0002 in.
0.002 in. max.

DRUM FILE PHYSICAL CHARACTERISTICS
76 in.
33 in.
68.5 in
2000 Ibs.

LENGTH
WIDTH
HEIGHT
WEIGHT

ELECTRIC SERVICE
AC INPUT TO DRUM FILE-60 CYCLE
KVA
STARTING SURGE
RUNNING
VOLTS
DC INPUT TO DRUM FILE SUPPLIED BY
DRUM CONTROL UNIT

5.5
2.0
230

POWER DISSIPATION
AC
DC

1600 watts
500 watts

COOLING
HEAT DISSIPATED
MAXIMUM ROOM TEMPERATURE
MAXIMUM ROOM HUMIDITY

* Time for data of a specific track to appear
under the head once the head has reached address.

Fig. 2. RANDEX II Specifications

9200 BTU/hr.
90 percent

196

4.5

Fig. 3. Front View, Less Casework, Showing Sealed Enclosure

197

4.5

Fig. 4. Rear View, Less Casework, Showing Access Areas

198

4.5

Fig. 5. Servo and Carriage Access Area

199

4.5

RAIL

PAWL COIL

PAWL MECHANISM
(LATCHED ON RACK)

CARRIAGE
DRIVE CABLE

SERVO-RACK
*HEAD ASSEMBLIES AND
HEAD CABLE REMOVED

Fig. 6. Carriage, Rail and Servo - Rack Arrangement

200
4.5

Fig. 7. Flying-Head Components and Assembly

201

4.5

Fig. 8. Lever Adder Assembly

202
4.5

OUTPUT
5/11
6/11
22-LEVER

3/4
1/4
12-LEVER
2/3

1/3

5/9 4/9

3-LEVER

9-LEVER

SOL.
SOL.
SOL.
SOL.
SOL.
12345

2------..
4------.-..

ADDRESS LI NES
Fig. 9. Lever Adder Schematic

203
4.5

I
I
I

•

LEVER
LINK

Fig. 10. Lever Assembly

205

5.1
DATA PROCESSING TECHNIQUES IN DESIGN AUTOMATION
By 'Dr. William L. Gordon
Minneapolis-Honeywell Regulator Company
Electronic Data Processing Division
Newton, Massachusetts
Summary
By providing a computer with basic information concerning the design of a device as
complex as the modern computer one not only obtains an efficient record retention system but
also brings to bear the full decision making abilities of the computer on the design problem
itself'. A major thesis of this paper is that
the automation of the design of a complex system
is primarily a data-processing problem in which
the most powerful tools reside in the abilit,r of
the computer to perform such jobs as editing,
extracting, sorting, and merging pieces of basic
design information. This contention is substantiated by briefly describing the system currently in use to\provide mechanized aids to design
and production at Minneapolis-Honeywell Regulator Company, Electronic Data Processing Division.

Introduction
In the course of proceeding from the design to the construction and maintenance of •
device as complex as the modem computer one is
led rapidly to the need for efficient record retention systems capable of handling such diverse
pieces of information as the formal logic of the
device or the production wiring specifications.
Not only must the record system be capable of
rearranging and presenting the information for
particular use, but it desirably must also do
what it can to reduce the' gigantic clerical job
of effecting the transition fram the basic design considerations of logic and circuitry to
their amalgamation in the finished machine.
The major advantages of such an automated
design system lie in its abilit,r to perform
rapidly and accurately while busily exploring
the consequences of basic design changes, however trivial. The fact that such automatic processes do exist is additional testimo~ to the
systematic approach to machine design so essential to the human consideration of any camplex device.
This paper is a report on such a Design
Automation System currently in successful use
at the Honeywell Electronic Data Processing Division. It is concerned primarily with 'the
techniques of utilizing the capabilities of an
electronic data processor, in this case the
D-IOOO. The inputs to this processing system
consist of statements of the purely logical design of a unit of arbitrary size, skeletal information as to logic and circuit. placement, and
descriptions of the individual circuit types.
au tpu ts are quite varied and range from analysis

of the logical design to wiring specifications
for the machine; this latter including punched
card decks to operate automatic wire wrapping
machinery.
The program system was originally executed
to aid in implementing the design and construction of the H-Boo and will find use as well
in the production of future systems. This latter
statement should be not interpreted as saying
that future designs will necessarily be forced
into the same mold, but rather as asserting that
the processing system is of sufficient flexibili ty and simplicit,r to guarantee rapid adaptability to changes in basic design philosophy.
Indeed, with a few data safeguards removed, we
would be quite capable of specifying a length of
coaxial cable between two remotely located insurance policies.
The most distinguishing feature of the program system in operation is its low usage of the
arithmetical abilities of the computer. This is
conditioned less by the fact that the D-IOOO is
most powerful when employed with the buSiness
data-processing operations of sorting, merging,
and high speed information flow to and fram magnetic tape as by the fact that the job at hand
was a data processing job with the model found.
1t is a major thesis of this paper that Computer
Design Automation (as well as design automation
of other complex systems) is principally a job
of symbol manipula~ion lying almost entirely
within the realm of standard data processing
technique. The reader will undoubtedly agree
wi th this statement insofar as record retention
is an aspect of the design problem. The point
to be made here is that the design process itself is largely a process of augmenting and expanding basic information by a series of merge
(match) passes, extraction, editing, or data
rearrangement passes (sorting), over the basic
information.
Basic Processing
Input
Logical design data is presented to the
machine in the form of Bodlean equations modified to meet punched card requirements. Each
logical statement carries with it an indicator
of the circuit type to be employed in the physical realization of the statement. This latter
device enables the designer to specify the inputoutput relations of non-logical or time-sensitive
devices for which Boolean'notation is inadequate,
the circuit type designator serving to remind

206

5.1
the reader (and the processing program) of the
way this black box should be treated. For example, the statement:
(1)

GBA A/B.e

* D.E.F

makes logical sense i f one interprete tt/tt for
Mequals tt , tt." for nandtt , and
for "or", but
may more simply be interpreted as establishing,
at the very least, an input-output relation between signals B and A, C and A, etc. Indeed, a
possible way to file away the logic is in this
latter form. However, given a file of logical
statements in the fonn (1) it may be easily
transformed into the latter by a single paSs
over the data. This leads us immediately to
the process of examination of the loads on all
signals •••• a process typical of machine use in
this system. (cf. Figure 1)

"*"

Signal Loading
The original logical statement is regarded
as specifying a source together with its inputs.
Dually, each input may be regarded as a load on
the source bearing its name. By forming an item
for each occurrence of each literal the logic
may be recast into a file of signal name pairs
indicating a relation of the form "B is an input
to Att. Sorting all such items on the input field
groups all occurrences of a signal name together
thereby fonning a list of all loads on all signals. The driving signal name itself is properly treated as an input to an unknown load. Wi th
auxiliar,r information descriptive of the circuit
type and gating structure dragged along for a
free ride, a final pass editing for printout has
an easy time tallying loads on each signal.
Matching the tape forming the input to the
sort with the sort output tape foms a simple
means of cascading each signal through another
level of logic. This is an effective method of
chaining the input relation through as many
stages as desired. By reinterpreting the relation as meaning nis a part of" this procedure
is seen to have a direct counterpart in the
business of exploding parts inventories on the
basis of assembly levels.
So far, this has examined the logic from a
purely abstract point of view (quite proper to
logic) but the designer is not merely playing
games on paper. These logical statements are
intended to have a circuit realization. Again
a dual statement may be made, i.e., the circuits
are to have a logical realization. With this in
mind a master file of available circuit (package)
types is treated in like black box fashion with
a typical entry appearing as s

(2)

GBA

10/11.12

* 1).15.17

where physical pin numbers or other designators
indicating location relative to the package at
hand replace the formal logical symbols. This
device of using the same format forces the logical aspects of the circuit description into the
same mold as the logic itself. Aside from ap-

pearing a natural way of representing the circuit it leads easily to the production oriented
step of detennination of' wiring configurations.
Network Determination
The formation of a file in which all pins
of the same wire network are grouped together is
identical to the process used in loading calculations with the exception that a correspondence
between the symbolic logic and the package structures must be made first. This is done via the
use of a third file specifying for each signal
the type of package it is being implemented with
and the slot location of the package in the
racks. The logical statements are matched with
this last file, the resulting tape resorted by
package type designator and then matched against
the pin structure. Resorting the final output
produces a file organized by logical signal name
in which the symbolic literals have had package
and pin locations associated with them in oneto-one fashion. The resulting document is a
compendium of the entire design and all other
information is derived from this generated file.
Reprocessing the pin modified logic through the
loadlist type extraction and sort regroups all
occurrences of each signal. The pin locations
that here ride along are likewise grouped together thereby fonning a first approximation to
a wiring list.
It should be remarked that the processing
system to this point is sensitive only to the
names of signals and location designators and
has not found it necessar,r to establish ~ geometric relations between the physical points.
In this sense no mathematical computation other
than tallying has taken place. Nevertheless,
the original logical design has been exploded
and recast into a form which could be used for
construction purposes. Indeed, a highly simplified version of this system was implemented with
tabulating equipment and employed in the successful construction of a small machine.
Wiring Determination
The principal remaining problem is to pair
the pins of a given signal run to form wires.
Here simple sorting is no longer effective, for
the circuit designers have determined that a desirable criterion for wiring a given network is
to minimize the total wire length in the entire
run. It is at this point that geometry rears
its head and metric relations between pins must
be examined. Nature and Mathematics still smile
however and this becomes one of those rare cases
in analysis where doing the best thing locally,
i.e., building up the network iteratively by appending closest points at every step, produces a
demonstrably minimum overall solution. With
further constraints (e.g., no more than three
wires may be commoned at a particular pin) the
algorithm breaks down; but again Nature is benign and the deviations tum out to be statistically insignificant.

207

5.1
It is this process, computational in
character, that forms the largest fly in the
ointment of the thesis that automated design
consists almost exclusive~ of information
shuffling. Con3equently it will not be reported upon in detail here, but is certainly of
sufficient interest to warrant independent presentation. Overall system flexibility is still
retained by isolating the length decision-making
algorithm with a routine which interprets all
pin designators in terms of an absolute 3 - dimensional coordinate system thereby allowing
complete revamping of the construction geometry
wi th small programming changes. A portion of
this wire determination system includes further
computation for the machine selection of the
various wire types to be used; which selection
procedure accounts for both wire length and circui t loading.
With Wires fully' determined, additional information as to capacitative loading, current
flow in each wire branch, number of wires per
pin, etc., iIlay be easiq accumulated and reported to the designer who may make necessary modifications, update his files and come through the
entire system again. When he is satisfied with
the design the wiring file for the unit is ready
for release to production.
Production Outputs
At this point the file of wires may be
broken down and sorted six ways from Sunday to
fi t production jigging and assembling requirements, (left-handed assemblers need not apply,
for the information is presented for assembly by
right handed operators). With all breakdowns
and sorts made from the parent wiring file, accuracy is guaranteed up to the point of wire insertion. Independent lists are provided for inspection and ring out purposes.
The use of automatic wire wrappirig machinery
in the production process has necessitated the
construction of a program system to effect the
translation of the wiring information to a deck
of punched cards which will instruct the offline automatic equipment. '!be value of the data
rearrangement is high in this case because the
problem of sequencing the wire wrap machine for
efficient operation requires great reordering of
the wires in terms of such criteria as path configuratioD;, color, length, number of wraps on pin,
etc. Again this particular work will be reported upon elsewhere.
Manual Entries
'!be only input point indicated to the system has been at the level of the basic logical
design. Although minor changes can be exploded
through the entire system it has been found desirable to allow the engineer access to the output wiring files. Manual intervention at this
point can account for the special cases not
worthy of programming into the system as well as
allow the engineer final say on what the results

of processing have been. It further enables the
engineer to make minimal changes to a machine
already under construction. The nature of the
decision making portions of the system, notably
the point at which the wiring network is determined, make it difficult to guarantee that
second passes through the full system on moderately input data will keep change minimal. This
is largely because the routines are trying to
minimize an overall criteria.
Checking
With manual modification possible the pro. cessing system continues, but in a different
mode. Now it cannot generate final information,
it can only check on the apparent accuracy of
the file. Two modes are still left open to perform these checks. The first is that after updating the wiring file a check can be made on
connectivity of each electrical path. The second
check to be made on the modified wires is to do
a complete reversal on the original processing
system. and regenerate from the wires the logic
that they implement. This latter file is the
true document of the machine incorporating all
known information about the design. Unfortunateq it is still incomplete for it mere~ describes what the machine should be - as opposed
to what it really is; this latter anomaly occurring only because the insertion of the wire
into the machine and into the machine file are
two different processes.
Extensions

Generalizations

The basic model exploited in the above system is quite simple, the computer is regarded as
a massive assemblage of "black boxes" (circuits
or packages) each possessing input and/or output
points connected together by a relational scheme
known on~ to the logical designer. The individual black boxes themselves are constructed as
an assemblage of other Itblack boxes" (components)
according to a scheme known only to the circuit
designer. We may continue up or down in this
hierarchy to include the system designer or the
co~onent designer at macro-molecular or subatomic levels, but for convenience and with no
real loss of generality will settle at the level
of the circui~ which the logical designer must
interrelate. Each such circuit has well defined
input and/or output points which in the finished
machine accumulate a large number of attributes,
among which are the following:-

1. A deaignator indicating the relative
position of the point in the machine (e.g.,
connector pin location).
2. A designator indicating the type of
circuit to which this node belongs (e.g., flipflop).
3. Number of connections made to this
point.

208
5.1
~. Description of the wire coming to this
point (length, type, route, etc.).
5. Items 1 and 2 for the other end of the
wire coming to this point.
6. Items 1 and 2 for the signal source
driving the network of which this point is a
member.
7. Current flow in the wire of i tern 4.
e. Wave forms at this point.
9. Name of the signal appearing at this
point - name of the network.
10. Structural significance of this point
in relation to the inside of the black bo~. (e.
g., 5th leg of the 2nd gate etc)
11. Name of the black box this wire is going
into.

The above list is by no means exhaustive,
nor does any person associated with the design,
construction or use of the machine have a need
to examine all of the information contained
therein at anyone time. By the same token it
is not until the design is complete that such a
compilation may be attempted for each node (pin)
in the device. The major function of the Honeywll Design Automation System is to piece together the essential pieces from various design
sources and at some points compute a few of the
items in the list.
In examination of the list more closely
several items may be grouped as falling into
distinct design areas. Items numbered (2),(9),
(10), and (11) suitably edited form the logical
design; whereas item (10) above represents the
link between logic and cireui try. Com~ining
items (9) and (1) is essentially the job of
package allocation. Matching these pieces of
design information produces input to a wiring
determination routine from which all else is derived. Curiously, in the course of back-tracking
from wires to logic the program system at one
point uses logical structure as a key for sorting.
The present system is keyed heavily to the
problem of backboard wiring interconnection of
the circuit "black boxes". An enlargement ot
the system will enable machine processing to go
inside the packages or outside to the major unit
complex. Here we will be exploiting the fact
that all location designators are relative to
the level at which they occur. For example,
each component placed on a package is located
only on that package; each package inserted into
a slot in the machine is located only relative
to that unit (e.g., peripheral control unit).

* Wiring networks

are usually simply connected,
i.e., there is only, one wire path (equipotential) between two points. A convention establishing one point in such a network as a
source establishes an orientation for the two
ends of each wire in the network.

Remarks
The generality of the above model suggests
its application to other equally complex jobs.
All we have really done is endowed each connection point with a .name and address obtained
from different sources. Relations between names
are interpreted as calling like relations between
addresses; indeed the very application of Boolean
Algebra to switching circuit theory came about
by making symbolic name assignments to physical
circuits, largely divorcing the problem of logical design from its physical implementations.
Certainly the same technique is applicable to
other complex systems ••• the procedures described here effecting the reverse step of making
all necessary name and address correspondences.
This degree of abstraction has played a significant role in computer design and use, enabling
the breakdown of a complex system into understandable smaller pieces; or rather the assemblage of the system from comprehensible
building blocks.
Name and address processing is certainly
familiar to the programmer who in an effort to
free himself from physical address considerations has constructed automatic program systems
to allow writing his program symbolically (as
the logical designer does today) letting the
machine solve his allocation problem. The only
essential difference here is that when this is
done he rarely has to communicate in detail the
resulting information to anything other than a
computer.
Acknowledgements
The system outlined here is not something
that springs full blown in either conception or
execution. The author is indebted to Dr. J.J.
Eachus for proposing this as a data handling
problem, to Dr. E.J. Dieterich for his adVice,
criticism and direct programming aid, and to the
members of the Systems Analysis Division of
Engineering for yeoman work in devising a working
program system. Both Engineering and Production
divisions of Honeywell EDP must be thanked for
their ready cooperation in the effective use of
the system.
The problems discussed here involve processing technique only. Such a working system
must also cope with the off line problems of
file and document control. The major difficulties that arise are in areas of human communication, for the design automation system has executed a heav.y influence on engineering and production procedures. Analysis and programming
are relatively mild aspects of the problem; but
perhaps this is because machines are really
quite docile.

209
5.1
FROM FILE UPDATING
SYSTEM

RUN# I
SET UP TAPES FOR
1----1.. MAJOR UNIT UNDER
PROCESS THIS RUN

RUN #2
MERGE LOGICAL DESIGN
INFORMATION WITH
LAYOUT INFORMATION

RUN#3
COMBINED
ITEMS INTO ORDER
BY PACKAGE OR
CIRCUIT TYPE

RUN#4
MATCH LOGIC AGAINST
f5'iN"S'5N PACKAGE t ACCOUNT FOR ALL PIN
FORM EXPANDED LDGIC
1 - - -.....
FILE MODIFIED TO
INCLUDE PIN INFORMATION

RUN#5
SORT FILE INTO
ORi5ER BY LOGICAL
SIGNAL NAME

RUN#6
FORM I ITEM FOR
..._--IEACH OCCURENCE OF
EACH L1TERALAPPEND CORRESPONDING PIN LOCATION

RUNH7
SORT BY LOGICAL
SIGNAL NAME TO
GROUP ALL OCCURENCES OF SAME
SIGNAL

EDIT FOR PRINT
COMPUTING LOADS
1 - - _.... ON EACH SIGNAL

EDIT FOR OFFLINE
PRINT
MACHINE FILE AND
DESCREPANCY
REPORTS

OUTPUT

t----I'" DOCUMENTS

FOR DESIGN EVALUATION AND RECORDS
TO WIRE DETERMINATION
(PIN PAIRING) SYSTEM (ON
DEMAND)

Fig.!. Process Flow for Generating Pin Groupings from Formal Logic and Packaging Information.

211

5.2

IMPACT OF AUTOMATION ON DIGITAL COMPUTER DESIGN
by
W. A. Hannig and T. L. Mayes
General Electric Company
Computer Department
Phoenix, Arizona
Introduction
A digital computer logician's job
may be defined as a two-fold task. First,
he ~st generate abstract ideas on the
organization of a proposed computer to
handle a particular type of problem, and
second he must convert these abstract
ideas into data that a factory can use to
construct and ch~ck out the computer.
At the General Electric Computer
Department, we have spent considerable
effort in supplying tools for the logician to use to simplify and to better
optimize the job of converting abstract
organizations into factory data. These
tools are automation programs which
allow the logician to use pro~rams, run
on existing computers, to des~gn proposed
computers.
The paper describes:
1. The functions performed by these
programs;
2. The logician's use of these
programs as a tool;
3. The use of the data produced
by these programs; and
4. The effect that the use of these
programs has upon the human organization
that designs and builds these computers.
The Functions Performed by the Programs
Summary of functions
The programs may be divided according to five major job categories:
1. Arrangement of Boolean equations
to describe the over-all computer logic.
2. Interpretation of Boolean
equations to determine logic gates and
other circuits required; how they are to
be interconnected.
3. Assignment of circuits to plugin circuit cards.
4. Generation of information for
interconnecting circuit cards.
5. Preparation of logic schematic
diagrams.
The program functions in each
category are discussed in detail in the
following sections.

Arrangement of Boolean Equations
(See F~g. la.)
For describing the over-all logic
of a digital computer,- it is of great
advantage to have a set of Boolean
logic equations which show how each
flip-flop is controlLed during each time
interval of each command. Such equations
are assembled and arranged by this program from a manually prepared list of
the control signals active during each
interval.
In the execution of a command,
various control signals, emanating from
a command decode network or from controlling counters, enable various gates in
a series of steps to execute the command.
Thus, for each command the logician lists
the control signals which are turned on
during each step of the execution. This
list, in punched card form, is sorted
and printed in order of command step and
also in order of control signal (to show
the command steps using each control
signal). The list in its former sequence
is one of the inputs to the program.
The logician also prepares on
punched cards a list of the logic
equations which are activated by the
control signals referred to above.
And, finally, the logician prepares
special program control information which
deals with the identifying headings.
These headings will appear in the printed
output, which deals with numerous exceptions to the pattern (such as the
implication of equations due to the
absence of a control signal during a
part~cular command step), and which
organizes the over-all program logic.
From these three inputs the program
collects the equations for each command
step. The equations for each step are
collected by searching the equation list
(on magnetic tape) for the equations
corresponding to the control signals
associated with that step. With suitable
headings interspersed to identify the
various registers, the collected equations
are subsequently formatted for off-line
printing on regular drawing forms. By
careful control, all the active equations

212
5.2

for one command step generally fit onto
one sheet to make the results easier to
use. (Example in Fig. 2.)
Each major, independent equipment
of the system requires this logical description information by preparation of
lists of control signals, equations, and
program control information. The three
kinds of data, prepared by the logicians,
are processed by one set of routines,
virtually unchanged from one equipment to
the next. This characteristic is generally true of the other programs as well;
the variations represented by the different major equipments were treated
simply as variations in the data processed by the programs.
Interpretation of Boolean Equations
(See Fig .. lb.)
The original equations discussed
above are grouped together manually to
form the complete "unimplemented"
equations for each flip-flop. The
logician then operates upon these
equations to match the available logic
circuit structures and circuit rules.
He expresses his results in the form
of "implemented" logic equations which
are punched into cards. (Example in
Fig. 3.)
These equations are interpreted by
a program in order to produce a list of
the "elements" required to implement the
desired logic. An "element" is the
smallest subdivision of a computer which
still retains its logical identity, e.g.,
AND gate, OR gate, flip-flop, etc. Each
element is described by a unique code
name and by a list of the input signals
to the element. Thus, this program produces an Element Input List which
identifies all the elements required and
shows how they are interconnected. These
elements are free-floating; they are not
associated with plug-in cards as yet;
hence, no pin numbers are present.
The process vf interpreting the
equations is related to other equation
interpretation programs in which the
equation is scanned and thereby divided
into unique entities, in this case, the
elements. Each equation contains signals
and symbols (logical operations, parentheses, and such). Beginning from
one end of the equation, the program
selects the first three of these, regardless of whether they are signal or
symbol, and classifies all signals as
simply another unique kind of symbol.
The three-symbol group is looked-up ip
a table containing all possible combinations of three symbols. If the group

is permissible (two plus signs together
would be impermissible), a "level increment" is obtained and algebraically
added to a cumulative level number. The
table also supplies information as to
whether the resultant level number should
be odd or even and what to do to it if
the number requires adjustment. When
finally acceptable, the level number is
stored in association with the middle
symbol of the group (the first and last
symbols of the equation are asterisks).
The same process is repeated for
the next group of three symbols, using
the second and third of the previous
group as the first and second of the
next. Thus, a two-symbol overlap occurs
between successive groups. In each case
the cumulative level is adjusted and
assigned to the middle symbol until the
entire equation has been traversed. In
some cases, a prepass is necessary to
ascertain the presence of certain kinds
of symbols.
Following the level assignment,
the program, still working on the same
equation, successively scans the level
numbers to detect particular values
grouped together. The signals within
such a group are the inputs to an element, and that element is immediately
identified and added, with its inputs,
to the list of elements being prepared.
The list of symbols,signals, and level
numbers is also modified appropriately.
In this process, successive levels of
gates are identified, starting from the
outside gates of the structure and continuing until the innermost gates have
been identified and set up.
The program complains if the number
of levels implied by the equation is
excessive for the particular type of
"source" element (which the gates, as a
group, control). The program shifts
the gating structure about somewhat in
accordance with certain limitations imposed by the circuitry. It also inserts
degenerate (one input) gates as required
by the circuits rules. Gate width is
checked as a function of the location of
the gate in the structure and the type
of source element involved.
The resultant list is, in a sens~,
a list of equations having only one level
each, where the logical relationship is
identified by the kind of gate. But_
rather than view them as equations, they
are viewed as elementary building blocks,
the distinct entities of which comprise
the computer being designed. This list
is the main stream of the programs which
follow. The Element Input List is

213

5.2
operated upon in various ways; other lists
are derived from it, but it continues to
appear along the line in altered, augmented form until it represents a complete
determination of the machine from which
manufacturing information and reference
documents are derived.
One of the uses of the Element
Input List is to serve as input to the
loading calculation routines which prepare a sort item for each element's
input signal whose loading must be evaluated. These items are sorted to gather
together the names of the load elements
on the sources being evaluated. Through
the use of a manually-prepared table
showing the location of the registers
(in a gross sense), the program computes
the wiring capacitance. Using a table
of a-c and d-c loading limits and information contained in the load list on
timing restrictions (derived from the
input logic equations) in which critical
and non-critical timing is identified,
the program assigns the loads to the
sources in such a fashion as to group the
loads geographically and to avoid overload. Parallel sources (producing
identical logic functions from identical
input signals) and the opportunity for
the program to add power drivers where
the timing permits, impose a relatively
complex assignment task. Each time a
load is added, for example, the wiring
pattern may change greatly or very little;
a great change may jump the capacitance
appreciably and prevent the addition of
the load. Thus, the wiring must be
routed and its length computed repeatedly.
Once the loads have been assigned,
the program determines the pull-up or
pull-down currents required to drive the
loads properly and produces a list of
data showing which specific source drives
each load as well as a list of the drivers
added. These lists are used to update
the Element Input List, which previously
has shown source signals in a generic
sense Qnly, rather than by specific element name. The load list is also formatted and printed for use by the
logician. Overload cases which the
program could not cure because of timing
restrictions also are listed for the
logician.
For some equipments, an additional
loading calculation is made to reduce the
amount of driving requirement, and hence
the circuitry, required. In this calculation.the loads on a source are examined for the presence of certain types
of signa~which would absorb all of the
gate's load, and which would be mutually
exclusive of each other. Introduction

of such signals into a pair of loads
driven by the same source would reduce
the effective load on the source to that
of only one load. The massive amount
of timing information and considerable
processing required made it imperative
to do this calculation by computer.
Substantial reduction of circuitry resulted, and in some cases otherwise
impossible logical configurations were
made possible by this approach. The
assignment of these mutually exclusive
loads required special treatmen't in
that the group could not be divided among
the driving sources without recomputing
the effective load.
Assignment of Circuits to Plug-in Cards
(See F~g. lc.)
The next program assigns the elements to plug-in cardsa The available
cards are represented in skeleton form
in a master file. Each skeleton includes the circuits contained on the
card in the form of outpu~and inputs
grouped together with the associated pin
numbers shown. Thus, the circuits are
in essentially the same form as the
elements.
Basically, the program must find a
circuit of suitable type for each element
and assign it by entering the name of
the element as the output of the circuit
and by entering the input signals of the
element as inputs into the circuit.
Space is provided in the skeletons for
the program to enter these input and
output signal names (the output signal
is identical to the name of the element).
If a suitable circuit can not be
found on an existing card, the program
must select an appropriate card type
from the skeleton file, copy it into the
list of cards being used, and assign the
element as described.
With numerous ways in which some
elements may be assigned, including
dividing them among two or more cards,
the program makes use of tables so
organized to provide intricate logical
ability in combination with control
data contained within the skeletons
themselves. Some of the plug-in cards
contain partial gating structures of
various types, and the program must do
considerable work to locate sets of gates
which can make use of these structures.
The programs also must look ahead, in
effect, to determine the card type which
should be set up not only to satisfy the
needs of the immediate element being
assigned - which might be satisfied in
any of several ways - but also to provide

214
5.~

a card type suitable for the remaining
elements to be assigned to this group of
cards.

Generation of Information for Interconnecties circuit Cards
(See Fl.g. ld.)

The group of cards dealt with together is limited to twenty-eight, the
number contained within a physical
module. Because a specific group of
elements is not always assigned to a
specific module~ the program must
assign and reassign increasing numbers
of elements to cards until the number
of cards reaches the allowable limit.
The reassignment is necessitated by the
changing pattern of card types and
numbers as additional batches of elements are added. Sometimes, an altogether different card type may be used
when elements are added to the group
because of their ability to justify such
a type. In another mode, a definite
batch of elements is designated for a
module, and the assignment becomes simpler and more rapid. In each case, a
manually prepared table is used to
designate the/twenty-eight card modules
Which are to contain various groups of
elements.

The Element Pin List represents a
collection of cards which contain the
circuits necessary to perform the
computer functions. Some of the interconnections are already made on the
cards, but the cards themselves must be
interconnected. This is accomplished
by a combination of etched back panels
into which the cards are plugged, and
harness wiring to interconnect the
etched back panels. The program prepares punched tape information to control
automatic machinery which produces the
etched back panels, and it prepares
wiring lists from Which the panels are
manuall¥ interconnected.

The resulting list of plug-in cards
shows all the cards assigned by the
program. Spare circuits are identified
by blank spaces, because of the lack of
signal names associated with the circuit
identification.
This list, called the Element Pin
List (EPL), is a key and permanent file.
Its format permits easy modification by
manual updating Which is accomplished
simply by preparing one punched card for
each pin the signal of which is to be
changed. Entire plug-in cards may be
added or deleted by single punched cards.
The update cards are processed by a
routine which finds the designated pin
or card, makes the indicated change,
prepares a new file, and causes a replacement sheet to be printed showing
the new conditions.
The EPL is used not only for the
subsequent preparation of wiring data
and schematics but its format (inputs
grouped with outputs) also permits the
generation of load lists which are automatically checked for overload. Such
checking is prudent after a series of
manual updates may have thrown a source
over the allowable loading limit. In
addition, load lists are added to logic
schematics derived from the EPL.

As the first step of this process,
the program must determine which signals
extend beyond the confines of a single
etched panel so that suitable panel
interconnection points may be provided
and connected by etched wiring. These
connection points are not specifically
called out at this stage because the
specific points will be selected by
the etched layout program.
These general connection points,
together with the other pins included
within an etched panel, are processed
in a group. Each pin in the group is
associated with a particular signal.
Pins bearing the same signal are wired
together. As the layout proceeds,
specific pins connecting to other panels
are selected and listed separately for
use by the harness wiring program.
The etched panel permits connections
through horizontal etched copper strips
and through vertical jumper wires inserted into holes in the panel. Thus,
a typical connection between two pins
may consist of a series of horizonta+
and vertical segments zig-zagging
across the panel. Isolation of one
run from other runs is accomplished by
means of breaks in the copper strips
which are provided in the etching
process.
The program must seek an open path there is a limited number of vertical
and horizontal lines. available - by
testing for cuts and for existing jumpers
which bar the way. The trials are made
and a path found much as a rat finds its

215
5.2

way through a maze, except that certain
preferences and patterns are established
to guide the process. In addition, the
task is somewhat simplified by seeking
merely a satisfactory rather than an
optimum layout.

logical patterns to enable the user to
trace rapidly through a series of elements and to identify the function of
each element readily. Input and output
pin numbers are shown. Names and pin
numbers of loads are included.

Once the layout is complete, the
data is converted to x-y coordinates for
the location of cuts in the copper strips
and for the location of holes in the
panels through which the jumpers will be
placed and dip-soldered to the etched
copper. A printed image also is prepared of the layout to show the location
of holes, cuts, and jumpers for manual
use. Commonly the progr~L is unable to
complete all the connections with its
somewhat limited imagination and rules;
uncompleted connections are listed for
manual completion with the aid of the
printed image of the panel.

These diagrams are generated from
the Element Pin List; as a result, the
diagrams match the wiring information
because both are derived from the same
source.

the harness pins are collected until
all the etched panels are layed out.
Again, pins bearing the same signal are
wired together. The routing is done to
reasonably minimize the length of each
string of wires. The resulting list of
"from-to" connections is grouped to
provide convenience to the manufacturing
operation. The connection items are
also sorted on signal name to provide
a signal reference list. Another list
is provided by reversing each connection item, adding it to the list,
and sorting the combined data on the
"from"'pin number to produce a pin reference list. And finally, the wiring
strings are sorted according to the lowest pin number in each string to produce
a list which allows semi-automatic
checking of the wiring by ringing out
each string in orderly, non-redundent
succession.
J

Minor changes are made manually on
the etched layout data through use of
the layout image. Changes to the harness
are made by preparing add-delete punched
cards for each wire added or deleted.
These cause the program to update the
list and produce a replacement sheet for
the pages thereby affected.
Pre~aration

( ee

F~g.

of Logic Schematic Diagrams
le.)

These automatic processes which
convert logic equations into lists of
circuit cards and their interconnections
mu~t also report what they have done.
The chief report is in the form of logic
schematic diagrams. (Sample in Fig. 6.)
These diagrams show in graphic form how
the elements are interconnected in

The logic schematic program involves a certain amount of pre grouping
of the information through sorting and
editing operations. The main format
routine traces through the data in
reverse order (upstream) to find and
lay down the elements in the print
image. This process also serves as a
useful check on the completeness of
the data, for should an element be
deleted in error, its absence would
break the chain and cause other elements to be "left over" at the end of
the tracing process.
The important task of keeping the
documentation of a computer in accurate
and complete condition is aided, not
only by the common-source generation
referred to above, but also by use of
an automatic updating process. When
a change is made to the Element Pin
List, the schematic program automatically detects such a change and produces
a series of operations which finally
result in printing a set of replacement
sheets for all those previous sheets
which experienced any changes.
All the output documents which are
to be distributed to various using
groups are printed on continuous-feed,
preprinted vellum forms. A double-faced
carbon sheet imprints on the back of the
vellum and produces a carbon copy for
immediate use while the "tracings" are
being reproduced. The various document
producing routines completely title,
number, and otherwise identify the drawings according to standard practice.
All the output data is printed on
a conventional printer having the usual
scientific characters such as parenthesis,
equal sign, and such.
General Comments
, The programs consist of over 60,000
single address instructions for the IBM
704 Computer and are produced through
regular assembly procedures (such as
the SHARE Assembly Program). They were

216
5.2

developed jointly by engineering and programming groups within the Computer
Department. Communication from the engineers to the programmers was primarily
by means of conventional flow diagrams
augmented by prose specifications and
tabular control data for specific
situations.
Use of the Automation
Program as a Design Tool
One of the first ways that a logician can record his abstract ideas is
in the form of an operation flow chart.
This chart lists the micro-operations
and their time sequence within a given
machine instruction or command. An
automation program gathers all the
micro-operation and timing information
and produces a concise set of organized documents called "Block Descriptions".
The Block Descriptions (sample shown in
Fig. 2) illustrate the control equations
for every micro-instruction interval of
time in all machine instructions. The
logician combines the equations from
each of the Block Description time intervals ,to form the complete Boolean
equation for each "stage" of the proposed computer. (A proposed computer
is sub-divided into a series of registers and a register is further subdivided into stages. A "stage" is a
logical device the fan-out of which can
be greater than one, for example: a
single driver, or a single flip-flop.)
The summation of equations for all stages
of the computer then form the complete
logical description of the proposed
computer. For a moderately large scale
computer this may result in 1000 Boolean
equations for 1000 stages. Each equation
describes the logical operations and
connections to be made within a stage.
All the equations, as a group, describe
the interconnections to be made among
stages of the proposed computer.
The Boolean equations now form the
input data to a group of computer programs which generate manufacturing
information for the factory. When the
equations are written, it is assumed
that all named logic signals are capable
of driving an unlimited number of loads.
Later programs either will remedy overload conditions automatically or complain
to the logician.
The equations are punched into cards.
The punched card format is entirely
variable (see Fig. 3), meaning that
equations are punched on the cards with
few restrictions. The philosophy is to
orient the input data to the logician and

leave the interpretation problem to the
computer program. (Refer to Fig. 3 for
a sample equation listing.)
The Element Input List program that
interprets the equations has three
functions. These are:
1. To conduct exhaustive checks of
the hardware implication of the equations
for circuit rule violations.
2. To generate what we call an
Element Input List. (As defined previously an "element" is the smallest
subdivision of a computer which still
retains its logical identity, e.g., AND
gate, OR gate, flip-flops, etc.)
3. To assign all loads to appropriate sources within each stage and
make a load list.
The "Element Input List" is a list
of the elements needed to implement the
proposed computer. These elements have
been named and their input signals have
been specified by logic name. After the
Element Input List is generated, all the
loads implied by this list are assigned
to sources within stages. Quite often,
this means the program must insert power
drivers to relieve overload conditions.
After the loads are assigned a load list
is made that shows the loads, including
wiring capacitance, presented to every
source in the machine.
From this first series of programs
which generate the Element Input List,
there are a tremendous number of possible
error print-outs which the logician may
receive. Examples of possible error
print-outs are:
1.
2.

Gates too wide.
Depth of logic too great.

How many of these error print-outs
occur is a function of how well the
equations conform to the circuit rules.
(Refer to Fig. 4 for an example of error
print-outs.) When an error print-out is
made, the logician can either modify his
equations to remedy the trouble, or, if
he can show that special conditions
exist, it may be possible to ignore the
print-out.
The next step in the design of the
proposed computer is to assign the hardware implied by the logic equations to
printed circuit cards and locate these
cards in the computer cabinets. When
an Element Input List acceptable to the
logician has been produced, he can proceed to the group of programs called
"Card Assignment" that will assign the

217
5.2
implied hardware and locate it in the
computer. cabinets.
The purpose of this set of programs
is as follows:
1.

To generate an Element Pin List;

and

2. To physically locate the plugin cards within the computer cabinets.

The Element Pin List is permanently
maintained on magnetic tape and is
printed for the logician to examine. The
printed Element Pin List displays one
plug-in card on each page of paper.
(Refer to Fig. 5 for example of Element
Pin List.) The Element Pin List is also
accessible to the logician for update
purposes. Generally, updating of this
list is for purposes of either optimizing the program results or for changing the computer's logic.
The logician's gross control of the
physical location of plug-in cards within the computer is achieved through the
use of the Module-Register table. This
table shows either the number of stages
from each register to be put into a
module; or the number of plug-in cards
of each register which are allocated to
each module. He is aided in making
this table by a program which prepares
the plug-in card count necessary for
each register. A Ifmodule H is a group
of up to 28 plug-in cards which go together into one area of a computer
cabinet.
There is a large amount of checking
within these programs to see that the
resulting Element Pin List conforms to
certain requirements and restrictions.
Some of the items being checked are:
1. An insufficient number of plugin card positions allocated to a given
register;
2. Clock omitted from flip-flop;
and
3. Register not assigned a
location in the computer.
If a rule violation is uncovered,
there is an on-line print made (as was
the case in the Element Input List programs). The logician then may remedy
the violation by one of the following
three methods:
1. Modify the input equations
and re-run all affected data;
2. Make the modification manually
by updating the element pin list; or

3. Show that special conditions
exist which permit the apparent violation.
Logic schematics are made from the
Element Pin List. (Refer to Fig. 6 for
example of machine produced logic
schematic.) These schematics are made
entirely by machine programs and are
printed on a conventional line printer.
Each schematic shows the logic interconnections and physical connections
(pins) within each stage of the computer.
The schematic drawings are organized
by stages and listed in sorted order by
logic name. A load list is presented on
the schematic which indicates the logic
name and pin number of each load on the
stage in question.
There is checking in the schematic
program for a "closed system" of elements. Examples of some of the checks
include:
1. Logic element called for (as
an input signal) does not exist in
Element Pin List.
2. Extra logic element was named
that was never used.
Errors uncovered by the programs
can be corrected either by updating
the Element Pin List, or by modifying
the input equations and re-running those
portions of the computer design data
that are affected.
From the Element Pin List, the
wiring information for manufacture is
generated by use of the wiring programs.
Our particular Ifproduct design" is one
that is wired with semi-automatic machine
tools. In particular, the modules (with
28 plug-in card positions) are wired
with printed circuit back panels. Horizontal "wires" on the back panels are of
etched copper and vertical insulated
jumper wires are put in place manually.
The harness which interconnects all the
module back panels is made manually.
The control data for the automatic
machine tool are in the form of two
punched paper tapes for each module.
One tape is used to operate an automatic
drilling machine to drill pin holes and
jumper wire holes in the back panel.
The other tape is used to operate the
same machine tool, but a light source is
substituted for the drill. The light
exposes a negative which controls the
back panel etching. Data on both of
these punched paper tapes is in the form
of X - Y coordinates to position the
machine tool table.

218
5.2

During the operation of the wiring
program each of the module back panels
has all the vertical and horizontal
"wires" determined. An image of the
back panel is printed out for visual
check and reference before manufacture.
The wiring programs also produce
four printed lists. The printed lists
describe the harness which interconnects
the back panels.
The first of these printed lists is
the "Logic Sorted Pin List tt as shown
in Fig. 8. All the pins are arranged
in the order of their logic name. This
Logic Sorted Pin List is used as a
reference document for maintenance of
the computer.
The next printed list is called the
master pin list. This list is sorted by
pin number and shows the connections to
each pin in the harness. During manufacture this list serves to check that
the proper number of wires are connected
to each harness pin.
The third printed list is the manufacturing list. This is a "from-to"
list of wires. It is sorted on logic
name but is partitioned to match the
manufacturing assembly process.
The fourth and final printed list
is the checking list. Semi-automatic
equipment is used to check that listed
harness pins have been connected together during manufacture, and this list
serves as the input checking data for
the semi-automatic equipment.
After a machine has been designed
and sent out into the field, these same
program-produced documents comprise much
of the documentation for the computer.
The Block Description, Logic Schematic
and Logic Sorted Pin List are the three
main documents sent into the field.
While this completes the description
of the design of a computer using design
automation programs, -it might be of
interest in retrospect, to observe the
philosophical approach taken in the programs, and to make certain comments on
the logic nomenclature used in the input
data.
From the beginning, it is always
assumed that the manual input data is
in error. Therefore, the programs continually check the data for format, and
circuit rule adherence.
The initial run through each major
program usually results in several pages

of on-line er~or prints for a moderately
large scale computer design. It is always hoped that the programs have been
designed flexibly enough to handle all
the varied configurations the logician
can dream up. It is not unusual that the
first pass through a program with new
data will uncover data configurations
that "we would nev~r use," (so said the
logician) but which would indeed cause
the program to halt. In such instances,
a small amount of repair to the program
is all that is necessary before it is
running again.
When automation programs are made
available to the logician, it becomes
vital that a rigorously descriptive
logic nomenclature be used. Stated in
another fashion, the only variable data
supplied to the automation program is the
input logic data. If this data partially
or clumsily specifies the proposed
computer - other information being
implied - the automation programs are
unnecessarily made more complex.
The logic nomenclature sy~tem we
are using progressively subdivides a
computer. The computer is subdivided
into registers. The registers are subdivided into stages. The stages are
subdivided into elements. The name of
a signal produced by an element is
identical to the name of the elemen~.
Every logic signal within the computer
will be associated with its own stage
and register by the logic name.
The logic name is a 10-character
fixed field as shown in Fig. 9. The
alphabetic characters in the first four
characters identify the register from
which the logic signal in question
originates. The first six characters in total - identify the stage which
originates the logic signal. The remaining four characters identify and
describe the specific element within
the stage.
Our pin number nomenclature, as
shown in Fig. 10, provides a similar
partitioning so that the complete pin
number identifies the physical location
of that pin.
Use of the Automation
Program Output Documents
Three documents of primary importance emerge from the computer design
phase.
1.
2.
3.

Block Descriptions;
Logic Schematics; and
The Logic Sorted Pin List.

219

5.2
Moreover, after a machine has been
designed and sent out into the field,
these same program-produced documents
serve as the total documentation for the
computer.
When a fault is to be located in a
computer, the first step is to determine
the machine instruction in which the
fault occurs. This isolates trouble
shooting to a few pages in the Block
Description. Tests are made until a
faulty stage signal has been isolated
within a register. Then the trouble
shooter moves on to the Logic Schematic.
With the Logic Schematic, the trouble can
be isolated to one or two wires, or it
may be located. If more information is
needed, the trouble shooter refers to
the Logic Sorted Pin List to determine
the exact routing of the wires in question.
Note that trouble shooting proceeds in an
orderly fashion through the documents.
There is a minimum of "page flipping" and
of moving from one document to another.
While the output documents have
been organized to allow orderly trouble
shooting, the most outstanding advantage of these machine-produced documents is not their ease of use but their
ACCURACY. One can be absolutely certain
that all three documents exactly reflect
the hardware being maintained and that
they are consistent within themselves.
Also, the continuity of information from
one document to another, through the
logic name, is assured since all three
documents basically originate from the
equation input data.
Although these three documents have
been briefly mentioned previously, it is
now necessary to explain them in more
detail.
The Block Description is a sheet
with a standard format that shows all
registers, error flip-flops, control
flip-flops, and the like that are basic
to the computer control. For each of
these registers, flip-flops, and such
there is a blank space to be filled out
which shows the control signal that is
activated to put the registers and flipflops into operation. If this control
space is left blank, it means that the
flip-flop cannot be operative during
this micro-step. Every micro-step of
every machine instruction has a Block
Description sheet showing appropriate
control signals. It is typical to have
ten or twenty Block Description sheets
for one machine instruction. (Refer to
Fig. 2 for example.)
For trouble shooting, it is usually
known which machine instruction is

failing. This isolates the trouble to
ten to twenty sheets of the Block Description. Next the micro-step that is
failing is located which isolates the
trouble to one sheet of the Block Description. Note that this one sheet
gives all the pertinent information on
the internal state of the computer.
The Logic Schematic displays in
pictorial form the structure of the
logic networks. Also, sufficient information is included so that equivalent
points in the hardware can be located
easily for testing. (Refer to Fig. 6.)
The entire set of logic schematics for
a machine forms a "closed loop" type of
document. This means that if you start
at some place in the drawings and trace
downstream from that point you will
eventually be able to trace back to the
starting point from the upstream side.
Thus, for trouble shooting it is necessary to be able to start at any point in
the schematic and trace upstream or
downstream with ease. Our schematics are
organized by stages and are arranged in
sorted order by stage logic names.
Upstream tracing with these schematics is done by extracting the logic
name which serves as an input to the
stage in question and proceeding to
this stage of the logic schematic. Downstream tracing is easily accomplished by
using the load list included on each
stage schematic. While the load list
gives all the downstream load information,
the load stage schematic also may be
located by the load logic name if necessary.
Due to its simplicity, the Logic
Sorted Pin List (see Fig. 8) mentioned
previously will not be described further
except to say that the logic names used
in the Block Descriptions and Logic Schematics are also carried through to the
Logic Sorted Pin List.
Automation Program Effects Upon the Human
OrganLzatLon DesLgnLng and
BULldLng Computers
There are about 60 separate routines
which together make up the five major
programs we have described. These
routines are largely stored on a program
magnetic tape, although some are stored
on punched cards. All of these routines
were written for use on an IBM 704 Computer. The machine operator must select
the routine and routine sequence he wishes
to use on the particular input data.
Generally these decisions are made before
"getting on" the machine, and a deck of
control cards provides the sequence of
routines to be called in from the program

220
5.2
tape.
Generally, the machine operator
function is performed by one person
whose sole task is to run the programs on
the data supplied by the logicians. Many
technical decisions are made while running
the routines. Quite often, the on-line
error printouts from the programs will
dictate immediate termination of a machine
run until corrections in the data can be
made. Sometimes error printouts may be
ignored. Therefore, the operator has to
be an engineer selected from the staff of
computer design engineers. This machine
operator, however, spends only a moderate portion of his time on the machine.
The remainder is involved in organizing
data to be run, keeping accurate control
on the large number of magnetic tapes
which represent the various machines
being designed, and communicating with
the logicians to give them results or to
show them where the input data is faulty.
The logicians are responsible for
preparing the input data for their particular machine design. Usually, this is
accomplished by recording the data on
forms and having the cards punched at
one central location. Then, it is the
logician's task to check the listing of
these cards and to order that certain
machine runs be made on this data. The
machine run order request is made to the
machine operator. The operator then
schedules the machine time for the run,
makes the run, and returns the results
to the logician.
The basic input data to these programs is the Boolean equation representation of a proposed computer. Any
equipment that is described with equations can be processed by these same
programs. Therefore, the programs are
invariant to the logic of the machine
being designed. This is borne out by
the fact that eight separate and distinct computer equipments (systems or
parts of a system) have been designed
to date with the same programs.
It has been indicated that a moderately large scale computer would have
equations for about 1000 stages. These
1000 equations are the prime input data
to this automation process. For the NCR
304 Central Processor which was built for
the National Cash Register Company by
the General Electric Company, there were
about 1000 equations that were stored on
approximately 2000 punched cards.
Listed below are some of the running
times of these programs on a 704 Computer.
These running times were for the design of
the Central Processor portion of the NCR

304 Computer.
Initial
Program

Block Description

6 hrs.

Element Input and
Load Lists

3-1/2 hrs.

Update
Run

*
1 hr.

Card Assignment

3 hrs.

Logic Schematic

2 hrs.

1 hr.

Wiring

8 hrs.

*Approximately equal to the update volume
divided by the total data volume times
the initial running time.
As illustrated, a complete design
can be done rapidly, assuming perfect
input data. With this ability to generate new designs easily and with speed,
the automation programs now can assume an
entirely new role. Such programs can be
used as evaluators to test the effect of
varying parameters and circuit rules to
optimalize the design.
One excellent example of the evaluation role of the programs took place
during the design of the NCR 304. A
power driver plug-in card had been built
and was within a few weeks of going into
production for th. NCR 304, when a transistor manufacturer announced a new
transistor with about 70% greater load
driving capability. However, the price
of the new transistor was considerably
higher than the transistor that might be
replaced. The questions to be answered
were:
1. Can the higher cost of the new
transistor be justified?
2. Can the new driver be included
in the design before the computer release
to the factory in the immediate future?
With the adjustment of a few constants within the program and a few
hours maChine running time, it was
simple to justify the higher priced transistors and generate all the new data
required for the factory.
To summarize the effects these automation programs have had upon the Engineering organization using them, here
are some of the immediate and rather
obvious results which were achieved:
1.
time;

Reduced computer design cycle

2. Reduced engineering design
manpower;
3. Better documentation of the

221
5.2

designed computer;
4. Greater reliability built into
the computer through complete adherence
to circuit rules;
5. Better optimized computer design; and
6. Drastic reduction in the educational effort necessary to teach the
logicians the circuit rules.
Now, let us examine some of the
above items in detail. An engineering
model of the NCR 304 Central Processor
was built by entirely manual methods.
The production model NCR 304 Central
Processor was built by using the automation programs. The production model
bore no physical resemblance to the
engineering model. Even the plug-in
cards were completely re-designed. Thus,
both designs were different except for
the logic, and both designs started with
approximately the same logic equations.
Considerably less' engineering manpower was needed for the design of the
production model than the engineering
model even though the production model
was a much more complete design. The
non-engineering personnel remained about
constant during the two designs. Using
the same manpower on the automated design as on the manual design, the
computer design cycle could be reduced,
and here it should be noted that with
the automated design, a few key engineering people can run the entire design
effort rather than spreading the design
among many groups of engineers. Stated
in another fashion, the design task has
been modified such that non-engineering
personnel can do much of the work formerly done by engineers, and yet a few
engineers can maintain absolute control
of the whole process.
One reason why fewer engineering
man-months are required in the automated
design is that most of the "engineering"
decisions of how to implement logic with
hardware are made by the programs. In
addition, having the programs implement
the logic into circuits produces an
additional effect of great importance.
This is that ALL logic configurations
are thoroughly checked to conform to
circuit rules. Such things as wire
capacitance loading on every source are
accurately calculated and factored into
the total loading picture. With an
entirely manual design process, this
would be almost impossible even though
reliable machine operation dictates such
calculations.
with t~e implementation of logic
into circuits by program, the designer
only needs to know the circuit rules in

a gross sense. The circuit designers
develop the circuit and its rules and
deliver this detail information to the
programming group who builds the rules
into the program. There are a total of
only two or three people in the programming group who ever see these detail
circuit rules as opposed to educating a
large number of personnel as was formerly
required. Thus, it is evident that one
of the difficult and important communication problems in digital computer
design has been circumvented.
When the Design Automation techniques
were introduced, there was considerable
resistance to them in certain areas.
Familiarization with the new documents,
however, brought firm support for the new
documents and their many benefits in a
very short time. The greatest advantage,
perhaps is the knowledge that the documents always exactly represent the
equipment in question. Also, the machine
updating of the drawings results in a
very short time lag until changes are
reflected in the drawings.
The digital computer design task
is never static. It will be continuously and progressively automated by the
use of programs run on existing computers. Better optimized designs and
design processes in which such matters
as accuracy and adherence to circuit
rules are effectively handled, both
serve as stimuli for automating the
design task.
Acknowledgements
The authors of this paper wish to
express their appreciation to the following employees of the Applications Section
of the General Electric Computer Department for their efforts and cooperation
in writing and debugging the Design
Automation Programs:
M. A. Anfenson
R. B. Cochran
D. D. Degler

W. T. Dodds
P. H. Jennings
R. W. Miller
R. E. Moore
W. J. willis

222
5.2

Assemble
Equations
for each
Block

Format
and
Print

Fig. la. Over-all Design Automation Flow Chart

Gather Loads
on
Each Source

Calc. capacitance; Assign
Loads to
Sources and
Drivers

Complete the
Input Signal
Identification

Format
and
Print

Fig. lb. Over-all Design Automation Flow Chart

223
5.2

Assign Elements
to Plug-in
Cards

Format
and
Print

Fig. Ie. Over-all Design Automation Flow Chart

224

5.2

Gather Pins
to be
Connected
Together

Assign
Connector
For Etched
Panels

Prepare
Various Wire
Data

Layout
Etched Panels

Fig. ld. Over-all Design Automation Flow Chart

Prepare
Load
List

Prepare Logic
Schematics

Fig. le. Over-all Design Automation Flow Chart

"'Ij

.....

C!C!

!V
~

"'Ij

::r' ~ ~::r' ..... Il)
~1l)::r'Oe.~
_ ....
rno

0102 0

= NJ111
NJ110
= FP141

OECI,..AL
ME~ORY

FPOOI XKAll
FP001 XKAll
XKA90

ADO
REGISTER

NO CHANGE OF CONTENT IN LOGIC PERIOD

MEMORY-SELECT • ADDRESS IN L-REG.

£E211-EE241 • FM011-FM041 FEOOI PE021
EE210-£E240 • F"010-'M040 FE001 PE021
FE011-EE201 • 'E051-EE241 Fe001 PE041
FE010-££200 • F£05O-EE2~O FEOOI PE041
FE001 • XP211 PE231
FEOOO •

XPO~l

PEl51

'EOOO • XP221
TALLY

~EGISTER

C6-REG)

NO CHANGE
MISC. 81T STORAGE
FlMl1 • (FL01-14 • CONSOLE SWITCHES)
JI401 IP231 IM-MAINI
FlM11 .'JI~11K • JI423K(FMOll+FM0211+
J1433K FM021+ JI~43K FMOll
FMOlI) XP081 PN231

--------'lORI • IP08 '"051 PftZ'l

D£CISf0f4 "'-OGle
'''011 •
FI(OlO • IP141

FK021 • (FAO,-01- 000) XPI01 PNZ31
FK020 - XP141
INSTRUCTION REGISTER
FN141-FN161 • FMOII-FM031 SR031 XPO~l
PN231
FNl.0-FN160 - FMOIO-FM030 SR031 xP091
PN231
• FM051 SHOll XP091 PN231
'N171
• F~O~O SAO'l XP091 PNZ31
'"110
PROGRAM COUNTER

(FN01-FN07,

FKOIO FK020 - COUNT TO NEXT BLOCK
FKOIO FKOl1 PH031

SKIP TO BLOCK

FKOll FK021.-

SKIP TO BLOCK

FK01! FK020 -

SKIP TO SLOCK

COMMAMD-

1
1 BI.OCK-

AD])

FNl T

FN1'"

LOOK UP SECOND WORD OF"
COMMAND

The automonitor FF is set
if the monitor address selection switches are equal to
the L-reg. and the' monitor
address switch is on; or if
the automonitor character is
equal to or greater than the
monitor charaeter selection
swf.tch setting.
The B & C portions of the
second word of the command.
containing the partial word
designations, are copied into the E-reg. from the M-reg,
The S2,.reg,_ is cleared.
The A portion. which contains the monitor character
and relative addreSSing instruetions~ are copied into
the A-reg.

If the monitor character is negative, the over-ride FF is set.
The mode bits of character 9 are copied into the N-reg.
providing the machine is not in R3 test mode.
The index register character (R) is copied into the L.S.
four bits of the L-reg. while the remainder of the L-reg. is
cleared.
The program counter counts to the next bloek if the index
register field selector (S) is not equal to zero.
The program counter skips to block 01-04 if the index
field selector (S) is zero.

registe~

Ut!'V
•
!'V
!'VOl

226
5.2

EWIIOA
EWIIIA
EWl20A
EWl2lA
FAOIOA
FAdllA
FAo20A
FA021A
FA030A
FA03IA
FA04QA
FA041A
FAOSOA
FA051A
FA060A
FAQ6lA
FA010A
FA011A
FAOaOA
FA08lA
fA090A
FA091A
FAIOOA
FAIOlA
FAllOA
FAIll~

FA120A
FA12lA
FA130A
FAl3lA
FA140A
FA141A
FBOOOA

FB001A

• QCOIIA * FP201A NGOIOA *
= QCOIIA * PGOl3A *
a QCOIIA * EW121A FG040A *
• QCOllA * EWIOOA EW120A FGOOlA FGOIIA FPOOOA DP230A EWlI1A •
• OCOIIA * FA050A OA05lA + FLOIOA OA061A •
a QCOllA * FA05lA DA05lA + FLOllA DA06lA *
• QCOIIA * FA060A OA051A + FL020A DA061A •
• QCOllA * FA061A DA05lA + FL021A DA061A •
• OCOIIA * FA010A DA05lA + FL030A DA06IA •
a QCOllA * FA01lA DA051A + FL03lA OA061A •
= OCOllA * FA080A DA051A + F~040A DA06IA •
= QCOIIA * FAOSlA OA051A + FL041A OA06IA •
a QCOIIA * FA090A DA051A + FL050A OA061A •
• QCOIIA * FA09lA OA05lA + FL051A DA06IA •
• OCOllA * FAIOOA OA05lA + FL060A DA061A *
= QCOllA * FAIOlA DAOSIA + FL06lA DA061A •
= aCOIIA * FAllOA DA05lA + FL010A DA06IA •
• QCOIIA * FAIllA DA051A + FL011A DA061A •
• QCOIIA * FA120A DA051A + FL080A DA061A •
= QCOIIA * FAl2lA DA051A + FL081A DA06lA •
• QCOIIA * FLO lOA OAOIIA + FMOlOA DA021A + NJOIOA OA031A
FSOIOA DA041A + FL090A DA061A + DA121A*
= QCOIIA * FLOIIA DAOIIA + FMOIIA DA021A + NJOIIA OA031A
FSOllA OA04lA + FL09lA DA06IA *
IS <)COllA * FL020A OAOIIA + Fr~020A OA021A + NJ020A DA031A
FS020A OA04lA + FLIOOA DA06lA + OA121A •
• OCOIIA * FL021A OAOllA + FM021A DA021A + NJ021A DA031A
FS021A OA04lA + FLIOIA DA06IA •
• QCOIIA * FL030A DAOllA + FM030A OA021A + NJ030A OA03lA
FS030A DA041A + FLIIOA DA061A + DA121A *
• QCOIIA * FL03lA DAOIIA + FM031A DA021A + NJ03lA OA031A
F503lA OA041A + FLIIIA OA061A *
• QCOIIA * FL040A OAOIIA + FM040A OA02lA + NJ040A OA031A
FS040A DA041A + FL120A DA061A + DA121A •
• QCOIIA * FL041A DAOIIA + FM041A DA02lA + NJ041A DA031A
FS041A DA041A +FL121A DAd6lA *
= QCOIIA * FL130A FP281A DAOIIA + FM050A FP281A DA021A + NJ050A
FP28lA DA031A + FS050A FP281A DA04lA + FL130A DA061A
FP281A DAl2lA *
s aCOIIA * FL131A FP28lA DAOIIA + FM051A FP281A DA021A + NJ05lA
FP28lA OA031A + FS051A FP281A OA041A + FL131A OA061A •
• OCOIIA * FL140A FP261A DAOIIA + FM060A FP281A OA021A
NJ060A FP281A DA031A + FS060A FP281A DA041A
FL140A DA061A + FP281A OA121A •
= OCOIIA * FLl4lA FP28lA DAOIIA + FM061A FP281A OA021A + NJ061A
FP281A ~A031A + FS061A FP281A DA041A + FL141A DA061A •
• OCOIIA * DPOOIA peS03A + OP031A P8533A + DP041A PB543A
DP011A PB573A + DP081A P8583A + OP09lA PB593A + OPlOIA
PB3;3A + OE321A FPOOIA PB643A + FSOIOA FS020A FS030A
FS040A FS060A FPOOIA P8353A + DPOIIA PB513A + DP231A PB733A •
• QCOIIA * OP221A PB423A + OP231A PB433A + OP021A PB223A
DP051A PB253A + OP081A PB283A + DE31lA FP26lA P8343A
fFSOIIA + FS02lA + FS031A + FS04lA + FS06lAJ FPOOIA
PB353A *

Fig. 3. Sample Input Equation Data
Figure 3 is a partial listing of the equations for a recently designed machine. The plus
sign is an OR relation and the parenthesis is an AND relation. The logic signals are the
six character groups. An AND relation is implied where no character appears between
logic signals. The asterisk denotes the beginning and ending of the equation input
terms.

227
5.2

SSWl IS UP--OUTPUT IS ON TAPE 8
D,\051 A
LEVEL TOO HIGH
DP071AOOOOOOOOOOO6
Di\051A
LEVEL TOO HIGH
DP061AOOOOOOOOOO06
DAOSIA
LE.VEL TOO HIGH
DP041AOnOOOOOOOOO6
DA051A
LEVEL TOO f-tIGH
DP031AOOOOOOOOOO06
PA081A
WIDTH ERROR IN GATt:
DAOBIASGOllDA081A
WIDTH ERI~OR IN GATE.
DA081A4GOllDA081A
I.J I l) THE RR OR I N GATE
OA081A3G011ILLEGAL eHAR
EA021A
EA081A
l.EVEL TOO HIGH
DU011AOOOOOOOOOOO5
EA081A
WIDTH ERROR IN GATE
I:.A08lA3G011FORMAT
EA801A
NO FIRST ASTERI3K.
SEQUENCE
EA091A
ILLEGAL CHAR
EA091A
fOR/·1AT
FAOOOA
CLOCK
FA011A
CLAI"\P ERROR IN GATE
FAOIlA2GOl1FAOB1A
WIDTH ERROR IN GATE
fAOBIA5GOllFAOBIA
WIOTH ERROR IN GATE
fA081A4GOllFA081A
WIDTH ERROR IN GATE
fL\OB1A3GOllFAOBIA
CLAt<1P ERROR IN GATE
fA081A2G018fORt-1AT
FA191A
NO FIRST ASTE~ISK.
FORt-1AT
A:)011AA0021A +
fCOlOA
fOR~~AT
fCOIOA
+
AD011AA0021A
fORMAT
fCOIIA
NO FIRST ASTERIS~
FORMAT
fC021A
NO FIRST ASTERISK.
fORI1AT
fe02lA
OA045A
FORI"-1A T
FC021A
DA046A
FORMAT
fCOIIA
NO FIRST ASTERISK
SEQUENCE
FCCllA
FOR:-.1AT
EQ sur-1
JC034A
JC043A
'II 10TH ERROR II'~ GA TE
JC043A5GOllJC043A
WIDTH ERROR IN GATf:
JC043A4GOllSEQUENCE
fNOBOA
fORMAT
PAOllA
NO Ef OJN

NO LOAD l.IST FOR
FPOOOA OFOl
NO LOAO l.IST FOR
fPOOOA OF02
El.EMENT
FPIOOA
5G021DOES NOT APPEAR IN INPUT DATA
ELEMENT
FP100A
5G041DOES NOT APPEAR IN INPUT DATA
NO LOAD LIST FOR
FP200A OF02
TAPE 5 IS FULl.. REPLACE AND PUSH START.
LOAD LIST FOR
LOAD LIsT FOR
NO LOAD LIST FOR
NO LOGIC ~OR LOADS
ELEMENT
FSllOA
ELEMENT
FSl20A
lEFT OVER El.EMENT

NO
NO

4G0714G071FS160A

FP240A OFOl
FP260A OFOl
FP290A OFOl
FP291AO"'OA
DOES NOT APPEAR. l~ INPUT DATA
DOES NOT APPEAR IN INPUT DATA
4GOl X
03F6
lC2140

Fig. 4. Error Printouts from Element Input List and Logic Schematic Programs
In Fig. 4, the upper half of the example shows a number of error printouts made by the
Equation Interpretation program. The lower half shows error printouts made by the
Schematic program. Both examples are from Production Input data.

CARD
LOCATION
OlHl

EQUATION
SUM

EL.LEVEL
& TYPL

ZG2

DM771A

4G 0 III

E~821A

FL142A

OE020OFOIB-

29
28

DM771A
FL093A

4G0111
OFG1D-

45
41

F L.l_C3A_
~G2__

CARD
TYP~

CKT.
TYPE

2G2

CARD SERIAL
NO. IN MOD.

__0 F_O LC....

__ __ __ _

PIN
NO.

UtI'-:)
•
I'-:)
I'-:) 00

04-

CKT.
TYPE
4 G2

4GZ

EQUATION ~L.LEVEL
SUl-1 __
_ __ & TY?~

PIN
NO.

D~ 8~ lA

__4 GO 2 12

FLQ93A

OF01D-

17
18

D~801A

~G0312

FL142A

OF015-

40 ___ ___
42

4 G2

D >18 0 l..!.

4 G0 41 1

FM810A

OF01E-

03
04

_4G0511_
OH013-

06
12
10

36
44

4G2 __ Q;-"180 lA_
DM181A

3~~~_____

ZGZ

4G2

13
14

37
2G2

46
31
32

DM761A
PMOO3A
EM82lA

4G0211

OHOAO

OE020-

DM111A
RM803A
EM821A

4GOZ11

11
15
16

OEOZO-

Fig. S. Plug-In Gate Card in Element Pin List Format
Figure 5 is an Element Pin List representation of a single plug-in gate card. Note that
some of the gates and some of the inputs have been left unused. Also, some pins have
identical logic names attached-indicating that these pins will be wired together.

O\C'J
C'J
•
C'Jl.(')

OLlIlA OH02 IE32 •
JI13lK
IE35 •
FS05lA OHOA IHl7 •
FP281A OHOA IHIS •
Dl111A OHOl IH41 •
FA131A OFOI lH13 •
OL19lA OHOZ IHl4 •

05 IE31 - - - - - - - - lE36 +
lE14
+
IE36
+
03 tHoa
IH45
04 1H09

FAl3lA OFOI IH19 •
FP28lA OHOA IH20 •
DLl5IA OHOl IH31 •

01 lH07
IH42

FM051A OHOA IHI5 •
FP28lA OHOA IHl6 •
DLl6lA OHOI IH35 •

02 IHll
IH44

lHO) •
SLl3lA
DL22lA OH02 IH04 •

06 IH05

+
+
IF19 +
+
+
+
+
+
IFl8 +
+
+
+ 01 IEBS FLl3lA OFOI
....--.....--...-....-...+ 01 IF05 ---- lE33 +
IF06
lE46
+
lE04
+
-- IF17 +
QCOIIA 2H80 lE01
+
+
lEl2
+
+
+
+
+
-- IF16 +
+
+
+
• lE34 +
-----

FL131A OFOI
MODULE - 02H8
DM401A
DM411A
DM421A
DM631A
DM64lA
DM65lA
FAI3lA
FA13lA
JK431A
NJ450A
NJ470A
NKM50A

5GOI
4G03
4G03
4G01
4GOl
4G01
4GOI
4G05
4GOI
----

0lH12N35
01HllS40
01HllS41
0lH12M36
01H12M38
0lH32Hl4
03H5ZS13
03H51R33
04F7lF43
03F51E09
03F51F09
4G04 04H41D3l

Fig. 6. Machine Produced Logic Schematic
The machine produced Logic Schematic displays the structure of the logic networks. In this schematic, interconnections between elements of the stage are made obvious by their placement on the drawing. Therefore,
the use of interconnecting lines is unnecessary. Rows of periods designate the scope, or width, of an AND
gate and rows of plus signs designate the scope of an OR gate. Any break in the sequence of these symbols
terminates the scope of the gate in question. Input pins to elements are physically located with the four
character pin number immediately to the left of the scope line for the element. To the right of the gate scope
symbols is the two character gate name (serial number) and next to the two character gate name is a four
character pin number identification of this gate output. I.f several circuits have to be connected in parallel
to implement this gate, then several output pins will be present in a column. It is implied that all pins in the
stage are contained in the cabinet, rack and module that is shown as the ~'module" in the upper right corner
of the drawing.

CJ1 I'-:)
•
W

1'-:)0

DL21LA

OH02 ••--~

FL13lA

4G05

JI13lK

FS05lA

OROA

FP~81A

OROA

DL17LA

ORO 1

FA13LA
DL19LA

FA131A
FP28LA

4G03

FL13lA

4G04

FL13lA

OFOle

I "\

OFOl

DL151A

FM05lA

(ROA

FP28lA
DL16LA

OROl

)

FL131A
4GOl

OROA:={)

FL131A

~
OR02~

I \

OH02-V

OROA:=]
OHOI

SL131A

FL13lA

FL131A

3GOl

lGOl

,\~Set input

I FL13LA

~~OP I

OFOI

Output 02HBlEO!'

Clock

QCOlLA 2H80

4G02

LOAD LIST
OlHl2N35
DN40LA 5GOl OlHl1540
DN411A 4G03
etc.

Fig. 7. Hand drawn Logic Schematic (with no pin information)
Figure 7 shows the equivalent hand drawn logic schematic for comparison to the machine
produced schematic of Fig. 6. It should be noted that Fig. 7 includes no pin number
(physical location) information whereas Fig. 6 has both logic and pin information.

231
5.2

LOGIC

PIN NO.

ENOIOEOEOI

41H22M29

41H32l11
41H41A38

ENOI1EOHOA

41H32ZJ9
41H42A23
41H51Z29

ENOI1EOHOB

41F19COl
41H32Z0'
41H41Z33

EN020EOEOl

41H41All
41H22MIO

EH021EOHOA

41F31Z2'
41F41A40
41H12Z40
41H31Z0J
41H42A40

EN021EOti08

41'19C06
41F41A20

41H52A20
41H41Z:42

Fig. 8. Sample page from Logic Pin List

232
5.2

'['rueli'alse
8il1nal

Alphabettcs Denote
Register

Desig-

Ma 10r
t

Compute
Unit

Numeri cs Denote
8bage

Element Circuit
Type
r

D03 1 B

Element Serial
Number
~

o 41

The following information is carried in the above logic designation:
Third stage of the FD register
True signal
Central Processor logic
Flip-flop element - fourth serial number in stage
Fig. 9. Sample Logic Nomenclature

Hinged
or
Fixed
Rack

Module
Number

Module
Row

"',

Module
Socket

Cabinet Number
t

0 3 H 6

Pin
Number

1 R 3

Fig. 10. Sample Pin Nomenclature

233
5.3

CALCULATED WAVEFORMS FOR THE TUNNEL
DIODE LOCKED-PAIR CIRCUIT
D. R. Crosby

H. R. Kaupp

Electronic Data Processing Division
Radio Corporation of America
Camden, N. J.
The purpose of this paper is to present an introductoryanalysis of the tunnel diode locked-pair circuit.
The characteristics of the tunnel diode, together with
the simplicity of the locked-pair circuit, make it a
major contender for use as a high-speed computer
element. 1, 2 High speed and high gain are the main
advantages of the locked pair; the multi-phase power
supply and lack of a simple means for logical inversion are the main disadvantages. The basic circuit
consists of two tunnel diodes in series, the node common to the tunnel diodes being both the input and output terminal. As a computer element, the locked pair
functions in much the same manner as the phase-locking
harmonic oscillator (PLO). Like the PLO, the locked
pair overcomes the difficulty of COincident input and
output terminals byusing a three-phase voltage source.
However, the theory of three-phase majority 10g!c is
not essential to the understanding of this paper. 3,4
A.

Basic Concepts of Locked-Pair Circuitry

The equivalent circuit of a tunnel diode is shown
in Figure lA, and the volt-amp characteristic of the
nonlinear conductive element is shown in Figure lB.

load. For the moment, neglect the source resistance.
Increasing the voltage E "draws" the load curve A
across the characteristic of the active element B.
This is analogous to what is done with tube and transistor circuits, the difference here being the nonlinear
load. Figure 3 indicates the current-voltage relationships for the circuit of Figure 2, at a particular value
of source voltage, where it is seen that the load curve
A intersects the element curve B at three points.
Points one and three are stable, while point two is unstable. The state in which the circuit locks, as the
source voltage is increasing, depends on which of the
two characteristics first reaches its negative conductance region. By inserting a locking current, IL (Figure 2) the operating point is predetermined (Figure 4).
The effect of 1L is to shift the family of operating points ,
causing element B to reach its negative conductance
region before element A. Thus, diode B goes to its
high voltage state. When the voltage E becomes equal
to EL, point three of Figure 3 will be the operating
point, so that a locking current into the node causes
the circuit of Figure 2 to have a high-voltage output.
Conversely, a locking current out of the node would
cause a low-voltage output (operating point 1 of
Figure 3).

FIGURE 2-IDEALIZED LOCKED-PAIR CIRCUIT
(INDUCTANCE AND CAPACITY NEGLECTED)
lIYI

1 BM B
A

+__+_

~_ _

0
5

EQUIVALENT CIRCUIT

2
Y8

-~-~-,,~~ ~\
\~~I
V

(Vp IpJ

----ANALyTIC
APPROXIMATION!

II
IiI

V
50

FIGURE3-CURRENT AND VOLTAGE RELATIONSHIPS .FOR
CIRCUIT OF FIGURE 2 FOR E-E,

100

)'
~k

/~
IYy,Iyl

200
250
MllI..IVOLTS

300

350

450

TYPICAL NEGATIVE CONDUCTANCE
CHARACTERISTIC

FIGURE I - TUNNEL DIODE

To understand the basic operation of the locked
pair, examine the idealized circuit of Figure 2, where
diode inductance and capacity are neglected. Assume
that tunnel diode B is the active element, and A is the

FIGURE4-RELATION OF CHARACTERISTICS NEAR CRITICAL
POINT OF SWITCHING

The locked pair is susceptible to a locking signal
in the region where the peaks of the diode characteristic
are crossing; thereafter it is relatively insensitive to
spurious signals.

234
5.3
A significant difference in diode peak current
produces the same effect as the locking current; hence,
the locking current must be large enough to overcome
the differences in diode characteristics.

400
EJOO

(I-COSI2WT)~/
."..-

/;V:e

The effect of source resistance on diode sWitching will now be examined. As in Figure 2, "tu-nnel diode
B will again be considered the active element. However,
the load curve now is the series combination ·of the
source resistance, R, and the V-I characteristic of
diode A. The source resistance affects the peak of the
load curve by moving it to a higher voltage. Hence, a
larger source voltage is needed to bring the characteristics to the critical point of switching, which is indicated quantatively in Figure 5A. Figure 5B indicates
the operating point of the circuit when the source voltage has reached an arbitrary maximum. The effects
of a high source resistance are seen as a delay in
switching, and a reduced output voltage.

/ I
/ il
/
II

.~,nU

"f\

20
I

\ 1\

I
I

\ \

1,\\

;\
)

\'\
\' r-.
\i\ \

://
'j

77
'I

I ii
00

__ v

\\
\

I-.

--1-.-,./

~
"-. ~

V
t
o/..v
VB

' " VB

T (NORMALIZED TIME)

FIGURE 6-WAVEFORMS OF IDEALIZED LOCKED-PAIR CIRCUIT
(INDUCTANCE AND CAPACITY NEGLECTED)

Ie
251-----+---+---+--+----+---+-----l---t--~

Computer Solutions

The technique related above and used for Figure 6
is invalid when the effects of capacitance and inductance
are appreciable. Through use of a digital computer, a
solution considering the effect of diode capacities, can
be easily realized. Such a computer solution excludes
the stray parameters associated with laboratory work
at high frequenCies, thereby disclosing the basic nature
of the circuit.

For the ensuing discussion a sinusoidal source
voltage is assumed, because it seems to be the most
practical waveform for driving a large number of
locked-pair circuits.

PRIOR TO SWITCHJNG

~
o

7~
I I~
~
7
!----ACTIVE ELEMENT

100

150

R-O

\~~5!l

t--

200

V
\/
}.

250

300

350

\
\

"'"Nve
450

MILLIVOLTS

AFTER SWITCHING
FIGURE 5- GRAPHICAL INTERPRETATION OF CIRCUIT IN FIGURE 2 FOR VA~IOUS
SOURCES RESISTANCES

The waveforms for the circuit of Figure 2 can be
obtained by making a point-by-point plot from the characteristics shown in Figure 5. The current and output
voltage waveforms in Figure 6 are plotted for a sinusoidal source voltage, and a source resistance of 5 ohms.

A d-c component is added to the sinusoidal source
voltage to keep the diode voltage from having negative
values. A negative voltage across the diode would
cause an wmecessary loss of power, and if the diodes
V-I characteristics are not well matched, the circuit
would exhibit an undesirable output voltage during negative excursions of the driving voltage. Therefore, the
source voltage will be of the following form as plotted
in Figure 6:
E

Kl - K2 Cos 2 1T ft

The values of Kl and K2 are somewhat arbitrary.
However, the d-c component, Kl, must be of such a
value that the minimum excursion of driving voltage is
less than the peak voltage of the diode characteristic
(Vp in Figure lB), otherwise the circuit will never relax. That is, the same diode will always go to its high
state regardless of the polarity of the locking signal.
For the problems solved on the computer, the chosen
d-c voltage component was equal to the peak sinusoidal
value:
.

235
5.3
The nominal inductance of RCA germanium tunnel diodes is 0.4 muhenries, yielding an inductive reactance of 1 ohm at 400 mc. Thus, for the values of
frequency and source resistance used in these examples,
the inductance of the tunnel diode may be neglected.
RCA germanium tunnel diodes (nominal 20-ma~
peak current) with identical nonlinear characteristics
are assumed. To facilitate compution, the programmers
developed an analytical expreSSion to approximate the nonlinear characteristic. The experimental
tunnel diode curve is compared with its analytic approximation in Flgure lB.

The first problem was solved for the circuit of
Figure 2 with diode capacity included. In order to keep
the problem as simple as poSSible, no locking signal
is applied; instead, the diodes switch because of the
difference in capacity. In this instance, diode B always switches to its high-voltage state because it has
the smaller capacity.

400

350

E/I

II I

30 0

250

100

)

l-/
o Lo

FREQ
MC

10
30
100
300
1000

140
47
14
47
14

0.4
o.s
06
T (NORMALIZED TIME)

0.3

I
/

0.2 volts, d-c component of source voltage
0.2 volts, peak value of sinusoidal component of source voltage

~
!

Ie \

'02

liB!

/
01

liB ...

I2B
fC

E=02(1-COS21TT)

Il 1\\:
~'
'. \:

5 ohms, the source resistance

0.&

sntf

/~~.".IIA

0.7

/" ~ ~

VOLTAGE WAVEFORMS

170
S7
17
57
17

ft, the normalized time (f = frequency in cps)

where:

t\VA

V
®

dVB

IVB

IS 0

are:

a-;- =

71
/

200

The defining equations derived from Figure 2
E

:..--~

'J
--"-'"

?4 o.s
06
T (NORMALIZED TIME)

V
\

\
\
09

"'-

CURRENT WAVEFORMS
FIGURE 7-TUNNEL DIODE LOCKED-PAIR CIRCUIT- BASE
FREQUENCY IOMC

Note that capacity and frequency appear only as
a product in the defining equations of the circuit.
Therefore, the waveforms can be interpolated for different values of frequency and capacity through use of
the relations:
170
CAil = 140 C BII

170 p.p.f, capacity of twmel diode A
140 ILlLf, capacity of tunnel diode B

Solutions were obtained for frequencies of 10,
30, 100 and 300 mc. The resultant voltage and current waveforms are shown in Figures 7 through 10.

** Both computer

solutions were obtained with the
assistance of R. W. Klopfenstein, Director of
Mathematical Services, and G. B. Herzog; RCA
Laboratories, Princeton, N. J.

where: fI is the frequency for which the waveforms
were originally calculated, and CAlI, CBII, and f II
are the new values of capacity and frequency for which
the waveforms are also valid.
From the voltage waveforms it is seen that switching is quite appa.rent at 10 and 30mc. (Figures 7A and

SA). Although some switching is evident at 100 mc.
(Figure 9A), it is not distinct. However, at 300 mc.
(Figure lOA) the diode capacity effectively shunts the
nonlinear element and switching does not occur. Also
note that at 300 mc. the diode voltages are almost sinusoidal. Examining the waveforms of Figure 6 which
neglect capacitance effects, in conjunction with the
waveforms of Figures 7 through 10, the effects of caacity become more clear. From the current waveforms it is seen that as the frequency increases, the
capacity retards the appearance of sharp irregularities
in the curves.

236
5.3

v~
! I 1\

400

jvB

1 \

150

100

;
o.L~V
0.

0.1

0..2

6
24

CA
pI

420.
140
42
14
42

5,0
170
51
17
51

... ..

f
II

8
6

._.IIA

/
0..1

0.2

0.3

0.1

CB-

0.2

,,
\~

\~.

0.5
0.6
T (NORMALIZED TIME)

; ,\

Ilk~l

0.4
0.5
0.6
"f' (NORMALIZED TIME)

I
/

0.8

\
\
0..9

118

CURRENT WAVEFORMS

\',
\

/
I

\
.....

- I'\..

0.3

~7\~o.i8

0.5
I

I
\
\\

/
'/

1\ ~

0..2

\
\

118_

••••IIA

V1
/"

1, iB

E(I).D 2(1-CDS 2" T)

I,'

0.
1.0.

10.

~f.~~.
1\
\

4
2

~
09

EU-

I
Ie

VOLTAGE WAVEFORMS

1711

oe-

/.'

4
2

1700
570
170
57

II /,"...

I'..
0-7

0.4

CA
pI

1400
470.
140.
47
14

I : \

S·'i.

10
30
100
30.0.
10.00

FRED
MC

~
~

I---

hIIB

......

0./
0.

liB!

'-,..- r'\:- ... --~/

~
I

I'Aj

~ ~

(

\
\

oL~
8

~ ,

!J
Ii

1.0.

Yf\

0.9

E(')

/r .. \

L / '/.~

VOLTAGE WAVEFORM

5fi

0.7

£(,)=0. 2(1-CDS21rT)

Ce
pI

10.
30
10.0
300
1000

~
®

FRED
MC

1\\

--1--

/ ' /I'Z

100

150

\1\

0.4
0.5
0..6
"f',i...NORMALIZEO TIME)

200

0.3

250

\\
\

/
1/ /
/
/
hVA

'" \

300

200

400

I"~

I..
/.:

1.0

~
T 1NDRMALIZED TIME)

FIGURE 8-TUNNEL DIODE LOCKED-PAIR CIRCUIT
BASE FREQUENCY 30 MC

C. Locked-Pair Circuit with Loading

From the previous discussion it should be noted
that the two possible voltage outputs for the curves of
Figure 3 are positive. To perform majority logic, it
is desirable to drive the locked-pair circuit from both
ends with voltages of equal magnitude but opposite polarity. The two possible voltage outputs of the circuit
will then be equal in magnitude but opposite in sign.
A typical locked-pair majority gate is shown in
Figure 11A. The locked-pair is controlled by the majority of n inputs (n must be odd), and in turn will deliver signals to m number of locked-pair circuits. The
input-output impedance of the locked-pair circuit will
be neglected as it is small in comparison with the coupling resistor. For majority rule, all but one input
current may be cancelled. Hence, the sum of the current inputs to the locked pair at a minimum is vo/Rc
where: Vo represents the output voltage of a lockedpair circuit and Rc is the value of a coupling resistor.
The equivalent circuit of the majority gate is shown in
Figure lIB.

® CURRENT

WAVEFORMS
FIGURE 9 - TUNNEL DIODE LOCKED - PAIR CIRCUIT - BASE FREQUENCV 100 Me

The circuit of Figure 11 was solved on the cOmputer for a fan-in and fan-out of six. (m = n = 3). As
in the first problem, equal tunnel diode V-I characteristics were assumed. The defining equations of the
circuit in Figure 11b are:
E

K (1 - Cos 2 1T T)

= 1A Rg +

VA + Vo

K (1 - Cos 2 1T T)

= IB Rg +

VB - Vo

10 Ro

= Vs

- Is Rs

[1-COS21T

237
5.3
400

350

250

/
1/

200

150

100

.-P
0.1

0.2

0.3

10
30
100

4200
1400
420
140
42

5100
1700
510
170
SI

o.S
0.6
T (NORMALIZED TIME)

28
24

"'" ~~
0.9

50 ohms, the equivalent
locking signal resistance

1.0

I
'~(~II ~
lIB

.-.....

,"..:,...

A..c'

/ ,/'

\
.....

L /.,'

.....

r\.

\
~2

.'.'

-!-\---

-'-'

.... /

0.9./'f'

~
t

1ft

OUTPUTS
(FAN-OUT!
CIRCUIT

EOUIVALENT CIRCUIT OF@.INCLUDING SOURCE RESISTANCE

FIGURE 11- LOCKED-PAIR MAJORITY GATE

the simulated equivalent locking
signal for n = 3

ft, the normalized time

The smaller values of capacity used indicate that
the diodes will switch at higher values of frequency than
those used in the first problem; therefore, frequency
values of 100, 300 and 600 mc. were used in this problem. As in the first problem, capacity and frequency
appear only as a product in the circuit equations; thus,
the waveforms become valid for other capacity and frequency values. The simulated locking signal, Vs, is
optimistic since it assumes the maximum output voltage of the locked-pair circuit is equal to the maximum
value of the source voltage E. Also, the locking signal
is assumed to lead the source voltage by 120°; however,
the actual locking signal is not only a function of the
Switching delay induced by the source resistance, ~,
but also is a function of the phase shift caused by tlie
capacitors. This may be seen by examjning the output
voltage and current waveforms in Figure 12 through 14.
From the figures, note that the output voltage
waveforms would barely be able to control the next
stage because the next stage lags by T/3. For more
positive control, the output voltage waveform should
be either shifted to the right .IT to .15T or be maintained for a longer portion of the cycle. Larger capacity would yield some positive phase shift, but only
at the sacrifice of amplitude. A decrease in source
resistance would increase the effective period of the
output voltage; but from practical considerations, 5
ohms is already small. One solution is to increase
the source voltage. An attractive solution would be to
use a larger source voltage and have it clipped.

-E
BASIC

"
~B

CURRENT WAVEFORMS

T (NORMALIZED TIME)

INPUTS
(FAN-IN)

.- \
"

lIB

!I!'••

FIGURE 10- TUNNEL DIODE LOCKED -PAIR
CIRCUIT - BASE FREQUENCY 300 MC

,/'.

50 ohms, the equivalent
load or output resistance

E(t)

-8

20 JLJLf

VOLTAGE WAVEFORMS

E(t)·0.2(1-COS21rT)

5 ohms, the source resistance

Y.:~

0.10 volts

'\~

1\
~ \

v
@

FREO
MC

~V- ~

300

1000

where:

V '\

In general, the current and voltage waveforms
for this problem are what would be expected after examining the waveforms of the first problem, i.e., the
waveforms become "smoother" and the voltage waveform of the diode in the high state (diode B) decreases
in amplitude as the frequency is increased. The output voltage at 600 mc. is almost zero. Although at
600 mc. , the neglect of inductance may not be entirely
valid, the waveforms indicate the restrictions placed
on the circuit by diode capacity alone.

238

5.3
"'-',

80.

26 0.
0.

180

160.

/
/

10. 0.

,.,

Vs_

'X'

/.
/..'

....~,r.

0.1

0.2

CA'C B
pf

30.
ICC
300
60.0.
1000.

667
20.
667
333
2

'\. 1\
\\

I
I
1

\\ "- /"
). "/
\\
....... ..~
K.~ ""-.
~
0..7

0.8

,IA'

E+

1/
//1
II
II

VS'33.3 [I-COS 211'

20.0.
60.
20.
10.
6

I \
// \

le-

0.-3

0.4
()!j
0.6
T (No.RMALIZED TIME)

0.7

-- ~

0.7

.........

0..8

1.0.

0..9

r+Ro.

1
10V~

r-;;18_

vsl

•

RS'RC'5C.o.

~'5.o.

- -

\\
\\
\ \

II
II

-l~~'--./j ' \'\
\J

;::.---

0.2

RQ
+
E_

0.3

0.5

'\..

0.7

I.\~

0.8

0.9

10.

r {NORMALIZED TIME)

0.8

0.6

E'ICD(I-CCS 21TT)
"s'3330-COS2'71'(T+\)j -

(T+-~)]

0.2

-" ,

)<'.....

VOLTAGE

\11 "

;)

0.5

:i -':-i I L

20.

0.4

10.

\ ""'-I
\

lirA
1/1

0.1

CA'Ce
pf

30.
ICC
30.0.
60.0.
10.00

RQ'5~

le//

FREQ
MC

RS·RL,5Q.o.

\
\\
\'

0.3

E'IDC( I-CDS 211'T)

..-/ ..........

0..2

1' .....

...,/ ~ ::?'

Rr l e •

I .:

~1:7"

,\1

'"\.

,/'

-~-

I VID
10

t-y

\
\

10.

0.9

./'

VOLTAGE

~~t-VA-

Vs _ _ -

- -

'r (NORMALIZED TIME)

20.

.....

40.

\\.

80.

"',

10.0.

'\. '\

-'f.

140.
0.

0.4
0..5
0.6
T (NDRMALIZED TIME)

@
FREQ
MC

160.

/1-"---,

./
0.-3

. . .i"

/'
/

180

120

20.0.

220.

20.

240

0.9

CURRENT

FIGURE 13- OUTPUT WAVEFORMS -BASE FREQUENCY 300 MC

10.

@ CURRENT
FIGURE 12- OUTPUT WAVEFORMS- BASE FREQUENCY 100 MC

The waveforms indicate that definite switching
occurs for a diode capacitive reactance to maximum
negative resistance ratio of 3 or greater. Consequently,
a conservative relationship for germanium tunnel diodes
in locked-pair circuits is:

240 . _

FREQ
MC

cA,c e

3D
ICC
30.0.
60.0.
10.0.0.

40.0.
120.
40.
20.
12

"'"

[ in megacycles

C1lrre~t I~ mnpampS)l

(capacIty In p.p. )

Figure 15 shows the waveforms at 300 mc. for
equal signal source and load resistors of 30 ohms.
The only noticeable effect of this increased loading is
to slightly decrease the output voltage. However,
upon increasing the power supply resistance from 5
to 10 ohms, the diodes did not switch at all (Figure 16).
D.

Graphical Interpretation of Loading

The effects of loading and source resistance,
neglecting capacity effects, can be predicted by graphical means similar to those indicated in Part A of this
paper. From the discussion of Figure 2, when element
B w~nt to its high voltage state, element A stayedinits
low voltage state. Since the voltage across non-switching

RC'Rs"D.o.

220.
E'IOD(I-CDS 21TT),
220.

'\
1\

120
10.0.

cl\IIs'333(I-Co.S2n[r+~r

.........

/
1/

0.1

0.2

...

.....

/.'
~.

_.1' ~

,/" •••• ~A.

-'v

140

160

250 fweak

VD
1

180.

r.witchi:::::::ru'J;L [

~Q
~~-:i I Rs.~-;-~
~}s

L"........
~

0.3

0.6

~"'"

~ ./

:>.:: ~...- ~

0..7

0.8

0.9

10.

T I NCRMALIZED TIME)

FIGURE 14- OUTPUT VOLTAGE WAVEFORMS-BASE
FREQUENCY 600 MC

element A remains less than Vp (Figure 18), element
A can be apprOximated by a resistance equal to Vp/lp.
Then, the equivalent circuit that is seen by active element B can be written from Figure 11. This Thevenin
equivalent circuit is shown in Figure 17 where:

239
5.3

24DI---+---+----+---+---I--t-----'--c-+-

~~~~~~~~~~2Tn\T+-~J)

2ZDI---+---+---+---+--E-+--/-¥~""'\+-

RS 'R

v:e

::1--_+-_-+-_

'30!/.

__+_-+/-+//-/-~/~.1-.__+_.,,~,~.+~~-~-j.~5n~~::::::

1~.~--~~---4r/--+---+V--_+--\~\-\+_r_--~__r
J

120.

-'\+---l--+--+

IOO~~---+-+/-+--~~/~---+-=-+~\\~\~--~--+
/

''-l

D~4~-_-+,~~/~,~~~~-/~~~~t~-r-+
DI--~~~~~~-~L---I~?-·-I--

+-~~--+-_+

-_+---.:-dL·/-+-----j~·;a~.t---+~A-+-+--+--\-\+---:'''_r_+-;..Li'_l_/
2D'I--~~-/~~~~4V--~~'-'74~V--_+'~~_+---\~~·>.~/--_r

40.1-1--

~~/~~~~9=~===±===1~=__~~,~-~_"'~~~~-~~~~~~~~~~~

Do.

0.1

0.2

0.3

0.5

0.6

0.7

0.8

0.9

10.

T (NDRMALIZED TIME)

FIGURE 15-0UTPUT VOLTAGE WAVEFORMS WITH INCREASED
LOADING-BASE FREQUENCY 300 MC

FIGURE 18-GR,APHICAL INTERPRETATION OF LOCKED-PAIR LOGIC GATE (FIGURE II)

FREQ
MC

CA,ce

30
10.0.
30.0
60.0.
10.0.0.

20.0.
60.
20
10.
6

,.,

...

1//

ISO

//
140

120.

I
0.
~S_ _

.. I

/
/
/

0.1

,
I,

,.,';../

~
- - VA-

0.3

+ Rg , Thevenin equivalent re-

_ VpA
r A - ---, linear approximation of element A for VA
IpA

(Rg+rA)RL

sistance

0.4
0..5
T (NDRMALIZEO TIME)

0-6

l:>-- F0.7

0.9

where: IVB is the valley current of the tunnel
diode that is in its high voltage state, and the
other parameters are as previously defined.

240

5.3
the diodes will not switch when the source impedance
is increased from 5 to 10 ohms, as seen in the computer waveforms of Figure 16. The criteria for diode
Switching, as affected by loading and source resistance, is determined from Figure 18.

where: VpB and IpB are the coordinates at the point
of peak current from the characteristic of the diode
that is expected to go to its high state.
All the calculated results agree with the unpublished experimental data, and show that a digital
computer Is a powerful aid in the analysis of such
complex nonlinear circuit problems.
FIGURE 19- GRAPHICAL INTERPRETATION OF CIRCUIT IN FIGURE II USING ANALYTIC
APPROXIMATION OF TUNNEL DIODE CHARACTERISTIC (SAME PARAMETERS
AS USED FOR 2nd COMPUTER SOLUTION)

Reference

This equatlon was obtained from Figure 18, and
was based on the assumption that the current in the
active element is near the valley of the V-I characteristic. This approach may be used where the diode
capacitive reactance is at least ten times the magnitude of'the maximum negative resistance.
From Figure 19 it can be seen that the load line,
RT, changes very little when the total load resistance
is decreased from 25 to 15 ohms. as was noted in the
corresponding computer waveforms of Figures 13a
and 15. Also predicted in Figure 19, is the fact that

1. Personal Communication with A. W. Lo.
2. ''Esaki_diode High-Speed Logical Circuits. "
E. Goto, mE Transactions on Electronic Computers,
Vol. EC-9, March 1960.
3. "Semiconductor Diodes in Parametric Subharmonic
Oscillators." J. Hilibrand and W.R. Beam, RCA
Review, June 1959.
4. "A New Concept in Computing." R.L. Wigington,
mE Proceedings, Apri11960.
5. ,tNegative Resistance Elements as Digital Computer
Component." Morton H. Lewin, Eastern Joint
ComI!uter Confere~ce Proceedings 1959.

241
5.4
ON ITERATIVE FAC'l'ORIZATION IN NE'NORK ANALYSIS
BY DIGITAL COMPUTER*'

VI.H.Kim, D.H. Younger
Department of Electrical Engineering
Columbia University
New York 27,N.Y.
C. V. Freiman**', W. Mayeda***
International Business Machines Corporation
Yorktown Heights, New York
Abstract
The need to determine the sum of all tree
admittance products occurs in almost all applications of topological network theory. This
paper describes a method of obtaining this sum
through an i terative factorization of the sum
of tree admittance products of successively
more complex subnetworks. Computational efficiency is achieved in that: (1) it is not necessary to test sets of branches for the presence of circuits; and (2) it is not necessary to calculate each tree admittance product ..
A digital computer program has been developed for use on an IBM-704 which accommodates
any netWork with complex branch admittances and
up to 14 nodes. Far more complex networks
ma.y be anaJ.yzed, however, if they are first decomposed into two-terminal subnetworks. A
detailed description and flow chart of the program are included.

Introduction
Although classical network theory has long
permitted the a.na.l.ysis of arbitrarily large
networks of prescribed form, it is only through
the. use of topolOgical methods and high-speed
digital computers that it has became possible to
ana.lyze a general RLC-network of any appreciable
size. At a given level of theoretical and
mechanical developnent, the practical limit on
the size and complexity of a network which lDa\Y
be analyzed is largely determined by the efficiency of the algorithms used to implement the
various topological network theorems. This
paper seeks to improve this efficiency through
use of a new method for computing the sum of
tree admittance products -- a quantity used in
almost all applications of topological network
theory.

Let us canpider an RLC-network of e elements and n nodes, and let us use N to
denote the graphical representation of the network. A number of authorsl ,2,3 have discussed
the generation of the sum of tree admittance
products in N,T(N), and, in general, the
methods they propose are based on:

(1) Determination of the trees of N by
testing each combination of edges taken (n-l)
at a time for the presence of circuits; and
(2) Calculation of the admittance product
corresponding to each of the trees determined
above.
The method we shall present utilizes the
decomposition procedure introduced in [4] to
compute T(N) in terms of the sums of tree adm.ittance products of the various subgraphs of
N. In practice, T is first determined for 3node subgrapns, then for 4-node subgraphs.
This iterative process continues until T(N)
has been calculated. In this way, it is never
necessary to test for the presence of circuits,
and no admittance product is ever individually
computed.
1.

Let N represent a connected, non-oriented
weightea graph. with n nodes and e edges.
(The term ''branchll may be substituted occasionally for "edge" but the term "element ll will
only be used in the sense of "element of a network" or "element of a set.") The sum of the
weights of all edges which are incident on both
node i and node j (i 1= j) will be denoted
by Wij. The method we shall use to determine
T(N) is based on the following iterative procedure.
1.

!b1s work was supported by National Science
Pbundatio"ll Grants 0-3676 and 0-6020.

Formerly at Department of Electrical Engineering, Columbia Uni versity, New York, N. Y.

***Presently at Department of Electrical Engineering, University of Illinois, Urbana,
IJ.J..~Oi~.

Iterative Determination of the Sum
of Tree Products

Select a generating node, say node n.

2. Partition the remaining (n-l) nodes
into k subsets in all possible ways for
k = 1, 2, ••• , n-l. (Example A illustrates
the partitioning for a particular 4-node
network.)

Example A
Node 1 is chosen as the generatins node.
(See Fig. 1.)

242

5.4

Identification
Number of Partition

1
2

Identification Number
of Partition Element:
1
2
3

(4)

3
4

(432)
(32)
(43)
(42)

(4)
(2)
(3)

(2)

(4)

(3)

(2)

Table I.

Substituting (4) in (3) we have

4. We may now express the sum of tree products for graph N as

=
-

r. S7i [T(N ) r.
IJ.

IJ.V

m
i€N
IJ.V

]}

(1)

,-,here T( NlJ.v) is the sum of tree products:fOr
subgraph NlJ.v, n is the generating node, and
i is any node in NlJ.v. If NlJ.v consists of a
single node (e.g. N32 of Example A), then
T(~~v) = 1; if NlJ.v is non-connected,
T(NIJ.'() = O.
The maximum possible number of nodes in
NlJ.v is (n-l). Therefore, the problem of finding tree products in an n-node net"imrk has been
changed into one of finding tree products in net"orks with at most (n-l) nodes. If (1) is
applied to NA, Fig. 1, as partitioned in Example A, "ive determine the sum. of tree products of
NA to be
T(NA)

T(Nll)'(e+f) + T(N2l )'(e+f)'T(N22)'O

+ T(N3l )·e'T(N32 )·r + T(N4l )·f'T(N42 )·e
+ T(N5l)·O.T(N52)·e'T(N53)·f

T(Nll)'(e+f) + T(N3l )T{N32 )'ef
_ + T(N41 )T{N42 )'ef

T(NA)

[(b+c)(a:+d) + ad](e+f)idef+e.ef

(5)

bae + bde + cae + cde + ade + bat
+ bdf + cat + cdf + ad! + def + aef

(6)

PartitiOninff of the Set
of Nodes (32)

3. Associate sub graphs with each element
of each partition as follovs. .An edge of N
'fill be included in NlJ.v' the subgraph associated with the v-th element of the IJ.-th partition, if and only if both of the nodes u:pon
'i.,rhich it is incident are contained in the v-th
element of the IJ.-th partition. (It is sufficient that orderings of both :partitions and
elements exist. The nature of these orderings
is uni.m:portant.) Fig. 2 presents the various
NIJ.V ,.,rhich are derived from the graph of Example
A.

T(N)

At this :point we observe that T(N32) = T{N42)
= 1, T{N3l) = d, and T{N4l) = a. We may
reuse (1) to obtain T{Nll) as

(2)

If equation (l) is applied to a 3-node graph,
the sum. of tree products of any subgraph is
either 1 or a sum. of edge-weights (e. g.
T{N2l) = b+c in Fig. 2b). Thus, in actual computation, we first calculate the sum. of tree
products for all 3:node subgraphs of N which
do not contain the generating node. These are
then used to find the sum. of tree products for
4-node subgraphs. This process is repeated
until we have calculated T{ N) itself. Example
B demonstrates the actual method of computation, but', for clarity, does not completely
reflect a computer solution. In Appendix B,
the graph of Fig. 3 is solved in the manner of
the computer solution.
Example B
(See Fig. 3). In any subgraph of N,B, the
highest numbered node will arbitrarily be chosen
to be the generating node. The symbol
T(abc ••• k) will denote the sum. of tree products for the subgraph which is formed from the
original graph by removing nodes other than
abc ••• k and all edges incident on these
deleted nodes. Thus, in NB, T(124) = at.
T(123)

T(12). (c+bfe) + (b+c)e
= f(b+c4e) + (b+c)e

T(124)

T(134)

T(234)

(b+c)(a:+d) + ad (Eq. 4)

T( 1234)

Hb+c)( aid)

+ ad]( e+f) + def + aef
(Eq. 5)

(9)

These constitute the sums of tree products
for all subgraphs of N:s vrhich do not contain
node 5. We nOiv determine T( N:a) to be
T(NB) = T(12345) = T(1234).-{gfb.) + T(124)'hg
+ T(234).hg + T(12)h'T(34)g

+ T(14)'h'T(32)g
(3)

(8)

(10)

243

5.4

T(~)

= {[(b+c)(a-Kl) + ad1(e+f) + def
+ fahg + [(b+c)(e:+d) + ad]hg

+ aef}(gfh)

Equation (11) results from the repeated
application of (1) to NB and various of its
subgraphs. Some idea of the effort require~ to
apply equation (1) to graphs of varidUs sizes
may be had by consulting Table II where the number of unique partitions for n-node graphs
(n = 1,2, ••• , 13) are tabulated. If the original graph contained seven nodes, then, after removing the generating node, all possible 3,4,5
and 6-node graphs would nave to be inspected.
From Table II, we see that a 6-node graph may
be partitioned in 203 unique ways. The corresponding numbers for 2,3,4 and 5-node graphs are
found to be 2,5,15 and 52. Thus, the number
of different partitions which must be considered
is found to be

+ fhdg (11)

As each edge of N:s has been uniquely identified, expanding (11) would result in an enumeration of all of the trees of NB. On the
other hand, if each edge were assigned a numerical value and only T(NB) were desired, only
those equations corresponding to (1) ,.,ould be
employed. T(N:s) is calculated in Example C
for a particular assignment of numerical values
to the edges of NE.
Example C
In Fig. 3, let

6
6
6
6
(3)·2 + (4)·5 +(5).15 + (6).52 + 1·203

a=c=e=g=l

and

(12)
When calculations involving this many partitions
are to be carried out, it becomes essential that
a reliable method of generating partitions be
found. This could lead to the use of a table of
partitions but, for computer calculations, the
follOwing procedure is preferable.

b=d=f=h=2
T(123)

= 2(2+1+1)

T(124)

= 1·2 = 2

T(134)

= 1·2 = 2

T(234)

= (2+1)(1+2) + 1·2

+ (2+1)1= 11

1. Choose one node, say node 1.
partitioned in only one way.

= 11

T(1234) = 11(1+2) + 2·1·2 + 1·1-2 = 39
T(~)

= 460

= 39(1+2) + 2·1-2 + 11-2·1 +

It can be

2. Add one node to the previously partitioned set of nodes increasing the number of
nodes from k to k+1. For each partition of
the k nodes into a subsets (a = 1,2, ••• ,k)

2-2·2·1 .

= 151

t3: number of elements in set to be partitioned
a: number of partition
elements
1
2
3
4
5
6
7
8
9
10
11
12
13

1 2

3 4

1 1 1 1 1 1
1
1
1
1 3 7 15 31 63 127 255
1 6 25 90 301 966 3025
1 10 65 350 1701 7770
1 15 140 1050 6951
1 21 266 2646
1
28 462
1
36
1

10
1
511
9330
34105
42525
22827
5880
750
45
1

1 2 5 15 52 203 877 4140 21147 115975

TOTAIS

Table II:

1
1
1023
2047
28501
86526
145750 611501
246730 1379400
179487 1323652
63987 627396
11880 159027
22275
11~
1705
55
66
1
1

1
4095
265720
2532530
7508501
9321312
5715424
1899612
359502
39325
2431
78
1

678570 4213597 27648528

The Number of Uni ue "\-fa; s in Hhich Sets of t3 Elements Can Be
Partitioned Into a-element Partitions nat3

Note that na ,t3

(a,t3 = 1,2,3, ••• )

244
5.4
form ~l partitions of the k+l nodes as follows. Form one partition of (~l) elements by
using the new node as an additionaJ. element; form
ex partitions of ex eleJnents by adding the new
node to each of the ex elements of the original.
partition in turn.
3. Repeat
partitioned.

until all nodes have been

I:f' the sums of tree products for all newly
developed subgraphs are generated at each step,
then this method allows a straightforward determination of the sum of tree products for the
overa.11 graph. Example D illustrates this for
N , the graph Qf Fig. 3.

Example D
Graph
nodes
selected

partitions

of Fig. 3
sum of tree products of
new1Y introduced subgraphs

'WOrk 'With as many as fourteen nodes provided a
32,168-Word maguet1c core storage unit is
available.
A block diagram showing the functional steps
in the overaJ.l calcul.a.tion is given in Flow
Chart I. Appendix A supplies deta.ils about the
format and execution of the various functions.
Appendix B demonstrates the method by which the
progr~ bandles the calcul.a.tion of T(N) for the
network considered in Section 1, Example B.

Note that the program makes a. dist'inction
between those nodes connected to the generating
node and those which are not. After a subgraph
has been selected and a generating node chosen,
the initial partitioning does not involve all
the remaining nodes of the subgraph but only
those nodes which are connected to the generating node. The unconnected nodes are then distributed among the elements of each partition
in all possib1e ways. The possibility of ever
having
E

1~N

1
1,2

J.LV

= 0

(13)

is avoided in this way.
1,2,3
The two potential limitations on any program whi9h caJ.culates the sum of tree a.dmittance
products are memory capacity and computer time.
Either or both 'Will limit the size and generaJ.i ty of the network 'Which may be analyzed.

1,2,3,4

T(134)

= ed

T(234) =

(bie).(artd}kW.
(Eq. 8)

T(124)

= fa

T(12;4) =

= [(bie)(artd)+ad](e+f)

+ def + a.ef

T(N:B) may now be caJ.cu1a.ted as in Eq. (11).
2.

Computer Determination of the SUm
Tree Admittance Products

The digital computer progr~ discussed in
this section was written for use on an IBM 104
and is designed to ca.lcu1a.te the sum of tree admittance products for an electrical net. .rork in
·which the branch admittances are expressed as
complex numbers. FOr input purposes these net...-rork admittances must be combined in such a form
that no more than one branch exists between any
pair of nodes. The progr~ . .-rill accept any net-

The problem of memory capacity is revealed
by the table of partitions, Tab1e II. For
n ~ 9, there are simply too ma.ny partitions for
them all to be developed in the computer core
memory at one time. The need to conserve computer time prohibits the use of any of the other
computer storage devices. To perform such an
extensive set of calcul.a.tions 'With a limited
storage capacity, the program must use an efficient procedure 'Which generates a few partitions,
evaluate3 these and stores the partial sum, generates a few more, etc., until all partitions have
been generated and evaluated. A re-examination
of the method used in generating the partitiona
of Example D indicates such a procedure. In
that example, the partition involving node 1
alone is developed, from this partition all partitions involving nodes 1 and 2 are developed, all the partitions involving nodes 1, 2,
and 3 are developed from these, and finaJ.ly all
partitions involving four nodes are developed.
In general., the method. generates all partitions
involving k+l nodes from a lmowledge of all
those involving k-nodes. However, it is
possible at a:ny stage to find those k+l node
partitions corresponding to only one of the knode partitions, then to find those k+2 node
partitions corresponding to only one of the k+l
node pl.rtitions, etc. When all the partitions
generated by a single k-node partition have been
utilized, then the 1*1 node partitions corresponding to another k-node partition are gene-

245
5.4
Flow Chart I
Start of Program
-I'"'

'I'

Step 1:

Have all groupings of 0 nodes
out of n-l been evaluated?
No
Yes

Set n = number of'
nodes in network.
FOr each :pair of nodes, store edge
weight of connecting branch.
Let 0=3.

Does o = n?

~~ ...
,~

Step 2:
Generate next grouping of
0 nodes out of n-l (generating
node for overall ne~vork not included).

Increase
0 by 1-

'I'

Step 3': Detehnine ,.,.hich nodes are
connected to generating node for over~
all graph.

-------

Step 3:
Select for each grouping a
generating node; determine 'VThich of
the remaining 0-1 nodes are connected to it.

"
step 4' :

Yes

N.o

Select generating node
for overall graph.

Same as Step 4 for overall
graph.

Step 4:
Generate next set of partitions of connected nodes. Evaluate
product term for each.
Step 5':

Same as Step 5 for overall
graph.

Step 5:
For each partition of connected nodes, assign unconnected nodef
in all possible ''fays. For each resultant :partition evaluate product term
and store cumulative sum.

,II

Have all partitions been
evaluated?
No
Yes

Have all partitions been evaluated?
Yes

Step 6: Store sum of tree products
for subgraph in memory.

Step 6':

...

Print
graph.

T(I~)

for overall

End of Program

246

5.4

rated, and these made use of in turn. In this
manner, alJ. the partitions may be generated.
Perhaps the method will be clarified by
reworking example D. Th~ object is to develop
the fifteen 4-node partiti-bns in such a way as
to retain the smallest number of partitiona in
JlM!DDOry at any one time. In Example E, which
shows the successive stages of the developnent
of these partitions, X indicates that the product term is evaJ.uated at that stage and added
to the cumulative sum. Note that at no stage is
it necessar,y to retain more than five partitions
in memory.
Exm!q?l.e E

Development of 4-node partitions by an
1terat1ve procedure, illustrat1ng a saving 1n
memory capacity.
(1)

~1)(2)
12)

~1)(2)

...

(1)(2)(,)
!131(2
1)(23 (4)

...

r)(2 H')(41
14)(2Wj

X
X
X
X

123)

r)(2) 1
~ 12H3T
124)(3
12)(34

...

...
X
X
X

11)(2)~)

13)(2l
1)(23

(1)(2)(3)

X
X

l34)(2~
(13)(24

...

123)(4) X
X
1234)

14)(23~
1)(234

~13)(2)(4)

Conclusions

(1)(2)
f12)(3)

12){3)

1~~24 3
1 2)(34

rated by adding the new node as a separate
element , it is not even necessary to divide out
any factor. The case in which one or more of
the factors is zero must be treated carefully
but provides no serious problems. The use of
this procedure is illustrated in Appendix B.
However, its usefulness is only appreciated by
considering a partition of-many elements -- say
twelve. In evaJ.uating such a partition we may,
instead of performing the twelve multiplications
of the element factors, perform one division
and one multiplication. Of course, it is not
just as simple as the above com,parison would indicate, since we must provide additional bookkeeping and also evaluate the partition products
for those inte:rmed1ate partitions used in the
generation.

X
X
X

The significance of this saving of core
stol'8ge is better appreciated by considering a
12-node subgraph. Table n shows that there are
over 4 m1ll1on 12-node part1t1ons. Yet it is
poss1ble to generate &ll of them. and evaJ.uate
the product term for each without ever retaining as many as one hundred partit10ns at any
time. These part1t10ns, being so few in number,
may be stored in memory in a convenient and effic1ent manner. For, the sake of programming
convenience, twelve storage locations are set
aside to retain a single partition of 12 nodes;
nonetheless, the total storage for partit10ns is
so small as to be negligible.
In evaluating the product term for the part1tions, a saving in cam;puter time has been
realized by orga.n:f.zing the canputat10ns to take
advantage of the i t~rhtive developnent of the
partit1ons. Oons1de; once again the part1tion
developnent given in Example E. The part1t10n
product for each 4-node partit10n may be evaJ.uated separately, and the sum cumulatively stored.
But each 4-node part1t10n is derived from some
3-node part1tion by altering at most one part1tion element. If' the ,-node partit10n product
has been evaJ.uated, each 4-node product derived
from. 1t may be evaluated by dividing out the old
factor and multi~ by the factor which replaces 1t. For those partitions which are gene-

The importance, in calculating the sum
of tree products for any graph, of using a
factored expression involving the sums of tree
products of the subgraphs, can be seen in the
following comparison. There are associated with
a 12-node graph (or network) N in which an
edge connects each pair of nodes 1210 or apprOximately 6.19 x 1010 trees. In analyzing
this network by our method, the product term of
Eq. (1), Section 1, must be evaluated for each
of 1.52 x 106 groupings of subgraphs. Thus in
a 12-node network, there are about 4 x 104 times
as many trees as groupings. Even these groupings
are not evaJ.uated separately; the iteratIve nature of the develolJll8nt of the groupings permits
evaluation of cOlIDIlOn factors of these products
once for many groupings. Since there are for a
given network many less groupings than individual
trees and since even these groupings are evaluated in factored form, a program based on our
method is potentiall.y orders of magnitude faster than any method which requires the calculation of individual. tree aiJmittance products.
The method by which T(N) is calculated
does not depend on any special structural characterist1cs (i.e. ladder or lattice structures,
etc.) of the network N. Networks of com.pl.etely
arbitrary topology and branch weights may be
analyzed provided the number of nodes in the
network does not exceed the prescribed limit.
However, networks of interest often contain
subnetworks which are connected to the rest of
the network through two' te:rm1nals only. In
such a case, the calculation can be shortened
by determ:1n1ng the driving point aiJmittance of
the two term:1nal subnetwork, which then is replaced in N by a single branch whose weight
is the complex aiJmittance of the subnetwork at
the frequency under consideration. The use of
such simplification, where poSSible, will greatly reduce the cam;putation t:tme.
MaeWilliams2 cited an example of a network of 11 nodes and 21 branches which requires ,0 minutes of IBM 704 time. 'Whether
the network had any topological characteristics
which simplified the cam;putation

247

5.4
is not known; further, it is presumed that the
edge weights of the branches were restricted to
:Pure real or pure imaginary values. For a network with 11 nodes, and arbitrary topology,
which may contain as m.any as 55 branches
each of .'which has a complex weight, our program
estimates less than 30 minutes in computation
of the sum of tree admittance products.
There are several ways in which the efficiency
and usetulness of the program may be extended.
The first modification, a simple one, effects a
considerable sav:t.ng of computer time wen the
network under consideration reflects a minor
change from the network previously investigated.
After a particuJ.ar grouping of a nodes out of
n-l has been generated, step 2 of Fig. 5, this
subgraph is tested to see if any of its edges
have been modified fram those of the network
previously anaJ.yzed. I f none have been modified, the value for that subgraph will already
be in memory and the program can proceed :f.mmediateJ..y to the next grouping.
A more general and useful calculation than
that perfo:rmed by the present p-ogram is to find.
the sum of tree admittance products as a function
of frequency. That is, instead of the input
edge weights expressed in tems of complex numbers, let these weights be given as a rational
function of frequency. The resultant sum of
tree products would then be expressed as a camplex function -of frequency. To solve this more
general. problem, certain modifications of the
program are needed, particularJ..y the method of
evaluation of the partitions. None of the difficulties involved appear to be of a fundamental
nature, although the camplexity of the network
which could be analyzed would be restricted.

A further extension is a program which considers any one of the network edges a variable
admittance. With this additional modification
the program couJ.d be used to directly calculate
the input admittance of a given network looking
in at any pair of terminals as a function of
frequency.

Appendix A
Programming deta:lls and format are given for
each of the furlctionaJ. steps indicated in Flow
Chart I, Section 2.

Stet? 1.
The value of n and the edge weights are
supplied on punched cards. For the latter there
is, for each pair of nodes in the network, a
card on which is punched two numbers designating
the nodes (such as 2-6) and also the real and
the 1maginary parts of the complex admittance
of the branch connecting the nodes. Where no
branch exists in the network between two given
nodes, the value zero real and zero j]Dsgf nary is
supplied. For non-zero admittances, the values
are given in floating point decimal using the

stande.rd decimal card code. The allowable range
of floating point decimal number~is approximateJ..y n x 10-37 to i1 x 10+..J I and zero.
With regard to these limits, same caution must
be exercised since these limits apply not only
to the input edge weights but to the numbers
arising from all calculations in the program.
After translating these branch weights into
floating point binary, ~e program stores them
as part of a larger table in core memory. !Jh1s
table will eventually contain the sum of tree
admittance products for all subnetworks; the input edge weights constitute the 81m of tree products for their two-node networks.* This table
will occupy two blocks of 2n - l memory locations,
one block for the real parts of the admittances,
one for the imaginary parts. Note that the exponent is n-l rather tban n since only those
subgraphs not including the generating node for
the overall graph will be analyzed. It is the
size of this table, 2n locations, which 11m1ts
the size of the network which may be analyzed.
For n = 14, ~ = 16,.";84 locations or onehalf of the core storage of a 32, 768-word memory
unit. This is one reason that the program is
limited to networks of not more than fourteen
nodes. The generating node will arbitrar1l.y be
chosen as the highest-numbered node.

This step generates the various groupings
of a nodes out of n-l. The format used
throughout the program to indicate a given
grouping of nodes is a simple one: the last n
binary positiom of the 36-bit computer word.
gives, in positional notation, the nodes considered. The subgraph, of a 6-node graph consisting of nodes 1, 3, 5 and 6 would be coded as
shO'Wll in Fig. 4.
To generate all groupings of a nodes out
of n-l, all binary numbers fram 1 to 2D-l
are first generated, along with the binary weight
of the number in the unused upper portion of the
word. From this set of 2D-1 binary numbe;t's
are chosen, in turn, those of lteight a (where
a = 3,4, ••• ,n-l). This is equivalent, according
to the format, to choosing all groupings of a
nodes out of n-l for a = 3, a = 4, etc.

It is necessar,y to select for each subgraph a generat~ node. The left-most binary
unit corresponding to the highest numbered node
is always selected. The rema.1n.ing nodes are
separated into two classes, those connected to
the generating node, and those not connected.
A node is considered connected i f either the
real or the imaginary part of the aiIm1ttance of
the branch connecting it to the generating node
* Actually the weights of input edges, where
one node is the generating node for the overall graph, will have to be stored in a separate table.

248

5.4
Flo" ahart II

From Step 3

Choose one connected
node; it can be partitioned in only one
way.

Evaluate for this
, partition the factor
' introduced into the

Proceed to

St~ [2.

p~duct.

Ir-

)

Add a second node to ~
the previously partitioned set· of nodes
fOrming the new par-

t~s
Divide out replac.. ed factor in partition product and
multiply by new
factor.

Evaluate for first
.. (or next) partition
' the new factor introduced.

t-tt1onA.

Does n
No

= 37
Yes

~Add

Evaluate, etc.

---~

.
,.

partition pro-

Divide out,
etc.

Np
Y~s
Is there a 3-node
partition that has
not been used?

J,
Does n
No

ducts~.cumulative

Add a third node,
etc.

Ni;>

Is there a 2-node
partition that
has not been used

= 41
Yes

'[\

JAdd partition product to cumulative
sum.

_-1-.

....,
)\

Yes
No
Is there a 4-node
partition that haf
not been used?

'I'

---

•

Add a thirteenth
node, etc.

Evaluate,
etc.

Divide out,
etc.

Yes I
ko
Is there a l3-node
~ition that has
[not been used?
1\

~
Does n

= l4?
Yes

,. Add partition pro-

duct to cumulative
Alnn

249
5.4

is non-zero; if both real and imaginary parts are
zero the node is considered unconnected.
Steps 4 and 5

Step 1
Set n = 5.
t:

The method of generating partitions for the
connected nodes, with the distribution of the
remaining nodes among the elements of each ~
ti tion in all possible ways, and the evaluation
of the product ter.m for each,constitutes the
core of the program. The structure of this
section of the program is quite complex. The
manner in which it faces the two potential limitations of the program, memory capacity and
computer time, has been given in the body of
the report.
To clarify the structure, a block diagram of
these two steps is shown in Flow Chart II. In
this diagram there is, for reasons of simpliCity,
no distinction shown between the treatment of
the connected nodes and the unconnected nodes.
The only distinction which the program makes
bet'treen the two is that unconnected nodes are
never permitted to occup,y a partition element
by themselves, since such a partition would
make no contribution to tbe sum of tree products.

Nodes
1 2
1 ;
1 4
1 5
2

;

2
2
3

0
0
0
0
0
0
0
0
0
0

5
4

;

5
5

Select node 5 as generating node.
Step 2
Generate all binary numbers from 1 to 24
to determine all possible groupings of nodes 1,
2, ; and 4.

Nodes
4

;

After all the partitions have been generated,
and evaluated, the cumulative sum, vThich is now
the sum of tree products for the subgrapn under
consideration,is stored in the appro~riate location of the table mentioned in connection with
step 1. The program then proceeds to step 2
unless all groupings have been considered. In
step 6', the sum of tree products for the overall graph is evaluated. It is translated back
to floating point decimal and the resuJ.t printed
out. If the va.1ues of the sum of tree products
for any subgrapns are desired, these may also
be translated and printed, out using the same
routine.
ApPendix B
The follOwing analysis of the network of
Fig. ; closely reflects the actual computer
solution. 'lhe numerical values of the edge are
those used in Example C, Section 1.
a
b

e = g

The steps ;'Thich are deSignated correspond. to
those given in the flow chart shown in Section
2, FlO'tv Chart I.

T(123)

T(124)

T(134)

T(234)

T(12;4)

250

5.4
Let

ex = 3.

Choose node 3 as generating node;

Partition

nodes 1,2 are connected.

New factor in product term

T(1)W31 = 1-1 = 1
T(2)w32 = 1-3 = 3
T(12)(w31+w32 ) = 2(1+3)

(1)

(1)(2)
(12)

= 8

Store T(123)

Step 6

Product term

Partia.l sum
of iroducts

1-3 = 3
!~8 = 8

3
11

= li_

T(124)
~

Choose node 4 as generating node;

node 2 is connected, node 1 not connected.

Steps 4 and 5
Partition

4
3 {

T(2)w42 = 1-1
T(12lw4i'kY42)

(2)
(12)

Store T(124)

Step 6

New factor in product term

=1
= 2· (0+1) = 2

= 2.

Product term

1
!.2
1

Partia.l sum
of oducts

T(134)
Choose node 4 as generating node;

node 3 is connected, node 1 not connected.

Steps 4 and 5

4[
Step 6

Partition

New factor in product term

(3)

= 1·2 = 2
T(13*4iw43) = 1(0+2) = 2

Product term

Partia.l sum
of products

T(3)w43

St~r! T(134) (:3h.

T(234)
Choose node 4 as generating node; nodes 2 and 3 are connected.
Partition

New factor in roduct term

T(2)w42 = 1-1 =1
T(3)w43 = 1'2 = 2
T(23)(w42~v43) = 3(1+2)
store T( 234)
Let

= 11

= 9

Partial sum

Product term

of iroducts

1·2 = 2
1·9
=9
1

= 4.
Choose node 4 as generating node;

nodes 2, 3 are connected, node 1 not connected_

251
5.4
Steps 4 and 5
Partition
(2)

Ne,., :factor in product term

(2)(3)

T(2)vT = 1·1 = 1
42
T(3)-tv42 = 1·2 = 2

1·2

(23)

T(23)(i-T42~v43)

= 9

!·9

(12)(3)

T(12)(W·41~v42) = 2(0+-1) = 2

(2)(13)

T(13)(W41+w )
1(0+2) = 2
43
T(123)(w41+W42~v43) = 11(0+-1+2)

i·2

=9
=4

g.2 = 2

2.33 =33
9

(123)

Step 3 t

= 3(1+2)

Store T(1234)

Node

Partial sum
o:f products

Product term

= 23

= 39.

is generating node.
Nodes

and 3

are connected, nodes

2 and 4

not connected.

Steps 4' and 5 I
Partition

Nffil

T(l)W = 1·2 = 2
51
T(3)w
1·1 = 1
53
T(13) (l-T +w ) = 1(2+1)

(1)

51 53

T(12)(l-T +w ) = 2(2+0)
51 52
T(23)(w +w ) = 3(0+-1)
52 53

(12)(3)
(1)(23)

2·1 = 2
2
~

~.4 = 4

g·3

= 2(2+OfO)

*.4 = 4

(124)(3)

T(124)(w51~v52+W54)

(12)(34)

T(34)(\V53+w54) = 2(140) = 2

~.2
=8
1

(14)(23)

T(14)(w51~T54)

(1)(234)

= 0(2+0) = 0
T(234)(w52-kT53-kv54) = 11(0+1+0) = 11

6
2".0 = 0·3
6
"3.11 = 22

(123)

T(123) (w51+w52+w53)

= 11(2+0+1) = 33
T(1234)(1v51-kT52+w53-kT54) = 39(2-1-0+140)

~'33 = 33
33'117 = 117
33

(1234)
Step 6'

151

Partial sum
o:f products

(1)(3)
(13)

Product term.

:factor in product term

= 4

= 117

4
12
12

151

Real
Imaginary

End o:f Program.
Bibliography
1.

Mayeda and M.E. Van Valkenburg, "Network
AnalySis and Synthesis by Digital Computers,!!
1957 "t-lESCON Convention Record, pt. 2,
pp. 137-144.

E. W. Hobbs, "Topological NetvTork Analysis as
a Computer Program (discussion)", IRE Trans.
on Circuit Theory, vol. CT-6, pp. 135-136;
March, 1959.

F.J. MaCT,Ii11iams, "Topological NetvTork Analysis as a Computer Program," IRE Trans. on
Circuit Theory, vol. CT-5, pp. 228-229;
September 1958.

:Mayeda, IIReducing Computation Time in the
Analysis o:f networks by Digital Computer,"
IRE Trans. on Circuit Theory, vol. C'l-6, pp.
136-137; March 1959.
'IV.

252

5.4

Fig. 1

c
N11

N22 = 04

N21=

N31 =

(b)

(a )

(c )

(d )

a
N51

=04

N52= 03

(e)

(f )

(g)

Fig. 2

(j)

253

5.4

Fig.3

36 - - - - - - - - - - - - - - - - -

0----------------- 000

CODING OF SUBGRAPH CONSISTING
OF NODES 1) 3 , 5, AND 6

Fig.4

255
5.5
A COMPUTER CONTROLLED DYNAMIC SERVO TEST SYSTEM
V. A. Kaiser and J. L. Whittaker
Douglas Aircraft Company, Inc.
Santa Monica, California
Recent years have seen an increasing number of
successful applications of digital computers to
a real-time control in industry. These applications generally concern the monitoring and
control of a large number of relatively slowly
varying parameters of a process. Equally successful has been an application of a control computer to provide control and data processing for
the dynamic testing of missile servo-control systems. At Douglas Aircraft Company, computercontrolled tests are currently being conducted on
servo systems which operate at frequencies ranging to 400 cps. In this application, emphasis is
placed on the monitoring of several rapidly
changing parameters in order to provide a realtime description of the dynamic characteristics
of the servo systems.

possible methods of improving the testing procedures. It was conceived that the duplication
of test equipment and personnel required by the
parallel testing procedure could be eliminated by
time-sharing a single master test system. Economic justification of the master tester could be
realized if the individual tests could be conducted serially in the same length of time as
that required for parallel testing by the conventional methods. The study was therefore directed toward an automatic computer-controlled
test system. The versatility necessary for development test work, as well as the speed,
accuracy, and reliability requirements, limited
the study to digital rather than analog eqUipment. From this study resulted a digital
computer-controlled dynamic servo test facility
which was placed in operation in mid-1960.

PURPOSE OF THE AUTOMATIC TEST SYSTEM
Steadily increasing requirements are being placed
on the performance, reliability, and operating
environment of missile flight control servo systems. To satisfy these advanced requirements has
demanded a continuous effort in the missile industry to improve on previous designs, maintain
closer design parameters, and to develop better
hardware. Each stage in the development of a
missile flight control system requires extensive
testing, and the development program cannot proceed until it has been ascertained that all
intermediate design requirements have been met.
These efforts are resulting in an ever-increasing
amount of laboratory dynamic testing.
Manual methods of conducting the many required
dynamic control system tests have become undesirable for several reasons. To complete a development program in the alloted time requires
that several tests be conducted concurrently in
order to offset the time required to conduct each
individual test manually. This parallel testing
procedure necessitates extensive duplication of
test equipment and a large labor force of test
engineers, technicians, and data reduction
personnel. The manual methods of conducting the
tests have thus become an economic burden. In
addition, the reliability of the manual test results is relatively low. Errors accumUlate from
numerous sources such as faulty equipment calibrations, incorrect interpretations of low
signal-to-noise ratio signals, and carelessness.
Small changes in servo parameters due to wear,
hydraulic fluid contamination, or operating environment may therefore be completely hidden in
the "data spread".
These deficiencies in the manual methods of control system testing were recognized by the Testing Division of Douglas Aircraft Company. In
early 1958, a study was initiated to investigate

This automatic test system, controlled by a
Thompson-Ramo-Wooldridge RW-300 digital control
computer, has been located in the HydroMechanical Systems Development Laboratory at
Douglas. With this facility, the many various
servo system tests which previously required
weeks to perform are now conducted daily.
GENERAL FACILITY DESCRIPTION
The RW-300 computer and its associated inputoutput eqUipment are located in what is called
the Control Center of the Systems Laboratory.
From this central location, tests are conducted
on missile servos located at eleven remote sites
in the laboratory as shown in rigure 1. These
sites include missile mock-Ups, environmental
chambers, and work benches. Switching is accomplished manually in the Control Center to select
one of these sites-, and the equipment located at
the selected site is tested automatically by the
computer. Intercom and closed circuit television
systems provide means for communications between
the operator in the Control Center and personnel
at the test locations. The operator can thus
observe the system in operation while the test is
being performed and can immediately stop the test
should a malfunction occur. With proper scheduling of tests at the various remote locations,
many different tests on various servo-system
hardware configurations can be conducted in
succession.
The RW-300 computer is the heart of the automatic
test system. Designed for process control, the
computer contains a flexible input-output subsystem. Using the digital and analog outputs,
control of the servo system configurations, the
driving functions applied, and other peripheral
equipment is maintained throughout the test
(Figure 2). The analog-to-digital converter, an
integral part of the RW-300 computer, is used to

256
5.5
convert samples of the servo system output signals to digital form. Conversion is under program control and the digital values of the
samples are stored automatically in a reserved
section of the magnetic drum storage of the
computer.
The memory capacity of the computer is approxi~
mately 8000 words, including 1024 words reserved
for analog data and 16 words of rapid-access
memory. Each word contains 18 binary digits, and
may be used for program storage (1 + 1 instruction system) or data storage (17 magnitude bits
plus sign). A total of 20 arithmetic and logical
decision operations are available for program
instructions.
The equipment located with the RW-300 computer in
the Control Center is shown in Figures 3 and 4
and includes a Flexowriter, X-Y plotter, a Master
Control Console, and the servo-system electronic
equipment and instrumentation equipment. The
Flexowriter serves as the primary input-output
device for the computer and includes a paper tape
reader and punch unit. The tape reader is used
to load the instructions into the computer memory
and to provide the test parameters and variations
for the program. The Flexowriter is also used
for tabulation of test results.
Complementing the Flexowriter as an output device
is a Mosely 2A X-Y plotter. The plotter is
computer-controlled and can plot up to six separate Bode diagrams describing the servo system as
the test is being conducted. The Bode plots may
describe the various loop or component frequency
responses, or, by the assignment of each plotter
symbol to a separate driving function amplitude,
may describe the amplitude-dependent nonlinearity of the servo system.
The Master Control Console houses the intercom
switching and the television camera SWitching.
A Hewlett-Packard 202A function generator, modified for digital frequency and amplitude control,
is also located in the console. The function
generator is used to provide the driving functions for the frequency response tests on the
servo systems. Digital drawers, which contain
the relays which effect the digital outputs to
the Flexowriter, X-Y plotter, and function generator complete the Master Control Console.
The four-bay electronic equipment console
(Figure 4) houses all the servo system electronics eqUipment. Many amplifier, filter, and compensation network combinations are located in the
console. Digital outputs from the computer are
used to form a specific configuration of these
elements for the particular servo system hardware
being tested. Also located in the console are
the strain gauges and thermocouple reference
junctions which make available computer monitoring of "g"-loads, pressures, flows, temperatures,
etc., at the test site during the test.

SYSTEM OPERATION AND COMPUTER PROGRAM
The capability of the computer to read punchcoded paper tape from the Flexowriter concurrently with the execution of the test provides
much of the versatility of the automatic test
system. The sequence of tests tc be conducted,
the specific driving functions to be applied, and
the data to be obtained are coded and listed on
paper tape~ This information is read as required
by the computer during the execution of the test.
The basic block diagram of the computer program
is shown in Figure 5. The program is divided
into six regions, each of which performs a specific function for the test. Entrance into a
region is only by a code read from the tape identifying that region. When the test is started,
Region I is entered. Here the time of day is
recorded, and the test is assigned an identification number, also printed on the result sheet.
The exit from Region I is Region II, where a digital input from the tape reader is performed.
The code read from the tape is interpreted, and
the program exits to the particular region identified by the code. When the instructions of the
region have been performed, the program immediately returns to Region II to read another region
code from the tape. Thus the regions are entered
in the order which they are coded on the tape.
The three basic types of tests available are (1)
Equipment Calibration, (2) System Frequency Response, and (3) System Stability Test. The regions which perform these tests are identified as
C, R, and T respectively. In addition, for the
equipment calibration and frequency response
tests, there are two regions which operate to set
up a required driving function. These two regions are identified by IF' and 'A'. In Region
F, the frequency of the driving function is read
from the tape and, by means of the digital outputs, set on the function generator. The desired
driving function amplitude is, in a like manner,
set in Region A.
A typical test tape format is shown in Figure 6.
The first character in each line identifies a region. The digits following the region codes contain the information required by the region to
complete the operations in that region. The digits following the C and R codes (calibration,
frequency response) are used to instruct the program (1) what output ratios to compute, and (2)
whether these gain and phase results should be
printed, plotted, or both printed and plotted.
The digits following the F code (frequency) are
the octal representation for a particular driving
function frequency. The driving function amplitudes follow the A (amplitude) region codes. The
digits following the T (stability test) contain
the information necessary for the stability test.
These digits contain codes for (1) the gain settings of the amplifiers, (2) the compensation
networks to be digitally inserted into the

257
5.5
various loops, and (3) the results to be printed
at the completion of the test. The S code is
punched at the end of each tape and is interpreted by the program a~ "te:st completed." The
computer stops operation upon receipt of this
code, and the operator may switch to another test
location to begin another test on a different
servo system.

Because each signal f{t) is represented in discrete samples, it is necessary to approximate
these integrations by numerical methods. The
trapazoidal method of numerical integration is
used, and the above integrals are approximated by
Equations (3) and (4).
N-l
A c:: -2 [So
sin (o) +
N 2
k = 1

For a frequency response test on the servo system
or an electronic equipment calibration, then,
three regions must be listed. (R, F's and A's or
C, F's and A's). For a stability test, only region T is entered. The test engineer list~ the
codes necessary to conduct the specific test desired. The digits following each region code are
obtained from a set of tables. A tape is punched
containing these codes in proper sequence and
placed in the Flexowriter tape reader. After
switching to the desired test site in the laboratory, computer operation is begun. The test is
then performed automatically, the desired results
are printed and/or plotted, and the computer
ceases operation when the test is complete.

B 0<

sin k89

2Bw

[so

2" cos

N 2

(3)

sin N

N-l

cos (0)

k~l Sk cos k89

( 4)

DATA ACQUISITION AND MAJOR CALCULATIONS
After the driving function has been sele.cted and
applied to the system, the data from which the
system response is calculated are obtained in the
following manner. Programmed digital outputs
from the computer connect four lines from the
servo system through scaling amplifiers to the
input of the analog-to-digital converter. The
scaling amplifiers are controlled by the computer
to scale the voltages to the most accurate range
for conversion. Upon command, these four signals
are sampled in sequence at the rate of 3840
samples/second or 960 samples/line/second. The
digital values of these samples are stored in a
prescribed sequence on the reserved section of
the magnetic drum memory. The converter is b.ipolar, and converts voltages ranging to ±10.23
volts with a resolution of ±10 millivolts.
Since the section of the RW-300 memory reserved
for the storage of analog data contains 1024
words, each of the four signals is sampled 256
times during one conversion cycle. From these
samples, the amplitude and relative phase of
each signal are determined. The method used is
that provided by Fourier analysis. The real and
imaginary components of the fundamental of each
signal are given by Equations (l) and (2).
2

rr J

A=!

Where:
So' Sl' ••• Sk ••• Sn - Samples of f (t)
N = Total number of samples
8 9 = Angle between samples Sk ana Sk+l

The integrations of Equations (1) and (2), and
hence the above summati9ns, must be performed
over an integer number of cycle of f(t). Since
the sampling rate is fixed, the number of samples
N is varied with frequency so that, as nearly as
possible, an integer number of samples are used
to ~epresent an integer number of periods of
f{t). It has been found that for N ~ 30, sufficient accuracy is maintained. At least thirty
samples of f(t) are therefore used in the above
summations.
Rectangular-to-polar conversion of the results of
Equations (3) and (4) provide the amplitude and
phase angle for each signal as given in Equation

(5).

f(t)
Where:

(5)

-1 B

= tan
C=

f( t) sin wt dt

= C~
A

B
sin

27T

B
Where:

f( t) cos wt dt

(2)

A = Real part of fundamental of f(t)
B = Imaginary part of .fundamental of f{t)
W = Radian fundamental frequency

After each of the four input signals have been
represented in this manner, the desired amplitude
ratios and phase relationships are calcula~ed.
The logarithms of the amplitude ratios provide
the gain in decibels. The component, loop, or
system gain and phase relationships are then
printed with the Flexowriter and/or plotted with
the X-Y plotter. The program is then ready to
read the coded tape to obtain the next requested
driving signal.

258
5.5
An example of a typical result sheet is shown in
Figure 7. This particular test began with an
equipment calibration. Under CALIBRATION are
listed the static test parameters. These include
the servo-amplifier quiescent currents, the
servo-amplifier gain, and the feedback transducer
excitation voltages. A brief frequency response
test on the electronic e~uipment in the feedback
loops was then conducted. Under FREQUENCY RESPONSE, the component, loop, and system gain and
phase relationships are tabulated for various
driving functions. Under each column is listed
the gain in decibels fol~owed by the phase shift
in degrees.
Plotted on the X-Y plotter during this test
(Figure 8) was the closed-loop system frequency
response. Each driving function amplitude was
assigned a different symbol on the plotter. The
spread observed on the plot is therefore a result
of the amplitude-dependent nonlinearity of the
servo system.
SUMMARY

The procedure used by the test engineer in conducting a dynamic test on the servo system with
the automatic test system is as follows. First,
the hardware to be tested is set up at one of the
remote sites in the laboratory. The loading
(inertia, spring, damping, etc.) and the environmental conditions for the servo system are arranged. A test tape, listing the codes for the
particular tests deSired, is punched with the
Flexowriter punch unit. This paper tape is
placed in the Flexowriter tape reader and the
automatic test system is switched to the remote
site where the servo system is located. Computer
operation is then begun. Without manual intervention, the computer program reads the punchcoded tape as the information is needed, executes
the operations instructed in each program region
listed on the tape, and prints and/or plots the
results of the test as they are obtained. When
the test is complete as indicated by a code on
the test tape, the computer halts and the engineer has the desired tabulated and plotted transfer functions at hand. Another test engineer,
with an entirely different servo system located
at another remote site in the laboratory, may
then switch the automatic test system to his location and follow the same procedure.
The justification of this serial test procedure
in replacing parallel manual testing has been
achieved. A typical dynamic servo system test
conducted manually required up to two hours to
obtain sufficient data with which to evaluate the
system. An additiona~ two hours were usually
required to calculate the results and plot the
desired transfer functions. A similar test conducted with the automatic test system now takes
from 10 to 20 minutes (depending upon the extent
of the test). Since the results are obtained in
plotted form, the entire test is accomplished in
only a small fraction of the time previously required. The many required tests can therefore be
conducted serially at a more rapid rate than was

previously possible using the parallel manual
method. The savings resulting from the elimination of duplicate test equipment will be considerable. A by-product of the time savings is
the reduction of servo system component wear.
Because the servo system is being driven only a
fraction of the previous time, wear and the resulting changes in operating characteristics
have been minimized. The previous expense of
maintaining several prototypes of each component
has thus been eliminated.
In addition, the accumulative errors accrued
during a manually perf.ormed test were estimated
to provide results accurate to only ± 10%. The
digital computer provides these test results accurate to ± 1%. Thus more confidence can be
placed on the test results, and more accurate
evaluations of the system performance can be
made.

ELEC. TEST LOCIN
r----I BENCH 2
II
CENTRIFUGE
LABORATORY

"J" BOXES

ELEC.TEST LOCIN
BENCH I
10

LOCIN 6
CONTROLS
SYSTEM
MOCK-UP

Ltl

nCP I
~

rlTl

MCONTROL
CENTER

LOCIN 8 l-Lr-ENVIRONICP
MENTAL I
CHAMBER
L-

LOC'N 4
TEST CELL NO.4
POWER SYSTEMS

LOCIN 3
TEST CELL NO. 3
SERVO SYSTEMS
a COMPONENTS

I
I
LOCIN 7
CONTROLS
SYSTEM
MOCK-UP

LOC'N 2
TEST' CELL NO.2
SERVO SYSTEMS
a COMPONENTS

HYDRO/MECH. a CONTROLS
SYSTEMS LABORATORY

~
CP

AMPLIFLIERS-POWER SUPPLIES
REMOTE CONTROLS-RELAYS
COMPUTER 8 MASTER CONTROL

LOCIN I
TEST CELL NO. I
SERVO SYSTEMS
a COMPONENTS

CP\.

~ INSTRUMENTATION - MONITORS

TEST CELL NO. 5
FIRE LAB

LOCIN 9
SERVO COMPONENT
DEVELOPMENT LAB
(DUST FREE)

CP -COMPUTER CONTROL PANEL
Fig. 1. Systems Laboratory Layout

C'.J1tv
•
C'.J1
C'.J1\O

CJ1 r-v
•
0'1
CJ1 0

MOSELEY MODEL 2A
X-Y PLOTTER

a::

0-3
CHAR.

w 0
t- w

o<[ t0
a:: w
-I
<[

:t:

~
~
Z

a::

PRINTER
~~

-z

ANALOG

AID
CONVERTER

.....
.....

INPUTS

(4)

~
~
~
"".

....
....
FLEXO- .....
......
WRITER

FREQ.CONTROL ....

....

....
RW-300
COMPUTER

DIGITAL
CLOCK

START-STOP
CONTROL
HEWLETTPACKARD
MODEL 202A

SYSTEM DRIVING .....
SIGNAL

...

AMPL. CONTROL .... FUNCTION GEN .

...

.......

....

.....

......

D.C. BALANCE
VOLTAGE

....
....

D.C. STEP
VOLTAGE

....
....

DIGITAL OUTPUTS
DIGITAL INPUTS

.......

Fig. 2. RW-300 Computer Input-Output System

SYSTEM
UNDER
TEST

......t lJ".)

\0
•
C'llJ".)

RW-300 COMPUTER

FLEXOWRITER

MASTER CONTROL CONSOLE

Fig. 3. Systems Laboratory Control Center

262

5.5

Fig. 4. Servo System Electronic Equipment and Instrumentation Console

REGION C
PERFORM
CALI BRATION TEST

I •

REGION R
I PERFORM FREQUENCY 14141...----,
RESPONSE TEST

REGION I
PROGRAM
INITIALIZATION:
PREPARATION
FOR TEST

REGION IT
INTERPRET
OPERATION
CODE

REGION T
PERFORM STABILITY 1411111------'
TEST
REGION F
SET SIGNAL
FREQUENCY
REGION A
SET SIGNAL
AMPLITUDE

?"'~

CJ1W

Fig. S. Basic Program Block Diagram

264

5.5

C212431410.
FOOl300
AOOOIOO

A000200

F006300
AOOOIOO

R432210310.
F000200
AOOOl20
AOOOl60

TI00036043172.

S
Fig. 6. Test Tape Format

265
5.5
10-20-60

1022 AM

RUN NO. ~

CAlI BRATI ON

11 211.9 MA
12 209.6 MA
AMP. GAIN 100.2 MA/V
BUZZ 20.'7 V
£Xl 10.,1 V
EX2 19.92 V
A MPL..
f'REQ.

YFAVjVCAL
-o.~ -0.890

E2/VeAL
0.091 -0.750

.0.101 -1.507

-0.007 -2.m

0.085 -0.554

-o.O~

-o.()'1JI. -8.296

0.171 -0.0'1

'.915

~.925

YFMjYCAJ..
-0.066 -0.656

".92
202.2

~.~
~.196

f'R[QUENCY RESPONSE
A MPl.
f'REQ.

,.960

Yf'Bl/El

YFBl/E2

-0.156 -190.6
-o.m -191.1
0.011 -188.0
o.~ -188.1
0.066 -187.9

1,.1!., -86.11
14.97 -~.12
16.42 -95.92
17.12 -97.25
17.~ -95.73

-6.925
-7.089
-8.015
-9.i196
-11.20

-101.'
-100.9
-100.1
-98.61!.

-'56.7
-3.917

-98.~

6.66Ji.
8.00'
8.390
7 .5"~
5.996

0.980
2.01.2
,.960
5.9Ji.9
7.976

-0.269 -195.7

-0.003 -192.5
0.078 -191.7
0.066 -191.2

11.10
12.11!.
1,.22
14.oJi.
11!.."

-92.75
-96.31
-97.19
-98.31
-97.80

-10.58
-10.51
-11.36
-12.88
-1~. 73

-106.6
-106.1
-10'.0
-loJi..6
-103.8

0.789
1.593
1.859
1.082
-0.'51

-3.695
-7.652
-9.196
-11.19
-10."

0.992

- 0 .265
-0.101
0.058
0.071!.
0.091

8.718
9.886
11.17
12.03
12.30

-96.71
-97.72
-100.3
-98.86
-99.06

-12.95
-13.02
-1'.90
-15.51

-111.1
-110.6
-109.2
-108.3

-3.972 -7.503
-,.~

8.091

8.0116

Yf'B2/E2

YF'B2/El

0.980
2.007
'.980

6.019

6.011

-7.566

2.0~

3.9Ji.l
5.91~

7.898
12.0,

1.007
2.035
'.914
,.851
7.875

15.95

0.992
2.00,
'.945
5.867
7.86,

20.07

1.000

O.O~ -1~.8

-200.1!.
-198.0
-195.8
-194.4
-19'.8

-17.~ -107.~

-7.~

-7.196
-6.785

-3'0~ -10.~

-2.785 -13.76
-12.75
-5.070 -12.67

-209.0
-206.1
-202.1!.
-200.'
-199.1

5.535
6.878
8.285
9.l32
9.5~

-99.85
-101.0
-102.5
-103.5
-101.9

-16.50
-16.53
-17.39
-18.99
-20.77

-123.5
-122.8
-118.6
-115.2
-11'.4

-10.6I!.
-9.1!.92
-9.250
-9.992
-11.38

-14.30
-17.72
-18.75
-18.39
-16.'7

-0.562
-0.023
0.2J16
0.308
0.'39

-217.6
-2l3.9
-207.9
-205.1
-202.9

,.,..,
1!..636
6."'7
7.3OJi.
7.911!.

-loJi..2
-105.5
-107.'
-107.1
-106.5

-18.98 -l3Ji..9
-18.92 -130.5
-19.811- -12'.4
-21.~ -120.3
-23.26 -116.8

-15.07
-11!..26
-13.75
-14.48
-15.70

-21.50
-22.15
-22.86
-22.34
-20.116

-0.792
-0.257
0.382
0.50'
0.562

-~.9

-220.7
-214.0
-209.9
-207.9

1.296 -108.1
2.96Ji. -109.7
~.632 -110.2
5.898 -111.1
6.~37 -111.3

-21.78
-20.49
-21.62
-23.42
-25.21

-11!.7. 7
-11U.1
-131.5
-l25.6
-12'.5

-19.69
-17.26
-17.37
-18.02
-19.34

-Zl.94
-30.07
-26.89
-26.811-

-239.,
-230.8
-22O.1!.
-216.0
-214.0

-o.~ -11~.7

-2,.oJi.
-22.58
-23.67
-25.25
-Zl.21

-156.2
-150.1
-138.8

5.949
7.8M.

- 0.968
0.00'
0.679
0.902
1.091

-22.53
-21.20
-20.95
-21.73
-2'.35

-'1.58
-34.89
-3Ji..76
-32.34
-35.116

30.01

0.960
2.015
'.898
6.250
8.382

- 2.105 -250.9
-0.839 -21!.1.2
o.~ -225.1!.
1.375 -219.8
1.781 -220.0

-0.742
2.326
'.789
'.785

-115.5
-116.4
-116.1
-122.2
-125.8

-23.11 -180.4
-2.... ZI -165.'
-alt..eo -1"'9.9
-Zl:T8 -11!.1.5
-29.01 -138.0

-2'.~ -1!.5.oJi.
-2~.17 -ltc.63
-22.96 -ltc.57
-25.36 -4'.95
-Zl.Ol -4'.92

ltc.oJi.

0.960
1.972
1!..156
5.886
8.2J16

- '.367
-0.945
1.082
2.'32

-267.8
-261.9
-N.5
-238.9
-20118.9

-4.972
-3.050
0.171
0.980
-o.161!.

-121.8
-128.,
-126.2
-l32.9
-l36.8

-~. 71!.
-26.04
-27.0'
-29.}5
-32.01

-~.9

-157.6
-169.7

-".35
-30.15
-27.94
-30.70
-34.73

-55.57
-51.35
-49.69
-51.71!.
-57.57

0.988
2.050
1!..042
5.95'
7.765

.5.238
-2.'39
1."5
1.m
1.707

-288.8
-m.o
-259.9
-265.7

-7 ....76
4.921
-1.601
-1.886
-2.882

-l32.4
-l32.2
-135.6
-139.5
-14,.8

-3505'1
-30.}2
-29.00
-30.81
-".51

-2ltc.5
-201..1
-181.,
-186.1
-197.2

-37.81
-32.91
-32.05
-34.66
-38.10

-811..14
-59.28
-57.1'
-59.94
-62.92

0.980
2.042

5.972
7.898

- 7.261
-1!..738
0.500
1.18,
0.171

-302.7
-295.9
-260.9
-266.1
-297.2

-9.488 -l39.5
-7.~ -138.9
-'.585 -1112.,
-11!.5.6

-34.01 -32l.9
-32.99 -235.'
-30.53 -201.6
-208.5
-35.1' -216.8

-".lIe

-36.2'
-35.73
-34.62
-38.25
-ltc.oo

-158.7
-78."
-6'.10
-68.07
-68.16

79.91

0.98It.
2.015
....007
5.96Ji.
7.9"

-11.30 -326.4
-9 ....1~ -~9.'
- ....667 -,1,.0
-2.289 -313.8
-2.826 -,19.1

-13.25
-11.66
-8.082
-6.59'
-7.082

-155.'
-149.6
-149.5
-15' ....
-155.7

-1!.7.89
-ltc.25
-37."
-36.00
-37.911-

-170.5
-261.1
-2"".7
-238.5
-2"',.1!.

-1!.9.8,
-1!.2.51
-ltc.85
-!Jo.,l
-42.19

-357.'
-91.36
-80.19
-78.05
-80.01

101.9

0.98Ji.
2.011
'.937
6.015
8.019

-17.05 -'36.6

-18.12
-16.01
-12.5I!.
-10.30
-10.0'

-159.5
-160.0
-159.'
-164.9
-161!..8

-42.0'
-52.lt2
-lt6.17
-"'1.08
-40.94

-270.7
-266.2
-267.5
-271.0
-267.5

..1!.'.10 -9'.62
-53.80 -90.91
-~.37 -9'.13
-".11!. -97.35
-".16 -9,.60

2.~

3.917
5.890
7.851
25.05

0.972
2.00,

'.9Ji.l

".99

59.~

I!..~

-0.32Ji.
-0.161!.
0.1"
0.l32
O.lltc

2.~

-~8.1

-l~.6' -"5.'

-l0.35 -"3.7
-7.2lt6 -'38.6
-6.816 -'38.~

1.386 -115.6
-116.,
1!..425 -116.9
.... m -118.6

'.394

-2.~76

-'.582

~.699 -1~.5

-1~.~

-130.9

-201.6
-1811-.9

Fig. 7. Typical Tabulated Result Sheet

-~.71!.

266
5.5

+4
,;'

ai
0

LaJ

m
>II

-2

~\ \

~\
i'Y
"
\\
~r\.
~
~
~

"r\.~~

GAIN

-4

""C~

..)

bf ~

.......

Ci
(!)

\ ~

1\ ~

-6

\ \
'i

-8

-160

-.....

-200

......

...... r-....:

--220

~ r"...~ ~
~ ~ ~~

~ ~ ~ :'\

N -240
CD
lL

-260

'\ ~

~ \. .\.'i~
'\: ~\ &

\\ ~ ~

\ .\ 1\'\"

::r:: -280
CJ)

\.~ \~\

11.1

~i\\ \~

en -300
«
::r::
Q..

PHASE SHIFT~ ~ ~ ~ l'I.

[\~

11.1

11.1
0
0

\ ,~

\ [\

'--- ~-IO

-180

\~
1\ ~

""i

-320

l\
.\ ~ l\
\ \ ~p
I" ~

-340
3

FREQUENCY-CPS

Fig. 8. Typical Plotted Result. Sheet

100

150

267

6.1
HOT-WIRE ANEMOMETER PAPER TAPE READER
John H. Jory
Soroban Engineering, Inc.
Melbourne, Flor:ida
Summary
'fhe Hot-Wire Anemometer Paper Tape
Reader was conceived as a relatively simple
apparatus to serve as a high reliability device
such as required in peripheral computation
equipment. The hot-wire anemometer principle
has been employed extensively in the past for
the study of transient air flow phenomena in
compressors and turbines. The principle of
operati~n concerns an electrically heated wire
used to detect a change in air velocity in its
immediate vicinity by observing its change in
temperature and consequent change in resistance. Using this principle to read perforated
members such as punched paper tape at high
speeds offers a number of distinct advantages
over conventional reading methods.
Methods of

Readin~

Paper Tape

At present there are available three general types of paper tape reading mechanisms.
Brush type readers employ brushes which rest
on one side of the paper tape and pas s through
perforations to engage contacts disposed on the
opposite side of the tape. Sensing pin type
readers mechanically insert pins through perforations occurring in the tape and thus accomplish the reading function. Photoelectric
readers employ a beam of light directed toward
a photocell which is interrupted at ail times
except when perforations are disposed between
the photocell and the light source. The two
former members are relatively slow since the
inertia of the sensing members limit the rate
at which perforations may be sensed. The
photoelectric' method is materially more rapid
than the other two methods but suffers from
difficulties arising from the presence of dirt
and paper chaff in the region of the photocells.
More particularly, dust and bits of paper from
the perforated member accumulate around the
photocells and limit the amount of light reaching the photo-sensitive element. Unless the
photocells are regularly cleaned the amplitude
of signals decreases to a point where the circuits
and system become unreliable. A further problem arises in the reading of oiled tapes which
are translucent, causing reflections from the
tape to appear as point sources at the tape,
introducing cross-talk between circuits. In
order to overcome these difficulties special-

ized techniques must be employed. Also inasmuch as oiled paper tapes are the most commonly used in the field due to their reducing
wear on punch pins, photoelectric readers are
limited in their application to paper tape
handling.
Hot-Wire

Reader

The Hot-Wire Reader operates by allowing air under pressure to pass through perforations in punched paper tape and be directed
over electrically heated wire elements which
are thereby cooled, causing their resistance
to change and thus indicating the presence of
a perforation in the tape. In the most advantageous interpretation of this reading scheme
the paper tape is situated between the following
sub-assemblies:

1. A plenum chamber with an arcuate
surface in which a slit is cut which bears on
the tape. This chamber is kept at a low pressure by means of a suitable vacuum source.
2. A sensor plate having a small window
opposite each channel position of the tape being read, the windows being aligned with the
opposed slit in the plenum chamber.
A small coil of wire is situated within
each window in the sensor plate and the se
sensing elements change their temperature
and resistance when a perforation in the tape
passes between them and the slit in the plenum
chamber. This hot-wire reading technique
inherently overcomes the difficulties encountered with photoelectric reading. Since there
is sporatic air flow through the reading station,
dust, dirt, and lint are automatically removed
and deposited in the pump filter. The reader is
capable of reading optically transparent, translucent, or opaque media. Moreover, the reader
is simple and inexpensive. ,utilizing readily
available amplifiers and hot wires. The reading speeds attainable are limited only by the
mechanical transport mechanism and the quality of the amplifiers used. In addition changes
in ambient temperature do not affect reading
even though changes in hot wire temperature
are being detected since the temperature of

268
6.1
hot-wires is maintained at about 400 0 C. which
is quite high with respect to ambient. The amplifiers adjust their drive continuously to maintain constant resistance in the hot-wire which
is' compared with a fixed resistor in a bridge
circuit.
Hot-Wire Elements.
The hot-wire elements
are composed of 15 or 20 turns of nicke 1-iron
alloy wire with a high temperature coefficient
of resistance. The coils are 0.001 inch diameter wire wound on a 0.005 inch mandrel. Hotwire elements themselves have relatively high
thermal time constants, and so a system which
allows the hot-wire to change temperature in
response to the initiation and termination of
air flow only would be slow in comparison to
photo-electric readers. By employing amplifiers with sufficient feedback the temperatures
of the hot-wires are maintained essentially
constant, and a resistance change merely
sufficient to generate an error signal occurs.
In addition the hot wires are wound in coils as
opposed to the conventional straight wire
elements. With straight wire elements the
thermal inertia of the end supports is found to
affect the response of the system. Thus by
employing a coiled wire, the major portion of
the wire is substantially removed from the end
supports so that their thermal inertia does not
injure the response.
Flexibility of Reading Technique. Either continuous or discontinuous reading may be employed with the hot-wire reader and either AC
or DC circuits may be used as amplifiers although there is a well known tendency for DC
circuits to drift. Also if discontinous reading
is employed a code may remain stationary over
the reading station thereby allowing the device
to act as a temporary storage register until
the equipment again begins to transport. If the
device stops with a web of the tape over the
reading station there will be no output signal at
this time and readings will be obtained while
transporting the tape. If the hot-wire sensing
elements are placed within the plenum chamber
and a low pressure maintained there, paper tape
could be pulled oyer the arcuate surface of the
chamber and edge guided only, not requiring any
sort of clamping device on one side of the tape.
In this configuration the chamber would have
holes rather than a slit so that each channel
could be sensed from inside the chamber. This
would eliminate any threading inconvenience
when loading the reader with tape.
One extremely important aspect of the
Hot- Wire Reader is the lack of the need for
sophisticated components in the construction

and operation. The operating air pressure
required is approximately one inch of water so
that extremely small blowers and motors may
be employed. Paper tape channels are on onetenth inch centers allowing ample space for
mounting of hot-wires. Due to the freedom
from complexity of this apparatus, it is an extremely reliable device, which concept is
gaining more and more importance in the data
handling field.

269
6.2

USE OF A DIGITAL/ANALOG ARITHMETIC UNIT
WITHIN A DIGITAL COMP UT ER

Donald Wortzman
IBM Corporation
Yorktown Heights, New York

Summary
A novel approach to arithmetic operations in
digital computers is described which combines
digital and analog techniques. This is accomplished by using parallel- serial interconnections
of digital/analog converters. The interconnections are under stored program control and
are effected by selecting multiplexers which
route the analog signals to perform various
arithmetic operations. The final analog signal,
which is the result of the computation is converted to digital form by means of an analog /
digital converter.
Because of the extreme parallel nature of D/ A
Arithmetic, high computational speeds are
attained, although all the ci. rcuitry is operating
slowly by present digital computer standards.
Using present techniques the analog nature of
the computation limits the accuracy to four or
five significant decimal figures. Therefore,
the D/A Arithmetic Unit could not replace the
arithmetic unit presently in digital computers,
but could be used to solve problems or parts of
problems that do not require extreme accuracy.
Digital/Analog Arithmetic
Introduction
A computer is usually classified as being either
analog or digital. Each has its advantages and
disadvantages, when handling mathematical
problems. In a previous paper l, it was shown
how digital and analog techniques could be combined to synthesize various analog type building
blocks having accuracies not obtainable with
conventional analog techniques.

This paper suggests a method of combining
digital and analog techniques in order to perform the arithmetic operations in digital computers. The techniques offer the potentiality
of extremely high computational speed at low
cost.
Arithmetic operations in the arithmetic unit
described in this paper are performed without
the use of conventional adder circuitry as found
in most stored program computers. This is
done by routing analog signals, by means of
multiplexers, onto the reference voltage inputs of D / A Converter s, summing the analog
signals thus formed, and finally converting
the result to digital.
Before beginning the discussion of the D/A
Arithmetic Unit, a brief discussion of D/A
conver sion, building blocks of D / A arithmetic,
and several interconnections of them will be
given.
Digital to Analog Conver sion
Figure 1 depicts a unipolar, three binary bit,
digital to analog converter. DI' DZ, and D3
are single-pole double-throw switches which
can be thrown independently to zero volts or V r
volts; zero being a logical 0 and V r volts being
a logical I. If the output voltage is calculated
as a function of Db DZ' and D3, equation I
results:
(1)

270

6.2
It should be noted that the bracketed factor in
equation (1) is the definition of a binary number,
where Dl is the most significant bit, DZ is the
next most significant bit, and D3 is the least
significant bit. Further, equation (I) illustrates
that the open circuit voltage is not only proportional to the digital input but is also proportional to the reference voltage, V r •
Digital/ Analog Building Blocks
Digital/ analog building blocks have both digital
and analog inputs and outputs; to provide clarity
th.e following rules are followed in this report:

1.
Z.

All digital quantities enter and leave the
top of the block.
All analog quantities enter and leave the
sides of the block.

The comparator, Figure 6, is the last of the
building blocks that will be described. A
positive current flows into A and a negative
curr ent flows out of B. The digital output D
indicates which current is larger in magnitude.
Tlts circuit is used in converting the analog
result of the arithmetic computation to digital
form.
Interconnection of Building Blocks
In Figure 7, the digital output of the comparator controls the logic which strives to make
BI and BZ equal.

Under this condition:
(2)

If AI. AZ and DZ are preset and DI is varied

until /BI/;:./BZ/' then equation 2.can be rewritten as:
Figure Z, the D / A Converter, is the block
representation of Figure 1. This block is important since it is through this that multiplication is performed. A requirement of the D/A
Converter is that it present a small load to the
voltage reference. The current that flows from
the voltage reference must first pass thr'ough the
the multiplexers, therefore a large current
would produce a large voltage drop across the
multiplexer's "on" impedance.
Figure 3 is a summing amplifier. It is used
for both impedance matching and summing of
the analog signals. Since it is required to
have little dc drift, it would most likely be
chopper stabilized.
The multiplexer, Figure 4, is one of the most
important blocks, since it is through multiplexing that the different arithmetic operations
are performed. It is required to have a low
"on" impedance and a moderately high "off"
impedance.

The circuit of Figure 5 is a variable gain
amplifier. This circuit is similar to the
summing amplifier except that the feedback
can be varied by means of the digitally controlled D/A Converter, which can change the
gain to any of three values, one-tenth, one or
ten. This scaling helps conserve the accuracy
of the D/A Arilhm.etic Unit.

(3)

If on the other hand. AI' A Z and DI are preset
and DZ is varied until BI ;:. BZ. then equation 2
becomes:

Al
DZ;:'- DI

(4)

The significance of equations 3 and 4
is that
depending on whether Dl or DZ is preset. the
function or its reciprocal can be digitized.
in Figure 8, C 1 is equal to the negative product
of Al and DI or
(5)

Similarly Cz is equal to the negative product of
AZ and DZ or

C z =-AZ

. DZ

(6)

The voltage B is equal to the negative of the
sum of Cl and Cz or

In Figure 9. the output voltage B is equal to the
product of U. DI and DZ. U is the normal reference voltage and is assigned the value unity.

271

6.2
therefore:
B

U . Dl . Dl

Dl . Dl

(8)

solution. The first is the computation of the
first e~ght terms of a Taylor series with arbitrary coefficients; the second is the multiplication of two eight by eight matrices.

Digital/ Analog Arithmetic Unit
Thus far, the "digital/analog building blocks and
some simple inter connections of them have been
explained. Figure 10 is the digital/analog arithmetic unit. It consists of three sections.
Section I performs tl},e arithmetic operations.
It contains 16 D/A converters, l4 negative unity
gain amplifiers and 7l multiplexers. It should
be remembered that with various interconnections of D/A converters and amplifiers many
arithmetic operations can be performed. However, with as many as 16 D/A converters, it is
unlikely that any particular arithmetic operation
would have many applications. The multiplexer s
reroute the analog signals so that many different
arithmetic operations can be performed. In
other words, by means of multiplexing, the interconnection of the D/A converters can be altered, thereby changing the programmed arithmetic operations within a few microseconds.
Section II is a digitally controlled variable gain
amplifier. It adjusts the gain so that the input
to Section III is as large as allowable. This is
done because Section III contributes the largest
part of the total error, so that if the gain of the
variable gain amplifier is large, the relative
error due to Section III is small.
Section III performs the analog to digital conversion. It can perform one of two functions.
Either it converts the value of the input analog
signal or it converts the reciprocal of the input
analog signal. If the input voltage is positive,
then the input is used as reference for D/ A18,
and - U is used as reference for D/ A19' Recalling from Figure 7 that depending on which of
Fl or F 3 , Figure 10, is preset a,rtd which is
varied until the inputs to the comparators are
equal will determine whether the function or its
reciprocal is digitized. If the input is negative,
then the input would be used as reference for
DiA19 and +U would be used as reference for
D/A18' The polarity indicator is used to make
this decision.

Example One. Assume that it is desired to calculate eX for arbitrary values of x. If eX is expanded in a Taylor series the result is:
(9)

If the proper multiplexers of Figure 10 are in
the 1 state and all other's are in the 0 state, the
interconnection illustrated by the heavier line
in Figure 11 results.
In Figure 11, the output of A3 is equal to x.

It
is the reference to D/AS' therefore, the output
of AS is proportional to xl, and similarly the
output of A7 is proportional to x 3 , and so on.
The digital input to D/ Al is I, therefore, the
voltage at BI is equal to 1. The digital input to
D/A4 is also 1. Because its reference is equal
to x, the voltage at Bl is equal to 1 . x or just
x. Similarly, the voltage at B3 is equal to
xl/ll and so on. The voltages of B1, Bl ... B8
are all summed in the summing amplifier in
Section II and its output is equal to:

(10)

or eX to the accuracy of the 8 terms of the
Taylor series. This voltage can be used as
such, or it can be converted to a digital number
in Section III. If the value of eX for a different
value of x is desired, the coefficients remain
the same and x is changed. For values of x
greater than I, 8 terms of the Taylor series
may not be sufficient. For this case additional
terms can be calculated separately and the results added.
Example Two. The second example is the multiplication of two eight by eight matrices. In symbolic form:
(C)

(A)

(B)

(11)

where the ijth entry of (C) ~
In summary, the arithmetic operations are performed in Section 1, and Section II and III convert the output of Section I into digital form.
..... ai8
To illustrate the flexibility of digital/analog
arithmetic two different problems are set up for

. b 8j

(1l)

272

6.2
Figure 12 is the interconnection (heavy lines)
that would perform this operation. The digital
input to D/ A1 is ail' making the reference to
D / AZ pr oportional to ai 1. The digital input to
D/
is b1j and therefore Bl is a voltage proportional to ail . b 1j . Similarly BZ is proportional to ai2 . bzj and so on. The voltage of B1'
B2 .. BS are all summed in the summing amplifier in Section II and its output is proportional
to:

This voltage is converted to digital form in
Section III. When multiplying two eight by eight
matrices, 64 such multiplications must be performed. In order to obtain the CiC ... l) term, the
"a" entries stay the same- and only ~e "b" entries
must be changed. In other words, in order to
get succeeding C entries only half the information must be changed. This of course is time
saving. If larger than eight by eight matrices
are to be multiplied it is done in parts, and the
results are added.
Although it has not been shown, the sign is
handled by digital means. This is easily done
because the', information that chooses the proper
channels to be multiplexed. determines the flow
of information. It turns out that this coupled
with the mathematical rules for signs is enough
to compute the sign of each term. Referring to
Figur e 10 again. it can be seen that if 51 is multiplexed in and Sz is multiplexed out. B 1 will be
positive. If the reverse is true. Bl will be
negative. The digital logic handling the sign
decides whether Bl should be positive or negative and selects 51 and Sz accordingly. BZ. B3
..... BS are handled in the same manner.
Another important point is that although only
digital inputs were used in both examples. combinations of both digital and analog inputs could
be operated on. In figures 10. 11, 1Z multiplexers M4. MS. M1Z. etc. can be used for this
purpos e . The typical digital/analog arithm-etic
unit would have this flexibility.
The D/ A Arithmetic Unit described in this
report is just an idea. however a scaled-down
model has been built. which at least demonstrates the feasibility of such a system.
The building blocks which make up the D/A
Arithmetic Unit were originally designed for
use in an A/D Converter. In order to test the
A/D Converter a special tester was built. The
tester would generate. by means of a D/A Converter. various voltages controlled by a fixed.

program and the A/D Converter would convert
these voltages back to digital. This digital quantity would then be compared to the digital quantity
in the tester. If they were different by more than
a prescribed amount the tester would stop and
an error indication would result. If the error
was smaller than the prescribed amount the
tester would generate a new voltage and the
process would be repeated. If the system diagram of the converter-tester combination is
referred to. Figure 13, it will be noticed that it
has many of the component building blocks of the
D/A Arithmetic Unit. and could be considered as
a scaled model of it. The results of the tests
made on the converter-tester combination not
only demonstrated feasibility of the DI A Arithmetic Unit but ,gave indication of what could be
expected in terms of speed and accuracy.
As far as speed goes the converter-tester combination was run at 100 usec. cycle period. a
cycle consisting ~f generating a voltage in the
tester. DIAl' converting it back to digital in the
converter. D/Pg comparing it with the original
digital input and then making the decision
whether to generate another voltage or to stop
the hlachine. Therefore, a D/A Arithmetic Unit
which performs at a speed of 100 usec per
operation is consistent with the actual performance of the scaled model.

In the data taken of the accuracy. the maximum
error between the digital generated number and
the digital output was less than t .05 full scale,
although the vast majority of errors fell within
± .OZ, full scale. This large difference between
the maximum error and the vast majority of
errors is to be expected in successive approximation type AID Converters. The reason for
this will not be discussed in this report. However. this error is quite small when one considers the number of contributing factors to it. for
example. two D/A Converters, two independent
references. one amplifier and one comparator.
In the D/ A Arithmetic Unit two separate references would not be used as was in the model since
the reference is the most difficult to accuralely
control. There are two other facts about this
test that are most encouraging. The fir$t is
that none of the semiconductor elements necessary for this high accuracy were specially selected for this purpose. Most of these semiconductors were randomly selected from normal
digital computer lots. The second important
fact is that many of the circuits used in this test
were superceded by later designs, which would
improve the operation considerably. These tests
and those made on the indivic:hal circuits indicates
that D/A and AID conversions can be performed

273
6.2
with average accuracies of .0010/ of full scale
and .010/ of full scale respectively.
If these performance specifications are written
in terms of Figure 10, then it appears practical
that Section I could be made accurate to one part
in 100 thousand of full scale and that Section III
could be made accurate to one part in 10 thousand
of full scale. The difference in accuracy between Section I and Section ill is the main reason
for requiring Section II. As an example assume
that A' B is to be solved. A current is produced
at the output of Section I accurate to one part in
100 thousand of full scale. Assume this produces an equivalent voltage at the output of
Section II also accurate to one part in 100 thousand. If this voltage is numerically ~qual to
7.6328 volts, when it is converted in Section III
four place accuracy is obtained, so that the voltage of 7 .6328 volts will convert to 7 .632 volts.
In other words, the last place figure is lost.
However, because Section II is a variable gain
amplifier this last figure can be recovered. If
now a slightly different problem is solved
A . B

7.6320

Figure 14 is the Auxiliary Arithmetic Unit (AAU).
The inputs to AAU are from two sources. The
digital information is from the digital computer
(not shown) whereas the analog information is
from external analog sources (also not shown).
for example. strain gages. tachometers. thermocouples. pressure gages or any other device
whose reading can more conveniently be converted to a voltage rather than directly to a
digital quantity. The analog sources may be
connected to the AAU through a bank of multiplexers. The output is a digital quantity which
is the result of the computation and which generally goes back to the computer or possibly a
remote D/A Converter which controls a part of
a process by ineans of a voltage. The easiest
way towards understanding of each of the building
blocks in Figure 14 is to show the chronological
order of events when solving a problem in AAU.
1..

A "Load Information" command comes from
the digital computer which tells AAU that
the operation registers and the data registers are to be loaded. (Referring to Figure
10 and Figure 14. the data registers contain
the digital information D l • D2 •.... D16 and
the operation registers select the operation
or computation.) In order to permit this
loading, the information gate as sociated
with these registers is opened by the controis.

The digital information comes from the
computer s erial by word, each word containing a tag which tells whether it is an
operation or data. The word is then gated
into the proper register. This process is
continued until the operation and all the
data is loaded into the proper registers.

The "Load Information" line is lowered.

The signs. '" • of the data D and the operation information M. N, V are applied to
polarity decoder. The output S of the polarity decoder is applied as the digital control
signals Sl' S2' S3' S4' etc.

The operation information M. N. V is applied
to their respective multiplexers which digitally controls the operation.

The digital information D is applied to the
appropriate converters.

The "Start Computation" command is given.

The polarity output P which senses the
polarity of the output of Section II. Figure
10. select Tl and T4 or T3 and T4

(14)

the voltage at the output of Section II will now
become
7.6328 -

7.6320

(15)

0.0008
Since Section III is only accurate to four places
o.0008 cannot be converted to digital in
Section ill. but if the gain of Section II is increased by a factor of 10. the output voltage of
Section II would be 0.0080 and Section ill could
convert this voltage and obtain an eight in the
last place. If the value of the first conversion
7 .632 is added to the value of the second conversion 0.0080, 7.6328 results. This is the
answer
10
desired. In other words. if
Section I is accurate to five places. a five place
answer can be obtained. by-using techniques
such as these.
Auxiliary Arithmetic Unit
In order to present a better understanding of
how the D/A Arithmetic Unit might operate within a digital computer the entire auxiliary arithmetic unit of which the D / A Arithmetic Unit is a
part will be described.

274
6.2
accordingly. In Figure 11 and Figure lZ
the polarity was negative so therefore TZ
and T3 were multiplexed in.

9. The polarity output P together with q,.

In digital/analog arithmetic most operations
take the same time, for example, the solution
of:

(which determines whether the function
or its reciprocal is wanted) presets FZ
or F3 in the manner previously described.

y=aTb

(16)

would take the same time as:
10. The scaling factor Fl b selected. This
can be done in several ways. One method
is to have the polarity block of Figure 10
also give the approximate magnitude of the
voltage at the output of Section II and then
select the sc;aling 'of Fl accordingly.
l1. The answer appears in FZ or F3 depending
on step 9. The information in Fl is also
needed since this is the scaling factor.

lZ. The process is repeated for the next
problem.
The auxiliary arithmetic unit performs fixed
decimal point operations and therefore the
decimal point must be considered separately.

Conclusions

( 17)

about 100 usec.
The average speed of computation for the single
addition in the first example is 100 usec.,
whereas the average speed of the 8 multiplications and 7 additions in the second problem is
6.8 usec. per single computation. The latter
speed is fast even when compared to high- speed
digital arithmetic.
Another aspect of speed to consider is the
number of times memory must be used in the
course of computation, since in high-speed
computation the memory may be the limiting
speed factor. Therefore, a less conspicuous
advantage of digital/analog arithmetic is that it
requires fewer trips to memory for similar
computation as compared to digital arithmetic.

Accura£Y
Practically, an average accuracy of ± .0011
to ± .011 full scale can be achieved. Since
most of the errors are fixed, it is particularly
desirable to operate as close to full scale as
possible. The variable gain amplifier helps
achieve this. Some numerical methods have
been considered for the purpose of improving
the accuracy. In general, their shortcomings
outweigh the increase of accuracy they may
offer.
When all is said and done, digital/ analog arithmetic will not be useful where accuracy is at a
premium. However, there are some problems
in which its accuracy may be sufficient. In
some problems the accuracy of the information
is limited, so that extreme accuracy of computation is unwarranted. Two examples of this
occur in industrial process control and circuits
analysis. In the former the input information
is in analog form and in the latter, the most
precise components are often 51 resistors.

A third important factor is that during the time
the digital/analog arithmetic unit is computing,
it can operate completely independant of the
rest of the computer. This allows the computer
to perform its necessary functions in parallel
with the digital/analog arithmetic unit for most
of its cycle. Also, becaus ether e is a long
lapse of time between successive operations, a
high percentage of this time can be utilized.
Acknowledgements
The author wishes to thank Mr. W. Brandenberg
for his help in the writing of the report and Mr.
D. A. Bourne for his encouragement in this
work. He is also indebted to Mr. D. J. Grenier
and Mr. Secundo Decceco for their work on the
A/D Converter and Tester.
References

Skramstad, H. K., "A Combined AnalogDigital Differential Analyzer", Proc. of
EJCC, 1959.

275
6.2
2.

McLeod. J. H. and Leger. R.M., "Combined Analog and Digital Systems", Instruments and Automation, Vol. 30, pp 1126.

"Applications of AD-DA Verter Systems in
Combined Analog Digital Computer Operation", Pacific General Meeting of the AIEE.
June '56, Paper #56-842.

Leger, R. M. and Greenstein, J.L.,
"Simulate Digitally or by Combining Analog
and Digital Computing Facilities", Control
Engineering, Sept. 1956.

Skramstad, H. K., Ernst, Nigro, J.P.,
"An Analog-Digital Simulator for the
Design and Improvement of Man-Machine
Systems", EJCC.

Blanyer, C. G. and Mori, H., "Analog.
Digital and Combined Analog-Digital
Computer s for Real Time Simulation".

~--~~------~----~----------~OUTPUT

1--

+Vr

o REFERENCE

FIGURE 1- THREE BIT D/A CONVERTER

D-------!
A-----..

D/A

t------8

+
FIGURE 2-DIGITAL TO ANALOG CONVERTER

A-----.....

~----8

FIGURE 3-SUMMING AMPLIFIER

276
6.2

0 - - - - -.......
A - - - -.....

......- - - 8

FIGURE 4-MULTIPLEXER

D--------------~
D/A

A - -....- -....

----B

:>-....

FIGURE 5-VARIABLE GAIN AMPLIFIER

--.. o
A
B

..........

COMP

FIGURE 6-COMPARATOR

277
6.2

....

...

82:

...

DIAl

: P OUT

I
COMP

.....

D/A2

FIGURE 7-TWO D/A CONVERTERS FEEDING A COMPARATOR

D,
AI

DIAl +
KI

D2
A2

O/A2 +

FIGURE 8 -

LOGIC FOR SUMMING TWO PRODUCTS

~--B

FIGURE 9-MULTIPLICATION OF TWO DIGITAL QUANTITIES

0\ tv
•

--J

tva:>

o
MI

M2
M3
+U~

..... p

FIGURE 10 - DIGITAL/ANALOG ARITHMETIC UNIT

POLARITY
INO

I I
I I
I

0, - - ,

-"-

DIA,

±.. -

.P
POLARITY

IND
F,

---'th-

-x...

........

"""'-

D/A ..,

ANSWER

TO
CONTROLS

I DIA,:I

"X..·I~

D/A '9

-u

III
FIGURE II - EXAMPLE I

COMP

I II
I II

---l

O\t-.:)
•
-.J
t-.:)\O

O\r-..J

I 1I
I I I

I I

r-..JO

blj

ail
0,

M,--'

L......

M2
•

In.

O/A 2

+u~

Iail-blj

M4X

IB,

.P
I

POLARITY
INO

ai2

b2j
04 -

0 3 ---,

M6 ---.

I I

M7--.

A3/

N4--.

I I

I I "-...

I n O/A,~~

S3 - - .

.II A4 /

III

I I

----,
--

T~IA,V

- TI

T2~

I+u
B3

ai3-b3j

FIGURE 12- EXAMPLE

-u

D/AI:I

B I COMP

T3~
T4

TO
CONTROLS

F2i

I I

a12-b2J T

I I

ANSWER

O/A'9

281

6.2

--..
CONTROLS a
DIGITAL COMPARATOR

......

DIAl

yy.,

..
..-

-..

,,
U2

AAA

COMP

D/A2

FIGURE 13-SCALE MODEL OF D/A ARITHMETIC UNIT
(CONVERTER-TESTER COMBINATION)

ERROR SIGNAL

282
6.2

ANALOG INPUT

DIGITAL INPUT

M,NtV _

OPERATION
REG

t...

POLARITY
DECODER

...

.. DATA
_ _- - 4...
..
.,. REG

M,N,V
..
'-----------;.;.;,D.:.;..;.:..~~: D/A

A.U.t-----

F.T :
~

'------'

...

INFORMATION GATE

4> ...
LOAD INFORMATION START COMPUTATION
~
---------------~----------~~~

CONTROLS

L....

H,P

FIGURE 14 AUXILIARY ARITHMETIC UNIT

F,T
REG

283
6.3
PBZ50
A HIGH-SPEED SERIAL GENERAL PURPOSE COMPUTER
USING MAGNETOSTRIC TIVE DELAY LINE STORAGE
By
Robert Mark Beck
Packar~

Bell Computer Corporation

Los Angeles, California

Summary
This paper presents the design objective
of a general purpose computer which is intended to serve as a component in special
purpose systems.
Some of the design considerations applied
toward meeting these objectives are also presented. The significance of the use of magnetostrictive delay memories in a low-cost
computer as well as the approach used to minimize the active elements in a flexible computer
input/output system are discussed.
Introduction
For the past three years, Packard Bell
Computer Corporation has designed and developed lJpecial purpose data gathering and
data handling systems.
A typical system function is to translate
several channels of analog information into a
prescribed digital format and record the digital
information on magnetic tape. In these
systems, an electronic mUltiplexer selects the
proper channel of input voltage and holds it for
digitalization by an analog-to-digital converter.
A special digital control unit then edits and
arranges the digital information into the required format. The digital information is then
recorded on magnetic tape.
Another typical· system function is to
generate control signals as a function of
several analog inputs. The control signals
thus generated are used to select, operate, or
control other units. A system of this type may
become very extensive, with many registers
required for such functions as accumulation of
data, multiplication, memory, shifting, or
intermediate storage of data. Therefore, even
a low-performance system of this type may require over ZOO flip-flops and 500 words of
memory.
Upon investigation of the special purpose
system approaches described above, the following major disadvantages were determined!

a. It is difficult to meet short schedules.
Large amounts of expensive design and development time are required since each system
must be built for its special function.
b. The special purpose system is not
flexible; therefore, when it becomes obsolete,
only a minimum of the 'Components can be
salvaged.
c. Because of the relatively short life of
special purpose systems, maintenaru::e knowledge and records can not be effectively accumulated.
Examination of the above facts compared
with general purpose computer characteristics
resulted in the following conclusion: A special
purpose system could have a major portion of
its disadvantages eliminated by making the heart
of the system a general purpose computer, especially designed with a flexible input/ output
which would allow it to operate with other equipment in the system. Of course, the crux of this
idea is to have the majority of the system engineering expressed in computer programming
instead of special hardware. The major advantages to be derived from this method of
implementing special purpose systems are as
follows:
a. Design and development time are minimized since a large part of the system function
is performed by the computer. Only the program
of the system must be developed, and portions
of it may be existing subroutines.
b.
The system is flexible since changes
are easily incorporated in the program to meet
new or revised system requirements.
c. The computer continues to be useful
even after the special purpose system becomes
obsolete. The major components, including the
computer, may be kept intact for use in future
systems. The program is the only part of the
system which becomes obsolete.
d.
The reliability and ease of maintenance
are increased because continual maintenance
knowledge and records will be retained for the

284
6.3
computer t which is a maj or portion of the
system. Check routines may be incorporated
to ensure that the computer is operating correctly.
Design Specifications

A computer to be used as a systems component, as set forth in the introduction,requires
stringent design specifications.
The computer must be very fast to perform sequentially the operations of a special
purpose digital system. Furthermore, a low
component count is necessary to make the computer cost competitive with the special equipment it replaces.
The communication required with other
units in a system dictates a flexible input/
output. Many input/ output channels with many
codes and formats must be available.
To be economical in all cases, the memory capacity must be expandable so that the
memory capacity can suit the size of the job.
Furthermore, programming should be made as
easy as possible in order to keep the programming time and expense less than the engineering
which it replaces. This suggests a complete
command list using single address operation.
Finally, if the computer is to be a component
in a system, it should be compact and suitable
for rack mounting.
Analysis of the above requirements led
to the design goals as follows:

High-Speed Operation - 50,000 commands per second

Minimizahon of Components
a.

30 Flip-Flops

b. 300 Transistors

Flexible Input/ Output - a.

Basic:

Flexowriter with Reader and Punch
b.

Other Equipment:

Magnetic Tape Handlers
High-Speed Paper Tape Punches
High-Speed Paper Tape Readers
Analog Voltage Multiplexers
Digitizers
Digital-to-Analog Converter
Card Punches and Readers
External Core Memories

Expandable Memory - 2,000 words

Basic - -

Expanded - - 16,000 words

Easy Programming - a.

Complete Set of Instructions

Single Address Operation

Double Precision Commands

Word Size - -

21 Bits plus Sign

Compact Construction - Suitable for Rack Mounting
Computer Description

Using these design goals, the first design
conferences were started in November 1959.
A 10-man engineering team took part in these
design conferences. This team worked simultaneously on the logic, circuitry, and mechanical design of the proposed computer.
In August 1960, a prototype of the computer
was placed in operation. Circuitry reliability
testing and program checking have been continuously performed on this computer since it
was placed in operation.
During the prototype checkout, ten production computers were built. The first production cOlll:puter was delivered in October 1960.
Memory Elements
The fundamental design decision was to
chose the type of memory element. Initially, a
magnetic drum with a 1 mc bit rate and speed
of 400 cps, and a low-speed core memory with
a cycle time of 10 microseconds were considered.
Our attention then turned to magnetostrictive delay lines, as a result of articles published
by the Ferranti Company and Arma Corporation
on the use of magnetostrictive delay line memories in the Pegasus computer and the Titan_
Missile test computer, respectively. An expandable memory could be made very conveniently by packaging each memory line as a
plug-in module. Based on a temperature coefficient of 0.5 PPM/oC, 6,144 bits could be
stored in each memory line register. This
would realize 256 words of 24 bits each per
memory line. Furthermore, using a 2 me NRZ
writing process, the desired goal for a highspeed serial operation would be practical. Hence,
based on these advantages, magnetostrictive

285

6.3
delay lines were chosen for the memory of the
PB 250 general purpose computer.
Figure 1 shows a complete memory line
module. This circuit card includes line address selection circuits in addition to the line
and the reading and writing circuits. The
writing circuit consists of a flip-flop which is
DC coupled to the magnetostrictive line's input
transducer. The reading transducer presents
a 2 mv peak-to-peak differential signal. This
signal is amplified, then reshaped by a Schmitt
circuit. The output of the Schmitt circuit is
gated into the read flip-flop. The waveforms
as they appear at various points in the delayline register are shown in Figure 3.

were designed to achieve reliable performance
with a minimum of semiconductor elements.
These circuits were derived from 3 mc circuits
used in Packard Bell Computer Corporation's
TRICE Computer ( a digital differential analyzer
system).
Computer Organization

Figure 2 shows a one-word delay line
module which is used in arithmetic portions of
the computer. This circuit circuit card is
smaller because it does not contain line address
selection circuitry.

The computer word is made up of 24 bits.
Two of the bits, the first ( a guard bit) and the
24th ( an odd parity bit), are not available to
the programming. Numbers in the machine are
expressed in binary with 21" bits plus sign. The
command format is indicated in Figure 5. This
block diagram also shows all the basic elements
of the PB 250. The heavy-lined rectangles
locate the five one-word magnetostrictive delay
line registers. The computer's 32 flip-flops
( excluding reading and writing flip-flops for
magnetostrictive delay line registers) are
summarized in Table 1.

Computer Circuitry

Arithmetic Operations

The characteristics of the basic circuits
used in the PB 250 are outlined below:

The computer's arithmetic operations are
based on the three one-word registers: A. B,
and C.

Gating - a.

Voltage Levels:
o volts (ft fals e ff level)
- 8 volts ( It true fI level)

Structure:
Two-level AND gates feeding OR
gates.

For double preCision operations, the A and
B registers are arranged to handle double precision numbers with the sign and 21 most sign!ficant bits of the number in A and the ZZ least
significant bits in B. The basic arithmetic operations are outlined below:
1.

Addition and Subtraction - Addend or Minuend ---_._..- A or A and B
Augend or Subtrahend
.. Memory
Results
.. A or A and B

Left and Right Shifting - -

Clock Waveform - Single phase, 2 mc square wave.

Flip-Flops - a.

A Register and B Register shifted as a pair,
C Register is incremented or decremented
to allow for efficient floating point subroutines.

Construction:
Two Transistors ( no clamping)

Input Coupling:
Capacitor - Diode

Emitter Followers

Multiplier
Multiplicand

One-Transistor
5.

Multiplication - -

Produ~t

.....
..

Inverter s - One-Transistor

Where delays would become too great,
transistor OR gates are formed by connecting
the emitters of several emitter followers.
Figure 4 shows the basic circuit configurations
( specialized circuits such as solenoid drivers
and clock generators are omitted). All circuits

B Register
C Register
AandB
Registers

Division - Numerator
Denominator
Quotient

~
~

...

AorAandB
C Register
B Register

286

6.3

for input! output operation.

Square Root - Argument

-------1__ A

or A and B

Square Root of
Argument - - - - - -.....- B Re gister
Each of the short registers recirculates
once per word time. Therefore, multiply,
divide, and square root commands produce one
new bit in the answers for each execution word
time. The shift operations require one word
time per shift. These commands are executed
for a programmed duration, for improved optimum programming.
Timing
Two methods of programming exist for the
PB250. The normal computer program consists of reading successive commands in sequence from a command line. This method
offers optimum storage usage. Every 3-millisecond cycle of a long memory line, a new
co~and is read and executed when the operand
in the command appears. Hence, the computer
waits a major portion of the time. An operation
rate of 333 commands per second is realizable
using this method of programming.
To provide high-speed operation, an
optimum time programming technique is av-ailable. Any command which contains an optimum code bit is called alL optimized command.
The command immediately available at the completion of the execution of the optimized command is read. Hence, the computer can be
reading or executing a command at all times.
Using optimum time programming, a computation rate of 40,000 commands per second is
obtainable.
The execution time for addition or subtraction is 12 microseconds for single preCision
numbers and 24 microseconds for double precision numbers. Execution of left shifting,
right shifting, multiplication, division, and
square root commands requires 12 microseconds
per word time of execution. As previously
mentioned, the length of execution of these commands is programmed within the structure of
the command. For example, a full-length,
22-bit plus sign multiplication requires 276
microseconds. Hence, with optimum time programming, the PB250 can perform 2,800 fulllength multiplications per second.

Each output character is delivered by an
output command which has a programmed duration. This programmed duration is controlled by using the C Register as a counter to provide output character signals ranging from 12
microseconds to 24 seconds.
Each 8-bit input character is entered into
a small input buffer contained in the computer.
These 8-bit input characters are assembled
into words by computer programming. The
same computer circuits are used to handle
character rates of 10 cps to 2,000 cps in an
efficient manner.
Computer handling of each character by
programmed operation removes any restrictions on codes or formats and also minimizes
the amount of hardware applied to input/ output
operation in the computer. High data transfer
rates may be obtained by using an external
buffer. For control applications, the computer's
complement of links with external equipment is
completed by its ability to sense the many input
lines and generate many f'f string pulling" output signals.
An external 2 mc shift register is provided
as auxiliary equipnlent for large, quick bursts
of input or output data. This is especially useful when dealing with analog-to-digital and
digital-to-analog converters, card readers and
punches, line printers, etc.
The computer may be programmed to sense
many parallel input lines. This capability is
enhanced by a command which allows program
branChing based on any of 30 input lines. The
converse is available for output operation; that
is, output pulse signaling to anyone of 30 output lines.
Finally, to provide a maximum of flexibility
for input and output, a special provision is incorporated for synchronbing and interconnecting
two or more PB 250. s. With this arrangement,
one computer may serve as the central computer, while other computer s may be us ed for
input and output functions.
Packaging

Input! Output Operation

Figures 6, 7, and 8 show the computer as
a rack-mounted component. The PB250 requires 33 1/4 inches of vertical rack space.
The Flexowriter requires an additional 17 1/2
inches of rack space.

The bulk of the input! output capability of
the PB Z50 is designed into the command structure. The computer handles characters in any
code configuration ( up to 8 bits per character)

The computer frame can accommodate up
to 15 memory lines ( approxinlately 4,000words).
Additional memory lines may be mounted in
another chassis. Any 256-word memory line

287
6.3
may be replaced by a shorter line, such as a
l6-word line. for increased fast access memory.
The total component count includes only
375 transistors and 2,300 diodes. There are
120 plug-in circuit modules. The open-book
case style. as shown in Figure 7, allows easy
access to all the socket wiring of these modules.
For program tracing, the control panel at
the left side of the front panel indicates the
status of the static flip-flops. The marginal
test switches located on the control panel are
used for varying the clock period. Further
m4rginal checking may be performed by adjusting the two main power supply voltages,
+ 6 volts and - 12 volts.
Performance Review
Although the PB 250 Computer was designed
to be a useful system component, it has also
proved to be a powerful general purpose computer. With, an automatic optimum programming assembly routine and a library of routines and subroutines, the PB 250 provides the
greatest advance in low cost computers since
magnetic drums were first used.
Efficiency of the computer is greatly increased by the use of the solid-state devices
such as transistors, diodes, and magnetostrictive delay lines. The efficiency of these components is made pos sible by using a 2 mc
operating frequency ( about 10 times the frequency of drum computers). This frequency
also allows more efficient logic coupling between the input/ output equipment and the computer. Hence, the burden of input and output
operations is placed on programmed subroutines, thereby reducing input/output hardware,
and' thus compensating for the expense of highfrequency components.
The PB 250 approaches or exceeds the
design ,?bjectives that were set for it. A large
numbei of special system programs are now
being prepared with very satisfactory performance indicated. These systems include tracking
radar antenna control, power plant control,
atomic reactor data logging, etc.
The complete PB 250 command list is
presented in Table 2. The commands in the
top half of the list are the basic single address
operations, whereas the commands in the lower
half of the list have a programmed execution
duration which starts in the word sector after the
command is read and ends at the address specified by the command.

Acknowledgements
The author wishes to express his appreciation to Dr. Stanley Frankel for his valuable
advice and consulting assistance in the design
of the PB 250 logiC. Congratulations are also
extended to Mr. Bmil Ruhman for his outstanding work on all aspects of the computert s circuit design and to Messrs. Jack Mitchell and
Donald Cooper for their efforts in the management and coordination of the overall engineering
project.

288

6.3

Table 1.
Function

Flip-Flops
FI, F2, F3, F4, F5
Ec, Rc

Pulse Time Counter ( P 1 - P 24 )
Phase Control - Ec Rc :

Wait to Read Command

Ec Rc:

Read Command

Ec Rc :

Wait to Execute Command

Ec Rc:

Execute Command

Comparison Detector - Compares Sector Counter and Instruction
Register

Oc, 06, OS, 04, 03, 02, 01

Operation Code Register

L5, L4, L3, L2, Ll

Operand Line Registel

K3, K2, KI

Command Line Register

Carry for Sector Counter

Carry for Arithmetic Unit Adder

Overflow

Parity Check

Ae, Be, Ce

Arithmetic Unit Register Shift Flip-Flops

Rf, Tf

Reader and Typewriter Controls

289
6.3
Table 2.
OP

Command

HLT

Halt

EBP

Extend bit pattern of A

lAC

Interchange A and C

GTB

Convert A from Gray to Binary

IBC

Interchange Band C

AMC

AND of M ItC

CLB

Clear B

03
04

LDC

LoadC

CLC

Clear C

LDA

Load A

CLA

Clear A

LDB

Load B

AOC

AND-OR Combined

LDP

Load AB double precision

EXF

Extract Field

STC

Store C

DIU

Disconnect Input Unit

STA

Store A

RTK

Read Typewriter Keyboard

STB

Store B

RPT

Read Paper Tape

STD

Store AB double precision

RFU

Read Fast Unit

ADD

Add

SUB

Subtract

LAI

Load A from Input

DPA

Add double precision

CAM

Compare A and M

DPS

Subtract double precision

Clear Input Buffer

NAD

Normalize AB

WOC

Write Output Character

LSD

Left Shift AB

RSI

Right Shift AB

SAl

Scale AB

2.4

NOP

No Operation

lAM

Interchange A It M

MLX

Move Memory Line to Line 7

WOC

Write Output Character

27
30

SQR

Square Root of AB to B

PTU

Pulse Specified Unit

DIY

Quotient of AB+ C to B

MCL

Move Command Line

MUP

Product of B x C to AB

BSO

Block Serial Output

BSI

Block Serial Input

TOF

Transfer on Overflow

TES

Transfer on External Signal

33
34

TCN

Transfer if C negative

TAN

Transfer if A negative.

TBN

Transfer if B negative

TRU

Transfer unconditionally

290

6.3

Fig. 1. Complete Memory Line Module

291

6.3

292

6.3
- - -Ov
Write Flip-Flop
(Driving Side)
- - -lOy

- - +Sv
Voltage Across
Launching Coil
--

-Sv

+2v

-2v

Delay Line Output
(Amplified from 2 mv
to 6 v peak-to-peak)

- - -Ov
Schmitt Output

- - - lOy

Time at 0.5 usee/div

Schmitt Output with
superimposed digital patterns

Time at 0.2 usee /div

Fig. 3. Delay Line Waveforms

293

6.3

OVVV
-BV

I 0.5 usee

Clock
Input

I
OV

-12V

AND Gate

Gate

+6V

+6v

-12V

Emitter Follower

Fig. 4. PB250 Circuits

-12V

Inverter

O\[\.;)
•
\0

Pulse Ctr

Wof:>.

Clock

Control
Ec Rc
WRC

P24

WEX
1

Ove~-

flow

I~Ol
I

P8-P15

P3-P8

~~C!-

Command Format
24

P
Rc

IVg

OP Code

Line
Selector
Parity
Bit

Optimum
Code Bit

ML
Line
Number
Read ML lrom I

Memory Lines
Guard
Bit

Fig. 5. PB250 Block Diagram

Fig. 6. PB2S0 Rack Mounted

296
6.3

Fig. 7. PB250 With Case Opened

297

6.3

Fig. 8. PB2S0 With Case Pulled Out

299
6.4
THE INSTRUCTION UNIT OF THE STRETCH COMPUTER
R. T. Blosk
Product Development Laboratory, Data Systems Division
International Business Machines Corporation
Poughkeepsie, New York

Introduction
The Instruction Unit (I unit) was developed
as the largest portion and the major control unit
of the large-scale, high-performance Stretch
computer. 1 This computer is the central processing unit of the Stretch system 2 contracted
for development and delivery to the Atomic
Energy Commission for their Scientific Laboratories in Los Alamos, New Mexico.
The purpose of this paper is to describe the
major functions. of the I-unit, give a general
picture of the internal machine organization and
the logical reasons behind it, and present several
examples of how some of the performance goals
were achieved.
A diagram of the Stretch system appears in
Figure 1. It consists primarily of the central
computer, 6 blocks of 2-usec memories (each
containing 16, 384 words of 72 bits}~ a basic I/O
Exchange unit with its associated I/O units and
adapters, and a high-speed Exchange (disk
synchronizer) unit wi th its disk unit and adapter.
The system is expandable up to a maximum of
16 memory blocks, 32 basic I/O channels, and
32 disk units.
The computer is divided into five major
elements: the memory bus control unit, the instruction unit, the lookahead unit, and the serial
and parallel arithmetic units. These are shown
in Figure 2.
One of the principal factors in achieving the
high performance in the computer is the ability
of these separate logical areas within the computer to operate independently and simultaneously. This means that while one of the arithmetic units is busy executing an instruction, the
lookahead unit can be "stacking" up the following
instructions with their operands, and the I unit
can be fetching and indexing more instructions
preparatory. to loading them into lookahead. In
many cases, the I unit can actually be executing
an instruction wholly within the I unit, simultaneously with the execution of apreceding instruction
in an arithmetic 'unit. In effect, the computer
is a form of "pipe-line" which once filled is
~apable of a very high output rate. Basically,

the main job of the 1 unit is td keep this "pipeline" filled by maintaining the instruction fetching and preparation rate compatible with the
operating rates of lookahead and the arithmetic
units.
A complete description of the specific
functional responsibilities of the I unit will be
given later. However, there were a number of
more general requirements which significantly
affected the entire design of the unit. The most
important of these were:
1.

It had to handle a large diversified instruction set in a wide variety of word formats. 3
(see Appendix Al.

It had to prepare half-word instructions,
full-word instructions, and full-word instructions across memory word boundaries.

To achieve the desired performance, it had
to process several instructions simultaneously.

It had to be completely interruptable and
.
.
4
recoverable on every lnstruchon.

It had to test for many exception conditions.!
set corresponding indicators, and be capable of suppressing or terminating the associated instruction if necessary.

It had to differentiate between three types
of memory -- external memory (EM}, index
storage (XS}, or internal register (IR} -- on
all fetches and stores (see Appendix B).

It had to update the time clocks every millisecond.

It b,ad to be virtually instantaneously
stoppable to provide meaningful automatic
error scans.

It had to be constructed with standard
circuits, panels, and frames.

10.

It had to be a reliable and thoroughly
checked unit.

300
6.4
As a result of these requirements, plus
the many assigned program functions, the instruction unit was designed and built to occupy
five full double-gate standard frames and parts
of three others, filling 46 standard panels,
using approximately 1275 standard ... circuit
double cards and 6385 standard-circuit single
cards, and requiring about 53,680 transistors.
Functions
The instruction unit has as one of its two
primary functions the fetching and preparation
of every instruction executed by the computer.
The fetching carries with it the responsibility
for checking and possibly correcting the word
after it is received from memory. Every word
in external memory contains 64 data bits and 8
error correction code (EGG) bits. These ECG
bits permit single error detection and correction plus double error detection. The preparation of each instruction involves the indexing 5
of the instruction (if required), the partial decoding to determine instruction class and unit
destination within the computer for execution,
plus the actual operand fetch and loading of the
instruction into lookahead. It also requires
various tests of each instruction for indica tor
setting and possible suppressing and/or interrupting. Some indicators require that the
instruction not be executed {suppres sed}, while
others permit full or partial execution with the
option of causing an automatic interrupt at the
·completion of the instruction. The actual point
of execution and interrupt test is not until some
time after processing by the I unit. In order to
know the memory location of every instruction
as it is tested for an interrupt, the I unit loads
the advanced instruction counter (IC) value
into lookahead with each instruction. If an
interrupt is detected later, the program can
store the IC value of the instruction following
the one being interrupted. This enables the
interrupt sub-routine to know where to return
to the main program after the interrupt.
Two type s of indexing can be spe cified -normal and progressive. The normal mode
modifies the operand address by the value of
the index word with the resultant effective
address replacing the original operand address,
In progressive indexing, the result of the algebraic addition of the operand address and index
value replaces the index value, and the original index value replaces the operand address
as the effe ctive addres s. This mode can also
specify a stepping of the count field and mayor
may not call for an automa1ic refill if the count
goes to zero.

All instructions eventually are loaded into
lookahead. There are four levels of storage
in lookahead, and each contains an op-code
field, an indicator field, an operand field, and
an instruction counter field. Normally an instruction only requires one level of lookahead;
however, some require more. An example is
a variable field length instruction in which one
level is used entirely for operation definition,
such as variable field length, byte size, and
offset. A second and possible third level is
then required fo1' the operands.
All instructions to be executed by the
floating point (FP) unit, the variable field
length (VFL) unit, and the Exchange units are
loaded into lookahead to await operand return
and subsequent execution. As the instruction
is loaded, the operand ~s fetched to the lookahead (LA) operand field, any indicators set by
the instruction so far are transferred to the LA
indicator field, and the IC value for the next
ins truction is set into the IC field.
If an instruction is of the index arithmetic
type which is executed wi thin the I unit, lookahead is loaded at the completion of the execution. In this case, the lookahead operand field
contains the old contents of the index word
that was modified. The indicator and IG field
are set normally. This provides a means of
recovering the index words which are modified out of sequence should an interrupt occur
on a previous instruction.

The second primary function of the I unit
is the actual execution of a large number of
instructions in the Stretch instruction set. Index arithmetic instructions form the largest
class in this set and they include direct,
immediate, and indirect forms of addressing.
The direct address refers to a location in
memory for the operand, whereas the
immediate address is the actual operand.
There are several special instructions which
act upon the index registers. Load Value
Effective is a load type of instruction using
indirect addressing, where the contents of the
location in memory specified by the address
may refer to another memory location. Load
Value with Sum provides a means of multiple
indexing by utilizing a form of geometric
addressing where each bit of the address refers
to a separate index register. Rename provides a method of "naming" index registers by
putting in one index register the location in
memory from which the contents of another
index register came and to which it can be
returned.

301

6.4
The Branch instructions comprise another
class which the Iunit is responsible for executing. They include all unconditional and conditional branches. The conditions may depend
upon: any of the indicators, any bit in memory,
and any index count field. In addition, each instruction has a number of modifier bits which
specify whether the branch should occur on a
zero or one condition, whether the bit should
be left alone, inverted, set to zero, or set to
one, and in the case of index count branching
whether the value field should be modified by
0, +1, +1/2, or -1. The index and indicator
branch instructions are half-word in length
and the branch on bit is a full word. The
half-word instructions may have a half-word
prefix specifying a store instruction counter
operation if the branch is successful. This
forms a full-word instruction. The store instruction counter half-word instruction never
occurs alone.
If an indicator branch is conditional upon
an index indicator, the I unit determines the
status and completely exe cutes the instruction. If the condition depends upon some other
indicator, then the I unit completes the instruction, assuming the branch to be unsuccessful. It loads the necessary operation
code, indicator location, and recovery informa tion (branch addre s s) into lookahead to
cause a test of the indicator later, after all
previous instructions in LA have been completely executed. If at this time the branch is
found to be successful, then a branch recovery
operation is initiated and lookahead returns the
branch address and all old index words to the
I unit . . This recovery is similar to an interrupt recovery.

Word transmission instructions form
another class which the I unit must execute.
These include two basic types. One is the
Transmit, which transfers data from one
location in memory to another. The other
type is Swap, which causes an interchange of
data between two locations in memory. These
instructions also contain a modifier bit which
specifies whether the word count is contained
in the instruction (immediate) or in an index
word (direct). Another modifier specifies
whether the addresses are stepped forward or
backward.
The remaining instructions executed by
the I unit include a general Refill and a Refill
on co unt zero which provides the ability of
refilling any word in memory. Execute and
Execute Indirect are two instructions which
provide the ability to execute "subject" in-

structions at direct or indirect locations in
memory. The Store Zero instruction forces
zeros into any memory location. A complete
list of I-unit instructions appears in Appendix

C.
Another function directly involving the
I unit is the automatic interrupt operation.
At the completion of every instruction execution, a test must be made on the indicators to
d~termine if an interrupt is required or not.
If not, normal program operation is continued.
If an interrupt is called for, recovery operations are initiated in lookahead and the I unit
An interrupt is signaled whenever the interrupt
system is enabled (by the program), and an
indicator in the register and its corresponding
bit in the mask register are one IS. The I unit
must determine the indicator causing the interrupt, -reset the indicator, and locate the
"free instruction" associated with that particular indicator. It then fetches the instruction, prepares it, and either executes it
or loads it into lookahead. If it is not a
successful branch instruction, the I unit returns to the original program and continues
normal operation; hence the term "free instruction". However, if it is a successful
branch, the I unit branches to the new program routine and proceeds normally until a
new branch instruction returns it to the
original program. The interrupt mechanism
is automatically disabled during the fetching
and execution of the "free instruction".
Time clock operation is another function
as signed to the I unit. The computer contains
two time clock values; an interval timer of 19
bits {8-1/2 minutes} and a real time clock of
36 bits {777 days}. These two quantities are
contained in one word located in the small,
fast-access, index core storage. Approximately every millisecond (1024 cps), while tl.le
computer is under program control, the I unit
must stop its normal operation, fetch this word,
and step the two clock values through the index
adder. The interval timer is stepped -1 and
the real time clock is stepped + 1. When the
interval timer goes to zero, a cbrresponding
indicator is set. The interval timer may be
set by the program but the real time clock may
not.
The I unit also has the responsibility for
monitoring all memory addresses for out-ofbounds conditions. All external memory
fetches for the computer are initiated by the
I unit, and each addres s is compared against
an upper and a lower boundary register. Depending upon the state of an outside-inside

302
6.4
control trigger, appropriate indicators are
~et according to the type of fetch {instruction
or datal. All stores are performed by the
lQokahead. However, before loading lookahead with a store operation, the 1 unit tests the
store address and sets a store indicator in
lookaheadl if out of bounds. These indicators
may cause suppression of the instruction and/
or an interrupt and automatic branch to a
corrective routine.
The last important function of the I unit
is providing manual controls for direct intervention by the operator console and customer
engineering maintenance console. Since the
I unit has complete control over all operations- to be performed by the computer, it was
found to be the logical place for the rm.jority
of the manual controls. These controls provide the ability to:
1. Start or halt the machine.
2. Load new programs.
3. Display or store memory.
4. Single-step the program an operation
or a cycle at a time.
S. Enter a particular instruction into
the machine.
6. Put the machine in a repeat instruction mode.
7. Continuously test index storage.
Repeat instruction mode causes the
machine to continuatly repeat the fetching,
preparation, and execution of one particular
instruction word.
In addition to these specific functions,
several problems arose which required special
handling. One of these was created by preaccessing instructions before completing the
execution of previous instructions. In the case
of store-to-memory types of instructions, it
was possible that an instruction might be
storing into the immediate program area and
particularly into an instruction that had already been fetched by the I unit. To guard
against this, a program store compare cir ...
cuit was designed which compared all in ...
struction fetch addresses against the store
address register in lookahead. 1£ the instruction fetch has not been made yet and it
compares equal, the I unit waits until the
store is complete before resuming. If the
instruction fetch has already been made, an
I-unit recovery must be made and the instructions refetched after the store is completed.
There are three different types of
'addressable memory in the system: internal

transistor registers, index,core storage
registers, and the main external memories.
This presents a problem in the I unit. When
indexing instructions and fetching operands
rapidly, the I unit loads lookahead and fetches
an operand on the cycle following the index
modification cycle. This leaves no time to
decode which type of memory is involved and
to select the correct control sequence. It is
presumed that the address refers to external
memory, and an external fetch is begun. The
decoding is complete before the midpoint of
the fetch cycle. If the presumption proves to
be wrong, the actual fetch can be blocked
and the correct fetch control can be selected
for the next cycle. If the presumption is
correct, the original fetch is completed and
a decode cycle has been saved.
These are just a couple of examples of
the many complexities which faced the design
group in designing the I unit to meet all the
functional, performance, and reliability requirements of Stretch and at the same time
keep the cost to a minimum.
Data Path Organization
The first step in the design of the unit' was
to design a data path system, with a minimum of
hardware, that accomplished all the functions
assigned to it. The next step was to determine
the amount of time-sharing that was possible,
and the amount of concurrency necessary to
achieve the high performance goals desired,
still at minimu~ cost~ Finally, after arriving
at a satisfactory compromise of the first two
points, the system was studied carefully and
checking / correcting circuitry added to obtain
the high degree of reliability desired.
The result was a machine organization as
shown in Figures 3 and 4. Figure 3 is a diagram
of the data paths for the principal part of the 1
unit, and Figure 4 is a diagram of the interrupt
mechanism. The basic I-unit organization consists of six transistor registers, two adder units
with checking, six data paths, two address
busses, and one checker/corrector unit. In
addition, there are indicator and tag storage
positions, a boundary compare unit, a program
store compare unit, lookahead load data transfer
busses, and a leftmost one detector-encoder for
the multiple indexing Load Value with Sum instruction. The interrupt mechanism consists of
two transistor data registers, one unit address
register, and a leftmost one detector-encoder.
These data paths account for approximately 40
per cent of the hardware. The remaining 60

3,03

6.4
per cent is taken up by extensive control logic,
with its associated timing, and decoder circuitry.
The six main registers in the I unit are the
instruction counter register (lCR), the instruction-data word buffer registers (1 Y and 2Y), the
index register (XR), the preparation and execution register (ZR), and the multi-purpose working register (WR).
Instruction Counter (IC)
The IC system was designed to provide the
actual memory address of the instruction currently being executed or prepared for lookahead -in the Z register, and at the same time
fetch succeeding instructions into the Y registers. Since a number (6) of instructions may
be located in the Y and Z registers simultaneously, some means had to be developed to keep
track of the instruction addresses as the instructions proceed througli the I unit. It was
found that we could eliminate the necessity of
multiple IC registers by using the one ICR to
keep track of the instruction being operated on
in the ZR, and using outputs of the ICR or the
IC adder to fetch following instructions.
The ICR contains 21 bit positions, two of
which are parity bits. The two low-order bits
are separated from the seventeen high-order
bits and haV"e their own individual advancing
mechanism to provide the flexibility needed for
advancing by half and full words. The highorder seventeen (0-16) bits feed a plus one, a
parallel, carry propagate adder, which actually provides the (ICR quantity +2> address. By
selecting combinations of ICR and adder outputs, we can obtain four full word addresses:
n, n+ I, n+2, andn+3, wherenis theICR
address. This provides all the lookahead
addresses needed for pre-accessing instructions into the Y-register instruction buffers.
The ICR has a set of in-gates (21) from
the lookahead IC buffer for use in recovery
operations. It also has a set of in-gates frorp.
the index adder out bus for branch operations.
The final set of in-gates is for setting the IC
adder output into the register for a full advance
of the IC system.
Both ICR and the IC adder output can be
gated out to the memory address bus for instruction fetching. The ICR also can be gated to the
index adder in bus A (ABA) for store instruction
counter and branch relative operations. The
ICR has a complete set of ungated output lines
to the lookahead IC input gates for loading the
associated IC address into lookahead along with

the instructions, and for program store testing.
It has a set of ungated output lines to the IC adder, and several special lines to the control
area. Another full set of these lines go to the
maintenance console for indicating the contents
of the IeR and the IC adde r output.
Instruction and Data Buffer Registers (1 Y and 2Y)
To achieve high-speed instruction preparation, particularly floating point instructions, it
was necessary to provide two instruction .buffer
registers. These two registers are identical
and are used alternately for receiving instruction words fetched from memory by the IC. They
are also used for data operands required for the
execution of instructions performed in the I unit.
They each contain 73 positions; 64 data bits, 8
check bits, and 1 memory check bit. The 8
check bit positions may contain error correcting
code (ECC) bits or parity bits. All words in
memory contain error correcting code bits, but
during the checking/correcting operation in the
I unit, the ECC bits in the Y register are replaced with parity bits for checking internal operations. The memory check bit indicates whether or not an error occurred during the memory
access, and, therefore, indicates whether the
word received is valid or not.
The Y registers have two complete sets of
input gates; one from the memory out bus
(IMOB) for memory fetch returns, and one from
the checker out bus (ICOB) for check/ correct
operations and internal word transfers~
Each Y register has a full set of out-gates
to the checker in bus (ICIB), again for checking/
correcting or internal word transferring. Each
also has two sets of half-word (36 bit) gates to
the adder in bus B (ABB) for direct transfer or
arithmetic operation through the index adder.
Four sets of out-gates from the two I fields of
each register permit addressing index storage
via the index address bus (XAB).
Both registers have 73 lines to the maintenance console for indication, plus a number of
ungated lines to the control areas for instruction
predecoding and special memory addresses.
The parity fields are split up across the Y
registers in the following manner:

(0 -

17)

(32 - 49)

PI (18 -

23)

(50 -

55)

(24 -

27)

(56 -

59)

(28 -

31)

(60 -

63)

2
3

6
7

304

6.4
These fields were found to be the best combination for effectively handling all the different
word formats encountered in the system.
Index Storage (XS) and Index Register (XR)
The specifications for the Stretch Computer
called for 16 index words located in high-speed
storage. The first approach was to use 16 transistor registers, but this was soon found to be
undesirable for several reasons. One was that
it was extremely expensive, particularly if each
register was to be capable of directly operating
with the index adder to perform all instruction
indexing functions and the execution of all index
arithmetic operations. Another reason was that
the large amount of hardware involved presented
a packaging problem and detracted from the anticipated high performance. It was apparent that
a buffer register would be required, which alone
would have all the required logical capabilities
and would allow each of the 16 index registers to
be transferred into it prior to execution. This
still presented a large and expensive piece of
hardware. The ideal solution was found by providing a compact, high-speed, 16-word, nondestructive-read, core memory for the index
words, with one data register (XR) to read into,
store out of, and perform all the logical operations
required.
The index storage (XS) was 'ac:tually designed
with 17 words of 73 bits each. The seventeenth
word contains the interval timer and the elapsed
time clock for rapid access and advancing of
these values. It is a two-dimensional array
(17 x 73) and has a read-out time of approximately
200 nanoseconds. Total access time including
address gating, transmission, and decoding requires one machine cycle. To store the contents
of the XR into XS requires two cycles. The first
one destructively reads the selected word, thereby resetting it to zeros, and the second cycle
writes the XR contents into the selected row of
cores. The index address is checked during the
decoding. The XR is checked during the following
logical operation for which the index word was
fetched.
The index register was designed with two
principal objectives in mind. One was to provide
the function of a data register for fetching and
storing to/from index storage. The other was to
provide the ability of executing all the full word,
half word, field transfer, and logical operations
required to execute all the I-unit instructions.
The result is that the XR has five sets of ingates and out-gates with many separately controllable fields.

This register contains 73 bit positions including 64 data and 9 parity check bits. Eight of
the check bits correspond to the eight in the Y
registers, and the ninth is the parity on bits 46 49 to provide means of obtaining a parity check
on the index count and refill fields.
The primary input to the XR is directly from
the sense amplifiers of the index storage during
an index fetch operation.
A full set of gates (73)
allow gating from the I-checker out bus straight
into XR for checking and full word transfer operations. Four sets of gates allow gating from
the adder out bus into four different fields of the
XR. These fields are: the 25 bits of XR beginning
at position 0, the 25 bits of XR beginning at position 32, the 18-bit count field beginning at position
28, and the l8-bit refill field beginning at position
46. These gates are all: used in the execution of
various types of index arithmetic instructions.
In addition to these inputs there is a direct reset
of all 73 positions for setting the XR to zero prior
to a read-out of index storage.
The XR has a full set of out-gates (73) to
the checker in bus for checking and full word
transfer operations. It has three sets of partial gates to the adder in bus "A". These provide the ability of gating the value field, the
count field, and the refill field to the adder for
arithmetic ope ration or transfers through the
adder. One set of gates (24-27) to the adder
in bus B provides the ability to check the sign
of the value field during value field operations
in the adde r.
There are three detector circuits connected directly to the XR. These circuits provide
the following indications:
X value less than 0

X count equal to

X value equal to 0

X count equal to 0

X value greater than 0 X refill equal to all l's
These are used to set indicators or modify
execution controls for various operations. In
addition, there are a number of special ungated
outputs of the XR which feed adder true/ complement controls, execution controls, and parity
adjust logic in the parity checker/generators.
A full set of ungated outputs go to the maintenance console for indicator purposes.
Preparation - Execution Register (ZR)
This register is the basic operating register
of the I unit. Every instruction is placed in

305

6.4
this register from the Y registers for indexing.
decoding. execution. and lookahead loading.
It is full word in width to accommodate full word
instructions and to speed up floating point halfword instructions. All full-word instructions
appear straight. left to right in the register.
regardless of how they were received from
me,mory and placed in the Y registers. There
are a large number of output gates on the register because of the many special functions
performed in the register in indexing (normal
and progressive). executing I-unit instructions.
fetching operands. and loading the instructions
into lookahead.
The ZR contains 74 bit positions. including
64 data and ten parity bits. Eight of the ten
parity bits correspond to the standard eight in
the Y and X registers. The other two are for
parity on the channel address field (12 - 18) for
I/O instructions, and the length field (35 - 40)
of VFL instructions. Associated with the ZR
is a small three-bit P register which is used
solely for retaining the progressive indexing
code (bits 32 - 34) during any index modification
of the right half of a VFL instruction.
The only in-gates provided on the ZR are
for gating the adder out bus into various positions of the ZR. There are two sets of these
gates. one for the left half of Z and the other
for the right half. These gates have split control to provide for partial gating. This takes
care of all the in-gating required by instruction
transfers from Y to Z, plus all arithmetic result gating into Z.
The out-gating of the ZR is more extensive
and complicated. There are two sets of outgates for gating the left half or the right half of
Z to the adder in bus B for arithmetic operations
on the left or right operand addresses. There
is a separate gate for gating the length field
(35 - 40) to the adder in bus A for word boundary cross-over test. and a separate gate for
sending the immediate count (50 - 55) in transmit instructions to the W register for counting
purposes. There are two sets of out-gates provided for gating the left (0-17) or right (32 -49)
operand address to the memory address bus for
operand fetches. There are five sets of gates
for gating the left or right operand address. the
left or right J field (index operand in index instructions). and the left I field (index address
for index modification) to the index address bus.
These permit fetching of index word operands
and the index fetch for the delayed modification
of the left half of Z.
There also is a set of ten out-gates to the
checker in bus for rearrangement of fields for

loading instructions into 100kahead. These also
have split control for selecting the width of the
fields.
In addition to the in and out-gates. the ZR
has 41 positions line driven to the control area
for operation and memory area decoding. As in
the case of all the registers. all positions of the
ZR have an ungated line to the maintenance console for indicator purposes.

Working Register (WR)
This register is only 19 positions long (including one parity). It is used primarily for
operand address storage. and secondarily as the
counting register for transmission type instructions which cross memory word boundaries. for
multiple indexing address decoding. and for automatic refill and interrupt address operations.
In transmIt operations the direct or immediate
count field is placed in the W register for counting purposes. while the from and to operand addresses remain in Z for the fetching. storing,
and stepping operations.
The WR has three in-gates: one from the
adder out bus for transfer and arithmetic operations. one from the maintenance console keys
for manual insertion of an address. and one from
the interrupt bit address encoder for automatic
interrupt operations.
The WR has three out-gates: one to the adder in bus A for arithmetic operations such as
counting. one to the memory address bus for
word boundary crossover and refill fetches. and
one to the index address bus for index fetches.
Ungated outputs of the WR feed a leftmost
one detect logical unit for multiple indexing address decoding. The output of the detect circuit
feeds an address encoder. the output of which
is set into a five-bit register called the geometric
load address register (GLAR). The detect and
encoder logic is checked.
Ungated outputs of the WR also feed various
decoder circuits for determining special address
and contents equal to one conditions. The output
of the leftmost one detector (LMOD) feeds the
adder in bus B for resetting the current multiple
indexing address bit in WR by a subtract operation through the index adde r . The output of the
GLAR feeds the index address bus for index
fetching during the Load Value with Sum execution.
All 19 positions of the WR and five positions of
the GLAR go to the maintenance console for indicator purposes.

306

6.4
Index Adder Unit (IAU)
The specifications for the I unit called for
arithmetic operations on fields up to 24· positions wide. High performance required a parallel adder of advanced design with a minimum
of logical levels. In order to guarantee complete reliability, it had to be thoroughly checked. Since the many operations of the I unit required all the registers to be capable of feeding
the adder, it was found that the transfer and
adder paths could be combined and time-shared
to provide the most economical and yet completely checked system. This was accomplished
by providing an eight-bit bypass path around
the 24-bit adder to permit half-word {32-bit}
transfers. A further study indicated that the
best performance could be gained by providing
a controlled complementer on one input, with
automatic re -complementing ability on the output. The basic 24-bit parallel adder was broken up into six four-bit blocks with parallel
carry lookahead and carry propagate detect
logic for each. Garries from block to block
and end-around carries are detected early and
propagated through. The 24-bit add or subtract is accomplished in five logical levels.
Input checking is accomplished by comparing
input parities with the half sum parity. and the
rest of the adder is checked by a. carry prediction checking method.
Standard I-unit parity is generated on the
output in parallel with special memory address
decoding. The bypass eight positions are parity
checked and passed through to the output bus.
The output is completely latched at sample
time to prevent race conditions through 'the ungated paths when gating the result back into one
of the input registers.
The adder in bus A (ABA) has a complementer on the input and is accomplished in the same
logical level that does the ~Ringo The inputs to
ABA are the IG, WR, XR, and ZR. Th,e ABB
is not complemented and the inputs come fro'm
the YR's, the LMOD, and the ZR. In-addition,
there are numerous lines to control the complementing, re-complementing, and pa·rity adjustments for various fields and operations.
The adder out bus (IAOB) has 32 data bit positions plus 11 parity bit positions for selection,
depending upon the fields involved. The IAOB
feeds the left and right halves of the ZR, the
left and right halves, count, and refill fields of
the XR, the WR, and the IGR.
The I Ghecke r
One of the earliest requirements of the
Stretch system was for automatic error correc-

tion of memory words. The method adopted
was that of using the Hamming 6 error-correcting code (EGG) which required eight EGG bits
with a 64-bit data word. In the I unit it was
necessary to be able to check and correct memory words (instruction and operands) and convert
to the I-unit parity system. It was also necessary
to provide a full word transfer bus for highspeed transfer operations in executing many of
the I-unit instructions. It was found that these
two operations could share equipment by combining the transfer bus with the full word EGG
checking/ correcting and parity checking/ generating logic. It was also found that the EGG
checking/ correcting operation on instructions
could be overlapped with the initial pre -decoding
required on the new instructions when they are
received in the Y registers.
Lookahead had a similar problem with EGC
checking/ correcting and parity checking/ generating on operands fetched to lookahead by the
I unit, and in storing result operands to memory.
A study of the two units showed that one I
checker unit could be time -shared between the
I unit and lookahead, provided a fast priority
system could be designed to guarantee little
loss in performance. This was done and the result is a single I checker with separate I checker
in busses from the I unit and lookahead OR'd at
the input to the checker. The checker out bus
(IGOB) is a 64-bit data bus plus 29 parity and
EGG lines for selection by the controlling unit
for the proper parity or EGG bits for the receiving register. This bus feeds the four lookahead levels· first and then the XR and the 2Y re·
gisters. The output of the checker is completely latched at sample tim~ to prevent race conditions through the ungated paths while gating the
result into the receiving register.
Interrupt Mechanism
Figure 2 shows a block diagram of the interrupt mechanism. It consists of a 64-position
indicator register (IR). a 28-position ma.sk register, and a leftmost one detect and encoder
circuit.
The indicator register has two inputs; one
from '.:he arithmetic checker out bus (AGOB),
and the other, the individual turn-on line from
each indicator's particular logical area. These
logical areas include the I unit, the VFL and FP
execution units, lookahead, exchange, and
memory. There is no parity on the contents of
this register because it is continually changing,
due to the many asynchronous inputs. The only
out-gate on the IR is to the arithmetic checker
in bus (AGIB) and is used for transferring the
contents of the register to another location.

307
6.4
Similarly, the input gate from AGOB is for
bringing in a new word to the IR. Ungated outputs from a portion of the register feed the updated indicator register in the I unit for recovery purposes. A full set of ungated outputs feed
the leftmost one detector and the maintenance
console.
The mask register has an input only from
the ACOB for bringing in a new mask word. It
also can be gated to the AGIB for storing purposes, and has ungated outputs to the leftmost
one detector and maintenance console. Logically, the first 20 positions (0 - 19) of the mask
register are always one, and the last 16 positions (48 - 63) are always zero. They are
fixed and are not programmable. There are
four parity bits associated with the mask register positions 21 - 47, and they conform to
the parity flelds of the arithmetic bus and
checker.
The leftmost one detect circuit has two
functions; one to test rapidly for any match
between an indicator position and its associated mask bit, the other to determine, in the
case of multiple matches, which one has higher
priority. Priority is established from left to
right (0 - 63), and the match with highest
priority blocks the remaining ones f:tom being
effective. The test for any match is done in
only a few levels by ORing all the compare
And circuits, and signalling an interrupt if the
mechanism is enabled. The enabling/disabling
is controlled by a single trigger which is set
on/ off by programming. Once an interrupt is
signalled, the leftmost one detect logic is
allowed time to establish priority, to encode
the matching pair of indicator and mask bits
into the register bit address of the particular
indicator, and set it into the' WR. The bit
address is a six-bit address plus one parity
bit.
Included in this logical area is a seven-bit
channel address register which is used to hold
the address of the I/O unit which sets I/O status
bits into the indicator register. This register
may be set by either the basic or high-speed
exchanges and includes two parity bits.- It can
be gated to the AGIB (positions 12-18) for transfer purposes.
Also designed for this area but not packaged
was the other GPU e1."egister. This register of
19 positions is used for systems involving more
than one computer. It can be gated out to the
ACIB and gated in from IGOB for transfer purposes. There are four parity bits associated

with the 19-bit field to conform with the arithmetic bus and checker requirements.
Updated Index Indicator Register (UXIR)
There are eight triggers in the I unit which
contain the status of the index register involved
in the most recent index arithmetic instruction
executed by the I unit. These indicators differ
from the status of the corresponding main indicator register triggers by the effect of the index arithmetic instructions which have been
executed by the I unit but whose result indicators are still in lookahead awaiting transfer to
the indicator register in proper instruction
sequence-hence, the term'updated indicators".
This UXIR is used to test for conditional
branches on these indicators.
A listing of the indicators contained in the
updated indicator register is as follows:
1.
2.
3.
4.
5.
6.
7.
8.

Index
Index
Index
Index
Index
Index
Index
Index

low - XL
equal - XE
high - XH
count zero - XGZ
value less than zero - XVLZ
value zero - XVZ
value greater than zero - XVGZ
flag - XF

Indicator and Address Tag Triggers
Due to the multiplicity of instructions that
are contained in and being operated on simultaneously in the I unit, it is necessary to tag
(store with the particular instruction) each instruction with identifying informati.on regarding
certain conditions which may arise during its
processing. Examples of these conditions are
memory and ECG checks on new instructions,
parity checks on instruction transfers from Y
to Z, and type of memory address decoded
during ,the transfer through the index adder.
These triggers are located for the most part in
the control area, so that they can immediately
condition the control trigger outputs of the
following cycle. There are some 26 triggers
of this nature in the control area of the I unit.
These include the following:
A.

Y Register Tags

1.
2.
3.
4.
5.
6.

1Y
2Y
IY
2Y
1Y
2Y

instruction fetch indicator
instruction fetch indicator
operand address invalid
operand address invalid
identifiable check
identifiable check

lYlF
2YIF
lYAD
2YAD
lYIDG
2YIDG

308
6.4
7.
8.

1 Y memory check
2Y memory check

Z Register Tags

Z left operand address -special (0':'15)

2.
3.
4.
5.

12.
13.
14.

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

W Register Tags

2.
3.

W operand address-special (0-15)
W operand address-index (16-31)
W operand address nonexistent

General

I unit contains non-identifiable check

6.
7.
8.

9.
10.

ll.

left operand address -index (16-31)
left operand address-nonexistent
right ope rand addre s s - s pe cia1 (0 -15)
right operand address-inde~ (16-31)
right operand address -nonexistent
left instruction fetch indicator
right instruction fetch indicator
left operand address invalid
right operand address invalid
left contains identifiable check
right contains identifiable check
contains data store condition
contains data fetch condition

1YMC
2Y1v.tC

ZLSA
ZLXA
ZLNA
ZRSA
ZRXA
ZRNA
ZLIF
ZRIF
ZLAD
ZRAD
ZLIDC
ZRIDC
ZDS
ZDF

WSA

WXA
WNA

NIDC

Control Orsanization
The remaining hardware in the I unit is
taken up by an extensive and complex system
which controls the flow of instructions and operands in the data paths previously described, in
many different combinations of simultaneous and
asychronous operations. The system consists
primarily of many control triggers, commonly
referred to as control stages or sequencers,
plus their input and output switching logic and
ORing of control lines to the data paths. Also
adding to the hardware is the extensive decoder
logic required to determine which operation and
variation is called for in instruction preparation
and execution. Associated with the control is a
considerable amount of powering circuitry for the
distribution of the clock pulses in each control
area. These clock pulses originate at the computer master clock and are distributed to various units using delay line techniques for skew
minimization. The data paths and control were
designed to operate with a 4 megacycle clock and
at present are operating at a 3.3 megacycle rate.
The I-unit controls operate at half the master
clock frequency.
The controls are divided logically into the
following categories:

1. Instruction cou.nter
2. Instruction preparation
3. Lookahead loading
4. Instruction execution
5. Miscellaneous
IC Controls
The instruction counter controls consist of
eight control stages for sequencing the operation of fetching instructions to the Y registers,
checking I correcting them through the I checke:r,
and advancing the IC :register. There are thirteen supervisory control storage triggers to condition the control stages as to whether a fetch is
in progress (outstanding), lY or 2Y is empty, ZL
or ZR is empty, a branch to lY of 2Y is required,
or a recovery is required. Six tag triggers indicate whether there are any checks, instruction
fetch alarms, or invalid addresses assoclated
with the instructions in the Y registers. There
are eight block and suspend triggers for ins.taneously interrupting the normal IC operation to
allow the I-unit instruction execution controls the
use of the Y registers.
These controls essentially attempt to keep
the Y registers filled with new and checked instructions. They signal the preparation controls
whenever Y register data is ready for transfer
to Z. In branch and recovery operations, the IC
controls are designed for rapid resetting and restarting at the new address in order to minimize
the time required to refill the Y regiSters.
These controls time share the I checker and
the memory address bus with other controls.
They operate simultaneously with the preparation and lookahead load controls as long as no
interlock occurs to indicate that no YR is empty,
an I unit instruction requires execution, or an
interrupt is required.
Preparation Controls
The preparation controls consist of eight
control sequencers which control the preparation of all instructions for the computer. This
preparation involves the transfer of instructions
from the YR' s to the ZR. the index fetching and
address modification if required, and the word
boundary crossover test for VFL instructions.
In addition to the sequencers, there are six
supervisory type control triggers which condition
the selection of the right or left half of the
current YR and the corresponding half of the ZR.
Instruction pre-decoding as to type of instruction and indexing requirements is stored in
eleven supervisory control triggers. There are
eight additional tag triggers associated with the

309

6.4
two halves of the ZR to indicate the class of
floating point instruction in Z, so that the lookahead load controls can rapidly take over and
load lookahead without a delay for decoding
purposes.
These controls signal the IC controls when
a YR is empty, and signal the lookahead load
controls or I-unit execution controls when the ZR
has a prepared instruction. These contro Is are
a completely independent set of hardware and
operate simultaneously with the IC and lookahead load controls. Their function is basically
to empty the YR I S and prepare and fill the ZR as
rapidly as possible. to insure a high rate of instruction flow through the computer.

Instruction Execution Controls
To execute the large number of I-unit instructions in all their variations required the
design of a large control system. The instructions were categorized by type and then divided
into logical operations and analyzed for maximum sharing of common controls. Circuit
limitations and packaging rules often prevented
sharing as much as was desired. As the control
logic grew, it became necessary to package it in
two frames instead of one, which, in turn,
created a communication problem in critically
timed areas. In order to keep the number of
logical levels to a minimum, it was necessary
to design a large amount of parallel logic into
and out of each control stage.

Lookahead Load Controls
The lookahead load controls consist of fourteen sequencers which control the loading into
lookahead of all I/O, VFL, and FP instructions.
Five of these deal solely with the loading of
VFL instructions and are in the form of a fivestage execution timer. Every VFL load begins
with the first stage and may then step to anyone
of the remaining four, so that every VFL instruction requires anywhere from two to five
steps. Each sequencer loads a different look ..
ahead level so that a VFL instruction may occupy
two to five levels. 1£ an operand address refers
to an index address, the basic sequence is broken
out of in order to fetch the index word by means
of a common index fetch sequencer, and then
control is returned to the VFL load sequence"!",::.
There are two complete sets of our FP load
sequencers for each half of the ZR. This was
necessary to guarantee the fast switching and
loading from the two halves of Z required to
achieve the high FP performance. Each set of
four FP sequencers controls the loading of onelevel or two-level FP instructions, depending
upon whether one or two operands are involved,
and it controls the actual fetching of the operands from external memory, index storage, or
internal registers. The majority of FP instructions require only one control step in which the
operand is fetched from main memory at the same
time that the FP instruction is loaded into the
single lookahead level.
While this loading is being executed, the IC
and the preparation controls rna y be simultaneously operating to maintain the instruction rate.
The lookahead load controls signal the preparation controls when an instruction is completely
loaded and the instruction in the ZR can be rep laced with a new one.

The instruction set was divided into four
categories: index arithmetic, branch. transmit.
and miscellaneous operations. Each group was
worked on separately. and the control sequences
and logic required were designed. These controls were then compared for similarities.
and wherever possible. common control logic
was combined. The result was that sixty-one
control sequencers and nine supervisory
triggers. plus an operation decoder. were required to execute the instructions in satisfactory
performance times. These controls provide for
fetching and checking operands from memory
(main memory, index storage, or internal registers), index adder logical operations, partial and
full word transfer, checking operations, and the
loading of lookahead with a large variety of operation codes and indicators. Most of these
operations have a large number of input and output conditions whose combinations can cause each
operation to be performed in a wide variety of
ways. Other requirements of these controls were
that they be able to stop immediately on errors,
be recoverable in case of instruction suppressing
and interrupt conditions, and be able to manually
step a cycle at a time. Every control stage has
a line to the maintenance conso Ie for indication.
Miscellaneous Controls
These controls are used primarily in the
execution of the manual operations and the
special recovery routines. They consist mostly
of supervisory control triggers which initiate,
condition, and terminat e control sequences
which perform the desired functions. The actual
operations within the sequences are controlled by
sequencers in the instruction execution area,
and are shared for this purpose. For this reason
the execution operation decoder must be blocked
so as not to affect the stepping of the sequences
for these special operations. Some special con-

310
6.4
trol functions also taken care of in this area are:
a store wait control when lookahead contains a
store to XS, or the indicator or mask registers;
time clock operation triggers; and I unit recovery
because of program store test. Some of these
special functions are very critically timed, since
they must block normal operation immediately,
or it will be too late and unrecoverable damage
may be done. These controls are packaged in the
IC control area so as to minimize the communication delay of the interlocks.
Performance Characteristics
Since the Stretch computer was originally
contracted for by the Los Alamos Atomic Ene rgy
Commission, certain of its performance goals
were particularly important to the customer. Of
primary importance was the complete floating
point operation, including the instruction fetching, preparation, operand fetching, and actual
execution. In the branch instruction, the Count
and Branch instruction was to be used extensively for controlling the many iterative program
loops characteristic of scientific computing. The
variable field length operation was desirable and
attractive but its performance need not be, nor
could it be economically, as high as FP. The
index arithmetic instructions were all very important.
The manner in which the Instruction unit
achieves the desired performance goals in these
areas wi 11 follow. These examples are chosen
because of their special importance in scientific
computing, and one should not infer that all the
remaining operations were not important or not
at a comparable performance level. The high
overall performance goals of Stretch required
that all the operations be executed in a much
more powerful manner than any previous
machine.
Floating Point Instruction Preparation
A timing diagram showing the preparation
of continuous FP instructions is shown in Figure
5. The preparation includes the fetching of instruction words from 2 usec memory, the ECC
checking of the instruction, the Y to Z transfer
and index fetch, the address modification, and
finally the operand fetch and lookahead load. It
can be seen how successive instruction fetches,
preparations, and lookahead loads are overlapped to achieve a performance goal of one FP
instruction every two cycles. Each instruction
is assumed to require indexing. If this were not
the case, then instantaneous rates would reach
one FP instruction every cycle, but the average
rate would still remain at one per two cycles.

This is because the maximum rate of instruction
fetches is balanced with the maximum indexing
rate and lookahead rates.
The diagram starts out by assuming a startup operation (either program start or recovery
operation) where two rapid fetches are made by
the IC to the Y registers. When the words are
received from memory, they are immediately
checked; if there are no errors, an extra
correct cycle is not required.
During
the check cycle, the ECC is converted to
parity and the preparation controls pre -decode
the type of instruction. In this case each word
contains two FP instructions. The next cycle
is the transfer from the left half of I Y to the
right half of Z. The criss-crossing of halfword locations was adopted as the simplest
way of handling the different combinations of
full-word and half-word instructions that can
occur. During this transfer, any addressed
index word is fetched into the XR. Assuming each instruction is to be indexed, the
next cycle is the actual address modification,
where the index value in X is added to the operand address in ZR through the index adde'r and
the result replaces the original operand address.
These last two cycles tied up the lAU, so the
next instruction in 1 YR waited. The first instruction is now ready for loading into lookahead and fetching of the operand. With the lAU
not busy, we can also transfer the next instruction to ZL and fetch its index word. The operand fetch would be initiated were it not for the
1 YR-ZL transfer emptying the 1 Y register.
The Ie controls anticipate this and try to fetch'
the next instruction word (IC + 3) into it. This
conflicts with the operand fetch of the lookahead
load cycle, but since -the IC controls have
priority, the IC fetch is made simultaneously
with the 1 YR transfer to Z and the index fetch.
The lookahead load cycle is blocked during this
cycle and completes the operand fetch and the
load operation on the following cycle, overlapped with the modification of the second instruction. This early instruction fetch
guarantees that the 1 Y register will be filled
and checked by the time the 2Y register is
emptied. In this manner the flow of instructions can be maintained. The degree of simultaneity in the I unit is best illustrated by the
cycle with the single asterisk (*) which shows
an instruction fetch to 2Y, a check cycle on 1 Y,
a 2YR transfer to Z, an index fetch, and an
attempted lookahead load, all occurring at the
same time.
The high degree of overlapped operation in
the computer is best shown by the last cycle
(**). In this cycle the following operations are

311

6.4
occurring simultaneously:

1.
2.

3.
4.
5.
6.
7.

Instruction 1 is being executed and
checked.
Instruction 2 is being transferred from
LA to the PAU.
Three of the 4 LA levels are loaded
with instructions 2, 3, and 4.,
Instruction 5 is ready to be loaded and
its operand fetched.
Instruction 6 is being transferred from
lYR to ZL.
The index word required by instruction
6 is being fetched.
Instructions 7 and 8 are being ECC
checked in the I checker and being predecoded.
The IC is fetching the 5th instruction
full word containing ins tructions 9 and
10.

This is but one variation of FP preparation. Other variations develop when the operand address refers to index storage or an
internal register, or where a second operand
is implied, as in Multiply Cumulative and Load
Cumulative Multiplicand, or when different
types of instructions are intermingled with the
FP ins tructions .
The diagram not only indicates how one
performance goal is achieved, but also indicates
the large amount of control complexity required
to efficiently interlock and execute this I-unit
instruction preparation function. It further illustrates how complete overlap of instruction
fetching, indexing, and lookahead loading is
achieved.
VFL Instruction Preparation
The preparation of a variable field length
instruction is shown in the timing diagram of
Figure 6. Starting at the same point as Figure
5, it shows the sequence when the second instruction is a full word VFL instruction located
across memory word boundaries. In this case
the left half of the first instruction word fetched
is an FP instruction, and the right half is the
left half of the VFL instruction. The left half
of the second instruction word fetched contains
the right half of the VFL instruction, while the
right half of this word contains another FP instruction.
The first instruction is processed exactly
the same as in the previous example. Notice
that this time when the right half of 1 Y is transferred to Z left, the eventual correct alignment
of the full-word instruction in Z is provided for.

Again, any index word addressed by the half
word in 1 YR is fetched into the XR. Before proceeding into the modification cycle, however,
the type of indexing called for. normal or progressive, mus't be determined. This information
is contained in the right half of the instruction,
and is not available until the 2Y register has
been filled, checked, and pre-decoded. In the
example, this is completed by the end of the
1 YR to ZL transfer, so no wait is required.
Assuming normal indexing, the next cycle is
the modification cycle for the left half. If progressive indexing (PX) had been specified, a
much different sequence would have been required, and the operation would be done in two
steps. The first one would replace the VFL
operand address with the value field of the index word, and the instruction preparation would
continue on and be loaded into lookahead. Following the lookahead loading, a control sequence
would be entered where the increment, count,
and refill operations on the index word, if
called for, would be executed. The results of
this operation would then be loaded into lookahead as the second of PX operations.
After normal modification of the left of the
VFL instruction, the right half is transferred
from 2YL to ZR and its index fetch executed.
The next cycle then modifie s the right haif of
the instruction. The indexing and instruction
operation codes are preserved during the modification. The next step is to determine whether
one or two memory words are required to obtain the operand field. The operand field can
start at any bit position in a memory word and
extend into the next memory word as long as
the total field length is 64 bits or less. The
word boundary crossover test (WBC) is done by
adding, in the index adder, the length field to
the full 24-bit operand address field. If a carry
into position 17 of the operand address field
occurs, then the instruction operand does, in
fact, cross memory word boundaries. The highorder 18 bits of the result are gated into the WR,
and this is actually the operand address for the
second memory word.
This completes the preparation, and all
that is left is to load the instruction into lookahead and fetch the operands. In this case
three cycles are required. The first loads the
instruction operation information into one
lookahead level. Since the data field is used
for part of the instruction information, no
fetched operand can accompany this level. The
next two cycles are for fetching the two operands
of the instruction into two more levels of
lookahead. The number of cycles required to
load VFL type instructions varies from two to

312
6.4
five, depending on whether the instruction requires one or two operands, whether it is a
fetch or a store to memory type of instruction,
and whether any special registers are implied
in addition to the operand addres s.
Having successfully loaded the instruction,
the next half word FP instruction can be transferred from 2YR to ZL and the normal FP prepara tion continued.
The dia.gram shows that the VFL instruction in this case took eight cycles as compared
to two cycles for a normal FP. If the instruction had no indexing specified and only one
operand memory word was required, the operation would have only taken five cycles. Again,
there are many variations of these instructions,
depending on the type of indexing required,
whether the instruction arrives straight or
across memory words, whether the operands
are in XS, EM, or IR, and whether it is a store
to memory operation or not.
Count and Branch Execution
The execution sequence for a Count and
Branch (CB) instruction is shown in Figure 7.
Assuming a continuation of the FP preparation
of Figure 6, the fifth instruction is defined as
a CB instruction. In the example, it is assumed
that the instruction requires indexing, and therefore, it is possible to overlap the operation decoding with the modification cycle. Otherwise,
it would have been necessary to take a separate
decode cycle. Once decoded, the operation
enters an execution sequence controlled by the
decoder outputs and conditions arising out of
the individual operations. The first cycle is a
fetch of the index word, whose count field determines whether the branch is successful or
not. The next cycle, the fetch of the branch
address instruction, is initiated, and at the same
time the count field of the index word in the XR
is decoded for a XC = I condition. If the condition for branching exists, the fetch is completed;
if the condition does not exist, the fetch is
blocked. This permits as rapid a fetch of the
next instruction as possible, in order to begin
filling up the Y registers with the new sequence
of instructions. Overlapped with the instruction fetch is the loading into a lookahead level
of the index word before modification. This is
referred to as a psuedo-stol"e level, and is only
used in recovery operations where the index
registers have to restore to some previous
level as a result of an interrupt or no-op condition. The next cycle is the actual counting down
through the index adde r of the count field of the
index word in the XR. After this is done, the

value field can then be advanced or diminished
'J:>yone or one-half, if called for by the instruction. This is also done through the index adder.
At the same time, the advanced IC value (address
of the instructions following the CB) is loaded
into the same lookahead level as the psuedostore. This is done because the next cycle destroys the IC contents by transferring into it
the branch address from Z. If a no-op of this
instruction is required, the I unit can continue
straight on in the program. After the advance/
diminish cycle, the updated index word is returned to XS. This is done by a clear cycle for
resetting the word during the same cycle that
transfers the branch address into the IC, and
then following with a store cycle which sets the
contents of the XR into the previously reset
word in the array. To complete the operation,
all indicators associated with this instruction
and the new IC value are loaded into lookahead
to be tested later in proper instruction sequence
for an interrupt. If a condition occurs which
will no-op the instruction, then the new IC field
is not loaded, only the indicators and a no-op
tag. This will cause any branching already done
to be cancelled by a recovery operation later.
Since the instruction branched to was
fetched early in the operation, the new instruction word has arrived and has been checked by
the time the CB instruction is completelyexecuted. Immediately the normal instruction
preparation is restarted, and in this case, the
branched to FP instruction is loaded into lookahead four cycles later.
The entire execution of the instruction
took six cycles and was overlapped with the
operand fetch, ECC check, and execution of
instruction 1. In other words, it took ten
cycles from the completion of one instruction
in the program to branch to another program
location and prepare and load the first new FP
ins truction into lookahead.
Variations of this instruction execution sequence occur with respect to the branch condition being 0 or not 0, the advance/diminish
modifiers, and the setting of indicators that may
cause a no-op or interrupt. In addition, there
are other instructions in the same category
which are more complicated and time-consuming. These include the Store Instruction Counter if Count and Branch (SIC - CB), the Count,
Branch, and Refill (CBR), and the SIC-CBR
variations.
Summary
The instruction unit is a large com.plex,
high-speed com.puter unit designed and built to

313
6.4
provide the major functional ability and control
for the Stretch Computer. A complete description of the major functional requirements is
given along with some examples of the difficulties encountered. The machine organization,
including data paths and controls, is described,
and many of the primary design considerations
are discussed. The complexity and size of the
unit are largely determined by the instruction
buffering, fast access index registers, the extensive overlapping and simultarleity of operations, and the innumerable combinations and
variations of instruction sequences that have to
be controlled. "The control is achieved by a
synchronous clock controlled network of variable sequence execution control stages. The
performance is shown for a few typical and
particularly important operations.

de sign of the data paths.
The overall engineering effort was under the
supervision of Messrs. E. Bloch and R. E.
Merwin.
References

Erich Bloch, "The Engineering Design of
the Stretch Computer, '1 Eastern Joint
Computer Conference Proceedings,
December, 1959.

S. W. Dunwell, "Design Objectives for the
IBM Stretch Computer, " Eastern Joint
Computer Conference Proceedings,
December, 1956, p. 20.

W. Buchholz, "Selection of an Instruction
Language, "Western Joint Computer
Conference Proceedings, May, 1958, p.128.

F. P. Brooks, Jr., "A Program-Cont:rolled.
Program Interruption System, "Eastern
Joint Computer Conference Proceedings,
December, 1957, p. 128.

G. A. Blaauw, "Indexing and Control-Word
Techniques, It IBM Journal of Research and
Development, July, 1959.

R.. W. Hamming, "Error Correcting and
Error Detecting Codes, " Bell System
Technical Journal, 1950, pp. 29, 147.

Acknowledgments
To give individual credit to the many people who
have contributed to the design of the instruction
unit would be impossible. However, major des~gn contributions were made by the following
individuals: Mr. S. F. Anderson for the index
adder and branch instruction execution controls,
Mr. L. L. Headrick for the interrupt mechanism, index arithmetic, and transmit inst:ruction
execution controls; Mr. C. R. Holleran for the
IC system and lookahead load controls;
Mr. S. L. Lindauer for a
portion of the data
paths and the instruction preparation controls;
and Mr. L. F. Winter for his assistance in the

0'1 W
.......
,j::o.,j::o.

16K WORDS- 2 MICROSECOND MEMORIES

2 INTERLEAVED

4 INTERLEAVED

INST
MEM

OPND
MEM

-1

•

•
l

•

...
.oil

•

MEM BUS CNTL UNIT

____- - - - - - ' f f

•
DISK
HS
EXCHANGE

•
~

I AOIPTI
PARALLEL
DISK
FILE

tl....-_ _ _---,

•

BASIC
~

I/O

CENTRAL COMPUTER

.oil

EXCHANGE

ADAPT

•

AO;PT
•

ICONSOLEII CD RDR II CD PUN

I IAO;PT I IAO~PT I IAO~T I
•

II PRINTER II

Fig. 1. The Stretch System.

•

TAPES

II TAPES I

729 12:

MULTIPLE MEMORIES

.I
BASIC ~
EXCHANGE

DISK
\4
EXCHANGE

•

..-r'

•

•
MEMORY BUS

CONTROL UNIT
~

MEMORY OUT BUS

......

INST REG I
INST REG 2
INDEX
REGS INSTRUCTION UNIT

MEMORY IN BUS

LEVEL I
LEVEL 2
LEVEL 3

•
INDS/CNTL

LOAD

LEVEL 4
LOOKAHEAD

SERIAL ARITHMETIC
UNIT
(VFL)
____________
_

t---+

ARITHMETIC REGS. t---+
STORE I

INDS/CNTL

BUS ,AND CHECKERS
1- - - - - - - - - - - - -

--+t PARALLEL ARITHMETIC t---+
UNIT

( FP)
BASIC EXCHANGE

D~K E~HANGE

•

~~TERRUPTM~HAMSM~~~~~~~IN=D~S~/~CN~T~L~~~~~~~~~

Fig. 2a. The Stretch Computer Central Processing Unit.

0\'-"
.......
"'" C.J1

0\ W
•

I-'

"""0\

MAINTENANCE CONSOLE

MEMORY BUS CONTROL
UNIT

INSTRUCTION UNIT

LOOKAHEAD SAU

PAU

ARITH. REGS. 8 CHECKER

Fig. 2b. The Stretch Computer Central Processing Unit.

TO LOOKAHEAD

MEMORY OUT BUS (64)

'\
f

...

FROM LOOK AHEAD
A

....

4~~

INDEX
REGS. (16)
~~

IYR
(64)

ICR
(19)

•

2YR
(64)

IC
ADV (19)

XR
(64)
INDEX ADR

ADDER

"
~r

,
U

INDEX
ADDER
(24-32)

a
~

,BUS A

"
~,

CHECKER I N BU~,

I
CHECKER
(64)

ADDER BUS B

...
...

WR
(18)

MEM ADR BUS

ADDER OUT BUS

ZR
(64)
BUS

TO LA

CHECKER OUT BUS

TO MBCU~

...

JIll .

....

.....

FROM ....
LA

J
.~

LA LOAD

......

OPERATION
DECODER

--..

Fig. 3. Instruction Unit.

INSTRUCTION PREP
EXEC CONTROLS

"'w
.......
~-...1

ARITHMETIC CHECKER OUT BUS (64)

O\W

•

I-'

~oo

HIGH SPEED EXCHANGE (7)
BASIC EXCHANGE (7)
MEMORIES (I)
EXCHANGES (9)

UNIT (5)

ARITH EXEC (24)
LOOKAHEAD (15)

++++++

•

INDICATOR REGISTER
(6'4)

MASK REGISTER
(28)

•

• •

OTHER CPU
REG (19)

UNIT ADR
REG (7)

•

ARITHMETIC CHECKER IN BUS (64)

LEFT MOST ONE
DETECT

•
INTERRUPT DETECT
AND BIT ADR ENC

Fig. 4. Interrupt Mechanism.

INTERRUPT ADDRESS TO I

UNIT (6)

MAS

IF-IY
t - - -...., .......

IF-2Y

...... ...........--... ..... ....... .....
...... .......

I CHKR

...... ......

....

IY.. ,Y................. 2Y-2Y
...... I CHK~
.... ICHKa'
DEC
DEC

...... - -

1<:......

...... ......

IY -IY
........,
I

XF/IYL
1

.........

..........

XF/IYR
I
I

XF/2YL
I
I

XF/2YR
I
I

XFIIYL
I
I

XFIIYR
I
1

ZR-LA
t----I

ZL-LA
1
I

1--- I .

ZR-LA

ZL-LA
I
I

ZR-LA
1----1

I
I

FP2

FP 3

LA#3

I
I

IFP 4

LA#4

L---_-,

LAI-E

LA .-. E

EACH FP I NST. INDEXED

FP1

LA#2

ASSUMPTION;

2Y-2Y
...... -1
I

LA#I

EXEC.

IF-IY

IYL- ZR MOD ZR IYR-ZL MOD ZL 2YL-ZR MOD ZL 2YR-ZL MOD ZL IYL-ZR MOD ZR IYR -ZL

IAU

LALD

IF- 2Y OF-LA30F-LA4

I....... ...... I
............

IF- IY OF-LA, OF-LA2

ILA2I

E
I

EI
. I

4 FP INSTRUCTIONS
8 CYCLES
FP RATE = 1/2 CYCLES

Fig. 5. Floating Point Instruction Preparation.

."'w..~

O\W
•

t-;)

MAB
I CHKR

IF-IV
t - - -.....I.....

IF-2Y

..... .....
..... .....

I.....

..... .....

........

IF-IYOF-LA I
I
,_
I

...... ..... ,

..... ......
.....

IV-IY ..... .....
2Y-2Y
--I
+ I
........ I
+ I
CHK
CHK
DEC
DEC

.....

.......... _

XF/IYL
I
I

XF/IYR
I
I

2YR-ZL

XF/2YR
I
I

XF/2YL
I
I

ZR-LA

LALD2LALD3LALD4

... - - - .....
I---t

FP 1

VFLII

I
VFLI

I
I

LA- E
EXEC.

LA#-2

LA#4

IVFLI

I
I

LAI- E
I
I

L
ASSUMPTION S t
I. VFL I NST. ACROSS MEM. WOo BOUNDS
2. NORMAL INDEX BOTH HALVES.
~ TWO OPNDS. REQD.

IY-IY
..........,
1

LA.;¥ I

LA#'3

IYL-ZR MOD ZR IYR-ZL MOD ZL 2YL-ZR MODZR WBC

IAU

LALD

OF-LA30F-LA4IF- 2Y

8 CYCLES

Fig. 6. VFL Instruction Preparation.

MAS

OF-LA

IF/Z-Y

IF-2Y

IF-IY
1",,- ""

........................
I

CHKR

IAU

IYL-ZR MOD ZR
I
I
I

XFIIYL
I
I

LALD

ZL-LA
I
I

MISC

X-LA
I
I

IC-LA
I
I
INoS-LA

XFIIYR
I
I
ZR-LA
... ----1

IYL -ZR MOO ZR IYR-ZL MOD ZL
I
I
I
I
I

CL/Z ST/Z XF/IYL
J
J
I
I
I
~

XF/Z J
I

DEC
I

COUNT AoV/olM Z-I€R

2Y-2Y
"""" ""-..... 1
1

6 CYCLES

Fig. 7. Count and Branch Execution.

O\W

"'" I-'

322
6.4
APPENDIX A
Instruction and Index Word Formats.

VFL

OA
1718

0
1/0

-I

TRANSMIT

SIC - BR

BR ON BIT

1000

ADR

1000

ADR

SIC

INDEX

IMMED. INDEX

DATA

COUNT a BR

BR ADR

BR. IND.

ADDRESS

ADR

COUNT
28

31
63

III

IND

III

REFILL
4546

I I

1000

28
60

ADDRESS

17
49

ADR

DIRECT INDEX

MISC.

OFFSET

AOR

I I

LENGTH BS

3132 35

lsi

0
32

11000 I I

VALUE

CHANNEL :ADR

FROM

110001 I

323
6.4

APPENDIX B
Memory Address Assignments
Location
0
1 P, a
1 P, b
2P
3P
3P
3P
4
5b
6
7
7
8
9
10
11 c
12 d
13
14
15
16-31
32-k

Name
Zero
Inte rval time r
Time clock
Interruption address
Upper boundary
Lower boundary
Boundary control bit
Maintenance bits
Channel addre s s
Other CPU
Left Ze ros count
All ones count
Left half of accumulator
Right half of accumulator
Accumulator sign byte
Indicators
Mask
R.emainder
Factor
Transit
Index registers XO - XIS
Normal external memory

Length
64
19
36
18
18
18
1
64
7
19
7
7
64
64
8
64
64
64
64
64
64
64

Bit Address
0-63
o - 18
28 - 63
o - 17
o - 17
32 - 49
57
o - 63
12 - 18
o - 18
17 - 23
44 - 50
o - 63
o - 63
0-7
o - 63
o - 63
o - 63
o - 63
o - 63
o - 63
o - 63

Type
EM
XS
XS
EM
IR
IR
IR
EM/MC
IR
IR
IR
IR
IR
IR
IR
IR.
IR.
EM
EM
EM
XS
EM

Permanently protected area of memory.

R.ead-only except for STORE VALUE, STORE COUNT, STORE
REFILL, and STORE ADDR.ESS.

bRead-only.
c

Bit positions 0 - 19 are read-only.

Bit positions 0 - 19 are always ones, and bit positions 48 - 63
are always zeros.

Last word address in a particular memory configuration.

IR.

Internal Register

Index Storage

External Memory

Maintenance Console

324
6.4
APPENDIX C
I Unit Instruction List

Modifiers:

A. Direct Index Arithmetic

a)
b)
c)
d)

1. Load index.

2. Load value.
3. Load count.

4. Load refill.
5. Store index.

6. Store value.
7. Store count.
8. Sto re refill.

E. Bit Branching
B ranch on bit

9. Add to value.
10.
11.
12.
13.
14.
15.

1.
2.
3.
4.
5.

6.
7.
8.

9.
10.
11.
12.
13.
14.
15.
16.

Modifiers:

Add to value and count.
Compare value.
Compare count.
Rename.
Load value effective.
Store value in address.

B. Immediate Index Arithmetic
Load value immediate.
Load count immediate.
Load refill immediate.
Load value negative immediate.
Add immediate to value.
Add immediate to value and count.
Add immediate to value and count
and refill.
Subtract immediate from value.
Subtract immediate from value and
count.
Subtract immediate from value and
count and refill.
Add immediate to count.
Subtract immediate from count.
Compare value immediate.
Compare value negative immediate.
Compare count immediate.
Load value with sum.

Leave indicator.
Set indicator to zero.
Branch if off.
Branch if on.

a)
b)
c)
d)
e)

Leave bit.
Invert bit.
Set bit to zero.
Branch if off.
Branch if on.

F. Index Branching
1. Count and branch.
2. Count, branch, and refill.
Modifiers:
a) Branch if count non-zero.
b) Branch if count zero.
c) Leave value is changed.
d) Add half to value.
e) Add one to value.
f) Subtract one from value.
G. Store Instruction Counter If
H. Transmit Operations
1. Transmit
2. Swap.
Modifiers:
a)
b)
c)
d)

C. Unconditional Branching
1.
2.
3.
4.
5.

Branch.
Branch relative.
Branch enabled.
Branch disabled.
Branch enabled and wait.
6. No operation.

D. Indicator Branching
Branch on Indicator

Forward
Backward
Direct count
Immediate count

J. Miscellaneous Operations

1.
2.
3.
4.
5.

Refill.
Refill on count zero.
Execute.
Execute indirect and count.
Store zero.

325
6.5

THE PRINTED MOTOR: A NEW APPROACH TO INTERMITTENT AND
CONTINUOUS MOTION DEVICES IN DATA PROCESSING EQUIPMENT
R. P. Burr
Circuit Research Company
33 Sea Cliff Avenue
Glen Cove, New York
Sunnnary
The printed d-c motor is characterized by high pulse torque capability and
freedom from cogging or preferred armature positions. These attributes lead to
a variety of applications in data processing equipment ranging from reel and
capstan drives in magnetic and paper tape
transports through detenting and positioning mechanisms.
Analysis of the motor on a velocity
basis yields a simple equivalent circuit
which is a powerful tool for designing
both the machine and its drive circuits
into a specific requirement. Since there
is no rotating iron in the structure and
since the field is supplied by permanent
magnets, the speed-torque curve of the
motor is a straight line whose slope defines a ''mechanical source impedance."
Inertia of the proposed load appears as
a capacitor in the same dimensional system. When the desired machine motion can
be expressed in terms of velocity and the
inertia of the load is known, the shape
and magnitude of the necessary driving
signal can be determined for the operating cycle.
A typical example of an application
in a paper tape transport is described.
Machine Structure and Printed Armature
Most of the important electromechanical characteristics of the printed
motor are shown in the exploded view of
a typical small machine as given in
Figure 1. Here we see the mechanical
relationship of the five key elements of
the device: exciting magnets, armature,
field return path, brushes and bearings.
In the photograph the eight pole pieces
of the permanent magnet cage are visible
to the right. These are polarized alternately north and south, so that there are
actually four pole pairs in the structure.
One should imagine that magnetic flux
leaves some particular pole, travels

parallel to the machine axis and traverses the armature disc into the soft
iron return ring at the left. Within
the return iron the flux divides and
travels in both directions circumferentially until it arrives under adjacent
magnetizing poles of opposite polarity.
At this point it re-emerges into the air
gap, passes again through the armature
and thence back into the magnet. Hence,
we have what is in effect a planar or
axial air gap d-c motor structure in
which the torque producing conductors
rotate independently of the magnetizing
iron, and in which, reciprocally, the
uniformity and smoothness of the magnetic
field is virtually unaffected by rotation
of the armature. The photograph also
shows the brush locations. One may observe that commutation takes place directly upon the surface of the armature
disc so that every conductor is commutated
in sequence. This point is of considerable importance when added to the fact
that rotation of the armature does not
modulate the flux density. The result
is that the printed motor displays no
cogging whatever: the armature has no
tendency toward a preferred set of
positions.
It would be difficult to imagine
a d-c motor of simpler construction. The
key, of course, lies in the design and
fabrication of the printed armature which
serves not only as the motor winding but
as the commutator, or vice versa. The
details of this important component need
not concern us here since they have bten
discussed elsewhere in the literature •
Suffice it to say for present purposes
that the armature is produced by modern
printed circuit techniques from a mas~er
drawing: the conductors have a flat
cross-section, are uninsulated in the
conventional sense, and are carried upon
a substrate of mylar, epoxy-glass, or
high-alumina ceramic, as the application
demands. The technique may be practiced

326

6.5

for machines ranging in power output up
to several mechanical kilowatts and in
peak torques from a few ounce-inches to
several thousand pound-feet. In each
case the armature may be thought of as
the "annular" equivalent of a wave winding in which commutation takes place upon
every active conductor.
Electro-mechanical Characteristics

negligible; torque at stall is in phase
with the applied voltage. Subsequently,
we shall be discussing intermittent operation of the motor at frequencies of
several hundred cycles per second so
that this point should not be neglected.
Equivalent Circuit Development
Equation (2) and the plot of Figure

4 show clearly that the end points of any
In order to visualize applications
for the printed motor we must first examine its electro-mechanical characteristics and attempt to construct an analogy for its performance as a circuit
component. As with most physically uncomplicated structures, we shall find
this approach to be both easy and gratifyingly simple.
A first step is to consider the relationship between speed and torque which
may be deduced from an inspection of
Figure 3, which is a schematic of the
machine from an electrical point of view.
Resistor ra is defined as the armature
resistance plus brush resistance plus the
resistance of the source of voltage ET,
if any. Voltage e a is the back EMF and
is related to the speed S in thousands of
revolutions per minute (or some other convenient unit) by a constant factor k e •
Similarly, the output torque, T, is given
by T = kT ia where kT is another constant
factor. Application of Ohm's law to the
circuit yields the classical equation for
an ideal shunt wound or permanent magnet
field d-c motor:
14"~
......L"

T ra
kT

keS

I:"a

kekT

+ S

Upon pursuing this idea a little
further, we are led to the concept of
an electromechanical equivalent circuit
on the basis of speed as shown in
Figure 5. Here the usual voltage source
is replaced by a generator of speed, Si,
delivering an "output" So through an
internal resistance, &ms. The flow of
torque, T, through &ros causes a speed
drop as shown in Figure 4. Torque is
therefore analagous to current. Nothing
is lost in regarding the machine from
this viewpoint, since Figure 3 and
Figure 5 are identical except for a change
of dimensions. Consideration of the power
relationships in both circuits will demonstrate this fact.

(1)

A slight rearrangement of this expression leads to:

family of speed-torque curves are a function only of the motor terminal voltage,
EI. A further step may be taken by recogn zing that the slope of these curves,
ra/kekT,is a useful measure of quality
in such machines. The dimensions of the
slope are speed-change-per-unit-appliedtorque and it may be thought of as reSUlting from an equivalent series mechanical resistance, which we shall designate by the symbol &ms.

(2)

which is the equation of a straight line
as shown in Figure 4 having a negative
slope numerically equal to ra/kekT.
Before continuing, we should pause
to note that no component for electrical
inductance is shown in Figure 3. In
point of fact, the inductance of a printed motor armature is so small as to be

The circuit of Figure 5 is a first
approach and is adequate to describe the
motor only so long as we are dealing with
steady state conditions and torque loads
(including friction from bearings and
brushes) which are independent of speed.
Practical experience with and analysis
of printed motors has shown that the total
loss torque to be expected must always
contain a viscosity component, or a torque
which is proportional to output speed, in
addition to a constant value. Graphically
the behavior is as shown in Figure 6. To
be consistent with our previous concept
of mechanical resistance we will assign
the symbol HmD to the slope of the viscosity or damping torque line. The damping,
component of torque to be expected at any
speed is therefore So/RmD.

327

6.5

By substituting the speed-varying
torque component into equation (2) or the
circuit of Figure 5, one obtains:

for several types of printed motors are
listed in Table II.
Interpretation of Equivalent Circuit

(3)

Having now devised a useful tool to
aid in thinking about the motor we are
in a position to draw several conclusions:

which, after some algebra, becomes:
S.
RmD
_ 'TI Ruts RutD
~ Rms+RmD
F Rms+RmD

(4)

whereupon we observe with the aid of
Thevenin's Theorem that RmD is a shunt
"resistor" across the output tenninals
of the network, as in Figure 7.
To complete the network for transient
operating conditions, which are usually of
chief concern in servomechanisms, we must
provide a component for the mechanical inertia of the motor and load. By inspection of the equations of motion for a
printed motor, one arrives at the conclusion that mechanical inertia may be represented as a capacitor of appropriate magnitude connected in parallel with RmD across the network output tenninals. In
particular, a possible equation of motion
for the circuit of Figure 5 in response to
a velocity "step", Si, is:
So

dS o
- J -dt- x Ruts

(5)

where J denotes total system inertia.
Rearranging this slightly we get
dS

JRms

o
--+--

First, we note that the veloctty
response of the motor to changes of the
input speed (i.e., applied tenninal
voltage) or output torque will be exactly analagous to the electrical response
of the equivalent single-time-constant
RC network. Conclusions on frequency
response, power dissipation, source
impedance and the like are equally valid
for either system. This is a comfortable
fact because it means that the motor is
a simple element to consider in the overall design of a servomechanism.
Second, the arrangement of the
circuit indicates clearly that an increase of the viscous damping component
is beneficial to the system response
time. The corresponding reduction of
RroD lowers the motor time constant, i.e.,
we broaden the bandwidth by loading the
"capacitor." At the same time, excessive
damping will result in an inefficient
machine useful only at low speeds, since
the speed attenuation through &rns into
RmD ultimately becomes large.

(6)

Third, for high perfonnance the
resistance of the "generator" is extremely
important and should be kept low with respect to the annature and brush resistance.
Otherwise the effective value of Rms will
rise above the theoretically attainable
value and the time-constant will increase.

(7)

Fourth, tne perfonnance of the motor
as a transducer is critically dependent upon
flux density in the air-gap. Both ke and
kT vary directly with field strength, so
that the value of both Rms and the timeconstant vary inversely as the square of
the field.

which is solved to obtain:

In this equation the factor J • Rms
is the system mechanical time constant,
1r, and is to be compared with the
analagous factor R • C in a simple
resistance capacitance network.
The complete equivalent circuit is
shown in Figure 8. Two sets of con~is
tent units are given in Table I, while
specific values of the various elements

Fifth, the transition between the
velocity input to the network and the
actual driving voltage is given by the
factor ke' since ET = ke Si. This is
to say that once the desired input velocity has been detennined the corresponding driving voltage is in direct
proportion.

328

6.5

Application
Two general types of servos are of
interest in the field of data processing
equipment. The first covers the range of
motor applications in velocity servos for
magnetic tape reel and capstan drives,
analog mUltiplying devices and similar
continuous motion applications. The second
area contemplates intermittent operation
of the machine as in paper tape drives,
card handling apparatus, printers and so
on. In this field, the desired result
usually involves the rapid and precise
acceleration and deceleration of some
medium from one position to another in a
manner which may not be repetitive. Control is usually provided by some form of
pulse position servo, the signals to the
motor being simply "ON" or "OFF". The
equivalent circuit is particularly useful for this type of operation since the
velocity hehavior in either of the two
states can be easily predicted.
Figure 9 shows a typical arrangement
for the step-by-step advance of perforated paper tape. Let us assume that it
is desired to eliminate all brakes and
clutches from the transport and to accomplish movement of the tape simply by
starting and stopping the motor,--which
is directly coupled to the tape drive
capstan. Further, we wish that slewing
operation with stop on a character be
available without modification to the
system. To achieve these conditions,
the following sequence of events can be
supposed:
1. Start: The motor is at
rest with the tape in registry
over the reading aperture. A
clock or command pulse is received, switching the electronics
and the power transistor controlling the motor into the
conducting state.
2. Run: The motor velocity
rises rapidly to its terminal
value (or very nearly) before
~ext sprocket hole appears
in the reading aperture. (This
condition guarantees a stop
will occur in registry independent of the tape travel
while slewing.)

3. Stop: A stop pulse is
received from the tape,
switching off the electronics
and the motor. The motor
velocity decays to zero in the
interval between the arrival of
the sprocket hole at the edge
of the reading aperture and the
movement of the hole to a position of good registry.
In order to arrive at the desired
velocities in the neQwork, we must
calculate from the various times,
velocities and displacements implied by
the specifications. One commences the
design by adjusting the diameter (and
there£ore the inertia) of the capstan
drum so as to maximize linear acceleration at the drum periphery. Next, the
total permissible time for the motion
may be calculated from the maximum
stepping speed required; it might be,
for example, 5 milliseconds for standard
one-inch paper tape. For the time period from Start to Stop as previously
described, one must assume that about
2.5 time constants elapse, so as to be
sure~t the motor is near terminal
speed when the Stop Signal is received.
Further, it is reasonable to assume
(by calculation from the equivalent
circuit) that the motor may be effectively stopped in about one time constant
with a small amount of reverse pulsing.
Therefor~we oonclude that the entire
motion time must occupy about 3.5 time
constants, so that one time constant
must equal about 5/3.5 or 1.4 milliseconds. Finally, we can estimate the
various displacement components of the
cycle accurately, since these are given
by the drum diameter and the dimensions
of the tape. From the information on
motion time, drum diameter, running
displacement and time constant, one may
calculate and plot a curve of the motor
output velocity which must be delivered
by the equivalent circuit. A typical
result is sketched in Figure 10. Note
that a reverse pulse is shown as beginning at Stop. The negative voltage
pulse applied to t~e motor terminals
during this interval is such that it
would result in a complete reversal of
the machine along. the dotted line extending into the negative velocity'region
if sufficientLy proionged.
The corresponding veloc'ty (or

329

6.S
terminal voltage) input to the network is
shown in Figure 11. The forward or "run"
velocity is effectively that obtaining at
the instant of Stop in Figure 10, since
we assume that terminal velocity has been
achieved during the "run" period. The
reverse velocity amplitude must be consistent with the assumption of a complete
stop in about one time constant. This is
the same thing as saying that the reverse
velocity asymptote shown in Figure 10 must
be
1 _

1
1 - lIe

times the forward velocity. The pulse
duration is set close to the expected
stopping time, but is not critical since
an error in timing when the motor velocity
is near zero results in only a small displacement.
Reduction to practice with such a
design procedure is fundamentally a
series of successive approximations: the
designer is bound by limitations of the
motor itself in terms of the realizable
values of Rms and RmD which may be
employed to get a usable result. Further,
the effect of friction torque is always
beneficial to intermittent motions if it
is not excessive and is difficult to
assess until the physical apparatus is
tested: friction is easily compensated
by raising the forward velocity and
assists in a rapid stop since the friction
torque "current" di~charges the inertia
"capacitor." In general terms, the
equivalent circuit approach is valuable
since it provides a point of departure
and as a means for reconciling unexpected
phenomena which are so often experienced
in matters of this sort.
Developmental Tape Reader
The circuit parameters and schematic
driving arrangement for a newly developed
high performance printed motor in a developmental paper tape reader are shown in
Figure 12. Note that the damping resistor,
RmD, which would normally be several ttmes
Ruts (Table II), is adjusted to be half
the series resistance. In practice this
is accomplished by laminating the armature with a thin disc of soft aluminum.
The tape capstan drum and other mechanical
parts of the machine are carefully adjusted to achieve low inertia.
°

Operating tests on this reader
transport show that a mechanical time
constant of about one millisecond has
been achieved. The motor will execute
the complete cycle of start, accelerate,
run, shut-off, decelerate and stop at
a rate of 250 lines per second for
standard one-inch paper tape. Stopon-a-character is automatically obtained
for slewing operation while the reader
will advance blocks of tape ten lfaes
long at a rate of 25 per second.
Conclusion
The printed motor is an electrically
simple device, providing smooth torque
from a low inertia mechanical structure.
Linearity of the speed-torque curves
allows the construction of a simple
equivalent circuit which accurately
represents the transient performance of
the machine in continuous and intermittent motion servos. The feasibility
of a proposed application may be studied
and a design formulated by reconciliation
of the desired velocity behavior with the
machine parameters.
1

Henry-Baudot, J. and Burr, R. P.,
"Printed Circuit DC Motors for
Electronic and Instrument Applications,"
IRE National Convention Record, Part 9,
March 1959 and Burr, R. P., "Printed
Circuit Motors" presented at 1959
AlEE Machine Tool Conference,
Cleveland, Ohio, October 20, 1959.

330

6.5

Table I
Consistent Units
Equivalent Motor Speed Network

Speed is measured in 1000 rpm, denoted by kpm.
Armature resistance, r a , in ohms.
Torque per ampere, kT' in in-oz/ampere.
Back EMF per kpm, ke' in volts/kpm.
Mechanical resistance, Rms, Rm~ in kpm/in-oz.
Inertia, J, in 105 x in-oz-sec •
Terminal voltage, ET, in volts.
Note:

The mUltiplying factor 105 for J arises from
a conversion between radians per second and kpm.

Speed is measured in radians per second, rad/sec.
Armature resistance, r a , in ohms.
Torque per ampere, kT' in gr-cm/ampere.
Back EMF per kpm, ke, in volts/rad/sec.
Mechanical resistance, ~s, Rmn in rad/sec/gr-cm.
Inertia, J, in gr-cm-sec •
Terminal voltage, ET, in volts.

Table 11

Motor

Rms
kpm/in-oz

l\nD
19!m/in-oz

?:
mi11iseconds

Cont.
Torque
in-oz

Peak
Torque
in-oz

Case
Diameter
inches

PM 368

94.5 x 10- 3

842 x 10- 3

150

4.250

PM 368 A

94.5 x 10- 3

13.2 x 10 -3

150

4.25

PM 488

23.5 x 10

400 x 10- 3

42.5

375

5.625

106.6 x 10- 3

140

1175

7.125

12.13 x 10- 3

1000

8400

11.0

7 x 10- 3

1.5

375

5.625

668

PM 1028
PM 368 HF

-3

2.5 x 10- 3
242 x 10- 3
15 x 10- 3

0\(..1)

•

(..I)

c.n ......

332
6.S

333

6.5

F19. 2. Desi gn of Printed Ci reud
O

Armat ure

0\ to\)
•
to\)
CJl~

rQ.
eGa:
•

'4.

ke S

T= kT iQ.

".-~,

S,T

E.::.

T rQ. + keS

Fig. 3. Electrical Schematic of Ideal Shunt-Wound or Permanent Magnet D-C Motor.

ET/

T=O,S= /ke

ra..

--0

S'~pe: ke.kT

""0-

cI)

TOY9 ue
Fig. 4. Printed Motor Speed Torque Curves
0\(.1.)
•

(.I.)

tJltJl

0'\ W

•

CJ10'\

Rms

,t
T

So
rO-

R
=
Si.= 7ke. ms ke. kT
ET/

Fig. 5. Elementary Mechanical Impedance Concept

337

6.5

{t::

~c
:>

8-(1)
8
e
"
.~ 0 ~
>u

-f.I

....0""0

:E
U

Ccal

~ ..

+Q..~
.~

ItS

"'tj

....c::Q)

CU
:>
()
~

't:
0..

as
c::

fIl

6""

f-4
fIl
fIl

......
0

c::

....

,~
,~

- -- ---

fIl

0
0..

U
~

ti:

338

6.5

Fig. 7. Location of Mechanical "Viscosity" Re sistance

Fig. 8. Complete Equivalent Speed Network Including Inertia Capacitor

Ca.fs:t-Cl.n

_....t. -:

:. ___•• ;--_.1

~t~r J

LAw., '"
•
TQ.."eo 0 0 ~ 00
--~

~efld

Meoj-_

ElecTYon,c:s

.,S1-op
,§1-G.W't

Fig. 9. Operating Principle of Step-by-Step Paper Tape Reader

"'w
•
W
c.n\O

340
6.5

•

I
I

~tI

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INDEX BY AUTHORS
Page
AXEL, G. J.:

UNIVAC - RANDEX II - Random Access Data Storage System. .

189

BECK, ROBERT MARK: PB-250 - A High Speed Serial General Purpose
Computer Using Magnetostrictive Delay Line Storage ................

283

BENDER, R. R. ; DOODY, D. T. ; STOUGHTON, P. N.: A Description of the
IBM 7074 System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

161

BLOSK, R. T.:

The Instruction Unit of the Stretch Computer . . . . . . . . . . . . . . . .

299

BURR, R. P.: The Printed Motor: A New Approach to Intermittent and
Continuous Motion Devices in Data Processing Equipment ...........

325

CROSBY, D. R. and KAUPP, H. R.: Calculated Waveforms for the Tunnel
Diode Locked-Pair Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

233

CUNNINGHAM, JAMES A. ; MEISSNER, PAUL; KETTERING, CLAUDE A. :
A Computer for Weather Data Acquisition .. ~ . . . . . . . . . . . . . . . . . . . . . . . .

DOODY, D. T. ; BENDER, R. R. ; STOUGHTON, P. N.: A Description of the
IBM 7074 System . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . .

161

FREIMAN, C. V.; KIM, W. H.; YOUNGER, D. H.; MAYEDA, W.:
On Iterative Factorization in Network Analysis by Digital Computer. . .

241

GILSTAD, R. L.: Polyphase Merge Sorting - An Advanced Technique.. . . . . . .

143

GORDON, WILLIAM L., DR.: Data Processing Techniques in Design
Automation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

205

HANNIG, W. A. and MAYES, T. L.: Impact of Automation on Digital
Computer Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

211

INNES, DAPHNE: FILTER - A Topological Pattern Separation Computer
Program . . . . . . . . . . . . . . . . . . . . . . -. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INNES, FRANK T.: High Speed Printer and Plotter. . ... . . .. . .. . .. . . . .. . .. .

153

JOR Y, JOHN H.: Hot- Wire Anemom.eter Paper Tape Reader. . . . . . . . . . . . . . .

267

KAISER, V. A. and WHITTAKER, J. L.: A Computer-Controlled Dynamic
Servo Test System. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

255

KAUPP, H. R. and CROSB Y, D. R.: Calculated Waveforms for the Tunnel
Diode Locked-Pair Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

233

(Continued)

INDEX BY AUTHORS, continued
Page
KAVANAGH, R. F.: TABSOL - A Fundamental Concept for SystemsOriented Languages
............................................

117

KETTERING, CLAUDE A. ; MEISSNER, PAUL; CUNNINGHAM, JAMES A. :
A Computer for Weather Data Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . .

KIM, W. H.; FREIMAN, C. V.; YOUNGER, D. H.; MAYEDA, W.: On Iterative
Factorization in Network Analysis by Digital Computer. . . . . . . . . . . . . . .

241

KOZARSKY, K. and LING, A. T.:

173

The RCA 601 System Design. . . . . . . . . . .. . .

KRANTZ, F. H. and MURRAY, W. D.: A Survey of Digital Methods for
Radar Data Processing .......
0................................
o

LANGMUIR, CHARLES R.: A Logical Machine for Measuring Problem
Solving Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0

LING, A. T. and KOZARSKY, K.:
LOMBARDI, LIONELLO:

••

The RCA 601 System Design ..

•

'0'

•••••••

•••

•

o. . . .

Theory of Files

1
173
137

MATTESON, R. G.: High Speed Data Transmission Systems. . . . . . . . . . .. . . . . .

MAYEDA, W.; KIM, W. H. ; FREIMAN, C. V. ; YOUNGER, D. H.: On Iterative
Factorization in Network Analysis by Digital Computer. . . . . . . . . . . . . . .

241

MAYES, T. L. and HANNIG, W. A.: Impact of Automation on Digital
Computer Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

211

MEISSNER, PAUL; CUNNINGHAM, JAMES A.; KETTERING, CLAUDE A.:
A Computer for Weather Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . .

MILLER, A. EUGENE: Organization and Program of the BMEWS Checkout
Data Processor

MULVIHILL, DENNIS E .. and REDMOND, GOMER H.: The Use of a
Binary Computer for Data Processing ........................•....

149

MURRAY, W. D. and KRANT Z, F. H.: A Survey of Digital Methods for
Radar Data Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PETRICK, S. R. and WILLETT, H. M.: A Method of Voice Communication
With a Digital Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(Continued)

INDEX BY AUTHORS, continued
Page
REDMOND, GOMER H. and MULVIHILL, DENNIS E.: The Use of a Binary
Computer for Data Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

149

SEEBER, ROBER T R., JR.: Associative Self-Sorting Memory. . . . . . . . . . . . .

179

SHOOMAN, WILLIAM:

Parallel Computing With Vertical Data. . . . . . . . . . . . .

III

SPIEGELTHAL, EDWIN S.: Redundancy Exploitation in the Computer
Solution of Double-Crostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STOUGHTON, P. N.; BENDER, R. R. ; DOODY, D. T.: A Description
of the IBM 7074 System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

161

WHITTAKER, J. L. and KAISER, V. A.: A Computer-Controlled Dynamic
Servo Test System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

255

WILLETT, H. M. and PETRICK, S. R.: A Method of Voice Communication
With a Digital Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

WOR TZMAN, DONALD: Use of a Digital/Analog Arithmetic
Unit Within a Digital Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

269

YOUNGER, D. H.; KIM, W. H. ; FREIMAN, C. V. ; MAYEDA, W.: On Iterative
Factorization in Network Analysis by Digital Computer. . . . . . . . . . . . . . .

241

LIST OF EXHIBITORS
American Telephone & Telegraph Co . .
Amp, Inc.
• .••..••
Ampex Data Products Co.
Anelex Corp. • • • . • •
Audio Devices, Inc.
Automatic Electric Co •.
Autonetics
The Bendix Corp. • • . .
Bryant Computer Products ••
Burroughs Corp. •
CBS Laboratories . • . • . . • • .
C-E-I-R, Inc. • . . • . .
C & K Components, Inc •.
C. P. Clare & Co.
C. P. Clare Transistor Corp.
Computer Control Co., Inc. •
Consolidated Electrodynamics Corp ••.
Control Data Corp. .
Di/An Controls, Inc • • .
Datamation • . • . • . •
Digital Equipment Corp.
The Digitan Co •••
Digitronics Corp ••
Dynacor, Inc • . • • • • • • .
Elco Corp.
Electronic Associates, Inc.
Engineered Electronics Co.
Epsco, Inc • • • • • • • •
Fairchild Semiconductor Corp.
Ferranti Electric. •
GPS Instrument Co., Inc.
General Ceramics
General Electric Co ••
Genesys
••••.•
Kenneth E. Hughes Co., Inc.
Hughes Semiconductor Division .•
International Business Machines Corp.
Laboratory For Electronics, Inc.
Lenkurt Electric Co., Inc.
Librascope, Inc.
Micro Switch • • •
Mnemotron Corp. • •
F. L. Moseley Co.
The National Cash Register Co.
Navigation Computer Corp.
Packard Bell Computer Corp.
Philco Corp. • • • • .
Photocircuits Corp.
Potter Instrument Co., Inc.
Radio Corporation of America
Ramo- Wooldridge
Reeves Soundcraft Corp.
Remington Rand Univac

New York, New York
Harrisburg, Pennsylvania
Redwood, City, California
Boston, Massachusetts
New York, New York
Northlake, Illinois
Downey, California
Los Angele s, California
Walled Lake, Michigan
Detroit, Michigan
Stamford, Connecticut
Arlington, Virginia
Newton, Massachusetts
Chicago, Illinois
Glen Head, L. I., New York
Framingham, Massachusetts
Pasadena, California
Minneapolis, Minnesota
Boston, Massachusetts
New York, New York .
Maynard, Massacp.usetts
Pasadena, California
Albertson, L. I., New York
Rockville, Maryland
Philadelphia, Pennsylvania
Long Branch, New Jersey
Santa Ana, California
Cambridge, Mas sachusetts
Mountain View, California
Hempstead, New York
Newton, Massachusetts
Keasbey, New Jersey
Johnson City, New York
Los Angeles, California
Union City, New Jersey
Newport Beach, California
New York, New York
Boston, Massachusetts
San Carlos, California
Glendale, California
Freeport, Illinois
Orangeburg, New York
Pasadena, California
Dayton, Ohio
Philadelphia, Pennsylvania
Los Angeles, California
Philadelphia, Pennsylvania
Glen Cove, New York
Plainview, New York
Camden and Somerville, New Jersey
Canoga Park, California
Danbury, Connecticut
New York, New York

LIST OF EXHIBITORS
Reese Engineering, Inc • • .
Royal McBee Corp.
Soroban Engineering, Inc.
Sprague Electric Co. . • • • .
Stromberg-Carlson Co.
Sylvania Electric Systems
Tally Register Corp • • . • •
Telemeter Magnetics, Inc.
Texas Instruments, Inc.
Union Switch & Signal. .
Uptime Corporation. . .
John Wiley & Sons, Inc.

(Cont.)

Philadelphia, Pennsylvania
Port Chester, New York
Melbourne, Florida
North Adams, Massachusetts
San Diego, California
Waltham, Massachusetts
Seattle, Washington
Culver City, California
Dallas, Texas
Pittsburgh, Pennsylvania
Denver, Colorado
New York, New York

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