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AFIPS
CONFERENCE
PROCEEDINGS
VOLUME 31
1967
FALL JOINT
COMPUTER
CONFERENCE
AFIPS
CONFERENCE
PROCEEDINGS
VOLUME 31
1967
FALL JOINT
COMPUTER
CONFERENCE
November 14 - 16, 1967
Anaheim, California
The ideas and opInIOns expressed herein are solely
t.hose of the authors and are not necessarily representative
of or endorsed by the 1967 Fall Joint Computer Conference
Committee or the American Federation of Information
Processing Societies.
Library of Congress Catalog Card Number 55-44701
AFIPS Press
210 Summit Avenue
Montvale, New Jersey 07645
© 1967 by the American Federation of Information Processing Societies, New York, N. Y. 10017. All rights
reserved. This book, or parts thereof, may not be reproduced in any form without permission of the publishers.
CONTENTS
HYBRID FACILITY PERFORMANCE IMPROVEMENTS
Multiprogramming for hybrid computation
The IADIC: A hybrid computing element
PHENO-A new concept of hybrid computing elements ....................... .
ADVANCED COMPUTER GENERATED GRAPHICS
Textile graphics applied to textile printing ................................... .
Holographic display of digital images ...................................... .
Half-tone perspective drawings by computer ................................. .
VISTA-Computed motion pictures for space research ......................... .
ADVANCES IN COMPUTER CIRCUITS
Current status of large scale integration technology ........... " ............... .
Large-scale integration from the user's point of view ......................... .
A family of linear integrated .circuits for data systems ....................... .
HYBRID COMPUTATION-SEVERAL APPLICATIONS
The effect of digital compensation for computation delay in a hybrid loop on
the roots of a simulated system . . ...................................... .
Hybrid Apollo docking simulation ... . .................................... .
Hybrid, six-degree-of-freedom, man-and-the-Ioop, simulation of a lifting reentry vehicle
Solution of integral equations by hybrid computation ......................... .
DISPLAY SYSTEMS AND EQUIPMENT
Graphic CRT terminals - Characteristics of commercially available equipment
How do we stand on the big board? ....................................... .
The CRT display subsystem of the IBM 1500 instructional system ............. .
Conic display generator using multiplying digital-analog decoders ............. .
IMPACT OF LSI ON FUTURE COMPUTER SYSTEMS
System architecture for la.rge-scale integration ............................... .
EXECUTIVE 'CONTROL PROGRAMS
Management of periodic operations in a real-time computation system
M. S. Fineberg
O. Serlin
J. 1. Crawford
M. J. Bodoia
W. Giloi
H. Sommer
J. R. Lourie
J. J. Lorenzo
L. B. Lesem
P. M. Hirsch
J. A. Jordan, Jr.
C. Wylie
G. Rommey
D. Evans
A. Erdahl
G. A. Chapman
J. J. Quann
R. L. Petritz
M. G. Smith
W. A. Notz
M. B. Rudin
R. L..O'Day
R. T.Jenkins
E. E. L. Mitchell
B. B. Johnson
S. S. Weiner
P. F. Bohn, Jr.
G. A. Bekey
R. Tomovic
J. C. Maloney
C. Machover
.M. L. Kesselman
R. H. Terlet
H. Blatt
H. R. Beelitz
S. Y. Levy
R. J. Linhardt
H. S. Miiller
H. Wyle
G. J. Burnett
A generalized supervisor for a time-shared operating system ...... ............. .
A real time executive system for manned spaceflight ....... ; ................. .
Executive programs for the LACONIQ time-shared retrieval monitor ........... .
An executive system for on-line programming on a small-scale system ........... .
INPUT /OUTPUT TECHNIQUES
Mass storage revisited· .. . . . . . . . . . . . . . . . . . . . . . ., .......................... .
High-speed themal printing ... ............................................ .
Solid state synchro-to-digital converter . . . . . . . . . . . .. . ........................ .
A new high-speed general purpose 110 with real-time computing capability ....... .
MANAGEMENT INFORMATION SYSTEMS
On designing generalized file records for management information systems ....... .
The planning network as a basis for resource allocation, cost planning
and project profitability assessment .... .................................. .
COMPUTING IN THEflUMANITIES AND SOCIAL SCIENCES - A STATUS
REPORT
Winged word.s: Varieties of computer applications to literature ............... .
Music and computing: The present situation ............................... .
Computer applications in archaeology ................ ................... .
Computer applications in political science . . . . . . . . . . . . . ...................... .
MEMORY SYSTEM TECHNOLOGY
The B8500 half-microsecond thin film memory
T. C. Wood
J. L. Johnstone
D. B. J. Bridges
L. V. Moberg
A. S. Hoagland
R. D. Joyce
S. Homa, Jr.
G. P. Hyatt
D. B. Cox, Jr.
K. Fertig
F. H. Benner
H. S, Woodgate
L. T. Milic
A. Forte
G. L. Cowgill
K. Janda
R. H. Jones
E. E. Bittman
Bit access problems in 2
~
D 2-wire memories ........................... .
Engineering design of a mass random access plated wire memory .......... . .... .
A new technique for removable media, read-only memories ................... .
Low power computer memory system ... : .................................. .
SOFTWARE FOR HARDWARE TYPES
Development of executive ro,utines, both hardware and software ................. .
System recovery from main frame errors ....... ............................ .
Language' directed computer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............ .
DIGITAL SIMULATION LANGUAGES AND SYSTEMS
An approach· to the simulation of time-sharing systems ....................... .
Hxperiments in software modeling ........................... ............. .
Design, thru simulation, of a multiple-access information system : .............. .
SODAS and a methodology for system design ............................... .
ACHIEVEMENTS IN MEDICAL DATA PROCESSING
Requirements for a shared data processing system for hospitals ................. .
Use of displays with packaged statistical programs ........................... .
MEDATA - A new concept in medical records management ................... .
P. A. Harding
M. W.·Rolund
C. F. Cho.ng
R. Mosenkis
D. K. Hanson
R. E. Chapman
M. J. Fisher
D. E. Brewer
S. Nissim
G. V. Podraza
A. Tonik
R. Armstrong
H. Conrad·
P.· Ferraiolo
P. Webb
W. M. McKeeman
N. R. Nielsen
D. Fox
J. ,L. Kessler
L. R. Glinka
R. M. Brush
A. J. Ungar
D. L. Parnas
J. A. Darringer
J. P. Bodkin
W. J. Dixon
C. Horton
T. M. Minckler
L. D. Cady
Requirements for a data processing system for hospital laboratories ", .......... .
An advanced computer system for medical research "."." ......... ,., ....... .
1. Etter
W. J. Sanders
G. Breitba:rd
D. Cummins
R. Flexer
K. Holtz
J. Miller
G. Wiederhold
POSITION PAPERS FOR MAIN FRAME MEMORY TECHNOLOGY - A DEBATE
Planar magnetic film , , , , , . , , ' , . . . . . . . . . . . . . . . . . . . . . . . . . . ................. .
Plated wire ......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .
Bipolar Semiconductor .. ................................... ............. .
Magnetics ... , ..... , ........... " .... , .. ,....... . ............... '....... .
Q.
G.
R.
R.
POSITION PAPERS FOR PANEL DISCUSSION: INFORMATION SERVICES AND
COMMUNICATIONS (COMPUTER UTILITIES)
Time-shared information systems: Market entry in search of a policy .. , ..... .
Communication Services-present and future ...... , ... , ... ,., ... , ........ .
Communication needs of remotely accessed- computer .... " .... , .. , ........ .
M. R. Irwin
W. B. Quirk
W. E. Simonson
NEW DEVELOPMENTS IN PROGRAMMING LANGUAGES AND
LANGUAGE PROCESSORS
Another look at data ' , ... , ... , . , , , ...... , , .... , ............. , ... , . , ...... .
Dataless programming ." .. , ...... , ..... , .... , ......... ,." .. , ............ .
PLAN IT - A flexible language designed for computer-human interaction .. , ... ',.,
A formal system for the specification of the syntax and translation
of computer languages .. , .. '.'". . .. ,., .... " .. " ... ".,", ....... , ... .
Generalized translation of programming languages .,.,', .......... , ...... " .. .
TECHNIQUES TO F ACILITATE ~ONVERSION TO NEW MACHINES
Computer change at the Westinghouse Defense and Space Center , ... ', ..... ',' ..
Machine-independence and third-generation computers ................... ,.,'.
POSITION PAPERS FOR PANEL DISCUSSION: THE IMPACT OF NEW
TECHNOLOGY ON THE ANALOG/HYBRID ART-I
Hybrid executive and problem control software ", .... ", .. ,' .......... , .... .
Diagnostic software for operation and maintenance of hybrid computers , .. ,., ... .
A large multi-console system for hybrid computations: software and operation ., ..
Simulation languages and the analog/hybrid field ... , .. , .. "., .. ,., ......... .
COMPUTER ORGANIZATION - I
Bulk core in a 360/67 time-sharing system. , ........ , , ' . , ........ , . , , ........
Modular computer design with picoprogrammed control .......... ,., ... , ......
Intercommunication of processors and memory .... , ........ , ...............
Stochastic computing elements and systems , .... "., .. , .. , ..... , ...... , ...
.
.
.
.
QUALITY PAPERS OF GENERAL INTEREST - I
AutoSACE - Automatic checkout for Poseidon
A practical method for comparing numerical integration techniques
Real-time spectral analysis on a small general - purpose computer . ,
Further advances in two-dimensional input-output by typewriter terminals .... , ...
THE ROLE OF THE GRAPHIC PROCESSOR IN PROGRAMMING SYSTEMS
A graphic tablet display console for use under time-sharing .. , .. , ..... ,., ..... .
Multi-function graphics for a large computer system .. ,",., ... , ... , ..... , ... .
Reactive displays: Improving man-machine graphical communication. , ...... , .... .
Graphic language translation with a language independent processor ., ..... " ...
W. Simpkins
A Fedde
S. Dunn
J. Petschauer
G. H. Mealy
R. M. Balzer
S. L. Feingold
J. J. Donovan
H. F. Ledgard
R. W. Jonas
W. B. Fritz
M. H. Halstead
E. Hartsfield
R. E. Lord
C. K. Bedient
J. C. Strauss
H. C. Lauer
J. G. Valassis
iW. W. Pirtle
W. J. Poppelbaum
J. W. Esch
C. A/uso
P. P. Shipley
G. W. Schultz
J. M. Colebank
A. G. Larson
R. C. Sin!(letol1
M. Kiner
F. Grossman
L. Gallenson
C. Christensen
E. Pinson
J. D. Joyce
M. J. Cianciolo
R. A. Morrison
COMPUTER ORGANIZATION - II
Design of fault-tolerant computers ......................................... .
Some relationships between failure detection probability and
computer system reliability ............................................. .
A distributed processing system for general purpose computing ................. .
QUALITY PAPERS OF GENERAL INTEREST - II
JOSS: 20,000 hours at the console: A statistical summary ..................... .
How to write software specifications ....................................... .
Observations on high-performance machines ................................. .
The Greenblatt chess program ............................................. .
A. A vizienis
H. Wyle
G. J. Burnett
G. J. Burnett
L. J. Koczela
R. A. Hokum
G. E. Bryan
P.· H. Hartman
D. H. Owens
D. N. Senzig
R. D. Greenblatt
D. E. Eastlake
S. D. Crocker
SPECIAL ACKNOWLEDGMENT
Data Processing Program for Technical Papers
To maintain good control over,the status of the three hundred technical papers submitted for this conference from receipt through distribution to reviewers, return from reviewers, final review and selection, and final disposition, a special
data processing program was written to keep track of status and issue timely status reportso Special acknowledgment is
made of the work of Mrs. Bernice Bjerke, who wrote the program, and to Aerospace Corporation for underwriting the
costs of writing, operating and documenting the system.
Multiprogramming for hybrid computation
by MARK S. FINEBERG and OMRI SERLIN
McDonnell Automation Company
Division of McDonnell Douglas Corporation
St. Louis, Missouri
gramming. are probably new, so it is worthwhile to
INTRODUCTION
establish a clear frame of reference at the outset.
A significant recent development in hybrid computation
is the increasing use of multiprogramming techniques
What is a time-critical hybrid job?
1 2 3
and multiprocessing hardware. • • To some extent this
As far as the digital computer is concerned, a timetrend is motivated by the development of multi-user
critical hybrid job simply represents certain loads on
systems in the pure digital field. However, the primary
the central processor (or other processors, if any),
justification for hybrid multiprogramming is economic.
memory and I/O facilities. It does not matter much
It is possible to show that, by sharing a large, powerful
whether the hybrid nature of the program is due to
central facility, the cost-per-computation can be rethe presence "in the loop" of analog computers, analog
duced by almost an order of mag~itude! as compared
hardware, or both. What does matter is that the timewith the alternative of using several smaller, whollycritical job must receive its share of the processor withcommitted computers. *
in a firm time limit. This time limit is shorter, by one
Associated with any multiprogramming system, hyor two orders of magnitude, than the response time in
brid or batch, are two fundamental requirements. There
other "real-time" systems such as airline reservations
must be a mechanism through which the available reor on-line banking. Another peculiarity of the timesources of the system (processor(s), working storage,
critical hybrid job is that it will rarely, if ever, tolerate
I/O) are allocated intelligently to satisfy users' needs
the sort of partial degradation ("overload") that is quite
while maintaining maximum throughput. Equally imacceptable, though undesirable, in a commercial "realportant is the need to guarantee the integrity of the systime" environment. If, for any reason, a time-critical
tem: users' programs must be protected !rom, and
hybriq job fails to get its quota ~f processor time even
independent of, each other, and the operatmg system
.once during a run-in one run the job may need the
must be immune to interference from a~y and ~ll u:;r.s. ~ processor hundreds of thousands of times-that run
The presence of time-critical tasks In the Job mix
must in most cases be abandoned or restarted.
complicates both the resource allocation problem and
There is another' important aspect in which the hythe task of safeguarding t~e syste~:s integr~ty. The
brid job differs from others; "page leafing" techniques
system must not only provide ~uffl~lent ser~lces,. b~t
cannot be applied to it, nor can it be relocated octhese services must be rendered m time, that IS, WIthIn
casionally in core, because the time frames within
a firm time limit. It is also necessary. to de~ect whenever
which it needs processor service are much too short
a job is attempting to use more than Its assigned share of
to accommodate either of these operations in the
resources, before this infringement affects other. users.
present state of the art.
The software and hardware features that permit successful resolution of these requirements in a time-critical
The goals of hybrid mult~progra~ming
.
environment, are the subject of this paper.
To be classified as a hybrId multIprogrammIn~ system, a computing complex must be capable of SimulA definition of hybrid multiprogramming
taneously servicing two or more time-critical hybrid
The concepts and terminology of hybrid multiprotasks in addition to pure digital batch processing. The
reas;n for insisting on a minimum of two hybrid jobs
*The debate between the proponents of these opposing viewis not purely semantic: the requirements imposed. on
points certainly deserves a wider recognition. For more dethe system configuration to enable it to run two timetailed discussions, see references 5, 6, and in particular, 7.
2
Fall Joint Computer Conference, 1967
critical tasks simultaneously are much more demanding
than those for servicing only one such job, whereas
the extension from two to any arbitrary number is
relatively straight forward.
The batch load may represent overflow from a pure
digital facility, or additional hybrid jobs in the digital
checkout phase, or it may be the primary load of the
system, the' hybrid jobs being occasional users only.
In any case, the most important criterion by which
the success of a hybrid multiprogramming system must
be measured is the degree to which each hybrid user
is made to feel that he has a committed computer at
his disposal. To maintain this illusion it is necessary to
guarantee protection and independence to all jobs. Protection requires that errors committed by one program
must not be allowed to interfere with the successful
running of programs other than the offending one. Independence implies that the coding, loading and checkout of one program need never be geared to the presence, absence or idiosyncrasies of other programs.
Almost equally important is the need to maintain
maximum throughput while servicing job mixes with
varying proportions of time-critical hybrid simulations,
other real-time tasks, and batch jobs. The economic
justification for hybrid multiprogramming depends to
a large extent on the ability of the system to service
I/O-bound batch jobs concurrently with the hybrid
jobs, which make relatively light use of peripheral equipment but represent a heavy load on the processor. Consequently the system cannot be regarded as a highly
successful one if the software features that are needed
to serve time-critical tasks significantly degrade the
throughput performance for all other jobs.
These are the ground rules; they need to be kept
in mind in th"e following discussion.
The central processor allocation problem
The proper allocation of the central processing unit
(CPU) in the presence of two or more time-critical
jobs is of prime importance in a hybrid multiprogramming system. These time-critical jobs, from the standpoint of the CPU, are characterized by three parameters (Figure 1):
1 Repetition Period, or Frame Time (Tf). This is
the period between two successive instants at which
the job demands CPU action.
2 Response Time, or Tolerance (Tr). This is the
period within which the equipment external to
the digital computer must have a "reply." Tolerance is measured from the instant of CPU request.
3 Compute Time (Tc). This is the amount of CPU
service, in terms of CPU-seconds, that the job
needs when it asks for the CPU.
A" 0
I
I:
A"O
_Tc. _ _
..
-r;.
If.
I
./
Figure I-The parameters of a hybrid job: T f is the repetition
period, usually marked by clock pulses which cause A~D
transfer. Tr is the response time; in this figure the digital
computer finishes its computation just in time to meet the
response-time constraint. Tc is the execution time" of the digital program.
Perhaps the most common hybrid job is the one for
which all three parameters are constant (or nearly so)
and Tr = Tf. Typically, an external "real time clock"
is used to generate pulses at intervals T f, (which are
hence also called "clock periods"). At the instants
marked by the real time clock pulses ("clock interrupts"), analog-to-digital (AD) conversion is initiated.
At the same instant, digital-to-analog (DA) data, which
is computed and stored in the DAC buffers during
the previous clock period, is also converted. To account for the fact that the DA data represents results
of computations based on conditions existing at the
previous clock interrupt, the digital program normally
includes a predictive algorithm that extrapolates the
DA data to the time at which the data" is actually
transferred to the analog domain. Because of this extrapolation, the "external world" (analog domain) is
insensitive to the actual time of execution of the digital
step, as long as all the required computation is completed prior to the next clock pulse.
A somewhat more complicated type of job is characterized by Tr .::
-Q.*
Figure 2-Standard quanitizing action of present analog
to digital converters
C ...
4:::>
-0
2q
Iq
pulse period, 6 T, equals q/Xmax.
t-
(3) R is chosen to make the integral of the feed-
back pulse,
q (where
B.
T
VT, equal to a quantum level,
CR
== Ih AT). Solving this relation-
ship for R yields the value for R or R == VT
qC
Merits
Before discussing the error sources associated with
the IADIC, some of its more obvious merits should
be brought to light. These are listed below:
(1) Integration is performed in real time and continuously in the analog domain.
(2) Integration is performed in parallel.
(3) Integration is performed with digital precision
(Le., resolution).
( 4) Once the integrator is placed in the operate
mode, it stays in operate mode for the duration
of the run. Thus no information is lost by going
through repeated "Hold" and "Reset" modes.
(5) The integrator output is not limited; therefore,
it can exceed the quantum level before, during,
or after a feedback pulse, and again no information is lost.
II.
Error analysis
Figure 3-.Quantizing action of the lADle
The following error sources will be considered in
this analysis:
( 1) An error due to the inaccuracy of the comparators which sense the quantum level q.
(2) An error due to an inaccuracy in the feedback
capacitor.
(3) An error in the reset pulse for the integrator.
( 4) An error due to the hardware limitations.
It will be shown that the first two errors are canceling or negligible. The significant error sources are
reset pulse inaccuracies and hardware limitations.
A.
Comparator error
The first error to be evaluated will be comparator
inaccuracy; th~ result of this error is illustrated in
Figure 6. The quantum level at which the comparator
should change state will be defined as q (see Figure
6), and e will be defined to be an error due to comparator inaccuracy. Therefore, the actual level at which
the comparator changes states is q
e. The effect
+
18
Fall Joint Computer Conference, 1967
+y
of this error is ·to cause a feedback pulse to be generated
at tl instead of to (the proper time), but the feedback
pulse will reduce X(t) by the correct value (q), and
an error of e will be left on the integrator. On the
next cycle (t2 to t3 ) , the comparator will trip at
q
e. This is a level change of q (not q
e) and
produces a new output pulse which is properly interpreted as a change of one quantum (q). Therefore.
the integral does contain an error due to the comparator inaccuracy; however, this error does not accumulate and represents only a small percentage of
one quantum. The decision to apply a reset pulse to
the integrator and not place the integrator in a reset
mode condition was predicated on minimizing the effects of this error and the next error to be discussed
(feedback capacitor error).
+
q o O.5000
~-~
SWITCtlNG
LOGIC
B.
-y
Figure 4-A scaled lADle
+
Feedback capacitor error
The next error 'source to be considered is an error
in the feedback capacitor. The output of an lADle
with a feedback capacitor error of E is shown in Figure
7. At any time. t, the integrator output can be determined from Figure 7 to be:
( 1) Output of integrator at t == output of integrator
at t l - 1 - integral of one reset pulse + integral
of input from t l - 1 to t_
Substituting actual parameters into equation (1)
yields:
v
T
t
(2) 6X(t) == q -
(l+E)q + (1+E)
r
J
Xdt.
t i -1
tn
t-
Now, if we let the integrator span the quantum
for this interval (i.e., 6X!== q), equation
2 becomes:
t==ti
Figure 5-Typical wave shape for a clock pulse
q ____+-______~----~t~i--I--------------~tl~---
,,I
,
I
11 x (tl
(I
+Elq
time-
Figure 6-Effect of comparator error
Figure 7-Effect of capacitor error
The IADIC: A Hybrid Computing Element
t
=q-
(3) q
f
(1+E)q + (I+E)
o
Xdt
which reduces to:
t,
(4)
J
Xdt
=q
t'-1
Although the feedback capacitor was in error
t,
by the factor E, the actual value of the
J
Xdt
t'-1
and the output of the IADIC spanned the quantum (q) in the interval t'-1 L. t L. t,. Because
the input of the IADIC (X) and the feedback
pulse are sensed by this integrator, it is obvious that the first count of the IADIC will have
an error due to E, but every. subsequent count
will.be independent of E. The decision to apply
a reset pulse to the integrator and not use a
reset mode was predicated on reducing the
effects of capacitor errors and comparator
error.
c.
Feedback pulse error
The next source of error to be considered is the
accuracy of the feedback pulse. For proper operation,
the integral of every pulse must be repeatable, accurately determinable, and equal to q (quantum level).
A single feedback pulse as illustrated in Figure 5 will
now be considered_
If the integral of this feedback pulse is defined --to
be q, then:
tn+T
qn
=
f
(feedback pulse) dt
= ;C
J
V dt
VT
= RC = q
where
R
C
V
= Feedback pulse resistor value
T
= Integrator capacitor value
= Reference voltage
= Pulse duration.
(see' Figure 1)
It has been shown that the capacitor value error
does not contribute significantly to the lADle error.
Errors in the reference voltage are insignificant because all measurements are, measured relative to the
same reference voltage. The two most significant errors
are the feedback resistor value and the pulse duration. State of the art summing resistors are adjustable
to within +0.0025 percent; however, the resistance
of the switch may be on the order of 50 to 100
19
ohms, which is a significant error if a lOOK feedback pulse resistor is used. Assuming that the fee4back resistor can be trimmed to account for switch
resistance, then the resistance error would be due
to stability of the switch resistance during a run.
The pulse duration is a function of the "turn on"
and "turn off" times of the switch. Again, if we assume
that the area of the pulse can be calibrated in some
fashion, then the actual "turn on" and "turn off" times
are not important, but the stability of these times
is important. We may now itemize the major contributors to pulse area errors by recognizing that there
are three (pulse generator, logic, switch) sources of
"turn on" and "turn off" time errors. These major
error contributors are as follows:
( 1) Switch resistance stability.
(2) Turn on time stability of the pulse generator.
(3) Turn on time stability of the logic circuits.
( 4) Turn on time stability of the switch_
(5) Turn off time stability of the pulse generator.
( 6 ) Turn off time stability of the logic circuits.
(7) Turn off time stability of the switch.
The authors were unable to obtain data on these
types of errors: however, the required values to obtain reasonable accuracy can be derived. If the lADle
is to be as accurate as a good analog integrator (1.0
JLf capacitor), then the feedback pulse area should be
accurate to ±0.025 percent. 9 Assuming that this is
a one sigma value and that an of the above error
sources are independent and equal, then each of the
seven error sources may contribute an error of
0.025/0
0.00945 percent to the pulse area.
Now assuming a lOOK ohm feedback pulse resistor
and a nominal pulse width of 10-4 second, the required accuracies of the seven error sources in order
to obtain 0.025 percent lADle accuracy are:
=
= 10
9.45 x 10-5
= 9.45 ohms.
(2) Turn on time stability of pulse generator, logic,
and switch = 10-4 x 9.45 x 10-5 = 9.45 nanoseconds.
(3) Turn off time stability of pulse generator, logic,
and switch = 10-4 x 9.45 X 10-5 = 9.45 nanoseconds.
Although the authors were unable to obtain stability
data on switch resistance, rise time, and decay time,
the required values above do not seem unreasonable
to the intuition when one considers nominal values
of 50 to 100 ohms for switch resistances and 20 to
40 nanoseconds for rise and decay times.
It should be noted that the expected accuracy of the
lADle will be different for monotonic and nonmonotonic functions. Since independent resistors. switches,
( 1) Switch resistance stability
5
X
20
Fall Joint Computer Conference, 1967
and perhaps logic circuits are used for positive and
negative pulses, the error for nonmonotonic functions
will be larger by approximately yz:
To summarize, the IADIC error is almost entirely
due to errors in the feedback pulse area and although
little or no data are available to determine this error,
a value of 0.025 percent appears to be attainable.
D. Hardware limitations
The decision to provide a resetting feedback pulse
and not to reset the mode of the IADIC (see Sections
A and B) when a quantum level is reached places
severe specifications on the hardware of the IADIC.
Because the IADIC may be in operate mode for a
long period of time, integrator drift will be detrimental to the accuracy of the IADIC. Therefore, the
hardware must be designed to ensure drift-free operation. Also, the hardware must be designed to obtain
a feedback pulse with a repeatability which will not
degrade the operation of the IADIC. Therefore. to
ensure proper operation, the following hardware requirements must be met:
( 1) Biases caused by any switch (especially switches S1 and S2 - Figure 1) in both the on and
off states must be miminized and balanced.
(2) The integrator must be designed to ensure that
the integrator rate limiting (due to maximum
amplifier current) does not distort the feedback pulse. This rate limiting will affect accuracy and will limit the minimum feedback pulse
duration. The amplifier must also be designed
to minimize drift.
(3) To obtain quantum equal to a small percentage ( 10-6 percent) of the variable either
the comparator levels must be set low or the
integrator gain must be high (or both). As the
integrator gain is increased, the probability of
obtaining drift-free operation will decrease.
Thus, the requirement to obtain drift-free operation will place a limitation on the maximum
integrator gain, and comparator setting accuracy
will place a limit on the minimum integrator
gain.
(4) Switches SI and S2 must have "turn on" and
"turn off" times repeatable to 9.45 nanoseconds. To obtain this repeatability the nominal
switch time should be on the order of 50 to 100
nanoseconds. Thus the current to be switched
must be limited, which places a restriction
on the minimum value of R and therefore the
minimum quantum level.
(5) DOW,6 Howe,7 and Driban8 have presented
discussions on the effect of capacitor dielectric
absorption on the accuracy of analog integrators. The circuit to compensate for dielectric
absorption developed by Driban8 could be incorporated into the design of the IADIC to
eliminate this dielectric absorption effect.
IV.
Analog to digital interface
Getting the count pulses from the IADIC into the
digital computer is an infinitesimal problem compared
to the normal method of analog to digital conversions
which requires: (1) analog sample and hold, (2) multiplexing, and (3) analog to digital conversion. The result of this conversion is a digital number which has
to be inputted to the digital computer.
Several schemes were conceived to accomplish the
task of getting the count pulses from the lADle into
the digital computer. The final method for imputting
the count pulses was to count and store these pulses in
a special buffer register. A bank of such registers would
be designed into the digital computer. This method excites the imagination because a direct line of communication is established between the analog and digital
computers and emphasizes the phrase "copartners in
computation. "
v.
CONCLUSION
Several papers1,2,3 have been written which tend to
validate the proposition that a hybrid computing element is the optimum device to interface an analog
computer with a digital computer, but the authors of
these papers are primarily concerned with digital to
analog communication utilizing the MDAC (Multiplying Digital to Analog Converter). The hybrid computing element (IADIC) introduced in this paper should
provide the flexibility and versatility to analog-todigital conversions that the MDAC provides to digital
analog conversion.
REFERENCES
2
3
4
T G HAGEN R TREIBER
Hybrid analog/digital techniques for signal processing
applications
AFIPS Conference Proceedings vol 28 pp 379-388
1966
R I RUBIN
Hybrid techniques for generation of arbitrary functions
SIMULATION vol 7 no 6 pp 293-308, 1967
W E CHAPELLE
Hybrid technique for analog function generation
AFIPS Conference Proceedings vol 23 pp 213-227
1963
R J JARRETT
An analog R. C. integrator with a digital output
Proceedings of the National Electronics Conference
vol XVI pp 611-618 1961
The IADIC: A Hybrid Computing Element
5
A K SUSSKIND
Notes on analog-digital conversion techniques
MIT Technology Press 1957
6 PC DOW
An analysis of certain errors in electron differential
analyzers II-capacitor dielectric absorption
IRE Trans. on Elect. Compo vol EC-7 pp 17-22
March 1968
7 R M HOWE
Design fundamentals of analog computers components
8
9
21
D. Van Nostrand Company Inc Princeton New Jersey
1st ed chap 2 pp 37-41 1961
S DRIBAN
Spurious damping in analog computers
Masters Thesis Drexel Institute of Technology
pp 49-55 June 1967
G A KORN T M KORN
Electronic analog and hybrid computers
McGraw-Hill Book Company New York chap 3
pp 110 1964
PHENO-A new concept of hybrid computing elements
by WOLFGANG GILOI
and HEINZ SOMMER
Technical University
Berlin, Germany
INTRODUCTION
PHENOs are based on the well-known fact that a
digital-to-analog converter with variable reference
(MDAC) can produce the product of an analog and a
digital variable. 1 While for multiplication and division
this principle can be used directly, it has to be modified
for function generation. In order to obtain a system of
computing elements in which any input or output variable can exist in analog or digital form, optionally,
D ACs and ADCs (analog-to-digital converters) are
combined. The straight-line-segment approximation of
arbitrary functions is done by splitting the (digital)
argument of the function in two parts. The first group
of r bits defines the nearest preceding breakpoint, while
the second group of (n-r) bits is used for linear interpolation (n being the digital word-length). In a second
method of function generation, which is particularly
suited for multivariable functions, digital table look-up
is combined with analog interpolation. On the base of
PHENOs, this procedure provides minimum table lookup execution time and avoids stability problems.
The ADCs are key elements with respect to operation speed. Here, adaptive continuous converters, using
the up-down-counter principle, show best performance.
Constant band width/accuracy ratio is obtained by
automatically adapted register length, i.e. for input increments greater than the least significant bit this bit is
dropped, resulting in a doubled step size, etc. The conversion rate is further increased by using a subranging
technique.
At the time being, the ADCs operate with 6 MC
dock frequency. Therewith, a continuous ADC can
track a 100 cps sine-wave with 0.01 % accuracy and 1
kc sine-wave with 0.1 % accuracy. Static errors of
multiplication, division and function break points are
less than. 0.01 % .
23
PHENO-equipped analog computers will essentially
not be more expensive than high-precision analog computers containing very precise time-division or quartersquare multipliers, but they will produce a much better
bandwidth/ accuracy ratio. Additionally, they require
no expensive interface when being linked with digital
computers, since the variables are partly existing in
digital form, anyhow. On the other side, PHENOs can
be used to build inexpensive, small-scale, special-purpose computers for military and process control application. For this, additional elements have been developed, for example, units which the the combination of PHENOs' with DDA-elements possible
(DDA == digital differential analyzer). As opposite
to usual analog computing elements, PHENOs
permit miniaturization and operation under difficult environmental conditions.
Principle of PHENO
In a ladder network according to Figure 1 the shortcircuit transfer conductance is2
1
n
:£
2R
--,
(1)
k==l
o
Sk ==
(switch connected with ground)
1 (switch connected with ell)
and, therefore, .proportional to the digital number
d* == dnd n-t . . . d2d1 stored in the register. Connecting
the output terminals 2-2' with the input of an operational amplifier with feedback resistor Rr == R results
in an amplifier output voltage, which is related to the
input voltage by
e.. == ell • d*
(2)
By exchanging the input and output network of the
24
Fall Joint Computer Conference, 1967
er (FGDAC) may operate with variable refrence, ti
performs the operation
amplifier we have the inverse relation
ell
eo = d*
(3 )
I
------=- ~io
I '
m
I
~ls.
2R
2R
R
2R
R
2R
= el • f ( d * )
(5 )
If the output of one FGDAC generating the function
fl (x*) is used as reference of a second FGDAC generating the function f2(Y*), we can obtain the expression
d*------------------_
I n-stage re~ister
I
I
i
I
eo
___
R
2
~
R
which, in many cases, gives a good approximation of
functions of two variables f(x,y).
Using a FGDAC as part of an ADC gives the operation
(7)
Figure I-Principle of Df A-conversion
Hence, we obtain in the first case the product of an
analog and a digital variable, while in the second case
we get the quotient of both variables. In both cases
the results are given in analog form. In the following,
such a multiplying digital-to-analog converter will be
called 'MDAC.'
Most analog-to-digital converters (ADC) are based
on the principle that by a certain strategy the register
setting d* of a digital-to-analog converter (DAC) has
to be found in such a way that the output of the DAC
equals the input voltage et2 that has to be converted.
When using a MDAC with reference voltage ell, we can
obtain a register setting
el2
d* == K - -
eo = el [fl(x*) • f2(y*)+a1f1 (x*)+a2f2(Y*)] , (6)
(4)
i.e., d* gives, in digital form, the result of dividing two
analog variables.
It is important to have an element for arbitrary
function generation as for multiplication and division.
In an analog computer (as well as in digital table lookup programs) the most simple solution of that problem
is a straight-line-segment approximation of the desired
function. This kind of function generation can be obtained for functions of one ( digital) variable by a
modified digital-to-analog converter, in which the argument of the fun:tion is split into two parts. The first
r bits of the digital input of length n define (in binary
code) the abscissa at the nearest breakpoint (the function being approximated, for example, by 2r straightline segments of equal length), while the remaining
(n-r) bits are used for linear interpolation within the
actual segment. For that purpose, this second part of the
digital input is fed to a MDAC which has the function
increment l::etween the two actual breakpoints to reference. Of course, it is just a matter of coding to obtain any other distribution of the breakpoint abscissa.
Since this function generating digital-to-analog convert-
(f-l being the inverse of the function f (d *) which is
generated by the FGDAC).
By com")ining the operations according to eqs. (2)
through (7) (that means combining digital-to-analog
and analog-to-digital conversions) multiplication, division, function generation or combinations of these
operations can be arbitrarily performed with analog
and/ or digital inputs and outputs.
The purpose of this new technique is to exceed the
accuracy limits of usual nonlinear analog computing
elements. Since any operation of the PHENOs is based
on conversion techniques, maximum static accuracy is
that of high-precision converters. An analog accuracy
of 0.01 % (single-scale) and a digital resolution of 14
bits plus sign can be achieved. Hence, the PHENOs
are well-matched to the static precision of best linear
analog computing elements.
The dynamic errors depend on the conversion speed
of MDACs and ADCs. The MDACs are not critical,
because all switches in Figure 1 are set simultaneously.
Even in the more critical case of variable reference
switches, their settling time (to an error smaller than
0.01 %) can be kept in the range of 1 ILs, approximately.
The conversion time of a successive-approximation
ADC is a mUltiple of that, because complete parallelism
in the ADC operation is too expensive. Even when
using an expensive subranging procedure, a conversion
rate of 200,000 per se::ond is the highest that could
be achieved till now. This extremely fast successiveapproximation ADC would lead to the same phase
error as in linear· analog elements with 60 kc 3 dBfrequency. The successive-approximation ADC starts
each conversion from zero; i.e. it does not matter
whether or not the input signals are continuous. Because the PHENOs are assumed to operate continuously, however, we can take advantage from this fact
in order to increase conversion speed. An ADC which
operates strictly on continuous signals is called a 'continuous converter.'
PHENO-A New Concept of Hybrid Computing Elements
The most simple principle for continuous converters
is that of using up-down-counters. Here, dynamic errors
are almost negligible as long as the condition holds
erer
d
-
dt
(el)
< - - . fc
(8)
2n
(n being the digital word length, fc the counter clock
frequency and 2- n e erer the step size).
When the input voltage slope is greater than the
counter clock-frequency multiplied by the magnitude
of the counter increment, the ADC is 'overrated,'
resulting in a time-increasing error. fc depends on the
settling time required by the comparator and the analog
switches. It is a function of the magnitude of the least
significant increment.
It is difficult to find appropriate semiconductors for
building analog switches with variable reference and
10-4 -accuracy (circuits with alloy· chopper-transistors
with high V BE reverse voltage or circuits with field effect
transistors have a relatively poor bandwidth). On the
other hand very fast variable reference switches with
10-3-accuracy are easy to implement. Therefore, it is
of advantage to use a subranging technique by dividing
the entire input signal range into k equidistant subranges. The actual sub range in which the input is falling
is then expanded by a factor k (e.f., k == 16), so that
a conversion accuracy of kel 0-4 is solely required. When
the input crosses a boundary between two adjacent subranges the next one. has to be selected. In this paper we
will show a special technique by which that can be done
within one clock interval. Of course, the comparator
and the analog switches can now work much faster since
they have to settle only to an error less than k.10-4.
An other important measure in order to increase
conversion speed is in using an automatically adapted
register length; i.e., when the converter is going to be
overrated n will be diminished. For example, when an
actual input increment exceeds the magnitude of the
least significant bit, this bit is dropped, resulting in a
doubled step size, etc. By this means a constant bandwidth/ accuracy ratio is obtained.
As we shall show in this paper, by using this advanced technique we designed PHENOs which have an
accuracy-'_andwidth performance suiting the most precise linear analog computing elements and exceeding
the nonlinear ones.
Realization of the AD-continuous converter
Subranging
PHENOs operate in a ± 10 V-range. In order to be
able to use fast current-switches of 0.1 % accuracy,
we divide the ± 10 V-range into 16 subranges. Therefore, each sub range covers 1,25 Volts of the input
25
voltage. A schematic block diagram of a subranging
converter ~s shown in Figure 2. In the subranging techniques one has to select, of all subranges, the one that
includes the input voltage, e.g., by subtracting all lower
subranges from the input signal. By the same operational amplifier the resulting difference is multiplied by
the factor 8. Thus, the following subrange-ADC has to
operate with the reduced accuracy of 0.1 %. Subtraction,
subrange-selecting D / A-conversion, and amplifying
must be executed with an accuracy of 0.01 % (with
respect to the input). One subrange contains 1024 steps,
which is the range of operations of the fast subrangeADC. As long as the input remains within a specific
subrange, it operates with the 6 mc clock frequency.
When running into the adjacent subrange, a new subrange must be provided with an accuracy of 0.01 %.
This operation takes much more time (some microseconds) than the clock rate of the subranging converter (0.16 fLs) gives. Therefore, considerable errors
could arise due to the slowly operating 0.01 %-accurate elements. The following section outlines measures
that eliminate these errors, although slowly operating
elements are used.
Figure 2-Schematic block diagram of a traditional ADC
with wbrang!ng
Principles of subranging continuous-converters
When the input signal is crossing the boundary of
one subrange, the converter has to switch over to the
adjacent one. If the next sub range is prepared by a
second subrange-selecting DAC, the required signal for
the sutranged-ADC is available at any instant.
For a special reason (which shall be explained later),
the subrange-ADC converts positive and negative input
voltages. As long as the voltage is positive the next
higher subrange is prepared. If it is negative, the adjacent lower subrange will be prepared.
Preparing of a new subrange is started when the input of the subrange-ADC crosses zero. Therefore, elements with 0.01 %-accuracy have a time interval available for reaching the steady state which is 1024 times
the clock-interval of the subrange-ADC. Hence, the
subrange-ADC operates over the full scale within subranges which are always in a steady-state, so that no
26
Fall Joint Computer Conference, 1967
additional errors can occur. The price for this IS In
providing a second subrange-selecting DAC. Figure 3
shows the block diagram of the complete continuous
converter.
The subrange-selecting DAC 'SSDAC l' is active,
when even-numbered subranges are used, and 'SSDAC
II' operates on odd-numbered ones. Whether or not
a subrange is even-numbered is determined by flipflop
FF 1, which switches the subrange-ADC to SSDAC I
or SSDAC II. Furthermore, FF 1 marks which system
is actually used and which one is in the preparing
state. Usually, subranging ADCs, which are known
from the literature, 2 have only one sub range-selecting
DAC. When the input reaches the upper boundary of
a subrange, the subrange-selecting DAC is set to the
next higher subrange, and the ADC is reset to the
lower boundary of that subrange. If the input voltage
decreases or if there is an overflow in the DAC-system,
the ADC must be switched back to the subrange just
left. This may cause an instable operation, in cases when
the input fluctuates around a subrange boundary.
This can be avoided by expanding the range of operation o~ the subrange-ADC to negative values. Nevertheless, the converter is set back to zero (and not to the
lower boundary) when the input crosses the upper
boundary. If the input is now decreasing, after just
having left a subrange, the converter can use the negative part of the new range. Due to this principle the
converter will always remain in the new subrange after
a subrange-change and, therefore, stability at the
transition-levels is secured.
If fC}r example the subrange-ADC in Figure 4 reaches the value 16, it is reset to zero and 16 is added
to the register of the subrange-selecting DAC. If the
input decreases immediately after a subrange-change,
the subrange-ADC continues to operate in the new subrange. Two special outputs ("Ae" and "i") are provided for a particular application described in section
4. Note that with "6,e" we have in analog form the
equivalent of the last 10 bits of the digital output, while
at terminal "i" we shall get an impulse every time the
input ell is going to cross a subrange boundary.
Automatic step size adaption of the subrange-ADC
Formula 8 of chapter 1 reads:
d
- (el )
eref
< - - . fe
dt
2n
In order to reduce the time-increasing errors of the
0.01- accuracy
0.1- accuracy
register output
~e
r---~brQnge-ADC - - - - ,
I
I
I
I
eilO"--------I
~--~~---4--~~~v-~~
I
I
I
I
I
I
,.
I
I
I
I
eil~--:-~~
I
I
I
I
counter
_________ JI
SSDAC - register
selector
"""-----4
- --4 bit-- --output
I
"step-size"
digit.
boundary
detector
register
-----------------------------------------------~------------------.d·
Figure 3-Block diagram of a PHENO-ADC
PHENO-A New Concept of Hybrid Computing Elements
usual up-down-counter ADC we can either choose a
higher clock frequency or a larger step size.
The transient function of most analog switches are
almost exponential. Thus, the transient time for 0.0 1 %
accuracy is equal to 9 time-constants. and the transient time for 0.1 % -accuracy is equal to 5 time-constants. By doubling the clock-frequency the error would
increase by the factor 100. On the other hand, errors
increase only linearily with the step size, so that a con.stant error bandwidth ratio can be obtained.
ereC
The step size 2--;;-- of a counter-ADC depends on
the magnitude of the reference voltage and the digital
word length (register length) n. The static error of
PHENO is less than tmV. Assuming a lOY-reference
voltage, we obtain a relative error of 0.01 %. With
decreasing reference voltage the step size decreases,
too. While· errors of the comparators and switches are
constant, the maximal slope of the input voltage is
reduced.
By an automatically adapted register-length the required step size can be matched to the slope of the
input-voltage. The criteria for changing the step size
can be obtained by measuring the summing-junction
offset of the subrange-ADC. Traditional counter-ADCs
detect whether the summing-junction has a positive or
negative offset, and thus the counter is set in the 'up' or
'down' mode. Additionally, in our case the amplitude
of the summing-junction offset is measured by two additional comparators. According to the used step size,
the threshold voltages of these comparators have to be
varied. A converter-'overrating' may occur under different circumstances. E.g.: if there is a positive step
and
(i) a positive overflow, the step size has to be halved
(ii) no overflow, the stepsize has to be retained
(iii) a negative overflow, the step size has to be
doubled.
For negative steps similar considerations will hold .
Hence, the sign of the last step has to be stored,
and, in order to decide how to change the step size,
that information has to be combined logically with the
outputs of the overrate-detecting comparators.
Our AD-continuous converter has 8 possible step
sizes, starting with t mV. The other step sizes are given
by successive doubling. The actual step size is stored
in a 3-flipflop counter, which determine the register
length and the threshold of the comparators.
Implementation of PHENOS
The elements
In table I existing standard types of PHENOs are
listed. In addition to elements for AD- and DA- conversion, multiplication and division as well as function
generation, special elements such as incrementing
ADCs and accumulating DACs have been developed.
They give the possibility of combining PHENOs with
digital differential analyzer elements (DDAs). By combining them, new systems can be created, e.g., hybrid
integrators, etc.
t
-32
NOTE:
27
Figure 4-Scheme of sub range-transition
The numbers at the arrows indicate the range of
operation of the various subranges, the encircled
numbers give the setting of the actual SSDAC
28
Fall Joint Computer Conference, 1967
It should be emphasized that the possibility of "slaving" several elements also exists. For example, one
ADC can be connected with two or more MDACs or
FGDACs, giving the possibility of" "multichannel"
multiplication or function generation.
,
---,-I
I
Analog switches and variable function
generator circuitry
The operating speed of MDACs and ADCs depends
mainly on the transient time of the analog switches. In
our subranging continuous converter two types of analog switches are required: (i) a very fast one with
0.1 % -accuracy and (ii) a very accurate switch
(0.01 %), which is uncritical in terms of speed.
Newly-developed, inexpensive variable reference current switches are meeting these requirements. The transient time of the simple, 0.1 % -accurate switch plus
comparator (/LA 710) is 150 ns. The transient time of
0.01 %-accurate switch is about 500 ns.
The principle of function generation has been ex.plained in section 1. The most significant r bits of a
digital number with length n define the breakpoints.
The remaining (n-r) bits are used for linear interpolation.
The function-ordinates at the breakpoints are adjusted by potentiometers, which are sources with inductive output impedance. The switches must provide
that the currents flowing in the potentiometers are not
affected ty switching (Figure 5).
As Figure 5 shows, the settings of potentiometers
Pt. . . P r are not affe~ting one another. A-::cording to
the digital number, a decoding matrix causes one pair
of FETs, e.g., F t and F't, to be switched on and the
transistors TI and T2 to be switched off. All other
switches are used the opposite way. If Fl is switched on,
the voltage -VI appears at the output of amplifier
At. At the same time a current (proportional to the
difference (V2 - V t » flows through the FET'2, resulting in the voltage -(V2 - Vt) at the output of amplifier
A 2. -(V2 - Vt) acts as reference voltage of a MDAC
which linearily interpolates between breakpoints.
The FET-switches 1 through r operate with an accuracy of 0.01 %; their settling time for that accuracy
is atout 2/Ls. By inserting them in the feedback loop of
an operational amplifier, errors due to their temperature-sensitive on-resistance are avoided. The FETs l'
through r' switch the difference voltages of two adjacent breakpoints to the summing-junction of the amplifier A2. Here, the temperature-variable on-resistances
of the FETs are part of the resistors which define the
slopes of the straight-line segments. This is possible
since the maximum function increments between adjacent breakpoints are limited and only small error
propagation can occur.
I
I
leo
I
I
I
IL- _
I
_ _ _ _ _ _ .J
interpolating MDAC
Figure 5-Circuitry of a FGDAC (schematic)
The transistors T t through Tr are in on-state when
the related FET-switches are switched off. By that
measure, discontinuities of the currents flowing in the
potentiometers are avoided.
Incrementizer for linking hybrid and DDA
sub-systems
DDA-elements are processing increments of digitally represented variables. Generally, these increments
1, -1, or 0, corresponding to
only have the values
the least-significant bit of the digital word.
When applying that DDA-technique to analog signals, increments smaller than the digital aperture may
occur if the rate of change of the analog signal is too
small (compared with the clock interval). Thus, the
DDA may not give any response at all, though the
analog signal can slowly vary over the entire scale.
This difficulty can be avoided by accumulating consecutive increments and continuing that until the sum
is going to exceed the threshold which corresponds to
the least-significant bit. In our counting-:ADC this procedure is performed by comparing the sum of all preceding output increments with the actual input. Thus,
a counting-ADC can be used for linking analog and
DDA-subsystems.
+
PHENO-A New Concept of Hybrid Computing Elements
Hybrid integrators
Analog computers perform integration with .respect
to time. The generalized integration of arbitrary functions can be performed with a hybrid integrator. For
this purpose integration is approximated by Euler's
formula
x
z(x) == K S ydx == Zn(X)
Xo
x
x(t)
y
yet)
(9)
n
Zn(X)
K °
L
Yk o 6 xk, 6Xk == +1 or -1 (10)
k==o
Referring to Figure 6, the hybrid integrator consists of two ADCs and one DAC. ADC I produces
the increments 1 oder -1 (with respect to the clock
period T*l). The analog switches SI and ~ generate
the product (Yn6xn) which is added to the sum
29
as part of a combined hybrid computer system offer
particular possibilities which do not exist in conventional hybrid systems.
As an example of great practical importance, we consider the problem of multivariable function generation.
On the base of PHENOs, the well-known digital
table look-up routine can be combined in a simple
way with an analog interpolation, resulting in minimum
execution time. Because of a direct analog path between input and output signals, the stability problems
of pure digital function generation are avoided.
The generation of arbitrary functions is executed by
straight-line-segment approximation. For example, in
the case of a function of one variable we have the interpolation formula
+
= fl
n-l
K·
L
+ mi (x -
for XI
Yk6xk
k==o
obtained before. The result is converted by ADC II
which works with a higher clock rate. The output of
ADC II is stored in DAC I (in digital form) and its
analog equivalent is fed back to summer S. The resulting Zn(X) is available in digital as well as in analog
form.
L.
XI) ,
X L. XI+ 1 ; fl == f(xl)
(13)
The breakpoint values fl (i == 0,1,2 ... ,B-1), B being the total number of breakpoints (e.g., B==24==16,)
and the average slopes ml are stored in the memory of
the digital computer. The necessary mUltiplication of
(mi and X-Xi) now can be performed by a MDAC.
Note that now, contrary to the FGDAC which was
described in section 3.2, the slope is given in digital
form while the function argument is analog. Hence,
for the digital table look-up routine, the argument x
first of all has to be converted by an ADC.
Because of the special subrange technique used in
the PHENO-ADCs, the last 10 bits of the 14-bit output word are available in analog form . .If the remaining 4 most-significant bits are used in order to define
the function breakpoint (corresponding with B == 24
== 16), the last 10 bits or their analog equivalence,
respectively, are identical to the increment (x - XI).
Thus, we can use the very simple setup outlined in
Figure 7.
Figure 6-Hybrid integrator, programmed with PHENOs
NOTE: Asterisks denote digital variables
PHENOS in hybrid computer systems
For being linked with a digital computer, PHENOequipped analog computers only require an inexpensive control interface but no data interface. Since all
required analog-to-digital conversions are simultaneously performed by independent continuius converters, no
errors due to the time shift of analog multiplexing or
to the skewing time of sample-and-hold circuits can
o:::cur.4 Moreover, PHENO-equipped analog computers
Figure 7-Hybrid generation of functions of one variable
on the base of PHENOs
Here, the function argument X is fed into a PHENOADC and converted in digital form. Simultaneously,
30
Fall Joint Computer Conference, 1967
the ADC gives out the analog signal (x - XI) which
is fed into a MDAC in order to build the product
m*. (x - XI).
The digital representation x* of the function argument is transferred into the digital computer, but only
the 4 most significant bits are required for the table
lpok-up routine. By appropriate indexing these four
bits can directly be used to give the (relative) addresses
of the memory cells in which the corresponding breakpoint abscissa f. and the average slopes m *. can be
found. 3 Therefore, the digital program has to execute
the following routine:
(i) Load x* into accumulator;
(ii) Shift x* to the right so that the most significant
4 bits give the relative address of the memory
cell in which f* I is stored;
(iii) Load f*J into DAC;
(iv) Add B to the address. This modification gives
the relative address of the memory cell in which
m *I is stored.
(v) Load m*1 into MDAC.
Now, for any breakpoint of the two-dimentional grid
the values f*J,k' mXJ*, and mYk * have to be stored. An appropriate modification of the above outlined special
indexing technique leads to a very efficient table lookup routine by which those values can be loaded into
the DAC and the two MDACs (requiring now 38 /Ls
on the SDS 930). Note that only one additional pair
of ADC and MDAC is necessary for each additional
input variable.
(In the case of the digital computer SDS 930 for
which the above routine was programmed, the entire
instruction sequence requires about 16 mem9ry cycles
== 28 /Ls).
That digital table look-up routine is not necessarily
part of the intrinsic hybrid computation. Since the ADC
provides an interrupt signal ("i") when the input 'x is
going to cross a sub range boundary (which is identical
with crossing a function breakpoint), the hybrid computation can be interrupted. While the analog computer
remains in the 'hold' mode, the actual values fl* and ml*
can be replaced by f*l+l and m*l+l, and then, the hybrid
computation may continue. During the real-time operation of the combined system there is an analog path
between input and output of the function generation
procedure. Hence, the stability problems are avoided
which can arise when a digital computer is inserted in
analog 100ps.4
We have to emphasize that this procedure is similar
to the one previously proposed by A. I. Rubin. 5 But
when PHENOs exist, our approach is simpler and
less expensive.
The above principle .can easily be expanded to the
task of generating functions of more than one variable. If, for example, a function of two variables f(x,y)
has to be generated, we use the interpolation formula *
PHENO offers a particular flexibility in building
precise, inexpensive, miniaturized, hybrid special purpose computers. If only 'static' operations have to be
performed (su~h as summing and subtraction, multiplication and division, function generation), a combination of PHENOs and analog summing amplifiers will
be sufficient. The accuracy is strictly dependent on resistors, electronic switches, and operational amplifiers.
Since all these components can be realized with small
temperature drift, operation under extreme environmental conditions is possible. A high degree of integration and, therewith, miniaturization can be obtained.
In the case of 'dynamic' problems, i.e., problems
which include integration, either the hybrid integrator
of section 3.4 may be used or a combination of PHENOs with DDA-elements. The first approach is advisable if only a few integrations are required. For the
second approach we shall give a typical example.
In case of a special purpose computer for solving a
proportional navigation problem, the solution of the
following equations is required
(15)
dl'M == K • dI>A-integrator
FGI>AC
AJ)C
counter
IdYM
DI>A-integrator
-u2dYM
I>I>A-integrator
uldYM
V Mdul
u1dVM I>I>A-integrator
V Mdu2
u 2 dVM I>I>A-integrator
accumulating-I>AC
IdVy
accum ulating-I> AC
ldVx
• dO"
Ko • f(e*)
K· 1
+
+
ADC
T G HAGAN
AMBILOG computers: hybrid machines for measurementsystem calculation tasks
Proc. 17th Annual ISA conf New York Oct 1962
2 DIGITAL EQUIPMENT CORPORATION
A nalogl digital conversion handbook
Maynard Massachusetts 1964
3 G SCHWEIZER H SEELMANN
The application of hybrid simulation for VTOL-aircraft
and certain reentry-problems
Proc. 4th Internat. Analogue Computation Meetings
Brighton 1964 pp. 18-29
4 W GILOI
Error-corrected operation of hybrid computer systems
~
ei2
=ei/
symbol
ei2~d'
ejl
FGADC
d k=f(ei2 ) ej2
ej/
A
G d
~.
ej/
MDAC
Figure 9 shows the resulting computer block diagram on the base of PH ENOs according to Table 1
and I>I>A-components.
REFERENCES
d
31
d
eo =e·l·d~
I
A·
eo
.~
ej/
DAC
ejJ
e=~
d
d.~e
A
0
ei/
FGDAC
d.~e
A
eo=eilof(d' .
0
ei/
Accumulat.DAC
n
.•
eo =ejr r.1dk /Jd
K='
Table I
~ eo
A.L
ei/
32
Fall Joint Computer Conference, 1967
d6'
counter
#4
u.
#5
Figure 9-Block diagram of a special purpose computer,
solving eqs. (13)-(19). The computer consists
of PHENOs and DDA-elements
Textile graphics applied to textile printing
byJANICE R. LOURIE andJOHN J. LORENZO
International Business Machines Corporation
New York, New York
INTRODUCTION
Description of textile graphics
Textile Graphics is a computer-aided technique l for
developing a textile design and textile patterning
mechanism information from an artist's drawing. The
computer is operated by a textile designer-technician who understands the particular textile machinery for which he is adapting the original drawing.
The designer-technician inputs the original drawing
by a combination of graphical input devices; tracing
on an on-line digitizing tablet, drawing free-hand with
light-pen on the screen of the IBM 2250 and manipulating the design with function keys.
After the original design is in core it is developed
into the information to control the patterning mechanism of a specific kind of textile machinery. For
example, a design to be woven must represent each
interlacing of warp and weft; a design to be knitted
must represent each stitch of the knitted mesh; and
a design to be printed must represent the areas of each
color as separate images.
The development of this information is done according to both structural and aesthetic rules. The designer-technician interacts with the computer using
the function keys, light-pen, 2250 and photographic
plotter.
When the design control information is developed,
it may be outputted under function key control.
The form of the output is commensurate with a specific patterning mechanism. For example, for a Jacquard loom which is controlled by punched cards,
Textile Graphics output is the pattern of the holes in
these cards; for a Raschel machine which is controlled by a chain of cam-links, Textile Graphics output is a map of the heights of the successive links;
and for textile printing machines which are controlled by etched copper rollers or silk screens, Textile Graphics output is a set of color-separated films.
Previous applications of textile graphics
The first application of Textile Graphics was to
jacquard weaving. 1 The Jacquard loom is controlled
by punched cards and the designs which it produces
may be described in computer terms as rectangular
(mxn) binary matrices with a "1" in any position. The
size of m and n may vary from "one" to several thousand.
This direct analogy between the representation of
computer data and textile design information was
noted in a description of Charles 8abbage's Analytical Engine. It said that his "computer" weaves algebraic equations like a Jacquard loom weaves flowers. It is this analogy which motivated the original
work in Textile Graphics. 2
Textile Graphics was then applied to developing
design control information for lace which is manufactured on a Raschel machine. Although the Raschel machine is a warp knitting machine and not a
weaving machine like the Jacquard loom, its design
control information is currently developed on a grid
paper analogous to the point paper described in Ref. 1.
This practice permitted the natural extension of Textile Graphics to lace and other knitted fabric design.
A new application of textile graphics
This paper describes the application of Textile
Graphics to textile printing. The application to textile printing differs from applications to other forms
of textile design because the printed textile design is
applied after the textile is fabricated.
Since the patterning mechanism is independent of
the fabric forming mechanism, there is no need to
represent the design on a grid paper, (which for other
textiles is translated into row by row, design forming
information). However, we will show that for a large
class of designs, the color-separated images which
printed textile designs require can be more efficiently
produced using Textile Graphics.
33
34
Fall Joint Computer Conference, 1967
First, the major current methods of producing
printed textile designs are presented. Then, the types
of designs are analyzed and reclassified to give more
insight into new methods of obtaining color separations.
We combine different parts of current methods with
Textile Graphics to expedite the production of the
design control information (color separations) for
approximately half of printed textile designs. In
addition, a new category of printed textiles, whose
color separations are easily generated using Textile
Graphics, is exhibited.
Current method of preparing designsfor
textile printing
Description of textile printing
There are two major methods of printing designs on
textiles. One of these, a roller method, uses etched
copper rollers to apply the paint directly to the fabric.
The area to be printed is etched in intaglio and the
remaining portions are left intact. A separate roller
is required for each color.
The other method, a screen process, uses fine silk
screens through which the paint is "squeegeed" onto
the fabric. Here, the area to be printed is left intact;
the remaining portions are masked. A separate screen
is required for each color.
Since the roller printing method accounts for the
bulk of textile printing production, we will illustrate
the application of Textile Graphics to this method.
There are analogous procedures for the screen
method.
Designs to be etched into copper rollers are transferred to the rollers in one of two ways. Either they
are traced, with a stylUS, into a coating on the roller,
or, a film bearing the design is wrapped around the
roller and then photographically exposed. The first
of these processes is called the "pantographic process"; the second is called the "photographic process." Each of them will now be described in greater
detail.
An outline of the pantographic process
The starting point for producing a copper roller by
the pantographic process is an artist's sketch. The
first step in this process begins by putting the artist's
sketch in a magic-lantern-like device and projecting
it, enlarged, on a coated zinc plate. The projection is
then traced with a sharp stylus which incises the design into the plate. The people who perform this operation are called sketchers and are the most skilled
and use the most ingenuity in the pantographic operation.
During this process "improvement" may be made
to the original design. For example, lines intended to
be made symmetric or with uniform thickness, which
were not made precisely so by the artist, will at this
stage be made so.
In addition, there may be a special treatment along
the boundary of two adjacent colors. Frequently an
extra line is placed at a specific distance from the
boundary. This line, called a double line, prevents
adjacent colors from running together. This double
line does not actually appear on the printed fabric
but is put on the zinc plate and later traced by stylus
onto the copper rollers.
After the zinc plate is prepared, it is given to another
person called a tracer. The tracer puts the plate on
the flat table-like surface of a machine called a pantograph. The pantograph machine has a stylus with
which the tracer will follow lines incised into the zinc
plate. As the tracer moves this stylus along the groove
in the zinc plate, a row of styli are simultaneously
moved. These other styli are tracing the design onto a
coated copper roller with the appropriate degree of reduction and number of repetitions across the width of
the roller. The areas of the zinc plate have been color
coded, and the outlines of each color are traced onto
a separate roller.
In addition to the original outline which the artist
drew, and the double boundaries mentioned above,
other information is imparted and traced onto the
copper roller. For example, a sizeable flat area will
be incised with parallel, diagonal lines called a
ground. When to use ground lines is part of the knowledge of the engraver in the shop who knows that the
paint must be kept at a certain level in the area to
prevent blotching and running during the printing
process. Therefore, he will specify to the tracer the
density of the lines within each area. A device called
an indexing drum is put on the pantograph and aids
the tracer in placing these ground lines into the
appropriate areas.
Another addition to the original artist's information
is called slashing: the design is placed on the roller
so that lines which are perpendicular to the edge of
the roller will be slightly angled. The reason for this
is so that the metal doctor blade, which squeegees
the paint, will not tend to break down the edges
(boundary outline) of the roller. Slashing is anticipated
in the initial set-up of the styli which trace on the
roller. Each successive stylus is progressively displaced along the circumference of the roller.
After tracing, a roller is sent to a touch up bench
where it is reviewed and imperfections are corrected
before the etching process. The roller is then dipped
in acid to etch lines into it. Lines which are to be
Textile Graphics Applied to Textile Printing
etched deeper go through more than one etching stage.
Between these stages, certain areas are painted out.
After the rollers are etched, they are chrome-plated.
The photographic etching method
Implicit in the discussion of the pantographic method was the assumption that the original artist's
design could indeed be conveyed by tracing. This is
certainly not true of all original artist's designs. Many
of them, which have been created by brush effects,
and so forth, cannot be recreated by a stylus alone.
Therefore, other techniques are necessary to transfer
the original art work to the copper rollers. These
other techniques are divided into three major categories: 1. those which are purely photographic; 2.
those which are purely manual; 3. those which are a
combination of photographic and manual. The object
of each of these processes is to produce color separation films - that is, a separate film for each color used
in the printing process. This is not a separation into
red, yellow, blue, and perhaps black. When the textiles are printed, the color which actually appears
?n the. fabric is the color of the paint used in printmg. It IS not a mixture at printing time of the primary
colors.
After these color-separated films have been made,
the process for etching the design onto the drum is the
same for each of the three techniques named. Therefore, we . will discuss this common etching process
after the individual processes for preparing colorseparated films.
Photographic etching Type 1purely photographic
In cases where it is desirable to reproduce the original artist's drawing exactly in the printed textile, and
furthermore, where the number of colors in the design
as well as their nature is such that each color can be
separated by a series of photographs with appropriate
color .filters, then the purely photographic Type I process IS employed. This is, however, applicable in a
minority of the cases. In the purely photographic
method, the original design is photographed once for
each color in the design. A filter is used to remove all
of one color from the design. The resulting film represents the filtered color separated from the other
colors. This part of the process produces one film
for each color.
ceramic designs as well, the original art work is not
of an acceptable quality for direct reproduction. The
r~asons. for this are many, but, for example, a simple
hne whIch maybe of varying degrees of thickness in
the original art work must be more carefully drawn
to have only a single degree of thickness for the reproduction process. Even the artist would acknowledge this and it is not intent which produces the original uneveness but ~ather the carrying out, on impulse,
of the idea. This kind of inaccuracy seems to be a
necessary concomitant of the artistic expression. The
restraint and precision necessary for the reproducible design is not and cannot be present in the original
creation. There have been many attempts to constrain
the artist as he works, constraining him to particular
colors or to work with a precision with which he does
not now work. These attempts have been unsuccessful, and we believe it is because of something inherent
~n the ori?i?al creative process. Therefore, the majorIty of ongmal designs must be manually recreated.
In this manual method, the art work is placed on a
table with light penetrating it from below. A clear
acetate film is placed on top of the artist's drawing.
Another person, also called an artist in the mill art
shop, prepares an acetate mask for each color of the
original design. He may prepare an acetate copy of
a? original color using brushes. He is of course doing
hIS best to reproduce exactly what he sees shining
~h~ough the light table. However, since this is a copy,
It IS to some extent an interpretation, no matter how
faithful he attempts to be.
Type III - A combination of photographic
and manual methods
Some of the manually painted acetate masks may
be negatives of certain colors, others may be direct
copies, hence positives. By photographically com?i?ing n~gative and positive films in different ways,
It IS pOSSIble to create masks of other areas.
In the simple example shown in Figure 1,
c
Photographic etching Type 11purely manual
As in the case with the reproductions of most art
work in textiles, and also true in some wall paper and
35
Figure I-Color "B" is the negative of colors "A" and "C"
36
Fall Joint Computer Conference, 1967
if one creates films for A and C, then a film for Bean
be created' by photographing A superimposed on C.
This third category may use some of the original art
work to photograph through acetate masks. For example, if there is brushwork in the original which is
directly reproducible then it may be photographed
and combined with acetate masks of other areas.
Choosing method I, II or III
There are cases when it would appear that it purely
photographic method is applicable. However, in many
cases, there may be an additional consideration;
namely, the design will not evenly fit into the basic
repeat size of the fabric on the printing machine.
Therefore, it must be reduced or expanded by a 'certain
percentage. Although the camera can be adjusted to
perform this reduction or expansion, nevertheless,
this results in producing a striated effect on the negative rendering it inapplicable for direct photographic '
reproduction. In cases such as this, a design which
seems to be of the purely photographic type may actually be of the purely manual type.
Common processes to types I, II, 111photographic etching
After the original color-separated films have been
made by one of the three methods above, each film
is used to produce what is ,called a long film. The
long film bears the original design with as many repeats of it as are necessary to fully' cover the roller
and is the same size as the copper roller, that is, the
same width and as long as the circumference of the
roller. This long film is wrapped around a copper
roller which is then photographically exposed and
etohed.
In order to make the long film, the individual
color-separated films are put, one at a time, into a
machine called a "step and repeat" machine. The
data which accompany the original color separation
film to this machine consist of the number of times
the design will have to be repeated on the drum, and
the placement of each repeat. There are step and
repeat machines which accommodate these data in
some automatic method such as a punch tape control.
Other models set the data manually. However, the
purpose of the machine is to subject the color-separated film to a number of exposures in different positions. They will be developed on the single "long
film." After the long film is developed, it is sent to a
room for inspection and correction before it is
wrapped around the copper roller and exposed. The
roller is then etched in acid.
Applying textile graphics
Categories of printed textile designs
From the previous descriptions of the two basic
methods of preparing copper rollers, it seems reasonable to divide textile print designs into two categories: traceable designs and non-traceable designs.
Traceable designs are those whose boundaries
can be created or recreated (traced) by a stylus.
The areas inside the boundaries are characterized by
flat painted effects which could be made by a brush
although they might as well be made by a device such
as a felt-tip pen. Non-traceable designs are those
which do not possess these properties. They are
characterized by brush and stipple effects.
It should be obvious that traceable designs could
be produced on a copper roller by either the pantographic process or the photographic process as these
two methods now exist. Indeed what we call traceable designs are sometimes now produced by either
process, so that calling such a design by the name
"pantographic type" as the industry now does is an
artificial distinction.
Using textile graphics for traceable designs
Textile Graphics may be used to develop long
films for traceable designs which constitute about
half of printed textile designs. The input to the computer is an artist's sketch and the output is a series
of color-separated long films.
There are three phases of this computer-aided
application: input, development and output. During
the input phase, part or all of the original artist's
drawing is traced on a digitizing tablet; any untraced
portions are built up with "symmetry" and other
function keys. The regularizing of the design (described above), which is currently done by the
sketcher, is done in this phase.
In the development phase, the designer-technician
interacts with the computer to develop the additional
information needed for printing the design. This information, (described above) which consists of color
separations, double boundary lines, ground lines,
and slashing is currently divided between the sketching and tracing phases of the pantographic operation,
or between the painting and photographing phases of
the photographic operation. The purpose of this
development phase is to develop one complete repeat of the design for each color.
During the output phase, the designer specifies
the "step and repeat" information to the computer
and a series of long films is outputted on the photographic plotter.
Textile Graphics Applied to Textile Printing
Input - phase I
Because a great deal of regularizing "of the original
artist's sketch takes place during the tracing phase or,
what is called in the printing mill, the sketching phase,
it is necessary to retain this tracing in any computer
assisted process.
The artist's sketch is entered into the computer by
tracing it on a digitizing device. The tracing styli of
commercially available digitizers are electrostatically
or capacitively coupled to a flat surface upon which
the art work is positioned. As the tracer moves the
pencil-like stylus along the boundaries of the design,
this outline coordinate data are transmitted into the
computer. The data are collected in the computer's
main storage and simultaneously displayed on the
IBM 2250 display screen. The 2250 also has a keyboard of "function keys." When the operator depresses one of the keys, the computer program
determines which key was depressed and branches
to the appropriate section of the program to perform
the requested "function." Using these function keys
and the light-pen, the designer-operator can translate,
enlarge, reduce, erase, or repeat part or all of the displayed design. If the design has symmetry, the
operator may elect to trace only a portion of it and
request the computer to generate and display the remainder reflected about any chosen lines of symmetry.
The advantages of this input technique over both
the tracing that is performed in the pantographic
method and the painting that is carried out in the
photographic method are significant. Less care
and precision is required of the operator (sketcher)
because the program "smooths" the free hand tracing.
Even assuming no data smoothing, the tracing is
physically easier. It requires no more pressure on the
stylus than that normally used for pen or pencil on
paper, while in the pantographic process, the sketcher
must inscribe the design into a zinc plate, and in the
photographic process he must paint the outline on
film with brush and ink.
The on-line graphic devices speed up the tracing
phase of the process for a number of other reasons:
(1) The pantographic sketcher is working on a
design at a fixed enlargement. The simpler areas of
a design are unnecessarily traced at this enlargement.
Conversely, the photographic sketcher is working
with a design at actual size, so that the complex
areas of the design must be painted at actual size.
The computer-aided approach permits the sketcher
to trace various sections of the design at different
degrees of enlargement. Under function key and light
pen control, the completed sections are then overlapped and given a common enlargement factor.
37
(2) When there is symmetry present in the artist's
sketch, the sketcher may need to trace only a portion
of the design. The computer program may calculate
and display the remaining symmetrical portions.
(3) Any regular shapes, e.g., squares, rectangles,
and circles, present in the design would not have to
be traced at all. The desired shape is retrieved from
an expandable library of frequently used shapes stored
in the computer, and displayed on the CRT. It is
given the required degree of enlargement and then
rotated and translated into position within the design.
(4) Sketching errors are easily corrected with the
light pen.
(5) It may be clearly the artist's intent that lines of
varying thickness in his sketch should actually be of
constant thickness. The sketcher, using brush and
ink, would find this operation tedious, at best. Using
light-pen and function keys, the sketcher maintains
uniform line thickness of any desired amount.
(6) Both the tracer operating the pantograph
machine and the sketcher painting acetate film will
circumscribe the entire outline twice. In the pantographic process, the boundary line separating two
colors will be traced on each of their respective
rollers, while in the photographic process, the boundary line separating two colors, will delimit each area
painted on their respective films. Tracing on a tablet
will eliminate all of the former tracing operation and
half of the latter.
(7) In pantographic tracing, if the length of the
basic design is a submultiple of the roller circumference (and it frequently is), additional complete
tracings are required. A digitizing tablet eliminates
this requirement.
Development - phase II
When the outline of the design has been completely transmitted to the computer, a function key
will initiate an algorithm which assigns a unique label
to each disjoint area of the design (Figure 2), and
displays the labeled areas on the 2250. This algorithm
is described in detail in Ref. 1. It performs a raster
scan of the design and assigns a zone number to each
row segment between "strikes." Every zone is
checked against the preceding row to determine if
there is any vertical overlapping. If there is, the current zone is given the same label as the zone with
which it has common columns. By successive applications of this process, and reassigning labels when it
becomes apparent that two zones are equal to each
other, it is possible to separate all disjoint areas.
In Figure 3, when the scan reaches row (n + m) it
detects that the entire row is one zone. This row-zone
38
Fall Joint Computer Conference, 1967
Figure 4 - Example of zone diverging
Figure 2 - Design with each disjoint area assigned a unique label
------~----------
n + m
n
Figure 3 - Example of zone merging
is the same as zone 1 because no curve has intervened.
On the other hand, the zone of this row is the same as
zone 3 for the same reason. Therefore, the algorithm
concludes that zone 1 and zone 3 are in the same connected area. A table of zone equivalences is kept, and
after the entire design is scanned, each row-zone is
assigned its unique area label.
Figure 4 is the inverse of Figure 3.
I t should be noted that this algorithm does not make
demands on the· user to label his own areas as he
creates them, a common procedure in some graphics
applications. The purpose of our a~proach is to
permit the designer to operate as naturally as possible.
Colors are separated in the following way: the designer uses a function key to enter the "EQUATE"
mode. Then he detects, with the light-pen, the labels
of all areas which he wants to be the same color. These
labels all become the same as the first label detected.
A separate file is created containing the set of boundaries for this color. This process is repeated for each
color.
Some areas of different color, which have a common
printed boundary may actually have such boundaries
etched into the respective color rollers at a slight
displacement. This displacement prevents "bleeding"
of the paint during printing. Such a displacement can
be specified on the total design by specifying a double
line at such places. The designer specifie-s, with function keys and light-pen, the areas and the amount of
displacement between their common boundary. Then
a double line is created along this boundary which
will give rise to the proper displacement on the rollers.
The ground lines, which are parallel, diagonal
lines within., the boundaries of sizeable areas, are
used to prevent the paint from running out of the
intaglio area on the roller. The areas which need such
lines are determined by an engraver and specified
by him on the original drawing. The designer-technician transmits this information: name of area,
angle of lines and distance between lines - with function keys and light-pen. He may display the design
on the 2250 either with or without these lines depending on whether he is looking to make a technical
or an aesthetic judgment.
The engraver also specifies the slashing angle of
the design. The designer, who transmits this, may also
view the design with or without this "angling."
Output - phase III
The output phase of the process is the generation
of "long films." These are efficiently produced by an
on-line high speed photographic plotter. The film is
wrapped around a cylinder and the cylinder is rotated
Textile Graphics Applied to Textile Printing
under a CRT. The scanning electron beam of the
CRT is digitally modulated, res~lting in a plotting
time that is independent of the density of the information plotted.
The computer program was initially supplied with
the exact width and circumference of the copper
rollers to be used. The basic design has been exactly
scaled and adjusted to provide the specified number
~f repeats, both vertically and horizontally, that will
completely cover the roller.
A separate film is now plotted for each roller in the
design. For example, the design shown in Figure 5 will
.~
.~
.~
.~
.~
.~
.~
.~
.~
39
.~
.~
Figure 6a,b,c- The three color separated films of design
shown in Figure 5
A new designing tool
Figure 5 - Three color design
result in the color separated films shown in Figure 6.
The double line, ground lines, and slashing (which
are not shown in the figure) would, of course, be
present. Using the on-line plotter to automatically
produce the "stepped and repeated" long films has
eliminated the set-up time and possible errors that
result when using either the engraving machine in the
pantographic process or the "step and repeat" machine in the photographic process.
Looking ahead to a "second generation" textile
graphics system, it appears feasible to replace the
film and cylinder of an on-line plotter with the copper
rollers and to directly photo-expose the design.
With Textile Graphics it is possible for the designer to do something which he has not been able to
do before.
Both the photographic etching process and the
pantographic etching process have a library of
"effects." For the pantographic process this is a set
of small round mills which are pressed onto the roller
over its entire surface; and for the photographic process this is a library of negatives with repetitive
patterns. Both methods use these libraries to generate
an entire copper roller with this effect repeated over
it.
We store such a "library" within the computer.
While sitting at the 2250 console, the designer can
specify any of these "effects" to occur within any
disjoint area which he points to on the screen. This
40
Fall Joint Computer Conference, 1967
greatly enhances his ability to generate patterns
since· he can use these effects like a Jacquard designer
uses "weaves."1
An illustration of this technique is shown in the
following figures. 7
\
The outline of the design is the same as Figure 5.
The design is to be printed in four colors. Areas 1, 4, 7
are color #A, areas 2, 6, 8, 9 are color #B, area 3, 5,
color #C. The background, area 10, is color D. Note
that in areas 1, 4, 7 there is an "effect" which is'ruso
color D. This is represented in figure 7.
SUMMARY
We have demonstrated a computer-aided method for
. generating color-separated "long films" for . traceable textile designs; starting with an artist's drawing.
These films are the direct input to the roller etching
process.
This method merges parts of two processes which
are almost distinct at the present time. Namely, the
tracing of the pantographicpro'cess is maintained, but
the etching is continued by the photographic process.
This method is a new application and extension of
the Textile Graphics techniques described in Ref. 1.
Previously, Textile Graphics had been applied only
to Jacquard weaving and to warp-knitting.
We have shown that Textile Graphics can significantly shorten the lead time between the creation of
the original art work and the etching of copper rollers.
The next logical step is to tie the technique into a
fully integrated system monitoring the other operations in the mill. For example, the colors specified for
the design, and the anticipated yardage to be· produced using this design, would be inputs to inventory
control and production scheduling programs. Raw
material requirements, finished goods inventory,
costing" and printing machine down-time analyses
are other areas of importance that can be made available to the textile manufacturer on demand.
l-
I-
l-
I-
REFERENCES
J R LOURIE J J LORENZO A BOMBERAULT
On-line textile designing
Proceedings of ACM 1966 National Conference p 537
2 J R LOURIE
The textile designer of the future
Handweaver and Craftsman p 8 Winter 1966
3 A REISFELD
Warp knit engineering
National Knitted Outerwear Association 1966
t.
l-
t.
I-
t.
l-
I-
Figure 7 a,b,c,d - Color separated films for four color design
showing "effects"
Holographic display of digital images
by L. B. LESEM and P. M. HIRSCH
IBM Scientific Center
Houston, Texas
and
J. A. JORDAN, JR.
Rice University
Houston, Texas
and transform it into a optical hologram, thereby allowing us to construct the three-dimensional image of
the scatterer of the sound waves. The same procedures
would translate a radar hologram into an optical one.
These processes may also make possible magnification of microscopic images in the computer; the optical
hologram of a microscopic object could be translated
so as to yield a greatly magnified image. Such an image
may well be free of the aberrations which so plague
three-dimensional microscopy.
The fulfillment of these ideas depends upon the
solution of several problems which have inhibited the
development of computer-simulated "holograms. Efficient
computational techniques must be utilized in order that
large-scale holograms may be generated in reasonable
amounts of computer time. In this paper, we discuss
first the mathematical representation of holography,
then the computational techniques which we have used,
and finally we exhibit some of the results of our efforts.
INTRODUCTION
An optical hologram is a two-dImensional photographic plate which preserves· information about the
wavefront of coherent light which is diffracted from
an object 'and is incident upon the plate. A properly
illuminated hologram yields a three-dimensional wave,front identical to that from the original object, and
~hus the observed image is an ~xact reconstruction
of the object. The observed image has all of the usual
optical propertie~ associated with real three-dimensional objects; e.g., parallax and perspective.
The computer-simulation of the holographic process
potentially provides a powerful tool to enhance the
effectiveness of optical· holography. The construction
of holograms in a computer provides a potential display device. For example, mathematical surfaces can
be displayed, thus permitting design, to be visualized
in three dimensions. In addition, computer generation
of holograms can provide a new optical element (Le.,
lenses, apertures, filters, mirrors, photographic plates,
etc.) without introducing the aberrations usually associated with such elements. Thus "perfect" systems
can be examined, and experimental parameters can be
easily varied. Also, a computer can perform operations, such as division, which are difficult or impossible,
using real optical elements. Furthermore, computer
holography can be used to filter the degrading effects
of emulsion thickness and non-uniform illumination
from optical holograms.
The computer generation of holograms is part of
a larger problem. Interpretation of holograms; i.e., the
construction of digital images from holograms, con5titutes the "inverse" problem. Together, these two
processes hold considerable promise. One can construct
computer techniques which would take an acoustic
hologram (the wavefront from a scattered sound wave)
Mathematical representation of the
holographic process
Consider a monochromatic wave from a point source
Po, which is incident upon an aperature A in a prime
opaque screen. Suppose the screen is a distance r from
Po and let the point P lie a distance s from the screen.
Using Kirchoff's boundary conditions (Born and
Wolf l ) one obtains the so called Kirchoff diffraction
formula
U(P)
Bff--A
[cos(n,r)
(1)
r+s
cos(n,s)] dA
where B is constant which depends on the initial
amplitude of the wave. In the limit of small angles and
41
42
Fall Joint Computer Conference, ·1967
plane wave illumination this integral further can be
simplified:
U(a,b) -
B
f f
(2)
F(x-a, y-b) dxdy
A
where *
F(x-a, y-b)
= ex p ~r 'k [(x-a)2 + (y-brl] 1~
_1
L 2z
J
The integral given in equation (2) can be extended
by superposition to become
T *.F = B
f f
T(x,y)F(x-a, y-b) dxdy
(3)
A
where the region A is a collection of apertures each
with transmittance described by the complex function
T(x,y). The integral in equation (3) is a convolution
(T*F) of the function T(x,y), the image, with the
function F(x-a, y-b) , the propagation function.
If one adds a plane reference wave, ArelkOa, incident
at a small angle () to the hologram plane to the diffracted wave front, the intensity of the total wave
front is given by:
H(a,b)
I T * F (a,b) + Arelkoa 12
= :T * F (a,b) 12 + A/ + (T * F)Are-lkOa
+ (T *F)* Are-Ikoa
(4)
In the reconstruction process, the hologram whose
plate darkening corresponds to the function H(a,b)
is illuminated by a plane, coherent, monochromatic
wave. Again, there is a convolution, but now (H(a,b)*
F (a-x, b-y». The result of this convolution is three
wave fronts: A wave with amplitude I T *F(a,b) 12
A/ is propagated in the direction of the illuminating
wave. A wave with amplitude (T.F) * F is propagated
at an angle () to the illuminating wave. This wave yields
a real image, or a reconstruction, of T at a distance z.
A wave front with amplitude (T.F).F is propagated
at an angle -(} to the illuminating wave. This wave
is identical with that which would be observed from an
object located a distanc~ -z from the hologram, and
thus yields a virtual image. Thus the first two terms in
Eqn. 4 represent a central order image, the third term
the real image' and the fourth term the virtual image. The
term e-1koa acts as a shift operator and spatially separates
the real image from the other two images; similarly the
+
"'We have recently modified this propagation function in order to spread the information over the whole of the hologram.
This spreading is analogous to that produced by the diffuser
plate used in optical holography. The numerical "diffuser"
is achieved by multiplying F(x,y) by an appropriate real-valued
function, e.g. l-e -C(X2 +y2) for some constant c. Our technique does not increase bandwidth needed to describe the object whereas the optical diffuser does.
term e-1ko separates the virtual image from the other
two.·
Comp..utational techniques
The computer, generation of holograms has been
inhibited by the massive task involved in the straight
forward numerical calculation of the convolution integrals of Eqn. 3. The first computer-generated holograms were reported by B. Brown and A. Lohmann2 in
1966. These holograms were of the "binary mask" type
which uses only two grey levels to encode the information in Eqn. 4. In 1966 J. Waters8 extended this binary
mask technique to three dimensions.
Huang and Prasada6 suggest~d the use of transform techniques for holograms which, to first approximation, may be considered as Fourier transforms. In
1967, we7 made holograms with 32 grey levels using
an array of 64 X 128 for the object. At the time of
this writing we have 105 resolution points in our image.
Since Eqn. 3 is a convolution integral, it may be
readily evaluated using Fourier transform techniques.
Indeed, the Fourier transform of H (a,b) is just the
product of the Fourier transforms of T(x,y) and
F(x-a, y-b):
H(',1])
=
T(" 1])F(" 1])
(5)
The convolution can be computed by taking the in~
verse Fourier transform of Ha,1]). In evaluating T • Ii:digitally' we use finite Fourier transforms3 rather than
infinite integrals.
A mathematical flow diagram of the program for
hologram construction is given in Figure 1. A major
part of the program is that in which T * F is evaluated
using a fast finite Fourier transform subroutine. In .our
work T(x, y) is defined in basic "building blocks,"
arrays of 64 X 128 elements. These arrays are mapped
onto the hologram plane using a propagation function
F(x-a, y-b) which is defined over 128 X 512 elements. Conventional techniques for performing this
map would require 2 29 machine operations (by a machine operation, we mean a complex multiply and
add). For an array of N elements, the fast finite Fourier transform technique requires only N log2 N operations; i.e., 221 operations in our example.
In the two-dimensional case, a further simplification can be made. The propagation function F(x, y)
is separable; i.e., F(x, y)
F 1 (x).F2 (y), where
=
*The first holograms, constructed by D. Gabor5 in 1948 lacked
the reference beam. He showed that the terms (T"'F) and
(T* F) '" were present on his photographic plates, but he could
not spatially separate them. A. Lohmann first proposed the
two-beam technique described here. Independently, E. Leith
and J. Upatnieks discovered the two-beam technique and made
the first usable holograms with a monochromatic laser source.
Holographic Display of· Digital Images
where
B(r,s) == T(r,s)
PROPAGATION
FUNCTION
IMAGE
T(x,y)
F(o-x,b-v)
==0
F()I.BER TR~~
OF T(XtY) ,
T{l' .71)
1
FaRER TRANSFORM
OF F(a-x,b-yh
IMAGE
PROCESSING
T{r .71)
Ftr ,n)
MULTIPLY
TRANSFORMS
111.'7)·F('f.1J)
The finite Fourier coefficients B(j, k) and F(j, k)
are given QY
NF-l MF-l
. L2: B(r,s)exp(-2'7T1(--+--»
.rj
sk
B(],k)=
NF
MF
(7)
and
NF-l MF-l
.
~~
rj
sk
F(],k)== L.,; L.,; F(r,s)exp(-2m( NF + MF-.»
r==O 8==0
INVERSE TRANSFaN
,
T. F(a,b)
The inverse finite transform
B(j,k).F(j,k) is defined as
INTERPOLATIO'J
OF T-F(a,b)
A(n,m)==
ADD REFERENCE
BEAM
T4' F+e ikO'
sa UARE MAGNTUDE
2
IT"F + e ikdl IS
HOLOGRAM
l
SCALING AND
PLOTTING OF
HOLOGRAM
Figure I-Flow diagram for hologram construction
2
iky
Fl(x) == e and F 2 (y) ==~; . Thus the Fourier transform of F satisfies F(t, T}) == F 1 (t).F2 (1])' If the
propagation function is an- NF x MF array, the savings in machine operatio'ns accomplished using the
separability property is (NF.ML log2 NF.MF) (NF lo~ NF + MF log2 MF + NF.MF /2), a saving
of 24 operations in our example.
These savings are not fully achieved- however. The
convolution which is obtained is not good over the
NF x MF points of the propagation function, as can
be demonstrated by the Helm-Sande theorem on finite
convolutions.· If the object T(x,y) is defined over
NF x MF points, where NF>NT and MF>MT, tben
the finite convolution of the two is written as
NF-l MF-l
2Z
W(n,m) ==
L L
r==O s==O
n==O,I, ... , NF-l
m==O,I, ... ,MF-l
the
product
B(r,s)F(n-r, m-s)
2: 2: B(j,k)F(j,k)exp(2m(-jn +
km
]
(8)
'=0 k==O
,J,
2
of
NF-l MF-l
J,
ikx
r==O,l, ... NT-I
s==O,I, ... MT-l
r=N~ NT+l, . . . ,N~l
s=MT, MT+l, ... , MF-l
r=O 8==0
I'
~
I
43
(6)
NF
MF
The Helm-Sande theore mstates that W (n,m)=A(n,m)
only for the region NT - The visible table contains the triangle number visible
at the designated x position of the scan ray.
3. Add to the visible table
a. Figure 10 shows a completed visible
table for a scan line.
b. The contents of the table are triangle
names (or numbers) showing which
triangle is visible at a given x.
c. For each x increment of the scan ray
update the x-occupied table. Using
the x-occupied table and the distance
computation, the visible table is modified by placing the name of the visible
Half-tone Perspective Drawings by Computer
triangle in the location corresponding
to the present x value (Figure 10).
d. The visible table is constructed for an
entire scan line and IS then used to find
which triangle's intensity interpolation
parameters are to be "lied for each x.
E. Per point intensity calculatio, s
Calculate the intensities for each x in the
current scan line.
1. We interpolate to find the intensity over
the visible interior of a triangle using only
the intensity values at the three vertices.
This allows a considerable reduction in
computing time. For simplicity and
speed, but not necessity, we chose linear
interpolation. The linear interpolation
parameters have already been calculated
and stored during the per frame calculations (Section II, B, 1, c).
2. The formula for the intensity at a point
x on the scan line y is
I=ax+by+c
Where I is the intensity and a,b, care
the linear interpolation parameters for
the visible triangle.
F. Output to display device
The list of intensities for this· scan line is
sent to a peripheral device for eventual display. The output subroutines are distinct
and independent of the half-tone algorithm
to permit flexibility as the display hardware
is improved or altered.
Results
I. Program
A FORTRAN IV program of the algorithm (Figure 11), called PIXURE has been written* and used
to produce half-tone pictures of a cube and tetrahedron (Figures 13 through IS). For both the cube (12 triangles) and the tetrahedron (4 triangles) the execution
time of PIXURE was roughly 25 seconds to calculate a frame of 512 x 512 points on a Univac 11 OS.
PIXURE at present is approximately 3S00 Univac
1108 assembly language instructions in length and
occupies 14K 36-bit words of storage for a picture
of 100 triangle complexity.
Preliminary tests indicate that the execution time
is most dependent on the number of scan lines that
intersect the two~space image of the object (e.g. there
are eleven scan lines, 2 ~ Y ~ 12, that intersect
triangles in Figure 6). It also appears that this cle*Modifications of this program and some new work are progressing rapidly.
55
RELATED
SECTIONS
I.A
Ir.B
II.e
SCAN LINE
COMPUTATION
I
I
I
II.D
PER POINT
CALCULATION
I
I
I
INCREMENT
Y
I
II.E
I
PER POINT
I
INTENSITY
CALCULATIONS
____II
---II. F
SCAN LINE
OUTPUT
NO
Figure 11- Flow chart of the half-tone perspective algorithm
pendence is very closely linear. On the other hand,
execution-time dependence on the number of triangles
(i.e., the number of intersection points per scan line)
appears to be much better than linear. The dependence
on the number of hidden triangles per intersection
point has not been rigorously determined, but seems
to be close to linear.
II. Hardware techniques
Each scan line that PIXURE generates is sent to
a PDP-S via a specially designed interface (Figure
12). The PDP-S serves essentially as 1) a buffer, 2) a
raster generating device for an oscilloscope, and 3)
an a-synchronous I/O channel comIl)unicating with
the 11 OS. Each scan line, in turn, is stored in the PO p.;.
S memory and then transmitted through a digital to
analog (D-A) converter to a Tektronix 453 oscilloscope. The scan position is dictated by ten bit x and y
registers in the D-A converter. The intensity of the
beam at each point in the scan is controlled by a six bit
z register. Due to storage and! lOS - PDP-S transmis-
56
Fall Joint Computer Conference, 1967
UNIVAC
1108
~36
BITS I WORD
INTERFACE
cally as possible, using two-dimensional images (or
displays). We have chosen to erase hidden surfaces
and use half-tone shading to give the illusion of depth
(or distance) and indicate spatial relationships. Although we are presently limited to a single source of
illumination at the view point; nonetheless, the pictures of our test objects show obvious dimensionality.
Figures 13, 14 and 15 represent a cube whose resolution differs by a factor of ten. It is evident that
Figure 14, representing a picture of 512 x 512 points,
"I BITS/WORD
1~12
...........................
....
... ... ...................
. .
.... .............
...............
::::::
::::::::::::::!:::::::::::::::::::::::
.. ::...
::::::::::;:
:::::::: :;::::::::::::.-::
: ::::::::
......................
:........ :.:.::
:::: .. .
:::::::::
u::--.:::::
.........
.
......... ..
..........
................
PDP-8
~iiiiii!:
o
\l
10 BITS
·ngillg~
:::::::::
iiiiit::::::::::
:::::::::H!mHHi-:!!!:
:::::::
1.~:::::::::::
..........
................
-::::::
:u::::::::::::::
-:::::::.
.......
e.......
..
::::::
-:::::
.::;,
..
......
...
.................. ..
•.......................
~~~~~
:::::::::::::::::::::::::::::
•• ••.• • •• HiH!!HiH!H:
:::::.--u::n:::u::.:.~:::
:~~~!
.......:::::HmHffiimmmmm~
-;!iiHHHH!m!!!!:ffi!!H**:fi:iiH::::::!;
···un::·········································
:;iHfmiii!iiHimHilimilimi!iii5!i.i!~
.uu:u ·u·· ..•:.•.•:.••......................
.:mii1atiiiiiiilibiiiliiiiiilif:Hiiliiiii~
xii VII Z
DC VOLTAGE LEVELS
Figure 13-Cube 100 x 100
HOR. VERT. INT.
TEKTRONIX
453 CRT
DISPLAY
SYSTEM
Figu're 12 - Display system
sion-rate limitations we have been forced to take time
exposure photographs of the scope trace. As soon
as a scan line is completed, the PDP-8 requests information for the next scan line~ For a 512 x 512 frame
it takes approximately ten seconds to generate a picture .
. III. Subjective interpretations
The principal objective of this project is to allow
people to see three-dimensional objects, as realisti-
Figure 14-CubeS12xS12
Half-tone Perspective Drawings by Computer
57
Figure 17 ~ Tetrahedron 512 x 512
Figure 15 - Cube 1024 x 1024
supplies sufficient information to adequately describe the cube. A more critical test on the resolution of the receding edge could not have been made,
and yet, the edge appears tn the higher resolution
pictures. The unusual perspective, however, was
merely the result of an arbitrary choice in geometry.
The apparent triangular composition of the cube
faces has since been corrected and a smooth transition across triangle boundaries achieved (Figure 16).
The pictures of the tetrahedron (Figures 17 and 18)
are superior in quality to those of the cube for two
reasons. First, a defect in the display hardware was
partially corrected, resulting in a more even display
pattern. Scan lines are still noticeable, but it is felt
that additional improvement in the hardware will
significantly diminish this defect. The second improve-
Figure 18 - Concave tetrahedron 512 x 512 (one side removed)
ment was in the selection of a more correct range of
intensity levels used in the brightness calculation.
Another objective is to display an object so that
it will not be ambiguously interpreted. The tetrahedron in Figure 17 is decidedly convex, but Figure 18
could be either convex· or concave unless the source
of illumination be specified.
SUMMARY
Figure 16-Cube 512 x 512
In the cases we have tested, the computing time
grows almost linearly with the resolution of the picture, the size of the visible portion of the object and
apparently, the amount of hidden surface. This makes
the algorithm practical, and is a result of special
58
Fall Joint Computer Conference, 1967
sorting techniques which greatly reduce the number
of hidden surface comparisons required. The objects
we have displayed appear quite three-dimensional
an'd their hidden surfaces are effectively eliminated.
The computing time required for a picture composed
of over 106 points was approximately 40 seconds
on a Univac 1108.
The present system definitely proves the feasibility
of the real-time display of two-dimensional half-tone
images. It is felt that the technique may be easily
extended to stereo representation of half-tone images.
Furthermore, the algorithm is so ·constructed as to
allow computations to be executed in parallel (see
the dotted section in Figure 11). As many scan lines
as hardware permits may be calculated simultaneously. Also, much of the computation may be performed
by incremental hardware. The parallel and incremental characteristics of the algorithm lead us to believe
that real-time movement and display of half-tone images is very near realization.
A typical user wishes to describe an object in a
form convenient for him. Also, a flexible and extensive data structure must be constructed to contain
and manipulate an object. Therefore, the practical
application of the algorithm depends greatly on the
ability of the system to convert an object into a suitable mesh of triangles. Our group has initiated work
in these direc·tions and at present has a triangle generation algorithm operational for objects composed
of planar surfaces.
ACKNOWLEDGMENTS
The authors are deeply indebted for the programming
assistance of Lee Copeland and Richard Blackburn.
The technical skills of Richard Jepperson, Charles
Eder and Y. T. Kim have assisted immensely in helping produce the first photographs. And, last but not
least, we wish to thank the University of Utah Computer Center for their patience and assistance in making these results possible.
BIBLIOGRAPHY
,
A L FASS and A R AMIR-MOEZ
Elements of lin ear spaces
Macmillan Company New York 1962
B E MESERVE
Fundamental concepts of geometry
Addison-Wesley Reading Mass 1955
L G ROBERTS
Homogenous matrix representation of N-dimensional solids
MIT Lincoln Laboratory Lexington Mass
L G ROBERTS
Machine perception of three-dimensional solids
MIT Lincoln Laboratory 1963 Technical Report no 315 Lexington
Mass
VISTA-Computed motion pictures for space research
by GEORGE A~ CHAPMAN
Computer Sciences Corporation
Silver Spring, Maryland
and
JOHN J. QUANN
National Aeronautics and Space Administration
Goddard Space Flight Center
Greenbelt, Maryland
INTRODUCTION
The application of digital computers to reduction of
telemetry data assumes an increasingly important role
in the analysis of physical problems. I Even after reduction of the raw sensor data, an immense volume of
resultant data remains. Thus there is a constant need
of new tools for computer-aided analysis, synthesis
and display of scientific results.
Graphic aids have evolved from printer-listings,
through lineprinter plots to a wide range of x-y plotter
techniques. Cathode Ray Tube devices (hard copy and
one-line console) have introduced the latest generation
of display capability. The trend, with this'latest capability, is from static x-y plots to dynamic time-sequence
displays.
This paper presents a generalized technique for
generation of off-line CRT motion-picture displays of
objects in three-dimensional space. Initial implementation of the system, called VISTA * (Visual Information
for Satellite Telemetry Analysis), uses the Univac 1108
computer to generate time-sequence displays for output on the Stromberg Carlson 4020 microfilm plotter.
The system accepts satellite orbit and attitude data and
produces motion pictures illustrating the three dimensional position and' orientation of the spacecraft in orbit,
relative to one or more celestial bodies.
sical picture of that data. The picture is not what is
normally referred to as a data plot but rather a true
representation of the spacecraft in orbit about a central
body. The program output is synchronized with orbit
time and is used to prepare multiple frames of 16 mm
or 35 mm film on the SC-4020.
Current statistics indicate that one to two 1108 computer seconds is required to produce each individual
frame (as illustrated in Figure 2). This variation in
computer time is due to change occultation requirements. Computing time approaches a maximum when
one body occults a dense portion of the earth's shoreline. At a camera rate of 16 frames per second, one
minute of viewing time requires 24 minutes of 1108
computer time.
When the film is viewed through a projector as a
motion picture, a continuous time history of the motion
and orientation of the spacecraft is observed thus enabling a viewer to assimilate in a few seconds a large
volume of data while subjecting the data to a rapid and
comprehensive analysis.
There exist two major subsystems in VISTA over
which the user has complete control and the potential
for dynamic alteration:
1. Presentation of a mapped earth system and a
spacecraft body system, ranging from a simple
point-mass display to an orthographic projection
of a solid spacecraft, which can be viewed from
any arbitrarily chosen vantage point.
2. Presentation of data from an experiment aboard
the spacecraft in one or more of several forms
designed to aid the viewer in his analysis of the
data.
.
VISTA-General description
VISTA is a generalized system which accepts spacecraft orbit and attitude information and creates a phy*VISTA was developed by Computer Sciences Corporation
for NASA-GSFC.
59
60
I.,
Fall Joint Computer Conference, 1967
The first subsystem is concerned with the dynamics
and the orthographic projection of bodies in motion in
some arbitrarity specified coordinate system. In the case
of three-dimensional objects, construction lines, object
lines and detailed markings not visible to the viewer
are automatically deleted from projection. This "hidden
line" capability is used when occultation occurs between one or more of the included bodies. The user
of the VISTA system has complete control over the
desired view angle or vantage point. The viewers location and view vector may be either static or dynamic.
The second subsystem is primarily concerned with
presenting and formatting data, title frames and selected
overlay inf~rmation. In this area, the prime objective
was to overcome the inherent jitter associated with data
plotting in a motion picture atmosphere and at the
same time include complete data presentation capabilities. Both objectives have been successfully achieved and
a wide variety of options and presentation formats are
included to aid the viewer in his analysis of the data.
These capabilities include presentation of data in the
form of a "clock" with the hands indicating orbit sensor
measurements. The speed at which the different hands
move reflects relative speed and acceleration of the
data variables. Two and three dimensional grids are
also available where the latter may be rotated to a
"best" view. Either the data or the grid can be oriented
for rapid recognition as the frames are repeatedly updated and projected. A "marker" is also available, which
points to the specific data point associated with the
given display.
Although both of these subsystems are of equal importance, this report is addressed to the capabilities and
techniques concerned with the dynamics and the orthographic projection of bodies in motion.
longitudinal (Y) axis and about the solar array (X)
axis are controlled so that the Body (Z) axis is directed
toward the center of the earth. The rotation of the
Main Body. about the Z axis and the rotation of the
solar array about its shaft axis are controlled so that
the array face is aligned perpendicular to the sun line.
The rotation of the OPEP with respect to its shaft· is
designed so that it tracks the component of the velocity
in the orbital plane. Therefore, in order to define the
orientation of the spacecraft there exist nine vectors,
each with three components in inertial coordinates. Add
to these 27 numbers other quantiti~s of position, velocity, latitude, longitude, height, etc., and it can readily
be seen that for any instant in time there is a large
amount of interrelated data which is difficult, at best,
to simultaneously correlate for analysis while at the
same time verifying the overall spacecraft system response.
Spacecraft
Coordinate systems
VISTA was originally developed as an aid in the
checkout of an attitude computation program for the
Orbiting Geophysical Observatory (OGO). The OGO
spacecraft, depicted in Figure 1, carries into orbit about
the earth, a large number of varied geophysical experiments. A greater understanding of the earth, and of
earth-sun relationships will be obtained from them.
The experiments will supply data on such phenomena
as auroras and low energy solar particles. 3
OGO has three main physical components: A Main
Body, a Solar Oriented Experiment Package (SOEP),
and an Orbital Plane Experiment Package (OPEP).
In orbit the Observatory has five degrees of freedom:
rotation of the Main Body about each of its principal
axes, rotation of the SOEPs with respect to the Main
Body, and rotation of the OPEPs with respect to the
Main Body. The rotations of the Main Body about the
Within VISTA three coordinates systems, central or
reference, body, and image, are used to describe the
rotation and translation of the various bodies introduced
into the viewing system and orient them in a proper
viewing perspective.
Position and orientation information relating the
body to the central coordinate system and similar criteria
relating the image coordinate system to the reference
system are sufficient to prepare the frames as shown in
Figure 2. In the development of these frames (and
the resulting motion picture) the central coordinate
system' was defined by information supplied from time
sequenced orbit and attitude data on magnetic tape.
Such data as vehicle position, velocity and sun position are expressed as vectors in the geocentric equatorial inertial system. Spacecraft axes orientations, also
expressed in this system, are given as unit vectors and
Figure I-OGO spacecraft
VISTA-Computed Motion Pictures for Space Research
61
ously. Points grouped as components are rotated and
translated to the image coordinate system where the
line descriptors define plottable line segments and the
loop descriptors are used in the final occultation testing.
The body represented in Figure 3 is a partial representation of the OGO spacecraft consisting of the main
body, and one solar array. The figure as shown is
described with 14 points. Since the solar array rotates
about the main body axis as it maintains alignment
with the sun, points 1 through 8 are grouped as one
component (the main body) and points 9 through 14
as another (the solar array). Seventeen lines and seven
loops complete the description. As an example, the
Y face of the main body is composed of lines ( 1,2) ,
(2,3), (3,4), (4,1) and forms one loop.
-zI
Figure 2-Projected frames
6
as such are directly applicable for use in the VISTA
rotational matrices. Other information relating to the
earth such as latitude and longitude of the subsatellite
point are given in geodetic coordinates.
In VISTA, the image system is formed with the
earth at the center and the viewer located on the
Z
axis. The X, Y plane thus becomes the image raster
"screen" to which all orthogonal projections are made.
This image system may be rotated from the central
inertial system by ordered angular rotations about one
or more specified axes. Any inertial vector available
in ·the data may be selected as the base view vector,
i.e., vector along the line of sight of the VISTA
"camera" taking the motion picture, and the appropriate
angular rotations will be automatically generated. Additional rotations from the selected vector may be applied providing the capability of viewing the central
system from any desired vantage point. In Figure 2
four views of the earth and the OGO spacecraft are
shown for the same portion of the orbit.
+
Models
The geometry or shape of a non-spherical body is'
entered as a set of X, Y, Z points where each point
describes the intersection of two or more lines or the
intersection of a line and a surface. In order to reduce
the complexity for intricate bodies, these points are
numbered and plottable lines and body surfaces (polygon loops) are specified in terms of these numbers.
When a body composed of hinged parts (e.g., the solar
arrays on the OGO), requires that these parts vary
with respect to each other then the points representing
the "components" are grouped together. Several bodies
may be introduced to the system in terms of points,
lines, loops and components and projected simultane-
Ir-I_ _ _ _ _ _ _ _...;12
-----;:-:::-:7
,,/
1
I
I
~--FIO~--~'--------____~x_
:I
'
I
I
:5
:8
_~---- ---:::.J
I
~+y
4
14
13
Figure 3-Partial aGO
This type of body description was a good balance
between the ease of introduction of bodies into the
computer (e.g., from scaled engineering drawings) and
the ease of operation and projection in an internal
computing sense. An interesting feature of this method
is the ability to pass vectors ( arrows) through the
vehicle representative of such quantities as the magnetic
field through which the vehicle is passing. Further, since
the spacecraft is originally in alignment with the inertial axes, the rotation matrices to orient the spacecraft p'roperly can be directly applied.
The earth as a spherical body is located at the center
of the inertial coordinate system. A mapping o~ the
shoreline features of the earth's surface is an additional
input to the system consisting of approximately 8000
vectors. Optionally calculated and added to this mapping
set are approximately 2500 vectors defining lines of
longitude and latitude. (Samples of this representation
of the earth are shown in Figure 2). The rotation of
the earth in the VISTA model is driven by time as
taken from the orbit data. The relative size and shape
of the earth-spacecraft system is in part determined by
the spacecraft position vector (magnitude) and in part
by the location of view of the entire system.
62
Fall Joint Computer .Conference, 1967
In cases where it is desirable to include the moon
or other major planets in the view, as with lunar orbits
or approaches, these bodies are introduced into the
system as spheres with appropriate surface mapping
features. Proper position and orientation for these
"special" bodies is achieved by utilizing ephemeris
information and interpolating with the spacecraft time.
Hidden lines
As previously mentioned, one problem which had
to be solved for the general case in order to achieve
the desired effect was that of the hidden Jines or occultation. This is a visibility determination; therefore,
the selection of valid plottable line segments in the
image coordinate system is performed last. All shoreline data as well as meridians, etc., are tested and
those with negative Z values relative to the sphere center are immediately rejected. In this sense, spheres on
which large amounts of data lie are handled in a some- .
what different manner than the general manner applied to rectilinear figures. In the latter case, all lines
associated with these figures that intersect others are
broken into separate segments such that no two line
segments intersect on the image plane. Examining
the relationships of this new set of line segments
and the body surface loops is sufficient for determining
valid lines. A line segment is' invalid if its midpoint
falls behind and inside some loop; otherwise, it will
be plotted.
This test for line validity is accomplished in two
separate steps. The first is the "inside," "outside" determination; the second, the "front" or "back." Two
different algorithms have been used for the first testboth successfully. Both solutions rely on lines being
constructed on the image plane from the point to be
tested (line midpoint) to each vertex of the particular
polygon loop forming a set of triangles. One method
computes and sums the interior angles about the test
point. If the sum is equal to 360 0 , the point lies inside the polygon and may not be plotted. The other
method computes in order the triangular. areas. A
change in sign in the area of any triangle determines
that the point lies outside the polygon and will be
plotted.
The second and final test for line valid~ty is accomplished by constructing a line parallel to the view vector
from the test point to the loop plane. If the point of
intersection has a larger Z value than the test point
itself, the point lies behind the plane and will not be
plotted. Several optimization techniques are employed
which effectively reduce needless validity testing. One
such technique first examines minimum and maximum
component or body values projected on the image plane
and avoids body to body occultation testing when appropriate.
Dynamic control
All system parameters can be modified from the
computer operator console as the system is running. In
addition, selected parameters (view, zoom) may be assigned to continuous alteration on a frame by frame
basis and controlled by the computer sense switches.
Thus additional bodies may be introduced to the system
and current ones modified. In this dynamic' fashion,
spacecraft .and booster separation may be performed
with relative ease. All transitions between views are
made smoothly so that no discontinuity is noticed when
the film is being projected.
Future applications
VISTA or VISTA-like computer techniques have
several obvious applications, and, with some imagination~ several not so obvious extensions. Two notable
applications in space research are for manned spaceflights and for a galactic probe.
for manned spaceflight, 'VISTA, modified for realtime processing, would allow ground based observers
to "See" docking maneuvers, rendezvous, or even a
lunar .touchdown. For these applications the user's
facility' for controlling the field of view would enable
the viewer to observe the surrounding environment
from any desired vantage point. The value of a viewing capability in rapid detection and analysis of anomalies in spacecraftinotion in immeasurable.
Another application of VISTA would be the display
of the orbit of a galactic probe. To show such an orbit
the coordinate system used could be heliocentric (sun
centered) rather than geocentric (earth centered). The
system view chosen could be approximately normal to
the planetary orbital planes. In viewing a motion picture
of such an orbit not only would a time compression
occur (orbital period measured in years, viewing time
in minutes) but the relative locations of planets to the
spacecraft and their influence could readily be seen
and appreciated.
A more down to earth application of an extended
VISTA is in air traffic control. The motion depicted
on a CRT and the change of reference capabilities could
significantly augment the controller-radar system. As
an example the center of the coordinate system. (radar)
for a controller would normally be the tower. However,
if any doubt arose concerning the vectoring of two
aircraft the view of the controller could immediately
be changed for better definition of the situation. If the
same radar information could be fed to hybrid computers aboard each aircraft and viewed there, the cen-
VISTA-Computed Motion Pictures for Space Research
ter of the coordinate system could be the individual aircraft and the pilot could "see" what was in his vicinity
as well as the directions of travel. Possible, yes-practical is another question.
SUMMARY
The VISTA system is designed to aid the space science
analysis effort by preparing motion pictures which are
realistic representations of the desired situation. This
type of visual presentation permits a rapid correlation
and intuitive understanding of the relationships of
dynamic bodies and subjects all data to a more rapid
and comprehensive analysis in a manner not available
through reading lists of numbers or even plots of some
particular parameter.
ACKNOWLEDGMENTS
Many thanks are expressed to Michael Mahoney of
Goddard Space Flight Center for his original concepts
and to Joel Erdwinn of Computer Sciences Corporation for his "hidden line algorithm" suggestions.
63
REFERENCES
F H HARLOW J P SHANNON J E WELCH
Science 149 1092 1965
B. R. GROVES Science 155 1662 1967
K C KNOWLTON Science 150 1116 1965
R A WEISS Journal of the ACM 13 194 1966
E E ZAJAC Journal of the ACM 7 169 1964
Edited by F F KUO J F KAISER
System analysis by digital computer
John Wiley and Sons, Inc chap 11 p 375 New York
New York 1966
R A SIDERS
Computer graphics
American Management Association chap 11 p 148
New York 1966
2
M MAHONEY J QUANN
Visual presentation of the motion and orientation of an
orbiting spacecraft (aGO)
NASA TN D-2918 1965
3
G H LUDWIG
The orbiting geophysical observations
NASA TN 0-2646 1965
Current status of large scale integration technology
by RICHARD L. PETRITZ
Texas Instruments Incorporated
Dallas, Texas
that will result from large scale integration technology.
The principal distinction between an IC and IEC is
that the latter is the result of interconnecting circuits
within the structure, whereas an IC is the result of
interconnecting devices within the structure. Figure I
shows the distinction between device, integrated circuit, and integrated electronic component.
I. INTRODUCTION
Considerable progress has been made in large scale
il}tegration technology during the past year. Many
of the goals, which were theoretical assumptions last
year, are now well along the way to reality. Accomplishments range from basic materials processing
improvements to systems architecture innovations.
While this paper will concentrate on large scale integration technology achievements, we shall also
focus some attention on progress in significant related areas.
The electronics industry has been relatively open
with respect to large scale integration (LSI) investigations, and much of the work has been, and continues to be, presented at technical meetings and
published in the literature. In addition, the U.S.
Air Force has under sponsorship a major program!
with three contractors 2 .:3.4 to develop LSI technology.
We shall make frequent reference to these reports
and to the author's papers of 1965 5 and 1966. 6
Reviewing the terminology which the author used
in previous papers,5.6 we see LSI as a system of technologies underlying the products which are called
IECs (integrated electronic components). * The distinction between "technology" and "product" is
summar; zed in Table I for three generations of solidstate electronics. Table I shows "transistor" as the
surviving product terminology of the second generation of electronics technology, and lists some of the
technologies. Similarly, "integrated circuits" is the
surviving product terminology of the third generation.
As discussed in Ref. 6 a distinction should be made
between "integrated circuits" (lC) and the produ.cts,
namely, "integrated electronic components," (ICE)
IEC
INTEGRATED ELECTRONIC COMPONENT
Ie
INTEGRATED CIRCUIT
DEVICE
Figure I - Pictorial view of integrated electronic component
(I Ee), integrated circuit (I e), and semiconductor device
Another term that is being used to some extent is
MSI (medium scale integration) along with LSI.
When used in the context of complexity level MSI is
generally related to complexity levels of 10-100 circuits, while LSI refers to complexity levels greater
than 100 circuits.
At least three well-defined LSI technologies are
under development:
LSI chip technology
LS I hybrid technology
LSI full-slice technology
*In reference 6, lEe was interpreted to mean "integrated equipment component." Because of the broad acceptance of the term
"integrated electronics" as the generic term of the industry in
place of "microelectronics," we now prefer lEe to mean "integrated electronic component." Another term under consideration is
integrated electronic device (I ED); however, we shall use I Ee in
this paper.
65
66
Fall Joint Computer Conference, 1967
Table I.
Generation of
Electronics
2nd
Technology - Producta
Technology TerminolOlY
grown JIIDCUon
Product TermioolOl)'
Tr&D8iltor
alloy
mesa
planar
bipolar
MOB
3rd
Integrated Circuit (lC)
monolithic
hybrid
thin film
thick film
4th
LSI technology
Integrated Electronic
Component (lEC)
chip• 100% yield over chip area
• fixed pattern metaUzation
• customized wiring
• single or few chips per package
full sllce• fixed pattern metalization
• discretionary wiring for
yield enhancement.
• customl:ted wiring
• redundancy
hybrld• interconnection of chlpa through
use of film technologies
• customized wiring
The basic characteristics of these technologies are
summarized in Table I, and Figure 2 illustrates
them.
CH I P TECHNOlOGY
HYBRID TECHNQOGY
FUll- SLICE TECHNOlOGY
term customized wiring (metalization) refers to a customized metalization pattern for a specific product.
Looking to the manufacturing process, we need to
recognize two major technologies, fixed pattern metalization, and discretionary wiring (pattern) metalization. The fixed pattern process uses the same metalization pattern from slice to slice in the manufacture of a
specific product, whether it be a standard or a custom product. For a custom product, the fixed pattern
metalization differs from product to product, but for
the manufacture of a specific' product it remains the
same.
Discretionary-wiring technology is a method of
enhancing yield and' provides different metalization
patterns for each slice in the manufacturing process,
whether the product be standard or custom. A particular advantage or the discretionary-wiring technology
is that for many applications it accomplishes the customized-wiring function with relative simplicity. However, in other applications this is not necessarily the
case.
In summary, both standard and custom products
can be manufactured with a fixed-pattern technology
or with a discretionary-wiring technology, or a combination of both. In order to abbreviate terminology,
we have defined on Table I chip technology to imply
fixed pattern metalization, and full-slice technology
to employ both fixed pattern metalization and discretionary wiring. As will be discussed later, the relative emphasis of fixed versus discretionary metalization varies for different full-slice technology lEes.
Progress will be reviewed in each of these technologies as follows:
II LSI Bipolar Chip Technology
III LSI Full-Slice Technology
IV LSI MOS Technology
V LSI Hybrid Technology
Section VI develops the considerations of complexity
(level of integration) versus cost, performance, and
reliability for LSI technologies.
I I.
10-250 ckts/chip
Single or few chips/pkg
100% yield
FiXed pattern metallization
Customized wiring
10 - 250 ckts/chip
4 - 20 chips/pkg
40 - 5,000 ckts/pkg
Thin - film interconnect
Customized wiring
100-10, (XX) ckts/slice
Redundancy
Discretionary wiring
Fixed pattern metallization
Customized wiring
Figure 2 - Pictorial view of large scale integration technologies.
The pictures represent compamble sizes
Because of confusion between the terms fixed
pattern metalization, discretionary wiring and customized wiring, and the need for preciseness in their
meaning, we will review these and related concepts.
First let us emphasize that we are discussing two
classes of products, standard .and custom. The
LSI bipolar chip technology
A. Review of Status of 1967 IC and
IEC Production Technology
The monolithic integrated circuit technology processes slices of silicon such as that shown in Figure
3a. The slice has been processed through metalization
and is ready for probing. Each small area (chip or bar)
on the wafer is probed, and the good and bad units
are marked accordingly. The slice is then scribed into
chips and the good chips in turn are assembled into
packages and tested. Figure 3b shows a sequence of
the silicon chip being assembled into a plastic package.
Current Status of Large Scale Integration Technology
Ib)
la)
Figure 3 - a) Semiconductor slice showing metalized integrated
circuit chip areas. The slice is ready for probing and then scribing
into chips. (b) From left to right, fourteen lead metal frame without
integrated circuit chip; the chip mounted in the lead frame; the
plastic encapsulation has occurred; the completed integrated
circuit in a plastic package
Table II is a listing of some of the key characteristics of the Series 54 T2L line of integrated circuits.
The important points are the following: bar (chip)
sizes average 2600 mil 2; the devices per bar average
25; the area per device averages 104 mil2; the average
number of circuits per package is 4; and the average
area per circuit is 620 miI2. These averages include the
effect of bonding pads. Line widths of 0.2 mil and
spacings of 0.2 mil are used.
Table II.
Device
No.
These data summarize modern slice processing
technology. Integrated circuits of 1962-63 vintage
would show one or two circuits per bar and the bars
would be considerably larger. For example the early
Series 51 designs used bar sizes 14,000 mil 2 (70 mil x
200 mil) and contained one to two circuits. Line
widths of 1 mil and spacings of 1 mil were used.
The industry recognized at least three years ago
that four circuits were about all that could be economically placed in a single package if all gate (circuit) leads needed to be accessible from the terminals.
Four circuits require 16 terminals, using 4 terminals
per circuit. At the same time it was also reasonably
clear that greater economics were ahead if more circuit
function could be incorporated into a single package.
Thus the direction was taken toward interconnecting
circuits within the chip, and this was the genesis of
the integrated electronic component product line.
Table III lists the Series 54 T2L IECs that are now
in production. Note that the average bar size is 7000
miI2; the average devices per bar is 124; the average
area per device is 56 mil2; the average circuits per bar
is 25; and the average area per circuit function is 280
mil2. By comparing these averages with those of Table
II it is apparent that IECs are more effective than I Cs
in utilizing the silicon area. Note the trend to larger
bar sizes, with several approaching 10,000 mil2.
2
Series 54/74 T L Integrated Circuits (ICs)
Circuit Type
SN5400 Quad -
2 input gate
Bar Size
(mn 2 )
Bar Size
(mi12)
No. of
Devices
Area/Device
2
(mn )
No. of
Circuits
Area/Circuit
(mil2)
50 x 60
3000
36
83
4
750
50 x 60
3000
27
110
3
1000
45 x 45
2025
18
125
2
1012
40x 40
1600
9
180
1
1600
50 x 50
2500
22
114
2
1250
SN5450 Dual 2-wide 2 input AND-OR-Inv. E
50 x 55
2750
24
115
6
460
SN5451
50 x 55
2750
24
115
6
460
SN5453 4-wide 2 inIAlt AND-OR-Inv. E
50 x 55
2750
18
153
5
550
SN5454 4-wide 2 inIAlt AND-OR-Inv.
50 x 55
2750
18
153
5
550
SN5460 Dual -
35 x 40
1400
6
230
2
700
SN5470 J-K Flip-Flop
55 x 60
3300
56
57
8
400
SN5472
55 x 60
--
80
-6
535
--
SN5410 Triple SN5420 Dual -
3 input gate
4 input gate
SN5430 Single -
8 inIAlt gate
SN5440 Power dual -
4 input gate
Dual 2-wide 2 input AND-OR-Inv.
4 input Expander
J-K Flip-Flop Master Slave
TOTAL
Average
. . . . .
. .
67
40
-
31,125
298
-
2600
25
3300
-
104
50
4.2
620
68
Fall Joint Computer Conference, 1967
Table III.
Series 54/74 T2L Integrated Electronic Components (IECs)
No. of
Devices"
Area/Device
2
(mn )
Equivalent Gate
3600
50
72
17
212
60 x 120
7200
120
60
24
300
Gated full adder
65 x 65
4225
69
61
14
301
SN5482
2- Bit full adder
65 x 65
4225
83
51
21
200
SN5490
BCD decade counter
50 x 115
5750
102
56
18
320
SN5491
8-Bit shift register
55 x 110
6050
143
42
35
173
SN5492
Divide by 12 counter
50 x 115
5750
96
60
17
340
SN5493
Divide by 16 counter
50 x 115
5750
96
60
17
340
SN5494
Dual P.I., S.O. 4-Bit S.R.
70 x 110
7700
125
62
20
385
SN5496
P.I., S.I., P.O. 5-Bit S.R.
70 x 140
9800
158
62
24
450
SN1286
P. L. Serial 5- Bit ring counter
70 x 140
9800
169
58
30
327
SN1287
Dual P. L. Count to Zero 5-Bit
R.C.
70 x 110
7700
153
50
33
230
Dual P. L. S. S., 5-Bit R. C.
70 x 140
9800
191
51
30
327
40
180
Bar Size
2
(mn )
Device
Function
SN5441
BCD to Decimal Decoder/Driver
60 x 60
SN5475
Quad latch
SN5480
SN1288
Bar Area
=
0.1
0.01
0
10
20
30
50
UN ITS OF AREA
Figure 8 - Plot of yield versus area (relative)
This defines a straight line function on semi-log paper
as shown in Figure 8. The actual data followed a line
of the general shape shown by the data line of the
figure. Because of proprietary considerations, the
abscissa of Figure 8 is relative - not actual area. The
important conclusion established by this study is that
yield holds up for larger areas than simple theory
predicts. In a qualitative sense we interpret that good
units tend to cluster, and, likewise, defects tend to
cluster, Examples in Figure 7 show this quite graphically; there are relatively large areas free of defects,
and areas where defects cluster. This is particularly
so around the slice periphery.
This study of yield versus area has led us to the conclusion that the LSI chip technology has by no means
exhausted itself at the areas of 10,000 miI2 represented
in Table III. Using the data obtained in this study,
along with some reasonable forecasting of yield improvement that will take place during the next few
years, we forecast that chip technology will be useful
for areas as large as ~ in. x ~ in. = 62,500 mil2.
The other major factor that governs complexity
level on a chip is the area required for a device.
We have seen over the past five years significant improvements in optical technology and we forecast that
improvements will continue to be made. For further
discussion of optical factors the reader is referred to
the discussion of Figure 21 in Ref. 6.
The combined effect of improved yield such that
larger chip areas will be useful, along with the smaller
areas required for circuits, leads us to forecast the
following PL complexity levels for the 1970's:
Logic:
250 gates/chip
Memory: 500 bits/chip
Texas Instruments has a program to reach these
complexity levels by an extension of the Series 54
Figure 9 - Family of plug-in IC and IEC packages
In summary, yield has improved to where, in 1967,
IECs of 10,000 mil2 containing 35-40 T2L logic circuits are now in or near production. Designs aimed
for production in the seventies should comprehend
chips containing up to 250 logic gates or 500 memory
bits. Packages are under development as shown in
Figure 9 with up to 50 pins per package to accommodate these chips.
C. Custom products versus standard products
The question of custom products versus standard
products is not a new one to the semiconductor industry. At the device level many custom transistors
are manufactured exclusively for a single customer.
Integrated circuits in their early phases attempted
to solve the custom-product problem by a master
slice with mixtures of transistors, diodes, and resistors which could be interconnected by specific metalization patterns to provide a specific circuit for a
customer. While the master slice has proved effective
for varying a basic circuit, it has not been used for a
broad range of circuits. Instead, the problem of cus-
72
Fall Joint Computer Conference, 1967
tom versus standard products has been handled
differently. Custom lines have been designed, developed, and placed into production for large customers whose total business warranted the expense of
this approach. Often these custom developments have
led to standard product lines patterned after them,
and a large part of the industry requirements has
been satisfied by standard product lines.
However, we must not conclude that a similar
course will necessarily follow for IECs. A useful
figure for analysis of the question was recently published by IBM.B Figure 10 plots the number ofuniqll:e
parts versus level of complexity (level of integration)
for Central Processing Units (CPUs) of 1 K, 10 K,
and 100 K circuits, respectively. We note that for
complexity levels of 3-4 ·circuits the number of unique
parts is relatively small. This is a key reason for the
wide acceptance of standard product integrated circuits.
Complexity levels from 10-250 circuits pose the
most difficult part-number problem, since high numbers of unique parts imply relatively small usage of the
corresponding parts.
1(0) 100, (o)-CI RCUIT CPU
10, (o)-CI RCUIT
PU
en
~
0::
< 100
Q.
L£J
~
Z
:::;)
LIo..
0
0::
L£J
GO
~
2
10
l~lL-------~lO--------~lOO~------~lOOO~~
LEVEL OF INTEGRATION
Figure 10- Plot of number of unique parts versus level of
integration
Thus we conclude that an efficient, low-cost, quickturnaround method will be needed to supply custom
IECs in the complexity range of 10-250 circuits.
There are many different approaches - but all appear
to focus on three basic premises: the first is that a good
computer-aided design capability be established so
that low-cost masks can be designed in a short time.
Secondly, automatic artwork generation and mask
making are required. Finally, some form of masterslice technology is needed to lessen the .processing
expense and to shorten the turnaround time.
Fairchild has described a master-slice approach for
bipolar (DTL) technology. Master chips of 8800
mil2, containing 32 three-input NAND gates, have.
been defined. One can expect these chip areas to
increase in size to allow for greater complexity levels.
RCA has chosen ECL as its basic approach for
LSI logic technology. Under their Air Force contract3 RCA has set goals of chip sizes to reach the
~" x ~" level. The gate areas will approach the 250
mil 2 size - thus complexity levels up to 250 logic
gates per chip are the goal. Their progress reports 3
show working arrays of 23,000 miJ2 containing 125
transistors and 90 resistors.
Texas Instruments has defined a master-slice
approach as a companion approach to the standard
IC and IEC Series 54 chip technology. Table IV
summarizes this program. Since this program is representative of the custom-wired LSI chip-technology
programs which industry is developing, we shall detail
some of its aspects.
Figure 11 shows an area 240 x 240 mil (57,600
miJ2) providing 256 gates, for an average area/gate of
225 miJ2. Note that a 60 x 60 miJ2 unit area is stepped
across the slice. Master slice No. 1 (Figure 12) has
16 gates in the 60 x 60 mil 2 area. There are 4 input
gates, 8 internal/expander gates, and 4 output gates.
The devices are interconnected to form these circuits with the first level of metalization as shown
in Figure 12a; pads are shown for interconnecting
these circuits into specific IECs. The mask for feedthrough holes is shown in Figure 12b, the secondlevel metal in Figure 12c, and the resulting function
in Figure 12d. The design rules for this program are
summarized in Table IV.
The three approaches outlined above, FairchildDTL, RCA-ECL, and TI-T2L, while varying in detail, have all taken the same basic approach; namely,
a master slice which has all diffusions made as the
standard item. Personality or customization is imparted through first- and second-level metalization.
The key technological advances required for a successful customized LSI chip technology include: improvement of yield such that chip areas 30-60 K
miJ2 can be economically used, two-level metalization
technology is required for crossover capability, and
finally computer-aided design capability must be
developed so that a customer's logic equations can be
translated directly into a mask layout for the interconnection wiring.
Current Status of Large Scale Integration Technology
Table IV.
I.
73
Custom Series 54/74 IEC Prop':am
P!!rJe!e:
1. To supply custom digital logic arrays in the 15 to 250 gate complexity
range for low cost, low volume requirements.
2. 4-week cycle Ume from receipt of customer order to shipment of
prototypes.
IT.
Approach:
1. Master slice with fixed second-level lead patterns interconnecting
from 2 to 16 bars.
2. Series 54/74 circuits.
3. 14, 16, 24 and 50 pin dual-in-line headers.
ITI.
Schedule:
Weeks
1. Array logic design and mask design
1
2. Photomasks from photolab
1
3. Material processing and assembly
1
4. Prototype testing and evaluation
1
Total
IV.
Design Rules:
Package
III.
.·4
Bars
Gates
Gates/Pin
Min.
Max.
Min.
Max.
Min.
Max.
14
1
3
15
45
1.07
3.2
16
1
3
15
45
0.94
2.8
24
2
8
30
120
1.25
5.0
50
8
16
120
240
2.40
4.8
LSI full-slice technology
We at Texas Instruments feel that the full potential
of semiconductor technology for integrated electronics will be realized only when the entire semiconductor slice constitutes the packaged· product.
Arguments for this position include: (1) the full slice
is the natural working unit of semiconductor technology, and (2) very high complexity levels (1-5 K circuits) are available directly on the slice of silicon.·
To this end we have a program, in part under Air
Force sponsorship,2 to develop LSI full-slice technology for IECs. Recognizing the limitations of yield,
this program has sought methods for producing working electronic functions which did not require 100%
yield over the full silicon slice; two main avenues have
been taken:
.
( 1) Discretionary wiring
(2) Redundancy
Fall Joint Computer Conference, .1967
74
.J
I I
.-
L
J~ ~ ~ ~ [
J~ ~ ~ ~ [
240
MILS
GATES
GATES
GATES
GATES
. GATES
GATES
GATES
GATES
] [±] ~ ~ [±] [
T·OOM~ ~ ~ ~ ~[
·,1,
60MILS
GATES
GATES
GATES
GATES
GATES
GATES
GATES
,.! I
f=
III
~
i
240 MILS
Figure It-Chip areas defined for custom Series
54 IEC program
44~
INPUT
GATE
INTERNAL
GATE OR
EXPANDER
OUTPUT
GATE
.
•
•
~
•
Ibl FEED lHRU
lal lEVEL 1
four main parts: a general-purpose computer, an active
memory (Read-Write and Read-Only), a phase shift
computer, and a video integrator. The characteristics
of these four parts and their implementation in terms
of LSI technology are summarized in Table V. More
detailed characteristics· of the logic arrays that have
been defined at this writing are summarized in Table
VI. Twelve logic functions are listed, with the number
of gates per function, the number of flip-flops, and the
number of equivalent gates (where one flip-flop is
equivalent to four gates) per function. We see that
the circuit complexity level varies from 134 to 262,
with 193 the average. Ten of the twel~/e functions are
used only once, the other two part-numbers having
high usage. This illustrates the need for. customized
wiring at this· level of circuit complexity and confirms the conclusion of Figure 8.
The program to develop the full-slice LSI technology includes work aimed at standard-product IECs
and ·custom-product lEes. The Read-Write memory
has served as the vehicle to develop discretionarywiring technology for standard-product lEes with
complexity levels greater than 1000 circuits/slice.
The Read-Only memory has provided a vehicle in
which both customized wiring and discretionary wiring are employed together in a relatively simple manner. The logic portion of the computer has served as
the vehicle for developing the technology for cus~
tomized and discretionary wiring of a more sophisticated nature than memory. We shall review both the
memory and the logic programs.
A. Read-write memory; standard-product lEes
•
•
•
•
.
1-
IcllEVEl2
I
~
INTERNAL
~
EXTERNAL·{~
Idl FlI4CTION PERFORMED
Figure 12 - (a) .Basic circuits for custom· Series 54 IEC program;
(b) feed-through mask; (c) second-level metalization mask; (d)
function to be performed
The concept of discretionary wiring is one of probing to identify the good or useful circuit elements on
the slice and then interconnecting them to make the
final function. Redundancy has been incorporated into
the design philosophy of the memory program so that
discretionary wiring has been reduced to that of a
-single mask per slice.
The Air Force-Texas Instruments LSI program
calls for the development and construction of a research vehicle, which is a computer for a terrainfollowing radar system. This computer consists of
The Read-Write memory offers a high-volume application for standard-product lEes. It also affords
the opportunity for incorporating complexity levels
of the 1-5 K bits per package while maintaining a
relatively small number of pins on a package. This is
accomplished by doing address decoding on the slice.
Figure 13 plots pin connections versus cell complexity for memory. The various lines show how incorporation of address decoding and/or other functions on the slice keeps the number of external pin
connections to relatively small numbers; for example,
5000 bits of word-organized memory can be accessed
in a 150-pin package.
The basic memory· slice is shown in Figure 14.
Note that 60 x 64 = 3840 potential storage bits are
provided, with up to 60 word drivers and decoding
gates. The basic circuitry is illustrated in Figure 15a,
the storage cell being two cross-connected multiemitter (T2L) transistors and two load resistors. The
use pf redundancy allows for 1J of 16 bits in each
Current Status of Large Scale Integration Technology
Table V.
Research Vehicle-Computer for Terrain-Following Radar
Part
GENERAL
PURPOSE
COMPUTER
Characteristics
16-bit word length
2-MHz clock rate
34 logic arrays of 21 wiring configurations (bl-b21) of
usage and complexity shown in Table VI. Total, 5519
gates, 400 flip-flops; average gates/pin = 2.4.
MEMORY
Read-Only, 512 words of 32 bits, non-volatile, store.s
program and essential parameters.
Read-Write, 128 words of 32 bits, volatile, stores radar
data being processed.
System access time, 2
p./sec.
Slice Technology:
16 Read-Only arrays, 1024 bits/array
4 Read-Write arrays, 1024 bits/array
2 Sense amplifiers, bit driver arrays, 32 SA/array,
32 bit drivers/array
9 Logic arrays for decoding and address register,
average complexity 200 gates/array
31 Arrays for memory
PHASE SHIFT
COMPUTER
VIDEO INTEGRATOR
14 Type b22 arrays (Table VI)
1 Type b23 array (Table VI)
6 Logic arrays b24-b29 (Table VI)
5 Memory arrays
,75
76
Fall Joint Computer
Conf~rence,
Table VL
1967
Logic Partitioning for LSI Computer
Logic
Function
No. of
Gates
No. of
rUp-Flops
b-01
138
10
178
16
b-02
148
20
228
1
b-03
139
27
247
1
b-04
158
26
262
1
b-22
80
28
192
14
b-23
162
14
218
1
b-24
124
22
212
1
b-25
66
26
170
1
b-26
49
24
145
1
b-27
62
27
170
1
b-28
38
24
134
1
b-29
68
24
--
164
-1
1232
272
2320
40
103
23
193
Total
Average
section of a column to be used. Thus actual word
lengths up to 52 bits may be employed. The original
design of the Air Force contract called for 32 words
of 52 bits, or 1664 bits per slice. Because of a change
in systems design the present slice utilizes 32 words
of 32 bits, or 1024 bits per slice as noted in Table V.
Figure 15b shows the layout of the storage bits, the
resistors on the right, the transistors on the left; note
that only 127 mil2 is required per bit. Figure 15c is
. an expanded view of the slice before metalization;
the decoder and word drivers are at the top and the
storage bits are at the bottom. Figure 15d is an ex-
Equiv. Gates t
1-FF = 4 Gates
Usage
panded view after first level metalization. Vertical
word lines which interconnect 16 bits in a column are
put down as part of the first level metalization. Redundancy is so employed that only 13 of the 16 bits
are required. In the next step a thin insulating layer
of Si02 is deposited and feed-throughs opened. Next,
metal is evaporated or sputtered over the entire slice,
.and selectively removed so that feed~throughs are
brought from the first level to the top of the slice.
All masking operations through this point have been
fixed patterns. No testing and no discretionary masks
have been involved.
Currel"t Status of Large Scale Integration Technology
I
DeCalER-WCRD
DRIVER!-I- - - W O f I ) I - - -
(a)
I, 000
L-..--'-_..L.-""""-~-'-
50
77
(b)
_ _----IL....-_-'-_ __ _
60 70 80 90 100
PINS
150
200
300
Figure 13 - Plot of number of memory cells versus number of pins
on package for different active memory organizations. The various
curves show the reduction in number of pins required by incorporating address-decoding and other functions on slice
2nd LEVEL DECODE GATES
AND WORD DRIVES
16 BIT COLUMNS
II 1
16 BIT COLUMNS
II I
16 BIT COLUMNS
It
16 BIT COLUMNS
I.·
II I
0
I
0
BIT
LINE
CONTACTS
~-------wo~os~
Figure 14 - Organization and layout of semiconductor active
memory slice.
(c)
(d)
Figure IS-(a) Memory circuits; (b) layout of storage cells, two
transistors and two resistors constitute a cell; (c) view of unmetaIized memory slice showing decoder-word drivers (top), cells
(bottom); d) metalized memory slice decoder-word drivers (top),
cells (bottom); and interconnections (middle)
At thfs stage the slice is probed and the good and
bad cells are identified. Figure 16a is a map of a typical
slice. From this information a single discretionary
mask is designed by a computer, a pattern of which is
shown in Figure 16b. Note the relative simplicity of
the wiring pattern.
This mask and associated metalization accomplish
four discretionary functions. The long horizontal
lines pick up 13 bits of the 16 bits in each segment of
the word line. Within the horizontal areas between the
16-bit groups, short vertical (or nearly so) lines connect groups of 13-bit word lines. At the top word lines
are connected to drivers. Finally. the word and bit
lines are connected to pads in the slice edge. Note that
these four discretionary functions are accomplished
by . a single level of metalization even though both
horizontal and vertical runs are made. This is accomplished by capitalizing on the regularity of a memory matrix, by employing redundancy, and by some
good design work. An article describing this memory
78
Fall Joint Computer Conference, 1967
ON - SLICE WORD DRIVERS AND DECODES
,
I
I
:
I
SUP'PLY
,
I
I
I
I
LI
I
I
/
'SECOND
LEVEL
BIT
I NTERCONNECTI ON AREA
LlN\
Figure 17 - Layout of R~ad-Only active memory
Figure 16-(a) Map of memory slice showing bad (dark) and good'
cells (b) Discretionary mask drawing for second-level metalization
of memory slice
The first-level metalization is again a fixed pattern
(the same for all slices) and serves to connect dc power
to the collectors, and word lines to bases for 16-bit
development has been published,9 and detailed ingroups, as shown in Figure 17. The second-level
formation is given in the contract reports. 2
metalization accomplishes the customized wiring by
connecting or not connecting to appropriate emitters
The principal technical development required is a
according to the customer's software program (horitwo-level metalization technology ~apable of high
zontal lines of Figure' 17). The' second-level metalizayield over a large area. Although this requirement is
tion .also accomplishes the discretionary wiring by
similar to that for chip IECs discussed above, it is
connecting bit lines only to transistors which have
more difficult because larger areas are involved.
been determined to be good during earlier testing.
The
second-level metal also connects, as in the case
B. Customized wiring and discretionary wiring
o(
the
Read-Write memory , 13':'bit word groups . tofor read-only memory
gether, word drivers to appropriate word lines, and
word and bit lines to pads on the slice edge.
The basic techniques described above for Read-'
Thus Read-Only memory constitutes a simple but
Write memory are extendible to Read-Only memory.
In the Air Force program the same basic slice is used
most important example where customized wiring and
for the Read-Only memory as for the Read-Write . discretionary wiring are combined.
memory. The storage bit is simply a transistor of the
The Air Force Computer will use Read-Only membasic cell shown in Figure 17. The two states are
ory to store the computer program and certain tables
achieved by either permanently connecting the transis,;.
of functions. The Read-Write memory will store only
tor into the matrix, or not.
data. The volatility problem is avoided since the loss
Current Status of Large Scale Integration Technology
of power only loses signal data, the Read-Only memory being non-volatile.
c.
New memory functions
An active-memory matrix is a function which has
not been used extensively in digital systems because
of the circuit costs. However, because of the unique
features of memory circuits in arrays, the cost of the
storage cell may be made a fraction of the cost of a
single gate. Scratchpad-memory arrays are now finding numerous applications and batch processing of
memories is being investigated. In the Air Force LSI
computer system, active-memory arrays will also be
used to implement the serial delay function in the
video integrator. For this application two logic arrays
are required to control three active-memory arrays.
This unit will provide the function equivalent to six
608-stage shift registers. A block diagram of this serial
delay function is shown in Figure 18.
ACTIVE MEMORY OF 608 WORDS 148 BITS
18 6-BIT GROUPS)
ON 3 SLICES
79
2.5-5 K bits of bipolar memory per slice in the years
ahead, and even higher for MOS.
D. Logic program for complexity levels
to 250 gates
The Air Force program at TI has a goal of providing customized wiring for logic in addition to the use of
discretionary wiring for yield enhancement. Complexity levels of 100-250 logic gates are the program
goals. To this end two basic slice types have been
defined for logic as shown in Figure 19 (the two memory slices are also shown). Slice (a) provides 881
T2L gates; the circuit and layout of the gate are shown
on Figure 20a and b, respectively. Figll~e 20c shows
the. metalized, circuit as a part of the entire slice of
Figure 20d. Slice (b) in Figure 19 is the slice to which
the logic partitioning of Table VI refers.
la) 881 GATES
Ib) 501 GATES
95 FlI P-FLOPS
' - - - _ 6-BIT WORDS SYNCHRONIZED AT 100 ns
Figure 18 - Block diagram of serial delay function active memory
The active memory approach to serial delay functions is more efficient than existing shift-register
functions because only the accessed word need dissipate power, and the rest of the memory may be held
at a minimum non-select condition. Shift-register
units, by comparison, must be active at all times. The
disadvantages of the memory approach are the complications and cost of the peripheral logic needed for
accumulation, serialization and address sequencing.
The minimum size for a serial delay memory is 2000
to 3000 bits.
Another memory function that can be implemented
in an active-memory matrix is that of a content-addressable (search) memory. This results because logic
can be incorporated in the storage bit.
The author is very optimistic about the use of LSI
full-slice technology for memory applications. While
our Air Force program goals are for 1024 bits of Read.;
Write or Read-Only memory, this number should go to
Ie) 3840 MEMORY CELLS
60 WORD DRIVERS
Id) 1«) SENSE AMPLIFIERS
Figure 19 - LSI basic slice types: (a) gates for log.c functions;
(b) gates and flip-flops for logic functions; (c) memory slice of
drivers and cells; (d) sense amplifier slice
The customized wiring requirement of the logic portion of the computer has already been discussed in
terms of Table VI, where the usage of different slices
is tabulated. Our study has shown that· the coupling
of customized wiring with discretionary wiring for
random logic requires three levels of metalization;
of these only the first-level metal is a fixed pattern.
The slice is probed after first-level. metal, and then
four discretionary masks are required for each slic~
to achieve second- and third-level metalization.
Development of this technology requires the de-velopment of routing software, low-cost rapid interconnection mask making, and three-level intercon.;
nection metalization technology. Considerable progress has been made in each of these areas and is
documented in the contract. rep'orts2 and publications. tO
80
Fall Joint Computer Conference, 1967
Vee
o 0 ..,
~
1~000~~---------------------------,--~
PARTITIONED AND 01 STRI BUTEO -........ •
CONTROL
'"V
81
Ii}.
~IJ
. fil
.
Ilmll·,
~
=
0
o ~~Io
I
I
I
I
I
I
1.000
(a)
.e
(b)
THIRD GENERATION MEDILM TO
lARGE SIZE MACHlht
e THIRD GENERATION MEDILM
SIZE MACHlht
A SECOND GENERATION MEDILM
SIZE MACHlht
100
SECOND GEhtRATION MEDILM
TO lARGE SIZE MACHlht
• SECOND GEhtRATlON MEDILM
SIZE MILITARY MACHlht
e:;)
• REGIONALAVERAGE
Ie)
10~~~L---~~----~--~~--------~
10
(d)
Figure 20-(a) Circuit diagram of LSI gate-this gate is functionally the same as the basic Series 54 gate; (b) layout of LSI gate;
(c) expanded view of LSI gate on semiconductor slice; (d) semiconductor slice containing 881 gates
E. Logic program for complexity levels
1000-5000 gates
Let us now discuss the prospects for logic function
products of very high complexity level (> 1000
circuits/slice). One important potential problem is the
pin-to-gate ratio. Figure 21 presents data3.11 from
three generations of CPUs that show a linear relationship between gates and pins. Assuming one could put
1000 gates on a slice of silicon, one would still have
the prospect of a 1000-pin package. This problem,
which relates to partitioning, has received study during the past few years. An important result presented
recently3.11 is summarized on Figure 21. The line titled
"partitioned and distributed control" shows that 1000
gates can be accessed with about 150 pins. This is
achieved by distributing the control function. In
terms of LSI technology this means incorporating
control circuitry on the slice of silicon.' This has an
analogy to the memory function, where by placing
address decoding (a control function) on the slice the
pin problem is also greatly alleviated (Figure 13).
It is the author's opinion that logic, as well as memory, will utilize the full-slice LSI technology approach for IECs of complexity greater than 1000
gates. However, much work must be done at the systems-architecture level to determine what these products will be. It is quite probable that sufficient regularity will need to be designed into the logic to assure
that some of the techniques that have been developed
in memory programs will be applicable to logic.
100
PINS
I, (XX)
1~ 000
Figure 21 - Plot of number of gates versus number of pin connections; the data points relate to the computers as listed in the
diagram; the dashed line shows the reduction in pin requirements
for partitioned and distributed control as compared with centralized
control
IV.
LSI MOS technology
A. Review of MOS program history through
development of ratio circuitry
It was recognized early in the MOS development
(3 to 4 years ago) that complementary structures (nand p-channel) could achieve considerably faster
switching speeds than single-channel structures.
C1 megohm
Internal with external trim
Reference Voltage
optional
Bipolar (Micro logic famiLogic Compatibility
lies of CCSL, fLL, R TfLL,
MWfLL, D7 fLL, T7fLL, and
CTL)
Code Format
Binary or BCD
0-70°C (Industrial)
Temperature Range
-55°C to +125°C (Aerospace)
D / A Conversion
Rate
Resolution
Accuracy
Selection of a conversion technique
DC to 50K words/sec:
8 to 10 Bits
±0.2% (full scale)
±O.l % (non-linearity)
The goal of the subsystem design was to satisfy the
stated specifications at a minimum cost to both the
manufacturer and user. Therefore the design economics
95
96
Fall Joint Computer Conference, 1967
must be considered first in the selection of a conversion scheme. The prerequisites for low cost for the
manufacturer are:
1. Batch fabrication
2. High volume
a. Minimum number of different chip types
b. Each component independent functionally and
individually saleable
3. High processing yield
4. Minimum amount of hand assembly work such
as lead bonding.
5. Capable of simple or automated testing.
The prerequisites for low cost to the user are:
1. Easy to understand and use
2. Minimum number of external components and
connections for assembly and test
3. Minimum number of device types to procure and
stock
4. Compatible with existing hardware
5. Flexible in design so may be adaptable to many
different applciations within the user's system(s)
and product lines.
The factors thus stated imply a system which utilizes
integrated circuits to the maximum extent permitted by
the existing semiconductor technology. Monolithic construction provides the means for low cost production
. and a large number of functions per package, thus
minimizing interconnections while enhancing system
reliability.
The subsystem specifications of speed, temperature
performance, and long-term stability could only be
satisifed by bipolar transistor design for both the linear
and digital portions of the circuit. Also, the logic levels
and power supply voltages required for other than
bipolar design would not be compatible with the majority of existing data equipment.
Preparatory to circuit design the known ADC and
DAC configurations were studied. l Those techniques
that would s~tisfy the subsystem performance specification and allow a major portion of the functions to be
monolithical1y integrated were cataloged for component
type and approximate count. A summary is tabulated
in Figure 1.
The choice of a D / A technique was limited to eitherswitched voltages/currents or switched resistors. Current switching was chosen because: (1) it is independent
of switch off-set voltages; (2) it is fast and may be
accomplished with a minimum of transient problems;
(3) control circuit isolation is easily accomplished;
( 4) mutual isolation of current sources and output is
easily accomplished.
The A/D techniques ranging from the ramp counter to cyclic, successive approximation, multi-compara-
DIA Techniques
R-2R
Weighted
Resistive VoItaoes or
Ladder Currents
(Binary
BCD
Octal)
AnoIoo
AID Techniques
Cyclic Cyclic
D/A
(X 2) (Charge Feedback
Divisiool (R-2R)
10
7
10
10
21
10
o
21
3
0
n Gain Amps(fast)
• Gain Amps(sbw)
• Ref Source
0
I
I
o
o
o
0
0
•
0
o
2
I
I
2
I
I
I
I
0
I
I
2
0
o
230
Precisbl Resistor
Precision OJpacitors
OJmporators
Laroe
I
I
Cascade
X2
(weiohted)
VORl)
20
Switches
D/A
~e:-
10
20
10
0
0
10
I
I
I
I
I
10
o
0
o
o
STORAGE
Capacitors
Figure I-Required component comparison for 10 bit converters
tor, ripple-through and parallel types were considered. 2•s
The choice was simplified by the following : the rampcounter types are too slow; multi-comparator, ripple
through and parallel types require excessive circuitry;
and the cyclic types require accurate voltage switching
in conjunction with large external capacitors. A D / A
feedback successive approximation converter easily
satisfied: tne performance specifications and could use
the D/ A as a feedback element. It offered these salient
advantages:
1. Generally well-known and understood and thus
easy for the user to become familiar with, and
use.
2_ Versatile- as the same building blocks may be
employed for both A/D and D / A operation.
~. Coding flexibility-applicable to any D/ A code.
4. Adaptable to all IC functional blocks for ultimate
economy. The commonality of chip types for
A/D and D / A means lower development and
manufacturing costs.
5. The functional blocks are independently saleable
products.
Because of the above considerations the design centered around a bipolar current summing D/ A converter.
The problem became one of defining the subsystem
breakdown on a circuit building block basis, relative
to IC technology capabilities.
DA converter configuration
Functional blocks needed for the DA subsystem, as
shown in Figure 2 include: 4
1. Transimpedance Amplifier
2. Logic buffer/current switching
3. Current sources
4. Voltage reference
5. Data register
A Family of Linear Integrated Circuits for Data Systems
PARALLEL DIGITAL
DATA INPUT
q
97
CONTROL
ANODE
CATHODE
FIG 3A
~ i (TO
BE SWITCHED)
SIMPLIFIED CURRENT SWITCH
r - - -.....--o
ANALOG
DATA OUT
OUT (CLAMPED AT
FIXED VOLTAGE) Vo
+ Vc C
OUT
~ i (TO BE
SWITCHED)
FIG 3 B CURRENT SWITCH
Figure 2-Current summing digital to analog converter
functional blocks
Adequate integrated summing amplifiers are currently available in large quantities. Because these amplifiers find application in other areas their production
volume is already high and their price, therefore, attractive. Further, such a choice allows the user to make
the cost/performance compromises and tailor the converter to his specific system requirements.
A simplified version of the current switching circuit
is shown in Figure 3A. It is apparent that current will
flow through the diode whose anode is at the higher
potential. By maintaining the output of the current
switch at a fixed potential the current flow can be
determined by applying various voltages to the "control" terminal. One disadvantage of this circuit is that
the control potential must be capable of supplying all
of the switched current. A significant improvement on
this circuit is realized by driving the control from an
emitter follower as shown in Figure 3B. The addition
of a current source level shifts the control potential
low enough in the "ON" condition to insure full current flow in the output. Summing any .number of
switched currents takes place by merely connecting
the outputs of two or more current switches in parallel.
However, care must be exercized to insure that the
reverse diode leakages are small to minimize error
current in the output. Quality silicon fabrication. gives
adequately low leakage over the temperature range for
ten switches in parallel. Even though the switches are
not gold doped, recovery is rapid enough for the required megabit operation since only one diode per
&witch is saturated.
To complete the explanation of the D / A converter
FIG 3C SIMPLIFIED
CURRENT SOURCE
FIG 3D
HIGH STABILITY CURRENT SOURCE
Figure 3
scheme, only the generation of accurate and stable
currents remains. Typically in bipolar circuitry, current sources are made using the basic circuit shown in
Figure 3C.
The collector current of such a circuit is given by
.
V-VSE . F or most tranSIstors,
.
h
lc = ex . RE
a approac es
unity and VBE is a logarithmic or weak function of collector current. As a result a reasonable current source is
obtained. Because the output conductance of most transitors is low, the collector voltage of the current source
has little effect on the collector current. For DA conversion where high accuracy ({nd stability of the current
value is required, steps must be taken to eliminate the
collector current dependence of lX, and thermal variations of VDE. In Figure 3D a more complex current
source is shown which remedies these variations.
Is', therefore
The circuit is designed so that Is
forcing the collector current equal to the current through
R s, the current determining resistor. This eliminates
the dependence of the collector current Ie on the transistor current gain, a. Because Tl and T2 are on the same
chip only a few mils apart, their characteristics are closely matched. In addition the use of high gain transistors minimizes I Is - Is' I .
Because a 10 bit converter requires 10 current
=
98
Fall Joint Computer Conference, 1967
sources whose currents must be related in a binary
manner, the VBE dependence of Ie must be accounted
for. Fortunately the collector current density is given
by J c = J Caat) exp
q~E
for many orders of current
magnitude and over the military temperature range. 5
Thus, by knowing the design current value, a given VBE
may be determined and compensated if the emitter
areas are held such ·that
Ie _ I sat
A-X
q V BE
explCT'
Much experience has been obtained in the matching of
transistor parameters through the production of differential operational amplifiers. This experience indicates
that the fabrication implications ot such a requirement
are not severe. Since Dl has similar geometry to T 1 and
its current matches T 1 , the temperature dependence of
VBE may be compensated. Th,us, by choosing appropriate values of R E , stable current generators are available. The technique of combining this type of current
source with current switching makes switching speed
independent of mode capacitances in the current setting
resistors, because the current continuously flows
through the precision resistors.
None of the preceding considerations precludes the
combination of the switches and the current sources on
the same chip. Indeed, the use of high gain transistors
imp~oves the quality of the current sources, while the
longer lifetime material required by these transistors
decreases the leakage currents in the switches. However, a compromise must be made in the minority carrier lifetime of the material, for if it is too long, switching speed will degrade.
It is also apparent that the value of the current
sources will depend on the value of the reference
voltage. Because a zero temperature coefficient reference can also be fabricated using the high gain process,
this too was included in the chip. Provision was made
for the user to supply his own external reference for
either (1) greater stability or, if required, (2) analog
multiplication.
The digital register was not included on the current
source chip for the following reasons.
1. Marginal speed without gold doping.
2. Incompatability with high gain used in the current sources.
3. Chip size would be inordinate for quantity production with present state of the art.
4. Avoidance of possible redundancy with respect to
digital system registers.
With very few compromises it is possible to integrate
the current sources, the current switches and the refer-
ence on the same chip at no loss of versatility for the
user and considerable gain in ease of use. By leaving
the preCision resistors off the chip the user may use
whatever codes he desires, thus enhancing flexibility.
With the inclusion of these three functions on the
silicon chip, an area 60 by 160 mils was required. By
using a proven process and designing with non-critical
masking tolerances, the best possible yields were assured for this large circuit. In addition, the circuit utilizes only NPN transistors, ten of which require matching equivalent to integrated differential amplifier input
transistors. The proven process consists of the standard
6 mask, monolithic epitaxial integration typical of
currently available LIC's. Figure 4 shows the circuit.
In the final DI A configuration (Figure 5) the integrated blocks consist of the data register, the summing
amplifier, the binary weighted current sources with the
switches and reference, while the resistors are separate.
The use of these functionally independent blocks allows the system designer to meet his conversion requirements at minimum cost.
The D I A performance curves for full scale drift and
non-linearity versus temperature are shown in Figures
6 and 7.
AI D
converter configuration
As mentioned earlier the DAC is utilized as a feedback element for a high speed successive approximation analog to digital converter (see Figure 8). The
general comments made for the D I A converter apply
also for the AID converter. Operation of the AID
configuration in Figure 8 is as follows:
The logic programmer will successively try each
data bit starting with the most significant (MSB). The
programmer will monitor the comparator output to
determine if the bit value is too large or too small. If
not (IsRsLyx), the comparator will cause the digital
data register to hold the bit in. If the bit value pulls the
summing bar negative (IsRs> Vx ), the comparator will
cause the logic to remove the bit. The programmer
then will try the next bit in succession until Y s~O and
the digital equivalent of the analog signal (Y s) is stored
in the register.
The summing current levels of the DAC, for 10-bit
operation, are not directly compatible with the temperature-dependent offset current of most presently
available IC comp.arators (e.g., ,uA 710). A thermally
stabilized differential pair ,uA726 may be used as an
excellent buffer stage. For moderate temperatures, a
simple differential pair is satisfactory. IC comparators
of the ,uA710 . class may be used directly for high
speed, low accuracy operation (i.e., 6 to 7 bits) over
a limited temperature range.
A Family of Linear Integrated Circuits for Data Systems
Vee
RE1
RE2
RE3
RE4
RES
REG
OUTPUTS 10 THE RESISTOR ARRAY
RE7
REg
REB
99
RE10
Figure 4-I.C. digital to analog converter
+.8
+.6
+.4
ILl
~MAX
~ +.2
1 megohm
Internal with external
trim op"tional
"1" less than +O.5VDC
"0" greater than
+2.5VDC
10 Bit Binary
8 Bit BCD
-20°C to +125°C
(Specification)
-55°C to +125°C
(Operating)
+15v
2.000kQ
SERIAL DATA IN
101
The resistor arrays used in two applications were
discrete metal wire-wound devices. Film resistor (thin
or thick) may be used, as the array values may be
pre-selected to achieve the accuracies stated. If
trimmed arrays to match the current sources are desired, the non-linearity error can be reduced to zero at
+25°C. Also the components are small enough to
easily fit within a P .C. board-mounted proportional
control oven. These would allow paralleling units for
greater accuracies and 13-15 bit resolution.
CONCLUSION
New IC functional blocks permitting all I.e. analog
digital data converters are now nearing production. As
with I.C. logic elements, the cost to the user can be
expected to fall to the point where economies will
grossly change design philosophies in the data acquisition field. These do-it-yourself components will make
low-cost analogi digital peripheral subsystems a true
reality.
RE AD COMMAND
+6.00v
REFERENCES
0-5v
VREF INPUT
aF DESIRED)
-15v
Figure 9-D / A converter
CLOCK INPUT
START CONY.
COMMAND
PARALLEL/SERIAL
DIGITAL DATA OUT
+6.00v
VREF INPUT
(I F DE SIRED)
- 6.00v o--~~""""""-'"
Figure 1O-A /D converter
ANALOG
DATA
INPUT
A K SUSSKIND
Notes on analog-digital conversion techniques
The Technology Press MIT and John Wiley & Son Inc
Chap 5 1957
2 K HINRICHS
Digital to analog conversion equipments and techniques
1964 Systems Engineering Conference New York N.Y.
June 1964
3 B D SMITH
Coding by feedback methods
Proc IRE vol 41 no 2 pp 1053-1058 August 1953
4 M B RUDIN R L O'DAY R T JENKINS
System circuit device considerations in the design and
development of a D / A and A / D integrated circuits
family
1967 International Solid State Circuits Conference University of Pennsylvania February 1967
5 C T SAH
Effect of surface recombination and ch(mnels on p-n
junction ana transistor characteristics
IRE Transactions on Electron Devices pp 94-103 January 1962
The effect of digital compensation for computation
delay in a hybrid loop
by EWART EDWARD LESLIE MITCHELL
Electronic Associates Inc.
Princeton, New Jersey
INTRODUCTION
Recent interest in hybrid computation has focussed
attention on the errors incurred because of the method
of solving the problem equations. In the past some attention had been given to errors incurred due to analog
component accuracy or round off error in a digital solution. However, with the advent of hybrid computation
and the knowledge that the sampling that had to occur
at the interface would perturb the solution, a number
of papers have been published to define the problem
and propose solutions. Probably the reason for the
stimulated interest is that the errors can be obtained
analytically for a number of simple systems. The proposed solutions to the sampling delay have shown an
order of magnitude increase in the accuracy of the
selected problems to which they were adapted.
It is the purpose of the paper, however, to show that
in general it is not possible to compensate for computation delay with a digital filter unless the basic damping of the system under study remains relatively constant over the duration of the problem or the sample
interval can be held to 30 or more per cycle.
Miura and Iwatal considered the effect of digital
execution time and showed that the delay would influence the poles of the system under study, obtaining expressions for the amount of the shift for a number of
simple systems. To compensate for the digital execution
time they suggested three compensation techniques:
(a) Assuming that the digital output is immediately
integrated, the output of the integrator is modified by adding (T+ T /2) of the input. Here T is
the delay due to the digital comP1:ltation and T
is the hold time at the output, where normally
T == T. See Figures 1 and 2.
(b) The digital computer can predict ahead by linear
interpolation, i.e.,
y
==
y'j
+ (T + T/2) (Y'J
-;. y'J-l)
103
(c) The analog first order hold can be implemented
in· order to avoid the staircase output and provide
the necessary lead. Here y'j is the computed output of the digital computation at the h time
step; Yj is the output compensated for the delay.
r
Figure 1-Definition of time T and
T
Figure 2-Compensation by modified integration
(Miura & Iwata)
Of these techniques the first one is the only one that
doesn't increase the order of the system. The other two
introduce extra roots into the system equations by
104
Fall Joint Computer Conference, 1967
using past history, which can be detrimental to solution
accuracy under certain conditions.
Karplus 2 has also examined the effect of digital execution time on the solution error. In addition to the
compensation techniques specified above, he also suggets modifying the input to the digital computer-if it
", is the result of an integration-by (T
T /2) times the
derivative. In a sense this is equivalent to (a) above and
does not affect the order of the system.
GilbertS also suggests modification of the input to
the digital computer when the derivatives are known in
a similar manner as above. Modifying the input to the
digital section avoids discontinuities in the outputs of
the analog integrators. Jumps occur when the compensation of Miura and Iwata is used.
The evaluation suggested by both Karplus and Gilbert for the compensation technique is accomplished by
observing the growth or decay of a simple sine wave
oscillator, which is very sensitive to phase shift. Unfortunately, these compensation techniques work very
well for lightly damped systems; it is the heavily damped
systems that produce the big errors.
Matlock4 extends the digital prediction technique to
higher order filters to better compensate for the phase
shift. These higher order filters introduce extra roots
into the system' which seriously· affect the performance
of heavily damped systems. This digital prediction technique has also been utilized by Deiter and Nomura!i
who obtain the prediction coefficients by GregoryNewton extrapolation. They evaluate the technique by
measuring the integral error in the representation of
a sine wave oscillator. Again the choice of a lightly
damped system for evaluation leads to false confidence
in the technique.
Our experience with predictive filters came about a
year ago when we applied the scheme to a hybrid helicopter simulation. The forces and moments are computed on the digital section and integrated on the analog. To stabilize the short period loops we included 2nd
order (quadratic) prediction in the moment equations.
The first evaluations-at hover-indicated that the
match with the real world was extremely close. Unfortunately, when we approached the top speed, the tail
started to wag, at a frequency about eight times higher
than expected, and the system went unstable. When the
prediction subroutine was removed, the instability was
also eliminated and left us with a simulation that had
frequency and damping still reasonably close to the
actual vehicle.
The explanation lies in the extra roots introduced by
the prediction technique and the fact that the natural
air frame is heavily damped at high speed. We will show
that the application of prediction to a heavily damped
system can lead to gross errors in the simulation when
+
the extra roots move into the region of interest-near
the unit circle in the z-plane or the jru axis in the s-plane.
To overcome the difficulty we had to adopt a techn'ique similar to that proposed by Gelman6 or Connelly.7
In essence a simple analog model is built up to approximate the system as closely as possible, and the digital
computer is used to determine errors in the ana10g
model. Provided these errors remain small correction
terms, then the major feedback loops are continuous
and adequate simulation accuracy can be maintained.
Adequate compensation should also have been obtained using the input compensation of Karplus or the
first technique (a) suggested by Miura and Iwata, since
the order of the sy:;tem is not modified.
In order to demonstrate the difficulties inherent in
digital prediction, consider the simulation of a simple
second order system and let us examine the effects of
different predictive filter coefficients and damping factors on the roots of the system equations. Naturally,
actual systems will be of higher order and contain nonlinearities, but significant trends can be unearthed by
treating the simplest possible configuration.
Problem statement
In order to represent a physically meaningful system
let us consider the simulation of vehicle pitch plane
dynamics, where the velocity vector is held constant.
The pitching acceleration, M, is assumed a function of
pitch rate, Q' and angle of attack, a. The differential
equations to simulate the motion are:
Q==M
a==Q
Note that we have absorbed the moment of inertia
into the moment M, so that M has the dimensions
rad/sec 2 rather than the conventional ft-Ibs.
Our digital computer is programmed to compute M,
and we will assume that this is linearly related to the
problem state variables. In actual practice, the computation of the forces and moments requires almost an
the available digital computation time; but for the purposes of analysis we will consider perturbations about
a steady state.
Expressing
M == MQQ
Mcr:CX:
the state equations become
+
The frequency and damping for the unforced continuous system are obtained from the eigenvalues of the
Effect of Digital Compensation for Computation Delay in Hybrid Loop
state matrix or roots of:
A" - MQA so that
Mo: = 0
2
= Mo:
where , is the damping and Ct)n the natural frequency of
the undamped system.
In the s-plane the roots are at MQ/2; + [MQ2/4
+ M
2 and it will be our objective to determine
a
how close the roots of the compensated system approach these desired values.
Now to compensate for the sampling effects at the
analog-digital interface we will apply up to quadratic
prediction to the computed M by taking a linear combination of the current value and past history-up to
3 time steps ago. See Figure 3.
.105
set of simultaneous equations given in the appendix.
The essential requirement of the prediction is the attempt to recover the lost 1.5 time steps (=a) due to
the combination of digital computation time and sample hold.
(Un
r
From Figure 3, the basic state equation can be expanded to develop the transition matrix that transfers
the state from one time step to the next.
T
Or+l
==
OJ
+ JMJdt
= OJ + MjT
o
T
+
aJ
J
Odt
o
Substituting for Mj, where
MJ =
l
k=O
ak M'J-k
&
~----------~ADC~----------~
leads to:
Figure 3-Flow diagram for hybrid damped sine-wave oscillator
i.e.,
all
1
OJ+l
OJ
OJ-l
OJ-2
aj+l
aJ
aJ-l
aJ-2
a12
a13 a14 au
a16 an alB
1
1
~l
~
~s
a44
~5
~6
au
~8
1
1
1
OJ
OJ-l
OJ-2
OJ-3
aJ
aJ-l
aJ-Z
aJ-S
where
where
+
Mo:CX:j
M'j = MQOj
and j is the time step count, incrementing in the sample time, T.
We want to consider the effect of various values of
the predictor parameters ~ - as on the solution. The
following interpretation can be made for the a's:
(a)
~ = 1
al = a2 = as = 0
The system corresponds to the case where the digital
computation time is zero, the error being introduced by
the necessity to hold the output constant over the sampling time, T.
(b)
•
0
al
1
a2=aS
0
This condition is observed in ruost current hybrid
simulations where the computation time is equal to the
sampl~ time. Thus, the output, M, is delayed from the
two inputs by one complete cycle.
Other coefficients may be obtained by solution o~ the
au
au
alS
a14
a15 a16
an
a18 =
l+~Mo:T
al~T
a2M QT
asMQT
~l
a42
~S
a44
~Mo:T
~5
alMocT
a2Mo:T
aaMo:T
a46
~7
~8
T+~MQT2/2
a lMQT 2/2
a2MQT 2/2
asMQT2/2
1+aoMo:T2/2
a lMo:T2/2
a 2Mo:T2/2
aaMo:T2/2
Now we can see that by adding in the predictionor compensation-terms, we have increased the order
of the system under study from 2nd to 8th, at first
glance, for the quadratic predictor. However, the rank
of. the matrix is only 5, so just three extra roots are
introduced. The eigenvalues of this transfer matrix
correspond to poles in the z-plane for the sampled system. It is immediately obvious that for stability, all
the eigenvalues must lie within the unit circle, otherwise successive application of the matrix will cause
(some) solutions to increase without bound.
This eigenvalue equation can be reduced to:
106
[1
Fall Joint Computer Conference, 1967
+ aoMQT - aoMoT2/-(2 + aoMoT2/2)A +
+ T[(I-A)MQ - (1+A)MoT2/2] [a A2+a2A
+ ~]A3 = 0
A2]A6
into instability still corresponds to crossing the imaginary axis. Placing an arbitrary bound of 10% round
the roots shows that we need about 160 samples/cycle
when MQ = .2 and 21 samples/cycle when MQ = 1.0
to maintain the system simulation to this accuracy.
I
Three of the eigenvalues are zero, but we are left
with a fifth order polynomial or three extra roots. The
characteristic polynomial can be rearranged to:
A5 + blA4 + b2A3 b3 A2 + b4 A + b 5
0
where
b l - - ao')' - 2
bl
- al'}' + aot + 1
ba - - a21' + ai'
b. - - aa'}' + a2'
~,
b5
and
l'
T(MQ+MoT/2)
+
~
-
=
110'0.2
160
32
II
Ie
0----------+------.. -4
1
s = -
loge z
T
results in roots at:
s = MQ/2± [Mo:+MQ2/4)12+0(T)
so that we have a check that the sampled system corresponds to the original continuous system for small
sample times.
Our object now is to study the behavior of the root
loci obtained by varying T for different prediction
parameters ao - aa and for varying damping MQ. We
1 corresponding to a natural frehave kept M
a
quency of 1/27T' cycles/sec; and on all the root loci,
sample time, T, is expressed as samples/cycle.
=
SAMPLES ICYCLE •
.7
0
~
.1
COEffICIENTS
.2
~'-I-'--'---'--------L._
-1.0
.. L-,-"- J .• l_._'_-'--_...J.. ___ --'--_. _ _ ~ •. _'_,~-'----'-_
0
- 0.01
- 0.001
-0 I
Figure 4-Root locus-no computation delay
Case II: No prediction but digital computation time
corresponds to sample time, T, i.e.:
ao = 0
al = 1
a2=aa=0
Figure 5 shows the root loci for the same two damping values. An extra root appears, but remains well up
to the left on the real axis while the system roots move
toward the imaginary axis and instability. Now 520 and
64 samples/cycle· are needed to keep the roots within
10% of the correct position for MQ = .2 and 1.0 respectively.
HMiH DAMPING
Mo'I.O
II
14
1
Results
Four cases of practical interest were examined and
applied to systems that had inherent high and low
damping. It would appear from this that at low sampling rates, the extra roots introduced by the prediction
can cross the imaginary axis and become unstable,
especially at high damping (MQ = 1.0).
Case I: Figure 4 shows the root locus for the system,
ao
=
I
SYST[III ROOTS
•
SAMPLES ICYCLE: •
o
--+!-
COE"ICI[NTS
.0 · 0
-. -,
-2. 0
.3. 0
1
al = a2 = aa = 0
for the two values of damping MQ = 0.2. and 1.0.
These loci correspond to the unrealized case of zero
digital computation time; but since it is the only one
where only two roots are maintained, can be used for
comparison. The root loci are plotted on the s-plane
because the variation of T causes the natural system
roots to move on the z-plane. Crossing the unit circle
.•
.1
S- PLANE
SYSTEM ROOTS,
T(MQ-Mo:T/2)
We can show that for T < < 1, the three extra roots
move into the origin as well, leaving the two that correspond to the original sys!em near the + 1 point.
Transforming these to the s-plane by:
1.0
21
-10.0
.. 0.1
-0.01
Figure 5(a)-Root locus-l cycle computation delay
Case Ill: Applying the simple linear predictor to
overcome the delay:
ao
0
al
2.5
a2
-1.5
aa=O
Effect of Digital Compensation. for Computation Delay in Hybrid Loop
UIII_
.. ..
.0 ·0.1
100
01
110
I
eo
..
I
I
I
..
.-"-....
"ITlIll IIIOOTI
•
........'./CYa,,1 •
..
eO''''''CI'_'1
00' 0
e,"
ez'
0
.,' 0
.J
.1
Figure 5(b)-Root locus-l cycle computation delay
107
Case IV: Using the quadratic filter to predict ahead
for 1.5 sample times, the coefficients become:
ao
0
al - 4.375
a2
-5.25
a,
1.875
Figure 7 shows the corresponding root loci. The five
roots provide three extra, two imaginary and one real.
In both cases the stability limit is exceeded by the extra
root pair crossing the imaginary axis-at 10 samples/
.2 or at 28 samples/cycle when
cycle when MQ
MQ = 1.0.
Note that prediction controls the principal roots in
the high damping case in such a way that the movement
is negligible.
=
Figure 6 shows the corresponding root-loci. Of note
now is the appearance of a second pair of roots since
the system polynomial is now fourth order. For the low
damping case, MQ = .2, these extra roots stay over on
the lefthand side, while the system roots move to the
right, toward the stability limit. However, when we
make MQ = 1.0, so the basic system is heavily damped,
the system roots move to the left; and the extra roots
move to the right crossing the stability limit at 13
samples/cycle and producing an oscillation at 2.7
rads/sec.
I"
"LA"
0
. .ITlII Il00Tl •
SAM'LES' CYCLE-.Jl-
COI""ClUTS
00'0
8, ' •. Sl'
·Z·-I.II
.s'
1.'7'
"G '0.1
-
-.0
..
'I E>
Figure 7(a)-Root locus-second order compensation
1-"-nlTlII IIOOTI
SAllll'LEI/CTCU
0
~
1:
COE"ICICMTI
.0' 0
l'!4
e,' I.'
.z.
.s'
-I.S
-.
.I
0
.
"GoQ.l
..
_z
0-=
I I I •. l
-'.0
1. ---L-_J ___ aL
l'
._.---L........o...1
-0.'
I-"L'II,
-0.01
S'ITIM
aoon • 0
.....-c.[S I CYCLE
•
II
~
COU'ICIIM"
Figure 6(a)-Root locus-first order predictive compensation
"d""'0
·0'0
8. ' •. "1
a'."
.z
·S'l."
o
I ..
10
-to
1..,.111 MOTI'
_II/CYCLI'
I I
I
14
-t-
COIFFICIlIITI
I
-0.1
nGUM J(.)r
0
IIXJrLGCUI
aCDID 0181 CDlPDSA1'lC1f
Figure 7(b)-Root locus-second order compensation
"0'0
.. '1.'
ea· ... .s
CONCLUSIONS
.J'O
-0.1
-O.()l
Figure 6(b )-Root locus-first order predictive compensation
The application of predictive compensation to lightly
damped systems, as suggested in the references, can
result in accurate simulations for as low sampling rates
as 10 per' cycle. However, it must be pointed out that
the important criteria for validity is whether we can
apply this compensation to highly stable systems. In
108
ala
Fall Joint Computer Conference, 1967
,"0.2
N
Z-PLANE
SYSTEM ROOTS •
SAMPLES I CYCLE.
'~O
-e::-
~
COEFFICIENTS
ak -
1
k ak
-
N
°0=0
~
k=O
01 '"4.375
02= -5.25
-a
°3'"1.875
k=O
~
1.0
q
kqak = (-l)q ex
N
where ex is the number of time steps extrapolatedfraction or integer, i.e.,
N
Figure 8-Root locus in Z-plane of second order compensation
fact, the majority of physical systems that come before
the simulation engineer will be highly stable, since a
normal design objective is to ensure suitable frequency
response and adequate damping.
If digital compensation is to be applied to several
systems-for instance as part of a software librarythen no higher order than the first need be used and an
adequate sampling rate must be maintained to keep the
roots due to the compensating polynomial away from
the rt:gion of interest. With unity damping (MQ= -2.0)
even first order prediction requires 25 samples/cycle
for stability, and at least 30/cycle would be necessary
for an adequate simul~tion. Basically, this is a
restatement of the old requirement-that hybrid computation requires the fastest digital computation to
maintain an adequate simulation performance.
A characteristic of these extraneous roots introduced
by the prediction technique is the speed with which
they move into the region of interest. That is, changing
the sampling rate by 1 or 2 samples/cycle can make all
the difference. Conversely, with a fixed sampling interval, no warning is given that stability limits are being
approached, since a small change in natural frequency
can cause the oscillation to appear.
k=O
If ex is negative, then an interpolation is obtained which
is useful for data smoothing or reconstruction. If
q = N, then the a's are completely defined, but if q------ RECOROER
(a)
Experimental control circuit for comparison - all analog.
REFERENCE
r----------RECORDER
IO-MILLISECOND SAMPLE PERIOD
ANALOG
I
I
I
I DIGITAL
I
(b)
Hybrid oscillator being evaluated.
Figure 12-Integrator eval uation circuits
Hybrid Apollo Docking Simulation
119
Figure 13-Analog and hybrid 06cillators, 10 cps
Grounding and noi~e rejection were' early problems of concern, but the first system tested for control
signals worked very well. Relays were used for isolation, and the commons of the relay power supplies were
tied together at each end. Results were not as good
for the analog signals. Three systems were tried before
a final configuration was reached.
The first was a chopper-driven, transformer-coupled
system built by AMF. The phase lags and noise
produced by the choppers were excessive. The second
method used differential amplifiers. Noise levels were
still intolerable. Finally, the transmission terminal
equipment was completely eliminated. The lines were
then driven, with no problems, directly from operational computing amplifiers. Considerable 60-cyc1e
noise was picked up because of ground potential differences. On input, this was removed by subtracting
the signal on the line (which was grounded at the
simulator end) from all of the other signals. On output, noise is added to the command information before transmission. Figure 14 is a schematic diagram
of the common mode rejection circuits (References
10 and 11).
The evolution of setup and checkout philosophy on
this project was very enlightening. The first approach
used hand-calculated potsettings and static check values
stored on punched cards. It was soon evident that the
frequency of changes to these decks would create an
excessive workload.
A program to calculate potsettings was written, and
the flexibility of changing problem parameters was
greatly improved. However, the program was so large
that changes to it were difficult. A single potsetting
change required about 2 hours for recompilation and
loading, but this method was used nevertheless because
of reliability and speed of calculation. The reliability
stemmed from the fact that data could be loaded into
the computer once and used for potsettings, digital
parameters, and documentation. This eliminated the
inherent unreliability of having a person input the same
data twice.
The static check philospophy was generalized somewhat by making it interpretive and by causing it to
recognize all forms of AID communication. However,
it was still manually prepared, difficult to maintain, and
hardware oriented. Memory space was at a premium,
largely because of the size and complexity of the setup
programs. As the system monitor grew in size, it be...
came necessary to overlay programs. The simulation
had two overlays which were automatically swapped
when required. Setup and static checkout was in one
overlay while initialization and all real-time programs
TRANSMISSION LINE
CUBIC AMP.
ADTD-
I
I
I
I
I
I
I _.
NO. 22 WIRE DOUBLESHIELDED TWISTED PAIR
SERVO AMP.
I
I
I
I
I
CONRflW~~
!
~:-I
-
COMPUTER HQ CND.
_______;____
CON~WER
""':(4-l~
!
Figure 14-Common mode rejection circuits
120
Fall Joint Computer Conference, 1967
were in the other. The data area was common to both
overlays.
CONCLUDING REMARKS
If this simulation were to be restarted with present
experience, several significant changes would be made.
The functions of potsetting calculations and static checkouts would be performed by a problem-oriented interpreter. This would permit rapid modification to the
analog program, with corresponding setup program
changes. It would also permit a calculated static check
for every configuration, n.ther than the single hypothetical case which was used. Such an interpreter would
look very much like the EAI Hytran Operations Interpreter, but three very significant changes would be
made. The interpreter would be subordinate to the
main control program of the simulation, and it would
communicate with the rest of the simulation by means
of a symbol table. Without these features, the operator
must input the same data twice in different formats.
The interpreter would also have the ability to handle
multiple analog computers. In addition, a fully automatic scaling program would be written for the analog
and conversion system programs.
The overall development schedule for the project
would be entirely different. A clear distinction would
be drawn between the buildup of the simulator and its
use for· testing purposes. This distinction might be
extended to include the use of different personnel for
the two phases. In particular, the simulator would l:e
built and checked out more slowly.
The load-cell system would be modified to insure
the impossibility of measuring physically unrealizable
forces and moments (that is, not equal and opposite
on the two bodies). This could be accomplished by using load cells on only one vehicle; however, some ot
the simu.lation realism would be lost. The best method
might be to use an overdetermined set, of perhaps
nine load cells per vehicle, which would eliminate the
noise and bias problems.
Only through the efforts of a large number of people
was the success of this simulation possible. It is hoped
that some raIt of the description of the problems, solutions, and experiences will be useful to others who are
now involved, or who may become involved, in simulations similar to the one described.
REFERENCES
R M DEITERS T NOMURA
Circle test evaluation of a method of compensating hybrid
computing error by predicted integral
Simulation vol 7 no 1 pp 33-40 January 1967
2. ANON
Dynamic docking qualification test program
October 1966
North :\merican Aviation Inc Report no SID 66-914
3 R GELMAN
Corrected inputs-a method for improved hybrid simulation
Proc· Fall Joint Computer Conference AFIPS 163
4 E G GILBERT
Dynamic-error analysis of digital and combined analogdigital computer systems
Simulation vol 6 no 4 pp 241-257 April t 966
5 W J KARPLUS
Error analysis of hybrid computer systems
Simulation vol 6 no 2 pp 121-136 February 1966
6 R E LANG
Digital integrator for hybrid applications
Instruments and Control Systems vol 40 no 1 pp 103-105
January 1967
7 0 L MATLOCK
Pulsed prediction filters applied to digital and hybrid
simulation
Simulation vol 6 no 3 pp 153-157 March 1966
8 EEL MITCHEL
The effect of digital compensation for computation delay
in a hybrid loop on the roots of the sinl'tlated system
Proc Fall Joint Computer Conference AFIPS 1967
J IWATA
9 T MIDRA
Effects of digital eecution time in a hybrid computer
Proc Fall Joint Computer Conference AFIPS 1963
10 E L STEWART
Grounds grounds and more grounds
Simulation vol 5 no 2 pp 121-128 August 1965
11 E L STEWART
Noise reduction on interconnect lines
Simulation vol 5 no 3 pp 149-155 September 1965
These pages, 121 - 142 deleted due to circumstances
beyond the control of the Fall Joint Computer Conference
and AFIPS Press.
Solution of integral equations by hybrid
computation
by G. A. BEKEY
and J .. C. MALONEY
University of Southern California
Los Angeles, California
and
R. TOMOVIC*
Belgrade University
Belgrade, Yugoslavia
INTRODUCTION
The mathematical description of many problems of engineering interest contains integral equations. Typical
of a large class of such problems is the Fredholm integral equation of the second kind,
y(x)
==
b
f(x)
+A!
K(x,t) y(t) dt
(1)
where f(x) and the kernel K(x,t) are given functions,
a and b are constants, A is a parameter and y(x) is to
be found. From a computational point of view, equations of this type may be considered as problems in
two dimensions, where one dimension (t) is the dummy
variable of integration. For digital computer solution,
both variables must be discretized. For analog computer solution, it is possible to perform continuous
integration with respect to the variable t for a fixed
value of x and perform a scanning process to obtain
step changes in the second variable. In either case, the
solution is iterative and results in a sequence of functions {Yn(X)}, n==1,2,... which, under certain conditions, converge to the true solution y(x) as n increases.
It is evident that such a sequential solution, with a
two dimensional array K(x,t), may be extremely time
* This work was initiated during 1964-65, while the author was
an NSF Senior Foreign Scholar and Visiting Professor at the
University of Southern California, Los Angeles. It was supported in part by the Office of Scientific Research U. S. Air
Force under Grant No. AF-AFOSR 1018-67.
143
consuming for pure digital solution. On the other hand,
the scanning and iteration procedures, which require
storage of the successive approximation to the solution,
do not lend themselves to pure analog computation.
Rather, the problems require a hybrid combination of
high speed, repetitive integration, memory, and flexible
control logic.
The advantage of using such hybrid computational
methods for the solution of integral equations was realized quite early. A special purpose computer for solution of integral equations was proposed by Wallman in
19501 • Basically, the computer technique consisted of
replacing the integration with respect to two independent variables by scanning at two different rates. These
original proposals for· iterative solution of integral
equations were based on the classical or Neumann
method. 2 In 1957 M. E. Fisher proposed an iteration
technique for high-speed analog computers equipped
with a supplementary memory capacity which resulted
in considerably faster convergence than the classical
technique. 3 However, little practical experience with
his method is available due to the complexity of the
function storage and playback apparatus. 4 One test of
Fisher's method was made using a repetitive analog
computer in which the computer operator manually
adjusted a set of potentiometers in a special function
generator at the end of each iteration cycle. s
The purpose of this paper is to examine hybrid computer solution of integral equations, by both the Neumann and Fisher methods.
144
Fall Joint Computer Conference, 1967
The Neumann iteration method
The classical or Neumann iteration procedure for
the solution of (1) is specified by
D
Yn+l(X) == f(x)
+ A .f K(x,t) Yn(t) dt
(2)
with Yo(t) == O. Under conditions discussed in Reference 4, the process converges to a limit Yoo(x) which
is the solution of (1).
From a computer point of view ~ an integration over
the whole range of t must be made for each particular
selected value of x. If the range of x is divided arbitrarily into I segments of length .1x, the function is
represented by the values of y(x» at the midpoint of
each segment, i.e., y(xJ), i == 1,2,3, ... 1. It is clear
that a total of I integrations in the t domain must be
made before a single change in Yn(t) is made in equation (2). Such an integration in t for a single value of
x == Xi will be called a minor cycle. In order to increase the index n, i.e., to derive the next approximating function Yn+l (t), one has to complete I minor
cycles. This group of minor cycles will be called a
major cycle. The complete solution theoretically requires an infinite number of major cycles. However,
practical experience'" has demonstrated that accuracies
of the order of 1 % are attainable in about 20 major
cycles using Neumann's method.
It should be noted that digital computer implementation of the strategy defined by (2) requires that the
variable t also be discretized and that an appropriate
numerical integration formula be used. For example,
if Euler or rectangular integration is used, Equation (2)
becomes
J
Yn+l(XI) == f(xi)
+A I
K(xi,tj) Yn(t j) .1t
(3)
J=l
i == 1,2, ... ,1
where .1t == constant is the integration step size and
J is the total number of steps in the interval (b - a).
Since t is only a dummy variable, the total range in t
must equal the range of x and it is possible to choose
the number of steps in t and x to be equal, i.e., let
I == J. . More sophisticated numerical procedures do
not change the need for minor and major integration
cycles. Equation (3) requires only the algebraic operations of addition and multiplication and is well suited
to digital computation.
For hybrid computer solution each minor cycle may
be performed continuously (using analog integration)
and the reSUlting values stored. Assignment of other
specific computational functions to the analog or digital
portions of a system may significantly affect overall
accuracy, as discussed in a later section of the paper.
Thus, the generation of the functions f(x) and K(x,t)
as well as the multiplication under the integral sign in
(2) may be perfonned either in the analog or digital
computer. A flow chart illustrating the programming
of Neumann's method is shown in Figure 1. A stopping
criterion given in the flow chart is based on reducing
the difference between successive approximations to a
sufficiently small value.
Figure I-Flow diagram of Neumann's method
The Fisher iteration method
An examination of Equation (2) and Figure 1 reveals
that Neumann's mithod requires the storage of Yn+l (XI)
at the end of each minor cycle (i.e. for i == 1,2, ... I).
At the end of I minor cycles the entire vector [Yr.(t)]
under the integral sign is replaced and a major cycle
has been completed.
Fisher's method 3 .'" for the solution of the same problem requires that one element of the vector [Yn(t)] be
updated at the end of each minor cycle. Consequently,
the Fisher version of the digital process of equation (3)
becomes
J
Yn+l(XI) == f(xi)
+A I
J=l
K(XI,t J) Yn.l-l(t J) .1t
i == 1,2, ... 1,
j == 1,2, ... , J,
I
==
(4)
J
Note that yet) under the summation sign now carries
a double subscript. The idea is to replace at the end
of each minor cycle the existing value of Yn(X I) in the
memory with the newly obtained value of Yn+l(Xi)'
The notation (n,i)i== 1,2, .. , I implies that during each
major cycle the unknown function y(xl) is gradually
adjusted as the index i is increased, not waiting, as in
Solution of Integral Equations by Hybrid Computation
the Neumann method, until all minor cycles are completed. In other words, Fisher's method is based on
using each piece of new information as soon as it is
available so that the adjustment from Yn(X) to Yn+1(X)
proceeds gradually, rather than being performed all at
once after I minor cycles.
The hybrid computer version of Fisher's method
takes the form
(IBM 1620 digital computer and Beckman 2132 analog
computer).
In order to facilitate the evaluation of the two methods, solutions, Yn(t) were compared with known exact
analytical solutions, z(t) , by means of a root-sum
square criterion, defined by
I
1=1
x
f(xl)+A
f
145
[z (Xl) - Yn(XI) ]2
(6)
t
K(Xh t) Yn+1 (t)dt
Example 1. The following equation was solved:
a
b
1
2
3
y(X)
i==1,2, ... I
(7)
+ 2 j'(X-t) y(t) dt
(5)
with the initial approximation yo (t) ==
The first integral on right hand side of (5) contains
the results which have been obtained during the previous minor cycles of the present major cycle. A flow
chart showing the hybrid computer implementation of
this strategy is shown in Figure 2.
2
3
The
step size was chosen as ~X == 0.1 and the multiplication was performed on the analog computer. The solutions obtained by the Neumann and Fisher methods
are compared in Figure 3 using the criterion F n defined
in (6). The considerably faster convergence of Fisher's
method is clearly illustrated.
Compori.on of Hybrid Solutions Using
Classical and Fish~r Methods
~2.0
ylxl' 213 + 2.[lx-tlYltldt
a:
a:
1&.1
'olxl' 2/3.
1&.1
~ 1.5
~....
::J
o
(I)
~
Ax' 0.1
A-Classical Method
o -Fisher Method
~ ....
1.0
....
\
o
o
a: 0.5
···A .... "
\
""'''''' ''6.
\,"O--_____ ~ ~~~~~·_:~~·~~.~6_::'''6 "" ......•
0.01----.----2r---~=T'3==4t=-=-=='t5>===.~~6----1==;~="'49
MAJOR CYCLE
NUMBER
Figure 3-Comparison of hybrid solutions using classical and
Fisher methods
Figure 2-Flow diagram of Fisher's method
Illustrative examples
Time histories of the kernel K(x,t) == x-t and the
functions Yn(XI) for several major cycles are shown in
Figure 4.
Example 2. The following equation was solved.
1
Fisher has shown4 that for symmetric kernels his
algorithm converges whenever the Neumann algorithm
does, and in certain cases also when the classical
method fails. (A symmetric kernel is characterized by
K(x,t) == K(t,x». Furthermore, using a simple example, Fisher has demonstrated that his method may
speed up convergence significantly. In order to obtain
practical results concerning this comparison, several
problems were solved using a small hybrid computer
y(x)
==
7
1.5x - -6- +
f
(x-t)y(t) dt
(8)
To illustrate the effect of choice of initial conditions,
the equation was solved once with yo (t) == 0 and once
with Yo(t) == 2/3. The results are shown in Figure 5
for ~X == 0.01. It is evident that a poor choice of initial
approximation may lengthen the convergence. process.
Example 3. Examples 1 and 2 used kernels which
146
Fall Joint Computer Conference, 1967
--
I
+1
Speed = 0.2 em Isee
Time History of Fishers
Solution to
y(x)
213 +
c
Yo (x)
I:
2'£CX- tly(t)dl
2/3
Figure 4-Time history of Fisher's solution
10.0Ir-""V---r-----r--.-----,----r--~--~-~
'~
5.0r---.--.---.--..----.--..------r----r----.
ComparoMln of Hybrid Soluloons USIng
Classical and Fisher Methods
II:
o
~8.0
4.0
~
A.·O.OI
Yo(I)'2/3,
o
ct
::>
Method
-Fisher Method
~
o
(J)
o(J)
Yo(x)=O,
Ax
'0.01
II:
I.
AI'
......
······.6..
",
··············A
"''G,
············· ... 6.
.........
2.0
0.01
6-Classical Method
o -Fisher Method
'"l!I",
I-
o
o
III:
,~.~....... .
"
'A.
UI
0-Fisher Method
(J)
o
o
Ya(x)'"
~ 4.0
0- Classical Method
~ 2.0
yl.).'+£~-·ty(t)dt
.....>&,'
~6.0
.to - Classical
::!3.0
······6>\"
....
II:
II:
W
ylx)' 3x/2 - 716 +4(X-t)yltldt
II:
Comparison of Hybrid Solutions Using
Clatsical and Fisher Methods
................ i!..
0.00~--:---:---:-..!...-..-~----"\:)...L·_'_"_'-_--c:>-.L.
_- ._~_~.-_-~:;.~.: . :~. : .-:. - :. 5-(.
_'-_'_--_-'0-..J....
O.O,f-----.-----.:¥=-=~~~~=~""""''''''''''o===_'==o===a
3
o
4
8
5
MAJOR CYCLE
NUM~R
could ce considered functions of a single variable.
Consider now the equation
+.r
1
xt
e- yet) dt
yo (t)
7
.
8
Figure 6-Comparison of hybrid solutions using
classical and Fisher methods
Figure 5-Comparison of hybrid solutions using
classical and Fisher methods
y(x)
4
5
6
MAJOR CYCLE NUMBER
(9)
0
The results are shown in Figure 6. Once again the
superiority of Fisher's method is evident.
Discuss!on of errors
The major errors which enter into the hybrid .solutions of integral equations are the following: (a) truncation errors (due to the fact that the functions have
been quantized), (b) AID and DI A conversion errors,
(c) other analog computer errors, and (d) phase shifts
due to digital exe~ution time.
Truncation errors arise from the quantization of the
variables x and t in equation (1). In order to test the
9
Solution of Integral Equations by Hybrid Computation
importance of the quantization interval, Example 1
above was solved using 10 intervals (Ax=O.l) and 100
intervals (Ax=O.Ol). A comparison of the root sum
squared errors for both interval sizes using the Fisher
method is shown in Figure 7. It can be seen that convergence is speeded up by the choice of a smaller interval. After a sufficiently large number of major cycles,
there is no apparent advantage to the small interval
size. In fact, an oscillation in the final error criterion
values ensues with the small AX, which may be due to
a random compounding of roundoff errors from the
large number of minor cycles.
O.l2r---~--.----r----.--~---''''---r--~-
A
~ 0.10
Comporison of
Fish,r Method
Hybrid
Solution' \Jain;
ylal" 2/3 + 2J:la-nyltlcl!
'Yolal" 213
II:
II:
....
~ 0.08
A -ila" 0.1
g
0 - ila" 0.01
<:
:::>
~ 0,06
147
region in the solution, as evidenced in the oscillation of
Figure 7.
Alternate mechanization of kernel generation and
multiplication were also investigated. The resulting effects on solution accuracy are clearly a function of
the quality and precision of available analog multipliers and function generators, as well as conversion errors. It should be noted however, that analog generation of the kernel K(x,t) has the advantage of producing a program which has a solution time independent
of kernel complexity and whose digital portion is universally applicable.
Solution time. While the actual times taken for a
given solution clearly depend on the particular digital computer being utilized, comparisons between
hybrid and all digital solutions are of interest. A speed
up factor of 300 to 1 was obtained by using hybrid
computation over digital computation, with comparable
final accuracy.
VI
Extension to other types of integral equations
t-
o
~ 0.04
The above discussion has been devoted entirely to
equations of the Fredholm type. However, extension of
the technique to many other types of equations is possible. Consider, for example, the Volterra equation:
0.02
7
Fi~ure
8
y(x) = f(x)
7-Comparison 'of hybrid solutions using
Fisher method
The effect of quantization also enters into the integration process since the approximating function Yn(t)
is reconstructed from the samples Yn(Xt), i = 1,2, ... I.
In the present study this reconstruction was accomplished using simple zero-order holds, i.e.,
At L.
Yn(t) = Yn(tl) for tl - -2- - t
At
< tl + -2-
(10)
It can be shown· that with both zero-order and firstorder reconstruction the errors are proportional to
(~tY. Second-order interpolation formulas will reduce
the error to 0(At)3, but the additional computation required to achieve it may not be justifiable.
Analog-to-digital and digital-to-analog conversion
errors were extremely important' in the solution of the
example problems. However, it should be noted that.
both the Fisher and Neumann techniques are stable
processes as long as the solution to the problem is analytically convergent (see Reference 4). Thus, random
errors (which may enter the problem from the converter or multiplier inaccuracies) during anyone iteration (major cycle) will be corrected in subsequent iterations. Consequently, random errors delay the converg.;.
ence process and may also cause a final indeterminacy
+A
.f
K(x,t) y(t) dt
(11)
This equation differs from the Fredholm equation in
that the upper limit of integration is variable. The algorithms of Figure 1 and 2 are still applicable if the kernel is redefined such that
(12)
K(x, t) = 0 for t > x
A simple digitally controlled switch (needed to implement (12» can ce used in conjunction with the Fredholm equation program to solve Volterra type equation ....
Wallman I and Fisher3 have also indicated possible
extension of hybrid techniques to the solution of multidimensional integral equations, integrodifferential
equations and certain more general functional equations. Such extensions have yet to be proved in practice.
CONCLUSION
Hybrid computation techniques, involving fast repetitive analog integration and function generation and
digital storage 'and control, are well suited to the solution of integral equations. Hybrid techniques lead to a
substantial reduct jon in solution time when compared
to all-digital methods. Further, the examples solved in
this study substantiate the faster convergence of Fisher's iteration scheme, when contrasted with the classical
148
Fall Joint Computer Conference, 1967
Neumann technique. Extensions to other areas of application appear promising but remain to be tested.
ACKNOWLEDGMENT
The writers express their appreciation to Messrs. L. J.
Gaspard and T. Deklyen for their assistance in obtaining a number of the computer solutions discussed
in this paper.
REFERENCES
H WALLMAN
An electronic integral transform computer and the practical solution of integral equations
J. Franklin Inst. 250:45-61 July 1960
2
F B HILDEBRAND
Methods of applied mathematics
Prentice-Hall Inc Englewood Cliffs N.J. 1952
3 M E FISHER
On the continuous solution of integral equations by an
electronic analogue
Proc Cambridge Phil Soc 53:162-173 1957
4 D B McKAY M E FISHER
A nalogue computing at ultra-high speed
John Wiley & Sons Inc New York 1962
5 R TOMOVIC N PAREZANOVIC
Solving integral equations on a repetitive differential
analyzer
IRE Trans on Elec Computers EC-9 503-506 December 1960
Graphic CRT terminals-characteristics of
commercially available equipment
by CARL MACHOVER
Information Displays, Incorporated
Mount Kisco, New York
INTRODUCTION
"Who needs another review of Graphic CRT Terminals when so many good ones have recently been
published?"
A reasonable questionAfter all, Adams Associates is now offering the
"Computer Display Review"! - in which they're trying
to do for the display field what they have been doing so effectively for the Computer field (with their
"Computer Characteristics Quarterly"). The Air Force
has just published their "Compendium of Visual DisplaysH2. Harry Poole's recent book, "Fundamentals of
Display SystemsHa admirably meets the author's stated
objective " ... to provide fundamental data and illustrate basic ~echniques used in the design and development of display systems". Excellent books covering
the use of displays in specialized application areas, like
James Howard's new book "Electronic Information
Displays for Management"4, are now available. Several
survey articles5' 6 have recently appeared. Reasonably
complete bibliographies of computer graphics literature have been published, such as the selected bibilography appearing in Ronald L. Wiginton's paper
"Graphics and Speech Computer Input .and Output
for Communications with Humans" inculded in "Computer Graphics/Utility - Production - Art". 7 These
examples by no means exhaust the list-but they do
emphasize the lead question "Why another one?"
The justification depends on two factors, I think.
First, there appears to be a need for user orientedhardware based information. (There is, to be sure, also
a need for user oriented-software based informationbut that will have to be the subject of someone else's
paper.)
.
Second, there is also the need, I believe, to define
terms. The user encounters words and phrases like
"jitter" and "flicker-free" which are used to describe
the performance and quality of a display system . . .
but the exact meaning of the terms are frequently left
undefined. This lack of definitions is not the result
of a mass conspiracy by display manufacturers - but
instead reflects the absence of standards and definitions in the field. Incidentally, one of the Society for
Information Displays goals over the next few years
is to establish a concensus on standards and definitions. This paper will attempt to clarify some commonly
used display terms, as a guide to user understanding.
Generally, the discussion will be oriented to commercially available equipment. * Table I is a representative list of manufacturers of commercial graphic
CRT terminals.
TABLE I
Manufacturers of Commercially Available
CRT Graphic Terminals
Bolt, Beranek & Newman, Inc. (BBN)
Bunker-Ramo Corporation (BR)
Control Data Corporation (CDC)
Digital' Equipment Corporation (DEC)
Ferranti, Limited
Information Displays, Inc. (IDI)
Information International, Inc. (III)
International Business Machines Corporation (ffiM)
International Telephone & Telegraph Corporation
(ITT)
Philco-Ford Corporation.
Sanders Associates
Scientific Data Sy'stems, Inc. (SDS)
Stromberg-Carlson Corporation (SC)
Systems Engineering Laboratories, Inc. (SEL)
Tasker Instruments Corporation
UNIVAC
*This is a good place to start defining terms. By "commercially
available" I mean relatively standard products regularly offered for sale - and meant to be used in an industrial rather
than military environment. Admittedly, this is arbitrary
(but, I hope, not capricious) and eliminates from consideration the numerous militarized command and control systems
- and the fine display systems developed in University and
Industrial Laboratories.
149
150
Fall Joint Computer Conference, 1967
Photographs of representative terminals are included
in Figure 1.
Section 2 of this paper briefly reviews the constituent elements of a typical Graphic CRT terminal.
Prices of these terminals range from approximately
$20,000 to $280,000. Generally, as discussed in an
earlier article, 8 price and performance are related.
However, because there are many factors that affect
performance, and the importance. of each factor depends upon the application, the cost-performance relationship is not a simple one. Section 3 of this paper
is a discussion of various factors which affect performance.
Block diagram
A typical block diagram for a Graphic CRT Terminal is shown in Figure 2. Generally, the terminal consists of:
A Direct View Cathode Ray Tube with associated
analog deflection and .video (intensification) circuitry,
plus ...
A Display Generator which contains several types
of function generators to produce graphic elements,
plus (occasionally) . . .
A Storage Element, plus . . . . . .
An Interface between the computer and terminal,
plus ...
A variety of Input Devices from the display to the
computer.
Cathode ray tube
The CRT may be deflected electrostatically, or electromagnetically or by" a combination of both. Commonly used configurations are illustrated in Figure 3.
Table II lists the deflection system used by various
manufacturers.
Most commercially available Graphic CRT Consoles use random positioning to produce a picture.
That is, the beam is moved to the desired location
on the screen and then controlled to produce the
graphic element (line, character, etc.). This is in contrast to the raster scan used in a TV set (and in
most alphanumeric CRT inquiry units). Philco is
one of the few suppliers of a raster scan graphic CRT
terminal. Figure 4 illustrates the difference between
random positioning and raster scan.
Tubes are available with a variety of conventional
phosphors offering a choice of color as well as persistence. Bolt Beraneck and Newman Teleputer System uses a CRT with storage screen.
So that an optically projected image can be combined with the electronically generated image, CRT's
in terminals supplied by Bunker-Ramo and Stromberg-Carlson have a window through which a picture
TABLE
n
Deflection Systems Used by Various Manufacturers
Manufacturer
BBN
BR
CDC
DEC
Ferranti
SC
IBM
101
III
ITT
Philco
Sanders
SDS
SEL
Tasker
UNIVAC
Dual Deflection
ElectroElectroMagnetic
static
static Magnetic Magnetic
Magnetic
+
+
x
:x
x
x
x
x
:x
x
:x
x
x
:x
x
x
x
x
can be projected onto the screen. This is illustrated
in Figure 5.
Display generator
The Display Generator contains the circuitry which
interprets the computer digital data word and translates it into analog signals to generate the graphic
elements on the CRT. The Display Generator is essentially just a digital-to-analog converter (0/A). Typically, the Display Generator will include such function
generators as a character generator, a vector (line)
generator, a circle generator, position generators (conventional D / A converters) and a dot generator.
All of the· graphic elements produced by the various function generators could also be produced by
appropriate computer software. For example, letters
could be programmed as a series of dots, or short
line segments. However, each dot or line segment.
requires a separate digital instruction from the computer and this tends to increase the computer programming. Therefore, although there are under development several interesting and commercially promising
graphic terminals using this technique, all currently
available commercial terminals, except the BBN Teleputer units, use special purpose function generators.
Instead of using a separate character function generator in the Display Generator, the Stromberg-Carlson
console uses a special CRT which shapes the crosssection of the electron beam into the desired character.
This is accomplished by inserting a stencil mask in the
Graphic CRT Terminals
Figure I-Typical graphic CRT consoles,
151
152
Fall Joint Computer Conference, 1967
r------------------------------------------
:
DISPLAY GENERATOR
'
I
:,........---...
INTENSITY
MINOR
DEFLECTION
c::J
LIGHT
PEN
~
MAJOR
DEFLECTION
INTENSITY
MINOR
DEFLECTION
L ___ - - - - - - __________________________ -J
MAJOR
DEFLECTION
+-,L:(7] FUNCTION KEYS
~~
KEYBOARD
Figure 2-Graphic CRT display
CRT. The beam is extruded through the appropriate
aperture and the beam cross-section assumes the
shape of the selected character.
Terminals often contain several other modules which
modify the outputs of the function generators. In IDI
terminals, for example, a digital size control is usually
associated with the character generator. By using one
or two digital bits, two or four character sizes can
be programmed. A line structure control is sometimes
included. This permits programming a line to be dotted,
dashed, or dash-dotted as well as solid. While this
could also be done with software, the hardware alternate allows the control to be done with one or two
digital bits, without increasing line drawing time. Hardware is often included so that the intensities of graphic
symbols can be digitally controlled. Any of the graphic
elements can also be made to blink, that is, turned off
and on at low frequency (about 5 cps).
and modifiers. In most terminals, several other hardware functions are assigned to the Mode Control. For
example, characters can be arrayed in typewriter fashion, as on this page, with the Mode Control, Spacing
can be automatically adjusted to character size. When
the end of the line is reached, the line can be automati~ally reset to the left hand margin (or to a programmed margin) and then advanced to start the
next line of characters. Characters can be rotated CCW
by 9~o and written vertically starting at the bottom
of the screen; or the characters can be superscripted
and subscripted. Logic for connecting (or stringing)
line segments can be included. Once the first line is
established, only the successive end points of the line
segments need be outputted to the Display Generator.
Special modes for curve or graphic drawings can be incorporated. The Mode Control may include address and
index registers to facilitate programming.
At the input to the Display Generator is a Mode
Control. The Mode Control decodes the computer data
word and activates the appropriate function generators
The design of the Mode Control represents the
manufacturer's trade-off decision betwen computer software and display hardware.
Graphic CRT Terminals
SCREEN
--------
..... -
...
---- ....
153
--- .............
------ .......
_----4--~----~
--- -- - ..--------c-
3A.
ELECTROSTATICALLY DEFLECTED CRT
+
Y DIRECTION
~ X DIRECTION
A. RASTER SCAN
38.
MAGNETICALLY DEFLECTED CRT
SCREEN
DEFLECTION PLATES
3C.
DUAL DEFLECTION CRT
ELECTROSTATIC PLUS MAGNETIC DEFLECTIONS
SCREEN
,Y _DIRECTION
~ X DIRECTION
J'JL_--~
LOWER INDUCTANCE
DEFLECTION COIL
3D. DUAL DEFLECTION CRT
TWO MAGNETIC DEFLECTION SYSTEMS
Figure 3--Commonly used deflection systems
Storage
In most CRT graphic terminals, the image must
be repeated (refreshed) in order to appear flicker-free*
to ~e user. If a terminal does not contain a storage
device, the computer must continually refresh the display.
. Man~ modern computers have a memory configuratIOn which can be used to refresh the display without
interrupting other computations. Where this is not
possible, a buffer memory is available within a display. Commercial terminals use core memories, delay
*"Flicker-free" is a term which will be discussed in Section 3.
B. RANDOM POSITION
Figure 4-Basic deflection schemes
lines, and drums. With the availability of low cost
high-speed, general purpose, digital computers, it be~
~omes feasible to consider including a digital computer
In the CRT graphic terminal. BR, DEC, and IDl offer
terminals in which the digital computer is an integral
part of the display and provides functions of storage,
plus some of the hardware mode control features.
As stated earlier, BBN terminals use a storage CRT
so that the image need be written only once and the
local memory is not required. However, these storage
tubes cannot be easily used in systems in which the
operator wants to use a light pen to input graphical
data to the computer.
154
Fall Joint Computer Conference, 1967
easily read; or, when small, to be easily distinguishable.
2. Those which affect the quality of the display . . .
that is, how the display looks aesthetically to the
observer, and
3. Those which affect the ease of use . .. both from
a human factors standpoint and from a systems
programming standpoint.
There is, of course, some "spill-over" among categories, but the categories provide a convenient frame
of reference for the discussion which follows.
Figure 5-Using a ported (window) CRT to combine projected
Interface
Because CRT graphic terminals are available from
manufacturers who do not make the computer with
which the display is to operate, an interface is usually
required to convert the computer output into a form
suitable for the terminal. The conversion may include
reorganization of the data words, conversion of logic
levels, and generation of appropriate communication
signals.
Input deviCes
The discussion thus far has been about a one-way
device; information is received from a computer, converted in the Display Generator, and presented -as a
graphic image on a CRT. However, one of the basic
reasons for the increasing acceptance of CRT graphic
terminals is the availability of an operator channel
from the display back to the computer. The operator
can converse with the computer on-line* and in realtime* using input devices such as a light pen, joy
stick, track ball, Rand tablet, and function keys.
Factors which affect performance
As can be inferred from the foregoing discussion, a
graphic CRT terminal is a conglomerate of devices,
each of which has a range of characteristics which can
affect' the performance and useability of the terminal.
For convenience, the various factors which contribute
to the effectiveness of the terminal can be grouped into
three categories:
1. Those which affect the data content . . . that is,
how much information can be displayed simultaneously without flickering objectionally and
with the graphic symbols large enough to be
*"On-line" and "real-time" are fairly abused terms in the
computer world, and are used here without being rigorously
defined. The sense is to describe J.G.R. Licklider's " ... 'online people,' which is to say, people who are interacting
directly with information and with information processors."9
Data content
The amount of data which can be displayed simultaneously, without appearing to flicker cannot be determined until one explores the concept of "without appearing to flicker."
"Without appearing to flicker" or alternately, "flickerfree" is not a factor to which a single number can be
assigned (as most manufacturer's are prone to do).
Perceptible flicker varies with individuals and has been
found to be a function of such factors as the individual's age, the color of the light, whether the individual
is looking directly at the object or looking out of the
corner of his eye, the brightness, the brightness variation, the variation between light and dark, ~nd the size
of the flickering object. Typical studies of flickero
use phrases like "the average observer" or "90%
of the observers" to bound statements about observable
flicker. H. Poole! presents a curve, reproduced as
Figure 6, which relates critical frequency (frequency
below which flicker is observed) to brightness. However, the data in Figure 6 make no allowance for the
persistence of the CRT phosphor.
The typical CRT non-storage phosphor used in commercially available consoles retains an image for times*
ranging from about 40 USEC to 0.6 seconds, as summarized in Table III. For these typical phosphors, J.
BrydenlO has experimentally determined (for a specified test condition) the "lowest refresh rate which
will give freedom from flicker for 90% of the observers," and this experimental value is tabulated in
Column 6 of Table III. Note that although Figure 6
indicates a critical frequency of about 50 cps at a
* Phosphors are categorized by the length of time required
for the image to decay to 10% of its initial value. Phosphor
classifications are summarized below.
Time Required to Decay to
10% of Initial Brightness
Phosphor Classification
Very Short (VS)
Less than 1 USEC
1 USEC to 10 USEC
Short (S)
10 USEC to 1 MS
Medium Short (MS)
1 MS. to 0.1 SEC
Medium (M)
Long (L)
0.1 SEC to 1 SEC
Longer than 1 SEC
Very Long (VL)
Graphic CRT Terminals
/
/
V
~
V
/
V
'/
/'
60
eo
40
30
20
10
o
.01
.1
10
100
BRIGHTNESS. FOOT - LAMBERTS
Figure 6-Critical flicker frequency as a function of brightness
brightness of 50 foot-Iamberts, the data in Table III
show that 90 % of the observers will not see flicker
at frequencies greater than 21 cps to 38 cps, depending on phosphor. J. Bryden presents another tabl~
(Table 4.1) which lists "Refresh Rate (cps) for Flicker
Threshold of A verage Person at 50 foot-Iamberts".
These values, listed in Column (7) of Table III range
from 17.5 cps to 33.5 cps depending on phosphor.
The purpose of detailing the varied results is to
emphasize that a simple statement of "flicker-free"
preseIltation is an inadequate user (or manufacturer)
specification. (Of course, if the console uses a storage
CRT, the image need not be refre~hed until intentionally erased, or until decay after relatively long
time measured in minutes; and the question of a flickerfree presentation is not meaningful.)
a)
Frame Rate
The basic problem, then, is deciding how many
times per second the image needs be repeated (or
refreshed) so that it doe& not appear to flicker to
the observer. Having decided this flicker-free rate,
the time available to write a complete frame of data
is simply the reciprocal of the rate . . . the faster
the refresh rate, the shorter the time available per
frame.
Why not always use a longer persistent phosphor,
thereby reducing frame rate and increasing time per
frame? For several reasons: (1) Shorter persistent
155
phosphors, such as the P31 (medium-short) tend
to be more visually efficient and look brighter to
the user. This is illustrated by Column (5) of Table
III which lists J. Bryden's test results showing the
brightness for several phosphors under identical test
conditions. (2) Long persistent phosphors, like the
P19 and P28, are more easily burned than the
medium-short persistence P4 and P31. (3) If the
terminal is displaying a rapidly moving graphic element, the long-persistent phosphors tend to smear
the image. (4) Brightness is a direct function of
frame rate.
In order to provide a standard reference in the
balance of this paper, all frame-time dependent
values and references to flicker-free presentations
in the following discussions are based on a 40
cycle frame rate (or 25 MS frame interval). Keep
in mind, however, that the data content can be
increased in direct proportion to frame interval. For
example, if a flicker-free data content of 250 points
is quoted, it is understood that the calculations are
based on 25 MS frame interval.
If, for example, in a particular system, with a particular phosphor, a frame interval of 50 MS (frame
rate == 201 second) were acceptable, the number of
points could be increased to 500.
b) Deflection Amplifier Response
A primary parameter of a CRT display is the
speed with which the beam can be positioned. In
random positioned systems, the beam can be moved
anywhere on the screen in times ranging from 3
USEC to 100 USEC. A complete specification of
deflection time should include a statement of the
accuracy to which the beam has settled within the
quoted time. For example, the quoted random positioning time of IDI systems is based on settling to
within ±0.1 % of final value. Until recently, electrostatically deflected CRT's tended to exhibit the
fastest random positioning times. The new electromagnetically deflected Tasker console, however, is
reported to have random positioning times as fast
as commercially available electrostatic units.
The number of random dots which can be displayed, flicker-free, ranges from 250 to 8300.
If the data can be properly formatted, it may be
possible to organize the information so that full
screen random positioning from dot to dot is not
required. Under these circumstances, the small angle
(incremental) positioning time of the deflection
amplifier is critical. In commercially available equipment, this ranges from 1 USEC to 10 USEC. Therefore, the number of incremental dots which can be
displayed flicker-free ranges from 2500 to 25000.
156
Fall Joint Computer Conference, 1967
Note that these factors are based on the assumption that the system uses random positioning. There
are systems, however, which use a raster scan similar
to that used in a conventional television set. Such
systems require complete formatting of the data.
However, by doing so, as many as 1,000,000 dots
can be displayed flicker-free, compared to a maximum of 25,000 dots in a random positioning system.
As illustrated in Figure 3C and 3D, and Table II,
many consoles employ dual deflection. This second
deflection channel, typically wide bandwidth (DC
to 50 MC) and small angle deflection, is used for
character writing.
c) Character Writing Time
Character generators available in commercially
available terminals write a character in times ranging from 2 USEC to 100 USEC. To these times
must be added the positioning time (ranging from
3 USEC to 100 USEC random or 1 USEC to 10
USEC, small angle). Therefore the number of random characters that can be displayed flicker-free
ranges from 125 to 5000, and the number of formatted character (text) that can be displayed flickerfree ranges from 220 to 8300. As a comparison, a
typical double spaced typewritten page contains about
2500 characters.
d)
Line Drawing Time
Two types of vector (line) generators are offered
in commercially available equipments. One type requires a fixed time to draw a line regardless of line
length, while the other requires a time proportional
to line length. Typical fixed time vector generators
require from 30 to 150 USEC to draw lines up to
full screen size, while the proportional vector generators have line drawing speeds ranging from 0.5
USEC per inch to 150 USEC per inch. This means
that the fixed time vector generators can draw between 160 and 830 flicker-free line segments per
frame. Depending on CRT screen size, this can
represent up to 16,000 inches of line. Proportional
vector generators can draw from 160 to 50,000
inches of flicker-free line per frame.
e) Circle Drawing Time
Hardware circle generators available with some
terminals can generally draw any size circle in from
100 USEC to 300 USEC. This means that from 83,
circles to 250 circles can be displayed flicker-free.
f) Logic Time
In addition to the actual time required to deflect a beam and write the various functions, the
logic in the Display Generator, the logic of the com-
puter, and the memory cycle time will affect the
amount of data which can be displayed. For example,
the word organization of the terminal may require
that the generation of each graphic element be controlled by several data words. Elapsed time from
the display's request for a data word and the terminal's set-up is in the order of 1 to 4 USEC. If 1,000
data words were required per frame (a typical
value) and between 1 and 4 USEC were consumed
in data transfer and logic set-up, 4% to 16% of
the frame time would be consumed and the data content would be reduced by that amount.
g) Resolution
Resolution determines such things as the smallest
readable characer that can be displayed, and the
minimum spacing that can be discerned between
lines. Basically, CRT beam spot size determines
resolution. In commercially available terminals, the
nominal spot will range from .01" diameter to .03"
diameter. * However, spot size might vary by a
factor of 3: 1 (on the same terminal) because of
beam intensity and spot position on the screen
(better in the center, poorer at the edges). Some
terminals use dynamic focussing techniques to keep
the spot size relatively constant over the display area.
Without being rigorous about defining resolution and spot size, one can observe that the resolution
of commercially available terminals is such that the
number of readable characters per inch ranges from
about 3 to 11. For comparison, a Pica Typewriter
spaces characters 10 per inch, and an Elite Typewriter spaces characters 12 per inch.
Addressability is sometimes confused with resolution. Addressability is a statement of how many
digital positions can be programmed (but not necessarily distinguished) along each axis. Typical terminals offer 9 bit (512) or 10 bit (1024) addressable
locations.
h) Screen Size
Screen size affects data content primarily from
the standpoint of resolution. CRT's used in commercial terminals generally range from 16" round to
24" round, * with available display areas of from
10" X 10" to 16" X 16". Therefore, the number of
readable characters per line can range from 30 (based
upon a 10" line of 3 characters/inch) to 176 (based
upon a 16" lnie of 11 characters/inch).
*Determination of spot size, and the correlation between spot
size and resolution is another area requiring the attention
of a standards committee. J. Bryden's paper includes an informative discussion of his measurement techniques.
*Except the BBN terminal which uses a 5" CRT.
Graphic CRT Terminals
i) Overlays
Static information can be superimposed on the
beam written data by projecting pictures (slides)
through an optical port in the CRT. Typical systems
can select from among 25-150 slides.
Quality
Several factors affect the image quality. Some of
these factors may also affect data content, as indicated
in the following discussion:
a) Accuracy-Accuracy describes how the programmed position of the beam corresponds to some
eternal reference. For example, if a grid were scribed
in the face of the CRT and the beam were programmed with a digital instruction which should cause
the beam to fall at a grid line intersection, the variance between the beam position and the intersection
is the accuracy. Commercially available systems have
accuracies ranging from 1 % to 5 % of full scale.
(Compared, for example, to a reasonably well adjusted frame TV set -which ranges from 10% to
15%.) Generally, pictures drawn with this accuracy
are quite acceptable to the observer provided there
is no attempt to superimpose the electronic image
with a mechanical reference. The presence of the
mechanical reference will emphasize the inaccuracy
of the ,display.
b) Short-time Stability----Short-time stability of the
image will affert the observer's reaction to it. Small
movement of the graphic element, called jitter, can
be quite objectionable when it occurs at low frequencies (less than 10 cps). Jitter results mainly
from a beat between the frame face and the power
line frequency (or submultiple frequency). In an
adequately shielded terminal, the jitter is about 0.5
to 1 spot-but even this value can be disturbing
to the user.
Two methods are used to reduce or eliminate the
apparent jitter. One is to maintain the frame rate
at such a value that the beat frequency is relatively
high . . . typically 20 cps. Although jitter still may
be present, the graphic element is moving so fast
that, to the observer, thee,line or dot simply thickens
a bit. Hence, the resolution is affected, but the
image appears stationary. This technique is especially successful when used with longer persistent
phosphors.
Alternately, since the jitter most frequently comes
from stray magnetic fields, the display frame rate
can be locked to' the line frequency and the jitter
essentially eliminated.
c) Repeatability-When the beam is programmed
to the s,ame location from various places on the
157
screen, the successive dots will probably not be
superimposed. The spread, called repeatability, may
range from 1 spot size to 10 spot sizes. In commercially available equipment this effect may be
particularly disturbing when various line segments
are programmed to start from the same point, but,
because of repeatability, they do not.
d) Brightness and Contrast-If the display is to be
used in a normally lighted room, it is important that
the presentation be bright or have a high contrast
ratio. Typical terminals produce 20 foot-lambert to
50-foot lambert presentations. Medium-short persistent phosphors, such as the P4 and P31 do produce
bright, easily read displays, but these phosphors require relatively high frame rates to reduce flicker.
Long persistent phosphors, such as P 19 and the
P28, reduce the frame rate requirements at the expense of brightness. Therefore, displays using long
persistent phosphors may require subdued room illumination. Contrast can be enchanced with neutral
density filters. Although these filters reduce total
brightness, they do increase and enhance the readability of the display.
e) Phosphor Color-Phosphors are available which
produce white, green, yellow, blue, and red outputs
(and shades in-between). The medium-short persistent phosphors are generally in the white, green
and blue range; while the long persistent phosphors
are in the orange, yellow range." See Table 111."*
f) Graphic Symbol Construction-Graphtic elements
can be constructen in a variety of waysll . . . some
of which enhance the quality of the display and others
which tend to detract from it. For example, characters formed from a 5 X 7 dot format may be readable but not aesthetically satisfying. Other gr~phic
e1.ements constructed from a series of dots may be
readable, but not pleasing.
Stroke characters usually produce acceptable quality. The beam forming and monoscope* techniques
permit a wide range of character formats, with few
limits on character style. Higher resolution dot formats, typically 16 X 16, are also capable of producing
excellent quality symbols.
Ease of use
There are two categories discussed in this section;
those which are based on human factor considerations
and those which are based on programming considerations.
a) Human Factors-The plane of the CRT screen
:~The
monoscope prod"uces character video by election beam
scanning of a target on which characters have been drawn
in ink. Typical commercial monoscopes, such as the Rayth~on
Symbolray, use targets with 64 or 96 symbols.
*Table III is shown on page 159
158
Fall Joint Computer Conference, 1967
ranges from vertical to approximately 45 0 from the
vertical. Generally, this is fixed although a CDC
unit features tiltable display screen (essentially continuously variable between vertical and horizontal).
A variety of light pen configurations are available ranging from a simple penholder type to a
gun type. Some pens are relatively heavy while others
are light weight. Some use a very flexible cable and
others use a rather stiff cable or coil cord. Aiming
circles are provided with some light pens so that
the operator knows where the sensitive area of the
light pen is pointed. Activating switches for the light
pen include mechanical shutters on the pen, electrical
switches on the pen, knee switches and foot pedal
switches.
Other operator input devices are available on
various consoles. Alphanumeric keyboards and function keys are used. Some function keys use plastic
overlays for additional coding. Track balls and
joy sticks are preferred by some users. The Rand
Tablet, which provides an easy method for graphic
input, is available as an accessory in several systems.
Operator controls on commercially available terminals range from only an on-off power switch, to a
group of manual adjustments for various display
parameters.
Servicing facilities incorporated in terminals range
from logic card extender to elaborate maintenance
panels, which include register lights and test pattern
generators.
Terminal packaging ranges from multiple cabinet
configurations, with the display console separated
from the display generator, to single cabinet integrated units which occupy 10-15 square feet of floor
space, and are 4-5 feet high.
b) Systems Programming-The display command
structure influences system programming. Two common types of command structures are shown in
Figure 7. In one approach, illustr~ted by Figure 7A,
each data word is completely self-contained and has
a mode instruction and all other information required to define a graphic element. In contrast, the
word organization currently favored (Figure 7B)
establishes a mode of operation with one word and
then uses a series of succeeding data words to program. identical kinds of graphic elements. Figure 7B
also illustrates a word organization which includes
computer-type instructions such as JUMP and JUMP
AND SAVE.
Some graphic terminals such as the CDC, DEC,
IBM, and IDI are designed so that more than one
display console can be driven from a common Display Generator. These other consoles may be slaved
(and have identical information) or they may have
FUNCTION
0
1
POSITION
Mode
3
2
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
V
X position
00
V
X Position
Mode
DOT
01
Mode
CHAR.
10
VECTOR
~
Y Position
CHAR. 2
CHAR. 1
VI
X position
Mode
Y Position
11
FIGURE
I
CHAR. 3
Y position
7A
TYPICAL WORD ORGANIZATION
(MODE CONTROL CODE IN EACH WORD)
FIGURE
7B
TYPICAL WORD ORGANIZATION
(CONTROL WORDS AND DATA WORDS)
Program Control Word
1
1
0.1
1
1 11
a
I LPI F
I
TYPE
I
BL"
INT
X Coord
Z
Y Coord
BI
Vector Mode Control Word
Vector Data Word Pair
Dot Increment Mode Control Word
Dot Increment Data Word
symbol Mode Control Word
Symbol Data Word
/6S
lINT
CHAR 2
11
Packed Symbol Mode Control Word
Packed Symbol Data Word
(77 • escape)
8
LP
.. disable light pen
BL
Z
F
• enable blink
• blank
• frame sync
1NT
•
00
01
10
11
-
nomal
dim
bright
off
TYPE • 00
01
10
11
-
position
Position, Write Dot
dash
solid
X,
y . 001 +1
010 +2
111 -1
110 -2
Others - no increment
/6s
• 00 - nomal, no offset
01 - small, superscript
10 - small, subscript
11 - small, no offset
MAR· 00 - N/6P
01 - set margin
10 - return to margin
11 - return to margin· and
line feed
*Thes? bits do n0 7 actually control the Display, but are included to
provl.de prograllUung mode canpatibility.
Figure 7-Typical word organization
different information. Such displays may be photographed or used to produce wall size pictures or
immediate hard copy.
SUMMARY
This paper has discussed the characteristics of commerically available terminals from an equipment viewpoint - not from an applications viewpoint. .One can
list a number of current and potential applications for
CR T graphic terminals, but data which describe terminal requirements in terms of these applications are
Graphic CRT Terminals
scarce. For example, the line drawing needs of a
terminal used by civil engineers for cut-and-fill analysis
may be quite different from those of an engineer using
the terminal to design integrated circuit masks. Adams
Associates, in their "Computer Display Review" formulated several typical presentations including a schematic diagram, floor plan, and weather map - and,
using terminal manufacturer's supplied performance
specifications, analyzed how long each terminal would
take to write the display.
Generally, though, the terminal user considers his
data (applications) content requirements proprietary,
and seldom publishes his findings. We can expect, however, that over the next few years, many more "How
Application Factors Determine CRT Terminal Specifications" papers to appear.
Sparton Books Washington D C 1966
HOWARD
Electronic information displays for management
American Data Processin~ Tnc. Detroit Michigan 1966
L C HOBBS
Display applications and technology
Proceedings of the IEEE vol 54 no 12 December 1966
D B PARKER
Solving problems in graphical dialog
IEEE Computer Group News vol 1 no 2 September 1966
R L WIGINGTON
Graphics and speech computer input and output for
communication with humans
Computer Graphics Utility-Production-Art
Thompson Book Co. Washington D C 1967 pp 92-96
C MACHOVER
Family of computer-controlled CRT graphic displays
Information Displays Inc July I August 1966 pp 43, 46
J C R LICKLIDER
Graphic input-a survey of techniques
Computer Graphics Utility-Production-Art
Thompson Book Co Washington D C 1967. p 43
J E BRYDEN
Some notes on measuring performance of phosphors ill
CRT displays
Seventh National Symposium on Information Display.
Technical Session Proceedings Society for Information
Display 1966
C MACH OVER
Converting data to human interpretable form
Data Systems Design vol 1 no 9 September 1964
J H
4
5
6
7
8
9
REFERENCES
Computer display review
Adams Associates Inc 128 Great Road Bedford
Massachusetts
2 Compendium of visual displays
(RADC Compendium 67-1, Rome Air Development
Center Research and Technology Division Air Force
Systems Command USAF Griffiss Air Force Base
New York March 1967) 2nd revision
3 H H POOLE
Fundamentals of display .'iy.~tems
10
11
LUMINOUS
EMMYSSION COLOR
TYPE FLUORESCENCE PHOSPHORESCENCE
(1)
(2)
(3)
PERSISTENCE
(4) (SEC)
FLICKER FREE RATES (CPS)
otrl'PUT
"1' 50 FT - :.AMl!ERT~
FOOT-LAMBERTS Average
90% of
(5)
Person (6) CI>.ervero (7)
P4
White
!alite
5.2
33.5
38.
P7
Blue
Yellowish Gr .... Blue 5 x 10- 5_
Yellow v x 10
5.2
3.0
29.8
33.
Pl9
Orange
Orange
2 x 10- 1
P28
Yellow Green
Yellow Green
6 x 10-
Green
4 x 10- 6
P31
NOTE:
159
1
3.0
17.5
21.
5.2
31.4
38.
12.0
32.5
36.
Column (2) Fluorescence is the light emitted by the phoaphor during the period.
of electron beam exci tation.
COlumn (3) Phoaphoreacence is the light emitted lw the phosphor after the
electron beam. excitation ia removed.
Column (4) Tinte for initial output to decay to 10% of initial value.
Column (5) Fran Table 3.1 of Reference 10.
Column (6) From Table 4.1 of Reference 10.
Column (7) Fran Figure 4.4 of Reference 10.
~
TYPICAL PHOSPHORS USED IN COMIIERCIALLY
AVAILABLE GRAPHIC CRT TERllINALS •••••••
A SUMMARY OF CIIARACTERISTICS.
How do we stand on the big board?
by MURRAY L. KESSELMAN
Rome Air Development Center
Griffiss AFB, New York
INTRODUCTION
When is a display a large scale display? There are no
hard and fast rules for answering this question. An
arbitrary, but convenient starting point is to say that
anything larger than 30 inches is considered large
scale because 30 inches is the practical limit on cathode
ray tube (CRT) size. Why should we want a large scale
display? The most obvious reason is that many people
have a need to view the same display surface and as
the audience grows larger, so must the size of the
display.
To illustrate this, Table I provides estimates of the
audience area available for views of a given display
size. The actual number of viewers will depend on
the. space allocated to each viewer.
make them desirable for many applications. Some of
these are:
1. In many cases, it is advantageous for an operator
to have information concerning the overall environment
within which he is functioning. He is better able to
anticipate future problem areas and he is in a position
to assume the functions of associated operators when
he has knowledge of the overall system status.
2. In presenting available information to a group of
individuals by means of a common display, there is
some assurance that all persons are reacting to a common data base. This is a critical consideration in a
rapidly changing environment where many people are
pursuing interrelated tasks toward a common goal.
When operators are "buried" within the confines of a
console, the particular information being reacted to
might be out of date or differ in some respects.
3. In an environment where a group of people require the same or very closely related information, a
large display may be more economical of money and
space. The addition of individual consoles may provide
nothing but a duplication of data that are already available in a form suitable to the accomplishment of a
particular mission.
4. The physical configuration of a particular work
space may indicate one centrally accessible source of
information rather than a number of independent ones .. /'
A particular environment may have size limitations
that only a large display can adequately serve. An
unused wall may be the only means available for the
presentation of required information.
5. One display may present less of a maintenance
problem than would a large number of consoles that
require periodic servicing. This could result in a saving
of manpower and of downtime with regard to overall
display capability.
TABLE I
SCREEN SIZE VS AUDIENCE AREA
WIDTH OF SCREEN
AUDIENCE AREA (sq ft)
40 in
120
60 in
340
7 ft
654
8 ft
848
9 ft
1078
10 ft
1338
This table is based on a rule of thumb that no viewer
should be closer than two times the maximum screen
dimension nor further than six times. The maximum
viewing angle of any observer to the plane qf the screen
is considered as being limited to 60 0 in making these
calculations.
As we have seen, the size of the display is determined
by the number of viewers. You may then ask the question "why not provide each viewer with an individual
display?". This is plausible under certain conditions, but
large scale displays have unique characteristics that
161
162
Fall Joint Computer Conference, 1967
9. Marketing Analysis
10. Product Planning
6. When one individual can control the composition .of a display, he can "force" the attention of all
individuals concerned to one problem area. The capability to direct group activities in a required direction
ensures that the lower echelons of a unit have the
same reference point as the person making the ultimate
decisions. All observers are using the same data base as
indicated previously.
7. A large display can be viewed from a greater
number of locations than can an individual console.
The factor permits a degree of mobility and flexibility
among interested personnel not afforded to individual
console operators.
Current state of the art
There are a limited number of available off-the-shelf
approaches to the generation of automated large scale
displays. The current technology includes rapid process
film systems, scribe systems, light valves, and projection
CRT's. A brief discussion of each technique follows:
1.
Film systems
Present photo-recording equipments consist of a
cathode ray tube (CRT) which provides a source
image, a light sensitive medium on which the CRT
image is recorded, and a processor which produces a
positive transparency suitable for projection (Figure 1).
Special cathode ray tubes are used to convert electrical signals to alphanumeric and vector images suitable for photographic recording. These are generally
five or seven inch flat face, high resolution CRT's
with electromagnetic deflection and focus, and use
P-l1 phosphor as the light emitter. The cathode ray
tube image is focused onto a film by means of a special
camera. To form a multicolor image, three or four
cameras are operated in parallel with each camera
exposing a different portion of the film. During projection, each film area is projected with a different color
filter and the images are superimposed at the screen
Use of large scale display
As can be expected, the uses of large scale displays
are varied and manifold. It is beyond the· realm of this
paper to discuss this subject in any detail. The following
is a partial list of present and future applications of
large scale computer driven displays:
1. Briefing
2. Corporate Planning
3. Simulation
4. Business Gaming
5. Situation Monitoring
6. Traffic Handling
7. Training
8. Education
Conde n sing System
Color
Filters
Matched
Projection
Lens
Shutte rs
Transparent Expose
a Processing Station
Optics
Waste
Figure 1-Multi-color film processor and projector
How Do We Stand on the Big Board?
to form a single multicolor image. To properly control
the color of data, each camera has a shutter which is
opened or closed, depending upon the color instruction
from the computer. For example, to generate the green
portion of a multicolor image, the proper shutter is
opened, "green" data is written on the CRT, exposing
the "green" frame on the film. Then after the other
exposures have been made, the image is processed and
projected.
The other colors are formed in the same way. For
mUlti-component colors, more than one shutter is
opened for a particular exposure.
Silver halide emulsion is the most widely used light
sensitive medium for recording the CRT image. The
absolute sensitivity of silver halide is such that character exposure times of 50 to 1000 microseconds can be
used. It can be seen from Figure 2 that the spectral
response of a blue-sensitive film such as Ansco Hyscan
is relatively flat out to 500 millimicrons, and well
matches the output of the P-l1 phosphor which peaks
at approximately 460 millimicrons.
~n~xpo.ed
~
Expose
_
Develope
~
Bleach
W
~ ~
Re-Expose
%
~
%
Redevelope
M"I
@iI
W
a Fix M}IJ W'J
vJM.
Wash
163
REVERSAL
Legend
~ Unexposed
Sliver Ha II de
PARTIAL REVERSAL
m
Silver
~ Sen'ltized Silver
Halide
Figure 3-Reversal processing
Blue Sensitive
",Film
cu
1.0
1/1
c::
o
0.
1/1
cu
a::
_0.5
cu
a::
400MU
500Mjl
Wavelength
Figure 2-Film phosphor spectral characteristics
The demand for rapid response in computer-type
displays has been met by the development of rapid
processing techniques. The process consists of the use
of special films containing hardened, large grain emulsions which make them suitable for processing at
elevated temperature without appreciable loss in image
quality. Total processing times of five to ten seconds
can be achieved with developer temperatures of 13,0 0
to 140 0 F. The negative image produced in conventional film processing is not suitable for projection in
a color additive process and therefore reversal processing is used to obtain a positive image. The steps in, volved in reversal processing are: (Figure 3)
Develop-Reduces the exposed halide crystals to
metallic silver and leaves unexposed areas unreduced.
The light energy absorbed by the exposed crystals increases their sensitivity to the developer and consequently they are reduced before the unexposed crystals.
Bleach-Converts the metallic silver into a water
soluble compound so that it can be washed from the
base material.
Wash-Removes the soluble products of the bleach
process and leaves the exposed areas of the film clear,
and the unexposed areas, which contain silver halide,
opaque.
The previous three steps constitute a partial reversal
process. The final image is the clear information areas
against the unexposed silver halide background. To obtain a full reversal process, the following steps are
added:
Re-expose-Sensitizes the remaining si1ver halide by
exposure to light.
Redevelop-Converts to metallic silver the exposed
silver halide crystals.
Wash-Removes remaining chemicals.
Under zero ambient illumination conditions, the partial reversal processes are capable of producing an
image contrast of better than 50 to 1, and full reversal
processes a contrast of better than 100 to 1. In applications where the surface area to be illuminated is
greater than 150 square feet, the increased contrast afforded by the full reversal process can compensate for
the lower display brightness resulting from the large
screen area and enhance display legibility.
164 Fall Joint Computer Conference, t967
technique in two large screen applications and in a
small screen application.
Valves
TABLE II
PERFORMANCE CHARACTERISTICS
Full
Reversal
To Atmosphere
Chemical Supply Tank
Waste
Tank
PULSED FLOW
Developer
Fix
Wash
Heat Exchanger
Process
Pump
Figure 4-Basic fluid handling systems
There are two systems of chemical fluid handling
currently in use; continuous flow and pulsed flow. Both
of these techniques maintain the processing chambers
below atmospheric pressure to lower the probability of
leaks:
In the continuous flow fluid system, the processing
fluids flow continuously through separate channels and
the film is moved across each head sequentially in such
a way as to come in contact with the required chemical
at the proper time. The supply tanks are then maintained at some temperature less than that required for
processing to extend the life of the chemicals and a
heat exchanger provides the capability of heating the
chemicals to the proper temperatures as needed. With
the pulse flow system, the chemicals required for processing of the film pass sequentially through a single
processing head. Normally-closed solenoid actuated
pinch valves are used to sequentially open the appropriate fluid lines and allow chemical flow, and then to
close the line after the required quantity of chemicals
have flowed into the head. This technique is more
reliable since an air pump is used, and because only
one head seal is required.
Table II is a tabulated summary of the pertinent
performance parameters of three systems which utilize
this technique for their display capability. The values
of the individual parameters do not necessarily represent a maximum, but rather represent a set of performance characteristics which have been achieved.
This summary includes the practical results of the
Projection Scheme
Screen Size (Ft)
Projection Distance (Ft)
Incident Illumination
(Ft Candles)
Fall-Off (%) of Center
to Edge Brightness
Symbol Brightness
(Ft. Lamberts)
Contrast Ratio
(Zero Amb.)
Symbol Height (Inches)
Colors
Color Fringing (Inches)
Resolution (Line Pairs
Per Screen Ht)
Linearity (%) of
Screen Width
Registration (%) of
Screen Width
Response Time (Sec)
Negative Partial
. Positive Reversal
Front
8 X 8
Rear
1Xt
3
Rear
12X16
22±lA
28±~
26
30
100
22
23
25
13
15
50
150:1
1.63
Seven
0.13
100:1
1.40
Seven
0.12
30:1
0.210
Four
N/A
940
910
1000
0.5
0.5
0.5
N/A
10
1.0
15
0.7
15
In summary, film systems can provide high quality,
colored, large scale displays of almost any size. They
are simple to integrate into data processing systems
and present no unusual demands on the data processor.
They gre mechanical devices and utilize corrosive
chemicals heated to high temperatures. Film systems
by their very nature are static displays and best applied
to tasks such as status monitoring and other functions
where the 10 to 15 second update delay is not objectionable. They are available off the shelf from many manufacturers.
2. Scribe systems
Scribe projectors can provide the dynamics lacking
in the film approach to large scale displays. These devices resemble a miniaturized x, y plotter. They utilize
a servo controlled stylus to scribe lines through opoque
metallic coating on a transparent base material (Figure
5). The resultant image is then projected by a conventional optical system which resembles a 35mm
slide projector. Some form of slide storage and access
is usually provided. The scribe projector is usually of
modular design; projection optics, light source, filters,
How Do We Stand on the Big Board?
and scribing mechanism can be interchanged and configured to meet many requirements. Prepared slides
can be substituted for the scribed slide and projected
for use as background material. A cursor can be substituted for the scribing stylus and various combinations of light source and projection optics are available
An analog character generator and a manual input
device may be included in the system. The manual
input device will include a plotting surface and an
auxiliary alphanumeric key board.
~ _____ SI;d......n; ••
I
I
165
TABLE III
TYPICAL SCRIBE SYSTEM PERFORMANCE
Stylus Slew Time
Symbol Scribing Time
Random Position
Adjacent Position
Stylus Positioning
Accuracy
Repeatability
Slide Storage Capacity
Scribing Area on Slide
Resolution at Screen
Slide Changer
Time to Adjacent Slides
60 miliseconds (Full Scale)
10 Symbols per second
20 Symbols per second
.1 % Screen Height
.03% Screen Height
40 Slides
1 in x 1 in
1000 line pairs (1.5 mil
stylus)
500 milliseconds
3. Projection· CRT's
Figure 5-Plotting projector
In an operating system, a group of plotting projectors
generally share a common set of control electronics.
Combinations of plotting, spotting (cursor), and background projectors can be used. Two projectors are
generally provided for each color required. This is to
allow one active projector for current data and one
idle projector to be used as follows. When the display
on the active projector becomes too cluttered and must
be changed, a limited history of past events is transferred to the idle projector. This projector is now
activated and continues to plot, and the previously
active machine is shut off. The slide can be then
changed with no blank display time and the cycle
repeated.
Table III is a brief resume of the typical performance that can be expected of currently available scribe
system.
Scribe systems can provide dynamic displays of high
quality. They are slow devices and can be interfaced
with most remote communications channels. Because
of their versatility, they can be configured to meet
many applications. They are highly mechanical devices
and contain many moving parts which limits the reliability that can be expected of the device. Scribe systems
are best applied where the total amount of data is
limited and where their dynamic characteristics are
desired.
Projection CRT's have been utilized mainly in the
TV mode of operation. They have been widely used
in simulators and trainers to portray to the operator
the world as it would appear to him in an actual
situation. In this application a computer would control the presentation by controlling a camera which
viewed a model of the terrain to be pictured. Projection TV systems have also been utilized to display
computer generated data. Here scan conversion or
direct digital conversion of data is required to provide
a TV format.
Two types of optical systems can be used with projection CRT's. Schmidt optics (Figure 6) provide the
best collection efficiency, but have poor resolution
and high distortion. Refractive optics are of better
quality and can be highly corrected for a given system.
Their optical efficiency is lower and their cost higher
than Schmidt systems. The CRT's used for projection
are 5 or 7 inch tubes and are operated at voltages
in excess of 30 KV. Voltages as high as 80 KV have
been used for some applications. In this range, Xrays can be a serious factor. Life of the projection
CRT is severely limIted by degradation of the phosphor and darkening of the face plate due to electron
bombardment.
Typical performance of a Schmidt TV projection
system is:
Resolution
Light Output
Screen Size
Throw Distance
CRT Voltage
Tube Life
600 TV Lines
200 Lumens
5 ft to 15 ft
10 to 25 ft.
40 KV
500 hrs.
Projection CRT's have been used for direct dis-
166
Fall Joint Computer Conference, 1967
CRT
~
[ Spherical
Mirror
Corrector
Plote
Projection
Lens
J
SCHMIDT OPTICS
REFRACTIVE OPTICS
Figure 6-Projection CRT systems
play of computer generated data, but the results to
date have been poor. The resolution of available CRT's
is not high enough for this mode of operation. Also
protection of the phosphor and face plate from damage
by a static or slowly moving high energy electron beam
has been difficult.
The low level of general performance has limited
the use of projection CRT's for large scale displays.
Their use has been confined mostly to the display
of pictorial information.
4. Light valve systems
Another approach to the large screen projection
of TV images is the "Light Valve" technique in
which a control medium is used to control the transmission of light from a light source to the screen.
The "Eidophor" is an example of such a device and
uses a thin film of oil as the modulation medium. Figure
7 depicts the basic "Eidophor" operation. In the "Eidopph or" a thin film of oil is continuously applied to a
rotating spherical mirror and mechanically smoothed
to a thickness of .1 millimeter.
The collimated light from a high pressure short are
Xenon lamp source is reflected off the bar system
and onto the oil surface which is contained with
a vacuum tight chamber.
I Electron
Lioht Source
Beam
-
_o~
Electron Gun
MIrror
ProJ ection
Lens
Figure 7.--;"Eidophor" light valve projector
An electron beam impinging upon the oil surface
causes deformation to form in the control layer. Light
passing through the deformed layer is refracted, reflected off the spherical mirror and refracted again;
thus by-passing the stop and reaching the projection
lens to be imaged on the screen. Light striking the nondeformed region of the oil film is imaged back upon
the stops and does not reach the projection lens. By
changing the size of the electron beam, the shape
of the deformation can be changed and the amount
of light passing through the system controlled.
Typical operating parameters are as follows:
Resolution
Light Output-525
line B&W
Lamp Size
Bandwidth
Screen Size (ft)
Throw Distance
Linearity
Cathode Life
1000 TV Lines
4000 Lumens
2500 Watt Zenon
Up to 30 MC
9 X 12 at 50 ft
projection distance
50 ft.
I % screen width
100 hrs
To utilize the Eidophor-to display computer generated information, the data must ce converted into
a form compatible with the TV mode of operation.
This can be accomplished in many ways. Some examples are:
a. View with a camera, the display being created
on a small CRT operating on the conventional random
writing mode.
b. Utilize a double ended electrical-in electricalout storage tube. In this device, the display would
be written onto one side of a storage target in the
random mode and scanned off the other side of the
target in the TV mode.
c. Utilize a digital data converter which, in real
time, converts digital descriptions of the display into
video signals compatible with TV operations.
While the Eidophor overcomes the limitation of
brightness and resolution, it still requires data conversion to effectively display computer generated data.
The present systems contain not only mechanical
systems to distribute the oil but also have a complete,
continuously operating vacuum system which includes
a mechanical pump and an oil diffusion pump. These
me~hanical components coupled with the short life
of the electron gun cathodes limit the applications to
situations where large amounts of periodic maintenance
can be performed and where continuous· operation for
long periods of time is not desired.
How Do We Stand on the Big Board?
CONCLUSION
While large scale display techniques have advanced
considerably in the past few years, these is still much
room for improvement. Their capability to handle
dynamic data needs considerable expansion. Cost
which is now high must be lowered and reliability needs
improvements.
Toward this end, considerable research is now underway to improve existing techniques. New films
which do not need wet chemicals are being explored
along with novel methods of processing conventional
films. Considerable effort is under way to improve the
performance of the light valve technology. Also, new
and tetter techniques are being developed to convert
digital data to the analog form necessary for the
exploitation of TV type devices.
Some of the specific techniques under study now
are:
a. The use of the "Bimat" process where the processing chemicals are contained in an absorbtive
web material, processing is accomplished by placing
the film to be developed in contact with the chemical
167
saturated web and maintaining this contact for a period
of time. A conventional negative and a positive result
from this system.
b. Photochromic flim, a reusable UV sensitive recording media has progressed to the point where prototype equipment is being designed.
c. Laser disp.lays have been under study for some
time. Results at this time are not conclusive and it
is doubtful if any application of the laser to large
scale display is in the near future.
d. Electroluminescence has been under study for
many years. While much progress has been made, we
are still far from applying this technology in practical
systems, but electroluminescence has reached the point
where it can be considered for use as discrete indicators.
With the concerted research directed at improving
the display art and the increased demand for large
scale displays generated by the growth of data processing in to the higher echelons of management, we will
see a dramatic expansion of the _use of large scale
displays.
The CRT display subsystem of the IBM
1500 instructional system
by R. H. TERLET
International Business Machines Corporation
Los Gatos, California
INTRODUCTION
The IBM 1500 Instructional System is an experimental system for computer-assisted instruction, designed to administer individual programmed lessons
to 32 students at once. Working through one or more
teaching devices at his own instructional station, a
student may follow a course quite different from, and
independent of, lessons presented at other stations.
Instructional programs stored in central files control
lesson content, sequence, timing, and audio-visual
medium, varying all of these according to the student's
responses.
Briefly, the system works like this: The processor
retrieves instructional material from the files and presents it on a station input/output device. The student
responds as directed. The processor then compares
his response with the answers anticipated in the instructional program and continues with the next
lesson material or branches to remedial instruction.
The system can keep records of student answers,
response times, and accuracy.
The IBM 1500 Instructional System is shown in
Fig. 1a. The central processor, an IBM 113 1, has
2310 DISK STORAGE
1518 TYPEWRITER
\
,
~
1510 INSTRUCTIONAL
CQ~'~1512 IMAGE
PROJECTOR
~
'
"
"
.
.
.
[]
rn
~
_
1510
~IGHT
1502 STATION
CONTROl.
PEN
1442 CARD
READPUNC~
ffi
~ROC:NGU~
1133
MULTIPLEX
CONTROl.
ENCLOSURE
~~\
1512
,
,,
LJ
1132 PRINTER
Figure la- The IBM 1500 instructional system
169
access to core storage of 32,768 sixteen-bit words
and a cycle time of 3.6 or 2.2 microseconds. Under
direction of the 1500 Operating System, the processor
controls the time sharing of the student stations
(Fig. 1b) and the execution of the instructional pro-
Figure I b - The IBM 1510 Student station
grams. The IBM 1502 Station Control multiplexes
the input and output of the station devices, which may
include an input/output typewriter, an image projector, and an audio play/record unit, as well as the
CRT display to be discussed. Each CRT display
unit includes a keyboard for student responses, and
may include a light pen as well. The 32 CRT display
units, the station control and the processor core
storage together make up the display subsystem.
CRT speed and flexibility make this type of display unit attractive as a basic instructional device.
In sO'me ways, however, the display requirements for
instruction are more demanding than those for conventional data processing applications.
A character set for instruction must often include a
far larger number of characters and symbols than is
needed for other applications. For example, teaching
,-
170
Fail J6int Computer Conference, 1967
a foreign language may require that two different
alphabets be displayed at once. In mathematics, a
display must often include exponents, subscripts, and
fraction lines, as well as alphanumeric characters
and mathematical symbols.
An instructional display must also be unusually
flexible. A student should be able to complete displayed sentences and to insert words within a sentence. It should be possible to display combinations
of simple images and printed text in teaching certain
concepts. To meet the needs of different student
stations and achieve a stimulating variety in lesson
presentation, character fonts should be easily changed.
Finally, to give course authors freedom in varying
the mode of lesson presentation, the CRT displays
should be in a form compatible with the alternative
typewriter printout.
These system objectives were achieved in a versatile display system capable of handling 32 student displays. The CRT display units are of conventional
design, 1 with a magnetic disk buffer to store and refresh the images. Characters and images are positioned under program control. The system is able
to handle any number of large character sets by means
of program-changeable fonts ("dictionaries") placed
directly in core storage, where they are accessible to
the character generation logic and to the system program. Allocation of space for the fonts reduced the
available core storage, already a good deal smaller than is common in multiterminal time-sharing
systems. The problem of satisfactorily sharing the
relatively small core area remaining was solved by
the application of data chaining techniques in core
storage. Here the high interrupt servicing overhead
usually needed to chain blocks of data was avoided
by making such chaining a hardware operation. These
solutions depended on a flexible manipulation of core
storage made possible by the storage access channel
feature of the processor.
Hardware description
The major components of the Display Subsystem,
shown in Figure 2, are (I) the CRT display, keyboard,
and light pen at the student station; (2) the display
control and light pen adapter of the station control;
and (3) the core storage of the processor.
Lesson material called from the disk storage is interpreted by the Operating System and, under the
direction of the display control logic, is translated
from a stream of computer-coded characters and symbols into a sequence of the appropriate displayable
dot patterns. These patterns are obtained from the
dictionaries which occupy a portion of the core
storage. As they are translated, the dot patterns are
DISK FU
Figure 2 - The IBM 1500 display subsystem
temporarily stored, a line at a time, in the line buffer,
before transfer to the video buffer. The video buffer
is a magnetic disk assembly in which a separate recording track, with an associated fixed read/write
head, is assigned to each display unit. This track can
store one complete frame of text and image material,
already coded in the video dot pattern, which can be
read again and again to maintain a continuous display.
The display control logic also generates timing signals that control the vertical and horizontal synchronization of the CRT displays and, during student
light pen responses, serve to identify the pen position
for the light-pen adapter.
The display unit consists of the CRT display, the
keyboard, and the light pen. The CRT display presents instructional text and images to the students.
The keyboard is the major input device for student
entries, which are in most cases immediately displayed on the CRT under program control. The light
pen is an optional input- device with which the student can point to selected response areas on the face
of the CRT.
The general characteristics of the CRT display are
summarized in the table. The display area on the
screen is 4.8 inches high and 8 inches wide. The control logic divides this area into 40 columns and 32
horizontal half-lines.
Each character is based on an 8 by 12 dot matrix
that is one column wide and two half-lines high. The
system logic does not allow for space between columns or half-lines; thus dot patterns can be joined
to form continuous lines, while needed space can be
written into the display code.
The display electronics are of conventional television design, with some special attention to linearity
of the vertical and horizontal sweep circuits.
The video buffer consists of a specially assembled
pack of six IBM 2316 disks, with 32 magnetic heads,
CRT Display Subsystem of IBM 1500 Instructional System
Horizontal Visible Dots
320
Vertical Visible Lines
192
Horizontal Frequency
6.5 kHz
Video Digital Frequency
2.5 x 10 6 pulses per second
Vertical Frame Rate
30 Hz
Interlace Ratio
2/1
Visible Dots
61,440
171
I
Character Matrix
8 x 12 dots
Display Size
8 x 4. 8 inches
Geometric Distortion
(Initial Settings)
Vertical Line + 0.06 inch
"Horizontal Lin-; + 0.01 inch
Linearity
(Deviation from Nominal)
Center Third: '::15%
Outside: '::25%
General characteristics of the IBM 1500 instructional display unit
in four assemblies of eight each, mounted around the
disks as shown in Figure 3. The h(fads are fixed in
position, and each one reads and writes a specific
(25-32)
_
o
32 READ/WRITE
HEADS
PRE-AMPS
(1-8)
Figure 3b- The video buffer (photograph)
of the video buffer disk pack, so that the format of
the data on the track corresponds to the scanning of
the face of the CRT, as shown in Figure 4. Since each
frame of the display consists of two interlaced fields,
half of the data track contains the odd scan field data,
while the other half contains the even scan field data.
o
--.-J.1 SECTOR = 3 SCANS
U
12
.
1 SCAN
f
=
n DOTS FOR HORIZONTAL
RETRACE
320 DOTS FOR VISIBLE SCAN
1~·"-~------...,
DIAPHRAGM
~~}6-DISK
~
PACK
1 HALF - TRACK = 32 SECTORS =
96 SCANS = I FIELD
VERTICAL BLANKING
(12 SCANS)
I-
Figure 3a- The video buffer, top and side view
track assigned to a given student display. Thirty-two
tracks on the outer edges of the 14-inch disks are
chosen to give longer and approximately equal track
lengths.
The video buffer stores and regenerates the images
displayed on the CRT. The information on the video
buffer tracks is recorded in the non-return-to-zerQ
(NRZ) mode. The digital recording is a· one-to-one
image of the dot patterns being displayed on each
instructional unit.
The disks rotate at 1800 rpm, and one revolution
of the disk corresponds to one frame on the display.
The CRT scanning is synchronized with the rotation
r
S"
-I
---------
---------
.....
I
Video Buffer
-----------------
}
I HA'HIN' - IO••• IEVEN
SECTOR =6 SCANS
=FULL CHARACTER HEIGHT
12 SCANS
---------
~~iv---Resulting Display Format
Figure 4 - Data format on video buffer and resulting display tormat
The 192 visible scan lines in a frame are addressable in 32 half-line segments of six scans each (automatically divided into three even and three odd scans,
which are stored on different halves of the data track).
A complete line of characters then represents 12
scans on the CRT, six in the odd field, and six in the
172
Fall Joint Computer Conference, 1967
even field. Each half-track, or field, consists of 96
visible scans, plus 12 scans for the vertical retrace in
the odd field, and 13 scans for the vertical retrace
in the even field - the extra scan here allows the field
interlace.
Each scan line in the video buffer consists of 392
dots (or bits). The first 72 are always blank to allow
for horizontal flyback time; the remaining 320 dots
correspond to the 40 columns of displayable data in a
horizontal sweep of the CRT.
In addition to the data tracks for each display unit,
the video buffer contains a separate timing track read
by its own fixed clock head. The timing track stores
a steady sequence of clock pulses with a biankhome
gap that serves as a reference for display sync signals
and disk read/write functions. The clock pulses increment digital counters, whose decoded output supplies signals that control display blanking and vertical
and horizontal sync. Since the display data in the video
buffer is written on the disk urider control of the same
data clock, the buffer output and CRT display are
thus properly synchronized.
The video buffer contains the necessary electronics
for head selection, writing, and sync mixing. Each
head is in a read (or display) mode except when writing, and a single write driver serves all the heads.
The display control logic circuits are time shared
for video buffer recording and character generation.
A single command to the video buffer control logic
can change any track (1) by erasing (i.e., rewriting
with blanks) the complete track, or (2) by rewriting
or erasing:
(a) a full line (12 scans),
(b) a half-line (six scans),
(c) a word or phrase (full or half-height) within a line.
Insertion of single words within a line is simplified by our choice of the NRZ mode of digital recording, with a binary magnetic state directly corresponding to black and white dots on the display. The
write circuits and control logic were designed to
insert short dot patterns on successive segments of a
track without disturbing previously recorded data.
The display unit uses a standard IBM keyboard.
The station control is an I/O device multiplexer operated under program control of the processor. At
regular intervals the adapter polls the I/O de.vices
and reads in any keyboard input. Under I/O servicing program control, the student's input message is
assembled and the character he keyed is displayed on
his CRT. In this way the computer program positions
the displayed student response and selects the character font in which it is displayed. This means that a
keyboard character set can be changed by the pro-
gram. The student keyboard itself could be changed
by an overlay.
The subsystem response time to keyboard inputs
is a function of the length of the queue to the video
buffer. The length of the queue in turn is related to
the input keying rate of all student stations. The
response time then can vary from 20 msec to a worst
case of 1.07 sec, 200 msec being typical.
Character generation
The Display Control logic basically adds two
special instructions, "translate" and "transfer," to
the repertoire of the processor. A sequence of translate and transfer instructions records a new display
frame on the video buffer, ready for immediate continuous display.
We can trace this process by looking again at Figure
2. The character generation logic operates on a string
of characters (the data stream) in core storage. It
translates the computer-coded characters into videocoded dot matrices by a table lookup techniquefinding the proper dot image in the designated dictionary, always at hand in core storage. The character generation hardware then stores the translated
video code in a reserved area in core: the line buffer.
The line buffer holds one full line (12 scans) of video
information.
When the CPU program gives a transfer command,
the line buffer contents are recorded on the selected
track and sector of the video buffer. The execution
of the transfer command automatically clears the line
buffer on readout.
The data stream may be of any length, but is always
organized in blocks of 32 sixteen-bit words. These
blocks are chained by familiar list processing techniques; that is, the last word in the block is the address
of the next block. In this case, though, programming
trouble and processing time were saved by "wiring
in" the repetitive subroutine necesshry to link the
blocks. No programming intervention is needed to
determine the new address; the logic automatically
reads in the address and continues the processing
of the data stream from the new core location.
Each dictionary occupies 768 consecutive core
locations. The number of dictionaries in the system
is a user option. Location of the dictionaries directly in core, readily accessible to the character generation logic, was a choice dictated by the need for
flexibility in changing fonts in an instruction system.
Different dictionaries can be used in one line of text.
The dictionaries can be loaded, altered, or switched
directly by program.
We could afford to use a fairly large proportion of
the relatively small available core storage for this
CRT Display Subsystem of IBM 1500 Instructional System
important function because list processing of the data
saved space. And we could afford to use list processing in the data stream of a multidevice time-sharing
system because automatic data chaining by the hardware saved time.
The line buffer is a fixed area of core, capable of
storing 240 words, It too can be directly loaded by
program.
The character shapes are specified by the user when
he constructs a dictionary. Each character or image
pattern takes six words of storage, enough to describe an 8 by 12 dot matrix. Characters are usually
constructed in 7 by 10 matrices, leaving one blank
space between characters and two blank scans be..;..
tween lines on the display. The 7 by 10 matrices can
adequately describe many kinds of characters sets,
including upper and lower case alphabets. For
graphics or very large characters, basic patterns are
usually specified in 8 by 12 matrices which can be
combined to form larger patterns.
Characters are generated in a "cycle steal" operation. The display control logic "steals" a cycle from
the core storage through the storage access channel.
This feature gives the display control random access
to all core areas needed for character generation.
It was decided to let this operation take all the
processor memory cycles it needs until the whole
data stream is completely translated. This had the
effect of reducing appreciably the programming interrupt overhead associated with the displays. Storage utilization is the same as if the processing was
overlapped, but no interrupt servicing is required because none of the processor registers are changed at
the end of the execution. File operations were given
a higher "cycle steal" priority so that system performance did not suffer.
Each code of the data stream is scanned in succession. A character code is translated and the appropriate bit pattern stored in the line buffer; a function
code will usually modify a control counter. Translation relies on one dictionary until a dictionary
change code appears in the data stream.
Translation stops at this point, and the program can
intervene to specify the next dictionary address. This
program intervention allows flexible assignment of
dictionary areas in core storage and relieves the course
author of the problem of addressing dictionaries in a
multi-user environment.
A character is translated as shown in Figure 5. After
initialization of the display control hardware, one data
stream code is read in (1). The code is combined with
the dictionary address to access the dictionary (2,3).
The character generation hardware reads in the 16bit dictionary word it finds (4), writes the eight highorder bits in the line buffer (5), and increments the
173
line buffer address counter one scan position (6).
Next it stores the eight low-order bits in the line buffer, and again advances the line buffer address
counter.
For each character, the dictionary is accessed six
times and 12 partial scan lines are stored in the line
buffer. At the end of this translation the line buffer
address counter points to the next character column.
UNE IUfF£1t
DICnONAlY
DATA STREAM
-foEI
-E2f3
E11 (SCANI1)
-EloEll
Core Storage
Figure 5 - Character translation
A transfer command causes the information in the
line buffer (5) to be read by the display control
logic (4), -serialized (7), and written in the designated
track and sector of the video buffer (8).
A transfer command may result in transfer of a full
line (Figure 6a), a half line (Figure 6b), or a few
columns within a line (Figure 6c), as in word insertion.
DispllY Format
~------------------------------------,
@
I
1I1I1I1I~lJIIIIIIllUl
fULL LINE
T....NSFE.
iI
®OMIT
HALF LINE
~
:
I
'1'1'100000:
:
I
I
I
II
I
@INSUTX
BBBBBBBBBBBBBB
@
I__ ~C
0
x 2 +y2
I
.-0
Z "-A
B
I
IL __________________________________
I
J
@
o
AtBJCIO
Z-=-tXf2Hyf2J---------------HA--B[@
WHERE
-
t oUVEISE HALF UNE FEED,
-lACKSPACE
, -tlALF UNE FEED,
--SPACE
Figure 6- Variable spacing with function codes
174
Fall Joint Computer Conference, 1967
The video output to the selected display is blanked
only for the line that is being recorded. The blanking
extends over a line and a half to blank out the transients induced by the write circuits in the read amplifier.
The blanking lasts 2.5 milliseconds and is not distracting to the person viewing the display.
Since storage in the line buffer is basically an OR
operation, characters can be superimposed on others
(as in underlining or placing accent marks over
letters) by combining the new character with a previously stored character.
The character generation logic also can handle subscripts and superscripts, as well as lines of text,
formulas, and graphic images extending over more
than one line of the display. Four function codes
give the flexibility needed for this kind of variable
spacing (see Figure 6d and 6e): half-line feed and reverse half-line feed to move a character down or up
half a line (e.g., for subscripts and superscripts);
space and backspace to move a character one column
to the left or right. With these function codes, the
data stream in the instructional system can have the
same basic format for CRT displays and typewritersthe two basic output modes; and input formatting is
simplified.
The vertical displacement codes alter the scan reference count in the line buffer address counter,
while the horizontal displacement codes alter the
column- count. The original address stored in this
counter is specified by each translate command.
Since the line buffer stores just one line (12 scans)
at a time, it is necessary, in writing an expression that
extends over many scan lines, to give one translate
and one transfer command for each line.
Figure 7 shows how characters and graphic images
constructed in this way actually appear on the face
of the CRT.
The light pen
An optional feature on the CRT display is the light
pen, a pen-shaped device that lets the student respond directly to the displayed instructional material.
Figure 7 - Sample CRT displays
The pen is a light-sensing device that transmits signals
to the light pen adapter.
To select a response from a number of alternatives
displayed on his screen, the student presses the tip
of the pen against a designated target area. The required depression of the pen tells the system that the
student is actively responding (and not just moving
the pen over the face of the display) and gates the,
detection circuits that will transfer position coordinates of the selected target to the program.
Light pen operation may be understood from the
diagram of Figure 8. Depressing the tip closes a switch
within the light pen. The photodiode can now detect
CRT Display Subsystem of IBM 1500 Instructiona, System
the phosphor light output as the electron beam
sweeps across the selected target on the face of the
C~ T, and the station is in an enter mode. In this
mode, horizontal and vertical sync signals from the
CRT deflection circuits are gated back to the light
Figure 8 - CRT light pen operation
pen control logic, and the amplifiedphotodiode pulses
are gated to the same coax line.
The horizontal and vertical sync signals from the
display control unit are used by the control logic to
determine that the light pen is in the enter mode. The
horizontal sync pulses also reset and start a counter
that counts timing pulses (from the video buffer clock
track) until a photodiode detect pulse is received. The
number of timing pulses between the horizontal sync
pulse and the photodiode pulse (see Figure 9) gives the
horizontal .position of the pen on the face of the
CRT. The vertical position is obtained by copying
the display control half-line counter at the time the
photodiode pulse is received.
IVIDEO BUFFER
CLOCK
392 PULSES
-,
11111111111111111 1111111111111 1111111111
"'------....IL.-_rL
-I
0
LIGHT PEN IN
152.-:
Display Separated Horizontal Sync Pulse
Detected Pulse From Photo Diode JES
2
[ffi ~ 8-----B
Figure 1 - MUltiprocessor
each type of module present. After a failure (or failures) there is less computation power available; consequently some of the programs will be eliminated.
This means that the periodic programs in a reconfigurable multiprocessor must be managed so that the setting of new program sequences is'a simple task. Because the Local Scheduler was initially developed
for a reconfigurable multiprocessor (shown in Figure
1), it can easily adapt to program changes. This is explained in Section I I.
In summary, the Local Scheduler presented in
Section I I provides for guaranteed scheduling of
periodic programs at their precise rates, relieves the
programmer of the necessity to link programs to each
other, provides for early call of I/O variables if necessary, and enables easy adapting to program sequence
changes. As will be shown, this is all done with only
a small overhead cost for execution of the Local
Scheduler subroutine.
II. Local scheduler
As discussed in Section I, the Local Scheduler is an
algorithm that uses a subroutine and a real-time clock
to schedule periodic programs on a processor-memory combination. (This refers to one of the processors and memories in a multiprocessor system or
to the only processor and memory in a single-processor system.) The Scheduler operates so that when the
periodic programs have been completed the Executive (Central Scheduler) is notified that the processor
and memory are free to do background programs.
Management of Periodic Operations in Real-Time Computation System
The Local Scheduler will then interrupt the background programs and also notify the Executive when
it is again time to carry out its periodic programs.
The Scheduler also relieves the programmer of the
task of specifying execution sequences or program
linkages within the operational programs themselves.
This job is not only time-consuming bolt also ineffici~nt
if not impossible when a large number of programs of
varying periodicity must be interleaved on one 'processor. As mentioned earlier, a third useful property
of the Local Scheduler is the ease of executing operation mode changes and of adapting to program changes
either because of reconfiguration after a malfunction
or because of a future system change. These points
will be clarified by the following explanation of the
Scheduler operatio'n. The discussion of the early call
of I/O variables is presented in Section III.
To best explain the Scheduler's operation, we will
present an example. Let us assume a group of programs with periodicity requirements, as in Figure 2.
Assume that the first three programs, A, B, and C,
PROG RAM
REQUIRED
PERlOO
TIME
TO RUN
(MSEC)
(MSEC)
1----+
1111111111111111111111111111
~
~
~
~
~
~
~
~
~
a
~
g B
~
Figure 2 - A group of programs with periodicity requirements
have precise periodicity requirements and the last
two programs, D and E, have only approximate
periodicity requirements. The total running time of the
whole program group is about 700 msec per second, so
that it can theoretically be accommodated on one
processor with 30 percent execution time to spare
(this time can be used to work on a queue of background programs from the Master Scheduler). One
possible interleaving of these programs for a single
processor is shown in Figure 3. The rule used to interleave the programs is: Start out doing the most
frequent program, A. Upon completion, do B, then
C, D, etc. When it is time to do A again, interrupt what
is being done and do A; then see if it is time to do B
again, if so, do B. Keep going down the line until the
interrupted program is reached and then resume it.
In trying to get back to the interrupted program,
several of the programs higher on the list may have
to be completed. Thus, several nestings will some-
203
times occur. One property of the algorithm may be
seen from Figure 3. Programs successively lower in
the list are guaranteed precise periodic execution
as long as their period is an integer multiple of the
period of the program immediately above them. Whenever this rule is broken, the program breaking the rule
and all programs below it can expect. their execution
period to be perturbed randomly, although their average execution period will remain the desired one.
Thus, the chart in Figure 2 would tell us that Programs A, B, and C will have precise periodicity, and
Programs D and E will be perturbed. The timing
chart in Figure 3 confirms this. This property of the
algorithm places no unreasonable constraint on the
system. It simply says that if precise periodicity is
desired the programs should be adjusted to meet the
integer multiple rule.
The local scheduling algorithm is simple to implement with a real-time clock in the processor and with
a subroutine. The real-time clock is set to the period of
the fastest program (A). It interrupts, saves the program status, gets reinitialized, and always transfers
program control to A. When A or any of the other
programs is finished, the finishing program always
transfers to the subroutine (the Local Scheduler). The
principal function of the Scheduler is to search through
a table that defines the Program Group (see Figure 4)
and determine which program is next. The state of
the table is shown at time ta = 271 msec in Figure 4.
"A" has just been completed, and the processor's realtime counter says 271; therefore, Program B will be
run next. The explicit operations performed by the
Scheduler Subroutine are shown in the flow chart of
Figure 5.
To determine the speed of the Local Scheduler,
the Scheduler was programmed using a simple instruction repertoire. Assuming a memory cycle time
of 2 microseconds, the Local Scheduler consumes
approximately 0.6 percent of processor time per 100
programs per second executed by a given processor.
The other portion of the Local Scheduler is the realtime clock interrupt routine. It is executed at the
rate of the highest rate periodic program (1 OO/second
in the case of Figure 2) and consumes about 80 usec
per execution or 0.8 percent of processor time per
100 executions per second of the highest rate program.
This means that the total Scheduler overhead for the
example of Figure 2 is only 2 percent.
We can now specify the means whereby the scheduling operation is updated after a system reconfiguration or a change in the computation load. A system
reconfigur(ltion, discussed in Section I, is necessary
in some advanced multi module systems (see Figure 1)
where it is generally desired to maintain a high relia-
204 Fall Joint Computer Conference, 1967
t
PROGRAM
NAME
A
I,
I,
I
I
I
I
I
I
B
I
I
I
I
I
,
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II
SPARE TIME
.,
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Figure 3 - A practical side for a periodic program group
HEAL-TIME COUNTEH: 1. 00 •••• 00271
"NEXT"
.NEXT TIME EXECUTION
"PERIOD"
OF TillS PHOGHAr.1 IS TO
PHOGRAr.1 IS TO
BE BEGUN. SIGN IlIT
BE EXECUTED)
IS ALSO USED AS
l\ONCO!\IPLETION FLAG.)
I. 00 •••• 00271
"ENTRY"
"HESUME"
(PERIOD AT WIIIC"
(!\ISEC)
(PROGRAM
(PROGRAM
STARTING
RESUMPTION
LOCATION)
LOCATION)
10
.A)
--
20
(il)
-1110
0.00 •••• 002:;"
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(C) 3170
1.00 •••• 00::-17
100
(D) 2tiG:J
1. 00 •••• 0028"
120
(E) :>111
3-115
Figure 4- Program group table of the local scheduler
bility for a certain set of computations. For example,
it would be desirable to continue the navigation calculations in an avionics or space mission after a
number of failures to be able to return home safely.
In this case the Master Scheduler would have a table
with the necessary navigation programs marked. After
any failures it would be necessary to change the program sequences so that at least the navigation programs are being carried out by an active Local Sched-
uler. * Changes in the computation load can occur
at any time in multiprocessor or single-processor
systems because of new or unforeseen needs. These
changes would also require changes or additions to
the existing Local Scheduler program sequences. It
should now be noted that both of the aforementioned
operations affect the scheduling of periodic programs
in the same manner, because in both cases it is necessary to set' up a new program mix on the processor
memory pair. The Executive Program could simply go
into the Program Group Table and remove the rows
devoted to the terminated programs and close up all
the rows. A comparison is then made between the
period of the program (or programs) to be brought
in and those on the table. The new program is then
placed between the two rows that bracket its period.
(Alternately, bypass bits on particular table rows
could be turned on and off.) The Local Scheduler is
then restarted with the highest rate program executed
first. It should be noted that this operation is very
simple and can be carried out automatically by the
*The reader may ask why a change in program sequence would be
necessary because this group of programs could have been set
up together initially; however, failures early in a mission may require some portion of the navigation programs and the automatic
terrain-following program to be continued in the remaining Local
Scheduler. As a result, these programs may be set up together
initially.
Management of Periodic Operations in Real-Time Computation System
at once. In this case one of the two following programs would be started late. The scheduler would
need to become very involved to avoid the latter
problem. The need to have the Master Scheduler
interruptable at all times would also inhibit the scheduling processor from carrying out precisely periodic
programs. Thus the Local Scheduler is not only a
very efficient scheduler for single-processor systems,
but also for multiprocessor systems.
ANY PROGRAM
IS COMPLETED
ADD (pERIOD) TO (NEXT)
FOR THAT PROGRAM.
SET TO "I" THE SIGN
BIT OF (NEXT) FOR
THAT PROGRAM
INCREMENT NOW INDEX
TO GET TO NEXT PROGRAM
IN THE TABLE. TEST INDEX TO
SEE IF NO MORE PROGRAMS
Y
205
NO MORE
PROGRAMS
Figure 5 - Flow chart of the local scheduler
System Executive. This should be contrasted with
the problems of changing linkages in a scheduling
system that uses control words to link periodic programs to each other.
Having presented the Local Scheduler, it is worthwhile to briefly compare it to a Master Scheduler.
Of course, a Master Scheduler is only distinct from the
Local Scheduler in a multiprocessor system. In this
case this large scheduler would be executed by one
processor and would schedule the periodic programs
for all the processors. To avoid maki~g the system
have single special modules (a single failure point),
each processor module would have a real-time clock
and be capable of executing the Master Scheduler; as
a result the Master Scheduler saves no hardware.
The Local Scheduler, as pointed out, is executed
whenever a real-time clock interrupt occurs or when
ever a program is completed. Therefore, the Master
Scheduler processor would save the other processors
the time for each to execute the real-time clock routine, but each processor would sit idle while the Master Scheduler performs its program completion and
program initialization functions. Because these latter
functions take the majority of the time, the Master
Scheduler would increase the scheduling overhead.
An even worse problem could easily arise with the
Master Scheduler if two programs were to complete
III. Early call of I/O variables
As discussed in Section I, the Local Scheduler can
be used to manage I/O traffic for the periodic programs efficiently. It carries out this function by
calling I/O variables for a periodic program just before it is to go into execution. In this way three important goals are achieved:
1. Separation of Computation from Input/Output
To preserve the integrity of multi precision numbers and of parameter sets that are internally related, it is essential to avoid computation on data in
memory during the time interval in which that data
is input or output.
2. Control of Transport Lags Through the Computer System
Both uncertainties as to transport lags (minimizable by separating computations from input/
output) and excessive transport lags (minimizable by establishing the proper time sequence
between input, computation, and output) must be
controlled.
3. Placing Input/Output Delays Off-Line from
Computation
Where input/output must take place in connection with format conversion and/or data communication, it is frequently prohibitively wasteful of
computer time for the computer program to request input parameters and then halt until they
arrive. Thus some sort of off-line procedure resulting in the data being available to the program
when the program needs it must be used.
One possible implementation of this task is described hereinafter. This implementation may be
referred to as "NESTED."
To have the Local Scheduler also carry out the early
call of I/O variables, two special input timing registers,
the High Rate Register and Low Rate Register, can be
added to the processor. The system then operates in
the same manner except for the inclusion of one new
task for the Executive and another for the Scheduler.
The task for the Executive involves initially setting each processor's High Rate Register to a time
delay appropriate to the sensors associated with the
206
Fall Joint Computer Conference, 1967
highest execution-rate program of a particular program group, e.g., 500 usec. Alternatively, this register could be eliminated by the choice of an appropriate, fixed time delay. When' the real-time counter in
a processor has decremented to the value contained
in its High Rate Register, a high rate request is automatically sent to the proper controller. The controller accepts the request (as soon as possible), goes
to a preset memory position, and picks up and executes the high rate I/O program. In this way, the processor is able to immediately begin work on the high
rate program when the system is interrupted for this
purpose.
The new task for the Scheduler, to enable it to
help call I/O variables, involves updating the Low
Rate Register whenever a program is completed. The
Scheduler still does its normal job of choosing the
next program, but it is now also required to compare
the next execution time of the program following the
next program to be run and the second from top program in the Scheduler table (Program B in Figure 4).
Whichever of these two programs is to be executed
first has its next execution time, less some delay
(say 500 usec), placed in the Low Rate Register. The
Scheduler then sets up the proper memory word with
the location of the I/O program for the chosen program's sensors. This is accomplished by loading an
established memory position with the program starting location from the Entry column of the Local
Scheduler Table, Figure 4. The controller, when requested by the low rate interrupt, goes to the established memory position and obtains and executes
the I/O program. After the aforementioned extra task,
the Local Scheduler as before sends the processor
to the next program to be run. The explicit operation
of this portion of the Scheduler is shown in the flow
chart of Figure 6. This figure is a continuation of
Figure 5.
The preceding I/O call routine was also programmed to ·determine its effect on the execution time of
the Scheduler. Again, assuming a 2-microsecond
memory cycle, the Local Scheduler was increased,
from approximately 0.6 percent of processor time per
100 programs pe~ second to approximately 1 percent
of processor time. With the foregoing overhead, plus
the 0.8 percent per 100 executions per second for
the real-time clock routine, the total scheduler and I/O
variable call overhead can be calculated for any system. For example, in an Avionics system under study,
one processor carries out the majority of the periodic
programs. This amounted to about 700 programs executions per second of which the highest rate program
accounted for 200 executions per second. Therefore,
this heavily loaded processor would only spend less
than 9 percent of the time in overhead.
Y
CONTINUA TION FROM FIGURE 5
SET SIGN OF (NEXT)
POSITIVE AND SET UP
(ENTRY + 1) FOR STARTING THIS PROGRAM
COMPARE STARTING TIME OF
NEXT PROGRAM IN TABLE
WITH THE SECOND PROGRAM
IN THE TABLE
Y
SET UP LOW RA TE REGISTER
WITH I/O CALL TIME OF
SECOND PROGRAM AND SET
UP MEMORY WITH THE I/O
PROGRAM ADDRESS
SET UP LOW RATE REGISTER
\vITII I/O CALL TIME OF
NEXT PROGRAM AND SET
UP MEMORY WITII TilE
I/O PROGRAM ADDRESS
GO TO (ENTRY + 1) TIIEREBY
ST ARTING THE PROPER
PROGRAM
, Figure 6- Flow chart for the 110 call routine
An alternate and somewhat simpler I/O traffic management scheme can be used. This scheme, which we
shall refer to as "QUANTIZED," does not require
the High Rate and Low Rate Registers of the NESTEb scheme, and it leads to a simpler Local Scheduler.
One difference between QUANTIZED and NESTED is that ·iteration rates of computations in QUANTIZED must be submultiples of the next-higher
iteration rates. Thus, in Figure 2, Program D would
have to be scheduled with a period of either 60 or
120 milliseconds, rather than 100 milliseconds.
A second difference between the two schemes relates to the granularity of starting times for I/O actions. In NESTED, computations can start at irregular times. The sensor inputs to these computations
can be initiated (by the High and Low Rate Registers)
at more or le.ss arbitrary times prior to the scheduled
computation starting times. Because the computation
starting times need not be correlated with each other,
neither will be the various I/O starting times. This
can result in a controller executing I/O sequences
nested within other I/O sequences, and can also result
Management of Periodic Operations in Real-Time Computation System
in uncertainty as to the starting time of some I/O sequences. Such uncertainties of I/O execution diminish
the efficiency and speed of I/O execution.
In QUANTIZED, I/O sequences can be started
only upon a processor real-time counter interrupt.
Furthermore, because the iteration rate sUbmultiple
method for computations leads to an easily predictable
computation sequence (especially if binary submultiples are used), a corresponding predictability is
associated with I/O sequence execution times. This is
related to the elimination of nesting of I/O sequences
in other sequences. The most practical technique for
QUANTIZED has been found to be the following:
1. Group together I/O actions for computations of
the same iteration rate into one long I/O sequence, or into one long Input sequence and
another long Output sequence.
2. Manually calculate the maximum possible execution times of these sequences. Have the
Processor's real-time counter interrupt and
begin the sequences sufficiently in advance of
the computation starting times that nonsimultaneity of input/output and computation is
preserved. Input/Output completion timekeeping can be accomplished by a table in the
Local Scheduler, by an interrupt from the I/O
Controller, or both.
A possible interleaving of computations and input/
output actions for the QUANTIZED scheme is
shown in 'Figure 7. For the mix of iteration rates
shown, the Processor interr.upt rate (by the real-time
counter) is a little more than twice the highest iteration rate of "A", the highest-rate computation
207
interrupts are achieve~.) Several implications. of Figure 7 are worth noting:
a. Input/Output and computation never occur
simultaneously for computations of any given
iteration rate. However, input/output for one
iteration rate may occur simultaneously with
computations of a different iteration rate.
b. The transport lag through the multiprocessor system (Controller input to Processor computation
to Controller output) for computations of anyone
iteration rate is equal to the inverse of that
iteration rate. This is illustrated in the detailed
view shown in Figure 8. However, for a system
of interlocking computations of different iteration rates, some care must be exercised to avoid
transport lag uncertainties and to provide transport lags characteristic of the highest iteration
rates rather than of the lowest iteration rates.
COMPUTATION
INPUT/OUTPUT
ACTUATORS
SENSORS
Figure 8 - Detail view of the schedule of Figure 7
• •d•dl•d•d\•d• d!•d• 01• d
PROGRAM
COMPUTATION
A
INPUT /OUTPUT
~
D:
"
,,
I
I
I
COMPUTATION
INPUT /OUTPUT
~ ~
d: d
,
,
,
,
•
d\
'
I
,,
I
I
C
INPUT/OUTPUT
d
+
~
,;
"
-. -.
I
I
,
"
I
I
I
B
I
"
II
D []:
d
-
°l
,
I
,
I
~
,
~
dl
--
0
:.-
d
ETC
+
ETC
Figure 7 - A practical schedule for the QU ANTIZED scheme
(By introducing still more uniformity into the time
allocations for input/output sequences, a simpler
pattern, more programming flexibility, and still fewer
Our experience has shown the QUANTIZED
scheme to be of greater interest than the NESTED
scheme. The QUANTIZED scheme has the further
advantage of being achievable with a conventional
Processor because the High Rate and Low Rate
Registers are not required.
CONCLUSIONS
This paper has presented a periodic program scheduler and two schemes for controlling I/O traffic in
real-time computation systems. These schemes have
been shown to be very efficient in terms of use of
processor time while providing the following important features:
1. Guaranteed precise scheduling of periodic
programs
2. No requirement for individual programmers
to set up linkages to other programs
208
Fall Joint Computer Conference, 1967
3. Call of I/O variables just prior to program execution to limit processor waits, to provide fresh
sensor data, and to prevent simultaneous computation and input/output.
4. Easy adaptation to changes in the periodic
program sequences because of either the need
for reconfiguration or changes in computation
load
The real advantages of the complete scheduler are
realized when a heavy load of precisely periodic programs must be processed. This situation is known
by the authors to occur in the newer central avionics
and future space computation systems; however, it
may well occur in a number of other real-time control
systems. In these heavily loaded systems, not only is
efficiency important but also a large number of program changes generally occur in development and
in the field. The Local Scheduler is easily able to
adapt to these changes without loss of scheduling
efficiency. As a tesult, the complete scheduler appears to have broad potential for application to realtime control systems.
A generalized supervisor for a time-shared operating system
by THOMAS C. WOOD
Computer Sciences Corporation
Richland, Washington
INTRODUCTION
An operating system may be considered an environment defined by a set of software processors operating
in conjunction with the facilities of one or more central processors and associated devices. Its function
is to allow its users to effectively command these
facilities. A time-shared multiple access operating
system provides apparent simultaneous availability
of its facilities to a large number of users. The Supervisor of such an operating system must provide
effective control of all of the facilities available to
the system.
The following paper is a formalized description of
the major components of the Supervisor of a timeshared operating system.
While no originality in the concepts presented is
claimed, it is felt that a subject in which so much
current interest is shown will benefit by such a formalization.
I nterrupt processor
The Interrupt Processor (Figure 1) may be said to
be the heart of the Supervisor. It consists of two
parts, the Hardware Interface and the Interrupt
Activation Routine.
The Hardware Interface recognizes and responds to
all physical interruptions, or traps, that the hardware is capable of generating. These traps fall into the
following general categories:
I/O Traps caused by the completion, successful
or otherwise, of an input/output operation. Such
traps are normally generated, e.g., when a channel or device signals that it has completed a
requested operation and it is free for new requests. Additionally, certain input/output devices
generate attention traps which indicate the readiness of the device to receive commands.
Timer Traps caused by the overflow of a hardware clock. The clock is most often used to force
periodic entrances to the Supervisor in order to
prevent any program from completely dominating
the facilities of the operating system.
Program Faults caused by the faulty execution of
certain machine order codes. Arithmefic operations leading to register overflow or underflow
are typical Program Faults. Another class of
Program Faults is generated by the attempted
execution of privileged or otherwise illegal instructions. The Supervisor is protected from
deliberate . or. inadvertent interference by its
clients by reserving to itself certain privileged
instructions. These instructions define the storage
boundaries and general operating conditions for
non-Supervisor programs. An attempt either to
execute these instructions or to violate the conditions results in a Program Fault. Further, in
order to maintain a strictly controlled operating
environment, the Supervisor has sole control over
Supervisor
The function of the Supervisor is to provide an
effective logical interface between the hardware
utilized by the operating syste~ and those modules
requiring these fa.cilities. The Supervisor directs the
flow between various components of the system and
resolves conflicts in the priority of usage and availability of all facilities. The Supervisor retains complete and rigid control over all input/output operations,
scheduling the input/output activities to make the
most efficient use of all devices, and administers all
interrupts resulting from hardware activity.
The major modules of the Supervisor are:
The Interrupt Processor
The Input/Output Processor
The Timer Administrator
The Program Storage Administrator
The Facilities Administrator
The Program Administrator
209
210
Fall Joint Computer Conference, 1967
all input/output operations. Any attempt by nonSupervisor programs to initiate input/output also
results in a Program Fault.
H ardware Faults caused" by hardware malfunctions. Under this "heading are memory parity
errors, channel and device failures and similar
difficulties which may be directly detected by the
hardware.
Request for Supervisor Service caused by the
execution in a program of an instruction known
as the Supervisor Call. Since the Supervisor
allows a program to have access to none of the
facilities of the hardware except the" arithmetic
and control units, provision must be made for
programs to communicate their desires for a
wider range of functions. This mechanism is the
Supervisor Call. Typical requests for service are
those to read and write logical records on a data
set.
While the Hardware Interface responds to physical
occurrences, the Interrupt Activation Routine concerns itself only with the logical consequences of
these occurrences. Two queues, the Interrupt Queue,
and the Priority Queue relate physical traps to logical interrupts.
The Interrupt Queue consists of on"e element for
each logical entity for which it is desired to define
an "interrupt. Certain entries correspond to physical
devices, e.g., a card reader; others correspond to
classes of devices, e.g., tapes mUltiplexed on a channel; and others to conditions, e.g., Timer overflow
or Request for Supervisor Service.
Each element is composed of three p.arts:
Device Identification indicating the logical class
causing the interrupt.
Interrupt Status which specifies the nature of
the interrupt.
I nterrupt Director which indicates the routine,
called an Interrupt Routine, responsible for
servicing the logical interrupt.
By changing the Interrupt Director, the response to
a logical interrupt may be dynamically altered by
components of the Supervisor.
Priority among interrupts is established with the
Priority Queue. The Interrupt Activation Routine
scans the Priority Queue in a fixed sequence. The
Priority Queue indicates the order in which logical
interrupts are to be processed. By altering the priority
assignments, the Supervisor may be tuned to process
certain classes of interrupts more rapidly than others.
A logical interrupt is serviced by executing a series
of routines beginning with that one indicated by the
Interrupt Director. The interrupt is in progress, or
active, until control is returned to the Interrupt
Activation Routine. While only one Interrupt can be
active at any time, physical traps may easily be
generated at a rate faster than the Supervisor can dispose of them. These traps are mapped into their
corresponding logical interrupts and stacked in the
Interrupt Queue where they await servicing when· the
current interrupt has been completed.
PHYSICAL TRAP
',r'- - - - - - - - - -
I~~~~~
/,r'- - - - - - - - - - -
~~~~::~:~12
: 1 42 12~
I ~~II
TIME:~~::::::
ROUTINE
INTERRUPT
110
I~b~~~~
t
Jf
_
f--ft--+--j'l
L---+_----1_I+
___f-II_ _ _ _ _ _ _ __
~
r-
/1------'.....1 . . - 0 1 - - - - - - _ _ TIME---+
I TIMER TRAP
l PLACE ENTRY IN INTERRUPT QUEUE
I BEGIN LOGICAL INTERRUPT
4 IIv INTERRUPT
Figure I-Interrupt processor typical interrupt sequence
Input/Output processor
An Input/Output Processor is a set of routines
which provides the operating system with the ability
to communicate with classes of hardware devices.
The Processors schedule requests for input/output
operations, initiate the physical data transfer, validate
the correct transmission of data, and, when necessary,
re-try operations found to be in error. The Processor
is also responsible for notifying the ultimate requestor
of the status of the operation upon its completion.
These activities may be grouped under the heading
of:
Scheduling
Initiation
Physical Post Processing
Logical Post Processing
An Input/Output Processor generally consists of
the following:
Request Queue
Schedular
Activation Routine
Input/Output Interrupt Routine
Associated Schedular Routine
Within a given time period, requests for input/output activities may be generated faster than the operations can be initiated. Requests for pending operations
are placed in Request Queues by routines known as
Schedulars, where they await servicing by an Activation Routine.
An entry in a Request Queue describes completely
the nature of the operation to be performed. This
description contains the specifications of the device
Generalized Supervisor for Time-Shared Operating System
SOtEDUI..IN&......
$
«
Il
INITIATION
PHY~~u~
;,
~~~
;/
:=~
ROUTINE~
I
Z
•
Z
)
HARDWARE
INTERFACE
ACTIVATE
INTEIRUI'T
110 INTERRUPT
ROUTINE
ASSOCIATED
SCHEDULAR
)
,,
,,
,,
1
ROUTINE -TIIoIE--+
L
La
L J
I PLACE REQUEST IN QUEUE
2 IDENTIFY DEVICE AVAILAILE
J START 110 OPERATION
.110 TRAP SIGNALS OPERATION
COMPLETE
I TRANSMISSION VALIDATED
Figure 2 - Input/output processor typical I/O sequence
upon which the operation is to take place, the operation itself, and the identification of the routine to
notify when the operation is logically complete.
The schedular is responsible for entering a request
in the proper sequence into a Request Queue. Once
the entry has been made in the queue, an attempt is
made to start any pending operations for the class of
device for which the requests are queued.
The Activation Routine scans the Request Queue,
identifies devices available to service the request,
and initiates all requests which may be started. When
a request is started, an Interrupt Director for the
logical interrupt expected is entered into the Interrupt Queue. This Interrupt Director defines the logical
interrupt associated with the operation.
Upon completion of a request, an I/O trap is generated and transformed into a logical interrupt by the
Hardware Interface. The operation must now be
checked for correctness and the ultimate requestor,
the routine which scheduled the operation, must be
informed of its completion.
The Input/Output Interrupt routine specified by the
Interrupt Director is responsible for validating the
transmission and requesting retransmission as necessary. Once the physical operation has been accepted,
the routine named in the Request Queue, known as
the Associated Schedular Routine, is notified. This
routine is associated with the request for operation;
invoking it signals that the operation scheduled is
logically, as well as physically, complete. As a part
of the post processing path, pending requests are examined in the Request Queue and an attempt is made
to start them. In this way the physical facilities associated with the class of request are driven at as high a
rate as possible.
Timer administrator
As can be seen in Figure 3 by the interaction between Schedular, its Activation Routine, Interrupt
211
Routine and Associated Schedular Routine, the Supervisor is basically asynchronous by nature. That is,
there generally is little relationship between the order
in which operations are started and that in which they
terminate. Further, an operation does not have to
terminate before other operations may be initiated.
Moreover, there are occasions when it is not possible to initiate an operation, but when it is desirable
to be about other tasks rather than simply to wait.
For this reason, the Supervisor provides itself with
the ability to return to a given activity after a specified time period expires.
The Timer Administrator consists of a set of routines collectively responsible for the maintenance of
physical and logical timers available for this purpose.
Logical Timers are created by the Timer Schedular
and consist of entries in the Timer Queue. Each entry
contains a time field and the identification of a routine,
called a Timer Routine, to invoke when the time expires.
11
li
I:
5
SCHEDULAR
Tlt.CER SCHEDULAR=n
HARDWARE INTERFACE
INTERRUPT ACTIVATION
INTE:~~~
ROUTINE
TIt.CER ROUTINE
/
/
/'
,
/~
-Tlt.CE-+
(
I OPERATION CANNOT
IE SCHEDULED
2 TIt.CER CREATED
J Tlt.CER TRAP
(
1..
1
I
• Tlt.CER EXPIRES
$ OPERATION
RE·SCHEDULED
• TIt.CER DECREt.CENTED
Figure 3 - Timer administrator typical time delay sequence
Periodically, as part of the processing of a logical
timer interrupt, the timers in the queue are decremented, and upon detection of an expired Timer,
control is given to a Timer Routine.
Programs
The Supervisor exists for one purpose only; to
provide services to entities known as programs. A
program performs some logically complete function
and may not invoke or directly communicate with
other programs. Communication with other programs
is achieved through data sets which may be read or
written by the programs. Additionally, a program is
characterized by the existence of a Program Definition Area, available to the Supervisor only, which
describes total environment for each program.
The primary direct service that the Supervisor provides for programs is that of Input/Output. To protect the integrity of itself, and of other programs which
may be concurrently occupying Execution Storage,
the Supervisor must exercise rigid control over the
212
Fall Joint Computer Conference, 1967
total environment. Not only are programs isolated
from one another by inviolable storage protect measures, but thenature and scope of Input/Output operations are limited to prevent one program from dominating the facilities of the operating system to the
detriment of others.
Requests for operations forbidden to programs
are made through the mechanism of the Supervisor
Call, generally an instruction which generates a physical trap. Given the specification of the operation desired in the program, this specification is transformed
into the corresponding action in the Supervisor as
shown in Figure 4.
PROGRAM
INTERRUPT
PROCESSOR
SERVICE
INTERRUPT
ROUTINE
~1'
,
I
ecution and Extended Storage assignments for the
program. Programs not in a position to utilize Execution Storage are placed on Extended Storage, and
the free Execution Storage pages are assigned to
other programs.
In order to retain an acceptable responsiveness
to programs attached to devices such as remote
inquiry keyboards, the Timer Administrator periodically interrupts the execution of programs active in
Execution Storage. These programs are forced onto
Extended Storage while other programs are activated.
This swapping process, as shown in Figure 5, insures
that each program will have periodic access to the
facilities of the central processor.
PROGRAM~:
INTERRUPT : : E : R
PROGRAM STORAGE
SCHEDULAR
Ir:---.J~"'t-~J,-----2
1
ADMINISTRATOR
ACTIVATION
ROUTINE
,
1/0 INTERRUPT
ROUTINE
I
ASSOCIATED
SCHEDULAR
ROUTINE - - T I M E - - +
I DETERMINE TYPE OF REQUEST
lsi
,
7
I
:r~___
'
1_____
2 _1....
--TIIo4E,---+
I TIME QUANTLIM EXPIRES
Z PROGRAM WRITTEN TO EXTENDED STORAGE
1 PROGRAM READ FROM EXTENDED STORAGE
4 1/0 TRAP
2 SCHEDULE 1/0 REQUEST
5 OPERATION COMPLETE
I START 110 REQUEST
6 PROGRAM REGAINS CONTROL
Figure 5 - Program storage administrator typical
swapping storage
Figure 4 - Programs typical supervisor call
Program storage administrator
F acUities administrator
In the course of the execution of a program, the
program occupies a portion of a larger space called
the Program Storage. Program Storage contains the
Program Definition Areas, Instruction Areas, Data
Areas, and Buffers for all programs actively engaging
the attention of the operating system.
That section of the Program Storage in which a program resides while making use of the arithmetic and
control sections of the prpcessor is known as Execution Storage. The remainder, that part which provides
passive storage for the program, is known as Extended
Storage.
At any given time, the total requirements for the
Execution Storage may be expected far to exceed its
availability. The Program Storage Administrator is
responsible for the orderly transition of a program
from Extended Storage to Execution Storage and back
again.
The relationship between Extended and Execution
Storage is summarized in the Execution Storage A vailability Table, which relates a section, or page, of
Execution Storage to that program requiring it. In
the Program Definition Area of each program the Program Page Table shows for any given instant the Ex-
Before a program can be placed in execution, all
of its requirements for facilities of the operating system must be satisfied. These facilities include catalogued data sets, such as would normally be found
on bulk storage; temporary or permanent tape files;
and printers or card readers. The Facilities Administrator attends to the task of satisfying requirements
for given facilities. The sum of these requirements
is contained in the Requirements List portion of the
Program Definition Area. Once all requirements are
assigned, the program may be placed in the program
state.
Program administrator
The operating environment exists in one of three
mutually exclusive states:
The Wait State
The Supervisor State
The Program State
The Wait State is the ground state of the operating
system. It is entered whenever there is no load on
the system. From this state the Supervisor State is
entered whenever it is discovered that an activity has
been completed or must be initiated.
Generalized Supervisor for Time-Shared Operating System
It is in the Supervisor State that all interrupts are
serviced, Input/Output is initiated, and response made
to Supervisor Calls.
When all pending operations in the Supervisor State
have been initiated, and no further processing can take
place, either the Wait State is re-entered, if no program can be placed in execution, or the Program State
is entered. The operating system is in the Program
State as long as a program has effective control over
the central processor. When this control is relinquished, either voluntarily as upon execution of a
Supervisor Call, or involuntarily because of the expiration of a time quantum associated with the program or other physical trap, the system reverts to the
Supervisor State. This is shown graphically in Figure
6.
Figure 6 - Program administrator system state diagram
Separate from the states of the operating system
are the states in which a program may find itself
throughout the time allotted to it for execution. These
states are governed by the attachment of the Program Definition Area to one of the following queues
called, collectively, Program Queues:
Program Definition Queue
Program Queue
Execution Queue
Service Queue
Service Pending Queue
Service Delay Queue
If the Interrupt Processor is the heart of the Supervisor, the Program Administrator is the heart of the
operating system, for it governs the flow between
these states and controls the priorities among programs.
The Program Definition Area of a program contains
descriptions of the environment of the program. The
area is divided into:
The Program Descriptor which defines the number of files attached to the program, the location
and extent of the program, the current location
counter and accounting information.
213
The Machine Environment which contains the.
volitile machine registers and indicators. This
environment is saved by the Program Administrator when the program relinquishes control
of the central processor, and is restored when the
program is in position to regain control.
The Requirements List which defines all data sets
and physical facilities assigned to the program.
The File Control Blocks for all files attached to
the program. Each file control block specifies
the properties of the file and contains information
relating to the current file positioning.
The Program Page Table which relates the location of pages of the program to both Execution
and Extended Storage.
The Program Symbol Table which relates symbolic labels to locations within the program.
While the Program Definition Area is being constructed, and the appropriate facilities assigned to a
program, the program is in the Program Definition
State. (See Figure 7.) When all facilities are assigned,
with the exception of Execution Storage, the program
moves to the Program State. In this state the program
is in contention for available Execution Storage. Once
sufficient Execution Storage is made available for a
program, it enters the Execution State. Programs in
this state are either using the central processor or are
immediately able to do so.
Figure 7 - Program administrator program state diagram
PROGIIAr.I--~--~---~------n
~~
SUPERVISOR
EE
WAIT----------------MS
PROGRAM A - - - - - ._ _r'-I- - - - - - -_ _- -
---..---tl-+---~-----rJ~I- + - -
P~7Jg~6~-.....L-t-.....,r-P't'"p-t1~11+-lo___4r_1- - + - -
PROGRAM.
I/OPROCESSOR~J2+--~:- - - - U
•• - -~._
-II. . .'--_---"'I. .____I . . ____I ......~--
PROGRAM _ _
ADMINISTRATOR
J
EXECUTION _ _- - - - -_ _ _ _- - - - - :
SERVICE
~
0 A
SERVICE PENDING
P R O G R A M - - - - - -_ _ _ _ _ _ _ _ _ _
--TlME~
~~
~
S
I REOUEST FOR SUPERVISOR SERVICE III
2 1/0 INITIATED
J 1/0 OPERATION COMPLETE
Figure 8 - Program administrator typical program sequence
214 Fall Joint Computer Conference, 1967
When a program makes a request for a supervisor
service, it enters the Service State where it remains
until the service requested can be initiated. If the service can be initiated, the Service Pending State is
entered until the service is completed. If the service
cannot be started, the Service Delayed State is entered. Periodically, the program is placed in the
Service State and the request re-initiated. Upon completion of the requested supervisor service, the program enters the' Program State where it is again in a
position to regain control of the central processor.
In order to minimize switching between the Supervisor and Program States of the operating system, all
activities in the Supervisor are brought- as close to
completion as possible before' attempting to enter the
program state. If no further Supervisor activity can
be attended to, a suitable program is chosen, the machine environment for this program is established, a
time slice assigned to the program so that the Supervisor can ultimately regain control through a timer interrupt, and control is passed to the location counter
indicated in the Program Descriptor.
SUMMARY
As systems become increasingly complex, it is increasingly important to be able to isolate the logical
functions that comprise the system. The preceding
paper is an attempt to specify the major functions
required for the implementation of a time-shared
operating system. By defining a reasonably formal
structure for each function, independent of a specific
implementation, a generalized machine-independent
design emerges. Prototype versions utilizing this
design have been implemented for two different
manufacturers' machines.
A real time executive system for manned spaceflight
by J. L. JOHNSTONE
International Business Machines Corporation
Houston, Texas
INTRODUCTION
The Real Time Executive Control System discussed
in this paper was the foundation for the applications
programs developed in support of NASA's Gemini
and early Apollo missions. Services provided by
the Executive included dynamic storage management
and allocation, two-level priority multiprogramming,
real time data control and routing, real time error
recovery, dynamic statistical monitoring, debugging
facilities, and the program linkages and services that
facilitated modular and independent applications
system design. 'While a selection of these services
may be available in other systems, the Executive design differs from other real time systems by these
characteristics:
• Modularity - The Executive design permitted
the addition of new services and facilities based
on equipment changes or applications requirements with no impact on the previously provided
services and facilities.
• Simplicity - Only a minimal instruction in Executive services was necessary before applications programmers could construct programs that
operated in a complicated real time environment.
• Versatility - Executive could be used in the
simplest simulated real time environment for the
debugging of one applic~tions program or the
support of the most demanding real time missions.
• Generality - Executive was non-applications
oriented; i.e., it operated equally well in a real
time Gemini mission, an astronaut training session, or in a non-real time environment using
simulated input from tapes.
• Invulnerable - The Executive was virtually unstoppable in real time; a feature vital for manned
spaceflight.
The executive environment
TheRTCC
A brief introduction to the Real Time Computer
Complex (RTCC) is necessary before proceeding to
any discussion of the Executive Control System.
The RTCC is a functional part of the Mission Control
Center at NASA's Manned Spacecraft Center in
Houston, The RTCC's missions during spaceflights
or training sessions are to:
• take spacecraft tracking and status data being
received from NASA's global communication
network and process it for display to flight controllers stationed in the Mission Control Room
and the computer complex;
• compute and then forward antennae-aiming
directions to tracking and communications networks all over the world so they can begin to
track the manned spacecraft as it approaches;
• send calculated navigation and other information to the computer aboard the spacecraft;
and
• simulate the data that network sites and space
vehicles would generate during an actual mission
so ,that personnel can be trained and equipment
can be checked and readied.
To perform these missions, each of five IBM
7094-II's was assigned a different role, and the RTCC
was engineered so that these roles could be exchanged at any moment. This unified set of computers
allowed NASA to run either two practice missions at
the same time, or a practice mission and an actual
mission at the same time. Figure 1 gives a dramatic
demonstration of the five systems at work in the latter
configuration. In the mission configuration,' network
data flows into the RTCC from one of the communications processors at the Manned Spacecraft Center
and is sent to the Mission Operational Computer
and the Dynamic Standby Computer by a switching
device called the System Selector Unit. In the simulation and training exercise, a nearby Gemini spacecraft trainer is in a closed loop system with one of the .
two identical Mission Operational Control Rool1}s
(MOCR). The other MOCR is being used for the
mission. One simulation computer contains a system
which is generating simulated network data; the other
computer is used as an operational computer. The
215
216 Fall Joint Computer Conference, 1967
MISSION
SIMULATION
Trainer
7094-11
Subsystem
A
7094-11
Subsystem
D
7094-11
Subsystem
B
7094-11
Subsystem
E
Communications
.---... Processor
DISPLAY
SYSTEM
(MOCR-R CC)
C
P
Communications
DISPLAY SYSTEM
(MOCR-RTCC)
IJ
C.
1
I~ I I~I
~
MOCR
Control
Room
(MOCR)
Ground
Radar
Spacecra't
~
Communication
Figure 1- RTCC data flow-simultaneous simulation and mission
fifth computer is a standby computer for both exercises; however, it is not idle but is processing a singlecomputer debugging exercise for checkout of a future
mission or simulation system.
Although all three of the functions being performed
in the RTCC are different, a single Executive is performing the control system functions for each.
The computer system
Each of the IBM 7094-11 computer systems (Figure 2) in the RTCC has 65.K primary memory, directly
addressable through automatic relocation hardware.
Each system has 524K words' of Large Capacity
Storage (IBM 2361) which is used as extremely highspeed buffer storage for programs and data. Programs
are buffered between main memory and the Large
Core Storage (sometimes termed "core file" or
"COFIL") and placed in main memory wherever
space is dynamically allocatable. A protect feature
permits areas of storage to be protected from illegal
storing operations. Tape drives are attached to standard data channels A and B. In addition, a card reader
and printer are attached to channel A (not shown).
The Direct Data Connection (IBM 7286) on channel
C provides a rapid demand-response interface to the
digital display (D/TV) television system. Access to
large storage areas at a high data rate is provided by
the use of the Large Capacity Storage on channel D.
Real time acceptance and transmission of large
amounts of data and control information are accomplished through the use of the IBM 7281-11 Data
Communications Channel (DCC) on channel F. At )
the RTCC, the DCC has 13 subchannels designated
either input or output. Both the Direct Data Connection and Data communications Channel interface
with the equipment and data networks serviced by
the RTCC. via the System Selector Unit (Figures 1
and 2).
65K Word
A
Main Memory
I
N
c
T
E
R
F
A
C
E
2361
Lg. Capacity
Storage
524K Words
Figure 2- RTCC 7094-11 computer system
A Real Time Executive System for Manned Spaceflight
As was shown in Figure 1, the SSU permits the individual computer subsystems to be configured either
singly, or in combination, to perform any of the
various mission, simulation, program testing, or
equipment testing functions of the RTCC. It is designed to process the inputs and outputs of up to six
RTCC computers. The System Selector Unit makes
switching connections between computers and their
inputs and outputs and routes data accordingly. The
SSU's routing assignments are made by plugboards.
The preceding paragraphs have discussed the Executive environment-the RTCC and its IBM 7094-11
computer in which the Executive performed the real
time computer control functions from Gemini IV to
XII and Apollo 201, 202, and 203.
The real time system design
What is executive?
We have placed Executive in an environment
geared to real time operation. But, to enter into any
discussion of real time, one must first define his version of real time; for there are probably as many
definitions of real time as there are real time systems.
To understand the Executive real time system design,
one must realize that the response time for the NASA
mission application must be an increment sufficiently
small to guarantee positive control of a manned spaceflight. At the RTCC, the usual time frame (or increment) in which data is received and presented to
NASA Flight Controllers is considerably less than
a second. Appreciating the response time required for
the real time Executive, we can now turn to a general
description of Executive.
General description
Executive is a collective term for those routines
which perform the support functions for the applications programs at the RTCC. Executive has two general responsibilities in this capacity: (1) to serve as an
interface between applications programs and the
RTCC input/output devices and communications
lines, (2) to control the execution of and communications between the application programs. Executive is
a non-applications oriented system; i.e., it supports
equally w~1I all the RTCC systems: the Gemini or
Apollo Mission system, the Simulation Checkout and
Training System (SCATS), the Dynamic Network
Data Generation system (DNDG), the Ground Support Simulation Computer system (GSSC)~ or the
Operational Readiness and Confidence Testing system (ORACT). The application programmers who
design programs for these various Executive sup-
217
ported systems code routines in assembly language
or FORTRAN to perform mathematical computations, interpret input data, or form output data. The
programmers are relatively uninformed as to how
Executive works .internally in performing its responsibilities. All that is required of the programmer to use
Executive is a basic knowledge of the communication
mechanisms with Executive and what he is to expect
in the way of input from Executive.
System modularity
The majority of the application system's situations
call for processing logic programs which can be segmented into controlling logic and a series of controlled processing elements. The former programs are
designated supervisors, and the latter are termed
processors (see Figure 3). Supervisors are multielement programs which control processors and treat
XTRANS OF
SUPERVISOR
XTRANS OF
PROCESSOR
SUPERVISOR
PROGRAM
PROCESSOR
PROGRAM
(ALWAYS THE
CALLER)
(ALWAYS THf
CALLED)
Figure 3 - Supervisor and processor
them as closed subroutines. Processors differ from
traditional subroutines in that no processor" can call
another processor. A processor can only execute and
return control to a supervisor; usually, the supervisor that called it. Some processors are general in
nature, as in the case of certain mathematical operations. Processors of this type can be shared by supervisors. Processors receive no input data from Executive. Supervisors receive and supply the processors
with the data needed for the processor's execution.
Supervisors and processors are relocatable units;
i.e., they are dynamically buffered" from static storage
on the Large Core Storage (LCS) to core by Executive when their logic is needed. The origin of a supervisor or processor in the 7094 core is at an address
which is a multiple of 256. This address, termed base
register, is set by Executive into the relocation register prior to execution of the processor or supervisor.
Although every supervisor and processor is assembled
with addresses relative to zero, the base address
(contents of relocation register) and the offset (gen-
218
Fall Joint Computer Conference, 1967
erated by the program at assembly time)'are summed
in the hardware for specification of actual memory
addresses. Address protection is also performed in
the hardware; the upper and lower bounds of a supervisor or processor in core are set into the protect
registers by Executive when the element is brought
into core. If the processor or supervisor references a
memory address outside these bounds, a protection
interrupt occurs. Certain "protected" instructions
also'cause an interrupt.
Although the Executive is primarily a core resident
monitor existing in the lower 13K of the 65K core
memory on the 7094, it too has about a dozen functional programs in the form of supervisors and processors that it buffers in and out of core as needed.
As a comparison, the Gemini Mission System contains about twenty supervisors for centralization of
flight/vehicle control logic and for supervision of data
processing and mathematical computation. Nearly
250 processors are callable by the supervisors.
Standard argument area
Every supervisor or processor contains a ten-word
table, called XTRANS (see Figure 3 and Figure 4.1).
When any program requires processing by another
program, the "calling" program fills its own XTRANS
with whatever data the "calied" program needs to
interpret the request.
For example, in a program used to compute square
roots, an XTRANS convention would be established
by the program. All other programs requiring square
roots would follow the convention. This convention
could be: when the square root program receives control, it will calculate the square root of the quantity
contained in the first cell of XTRANS. This square
root program also would specify that the third word of
XTRANS will always be set to zero (Figure 4.2), unless. some error occurs in the square root calculations
(Figure 4.3). This simple example could be complicated slightly by changing the program to a generalized
root extractor. In this case, the root extractor program might define the first word of XTRANS to contain the argument, the second word to contain the
power, the third to return an error code or zero, and
the fourth to contain the absolute answer.1
Once a supervisor or processor (program) defines
its input and output XTRANS, that program's services are available to any programs requiring them.
When one program (usually a supervis'or) calls another
program (usually a processor), Executive moves the
contents of the caller's XTRANS to the XTRANS of
the called program. When the called program completes and returns control to Executive, Executive
moves the contents of the completed program's
XTRANS back into the XTRANS of the caller, as
shown in Figure 5.
Standard control interface
lhe Executive provides a standard interface which
is used to pass control between application programs
(supervisors or processors). By using this interface,
the Executive solves such problems as: allocating a
program to main memory prior to execution, executing
programs according to their priority in the system,
and multiprogramming the asynchronous flow of
many paths of logic. (See Multiprogramming Aspects
below.)
The responsibility of determining how the Executive should pass control from program to program
rests with the programmer by use of the CALL statement. The CALL statement requests a service from
the Executive, while the arguments dictate how the
service should be performed.
The mechanism of a CALL statement is to enter a
specialized Executive routine in the resident nucleus,
provide the routine with arguments supplied in the
CALL statement, and have Executive execute according to the definition of the service and the supplied
arguments.
To reach the resident Executive routine to perform
the service requested by the CALL statement, a
subroutine, which was attached to the supervisor or
processor (element) at assembly time, is first entered.
(Each Executive service has its own subroutine.) This
subroutine simply places a certain code in a Store-andTrap (STR) instruction, and then executes the instruction. The executing of the STR causes an interrupt (trap) in the 7094. The Executive fields the trap,
interprets the code, and transfers control to the
specialized routine designated by the code.
Multiprogramming aspects
As noted in the Introduction, the Executive is a
multiprogramming system; i.e., it permits many independent paths of logic to proceed asynchronously
and is able to switch control of the CPU (Central
Processing Unit) from one path to another, depending
on the priority of a supervisor or processor and its
availability for a particular path. The priority of the
supervisors and processors is determined by the order
of its entry in the Executive priority table. This entry
not only establishes the element's priority but reflects
the general status of the element at all times by giving
the following indications:
• Is currently operating or idle.
A Real Time Executive System for Manned Spaceflight
219
Executive
~
XTRANS Table
10 Words
PROGRAMS
Figure 4. 1 Standard Argument Area: XTRANS
I
~ XTRANS (1)
I
XTRANS-(2)
I
I
"
25.0
5.0 ~
XTRANS (3)
\
O~
I
_\
\
I
I
I
\
~
I
,
"
ROOT
/
/
SQUARE
I
/
,/
,
\
\
\
\
X
T
R
A
N
S
/
T
~
A
B
L
E
/
/
/
/
~ XTRANS (1)
5.0~
XTRANS (2)
/
I
"
-25.0
XTRANS (3)
1
I
~. ' \
\
I
\
I
I
\
\
,
X
T
R
A
N
S
,
\
J
T
~
A
I /
"-
I /
SQUARE
""-
PROGRAM
1/
ROOT
'/
,/
PROGRAM
Figure 4.1 - Standard argument areas: XTRAN S
Figure 4.2-4.3 - Square ro.ot program
• Has one or more XTRANS waiting in a queue to
be sent to another supervisor or processor.
• Is being loaded into core.
• Is in core at location XXXXX, or is not in core.
• Is on LCS (program must be loaded from tape to
LCS to core for execution; programs generally
loaded into LCS from tape once per many core
loads).
• Is a supervisor or processor.
• Is privileged (runs with Executive ignoring protect interrupts).
• Is suppressed from running.
B
L
E
220 Fall Joint Computer Conference, 1967
-.
XTRANS OF
CAllER
Calling
Program
f+----
V
~--- ....
XTRANS OF
CAllED
""
XTRANS
XTRANS
Called
" ",
1
XTRANS
Function B Function C
Function A
Program
......
SUPERVISOR
F
U
N
C
T
N
C
T
I
F
U
N
C
T
I
0
0
N
N
N
A
B
C
F
U
I
0
EXECUTIVE SUPPORT
Figure 5 -Executive and XTRANS
The order of the entries in the priority table is
established by the applications programmers through
a macro at nucleus assembly time. During execution,
Executive scans the priority table from the top each
time a status change occurs. When Executive finds a
program ready for execution, the scan stops, and that
program is given control.
A supervisor further inhances multiprogramming in
that it consists of one or more programming elements,
called functions. Each function has its own XTRANS
area and may operate independently; in addition, all
functions share a single copy of a permanent data area
kept for each supervisor in a special buffer called
XTPERM. (See Figure 6.1.) XTPERM is permanent
since the Executive preserves the contents of the
table when the main core storage occupied by a supervisor must be made available for other uses. When the
supervisor again receives control, the supervisor's
XTPERM is exactly as the supervisor last left it. Processors have no XTPERM but many have temporary work space while executing. The size of
XTPERM" is established by the programmer to fit
his needs for permanent data. There are probably no
two supervisor XTPERM's the same size in the
RTCC systems.
The second level of the two-level mUltiprogramming
structure discussed in the Introduction of the paper is
found in the functions of supervisors. Functions have
an internal priority that determines which function is
to receive control when two or more functions of a
supervisor compete for control.
The function's design is based on the concept that
a small package of functions (a supervisor) could
effectively generate a number of parallel logic paths,
and that multiprogramming will occur almost without
XTPERM For
All Functions
Figure 6.1 - Three-function supervisor
the programmer being aware of it. With a number of
more-or-Iess independent logic paths operating
asynchronously, the Executive can maximize the
effective utilization of the CPU.
The supervisor function can call a processor several
different ways. The classical method is to call a processor as a subroutine (see Figure 6.2). When the processor completes its task, ~t returns control to the
function at the next instruction after the call. The
function is ~ut of operation, so to speak, until the
processor completes.
XTRANS
....-----t~,
F
U
N
"
'"
XTRANS
C
T
I
o
PROCESSOR
N
XTPERM
Figure 6.2 - Function of supervisor calling processor
A Real Time Executive System for Manned Spaceflight
Anotner approach permits the supervisor function
to "send" a call to the processor so that the function does not give up control. Consequently, for calls
that are sent, a function may call a number of processor (see Figure 6.3). In this method, a function
may initiate a number of parallel operations. Furthermore, sending calls provides another control option.
The supervisor function, in sending a call, can permit
the processor to determine whether a return is to be
made or not.
ueue for
XTPERM
221
PROl #1
Queue for
#2
XTRANS
XTRANS
PROC #1
PROC #2
Returns
XTRANS
to FUNC 1
No
Return
End Logic
PRO}
Figure 6.3 -Calls sent to processors
If no return is to be made, the processor represents
an "orphan" task in mUltiprogramming that simply
executes and completes the task entirely. Thi~ is a
fairly typical operation where processors update
D/TV displays and no return to a supervisor function
is. expected, that is, unless something unusual is uncovered in the processor's execution. If the processor
returns, it must return to the start of the function
specified by the arguments in a calling sequence of the
original calling function. The function returned to may
even be a function of a different supervisor. Therefore,
the processor is effecting a transfer of control without
knowing where this control is going.
Finally, functions of the same or different supervisors communicate by calls that transfer the
XTRANS of the calling functions into the queue for
the called function. If the calling function has the
higher priority, control remains with that calling
function.
Real time processing
Basically, we have placed the Executive in lower
65K core and stated that it performs allocation of
supervisors and processors into main core storage
from the LCS (more on allocation later in the paper)
when a requirement for the supervisor and processor
is known.
We have shown the supervisor (with its functions)
and the processor giving request to the Executive
for certain services. Now we turn to the major requirement for a supervisor or processor to be brought
into operation. That requirement is the receipt of real
time data.
Real time data receipt
In Figure 7 we find a processor in operation when a
data channel trap (or interrupt) is received from the
7281 DCC (channel F). What has happened is that
222 Fall Joint Computer Conference, 1967
Routing Logic is Shown
Chan.
Chan.
Chan.
Chan.
D
C
B
A
-'co_re fi Ie
Displays/Switchover
Tapes
_T_a~p_e~s/P~r_in_t_e~rf_C_a_r_d_r_e_a_d_er________~
t
'r ~Ir
Executive
DCC
(7281)
Chan. F
·Comm."
lines
&
time
chan.
r------- ~
~-----~:.
Save machin. e
conditions
Time Type of tra~p~____________O_u_tP_u...,t
Data
+
t
Store data in
buffer pool
"
Clean-up last
output
Log data
ROUTE
•
~ STOR~
Queue
input
logic
Save data
in core
file
---.. . . . . +.4---.
•
,
Unqueue and
output next
request
Log data
Scan priority (Sequencer)
Processor
XTRANS
Save buffer
for traps
I
I
Data trap on
chan. F
Figure 7 - Trap control logic
data is now being placed in a buffer in lower core by
the hardware. (Each of the DCC input subchannels
has an addressed buffer in lower core.) The Executive receives control from the processor when the
interrupt occurs and saves those registers and addresses that will permit return to the processor without change to the conditions existing before the interrupt occurred. Executive takes the data that has
been placed in the input subchannel buffer and places
it in' a main core buffer pool for it to be logged onto
an output tape. The other process that Executive performs on the data is termed routing and is covered in
the next section. Now that Executive has received
control via the data channel interrupt, it has an
opportunity to scan the priority table to find the
highest priority element (supervisor or processor)
with a work queue waiting for it. The element found
in the scan is then entered.
A Real Time Executive System for Manned Spaceflight
There are, of course, other Data Channel Interrupts, as shown in Figure 7, for channels A, B, C,
andD.
Executive
Creates XTRANS
From Routing
Directive
Routing
The RTCC computers must interface with other
computer installations and man/machine devices.
Additionally, the RTCC computers must keep in step
with Greenwich Mean Time (GMT) so results will
be maintained in real time and will be synchronized
with computing efforts elsewhere. The Executive
routing feature manages the input from the communications lines (DCC) and routes data and time (GMT)
to the proper functions and processors.
The routing logic is part of Executive; however,
Executive makes no original decisions as to the destination of input. Routing information (directives)
for time and data is supplied to Executive by the
application programs. This information is stored in
routing tables associated withDCC input subchannels. The user must activate and deactivate the
directives by chaining.
When data arrives in the system, the data identification (ID) is compared to all possible ID's of data
that might arrive over that subchanneL When the data
ID matches an ID stored in a chained routing table,
the routing table information is used to queue the data
to an input function or processor, to store the data
until a future time, or to discard the data because they
are not needed.
When time arrives in the system, the current time
(G MT) is compared to all routing tables which are
used to direct queues depending on time. Routing will
generate a queue to all functions and processors for
which the request for time has been met.
Time signal routing
One type of routing is time·routing. For instance,
suppose a supervisor has to produce display output
every second. The supervisor would inform the
Executive that the supervisor requires control every
second. The Executive would file this request in a
routing directive for future reference. (See Figure 8.)
Every second thereafter, the Executive would
notice, while scanning its time routing directives, the
name of this supervisor listed as requiring a call every
second. The Executive would create an XTRANS for
the supervisor and would, in effect, call its type; i.e.,
time, and the current time. The type code would distinguish this particular XTRAN S from any other
types of XTRANS the supervisor may receive. (It
should be noted that supervisors may call upon this
supervisor with other type codes in XTRANS.)
223
......
-- - -
.......
"~
Routing .
Directive
Time to
Super 1
Resident
Nucleus
XTRANS
Ready for
Super 1
.,
/
/
////~
XTRANS of
Super 1
"
Super 1
Buffer
Space
~
Figure 8 - Routing of time
It is particularly important to note that the supervisor need tell Executive only once that repetitive
calls are required each second. The Executive will
generate these calls every second, indefinitely, until
the routing directive is modified or cancelled.
After the XTRAN S is created, the Executive would
attempt to give this XTRANS to the supervisor so
the supervisor can begin processing. Frequently, a
supervisor or processor cannot immediately receive
the latest XTRANS because:
a. The supervisor or processor is not in main core.
b. The supervisor or processor is busy doing something else.
c. More important work, i.e., some other supervisor or processor has to be done first.
These problems are avoided, or at. least deferred, by.
inserting the XTRANS into a queue for the supervisor
involved. Every XTRANS, given to or created by
Executive, enters a queue for the program that is to
process the request. The queue is ordered chronologically; the earliest request is always at the top of the
queue. When the program involved is available in core
and has the highest priority, the request le.aves the
queue immediately. Otherwise, requests wait in the
queue for their turn. Each ti~e a program completes
processing of one request, the program is available for
the next request in the queue (see Figure 9).
Real time data routing
The Real Time routing in Executive brings real time
data to the application programs. The data routing
224 Fall Joint Computer Conference, 1967
Real
Executive Space
Time
Data
Queue
for
Proc 1
1st & Last
XTRANS
For Proc 1
RT
Data
Buffer
Queue
r
2nd & Last
for
Super 1
1st XTRANS
Routing
XTRANS
for
Directive
For
Super 1
Data For
Super 1
Super 1
/
/
/
/
Buffer Space
/"
/
Figure 9-Queues ofXTRANS
process is similar to the routing of timing signals.
The application program specifies a routing directive
for data. This routing directive is composed of two
parts: the first gives Executive the criteria to identify
the particular data the program requires, and the
second part of the routing directive tells Executive
what to do with the data that satisfy these criteria.
There are basically two options for applications
programmers in routed data; direct routing, and storemode routine. (See Figures 10 and 11.)
Direct mode routing
RTCC has few variable length messages. Messages
of a given type generally have a constant size. Some
types of real time data messages are small enough to
fit within an XTRANS. For these messages, the programmer can specify direct mode routing. When a data
channel interrupt occurs, Executive simply creates an
XTRANS table, places the data into the XTRANS,
and places the XTRAN S into the queue for the program named in the routing directive. When the program receives the XTRANS, the data are then ready
for processing.
If the data are too large for the XTRANS~' the Executive places the data into a buffer in lower core and
places information in the XTRANS that describes the
location of the data in the buffer. Using the information provided in the XTRANS, the program obtains
"
Points to
Data in Exec"
S
E
o
o
M
M
Figure 10- Direct mode data routing
the message by executing a CALL statement to request the Executive Real Time Input/Output Control
System (RTI OCS) to move the message into the program's area.
The direct mode of routing (as demonstrated in
Figure 10) is generally most effective for the small,
non-repetitive real time data inputs.
Store mode routing
For cyclic real time data applications, processing
usually consists of two phases: data collection, and
data processing (see Figure 11). The data collection
process can be processed entirely by the Executive.
The programmer defines a routing directive that instructs the Executive to store the selected data into
a data table on the LCS (data tables are termed
Z-tables). The programmer also creates, separately,
a routing directive that causes Executive to generate
a periodic XTRANS as a function of time. When the
A Real Time Executive System for Manned Spaceflight
225
mine the type of call and then passes control to the
associated Executive service routine.
Executive sequencer
(1) Moves Data ta ZT ABLE
('2) Te lis ~per 1 When
Cycle Starts
Routi~
Directive
Time for
Super 1
Routing
Directive
Data Into
ZTRTIN
The Executive Sequencer consists of those routines
within Executive which service the real time system
by:
a. Interpreting Central Processing U~it (CPU)
traps which occur from the execution of an STR
instruction within a relocated element.
b. Servicing floating point and protect CPU traps.
c. Assigning control to the highest priority element
which has work outstanding.
d. Saving and restoring machine conditions when a
data channel trap or CPU trap occurs.
e. Interpreting requests for transferring control
between the elements of the system.
Real time input/output control system
Figure 11 - Store mode routing
program receives this XTRANS, it requests RTIOCS
to read the collected real time data from the Z-table
into a designated area of the program for processing.
The major elements of executive
We have placed Executive in the Real Time system and shown to a limited extent how it provides
the support and control necessary to sequence the
execution of the various supervisors, functions, and
processors through their request and through the
receipt of real time data. We have spoken of Executive in general terms and definitions; now, we can
turn to a brief description of some of the major elements that give Executive its structure.
Executive linkage
Executive linkage with supervisor/processors is
effected through library routines appended to supervisors/processors at assembly time as the result of
CALL statements within the supervisors/processors
and associated service routit:tes within Executive. As
has been shown pr~viously, when an Executive
capability is called by a supervisor/processor, the appropriate library routine in the supervisor/processor
sets up and executes an STR instruction that contains
a numerical code identifying the type of call. Execution of the STR instruction causes control to be passed
to Executive under hardware control. Executive
references the .code in the STR instruction to deter-
The purpose of the Real Time Input/Output Control System (RTIOCS) within the Executive is to
provide a simple (from the programmer's standpoint),
flexible communication link between the supervisors
and processors and the various input/output media
available in the RTCC (no "Raw I/O" is allowed outside the RTIOCS). The RTIOCS consist of a series
of integrated routines which perform all necessary
input and output functions to the following devices
and storage media employed within the RTCC: Tapes
(Channels A and B), 7286-11 5I2K core file (Channel D), 7281-11 Data Communications Channel
(DCC, Channel F) which consist of 13 subchannels
connected to such devices as plotters on the output
side and real time data receivers on the input side,
the Digital/TV System (Channel C), 65K primary
main core memory, printer and card reader.
The basic framework of the RTIOCS, from the
user's standpoint, is a statement CALL I*GETT or
I*PUTT (* = "R" if the call is made by a processor
and "U" if made by a supervisor) and a series of three
to five arguments showing the action to be taken. A
typical call might be: CALL IRGETT (ZXAMPL,
MYBUFR, NBRWDS, LOCINB, BLKNUM). This
translates to: from data file ZXAMPL, starting at
LOCINB (a symbol containing an integer) in
BLKNUM (a symbol specifying a block number if
this is batch data) transfer NBRWDS (a symbol
which contains the number of words) into MYBUFR
(a symbol for a buffer area, normally within the calling
processor). The data file name termed Z-table name
(in this example, ZXAMPL) is a symbolic name of a
four-word table (File Control Block) in Executive
which defines the data file (its location, its type, jts
226
Fall Joint Computer Conference, 1967
size, and other information pertinent to the particular
device that is the data file). Data files may be on tape,
LCS, main core, etc.
Figure 13 gives an example of RTIOCS servicing
a request for I/O from a user. The same type CALL
service logic using the STR instruction· that was discussed earlier in this paper is used for I/O request.
Dee servicer
The DCC Servicer processes all 7281-11 DCC subchannel traps. These traps may be caused by both
the input and output subchannels. The DCC Servicer moves the data from the cells in lower core in
which the hardware placed the input data into the
Executive Buffer Pool, sets UP information for the
Executive logging routines to log the data, and sends
a request to Routing to route the data.
Dynamic main memory and auxiliary storage
allocation
It was expected that the Geqlini systems would
change from mission to mission and would grow to
exceed the capacity of the computer main memory.
Since this change and growth could not be contained,
the necessary flexibility was built into. Executive to
permit such change and growth. Part of the flexibility
is in the design of the storage allocation routines of
Executive. No permanent storage location is assigned
to any problem program. Storage is allocated on demand and in the quantity necessary to accommodate
the particular program.
Two distinct levels of storage allocation are used.
The first, allocation of main memory, is essential to
every run. It provides for the allocation of areas of
memory to required relocatable supervisors and processors and uses the Executive RTIOCS capability
to load the programs into memory from the LCS (see
Figure 12).
The second, LCS allocation from magnetic tape, is
necessary only when there are more relocatable programs than can be accommodated ·concurrently in the
LCS. It provides for the allocation of areas in the
LCS to relocatable programs (processors only) according to both actual and user-anticipated requirements. It also supervises the transmission of the programs from magnetic tape to the LCS.
When a request for a supervisor or processor is
made, the Executive Sequencer det~rmines if it is in
main memory. If it is not, Sequencer makes an explicit
request for the program by transferring to the Executive allocation routines. If the program is available
in the LCS, the main memory allocation routine
attempts to' allocate memory for it. If the program is
not in the LCS, the LCS allocation program is queued
to bring the needed program from magnetic tape to the
LCS, after which memory allocation will be reattempted.
Once main memory has been allocated for a program, the Real Time Input/Output Control System
(RTIOCS) reads the program from LCS into main
memory. Control is then returned to Sequencer. When
no main memory can be allocated for a program due to
relative priority, activity status, and length considerations, the request for allocation is retained so that it
may be re-attempted later.
LCS allocation is initiated in response to actual
requirements for programs to execute in main memory
or in response to user calls that specify which programs will be placed and held in the LCS in anticipation of actual requirements.
I nitializing the real time system
The final element in a discussion of the Executive
is Initialization. Executive initialization provides
user options for the Executive nucleus to execute in
several modes and in various hardware configurations.
Initialization occurs prior to entering Executive and
prior to starting a real time or simulated real time
operation. The initialization .options permit distinctions between real time or simulated time, real input
data or simulated data, and actual I/O devices or
simulated replacements. The general scope of initialization includes:
• Establishing initial hardware conditions
• Establishing parameters and initial conditions for
storage allocation
• Ensuring proper linkages between certain real
time programs
• Assigning tape drives
• Loading initial data into data files on the LCS
(Z-tables)
• Creating the Executive buffer pool
• Establishing debug request tables.
Prior to entering into the discussion of Initialization, it is essential that we give the two steps the user
must take before his supervisor or processor is in an
application system that is being initialized. The first
step is to accomplish unit testing of his supervisor/
processor and the second is to create the application
system tape.
Job shop simulator
Since· all the Executive services are provided via
the CALL statement, a simulator of the real time environment was easily provided under the IBM 7094
IBJOB system. This capability permits testing of a
A Real Time Executive System for Manned Spaceflight
LCS (corefile)
7094 MOD II
Executive:
~
~ Do core allocation
Data in
Z-tables
~
Process
Store
and
Trap
Request I/O to
obtain logic
~
Suppress new
~
\
\
\
logic (not in core)
Queue new
logic
\
All supervisors
and processors
\
\
\
+
New logic
in core
~
No
\
,r
\
\
\
Priority scan (Sequencer)
I
\
t
\
Enter the highest
priority function
or processor
L.....-
227
V
\ ..
Vt V
N- r----- r----
New
logic
Supervisor requests for
contro I services
LCS = Large Core
Storage 512K CCF!LE
Figure 12 - Program control flow
single processor or supervisor, or a supervisor and
several processors, in a batched-job system. Some of
the more exotic features of Executive's multiprogramming facility cannot be simulated adequately in a
sequential (essentially IBJOB) environment. But for
most unit, string, or subsystem testing, the Job
Shop Simulator is very effective. The fact that processing is sequential often makes it possible to identify
bugs before the environment changes completely (a
constant problem in multiprogramming debugging). In
addition, the capability of conducting significant
debugging in a batch environment greatly economizes
the computer time required to deliver checked out
systems.
Creating the real time systems tape
When unit testing has been completed with the Job
Shop Simulator, the programs can move unchanged
228
Fall Joint Computer Conference, 1967
LCS {corefile}
7094 MOD II
Executive:
I/O channel
Process
Store
and
Trap
busy
No
~
Interpret
,
!
Yes
Drive
I/O
I/O request
Queue the
I/O request
Suppress
logic
Priority scan (Sequencef)
+
Requested
data
r
Enter another unit of
logic or wait for I/O
Supervisors
and
Processors
Processor requests
for I/O services
(buffer)
Figure 13-Real time IOCS
into the real time system testing environment. The
first step is to create a real time system tape.
The Executive has been described as a single-computer program serving many real time applications
systems. The user must define his application system
to the Executive by building tables inside the Executive. This is accomplished by macro statements that
the user inserts into· a speCial Executive card deck.
When this deck is assembled, the user's section of
Executive is created. These macros basically define:
a. The supervisor/processors of the application
system and their relative priority (the priority
table)
b. The file control blocks (for Z-tables)
c. The initial routing directives.
During the building of the system tape, the user's
decks are combined with the Executive code to produce the "Executive nucleus. In the process, all of
the symbolic names (program names, Z-table names,
etc.) are translated into indexes. The translation
A Real Time Executive System for Manned Spaceflight
process simply trades pre-execution time to save
translation in real time. The nucleus Executive is
written on the real time system tape along with copies
of the remainder of the non-resident Executive and all
of the user's application system programs.
229
run under either the error halt or the error recovery
mode. Once this system is started in the error halt
mode, the mode may be changed to error recovery and
back, at the setting of a sense switch. Once the system is started in the error recovery mode, the mode
may not be reset.
Real or simulated time
The first significant Initialization option is whether
or not the user requires an internal/external clock synchronization. Unless external devices (including other
computers and/or people) are involved, synchronized
time is rarely used. U nsynchronized or simulated time
simply uses an internal clock that never runs when the
computer is idle. When idle time occurs, this clock
is spaced forward to the" next clock interrupt. For
example, this feature permits an orbit of 90 minutes
to be completed in about 10 minutes of elapsed time.
No changes are required in any applications system
program. In fact, there is no wayan application
program can tell that a simulated clock is being used.
When running in the simulated mode, the user can
specify that any or all of the real time input devices
(subchannels) are to be simulated with canned data
from tape or, in some cases, the card reader. Any of
the real time input devices can be simulated while the
remainder accept actual data, or are unused, in any
combination. Furthermore, the real time output
devices can be used or the outputs can be diverted
to the LCS by requesting on-line for Initialization to
modify the file control block.
Debug request
The RTCC version of the IBJOB debugging system that permits core snapshot dumps, heavily used in
job shop runs, is also available when running a real
time system in the simulation mode. Since the debugging package operates with the simulated clock turned
off, the applications programs cannot recognize that
the debugging operations are taking place.
When a real time run is specified, initialization
automatically removes any debug requests.
Error halt or error recovery mode
The normal inclination of the real time Executive
is to continue processing, regardless of any errors
that may occur. Some error recovery action is instituted in hope that the condition was only transitory.
This is the sensible approach to real time support. But
in debugging a system, especially a highly dynamic
mUltiprogramming system, evidence should be saved
as soon as the error is discovered. Consequently,
another initialization option permits the system to
Real time statistics
Another initialization option permits the user to
accumulate statistics during a real time run. The
accumulation of statistics operates only in the synchronized real time mode and generally requires about
five percent of the CPU in overhead. (The RTCC
experience has been that the five percent of the
CPU is not the difference between success and
failure in a real time run.)
Once the initializatipn option has been set, the
Statistics Gathering System (SGS) may be activated
or deactivated dynamically from the Manual Entry
Device (MED) or by the card reader used to simulate
the MEDs. Statistics are accumulated in three categories:
a. Internal Executive Logic - frequency of use,
average execution time, core allocation attempts
and successes, etc.
b. Supervisor and Processor- number of uses,
average "execution time, number of uses per time
loaded into core from the LCS, number of Executive CALL's, etc.
c. Total CPU Utilization-amount of time in
execution, in waiting on I/O, and idle.
SGS, originally conceived and "implemented to
support the extensive GPSS (Gordon General Purpose System Simulator) modeling activities at RTCC,
has proved useful to many of the applications programmers in analysis of their systems.
OperationalJeatures oj executive
Real time run synopsis
When the run terminates, the user has the option of:
• A synopsis that consists of a formatted presentation of all the significant Executive tables: the
state of the priority table, the state of all the
processors and supervisors, the chains of
XTRAN S in the queues for all the. processors
and supervisors, etc.
• An octal dump with assembly language operational codes.
• A full symbolic dump.
If any debugging system snapshots were taken,
these are formatted in the post-execution processing.
Programmers generally take the synopsis and 'an octal
dump.
230
Fall Joint Computer Conference, 1967
Real time internal control mode and generalized
on-line display capability
The 'Real Time Internal Control Mode (RTICM)
of Executive gives the user of Executive more control of the multitude of initialization and dynamic
options, while giving the user the capability to exercise these options remotely. Most of the Executive
options, prior to RTICM, required the user to set
and reset the sense switches and keys of the 7094
console. RTICM permits all options to be punched
into cards and allows selective dynamic use of these
cards to be governed by the processing itself. The online display capability allows a user to select dynamically, via the Manual Entry Devices, information
from main core on the LCS to be displayed on the
television system. The information can be selected
symbolically, saved, and recalled by name.
Reliability
During the Gemini and Apollo missions, the Executive is keyed to keeping the real time system up and
running no matter what adverse conditions are encountered. In doing this, the Executive has provided
an elaborate Error Recovery System to intercept program errors, hardware generated errors, and data
generated errors. When one of these errors are encountered, Executive quickly examines the situation
and produces an appropriate .recovery method to
enable the real time processing to continue. If the
error encountered is of such a nature that recovery
is either impractical or unfeasible, the Executive
will recommend Switchover to a standby system. If
necessary, the 65,000 words of core memory and the
524,000 words of COFIL memory can be transferred from this standby computer to a new operational computer by the Executive RESTART logic in less
than five minutes. In the worst case, real time processing is never delayed more than three minutes. If
an I/O device fails in any manner, Executive provides time-out logic to ensure that failure on one
device will not interfere with the remainder of processing in the real time system. If tapes fail or become
full, Executive provides tape switching logic.
CONCLUSION
Some of the basic ideas for the Executive were developed in the Real Time Mercury Monitor for
NASA's Project Mercury and, in turn, some of the
ideas conceived in the Executive design are being used
in the development of the Real Time Operating System/360 for Project Apollo. It has been found in
these endeavors that real time system development is
an evolving creature, for the predominant requirement in its development is that its design must be
able to evolve as the environment in which it will
operate is understood. 2
REFERENCES
J H MUELLER
The philosophy of the RTCC control proRrams
IBM Real Time Systems Seminar Proceedings 1966
2 R L HOFFMAN
Managing the design, development, and implementation of
large scale generalized real time systems
IBM Real Time Systems Seminar Proceedings 1966
Executive programs for the LACONIQ
time-shared retrieval monitor
by D. B. I. BRIDGES
Lockheed Palo Alto Research Laboratory
Palo Alto, California
INTRODUCTION
LACONIQ* was designed to give several users who
are not necessarily familiar with programming the apparently exclusive on-line use of a small computer for
processing large information files. Processing of the
data may include manipulations such as retrieval, updating, or the deletion or creation of records, documents, files, etc. Thus, LACONIQ is general-purpose
in the sense that many types of information files may
be processed, but is special-purpose in the sense that
scientific computations on-line are not necessarily intended to be practical.
Considerations which led to the major design decisions for LACONIQ are given in reference 1. The introduction and bibliography from an early version of
reference 1 are reproduced by Appendix A. Very briefly
summarized, the more important features of the system
are its multilevel structure (user-application-monitor),
the event-driven rather than clock-driven nature of the
system, the polling of consoles at the convenience of
the system, the avoidance of program roll-out to a
peripheral device, and the scheduling of resources for
a small computer.
This paper is primarily concerned with the development of LACONIQ executive program~ on an IBM
360/30 computer. The four sections immediately following are principally concerned with overall system
considerations including hardware, software, and pertinent system events. The remaining major sections proceed from the general to the detailed regarding a central exe~utive scheduling program for LACONIQ.
Hardware
LACONIQ is programmable on any small computer
that has moderate capabilities for programmed and
I/O interrupts, storage prote~tion, base registers, etc.,
*LAboratory Computer ON-line InQuiry monitor.
231
such as the IBM 360. 2 An IBM 360/30 with 32k
bytes of 1.5 J-tsec core was chosen for experimental exploration of the LACONIQ design. The hardware configuration is shown in Figure 1.
2311
Disk
IBM 360/30
Inlernl~S
Storage Protect
!:c~a&e RegiBten
Selector
t----+r.Ch:::ann:::;el-t-----4~ MPX Channel
32k Core
BOS
LACONlQ
Free Storage
1052
Console
Figure I-Hardware for initial LACONIQ implementation
In the LACONIQ system, core is divided into three
main areas. One area contains the IBM Basic Operating
System (BOS) and a second area contains the LACONIQ system programs. The remaining free storage
is dynamically allocated to application programs,
scratch areas, and internal buffers.
The minimum peripheral storage needed for LACONIQ is one disk. The disk must contain BOS and
areas assigned for application programs. The disk may
also contain areas for working storage, file directories,
and data. Ordinarily, large data files would be stored
on a bulk storage device such as an IBM 2321 data
cell. Two disks and one data cell were used on one selector channel for the initial LACONIQ implementation because information retrieval from a large file was
one of the prototype system applications.
The on-line consoles used for LACONIQ contain
recirculating buffers large enough for one full CRT
232
Fall Joint Computer Conference, 1967
screen display of 960 characters. The presence of this
buffer allows LACONIQ to interrogate each console at
a convenient time from the point of view of the system.
The initial hardware' configuration included three IBM
2260 CRT consoles of which one or two were attachable at a remote location.
A small printer was attached· at each controller principally for user-initiated display printout. The CPU
console, line printer, and card reader attached to the
multiplexer channel are used by BOS and some of the
LACONIQ diagnostic procedures.
Types
0/ LACONIQ programs
Since the system is oriented toward a particulaI
series of applications (information processing), all programs might be considered as application programs.
However, a division of the LACONIQ software into
two major levels, application and system, enables the
use of the system to be more conveniently specialized
for each of the several different types of processing
which may be desired on the several different.infor!l1ation files accessible to the computer.
The first level of software, with which the unsophisticated console user interacts most directly, consists of
prewritten application programs especially tailored to
efficiently process data from his file or request input
(output) from (to) his file. The second or inner-most
level of software consists of system programs designed
to satisfy the requirements of all users on a resourceshared basis.
The system programs and application programs have
some conventional characteristics. In general, a system
program is general purpose, frequently used, and resides permanently in core. An application program is
special purpose, less frequently used, and resides on
disk storage.
A third class of programs in LACONIQ is called
application-zero. The name is derived from the assignment of J.D. numbers to LACONIQ applications in the
series 1,2,3.... Zero is used as the J.D. number of
the system-type applil.:ation programs mainly for ease in.
verbal reference. Application-zero programs are general purpose (system) in function, but reside on disk
to save core space at negligible degradation of response
time (because they are relatively infrequently used).
Application programs
Application programs are written in assembly lan~
guage except for I/O. * There have been three principal
pilot applications written to date. 'One of these concerns text writing, updating. and retrieval from a data
tank of engine~ring documents. A second is concerned
with processing of failure data on missile component
parts. Another application finds facts from a file of
information concerning military capabilities and· resources. A set of disk-resident programs is written
especially for each data file and particular processing
goal. LACONIQ imposes few restrictions on data file
organization. Application' programs include the capability for on-line dialogues of the type described in
refer~nce 4. Generally, these dialogues give the user
the result of each significant processing step and provide options for continuing the process or for returning
to a previous step. The user's response is frequently a
single key stroke or the typing in of a word, but in
textwriting applications the user could type in several
hundred characters .. Typically, application programs
include optional tutorial dialogues to acquaint the console user with how to use the system to manipulate his
data file.
The applications are programmed in separate segments. which are brought into core one at a time for
each console. Each segment is executed to completion
while residing in core. Its execution may be interrupted
by its own requests for service or by I/O interrupts.
Also broqght into core with each application segment is a self-descriptive section and the identification
of all possible successor segments. These descriptions,
written by the applications programmer, contain data
such as segment length and block size. The descriptions are stored in a reserved area of core which includes a communication area (for transfer of data from
one segment to the next) and an input area (for short
console inp.ut strings).
System programs
The LACONIQ system programs and their principal
interconnections are shown in Figure 2. The central
scheduler performs various housekeeping tasks, makes
entries in I/O queues, assigns priorities, and gives control of the CPU to system programs or application segments as required. The functions of the two programs to
the left of the central scheduler (Figure 2) and the two
programs to the right are parallel. The programs on
the left resolve I/O needs for console communication
and the programs on the right are concerned with I/O
for peripheral storage. The latter include input of both
data and program segments as well as data output.
The programs horizontally adjacent to the central
scheduler perform the task of scheduling I/O requests
for particular devices. If these devices are not busy, the
schedulers call their respective control programs which
issue the required CPU instructions and channel commands to initiate a request.
*The use of a higher level data manipulation language such
as ALTEXT3 is currently under investigation.
Executive Programs for LACONIQ Time-Shared Retrieval Monitor
-----,
~~~-
I
Figure 2-LACONIQ system program organization
A complete discussion of the scheduling algorithm
for peripheral devices is given in another paper.:I Very
briefly summarized, it schedules I/O for slow devices
before fast devices and gives preference to queued requests which require a minimum physical (e.g., disk
arm) movement from the current position.
The scheduling of console output requests is handled partly by the central scheduler and partly by the
console scheduler. When the console scheduler is called,
it checks the controller line status and if the line is not
busy, it passes the next request in the queue to the control program.
The two principal types of interrupt programs are
for Supervisory Call (SVC) and I/O interrupts. The
SVC on the IBM 360 series machines has several functions. One is to cause an interrupt with up to 256 different programmed interrupt codes possible. LACONIQ currently allows 16 of these codes to be used
by application programs for service requests. Requests
for I/O and other service needs are communicated to
the executive routines via SVC interrupts. The I/O
interrupt routines for consoles and for peripheral devices up3ate various status indicators whenever channel or device end interrupts occur.
Not shown in Figure 2 is the program which dynamically alloca.tes and releases free core storage. The storage algorithm has been described in another paper.5
Briefly it involves look-ahead procedures utilizing the
application program segment descriptions. This allows
division of free storage into occupied and usable areas;
the usable area is divided into available and storage-inwaiting.
Allocation requests originate principally in one or
another of the three schedulers. Release of program,
scratch, and peripheral input storage is usually set up
by the SVC exit routine. The application segment requests the SVC exit routine when it has finished execution. Storage for console input is released at input interrupt time provided input is less than 33 characters
233
(the usual case) when the input is stored in a consolededicated area. Release of output buffer storage is
usually requested by a routine which handles the interrupts· when all output is completed.
Application-zero programs
Examples of disk-resident system programs are
those which output the initial "hello" display to a console, analyze console input, and perform diagnostic
procedures.
The successor segment to an application segment
which has completed its execution may be uniquely
identified in the appropriate successor description area,
or its selection may depend on user console input. In
the latter case, the input analysis program is called into
core. The console input must either match specific
strings contained in the description area or fall into a
category of input described as legal for the completed
segment. The category of input might be, for example,
a string of alphabetic or numeric characters containing
no arithmetic operators or special characters.
Diagnostic procedures in LACONIQ include various
failure levels. For example, if an error is detected in
the execution of an application segment, the user is
usually given an opportunity to re-try. If the error persists, the user may be told via a display that his console is temporarily not operable.
Use of IBM basic operating system
The core-resident LACONIQ system programs all
look like problem programs to BOS. They ·are assembled and,linked following the ordinary rules for BOS
modules. The BOS Linkage Editor resolves all relocations and the BOS Job Control program puts LACONIQ's initialization program into execution. The initialization program reads the hardware specifications (descriJing the current peripheral environment and on-line
consoles) in from cards, modifies the new program
status words (so that LACONIQ will capture the interrupts), and puts the processor in the supervisory
mode so that LACONIQ programs can execute privileged instructions. The complete status of the. System/
360 is contained in a program status· word (PSW).
Each class of interruption (program, supervisor call,
external, machine check, input-output) has two fixed
locations in main storage: one to receive the old PSW
when an interruption occurs, and the other to supply
the new PSW that governs the servicing of that class of
interruptions. In the IBM 360 certain instructions may
only be executed by a supervisor program. Examples
are instructions for I/O and instructions to set storage
protection keys. If these instructions are executed
in the non supervisory mode (problem mode) a pro-
234
Fall Joint Computer Conference, 1967
gram check occurs and execution of the offending programs stops.
The major parts of BOS which are used on-line
after LACONIQ initialization are physical 10CS and
certain error-handling routines for peripheral devices.
By maintaining its own status indicators, LACONIQ
never causes the queuing procedures in BOS to be invoked.
System events
The two principal types of events in the system
are the SVC and I/O interrupts. Requests for I/O and
other service needs of a segment are communicated
to the executive programs via SVC interrupts. It is considered illegal for a segment to issue I/O control instructions or to use physical 10CS.
The SVC interrupt routines interpret an interrupt
code which reflects the type of service desired. LACONIQ provides SVC codes for the following kinds
of service:
• I/O for peripheral devices*
• I/O for user consoles
• Allocation (release) of scratch core areas
• Movement of data
• Point-to-segment description areas
• Exit (and performance of housekeeping functions)
The SVC exit routine signals one of the fundamental
events in LACONIQ: the segment has finished execution and the core areas it required may be released. A
more common practice in time-sharing systems is to
give each program (segment) a time partition of arbitrary length. (See Biblography and Appendix A.) When
the segment executes for the specified length of time, it
is interrupted and may need to be rolled out to disk
(and later rolled in) if its core space is needed by another program. As explained in reference 1, in addition to avoiding roll-out, completion of each segment
implies fast response time for simple tasks and somewhat longer response time for more complex tasks.
I/O interrupts are accepted whenever application
segments are in execution and periodically when the
central scheduler enables interrupts momentarily. The
console or peripheral interrupt routine executed at
interrupt time posts various status indicators for the
executive programs.
An I/O interrupt of particular interest is the interrupt resulting from the depression of the ENTER
key* by a user on. a local console. This interrupt is
posted and handled later at a time convenient to the
*At
the present time, the application programmer must
write SVC requests for peripheral 110 for particular devices.
Work is underway to allow SVC's for this function which
are device independent.
system. Remote consoles do not generate this interrupt
so they are periodically polled (whenever input is
pending) to ch~ck if the user has depressed the ENTER
key. One effect of the. postponement of handling of
local console interrupts is that all consoles, whether
remote or local, are given the same kind of service.
Other events occur for external and program check
interrupts. The external check usually signals that a
segment has exceeded its maximum allotted execution
time (a rare occurrence) and the program check invokes diagnostic procedures. The storage protect feature prevents an application segment from writing in
the LACONIQ system area of core. The chance of
a program error occurring on-line is considerably reduced by requiring that applications be checked out
with an off-line program called LACSIM which simulates the LACONIQ environment.
A typical sequence of events in the system is given
in Appendix B.
Executive schedulers (general considerations)
It is important to be efficient in use of the CPU in all
on-line system .programs, particularly in the operation
of the central scheduler. Several dominant reasons are:
• The efficient use of the CPU is of interest for nonI/O-bound situations which may aris~ in a given
situation, application, or configuration. For example, LACONIQ could te used with very fast
peripheral devices, or bulk core, or in applications
which are ordinarily compute-bound.
• Overhead costs to on-line console users are reduced.
• More CPU time is available for background processing.
• An endless variety of auxiliary tasks can be performed in CPU time not required for the more
fundamental system functions.
Examples of auxiliary tasks are the gathering of
system performance statistics and dynamic adjustment
of system parameters to attempt to optimize system performance. Examples of tasks of the last type are updating of priorities for requests in queues, adjustments
to ensure equitable distribution of resources to remotely located consoles whose service is degraded by
slow transmission rates, policing of application segments in a partially checked-out status, and controls on
maximum response time to console requests based on
elapsed clock time.
The general LACONIQ approach to efficiency in
CPU usage has been to maintain rather detailed status
*All
CRT communication devices have one or more keys
which the user depresses to indicate that he has finished
his keyboard input. This key is called' the 'ENTER' key for
the IBM 2260.
Executive Programs for LACONIQ Time-Shared Retrieval Monitor
indicators pertaining to the work-in-progress for each
console. Various status indicators are up-dated throughout nearly all system programs to be interrogated by
the central scheduler. The central scheduler gives control to a system program or an application segment depending on the configuration of the rtatus indicators.
An alternative to this procedure whic.t was originally
considered (but discarded because of predicted inefficiency) was to have the central scheduler give control
of the CPU to various system routines on a periodic
basis (rather than a known-need basis). Each system
program would then search various queues and indicators to find something to do. A major disadvantage
to this approach is the time wasted searching for a task
when there is nothing pending.
In the current system, the peripheral scheduler
(PIOS) is the only system program which can get control of the CPU when a need does not exist. Due to the
peripheral I/O-bound nature of the retrieval process,
PIOS always gets control following peripheral I/O interrupt handling so it can immediately schedule another
request (if one is pending-the usual case).
System status information
The system core lay-out in Figure 3 serves as a summary of the principal status indicators in the system.
The selector channel status contains a busy bit for
the channel and a busy bit for each device attached to
the channel. In general, these indicators are set "on"
by the perip.heral control program when I/O is initiated, set "off" by an interrupt routine when I/O is
completed, and interrogated by the peripheral scheduler.
The multiplexer channel status area contains one
bit for each subchannel. This bit is interrogated by the
console scheduler, set to "busy" by the console control
program, and set "free" at interrupt time.
There is one peripheral I/O queue for each peripheral device. Each entry in a queue contains bits to indicate whether the request is in process or finished.
A 32-bit status word interrogated by the central
scheduler (called WIPS for work-in-progress scheduler)
is contained in the system part of each console-dedicated area.
The console status word
The significant status indicators which are grouped
(for convenience) into a single 4-byte computer word
are identified in the left-hand column of Table I. E~ch
indicator is implemented either as a single computer
bit (for YES-NO or ON-OFF type conditions) or as a
group of tits (for the numerical count of the .number
of pending I/O requests) as shown in the second col-
235
BOS
LACONIQ Programs
File Descriptions
Selector Channel Status
MPX Channel Status
Peripheral I/O Queues
Console 1 Dedicated Area
System
Hardware Addresses
Storage Maps
Restart Conditions
Output Queue
WIP Status
I
I
I
User
-
Segment Description
I Succ. Segm. Desc.
I Communication Area
I Input Area
I
I
I
I
Console 2 Dedicated Area
I
I
--
-
I
-
--
[--~
Figure 3-System area of core (two active consoles)
umn from the left. The remaining columns of the table
are headed by names of the principal executive programs which update the status word, i.e., turn an indicator on/off, or increment/decrement a count. A "1"
entry in the table indicates the program at the top
turns on the indicator identified on the left. A "0"
entry indi~ates that the program turns the indicator off.
An "up" arrow indicates that the program increments
the count and a "down" arrow indicates that the program decrements the count.
All indicators above the dotted line in Table I are
individually interropated by the decision logic of WIPS.
All indicators telow the dotted line are checked as a
group by WIPS to indicate work is still in progress for
the console. The purpose of each indicator will become
more app.arent as we discuss the conditions which
cause an indicator to ce updated (in the remainder of
236
Fall Joint Computer Conference, 1967
this section}, and the interrogation of the indicators by
WIPS (in the next section).
The following discussion applies primarily to local
consoles whose console output requests are restricted
to the CRT screen. There are minor variations for
remotely. located consoles and for output requests to
the 1053 printer. The updating of indicators will be discussed in' the order (top to bottom) in which they appear in Table I.
The console inactive bit is turned off when the initialization program reads in a card identifying the console as active. The bit remains off unless one or more
of four things happen: (I) a catastrophic error occurs
in application programs used by the console; (2) failure occurs in hardware used by the console; (3) the
user fails to respond when input is expected; * (4) the
user signs off.
Table I
CONSOLE STATUS WOIm
Pl'ogram Identification
Status Word
Bit Identification
No. of
Bits
Console inactive
WIPS
Console input requested
User has finished input
Console input not
initiated
Console input completed
1
0
1
1
0
1
1
1
1
0
Periphcral scheduler
needed
1
l.0
Tape output I'e quested
Tape output not initiated
1
1
-
Peripheral I/o
Intl'lTupt
t
>1
Console page-back node
point
Page-back not initiated
-
ConsolI'
IntelTupt
S\'C
IntelTupt
1
No. of console output
requests
Console output not
initiated
-
Console
Scheduler
-
Segment input l'cquestcd
No. of disk input
requests
No. of disk output
requests
l'\o. of data cell input
requests
l'\o. of data cell output
requl'sts
1\0. of peripll('ral
transfcrs
-
1
>1
>1
>1
>1
>1
•
1
I
0
I
I
0
1.0
1
0
1
1
I
0
0
-
~
1
-
- -I - 0
t
t
t
t
t
I
1
f---1
•
•
•
•
•
If an application segment executes an SVC instruction for console output, the SVC interrupt program posts the "number of console output requests"
and turns on the "console output not initiated" bit.
Up to four requests may be stacked in each console
*Time-out procedures vary according to the application.
For example, a console might be considered inactive if
there is no response for 5 minutes in one application whereas
a reasonable time-out for another application might be 30
minutes.
queue to allow various combinations of writing modes
(erase, write full-screen, and write with line-addressing). The "console output not initiated" bit signals
WIPS to call the console scheduler which turns off
the bit if the console control program successfully
initiates output. The console interrupt program decrements the "no. of console output requests" and turns
on the "console output not initiated" bit as each reques~ is completed. When the number of console output
requests reaches zero, the console interrupt program
leaves the "console output not initiated" bit off.
The next two lines in Table I ("console page-back
node point" and "page-back not initiated") are concerned with the capability for a user to return or pageback to a previous stage of processing, and restart
from there. Each output display is optionally a pageback node point event. When WIPS detects the node
p.oint, the display and restart information is stored on
disk. The user may invoke page-back by hitting a key
on the console which has been assigned the page-back
function.
The SVC exit routine turns on the "console input
requested" bit and the "console input not initiated"
bit if the segment description in the console-dedicated
area indicates input is needed. When the user has
finished typing his input and hits the ENTER key,
the console interrupt program turns on the "user has
finished input" bit. The console schedule turns off the
"console input not initiated" bit when the console
control program successfully initiates input. When inp.ut is completed, the console interrupt program turns
on the "console input completed" bit. WIPS (later)
turns off the "console input completed" bit when it
enters a peripheral request in the peripheral queue for
either the unique successor segment or the input analysis pfogram (depending on whether the input is
relevant to the selection of the next segment).
The "peripheral scheduler needed" bit is turned on
by WIPS when a segment input is pending to ensure
that the request will be recognize3 in case there is
no peripheral I/O pending. (Recall that the peripheral
scheduler would be called at interrupt time if there
were outstanding peripheral requests.) The "peripheral
scheduler needed" bit is also turned on by the SVC
Interrupt program whenever data cell input at output
is requested. (Data cell input or output requests require a unique successor segment to be input from
disk so that core space will not be taken up while
awaiting console input.) The "peripheral scheduler
needed" bit is turned off by WIPS when the peripheral
scheduler is given the CPU (provided the peripheral
scheduler does not fail to schedule a request because
of temporary shortage of free storage).
Executive Programs for LACONIQ Time-Shared Retrieval Monitor
The "tape output requested" and "tape output not
initiated" bits are handled in a manner analogous
to console output.
The "segment input requested" bit is turned on
by either WIPS or· the SVC interrupt routine when a
successor segment has been identified. It is turned off
by the peripheral interrupt routine when input of the
segment is complete.
The numbers of peripheral I/O requests are posted
by the SVC interrupt routine and are decremented
by one for each request completed.
The central scheduler
The logical flow of control for the central scheduler (WIPS) is shown in Figure 4 in simplified form.
Solid Lines: WIPS
Dotted Lines: Other Programs
i + 1 -
I
i
I
Call System
Program.
Update Status
~f Conso~.
,-
-.J
r--,
Execute
Application
Lsegme~
r-
..J
fEx'ec~ Interr;;l
Programs.
Update Status for
~o~o~ _
t- -
.J
Yes
Figure 4-Basic functions of WIPS
237
The specific conditions which WIPS can. recognize
may be grouped into three categories.
• One or more LACONIQ systems programs are
needed for input message analysis, output message scheduling, peripheral I/O scheduling, paging-back, etc.
• An application segment is ready for execution
• One or more I/O interrupts are pending
When and where to branch out of WIPS for the
first condition is determined by examination of the
32-bit status word in the console-dedicated area. Each
significant bit which is on in the status word relates
to a specific need or event which must occur before
an application segment for the console can be executed.
When the need is satisied or the event occurs, the bit
is turned off.
The needed action indicated by a bit (or bits) in
the status word may be caused automatically as in
the case of the I/O interrupts or by the calling of an
appropriate system program by WIPS. When a bites)
indicates that a system program needs to be called,
WIPS branches to that program with appropriate parameters. If the system program performs its task successfully, return is eventually made to WIPS with the
bites) off. If the system program cannot complete its
task (e.g., because of temporary shortage of free storage), return is made with the bites) still on so that
the need for the task will again be recognized during
a subsequent pass through the WIPS loop.
The second condition, segment ready for execution, is recognized by WIPS when all bits in the
status word are off. (An exception of minor importance occurs for remotely located consoles.) In the
usual case, several passes will be made through WIPS
cefore all the status bits are off. When the bits are
off, WIPS will re-initialize (or initialize) segment conditions (e.g., restore base registers) and branch to
the lo:ation in core containing the next (or first)
instruction to be executed for the segment.
Satisfaction of the third condition, I/O interrupts
pending, will occur when WIPS enables interrupts
once in each cycle through the consoles. Interrupts
are disabled in all other LACONIQ system programs
(except for exceptional situations such as a fixedlength peripheral queue overflowing) so that there may
be one or more I/O interrupt request stacked up. Upon
enabling interrupts, the stacked requests will be handled
by various LACONIQ and/or BOS programs. After
updating of queues and the status words, return is
made to WIPS where interrupts are again disabled
anJ the checking of console status words is resumed.
When WIPS can find no on-line requirements to ce
met, the CPU is available for background. Background
i
238
Fall Joint Computer Conference, 1967
processing will be interrupted periodically to investigate on-line needs. If no background is waiting, WIPS
sets the CPU to the wait state. Entering the wait state
without background processing is the current operating procedure. In the wait state, the meter used by
IBM for accounting purposes does not run. A dock
interrupt is used to periodically leave the wait state
for WIPS to check for on-line requirements. Background processing will be implemented when the core
size of the 360/30 is increased from 32k to 65k bytes.
Figure 5 shows the major logical decision flow in
WIPS in considerably more detail. However, several
auxiliary tasks are omitted from the figure for clarity.
The tasks omitted are concerned principally with updating the priorities of requests in the peripheral queues
which otherwise might not be serviced in a reasonable
time period, procedures (which should rarely be executed) for handling a full queue condition, and
general housekeeping functions. Entry point WIPS is
entered only once, from the initialization program
LACON I. After some additional initialization a pointer
is set at WIPS 1 for the first console. WIPS 1 is reentered only from the WIPS program (the first decision branch after WIPS2) whenever the status words
for all consoles have been checked and it is time to
start over with the first console. WIPS3 is the reentry point from all interrupt routines and WIPS2 is
the reentry point from all other system programs.
Assuming on-line requirements exist, flow proceeds
from WIPS 1 to WIPS2 where interrupts are temporarily enabled. The enabling of interrupts allows recognition by the system of the attention bit (triggered by
the local user hitting the ENTER key) and allows
other interrupt handling in cases where no application segments are in an executable state (where interrupts are always enabled). If an interrupt is pending,
return from the interrupt routine is eventually made
to WIPS3 which immediately branches back to WIPS2.
Thus, all pending interrupts will be handled before
the interrogation of console status bits proceeds downward from WIPS2.
The decision blocks in Figure 5 shaped like the
follow;ng (
) are interrogations of the bits
previously identified in Table I above the dotted line.
As interrogations proceed downward from WIPS2,
tranches are made to the right either for additional
interrogations or to call a needed system program.
For example, if console output has been requested
but not yet initiated, the console scheduler is called
for output.
There is considerable significance in the order in
which the console status bits are checked. (This order
is the same as the bits were listed in Table I.) For
example, it is impossible for a user at a console to
wipe out pending console output or a page-back-inprogress procedure since these bits are checked before console input is allowed. The keyboard at the
console is physically locked out until the pending requests are cleared.
The branches to other programs from WIPS2 occur as needed with eventual reentry at WIPS2 where,
the console pointer is incremented to allow interrogation of the next console's status word. If there are
no system programs to be called and all I/O for
the console has been completed, all significant bits
in the status word will be zero. In this event, flow
will pass straight downward from WIPS2 and the
branch to WIPS4 will be taken. WIPS4 will restore
the user's base registers (1 through 15), the storage
protection key and the problem mode will be set,
interrupts will be enabled, and a branch will be made
to that location in core where the next instructions
for the segment are located.
All I/O interrupts that occur during the problem
state, i.e., during execution of an application segnent, eventually cause WIPS to be reentered at
W'IPS3 where the decision branch goes to WIPS4.
SVC interrupts of the exit type, i.e., those that request
peripheral device or console I/O, that occur during
the problem state eventually cause WIPS to be reentered at WIPS2. SVC interrupts of the non-exit
type cause WIPS to be reentered at WIPS3 where the
decision t ranch faIls through to WIPS4.
CONCLUSION
Although little effort has been expended to measure
the performance of LACONIQ (or even to select the
best performance criteria), the system works well
enough in the laboratory to proceed on an expanded
system which will include background processing, peripheral device independence, additional facitiIies for
writing application programs, and compatibiIty with
the IBM Disk Operating System.
The major aims of this paper have been to point
out the types of events in a system such as LACONIQ,
the interfacing of executive-type programs, and one
way that status indicators may be defined, updated,
and interrogated. The methods used for the latter
appear to be sufficiently efficient for use in the expanded LACONIQ system currently under development.
ACKNOWLEDGMENTS
The design and programming of the LACONIQ
routines which have been described involved all members of the LACONIQ group. In addition to D. L.
Drew and A. Reiter who have been previously cited,
Executive Programs for LACONIQ Time-Shared Retrieval Monitor
Rutore
8el(lftent
Condltlone
Call Con80le
Scheduler
(or Input
Format Requeet
for BucceellOr
Format Requeet
for INAL
Call Program
for Tape Output
Figure 5-Logical decision flow of WIPS
Enter Requeat
In Perlph. Queue.
TurnOff ConllOle.
Input Completed
Blt.
239
240 Fall Joint Computer Conference, 1967
the members of the group have included S. Burr, E. R.
Estes, J. L. Fick, K. R. Gielow, A. J. Nichols, S.
Shayer, and G. T. Uber.
Appendix A
MAJOR DESIGN CONSIDERATIONS
(Excerpts from reference 1)
REFERENCES
2
3
4
5
D L DREW
The LACONIQ monitor: time-sharing for on-line
dialogues
Communications of the ACM (to be published)
IBM CORPORATION
IBM System/360 Summary Form A22-6810
M R STARK
ALTEXT-multiple purpose language manual 6-75-65-15
Lockheed Missiles & Space Company 27 Sep 1965
D L DREW
Two reference-retrieval dialogues
Information Retrieval Note 78 11 Aug 1965 Internal
publication of Lockheed Palo Alto Research Laboratory
A REITER
A resource allocation scheme for multi-user on-line
operation of a small computer
Proceedings of the 1967 Spring Joint Computer
Conference May 1967
BIBLIOGRAPHY
R G CANNING et al.
Five approaches to the same data base problem
Proceedings of the Second Symposium on ComputerCentered Data Base Systems at System Development
Corporation Dec 1965 available from Defense
Documentation Center/Defense Supply Agency
J B DENNIS E L GLASER
The structure of on-line information processing systems
Information System Sciences Second Congress Nov 1964
J W FORGIE
A time- and memory-sharinl: executive program for
quick-response, on-line applications
AFIPS Conference Proceedings Vol 27 Part 2 1964
pp 127-139
INFORMATICS, INC. Staff
Implementation procedure for on-line systems
Technical Paper TP-63-12-WHG
J M KELLER E C STRUM G H YANG
Remote computinl:-an experimental system
Part 2: Internal desil:n
AFIPS Conference Proceedings Vol 25 1964; 425-443.
H A KINSLOW
The time-sharinl: monitor system
AFIPS Conference Proceedings Vol 26 1964; 443-454
G E PICKERING E G MUTSCHLER
G A ERICKSON
Multicomputer prol:rammim~ for a larl:e-scale real-time
data processing system
AFJPS Conference Proceedings Vol 25 1964; 445-461
J F SPITZER
The Colingo system design philosophy
Information System Sciences Second Congress Nov 1964
INTRODUCTION
The basic requirement in the design of the LACONIQ* monitor was that it should facilitate the programming and operation of on-line "dialogues." These
dialogues typically consist of inquiries directed to a
large data -file, to which prepared programs respond
in an attempt to help the system user find and display specific information. The prototype application
is that of document reference retrieval.
This approach led to an event-driven monitor, as
opposed to the usual "clock-driven" time-sharing monitor in which application program execution is carried
on during a fixed interval, then interrupted until the
program has another "turn." In the LACONIQ monitor, each application program is processed to completion. (This is only practical, of course, because the programs are limited in their duration.) _Each such program corresponds to at most one step in the dialogue.
Long operations might require that a sequence of such
short programs (called program segments in the following descriptions) te executed, and this is foreseen
in the monitor. The basic event that governs the timing of happenings in the monitor is then the completion
of processing of a program segment.
This decision to set an upper limit on the amount
of processor time each segment is allowed rather than
to interrupt the segment ("roll it out" to a peripheral
storage unit, and bring it back for later continuation)
was based on a tradeoff between constraining the application programmer and increasing system response
time. Given the conversational nature of the foreseen
applications, it was felt that limiting segment execu:tion time would not be a serious constraint because
very few segments would approach this limit. (This
has turned out to be the case.) The improvement in
system response due to this doctrine derives not only
from the smaller number of disk references but from
the simpler mechanisms needed to handle the segments.
A second major design decision was to make the
monitor poll the remote consoles, i.e., to accept input
at the system's convenience rather than in response
to interrupts generated by user's consoles ("contention"
mode). Polling is made practical by the existence of
adequate local buffers at the remote consoles. The
principal advantage of this mode is that remote input
*LAboratory Computer ON-line InQuiry
Executive Programs for LACONIQ Time-Shared Retrieval Monitor
can be scheduled, so no dedicated input buffer areas
are required.
All the resources of the system-communication lines,
core storage, use of the CPU, and use of the I/O
channels-are scheduled in one way or another. The
most fundamental scheduler, the work-in-progress
scheduler, calls in both program segments and systems
routines as appropriate and when needed.
The monitor was not primarily designed to facilitate
programming at the user console, although incremental
assemblers or compilers can be added in the form of
applications. The basic criterion was rather to make
it easy for a skillful programmer to prepare an application with which the (usually untrained) user, at his
console, could interact in a language natural for that
application. This monitor might be described as a threelevel system, with the programmer mediating between
the layman-user and the computer, and is a step
toward making the power of the computer more generally accessible.
It is probably obvious, but perhaps worth mentioning that a further requirement on the monitor was
that it should be capable not only of supporting several
terminals processing a given application, but also several different simultaneous applications.
Many of the detailed features of the monitor are
directly related to the IBM 360, and some even to
the configuration of the particular computer system at
hand, which consists of a 32k 360/30 main-frame
with two 2311 disk drives, a 2321 data cell drive, a
tape unit, and multiple remote CRT consoles (IBM
2260 and Sanders 720). The disk drives e~ch store 7.2
million bytes with average access time of 85 msec,
the data cell stores 4.8 million bytes with a maximum
access time of 600 msec. The CRT consoles display,
respectively, 960 and 1024 alphanumeric characters
at 120 characters per sec (line rate). Some hardware
factors which have been important in their influence
on monitor design are the small core storage, the
large peripheral storage, and the local buffers for th~
console displays.
The first version of LACONIQ was operational in
December 1966, supporting three IBM 2260 consoles
and using two disk drives and a data cell. It has
been continually upgraded and at this writing it is
being set up to have a high degree of compatibility
with the IBM Disk Operating System and OS/360.
The changes include exploiting a larger core storage
(64k bytes) and introducing a background capability.
Depending on the size of the background partition
and the application mix it is foreseen that the monitor
will support between six and twelve CRT consoles
with an (approximate) 2-second response time. Sys-
241
tem overhead is estimated at 25 %, and it is believed
that more careful measurement will show this to be
pessimistic.
BIBLIOGRAPHY (From reference 1)
"Programming Real Time Systems," by James Martin, Prentice Hall, 1965, is an excellent general discussion of the problems encountered and dealt with
in the SAGE, Project Mercury, SABRE, PANAM,
New York Stock Exchange, and other systems.
Information on the well-known Project. MAC is
available in Memoranda, Technical Report, and Progress Report form from Project MAC" Massachusetts Institute of Technology, Cambridge, Mass.
Appendix B
TYPICAL SEQUENCE OF EVENTS
Consider that two consoles are currently being used
on-line and both are part-way through some retrieval
process for their respective data files. Core might be
allocated as shown in Figure 6. Assume that there
are presently no outstanding I/O requests for either
console and the segment for console 2 is in execution.
In the hypothetical and simplified sequence of events
that will be described, abbreviated names for the
major system programs and subprograms will be used
as follows:
Central scheduler
-WIPS
Peripheral scheduler - PIOS
Console scheduler
- RIOH
Console control
- LINECT
Peripheral control
PERIF
Input analysis
- INAL
Interrupt programs:
SVC
SVCROU
PINT
Peripheral I/O
Console output
ROP
Console input
RIP
Sequence of events:
1. Segment 2 executes an SVC requesting disk input.
2. SVCROU places the input request in the peripheral I/O queue and transfers to PIOS.
3. PIOS finds the request in the queue and the device free. PIOS calls PERIF.
4. PERIF initiates the input commands for the requests and marks the device busy. PERIF returns
to PIOS which returns to WIPS. m
5. WIPS checks needs for the next console (console
1 in this case) and finds that segment 1 can be
executed. (Segment 1 has presumably been waiting
242
Fall Joint Computer Conference, 1967
Basic Operating System
LACONIQ Program Area
System
Area
(Fixed)
Console N Dedicated Area
Application
Area
(Dynamic)
Scratch Area for Console 2
Figure 6-Typical items in core for two active consoles
6.
7.
8.
9.
for data input from peripheral which has been
completed.)
WIPS gives control to segment 1 which mainipulates its data and requests output to peripheral.
The SVC which segment 1 executed for an output request is interpreted by the appropriate SVC
routine. SVCROU formats the request and places
it in the peripheral queue and transfers to PIOS.
Steps 3 and 4 are repeated for the output request.
WIPS finds that there is nothing to do for either
console and "WAITS." (Background will eventually be performed in this situation.)
The output completion interrupt occurs for segment 1. PIOS is calied to initiate another request,
but none are pending so PINT is called immediately to finish processing the interrupt.
10. PINT posts appropriate bits for later interrogation by WIPS, re-sets indicators for hardware
status, and goes to WIPS.
11. WIPS, which had been "waiting," finds the output
for segment 1 completed and puts segment 1
into execution again (at the point in the segment
immediately following the recently completed output request).
12. An interrupt for completion of the input for segment 2 occurs while segment 1 is in execution.
13. PIOS finds no more requests in the queue and
calls PINT.
14. Status indicators are set by PINT to indicate that
the input for segment 2 is complete. PINT returns
to WIPS.
15. WIPS allows segment 1 to resume execution at
the point interrupted.
16. Segment 1 requests console output. Assume the
segment description for segment 1 requires that
a user decision (console liP) be made before
processing (with another segment) can continue.
17. RIOH finds the line is free, formats the request,
and calls LINECT which executes commands to
put the segment 1 display on the screen. LINECT
returns to WIPS.
18. Segment 2 is put back into execution by WIPS.
19. The user at console 1 types in· his input and hits
the ENTER key. (It is very unrealistic that the
user could respond as rapidly as indicated here,
but the situation is satisfactory for illustration.)
20. An interrupt routine in LINECT posts that input
is waiting in the buffer at console 1 and goes to
WIPS.
21. WIPS calls RIOH which calls LINECT to initiate
commands to pull in the buffer contents. Return
is to WIPS.
22. WIPS puts segment 2 back into execution.
23. The input from console 1 is completed causing an
interrupt.
24. RIP turns on a "console input completed" indicator and returns to WIPS.
25. WIPS calls INAL to process the console input.
26. INAL analyzes the input and determines the next
segment to be executed for console 1. The input
request for this segment is placed in the peripheral
queue by WIPS.
etc.
An executive system for on-line
programming on a small-scale system
by LANCE V. MOBERG
Univac Federal Systems Division
Sperry Rand Corporation
St. Paul, Minnesota
different and, in some cases, completely new approaches to supporting the software and system users.
The true objectives must be viewed from a total
system standpoint. These are best conveyed by the
question asked of Univac at the project's outset.
Can a small-scale computing system be designed, developed and delivered which provides real-time response to a minimum of sixteen independent consoles
manipulating a common, large data base and ensure
complete system integrity?
This meant that priority control, time-sharing, realtime demand operation, and complete program and
data security were among the many obstacles. In addition, the software system must support the illusion of
infinite computer memory. This meant maintaining
complete flexibility such that an operator untrained in
computing could connect and disconnect functional
elements, at will, to solve his problems. This was considered a form of an implicitly programmed system.
After some background information is presented, the
remainder of this paper describes the extent to which
these objectives were met.
INTRODUCTION
The role of Executive Control Programs is increasing
with the number and size of the applications of computers to data processing problems. As problems become more complex and as the computer's external
equipment becomes more numerous, Executive Control
Programs serve as monitors in increasing the efficiency
of the computer as well as its capability of shared utilization of hardware and software. They are, therefore,
an enlightened compromise of hardware and software.
Executive Control Programs can vary from simple
to complex; from use on small system configurations
to large-scale, costly systems. They can be simple,
interrogate-and-jump routines; they can be completely
program-encompassing; or they can fit almost anywhere along the range between these two.
The system described in this paper represents one of
few currently operational data processing complexes
bridging the gap between small, limited budget configurations and very large and costly systems. This gap is
perhaps more apparent in the militarized market than
commercially. This militarized system fills a need for
a small-scale configuration with nearly unlimited capability for solving extremely large problems. Primary
use of the system is for information retrieval and computational assistance. However, the capability for online programming is a most significant feature of the
support software.
System programs developed include the Executive
Control Program, a machine language assembler, CS-l
Compiler, JOVIAL Compiler, and utility routines. This
paper is primarily concerned with describing the Executive Control Program. Software objectives in this
development were in the interests of implementation
rather than towards a technological breakthrough.
Methods employed are largely adaptations of already
known programming systems and techniques. Major
distinction in this effort is that features of many systems were combined into one system resulting in an
operational product. Hardware objectives used slightly
Active hardware components
Central computer of the system. is the UNIVAC
1218; a member of the general-purpose I8-bit word
length family of the Univac Federal Systems Division product line. The computer has a 32K word memory with six microsecond access time and eight input/
output channels. Time-sharing features were incorporated to provide privileged/non-privileged instruction
modes, memory protection, and time accounting clocks.
The mass storage unit is a Data Products Corporation model 5025 Disc file with a total storage capacity
of 400 million bits. The unit consists of sixteen separate
discs each with an independently moving arm containing heads to access eight tracks from one position. Average access time is 125 milliseconds.
System consoles are Raytheon CR T units with
UNIVAC designed control circuitry and internal core
243
244
Fall Joint Computer Conference, 1967
memory. A message at the console consists of a maximum of 34 lines of 80 alphanumeric characters each.
Extensive editing can be performed at the console, by
use of the keyboard special controls, independent of
computer action. The console interfaces with the computer through a buffer unit where each connected console has storage for 39 full/messages. Messages stored
in the buffer are called and returned by means of keys
on the console. In addition, a TO COMPUTER key
and twenty-four program select switches signal the
computer wit~ encoded interrupts. Seventy-four indicators are .also present on each console for program run
lights and message identifiers. Figure 1 shows a typical
system console.
Operational characteristics
Hardware and system software interact to provide
many conveniences for the programmer and user of the
system. The first of these is a two-stage priority control. Programs are executed based first on the importance of their function, and secondly on the console
from which they are requested. There are six levels
with which to specify function importance; console priorities are relative to each other and changeable. Function (or program) priority is a significant factor in controlling program swapping to the disc file.
Areas on the system disc file are identified and referenced by unique, programmer contrived, alphanumeric names. One-third of the file is catalogued in
4096-word segments addressable in 512-word blocks;
the remainder (the data base) is referenced as one area
with a unique alphanumeric name and addressable in
512-word blocks. All disc file references are subjected
to access permissibility tests established from the out-
SSAGE-WAITING
INDICATORS
PROGRAM RUN
INDICATORS
PROGRAM SELECT
SWITCHES
MESSAGE
SELECT
INDICATOR
CURSOR
.~=._.~~~~~~7.,~ POSITIONER
(JOYSTICK)
MESSAGE
SELECT
KEYS
KEy-oPfRATED
INTERL( CK
SWITCH
MESSAGE
CONTROL
KEYS
KEYBOARD
Figure I-System console
E?,ecutive System for On-Line Programming on Small-scale System
side (site manager). Areas are categorized as temporary, permanent, or console storage.
The system consoles are identified by logical unit
assignments. Program-to-operator communications can
be by simple button depression and/or definitive messages.
Library programs can be dynamically linked together in variable sequences to provide an automatic
schedule of programs to execute. Schedule length is
completely variable and has no practical limit. For
example, on-line programming can be scheduled by
linking the Source Language Librarian, language processors, supervisor communication program, and the
worker programs under development. All system language processors could be included in the schedule
(sequence) with the specific processor desired being
selected by a single button depression during execution
of the schedule.
System support software
System software consists of an assembly system, two
(;ompilers, source program library and librarian, object
program library, utility system, and worker programs
operating under control of the Executive Control Program.
All programs operating outside of and under the
control of the executive are termed "operational programs." An operational program may consist of one
program or a sequence of programs, each individually
designed to accomplish a particular job. Therefore, an
operational program is otherwise termed an Operational Sequence of JOB programs. The assembler, compiler, source language librarian, and utility system are
examples of support programs that fall into operational
program classification. Operational programs are constructed by linking together a sequence of JOB programs generated through the assembly or compilation
process. Typical problem solving JOB programs are
mathematical routines, computational-assistance programs, data acquisition algorithms, data reduction and
formating routines, and report generators.
Operational programs are entered into the system in
the following manner: Any operator in the system may,
from any console, enter JOB programs coded in source
language into the source library via the source language
librarian. Source language may be prepared and entered via the console display or punched paper tapes.
Having entered his JOBs in the source library, the operator may then call on a language processor to generate
his programs placing them into the object library. Each
JOB program is assembled or compiled separately.
System control is under complete direction of a site
manager trained in the capabilities and operational
characteristics of the software. Among the duties of
245
this site manager are security control, program library
and data base management, and system utilization
factors such as priorities and execution limits. One of
the consoles in the system is dedicated to these duties
and use by the site manager. Operators may communicate with the site manager by transmitting messages
between their consoles and the Supervisory Console.
With all JOBs to comprise an operational program
in the generated library the operator may then request
the site manager to construct an Operational Sequence.
A set of worker programs, requestable from. the Supervisory Console, aid the site manager in this task. These
worker programs are termed "System Supervisor Functions." In constructing an operational program, the operator supplies the site manager with certain information and he in turn, dictates operating constraints. Information supplied to the site manager is:
1) Identification of JOBs to form the operation program and the sequence in which they are to be
executed,
2) System data areas referenced by each JOB,
3) Hardware facilities required by each JOB, and
4) Console program select button assigned to activate the sequence.
The site manager specifies the priority level at which
the sequence should run and the execution time. Following accumulation of this information, the site manager constructs the Operational Sequence by executing a
"System Supervisor Function" for entering this data.
A second "System Supervisor Function" is then executed to submit authorization to the executive to allow
the new sequence to manipulate its declared system
data. The operational program is now ready for execution by the operator seated at his console.
Program construction
The system language processors produce programs
in page format. Pages are 512 words in length. This
size is the common denominator resulting from the
computer instructions address domain and the special
memory interlace modification which provides program
protection. As a processor generates, instructions are
positioned at the top of a page progressing downward,
while local data and indirect addresses are positioned
in a transfer table located at the .end of the page progressing upward. The processor automatically generates
indirect addressing through the transfer tacle thus producing a free-standing set of instructions requiring no
modification for relocatable loading.
The CS-l and JOVIAL Compilers in addition to
constructing pages optionally generate a program to
execute interpretively. In this way a programmer may
write a program in high-level language with no consideration for the size of the generated program. A
246
Fall Joint Computer Conference, 1967
special routine is automatically generated by the compiler to interpret all memory references external to that
page and call the proper page into memory.
A control block for executive linkage is also produced by the language processors. It is by means of
this control block that the programmer can reference
disc file areas symbolically. Two directives are used by
the programmer to declare data areas; these are PERManent and TEMPorary. Alphanumeric names coded in
the operand positions following the PERM and TEMP
operators are automatically assigned "name-numbers."
The processor records the permanent alphanumeric
data names in the control block to enable the executive to perform access validation when executing the
program. The name-numbers are employed in the
generation of executive calling sequences for PUT and
GET requests for data on the disc file. Hence, the programmer simply writes GET • BOX lA(3) • BUFFER having declared the area by writing PERM • BOX
1A.
Permanent data areas are catalogued in a system
directory by the site manager. Data contained within
these areas are preserved by the executive until removed
by the' site manager. Access controls imposed by him
are honored by the executive to provide additional system integrity. Accessed data or instructions can be validated at load time and/or requested dynamically during the program's execution.
Temporary data areas live only during the execution
of the declaring program. Provisions are included for
passing these areas between jobs of an operational
sequence and for equating their symbolic names. Temporary areas can be obtained by pre-declared requirements satisfied at load time and/or dynamically during
execution.
A third type of data area can also be accessed as
instructed by the console operator. These areas are
obtained and released on request from the operato~
and can be accessed by any program activated at his
console. After generating a program, the language
processor can be instructed to enter the object language into the generated library on the disc file. At this
time the program is assigned a JOB ID which is presented to the operator for future reference.
Operator capabilities
The system's consoles contain, in addition to CRT
and typewriter keyboard, a variety of indicators and
switches. Each console contains a bank of 24 interrupt producing switches (with accompanying code)
and a bank of fifty indicator lights which can be illuminated by the computer. As described in preceding
paragraphs, the site manager assigns program sequences to the console switches. For example, the assem-
bier, compiler, and source language librarian would be
assigned to a console to be used for on-line programming. The dedication of these switches to these functions is recorded in a system table until the site manager rededicates the switches to other functions.
The operator activates program sequences by depressing the appropriate program select switch. A typical sequence of events following a program request is:
1) Executive acknowledges receipt of the request,
loads and initiates the program
2) Program queries the operator with a message
3) Operator types a message and transmits it to the
computer
4) Executive stores the message in the requesting
program
5) Program proceeds as directed.
Other operations available to the operator at his console are:
1) Direct the execution of this program by button
depressions in lieu of or in combination with
messages
2) Turn off indicators
3) Edit messages via character, word line or message errasures, inserts, or copy
4) Store up to 39 messages in auxiliary storage in
the console t. uffer unit
5) Any other function available through assigning
program sequences to select switches.
Operations available for on-line programming would
also include inspect and change proc'edures for program
and data, program dumps, request for mass storage
area, and various data transfers and code conversions.
The exact operation of the console is not relevant to
this paper~ what is .important is the flexibility programmed into the system to allow changing the mode
of any console. An on-line programming mode was
chosen for this discussion. Neither the system or its
consoles nee::! be dedicated to this mode. Modes are
changeable by the site manager at any time with any
desire::! frequency. In examining how this applies to
on-line programming the following areas are of interest.
If a programmer (temporarily terined operator) desires
to compile a "disjointed segment" of a program and
execute the results he may do so by the following operations at his console:
I) Enter the segment source language into the system source library. This can be done by console
typewriter entry, if so desired, or by loading
paper tape.
2) Generate the o:ject program by executing one of
the language processors.
3) Before recording the object program in the object
library, inspect the generation on the CRT. Diagnostic warning codes pinpoint syntactic errors.
Executive System for On-Line Programming on Small-scale System
4) Produce a hard copy, if desired.
5) Correct the program source language and regenerate the object program if necessary. Minor
generation errors could be left for patching at
execution time if desired.
6) Finally, enter the object program into the system
library.
7) Request the site manager to assign this new program to the console.
8) Initiate execution.
Attributes of the executive and language processors
which make this possible are many. Program page construction provides independence from execution area.
The memory area in which the segment executes now
mayor may not be the same as the area for execution
of the segment when it is joined with its parent program. Breakpoints allowing operator (programmer) intervention are possible by program request to the executive. At this point data can be inserted into disc areas
or core memory for processing by the segment. Program execution will not proceed until directed by the
operator. Execution by the executive is made possible
by the Operational Sequence of JOB programs concept.
Since the only definition of JOB is any set of instructions produced by a single run of a language processor,
disjointed segments would be considered JOBs. In fact,
one or mo're disjointed segments could be executed in
combination (sequentially) by constructing an Operational Sequence of them. Communication between segments can be via disc file areas or operator console. '
Naturally, not everything is automatic with this system. Certain attention has to be paid to system philosophies when designing programs. As in any system,
awkwardness can develop if planning was not sufficient.
However, the majority of the problems of on-line programming can be met with this system. This includes
heretofore unmentioned capabilities of debugging aids,
executive diagnostics, and backup library.
Standard supervisory functions provided by the executive for exclusive use by the site manager are enumerated below.
•
•
•
•
•
•
•
•
•
•
Create operational sequence
Enter data names and job list
Abort operational sequence
Designate facility status
Core memory print
Core memory inspect and change
Disc file inspect and change aid
Magnetic tape inspect and change aid
Enter time-of-day and date
System runout
247
Executive control program
The Executive Control Program has four main functions:
• Control of all Input/Output
• Receive, interpret, and process all interrupts
• Maintain communications with each console operator and schedule his requests for execution
• Allocate mass storage and control access to the
unit
The heart of the executive is the switcher. All executive routines relinquish control either directly or indirectly to the switcher, and the switcher in turn routes
control to the appropriate executive routine. This procedure is based upon a periodic scan of six queues of
"outstanding work." A real-time clock is preset with a
value sufficient to interrupt the computer at an optimum interval to cause the switcher to interrogate these
queues. They are, in order of scan:
•
•
•
•
•
•
Unanswered interrupts
Executive lost control points
Executive ready return points
Executive task timing queue
Executive task queue
User programs
If no work is indicated by any of these queues, the
executive idles until a real-time clock or other interrupt occurs.
At the time of an interrupt, the hardware automatically inhibits all further interrupts from disrupting a
routine. The answering routine thus has a chance to
perform necessary housekeeping chores such as saving
register contents and setting up a return point in a
queue before releasing the interrupt inhibit. Since an
interrupt causes routines to be suspended until the
interrupt is processed, the Unanswered Interrupts queue
carries the highest priority. Unanswered interrupts are
interrupts that have been received, but not yet analyzed
because the interrupted coding was not suspendable.
After an interrupt has been processed, the switcher
determines if any other interrupt answering routine was
suspended, and if so, routes control to perform the
analysis.
If the switcher find~ that there are no unanswered
interrupts, the Executive Lost Control Point queue is
checked to determine if interrupts have taken control
from the executive. If so, the necessary registers are
restored and control is returned to where the executive
was last in control. The switcher next checks the Executive Ready Return Point queue. When the executive
uses the special REXEC instruction to call upon another executive routine to perform an executive func-
248
Fall Joint Computer Conference, 1967
tion (such as a disc file read or write), control is relinquished pending completion of the operation. When
the operation is complete, an executive ready return
point' is created. Executive processing is expedited by
returning to ready points before considering other
places to go.
The Executive Task Timing queue is metered by the
real-time clock routine in conjunction with the realtime clock interrupt. Executive tasks which are to be
initiated upon expiration of an interval of real-time are
recorded in this queue. Examples of this are delayed
turn-off of a console indicator or periodic attempts to
execute routines waiting for some other dependent but
separate action. Tasks revealing expired time intervals
are given control at this point. Newly received requests
for executive action are queued in the Executive Task
queue. The last attempt to route control to an executive
routine is accomplished by a dispatcher scan of this
queue. If no work is to be done in the executive, the
dispatcher checks the processing priority table (PPT)
to determine if any job program is to be executed. If so,
control is routed; if not, the executive becomes idle.
Jobs are entered into the PPT table by the request
processor. Console requests for job executions are obtained by the request processor from the Request Table.
An attempt is made to queue the request processor at
each real-time clock interrupt. If the request processor
discovers new jobs to be initiated, it in turn queues the
scheduling processor.
The scheduling processor determines which job(s)
the program loader should load into core from the disc
file. The considerations for scheduling a job are in
descending order:
•
•
•
•
Job priority
Eligibility
Available core
Availability of facilities, if required
If necessary, currently resident jobs are swapped to
make room for higher priority jobs. After a job is
loaded, control is returned to the switcher which in
turn gives the job control.
There are three other major executive routines in the
Executive Control Prorgam:
• Terminate
• Indicate
• Overtime and overdue clock routines
When a job terminates, "terminate" performs housekeeping for the operational sequence of jobs. Terminate may also queue the scheduling processor to initiate
the next job if the terminating job was not the last· one
in the operational sequence.
Indicate, as its name implies, transmits information
from the executive to each console. Job status, system
status, sequence progress and all error conditions are
communicated to the operators.
The overtime clock routine causes a job to be aborted
if the job exceeds its maximum allowable execution
time. If a job is eligible to be loaded (either new or
swapped) but encounters delays, the overdue routine
updates its priority at intervals to ensure that it will
be loaded without excessive delay.
Figure 2 depicts the general processing flow of the
executive.
The operation of the executive is completely based
upon the proper coordination of its various modules
such that they come in and out of control in the
proper sequence to provide the necessary processing.
Modules are constructed to accept tabular information,
from one or more tables, as their sole input and, as
a result of their processing, produce tabular information as their sole output. Control is routed through the
executive in one of two ways: queuing of a module,
or requesting an executive process. Processes are
identified to the Executive Control Coordinator (ECC)
by means of an ECC Flag. A program may request
these services of the executive:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
,.
•
Put data on disc file
Get data from disc file
Query/inform operator
Convey message to program
Read mess,!ge from originating console
Check request completion
Convey button code to program
Read Program Relocation Register (AMR)
Set AMR and transfer control
Set AMR, transfer control and save return ponit
FaC'ility request/release
Console Buffer I/O operations
Printer I/O operations
Magnetic Tape operations
Paper Tape operations
Segment load
Obtain temporary disc file storage area
Validate access to permanent disc file storage area
Validate access to console storage on disc file
Inter-interlace data move
Terminate
The executive contains extensive error checking and
parameter validation procedures to ensure that neither
the operator nor the user program can destroy the
system. For those conditions which are not detectable,
the system is designed to turn their effects back to
the erring program, thus maintaining the integrity of
the executive as well as other user programs.
Executive System for On-Line Programming on Small-scale System
SYSTEM
MESSAGE
OR
PROGRAM
[~~r
249
lep
- - -'2:::=)1"--,
INTERRUPT
ANSWERING
SERVICE
SP
r-"'-"
I
COMPUTER
RTC
BUILD SCHEDULING
TA8LE
I
I
I
SE~UENCE
EXECUTIVE
OPERATIONS
--I=:==L_
..
c=
- -... -..1
REXEC
-,
I
I
TO
DETERMINE JOB
TO RECEIVE
CONTROL
I
JOBS
I
I
I
I
.. -
CO~TROl
EXECUTIVE
SERVICES
..._..tI
-,r-
INITIATE
INPUT IOUTPUT
PROGR ....
REQUESTS
I
I
I
DATA
PATH
CONTROL
PAn'"
-""
Figure 2-Executive control program flow diagram
Use of the magnetic tape, paper tape, and printer
facilities is controlled by peripheral to program assignments. Provisions are incorporated for queuing requests for facilities already in use and aborting of
programs requiring facilities rendered inoperable for
servicing.
Inputj Output
The three main Input/Output modules of the executive are the Input/Output Programs (lOP), Input/
Output Coordinator (lOC), and the Interrupt Control
Programs (lCP). Basically, the lOP consists of handlers
and parameter validation routines, the ICP consists
of interrupt answering and evaluation routines, and
the IOC consists of those routines used for general
housekeeping functions and for routines used to coordinate and interface the lOP and ICP.
Processing in the input! output section is based
upon the simple approach. While some systems may
require more complex algorithms, this approach
proved practical for this system. Of primary considera-
tion in choosing this philosophy is the basic data flow
of the. operational system. Only two devices are in
the primary line of flow; operator console and mass
storage. Considering the transfer rates, data construction, non-linea~ files, and response times, the following simplifying ground rules were established.
1) In determining what action to take next, input/
output should be considered first;
2) Job priority need not be applied to I/O servicing; and
3) Swapping programs with outstanding I/O operations would not be economical.
As requests for input/output operations are received
by the executive, they are automatically queued in
one of the Input/Output Handler Queues. There is a
separate queue for each handler, i.e., for each piece
of peripheral equipment. The length of the queues
are set, based upon the estimated usage of the associated equipment. The queues contain the address
of the parameter packet of the requested operation.
250
Fall Joint Computer Conference, 1967
Input/Output operations are initiated whenever a
channel becomes "not busy." Associated with each
channel is a channel busy flag which is zero if the
channel is free to use and set to the address of parameters of the requesting program if the channel is
busy. At request time, this channel busy flag is examined. If no other requests are queued in the I/O queue
and if the channel busy flag is clear, the request is
initiated, otherwise, the request must work its way up
the queue.
Each time an interrupt is received the Input/Output Active Flag (lOAF) is referenced. This' flag is
used to indicate that status of the entire input/output
section. If upon receiving an interrupt this flag is
clear, immediate interrupt status word evaluation proceeds and control branches to the proper evaluation
routine. If this flag is set, i.e., if the I/O section of
the executive is already busy, the interrupt status
word(s) and a return point are stored into the unanswered interrupt queue. This queue is later scaDIled
at the convenience of the executive, at which time
normal status word recognition and evaluation is
performed.
Programmer requests for input/ output operations
are always accompanied by a parameter packet with
the desired control information. A special flag called
the Executive Control Coordinator Flag (ECC) accompanies each packet and denotes the type of executive action required. The I/O packets themselves are
of the following general form:
The 10RF used in the MWRT executive
form:
of the
I I
A
B
c
D
I IORF
~~--~--~~----------------___ ----J
A
1 I/O Has Not Completed
o
B
I/O Has Completed
1 JOB Program Request
o Executive Request
C
1 Check of request's status received
o
D
Check of request's status not received
Must contain one of the following:
(1) Job program's table index (PPT index)
(2) Executive task number
(3) Address of working storage
The operation code for each function is defined to
be the same for similar operations on the various·
pieces of peripheral equipment. For example, an operation code of 21 means a read operation whether on
the disc file, the magnetic tape or any piece of equipment which might be associated with the Executive
System.
Job control
FOR EXEC. USE
WORD
I
I--
r-
I--
OTHER MORE
SPECIALIZED IN FORMA TION
--
0
OP CODE
--
n
Word zero of the packet is reserved for executive
usage and is referred to as the Input/Output Request
Flag (lORF). As a request is processed, certain vital
housekeeping and control information is placed in the
IORF to enable the executive to maintain proper control over the request. The control information necessary for the executive's performance is:
I)
2)
3)
4)
An
An
An
An
index to a table of vital registers
input/output active indication
input/output completion indication
indication of the source of :'"cquest
The Scheduling Processor determines which job programs to schedule for loading. Considerations, in
order, are:
1)
2)
3)
4)
5)
6)
Priority
New request versus initiated
Eligibility
Shelving (swapping)
Facilities
Sufficient core
A counter is used to determine if the scheduling
processor should be queued. For each new request
that is received the counter is incremented by one.
After a job terminates or is aborted the counter is
incremented by one unless that job was the last in
the sequence. Each time a job is swapped, the counter
is incremented by one. When a job is loaded the counter
is decremented by one. This procedure ensures that
every jo~ will be scheduled to be loaded.
Six levels of program priority are considered by the
Scheduling Processor. They are, in decreasing impor-
Executive System for On-Line Programming on Small-scale System
tance: Emergency, Crash, Priority, Interrupt, Working, and Deferred. In general, the priorities differ only
in the power they have to usurp control. Table 1
summarizes these priorities.
Table 1. Summary of priorities
Emergency Will destroy prevailing programs and preempt facilities to allow immediate execution.
251
es above 2100 8 are interlaced according to a program
modification register which is added to the program
address counter as execution proceeds. The executive
interlaces programs into every eighth memory location
as depicted in Figure 3. Additionally, the memory is
constructed from banks of 4096 words. These two
organization structures interact to form multiple pages
per interlace position with program protection enforced between interlace positions.
Crash
Will pre-empt facilities and cause programs to be swapped to allow execution.
Priority
Second level capable of pre-empting facilities and causing programs to be swapped
to allow execution.
10,0005
Intervenes between job steps of lower
priority sequences.
17,775
17,776
17,777
20,005
20,006
20,007
Interrupt
Working
Normal processing levelof most programs.
Deferred
For infrequent, time-independent executions of the background variety.
Three tables are manipulated by the Scheduling
Processor; Processing Priority Table (PPT), Link
Table (LINKTB), and Processing Priority Link Table
(PPLT). Each serves its own function in the system
to: 1) maintain orderly records of all active requests
(PPT), 2) maintain a. priority ordered structure
(LINKTB), and 3) expedite dispatching of control
amongst the resident programs (PPLT).
After a job is scheduled for loading, the Program
Loader is called upon to perform the necessary tasks
to load a job into core from the disc. A Centralized
Catalog Handler (CCH) is used by the program loader
to obtain the location of and information about the
program in the object program library on the disc
file. All mass storage requirements are processed
(validated) by the CCH by placing assignments into
tables associated with the job. When the loading is
complete, the Scheduling Processor builds an entry in
the PPLT and enters pertinent data into the PPT. The
LINKTB is then scanned for additional jobs to load.
The scheduling processor can choose to swap a
resident job if the job is sufficiently low in priority
or waiting for an operator response or facility request.
The job and its volatile registers and mass storage
assignments are written onto the disc and the ~ore
area is made available for another job. When, the job
attains sufficient priority, the necessary operator response is received, or the facility is assigned, the
swapped job is eligible for reloading.
Program swapping is performed on the basis of
the computer's memory organization. Memory address-
Interlace Positions
JOB.A
10,006
27,775
27 776
27, 777
30,005
30,006
30,007
JOB B
JOB C
JOB D
EXECUTIVE CONTROL PROGRAM AREA
INTERLACE POSITIONS WHICH MAY BE
OCCUPIED BY INDEPENDENT JaRS
PAGES OF INTERLACE POSITION 6
Figure 3-Interlace divisions
Swapping of programs considers memory requirements according to the following algorithm:
1) A job requiring x (x == 1, 2, 3, 4) interlaces
will first swap a resident. job using exactly x
interlaces.
2) If x was 1 and there were no swappable jobs
resident with only one interlace position, a try
at x equal 2 is made, If no job of 2 interlace
positions is found, the job is not considered
further for scheduling on this round.
3) If x was 2, 3, or 4, and no job was found with
matching interlaces, an attempt is made to
acquire the required number of interlaces by
swapping single interlace jobs.
Mass storage allocation and addressing
All programs, including the executive, address the
disc file symbolically via the disc file handler program, Symbolic addressing in this system is implemented in two phases, Alphanumeric names coded by
the programmer are converted to a numeric representation by the language processors. These "name numbers" are then translated by the executive (partially
252
Fall Joint Computer Conference, 1967
at load time and partially at program execution time)
to access the disc file. Four categories of data areas
are provided; 1) permanent system areas, 2) temporary program areas, 3) console assigned areas, and
4) application data base area.
All areas, excepting the data base area, are 4096
words in length addressable in 512 word blocks.
Permanent, temporary, and console areas occupy onethird of the total disc file storage. The data base area
consists of the remaining two-thirds and is also addressable in 512 word blocks.
Permanent system areas are established in a Data
Reference Catalog by the site manager. Read, Write,
or Read and Write access privileges are also specified
for individual JOB programs. These areas remain
assigned until released by the site manager. Temporary program areas are assigned to a program by
the executive when the program executes. Temporary
areas are assigned when a program is loaded (based
upon stated size requirements) or as a result of dynamic program requests to the executive. Similarly, the
areas are released upon program termination or in
response to a program request. Console are'as are
assigned and released by the executive at the request
of an operator. Any programs requested from a particular console have access to console areas assigned
to that console. The data base area is permanently
allocated to a physically contiguous area on the disc
file.
All requests to access the disc file are programmed
through the use of two I/O statements as declared
through the use of two declarative statements. For
example, the statements to move temporary data to
a permanent area are as fonows:
[OPERATOR] • [OPERAND 1] •••
[OPERAND N]
ERM • BOX • BOX
C
J
declaratives
TEMP • LOT • LOT 2
~
ET
~Block
• LOT (7) •
No.
BUFFE~
I/O calls
PUT • BUFFER • BOX (0)
Three significant aspects of this method are: 1)
lengthy request parameter packets carrying unwieldy
alphanumeric names are not necessary; 2) reques't
validation and processing by the executive is expedient; and 3) data can be physically relocated. on the
disc file without any changes (or regeneration) to
the using programs. The first two aspects are made
possible through an indexing scheme employing the
name-number. The relocation capability is made
possible because the disc file is "mapped" in 4096
segments. Each segment (area) is fixed to a physical
(absolute) disc address and are mutually independent.
The price paid for this flexibility is the fixed 4096
word length of areas and the responsibility for proper
coordination and control delegated to the site manager. However, these considerations may, as in this
application, be worth the price where data standardization is possible and strong control by a human is desirable.·
System catalogs
Several catalogs are employed by the executive to
inventory mass storage allocations and object program library. Continuing the themes of program
modularity and system integrity, a single program
was designed to implement the catalog philosophies.
The Centralized Catalog Handler (CCH) has exclusive control over the system catalogs and complete
responsibility for their creation and maintenance. The
CCH provides the following services:
1) Supplies the program loader with information
stating the whereabouts and size of a program
to load
2) Supplies information to the source language
librarian and language processors stating the
whereabouts of a program's source language
3) Supplies information to the source language librarian and language processors stating where to
store a program's source language or generated
language
4) Catalogs the location of program source language, generated language, permanent data, and
console data.
5) Validates access to permanent data and console
data and provides linkage for proper access
6) Obtains temporary storage and provides linkage
for access
7) Ensures the integrity of the system disc file
storage through proper maintenance of the catalogs and tables.
Figure 4 illustrates catalog formats.
Peripheral and core allocation
Allocation of peripherals in this system concerns
only three devices; two magnetic tape units and one
printer. It is sufficient to summarize the functional
provisions associated with the allocation process as
follows:
1) To avoid waste of time in loading a program,
only to find that during execution the required
peripheral is inoperable, facility requirements
can be stated at the time an operational sequence is constructed. At the time the sequence
Executive System for On-Line Programming on Small-scale System
I
.... '11
I
PROCRAM_
:
f--PoINTER
-
-
~
-i SPAcr=TOMAP-ro~
,
~iNTER TO~;-FOR a.- r - ""
:
r- ~
-..
==~
.
•
_._ . _ _PFQGR""" ENTRY ~~-
-
---
..
~~
~
..
==-""'r
- :
_~-
253
AUJLUTE
'--?!777 nil
DISC
IN-USE
_II
~............ ~
AIlOR ESSES
INDICATORS
..
ClllSSI1EFEJIBIC(CAT...... 111II
PERM ADDRESSES
! !
__. . LJ
I"""""
t
~
1777 ' - -_ _---L_ _ _....J
CROSS REFE RENCED JOB ID
INCREMENT NEXT AVAILABLE PERM LOCATION
~"'.If
I....a..
---------~
·rlnnm:~~,.-~
ITEM NUMBER IS JOB 10
INCREMEN~~V=-:~P LOCATION
~
~
TEMP
TEMP
TEMP
TEMP
INDICA TOR FORMAT
17
I.
I I
IF
7
I I I I I I
I
0
I" IBLlodK
~SEtD
I
"
t
ADDRESS
MAP INC
ADDRESS
MAP INC
SII 0 ' - -_ _ _ _ _ _ _ _---J
F - USE OF AREA
o
~
AN
- - - NAME
_:_
_~~A_ _
I
---
J
~-~-~-~~J -~~
6
R';
PO!~[~~!l>~_D~MAP~----=_""'~
F, 0
F' I
F' 2
F' 3
F..
PERMANENT AREA
SOURCE LANGUAGE
GENERATED LANGUAGE
CONSOLE AREA
TEMPORARY AREA
...
1
Il
II
PERM ADDRESSES
11
13
14
I
I~
:
16_
11
D
11
71
~
'--
1
I
t-S~EC~TI=OtN:-::O-;:-;FP::;CER;:I-;·M--:-:-:'N-=CO=RE~
.;.I---_T~lEMP=----:.::ADD:::.:RT1ES:::::SEc:..s--I
:~ I----:S=EC=TION~OF::-:T=EMP=--=,N-=CO=REo--l
141
SYMBOLIC ADDRESS OF PT
RWan:
o 0 READ AND WRITE ALLOWED
o 1 R[ADONLY
1 0
WRITE ONLY
ITEMS
ORGANIZED
ALPHAB£TICALLY
DATlI1EFEJlBlC(CAT...... 111II
Figure 4-Symbolic addressing catalogs
is requested the executive will discover the
facility's inoperable status and inform the operator. Programs can be designed to divert data
to the disc file for later dumping by system
utility routines, however the executive does not
automatically perform this function. The operating status' of peripherals is designated by the
site manager through use of a supervisory function at his console.
2) Requests to obtain or release peripherals are
submitted under program execution. Any JOB
in a sequence can submit these requests. Request can specify any combination of the three
assignable peripherals.
3) Facilities are optionally assignable for the requesting JOB program only, or for the remainder of the Operational Sequence. If not
released by program request, the executive will
automatically release them upon JOB or sequence termination as applicable.
Core memory allocation is largely a function of
computer memory organization. When an operational
sequence is constructed, program size requirements
are specified in terms of interlace positions (seven 512
word pages per interlace position) for each JOB.
Since memory/program protection is enforced between interlace positions, suballocations to different
programs are not permitted. JOB programs may occupy a maximum of four interlace positions of resident. program. Program segments may be loaded ,from
the object library by call to the executive.' Also, for
extremely large programs, a special interpretive mode
of operation can be selected at compile time. This mode
of operation provides for automatic "ping-ponging"
of program and data pages between core memory and
disc storage as required during execution.
The executive itself employs a versatile method for
page allocation which allows for "shuffling" of pages
during debugging and facilitates executive overlays.
The method is essentially a table of the executive tasks
and a map of the memory divided into pages. The
following information is recorded about each executive task:
1) resident or transient indicator
254
2)
3)
4)
5)
6)
7)
Fall Joint Computer Conference, 1967
busy or not busy indicator
entry point
interlace position
page position within interlace
size
symbolic address of task on disc file
This information is indexed by task number. Additionally, for each page of memory an occupied or unoccupied indicator is maintained.
Executive Task Parameter Table
TN 1
7
I
6
I
5
I
4
3
I I
2
1
2
3
!
/
~
N
~
Note: Table construction is parallel (horizontal); numbers refer
to preceding discussion points
SUMMARY
In reviewing this effort, one can identify a few
major design features which greatly simplified development. Such things as constructing modules to
both process and produce tabular data considerably
aided the debugging process. This was largely due
to the resulting module independence which made it
possible to check out isolated modules. Table designs
play very important roles in at least two ways; the
obvious concern of all designers about the effort required to manipulate frequently accessed data, and
the grouping of data according to the way the system
flows. The latter means that modules manipulate a
minimum number of tables. Also, at any point in the
cycling of the system it is possible to obtain pertinent
data on any given situation with a minimum of effort.
Illustrating this point, the Processing Priority Table
proved invaluable in assessing the status of the system at the time of a malfunction (since the system
had almost invariably cycled "far down the road").
Several decisions in the processing of input/output
simplified the system greatly. These include first-in,
first-out queuing, minimal automatic recovery, and
prohibiting swapping of programs with active input/
output.
Since systems vary greatly in equipment types and
capabilities and also in application, designs which may
be optimum in one system may not be (and usually
aren't) good for another system. Many trade-offs were
made in designing this specific system. The areas of
decision would have to be reanalyzed if this system
actively used magnetic tape or card equipment or
utilized different consoles. Another major design factor
was the amount of human influence desired on the
system operation. In this system, the design appears
satisfactory-based upon observance of limited operation. The programming required to implement the
application is not yet complete; therefore, data on
sustained operation in executing actual application
problems is not available. However, in its present stage
the system has proved to be effective and flexible for
developing programs on-line. Consoles can be rapidly
changed between a program development mode and
a problem solving mode. Total system integrity is
ensured as governed by the authority vested in the
site manager. Variations in the approach to solving
a problem can be introduced, tested, and approved,
all on-line, by means of the operational sequence
technique of scheduling. Simple, relatively non-exotic
methods were employed in the interests of achieving
an implementation deadline.
ACKNOWLEDGMENTS
This work was sponsored by the Air Force (Rome
Air Development Center) as part of a research and
development contract .with Univac. Specifically,
Messrs. L. Odell and J. McLean contributed significantly to the system design.
Mass storage revisited
by ALBERT S. HOAGLAND
IBM Watson Research Center
Yorktown Heights, New York
INTRODUCTION
Mass Storage as a functional need in computer systems is continually increasing in importance with the
growing trend to interactive terminal-oriented systems, serving as peripheral or external on-line memory
for storing a systems data base and resident programming systems. The associated capacity, plus the
ever expanding magnitude of such data, far exceeds
the range where "electronic" memory is economically
competitive. Included in the product category defined
as mass storage are drum, disk, tape, card, strip, and
chip recording structures. Direct access storage is
becoming a standard feature of computer systems,
with much the same type of distinctiveness as the
CPU and main memory have achieved.
Five years ago I made a "tour d'horizon" of mass
storage for the 50th Anniversary Issue of the Proceedings of the IRE.l It is of interest to preface this
review by certain observations on the situation as seen
then contrasted with now.
I felt then and still feel that magnetic recording will
remain the technological base for mass storage for the
foreseeable future. While this prediction has held true,
the amount of exploratory activity in so-called beam
addressable storage (optical and electron beam recording) has greatly increased. This current review
(circa 1967) reflects a large relative increase in the
material devoted to new technological approaches
to mass storage.
Five years ago the highest storage density in a
commercial file was 25,000 bits per square inch,
while today this figure is approximately 250,000 bits
per square inch - an order of magnitude increase
(giving two orders of magnitude improvement 9ver the
last decade). However, at that time I felt eventually
magnetic recording storage densities in excess of 106
bits per square inch would be realized and will restate
the same conviction, reinforced by the advances
already achieved.
An unanticipated factor which emerged to play a
major role in the accelerating importance of develop-
ment activity in mass storage is the challenge posed
by programming systems residence. The complexity
and size of operating systems is a fact of life that was
little appreciated in 1962. The storage needs here
serve to emphasize fixed head files with their capacityaccess trade-off favoring short access time.
The success of the replaceable disk pack file has
been remarkable and placed this device in such a predominant position that the long .range role of striptype storage structures has not emerged nearly as
clearly as was expected.
In the last decade significant advances have also
been made in tape drive performance as well as in the
elegance of their design for reliability and serviceability. However, we are concerned here with the
"image" of mass storage and these product advances
do not essentially change the perspective of tape
devices in an ov\;rall sense.
Overall, in the last five years, technology appears
to have advanced as fast as suggested while the systems organization and use of mass storage hierarchies
retains almost as much fertile ground for sophisticated
design and application as appeared then.
Functional considerations
Computers that manipulate data are primarily
limited by the number and size of files that can be
made readily accessible for processing. Further, mass
storage devices are now called on to fulfill important
systems functions. Random (or direct) access units
are used in compiling and assembling programs where
their ability to reach large directories and subroutines
rapidly is necessary for responsive program-preparation and execution. For time sharing, programs and
data of many users can be stored on-line with a mass
storage, to be run as requested in accord with some
"optimum" allocation of facilities.
Capacity, access time, "latency," data transfer
rate, and cost per bit are the basic performance characteristics of mass storage devices. Each mass storage
255
256
Fall Joint Computer Conference, 1967
unit has its own particular attributes, and many applications require that several different devices, or a
hierarchy of devices, be connected within the same
computer system. The short access times and high
data rates of fixed head drums or disks save valuable
processor and internal memory time when it is necessary to swap programs, as in time-sharing. However,
the higher cost per bit of these devices generally
makes them too expensive for file storage, and other
structures of higher capacity (and longer access time)
but lower cost per bit are used. Cost of storage (in
superficial terms) in inversely related to the number of
bits stored per independent read/write transducer.
Systems-derived performance factors such as
throughput depend not only on the mass storage specifications but also on indexing procedures, memory
allocation and chaining provisions, file activity
(ratio of records actually processed to total), provisions for queuing and ordering of access requests,
checking techniques, etc. Thus, the associated control
logic is an integral facet of any mass storage subsystem.
Technological considerations
The continuing need for high capacity storage has
required the intensive exploitation of recording technologies for the economic implementation of mass
storage. Thus, storage units involve the physical integration of recording media, transducers, precision
mechanics, servo systems, and electronic encoding
and decoding techniques to achieve a meaningful set
of capacity access time tradeoffs.
Access to any data location is provided by relative
motion between the storage surface and an associated
transducer able to record signals on and sense the
state of the storage medium. A single transducer may
service many data "tracks" by a positioning mechanism operating normal to the direction of scanning.
The recording density (bits per square inch) is
principally a function of the registration tolerances
(three-dimensional) that can be realized between the
storage film and the coupling transducer. The access
time variability to memory locations arising from the
requisite motion necessary to scan large areas, makes
the data organization of a mass store a key factor to
effective systems utilization.
The greater the bit storage density (and hence the
number of bits associated with a given read/write
transducer) the lower the cost/bit and, correspondingly, the shorter the average access time for any given
capacity. The average random-access time will range
from milliseconds to seconds because mechanical
,motion is required for accessing masses of data, i.e.,
the larger the memory capacity, the greater the re-
quired surface area that must be accessible to a read/
write station.
Although it is only in recent years that magnetic
recording has come into wide general use, its invention by the Danish engineer, Valdemar Poulsen, dates
back to 1898. The paramount functional advantage of
magnetic recording surfaces is their unlimited reusability.· This property permits the direct modification of stored information. Additional advantages
of magnetic recording for mass storage of data over
other potential storage film media are: the simplicity
of recording transducer "(a magnetic head); the flexibility in mechanical st~ucture possible (and hence,
choice of performan~e specifications) due to the
ability to place the storage film on almost any supporting surface in conjunction with ease of mounting
a magnetic head; the hig'h bit storage densities and
read-write transfer rates obtainable with magnetic
recording; and great ruggedness with respect to
handling and environmental conditions. The further
features of replaceability and off-line shelf storage
(e.g., tape reels and disk packs) make this mass storage
technology extremely attractive and very economical.
Magnetic recording represents the integration of
several basic engineering fields and has been generally
characterized by rapid progress achieved by evolutionary advances rather than dramatic innovations.
The one "breakthrough" that can be, identified with
the computer field is the "air-floated" head. Otherwise, advances in the magnetic recording art have
largely emanated from increasingly higher precision
and quality in components.
Historical g~owth and present status
The original work which ushered in mass data
storage was firmly under way by 1947. This activity
was associated and concurrent with the explosive
"take-off' of the digital computer field at that time.
Early work was oriented to the needs of the scientific
computer market. The principal mass memory device
was the magnetic tape unit, to provide both an auxiliary "back-up" storage for main memory and terminal
buffering (data rate "matching" between input/output equipment and the central processor) in largescale scientific systems. The later emergence of commercial data processing brought with it, a wider
variety of functional usages and mass storage hardware. Magnetic drum memory development for small
and medium speed processors served to significantly
add to the technological base of digital magnetic
recording.
Commercial or business data processing, as it was
evolving as a main facet of activity in the electronic
Mass Storage Revisited
computer field in the early 1950's, gave a tremendous
impetus to mass storage development and had a major
impact on its direction. File storage for records
maintenance was the central requirement.
Magnetic tape was first exploited for mass records
storage. The only practical way to use tape is to address by record content. In updating a file, for example, the master and transaction tape reels are
serially read (information is arranged and maintained
in ordered sequence) and a "new" tape is created, on
another transport, with the unmodified as well as the
altered records being transferred. It was easy to make
insertions and deletions in this process as well as to
handle variable length records, as physical sections of
tape have no specific identify; although to modify or
insert a single record, the entire tape must be rewritten. A tape reel is relatively cheap and therefore
low-cost, off-line, archival storage is attractive. For
low file activity, tape devices are very inefficient, due
to the constraint of sequential access. Further,
effective file inquiry operations are not possible.
The character of much business data processing indicated the need for an entirely different type of mass
storage. The desirability of storing large volumes of
information with any record available rapidly gave
stimulus to the development of a mass random access
memory.
The air bearing supported head (using an air cushion
to control head-to-surface spacing) was the innovation
which, associated with the above memory concept,
brought about this entirely new type of mass storage.
An air-bearing head can follow considerable surface
fluctuation - up to 100 times the spacing. Since the
readback amplitude wavelength dependence on separation is given by e- 21Td/ .\ (where d = separation and
A = wavelength) high recording densities would be impractical without such a method of maintaining close
and accurate spacing. By this air-bearing spacing
technique, it was possible to develop a high-capacity
rotating disk array since a head could closely follow
the appreciable runout of large disks.
The first version (the RAMAC, announced in 1956)
could store five million characters with an access time
to any record of less than a second, having one head
mechanism servicing the entire disk array. Secondary
technical features of note were the use of self-clocking
and a wide erase narrow read-write head unit. These
design approaches, combined with the use of an airsupported head, provided techniques that compensate
for the head-to-track registration tolerances of such
a gross mechanical structure, and thus permitted the
high track density and high bit density necessary for
large capacity.
Random access memory involves addressing by
physical location to a single record or a particular
257
block of records (one track), which is then scanned.
Any record can be read, written or modified without
affecting any other record. The "set of keys" (record
identifiers) of a file- will, in general, bear no direct
relation to the -closed set of machine addresses.
Various randomizing techniques (key transformations)
are used to convert scattered keys covering an extensive range to a dense and relatively uniform distribution of numbers to obtain automatic addressing
capabilities.
Initially pressurized air was fed into the spacing gap
to maintain separation. Around 1960 a significant advance was achieved as self-lubricating air bearings
came into general use on both disks and drums,
bringing great simplicity and cost advantages, and in
particular making head-per-surface disk arrays
feasible.
Many approaches to chip, or strip, or card type mass
storage devices have been undertaken over the last
decade and NCR has been the leader with their
CRAM.2.3 However, the simplicity of rotational
motion over card shuffling has favored disks, and no
strip-type storage structure has emerged as a clearly
identifiable industry symbol. Indications are that such
devices must be complementary to disk storage and
it is still premature to detail such configurations in
the context of their evolutionary significance.
The next major innovation in mass storage (196263) was the replaceable disk pack concept, which
emerged as a practical alternative with the rapid
progress achieved in storage density - from 2000 bits
per square inch (1956) to 50,000 bits per square
inch (1962), permitting adequate capacity to be stored
on a few small disks. 4
Three discernible themes have emerged in the area
of mass storage.
1. The replaceable disk pack file is clearly appearing as the principal mass storage structure characterizing third generating computer systems. The
disk pack file appears well on its way to becoming as
ubiquitous as were tape drives on the computer systems of the late 1950's. With the major trend toward
high performance disk files, there is concurrently
much less forward momentum in magnetic "strip"
storage as a competitive alternative, contrary to some
earlier projections.
2. A second aspect is the vastly increased discussion and presentation of advanced work in new
technologies that may become significant for computer
storage.
3. Fixed head files, either drum or disk, have entered a stage of greatly renewed interest due to the
demands now being generated for high capacity
storage with fast access to store extremely large and
258
Fall Joint Computer Conference, 1967
sophisticated programming systems as well as meet
the data and program swapping needs of time-sharing.
The disk pack cluster demonstrated another answer
to very large on-line storage and could become a principal approach to serving requirements generally met
today by large disk array files. For example, the IBM
2314 consists of eight disk packs (plus one spare)
each with a completely independent access mechanism, all in one assembly. With this concept, by overlapping accesses, the mean access time can go down
with increasing capacity at a relatively fixed cost per
bit. The performance region of several hundred
million bytes of data with access in milliseconds is a
key to many on-line "data bank" type information
systems and the appeal of such facilities spurs the
rapid trend to direct access file-oriented systems.
The "state of the art" magnetic recording density
for production disk files (1966) moved to the region
of 250,000 bits per square inch (2500 bpi by 100 tpi),
a factor of 125 greater than the density of the first
commercial disk file announced only a decade ago.
Further, major advances in density and thereby capacity are clearly indicated based on many current
laboratory investigations in the range of 10,000 bits
per inch. Techniques that may make equivalent strides
in reducing access time are still undefined. The trend
to large on-line data banks will undoubtedly accentuate reliability considerations far beyond traditional
experience - a question with electromechanical devices of constantly growing concern.
New beam addressable concepts for storage are also
being described periodically that may be promising
for the future. Numerous groups revealed activities
looking towards developing reversible magneto-optic
storage techniques. Writing is accomplished by
thermal heating (e.g., with a laser beam) in the presence of a magnetic field and reading by sensing the
rotation (caused by the magnetic state of the film) of
a polarized beam of light.
Among other mass storage approaches recently
presented were: a trillion bit storage system for the
Livermore AEC Laboratory based on electron beam
recording on photographic film - with .a flying spot
scanner for reading; an electron beam multi aperture
recording structure; several concepts using holography as a means for very high density optical data
storage, a recording scheme which stores information
in a plastic film with a laser by "drilling" holes (whose
presence or absence can be optically sensed), as well
as variants on these methods. These latter schemes do
not allow direct updating of recorded information.
Most of these development activities are in a very
preliminary stage and one would not anticipate commercial products that capitalize on such technologies
to appear for several years. Nevertheless, these
releases do dramatize a recognition of the growing
importance of achieving higher performance storage
products to meet the growing system demands posed
by the trend towards on-line multiuser systems
oriented to remote terminals.
Future trends
Each user wants all data immediately available to
him. The appetite for more mass storage capacity
with high speed access appears as insatiable as the
appetite for more computer speed.
A major problem in file-centered systems is determining the proper balance of mass storage devices.
A hierarchy of storage modules (of varied performance parameters) closely integrated can best optimize overall systems performance, recognizing that
cost trends to be inversely related to access time for a
given capacity. We need to better understand the flow
of data and develop design guidelines here, recognizing that the access "gap" from electronic memory
through electromechanical storage devices will cover a
relative access speed differential of 103 to 105 • Mass
storage control logic is now beginning to extend to
the functional ability to automatically arrange records
within the hierarchy of memory/storage according
to their activity, significantly improving access utilization. Much sophisticated systems development
work is still necessary if we are to fully exploit our
technology capability.
A 'major advance in hardware reliability is urgently
needed if the full potential of mass storage devices
is to be realized. Capacity-access time improvements
must be at the price of higher reliability because of
the nature of on-line systems.
In this regard the mechanisms of strip-type mass
storage devices are considerably more complex than
those of disk files or drums (the proper surface must
be selected at random from many hundreds, accelerated, guided repeatedly past a read/write station,
decelerated, and returned to the file), and there is
consequently a higher probability of device malfunction.
Beam addressable storage technology
A read-only photographic rotating disk memory was
developed several years ago to serve as a dictionary
for langauge translation. 5 The model stored 30 million
bits (approximately 1500 bpi X 1500 tpi) with an access time of about 50 milliseconds. Optical sensing
using a CRT flying spot scanner permitted "servo
tracking" with extreme sensitivity, allowing a much
Mass Storage Revisited
closer balance to be obtained between bit and track
densities than in magnetic recording.
A number of new electron beam and optical techniques have since been proposed which eliminate the
need for mechanical motion for access, at least within
a large block of information. These schemes have an
appeal since beam addressable techniques have the
unique capability for microsecond access to densely
recorded information within the field of view of the
beam. An electron beam can readily be deflected and
modulated. A laser provides a light source whose output can be focused to a small size at high power densities. There is confidence that means for modulating
and deflecting laser beams will be found that are
practical.
Electron beam spot sizes less than one micron in
diameter have permitted writing (in a vacuum) at a
density of. several million bits per square inch (approximately 2000 bits/in. by 2000 tracks/in.) on silver
film. Readback must be done optically at a separate
station after film processing. Future improvements
may give even smaller beam sizes over a wider field
of view. However, as in magnetic recording, we can
now write information at much higher densities than
we can effectively readback because we encounter
still unconquered signal detection problems.
Optical techniques offer greater possibilities for
high speed parallel data flow as well as the prospect
of "distributed" bit storage (e.g., by holography)
where the effects of media defects and registration
misalignment at high densities may be minimized. A
hologram is created from the bit pattern and recorded.
The original image is reconstructed for readout by
photodetectors. The greater possibilities of developing
suitable "reversible" optical media (e.g., magnetooptical films) provide a further incentive for pursuing
explora.tory studies in optical recording.
Interest in photographic film stems exclusively
from the potential it offers for high storage density.
Photographic emulsions, which can be written with
either light or high-energy electrons, are capable of
resolutions of the order of 100 million spots per square
inch. High speed recording is possible at a reasonable
power level. But silver film is not reusable and a long
delay occurs between the writing of information and
its availability for write verify or reading. A significant capacity/cost advantage must be achieved in a
read-only type store to justify the acceptance of the
systems performance limitations on updating, posting,
and immediate write-checking.
Organic photochromic materials fatigue with use
and are relatively slow. Thermoplastic type media
(which can be recorded upon by an electron beam)
while reversible, involve a distinct developing phase,
259
and the "deformation" storage mechanism limits
resolution.
There are severe problems in locatinr and tracking
information stored at very high density. Servotechniques (also being pursued fo~ higher track
density in magnetic recording) based upon trackseeking principles are essential for bf'am scanning
approaches.
Magnetic recording technology
Magnetic he'ad design skills have advanced to a
point where the principal concerns are to evolve batch
fabrication techniques that will provide precision
assemblies at a much lower cost. Magnetic heads
can yield in excess of 10,000 cycles per inch resolution with frequency bandwidths extending considerably beyond ten megacycles.
No physical phenomenon for magnetic recording
appears competitive with the simplicity and flexibility of the conventional magnetic head. Rather, the
next major state of progress in the transducer area will
be automated head fabrication (rather than watchmaker-like assembly), resulting in dramatic cost
reductions. Such a breakthrm,<-.:h would have an impact upon the hardware composition of mass storage
mt?chanisms, by making it economical to radically
increase the overall ratio of heads to tracks.
The mainstream effort in magnetic surface work is
to achieve higher quality, thinner recording surfaces.
(Magnetic films in use today are oxide coatings formed
from a dispersion of either Fe304 or 'Y - Fe 2 0 3 in an
organic binder, and Co-Ni platings.) Thinner magnetic recording films are indispensable for higher
resolution whenever "bulk" erasure is not feasible
and in any event must be correspondingly higher in
quality (uniformity, finish, etc).
Reduced head-to-surface spacings (from approximately 100 /-Linches today down to approximately
25 JLinches) will bring about a further large increase
in "noncontact" bit uensity. Track seeking and following servo access techniques, which can circumvent
the track density limitations imposed by the build-up
of cascaded mechanir.'ll dimension tolerances, will be
applied to effect significant increases in track density.
Thus, recording mechanics still offer considerabie
room for further advances in storage density.
Improvements in the speed of head positioning
actuators appear possible. However, progress in this
area is not rapid and even a factor of two in speed will
be difficult to achieve. Rather, if proposed batch
fabrication processes can be successfully applied to
achieve a drastic reduction in the cost of magnetic
heads, and LSI (large-scale integration) enables a
260
Fall Joint Computer Conference, 1967
corresponding decrease in the cost of head switching
and read/write electronics, there will be a substantial
increase in heads per file module, minimizing the
access dependence on head positioning.
Recording methodology is as yet an inadequately
explored means to further upgrade storage density.
Since the advent of digital magnetic recording for
mass data storage, the primary avenue taken to increase density and thus performance has been
through improved recording mechanics. This work
emphasizes improving the "resolution" of a recording
system and is approaching basic physical limitations.
A relatively untapped potential exists for increasing
magnetic recording density by the application of more
sophisticated communication concepts to the encoding
and decoding of the information to be stored.
Recent communications work exploiting adaptive
equalization techniques and advanced coding theory
has successfully demonstrated dramatic increases in
data rates on transmission lines. In a similar vein the
use of advanced communications techniques for the
magnetic recording "channel" may yield significant
gains in bit density relative to pulse width.
The calculated density limit based on a typical pulse
response with standard recording techniques under
ideal conditions is extremely high. However (even
on paper), a large reduction in this potential figure
results from a simple consideration of variability between magnetic heads, tolerances on magnetic
coating thickness, radial variations in spacing and
speed (with disks), head-to-track registration stability,
surface speed fluctuations, etc. In addition we must
deal with "noise" sources, such as surface imperfections, etc. All these factors must be accounted for
in current file systems, which generally are designed
around a single read/write channel serving a multiplicity of positionable transducers. Thus the actual
operational density falls far short of that projected
based only on a typical pulse waveform.
If adaptive techniques and advanced coding
methods permit us to compensate for a number of
these factors and operate anywhere near the "theoretical" limit of an idealized magnetic recording
channel, the gain (through electronic rather than
"mechanical" means) realized could be very significant.
Despite the bright projections into the near future
for magnetic recording (the next generation of magnetic recording data storage devices may consolidate
around 5000 bits/in. and 200 tracks/in.) the outlook
for this recording process in the next ten years is not
nearly so reassuring because it does not seem to lead
as far as we would like to go.
At the present time there is no approach to mass
data storage that could obviate the use of physical
motion, using a continuous recording medium and
transducer. While a completely electronic mass data
store is an obvious goal, such memories seem possible
only on the low capacity, high-speed side of mass
storage (now filled by drums and disks with fixed
heads).
There are substantial reasons to believe magnetic
recording will undergo another decade of progress
comparable to the past one, although there is something in man that rebels against the mechanical
shuffling of data to recall information. We want
instant memory and we desire this capability in the
computers that we use.
For the foreseeable future, however, it is clear that
mass storage based on magnetic recording has a vital
and increasingly important role in information processing.
REFERENCES
2
3
4
5
A S HOAGLAND
Mass storage
Proc IRE 50 1087 1962
A F SHUGART YU TONG
IBM 2321 data cell drive
Proc SJCC Spartan Books Washington DC vol 28 p 33 1966
L BLOOM I PARDO W KENTING E MAYNE
Card random access memory (CRAM): functions and use
Proc EJCC Washington DC 1961 p 147
J D CAROTHERS R K BRUNNER J L DAWSON
M 0 HALFHILL R E KUBEC
A new high density recording system: the IBM 131 I disk
storage drive with interchangeable disk packs
Proc FJCC Spartan Books Las Vegas Nevada 1963 p 327
G W KING G W BROWN L N RIDENOUR
Photographic techniques for information storage
ProC'"I RE 41 1421 1953
BIBLIOGRAPHY
T H BONN
Mass storage: a broad review
Proc IEEE 54 1861 1966
W W CARVER
Comparing storage methods
Electronic Industries 21 120 1962
J S CRAVEN
A review of electromechanical mass storage
Datamation 12 22 1966
L C HOBBS
Review and survey of mass memories
Proc FJCC Spartan Books Washington DC p 195 1963
W W PETERSON
Addressing for random-access storage
IBMJ Res and Dev 1 1301957
C B POLAND
Advanced concepts ofutilization of mass storage
Proc I FlP Spartan Books Washington DC p 249 1965
High-speed thermal printing
by RICHARD D. JOYCE
National Cash Register Company
Dayton, Ohio
and
STANLEY HOMA, JR.
u. S. Army Electronics Command
Fort Monmouth, New Jersey
• Reliability-Inherent high reliability due to the
absence of moving parts.
• Low RFI-The absence of high voltages and solenoids allows even the rigid requirements of FEDSTD-222 to be met.
• Silent-The printing process itself is completely
quiet; the only sound is that of moving the paper.
• Low power-Due to high efficiency of direct electrical to thermal energy conversion.
• Speed-Absence of moving parts and their associated inertias allows high speed operation.
• Clean-No inks, powders, or fixing actions are
required.
• Multiple copies-Most non-impact printers do not
have this capability.
INTRODUCTION
Thermal Printing is a unique new concept in non-impact
printing, whereby electrical signals are directly converted to heat to produce a printed output. This paper
covers a program to build an advanced development
model of a High-Speed Thermal Teleprinter, utilizing
the Thermal Printing technique, for the U. S. Army
Electronics Command. The teleprinter, which prints at
240 characters per second, was the result of the development.
History
The concept of Thermal Printing was developed to
meet a requirement for a low-cost, quiet, high-speed
computer print out device. At the time that the contract was awarded to NCR (June 1964), however, the
most advancecLThermal Printer was a keyboard operated, strip px:inter, which had a maximum operating
speed of 15;.Gharacters per second, and made only a
single copy .. '
Viewed against this background, a 2 year program
to develop a Teleprinter which printed across a full
page at 60, 120, and 240 characters per second and
made from three to six copies certainly appeared to be
a very energetic undertaking. However, from the Government's point of view, the features of thermal printing made the potential gains commensurate with the
risks.
Features
0/ thermal printing
In addition to being non-impact, Thermal Printing
has the following salient features which make it attractive for both military and industrial applications:
Thermal technology
To achieve Thermal Printing, two novel components
are utilized. The first, a print head, is an array of resistors selectively heated electrically to generate a
thermal image. The second is a thermal sensitive paper
which is held in contact with the print head to provide
a printed record of the thermal image.
Numerous approaches have been tried in fabricating
print heads, and several promising new approaches 1
are still being developed. However, the print head configuration described herein has been used in all Thermal Printers built to date.
Each individual printing element consists of a tin
oxide resistor deposited on the edge of a ceramic substrate (Figure 1a). Electrical connection to the printing
element is made through the copper leads on the top
and bottom surfaces of the substrate. Fifty print elements are fabricated on a single substrate to form a
261
262
Fall Joint Computer Conference, 1967
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serial input mode, provide a MIL-STD-188B interface,
and produce multiple copies.
Let us now discuss what problems were encountered
along the way, what significant advances were made,
and how this printer operates.
When this thermal printing contract was initiated,
there were some major areas where either ideas had
not been proven or no firm ideas existed at all. Major
problem areas were known to ce the print wafers and
a mUlti-copy process.
Print wafer problems
PRINT WAFER
F/G(/Rt! Ib
PRINT HEAP
~/~U~~
Ie
Figure la-Print element
Figure I b-Print wafer
Figure Ie-Print bead
print wafer (Figure Ib). They are arranged in 10 groups
of 5 with a space in between each group.
Five wafers are mounted together to form a print
head (Figure Ic). Each print head contains ten 5 X 5
matrices; each matrix is capable of printing one character. Eight print heads are mounted side by side in
the printer to achieve the 80 character line.
By applying power to combinations of print elements
in a matrix, the thermal image of the desired character
can be formed in the appropriate position on the print
line. The Thermal Printer has the capability of printing
anyone of 64 alphanumeric characters or symbols in
any position on the print line.
A 5 X 5 matrix was chosen over the more widely
used 5 X7 matrix for the following reasons:
1. Choosing the 5 X 7 matrix font would ini:rease the
number of print head wafers and driver circuits
by exactly 40 % plus increase the complexity of
the selec..tion logic by approximately 40%.
2. The intelligibility of the printed characters employing the 5 X 5 font rather than the 5 X 7 font
was not significantly reduced.
High-speed thermal teleprinter
The High-Speed Thermal Teleprinter was developed
to print at speeds of 60, 120, and 240 characters per
second, print 64 Alphanumeric Characters using the
There were four basic problems in the print wafers
alone. They were abrasions, interconnections, alignment, and burnout.
The abrasion problem was due to the print heads
rubbing against the paper while printing. At the time of
the contract award print head life was about 15,000,000 lines of print. Through tests of various resistor
materials and overcoats, and continued plated mechanism development, the life of the print head was extended. to 50,000,000 lines of print, which is equivalent to operations at the 240 characters per second
speed with a 25 % duty cycle for 2 years. The total
printed output would ce equivalent to that of an
existing 10 characters per second, Standard A, Military Teleprinter operating at a 25.% duty cycle for
48 years.
The next problem area was interconnections. For a
full 80 character line, there are over 2,000 printing
elements lined up in 5 rows. The print line is 0.1 inch
high and 8 ~nches wide. This means that over 2,000
connections had to be made to the wafers through a
cross sectional area of only 0.8 square inches. To do this
a technique was developed to connect high density, copper clad, mylar cable conductors to the matching conductor pattern on the wafers. The conductors are on
0.028 in:h centers-O.OI8 inch conductors with 0.010
inch spaces. There are several standard ways that the
cables could be fastened to the print wafers. The connections could be bonded with a conductive epoxy,
soldered, or welded. All of these processes, however,
require very precise registration and would need to be
performed in a clean room as foreign particles. could
short out adjacent conductors. In addition, the soldering and welding . oth damage the copper clad mylar
cables, and the problems of registering a conductive
epoxy pattern would be difficult. To overcome these
problems, the process that was used for this development was first to apply a very thin coat of non-conductive epoxy on one side of the wafer, then lay the cable
on the wafer and align the conductor patterns visually.
Next, the cable and the wafer are clamped together
High-speed Thermal Printing
with a plastic clamp that permits visual verification of
the alignment while the epoxy is drying. After the
epoxy dries, we have not only a permanent, rugged,
mechanical bond between the wafer and the cable but
also a good electrical connection between each conductor on the wafer and its corresponding conductor on
the cable. The mechanical bond is, of cours'e, formed
by the epoxy. The electrical connection is not so easily
explained, since this epoxy is a good electrical insulator.
The key to understanding the electric~l contact is
that the conductor surfaces are not microscopically
smooth but composed of tiny hills and valleys. When
.bonding is performed, the pressure forces the epoxy
into the valleys and causes the hills to make contact.
After the epoxy is dried and the damp removed, the
epoxy still holds the conductor surfaces in contact.
Typical resistance' is 0.1 ohm with a maximum resistance of 0.25 ohm. Connections of this type have been
tested successfully at temperatures as high as 1000° F,
at which point the mylar cable failed (not the electrical
connection). Over 100 cables, having 30 conductors
each, have been bonded to date, and only two defects
have been found. This would indicate a 98 % ' yield
which is better than previous experience with a dip
solder technique for this application. This process may
find other uses. In general it could be considered whenever a permanent connection is desired between multiplicities of conductors and space is at a premium.
The next problem area is alignment. If all the printing elements are not located in the same plane thermal
transfer to the paper will be poor, resulting in poor
quality printing. Tests have shown that the allow~ble
deviation from the printing plane is around ±0.0002
inch. Since the print head plane is composed of five
discrete wafers, the required alignment is not easily
maintained. In previous work this had not been con-·
sidered a major problem because only single character
printers had been built. In these instances the area of
the printing plane and the' cost of the wafers were both
relatively small. This led to hand tailored wafers and
assembly procedures which could not easily be expanded to adequately meet our problem. Although
maintaining the flatness of the printing surface on the
wafer to these dimensions was no problem, the tolerance on the dimension which located the printing plane
could not be held closer than ±0.0005 inch.
Consequently,- the procedure adopted was to measure
and divide them into groups of five, such that each
group was within the required tolerance. Each gro¥P
of five would then be used in one print head assembly.'
The print head assemblies were then made so that they'
could be adjusted to overcome the alignment .problem
263
between adjacent print head assemblies. Although this
approach has produced a functioning printer, it is felt
that the problem has only been eluded rather than
solved. However, there are other techniques currently.
under development for producing print heads that
would not have an alignment problem.
This brings us to the remaining problem area-burnout, where the most significant contribution was made.
When this program started, the state-of-the-art thermal
print heads were satisfactory for 15 cycles per second
operation, consisting of a 10 millisecond print pulse
followed by a 57 millisecond cooling period. However,
in this application, under worst case conditions, we had
a 4 millisecond print pulse followed by 21 milliseconds
of cooling time. The only easily measured parameters
which were useful in this area of development are
energy required per pulse to achieve printing, and energy required to cause failure (burnout) at a given duty
cycle. In this design a 10 mws pulse of energy is used
to print and, at the maximum duty cycle of 16.7%,
15 mws of energy per pulse would be required to cause
an element to fail.
It is interesting to note that unlike most other printing systems, thermal printing does not require more
energy to go faster. This is because the inertias associated with mechanical printers have no thermal counterparts. The term "thermal inertia" is a widely used
misnomer which can lead to faulty conclusions about
heat flow. Printing has been achieved with pulse times
as short as 150 microseconds.
The limiting factor in high speed operation is not
therefore the energy required, but the maximum temperature which the elements can withstand. With constant energy required, shorter pulse time causes the
input power (rate of energy) to be increased causing
the maximum 'temperature to increase.
Since a thermal print element is composed of b.yers
of different materials in a three dimensional configuration, an accurate mathematical model is difficult to
construct. However, a simplified mathematical model
has ceen constructed from the equations for the temperature of a semi-infinite solid with Cl: single heat
pulse applied at the surface and parallel heat flow, perpendicular to the heated surface. 2 A number of assumptions (which are now known to be not precisely
correct) must ce made to apply to these equations to
simplify them; the resulting curve approximates the
shape of the measured Temperature versus Time curve
for a printing element (Figure 2). The model consists
of two equations, one for the time while the print element is heating and one for the time while it is cooling.
TH
==
CP y t
A
(1)
264
Fall Joint Computer Conference, 1967
WAFER # 696
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Figure 2-Thermal. printing process
RESISTANCE IN OHMS
(2)
where
TH
P
A
t C
Tc
tp
Temperature while heating
Input Power
Area of Printing Surface
Time
Empirical constant
Temperature while cooling
Time of printing pulse
The vertical tangent at t == 0, in both the theoretical
and measured time-temperature curves, graphically
emphasizes that the previously discussed "thermal inertia" does not exist. lncan also be seen from equation
(2) that the rate of cooling is a function of the rate of
heating. This feature, which has been confirmed experimentally, means that for high-speed applications
where a short-heating pulse is applied, cooling also
occurs more rapidly.
Since the energy required for thermal printing remains nearly constant regard'less of pulse width, this
application was more severe in two respects. First,
applying the same energy in a shorter time causes the
element to be driven to a higher maximum temperature.
Second, since the applied energy is the same but the
cooling period is shorter,.,the energy must be carried
away faster. The' graph, referenced in Figure 3, shows
the performance of the elements on a print wafer that
was available when .this '; program started. The "y"
axis represents energYr,and:the "x" axis represents the
print elements. For each print element there is a
circle representing the print energy and a triangle
indicating the' burnout energy. Three important aspects
of the print elements should be observed on this graph.
The first is that the variation of both the print and
i
Figure 3-Print element temperatures vs time
the burnout energies are large. The second is that
some of the print levels are higher than some burnout
levels, indicating inadequate performance. The third
is that some elements show adequate margin of
safety between the print and burnout energies. Many
changes in the print element were tried in an attempt to obtain a consistent, adequate margin of
safety between the print and burnout energies. Finally
a real breakthrough came. It was found that the thickness of the copper conductors on the wafers was a very
important factor in obtaining high performance print
elements. This makes sense since the copper conductors
would be a major thermal conductor also. Using this
knowledge it was also found that the dimension from
the printing surface to the copper termination was also
an important factor. By controlling and optimizing
both these parameters it was possible to both reduce
the variation in print and burnout energies and maintain a consistent high performance level. This is shown
in Figure 4. Wafers having thse characteristics were
used in the printer.
Although successful Thermal Printers have been produced, much work in the basic research areas needs
to be done if the full potential of Thermal Printing
is to be realized. Two of the more promising areas are:
( 1) Refining the mathematical model to include the
effects of paper and the copper leads; both of
these are known to cause gross effects. Extend the model to handle the case where multiple heat pulses are applied.
(2) Testing thermal sensitive papers down to millisecond response time range to determine the
limitations which the papers themselves may
impose on the process.
High-speed Thermal Printing
.. ..
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THERMAL
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PAPER
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•• • ••
•••
•
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•• • • ••• • • • •
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15 21
25 31
35 41
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PRESSURE
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265
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Figure 4-Early print wafer
Multiple copy problem
The other major problem area was in making multiple copies. All previous thermal printers made only a
single copy by contact with a heat-sensitive paper which
changed color when and where it was heated. Therefore, a paper was used which had the particular property that it is sensitized by heat and makes copies by
transfer under pressure. When the paper is heated by
the print heads the back coating becomes tacky - not
tacky to the touch but tackiness that will cause colored
material to be transferred to plain paper when it is
subjected to the fairly high pressures of the pressure platen and pressure rolls as shown in Figure 5.
There are 300 to 400 pounds of pressure on these
rolls in order to insure good copy. The tackiness remains for approximately 15 minutes so copies can
be made during this time period. The paper must also
retain enough of the colored material so that it will
not all be released initially but can make a number
of copies. A very desirable feature of this copy process
is that only plain paper is needed to make copies
thus reducing the operating cost. Three copies can be
made in the printer and three more by a copy roll
box which was also delivered with the printer.
Papers capable of producing up to 20 legible copies
have been tested. Copies made in this manner will
not smear with handling or fade due to time or temperature.
Although the single copy and multiple copy papers
are functionally different, they can both be used on
the High-Speed Thermal Teleprinter. Threshold temperature for both types can be altered to fit different
Figure 5-Improved print wafer
applications. Normal threshold temperatures range
from 125 0 F to 200 0 F.
Printer logic
This printer uses the thermal print heads to give
a 5 X 5 matrix font in a full 80 character line arrangement as described previously.
Now that we have the print heads, let us discuss
how the printer operates electronically to cause thermal
printing. The block diagram shown in Figure 6 will
aid us in this discussion. The printer receives the
incoming data in serial form - a start bit, 7 bits in
ASCII* format, a parity bit, and then a stop bit. This
represents one character. In the Input Section, the
digitizer converts the data to logic voltage levels and
stores this information in parallel form in the receive
register. It also checks the data bits to be sure that
they are of odd parity and checks the stop bit to make
sure that synchronization has been maintained over
the character interval. After the stop pulse has been
received, the contents of the receive register are loaded
into the intermediate register to make room for the
reception of another character. Next, the Control Section will shift the contents of the intermediate regis tel
into the print register. The contents of the print register
are then decoded to determine the proper character
to be printed. This character information is then sent
266
Fall Joint Computer Conference, 1967
DATA
INPUT
INPUT
POWER
SUPPLIES
PRINT
PLATEN STOP
ADJUSTMENT
PAPER
FEED
SECTION
ELECTRONICS
RACK
Figure 6-Printer block diagram
Figure 7-Printer layout
to the Encoder and Driver Section where encoding into
the 5 X 5 font code is performed and the appropriate
bit drivers are turned on so that the desired character
will ce printed. The position in which the character
is printed is determined by the Character Positioner.
When the character has been printed, the character
position counter in the Character Positioner will be
upcounted. The outputs of the position counter are
next fed into the character decoder which in tum
selects the character driver which determines the position in which the character is .to be printed. If the
character received is a carriage return or line feed
symbol, a line feed operation will be performed by
cycling the clutch and trake circuit in the Paper Feed
Section, and a carriage return operation will be performed by merely resetting the character position
counter to zeros. Notice that no mechanical action is
involved for a carriage return operation.
After several line feeds have been performed the
copy paper tension switches in the Paper Feed Section will sense the slack in the paper and activate the
copy roll gear motor which will drive the copy section.
paper are stored together in a 2-ply fan-folded format
with the folds on 5~ inch perforations. This media
is sprocket fed one line at a time. As this media comes
under the print head the master paper is on the bottom. To effect printing the platen is operated towards
the media in order to obtain a firm contact between
the print head and the media. This platen remains
operated until a line feed character is received, then
the platen is moved away from the media and the
media is stepped one line to prepare for the next line
of print. As a message is printed, the original copy
moves up the front of the printer and this copy can
be viewed through a window. The master copy goes
down into the copy section where two more copies are
made. If only the original copy is desired, the master
copy can be routed directly out of the machine after
producing the original copy. Then, if desired, the
master paper can be used off-line with a copy roll box
to make at least five more copies. A photograph of
this printer is shown in Figure 8.
Hardware
Now that we have discussed the operations of the
printer, let us look at how the hardware for this printer
fits together. A side view of the printer is shown in
Figure 7. The location of the electronic circuits, power
supplies, paper supply, paper feed mechanism, printing head, platen, copy section, and control panel is
shown in this layout. It should be pointed out that
all the logic in the machine is integrated -circuits even
though the design was started in 1964.
The way that the media is handled in this printer may
copy roll gearmotor which will drive the copy section.
Other developments in thermal printing
Let us now talk briefly about other developments in
thermal printing and possible applications.
Contrary to what many people think, the speed of
thermal printing is relatively fast. A 150 microsecond
current pulse has been found to cause printing although
this speed of printing has not been thoroughly tested
to date. But even forgetting about this 150 usec rate
and taking .the 4 msec rate of printing used in the HighSpeed Thermal Teleprinter, we can show that thermal
printing compares in speed with high-speed line printers .The present High-Speed Thermal Teleprinter prints
serially by character so with the addition of multiple
electronic circuits, this thermal printing technique
High-speed Thermal Printing
267
which is comparable with the speed of other type line
printers of this size.
USAECOM has also sponsored a development of
Miniaturized Techniques for Printing (MINIPRINT)
with NCR. This is an exploratory development printer
which prints at 15 characters/second, can be operated
from a keyboard, and was developed for potential use
as a self-contained, battery operated, tactical teleprinter. The package size of the present model (cigarbox size) may also contain all the required electronics.
The printing is immediately visible on new thermal
sensitive master paper. The master and first copy are
made simultaneously in this printer and at least ten
legible copies can be obtained using the master copy
and plain paper in an off-line pressure device.
CONCLUSION
Figure 8-High-speed thermal teleprinter
could be incorporated into a line printer configuration
-printing each line of characters simultaneously. The
speed calculation for such a printer is as follows:
Assuming a 4 msec print time and a 21 msec line
feed time (which is within the state-of-the-art for line
feed techniques and will also be equal to the cool down
time for the print head) we have 4 msec + 21 msec ==
25 msec per line. Therefore
2400 lines
1
X msec X 60sec
---10-3sec
25 msec
minute
1 min
line
The Thermal Printer can print data received at any
mixed rate of input - including input from a keyboard.
The rate of input has been tried and tested at rates
as high as 240 characters/sec which is certainly not
the upper limit. Since we also get an electronic, nonimpact printer which appears to be very reliable and
can produce multiple copies on plain paper, thermal
printing may have potential application in many systems - both communications systems and· automatk
data processing systems.
REFERENCES
2
W H PUTERBAUGH S P EMMONS
A new printing principle
Proceedings of the Spring Joint Computer Conference
pp 121-124 1967
H SCHROEDER
Thermal printing
NCR Report AD-1232 pp 9-11 1964
Solid state synchro-to-digital converter
byG.P.HYATT
Teledyne Systems Company
Hawthorne, California
INTRODUCTION
The application of digital computers has been severely
limited in systems that must interface with analog
computer equipment. This limitation is particularly
prevalent in aerospace systems where the lack of the
appropriate interface equipment often precludes the
use of a digital computer. Although digital computers
are highly miniaturized and economical, the interface equipment often offsets these advantages with
mechanizations that can exceed the computer size and
cost. In order to enhance the applicability of digital
computers for aerospace applications, Teledyne has
expended considerable effort in the development of
hybrid interface equipment. This hybrid equipment is
mechanized with the latest solid state components
and advanced packaging techniques to implement a
universal interface that is miniaturized, modular, and
economical. This interface unit is compatible in
performance and packaging with the Teledyne family
of digital computers.
The basic guidelines for the development of the
hybrid interface equipment were to:
I. Place the burden of the conversion on the digite:. ~
equipment,
2. Minimize the performance requirement placed
on the analog equipment, and
3. Eliminate electromagnetic and electromechanical
equipment.
The most complex part of the hybrid interface
equipment is the synchro-to-digital (SID) converter
because of the three wire (1200 coordinate system)
AC analog form of the synchro signals. The Solid
State SID Converter accepts these three wire AC
waveforms, performs a minimum of signal processing
in the analog domain, then efficiently converts the
data to a digital form for processing in the digital
domain. The analog equipment converts the AC
analog 1200 coordinate signal forms to incremental
digital orthogonal coordinate dC!ta. The digital data
269
is processed with a digital "follow-up servo" implemented with Digital Differential Analyzer (DDA)
computer modules. The DDA will insure scale factor
and phase angle precision and automatically compensate for many errors introduced in the analog domain.
The digital output of the SID converter will contain
the sine and cosine functions in addition to the angle.
This is a significant advantage over converters that
only generate the angle, because the trigonometric
functions of the angle are often the parameters that
are required.
Contemporary SID converters perform the conversion with electromechanical follow-up servos driving
digital shaft encoders or with switching of taps on
transformer type electromagnetic equipment. These
techniques require large, heavy, and expensive electromechanical or electromagnetic hardware used in
a servo loop to null the input signal. The size, weight,
performance, and cost considerations preclude the
use of the~ converters for many aerospace applications.
A description of the Solid State SID Converter
mechanization will be presented following an analysis
of the pertinent characteristics of the synchro waveforms.
Synchro signal forms
A synchro is an analog angular position transducer,
where the output signal is an AC voltage with the
amplitude indicative of the angular position of the
rotor.
A schematic representation of a synchro is presented in Figure 1. The rotor is excited with an AC
voltage that couples to the Y windings of the stator
through transformer action. The angular position of
the rotor, with respect to the stator, will determine the
electromagnetic coupling between the rotor and each
of the stator windings, thereby defining the amplitudes of the signals in the three windings. The stator
output voltages are either in-phase or 1800 out-of-
270
Fall Joint Computer Conference, 1967
phase with the reference excitation. The amplitude
and phase (in/out) of the output voltages is indicative
of the angular displacement. The output signals are
in time phase with the excitation signal, with the amplitude of the output signals conveying the trigonometric information. Phase shifts between the reference
and the output waveforms do not convey angular information, but are potential sources of error in
interpreting the output signals.
The excitation signal, shown in equation (1), is
electromagnetically coupled to the output windings
of the synchro, generating the output signals shown
in equations (2) through (4).
E sin cut
(I)
Vexcitation
KIE sin cut sinO
(2)
V O- 1
KIE sin cut sin (0 - 120°)
(3)
VO- 2
KIE sin cut sin (0 - 240°)
V O- 3
(4)
The time dependent term, sin cut, is common to all
signals and is not a function of rotor position. The
other terms of the synchro output equations are amplitude defining qualities, independent of the time
varying portion of the waveform. I t can be seen that
the output signals are all in time phase with the
excitation signal, and the amplitude is a trigonometric
function of the angular position of the rotor. Equations
(2) through (4) define the voltage induced in the
winding from the common point of the three coil Yconnection to the output terminal. The common point
of the three windings is usually not available for
synchro follow-up operation. Therefore, it is necessary to operate on the voltages across the three output winding legs. The output signals of the synchro
are listed in equations (5), (6) and (7). The subscripts define the terminals across which the voltages
are measured.
V 1-2
K2E sin cut sin (0 ~ 150°)
(5)
K2E sin cut sin (0 + 90°)
(6)
V 2-3
V3- 1
K2E sin cut sin (0 - 30°)
(7)
The signals defined in equations (5), (6) and (7)
represent those signals which are available at the interface. Equations (5) and (7) contain sufficient information to completely define the synchro position,
while equation (6) is redundant. The information contained in equations (5) and (7) can be organized in a
more intuitive form with the use of the trigonometric
identities, illustrated as equations (8) and (9).
sin(O - 150°) = sinOcos 150° - cosOsin 150°
= - Y3!2 sinO - 1/2 cosO
sin(O - 30°) = sinOcos30° - cosOsin30°
= Y3/2 sinO - 1/2 cosO
(8a)
(8b)
(9a)
(9b)
substituting equations (8b) and (9b) into equations
(5) and (7) yields equations (10) and (] I), respectively.
V a- 1
~2Esin cut (Y3sinO + cosO)
(10)
~2Esin CUT (\13 sinO -
(11)
cosO)
From equations (10) and (11), it can be seen that the
voltages measured from synchro outputs 2 and 3;
using synchro output 1 as a reference; is composed of
sine and cosine components of the angular displacement of the synchro rotor. The coefficients of the
corresponding trigonometric functions of 0 from
equations (10) and (11) are equal. Therefore, algebraic manipulation of equations (10) and (11) can be
used to isolate the components of the interface signals
that define the sine and the cosine of the synchro
angular position. The addition and subtraction of
equations (10) and (11) will yield equations (12) and
(13), respectively.
V 2- 1 + V a- 1 = K2 v3E sin cut sinO
V 2- 1 - V 3- 1 = K2E sin cut cosO
(12)
(13)
The time varying term, sin wt, is removed with a
Phase Sensitive Demodulator. This term is removed
from the signals represented by equations (10) and
(11) before they are added to form the signals represented by equations (12) and (13).
Equations (12) and (13) completely define the angular position of the synchro. I t should be noted that
the trigonometric functions of 0 contribute only to
the amplitude of the respective signals, introducing
no inherent time or phase sensitive terms. The two
signals defined in equations (12) and (13) are time
coincident with the excitation to the synchro, excluding error mechanisms.
The resolver is an alternate type of angular position
transducer sometiines used in place of the synchro.
The resolver is shown schematically in Figure ] B.
This device will transform the excitation signal into
sine and cosine components of the angular displacement of the rotor. With the excitation, defined in
equation (14), applied as illustrated in Figure I; the
output signals from the resolver will be as defined in
equations (15) and (16).
Vexcitation
E sin cut
(14)
Vs
=
E sin cut sinO
(15)
Vc
=
E sin cut cosO
(16)
These equations are similar in form to equations
(12) and (13), yielding a common signal form upon
which to develop compatible synchro/resolver-todigital converters.
A Scott-T transformer is a device that is capable of
converting between two phase and three phase signal
forms. The synchro signals are in three phase form
while the resolver signals are in two phase form.
Therefore, the Scott-Tis a convenient conversion
Solid State Synchro-to-Digital Converter
r----------- VI
AC
OUTPUT
~--------------------------------~-~
(A) Synchro
~
\
~;ClTA. -,T:_O_N - -.~'- r-~R_O_TO_R~0=::
___
e T A TO ,
(B)
:
OUTPUT
Vc
Resolver
Figure I - Angular position transducer
device between synchro and resolver type signals. It is
desirable to have the signals in two phase form for
convenience of processing and conversion. Therefore,
the Scott-T may be used to convert the synchro signals to two phase form. Most contemporary synchroto-digital converters use a Scott-T to convert the
synchro signals to two phase form prior to performing
the digital conversion. A Scott-T is a relatively
bulky, heavy, and expensive component. Therefore,
the techniques described for the Solid State SID
Converter perform the conversion between the two
and three phase signal forms using semiconductor
components instead of the transformer type Scott-To
This conversion is implemented merely by adding
summing resistors to the input of an integrated circuit
operational amplifier, thereby implementing equations
(12) and (13). It is obviously a good tradeoff to
replace a Scott-T with only two summing resistors.
Synchro-to-digital converter
A representative mechanization of the Solid State
SID Converter is illustrated in Figure 2. It is basically
271
a succession of conversions from each signal form to
a more convenient signal form that permits appropriate processing. This approach permits many variations
of the conversion concept, depending upon interface
considerations and tradeoffs. In a typical application,
the synchro transmitter is excited from a reference
AC voltage supply. The excitation is coupled to the
output windings as a function of the mechanical
angular displacement of the synchro rotor. This
angular displacement is illustrated as the (}I input
angular displacement. Three output lines are presented to the interface with signals that are indicative
of the angular position of the synchro. These interface signals are in AC analog form, with an AC
carrier frequency that is amplitude modulated as a
trigonometric function of the angular displacement
of the synchro. The time varying components of these
signals are either in-phase or 1800 out-of-phase with
the reference excitation. A Phase Sensitive Demodulator (PSD) is used as an AC analog to DC
analog converter. The Demodulator is a synchronous
chopper, switching the input signals onto the output
line in synchronism with the reference signal waveform. The output of the Phase Sensitive Demodulator
is a DC signal with a high ripple content, similar to
a full wave or half wave rectified waveform, whichever is applicable.
In typical applications of a Phase Sensitive Demodulator, the output signals are filtered to remove
the large ripple content. In the mechanization illustrated in Figure 2, the output of the Phase Sensitive
Demoduiator is operated on by a Reset Integrator
(RI), which will provide a filtering function superior
to that of a passive filter. In addition, the ripple will
not propagate into system errors due to the inherent
error compensation characteristics of this converter.
The Reset Integrator provides the primary function of a DC analog to pulse rate converter. In the
mechanization shown, the Reset Integrator also provides the secondary function of algebraic summation
of the synchro information, described analytically in
equations (12) and (13). This summation function
effectively converts from three phase synchro type
information to two phase resolver type information.
Therefore, the output of the Reset Integrator is in
orthogonal coordinate trigonometric functions.
The Reset Integrator primary function of DC analog
to pulse rate conversion is accomplished by implementing an analog integrator which integrates the
DC voltages applied at the input. When the integrator
output exceeds a voltage threshold, a precise reset
pulse is generated to reset the integrator a calibrated
amount by discharging the feedback capacitor. The
rate at which the integrator continues to exceed the
272
Fall Joint Computer Conference, 1967
REFERENCE EXCITATION
SYNCHRO
~IGITAL
COMPUTER
INTERFACE
Figure 2 - Synchro-to-digital converter
threshold is a function of the input voltage levels.
The resetting pulse rate is also used as the Reset
Integrator output and is indicative of the rate at which
the integrator continues to exceed the output voltage
threshold. Therefore, the output pulse rate is directly
proportional to the average input voltage magnitude.
The mechanization illustrated in Figure 2 makes
multiple use of the Reset Integrator functional block,
where it is used to:
1. Perform the DC voltage to pulse rate conversion.
2. Perform the three phase synchro to two phase
resolver type signal conversion.
3. Perform the filtering function for the DC signals from the Phase· Sensitive Demodulator.
The ease with which the multiple functions are implemented in the analog domain significantly reduces
handware and improves accuracy of this mechanization. For example, the three phase synchro to two
phase resolver type signal conversion is accomplished
by the addition of one resistor to each Reset Integrator summing junction. These two resistors are used
to replace the Scott-T transformer type three phase to
two phase signal converter. Therefore, the advantages
of this technique is quite significant.
The Reset Integrator outputs are pulse trains, the
rate of which is proportional to the trigonometric
functions of the synchro angular displacement. These
two pulse trains are significantly amplitude sensitive; where synchro excitation variations, synchro
transformation ratios, and other mechanisms that
affect the scale factor of the signals will affect the
amplitude of the Reset Integrator output. Direct use
of this pulse rate information in the computation will
result in amplitude or scale factor errors, but which
will appear as angular displacement errors. These
scale- factor errors can be conveniently eliminated by
using the ratio of the two pulse trains instead of each
pulse train by itself to determine the angular displacement of the synchro.
A Digital Differential Analyzer (DDA) trigonometric computational block is implemented to
eliminate the scale factor sensitivity of the synchro
signals. This computation is described in the corresponding section of this report. Effectively , equation
(17) is implemented with a DDA computational block.
sin(OI - Oe) = sinOIcosOc - cosOIsinOc
(17)
A DDA sin-cos generator, used as a "digital resolver," is rotated computationally to balance the
input pulse rates. The solution of equation (17) using
DDA techniques assures the availability of the synchro trigonometric functions that are completely
independent of any scale factor type errors from the
input. The outputs of the computation block are whole
number serial trigonometric (sine and cosine) functions, whole number serial angular information, incremental trigonometric functions, and incremental
angular information. This DDA computation is a
necessary part of this Synchro-to-Digital Converter
concept, because the scale factor sensitivity of the
273
Solid State Synchro-to-Digital Converter
synchro information would not permit sufficient
accuracy, in most applications, without this compensation. As a contrast, the insensitivity of the converter outputs to the input scale factor parameter
significantly decreases the cost of the analog equipment and provides a very significant amount of automatic compensation of scale factor type errors in the
analog hardware. The predominating error mechanisms in the analog equipment are of a scale factor
nature. Therefore, the elimination of the scale factor
sensitivity consideration will permit extremely accurate analog mechanizations with only moderate
consideration to many of the predominating error
mechanisms. In addition, this D D A computation
generates the trigonometric functions of the angle
in addition to the angular information. Other types of
SID Converters typically generate the angular information only, requiring additional computation to
generate the trigonometric functions of the angle.
Therefore, cost and equipment comparison between
this mechanization and other converters should be
made on a comparable basis, where the DDA computation is included in the comparison only if the
alternate converter will present the trigonometric
functions of 8 at the computer interface. If the other
converter will generate only the angular information,
a functional block equivalent to the DDA computation must be added to generate the trigonometric
functions of the synchro angle. An alternate tradeoff would be to draw the computer interface at the
input to the DDA computational block for a realistic
comparison with the alternate type of converter. That
is not to indicate that this converter can operate
independent of the DDA computational block, but
only to compare the alternates on an equivalent basis.
These considerations are contingent upon the requirement for trigonometric functions of the angle in the
computation. Experience has shown that, in general,
the trigonometric functions of the angle are required
and not the angle explicitly.
An alternate mechanization of the Synchro-toDigital ·Converter is illustrated in Figure 3. This
mechanization accepts the three phase synchro type
information and converts it to two phase resolver
type information with a Scott-T transformer. The two
channels operate virtually independently, without the
need for cross summing DC analog signals. The outputs of the Scott-T transformer are AC waveforms
with amplitudes indicative of the trigonometric functions of the synchro angular position. The Phase
Sensitive Demodulators will act as AC analog to
DC analog converters, with the Reset Integrators
acting as DC analog to pulse rate converters. The
DDA computation is identical to that used in the
previously described mechanization. The considerations for this alternate mechanization are identical
to that for the first mechanization, with the exception
of the added cost and weight factors introduced by the
Scott-T transformer.
DDA trigonometric computation
The DDA trigonometric computation functional
block is a requirement for this Synchro-to-Digital
Converter mechanization in order to eliminate the
scale factor sensitivity of the converter. It is conceivable that, in certain types of applications, the
synchro scale factor parameters could be controlled
REFERENCE EXCITATION
-
i
+
I
IV 1
SYNCHRO
IV2
i
~ V3
Vs
-
~
I
,
SCOTT T
..
Vc
1
I
AC ANALOG
SIN WT
..
PHASE
Vs
SENSITIVE
~
DEMODULATOR
PHASE
Vc
SENSITIVE
DEMODULATOR
r-=-+
RESET
INTEGRATOR
RESET
INTEGRATOR
DC ANALOG
SYNCHRO
INTERFACE
d(
SIN 8 dt
1
~
DDA
TRIGONOMETRIC
COMPUTA TlON
COS 8 dt
1
..
I
d(COSf):)~
d(SINHJ~
COS8 c l
J
SIN Or:: __ JI
8c
PULSE RATE
I
(J c)
--I
DIGITAL
COMPUTER
INTERFACE
Figure 3 - Synchro-to-digital converter
274
Fall Joint Computer Conference, 1967
within the requirements of the conversion. In the
general case, tolerances are an order of magnitude
greater than the required conversion accuracy,
necessitating this computation. For high accuracy
type converters, the DDA equipment that is required
will be offset by the simplification of the analog
equipment due to the reduction of the scale factor
sensitivity of the converter.
The converter implicit servo is implemented in the
digital domain with Digital Differential Analyzer
(DDA) computational elements. This DDA is a
parallel computation serial word computer; where
all computations are performed simultaneously in
a bit by bit serial fashion. The DDA performs computations by successive additions accomplished at the
rate of 32,000 iterations/second to approximate integration or multiplication. A detailed description of
DDA operation is contained in Reference 1. The
DDA Computation is illustrated functionally in
Figure 4. This functional diagram implements equation (17), which is the trigonometric identity for the
sine of the difference of two angles. The input angle,
OJ, is defined by the synchro rotor displacement with
respect to the stator. The computed angle, ()e, is contained in the DDA sin-cos generator. For the condition that ()I is equal to ()e, equation (17) will be nulled.
The implementation of equation (17) with a DDA in
an implicit servo type function will cause the DDA
sin-cos generator to be driven to a condition equivalent to the angular displacement of the synchro. As
the synchro is rotated, the DDA sin-cos generator
will be servoed to the corresponding angular position.
Effectively, the DDA Computation block performs
the function of a digital "follow-up servo."
The functional diagram, illustrated in Figure 4A,
implements an implicit servo to solve equation (17).
DDA computational elements 1 and 2 are used as
pulse rate multipliers, where the input trigonometric
function pulse rate information is multiplied by orthogonal trigonometric functions from the "digital resolver." The symbolism used for DDA computational
elements 1 and 2 indicates that the R register and R
logic functions are utilized, but the Y register word
is fanned-in from other DDA computational elements.
For example, the Y register number for computational
element 1 is obtained from the Y register of computational element 4. This Y register number is fannedout to the two R logic functions, one in computational
element 4 and the other in computational element I.
This fan-out is illustrated more graphically in Figure
4B, the sub-functional block diagram. Computational
elements 3 and 4 implement-a DDA sin-cos generator.
The two pulse rate products from computational
elements 1 and 2 are subtracted in the rate summer
to generate an error rate which is a solution to equation (17). If this error rate is zero, indicative of the
two trigonometric products being equal, the "digital
resolver" is at the equivalent angular position of the
synchro. If the error rate is not at null, the incremental pulses will be used as the d() inputs to the DDA
sin-cos generator, resulting in this "digital resolver"
being rotated to null the error rate.
The sub-functional block diagram, illustrated in
Figure 4B, implements rectangular integration for the
pulse rate multipliers and trapezoidal integration for
the sin-cos generators. The trapezoidal integration
algorithm will reduce the error buildup in the "digital
resolver" to an extremely small level.
It can be seen that scale factor coefficients of the
trigonometric functions will not affect the computation at the "digital servo" summing junction,
which is the rate summer. A true scale factor coefficient will be common to each of the trigonometric
sub-products of equation (17), thereby affecting the
gain of the "digital servo" but not the null. The
DDA computation that implements equation (17)
will be nulled independent of the scale factor of the
respective angular functions.
The output scale factor of the "digital servo" is
dependent on the initial conditions loaded into the
sin-cos generator. The vector sum of initial conditions for the sin-cos generator will define the scale
factor of the output trigonometric functions. These
initial conditions will be simple to generate, permitting a zero to be loaded into the sin ()e register and
a nominal scale factor, typically unity, to be loaded
into the cos ()e register. These initial conditions are
representative of an initial 0° angular position with
a unity scale factor. After the initial conditions are
loaded, the "digital servo" loop will be closed; thereby permitting the "digital resolver" to be driven to
the corresponding angular position of the synchro.
Therefore, only constant initial conditions need be
loaded; as the "digital resolver" will automatically
generate the proper parameters after the "digital
servo" loop has been closed.
Phase sensitive demodulator (PSD)
The Phase Sensitive Demodl,Ilator is effectively
a synchronous chopper that switches the input signals
in phase with the reference signal. Because the input
signals are either in phase or 180 out of phase with
the reference signal, a synchronous chopper will have
the effect of rectifying these signals, thereby generating an equivalent DC voltage proportional to the
amplitude of the AC voltage. The output waveform
will be rectified positive or negative voltage levels.
The PSD is implemented with FET (Field Effect
0
Solid State Synchro-to-Digital Converter
Ail
~
7
SIN flldt
--
I
8e
~
1
~ COS
(Ie
COS (lidt
I
[
I
2
~ SIN
(1 e
r--
~
RATE
SUMMER
I
-
3
~ SIN
(Ie
+--{ 0:
--
COS
d(
(1
e
)
SIN
(1
COS
(I
--:- d(SIN
d(COS
c
e
(1)
(I )
e
(A) FUNCTIONAL DIAGRAM
~------------~.~
~--...I
COS 0ldt
__--------------------------------------------------+-----+-----------~d(O e )
RATE
SUMMER
__---------~~--~-----.~SIN
(I
c
o-__________~---~------~COS(lc
L-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
d(SI N H )
c
L----------------------------------._d(COS0r.)
lB) SUB-FUNCTIONAL DIAGRAM
FigureA-DDA trigonometric computation
275
276 Fall Joint Computer Conference, 1967
Transistor) switches, synchronously chopping the
AC waveform into the input of an operational amplifier, illustrated in Figure 5.
a a a
V2 SIN wt
VI SIN wt
v
V V
SINwt
REF RETURN
VI SINwt
000
V v v
analog integrator to generate a ramp output~ the
slope of which is proportional to the DC voltage
input. A threshold detector generates a reset pulse
when the ramp exceeds a fixed threshold. The reset
pulse will reset the ramp by a fixed increment and
generate an output increment. The threshold detector,
by generating reset pulses, will maintain the ramp
amplitude below the fixed threshold. The rate at which
the ramp continues to exceed the threshold, in the
presence of the reset pulses, is indicative of the
average DC voltage impressed at the input. Therefore,
the pulse rate is proportional to the input DC voltage.
A typical Reset I ntegrator is illustrated schematically in Figure 6. This Reset I ntegrator is of the ternary
type, generating output pulses on the plus or minus
.REF
-REF
r:=~------------.
±E,
r-------:...
.j
Figure 5 - Phase sensitive demodulator
The PSD exhibits high common mode rejection
characteristics, which are inherent in the operational
amplifier inputs. Each channel of the PSD is driven
by the reference amplifier, which is used to "squareup" the reference input. This signal is used to switch
or synchronously chop the input signals with FET
shunt switches. The two switches for each channel
are driven in phase, controlled by the output of the
reference amplifier. A half wave" PSD results, where
the output has an amplitude and polarity determined
by the algebraic difference of the two differential input
signals. A half-wave Demodulator is acceptable
due to:
a. The freedom to achieve large scale factors
through the inherent gain of the operational
amplifiers.
b. The lack of concern with filtering the high
ripple content.
Many of the analog errors are automatically compensated in the digital equipment. The FET switch
on-resistance introduces an insignificant error due
to the swamping effect of the input resistors. Considerations such as signal phase shift and ripple do
not propagate to system errors, due to the automatic
compensation characteristics of the DDA.
Reset integrator (RI)
A Reset Integrator is a functional block that
generates a pulse rate output proportional to a DC
voltage input. It is used as a DC analog to pulse rate
converter. This function is implemented by using an
Q
e
j
R Q
S
Q
R Q
Figure 6 - Reset integrator
lines depending upon the polarity of the input DC
voltage. The input voltage, eh is integrated with the
operational amplifier integrator, where the output
voltage, eo, is equal to the integral of the input voltage. The integration time constant is RIC I, as illustrated in equation (18).
ei dt
eo RIC I
(18)
The output voltage is applied to two operational
amplifier level detectors, analogous to the conventional schmidt triggers. These operational amplifiers
will generate a large positive output when the output
voltage exceeds the voltage threshold defined by the
resistor voltage divider. The positive and negative
the summing junction are used to achieve
inputs
bipolar threshold detection. When the output of the
Reset Integrator exceeds a threshold, the output of
one threshold detector will go positive, thereby
enabling the flip-flop to be set. The synchronization
source will cause that flip-flop to be set at the appro-
-J
to
Solid State Synchro-to-Digital Converter
priate computer bit time, yielding a pulse-on-demand
type of Reset Integrator. This synch source will also
provide the reset pulse for the flip-flop, providing
precise timing for the pulse width. The output of the
flip-flop will be high for one pulse width period,
generating an output to the computer and a feedback
signal to the switch. The switch will cause a reference
voltage to be applied to the integrator summing junction through the reset gain setting resistor, R 2 • The
polarity of the reference voltage applied to the operational amplifier input is a function of the threshold
detector whose threshold was exceeded. The reset
voltage will be integrated, thereby driving the output
voltage below the threshold. The reset pulse is a precise increment, defined in equation (19).
~eo =
JotlRErdt
C
2
~e =
Ertl
l
(19a)
(19b)
In normal operation, the integrator output, as reset
by the feedback pulses, will have a value defined in
equation (20).
(t ejdt
N
eo = }o RIC I ~eo
(20)
The parameter N is the number of pulses out of the
Reset Integrator. The output pulse train from the
Reset Integrator is the most significant part of the
solution. The integral term, which is the least significant part of the solution, will be retained in the output of the integrator. Deleting the integral term from
equation (20) and substituting equation (18) and (19)
into the balance of equation (20) will result in the
transfer function for the Reset Integrator. The integral term can be deleted because it is the remainder
which is less than the resolution of the Reset Integrator. Differentiating equation (20) with respect to
time, then rearranging will yield equation (21); which
defines the output pulse rate in terms of the input
voltage. Equation (21) is the transfer function for the
Reset Integrator.
dn
e 1 R2
(it = RIErtl
(21)
All of the terms in this equation define the scale
factor of the functional block. Error components
inherent in these terms will cause a scale factor type
error. Because this converter mechanization is insensitive to scale factor type errors common to both
channels, most of these error mechanisms will not
contribute to the overall converter error. This is a
very significant error compensation affect, because
much of the complexity in mechanizing the Reset
Integrator is expended to minimize scale-factor
errors. This complexity includes precision reference
voltage supplies, low temperature coefficient resiso
R2 C l
277
tors, precision switching envelopes, and other such
considerations.
Hardware description
The electronics industry has made tremendous
progress in the development of advanced electronic
component and techniques. In particular, the advent
of integrated circuits has virtually revolutionized
the electronics industry, especially the digital computer area. The trend has been towards components
that are very small, fast, low in power consumption,
and highly reliable. In order to take advantage of the
new hardware available, new and sophisticated
handling and packaging' techniques have been required. In order to handle and package the miniature
components, much of the advantage of the small size
has been lost. Teledyne has developed packaging
techniques that make maximum use of the characteristics of the advanced components. In particular,
the Micro-Electronic Modular Assembly (MEMA)
takes maximum advantage of the characteristics of
integrated circuits. These are:
a. Preserving the small-sized characteristic of
the integrated circuit chip by placing many
chips in a single package.
b. Preserving the high speed characteristics of the
integrated circuits by placing them in very close
proximity with extremely short interconnections.
c. Preserving the inherent reliability of the integrated circuit by eliminating multiple packaging
levels.
In addition, greatly improved manufacturing and
maintenance techniques, are realized and manufacturing costs are significantly reduced. The basic
MEMA is a hermatically sealed flat pack with 24 leads. The dimensions are 1.0 x 0.75 x 0.06 inches.
Each l\:fEMA can contain up to 30 digital integrated
circuit "bare chips" or 25 analog chips (integrated
circuit, resistor, capacitor, etc.). The digital MEMA
is illustrated in Figure 7 and the analog MEMA is
illustrated in Figure 8. The "bare chips" and 1 mil
wire jumpers are clearly visible with the covers
removed. The interconnection pattc;!rn is photoetched onto the ceramic substrate. The chips are diebonded to the substrate, then the jumpers are used to
connect the chip signal pads to the substrate interconnection pattern. The jumpers are composed of 1
mil (1/1000 inch) diameter aluminum wire ultrasonically bonded to the chip substrate.
The MEMA contains the equivalent functional
complexity of a large printed circuit board within
a highly miniaturized package; reSUlting in enhanced
performance, reliability, cost, size, and weight.
278
Fall Joint Computer Conference, 1967
INTEGRATED
CIRCUIT
CHIP
SUBSTRATE
INTERCONNECTIONS
Figure 7 - Digital circuit MEMA
SUBSTRATE
INTERCONNECTIONS
INTEGRATED
CIRCUIT CHIP
CAPACITOR
CHIP
RESISTOR
CHIP
TRANSISTOR
CHIP
Figure 8 - Analog circuit MEMA
Error corisiderations
As previously described, scale-factor type errors
common to both channels of this converter will
not propagate to system errors, but will be compensated for automatically. Most of the temperature sensitive errors, voltage sensitive errors, phase
shift errors, reset pulse shape errors, and many other
types, will be automatically eliminated due to the can-
cellation nature of the amplitude sensitive errors.
Many of the balance type errors; such as resistor and
capacitor tolerances, bias errors, and other types; can
be minimized by simple adjustments on one channel
with respect to the other. These errors will then have
a tendency to track each other over temperature and
voltage type variations, providing automatic compensation over the operating spectrum. These automatic compensations and simple balance type adjustments very significantly decrease the cost and
complexity of the converter while significantly increasing the inherent and ultimate accuracies of the
device.
The Reset Integrator is the more critical of the two
major analog functional blocks in the converter.
Therefore, specific errors will be discussed for the
Reset Integrat6r with reference to Figure 6. The
Reset Integrator, when used alone, is extremely
sensitive to variations in the reference voltage that
defines the reset pulse. This reference voltage
will be common to both Reset Integrators and, therefore, will contribute corresponding scale-factor
errors to both channels. Therefore, a precision reference supply is not required for this converter mechanization. The voltage may be permitted to vary within moderately large tolerances over the operational
and environmental extremes. The ripple content of
the PSD output will have a tendency to frequency
modulate the Reset Integrator outputs. The ripple
content for both channels is phase locked and of
a scale factor nature. Therefore, this signal characteristic will not produce converter errors.
Some of the discrete resistors and the C 1 capacitor,
illustrator in Figure 6, will not contribute errors to
the Reset Integrator operation. The balance of the
discrete resistors will contribute primarily scalefactor type errors. The tolerance of these resistors
will cause a scale-factor spread between the two channels of the converter. This nominal spread will cause
an error that will not be cancelled, but can be adjusted
for. Operational. and environmental variations that
affect the value of the resistors will be common to
both channels of the converter and will be automatically compensated. Therefore, low thermal coefficient resistors are not necessary for this mechanization. The saturation resistance of the field effect
transistor (FET) switches has a spread of values that
can be swamped-out if the value of. R2 is made sufficiently large. Additional accuracy can be achieved
by matching the FET switches in both channels. The
temperature sensitivity of the FET parameters will
be common to both channels and should introduce
scale-factor type errors that will automatically compensate.
Solid State Synchro-to-Digital Converter
The Reset Integrator scale factor is inherently
dependent upon the shape of the reset pulse. Because
predictability of the Reset Integrator scale factor
is not a prime consideration, the shape of this reset
pulse need not be accurately defined geometrically. The only requirement is that both channels
exhibit corresponding pulse areas. Therefore, switching devices need only have moderately fast switching characteristics.
An analysis of the AC signal inputs to the Phase
Sensitive Demodulators verifies that a phase shift
between the reference excitation and the synchro
signals contribute a scale factor type of error to the
Converter. Therefore, there will be no error contribution due to the gross phase shift thru the synchro.
The system error will only be a function of the difference in phase shift between the two channels.
The types of errors described that are not of the
automatic compensating nature are primarily of the
bias type. Most of the bias errors can be balanced
with a single padding resistor in one of the Reset Integrator channels. This simple balance technique
would reduce the nominal bias and matching errors,
leaving the errors caused by changes in operational
and environmental conditions as the predominating
effects. Most of the operational and environmental
sensitive terms will be common to both channels
and of a scale factor type nature. Therefore, only
the second order differences in operational and environmental sensitivities between corresponding components and sensitivities of bias type effects will contribute to the converter errors. Because of these considerations, it is relatively easy to reduce the predominating error mechanisms inherent in the converter
279
to those normally considered as third order type
affects.
.
This description of the predominating errors in the
Converter illustrates that there is little need for a
highly precise reference power supply, low temperature sensitive equipment, or sophisticated circuit design techniques to facilitate a highly accurate
Reset Integrator. Relatively simple design techniques coupled with a simple balancing scheme could
easily implement highly accurate analog equipment
for this Converter.
CONCLUSION
The Solid State SID Converter permits the mechanization of a low cost accurate, versatile, and miniature interface that can accommodate synchro input
signals. This Converter will increase the feasibility
of using digital computers in conjunction with electromechanical analog computers, which are common
in aerospace applications. In addition, a more optimum mix of analog and digital techniques will be
practical for hybrid computers.
REFERENCES
E L BRAUN
Digital computer design
Academic Press N ew York Chap 8 p 448 1962
2 S A DAVIS B K LEDGERWOOD
Electromechanical componentsJor servomechanisms
McGraw Hill Book Company Inc New York Chap 3 p 92
1961
3 B C KUO
Automatic control systems
Prentice-Hall Inc New Jersey chap 4 p 92 1962
A new high-speed general purpose I / 0
with real-time computing capability
by KENNETH FERTIG
DUNCAN B. COX, JR.
MIT Instrumentation Laboratory
Cambridge, Massachusetts
(and its inverse) with phase information is the key
element in the I/O discussion. As a result, the realtime control problem and hybrid computer problem
may ce considered as essentially the same time shared
computer problem, and the traditionally complex I/O
pr~)blem of tying analog elements to the OPC may be
solved in the same simple way.
Several significant improvements can be made in
computer usage by the proper design of an I/O. In
particular, the programming can be simplified, more
useful computing can be carried out in a given time
interval, and greater system flexibility can be achieved.
INTRODUCTION
Real-time data acquisition and control systems incorporating a general purpose digital computer (GPC) are
considered for convenience to be composed of three
parts: transducers and transmission paths, an inputoutput mechanism (I/O), and the OPC. The transducers and transmission paths considered in particular are
those resulting in the desired data being phase-modulated on carrier waveforms. This type of phase-encoded
information may be received from a variety of sources,
among which are shaft-angle resolvers with sine-cosine
excitations, and Doppler navigation systems. The primary focus of attention in this paper is a new I/O
which can receive the phase-modulated waveforms directly, perform a variety of processing functions on the
raw data in its phase-modulated form, and present the
processed data in a convenient binary format to the
GPC. The new I/O can process data from a number
of sources in parallel at relatively high speeds, thereby
leaving the OPC time for monitoring, adaptive parameter adjustment, and other sophisticated decision and
control functions. Similar techniques utilizing different
phases of the computer clock signal permit the OPC to
generate digital and/or analog commands to transducers via the I/O.
Some examples of transducers and transmission links
are briefly presented as background material and motivation for a discussion of the I/O itself. The operation
of the I/O is then discussed in detail with reference to
a practical system for obtaining and processing wholeangle data from a multi-speed shaft-angle resolver and,
in more generality, with reference to a wide variety of
signal sources producing phase-modulated information.
The ease of performing analog/digital conversion
Transducers and transmissions links
In preparation for the detailed discussion of 'the
I/O, some examples of transducers and transmission
links pr.oducing phase-encoded information are given.
These examples serve to introduce some simple but
useful mathematical notation and to provide a physical
interpretation of the origin and meaning of the phaseencoded waveforms that are central to the discussion
of the new I/O. The examples also serve to introduce
the ideas that there may be several information sources
(either independent or dependent) operating simultaneously and that the information can conveniently be
multiplexed without altering the phase encoding. The
new I/O has the natural capabi~ity of processing the
phase-encoded information from several sources simultaneously.
A typical example of a transducer producing phasemodulated information is the shaft-angle resolver shown
in Figure 1. These transducers are found in equipment
ranging from inertial to machine-shop. The input signals el and e2 are any periodic waveforms with fundamental components E sin 2 1T f t and E cos 2 1T f t,
281
282
Fall Joint Computer Conference, 1967
respectively. The resolver produces an output
eo == el cos cp
e2 sin cp
(I)
where cp is the mechanical resolver angle. Hence the
fundamental component of the output is
fund (eo) == E sin (2 1T f t
cf>)
(2)
which is linearly phase modulated by the resolver
angle. Henceforth, we shall assume for convenience
that the input waveforms are square waves with frequency f and phase angles 0 0 and 90 0 , these are
denoted by fLQ and fL.2.Q, respectively, as shown in
Figure 1. Implicit in this notation is the assumption of
a reference zero phase angle, which we shall assume
is established by a reference clock. * The output of the
resolver we shall denote by ff.!! to indicate that the
fundamental component of the waveform is of frequency f and phase angle cpo
+
+
f.2f•..•. 2"f
ovailabl. at r.quired pha •••
4>'
mechanical
angl.
fll. • Pha..
modulated output
-'ann
containing fun-
cbMntai component at
frequency ·f· and angl."4>'"
Figure 1-A shaft-angle resolver with phase-modulated output
Often an m-speed resolver** yielding an output
fL.msk may be used with a one-speed resolver on a common shaft to assign roughly equal parts (in the sense
of double precision) of the desired angle information
to each of two modulated waveforms. Where there are
severCl J resolvers, their output may be time multiplexed
over a common transmission path with, e.g., four samples of each waveform taken per cycle, without distorting the phase of the fundamental component. l Another
possidlity is to effect frequency multiplexing by choosing the excitation frequencies for different resolvers as
binary multiples, e.g., f, 2f, 4f, etc. Of course, both
time and frequency multiplexing may be used simultaneously. In that case the outputs of the time multiplexer would be several xero-order-held waveforms,
each resembling the resolver output waveform _shown
in Figure 1, but' at different excitation frequencies.
These phase-modulated outputs would be received by
the new I/O. The frequency demultiplexing of the
*A clock is a high-frequency oscillator followed by a (typically binary) countdown chain from which several signals with
locked frequencies and phases may be obtained .
:;'*An m-speed resolver has windings with m pole pairs so
that its output phase angle passes through 360 degrees when
the mechanical shaft rotates through 360/m mechanical degrees.
information is automatically achieved in the new I/O
because an integral part of the new I/O is a set
is a set of phase-locked loops.
Other examples of transducers yielding phase-modulated information abound: Loran, Doppler radar,
sonar; etc. In these systems phase shift data correspond
to measurements of distance. Two or more carrier
frequencies (often multiplexed on a third) are often
used to measure the same distance variable. This
technique is completely analogous to that of using
one-speed and m-speed resolvers to measure a common
shaft angle.
The new I/O
A basic element in the new I/O is the phase-locked
loopt shown in Figure 2a. It consists of a phase-sensitive detector (PSD), a low-pass filter (LPF) with
transfer function F(s), a voltage-controlled oscillator
(VeO),:j: and a binary n-stage forward counter (countdown). The countdown output fLJL is a square wave
which in normal operation is locked in frequency
and phase with the fundamental component of the
input f& to the phase-locked loop. Ideally, () is
equal to cp plus 90 0 ; careful loop design can insure
that this relation is maintained reasonably well, in
many cases 00 within a small fraction ~f a degree.
The PSD can be a simple switching modulator that
mUltiplies the input waveform by
1 or -1, depending upon the state of the countdown output. The
LPF extracts the average value of the PSD output
and, in its most general form, p.erforms several other
filtering functions. The basic phase-locking operation
of the loop depends upon the action of the PSD in
producing an error signal to increase or decrease the
frequency of veo oscillation in order to drive the
phase error to zero. This mechanism is illustrated by
the block diagram in Figure 2b. Because of the presence of the n-stage countdown, the veo frequency
is 2 n times the input frequency. Loops of this type
have teen operated satisfactorily with veo frequencies
as high as 5 mc and with as many as ten countdown
stages. Standard heterodyning techniques can be used
to accommodate input frequencies that are impractically high for the basic loop shown in Figure 2a.
The effect of the phase-locked loop is to create a
set of square waves, each wave being the output of
one stage of the countdown in Figure 2a, that track
the phase cf> of the fundamental component of the
input waveform. The phase angle () of this set with
+
"i"ror good sources of information on the behavior, design and
use of pha~e-Iocked loops the reader is referred to Tausworthe2
and Gardner. 3
:l:Any simply controllable oscillator is usable, including digital
oscillators made by DDA techniques.
A New High-speed General Purpose I/O with Real-time Computing Capability
Phase Sensit ive
Detector PSD}
Voltage Controlled
Oscillator
Low Pass
Filter F s
fLe/>
INPUT
LPF
fL8
VCO
2- n Countdown
flwvco
KpSD = Gain of PSD
cp
=,J'~
:
~
.~
-...
KpSD
283
KVCO
-
.....
-....
F{s}
= fl input voltage to VCO
1
KVCO-;
90°+9
I
I
2- n I_
1-
Figure 2-The phase-locked loop
respect to a reference clock waveform fLQ. is easily
determined by the process diagrammed in Figure 3.
At the instants when the clock waveform fLU. changes
states in the positive going direction a determination
of the states of each of the countdown waveforms
is made. Knowledge of whether fLJl.. is up or down
narrows the uncertainty in the angle to a 180 0 region;
knowledge of whether 2f/2() is up or down further
narrows the uncertainty in the angle to a 90 0 region;
etc. This process, referred to hereafter as "strobing
CLOCK
fLO°
STROBE
fL80
1
LOCKE
2f/.J.8°
n
2 fOn8 0
r--t----'-....L......J'--'--'-t"'--"---'--...........L-............L--~--L.....L-..JI....-
Figure 3-Strobing waveforms
the countdown waveforms with the clock waveform,"*
results in a unique synchronous binary encoding of
the angle and is the heart of the new I/O. A functional
implementation of the strobing technique to measure
a resolver angle is diagrammed in Figure 4.
The strobing process for obtaining binary encoding of phase angle can easily be extended to the case
where there are two signals available corresponding to
a common measurement variable, as from one-speed
and m-speed resolvers on a common shaft. The onespeed signal flL2 and the m-speed signal f2~ can,
of course, be encoded separately, each with its own
phase-locked loop strobed from a common clock.
However, with this arrangement, as with any independent encoding scheme, unavoidable misalignment between the one-speed and m-speed data will cause,
*Note that the process could be modified to obtain angle
encoding by having the signal f Lfl from the phase-locked loop
strobe the signals in the clock countdown, in which case the
phase-locked loop would be acting as a filter and zero-crossing
detector. However, with this arrangement, the precise times
at which the data strobes occur would not be known a priori,
and this uncertainty could be an important disadvantage when
precise dynamic measurements are required.
284
Fall Joint Computer Conference, 1967
RESOLVER
f
8"lt/J-90·
other
freqUenCiesL_ _ _ _ _ _ _ _-G~~~~
available
The introduction of the correction signal for misalignment angle is easily accomplished by adding a
small fixed voltage to the signal at the output of the
PSD of the coarse-data loop. Then the indicated strobing scheme results in whole-word data being obtained
jointly from the one-speed and m-speed phase-modulated signals.
The elementary I/O as described has been constructed and operated satisfactorily to obtain 13 bits
of whole-word data at a I KC synchronous strobing
rate from a 1- and 16-speed shaft-angle resolver.
Comparison with conventional anglemeasurement techniques
Figure 4-Strobing technique to obtain binary phase output
for certain angles, an inconsistency in the binary
encoded data. An example of such data from I-speed
and I6-speed resolvers on a common shaft is shown
in Figure 5. The inconsistency lies in the fact that
the overlapping bits do not agree. In this case it is
I
I
I
I
most
significant
bit
I
0
,1
coarse data (from I-speed resolver)
1 I I 0 I fine data
(from 16-speed
resolver)
I
overlap
bits
1
least
significant
bit
Figure 5-Data misalignment
necessary to establish the direction of phase misalignment and to add or subs tract a unit from the coarse
word accordingly. However, with the new I/O a bit
can be added to the coarse word merely by delaying
!he coarse-word strobe. Hence, an efficient and easily
implemented technique for data alignment is as
follows:
• Introduce a phase misalignment in the waveform
f1LJl. from the countdown of the coarse-data loop
such that the waveform corresponding to the
least significant bit from that loop lags the waveform corresponding to the most significant bit
from the fine-data loop by about 90°. Strobe the
countdown of the coarse loop as usual (on the
same clock signal as for the fine loop) if the overlap bits agree. Otherwise, delay the strob~ of the
countdown of the coarse loop until the overlap
bits do agree. (Clearly, this is not the only possible method of data alignment. It bears similarity
to a double-precision operation involving a carry
bit.)
The elementary I/O is in essence a new and powerful technique for measuring and encoding phase angles
of time waveforms. On this basis alone, without consideration of the additional processing and computing capabilities, the elementary I/O offers several
advantages over conventional phase-measurement
techniques.
Almost all phase measurement techniques require
the conversion of the phase-modulated waveforms to
rectangular or square waveforms which are in tum
used directly for timing measurements. In the new
I/O; as often in the field of radio telemetry, the conversion is made through the use of phase-locked loops.
In conventional systems for measuring resolver angles
the conversion to square waves is done through the
use of zero-crossing detectors, perhaps preceded by
band-pass filters. The phase-locked loop has a superior
capability to discriminate against noise (thereby
avoiding totally false readings due to multiple false
triggering of level detectors) and, in addition, avoids
errors that occur as 'a function of frequency shift in
direct transmission through a band-pass filter. The
new I/O broadens the area of application of phasetracking techniques long known in the communication
field.
Conventionally, the timing measureme)lts on the
square waves are performed by either of two basic
methods: One of the methods is to use a linear analog phase detector to determine the phase of the zerocrossing detector output with respect to a clock waveform. The phase detector output must then be filtered
and A/D converted to obtain a numerical representation of phase angle. This method relies strongly on the
linearity of the phase detector, and results in significant
dynamic errors due to the filter. The new I/O offers
the advantage of utilizing a nulled phase detector,
which need not be linear, and the advantage of greatly
improved dynamic performance. It also has the advantage of relative ease and simplicity, (and therefore
A New High-speed General Purpose I/O with Real-time Computing Capability
economy) of A/D conversion. The other conventional
method of processing the zero-crossing detector outputs is to use their rising and/or falling edges to start
and stop a counter that is driven by the reference
clock. The final counter outputs (at variable clock
times) are the encoded phase angle data. This method
is the open-loop counterpart to the strobing method
of A/D conversion used in the new I/O. In the new
I/O the counter is incorporated in the phase-locked
feedback loop and numerical angle data is obtained
at known clock times by the strobing process. Hence,
the elementary I/O combines the signal-tracking capabilities of the phase-locked loop with the capability
of synchronous angle encoding by the strobing process.
The new I/O has the additional advantage that it
can easily be generalized to perform a wide range of
simultaneous signal processing tasks that cannot be
performed as effectively by conventional schemes.
Advantages and computing capabilities of the new I/O
Sensor as part of system memory
One important capability of the new I/O is the
ability to provide synchronous whole-word data from
a single or multi-speed source without the requirement of memory registers. After momentary interruptions in power sources, communication channels, etc.,
the current data word is completely restored. In a very
real sense, the analog data source - e.g., the resolver
- can function as part of the system memory and is
an adjunct to the computer memory. Similarly, the I/O
is akin to an addressing mechanism for the system.
Equally important is the capability to perform simply and rapidly a useful set of computing (data processing) functions, which will be enumerated presently.
When a multiplicity of data sources are present these
computations are performed simultaneo~sly by the individual sections of the I/O, and the processed data
can be addressed serially, randomly, or otherwise, by
the GPe and/or by an off-line processor. In this manner the new I/O can take on a rather large real-time
computing load which otherwise would have to be
assigned to the GPC.
285
ing. In those cases real-time smoothing by means of
a GPe would require computations to be performed
at a frequency more than twice the highest important
frequency component in the power spectrum of the
angle data. The new I/O performs the filtering operation automatically on the phase-modulated waveforms
and thereby relieves the GPe of a rather large computing load that it is generally not designed to handle
in the first place. The general purpose computer remains free to alter the filtering time constants according to either a programmed or adaptive control law
by altering the parameters of the low-pass transfer
function F(s).
Time-derivative data
Often, particularly when the data is being used in
a control loop, it is desirable to obtain the time derivative of the variable being measured. When the
data represent mechanical angle the GPe is often
assigned to compute the derivative, a task which it
cannot efficiently perform at high speed. The new I/O
can provide the time-derivative (angular velocity) data
directly in the form of a shift in the VCO frequency
from its nominal value 2nf. Because both the frequency
shift and the nominal frequency of the transmitted
phase-modulated signal are magnified in the phaselocked loop by the factor 2 n (where n is the number
of countdown stages), the determination of the shift
can be made both accurately and rapidly. Many convenient and practical methods of measuring frequency
shifts have been developed over the years for Doppler
navigation, FM data transmission, etc. Any of these
can be used to obtain the encoded time-derivative
data. As an example, Figure 6 shows an analog frequency-difference detector followed by an A/D converter to provide encoded time-derivative data to
the GPe. An alternate rate signal may be derived from
the error signal to the VCO in the phase-locked loop
and the choice is a matter of signal-level and hardware considerations.
RESOLVER
Filtering
One type of data processing function naturally performed by the I/O is filtering. Because the phaselocked loops are tracking filters with limited b.~nd
widths, they serve not only to discriminate against electrical noise in the transmission path, but also to
smooth the angle data itself. This smoothing function
is particuiarly useful in the cases where the angle variations to te "smoothed out" are relatively rapidly vary-
TIME
~ DERIVATIVE
"---.......
Figure 6-The generation of time-derivative data
DATA
286
Fall Joint Computer Conference, 1967
Compensation of periodic instrument errors
Another type of computation that the new I/O·
can usefully perform is the removal of periodic instrument errors. Ideally the electrical phase angle of
the transmitted data is linearly proportional to the
quantity to be measured, e.g., shaft angle. Departures
from linearity are objectionable and are often called
"errors." However, the accuracy of the transducer may
be considerably greater than its linearity, in which case
it is desirable to remove the known non-linearity from
the data numerically or otherwise. Although this is an
extra and perhaps unwieldy task in real time for a
ope, the new I/O handles the task readily in the following JT!anner: Suppose, for example, that the lowest-frequency signal f~ in the phase-locked loop in
Figure 2a is multiplied (an "exclusive-or" operation on
square waves) by the signal filL from the clock. The
average value of the product is a triangular function
of the angle () and, hence, of the angle <1>. If this
product signal is added to the signal at the output
of the PSD in the phase-locked loop, the output data
angle 0 will be displaced from the input data angle
b ythe triangular correction function (here assumed
to be suitably small so that the effective gain of the
PSD can be considered fixed). Similar correction functions can be generated with different periods and
phase angles as a function of 0 by using different
frequencies and angle references in time, as indicated
in Figure 7. By using a set of correction voltages gen;
erated in this manner, essentially any nonlinearity
can be compensated for if it is a known periodic function of <1>. In this manner the binary angle (and angular rate) data is compensated for before delivery to
the GPe. The latter remains free, for example, to
oversee the correction process, perhaps to set adaptively the correction 'parameters, e.g., Kc and a in
Figure 7, which can be stored temporarily or permanently in the I/O itself.
In Figure 7 the square wave mf2
{
or
fl - f2/~1 -~2
Figure 8-Fundamental element of frequency synthesizer
Correction of phase delay as a function
of frequency
In some resolver applications, energy-storage mechanisms associated with the transmission path can
introduce a phase shift into the carrier waveform as
an approximately linear function of frequency. The
ne~ I/O can easily compensate for this phase shift,
WhICh can be considered as a dynamic phase error
by adding a small voltage from the frequency-differ~
ence detector to the voltage from the PSD as shown
in Figure 9. This type of correction, not easily handled
by the GPe, would be particularly valuable in applications where instantaneous angle data is desired from
a resolver rotating at high angular velocities.
Redundancy reduction
In many applications, the behavior of the phase
RESOLVER
f
flO.
other
frequencies
available L-.-+------....r;;:niiiNTrv:ill~
'--------.:J:.-.-I-----I COUNTDOWN
t'f~
Figure 7-Correction for periodic instrument errors
Figure 9-Phase correction as a linear function of frequency
*The technique, which is akin to single-sideband operations
and results in a felxible frequency synthesizer,4 was developed
by Edmund Foster and Kenneth Fertig.
A New High-speed General Purpose I/O with Real-time Computing Capability
and frequency of the incoming waveform to the I/O
is approximately known a priori, and the real data of
interest is the departure of the actual data from the
nominal data. Examples of this situation arise in a
number of Doppler~type navigation systems when the
approximate course of the vehicle is known from other
sources of navigation information. In such cases it is
useful to be able to reduce the computing load of the
GPC by subtracting the expected data in real time
from the actual data. This is easily accomplished in
the new I/O.
Suppose that the expected Doppler shift is Kif cps,
where Kl is some rational numbr less than unity. This
can be removed from the data by using a strobe waveform
fLQ EB K,fLQ == (1
K ,) fLQ
(3)
287
the strobe waveform in place of the .clock waveform as
an input to the frequency-difference detector, the redundancy reduction of the time-derivative data is also
effected.
The I/O can perform frequency correction also as
a function of the frequency of the incoming signal.
This is accomplished by letting the strobe waveform be
fLQ EB K,fLQ. EB K2f IK28
(4 )
as shown in Figure 10.
Figure 11 shows a functional diagram of the new
I/O with provision included for the computing options mentioned thus far. By placing the phase-preRESOLVER
F
+
where EB indicates the heterodyning operation in
Figure 8. If this strobe signal is used, and if the actual
data is equal to the expected data, the strobed binary
angle is a fixed number. Small deviations in the actual
data from the expected data result in slowly varying binary angle data. The GPC in tum has to process
only the slowly varying data, which contain the
significant information, and can ignore the rapidlyvarying unprocessed data containing redundant information on the already-known nominal path. By using
fLfl
Figure i O-Method of correcting frequency as a
function of frequency
V(cp)
Kc~
~m8
a 2".
FREQUENCYDIFFERENCE
DETECTOR
n
2 fLO
COUNTDOWN
mf/g
~--Ir---Io........ flO, ... , ~lO
mf/m8
FREQUENCY
SYNTHESIZER
Figure ll-Composite correction mechanism. The GPC controls
F(s), the frequency-difference detector, and the
frequency synthesizer
TIME
DERIV.
DATA
288
Fall Joint Computer Conference, 1967
serving frequency synthesizer under GPC control any
schedule of expected data may, in principle, be used
in the redundancy reduction process. Moreover, the
GPC may be used to perform a monitoring function
to determine the extent of redundancy and error reduction and to modify the synthesizer accordingly.
loop to obtain relative-angle data.
(3) Digital-differential-analyzer Ideas can be incorporated to allow products of data words
to be obtained.
(4) Generalized hybrid computation may be considered where the ladder networks of (1) are
excited by voltages related to real signals. Depending upon where the feedback loop is closed
with respect to input and ladder output,
analog multiplication, division, etc., can be performed as shown in Figure 12. If the ladder
is on the countdown, a continuous presentation
of data on a modified carrier may be obtained.
By using the mUltiplication and data-storage
capabilities, correlation of data can be performed.
(5) By incorporating logic circuitry in the clock to
allow generation of waveforms at independently
controllable phase angles, GPC outputs may be
phase encoded for subsequent processing by
the new I/O. The I/O could present the results in digital, analog, or phase-encoded form.
Other computing capabilities
The computing capabilities discussed in the foregoing are substantial but rather obvious once the basic
operation of the new I/O is understood. Many other
types of computations can be performed, and it is
likely that those mentioned are only the beginning of
a long list. Some of the other possibilities presently
under investigation are briefly summarizd below:
(1) Ladder networks can be used in conjunction
with the holding register to form linear and
transcendental functions of the strobed angle
data.
(2) A countdown in one phase-locked loop can be
strobed with a signal from another phase-locked
TRANSDUCER
fLcp OR
CLOCK fLQ
ANALOG
SIGNAL Vi
PSD
VCO
CONTINUOUS DATA
ON MODIFIED
CARRIER
fL9
LADDER and SUMMING NETWORK
STROBE
COUNTDOWN 2- n
GATE
EXAMPLE:
VO= e9 = Ke(Vi -Vf)
Vf = GVO, GKe
»1
HOLDING REGISTER
LADDER and SUMMING NETWORK
4
wl
1 •••
wn = ~
9 '" Vi
=eG
FEEDBACK
SIGNAL
Figure 12-HYbrid computer element
2nf/2rte
INCREMENTAL
OUTPUT
-~~RATE
A New High-speed General Purpose I/O with Real-time Computing Capability
Geaeralization: Instrument servo and new 1/0
The properties of the new I/O result from the action
of the VCO in the phase-locked loop. The properties
of the instrument servo of prehistoric analog computer days were largely dependent on the motor which
acted as an integrator in the sense that a voltage applied to the motor control winding resulted in an angular velocity, the integral of which is angle. Similarly,
the voltage input to a VCO controls frequency whose
integral is phase. In the old servo, the motor shaft
could ce loaded by tachometers, resolvers, synchros,
potentiometers, etc. In our phase-locked loop, the VCO
and counter may be loaded by FM detectors (note
that the loop error signal is the Doppler shift), ladders,
etc., as shown in Figure 12. Clearly, the similarity between the phase-locked loop and the instrument servois being stressed. From this similarity, all of the computing capability obtained previously with the instrument servo may be obtained from the electronic servo
- the phase-locked loop.
As a result of the preceding discussion, a further
generalization may be made which is incidental to the
discussion of I/O. The phase-locked loop is really
an accurate operational amplifier and the technique
may be used to make a family of analog computing
elements, servos, etc.
Hardware implications
The circuit elements which are used to make a phaselocked loop lend themselves to microminiaturization.
The developments in integrated circuits, and large
scale integrated arrays make hadware I/O improvements attractive.
Further, examination of existing I/O's for several
real-time computer/control systems shows that the system designers, in order to alleviate the computer dataprocessing load, have placed in the I/O adders, forward-backward dual-rank counters, A/D converters,
etc. The phase-locked loop, utilizing a forward-only
counter, etc., appears to lend itself to a building block
concept which represents no increase in hardware but
father a regrouping and a considerable increase in
flexibility.
CONCLUSION
A simple high-speed I/O with real-time computing
capability has been described. The I/O is particularly
well suited for performing high-speed calibration and
redundancy reduction on data received as phase modu-
289
lation on carrier waveforms, and for presenting the
p.rocessed data in a convenient whole-word binary
format for further processing by a general purpose
computer. The I/O is non-incremental in nature and,
hence, is completely self-restoring after momentary
equipment interruptions and can be adaptively manipulated under general purpose computer control.
The new I/O is a step in the direction of freeing
a general purpose computer in a real-time measurement and/or control application from high-speed but
routine data-reduction tasks (for which it is not well
suited) to perform computation, sophisticated monitoring ~nd adaptive adjustment tasks (for which it is particularly well suited) . Although the examples have
teen about inputs to the general purpose computer
from continuous sources, the techniques described
would apply to the generation of outputs from the
general purpose computer which commands or controls some element of a system.
The concepts of I/O have been generalized to
include the general problem of analog computation and
simulation and to lead naturally to hybrid computation techniques.
ACKNOWLEDGMENT
This report was prepared under DSR Project 5228611-22S sp.onsored by the Ballistic Systems Division
of the Air Force Systems Command through Contract
F04694-67 -C-0028 with the Instrumentation Laboratory of Massachusetts Institute of Technology in Cambridge, Massachusetts.
REFERENCES
L J QUAGLIATA
A sampling technique for the transmission and recovery of
phase-encoded information
Master of Science Thesis Massachusetts Institute of
Technology Cambridge Mass Instrumentation Laboratory Report T-428 June 1965
2 R, C TAUSWORTHE
Theory and practical design of phase-locked 'receivers
Vol 1 Jet Propulsion Laboratory California Institute
of Technology Technical Report No. 32-819 15
February 1966
3 F M GARDNER
Phaselock techniques
John Wiley & Sons Inc New York 1966
4 E FOSTER
.A circuit to perform frequency addition of square waves
Master of Science Thesis Massachusetts Institute of
Technology Cambridge Mass Instrumentation Laboratory Report T-475 January 1967
On designing generalized file records
for management information systems
by FRANK H. BENNER
Bell Telephone Company of Pennsylvania
Philadelphia, Pennsylvania
INTRODUCTION
The centrality of the files in a MIS (Management Information System), or in any other large scale computer
application, has been traditionally considered as selfevident. The new problems of operating systems and
the languages for use in the 3rd generation computers,
plus the relatively unknown world of integrated data
communications may tend to remove the files from the
limelight. This should be avoided. Most business applications will continue to be "file bound," or I/O limited,
even with random access to the data base.
A file reorganization to correct design deficiencies
can be catastrophic in its impact on programs that were
"on-the-shelf." The majority of the system hardware
cost is probably charged to file devices. The continuing
requirements for an optimum design for the complete
system is recognized and honored. It is suggested that
the search for this elusive design solution should begin
in the files area. Here the payoff is handsome for success, and the fiscal and operational deficit is unrelenting
for failure.
In a changing business environment, the mortality of
a special-purpose file organization is expected to be
high. The prudent approach for the designer is to make
no a priori assumptions about the way in which the data
base will be used, new uses will arise; or the limit of
the required descriptors, new data will be added. Both
R. v. Head 1 and W. H. Desmonde,2 while describing
different real-time systems, are strong in their emphasis
on file organization as a limiting factor on throughput
and cost, which requires rigorous optimizing techniques.
A new approach to file. design seems required which
takes advantage of the "naturalness" that may exist in
families of information. Paraphrasing Alexander,3 the
difficulties attended upon third generation computer
applications are much more subtle and complex than in
the past. As in the usual case, the temptation to fall
back on some arbitrarily chosen order or design tech-
nique is alIJlost overwhelming. But, if we continue to
apply essentially punched card or tape file design techniques to the direct access file problem, we will live
with essentially an unsolved problem and pay for the
designers comfort.
.
Design criteria
This paper reports on a method for analyzing the
logical record requirements and designing the physical
records to be housed on direct access storage devices.
This methodology has been followed in the Pehnsylvania
Company to design the file system for BIS (Business
Information System), a specific term used in the Bell
System to identify an indigenous MIS. This system is
characterized by large direct access files, a variety of
real-time activity to the files with "background" work
during the business day, and intensive and periodic
batch processing of the files on non-prime time. These
characteristics are, in many ways, similar to the corporate MIS for many businesses.
A MIS usually consists of two operational categories
of programs; real-time and batch. The file system to
support these processes must at least consider;
1. Security of information.
2. Recovery of system operation after failure, and
restoration of data when mutilated.
3. Key and Addressing schemes that will result in
densely populated storage.
4. Need for additions and changes to the data base to
meet changing requirements.
5. Performance requirements of all types of activity.
6. Reduction of wasted mass storage, consistent with
performance requirements.
7. Coordination of the file system with the programming system.
Of the above, security, recovery, restoration and addressing do not lend themselves to a universal treatment.
The speed requirements for recovery of operation and
291
292
Fall Joint Computer Conference, 1967
correction of mutilated data is not the same for all systems. Some can tolerate times in terms of days; others
demand action in minutes. Economics is also a factor
in designing for system assurance. Duplexed files are
expensive, but not always required. Each application
has its own unique security problems and scheme for
identifying records. The requirement for an optimum
file record is present in all applications however.
The record designer must be able to qualitatively
describe this optimum record before attempting his
work. When this record is designed, his search is ended.
The optimum record will:
1. Utilize the greatest amount of the space allocated
at the home address of the storage device.
2. Permit selection of data from within the record.
3. Be structured so that data fields can be added,
eliminated, and rearranged.
4. Identify records by using a logical description, in
addition to absolute identification.
S. Be as short as possible and yet, in the selected
length, supply the greatest amount of file data to
the programs in one "seek."
Logical record considerations
Most business applications will be dealing with a
logical record in the data base. In an Inventory Application, the logical record may be the set of all the subsets
whose elements contain information primarily about a
particular Piece Part. In an Order and Billing Application, the logical record is usually a Customer Account.
With a total systems approach as used in a MIS, those
applications which were previously separate bounded
systems, now are subsumed into the MIS or are subsystems. If we were to arbitrarily retain the demarcation
between ~ay, an Inventory System and an Order and
Billing System in an MIS environment, there would be
unnecessary redundancy of data and a high likelihood
of subjectively favoring one of the subsystems of the
MIS at the expense of the others.
The amount of information making up a logical record is usually not homogeneous throughout the universe
of the records. Some of our inventory items or our customers are more active or larger than others. Thus, the
logical record size will most likely vary. We could make
each physical record the· size required to accommodate
information in our largest logical record. This would
give excellent performance, but low utilization of storage
would result. We could make our record length cater
to the "average." This would give us good storage
utilization. Since it is usually the larger and complex
entities that are most active, "average" record length
results in lower system performance. A disciplined ap-
proach to record design is required to properly weigh
all factors.
Attributes of record components
Analysis of the natural components of a logical record is aided by the diagram, Logical Record Components, Figure 1. We see that a Logical Record is the
superset of functionally related Main and Auxiliary
Records uniquely identified with a particular entity. The
subsets of the Main and Auxiliary Records are the
Data Segment(s) and one Record Control Segment. A
Data Segment is a collection of fields that cover a particular aspect of the Logical Record. Then, the elements
of the Data Segment are Data Fields, with possible
intersection shown. Each Logical Record has one Main
Physical Record and zero or more Auxiliary Physical
Records, depending upon the amount and kind of data
making up the record.
There has been an increased interest in memory
svstems where information is stored or retrieved on the
b~sis of content. This is in contrast with using specific
addresses to reference locations containing data that
must .be examined. This rationale is generally referred
to as being "associative" in orientation. 4 Since about
1961 the term "associative criterion" has been used to
define the list of descriptors for the desired group of
data or record. In this context an item for/of entry in
an associative memory is described by as many characteristics as are required. The object record is located or
identified at the intersection of all these descriptors.
Using the associative philosophy of the memory system
designer, it is a short step into a new logical organization
for file records. s Each record can still be specifically
identified, but it also may be understood from the associative logical criterion. Each set of descriptors then
describes an object, but the object described is not
always congruent with only one specific record. This
idea permits the accommodation of more than one logically consistent file in the same physical file structure.
The value of such an organization is its generality of
logical flexibility.
Fitting the physical records into such a file requires
an examination of the record elements. In a direct access record, the basic building block is the data field.
Close ties between fields are reflected by the creation of
data segments. We must know specific information
about the data fields so we can determine the particular
components of an optimum main record These attriLutes relate to:
1. How often the field even exists to contain significant data?
2. When it does exist, how long is the field?
On Designing Generalized File Records for Management Information Systems
293
LOGICAL RECORD
/RE\
MAIN PHYSICAL
RECORD CONTROL
SEGMENT
CONTROL
FIELDS
nth AUXILIARY PHYSICAL
/C\
1st DATA
SEGMENT
DATA
FIELD
DATA
FIELD
RECORD CONTROL
SEGMENT
DATA
FIELD
DATA
FIELD
DATA
FIELD
CONTROL
FIELDS
nth DATA
SEGMENT
DATA
DATA
DATA
FIELDS FIELDS FIELDS
Figure I-Logical record components
3. How often is the field required when the Logical
Record is processed?
4. When it is required for use, what other fields are
also needed?
The information pertaining to how often a field significantly exists aids in attaining efficient use of storage.
The length of a field and its variance help determine the
use of storage, and how often the system will be required
to access "overflow" data. The way in which, and how
often, the data is used in servicing transactions or processing requirements will permit a design that lets each
application "stand up and be counted" on its true need.
These facts about a mythical record are shown on
Data Segment and Field Attributes, Figure 2. Each
column on the chart contains specific information about
the data field or data segment that appears on a particular row. Note that Segments A and D have no
component fields shown. This is because the fields are
a tight family, (exist with practically the same probability and level of activity) so they are considered
as being one large field. The column headed Prob.
refers to the probability that the field will contain significant data in the Logical Record.
(1)
where:
E is number of Logical Records in which ith
field =1= 0,
and:
N is number of Logical Records in the data
set
The Mode column refers to the characteristics of the
field in terms of being fixed (F) in length or variable
(V). In fixed length cases, only the Min. column is
used. The details of how a length varies are required
only for variable length fields or segments. This is
done by expressing the field length and frequency as
a series of coordinates in the columns under Data
Length headed Pt. 1, Pt. 2, Pt. n. In these columns, L
and f (L) are shown for the variou·s points. The Min
column pertains to the shortest length the field was
found to have.
Activity on the system is expressed on Figure 2 in
terms of the frequency of need in a given time period
for the particular fields and segments. The Real-Time
column pertains to the transactions to be conducted
in real-time. In the illustration, two different kinds of
real-time transactions have been shown.
Type 1 requires Segment A, Segment B Field 1,
and Segment C, Fields 1 & 2
Type 2 requires Segment A, Segment C Field '1,
and Segment D
The Batch column refers to the requirements for
294
Fall Joint Computer Conference, 1967
Field or
Segment Name
Data Length
Pt.
Pt.
3' •
2
Pt.
1
Processing
Volumes
Real Time
Batch
..!.--2
1
2
Activit~
Pt.
n
Probe
Mode
Min.
1. 00
F
10
10
F
10
5
10
15\
10
10
F
Fld. 1
Fld. 2
10
F
F
V
Key #1
10
Key #2
(10,10)
Key #3
(50,7)
15
10
20
10
10
15
10
15
10
20
20
Key #4
Figure 2-Data segment and field attributes
information to meet these similarly appropriate needs.
The volumes shown must be taken for the same period
of time. Total activity to a Segment or Field is simply:
n
n
E
L
i=1
where:
RT,
+
L BTCH
J
(2)
j=1
i is a real-time transaction
j is a batch transaction
E is > 1
and:
At is. Total Weighted Activity
The strategy to be employed later will involve certain
computations that use the length, probability, and the
activity for each of the data segments. Most of these
file systems must serve both real-time and batch
processes.
If the file is to have no particular orientation, all
of values L, P, and A can be used as they are found.
If there is to be an orientation toward the real-time
requirements, the records should be so designed. The
factor E in the above equation (2) is used to effect
this orientation. It is a number, proportional to the
relative importance of the real-time activity. Arriving
at this value is similar to assigning the priority or the
transaction limits for the use of the control package
or operating system. For instance, the control program
might be arranged to permit a limit of say three or
four real-time transactions to be served and then one
tackground transaction. This same limit can be effectively used as E.
From an examination of raw activity, shown on
Data Segment and Field Attributes, Figure 2, and, if
we wish to emphasize the influence of our Real-Time
activity by E = 2 as discussed earlier, equation (2),
we have weighted values:
Segment or Field
Segment A
Segment B, Field
Field
Segment C, Field
Field
Segment D
*Total Activity
Weighted
Real-Time
50
20
1
2
50
1
20
2
30
Batch
30
10
10
30
20
10
At*
80
30
10
80
40
40
By using this Total Weighted Activity, along with
the related probability and the length we will be able
to evaluate the relative importance of a field or segment.
Utilization of mass storage
The designer faces an implied constraint in the
form of the economic use of storage. This is evidenced
in his reluctance to provide space in the record for
fields that'" occur infrequently. In tape records, this
problem could frequently be taken care of by the placement of these fields where "zero suppression" could
keep the tape record shorter if the field contained
no significant data. In direct access devices there are
as yet no such aids, so the decision cannot be so easily
determined. The designer must have an objective in
terms of storage utilization. Storage utilization is simply the probability that a position in storage will
contain significant data.
Fixed length data fields
From the data on Figure 2, the designer has no problem with fixed length Segment A and Field 1 of Segment B, since there is a P equal to 1, Key # 1. This
tells him that they always significantly exist. The P
for Field 2 Segment B, and Field 2 Segment C, Key #2,
with P equal to .55, p.resent a dilemma. If his objec-
On Designing Generalized File Records for Management Information Systems
tive is a utilization say of .70, the designer is tempted
not to reserve space for these fields. This is fallacious
if we consider only the lengths of the fields, since if
a field might not exist, the problem programs must
be able to test a control field associated with the object field to see if it is present.
Pan6 in his pioneering work provided useful formulae
for applying linear programming techniques to help
solve the record design problem. In this particular example, after Pan, we can test the fixed length fields
Field 2 Segment B, Field 2 Segment C, Key #2, and
determine if we should always provide space in our
physical record for these fields. To do this, the term
Weighted Storage Utilization is used which is essentially the probability for the field, weighted by the ratio
of a control length to the data length of the field.
LI+C
(3)
LI
where: LI is the data length of the ith field
PI is the probability of the ith field
C is the length of the control field used in
the programming system.
If the programming system requires 3 digits for control to provide field identification and length, we have
for Field 2 Segment C, on Figure 2:
WI
==
LI ~ C (PI)
15
t
1
utilization of storage, is more complex. Here, in addition to treating the probability of the field, we also face
the problem of deciding on a data length to provide
on the first "read" of the record containing the field.
Most methods of organizing records for direct access
devices use a "chaining" or "overflow" address when
data exceeds the space initially allotted. This "chaining
address" field, incidentally, should be treated as any
other fixed length field since it significantly exists only
when overflow exists. The use of the additional detail
on variable length fields is fairly obvious. It wlll be
used to produce a probability function for each particular field. The skew present in a frequency distribution
of the data has shown this essentially social data transforms, with good fit, into a form of the Gompertz
Curve. 7 This curve fits well into a probability function
where we encounter the probability showing an increasing ratio of decline as field length increases, but the
ratio is not changing by either a constant amount or
percentage. While this curve:
bX
Y == ka
(4)
is mathematically attractive, it cannot easily be managed for solution and integration in a digital computer.
Raw data is used directly for this purpose.
'The need for integration is to develop the storage
utilization for variable length data. Recall that this is
the probability that a position of allocated storage will
contain significant data, or the ratio of the allotted
area to the occupied area. For variable length fields:
3 (.55)
n
L
.66
i
where:
L
15 per Key # 3, Figure 2.
For Field 2 Segment B, on Figure 2:
WI
5
t
3 (.55)
.88
where:
Li
5 per Key #4, Figure 2
Assume the rule, "Always allot space for data in the
physical record when the Weighted Storage Utilization
of the field equals or exceeds the design objective."
Recalling our objective of .70, space will always be
provided for Field 2 Segment B, WI == .88; but none
will be reserved for Field 2 Segment C, WI == .55. If
the application programs are "process" limited, borderline cases may be judged accordingly. This is due to
some additional processing that is required to locate
data using a control field, rather than by direct use of a
"label" that designates specific positions in memory.
Variable length data
The problem with variable length fields, in terms of
295
where:
== °
f(LI)dL+ C
(5)
a particular variable length field,
LA is length of allotted area, and,
C is the length of chaining address. data .
Morses treated a similar problem in computing Mean
Service Time by using Taylor's Theorem. While our
problem is not one of queues, it can be treated in a parallel manner. Figure 3 is a graph of the Probability
Function of a Variable Length Field. First, consider the
probability that the field length, for any record in which
the field appears, is greater than length L. This is the
difference between the probability that the field will be
of length (L) and (L + dL).
1 IS
P(L)-P(L+dL)
= P(L)-P(L)- ':L dL =
(6)
p(L)dL
00
,where: peL)
== -
dP or
err:-
peL)
==
J
o
p(L)dL
296
Fall Joint Computer Conference, 1967
1.0
Freq
Prob
1.0 -.,--~.....
.9
Probability Density
that Segment Dis
~ Length L
.8
Probability (P)
.7
.6
50
dL
Lm
Length (L)
Frequency Distribution
of observed data
.5
40
.4
30
.3
20
.2
10
.1
Pt. n
5112233445
050505050
Figure 3-Probability function of a variable length field
This quantity peL) is the probability density that a
field is of length L. This is a rate or change in probability per length. Then peL) is a measure of the mean
rate at which Fields are meeting the length (L). The
average length of the fields is:
Data Length of Segment D
Figure 4-Functions for segment D
Applying this result to equation (5) for Segment D,
and assuming "C" equals 3 digits,
J
00
n
L p(L)dL
f(LI) dL
o
00
--_····_(P I )
LAI
00
+
[ L P(L)]
o
J
56
P(L)dL
l:.?
0
P(L)dL
(7)
o
where: Lm is the average length.
Discarding the quantity in the square brackets is
justified since it is zero when (L) equals zero; and when
(L)~ 00, peL) has already reached zero for all practical
purposes.
Using the Trapezoidal Rule for approximation of the
definite integral of the Probability Density in Figure 4,
Functions for Segment D:
xn
A:::::
J
f (x) d x
(8)
Xo
dx
-
2
5
~
2
(Yo
+ 2Y + 2Y + 2Yn- + Y
:::
1
2
1
+ 2 + 2 + 1.88
+ 1.52 + .96 + .54
+ .38 + .26 + .16 + .04)
(1
5
'""'"
(9)
3 (1.00)
.60
00
J
+C
(10.74)
2
26.85 ~ 27
n)
This would be true if LAI is set equal to the maximum length the field was found to have. Therefore, the
length of the allotted space should be reduced until WI
equals the objective, if possible. Through an iterative
process we arrive at:
462 (1.00)
WI
==
26
Wi
==
.72
(10)
So that if we allot 40 characters to Segment D, we
will have a Storage Utilization of .72, the field will
always appear in the physical record. From Figure 4,
Key # 1, the probability that Segment 0>40 characters is .12 or; about 12 % of the times Segment D is
required, an additional read would be required to secure the excess data. The number of device read commands that must be given to completely satisfy the need
for specific data is an important factor on through-put.
Therefore, it is necessary to keep file action to a minimum. The ability of a file record to meet the needs for
data is expressed as "Performance," and is calculated
as follows:
(11)
On Designing Generalized File Records for Management Information Systems 297
where:
(12)
n
~N,
i == i
Record design strategy
Where:
SI is a Data Segment provided for in the combination C r being rated for Performance, and,
P (Cr) is the Performance of Cr.
Where:
i is the number of different segment combination required by transactions.
N is the number of times a particular combination is requested by processing needs.
and:
HI is a "hit" factor
HI == 1 if all required segments are found
with C r
HI == 0 if one or more of the required
segments are not with Cr
Example:
C == {a, b, c, d, e} is the combination being rated
for the main physical record.
The different combinations requested:
1
2
3
Processing
Volumes
HI
Combination
HI
H2
H3
{a, b, c,}
{a, c, e,}
{a, b, f,}
1
1
0
1
2
3
== 50
== 40
== 10
then:
n
i
P(Cr)
~
H,N,
== 1
(13)
n
~
i == 1
(1).(50)
N,
+ (1).(40) + (0).(10)
+ 40 + 10
50
90
100 == .9
Storage Utilization is a similar rating that measures
the expectation that a character position of storage
will be occupied by useful intelligence from the data
base.
n
SU -
i
~
L,W ,
== 1
(14)
n
~
i
== 1
L,
L, is Segment length
WI is Weighted Storage Utilization for the
segment
The designer will naturally attempt to produce alternate main record designs that will differ in:
1. Length
2. Performance
3. Utilization of Storage
There are a number of techniques that efficiently
utilize available storage addresses. 9,lo In this strategy,
we attempt to make the best use of the capacity available
at the addresses. The combination of segments chosen
for the Main Physical Record will determine the number
of times that required data is not initially available to
the system activity. In this procedure, the designer first
expresses these factors:
1. The length of the control fields to be used by the
Programming System for Variable Format Fields
(Figure 5, Memory Map of Data Segment, Fields
I. and L,),
2. The length of the chaining fields when used for
variable length data.
3. The factor "E", as discussed earlier, gives emphasis to real-time activity in the design.
The basic strategy is shown on the flow chart on
Figure 6, Design Procedure. When the Weighted Storage Utilization is low, most fields will be made fixed in
format, and variable length fields will seldom require
a second access to overflow. The record will be long
and the Storage Utilization will be low. For each value
of Weighted Storage Utilization there will be some
length where the Performance is acceptable. The designer then plots these Performance and Storage Utilization results for each of the feasible lengths. The optimum record length is selected for implementation; the
contents of the record is the combination of segments
used to develop the selected results. On Figure 7, Graph
of Performance and Storage Utilization, is shown the
plot of Performance (solid) and Storage Utilization
(dotted) that were generated from information for a portion of the BIS File System.
As record length increases, Performance increases
since more· segments are present in the record. Conversely, Storage Utilization decays since data with
lower P are being included. There is a minimum performance that the selected record length must provide.
The decision on exceeding that length is a tradeoff
between the increase in performance that will be enjoyed, versus the decrease in the utilization of storage
that will be encountered. For instance, on Figure 7, if
298 Fall Joint Computer Conference, 1967
CASE 1
All variable format
fields present
Fixed Format
Fields
SL
= 120
1-----------r-----r-----,--,---------1
+1
I
n-l
EI+l
EL
L
n-l
n-l
Variable Format
Fields
CASE 2
Variable format
field (i+l) missing
SI·
S~j
==
Segment Identity
= Segment Length
n
SL· = ELj+~ Li
J
i=l
ELj = Fixed format field
edit length
I i = Variable format
field identity
Li = Variable format
field length
ELi = Variable format
field edit length
SL = 112
Note: Cross-hatched
memory position
indicates last one
of segment
Figure 5-Memory map of data segment
On Designing Generalized File Records for Management Information Systems
Develop Total Activity
At for each field and
segment.
l
Assume an objective for
Weighted Storage Utilize
W = .01
~
USing Pi and Li' compute
Wi for each field and
segment.
~
Determine format of data
based on results.
~
Select length of shortest
r--+
segment for first trial.
t
Compute P(C r ), S U, and
~
Record Length for the best
Cr·
~
Select next greater feasible Record Length.
~
Increase W to next multiple of 5.
~
Completed when W = 1.00
Figure 6-Design procedure
299
300
Fall Joint Computer Conference, 1967
a minimum Performance of .90 is required, the length
of such a record will be 600 characters. If the . next
feasible length is 700 characters, the decision to use this
length is based on the absolute change in Performance
and in Storage Utilization. A useful rule is to subject
the change, or Gain ratio to a slope test:
G
==
~P
~SU
.02 == .4 If G >
== ---:os
=
1, take next length
(15)
There are times when certain solutions might be ruled
out ·due to address breaks, device constraints, and economics. This action should only be taken after the
theoretical solution is found. These techniques may be
difficult to use without some computer aids. Most
designers will have a linear programming package available to them, or can have one written. Many of the
ideas in this design method appear in a programll available from the IBM Corp and used in the Pennsylvania
Company. Certain restrictions and specific understandings are in force when it is used.
After the contents of the Main Physical Record has
been decided, the rest of the logical record will be in
the Auxiliary Record(s). These records will contain seldom used data and the excess of the variable length
data from the main record.
1.0
A = .02
.9·
.8
... •••••
.7
,
~---
.6
.5
Utilization
.3
.2
.1
400
800
1200
n
SLj
L
== EL +
ELI
(16)
i == 1
The field designated EL is used to show field length
and certain edit information. Note that Case 1 is longer
than Case 2 for the same segment, on different records.
It will also show the mode of the data:
Packed Decimal-Unsigned
Packed Decimal-Signed
Binary
Eight Bit etc.
j
All this information will be used by the File Interface
Program to be discussed later.
Recall that each physical record will contain a Record Control Segment and one or more data segments.
Within the R~cord Control Segment, Figure 8, Memory
Map of Physi~al Record are fields to show the length
(RCL) of this segment, the total length (RL) of the
record data on the track, and the address of Auxiliary
Physical Record(s). Figure 8 shows the record and some
of the fields mentioned. It can be seen that:
n
A = .05
... ................
\ Storage ......••••••••.
.4
programming system. A fairly representative selection
of storage devices12.13.14 show a variety of capacities and
speeds available. Capacity and high cost has been softened as a limit. On Figure 5 is shown how a segment
will appear in main memory after it has been read from
the device. Each segment must carry its identity (Sl j ) ,
or, type of data it contains. The total length of the
segment (SLj ) must be shown for programming housekeeping. The segment length is a function of the length
of the fields present.
1600
Length
Figure 7-Performance and storage utilization
Programming considerations
Until now there has been emphasis on storage utilization, throughput and efficiency. However, it is necessary to place the resulting record in the context of the
RL == RCL
+
L
SLj
(17)
j == 1
All Record Control Segments in the file system are
managed the same way. After a record is read into
memory, the start of the Record Control Segment will
always be known. By looking at field N, the programming system can initialize to handle the number of
segments possible in the subect file record. This is an
aid to setting up "looping limits." Any segment can be
located in the input area by referencing the positionally
significant segment bit (SB j ) that pertains to the desired
segment. This bit has two states:
Set == the segment is present in the record.
Reset == the segment is not in the record.
When the bit is found "set," reference is made to the
associated Displacement Field (DJ) for the segment.
This field contains the numcer of positions away from
the start of the record where the segment is found. By
consulting control fields in the segment any data can
be secured.
On Designing Generalized File Records for Management Information Systems
RCL
Jl
Record
Control
~==~==~~~~J-~~~~~~~=-~~--~D--~
r-______________________~~~~~~~_L~n~~ }
OTHER DATA SEGMENTS
Dj
Se~ent
RCL is length of
Record Control
Segment
RL
RL
301
is length of
recorded date
Aux. Rec.
Addr. is address of
Auxiliary
Physical Record
jth Data Segment
N
is number of
(SBj, Dj) in
control segment
OTHER DATA SEGMENTS
wasted
track
End of
allotted
track
Figure 8--Memory map of physical record
302
Fall Joint Computer Conference, 1967
In many business applications there is a constant
need for studies of the file records. Frequently the records desired are not known specifically, but will meet
certain criteria. This is the need for an associative capability. By placing the Record Control Segment in the
Key Area of the record, the records can be located using a simple key scan program. This way the entire
record does not need to be brought into memory. If the
Record Control Segment is not placed in the Key Area,
the entire record must be brought in, but the logic remains the same. By using the Segment Bits (SBj) Figure
8, in a register, simple Boolean Statements will identify
the desired records without lengthy special coding of
"compares and branches."
There are many ways in which the contents of the
data base in a MIS can be developed. Unless a discipUned approa,::h is used,15 subtle duplication or omission
of data may result. Earlier, it was mentioned that the
mortality of special purpose files is expected to be high.
This is in part due to the changing needs of the business
enterprise. New information must be entered into the
data base. There is always a healthy concern for existing
programs when the file is changed. By having the file
record itself contain information about where data are
located and making it relative, the impact of change
is kept to a minimum.
Most programming systems will provide for the "linking" together of various subroutines. Since we can have
a general way in which data can be extracted from a
file record, it is natural to· have a generalized routine
written once. On the project where these techniques
were used, the name used for this routine is File Interface Program (FIP). This program requires only the key
to the desired record and a mask of the requested data.
It is written in "tight" coding, which translates an efficient but complex file record into a simplified record
for use of programs written in COBOL. It relieves the
problem programs of all file reading and writing responsibility. Problem programs need no knowledge of specific locations of file data. As the system evolves, the
value of FIP is expected to be even more apparent.
Application comments
Information about BIS is generally available16 and
has been discussed at several industry conferences. In
the Pennsylvania Company, some of the phases of BIS
have already been implemented. The techniques described here were developed to design the file for BIS.
Earlier in 1967, the first real time aspects of the system
were placed in service on a trial basis. The File Interface
Program, written in assembler language, is serving the
inquiry programs that retrieve data on customers' accounts for the use of Service Representatives. This inquiry takes place while the representatives are convers-
ing with the customers, so there is a need for a fast
response. The file system is list structured. Some data
sets are "threaded." Others are based on the Multi-List
System or on the Inverted List technique depending on
the operational characteristics which are required. The
management of the keys and the interior of the record
makes this diversity possible. Presently, the file system
contains only those segments which are required for the
real time and batch processes active today. As additional segments enter the file due to new work to be
done, FIP should preserve the investment in existing
application programs.
These problem programs were written in COBOL to
give a high degree of transferability. The data mode and
organization of the file record is one that conserves
storage, tut is not suitable for direct use with COBOL.
Therefore, the interface program edits and code translates the data to an eight bit mode. Initially, the file
device used for the massive data base is the IBM 2321
Data Cell. When or if there is an increase in the use of
the file beyond the performance of this device, the same
records will be transferred to a faster device without
serious reorganization. The record length will be chosen
in accordance with the principles discussed, but there
will not be changes to existing programs. In fact, due to
shipping schedules, initial program testing was done on
an IBM 2311 Disk using the same record discipline. An
additional advantage of the optimizing techniques was
in the form of providing input to the simulation models
of the file system. The design loop was one of data
colle:tion, .pre:iminary file design, simulate, analyze results, modify design, simulate, analyze, etc.
These techniques have served well. The massive files
enjoy a Storage Utilization of 65 %. The actual record
length of the Main Physical Record is down to 796
bytes; froIR early designs, not using these methods, of
1800 bytes. A more favorable balance between file
processes and application program time exists. This
ratio is (l: 1.2). The informal objective of a mean response Time of 10 seconds for inquiries has been met.
The distrLution of response times is shown on Figure 9,
Inquiry Response Times. This data is taken from a
GPSS (General Purpose Systems Simulator) model that
was used in the design effort. It has been validated by
empirical measurements of reality and is deemed conformal.
Fundamental thinking still takes place in the whole
problem of data management. The functions performed
by FIP seem to lead to a solution using either:
1. Macro Statements-given in the application programs that would be assembled along with problem coding. An expanded GET. (Example: GET
File Name, Record Key, Segment Name 1, Seg-
On Designing Generalized File Records for Management Information Systems
ment Name 2, Segment Name n.)
2. Read Only Storage-- the coding of FIP could be
placed here with obvious savings. In effect, a
. privileged command, or ROS MACRO
Inquiries
40%
35
30
25
20
15
10
5
2
4
6
8
10
12
14
Response Time in Seconds
16
18
Figure 9-Inquiry response time
It is felt that File Spread Sheet Analysis or intuition
would not have produced results as satisfactory as the
current design. These techniques are the only ones that
seem to properly consider data length, probability, and
activity in determining the record design. Other schemes
fail to consider them all, or treat some of them casually.
ACKNOWLEDGMENTS
The work described here represents the contribution of
many other than the author. Much of the numerical
analysis work was built on a solid base provided by Mr.
George Pan, of the General Electric Company, Schenectady, N.Y. Messrs. Robert Lanham and Jack Lauback
of IBM at Kinston, N.Y., contributed many ideas or
participated in application of these techniques". Mr.
Richard S. Kaufman of IBM at Philadelphia, Pa. pro-.
vided the needed counsel for the associated simulation
effort which was imbedded in much of this work. Mr.
James Weisbecker of the Bell Telephone Company of
Pennsylvania was responsible for the demanding application of the files and the development of FIP as a
working program. This recognition can only understate
the value of their individual talents to the work reported
here.
303
REFERENCES
1 RV
HEAD
ReaL-time business systems
Holt Rinehart & Winston Inc New York p 78. 79
1964
2 W H DESMONDE
Real-time data processing
Prentice-Hall Englewood Cliffs N J p 107 1964
3 C ALEXANDER
Notes on the synthesis of form
Harvard University Press Cambridge Mass p 1-5
1964
4 G J SIMMONS
Application of an associatively addressed distributive
memory
AFIPS Proc vol 25 1964
5 E W FRANKS
A data management system for time-shared file processing etc
AFIPS Proc vol 28 1966
6 G SPAN
Linear programming method for optimum file design
Unpublished Master's Thesis Syracuse University
N Y 1965
7 F E CROXTON D J COWDEN
A pplied general statistics
Prentice-Hall Englewood Cliffs N J p 302-303 1955
8 PM MORSE
Queues, inventories and maintenance
John Wiley & Sons New York N Y p 9 1958
9 W W PETERSON
A ddressing for random address storage
IBM Journal of Research and Development vol 1 no 2
1957
10 W P HEISING
Note on random add~essing techniques
IBM Systems Journal vol two 1963
11 The weighted record analysis program users guide
Un-numbered Communications Industry Marketing
IBM Corp White Plain" N Y 1966
12 Introduction to IBM System /360 direct access devices
and organization methods
C 20-1649-0 IBM Corp White Plains N Y 1966
13 Random access devices series references manual
70-06-500 RCA Camden N J March 1966
14 Series 200 summary description-file storage units NP7099
15
16
Honeywell Inc Wellesly Hills Mass 1965
J C MILLER
Conceptual models for determining information requirements
AFIPS Proc vol 25 1964
Business information systems
American Telephone and Telegraph Company New
York N Y 1965
The planning network as a basis for
resource allocation, cost planning and
project profitability assessment
by H. S. WOODGATE
International Computers and Tabulators Limited
London, England
INTRODUCTION
The planning network is well established as a tool for
the planning of projects, and its usefulness as a catalyst
for both time and cost control has been demonstrated.
However, the task of management involves consideration of other factors besides merely time and cost.
The overriding objectives of most commercial organisations are to make a profit, to maximise that profit and
to obtain that profit from the deployment of available
(or acquirable) resources. The basic planning problem
is, therefore, how to decide between alternative ways
of using resources such that the best profits are obtained.
These decisions are perhaps the most difficult that
iT anagement have to face. It is often necessary to make
decisions which will affect a significant proportion of
the organisation's money flow for many years ahead and
to make those decisions at a time when there is a
paucity of sound information upon which to base them.
Previous experience is often used as a basis of evaluation but as technology advances new projects become
more complex and previous experience has less relevance.· Simultaneously, competition becomes more fierce
and it is increasingly necessary to evaluate cash flows
accurately so that adequate (but not uncompetitive)
profit 'margins can be maintained.
It is particularly true of projects where the investment and revenue is spread over several years that
the traditional methods of comparing average annual
income with total investment are no longer sufficiently
accurate to guide the present day decision taker. Project evaluation methods are required which take account of time in conqunction with investment and revenue, so that investment decisions can be made based
upon a realistic appraisal of the relative economics of
alternative policies.
Two developments have recently appeared upon the
commercial and industrial scene in answer to the de-
mand for more accurate financial evaluation of projects. They are the perfection of planning networks, or
arrowed diagrams, as a basis for resource allocation
and profit planning, and the widespread use of electronic
computers capable of rapidly analysing these networks.
The logicality of the planning network and the speed
of computer processing enable management to test
alternative plans and different degrees of planning detail before embarking on major forward planning decisions.
It is, however, unrealistic to expect a computer program to give in a single calculation, a "black box" type
of solution to a large complex planning problem involving many estimates and many imponderables. The
computer will predict (according to the rules it knows),
but management judgement can often enhance these
predictions by guiding the calculation along preferred
paths. For this reason, the most effective way known
so far towards accurate project profit forecasting involves a combination of managerial judgement (to
specify the areas of uncertainty) and computing power
(to analyse the impact of uncertainty upon factual
data). In such a system the computer becomes an extension of the manager's intellect and is used in the
way that a manual worker uses a power tool.
This approach marks an important distinction from
some earlier experimental systems in this field, where the
Figure I-The planning systems pyramid
305
306
Fall Joint Computer Conference, 1967
computer program attempted to provide one single
answer, the value of which entirely depended upon the
relevance of the programmed decision rules to the project situation being analysed.
In this paper, an approach to profitability assessment
is described through the stages of resource allocation,
cost planning and profit evaluation. In the system
described, the managerial decision process and risk
assessment interacts with the preset programmed decision rules in such a way that solutions are reached
which exploit 'to the full any innate managerial wisdom.
This method can ce "onsidered as a step by step approach and the various stages are as shown in Figure 1.
The foundation of this "planning system pyramid" is, of
course, the project specification· and progress towards
profitability and financial risk assessment proceeds
through the steps of network construction, time analysis,
resource aggregation, resource allocation, and cost
analysis. Many of these stages interact and in some
cases the inter-action can be delegated to preset decision rules. However, it is a main premise of this paper
that many of these inter-actions are managerial decisions
and as such should properly be under the direct control of project management. The early steps on the
pyramid have been amply described elsewhere and
this paper concentrates mainly upon resource, costs
and profit planning.
After setting up the planning network and time
analysing it in the usual way, the next step is then to
consider alternative ways in which resources can be
deployed to achieve the physical completion of the
project.
Planning resource requirements
The planning network will have yielded at this stage
a preliminary estimate of the total project time required
and the criticality of individual activities indicates ways
in which improvements can be made. However, the
execution of the project' requires the deployment of
men, machines and materials and these invariably fall
into a hundred or more non-interchangeable categories.
Often too, the amount of resources available is limited,
or for economy reasons must be held at a steady
level of utilisation.
In planning resource requirements, therefore, the following key questions have to be answered:
.1. What are the total resource requirements for a
project over its duration?
2. What is the minimum delay to the completion of
the project when insufficient resources are available?
3. What is the most efficient utilisation of re.sources
to carry out the project in a fixed time?
Inspection of a network time analysis will quickly
indicate that, even with resource information available,
finding the answers to the above questions is a formidable undertaking without the aid of a computer.
However, once resource requirements have been
added to individual network activities, it is a relatively
simple matter for a computer to aggregate the resources
required over the time span of the project, to show
the total requirement of each type. If the computer is
also given a statement of the resource availability, comparative statements can be produced which indicate the
resource requirement! availability situation, thus giving
project management the answer to the first question.
Resource aggregation
The resources for activities on the critical path are
accumulated in the time period allocated to each critical
activity. For other activities having float time available,
however, there is a choice between aggregating resources at the earliest time or the latest time.
Figure 2 shows the typical effect of these alternatives. In Figure 2 (a) the resources required for the
simple network shown have been aggregated at the
earliest time which can be allocated to each activity
and in Figure 2 (b) resource requirements. have been
aggregated at the latest time each activity can be scheduled. A resource availability level is also shown and
it is seen that in both cases this has been exceeded.
Assuming the extra resource requirements could be
met, it would most probably be at some extra cost (i.e.,
overtime working, sub-contracting or engaging temporary staff). Also it will be noted that available resources
are unused for some part of the time and thus further
costs are incurred which are additional to the 'productive labour involved. Both these schedules (earliest
or latest) are, therefore, likely to be high cost schedules
due to the inefficient use of resources. Thus instead
of merely aggregating resources against previously determined time schedules, it is necessary, if minimum
costs are sought, to allocate the work to be done against
the resources available.
Resource allocation
The planning network provides an ideal basis for the
allocation of resources, as the network itself defines
the sequence in which the work must be carried out
and the tirre analyses show, by the amount of total
float, the relative priority attached to each activity .
The general method used in resource allocation is to
commence at the beginning of the network and prepare a list of all the activities available for scheduling.
In the first instance this will naturally be all activities
starting from the first event, later in the scheduling
process, however, the list of activities available for
scheduling will be composed only of activities whose
The Planning Network
,.
1 man
1 man
6 wNlcs
Men
Weeks
(a)
Scheduled at Earliest Dates
1 man
6
w~s
1 lnan
Men
4
Resource
- - - - "'ivc:ii'iabitiiy -
o
(b)
Weeks
Scheduled at Latest Dates
Figure 2-Resource aggregation
307
308
Fall Joint Computer Conference, 1967
ferent types of resource. Each network activity may
preceding activities have already been scheduled.
.
require several different resources ( e.g., bricklayers,
The usual scheduling method is then to allocate the
labourers and cement mixers) to be considered simulavailable resources to activities on a day by day (or
taneously.
Sometimes a resource may only be required
time unit by time unit) basis. There will be several
for
part
of
the activity duration, as for example in
activities in the list, and as they can only be dealt with
building
a
wall
where labourers may dig and lay the
one at a time, the next step is to arrange them in order
foundation
but
bricklayers
only arrive after this work
of priority. The squence in which activities are schedhas
been
done.
uled is important as it is a question of 'first come first
There are often special conditions to be observed
served', the first activities having the pick of available
when
formulating work schedules. For example, some
resources and the later ones possibly having to be deactivities
once started must be worked continuously
layed.
without
interruption
(as laying concrete), others may
It might at first sight appear that critical activities, or
be
interrupted
at
any
time (as building a fence), others
activities with small amount of float, should be schedcan
be
interrupted
only
at special times (as between
uled first. In practice however, it has been found that
finishing
the
foundation
and
commencing bricklaying).
there is advantage in scheduling the shortest activities
Also,
resources
fall
into
different
categories and refirst and other .factors also influence the choice of
quire
different
treatment,
for
example
manpower and
scheduling priority.
equipment
are
wasting
assets
in
as
much
that if they
As resource allocation proceeds on a day by day
are
not
used
then
productive
capacity
is
lost
forever,
basis from the beginning of the network to the end,
Materials on the other hand, if not used, can be stored
the situation inevitably arises where there are insufand used the next day without waste. Some materials
ficient resources available in a particular time period
(like concrete) are consumed and others (like scaffold
and then an activity, or part of an activity, must be
tubes)
can be reinstated as available resources after
carried over until the next time period which has sufuse.
ficient resources available. In a resource limited situaAvailabilities of resources too seldom follow the
tion such as this, the carrying over process will usually
constant line shown in Figure 2. They are ,usually
extend the project duration and cause the completion
cyclical with five or six days of work and two or one
date to be delayed.
day (weekends) of no work. Some industries have lowAn example of this is shown in Figure 3 (a). Here
er resource availabilities on Mondays and Fridays due
the network shown in Figure 2 has been allocated on
to absenteeism. Thus each week comprises not one but
a r~source limited basis and in consequence the comfour levels. Public and annual holidays add further
pletion date has to be extended by 1 unit (from 6 to
complexity to the scheduling process.
7). Thus the second question "What is the minimum
Additionally, resource levels themselves are not finite
delay to the completion of the project when insufficient
and absolute. The initial prognosis may be to only work
resources are available?" is answered in this particular
normal hours, but overtime working is an established
case.
part of the current industrial scene. Thus any practical
However, the third question posed above "What is
approach to resource allocation must take account of
the most efficient utilisation of resources to carry out
the possibility of employing labour and equipment for
the project in a fixed time?" is still to be answered.
a greater time than the normal working hours-overTo ascertain this the allocation process is carried out
time will probably be worked anyway!
with a fixed time limit and no delaying of activities
When resource scheduling, therefore, it is usual to
is permitted beyond the amount allowed by the availspecify two levels, firstly, the normal level and secondly
able float time. In doing so, it is inevitable that the level
the maximum level. This second level is usually the
of available resources is exceeded but it is arranged
maximum possible overtime and in the terminology of
that this will take place at the point where it makes
resource allocation is known as the "resource threshthe minimum increase above the preset level. The effect of the operation is shown in Figure 3 (b), where
old." The cost of resources within the threshold will
the level of resource availability has been exceeded in
usually ce higher, a point having significance in projtwo places but the increase nowhere exceeds one unit.
ect cost analysis, which is described later.
Thus, the four schedules, Figure 2 (a) and (b) and
To complete this survey of the factors to be conFigure 3(a) and (b), indicate the main alternatives
sidered in resource scheduling, it is necessary to conavailable for the specimen network.
sider the significance of the project end date. Like reHowever, real projects are much more complex than
source levels, the end date is not usually fixed and
this example. The network may comprise several thouunalterable, some flexibility is usually present in as
sand activities and involve more than a hundred dif- . much that project completion is acceptable over a range
309
The Planning Network
PrOject Time
Extended 1 week
,-
I
, man
2 weeks
1 man
6 weeks
Men
4
8
Weeks
(a)
Allocation within resource limit
float
I
I
I
:
Men
Fixed
r--Time
4
I
I
Limit
I
I
Resource
- - - - AVOiiObiTity-
8
Weeks
(b)
Allocation within time limit
Figure 3-Resource allocation
310
Fall Joint Computer Conference, 1967
of dates. This is especially true at the initial planning
stage where contractual commitments have not yet been
established. When. it is realised that the plan eventually
adopted will inevitably be a compromise between early
completion dates, efficient resource utilisation and
economic costs, it becomes apparent that flexibility of
completion date is the only means of obtaining suitable arrangements in terms of resources and costs.
A method of expressing flexible end dates is to set a
"preferred completion date" and a "maximum permissible completion date". In the jargon of the trade, the
difference between these two dates is known as the
"project duration threshold."
In this brief survey, the principle factors to be considered have been described sufficiently to highlight the
somewhat overwhelming complexity of the resource
allocation task. Fortunately considerable headway has
been made in recent years in development of computer
prograIffl to undertake this calculation. It must be said,
however, that the mathematics for a perfect solution
does not exist and it is still necessary for management to
exercise judgement in the specification of scheduling
objectives, priorities, the validity of basic data (networks and time/resource estimates) and approval of
computed results. Here the senior manager is fulfilling
his tooditional role of giving instructions to his planners
and approving their work without necessarily being
able to check the calculations in detail. Using a computer, however, he is assured that his instructions (inherent in the computer program) are obeyed exactly
and clerical mistakes will be virtually non-existent.
A computer can very quickly calculate the best manner of allocating available resources so that particular
project objectives can be met within the priorities set
by management. In these complex situations, a computer will ascertain the best solution, but it often happens that the basic problem described so far is insoluble
when the resource requirement exceeds the resource
availability and the project duration is considered to
be fixed. The adage "you cannot put a quart into a
pint pot" is particularly relevant to this situation and
it is necessary to exercise a deliberate choice of the
manner in which the resource requirement shall overflow
the resource availability. The choice is usually between
delaying the completion date, using more men and machines, or working extra hours. Any of these choices
will usually have maximum limits (thresholds) which
it is not possible to exceed.
The alternatives are shown diagrammatically in
Figure 4. Here the resources (vertical scale) are plotted
against project duration (horizontal scale). Referring
to Figure 4, it is seen that the resources have a normal
level (Le., the most economic rate of working) and
above this the resource "threshold" representing an ad-
ditional capacity which can be obtained at additional
cost (Le., overtime working, double shift working, extra
plant, etc.). The threshold has, however, a finite capacity which cannot be exceeded. Also shown beyond the
preferred completion date on the horizontal scale is a
project duration threshold up to the maximum permissible completion date. The project duration threshold represents the tolerable delay (if any) which can be permitted under dverse resource availability situations.
Figure 4 (a) shows the simple case where there are
adequate resources for the completion of the project
by the preferred completion date and Figures 4 (b ) ,
(c) and (d) illustrate the alternatives when resource
availabilities are insufficient. In Figure 4(b) the resource
threshold has not been used by the project and the completion date is extended. In Figure 4(c) the completion
date has been maintained but the (higher cost) resource
threshold has been utilised. In Figure 4 ( d), both the
resource threshold and the project duration have been
taken up.
A further case exists, of course, where even if the
resource threshold is used the project cannot be completed by the maximum permissible completion date.
Usually in this event drastic action is necessary in respecifying the project.
Consideration of the different scheduling alternatives
involves an iterative analysis of the project with differing restrictions. The computer is particularly useful
at this stage, as it can produce a variety of simulations
of possible alternatives and print the results in a form
which can be quickly assimilated by those responsible
for taking decisions about the· project plan.
Examples of computer analyses are shown in Figure
6 which is a resource histogram of one trade on the
network Figure 5. In Figure 6(a), the computer has
constructed a schedule which contains the entire work
content within the normal resource level. This has delayed the completion date from 4th January 1967, to
23rd March 1967. In Figure 6(b), however the computer was instructed to schedule within the fixed time
(4th January 1967) given by the original time analysis.
Here it is seen that the work can be achieved but this
particular resource is utilised right up to the threshold
level for two weeks and within the resource threshold
for five weeks.
The computer has produced clear unequivocal statements of alternative policies but it is still the prerogative of project management to decide between them.
Further guidance will obviously be helpful and fortunately this can be extracted from the planning network.
As the differing scheduling alternatives give different
project durations and project costs, it is useful to consider the alternatives in conjunction with project cost
analyses before selecting the plan to be implemented.
The Planning Network
e~
~i=
~W
311
~~
C13i=
~2iWw
~~W !i~~
~~~ ~~~o
Q..uo
~Q..U
~~~~~~E--'~------------------------------~--~ ~~~~~~E~------------------------------~----f
LEVEL
LEVEL
RESOURCE THRESHOLD
:~~~iCE~------------------------------~--~ :~~~;C~~-'~TT~------~~~~----~~~~~
LEVEL
LEVEL
If)
UJ
u
a::
:J
~
UJ
a::
PROJECT DURATION
Ca) Schedule within re.ourea and prolect dUt'atlon limit.
e~
~E
W..I
~~
Cb) Within resource Umlt. but with extanded prolect duratl!rS
~~
W_
113-
~~~W
~:;;
i~..I
~~w
_~Q..~
~~~ ~w~O
LL.Q..W
MAXIMUM __
~
______________________________
Q..UO ~Q..U
~
__
~
RESOURCE
LEVEL
NO~AL
W~I~O~
--~~~~---+~~~----~~~~--~--~
RESOURCE
Q..UO
~~~
!:itw
)(~~I
~wo~
~Q..UO
~~~~~~E~~;=~---r~~~r---~~rJrr-r71~-rf
LEVEL
NORMAL
-~~~~-+~~~~~--~~~~~~~~
RESOURCE
LEVEL
LEVEL
lfl
If)
a::
a::
::J
o
If)
UJ
U
UJ
u
:J
~a::
UJ
a::
Cc) Within preferred project duration but with exce .. ive resource
requirement.
Cd) Schedule exceed. both , . .ource Umit. and pre""ed prolect
duration
Figure·4-Resource and project duration thresholds
Project cost analysis
The next step of progress towards an acceptable project plan is to carry out a cost analysis of the network.
When performing this, it is convenient to consider project costs in two elements viz.:
Direct Costs
Indirect Costs
Direct Costs are those expenses which can be attributed directly to individual activities and are usually
obtained by applying the appropriate rate to the resources necessary for the activity. Hence labourers
may be priced at £ 3 per day and bricklayers at £ 5
per day for normal working. Where premium (or
threshold) resources are available, then the appropriate higher rate will also be specified. During resource
allocation, the aim is to minimise the amount of premium resources used and hence the lowest cost schedule will be produced automatically. For cost analysis
purposes, the amount of each resource used is extended by the rate which is applicable, i.e., normal or
premium and the amount accumulated for each time
period covered by the network.
Indirect Costs arise from the practical difficulty of
apportioning some costs accurately to individual activities. Such things as administration, storekeepers, security
and other overheads cannot properly be defined as
relating to particular activities but rather to groups of
activities or even the entire network. The network
planning method of handling these costs is to introduce
special activities which are for the sole purpose of
spreading indirect costs. These will start and finish at
the events on the network where the particular indirect
costs are deemed to start and finish and the money involved is applied to these activities either as a rate per
day which is then built up over the calculated duration between the two events, or as a lump sum which
is spread over the duration of the activity. No time
is specified for these "cost only" activities, as their
duration is calculated during the analyses of the network.
A further use of "cost only" activities is to provide
a means of bringing project delay costs into the calcula-
312
Fall Joint Computer Conference, 1967
... 0
DESIGN COVERS
A.... B.3
PROJECT GO AHEAD
6·0
TOOLS
MANUFACTURE
TOOLS
A-2, B-2, C-3,'-----.r--A
F-3S0 10.0
MAKE
COMPONENTS
A;2, B-2, C= .. ,'--.........~
E-SOO
3·0
MAKE
SUB-ASSEMBLY
A
=
DESIGN ENGINEERS
B = DRAUGHTSMEN
C = INSPECTORS
7·0
OBTAIN ELECTRONICS
- -...~
CRITICAL PATH
D = ASSEMBLY ENGINEERS
E = MACHINE HOURS
F
= TOOLROOM
HOURS
Figure 5-A small planning network
tion. Contract penalty clauses are an obvious application of this technique, but it will apply equally to the
cost of lost revenue occurring through non-completion
on certain dates, i.e., loss of rents of buildings, loss of
production when plant is shut down for maintenance,
loss of income· from delayed opening of shops, etc.
To complete the build-up of project costs, the direct
and indirect costs are accumulated to obtain the total
expenditure over the duration of the project. It is customary to show the project cost analysis as a cumulative curve as in Figure 7, from which it is possible to
see at a glance the total expenditure required and also
the way in which the rate of expenditure is spread over
project duration. The calculations involved in this
analysis are not particularly complicated, providing the
basic data is available, and if a computer is used for
the analysis of the network and the allocation of resources, then cost curves (as shown in Figure 7) can
be printed direct from the line printer of the computer.
It will be apparent that, with the range of factors
considered in this cost analysis, both spread of cost
and total cost are influenced by the work schedule. produced during the resource allocation process. The direct
costs will vary according to how much higher-cost, or
threshold, resources have been used and some indirect
costs will rise with increase in project duration.
Examples of the variation which may occur are shown
in Figure 8. Here are shown alternative cumulative cost
curves which could arise when differing resource all0cation policies are applied. In Curve No.1, the projc::t was scheduled within a fixed time limit which
caused high-cost threshold resources to be used and
hence produced a high-cost schedule, requiring £ 19,600. In the case of curve No.2, a schedule was calculated within normal resource availa':ilities and thus
threshold costs were avoided. The project completion,
however, is delayed and as the project bears some indirect costs which are proportional to time, these continue to rise during the extra project time and more
than offset the saving accruing from. the avoidance of
resource threshold costs. The combined effect is to
produce a total project cost of £ 21 ,200 which is higher than alternative No.1.
Dependent upon the rate and time displacement of
indirect costs, however, the cost analysis could well
have resulted in curve No.3. Here the indirect costs
do not offset the savings in direct costs (resulting from
the avoidance of threshold resource costs) and the
The Planning Network
It
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DATE
lHAR66
ICT 1900 SERIES PERT ANALYSIS or PROJECT AS66 rOR TREP ENGINEERING CO.lTD.
ZERO DATE lJUN66
DESIGN ENGINEERS
HISTOGRA" OF RESOURCE REQUIREHENTS
2 CHARACTERS
RESOURCE lI"ITED SCHEDULE
11
REP~ESENT
I
.1
10
I
9
I
I
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ilv£shokl ~:
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•••••••••••••••••• ---••••••••••••••••••••••
.
6 ••••••••••••••••••••• ----------------1
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5 -------------------
Re;oo.ln:e ~
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Ret wired
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1
I
I
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••••••• I ••••••• I ••••••• ' ••••••• : ••••••• 1 ••••••• I ••••••• I
6JUN
66
4JUL
66
lAUG
66
29AUG
66
26SEP
66
2<40CT
66
21~OV
66
I
• • I ....
19DEC
66
•
•
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•
•
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•
•
•
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•
•
I
1
1
•
•
•
•
I
2
1 WEEK
PAGE
313
I
16JAN
67
•
•
Figure 6(a)-Resource histogram-resource limited
combined effect is to produce a lower overall cost
( £ 17,800) for the completed project.
Using techniques of network based resource allocation and cost analysis, project management have available a convenient method of realistically evaluating
planning alternatives. It will, however, be apparent
that a considerable amount of calculation is involved
to produce a number of alternative schedules and cost
analyses upon which management can adjudicate and
the computer is particularly useful as a means of alleviating this chore. The fact that the modern computer
can produce such information in graphical form considerably aids communication between management and
planning personnel. An example of a computer produced diagram is shown in Figure 7.
Project prQ/itability
Having assessed in some detail the amount and
spread of costs which the project is likely to incur, it
is next necessary to make similar estimates of the income and any other cash movements which may be
associated with the project before profitability can be
analysed. To assess profit accurately, it is necessary
that the whole of the life of the project be considered
and all associated incomes and expenditures be included.
Thus complete analysis will involve continuing operating costs, revenues, investment grants, taxation and tax
allowances.
An important factor associated with these estimates
is their displacement in time relative to the initial project expenditures. The planning network can be used
to obtain these displacements merely by inserting the
appropriate costs (suitably identified) into the network
at the appropriate point and by extending the network
(if necessary) with "cost only" activities beyond its
normal completion.
314
..
Fall Joint Computer Conference, 1967
- -- - - - - - - - - - - - - - - - --- - - ---- - -- -- .. - - - -- - -- - - - - - - -- -- - -- - -- - -- --- -- --. ------DATE
1"AR66
ICT 1900 SERIES PERT ANALYSIS OF PROJECT 4S66 FOR TREP ENGINEERING CO.LTD.
•
•
It
PAGE
1
..
DESIGN ENGINEERS
HISTOGRA" OF RESOURCE RECUIREMENTS
..
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
I
ZERO DATE 1JUN66
2 CHARACTERS REPRESENT 1 WEEK
11
I
10
I
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TIl T
Til
11 T
TIl T
9
I
I
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11 TTTTTTTTTTTTTTTTTTTTTTTTTTTT
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Til
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8 TTTTTTTTTTTTTTTTTTTTT
I
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I
I
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I
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11
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6 •••••••••••••••••••••
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I
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1
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• 0
;;~: .... :~~: .... ;;~~ ... ;;;;; ... ;;;;; ... ;:~; ...
;;;;:I .. ;;;;;...
1
- - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--
•
•
•
•
•
It
- - - - - - - - - - - - - - - -- - - - - - - - - - -- _.
Figure 6(b )-Resource histogram-time limited
A further factor in this analysis is an assessment of
risk, as future profits can never be free from uncertainty.
The degree of risk, however, will vary and thus the
quantitative assessment of the degree of risk is a necessary adjunct to the consideration of the possible
amounts of profits. Risk arises because of uncertainty
inherent in the various estimates made during the analysis. Thus an objective financial assessment of a project
must take account of the following main factors:
1. Amount and timing of investment
2. Amount and timing of income
3. Possible variations in both investment and income.
Cash flows
The amount and timing of both investment and income can conveniently be considered as cash flows,
whereby an expenditure represents an outward flow
(negative) and an income represents an inward flow
(positive). Uncertainty about either inward or outward
flows can then be represented by al~ernative values for
these items.
The use of network planning techniques a~ a basis
from which to build up realistic work schedules and
a:::curate assessments of project costs have been described earlier. The cumulative cost curve of the project
plan selected shows the proposed expenditure over time
and thus provides the basis for one of the principle
cash flows involved in profitability assessment. For a
complete evaluation, however, it is necessary to consider all other expenditure and incomes which will be
relevant to the project.
An example of such a study (made by computer) is
illustrated in Figure 9. Here the building of a factory
extension is under consideration. The plan envisages
that this will be built over a period of 2 years 3 months
(between 1966 period 3 and 1968 period 3) special
The Planning Network
- . - -.- - - .. - ..
~:T: - :;A~6-6-- - - ;C~ -1~:0 - :E:I~::E-R~ -A::~S-I: -0; ~;O~E~; ~~6~ -r~~ ~~E~ -E~~I~:E~;~ -C~~:~:~- - - --P~~:-- -~ -- ~-l
PLANNED COST PROJECTION rOR TIHE LIHITED SCHEDULE
REPORT DATE
..
2 CHARACTERS REPRESENT 1 WEEK
4t
22000
.
20000
.x
x
x
x
18000
4t
4t
4t
16000
4t
.X
x
x
12000
X •
.
10000
x
x
•
•
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X
x
x
x
x
8000
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6000
X
xx
x
x
4t
4t
£,cp~ ih.&re
.t;lq~600
:
x
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4t
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lJUN66
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4t
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4000
xxx
2000
• xx
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•
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.
l_~ ______________ ~~:N___ ~~~~ __ :~~G__ ~~:~. _::~!~ :~~~: :l~~Y__ :._~~c___1:~:~ __ ~~~___________________ ;_
Figure 7-Project cost curve
equipment to be installed will have a life of 4 years
(between 1968 period 2 and 1972 period 1). The total
cost of the factory and plant will be £270,618 and
this will be depreciated over 4 years, after which it will
have a scrap value of £ 2,000 (in 1972 period 2).
There is also another small recovery of £500 (in
1971 period 1) due to the interaction of another project which will make part of the plant redundant. The
initial cost and the two recoveries are shown in Figure
9 in the columns headed "CAPITAL INVESTMENT"
and "OTHER CAPITAL." As described earlier, the
negative sign indicates expenditure and no sign indicates income.
Investment grants, initial and annual tax allowances
are significant items in the financial evaluation of a
development project, the incomes accruing from these
have been calculated by the computer and are shown
separately in Figure 9 in the columns marked "INVESTMENT GRANT" "INITIAL ALLOWANCE"
and "ANNUAL ALLOWANCE." These items are subject to delayed payment-this delay has been calculated
and the amount entered at the date at which the cash
value of the allowance will be received. The negative
annual allowance figure is a refund caused by the recovery of the scrap value of the project.
In order to ascertain the income which will be ob-
316
Fall Joint Computer Conference, 1967
..J----..- 121,310
.-t---,,-----ir-----fTIME LIMITED SCHEDULE
USING HIGH COST THRESHOLD
RESOURCES
.,..
119,600
- t - - -........ 117,800
LOWER COSTS DUE
TO AVOIDANCE OF HIGH
COST THRESHOLD RESOURCES
t
~
en
8
EXTENSION OF
PROJECT TIME DUE TO
RESOURCE LIMITATIONS
TIME - - .
Figure 8-Alternative cost plans
tained from the project, estimates of the operating
costs and revenue are included in the appropriate time
periods. The income derived from the project is shown
under the heading "REVENUE INCOME," and the
routine cost of operating the plant and using materials,
labour, etc., is shown unded "REVENUE COST." The
computer makes' the simple subtraction to give the incomes shown under "REVENUE PROFIT." Here it
will be noted that the first operating period (1968
period 2) is expected to make a loss (-5000) during
the time the plant is working but not yet producing
goods.
"The tax man cometh!" In the next column on
Figure 9 marked "TAX ON PROFIT" the amount of
corporation tax payable on the revenue profit shown
in the previous column is calculated. The cash value
shown in this column is entered after the appropriate
time lag at the actual date the tax payment is made.
With this information, the "NET CASH FLOW" is
calculated. This is the difference between the cash inflow (income) and cash outflow (expenditure) and is
the arithmetic sum of the capital investment and the
various allowances, the revenue profit and tax on
profit. This column indicates the amount of money
which is to be put in or taken out during each time
period of the project.
In the next column of Figure 9 an increment has
been included for "INTEREST" on the cash required
to finance the project. In this example, it has been
specified that cash required will attract an added interest rate of 7 % per annum (amount indicated by a
minus sign) and when the project accrues surplus
funds, then this can be re-invested at 4 %. per annum.
These percentages are selected as representing the borrowing and lending rates open to the company at the
time. The net cash flow and interest elements are now
combined to give the "CUMULATIVE CASH FLOW,"
shown in the last column. This total shows the position of the investment at the end of each successive
period.
Financial evaluation of project
The cumulative net cash flow for the project shows
the pattern of increasing expenditure during the initial
period of the project and how recovery is effected. It
shows the point at which the cumulative income exceeds the cumulative expenditure (the project duration
to this point is usually known as the payback period)
The Planning Network
317
FINANCIAL EVALUATION OF PROJECT
EXTENSION
BLACKMORE PLANT,
DEVLPMENT AREA -
STR. LINE. NO COST/INCOME IN/DEFLATION.
CAPITAL
INVESTMENT
OTHER INVESTMENT INITIAL
ANNUAL
CAPITAL
GRANT
ALLOWANCE ALLOWANCE
2
3
-3766.0
-7832.0
-51800.0
-12317.0
-33718.0
-60214.0
-83261.0
-15567.0
-2U3.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
500.0
0.0
0.0
0.0
2000.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
15053.5
18565.2
3891.7
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
'0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
2709.6
0.0
0.0
0.0
4042.3
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
9002.5
0.0
0.0
0.0
9002.5
0.0
0.0
0.0
9002.5
0.0
0.0
0.0
11253.1
0.0
0.0
0.0
-800.0
TOTALS
-270618.0
2500.0
37510.4
6751.9
37460.6
YEAR PERIOD
1966
3
4
1967
I
2
3
4
1968
I
2
3
4
1969
I
2
3
4
1870
I
2
3
4
1971
I
2
3
4
1972
I
~
3
4
1973
I
TOTAL INVESTMENT (LESS ALLOWANCES)
TOTAL REVENUE INCOME
.
NET PROFIT (AFTER TAX a DEPREC.)
REVENUE
INCOME
0.0
0.0
0.0
0.0
0.0
0.0
0.-0
20000.0
35000.0
50000.0
60000.0
70000.0
70000.0
70000.0
70000.0
70000.0
70000.0
65000.0
65000.0
65000.0
60000.0
60000.0
60000.0
0.0
0.0
0.0
0.0
0.0
<;>.0
5~
ANNL. MARKET GROWTH.
REVENUE
COSTS
REVENUE
PROFIT
TAX ON
PROFIT
0.0
0.0
0.0
0.0
0.0
0.0
0.0
-25000.0
-32000.0
-35000.0
-30000.0
-27000.0
-27000.0
-27000.0
-30000.0
-30000.0
-33000.0
-35000.0
-35000.0
-40000.0
-40000.0
-45000.0
·50000.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
-5000.0
0.0
3000.0
0.0
15000.0
0.0
30000.0
0.0
43000.0
0.0
43000.0 -5200.0
43000.0
0.0
40000.0
0.0
40000.0
0.0
37000.0 -63600.0
30000.0
0.0
30000.0
0.0
0.0
25000.0
20000.0 -58800.0
15000.0
0.0
10000.0
0.0
0.0
0.0
0.0 -36000.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0 -4000.0
960000.0 -541000.0
419000.0-167600.0
NET CASH
FLOW
INTE
REST
CUMULATI VE
CASH
FLOW
-3766.0
-7832.0
-51800.0
-12317.0
-33718.0
-60214.0
-83261.0
-20567.0
3566.6
15000.0
30000.0
58053.5
69410.0
46891.7
40000.0
40000.0
-17597.5
30000.0
30000.0
25500.0
-29797.5
15000.0
10000.0
2000.0
-24746.8
0.0
0.0
0.0
-4800.0
-64
-198
-1082
-1310
-1905
-2961
-4427
-4852
-4874
-4702
-4272
-3357
-2235
-1475
-820
-155
-456
26
311
556
278
423
522
546
316
320
323
326
-3766
-11662
-63660
-77059
-112087
-174206
-260429
-285423
-286709
-276583
-251285
-197504
-131451
-86794
-48269
-9090
-26842
2702
32728
58539
29298
44576
54999
57521
33320
J3644
33964
34287
29812
186395
29812
PAYING RATE (4.00 , EARNING RATE)
~ PAY I NG RATE a 4.00 , EARN I NG RATE
10.96 ,
D.C.F. NET PRESENT VALUE
22636 AT 7. 00
PAYBACK PERIOD
GRANT, 15' INITIAL, 20' ANNUAL
960000
D.C.F. YIELD RATE OF RETURN
AVERAGE ANNUAL RATE OF RETURN
25~
INCOME EST. ON
3.43
.
~
4 YEARS 2 PERIODS
Figure 9-Financial evaluation of project
and also gives a general indication of the relative size
of expected profits to expected expenditure.
The same information is calculated by the computer
and printed on the financial analysis Figure 9, where
it is seen that the net profit after meeting all tax commitments and fully depreciating all plant and equipment, is expected to be £ 29,812. The net profit
shown here is, of course, only a guide to the general
order of profit expected at the end of the project. It
will be seen that the amount is heavily conditioned by
the interest rates (7 % and 4 %) applied to the cash
flows. If these rates are varied, then the net profit will
also alter significantly. This net profit shown is derived
from a net capital investment of £ 186,395 and a
revenue income of £ 960,000. The maximum cash requirement at anyone time will be £286,709 and will
occur in 1968 period 3. Also calculated and shown in
Figure 9 is the payback period (described above)
which is here 4 years 2 periods after the commencement of the project.
Discounted cash flow yield
However, this information does not complete the
analysis. The next step is to calculate the financial
yield (i.e., return on investment expressed as a percentage) obtained from the project. Here it is called
Discounted Cash Flow (D.C.F.) Yield and follows the
'discounted cash flow' method of calculating financial
yield. Discounted cash flow is gaining increasing usage
in recent years and is based upon the fact that the purpose of an investment is to obtain a series of future
annual incomes over the life of the project. The technique of D.C.F. Yield is to find the rate of interest
which discounts future income from the project down to
a 'present value' equal to the initial investment. This rate
is called the "yield" and is often used as a profitability
index for the purpose of inter-project comparisons.
Another way of defining "yield" is that rate of interest which the funds estimated to be required for the
project would need to earn if, instead of being used
318
Fall Joint Computer Conference, 1967
on the project, they were invested elsewhere at the
same time as those estimated for the project, so as to
give exactly the same returns at exactly the same time
as the project predicts.
This concept of time and value can best be illustrated relative to a table of compound interest i.e.,
£ 100 invested at 5 % compound interest increases
each year as follows:
1st year
£ 100 x 1.05
== £ 105
2nd year == £ (100 x 1.05) 1.05
== £ 100 X 1.052
== £ 110
3rd year == £ 100 X 1.053
== £ 116
4th year == £ 100 x 1.054
== £ 122
Thus it can be said that the 'present value' of a profit of £ 122 in four years time· is only £ 100. Similarly
the 'present value' of any future profit can be obtained
by dividing by a 'present value factor' which is the
reciprocal of the compound interest factor e.g. again
assuming 5 % compound interest, £ 100 in four years
time has a 'present value.'
1
== £100 x == £100 x
105 4
== £ 100 x .8227 i.e. present value factor
== £82
There are, therefore, three elements involved-present value, future value, and the compound interest
rate which relates the two values. If the two values are
considered as cash flows (as in example Figure 9) then
the present value is negative (i.e., expenditure) and the
future value is positive (i.e., income). The interest
rate is then the rate at which discounted positive cash
flows equals discounted negative cash flows.
The present value of negative £82 however, shown
above, is not discounted (as it is already the present
day) and the positive £ 100 is only discounted for one
year. In the larger example Figure 9, both the negative
and the positive cash flows occur over several years
the present value is negative (i.e., expenditure) and the
D.C.F. Yield) applicable to the combined cash flows
of several years. The method of obtaining this involves
repeated calculation of the present value using different yield rates until a rate is found for which the
and it is required to calculate the interest rate (Le., the
sum of the discounted negative cash flows.
Dual rate D.C.F.
In the single rate D.C.F. method just described, the
discount rate is considered to be the same when the
calculation is on either positive cash flows or negative
cash flows. This is not entirely realistic, as it is normal
for interest rates to be different according to whether
the required cash is being "lent" or "borrowed." To
accommodate this distinction, the calculation can be
made with different rates according to whether the
project is absorbing capital or showing a profit. The
two rates are termed earning rate and paying rate.
Earning rate is the rate of interest which can be obtained on the surplus funds accruing to the project.
In the example Figure 9 this rate has been set at 4 %
but ft could be set higher if the money is to be invested
more profitably or it could be zero in the unlikely
event of the cash not being used.
Paying rate is the rate of interest which the project
must pay in order to obtain the funds necessary to
finance the project. This could be the market rate
(e.g., 7%) or if it is desired to calculate the yield, it
could be the D.C.F. rate, i.e., the calculated rate which
discounts the present value of the project to zero.
The application of different rates according to the
state (i.e., positive or negative) of the investment is
usually known as a dual rate analysis and where one of
the rates (usually, but not necessarily, the paying rate)
is the D.C.F. rate, it is termed dual rate D.C.F. analysis.
A dual rate D.C.F. analysis has been performed on
the cash flows shown in Figure 9 with the earning rate
set at 4% per annum and has revealed a D.C.F. yield
paying rate of return of 10.96%. This indicates that
if the project had not been undertaken, it would have
been necessary to obtain that rate of investment in
order to earn the same profit from the same amount of
money invested over the same time span.
Profitability Analysis
With the information shown on the "Financial Evaluation of Project," management have a comprehensive
set of data upon which an assessment of the financial
merits of the project can be deduced. Perhaps, more
important, because the information has been arranged
and analysed in a logical manner, it offers a standard
method of making comparisons between the respective
merits of different projects or different approaches to
the same project.
This consistency of evaluation is invaluable in the
process of communication, when several managers are
required to discuss the merits of different projects. The
facts presented in the analysis are unambiguous and
based upon sound mathematical principles but, even if
details of the method are challenged, the fact that it has
been consistently applied to all projects under consideration stilI enables the comparative aspect to apply.
Initial evaluation is, however, usually only the starting point for a further study of alternative plans. The
project may be speeded up by refining the planning
network, more resources may be applied, production
costs may be re-examined and alterative marketing
strategIes (i.e., pricing structure and sales forecasts)
may be test~d to ascertain the effect upon income. With
each set of data. the calculated D.C.F. Yield and associated information give a sound guide to the financial merits of each particular plan.
The Planning Network
Financial risk assessment
It will have been noted that the financial evaluation
of the project in Figure 9 was based upon a number
of estimates about probable expenditures and incomes
in the future. Whilst the detailed cost plannirig will
have introduced a good measure of accuracy into part
of the expected cash flows, there remains much data
which could be subject to wide fluctuation. Actual sales
will ultimately depend upon the state of the market
at the time that production is possible and this is conditioned by the general economic situation and the actions of any competitors. Similar factors such as the
variability of cost of materials and labour could also
influence production costs. Any variation in the information used will of course, affect the yield and
hence the profitability of the project. Few investment
decisions will, therefore, be settled by a single evaluation calculation and the decision taker will certainly
want to investigate some of the alternatives which might
arise.
Whilst it is apparent that the technique described
so far can easily be repeated for the major alternatives
( e.g., to build a new factory in place of a factory extension), it is not a satisfactory way of handling variability of the individual estimates used in the calculaton.
What is required is a method similar to that sometimes
used for network time estimates, where three time estimates, (optimistic, most likely and pessimistic) are
quoted when uncertainty exists.
In specifying financial uncertainty however, a more
flexible method is adopted whereby each alternative
estimate is given aprobability rating. Here the probability rating is an expression of the chances of that
particular estimate becoming a reality. It can be likened
to the odds quoted for horses in a race, which are the
bookmaker's assessment of the chances of each particular horse winning (or rather not winning). The
number of successful bookmakers gives some weight
to the accuracy of the probability estimates.
In the case of project risk evaluation, the probability
is usually expressed as a decimal or as a percentage,
this showing the "weight" to be attached to that particular estimate. A series of calculations are then made
to determine the profit which will result from alternative cash flow patterns. This calculation takes account
of the "weight" applied to each cash flow value.
The method is to use a sequence of random numbers to guide the selection of dependent variables to
be used. Each of the estimates is assigned a range of
num':ers the size of which is proportional to their P~9b
ability. From a standard table of random numbers,
the first number is taken and this is checked with the
range assigned to each variable and when correspondence occurs that estimated value is taken for the cal-
319
culation. The next random number selects the estimate
for the next factor and so on until a full set is obtained
upon which to perform the profitability calculation.
When a set of data has been selected by this means, the
calculation is made and the answer recorded. The calculation is repeated a number of times using figures
obtained by the ran~om number procedure described.
After each calculation a count is made of the number
of times that each profitability yield rate has occurred.
"The distribution of the answers (Le. number of times
each particular yield rate occurred) then gives an indication of the relative probability of obtaining each
answer.
The calculation is, therefore, in the nature of ,
simulation of alternative solutions and when repeated
for a sufficient number of times gives an assessment of
yield probability. A sample of 100 calculations is perhaps the smallest quantity which will give a reliable
indication and it will be apparent that the use of a
computer is essential for this chore.
The answer appears as the frequencies with which
particular profitability p.ercentages are likely to occur
over the full range. An example of the results· from this
calculation on the D.C.F. Yield of the "Blackmore Extension" (Figure 9) is shown in Figure 10. Here 500
calculations have been undertaken to find the D.C.F.
Yield with a variety of input data having different
probabilities. The number of times each percentage
was calculated is shown alongside that particular percentage. It can be seen that 10% with 168 occurrences
gives the highest expectation, but there is a small chance
that the yield might be as high as 12 % or as low as
5 %. If all figures achieved fall within forecast ranges
supplied, there is no chance that the profitability will
fall outside the calculated range.
In Figure 10 these frequencies have been converted
to percentages and plotted graphically as a line of XXs.
This chart then gives a quick guide to the range and
probability of particular project outcomes.
The computer has also plotted the cumulative percentage (shown as 0-0-0 in Figure 10). This is
merely the sum of the frequency distributions converted
to a cumulative percentage and provides a convenient
reference chart, enabling the probabilities of achieving
particular yields to be read off at a glance. For example,
it can be seen that there is a 90% chance of achieving
8% or better and only a 10% chance of obtaining
11 % or better. Conversely, there is an even chance
(50% pro~abi1ity) that the actual D.C.F. Yield will
fall above (or below) 9.6%.
With probability frequency distributions of the main
factors involved in financial evaluation of a project,
management have a useful way of analysing financial
uncertainty. Risk can be categorized and so a degree
Fall Joint Computer Conference, 1967
320
D.C.F. YIELD PROBABILITY FREOUENCY DISTRIBUTION
-----.----- .-------- .-----------
EXTENSION - BLACKMORE PLANT.
DEVLPMENT AREA - 25"
GRANT.
15~
INITIAL.
20% ANNUAL
D.C.F.
YIELD %
15
X X X DISTRIBUTION PERCENTAGE
14
000
CUMULATIVE PERCENTAGE
13
12
11
10
9
11
23
I
I X,
:~
1/
7 IX
(
4
I
I
I
I
I
I
o
: ••••••••• 1 ••••••••• 1 ••••••••• 1 ••••••••• 1 ••••••••• 1 ••••••••• 1 ••••••••• 1 •••.•••••• 1 ••••••••• 1 ••••••••• 1
o
TOTAL RUNS
500
10~
20%
30%
40%
50~
60%
70~
80%
90%
100%
RANDOM SIMULATION - FREOUENCY DISTRIBUTION
Figure to-D.C.F. Yield probability frequency distribution
of segregation is achieved between those schemes which
are viable propositions and those which are either
distinctly unprofitable or involve an unacceptable degree of risk.
REFERENCES
H S
WOODGATE
Plannillg by network
Business Publications Ltd
2
London
International Computers and Tabulators Ltd 1900 series
PERT and 1900 series PROP
The computer programs referred to are ICT Application
Packages PERT (Programme Evaluation and Review
Technique) and PROP (Profit Rating of Projects)
Winged words: varieties of computer
applications to literature
by LOUIS T. MILIC
Columbia University
New York, New York
On August 6, 1961, an item appeared in the New York
Times describing a rather unusual project that a young
classical scholar named James T. McDonough had been
actively pursuing. According to the account, for the
previous four years McDonough had been reducing the
Iliad of Homer to patterns representing the meter of the
Greek epic, key-punching these patterns on a large
number of punch cards and running them on an IBM
650 in the hope of discovering whether the uniformity
of the patterns showed that the poem had been written
by a single author, a question about which there had
been a great deal of argument during the past century.
McDonough hoped to earn a Ph.D. at Columbia with
this work. Whether he succeeded or not, he had made a
landmark in being one of the first who used computers
in the solution of a literary problem. Since that beginning, others have availed themselves of electronic aid.
As it is now ten years since the beginning of the relationship between computers and literature, it may be
time to survey some of the results, to consider what has
been achieved and what the prospects are.
In talking about literary computation, I want to confine myself to activities which are strictly literary. There
are a number of related activities which border on literature but which are really tangential or preliminary to
literary study. Among these I include machine translation, the making of concordances, attribution study,
editing and bibliography, as well as most kinds of linguistic study. The reasons are relatively simple.
Machine translation arose out of a suggestion made in
1947 that machines might help to deal with the large
bulk of foreign-language materials, especially in Russian,
that government agencies and scientists found it necessary to go through in order to keep up with current
developments. At first, owing to certain oversimplified
ideas about the structure of languages, this seemed like
a reasonable task to ask a computer to perform. Naturally the government was interested in furthering this
research and invested substantial amounts in hardware
and programs. The linguists were excited by the challenge and devised ever newer grammars to deal with the
binary nature of the machines. Gradually, the hope of
success dimmed as a realization of the incredible complexity of natural language gradually emerged. Not machine limitations but inadequate knowledge about the
processes of the human mind and the nature of language
finally doomed the machine translation project.
A year ago, the Automatic Language Processing Advisory Committee of the National Research Council
issued a report in which it was concluded that, although
machine-aided translation might be deserving of further
support, pure machine translation could no longer be
considered a practical possibility and ought not to receive further financing. The difficulties that machine
translation programs have in distinguishing between
literal and metaphoric uses of language and in dealing
with idioms and problems of context are notorious. They
can be illustrated by two examples, probably apocryphal.
The expression "out of sight, out of mind" was supposed to be translated into Russian, where it became
"invisible idiot." The phrase "the spirit is willing but
the flesh is weak" returned from the Chinese analyzer
as "whisky O.K., meat no good."
Whether these are true or not, they suggest the
superiority of the human mind in dealing easily with
levels of literalness. The twenty years and the millions
spent on the effort to develop translation programs were
not wasted on a mere effort to inflate the human ego.
Though little translation actually took place, a great
deal was learned about the nature of language. It may
be claimed that postwar linguistics was revolutionized
by the discoveries of machine translators and their auxiliaries, the mechano-linguists.
The field of computational linguistics is very active
now and a great deal of valuable research is taking place
in it which will ultimately be of use in translation and
even In literary analysis. Work in automatic syntactic
analysis, sentence generation, semantics has implications
321
322
Fall Joint Computer Conference, 1967
for all kinds of word-connected activity. It is, however,
remote from the immediate concern of the literary
scholar and is not properly included in literary computation. All these linguistic projects are related to the
scientific study of language, which today has the status
of a behavioral science. The study of language as tl).e
medium of literature is quite a different realm, however
much it may overlap that of linguistics, because its main
concern is not with the characteristics of the code itself
but with the individual and aesthetic use of the resources
of language.
For that reason another whole class of studies may be
excluded from consideration here, although they seem
to reflect a much nearer concern with literature. I refer
to concordances, dictionaries, glossaries, indices verborum, word-lists and bibliographies. Computers have
vastly facilitated the compilatIon of these tools, and
these tools do have something to do with the study of
literature, but the use of computers in literary research
is something different from the mere construction of
lexical works of reference, which have existed in on~
form or another for centuries and which, when completed, are not essentially different from their handmade
predecessors. The essential use of computers in literary
research should diverge both quantitatively and qualitatively from the conversion of manual to electronic processing of data. The computer has made possible the
processing of information in such quantities that no
,man's lifetime or energy could previously have contained it.
The mere amount of computer processing is a kind
of innovation that we owe to technology. The class of
studies that best fits this description of quantitative
innovation is that of attribution, which has developed
considerable activity since the advent of computers. To
attribute an anonymous or uncertain work to its author
requires processing a substantial corpus of text for each
possible author and comparing its features with those
of the work in question. Previously such attributions
were made impressionistically on the basis of intuitivelyperceived similarities or differences which could only be
vaguely described: "This poem or this essay sounds like
the work of Pope or Shelley or Ruskin." The inherent
characteristics of the computer have necessitated the
formalization of aspects of style for electronic processing. The predominance of short sentences, or of certain
types of function words, the presence of certain grammatical constructions or favored lexical items, intervals
between successive conjunctions, statistical properties of
sentences or word-length distribution are examples of
formal features of style.
The resultant combination-large corpora of text and
cmpirical features of description-has made possible
the identification of disputed works in ways that could
not previously be imagined. Those who conducted the
attribution studies on The Federalist papers, the Letters
of Junius and the Epistles of St. Paul dealt in millions of
words and have lived to tell about it. In the process of
providing descriptions of the text explicit enough for
the machine, they have added to our knowledge of these
texts. Naturally, their results have not found favor everywhere, but they are on sound ground statistically and
they have in fact merely ratified prevailing opinions in
all three cases. Doubtless many more such studies will
be undertaken now until the supply of disputed works
runs out. One may look forward if he wishes to a definitive settling of the Bacon-Shakespeare-Marlowe contest.
Despite their usefulness to students of late eighteenth
century political writing and of New Testament Greek,
these studies are not essentially literary either. Their
main interest is historical. They answer the question:
"Who wrote this?" The literary information produced is
merely a byproduct of the investigation. To be sure, a
succession of attribution studies would provide extremely valuable information-information of which we
have but the outlines at present-about the historical
development of the English language. Such information,
however, is linguistic rather than literary in nature. It is
the background for stylistic studies but it is not itself
literary. It is related to but not a fundamental part of
the basic literary questions, which underlie the vast mass
of literary scholarship.
If we now look at what has occupied scholars during
the first decade of literary computation, we may be able
to say whether they have been concerned with literature
or with the preliminaries. Turning first to published
work, we have some large projects resulting from the
cooperation of a number of individuals and institutions.
The Cornell Concordances, jointly fathered by Cornell
and IBM, now cover Matthew Arnold, Emily Dickinson,
and WiIliam Butler Yeats. The same group has plans for
a number of additional works including most of the
English poets whose works have not yet been so favored.
A French group at Besancon has been conducting
studies of the French vocabulary and making wordindexes of French poets and playwrights, publishing
their results in two periodicals of their own. One of their
separate publications is a concordance of Baudelaire
which came out in the same year as one made by an
individual scholar in this country. There is also a concordance to the Revised Standard Version of the Bible,
which was published right at the beginning of our
decade and a number covering medieval works in English and German which have just come out. It seems
clear that for many scholars, using a computer has
meant making a concordance.
Another large project was the attempt to solve the
attribution problem in The Federalist Papers. Alexander
Winged Words: Varieties of Computer Applications to Literature
Hamilton and the editor of the Papers, James Madison,
had long been considered in contention for the honor
of having written a certain number of these pieces. Many
historians were inclined to give them all to Madison
despite the circumstantial evidence for Hamilton's claims
to authorship. Two statisticians, one at Harvard and one
at Chicago, decided to test the value of the Bayes theorem by applying it to this problem. With the help of a
corps of assistants, two computers and a variety of government grants, Mosteller and Wallace concluded, as the
scholars had done, that Madison had written them all.
Because their concern was in statistics rather than in
literature, their results do not have much interest for
literary scholars. The work of a Swedish student of
English literature, Alvar Ellegard, on a similar problem,
the authorship of the "Junius Letters, has been more interesting because of the information about the language
of this period that he turned up. His conclusion about
the authorship of the Letters coincided with prevailing
opinion.
The researches of the Rev. Mr. Andrew Q. Morton
of Scotland and his statistical colleagues is in a slightly
different category. They have tried to distinguish between the various Epistles of St. Paul, the genuine and
the spurious. Partly because of the manner in which his
claims were presented and partly because of some sense
among the public that the final sanctuary had been
invaded by the machine, Mr. Morton has called down
on his head the anger of a great number of people,
including even some of the members of his cloth who
are themselves using computers. Morton's results have
not been fully made public, but he seems to have also
found himself in agreement with previous, manuallyassisted, scholars in his field. The criteria he used are
not unlike those applied to Junius and the Federalistfrequency and distribution of function words in the text
-but the text he uses is necessarily less reliable than
theirs. After all, original copies of the eighteenth-century
journals still survive but the text of St. Paul is in altogether a different state. The controversy continues to
give off energy.
Questions which may be considered editorial were
tackled by two scholars who used a similar technique in
widely separated places. Both took advantage of the
computer's ability to make a great many precise comparisons in trying to decide by means of spelling which
text of Dryden or of Shakespeare had greater authority.
In a sense the procedure is like that of the concordance
maker with one important difference. A concordance
program can only with difficulty be adjusted to recognize
spelling variants of the same word. The studies just
mentioned took advantage of this limitation in discovering spelling variation.
Projects even more remote from strictly literary work
323
have been done and include a bibliographic index to
the whole run of a Spanish literary journal, a millionword corpus of modern American English-this latter
not published but stored on tape and available for consultation-and some collation and editing procedures
that are of interest only for technical reasons.
Some very ambitious pilot studies have emanated
from the workshops of Mrs. Sally Sedelow, now of
Chapel Hill. Her interest, like my own, is in computational stylistics, the study of idiosyncratic patterns in
individual writing. One of her programs converts specified verbal characteristics into graphic equivalents for
easier comparison. Thus each noun and verb in a text
could be indicated by a particular symbol, all other
words being represented by zeroes. The noun-verb distribution would then be clearly visible and could then
be evaluated. The trick of course is to think of the right
things to look at, things that will tell us something about
the text. The other program is more conventional, in the
sense that it resembles a technique already in use for
some time in the social sciences and named Content
Analysis. The General Inquirer system, only recently
applied to literary problems is a well-known example
of a computer implementation of this technique. In essence, it consists of a thesaurus of themes and categories.
If a text contains a sufficient selection of terms from a
given category, it is concluded that the writer was concerned with that theme. Thus Mrs. Sedelow concludes
from the number of words about lunacy (mad, madly,
madness, insane, disease) in the first act of Hamlet that
Shakespeare had this in mind when he wrote the play.
Doubtless more esoteric conclusions can be reached by
studying word-clusters and word-associations. At any
rate this approach has the virtue of attacking the semantic component of language, which has been a great problem to all literary users of computers.
Not to overlook present company, I should also mention Professor Raben's well-known study of the influence of Milton on Shelley. In trying to pinpoint this
debt, he tried to find how often in any sentence, Shelley
used Milton's actual words. Contrary to his most optimistic estimates, he found an amazing number of such
uses, clearly demonstrating the extent to which the later
poet had incorporated into his mind the words of his
predecessor. As might also have been expected, the
handling of poems running into 200,000 words in the
aggregate caused a certain number of space problems
in the computer itself.
My own study of the style of Jonathan Swift, part of
which was done on an IBM 1620, may perhaps be
properly added to the end of this list, at least because it
was only published this year though completed in 1963.
My concern was to discover the individual features of
this writer's style and to draw some literary conclusions
324
Fall Joint Computer Conference, 1967
from this. After programming, the main technical problem I faced was the large amount of time that my listprocessing procedures were using up.
As can be seen from this list, all but a few of these"
results of applying computers to literature have produced
data sure to be useful to literary scholars-works preliminary to literary study-but are not themselves literary studies for the most part.
If we move now to work in progress as it is listed
in the May issue of Computers and the Humanities,
we find a vastly increased amount of activity. There
are 120 projects listed under "Literature," though some
scholars are responsible for more than one. Under
examination, these break down into the following components. Predictably enough, the largest class (53)
consists of concordances, dictionaries, word-lists, indexes, and catalogues of lexical items. The second
largest category (25) includes various kinds of linguistic studies, programs for analyzing the linguistic
characteristics of languages rather than of authors.
There are seven bibliographical projects and six concerned with editing, collating, formatting and text history. Another six are devoted to various aspects of
content and semantic analysis and the discovery of
keywords. Five are attribution studies and another five
are studies of meter and rhyme. Four are in machine
translation. Of the remaining nine, two represent attempts to work up programs to serve literary scholars
and are therefore really projects in information processing. This leaves seven which can be classified as
strictly literary.
The descriptions provided are not full enough to
permit complete understanding but it is possible to
hazard some guesses as to what these projects may
attempt. Two are studies of individual writers, one on a
psychological basis involving word or image clusters,
the other through his syntax. There is an attempt to
determine whether a sonnet style exists. A comparison
between a book of proverbs and a play is intended to
show the reliance of the dramatist on proverbial sayings. There is a census of the roles of actors during a
certain period to determine the nature of their specialization. And there is a study of the relation of grammatical deviation to mental disturbance, a matter of
some interest considering how many poets have been
or have been considered crazy. Except for the emphasis on linguistics, the distribution is similar to the
earlier one.
Anyone who was not aware of the computer implementation of these projects and compared them to
those recorded in such a Bibliography as the one
published annually by the Modern Language Association might reach the conclusion that a revolution in
the study of literature had taken place. Nearly half of
the projects devoted to making reference-lists, nearly
a quarter to linguistics! To be sure, the two samples
differ considerably in size. The current issue of the
PMLA Bibliography, recording almost exclusively
items published in 1966, contains more than 20,000
entries covering work on all the major European languages since the Middle Ages. In it there is a small
sub-sub-section on Computer-Assisted Literary Research, which contains some forty items, some of them
merely general or popular exphnations. At most this
activity represents a very small fraction of the admittedly excessive total: one-fifth of one per cent, or one
literary scholar in 500 is working with computers.
Because there is no classification of the items by
type in the PMLA Bibliography, it would be very timeconsuming to draw up a table, similar to the one just
presented, for the efforts of traditional scholars. A
casual examination of a random 120 items reveals,
however, a predominance of historical studies of texts
and documents, related social and political investigations, explications and· criticisms of individual works,
as well as some stylistic and linguistic studies, probably
based, as is generally the case, on inadequate data.
Without question, a number of all these studies could
have benefited considerably from the data-gathering
and data processing power of computers. In fact, it is
probable that some studies are of doubtful validity
because of the unrepresentative nature of their database. Traditional literary scholarship is notorious for
extrapolations that go vastly beyond the data and even
for conclusions reached without primary data of any
sort.
What this suggests about the relationship between
traditional and computer-assisted literary research is
that both kinds of scholars seem to be pursuing the
same ends but that what I may perhaps call the "modern" scholar has in the main limited his scholarship to
certain kinds of preliminary work which is the basis
for conclusions of a more far-ranging character. Concordances and the like permit studies of works and
authors to be more soundly based. Attribution studies
enable the critic to feel more positive about the canon
of an author's work. But all these studies ultimately
serve the same master. To be meaningful they must
stand in a certain relation to the basic critical questions which determine the nature of any art.
What are these literary questions to which such deference must be paid? They are all· primarily founded
on the aesthetic aspect of human activity, the third
member of the Platonic trinity of the good, the true
and the beautiful. More specifically, literary criticism
and scholarship must concern themselves with distinguishing between the aesthetic and .the everyday,
good literature and bad, poetry and mere verse. In so
Winged Words: Varieties of Computer Applications to Literature
doing, the scholar must give his attention to the nature
of the aesthetic effect, the creative activity of the writer
as opposed to the merely routine aspect of communication. This question was, until recently, unique with
literature because its practitioners use the same language in writing odes and sonnets as is used in the
daily newspaper, the freshman theme and manuals of
instruction for computers. Pop art (the conversion of
tomato soup cans and giant hamburgers into the substance of art), the underground film (the 8-hour showing of a man sleeping), and certain tendencies in music
(the bizarre use of musical silences and ugly sounds),
have, however, eroded the uniqueness of this feature
peculiar to literature. These other arts have now been
compelled to take a stand on the basic aesthetic question "What is art?"· before being able to arrive at the
next one, "What is good art?"
For literary students, the basic question remains
"What is literature?" In the process of trying to answer
it, the scholar finds himself dealing with a variety of
subordinate questions, the answers to which he hopes
will lead him to solve the main one. A favored form
of the basic question about literature is "What is the
meaning of this play, this novel, this lyric poem?" This
question branches out into other questions of meaning:
of words, phrases, themes, plots, symbols, stylistic
devices . . . . Questions of meaning are, as the linguistic philosophers have shown and as everyone now
knows, very difficult to answer. In part this is because
the verification of problems of meaning is not empirically possible, as meaning is an abstraction at a certain
remove from the events under examination. Disagreements about meaning, about the interpretation of literary works, abound In literary study. In a sense every
interpretation is correct or at least justified since it may
be supported by a proper selection of evidence and
since there is no established priority governing the evaluation of evidence. Thus literary interpretation generally depends for its effect on the persuasiveness with
which the selection of evidence is presented and it usually relies for its acceptance on a certain set of beliefs
or expectations common to the interpreter and his
audience. For example, the question "What does Hamlet mean?" has been answered in this century by reference to the possible incestuous relationship between
Hamlet and Gertrude and Hamlet's supposed Oedipus
complex, which in turn have ·been traced to some emotional difficulties in the playwright. But other meanings
of Hamlet have been successfully defended which are
supported by a different selection of evidence.
As is well known, there can be no progress in interpretation. Explications survive for as long as the willingness to believe the theory on which they are founded
persists. When the winds of critical doctrine change,
325
what was previously acceptable-:-theory, interpretation,
evidence-is swept away to be replaced by the newer
thing. This is a discouraging state of affairs but one to
which literary scholars have become adjusted. Their
way of adjusting to this fluid and unstable situation is
by the reduction of big problems to little ones, by
the conversion of why questions to how and what
questions.
Preliminary to any inquiry about the meaning of a
given work is usually a set of subordinate questions,
some of which may seem rather remote from the main
event. Thus, the study of Hamlet implies the study of
the medieval theatre, beliefs about lunacy, ghosts and
family relationships, the sources of this particular play,
the shape and appointments of the Elizabethan playhouse, Shakespeare's life, his philosophy as it is reflected in the speeches of his characters and in his
imagery, his language as it differs from or corresponds
to the language of the playwrights and writers of his
time, and an innumerable list of sub-questions. Presumably, when all the evidence is in on these lowerechelon matters, the main question-"What is the
meaning of Hamlet?"-can be tackled, unless someone
comes along with a critical theory that denies the possibility that plays or other literary artifacts can have
meaning, apart from mere existence. The words of a
modern poet record this position of critical nihilism:
"A poem should not mean but be."
Without an unceasing concern for the ultimate necessities, the questions of meaning and value, any
study is in danger of becoming merely the trivial sorting of artifacts, the solving of puzzles or riddles no
more significant than a newspaper crossword. In other
words, literary scholarship, computerized or traditional,
must be informed by this concern for what literature
is and means and for the things that literature springs
from and tries to illuminate. Computer scholars are
more vulnerable to such a danger than traditional
scholars because the traditional tools of researchcards, files, pencils and typewriters-do not exercise
the dangerous and autonomous fascination that the
electronic data-processors do. The computer study of
literature always threatens to take over the scholar,
who becomes seduced by the ease with which it can do
certain things into abandoning his real goals and responsibilities. At the same time, he is subject to another
sort of accusation which is quite the opposite. If he
uses a computer, he is expected to solve all the outstanding problems of literature, simply because the real
accomplishments of the computer and the efforts of
the manufacturers' public relations men have accustomed the public to expect decisions, solutions and
miracles from the computer, as a matter of routine.
Anything less counts as a failure. These and other
326
Fall Joint Computer Conference, 1967
jeopardies face the literary scholar who has turned for
help to a computer.
The problem is truly paradoxical. The traditional
. literary scholar cannot solve the great problems unless
he first solves the small ones. These invariably consist
of the accumulation and compilation of data, minute
in size and immense in quantity. H he immerses himself in these, he is very likely to lose sight of his
original purpose. If he does not, his conclusions are
mere baseless speculations. To this paradox, the computer can bring a solution because of its ability to
undertake the drudgery required for answering the
subordinate questions.
Nonetheless, it is difficult to escape the conclusion
that ·computer-assisted literary scholarship has until
now been woefully conservative. It has done little to
exploit the machine's genuine possibilities for qualitative innovation. It has largely limited itself to the
mere quantitative aspect. These efforts will doubtless
earn some praise as the results become available and
useful to the community of scholars, but they will not
inspire other scholars to emulation because the results
are not truly inspiring or exciting. Not until the computer scholar turns out results which diverge sharply
from what has been done before will he earn the respect and interest of his traditional colleagues.
One explanation of the conservative nature of the
computer-assisted projects has to do with the relationship between the scholar and the machine. H~ has
learned to think of it as a highly efficient but bramless
clerk--despite everything written about artificial intelligence. Therefore he has entrusted it with merely
clerical tasks. Moreover, he has usually employed an
intermediary to convey his instructions because he is
not himself sufficiently conversant with its language to
do so himself. In a sense, therefore, he is doubly dependent and doubly limited: he has a foreshortened
view of the computer's abilities and he must depend
on the understanding of another person to express his
needs. He must free himself of both these limitations
if he wishes to make his scholarship creative. Both, it
seems to me will yield to the one cure: the scholar
must learn to be his own programmer. That is axiomatic. He cannot learn what the computer can do if he
has to ask another to interpret for him. With the
development of new high-level languages like SNOBOL, competence in which can be acquired even by
the stiff reflexes of the middle-aged scholar, though not
without effort, there can be no excuse for remaining
technologically illiterate. The scholar who familiarizes
himself with the means of communicating with his
computer will learn at the same time how extensive
are its possibilities, how untried its opportunities.
The aims of humanistic scholarship, according to
the recent words of a well-known classicist, should be
primarily educational. They should, that is, instruct the
scholar and enlighten his instruction, especially in the
sense that a knowledge of the past can help one to
judge the present. If the fulfillment of the literary
humanist lies in this sort of activity, the computer
properly used can make a considerable contribution.
Music and computing: the present situation*
by ALLEN FORTE
Massachusetts Institute of Technology
Cambridge, Massachusetts
Perspective
There may be those who find that the terms music and
computing form an unlikely pair. We remind them that
the monochord, a device usually associated with music,
was one of the first scientific measuring instruments.
We need not stop there. In virtually any historical period
one finds an interaction between music and science and
mathematics. With respect to the seventeenth century,
for example, Claude Palisca has observed:
In any discussion of science in the seventeenth
century, among the names that inevitably arise are
those of Galileo Galilei, Marin Mersenne, Rene
Descartes, Johannes Kepler, and Christian Huyghens. It is no mere coincidence that these . .. were
all trained musicians and authors on musical subjects ... because music until the seventeenth century was a branch of science and held a place
among the four mathematical disciplines of the
quadrivium beside arithmetic, geometry, and astronomy.1
The interaction has not been uncontroversial. In the
fourth century B.C. Aristoxenus, one of Aril:!Lotle's most
eminent pupils, took issue with the Pythagoreans, who
maintained that the science of harmonics, regarded as
central to music, was based upon numerical relations.
Aristoxenus asserted that a rational interpretation must
take into account the more basic fa9tors of sense-perception and memory. This view was echoed by the celebrated mathematician and encyclopedist, D' Alembert, in
the preface to his treatise on Rameau's theory of music:
One can consider music either as an art, the purpose of which is to provide one of the principal
*This is a summary paper. The author's own work, to which
passing reference is made, was supported (in part) by Project MAC, an M.I.T. Research Project sponsored by the Advanced Research Projects Agency, Department of Defense, under Office of Naval Research Contract Nonr-4102(Ol).
pleasures of the senses, or as a science by which
that art is reduced to principles. 2
A nineteenth-century scientist took a simpler view (and
one perhaps substantiated by the current commercial
musical product) :
I conclude that musical notes and rhythms were
first acquired by the male or female progenitors of
mankind for the sake of charming the opposite sex. 3
Although the association has sometimes been ludicrous ~r even fraudulent, the point is that some aspects
of musIc have long been involved with science, mathematics, and technology in some way. It is not at all
strange, therefore, that a significant segment of contemporary work in music theory and composition should
be concerned with logic, mathematics, and machines.
Indeed, a natural synthesis of these seemingly divergent
enterprises is even now taking place in computer-implemented music research and composition. 4
This trend is especially evident in recent work in this
country, much of which has been inspired by the theoretical formulations of Milton Babbitt5 and set in motion
by the pioneering efforts of Lejaren Hiller and his associates. 6 Ii is now evident that an intellectual climate
exists-albeit in a very small group-such that one can
predict with some degree of certainty that computerimplemented music research and composition will continue to extend and will produce significant results.
Because of the diverse applications that have been
made or proposed, it would be pretentious to imply that
a comprehensive view of the present situation can be
given here. Nonetheless, an attempt will be made to
indicate those directions and activities that are currently
visible. Much of the work is long-range and experimental. Accordingly, it is necessary to say, once and for
all, that we are still in a pioneer stage.
Sound-generation by computer
Sound-generation by computer involves the computa327
328
Fall Joint Computer Conference, 1967
tion of waveform samples at a specified sampling frequency and the conversion of these to an output waveform through a digital-analog device, a low-pass filter,
and an amplifier. 7 For "real time" generation, which
presumably is to be preferred to the "off-line" situation
where digital computer output is converted to analog
form by a transducer separate from the computer, speed
and storage capacity are critical factors. It appears that
more effective use of the computer for sound-generation
must await hardware improvements, since the "off-line"
situation requires an excessive amount of machine time
for the production of complex sounds, while real time
generation necessitates compromises in the form of limitations upon obtainable sounds.
At present, the generation of sound by computer
affords the researcher and composer at least three interesting possibilities: (1) experiments in auditory perception-characterized by Babbitt as "the most refractory
of areas";5 (2) the study of musical "grammars";
(3) the development of original compositions. The
greatest amount of activity has occurred in the latter
category. Early credits go to Max Mathews and the
MUSIC IV program for sound-generation and to Lejaren Hiller at the University of Illinois. More recently,
computer generation has been carried out at Princeton
(by James Randall,s Godfrey Winham, Hubert Howe,
and others), at Yale (by James Tenney), and at M.LT.
(by Ercolino FerrettP and by A. Wayne Slawson).
The second category (study of musical grammars)
is relevant to contemporary work in music theory. Is
it possible to write a computer program to produce
new music in a familiar style? The serious issues and
problems involved here have been obscured, unfortunately, by the occasional efforts-dutifully recorded by
the press-to produce music that "sounds like" Mozart, Bach, Irving Berlin, etc. To my knowledge, no
such effort has been successful. (It should be remarked,
in this connection, that actual sonic output would not
tc required. For example, the computer might produce
or display a score in complete music notation.)
Music research
Under this heading come a variety of applications:
information retrieval, style analysis, study of musical
systems, and the development of music representations
for computer processing. (Most of the projects cited
below are described in more detail in the compilation by
Edmund A. Bowles listed in the references~10)
In the information retrieval category perhaps the most
impressive project is the important RILM (Repertoire
International de la Litterature Musicale), directed by
Barry S. Brook, that is b('ing carried out at New York
University Institute for Computer Research in the Humanities. l l The long-range goal of this project is biblio-
graphic control of the scholarly information about music
past and present.
Several eminent scholars are interested in patternrecognition, with a view to codifying style-characteristics
for a particular corpus of music. Among these are Arthur Mendel (the vocal works of J. S. Bach), Lewis
Lockwood (the masses of Josquin), Jan LaRue (Haydn
symphonies), and Harry Lincoln (Frottole repertory).
This work is characterized in part by what might be
called "overlay" procedures, the comparison of variant
texts for relevant similarities and differences, and thus
has an affinity to certain work being done in literary
research.
Research in what may be called, loosely, musical
systems has been undertaken by Stefan Bauer-Mengelberg and Melvin Ferentz,I2 by Michael Kassler,I3 Hubert
Howe,14 and by the present writer.I5 These projects are
characterized by a concern with combinatorial problems,
complex decision structures, and non-statistical mathematical models. I6
Both in style analysis and in the study of musi~al
systems a distinction can be drawn between "numeric"
and "non-numeric" processing. If the researcher deals
indirectly with music, that is, if his data consist of
numeric sets representing some musical property or
properties, information-loss is assumed and the problem
is usually solved in a straightforward way, using available mathematics. If he deals more directly with music,
however, the question of input data and informationloss becomes central. What is to be the object of study?
Bauer-Mengelberg17 maintains that it is the score and
makes a cogent case for a syntactic representation that
is c()mplete for any composition. Other researchers take
a more casual view and are content with incomplete or
ad hoc representations. The issue is interesting and significant, for it may ultimately affect the viability of a
research project.
The question of music representation is but one of
many we are beginning to cope with. Interpretation of
output, which involves criteria of parsimony and significance, formalization, and the development of efficient
algorithms is a matter of immediate concern. The question of appropriate high-level languages and their natural
data-structures is also in the foreground for those of us
who are active in computer-implemented research.
A look ahead
We confine our remarks here to music research, although some of them are probably relevant to composition as well.
To a large extent the future of music research vis-a-vis
the computer depends upon education. If computer-implemented research is to have a significant effect it must
be undertaken by more scholars than are now active in
Music and Computing
that area. They must be scholars of the highest rank,
well versed in subject matter and sufficiently competent
to be able to program fluently and to supervise programming, where that is desirable and feasible. It might be
noted here that the Harpur Seminar on Music Research
and the Computer, a two-week summer course directed
by Professor Harry Lincoln, represents a pioneer effort
to effect a rapprochement of music scholar and computer. 18 For younger scholars-mature graduate students
in particular-the problem is simpler. They must be
taught to use the computer as a normal part of their
formal education. This is especially important for those
in the area of music theory, but is probably also essential
for scholars whose main interests are historical-on the
assumption that even though the scholar's historical interests might be confined to the period from 1601 to
1603 he lives in the 20th century and presumably should
have access to contemporary research facilities.
It is wise to remember that many problems in music
are complex. The extent to which clata-processing technology will render solutions more accessible than do
traditional procedures remains an open question. For
example, it now appears that computer-generated
graphic displays offer new resources for the editing
proct.!dures that are central to much work in musicology. Yet, a great deal of work must be done before
machine-implemented editing can cope with the notational systems of various historical periods or with such
a complex representation of the human creative process as a page from a Beethoven sketchbook. In attempting to cope with such problems, however, we can
expect that traditional music scholarship will obtain
insights that may determine extensive critical revisions
of conventional methods and criteria.
5
M BABBIIT
The use of computers in musicological research
Perspectives of New Music vol 3 no 2 Spring-Summer
1965
6
L A HILLER L M ISAACSON
Experimental music,' composition with an electronic computer
7
8
9
McGraw-Hill Book Co New York 1959
JAMES C TENNEY
Sound generation by means of a digital computer
Journal of Music Theory vol 7 no 1 Spring 1963
J K RANDALL
A report from Princeton
Perspectives of New Music vol 3 no 2
1965
Spring-Summer
E FERREIT!
The computer as a tool for the creative musician
In Computers for the Humanities?; A Record of the
Conference Sponsored by Yale University on a Grant
from IBM January 22-23, 1965 Yale University Press
New Haven 1965
10
E A BOWLES comp
Computerized research in the humanities; a survey
ACLS Newsletter, Special Supplement June 1966
II
B S BROOK
RILM repertoire international de fa litterature musicale
Computers and the Humanities vol 1 no 3 Jan 1967
12
S BAUER-MENGELBERG M FERENTZ
Oil eleven-interval twelve-tone rows
Perspective of New Music vol 3, no 2 Spring-Summer
1965
13
M KASSLER
A sketch of the use of formalized languages for the
assertion of music
Perspectives of New Music vol 1 no 2 Spring-Summer 1963
H S HOWE
Some combinational properties of pitch structures
Perspectives of New Music vol 4 no 1 FalI-Winter 1965
14
REFERENCES
C V PALISCA
Scientific empiricism in musical thought
In Seventeenth Century Science and the Arts edited by
H H Rhys Princeton University Press 1961
2 J D'ALEMBERT
E!emens de musique
London 1772
3 C DARWIN
The descent of man
London 1872
4 A FORTE
Computer-implemented analysis of musical structure
In: Papers from the West Virginia University Conference
on Computer Applications in Music West Virginia University Library Morgantown 1967
329
15
A FORTE
A program for the analytic reading of scores
Journal of Music Theory vol 10 no 2 Winter
16
J ROTHGEB
Some uses of mathematical concepts ill theories of music
Journal of Music Theory vol 10 no 2 Winter 1966
17
S BAUER-MENGELBERG
The truth, the whole truth, and nothing but the truth
Paper read at The Computer and Research in the Humanities a conference held at the University of North
Carolina
Chapel Hill March 1967
18
J PRUETT
The Harpur College music-computer seminar: a report
Computers and the Humanities vol 1 no 2 Nov 1966
1966
Computer applications in archaeology*
by GEORGE L. COWGILL
Brandeis University
Waltham, Massachusetts
follow easily once their data were somehow "computerized." Naturally nothing really marvelous has come
out of these eady studies. Results have always been
interesting, and in some cases important contributions
to archaeological problems have been made. Yet, nothing done so far has convinced the archeological profession as a whole that there are any often-encountered
tasks or problems for which computers ought to be
used as a matter of course; that there are tasks for which
it would show incompetence not to use a computer. My
impression is that the majority of archaeologists are
still watching results of computer work with attitudes
ranging from hostility to friendly interest, and are not
going to make any real commitment either to learning
or to using machine techniques until there is more
evidence that computers can really offer economies in
the performance of familiar tasks, or that the results
of novel computer approaches are really valid and intelligible. The incidence of intelligent comprehension
of computers is still depressingly low among archaeologists of all ages, although it may be rising rapidly in
the current generation of students. I think archaeologists
really engaged in computer work have reached a "second
generation" stage where it is more fully appreciated
that a great deal of hard work, hard thinking, and
trial and error are still needed before we can make the
best uses (and non-uses) of computers, but nonetheless a stage where we have a substantial body of earlier
efforts whose successes and failures we can learn from.
It seems wasteful for either archaeologists or computer
people trying to help archaeologists to begin computer
projects today without knowing what has already been
done or attempted in archaeology. An extremely important source of information on this work is the N ewsletter 0/ Computer Archaeology.
INTRODUCTION
In preparing this paper I have tried to give an accurate general picture of the kinds of things which have
been done with computers by archaeologists and to give
some of my own views about things which most need
present a code for metal tools and weapons. An unpublished code for computer analysis of textiles, developed at the American Museum of Natural History, is
discussed by Bird. 16
The matter of developing general codes for decorations of objects, where the concern is with design elements, style, iconographic content, or subject matter,
seems far more difficult. It is an area where methods
adapted from descriptive linguistics seem very promising. Gardin1 gives a very important discussion and
illustration of some of these methods. Also very important, though not intended for immediate use with
computers, is the work of John Rowe and his students
at Berkeley,17 and of Muller. II This is plainly a topic
where archaeology and art history have many similar
needs and problems.
One application of archaeological data codes which
is somewhat distinct from their use in specific research
projects is in the "computerization" of the catalogs
of large museums. This task is under way or seriously
projected by Dee Green at the University of Missouri
and by Jaime Litvak and Felicity Thomas at the Instituto Nacional de Antropologia e Historia in Mexico
City. Irwin Scollar 19 reports that this may be done at
the Rheinisches Landesmuseum in Bonn.
Statistical studies
One reason why computers have not yet had any
great impact on ·archaeological practice is that no one
has yet completed and made available a file containing
any really large body of important data coded to include what is relevant for important problems. Probably
the largest published. file is by Christophe and Deshayes/~ which includes about 4000 metal objects, using
optical coincidence cards rather than electronic equipment. The statistical studies which have been done
so far have never been based on samples of more than
a few thousand objects (at most, a few tens of thousands if very fragmentary objects or workshop debris
are included). In many cases, of course, good samples
of this order of magnitude are quite sufficient to produce important results, but it does mean that the volume
of data processed has never been very large relative
to the millions of objects (mostly small pottery fragments) which major excavations often produce. The im-
334,
Fall Joint Computer Conference, 1967
portance of computer studies will increase greatly when
larger files of significant data are accumulated, especially as whole regions and substantial time spans come to
be covered with some adequacy. Even so, it does not
seem profitable to try to include all data on all objects excavated, and good statistical sampling design
is a matter of increasing concern. 20
Some important examples of archaeological applications of statistical techniques by computer include theuse
of chi-square and regression by Freeman and Brown;21
multiple regression by McPherron 22 and by Longacre;23
factor analysis by Jennings,24 Binford and Binford/5
Cowgill,26 Hill/7 and Benfer,28 proximity analysis by
Hodson and others;29 scalogram methods by Eliseeff;30
and automatic classification methods by Hodson29 and
De La Vega. 31
Few archaeologists have been involved in development of new statistical programs for their work. Deetz's3
work in 1960 is one exception. For a number of reasons, his work was probably more influential than any
other single project in persuading American archaeologists that computers might 'possibly be valuable for them.
Deetz addressed himself to an original and important
problem; whether the historically documented breakdown of social organization (particularly a pattern of
matritocal residence) under increasing European pressures on an Indian village in South Dakota in the
18th century might be reflected in a parallel breakdown of clustering in ceramic design elements. But it
is evident that no one with basic statistical competence
gave this work any serious attention. Many archaeologists, notably Deetz himself, are well aware that even
well-demonstrated changes in clustering of artifact design elements may not have clearcut social implications.
What needs to be emphasized is that Deetz's demonstration method itself involved computations that were unnecessarily tedious and unnecessarily ambiguous; and
should not be used as a model for further work. He
attempted to assess degrees of association among ~ross
tabulated attributes, by a technique which was ingenious but less useful than standard measures like
phi or lambda. 32
Kuzara, Mead, and Dixon33 have developed what
seems to be a very good program for the task known
to archaeologists as "seriation"-arranging a set of
units in the order which best satisfies the requirement
that the more similar any two units are, the closer to
one another they are in the final sequence. Archaeologists have had a fair amount of experience in doing this
directly by manual rearrangement of the units, so there
is already fair· understanding of the rationale, and the
convenience of doing it by computer is appreciated.
Kuzara; Mead, and Dixon's program appears to work
better than an earlier one designed for this purpose by
the Aschers. 34 It has already been applied by other
archaeologists, including a study of stone tools in Texas by LeRoy Johnson, 35 and it has good prospects of
becoming quite popular. Its only serious limitation is
that it amounts to ordering units along some one best
axis or factor. Where there is any reason to think two
or more factors may be relevant, it would be preferable
to use a multidimensional technique such as factor
analysis or something like R. Shepard's proximity
analysis. 36
In most multivariate approaches a pervasive theme
is the drive toward certain kinds of parsimony. What
are the best variables for discriminating between members of several categories, what are the best predictor
variables for some set of criterion variables, or what
are the fewest independent factors which account for
most non-random variance in some larger set of variables? In many archaeological problems these are indeed the kinds of parsimony we want. Often, though,
we really want something else; namely, the most parsimonious account of the patterning of all variables of
some set. Probably we should rely less on methods
developed for the reduction of experimental data (especially by psychologists, agronomists, and biologists),
and more on analogies with descriptive grammars.
Lounsbury's37 approach to formal accounts of systems
of kinship terminology is an especially important and
lucid exposition of this approach. Excellent archaeological work along these lines has been done by John
Rowe and those influenced by him at Berkeley, 17 working without computers. Rowe and his students have
produced results far more important than anything
which has been done so far in archaeology by computer, largely because they have applied a good method
to rich bodies of data, while computer studies have
geen short on one or both of these scores. Muller18
has also done important work in applying a generational grammar approach to a prehistoric art style. It
is likely that computers could be used to make the
"grammatical" approach more powerful and less laborrious, but this will require more hard and original
thinking, than is demanded by the adoption of readymade multivariate programs. Gardin's1 work on codes
for iconography is an important contribution in this
direction. Sackett's38 non-computer work on multiple
contingency tables is superficially quite different, but is
probably also leading in the same direction.
The general field of mathematical geography, or
mathematical analysis of spatially distributed data, is
another promising. field for computer applications to
archaeological data. Work here includes Lipe and
Huntington's use of centrographic techniques for demonstrating differences in distribution of ceramic categories,39 and the use of linear spatial filtering to im-
Computer Applications in Archaeology
prove contrast in plots of magnetometer survey data
by Scollar and Krlickeberg.'o Data smoothing and trend
surface fitting techniques are also likely to prove useful. I am currently engaged in analysis of data from
Teotihuacan, a 25 square kilometer prehistoric metropolis in central Mexico,'1 where differences between
districts within the city is one major concern. We are
working with a data matrix of 391 observations on
each of possibly 4000 units. While most of our computer work utilizes multivariate statistical methods, we
have also found it useful to produce maps by computer
of data distributions using a program (SYMAP) developed under the direction of Howard T. Fisher, of
the Laboratory for Computer Graphics of Harvard
University. By far the greatest advantage over hand
methods comes when functions of data at two or more
points must be computed, as in smoothing or filtering
procedures.
Other applications
One special field of computer work is on decipherment of ancient writing systems. An early attempt to
decipher ,Maya hieroglyphs by Evreinev, Kosarev, and
Ustinov at Novosibirsk was unsuccessful and strongly
criticized by others, including Knorozov. 42 Current work
in Mexico on a concordance of Mayan inscriptions is
not aimed toward instant decipherment and is likely to
be far more useful. '3 At least two computer projects
involving Minoan writing are presently under way."
A KWIC index of American Antiquity, a major
American journal, has been produced by Dee F. Green'S
but is not yet published. According to Irwin Scollar19
the annual and cumulative indexes of the Bonner
lahrbuch and a concordance of aerial photos of archaeological sites are all being compiled by computer at the
Rheinisches Landesmuseum, Bonn.
Perhaps the most unusual computer application so
far in archaeology is in connection with the work of
G. Hawkins, who used computed ancient stellar positions for his study of the astronomical significance of
Stonehenge. James Dow has also used this program
for research on possible stellar bases for orientations
of ancient cities and temples in Mexico.'s Undoubtedly
many more special applications of computers in
archaeology will appear, in addition to their major uses
for data storage and retrieval and for statistical and
formal analysis of data.
REFERENCES
2
J C GARDIN
Methods for the descriptive analysis of archae%gicaJ
material
American Antiquity 32 13-30 1967
J C GARDIN
Reconstructing an economic network in the ancient East
335
with the aid of a computer
In Hymes D The Use of Computers in Anthropology
Mouton & Co The Hague pp 377-391 1965
3 J DEETZ
The dynamics of stylistic change in Arikara ceramics
University of Illinois Press Urbana 1965
4 R G CHENHALL (editor)
Newsletter of computer archaeology
Department of Anthropology Arizona State University
Tempe 1965 and later
Other useful sources include:
D HYMES
The use of computers in anthropology
Mouton & Co The Hague 1965
B WARREN
Computers and research in archaeology
Dittoed 1965
D F GREEN
Computer bibliography
Machine listing available on request from the author
Weber State College Ogden Utah 1967
5 W D LIPE
Personal communication
1967
6 R G CHENHALL
The description of archaeological data in computer
language
American Antiquity 32 161-67 1967
7 R G CHEN HALL
An investigation of taxonomic systems for the storage
and retrieval of material-culture data on electronic computers
Department of Anthropology Arizona State University
Tempe 1965
8 A a SHEPARD
Ceramics for the archaeologist
Carnegie Institution of Washington Washington DC
1957
9 C R McGIMSEY D F GREEN
IBM ceramic code outline
University of Arkansas Museum 1965
lOA D KRIEGER
New world lithic typology project: part II
American Antiquity 29 489-493 1964
11 E M WEYER
New world lithic typology project: part I
American Antiquity 29 487-489 1964
12 L R BINFORD
A proposed attribute list for the description and classification of projectile points
University of Michigan Anthropological Papers 19 193221 1963
13 J D JENNINGS
Information on University of Utah computer study
Department of Anthropology University of Utah 1964
14 EM STERN
Using the IBM 7090 in the classification of ground
stone tools
Michigan Archaeologist 12 229-234 1966
15 J CHRISTOPHE J DESHAYES
Index de l'outillage sur cartes perforees: outils de ['age du
bronze, des Balkans a l'lndus
336
Fall Joint Computer Conference, 1967
Centre National de la Recherche Scientifique Paris
1964
16 1 BIRD
The use of computers in the analysis of textile data;
specifically archaeological fabrics from Peru
The American Museum of Natural History New York
1967
17 R P ROARK
From monumental to proliferous in Nasca pottery
'N"awpa Pacha 3 1-92 Dept. of Anthropology University of California Berkeley 1965
18 1 MULLER
Style and archaeology
Department of Anthropology Southern Illinois University Carbondale 1967
19 I SCOLLAR
Personal communication 1967
20 Important recent papers on archaeological sampling include Vescelius G Archaeological sampling a problem
of statistical inference
in Dole and Carneiro Essays in the Science of Culture
in Honor of Leslie A White Thomas Y Crowell New
York 1960 pp 457-70
S ROOTENBERG
A rchaeological field samplinR
American Antiquity 30 181-188 1964
G L COWGILL
The selection of samples from large sherd collections
American Antiquity 29 467-474 1964
L R BINFORD
A consideration of archaeological research design
American Antiquity 29 425-441 1964
J N HILL
Random sampling a tool for discovery
Department of Anthropology UCLA 1967
elude Vescelius G
21 J A BROWN L G FREEMAN
A UNIVAC analysis of sherd frequencies from the Carter Ranch Pueblo Eastern Arizona
American Antiquity 30 162-167 1964
L G FREEMAN J A BROWN
Statistical analysis of Carter Ranch pottery
Fieldiana: Anthropology 55 126-154 Chicago Natural
History Museum 1964
22 A McPHERRON
Programming the IBM 7090 for optimizing taxonomy
ill archaeology
Department of Anthropology University of Pittsburgh
1963
23 W A LONGACRE
Archaeology as anthropology: a case study
Science 144 1454-55 1964
24 J D JENNINGS op cit
25 L R BINFORD S R BINFORD
A preliminary analysis of functional variability in the
Mousterian of Levallois facies
American Anthropologist 68 no 2 part 2 238-295
1966
26 G L COWGILL
Evaluaci6n preliminar de la aplicaci6n de metodos a
maquinas computadoras a los datos del mapa de Teotihuacan
27
28
29
30
31
32
33
34
35
36
37
38
39
Department of Anthropology Brandeis University
Waltham Mass 1966
J N HILL
A prehistoric community in eastern Arizona
Southwestern Journal of Anthropology 22 9-30 Albuquerque 1966
R A BENFER
A design for the study of archaeological characteristics
by population genetical and psychological models
American Anthropologist in press
F R HODSON P H A SNEATH J E DORAN
Some experiments in the numerical analysis of archaeological data
Biometrike 53 311-24 1966
J E DORAN F R HODSON
A digital computer analysis of Palaeolithic flint assemblages
Nature 210 688-89 1966
V ELISEEFF
Possibilites du scalogramme dans ['etude des bronzes
chinois archaiques
Mathematiques et Sciences Humaines 11 1-10 1965
W F DE LA VEGA
Classification des tombes d'une necropole d'ltalie du sud,
sur calculateur
Proceedings of the International Symposium on Computational and Mathematical Methods in the Behavioral
Sciences Rome 1966 International Computation Centre Rome in press
Much the same point is made in a review of Deetz's
work by Spaulding
A C A merican Anthropologist
68 1064-5 1966
R S KUZARA G R MEAD K A DIXON
Seriation of anthropological data: a computer program
for matrix-ordering
American Anthropologist 68 1442-55 1966
M ASCHER R ASCHER
Chronological ordering by computer
American Anthropologist 65 1045-52 1963
L JOHNSON
Towards a statistical overview of the arclla culture...
of Central and Southwestern Texas
Texas Memorial Museum Austin Bulletin 12 1967
R N SHEPARD
The analysis of proximities: multidimensional scaling
with an unknown distance function
Psychometrika 27 125-140 and 219-246 1962
F G LOUNSBURY
A formal account of the Crow- and Omaha-type kinship
terminologies
In Goodenough W editor Explorations in Cultural
American Anthropologist 68 no 2 part 2 356-94
York 1964
J R SACKETT
Quantitative analysis of Upper Palaeolithic stone tools
Department of Anthropology State University of New
1966
W D LIPE C F HUNTINGTON
The application of some centrographic techniques to the
analysis of archaeological data
Anthropology McGraw-Hill Book Company Inc New
York at Binghamton 1964
Computer Applications in Archaeology
40
41
I SCOLLAR F KRUCKEBERG
Computer treatment of magnetic measurements from
archaeological sites
Archaeometry 9 61-71 1966
Principal investigator of this project is Rene Millon
Papers concerning the computer work include
G L COWGILL
Computers and prehistoric archaeology
In E Bowles editor Computers in Humanistic Research Prentice-Hall Inc Englewood Cliffs New
Jersey 1967 chap 6 pp 47-56
G L COWGILL
Computer archaeology at Teotihuacan Mexico 1965
Statistical and computer approaches to sociocultural interpretation of an ancient city of Mexico 1966
Evaluacion preliminar de la aplicacion de matodos a
mdquina.\· computadoras a los datos del mapa de Teotihuacan
337
Department of Anthropology Brandeis University
Waltham Massachusetts 1966
42 IU V KNOROZOV
Machine decipherment of Maya script
Soviet Anthropology and Archaeology 1 43-50 1962/3
43 J J RENDON A SPESCHA
Nueva c1asificacion plastica de los glifos Mayas
Estudios de Cultura Maya 5 189-280 Mexico City
1965
44 One is by Elizabeth W Barber Department of Linguistics Yale University The other is by Richard Morgan
and John Reich Classics Dept University of Manitoba
cited in Computers and the Humanities 1 233 1967
45 D F GREEN personal communication 1967
46 J W DOW
Astronomical orientations at Tectihuacall a case study
in astro-archaeology
American Antiquity 32,326-334 1967
Computer applications in political
SCIence
by KENNETH JANDA
Northwestern University
Evanston, Illinois
INTRODUCTION
To some, "political science" is a contradiction in terms.
They regard politics as an art which defies systematic
study and, hence, offers no basis for a "science." Others
contend, as I do, that human behavior is subject to systematic study, explanation, and prediction-and this includes man's political behavior. While the attitude of
the professional student of politics toward this issue may
still reveal his attitude toward the computer as a useful
or even "legitimate" tool in his research, the argument
over the "behavioral approach" in political science is
fast becoming irrelevant to computer applications in political research. Not only is the computer becoming a
"conventional" research tool in patently humanistic
studies like literature/ music,2 and art,3 but it is also
winning favor as a useful aid to hard-nosed professional
politicians-witness the conference held in Chicago last
spring on data processing for Republican party workers.·
Exactly how have computers been used in political
science? This paper will try to answer the question by
reviewing actual computer applications in ·three methodological categories: data analysis, information processing, and simulation. Within each of these categories, the
discussion will proceed from the more frequent to less
frequent usage of computers in political research. In
this review, relatively little attention will be given to the
techniques themselves-most of which are assumed to
be familiar to the audience toward which this paper is
directed. Instead, attention will be focused on substantive applications by citing publications of political scientists who have used computers in their research. These
citations will be illustrative of the applications rather
than exhaustive of the work done on the topic.
Data analysis
By far the most common usage of computers in political science is to analyze quantitative data on individual
actors in the political process (e.g., voters, legislators~
judges, etc.), aggregates of citizens (e.g., nations, states,
cities, etc.), and political institutions (e.g., courts, political parties, legislatures, interest groups, intergovernmental organizations, etc.) . A general introduction to recording and analyzing political data in punchcard form is
contained in my book, Data Processing: Applications to
Political Research. 5
In large part, computer analyses of these data involve
nothing more than the application of conventional statistical routines incorporated in general library programs. 6
For purposes of discussion, these routines will be separated into "bivariate" and "multivariate" analyses. But
for some types of political analysis, existing statistical
programs are of little use, which gives rise to the development and application of "special purpose" programs
for political research. This section will review, in turn,
"bivariate," "mu1tivari~te," and "special purpose" computer analyses of quantitative political data.
Bivariate analysis: Her~, the term "bivariate analysis"
includes all measures of association between two variables, be they nominal-, ordinal-, interval-, or ratio-scale
variables. 7 For much of the data that interest political
scientists, the computer is instructed merely to crosstabulate one variable against another-sometimes calculating appropriate parametric or nonparametric statistics to summarize the extent of the correlation or sometimes providing only percentages to facilitate interpretation of the relationship. Occasionally the computer holds
one or more other variables "constant" when cross-tabulating two variables, but this analysis is still essentially
bivariate rather than multivariate.
Without question, the type of political data employed
most frequently in bivariate analysis with a computer is
generated through sample survey research. Questions
about attitudes towards politics, voting intentions, and
339
340
Fall Joint Computer Conference, 1967
sociological characteristics have been employed in
countless studi~s of voting behavior and political participation. Although the results of 1,000 or more interviews
with a national sample of the electorate are invariably
recorded on punchcards, it should be pointed out that
these studies are often analyzed with unit record equipment (i.e., a counter-sorter) rather than computer. This
is especially true of the surveys done by the national
polling organizations, e.g., Gallup and Roper.
While the counter-sorter is useful for processing the
few questions asked by a commercial polling organization, it is rapidly overshadowed by the power of the
computer when the number of questions is large, as in
surveys conducted by academic research organizations
like Michigan's Survey Research Center. The SRC's
landmark study of voting behavior in the 1952 and 1956
presidential elections, The American Voter,8 utilized approximately 2,000 interviews taken before and after
each ele.ction, producing eight cards of data per
respondent in the 1952 election and nine cards
per respondent in 1956. For this increasingly popular form of research, involving many variables for a
relatively large number of cases, the computer's talents are used to generate desired cross-tabulations and
associated statistics vital to the researcher.
More recently within political science, the computer
has been used in bivariate analyses of data collected on
nations instead of individuals. The data represent such
variables as gross national product, legislative-executive
structure, number killed in domestic conflict, nature of
the party system, literacy rate, and so on. 9Some of these
variabler are patently quantitative in nature, others involve qualitative categories.
Representing one approach to computer analysis of
such data, Banks and Textor's A Cross-Polity Surveyl0
expanded a total of 57 quantitative and qualitative variables to 177 different dichotomizations of the variables
across 115 countries or "polities." They instructed the
computer to cross-tabulate every dichotomized variable
against every other dichotomized variable, printing out
only those fourfold contingency taDles that were statistically significant at the .10 level. The 1,200 page CrossPolity Survey, reproducing the computer output from
this analysis, was published as a reference source for
political scientists seeking the relationship between basic
variables on countries across the world. In the case of
such cross-national research, the number of units under
study does not justify the use of the computer as much
as its power and flexibility in cross-tabulating variables
for analysis.
Multivariate analysis: Although bivariate analysis,
constitutes the most common usage of computers in political research, the above section does not dwell on
those applications because bivariate analysis is assumed
to be relatively routine and uninteresting to those outside
of political science who are already familiar with computers. A far more interesting application of computer
technology lies in multivariate analysis of quantitative
political data.
For some reason, factor analysis has been the most
popular multivariate technique reported in the recent
political science literature within the last seven years.
One condition which accounts for the popularity of factor analysis in political research is the ready availability
of suitable computer programs. As Pinner noted in
1960:
For decades, factor analysis has been the exclusive
domain of experts,' ~he mathematical sophistication
needed and the inordinate amount of labor often
required made it prohibitive to the ordinary researcher in social science. Recently these difficulties
have been largely removed. We have now good introductory descriptions of the method written for
people of moderate statistical means. Moreover,
the presence of high-speed computers on most
larger campuses and the existence of Ucanned" programs has taken most of the work out of factor
analysis. 11
Another condition for political scientists' focus upon
factor analysis as the multivariate technique most often
applied to political data is the relatively low state of
theoretical development within most fields of research.
Factor analysis, which discloses the relationships that
underlie an intercorrelation matrix for large numbers of
variables, is well suited to "fishing expeditions" when
the researcher has few hypotheses to guide his search
for relationships among variables.
A lengthy review of substantive findings from various
factor analyses of political data is available elsewhere,12
and I will confine my treatment to illustrating the range
of applications within political science. Factor analysis
has been applied to roll call voting" in the United Nations
General Assembly/3 the United States Congress,14 various state iegislatures,15 and the French Chamber of Deputies;16 decisions and opinions in the Supreme Court;1T
survey interview responses;18 interaction patterns observed within local government bodies;19 domestic and
foreign conflict behavior within and between nations;20
election returns and demographic variables by geographical areas;21 and even attitudes of political scientists
toward their profession. 22 In fact, the use of factor analysis in political research has been sufficient to cause one
political scientist, Rudolf J. Rummel, to write a textbook
on the subject. 23
For right or wrong, factor analysis has emerged as
the principal multivariate technique in political sciencemuch as the analysis of variance has emerged as the
Computer Applications in Political Science
major statistical technique in psychology. It is interesting
to note that the conditions which promote usage of
analysis of variance in psychology-specific hypotheses
to be tested and controlled experimental conditionsare largely absent in political research, making for a
noticeable dearth of research in political science based
on multiple-way analysis of variance.
Following some distance behind factor analysis, the
most frequent type of multivariate computer program
used in political research is multiple regression analysis
-usually reported only as mUltiple correlation. More
recently within political science, attention has been given
to other techniques of multivariate analysis now available through standard library computing programs. In
particular, canonical correlation and discriminant analysis have been applied to political data. 24 Moreover, a
great surge of interest has developed in the causal inference techniques that Simon25 and Blalock26 have introduced into social research. While programs to construct
and evaluate alternative causal "models" of political
phenomena are not yet standard library items at most
computing centers, they soon will be, and the amount of
work done with causal inference can be expected to
mushroom as these programs become available.
Special purpose analysis: The causal inference programs mentioned above are not what I regard as special
purpose programs for political analysis. Causal inference is a general technique applicable to many types of
data and indeed came into political science from sociology.27 On the other hand, some problems of political
research are defined by the nature of the data and have
relatively few counterparts outside of political science.
One clear instance of this is roll call analysis; another
example somewhat less exclusively within the province
of political scientists is the analysis of transaction flows.
The recent book by Anderson, Watts, and Wilcox,
Legislative Roll-Call Analysis,28 establishes the place of
the methodology within political science and contains a
set of four computer programs specifically designed for
the analysis of roll call votes. The tasks these programs
-perform with roll call data, apart from the factor analysis application mentioned above, bear little relation to
standard statistical techniques. For instance, one program read& the voting positions of all the legislators on
a given set of issues in the Congress or state legislatures
and produces the Democrat-Republican division on each
issue, an index of cohesion within each party, an index of
party likeness on the bill, and Riker's coefficient of significance for the vote. Another program gives the Riker
coefficient of significance from marginal divisions when
individual votes are not available; a third generates fourfold cross-tabulations with corresponding correlation coefficients, measures of cohesion, and measures of party
likeness; and the last program calculates the Lijphart
341
Index of Agreement for pairs of nations casting votes in
the United Nations General Assembly.
Although transactions between units of analysis (e.g.,
notes transmitted between office workers, smiles directed
toward friends of the opposite sex, goods traded between
Indians) may be of interest to other social scientists, the
political scientist has a special stake in analyzing transaction flows. Large amounts of public data exist on the
political, economic, social, and cultural relationships
among governmental units-especially nations in the inte(national system. The availability of this information
and interest in international relations has stimulated political research into transaction flows. Findings from
transaction flow analyses among nations in the form of
diplomatic exchanges, trade, and shared membership in
intergovernmental organizations. Brams wrote his own
computer program to analyze his transaction data,30 and
also used another computer program for-the hierarchical
decomposition of his transaction flow matrices to identify subgroups of nations most closely linked together.
Information processing
In contrast to "data analysis," where input to the
computer is in numerical form, "information processing"
utilizes the computer capabilities for accepting natural
language text as input. This is an important feature of
the computer for political scientists, whose material often
resists easy quantification. Consequently, we find a considerable amount of research being done with the computer on content analysis of political documents. In addition to analyzing the content of natural language text,
the computer is also being used with increasing frequency to search and retrieve information from textual
material in machine readable form.
Content analysis: There is something about political
documents-be they speeches, tracts, treaties, or diplomatic messages-that invites content analysis. 31 Many
non-political scientists who write computer programs for
content analysis elect to apply their programs to political texts. Thus we find non-political scientists using the
computer to determine the authorship of disputed papers
in The Federalist/ 2 to locate ambiguities in the Nuclear
Test Ban Treaty,33 and to score speeches by Castro,
Kennedy, and Nixon on a set of themes or concepts. 34
Notwithstanding these varied approaches to the subject, by far the most concerted work in content analysis
of political documents has been done with the use of a
computer program called "The General Inquirer," which
was developed by Philip J. Stone and his associates. 35 As
a social psychologist, Stone was not explicitly concerned
with the application of his program to political documents, although he and his associates did carry out some
of this work. Within political science, Holsti has concen-
342
Fall Joint Computer Conference, 1967
trated the most on research applications of the General
Inquirer. 36
The General Inquirer requires some editing of the
text before analysis. This amounts to chopping off "ed"
and "ing" endings and, in some applications, adding
subscripts to important words in the sentence to identify
the "perceiver," "agent," "action," "target," and so on.
The General Inquirer then matches each work in the text
against a dictionary of terms for scoring purposes. Holsti
created a dictionary of 4,000 political terms, each of
which was rated along dimensions of affect, strength,
and activity. For example, the word "abandon" might
be rated negative, weak, and passive. The program has
several capabilities for content analysis, including the
generation of statistics concerning· the appearance of
words in the text as rated along the scales built into the
dictionary; the identification of themes according to use
of certain words or dimensions; and the indexing of certain words in the text. Holsti has applied this computer
system for content analysis to messages between key
decision makers in the 1914 crisis and to communications during the Cuban missile crisis of October 1962.37
Information retrieval: Computer programs for content analysis are designed to evaluate messages contained
in a relatively small amount of material. Information retrieval programs, on the other hand, have the function
of searching relatively large amount of material and delivering on command specified subsets of that material.
An introduction to some basic techniques in information retrieval is contained in my Information Retrieval:
Applications in Political Science. 38 Within political science, information retrieval programs have been applied
to bibliographical material, propositional inventories,
and descriptions of studies and variables stored in local
"data libraries." Examples of each application will be
presented.
Computer programs for indexing bibliographical material according to "keywords" in titles or annotations
have been applied to the behavioral sciences 39 with results comparable to their success in the physical sciences. 40 Specifically within political science, keyword-incontext (KWIC) indexing has been used to compile a
cumulative index to all articles published in The American Political Science Review from 1906 through 1963. 41
Another index has been published for all articles in the
Midwest Journal of Political Science from 1957 through
1967. 42 A far more ambitious approach to indexing the
literature on political science is exemplified by the Universal Reference System, whose scheduled "Government
and Public Policy Series" is designed as a ten-volume
comprehensive index to virtually all fields of political
science. 43 Volume I of this series, International Affairs,
has already been published. 44
Another approach to computer retrieval of biblio-
graphic material involves searching abstracts of documents according to logical combinations of keywords.
This approach is being followed at Northwestern University, where a computer program called TRIAL (for
Technique to Retrieve Information from Abstracts of
Literature),45 is being used in a "selective dissemination
of information" system for political scientists and other
faculty members interested in cross-national and interdisciplinary studies. 46 A similar system is in operation
at the University of Georgia, where political science students and faculty cooperate in contributing abstracts to
a file that can be searched with the TRIAL program. 47
It is obvious that computer programs for keyword
indexing and the retrieval of logical combinations of
keywords need not be limited to bibliographic material
but may be applied to different types of textual input.
Within political science, these techniques have been
employed in building and managing inventories of propositions dealing with political participation48 and political parties. 49 In these applications, researchers identify
and formulate the propositions, which are then keypunched for computer processing. Computer-generated
keyword indexes to variables in the propositions can be
helpful in building thesauri and clarifying terms. Programs for searching the inventory and retrieving desired
propositions provide a method for using the propositions
once collected.
One of the most promising applications of information
retrieval techniques within political science-or within
the social sciences generally-is in providing access to
data gathered by other researchers and deposited in data
repositories or "libraries." The research interests of political scientists call for a bewildering variety of data
gathered across time for political institutions and classes
of people across the world. The vast amount of time
required to collect, check, and keypunch almost any set
of political data-e.g., roll call votes in a state legislature-emphasizes the need for constructing useroriented libraries for storing and disseminating machine
readable data.
This need has been felt most clearly by those engaged
in sample survey research who want to make more effective use of the data gathered in literally thousands of
polls and surveys taken in the U.S. and abroad. Most
effort toward developing. systems to retrieve political
data has been focused on locating surveys containing
questions of interest to the researcher. The goal of such
systems is not only to identify the survey, but to furnish
the researcher with the actual questions and the column
locations in the data cards indicating where the responses are recorded. One such system for retrieving interview questions from sample surveys employs the General Inquirer;50 another adapts the TRIAL program for
this purpose. 51
Computer Applications in Political Science
Of course, the idea of retrieving data for specific research needs can be generalized beyond sample survey
data. Although the accomplishments here are not as impressive, one can cite the use of keyword indexing for
locating the substantive issues on which roll call votes
were taken in state legislatures, the U.S. Congress, and
the United Nations General Assembly.52 Working with
mainly quantitative data, Beck and Stewart have developed their own routines for retrieving biographical information on Eastern European elites. 53 An effort is under
way at Northwestern University to develop a system for
retrieving desired studies and variables from a variety of
studies, including sample surveys.
Simulation
From the standpoint of substantive political science,
the computer's major contribution may well come from
what is so far its least common application: simulation
of political processes. While computer simulation is fast
becoming a conventional tool of industrial engineering
and has entrenched itself within the social sciences in
economics and psychology, it is JUSt emerging as an aid
to theory construction in political science.
Interestingly, one of the earliest successes in computer
simulation of social phenomena occurred in political
science. Late in the summer of 1960, Ithiel de Sola Pool
and his associates simulated the results of the forthcoming presidential election if Kennedy were to meet the
religious issue head on in his campaign. 54 Using data collected from some fifty national sample surveys between
1952 and 1958 (an interesting use of a "data library" in
itself), Pool and associates constructed 480 voter
"types" based on seven different variables. They then instructed the computer to apply one of several sets of
calculations for each of these voter types, under the
assumption that party identifiers and religious groups
would te affected in certain ways because of the religious issue. The results of their simulation correlated
.82 with the actual vote for Kennedy, when the election
was held months later.
The value of simulation as a theory building tool was
not demonstrated until later, when essentially the same
model was applied to the 1964 election of Johnson
versus Goldwater. In the course of adjusting the equations and parameters for the new electoral situation,
vague notions about the campaign and expected voting
behavior became articulated, and the causal mechanism
of the election became clearer. Because the computer
will not tolerate vagueness, the researcher must understand his theory and the extent of his knowledge to write
a simulation program. By enabling the researcher to test
alternative theories, the computer offers him a way to
improve his thinking and his theory.
An even better example of the use of the computer
343
to build theory about the political process may be found
in Shapiro's and Cherryholmes' computer simulation of
the U.S. House of Representatives. 55 Shapiro and Cherryholmes devised a simulation that had both deterministic and stochastic elements. In the deterministic phase,
each member of the House in the 88th Congress was
confronted with selected bills dealing with foreign affairs and social welfare. As his background characteristics were matched against coded information on the bill,
the representative was scored as "predisposed" to vote
for or against each bill. Those men who were strongly
predisposed for or against were assumed to vote that
way; those who were not strongly predisposed in either
direction then passed into the stochastic "communication" phase of the simulation.
In this phase, each "undecided" legislator "talked"
with a certain number of other legislators, thus exposing himself to their predispositions and thus their "influence. " Who the representative talked to was determined
by calling random numbers matched against probabilities
attached to the relationship of the representative with
every other legislator. For example, the probability was
higher that he would talk to someone of his own party,
from his geographical region, on his committee, etc.
These values or parameters entered into the program
were drawn from available research studies on interactions within legislative bodies. Up to now, these studies
offered little more than isolated findings, but Shapiro
and Cherryholmes were able to incorporate their findings into a theory of the communication process within
Congress. Even in this initial attempt, their success in
building theory about the political process can be judged
from the fact that they correctly predicted the vote of the
legislators in 85 % of the cases and that their estimates
of the House's for/against split on each of some 50 bills
correlated above .95 with the actual votes.
SUMMARY
Within political science, computers have been most frequently used for relatively standard statistical analysis
of quantitative data. While the statistical treatment usually encompasses only bivariate analysis, it sometimes
extends to multivariate techniques - especially factor
analysis. The analysis of political data also requires some
special purpose programs, particularly in the case of
roll call data, but in this sense political science may not
be any more demanding than the other social sciences
and probably less demanding than the physical sciences.
Apart from statistical analysis, computers have had
numerous applications within political science to problems of information processing. Heading this list of
applications is content analysis, much of which has been
done using the General Inquirer program. Keyword indexing of titles, selective dissemination of information,
344
Fall Joint Computer Conference, 1967
and retrospective searching of abstracts have also been
done with bibliographical material in political science.
One of the most promising applications of information
retrieval techniques lies in the improved utilization of
data libraries formed to house collections of studies.
Finally, computer simulation of political processes,
while not yet a standard research technique within political science, is certain to be used more in the futurejudging from the impressive results of some simulations
that have been done.
REFERENCES
L T MILIC
Computer and the humanities
149-150 March 1967
2 G BERLIND
B S BROOK
Ibid 150-152
3 L MEZEI
Ibid 154-156
4 Electronic data processing training conference
Sponsored by the Republican National Committee Chicago 20-21 April 1967
5 Evanston: Northwestern University Press 1965
6 W J DIXON ED
BMD: Biomedical computer programs
Los Angeles School of Medicine University of California 1964
7 This distinction among different types of measurement or
sc,iIing is elaborated in Janda, op cit 168-171
8 A CAMPBELL P E CONVERSE W E MILLER
D E STOKES
New York John Wiley 1960
9 B M RUSSETT ET AL
World handbook of political and social indicators
New Haven Yale University Press 1964
R J RUMMEL
The dimensionality of nations project
In R MERRITT S ROKKAN EDS
Comparing nations: the use of quantitative data in crossnational research
New Haven Yale University Press pp 109-129 1966
lOA S BANKS R B TEXTOR
Cambridge M.LT. Press 1963
11 F A PINNER
Notes on method in social and political research
In D WALDO ED
The research function of university bureaus and institutes
for government-related research
Bureau of Public Administration University of California Berkley p 205 1960
12 R L MERRITT
Political science and computer research
In E A BOWLES ED
Computers and humanistic research
Englewood Cliffs NJ Prentice-Hall pp 90-107 1967
13 H R ALKER JR.
Dimensions of conflict in the general assembly
American Political Science Review 58 642-657
September 1964
14 C D McMURRAY
A factor method for roll call vote studies
American Behavioral Scientist 6 26-27 April 1963
15 J G GRUMM
A factor analysis of legislative behavior
Midwest Journal of Political Science 7 336-356
November 1963
16 D MAcRAE JR
Intraparty divisions and cabinet coalitions in the Fourth
French Republic
Comparative Studies in Society and History 5 64-211
1963
17 G SCHUBERT
The judicial mind
Evanston: Northwestern University Press 1965
18 C D McMURRAY M B PARSONS
Public A ttitudes Toward the Representational Roles of
Public attitudes toward the representational roles of legislators and judges
Midwest Journal of Poliitcal Science 9 167-185
May 1965
19 J D BARBER
Power in committees: an experiment in the governmental
process
Chicago Rand McNally 1966
20 R J RUMMEL
Dimensions of conflict behavior within and between
nations
General Systems Yearbook 8 1-50 1963
21 E ALLARDT
Social sources of Finnish communism: traditional and
emerging radicalism
International Journal of Comparative Sociology 5 49-72
1964
22 A SOMIT J TANNENHAUS
American political science: a profile of a discipline
New York Atherton 1964
23 A pplied factor analysis
Evanston Northwestern University Press (forthcoming)
24 B RUTHERFORD
Canonical correlation and political analysis
Evanston Department of Political Science Northwestern University (unpublished paper) 1966
I ADELMAN C T MORRIS
'Self-Help' criteria for underdeveloped countries: an operational approach
Evanston Department of Economics Northwestern University (unpublished paper) 1967
25 H A SIMON
Models of man
New York lohn Wiley especially chaps 1 to 3 1957
26 H M BLALOCK JR
Causal inferences in nonexperimental research
Chapel Hill University of North Carolina Press 1961
27 H M BLALOCK JR
Causal inferences, closed populations, and measures of
association
American Political Science Review 61 130-136
March 1967
28 L F ANDERSON M W WATTS JR A R WILCOX
Legislative roll-call analysis
Evanston Northwestern University Press 1966
Computer Applications in Political Science
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Op cit 23-26
S J BRAMS
Transaction flows in the international system
American Political Science Review 60 88-898
December 1966
R NORTH ET AL
Content analysis
Evanston Northwestern University Press 1963
F MOSTELLER
D L WALLACE
Inference and disputed authorship: The Federalist
Reading Mass Addison-Wesley 1964
R A LANGEVIN M F OWENS
Computer analysis of the nuclear test ban treaty
Science 146 11-86-1189 27 November 1964
A R CARLSON
Concept frequency in political text: an application of a
total indexing method of automated content analysis
Behavioral Science 12 January 1967 68-72
D C DUNPHY M SMITH
P J STONE
D M OGILVIE
The general inquirer: a computer approach to content
analysis-studies ;'1 psychology, sociology, anthropology
and political scic1l':e
Cambridge MIT Press 1966
0 R HOLSTI
An adaptation of the 'general inquirer' for the systematic
analysis of political documents
Behavioral Science 9 332-338 October 1964
0 R HOLSTI R A BRODY R C NORTH
Violence and hostility: the path to world war
Stanford University Studies in International Conflict and
Integration February 1964 (multilith)
Theory and measurement of interstate behavior: a research application of automated content analysis
Stanford University Studies in International Conflict and
Integration May 1964 (multilith)
o R HOLSTI
Computer content analysis in international relations research
in E A BOWLES ED
Computers in Humanistic Research
Englewood Cliffs NJ Prentice-Hall pp 108-118 1967
Indianapolis Bobbs-Merrill (in press)
K JANDA
Keyword indexes for the behavioral sciences
American Behavioral Scientist 7 55-58 June 1964
M FISCHER
The KWIC index concept: a retrospective view
American Documentation 17 57-70 April 1966
K JANDA ED
Cumulative index to the American political science review
volumes 1-57: 1906-1963
Evanston Northwestern University Press 1964
NEAL E CUTLER
K JANDA
Cumulative index to the Midwest journal of political
science, volumes 1-10: 1957-1966
Midwest Journal of political science 11 225-255
May 1967
43
44
45
46
47
48
49
50
51
52
53
54
55
345
A DB GRAZIA
Continuity and innovation in social science reference retrieval: illustrations from the universal reference system
American Behavioral Scientist 10 1-4 February 1967
20 Nassau St Princeton N J 08540
Universal Reference System 1965
K JANDA W H TETZLAFF
TRIAL: a computer technique to retrieve information
from abstracts of literature
Behavioral Science 11 480-486 November 1966
K JANDA GRADER
Selective dissemination of information: a progress report
from Northwestern University
American Behavioral Scientist 10 24-29 January 1967
W A WELSH
The TRIAL system: information retrieval in political
science
American Behavioral Scientist 10 11-24 January 1967
L W MILBRATH K JANDA
Computer applications to abstraction, storage, and recovery of propositions from political science literature
Paper Annual Meeting of the American Political Science
Association Chicago 1964
K JANDA
Netrieving information for a comparative study of political parties
In W J CROTTY ED
Approaches to the study of party organization
Boston Allyn and Bacon (in press)
E K SCHEUCH P J STONE
The general inquirer approach to an international retrieval
system for survey archives
American Behavioral Scientist 7 23-28 June 1964
A R WILCOX D B BOBROW D P BWY
System SESAR: automating all intermediate stage of survey research
American Behavioral Scientist 10 8-11 January 1967
K JANDA
Information retrieval: applications to political science
Qp cit Chap 8
C BECK D K STEWART
Machine retrieval of biographical data
American Behavioral Scientist 10 30-32 February 1967
I DE SOLA POOL R P ABELSON S POPKIN
Candidates, issues, and strategies: a computer simulation
of the 1960 and 1964 presidential elections
Cambridge M.lT. Press 1965
C H CHERRYHOLMES
The House of Representatives and foreign affairs: a computer simulation of roll-call voting
Northwestern University 1966
(unpublished doctoral
dissertation)
M J SHAPIRO
The House and the federal role: a computer simulation of
roll-call voting
Northwestern University 1966
(unpublished doctoral
dissertation)
The B8500-microsecond thin-film memory
by RICHARD H. JONES and ERIC E. BITTMANN
Burroughs Corporation
Paoli, Pennsylvania
INTRODUCTION
The computer in a B8500 modular data processing
system may be equipped with as many as 16 memory
modules, each of which has a capacity of 16,000
words of 52 bits each. The modules are self-contained
with power supplies, logic circuits, and receiving and
transmitting circuits which communicate with the
computers.
The storage unit in a memory module is mounted
in a single cabinet housing four memory frames
with planar, ferromagnetic film storage elements. The
films are interrogated in a linear select mode, in which
a destructive "read" is followed by a "write" or a
"restore" cycle. The half-microsecond memory
cycle was chosen for reasons of economy and is
not the upper frequency limit of a film memory.l,2,3
In addition, four 52-bit words are always read during
one memory cycle (fourf~tch), because one thin-film
word line embraces 208/oits.
The memory cell
The memory cell configuration was chosen which
combined the film memory's characteristic high-speed
switching behavior with a low-cost assembly technique. The packing density chosen yielded a reasonable sense signal and still allowed the employment
of mass soldering techniques for the interconnection·
between the stack and electronic circuits.
The basic cell is assembled from paired substrates
in which film spots are placed face-to-face, but separated by the word, digit, and sense conductors
in a triplate arrangement. The separation between
films is about 4 to 5 mils and tests have shown that
magnetic coupling reduces the shape anisotropy by
about 50 percent. The substrate pairs are enclosed
with continuous ground sheets which provide the return conductors for the triplate arrangement of the
word, digit, and sense line conductors. The triplate
.. has the advantage that the fields generated by the
return currents in the grounds cancel in the vicinity
of the film cells, thereby reducing the effects of the
disturbing field emanating from the neighboring word
and digit lines. A disadvantage of the triplate is that
because of this field cancellation effect, higher currents than those needed in the conventional strip line
are required to generate a given field in the center
conductor. However, improved memory cell performance and ease of assembly more than justify the increased current demand.
The magnetic thin-films are produced by vacuum
desposition of Molypermalloy onto 3-mil thick glass
substrates. The film spots are obtained by chemical
etching. The spots are placed on 25-mil centers in
the word direction and on 50-mil centers in the digit
direction. A single glass substrate contains 3072
film rectangles.
Memory plane
Memory cross section
The memory cell previously described is mechanized as shown in Figure 1. The sense-digit lines and
the word lines are fabricated from I-mil-thick Kapton, * 1/2-ounce copper laminate. The sense-digit configuration and the word-line configuration are etched
on separate pieces of laminate. The magnetic films
on 3-mil-thick glass substrates are bonded to both
sides of the sense-digit and word line laminates.
Properly spaced copper ground planes complete the
package.
Lattice construction
The basic element of the memory plane is the lattice assembly, as shown in Figure 2. Five sense-digit
line tapes and four word line tapes are aligned and
taped to a master with the ends of each tape precisely
positioned. The group of tapes is then laminated into
a lattice in a laminating press to assure uniformity
of the cross section of the assembly. Next, 3-mil glass
substrates are precisely positioned and laminated to
*A registered trademark of the E. I. du Pont Company
347
348
FaIl Joint Computer Conference, 1967
adhesive system is intermediate, and (3) the substrateto-lattice laminating system requires the lowest temperature.
~
GLASS-EPOXY BACKING BOARD
WORD LINE RETURN PLANE (Cu.)
SENSE-DIGIT
APE
Z{
'\{
3 MIL. GLASS
~FI LM
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~
l
SENSE-DIGIT TAPE (1/20l.Cu. ON 1MIL."H"FILM)
COPP£R
rTHERMOSETTING ADHESIVJ;_AND INSUL ATION S
WORD LINE TAPE(1/20Z.Cu.ON1 MIL "H FILM)
I
WORD LINE
TAPE
1
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3 MIL. GLASS
NI-FeFI LM
WORD LINE RETURN PLANE (Cu.)
(
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>
SPUT
DIGIT
LINE
The sense-digit cross section
Figure 3 illustrates the basic relationship of the
sense and digit lines. This configuration was chosen
to allow packaging of the digit drivers and sense
amplifiers at opposite ends of the plane. The sense
line crossover provides digit write noise cancellation. Assembly of four of the previously described
lattices is illustrated in the exploded view. The triplate transmission line is mechanized with two outside
ground planes (2-ounce copper laminated to glassepoxy backing boards) and a solid copper inside
ground plane. The inside and outside ground planes
are electrically tied together at the periphery of the
lattice.
The sense-crossover and digit feedthrough is made
by using a three-level multilayer board assembly. The
end-around functions are made by using an etched
section of Kapton laminate wrapped around a glassepoxy backing board. Sense-digit lines are terminated
in printed-circuit boards which provide the connector
interface to the digit drive and sense circuitry.
Figure 1 - Memory cell crossection
Word line cross-section
Figure 4 illustrates the basic relationship of the
word lines in the memory plane. Triplate transmission
line characteristics are maintained with the same inner
and outer ground planes as previously shown in the
sense-digit cross-section. The shorted end-word line
is fabricated by soldering the bussed end of each
word line tape to the inside ground. The word lines
are placed on 25-mil centerline connectors but, because of the relative unreliability of 25-mil centerline connectors, the word lines are permanently tied
to a printed circuit board which holds an 8 x 8 wordselection transistor matrix that permits a reliable connector interface on 0.1 OO-mil centerlines.
Figure 2 - Assembly of lattice
the lattice. Assembly criteria require that all portions
of each intersection of a sense-digit group and a
word line be covered by the corresponding magnetic
bit. Special care is required to keep the magnetic
film in intimate and consistent contact with the lattice. A gradated system of adhesives is used to maintain alignment during later laminating operations:
(1) the copper-to-Kapton bond requires the highest
temperatures, (2) the word-line-to-sense-digit tape
Plane assembly techniques
Although the connector interface of the memory
frame utilizes well-proven commercial connectors,
the great number of solder connections necessary
within the plane required a new connection technique
that was both reliable and economical. The design
of the memory plane internal connections was standardized using a process that can simultaneously
solder many joints at a time. In each case, the end of a
copper-Kapton hlminated tape is reflow-soldered to a
mating printed-circuit board. The etched copper-
The B8500-microsecond Thin-film Memory
349
CROSSOVER
(5 REQUIRED)
DIGIT BALUN BOARD
(5 REQUIRED)
OUTSIDE
GOUND PLANE
(4 REQUIRED)
LATTICE
LAMINATION
(4 REQUIRED)
DIGIT
END AROUND
(5 REQUIRED)
INSIDE
GROUND PLANE
(2 REQUIRED)
SENSE END ARQUND
(5 REQUIRED)
P2??22;););;;;;;)21
SENSE
TERMINAL
BOARD
(5 REQUIRED)
.v22222222222222??4
CASTING
ELECTRICAL EQUIVALENT
OF PLANE
SENSE LINE
Figure 3 - Sense-digit lines crossection
--woRD DRiVE"'LiNe: - -
Figure 4- Word line crossection
Kapton laminate and the printed-circuit board are
then solder-plated to a closely controlled thickness
and the plating is reflowed in hot palm oil.
A soldering machine was designed to apply a sold.~r
ing blade to the Kapton side of the copper-Kapton
laminate with the proper heat, timing, and distribution of pressure. The machine also provides the
back-up and hold-down devices to ensure consistent,
reliable reflow-solder joints. The heat is transferred
through the Kapton to the plated conductors on the
other side. These conductors have been previously
aligned with plated conductors on the printed-circuit
word. The temperature is adjusted for reflow of the
solder. at the interface of the conductors to be joined.
To provide the maximum strength and reliability of
the joint and a minimum of solder splashing between
conductors, the following must be earefully controlled:
temperature, pressure, cooling cycle, method of holddown while cooling, and quality and thickness of
solder plating. The plane can be indexed under the
soldering head to previously set stops. The solder
blade applications required for intraconnection of the
plane can be made in less than one hour.
M emory circuits
The electrical interface and the logic functions are
made using CTJLL microcircuits. The current drivers
and sense amplifier~ are assembled in hybrid form
utilizing Cermet silk-screened register-conductor
patterns on alumina substrates. Semiconductors and
capacitors are hand-soldered to the circuit chips.
350
Fall Joint Computer conference, 1967
Word drivers
Current to each word line is supplied by 1024
transistor switches which form a 32 x 32 matrix. The
matrix is packaged on 16 multilayer cards containing
64 transistors each.
The 32 emitter drivers and the 32 base drivers energize the appropriate rows or columns in this matrix.
All transistor switches are normally reverse-biased.
Word current flows in a selected line when the emitter-output transistor saturates and supplies a negative
current pulse to the appropriate emitter lines while
the associated base driver removes the reverse bias
from the selected transistor switch. A resistor be·
tween the emitter-driver output and the matrix controls the current amplitude. The word current has an
amplitude of 600 ma ±10 percent and a rise and fall
time of 15 to 20 ns with a duration of 150 ns.
The 32 emitter drivers and the 32 base drivers are
packaged 8 to a card onto 4 printed circuits each.
These 8 driver cards and the 16 word-matrix cards
are interconnected through a multilayer backplane
which forms part of the memory frame. (Refer to the
subsequent paragraph and illustration describing
the memory frame~)
Figure 5 - Memory frame
Digit drivers
The digit drivers provide currents of either polarity
and determine the future state of each memory cell
after the word has been written into the stack. Digit
current turn-on occurs while the word current
flows and ends after the word current terminates.
The digit currents are supplied from two saturatedoutput transistors: one a PNP type for positive currents and one a NPN type for the negative currents.
The digit lines are shorted and resistors placed between the output transistor and the digit line control
the current amplitude. The digit current has an amplitude of 150 ma ±10 percent, and a rise and fall time
of 20 ns with a duration of 100 ns.
Figure 6 - Sense amplifier board
Sense amplifier
The nominal sense signal of ~ to ~ millivolt amplitude is amplified first by two differential stages followed by a threshold amplifier. The differential stages
and the threshold amplifier are packaged on one hybrid chip each. The differential amplifier has over
45 db common rejection, eliminating the need for
transformers at the amplifier input.
Memory frame
The memory frame shown in Figure 5 is made up
of the memory plane and the memory circuits. Be-
Figure 7 - Word address assembly
The BS500-microsecond Thin-film Memory
cause of the large ratio of power iIllpressed on the
memory to power-out of the memory and the proximity of conducting lines that allow crosstalk to occur.
the memory electronics must be placed physically
as close to the plane as possible. For this reason, the
digit drivers, the sense amplifiers, and the word-address drivers are packaged integrally with the plane
to form a memory frame. Each 1024-word X 20S-bit
frame has an interconnection level at the logic level
(Fairchild CTJLL).
The sense and digit circuit packaging is illustrated
by the typical assembly shown in Figure 6. The sense
amplifiers and digit drivers are each packaged on a
hybrid circuit. The hybrid assemblies are plugged
into receptacles on the mother board. The sense
amplifiers and digit drivers are packaged on mother
boards in groups of 22.
The 32 X 32 matrix which forms the 1024-address
system for the memory is packaged as shown in Figure 7. The assembly interconnects the S x S matrix
selection boards, which are a part of the plane, into
a 32 x 32 matrix. The assembly also houses the 32
base and 32 emitter drivers which drive the word
selection matrix. The interconnections for the
selection matrix are fabricated using a 12-level multilayer printed-circuit - board which maintains all interconnecting lines at 100 ohms characteristic impedance.
351
Memory organization
The 16',000 words of 52 bits each are stored in 4
thin-film memory planes as shown in the block diagram, Figur~ S. Each plane has a capacity of 1024
words of 240 bits each, of which 20S bits are activated
and the remaining 32 bits act as spares if needed. A
film word line stores four computer words and every
read cycle interrogates four words.
A 1024-word film plane contains word drivers, selection matrix, digit drivers, and sense amplifiers. The
four planes share the address register, the information
register, and the timing and controls circuits.
New words are written into the memory in 52-bit
groups. If desired, all 20S bits can be loaded into the
information register in four steps requiring 300 ns,
after which all 20S bits are written into the selected
address.
M emory timing
A memory cycle (Figure 9) begins with ~n initiate
pulse and the gate pulse is sent to the selected base
drivers 75 ns later. The emitter drivers receive their
selected gate pulse at 100 ns. Emitter current to the
matrix flows at 130 ns. Word current in the selected
line interrogates the films at 140 ns. Sense signals
appear at the differential amplifier output stages at
160 ns. The strobe pulse gates the sense signals into
ADDRESS
INPUT
MAR
MIR
OUTPUT
208
MEMORY INFORMATION
REGISTER (MIR)
STROBE
GATES
WORD
D
208
STROBE
PULSE
BASE
GATE
STROBE
PULSE
MAR
208
WRITE
GATES
208
WRITE
DIGIT GATE
WRITE
Figure 8 - Thin-film memory block diagram
DATA INPUT 52
352
Fall Joint Computer conference, 1967
The memory stack
START• INITIATE MEMORY CYCLE
NANOSECONOS
200
3;xl
100
0
~
t==-ll=I- I-- 190
EMITTER DRIVER GATE
EMITTER CURRENT
f--lOO - , " - ' 5 0 ~
f - - 130 f---*--I50 ~
WORD CURRENT
150~
'--140
'0'
r--I60
SENSE OUT (DIFF.AMP.)
SENSE OUT (TIflESHOlD AMP.)
.----185
STROBE PULSE
.----195
---."
-..$. K:DIGIT
~.
WRITE
~NOISE
240
>-<
DIGIT}- t - WRITE
NOISE
\
210-
~
---- ----- 1'-----
~IOO
DIGIT GATE
DIGIT CURRENT
500
-~
SASE ORIVER GATE
INFORMATION REGISTER
400
230
:l[
Each memory frame contains 1024 words, 208 bits
long. Four of these frames are interconnected at the
logic level. The associated circuits which these four
frames share are packaged in a configuration similar
to a memory frame. The interconnection is as shown
in Figure 8. The frames slide into articulating connectors which are mounted on interconnecting controlled-characteristic-impedance multilayer printedcircuit boards. By opening an articulating connector
at both top and bottom, any frame can be slid out for
maintenance or replacement.
lOO~
---
__I
Figure 9 - Thin-film memory timing diagram
CONCLUSION
Fabrication, assembly, and operation of these halfmicrosecond memories has proven that large numbers
of reliable film substrates are producible and that
the completed memories can compete in both speed
and price with the high-speed 2-1/2 D-type core
memories. The future for planar films looks very
bright; both larger and faster memories are in the
design stage. These memories will combine the economic advantages of batch fabrication with the fast
switching properties of thin-films.
ACKNOWLEDGMENT
Figure 10- Sense signal waveform
the memory information register at 1.95 ns. The read
data appears at the information register output before
210 ns. The restore or write cycle begins with the digit
gate pulse at 215 ns. Digit current begins to flow in
the plane at 230 ns and lasts for 100 ns. Word current
turn-off occurs before digit current termination at
285 ns. Digit current turn-off at 330 ns completes the
memory cycle. The additional time to make up 500 ns
is needed to allow the sense amplifier to recover from
the digit write noise. Typical sense readout signals
from the memory stack are shown in Figure 10.
The authors wish to express their appreciation to the
many people who were responsible for the successful
completion of this project-especially to J. T. Lynch
and V. Z. Smith for project management; to R. Benn,
E. Trimbur, J. Engelman, and A. Hardwick for film
production; to A. Bates, W. Wikiera, and L. Fiore
for electronics design; and to E. Duckinfield and
R. Saunders for mechanical design.
REFERENCES
S A MEDDAUGH K L PEARSON
A 200-nanosecond, thin-film main memory system
AFI PS Conference Proceedings 29 281-292 1966 Fall
Joint Computer Conference
2 E E BITTMANN L ARNDT J W HART
A 20-MHz NDRO thin-film memory
To be published in IEEE Transactions-Magnetics
3 E E BITTMANN
A 16K word, 2-Mc magnetic thin-film memory
AFI PS Conference Proceedings vol 26 pp 96-106 1964 Fall
Joint Computer Conference
Bit access problems in 2-V2D 2-wire memories
by PHILIP A. HARDING and MICHAEL W. ROLUND
Bell Telephone Laboratories
Naperville, Illinois
INTRODUCTION
The obvious cost advantage of a 2-wire 2-1/2D core
mat over a 3-wire mat has, in the past, been offset by
the increased complexity of the access and detection
circuitry required for a 2-wire array. This paper will
concentrate on 2-wire bit accessing schemes and
describe one which appears to be cheaper and less
noisy than the conventional bit access which uses a
complete matrix per bit. It will then discuss the readout noise problems. To predict the amplitude of noise
a multi state core model similar to J. Reese Brown'sl
will be developed. The paper will then show how the
individual core characteristics can be extrapolated to
predict overall optimum memory performance.
2~D
BITS
I· ...... ·24
BIT ACCESSING
INDEPENDENT BIT MATRIX
ORGANIZATION
I···· . ·16
I······· ·16
FIG.I B
SEGMENT
SElECTION ORGANIZATION
1·······24
Extrapolation 0/2-1/2 D memories/rom
2 D memories
The line drawing of a 32,768 word, 24 bits per word,
2-wire memory (Figure 1A) and the extension into
two types of 2-1/2D (Figure 1B and Figure 1C)
illustrates the derivation of both the typical 2-1/2D
configuration2 and the 2-1/2D configuration proposed
in this paper.3 In the 2-wire scheme, there are as mal)Y
independent address lines as addresses and as many
bit lines as bits per word. The example shown illustrates 32,768 address or word lines and 24 bit lines.
Current on a selected address wire fully switches all
cores whose signals are readout on the independent
bit wires. Coincident currents on the selected address
line and the independent bit lines are used to write
back independent bit information into the selected
word.
The first type of 2-1 /2D memory which we call an
independent bit matrix organization, segments each
of the bit lines (typically 16 segments as shown in
Figure 1B); independent selector circuits, one for each
bit, are used to simultaneously select a segment for
each bit. Since the bit lines ·have been segmented, the
number of word lines can be reduced by a factor equal
to the number of segments. The memory is read by
I········· 24
30.720
FIG.1A
FIG.1C
Figure 1-(a) Word organized, 32,768 word by 24-bit memory.
(b) Conventional 2-1/2D realization of (a). (c) Segment organized
2-1/2D realization of (a)
sending a word current into the selected word line
and simultaneously sending a bit current into the
chosen segment of each bit. This achieves a coincident
current selection of a core for each bit line. The bit
segment selector circuits, although simple in function,
are expensive and needlessly repetitious because there
is a simultaneous decoding in each of the 24 bits; each
selector making the same logical selection. For the
memory on Figure 1B, the one out of 16 selector circuit requires at least 8 bidirectional or 16 unidirectional switches per selector and since there is a selector per bit, this scheme will require 192 bidirectional
or 384 unidirectional switches.
353
354
Fall Joint Computer Conference, 1967
A second form of 2-1/20 is a simple rearrangement
of the segments as shown in Figure 1C. In this case,
the adjacent segments of 24 bits are grouped rather
than the 16 segments of each bit. The two-dimensional
memory section called segment 1 in Figure 1A maps
into the segment 1 section of the 2-1/20 memory in
Figure lC; the higher numbered segments map correspondingly. A single group selector circuit is activated
and current is simultaneously sent to the 24 lines of
the segment associated with that selection circuit.
Word current is then sent to a selected word line. The
simultaneous word current and bit segment currents
select 24 cores in a word for readout. The group selection circuit is obviously a higher power circuit since
it must deliver current to 24 lines but it has a much
reduced logic decoding. A single one out of 16 selection must be made to pick the proper group selection
circuit. This scheme, as will be shown later, can be
realized with a total of 8 switches rather than the 192
or 384 in the alternative 2-1/20 memory, without
materially affecting other component counts.
2~D MEMORY WITH
INDEPENDENT BIT MATRICES
lIT DI'UIS
lIT UUlIT --- 24
MATI'ClS
IUOOUT
MUIICU
IUDOUT
OlT(CTOIS
'15UI£ 2A
-Ji----
_____12._~~Dllm
~!'~!.!--j
IILUIS
I
1I01l£C1I0UL
s.nun
•
I
I
I
:
:
,
I
I
I
In
:
I
M(MOIT
-----iiiiS-----
I ndependent bit matrix
1
A block diagram of the independent bit matrix
organization is shown in Figure 2A. There is a word
access selector shown at the left. The bit selection
circuitry is made up of 24 independent matriees, one
of which is schematically depicted in Figure 2B. The
load at each matrix crosspoint contains two memory
lines connected by a readout transformer, which also
balances the bit current. The bit circuitry contains
a total of 384 readout transformers, one for each pair
of memory lines, 96 bidirectional switches, 192 unidirectional switches, and 768 bit access diodes. In
addition, there must be some means of funneling the
secondaries of the 16 readout transformers per bit
into a readout detector. This could be done by using
a low level selection switch per transformer for a total
of 384 switches. At the expense of some loss in signal,
one can connect several transformer secondaries in
series as shown in Figure 2C, and thereby reduce the
number of low level selectors required. In practice,
it would be undesirable to connect more than four
secondaries in series since the signal must then pass
through the equivalent of 8192 cores. Therefore, at
least 96 low level switches are needed.
Segment oriented bit access
The segment selection organization depicted in
Figure 1C can be implemented by the configuration
shown in Figure 3. The typical bit matrix of Figure 2B
is replaced by an assembly of 16 diode bridge rails, one
of which is activated to select a pair of memory lines
2
TlUUU:ns lu.AJ lu.AJ
3.
M(UIY LlIlS
11
lu.AJ Lu.J Lu.J Lu.J lu.AJ Lu.J_____LuJ lu.AJ lu.AJLuJ
nPiCAL IUODUT
fIC. 2C
MATlII
Figure 2-(a) Conventional 2-1/20 memory. (b) Typical bit matrix.
(c) Typical readout matrix
for each bit. All of the diodes except for those associated with a selected rail are back biased by the +v
and -v potentials shown on the left of Figure 3. This
automatically isolates unselected bit lines so that the
bit current driver will not send current through these
segments and signals generated on the segments will
be isolated from the readout transformer at the top.
The selected rail is activated by driving current
through the primary (shown in Figure 6) of the transformer associated with the selected rail. This forward
biases all diodes on that rail and provides a phantom
ground to the lower ends of the pair of memory wires
in each bit associated with the selected rail. This
provides a current path for the bit driver and a signal
path for readout to the transformer at the top.
This technique eliminates the need for low level
selectors and requires only 24 readout transformers.
For the short bit line segments being considered here,
the transmission time of a bit line is short compared
to the switching time of a core. Hence the effect of
signal reflections due to the 15 open-circuited lines
paralleling the selected line is slight. The capacitive
Bit Access Problems in 2-1/2D 2-Wire Memories
355
Multi-dimensional access
The capacitive limitations imposed by paralleling
many memory lines can be reduced by using the technique illustrated in Figure 5. The 16 pairs of lines of
a given bit are divided into two groups, each of which
is connected to a separate readout-balun transformer.
The desired pair of bit lines is selected by simultaneously activating one of eight rails at the bottom
and either Rail A or Rail B at the top. This method
effectively halves the parasitic capacitance seen by
the bit driver.
COl(
PUNE
i-
BIT 1 _ _ :
- I I T 2 __ _
TO IIEXT
liT
;~§~~~~~~~;;;:::
RAIL
SEL£CTIOI
.. ATRIX
16 POS
Figure 3 - Group selection circuit with inherent readout selection
loading of these 15 lines on the selected line will tend
to degrade the current rise time, but this can be
minimized by sectioning the access into a multidimensional configuration which will be described
later.
0100£
RAILS
--
Figure 4-Group selection circuit without inherent readout
selection
Alternative organization
Rail selection matrix
There is an alternative organization which utilizes
half the number of diodes, but increases the number
of readout transformers. This scheme shown in Figure 4 is almost identical to the scheme shown in
Figure 3; it contains 16 pairs of rails, but instead of
having front and back lines independently connected
to their own diode bridges, it couples the front and
back segments by means of a balun-readout transformer. The center of the readout transformer is
connected to the rails through a bridge diode configuration. The selected rail causes the bit current
to flow to the selected front and back bit line while
all other segments block current. The readout signals
are coupled to the individual bit segment transformers.
However, to obtain readout isolation, it is necessary,
with this arrangement, to switch the secondaries of
the 16 readout transformers by means of low level
selectors to a common readout detector circuit.
The rail selection matrix shown in Figure 6 is an
electronic 24 pole 16 position switch. At the right of
the figure is shown a typical rail, normally backbiased. The rail is activated by current flowing out
of the secondary windings of the transformer through
the diodes with the grounded bridge node; this forward-biases all diodes of the multi arm bridges on the
rail. Thus, each node is virtually grounded through the
forward-biased diodes during the entire memory cycle
regardless of bit current polarity on the bit segment
wires. By alternating the direction of current on
adjacent bits (shown by sending bit 1 current up and
bit current 2 down during read time in Figure 6), the
current handled by the transformer is halved. In
effect, the transformer and grounded diodes merely
switch the current from a bit to its neighbor.
The transformer primaries are themselves in a 16
crosspoint matrix containing 8 unidirectional 1 ampere
356 Fall Joint Computer Conference, 1967
TO MEMORY
liT WIRES
-, .,
I
liT 1
lIT 2
DIODE
RAILS
SWITCHES
RAIL SELECTION MATRIX
Figure 6-24-pole, 16 position bridge drive matrix
Figure 5 - Multi-dimensional group selection
switches. By selecting one of the four switches at the
top and one of the four switches at the bottom, current
is sent to one of the 16 crosspoints which, in turn,
couples through the transformers to forward-bias a
rail. In this drawing, we illustrate 6 transformers
per crosspoint. This is done to limit the transformer
current and rail current; by subdividing the rails, and
cascading transformer primaries, currents in the order
of only 1 ampere can drive an entire 24 bit word. In
summary, the organization shown in Figure 6 has a
number of distinct features. These are:
1. Bit segments are virtually grounded when
selected so that no voltage drop is required by the
access switch. This lowers the voltage to the bit
current drivers and improves current control
capability.
2. The selected bridge nodes have very low dynamic impedances because the current paths pass
from one bit to its neighbor without having to
transfer through long wire lengths with attendant
parasitic inductances and capacitances. During
the memory read time there will be an insignificant change of current out of the transformer
secondaries and negligible net current into the
ground of the reference diodes. Dynamically the
current will flow down bit 2, through the bridge
diodes and back up the bridge diodes into bit 1.
The entire matrix, with the exception of the diode
rails, can be remotely located from the core
module without affecting current wave-shapes
in the module.
3. Only 8 switches are required in the primary
matrix to simultaneously select 24 pairs of segments out of 384.
A summary of component counts for the various
access schemes considered is given in Table I.
Table I - Bit access and detection circuit counts
32,768 Words
24 Bits/Word
Segment Oriented Access
Conventional
Access
Without With
Inherent Inherent
Readout Readout
Selection Se.Iection
MultiDimensional
Access
Switches
384
8
8
8
Access
Diodes
768
960
1728
1752
Access
Transformers
0
96
96
60
Readout
Transformers
384
384
24
48
96
96
0
0
Low Level
Selectors
Influence of the core characteristics upon
memory performance
For a 2-1/2D 2-wire configuration the requirements
of the core differ from the standard three dimen-
Bit Access Problems in 2-1/20 2-Wire Memories 357
sional coincident current core. It is obvious that the
memory output signal is heavily influenced by the
noise generated by bit current shuttling the many
cores of the bit segment wire. The readout transformer
must measure a small core switching signal in the face
of thousands of cores shuttled by half currents. This
is an order of magnitude larger than the typical three
dimensional memory, where .the readout must be
sensed in the face of only a few hundred cores
shuttled by X and Y half currents.
To analyze the bit current noise, we make use of
the 6 state hysteresis loop characteristic of the core
shown in Figure 7. As will be seen later, it is desirable
to operate the 2-1/20 memory with offset currents;
i.e., bit current less than word current. For this case,
a number of additional intermediate states exist. However, the worst case disturb condition is generated by
the larger amplitude word current and we can neglect
the less noisy intermediate states. The states are
defined as follows:
ul
rwl-d~~T
rl
4. Subsequent excitations of half read and half
write currents shuttle the core between rl and
rwl.
5. The state uz occurs when a core is fully switched
by a read current.
6. The state wz occurs when the core in the uz state
is excited by a half write current. Similarly,
there is an upper state dz which is achieved when
the core is repeatedly excited by a half write
current. However, the difference between wz
and dz is small as far as the core responses are
concerned.
7. The state wrz is achieved when a core in the
wz or dz state is excited by a half read current.
8. Subsequent excitations of a half read and half
write current shuttles the core between wz and
wrz.
A core in the states ul, rwl, wz, and dz exhibit
irreversible flux switching when excited by half read
currents. Irreversible domain wall motion occurs even
for very low half read currents. Thus, there will be an
output from cores in these states even after the
exciting current rise time has expired. Figure 8 illustrates the effect for half read bit currents. The core in
state ul has the uVhl output, rwVhl is the output of the
core in state rwl, and wVhz is the output of the core in
state wz. All of these responses exhibit a recovery
tail due to domain wall motion even after the rise time
of the excitation current. Cores in the states rl, dl, wrz,
and uz exhibit mostly reversible flux when excited by
a half read current; the output is negligible after the
current rise time. This is illustrated in Figure 8 by
rVhl (rl state), wrVhz (wrz state), and uVhz (uz state).
TYPICal MAGNESIUM MANGANESE
500ns SWITCHING TIME
500 ma DRIVE
30 mil OD
wz
wrz
uz
r
0'
Figure 7 - 6 state hysteresis loop model
1. ul is the state arrived at when the core is switched
by a full write current.
2. rl is the state arrived at when a core in ul is
excited by a half read current. There is another
state somewhat lower than rl called dl which will
occur when the core is continuously exicted by
half read currents, however, the core outputs
are almost identical in states rl and dl.
3. The state rwl occurs when a core in rl or dl is
excited by a half write current.
I
I
I
I
I
_ _ t~E _ _
lIlT
I BIT =17Sma
tRISE = lOOns
I
~_l
Figure 8 - Core output waveshapes when excited by half-select
bit current
358 Fall Joint Computer Conference, 1967
For the 2-wire 2-1/2D memory shown, the bit half
current will excite 1,024 cores in the front plane and
1,024 cores in the back plane whose output signals are
sensed differentially in a readout transformer. If the
cores in the front plane are in an irreversible flux
state while the cores in the back plane are in a reversible flux state, a large recovery tail noise will
occur. It will exist long after the bit rise time is over
and will interfere with the signal output. In a 2-1/2D
memory with a read regenerate or erase and write
cycle, it is impossible to have any cores in the uz state
,and no more than one core can be in the ul state.
Therefore, for practical purposes, the worst case will
occur when all positive sensed cores are in the rwl
state and negative sensed cores are in the rl or wrz
state or vice versa.
Word access wiring
To improve memory performance, there is anobvious desire to minimize the number of cores in the
front plane or the back plane that are in the irreversible flux state. Fortunately, there is a word access
wiring technique that can reduce the number of irreversible flux state cores by a factor of two; the
technique is illustrated in Figure 9. A typical bit loop
with a readout transformer at the top, the oit drive
current at the center of the readout transformer, and
the bridge diode rails at the bottom are shown in
Figure 9A. The bit drive current splits evenly between the front and back segments into the grounded
nodes at the bridge diode. The transformer at the top
not only senses the switching core output, but equalizes the current on the front and back plane because
of its balun connection. However, the noise difference between the front and back cores due to bit
current will show up as a differential signal across
the readout transformer.
By wiring the word loops so that a word loop intersects two adjacent cores on the same bit segment and
by separating front plane word loops from back word
loops four distinct advantages result.
1. Either the upper or lower core of the pair excited by the word loop can be selected by the
direction of word loop current. 4 Thus, the number of word loop accessing circuits are reduced
by a factor of two.
2. The upper core will generate a noise that is
opposite to the noise of the lower core when
excited by word loop current and the readout
transformer will see a cancelling signal from
two adjacent cores; this will lower the noise
due to the word loop current.
3. The most important advantage, however, is the
fact that when the word loop current pulses, it
automatically drives one of the two cores into
the reversible flux state. Thus, it is impossible
to have more than half the cores on a bit segment excited by word current in an irreversible
flux state. It can be shown that this cuts the
bit line recovery tail noise in half.
4. The cores can be oriented in line rather than in
a diamond pattern. This allows the cores to be on
closer centers.
Figures 9.8 and 9C illustrate an additional advantage
achieved with the word access wiring shown. In
high speed memories it is ~lso necessary to reduce
the capacitance coupling between the word loop and
the bit loop. Unfortunately, the word loop of Figure
9A couples to only one side of the bit loop. Thus, any
voltage bounce on the word loop would capacitively
couple into one side of the bit loop and would be
sensed as a differential signal by the readout transformer. It we arrange the word loop access matrix as
shown in Figure 98 so that half the word loops on any
rail (vertical or horizontal) couple to the front segments of the bit loop and half to the back segments of
the bit loop, then voltage bounces in the word access
rails will generate equal capacitance coupling signals
on the front and back segments of the bit loop. The
readout transformer will not sense these signals; it will
reject them as common mode noises voltages. Figure
9C illustrates physically how the word loops should
be wired to realize common mode cancellations; the
word loops interlace alternately between the front
and back plane of the module.
Memory !ignais
Figure 10 illustrates the bit current excitation and
the resulting output signal. The bit current is pulsed
first to allow time for the recovery tail to expire.
After recovery tail expiration the word current is
turned on. A large inductive nOIse pulse will occur
during the rise time of bit current. After rise time,
there will be a bit line recovery due to irreversible
flux switching. The recovery tail will ride upon a DC
pedestal which is due to the difference in resistance
and difference in diode voltage drops between the
front and back plane. In this memory, therefore, the
readout detector must sense the output signals with
respect to the pedestal. A number of techniques can
be employed such as DC restoration or delay line
restoration;5 the actual scheme utilized is a capacitance charging DC restorer. After restoration, the
word current is pulsed to readout a "1" signal or a
"0" signal from the selected core. The "0" signal will
decrease after the rise time of word current so that
during the peak of the "1" signal the major noise
present will be the recovery tail due to bit current.
Bit Access Problems in 2-1/20 2-Wire Memories
READOUT
W
t
I
I
I
I
ro
I
FRONT:
WORD: :
LOOP~
I
I
BACK
:
WORD
ops
BIT LOOP
FIG. 9A
2 ----
----64
2
I
FIG. 9C
16
IF~ I ~
WORD ACCESS
FIG. 98
;----------,
I
I
Applied
------z.
L~e--j
Figure 9- Word access wiring pattern for minimum magnetic and
capacitive noise. (a) Bit loop. (b) Word access. (c) Pictorial
representation
359
360 Fall Joint Computer Conference, 1967
MICROVOLTS
BIT CURRENT,--_...I
2000
J
1000
800
./
170ns
t
V
-I
WORD CURRENT
cc 400
....
I
I
fa
,
,
-----------
>ac: 200
L&.I
>
e 100
u
80
u
L&.I
ac:
:; 40
>
~
20
INDUCTIVE
DIFFERENCE
NOISE
'1'
BIT PAIR
DIFFERENTIAL
/
t 300ns
-
-
...
BIT LINE RECOVERY
10
}
~
/
'/
I WORD =I250ma
t r =100ns
I
o
300
200
100
Figure 10- Memory current timing and readout waveform
Thus, it is evident that the signal to noise ratio is
predominantly influenced by the bit line recovery tail
and not by the' "0" readout of the selected core.
To quantitatively prove this fact, we study the core
characteristics shown in Figures 11, 12, and 13. The
core characteristic in Figure 11 A is the millivolt .outCORE
I
Figure 12 - Amplitude of rwV hI recovery tail as a function of IB
at fixed time t after start of IB
CHARACTERISTICS
W 0 r d= 250m a
t r =10 0 ns
60
500
50
mv
40
~----::~==!J;=====t=
30
20
10
o
200
dV z
AT
dV,
100
200
300
100
200
18 (mal
18 (mal
FIG. 11A
Fill. 111
I
I
18= 200ma
I
I
18= 250ma
100
PEAK~~~====~
IB = 10 0 m a
300
Figure II - Core output characteristics for current timing as shown
in Figure 10. (a) Readout amplitudes. (b) Time intervals.
put of a core switched by the coincidence of a bit
current, whose ampl,itude is varied, and a fixed word
current of 250 milliamperes with a 100 nanosecond
rise time; the bit current is turned on first and the·,word
current second as shown in Figure 10 to simulate the
actual 2-1/2D operation. The output occurs during the
word current, but we are plotting the output as a
function of bit current amplitude. Two important conclusions can be drawn from this characteristic. First,
the plot differs from the typical curves of most manu-
200
400
t
IN
ns
600 800 1000
Figure 13 - Amplitude of rwV hI recovery tail as a function of
time for various values of bit current
facturers because the manufacturers do not characterize the cores with a time staggered sequence of
coincident currents. Secondly, the dV z output at the
peaking time of the dVI is less than 1% of the" 1's"
Bit Access Problems in 2-1/20 2-Wire Memories
output even at bit currents of less than 150 milliamperes. Even though the dVI is maximum at 275
milliamperes, there is an obvious tendency to use low
bit current to reduce the bit recovery tail; Figure 12
illustrates quantitatively how low bit currents reduce
tail noise. A plot of rwVhl versus bit current at 170
nanoseconds and 300 nanoseconds after start of bit
current is a measure of the recovery tail for a core
since the rise time of the bit current is 100 nanoseconds. For a bit current of over 250 milliamperes,
the recovery tail becomes extraordinarily large and
the memory noise due to irreversible flux increases
rapidly. Even at low bit currents and at a recovery
tail time of 300 nanoseconds, an output of 20 millivolts will occur from 500 cores,generating a noise
close to 50% of a "1 's" output. This proves that the
recovery tail is by far the largest noise source and
limits the performance of the 2-wire 2-1/20 memory.
Figure 11 proves that we 'need high bit currents to get
large dVI outputs up to a current of 275 milliamperes.
Figure 12 proves that we need low bit currents to get
low recovery tail; therefore, there must be an optimum
to achieve best signal to noise ratio.
Figure 13 contains plots of the recovery tail as a
function of time. on a Log-Log scale for different bit
current amplitudes. The straight lines. indicate an
interesting characteristic; the output voltage falls off
approximately as the inverse of time squared (l/t2)
for moderate bit currents. Another important conclusion exhibited by Figure 13 is that the recovery tail
to 10% of the nominal core output (for bit lines of
1,024 cores) lasts for the order of 400 to 600 nanoseconds for a core with a switching time in the 400
to 600 nanosecond range. Thus, the recovery tail is
as long as the switching time.
361
30~---------------~----------~~~~-----------r------.
SIN
I db I 10
o ~--------------~~----~----~--------~~r-----;
-10
1------+----1
100
=250ma
I
t r =100ns
WORD
200
300
I B Imal
Figure 14-Ratio of dV t to amplitude of rwV hl tail at t
that T mem = tt + 2t8
= tt such
current of 225 milliamperes; this is optimum at a bit
current 25 milliamperes lower than the word current
and 50 milliamperes lower than the peak" 1's" output
current. Similar data have been taken for many cores
with almost the identical result. A converse plot, for
a fixed signal to noise ratio, of memory cycle time
versus bit current proves that minimum cycle time
will occur at a bit current of 225 milliamperes. Thus,
we can conclude that the best signal to noise performance and the minimum cycle time will occur at a
bit current lower than the word current and underdriven to the extent of decreased" 1's" output.
SUMMARY
Signal to noise optimization
By combining the dVI output of Figure 11 A, the
switching time, ts, (initial 10% to final 10% of dVl)
and peaking time, tp, (initial 10% to peak of dVl)
characteristic of Figure 11 B and the recovery tail
voltage of Figure 13. it is possible to obtain a signal
to noise plot as a function of bit current for the
2-1/20 memory. Figure 14 contains a plot of the signal
(dVl) to noise (Recovery tail due to the bit current)
for 1000 cores on a bit line as a function of bit current,
with memory cycle time as constraint. The memory
cycle time is defined as the read switching time plus
the write switching time of the core plus the recovery
tail time. This plot has been carried out for a typical
500 nanosecond, 500 milliampere, 30 mil outer diameter core in a memory cycle time of 1.4 microseconds,
1.2 microseconds, and 1.0 microseconds. The result
is that the best signal to noise ratio occurs at a bit
In this paper, we have described a class of new access
schemes that-appear to be economic without degrading
performance. An analysis of secondary and primary
core characteristics has been carried out to assist in
predicting optimum memory performance.
REFERENCES
J R BROWN JR.
First and second order ferrite memory core characteristics
and their relationship to system performance
IEEE Transactions on Electronic Computers Vol EC-15
No 4 August 1966 pp 485-501
2 T J GILLIGAN
2-1/2D high speed memory system-past, present, andfuture
IEEE Transactions on Electronic Computers Vol EC-15
No 4 August 1966 pp 475-485
3 P A HARDING M W ROLUND
Novel low cost design for 2-1/2 D storage systems
362 Fall Joint Computer Conference, 1967
1967 Solid State Circuits Conference Digest of Technical
Papers Vol X - IEEE Cat No 4C49 pp 82-83
4 T J GILLIGAN P B PERSONS
High speedferrite 2-/ /2 memory
AFIPS Conference Proceedings FJCC Vol 27 Washington
D C Spartan Books 1965 pp 1011-1021
5 A M PATEL J W SUMILAS
A 2.5 D ferrite memory sense amplifier
1966 International Solid-State Circuits Conference Digest
of Technical Papers Vol IX IEEE Cat No 4C27 pp 96-97
Engineering design of a mass random
access plated wire memory
by C. F. CHONG, R. MOSENKIS, and D. K. HANSON
Univac Division, Sperry Rand Corporation
Philadelphia, Pennsylvania
INTRODUCTION
Among the newer memory ~lements, plated wire has
been shown to be a serious contender for aerospace
and central store applications. 1,2,3 This paper describes a memory development project, sponsored by
the Rome Air Development Center, to extend the
application of plated wire into the area of mass storage.
The basic memory module consists of 107 bits; the
mechanical package can hold 10 modules. The potential speed is a I-to-2-microsecond word rate. Preliminary system, stack, and circuit designs have been
completed and a partially loaded model was fabricated and tested.
ADDRESS
WORD LINE
DRIVERS
SWITCHES
BIT POSITION
SELECTOR
BIT DRIVER
(72 BITS)
INFORMATION
---------
WORD LINE
DRIVERS
SWITCHES
BIT POSITION
SELECTOR
BIT DRIVER
M emory organization
The memory under development has a capacity
of 108 bits. This capacity is achieved by stacking ten
107 -bit modules into one unit. Figure 1 shows the
arrang~ment and organization of such a memory
Each module has its own set of driving circuits and
sense amplifiers. This arrangement leads to a fast,
random-access memory, readily realizable mechanically; it is justified from the viewpoint of modularity and cost because the electronic circuits are shared
by a large number of bits. All modules share one set of
auxiliary circuits, which include the address decoders,
timing circuits, information registers, and power
supplies.
The organization of the 107-bit memory module is
shown in Figure 2. The memory plane contains 2048
word lines and 4608 plated wires. The word lines are
spaced at 0.045-inch centers and the bit lines are
spaced at 0.015-inch centers. This results in a storage density of approximately 1500 bits per square
inch. The reason these spacings were selected will
be discussed later.
OUTPUT
(72 BITS)
Figure 1- Arrangement and organization of lOll-bit memory
The plated wire used is a nondestructive readout
(NDRO) element with equal word currents for reading and writing. 3 This property makes it unnecessary
to have rewrite circuitry for each stored bit. A word
line may be made many machine words in length; each
time all the bits in such a word line are interrogated,
only the bits belonging to the selected word are routed
by a set of gates, called the bit-sense matrix, to the
sense amplifiers. After interrogation, all the originally
stored information at each bit location along the word
line is left unchanged. Correspondingly, the same set
of bit-sense matrix gates is employed to route the bit
drivers to the proper bit lines of the memory. This
feature is illustrated in Figure 3. This property is very
363
364
Fall Joint Computer Conference, 1967
',437,114 BIT
IIEIIORY PLANE
IlII'uT
OUTI'UT
Figure 2 - Organization of l07-bit memory module
• WORD GROUP LINES
READ
AMPLIFIER t
BIT
DRIVER t
11111111111111111
READ
AMPLIFIER 2
full-turn line provides a stronger and more confined
field per unit of word current, thus giving less adjacent-word interaction and allowing lower word currents to be used. However, it presents significant
mechanical problems in plane construction. Word
lines must be etched double-length, and accurate
registration between top and bottom conductors must
be maintained.
Work has been published4 which indicates that the
placing of a magnetic keeper over the half-turn word
line gives that configuration the advantages of the
full-turn line, namely, low operating word current and
low susceptibility to adjacent word interaction. Tests
'were performed to verify the theory; the results are
shown in Figures 4 and 5 for full-turn and keepered
half-turn word lines on 45-mil centers. In these
figures, Iwp is the so-called "pop point" word current,
representing a lower limit on word current; IwD is
the word current for destructive readout, and IWA
is the current flowing in the adjacent word line which
will cause significant interaction in the bit under
test. Based on these tests, it was decided to use a
half-turn keepered word line, 33 mils wide, on 45-miJ
centers.
n BITS
WORD - GROUPS
p WORDS/WORD-GROUP
II BITS/WORD
2000r-------r------~------~----~
III
BIT
DRIVER 2
PIli
PlATED
WIRES
IwA
tOOO~--~~~==~====~==~~
4'
2
800~--~~~--_4------+-----~
READ
AMPLIFIER q
BIT
600~----~~--_4------+-----~
DRIVER q
t OUT OF
P SELECTION
400~~
20
Figure 3 - Modified word-select memory organization
important because it allows a memory configuration
to be chosen which leads to a minimal number of bit
and word drivers and sense amplifiers.
The word-line matrix, bit-selection matrix, and
selector switches are included physically in the memory stack; as a result, the number of connections
between the memory-access circuitry and the module
is reduced to a minimum.
__~__~~__~__~~__~
40
35
30
25
WORD-LINE WIDTH (MILS)
o.
20
:Ie
c(
:-
w
>~
!~
Eo
40
01
W:Ie
c(
--- -
r
W
CL
o
20
1
~
I
25
30
35
40
WORD-LINE WIDTH ,(MILS)
Stack design
Two possible word-line constructions were considered. The first, called a half-turn line, consists of
a single flat conductor over the plated wire, the wire
being over a ground plane. The second type, a fullturn line, is a flat conductor wrapped around the wire,
with the entire assembly mounted over a ground. The
b.
Figure 4- Word current (a) and output (b) as functions of line
width, for one-turn copper word lines
When an 8-foot sense line was contemplated, crosstalk between plated wires during a read operation was
a major consideration. With a readout signal being
Engineering Design of Mass Random Access Plated Wire Memory
1000
IwA> 1700MA
//
800
;{
l'
-
~
.?
-
600
o
."",,0/
IwD
---'
400
amplifier, which would occur if current flowed only
in the plated wire. When information is read from the
memory, identical noise is coupled into the plated wire
and the dummy by the word current and hence can be
rejected by the differential sense amplifier.
I
l-
-,.--t:.~
Iwp
I
/
A"_
BIT-SENSE
MATRIX SWITCHES
1
I
20
10
30
I) )
2
40
WORD-LINE WIDTH (MILS)
PLATED
WIRES
BITGROUP
IA
32
a.
t-c - jwt). The negative itself
becomes an object scattering the incident illumination
in proportion to the ,real amplitude transmission such
that the transmitted field becomes
Zp
I
I
COHERENT
LIGHT
--- ----- ---
PHOTOGRAPHIC
PLATE
INTERFERENCE OF OBJECT AND
REFERENCE RADIATION
Etrans = EcexpGcf>c - jwt) . to'
Substituting for tm its equivalent expression in terms
of the original object field, one obtains a final value for
the transmitted wave,
Figure 1- Holographic construction
a second field results from object scattering. The
total scalar field at the plate may be written as
E expGcf» = expGcf>r - jwt)[Er + EdexpGcf>d - jcf>r)] (1)
where
Ed(x,y) exp Ucf>d(X,y) - jwt]
and Er(x,y) exp Ucf>r(x,y) - jwt]
represent the modified and unmodified light respectively. The resultant power density (intensity) of the
total field is equivalent to the square of the absolute
value of the wave, or
1= [E expGcf»] . [E expGcf»]*
where * indicates the complex conjugate. Substituting
Equation (1), one obtains
1= IEdl2 + IErl2 + 2ErEdCOS(cf>d - cf>r).
373
(2)
Because photographic emulsions are sensitive to
incident optical power, they will record this expression. Note that the time factor expGwt) has been eliminated, thereby making the power distribution fIXed
or stationary relative to time. Such a condition is
maintained due to the coherent property of the light.
Further, this expression exhibits information about
the scattered phase cf>d as well as the scattered amplitude. The first and second terms of Equation (2)
may be considered as D.C. components which contain littie information but act as a bias level for the
signal. The final term, representing the signal, expresses the modifications of light due to object scattering
as the relative phase and amplitude variations with
respect to the unmodified or reference light. The
variations are functions of the spatial coordinates in
the photographic plane but are invariant in time.
Through the ordinary photographic recording process, the energy distribution incident upon the plate
E trans = knEcErexpGcf>c - jwt) . [Er + Edexp j(cf>d.icf>r)]
~2
+ knEcErexpGcf>c -
jwt).
+ knEcErexpGcf>c -
jwt) . [EdexP(-jcf>d + jcf>r)].
r
where kn is a constant of the photographic process.
Comparing this equation with Equation (1). one can
see the direct resemblance of the first term of the reconstructed wave to the original signal. It differs
by a mUltiplier and a constant phase shift. The second
term has little significance and may be considered
as noise. The third term is critical, however, and is
characteristic of the holographic process. It is generated by the modulating action of the emulsion and
is therefore characteristic of all holograms. That
is, because the emulsion acts essentially as a square
law device, recording the product of the field and its
complex conjugate, this final term will be produced
in all holograms. It is frequently called the conjugate
or twin imuge of the signal, for it contains the same
amplitude as the signal but has opposite phase shifts
"elative to the background.
S:'RTUAL 'MAGE
COHERENT
LIGHT
\I
OBSERVATION
t
Figure 2 - Holographic reconstruction
When the hologram is viewed as in Figare 2, the
signal term seems to diverge from an object behind
the hologram plane, thereby appearing as a virtual
374 Fall Joint Computer Conference, 1967
image. This signal is a replica of the field that would
be produced if the object were in place. The conjugate term represents a real image whose rays converge
to a plane in front of the hologram plate. When constructed in this manner, these real and virtual images
are superimposed acting as mutual noise. The effect
of such noise on the original signal is a major problem
with Gabor's original technique, but such effects can
be reduced by special construction methods, e.g.,
masking. 5
The second term in Equation (3) acts as background
noise for both the real and virtual images. Its effect
may be reduced by controlling the reference light
amplitude during the construction phase. 5
Hologram storage characteristics
General discussion
The system characteristics for the memory have
been established previously. The distinguishing memory characteristics of high speed, large capacity,
permanent store, and low cost are the major factors in
determining system feasibility. The additional factors
of expandability, small size, low power consumption,
and high environmental resistance are included to insure compatibility of the memory with the remainder
of the computer system.
- - - - ---T
r--:I~S--i
-.--. -. -. -. -.-.
----------- --- --~--':.-- --------
':._--:._-
--:.--------':.~-----:..-----__ --- 64
--_ -------_ -------_ ----lwoRDS
':..-"'"--
---:.-:..~->~~~--:.-~ -~~--- -- -- -.-.-.- .-.-.-.-
TYPICAL SUBGROUP
.
DODD
DDDD
DODD
DODD
16 SUBGROUPS
Figure 3 - Data array configuration
A diffused illumination, twin-beam hologram is to
be constructed of a binary data array which consists
of 1024 words of bit length 40. A possible configuration for the array may resemble Figure 3 which illustrates the placement of the data into sixteen subgroups each containing 64 computer words. The
dimensions of the final array and bit configuration
depend upon the capability of the holographic process
and the physical limitations imposed by the read unit.
During reconstruction, the read unit would allow
a real image of this array to be continually focused
onto an optical read matrix, which consists of a photo-
detector for each bit location. Access may then be
accomplished randomly by electronic selection and
sensing of the individual detectors.
Information capacity
The digital information capacity of photographic
emulsions has been shown to be extremely large. 6
Future photographic systems are predicted which
have storage densities greater than those of contemporary storage techniques by a factor of 106 , and this
recording potential is surpassed only by genetic memories. 6 Analysis of emulsions on the basis of data
capacity has been given extensive treatment in literature. 7 It has been demonstrated, to a first order
approximation, that the information capacity in bits
per unit area is equivalent to the square of the emulsions's resolving power. Numerically, then, Kodak
649-F plates (estimated to have a resolving capability
of 2000 lines per millimeter) have an upper limit of
4 x 106 bits per square millimeter capacity. 7 Of course,
attainment of such capacity depends upon the techniques of processing the data.
In terms of a one-to-one storage technique, a larger
memory (4096 words) contains approximately
160,000 bits. If it is assumed that only 30% of 21square inch media area is devoted to data, the bit
packing density is only 40 bits per square millimeter.
Obviously, this value imposes a modest demand upon
the plate resolution.
Image Intensity: During reconstruction, it is desirable to transmit maximum light energy into the real
image in order to maximize the electrical signal,
improve signal-to-noise ratio, and compensate, to
some degree, the variations in detector characteristics. With the holograms considered, there are several parameters that can be controlled to vary the
real image intensity. The most obvious parameter
is the output power of the reconstruction light source.
It must be remembered, however, that since the outputs of present continuous wave lasers are proportional to the physical size of the device, there is a
definite size limitation imposed by the memory on
applicable lasers. Work on semiconductor lasers may
prove useful in eliminating such 'a limitatJOn. Secondly, it was noted that the image intensity is directly
proportional to the amount of hologram area illuminated. Thus, a larger illuminating area seems advantageous. Thirdly, it may be shown by Equation (2),
which relates the signal and bias levels, that a maxi, mum signal is obtained by making the modulation
New Tec,hnique for Removable Media, Read-Only Memories
2Er E d
index, (Ei+E r2), equal to unity. This may be done
by controlling the object and reference beam levels
with filters. With this index set at unity, the ~xposures
may be controlled to permit operation of the photographic process in a linear region of the Hurter-Driffields curve, thereby producing low· plate densities
after development. A low density plate transmits
and, therefore, diffracts more of the incident light
into the real image.
Resolution: Armstrong8 demonstrates that the size
of t~e hologram plate constitutes a finite aperture
for Fresnel-hologram imaging systems. Mathematically this may be seen by extending the Fresnel process equation into two dimensions and integrating
over the finite limits specified by the dimensions of
the photographic plate. Upon performing the integration, it is found that the reduction in resolution is
proportional to the constriction of aperture area.
Thus, the introduction of particles or scratches decreases the resolution by reducing the effective aperture area below that of the plate. It may be stated that
the resolution loss varies as the ratio of aperture sizes
before and after the inclusion of a particle. This indicates that with half the hologram destroyed or blocked
half the original resolution is obtainable.
Further, since the image intensity (assuming constant illumination) is dependent upon the illuminated
area of the hologram, a reduction in the effective hologram area reduces the image power. This may be
seen if one considers each hologram point as a lens
which focuses into its own image. The total intensity
of the image then is a function of the number of lenses
or the illuminated area of the hologram. The amount
of light diffracted into the image depends upon the
source intensity and the area effecting the diffraction.
This variation of resolution and intensity as a function of plate aperture is not a characteristic of ordinary photographs. If half a photograph is destroyed,
only half the image is visible, but the resolution and
intensity of the remaining half has not been changed.
On the other hand, if only a portion of a diffused
illumination hologram is used, the entire image can be
retrieved, but the intensity and resolution of this
image is proportionally reduced. In digital storage
applications, this effect may not be critical because
half an image may be more necessary than half the
resolution. The memory, for example, may tolerate
reduction of resolution (assuming the initial . value
.was adequate) but cannot tolerate the loss of any part
of the image.
Registration effects"
The coupling problem associated with most optical
read memories may be divided into two major areas.
375
First, . there is the difficulty of converting the light
signals into corresponding electrical outputs. This
conversion becomes a function of the image intensity,
and of the optical sensitivity and speed of the photodetectors. Second, there are problems in the registration, or alignment, of the media and the light· signals
with respect to the detectors. These problems are
related to the bit size and the mechanical limitations
imposed by the removable media requirement. The
registration problem is not peculiar to photographic
memories but stems from the high bit density and the
removable media criteria. The difficulty can generally
be traced to the storage scheme which, for most
memories, is on a one-to-one basis. Each data bit
then, is allocated a physical position in the memory:
The media placement must register each bit location
onto a corresponding sensor location.
To briefly demonstrate the superiority of hologram
registration, consider a possible random-access photographic memory which uses bit-by-bit storage. The
media is a photographic picture of a data array which
consists of appropriate transparent and opaque areas.
This array is focused by a lens system onto an associated photosensor matrix. The positioning of the
media with respect to the lens system must permit
focusing of a single bit such that the movement or
displacement of the media does not result in a movement or displacement of the image more than a fraction of the bit size. Therefore, the mechanical holders
for the media must maintain placement to within a bit
size, assuming a direct relationship exists between
media and image positions. Numerically, assume that
the memory specifications require 1024 words of 40
bits each to be stored on a 2 I-square inch media. This
demands a maximum bit length of .0224 inch. Positioning accuracies should be well within one quarter of
this size, allowing a .0056-inch positioning tolerance of
the media in the media plane. This one-quarter derating factor must reflect the resolution available, diffraction effects, lens distortion, and photodetector
characteristics. It may be that this value is too large
and greater mechanical accuracies are necessary.
N ow consider the holographic reconstruction process depicted in Figure 4. A diffused, twin-beam,
Fresnel hologram is used to generate a magnified real
image at a finite distance from the plate. A normal
incident beam will, in the case illustrated, produce a
diffracted, first-order, magnified image. It is evident
that a transverse shift of the hologram by a distance d
across the beam will cause the real image to move the
same lateral distance d. Therefore, even with magnification, there is a unity factor between the positioning
of the media and the' image.
Although the Fresnel holograms seem to offer an
improvement over conventional photographic tech-
376
Fall Joint Computer (;onference, 1967
x
-
IMAGE
PLANE
rHOLOGRAM
ILLUMINATION
Z
OPTICAL
AXIS
-
MAGNIFIED
IMAGE
angular position of the image does not vary (cf Figure 6). However, unlike the Fresnel type of hologram,
a lens is required to produce a reconstructed image at
a finite distance. Figures 7 and 8 illustrate the characteristics of diffused illumination Fraunhofer reconstructions with respect to image registration.
Although the preceding discussion does not consider
all of the possible displacements of the hologram and
the resulting effects on the reconstructed image, it
does serve to illustrate some of the more sigriificant
advantages of the technique.
ILLUMINATION
Figure 4 - Lateral shift of plate, Fresnel hologram
8
niques, an attempt was made. to determine a more
optimum condition for image registration. In this
respect, Fraunhofer holograms appear to offer significant advantages. Figure 5 shows the Fraunhofer construction of an object composed of an infinite number
of line sources. Because each source is placed at the
HOLOGRAM
PLATE
LENS
8 - ANGULAR
DIFFRACTION
OF IMAGE
Figure 6 - Reconstruction with image at infinity
PLATE
I
z
-L-Lf~J
_.
-·1·-
ILLUMINATION
i>IMAGES
I
--f--+-
I
.1
FOCAL
LENGTH
II'> IMAGES
ILLUMINATION
1/
Figure 5 - Construction of object at infinity
focal plane of the lens, it will generate, in conjunction
with the lens, a plane wave emanating at a predictable
angle. Each source then creates a corresponding plane
wave across the plate. The addition of a reference
beam produces a sinusoidal intensity distribution on
the plate for each source. Interference between source
components is not considered. Because the distribution for a single source is similar over the entire plate
in one linear dimension, illumination of any section
during reconstruction will produce th~ same result.
That is, employing a reconstruction beam whose
illuminating area is less than the plate area causes
plane waves to be emitted and, therefore, an image to
be produced whose angular position does not depend
on the hologram's linear displacement in one dimension, but which is a function of the incident beam position. As the hologram is moved across the beam, the
PLATE
SHIFT
Figure 7 - Z axis displacement, Fraunhofer hologram
PLATE
LENS
:~F~:.=-===~::::t'
ILLUMINATION
PLATE
SHIFT
~:~
~u
I
14.4 - - - f
----1~~
IMAGES
Figure 8 - X or Y axis displacement, Fraunhofer hologram
New Technique for Removable Media, Read-Only Memories
System design considerations
Read matrix requirements
As previously stated, one approach to the implementation of a removable media, read-only memory
by holographic techniques is as follows. The removable media would consist of a hologram of a
binary data array. The actual dimensions of the array
and the final configuration of the data will depend
upon the capability of the holographic process and the
physical limitations imposed by the read unit. During
reconstruction, the read unit would allow a real image
of the array to be continually focused onto an optical
read matrix consisting of a photodetector for each bit
location. Access may then be accomplished randomly
by electronic selection and sensing of the individual
detectors. It is proposed to use a laser to provide the
coherent illumination.
In the design synthesis, advantage should be taken
of the specialized nature of the read only function. For
example, effort should be made to decrease access
time and to implement the system with a minimal
amount of hardware. In this case, the effort will consist of gaining simplicity in the control block and in the
remaining circuitry peripheral to the detector matrix.
Overall, the memory must provide a word-oriented,
random access, nondestructive read capability while
being compatible with the remainder of the computer
through the processor-memory interface. F\gure 9
shows a block diagram of the proposed memory
design.
COMMANDS
t
INPUT
INTERFACE
~
DECODING
MATRIX
--""
PHOTODETECTOR
MATRIX
l..-.+
OUTPUT
INTERFACE
+v
NOTE- -6--INDICATES PHOTODETECTOR
~~~~l
FOUR
WORDS
A
,
CONTROL
The read unit matrix, in conjunction with the control section, must accept the address, decode the address, and place the data into the sense amplifiers. The
matrix consists of a 40,960-bit planar array of detectors.and associated address-decoding circuitry. Figure
10 shows a simplified matrix which demonstrates the
access .. technique. Here, a diode decoding matrix,
driven by the address line drivers, A,A,B,B, exhibits a
word-oriented,· random access, linear select function.
The speed of decoding depends upon the diode switching speeds which, in turn, are functions of diode capacitance. Extension of this simple matrix to the full
tance. Extension of this simple matrix to the full
1024-word memory would indicate, due to the number
of diodes involved, the necessity of address drivers
to insure a .I-us access time. Such an expansion would
also indicate the 1024 lines connecting the decoding
circuitry to the photodetector array and the need for
completing these connections during fabrication of the
matrix. It may be possible to utilize the photodett!ctors in the array for address decoding if the proper
addressing is included in the image of the hologram.
L..AAA~~~l
8
ADDRESS
---+-
377
f+-
+
DATA
Figure 9 - System organization
A
B
B
,--ADDRESS----I
INPUT
~ OUTPUT ~
BIT LINES
Figure 10- Simplified read matrix
Each bit location, or cell, contains an electrically
fast, highly sensitive photodetector and a high speed
isolation diode to prevent crosstalk. The electrical
characteristics of both the photo detector and the
isolation diode affect the read cycle. To increase the
speed, the capacitance per cell should be reduced to
the lowest possible value. It is conceivable to use a
driver per word line or a driver per element although
such additions would increase matrix complexity
beyond present day practical realization.
Detector Study: It should be apparent that many of
the matrix characteristics depend upon the type photodetector to be used, and, indeed, the photodetector
378
Fall Joint Computer Conference, 1967
properties may dictate system feasibility. The principal concern is the choice of appropriate detectors
and, from those available, which can be fabricated by
simple techniques. In choosing the most suitable
detector, the main properties that are required are
optical sensitivity, electrical response, and ease of
fabrication. The sensitivity of each detector must be
high due to the relatively low optical power usually
concentrated in the hologram real image.
In examining the electrical speed of the detectors,
one must differentiate between optical and electrical
switching characteristics. To illustrate these differences, consider a photo detector which is maintained
at the proper electrical bias. If it is exposed instantaneously to a level of light, the optical response or
switching time will be defined as the time required to
electrically detect (at the output terminals) the total
light change. This time includes the delay through the
device and the rise time of the electrical variable,
voltage or current. If, on the other hand, light is constantly on the detector, and the electrical bias is
applied as a unit step function, the time required to
fully sense the state of the detector will be referred
to as the electrical switching time.
A survey of several optical detectors, including a
discussion of the basic physics of their operation, can
be found in the literature. 9 • lo The devices which are
applicable, especially from the standpoint of fabrication, are photoconductors, photodiodes, and phototransistors~ In terms of the distinguishing characteristics dictated by the memory, i.e., sensitivity,
speed, and ease of fabrication, all three detector types
seem applicable. Because the image of the data array
will be continually focused onto the detectors, the
electrical switching characteristics are most interesting. From this standpoint, perfect photoconductors
act simply as resistors, and therefore the electrical
swit~hing response is dependent upon its conductance
and the impedances of the pre- and post-circuits.
With good circuit design, this response becomes that
of the pre- and post-circuits which, in this case,
includes the decoding circuitry for the matrix. (Practically, there will be some parasitic capacitance
associated with each detector element.)
Experimental results
A number of basic experiments were performed in
an attempt to verify the predicted characteristics of
holograms with respect to the read-only memory
application. The primary areas of interest were the
image intensity, image resolution, and registration
effects associated with the construction and reconstruction of holograms storage images of two dimensional digital arrays.
The experiments confirmed the predicted registration effects and the application of holographic techniques to th£! read-only memory problem appears to
offer significant advantages in the area of image·
registration with respect to the detectors. Measurement of the image resolution indicated that the resolution achieved was in the order of 13 lines/mm. However, due to the "granularity" which appears under
visual observation of the reconstructed image, it is
felt that the measurement was limited by the technique and that the actual resolution exceeds this
figure. In addition, the resolution is also a function
of the sophistication of the experimental facilities and
technique and this value should not be interpreted as
a maximum limit. Image intensity requirements are
obviously dictated by the sensitivity of the selected
photodetectors. To obtain some indication of the adequacy of image intensity for the intended application,
as well as the overall feasibility of this approach, a
breadboard model was constructed to actually read
digital information from a hologram.
The breadboard model as shown in Figure 11, consisted of (1) a main chassis containing address selection switches, sense amplifiers, a four-bit output
register and associated indicators, and (2) an auxiliary
chassis containing a 4 x 4 array of photoresistors
with an associated diode selection matrix. The photodetectors were organized into four words of fo~r-bits
each and were located in the auxiliary chassis to
Figure II - 16-bit breadboard
facilitate positioning with respect to the reconstructed
image. A Neon-Argon gas laser-with a power output of
0.6 mW (fundamental mode) was used as a source to
reconstruct a hologram of a 16-bit data array. When
the photodetector array was illuminated by the reconstructed image of the data array, it was possible to
select and read out a four-bit word.
New Technique for Removable Media, Read-Only Memories
Alternate approaches
The proposed approach for implementing a readonly memory using holographic techniques specifies
a single reconstruction source and a single photodetector array with sufficient capacity to read the
contents of a 1024-word memory. However, the ultimate feasibility of the technique need not depend on
the development of such a photodetector array. Alternate configurations are possible which would allow
the use of detector arrays with fewer photodetectors
without reducing the total storage capacity of the
memory.
For example, by using two reconstruction sources
and by constructing two different holograms on a
single photographic plate (each covering one-half
the plate), the number of photo detectors in the array
may be reduced by one-half. Each hologram would be
associated with one of the reconstruction sources
and would be constructed to cause proper imaging on
the photo detector array upon illumination by the
associated source. Then, access to a desired word
would involve the selection and triggering of the
proper source in addition to the normal selection in
the photo detector array.
Of course, this scheme would require that the optical response of the photodetectors be less than 100 ns
since the illumination of the elements in the array
is no longer steady-state. This requirement would indicate the use of photodiodes or phototransistors in
the photo detector array.
ments, as previously defined. Moreover, the requirements for the reconstruction or reproduction of a
storage media are much less stringent and appear t?
be capable of allowing the development of a read umt
which is suitable for operation in a field environment.
I t has been shown that holograms can be reproduced by contact printing and that holograms can be
reconstructed by noncoherent light sources.
Of course, the development of a feasible holographic read-only memory does not depend solely on
holography. It is apparent that the ultimate success
of this concept also requires the existence of photodetector matrices with sufficient size, sensitivity, and
speed for this application, and which, in addition, are
capable of economic fabrication. The development of
photodetector matrices with the required characteristics appears to be within the state-of-the-art and
should present no insurmountable obstacles. Indeed,
if a "multiple-source/multiple-hologram" approach is
selected the number of bits required for the photodetector'matrix may be small enough to allow practical
and economic fabrication of the matrix on a discrete
element basis.
REFERENCES
2
CONCLUSIONS
3
In general, the results of this study have indicated
that holographic techniques are particularly suited to
satisfy the functional requirements of read-only memory as specified. For example, holography offers solutions to two key problems associated with the requirement for a single removable media storing up to
160,000 bits. First, the unique redundance inherent
in holograms constructed with diffused illumination
eliminates the loss of data due to such environmental
effects as dust and scratches. Second, the potential
freedom from registration effects which can be
achieved by proper selection of construction techniques allows the manual insertion and removal of
media with high bit packing densities and does not
add a requirement for complicated mechanical positioning or complex electrical interconnection in the
read unit.
Although the initial construction of a storage media
by holographic techniques requires a coherent light
source and a fairly stable system, these requirements
are within the scope of the system functional require-
379
4
5
6
7
8
9
to
B H GRAY D R HADDEN JR. D HARATV
Block oriented random access memory
Paper presented at the IEEE Conference on The Impact of
Batch Fabrication on Computers Los Angeles Calif 1965
A V CAMPI R M DUNN B H GRAY
Content addressable memory system concepts
IEEE Transactions on Aerospace and Electronic Systems
Vol AES-I No 2 1965
D R HADDEN JR.
Private communications, Comm/ADP Laboratory, USAECOM Ft Mon N J 1965
E LEITH J UPATNIEKS
Wavefront reconstruction with diffused illumination and
three dimensional objects
JOptSocAm Vol 54 p 1295 1964
D GABOR
M icroscopy by reconstructed wavefronts
Proc Rov Soc London Vol A 197 p 454 1949
M CAMRAS
Jnformation storage density
IEEE Spectrum Vol 2 p 98 1965
C McCAMY
On the information in a microphotogr~ph
AppOpt Vol4 p405 1965
J ARMSTRONG
Fresnel holograms: their imaging properties. and aberrations
IBMJourR&D Vol 9 p 171 - 1965
D CADDES B McMURTRY
Evaluating light demodulators
Electr Vol 37 p 54 1964
R KAUS
J965 survey of commercial semiconductor photosensitive
devices
Electr Ind Vol 24 p 82 1965
Low power computer memory system
by D. E. BREWER
Air Fo.rce Avionics Laboratory
Wright-Patterson Air Force Base, Ohio
and
S. NISSIM and G. V. PODRAZA
The Bunker-Ramo Corporation
Canoga Park, California
INTRODUCTION
One of the critical technologies for aerospace missions
is electrical power. Increased emphasis is being given to
reducing power requirements of electronics as well as
toward improvements in power sources themselves.
In present day aerospace computers the memory
subsystems consume approximately 40 to 60% of the
total computer power. This is primarily due to the high
drive requirements of present core memories or to the
sensing problems associated with thin film memories.
Reduction in memory power requirements would,
therefore, have a significant effect on extending allowable mission time.
The objective of the effort described in this paper is
to demonstrate a capability for the design and construction of an aerospace computer memory having very
low power requirements. The device technology selected to accomplish this objective is the metal oxide
silicon (MaS) --transistor memory array. The MaS
transistor is an insulated-gate field effect device formed
in a silicon crystal and is suited for low-power applications. The idea of u~ing active devices for storage of
data in computers is as old as computer systems. However, until very recently, the power required and the
cost of active memories were prohibitive for almost all
applications. With the progression of integrated circuits technology from the gate functional level to very
large scale integration of system functions, considerable
interest has been devoted to development of monolithic memories. 1- 4 Predicted power requirement for a
random access memory subsystem using monolithics
varied over a wide range depending on various proposed designs. This effort primarily emphasizes low
power circuit design and memory organization con381
cepts leading to a low power aerospace computer memory that is suitable for economical production.
As the feasibility vehicle for this approach, a 1024word, 30-bits/word, random access memory was constructed using P channel MOS transistor arrays for
storage and bipolar transistors for the peripheral accessing circuitry. This system is an NDRO, electrically
alterable, memory with a read access time of 0.7
microseconds, a read or write cycle time of 1 microsecond and has a total power requirement of approximately 3.5 watts. This unit has been successfully constructed and delivered to the Air Force Avionics Laboratory. Significant results were obtained in the areas of
low-power circuit design, memory design, and organization concepts using MaS transistor arrays. All of the
areas will be covered in detail in this paper.
Outline of technological approach
review of the circuit operation if the basic memory cell
The MOS integrated circuit approach was chosen
as a means of developing a low power memory array
for two reasons, namely (1) MaS bistable arrays can
be operated with very low power by using pulsed operation techniques, and (2). this approach is well suited to
large scale integration and reasonable yield, an essential prerequisite from an economy viewpoint.
The peripheral circuitry, which included the address
decoder, write drivers, sense amplifier, and control
circuits, utilized bipolar transistors and employed commercially available integrated circuits whenever possible. The MOS-to-peripheral system interface circuits
were fabricated from discrete components because
voltage levels involved in these circuits were not compatible with the relatively low voltages of bipolar inte-
382
Fall Joint Computer Conference, 1967
grated circuits. A savings in power is achieved in the
peripheral circuits by employing techniques which
minimize power until circuits are actuated by pulse
signals. Further power reductions were realized by
employing special nonlinear switching circuits with inductive source impedances to decrease the power consumption when driving large capacitive loads in the
MOS array and distribution lines.
The system development included a memory exerciser to aid in testing and in demonstrating operation
of the memory, and a power supply operated from a
110 volt, 60Hz source to furnish the + 13, + 12, +4,
-4 and -7 supply voltages required by the memory.
The exerciser and power supply are of· conventional
design, were not concerned with power conservation,
and therefore, will not be described in detail.
RESTORE
U
NODE 2
Description of the MOS memory chip
The memory cell circuit, monolithic configuration
for the 64-cell chip, and basic principle of low power
operation are described in a companion paper.s For the
sake of completeness in the present paper, a brief
review of the circuit operation of the basic memory cell
is presented in this section.
Figure 1 is the schematic of the memory cell utilizing P channel enhancement mode, MOS integrated
transistor structures, having a nominal threshold voltage of 5 volts The substrate is operated at a 12 volt
potential. Transistors Ql and Q2 form the basic bistable
storage element of the cell .. Transistor Q3 serves as a
"load" for Ql, while Q4 is the load for Q2. Transistors
Qs and Q6 are biased off during quiescent memory
operation (i.e., neither reading nor writing).
Assuming Ql in the bi-stable is on and Q2 off, the
node voltage at the drain of Ql will be + 12 volts,
while the Q2 node will be near ground potential. During
quiescent operation, the capacitance of the Q2 -node
will begin to charge toward + 12 volts because of
the leakage current through the P-to-substrate junctions common to this node. These junctions are constituted by the drains of Q2 and Q6, the source of
Q4, and any interconnection crossunders that utilize
a P-diffusion onto the substrate. The voltage buildup
on the node capacitance by leakage would eventually
cause Q2 to turn on and cause possible loss of the
logic state of the bistable. To prevent this, the restore
pulse is periodically applied to Q3 and Q4, resulting in
discharge of the Q2 node. The Ql node voltage is
not appreciably affected by restore, since Ql is biased
on and has a much greater transconductance than
Qs. Periodicity of restore must be sufficient'to keep the
Q2 node properly discharged under condition of worstcase leakage current. .The restore pulse for each cell
,.,,=50
~DIGIT
LINE)
Figure l-Schematic for basic memory cell circuit
is 18 volts in amplitude, 1.5 microseconds in width
and has a repetition rate of approximately 10KHz.
When reading from the cell, or writing information
into the cell, use is made of the Q5 and Q6 gating
transistors. The cell is addressed by applying the Xand Y-address pulse, as shown in Figure 2 and 3,
to the respective source and drain electrodes of Q7.
Coincidence of these address pulses causes Q7 to conduct, biasing the gates of Qs and Q6 on. The Y -address
pulse must have a longer duration than the X-pulse in
order that Qs and Q6 be turned off by the transition
of the X-address pulse back to + 12 volts.
Writing is accomplished by applying a write pulse
(Figure 2) to the cell simultaneously with the address
pulses. With Ql assumed conducting, and Q2 off, a
logic "1" is stored in the cell. If a "0" is to be written
into the cell, the write pulse, which rises from ground
to + 12 volts, is applied to the digit complement while
the digit line is held at ground potential.. This causes
Q6 to conduct current into the capacitance at the Q2
node, resulting in turn-off of 01. The Ql node is now
discharged toward ground through Q5, resulting in
the turn-on of 02. With termination of the address
and write pulse signals, the bistable is then retained in
the zero state.
Low Power Computer Memory System
383
VOLTS
,..----,---~--T""--
1
~I
+4
I
I
,.._--:-----1 +12
WRITE COMMAND
(FROM MEMORY
EXERCISER)
~,.--~--I ------- :, ~~r''''
+4
I
I
ADJUSTABLE
~---I+\2
MONOSTABLE
I
I
I
(100 TO 200 NANOSECONDS)
0
1
----I ----I --~':""'---IO
',.---1-----1-'..
l
' ..
---=----+---....;...--.....;----.,..-----1
I
I
I
LOGIC "I"
READOUT
+1
READ OUT (FROM
MEMORY CELL ON
1
o DIGIT OR DIGIT'LINE)
WRITE PULSE
~1~~i~~~~Goc:,"
READ STROBE
SIGNAL APPLIED
TO SENSE AMPLIFIERS
MEMORY·
12,
0
'l'1~ll8~,;~~NT
TRANSITION
RESPONSE OF
BUFFER FLIp·
FLOP RECEIVING
READ DATA
liN MEMORY
EXERCISER)
·NOTE: SOLID LINE FOR WRITE "I"
AND DOTTED LINE FOR
WRITE "0"
0.2
0.4
0.6
READ SWITCH
SIGNAL (UNGROUNDS
DIGIT LINES, D AND D')
~--";---..!f--- --~-4
~I,ro:s¥~~l
12
1
PULSE
READ DELAY
MONOSTABLE
+4
"-i-----~i--....;1:...----:-'----1
Y-ADDRESS
--~+4
Y-ADORESS
PULSE
-14
OE~Y
Y-ADDRESS
DELAY MONOSTABLE
I ~--I-14
~I
:' ,...,,''''
~~--~--~~--~---~O OE~Y
~---I+l2
X-ADDRESS
PULSE
1-----1-14
I
I"'''''''''''!,,'" "" ,1" """''''?"'''
READ COMMAND
(FROM MEMOR Y
EXERCISERI
---/
VOLTS
I
+4
1.0
TIME (MICROSECOND)
0.4
02
06
0.8
10
TIME (MICROSECOND)
Figure 2-Memory timing diagram for write cycle
Readout of the cell (Figure 3) is accomplished by
addressing the cell in the same manner as for writing.
Both the digit and digit complement lines are near
ground potential for read. When addressed, current
from the "on" transistor in the bistable will flow into
the respective digit or digit compleII:1ent line. The
node of the "off" transistor will be near ground potential ahd, hence, will not cause a current flow into the
corresponding digit line. A differential amplifier, connected to the D and D digit lines, senses the readout.
The monolithic chip, shown in the microphotograph
of Figure 4, measures 80 mils by 100 mils and contains
64 memory cells interconnected to form one bit of
64 different words. One memory cell occupies an area
of approximately 100 mils 2 on the chip. The chips
were individually housed in 22-lead flatpacks. The
monolithic parameters of importance, external to the
flatpack, are the capacitanc('!s looking into the restore,
the digit and the address terminals. These capacitance values are shown in Table I based on averages
of several flatpack samples.
Figure 3-Memory timing diagram for read cycle
Table I
Capacitance to Substrate Measured on 64-cell
Monoliths Housed in 22-Lead Flatpacks
Measured Point
(to substrate)
D line
D' line
X line
Y line
R
Typical
Capacitance
(picofarads)
17.08
16.75
7.00
7.48
26.5
System description
Figure 5 shows the basic organization of the system,
The memory stack is comprised of the MOS transistor
arrays described in the preceding section, while the
peripheral circuitry is composed of the address decoder, write drivers, sense amplifiers and timing circuits. In the case of this feasibility model, the memory
384
Fall Joint Computer Conference, 1967
Address decoder
The 20 address input lines (l 0 digits plus complements) supplied from an address register (contained
in he exerciser unit) represent a capability for addressing the 1024 words in the memory. Decoding is
achieved in a conventional manner for a two coordinate
addressing system. Figure 6 presents a block diagram
of one of the .two identical X or· Y decoders. Three
of the~five digit inputs are decoded by eight NAND
gates, labeled 0 through 7, while the remaining two
digits are decoded by four NAND gates (A through
D). These respective NAND gates drive pulse activated
transformer circuits which in turn drive a 4 X 8
matrix of transformer circuits for the 32 output lines.
Schematics associated with the various blocks are
shown by inserts in Figure 6. Commercial integrated
circuits were employed. for the NAND gates. One
high level matrix driver and one low level matrix
driver is actuated in correspondence with the address
code when the address command pulse occurs. The
two actuated circuits in turn select one of the 32.
identical address driver circuits in the address matrix
corresponding to the circuit path from the high level
oriver through the transformer winding to the ground
return provided by the low level driver. Operation of
the address driver circuit is discussed in a subsequent
section dealing with power conservation.
Figure 4-Monolith arrangement of 64 memory cell circuits
exerciser system (not shown) was built into the system
to serve as the data processor. The exerciser supplies
write information, and accepts read information from
the memory, and also has the capability of detecting
and locating any digital errors created in the memory
system in terms of the word address and specific
bits in the word.
As shown in Figure 5, the lO-bit address input is
divided into a 5-bit section for decoding in 32 Xlines and a similar 5-bit section for the Y lines. A
common pair of digit lines (Data and Data) connects
all l024 memory cells corresponding to a specified
bit :n each word. These digit lines are multiplexed to
carry both the write and read information to and from
the memory.
Each 64-cell chip in Figure 5 is labeled with the
address line designations which it receives. The columns
represent the bit or digit positions, while each row
represents a 64-word group.
Bipolar transistors were found advantageous for
driving the large capacitances associated with the
memory arrays. These bipolar peripheral circuits are
individually described in the following paragraphs.
Write drivers
Sixty input data lines (30 digits plus complements)
representing the information to be written into the
memory, are supplied from the memory exerciser.
Each input line is supplied to a write driver circuit.
Upon receipt of the write command, the lines having
a logic "l" state activate the respective write driver
for either the D or D digit lines.
The schematic for the write driver is shown in
Figure 7. The digit line associated with each write
driver is grounded through Rs and Q4 during quiescent
operation. When writing, Q2 is turned on if the transformer is energized, while Qa and Q4 are driven off
thus allowing the twelve volt write pulse to be developed on the digit line. When the pulse terminates,
Q2 is driven off by the reversal of voltage across the
secondary windings due to "flyback" action6 of the
transformer, while Qa and Q4 are driven on. This
rapidly discharges the digit line capacitanet and
clamps the digit line back to ground.
Read sense amplifiers
Similar to the write drivers, each of the 30 sense
amplifiers connects to the main digit (and digit complement) line which ties together all the individual
digit lines from the 16 flatpacks corresponding to a
Low Power Computer Memory System
385
30 BITS WRITE DATA
tit
r
WRITE
COMMAND
PULSE
WRITE STROBE
CIRCUITS ~---..!!!..:.:..!..!::..::..:..:..:;===-~----
.....~f----.--+--. ••
WRITE
DRIVERS
ADDRESS
ACTUATE
64 CELL I---~
MONOLITH
(TYP.)
30-ROW
BY
16-COLUMN
..
~NLlTHIC
ADDRESS
DRIVER LINES
10 BIT
ADDRESS
CODE
INPUT
MEMORY
•
•
•
•
•
•
•
•
•
•
•
X24- X31
Y 24-Y31
READ
COMMAND
PULSE
CIRCUITS
~
READ STROBE
L __ ~
•••
,
• • •
¥
30 BITS READOUT
Figure
5~Block
diagram of memory system
specified bit position. When a read command is re.ceived, the memory cells of the addressed word supply
current to the digit lines. The differential between the
digit and complement line signals are sensed to produce the corresponding read output when the strobe
pulse is applied by the read strobe generator circuit.
The real sense amplifier schematic is shown
in Figure 8 .. In consists of a differential amplifier (Os and 06) which "primes" a flip-flop comprised
.of transistors 01 and 02. When the negative strobe
signal is applied to the flip-flop it is actuated to the
state determined by the differential amplifier. The
sensitivity of the sense amplifier is improved by isolat-
ing the flip-flops from a possible unbalanced output
loading by employing buffer transistors 03 and 04.
Restore circuits
The restore pulse, as previously described, is applied
periodically to each cell in the memory to discharge
the voltage buildup, due to leakage current, on the
. intrinsic capacitance at the flip-flop node.
To prevent large surges of current that would be
required if the restore signal were applied to the entire
memory simultaneously, the memory is divided into
eight sections. Figure 9, showing the restore circuitry,
consists of a 3-stage counter and associated binary-
386
Fall Joint Computer Conference, 1967
r----------------mWLn-'
,
I
I
IHIGH DfI1VEROo-I~....._::..;I~
I
I
I LOW DRIVER 0,-M---~I>
I
I~----~
I
I
1.5:1:1
'
I
R4
,
m~1
I
r------,
I
TTL INTEGRATED I
I __
CIRCUITS
_ _ _ --.1I
~~
-7
32·ELEMENT ADORESS UNE DRIVER MATRIX
A.
I
'\
I
r----------XO(Yo)
L_('L _ _ _ _ _ _ _ ~VOL~ _ _1
/,(y,)
I-----------~~----I
I
'I
,
I
I
5
CRI •
IN3605
TOTAL
COLUMNS
I
DECDOING l : : : J l . S : l
I GATE RETURN
10
.. . -.- ...
I
2
Tl
•
3
CR2
IN3605
I
I
~~~ORM£R I++-----:-----i----'
RETURN
I
I
ADDRESS
LINES TO
MEMORY
TOTAL 8 ROWS
L _______ ~ ____ J4tOrn _ _ _ _ ~
5 BITS OF
ADDRESS CODE
---------,
r - - - - - - - - - - - +4WLTS
I
I
R2
I
5 OHMS
I
I
10
CL·47 MICROFARADS
4GROUND
ADDRESS
ICOMMAND
I
I
I
I
I
I
Figure
I
I
~
I DE~ODING
I GATE RETURN
2
TO ADORESS
IL _ _ _ _
__
_____
(b) _ _ _ _ _ _ _ _
DRIVER
MODULES
6~Address
decoder block diagram with circuit
schematics
to-octal decoder, with each output of the decoder controlling a respective restore pulse generator. A selfcontained restore clock, asynchronous with the rest
of the system, generates the shift pulses for the counter.
Each time a restore clock pulse is generated, the pulse
gate corresponding to the actuated line of the octal
decoder delivers a pulse to its respective restore driver.
The restore driver schematic is shown in the insert
of Figure 9.
Timing control circuits
The control circuits cause the memory to be addressed whenever a read or. a write command is received, and they generate the corresponding activating
signals for the sense amplifier or the write driver circuits. Figure 10 shows a block diagram of the control
circuits, with integrated monostables used for timing
control. The schematic for the address command pulse
driver, shown in Figure 11 is typical of the. output
driver circuits in Figure 10. Signal timing diagrams for
the write and read cycles, respectively, are shown in
Figures 2 and 3.
Physical arrangement
The physical packaging arrangement utilizes four
multilayer printed circuit boards two for the
memory stack and two for the peripheral circuitry.
The X-address decoder and the restore generator are
packaged on one of the periphral circuit boards. The
Y -address decoder and the control pulse circuitry are
packaged on the second peripheral circuit board. No
attempt was made to achieve a high degree of miniturization in this developmental effort.
The memory array consists of 480 identical flatpacks arranged in a 16 by 30 matrix and packaged
on two multilayer printed circuit boards. One of
these boards with the full complement of 120 flatpacks is shown in Figure 12.
The memory, exerciser, and power supplies are
. packaged in a Samsonite suitcase with exterior dimen-
Low Power Computer Memory System
387
+4 VOLTS
LI
6.8 MICIIOHENRIES
5
TO CIGIT LINE
(C OR Ii )
~---=-----r--J"'~----
PROCESSING
,
"
PROCESSING
@,
1.0
t:::\
'\SI
"'
<'!>----0------ AVERAGE
40
.5
T
TIME
(SECONDS)
30
EFFECTIVE SYSTEM
RESPONSE TIME FOR
MULTI-JOB
PROCESSING
24K
JOB DEFINITION TIME
32K
40K
CORE MEMORY SIZE (WORDS)
10
Figure 7 - Average job processing time
24K
32K
40K
CORE MEMORY SIZE (WORDS)
Figure 6-Job turn-around time (multi-job processing)
Recalling that 40 seconds of the average job turnaround time i~ attributable to user response delays,
one can see in Figure 6 that the average rate of processing defined jobs is on the order of two seconds.
Here, then, is the explanation of the lack of buildup
in the job queue. With each user requiring about 40
seconds to define a job, the combined group of users
can input an absolute maximum of one job every five
or six seconds, while the processor can handle defined
jobs at about three times that rate.
Job processing time
There were differences, though small ones, in the
average processing times for each run. processing
time, in review, is defined from the time of input of a
defined job at the job queue to final output at the terminal. Figure 7 depicts the average processing time
for multi- and single-job processing, as well as for a
defined-"effective" multi-job processing time.
Curve A of Figure 7 is drawn from the results for
the multi-job processing scheme. In the 32K model,
two jobs were taken from the job queue whenever
possible and processed together to completion. In
40K, up to three jobs were processed concurrently
when they were available in the job queue. This approach moves more jobs through the system in a given
amount of time than does the single-job processing
scheme, by avoiding, among other overhead functions,
repetitious program reading. For example, if two jobs
processed individually take two seconds each, the two
processed together might take a total of 3.9 seconds
for a time savings of 0.1 second. Note that for the jobs
processed individually, the average is two seconds,
while the two processed together, by virtue of waiting
for each other, average 3.9 seconds each in the processing area. On occasion, the user might in fact
sense this real delay as his job, the first in the job
queue, waits for other jobs in the batch to be completed. Nevertheless, the system would experience
an over-all improvement in output rate. Curve A
shows the average job processing time, perhaps more
accurately called average time in the processing phase,
as seen by the terminal user.
Curve C represents an alternate viewpoint of the
multi-job processing capability by showing the "effective" system response time. The effective system response time for ajob in a multi-job processing system
is defined here as the quotient of the processing time
for a batch of jobs processed together divided by the
number of jobs in the batch. Thus, from our prior
"example, two jobs processed together in 3.9 seconds
would be said to have an effective system response
time of 1.95 seconds each. But this view of system
Design of a Multiple-Access Information System
performance although useful to the system designer
is more relevant to the system manager than the system user.
Since there were no significant buildups in the job
queue, the multi-job processing solution had little
opportunity to produce any important processing
gains relative to the single-job processing scheme. A
comparison of Curve B, drawn from the results of
the single-job processing runs (multi-job processing
i.lhibited in 32K and 40K) with Curve A demonstrates
that this was in fact the case.
Equipment statistics
The cpu utilization, disk channel, disk arm and
magnetic tape channel utilization statistics for each
run are listed in Table II.
MULTI-JOB
PROCESSING
CORE MEMOR)
SIZE (WORDS)
CPU UTILIZATION ('Yo)
01 SK CHANNEL
UTILIZATION ('Yo)
DISK ARM
UTILIZATION (%)
•
•
•
•
SINGLE-JOB
PROCESSING
24K
32K
40K
32K
40K
9.0
6.6
5.8
9.0
8.9
24.2
19.8
11.9
24.2
12.3
5.6
8.9
5.7
ARM 1#1
6.9
7.5
ARM 1#2
18.4
11.3
3.8
15.4
4.4
ARM 1#3
11.1
10.2
10.1
11.4
11.2
ARM 1#4
2.5
3.2
2.7
2.7
2.6
MAGNETIC TAPE
CHANNEL UTILIZATION
.2
.2
.2
.2
.2
(%)
Table II - Equipment utilization statistics
For all core size designs, the simulated cpu was performing useful work; that is, not idling, for less than
10% of the simulated run time. This apparently low
percentage should be viewed in light of the fact that
for approximately 66% of the time the cpu is forced
to idle because there are no jobs in the system, and
therefore the maximum possible cpu utilization in
the type of operating environment modeled is approximately 33%. The decreasing cpu utilization with increasing core size is attributed to the reduced requirement for executing program loader and initialization
functions.
The disk channel utilization, which represents the
percentage of the simulated run time during which
commands or data were being transferred via the disk
channel, shows a decrease at the increasing core size
designs. This reflects the impact of not reading processing programs from the disk at the higher core
445
sizes. Thus, it can be interpreted that for the 24K
core size design approximately one-half of the disk
channel utilization time is spent in transferring processing programs from disk to core.
The utilization of the magnetic tape channel, which
was modeled as a path distinct from the disk channel,
was extremely low and constant for all core size designs. The constant 0.2% value is attributable to the
fact that of the job types modeled, only the file update job was defined as requiring data transaction
recording on the tape. Both the frequency of occurrence of this job type as well as the volume of data
transferred was low.
Disk arm utilization, per arm, is relatively constant
for all core size designs with the multi-job processing
capability. The reading of processing programs from
disk arm #2 accounts for the higher utilization at the
lower core size designs. Similarly, the disk arm #2
utilization for the 32K core size design with singlejob processing is higher than the 32K design with
multi-job processing because more program reads
were executed to. handle the jobs singly than in
groups. Disk arm utilization is a valid criterion for
evaluating the merits of a disk map relative to the
reliability of disk operations. That is for any given
core size design, a constant utilization across all four
disk arms reflects an evenly distributed work load
and minimizes the relative vulnerability of any particular disk arm to failure.
SUMMARY
The primary goal of this effort was to examine from
the system user's point of view, the effect of core
memory size on system performance. For a dedicated
special-purpose type of multiple-access information
system such as the one modeled, it was evident that
the advantages to be gained through· incremental increases in core storage space could only be reflected
in the model, as well as in the actual system, by increasing the system's apparent processing capability.
The specific interest here was not in validating a
specific software design, particularly since at the time
the activity was conducted neither a control nor application program solution existed. Therefore only an
envisioned design, deemed to be appropriate and responsive to the implied requirements of the system,
was modeled on a broad, or macro, level Starting
with a 24K word core memory size which was pased
on certain assumptions of program, buffer, and work
space requirements, the capability of the processing
system was improved for additional increments of 8K
words by increasing the available user work area.
In the modeled system, this allowed for more appli-
446
Fall Joint Computer Conference, 1967
cation programs to co-exist in core memory and increased the multi-job processing limit.
The most significant characteristic of the system,
as demonstrated by the simulation statistics, was the
slow job input rate relative to the fast job processing
rate; viz., a ratio of approximately 1: 3. Since the user
terminals were the sole source of jobs into the system,
then the man-machine mechanism for entering job
statements was most significant in establishing the
input rate. This disparity in rates was such that there
was no significant queueing in the system at any core
size solution. It is evident that the operational configuration represented in the model could withstand
substantial 'change and not appreciably affect the job
turn-around time. With the same job types and operational procedures, doubling the number of active
user terminals, for example, would only raise the job
input rate to approximately two-thirds of the processing rate. With eight user terminals active, halving
the number of steps in the job definition sequence or
halving the speed of the modeled cpu would have
similar effects.
The cpu represented in the model is characteristic
of the' processing power usually associated with multiple-access time-sharing systems, and on that basis
was a priori consIdered to be an appropriate hardware solution. As the run results indicate, however,
the cpu overpowers this system's processing problem.
A cpu with one-half to one-third of the execution
speed modeled (i.e., an average instruction execution
time between,20 JL seconds and 30 JL seconds) could
still result in an input to processing rate ratio of less
than unity, and thus no significant queueing in the
system. The processor's response to user input would
be slower, of course, but imperceptibly different to
the system user.
Based on an understanding of the operational requirements of this system and some prior association
with information handling programs, a level of detail
was established in the model which would support
the objectives of the simulation. Certain quantitative
assumptions established the minimum core size to be
modeled at 24K w~rds; this was an arbitrary reference
point from which to examine the effect of core memory size on system performance. The run statistics
showed that as the oore size, and hence the processing
capability, increased there was no appreciable change
in system performance from the system user's point
of view. We conclude that not only is the smallest
core size modeled adequate, but that lower core memory sizes (i.e., 16K words or less), which would require considerably more, program overlaying in the
control and user program areas, would provide
an adequate and responsive solution. Implicit in this
conclusion, is that an improved processing capability,
such as multi-job processing in the modeled system,
is of little value in a system where the job input rate
is considerably slower than the processing rate.
Admittedly, certain of these results could have been
determined through analytical methods. This is largely
due, however, to the nature of the chosen example
system. In general, the system designer's choice of
analysis methods should' not be delimited by only
the immediate considerations, but should instead be
made in light of the entire planned system development activity. A simulation program model, even in
the case of the cited example system and however
gross in its initial form, provides the designer with an
important analysis tool which can be modified and
refined part by part as the system design phase progresses so as to evaluate and verify the evolving solution.
A mUltiple-access, information storage and retrieval system in which the job input rate is considerably
slower than the job processing rate has been discussed
here, whose design requirements contrast rather
sharply with those of other mUltiple-access computing
systems. This special purpose system is representative
of a type which can be expected to become widespread
as data processing extends to the smaller installations
and users. The handling of current account data on
credit applicants in a merchandise chain or the maintenance of current warehouse inventories by wholesale distributors are examples of such systems which
typically would not require extensive processing
power. The information storage and retrieval processing requirements of these types of installations
as those of our cited military system, can be satisfied through straight-forward programming solutions,
implemented on computers with moderate speeds and
with modest core memory capacities.
This activity, furthermore, has served to emphasize
the value of a macro level modeling approach to a system design problem; which in the authors' opinion is
a fact not commonly enough recognized. When employed as early as is reasonable in the design process,
it can yield, with an economy of effort, valuable insight to the system under study.
REFERENCES
1 J McCARTHY
Time sharing computer system
In Computers and the World of the Future M. Greenberger
ed. The MIT Press Cambridge Mass pp 22 I-236 1964
2 J BDENNIS
A multiuser computation facility for education and research
Communications of the ACM vol 7 pp 521-529 September
1964
3 AHTAUB
On time-sharing systems, design and use
Proceedings-IBM Scientific Computing Symposium on Man-
Design of a Multiple-Access Information System
Machine Communication pp 9-16 1965
4 RMFANO
The MAC system: the computer utility approach
IEEE Spectrum pp 56-64 January 1965
447
5 J I SCHWARTZ et at
A general-purpose time-sharing system
Proceedings-Spring Joint Computer Conference pp 397-411
1964
SODAS and a methodology for system
design
by DAVID L. PARNAS and JOHN A. DARRINGER
Carnegie Institute of Technology
Pittsburgh, Pennsylvania
INTRODUCTION
of a problem before attacking it. Throughout such
courses or textbooks this appears as a recurrent theme:
A precise definition of the problem is a prerequisite
to the complete understanding of the problem by the
designer. A precise definition of the problem is the
first step in finding the proper structuring of the problem into sub-problems. A precise definition of the
problem is necessary to the evaluation of proposed
solutions.
In the design of complex systems, such as computer
systems, precise definitions of the goal of the design
process are not easy to find. As a particularly simple
example, consider the problem of designing a special
purpose traffic control computer for the single intersection shown in Figure 2. Certain aspects of the
problem are easy to define. The nature of the inputs
to the computer can be specified, e.g., "20 inputs from
sensors: 1 volt indicates the presence of a car, 0 volts
the absence of a car." The nature of the outputs (e.g.,
the lights to be controlled) can also be specified. It is
very difficult to specify the behavior desired of the
computer. One can discuss the design criteria for the
behavior of the computer, e.g., it should minimize average wait time or maximize the traffic handling capacity.
One can place restraints on the behavior, e.g., the
maximum time for lights to remain in any mode is
three minutes. Such statements do not specify the behavior; they constrain the behavior of the system. One
of the design principles motivating the design of the
SODAS system is that the behavior should be defined
before the design of the computer itself is started.
The behavior of the system can best be described
by an algorithm. * Certain variables in the algorithm
can be designated as inputs or outputs, the behavior
of the system described being the output response to
each permissible string of input values. A designer who
begins the design of a computer or similar system without such a specification has set out to solve an un-
SODAS (Structure Oriented Description And Simulation) is a simulation language and compiler being designed at Carnegie Tech for use as a tool by the designers of computer systems. The structure of the language and its translator reflect a definition of "system"
and a methodology for "system design." It is the purpose of this paper to present the proposed methodology
and language.
Definition of "system"
We shall propose a definition of "system" to be used
within this paper. It is not proposed as a general definition of system, but as a local definition within this
paper as an aid in discussing the design and simulation
of systems. There may be systems which do not fit the
definition, but it will be clear that those items usually
called computer systems, either hardware or software,
do fit the definition.
A system is a connected set of components whose
behavior is self determined. By self determined we mean
that the state and outputs of the system can be predicted from knowledge of the state of the system and
the inputs. A component is a device or program which
is self determined and may, in fact, be a system itself.
By connected we mean that the inputs to some of the
components may be the outputs of other components
of the system. It should be clear that the distinction
between system and component is one of level rather
than substance. Any system may be a component of
some other system. Ultimately, the components of the
system are basic units of some sort. The only requirement that we place on these basic units is that they
have well defined behavior, i.e., that it must be possible
to find an algorithm which describes their behavior.
A system design methodology
A principal point in most courses in engineering
analysis is the importance of having a precise definition
• *The algorithm need not be a computer program.
449
450
Fall Joint Computer Conference, 1967
specified problem and, in all likelihood, he will design
a system with suboptimal behavior (because he will
confuse the question of behavior with the question of
how to construct the system). The availability of an
algorithm specifying the behavior makes it possible (1)
to experiment (by simulation) with behavior explicitly
(thereby determining exactly what is optimal behavior),
and (2) to compare a proposed design with the specified behavior (to make sure that the system, as designed, accomplishes its goals).
After the behavior of the system is specified, a further structuring of the problem is desired. This usually
means a specification of the various sub-systems or components and the way in which they are connected. Each
of the sUb-components will then become a design problem in itself. Two problems arise: the first is specifying
the behavior expected of the sub-component; the second
is determining that the specified sub-components, working together, will actually result in correct behavior for
the whole system. Every system design team has had
the experience of bringing together separately designed
components only to find either (1) that the specifications for some component had been ambiguous or
misunderstood or (2) that the components actually
did not work together, although they did meet the
specifications. The behavior of the sub-components
may also be specified by algorithms. If desired, these
algorithms could be verified by simulating the set of
connected components and comparing the behavior of
the whole system to the original specification of its
behavior.
Each of the sub-components can then be broken
down in the same way, until units small enough to be
completely designed are obtained.
We call this approach to system design the "top
down" approach. It involves starting at the "top" with
a complete specification of the desired behavior of the
system, then breaking the system down into smaller
and smaller components until the system is specified
in terms of the basic building units.
If the specifications are in languages for which computer translators are available, then it is possible to
make use of simulation throughout the design process
(to verify that the specifications correctly indicate the
desired behavior). The specifications at every level
provide evaluation criteria for the next lower level.
It is probably worthwhile noting the most obvious
and important advantage of using simulation throughout all levels of the design problem. Often when the
design has reached a level of great detail, decisions
made at higher levels demonstrate themselves to be
inconvenient and costly. If the lower levels of detail are
reached only when the design has progressed to the
point where a hardware implementation has begun, it
is often too late to go back and make changes. If the
simulation language allows the design to proceed to
gr~~t detail, entirely in simulation, a new feedback loop
is added to the design process. The detail design of one
component can be allowed to influence a higher level
design of that component or other components. The
result should be a better design with fewer last minute
changes.
Properties of the specification-design
language and translator
In the following paragraphs we shall attempt to list
and discuss the features which must be present in a
specifications language and simulation system if it is
to be a useful tool for "top down" system design. In a
later section of the· paper we shall discuss our current
attempt at producing such a language and show that it
provides the necessary features.
(1) Designation of inputs and outputs
It is necessary to specify which variables in the
algorithm describing a system are inputs and outputs.
If these are not distinguished, the system is likely to
be overspecified (since the designer will have to produce a component that will duplicate the behavior of
the algorithm on all its variables, not simply those
which will be used as inputs and outputs).
(2) Combination of independently written
descriptions
The language must allow the description of systems
of components which have been separately described.
It must be possible to take separately written algorithms,
indicate the way that inputs of one are connected with
the outputs of others, without excessive worry over
conflicts in names of variables, etc.
(3) Correct handling of simultaneous events
The translator for the language must be capable of
correctly simulating simultaneous events in a system.
If two of the separately described components (as mentioned above) happen to be active at the same time
anJ interact closely, the translator must correctly simulate these simultaneous events (although it is restricted
to serial execution of the individual algorithms). A
method for doing this has been described in detail elsewhere. 1
(4) Components which are themselves
descriptions of systems
The language structure must be recursive; i.e., any
system described in the language must be acceptable
as a sub-system of a system to be described in the
language. To phrase it another way, all the features
available to the designer for describing the whole system
must be available for describing the sub-systems.
SODAS and a Methodology for System Design
(5) Descriptions with mixed levels of detail
The language and translator must permit the description of components of the system in varying levels
of detail. The design of one component may advance
faster than the design of the rest of the system. It
should be possible to combine a detailed description
of one component with less detailed specifications of
others for testing purposes. Without this the detailed
testing of components in large systems would be impossible.
(6) Mixed structural and behavioral descriptions
The language must allow structural or behavioral
descriptions, where appropriate. A structural description of a system describes it as a set of components
and their interconnection; a behavioral description is
an algorithm which duplicates the behavior of the system. At various stages in the design process there is
need for structural descriptions, behavioral descriptions
and mixtures of both. The language must be designed
L Jermit this. (The ultimate goal of the design process
is ~sually structural description down to a low level of
detail, but the description of the components at the
lowest level is behavioral.)
(7)
Br~d
class of systems
The language must allow the description of both
synchronous and asynchronous discrete systems as well
as analog or continuous systems and hybrid systems.
(8) Variety of languages for component description
The descriptive language and simulation system
should allow a variety of means of describing the
various components in the system. There are already
many general purpose and special purpose simulation
languages. Each of thes~ has its own strengths and
weaknesses. The language most appropriate for the
description of one component may not be the same as
the language most appropriate for the description of
other components. It is a desiratJle (though not strictly
necessary) feature of a simulation system that it permit
the description and simulation of systems whose components are described in quite different languages.
Often considerable space may be saved by simulating
a part of the system in space-taking detail and the
remainder at a higher level which requires less space.
Other significant design goals for the language which
are not peculiar to the problem discussed here include:
( 1) Small local changes in the system being described should require only small or local
changes in the descriptive program.
(2) It should not be necessary to provide duplicate
descriptions of duplicate components or even
451
of components that differ only in the values of
parameters.
A description of SODAS
This section is a description of the SODAS language.
Several preliminary comments are in order:
(l) SODAS is an experimental language and is in
the midst of its first experimental implementation. This results in several problems:
(a) Some of the sub-languages to be used in
the system are not as yet defined. The
grammar contains several terminal symbols
indicating descriptions in other languages.
These will eventually become non-terminals
in the language.
(b) The language has not received actual use.
Use will undoubtedly reveal restrictions and
omissions in the language which will have
to be removed.
We have chosen to present the language at
this time in spite of its unfinished implementation because we felt that the philosophy underlying the system is sufficiently different from
the underlying philosophy of other simulation
languages to be worth communicating in itself.
Further, we hope that interested readers not
involved with the project will give us the advantage of their different viewpoints with constructive criticism.
(2) Our preliminary implementation of the language uses a slightly extended version of the
Wirth-Weber precedence analyzer and parser
which was described elsewhere 2,3. The class of
grammars for which this analyzer is useful is
only a proper subset of the class of context
free grammars. In order to use the analyzer
the grammar has been distorted from what
might seem a more natural grammar for the
language. Readers who wonder about certain
parts of the grammar where the construction
seems a bit strange can attribute the strangeness
to our attempts to force the grammar into a
restrictive mold. While it would have been
possible for us to use a different grammar for
expository purposes than we are using in driving
our implementation, such an approach seems
to introduce too many possibilities for error
and has thus been avoided.
The main points contained in the grammar shown
in Figure 1 are:
(1) A SODAS system is a set of sub-systems, each
with specified inputs and outputs, together with
a "wiring diagram" description of the way that
452
Fall Joint Computer Conference, 1967
is a property of the simulation algorithm that
is the basis of SODAS. The algorithm depends
only on the existence of algorithms for simulating the sub-systems and not at all on the language in which the algorithms were originally
described.
the components communicate.
(2) There may be only one sub-system-the system itself-or any number of sub-systems.
(3) The sub-systems may be described in any language which has been implemented in the system, including the SODAS language itself. This
t
:: = I I
SODAS begin end I
SODAS begin end
::=
::= I ;
; I
::= integer I real I Boolean
register
::= identifier-J , identifier
::=
::= input I input array
::= output I output array
::= I array
::= identifier I [ ]
::=
:: = ~ •
::=
::= I ;
::=: ,: ::=
::= [ ]
::= subsystem ( ) <=dep decs>
<€omp body>
subsystem /
subsystem I
subsystem ( )
::= I ~l~ck
::= subsystem
subsystem
subsystem ( ) I
subsystem
::=
::= I ;
::=
::= ~ I ~ I
" ~ I " ~
::=
::=l1 , I
,
::=
::=
::= I
::= I ~odee>
::=
::= I
I
I
Figure I-Grammar for SODAS
SODAS and a Methodology for System Design
There is, however, much information about the language which cannot be contained in the syntax.
The language is designed for use in simulating discrete systems. These are systems which can be considered as changing state only at discrete points in
time known as "clock pulses." As is always the case
in simulation on digital computers, systems whose state
variables are changing continuously over periods of
time can be simulated only to the extent that they can
be approximated as discrete systems. *
The, algorithms descriGing the behavior of a system or component describe the behavior on each clock
pulse. The variables in the algorithm are the memory
of the component, the information that it carries from
clock pulse to clock pulse. Inputs are read and outputs computed on each clock pulse. It is, however, possible for· an algorithm to indicate that it will be inactive for a fixed number of clock pulses or until certain external conditions hold. The simulation system
can take account of this in determining an efficient way
to simulate the system.
To correctly simulate simultaneous events by simulating the individual events in sequence, it is sometimes
necessary to simulate one component, restore it to its
previous state, and later simulate it again.
Therefore, the simulation algorithm requires of a
sub-language that its compiled algorithm can be simulated without a permanent change in the state variables
or memory of the algorithm. Since this is the only firm
requirement of sub-languages, it is possible for sublanguage compilers to be written independently of the
SODAS compiler itself.
We shall now consider the interpretation of the
various syntactic units of the language.
SODAS DESCR: A SODAS description may be a
description in any of the various other languages included in the system, or it may have the form:
SODAS BEGIN
- - - END
The terms in italic are terminal symbols in the
language and have no syntactic definition in the grammar.
DEC SET: A DEC SET is a set of declarations much
like ALGOL declarations. Variables may be declared as
inputs, outputs, or simply interconnecting variables.
Those declared to be inputs and outputs are for use in
communicating, witth external systems; the others are
used later in describing the way that the components are
connected. They may be thought of as patch cords
which are used to connect the output of one compo*This restriction is fundamental to the problem of simulating
continuous change on a digital computer. It is not a special
restriction in SODAS, nor is it a disabling restriction. We are
as close to achieving design goal (7) as is possible.
453
nent to the input of another.
C-DEC SET: A C-DEC SET is the set of component
declarations. Any component or type of component
which will be used more than once in the system can
be declared here and given a name and optional parameters. The name can be used later as a substitute for
a description of the component. If the parameters are
given, then the declaration is a description of a class
of components. A member of this class is determined
by supplying values for the parameters during the use
of the component. Separate uses of the component or
members of the class of components are completely
independent. They have no common memory or interconnectors. They are simply copies of a common template.
The form of a component declaration is:
SUBSYSTEM (
C-IDENT: The C-IDENT is the identifier assigned to
the component or class of components. The IDSET is
simply the (pos'sibly empty) list of parameters for a
declaration which defines a class of components. The
I/O DEC SET is a set of declarations (as described
above) which indicate the inputs and outputs of the
component.
DEP DECS: The set of statements known as DEP
DECS is a description of some basic properties of the
component. It is possible in SODAS to deal with devices that have instantaneous response. An output of
a device at some discrete point in time can be a function
of the inputs to that device at the same time. SODAS
is capable of simulating such components and systems
correctly, but it must have information about such
immediate dependencies.
A DEP DEC is a statement of the form:
(Output)
(Input)
IDENTIFIER ~. IDENTIFIER
The variable on the left must be an output of the component, the variable on the right an input to the component. Such a declaration indicates that the value of
the component on the left may be a delayless function
of the input indicated. If the statement is not true it
may result in a less efficient simulation than necessary,
or in some cases in the SODAS system's deciding that
the system cannot be simulated. An unnecessary statement will never produce an incorrect simulation, but
a missing statement might do so. It is planned to allow
such declarations to be conditional in future implementations-this will expand the class of systems that
SODAS can deal with. At present the syntax only allows
unconditional declarations.
The component body is a system description, either
in SODAS or in some other system
454
Fall Joint Computer Conference, 1967
COMPONENTS:
The syntactic type COMPONENTS is the set of all the parts of the sub-system.
Each component is either an instance of a declared
component type or is described in the body of the
system description. Components which are instances
of a type already declared are specified by the identifier
used in their declaration and the values of the parameters, if any. The declaration and body of other components appear in the system description. As each component is described, its connections are also described.
A connection is described by statements of the form
(Input)
(Interconnector)
IDENTIFIER ~ IDENTIFIER
where the identifier on the left is an input variable
for the component, and the identifier on the right is an
interconnector (or wire) in the system, or by a statement of the form
(Output)
(Interconnector)
IDENTIFIER ~ IDENTIFIER
where the identifier on the left is an output of the component and the one on the right is an interconnector.
By consistently placing the interconnector on the
right side of the statement, it is possible to resolve any
possible conflicts between the names of interconnectors
in the system and inputs to the component.
In the following we find it convenient to use the
term "parent" system to describe the smallest system
which contains a given system as a component. Any
system which contains the given system as a component
may be termed an ancestor.
Timing
It was mentioned earlier that each component of a
system is described by an algorithm which performs the
actions taken on a single clock pulse each time it is
executed. The most straightforward method of simulating such systems would be to execute every algorithm
on every simulated clock pulse. Such a simulation would
often be a very inefficient simulation of a system.
SODAS has several descriptive features which avoid
such simulations where possible.
The systems simulated in SODAS are discrete systems in that activity is presumed to occur only at discrete points in time. The system as a whole can be
thought of as being driven by an external clock pulse,
but the clock pulses need not be thought of as equally
spaced in time. There must be a clock pulse whenever
activity occurs, but these periods of activity need not
be at integer multiples of some basic time unit. This
facilitates simulation of systems whose sub-systems are
not naturally described on the same time scale.
Systems in SODAS may be either synchronous or
non-synchronous. In a synchronous system all subsystems or components are assumed to 'be clocked by
a master clock of the system. Activity takes place only
on clock pulses which occur once every basic time unit.
For each SUb-system, the time between clock pulses is
either the same as that of the parent system or some
integer multiple of it.
In non-synchronous systems each component determines its own periods of activity and inactivity. If all
components of a system are inactive, the system is inactive.
Both types of system may be simulated in SODAS.
A SODAS system is synchronous if all of its sub-systems are synchronous. A non-synchronous system may
have synchronous sub-systems, but a synchronous system may not have non-synchronous sub-systems.
Both synchronous and non-synchronous components
may be described as having a clock interval which is a
constant multiple of the clock interval of the parent
system. For synchronous systems the clock interval of
a component must be an integer multiple of the clock
interval of the system. For non-synchronous systems
the interpretation of the clock rate description is quite
different. Each non-synchronous component must keep
track of the simulated time. The clock rate description
simply indicates a difference in scale between the time
measures used within the component and that used in
the parent system.
Both synchronous and, non-synchronous systems
may have components which indicate that they are to
be inactive for periods of time. For a synchronous system the inactive periods must be integer mUltiples of
the basic time unit, but this restriction is not needed
for non-synchronous systems.
Both synchronous and non-synchronous sub-systems
may indicate that they will be jnactive until some
Boolean expression involving inputs holds. This is
equivalent to the wait until of SOL. s
A system is active only if at least one of its components is active. Thus, if all components of a system are
inactive, the system need not be simulated. If one or
more components are doing a "wait until," and their
Boolean expressions include inputs external to the
parent, then if all sub-systems are inactive, the parent
system must report to the ancestor system that it is doing
a "wait until," and indicate the variables involved.
It is hoped that the above provides a' sufficient set
of mechanisms to allow efficient simulation of subsystems which are essentially inactive (either marking
time or waiting for an external event). With this feature, one can approach the efficiency of systems like
GPSS 10 and SIMSCRIPT.ll The unique feature of the
simulation method used in SODAS is its behavior when
several components are active at once. At this point
SODAS can determine a correct order for simulating
the sub-systems.
SODAS and a Methodology for System Design
We are including an example to demonstrate the use
of SODAS. Since the SODAS system is not yet operational, we have had to simulate its behavior using
Carnegie Tech's ALGOL and BOOLEs• translators . The
problem is not claimed to be a practical problem, nor
is it touted as an example of a particularly good design.
It was chosen because it was small enough for presentation and assimilation in a relatively short period of
time, yet large enough to illustrate the features of
SODAS. The example is presented in considerable detail so that those who wish to study the way that the
language is used may do so.
The problem that will be discussed was first presented in a Carnegie Institute of Technology course on
logic design in 1963. In this course, the students must
completely design a working system in terms of idealized
logic. The problem constitutes a term project for groups
of three students who were seniors in Electrical Engineering. In 1963, the majority of the groups completed the design in the relatively short period of time
alloted. SODAS was not available to the students.
This project, and those of later years, gave the senior
author the opportunity of observing a large number of
design teams working on the same design project. This
observation led to a number of conclusions:
(1) Groups which used the "bottom up" approach,
designing small parts of the project and trying
to put them together into a total system, did
not produce working systems.
(2) Among the groups that were successful, the
work was generally quite poor, unstructured,
and incorrect, until they either hit upon ( or
were led to) the top-down approach. All work
before that could be classified as false starts.
(3) After the top-down approach was started, the
work progressed well until it became time to
test the unit composed of the components
designed separately by the various ·members of
the group. There were two distinct sorts of difficulties:
(a) Components which should have worked
together did not. The students did not have
a precise way of communicating the specifications of the components to each other.
When they came down to the moment of
truth, it was apparent that each had his own
idea of the division of labor. As a result,
extensive last minute redesign was required.
A few groups did not complete the proje.ct
due to this factor.
(b) Even though the individual components
met their specifications, the combined system failed. The difficulty was that the students had no means of verifying that their
455
initial structuring of the problem was correct and feasible. Some oversight at the
earlier "behavior specification of sub-components" stage had not been detectable until the components were designed and being tested .. These errors were often very
difficult to recover from, and the redesigned systems that did work often were
obtained at the price of poor performance
by the system.
We have no doubt that the SODAS system would
have been a great deal of aid to these students-enough
aid to turn what was, for them, a very difficult problem into a relatively easy problem. The authors feel
quite strongly that such problems are not confined to
students in courses, but are common in professional
circles as well.
The problem described below is deceptively simple.
Assigned to the class mentioned, without SODAS, it was
a problem that was probably too large for the time allowed to the students. With the aid of SODAS and
the methodology discussed above, it now appears far
too simple for the course. This may only be a matter
of appearance, resulting from our increased familiarity
with the problem; only actual experiments in design
with the aid of SODAS will test our conjecture that
the increased simplicity of the problem results from
the availability of the new system.
An example: design of a traffic control module
A modular design of a traffic control system would
include traffic control modules at each intersection and
a master control unit to supervise the overall operation.
In the following example we are going to look at possible specifications for an individual module and follow
through the design of some of the actual hardware-.
using the "SODAS Method" of system design.
Specifications for traffic control module
Each module is to control a single intersection such
as is shown in Figure 2 and be easily adaptable to a
simpler intersection. It is to operate with various degrees of influence from the master unit, ranging from
complete outside control to independent operation. In
addition to controlling the traffic lights, the module is
to supply information about the local traffic conditions
to the master unit.
To limit the complexity of this example, the module
will use only the two sets of modes (traffic flow patterns) shown in Figure 3. The first set (modes 1
through 4) is to be used if the intersection does not
have a separate left turn lane. Otherwise, the second
set (modes 5 through 8) is to be used.
456
Fall Joint Computer Conference, 1967
[JJ1(g]
I
LEG I
LEG 2
U§J
--
D1l
[jQ]
~
=rill&>
~_rnJ~~
I
I
D
SENSOR
~LIGHT
LEG 3
Figure 2-Model intersection
Control module inputs (from sensors and
master control unit)
SENSOR [1 :20]
-Sensor inputs (See
Figure 2.)
OUTSIDELIGHT [1 '12] -Master unit's control lines for the
lights
TMAX
-Maximum time in
any mode (traffic
flow pattern)
TMIN
-Minimum time in
any mode
CYCLETlME
-Total time to cycle
through all 4 modes
---
SODAS and a Methodology for System Design
457
~L~L~L~L
-JlJL -J tL ~ Uk- ~ L
I~I ~'r-I ~
SET NO.2 - LEFT TURN LANE
Figure 3-Traffic flow patterns
INITIALMODE
-Initial mode
COC
-Complete outside
control switch
LOC
-Limited 0 u t sid e
control switch
RESET
-Initialization switch
Control module outputs (to lights and master
control unit)
CARS [1 :4]
-Number of cars waiting
in each leg of intersection
LEFTTURN [1 :4]
-Lines indicating whether
cars are waiting in leftturn lanes
LIGHT [1: 12]
-Signals controlling the 12
traffic lights.
Through inputs COC and LOC the master unit indicates one of three possible degrees of outside control:
complete outside control, limited outside control, independent operation. When the module is operating
independently, it is expected to keep account of the
number of cars waiting to pass through the intersection
and to control the lights appropriately. The control is,
however, to be subject to two parameters, the minimum
time and maximum time to spend in anyone mode
(condition of the traffic lights). This will assure the
driver of a minimum amount of time to pass through
the intersection, once he receives a "green light," and
also assure him of a maximum waiting time (when he
Is on a little-used road intersecting one which is very
heavily used).
The LOC input signal indicates that the module is
to leave its completely independent operation and submit to limited outside control. In this type of operation,
the module is still partially in control, but is subject to
a basic cycle time imposed by the master unit in order to synchronize it with other units. The basic cycle
time is the total time in which the unit must complete
its cycle of all four modes shown in Figure 3. At this
time, of course, the master unit can also set the maximum and minimum times to values which will give
the module the degree of freedom desired. At the time
of initiating outside control the master control unit
indicates the initial mode for the module, thus bringing
about complete synchronization. Provision is also made
for direct control of the lights by the master unit (OUTSIDELIGHT [1: 12]). For each of the 12 lights at the
intersection, a line is provided to signal TRUE for
green and FALSE for red. It is assumed that the traf-
458
Fall Joint Computer Conference, 1967
fic lights have mechanical timers' that control the yellow light during the changes. .
The clock frequently is to be 10Hz. Although un;.
usually slow, it assures that all cars will be detected
correctly at speeds less than 100 mph.
First level of design
The first step taken was to treat the module as the
black box shown in Figure 4 and to write a SODAS
program describing its inputs, outputs, and behavior.
This initial description was written in SFD-ALGOL,7
an ALGOL-like sub-language of SODAS with facilities
for specifying inputs, outputs, and timing.
In conjunction with the above, a traffic simulator
was written. Such a simulator is most easily described
in a SODAS sub-language resembling SIMULA12 and
is treated as a component in the total system.
The entire system, including the traffic, was then
simulated and changes were made in the algorithm that
selects the traffic flow pattern until reasonable traffic
flQW was obtained. Since, at this stage, the control
algorithm was described in an ALGOL-like language
and not embedded in hardware, such testing and changing was a simple task. Figure 5 contains the SODAS
description of the traffic control system at this point.
INTERSECTION
LIGHT (j:I~
SENSOR
-
I--_----=C:.:....O=.=C.--~
/ /~1
C
M
A
S
T
E
R
C
o
TMAX
RESET
T
j1lzr
I
I
II/
~___T~M~IN~__~/Iij/
CYCLE TIME (TTOT)
I 1
I---!:.IN!!..IT:...:.:IA::.:L:....:.M:.:.::O~D=-E_-.;'
U
N
I
I
/
N
L
'~~
///~w
I-------=-~~---II~ /
T
R
o
--::.//J ,--",'"
L 0
~--~~'='~'~--~-
OUTSIDEUGHT
I
1/
III
TRAFdc
CONTRpL
MODU4E
~I
I
~: 12J ~ ~ 1
I
I
II
II
I'
CARS [1:41
I
I
/4---;;..;....;;..;.;;;..I.;...~--f-J- -
[I:~
-
LEFTTURN
) __ 14---~=-':'''':'';;''';~::...-:t-f/'''''-'
-
-
I
--1I
-
Figure 4-First level of description
D: 20J
Secoild level of design
At the second level of design, structural information
was added to t4e behavioral description obtained· above.
. The module is required to count the cars waiting
m each leg of the intersection at all times. Since this
task is identical for each leg and since such a counter
is easily isolated from the rest of the system, it was
decided to design four counters as sub-systems.
The single sensor in the left-tum lane makes the
counting of cars more involved. It is assumed that if a
car were waiting in the left-turn lane and there were a
green light on the last clock pulse, it would leave on
this clock pulse. This assumption forces the counter
for each leg to record the "left-turn light" to account
for cars leaving the leg through the left turn lane.
The module initially selects its traffic flow pattern
from the first set (Figure 3). It assumes that no leftturn lane exists until one of the left-turn sensors is
activated. These signals are combined by a "joiner"
(actually an "or" gate). Figure 6 indicates the structure
introduced at this point.
In the first level of design, the task of counting cars
was handled by the procedure "count." However, as
written, this procedure had to be executed twice for
each simulated clock pulse-once to update the carcount and again to store the value of the left-turn light
after it was determined.
At the second level of design, this problem is reflected in the fact that the values for LIGHT [1: 12J
(counter input) are declared immediately dependent
on CARS [1 : 4] (counter output). This immediate
dependency and others are indicated in the block diagram (Figure 6) by dotted lines apd in the .SODAS
description (Figure 7) by dependency statements.
The reader should note the close correspondence bet,:een the block diagram and the SODAS description.
Smce the four counters are identical, only one needs to
be described (by a component declaration). Then the
four counter descriptions are references to that declaration.
Third level of design
The third step in the design is the final step in our
example. In it the counter for leg 1 is divided into four
sub-systems and each of these is implemented in idealized logic elements (flip-flops and gates). Although
we could have introduced one more level by describing the components of the counter in SFD-ALGOL
these descriptions would have been extremely simpl~
and it seemed more reasonable to implement them directly using logic elements.
Of the five sensor inputs to the counter for leg 1,
two (1, 2) indicate cars entering the leg and two (3,4)
SODAS and a Methodology for System Design
SODAS Description
Comments
SFD begin
input Boolean array sensor [1:20J;
input Boolean array outsidelight [1:12J;
input Boolean loc, coc, reset;
input integer tmax, tmin, ttot, initialmode;
~t Boolean array light [1:12J;
output Boolean array leftturn [1:4J;
output integer array cars [1:4J;
integer mode, tim, ctmax, ctmin, cttot;
Boolean ltl;
real factor;
declaration of
input, output and
internal variable
procedure initializecontroller;
begin
integer i;
for i~1,2,3,4 do
--begin
cars[iJ(--();
leftturn [iJ~alse;
end;
for i~l step 1 until 12 do light[iJ~alse;
mode ~ initialmode;
tim~max;
ctmax~max;
cttot~
initializes
infernal
variables
(memory) and
output
factor~;
variables
ctmin~min;
if loc then
ttot else 1800;
ltl~alse;
end ititialization of the controller;
procedure count (a); Boolean a;
begin
if the parameter
own Boolean array lastleftturn [1:4};
a is true, the
Triteger i,j;
number of cars
for i~l, 2,3 ,4 do
--if a then waiting on each
leg is updated
begin
and a left-turn
for j~,3 do if sen~or [5*i-jJ then
lane is checked
--cars [iT~cars [iJ + 1;
-for. if a is
for j~ 2,1 do if sensor [5*i-jJ then
false, the
--cars [iJ-;' cars [iJ -1;
-values of
if sensor [5*iJ then leftturn [iJ ~ ltl ~ true;
the leftif leftturn [iJ A lastleftlight [iJ then
turn lights are
'begin
recorded to be
cars [iJ ~ cars [iJ-l;
used on the next
leftturn [iJ ~ false;
clock pulse.
end;
end else lastleftlight [iJ ~ light [3*iJ;
end count ;
- -
I
Figure 5-S0DAS description of traffic control module
at level one
(Pts I, II, III)
459
460
Fall Joint Computer Conference, 1967
Comments
SODAS Description
procedure setlights (a,b); Boolean array a;
integer b;
begin
integer i;
for i~l step 1- until 12 do a[iJ~ false;
if b=5 then a[ lJ~[ 6J~[ 7]~[12J~rue else
if b=6 then a[ 4J~[ 5J~[lOJ~[11}--true else
if b:c 7 then a[ 4 ]~[ 3 ]~[lO]~[ 9]H:rue else
if b=8 then a[ l]~[ 2]~[ 7]~[ 8]H:rue else
if b=2 then a[ l]~[ 4]~[ 5J~[ 6JH:rue else
if b=4 then a[ 7]~[lO]~[11]~[12]H:rue else
if b=l then a[ l]~[lO]~[ 2]~[ 3 ]~rue else
if b=3 then a[ 4}-a[ 7]~[ 8]~[ 9]~rue;-
end setlights;
sets the traffic
lights given a
desired traffic
flow pattern
(mode)
integer procedure newmode;
begin
integer i, high, nscars, ewcars, tcars;
nscars~ars[l] + cars[3];
.
ewcars~ars[2] + cars[4];
tcars~wcars + nscars;
if tcars=O then tcars~l;
if .ltl the-n-selects new
mode to maximize
the number of
cars allowed
to move
integer procedure cycletime;
if mode = 5 V mode = 7 then cycle time
else if .. lac then cycle time ~ tmax
else cycle time ~ factor*cttot;
~
tmin
SODAS and a Methodology for System Design
SODAS Description
Conunents
continue: time begin
if reset then initializecontroller;
if coc then
begiIl1ii:teger i;
for i~ step 1 until 12 do
--light [i] f- outsidelight [i];
go to done;
start of clock pulse
under complete
outside control
lights as set
by master
control's input
end-'-
--'
if lac then cttot
tim
f-
tim
f-
461
ttot else cttot
f-
1800;
}
{
under limited
outside control
the master unit
sets the total
cycle time
+ 1;
tim is time in mode
update car count
if tim> ctmax then
begin
tim f- 1;
mOde f- newmode;
ctmax f- cycletime;
setlights (light, mode);
count (false);
end;
done: go to continue;
end time block;
end SFD ALGOL description of traffic
---control module
indicate cars leaving. SENSOR [5] also indicates cars
leaving but only if the left-turn light is green. Thus
at a single clock pulse it is possible for the net change
in the number of cars waiting to be +2, +1, 0, -1,
-2,-3.
In looking for a structure for the counter, the following was noted:
1. A binary to decimal conversion would be needed
to allow communication between the binary outputs of the counter and the decimal inputs of the
rest of the system.
2. A special counter would be needed that could
accept increments of 1 or 2 and decrements of 1,
2, or 3 in a single clock pulse.
3. A network would be needed to decide
(i)
if a left-turn lane existed
(ii)
if cars were waiting in the left-turn lane
(iii) if a car had left via the left-turn lane
after specified
time select new
mode, new cycletime, and store
new light values
for counter
-
end of clock pulse
4. A decoding network would be needed to interpret the signals from the sensors and compute the
net change in number of cars waiting.
Figure 8 shows the block diagram of the counter
for leg 1 incorporating the structure discussed above.
The "special counter" is a 7-bit counter that ignores
inputs attempting to take its value below zero or over
127. This was done to limit error due to incorrect inputs or inadequate counter capacity.
The binary to decimal conversion was described in
SFD-ALGOL while the special counter, decoder, memory unit, and the joiner (Figure 6) were designed using
standard logic design techniques and described in
BOOLE,s another sub-language of SODAS.
Figures 9 through 12 show the structural diagrams
of the three counter components implemented in logic
elements. Studying these figures and the SODAS description of the memory unit at this level in Figure 13,
Fall Joint Computer Conference, 1967
462
LIGHT [I: 12J
....
.....
COUNTER I
~_~L~E~F~T~T~U~R~N~[~a~~________________~~ _ _ _ ~_~S~E~N~S~O~R~U~:~5]~~
~
I
\
L.._--.:C~A:!R:..:S::.--.![~I]_____-+,-j-----~t'=--,..I' \
LIGHT13J....
RESET
M
A
~\
-
.....
~~_ _ _---.
'~--4l
....
,7
-
~~
"" ", (
pi
I
[2]
s
L...--="::':--=''-:''':':'::':':'~~----':~~---T--------r~,../\
/
\
E
R
1/- ~~~~~-----~~~~~r-------~
;T
c
o
RESET
/Ij~\" ... -:.
J,..:.:.:::.=.=:...:..-.----.r=-II~ l~l~ \ '\
T
__ LEFT TURN
-
__ CARS
r
[2]
_~~_.L....-"""'" LIGHT[e]
- .J'
-~
h
-\-\l/ -
L
T MAX
..
TMIN
U
N
I
T
.
~ " 1\ \ \
!
~ I \\ \ \
CYCLETIME{TTOIlv! "
INITIALMODE
..
- I
.....
-
[3J
\
/ 1\
/
I
/
OUTSIDELIGHT [I:ltJ 1/
__ CARS
'\
/
j
+
\
\
R
S
E
L '(2]
L
,.
[I]
"
~,
\ "
J~
\
\
LIGHT
\
\
l
-rl
~
[91 COUNTER 3
~~
L[a]
L[4]
....
/('1
~'\_~_"'.I
~ .!ENSOR
0I :If2
_,
~
~~~~~~~~~~~--~-rr-----------1t--~~~l--~
LEFT TURN [3]
J
__
~
I
l
RESET
CARS r4]
~~~~c~
-
T
[12]
_---~*:----:!-L----...
II
('
...
/ I __ ~
~ __SENSOR
(16: 20]
____~~________________~~+
~~
~~~~~~~
I
~_~L~E~F~T~T~U~R~N~r[~~____________________--rIL~
--~~
"
.
LIGHT
~--
~C-0-UN-T-E-R-4~
Figure 6-Second level of description
C
T
I
,,,,,-~..-L_T_L_ _ _ _ _ _ _~~~~NER
\
\
E
\\
'"
\
\
"
COUNTER~2----'
- II ~JI \ '\
N LOC
~:"':""'----I~...r
"," 1'\ \ \ \.
___ ~ CONTROL
T
_IJ~, 1\\ \ \ ' \
UNIT
R coc
o
I
N
T
_ SENSOR [&:10",
o
N
SODAS and a Methodology for System Design
SODAS Description
Comments
SODAS begin
input Boolean array sensor [1:20];
input Boolean array outsidelight [1:12];
input Boolean loc, coc, reset;
input integer tmax, tmin, cyc1etime,
initialmode;
output Boolean array light [1:12];
output Boolean array leftturn [1:4];
output integer array cars [1:4];
Boolean array L[1:4]
subsystem counter
declaration of
inputs, outputs,
and interconnectors for
the traffic
control module
-- component declaration
input Boolean array sensor [1:5];
input Boolean reset, light;
output Boolean ltl, leftturn;
)
output integer cars
ltl ~. sensor; ltl ~. reset;
leftturn~. sensor; leftturn ~. reset;
}
cars ~. sensor; cars ~. reset
SFD begin
iUPut:BOOlean array sensor [1:5J;
input Boolean reset, light;
Note #1
output Boolean ltl, leftturn;
output integer cars;
integer i, j ;
Boolean lastleftlight;
1a: time begin
if reset then
begin
leftturn ~ false;
ltl ~ false;
cars ~ 0;
end;
for i~1,2 do if sensor [i] then
--cars ~ Cars+ 1;
for i~3,4 do if sensor [i] then
--cars ~ Cars- 1;
if sensor [5] then leftturn ~ ltl ~~;
if leftturn A lastleftlight then
begin
---leftturn ~ false;
cars ~cars - 1;
end;
lastleftlight ~ light; go ~ la;
end of time block;
end SFD ALGOL description
declaration of
subsystem inputs
and outputs
declaration of
immediate
dependencfes
updates count
of cars waiting
in each leg,
indicates if
left-turn lane
exists and
stores current
values of leftturn lights
J
Note #1: This redeclaration of inputs and outputs allows the sublanguage
compiler to operate independently of the SODAS compiler. In the future
this cedundancy will be eliminated.
Figure 7-S0DAS description of traffic control module
at level two
463
464
Fall Joint Computer Conference, 1967
SODAS Description
subsystem counter
sensor [lJ ~ sensor [lJ A
sensor [2] ~ sensor [2] A
sensor [3] ~ sensor [3J A
sensor [4] ~ sensor [4] A
sensor [5] ~ sensor [5] A
reset ~ reset A light ~ light [3] A
1t1 -7 L[l] " 1eftturn -71eftturn [1] A
cars -7 cars [1];
Corrnnents
counter for leg 1 reference to com( ponent defined above
specification of
connActions to
interconnectors
subsystem counter
sensor [1] ~ sensor [6] "
sensor [2] ~ sensor [7] A
sensor [3J ~ sensor [8J A
sensor [4] ~ sensor [9] "
sensor [5] ~ sensor [10] "
reset ~ reset" light ~ light [6] A
1t1 -7L[2J " 1eftturn -71eftturn [2J "
cars -7 cars [2] ;
counter for leg 2
subsystem counter
sensor [lJ ~ sensor [llJ A
sensor [2] ~ sensor [12J A
sensor [3J ~ sensor [13J A
sensor [4J ~ sensor [14] A
sensor [5] ~ sensor [15] A
reset ~ reset" light ~ light [9] "
1t1 -7L[3] " 1eftturn -71eftturn [3J "
cars -7 cars [3]
counter for leg 3
subsystem counter
sensor [1] ~ sensor [16] "
sensor [2] ~ sensor [17] A
sensor [3] ~ sensor [18] A
sensor [4] ~ sensor [19] A
sensor [5] ~ sensor [20] A
reset ~ reset" light ~ light [12] A
1t1 -7L[4] " 1eftturn -71eftturn [4] "
cars -7 cars [4] ;
counter for leg 4
SODAS and a Methodology for System Design
SODAS Description
subsystem
Comments
-- joiner
declaration of:
-- inputs
- outputs
input Boolean array L[I:4];
output Boolean ltl
L[l] <-L[l] A L2] <-L[2] A L[3] <-L[3] A
L[4] <- L[4] " ltl ~ ltl
ltl
~
-- connections
L
-- immediate
dependencies
BOOLE begin
input L[I:4];
element ltl;
gate ltl ~ £E inputs L[l], L[2],
L[3], L[4];
outputs ltl;
end BOOLE description of joiner;
subsystem
input Boolean array outside light [1:12];
input integer array cars [1:4];
input Boolean loc, coc, reset, ltl;
input integer tmax, tmin, ttot, initialmode;
output Boolean array light [1:12]
outsidelight[ l]~utsidelight[ l]Alight[ l]~light[
outsidelight[ 2]~utsidelight[ 2]Alight[ 2]~light[
outsidelight[ 3]~utsidelight[ 3]Alight[ 3]~light[
outsidelight[ 4]~utsidelight[ 4]Alight[ 4]~light[
outsidelight[ 5]~utsidelight[ 5]Alight[ 5]~light[
outsidelight[ 6]~utsidelight[ 6]Alight[ 6]~ight[
outsidelight[ 7]~utsidelight[ 7]Alight[ 7]~light[
outsidelight[ 8]~utsidelight[ 8]Alight[ 8]~ight[
outsidelight[ 9]~utsidelight[ 9]Alight[ 9]~ight[
BOOLE
description
of "or"
gate
-- control unit
}
input declarations
output declaration
1]A
2]A
3]A
4]A
5]A
6]A
connections
7]A
8]A
to inter9]A
outsidelight[IO]~utsidelight[IO]Alight[IO]~ight[IO]A
outsidelight[II]~utsidelight[II]Alight[II]-iight[ll]A
('onnectors
outsidelight[12]~utsidelight[12]Alight[12]~light[12]A
IOC~oCAcoc~ocAreset~esetAltl~tlA
tmax~ma~tmin~minAttot~ycletimeA
initialmode~nitialmodeAcars[I]~ars[l]A
cars[2]~ars[2]Acars[3]~ars[3]Acars[4]~ars[4]
light
light
light
light
~
~
~
~
reset; light ~ lOCi light ~ coc;
outsidelight; light ~ ltl;
tmax; light ~ tmin; light ~ cycle time;
initialmode; li8~t ~ cars
declaration
of immediate
) dependencies
465
466
Fall Joint Computer Conference, 1967
COnmtents
SODAS Description
SFD begin
comment control unit subsystem;
input Boolean array outsidelight [1:12];
input Boolean loc, coc, reset, ltl;
input integer array cars [1:4];
input integer tmax, tmin, ttot, initialmode;
output Boolean array light [1:12];
integer mode, tim, ctmax, ctmin, cttot;
real factor;
control unit
now has more
inputs and
fewer internal
variables
integer procedure newmode;
begin
integer i, high, nscars, ewcars, tcars;
nscars~ars[l] + cars[3];
ewcars~ars[2] + cars[4];
tcars~wcars + nscars;
if tcars=O then tcars~;
if -. ltl then-begin
selects new
high~;
for i~,2,3,4 do
--if i -, = mode 1\ (cars [i]>O V loc) then
begin
if cars [i]>high then
begin
--high~ars[i];
mode to maximize
the number of
cars allowed
newmode~i;
end;
end-;-
to move
factor~igh/tcars;
end else
"be"ginif
-if
-if
--
mode -. =51\mode -. =71\ewcars) then
- - ---begin newmode~; factor~scars7tcars;end else
begin newmode~; factor~wcars/tcars;end;----
:~:;Of
J
new mode procedure;
integer procedure cycletime;
if mode = 5 V mode = 7 then cycle time
else if -. loc then cycletime ~ tmax
else cycletime ~ factor*cttot; .
~
tmin
}
determines the
time to be spent
in the new mode
SODAS and a Methodology for System Design
SODAS Description
procedure initia1izecontro11er;
begin
integer i;
for i~ step 1 until 12 do 1ight[i]~a1se;
mode ~ initia1mode;
tim~max;
factor~;
ctmax~max;
cttot~
ctmin~min;
if loc then ttot else 1800;
1t1~aiSe;
Comments
initializes
internal
variables
and outputs
end initialization of the controller;
procedure set1ights (a,b); Boolean array a; integer b;
begin
integer i;
for i~l step 1 until 12 do a[i]~a1se;
Ub=5 then a[ 1}-a[ 6]~[ 7J~[12]~rue else
sets traffic
if b:6 thenar 4]~[ 5]~[10]~[11]~rue else
if b=7 then a[ 4]~[ 3]~[10]~[ 9]~rue else
lights, given
if b:8 then a[ 1]~[ 2]~[ 7]~[ 8]~ else
if b=2 then a[ 1]~[ 4]~[ 5]~[ 6]~ else
desired mode
if b=4 then a[ 7]~[10]~[11]~[12]~ else
if b=l then a[ 1]~[10]~[ 2]~[ 3]~ else
if b=3 then a[ 4]~[ 7]~[ 8]~[ 9]~rue;-end set1ights;
continue:
time begin
if reset then initia1izecontro11er;
if G.oc thenbegi'iiinteger i;
for i~ step 1 until 12 do
--ligh.t [i] ~ outsidelight[i];
~ .!£ done;
end;
if loc ·then cttot ~ttot else cttot ~ 1800;
tim ~ tim +1;
if tim>ctmax then
begin
-tim ~ 1;
mode ~ newmode;
ctmax ~ cyc1etime;
set1ights (light, mode):
end;
done: ~ ~ continue;
end of time block;
end of SFD ALGOL description of control unit
end SODAS description of traffic control module
this is the
same control
algorithm
discussed in
Figure
except cars
is now an
input and not
an internal
variable
467
468
Fall Joint Computer Conference, 1967
LEFTTURN [I]
SENSOR
CARS [I
LIGHT [3J
RESET
LEG I COUNTER AT SECOND LEVEL OF DESCRIPTION
BINARY
8.uT(I:~ SPECIAL ~NO:q1 DECODER _
.......I - - - - - + - _ + _ _ _T_O_
- ..
-,
~
DECIMAL
\ CaJNTER
\
CONVERTER
\
\
-
-
&......r-----'
. . . LEFTTURN II]
-~-----~-~------------~'I~----~I
LIGHT
SENSOR [1:4]
~-+------=---=
MODSENSOR
C31MEMORY
UNIT
RESET
Figure 8-Leg 1 counter at third level of description
SODAS and a Methodology for System Design
SENSOR
469
----------------~~----------~r-----------~
J
LTL
RESET------~----------~--------~--~~~
MODSENSOR
NOT
RESET
LIGHT
LEFTTURN
o
Figure 9-Logic diagram for memory unit
the reader should note the strong correspondence between block diagrams and the structure of the SODAS
program.
We consider t!1is correspondence one of the most
important features of SODAS and its sub-language
BOOLE. There is a simple (mechanical) process to go
from a block diagram to a SODAS description of a system, or from a logic diagram to a BOOLE description
of a network. SODAS does not restrict or influence the
designer's way of thinking-except possibly to encourage him to be more precise in his definitions.
CONCLUSIONS
We have presented a methodology for systems design, and a language that we feel is a significant aid
to systems designers. The aid that SODAS provides is
probably best indicated by the phrase Structure Oriented Description And Simulation. SODAS is unique in
its ability to describe systems as structures of components that operate in parallel. It is also unique in its
ability to simulate such parallel structures correctly. We
feel that these two features are almost indispensable in a
software system to aid in the systems design process.
As evidence we offer the example of the traffic control
module; although the system is a small and simple one
by today's standards, SODAS appears to be a substantial aid to the design and description of the example.
Interested readers may wish to compare it with the
description of student solutions to the same problem. 9
As an example of one of the incidental benefits of
such a system, consider the problem of grading students (or evaluating the work of members of a pro-
fessional design team). In either situation it is extremely
difficult to evaluate the work of the individual team
members when part of the system fails or is not completed. It is extremely difficult to determine just who
is at fault, and, more important, to evaluate the work
of the remaining team members. With SODAS, the
specification of part of a system can be substituted for
the actual design in determining if the remainder of the
system functions correctly. Further, since there are
precise and testable specifications, it is possible to determine which components do not meet those specifications. It appears to us that this will be a valuable tool
for the managers of system design projects.
Our work on the example has indicated that the use
of SODAS forces a dis<;ipline upon the system designer
that could greatly improve the quality of his work and
reduce the time needed to complete a project. We have
found that this discipline carries over to design problems in which, for one reason or another, SODAS is
not used (e.g., the design of the SODAS system itself).
REFERENCES
D L PARNAS
Sequential equivalellls of parallel processes
Center for the Study of Information Processing Carnegie
Institute of Technology Pittsburgh Pennsylvania
2
N WIRTH H WEBER
Euler: A generalization of A LGOL and its formal definition
Part I CACM 9 pp 13-23 January 1966
3
Ibid
CS 20 Technical Report Computer Science Department
Stanford University Stanford California
470
Fall Joint Computer Conference, 1967
SENSOR
[J] ---...-----4t---_
I.XJJ--~
SENSOR
00
"--~
PI
'---~
PO
1------1...
P2
----~--~--~
SENSOR [3] - - - 1_ _ _- , - - - - - - . - - - - - - . . . . - - ,
M3 MO
MI
M2
P2
MI
ADDTWO
ADDONE
M3
PI
~P2
~ ~MO
MO
SUBTWO
'PO
P2
M3
SUBONE
:~
SUBTHREE~M3
PO
--- ~PO
MI
Figure lO-Decoder
M2
SODAS and a Methodology for System Design
x
471
y
NOTG
G
u
F
V
NOTF
w
u
E
V
NOTE
w
u
'v
NOTD
0
w
u
V
NOTC
C
w
u
w
ADDTWO
B
V
V
u
w
SUBTWO
AADDI
ADDTWO
ADDTWO
NOTS
NOTA
A
ADDONE
SUBONE
Figure Il-Gaiting for special counter
472
Fall Joint Computer Conference, 1967
NOTG
X
GT
YG
XG
Y
T
YF
XF
Y
T
X
OT
T
Y
CT
XO
y
T
'YC
XC
Y
T
VB
XB
Y
T
JE
0
JO
C
JC
B
JB
NOTA
X
Y
E
NOTB
X
AT
JF
NOTE
NOTC
X
AT
F
NOTD
X
BT
JG
NOTF
X
FT
G
YA
XA
T
Figure 12-Memory for special counter
A
JA
SODAS and a Methodology for System Design
Comments
SODAS Description
- memory unit
subsystem
input Boolean sensor. light, reset;
output Boolean ltl, leftturn, modsensor
deClaration of
) inputs and outputs
sensor +-sensor [5]" light +-.light [3]"
reset +- reset A ltl --) ltl "
leftturn --) left turn [1] A
modsensor --)modsensor
declaration of
} interconnections
ltl ~ reset;
leftturn ~ reset;
ltl ~ sensor; leftturn
modsensor ~ sensor;
modsensor ~ reset
~
sensor;
BOOLE begin
input sensor, light, reset;
element notreset, ga, gb, jk, jl, ta, tb,
L[I:3], ltl, leftturn~ notl, modsensor;
gate notreset ~ ~ inputs resets;
gate ga ~ and inputs n6treset, light;
gate ga ~ £E inputs sensor, leftturn;
gate modsensor ~ and inputs ga, L3, notreset;
gate ta ~.2! inputs sensor, Ll;
gate tb ~ £! inputs jl, L3;
gate ltl ~ and inputs ta, notreset;
gate leftturn ~ and inputs tb, notreset;
gate jl ~ and inputs sensor, notl;
gate not.l ~ ~ inputs L3;
gate kl ~£! inputs modsensor, reset;
flip-flop Ll ~ ~ inputs sensor, reset;
flip-flop L2 ~ ~ inputs jl, kl;
flip-flop L3 ~ ~ inputs gb;
outputs ltl, leftturn, modsensor;
end BOOLE description of memory unit;
Figure 13-Boole description memory unit
declaration of
immediate
dependencies
J
Note =11=1
declarations of
circuit elements
and their
interconnections
Note =11=1
473
474
4
Fall Joint Computer Conference, 1967
P NAUR (ed)
Report on the algorithmic language ALGOL 60 (revised)
CACM 6 pp 1-17 January 1963
5 DE KNUTH J L McNELY
SOL-A symbolic language for general purpose systems
simulation
IEEE Transactions on Electronic Computers August
1964
D E KNUTH J L McNELY
A formal definition of SOL
IEEE Transactions on Electronic Computers August
1964
6 D L PARNAS L C RICHARDSON W H KOHL
Preliminary version-an introduction to Boole-66
. Unpublished manual available from Computation Center Carnegie Institute of Technology
7 D L PARNAS
A language for describin$? the functions of synchronous
systems
Comm· ACM February 1966
8
J FIERST (ed)
ALGOL 20 language manual
Computation Center . Carnegie Institute of Technology
Pittsburgh Pennsylvariia
9 J C STRAUSS D L PARNAS Y WALLACH
R W SNELSIRE
A design emphasis problem solving experience
Department of Electrical Engineering Carnegie Institute
of Technology
10 IBM Corporation White Plains New York Introduction to General Purpose Systems Simulator III
11 H M MARKOWITZ B HAUSNER
H W KARR
SIMSCRIPT a simulation programming language
Prentice Hall Inc Englewood Cliffs New Jersey
1963
12 0 J DAHL K NYGAARD
SIMULA-An ALGOL based simulation language
Comm ACM pp 670-678 September 1966
Requirements for a shared data processing
system for hospitals
by JOHN P. BODKIN
Minnesota Hospital Service Association
St. Paul, Minnesota
INTRODUCTION
The Service to Minnesota Hospitals program is one in
which Minnesota Blue Cross, together with participating hospitals, have joined in making available the best
possible EDP services to hospitals in this area.
Consideration of this program began in 1963 when
a feasibility study commenced in which Blue Cross and
four hospitals in Minneapolis participated with approvals
from the Twin City Hospital Association and the Minnesota Hospital Association. This study was concluded
in mid-1964 and the results were incorporated in the
publication entitled "Cooperative EDP for Minnesota
Hospitals" released to all hospitals in the State in September, 1964. The conclusions reached by the Study
Committee were that a cooperative EDP system for
Minnesota hospitals in which centralized computer
facilities would be installed at Minnesota Blue Cross is
definitely feasible and would result in significant benefits to the hospitals served. It was further recommended
that the cooperative program should result in the eventual installation of an integrated system of EDP services
for all feasible applications in hospitals but that the
initial applications to be developed should be referred
to as "Stage I" and should consist of:
• Patient Accounting.
• Payroll and Personnel Record Accounting.
(Employee Information System)
• Inventory Control and Purchasing.
• Accounts Payable Accounting.
• Property Ledger Accounting.
• Preventive Maintenance Scheduling.
• General Ledger Accounting.
The principal advantages and disadvantages of a
cooperative as compared to individual hospital EDP
effort were concluded to be the following.
Advantages
The cooperative approach to EDP provides greater
potential benefits to hospital operation for less cost.
Some of the individual factors which justify this observation are as follows:
1. The combination of equipment and staff under a
cooperative system can perform greater services
due to Greater Capability of Equipment-a cooperative system can afford the computing and
peripheral equipment to most effectively perform
all hospital functions that should benefit from
EDP. Technological obsolescence can be more
effectively coped with as new and better equipment becomes available since there is a broad
base over which to share any replacement costs.
Skilled Systems, programming and operating staff
can be retained. The highest degree of d-ata processing skills can be brought to bear in the development and operation of a cooperative system.
Desirable specialization of. functions can be achieved. Retention of key individuals in small individual systems can become extremely difficult
due to the competition that exists.
A broad base of analysis is made available through
the cumulative hospital experience of numerous
hospitals.
Contributions in Consultation as well as direct
effort from outside sources can be very significant particularly in a cooperative approach.
These outside contacts include equipment manufacturers, consultants, other hospital and hospitalrelated institutions, etc. These contributions will
be particularly valuable in the development and
realization of long-range systems planning.
More Operating Systems for each hospital will result in a shorter period of time due to the ability
475
476
Fall Joint Computer Conference, 1967
of a relatively large staff to simultaneously plan
for and implement several areas of EDP services.
2. Initial Investment-Under the cooperative approach, the initial investment is substantially reduced since all costs are recovered through monthly service charges that commence only when a
system becomes operational for that hospital.
Elements of this initial investment expense consist of such items as:
Salaries for systems analysis, programming, proect director, training of operating staff, etc.
Equipment Rental for any period of time during
which the computer is on rent and not yet productive (or fully productive).
Construction Costs for a data processing room
including necessary temperature and humidity
control, special electrical power, etc.
Supplies-particularly magnetic storage (tapes or
other type) which are a costly item of initial expense.
3. Supporting Staff-The installation and operation
of an EDP system requires the efforts of a skilled
and well-managed staff. In an individual as well
as in a cooperative system, all these skills must
be procured and retained .. The personnel expense
for this staff is significant. In a cooperative approach, however, the cost per hospital through
the monthly service charges is drastically reduced.
4. Eqlfipment Rental-It is fundamental that potential processing cost per unit is cheaper as the size
of the computer is increased. Therefore, substantial ultimate benefit to participating hospitals due
to the fact that larger, less expensive per unit of
processing equipment is utilized.
Disadvantages
The cooperative approach inherently requires willingness to compromise individual hospital interests
where necessary to achieve the benefits that can be
realized. Some elements of this compromise are:
1. Systems Design-The precise design of operating
systems can be made flexible to include numerous
options which will accommodate the desires of one
or more hospitals. This, however, is not always
economically practical.
2. Planning-Planning for future systems must be
done cooperatively.
3. Priorities-Decisions as to the sequence of applications to be installed as operating systems
will have to be worked out on a basis of the aggregate benefit to all participating hospitals. The
same would be true with respect to selection of
future applications for further research and implementation.
Hospital data processing council
, To coordinate the activities of the EDP program, a
Hospital Data Processing Council has been established.
This Council consists of administrative representation
from each hospital participating in the program. The
purposes of this Council are to receive recommendations
from the Blue Cross staff and to make all final decisions
regarding the characteristics of the systems that are to
be offered.
Participating hospitals
Data processing service by Blue Cross to Minnesota
hospitals commenced in 1955 when the first hospital,
St. Barnabas of Minneapolis, transferred its Payroll
processing to Blue Cross. Since that time, this Payroll
service has consistently increased until currently there
are over 30 hospitals in Minnesota whose payroll is
being processed by Blue Cross. This system has undergone many changes since 1955 and is now a completely
computerized operation. This service handles the payroll
for approximately 22,500 hospital employees. A second
service that was added was Di~charged Accounts Receivable processing in 1963.
The above services of Payroll and Discharged Accounts Receivable were not planned on a form allyorganized basis with hospitals .and will be eventually
merged into the. cooperative program otherwise described. Those hospitals which have to date elected to
participate in the cooperative EDP program and whose
activities are governed by the Hospital Data Processing
Council are as follows.
Minneapolis
Abbott Hospital
Lutheran Deaconess Hospital
Eitel Hospital
Mount Sinai Hospital
Northwestern Hospital
St. Barnabas Hospital
The Swedish Hospital
The University of Minnesota Hospitals
St. Paul
St. John's Hospital
St. Cloud
St. Cloud Hospital
By July, 1967, the Patient Accounting System will
be installed in all participating hospitals. All other Stage
I Systems will either be installed, or available for installation, by the end of 1967.
Requirements for Shared Data Processing System for Hospitals
Financial policies
Charges by Blue Cross for hospitals serviced under
the cooperative EDP program are based on actual costs
of operation, including amortization of necessary development expenses. Cost accounting methods are used
to assure that hospitals are not charged for the services
beyond the actual costs of operation, nor will the operation be subsidized by income from Blue Cross subscriber
payments.
Computer center equipment
The computer center at Blue Cross currently consists of two Honeywell Series 200 computers. One computer, an H-200, is primarily a communication processor and is connected by communication lines to each
hospital.
As of May, 1967, the configuration of this system
was as follows:
H-200 Central Processor-28K (characters) memory.
I-Tape Control Unit.
2-20kc Magnetic Tape Drives.
2-High Speed Random Access Drums (2.6
million characters of storage-each drum).
1-High-speed Printer.
I-Console Printer.
This system is the interface between the hospitals and
the accounting systems that are run on another computer.
All input for the various accounting systems is prepared in the hospital and transmitted via communication lines to this system. Batch total reports, error reports, census reports, and other low volume reports are
transmitted back to the hospital via this computer.
There is also a once a day update of the .random
access drum, where summary bills for in-hospital patients are stored. Summary bills and other patient data
are printed in the hospital on demand.
In addition to handling traffic to and from the hospitals, the system also drives a high-speed printer utilizing
print image tapes from other processors.
At the present time, all devices connected to this
system operate at their maximum speed, simultaneously.
We do not anticipate a noticeable slowdown of individual peripheral devices until after thirty (30) communication lines have been connected to the system.
This slowdown would then only occur in a worst-case
condition.
The other computer used for these accounting systems is a Honeywell 1200 equipped as follows:
2-Tape Control Units.
4--44kc Magnetic Tape Drives.
477
4-67kc Magnetic Tape Drives.
1-High-speed printer.
1-High-speed card reader.
I-Console Printer.
All processing for the accounting systems is accomplished on this system. Quite frequently this system
operates in the foreground/background mode. In other
words, card-to-tape, and tape-to-printer operations occur simultaneously with, but independent of, other processing.
As additional hospitals and/or services are added
to the cooperative program beyond the capacities of
the installed units, the Series 200, as well as equipment off((red by other manufacturers, offers built-in
growth potential so that all types of services desired
by participating hospitals can actually be performed by
the computer center.
Mechanisms for adding capacity for the present
Series 200 systems consist of the following:
• Additional Series 200 computers.
• Successively higher speed central processors which
offer growth without program translation thm
higher speed execution of instructions, and increased capability in the area of multi-program~
ming.
• Additional internal memory. Maximum memory
size of a single Series 200 processor is over one
(1) million characters.
• Random access storage. Several types of random
access devices are available.
Communications and terminal units
All accounting systems are on-line systems requiring
data communications lines and terminal keying and
printing units to be located in the hospital. Specific information relative to these devices is as follows.
ACS-35
This is a combination keying, printing and paper tape
reading/punching device provided by the Northwestern
Bell Telephone Co. and manufactured by the Teletype
Corporation. It is directly connected to the H-200 communication computer via communication lines.
Basically, this device is an ASR-35. It has been modified to include a second paper tape reader and a stepping
circuit. The purpose of this modification was to provide
format control when keying data for the accounting
systems. This device operates at a speed of ten (10)
characters per second.
Friden add punch
This is a free-standing paper tape punching device
operated by a ten-digit keyboard for use in punching
478
Fall Joint Computer Conference, 1967
numeric only data. The device includes a check digit
verifier which will automatically detect errors in keying
when they occur, and before they are recorded in the
punched paper tape. The paper tape created by this
device is transmitted to the computer center utilizing
the ACS-35.
The above units are the initial units specified for
operation with the various accounting systems. Improvements will be made in this area from time to time as
the situation warrants it. We expect these changes will
be in the following areas:
• High-speed transmission of paper tape.
• Faster character printing capability.
• Line Printers.
• Cathode ray tubes for use as input and temporary
display devices.
What systems shall a cooperative group
implement first?
In any cooperative venture into Hospital Data Processing, several factors must be taken into consideration
before a cooperative group can make a decision as to
what area of the hospital is to receive the benefits of
data processing first. Some of the factors are:
Ohjectives of the cooperative group
Long-range and short-range objectives of the cooperative group must be outlined. Following are some
questions that should be answered.
• Do we desire to develop or acquire a standard
Hospital Information System that would be installed in all hospitals, or, on the other hand, do
we merely wish to share a central computer and
develop our own systems, designed to an individual hospital's specifications?
• To what extent do we desire standardization of
systems and procedures?
• To what extent do we wish to share or compare
information concerning patients, employees, supplies, services, etc.?
• What hospitals in the community or the state will
these services be offered to, and what will be the
method of input-On-line or off-line?
Source and amount of funds available
Are they:
• A Government or private grant?
• Hospital supplied?
• A loan?
• Must they be repaid or merely accounted for?
Data processing staff
• What are their skills and backgrounds?
• What are their abilities and knowledge of the task
at hand in the areas of:
Systems analysis?
Systems design?
Computer and related hardware?
Computer software?
Hospitals?
Equipment suppliers
• What kind and how much support are the equipment suppliers willing to give?
• What application packages or capabilities, that will
assist you in attaining your objectives, do they
have or will commit themselves to supplying?
Computer hardware and software
• Is the hardware and software, that will enable
you to achieve your systems objectives, available on the market?
• Can it be delivered in time to meet your implementtation plan?
• Can you afford it?
Accounting systems first in Minnesota
After taking all of the above factors, and many others,
into consideration, the Study Committee concluded that
a cooperative EDP System for Minnesota hospitals
utilizing a centralized computer facility was definitely
feasible, desirable, and would result in significant benefits to hospitals served. This cooperative system would
provide EDP services for substantially less cost than
would be incurred for comparable services if hospitals
individually installed computers. Tl).e services rendered
through cooperative data processing ·would tend to be
superior to services which could be rendered by individual hospital computers due to greater computing ,
capacity and the potential for economical growth.
The recruiting and retention of a skilled systems,
programming, and operating staff would be easier and
more economical on a group basis. Substantial duplication of effort in research (system analysis), systems
design, and programming activities would be avoided
as compared to several hospitals doing these things
separately.
It was determined that there are many types of data
processing services whic4 could be provided hospitals
by such a cooperative system. Some of the potential
functions were currently being performed in certain
hospitals, such as patient accounting, inventory controL
payroll, etc. There are many other potential applications, however that, for the most part, have not as yet
been defined, and developed.
There is great interest today in EDP as an aid to the
clinical practice of medicine. This could include, for
Requirements for Shared Data Processing System for Hospitals
example, the handling by electronic means of all or
much of the information in the patient's chart. There
can be no question that once clinical applications are
perfected and adopted by the medical and professional
hospital staffs, they will be of substantial benefits to
health care.
There is, however, widespread consensus that hospitals must initially install those EDP applications that
are practical, proven, easily defined, and understood,
and do not add significant cost to patient care. For these
reasons, we chose to implement those accounting applications previously referred to as "Stage I Systems."
In retrospect, both the member hospitals and Minnesota Hospital Service Association feel that this was a
very sound decision. We feel that the experience gained
by the data processing staff and the administration of
the hospitals will be invaluable in the. development of
future systems or extensions and improvement of the
initial effort.
Future systems development
During the remainder of 1967, a detailed systems
analysis will be made in two areas of the hospital-the
Clinical Laboratory and the Pharmacy.
In a recently completed survey, four major problem
areas in the Laboratory were identified that have potential EDP solutions. They are:
1. Test ordering-Can be made more accurate and
much faster. Can be used to prepare lab worksheet and specimen collection schedule. Should
include a better, more efficient means of specimen
identification. A by-product of test ordering would
be automatic preparation of charge data for the
Patient Accounting System.
2. Test Reporting-Can be faster. Can have a better
form a display than "shingles," and can be made
available for instant display in areas such as the
Doctors' Lounge, lab, or nursing station.
3. Quality Control-Is presently very time-cqnsuming and subject to manual inaccuracies. The personnel interviewed would like improved quality
control procedures as part of any new system.
4. On-Line Monitoring - Automated equipment,
which most of the laboratories have installed or
ordered, allows many more tests to be performed.
Results must still be monitored and recorded. If
these devices were on-line to a computer, monitoring and recording would be automatic.
Characteristics of such a laboratory system would be
as follows.
Laboratory requisitions would be entered into the system from the physician's order by the nursing staff, or
479
directly by the physician. As a result of this action, the
system would produce the following:
1. Specimen collection schedules.
2. Specimen labels.
3. Laboratory work schedule.
4. A charge to be posted to the patient's account.
5. Updated file of ordered but not completed tests.
When specimens are collected and delivered to the
laboratory, they will have the following positive identification:
1. Accession number.
2. Patient number and/or name.
3. Test number and/or name.
4. Date.
5. Time required.
It would be desirable if a portion of the label were
in machine-readable format if the test is to be run on
automated test equipment.
When a series of tests are set up, either manually or
on automatic testing equipment, basically the same
procedure is used-the test is calibrated by running a
control specimen or a series of controls. Controls may
be interspersed to verify continued accuracy· of test results. The verification of control results should be performed by the computer, either manual entry of raw
results or automatic entry via on-line monitoring.
During a run with an on-line automatic testing machine, results may be adjusted by the computer for
drift and specimen interaction as detected by control
specimen tests. As tests are completed and filed in the
central computer, a report, together with previous tests
for the patient, would be made available in the laboratory, the nursing station, and any other location required by the medical staff.
With all test results available on-line, it will be possible to recall a patient profile at any time. Display of
the profile can be a permanent hard copy printed by
the character printer or temporary display on the cathode ray tube. The profile would display the results
of all completed tests and, in addition, tests that have
been ordered but not completed.
Completed tests will be automatically audited against
tests scheduled; an exception reporting system for the
laboratory will assure that all ordered collections have
been made and that the tests have, in fact, been completed. We feel that the benefits of such a system would
be:
1. Reduced clerical effort in the laboratory.
2. Reduced clerical effort in the nursing station.
3. Increased accuracy in test ordering.
4. Better quality control.
5. Improved reporting and display of results.
6. Lost or misplaced test results will be detected and
reported.
480
Fall Joint Computer Conference, 1967
7. Fewer medical technologists will be able to perform more tests.
8. The ability to perform admission screening and
multi-testing economically and rapidly benefits
the laboratory, the medical staff, and th~patient.
Pharmacy system
Listed below are some of the reasons that we feel
that data processing can playa major role in the Pharmacy and medication administration.
• Studies have shown that 30-40% of physicians'
orders are for medications.
• Much of the pharmacist's time is spent in clerical
work---:<>rdering, stocking, taking inventory, typing
prescription labels.
• Medication charges lack accuracy because of
clerical work involved.
• Errors due to poor communication and control
directly affect patient care.
• A large amount of nursing time is spent on paper
work associated with medications.
Our present concepts are that a Pharmacy System
would be developed in three stages. These three stages,
as well as the benefits to be derived from each, are
listed below.
Stage one
Development of a computer-based inventory and
formulary catalogue.
Benefits:
• Reduced clerical effort in the pharmacy.
• Improved purchasing including group buying.
• Formulary listing by therapeutic usage makes
generic dispensing feasible.
• Drug location index assists inventory and order
filling.
Stage ·two
Integration with Patient Accounting.
Benefits:
• Changes based upon drug cost to both inpatient
and outpatient prescriptions.
• Patient drug profiles may be prepared off-line for
medical records, probably for medication administration.
• Statistics including drug usage and adverse reactions may be a by-product.
Operating reports may be prepared automatically.
Stage three
On-line, real-time medication administration system.
Benefits:
• On-line drug profiles available in pharmacy, at
any other locations.
• On-line medication schedules.
• Automatic stop or hold orders.
• Computer p.reparation of prescription labels.
Hardware requirements
If it is determined that it is feasible to implement the
above concepts in total, we feel that a real-time computer with the following-capabilities will be a requirement in the hospital:
1. Communication switching-intrahospital and hospital to the computer center.
2. Analog digital capabilites.
3. Scientific computing capabilites.
4. In-hospital real-time computing capabilites.
5. High-speed random access for storage of programs
and small data files.
6. The system must be capable of communicating
with a mutiplicity of terminal devices such as
cathode ray tubes, teletype printers, and the central computer center.
The system must be capable of being expanded so
that other departments in the hospital, such as admitting,
dietary, X-ray, may also be served. The computer center
hardware must also be upgraded so that patient files
are on-line and available at all times.
Use of displays with packaged statistical programs
by W. J. DIXON
Univer~'ity
of California
Los Angeles, California
During the past few years there has been a great
increase in the use of packaged statistical programs.
These programs are prepared in a general form. For
example, a regression program will allow the user to
specify:
the number of variables being introduced as a data
set
the number of cases
the choice from this data set of the dependent variable
the choice of some subset of the input variables to be
the independent variables
the type of input (cards vs. tapes, etc.)
the transformation of any variable in the data set
the construction of new variables for some stated
function of the input variables
the stepwise computation of regression function
the priority with which variables may be considered
for introduction into the regression equation
the plotting of residuals vs. various input variables.
The output provided includes means, standard de~
viation, correlation, and at each step of the regr~ssion
process regression coefficients, partial correlation, and
an analysis of variance table for the regression.
At the end of the process a list of residuals and the
plots mentioned above are provided.
A regression program of this generality will enable
a user to compute a wide variety of problems, as well
as the standard regression problem, e.g., analysis of
variance, contrasts either orthogonal or dependent, analysis of covariance, discrimination, etc.
A library of statistical programs such as the BMD
series developed· at UCLA gives the user a selection
of several different regression packages as well as
a variety of data screening, analysis of variance, multivariate analysis and other statistical procedures, all
providing a considerable degree of flexibility to cover
a wide variety of problems.
.
In biomedical applications, as well as in other
fields, studies with large amounts of data are analyzed
sequentially. Various analyses are carried out to choose
among various possible dependent. or outcome variables and to relate these variables to the many independent variables. Analyses are made to screen the
data for accuracy, including search for outliers, etc.
The data are examined for linearity, homogeneous covariance matrices, etc. The investigator can be assisted
by the computer during this phase, but he must still
participate actively in directing the process.
If these programs are used at a computing facility
providing batch processing and providing these programs in its internal program library the successive
steps in the analysis can be accomplished by submitting a call for a specific program along with a specification of the program parameters and a data deck
or tape. Each stage may be submitted separately and
the statistician will usually adjust later steps in the
analysis from the outcome of earlier computations. The
same program, or several different programs, may be
used. It may be possible also to store the data in the
computer and call it from the file whenever the next
analysis is desired. The return of each portion of
the analysis may be a matter of hours, perhaps in some
cases, a matter of minutes. The data analyst may designate different dependent variables or modify the
choice or priorities of the dependent variables, transform the variables, include or exclude cases, or more
generally he may choose the definitions of strata.
This analytical search is in some ·ways analogous
to the stepwise regression itself. The art of data analysis has not yet matured to the point where the investigator can specify in advance the algorithms which
might be brought to play in this analytical process
much less to specify their sequence.
The development of. interactive computer systems
will greatly enhance the researcher's capacity to ana481
482
Fall Joint Computer Conference, 1967
lyze his data. In such systems summary information
can be supplied to the user at a console and he can
supply commands to the computer from his console.
The investigator may therefore intervene in the strategy
of analysis, indicating that a run with the same program
should be repeated with a specification of new or
modified parameters, etc. Thus, this type of system
reduces the turnaround time for successive stages of
the analysis. Some investigators have found earlier
interactive systems to be too restrictive in their available modes of input and output and would prefer a
capability additional to that of the typewriter console
to provide card input and fast printer output. However, it should be noted that output which requires a
great amount of time to read may as well be provided
off-line. Also, a very large number of ·cards may be
more easily handled at a cen~ral computer.
Computing systems to handle interactive consoles,
as well as providing adequate capacity for executing
large statistical programs, will soon be generally available. So far the statistician has been required to choose
between interactive capacity and capacity to do a
comprehensive analysis. He, of course, requires both
capacities concurrently. He also needs aid in visualizing
the interrelationships of variables and the goodness-offit of various statistical models.
Statistical graphs
Many experts in data analysis have always used
graphical methods to aid their analysis of data. One
often hears directives of these experts to their assistants something like, "go thou and plot your data."
The plots and charts frequently do not survive the
process of report writing and publication, but have
played an important part in the analytical process
itself.
These charts have employed various colors or symbols to identify strata and lines have been drawn,
dotted, dashed and perhaps wiggly. Question marks
annotate extreme values. Regression lines or frequency
contours may be drawn in alternate forms with and
without suspect cases or with and without· doubtful
subgroups. Various forms of graph paper are used and
curves are plotted with standard error regions.
The data analyst who has taken the computer unto
himself may have dropped some of these time consuming graphical procedures in favor of various computer aided analyses of alternate approaches. He still,
however, seeks graphical output from the programs he
uses and still very likely employs some graphical
methods in plotting his next analytical move.
Recently the interactive computing systems have been
introducing television type screens to supply more rapid
output at the user's console. These scopes may also be
equipped with a light pen to be used for communicating signals from the user to the computer. These signals
may be used as commands to steer the course of the
analysis by supplying parameters ,changes in parameters, choice of subroutines and identification of data
points, etc. The light pen is slightly larger than a fountain pen and affects the designation of information on
the screen by sensing the screen regeneration at a particular position.
The users console may have available also a typewriter, instruction keys and perhaps card input, or
more luxuriously such additional input media as paper
tape, magnetic tape, disc packs and film. When the
console is connected with a computing system that has
a well developed operating system, program library
and file service, the user may build effective programs
by virtue_ of having his commands executed within a
reasonable length of time, having available many packaged service and analytical programs as he works at
the console. A few computing facilities are approaching this capacity at the present time. These facilities
provide much of what is needed for effective data
analysis.
A major difference will be the need to operate at a
computer language level at least one step higher than
that required for the· programmer. The statistician will
not in general be able to make sufficiently rapid progress with his analysis if he must do any significant
amount of programming while he is "on-line."
Simple scopes which provide only character displays
can satisfy needs of the programmer but will not provide the graphical needs of the statistician. Scopes are
available which provide plotting capabilities and vector
or line drawing features. When a scope of this type is
coupled with a light pen to provide a simple form of
identification and communication concerning the results
observed on the scope and a function keyboard to
initiate commands to subroutines and to supply parameter values, etc., the hardware capacity is available
for the statistician to construct graphs and to interact
with an analysis in progress in the computer in a
"plotting" or graphical mode.
The next step in providing an operative system for
him is to design the supporting software. The overall
system will need to be serviced at several levels of programming. The following paragraphs indicate some of
the statistician's needs.
Data storage
A basic data file will be assumed to be structured
to an extent that one may arrange the data into a data
matrix whose columns represent variables (i.e., types of
measurements) and whose rows represent individuals
or cases on whom the measurements have been made.
Use of Displays with Packaged Statistical Programs
It is not assumed that every measurement is. available
for every case, but that various types of "missingness"
are either coded in the original data or provided by a
computer program.
Operations on the data file
One or more variables may be selected by name or
number. Operations ·available on· this variable (or on
several variables) include functional transformation by
a function supplied at the console. These new variables
may be added to the data matrix or; if necessary, replace other variables in the data matrix to conserve
storage space. Stratification of cases can be accomplished by forming submatrices based on categorizing
statements involving the data entries for one or more
variables. The above features provide, for example, the
capacity to compute residuals from a regression function based on the same or other observations.· Submatrices or extensions to matrices may be stored as
derived files.
It is frequently desirable to perform a transformation on one or more variables where the functional form
is known but for which not all parameters are either
known or computable. from the given data. One may
wish to examine the effects of the transformation in a
regression or discrimination problem and note the effect on the prime analysis of various selections of the
parameters of the transformation. This calls for a convenient way of providing' a sequence of values to one
or more parameters and to watch at the scope the effect on the plotted outcome of the computations. In
some cases it may be sufficient to display conversion
indicators in numerical form and guide the process accordingly.
Parameter pacing
A simple replacement of the parameter values one
by one at· the console is frequently not sufficient to the
task. A pacing subroutine needs a starting value and
an increment to provide a succession of inputs so that
the progression of events may appear as rapidly at the
scope as they maybe provided by the main computer.
This subroutine also provides an "increase" and "decrease" instruction to accelerate or decelerate pacing
and a backspace instruction to avoid restarting the
parameter search when an optimum point has been
passed.
.
Scope plots
The statistician uses plotting on paper in many ingenious ways to increase his understanding of various
characteristics of the data. A change of scale, e.g., from
arithmetic paper to logarithmic paper or the use of
probit or logit paper for cumulative proportions can be
accomplished on the computer by transformations on
the data.
483
The ability to plot data pairs (x, y) on paper including the use of dots or other characters to represent
strata is directly transferable to the scope. Although
the use of colors for strata is not generally available on
today's computers, the use of motion provides an even
richer visual presentation. If a· particular stratification
merely represents an ordered categorization based on
a third variable the identification of strata may be
viewed as the capacity to introduce a third dimension
to the two cartesian coordinate variables for the plane
face of the scope.
Let us examine for a moment what can be displayed
on the scope. The simplest representation of one variable can be dots along a line or, in two dimensions, a
point in the plane. A second variable can be introduced
in the plane by locating a line segment at x-horizontally
and using a line segment for y (sometimes called a
histogram). A third dimension may be added to a point
(x, y) by changing the dot size or displaying a line
segment whose center is (x, y). The value of a third
variable can be indicated by the length of the line. A
third variable may also be introduced by using a short
line segment of fixed length whose center is positioned
at (x, y) but whose angle of inclination represents a
third variable.
Stereo representations can be provided which give
true stereo with the use of viewing lenses and the impression of stereo by configurations changing shape as
though rotating in space. When regeneration is spaced
in time and applied successively to subgroups of the
points (or symbols; characters, or line segments) attention is drawn successively to each subgroup in turn.
The subgroup designation may be a third variable. Subgroups may be differentially highlighted by the frequency or duration of regeneration. If sufficient system
support can be given to the console scope, line segments may be given either a metronome motion or
rotation whose frequency or speed represents an additional variable. Lengths of line segments may be automatically scaled down from maximum length to give
a length proportional to the third variable. The slope
of a line segment may represent a residual scaled by
the . maximum residual or represent a third variable
scaled to cover its range between 1 and -1. These
facilities can be supplied with relative ease to the
graphical system. The pictorial display may be alter- '
nated with or overlayed by the usual numerical output of the statistical program. The "printed" and pictorial presentation can also be located at different places
on the scope.
+
Background grid
A grid of the usual graph paper type can be easily
provided but since color is not usually available, the
484
Fall Joint Computer Conference, 1967
grid lines should be of lesser intensity than the data
points. A more effective mode for the user is provision of regeneration to the background only at specified
times or on call. The user must be able to specify line
widths and different frequencies of regeneration. For
finer work, provision for second or fifth lines preferably
at a different intensity or width should be provided.
Before giving further details on the specification of
other modes for displaying additional dimensions, we
give examples of the types of variables which one may
wish to display.
'Since each observation of multivariate data on continuous variables is often conceptually visualized as representing a point in higher dimensional space, the
capacity to represent more dimension in the two-dimensional frame is desirable. Categorical data which is
ordered can be treated similarly. Special attention may
be needed for unordered categories. Preliminary analyses may·· provide additional dimension to the plotted
data. If the plotted points are means, the additional
dimension of sample size and standard deviation are
important. If percentages are computed· on categorical
.data, 'the sample size and proportion non-responding
are important, etc.
Case identification
The light pen may be used to identify a point representing a case. This can cause the computation to be
repeated removing this case, showing the resulting
changes in the display. A simple example is the display of two alternate regression lines computed with
and without one or more designated points ( cases) .
Upon identification of a point and specification of a
particular variable, the user can request a histogram
showing the entire distribution of that variable with a
flashing or highlighted location of the identified case
in the distribution.
Program control by light pen
Sequencing of the analysis can be made by light pen
or by function keys. Experience has shown that the
light pen is easier to use because of the appearance of
memory cues and choice alterations on the scope. The
pacing of parameters can also be guided by light pen
from a choice of the pacing parameters themselves.
Selection of strata
The specification of various strata for analysis can
be readily accomplished by calling a selection subroutine
whose descriptors are prepared for the particular study.
Consider for example a tumor registry which has been,
prepared using various codes for age, sex, diagnosis,
treatment, etc. This subroutine can exhibit first these
prime variables. The touch of the light pen to the word
"age" appearing on the screen will c~use the .specific
code forage to appear, perhaps .showing that age is
coded to 5 year age groups. The light pen can be used
to touch the desired age groups and return to the original
list and proceed. In· some cases (depending on which
variable is chosen) a choice tree of several levels may
be specified by a succession of choices determined by
light pen. The computer program constructs a Boolean
selection statement which can be used to operate on
the data file.
It is fairly obvious that the various forms of case or
strata selection can be combined with the various
forms of variable selection, the various forms of graphic
presentation and the various statistical models of analysis to provide a very powerful tool.
The literature holds fairly complete documentation
of the analytical methods available. Systems of data
analysis programs are described by W. J. Dixon as
Chapter 3 in Computers in Biomedical Research edited
by Ralph W.Stacy and Bruce Waxman, Academic
Press, New York, 1965.
Examples of packaged graphics programs developed
thus far using some of the above features are:
1) Simple plot and regression. This program provides data matrix operations including selection and
transformation, provides scatter plots with case removal
or addition with adjusted regression.
2) Stepwise regression with control of selection and
exclusion of variables, transformation, etc.
3) Spectral analysis with series selection, transformation, filter construction and providing spectrum, cospectrum, phase relations, etc.
4) Non-linear regression with specification of function parameters and boundary conditions and control
of iterations.
5) File search with code assisted Boolean specification for constructing subfiles with control of descriptions of subgroups.
MEDATA-a new concept in medical records management*
by CAROLINE HORTON, TATE M. MINCKLER,
and.LEE D. CADY JR.
INTRODUCTION
The potential applications for computers in expediting medical research and improving patient care are
well recognized. However, in a medical environment
full exploitation of the latent powers of available electronic devices depends on one vital factor. That is,
giving the physicians, research scientists, or administrators direct control of the type of information
acquired and stored, how it is related, and the timing
of acquisition and retrieval. From the viewpoint of
these professional users, the paramount goal is to
achieve such direct control without sacrificing the
valuable time and effort required to become experts
in the esoteric art of computer programming and systems operation. This concept of immediate control
was the basis for developing MEDAT A, an amalgamation of techniques which allows the user to
organize, collect, store, and retrieve all types of medical data without resorting to the intricacies of formal
computer science.
Organization of data
The MEDAT A system does not specify the information structure but provides a framework for
processing any structure required for the purposes
of the user. Data are collected routinely on some form
or questionnaire. Compilations such as abstracts in a
library may not use printed forms, but the questions
are implied by words such as Title, Author, Journal,
and Abstract associated with the data.
Data on forms are usually related by headings and
subheadings into a format resembling an outline. In
the MEDAT A system selected typewriter symbols
are used as prefixes to the questions or headings which
*This project was supported in part by the National Aeronautics
and Space Administration Contract No. NSR 44-012-039 from the
Manned Spacecraft Center.
The University ofTexas M.D. Anderson H ospitai and
Tumor Institute , Texas Medical Center,
Houston, Texas.
485
express and preserve the relationships established by
the user. A heading usually represents a broad classification of the questions following it, as illustrated
in Figure 1. Occasionally the heading will be additional information to be retrieved with each question,
as in Figure 2.
$CLIN PATH
ICSC
@Hb:
@WBC: .
@MORPH
*RBC:
*\~BC :
*PLATELETS:
IUA
@pH:
@Sp Gr:
@Alb:
@~11 CRO
*RBC:
*~/BC :
*SACT:
$X-RAY
Figure 1- Sample program tape
When forms are used, the answers can vary from a
rlUmeric quantity to English prose and are frequently
a combination of these. The technique of enclosing
quantitative or coded data in parentheses at the beginning of the answer permits expression of any type
of answer. This gives the physician opportunity for
unrestricted expression and the statistician opportunity to retrieve quantitative data. 12
Methods of data input
A programmed typewriter with an auxiliary paper
tape is the input device. This procedure has several
advantages. Unlimited numbers of characters may be
used for entering data. The transcriber is the secre-
486
Fall Joint Computer Conference, 1967
W HAL E R S H 0 S PIT A L
New Bedford, Massachusetts
MEDICAL SUMMARY
$10
NO:
$NAME:
$DATE:
$PURPOSE OF EXAM:
IPRESENT ILLNESS:
IDIAGNOSIS:
'TREATMENT:
'COMMENTS:
$EXAMINING FACILITY:
affect the appearance of the typed document but will
not affed the storage and retrieval program. When the
specific tape created for the form is used as a control
tape, special headings are copied onto the paper tape
being punched. Figure 2 is an example of a program
tape used for medical summaries showing the outline
headings and the position codes.
The position codes, the question, and the colon are
copied from the control· tape to the new paper tape.
The question and colon are typed on the document. If
data are to be entered, the typewriter programming
codes after the question will cause control to be transferred to the secretary. Data entered through the keyboard will appear on the document and will be
punched into the new paper tape. Quantitative or
coded data are enclosed in parentheses at the beginning of the entry. Any parentheses after the first
character of the data are assumed to be part of the
prose data. Figures 3 and 4 are medical summaries
collected using this procedure.
$PHYSICIAN:
W HAL E R S
H 0 S PIT A L
New Bedford, Hassachusetts
Figure 2 - Program tape for medical summary
"EO I CAL
SU~"1ARY
123"5
tary, who is accustomed to using the information and
is familiar with the notations and spelling. Coding
sheets, which are laborious to prepare and proofread,
are eliminated. The typed copy produced simultaneously with the data tape satisfies the legal requirements for preservation of a document signed by the
physician.
The programmed typewriter is used to define the
hierarchical structure for the questions as well as to
enter the data collected. To enter the format of a new
data collection form into· the system, the questions
in their outline form are typed and simultaneously
punched into a paper tape. This paper tape uniquely
defines the collection form and is used to control the
typewriter and paper tape punch each time data are
collected on this questionnaire. The position of the
question in' the outlin~ format is flagged by preceding
it with one of the selected typewriter symbols. Questions may be grouped in subdivisions to nine levels.
The typewriter characters selected to relate these
subdivisions are referred to as position codes. These
codes are $, #, @, *, ?, ¢,±,', %. A colon (:) and typewriter programming codes are entered after each
question requiring data. Figure 1 is an example of part
of a laboratory collection form showing several levels
of subdivisions.
Any headings or typewriter formatting characters,
such as the name of the form or institution, can be
entered preceding the first position code and will
rlohlus, Rlchiird
1"Oec66
PURPOSE OF EXA":
.PBESENT ILLNESS:
Medical Complalnt--Llmp
SevC!r;tl y,.lrs .1;:0 ..,·)tlt:'ed severe limp
after ocean voyage. PE shows absense
of left lower extremity.
pIAGNOSIS:
(Y902-"991-0000). Traumatic amputation
(whale hlte) left lower leg, old.
TREATr~ENT:
Tender loving care
~:
Continue follow-up
EXAM 1111 ur. FAC I LI TY:
I-Ihalers lIospltal', !lew Bedford,
PIIYSICIAtl:
David Jones, M.D.
~Iass.
Underlined words were typed automatically hy programmed typewrlter·under the control of the program tape described In
Figure" •
3
Topography Y920 Lower left extremity
-SNOP codln/::
Morphology 1"72 Traumatic amputation
complete
EtIology
~991
Uhale
FunctIon
0000 Not applicable
Figure 3 - Medical summary - 14 Dec 66
This subsystem for data collection has been formally titled STAT for systematized terminal acquisition technique and is being prepared in detail for publication. 13
Storage of data
The method of storing data on the mass storage
medium departs radically from current data handling
techniques. Both the question and its answer are
stored for each set of data. This is an extravagant use
MEDATA
1-1
HAL E R S
N~w
Redford,
0 S PIT'
Ii
/I
L
WHO
WHAT
WHEN
I/O
Massac~usetts
/IED I CI\l
5U~1~IARY
123"5
:1obius, Richard
Il.8I.t:
01Jan67
Pl:rlPOSE OF EXAII:
Medical Complaint "not
noc"
feelin~
well,
PrlESENT ILLNESS:
About 3 hours following consu~Ption
of one-half barrel spiced Jamaican
rum, patient noticed onset of blurred
vision, occasional dizziness, nausea,
and acute heartburn. Exam showed
elderly white male in minor distress
without si~nificant physical findinp.s.
DIAGNOSIS:
(0000-0000-0000-723b)* Acute overdose
of spices
TREAnlENT:
r,elucil PHN
Advised patient to use unspiced rum
in future.
~:
EXAlllfHfjr, FACILITY:
~avid
PIIYSI CI Ml:
12345
MOBIUS, RICHARD
14DEC66
MEDICAL SUMMARY
PURPOSE OF EXAM:
MEDICAL COMPLAINT--LIMP
PRESENT ILLNESS: SEVERAL YEARS AGO NOTICED SEVERE LIMP
AFTER OCEAN VOYAGE. PE SHOWS ABSENCE
OF LEFT LOWER EXTREMITY.
DIAGNOSIS:
(Y902-1472-4991-0000) TRAUMATIC AMPUTATION
(WHALE BITE) LEFT LOWER LEG, OLD.
TREATMENT:
TENDER LOVING CARE
COMMENTS:
CONTINUE FOLLOW-UP
01JAN67
12345
MOBIUS, RICHARD
MEDICAL SUMMARY
MEDICAL COMPLAINT "NOT FEELING WELL,
PURPOSE OF EXAM:
DOC"
PRESENT ILLNESS:
Hospital, tJew Fledford, "ass.
Janes,
DIAGNOSIS:
TREATMENT:
~.n.
Underl ined words ~/erf~ typed automaticall y by prol!;rammed typewriter under the control of thp prOl!;ram tape described in
Figure II.
*SIIOP cod I np.;: 3
12345. MOBIUS, RICHARD.
SUM-PURPOSE OF EXAM.
ALL.
TYPE.
Return for follow-up one week.
\\'!hal~r5
.Topography
t:orpho logy
Etiology
Function
0000
0000
0000
7236
~ot
COMMENTS:
applic~ble
of storage facilities, but it allows extreme flexibility,
which is the primary objective. If the question precedes each answer, the information may be retrieved
by restating the question and doing a phrase search
of the mass memory. Any question can be added to
the system by inserting it on the tape controlling the
typewriter. No changes are required in the storage
or retrieval programs. The physician and his secretary
have complete control. Facsimile storage, or F ACS,
as this data management concept is called, will be
discussed in detail elsewhere. 13
Retrieval of data
Extraction of pertinent data from the file is as flexible as the storage of the data. The terminal typewriter
or card reader is used for medical requests based on
four questions: WHO?, WHAT?, WHEN?, I/O?
WHO? may be the patient's name or ID number
for medical records or the author's name for library
purposes. If more than one name is required, they can
be entered in a series separated by semicolons. If
selected data are to be retrieved for every name in
the file, the request is answered by the word "ALL."
WHAT? may have answers ranging from one item
to a complete medical record. If a complete record is
required, the name of that record is entered. A single
item or group of items can be retrieved by entering the
name of the record, a hyphen, and the name of the item
ABOUT 3 HOURS FOLLOWING CONSUMPTION
OF ONE-HALF BARREL SPICED JAMAICAN
RUM, PATIENT NOTICED ONSET OF BLURRED
VISION, OCCASIONAL DIZZINESS, NAUSEA,
AND ACUTE HEARTBURN. EXAM SHOWED
ELDERLY WHITE MALE IN MINOR DISTRESS
WITHOUT SIGNIFICANT PHYSICAL FINDINGS.
(0000-0000-pOOO-7236) ACUTE OVERDOSE
OF SPICES
GELUCIL PRN
ADVISED PATIE~T TO USE UNSPICED RUM
IN FUTURE.
RETURN FOR FOLLOW-UP ONE WEEK.
Figure 5 - Purpose of exam retrieved
Not applicablp
Ilot assir.ned (Spices)
Food Intolerance
Figure 4-Medical summary-OUan 67
487
or group to be retrieved. Figure 5 illustrates the information retrieved by a request for all summary information on a patient. SUM is the name of the record of
MEDICAL SUMMARY data. If a common item is
to be retrieved from several records with different
names, such as the diagnoses from all hospital records
for the patient, the question is answered ALL-DIAGNOSIS. Figure 7 shows how ae item of information can be retrieved from charts originating in several
unrelated offices with no limitations imposed on any
of the offices. If selected records are to be retrieved
depending on content, the question is answered by
the name of the record, hyphen (-), the question, colon
(:), and the required series of symbols. Figure 6 shows
the selection of the chart with a specified phrase in
the diagnosis.
WHO
WHAT
WHEN
I/O
ALL.
SUM-DIAGNOSIS: WHALE BITE.
01DEC66 - 2BFEB67.
TYPE.
12345
MOBIUS, RICHARD
14DEC66
MEDICAL SUMMARY
PURPOSE OF EXAM: MEDICAL COMPLAINT--LIMP
(Y902-1472-4991-0000) TRAUMATIC AMPUTATION
DIAGNOSIS:
(WHALE BITE) LEFT LOWER LEG, OLD.
Figure 6 - Diagnosis retrieved
The user-designed system of headings and subheadings has a particular advantage in handling medical data. For example, if information on eyes is requested, the data are returned with all superior and inferior headings-pupils belonging to eyes, under
488
WHO
WHAT
WHEN
I/O
Fall Joint Computer Conference, 1967
MOBIUS, RICHARD.
ALL-DIAGNOSIS.
01JAN67 -·28FEB67.
TYPE.
12345
DENTAL REPORT
DIAGNOSIS:
MOBIUS, RICHARD
03FEB67
GUMS AND REMAINING TOOTH HEALTHY.
12345
MOBIUS, RICHARD
28FEB67
EYE EXAMINATION
DIAGNOSIS:
POOR EYES, MAY CHASE WHALES WITH GLASSES ONLY.
12345
MOBIUS, RICHARD
01JAN67
MEDICAL SUMMARY
DIAGNOSIS:
(0000-0000-0000-7236) ACUTE OVERDOSE
OF SPICES.
Figure 7 - Diagnosis retrieved
the major title, head. This is necessary for questions like WBC (white blood cells or count) which may
be found in blood, serum, urine, etc. Data on WBC are
retrieved with all the headings under which it appears.
Figure 8 shows the retrieval of an item and its identifiers from several sections of the chart shown in
Figure 1. LAB is the record name for the LABORATORY SCREENING TESTS.
WHO
WHAT
WHEN
I/O
MOBIUS, RICHARD
LAB-wac.
06MAR67.
TYPE.
12345
MOBIUS, RICHARD
LABORATORY SCREENING TESTS
CLINICAL PATH
CBC
wac: 10,200
MORPH
wac: NORMAL
UA
MICRO
wac: NEGATIVE
06MAR67
Figure 8 - WBC retrieved
WHEN? may be a specific date, a series or range
of dates, or all dates. Figures 5, 6, 7, 8 illustrate this.
I/O is the choice of the available output units:
TYPEWRITER, PRINTER, MAGNETIC TAPE,
or DISK depending on the application and availability.
This data storage and retrieval system can be used
as a FORTRAN subroutine in developing the data
tapes for more elaborate '" tabular or mathematical
statistical manipulations which users may wish to
undertake with existing packaged statistical programs.
Of course, special programming is required, but the
task is more than half finished when the data are available in computer-readable form. A complete description of this natural inquiry language for retrieval is in
preparation. 13
Computer requirements
Computer requirements for the system are minimal.
The system is written in an extremely basic FORTRAN using only READ, WRITE, DO statements,
GO TO statements, computed GO TO statements,
arithmetic IF statements, arithmetic statements, and
COMMON. All communications between subroutines are done through COMMON to achieve maximum speed and minimum core requirements. As realtime multiterminal monitors become available,
the FORTRAN program can be modified to accept
requests from terminals.
MEDAT A was developed using an SDS 930 with
a console typewriter and magnetic tapes for storage.
An IBM 1050 is the programmed typewriter used in
this system.
Plans for use ofMEDATA concepts
The system is being used for processing medical
data on the astronauts at NASA Manned Spacecraft
Center, Houston, Texas. The basic techniques are
. applicable for -literature storage and retrieval, administrative records, and many other automated data'
processing requirements of a medical institution.
Currently, the MEDAT A methodology is being
adopted for storage and retrieval of all personnel data
for the staff of The University of Texas M.D. Anderson Hospital and Tumor Institute. Preliminary demonstrations have been conducted as the first step toward
applying MEDAT A techniques for all medical records
in the institution.
The system has received enthusiastic support
from the professional staff using the techniques and
those who have participated in demonstrations. The
operations are quickly assimilated by persons with no
background in computer science, and the users appreciate a sense of full control.
Secretarial or clerical personnel were easily and
rapidly trained to create basic master tapes from the
medical records and insert initial data as well as add
subsequent observations. The only prerequisites are
familiarity with mechanical operation of the programmed typewriter and reasonable typing skill.
Typographic errors are quickly corrected by deleting
incorrect entries and typing the correct information.
Querying the computer using the WHO, WHAT,
WHEN, lio technique can be accomplished by anyone - typist or not - after five minutes of training.
N either the physician nor the typist nee~s to learn a
new language to use the computer.
Discussion
The pattern of progress in applying computer
sciences to everyday problems may be likened to the'
MEDATA
pattern of growth in an Airdale puppy. Each extremity seems to develop independently, and not until
maturity is reached does the beast present an appearance of functional integrity. The advent of time-sharing technology is focusing increasing attention on the
most retarded extremity of computer science - providing the unsophisticated user access to computer
power. For the concept of time-sharing to realize its
full potential, the computer must become a functioning
part of the user's environment. The capabilities of
computer connected terminals are multifold and include not only the control of central computer analyses and communication facilities but also provide
significant improvements in data collection and retrieval options. The developments reported here
explore the integration of new ideas and available
equipment to produce a user-oriented medical data
collection, storage, and retrieval system.
During the conception and embryogenesis of
MEDAT A, a concerted effort was made to utilize the
applicable published ideas in the field. The integration of a terminal into the system for acquisition and
retrieval of data by the medical user has been employed by others. 2.9 • 14 The advantages of direct input
by the secretarial personnel through a programmed
typewriter terminal was adopted by the National Library of Medicine MED LARS activity, 1 and .elsewhere. 12 User-oriented data organization and variable
field structuring are fe.atures of several medicallyoriented systems,4.6.7.8.IO and the user-oriented retrieval language (Who, What, When) was first published by our own group a year ago. 5 The amalgamation of these approaches to the various facets of medical records automation resulted in MEDAT A, which
offers new dimensions to the field.
SUMMARY
MEDAT A, an automated medical records system,
represents an organized approach to the collection,
storage, and retrieval of medical data. This completely
user-oriented system takes advantage of the background and training of the medical secretary and simultaneously by-passes the conventional keypunch
operators and coders. It is capable of responding
directly (in his own terminology) to the user who
lacks extensive computer background. The system is
inexpensive to maintain, and the programs and basic
system concepts are machine independent.
489
REFERENCES
1 CJ AUSTIN
Data processing aspects ofM EDLARS
Bull Med Libr Assn 52( I): 159-163 1964
2 G 0 BARNETT P A CASTLEMAN
A time-sharing computer system for patient-care activities
Computers and Biomedical Research 1(1 ):41-50, March 1967.
3 College of American Pathologists Committee ~n Nomenclature and Classification of Disease
Systematized nomenclature ofpathology (SNOP)
Chicago Illinois
4 R H DREYFUS W J NETTLETON JR, J W SWEENEY
Tulene information processing system - version I I
Tulane Univ Comp Sci Series Monograph Number 3 1966
5 W F FARLEY A H PULIDO T M MINCKLER
L D CADY JR
Man-machine communications in the biological-medical
research environment
Proc 21st Nat ACM Conf Assoc for Computing Machinery
pp 263-267 1966
6 C HALl C MELLNER T DANIELSSON
A data processing system for medical information
Meth Infor Med 6(1); 1-6, 1967
7 J KOREIN A L GOODGOLD C T RANDT
Computer processing of medical data by variable-field-length
format-II
Progress and Utilization of the Technique. N. Y. Univ. Med.
Cent. pp. 1-16,June 1965.
8 B G LAMSON B C ULINSKI U S liAWTffORNE
J C SOUTTER W S RUSSELL
Storage and retrieval of uncoded tissue pathology diagnoses
in the original englishfree text form. appendix A _
In user's Manual I -A· Natural Language Information Retrieval System. IBM Data Processing Division of Los Angeles
Scientific Center, November 1966
9 L J LAULER W D FULLER
The Lockheed Hospital in/ormation system
Fifth Annual Symposium on Biomathematics and Computer
Science in the Life Sciences, Houston, Texas (abstract).
pp70-74,1967
10 'L- B LUSTED
Primate record information management experiment
(P.R.I.M.E.)
Oregon Regional Primate Research Center 1966
II T M MINCKLER R K AUSMAN T GRAHAM
G R NEWELL P H LEVINE
HUMARIS-An automated medical data management system
Meth Info Med 6(2):65-69, April 1967
12 T M MINCKLER
The ANTICS of medical coding
Presented at annual meeting ASCP-CAP 27 Sept 67 Chicago,
Ill.
13 T M MINCKLER C L HORTON
A utomation of medical records - the M EDA TA system
Chapter in NASA Publication Uses of Computers in the Life
Sciences (in prep)
14 M V SLACK B M PECKHAM L J VANCURA
W F CARR
A computer based physical examination system
J.A.M.A. 200(4):224-228,1967
Requirements for a data processing system
for hospital laboratories
by IRWIN R. EITER
The Mason Clinic
Seattle, Washington
INTRODUCTION
The modern clinical laboratory should employ automation wherever it is applicable in a continuing effort to
meet the demand for ever-increasing amounts of analytical information. The laboratory must also keep pace
with the latest fruits of medical research which must be
added to the clinical diagnostic armamentarium. This
laboratory information explosion imposes great demands upon the laboratory staff. Little hope exists for
expanding the staff to meet all these demands. Instead,
more efficient use must be made of trained personnel.
This can test be obtained by automation of clinical test
procedures and automation of the accompanying paper
work.
Much has been accomplished in the automation of
test procedures. Several sets of equipment are now
commercially available which relieve the laboratory
technician of the tedium of handling each sample at all
stages of analysis. Many more will be forthcoming in
the near future as instrumentation manufacturers realize the great potential market size and as new instruments become available.
While new automatic instruments perform chemical
analyses and relieve the bottleneck at one stage of the
laboratory information flow system, if not joined with
computers they tend to impose another bottleneck
immediately downstream. This is due to the large
amounts of time required to perform calculations on
the resulting laboratory data and to perform the clerical procedures required by the hospital. At this one
facility it has been estimated that the ratio of time spent
on paperwork versus true technical work approaches
3: 1. The greater the degree of an instrument,!l automation the larger the ratio.
Typically, the hospital laboratory staff must translate voltage values obtained on an instrument into
meaningful values for the clinician, expressed in concentration per unit volume. This alone requires tedious
mathe!11atical or graphical manipulation in which gross
errors occur due to fatigue. In parallel with the calculation stage, the staff must prepare daily log sheets,
laboratory sUl!1mary and statistical reports, quality
control reports and billing information. All of these
procedures are clearly within the capability of currently available computing systems. The major difficulty is one of obtaining operating systems at costs that
will be economically justifiable. As computer piices
drop such systems should become available.
The overall general requirements may be summarized as follows:
1. To minimize routine data processing by laboratory personnel.
2. To reduce error inherent in high volume routine.
3. To provide better utilization of trained technologists for research and development.
4. To reduce data processing time.
5. To provide documented quality control, data.
6. To provide predetermined and invariable parameters for acceptable quality of standards, instrumentation drift and deviation of pooled samples,
documented during test runs.
7. To provide daily, weekly, and patient summary
reports for laboratory, accounting, and clinician
uses.
8. To provide these services on-line during the time
of actual specimen processing.
9. All of this fully justified economically.
Requirements imposed by instrumeniation
Most hospital and/or clinic laboratories have three
types of samples to run: routine (hospital), emergency
(hospital and clinic) and routine (clinic). Routine hospital samples must be reported out of the laboratory
within one day after having been drawn (some specialized tests can take longer). Emergency samples must be
reported as soon as possible. This is especially true of
491
492
Fall Joint Computer Conference, 1967
hospital samples where test results are a major factor in
determining patient treatment. In a clinic, fast response
may be required for some diagnoses, but a one-day
interval is often sufficient. Ideally, in all cases, only
a few hours el~psed time between sampling and reported results should exist. This requires that any data
processing system used to process laboratory results
should te on-line with the instruments and should be
capable of producing results as soon as the sample is
run. A laboratory data processing system must interface
with two varieties of instruments: automated and manual. Automated instruments operate at a variety of
speeds from high frequencies of 1000 cycles/sec. to
slow instruments of 1/10 cycle/minute. The speed of
manual instruments depends on the rate at which samples can be placed in the instrument and the length
of time required for the ins~rument to reach a steady
state reading for the sample. Most manual instruments
produce data points at a frequency of about l/minute.
A variety' of approaches can be used to monitor the
operation of the instrument.
Two basic approaches can be used for the manual
instrument. Since an operator is required to be at the
instrument while it is running, he can either record the
readings and· then enter them into the data processing
system, or he can signal the system to read the signal on
the instrument automatically. Each of these approaches
has som~ advantages. The first approach of recording
the data and entering it together with patient number
into the system after a run is finished is the least expensive of the two methods considered. A standard
keyboard (e.g., teletype or Selectric) typewriter can be
used. Since all of the information is entered in digital
form, signal processing is not required. Human transference of numbers allows room for error and is the
major drawback in the approach. This approach will
also be more time-consuming. The more sophisticated
approach is to have the computer system joined to the
. instrument. When a sample is placed in the instrument,
it can generate a signal which causes the system to read
the instrument signal and search successive readings for
a steady. state level. This approach is free of error from
human data handling and entails less operator time,
but may be twice as expensive as the first approach.
Further pilot evaluations of the relative economics,
accuracy and speed will be the deciding factor between
the two approaches.
The critical factors in evaluating the approaches to
be taken to handle the automated instrument are frequency content and duration of the signal. Most instruments fall into three groups": High frequency-short
duration, medium frequency-medium duration and low
frequency-long duration.
High frequency-short duration instruments are typified by high speed mass spectrometers and cell counters.
At very high speed!), many data points are generated.
Often the scan is repetitive and can be displayed on an
oscilloscope. The best way to handle these instruments
is to store rapidly and continually the raw data by
sampling the signal and converting it at high speed
and to process the data at some later time. This is
effectively slower than real-time computer operation.
An alternative approach is to record the data on high
speed magnetic tape for slow replay into the computer.
This is probably a less expensive approach since high
speed input devices for the computer system can be·
eliminated. Fidelity of the signal is reduced very slightly
by using the tape intermediate, and the costs are certainly reduced. Permanent analog record of the data
is also provided in this approach. For some laboratories and instruments this may be an important feature.
Medium frequency-medium duration instruments are
typified by the "Auto-analyzer" and gas chromatograph. For instruments in this range, real-time data
processing is possible. In this mode, the instruments
are monitored about once each second, the raw data
being processed as it becomes available. In some situations, short delays in processing may be necessary when
exceedingly long routines are required. The effect seen
by the laboratory staff has been one of real-time operation.
On-line data processing is highly inefficient for low
frequency-long duration instruments typified by amino
acid analyzers for which a run may be several hours
long'- with significant data being developed about once
each hour. For these instruments tape recording of data
with fast replay into the computer seems to be the best
approach. Signal fidelity will be maintained bccause the
signals are of low frequency. Since very few tests run
on these long-running instruments are urgently required
by the medical staff, the· computer can be scheduled to
process these tapes during its idle periods (e.g., evenings).
The varied requirements imposed by the laboratory
instruments are:
1. Manual entry station for off-line manual instru-
ments.
2. High speed data input channel for on-line high
speed instruments.
3. Low speed input channels for medium speed instruments.
4. Analog tape input for fast replay of slow instrument signals and slow replay of fast instrument
signals.
Requirements for Data Processing System for Hospital Laboratories
Requirements imposed by hospital personnel
Information stored in the data processing system
must be readily available to hospital personnel. Laboratory staff, doctors, and research workers all will require the capability of entering information into the
system and of interrogating the system as to its contents. These data transfers should require little or no
typing skill on the part of the personnel and should
yield reports with a minimum of excess information.
The laboratory staff must enter information about
test requests into the system. In addition, queries as
to the status of on-line instruments and the contents
of patient files must be entered. Similarly, information
about the test procedures will require modification as
procedures are changed in the normal course of laboratory development. Routine reporting of test results on
each patient and documentation of laboratory work
performed will be initiated by the system itself or they
may be requested by laboratory personnel.
The doctors' prime requirement of the system is a
supply of up-to-date information about their patients.
Test requests are initiated by the doctors who desire
clear, concise laboratory reports of the results obtained
and their statistical significance with respect to hospital norms. In addition, the possibility of entering significant clinical observations into the patient record
should be provided to allow clinical researchers to
have as complete a file on each patient as possible.
The laboratory data processing system is small and
cannot be used to provide a patient record-keeping
service. This task should be considered for the hospital information system which is the central information
system.
Medical research personnel will require the data
processing system to have the capability of being used
as a limited capacity, general purpose computer. In
addition, those involved in the development of laboratory techniques will require access to data developed
in the laboratory in order to evaluate their ideas.
The requirements imposed by the hospital personnel
may be summarized as:
1. Flexible information input capability for both
fixed and variable format data.
2. Multiple output units with a wide variety of
formats.
3. General purpose, as well as special purpose capability.
4. Rapid data retrieval.
Hardware configuration
The description of a system that will satisfy the
foregoing requirements is intended as a guide to the
perplexed, both the manufacturers and the users of
493
data acquisition systems. Several systems are capable
of performing the data acquisition task. Factors of cost
and reliability dictate the use of small systems composed of a minimum of devices. Our experience is
proposed as a guide to the fundamental elements desirable in a hospital laboratory data acquisition system. At the heart of the data acquisition system is a
small computer. The computer acts as both system
controller and data reduction center. Several smallto-medium sized machines, currently on the market,
have sufficient capability to meet the requirements.
The major hazard in selecting a computer is extremism. Too small and/or slow a machine will limit the
ultimate capabilities to which the system may be expanded. Too large a machine is a waste of capability.
Computer specifications should fall within the following capab~lities:
Memory Size_______________________________________ 4-16K Core
Arithmetic Unit ________________ Hardware-Add, Substractless than 3 /L sec.
Hardware-Muftiply-Divideless than 30 /L sec.
Hardware Index Registers
Real-Time Clock
Flexible Input/Output Structure
Direct Memory Access Channel
Data Channels
Program Controlled Data Transfers
Program Interrupt
It should be stressed that the instruction repertoire
need not be very large since -the system will mainly
contain one fixed program. It should not, however,
require a major effort to modify the program. Reliability of the computer is essential to efficient on-line
operation. The computer is potentially the most reliable component of the system and it should te expected that computer failure be a rare occurrence.
Peripheral devices (i.e., tape recorders, typewriters,
printers) have been of notoriously low reliability. This
dictates the use of minimal number of peripherals and
wherever possible some duplication. The system should
be designed to allow operation to proceed despite
any peripheral failure.
In any data acquisition system of more than minimum size, some mass storage device is necessary.
Exceedingly high speed access is not of major importance. Reasonably long times (up to 1 sec.) can be
tolerated to retrieve a record from the mass storage
device. The "majority of this time would be spent
in finding the location of the record in the mass
storage and only a short time spent on actually performing the transfer. The processing system must be
capable of sending a request to the mass storage de-
494
Fall Joint Computer Conference, 1967
vice and then continuing operation until the actual
data transfer takes place. Reliability is of great importance here since system operation would be drastically curtailed if the mass memory unit became inoperable.
The basic communication channel between the system and the hospital personnel is through the keyboard typewriter/printer unit. The most widely used
unit is the teletype. At least two are highly recommended and the most rugged versions should always
be used. One unit should be equipped with a paper
tape punch and reader. Only in very large systems
will' a high speed line printer be worthwhile.
A slow speed card reader should also be included. Information entered on cards includes: test
type information, to be entered only when modified, and any standard input information to relieve
the need for typing. It is expected that the card reader
will occasionally not be functioning properly.
The analog and digital interface which allows direct monitoring of laboratory instruments is composed
of scanners or multiplexers, A to D converters, and
a set of digital logic for testing instrument operating
conditions. Two analog input systems. can be used
for fast and slow input respectively. The slow speed
unit should be capable of accessing 200 points/sec.
while the high speed unit should be capable of at
least 10,000 points/sec. Both units should operate
under program control. The digital interface should
be able to detect voltage above a preset level and
switch closures, generating logic levels 1 and 0 for
true and false states respectively. In addition, the
capability of reading a set of voltages or switch closures in groups equal to computer word size and
organizing them into computer words is essential.
The signals on most slow and medium' instruments
can be taken from the swinger of a retransmitting
slide-wire mounted on the recorder. The swinger is
connected to the input of the scanner. The scanner
in the slow speed input unit is sequentially connected to
each position. At each position are several signals:
1) a ground reference, 2) the signal from the swinger,
and 3) any logic that may be used to test instrument
conditions. From the scanner, the analog signal is
sent to the analog-to-digital converter which is under
program control.
The digital interface consists of a battery of logic
elements which interrupt the computer when instruments need to be serviced. Instrument priorty may be
established either by hardware logic (e.g., a daisy chain
in which instruments connected closer to the system
have higher priority) or by software routines which
check a sequence of interrupt sources; the sequence
establishing the priority. Also included in the digital
interface are control units located at the instrument.
These units are used by the laboratory personnel to
inform the system of the status of the instruments
at that location. In addition, any manual data entry
stations are processed by a digital interface which
essentially reads a special purpose keyboard.
Software configuration
The key element in obtaining a working data acquisition system is the software. Many shortcomings in the
hardware can be offset by creative programming.
There are basically four parts of software: executive
routines, data processing routines, bookkeeping routines, and communication routines.
The executive routines are responsible for controlling the operation of the system. The order and
timing for servicing interrupts are its most important
responsibilities. Many different approaches to priorities can be used. One simple approach is to perform
a minimal amount of processing on each interrupt as
it occurs. The interrupts which are waiting and have
not been completely serviced are then checked to
determine which is oldest and the oldest is then processed. An alternative is to develop some method of
deciding how much is to' be done with each interrupt
and handle the shorter ones before the longer ones.
Another scheme which has merit is to assign levels
of processing required of each interrupt, e.g., level
1 will be storage of raw data, level 2 will be data
smoothing, level 3 peak picking, etc. Level 1 is
performed on all interrupts. Then, if time permits
before the next interrupt, any level 2 processing
jobs will be done. Certain levels like level 3 will result
in assigning. higher levels to the data .(e.g., performance of standardization· or conversion of a peak value
to, concentration units) or will result in completed
processing of that piece of data. It is assumed in
all these priority schemes that there is sufficient time
to process all the interrupts since there will be slow
periods when less work is required by the system.
The executive routines also control the sequencing of
the printout routines, assigning highest priority to
those messages which require some action on the part
of the laboratory staff (e.g., a warning that the standard
samples are not in the proper ranges) and lowest
priorty to printing long summary reports.
The data processing routines are called in a variety
of sequences by the executive routine to perform all
mathematical manipulations of the data stored iri the
computer. For most on-line instruments, the data
processing steps of "smoothing" and "peak-picking"
are common to several types of instruments, while
Requirements for Data Processing System for Hospital Laboratories
others such as the calibration and unknown determination routines may be specific to one type of instrument. Development of these data processing routines
requires a thorough understanding of the laboratory
methods. Also, included in the data processing routines
are a group of subroutines that are used by many
different routines. Such subroutines as floating point
addition, multiplication and division, binary to Binary
Coded Decimal (BCD) and BCD to binary conversion
routines, transcendental functions, and various logic
routines 'that are not performed by hardware registers
are included in the set.
Bookkeeping routines perform all the data sorting
required by the system. This includes sorting test
requests into lists of samples to be run on each test
type, relating calculated data on an instrument run
to the patient's record where they are to be filed,
and assembling data in formats required for typeout
routines. No data manipulation is performed by these
routines except for data conversion between the coding
required by the input/output peripherals and the binary
coding of the computer.
Communication routines perform all the operations
of acquiring data into the system from the instruments
and the peripherals, and developing reports for the
laboratory and hospital staffs. These ,routines include
the testing of instrument status (on, off, test type,
samples exp.ected, etc.), obtaining analog data from
the instruments in the digital form required by the
computer, obtaining information entered through the
teletypes and card reader, printing of laboratory work
reports (instrument load tests, daily work reports, billing reports), and patient record reports on a test
request basis and on a summary report basis.
In the normal mode of operation, the executive
routine resides in core and calls routines as needed
from bulk storage into core. Sections of core are also
reserved as transfer stages between core and bulk
storage and between core and peripheral devices. In
addition, all data of current interest to the system
are stored in core including fixed information such
as values of test standards and the information currently being developed by the instruments. The executive routines also reside in bulk storage to eliminate
the need of loading it through the paper tape reader.
Initially, a small paper tape routine is entered into the
computer which when executed enters the executive
routines into core and starts the operation. The executive routine need not be entered into core again
unless it is determined that part of the routine has
been lost.
All software routines are permanently stored on
paper tape and cards. In addition to the full system's
495
normal routines, several operable routines of a more
limited scope are available to avoid using particular
components of the computer should any part of the
system be out of operation. Thus, if the bulk storage
is inoperable, a routine can be used which merely
processes the data as it is developed on the instrument and produces reports based on laboratory runs.
Data sorting according to patient is eliminated as is
summary reporting. All data produced during this
period are stored on paper tape so they can later be
entered into patient records when the bulk memory
is again operable.
System development
Since the system described here is large and the
operation complex, it is recommended that development be done stepwise. This will allow the laboratory
staff to gain confidence in the system's capability and
not frighten them with a large "monster" they cannot
understand. Laboratory personnel should be closely involved in the development to aid in obtaining acceptance of the system. The cost of such a system is relatively high for most hospital laboratories and the
stepwise acquisition of the system greatly eases the
strain on the budget. Almost all that is done during
the early stages will be of use at later stages.
The first stage is the development of a unit which
will acquire data from several instruments of the
medium speed variety in an on-line, real-time mode.
No patient identification or sorting is performed by
the system at this stage. All results are in the form
of a report on an instrument run. (Correlation between
position on the run with patient is still done by hand.)
The report, developed at this stage, will be used in
later stages as a laboratory work report to provide
documentation of laboratory procedures. At present
pricing levels, cost of this initial system can range
between $35,000 and $100,000 depending on the size
of the computer and the size and type of interface (instrument and human) developed.
This level is a convenient point to use on the first
stage since it will not appreciably disturb the information flow in the laboratory and will relieve the
laboratory staff from hand mathematical processing
of instrument data. Since little peripheral equipment
is involved (teletype, analog, and digital interface)
reliability of the system can now be proven. Laboratory staff should become involved with the system to establish complete confidence in the system's capability.
Further development is aimed in two directions, increasing the number· of instruments tied into the system and increasing the amount of the paper work load
496
Fall Joint Computer Conference, 1967
assumed by the computer. As new instruments are put
on-line with the system, thorough testing of the data
processing must be performed. Addition of peripherals
such as a card reader will enable the computer to
assume the job of preparing load lists for the instruments. Bulk storage will allow for the keeping of patient records and reporting of results on a patient-bypatient basis thus eliminating two of the major paper
work jobs now performed by laboratory personnel.
The major guidelines at all times should be proven
capability, system reliability, economic justification for
expansion, and maintenance of system flexibility. At
present a reasonably sized data acquisition system for
a hospital laboratory will be capable of accepting test
requests on punched cards, providing instructions to
laboratory personnel for the running of instruments,
automatic retrieval of data from about twenty automatic instruments and several manual instruments. It
will also provide documentation for the laboratory,
the medical staff, and the billing office in terms of test
results, individual and summary reports on each patient, and amounts to be charged to patient accounts.
While little or no attention to the inner workings of
the system should be required during normal operation,
in-house capability to modify the computer system will
become desirable if the unit is to keep pace with laboratory developments. At present price levels in the
computer industry, such a system as described here
will cost approximately $250,000. This is more than
the market (with a few exceptions) will be able to
afford. A price tag closer to $150,000 will be more
acceptable for a system that is completely assembled
with a complete set of operating software.
As hospital computer systems of several varieties
are developed and become accepted pieces of equipment, an integrated hospital system will be required.
Each separate unit such as the laboratory data acquisition system should then act as a satellite unit exchanging information with a central hospital information system. The need for a separate laboratory unit
will then become especially great. The central hospi:'"
tal system will be occupied with retrieving, assorting,
and supplying information to and from all parts of
the hospital and should not be required to devote
large amounts of time to processing laboratory information. With a laboratory data acquisition system
preprocessing the laboratory data into a form that is
compatible with a central information system, the
laboratory will be able to make highly efficient use
of the central system.
An advanced computer system for medical research
by WILLIAM J. SANDERS, G. BREITBARD,
D. CUMMINS, R. FLEXER, K. HOLTZ, J.
MILLER and G. WIEDERHOLD
ACME Project, Stanford Medical Center
Stanford, California
INTRODUCTION
The ACME project
The Stanford University School of Medicine is located
on the main campus of Stanford University, in Palo
Alto, California. It was moved from San Francisco to
the Palo Alto campus, in 1959, with the purpose of
more closely integrating medical research and education with the other activities of the University. It
shares, with other departments of the University, thecomputing facilities of the Stanford Computation Center. These. facilities include an mM 7090, a Burroughs B-5500, and a recently delivered mM/360-67.
In addition, there are currently four PDP-8, four LINC,
and one LINC-8 computers in use within the medical
school. Although this collection of computer~ represents a great deal of computing power, its distribution
was such that the research needs of the medical school
were not being fully met.
The Stanford Computation Center is dedicated to
serving the broad needs of the University community.
With the current batch-processing systems on the 7090
and B-5500 and the planned time-sharing system on
the 360-67, the Computation Center is obliged to provide general-purpose computing to a large number of
users with quite diverse interests. Inevitably, the needs
of any special group cannot be entirely satisfied. In
particular, many of the needs of the medical research .
program are such that a general purpose computing
system is not satisfactory. Among these needs are:
1.
2.
3.
4.
5.
Analog-to-digital and digital-to-analog conversion
Real-time data collection and analysis
On-line control of experiments
High-speed data acquisition and distribution
Support of satellite computers.
497
The small computers within the· medical school provide some relief, in that they are equipped for analogdigital conversion and are being used for data collection and analysis and for control of experiments. However, being small and having few peripheral units, they
are limited in the amount of data analysis they can do
economically. They are also more difficult to program,
since their software is generally quite primitive. In addition, not all research projects can afford the lUXUry
of having their own computer nor the specialized manpower to program it.
In order to determine how the needs of the medical
school research program could best be met, a medical
school computer policy committee was formed. The
committee worked actively with the medical school
computer user's group, the Stanford Computer Sciences
Department, and the Stanford Computation Center. The
result of the committee's work was a proposal for the
ACME (Advanced Computer for Medical Research)
Project. Initial funding for the Project was a planning
grant from the Josiah Macy Foundation, while ongoing support has been provided by a grant from the
National Institute of Health, the Macy Foundation, and
sharing of costs with other projects at the Stanford
Medical School.
The purpose of the Project is to provide a computer
system specifically designed for medical research. The
ACME system is designed to act as a complement to
currently existing facilities. It is assumed that a great
deal of data-processing still will be done using the
facilities of the Computation Center. By providing data
storage and analysis facilities for the small computers,
their capabilities will be greatly enhanced. In addition,
by providing central signal-processing equipment, the
system will support researchers that do not have their
own computers.
498
Fall Joint Computer Conference, 1967
A unique aspect of the Project is that it is a research
project in support of research projects. In order to
provide the medical school with the computational
facilities necessary to do research, much development
must be done by the project. It is planned that the
ACME system will always be in a state of flux. As
the more general-purpose computer systems are able
to provide a service that is also being provided by
ACME, that service will be dropped by ACME in
favor of the other systems. At the time a need is found
for a service not then available, that need will be met
be extensions to the system. Thus, it is planned that
the ACME system will be constantly devoted to the
new and untried areas of computation, and in this way
also will be a complement to existing facilities. '
Within the ACME project, there is equal emphasis
on hardware and software development. Hardware
development is mainly concerned with interfacing the
ACME system with the users and their experiments.
Software development is concerned with providing noncomputer oriented researchers with the tools necessary
to do their work in a rapid and convenient manner.
There has been a great deal of effort expended in
developing a hardware/software complex where the
hardware and software closely match both each other
and the user and his experiment. Much effort has also
been devoted to developing more suitable, and often
less expensive, alternatives to manufacturer supplied
hardware and software.
Bpth in terms of size and budget, the ACME Project is modest compared to many. But because of the
fact that its goal is also relatively modest, that of
providing a specialized set of services to a small and
quite homogeneous set of users, it has already made
a great deal of progress toward achieving that goal.
ACME system
The main purpose of the ACME system is the acquisition, analysis, storage, and retrieval of medical
research data. In addition, there will be writing and
debugging of programs necessary to support these
activities. In the light of these requirements, it was
decided that the most reasonable mode of operation
for the ACME system would be time sharing; with
emphasis on real-time data acquisition, and data storage and retrieval. This is an area where equipment that
is currently available is very weak. Only very large
specialized systems, mainly in military and space exploration environments, have achieved operational status. In order to make program writing and debugging
as easy as possible it was decided that a compiler for a
simple, yet relatively powerful programming lan~age,
would be written specifically for the ACME system.
It should be noted that the design criteria for the
ACME system are relatively different from those of
most other time sharing systems. Because of the demands of real time data acquisition, emphasis is not on
giving fair and equitable service to a large group of
users. Rather, it is to give high performance service to
a relatively small group of users, while also answering
the lighter demands of on-line program creation and
debugging. Because of the demands of real-time operation, it is often better to refuse service to a user (telling him to try again later) than to offer a service that
is degraded beyond usefulness to him or others using
the system. Special provisions in the hardware and
softwar~ have been made to reflect this philosophy.
Hardware for the ACME system
A general sketch of the ACME system is shown in
Figure 1. The central processor for the ACME system
is an IBM/360-50. This was chosen for several reasons. First, it is supported by a large amount of mMsup.plied software. Inasmuch as is possible, this software is used in preference to expending the effort to
create similar software. Second, it is supported by a
large variety of peripheral units, both mass-storage and
input/ output. Third, it provides a large measure of
computing power and I/O versatility for a relatively
low cost. Fourth, it provides upward-and-downwardcompatibility with a broad line of computers, so that
the system can be easily up-graded or down-graded to
meet future conditions. Finally, it is highly compatible
with the 360-67 at the Computation Center.
In order to provide real-time capability in a straightforward manner, it is necessary that the user program
and data areas can be accessed very rapidly in a random
manner. Core memory is the only device satisfying this
requirement.
Estimates of the amount· of memory required led
to the following balance of the core memory versus
number of users.
Assumptions:
(1) A control system of 7090 size.
(2) A resident compiler, library and input/output
system, requiring 3 times the available memory
of a 7090.
(3) User problem size distribution as on current
large machines (i.e., IBM 7090's etc.) leading
to an average of 14,000 words. See Figure 2.
( 4) Program writing and translation will occupy
the system 25 % of the time.
With these assumptions:
3 x 26000
n
Memory required == 6000
n x .25 x 6000
X .75 x 14000
or 84000
n x 12000
This meant that a balance could be achieyed at 15
users and 264000 words of memory.
+
+
+
+
An Advanced Computer System for Medical Research
Collected
7B9
track tapes
Main processor
360-50
System
User Programs
and Data
Disks
2311
Resident
Programs
4.10 8
characters
Data Cell
2321
Data
499
Analogue and
Digital
Devices
50 pOSSe
20 active
User Commands
User Buffers
Commands
Resident
1----------1
Data 1 Kc
B
Index
Data> 10Kc
Fast Memory
2702
Typewriter Stations
50 pOSSe 30 active
initially 32 pOSSe I 5 active
Figure l-Sketch of ACME system
2701
Small
Computer
Users
270X
Multiplex
Data
8 pOSSe
4 pOSSe
active
4 connected
4 active
500
Fall Joint Computer Conference, 1967
Words of Memory
32,000
24,000
18,000
12,000
6,000
.I
.65
.75
1.0
Cumulative fraction of use
NOTES:
I.This region represents users using facilities on data stored
in files, or doing desk calculator level work.
II. This region represents the normal computing workload.
Much of this is used for data array storage. Declared
arrays are generally only partially filled, leading to the
apparent steepness of the curve.
III. Some percentage of users find that they tend to exceed
the capabilities of the system and operate just below
the maximum.
IV. During translation, program text and symbol tables
very rarely exceed 6000 words.
Figure 2-User program size distribution
In order to get this amount of memory economically,
it was decided that a minimum amount of relatively
expensive fast memory would be obtained. The fast
memory is used for residence of the 360 operating
system and the most frequently used portions of the
ACME software.
The major portion of the memory for the ACME
system consists of a one million byte Large-Capacity
Storage unit. This is attached to the central processor,
and is addressable contiguously to the fast· memory.
Although its cycle time is much slower ( 8 IL sec vs. 2 IL
sec), its cost per bit is about one-fourth of the central
processor memory. Furthermore, the processor of the
Model 50 can do some parts of a process without core
references, and tests have indicated a factor at 2.3
performance degradation. In this way, enough memory
could be obtained to keep the entire ACME system
and all active user programs core-resident at all times.
This is extremely important to the philosophy of providing high-performance service and is possible because of the small number of users. Because an active
program is always core-resident, it is always executable,
and hence can respond rapidly to real-time demands.
Because all active programs are core:-resident, memory
allocation problems are minimized and such techniques
as program relocation become unnecessary. The lack
of memory swapping, paging, and concomitant problems such as special I/O buffering, greatly reduces
system overhead.
Mass storage for the ACME system consists of
three hierarchical levels. The lowest level is magnetic
tape, which will be used for archival purposes. One 7track unit is provided for compatibility with the 7090
and B-5500. One 9-track unit is provided, because of
its higher performance and because it is necessary
for generating the 360 operating system.
The next level of mass storage is the 2321 data
cell. It has a storage capacity of 400 million bytes, with
an average access time of 600 ms. This is the main
storage device for the ACME system. On it, all user
source programs and data are stored. Its capacity is
large enough that it is expected that all programs and
data will be permanently resident in the data cell, with
no need to dump or reload from tape, except for backup purposes. Special programming techniques have
been developed to minimize the effect of its relatively
slow access rate and to take advantage of its large
capacity.
Another level of mass storage is the 2311 disc storage drive, of which there are only two in the ACME
system. No user storage is provided here. One disc
drive is used to store the non-core-resident portions
of the 360 operating system. The other disc drive is
used for two purposes. First, all of the ACME software
is stored there, for initial loading when the system is
started. The second, and most important, function
of the drive is to store indices to information on the
data cell. Whenever a user file on the data cell is
opened, its location is determined from a catalog. An
index to all records in the file is then moved from the
data cell to the disc. Subsequent references to records
in the file are then made using the disc-resident index.
An Advanced Computer System for Medical Research
Figure 3-Terminal indicator panel
501
Figure 4-Switchboard
is feasible at a great reduction in cost over other modes
When the file is closed, the up-dated index is copied
of operation. Communication with the 2741's is proback from the disc to the data cell.
cessed by a 2702 communication multiplexor.
Each user of the ACME system has an IBM 2741
The need for other than typewriter output devices
terminal. This is the device used to input programs,
has been obvious for a long time. But the cost of
debug them, and control their execution. Since it is
commercial devices in a medical environment is such
basically a modified Selectric typewriter, it has the
that they are scarcely defensible in comparison to other
advantage of being familiar and easy to use for nonmedical aids.
computer oriented users. ACME has modified its 2741
However, two Sanders Associates character-oriented
by the addition of a 4 light indicator panel (Figure 3).
CRT displays have been ordered as experimental adLights on the indicator panel are controlled by nonjuncts to the ACME system. These will be used for
printing characters transmitted to the 2741. There is
development in areas of text editing and information
one light that reads, "ACME IS ON." It is driven by
retrieval. Because of the high data rate necessary to
the transmission control signals to indicate that the
support these devices, they will be connected to the
system is operational. Another light reads, "YOU ARE
ACME
system via a 2701 with a parallel data adapter.
ON." It is pulsed at a rate proportional to the amount
to the 2701 is being supplied by Sanders
The
interface
of computing time the user is getting. The flicker rate
Associates.
thus indicates the performance of the system with reA special CRT display has been designed and built
spect to that user. Another light reads, "WAITING
by the ACME Project for the input/output of graphical
FOR YOU." It is on whenever the system is expecting input from the user. The final light reads, "SPE- , data (Figure 5). It is driven by vector-drawing logic
and a core refresh memory. This unit is capable of
CIAL RUN ON." It is on whenever a high demand,
displaying 2046 vectors simultaneously. It was built
real-time data transmission process is active. It infrom integrated circuits, and the component cost, indicates that severely degraded terminal performance
cluding the memory, was about $8,500. It will be concan be expected.
nected to the ACME system via another parallel data
Most of the 2741's are connected directly by cables
adapter on the 2701.
to the ACME system. Because of the fact that most of
A need still exists for a silent hard copy device for
the 2741 's are within 2000 feet of the system, no indeveloping data distribution to hospital wards.
tervening cable drivers are necessary. The cables termiFor the processing of user analog and slow (less
nate in a switchboard-like patch panel (Figure 4).
than 1 Kc; i.e., 1000 samples per second) digital data
When a user wants to use his terminal, he telephones a
an IBM 1800 computer is used. The 1800 is a small
computer operator, who connects his terminal to the
process control computer with a large complement of
system via the patch panel. Initially, there are 32
signal processing attachments. It will be used to do
terminals with the possibility of 15 active at one time.
analog-to-digital and digital-to-analog conversions, as
Because of this low ratio, and the fact that terminal
well as some primitive signal processing such as smoothsessions are expected to be lengthy, manual switching
502
Fall Joint Computer Conference, 1967
Figure 5-Prototype of graphical display
ing and validity checking. It is connected to the .central
processor via a high speed data channel so that it
behaves essentially like an input/output device as far
as the system is concerned. When relatively low band\yidth analog signals are transmitted, and no more than
8 bits of accuracy is needed, analog-digital conversion
is done on the 1800. For more demanding signal processing, the analog-digital conversion has to be done
in the laboratory and digital data is transmitted to the
1800. There are currently 32 analog-to-digital inputs,
8 digital-to-analog converters,· 20 digital inputs, 12
,.digital outputs, and 80 process interrupt lines on the
1800. The timing of the data acquisition and distribution is user controlled through the process interrupt lines
so that no synchronization of multiple experiment data
rates is required. All analog and digital transmission
equipment was designed and built by· the ACME Project. One of the most interesting pieces of analog
transmission equipment is an FM analog transmitter
and receiver that is magnetically and acoustically
coupled to an ordinary telephone. This will be used
to process analog signals over distance or where no
cables have been pulled.
For transmitting digital data in the speed range be-
tween 1 and 10 kc, a special multiplexor has been designed and constructed by IBM for the ACME Project. For lack of a better name, it is called the 270X.
It is capable of multiplexing 8-bit digital transmission
over cables between the ACME system and up to 16
remote units. Each remote unit is called a 270Y. There
are currently four 270Y's. The 270Y's are designed for
laboratory use, and are rack mountable. Each has binding posts for 8-bits of input and output, and for timing
and control signals. Each has a push-button to terminate a transmission, and a signal line to cause a central
processor attention interrupt. In addition, each 270Y
has a built-in variable frequency oscillator to control
sampling rate, or the sampling rate may be controlled
via an external line. In addition to the local samplingrate oscillator in each 270Y, there is a programselectable oscillator in the 270X whose rate is adjusted
to drive a digital incremental plotter. Thus, for example, a typical use of the 270X-270Y might be as
follows. The inputs would be connected, via a suitable
analog-to-digital converter, to an instrument such as
a gas chromatograph. The sampling rate would be
determined by the setting of the local oscillator on the
270Y. The outputs would be directly connected to an
incremental plotter. A trial would be run, the data
analyzed by a program that the user has written, and
the results plotted immediately at the experimenters
station. It takes little imagination to see the potential
for this mode of operation.
It is expected that data rates in excess of 10 kc will
be generated only by the CRT displays and the small
computers. These will be connected to a 2701 with
four parallel data adapters. Each parallel data adapter
has a data path 16 bits wide, and is capable of sustaining speeds in excess of any demand now foreseen. Because of this high data rate, the 2701 has been connected to a central processor selector channel,. which
can sustain a high data rate with lower interference
to computation. But since the selector channel can
control only one transmission at a time, there must be a
limit to the amount of time each transmission takes.
Thus, it was decided that the normal mode for high
data rate transmission (Le., over 10 kc) will be short,
very high speed bursts of data (Le., 20 kc or higher).
To connect the small computers to the 2701, a special
interface was designed. The interface transmits data
in parallel over cables on a demand/response basis.
Provision has been made for remote computers to gain
the attention of the central processor via an attention
interrupt. In addition, a 25 ms. "dead-man" timer in
the interface limits the time any single burst of data
transmission can take.
The remaining hardware consists of unit record
equipment on the 360 and 1800. This will be used
An Advanced Computer System for Medical Research
mainly for batch-mode operation during software
development and checkout. In addition, during the
early stages of time-shared operation the 360 printer
is being used to keep a log of all transmissions to and
from terminals. This should greatly facilitate the detection of problems that develop in using the system, both
from the point of view of user difficulties and the
detection of bugs in the software.
Software for the ACME system
The software for the ACME system will be divided
into, the following categories for purposes of discussion:
1.
2.
3.
4.
5.
6.
7.
The 360 Operating System
The ACME compiler
Resource allocation (including time-slicing)
Data-file management
Terminal input/output
Real-'time input! output
Library subroutines
One of the early, and significant, decisions in the
design of the ACME system was the decision to use
manufacturer supplied software whenever this was
feasible. Thus, the entire ACME software system was
designed to run as a single job under Operating System/
360. During the operation of the ACME system, OS/
360 provides such services as low-level input/output
management and memory allocation, dynamic subroutine loading, and interval timing. This mode of
operation has two significant advantages. First, a great
deal of highly specialized programming can be avoided.
Second, most of the remaining programs are machine independent, and hence can be written in a
machine-independent manner. In fact, most of the
ACME software has been written in FORTRAN. It
was found that the IBM H-level FORTRAN compiler
is capable of producing very efficient code and, thus
there was virtually no advantage in not using this
machine-independent language. The few routines that
were written at an assembly language level were mostly
for such machine-dependent operations as character and
bit-manipulation and for communication with the
Operating System and for machine code skeletons.
Almost no modifications were made to OS/360.
The few exceptions were in areas where the operating
system provides for user-supplied modifications and
these modifications were relatively straight forward
Hence, almost anyone with a similarly configured 360
should be able to use the ACME software with a minimum of effort. In fact, with the mUlti-programming
versions of OS/360, the ACME software is useable
concurrently with other modes of operation.
The ACME compiler will be discussed fully in a
503
future paper, and hence will be only briefly discussed
here. The compiler is for a subset of PL/l that includes many of the most useful features of the language.
It is incremental; that is, it compiles one statement at
a time and a program is always capable of execution.
It compiles all the way to machine language, and thus
produces relatively efficiently executing code. All system-user communication is processed by the compiler,
hence the system command language is a subset of the
compiler language, with identical syntax. Also included
in the compiler language are text-editing functions for
modificatio'n of program texts. For such processes as
input/ output, subscript range checking, and the computation of mathematical functions such as SIN, COS,
and standard statistical procedures, the compiler generates calls to a resident library of subroutines. Some of
these subroutines are also written in FORTRAN, and
in fact use the IBM-supplied FORTRAN subroutine
library for such things as input/output formatting.
Resource allocation consists mainly of memory allocation and time-sharing. Memory is allocated to users
in 4048 byte ( 1024 word) quantities called pages.
When a user has logged. in he is assigned one such
page in which his file names, etc., are kept. For programming two more pages will be assigned for program and data storage. More pages are assigned as they
are needed during the compilation of his program.
Memory for object-program arrays is not allocated
until each array is referenced during execution. Hence
there is some saving in memory during the time a user
is creating his program. It is not necessary that the
pages for a user program be contiguous in memory.
Hence the problems of memory allocation are greatly
simplified.
Because most of the ACME software was compiled
under H-Ievel FORTRAN, which is not capable of
producing re-entrant code, allocation of time to users .
is not done in the usual manner. Instead of switching
from one user to another at the end of some arbitrary
time interval, switching is done only at so-called "reentrant points." A re-entrant point is defined as a
point at which:
1. All required information concerning the current
user is located in storage peculiar to that user.
2. The next operation to be executed on behalf of
the user is a call to a subroutine which will not
return to the calling routine.
These two conditions are sufficient to insure a somewhat limited, but nevertheless adequate form of reentrant programming. The scheme relies on the fact
that the H-Ievel FORTRAN compiler generates a prologue which is always executed upon entry to a subroutine. This prologue initializes information internal
504
Fall Joint Computer Conference, 1967
to the subroutine, but peculiar to the current invocation
of the subroutine.
The necessity of limiting switching to only certain
points leads to the interesting situation in which the
current user graciously yields his control of the machine, rather than having it wrested from him. However, proper etiquette in this regard is assured in several ways.
1. When a user is compiling a program, the structure of the compiler assures a reasonable discipline for user switching.
2. All requests for input! output activity require a
yicld.
3. A check is built into the code generated by the
compiler at each GO TO and END statement
for the end of a time interval. A yield will result
if the time interval has elapscd.
In the process of yielding, a "resume routine" is indicated. This routine is entered when the user is next
given control. Yields that accompany input/output requests generally specify a wait until the input activity
is completed, due to the interactive nature of most
system use. Users currently are served in strict order,
on a round-robin basis. There is some probability that
a priority scheme may be introduced later, if experience
indicates that high data-rate experiments cannot be
served with the round-robin scheme.
Because one of the major purposes of the ACME
system is information storage and retrieval, special data
management pro~edures have teen designed to facilitate
these operations. User data, and programs, are stored
in data sets on the data cell. Data sets are ordinarily
catalogued by us'er name, then by a project name, and
finally by a user assigned data set name. When a data
set name is mentioned in a program, it is automatically
qualified by the user name and project name supplied
at log-on time. This automatic qualification is overridden by explicit qualification of the form USERNAME.PROJECTNAME.DATASETNAME. This method of
data set naming is essentially identical to that used by
OS/360, although OS/360 cataloguing procedures are
not used. In addition, certain public data sets will be
available. Among these will be a set of standard useroriented programs.
Within the data sets, data is stored in the form of
records. Records may be stored sequentially or randomly and may be retrieved sequentially or randomly.
Records may be of arbitrary length. Data items are
stored and retrieved from records by name. Hence,
data items may be retrieved in an order different from
the one in which they were stored. Moreover, fewer
data items may be retrieved than are stored in a given.
record. This mode of operation is unlike that used in
most current programming systems, -where item order,
not name, is significant. It is felt that the mode chosen,
although somewhat less flexible, is much more in line
with the thinking of the non-computer oriented personnel who wi1l be the prime users of the ACME
system.
The terminal input/output procedures used by the
ACME system were also designed by the ACME Project. Output from the system is generally in the form
of a message and a prompt. The message portion is
the result of the last operation performed and the
prompt portion is used to indicate what should be done
next. A question mark (?) is used to indicate the end
of the output. For example, during the log-on procedure
the output from the system is the prompt NAME?
The user then supplies his name. If the name is not
acceptable, the system types an error message and reprompts NAME? During compilation, the system
prompts the line number of the next line when compilation of the preceding line is successful. If the compilation of the preceding line is not successful, the compiler supplies an error message and re-prompts the
previous line number. Messages are genenilly quite
long, so that a maximum amount of information can
be conveyed. If a user recognizes a message and does not
want to see it again in its entirety, he pushes the ATTENTIoN button on his terminal, which causes an
ellipsis ( . . . ) to be typed and the rest of the message
to be skipped.
The prompt portion of a message can usually not
be ignored because it remains in a buffer as part of
the user's next input. All prompts are recognizable
to the compiler as commands, with the question mark
treated as a blank. Hence, if PROJECT? is prompted
and the user types DOGWEIGHTS, the input to the
system is PROJECT DOGWEIGHTS. In fact, the system forgets what it has typed out; it only looks at the
next input line to decide what to do next. If the user
wishes to ignore a prompt, he may back-space over
it, which causes it to be deleted, or he may push the
ATTENTION key which causes the current input line
to be ignored and a prompt of ? to be typed. Similarly,
in the case of some syntax errors, the compiler merely
prompts a corrected version of the statement. If the
user wants to use the corrected version, he merely types
carriage return, which causes the prompt to be used
as input.
Real time input/output was also designed to maximize user convenience. With the exception of the 270X,
which is still in the developmental stage, all real-time
input! output is generated by satellite computers, either
the ACME 1800 or the remote small computers. A communication protocol has been established for all transmission between computers. The protocol is designed
An Advanced Computer System for Medical Research
mainly for batch-mode operation during software
development and checkout. In addition, during the
early stages of time-shared operation the 360 printer
is being used to keep a log of all transmissions to and
from terminals. This should greatly facilitate the detection of problems that develop in ~sing the system, both
from the point of view of user difficulties and the
detection of bugs in the software.
Software for the ACME system
The software for the ACME system will be divided
into the following categories for purposes of discussion:
1.
2.
3.
4.
5.
6.
7.
The 360 Operating System
The ACME compiler
Resource allocation (including time-slicing)
Data-file management
Terminal input/output
Real-time input/output
Library subroutines
One of the early, and significant, decisions in the
design of the ACME system was the decision to use
manufacturer supplied software whenever this was
feasible. Thus, the entire ACME software system was
designed to run as a single job under Operating System/
360. During the operation of the ACME system, OS/
360 provides such services as low-level input/output
management and memory allocation, dynamic subroutine loading, and interval timing. This mode of
operation has two significant advantages. First, a great
deal of highly specialized programming can be avoided.
Second, most of the remaining programs are machine independent, and hence can be written in a
machine-independent manner. In fact, most of the
ACME software has been written in FORTRAN. It
was found that the IBM H-level FORTRAN compiler
is capable of producing very efficient code and thus
there was virtually no advantage in not using this
machine-independent language. The few routines that
were written at an assembly language level were mostly
for such machine-dependent operations as character and
bit-manipulation and for communication with the
Operating System and for machine code skeletons.
Almost no modifications were made to OS/360.
The few exceptions were in areas where the operating
system provides for user-supplied modifications and
these modifications were relatively straight forward
Hence, almost anyone with a similarly configured 360
should be able to use the ACME software with a minimum of effort. In fact, with the mUlti-programming
versions of OS/360, the ACME software is useable
concurrently with other modes of operation.
The ACME compiler will be discussed fully in a
505
future paper, and hence will be only briefly discussed
here. The compiler is for a subset of PL/1 that includes many of the most useful features of the language.
It is incremental; that is, it compiles one statement at
a time and a program is always capable of execution.
It compiles all the way to machine language, and thus
produces relatively efficiently executing code. All system-user communication is processed by the compiler,
hence the system command language is a subset of the
compiler language, with identical syntax. Also included
in the compiler language are text-editing functions for
modification of program texts. For such processes as
input/ output, subscript range checking, and the computation of mathematical functions such as SIN, COS,
and standard statistical procedures, the compiler generates calls to a resident library of subroutines. Some of
these subroutines are also written in FORTRAN, and
in fact use the IBM-supplied FORTRAN subroutine
library for such things as input/output formatting.
Resource allocation consists mainly of memory allocation and time-sharing. Memory is allocated to users
in 4048 byte (1024 word) quantities called pages.
When a user has logged in he is assigned one such
page in which his file names, etc., are kept. For programming two more pages will be assigned for program and data storage. More pages are assigned as they
are needed during the compilation of his program.
Memory for object-program arrays is not allocated
until each array is referenced during execution. Hence
there is some saving in memory during the time a user
is creating his program. It is not necessary that the
pages for a user program be contiguous in memory.
Hence the problems of memory allocation are greatly
simplified.
Because most of the ACME software was compiled
under H-Ievel FORTRAN, which is not capable of
producing re-entrant code, allocation of time to users
is not done in the usual manner. Instead of switching
from one user to another at the end of some arbitrary
time interval, switching is done only at so-called "reentrant points." A re-entrant point is defined as a
point at which:
1. All required information concerning the current
user is located in storage peculiar to that user.
2. The next operation to be executed on behalf of
the user is a call to a subroutine which will not
return to the calling routine.
These two conditions are sufficient to insure a somewhat limited, but nevertheless adequate form of reentrant programming. The scheme relies on the fact
that the H-Ievel FORTRAN compiler generates a prologue which is always executed upon entry to a subrputine. This prologue initializes information internal
506
Fall Joint Computer Conference, 1967
to the subroutine, but peculiar to the current invocation
of the subroutine.
The necessity of limiting switching to only certain
points leads to the interesting situation in which the
current user graciously yields his control of the machine, rather than having it wrested from him. However, proper etiquette in this regard is assured in several ways.
1. When a user is compiling a program, the structure of the compiler assures a reasonable discipline for user switching.
2. All requests for input/output activity require a
yield. .
3. A check is built into the code generated by the
compiler at each GO TO and END statement
for the end of a time interval. A yield will result
if the time interval has elapsed.
In the process of yielding, a "resume routine" is indicated. This routine is entered when the user is next
given control. Yields that accompany input/output requests generally specify a wait until the input activity
is completed, due to the interactive nature of most
system use. Users currently are served in strict order,
on a round-robin basis. There is some probability that
a priority scheme may be introduced later, if experience
indicates that high data-rate experiments cannot be
served with the round-robin scheme.
Because one of the major purposes of the ACME
system is information storage and retrieval, special data
management pro:edures have teen designed to facilitate
these operations. User data, and programs, are stored
in data sets on the data cell. Data sets are ordinarily
catalogued by user name, then by a project name, and
finally by a user assigned data set name. When a data
set name is mentioned in a program, it is automatically
qualified by the user name and project name supplied
at log-on time. This automatic qualification is overridden by explicit qualification of the form USERNAME.PROJECTNAME.DATASETNAME. This method of
data set naming is essentially identical to that used by
OS/360, although OS/360 cataloguing procedures are
not used. In addition, certain public data sets will be
available. Among these will be a set of standard useroriented programs.
Within the data sets, data is stored in the form of
records. Records may be stored sequentially or randomly and may be retrieved sequentially or randomly.
Records may be of arbitrary length. Data items are
stored and retrieved from records by name. ~ence,
data items may be retrieved in an order different from
the one in which they were stored. Moreover, fewer
data items may be retrieved than are stored in a given
record. This mode of operation is unlike that used in
most current programming systems, where item order,
not name, is significant. It is felt that the mode chosen,
although somewhat less flexible, is much more in line
with the thinking of the non-computer oriented personnel who will be the prime users of the ACME
system.
The terminal input! output procedures used by the
ACME system were also designed by the ACME Project. Output from the system is generally in the form
of a message and a prompt. The message portion is
the result of the last operation performed and the
prompt portion is used to indicate what should be done
next. A question mark (?) is used to indicate the end
of the output. For example, during the log-on procedure
the output from the system is the prompt NAME?
The user then supplies his name. If the name is not
acceptable, the system types an error message and reprompts NAME? During compilation, the system
prompts the line number of the next line when compilation of the preceding line is successful. If the compilation of the preceding line is not successful, the compiler supplies an error message and re-prompts the
previous line number. Messages are generally quite
long, so that a maximum amount of information can
be conveyed. If a user recognizes a message and does not
want to see it again in its entirety, he pushes the ATTENTION button on his terminal, which causes an
ellipsis ( . . . ) to be typed and the rest of the message
to be skipped.
The prompt portion of a message can usually not
be ignored because it remains in a buffer as part of
the user's next input. All prompts are recognizable
to the compiler as commands, with the question mark
treated as a blank. Hence, if PROJECT? is prompted
and the user types DOGWEIGHTS, the input to the
system is PROJECT DOGWEIGHTS. In fact, the system forgets what it has typed out; it only looks at the
next input line to decide what to do next. If the user
wishes to ignore a prompt, he may back-srace over
it, which causes it to be deleted, or he may push the
ATTENTION key which causes the current input line
to be ignored and a prompt of ? to be typed. Similarly,
in the case of some syntax errors, the compiler merely
prompts a corrected version of the statement. If the
user wants to use the corrected version, he merely types
carriage return, which causes the prompt to be used
as input.
Real time input/output was also designed to maximize user convenience. With the exception of the 270X,
which is still in the developmental stage, all real-time
input! output is generated by satellite computers, either
the ACME 1800 or the remote small computers. A communication protocol has been established for all transmission between computers. The protocol is designed
An Advanced Computer System for Medical Research
around the concept of a conversation between the main
computer and a satellite computer that can be initiated
by either party. Once initiated, the conversation continues until there is no more data to be transferred in
either direction. Because some satellite computers, such
as the 1800, may be processing several different sets
of input/output concurrently, provisions have been
made for several concurrent conversations between the
same pair of computers.
As far as the user is concerned, real-time input/ output is programmed in exactly the same way as datafile input! output. Each real-time input/output path is
treated as a data set by the ACME system. The data
sets are catalogued in the same way as data-file data
sets and accessed by the same set of commands. Data set
attributes, catalogued with each data set, allow the
software to distinguish between real-time and data-file
sets. Conversion is automatically done by the ACME
software to provide compatability between satellite
computer data formats and ACME system data format.
The subroutine library consists of commonly used
subroutines for such operations as statistical analysis,
graph plotting, etc. Although some subroutines may be
written in the ACME compiler language, the majority
will probabily remain in FORTRAN or assembly language, due to the higher object program efficiency that
results. The most commonly used routines will always
be core-resident, with direct linkage provided by the
ACME compiler. These are not re-enterable, so their
execution time must be small. Less frequently used
subroutines, or subroutines with long execution time,
will be dynamically loaded and assigned to individual
users. When these routines are no longer needed, the
memory they occupy will be released and made available to other users.
CONCLUSION
As of July, 1967, all of the hardware described in this
paper is operational, with the exception of the Sanders
Associates displays which have not been delivered yet.
Connection has been established between the 1800 and
two research laboratories. One small computer has been
connected to the system. The ACME compiler is almost
complete. Timing tests have indicated that its object
code efficiency compares favorably with that of similar
compilers. The resource allocation software is complete
and allows time-shared use of the system. The terminal
input/ output routines also have been completed. The
data-file management routines allow only program storage, due to a delay in IBM software support for the
data cell. The real-time input! output routines are in
an advanced stage of development, and currently allow primitive real-time input/output. The subroutine
507
library is partially complete, with work continuing to
expand its scope.
It is hoped that this paper will provide encouragement to those who believe that a successful time-sharing system is possible and is realizable by an organization with limited resources.
At a time when many highly-touted time-sharing
systems are proving to be less than successful, the
ACME Project is quite proud of its accomplishments.
If there is any lesson to be learned, it is that a small
group, with specific and well defined goals and a
highly cooperative user community, can quickly and
effectively provide a needed service to that community.
ACKNOWLEDGMENTS
The planning work was sponsored by a Josiah Macy
Foundation planning grant and further funding has
been granted from NIH (Grant No. FR-00311) and
Macy Foundation. Much credit for these ideas and
procedures goes to other computer installations and
other people, notably project MAC at M.LT., MEDLAB at the Latter-Day Saints Hospital in Salt Lake
City, the Computer Center and ARP A project at
the University of California, Berkeley; University of
California San Francisco Medical School; U.C.L.A.
Health Sciences, etc., and of course the Computation
Center and the Computer Science Department of Stanford itself.
REFERENCES
H D HUSKEY W WATTENBURG
A basic compiler for arithmetic expressions
Communication of the ACM January 1961
2 W KEESE H D HUSKEY
An algorithm for the translation of Algol statements
Proceedings of the IFIP Congress 1962
3 F J CORBATO et al
The compatible time-sharing system
MIT Press 1963
4 G WIEDERHOLD
A proposal for a simple system allowing direct access to
the computer
Internal Paper Berkeley Computation Center 15 May.
1963
5 J H SALTZER
TYPSET and RUNOFF
Memorandum editor, MAC Memo 193-2 11 January
1965
6 G WIEDERHOLD
Student, a fast FORTRAN IV compiler
Internal documentation Berkeley Computation Center
1965
7 J SHARP C GRAM B PANZL
Student language manual, The language and the processor
Department of Electrical Eng and Computer Science
Berkeley 1 March 1966
508
Fall Joint Computer Conference, 1967
8
H BERG et al
Report of the SHARE Advanced Language Development
Committee 1 March 1964
9 A J SCHERR
Time sharing measurement
Datamation February 1966
lOG WIEDERHOLD
A summary of the ACME system
Proceedings of the ONR Computer and Psychobiology
11
12
Conference Monterey 17 May 1966
G Y BREITBARD et al
ACME notes
Internal documentation Stanford Computation Center
ACME Facility November 1965 to present
V WIEDERHOLD
How to use PLI ACME
Document No 80-50-00 Stanford Computation Center
15 July 1967
A panel discussion
The impact of new technology on the
analog hybrid art - I
G. A. BEKEY. Chairman
University of Southern California
Los Angeles, California
Present day hybrid systems are characteriz~d by
increasingly sophisticated software requirements. The
first attempts at creation of usefulanalog-digital computer systems were faced with a multitude of hardware
problems associated with communication between discrete and sequential machines on the one hand and
continuous and parallel machines on the other. Now,
however, since the hardware marriage has been successfully consumated, a multitude of software problems remain. This panel will concentrate on the most
important of these problems. Position papers by each
of the four panelists are presented below.
common to a vast majority of hybrid problems that
lend themselves to standardization through an executive
routine. This would include such operations as data
input and output, bilateral problem control (i.e., the
sequencing ~f the analog computer through modes from
either the digital computer or the analog computer),
and problem debugging procedures.
Hybrid executive software is aimed at solving these
problems. There is a wide diversity of executive routine
philosophies and implementations, reflecting, perhaps,
the fact that no two hybrid installations are the same
either in a systems sense or in terms oJ the modes
operandi of the facility.
This presentation reviews the general state-of-the-art
in hybrid executive software and some of the major
considerations one faces when initiating the development of software of this type.
Hybrid executive and problem control
'software
by E. HARTSFIELD
TRW Systems
Redondo Beach, California
Diagnostic software for operation and
maintenance of hybrid computers
Hybrid executive and problem control software
provides features quite analogous to those provided in
Monitor systems associated with stacked job oriented
data processing centers. The major difference is that
a hybrid executive routine stresses execution time
utility as opposed to the compilation and assembly
time utility emphasis of stacked-job Monitors. If one
accepts the proposition that hybrid simulation is an
extension of analog simulation, then the need for a
software system that facilitates communication between the user and his program is brought clearly into
focl,ls.
Unlike a data-center mode of operation, where the
user submits his job to an operations desk and does not
receive results (good or bad) for several hours, a hybrid
user operates on the same program for several hours at
a time. In addition, there are a number of operations
by R. E. LORD
Comeor/ Astrodata
Anaheim, California
Diagnostic software is based upon the premise that
programmers occasionally make mistakes and that
sometimes hardware behaves less than ideally. The
major problems in producing good diagnostics are:
(1) how does one find the errors and (2) once they have
been found, what does one do about them. In the case
of maintenance software, the problems are primarily
in finding the errors. Once found, the course of action
is fairly clear: report it. In the case of operational diagnostics, the course is not quite so clear. For those
operations that occur during a time critical phase, one
must examine whether there is time available for
509
510
Fall Joint Computer Conference, 1967
complete diagnostics. or these cases, it is often better
to build diagnostics into hardware than it is to rely on
software. During non-critical phases of a problem, complete diagnostics can usually be performed and errors
readily detected. The problems here are in determining
what action to take. In general, batch processing takes
the view that any error serious enough to diagnose for,
is serious eI1'ough to cause an abort. The hybrid problem however, generally involves a high degree of manmachine interaction and hence, upon diagnosing an
error, one should determine if the user can fix or
quickly program around the error. If this is the case,
then a complete report of the error should be made.
Only as a last resort should an abort be initiated.
A large multi-console system for
hybrid computations:
software and operation
by C. K. BEDIENT
Lockheed Missiles and Space Company
Sunnyvale, Ca lifornia
In the first quarter of 1966, Lockheed Missiles and
Space Company completed negotiation for a new
hybdd computer system. This system contained four
cr 5000 analog computers and two intracoms manufactured by Comcor, Inc. It also contained a 6400
digital computer system manufactured by Control Data
Corporation. Astrodata, the parent company of Comcor, was given complete system responsibility including
software development. This discussion traces this software development and the resulting operating system.
To implement this software development, Lockheed,
Control Data, and Astrodata were each to supply programming support. To direct the programming effort,
Astrodata retained Dr. Ralph Dames of Spectrodata.
The first part of the discussion reviews the features
of the 6400 computer and the Chippewa operating system. It reviews the modifications required to this system to give it the features required to do hybrid computation. Tracing the design of the linkage equipment
it is shown how features of the hardware and software
are used to advantage to produce the final integrated
software hardware package. This includes a description
of interrupt processing, pattern input-output, and the
effects of multiproblem usage.
The second part of the discussion shows the organization of a simple problem and demonstrates its operation on the system.
Other features of the system are briefly outlined,
including:
1. Fortran Library
2. Display System
a. Job Control
b. Variable Display
c. Source Modification
d. Input/Output
e. Preventive Maintenance
f. Engineering Aids
g. Hybrid Utility
h. Datafile Display
3. Preventive Maintenance
4. Automatic Problem Verification
Simulation languages and the analog
hybrid field
by JON C. STRAUSS
Carnegie Institute of Technology
Pittsburgh, Pennsylvania
Languages to facilitate the representation and simulation of continuous dynamic systems on digital computers are currently related to analog/hybrid computation mainly in the sense that they both are concerned
with- the same problem class (with the possible exception of real time simulation). There is, however, some
indication that current work will lead to general hybrid
programming languages. This brief position paper describes some of the current work in simulation languages, its relation to previous work, and its potential
relation to the analog/hybrid field.
The early simulation languages were very much influenced by the outlook and objectives of their analog
computer oriented designers; i.e., the work was motivated by the need for accurate dynamic check solutions. As digital computers become faster and less
expensive, these analog oriented simulation languages
were increasingly employed for stand alone digital simulation. The justification was generally based on the
greater accuracy, accessibility, and result reproducibility of the digital computer coupled with a much
smaller relative setup cost and time for one shot simulations.
Due primarily to the orientation of their designers,
most of the early simulation languages provided for
continuous system simulation by simulating the operational device characteristics of the analog computer;
system simulations were programmed by, in effect,
describing an analog computer wiring diagram and
pot setting sheets to the computer. It was not until
very recently that simulation language designers began
to take advantage of the fact that the simulations are
The Impact of New Technology on Analog Hybrid Art-I
being performed on a digital computer with capabilities
that are just not present on the typical analog. The
most recent and certainly the most carefully designed
simulation language is CSSL (the Continuous System
Simulation Language); it is the product of several years
work of-the SCI Simulation Software Committee. CSSL,
although not presently implemented in its entirety,
serves as an excellent basis for discussion of simulation
languages, their relation to, and their ultimate effect on,
the analog/hybrid simulation field.
CSSL was designed primarily as a digital simulation
langu,age but care was taken to provide for future
upwards compatible expansion to a complete hybrid
programming language. The main contribution of CSSL
lies not in its detailed syntactical structure but rather
in the underlying ideas that it presents. These include:
1. The explicit recognition of the different requirements of simulation in general; namely: model representation, programmed experimental control, interactive control/communication, and problem oriented
operators to describe their problems.
2. The need for a flexible model representation
scheme so that investigation in different fields can use
the same language system with different sets of problem oriented operators to describe their problems.
3. The concept of programmable structure that permits and, in fact, encourages use of the same simulation
511
system by users, and for problems, varying greatly in
sophistication.
The question at hand is how does all this relate to
the analog/hybrid field. The following observations are
pertinent if somewhat controversial:
1. Simulation Languages and all digital simulation
will continue to find greater application areas now considered to be the exclusive province of analog and
hybrid computers. This trend will be accelerated by the
development of graphic consoles and time shared programming techniques'that will allow the user to achieve
the same or perhaps even greater degree of communication with his problem that he now enjoys with analog
computation.
2. As evidenced by the design features of CSSL,
development of HSL, a dialect of CSSL, by EAI, and
recent indications in the literature (e.g., R.T. Dames,
Simulation, March 1967), simulation languages will
find increased application as hybrid programming languages; i.e., they will be used to program the digital
portion of a hybrid problem.
3. If the interest in, and need for, hybrid computation continues to increase, the current unpleasant task
of getting a problem on the computer will be automated through development of hybrid computer analogs of APACHE. Such work could be readily mechanized in the general framework provided by CSSL.
A panel discussion
Information services and communications
(computer utilities)
E. M. GRABBE, Chairman
TRW Systems
Los Angeles, California
With the continuing increase of computer installations utilizing some form of data communication, experience is being accumulated on the remote terminal
operation of computer and information services for
interactive usage, batch processing and other data
retrieval services. Important factors in the future commercial development of such services are the availability
and cost of communication circuits and terminal equipment. Interest has recently been focused on these
areas by the Federal Communications Commission's
inquiry into the "regulatory and policy problems presented by the interdependence of computers and communications service facilities."
The goals of the panel will be to clarify the interdisciplinary pro:lems and relationships between computers and communications which, as one panel member stated, "have placed the computer and communication industries on a collision course." Specific areas of
information services to be reviewed in relation to communications are: experience in operating hardware
and software systems, interface requirements, system
economics, communication circuits and public policy.
Position papers submitted by three of the panel
memters follow.
Time-shared information systems:
market entry in search of a policy*
by MANLEY R. IRWIN
University of New Hampshire
Durham, New Hampshire
I. INTRODUCTION
Recent developments in computer hardware and programming now enable several users to share the stored
information and logic capability of data processing
machines. The subscriber, no longer adjacent the computer, may access the computer's logic and memory
via telephone lines tied to the data center. Indeed,
the combination of data centers, communication lines,
and termnial equpiment form the elements of what
some forecast as a new industry, time-shared services
or what others call the computer or information utility.
Services arising out of this industry includes bibli-
ographic retrieval, stock quotation, hotel reservations,
legal indexing, market reports, banking by phone, hospital information systems, common data files, program libraries, to mention a few. Such services soon
promise to be international as well as domestic in
operation and scope.
Last year, the Federal Communications Commission
initiated an investigation into the policy implications of
computer time-shared, operations. 1 The Commission
seeks to determine its statutory obligations given what
it terms the "growing interdependence" of computers and communications. This paper proposes to examine one of the issues posed by the Commission's
investigation. Specifically, we will (1) state the regulatory issues as the Commission views them; (2) discuss
the background events that prompted the inquiry;
and (3) evaluate some of the competitive issues associated with time-shared computer services. We will
conclude that the ground rules for market entry are
at stake in the FCC's investigaiton.
II. The investigation
The Federal Communications Commission announced its computer inquiry on November 10, 1966.
Some of the Commission's questions dealt with the
adequacy of tariffs, rates, and customs practiced by
the communication carrier industry. Other questions
focused on the issue of privacy and telephone wiretapping incident to the growing concentration of information. The central if not the most controversial
issue,. however, settled on the question of the Commission's regulatory obligations. Specifically, the
Commission asked:
The circumstances, if any, under which any of
the aforementioned services (data processing, special information services, message or circuit
switching) should be deemed subject to any regulation pursuant to the provisions of Title II of
the Communications Act.
(1) when involving the use of communications facilities and services;
(2) when furnished by an established communication common carrier;
(3) when furnished by entities other than established communication common carriers.2
513
514
Fall Joint Computer Conference, 1967
These questions may have caught some observers
by surprise, particularly members of the computer
industry. However, a review of the factors contributing
to the inquiry suggests that the FCC may have had
little choice in exposing these issues for public discussion. In fact, the Commission's attempt to distinguish between "data processing" and "communications"
may prelude a more general policy search in the growing field of time-shared computer services.
Ill. Source of investigation
First, what prompted the investigation. Obviously
the inquiry resulted from the interplay of many factors. However, four can be identified as being singularly
important: (1) the Bunker-Ramo case, (2) the IBM
letter, (3) dinersification efforts of Western Union, a
domestic telegraph carrier, (4) diversification efforts
of ITT Worldcom, an international telegraph carrier.
The background of each follows.
A. The Bunker-Ramo case
. The first issue, determining the content of a communication common carrier service, erupted in a service offering by the Bunker-Ramo Corporation. BunkerRamo sells a stock quotation service to brokers, bankers and insurance companies. Stock information is
gathered from the main Exchange floor in New York,
transmitted and stored in Bunker-Ramo's regional
offices. Computers in these offices then distribute this
information via telephone lines to the firm's customers
throughout the country. By means of desk units supplied by the company, subscribers query the computer
for a host of market security information. BunkerRamo, designating its service as Telequote III, operated
an information retrieval system on a real-time or
instant use basis.
Under this system, Bunker-Ramo provided its subscribers with stock quotation service, desk display
units, and telephone communication circuits, all as a
'total package. Although Bunker-Ramo owned the
former two units, it obviously did not own the latter.
Communication lines were necessarily secured from the
communication common carrier industry and then resold by Bunker-Ramo to its customers.
As a rule, the common carriers do not lease communication lines to firms who resell them. The carriers hold such activity subsidizes their competition,
dilutes revenues, and ultimately translates into higher
rates for their telephone or telegraph customers. The
carriers argue, moreover, that the exchange or routing
of messages among or between persons constitutes the
essence of "communications" as conventionally defined.
This function is obviously confined to regulated communication firms.
There are, however, exceptions to this policy. Reselling of communications is permitted under the carriers' authorized user tariff. A firm may resell circuits
if the carriers determine that both the firm and its
customers are engaged in the same business activity.
Bunker-Ramo customers, stockbrokers, etc., qualified
under the authorized user tariff. Thus, the firm acting
as literally a broker between its customers and the carriers, sold leased communication facilities. 3
The announcement of a new stock quotation service,
Telequote IV, reopened not only the question of
definition but also the question of circuit availability.
In contrast to Telequote III, Telequote IV grafted
electronic message switching to the computer's capability of data processing, message switching that permitted
brokers to place, execute and confirm stock orders
between their offices. The carriers agreed that the message switching element constituted a new and crucial
element to Bunker-Ramo's service.
Specifically, the carriers held that the store and forwarding of information constituted a tariff violation .
Stated differently, Bunker-Ramo's service embraced
enough communications so as to infringe upon an
activity reserved to regulated entities.4 The implication was strong that if communications was BunkerRamo's intent then the firm ought to apply for a
franchise of convenience and necessity. In the meantime, the denial of communication lines effectively
foreclosed the operation of Bunker-Ramo's new service.
This impasse prompted Bunker-Ramo to issue a
letter of complaint to the FCC. The firm granted that
its message switching of administrative data might be
interpreted as the transportation of communications.
However,
Such transportation rarely occurs as an incident
to another primary busines.s and although a charge
is collected for the overall service, the incidental
transportation is not supplied with the purpose to
profit from whatever transportation service may
thus be performed. 5
In short, Bunker-Ramo invoked the primary business
test.
To emphasize the incidental nature of Telequote
IV's communications, Bunker-Ramo revealed a breakdown of Telequote IV; 84% was assigned to services
of stock quotations; 10% assigned to orders and
confirmations; 1 % to market opinions, and 3 % to
customer accounting. The controversial segment, the
routing of administrative data, consisted of some 26 %
of the entire stock quotation service. 6 Clearly, argued
Bunker-Ramo, this small portion did not constitute
communication activity in its generally accepted sense;
Information Services and Communications
and clearly such activity should not condemn BunkerRamo's entire service as illegal.
Ultronics Systems Corporation, a competitive supplier of stock quotation service, volunteered its observations to the FCC. Ultronics submitted that the Telequote IV service embraced enough message switching
or communications so as to indict the entire service
as a regulated communication activity.7 Interestingly
enough, this position paralleled Western Union's thesis
that communication rather than data processing was
actually the dominant element of Bunker-Ramo's contemplated service.
In the ~nd, the Telequote IV dispute did not require
the Federal Communications Commission to promulgate a formal ruling. Subsequent negotiations between
Bunker-Ramo and the Bell Telephone System (AT&T)
found room for compromise. Bunker-Ramo agreed to
eliminate the 2 % administrative segment of its service;
Bell agreed to lease circuits under its authorized user
tariff. As a result, the policy issues latent with this
disr,.ie were merely postponed.
B. The IBM letter
The FCC's inquiry was also identified with an open
letter submitted to the Federal Communications Commission by IBM. 8 The letter was both cautious and apprehensive. IBM cegan by drawing a sharp distinction
between the terms "communication" and "data processing." Data processing or the transformation consisted of analyzing, classifying, correlating, sorting,
calculating, summarizing, and producing records and
reports. By contrast, communications embraced the
transportation or transmission of information by wire
or radio under the Communications Act of 1934.
Lest the Commission confuse the two, IBM observed:
If intelligence is sent from A to a computer
and transformed by the computer and the message
then goes forth from the computer to B containing the transmitted intelligence, it is clear that
there has not been transmittal of a message from
A to B through a computer. 9
The issue in the Bunker-Ramo case, however, was
not solely one of determining the appropriate mix
between data processing and communications. The
parties generally agreed that Telequote IV embraced
the- electronic routing of message communications.
The question, however, turned on the status of switch~
ing activity performed by a firm not licensed as a communication carrier. IBM suggested the primary business test as a guide to resolving any such determination.
And if communications were indeed incidental, suchactivity did not qualify as regulated, limited exclusively to telephone or telegraph companies.
515
What about the reverse situation, the case when a
regulated carrier engages in data processing? Obviously aware of Western Union's diversification into data
processing services, IBM cited an FCC decision with
respect to the telegraph company's flower service.
Though part of its communication plant is so employed, Western Union does not file tariff schedules
on the flower segment of the service. This policy,
argued IBM, provided sound precedent for Western
Union's or any carrier's move into unregulated, data
processing services. lo
In sum, IBM counseled the FCC to consider the
primary business test when non-regulated firms find
themselves engaged in regulated or message switching
activities. By the same token, IBM submitted that data
processing services supplied by regulated entities does
not automatically redefine that activity as a regulated
one.
c.
Western Union's diversification
Since telephone or telegraph lines are by definition
critical to remote data processing services, it was perhaps invitable that the communication carriers would
find computer services an attractive source of market
qiversification. Indeed, Western Union's concept of a
national information utility, a blending of computer
and communication faciltes, epitomized that diversification.11 To this end, the telegraph' company announced the computerization of its Telex switching
centers, the establishment of lata processing service
centers, the announcement of specific data processing
services-legal index, employment service, among
others-and the introduction of a management information system available to commercial and government users.
Western Union's entry into information services
originated with its government contracts. The Autodin
contract, for example, consisted of a joint data processing and message switching system to the Defense Department. A similar service, the Advanced Record System, was also leased to the General Services Administration; a system whereby the telegraph company has
been responsible for the automatic dial nationwide
circuit switching system, three message switching centers, and the supply and maintenance of software and
message switching capability. (The computers route
multiple address messages-, recognize priorities, and
hold messages for specific delivery time.)
The seeds of controversy inherent-in a regulated firm
engaging in a non-regulated activity commenced with
these government contracts. As early as August 1964,
the FCC requested Western Union to justify why the
data processing segment of the Advanced Record Sys-
516
Fall Joint Computer Conference, 1967
tern, was excluded as a tariffed service. The Commis-'
sion wrote:
We are advised that you do not intend to include in your tariffs on file with the Commission
charges for off-line processors furnished in connection with this system. It is requested that you
advise us as to what you believe to be the legal
justification for furnishing this item of equipment
without having charges therefor on file in your
tariffs.12
Later, the question of tariffing and contracting arose
again with Western Union's announcement of its management information system for Dun & Bradstreet
and Blue Cross.13 Finally, last year the FCC urged
the telegraph company once again to explain its policy
with respect to its data processing services. 14
Western Union's response attempted to place its
new activities in perspective. The telegraph company
reminded the Commission that it compted directly with
firms whose computers were replacing Western Union's
torn-tape switching systems. Rivalry between the carriers and computer firms, explained Western Union,
was immediate and direct in the GSA Advanced Record System contract; and Western Union argued that
had it tariffed its service, the telegraph company would
have been placed in an untenable position vis-a-vis its
competitors.
To illustrate the need for flexibility and hence
tariff policy, Western Union recalled that its original
bid to GSA had been high. A downward revision occurred through the cooperation of Univac's Division
of Sperry Rand-a revision that resulted in a bid that
ultimately secured the contract for the telegraph company. Western Union continued:
GSA expressed concern that since the Western
Union bid was of a tariffed nature, the quoted
price was not firm for (a) tariffs would be necessarily filed months after the award of a contract,
and (b) regulatory action would be in effect bring
about a superseding of the contract. Western
Union was therefore advised that it could have a
contract only on the condition that a firm fixed
price contract for five years could be offered, and
had Western Union not acceded, GSA would have
made a contract award to ITT.Is
. What was true for the government sector was
equally true for the private sector. To meet market
competition, Western Union responded that its data
processing activities need not be subject to regulation
despite the fact that the company itself was a regulated
carrier.
.
Finally, Western Union elicited restrained enthusiasm
from the primary business test as a policy guide to
determining the communication activities of data processing firms. The primary business test, observed the
telegraph company, threatened the very concept of
regulation.
Such companies as IBM would always be in
the position of furnishing a part of the communication business on an incidental basis and hence,
would never be subjected to regulation. The safeguards of the utility concept would thus ce
eroded. 16
In specific reference to Telequote IV, Western
Union was concerned that the element of direct communication among the subscribers would persist. Although the compromise between Bunker-Ramo and the
Bell System may have been workable to Bunker-Ramo,
it was less than satisfactory from Western Union's
standpoint. 12
D. ITT WorIdcom's diversification
A third element that impelled the Commission's
Notice of Inquiry was associated with developments
on the international scene, the international communication carrier. Last year, ITT Worldcom, a subsidiary
of International Telephone & Telegraph and an overseas record carrier, filed a tariff on a computer message switching service .The tariff, designated ARX
(customer data re-transmission) excluded individual
circuits and terminal apparatus. Rather, the subscriber
was billed on the number of messages routed through
ITT's computer switching system.
The tariff encountered opposition immediately. 18
Western Union, for example, objected that as an international carrier, ITT was diversifying into the domestic communication market competing with and eliminating Western Union's torn-tape relay switching systems, thus diluting needed revenues from the telegraph
company. Western Union International Telegraph Company, an overseas record carrier, joined Collins Radio,
a manufacturer of computer switching equipment, in
voicing further objections to the ARX tariff. Western
Union International asserted that the tariff was unclear
and ambiguous; and Collins Radio suggested that the
tariff was underpriced and hence, non-compensatory.19
ITT Worldcom acknowledged that some of its
switching systems would be located within the United
States. However, as long as its customers leased one
private line circuit overseas, domestic switching was
permitted under the Communications Act, Section 222.
(The act defines an international carrier as one whose
major portion of traffic and revenues is derived from
international telegraph operations.Yo
Significantly, ITT Worldcom asserted that computerized message switching was an activity subject
Information Services and Communications
to the jurisdiction of the Federal Communications
Commission. Indeed, since the ARX tariff had been
filed under this assumption, ITT Worldcom requested
that the FCC expedite its approval of the ARX service.
Its customers, explained the carrier, might seek alternative suppliers of automatic switching, suppliers not
subject to FCC jurisdiction. Thus, on October 1,
1966, the Federal Communications Commission denied
petitions for tariff suspension and ITT Worldcom's
service took effect. 21
As if matters were not complicated enough, RCA
Communications, an international record carrier and
a subsidiary of RCA, inaugurated a service called
Aircon devoted to the needs of international air carriers. Aircon, a computerized message switching service, also contemplated the processing of seat reservations, inventory, accounting, data on cargo, freight
information, as well as a wide variety of administrative
services. RCA's service was thus dircetly competitive
with that offered ty ITT Worldcom. The difference
tetween the two was crucial; RCA refused to file
a tariff.
ITT Worldcom lost no time in urging the FCC
to force RCA Communications to file an appropriate
tariff schedule. As requested, the FCC asked for a
statement of policy from RCA Communications. The
carrier replied that its automatic information reservations service would not only be at a competitive disadvantage with those provided by Collins Radio, but
filing a tariff would prejudice the issues posed in
the FCC's computer inquiry which by this time had
been announced. Thus, RCA Communications observed:
It must maintain a competitive position that
would enable it to compete effectively on a
meaningful basis with non-regulated entities.
Beyond this, a tariff filing would afford nonregulated companies an unfair advantage by
exposing the entire Aircon service offering to
their scrutiny while their offerings are beyond
the regulatory purview. 22
Where is the communication-data processing situation as it now stands? First, firms in both industries
do not agree as to the precise limits and hence proper
jurisdiction of data processing and data switching.
Second, the domestic and international carriers are
split among themselves as to what constitutes the
relevant market for data switching; third, the international carriers are divied as to the FCC's jurisdiction over computer switching; and finally, the
question of promotional pricing, and rate levels continue to beset carriers and non-carriers alike.
IV. Policy issues
5 17
A central theme can be detected in the confluence
of events that prompted the FCC's investigation; and
that is the question of establishing ground rules for
market entry and competition. Consider this theme
as it applies to three questions: 1) the leasing of
communication lines, 2) carrier merger policy, and
3) joint cost allocation.
A. Market entry and communication lines
To repeat the obvious, regulated entities are attempting to engage in non-regulated activities, namely
data processing, non-regulated firms are attempting
to diversify into what is commonly regarded as regulated activities - communications. RCA Communications and Western Union typify the former trend;
Bunker-Ramo typifies the latter trend. But as the
Bunker-Ramo case suggests, diversification is not a
reciprocal relationship. The carriers own and su~~ly
the nation's communication circuits, clearly an actiVIty
subject to state and federal regulation. With this as a
base, it may be less difficult for regulated entities to
diversify into unregulated activities than vice versa.
In short, the granting of franchises is slow, expensive
and hardly conducive to market entry for data processing firms.
. . .
What is important is that the carners lease CIrCUIts
to a growing group of firms who pose both as competitors as well as customers. This relationship can
be expected to intensify; and as the Bunker-Ramo
case testifies, market diversification poses no little
problem to the Fderal Communications Commission.
The Commission may find that carriers deny lines to
companies who engage in communication on grounds
that such activity is subject to regulation~ On the
other hand, the carriers may refuse to file tariffs on
their data processing packages on ground of market
competition. This asymmetrical relationship effectively
bars market entry to major candidates who are seeking to offer computer utility services, particularly
if those' firms reside in the non-regulated sector of
the economy. By foreclosing or conditioning market
entry, the structure of this new industry obviously will
be predetermined.
. . ,
There is a deeper problem. RCA CommulllcatlOns
refusal to file a tariff on computer switching suggests
a profound policy disagreement, at least wi~hin the
ranks of the international carriers. At odds WIth both
a domestic carrier (Western Union Telegraph Company) and an international carrier (ITT Worldco~),
RCA Communications apparently assumes that Its
activities now and in the future will be competing
directly with those services offered by non-regulated
entities.
It is clear that the blurring of data processing and
518
Fall Joint Computer Conference, 1967
communications does not lend itself to easy solution.
In this search, the primary business test is an unsettling policy guide. Communication and computer
firms will obviously employ the test to their own
ends, however those ends are defined. That such
a test borders on the arbitrary can be seen in its application. In the eyes of Western Union, flower and
data processing service are "incidental" to communications. Yet the communication industry becomes less
tolerant when the identical test is invoked by the
d~ta processing industry, to wit, the Bunker-Ramo
case.
Thus, the primary business test cuts both ways;
it can be employed to rationalize a movement from
communication to data processing; or from data
processing to communications. And if such a test is
resurrected as a policy guide, it takes little imagination to visualize a backlog of adjudicatory proceedings
in which the adversaries seek the magic number of
49%.
B. Market entry and merger
As noted above, non-regulated firms generally seek
refuge in the primary business test as a means of
avoiding "the burden of regulation and the obligation
of service." But it is conceivable that a data processing firm may assume or perhaps even hope that its
activities are a legitimate common carrier function.
This may occur when a data processing firm merges
with a regulated firm.
Any such consolidation poses two questions. First,
does merger with a common carrier sanction the
conversion of a non-regulated activity to a regulated
activity. The answer is, of course, speculative. The
merger, however, of the Ultronics Corporation with
General Telephone and Electronic Corporation, the
nation's second largest telephone carrier, suggests that
this possibility is very real. 23 Indeed, it was Ultronics
who argued that Bunker-Ramo's Telequote IV encroached upon a regulated communication activity.
Secondly, if movement from a non-regulated to a
regulated status offers a solution to Ultronics, what
options are open to Bunker-Ramo, Scantlin, and other
rivals of Ultronics. Does the existence of direct competition among these firms stimulate what Kaysen
and Turner term "parallel integration." And what are
the implications of these activities in terms of the
long-term environment for computer utility services.
Merger policy, particularly the consolidation of nonregulated with regulated entities, raise provocative
issues in terms of market entry.
c.
Market entry and joint cost
Finally, the straddling of communications and the
data processing package half regulated, half unregulated, conjures major accounting problems associated
with joint costs. Like any regulatory body, the Commission is not entirely unacquainted with the problems
of cost separation. Although it granted the telegraph
company an accounting waiver for the data processing segment of the ARX service, the announcement
by Western Union of its management information
systems for Blue Cross and Dun & Bradstreet prompted
the Commission to inquire as to the feasibility of
separating the telegraph company's communication
activities. In response, Western Union observed:
Certain non-communication activities which
are now clearly incidental to communication activities are expected to become significant in the
future. The whole field of computer applications
and information storage and retrieval is in a
state of development; more important, many
matters such as the method of operation remaining unsolved. 24
Western Union's position of incipiency hardly eases
a problem that is likely to become aggravated over
time. The question of cost separation, in short, will
undoubtedly command the attention of all participants
in the FCC's computer inquiry.
That cost separation is no easy task is demonstrated
by past experience. The carriers generally prove more
receptive to discussions of rate of return rather than
questions of rate structure. Even when the Commission persuades a carrier, as it did the Bell System,
to calculate rate of return on fully allocated costs,
the carrier tends to regard its studies as less than
meaningful for purposes of public policies. 25 Thus,
the search for cost separation standards within the
regulatory sector is fraught with complexity. But
more important, the search for standards applicable
to a firm half in and half outside the bounds of regulation is equally imposing.
Yet, regulatory experience suggests that such separation is crucial. The telegraph investigation indicated,
for example, that the Bell System was not above
emplaying its monopoly markets to carry its competitive markets - all within the regulated sector. 26 No
one doubts that the Telpak tariff has throttled the
innovation of private microwave communication systems. If then, internal subsidization places a continual
burde non regulation, the accounting hazards of a
firm partly regulated and partly unregulated are no
less challenging. To repeat, market structure and rate
structure are inseparable. Both bear on the viability
of market entry.
There is a final issue. The carriers are in one sense
integrating forward, packaging communication lines
Information Services and Communications
together with computer services. At the same time,
the carriers lease circuits to potential competitors the computer industry. Will wholesale, retail rates
distort prices sufficiently in the final product market
to rule out meaningful market competition? Bluntly
stated, will the carriers accord themselves internal line
discounts denied their customers? And if the carriers
lease circuits from themselves or from other carriers,
will such transactions, now apparently residing beyond
the province of FCC jurisdiction, accord the carriers
comp~titive advantages that ultimately spell who survives in the computer services industry?27 Again, market entry rides on these issues, no matter how premature they might appear today.
V. CONCLUSION
In sum, the Commission's computer inquiry is confronted with an imposing agenda of policy questions.
Not .the least is the issue of definition and jurisdiction,
for out of their determinations rests the question of
market entry and market structure. Two options are
clearly open to time-shared computer services: competition or regulation. But these choices apparently
assume that the firm is restricted to the either/or
extreme of data processing or message switching. The
imperatives of technology suggest, however, that the
pure case may be the exceptional case. As the amalgam
of data processing and communications continues, a
third choice, namely de-regulation, may pose as a
policy alternative worthy of consideration. Perhaps
it is unthinkable that a government agency cut the
Gordian knot of regulation with any degree of seriousness. But the solutions to the computer utility question are sufficiently urgent to warrant broadening the
search for unique policy prescriptions.
5
6
7
8
9
10
11
12
13
REFERENCES
Before the Federal Communications Commission. In the
matter of regulatory and policy problems presented by
the interdependence of computer and communication
services and facilities. Notice of Inquiry, Docket No.
6979, November 25, 1966.
2 Ibid., p. 1.
3 Bunker-Ramo letter to Federal Communications Commission, March 12, 1965.
4 Letter from the Western Union Telegraph Company to
the Federal Communications Commission, December 3,
1965.
As we understand the Telequote IV proposal, the
service would be offered to the brokerage industry,
the conclusion is inescapable therefore that under
the proposal, there would be a holding out to the
general public as that term is used in the law of
common carriage.
See also American Telephone & Telegraph letter to the
FCC, September 29, 1965, p. 2.
14
15
16
17
18
19
20
5 19
It would appear that the transmission of communications is at the heart of its (Bunker-Ramo) proposal for 'message switching' services, which services
might prove in fact a most significant element of
Telequote IV. The so-called 'data processing' to the
extent they exist at all in Stich cases might be
deemed ancillary to the transmission of communications. In such circumstances, we believe a conclusion that Bunker-Ramo was not engaged in a
common carried undertaking subject to regulation
under the Communicati-:-m Act would be open to
serious question.
Ibid., p. 3.
Bunker-Ramo letter to Honorable E. William Henry,
Chairman of the Federal Communications Commission,
August 23, 1965.
Letter from Ultronics Systems Corporation to the Federal Communications Commission, January 17, 1966.
Letter from IBM to Federal Communications Commission, February 15, 1966, p. 5.
Ibid., p. 7.
Ibid., p. 6.
Western Union Annual Report 1965, p. 10.
Telecommunications Reports, August 10, 1964, Volume
30, No. 37, p. 19.
We are advised you do not intend to include in
your tariff on file with the Commission charges for
off-line processors furnished in connection with the
system (ARS). It is requested that you advise us
as to what you believe to be the legal justification
for furnishing this item of equipment without having
charges therefor on file in your tariff.
Telecommunications Reports, November 22, 1965, Volume 31 No. 51, p. 14. Western Union states:
The type of computer equipment furnished varies
according to the requirements of each customer.
Depending upon the capabilities of the particular
equipment furnished, such equipment may be utilized
for electronic processing of business data and for
electronic switching of message communications.
The telegraph company also undertakes on request
to provide programming of the computer equipment
on an initial or a continuing basis.
Telecommunications Reports, November 29, 1965, Volume 31 No. 52, p. 3.
Letter from Western Union Telegraph Company to the
Federal Communications Commission regarding computer lease and service arrangements, March 14, 1966,
p. 10.
Ibid., pp. 37-38.
Ibid., p. 34.
In the matter of ITT World Communications Inc.,
Tariff No. 54, June 9, 1966.
Ibid.,' Petitions of Western Union International for suspension; Reply of Collins Radio to reply of ITT World
Communications, Inc. to petitions of the Western Union
Telegraph Company, Western Union International Inc.,
and Collins Radio, Inc.
Ibid.; Reply of ITT World Communications, Inc. to
petitions of the Western Union Telegraph Company,
Western Union International, and Collins Radio, June
16, 1960, p. 5.
520
21
22
23
24
25
26
27
Fall Joint Computer Conference, 1967
Telecommunications Reports, October 3, 1966, Volume
30, No. 43, p. 8.
Telecommunications Reports, February 27, 1967, Volume
33, No. 11, p. 6.
Wall Street Journal, May 16, 1967, p. 14.
Telecommunications Reports, September 12, 1966, Volume 33, No. 40, p. 16.
Before the Federal Communications Commission. In the
matter of domestic telegraph service, Docket No. 14650,
Report of the Common Carrier Bureau.
Ibid., pp. 156-157.
Amendments to Title II of the Communications Act of
1934 (Common Carrier). Hearings before the Commitmittee on Interstate and Foreign Commerce, House of
Representatives, 88th Congress, Second Session, HR
6018, a bill to amend section 203 (A) of the Communications Act of 1934 as amended with respect to the
filing of schedules of charges by connecting carriers;
1965.
Communications servicespresent and future
by W. B. QUIRK
American Telephone and Telegraph Company
New York
There is a fable about a king who was so vain that
he wanted only his image on the coin of the realm.
Therefore, he ordered his goldsmith to make him a
coin with just one side. After many tries the goldsmith confessed that he couldn't make such a coin,
and, in the best tradition of fairy tales, he had his
head chopped off. We can learn a lesson from this
story. Just like a coin, a computerized information
system has two sides communications on one
side of the interface and a computer on the other.
It isn't possible to construct a successful system by
considering just one side. If one tries, he too may
lose his head - or at least go out of his mind.
The telephone industry can speak with experience
about total information systems because the nationwide dial telephone network is in reality a giant
"computerized" information system. Even though the
telephone network provides the user with communications services rather than data processing, the technology used closely parallels that of a general purpose computer system. Even the concept of shared
use, which is the basic building block of the so-called
computer utility, has been used for years in telephone
switching systems.
When I try to convince people that there is nothing
really new in the basic idea of a time-shared information system, I feel like Sisyphus, the legendary king
of Corinth. He was condemned, you may remember,
to roll a heavy rock up a steep hill in Hades, only
to have it roll all the way down again when he got
it near the top. Then he had to start all over.
I'm getting tired of pushing this rock up the hill,
so for the moment I'll concede that perhaps the timeshared information system is something new. But I
still feel sure that many of the lessons learned by the
telephone industry over the years can be applied in
planning and implementing computer utilities. Furthermore, we in the telephone business have an
important role to play in providing the vital communications links which give life to computer utilities.
These communications channels can be compared
to arteries or pipes. A pipe carries a stream of fluid;
a communications channel carries a stream of electrical signals .. A pipe can transport a variety of different liquids, so, too, for communications channels.
Whether what goes in be voice, handwriting, machine
data, still or motion pictures, or Beethoven's Fifth
Symphony - so long as it can be translated into
electrical signals - it can be transmitted.
The world's greatest arterial system for the flow
of data signals already exists in this country - the
nationwide telephone network. Today it reaches over
100 million telephone sets, and each of these locations can be arranged to send of receive data. The
suitability of the dial telephone network to carry data
signals was demonstrated by a series of Bell System
tests in the late 1950's. The results of these tests were
published in the now famous Alexander, Gryb, Nast
Report.
Since then, of course, data communications needs
have changed drastically - and they continue to
change. The capabilities of the telephone industry
are expanding right along with those needs, In fact,
the real success of our business has been its ability
to anticipate the future, to introduce new services
even before users have requested them. For example,
nationwide dial teletypewriter facilities were ready for
time-shared computer use by the time prototype computers were being laboratory tested.
To date, Bell Laboratories has developed over 80
different models of data modems, 40 of which are
now being offered to the using public. These together
with the associated channels and a variety of station
gear .comprise a wide spectrum of data communications services. But we don't stop here. More are on
the way, in a variety of common user and private line
offerings - from narrowband telemetry services at
one end to megabit and higher services at the other.
I'd like to tell you about some of these new services,
paying special attention to communications costs and
interdisciplinary problems.
Information Services and Communications
We talk about service rather than about hardware
because service is what we offer - our end product.
Hardware is only a means to an end. The two most
important ingredients of the services we offer are
innovation and reliability. I want to direct my comments today to the first one - innovation - and skip
the second. But I want to assure you that the telephone industry doesn't skip reliability; reliable service
demands hard work on the part of many people.
We think it's important to provide service rather
than hardware because it allows the greatest scope
for flexibility, economy and innovation. Improvements
in technology can be introduced when and where
they will provide the greatest benefits to users. The
careful phasing in of technological innovations is essential in keeping facilities cost down. Naturally, this
has a beneficial effect on rates, even though cost of
equipment is only one factor in setting rates. Similarly,
by avoiding unnecessary duplication of useful plant,
we also help keep costs down.
There are computer users who want· the telephone
industry to serve them only with the new digital transmission systems, instead of leaving the choice of
facilities to the telephone company. They claim that
this would let them get more data thruput for their
dollar. Such proposals are impractical. They fail to
recognize that perfectly usable plant would be unnecessarily duplicated by such digital systems. To do
so would mean higher cost to the telephone companies.
What's more, they ignore the prohibitively high
amounts of capital needed for such an undertaking.
Others suggest that the best way to lower the cost
of data communications is to establish a totally new
digital network provided by. a new data communications common carrier. This would duplicate the highquality data services offered by present common
carriers. To provide the using public with the same
data service capabilities as available with DATAPHONE service would mean a digital network the
size of the present telephone network!
The advantages of planned, systematic innovations
are demonstrated by the Bell System's T-Carrier program. We are now installing T -1 digital carrier systems
to meet growing communications needs - both voice
and data. These systems, by using pulse code modulation, can transmit up to 1.5 megabits per second or
24 simultaneous voice calls over two regular twisted
cable pairs. We are adding these facilities wherever
the needs warrant it. Today these digital systems are
available only in selected locations, but eventually a
large part of our plant will be of this type. Even higher
speed digital systems are now being developed. A
521
281 megabit per second T -type facility is planned
for 1971.
Our program for introducing T -Carrier is somewhat analogous to the way airlines have phased in
jet aircraft. They didn't immediately junk all their
propeller-driven aircraft. Instead, they added jets where
they could do the most good, to improve service and
to reduce costs. We have the same objectives for
T-Carrier.
Innovations are also being planned to improve the
effectiveness of our existing plant to carry data signals.
For example, a new DATA-PHONE data set, capable
of transmitting 3,600 bits per second over the dial
telephone network, is now in the technical trial stage
and will be available in the near future. A similar data
set has been developed for private line service, but
this one is able to handle 7,200 bits per second. Even
higher speed versions are being planned for later on.
We are constantly looking for new ways to meet
the expanding data communications needs of the public, including the need for lower priced new services.
One such approach, now being studied, is a limited
distance data communications system which uses extremely low-cost data sets and line concentrators.
Such a system looks especially attractive for use with
a time-shared computer at a university campus, in
an industrial complex or within a community or other
limited geographical area. As planned, this system
would be able to serve distant terminals at a somewhat higher cost, but the greatest cost savings would
be for stations within a limited service area.
Data line concentrators and multi-channel data sets
(multiplexors) are being developed. The sub-channels
of these data sets will match the bandwidths of our
other narrowband service offerings. For some time
now, our tariffs have allowed customers to do this
kind of channel deriving on our private line voice
channels, using their own equipment.
At the wide band of the data spectrum we find
requirements for the transmission of occasional high
speed bursts of data - to update computer memories,
to load-share a computer or just for back-up in case
of computer failure. While these and other applications need wideband channel capacity, they can't
justify the costs of full-time wideband private lines.
Recognizing this need, we are now introducing on a
trial basis a service calied DATA-PHONE 50 - a
50 kilobit per second common user switched service.
Initially, it's being offered in Chicago. Additional trial
offerings may be made in other cities in the near future.
These and other planned new services reflect a
continuing research and development effort that began
way back in the earliest days of the telephone. It
522
Fall Joint Computer Conference, 1967
continues today in the realms of both voice and data
communications. Our basic function hasn't changed at
all; the computer and its requirements have simply
added a new dimension to our historic function.
Communications common carriers are the vital link
between the computer and those who use it. We provide the transparent channel to interchange signals.
We provide some input-output devices, such as teletypewriters and TOUCH-TONE telephones. And we
are working constantly with designers of computer
systems to establish plans for total computer communications systems. In this process we are blending
old technology with new-Rembrandt with Picasso,
Bach with the Beatles. If we can be as creative as
they are-or were, computers and communications
will make beautiful music together for decades to
come.
Communication needs of remotely
accessed computer
by W. E. SIMONSON
University of Southern California
Los Angeles, California
There are a variety of problems posed by increasing interest in remote access to computers. These problems are further compounded by the circumstances
facing firms such as mine which have the audacity
to attempt a commercial offering in the face of these
problems. This entire area has been much the center
of considerable attention as a result of the FCC nottce
of inquery. The question has now been raised as to
what are the real demands of a remotely accessed
computer complex.
On the broadest and most philosophical level there
is a problem in the basic environment of a highly
regulated utility, especially in the face of a rapidly
changing technology. The basic proposition that it
is possible for a group of men without substnatial
exposures to intricacies of this business to adequately
regulate communication is suspect. This is not intended as criticism of the job done by the commissioner, but a question of the assignment. It is my- firm
belief that except in the case of natural monopolies
(montonic decreasing cost functions or industries where
the public inconvenience and implied cost of competitive service would be disruptive) regulation should
be aimed at creating and maintaining a comptitive environment. Any attempt to engage in regulation of
substantive issues (specific rates, services) presumes
a competence on the part of regulatory bodies which
is hard to maintain. If such regulation to substantive
issues were felt necessary in the computer industry,
I feel that it would clearly require a specialized agency.
Can you imagine the problems of setting tariff schedules on custom programming or on such things as
a payroll service considering all the variations that
such a service could provide.
Let me develop my thesis in the context of the
services of a commercial time sharing venture. What
are the communication services require by the firm
and its customer? They include terminals, modems,
and lines. Of these, only the lines or channel capacity
are inherently a common carrier function (even though
a common carrier might well do a better job of providing the others). Even here it is p.ossible to consider
private microwave.
Private microwave offers a good case to illustrate
my point. There is a basic economic consideration as
to whether or not it is economic for a user to consider. The competitiveness of microwave can be reduced beyond economic arguments by having ·arbitrary
restrictions on interfacing microwave lines with the
lines of a common carrier. Where interface specifications are met, say by using the common carriers' equipment, in my opinion no objection should be raised.
In another example the ownership of a piece of
communication equipment obviously does not affect
its performance and hence should not be an issue.
If one uses AT&T lines there is no clear reason why
Bell Modems need be used. In the case of private lines
this is no longer true. Restrictions do apply to the
dial-up network. The nee~ for some control of the
signals to go through the switched network cannot
be argued. However, if GTE modems give acceptable
signals coming from an independent telephone company, they should also yield acceptable signals from
a private firm. Similarly, other models that conform
to interface specifications should be acceptable.
This does not mean that I would suggest that
one is better off with non-Bell equipment; quite the
contrary. However, if the prices Bell charged got
too far out of line or their service too inferior they
would than run the disk of losing business. This competitive pressure will do for more to ensure that Bell
offers the best service they are able to than any
amount of FCC inquery. Similarly, individua1 users
might chose to accept- lower levels of safety as far
as reliability is concerned in order to get faster transmission. If AT&T feels that they cannot announce
service, they are not prepared to make generally available, then the customer should have the right to run
the risk of using faster devices within a Bell System
guarantee.
Information Services and Communications
The entire question of technological development is
a serious one. The more closely regulated an industry
is the slower technological progress will tend to be.
The administrative process alone will tend to slow
down the provision of new offerings. Similarly procedures used in rate base calculations can serve to remove
economic incentive from new developments. Since
the development of new transmission technologies, the
savings they can bring have substnatial affects on the
economics of remote computation. It is of particaular
interest to our industry that means be found to encourage the offering of new services that represent
the best state of the art techniques. If there are risks
in the utilization of such s~rvices. or if it is not practical to make them uniformly available, restricted offerings should still be available. In light of recent FCC
decisions on the regulation of AT&T's rate of return,
an examination of incentives to provide new state of
the art offerings may have increased importance.
Let us turn to the areas of message switching. A
question has been raised as to whether message switching is inherently a common carrier function. Although
the channel capacity is purchased from a common
carrier, we fail to see how the public is benefited
by restrictions on the nature of the data sent down the
line. The situation is analogous to having the computer
manufacturers say they will happily sell you a computer but tell you that you are not allowed to run
your payrolls on the machine. For that purpose you
must buy time on their data center machine even if
you have substantial quantities of idle time on your
own computer.
One of the problems in the regulation of major
portions of this area is that the common carrier himself constitutes a court of first resort. If he thinks you
propose a use of his lines which he feels is improper
he will refuse to sell you the lines. Now you carry
the burden of proof and its attendant legal costs.
Minimally, it would appear that it would be only fair
to presume that the service is leigtimate and force the
common carrier to prove that he should be allowed
to discontinue service.
This situation is exemplified in the Bunker Ramo
case where Western Union had refused to sell lines
for a version· of Telequote (because Western Union
felt that features of the service impinged on common
carrier prerogatives). Bunker Ramo then negotiated
a system specification that AT&T felt acceptable.
Though this explication is oversimplified, it bothers
523
us that the common carrier, which in the case of
Western Union desires to be a major competitor in
the service bureau industry, should have the prerogative of deciding whether or not a service violates the
law. We feel that they should be required to sell to
anyone and, if they feel that a particular use is not
legitimate, they should bear the burden of proof as
to why they should be allowed to discontinue service.
This important difference would give the brunt of
the legal cost and risk to the common carrier and
would give the user service during the period of
dispute.
It is clearly a matter of opinion in many cases as to
whether a specific computer service provides message
switching functions. Not only commercial services are
affected, but those of any firm providing service or
communicating ~ith its customers and suppliers. In an
area this unclear it would appear to me that (1) there is
no public interest served by a prohibition of message
switching; (2) if prohibited, any decisions as to the
presence or absence of a violation should be made only
by a disinterested party.
The last item that I would like to suggest, is the desirability of including line standards and transmission
characteristics (envelop delays, noise, etc.) in the tariff
filings (perhaps with deviations by city or major trunk).
This might be helpful in having a standard against
which one could test in case of disputes on the quality
of lines. As I am sure many of you are aware, problems arise when multiple suppliers are involved in an
installation. Hardware suppliers typically blame lines
for most problems and vice versa. Though we have
always found Bell to be cooperative in trying to run
down the source of problems, an objective standard
against which one could test could aid in the resolution
of many of these disputes.
In closing, then, let me summarize by simply verbalizing the hope that these ideas will at least prove sufficiently provocative to stimulate some thought and
new ideas. If so, they will have served their purpose. If
nothing else, the FCC inquiry should demonstrate the
need for considerable thought. Ignoring the specific
illustrations, I have tried to advance the thesis that the
needs of remote computational usage would be best
advanced by as open,.- competitive, and generally unrestricted an atmosphere as can be created. Where regulation or restriction is deemed absolutely essential,
every effort should be made to see that such regulation
does not retard technological progress.
Another look at data
by GEORGE H. MEALY
Computer Consultant
Scituate, Massachusetts
INTRODUCTION
We do not, it seems, have a very clear and commonly
agreed upon set of notions about data-either what
they are, how they should be fed and cared for, or
their relation to the design of programming languages
and operating systems. This paper sketches a theory
of data which may serve to clarify these questions.
It is based on a number of old ideas and may, as a
result, seem obvious. Be that as it may, some of these
old ideas are not common currency in our field, either
separately or in combination; it is hoped that rehashing
them in a somewhat new form may prove to be at least
suggestive."
To begin on a philosophical plane, let us note
that we usually behave as if there were three realms
of interest in data processing: the real world itself,
ideas about it existing in the minds of men, and symbols on paper or some other storage medium. The latter realms are, in some sense, held to be models of
the former. Thus, we might say that data are fragments of a theory of the real world, and data processing juggles representations of these fragments of
theory. No one ever saw or pointed at the integer we
call "five" - it is theoretical- but we have all seen
various representations of it, such as:
V
(101)2
(5)8
5
O.5E01
and we recognize them as all denoting the same thing,
with perhaps different flavors.
We could easily resurrect disputes in medieval philosophy at this point! The issue is ontology, or the
question of what exists. While a Platonist would claim
that even universal concepts, such as redness, exist
independently of whether anyone perceived them
properly or at all, a conceptualist might claim that we
perceive only ideas and they have no existence until
they are perceived. No doubt, both of these gentlemen would quarrel with what I have already said. My
friend the nominalist, however, would permit me to
entertain such notions, so long as I did not insist upon
his treating them as anything but words. * Since it
happens that the following does not depend on any
particular ontology, we can avoid a quarrel by adopting the nominalist's position.
Our plan of attack is to indicate the nature of
the theory of relations, based on the example of genealogical data. This will lead immediately to formulation of our notions about data in general, including
rather precise definitions of concepts such as data
structure, list processing, and representation. These
notions are used in the second part of the paper as
the basis for some remarks and suggestions concerning language and system design.
Toward a theory of data
Relations
To fix our ideas, consider the following example of
genealogical data, taken from Reference 2:
... SNOW ...
4. HENRY (7) [Henry (6), David (5), Anthony (4),
John (3-2), Nicholas (1)], b. 18 Sept., 1810; m. 13
Dec., 1840, Susan Stoddard, dau. of John and
Betsey (Stoddard) Lincoln. She was b. 21 Aug.,
1822, and d. 13 Sept., 1880. He d. 25 April, 1904.
"Master mariner." Resided in house which he
built on So. Main St. south of his father's.
"
Ch., b. in Coh.,i. SON, 17 April, 1841; d. 6 May, 1841.
ii. JAMES H., 28 June, 1842.
iii. ANN FRANCES, 24 Aug., 1844; d. 5 July,
1869, unm.
iv. SUSAN ELIZABETH, 20 Oct., 1846; m. 1
Jan., 1869, Leonard A. Giles, Troy, N.Y.,
She d. 25 April, 1827.
v. RUTH NICHOLS, 29 June, 1848; m. 24
Jan., 1892, James H. Nichols.
vi. CHARLOTTE OTIS, 8 Nov., 1850; m. 5
Mar., 1879, George W. Mealy, Troy, N.Y.
·See W. V. Quine's essay "On What There Is" in Reference 1 for
an interesting and frequently entertaining discussion of these
points of view.
525
526
Fall Joint Computer Conference, 1967
vii. BENJAMIN LINCOLN, 2 Aug., 1853;
d. 24 Jan., 1859.
The above, of course, does not record more than a
few facts concerning Henry(7) Snow, Jr.; we are
already in the realm of symbols. The nominalist is
equally prepared to be told that James H. Snow is a
misprint or that he is alive today. Officially, the nominalist is under no illusions about data: A data base
never records all of the facts about a group of entities; a fact may be recorded with complete or lesser
accuracy; and non-facts may be recorded with equal
facility.
It was, no doubt, the study of genealogical data
that led to the invention of the theory of relations,
which will lead in turn to our. notions about data in
general. Informally, relations are simply a generalization of family relationships, and genealogical data
is one of the older instances of recorded data.
We start with a set of individuals (or any other type
of entity) and a second set, which mayor may not be
the same set as the first. A relation is a correspondence between members of the two sets. For instance,
son-of, children-of, father-of, ancestor-of, sib-of,
and the like are all relations, as are birth-date-of,
occupation-of, age-of, residence-of,. marital-status-of,
etc. The children-of relation, in the case of the Snows,
is a correspondence between Henry (7) and his children, Henry (6) and his, and so forth. To be somewhat
more accurate, there are at least two possible childrenof relations; due to the possibility of remarriage, for
instance, the set of children of a given.pair of spouses
is not necessarily the same as the set of children
of a given individual of that pair. This is to say that,
in general, relations are correspondences between
n-tuples from a set and m-tuples from some possibly
different set. .
Another manner of speaking about the same subject material is also in common use; we speak of some
set of things, attributes of those things, and values of
attributes. Attributes are the same as relations, being
a correspondence between the things and the values
(which may also be things). Still another manner of
speaking is to use the term "map," as we shall do
shortly. A final manner of speaking is to use the term
"function"; in the theory of relations, this term is
reserved for the special case of relations which are
single-valued.
The notion of attribute should be distinguished
(as PL/I does not) from that of property. To say that
something has a given property is to say that some attribute of that something has a certain value. Thus,
when I say that a house is red, I mean that the value
of its color attribute is red, not that I intend to identify
the house with the universal concept of redness. Prop-
erties may be combined using the usual logical connectives to form new properties, unlike values. Thus,
the tall, red house has a property not shared by the
long, red house, except by accident. Its color attribute has the value red and its height attribute has the
value tall. PL/I would with more precision state that
the variable X has the property FIXED BINARY
DATA-TYPE; the data type is the attribute, and
FIXED BINARY is its value, or part thereof, as
we shall see.
Before proceeding, it is worth noting that the genealogical example illustrates two types of relations
which seem to be qualitatively different. On the one
hand, we have the family relationships and, on the
other hand, we have relations between individuals
and elements of other sets, such as dates .. There are
other relations which are more akin to family relationships, such as the relations between people who live
in the same dwelling or who work for the same organization. An organization chart also illustrates this
type of relation, which we will call "structural."
Data maps
We have called data fragments of a theory of the
real world. It is now time to examine the nature of that
theory. Along the way, it will be possible to propose
precise definitions for many terms which are normally used rather more loosely. We start with the
(undefined) notion of a set and introduce the notion
of a map more precisely than we did above. We will
use standard notation from set theory: Sets will be
represented by capital, Roman letters and elements
of sets by lower case letters. If a is an element of the
set A, we write
aeA·
If A is a subset of B (that is, all elements of A are also
in B), we write
A~B'
Maps will be represented by Greek letters. In talking
about a map of the set A into the set B (that is, the
map makes values in B correspond to arguments in
A), we will write
JL: A~ B
or
JL
A~B'
The latter form is useful in diagrams displaying several sets and maps.
We require of a map that it assign to each element
of A either nothing or one or more elements of B;
some members of B may not be assigned to any element of A. If every element of B is assigned to at
least one element of A, we call the map "onto." If a
unique element of B is assigned to each element of A,
Another Look at Data
the map is called "one-one." A one-one onto map
pairs each element of A with a unique element of B
and vice versa.
We will write ordered n-tuples of set elements as a
parenthesized list:
(ah~'" ,an)
In such an n-tuple, if each ai comes from a corresponding set Ah then the set of all possible such ntuples is written as:
A t XA2 X ... xAn
If all of the sets Ai are the same set A, then the set
of all n-tuples from A is written as:
An
The set of all subsets of a set A is usually symbolized
as
2A
owing to the fact that there are exactly 2n possible
subsets of a set of n elements. Figure 1 displays a
two element set A together with the set of pairs of
elements in A and the set of subsets of A.
0
\:)
(a ,b)
(b, a)
0
0
(b,b)
(0
0
(0,0)
0
527
We will call D a set of "data maps". As we shall see
later, D is a set whose elements are subsets of the set
Ex V. That is,
D
~ 2(EXV).
In the case of the Snows, one of the data maps in
D assigns to Henry(7) his birth date in the value set
of dates. The same data map assigns a birth date to
James H. Snow. The date-of-death data map assigns
no death date to James (at least, not on the basis of
the evidence quoted earlier); its value for him is
undefined. The father-of map assigns Henry (6) to
Henry (7), but its value for James H. Nichols is again
undefined. In the case of this map, the value set V
must contain E as a subset; we have an instance of a
structural map, which we define as any map of the
form:
u: En-+Em
for some non-negative nand m. This is, by our previous definition, a data map only if n = 1.
The set of entities, E, might be larger than one might
expect. For technical reasons, it is often convenient
to introduce certain auxiliary entities. For instance, in
the genealogical example, it might be appropriate to
introduce entities corresponding to married couples
as well as the entities representing individuals. Again,
one normally wishes to record information that has
no direct bearing on the entities the data are about,
such a file name, retention date, etc. In this case,
we merely augment the set E with a special element
eo together with data maps defined only for eo·
We have not inquired into the possible structure
of the value set V, nor have we admitted all possible
structural maps as candidates for the set of all possible data maps. The motivation for this is to simplify
matters by considering only the structural data maps
u: E-+ E
and by restricting the data maps to be functions - that
is, to have a single value for each argument. By appropriate adjunction of additional elements to E and
data maps to 0, this can always be done.
V, itself, might be considered to be constructed
from other sets. For instance, in the definition of
data maps we have implicitly assumed that E is a subset of V in order to admit structural data maps. The
set composed of the element~ of V which are not ele'
ments of E, that is
Figure 1- Sample sets
W=V-E,
Now data are supposed to record a set of facts'
about some set of entities, be they real or abstract.
In our present formal manner of speaking, we can
contemplate a set of entities, E, a set of values, V,
and a set D whose members are maps of the form:
could have structure, however. It might be a set of
ordered triples or something more complicated, such
as a set of vectors whose elements are vectors, and
so forth - in other words, a set of tree structures.
On the contrary, we will insist upon explaining structure by using structural data maps, and it will then
be the case that all data maps can be defined in terms
{}: E-+V
528 Fall Joint Computer Conference, 1967
of a non-structural map T applied to a structural map
a-. That is, if p- is an arbitrary data map, the situation
shown in the following diagram can be made to obtain.
E
p,
----..,.~V
a-
iJ
ko~eo~
kl
•
•
•
iJ
iJ
)
kn~
E
aeo' ------+
a-
eo"~
u
el---4 e 1 ,~ et" ~
a-
en~
en'
a-
~
...
a-
en"~
___7_~.,W
In the diagram, L is the identity map of W into V, expressing merely that W is a subset of V. The diagram
expresses the fact that, starting with an element of
E, one gets the same value by applying the map IL
as by applying a-, T, and L in that order.
Access functions
We need a way of t",avelling around over the entities, or locating them either relative to each other
or from something roughly like names or addresses.
This mechanism is provided by the notion of an access
function, which will be any map whose value set is the
set of entities or a subset thereof. Access functions
are not necessarily structural data maps, as we shall
see immediately.
Certain special types of access functions fall out
at once. Suppose we have a set K (for "key") and a
map from K which is one-one into E; this is a direct
access function, for we may regard K as a set of
keys, addresses, or names of entities in E. On the
other hand, suppose that we have a structural data
map and some initial element of E, say eo; if each application of the map gives us a new element of E,
until the final application gives us nothing, then we
say that the map is a sequential access function. It
mimics the. behavior of the successor function of elementary nu~ber theory, except that E is finite rather
than countably infinite. These two situations can
be illustrated by the diagram:
This is reminiscent of the indexed sequential access
method of Operating System/J60.
Data
We have still not explained which of the objects
above we mean to regard as data. The data maps themselves, or rather their elements, will be so considered,
but this choice requires further justification.
What happens when data are processed? Our naive
notion is that values are used as arguments to the
procedure and the result is that values get defined,
redefined, or undefined, so that the value set V must
be regarded as being the data. But, what if V is the
set of integers? It certainly cannot be the case that
data processing redefines the integers! Nor are the entities changed, so we are left with the data maps. This
notion may be a bit hard to stomach at first, but
may be made more palatable by considering ways in
which a map may be specified:
• We may specify a test which decides whether
or not the map actually assigns a given value to
a given argument.
• We may have a rule, or procedure (such as
applying several maps in succession) which will
designate the value, given the argument.
• We may define the map by actually exhibiting
the pairs of corresponding arguments and values.
In the theory of relations, the third approach is usually
used to define a relation - it is simply a set of ordered
pairs.
In our case, suppose that
lL(e) = v
Note that we have not required that the maps be onto
- a map into mayor may not be onto. A case in which
the maps are not onto is given in the following diagram:
This is the same as saying that the ordered pair (e,v)
is a member of the set IL. To redefine the value of
the data item (e,v) is to redefine IL by removing that
pair from it and adding a new pair (e,v'). This justifies our earlier statement that
D k 2 ExV)
Thus, data processing changes neithOer E nor V, as
desired.
Another Look at Data
We have, incidentally, slipped in a definition of
data item, which is an element of a data map. A data
element will be the set of all data items associated
with a given entity. List elements in IPL-V and
LISP are data elements, in this sense. The notion
of a logical record also corresponds to data element
in our sense, and field corresponds roughly to our
data item.
This explanation of data processing may seem
quite artificial, in view of our Platonistic feeling that
the "right" rule for assigning the value of a data item
should be independent of how we do our data processing. My friend the nominalist would not be bothered
by this scruple - he did not claim that such a thing
as a "right" rule existed in the first place; data do
not necessarily represent facts with utter accuracy.
Data processing, he might say, is data's way of attempting to adjust to the facts, if such there be.
Procedures
We have now noted the effect of a procedure-it
redefines one or more data maps or, what is the same
thing, changes the value part of certain data items.
The effect on D is to map it into a new subset of the
data maps. In other words, procedures are maps of
the form
Our idea about D is that it is the data at any given
moment of time, not the data for all time.
The import of our introduction of the auxiliary
entities was to effect a clean separation of structural
from other considerations. That is, we have set things
up so that any data map can be decomposed into a
structural data map followed by a non-structural data
map. The structural data maps are maps of E into E,
by definition. Our long-standing name for data items
in such maps is "pointers." This, in turn, suggests
an identification of list processing with procedures
which process structural data. A list processing
proceq.ure, hence, is any map of the form
529
characters, bits, registers,etc.). Maps specify attributes of the storage cells (more properly, properties) such as content, structure, parity, ability to read
and/or write, address, protection key, and the like.
The structural maps and access functions clearly
correspond to our more usual notions of storage
structure and access.
If our data maps are an abstract theory of the real
world, we must do data processing with something
else; computers are, after all, not abstract objects.
However, the abstract theory is just as capable of
modeling computation as it is of providing models of
the real world-possibly even more so. We are confronted, we might say, with three systems in any
specific situation. Each such system is composed of a
quadruple of entities, values, data maps, and procedures. The first system is, at least from a Platonistic point of view, some part of the real world, the second is our theory of the first, and the third is a machine representation of that theory. A representation
is, itself, now defined as a map establishing a correspondence between two systems.
What criteria should a representation satisfy? Well,
consider a system in the above sense:
S=(E,V,D,P)
where P is the set of procedures. Further, let 7T be
any procedure in P, mapping D into a new set of data
maps D, and let p be a representation map which
maps S into S':
p: (E,V,D,P)~(E',V',D',P')
For any object in S, we wish the representation to
assign a unique object in S', and vice versa. In other
words, p should be one-one onto. However, we desire
more than just this; in order to insure that anything
happening in the one system also happens in the other,
we require that the following diagram be commutative:
D
P
----~~
D'
P
D ---~) D'
This is a precise version of our vague notion that list
processing has something to do with pointers and data
structures.
Data storage and representation
The foregoing model obviously can be taken to
apply directly to physical storage media. 3 To entities correspond cells in storage (blocks, words,
or, in other words, that:
P7T=7T'p
This criterion can fail in two ways: (1) obviously,
when the map p is not one-one onto, and (2) when the
procedure 7T', chosen in the belief that it corresponds
to 7T, does not in fact so correspond. It might be
thought that the second alternative can happen only
by mistake, since we could presumably define the
530 Fall Joint Computer Conference, 1967
procedure maps in terms of E and V and they are
mapped into their primed counterparts in a one-one
onto fashion. The rub is that, in practice, the first
condition frequently does not obtain, and this gives
rise to doubt as to which procedure 'TT' best represents an abstract computation 'TT.
The reason p fails to be one-one onto, usually, is
that the set V is of a different size than the set V.
The most obvious example is the case of machine
representation of the real numbers; only rational
numbers may be represented with complete accuracy
on a machine (numerically, at least), and our common floating-scale representations are capable of
representing only a finite number of rationals at
that. * Moreover, the primitive operations out of which
we compound procedures are only "best" representations of the abstract operations we have in mind. The
size of the literature on floating-scale representations
and arithmetic testifies to the amount of disagreement
existing on what "best" means!
In the case of a machine representation, we have
an abstract system and a representation map mapping
it into the machine system. In fact, we frequently
employ more than one machine representation for
certain data items (e.g., numeric data). On the other
hand, there is the physical storage system, and the
machine representation of the data and procedure
maps must be mapped into the physical storage. The
structural part of this mapping-that is, the correspondence between the structure of the data and
the structure of storage, we call the data organization.
While this enables data access, it is not access. Access is a feature of the processing of the data, not of
the data itself or how it is represented; different procedures will, in general, want to access the same data
in different ways and orders. The order in which data
items are fetched and stored is (or should be) independent of the data organization; this notion was an
important principle in the design of the data management subsystem of Operating System/360.
I
Data description
What do we mean in general by the term "data
description 1" We might be tempted to confine our
attention to the theoretical realm and, like ALGOL,
talk of real numbers, integers, dynamic own arrays,
and the like, considering it the job of any representation to be faithful to our theory. To do so, however,
would be to beg the question by ignoring descriptive
information which we use every day, and in machine*Matula4 has studied the maps which convert a floating-scale
number from one radix· to another. He shows that the map may
be one-one or onto, but not both!
processable form at that. For example, the COBOL
Data Division contains information which we would
call data description, such as field lengths, and these
certainly describe the machine representation, albeit
incompletely. Information describing a data set appears in the volume and data set labels, and still
other information is used to compile the procedures.
All of this information, and more, is data description,
although not all of it is stored explicitly or even in
one place, nor is it available at all times. Some of
it exists only in the minds of men!
So, I will be dogmatic: Data description describes
machine data systems, representations, and organizations, rather than abstract data itself. That is, it is a
specification of the maps, usually in terms of procedures which will accomplish the mapping, and the
salient characteristics of the entity and value sets.
To describe a data aggregate-that is, a file or data
set - we supply this information together with information concerning the aggregate as a whole.
The term "data type" has been used informally
above, but not in any essential manner. Intuitively,
we feel that the data type tells us what kind of data
we are dealing with. Had we not discovered that data
items must be regarded as being elements of data
maps rather than elements of value sets, our first
false start toward a definition of data type might be
to regard it as an attribute of the value set. A moment's reflection, however, is enough to convince
one that this is an untenable notion; a given bit pattern may represent an element of anyone of a number
of value sets (binary integer, floating hexadecimal
number, character string, or something else). In fact,
it is not unusual to treat the content of a given storage cell as if it were of one data type at one point in
a program and of another data type somewhere else.
Our next theory about data type, then, might be that
it is related to the kinds of procedure maps used to
process the data items. We retreat to the abstract
realm, and consider the data type as specifying the
mathematical system which governs processing. We
might then come out with the following generic data
types:
• String -free monoid on a finite number of
tokens
• Boolean - Boolean algebra (or, equivalently,
ring)
• Numeric-field (or more general system)
• Pointer -directed linear graph
This doesn't help very much. We distinguish between
fixed binary and double precision complex floating
decimal data, and this false start manages to keep us
from making distinctions of practical importance by
preventing us from talking about representation.
Another Look at Data
Nevertheless, the above are not irrelevant to data
type; they are merely incomplete definitions. We are
forced to conclude that a data type is a fragment of
data description and, as such, describes a portion of a
system and its associated representation and organization maps. It is an attribute of entities. We can tie
the notion down better by looking at further determinants of data type for each of the generic data types
mentioned above:
String
• Code-the code for each token (character, bit,
etc.). E.g., USASCII, EBCDIC and the like.
• E.g., USASCII, EBCDIC and the like.
• String length - fixed or variable, and value of
length attribute.
• Justification-left or right, and padding token.
Boolean:
• Code - the code for each truth value (or n-tuple).
• Field length.
Pointer:
• Code - machine address, base and displacement,
item number in table, etc.
• Code for null pointer.
Numeric:
• Code - digit code, radix or weights, excess.
• Sign treatment - unsigned, sign and magnitude,
radix or radix minus one complement.
• Scale - fixed or floating, value of scale.
• Rounded or truncated calculation.
• Arithmetic algorithms.
• Numeric limit(s) on value.
• Field length, or precision.
• Aligned or packed (storage mapping restriction).
It is evident that a complete description of a given
data type contains information concerning representation of elements of the value set; information stating
which representation, procedure, and organization
maps are applicable; and data to be used in any
mapping (such as value of scale). It is further evident
that two entities which are not identical in all of these
respects should not be regarded as having the same
data type, unless the variable information is stored as
data to be used interpretatively in accomplishing any
of the mappings. Thus, variables of type real in ALGOL must be regarded as having different data
types as represented, say, on the IBM System/360
and the CDC 6600.
Thus far, we have not discussed structural data. We
even seem to have done a bit of violence to the notion
531
of separation of structural from other data, but this is
easily fixed. For instance, consider a floating-scale
entity. Both the mantissa and the characteristic must
be available during calculation, and they are treated
as one entity during floating-scale arithmetic but as
two entities during radix conversion. To be completely
consistent, for each floating-scale entity we should
introduce two more auxiliary entities; each of these is
a fixed scale number and can be described appropriately. Similarly, we can take care of complex and
multiple precision entities.
Turning to purely structural data, it is clear that we
can invent data types, such as arrays, lists, tables,
ring structures, etc., for any sort of structure worth
classifying. In practice, of course, we suppress
most of the detail involving the auxiliary entities and
write down descriptions like:
DECLARE A(3,3) FIXED BINARY (15);
to describe a three-by-three array of 15 bit fixed-scale
binary integers.
Languages and systems
On the basis of the point of view about data advocated earlier, more light can be shed on several
issues of current interest. In some sense, these
issues are all related to the possibilities of flexibility
in choice of machine (machine independence), choice
of data representation (ability to define new data
types), or ability to strike a balance between compilation and interpretation (variable binding time).
Representation independence
For some years now, one of the more persuasive
arguments in the favor of narrative languages such as
ALGOL, COBOL, FORTRAN, JOVIAL, NELLIAC, and PL/I has been that they have ~ffered
some measure of machine independence. That is, the
user is offered a greater or lesser degree of hope that
a program written in a particular language together
with data processed by the program can be processed
on a variety of computing systems, with something
like the same results.
Independent of one's personal degree of confidence
in fulfillment of such an objective (and most of us
believe that the objective is a Good Thing), I would
urge adoption of the term "representation independence" as being more appropriate than the term
"machine independence." In espousing such an objective, one's philosophical point of view might be
that data processing takes place in the abstract realm
in which our theory of data is formulated. It is, following this line of thought, more or less an accident
(economic issues and questions of accuracy aside)
532 Fall Joint Computer Conference, 1967
which computing system and machine representations
are chosen in order to do the actual processing, and
all such choices should lead to the same results. * In
principle, I cannot quarrel with such a view; in practice, I wonder if blind pursuit of the objective does not
often result in prejudgment of the economic issue. I
hasten to add, however, that most programmers tend
to be too pragmatic - in the long run, generality often
costs less than specificity.
Representation independence is a more stringent
objective than is machine independence. Representations are equivalent only when the representation
maps are one-one onto and commute with the procedures, as we have seen, and there are cases in which
this simply cannot be achieved in practice. Even in
cases where one can choose a representation which
satisfies our criterion, the cost may be unacceptable
and we are forced to make do with a "best" representation. This should be counted as no disaster; it
simply means that in practice we must relax the
criteria of representation independence sufficiently
to stay within optimal bounds of accuracy and economic data processing. Paradoxically, the best way
to follow the spirit of our objective is to recognize
that we can't live up to the law in all cases.
Our Platonistic tendencies have led us, in the past,
to attempt to banish considerations of representation
from language design and usage. I would suggest,contrariwise, that any serious attempt to design languages
which are significantly more representation independent that at present is doomed to failure unless the
notion of representation is made part of the language,
ungrudgingly. At that point, we are again faced with
the issue of how cleanly we can separate specification
of the algorithm from specification of the data representation. Possibly, this introduces a new version of
the UNCaL controversy! To overstate the case, the
notion behind UNCaL was that one could pump a
language description into one end of a compiler, a
machine description into the other end, and come out
with quality compilations. While many would still
like to believe this, the evidence is that the two
descriptions cannot be separated that cleanly. What
I am suggesting, however, is counter to separatist
sentiment - I claim that we should see what happens
if we let the programmer talk about both procedure
and representation.
PL/I is the latest language design to attempt suppression of representation. Yet, UNSPEC finally
made its appearance. For a purist, the use of UNSPEC is as unacceptable as in-line machine language
*This is not my own point of view, needless to say. However, the
notion of representation independence makes sense whatever one's
philosophical bias.
'
coding. Why, then, did UNSPEC slip in? The reason,
I suspect, was two-fold: (1) to allow use of data types
not already defined in the language, and (2) to allow a
given storage cell content to be treated according to
one data description at one point in a procedure and
according to another somewhere else. It seems to me
that the attempt to banish representation considerations from language design has, in this case at least,
led inevitably to their sneaking in the back door in a
quite unpalatable form.
The dilemmas posed by representation independence, UNSPEC, and the CELL construction in
PL/I are unfortunate inheritances from past history,
.earlier forms of which occurred in FORTRAN. They
resulted from our inherited belief that symbols are
names of storage locations rather than names of entities assigned to them by the data organization. The
crux of the situation is this: The programmer wishes to
be representation independent to the extent that considerations of accuracy and economics allow. On the
other hand, in some cases, he is definitely concerned
with specific representations - for instance, in specification of procedures which convert data from one
representation to another. To be so doctrinaire in
language design as to insist on complete representation independence is to cut off one's nose to spite
one's face. The language feature needed in the specific
case at hand is the ability to say "I have a value for
data item A in storage, and I now wish to use that as
the value for data item B, which has a different data
type. Furthermore, no matter how complex the structure and data organization for A and B, I know that
-the bit patterns for the two values are identical (I
just told you so), so don't bug me about representation independence." In other words, the programmer
must be allowed to pay his money and take his choice.
Language extension
PL/I has been lambasted both for having too many
and for having too few data types available. The
former point is made by many who have been unfavorably impressed by the sheer size of the code required
in PL/I compilers, although this might with more
justice be blamed on the amount of automatic data
conversion required. The latter point is made by those
who wish to handle data of more complex structure
with less circumlocution. The suggestion has been
made in many quarters that what we really need is
fewer data types along with apparatus which will
allow the user to define his own. I find myself in this
camp, although I don't believe that the problem is by
any means as trivial as is sometimes claimed.
Part of the problem, of course, lies in adopting a
consistent view of what data are and finding suitable
Another Look at Data
methods for writing and storing data descriptions
(including both representation and organization). The
theory of data advanced above seems potentially
adequate for these purposes; what is not so clear is
how to link the data description apparatus to the code
generation and optimization apparatus of the compiler.
Galler and Perlis 5 have done some interesting work in
this area.
Variable binding time
How much of the data description is stored explicitly, and where, is partially a matter of taste. It is
largely determined by the language, language processor, and operating system one is working with at
present. Classically, we have tended to use the data
description at compile time and then throw it away.
Moreover, much of the data description has been iinplicit in the compiler's structure; the programmer has
had little explicit control. List processin,g is an intermediate case - processing variable data structures
must be done interpretatively, even though the code
for other processing can be compiled out. At the other
extreme, interpretative operation tends to use the data
description at execute time, over and over ,again. In
the former case, the bet is that the program will not be
recompiled too often and the data description will not
have to change during execution, nor will the data
structures. In the latter case, the bet is that less overhead will occur through interpretation than would be
incurred by frequent massive compilations. Conversational processing tends in the latter direction.
But, in the case of all systems that have been designed thus far, the choice of binding time is pretty
much cast into concrete by the system ,and language
processor design, even though it' is hard to believe
that the choice can possibly be appropriate for all
tasks. We should, I believe, seriously investigate the
possibility of system designs that allow the individual
user to make his own judgment of the proper tradeoff.
This would necessitate explicit storage of data descriptions -:- a few systems have' allowed this, ~otably
the CL-I and CL-II systems. 6
SUMMARY
In the first part of the paper, we have proposed a
theoretical model for data and data processing. The
model is a system of sets of entities, values, data
maps, and procedure maps. The entities correspond to
the objects in the real world about which data are
recorded or computed. The data maps assign values to
attributes of the entities; these maps are regarded as
being sets of ordered pairs of entities and values, or
data items. Structural data is a special type of data
533
map where the value set is the set of entities itself;
structural maps are composed of pointers. By introducing structural data maps and auxiliary entities, we
can explain any data map as being composed of a
structural data map followed by a map whose value is
a quantity with as simple structure as we wish (for
example, an integer). Procedures are operations on
the data maps, producing new (or redefined) data
maps. List processing procedures operate on structural data maps, or sets of pointers.
Data processing occurs in the machine realm,
operating on objects which are mapped into the
storage facilities of the computing system. We require, ideally, that such a system be a representation
of the real or abstract system being modelled; this
means that the representation map is one-one onto
as regards the entities, values, data maps, and procedure maps and, further, that the representation map
commutes with the procedure maps.
Access functions are maps whose ,values are entities; they are used by procedures to get access to
the entities, and hence to the data. Access functions
may involve use of structural data, but are principally
a feature of the individual procedure. Data organization, on the other hand, is the way the structure of
the data.is mapped into the structure of the storage
media.
Data description is a specification of machine data
systems and representations; a data, type is a fragment of data description, describing an entity and 'its
applicable maps.
The first part of the paper, then, was a discussion of
the nature of data and the relation between what it is
and what.we do with it. In t~e second part of the paper,
these notIons were used as a framework for discussing
several issues of current interest.
The notion of machine independence, apart from
its roots in practical needs, proceeds from the point
of view that data processing takes place in the abstract
realm and, hence, its results should be representation
independent. This is an attainable goal only when our
criterion for a representation can be satisfied economically. However, language design has tended to
suppress the notion of representation to the extent
that the programmer frequently cannot talk about it.
I regard this as being a mistaken approach toward our
practical goals; on the contrary, significant progress
toward representation independence of -results can
only be made by making the notion of representation
much more explicit in language designs than it is at
present.
A second argument for emphasizing the role of data
description in language design is related to the issue
of language extension. A trend in language develop-
534
Fall Joint Computer Conference, 1967
ment has been to expand the number of data types
available to the programmer, at the expense of significant increases in compiler size and complexity,
and without satisfying those who have a genuine need
to use data types over and above those already avail.able in a given language. The way out of this dilemma
appears to lie in the design of languages with a limited
number of data types (perhaps only one instance of
each of the four generic types mentioned earlier)
together with facilities enabling the user to introduce
arbitrary data type definitions as heeded.
Finally, it was argued that language and system
design should make increased use of stored, explicit
data descriptions. This will serve two purposes:
First, it is a prerequisite for the design of systems
which allow the user to strike his own economic
balance between compilation and interpretation.
Second, the extent to which current system designs
achieve the goal of independence of procedure specification from data representation is due to the use
of stored descriptive information, together with interpretation of the description, be it at compilation,
execution, or some other time. Standardization of
methods of data description may ultimately prove to
be much more important than standardization of methods of data representation and procedure specification.
REFERENCES
2
3,
4
5
6
W V QUINE
From a logical point of view
Harvard University Press Cambridge 1953
G L DAVENPORT E 0 DAVENPORT
The genealogies of the families of Cohasset, Massachusetts
Stanhope Press Boston 1909
A W HOLT
Proceedings oflFIP Congress 1965
Spartan Books Inc Washington DC 1966
D W MATULA
Base conversion mappings
AFIPS Conference Proceedings, Spring Joint Computer
Conference vol30 pp 311-318 1967
B A GALLER A J PERLIS
A proposal for definitions in A LG 0 L
Comm ACM 10204 1967
T E CHEATHAM,JR.
Data description in the C L-II programming system
Digest of Technical Papers National Conference Association
for Computing Machinery 1962
Dataless programming
by R. M. BALZER *
The RAND Corporation
Santa Monica, California
INTRODUCTION
A programmer using existing programming languages
typically codes a problem by (1) defining it, then
(2) analyzing the processing requirements, and (3)
on the basis of these requirements, choosing ;t data
representation, and finally, (4) coding the problem.
Almost always, difficulties arise because necessary
processing not envisioned in the analysis phase makes
the chosen data representation inappropriate because of
a lack of space, efficiency, ease of use or some combination of these. The decision is then made to either
live with these difficulties or change the data representation. Unfortunately, changing the data representation usually involves making extensive changes to the
code already written. Furthermore, there is no assurance that this dilemma will not recur with the new
data representation.
The Dataless Programming System is designed to
help alleviate this problem. All data and function
references are expressed in a single canonical form,
so that the alteration of a data representation has no
syntactic effect on the program, but only affects the
internal processing associated with the data or function references - i.e., changing the data representation does not affect the program's source statements.
Unless the change in the data representation causes a
change in data values (e.g., a change in precision),
the values produced by the program will be unaltered.
(Naturally, the behavior of the program in terms of
efficiency, speed, and space required may be affected
by any change in data representation. ) Hence, the
data representation can be specified after the program
is written, and analysis of the problell!~ definition and
*This Research is supported by the Advanced Research Projects Agency under Contract No. DAHC15 67 C 0141. Any
views or conclusions contained in this paper should not
be interpreted as representing the official opinion or policy
of ARPA. This paper is a condensed version of the author's
Dataless Programming, The RAND Corporation, RM-52 90ARPA, July, 1967.
code production can be integrated into a single phase.
The programmer should be able to construct his program in terms of the logical processing required without
regard to either the representation of data or the
method of accessing and updating. This concept we
call "Dataless Programming."
Dataless Programming is more than a new language.
It conceives of a program as the specification of a
set of manipulations to be performed on a set of data
values, and that this specification should be independent
of the form in which these data values are represented.
To achieve' such independence, there must be a set
of declarations that tell the programming system how
to retrieve and store data values from the particular
representation being used. The independence thus
achived will allow the programmer (1) to disregard,
while specifying the program, the details. of data processing, memory space requirements, and matching of
data representation to the processing done on it; and
(2) to handle them, instead, during the data declaration phase.
The Dataless Programming Language is the embodiment of the above concept. It also helps simplify the construction and debugging of programs by
providing high-level data-handling and control facilities
(insertion, deletion, generators, bugs, search expressions, and implied qualifications of data references) and
a STATE-statement (enabling a wide range of monitoring and tracing facilities to be specified).
Throughout the design of the language, an effort has
been made to allow the programmer to express his
intent more clearly through new program statements
rather than in separate comments. That is, we have
attempted to make the purpose of commonly occurring
statement groups more apparent by combining them
into an appropriately worded statement. Examples of
this effort are the FOR-clause, search-expressions, and
the extended IF-statement. The programmer can also
increase the program's self-documentation through the
536
Fan Joint Computer Conference, 1967
----------------
use of mnemonic names for data items which are then
defined as functions (as has been done in the programming example in Sec. IX below).
II.' The dataless programming language
The Dataless Programming Language is a high-level
algebraic' language which. is an extension of PLj 1
and uses PLj 1 syntax notation * and syntax, except
as noted. The language is based on a single canonical
representation for all data and function references.
This form is:
{collection-name I
function-name [( expression [, expression] . . .)]
If the name identifies a function name, the expressions, if any, are interpreted as parameters. If the
name identifies a collection name, the semantic interpretation is that there exists a collection (or group)
of data which has a common, unique name (the collection name). This collection 'has the property that, given
a single integer index (computed from the expression.
called the index expression. which follows. the coIIec.tion name), there exist algorithms which use the value
of this index to operate on the data collection, performing the functions of accessing and updating the datum
selected and inserting or deleting a datum from the
collection. The system asumes that there exist such
algorithms, determining what they are not from the
form of the program's source statements but rather
from explicit declarations. supplied with the program.
Hence, .changing a collection from an array to a list
does not change the source statements but merely
changes a data declaration. Also, since function references are syntactically identical with data references, the
user can change a function reference to a data reference, or vice versa, by merely changing a declaration.
Separ~ting the data definition and its implied datahandling routines from the common appearance of data
or function references in the source code provides the
main power of the language. This feature allows the
user to program in a top-down fashion in terms of the
logical pieces of information necessary for the required
processing. Once the user has completed this programming, he can determine for each collection what data
representation is suitable for the processing involving
that collection. He may also decide that a piece of information should not be supplied by a data reference
on a collection, but should be supplied by a function
through a calculation or series of calculations on other
information-either data or further function references.
The user rimy use the language's full power in defining
either a function or the data-handling routine for his
':'As defined in Ref. 1. PP. 11-17.
data representations, and so is able to program each
part of his problem in a top-down fashion.
Logically, since the data-handling routines operate
with a single index, the data representations are ordered
lists. The system allows the following data representations (for which it provides the data-handling routines) :
(1) ARRAY
(2) LIST (forward links only)
(3) DOUBLE LIST (list with both forward and
·backward links)
( 4) RING (forward links only)
(5) DOUBLE RING (ri,ng with both forward and
backward links)
(6) STRUCTURE (as defined in PLj1)
(7) Structures of any of the above (e.g.. arrays
of lists of structures).
In addition, any other ordered area representation
can be used by providing the necessary data-handling
algorithms. These algorithms can consist of a call to
an external procedure and can be written in any
language desired (including assembly language). Hence,
within the restriction of ordered data representations,
the representations allowed are completely open ended .
This class is large and significant, covering most currently used representations. Clearly, however, some
representations (e.g., colored pictures) lie outside this
class; and we have no ideas on ways to incorporate these
into the Dataless Programming Language.
Since all data manipUlations of a collection are performed by the data-handling routines, these routines
can be altered to provide a powerful monitoring capability. By suitably altering the update routine for a
data collection, the system can be notified any time
a member of that collection gets updated. Hence. the
system can perform any desired action as a response
to the occurrence of a particular state of the program
variable, i.e., it can handle STATE-statements. The
form for these STATE-statements is:
{ON I WHENEVER} (boolean-expression) statement;
For implementation purposes, the boolean-expression is restricted so that all variables which effect its
truth value must explicitly be part of the expression
(enabling the system to determine which variables require checking), and the evaluation of the booleanexpression must not change the value of any of these
variables (and care should be taken that it also does
not change the value of any other program variables
which affect the behavior of the program. so that its
removal does not affect the program). Whenever one
of these explicitly named variables is updated, the
boolean-expression is evaluated and, if true, the associated statement is executed. As an example, if the
STATE-statement
Dataless Programming
ON (x == y I x == z) CALL print;
occurred, the data updating routines for x, y, and z
would be altered so that this on-condition would be
checked whenever either x, y, or z was updated. If
the on-condition was met, the indicated action would
be performed. Thus, a wide range of trace and/or
debugging features can be specified. Also, a variety of
special case monitoring of the program, which is nondebugging - but part of the desired processing can be incorporated in the language.
The language provides the following data-handling
statements (small single letters will be used to denote
data collection names):
(1) DELETE region;
(2) INSERT region {BEFORE I AFTER} X
(index-expression) [AND MAKE
CURRENT];
(3) REPLACE region BY region;
(4) ADD region TO x [AND MAKE
CURRENT];
where a region is defined as
collection-name (index-expression)
[TO collection-name (index-expression)]
and specifies a continguous inclusive set of collection
members (the collection names must be the same and
the indices must ascend in order). (The AND MAKE
CURRENT option is explained below in Sec. III.) The
REPLACE and ADD statements are defined in terms
of the INSERT and DELETE statements. REPLACE
is equivalent to DELETE followed by INSERT BEFORE, and ADD is equivalent to INSERT AFTER
the last member of the collection. The above statements
are defined for all data representations allowed in the
language; e.g., insertion into an array is defined as
increasing by 1 the index of all members with indices
greater than or equal to the value (i) of the inserted
index, and the storing of the value of the inserted datwu
as the new ith member of the array. (The problems
concerning the maintenance of data collections and of
pointers to members of these collections are discussed
in Sec. VI below.)
Two facilities are provided for sequencing through
a data collection. The first is the FOR-clause which
sequences through a data collection searching for all
members which satisfy a specified condition and, as
each one is found, causes a single statement or a
group of statements to be executed. Thus, one cycle
of an "iteration" is performed for each member of the
subset of the data collection which satisfies the specified condition. This facility essentially combines a
DO-statement (to sequence through the data collection) with an IF-statement inside the range of the
DO-statement to test the given condition.
537
The second sequencing facility: (1) sets up a search
through a data collection, in the same way as a FOR.:.
clause; (2) searches for the first member of the data
collection which satisfies the given condition; and (3)
causes a placemaker to point to that member. This
placemarker can be used for processing the selected
member. When the next member of the sequence is
desired, it is explicitly requested, causing (1) the data
collection to be searched for the next member which
satisfies the previously specified condition, and (2) the
setting of the placemarker to point to the newly' selected
member. This facility generates, upon request, the next
member of a collection which satisfies a given condition. Hence, the facility is called a "generator," the
statement which sets up the sequencing a "GENERATE-statement," and the placemarkers "generatorvariables." The generator method of sequencing differs
considerably from the FOR-clause method in that (1)
it is not associated with a particular statement or group
of statements, and (2) is not automatic but occurs only
on request. The same code is not necessarily used to
process all members in the sequence, and the same code
can be used for different data-collection sequences.
These generators can operate independently of each
other, and more than one can be sequencing through a
data collection simultaneously (if two or more generators are sequencing through a data collection, and the
processing done in connection with one of them alters
the data collection, the set of selected members of the
other generator (s) may also be altered, as the current
state of the data set is used in the determination of the
next member to be selected).
The FOR-clause is used to control the execution of
a single statement or group of statements for selected
members of a collection. Its syntax is:
FOR {ALL I EACH I EVERY} collection-name
[iterative-specification]
where an iterative-specification is defined as
[IN THE DOMAIN specification [, specification] ... 1
[SUCH THAT (Boolean-expression)]
and a specification has the form
expression-l [TO expression-2] [BY expression-3]
[WHILE (expression ~4 ) ]
The precise semantics of a specification are given in
the PLj 1 specifications/ but basically correspond to
the following: a region is specified (by expressions 1
and 2) through which an index is incremented in steps
of size expression 3; and the WHILE-clause specifies
a condition which, if not met, causes the termination of
that specification. Notice however that contrary to the
DO-clause, the index is not specified; it is not needed
and is supplied automatically by the system.
The FOR-clause is associated with a single statement
by inserting the FOR-clause before the statement's ter-
538
Fall Joint Computer Conference, 1967
minating semicolon (e.g., x == y FOR ALL x SUCH
THAT (x < 5);), or with a group of statements by
preceding the statement by:
FOR-clause DO;
and following them by
END;
The FOR-clause causes execution of the associated
statement or group of statements for all members of the
collection in the specified domain for which the booleanexpression is true. The iterative specification has the
same interpretation as in PLj 1. If no iterative specification is given, then all the members of the data collection, taken in ascending order, are used as the domain.
Generators are used to give the programmer explicit
control of the sequencing through a data set. A new
variable type-generator-variable-is introduced for this
facility and is used to obtain the successive members
of the collection. These variables allow more than one
generator to be operating on a data collection at once,
and also allow one generator variable to sequence
through two or more different data collections during
program execution (but only one at a time). The syntax for generator statements is:
GENERATE THROUGH collection-name USING
generator-variable [AND MAKE CURRENT]
[iterative-specification] ;
This statement sets up the sequencing implied by the
iterative-specification as defined in the FOR-clause (or
a sequence of the successive members of the collection
taken in ascending order if the iterative-specification is
not specified) and establishes the generator-variable
as a synonym for the first member of the collection
selected by the sequence. (The AND MAKE CURRENT option is explained below in Sec. III.)
The programmer explicitly instigates iteration by execution of the GET NEXT statement:
[GET] NEXT (generator-variable [ {AND I BUT DO
NOT} MAKE CURRENT]; [OTHERWISE statement]
This causes the generator-variable to become a synonym
for the next member of the collection selected by the
GENERATOR-statement. If no other members exist
for the generator and an OTHERWISE-statement
(which· can be a block or group) is present, it is executed as an ON-unit. * If not, a new condition-the
END GENERATOR condition-is raised and can be
handled by an appropriate ON-unit. (The maintenance
of the correspondence between a generator-variable
and a collection member in a dynamic environment is
explained in Sec. IV below.)
Search-expressions cause a data collection to be
searched for a member which satisfies a condition.
Either this member or its index is the value of the ex-
pression. The syntax of a search-expression, which can
be used anywhere an expression can, is
[INDEX OF] numeric-specification collection-name
[IN THE DOMAIN specification] SUCH THAT
(boolean-expression)
where specification is defined as in the FOR-clause,
and numeric-specification has the format:
{FIRST I SECOND I LAST I {decimal-integer
(expression)} {ST I ND I RD I TH} }
Examples:
10TH
21ST
(x+3)RD
The numeric-specification specifies a value i, and the
value of the search expression is the ith member (or
the index of the ith member if INDEX OF is specified
of the data collection which satisfies the Boolean-expression with the order of iteration specified by the.
iterative-specification.
The statement following a statement containing a
search-expression can begin with the keyword OTHERWISE. This statement is executed as an ON-unit** if
and only if a value cannot be found for the search
expression.
If the OTHERWISE option is not specified and the
search-expression does not produce a value, a new condition, SEARCH FAILURE, is raised and can be
handled by an appropriate ON-unit.
Many times a search-expression is used only to find
out whether or not a member of a collection exists which
satisfies a certain condition. To make the intent of this
use of the search-exp'ression more apparent, the syntax
of the IF-statement has been extended as follows:
IF {boolean-expression I THRERE [{DOES ' DO}
NOT]
{EXIST I EXISTS} (A I AN I number I (expression)}
collection-name SUCH THAT (Boolean-expression)}
THEN statement [ELSE statement]
The semantics of the IF-statement remain unchanged;
*ON-units and conditions are fully explained in Ref. 1, pp. 7984, but basically consist of the following: When such conditions as fixed point overflow, end of file, or END_GENERATOR occur, the program execution is interrupted. If
an ON-unit has been specified to handle a condition which has
occurred, then it is executed. This group of code can take
corrective action and return to the program, print out an
error statement, or terminate the program. If no ON-unit
has been specified, the software system takes some default
action (usually terminating the program) . ON-units can be
specified for any occurrence of a condition or only for
those occurrences related to a specified set of variables. Thus
the action taken can be dependent on which variable was
related to the occurrence of the condition.
**For a discussion of ON-units and conditions, see Ref. 1,
pp. 79-84.
Dataless Programming
i.e., the statement following the THEN is executed if
and only if the condition specified between the IF and
the THEN is true; and the statement following the
ELSE, if present, is executed if and only if the condition is false.
Examples of the extended IF-statement are:
IF THERE EXISTS A Y SUCH THAT (y < 10)
THEN GO TO z;
IF THERE DO NOT EXIST 10 Y SUCH THAT
(y
>
0)
THEN RETURN (0); ELSE RETURN(l);
III. Hierarchical data references
For data representations which are hierarchical, references to the elements can be fully specified by using
the following form, where n is the level of the element
being referenced:
Collection-name n (index n) OF collection-name n-l
(index not) OF . . . OF collection-name 1 (index t )
For example, consider a list, x, of arrays, y, where the
ith member of the jth array is referenced by
y (i) OF x (j)
This notation assures unambiguous data references but
is: notationally burdensome; restricts our reuse of the
variables used in higher level indices; and necessitates
referencing through each level of the hierarchy. Instead, it would be convenient to reference data relative
to some member of a collection. Once a user has decided to talk about the jth member of the collection x,
he would like to be able to reference the ith member
of collection y by writing
y (i)
This facility is achieved by introducing a new statement which allows the programmer to specify that a
particular member of a collection is to be made a reference point for further data specifications. This is
called making the member current. One (and only one)
member of each collection can be made current. The
form of this statement is:
MAKE collection-name (index-expression) CURRENT;
The specified member of the collection is made
current.
Each FOR-clause saves the current member of the
data collection being iterated through, and each iteration of the loop makes the newly selected member current. Normal termination of the loop (the iteration has
been completed) causes the saved member to be made
current again. If the loop is terminated by a transfer
(GO TO), the current member remains current and
the identity of the previous current member is lost.
Whenever a reference is incompletely specified, the
system will supply the -necessary current member (or
members) of the missing collection (or collections) to
539
complete the specification of the reference. This is done
in the following way:
(1) If the highest level collection in the reference
is not completely specified, then the current member of
the collection at the next higher level is used to complete this part of the specification. Thus, in the previous examples, a reference of "y(i)" will cause the
system to complete the specification by supplying the
current member of collection x.
(2) If there are any missing collections which are
intermediate in level between the highest and lowest
collection specified in the collection, the index of the.
current member of those collections is used as the index of those collections to complete the specification.
For example, given a five-dimensional array (xl, x2,
x3, x4, x5), the reference "x4(2) OF xl (10)" would
be completed by the system and become "x4(2) OF
x3 (CURRENT) OF x2(CURRENT) OF xl (10)."
(CURRENT is a function whose value is the index of
the current member of the collection in whose index
expression the function reference appears.)
Notice that the above completed specification is different from the reference "x4 (2)" (which would be
completed by rule 2) above to "x4(2) of x3"), and
the current member of x3 does not necessarily have to
be a subpart of xl (10).
Any data reference may require none, one, or both
of the above rules to be completed. For example,
"x4 (2) OF x2 (5)" requires both rules to be completed as "x4(2) OF x3 (CURRENT) of x2(5) of xl."
By use of these mechanisms, data references can be
specified relative to a base determined by the current
member of a data collection. Generator-variables can
also be used for relative data specifications by specifying the generator-variable as the relative. base. For example, if "gen" were a generator-variable sequencing
through data collection x, then "y(i) OF gen" would
refer to the ith member of whichever member of x "gen"
was set to. This method of hierarchical references is
similar to the use of "bugs" in L6 2 and to the concept
of "current" in APL3 •
Since generator-variables can be set to an individualmember of a collection (e.g., "GENERATE
THROUGH x USING gen IN THE DOMAIN 5";
causes "gen" to be set to the fifth member of the collection x), the full power of the bug concept of L6 is
available. To make this cause of. generator-variables
easier, the following statement has been introduced:
SET generator-variable TO collection-name (indexexp);
This causes the specified generator-variable to
be set to the specified member of the named collection
(any attempt to execute a GET NEXT statement for
540
Fall Joint Computer Conference, 1967
this generator variable will raise the END-GENERATOR condition).
To extend the use of the current concept to generators, options have been included which allow the programmer to specify whether the members generated
should or should not be made current. In the GET
NEXT-statement, he can specify whether the members
generated through the use of that particular GET
NEXT -statement should be made current or not. If
neither option is specified, then the GENERATE-statement is used for the determination. If the AND MAKE
CURRENT option is specified, the generator members
will be made current; otherwise, they.will not.
Similarly, the programmer can specify in an INSERT or ADD-statement that the inserted or added
member is to be made current. (If a region is inserted
or added and the AND MAKE CURRENT option is
selected, the last member of the inserted or added region
is made current.)
To extend the programming facilities and/or for
notational convenience, the following built-in functions
have been defined-where a collection-member-expression can be a collection member reference, a searchexpression, a generator-variable, or a function reference which returns a collection member as its value.
NEXT (collection-member-expression),
PREVIOUS (collection-member-expression), and
INDEX (collection-member-expression)-the value
of the function is the next or previous member,
respectively, of the collection specified in the expression from the specified member or the index
of the specified member of the collection. An
OTHERWISE-statement can follow a statement
including these functions. This statement is executed if and only if the desired member does not
exist. If an OTHERWISE-statement is not employed and the desired member does not exist,
the NO_NEXT, NO_PREVIOUS, or NO_INDEX
condition is, respectively, raised.
NUMBER (collection-name) returns the number of
members in the specified data collection.
LAST and CURRENT return, respectively, the number of members in the specified collection and the
index of the current member of the specified collection. These functions can only be used inside
an index-expression, and the collection referenced
is the one to which the index-expression applies.
NEW [ (collection-name) ] a new member of the
specified collection is created; and, if initial values
have been specified, it is initialized. This function
can only be used in an ADD or INSERT-instructions; and if an operand is not specified, a new
member of the collection being added to or inserted into is created. This function together with
the ADD and INSERT-statement constitutes the
collection-building capability of the language.
IV. Data definition
The individual members of a collection that are not
themselves collections can be any of the forms defined
in PL/1 for data elements. Arrays, lists, and rings are
defined by inserting the appropriate keyword (ARRAY,
LIST, DOUBLE LIST, RING, or DOUBLE RING)
after the collection-name in the PL/1 definition. Structures are defined as in PL/1. Thus an array of lists of
structures would be defined as:
DECLARE
1 department (20 ARRAY,
2 people LIST,
3 name CHARACTER (20) VARYING,
3 man-number BINARY FIXED,
3 projects LIST CHARACTER (10);
For those data representations that cannot be defined using the system-defined representations, the definition is supplied by providing programs which handle
the necessary manipulations on the data representation.
The form of this definition is:
Collection-name ACCESSED BY program 1;
UPDATE USING program 2;
INSERT USING program 3;
DELETE USING program 4;
The programs used in the data definition can contain any of the features provided by the system. In
addition, they can include, where applicable, references
to the addresses of an operand and the contents of an
address. Two system functions are provided for this
purpose:
ADDRESS (variable)
and
VALUE (location, from)
where location specifies where the desired value is, and
form specifies the transformation to be used to extract a value from this location. Typical forms are
(with the IBM 360's in mind) :
BF == sign + 31 numeric bits;
HBF == sign + 15 numeric bits;
QBF == sign + 7 numeric bits;
QL ==
8 numeric bits;
QB ==
8 logical bits.
These same forms could be specified in the left-hand
side of an assignment statement to indicate the form
in which a value should be stored:
y == VALUE (ADDRESS (x) + 5,HBF) +3;
the 16 bits at location (address (x) + 5) are
treated as a sign + 15 numeric bits and are added
to the number 3 and the result is stored in variable y
x-2 IN FORM BF == ADDRESS (y);
Dataless Programming
the location (address (y)) is stored in location
(x-2)in form BF
When the system passes collections as parameters
to a subroutine, it also passes the necessary data-handling routines (either the standard system routine or the
user's routine) so that the subroutine can operate on
any allowable data collection. Such routines are datarepresentation independent, and libraries of them
should provide a flexible programming environment.
One major problem not satisfactorily solved is finding
a method that allows the user to change the form of
the variables of a collection (such as from character
strings to floating point numbers) and still use the
same subroutine to process both forms. Present plans
for handling this have the user:
(l) declare those parameters which can be of different forms to the 'FREE,'
(2) perform form checking on all operations involving these FREE parameters,
(3) utilize the correct routine to handle them properly.
The user would also have to specify in the calling program which parameters to the subroutine were FREE
so that their forms could also be passed.
V. Further language features
In defining the Dataless Programming Language,
several other features seemed desirable that were not
currently available in algebraic languages in generaland specifically not in PLj 1. These features are included
here* (although they do not directly relate to the main
goal of separating data description from program description) :
(1) a source-level execute command which causes
the named statement or group of statements to
be executed, and allows the passing of parameters for this execution:
(2) a compare statement which stores the result of
a comparison in a cell associated with the label
of the compare statement, and which allows
this cell to be subsequently interrogated and, if
desired, modified;
(3) the CASE function of LISP 1.5, which permits
an expression to determine which of a series of
expressions should be used as the value of the
function.
VI. Maintaining pointers in a dynamic environment
There are two types of pointers in the Dataless Programming Languages: the generator-variables, and the
current member of each data collection. Both types
*These and other features will be fully described in a paper
now in preparation.
541
point at members of data collections, and these pointers
must be maintained while the data collections are altered.
There are two types of alterations which can affect
these pointers. The first is an insertion or deletion
from the data collection, causing a change in the location of the members of that collection (an insertion or
deletion from an array has this effect). The second is
the deletion of a member being pointed to. These pointers can be maintained by keeping a list for each data
collection of all pointers which point to members in that
data collection. While moving or deleting a member
(and its submembers), the system can check for pointers which refer to the affected members (and submembers), and take appropriate action. This action for
movement is merely the repositioning of the appropriate
pointers so that they point to the member's new location. In the case of deletion, the action taken is more
complex. First, the affected pointers are set to a state
called "undefined" (all pointers-generator-variables
and current member of all data collections-are initially
set to this state), which will cause any subsequent attempt to reference the deleted member to raise the
UNDEFINED_POINTER condition that can be handled
by an appropriate ON-unit. Secondly, internal pointers
to the next and previous members of the collection (if
they exist) are associated with the undefined pointers
so that they can subsequently be used to move to these
members. (If these members do not exist, an attempt
to use these internal pointers will cause the NO_NEXT
or NO PREVIOUS condition to be raised.) These internal pointers are also maintained through any subsequent alterations of the data collection.
VII. Implementation
Present plans call for an implementation of the Dataless Programming Language, in a restricted form,
through an editing program utilizing Leavenworth's
Syntax and Function Macros4 (which puts the program
into standard PL/1) plus a set· of run-time routines.
This method will impose certain restrictions (e.g., lists
and rings must be implemented as arrays because the
list processing capability of PLj 1 is not available) and
will be detrimental to program efficiency. But it will
enable running programs written in Dataless Programming at a relatively small cost. With experience, the
language can be improved, and plans made for a full
implementation. Although most of the capabilities of
Dataless Programming can be achieved by placing an
editor between the program and the PLj 1 compiler,
this is no way alters the fact that Dataless Programming
provides a radically different view of the programming
environment than does PL/1.
542
Fall Joint Computer Conference, 1967
V II I. Expected advantages and difficulties
Programming should be simplified because it can be
constructed top-down in terms of the logical processing
required. The problem of data representation can be
left until this programming has been completed; thus,
a more rational decision can be made concerning an
optimal representation. Because of this separation, the
programmer should be able· to think through his problem better.
The data-handling features incorporated to handle
all data homogeneously put the language into a more
canonical form, make it more mnemonic, improve its
readability, and increase its .self-documentation. This
improved readability will undoubtedly help reduce the
number of programming errors in the original programs, and make finding and correcting the remaining
errors easier. All this, in some sense, increases the
"high-levelness" of the language.
Since Dataless Programming takes care of passing
the necessary data-handling routiness to subroutines or
functions libraries of routines which are data-representation independent (within the basic ordered-list
restriction of the language) can be created for use in
a general programming environment.
Also, since data representations can be easily
changed, it is possible to determine experimentally
which is best for the given program, i.e., with reference
to the Dataless Programming system. Even so, this
would provide one objective measure for different data
representations from which criteria might be generalized
and developed for the choice of representations.
The main difficulty with the system is the level of
efficiency. Inefficiencies come from two sources: ( 1 )
the separation of the data-handling routines from the
program and from the homogeneous manner in which
all data are handled; (2) since data treated homogeneously, the programmer cannot take advantage of
the special properties of one representation in writing
a program without having already decided what representation will be chosen. It is hoped that once the program is debugged there will be ways to remedy some
of the inefficiencies.
There are several other difficulties and shortcomings
of Dataless Programming, including the incomplete
1.
2. read:
3. locate:
4.
5.
6.
7.
8.
9.
separation of data description from program description, and the lack of a method of extending the allowable set of data representations beyond ordered lists.
Also, the language is now a hodgepodge of all the
facilities considered desirable for either their processing
capabilities or convenience. As such, it is not a smooth,
polished, well-integrated system.
The essential considerations, however, are how easy
and natural is it to learn and program in the Dataless
Programming Language, and how much more powerful it is than existing languages.
IX. Dataless programming example
In the following example, the problem statement is
followed first by the uncommented program and then
by the set of comments pertaining to the program. The
numbers at the start of each line of the program are
not part of the program, but are used to associate comments with statements. Notice that almost all comments
explain the functioning of the language statements; little commentary is needed to explain the processing,
i.e., once the functioning of the various language statements has been mastered, the program itself becomes
mnemonic because the intent of the programmer is
usually apparent from the language statements themselves.
The example chosen is a problem which appeared
in he article, "APL-A Language for Associative Data
Handling in PLj."3 Since APL and Dataless Programming share many similar features, the problem affords
a means of comparison. This example was also chosen
because it illustrates many of the facilities of Dataless
Programming, including the use of functions as if they
were data, the automatic passing of the current member of a collection, the use of a generator-variable as
a bug, and the use of search expressions (with the
OTHERWISE option), iteration statements, and the
collection-building facility.
The problem is to compute the· starting and ending
dates for a set of jobs. The input data consists of a set
of entries, one for each job. Each entry consists of the
job's jobname and its duration, followed by a list of all
jobs that must be completed before this particular one
can be started. It is assumed that these dates are in
a form suitable for PLj 1 list-directed input.
ON ENDFILE GO TO compute;
GET LIST (ident);
MAKE 1ST job SUCH THAT ident == jobname CURRENT;
OTHERWISE DO;
ADD NEW TO job AND MAKE CURRENT;
jobname == ident;
END;
GET LIST (duration);
SET presen00b TO job;
Dataless Programming
543
10. read_predecessor: GET LIST (ident);
11.
IF ident == " THEN GO TO read;
EXECUTE locate;
12.
13.
ADD INDEX (job) TO predecessor OF present-job;
14.
GO TO reacLpredecessor;
15. compute:
16.
FOR EACH job SUCH THAT (all predecessors finish known
E finish date is unknown) DO;
-17.
starLdate == maxyredecessoLfinish
1;
18.
finish date == start date
duration;
19.
GO TO compute;
20.
END;
IF THERE EXISTS A job SUCH THAT finish_date_is
21.
unknown THEN
22.
PRINT LIST ('incorrect data')
23. ELSE
24.
PRINT LIST ('satisfactory run');
25. DECLARE
26.
aILpredecessors_finish_known BIT (1)
ACCESSED BY
27.
28.
IF THERE EXISTS A predecessor SUCH THAT
(finish_date_is _unknown (predecessor)
THEN RETURN ('O'B);
29.
ELSE RETURN ('I'B); ,
30.
finish_date_is_unknown BIT (1)
31.
ACCESSED BY
32.
IF_finish_date = 0 THEN RETURN ('1'B);
ELSE RETURN 'O'B);,
0
33.
34.
max_predecessoLfinish BINARY FIXED
35. ACESSED BY
36
DO;
37.
x == 0;
38.
x == MAX (x, finish_date (predecessor) ) FOR
EACH PREDECESSOR;
39. END;
40.
1 job LIST,
41.
2 jobname CHARACTER (20),
42.
2 start date BINARY FIXED INITIAL (0),
43.
2 finish date BINARY FIXED INITIAL (0),
44.
2 duration BINARY FIXED,
45.
2 predecessor LIST BINARY FIXED;
46. DECLARE
47.
ident CHARACTER (20),
48.
present job GENERATOR,
49.
x BINARY FIXED;
+
+
Comments
1
2
3
Sets up an ON-Unit that will cause transfer of
control to the statement labeled "compute"
when the end of the input file has been reached.
A PL/l input statement that causes the next
value in the input file to be assigned to the
named variable ident.
Find and make current the job that has a jobname equal to the value of ident.
4
5
6
8
An OTHERWISE-clause. These statements are
executed if and only if the search in statement
3 failed, i.e., if there did not already exist a
job that had a jobname equal to the value of
ident.
Creates and initializes a new job, adds it to the
list of jobs and makes it current.
The jobname of the newly-created job is set
equal to the value of ident.
The next value in the input file is assigned to
544
Fall Joint Computer Conference, 1967
the named variable duration (the reference
"duration" is incomplete and is completed by
using the current member of data collection
job, hence the duration of the current job is
the variable referred to).
9
The generator-variable present job is set to
refer to the current job.
10
The next value in the input file is assigned to
the variable ident. This value is the name of a
predecessor of the current job.
11
Test for the end of th~ list of predecessors. If
the value of ident is NULL, the end of the list
has been reached and control is transferred to
the statement labeled read to process the entry
of the next job.
12
This is an additional feature that causes the
specified statement· (the statement labeled
locate together with its associated OTHERWISE-clause, i.e., statements 3-7) to be executed, after which execution continues with
the next statement (statement 13). This group
of executed statements (3-7) makes current
the job whose name is the value of ident, and
if this job does not already exist, creates and
initializes it.
13
The index of the job which is a predecessor of
the job referred to by present job is added
to the collection of such predecessors.
14
Get another predecessor.
15
The input phase has been completed; calculate
the start and finish dates for the jobs.
Sequence through the collection of jobs, select16
ing those which satisfy the given condition.
(The condition is specified in· terms of two
items defmed in the data declaration.) Notice
how the details of finding the next job to be
processed are removed from the program and
can be stated in terms of the logical requirements of the process, i.e., to process a job the
finish data of all its predecessors must be
known and its own finish date must be unknown.
Calculate the start date of the current job (a
17
job selected by statement 16 above) by use of
a data item defined in the data declaration.
Again, notice how the processing has been
expressed in terms of the logical processing
required.
The finish date of the current job is set equal
18
to the start date of this job plus its duration.
Begin the search again.
19
21-24 Test for the satisfactory completion of the pro-
gram and print conclusion. If any jobs have
an unknown finish date, then the data used
in the program must be incorrect.
25-29 Definition of all predecessors finish known
as a function.
28
The collection of predecessors of the current
job is searched for one for which the finish
date of the job whose index is the value of
predecessor is unknown. If such a predecessor
exists the finish date of all the predecessors of
the current job is not known and the bit string
'O'B is returned.
.30-33 Definition of finish date is unknown as a
function.
34-39 Definistion of max predecessor finish as a
function.
40-45 Definition of the structured collection named
job.
46-49 Definition of the remaining variables.
ACKNOWLEDGMENTS
I am indebted to J. C. Shaw and Dr. Allen Newell for
their comments and suggestions on the topics contained in this paper.
REFERENCES
2
3
4
5
6
7
8
IBM operating systems/360 PL/I language specifications
IBM Form C28-6571-3 IBM Corporation White Plains
New York 1966
K C KNOWLTON
A programmer's description of L6
Communications of the ACM
vol 9 August 1966
G G DODD
APL-A language for associative data handling in PLII
AFIPS vol 29 Proc FICC Spartan Books Washington DC 1966
B M LEAVENWORTH
Syntax macros and extended translation
Communications of the ACM vol9 no 11 November
1966
A NEWELL
Information processing language-V manual
Prentice-Hall Englewood Cliffs New Jersey 1961
P ABRAHMS et al
The LISP 2 programming language and system
AFIPS vol 29 Proc FICC Spartan Books Washington DC 1966
J C SHAW
JOSS: A designer's view of an experimental on-line computing system
The RAND Corporation P-2922 August 1964
Revised report on the algorithmic language ALGOL-60
Communications of the ACM vol 6 no 1 pp 1-17
1963
PLANIT -A flexible language designed for
computer-human interaction*
by SAMUEL L. FEINGOLD
System Development Corporation
Santa Monica, California
INTRODUCTION
Time-sharing has brought about a new age in computer
usage: With the advent of time-shared systems, on-line
use of the computer will become economically feasible
for the average user; and on-line with him will be a
wealth of software utility support never before available. No longer faced with a 24-hour turnaround-the
average turnaround time in some existing time-sharing
systems is a few seconds or iess-he can perform program research, development, and checkout with ease
undreamed of heretofore.
But time-sharing also has a price: It demands that
we do something about an area that has previously
been considered too expensive to address properly. We
might call that area Computer-Human Interaction
(CHI). Before time-sharing, only fragmented CHI
could take place unless large blocks of computer time
(costing large sums of money) were dedicated to individual users. And during such costly interaction, most
of the time the computer was "idling," waiting for the
user to make an input. Now that time-sharing provides
the capability for many users to converse with the computer simultaneously and for extended periods of time,
we are faced with the opportunity-and the need-to
refine this interaction.
Many programs have now been written for time.shared use-programs for computer-assisted instruction, computer-based vocational counseling, computerassisted training, interviewing for medical history, etc.
These might all be described as interactive programs:
The user may spend an hour or more interacting with
the program at the teletype or display console.
The following discussion describes a language (and
program) called PLANIT that has proven extremely
useful for the preparation and execution of interactive
programs.
*The work reported herein was sponsored by SDC and the
National Science Foundation under Grant GY-371.
Background of the project
PLANIT (Programming LANguage for Interaction
and Teaching) is a system employing a flexible language designed for CHI. PLANIT provides for the de-.
signer a powerful and flexible tool for entering communication material into the computer, for modifying
the material, for presenting it to the user, and for prescribing the behavior of the computer as a function of
the user's current response and past performance. In
addition, the language is simple enough to allow a
nonprogrammer to use it easily.
The program and language were designed at System
Development Corporation by a study team from the
Research and Technology Division's Education and
Training Staff. The purpose of their project (supported
partially by an NSF Grant and partially by SOC's independent research program) was, in general, to explore the use of the computer in the teaching of statistics and, in particular, to develop a set of computerbased instructional materials. Initial efforts produced
a first version of the laboratory portion of a course in
statistics. A program, called STAT, was coded in a
high-level language, JOVIAL.1 This first program,
tested on nine graduate students in psychology at the
University of California, Los Angeles, was useful in
pointing out a number of problem areas in the material. Morecf> LABEL==*HIST
2. SQ.
*?
2. SPECIFY QUESTION.
*WHO INVENTED THE ELECTRIC LIGHT?
*
3. SA.
*A+THOMAS EDISON
*See Reference 7 for a detailed discussion of all frames.
548
Fall Joint Computer Conference, 1967
*B ALEXANDER BELL
*
4. SAT.
*A F:THATS VERY GOOD B:3
*B R:HE INVENTED THE TELEPHONE, TRY
AGAIN ...
*-R:
*-C:
Explanation of Frame 1
First line. All frames are, automatically, serially
numbered by the program. Here the LD chooses to
label the frame HIST. (If he chooses not to label the
frame, he will merely strike the space bar and the carriage return and pass on to Group 2. Group 1 consists
merely of the frame label.)
Group 2: SQ. The LD, not sure what SQ means,
types in the question mark (?). PLANIT immediately
repeats the group number, 2, and elaborates. The LD
then types in his question WHO INVENTED THE
ELECTRIC LIGHT? PLANIT returns with an asterisk, waiting for more lines of input. PLANIT has no
way of knowing when the LD is through with the
question group and so returns with an asterisk for
each next line. The LD ends the group by striking
the space bar once and then the carriage return key.
There is no theoretical limit to the number of lines
that can be entered in each group. We do, however,
have a practical limit of 63 lines for the entire frame.
Group 3: SA. PLANIT is asking the user to SPECIFYANSWER. The LD now enters all the anticipated
answers, tagging the first one A and the second B, etc.
The plus sign (+) next to the A indicates to PLANIT
that this is the correct answer. The LD then indicates
the end of the group by striking a space bar and carriage return.
Group 4: SAT. User is requested to SPECIFY ACTIONS to be TAKEN, depending upon which answer
the student gives.
There are four types of commands in the action
group:
F: What follows is the feedback message that is to
be presented to the student. If no message follows F:,
PLANIT will choose one randomly from its stored list
of feedback messages, according to whether the student's answer was correct or incorrect. The LD can
thus enter F: by itself, knowing that the student will not
get a monotonous YES or NO when he enters an answer. (Responses are usually one-word messages such
as FINE, YES, CORRECT, NO, WRONG.)
R: This command instructs PLANIT to wait for
another answer without printing the question again.
It can be entered along with an appropriate message
such as in the above example. In this case the student
receives the feedback: HE INVENTED THE TELE-
PHONE, TRY AGAIN; and PLANIT then waits for
another answer. R: by itself instructs PLANIT to print
out a fixed message (WRONG, TRY AGAIN) and
wait.
C: This command used alone instructs PLANIT to
print out the fixed message: THE CORRECT ANSWER JS, followed by the correct answer (indicated
by the plus sign in Group 3). C: can be followed only
by another command-F:, R:, B: or a CALC statement. For example, C: COUNT :=COUNT* 1 or C:X
==FACT(3). This puts PLANIT in the CALC mode.
COUNT is an item in CALC, as is X. Here COUNT is
to be incremented by one and X is set equal to FACT
(3), i.e., the factorial of 3.
B: This instructs PLANIT to branch (B: 3 means
BRANCH TO FRAME 3). All frames are numbered;
they can also be labeled, and a branch can be made to
any numbered or labeled frame. In addition, B:LSNAM
(where LSNAM is the name of another lesson) means
that the lesson LSNAM will now be brought into PLANIT and exe~uted as a part of the current lesson; the student will never know the difference. Upon completion of
the lesson LSNAM, PLANIT will continue with the next
frame in the original lesson. B: by itself causes PLANIT
to return to the calling lesson. For example, if during
lesson AA the command B:BC is encountered (where
BC is a lesson name), lesson BC will be called and run
until the command B:, in lesson BC, automatically
returns PLANIT to lesson AA. Similarly, B:PROGM
means branch to the program whose name is PROGM.
When PROGM relinquishes control, execution continues with the next frame in the calling lesson.
The first user ipput in Group 4 is read as follows:
If the student gave answer A (THOMAS EDISON),
print out the message: THATS VERY GOOD and
branch to Frame 3.
The second input is interpreted as follows: If the
student gave answer B, print out: HE INVENTED
THE TELEPHONE, TRY AGAIN ... and wait for
another answer.
The third input, prefaced by a minus sign, indicates
an action to be performed if the student's answer did
not correspond with either A or B-namely, for any
unanticipated response, wait for another answer. (In
this case, since nothing appears after the R:, PLANIT
then prints out the fixed message: WRONG, TRY
AGAIN, and waits for another answer.)
The LD terminates the group and thereby the frame
by striking the space bar and the carriage return key.
The space bar and CR alone on any line will terminate the group. The dollar sign ($) and CR alone
on any line will terminate the frame. If, for example,
the LD (in the middle of Group 3) decided to end
the frame and proceed to the next frame, he would
PLANIT
only have to enter the $ and CR alone on a line and
PLANIT would respond with:
P/O/M/D/C.
User may then, to give another illustration, build a new
lesson as follows:
*0
FRAME 2.cpcp LABEL==*MATH
2. SO.
*LETS SEE WHAT YOU REMEMBER ABOUT
TEMPERATURE. USING F FOR DEGREES
*FAHRENHEIT AND C FOR DEGREES CENTIGRADE, WRITE THE FORMULA FOR
*CONVERTING FROM DEGREES FAHRENHEIT TO DEGREES CENTRIGRADE.",
*HINT:
F==9*C/5+32 CONVERTS FROM
CENTIGRADE TO FAHRENHEIT.
*
3.
SA.
*cp FORMULAS ON
*A+C== (5/9) * (F-32)
*B F==9*C/5+32
*C C==(5/9) *F-32
*
4. SAT.
*A F: B:7
*B R:YOUR ANSWER IS THE SAME AS THE
ONE I GAVE YOU, TRY AGAIN ...
*A F: NOW YOU'VE GOT IT. B:15
*B R:YOU'RE STILL CONVERTING FROM
CENTIGRADE TO FAHRENHEIT, TRY
AGAIN . . .
*BC F:NOTE THE DIFFERENCE. C: B:OUT
*-R:
*-C:
*
Explanation of Frame 2
First line. The LD labels this frame MATH.
Group 2. SQ. The LD enters his question. Notice
the back slash ("') after CENTIGRADE on the third
line. This instructs PLANIT to skip a line after printing out CENTIGRADE-to set off the following HINT.
For example:
LETS SEE WHAT YOU REMEMBER ABOUT
TEMPERATURE. USING F FOR DEGREES
FAHRENHEIT AND C FOR DEGREES CENTIGRADE, WRITE THE FORMULA FOR
CONVERTING FROM DEGREES FAHRENHEIT
TO DEGREES CENTIGRADE.
HINT: F==9*C/5+32 CONVERTS FROM CENTIGRADE TO FAHRENHEIT.
The """-." can be used anywhere in Group 2.
Group 3. SA. This group illustrates the algebraic
matching ability of PLANIT (activated by the expres-
549
sion: cp FORMULAS ON). The student can type in
any equivalent algebraic form of the correct answer
and get full credit for it; e.g., C==(F-32) *(5/9),
C==5*(F-32)/9, C==(5*F-160)/9, etc., are all
equivalent and therefore acceptable forms. If FORMULAS is not turned on (or is deactivated by the expression: cp FORMULAS OFF), then only the exact
form as typed in by the LD would be looked for in
the answer. This, of course, is not true symbol manipulation; we merely employ a technique which (in part)
includes performing algebra on the student's answer.
The match!ng technique is not restricted to correct
answers alone but works for all anticipated answers
in Group 3.
Group 4. SAT; This group illustrates repeated use
of a frame. The first time. through this frame, if the
student's answer corresponds to:
A-he receives a (randomly selected) feedback
message followed by a branch to Frame 7.
B-he receives the feedback message: YOUR ANSWER IS THE SAME AS THE HINT I GAVE YOU,
TRY AGAIN ...
C-he receives: NOTE THE DIFFERENCE. THE
CORRECT ANSWER IS: C==(5/9)*(F-32) ...
followed by a branch to the frame whose label is OUT.
If he gives an unanticipated answer (neither A, B, nor
C), he receives the message: WRONG, TRY AGAIN.
The second time through the frame, if the student's
answer corresponds to:
A-he receives: NOW YOU'VE GOT IT. PLANIT
then branches to Frame 15.
B-he receives: YOU'RE STILL CONVERTING
FROM CENTIGRADE TO FAHRENHEIT.
TRY AGAIN ...
C-he receives the same message as in C above.
If no match (second unanticipated answer), he receives: THE CORRECT ANSWER IS C==(5/9)*
(F-32). PLANIT will then go on to the next frame
in the sequence.
If the student goes through the frame a third time,
or more, and gives an answer corresponding to:
A-he receives the same feedback as for A the
second time through.
B or C-he receives the same feedback as for C
above.
Unanticipated answer-he receives the same feedback as for unanticipated answers the second time
through.
Note: Several commands (F: C: R: B:) occurring
on one line are performed in the order of their appearance from left to right.
If there is no Group 3, then all commands in Group
4 will be executed, and there will be no pause for the
student's answer.
550
Fall Joint Computer Conference, 1967
Let's go on to another example frame illustrating
the PHONETIC and KEYWORD routines.
P/Q/M/D/C.
*Q
FRAME 3.¢¢ LABEL==*PRES
2. SQ.
*WHO WAS THE FIRST PRESIDENT OF THE
USA?
*
3. SA.
*¢ PHONETIC ON
*¢ KEYWORD ON
*A+GEORGE WASHINGTON
*B ABE LINCOLN
*C+G. WASHINGTON
*
4. SAT.
*A F: B:SOMEPLAC
*B R:HE WASN'T THE FIRST, TRY AGAIN ...
C: COUNT==COUNT+l
*C R:SPELL HIS FIRST NAME.
*
Explanation of Frame 3
First line. The LD labels it PRES.
Group 3. SA. Two different correct answers are
designated above by the letters A and C. This is perfectly
acceptable to PLANIT. However, when the command
C: is used, the correct answer printed out will always be
the last one with the plus sign. This group also illustrates the use of the phonetic and keyword matchers.
The phonetic matcher encodes all answers into their
phonetic equivalent. The keyword function looks for
the answer or answers designated by the LD anywhere
in the student's response. Both phonetic and keyword
are turned on, as shown in Group 3. The zero in front
of PHONETIC ON and KEYWORD ON tells PLANIT
to perform this function before any answers are matched.
Their combined use would cause PLANIT to accept the following answer as correct: I THINK IT
WAS JEORGE WASHINGTUN. KEYWORD does
not accept the answer in reverse order; i.e., WASHINGTON GEORGE would not be accepted. However,
if FORMULAS was turned on too, then either order
would be accepted.
(M) THE MULTIPLE CHOICE FRAME
The M frame is built exactly the same as the Q frame.
The only difference is that during the execution of the
lesson, the choice of answers (in Group 3) is printed
out. The plus sign, if any, is omitted of course.
(P) THE PROBLEM FRAME
The use of this frame is rather specialized. Three
kinds of information may be inserted here by the LD:
• Probability distribution parameters for generating
data in the form of random samples, e.g., means,
variances, and correlation coefficient for a bivariate Gaussian (normal) distribution. The random
data would actually be generated for student use
during the execution, for example, of a statistics
lesson (the LD can also specify headings and
format for the actual printing of the data).
• Steps to the solution of a problem in which the
random data will be used (the student receives one
step at a time in response to his request "STEPS").
• Controls over the mathematical functions which
shall (or shall not) be made available to the student when he attempts to solve a particular problem.
In addition there is another less specialized use for
this frame. The LD may insert here the names of files
(data bases) that can be used by PLANIT to search
for answers to questions posed by students.
(C) THE COPY FRAME
The Copy frame is more of a building aid than a
frame in its own right. It allows one to copy and modify
any frame previously built in the same lesson and to
include it in the frame presently being built.
(D) THE DECISION FRAME
As previously illustrated, all branching decisions are
made as a function of what actions have taken place
during execution of the frame. The Decision frame
affords the LD the opportunity to consider branching
decisions (and other forms of program behavior) as a
function of the student's past performance, that is, as
a function of results that have taken place during execution of a set of frames. Since our goal is to provide
the user with a language for handling- quickly, naturally, and easily-the kinds of problems that one encounters in CHI, we devised a "language" for describing patterns of past performance. This language takes
two basic forms.
The first form, called the pattern form, allows one
to inquire if the student took a particular path through
the material. For example, let us imagine the student
went through Frame 1, answered A or C, and followed it by Frame 5 (in which he responded incorrectly), and then followed that by Frames 10 through 15,
where the student was correct. An inquiry concerning
whether or not the student went through that pattern
exactly with no deviations can actually be written in
the language pretty much as it has been stated. For
example:
IF I,AC 5,- 10-15,+
This, then, is the form of the pattern question. If the
query is answered affirmatively, one can then use any
combination of the three action commands:
F:, C:, and B:.
The second form permits queries about summarized
student performance over a set of frames. For example,
PLANIT
one may want to know if the student got less than or
equal to five right out of Frames 10 through 22 and
Frames 30 and 33. This can also be written, almost as
stated, in the following manner: IF LQ 5 RIGHT
10-22,30,33. Similarly, if these conditions are satisfied,
any of the three commands can then be executed. In
place of RIGHT, one can substitute WRONG, SEEN,
MINUTES, USED. With USED, one can have any
function like FACT (factorial), SIN, COS, etc. For
example:
IF GQ 5 MINUTES 10-15 B: 10
IF USED SIN 6 B:7
means: If the student spent at least five minutes on
Frames 10 through 15, then branch to Frame 10. The
second IF statement reads: If he used the function SIN
in Frame 6, then branch to Frame 7. Also, in place of
GQ one can substitute LS for less than, GR for greater than or other relationals such as LQ, NQ, EQ.
Finally one can use IF statements to query the contents of items set in the calculation mode. IF IQ LS
50 B: WORK means: If the item whose name is "IQ"
contains a value less than 50, branch to the frame whose
label is "WORK."
All these forms can be connected as one large statement via the connectives
AND and OR, e.g.:
IF 1,AC 5,- 10-15,-+
OR GQ 5 MINUTES 10-15 AND USED SIN 6
AND IQ LS 50 B:WORK
The above examples illustrate only a few uses of
PLANIT. In the calculation (CALC) mode, these
same capabilities can be turned to mathematical subject matter. CALC provides a powerful computing
capability; arithmetic expressions can be instantly
evaluated, mathematical functions can be defined, and
a number of stored functions (such as the generation
of pseudorandom numbers) and primitives (e.g.,
FACT(N) ~ N!) are available to teacher and student. If, for example, the student is operating in the
execution (EX) mode and working on a lesson frame
that requires him to perform computation, he may enter
the CALC mode by typing a left arrow, instruct the
machine to perform the desired operation, and receive
an immediate answer, as illustrated:
Dialogue
Current and future uses
Materials produced via PLANIT are: Instructional
sequences in statistics (aimed at students of the social
sciences enrolled in a first course in statistics); spelling
and vocabulary (for children three to eight years);
economics (for undergraduates); introduction to computer programming (for persons having some knowledge of algebra). Agencies who have used or are
using PLANIT are: System Development Corporation, Southwest Regional Laboratory, University of
California at Los Angeles, University of Southern
California, University of California at Irvine, United
States Naval Personnel Research Activity (San Diego,
California), New England Educational Data System,
and Lackland Air Force Base.
In view of PLANIT's interactive and evaluative
capabilities, one can readily employ the system for
other applications. For example, it is being currently
used in the development of a computer-based vocational
counseling program, and is being adapted for use in
administrative planning and management. Its usefulness in this area will be greatly enriched by the CALC
capability.
The PLANIT system, now operating on SDC's Q-32
time-sharing system, will soon be available for use on
the IBM 360/65. In the near future we hope to make
conversion to other smaller computers such as the
IBM 360/30.
ACKNOWLEDGMENT
The author wishes to acknowledge the work of Dr.
Charles Frye of System Development Corporation
who was co-developer of the system.
REFERENCES
M H PERSTEIN
Grammar and lexicon for basic JOVIAL
System Development Corporation Santa Monica California Technical Memorandum TM-555/005/00 10
May 1966
2
D L BITZER J A EASLEY
PLATO: A computer-controlled teaching system
In M A Sass and W D Wilkinson Eds Symposium on
computer augmentation of human reasoning Spartan
Books Washington D C pp89-103 1965
3
IBM 1401 1440 or 1460 operating system computer
assisted instruction
IBM Reference Publication C24-3253-1 Rev
International Business Machines Corporation 1964
4
L M STOLUROW
Systems approach to instruction
University of Illinois Training Research Laboratory
Technical Report no 7 July 1965
Explanation
Defining of function A(X,Y) to
*FUNCTION
A(X,Y) ~ X*Y be equal to the product of X and Y.
System: IN
Using the function with arguments
User:
*A(5,4)
5 and 4.
System: 20.0
*A(7,FACT(3) ) Using the function with arguments
User:
7 and the factorial of 3.
System: 42
User:
551
552
Fall Joint Computer Conference, 1967
5
A manuaL for BASIC, the elementary aLgebraic language
designed for use with the Dartmouth Time Sharing System
Dartmouth College Hanover New Hampshire 1 January 1965
J M NEWTON
ONR conference on CAl languages
Report of material presented at conference March 2-3
1966 Cambridge Massachusetts ENTELEK Incorpo-
6
rated Newburyport Massachusetts
cal report
7
unnumbered techni-
S L FEINGOLD C H FRYE
User's guide to PLANIT
System Development Corporation Santa Monica California Tech Memo TM-3055/000/01 17 October
1966
A formal system for the specification of the syntax and
translation of computer languages*
by JOHN J. DONOVAN and HENRY F. LEDGARD
Massachusetts Institute of Technology
Cambridge, Massachusetts
INTRODUCTION
This paper presents two basic results: the use of
established methods of recursive definition to present
a single method to
1. specify the syntax of computer languages (including contextsensitive requirements, such as
the restrictions implied by declaration statements),
2. specify the translation of programs itt one computer language into programs in another language.
The method can be used to write one specification
for both the syntax of a language (e.g. a source language) and its translation into a target language (e.g.
an assembler language). A syntactically legal program
and its translation into the target language can then
be generated Wi.ng the specification. If the target language is understood, the semantics of the first language is specified.
The paper develops the method of recursive definition in conjunction with an example specifying the
syntax of a limited subset of PL/I (including declaration, arithmetic, and conditional statements) and its
translation into IBM System/260 assembler language.
Background
Our objective is to present a single method for expressing the syntax and translation of computer
languages. The method was presented and first
applied to specify only the syntax of computer languages in an earlier work by Donovan. 4
The objective to develop methods for specifying
either the syntax or the translation of computer
*Work reported herein was supported (in part) by Project MAC, an
MIT research program sponsored by the Advanced Research Projects Agency, Department of Defense, under Office of Naval
Research Contract Number N onr-41 02(0 1).
languages is not new. In response to the demand for
numerous problem-oriented computer languages to
meet the needs of diverse fields, there has been
considerable activity to ease the effort required to
define and implement a language.
Much of this activity has led to the development of
methods for specifying, at least in part, the syntax of
computer languages. 9 - 14 The methods for specifying
syntax have facilitated the description of computer
languages to members of the computing field and have
led to the development of syntax-directed translators. 25 -28 However, most of the methods for specifying syntax have been shown to be equivalent to
,context-free phrase structure grammars and hence
inadequate13.23.24 for completely characterizing the
syntax of computer languages. For example, some
programming languages require that all statement
labels in a program be different, that reference labels
refer to existing statement labels, that the arithmetic
type of a variable be declared, or that the dimensions
of an array be declared before referring to an element
within the array. In a Fortran program, for instance,
the statement "GO TO 20" is not legal unless "20"
occurs as a statement label in the same program. Restrictions like these cannot be specified by a contextfree grammar. We consider these restrictions to be
syntactic in that programs violating these restrictions
are never translated, but are rejected solely on their
form. Debate as to whether these restrictions are syntactic or semantic is immaterial when we wish to
specify both the syntax and translation of a language,
because then all these restrictions' must be satisfied.
Other activity has been directed to developing
table-driven compilers 27 ,28 and programming languages
for expressing string transformations. 2o ,21 The tabledriven compilers have generally been limited to a
particular type of target language and have required
excessive detail in writing the specifications to fill
553
554
Fall Joint Computer Conference, 1967
the tables for a particular source language. The string
transformation languages have been limited to special
types of string transformations and have not been
found generally useful for translating computer languages. Approaches to the formalization of the semantics of computer languages have also been made. 16- 19
Here we present a single, formal method for specifying completely the syntax and translation of a computer language. The method is independent of both
the source and target languages. The method uses an
uncluttered, readable notation. The method recursively classifies sets of strings. The syntax of a
computer language is characterized by specifying a set
where each element is a syntactically legal program.
The translation of a computer language is characterized by specifying a set of ordered pairs, where the
first element of each pair is a syntactically legal
program in the source language, and the second
element is a corresponding program in the target language that preserves the meaning of the source language program. If the target language is understood,
the semantics of the source language is specified.
The paper develops the method of recursive definition with an example specifying the syntax of a limited
subset of PL/I and its translation into IBM System/
360 assembler language. The power of the method of
recursive definition is discussed and an ordered set
of appendices is presented. The appendices present:
1) a brief summary of the notation for the method of
recursive definition, 2) two programs in the subset
of PL/l and their translation into System/360 assembler language, 3) a Backus-Naur Form specification of the syntax of the subset of PL/I, 4) a complete specification of the syntax of the subset using
the method of recursive definition, and 5) a complete
specification of the syntax of the subset and its translation into System/360 assembler language using the
method of recursive definition.
Basis offormalization
The formalization for the method presented here
evolved from Post's canonical systems, I and hence
will be called canonic systems. Smullyan2 used an
applied variant of the canonical systems of Post in
his definition of elementary formal systems. In class
notes on the application of elementary formal systems
to the definition of self-contained mathematical systems, Trenchard More3 modified the definition of
elementary formal systems. Elementary formal systems (now called canonic systems in recognition of
the earlier work by Post) were further modified to
meet the definitional needs of computer languages
and applied to the definition of syntax by Donovan. 4
Canonic systems were later applied by Ledgard 5 to
specify the translation of computer languages. This
paper is a synthesis of the last two works.
Canonic systems, which are equivalent to elementary formal systems, can be used to specify any
recursively enumerable set. 2 Smullyan used elementary formal systems as the basis for his entire study
of formal mathematical systems and recursively
enumerable sets. We use canonic systems to define
two examples of recursively enumerable sets, the
set of syntactically legal programs comprising a
computer language, and the set of ordered pairs
specifying the translation of programs in one language
to programs in another language. We may feel confident that canonic systems can specify any programming language, or more generally, any algorithm or
translation that a machine can perform. This confidence is a direct consequence of the works by
Turing34 •35 and Kleene. 36 Here the notion of "recursive sets" (which are encompassed by canonic systems) was shown equivalent35 •36 to the notion of
functions computable by a "Turing machine", and
functions computable by a Turing machine were
asserted34 to comprise every function or algorithm
that is intuitively computable by machine.
Canonic systems
A canonic system is a finite sequence of rules for
recursively defining sets. The elements of the sets
are strings of symbols selected from some finite
alphabet. Each rule is called a ~. A canon generally has the form
at set Al
9-
a 2 set A2
+ ... ,.
an set An
r b set· B.
which may be interpreted informally:
If "at" is a member of the set named "set At", and
"a2" is a member of the set named "set A g " , ••• ,
and "an" is a member of the set named "set An",
then we can assert that "b" is a membei=Ofthe
set named "set B".
The "at and "b" represent symbols from the finite
alphabet; the "set At and "set B" are the names of
the sets defined-.- --In the remainder of this section we will elaborate
on this notation. A synopsis of the notation is given
in Appendix 1. and may be used as a reference
throughout the text. The notation will be developed
by a series of examples taken from the canonic system specifying the syntax of a subset of PL/I, called
Little PL/1. This subset includes limited forms of
PL/I GO TO statements, IF statements, label assignment statements, label declaration statements, and
lrithmetic assignment statements. The Backus-Naur
Formal system for specification of syntax and translation of computer languages
Form description of the subset is given in Appendix
3. Two example syntactically legal programs in the
subset are given in Appendix 2. One of these examples
is repeated here:
Q:
PROCEDURE;
DECLARE LX LABEL;
L:
I = 1+IAxIB-IC;
LX=L;
GOTO CHECK;
M:
1=1+ 1;
LX=M;
CHECK: IF I < LIMIT
" THEN "GO TO LX;
ENDQ;
We define the syntax of a language as the set of
rules for specifying the strings that can be recognized
by a translator and translated into some other language. The set of rules excludes strings that the
translator would reject solely on their form. The syntax of Little PL/l has the following restrictions, which
for all practical purposes make Little PL/I contextsensitive and therefore impossible to completely
characterize in Backus-Naur Form:
1. Different declarations of the same identifier are
in error. i.e.
a. The lists of fix-pt variables, statement labels
and declared label variables for a program
must be mutually disjoint, and
b. the label before PROCEDURE must not
occur within the procedure block.
2. The label after END must be identical to the
label before PROCEDURE.
3. All statement labels must be different.
4. The identifier in a GO TO statement must refer
to an existing statement label or a declared label
variable.
5. The identifier on the left hand side of the "="
in a label assignment statement must refer to a
declared label variable; the identifier on the
right hand side of the "=" must refer to an
existing statement label or a declared label
variable.
We begin our discussion of the notation for canonic
systems by specifying a set named "letter". The
canons for this set are as follows:
(1)
(2)
~ Z letter
These canons may be read:
(26)
555
(From no premises) we can assert that the symbol
"A" is a member of the set named "letter".
(From no premises) we can assert that the symbol
"B" is a member of the set named "letter".
And so on.
The canons specify a set named "letter" comprising
the capital letters of the English alphabet. The sign
"~" is the assertion sign. The strings "A letter",
"B letter", ... , and "Z letter" are conclusions. The
capital English letters A through Z are members of
the object language. The underlined, lower case
characters are predicates. A predicate, here "letter",
is the name of a set.
The set named "identifier" may be specified in
terms of the set named "letter":
Ll
Ll
r
letter
.t 1 identifier
letter ~ J. 2 letter ~ 11..£2 identifier
(27)
(28)
(34)
These canons may be read:
If "il" is a member of the set named "letter", then
we can assert that ".11" is a member of the set
named "identifier".
If "Ll" is a member of the set named "letter" and
".12" is a member of the set named "letter", then
we can assert that ".It1.2" is a member of the set
named "identifier".
And soon.
The canons* specify a set consisting of identifiers of
one to eight capital English letters. The lower case
(possibly subscripted or superscripted) English letters
rll through I.H are variables that represent members of
the set named "letter". The strings "ott", ".1112" are
li!mls. A term is a string of variables or symbols from
the object alphabet (e.g. ")1", "1 112", or "AJ 1J2")·
The sign ''f' is the conjunction sign. The strings
....l1 letter", "/2 letter", ....la letter" are premises. The
"i-" before an "F' separates premises, all of which
must be satisfied to assert the conclusion. The
strings ".II letter", ".tl identifier", "tl2 letter", ".l1.A.2
identifier" are remarks. A remark is either a premise
or a conclusion.
*Actually, these canons should properly be called canon schema,
which denote instances of canons.
556
Fall Joint Computer Conference, ) 967
The vocabulary used to describe a canon is summarized as follows:
..tl letter
~
,(1
identifier
~riable
L-J
~riable
'
term predicate term predicate
,
premise
«
,
remark
+... t
Cn
2. If t 1 ,t 2 , ••• , tn are terms denoting members of the
same set named "S", the remarks
tnS
tIS +- t2 S 1- ...
may be abbreviated
t 1ft 2? .. ;tnS
t-
'L.-I
'
may be abbreviated
Q ~ C t i- C 2
,
Thus the canons for "letter" may be abbreviated with
abbreviation ):
conclusIOn
~emark
canon
To demonstrate the property of recursion in canons,
we define a set named "list". The set named "list" is
needed in the canonic system for the syntax of Little
PL/I to specify the requirement that the list of all
reference labels for a program must be contained in
the list of all statement labels. The canons for the set
named "list" are as follows:*
~ Alist
(35)
i identifier ~ i, list
a list t b list f- ab list
(36)
(37)
We can use canons (1) through (37) to derive the conclusion that the string "A,BB,A," is a member of the
set named "list". Using canon (I) we can assert that
"A" is a member of the set named "letter". Using
canon (27) we can assert "A" is a member of the set
named "identifier". Using canon (36) we can assert
that "A," is a member of the set named "list". Similarly, using canons (2), (28), and (36) we can assert
that "BB," is a member of the set named "list". Since
the premises "A, list" and "BB, fu.!" have been
asserted, we can use the instance of canon (37)
A, list 1- BB, list ~ A,BB, list
to assert that "A,BB," is a member of the set named
"list". Using canon (37) again (recursively) and letting
"7 denote the list "A,BB," and "b" denote the list
"A," we can assert that "A,BB,A," is a member of
the set named "list".
The repeated use of the same predicate names in
the above canons strongly suggest the use of two
abbreviations:
1. If C 1 ,C 2 , ••• C n are conclusions with identical
premises Q, the canons
Q ~Cl
Q ~C2
r A letter t B letter t ... 1- z letter
or further abbreviated with abbreviation 2:
r AfBr· .. 4'Z letter
The canons for "identifier" may be abbreviated*
.e t?.tA' .. ·t.tH letter ~
1?.t1.L2?' ..
?.JI.£:!.13t..l}:;A(iI7.~H identifier
This canon may be read:
If ".It", "J.2", . .. , and "~H" are members of the set
named "letter", then we can assert that ",P t " ,
".tt-.i2", ... , and "J.Ii.2~;1J.41.5I.f;.J7lH" are members
of the set named "identifier".
We also introduce the following abbreviation:
3. In cases where many canons have some common
premises, a block structure abbreviation may be
used. The common premises are stated once and
understood to be added to the premises of all
canons within the scope of the common block.
This abbreviation greatly eased the writing of the
specification for the syntax of the simulation language
GPSS.4 There was no need to incorporate this abbreviation into the canonic system of Little PL/I. An
abbreviation of two or more canons is formally called
an edict. However, we will usually refer to edicts as
canons.
Thus far we have specified only sets of I-tuples, i.e.,
predicates of degree I. For a complete specification
of Little PL/I, we will have to specify sets of n-tuples
for n greater than 1, i.e., predicates of degree n, n> I.
We use the notation
to denote an ordered n-tuple. The sign "<" separates
elements of an ordered n-tuple. For the requirement
that the list of reference labels for a Little PL/I program be contained in the list of statement labels, we
specify a set named "in". The predicate "in" names
the set of all ordered pairs such that the second ele*To obtain the given abbreviation for "~", we must first
change the premises of each of the eight unabbreviated canons to
"It liill£r f- J2 ~
1- Jsletter". This change does not effect
the validity of the canons.
t ...
*The symbol "A" denotes the null string.
L
Formal system for specification of syntax and translation of computer languages
ment is a list of identifiers and the first element is
a list of identifiers contained in the second list.
The set named "in" is defined:
~btc list ~ in
<~J> ill
in t-
t
(38)
(39)
ill
To suggest more strongly the relationship among the
elements of an n-tuple, we allow premises and conclusions of the form
text 1 text2 ... textn
-1
to be written
al text 1 a z text2 ... textn
an
-1
Thus the canons for "in" become
(38)
(39)
afbtc list ~ b in abc
a ill 1. cr b in.l ~ ab in,t
These canons may informally be read:
If "a", "b", and "c" are lists, then we can assert
that the list "b" is contained in the list "abc".
If the list "a" is contained in the .list 4' l" and the
list "b" is contained ;" the list "~", then we can
assert that the list "ab" is contained in the list
"~I"~.
The following conclusions can be derived from canons
(1) through (39):
A, in A,B,
A,A, in A,
R,S, in S,T,R,
ALPHA, in ALPHA,BET A,
Finally, we extend the use of the symbol '~' to
abbreviate the writing of n-tuples by allowing remarks
of the form
al text 1 a z text 2 ... textn -1 an
a'l
~1
a'z
~2 •••
textn '-1. a'n
to be abbreviated
alta' I ~ az+a' z !lli3. ... textn
-1
anfa' n
Thus canon (39)
ainJi-binJ I-abin'"
(39)
may be abbreviated
(39)
Canonic system specification of syntax
This section is concerned with the motivation and
development of a canonic system for the syntax of
Little PL/I, including context-sensitive requirements.
Our approach will be to specify eventually a set of
557
I-tuples named "PL/I program". Each member of this
set will be a syntactically legal Little PL/I program.
The entire canonic system specification of this set is
given in Appendix 4. The numbers of the BNF productions of Appendix 3. and the canons of Appendix
4. correspond in that productions and canons with
corresponding numbers specify corresponding syntactic constructions.
The sets of letters and digits are specified by canons
1. and 2. of Appendix 4. An identifier in Little PL/I
is a string of one to eight letters. Canon 3. specifies
the set of identifiers. Similarly, the set of unsigned
integers, whose members are strings of one to ten
digits, is specified by canon 4. Little PL/l has only
fixed-point arithmetic variables. Canons 5.1 and 5.2
specify the set of fixed-point variables. Canons 6.
and 7.1 specify the set of labels and label variables.
To specify the restriction that a reference label in
a GO TO statement be contained in the list of statement labels or that all label variables for a program
be contained in the list of declared label variables, we
define the sets named "list" and ':ill' (canons 7.2
through 7.6). The canons for "list" specify a set of
lists, where each list is a sequence of identifiers
separated by commas. The canons for "in" specify a
set of ordered pairs of lists, where each identifier in
the first list is contained in the second list.
To specify the restrictions that the sets of fixedpoint variables, statement labels, declared label
variables, and the procedure label for a program must
be mutually disjoint, we define the set of ordered pairs
named "disjoint" (canons 7.10 through 7.13). The first
element of each ordered pair is a list of identifiers; the
second element of each pair is a list of identifiers,
none of which appears in the first list. For example,
the ordered pair "" is a member of
this set. To define the set named "disjoint", we first
define a set named "differ" (canons 7.7 through 7.9).
Members of the set named "~" are ordered pairs,
in which the first element is an identifier and the
second element is a different identifier.
Canons 8.1 through 18.4 specify the constructions
for Little PL/I primaries, GO TO statements, relational operators, boolean expressions, IF statements,
label assignment statements, arithmetic assignment
statements, and label DECLARE statements. For
example, with every GO TO statement we keep track
of its reference label (to check later if it is in the list
of statement labels) or keep track of its label variable
(to check if it is in the list of declared label variables).
Thus we define the canon for a GO TO statement:
llabel t- GO TO I.; go to stm with ref label ~,
label var A
(9.1)
558
Fall Joint Computer Conference, 1967
This canon specifies a set of 3-tuples named "goto stm
with ref label-label var". The first element of a 3-tuple
is a GO TO statement, the second element the reference label for the GO TO statement, the third element
the label variable for the GO TO statement. The
canon has the following instance:
A label ~ GO TO A; goto stm with ref label A,
label var A
or
r
A label
goto stm
with ref label-label var
r
Likewise, with every arithmetic assignment statement
we keep track of the list of its fixed-point variables
(to check later if the list of fixed-point variables for
a program is disjoint from the lists of statement labels,
declared label variables, and procedure label for the
program). Hence the canons for an arithmetic expression and an arithmetic assignment statement
specify sets of ordered pairs, in which the second
element of each pair is the list of associated fixedpoint variables. In the same manner, we define a set
of ordered 4-tuples to specify an I F statement, a set
of ordered 3-tuples for a label assignment statement,
a set of ordered pairs for a DECLARE statement.
Canons 19.1 through 19.4 specify a statement
sequence consisting of a single (possibly labeled*)
statement. Canon 20.1
sts' stm seq with stm label§ .lstJ' s ref labels .Irf..t' r
label vars ,tift' v decl label vars ~vcfi~' vd
fix-pt vars vtv '
1s disjoint J.' s
(20.1)
~ ss' stm seq with stm labels lsi's ref labels J'rJ'r
label vars Pv./v' decl label vars ~vdJ.' vd fix-pt vars vv'
t
specifies a statement sequence of two or more statements. This canon may informally be read
If "s" is a stm seq with stm labels "is", ref labels
".tr", label vars ".Iv", declared label vars "R.vd'"
and fix-pt vars "v",
and "s" is a stm seq with stm labels "/'s", ref labels
",I'r" , label vars "l' v" , declared label vars
"P'Vd"', and fix-pt vars "v"',
and the list of stm labels "is" is disjoint from the
list of stm labels "Ils''',
then we can assert that "ss'" is a stm seq with stm
labels "Isl.'s", reflabels "I. rl.'r", label vars ".P. v t'v",
declared label vars ",J.V(]J;' vd", and fix-pt vars
"vv'''.
*The element "stm labels" for a labeled DECLARE statement is
given as "A" since statement labels for DECLARE statements are
ignored in PL/I.
The premise "Ps disjoint J.' s" insures that the statement labels for each statement sequence are different.
Canon 20.2
s stm seq with stm labels 1.s ref labels .i r label vars ~v
decl label vars Lvd fix-pt vars v 1- v disjoint ls,fvd
1- .ls disjoint .tvd 't,lr in.is .tv in;. vd
(20.1)
s legal stm seq with stm labels ,l.s ~ .tvdV
+
r
specifies a syntactically legal statement sequence.
The premises "v disjoint '.tsr,LVd" and "~s disjoint .lvd"
insure that the lists of declared label variables, fixedpoint variables, and statement labels for a Little PL/I
program are mutually disjoint. The premises "I.r in Is"
and ".tv in. .t.Vd" insure that all reference labels refer
to existing statement labels and that the label variables
used in the label assignment and GO TO statements
are declared.
Finally, canon 21.
t s legal stm seq with stm labels R.s V.ill:§ v
1-1., disjointlsv r R.: PROCEDURE; sEND.l;
J. label
PL{I program.
specifies a syntactically legal PL{I program. The
premise "R., disjoint l. s v" insures that the procedure
label "f' is not used within the statement sequence
for the program. The set named "PL{I program" is
our desired set, the set of I-tuples such that each
member of the set is a syntactically legal Little PL{I
program.
We thus state our first basic result:
1. The language of canonic systems can be used to
specify (exactly) the syntax of a computer language.
Canonic system specification of translation
We know that theoretically, at least, the translation of programs from one computer language to programs in another computer language is a process that
can be expressed by a canonic system. We can view
every translator as specifying a function from one set
of strings to another. Since the translation of programs is a task performed on computers, we can assert
that the function specifying the translation is recursively enumerable and hence can be specified by a
canonic system. The ordered pairs defining the function comprise the recursively enumerable set. The
first element of each ordered pair is a program in one
language, the second element its translation into the
target language.
We use this last fact to motivate our development.
We will develop the specification for the translation of a language by
a. modifying the specification of the syntax of the
language to distinguish further the semantically
Formal system for specification of syntax and translation of computer languages
different strings (e.g., the set of arithmetic
operators +, -, *, and / will be split into two sets,
one for the addition operators + and - and one
for the multiplication operators * and I), and
b. appending to each .n-tuple specifying a translatable string one more element specifying a
corresponding string in some other language that
preserves the meaning of the first string.
Instead of eventually specifying a set of I-tuples
comprising the set of syntactically legal programs
(as we did in the previous section), we will eventually
specify a set of ordered' pairs. The first element in
each pair will be. a syntactically legal program, the
second element its translation into the target language.
As in the previous section, we will illustrate our
approach by example. The syntactic specification of
Little PL/l will be modified to specify not only the
syntax of Little PL/I but also its translation into
IBM System/360 assembler language. A complete
specification of the syntax and translation of Little
PL/I is given in Appendix 5. Two example syntactically legal programs and their translations specified
by Appendix 5. are given in Appendix 2. As in the
example translations, the canons of Appendix 5.
specify comments entries with the assembler statements so that (hopefully) the reader will not have to
be familiar with IBM System/360 assembler language
to understand the translation.
In the succeeding paragraphs of this section we
present a discussion of the canons of Appendix 5.
The reader may wish to omit this discussion. The
techniques used in forming the canons of Appendix 5.
may be grasped by comparing the correspondingly
numbered canons of Appendices 4. and 5. For example, canons 9.1 and 9.2 of Appendix 4. give the
canons specifying the syntax of a GO TO statement,
and canons 9.1' and 9.2' of Appendix 5. give the
canons specifying the syntax of a GO TO statement
and its translation into assembler language. Following this section we indicate further applications of
canonic systems and conclude with a discussion of
the use of canonic systems as a method of definition.
Consider first canon 9.1 of Appendix 4:
GO TO (; go to stm with ref label .e,
label var A
(9.1)
I label
~
The assembler language statement for a GO TO
statement such as "GO TO A;", where A is a reference label, is simply
B A
*BRANCH TO A
559
where "B" is the operation code for an assembler
branch statement, "A" is the symbolic address* of
the first assembler statement for the referenced
Little PL/I statement, and "*BRANCH TO A" is
a comments entry. We may specify this translation
by modifying canon 9.1 :
.1 label ~ GO TO L; go to stm with ref label/.
label yarAassembler stms
(9.1 ')
B.,l
*BRANCH TO /
The modified predicate "goto stm with ref' labellabel var-assembler stms" names a set of 4-tuples,
where the elements of a 4-tuple are
1. a GO TO statement
2. the reference label for the GO TO statement
3. the label variable for the GO TO statement
4. the assembler statement for the GO TO statement.
The instance of canon 9.1' for the GO TO statement
"GO TO A;" is simply
A label I- GO TO A; goto stm with ref label A,
label varAassembler stms
*BRANCH TO A
B
A
Similarly, canon 9.2 of Appendix 4., the canon for a
GO TO statement with a label variable, is modified
to specify its translation in canon 9.2~.
The assembler language statements for an IF statement, such as
IF 1<5 THEN
might be as follows:
L
C
BNL
•
•
,
1,1
*LOAD I
1,=F'5' *COMPARE WITH =F'5'
Z
*BRANCH IF NOT LOW TO Z
(translation for non-DECLARE statement
following the boolean expression)
•
Z EQU *
*SYMBOLIC ADDRESS OF Z
For these assembler statements we must know:
a. The operand entries (I and =F'5') for the primaries (I and 5) of the boolean expression
b. the branch operation code (BNL) for the relational operator «)
c. the symbolic address (Z) of the assembler statement to which control should be passed if the
boolean expression is not true.
These requirements necessitate that we
·We assume that identifiers occurring in a Little PL/I statement will
not be changed upon translation into assembler statements so that
the same identifiers may be used.
560 Fall Joint Computer Conference, 1967
a. modify the canon for primaries to specify the
operand entry for each primary
b. modify the canon for relational operators to
specify the operation code for each relational
operator
c. add a premise to canon 11. to specify a new label
d. modify the conclusion of canon 11. to carry the
new label for use (canon 12.') in specifying the
EQU assembler statement needed to terminate
the assembler statements for the IF statement.
Canons 10.', 11.', and 12.', in coniunction with cannons 8.1' and 8.2', specify the translation of an IF
statement according to this format. T.he premise
"I, disioint !'a" in canon 12.' insures that the new
branch label differs from any that occur in the translation of the non-DECLARE statement "s". The element "assembler labels" in the predicate for an IF
statement is specified so that the label needed to speciby the proper transfer of control for a false boolean expression may later be specified to be different from
the other assembler labels and PL/I identifiers.
Canons 13.1 and 13.2 of Appendix 4., the canons
for a label assignment statement, are easily modified
to specify their translation in canons 13.1' and 13.2'.
We next consider canons 14., 15., and 16., of Appendix 4., the canons for an arithmetic expression:
~ +t-y*{»1 arith op
p primary with fix-pt vars v ~ p arith exp
with fix-pt vars v a+a' arithexp :with fix-pt
0 arith oPr aoa' ar~th exp
vars v~v'
with fix-pt vars vv'
(14)
(15)
+
(16)
We cannot immediately add to each of these canons
the elements specifying the correct assembler language statements. In the evaluation of arithmetic
expressions, the operations of mUltiplication and
division are carried out before the operations of addition and subtraction. We may specify this requirement
for a left to right evaluation of arithmetic expressions
by:
a. separating the arithmetic operators (+,-,*, and!)
into two classes, one for the addition~operators,
+ and -, and one for the mUltiplication operators,
* and I, (canons 14.1' and 14.2'),
b. defining a new construct "term" that consists of
a sequence of two or more primaries separated
by multiplication operators, * and I,
c. re-defining an arithmetic expression as a sequence of one or more primaries or terms separated by addition operators, + and-.
d. specifying that the left-most primary or term in an
arithmetic expression be evaluated first, in machine register 1 (canons 15.1' through 15.4' for
result in register 1),
e. specifying that succeeding primaries in an arithmetic expression be directly added or subtracted
to machine register 1 (canon 15.5'),
f. specifying that succeeding terms in an arithmetic
expression be formed first in machine register
3 (canons 15.2' and 15.3' for result in register 3)
before being added or subtracted to machine
register I (canon 15.6').
For example, canons 15.1' and 15.5' specify "1+1"
as a legal arithmetic expression with assembler statements:
*LOAD I
1,1
L
*ADD=F'I'
I,=F'I'
A
Canons 15.1',15.2',15.3' and 15.6' specify "A+B*C*
D" as a legal arithmetic expression with assembler
statements:
L
L
M
M
AR
I,A
3,B
2,C
3-I,D
1,3
*LOAD A
*LOAD B
*MULTIPL Y BY C
*MULTIPLY BY D
*ADD REGISTERS
(canon
(canon
15.1 ')
15.2')
(canon
(canon
15.3')
15.6')
The remaining canons of Appendix 5. readily follow. Canon 16'., specifies the assembler store instruction appended to the assembler statements
for an arithmetic expression. Canon 17'., is identical
to canon 17. of Appendix 4. Canons 18.1' through
20.2', the canons for a non-DECLARE statement
and a statement sequence, are similar to those of
Appendix 4., with the added predicate elements
needed to carry the associated assembler labels and
assembler statements. The premise ".fa disjoint L:"
added to canon 20.1' insures that the assembler labels
differ from each other. The premise ".fa disjoint ~ s
P.VdV" added to canon 20.2' insures that the assembler
labels differ from the other identifiers in a Little PL/I
program.
Canon 21.1' and 21. 2' are new. These two canons
specify the assembler data storage statements for a set
of variables. For example, if "I" were the only variable in a PL/I program, the following instances of
canons 21.1' and 21.2' would specify the storage statements for "I":
~ Aset of vars with assembler data: -stmsA
Aset of vars with assembler data stmsAt I identifier
1- I, disjointA I, set of vars with assembler data stms
t
I
DS
F
*STORAGE FOR I
Finally, canon 21., of Appendix 4., the canon for a
syntactically legal little PL/I program, is modified to
give canon 21.3'
Formal system for specification of syntax and translation of computer languages
Jlabel I S legal stm seq with stm labels .Is
~ v assembler stlJll. Sa q. . ../, disjoint ..fs V 4
v' set of vars with assembler data stms Sd 4 v in v'
.I: PROCEDURE; s END.L~ PL/I program with
translation
(21.3 ')
r
*
* ASSEMBLER LANGUAGE PROGRAM FOR..!
*
BALR 15,0 *SET REGISTER 15 AS BASE
REGISTER
USING*,15 INFORM ASSEMBLER THAT
Rl5 IS BASE REG
sa-
SVC
0
*RETURN
TO
561
Canonic system may be used to obtain structural
information 37 (e.g., syntactic trees) of programs. The
series of canons used in generating a string provides
structural information about the generated string. This
series of canons constitute a "derivation" of the generated string. Only an intuitive notion of a derivation
has been indicated here. However, using the concept
of higher level canonic systems, the rules for constructing a derivation can be formalized, and, in turn,
the rules for constructing a structural description of a
derived string made explicit. Higher level canonic
systems, and their application to provide structural
descriptions, are also described elsewhere.(6,7)
SUPERVISOR
*
DISCUSSION
*TERMINATE ASSEMBLY
The added premise "v' set of vars with assembler
data stms Sd" specifies the assembler data storage
statements for the variables of the legal statement
sequence.
The set named "PL/I program with translation"
is our desired set. This predicate names the set of
all ordered pairs such that the first element of each
ordered pair is a syntactically legal Little PL/I program and the second element is its translation into
assembler language.
We thus state our second basic result:
2. The language of canonic systems can be used
to specify the translation of programs in one
computer language into programs of another
computer language.
If the predicates needed to specify the syntax of a
source language are properly modified, the language
of canonic systems can be used to write one specification for both the syntax of a source language and
its translation into a target language.
Related applications
An immediate use of canonic systems is in the development of a generalized translator, i.e., a translator
that is independent of both source and target languages. We have used canonic systems to define a set
by specifying canons for generating its members. To
use a canonic system specification of the syntax and
translation of a language as a data base for a generalized translator, an algorithm to recognize source
language strings specified by a canonic system and
construct their associated translation is needed. No
algorithm for recognizing and translating strings specified by a canonic system is presented in this paper.
However, work on the application of canonic systems
to a generalized translator has been initiated and is
more fully described elsewhere.(6,7,8)
Many features of PL/I were omitted in choosing
the subset Little PL/1. We have ignored the specification of allowable spacing of Little PL/I programs.
Spacing, as well as card format, has been specified for
another computer language (4) using canonic systems.
Some of the other omitted features (e.g., nested arithmetic expressions) would have required only minor
modifications to the specifications of Appendices 4.
and 5. The use of identifiers containing up to thirtysix characters would have required that the identifiers
in a program be changed upon translation to assembler
language, where identifiers of only eight or less characters are allowed. The use of both fixed and floating
point variables was initially considered, but was omitted because many additional canons and several additional elements were needed to specify the translation
of arithmetic expressions. The inclusion of these features would not have added any new ideas to our
development. The large number of other PL/I features, such as the assortment of data types, block
structure, procedure references and definitions, and
input/output were disregarded. It is certainly within
the capacity of canonic systems to specify both the
syntax and translation of these features.
However, an equally important issue is whether
canonic systems provides a natural and concise
specification of these features. A canonic system for
the complete syntax of only one language, the simulathe complete syntax of one language, the simulation language G PSS/ has been written.
It is clear that a complete specification of the syntax of PL/I and its translation to assembler language
might be unduly large. We feel that this largeness
is due to three principal factors. First, the PL/I
and System/360 assembler languages are complicated, and the degree of the canonic system predicates
grows as the complexity of the source or target language grows. Second, on some features PL/I and IBM
System/360 assembler language are poorly matched.
562
Fall Joint Computer Conference, 1967
For example, many modifications to the canons of
Appendix 5. would have been required to specify the
assembler statements for the evaluation of arithmetic
expressions containing both fixed and floating point
variables. For any source and target languages, if
a canonic system of the syntax of the source language
and its translation to the target language were written
before finally defining the languages, it is likely that
we could better match the languages. The unwieldiness of portions of the canonic system would clearly
indicate where the languages were ill-matched. Third,
we feel that a part of the unwieldiness is due to the
shortcomings of assembler language as a generalpurpose target language. We feel strongly that if a
better set of language primitives were devised, the
specification of the translation process, using the new
language as a target language, would be greatly eased.
I t is important to develop languages whose descriptions are concise. The Backus-Naur Form specification of Appendix 3., and the associated five English
sentences given in text describing the context-sensitive requirements, provide a very concise description of the syntax of Little PL/1. In their present form
canonic systems will not replace Backus-Naur Form
and the English language for describing programming
languages to people. Present research has yielded a
notational convention that will eliminate much of the
detail of Appendices 4. and 5. We hope that this modification to the notation for canonic systems will make
canonic systems as suitable as Backus-Naur Form
for describing programming languages to people.
However, in their present form canonic systems, although yielding larger specifications, provide complete
descriptions in a precise language that a machine can
be instructed to understand with present techniques. 8
Moreover, the language, of canonic systems, like
Backus-N aur Form, is readable.
We wish to point out two additional features of the
canonic systems of Appendices 4. and 5. First, barring any inadvertent errors, the canonic systems
describe a set of PL/I programs and assembler language programs that will run on a computer when translated by a PL/I compiler or System/360 assembler
Second, the specification of the comments entries
in the assembler language statements was provided
not only to aid the reader. The comments are meaningful context-sensitive strings in the English language.
The specification of these strings was handled as
easily as the specification of the strings in assembler
language. The specification of the strings in the
English language illustrates the use of canonic systems to specify the entire operation of a translator,
including the specification of meaningful comments.
Moreover, it suggests the capacity of canonic systems
to handle communication and translation in languages
other than computer programming languages. We have
not explored this enticing area.
Canonic systems are applicable to the definition of
an "abstract" syntax l5 of a language. An abstract
syntax of a language is a description of the syntax of
a language that is independent of any actual representation of the symbolic expressions in the language.
By 1) omitting the canons specifying only symbols
in the object language (e.g., the canons for "letter"
and "digit"), and 2) using the application of the abstract syntactic functions in place of elements specifying strings in object language (e.g., writing the canon
for a Little PL/I GO TO statement as "-, label
GO (J) goto stm with ref label,£, label var A", where
"GO" is a function to be specified in defining a "concrete" syntax of Little PL/I), a canonic system could
be developed to provide an ~xact specification of an
"abstract" syntax of a language.
As mentioned earlier, the results of this paper apply
to any recursively emunerable set. Any function or
relation that is recursively enumerable can be specified by a canonic system. Canonic systems can be
used to express language and string transformations of
a much more different nature than given here. The
facility with which comments entries were specified
suggests many uses, for example, in handling interterminal computer communication. We do not know
to what extent canonic systems can practically be
used to express more varied algorithms than those for
string transformations.
We have used canonic systems to present a single
method for specifying the syntax and translation of
computer languages. To ease further the specification
of the translation of computer languages it would be
desirable to use a target language other than an assembler language. This new target language would have
a set of primitives in which the constructions in a
large class of languages could readily be expressed.
This target language has not been developed.
+
REFERENCES
The work presented in this paper has evolved from the following
works:
I EMIL L POST
Formal reductions of the general combinatorial decision
problem
Am J Math 65 pp 197-217 1964 This work presents a formal
system named canonical systems and demonstrates that every
system in canonical form can formally be reduced to a system
in normal form.
2 RAYMOND M SMULL Y AN
Theory offormal systems
Princeton University Press Princeton New Jersey, 1961
This work describes a variant (elementary, formal systems)
of the canonical systems of Post as the basic formalization
Formal system for specification of syntax and translation of computer languages
for a study of formal mathematical systems and recursively
enumerable sets.
3 TRENCHARD MORE
Class notes for course EAS 3 J3b applied discrete mathematics
Yale University New Haven Conn spring 1965 In this work the
definition of elementary formal systems were modified to
parallel More's definition of propositional complexes ref.
32 and applied to the study of various mathematical systems.
4 JOHNJDONOVAN
Investigations in Simulation and Simulation Languages
Ph.D. dissertation Yale University New Haven Conn fall
1966. Elementary formal systems were further ·modified (now
called canonic systems) in recognition of earlier work of
Post to meet the definitional needs of programming languages
and applied to the definition of the syntax of computer languages.
5 HENRY F LEDGARD
A scheme for the translation of computer languages
Ph.D. thesis proposal MIT Cambridge Mass July 1967
Here canonic systems were applied to specify the translation
of computer languages.
The following references 1) describe canonic systems and their use
in specifying syntsx and translation, and 2) present higher level
canonic systems, their use in formalizing the notion of a derivation
of a program string, and a discussion of the application of canonic
systems to a generalized translator for computer languages.
6 JOHN J DONOVAN and HENRY F LEDGARD
Canonic systems and their application to programming languages
Project MAC memorandum MAC-M-347 MIT Cambridge
Mass April 1967
7JOHNJDONOVAN~dHENRYFLEDGARD
Canonic systems and their application to computer languages
Submitted paper August 1967
The following references 1) describe canonic systems and their use
in specifying syntax and translation, and 2) present higher level
strings specified by a canonic system and generate their translation.
8 JOSEPH W ALSOP
A canonic translator
B. S. Thesis MIT Cambridge Mass June 1967
The following references describe other formalizations used to
characterize computer languages.
9 JWBACKUS
The syntax and semantics of the proposed international algebraic language of the Zurich ACM-GAMM Conference
Proc Inter'l conf information processing UNESCO Paris
pp 125-132 June 1959
10 DEKNUTH
Backus-normalform vs Backus-Naur form
Comm ACM vol 7 p 735 December 1964
11 W H BURKHARDT
Metalanguage and Syntax specification
Comm ACM vol 8 pp 304-305 May 1965
12 K ElVERSON
A method of syntax specification
Comm ACM vol 7 pp 588-589 October 1964
13 R W FLOYD
The syntax ofprogramming languages - a survey
IEEE Trans of electronic computers pp 346-353 August 1964
14 T B STEEL Editor
Formal language description languages for computer programming
North-Holland Publishing Co Amsterdam The Netherlands
1966
563
15 JOHN McCARTHY
Towards a mathematical science ofcomputation
Proc of IFIP congress Munich 1962 North-Holland Publishing Co Amsterdam pp 21-23 1963
The following references describe formalizations used to characterize the semantics of computer languages.
16 PETER LANDIN
TheA-calculus approach
Advances in programming and non-numerical computation
pergamon press 1966
17 A VAN WIJN-AARDEN
Recursive definition of syntax and semantics
I F I P working conf Baden September 1964
18 J A FELDMAN
A formal semantics for computer languages and its application
in a compilier-complier
Comm ACM vol 9 pp 3-9 January 1966
19 N WIRTH and H WEBER
EULER a generalization of ALGOL and its formal definition
PARTI
Comm ACM vol 9 pp 13-23 January 1966 PART II Comm
ACM vol 9 pp 89-99 February 1966
The following papers describe programming languages for expressing string transformations.
20 D J FARBER R E GRISWOLD and I P POLONSKY
SNOBOL a string manipulation language
Journal of the ACM vol 11 no 2 pp 21-30 January
21 CALVIN N MOOERS
TRAC a procedure-describing language for the reactive
typewriter
Comm of the ACM vol 9 no 3 pp 215-219 March 1966
The following paper describes a computer program for expressing
transformations on natural language input strings.
22 JOSEPH WEIZENBAUM
ELIZA -A computer program for the study of naturallanguage communication between man and machine
Comm of the ACM "019 no 1 pp 36-45 January 1966
The following references and ref 13 point out inadequacies of past
specifications in specifying the syntax of programming languages.
23 P GILBERT
On the syntax of algorithmic languages
JACM vol 13 pp 90-107 January 1966
24 A C DiFORINO
Some remarks on the syntax of symbolic programming languages
Comm ACM vol 6 pp 456-460 August 1963
The following references and (ref. 18) describe generalized translators that have been implemented as table-driven compilers.
25 E T IRONS
A syntax directed complier for ALGOL 60
Comm ACM vol 4 pp 51-55 January 1961
26 R A BROOKER and D MORRIS
A general translation program for Phrase-structure languages
JACM vol 9 pp 1-10 January 1962
27 T E CHEATAM JR and K SATTLEY
Syntax-directed compiling
Proc spring joint computer conf Spartan Books Baltimore Md
vol 25 pp 31-57 1964
28 C L LIU G D CHANG and REMARKS
The design and implementation of a table driven compiler
system
AFIPS vol 30 1967 Spring Joint Computer conference Spartan Books Washington 1967 A detailed discussion of this
translator is given in a project MAC technical report MACTR-42
564
Fall Joint Computer Conference, 1967
The following references describe to an extent the syntax of PL/1.
29 H CHLADEK V KUDIELKA and E NUEHOLD
SyntaxofPL/1
IBM Technical report TR 25.058 VIenna Laboratory September 1965
30 _ _ , formal definition of PL/I I BM Technical Report TR
25.071 by PL/I definition group of the Vienna Laboratory
December 1966
Definitions of the logical terminology used in this paper may be
found in the following works.
31 PAULC ROSENBLOOM
The elements of mathematical logic
Dover publications Inc 1780 Broadway New York 19 N Y
1950
32 TRENCHARD MORE
Relat ons between simplicational calculi
PhD dissertaton M IT Cambridge Mass May 1962
33 ALONZO CHURCH
Introduction to mathematical logic
Princeton New Jersey 1956 vol 1
34 A M TURING
On computable numbers with an application to the entscheidungs problem
proc London Math soc vol 42 pp 230 265 1936
35 A MTURING
Compl!tability and lambda dejinability
J symb logic vol 2 pp 153-163 1937
36 STEPHEN C KLEENE
Lamba-definability and recursiveness
Duke mathj vol 2 pp 340 353 1936
37 NOAM CHOMSKY
On certainformal properties of grammars
in readings of mathematical psychology Luce R D et al
John Wiley and Sons Inc New York N Y vol 2 pp 125-155
1965
The following manuals were used in developing the example subset of Little PL/I and defining its translation to IBM System/360
assembler language.
38 ___ IBM System/360 operating system PL/I langullge
specification
I BM systems reference library form C28-6571-3)
39 ___ , A programmer's introduction to the IBM system/360
architecture instructions and assemblerillnguage
Student text form C20-1646-1
40 ___ , IBM system/360 operating system assembler language
I BM system reference library form C28-6514-4
Appendix 1 SUMMARY OF NOTATION FOR CANONIC SYSTEMS
To provide the reader with a conche reference, the canonic 'Ylterna notation uled in
th!o paper will be preoented by a oerieo of ohort exampleo.
Abbreviationl and alternate notationl:
Canon!o)
I.
Interpretation
rA~
New Conotruclion(o)
(From no premilel. we can
conclude that) "All i, a
Z.
r
"r"
II
i. the a •• ertion .iln;
Canon!o)
8.
A l!.!.!!.!" i. a conclulion;
A~
't
B.!!.!!!!
New Con.truction(.)
"~"
named "letter" and "B" il a
conclulionl, all of which can
member of the let named
be allerted if the premiae.
and "A" i. an element in the let.
"~.
(here none) are .atialied.
The name of the let, here
I. and Z.).
i. the name of a let
9.
r
A tB
~
(aame a. canonl
"A" and "B" are member. of
the let named
".!!.!!!!"
(aame al canon 8. ).
lie"
i
~
j
1-
~
r
ij~
Alternate noution Cor
The .mal1letter "I" il a
named "differ" (lame al
the notation
we can conclude that" I"
variable denoting ~ny member of
canon b.).
'tal textl a
i, a member of the let
the
let named
''...!!.!!!!".
then
~
.et named
"~II
and
if "j" io a member of the
"~",
then
• •• textn-l",
11
where "< a 1"
n
il an n-tuple and
premioeo, all of which muot be
"textl textZ ••. textn-l"
oatiofled to auert the
II
conelulion.
"~'.
In leneral, the notation
conlllU of
The ordered pair "< A(C>"
named "differ".
the name of the let In which
the n-tuple ia a member.
The notation "< A< B>" denoteo
il a member of the let
III leneral,
" ~
"t, the conjunction .ign;
Itt" before the: "r" .eparatel
an ordered pair.
The .et named
~'.
text2 •.• ~
2
an" il an alternate Corm lor
.et named ''...!!.!!!!''.
The ordered pair "< A( B>"
are different.
< A differ
a premi.e;
i. a member of the let named
ordered pairl whOle element.
r
~"i.
"~".
"~'
7.
"I
'I~tl.
U "i" i. a member of the
named
< A< B>
A~B
"< A
10.
"ij" i. a member of the let
r
r
The ordered pair "< A"
.et named
6.
memberl of the lame let.
il a member of the let
named
5.
''...!!.!!!!''.
U "I" i. a member oC the
I ~
"t" il uled to separate two
or more elementl that are
i, a member of the let
named
'.!!.!!!!
leparatel
".!.!.!!!.!"
named ·'letter".
4.
"r"
member of the aet named
"B" iI a member of the let
3. rC.!!.!!!!
after the
I'.!.!.!!!.!".
"letter", il called a predicate.
B letter
r
Interpretation
"A" il a member of the .et
II.
r
AtA
~
BtC The ordered pain "< A"
and "< A" are members
of the let named
"~"
(lame al canOnl 6. and 7. ).
denote. an ordered n-tuple.
"t" il used to leparate
the
elementl of two or more
ordered pairl that are
member. of the lame let.
Thil notation i. extended to
handle n-tupleo.
Formal system for specification of syntax and translation of computer languages
565
Appendix 2 TWO SYNTACTICALLY LEGAL PROGRAMS IN LITTLE PL/l AND THEIR TRANSLATION
INTO IBM SYSTEM/360 ASSEMBLER LANGUAGE
Legal Program P
Translation {or P
*
*
ASSEMBLER LANGUAGE PROGRAM FOR P
*
P:
PROCEDURE;
A:
I = I + 1;
IF I < 5 TH.EN GO TO A;
BALR
USING
EQU
L
A
ST
L
C
BNL
P
A
END P;
Z
*
Lesal Prosram
q
PROCEDURE;
DECLARE LX LABEL;
L:
I = I + IA*IB - IC;
LX = L;
GO TO CHECK;
M:
I = I + 1;
LX = M;
CHECK: IF I < LIMIT
THEN GO TO LX;
B
Z
A
EQU
SVC
*
0
*SET REGISTER 15 AS BASE REGISTER
*INFORM ASSEMBLER THAT R15 IS BASE REG
*SYMBOLIC ADDRESS FOR PL/I LABEL A
*LOAD I
*ADD = F'l'
*STORE RESULT IN I
*LOAD I
*COMPARE WITH =F'5'
* BRANCH IF NOT LOW TO Z
*BRANCH TO A
*SYMBOLIC ADDRESS OF Z
*RETURN TO SUPERVISOR
DS
END
F
P
*STORAGE FOR I
*TERMINATE ASSEMBLY
Translation {or Q
*
*
*
Q:
15,0
*,15
*
I, I
l,=F'I'
1,1
I, I
I, =F'5'
ASSEMBLER LANGUAGE PROGRAM F£>R Q
Q
L
END Q:
M
CHECK
Z
*
LX
I
IA
IB
IC
LIMIT
BALR
USING
EQU
L
L
M
AR
S
ST
MVC
B
EQU
L
A
ST
MVC
EQU
L
C
BNL
L
BR
EQU
SVC
15,0
*, 15
*
I, I
3,IA
3-1,IB
1,3
l,IC
I, I
LX, =A(L)
CHECK
*
I, I
I, =F'I'
I, I
LX,=A(M)
*
I, I
I, LIMIT
Z
I,LX
1
*
0
*SET REGISTER 15 AS BASE REGISTER
*INFORM ASSEMBLER THAT Rl5 IS BASE REG
*SYMBOLIC ADDRESS FOR PL/l LABEL L
*LOAD I
*LOAD IA
*MULTIPLY BY IB
*ADD REGISTERS
*SUBTRACT IC
*STORE RESULT IN I
*SET LX EQUAL TO ADDRESS OF L
*BRANCH TO CHECK
*SYMBOLIC ADDRESS FOR PL/I LABEL M
*LOAD I
*ADD=F'I'
*STORE RESULT IN I
*SET LX EQUAL TO ADDRESS OF M
*SYMBOLIC ADDRESS FOR PL/I LABEL CHECK
*LOAD I
*COMPARE WITH LIMIT
* BRANCH IF NOT LOW TO Z
* LOAD ADDRESS STORED IN LX
* BRANCH TO THIS ADDRESS
*SYMBOLIC ADDRESS OF Z
*RETURN TO SUPERVISOR
DS
DS
DS
DS
DS
DS
END
F
F
F
F
F
F
Q
*STORAGE FOR LX
*STORAGE FOR I
*STORAGE FOR IA
*STORAGE FOR IB
*STORAGE FOR IC
*STORAGE FOR LIMIT
*TERMINATE ASSEMBLY
566 Fall Joint Computer Conference, 1967
Appendix 3 BACKUS-NAUR FORM SPECIFICATION OF SYNTAX OF LITTLE PL/I
I.
< letter>
: := AlB •.•
Z.
< digit>
: :=
Iz
IF < boolean expre.sion>
13.
< label a .. ign statement>
< label variable> = < label>;
THEN < non-DECLARE statement>
~
[< letter>]
4.
< unsigned integer>
[< digit>]!O
5.
< !ix-pt variable>
[I IJ I KI LI MIN]! [< letter>]
: : = < identifier>
7.
< label variable>
: : = < identifier>
S.
< primary>
: : = < unsigned integer>
~
14.
< arith op>
15.
< arith exp>
I
< primary> < arith exp>< arith op>
< arith exp>
I
lb.
< arith auign statement>
< fix -pt variable> = < arith exp>;
17.
< DECLARE statement>
DECLARE < label variable> LABEL;
IS.
< non-DECLARE statement>
< n;'-pt variable>
9.
< GO TO statement>
: := GO TO < label>; I
I
< GO TO statement> < IF statement>
< arith anign statement>
: := <1= I>
10.
< rei op>
11.
< boolean expression> : : = < primary>< rei op>
19.
< statement>
: . _ [< label>:] ~
[< label>:]
< primary>
ZOo
< statement sequence>
Zl.
< PL/I program>
< non-DECLARE statement> I
6 < DECLARE statement>
::= []';
< label>:
PROCEDURE;
< statement sequence>
END < label>;
In addition to pure Backul-Naur Form, we use the brackets [
to designate any number from kl through k
Z
of occurrences of the enclosed expression.
Appendix 4 CANONIC SYSTEM SPECIFICATION OF SYNTAX OF LITTLE PL/I
1.
letter
~
Z.
~
~0+q
3.
identifier
'1 +'2 + ' 3 . '4
4.
unligned integer
d I + d 2 +d 3 + d 4 +d S +d 6 + d 7
5.1
Urlt letter for
fix-Et var
~ I+J
fix-Et var
~
i~
7.1
~
i~
7.Z
list
~
i~
7.4
a +b
7.7
differ
7. S
7.9
!!!!,
a
+b + c
a
~I
~
r
i~
i~
7.10 disjoint
r
7.11
list
t
b
r
i,
!!.!!
~
ab
!!.!!
~
b~abc
~I ~
ab
~I
A+A+ ••• +A!!!!!!!.B+C+ ••• +Z
B +B
x +y
x
~
~
A!!!!,
7.3
~
+'5 + 'b . ' 7 +'s letter ~ '1 +'I'Z+ ••• +IIIZI3'4Is'6'7's ~
+d S + d 9 +d lO ~ ~ d l +dld Z + ... +dldZd3d4dSd6d7dSd9dlO unligned integer
+K+LtMtN first letter for fix-pt var
5. Z
7.6
letter
... +9!!!.i.!!
b.
7.5
+z
At B t •••
+ ... +B differ A + C
!!!!!!.
~y
t
r
x !!!!!!!. y
t
+ ••• + Z
<d + a yc
~ ~
axd!!!!!!!. a yc
Y!!!!!!!.x
A disjoint A
i
~
7.IZ
i
~j
7. 13
x
disjoin~
r
~
I
1-
I
< label assign statement> I
GO TO < label variable>;
~:
I
< label variable> = < label variable>;
< label>
b.
< IF statement>
011 ... 19
< identifier>
3.
IZ.
1-
i, disjoint A
A disjoint i,
i, disjoint j,
y disjoint I
~
xy disjoint I
t
I disjoint xy
Formal system for specification of syntax and translation of computer languages
567
Appendix 4 (continued) CANONIC SYSTEM SPECIFICATION OF LITTLE PL/I
B. I
primary with fix-pt var
B.Z
9. I
i unsigned integer
~ i primary with fix-pt var A
v fix-pt var
~ v primary with fix-pt var v,
~
goto .tm with ref labellabel var
GO TO ,; goto Itm with ref label I, label var A
,~ ~ GO TO ,; goto Itm with ref label A~',
9. Z
r
10.
<
+p'
+ = + > rei op
boolean exp with fix-pt vare
p
lZ.
if Itm with ref label-label van-
b boolean exp with fix-pt van v t
fix-pt vare
13. I
label a .. ign atm with ref labellabel varl
13. Z
arith exp with fix-pt vare
~ t , label ~ v
v
+v'
+
~
~
v
r rel op
~ prp' boolean exp with fix-pt varl vv'
I non-declare .tm with ref labels' r label van' v
label auign Itm with ref label"
=v';
label varl v,
label allign Itm with ref label A label varl v, v' ,
+ - +• +/arith op
~ p arith exp with fix-pt van v
arith exp with fix-pt varl v
16.
arith auign .tm with fix-pt van
v 1 fix-pt var t
17.
declare .tm with decl label var
v label var
lB. 1
non-declare Itm with ref labellabel van-fix-pt van
g goto Btm with ref label' r
lB.Z
= ,;
p primary with fix-pt var v
+a'
t
I
IF b THEN I; if Itm with ref label' r label van' v _fi_x_-....
p_t_v_a_rl_ vv '
v
a
15. Z
~
fix-pt van v'
r
14.
15.1
primary with fix-pt var v
+v
11.
r
t v'
r
a arith exp with fix-pt van v
DECLARE v LABEL;
r
t o arith op
d~clare
v1
aoa' arith exp with fix-pt varl vv'
= a;
arith auign Itm with fix-pt van vv l'
Itm with decl label var v,
!!.2!.!..!!!. 'v
L
r g non-declare Itm with ref labels' r label van' v fix-pt van A
. i if Itm with ref label' r label van' v fix-pt van v
L
r
r
i non-declare Itm with ref labels,
r
label varl'
lB.3
, label auign Itm with ref label' r label van' v
IB.4
a arith alsign Itm with flx-pt varl v
'non-declare Itm with ref labels' r label van
v
fix-pt van v
'v fix-pt van A
~ a non-declare Btm with ref labels A label van A fix-pt varl v
19.1
.tm leq with .tm labelsref labels -label vandecl label vare-fix-pt vare
19. Z
r
I non-declare Itm with ref labels, r label van' v fix-pt van v
I Itm leq with Itm labels A ref labels' r label van' v decl label varl A fix-pt varl v
I non-declare Itm with ref label'
~ ,: I .tm
r
label varl'
v
fix-pt varl v d... , label
T -----
leq with .tm labels', ref labels' r label van' v decl label varl
A
fix-pt varl v
19.3
d declare Itm with decl label var v
19.4
d declare Itm with dedlabel var v
r
r ,:
d Itm leq with .tm labels A ref labels A label varl A decl label vaz:.· v fix-pt van A
ZO.l
•• I' Itm leq with Itm labels
fix-pt van v
L
r
1- ' ~
d Itm leq with Itm labels A
+v' cl,
r
I
'I t ,~
~ A label
ref labels 'r
disjoint"
van A decl label van v fix-pt van A
+,~ label van 'v t '~decllabel van 'vd t '~d
I
u' Itm aeq with Itm labela' "
••
ref label. , " label van' "
rr
vv
decl label van 'vd' vd fix-pt van vv'
ZOo Z
legal atm leq with .tm labels-
:::!!.!
ZI.
PL/I program
a .tm leq with atm labels 'I ref labels 'r !abel var. 'v dedlabel van 'vd fix-pt van v
cl
d.., in' d
T v disjoint' I , v d el,
T • diljoint' v d d..,
T rin'
- • T v- v
. r
,~ t
~
I legal atm leq with Itm label I ' . !!!!.'vdv
I legal Um leq with Um labels 'I !!!.!. v t
,: PROCEDURE; I
END'; PL/I program
"
disjoint ' . v
568
Fall Joint Computer Conference, 1967
Appendix 5 CANONIC SYSTEM SPECIFICATION OF SYNTAX OF LITTLE PLII
AND TRANSLATION INTO IBM SYSTEM/360 ASSEMBLER LANGUAGE
(Canons 1 '. through 7.13' •• ame a. canon. 1. through 7.13. in Appendix 4.)
8. l'
Erimarl with fix-Et varoperand code
i un.igned integer
soto Urn with ref labellabel var-assembler stms
1 label
9. l'
r
10. '
rei op with branch code-messase
11. '
boolean exp with fix-pt varebranch label as.embler stm.
r
p
v, primarl with fix-pt var v, operand code v
r
GO TO 1; Soto .tm with ref label II. label var 1 assembler stms
1,1
*LO~ESS STORED IN 1
L
1
BR
*BRANCH TO THIS ADDRESS
+- + > rei op with branch code
<
+p'
primarl with fix-pt var v
1-
r
1~
prJ'
~
C
a-
lZ. '
if stm with ref labellabel vare-fix-pt varsassembler labell-assembler .tm.
= F'i'
GO TO 1; go to .tm with ref label I, label var II. auembler stms
*BRANCH TO 1
B
1
1~
9. Z'
i, primary with fix-pt var II. operand code
r
v fix-pt var
8. Z'
r
+v'
BNL
+BNE +
BNH mellale NOT LOW
operand code x
+x'
1-
+NOT EQUAL + NOT HIGH
r reloE with branch code b menase g
boolean exp with fix-pt yare vv, branch label I, assembler stms
l,x
* LOAD x
l,x'
*COMPARE WITH x'
1
* BRANCH IF g TO 1
b bool . . . . . , witla fix-pt van v branch label 1 assembler stms 'a
1-
• _-_clare .t.. with r.i label 1 r label yare 1 v fix-pt vare v' as.embler labels 1 a
r
-'r
• ••• mW.r .tm•• '
I, ciiljoint 1
IF b THEN s if stm with ref label 1 label vare 1
•
a
r
v
fix-pt var. ¥v' • • • • mitl.r labell 1 ai, as.embler stms
••
•
EQU
,
13. l'
label alliin Urn with ref labellabel vars-as.embler .tm
add op with op code-mellage
14. Z'
IS. l'
IS. Z'
v lab.l var
---
t
arith exp with fix-pt vanresult in reg-assembler stms
term with fix-pt varsresult in reg-assembler stms
r
+
•
J
r
---ave
v = v';
r
!dVC
v
= I;
label assign IItm with ref label I, label vars v, assembler stm
v,=A(I)
*SET v EQUAL TO ADDRESS OF 1
label aslign stm with ref label II. label yare v, v,' a •• embler .tm
v,v'
*SET v EQUAL TO v'
p primary with fix-pt var v operand code x
a •• embler stms
L
p
+
*SYMBOLIC ADDRESS OF 1
*
+ - add op with op code A + S mellage ADD t SUBTRACT
+ Imultop with op code M +D mellaie MULTIPLY BY t
p' primary with iix-pt var v
r
1-
15.3'
'
'l.bel
v+v'~
13. Z'
14.1'
•
r
l,x
+v'
p arith exp with fix-pt vars v result in reg 1
* LOAD x
operand code x
pmp' term with fix-Et vars vv' result
l,x
L
O,x
M
pmp' term with fix-pt yare vv' result
3,x
L
Z,x
M
p primarl with fix-pt var VI operand code x
B
arith exp with fix-pt vareresult in res-assembler .tm.
1 5.5'
1-
1-
m mult op with op code c me •• ase g
tmp term with fix-pt vars vv 1 result in reg i a •• embler stms
a
i-I, x
c
15.4'
t x' 1- m mult op with op code c mellage g
in reS 1 as.embler stms
* LOAD x
*g x
in res 3 as.embler .tm.
* LOAD x
*g x
t term with fix-pt vars v result reg i assembler IItms sa
r
*g x
t term with fix-pt vars v re.ult in reg 1 a.sembler stms sa
r
t arith exp with fix-pt vars v result in reg 1 assembler stms sa
a arith exp with fix-pt var. v result in reg 1 assembler stms 'a
p primarl with var VI operand code x
r
1-
II
a
l,x
*g VI
a arith exp with fix-pt yare v result in reg 1 auembler .tms sa
t term with fix-pt vare v' result in reg 3 allembler stmll
meslage g
r
s
11-
s~
0 add op with op code c
aot arith exp with fix-pt varl vv' result in reg 1 all sembler 8tms
a
II'
-,_.
1-
0 add 0E with op code c mes saSe g
aop arith exp with fix-pt vare vv 1 re.ult in reg 1 allsembler IItms
c
15.6'
DIVIDE BY
a
cR
1,3
*g REGISTER!.
Formal system for specification of syntax and translation of computer languages
569
Appendix 5 (continued) C.4NONIC SYSTEM SPECIFICATION OF SYNTAX OF LITTLE PL/I
AND TRANSLATION INTO IBM SYSTEM/360 ASSEMBLER LANGUAGE
16. '
17.
lB. I'
arith a .. iln atm with flx-et vanaaaembler atma
1- a arith exp with fix-pt van v ruult in reg I aaaembler dma aa
vI Cix-pt var
r
v I = a; arith aa dgn atm with Cix-pt vara vv I' aaaembler atma
a
a
ST
r
declare atm with decl label var
v label var
non-declare etm with ref labelavanaaaembler labela-assembler 8tms
g goto etm with ref label'
r
r
r
r
r
~-Cix-pt
.STORE RESULT IN vI
I, vI
DECLARE v LABEL; declare atm with decllabel var v,
label var' aaaembler atma a
r--- v
a
g non-declare atm with ref labels' r label van I v Cix-pt vara /\ auembler labela I\.
IB.2'
i if etm with ref label I
IB.3'
I label auign Itm with ref label I r
IB.4'
a arith auign 8tm with fix-pt vara v aasembler Itml la
19. I'
Itm aeq with atm labelaref labela-Iabel vandecl label vara-fix-pt varaaaaembler [abela-aaaembler etma
19.2'
aaaembler atms a
label vara I v fix-pt vara v aaaembler label a 'a aaaembler atma aa
r---i non-declare atm with ref labela I r ~
Cix-pt vara v aaaembler labela I a auembler etma aa
~
'v
a
'v flx-pt vara /\ asaembler labela I\. aaaembler atma aa
I v aaaembler dma a
I non-declare atm with ref label a 'r~
__
_ /\ fix-pt vara v aaaembler labela /\ aaaembler. etma a a
a non-declare atm with ref labela /\ _
label
van
e non-declare atm with ref label a ,
a Itm aeq with atm labela
label vara' fix-pt vara v auembler labela I aalembler atma a
a
r---- v
a
I\.~ ' r label vara
decllabel varal\. fix-pt vara v
'v
a.aembler label. 1
a •• embler atm. a
a
a
e non-declare dm with ref labela , label vara I v fix-pt van v aaaembler labela I a aaaembler atma a
a
r----
t
l~
r'
I atm leq with atm labela " ~ I r ~ 'v decl label vara /\ fix-pt vara v
:
a .. embler labela I aaaembler atma
a
EQU
-SYMBOLIC ADDRESS FOR PL/I LABEL I
I
e
a
-
19.3'
d declare atm with dec1label var v
r
d Itm eeq with atm labela I\. ref label./\.
~
I\. decl label van v fix-pt van/\..
auembler label. /\ auembler atma I\.
19.4'
d declare atm with decl label var v
r
1- I ~
I: d dm seq with dm labela
I\.~ I\.~
/\ decllabel van v fix-pt van I\.
aaaembler label a I\. aaaembler atma I\.
lO. I'
a
+a'
atm seq with atm labela 'a
. fix-pt van v
r'
+v'
+ I~ ~ 'r + I~ ~ I )
a .. embler labela I
I~ decllabel van 'Vd
+I~d
t I' aaaembler atma aat a
a' 1- I disjoint I' 1- I
aa
a
a
a
disjoint I'
a
aa' stm aeq with dm labela I I' ref labela I " label van I I' decl label vara I d"d
I a - - - r r---- v v
v v
fix-pt van vv' a.eembler labela 'a' ~ aaaembler atma a a'
a a
ZO.2'
legal etm aeq with etm labelavara-aaaembler Itma
a atm leq with atm labela
ae.embler labels I
I
r
ll. I'
ll.2'
eet of vara with aaaembler
~
r
disjoint I d
.---
v
1- I
a
'a
~
I r label vara 'v dec! label vare I vd fix-pt vara v
a .. embler atma a
in I
r-
8
1- I
1- v -disjoint
1 I d 1--IV
1- I &--diajoint' , d V
av
a
in I d
v- v
a legal stm leq with atm labela 'a
~ lvd v
a .. embler atma aa
I\. set of vars with asaembler data atma /\
v set of van with s .. embler data atma ad
r
t
VI
~
+
VI' disjoint v
vv l ' set of vara with aaaembler data atma
ad
DS
VI
ll.3'
PL/I program with translation
1-
F
-STORAGE FOR VI
I label
siegal stm aeq with atm labela I vare v aaaembler dma a
-aa
I, diajoint
v
v' aet of varl with a .. embler data dma ad
v
r
t
'a
I:
1-
1~ v'
PROCEDURE; a END I; PL/I program with tranalation
···
I
"
ASSEMBLER LANGUAGE PROGRAM FOR I
BALR
USING
8
a
SVC
15,0
·,15
.SET REGISTER 15 .\S BASE REGISTER
.INFORM ASSEMBLER THAT RI5 IS BASE REG
0
.RETURN TO SUPERVISOR
I
*TERMINATE ASSEMBLY
e
d
END
a
Generalized translation of programming languages
by RONALD W. JONAS
Linguistics Research Center
The University of Texas
Austin, Texas'
INTRODUCTION
A generalized model for the computer translation of
both programming and natural languages has been
developed at the Linguistics Research Center of The
University of Texas. The design of the model is discussed here and sample grammatical descriptions are
given to illustrate how the generalized translation of
programming languages may be accomplished.
A
Discussion of the model
The linguistic theory of transformational grammar
provides convenient terminology for explaining the LRC
model. This theory maintains that there is not merely
one structure underlying a language, but two: surface
structure and basic structure. Viewed as a generative
system, a transformational model is composed of a,
base component, which generates basic tree structures,
and a transformational component, which maps these
basic trees onto surface tree structures. The terminals
of the resultant surface trees define strings of some
particular language, such as FORTRAN or ALGOL.
If we think of the transformational model as primarily generative, the base may be regarded as the
first phase of the process, generating structural trees
explicitly stating linguistic relationships underlying language strings. These trees have terminal nodes, but
they do not necessarily form a string which is meaningful in any particular language. The representation used
by most linguists for the base is an ordered context
sensitive grammar. Context sensitivity and ordering together control the type of structures output from the
base. Figure 1 shows one such structure.
The transformational component, the last phase of
the generative process, is expressed as a grammar having ordered rules in a highly specialized format. These
rules specify how to take particular basic trees and
reshape them so the terminals of the resultant trees are
in the desired order. The resultant terminals must form
a string, reading left to right, which belongs to the lan-
a
c
b
e
d
f
Figure 1-Basic tree
guage for which the transformations are written (e.g.
FORTRAN or ALGOL). For example, if the string
abcedf in Figure 1 is not a string of language X, then a
transformation may be specified to yield some surface
tree with string abcdef belonging to the language X.
One result of such a transformation is shown in Figure
2. In this case the transformation specifies that terminal
branch d is to be moved from node C to node B of the
tree.
A
a
b
c
d
Figure 2-Surface tree
570
e
f
Generalized Translation of Programming Languages
The transformational model details a mapping from
base trees onto surface trees for only those parts of the
two trees which are not identical, creating a rather
economical statement of structure. A minimal statement is achieved for the generative process with base
trees (formed by the base component) and a set of
transformations (applied by the transformational component), which together yield a surface tree. Since
transformations serve simply to reshape the basic tree
into a surface tree, the mapping of base structure into
identical surface structure is not explicitly stated.
Some linguists maintain that the base component
characterizes language-independent organization while
the transformational component characterizes languagespecific organization. It is tempting to say that the base
states semantic relationships and that the transformational component states syntactic relationships, but such
a dichotomy is artificial at best. In such a model,
syntax, as it is traditionally defined, refers to the structure explicitly stated by both the base grammar and the
transformations. Semantics would then be defined as a
combination of what is implicitly stated by the syntax
and of the theory which led to the particular base and
transformational rules in use. The semantics of language
is explicit to the extent that the theory specifies algorithmically how to code the base and transformational
component grammars. Perhaps it is better to say, for a
particular language, that the surface structure highlights the syntax while the basic structure highlights
the semantics.
By virtue of the power available in its pair of
hierarchically-arranged grammars, transformational theory provides a system of importance to the mechanical
translation of languages. To be sure, transformational
theory itself does not solve the problem of translation,
for it is concerned only with representing basic trees
and mapping them onto the strings of some Ianguage(s).
Translation must involve a reverse process as well, as
suggested by Figure 3. For the compilation of programming languages, this diagram has a special interpretation. The input processes may be yiewed as
FORTRAN, ALGOL, etc. The output process may be
using grammars of programming languages such as
viewed as using grammars of particular machine languages such as CODAP, MAP, binary codes, etc.
Although the input and output processes would
seem to be inverses of each other, there are some very
definite reasons why they are not. The input process
is attempting to guess what basic trees underlie the
input strings. Box 1 guesses what surface trees are
likely to be involved. Box 2 uses this best-guess information to control its guesses as to which basic trees
might be involved. Given certain basic trees, the output process merely applies the transformations specified
571
for the target language to yield surface trees (Box 4)
and finally synthesizes the surface trees into output
strings (Box 5).
There is, nevertheless, much similarity -between the
input and output processes. Boxes 1 and 5 are each
applying surface grammars of their particular languages
to produce surface trees and output strings, respectively. The two operations differ in that one is using its
grammar to find all possible surface trees that may
Figure 3-Generalized translation process
lead to the given input string while the other is given
a particular surface tree and knows (from its grammar)
exactiy what string to produce from that tree. Analogously, Boxes 2 and 4 have their grammars of transformations. They differ in that one is trying to find
all basic trees underlying the hypothesized surface trees
while the other is given a particular basic tree from
which to produce related surface trees.
Box 3 defines an interlingual mapping of input language basic trees onto output language basic trees. This
process is best regarded as a two-stage operation: a
subprocess which maps input basic structure into a set
of interlingual classes, and a subprocess which maps
these interlingual classes into output basic structure.
These subprocesses are driven by grammars which associate basic substructures with certain interlingual classes. Those interlingual classes containing a single basic
substructure for each language would provide exact
translations, while classes containing multiple substructures per language would provide loose transJations.
For programming languages this would reflect the difference, for example, between FORTRAN statements
which can be compiled into code only one way (e.g.,
CALL) and those which may be compiled any number of ways (e.g., A==-(B+C)).
A mechanical translation model much like the one
discussed here is operational at the Linguistics Research
Center. The specification languages of all boxes are
roughly context free grammars, but ones which have
operators available for each term of a rule. With these
grammars it is possible to define and manipulate a
terminal vocabulary in Boxes 1 and 5, to perform a
572
Fall Joint Computer Conference, 1967
monolingual mapping between surface and basic trees
in Boxes 2 and 4, and to scan trees and associate interlingual classes in Box 3.
Descriptive procedures
To accomplish generalized translation within the
framework of this model, it is necessary to define
a semantics of computing and to establish grammars
suitable for intertranslating procedure-oriented languages. machine-symbolic languages, and machine
codes. The present objective is to formulate descriptions which will be suitable for translating procedureoriented Janguagcs and machine-smbolic languages into
binary code. If the descriptions prove to be truly generalized, then any-direction translation will be possible;
but the current objective is generalized compilation.
The usual procedure in generalized compiling is to
apply a grammar to the input strings and then to engage
semantic routines to interpret the results. The structural trees assigned to the input by the grammar contain nonterminal classifications which control the operation of semantic routines. Careful formulation of the
grammars permits the proper semantic effects. The
semantic routines build tables of semantic information
which eventually yield the necessary machine code.
While certain current compilers have been designed
to handle programming language syntax in a general way
by accepting syntactic grammars, little has been done'
to generalize the information contained in the semantic routines of these compilers. The value of the model
discussed here is that it permits complete grammatical
description of both syntax and semantics. This allows an
explicit statement of semantic classes in the form of a
grammar rather than the implicit statement afforded
by semantic routines. By providing the capability for
coding a semantic grammar which captures the semantic information, this model eliminates the necessity for
programming in a compiler and puts compilers, instead, completely in the realm of grammatical description of languages.
These are many problem areas requiring investigation before it is possible to write semantic grammars.
The principal ones are as follows:
1. Data Representation
a. Types of data; e.g., floating-point numbers,
signed integers, alphabetic strings.
b. Structural organization; e.g., matrices, lists,
files.
c. Forms of storage; e.g., bit strings, character
strings, words, disk files, tape records.
2. Data Representation Operations. These would
establish, change, and abolish data representations; exemplary operations: declarations, assignment statements for converting data types.
3. Data Manipulation Operations. This would include all operations upon any of the data defined
in 2.
a. General: add, test, truncate.
b. Input-output: read, write, print.
c. Transfers: move block storage.
4. Sequencing Operations. Any operations controlling the flow and synchronization of data
manipulation operations would be in this group.
a. Central processor: conditional and unconditional transfers, index jumps, central processor
interrupts.
b. Input-output: synchronization of independent
data units, input-output interrupts.
c. Console: communication interrupts.
All of these areas have been investigated preliminarily.
The remainder of this paper will be devoted to a discussion of the data manipulation and sequencing operations.
As suggested above, discovering and grammatically
describing basic' trees is of great importance for this
translation model. Of equal importance, however, is the
necessity for defining the interlingual classes naming
equivalent substructures of basic trees (Figure 3, Box
3). It does little good to define the semantics of each
language to be translated unless a mapping can be
guaranteed between the basic trees. Interlingual classes
are used in defining this mapping. When a basic tree
is partitioned into meaningful syntactic-semantic units,
each block of the partition should be assigned to an
interlingual class. If the corresponding basic trees entering and leaving Box 3 (Figure 3) are partitioned
into equal numbers of blocks, then interlingual classes
may be assigned to the blocks of the partitions in such
a way as to define a 1: 1 mapping between the input
and output basic trees.
These interlingual classes are best defined before
semantic grammars of particular languages are coded.
Yet these classes can only be defined in a meaningful
way by inspecting the types of basic trees they are
intended to classify. Both will be discussed together
in the following presentation.
Illustrative grammatical descriptions
The basic trees in Figures 4, 5, and 6 illustrate interlingual mappings for ALGOL, MAP, and some
imaginary Machine X. Each figure contains basic trees
which are equivalent and presumably translatable for
the indicated languages. Solid lines define basic trees
(such as the ones resulting from the application of
grammars in both Boxes 1 and 2 of Figure 3). Brokenline enclosures are interlingual classes assigned to the
substructure of the, basic trees by the grammar of Box
Generalized Translation of Programming Languages
3; the names of these interlingual classes are indicated
as some T x. The names themselves define the interlingual mapping of basic trees within each figure. See
the Appendix for an explanation of MAP mnemonics.
.,. ...---- ........ ......
1/
Unit
"
I
\
,
I
/'
\
(Name,
I~
1\ II,I
ALGOL
t
-
t
\
\
'1 n \ \ I
I III I
[sTol!l Z I ; I
STOjl \1 \ J
op
,r
t
\
Command
~
I
oP, n ,
'1\ /1 CLAI I I
\~ .J
]' A \
I I ~DQ J I \..
\
1flli \
Command
, n
ALGOL
573
I
--r' J '-
7090 MAP
7090 MAP
Figure 4-Structural mapping of addition operation
MACH~E
CODE X
Figure 6-Structural mapping of data transfer operation.
Terms within the two pairs of brackets are to be mutually
selected. That is, CLA and STO co-occur or LDQ and STQ
do. Colons and semicolons do not occur in MAP but are
simply added for clarity (with ALGOL interpretations)
ALGOL
7090 MAP
Figure 5-Structural mapping of assignment statement
As Figure 6 shows, the interlingual class T 1 serves
to relate four equivalent operations within the three
languages represented. Because the mM 7090 is a
single-address machine, more structure is included in
the class T 1 for MAP than for either ALGOL or the
multiple-address Machine Code X. In the same example, classes T 2 ,T4 , and Ts provide an interlingual
mapping of the variables involved in programming
statements. As suggested in the earlier discussion of
the translation model, these classes differ from other
interlingual classes in that they may be defined during
the translation process by special operators. For example, the intermediate symbols v in the ALGOL structures of the above examples may have associated operators which assign the lexical items M, Z, and A to
unique interlingual classes (in this case, T 2 , T 4 , and
fs, respectively).
The relationships implied by the interlingual class
names in these examples might be:
Tl
Move data "statement"
T3
"Statement" name
TlO
Store value "statement"
T 11
Summation "statement"
T 2 ,4,5
map particular data structures from language to language
These classes explicate the semantics implied by the
basic trees. For example, anyone who sees the symbol
in a statement quickly realizes it is an "assignment
statement". He has mentally given a gross semantic
classification to the part of the structure involving :
One important fact that this overlooks is that the symbol
; was just as important in the definition of assignment
statement as was :
The classes named above are intended to reflect
greater refinement of the semantic classifications. "Assignment statement" is too gross in the sense that it
unites the semantic distinctions made by interlingual
classes Tl and T 10 , i.e., the basic difference between
'moving a block of data into a new location (T1) and
storing the result of a summation (T10 ) . By more exact
.=--
==.
==.
574
Fall Joint Computer Conference, 1967
isolation of structural information, the grammars which
map basic trees into. interlingual classes are able to
specify explicitly all the semantic distinctions.
As might be guessed, there is no restriction on the
size structure which might be included in an interlingual class. The smallest classes will consist of such
things as variable names~ some punctuation, and rather
simple operations. The larger classes may be increasingly inclusive: programming loops in machine language
may be interlingually equated to DO loops in
FORTRAN or FOR loops in ALGOL; subroutines
and even whole programs may become single interlingual classes or a set of such classes. For single interlingual classes to be semantically more inclusive, it
is necessary to define larger basic trees. The only
limit on such definition is the practical one of how
inclusive the grammar is to be. For example, Figure 7
illustrates the basic trees for one possible DO loop to
sum the elements of a matrix.
FORTRAN
7090 MAP
Figure 7-Structural mapping of basic trees underlying
a DO loop
Generalized Translation of Programming Languages
Clearly the MAP code used in Figure 7 is not the
most efficient for representing the DO lo'op, although
it is perfectly valid. This is due to the fact that the
basic tree for the MAP statements is isomorphic with
its corresponding surface tree. An improved sequence
of MAP code is shown in Figure 8. The solid lines
575
represent the surface structure imposed on the code.
Dotted lines represent a transformation which maps
that surface structure into the basic structure illustrated
in Figure 9. Only the interlingual mappings' which are
different from those of Figure 7 are shown.
Figure 8-Structural mapping of surface tree for 7090
MAP code underlying DO loop
The surface tree (Figure 8) illustrates the improved
MAP code in normal order. The basic tree (Figure 9)
demonstrates the semantic functions isolated by the
interlingual classes, as follows:
Section a: Opening and closing of DO loop
f3 : Name of loop
'Y : DO loop proper
Clearly the basic tree explicates semantic information
which is only implied in the surface tree. This is the
motivation for investigating basic trees and interlingual
classes rather than surface trees in defining the semantics
of computing.
Data manipulation operations
With the advantages of basic trees in focus, it is
timely to ask what the semantic classes should be and
from what primitive units they should be Quilt. The
matter ·of semantic primitives is of most importance,
for these will be the terminals of basic trees. For
ALGOL the terminals might be operations such as
:==+-/*. For MAP it might be ADD CLASTO, etc.
If one were a computer engineer, the primitives of interest might be the operations of switching theory: and,
or, complement and perhaps nand, nor, exclusive-or.
Semantic primitives defined in this way appear not to
576
Fall Joint Computer Conference, 1967
",
/
T4
,,""'" ----- ~ "DO
,
"\
,
~I /
(
\
I
/'
/'
/'
/
/
/
/
/
I
/
/
, op
I
T 12
/'
/'
"" '\
IIv
I
I',-'.
v \
I
I
I
I'I
....
'-----
\
\
\
I
tLXA/N
\ ..-/ I
~
/
/'
I
I
/
\
I
,.., ,,--,,/'
\
\'T
11
+ +
......
-----~--a
-
I
\
,':, \ vI
Iv
I
I I I
I I I
STQ' Z I ; I X I : ,I ADD I A
I \~
\J \ --' J
,/
----~
T
IO
+ N
....
'-----
....
-----~--'Y
-----~
Figure 9-Structural mapping of basic tree for 7090 MAP
code underlying DO loop
be generally applicable. One would not, for example,
be happy with switching theory primitives as a basis
for grammatical descriptions of ALGOL; and the
ALGOL primitives would be entirely too gross for a
grammatical description of sub-machine operations. In
short, a separate set of semantic primitives must be defined for each language to be grammatically described.
Semantic primitives of this type, while useful for
describing each language for which they are chosen,
appear to have little interlingual value. The problem
of mapping the primitives of one language onto those
of another remains. This mapping is part of the more
general problem of forming interlingual classes. Given
that our initial task is the generalized compilation of
programming languages, the mapping of primitives is
an exercise in discovering the interlingual intersection
of primitives for binary code and procedure-oriented
or machine-symbolic languages. If we look at inter-
lingual class T 11 in Figure 4, we see that it contains
the primitive operation
for ALGOL. The corresponding MAP code for ~ is not at all primitive, however. Can the class Tll be called primitive? As suggested above, a given interlingual class is likely to be
primitive only with respect to one of the two languages
being inter-translated. This will be the language whose
primitives are larger. Only when the two languages
being translated are highly alike will there be any
classes which are primitive with respect to both languages.
It appears, then, that the more useful process is
that of finding, for two languages, which primitives
must be defined in terms of sets of other primitives.
For example, in Figure 4 the ALGOL structure mapped
into interlingual Class T 11 involves a single primitive.
The MAP structure mapped into T 11 involves the sequence of primitives CLA ,. ADD ,'. We can say
+
Generalized Translation of Programming Languages
+
that the ALGOL primitive
is equivalent to the sequence of MAP primitives. This suggests an algorithm
for creatjng interlingual classes; it would be applied to
all languages in pairwise fashion: In general, the primitives of the more high-level language would define interlingual classes. The structure of the low-level language would be mapped into these classes as sequences
of low-level primitives.
As an illustration of this process, assume we are~
translating MAP to 7090 binary code. The smallest
interlingual classes would correspond to the primitive
Mnemonic
Description
operation codes of MAP, such as CLA, STO, ADD,
etc. While there is one complete 7090 binary code for
each MAP operation, complete operations would not
necessarily be the best primitives used in the grammar of the 7090. The 7090 operation code values reflect rather clearly the suboperations of the computer,
and it is these suboperations which best serve as monolingual primitives of the binary code grammar. Table
1 is a partial list of MAP operations and the corresponding 7090 binary codes. The primitive suboperations indicated in Table 1 are explained in Table 2.
Octual
Code
Multiply
Variable-length multiply
Divide
Variable-length divide
MPY
VLM
DVH
VDH
0200
0204
0220
0224
Floating add
Unnormalized floating add
Floating add magnitude
Floating subtract
Unnormalized floating subtract
Floating subtract magnitude
Add
Subtract
FAD
UFA
FAM
FSB
UFS
FSM
ADD
SUB
0300
4300
0304
0302
4302
0306
0400
0401
Place
Place
Place
Place
Place
Place
accumulator address in index
accumulator decrement in index
accumulator address in index compo
accumulator decrement in index compo
index in accumulator address
index in accumulator decrement
PAX
PDX
PAC
PDC
PXA
PXD
577
0734
4734
0737
4737
0754
4754
Binary Code
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
F
0 0
1 0
0 0
1 0
0 0
1 0
C
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
A
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
t
1
~
D
0
0
1
0
0
1
0
E
1
1
1
1
1
t
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
I
1
0
B
0
0
1
1
0
0
0
1
1
0
0
G
Table 1. Partial list of operation codes for IBM 7090 computer.
Certain suboperations are enclosed in boxes.
A
Basic operation: multiply, floating point addsubtract, fixed point add-subtract, load into index, load
from index
B Suboperation: add, subtract
C Word segment: address, decrement
D Length: word length, variable length
E Signing: signed value, magnitude
F Normalization
G Complementation
Table 2. '-Primitive suboperations chosen
for IBM 7090 computer.
Clearly, the binary code is readily partitioned and
yields a better set of primitives for the grammar of
the machine than the full operation code. If each MAP
operation defines an interlingual class, then the chart
reveals the set of 7090 binary primitives which maps
into each interlingual class. For example, the MAP
operation FAD would be interlingually mapped together with the binary primitives A. B. E, F to cause
translation into the complete binary operation 0300.
An ALGOL operation would be mapped quite differently into the primitives, however. For example, the
ALGOL addition operation makes no explicit statement
about the variety of addition chosen. In the statement
X : == Y + Z, the operation + would map into only
the binary primitive B (Table 2). It would not involve
the choice offered by primitives A, E, Fi i.e., floating
point vs. fixed, signed vs. unsigned, normalized vS.
unnormalized. These parts of the binary operation
could only be translated from information interlingually
mapped with the variables X, Y, Z.
578
Fall Joint Computer Conference, 1967
Sequencing operations
The grammatical description of sequencing operations is equally as important as the description of data
manipulation operations. Such a description must account for the order in which data manipulation operations are executed and in which registers of the computer are addressed by these operations. The formulation of the description depends, once again, upon the
definition of semantic primitives for sequencing.
In a computer like the IBM 650, every command
explicitly states the location of the next command by
an overt address. But in contemporary binary computers, sequencing is determined by a meta-process. That
is, except for certain branching commands in the computer's repertoire, next addresses are determined by an
addition process. There is an Address Register, much
like the accumulator, which is stepped as each command is operated in order to cause sequencing to proceed linearly through memory. This process is depicted
in Figure 10. It illustrates three alternate types of sequence control, which are characterized by the basiC
structures in Figure 11.
Unconditional Branch
Conditional Branch
Other
Figure II-Basic structure for three types of sequence control
in the central processor of the IBM 7090 computer
unconditional branch
Put address given in
command into A.R.
Figure IO-Conceptualization of meta-addressing in IBM
7090 computer
Ordinarily when we talk of computer operations, we
refer only to what is going on in Boxes C (Figure 11).
All of the hidden performance which goes into the processing of a sequenct of operation, however, is represented by the rest of the basic trees. These trees
suggest a level of control in the computer which is
superordinate to that of the operations proper, namely
the control of sequencing.
While the above trees account for only the simplest
variety of sequence control, related ones are capable
of explaining a more difficult sequence phenomenon:
interrupts. Each interrupt available on a computer is
linked with some device which operates independently
of the central processor. The key to the independent
.operation of each device and the behavior of its interrupt lies in Address Registers like the ones referenced
in Figure 10 and 11. Each independent device may
have an Address Register of its own to control its own
sequencing. It may likewise have Address Register
controls much like those in Figure 11, Boxes A and B.
The device will only need such a control if it has a
sequence of suboperations to perform. In any event,
these devices are all coordinated with the central devise via its (central) Address Register.
As indicated in Figure 11, after each operation of
the central processor is performed (Boxes C), control
is returned to the central Address Register. Any time
some independent device needs the services of the central processor, it may interrupt by altering the contents
of the central Address Register while Box C is in progress for the central processor. Upon arriving at Box
D ( and subsequently A), the central processor will
automatically be redirected by the contents of its altered
Address Register. Therefore, we may account for even
the interrupt behavior of computers by positing a basic
structure for each interrupt. For example, the interrupt
behavior of a typical independent device A might be
'characterized as in Figure 12.
A solution to the more general problem of addressing memory follows from this. The important consideration is that arithmetic may be performed on the
Generalized Translation of Programming Languages
Figure ] 2-Basic structure underlying the interrupt behavior
of Device A. Box X cames central processor control to be
diverted
reference addresses themselves, not merely the data they
reference. For example, every reference has potentially
a base address and an index, which, when added together (or subtracted), yield the effective memory address. The execution of every command (Figure 1,
Boxes C) having such an indexable address may be
regarded as having a subcycle in which this effective
address is computed, as shown in Figure 13. The 7090
has another such meta-operation. When more than one
index is referenced by the same command, the logical
sum of the indexes is taken and the result is then added
(or subtracted) to the base address. This would require another subcycle on the far left of Figure 13
which accounted for the summing of indexes.
c
Add base address
and contents of
index register
Figure 13-Basic structure underlying address indexing
In general, the grammars accepted by current compilers express relationships only within individual programming statements of the language being described.
The relationships implied by the order in which these
individual statements are executed is not explicitly
coded. Compilers have not required or used this variety
of information in the grammars. Data manipulation
operations, on the other hand, involve well-defined
functions for which convention has come to dictate fairly final grammars. Until grammars are written which
state explicitly all the features of programming languages, including sequencing, translation of programming languages will not be general enough to be altogether semantically satisfying.
Optimization
The foregoing discussion has revealed that it is not
enough merely to look at procedure-oriented languages
as a means to formulating a theory of computing. The
579
features of semantic grammars for procedure-oriented
languages and for binary codes must be highly correlated
if translation is to be realized. Such correlation is complicated by the fact that there is not always a single
best way to map a procedure-oriented languag~ such as
ALGOL into the binary code for a particular computer. For example, one can define multiplication or division by powers of 2 in terms of either arithmetic or
bit-shifting operations. A generalized compiler should
be able to select either mapping. Furthermore, one
would expect the compiler to select the code which
leads to the shortest execution time for the given computer. If bit-shifting operations are faster but arithmetic operations are more general, then clearly the interlingual classes should include both to achieve the
best translation of all multiplication and division statements into machine code. Inclusion of all such alternatives should be an objective for good semantic grammars.
SUMMARY
A model for language translation has been presented
as a means for compiling computer languages. While
in the same class as compiler building systems, it offers the advantage that the specification of programming languages and computer characteristics may be
accomplished completely grammatically. In addition to
providing generalized descriptive methods, the model
offers the potential of free inter-translation of languages once grammars are coded.
An approach to the writing of grammars for programming languages is outlined. The suggestion is made
that currently available syntactic grammars may be
considered adequate and that effort should be put into
the coding of semantic grammars. Major problem areas
requiring investigation to this end are: ways of representing and storing data, operations for data representation and manipulation, and sequencing control. Exemplary grammatical descriptions are shown.
Particular attention is given to the description of
data manipulation and sequencing operations. The discussion includes consideration of both the monolingual
and interlingual problems of grammars for procedureoriented and machine-symbolic languages and binary
machine codes. The definition of a semantics of computing involves, consequently, not only determining
what machine code is substituted for programming
statements but also what the meanings of statements
and sequences of statements are in both languages and
what their common structural intersection is (interlingual classes). This has led to some tentative conclusions about what units are needed in a semantic
theory in order to completely describe programming
languages.
580
Generalized Translation of Programming Languages
APPENDIX: IBM 7090 MAP Operations
Mnemonic
ADD X
CLA X
LDQ X
LXA X, Y
STO X
STQ X
TIX X, Y, Z
Explanation
Add contents of X to accumulator
Clear accumulator and add contents
of X
Load Q register with contents of X
Load index register Y with address
of word at X
Store accumulator contents at X
Store Q register contents at X
Reduce index register Y by Z
amount; if result is 0, transfer
to location X
BIBLIOGRAPHY
2
3
4
E W BACH
A n introduction to transformational grammars
Holt· Rinehart and Winston Inc New York 1964
N CHOMSKY
Aspects of the theory of syntax
The MIT Press Cambridge 1965
R S GAINES
Oil the translation of machine language programs
Communications of the ACM 8:736-741 December
1965
5
6
7
8
9
10
IBM 7090 Principles of operation
IBM Systems Reference Library File No 7090-01
Form A22-6528-5 August 1963
R K LINDSAY
Inferential memory as the basis of machines which
understand natural language
Computers and Thought Edited by E. A. Feigenbaum
and J Feldman McGraw-Hill Book Co New York
1963 pp 217-233
J D McCAWLEY
Concerning the base component of a transformational
grammar
Ditto Revised University of Chicago August 16
1966
M R QUILLIAN
Semantic memory
Bolt Beranek and Newman Inc Cambridge Scientific Report no 2 October 1966
W A SASSAMAN
A computer program to translate machine language into
FORTRAN
AFIPS Conference Proceedings 28:235-239 Spring
Joint Computer Conference 1966
Thirteenth quarterly progress report
Linguistics Research Center The University of Texas
at Austin pp 22-34 1 May 1962-31 July 1962
A M ZWICKY et al
The MITRE syntactic analysis procedure for transformational grammars
AFIPS Conference Proceedings 27 :317-326 Fall Joint
Computer Conference 1965
Computer change at the Westinghouse
Defense and Space Center
by W. BARKLEY FRITZ*
WestingilOlise Electric Corporation
Pittsburgh, Pennsylvania
INTRODUCTION
The Westinghouse-Baltimore Defense and Space Center is a military contractor of approximately 13,000
employees with sales billed in the neighborhood of
one-quarter billion dollars annually. Computer operations are centralized with research , enmneerin
0&
.'J:>' management science, and business data processing all being
handled by the same facilities located in an Administrative Services Building nearby the two major Divisions
of the complex but up to 60 miles away from other
operations which it serves. At the present time the central computer is a UNIVAC 1108 with four connected
UNIVAC 1004's, eight IBM 1050's and additional
Friden Collectadata equipment which permit access to
the 1108 from various remote and not so remote locations.
A status report on these facilities, however, is not the
subject of this paper. My subject is computer change
and in particular computer change from the point of
view of an organization which has undergone fairly
frequent and successful change.
The basic reasons for computer change are to reduce
costs and provide adequate computer capacity. The demands of the rapidly changing technology of the defense business and the needs of its customers for machine processed information sometimes seem almost
impossible to satisfy. However, it does not follow that
the cost of computer processing must continue to climb.
In fact, at the Westinghouse Defense and Space Center
total costs for computer service have actually been reduced by nearly 40 percent during the past two years.
This reduction has taken place in spite of the fact that
the requirement has continued to grow. As a rule-ofthumb, by taking advantage of improved equipment,
exploiting improved software and techniques and by
more effective loading of equipment, it is possible to
reduce per job computer costs by a factor of two every
two years. In fact, the Westinghouse Defense and Space
Center has used this rule-of-thumb as a guide for
evaluating its performance over the past six years.
Computer acquisition at Westinghouse
At the Westinghouse Electric Corporation, we have
developed over the years a fairly advanced computer
acquisition procedure of which we are justly proud.
We have centralized computer ordering. We treat the
a~q~i.sition of computers as cost reduction projects.
Dlvl~lons of the Corporation desiring computers are
re~Ulr.e? t~ conduct a feasibility study culminating in
a JustificatIOn report. A procedure exists requiring the
approval of the Division Manager, the Headquarters
Man.agement Systems Department, the Group Vice
PreSident to whom the Division reports, and for the
most expensive models, the Corporate Capital Expenditures Committee. Our Headquarters Management Systems Department contains experienced computer
specialists who assist the divisions in such deliberations.
Reports have been issued describing our computer acquisition procedure, the cost reduction guidelines which
must be met, and a checklist of items to be considered
in the feasibility study and documented in the justification report. Among the items covered are the requirements that more than one computer supplier be considered and that the purchase or rent question be
evaluated.
Additionally the Headquarters Management Systems
Department negotiates contracts with the various computer manufacturers. These negotiations have resulted
in several contractual conditions which have made computer change easier for the Westinghouse Divisions.
These contractual conditions include:
1. 90-day cancellation option for· complete systems;
2. 30-day cancellation option for individual units
or subsystems;
3. Letters of intent and "pool" orders to facilitate
delivery schedules; and
*The author was until recently the Manager of Information
Systems and Programming at the Westinghouse-Baltimore Defense and Space Center where he had responsibility for computer planning and programming.
581
582
Fall Joint Computer Conference, 1967
4. Software modifications or special software requirements to meet local needs.
Through the use of cost reduction guidelines for computer projects and additional contractual conditions,
Westinghouse management has allowed healthy growth
of its computer systems and their usage, while continuing to maintain effective control of the equipment.
Management guidelines
Efficient and effective change requires adherence to
certain management guidelines on the use of the computer systems. Some of the more important of these
guidelines in effect at the Baltimore Defense and Space
Center are as follows:
1. Machine independent programming languages are
used with careful attention to modularity in system design. Subroutines are constructed in such
a way that they can be used in more than one
application without change.
2. Data files are established in a standard machine
processable format so that these files can be
effectively maintained and used for more than
one information requirement.
3. Follow-up analyses are performed as a standard
part of any equipment acquisition as well as for
each application implemented. All too frequently
a computer based information system is designed
to provide information to solve a particular problem. It is essential that the information should
stop flowing when the original problem has been
solved. Exception reporting should be the rule
rather than the exception. The emphasis and format of computer output should continue to change
as necessary to respond to changing management
needs.
4. Backup arrangements are provided for all equipment. It is generally not economically feasible to
have sufficient in-house equipment to meet all
emergency situations, but one can usually have
a neighbor with compatible equipment that can
serve as mutual backup. Organizations such as
users associations help to foster individual local
arrangements. Sharing of ideas as well as equipment can also result from such backup arrangements. Eventually with machine independent programming, it won't be necessary for the backup
installation to have the same type of equipment.
5. New types of ADP Equipment should never be
acquired until such time as an extensive workload
has been established on Service Bureau or other
equipment elsewhere. This means that the computer programs required will have been written
a:1d tested before new equipment is installed.
6. Follow-up of equipment and individual applications is emphasized via the project schedule
technique. Evaluation and monitoring of the total
load is also performed. Charts indicating hours
of usage, number of runs being made, hours per
shift of "distributable" use, and related usage
figures are maintained and carefully examined to
ascertain trends. The amount of time for re-runs
and set-up is monitored and action taken to control any undesirable trend. Unlike other service
costs, computer service costs per unit of work,
when properly controlled, do go down.
7. USASI sponsored standardization efforts are care- i
fully followed to be certain that the internal
standards policy is consistent with USA Standards. I
Proposed USASI standards are regularly pub- I
lished in the Communications of the Association _.
for Computing Machinery.
8. New problem solving techniques are communicated to individuals responsible for implementing
new computer programs. We must be certain
that all of our system design work and each new
computer program is properly reviewed by senior
personnel to check accuracy, conformity to standards and to make certain that poor techniques
are not being used. Programmers don't like this,
but other work is reviewed, why not computer
programs? Individuals are given responsibility
for the quantity and quality of their work. They
are informed as to the total requirement and the
individual Analyst/Programmer is made responsible for his individual effort.
Westinghouse-Baltimore experience
To be more specific now with respect to the Westinghouse-Baltimore Defense and Space Center, I have
included three figures which illustrate our growth in
computer usage and improvement in price performance.
Figure 1 shows the decline in typical job cost. Figure
2 illustrates the reduction in average cost per equivalent
IBM 7094 hour over the past six years. In spite of, or
rather in part because of, a growth from 10,000 computer passes per month in 1962 to over 25,000 passes
at the present time as illustrated in Figure 3, the average cost per typical job and the average cost per equivalent computer hour have easily met the goal of a
factor of two cost decrease every two years.
During the past four years over 40 changes have
been implemented to the Westinghouse-Baltimore facilities. Some of the changes involved only individual units
or special features; however, during this period 12
computer systems were released and replaced by 10
new systems. One of these changes was for a mechanical
replacement of a 1401 system which was replaced by
Computer Change at Westinghouse Defense and Space Center
583
V.ESTlNvH.:>USE - BALflMVRE DEFENSE AND SPACE CENTER
COMPU rER RUNS PER MOO fH'
ALL COMPU TERS
WESTINGHOUSE - BALTIMORE DEFENSE AND SPACE CENTER
TYP teAL JOB COS T
16,000
'USING RENTED COMPUTERS'
24000
'800
COfw1PUTERS USED
'61
10/61
IBM JI().I
IBM 1090
3/63
IBM 709.4
6/64
6/66
UNIVAC 1107
UNIVAC 1 !08
20.000
18,000
lfl,OOO
200
10,000
1962
1963
1964
1965
1966
1967
1968
1969
,
, ..... " .. Co'
1')62
Figure l-Westinghouse-Baltimore Defense & Space Center
typical job cost (Using Rented Computers)
WEST1NGHOUSE - BALTIMORE DEFENSE AND SPACE CENTER
AVERAGE CaiT PER EQUIVALENT 709" I HOUR
$1000
7094
1107
EXPECTED COS T
Q-
"
......... , . . .
I%J
~
.. Co, .- ........ ,
J
....
1964
<...
0,. "...... , , .... ) ..
Ib60S
u
, ........... ,
1966
J
... "
.. Co
I
•
.., . . .
I
I
...
- ' ' ' Co I
~
.....
1967
Figure 3-Westinghouse-Baltimore Defense & Space Center
computer runs per month-all computers
sary to meet changing needs.
I hope I have set the stage properly. Computer change
shouid occur because newer equipment makes it possible to do the same load or an increased load at lower
cost. I have tried to demonstrate that the WestinghouseBaltimore Defense and Space Center has been able to
make frequent change and has reaped the financial payoff from such change.
COMPUTERS USED'61
704
10161
7090
3/63
6/64
6/6(,
/68
~
·BASED ON FACTOR
OF Z DECREASE
EVERY 2 YEARS)
. A ttitude for change
,961
T962
196]
196"
1965
1966
1967
1968
1970
1971
1972
,973
Figure 2-Westinghouse-Baltimore Defense & Space Center
average cost per equivalent 7094 I hour
IDM when it could no longer be maintained. Most of
the other changes were upgrading of 1401's to 1460's
and finally to 360/30 systems. During the 4-year period,
six 1401 systems and three 1460 systems were replaced
or released. During the same period an IBM 7090 was
upgraded to a 7094 which was later released. A UNIVAC 1107 was acquired and later replaced by an 1108.
The present configuration consists of an 1108 and
three IBM 360/30 systems.
Everyone of these changes was fully justified and
controlled, as discussed previously, as a cost or expense
reduction project. As I have attempted to show, computer change has made possible significant per job reductions in computation costs and provided desirable
adjustments in the configuration of equipment as neces-
Change must be supported by the right attitude. Essentially the attitude which supports change seems to
be common among individuals who have been connected with computers for at least five years, sometimes much longer. Many of us were using such equipment even before the prevalence of magnetic core storage. We have lived through extensive technological
change. At some time in the past we may have felt
"stuck" with equipment beyond its technological or
economic life because of the reprogramming problem.
However, we are now going to make certain that we
will not be "stuck" again. During the past several years
we have insisted on the use of machine independent
programming languages. We have recognized that
change. At some time in the past we may have felt
changes in existing operating pregrams to meet changing requirements. In being successful, our work load
has grown through the introduction of new applications.
We have a record of frequent change of our rented
equipment because we have long ago recognized that
modular hardware existed and that equipment could
grow and change to meet new requirements. Although
users, we have helped to force upon the computer
manufacturer some of the hardware and software im-
584
Fall Joint Computer Conference, 1967
provements currently available. Our ideas and needs
have contributed to the new generation of equipment
now being made available. In summary, we "liberals"
of the computing field are prepared to make rapid use
of the new equipment. Change for us means an ability
to get more throughput per dollar, to move Into areas
heretofore untouched and to help make ADP an increasingly important part of the entire organizational
picture.
State-of-the-art of program conversion
As further background, or stage setting, for my
simple "formula for change," I would like to review
briefly the state-of-the-art in the area of computer system change and reprogramming.
In June, 1965, the ACM sponsored jointly with Applied Data Research, Incorporated a "Reprogramming
Conference." The three-day meeting was held in Princeton, N. J., and ten of the papers presented were published in the December, 1965 issue of the Communications of the ACM. For those interested in the reprogramming problem, this issue of CACM and the many
references presented is a useful starting point.
Following is a brief summary of what was said at
that conference-in essence an abstract of the abstracts:
1. A large file maintenance and retrieval system was
written in COBOL and run successfully on three
different IBM computers ( 1410, 7080, and
7090) .
2. Completely automatic translation of machine
language programs, although highly desirable, has
not been achieved. Problems are primarily of a
semantic nature which can be resolved by a semiautomatic procedure.
3. A set of macro-operations was used to assist in
translating from the 7090 to the 7040 by inserting this set of macros at the beginning of the
7090 symbolic deck.
4. An RCA 301 "emulation" system ,,ras used to
enable 301 object programs to be run on the
Spectra 70/45. The emulation concept makes
use of both hardware micro-program routines and
software to accomplish the required action.
5. The emulation concept was further described as
it applies to running 7074, 7080 and 7090 programs on the IBM System/360.
6. A translation system was described to eliminate
"most" of the effort formerly required to reprogram Phi1co 2000 programs for operation on the
IBM 7094.
7. Techniques utilizing a meta-language to map from
one assembly language into another were de-
scribed. Timing problems and "perverse" use of
instructions presented difficulties.
8. The 1401 compatability feature for the IBM System 360 Model 30 was discussed. This paper
covered what proved to be the most widely used
computer conversion aid during the past two
years. As most of us know, the read only storage
used on the 360/30 has made the running of
1401 programs on the 360/30 a highly successful and economical venture.
'
9. A variety of special translation programs have
been written to aid in the translation of programs
from one version of FORTRAN to another and
from one computer to another. LIFT and SIFT
are two such programs. CAT (Computer Aided
Translation) was a CDC 3600 programming
system designed to aid in the translation of IBM
7090 FAP programs into 3600 COMPASS language programs.
10. A final survey paper considered hand recoding,
automatic machine language to machine language
translation, decompilation, meta-assembly (a
generalized assembly program that accepts as input both symbolic instructions to be assembled,
and parameters that in· effect specify the machine for which they are to be assembled), and
computer transference.
Not included in the wrap-up paper were the techniques used to translate very similar languages (e.g.,
FORTRAN II to FORTRAN IV), the quasi hardware "emulator" concept for translating existing application programs (both discussed in other papers),
or the very generalized UNCOL concept which requires
more unanimity among computer manufacturers and
users than seems achievable.
A number of computer conversions have been recently reported, e.g., Doug Williams' article in the
January issue of Datamation entitled "Conversion at
Lockheed Missiles and Space." Another aid in converting was reported in February Datamation by Don
Herman, of Comress, Incorporated, which is now
marketing TRANSIM for "translating programs" from
one machine to another. This· is apparently a 100%
effective translation for certain selected pairs of machines.
Management responsibility for change
The successful Westinghouse-Baltimore approach
(our formula for change) is based on a fundamental
tenet of management policy, i.e., the computer facility
will replace existing hardware with new improved better price performance hardware as it becomes available.
Changes, as outlined previously, did take place so
Computer Change at Westinghouse Defense and Space Center
computer users have come to expect change and be
ready for it.
In Westinghouse-Baltimore, personnel involved in
the development of information systems have been also
"exposed" for some time to a Department Manual
which includes an introduction that emphasizes flexibility, and I quote, "a policy of obtaining the most effective processing equipment (from a cost per ).mit
. computation point of view) and using this equipment
to its maximum potentia1." Such a policy requires the
use of programming practices which minimize the cost
of conversion to new equipment, thus the necessity for
so-called machine independent programming.
The Department "goal" and "responsibilities" again
emphasize these points and the following statement of
programming policy puts added teeth into the management emphasis.
"FORTRAN/BEEF programming policy
"The basic programming policy is that all programming be accomplished as described in "The Compleat
Guide to FORTRAN/BEEF Programming," published
by the Westinghouse Defense and Space Center. This
document provides the specification of this machine
independent programming approach and documents
acceptable programming practices and techniques.
"The following "Statement of Programming Standards" will be rigidly adhered to:
1. FORTRAN will be used as the programming
language for all scientific, engineering, management science and data processing applications.
2. When conventional FORTRAN statements are
basically inadequate, already prepared standard
subroutines (BEEF) will be used via the CALL
statement.
3. If the existing subroutine library is not adequate
to accomplish the required result, a new subroutine will be defi.ned, specified, programmed,
and' added to the BEEF library. This new routine
will be written in FORTRAN and/or the symbolic language of the computer being used. In
order to maintain machine independence the new
subroutine will be written for any other computer
on which the program is to be run, in other
words the BEEF library will be maintained.
4. As an aid in debugging new programs, the BEEF
editor will be used.
5. All programs will be written so that all referenced
files may be changed among tapes, card readers,
drums, discs, card punches, and printers by an
appropriate change of unit number.
6. Careful attention must be given to make certain
that any change to a new computer, a new ex-
585
ecutive system or exploitation of major increases
or decreases in hardware configuration can be
accomplished without difficulty.
7. Adequate comments will be included to make
certain that the intent of the program is understood by others trained in FORTRAN programming.
"You Can Be Sure If It's Westinghouse" that the
present computer will be replaced by a new system in
the near future."
Obviously, a management policy does not mean computer conversion is automatic. A single programming
language is not the complete answer, for although the
basic programming language may be the same on two
computers, there are frequently operating system differences. This facet of the problem can be solved by
computer editing of input decks prior to their compilation. For example, it was possible for WestinghouseBaltimore to run IBM 7094 FORTRAN program decks,
using the IBSYS control cards, directly on the UNIVAC 1107. This was accomplished by having the control cards automatically converted by the 1107 on input. A few ground rules established in 1963 provided
the basis for a standard FORTRAN. The burden was
placed on the new system to behave like the old. This
approach to handling the minor differences in operating
systems is probably in fairly common us~.
A problem in computer system conversion is that
the user is only being partially supported by the supplier. The supplier is willing to provide assistance in
converting from a competitor's equipment to his own,
but is really not interested in helping the user to become independent of all suppliers, including himself.
It would appear that today's operating systems arc designed to help lock you into the brand you are now
using. Again, the solution is in the hands of user
management who must take steps not only to establish
policy as noted earlier but in following through to see
that machine independence is maintained. In-house
operating systems capability is a must for effective
follow-through.
Another facet of the "reprogramming" problem is
the fact that many of the required major information
systems in wide use were written for a particular computer by the supplier, e.g., PERT/COST, or a specific
Design Automation System. The supplier of the equipment probably has written the major application system
in' symbolic machine language and unless forced to do
so the supplier of the new equipment will not readily
agree to rewrite the system. Contract negotiation time
is the point when such problems must be resolved. The
production of generalized software to meet user specification is one area where the computer supplier will
586
Fall Joint Computer Conference, 1967
assist, particularly if that software is of general use.
Westinghouse-Baltimore has had no trouble, for example, in getting the BEEF subroutines rewritten for
new equipment. McDonnell and IBM have collaborated
in the rewriting of BEEF for the 360 systems. CDC
has included most of the BEEF subroutines in their
software support and, of course, UNIVAC maintains
this package for the 1107/1108.
Another problem is getting to and maintaining computer independence in programming is the attitude of
the programmer himself. Unless very carefully trained
and "managed" he will' not automatically adhere to
computer independence concepts. Consciously or unconsciously, he doesn't want to write programs that
others can understand and change or adapt to new requirements. He seems to fear being not needed on
his "creation." He tries to place his own personal touch
on his programs. At Westinghouse we instill in our
programmers the concept that the opportunity for advancement is in a large way depende'1t on their ability
to keep their work machine independent by careful
adherence to standardized routines and by careful adequate documentation. A complete description of standard documentation procedures has been included in
the Department Manual referenced earlier. If the programmer doesn't do the job in this respect, he is released or becomes relegated to the role of a clerk or
maintenance programmer with little opportuaity for
promotion or for involvement in the development of
new systems.
Computer system change should also be examined
from the point of view of the level of development of
the applications being run on the existing system.
Briefly as we see it in Westinghouse, there are four
levels of application development:
1. Observation-Standard data reduction or data
processing, the traditional data in, processed data
out approach.
2. Predictive simulation-First level in which the
information system or the mathematical model
is used for forecasting purposes; sometimes called
the "what if" game.
3. Inversion-The problem of predictive simulation
is turned around in order to achieve a "design"
having a specified performance.
4. Optimization-At the highest level, the concern
is to obtain a "best" solution from among "all"
designs providing a satisfactory performance.
<;;omputer system change in a large way depends
on the application level at which an organization is
currently operating; complete resystematizing and reprogramming may actually be desirable in order to
provide the impetus or opportunity to move up to a
higher level at the same time as hardware change.
Personnel attitude toward change and the ,requirements and competitiveness of the industry in which the
organization functions are other major factors affecting
such action.
CONCLUSION
All of these problems, however, are overshadowed
by the reductions in cost per job that computer change
allows. With the right attitude, the proper management
support, and proper planning, computer change can
be highly successful.
I have attempted to point out that computer change
is a full time continuing problem. Change to the next
system must be considered even while implementing
today's system change. Management policy must support change and all levels must work together to see
that change can occur economically, quickly and effectively to satisfy the changing requirements of today's
dynamic economy.
Machine-independence and third-generation
computers
by MAURICE H. HALSTEAD
Lockheed Missiles & Space Company
Sunnyvale, California
and
Purdue University
Lafayette, Indiana
INTRODUCTION
As a man with keen insight noted when third-generation equipment was first announced, the problems
posed by this equipment have only one reasonable solution: "Wait till you have the new equipment before
setting up your computer center." Accepting that point
of view, it follows that those of us working with existing computation facilities must concern ourselves with
somewhat less reasonable solutions and more difficult
approaches. It is one of these approaches, intended to
reduce (rather than to eliminate) the effort involved in
conversion, that will be described first.
Approach
The basic approach is quite simple. All that is really
involved are the implementation and usage of a software system that analyzes the binary deck of an IBM
7094 program, converts it to a machine-independent
language, and then compiles the machine-independent
version for the same or any new computer. Stated in
such direct terms, the concept is neither new nor complex. I ,2 However, it did require several years of implementation time.
One of the basic elements in the system is the machine-independent, manufacturer-independent, openended self-compiler employed both as the language in
which the system is written and as the language into
which the IBM 7094 machine-language programs are
converted. The language chosen for this role was
NELIAC. Because NELIAC has several unique features which contribute importantly to the success of
the system, these warrant description.
NELIAC
NELIAC originated at the Navy Electronics Labora-
tory eight or nine years ago, where it was first implemented on the Univac Countess (ANjUSQ 17)
computer. After the first 4000 words of the original
compiler were written in machine language, they were
rewritten in the NELIAC language and compiled. The
original 4000 words of machine language were then
discarded and all further extensions were programmed
in the source language itself. This approach provided
a relatively inexpensive method for extending the language to other computers. This can be seen in Figure
1 by noting the way in which the language has branched
from one computer to another.
The experience which Lockheed Missiles & Space
Company (LMSC) gained with this self-compiler on
the IBM 7094 illustrates some of its useful features.
Over a period of more than a year, a systems programmer added a new capability to the compiler about once
every month. Since he did his programming in source
language, each time the programmer added a capability
he compiled the new version by means of the old.
The data in Figure 2 show that even though the
size of the compiler increased as improvements were
added, the total time to compile the compiler was reduced by one-half. This is due to the fact that the
compiler was, by itself, a compiled program which
could benefit by these improvements. (Obviously, this
increase in speed of compilation was not gained at the
expense of the efficiency of the object code produced,
because the compiler was also object-code produced by
the same object code.) The combined effect is shown
by the data on Figure 3.
Starting with this compiler on the IBM 7094, the
process of converting it to the UNIVAC 1107 j 1108
involved nine steps as shown individually in Table I.
As can be seen from Table II, the effort required
587
588
Fall Joint Computer Conference, 1967
UNIVAC
AN/USQ
17 (1)
LEGEND:
1. NEL
2. UC - (BERKELEY)
3. CAl
4. TRW
5. LMSC
6. NRL
7. NOTS
8. WESTINGHOUSE
9. PACKARD-BELL
10. PERKINS-ELMER
11. GENERAL MILLS
12. AEROJET GENERAL (SACRAMENTO)
Figure I-NELIAC tree showing how the compiler on a
given computer was employed in the implementation of a
similar compiler for different machines
u.
o
w
!::!
VI
0
~ 0 ~::-,":"-:-:-~~J-.J.-:-I-..L--y.~..L...l.....L..J.......JL...1....L.L..l-L.J
;::
JFMAMJJASONDJFMAMJJASOND
1963
1964
Figure 2-Changes with time in the speed and size of a
NELIAC compiler on the IBM 7094
to produce the Intermediate Compiler (which ran on
the IBM 7094, accepted source statements, and produced UNIVAC 1107/1108 binary decks) was accomplished in 18 manweeks.
The control of both the language and the compiler
which this approach provided was used to make the
required extension. While it would have been desirable
to use FORTRAN as the language into which to decompile, the limitations of that language were often
responsible for the fact that programs were in machine
or assembly language in the first place. These, and
other limitations noted by Sassaman3 would have been
encountered. Seven of the features which were found
necessary to add or have in the language are shown
on Table III.
The decompiler was designed to operate upon either
an absolute or a relocatable binary deck of a complete
program. Theoretically, only a program which is complete and includes all of the subroutines upon which
Machine-independence and Third-generation Computers
589
_20
•
W
J-
::::>
Z
~
15
0:::
W
a..
Vl
J-
Vl
Z
~ 10
w
o
0:::
o
J-
3
Vl
o
«J-
u..
u..
o
Vl
ow
0:::
o
Vl
5
Z
::::>
I
o
4
z
«Vl
::::>
o
I
J-
o
J FMAMJJASONDJFMAMJJASOND
1963
1964
Figure 3-Variation with time in the speed of compilation of
a NELIAC compiler on the IBM 7094
Table I
Table II
STEPS REQUIRED FOR TRANSFERRING A NELIAC COMPILER FROM
THE IBM 7094 TO THE UNIVAC 1107/1108
EFFORT EXPENDED IN ACCOMPLISHING STEPS
NOTED IN TABLE I
1.
Rewrite generators, in NELlAC, to produce UNIVAC 1107 code
instead of IBM 7094 code.
2.
Compile the resulting intermediate compiler, using the original
IBM 7094 compiler.
3.
4.
Compile test case with intermediate compiler on the IBM 7094.
Execute test case on the UNIVAC 1107.
5.
Rewrite syntactical analyzer portion of the original IBM 7094
compiler.
6.
Combine rewritten generators with rewritten syntactical analyzer
and compile with the intermediate compiler on the IBM 7094.
7.
Load object deck produced in step 6 (on the IBM 7094) into the
UNIVAC 1107.
8.
Compile and execute test program on UNIVAC 1107.
9.
Compi Ie source deck used in step 6 with the compi ler loaded into
the UNIVAC 1107 in step 7.
4
8
9
CALENDAR TIME (WEEKS)
9
20
26
MAN MONTHS
4.5
10
12
118
118
TOTALS THROUGH STEP:
RUNS (IBM 7094)
47
COMPUTER HRS (IBM 7094)
RUNS (UNIVAC 1107)
2
12.22
12.22
14
42
COMPUTER HRS (UNIVAC 1107)
0.82
2.50
Table III
it calls can be decompiled. In practice, however, this
requirement seldom applies because most subroutines
do not alter the actual instructions of the calling program.
Again, in theory, the first pass of the decompiler is
intended to start with the first executable instruction
and determine the entire program flow, thereby separating data from instructions. In practice, as is expected,
the line of separation between data and instructions is
MAJOR EXTENSIONS TO THE NELIAC LANGUAGE REQUIRED
FOR THE DECOMPILATION PROCESS
cn D,
REMAINDERS:
A/B
INDIRECT ADDRESSING:
A[I]
MODE OF INDIRECT:
A[I] + .[BL] -+
BIT NOTATION:
A(0~14)
-+ B(0-+15) ,
SHIFTING:
A/2 i 5
-+
INDEXED INDIRECT:
A[I} + .[BL[IIJ-+
INDIRECT TRANSFERS:
X.
-+
+ [BL]
-+
C[I],
c(1),
A,
[L+IJ.
c[ll,
590
Fall Joint Computer Conference, 1967
not clear, since an instruction is often altered by storing
a new instruction into it. Separating data which are
always treated as data from those instructions which
"are always treated as instructions was, therefore, the
simplest part of the task. Determining those cells which
served both functions and then converting them to a
machine-independent form was the task which required the greatest talent.
Based upon this pass, or passes, the decompiler produces a NELIAC noun list that contains names which
it assigns to constants, variables, arrays, switches, etc.,
together with its determination of fi~ed, floating or
mixtd mode, initial values, etc. The decompiler then
generates the NELIAC statement of the logic of the
program, insofar as it is able to do so. In this process,
it utilizes those extensions noted above where they are
applicable and inserts, as crutch coding, any machine
instruction which it cannot handle.
Table IV is an example of a printout which shows
the absolute octal instructions of a program, together
with an assembly listing produced by the decompiler,
followed by the program as produced in NELIAC by
the decompiler. Table V shows the same items for a
subroutine called by the program of Table IV.
Table IV
SAMPLE OF AN ABSOLUTE OCTAL PROGRAM AS READ BY THE
DECOMPilER, ACCOMPANIED BY A DISASSEMBLY LISTING AND
FOLLOWED BY THE NElIAC STATEMENTS AS PRODUCED BY
THE DECOMPilER
040"13
04014
04015
04016
04017
04020
04021
04022
04023
04024
04025
04026
04027
0774
0500
0300
0601
0500
0300
0601
0074
0000
0000
0601
2000
0074
00
00
00
00
00
00
00
00
00
00
00
01
00
t
1
t
0
1
1
0
4
0
0
t
1
4
00006
04037
04045
04030
04053
04061
04031
04000
04030
04031
04067
04014
01000
El
AXT
ClA
FAD
STO
CLA
FAD
STO
TSX
PZE
PZE
STO
TIX
TSX
6, 1
FX5,1
FlTPT4,1
FX7
FX3,1
FlTPT2,1
FX6
Pl,4
FX7
FX6
FX1,1
El, 1, 1
EXIT,4
AC, FLTSP=O.O, FX 1(6), FlTPT2(6}=0.0, FX3(6),
FlTPT4(6)=0.0,
FX5(6), FX6, FX7, FXS;
START:
6-1,
E1:
FX5!1! + FlTPT4[1! _ FX7, FX311! + FlTPT2[J] _
PI (FX7 , FX6), AC _ FX II J] ,
1>1: I - I - I , E1.;EXIT, ••
FX6,
Crutch coding inserted into a program, when in the
language of the IBM 7094, serves as a flag to indicate
a point at which a conversion expert must study the
instruction and supply the proper machine-independent
statement. While this expert needs only to determine
what the instruction actually does and is not concerned with what the original programmer had intended,
Table V
A SUBROUTINE CAllED BY THE EXAMPLE OF TABLE IV
TREATED IN THE SAME WAY
04000
04001
04002
04003
04004
04005
04006
04007
04010
04011
04012
0634 00 4
0560 60 4
0260 60 4
0601 00 0
0560 60 4
0260 60 4
0300 00 0
0074 00 4
0774 00 4
0020 00 4
000000000000
PI: (D1.D2.)
{Dl*Dl --t FlTPTS,
04010
00001
00001
04012
00002
00002
04012
01000
00000
00003
PI
X4010
FLTPTS
D2*D2 + FlTPTS _
SXA
LOQ*
FMP*
STO
LOQ·
FMP*
FAD
TSX
AXT
TRA
PZE
X4010,4
1,4
1,4
FlTPTS
2,4
2,4
FlTPTS
SQRT ,4
**,4
3,4
AC, SQRT(AC)'} ••
it is still true that those things which the decompiler
does not handle are often even more complex than the
most sophisticated things which it does handle. Consequently, it is rather misleading to mention that the
decompiler handles 98 percent of the instructions in
straight-forward programs, or more than 90 percent of
the instructions in systems programs. While the decompiler does this, the remaining 2 or 8 percent requires a proportionately greater amount of programmer
time. Therefore, it seems more reasonable to say that
the decompiler eliminates % to 'VB of the reprogramming work.
While the LMSC Decompiler is not the first to be
written, it may be the only one to have reached operational status. As with all software systems, a considerable amount of improvement was required as a result
of the first field tests.
Programs converted with the system tend to lose
something in efficiency, running only twice as fast on
the UNIVAC 1108 as on the IBM 7094 (they should
run at 2.4 to 1) and usually requiring 1/3 more core.
While the date available are far from being complete, they do indicate what a very sma1I team of programmers, well versed in both the language and the
use of the decompiler, has experienced. They converted
some 250,000 instructions of combined FORTRAN II
and FAP by "Lifting" the FORTRAN and decompiling the F AP, as shown in the procedure chart of Figure
4. The task required fifteen weeks, with results distributed as shown on Figure 5.
The procedure being employed has not, as of this
writing, been extended to an operationally-tested tool
for recompiling decompiled programs on the IBM 360
system. While the Tree in Figure 1 shows that a
NELIAC compiler has been written for that computer,
the extensions noted in Table III have not all been incorporated into it and, consequently, only restricted
test cases have successfu1Iy demonstrated the process
for those computers.
Machine-independence and Third-generation Computers
I
I
NR:
OBTAIN
SUPERVISOR
CONTACT
I
DEPT:
J
r--
OBTAIN
PROGRAMMER
CONTACT
/
/66
/
OBTAIN
DECK
r----
/66
E:
/
/66
A:
/
/66
f--
I 59-22
I
PROGRAM NAME:
SIZE
JOB
--WORDS
--%FII
--%F IV
--%FAP
--%
-HR/MO
f-
-r-
COMPILE
FORTRAN
--
TEST
PROGRAM
E:
/
/66
E:
/ /66
E:
/
/66
A:
/
/66
A:
/ /66
A:
/
/66
DECOMP.
FAP
E:
/
A:
/ /66
l-
/66
~
COMPILE
NELIAC
E:
-
-
I
PROGRAMMER:
LIFT F 1\
:e-
591
REWRITE
FAP
E:
/
/66
A:
/
/66
-
A:
OBTAIN
TEST
DATA
/
/
I--
PREPARE
DOCWENT
/66
E:
/
/66
/66
A:
/
/66
CREATE
TEST
DATA
-
SATISFY
CUSTOMER
E:
/ /66
E:
/
/66
E:
/
/66
A:
/ /66
A:
/
/66
A:
/
/66
Figure 4-Sample of procedure charts maintained on each of
the programs converted
0
UJ
I-
0::
UJ
>
80
•
70 -
Z
0
::c
60 -
Z
50 -
U
I-
0
••
•
~
0::
UJ
c..
•
40 -
.
VI
0::
::>
0
::c
'g;
"""
30
I-
20 to-
•
,......
...J
4:
10
I-
0
0
•
•
•
••
I-
0l -
•
••
I
I
10
20
30
40
I
I
I
50
60
70
80
WORKING DAYS
Figure 5-Cumulative totals of computer load (in IBM 7094
hours/ month converted by an expert team)
Future strategy
While the methods discussed above are as useful
as any we know for handling the conversion of machine-
language programs-serving as it does both to convert
to the new computers and to "ge~ us out of the box"
of machine language-it is not a complete solution for
the future.
As pointed out in a paper by Dr. G; A. Garrett,4 the
advent of each new language, or of each new version of
an existing language, has been both a source of increased efficiency and a source of additional cost .
While the management of a computer center certainly
cannot be criticized for wanting to weigh the value of
the change against its expected cost, all too often in
the past this weighing has been rendered academic.
The manufacturers tend to implement only the newest
system on their newest machine. While they may provide FORTRAN IV under a given executive system,
the newer system will only have FORTRAN V. We
must look forward to the possibility that PL/I is only
the first term in some finite series, each imbedded in
a new and improved operating system. Since the operating systems are becoming, and must become, more
and more closely coupled to the operation of a computer program, it will not suffice in the future to have
machine-independent computer programs. They must
592
Fall Joint Computer Conference, 1967
be operating-system-independent programs as well. This
last requirement is worth considerable thought. The
number of control cards required to run a program
under each new operating system has been rising rapidly, and thus far, at least, there is neither a de facto
nor an ASA standard operating system. In fact, it is
not at all clear how such a standard could be reached.
Therefore, it appears only prudent for the larger users
of computers to examine the possibilities of producing
their own operating systems.
It is immediately apparent that if these operating
systems are to remain as cumbersome and expensive
as those now being produced by the largest manufacturers, then no user could afford his own. But as
drastic cost reductions in writing compilers followed
the introduction of higher-level languages sufficiently
powerful to write efficient compilers, it might be expected that the cost of operating systems might also
be reduced in a similar manner.
While a fair amount of emotional trauma would be
involved because operating systems are the last stronghold of the machine-language programmer, it appears
that a properly designed operating system, implemented
in an efficient higher-level language, might be transferred to a completely new machine as readily as the
compiler described above.
At that point, then, it would be feasible to provide
FORTRAN, COBOL, PLjI, and SIMSCRIPT to Base
Language translators, each written in the "Systems
Language." The Systems Language could, and should,
be extended to cover that part of present programs defined as the "Housekeeping" (in David Sayre's terminol-
ogy, the Phase 2 programming). Then, a single Systems Language to machine-language compiler and an
operating system under which they run would be the
only programs requiring change to fit a new computer.
Furthermore, the languages of the applications programmers would only be modified or extended when
the extension was deemed worthy by those responsible
for the results, the computer center management.
ACKNOWLEDGMENTS
The author is indebted to the members of the Advanced Software Group of LMSC Sunnyvale who have
implemented the system described, and especially to
Mr. Robert Stelloh and Mr. William Caudle for providing material for some of the figures presented.
Thanks are also due Dr. G. A. Garrett, Director of
Information Processing, whose quick perception of its
inherent value made the development possible.
REFERENCES
A OPLER
A utomatic program translation
Datamation vol 9 no 5 pp 45-48 May 1963
2 M H HALSTEAD
Machine-independent computer programming
Spartan Books Washington D C Cf especially chap 11
1962
3 W A SASSAMAN
A computer program to translate machine language into
FORTRAN
Proceedings 1966 Spring Joint Computer Conference
4 G A GARRETT
Managemellt problems of all aerospace computer center
Proceedings 1965 Fall Joint Computer Conference
A debate
Main frame memory technology
T.R. FINCH, Chairman
Bell Telephone Laboratories
Murray Hill, New Jersey
Present day digital processing capability has been
accelerated into being largely through the system opportunities offered by high-speed, large-capacity, random-access memories. Multi-user, multi-processor,
time-sharing systems extend system dependence on
improved memory and is bringing forth additional
technologies, such as optical and semiconductor to
compete with magnetic in the working memory area.
This session presents some of this competition by
bringing together magnetic and semiconductor specialists to discuss properties of their technologies related
to next generation main-frame memory systems. Magnetics versus semi-conductors; planar magnetic film
versus plated wire; and bipolar semiconductor versus
MaS will be discussed. The authors represent organizations that have interest and activities in all technologies so they are not asked to represent company or
system commitments. Emphasis is placed on memory
system requirements and the device-circuit-memory
properties of the several technologies may forecast
future acceptance and probable use.
Position papers by four of the panelists follow.
Planar magnetic film memorIes
deposition parameter control. The film may be continuous, or it may be etched into separate bits on lines.
Some form of flux closure is advantageously employed.
This may take the form of a ferrite or metal keeper;
or, in the case of a fu]]y-integratet structure in which
the drive and sense lines are deposited on the same
substrate as the magnetic film, complete closure in at
least one dimension can be obtained. One such structure is geometrically the equivalent of a flattened wire
memory.
The deposition technology employed may be vacuum
evaporation, sputtering, plating, or some combination
of these techniques. The planar geometry makes all of
these techniques practical whereas the cylindrical geometry of the wire memory is somewhat more restrictive.
Substrate material may be either dielectric material,
such as glass or mica, or it may be metal. Metallic substrates offer considerabl eadvantage in that they may
be employed as a reference ground plane simplifying
the line geometry and providing low impedance lines
with consequent low power and voltage levels.
A wide variety of film array terminal properties are
attainable within the definitions given above. Typical
properties for a fully integrated coupled film array are
given below:!
I Word
by Q. W. SIMKINS
Planar magnetic film memories offer many advantages for applications as main computer storage
units in the capacity range of 200K to 5M bits.
However, before we discuss these advantages, we
should define the technological alternatives available.
A planar magnetic film memory may involve either
integrated drive and sense lines, or separate drive and
sense lines on thin dielectric substrates. The film material most generally employed is a nickel-iron permalloy with or without the addition of small quantities of
another material such as cobalt. First-order zero magnetostriction is generally sought by composition and
200 rnA (6 nsee use time)
15mA
Illit
IlltemationaL Business Machines Corporation
Essex Junction, Vermont
1-2 mV
VSlgnal
Word lines
Bit lines
Somewhat lower packing
rent for equivalent signal
integrated array.
7 mils on 14 mil centers
4 mils on 6 mil centers
density and higher bit curlevel are required in a non-
Advantages
1. High-speed operation
Thin magnetic films switch very rapidly. Thus, the
access and cycle time of film memories is dependent
not on the individual device properties but rather on the
Hsu Chang, "Coupled Film Memory Elements," J. Appl. Physic
vol. 38, no. 3, p. 1203 (1967).
1
593
594 Fall Joint Computer Conference, 1967
array parameters and circuit and packaging designs
employed. Planar film memories have relatively low
drive currents, low impedances, and, consequently, low
power. This requirement permits the use of very highspeed circuits. In addition, array packing densities of
the order of 104 bits/in. 2 are achievable, leading to
relatively short drive and sense lines with relatively
large numbers of bits per line. When properly terminated, these transmission lines will result in fast array
recovery. This combination makes possible the design
of film memories of a million bits or more with cycle
times of < 100 nsec.
2. Low power
Word currents in the 100-200 rnA range are attainable as are bit currents in the 10-30 rnA range. Line
impedances of substantially less than 50 ohms are easily
realized. The low power requirement permits the use
of very high-speed circuits and also provided compatibility with monolithic drive and sensing circuits thus
contributing to low cost.
3. High packing density
Array packing densities of the order of 104 bits/in. 2
or even higher are achievable. These are at least an order of magnitude better than can be expected with wire
memories.
4. Large-scale integration
As technological advances are made, the planar
technology permits us to pack more and more bits on a
single substrate thus reducing the interconnection problem and simplifying the total memory packaging job.
This integration will reflect in the long run on product
cost and product reliability.
5. Magnetostriction effects
The use of a rigid planar substrate reduces the sensitivity of the film structure to magnetostrictive effects.
Disadvantages
1. Complex processing
The highly integrated structure requires somewhat
greater complexity in processing. However, this is an
initial entry barrier: the compensating advantage of
simplified packaging for the entire memory and the
reduced number of interconnections will far outweigh
this disadvantage.
2. Low signal levels
Although low signal levels are not necessarily inherent to the planar structures, they are the natural consequence of attempts to reduce power level and increase
density. Indeed, they represent a limitation in the
memory design and will require design of high gain/
low noise sense amplifiers. On the other hand, the electrically generated noise level in the planar array is
very low, particularly if a metallic ground plane is used;
and, as a consequence, the inherent signal-to-noise ratio that may be obtained is still quite favorable.
Plated magnetic cylindrical thin film
main memory systems
by G. A. FEDDE
Sperry Rand Corporation
Univac Division
Philadelphia, Pennsylvania
INTRODUCTION
Since research and development work started on permalloy thin films for random access memory elements in
the mid-1950's, the rapid development of ferrite core
memory technology has prevented the general use of
magnetic thin films. This occurred because magnetic
film memories did not have enough advantage in the
cost-performance-capacity comparison with ferrite
cores.
For the next generation computer main memory,
it appears that magnetic film memory elements will be
dominant compared to ferrite cores. The next generation main memory is defined to be within the limit
given below:
Cycle time - less than 500 nanoseconds
Capacity
- larger than 2 X 105 bits
- smaller than 5 X 106 bits
Random access to any word or byte
Based on film geometry, there are two main forms of
magnetic film memory elements-planar and cylindrical. Based on manufacturing technology, there are two
principal methods of film deposition-vacuum evaporation/sputtering and electroplating. For the businesscommercial' environment, the cylindrical magnetic thin
film appears to offer the best combination of advantages. For cylindrical films, electroplating is the most
practical means of depositing the film. Therefore, for
the purposes of this debate, it is asserted that plated
cylindrical magnetic thin film memory elements will
become dominant in the next generation computer main
memories. The degree of correctness of this assertion
should be apparent within the next two to five years.,
If the assertion is essentially correct, it is because of the '
factors discussed in the following paragraphs. It must
also be recognized, howevef, that even if all but one
major manufacturer committed their next generation
main memory designs to cylindrical films, they could
Main Frame Memory Technology
595
- - - - - - - - - . - - - - - - - - ----- -------.
remain subordinate if millions of bits produced per year
is the only measure of the degree of dominance. The
converse is also true. Whatever memory element and
technique is successfully used, by this same major manufacturer for their "next generation main memories",
could ce dominant based on production volume. An
equally signiicant measure of dominance, from the
standpoint of technical performance-cost factors, is the
percent of computer manufacturers that coml1)it their
new generation designs to plated cylindrical magnetic
film memory elements.
X 106 bits total; an individual bit yield of 99.728%; a
desired substrate size of 2.56 X 10 2 bits; and defects
are randomly distributed; then we find that cutting at a
fixed size (256 bits) gives 10 4 length with all bits good,
and ] 0 4 lengths with one or more defective bits. If we
cut the substrate whenever a defective bit is found,
the same total production yields 1.3 X ] 0 4 lengths with
all bits good. This 30% improvement in manufacturing
yield provides an important advantage for the continuous substrate manufactured and tested plated wire
memory element.
Elemental advantages
System advantages
Practically all widely used magnetic devices have
closed flux. paths except for those devices in which an
air gap is absolutely essential to their functioning. Magnets used in motors. voice coils, and kitchen cabinets
are examlpes in which an air gap is essential. Air gaps
in magnetic memory elements are generally nuisances,
or worse, and there appears to be a strong trend in
planar film memory devices to close the gap. A single
plating operation on a continuous cylindrical substrate
should result in a significant advantage for plated wire
compared to the alternate multiple process steps required in planar film technology to achieve a closed
flux path.
Another advantage is realized from the relatively low
cost of the capital equipment and high degree of mechanization possible in the large volume manufacture of
plated cylindrical thin film memory elements.
The continuous substrate provides another advan~age in the production testing and assembling of the
memory stack. Any memory element used in a nonseparable group of similar elements puts a severe demand upon process control and uniformity. This is true
for both cylindrical and planar magnetic films. Consider
the tyranny of numbers over yield using a wire length or
substrate area for 256 bits. A ferrite core yield in the
pressing sintering process of 95 % is excellent. The
probability of achieving 256 consecutive good cores at
this yield is 1.98 X ] 0- 6 • This is, of course, totally
unacceptable for a substrate yield. The wire substrate
is tested before cutting, so that when a bad bit is detected somewhere within the desired wire length (256
bits long), the wire can be cut and the short segment
discarded or used in a different memory design utilizing
shorter length wire. This compares to the testing of
planar films after the sense line has been bonded (open
flux path) or deposited (closed flux path) on the substrate and only the word lines need to be added. At such
a stage in planar film technology, a detected bad bit
rejects the entire 255 good bits instead of a fraction of
that number. If we assume a manufacturing run of 5.12
Perhaps the most significant system advantage available to users of plated magnetic cylindrical thin film
memory elements is a non-destructive readout capability. For main memory use, NDRD with equal ReadWrite drive currents is most advantageous. It allows
the greatest possible flexibility of organization and
operation. For maximum economy, many memory
words or bytes) may be accessed by a single word drive
iine without need for more than one set of sense amplifiers and bit current drivers. The set contains only the
number of amplifiers needed to process the bits of
one word (or byte) in parallel.
NDRD provides a higher average speed memory
memory system. If we normalize cycle time to the time
interval from initiation of a write cycle to the earliest
possible initiation of a read cycle within the same
module, then successive read cycles or a write cycle
following a read cycle may occur at a 50% to 60%
cycle time. For a system using 3 read cycles for each
write cycle, on the average, an overall average cycle
time of 62.5 % to 70% can be achieved if the computer system is organized to take advantage of this
fact.
The nominal value of bit-write current, compared to
some planar film memories, makes integration of the bit
dimension electronics straight-forward. At the present
time, plated magnetic cylindrical thin film memories
in production require 600 to 900 milliampere turns of
word drive. This is not a fundamental limitation but
indicates that the drive current amplitude has not been
a major drawback and other aspects of the develbpment of these memory elements has received priority.
The same techniques used by some planar film memories in the development laboratory, such as thinner
films, lower H k , and smaller geometries, are equally
applicable to cylindrical films to achieve low values of
word drive current if necessary.
Permalloy thin films, whether planar or cylindrical,
have high curie temperatures and are, therefore, relatively insensitive to changes in the temperature of their
596
Fall Joint Computer Conference, 1967
environment. In addition, both geometries switch a
smal1 volume of magnetic material so that drive line
inductance and impedance arc determined largely by
the detailed physical construction, particularly if a
magnetic keeper is used. From a practical standpoint,
the necessary drive voltage for a cylindrical film memory, with 640 bits per word drive line and 40 ns. rise
time, is only 5 volts which is easily handled in a
variety of ways. These considerations lead to a standoff between cylindrical and planar films. A similar
situation exists regarding operating current margins.
Cylindrical film NORO memories can be operated
with ± 20% margins on word and bit currents if al1 the
wires in a stack come from well control1ed production
lots. Since these margins are larger than necessary,
wider variation in lot-to-lot parameters are permitted
to improve manufacturing yield. Thus typical NORO
cylindrical film memory operating margins will be
±7%. For a fair comparison to planar film ORO
margins which may be a little wider, it must be remembered that DRO operation of plated wire memories
with the same wire population, would allow margins
of at least ± 10% .
Rather than attempt to quote price per bit and its
relationship to speed and capacity, the following table
shows relative cost only. Price is influenced by many
non-technical factors and can be misleading. The best
reference point that can be given to relate cylindrical
film memory cost to absolute numbers is that 8192 and
16384 byte plated wire NDRO memories (9 bits per
byte), with a 300 ns. access time and 600 ns. cycle
time, are significantly lower cost for us than ferrite
core memories of identical size and speed but with
DRO.
Module
Nanoseconds
Capacity
(bits)
Relative Cost
Cycle Time
1000
1/2
1 X 10 7
2-3
300-400
1 X 106
100
6-8
2 X 105
The closed flux path geometry provides a substantial construction advantage. The plated wire is tolerant
of wide variations in the relative alignment of word
drive lines to the longitudinal wire axis which is also
the "hard axis." This kind of mis-alignment does not
produce a favored direction of information storage
since there is not a component of word drive field paral1el to the circumferential easy axis. Plating the magnetic film directly on its own sense line also provides
constructional simplicity since no other drive or sense
line is used. The use of a continuous film eliminates the
need for any lengthwise alignment of wire to word
lines and allows the center line spacing tolerance to be
determined by other factors. Finally, the construction
of a plated wire memory stack makes it very easy and
quick, (approximately I minute), to replace a wire
that has slipped by the less than perfect clement testing
level preceding stack assembly. These advantages combine to make the fabrication and assembly of a cylindrical film memory appear to be substantially simpler
than a ferrite core memory.
SUMMARY
The foregoing very brief discussion has spotlighted
the basic advantages that are expected to bring plated
magnetic cylindrical thin film memory elements to a
dominant position in the next generation computer
main memory. They all point to higher performance at
lower cost than present main memories.
The case for bipolar semiconductor
memories
by R. S. DUNN
Texas Instruments 11Icorporated
Dallas, Texas
The discretionary wiring approach to the large scale
integration of active memories! permits several thousand memory cells to be interconnected on a single substrate. It also allows drivers decoding, and sensing to
be integrated with the memory matrix. This feature is
vital1y important in reducing the number of array connections required, maximizing packing density and
widening noise margins. Such a bipolar memory array
with 1600 active cells is shown in Figure 1. This technology is also appropriate for MOSFET memories.
Some method of minimizing the ratio of the number
of cel1s to the number of connections is essential to
realize the MOSFET potential for extremely high
packing density. However, integration of the MOST
control circuitry is only achieved at a substantial speed
and size penalty. Thus MOSFET discretionary wired
LSI memories will compete' most effectively at the
slower speed end of the memory spectrum. Multi-chip
assembly technology in particular beam lead systems 2
are attractive memory techniques since bipolar control
circuits and MOS storage cells may be intermixed.
However, the assembly costs and reliability are not
likely to be competitive with the bipolar LSI array. The
state of the art bipolar memory array such as that
shown in Figure 1 is fabricated by interconnecting 16
bit memory circuits with a second level of interconnection to form a larger function. The most important ad-
Main Frame Memory Technology
597
current distribution problems more than mask resolution capability and only modest reductions to 0.006"
x 0.01" are forecast over the next two years. However,
60 square mil memory cells provide over 8000 cells on
an 11;4" slice as shown in Figure 3. The discretionary
wiring approach will then allow products to be made
X 10-&
eXI '
./
6X 10'
./
/'
/'
./
-4 X 10"11
./
MEMORY
BITS
SQUARE
INCH
Figure I--Active memory array
2X10'
vances required to produce this array have been:
1. High yield circuits-extended through the use
of redundancy
2. Accurate automatic test
3. Efficient computation of the discretionary mask
4. Low cost mask generation
5. Very high quality multilevel technology
The cell using 0.0003" mask dimensions occupies an
area 0.009" x 0.015", as shown in Figure 2, and has
a read delay of 15 nsec and typical slice yield in excess
of 80 %. Projections on area per bit will be limited by
Figure 2-Active memory circuits
2Xlcr
- - CELL AREA
BITS ON ARRAY (I i-"SLIC
BITS INTERCONNECTED
Figure 3-Bipolar LSI array trends
with over 5000 of these cells interconnected and integrated with drive and sense circuitry. This then is more
than the matrix or stack, it is a functional memory
module which may be extended by the addition of
more modules, and represents the bulk of the memory
system cost. Relative to a fixed interconnection bar of
64 bits of similar cell quality with a 5% to 10% yield
per slice the discretionary connection will be 5 to 10
times more efficient in the use of the cells on a slice. A
5000 bit array price of $100-$150 would yield a per
bit cost of two-three cents and will be achievable within
the next few years. Further advances using larger slices
will further reduce bit costs by larger integration up to
10,000 bits per slice and represents the most significant
incentive for the use of larger slices. A block diagram
of a 128 word by 36 bit array is shown in Figure 4.
With address decoding less than 100 signal connections to the array are required.
The LST bipolar memory is hence applicable to
memory functions from 5000 bits onwards. The next
level of modularity beyond a single array will be
several arrays on a circuit board. A board of 1024
words or eight arrays represents a convenient size for
wired OR data line connections. In general the flat
board assembly is preferable in terms of maintenance
and thermal requirements to other assembly techniques.
598
Fall Joint Computer Conference, 1967
nsec by 1971. The larger memory capacity needs will
be met by the duplication of whole memories. This organization, coupled with NDRO operation and pipelining information flow cycling through the memories
presents many opportunities for increasing the efficiency of memory utilization. The opportunities in active memories to the semiconductor manufacturer are
such that this area will be one of the major markets
within the next five years.
ADDRESS INPUT
DECODE DRIVERS
REFERENCES
MEMORY MATRIX
R S DUNN G JEANSONNE
A ctive memory design using discretionary wiring for
DATA
OUTPUT
LSI
MEMORY MATRIX
2
I-
ISSCC 1967
J E IVERSEN et al
New implementation of bipolar semiconductor memory
ISSCC 1967
iiilL _ _ _ _M_E_M_O_RY_MA_T_RI_X_ _ _----'
Magnetics-still the best choice for
computer main nlemory
Figure 4-Memory array organization incorporating driver
and control circuitry
The access through the 1024 word memory board will
be kept below 90 ns with a dissipation of around 30
watts, i.e., 1 m W /bit.
This speed power performance requires only modest
advances from today's arrays. The board module size
is convenient for small memory applications and indicates the method whereby LSI memories will establish the production volume and the impetus for main
frame memory applications. The LSI memory being
produced for the Air Force by Texas Instruments
Incorporated falls into this category.
It is not anticipated that bipolar main frame active
memories will find commercial use prior to 1970 when
5000 bit arrays are available in volume. Some advantages of this class of memory are a common assembly
technique. One cooling system and a single impedance
level and signal level may be used throughout as only
one technology is used for storage and for control.
Ground return techniques and noise considerations
are also simplified, due in part to the high degree of
modularity. Power supply needs are uniform and the
number of supplies minimized. It is not, however, expected that any significant advances in volume or dissipation will be achieved by active memories. An examination of the speed and capacity of such a memory and
price trends indicates no real reduction for memory
systems over 500,000 bits. Target figures are 4-5 cents
per bit for memories with an access time of 100-150
by RICHARD J. PETSCHAUER
Fabri-Tek Incorporated
Edina, Minnesota
In virtually all of the computers designed in the last
10 years, static (non-rotating) magnetic devices have
been used for the random access main memory. Toroidal ferrite cores have been the predominant element
used principally because of their relatively low cost and
the circuit economies resulting from coincident-current
operation. Batch-fabricated magnetic structures have
received increased attention during the last 5 years by
workers in the field because of their promise to lower
memory array cost and increase speed. Most of the
activity has centered around the use of metallic films
in the form of planar structures or cylindrical surfaces
as in the plated wire. Commercial exploitation of these
film memories has begun as evidenced by recent announcements in the industry. Present applications are
in the area of high performance memories, but there is
reason to expect eventual lower cost as well.
Role of semiconductor memories
The rapid and widespread use of integrated circuit
logic devices by computer designers" coupled with
further improvements in semi-conductor technology
has raised the question of the impact of Large Scale
Integration (LSI) on computer equipment. It is generally agreed that this is a very complex problem. The
use of Large Scale Arrays for logic require solutions
to the problems such as forming interconnect~ons, debugging logic networks, specifying and testin'g multi-
Main Frame Memory Technology
state arrays, and attempting to standardize arrays so
that reasonable production runs and low per unit design costs can be obtained.
Since most of these problems are eliminated for
the memory function, where repetitive cells can be
used, some attention has been directed toward implementing memory with integrated semi-conductor
arrays. However in a memory of sufficient size for
main storage (5 X 105 ~ 5 X 106 bits) several other
serious problems arise which the writer feels will prevent their practical use in the foreseeable future. The
principal of these will be excessive storage cell cost
considering the competition of a magnetic memory.
Comparison must not be with present logic gates of
about 50c, but with a magnetic array of about 1c per
bit or less. In an attempt to reduce cell cost, density
must be increased substantially aggravating the processing, interconnection, and yield problems. Another
serious problem is the failure rate of equipment with
such a large number of semi-conductor junctions,
crossovers and connections. Based on· present integrated circuit failure rates, a 106 bit memory would
have a mean-time between failure of only a few
hours. Several orders of magnitude of improvement
are needed. Even if this could be obtained, accessability for testing and replacement of defective memory
cells must be considered and this could complicate the
design. Other secondary problems which must be
solved with I-C memories are handling the volatility
problem, keeping cell dissipation low, and removing
heat from the silicon.
Fruitful exploitation of I-C memories need not be
for main memory. They offer some obvious advantages for high speed scratch pad memories, shift
registers, small associative memories, some read only
memories, and other general areas requiring a high
ratio of logic-to-storage functions. The interest in
main memories seems to be less with the semi-conductor workers than it is with possible users. The chief
advantage of I -C memories is their compatibility with
logic. Their relatively low cost of selection circuitry
and their high storage cell cost causes cell cost to
predominate at capacities above 103 - 104 bits. Per
bit cost of magnetic memories continues to drop as
capacity is increased to 105 - 107 bits. It is not expected that the cost-crossover point will exceed 104 105 bits. Both types of memories will probably exist
together in new system designs utilizing some distributed semi-conductor logic and memory together with
a magnetic main memory providing the bulk of the
storage function. The magnetic memory could, of
course, be made in modules to increase throughput
or allow overlapping or simultaneous operation.
599
Bene/its 0/ magnetics
The main advantage of magnetic memories is
probably that they were invented first and are now
in a fairly advanced state of perfection. This applies
particularly to the ferrite core. It must be remembered that the development of any new memory approach is less of a design problem and more of the
development of a manufacturing process. This takes
time and money. Much of this time has already passed
for magnetic memories and a good part of the money
has been recouped during a period when the lack of
a competing technology allowed start up and learning
costs to be charged off.
At the same time it is felt that there is considerable
possibility for improvement in the cost-performance
of magnetic memories. Primary reasons for this are
the relatively simple and reliable magnetic array which
can be used, the fact that is amenable to batch-fabrication, as well as the practicality of integrating substantial parts of the electronic circuitry.
Future trends in magnetic memories
Trends which we should expect to see in future
magnetic memories are listed below:
1. Trend toward simple cell structures-2 or 3
wire arrays
2. More automated assembly and conductor termination or batch-fabricated arrays.
3. More fully automated plane testing
4. More standardization
5. Extended use of integrated or hybrid circuits
6. Improvde methods of packaging for stack and
stack interface circuits to reduce packaging and
assembly costs.
7. Reduced physical size
Some examples of possible magnetic memory approaches for future main memories are listed below.
Basic manufacturing costs do not include development costs, return on investment, administrative or
selling costs.
Examples 0/ possible magnetic memory approaches
1) Ferrite Core Memory
3 wire, 2~D 14/18 mil core; 500 nsec cycle
time; 106 bits, hybrid-integrated Y (digit) drivers and diode select; 2-3 ¢ basic manufacturing
cost.
2) Planar Film or Plated Wire Memory
2 wire, 2D; 2 x 106 bits (l6K x 144), 250
nsec - 500 nsec cycle time; hybrid-integrated
sense - digit circuits, discrete word selection;
2-4¢ per bit basic manufacturing cost.
600
Fan Joint Computer Conference, 196i
3) Advanced Ferrite Core Memory
2 wire, 2~D, 16/11 mil core; 500 nsec to 1
usec cycle time; 5 x 106 bits;
1¢ per bit basic manufacturing cost.
4) Second Generation Planar Film/Plated Wire
Memory
2 wire, 2D, higher density stack; improve flux
closure 4 x 106 bits, (32K x 144); 200-400 nsec
cycle time, integrated sense digit circui!s and
word. selection; 1c per bit basic manufacturing
cost.
SUMMARY
Integrated circuit memories, while finding use for
small capacity stores, are not expected to replace magnetic memories in capacities as great as those needed
for main memory (above 104 - 105 bits) primarily because of cost, manufacturing problems, and reliability.
We can probably expect a further increase in the types
of memory approaches employed - another level in
the heirarchy of memories. The system designers will
probably have the final answer in determining the
proper role and relationship of small fast semi-conductor memories and the lower cost magnetic stores.
Bulk core in a 360/67 time-sharing system
by HUGH C. LAUER
Carnegie-Mellon University
Pittsburgh, Pennsylvania
INTRODUCTION
In the fall of 1965, Carnegie Institute of Technology
decided to install Large Capacity Core Storage (LCS)
as the auxiliary storage device on its IBM 360/67
Time-Sharing computer system. The bulk core will be
used as a swapping device, replacing the drums of
conventional configurations, and as an extension of
main core memory. The decision was motivated by an
analysis which yielded the following results:
• The effective rate at which the system can deliver
pages to user tasks is increased to its theoretical
limit with LCS, representing a significant improvement over drum performance.
• The potential response time to users is decreased
because LCS has no rotational delay.
• Less main core is needed for effective system
operation.
In addition, LCS provides the memory necessary to
support specialized computing requirements such as
artificial intelligence research or large table-driven
compilers.
In this paper, we will present the assumptions and
analysis which shaped the configuration, ltJok at a
model of a drum-oriented system, compare it to LCS,
and present the Carnegie system and implementation
plan.
Background and assumptions
When a task executes in machines of the class of
the IBM 360/67 or GE 645, only the local portion or
neighborhood of its program and data which is actually
relevant at a given moment need be in core. What the
program "sees" is not physical core, but a space of
addresses called a virtual memory. A hardware
mechanism translates each address into a core location, if that address is part of the neighborhood in
core, or to a sllpervisor interrupt if it is not. In the
latter case, the monitor causes the block of virtual
memory, called a page, which contains that address
to be read from a swapping device into core. Thus, a
machine with a small physical memory can allow
several large programs to share it simultaneously. The
user is absolved from preparing overlays and deliberately fragmenting his program, while the system
bears the burden of swapping pages in a timely and
efficient manner. It is the efficiency of this swapping
process that concerns us here.
There are some special restrictions on the user
program in this system. For example, it is unwise to
refer randomly to locations in virtual memory; that
would generate a very high demand rate for pages.
Rather, the task should work in reasonably small
neighborhoods for relatively long periods of time. The
system is, however, a step toward the goal of providing
a comprehensive time-sharing system in which users
can operate conversationally or non-conversationally,
without restrictions on language, facilities, or program
structure. While we are realistic enough to see that
this goal will not be closely approximated for several
years, we do allow it to affect our thinking.
What we have just described is a system which
simulates a large core memory with on-line storage,
usually a disk or drum. The time-sharing capabilities
come with the structure of that memory, not its size.
It is worthwhile then to look at a large core simulation
system. One successful machine, at the University of
Grenoble, provides an 800,000 LISP word memory
on a 7044 with disk. 1 In this system, a swapped
program ran approximately one-third as fast as the
same program residing in core. However, from the
published data, it can be seen that the mean time
between calls for new pages (one might call it the
mean free path of the program) is a function of the
number of pages already in core, and is usually greater
than three seconds. If it is smaller, then the swapping
ovtrhead time becomes large relative to the user task
time, and the system loses efficiency.
Clearly, the mean free path depends on the structure
of the programs in the system. Investigators at SDC
have examined the behavior of several programs that
might be typical in a time-sharing environment. 2
601
602 Fall Joint Computer Conference, 1967
Existingjobs from the Q-32 machine were run under a
simulated paging system, and the mean free paths
were measured as a function of the number pages in
core. It was discovered that with neighborhoods
of only a few pages, the mean free path was extremely
small and the demand rate for pages per unit of task
CP time was high. In Figure 1, the number of pages
PAGES
IN CORE
TIME RELATIVE TO THE
BEGINNING OF THE TIME-SLICE
( MILLISECONDS)
Figure 1- Reproduction of data presented by Fine, et al SDC
in core is plotted against the time within a time slice,
assuming that the task starts out with no pages and
each is brought in on demand. It can be seen that once
a working set of pages is available, the demand rate
goes down from its initial high level. However, the
authors point out that with the program structure as it
is, the paging mechanism is bound to congest very
quickly, and "there would be little chance of processing-fetching overlap." Paging demands would
overwhelm the system.
We must be careful about translating such experiences to other computers, for the environment
has a heavy impact on the character and structure of
programs. For example, in the Q-32 analysis, they
were 30-46 pages long. In the 7040 and 7090 systems
programs are less than 32 pages long; yet results
for these machines strongly influenced the design
of the 360/67 and its software.
In the IBM Time-Sharing System/360 (TSS), there
is a tendency to code in many small modules, to separate data from procedure, to write re-entrant routines, and to functionally fragment programs. None of
this appeared in earlier machines, and all of it tends
to increase paging demands. Early experiences at
Lincoln Laboratory and at IBM with TSS indicate
that estimates such as Figure 1 are conservative, and
that the system is more page-bound than was anticipated. In particular, the knee of the curve lies at
about 40 pages. The Carnegie LCS-oriented system
is an attempt to create a machine which is not pagebound while minimizing restrictions on the structure
of task programs.
In the analysis that follows, we must make some
assumptions and avoid· others, based on experience
and "what's reasonable." In particular:
• We assume that the system is page-bouhd, with
a demand rate of the order of hundreds of pages
per second. Specifically, we assume that the
amount of swapping channel time is greater than
the amount of CP time which it supports, and
we direct our efforts to eliminating the consequent CP idleness at a reasonable cost.
• Our analysis will be oriented about the stochastic
nature of the system. We assume that each task,
and all random variables describing it, are independent of all other tasks in the system.
• We are unwilling to assume that any random
variables have particular distribution functions, with only the following exceptions:
1) The wait-time between the moment a task
requests a page to be read and the time at
which the swapping device becomes available to service it is uniformly distributed
over the length of the swapping channel
program.
2) The variable designating the location of a
page or group of pages on the swapping
device will have either the uniform or
singular distribution.
Both are justified because the state of the art
does not now provide mechanisms for decreasing
the expected wait-time to find pages in this
environment. Any such techniques depend inherently upon program struc"tures, about which
we know very little.
• We ignore file activity and concentrate only on
the swapping process. A more comprehensive
analysis, which will extend these results to
account for other devices, will be published in
the future.
• We will ignore correlations between the state of
the system at the end of a time slice of a task and
the state of the beginning of the next time slice
for that same task. We can treat shared pages,
which are swapped only infrequently, if at all,
as part of the resident system, and not as part of
the swapping load. The demand for space for nonshared pages will be sufficiently high that only
Bulk Core in 360/67 Time-sharing System
a negligible number of them will survive in core
during the interval between time slices.
• After we have experience with the system, we will
take advantage of correlations between system
states to improve scheduling algorithms; now we
can only do this in a limited way.
• Inefficiencies in monitor coding can be ignored.
We are interested in the hardware capabilities,
not software performance, so we will assume the
ability to write clean code. The supervisor
overhead for an interrupt can be assigned to the
task which caused it. Consequently, the task time
is the total amount of CP time dedicated to that
task for both user computing and overhead, i.e.,
the marginal increment of computing load added
to the system by that task. The fact that overhead may amount ot 1% or 90% of the task time
is irrelevant to us here.
With these assumptions, we can proceed with the
analysis.
Drum-oriented system
The drum which we consider as a swapping device
has one read-write head for each track, but only one
head can be connected to the channel at any moment.
There are p pages recorded on the circumference of
each track, and there is sufficient space between
pages to permit head switching. Thus, it can read the
first page on track a, followed by the second page on
track b, and so on through the pth page on track x, all
in one revolution. We can regard the drum then as a
,equence of p slots passing by a single head. When the
head is over a particular slot, one and only one page
may be read or written in that slot. The drum operates
asynchronously from the CP under the control of its
own channel program. Once an operation has been
started, it may not be interrupted or altered except
in the case of malfunctions.
Figure 2 will help describe the system which we
model. At time A, a channel program was initiated to
run until time B. Tasks 1, 2, 3, 4, and 5 execute in
turn until each develops a page request. By time B, all
requests have been analyzed and a new channel program has been prepared. The figure shows examples
of what can happen:
1) The page for task 4 was located on the first slot,
so that task 4 is ready to execute almost immediately.
2) Task 1 is serviced next, then task 2.
3) The page request for task 3 happened to fall in
the same slot as that for task 2, so it must wait
a full revolution before it can be serviced.
4) Task 5 has a long wait because of the locatIon
of its page on the drum.
603
ALL TASKS IN
_IT STATE
~
2.-------!.---.----.... ---..1!.
TASK I
~------!.----_.--
TASK 2
ROY
__--. R.
-------!-------..
• EX •
• EX • _____! ______ •
ROY
••- __.::.:;LOT=COIIFUCT=:..:..:_=-;.::WIT=A.:::.;!OLIITIOJ=~R..........EX::.-.
• W, R.~
EX
• ---.;.--!.--------...A.
~-_-!----
TASK 3
EX
TASK 4
EX
•
___________!. _____________
~
TASK 5
~
B
A
:;I cr l'
'lID' '
PC*T _ _ _
T ___
~·~II~X
I'OIIIT
U.
c
I
,
,
I
,
,
""_X
I'OIIIT
y
P SlOTS PER
- REVOLUTION
.,... .l • TRANSFER TIME
!! PER PAGE
'.
TIME
EX-EXECUTE
W - WAIT FOR PAGE
R -READ.
ROY-READY
WR-WRITE
Figure 2 - Example of system execution
5) Several slots which are not needed to service
tasks at the moment are used to write out old
pages from core in order to make room for new
pages.
6) Shortly after time C, the CP enters the wait
state because all of the tasks are waiting for
pages, and there are no others ready.
Though we had four requests at point B, we could
only service three of them because of a slot-conflict.
Of course, had the system been able to anticipate
either the slot conflict or the idle time, it would have
taken corrective action; but our assumptions about the
independence of tasks and the randomness of page
locations preclude this.
In the following paragraphs, we will calculate the
rate at which the drum can deliver pages and observe
the relevance of this to the mean free path of tasks.
Then we will discover a lock-out phenomenon, by
which the drum causes pages to be withdrawn from
usable core. We will also explore some ideas to swap
groups of pages as a means to overcome some of the
problems we encounter.
Deliverable page rate - demand paging
We consider the case in which all channel programs
are the length of one drum cycle, of time T. The expected rate at which pages are read is a function of k,
the number of tasks in the drum queue, and!, the probability that a page must be written out to make room.
It is possible thatf < 1, since some pages in core may
have valid copies on the drum already (by virtue of
being re-entrant, or otherwise not changed since
being read). Then for each page requested, the swapping channel must handle an average of 1 + f pages.
604 Fall Joint Computer Conference, ! 967
Thus, the maximum
aver~ge
request rate which a p-
slot drum can service is 1 ~ f per
revolution
or
200
...,::::.:::::
(1 -:j)T pages per second. The one-sided effect which
occurs when f is greater than its mean is negligible
if the system maintains a buffer of free pages into
which the drum can read.
Because of slot conflicts, this rate can only be
approached. A classical probability exercise known
as the Urn-model Occupancy problem gives us the
result. 3 With p slots and k requiests, the probability,
Ph that exactly i pages (1 ~ i ~ min (P,k)) can be read
in one revolution is given by
P, = (p
_P~,
±
0' v=o (-I)"
I . I.
(C~!)'
,) (i p- v )~.
v. v.
I
The average or expected number of pages which the
drum can read, given k, is
,..
M,,=LiPj.
i=l
If Mk is less than I ~ f
there will be sufficiently
many unused slots in each revolution to do the necessary page writes. Slot conflicts pose no concern
during writing because the supervisor chooses the
output location after the read requests have been
scheduled. Thus, for queue of length k, the drum can
deliver
Q,.. = min
(M,.., I ~f)·
pages per revolution. The total effective swapping
rate is the mean of the Q" weighted over the probability distribution of k. (This distribution can be
determined empirically or by making assumptions
about the program structure.)
In Figure 3, we plot M" as a function of k andffor
several examples. The case p = 9 and T = 34 msec is
the TSS drum system, where 9 pages are recorded on
two tracks (the length of a page is 4096 bytes = 1024
words). The case p = 4, T = 17 msec, is the same drum
reformated to waste some space in favor or reducing
the length of the cycle. The final case is a hypothetical
drum which can hold only one page per track, but
rotates with T = 3.4 msec, the maximum speed of the
channel.
We see from the figure that the hypothetical drum
requires only one task queued for service in order to
maintain the maximum swapping rate, but the others
require 3-4 tasks and 8-10 tasks in the queue for p = 4
and p = 9, respectively. If k is smaller, then some slots
are idle while tasks wait because of slot conflicts.
rT;-i7r----:-.::::- - - - - -
~--------..,.'.:.::::::.•.:!::..~~::.•.: ....:.
,
...
/--f"';'213-..::·--------------/
150
Mk • DELIVERABLE
PAGE RATE
J
PAGESI SECOND
I
J
I
J
J
f.···
....
/
/
f ·112
I
••.•••
...
•••.
!'p.4
•..•
...
.....
.... p.g
••••
....
•••
..'
f.···
2
345
6
7
8
9
~
~ a NUMBER OF REQUESTS IN DRUM QUEUE
Figure 3 - Deliverable paging rate
But those slots must still pass the read.:write head,
and this wastes channel time. Our initial assumption
was that channel time is at a premium and cannot be
lost; so if we use one of these drums, we must operate
with a large k. Main core must then be big enough to
contain the many tasks which make up the drum
queues plus some tasks which are ready to execute.
We will see shortly just how much core this must be.
The· effect of adding drums on separate channels
can be seen from this model. Although they would not
be synchronized, they could be coordinated and
scheduled together. Then for n drums, the maximum
n·p
page rate is I + f One could also plot a graph of M I,
versus k, and one would find a more rapidly rising
curve than in the case of a single drum. This can
be attributed to the fact that there are n times as
many slots passing the heads in the interval of time
T, and thus less chance of a slot conflict for a given k.
Requirements of mean free paths
We would like to maintain complete processorswapping overlap. To do so, the total amount of CP
time necessary to do the work must be at least as
great as the total amount of channel time necessary
to support the CPo From this, we can determine the
minimum mean free path of tasks. If k is the drum
queue length, then in a revolution of time T, Mk tasks
are delivered to the CP, on the average. Their total
execute time must exceed T so that the mean free
path must exceed TIM,... In Figure 4, we plot this
value as a function of k. For large k, there is little
difference between the three cases; but for k, equal to
two or three, the hypothetical drum restriction is less
Bulk Core in 360/67 Time-sharing System
605
single page, a function of the rotational delay of the
drum. Suppose for the moment there are no slot conflicts. Then the wait time is
w = tl + joT
where
tl = a uniformly distributed random variable representing the time to the beginning of the next
channel program;
o ~ tl ~ T.
j = the slot position of the pag~ requested, uniformly distributed over
MINIMUM
MEAN FREE
PATH
MSEC.
I
5
T
7
8
9
10
Figure 4- Minimum allowable mean free path
by a factor of two to four. (We will see that LCS,
when operated with a core-to-core channel is a realization of this hypothetical machine.)
From this calculation, we can discover how short
our average time slice can be. An example will help.
Suppose that tasks exhibit the behavior of Figure 1
with the knee of the curve at one millisecond and ten
pages. Suppose that the drum can deliver 100 pages
per second. Then the time slice must be at least 100
milliseconds, for the drum can "set up" no more than
ten tasks per second. Any attempt to run with a
smaller time slice will automatically generate CP
idling.
I t should be pointed out that this discussion deals
with averages, and not the statistical fluctuations of
random variables. Thus, our requirements are only
necessary; they are definitely not sufficient. For
example, if all tasks with free paths less than the
mean were scheduled together, followed by all others,
first the CP would idle, then the channel. On the other
hand, if there is one task with an infinite free path,
then there is no restriction on the others provided that
one is not bumped from core. When a more comprehensive model and some empirical evidence are available, we will be able to generate sufficient 'conditions
for complete overlap.
The lockout effect
Suppose we are able to keep the CP ahead of the
channel. We will make an estimate on the amount
of core necessary to support this - i.e., the amount
of core necessary to contain the tasks which are in
the page-wait state. To do this, we want to calculate
first the amount of time a task spends waiting for a
~j ~
p.
T
= - = the transmission time of a page.
p
Then the mean wait time is
_
_
7_
T P+ 1_
(
1)
w = tl + J"T = 2 + -2-- T = T 1 + 2p .
If n pages are requested by a task during a time slice,
it spends n time the value w in the wait state. When
we consider slot conflicts, this value could increase
by as much as 50%. However, we must know the
stationary distribution of k in order to make explicit
calculations.
Let a task begin a time slice. It demands its first
page and waits an expected time of w milliseconds,
and ties up one page of core for that time. A short
while later it demands its nth page, it ties up n pages
of core for w milliseconds. During the entire time
slice, it causes a total of page-milliseconds of core to
-+2-+
- = w
-~.
.w ... + n.w
L.J 1= _n(n-l),
W ---'--....:.
1.w
i=1
2
have been devoted to waiting for the drum to spin.
These page-milliseconds are not available for any
other purpose, but only to support the task for its
slice of length, say, t. In other words, we must expend
- n(n 2t
+ 1) page-ml·11·Isecon d s 0 f
·In page walts
. to
w
core
get a millisecond of useful work. I.e., in complete
processing-swapping overlap conditions, an average
of
Wn(n
2t
+
1)
core pages are tied up waiting for the
drum at all times.
Let us calculate an example using the SDC data
of Figure 1 applied to the 360/67. From the figure,
we see that if t = 160 milliseconds, then n = 24 pages.
For a conservative estimate, we ignore slot conflicts
and take w = TO
ip-). Then
+
iii = 36 msec if T = 34 msec, p = 9;
W = 19.1 msec if T = 17 msec, p = 4; and
w= 5.1 msec ifT= 3.4 msec,p= 1.
606 Fall Joint Computer Conference, 1967
The total wait-time for all 24 requests is
860 msec if T = 34, p = 9;
460 msec ifT = 17, p = 4; and
122 msec if T = 3.4, p = ].
(I.e., the setup time for a 160 msec time slice is 860
msce in the case of the nine-slot drum. During this
time, others are computing, but the conversational
user will see the delay in the form of poor response
time.) The locked-out core amounts to
62 pages for T = 34, p = 9;
33 pages for T = 17, p = 4; and
8.8 pages for T = 3.4, p = I!
With regard to slot conflicts, observe that each conflict adds only 3.4 milliseconds to iii in the case of
p = 1, but it adds 34 milliseconds to w in the case
p = 9. Thus, the high probability of conflict on the
hypothetical drum is offset by the expense of conflict
on the nine slot drum. I n actual operation, we would
find that the number of pages locked out would be
greater than the values we calculated by roughly the
same factor for each of the three cases.
These costs in core to support demand paging with
conventional drums are very high, and nearly all of
it can be attributed to the rotational delay. The analysis can be generalized and the same kind of results
can be obtained for file operations from disks. It can
also applied to non-360 time-sharing systems to obtain
similar results. Neither must one restrict himself to
fixed sized pages or a demand-paging concept. The
principle is clear that the best device is one which
rotates with a cycle of no more than the transmission
time of the smallest swap, or one which does not rotate at all- i.e., LCS.
Affinity paging from a drum
Several proposals have been made to improve drum
performance over the demand paging case. Most of
these involve swapping groups of pages which have an
affinity for each other. I.e., if one page is requested,
the supervisor recognizes that certain others will be
requested with a high probability and initiates the
swaps for those at the same time. In this way, the
wait time for several requests is overlapped, and the
amount of core necessary to support the drum is cut
by an appropriate factor. Among the proposals are.
that of swapping whole programs at once (CTSS at
Project MAC), reading in at the beginning of a time
slice all of the pages which the task used during the
previous one, or maintaining a set of links in the page
tables in the supervisor which relates every page to
its companions.
One can either require that all related pages be
,written in contiguous slots on the drum or allow them
to be located randomly; each has advantages. In the
former case, there is no possibility of slot conflicts
between pages of the same group, and there need be
a delay of at most one rotation to access them all.
However, if two tasks each request groups of pages,
and the sequences of slots for these pages overlap,
one task has a very long wait while the other reads
plus an additional wait while the drum spins to the
proper place. The latency for two independent requests cannot be overlapped as it could in the demand
paging case. Furthermore, when the system must
write pages, it must find a sequence of slots long
enough to contain all of the group. Our analytical techniques are not sufficient for calculating Jhe deliverable page rate or the amount of locked out core under·
this configuration. Neither can we determine here
whether the advantages offset the disadvantages.
In the latter case, where pages are located randomly on the drum, the calculation of the deliverable
page rate for the demand paging drum applies. If a
task demands m pages, this is equivalent to m tasks
each demanding a page, at least from the point of view
of the drum. I n fact, we increase the effective value
of k in those calculations, increasing the swapping
rate, without adding more tasks to core. The fact that
the latency of the m pages is partly overlapped also
reduces the total amount of core time necessary to
support a time slice of computing. Clearly, this type
of affinity paging is an improvement over demand paging.
If swapping is done from LCS, affinity paging is
useful only if the swapping channel is not busy. Since
there is no latency time, the amount of waiting for
two pages is twice that of one page. If the channel is
free, then we can initiate a swap for the task which
is executing before it demands that page. But if other
tasks are demanding immediate service, they must be
handled first to reduce the chances of the CP idling
for lack of work in the ready state.
We should point out that we assumed the system
supervisor has some way of recognizing page affinities. This might result from a heuristic operating in a
demand paging environment which- "learns" which
pages are related. We might require the user of his
compiler to specifically define the relationships before run time. Or some other method could be used.
In any case, affinity paging appears to be a necessity
for systems committed to using drums for swapping.
But the benefits of using LCS go beyond the realization of the hypothetical one-slot drum, as we will see.
Comment
We have seen that a drum cannot deliver pages to
tasks at the maximum rate of the ·swapping channel
Bulk Core in 360/67 Time-sharing System
unless we allow large queues for service to build up.
This is because of its inherent rotating nature, which
wastes channel time with slot conflicts. Only in the
degenerate case of p = 1 is it possible to get maximum
performance with short queues. The rotational
delay causes tasks to spend a disproportionate amount
of time in the page wait state, relative to the computing they do; and this eats up core. Affinity paging reduces these problems, but so does LCS with a swapping channel. Carnegie has chosen the latter path.
The concept of giving each user a slice of CP time
out of an operational cycle of say, one or several
seconds, has been very popular in time-sharing circles - indeed, some will take it as the definition of
time-sharing. But our analysis has shown that there
are other costs in providing computer service, such
as core space-time, and channel time. If the user
demands these in unusual proportions, the system can
get bogged down. Perhaps when we allocate his time
slice, we should also allocate core time, channel time,
I/O time, and other resources. If he exceeds anyone
allocation, or perhaps if he exceeds some function of
them, his turn in the operational cycle should be considered ended. If, for example, we granted a core time
slice instead of a CP time slice, he would be entitled
to squeeze as much computing out as he could, provided he did only little paging. Or he would be entitled to swap heavily but only compute a little. But
whatever the allocation scheme, it should be designed to keep the demands for the various scarce resources in proper balance to avoid waste.
We have examined the system costs with respect
to channel time and core space, but we have not discussed the effect of fixed size pages. In the 360/67,
this is irrelevant because the hardware is designed for
4096 byte pages. In the larger domain of time-sharing,
variable size pages should be considered, for it is
apparent that a lot of swapping is done to gain access
to only a few words. If only those words were swapped, it might be possible to save significant amounts
of overhead. LCS will provide us a crude approximation of this ability by allowing direct accesses to
words stored there.
The Carnegie LCS-oriented system
In place of a drum, we provide an equal amount
of bulk core storage with 8 /Lsec cycle time, addressed
as an extension of main core. A con~-to-core channel
(known as the Storage Channel) allows information
to be block-transferred from any memory location
to any other, independent of and overlapped with
CP operation. This channel behaves exactly like any
other I/O channel on the system and operates slightly
faster than a drum channel. Thus, we can treat the
607
LCS as an on-line device which does the page swapping.
Because there are no rotational delays, the channel
can access any page as soon as it finishes a previous
operation. In this sense, it is like the one-slot hypothetical drum which we discussed above. With it, we
can enjoy the maximum possible paging rate without
maintaining large queues of idle tasks. The restriction on the mean free path of programs is less than it
would be if we allowed only a small number of
tasks in core and a low drum paging. rate. Perhaps
most significantly, we do not need to maintain the
extra 30 to 60 pages of fast core to drive the drum.
Each task spends less time in main core waiting for
pages and, consequently, gets through its time-slice
in less real time.
An equally important benefit of LCS is the fact
that it is addressable directly by the CP as an extension of main memory. It is possible that when a
task references a page, it may not be worth the overhead to swap it. For example, only a few words from
the page may be needed for the immediate processing. If the page resided on a drum, it would have to be
swapped, no matter what. But if it resides in LCS,
then the page tables can be set so that the CP thinks
it is in core and accesses the information directly,
word by word. The cost involved is the CP degradation due to the long cycle time of bulk core; the savings
come from the fact that there is no swap or other system overhead. The trade-off point is determined by
the usage of the page.
For example, suppose that it takes 500 /Lsec of CP
overhead to process a paging interrupt. Suppose also
that it takes 4 /Lsec to fetch a double-word in LCS,
over and above the normal access time in fast memory.
Then by not swapping a page, we can buy 125 direct
accesses to LCS; we leave.the Storage Channel free
for other use; and we do not tie up a page of fast core.
One can easily think of many data structures which
occupy a thousand words, but are not referenced more
than 125 times per time slice: e.g., a data set catalog,
a portion of a large IPL-V list, or a string of post-fix
code to be executed by an interpreter.
A. L. Sherr has pointed out that there is much to
be. gained from small page sizes, provided the overhead of swapping can be counquered. 4 What the LCS
configuration does is provide two different page sizes
- the one is the 4096 byte page which is swapped, but
which remains available throughout a time-slice;
and the other is a double-word "page" which is accessed only at the cost of an LCS cycle, but which is
highly transient and must be re-accessed each use.
Each serves its own function; the larger supports
normal computing, while the smaller provides effi-
I
608 Faii joint Computer Conference, 1967
cient .access to large data structures. This duality decreases the rate of demand for swapped pages by the
task, or equivalently, increases the ability of the system to Uleet the demand rate.
The question of how to decide which pages should
be swapped and which should be accessed directly is
an unsolved one, not unlike the question of defining
affinities between pages. We propose no solution here,
but we observe that a simple method is to require
users and ~ompilers to identify which pages are
which. Certain stimuli can be created to induce users
to do this efficiently, but caution is important. Our
object is to fit the machine to the users, not the users
to the machine.
The machine configuration
Figure 5 shows the single-processor simplex system initially installed. The machine differs from a
able for other use in the LCS system, cost 6%-12%
c. The same basic system with LCS cost
c - (drum) - (locked out core) + LCS
or 7%-12% more than the drum machine. However,
for this, we get a faster paging rate and a much more
flexible machine.
A duplex system scheduled for operation at Carnegie in the future is shown in Figure 6. The system
has two Central Processors and two Channel ContrQllers, each with an independent access path to
memory modules. Attached to each Channel Controller is a Storage Channel as well as conventional
multiplexor and selector channels. There are no
no drums, but other I/O devices are configured in the
same way as on a standard Model 67 .
A half-duplex system is.essentially half of the system in Figure 6; i.e., one CP and one Channel Controller each with an independent access to memory.
-____
_ __ _
4rBOXES
FORA._A_TOTAL
OF 8M
MODEL
67
CP
MODEL
67
CP
DISKS
DRUM
NOTES
K' 2'0. 1024
M. 220. 1024K •
S'OItl" ACCEIIWIDTH " • IYTU
(.6. IITS PLUS '''",TY»
ALL ITOIilAK IS TWO· •• T INTIIIIUAV(D
FIGURE 6
Figure 5 - Simplex 360/67 with LCS
standard 512K byte 360/67 5 by including over four
million bytes of IBM 2361 Large Capacity Storage
and the Storage Channel for core-to-core transfers.
No drum will operate in the system. The LCS has an
8 microsecond memory cycle, a 4 microsecond access
time, an 8 byte (64 bit) data width, and is two-way
leaved. Thus, it can support a data rate of two million bytes per second. The Storage Channel is controlled by the same type of channel program as other
360 channels, and can transmit 1.6 million bytes per
second (400 pages/second) between locations in core.
This machine costs more than the equivalent drum
machine. Suppose c is the cost of a basic 512K
360/67 with one drum and a normal complement
peripheral gear. Then, the drum and its channel represents about 7% c, while the same capacity of LCS
(with Storage Channel) costs 25% c. The amount of
fast core locked out by the drum, but which is avail-
PUPLEX 360167
~
NOTES:
IK - 1024 _ 210
1M- 1024K-2z0
DATA WIDTH 'OR
nORA. IS I IYTES.
AU. MEMORY IS
TWO-WAY INTUL.t:AVED
Figure 6 - Duplex 360/67 with LCS
It is logically identical to the simplex system, but
functionally the conflicts between I/O, Storage Channel, and CP are resolved at the core modules rather
than at the storage bus. The resolution circuitry introduces a delay of 150 nano-seconds per memory
access, which degrades CP -performance from specifications. However, high I/O rates and Storage Channel transmission also degrade CP performance in a
Bulk Core in 360/67 Time-sharing System
simplex system by causing memory bus interference.
The trade-off point between the simplex and halfduplex systems was determined by simulation6
and corroborated by analysis of manufacturers' reports. Essentially, if the utilization factor of the
Storage Channel is less than approximately 50%,
then the simplex system gives better performance,
Otherwise, the half-duplex system gives better performance. There is no suitable half-duplex machine
available to compare to the simplex machine in order
to verify these results. If the present analysis holds
up, Carnegie will upgrade its initial system to a halfduplex machine when practical.
CONCLUSIONS
From the analysis presented in this paper, Carnegie
Institute of Technology has discovered that it cannot
live with time-sharing on a drum-oriented machine
with demand paging. The swapping rates which it
can support are too low for practical operation, unless
we admit a lot of extra, expensive main core. Paging
from bulk core, where there are no slot-conflicts,
yields a factor of two to four better performance. At
the same time, the LCS allows a reduction in the page
demand rate because it can be directly referenced.
We have also discovered that the inherent rotational
delay of the drum has the effect of withdrawing 30
or more pages of memory from usable core at all
times. Then in itself is expensive.
We recognize that, like all models, our model is
only an approximation. However, we feel confident
that we have effectively handled the first major problem of understanding what is required to make timesharing work. Whether we have made forward progress or whether another equally big problem is hiding
behind this one, only time will tell.
All of the improvements which come with LCS
are needed, and they more than justify the extra expense. A rotating memory is too inflexible and in-
609
accessible to support a comprehensive time-sharing
facility, just as it was found to be too inflexible and
inadequate as the main memory for second generation
computers.
In fact, before the "fourth generation," we will
probably find that large non-rotating memories assume
increasing importance both as swapping devices and
storage for large on-line files. Carnegie cannot afford
to wait for this trend.
ACKNOWLEDGMENT
I wish to thank Professors Allen Newell, Alan Perlis,
and Mr. David Nickerson for their valuable comments
and their enthusiastic endorsement of the system.
Mr. Michael Gold and Mr. Manuel Langtry were very
helpful in clarifying the ideas and presentation. Miss
Polly Breza, Mrs. Cynthia Yang, and Mr. Albin Vareha, who are responsible for the software modifications to TSS, have kept the discussion down to earth.
Finally, Miss Joyce N issenson has helped with the
manuscript.
REFERENCES
1 J COHEN
A use of fast and slow memories in list-processing languages
CACM Vol 10 1967 p 82
2 G FINE CJACKSON and P McISSAC
Dynamic program behavior under paging
Proceedings - Nat onal ACM meeting 1966 p 223
3 WFELLER
I ntroduction to probability theory and its applications
Voll pp 91 ff
4 ALSHERR
Analysis of storage performance and dynamic relocation
techniques
IBM document TR-OO-1494
5 CTGIBSON
Time-sharing with the IBM 360/67
FJCC 1966 p 61
6 K GRAHAM
Unpublished results Carnegie Institute of Technology 1966
Modular computer design with picoprogrammed control
by J. G. VALASSIS
Automatic Electric Applied Research Laboratory
Northlake, Illinois
INTRODUCTION
The subject computer is a 16-bit, one microsecond,
integrated circuit computer implemented with picoprogrammed! internal control. (Picoprogramming is
conceptually comparable to microprogramming but
without the need for decoding logic.) The design
provides for modular CPU expansion both in wordsize and instruction-repertoire. In addition, it lends
itself very admirably to post-design tailorability, which
is the most important unique feature of its picoprogrammed control design.
Picoprogramming is realized by use of the MR YiAperture (MYRA2) element, a multi aperture ferrite
device which is the basic building block of the instruction module. Each instruction module is a complete entity and is fabricated on a conventional printed
wiring card that can be inserted in a conventional PC
connector. Incorporation of a new instruction in the
computer or alteration of an existing one is accomplished by the addition or substitution of the appropriate instruction module card.
Decoding of the contents of the machine instruction
word provides the address for the selection of a particular instruction module. A selected instruction
module generates the necessary serial control levels
and pulses. The timing of these pulses has been
charted to effect the appropriate data transfers within
the machine's CPU to hardware-implement the microoperations specified by a particular instruction (e.g.,
ADD, Y). Each instruction module can be thought of
as the decoded output of a fast microprogrammed
memory whose microinstruction-word contents dictate specific operations within the CPU to hardwareimplement the specified machine instruction. The
number of words of this virtual microprogrammed
memory is dictated by the complexity of the particular instruction. For the ADD instruction, for
instance, the equivalent of eight such microinstructions are necessary; and since two main-memory references must be made (one to fetch the next
machine instruction and the other to fetch the oper-
and), the maximum cycle time of the virtual microprogrammed memory must be 250 nanoseconds.
In the MYRA picoprogramming element, this 250
nanosecond speed of operation is realized by generating sequential control pulses with pulse-widths of
250 nanoseconds. Hence, the total access time of the
MYRA element must be 2 microseconds.
This paper will not concern itself with the computer
architecture, which is comparable to contemporary
computer organizations, but rather with the design
aspects of its picoprogrammed control unit. The discussions within this paper will also point out design
shortcomings of the MYRA concept and how novel
techniques are employed to ameliorate inherent speed
limitations of the picoprogramming MYRA element.
Computer control requirements
The computer has the general salient features shown
in block diagram form in Figure 1. The hardware implementation of the instructions, specified by the
program residing in the ferrite core memory, is accomplished by the internal logic control provided by
the MYRA picoprogrammed control unit. Transfer
control pulses within the CPU or the Direct Memory
Access (DMA) unit with core and I/O are produced
by specially flow-charted instruction modules.
In synchronous wired-control logic computers,
these sequential transfer-control pulses are generated
by the wired logic at a rate specified by the repetition
frequency of a master clock. In microprogrammed
logic, these sequential control pulses are generated
by successive microinstructions contained in consecutive words in an internal fast control memory.
Appropriate decoding of the contents of these sequential words produces the necessary control pulses
to implement the operations specified by the microinstructions. Since picoprogramming is a step beyond
microprogramming, in that the generated sequential
control pulses are alreadY decoded as they are produced by the MYRA picoprogramming module,
611
612 Fall Joint Computer Conference, 1967
I/O
CHANNEL
MEMORY DATA
CHANNEL
FERRITE
CORE
MEMORY
CENTRAL
PROCESSOR
UNIT
(CPU)
MYRA
PICOPROGRAMMED
CONTROL UNIT
DMA
lJt.J IT
DI =DEVICE INTERFACE
CNC= CHANNEL CONTROLLER
Figure I - Picoprogrammed computer configuration
charting of machine instructions in terms of microprogrammed flow charts is quite useful to formulate
the control pulse-timing requirements to implement
the respective machine instructions.
To demonstrate the direct correspondence of microprogrammed control to picoprogrammed control, the
ADD instruction's microinstruction flow-charting
is chosen as an example. Figure 2 indicates the necessary operations that must be performed in a sequential
fashion to implement this instruction. The control
levels required to effect execution of the specified
microinstructions are shown in Figure 3. They are
associated with Place Levels (PL), Accept Levels
(AL) and Transfer Levels (TL) of registers and circuits in the CPU, shown in Figure 4.
There are two types of control levels generated by
the instruction modules: unbuffered levels (e.g.,
BTL), and derived levels suffixed with the letter "D"
(e.g., UPLD). An unbuffered control level is wired
directly from the output of the instruction modules to
the corresponding control point of the Central Processor. A derived control level is produced by a logic
decision generator circuit. For example, the logic
expression of the output of the UR Place Level (UPL)
logic generator is:
(UPL) + [(COND 1) . (ADRD)]
+ [(COND2) . (UPLD)]
This derived UPL control level is produced .unconditionally with UPL, conditionally with derived control level ADRD as specified by the logic requirements of the 2nd microinstruction (COND1), or
conditionally with derived control level UPLD as
specified by the logic requirements of the 4th microinstruction (COND2). Since the hrO derived MYRA
signals, ADRD and UPLD, are mutually exclusive,
false generation of the derived UPL level is avoided.
Picoprogramming implementation of
microinstructions
Selection of the appropriate instruction module is
accomplished by decoding the contents of the instruction register (lR). The select-set condition of the
MYRA element is an AND function of the OP-code,
Modular Computer Design with Picoprogrammed Control
613
I
SELEr:T MfRA RESET
(t.«:·MB·ADD)
SELECT MYRA SET
(lli·MC·AOQ·Nil
I
1
1ST MICROINSTRUCTION
5TH MICROINSTRUCTION
1
I
I
$
~
~
FETCH
NEXT
I NSTRCT.
ABSOLUTE
ADDRESS
RELATIVE
ADDRESS
INOIR. OR
INDEX
ADDRESS
A-uR
PR-TR;I-UR
(if- 2' S Ca.tPLl
R/R
I
1
I
I
INTERROGATE
INTERRUPT
(~
2-WORD
INSTRUCTION
(ADC)=A-+ PR-DR
TR=PR-DR
I
C
J
I
FETCH
OPERAND
I
RlR
DR-OU-IR
J
I
MA-~
I
(MA - MODIFIED
ADDRESS)
6TH MICROI NSTRUCTIOO
I
I
L
I
I
~
UR=MA-OR
I
j
PR-PAC·M
J
I
7TH MICROINSTRUCTION
I
1
~
ACR-UR
I
I
I
2ND MICROINSTRUCTION
$
I
I
I
I
(y}-TR
3RDMICRO-
INSTR~CTION
I
AR-PR
I
I
~
OR-TR
DR-MA-UR
8TH MICROINSTRUCTION
I
I
4TH MICROINSTRUCTION
¢
I
I
ADC:[(Y}+ACR]-ACR
-~-
INDEXING WITH
OR· SPECIFIED
NO INDEXING
AOC=OR+MIEY-AR
URzMA=Y-AR
I
L
WITH OR
I
I
(]U- DR
( ILI=NEXT
INST RUCTION)
I
I
II
I
PR+1-AR
I
I
SENSE
OVERFLOW AND
CARRY-OUT
I
I
I
NEXT
INSTRUCTION
I
Figure 2-Microinstruction flow-charting of the ADD instruction
the memory not busy (MB) signal ana the MYRA control (MC) status. For the ADD inst!!!£!ion:
SELECT MYRA SET = (MC)·(MB)·(ADD) (Nl)
where N I indicates that indirect addressing or indexing with respect to memory locations 0, or 1 is
not specified. If such address modification is specified,
it is implemented with picoprogramming control produced by the indirect addressing and indexing modules
respectively before selecting the ADD instruction
module.
When the Select-MYRA-Set condition becomes
true, the MYRA driver of the ADD instruction
module is turned on, and with the aid of the sustain
set (SS) winding (Figure 5) switches the first 4 areas
of the MYRA disk. Each area looped with a control
winding will induce in the winding a 250 nanosecond
pulse. Winding arrangements corresponding to control-level requirements to perform the first four
microinstructions associated with the implementation
of the ADD instruction are obtained directly from the
. pulse timing diagrams of Figure 3. Thus, the UTL control winding loops only the third area, while the BTL
control winding loops areas 2, 3 and 4 of the.MYRA
disk.
The first four control levels of Figure 3 are necessary for the proper operation of the MYRA control
circuitry and are common to all MYRA modules. All
of the control pulses produced during the setting of
the MYRA element are common to most of the
memory-referenced machine instructions. This is
evident from the fact that the first four microinstructions are performing address modification to evaluate
the effective operand address (Y), while waiting for
the memory to fetch the next machine instruction.
The last four microinstructions necessary to implement the AD 0 instruction are executed under control of serial control logic generated by the ADD
instruction module during resetting of its MYRA element. Resetting the MYRA disk is initiated when the
reset condition becomes true:
614
Fall Joint Computer Conference, 1967
~SET~
o
SS
I
I 2 340 I 234
I
1
I
BTL
QPL
UTL
UPLD
ADPLD
MAL
DTL
IIRL
ITL
PUD
APL
UAL
MTL
MDTL
TAL
PTL
ADPL
AAL
LCL
OVCL
I
2
r-___ 3
MeR
R/R
ADRD
--
I
SR
MCS
DUD
TTL
rTCL
~RESET~
4
11
5
I
I
H
6
I
7
8
I
I
I
---
I
rl
H
I
I
I
I
I
I
I
I
I
9
10
II
12
13
14
15
16
17
n
18
19
I
J
I
I
I
I
I
11
20
21
I
I
I
I
H
22
23
24
25
I
I
I
I
I
I
I
I
I
26
27
28
29
0
0.5
1.0
0.25 0.75
o 05 1.0 0.25 0.75
TIME- jJ.SECS
Figure 3 - Picoprogrammed control logic to implement the ADD
instruction's microinstructions
Modular Computer Design with Picoprogrammed Control
INSTRUCTION
(I R)
LOGIC a MYRA
CONTROL
DR
QR
ACCUMULATOR
(ACR)
FERRITE
CORE
MEMORY
615
10, 20, 21, 26, 27, 28 and 29 of Figure 3 are the only
unique pulses associated with the ADD instruction.
The beneficial aspects of the small ratio of unique
windings to common windings, approximately 1/10,
result from the fact that mass prefabrication of
classes of instruction modules is possible. To these
prefabricated modules, the small portion of unique
windings needed to fabricate the required instruction
module can be added with a comparatively small time
and effort. Thus, modular expandability of the
machine's instruction-repertoire by the addition of a
new instruction module, or modular alterability by
substitution of an existing instruction module with a
new one is readily realizable.
UR
ADDER
(ADC)
TR
PROGRAM
COUNTER
(PR)
PR ADVANCE
(PAC)
BUS TRANSFER
(BTC)
MEMORY
ADDRESS
(MR)
Figure 4 - Partial CPU configuration
SELECT MYRA RESET = (MC)·(MB)·(ADD)
The sustain reset (SR) winding allows switching of the
disk up to the fourth area, thus returning the disk to
its unselected state.
During resetting of the disk, the appropriate winding
distribution produces the desirable· control levels as
dictated by the chart of Figure 3. The majority of these
pulses are common to most of the memory-referenced
instructions, since they represent housekeeping
operations. These operations include advancing the
program counter (PR) and loading the instruction
register (lR) with the next instruction. Control levels
Figure 5 - MYRA picoprogramming element arrangement
I nstruction module implementation
The switching operation of the instruction module is
as follows. As soon as the "Select-MYRA-Set" level
becomes true, the driver of the selected instruction
disk is turned on. With the output transistor-switch
in saturation, a step function voltage is applied across
the MYRA drive winding causing a current ramp to
flow through it. Thus, a propagating flux-change wave
will result that will traverse the disk in an outward
radial direction with a uniform velocity. As this wave
traverses consecutive areas that have been looped
selectively with picoprogramming control windings,
the induced emf will produce the necessary serial
picoprogramming control logic. The switching parameters of the disk have been chosen such that the produced MYRA winding pulses have voltage amplitudes
compatible with the Sylvania SUHL I.C. logic which
is used to implement the computer. This voltage level
compatibility is significant because the output of the
MYRA winding, due to its very low internal impedance (~ IOn), can be thought of as a virtual high fanout
logic gate with a fanout factor in excess of 50. High
fanout is a requirement in register control levels
where all 16 bits of registers in the arithmetic unit
are to be loaded with new information.
616 Fall Joint Computer Conference. 1967
When the flux-change wave has traversed the fourth
area, the zero state of the SS level causes the set
driver to turn off. Thus,.the current ramp that flows
through the set winding drops rapidly to zero. The
MYRA control set (MCS) winding that loops the
fourth area of the MYRA disk has conditioned the
MYRA selection unit to receive the succeeding reset
signal to switch (reset) the selected MYRA disk to its
original state.
Logic control levels are produced both during
setting and resetting of the disk as dictated by the
timing chart to perform the microinstruction operations. An DRing gate arrangement is used to chain
MYRA windings associated with a particular control
signal. This DRing arrangement, a 2-input diode DRgate per MYRA control level, makes possible the
utilization of control pulses that are produced during
either setting or resetting of the disk.
The switching constant (Sw) of the ferrite MYRA
disk material will yield a good resolution at speeds
below 500 nanoseconds per area. In this serial logic
arrangement, resolution is referred to as the ("one" /
"zero") ratio in the worst-case condition where a
logical "one" is both preceded and followed by logical
"zeros." At the speed requirements of this computer
(250 nanoseconds per area), the resulting resolution
is so poor that the produced ("one"/"zero") ratio of
2 cannot be used for picoprogramming control purposes. The degradation in resolution at high switching
speeds results from flux-change-wave broadening that
causes several adjacent areas of ferrite material in
the radial direction to switch simultaneously. As the
rate of the magnetic-field build-up increases with an
increase in current ramp slope, impUlse switching conditions prevail and the ferrite material in the eighth
area of the disk starts switching, while ferrite material
in the first area has not yet been completely switched
to its reset state. It is obvious then that such fluxchange-wave broadening can be prevented if an in·
hibiting arrangement of areas beyond the one associated with the flux-change-wave front is devised.
The biasing winding arrangement of Figure 6
accomplishes the desirable inhibiting function. Under
the assumption that the internal impedance of the
current driver is small, the rate of change of flux with
time is constant. Therefore, the current through the
biasing winding for a given· area (radial depth) is a
function of the biasing resistor (R B ), the amplitude of
the step driving voltage (V 0), and the number of turns
(No) of the drive winding. As a function of the radial
position of the flux-change-wave, in terms of areas in
the radial direction (n), the biasing current is proportional to n or
I - n Vo . _
B = RB No' n - 1,2, ... 8.
BIASING
WINOO«; ARRANGEMENT
Figure 6-Cut-view ofa biased MYRA-disk radius
Since the driving current ramp has a similar linear
variation with n, knowledge of the switching parameters of the ferrite material (Sw and He) will' allow
determination of the value of RB for a given V 0 and
No to produce optimum serial resolution at the
specified speed of operation of the MYRA element.
The effect of the biasing winding on the resolution
of the MYRA serial control logic is depicted by the
oscillograms of Figure 7. The picoprogramming code
10101010 was chosen as the worst-case resolution
condition. From the oscillograms it can be seen that
an effective discrimination range improvement in
resolution of about twenty to one is obtained.
The outputs of the three picoprogrammed windings
to effect the micro-operation (QR ~ TR) specified
by the 3rd microinstruction of the ADD instruction
are shown on the oscillograms of Figure 8. The fourth
pulse which is necessary to reset TR and gate the new
information into TR is not directly derived by MYRA
windings but is logically produced from the leading
edge of the TAL pulse.
Instruction modules are packaged as single units on
conventional double-sided PC cards. Two types of
such cards are employed in the control unit of the
computer: the single-disk instruction module (Figure
9) which contains the MYRA disk and two drivers
(a set driver and a reset driver), and the double-disk
instruction module (Figure 10) which contains two
MYRA disks and three drivers (two separate set
drivers and a common reset driver). From economic
considerations, double-disk modules are preferable
to the single-disk, because a saving of one driver and
one PC card per two instructions is realized. From the
Modular Computer Design with Picoprogrammed Control
617
(a) DRIVE WINDING
CURRENT RAMP
13 AMP. TURNS / DIV.
(b) -'OIOIOIO·-PICOPROGRAMMING
MYRA WINDING
(UNBIASED)
I V/ DIV.
(el ·IOIOIOIO"-PICOPROGRAMMING
MYRA WINDING
(BIASED)
I V / DIV.
(a).(b).(e) i 0.5 MICRO SEC. 10 IV.
(d) "0101010· MYRA WINDING
(.) "0101010· SUHL
2V/0IV.
( d 1i 0.2 MICRO SEC.I DIV.
Figure 7 - Effect of biasing winding on serial pulse resolution
I.e. OUTPUT
618
modularity and diagnostic point of view, however,
single-disk cards that are associated with single instructions only are preferable. This is obvious from
the fact that an inoperative instruction can be immediately traced to the respective module and diagnosed instantly, with no regard to ambiguities introduced from possible interaction of the adjacent
instruction sharing the same module. In the computer,
an equal number of single- and double-disk .modules
were nCOlPci
QPL
BTL
TAL
TCP
\
n
\
SCALE: VERTICAL; 5V/DIVISION
HORIZONTAL ;0.1 J.lSEC I DIVISION
Figure
8 - Sample
microinstruction picoprogrammed
requirements
control
Figure 10- Double MYRA disk instruction module
Figure 9 - Single MYRA disk instruction module
Designfeatures ofpicoprogramming
The modular expandability in terms of instruction
repertoire of the picoprogrammed computer has already been discussed. The post-design tailorability
of the machine by introducing or modifying features
will now be considered.
It has been indicated that the computer has three
index registers. One is a hardware register (QR) residing in the arithmetic section and the other two are
the 1st and 2nd word locations of the ferrite core
memory. When indexing with respect to a core index
register is specified by the machine instruction, a
special indexing MYRA module is employed. This
module is accessed before the main instruction module
is selected and address modification with the specified
core index register is performed. This type of indexing
is time-consuming in that it requires 1.4 microseconds
more time than indexing with the QR which is in the
arithmetic unit. With the present design, a future
replacement of the core index registers with hardware
is possible by the incorporation of an I.C. card that
contains two 16-bit registers in the Central Processor
and the elimination of the indexing MYRA module.
The incorporation in the computer of the optional
Direct ·Memory Access (D MA) feature is also done
by the addition of the DMA control unit and an I.C.
card per required controller. This DMA control unit
consists of three MYRA modules - one to initialize
the selected DMA controller (load the block length,
and the st~rting address) and one each to transfer
data between the I/O device and the memory.
Cyclic instructions, like the hardware multiply and
divide, are incorporated by the addition of four
MYRA modules. The first initializes the instruction.
The second partially implements the instruction by
Modular Computer Design with Picoprogrammed Control
performing seven successive test-add-shift operations. The third completes the implementation of the
instruction by performing the last eight successive
test-add-shift operations required to mUltiply two 16bit numbers. The fourth finalizes the instruction.
CONCLUSIONS
The MYRA picoprogramming control technique was
applied successfully in the design of a full-scale
real-time control computer. Instruction modularity
and post-design tailorability afforded the design by
the picoprogramming concept were demonstrated.
The former provides instruction-repertoire expansion
or alteration in modular form, while the latter facilitates modular incorporation of machine features.
Operation of the picoprogramming MYRA element
at speeds beyond its inherent acceptable resolution
range was made possible with the incorporation of the
unique biasing winding technique. This technique
makes possible the application of the MYRA element
in other serial logic designs as well.
The speed of operation (1 JLsec. cycle-time) and the
complexity of the computer (15 memory-referenced
instructions, and 95 augmented OP-code non-memory-referenced instructions) made it an excellent
worst-case-design vehicle. At the same time, it demonstrated that full advantage of the inherent useful
properties of the MYRA picoprogramming concept
(high fan-out, instruction modularity, diagnosability,
619
etc.) is achieved with less complex CPU designs. In
particular, the technique could prove very beneficial
in multiprocessor design approaches where each
satellite processor is relatively simple and is requested to handle only specialized types of data processing as part of a very powerful master processing
unit that assigns specialized processing tasks to these
satellite. picoprogrammed processors.
ACKNOWLEDGMENTS
The a~thor wishes to thank E. L. Scheuerman and
J. E. Fulenwider for their helpful suggestions during
the preparation of this' manuscript. The efforts of
J: R. Holden, who conceived and developed the
biasing winding technique, are especially acknowledged. The ferrite processing contributions of Dr.
M. E. Dempsey's materials group, and W. A. Reimer's
efforts in packaging the MYRA control modules
are greatly. appreciated.
REFERENCES
B E BRILEY
Picoprogramming: a new approach to internal computer
control
Fall 1965 Joint Computer Conference Vol 27 Part I Spartan
Books Inc Washington 0 C 1965
2 B E BRILEY
MYRA: A new memory element and system
Proc 1965 Intermag Conference
Intercommunication of processors and memory*
by MEL PIRTLE
University of California
Berkeley, California
INTRODUCTION
Many computer systems include one or more high
transfer rate secondary storage devices in addition
to numerous input-output (I/O) devices. When the
processors which manage these devices (frequently
referred to as I/O controllers or channels), together
with the central processing unit (CPU), communicate
almost exclusively with a single primary memory, as in
the configuration illustrated in Figure 1, the problem
of providing these processors with adequate data
transfer capability becomes formidable. 1 Ideally,
each processor should be able to transfer a datum to
or from primary memory at its convenience without
regard to the ability of the memory to accept or supply
the datum at that particular moment, or the ability of
the processor-to-memory transfer path (memory bus)
to effect the transfer. Unfortunately, economic and
technical considerations dictate that memory systems
of the capability implied must be relegated to the role
of standards with which more practical systems may
be compared. With practical memory systems, the
rate at which data can be transferred between processors and primary memory is limited by the transfer
capabilities, or bandwidths, of the memory itself and
of the memory busses over which the transfers are
made. Furthermore, since the memory system is
shared by several processors, care must be taken to
keep performance from being degraded excessively
by interference caused by simultaneous attempts on
the part of several processors to utilize a facility,
such as a memory bus, which is capable of handling
only a single data transfer at any given moment.
To provide the required memory bandwidth, many
memory systems currently in use are partitioned into
several modules which can operate concurrently.2 In
addition, some systems employ memories having a
physical word length which is a multiple of the
*The work reported in this paper was supported by the Advanced
Research Projects Agency, Department of Defense, under Contract
SD-185.
logical, or CPU, word length. 3 To make this memory
bandwidth available to the processors, these systems
frequently employ multiple memory busses, as shown
in Figure 1. 4 To make a memory reference in one of
these multi-bus configurations, a processor first
makes a request for the use of its memory bus; and,
when this request is granted, uses this bus to transmit
its memory reference request to the appropriate
memory module. If either of these two requests are
rejected, the processor repeats the procedure beginning with the request for the memory bus. To resolve conflicting requests for either a memory bus
or a module, some type of priority mechanism is
employed. Priorities typically are assigned to processors and to memory busses;5 the former are used to
resolve conflicting requests for a memory bus and
the latter to resolve conflicting requests for a memory
module.
81
82
Figure 1 - General processor-memory configuration
Although these memory systems are generally able
to satisfy the needs of the computer systems in which
they exist, primary memory systems of even greater
capabilities are required to meet the demands of newer
computer systems which have faster CPU's, secondary storage devices with higher transfer rates, and a
621
622
Fall Joint Computer Conference, 1967
high degree of concurrency of processor operation. 6 It
is the purpose of this paper to discuss certain aspects
of the problem of effective processor-memory intercommunication. A priority mechanism is suggested in
which priorities are assigned to requests, on the basis
of immediate requirements and conditions, rather than
to processors. In addition, some memory system configurations and I/O processor buffering schemes are
proposed which, together with the priority assignment mechanism, provide for high CPU performance
and memory transfer utilization in an environment
of simultaneous computation and high transfer rate
I/O activity. Results of simulations of several configurations and priority assignment algorithms are
presented in support of these suggestions.
General
To facilitate the discussions to follow, let us consider in detail the specific processor-memory configuration shown in Figure 1. This configuration includes a primary memory which is partitioned into
four identical, independent modules having physical
word lengths equal to the logical word length of the
CPU. It also includes two memory busses labeled B 1
and B2, the CPU having exclusive use of Bland the
several I/O processors sharing the I/O bus, B2. For
these discussions, it is postulated that the transfer
of a single word between a processor and memory
requires the exclusive use of one memory bus and
one memory module for a complete memory cycle (the
time required to read and regenerate, or store, a word),
and that the memory cycles are contiguous. Thus the
memory system is synchronized: it accepts requests
for the I/O bus and requests for memory references at
regular intervals.
This memory system is capable of supporting simultaneous references to two of the four modules, one
over each of the two busses. Thus, for example, the
CPU can make a sequence of references to module
MOusing bus Blat the same time that the drum processor is making a sequence of references to module
M 1 using bus B2. Furthermore, if both of these
sequences of references are made at a rate of 1IT,
where T is the time required for one memory cycle,
then 100% of the bus bandwidth available to each
of the processors is utilized along with 50% of the
memory bandwidth. However, simultaneous attempts
to reference anyone of the modules will result in the
acceptance of only one of the requests, and simultaneous attempts by I/O processors to use the single
I/O bus will result in the acceptance of only one of
these requests. Since requests are sampled only once
each memory cycle, a processor having a request rejected must wait for one memory cycle before having
the req,!est reconsidered; furthermore, the memory
bus used for the rejected request cannot be used for
any other request during the one memory cycle period.
The effective resolution of these potential request
conflicts will be given considerable attention below,
but before considering this problem in detail, let us
question the general capabilities of the system under
discussion. The system includes a CPU, a drum processor, a disc processor, a cathode ray tube (CRT)
display processor, and a mUltiplexing processor which
manages low demand I/O devices. Frequently,
several of these processors will be active simultaneously. Some pertinent questions then are:
1. Does the memory have sufficient bandwidth to
accommodate the transfers requested by the
several processors?
2. Does each of the busses have sufficient bandwidth to accommodate the transfers requested
by the processors attached to it?
3. Given that the answers to questions I and 2 are
in the affirmative, can these bandwidths be
effectively utilized?
The first two questions are purely theoretical, and
easily answered: the first by comparing the memory
bandwidth nIT, where n is the number of memory
modules, with the memory request rate; and the
second by a similar comparison between memory bus
bandwidths and the memory request rates of attached
processors. The third question is not answered so
easily, however, since it involves not average request
rates, but instantaneous request rates and the distribution of these requests over the busses and
modules. For example, consider the configuration
shown in Figure 1 and a situation in which the CPU
and the drum processor are both active, the CPU
making requests at a rate of I IT and the drum processor at one-half this rate. Now, if the CPU and
drum processor are referencing exclusively MO and
M 1 respectively, there are no request conflicts and
the required portion of the available bandwidths
are used effectively. Also, if the CPU is referencing
M I instead of MO on occasion, there is still no serious
difficulty if the CPU refrains from making two consecutive requests to M 1, since the drum processor
can conveniently defer a reference for one memory
cycle; although in this case, additional B2 bandwidth
is consumed by rejected requests made by the drum
processor. However, if both the CPU and the drum
processor attempt to reference MO exclusively, then
either the drum processor is obliged to forgo the
attempted data transfer or the CPU is forced to
operate at one-half capacity. In this latter case only
one-fourth of the memory bandwidth can be used although three-eighths of the memory bandwidth and
Intercommunication of Processors and Memory
three-fourths of the total memory bus bandwidth are
requested.
The question of memory bus utilization is similar to
memory utilization except that in this case the only
parameter to be considered is time since there is no
opportunity for parallel activity on a given bus. The
memory bus bandwidth can be easily utilized if each
processor handling a synchronous device, such as a
drum, is designed so that whenever it is transferring
at a rate of R words per second it can make each word
transfer at any point within the I/R second interval
between transfers. However, if each transfer must be
made within some small portion of the I/R second
interval, as is frequently the case, then it is much
more difficult to make full use of the bandwidth.
To see that this is the case, consider a configuration
in which three processors sharing a single memory
bus must each make a transfer within a two memory
cycle portion of their respective transfer intervals
(the interval between transfers). Since each of these
processors can defer a reference for at most one memory cycle, they cannot operate simultaneously,
independent of their (non-zero) transfer rates, unless
the operation of at least one of these processors is
appropriately synchronized relative to one of the
others. For only with synchronization can it be insured
that the processors will not require three transfers in
two memory cycles.
I t is apparent that high utilization of memory and
bus bandwidths are facilitated by transfers which are
evenly distributed over time and over the several
memory modules. The ease with which a given processor can provide an even distribution of memory
references depends 'strongly on the manner in which
the addresses are distributed among the memory
modules and on the function performed by the processor. If the addresses of a memory consisting of n
modules of m words each are distributed so that
addresses 0 through m-I are in module M(O) and
addresses m through 2m-1 in M( I) etc., then a relatively even distribution of references over the
modules can be effected by assigning to each processor a portion of the modules, and hence a memory
bandwidth, commensurate with its transfer rate. However, this address assignment has the disadvantages
that
I. The size of the memory assigned to a processor
is directly proportional to its transfer rate, even
though this relationship is frequently not con- .
sistent with other considerations.
2. In cases in which other considerations dictate
the assignment of a single module to several high
reference rate processors, the performance of
one or more of these processors will be severely
degraded, and
623
3. the memory bandwidth available to a sequential
processor (a processor which transfers to sequential memory addresses) is limited to that of
a single module.
These disadvantages are replaced by others of much
less severity when the addresses are distributed over
an n module memory so that address 0 is in M(O),
address 1 is in M( 1) and, in general, address X is
in M(i) where i == X modulo n. As will be illustrated
in subsequent sections of this paper, this address
distribution together with appropriate memory bus
configurations allows a given processor to be assigned
any desired portion of the total memory bandwidth
without regard to the size or location of the portion
of memory assigned. This distribution, commonly
referred to as interleaved addresses, does have two
disadvantages: first, the operational failure of any
of the modules nearly always renders the entire memory inoperative; and second, the simultaneous operation of several processors will almost always cause
some degradation of processor performance. The
former disadvantage is mitigated by employing reliable
memory systems, * and results presented in subsequent sections show that the magnilude of the latter
disadvantage can frequently be redl'';ed to an acceptable level. All memories considere' , the remainder
of this paper will have interleaved auJresses.
The function performed by a . 1icular processor
also influences the economic feasibility of distributing
its references over time and over the memory modules. For example, a drum proce"sor usually references sequential addresses at regular intervals, thereby distributing its references evenly over the memory
modules and over time. A CPU, however, may frequently make several successive references to a
single module or to a small number of modules, and it
makes memory references at frequent, irregular
intervals. More generally, there are four factors to
be considered. They are:
I. The frequency of memory references
2. The ability of the processor to anticipate the
need for a memory reference
3. The cost of deferring a reference
4. The natural distribution of references over
memory modules
The importance of these factors will become evident
in the later sections. At this point, it is sufficient to
point out that processors making low speed, synchronous, sequential transfers are generally ideal with
respect to the desired values of these factors and
therefore to effective bandwidth utilization. The only
difficulty with this type of processor is that a rela*Ouring the past 18 months of operation, Project Genie's modified
SOS 930 has experienced no memory failures.
624
Faii joint Computer Conference, i 967
tively high cost recovery procedure must be invoked
whenever a transfer is deferred so long that the synchronism of the transfer is destroyed. On the other
hand, processors making very high rate synchronous
transfers, with their short transfer intervals, and
processors making high frequency references to quasirandom addresses, such as CPU's, are far from ideal
with respect to these factors.
-From the above discussion, it should be evident that
processors which distribute their references evenly
over the memory modules and which have transfer
intervals of several memory cycles provide a potential
for high utilization of the available memory and memory bus bandwidths. However, this potential can be
realized only when the references are made at optimum times. To insure this timing of references would
require the use of some extremely clever logic whic.h
would consider not only the requests presented at a
given moment, but also requests to be presented within the next several memory cycles. A fairly simple
alternative to this anticipatory logic which produces
near-optimum results for systems of reasonable complexity is described in the following section.
Description of request priority assignment
Given a computer system such as the one shown in
Figure 1, it is common practice to use priorities
assigned to the various processors and busses to
resolve conflicting requests for a memory module or a
memory bus. 5 These priorities are fixed and generally
assigned primarily on the basis of two considerations:
I. The lower the priority assigned to a bus or processor, the lower the amount of interference to
other processor-memory intercommunications
caused by requests associated with this bus or
processor.
2. The cost associated with the disruption of a
synchronous data transfer, such as from a drum
processor to memory, is substantial.
Consequently, the I/O bus (or busses) are generally
assigned a priority higher than that of the CPU bus;
and the processors handling high transfer rate, synchronous devices are given priorities higher than
those handling lower transfer rate or asynchronous
transfers. More precisely, the priority assignment is
generally made by assigning to each processor the
lowest priority which will insure that, under worst
conditions, no high cost disruption of data flow or
loss of data will occur.
The following examples will illustrate the inadequacy of this type of priority assignment. First, consider a case in which an I/O processor handling a
medium-rate-transfer attempts to reference a particular memory module simultaneously with the CPU.
Usually, the I/O processor can step aside and allow
the CPU to make its reference without any difficulty
since it can simply repeat the memory request at the
nextI memory cycle. However, if the fixed priority
assignment described above were used, the I/O processor would usurp the memory module and thereby
degrade the performance of the CPU, since the I/O
processor would have been assigned a priority higher
than that of the CPU to guard against the infrequent
instances in which it cannot further defer a memory
reference. Second, consider the case of the CRT display processor which refreshes the CRT image. Generally, this processor can defer a particular memory
reference for an appreciable time without unduly
degrading the performance of the display. However,
this processor is commonly connected to the same
bus as is the drum processor; and this bus is required
by the presence of the drum processor to have a high
priority. Therefore, the requests of the display processor outrank those of the CPU even though the
display processor can conveniently defer its memory
reference. The consequence of these inequities is
either that the utilization of the memory and memory bus bandwidths is limited, or the performance of
one or more processors is severely degraded.
These examples and the discussion above suggest
that priorities should be assigned to individual requests rather than to processors and busses, and that
each processor should be given a selection of priorities
for assignment to a given request. With a priority
mechanism having this dynamic priority assignment
capability, a processor can choose for each request
a priority which is commensurate with I) the cost to
be incurred by the rejection of the request at that
particular moment, 2) the probability that a request
with a given priority will be rejected at that particular moment, and 3) the general desirability of
making low priority, minimal interference requests.
The exact costs and probabilities are, of course,
difficult to ascertain; however, in most instances,
they can be adequately approximated. Moreover, in
every instance they can be assumed such that the
resulting priority assignments are at least as good
as the fixed assignments to processors currently used.
Numerous examples of improved system performance realized by the use of dynamic priority assignment are given in the next section. At this point, the
following two examples should illustrate the advantages and some of the ramifications of this type of
priority assignment. First, consider the priorities
assigned to requests by an I/O processor handling
a synchronous transfer. If it is assumed that the
highest priority available to this processor is higher
than that available to any other processor, then the
Intercommunication of Processors and Memory
probability of having a request of this highest priority
accepted is one. Therefore, this processor will commence a sequence of requests of relatively low priority
at the beginning of each of its transfer intervals and
continue this sequence until a request is accepted
or until only one memory cycle remains in its transfer interval. Only when the entire sequence of low
priority requests is rejected must the processor resort
to making a high priority request. Second, consider
the display processor mentioned above. The cost of
deferring one of its references for a few memory
cycles past the end of its transfer interval is usually
not very large. Therefore, this processor might commence a transfer interval with a sequence of requests
of very low priority, change to a medium priority
near the end of its transfer interval, and change to
a relatively high priority sometime following its transfer interval. Thus, if the frequency of requests made
by this processor is not too high, the probability of its
interfering with requests of other processors is extremely low.
Processor-memory configurations
Results of simulations of several processor-memory
configurations and I/O processor buffering mechanisms are presented in this section. The characteristics of the memory modules and the basic memory
bussing mechanism are the same for all situations and
are similar to those of the system illustrated in Figure 1. More precisely, the memory modules are all
identical, having an access time (the time required
to read a word from memory and make it available to a
processor) of .8 usec and a cycle time of 1.75 usec.
As before, the several memory modules are synchronized, and a processor making a memory reference is logically connected to the memory module via
its memory bus during the entire 1.75 usec memory
cycle. The memory addresses are interleaved over
all of the memory modules in each of the configurations considered.
The CPU simulated is the SDS 930 as modified by
Project Genie. 7 This is a word-oriented processor
having a single instruction per word and a single
operand address per instruction. It has one index
register and provides for indefinite levels of indirect
addressing with pre-indexing at each level. The instruction repertoire includes one conditional jump
instruction, several conditional skip instructions,
numerous central register manipulation instructions
(not requiring a memory reference for an operand),
some memory-to-memory instructions (e.g., increment
contents of the specified memory location) which
require two consecutive references to the same mem-
625
ory location and a full complement of arithmetic
and logic instructions.
Most instructions require two memory cycles for
execution: Y2 cycle for indexing, Y2 cycle for fetching the operand, and one cycle for processing. The
operand is regenerated in memory during the first
Y2 cycle of processing and the next instruction is
fetched during the last Y2 cycle. The instruction is
regenerated during the indexing Y2 cycle. A pertinent
peculiarity of this processor is that all store instructions require three cycles; no memory reference is
made during the middle cycle.
lC1.IrI.ber of
Momory
~
16
Probability
of no memory
reference at
next cycle
Probability
of reter_
Probability
Probability
of'rrterence
ot reference
or
ot reference
to lame
module
to
to aame
module
at next
f1~ cyclu
ence to sUie
raodule at
Mxt cycle
ProbabUity
reference
I . .e
module
at next
at next
two cyclu
three cycles
four cycles
.012
.091
.454
.166
.054
·091
.230
.040
.010
.091
.117
.008
.001
.000
.002
.000
.000
·091
Probability
.004
.001
Table 1- Probabilities of the CPU referencing the same memory
module at consecutive memory cycles (following a reference to a
particular module)
As might be expected, simulations of this CPU
show that the distribution of memory references over
the memory modules is uniform and quasi-random.
Some probabilities of multiple consecutive references
to a module are given in Table I. Two observations
of these figures, which are averages over all of the
modules in each configuration simulated, warrant
comment: first, the approximately 9% of the cycles
during which the CPU makes no memory reference
result primarily from the execution of store instructions; second, the probability of two consecutive
references to a module is slightly higher than might be
expected. This higher value, particularly noticeable
in the case of 16 modules, results primarily from the
execution of those instructions which made consecutive operand references to the same memory location.
The program used in the simulations was the Berkeley
Time-Sharing System's macro assembler. Although
several other programs including a text editor and a
list processing interpreter were also simulated, the
results obtained from these simulations were almost
identical to those obtained using the assembler and
therefore are not presented.
With this background, consider the configuration
illustrated in Figure 2, which is similar to that in Figure I. As mentioned previously, the two memory
busses Bland B2 provide for simultaneous transfers,
one to the CPU and one to an I/O processor. There
are two types of I/O processors shown: a drum pro-
626
Fall Joint Computer Conference, 1967
cessor which transfers data at an average rate of
word every 8 usec, and four independent CRT display
processors, each of which fetches data at an approximate rate of 1 word every 20 used. More precisely,
display processors 1 through 4 require for 100% performance a word every 20.1, 19.9,20.2, and 19.8 usec
respectively. Furthermore, the storage capability
of these processors is limited in that they cannot
accept a word during the first 10 usec portion of these
periods.
Display processor and drum processor performance
- the ratio of the number of words transferred
in the environment simulated to the number
transferred in an environment free of memory
interference.
Memory bandwidth utilization - the ratio of the
number of memory references made in a given
period to the number of references possible in
that period (i.e., the product of the number of
B1
82
Figure 2 - Four display-processor configuration
Each of the I/O processors has two priorities (high
and low) available for assignment to its requests.
These priorities, which are used to determine access
to both the I/O bus and the memory module, are assigned by each I/O processor in a fixed sequence of N
low priority requests followed by as many high
priority requests as necessary. The value of N chosen
for each processor is determined by the length of the
processors transfer interval, the cost of failing to
make a memory reference within this interval, and the
probability of having one of its high priority requests
accepted. This probability is dependent, in turn, on
the relative priorities which are shown in Figure 3.
Because the cost of a failure by the drum processor
to make a memory reference within its transfer interval is substantial, the value of N for this processor is conservatively chosen so that its' performance is assured to be 1.00.
Some results of simulations of this configuration
are given in Table II, where the tabulated parameters
have the following definitions:
CPU performance - the ratio of instruction execution rate in the environment simulated to the rate
in an environment free of memory interference.
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Display 3
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CPU
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Display 1
Display 2
Display 3
Display 4
High
High
High
High
Low
Low
Low
Low
Memory Module Priority
Figure 3 - Relative priority of requests
memory modules and the number of memory
cycles in the period).
These results show the improved CPU performance and memory bandwidth utilization obtainable
using dynamic priority assignment with a very simple
priority assignment algorithm. More specifically,
they show that in the configuration including only
two processors, a CPU and a drum processor, the
use of dynamic priority assignment and the memory
Intercommunication of Processors and Memory
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an increase in processor-memory intercommunication
capability beyond that of the configuration in Figure
2 requires either an increase in the bus bandwidth
available to processors or a means by which more
effective utilization can be made of a given bus bandwidth. Let us first consider methods of increasing the
bus bandwidth available to the I/O processors.
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Table I I - Processor performances and memory bandwidth utilization for the configuration in Figure 2
bandwidth of two memory modules provides better
CPU performance and a much greater memory bandwidth utilization than that provided by twice this
memory bandwidth (four memory modules) and a
fixed priority assignment. Also, the addition of the
four display processors causes little degradation to
CPU performance. In fact, if .96 display processor
performance is acceptable, this addition of display
processors can be made at no loss in CPU performance by. simply making all display processor requests at low priority. This result substantiates a
previous statement regarding the ideality of processors which 1) distribute their memory references
over the modules, 2) can anticipate the need of a
reference, 3) can tolerate an occasional small delay in
making a reference, and 4) require references at a
moderate rate.
The results presented in Table II verify that the
efficiency of a computer system can be significantly
increased by assigning priorities to requests rather
than to processors and by having the processors make
a sequence of requests with appropriate priorities
for each word to be transferred. It should be observed,
however, that in each case considered the aggregate
transfer rate of the I/O processors sharing the I/O bus
is well below the bandwidth of the bus. In fact, the
case in which 73.5% of the memory bandwidth was
used, only approximately 56% of the I/O bus bandwidth was used for data transfers. Most of the remaining 44% was used for low priority requests which
tied up the bus even though they were rejected at the
memory module. Since an excess of bus bandwidth
over transfer rate is obviously necessary' for the
effective operation of the dynamic priority scheme,
Figure 4- Increased memory buss bandwidth provided by two
I/O busses
It is apparent that the maximum bandwidth available to any I/O processor in Figure 2 is limited to l/T
by the bandwidth of the I/O bus. Moreover, since
the bandwidth must be shared by the several I/O
processors, the actual bandwidth available to a"given
processor is considerably less than this limit. As illustrated in Figure 4, providing two I/O busses doubles
the bandwidth available to the I/O processors while
retaining the absolute limit of l/T for anyone processor. To increase this latter limit, two (or more)
busses can be provided a given processor. This can
be done either by providing the processor with two
busses, each of which connects to all of the memory
modules, or by providing one bus which connects to
the even-numbered modules and one which connects
to the odd-numbered modules as shown for I/O
processor 3 in Figure 5. The second alternative requires less logic to implement and, since alternate
busses are used in referencing sequential addresses,
it is as effective for processors which reference
sequential addresses as the first alternative. Therefore this second alternative, which can be extended
in an obvious manner to four busses (provided the
number of modules is an integer multiple of four), will
be discussed exclusively in the remainder of this
paper.
To illustrate the value of increased bus bandwidth to the processors, simulation results for the
configuration shown in Figure 6 are given in Figure 7.
The drum processor, which transfers data at the rates
indicated, has a single buffer register and separate,
628
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..... -_&&&1"'-"-" - - - ....... _ ... _&&_-, . . _-.
...
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91
93
94
Figure 5 - Increased memory buss bandwidth provided by
two busses to a single I/O processor
Drum
Processor
82
83
81
Figure 6 - Drum processor with single buffer registers
identical, request logic for each bus to which it is
attached (in addition to a single buffer associated with
the drum write amplifiers and read amplifiers.) The
request logic begins making low priority requests
when its associated buffer register becomes ready
(full on drum-to-memory transfers and empty on
memory-to-drum transfers). It continues to make low
priority requests until either a request is granted or
only one memory cycle remains in the transfer interval. When the latter situation occurs, a request having
a priority higher than that of CPU requests is made,
thus insuring that the transfer will be made within
the transfer interval. For comparison, several results
are given for request logic which always makes high
priority requests. These results are presented in tabular form together with memory bandwidth utilizations in Table III.
As was anticipated, dynamic priority assignment is
effective only when the data transfer rate of the drum
processor is considerably less than the bus bandwidth
which is available to it. However, the results for the
two memory module configuration with two memory
busses to the drum processor suggest that dynamic
priority assignment is only slightly effective when
there is a two to one ratio of bus bandwidth to transfer rate. This is not generally true; this anomaly is
caused by a tendency for the CPU in this particular
case to get into phase with the drum processor, alternating memory references to each of the two memory
modules. This phenomenon is illustrated in Figure 8
for' a sequence of typical two cycle instructions. As
shown in this figure, when the drum processor makes
only high priority requests (one request every other
cycle on each of its two busses), the execution of
each of the two cycle instructions requires three
cycles, regardless of which module contains the operand. Furthermore, when each high priority request
made by the drum processor is replaced by a low
priority request followed, if necessary, by a high
priority request, then some of these low priority requests will be accepted - thereby causing the associated references to occur one memory cycle earlier,
but not changing the fact that each of the two cycle
instructions requires three cycles for execution. It
should be observed, however, that even in this unfavorable situation, the two-module, two I/O bus configuration with dynamic priority yields a higher CPU
performance and memory bandwidth utilization at
the lower drum processor transfer rates than a fourmodule, two I/O bus configuration with fixed priority.
To improve the processor performance in the situation just described, and to generally increase the effectiveness of a given bus bandwidth, the transfer intervals of I/O processors must be increased. The processor shown in Figure 9, which is similar to the one
described above except that it has one additional buffer register inserted into the path of the data flow to
each bus, demonstrates one method of achieving this
goal. To illustrate the function of this buffer, consider
a drum with a data transfer rate of 1 word every 2
usec. Assume that a memory-to-drum transfer is in
progress and, at a time 'designated to, BRI is full
(with contents f3) and BR2 (with contents ex) is in
the process of being transferred to D, a process which
consumes 100 nsec. Then at to + 100 nsec B R2 is
empty, and a BRI to BR2 transfer is initiated; at to
+ 200 nsec the transfer is completed and BR 1 is
empty. Since the drum receives only every other word
from BR2, f3 is not required by the drum until to +
4000 nsec and 0, the next word to be fetched into
BR 1, is not required until to + 8000 nsec. Therefore,
Intercommunication of Processors and Memory
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.30
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Average time between drum processor initiated memory references
Figure 7 - CPU performance for single buffered drum processor
(for 2 and 4 memory modules and 1,2, and 4 memory busses to the
drum processor)
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o - - Operand
reference -0)
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Figure 8a-Memory reference sequence when drum processor
makes high priority requests only
Table III-CPU performance and memory bandwidth utilization
for single buffered drum processor (Figure 6)
there is a 7.7 usec period in which to fetch a into
BRI. This period is greater than the time required
for four memory cycles; therefore, the processor can
make two or possibly three low priority requests
630 Faii joint Computer Conference, 1967
o
MeJIory cycle
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He request if no dr\lll processor request
DO
operand reference
Figure 8b - Memory reference sequence when drum processor
makes a low-high priority sequence of requests
100
nsec.
BR 1
B2
83
Figure 9 - Drum processor with double buffer registers
before resorting to a high priority request, instead of
the one low priority request possible with the processor having a single buffer register. It should be
apparent that the second buffer register allows the
processor to take advantage of the acceptance of a
low priority request to lengthen its subsequent transfer interval.
CPU performances obtained with a drum processor
having two buffer registers are given in Figure 10 and
tabulated along with memory bandwidth utilizations
in Table IV. The CPU performances presented in
this figure are uniformly higher than those obtained
for I/O processors having single butTer registers. In
fact, two combinations of memory and bus bandwidths
yield very good results: the two-module, two I/O
bus configuration yields a CPU performance in excess
of .95 and a memory bandwidth utilization in excess
of .80 for drum processor transfer rates between 1
word per 2.00 usec and 1 word per 2.50 usec; the
four-module, two I/O bus configuration yields a
CPU performance in excess of .95 and a memory
bandwidth utilization in excess of .50 for drum processor transfer rates greater than the bandwidth of a
single module. Also, the four-module, four I/O bus
configuration yields an impressive .99 CPU performance for a drum processor transfer rate approaching
twice the bandwidth of a single module.
The effect on CPU performance and memory bandwidth utilization caused by the addition of a disc
processor to a configuration similar to that in Figure
6 'is given in Table V. These results are for drum and
disc processors which make memory references
(on the average) once every 2 usec and 18 usec respectively. Both processors have double buffer registers and, as shown in Figure II, they have separate
memory busses. The disc processor has request logic
which makes low priority requests until a request
is accepted or until only three memory cycles remain
in the transfer interval; in the latter event, high
priority requests are made until one is accepted.
Since the drum processor, which has the highest request priority at its disposal (Figure 12), will not
make more than two consecutive high priority requests to any particular memory module (at the
transfer rate indicated), the disc processor is assured
of a memory reference in each transfer interval. A
comparison of these results with those given previously shows that in most cases the addition of the
disc processor causes only a very small degradation
of CPU performance. Although this disc processor
must make a memory reference each transfer interval,
its relatively low transfer rate and its buffer-registerextended transfer interval make it a near ideal processor. This is evinced by the near optimum result
of a CPU performance of .94 and a memory utilization
of almost .91 for a two-module configuration.
CONCLUSION
It has been shown that the assignment of priorities
to requests, rather than to processors and busses,
can be very effective when used in conjunction with
memory systems which provide ample memory
bus bandwidth to the processors. Although an excess
of bus bandwidth over processor transfer rate must
be provided, processors with appropriate data buffering mechanisms can operate effectively with
transfer rate to bus bandwidth ratios exceeding threefourths. More importantly, in optimum configurations
the several processors, can operate at very high per-
Intercommunication of Processors and Memory
1.00
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Fixed (high)
Priori1;y Assignment
/
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lOO
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1.25
1.50
1.75
2.00
2.25
Average time between drum processor initiated memory references
2.50
Figure IO-CPU performance for double buffered drum processor
(for 2 and 4 memory modules and 1,2, and 4 memory busses to
the drum processor).
NUllJlber
of Meomory
of
BuSIIPII
Dynemi('
Priority
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Number
of Memory
... ~O
CPU
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~
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.716
.89<
.716
,'/47
.8.'6
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.715
.796
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.7)3
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.401
.IM
.3(0
1.000
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~
of Busses
of Busses
to Dr""
~
~
to Disc
Memory
CPU
~
Bandwidth
~
.112
.837
.931
·909
.~
.898
.447
.383
.998
.470
1.000
.470
.7/4
.1/3
perroraanc~.
~lIIorybandwit1thutili"lIItion.
Table IV -CPU performance and memory bandwidth utilization
for double buffered drum processor (Figure 9)
Table V -CPU performance and memory bandwidth utilization
for double buffered drum and disc processor averaging one memory
reference every 2 usec and 18 usee respectively
632
Fall Joint Computer Conference, 1967
~
Drum
CPU
Rrocessor
Disk
Prcx:essor
.-
"'-
--.....-
r--
82
81
I
MO 1
1 M1
M2 1
I
M3
Figure I I - Drum processor and disc processor (with double
buffer registers)
>,
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OM
H
0
'M
Drum High
~
Disc High
bD
CPU
0
OM
CIJ
«l
Q)
H
Drum Low
()
C
H
Disc Low
Figure 12 - Memory request priorities for CPU. drum and disc
processor configuration
formance figures while using more than three-fourths
of the memory bandwidth.
It should be noted, however, that the results presented in this paper were obtained from simulations
of computer systems having a relatively small number
of high-transfer-rate processors and having synchronous memory systems. As a result it was possible
to make the logic used in these systems to determine
the priority of a given request relatively simple. Systems having several high-transfer-rate processors,
however, must provide mechanisms by which priorities can be determined on the basis of other requests
made at the same time by other processors. For example, in the systems described, the single high-transfer-rate processor (drum processor) makes low
priority requests until there is only one memory
cycle remaining in which to make the reference. It
t;an wait this long because there is no processor
which can make a request of higher priority. If no
additional means of assigning and interpreting
priorities is provided, then one of the drum processors
in a four drum system would have to start making
high priority requests when there were four memory
cycles remaining in its transfer interval. This is obviously not an optimum procedure. A more reasonable
method is to assign a priority which reflects precisely
the number of cyles remaining before the reference
must be made. Logic at each memory module can
then interpret the priority of requests from a more
englightened viewpoint, considering the likelihood of
congestion at the module within a few cycles. For example, it a request from a CPU is received by a
module simultaneously with two drum processor requests, the CPU request should be accepted unless
the drum requests indicate that 1) both drums require
a reference within two memory cycles or 2) one drum
requires a reference immediately. A simple scheme
which is effective in systems with only two or three
high-transfer-rate I/O processors provides a "warning" priority which is employed on the one or two
cycles preceding high priority requests. At each module, a single warning priority request is interpreted as a
low priority request whereas mUltiple (simultaneous)
warning-priority requests are interpreted as high
priority requests. This interpretation assists in allowing a drum processor to make several low priority
requests while precluding the occurrence of multiple
high priority requests at a given module which cannot be accommodated.
An additional complication is introduced if the
memory system is asynchronous. Such a system
allows a processor to make a memory request at an
arbitrary time, without regard for memory cycle
times. This freedom provides several advantages, such
as allowing the CPU to make an operand reference
immediately upon determining its effective address
without waiting for the next memory cycle. However,
this type of memory is not amenable to dynamic
priority assignment as described, because most requests in this type of system are granted on a firstcome-first-served basis. Only when mUltiple requests
are presented to a module (or bus) simultaneously
is a decision based on priority. Work on a memory
implementation which will provide the advantages of
asynchronous systems and dynamic priority assignment, plus other advantages, is currently being pursued by the author; preliminary results from this
work are very encouraging.
ACKNOWLEDGMENTS
For the simulation results presented, I am indebted
to Mr. Eric Ha who wrote the simulation programs
Intercommunication of Processors and Memory
and to the programming staff of Project Genie for
the Berkeley Time-Sharing System on which these
programs v:ere run.
4
REFERENCES
5
1 CTCASALE
Planning the 3600
Proceedings of the Fall Joint. Computer Conference 1962
pp 73-85
2 GMAMDAHL
Engineering aspects of large, high-speed computer design;
Part II-logical organization
IBM Technical Report TROO.1227 December 18 1964
3 M KENRO K NAKAZAWA
6
7
633
Very high speed and serial-parallel computers HITAC
5020 and 5020E
Proceedings of the Fall Joint computer conference 1964
pp 187-203
J P ANDERSON et al
D825 -A multiple-computer system for command and control
Proceedings of the Fall Joint Computer Conference 1962
0086-96
System description Univac I J08 multi-processing system
Univac Reference manual, UP-4046 Rev 1
MJ FLYNN
Very high-speed computing system
Proceedings of the I EEE Vol 54 No 12 December 1966 pp
1901-1909
W W LICHTENBERGER M W PIRTLE
A facility for experimentation in man-machine interaction
Proceedings of the fall joint computer conference 1965 pp
589-598
Stochastic computing elements and systems
byW.J. POPPELBAUM, C. AFUSO andJ. W. ESCH
University of JIIinois
Urbana, Illinois
INTRODUCTION
To date essentially only two fundamentally different
representations of numbers have been used in electronic computers: One is the analog representation
by a voltage or current inside a given range, the other
one, the digital representation which maps a sequence
of O's and 1's onto a spatial or temporal sequence of
voltage or current pulses. Of late, interest has arisen
in the use of random pulse sequences as information
carriers. (l), (2), (3), (4), (5), (6). It turns out that
the use of random pulse sequences leads to the use
of digital ANDs or ORs for the fundamental operations of multiplication and summation and therefore to a very considerable reduction in cost of the
computational equipment. I t is the purpose of this
paper to present the theory of these random pulse
sequences as well as their practical circuit implementations, and to give some systems design examples. In the final section some non-Von Neumann
organizations will be discussed which are made possible by the use of stochastic computing elements.
In the course of developing the techniques in question our initial Random Pulse Sequence System
(RPS) was replaced by the Synchronous Random
Pulse Sequence System (SRPS). In the former case
a sequence of standardized pulses represents the variable value by its average duty cycle, with the understanding that the standardized pulses occur at entirely
random·times. In the SRPS system these standardized
pulses occur in fixed time slots with a probability of
occurrence equal to the variable value. The main advantage of the latter system is that addition and multiplication of two SRPS's in an OR or an AND leads
to another SRPS without any further normalization.
Figure 1 shows a way of generating controlled
RPS's and SRPS's. The principle is simply to generate white noise in a noise diode and to -amplify it
in a threshold device, the threshold being proportional
to the variable value. Reshaping of the output of this
threshold differential amplifier leads to an appropri-
ate RPS. For the production of an SRPS it is only
necessary to set a flip-flop into the 0 state by the above
RPS and to clear this flip-flop to 1 by a clock having a
period considerably smaller than the average period
of the RPS. The pulse transmitted through a capacitor
upon resetting the flip-flop (if it had been set by the
RPS during the preceding clock period) can now be
reshaped in order to obtain an SRPS.
Figure 2 shows the inputs and outputs of an AN D
and an OR receiving as their input two SRPS's. It is
easily seen that the average frequency of the outputs
is respectively proportional to the sum or the product
of the average input frequencies. It should be noted
that certain difficulties (coincident pulses) arise in
the case of the OR circuit when the incoming sequences are not mutually exclusive. This case can be
easily eliminated by slightly more sophisticated design discussed in Section 4. A more detailed discussion of the mapping of numbers onto RPS's and
SRPS's will be found in Section 2.
It is now clear that since adders and mUltipliers have
the simple form of DRs and ANDs the production of
very complicated linear combinations of numbers can
be done with great ease and at low cost. The principal application of stochastic computingr- elements
should therefore lie in those areas where such linear
combinations are of use. Happily enough, the series
expansion of the most general functions contain such
linear combinations. One of the most attractive applications is that of a General Image Transformer
described in Section 6.
It should be emphasized at this point that theory
shows (See Section 2) that approximately 10,000
pulses are needed in order to obtain 1% precision. This
means that a 1% result must wait for 1 millisecond if
the average pulse repetition frequency is 10 MHz.
This precision is entirely sufficient for most control
applications and certainly more than adequate in the
processing of light intensities, i.e., video information.
Unluckily, a tenfold increase in precision, i.e., a
635
636 Fall Joint Computer Conference, 1967
.JLJL.JLJUL
SHAPING
CIRCUIT
P
DIFFERENCE
AMPLIFIER
I
MODULATING
VOLTAGE v
NOISE
DIODE
SHAPING
CIRCUIT
Q
THRESHOLD
v -ft---I'-I-t-A--++----I-A---
SRPS
POINT P ----.
POINT Q ----.
Figure I - Production of synchronous random pulse sequences
result known to within .1 % necessitates not ten times
more but 100 times more pulses. Stochastic computing elements are therefore strictly limited to calculations in which roughly .1 % precision is the very
upper limit. It should be emphasized that the limited
precision in stochastic computing elements is inherent in the method because of the fluctuations encountered .in the random process. This means that
if we represent a constant value by an RPS or SRPS,
the average frequency will vary slightly between adjacent time intervals. It is only when these time intervals are made long enough that the RMS value of the
f1uctuatipn becomes small enough_ This still by no
means excludes an entirely unlikely value for the
average frequency in some very rare cases!
Mapping of numbers onto RPS's and SRPS's
I n! a RPS described by e(t) each pulse is of height
Vo and width T and the frequency changes at random
ahout an average value f: Figure 3 shows such a
seqt)ence. We can define the average voltage V over
a time T(T» T) by
V
= TI IToe(t)dt
(2.1 )
and the average duty cycle x by
v
x=Vo
(2.2)
Note that x is simply the probability at a given time of
finding e(t) = Vo. It is easily seen that 0 :::::; x :::::; I and
that
f=~
T
(2.3)
In the RPS-System it is natural to represent a normalized positive number X by x = X. Normalization
is, of course, no restriction because any computer
representation demands it. The restriction X ~ 0
can be lifted in two ways: We can invert the pulses
so as to obtain negative values of V or we can use a
separate wire to carry the sign information.
As we pointed out before, the shape of pulses is
destroyed by passing them through OR's and AND's.
This difficulty is eliminated by timing the beginning
of each pulse, should it occur, by a centralized clock.
The characteristics V 0 and'T of each pulse remain unchanged. Figure 4 shows such a SRPS and it is clear
that AND- or OR-operation no longer affect the
Stochastic Computing Elements and Systems
Jl~11
I
637
n~
I
I
I I
AVG. FREQ. FI
I
II
I I
I .
I
I
I:::I
II
I I I I I
I I I 11,....1----,
I
I
I
I
I
AVG. FREQUENCY- PROP. TO SUM F 1+ F2
I
I
AVG. FREQ. F2
___
Jl~1 III_ ~n
I
I
I
I
I
I
I
AVG. FREQ. F I
I
II
I
I
I
I
I
I
_______H
iI I II :I : :I
1
:
I
I
I
I
1
I
I
I
h~:_
AVG. FREQUENCY - PROP. TO PRODUCT FI F2
AVG. FREQ. F2
Figure 2 - Use of or's & and's for addition & multiplication in
synchronous random pulse sequence system
given time-slot. All we have done, of course, is to
replace X ~ x by X ~ u with
e(t)
t
Vo
U=X(T; )
o
(2.5)
-t
Figure 3 - A random pulse sequence
shape. It is also clear that equations (2.1) ... (2.3)
remain valid. Here, however, the maximum value of
x is ~ 1 because T is usually less than the clock period
To: It is more efficient to map X onto
f
I
u =fo where fo = To +
Sign questions can again be solved as above.
In practice the averaging time T is finite and all
quantities in (2.1) ... (2.5) show fluctuations: These,
as pointed out before, are inherent in randomness and
limit the dynamic accuracy of the system. For a RPS
with T < < T the pulse distribution in time is described
by a Poisson distribution with standard deviation
given by VIT. Therefore the relative fluctuation of
all variable values with respect to the average value,
fT, is
(2.4)
i.e., the probability of the occurrence of a pulse in a
(2.6)
Faii joint Computer Conference, 1967
638
operations depending on a "function signal" from the
outside world. Such a GCE is shown in Figures 6 and
v
e(t)
to
7.
.......
CLOCK
PERIOD
Figure 4 - A synchronous random pulse sequence
For a SRPS the probability distribution in the fixed
time-slots is binomial with standard deviation given by
v' nu( 1 -
u). The relative fluctuation with respect to
the average value, nu, is
%
(2.7)
where n is the number of clock pulses during T, i.e.,
n=T/To·
The four fundamental operations of arithmetic for
RPS's
I t is trivial to show that in the mapping X ~ x we
can use OR's for addition if we neglect the case of
overlapping inputs. The reason is, of course, that
under this assumption we have simply f = fl + f2 where
f corresponds to the output and fl and f2 to the inputs.
This implies that
For multiplication we use the probabilistic interpretation of (2.2) which gives directly
(3.2)
for the output of an AN D circuit fed by RPS's
corresponding to Xl and X2 respectively.
Unluckily subtraction and division offer slightly
more difficulty: They both necessitate the generation
of an output RPS by a new RPS-generator, the latter
being steered by an appropriate combination of aver. age values. In the case of subtraction, we invert the
sequence to be subtracted (i.e., form a sequence whose
pulses go negative from ground) and use the difference
of the average values of minuend and subtrahend to
steer our generator. For division we use a layout'as
shown in Figure 5 in which the generator for X3 is
steered by a feedback system: When X3 is such that
X2X3 is on the average equal to Xl, we obviously have
X3= XI/X2'
I t is entirely possible to design a General Computing Element which performs anyone of the above
G b G 2, ... , G 7 are diode gates whose input impedance are practically infinite when they are OFF .
For multiplication, G b G 3, and G 6 are ON (gate control voltage = 0) and the rest of the gates are OFF
(gate control voltage = 5v if the pulse height of the
R.P.S. is 5v). Xl and X2 are ANDed with DI and D2
and the average voltage of the inversion of the
product is compared with the average voltage of the
inversion of the local R.P.S.G. R.P.S.G. is controlled
by the comparator output such that the inputs to the
comparator have the same average value.
For division, XI/X2, (assuming Xl < x2!) only G 2,
G3, and G 7 are ON. X2X3 is formed with D2 and D3
and the corresponding average voltage of X2X3 is compared with that of Xl and the R.P.S.G. is adjusted so
that X2X3 = Xl' The output, X3, thus gives XI/X 2'
For addition, only G I, G 5 , and G 6 are ON. Since
G 3 and G 7 are OFF (5v) the AND gate formed with
Db D 2, and D3 gives Xl itself. At the collector circuit
ofTI.and T7 the analog sum is formed and the R.P.S.G
is adjusted so that X3 = Xl + X2.
For subtraction, Xl - X2, assuming Xl ~ X2, only
G b G 4 , and G 6 are ON. The situation is the same as
that of addition except that X2 is fed through T 5 and
T 6' Analog inversion takes place at T 6 and hence
X3= XI - X2·
Since R.P.S.G. employs 5 transistors and a few
diodes, the whole unit employs 12 transistors and
about 30 diodes. In order for the element to be able
to handle negative inputs and outputs, additional sign
carrying wires and sign detector circuits are needed.
The four fundamental operations of arithmetic
forSRPS's
In the mapping X
~ X(
:0) = L= u .we see with-
out difficulty that we have again f=fl
put of an OR, i.e.,
u = ul
+ U2
+ f2 for the out(4.1)
The probabilistic interpretation of u in (2.4) leads
immediately to
u
=
U I • U2
(4.2)
for the output of an AND and therefore produces
multiplication, this time without danger of damaging
the pulse shapes.
Having in hand addition and multiplication by
purely digital methods it becomes attractive to handle
subtraction and division in a purely digital fashion.
Happily enough this is possible in the case of SRPS's
because of their occurrence in fixed time-slots. For
subtraction we can build a simple deletion circuit in
Stochastic Computing Elements and Systems
639
----)-
MULTIPLIER
INPUT
X2
b
~
~
X2- Xl
-
AVERAGING
UNIT
X3 GENERATOR
OU TPUT
-
DIFFERENTIAL
AMP.
---
AVERAGING
-
IN
'-
UNIT
-
- DISCRIMINATION
LEVEL CONTROL
DIVIDER
Figure 5 - Multiplier and divider in the R.P.S. system
which (for the case minuend> subtrahend) the occurrence of a subtrahend pulse leads to the deletion of
the next minuend pulse. In order to obtain higher
precision a small memory buffer may be incorporated
so that bunching of subtrahend pulses can be taken
care of. Note that the output of such a deletion circuit is again a SRPS and that obviously f = f. - f2 •
Division finally can also be handled digitally by
observing that the problem X/Y can be solved for
X « 1 and 0 ::::; Y ::::; 1 by the following procedure:
1. Each time an X-pulse occurs, mark the next Ypulse as the beginning of a "counting interval"
and the Y -pUlse following it as the end of a
"counting interval."
2. Count all time-slots inside a "counting interval"
and add 1.
3. The SRPS consisting of groups of bunched
pulses in "counting intervals" represents
Z=X/Y.
That this is effectively so, is seen by considering a
very long sampling time T: in it there will be (See
Figure 8)
(4.3)
n = TfoX X-pulses
since X = fIfo. The average period S of the Y -pulses
is given by
(4.4)
This is by definition the length of a "counting interval" and corresponds therefore to Sfo pulses of the
output sequence. During T we shall observe n bunches
of Sfo pulses, i.e., the output represents a number Z
such that
Z = avg. frequency = # of pulses
fo
Tfo
(4.5)
Again it is possible to design a GCE which, however, this time uses digital circuitry only. Figures
9-12 show a possible solution in which only the important paths are shown in a GCE consisting of
l. An UP-DOWN Counter.
2. A J-K Flipflop.
640 Fall joint Cumputer Cunference, i 967
tZ
(!)
(/)
W
Q.
a:
II
II
~
W
.....J
W
-.J
0
W
en
z
}OW
e . . ....
@
W
en
-.J
:::>
(!)
w~
~
X
zw
oz
a...
u
~
II
0
0
z
«
0::
0
::>
II
II
<.9
CJ)
a...
0::
Figure 6 - Schematic diagram of general element
II
Stochastic Computing Elements and Systems
CONTINUED FROM
PREVIOUS PAGE
'CD ®'
RPS
IN
Figure 7 - Schematic diagram of general element
3. Digital Steering Circuitry.
4. Feedback Paths Wand Z.
The system is visibly synchronous: The element puts
out the sequence delayed by one clock period. In case
of the division circuit an additional refinement injects a normalizing factor .1 so that we can use
o :s X :s J and 0 :s Y :s J with the single restriction of
X:sY
Again operation with negative numbers is possible
but will not be discussed at this point.
An array computer using GeE's
By a slight extension of what was discussed in the
previous section, we can define a computing element
which performs on its two inputs a and b the operations a + b, a - b, a x b, as well as two types of
division a7 b (denoted by I) and b 7 a (denoted by I).
To this repertory we shall add the operation (A) ~
connection of output to a and (B) ~ connection of
output to b.
641
I t is then possible to design array computers of considerable power having a fixed structure. Figure J 3
shows a three row, eleven column array with a
"straight through" connection for the top row and a
"down right" connection for the bottom rows. Programming this array now simply consists in defining
the function of each GCE for the operation. An
interesting example is furnished by functions F which
can be expressed as sums of continuing fractions, i.e.,
F = ~ fi where fi = continuing fraction. In this case
there exists a simple 5-step algorithm to determine
the operation to be performed by each element:
Step 1.: Using a "Polish Notation" in which operands
precede operators and using the symbols + ,-, I, I,
(A) and (B) defined above, write 2fi as a "Polish
String" ,PS, with (B) inserted after the first fi.
Step 2.: Write each fi as a PS with all products treated
as single variables (called "product variables") and
insert (B) after the first variable or "product variable"
of the f i.
Step 3.: Write each "product variable" <;If Step 2 in
terms of individual variables in a PS. Insert (B) after
each variable which is not a "product variable" and
each first variable of a "product variable."
Step 4.: Combine Steps J through 3 into a single PS.
Step 5.: "Fill in" the functions of the elements by
reading off the PS of Step 4. To this end start with the
bottom left-hand element of the array and procede
horizontally. When more than one operator occurs
consecutively, fill in vertically until the next operand
is reached. At the end, fill in all unspecified elements
with the operator (A).
The figure shows as an example the set-up for the
function
F = r/(s + t) + (gh)/{(wt) + b [(dp) + y]}
I t is easily verified that the algorithm leads to the PS
given below the expression for F and that the array
effectively forms F.
A stochastic image tran:,former
As mentioned in the Introduction, one of the most
attractive applications of stochastic computing elements is the simultaneous formation of very extensive
linear combinations of variable values. We shall now
describe a machine organization (which is as far removed from a Von Neumann machine as possible)
which uses exclusively such linear combinations. Although we call this system an Image Transformer, it
should be realized that "Signal Transformer" would
be more appropriate. Figure J 4 shows the schematic
diagram of what is proposed: The object of the game
is t9 map n 2 signals Xu (ij = J, ... , n) onto n 2 output
signals Ykl (k, I = I , ... ,n) in such a fashion that
each one of the y's is a weighted linear combination
642 Fall Joint Computer Conference, 1967
rI I
I I I
I I
JlII II II
SRPS~x
I
I
I
I
I
I
1
~
I
I
1
S
~
nl I I In
I
I
SRPS --.y
I
\
I
I
I
I I
11 I
I I I II
I
I
I
I 1
I
I
I
I
1
I
I
I
I
I
I I 1
S --.I I
I I
I
1 ~I
1
nl nl
I I I
I I I I
I I 1 1
I I I I I
I I I
flJlJ1fUl1
I
I I
I I I
SRPS--.z
1
1
I 1 1
I I---
1
1
I
I
I
I
1 I
I
1
I I
I I
I I
I
J
"'"
I
I
-I
flL
1
I
I I I
1
I
I
I
I
1
nil
I I
I I
I
I
I
I
~
I
I
I
I 1
T
!
1
I
I
I
I
II I1
I
I
I
I
nnnJl:
I
I I I
I 1
1 I
I
I
1
Figure 8 - Division of SRPS's
r--------------------------,
~~
w
CLOCK
A
~
~N~
l
UP
DETECT ALL l's
C
COUNTER
DOWN
DETECT ALL 0',
-- -
lOR
B
oJ
CLOCK
Ar----------------------------,
~
I
I~~~~---~J
~
lr-~~AB~
:
C
BI
K
0
L _____________________________
:
~
A+B
1
C
I--
~N~
K 0
1--_
l
L ____________________________
J
Figure II - Multiplication of SRPS's A and B
:+:.
r-------------------------------,
Fgure 9-Addition ofSRP's A and B
I
: ~_-« ~---OI
r----------------------------,
I
I
A
I
AI
C
I
I
.11
COUNTER
DETECT ALL 0',
I
I
i!
I
B
l--P
n
L
Xj exp(i27Tjk/n)
j=O
for k = 0,1, ... n-l, where Xj are complex data values
and O!k are complex Fourier coefficients. The algorithm can also be used to evaluate the inverse transform
n-I
Xj =
j
n-I
L ak exp(-i21T'jk/n)
k=O
j=-m+1
for k = 0,1, ... n/2 are useful, and can be computed
quickly, and without mUltiplication except for scal-
for j = 0,1,. .. n-l. The method of computation is
based on decomposing n into 'its factors nj for j =
1,2, ... m, where
Real-time Spectral Analysis on Small General-purpose Computer
n=
The transform is computed in m stages, with n/nj
transforms of dimension nj evaluated at the jth stage.
The number of arithmetic operations is proportional
to
m
n L nj
j=1
instead of n2 as in most other methods - a substantial
saving when n has more than one prime factor.
Clearly, small factors are advantageous.
In the system described in this paper, n is assumed
to be a power of two and we use factors of two in the
transform. Factors of four or eight give some gain in
efficiency, taking better advantage of multiples of
'TT12 and 'TT14, but require larger programs. This possibility should be investigated if sufficient program
storage is available. Other factors, such as three
or five, can be provided for if needed by added coding,
Without significantly changing the maximum bandwidth of the system.
Since the input data are real-valued rather than complex, we can take advantage of the complex conjugate symmetry
a*n-k=ak
for k = 1,2,... n/2 of a complex transform of real
data, and transform two sequences of real values at
the same time, storing one as the real component
and the other as the imaginary component of the complex vector to be transformed. The symmetry property
allows separation of the two transforms. In a single
input system, we take the even- and odd-numbered
data values for the two real sequences, compute a
complex transform of dimension one-half the number
of data points, separate the cosine and sine coefficients for the two sequences, and then combine results as a final step to give the Fourier series cosine
and sine term coefficients for the full set. In a system with dual input channels, and assuming equal
sample sizes for the two channels, we simply separate
the results after computing the complex transform.
When the fast Fourier transform is computed in
place - that is, with the results of each elementary
transform of dimension nj stored in place of the nj
complex values used in computing the transformthe final result must be permuted to bring it into
normal order. Alternatively, the data can be permuted
initially and the transform computation rearranged to
669
give the final result in normal order. The choice between the two approaches makes little difference in
computing time; we have used both ways, and now
permute prior to the transform, while storing the
initial input data values. For n a power of two, a
reverse binary permutation is required - that is, the
data storage locations are indexed in inverted bit
order. In 'our real-time system, a stored permutation
table of length ~ the transform dimension (~ the
sample size) is used for this purpose. This table can
be eliminated with some loss in computing speed if
additional storage space is needed; a programmed
reverse binary counter would then be used.
As is typical of many small computers, the SDS
930 computer used in our real-time analysis system
performs fixed-point arithmetic considerably faster
then floating-point. This led us to consider the
possibility of computing the last Fourier transform
with fixed-point arithmetic. When we examine the
computational steps, we find that if the complex data
values are scaled initially to be less than one in magnitude, and are then scaled by an additional factor
Ilnl prior to the first stage, where n1 is the first
factor of n in the transform, the complex values on
completion of the first stage are again less than
one in magnitude. If we continue, scaling prior to
each stage by the reciprocal of the factor of n used in
that stage, the final and all intermediate complex
values remain less than one in magnitude. The overall
scaling during the transform is lIn. For our program,
using only factors of two, we scale the real input data
values to be less than 0.25 in magnitude, yielding
initial complex values less than Y2t4 in magnitude.
The results of each two-by-two transform in the first
phase are tlien less than one in magnitude (in fact,
less than Y2t2), and are scaled by 1/2 before storing.
The intermediate results are similarly scaled by 1/2
between succeeding stages of the transform computation. The final step of separating the Fourier coefficients for the even- and odd-numbered data entries
and combining the results induces a mUltiplication by
2, yielding a value of laol < 1.0, and all other Fourier
cosine and sine coefficients <0.5 in magnitude. With
this scaling, all numbers remain less than one in
magnitude, yet good accuracy is maintained.
Bandwidth
In using the term maximum bandwidth, we refer to
the maximum bandwidth attainable without omitting
segments of the original signal. If the computing time
for a given number of sample points is greater than
the time span of the sample, we must sample bursts of
data. In this case the spectral barldwidth may exceed
the maximum for continuous sampling, but some data
670
Fall Joint Computer Conference, 1967
is lost. The seriousness of this loss will depend on the
rate of change of the spectral content of the signal.
We can, on the other hand, overlap samples, with a
corresponding decrease in bandwidth. When using the
data-window function (3), overlapping samples by 50
percent gives improved utilization of the available
data. In this way, each sample value is divided between two sample sets, with a combined weight of
one; however, the maximum bandwidth is reduced by
one-half.
In a multiple-input system, the available maximum
bandwidth is shared among the several channels.
With two channels and samples of equal size, the
bandwidth is approximately one-half that for a single
channel. In this case, a single complex Fpurier transform can be used to transform the two samples. With a
relatively simple change, the transform program can
handle any even number of equal-sized samples, with
some saving in indexing time.
a result significantly better than the quantization
range of the ADC. We see that doubling the sample
size gives a 3-dB improvement in signal-to-noise
ratio (10 log102). Each additional ADC bit -i.e.,
doubling the number of possible converter output
levels - gives a 6-dB improvement in signal-to-noise
ratio. Experimental results give good agreement with
the performance predicted by the above formula.
With k = 8 for our converter, and with a sample of
2048 data points (m = 11), the predicted signal-tonoise ratio is 80 dB; this is about the average base
noise level observed experimentally for a sample of
this size. Use of a 14-bit converter, a commercially
available product, would raise the theoretical dynamic
range to 116 dB for n = 2048.
The power spectrum of an unwindowed signal of
. approxImate
.
. amp1·ItU d e at f requency -xfs IS
1y
umt
n
2
Dynamic range
In a digital spectral analysis a number of factors
combine to give a base noise level in the frequency
domain, even without noise in the original signal. In
order to distinguish a periodic component in the
signal, it must stand above the random fluctuations in
the base noise level in the frequency domain. The
main factors determining this base level are response
to single tone input, the analog-to-digital quantization
noise level, the sample length, and the computer
roundoff noise.
First we establish a reference level with which to
compare the base noise. Suppose we have an analogto-digital converter with k-bit output, giving 2k possible sample levels, and assume a sine function signal.
Using the full range of the converter, the rms level of
the signal is 2 k - I /Yf', or, in dB,
signal level = 20 loglo(2 k - I /v2)
= lO(2k - 3)loglo(2).
If we assume the converter to be a noise source,
adding a random component with uniform distribution
on the interval [- ~J2] to the signal, the resulting
noise spectrum is nearly uniform over the 2m - 1
spectral estimates for a sample of 2m data values. The
average power level (variance) of this uniform noise
can be shown to be 1/12. Thus the noise level of the
spectrum from this source is approximately
noise level = 10 loglO(I/(l2 x 2m - I »
= - 10m loglo(2) - 10 loglo(6).
The resulting signal-to-noise ratio of the spectrum in
dB is then
signal/noise= 10(2k + m - 3)log 1o(2) + 10 loglo(6)
= 3(2k + m) - 1.25,
I [ sin(7T(k-x» ]
2 n sin(7T(k-x)/n)
(4)
for values of k near x. If x is an integer, the powerspectrum value is 1/2 at j = x, and zero ·elsewhere.
In general, however, the power spectrum of an unwindowed signal falls off slowly with IX-jl, and the
dynamic range is seriously limited. Using the data
window in Eq. (3), the main peak of the response function is broadened, but beyond two resolution cells
falls off more rapidly with Ix-jl than function (4),
fast enough to be below the usual analog-to-digital
converter noise level by 10 resolution cells away
from a periodic signal at the maximum amplitude
allowed by the converter. In most cases this is adequate data windowing to eliminate response shape
(leakage) as a limiting factor in dynamic range.
With typical computer word lengths, computer
roundoff noise is negligible compared with the other
two factors we have discussed. Since the fast Fourier
transform of n = 2m real data points requires only m
steps, including the final step to separate and recombine the transform of the even- and odd-numbered data values, round-off error in the transform
is low, even when using fixed-point arithmetic.
However, in squaring the sine and cosine coefficients
to form the power spectrum, double precision results should be retained or a shift to floating-point
arithmetic made. Otherwise, the potential dynamic
range of the computations will be reduced. The
computer in our real-time analysis system has 24bit words, including sign, which is more than adequate in comparison with the 8-bit' analog-todigital converter. On the other hand, a 12-bit com-
Real-time Spectral Analysis on Small General-purpose Computer
puter word-length would result in computer roundoff being a more important factor in limiting dynamic range than the analog-to-digital converter.
The ability to distinguish two tones as separate
peaks in the power spectrum depends mainly on their
relative levels and the number of resolution cells
separation between the two tones. For tones of equal
amplitude, a minimum separation of three resolution
cells (i.e., 3fs!n), is needed to give a dip between
peaks. For detection of a weak peak near a strong
one, as in Doppler signal analysis, more separation
is needed. And the weak peak must, of course, be
above the base noise level of the spectrum. In Figure
2 we show the results of an experiment to study the
effect of windowing in two-tone resolution. These
analyses were computed with n = 512, giving 256
resolution cells. Smooth curves were drawn through
the discrete points. The simulated signal was
sin(7Tj 128.5/256) + 0.001 sin(7Tj 137/256)
for j = 0 1,... 51 1. The first component is midway
between two mUltiples of fs/n, and the second is 60
dB down and 8.5 resolution cells higher in frequency.
The power spectrum was computed without data
windowing, with the data window
sin2(7Tj/n)
(5)
and with a second data window
sin4(7Tj/n).
(6)
The signal 60 dB down and displaced by 8.5 resolution cells can be seen in the runs with window function (5) and (6), but not in the unwindowed run.
671
O~---.---------.--------.---------.-----~--------~----~
-10
-20
CD
"CI
I -30
UJ
(J)
z
o
Il.
(J)
UJ
a: -40
a:
UJ
I-J
~ -50
I-
z
UJ
-J
ct
~
-60
:l
o
UJ
-70
\
-80
'It
.4
'\F sIn
,
..,,
-90
WINDOW
..,
-I 00 0;.--------"*--------~--------~--------lL....--------'-1
0......---L.....J12-----~14
FREQUENCY -
resolution cells
Figure 2 - Effect of windowing on two-tone dynamic range
I mplementation of a real-time digital
analysis system
The components of a typical real-time digital spectral analysis system are shown in Figure 3. This diagram illustrates a multiple-analysis-channel system,
designed for simultaneous processing of several
spectral channels. A high-speed digital switch (or
multiplexer) under computer control is used to sequence among the analog input channels. An ADC
is used to convert the voltage level on the designated
channel to a binary-coded sample value. Once the
power spectrum is calculated, the values may be displayed or used as data for further calculations. With
most display units, some form of digital-to-analog
converter (DAC) is needed. Digital interface circuitry linking the ADC and DAC units to the central
computer is also needed.
The necessary size of high-speed memory for a
computer in a rcal-time analysis system is mainly a
function of the maximum number n of data points to
be processed in an analysis ir..terval-i.e., of the sum
of the sample sizes for each of the input channels in
a multi-channel system. The minimum storage re-
quired is of the order of 2n for data, n locations
for the data currently being transformed, another n
locations for storing the next data set, and several
hundred locations for program storage. Adding table
storage of the sine and reverse binary functions, we
arrive at a practical minimum of 3n locations for data,
program, and tables. In this we make no allowance
for separate output buffer areas. We assume either
that the output is completed by high-speed transfer
prior to the start of computing for the next sample,
or that a common input-output buffer area is used.
In the latter case, an output operation is interleaved
between each pair of input operations; every second
input value replaces an output value that has already
been used, and the output is clocked at half the input
rate. If equipment limitations require separate input
and output buffer areas, then one or two additional
areas of size n/2 will be needed for output.
In selecting a computer for real-time spectral analysis, input-output buffering independent of the main
program is a desirable feature to have. Lacking this,
an efficient method of external interrupt is essential
672 Fall Joint Computer Conference, 1967
is also a valuable asset for a computer in this application.
Description of SRI's real-time spectral
analysis system
MULTiPLE
ANALOG
INPUT
CHAN"[LS
An experimental real-time spectral analysis system
using a general-purpose digital computer has been
assembled and tested at Stanford Research Institute.
A relatively small version of the SDS 930 digital
computer is used. This computer has 8192 24-bit
memory locations, which limits the sample size to
2048 values. It has one index register. Addition
time is 3.5 f.LS and mUltiply time is 7.0 f.LS. To reduce
computing time, the program for real-time spectral
analysis is written in machine language, and sine function and reverse-binary tables are used. A sample of
1024 data points can be transformed in just under one
second. Times for an earlier FORTRAN version
of the program, using floating-point arithmetic,
were slower by a factor of ten.
Figure 3 - Components of a real-time spectral analysis system
in processing real-time data. If data must be moved
between buffer areas and working storage arrays, the
capability to rapidly transfer groups of words is also
important. However in our demonstration system
input and working storage arrays interchange roles
for alternate data sets, thus avoiding the need for
actual transfer of location.
In the fast Fourier transform for n a power of two,
the inner loop of the algorithm performs a computation on a pair (Xj,Xk) of complex data values, and
stores the results (Yj,Yk) in the original locations.
This loop accounts for over 50 percent of the total
computing time. The complex arithmetic operations
are either
Xj + Xk ei8
Yj
and
Xj
Xk ei8
Yk
or
Xj + Xk
Yj
and
(Xj
xk)e i8
Yk
I~OOr-------------------_ _
1400
1300
..
:r
~ 1200
....
o
i
o
z
ct
CD
><"00
ct
~
depending on the particular form of the algorithm
used. The two forms require an equal number of arithmetric operations. When expanded into real and
imaginary parts, Re(') and Im('), the second form is
Re(Yj) = Re(xj) + Re(xk)
Im(Yj) = Im(xj) + Im(xk)
1000
9OO~~---~---~~--~~--~---I~02-4---2-J048
SAMPLE SIZE, N
[Re(xj) = [Re(xj)- Re(xk)]cos8 -[Im(xj)- Im(xk]sin8
[Re(xj) = [Re(xj)- Re(xk)]sin8+[Im(xj)- Em(xk)]sin8
Figure 4- Measured maximum bandwidth for real-time
analysis system
Since complex values require two storage locations,
four array entries are used in the calculation. The
locations of the four entries are incremented by a
common constant each time through the loop, until
a limit is reached. This constant, the separation k-j,
and the angle 8 are varied outside this loop. In comparing computers for possible use in real-time spectral
analysis, the estimated times for this loop should give
a good relative measure of computing speeds. Time
for this loop on our SDS 930 computer is 187 f.LS.
Multiple arithmetic registers can be used to advantage
in these computations; efficient address modification
Input to the system is through an 8-bit multiplexed
ADC; output leaves via two parallel 12-bit DACs,
under computer control through a digital interface.
Input of sample values is controlled by real-time interrupts. The input-output interface will permit only
single word operations; thus the main program is
interrupted for each input or output transfer. Maximum bandwidth for single-channel operation is approximately 1000 Hz, but varies somewhat with sample size as shown in Figure 4. At the maximum sample
size of 2048 values, the measured dynamic range is
approximately the 80-dB level predicted theoretically.
Real-time Spectral Analysis on Small General-purpose Computer
This digital spectrum analysis system has been used
to provide spectral measurements in a variety of research areas. The input data for these mea,surements
has typically b'een recorded on analog magnetic tape.
This is unfortunate in that the potential dynamic
range of the measurement is limited by the characteristics of the analog record-reproduce equipment;
the full dynamic range of the digital system is not
used. However, the resulting range is considerably
better than with currently available analog analysis
equipment. In addition, the real-time speed of analysis
allows tape playback at the same speed as recorded.
Equalization problems are minimized.
The analysis program allows two forms of output
for the estimated power spectrum. In one option, the
results are recorded on magnetic tape for later use.
In the other option, spectral estimates are sequentially
read out through a DAC in step with a ramp-function
(time sweep) on a second DAC to produce a two-axis
display. The results may be observed on an oscilloscope, and photographed, or used to drive an intensity-modulated electrographic chart recorder. In
the latter case, the power spectrum is logarithmically
scaled to better display the dynamic range of the
measurements. Although these devices work reasonably well, we feel there is a need for better display equipment for real-time spectral analysisi.e., equipment with improved resolution, dynamic
range, and ability to operate at real-time speeds with
a minimum of computer formatting and control.
The principal use we have made of this system is
in the analysis of Doppler radar signals. The high
analysis dynamic range has also made this spectral
measurement technique valuable for the on-line examination of frequency synthesizer output for spurious content and for measurement of radar receiver
frequency response. This initial system has served as a
useful tool in the development of theory and practice for real-time digital spectral analysis.
Possibilities for bandwidth improvement
The main limitation of the present system is bandwidth. The dynamic range is excellent, and can be
improved by buying an ADC with a greater number
of output bits, at a small increase in total system
cost. The resolution is also excellent, and can be
increased if necessary by providing additional
high-speed storage for data. Bandwidth, however,
can be increased only a small amount by means other
than substituting another, faster computer. Addition
of an independent input-output buffering system, not
interrupting the main program, would incr~::tse bandwidth in the order of 10 percent.
673
Multiple arithmetic units and ultra-high-speed
"scratch pad" memory can be used to good advantage in computing the basic two-by-two transform
loop. The Control Data 6800, one of the several large
computers with these features, would, for example,
allow a system bandwidth in excess of 70 kHz.
Another possibility is to add special-purpose hardware for~ complex arithmetic, or for computing the
entire two-by-two transform, to a general-purpose
computer.
By further use of parallel processing, system bandwidths of the order of one megahertz or larger would
be possible. The fast Fourier transform is an! ideal
candidate for parallel processing, since for each factor
nj of n we compute n/nj independent transforms of
dimension nj. Thus we could use n/nj processors operating in parallel. A multiple parallel processor for
the fast Fourier transform could be constructed
as a special-purpose device, using integrated circuit
techniques. The wiring-plan simplicity of one particular organization of the fast transform for computing with these techniques has been noted by Singleton 9 and by Pease and Goldberg. tO With this organization, a transform of dimension 2m is computed in
m steps, while copying back and forth between two
data vectors with fixed interconnection paths. A
preliminary study by Pease and Goldberg tO indicates
that system bandwidth can be increased by a factor
of 1000 or more through parallel computing. Bergland
and Hale l l have proposed another organization, using
m parallel arithmetic units for a transform of dimension 2m , but with serial computing within each of the
m steps. This proposal also offers promise of greater
improved bandwidth. In either case, the parallel processor could be an auxiliary device connected to a
general-purpose computer.
CONCLUSION
The fast Fourier transform algorithm has led to
revision in the methods of spectral analysis. I t has
also reduced computing time for spectral-analysis
calculations to a level where current-generation
general-purpose computers can perform spectral
analysis at real-time rates and with bandwidths that
are sufficient for many problems. Advantages of high
resolution, high dynamic range, repeatability, and of
flexibility of method through programmed, rather than
competitive with analog spectral analyzers.
We have assembled a real-time spectral analysis
system, using an available, small general-purpose
digital computer. The experimental results on this
system have met theoretical expectations. In this
system we have demonstrated a powerful new tool
674
Fall Joint Computer Conference, 1967
for real-time analysis of non-stationary time functions in the presence of noise.
Future developments in digital technology will lead
not only to faster and more versatile small generalpurpose computers, but probably also to parallel
Fourier transform processors as adjuncts to these
computers. The greatly increased bandwidth can be
expected to bring many more spectral analysis applications into the realm of real-time digital processing.
ACKNOWLEDGMENTS
The authors wish to thank the many Stanford
Research Institute staff members who gave helpful
suggestions and encouragement in this work.
REFERENCES
R B BLACKMAN J W TUKEY
The measurement of power spectra
Dover Publications Inc New York ]958
2 C BINGHAM M D GODFREY J W TUKEY
Modern techniques of power spectral estimation
IEEE Trans. on Audio and Electroacoustics Vol AU-15
No 2 pp 56-66 June 1967 This is a special issue on
the last Fourier transform and its application to digital
filtering and spectral analysis
3 T G STOCKHAM
High-speed convolution and correlation
AFIPS Conference Proceedings 1966 SJCC Vol 28 pp 229233 Spartan Books Washington DC] 966
4 W M GENTLEMAN G SANDE
Fast Fourier transforms-for fun and profit
AFIPS Conference Proceedings ]966 FJCC Vol 29 pp 563578 Spartan Books Washington D C 1966
5 R C SINGLETON
An ALGOL convolution procedure based on the fast Fourier
transform
SRI Project ] 8] 53] -132 Stanford Research Institute Menlo
Park Calif January] 967 AD-646 628
6 R C SINGLETON T C POULTER
Spectral analysis of the call of the male killer whale
IEEE Trans on audio and electroacoustics Vol AU-]5 No 2
pp 104-] 13 June] 967
7 J W COOLEY J W TUKEY
A n algorithm for the machine calculation of complex Fourier
series
Mathematics of computation Vol ]9 No 90 pp 297-30]
April ]965
8 R C SINGLETON
On computing the fast Fourier transform
Communications of the ACM Vol 10 No 10 October 1967
9 R C SINGLETON
A method for computing the fast Fourier transform with
auxiliary memory and limited high-speed storage
IEEE trans on audio and electroacoustics Vol AU-]5 No
2pp9]-98June ]967
10 M C PEASE J GOLDBERG
Investigation of a special-purpose digital computer for online Fourier analysis
Special technical report No ] project 6557 Stanford Research
Institute Menlo Park Ca ifornia April] 967
]] G D BERGLAND H WHALE
Digital real-time spectral analysis
IEEE Trans on electronic computers Vol EC-] 6 No 2 pp 180] 85 April 1967
Further advances in two-dimensional
input-output by typewriter terminals**
by MELVIN KLERER ~ and FRED GROSSMAN
Columbia University, Hudso1l Laboratories
Dobbs Ferry, New York
INTRODUCTION
The purpose of this paper is to describe some new
applications in the realm of two-dimensional inputoutput by typewriter terminal. These applications are
extensions of the software and hardware system techniques covered in the references 1-4, 11-21. The principal elements of this approach consist of a versatile
programming language and a reverse-indexing typewriter equipped with a special character set. This set
permits not only normal alphanumerics but also the
construction of arbitrarily-sized symbols by the use of
a few interlocking primitive strokes. The reverse-indexing and indexing, together with spacing and backspacing,
allow full two-dimensional keyboard control of the
typed document. Typing errors are corrected by moving
to the desired point and overtyping, or by pressing an
"erase" button.
We have worked with computer input-output typewriter terminals primarily because of their ubiquitous
nature. Thus we have sought to demonstrate that a flexible computer language and input-output capability could
be made available with essentially conventional equipment. Nonetheless, where alternatives were possible, we
have chosen those directions which could be easily
implemented on more flexible (and more expensive)
devices. Specifically, all of the examples cited in this
paper could be implemented, using exactly the same
software techniques, on keyboard controlled cathode ray
tube displays designed for retentivity of alphanumerical
information. The use of red alphanumerics, easily available on a typewriter, could be effected in the black and
white tube by dotted or dashed characters (or a different
type style). The major limitation of the CRT is its relatively small visual working area; but a 20-inch carriage
The purpose of this language facility is to allow two
degrees of freedom for formatted printing of computed
labels. These are embedded in a two-dimensional construction. In order to keep within the user oriented
framework established in earlier work, we felt that the
output should be a literal image of the input. Further,
the relative location, numerical size, and numerical character of computed labels should be indicated by simply
"marking" the desired location rather than by counting
spaces and inputting coordinate information. The com-
* Present address: Department of Industrial Engineering, New
York University, New York, N.Y. 10453
**This work was supported by the Office of Naval Research
and the Advanced Research Projects Agency.
* An example of this statement was demonstrated at the 1965
FJCC in connection with the verbal presentation of the paper
cited in reference 16. However, it was not documented in that
paper or subsequent published work.
typewriter, similar to our own, could be used as an
accessory device. Essentially the same output techniques could drive a conventional paper-tape controlled
typesetter, photo-composition device, or a high speed
printer with a special character set. If extended subscripting and superscripting (indexing and reverse-indexing) are available as a hardware facility, then no
modification of the output methods is necessary. If
subscripting/ superscripting is not available, then the
order of output. can be modified to move left to right,
line by line. The final output would be the same. The
only difference is that the latter method takes more time
since unnecessary blank space must be scanned. Also
it is more critically dependent on the alignment of the
machine when inter1~cking primitive strokes are used to
construct large two-dimensional characters.12.13.16 Therefore, further development and extension of these techniques with a high speed photo-composition device can
be used to produce or edit documented programs, mathematical text, or text with displayed mathematical equations to a high degree of typographic quality, a good
deal of this process being automatic.
A two-dimensional format statement""
675
676
Fall Joint Computer Conference, 1967
mand to compute the required labels is exemplified by
the statement PRINT IMAGE N, X, Y, E, F, Z == G.
N is the numerical identifier for the IMAGE statement.
X and Yare variables which have been previously computed. E and F stand for arithmetic expressions to be
computed which themselves may contain two-dimensional constructions. That is, the expressions E and F
may contain superscripted or subscripted quantities, the
numerator over denominator form of division and the
integral, sum, product or square root operators displayed
as arbitrarily sized symbols. The artifice Z == G indicates
that the expression G is not. only to be computed and
printed but also should be stored as the value of the
variable Z.
An example of a format definition is
LLL LLLLLLL xxx.xx LLL LLL
LL
IMAGE N
LLLLLLL xxxxxX.xx LLL
L LLL
xx
L
LLLL
LLLLLLL xxxx LL LLLy
where the L's stand for any typable character or any
constructable symbol. A symbol, such as a constructed
arbitrarily sized sigma is interpreted as a summation
operator if it appears in the PRINT (image) command.
But if it appears in the IMAGE statement, which is the
format, it will be interpreted as a picture, not as an
operator. The picture linked with the summation operator could just as well be the drawing of a house. The
values of X, Y, E, F and G are the computed labels inserted where the lower case x's appear in the IMAGE
format statement. The number of lower case x's in each
set indicates the maximum (rounded) integer size or
the maximum number of digits to the left or right of
the decimal point. A lower case y indicates that a ,computed label in floating point notation is to be inserted at
the indicated location. The linkage between each set of
lower case x's or lower y's and the order of the computed labels (reading from left-to-right) is governed by
a precedence rule. The first computed label is inserted
into the location indicated by that set of lower case x's
(or lower case y) that are the left-most and highest. The
second compute.d label is inserted into the location
designated by that set of lower case x's (or lower case y)
that is the next highest at that columnar position or
next left-most.
The first line of Figure 1 illustrates a print image
statement. An integral, a sum, and a square root are
computed for various values of the parameter i. The
SLEW 5 phrase indicates that five blank lines are to be
inserted between each image. The several values of i
that appear in the PRINT image command are inserted
for format control so that the specific value of i used
for each image can be indicated in the pictorial output.
The second line of Figure 1 is the two-dimensional format statement and indicates where the computed labels
are to be placed. The third line of Figure 1 is the output
of the program for the parameter i == 2. The fourth line
is the output for i == 3, and so on. The upper part of
Figure 2 represents an edited version of this program
when operating in an on-line, interactive mode. The
original PRINT image statement has not been altered.
However, the IMAGE 1 format has been replaced by
another. A drawing of a "house" has been substituted
for the integral symbol, a box has been circumscribed
about the summation symbol, and the square root sym.bol has been replaced by another indiosyncratic version.
Also the last computed label has been changed to fixed
point (x's), rather than floating point (y). The lower
four lines of Figure 2 represent the output of the new
IMAGE for the values i == 2, 3, 4, 5 respectively.
Figure 3 represents the input and output of a program
run in an on-line interactive mode. The program input
in the upper part of the figure is terminated by the word
FINISH. The word INPUT is typed by the system indicating that it is ready to accept input data. The numbers
that follow, 12, 2.5, 10, 3.5, 6 are the first set of values
for V, R 1 , R 2 , R3 , and R4 respectively. The lower part
of Figure 3 is the program output where computed labels
have been inserted into the two-dimensional figure. The
program will then request a new set of input data and
output another figure with new values.
Editing two-dimensional programs or text
One way of editing programs is by inserting or deleting entire statements or statement segments under control of such editing instructions as EDIT, INSERT,
DELETE, OMIT, LIST, etc. For a programming language that is restricted to short statements, such an
approach might be completely satisfactory. However,
although such commands are permitted in the basic
system,12.13.16 they do not prove to be as satisfactory as
they would be for the more restrictive languages. This is
because the basic language allows quite long statements
that may extend over several lines (a maximum 18-inch
typed line is possible on our Flexowriter model 13 inches
on our Selectric model) and permits complex twodimensional constructions. Therefore the need was felt
for an editing technique that would allow character editing as easily as statement editing while still keeping full
two-dimensional control for character or constructed
symbol insertion. In keeping with the user oriented
approach of the original programming system, the technique was designed to minimize the number of necessary
formal conventions.
A first veri son of this special editing program is now
operable in an off-line input mode. Therefore all subsequent remarks in this section will refer to a procedure
Further Advances in Two-Dimensional Input-Output
677
1
rROM 1-2 TO 5 SLEW 5, PRINT IMAGE 1,1,1,1,
A1-~
e
-1z SINH-1 .!
2 dz, 1,1,1,
z5+ .1
o
2
IMAGE 1
dz - .xxxxx
5
dz - .12922
dz - .07884
dz - .05161
dz -
.03577
Figure 1
where the original program (or any textual material)
has been typed and removed from the terminal to be
proofread or compiled. The editing begins when the
original document (the typed program) is re-inserted
into the terminal and the editing marks and new text are
typed. The typing process also produces a paper tape.
When the editing operation is finished, the paper tape
representing the original document is read into the system, followed by the paper tape representing the edit
operation. The output of the system is a paper tape
representing the edited program or text or, at the user's
option, output may be directly on-line to the typewriter
terminal. The paper tape may be reproduced as a document on the typewriter terminal or compiled as a program. The same technique, in principle, can be extended
to an on-line, interactive mode. We have not yet done so
purely for practical reasons,' such as a relatively small
memory in the available computer.
After the user inserts the original document (program
or text) into the typewriter, he moves the platen by
keyboard control to the first typed character of the
document. He types a red underline which serves as a
reference point for any subsequent scanning. If he
wishes to insert a new character, word, phrase, or statement, he simply types them just where he wants themif there is blank space available. To change any characteres), he can overtype with the desired character(s).
Should he wish to delete any character(s), he positions
the platen over the character and either presses a special
"erase" button or overtypes with a red lower case or
678 Fall Joint"Computer Conference, 1967
upper case x. To delete an entire statement he need only
type a red slash anywhere in the statement. The typing
sequence for' any of these actions is arbitrary.
However, there are many programs or texts that do
not offer enough blank space in which to type the new
characters(s), phrases, or statements desired. But there
may be room in the margin, at some other place in the
program, and certainly, always at the extensible "bottom" of the document.
Thus, to indicate the exact location of an insertion,
the user types a red vertical. The basic cl),aracter set has
been designed to that the vertical stroke always falls
between any two contiguous alphanumerics, so there is
no possibility of an ambiguous location. Regardless of
how the rest of the red insert mark is extended, vertically or horizontally, the position of the first red vertical
determines where the left-top-most new character will
be inserted. The right-most point of the new insert
(relative to the left-top-most character) is determined
by a red slash which also acts as the terminator of the
wtiAT MOOE
EDIT.
READY
REPLACE A20.
IMAGE 1
HOUSE x
.-7[0
~
1
- 1 xxxx
~2
ROOT x 2+1
- 1 x.x.xxxxx
FINISH.
HOUSE 2
~
HOUSE 3
~
HOUSE 4
~
HOUSE 5
~
2-7[0
1-1
\
J
--/
L0
[0
5-7[J
4-1
1-1
-1
G
1
2
5
ROOT 22+1
36
ROOT 32+1
354
ROOT 42+1
0
4425
ROOT 52+1
E12 ---1
---1 2.236068
1
---1
---1
---1
Figure 2
~2
1
2
---13.162278
---14.123106
1
5.099020
Further Advances in Two-Dimensional Input-Output 679
xx VOLTS
r--------f
'MAGE 1
11I1I111
t----_
xx.xx OHMS
xx.xx AMPS
R-
1
L+-1.+-1.
R2
I_Y...
1
r
• v-Rxl 1 •
12=
R3
R4
V/R2 , I3-V/R3 , '4-V / R4.
PRINT IMAGE 1, R1 , 'II V, R2 , 12 , R , 1 , R4 , '4 AND SLEW 10.
3 3
GO TO STATEMENT 1.
fiNISH.
INPUT 12 2.5
10 3.5
6
12 VOLTS
.----~
IIIIIIII
t--------,
10.00 OHMS
Figure 3
insert operation. Thus an insert construction consists of
any figure constructed with an extensible red vertical,
an optional extensible red horizontal and a terminating
red slash. In order to increase flexibility and ease of use,
leading blank spaces of the insert are ignored, but trailing blanks are entered into the edited program or text.
This permits bringing the new character(s) into the
margin but still giving control over space adjustments at
the point of insert. Should the user change his mind
after starting an insert, he can "erase" the current process by overtyping the first red vertical with a red slash.
Should he change his mind while in the process of typing
a new statement in a previously blank area he may cancel this by typing a red slash anywhere within the cur-
rent typing. Should he wish to type the new character(s)
elsewhere in the program or text, he may type INSERT
N or just N within the insert mark. N is any red number
from 0 to 9999. The actual insert may then be typed
anywhere on the page as long as it is preceded by the
declared insert number. Of course, any specific insert
may be referenced as many times as desired.
To delete a two-dimensional area, two extended red
vertical lines are constructed. The deleted area is defined
as being bewteen the two verticals. A red slash in this
area initiates deletion. (Strictly speaking, the lines need
not be equal. The deleted area is defined by ignoring
the extension of one line higher or/lower than the other.)
For a lengthy program, there is always the possibility
680 Fall Joint Computer Conference, 1967
of the paper getting out of alignment after it has moved
large distances from the initial red underscore. To prevent this possibility, the user is advised to occasionally
type over any black letter in the text with its red equivalent, except for the letters X or F. This will enable the
system to'make automatic realignment adjustments. The
red letter X, lower case or upper case, is reserved for
erasure and red F is used to tenninate the edit operation.
Some of the possible editing techniques are illustrated
in Figures 4A, 4B, 4C, and Figures 5A, 5B, 5C. In each,
(A) represents the original program, (B) the pr:ogram
with the edit marks and new characters and (C) represents the final program output of the system.
In Figure 4B, at (1) and (4), new statements are
typed directly into the desired locations. Insert marks
are used at (2) and (3) where there is no available
space to type directly. The actual insert designated by
fUNCTION G(x)-
ISI~¥ I .
fROM n=-l BY .2 TO 20
insert 5 at point (3) is typed (point 5) at the bottom
of the sheet. At point (6) a statement is deleted by typing a red slash. Characters are inserted by typing where there is room (7) or by using any of the
insert marks shown. The insert mark may be freely
extended horizontally ( 8 ) or vertically (9) and the
actual insert may be typed anywhere above the horizontal line, leading spaces being ignored. The tenninating red slash need not come at the end of the horizontal
line (8), (2), therefore not restricting the user to a neat
or sequenced construction. Further, the mark may point
in any direction (9). At point (10) characters are
deleted by "x-ing" out and at point (11) the area to
be deleted is enclosed between extended vertical lines.
Note that at point (12), the "FINISH." statement has
been deleted. Since the language system requires a
"FINISH." statement to complete the compilation pro-
SLEW TOP.
AND raO TO 4,
N-
INTEGER PART (lOA),
N
50
~
f(u)G(u)SIN
u
~u
G(u)
+ L(f(k)-G(k)
kwI
PRINT n,A,S.
fiNISH.
u-O
Figure 4A
o
®
w.x IMUM N=200.
[UNCTION G(x)-
I
SIN ~x
9f.
rROM n--1 BY ... TO
~x
I
•
SLEW TOP.
A
~
f
-11- ~ fRACT 10NAL PART ~ 1. ;1.. ... , •
c/!l~R
1 '\- ;- G(ky)dy fIJi['" 1<-0 TO N.
"!0
--
roO TO 4.
fUNCT ION f(x)
-IT
\!)
TH N
CyL
"(u) ""!u
k-1
~
"'10" ..... INTEGER PART (lOA),
JooO(l)N •
\!)
~
.
I
.... ,
f,~ISH.
+
@
®
I6A X-LOG A, PLOT P,X,0,2.1.
p- ;:j'
5lT0
5 ( If ~Q THEN Q-N AND ( fROM J-O TO N, ( If fRACTIONAL PART ~ -0 THEN CJ-I AND OJ-O ELSE CJ-O AND OJ-I))),
Figure 4B
I
,
Further Advances in Two-Dimensional Input-Output
cess, the edit program will supply such a statement if
the user forgets (Figure 4C).
In Figure 5B, point (1) shows that inserted characters are referenced by typing INSERT 24 and at point
(2), just the number 10 is typed inside the edit mark.
The actual inserts (points 3) may be typed anywhere
on the page. Insert 10 has been referenced twice (2).
The statement fragment at point (4) has been deleted
by typing a red slash and was retyped at point (5). This
statement was later re-edited at (6) where as many
blank spaces as there are between the vertical and the
slash of the insert mark are inserted into the final statement (as shown in Figure 5C).
In keeping with our general philosophy for educating
programmers and intermittent users, we have always
tried to produce "one-sheet" instruction manuals. Figure
9 is the one-sheet instruction manual that we are presently distributing to our in-house users of this editing
technique. As with our previous manuals, the intent has
been to eliminate the thick, and often-times incomprehensible, text supplied with many conventional systems.
Hopefully, as we extend our work more into the realm
MAX I MJM N-200.
fUNCTION G{x)-
SIN
I
¥
1rX
I
A
•
SLEW TOP.
I
fUNCTION f{x) _ 1-
~ fRACTIONAL PART 2~X
fROM 0--1 BY .02 TO LOG 20
I·
AND r-O TO 4, (If n--l THEN
B- ~2r),
A-10n,
N- INTEGER PART (lOA),
..
P- 16A3' X-LOG A, PLOT P, X, 0 , 2 1
S1r
fiNISH.
Figure 4C
SLEW TOP.
fUNCTION
X(~).
ISo.
fROM 6=0 UNTIL SIN
X{~) < TAN
i ~ ~~:l
x{e)
Z~ ~ .-auv
COS [ LN
681
SIN u + TAN u
SIN v - TAN v
o
fiNISH.
Figure SA
]
dudv AND PRINT S,Z.
682 Fall Joint Computer Conference, 1967
of truly interactive (man-machine) systems, even this
short list of instructions will be replaced by immediate
system responses to indicate if the user's communication
has been correctly understood.
recognize mathematical expressions, even when they are
not typed according to a restricted syntax or in a neat
format. These basic techniques may be extended to
manipulate and format mathematical text. One of us
(M.K.) is directing an effort to produce a table of integrals whose accuracy has been verified by various computer strategies. The algorithms used for the verification
Automatically edited mathematical text
The original programming system was designed to
SIN u + TAN u
SIN v - T v
]r
fORMAT 1
v
AND PR I NT
2~
,.z..•.
..
_ ..........t..f~QBMA:.=.IU...
T .....1...''''''·_
J.®
fI~USH.
·
..
r
.·
.
TH~@
fUNCTION f(x,y)- SIN x ~OS
y
xy
(!)
or
THE VALUE
fORMAT 1
THE
INTEG~ THE~ -xx.
IoIiEN
fiNISH.
Figure 5B
SLEW TOP.
fUNCTION X(~)-
ISo ·
fUNCTION f(x,y)=
SIN x COS y
xy
2
fROM 8=0 BY 2 UNTIL SIN
X
(O)
z-
7
o
fORMAT 1
lOX
(D)
-auv
e
X(~) < TAN ~
0051
[
:
~~~~ $1
LN f(u,v)
f(8,X(O»
1
SIN u + TAN u
SIN v - fAN v
J
I r(D,X(D» I
0
THE VALUE Of THE INTEGRAL.y
WiEN THETA -xx.
fiNISH.
Figure SC
dudv
AND PRINT fORMAT 1 e,z.
Further Advances in Two-Dimensional Input-Output
of integrals will be treated elsewhere. However, it is the
purpose of the present note to point out that the techniques of the basic programming system and its recent
extensions permit the input of matnematical text in a
relatively free (and sloppy!) form. This text, in its
internal representation, may be compiled for computation or manipulated symbolically to produce a neat
form suitable for output and photo-reproduction. The
essential point here is that these techniques permit adequate "typesetting" of mathematical text by relatively
unskilled typists. Figure 6 represents input of five indefinite integrals. These have been typed so that numerators are not centered over denominators, portions are
offcenter, and excessive or inappropriate spacing has
teen used. Figure 7 represents the output of a program
that has automatically manipulated these expressions
into a format suitable for photo-offset reproduction. As
is illustrated in Figure 7 (E), the program will automatically break up those lines of text, which are too long
(A)
/
(a2 +x2 )2(~
x'"
(e)
for one line, at the mathematically appropriate points.
In the basic programming system and in each of the
above extensions, the user may type in any sequence.
That is, he may arbitrarily space, backspace, superscript
(move up), subscript (move down), overtype or output
a code which indicates that an erasure is to be made.
Thus he inputs an arbitrarily ordered string of primitive
characters. This string must be reconstructed internally
to correspond in some fashion to the typewritten document. The arbitrarily-sized (and possibly asymmetric)
symbols must be recognized. Although the scanning of
computer-stored text can be formalized as transformation rules on linear character-strings, we have found it
convenient to consider the text's core image as _a literal
two-dimensional graph. The basic techniques for scanning along connected paths of the graph and through
its nodes and along branches are simple and have been
treated elsewhere.11·15.11.2o Thus manipulations such as
the elimination of unnecessary blank space can be ac-
dx
+
x
a2'2~2+a2}
2(~2+a2)2
LN (
a 2+x2
+
Ir
)
(C)
(
(
- a LN
a+x
I ---a:xI ).
6e3
+
3e
-'iT ).
Ie
(D)
683
1
1
(E)
J
~
1 dx
-x....5-(....
A2.....
_X...,,2~)~31~2~
+
Figure 6
1~7
LN
I
A+(A2_X2}1/2
x
I ).
684
Fall Joint Computer Conference, 1967
(A)
(B)
(c)
(D)
J /'
J
(A+Bx)3
3
kx
1 kx «A+Bx) 3 _ '38 LA+8x)2 + 6B2 (A+BX) _ 6B )
e
dx - k e
k2
k3
/ ' 1S TANH- 1 ';A dx
x
a:
4:. (l.r, _ ~) TANH- 1
...
A'"
x'"
~
1
1
- 12Ax3 - 4A 3x
Figure 7
complished by straightforward testing and commands
which move only one character at a time. Since one is
always working with a literal picture, at least as far as
the system programmer is concerned, there is never any
question of hidden coding ambiguities. The only question is whether the programmer has been clever enough
to anticipate enough practical situations so that the
system as a whole can be considered viable. Systems,
such as these, are based on an ad hoc assemblage of
straightforward strategies and are highly dependent for
their success on the insight of the implementer and a
correct assessment of the psychological traits of the
user. Our experience has been that such systems can be
brought rapidly to a state of working practicality in a
relatively short period of field testing among uncommitted users.
Usage in programmed instruction
The field of Computer Assisted Instruction seems to
be on the verge of a rapid expansion. One approach has
been to use typewriter terminals with or without film
projectors or CRT displays. Regardless of one's position on the feasibility or advisability of this kind of
mechanical instruction, it would seem that capability for
adding another degree of freedom for textual output can
only improve the result. Since this can be accomplished
at minor cost, it would seem a valuable extension to any
such system. This would permit the construction of
symbols and certain types of restricted "drawings" without increase in hardware complexity and with the use of
programming techniques that have already demonstrated
their feasibility.
Figure 8 is a fragment of a programmed lesson in
differential and integral calculus which was written in
the basic programming language. Essentially the student
is offered a choice of three answers. He types his choice
after the system types the problem" and the word INPUT.
If his answer is correct the system goes on to a problem
of a different class. If his answer is wrong, it informs
him which general formula is applicable to the problem
and then outputs a similar example but with different
parameters. It will keep varying the parameters on subsequent examples until a correct choice is made.
CONCLUSION
The point we wished to demonstrate in these various
implementations is that it was possible to develop these
perhaps elaborate methods using a relatively small com-
Further Advances in Two-Dimensional Input-Output
685
TYPE THE NUMeER Of THE CORRECT ANS\£R AfTER THE 'ftORD INPUT IS TYPED
d 9
dX X -
(1) 9Xa -OR
(2)
ax9
(3)
OR
axa
INPUT 1
- YOUR ANSWER IS CORRECT
X4dX _
/
(1 )
X3
"3
(2)
OR
X5
5
OR
(3)
x4
5
INPUT 3
WRONG, TRY AGAIN BUT REMEMBER THAT THE GENERAL fORMULA IS /
OR
OR
(3)
xn
dX =
X::~
f
INPUT 2
YOUR ANSWER IS CORRECT
d 6 X
dX X e =
.INPUT 3
YOUR ANSWER IS CORRECT
Figure SA
/ ' SIN 3X COS
x dX
-
(1)
~
OR
(2) SI~
2
x
OR
INPUT 1
YOUR ANSWER IS CORRECT
~ COS7X S IN 7X - (1) COS 6X SIN6X (SIN x + COS x) OR (2) COS 6X SIN6X (7 COS 2x - 7 SIN2x) OR (3) COS8X SIN8X (7 SIN x ~ 7 COS x)
INPUT 2'
YOUR ANSWER IS CORRECT
~
(1!X)6 INPUT 1
(1)
(1::)5
OR
(2)
(1!X) 1
OR
(3)
(1::)7
~G. TRY AGA IN BUT RE'·IFJ·eER THAT THE GENERAl F'ORHJLA IS ~ ~.
dX (l+X)ft
d
ax
1
(1+X)3
-
(1
)-=.L
(1+X)2
OR
(2)
~
(l+X)
OR
(3)
~
(1+X)
INPUT 3
YOUR ANSWER IS CORRECT
Figure SB
=D
(1+X)n+1
686
Fall Joint Computer Conference, 1967
(Sh4d~d
Special Edit Program
Operational Version 2 - December 1966
eh4~4et~~~ indie4t~ that thty 4~~ to b~ typ~d in
~~dl
The purpose of the edit program is to provide a character by character editing facility at the Flexowriter. The
original program document which is to be edited is inserted into the Flexowriter. Do not turn the platen .anually!
Initialize the edit operation by typing a
~
underscore under the first character in the program*.
'To insert characters. phrases or statements. type them in the desired location.
To change any character(s) in a statement merely overtype with the desired character(s).
To erase any character in the statement. press the special erase button when positioned over the character or overtype
with a red upper or lower case x. To erase a period. overtype with a red x. To delete an entire statement. type a red
slash anywhere in the statement. (These may then be overtyped with the desired characters. phrases. or statements.)
Where there is not space to type directly into the program. an insert construction may be used. An insert construction
consists of ~ figure constructed with an extensible red vertical. an (optional) extensible red horizontal. and a
terminating rea slash.
LLLLI
. TE~rt TEXT
LLLLLLl
..llkLJ
TEX
~
The first (in time) character typed in these constructions is a red vertical. The location of this red vertical
determines where the left top-mo~t character 1n the insert will se-located 1n the program. The last-rIn ti.e)
character typed is a red slash which determines the right-most point of insert and terminates the insert.
LLLL represents any typabre-cnaracters.
Blanks may be inserted by using only those "empty" constructions where the slash is to the right of the vertical;
the length of the blank will equal the empty space between the vertical and the slash.
Lhadin! blanks to the first insert character are ignored but, trailing
t e re iI"iiJlare~.
~
between the last insert character and
Example:
-~
o
F(x)dx
it
J
I
A-B
Insertion may be made or repeated by using the construction
IJ
-
,: i:,,,,.,.·I:l·
F(x)dx
+
C •
o
or
I
I·;';~
where
O~.9999.
The insert may be typed anywhere on the document as
LLLLLLLLqI (L stands for any typable character).
the insert or insert construction may be typed first and an insert may be referenced any nu.ber of times.
Exa.ple :
A=B+C.
o-~t·. .,::. ~. .
X-Yo FINISH.
_'" ,.HSEftT 1-1/ .' ,:
. - SIN
The program from this edit operation would then be:
Either
X.
A-B+C. O-E -
SIN
X • F-G - SIN X-I. X-Yo FINISH.
To ~ancel the process of typing a new statement. type a red slash anywhere within the current typing. To erase an
insart before typing a red Slash. overtype the first red vertical with a red slash. [Once the insert is terminated,
no further edit modifications may be made in the insert. Insert constructions may not be located above or below an
underscore.] '(The bracketed restrictions will be removed in the next program version.)
To delete an area from the progra.:
I~I
Note:
Only tho shaded area is deleted.
The area to be deleted is enclosed between red vertical lines and the deletion is terminated by a red slash typed
in the two-dimensional statement between the verticals. (Only portions of ~ statement may be deleted at a time.)
The edit operation is terminated by typing a red F. If the edit operation is terminated and the program does not
contain a "FINISH." statement, the edit program will insert "FINISH." after the last statement in the program.
In order to maintain proper vertical alignment, the user should realign the edit operation every few lines by
overtyping in red any black ~, except F, X, x.
* When inserting the program page into the Flexowriter. possible horizontal skew .ay be tested by overtyping near the
be,inning and near the end of the first or subsequent lines before initializin,.
Figure 9
Further Advances in Two-Dimensional Input-Output
puter (a GE-235). The extensions were particularly
easy to implement by building on the assets of the basic
programming system.
ACKNOWLEDGMENT
We extend our thanks to Jack May who participated
in the development of the IMAGE statement and to
Charles Amann for his asSistance with the hardware
aspects of this system.
14
15
16
REFERENCES
2
3
4
5
6
7
8
9
10
11
12
13
C AMANN M KLERER
Flexowriterl DIOA system
Columbia University Hudson Laboratories Technical
Report no 124 Defense Doc Cntr Acq No 635 229
February 1966
C AMANN M KLERER
Documentation of a general purpose paper tape reader
Columbia University Hudson Laboratories Technical
Report no 125 Defense Doc Cntr Acq no 635 379
March 1966
C AMANN M KLERER
Hardware documentati.Jn of a 127-buttoll accessory keyboard
Columbia University Hudson Laboratories Technical
Report no 126 Defeme Doc Cntr Acq No (pending)
C AMANN M KLERER
Hardware documentation of an 8-button keyboard
Columbia University Hudson Laboratories Technical
Report no 127 (in preparation).
K G BALKE G CARTER
The COLASL automatic system
Dig Tech Papers ACM Natl Conf pp 44-45 1962
A J T COLIN
Note on coding reverse polish expressions for singleaddress computers with one accumulator
Comput J vol 6 pp 67-68 1963
H J GAWLIK
MIRF A C: a compiler based Oil standard notation and
plain English
Comm ACM vol 6 no 9 pp 545-547 1963
A A GRAU
The structure of an ALGOL translator
Oak Ridge Natl Lab Rept 3054 February 1961
M GREMS M 0 POST
A symbol coder for automatic documenting
Comput News vol 147 pp 9-18 and vol 148 pp 15-19
1959
C L HAMBLIN
Translation to and from polish notation
Comput.J vol 5 pp 210-213 1962
M KLERER J MAY
Algorithms for analysis and translation of a special set of
computable mathematical forms
Columbia University Hudson Laboratories Technical
Report. no 113 Defense Doc Cmtr Acq no 601 981
October 1963
M KLERER J MAY
An experiment in a user-oriented computer system
Comm ACM vol 7 no 5 pp 290-294 1964
M KLERER J MAY
A user oriented programming language
Com put J vol 2 no 2 pp 103-109 1965
17
18
19
20
21
22
23
24
25
26
27
687
M KLERER J MAY
Automatic dimensioning
Comm ACM vol 10 no 3 pp 165-166 1967
M KLERER J MAY
Recognition of arbitrarily sized and asymmetric typed
symbols
Columbia University Hudson Laboratories Contribution no 232 July 1965 To be published
M KLERER J MAY
Two-dimensional programming
Proceedings of the FJCC 1965 vol 27 part I pp 63-75
Spartan Press Washington DC
M KLERER J MAY
Program documelltatio1l of a user-oriented programmi1lg
system-part I
Technical
Columbia University Hudson Laboratories
Report no 118 Defense Doc Cntr Acq no 635 325
January 1966
M KLERER J MAY
Program documentation of a user-oriented programming
system-part II
Columbia University Hudson Laboratories Technical
Report no 119 Defense Doc Cntr Acq no 655 340
January 1966
M KLERER J MAY
Program documentation of a user-oriented programming
system-part III
Columbia University
Hudson Laboratories ContribuReport no 120 Defeme Doc Cntr Acq no 635 339
January 1966
M KLERER J MAY
Program documentation of a user-oriented programming
system-part IV
Columbia University
Hudson Laboratories Technical
Report no 121 Defense Doc Cntr Acq no 635 341
January 1966
M KLERER
Hardware documentation of a user-oriented programming
system
Columbia University Hudson Laboratories Technical
Report no 123 Defense Doc Cntr Acq no 635 330
January 1966
J H KUNEY ET AL
Computerized typesetting of complex scientific material
Proceedings of the FJCC1965 Spartan Press Washington DC
Los Alamos Scientific Laboratory
MANIAC II
Comm ACM vol 1 no 7 p 26 1958
W A MARTIN
Syntax and display of mathematical expressions
Project MAC Memorandum M-257 MIT 29 July
1965
M B WELLS
MADCAP: a scientific compiler for a displayed formula
textbook language
Comm ACM vol 4 pp 31-36 1961
M B WELLS
Recent improvements in MADCAP
Comm ACM vol 6 pp 674-678 1963
A V ANDERBURGH
The Lincoln keyboard-a typewriter keyboard designed
for computers input flexibility
Comm ACM vol 1 no 7 p 4 1958
A graphic tablet display console for use under time-sharing
by L. GALLEN SON
System Development CorporatIOn
Santa Monica, California
INTRODUCTION
The RAND Tablet, a graphical man-machine communication device, is potentially one of the more
fruitful approaches for two-dimensional graphic input
to a computer. The high resolution of the tablet, high
data transfer rates, and ease or "naturalness" of use
are its chief assets. These same characteristics, however, give rise to the major problems in designing the
tablet/computer interface. These problems are amplified when the interface is with a multi-accessed, timeshared computer.
A graphic tablet display (GTD) console has recently been designed to operate with the Q-32 TimeSharing System (TSS) at System Development Corporation. The successful completion of the task has
provided new insights into system design problems
involving highly interactive consoles in a time-sharing
environment; some interesting innovations in the
design of a graphic tablet console; and some solutions to graphic tablet interface problems.
The TSS at SDC has been well documented. 1
Understanding the operation of the graphic tablet
display console does not necessarily require a complete understanding of TSS. Suffice it to say that
TSS affords the capabilities of a large digital computer
simultaneously to a number of users, each of whom
assumes he has the full capabilities of the computer
system.
For the typical TSS user's console-a keyboard/
printer - to be considered interactive, it must receive
some response from TSS in fractions of a second, and
a certain amount of computational response within
several seconds. With the graphic tablet display console, however, TSS reaction time must be on the order
of a few milliseconds, and computational response on
the order of one second. The high data transfer rates
and the speed of response required for user psychological reasons demand that the user-to-system
interface be "tightly coupled."
The trend in modern computer system design is to
provide external I/O buffers for CRT and graphic
consoles; thus data is not readily accessible to the
object (user) program. Typical systems require block
transfers of all the data from the console into main
core for processing, maintenance of the complete
image of display tables within the user's core space (or
complicated algorithms for regenerating the tables),
and finally, block transfers back to the I/O device. In
designing an interface for a highly interactive console
to these computer systems, the I/O transfer time can
become an appreciable portion of the required interaction time. The system configuration described in
this paper provides an I/O buffer area in core memory
that is directly accessible to both the central processor
and the console, thus placing the data in a display
buffer very "close" to the object program.
TSS/GTD general system description
The major components of the Time-Sharing System (TSS) are the AN/FSQ-32 computer, a PDP-l
computer, and the time-sharing executive. The Q-32
is the main processor; the PDP-l serves as an I/O
processor for all the interactive I/O devices. The two
computers are coupled via a core memory, called Input Memory (1M), which is part of the Q-32 and is
directly addressable by both computers. 1M is a core
bank identical to the other Q-32 main memory
modules (16,384 48-bit words with a 2.5-J,Lsec cycle
time). It is accessed by the Q-32 for reading or
writing data, but programs cannot be executed from
it. TSS protects 1M with write-protect logic from the
Q-32; therefore only the executive can write into 1M.
To the PDP-I, 1M appears as 32,768 18-bit words
of main memory extension (since the PDP-I has 18bit words). Thus, 6 bits per half word of 1M are
potentially lost to the PDP-I. To avoid the loss of
memory capacity, two special instructions - "load
byte" and "deposit byte" - have been added to the
689
690
Fall Joint Computer Conference, 1967
PDP-I. These instructions allow the PDP-l to access
all of 1M with 6-bit bytes for data fetch and store
cycle~. Using an I/O preprocessor to store data in a
core buffer that is directly addressable by the main
processor has proven to be a powerful device for implementing TSS, and has facilitated the interfacing
of the graphic tablet display console.
The PDP-l initiates service to all interactive consoles in response to an interrupt from the console.
The processing of the interrupt causes the execution of routines unique to the class of console requesting service. In general, the routines transfer
the data in or out, buffer the data, translate to appropriate codes, examine the data for end-of-message
cues, and inform the Q-32 of user requests.
The use of a separate processor for all interactive
data I/O for TSS has given SDC the ability to interface a large variety of devices with TSS. These include
teletypes, special keyboards and typewriters, lightpens for displays, special pushbuttons, high-speed
data lines for computer-to-computer communications,
automatic dial-up units, as well as the graphic tablet
display console. To provide quick response time to
the user of the GTD console, the PDP-l performs a
significant amount of preprocessing on the raw data.
A project is currently underway to study the tradeoffs of allowing the slower PDP-lor the faster Q-32
to perform the required user functions. Although the
user cannot directly modify the PDP-l executive
interactively, a system programmer can modify it to
meet new user requirements.
Figure 1- Graphic tablet display in operation
POP-, COMPUTER
INTERFACE
Accumulator
Program
Counte,
I/OR-eitf.,
I
I
I
I
Operation ofGTD console
The operation of the GTD console in TSS can best
be described in the context of a user of the console.
One such user at SDC is involved in a research program that is attempting to provide on-line computer
recognition of characters written on the RAND Tablet. 2 The user can draw, or print, characters and observe the "inking" on the tablet surface (see Figure
1). After removing the pen from the tablet, TSS resp'onds by displaying the symbol(s) as interpreted by
the object program. This process is performed by a
hardware/software interface between' the GTD console and the TSS (PSP-l). Figure 2 depicts the major
data paths to and ffom the GTD console.
Hardware operation
Inputs to the PDP-l are initiated by interrupts from
the console to the sequence break system. The interrupt causes the PDP-l to execute routines for preprocessing the data from the console. A variable
strobe clock (which determines the interrupt rate of
INPUT MEMORY
-,,
,
I
I
I
I
To Display
Figure 2-GTD console interface block diagram
the tablet) is provided to minimize the buffering and
processing requirements. A 2- or 4-millisecond rate
(500 or 250 points-per-second) is adequate for present
users at SDC. A second oscillator (30 Hz), effective
only when the pen is up, also initiates interrupts to
the PDP-l ~o that pen coordinate data for positioning
information and pen switch time-out can be processed.
All interrupts from the console are ignored by the
software if the display is not being used or if an object
program using the console is not loaded in TSS. Input
data are preprocessed by th~ PDP-l and stored in
the display core buffer located in Input Memory
Graphic Tablet Display Console
(1M). The display buffer is continuously read by the
display control logic; thus immediate visual feedback
is given to the user.
The display portion of the console interface consists
of memory access logic to 1M, data transfer lines, and
priority logic to handle PDP-l and display memory
access conflicts. The memory access logic is essentially a counter, modulo 2048, stepped for each display
word cycle. The counter is used to step through the
core address within the block of 1M dedicated to the
GTD buffer. The average display word cycle is 15
microseconds or 30 milliseconds per display frame.
The display uses 24 bits of the 48-bit word in core
(two display words per 1M word) for each display
cycle, so that gating is provided to transfer the proper
half word to the console. The address counter is also
available to the I/O register of the PDP-I, so that
when using the stylus in the "light-pen mode," the
address of the displaye4. data is made available to the
user.
The display buffer is 1024 words (48 bits) of core in
1M and contains the processed display table, the
stylus input data, as well as several control words and
indicators. For example, the pen input contains coordinate data which are displayed in the left 24 bits; the
point-count, start-of-segment indicator and other control bits are in the right half word. The user has control of almost all the 2,048 display words available
within the table, and determines how the buffers are
divided between the stylus inputs and display.
The 1M has three potential users: the Q-32 central
processor, the PDP-I, and the display, so that logic
is required to control the traffic problem. A priority
scheme of CPU, PDP-I, and console (highest to
lowest) has been established, and no device is capable
of usurping all the core cycle time. Actually, programming conventions for the PDP-I and the Q-32 are
such that the problem of one device requiring COIitinuous service from 1M is never encountered. The
priority logic is required, however, to take care of
simultaneous requests for core memory.
Software operation
Processing for the GTD is initiated by an interrupt to the PDP-I for pen tracking or pen data inputs
(see Figure 3). Pen tracking occurs at a rate of 30 Hz
while the pen switch is open. The x and y positions of
the pen are read and placed into one register of the
buffer table. Pen data inputs occur while the pen is
in use (i.e., the switch is closed). The functions performed by the PDP-l in preprocessing the raw data
are as follows:
691
1. Filtering: a point must move at least 3 increments
in x or y before it is called a new point; 500
points-per-second are examined.
2. Point count: a count of the number of times a
point remains within the filter window is stored
with the point coordinates.
3. New stroke: setting a control bit within the display word indicates that the point is the start of
a new stroke.
4. Min/max: each stroke is described with an x and
y minimum and maximum at the end of the
stroke. (This feature is available in one version
of the PDP-l program, but is not shown in
Figure 3.)
5. "Inking": new pen data are placed in the display buffer in an appropriate format for displaying.
6. Pen up/down: the tablet is read periodically to
determine if the stylus is in use.
7. Smoothing: new pen data are averaged over the
last eight inputs, prior to filtering.
In addition, a certain amount of bookkeeping of the
display buffer is performed. The processing of pen
data consumes 30 percent of PDP-l time when
reading 500 points-per-second. The PDP-I time required for pen tracking (pen up) is insignificant.
Further preprocessing capabilities will be introduced
into the software as requirements dictate, for example,
the capability of selectively erasing a single point or
character on command from the user.
When input from the GTD is complete, the PDP-I
alerts the Q-32 executive to request processing. Completion is noted by either of two events: (1) when the
tablet buffer is full (no "ink"), or (2) when the pen
has not been used for a predetermined period of time
after an input. The Q-32 executive then schedules the
user's object program. The processing of the data is
performed by the object program directly accessing
the data in 1M.
At the completion of the processing by the object
program, the display table is updated. New display
information is added, deletions are made, and the control words are reset. The Q-32 executive must transfer the table from main core to 1M, since the 1M is
write-protected from all users (a number of sensitive
tables and data for TSS also reside there). The display table contains control words used by the PDP-l
program. These include a pointer to a starting address
for the input of new pen coordinate data, and an octal
number (from 1 to 37) representing the delay time in
~ seconds that the pen is allowed to be inactive prior
to an input-complete signal.
692
Fall Joint Computer Conference, 1967
Read X, Y
Nent- Buffer
Nent-O
N up-- Nup + 1 1------<
Set Flag
--
~T
1
=
0
INK = 0
Initialize
Addressing
Zero Up Count
YES
L: Xi = Xn
-8L: Yi = Yn
-8-
Flag -- 1
Cnter--O
i -- i +
1
Set Smoothing
Table
x --
Xi
Y
Yi
-
i - 0,8
x, Yn -- Buffer
N ent -- N ent + 1
lac
- lac + 1
Figure 3 - PDP-l preprocessing flow diagram
G T D console components
The graphic tablet display console (see Figure 4)
consists of a RAND Tablet (Grafacon Model lOlOA
built by Bolt, Baranek and Newman),* an input stylus,
and an oscilloscope and lens system for rear-projecting the CRT image on the tablet surface. The
rear-projection technique was originally suggested
*Graphic tablets are also currently available from other vendors.
by the inventors of the RAND Tablet- Davis and
Ellis3 - and was developed at SDC. It produces the
effect of a "live piece of paper," which was the intent
of the tablet inventors. They maintained that a directviewing oscilloscope adjacent to the tablet was desirable and that users normally adjusted to the problem of conceptually superimposing the pen and "ink"
in a matter of minutes. Experience with the tablet at
SDC indicates, however, that a significant number of
people have difficulty using the tablet in that manner.
Graphic Tablet Display Console
Tablet
Logic
Pen - - - - - - - -
693
Tablet
Control
Tablet ~-.......wr
18
bIts
I
\
I
\
II
I
\ I
\I
Time-Sharing System
Lens-[j;;J
I \
D/A Converter
\
•
f4.-~
Voke
X,V
A X, AY
Buffers
x
CRT
24
bits
, Power
:;uppl y
(27KV)
Y
Osc i Iloscope
Circuits
Display
Control
48 bits
I
I
I
-~L+_+S;:=X====:.J
V
z
Figure 4-GTD console components
Tablet
The superposition of the display on the tablet surface is a natural evolution and makes the displayed
feedback more meaningful to the user, as well as
easier to use. The tablet is operated by pressing the
stylus pen on the tablet surface, thus closing a microswitch contained within the pen. The pressure necessary to activate the switch is equivalent to that normally required to write with a ball-point pen. The
tablet electronics reads some 4,500 points-per-second,
which proves to be more than adequate for all current
applications. The amount of input data can be reduced - thus reducing the size of the input buffer
required - by introducing a variable oscillator used
for generating the PDP-l interrupts.
Typically, the tablet is read by the PDP-l ev~ry 2
or 4 milliseconds, 250 to 500 points-per-second. The
tablet electronics provides a 22-bit buffer register
(10 x-bits, 10 y-bits, and 2 control-bits) to hold the
stylus position information until read by the computer.
The PDP-l is an 18-bit machine, so that at least two
input read cycles are required. The extra bits gained
in this 36-bit transfer are used to provide additional
information to the user. These include data for:
• The setting of the read interrupt clock.
• Identifying the first point of a new stroke (pen
down after a previous pen up).
• Pen switch down.
• Foot switch down (not used).,
694 Fall Joint Computer Conference, 1967
All this information can be made available to the
user by the PDP-l preprocessing. However, the
PDP-l typically ignores some of this data at the
discretion of the user.
Display
The display function is performed by an oscilloscope with appropriate buffer, digital-to-analog
converter, and control logic for handling the digital
data and driving a projection-type CRT. There are no
special requirements for the oscilloscope; the tolerable
drift, linearity, and amplification for driving the CRT
are well within the state of the art. The logic for producing the analog voltages, buffering and unblanking
signals is also typical of currently designed displays
using random positioning combined with a delta
positioning mode for special features.
The display uses a 24.-bit word, 10 bits each for the
x and y positions, an unblanking bit, and 3 bits for
mode control. The dx and dy data are represented
by 3 bits each and are primarily used for generating
characters within a 5-by-7 dot matrix. The data is
double-buffered so that movement of the CRT beam
between successive points is minimized, reducing the
settling time of the beam and increasing the speed of
operation. The second buffer is also used to store the
positioning data when in the character mode to provide the reference for subsequent delta positioning
information. The average display cycle time per 24-bit
word is 15 JLsec, which includes 4 JLsec for unblanking the CRT. Consideration is currently being given
to improving the display capability with vector, circle
and arc-generating logic.
The CRT used for projection is a 5ZP4, and was
selected for convenience. No appreciable amount of
effort has yet been expended in surveying the market
for a better performing CRT for this application, since
the current one seems adequate. The 5ZP4 operating
at 27,000 volts anode potential is. predicted to have a
5-mil spot size and can produce a spot of 300 foot
lamberts when operating with 30 microamps anode
current unblanked for 4 JLsec. The CRT raster is
limited to 2.2 inches to minimize effects of the CRT
distortion (pincushioning and barrelling).
The CRT image· is projected through appropriate
optics onto a rear-projection screen which is built
into the front surface,. or wearcoat, of the tablet. The
projected image is 10 by. 10 inches - the tablet sizewhich calls for a 4.5 magnification in the optics. The
net effect produces an image of 15 foot lamberts and
a spot size of 20 mils. The light loss through the
printed circuit wires/screen combination is 75 percent, and the remaining loss of brightness is due to
the optics. The display's visual characteristics are
produced with an average 50-Hz refresh rate; the
results are comparable to those obtained with the
direct viewing displays SDC has been using with the
graphic tablet.
A recent innovation (which is being incorporated in
the GTD console at SDC) was developed at The
RAND Corporation. "Comparator" logic was designed that can compare (within preset limits) the
analog x and y voltages of the display with the digital
coordinates of the tablet. This provides the user a
"light-pen" capability with the stylus and tablet. The
user can point close to a spot, being displayed and
receive positive indication about the point of interest
from the display table rather than from inputs from
the pen. In the GTD console, the comparator will be
used to generate an interrupt pulse to the PDP-I.
The PDP-l can then read the address counter of the
display, providing the object program the address of
the word being displayed rather that the x and y positions.
CONCLUSION
A graphic tablet display (GTD) console embedded
in a time-sharing system can provide a 'highly effective means for direct input of graphic information to a
computer. Such a device, employing a RAND Tablet
with a rear-proiectiC)n displav. has recently been
developed at SDC. The interface makes the input and
display buffer directly accessible to the object program, which enhances the response time and is efficient in use of core memory. The interface takes advantage of the previously designed interface of the
PDP-l and Q-32 computers. Thus, integrating the
GTD console into the system was relatively simple.
Experience at SDC-where a variety of I/O devices have been installed with TSS - has demonstrated the advantages of an I/O preprocessor for
interfacing interactive consoles. Although there are
limitations as to the amount of preprocessing the
PDP-l can perform (due to space and timerestrictions, compounded by the limitations of a small
machine), the I/O preprocessor does provide another
important degree of freedom for the system designer.
Employing the tablet display as a projection on the
writing surface has improved the "naturalness" of
this I/O device and has encouraged more users. The
display hardware is more expensive for equivalent
quality of direct-viewing displays, but the additional
advantages gained may be justified for given applications. Additional innovations can be introduced
to improve the flexibility of the GTD configuration.
These include: the projection of slides in conjunction with the CRT image for tablet manipulation; the
adding of a color wheel to achieve computer-generated
Graphic Tablet Display Console
color displays; and the use of a camera to achieve
hard copy output from the CRT. Significant improvement in light output of the projected CRT image must
be achieved before these additional capabilities are
introduced.
The GTD console described in this paper has been
successfully demonstrated. As yet, it has not achieved
its full capabilities as a tool for man-machine communication. Currently, several interesting programs
are being developed at SDC using the GTD console,
including the one described above - computer recognition of hand-printed characters. The intent of the
GTD design and interface is to provide sufficient
flexibility and ease of use to encourage a variety of
users to employ this new, powerful tool. Efforts are
currently underway to design a similar console and
interface for an off-the-shelf, third-generation computer.
695
ACKNOWLEDGMENTS
The author wishes to express his gratitude to Mr.
Clay Fox and Mr. Morton Berstein of SDC for their
contributions to this project. Mr. Fox provided
PDP-l programming support; Mr. Berstein is an
imaginative user of the console, who suggested
many of the system features.
REFERENCES
J I SCHWARTZ E G COFFMAN C WEISSMAN
A general-purpose time-sharing system
Proceedings Spring Joint Computer Conference pp 397-411
1964
2 M I BERNSTEIN
An on-line system/or utilizing hand-printed input
SDC document TM-3052 19 pp July 1966
3 M R DAVIS TO ELLIS .
The RAND tablet: A man-machine graphical communication device
Proceedings Fall Joint Computer Conference pp 325-350
1964
Multi-function graphics for a large computer system
by CARL CHRISTENSEN and ELLIOT N. PINSON
Bell Telephone Laboratories, incorporated
Murray Hill, New Jersey
I. INTRODUCTION
Although much effort has been spent trying to improve
communications across the man-computer boundary,
most large computer centers still rely on punched-cardinput and line-printer-output for the bulk of their load.
Even modern "time-shared" systems rely principally on
teletypewriter alphanumeric communication between
man and machine.
A great deal has been learned, however, about other
ways of communicating with computers, particularly in
terms of graphical information. 1,2,3 On output, graphs
and drawings convey meaning to a human viewer much
faster than large tables of numbers. Computer generated
motion pictures add a time dimension to a display that
can help provide physical insight into complex problems.4,5 On input, the ability to identify objects in a
picture by pointing at them, or to modify a picture in a
natural way by drawing in it is a great convenience. 6• 7
Graphical output has been an important way of presenting results to Bell Laboratories' computer users
since the fall of 1961, when a Stromberg Carlson 4020
microfilm printer was installed at Murray Hill. It has
allowed users to replace pages of tabular data with pictures that are far easier to understand. Microfilm picture generation was running recently at a rate of about
500,000 frames per year. In addition, computer movies
were being generated at a rate of about 1,000,000
frames per year.
In 1964 the experimental GRAPHIC-1 display terminals was interfaced to a 7094 at Murray Hill to provide semi-on-line graphical input-output to the 7094
for a single user at a time. Despite the fact that this was
a one-of-a-kind system, it was extremely popular and
heavily used. It incorporated a small processor in the
terminal to handle all real time requirements generated
by the user.
More recently, an experimental on-line graphical output device that can produce hard-copy at a rate of
about one page every five seconds was interfaced to the
7094. This device uses a microfilm intermediate stage
with a rapid high temperature developing process to
produce output within 30 seconds of the film being exposed. This, too, has been popular with users, although
mechanical problems have caused excessive down-time
for the device.
Although the graphics facilities on the 7094 system
were extremely useful, they were far from what a
modern, large-scale computing center should offer its
customers. Among the features that seemed ready for
improvement were the hard-copy output turnaround
time (frequently overnight on the SC-4020, although
sometimes as good as a few hours), the fixed geographical position of all devices, the inaccessibility of the system through standard transmission facilities, and the
extremely small number (in fact, just one) of terminals
from which users could run their graphical programs.
In Section II of this paper an overview is given of
a new graphics system being developed at Bell Laboratories. Following sections. describe certain aspects of the
system in more detail. Section III describes hardware, and Section IV describes the Graphical Data
Structure used to represent picture information in the
computer. The GRIN-2 graphical programming language is discussed in Section V (an annotated example
of a GRIN-2 program is given in the Appendix). Section VI describes some functions
performed
by the
r
.
GRAPHIC-2 Executive System, and Section VII describes briefly some of the functions of the GE-645
Software System. A brief summary is given in Section
VIII.
II. System overview
A modern large scale computer facility should provide a variety of graphical services for 'its customers.
These range from hard-copy output of high quality to
highly interactive on-line graphical communication be697
698
Fall Joint Computer Conference, 1967
tween man and computer. The graphical services provided by the system described in this paper include:
1. Rapid hard-copy output (STARE system);
2. On-line direct-view cathode ray tube output
(GLANCE system) as an accessory display for a
teletype console;
3. Remote on-line interactive graphical input-output (GRAPHIC-2 system);
4. Precision microfilm and hard-copy output;
5. High precision drafting quality output.
Obviously, no single type of display can provide these
very different services in an economic~l way. Rather,
several different kinds of equipment are required. Services 4 and 5, although very important, will not be discussed further since they are provided by standard commercially available equipment, namely, an SC-4060
microfilm printer and a Gerber drafting table. As will
be seen below, however, programming support for these
devices is handled in large part by software used in
common for all hardware systems. The first three categories involve systems for which a combined hardwaresoftware design effort was performed. Hardware details for each of these systems (STARE, GLANCE, and
GRAPHIC-2) are given in Section III.
The graphics systems will run on a large multi-access
computer installation at Bell Laboratories' Murray Hill
facility. This computer system will soon be operating
under the Multics9-13 system. The equipment features a
dual-processor GE-645 computer with 256K of 36-bit
1 JLs core memory and extensive on-line mass storage
(drum, disk, etc.). Multics system features include a
large on-line multi-level file system, memory segmentation and paging (to give each user an extremely large
virtual memory space), and the ability to communicate
with many on-line communication devices. The system
will simultaneously service many console users and programs entered in a conventional "over-the-counter"
mode. Most on-line consoles will be of the teletypewriter variety. Additional graphic' consoles as described
in this paper will also be available. Response times for
users of the graphics system will be measured in seconds
rather than minutes (for GRAPHIC-I) or hours (for
the SC-4020). True remote access to the computer vic
dialed up voice grade phone lines will be possible from
several of the terminals.
For computer graphics to have a substantial impact
on many people, it is necessary to make graphic equipment available and accessible. Two factors must be considered: first, physical accessibility, made possible by
providing multiple devices which can be used simultaneously and which are conveniently located; second,
program accessibility made possible by providing the
user with a powerful set of system functions and a higher
level language for his graphical programming (see Sec-
UP TO 16
GLANCE
SCOPES
UP TO 16
GLANCE
SCOPES
4 - 8 LOX 'PRINTERS
Figure I-On-line computer graphics facility
tion V on the GRIN-2 language). Although specific
numbers of devices are not known at this time, Figure
1 shows a configuration that should be achieved during
1968.
Despite the fact that many different types of hardware are supported, the bulk of the software in the
central computer is device independent. This is because
a device independent representation of picture information is used in the central machine. This representation,
called the Graphical Data Structure (see Section IV)
describes a picture that can be displayed on any of the
graphical terminals in the system. The Graphic Data
Structure provides a standard for communcation of picture information between programs and is the form in
which pictures are stored in the GE-645 File System.
Device dependent Translator modules are used to convert from the central format to the command formats
required by a particular device. There is one such
Translator module for each type of graphic device in
the system.
In the case of the STARE hard-copy system, a user
will be able to go to an output station near his office
rather than have to go to a single central distribution
point. Up to eight such remote printer stations may be
served by the hard-copy system. Among other uses, the
rapid hard-copy facilities are expected to aid users accessing the machine from teletype consoles whose low
speed makes them unsuitable for listing alphanumeric
files. Dumps and other listings can be produced on the
STARE system upon command from a teletypewriter
console.
The intent of the GLANCE on-line direct view CRT
system is to provide an accessory graphical display capability for standard teletype consoles. The CRT dis-
Multi-Function Graphics for Large Computer System
play is physically independent of the teletypewriter, although located immediately adjacent to it. Under software control, graphical output from the program being
controlled from the teletype will be displayed on the
CRT display. The CRT display can be maintained without consuming costly central machine resources, since
a special high-speed disk buffer is used to store the
commands that generate the picture. A track of this
disk has to be loaded once for each picture to be shown.
Thereafter, the picture is maintained on the display tube
without central machine intervention. Since a high data
tate is used between the disk buffer and the displays it
supports, each display must be within coaxial cable
reach of its buffer. A complete GLANCE system (disk
plus CRT terminals) can be located remote from the
central computer if a small computer is added to the
system. The small computer can receive coded graphical
data at low speed over a transmission link, convert it to
the command set required by the display logic, and
. write a picture at a time at high speed onto the magnetic
disk. An example of this type of operation is shown in
Figure 1.
The GRAPHIC-2 system is an interactive graphic input-output terminal. Graphical input is accomplished by
using a light pen to point at objects displayed on a
CRT. This system accesses the central computer over
a voice grade transmission line. One of the principal
objectives of the GRAPHIC-2 system is to provide good
terminal response to the operator while using slow (but
economical) communication lines to the central computer system. Unfortunately good terminal response is
measured in fractions of a second, while response from
the central computer may take several seconds. For
example, transmission of a 100-word data block (18 bit
words) takes almost one second over the 2000-baud
voice grade line. Added to this must be the delay involved in capturing the central processor (which is
simultaneously trying to service numerous other users)
and in carrying out central machine computations.
The solution to this problem lies in having GRAPHIC-2 itself handle users' real time demands. Thus, such
actions as pen-tracking and drawing are handled in real
time at the display terminal (by the PDP-9 processor
that is part of the GRAPHIC-2). It is only the results
of these actions (final X-V coordinates or identity of a
selected object) that are sent back to the central computer, where a master copy of the picture is updated.
Fortunately, modifications to this master copy do not
have to be made in real time since the user at the
terminal sees the results of his actions on the local version immediately.
Two versions of a user's program are compiled. These
programs originate from a single GRIN-2 (see Section
V) source program. Both compilations are performed
699
by the GE-645. One produces GE-645 .machine code
and the other produces PDP-9 machine code. The former executes in the GE-645, operates on the Graphic
Data Structure (see Section IV) in the central machine
and obtains its "pseudo real-time" -inputs from a queue
sent back from GRAPHIC-2. The latter executes in a
GRAPHIC-2 terminal, modifies a local (at GRAPHIC2) copy of the data structure and services real-time inputs as they occur (light-pen strikes, button pushes,
keyboard inputs), simultaneously recording their occurrence on the queue destined for the GE-645. The queue
is periodically sent to the central computer, allowing
the GE-645 execution of the user's program to catch
up with GRAPHIC-2. This strategy minimizes the
amount' of data that have to be transmitted from
GRAPHIC-2 to the central machine, since only the
real time events are transmitted.
III.
Display hardware systems
The following three display systems are described:
A. The STARE (Short Turn-Around REcorder)
rapid hard-copy system.
B. The GLANCE (GraphicaL Accessory oN-line
ConsolE) cathode ray tube output display.
C. GRAPHIC-2, a graphical input-output display
terminal that includes a small processor, display
CRT, light-pen and keyboard.
A. The STARE hard-copy system
The STARE hard-copy facility accommodates up to
eight rapid hard-copy output stations. The organization
of the system is shown in Figure 2. The system consists
of multiple remote Xerox LDX (Long Distance Xerography) Printers interfaced to a central buffer memory
and ('ontrol unit that is located near the GE-645. The
LDX printers form an image by a raster scan technique,
DATA
GE 645
LOX ADORESS
COMMANDS
COMMANDS
Figure 2-STARE system organization
4-8 LOX
UNITS
700
Fall Joint Computer Conference, 1967
so the data from the central buffer unit to the printers
are essentially a video signal for controlling the intensity along each scan line. These data to the LOX
Printer are transmitted from the central buffer at about
a 250,000-baud date over coavial cable links. There are
eight separate buffer areas on the magnetic drum which
function independently. Therefore, transmission to up to
eight printers can take place simultaneously.
The central buffer unit is a digital scan-converter. It
accepts drawing commands in an incremental command
code (the same one used by the GLANCE system described below) and converts these to the raster scan
required by the LOX Printers. The complete picture is
specifIed on a plotting grid 1024 X 1408 (corresponding to a plotting area of 8" X 11"). The core memory
contains enough storage to represent the raster scan of
about a one inch strip of the output (128 lines by 1024
bits/line). An I/O command from the central computer
specifies which strip the core buffer is to scan-convert.
The incremental commands that specify the entire picture are then sent to the buffer unit. The buffer logic
transforms these to raster scan bits for the proper strip
and stores them in the core buffer, 1 bits representing
black dots and 0 bits representing white. After the picture has been scan-converted, the core image is automatically transferred to the appropriate tracks on the
magnetic drum. This process is repeated eleven times
to transfer the entire picture to the drum. An I/O Print
Command is then issued to the computer which starts
the appropriate LOX Printer and initiates the drum-toprinter transfer.
The data rate between the central computer and the
core buffer unit is about 2xl0 8 baud. Since a complete
picture is often specified in under 105 bits in the incremental code, each burst of data takes about .05
seconds for the core to core transfer. The buffer-core
to drum transfer is at about a 106 baud rate, and takes
about .15 seconds to complete (including drum latency).
A full picture (11 strips), by these rough calculations,
takes about 2.2 seconds to transmit from central computer to drum buffer. About an additional five seconds
are required for the drum to LOX Printer transfer.
Thus, a single printer can produce about 8 frames per
minute in this system, and a maximum throughput of
over 24 frame'S per minute distributed among. several
printer stations is possible.
B. The GLANCE direct-view scope system
The GLANCE system has been described in a previous paper .14 However; the essential elements will be
repeated here for the reader's convenience. Figure 3
shows the GLANCE configuration. A central disk buffer holds picture information for up to 16 GLANCE
display terminals. A single track of the disk is dedicated
OTHER
TELETYPEWRITERS
I READ AMPLIFIER AND COAXIAL CABLE
I (ONE PER CHANNEL)
, (4 MEGABITS/SEC)
DATA DISC MEMORY
16'-32 TRACKS,HEAD PER TRACK
1800 RPM, 30 FRAMES/SEC
132,000 BITS/TRACK
33,000 INSTRUCTIONS/TRACK
lpo SEC/INSTRUCTION
ONE OF A POSSIBLE
16-32 DUPLICATE
CONSOLES
Figure 3-GLANCE system organization
to each of the terminals, and each of the tracks has its
own read-head and line driver. The picture on each
track is specified in terms of the simple four-bit incremental commands shown in Figure 4. These commands are decoded by logic in each of the scope terminals where X-V deflection and unblanking signals are
produced to position and display points. The commands
allow the 'beam to be moved a certain number of units
in any direction on a 1024 X 1024 grid (left-right, updown, or diagonally) covering a 10" X 10" area on
•' t•/ •
.~.~.
/ t ~-----preseni
•
•
•
Position
COMMANDS
Control
No op
Reverse beam on/off
Increment intensity (mod.4)
Set scole x I
Set scole x2
Set scole x4
Set scole x8
Set scole xl6
Moves
Right
Right-Up
Up
Up- Left
Left
Left-Down
Down
Down- Right
Figure 4-Incremental command plotting technique
Multi-Function Graphics for Large Computer System
the scope-face. Moves can be made with the beam
blanked to reposition it without leaving a trace. Four
spot intensities can be used. A scale-factor can be preset so that incremental commands cause a beam move
of one, ,two, four, eight, or sixteen grid units. This permits fast slewing with the beam blanked.
The disk rotates at 30 revolutions per second (lS00
rpm), so the picture on each scope is refreshed at a
30-cycIe rate. With the proper phospher this rate is
high enough to give a flicker-free display. The data
transfer rate from disk to display scope is 4x10 G baud,
so this connection is made with coaxial cable. The display terminals can be located up to a mile or so cable
length from the central disk buffer. At the data rate
used, lOG points/second are plotted by the display
terminal. Figure 5 shows a picture of a GLANCE console including a Teletype, and Figure 6 shows pictures
taken directly from a GLANCE CRT.
Figure 6-Sample pictures from a GLANCE CRT
Figure 5-The GLANCE terminal
c.
GRAPHIC-2
Many of the factors that affected the design of
GRAPHIC-2 were discussed in Section II of this paper.
A detailed description of the system is presented in a
forthcoming paper. 15 Only the essential elements will be
repeated here. Figure 7 shows the GRAPHIC-2 organization. A picture of the hardware is shown in Figure S.
A standard DEC PDP-9 with optional automatic priority
interrupt and a direct memory access channel is the
heart of the system. Its memory consists of SK words
of IS-bit one microsecond core. This memory serves as
display buffer memory and also holds programs that
execute in the PDP-9. An optical paper tape reader
and a paper tape punch are standard. The display scope
and display command set are described in detail in the
forthcoming paper .15 A light-pen and keyboard (ASCII
alphanumerics plus S pushbuttons) complete the
GRAPHIC-2 hardware.
,------------,
STANDARD PDP-9 COMPUTER
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
L ____ _
Figure 7-GRAPHIC-2 organization
701
702
Fall Joint Computer Conference, 1967
Figure 8-The GRAPHIC-2 terminal
The scope has a character generator that can display
the full ASCII 96 graphic set. Among the features that
have been included in the scope hardware to facilitate
programming are: Edge violation traps whenever a
command tries to make a line cross a scope boundary,
either in or out; software commands to determine the
exact state of the scope at any time and to restore the
scope to any state; commands which when encountered
automatically stop the scope and interrupt the PDP-9
processor. In short, a great deal of thought was devoted
to the design of a scope-processor system that is easily
programmable.
IV.
Although the main graphical data base is in the large
central computer, the GRAPHIC-2 terminal stores picture information in an identically structured form. As
will be seen, information in the graphic data structure is
stored in discrete blocks that are linked together by
chains of pointers. Although formats within blocks in
the GE-645 are different from those in the GRAPHIC2, there is a one-to-one correspondence between blocks
in the two structures. Because the memory in the
GRAPHIC-2 is small (8K, 18-bit words), all blocks
in the data structure do not have to be present in
GRAPHIC-2 at the same time. A dynamic memory
management system fetches blocks from the central
computer when they are needed, and releases memory
in GRAPHIC-2 to free storage when blocks are no
longer needed. Some differences between block formats
in the central machine and in the GRAPHIC-2 are
explained at the end of this section. The following discussion describes the graphical data structure in the
central computer.
Blocks in the structure
The graphic data structure contains four types of
blocks: node blocks, branch blocks, leaf blocks and
data blocks. These are shown symbolically in Figure 9.
(Although a branch is represented by an arrow, it is
not simply a pointer, but is a contiguous set of memory
locations, as are each of the other block types. ) Nodes
The graphic data structure
The various graphical devices that are supported by
GRAFCOM (GE 645 Graphical Communication software) function quite differently at the hardware
level. In particular, they use different command formats
to generate pictures. However, in the GE-645 a single
standard way of describing graphical information is used
that is independent of any particular display device.
This common representation is called the Graphic Data
Structure. All picture building routines generate blocks
that are attached to the user's graphic data structure.
All picture editing routines assume they are operating
on pictures represented in this standard way. Thus a
single set of graphical programs is used to manipulate
graphical information whether a GRAPHIC-2 interactive console, or any other graphic output device
is being used. Before display commands are sent
to a particular type of device, a device dependent program is called to convert from the standard format to the
special command set used by the device. Methods for
representing picture structure have been described in
the literature. 1•16 •11 The structure used in GRAFCOM
differs from these in detail, but was strongly influenced
by several previous systems.
o
Nodes
Branches
o
C_____)
Leaves
Non-Display Data
Figure 9-Blocks in the graphic data structure
and branches are blocks of fixed size; other blocks may
be of arbitrary length. The generic form of graphical
structures is the directed graph (with no closed loops).
A directed graph is a set' of nodes and connecting
branches in which the branches have a direction as-
Multi-Function Graphics for Large Computer System
sociated with them, i.e., they point from one node to
another. Some of the terminal nodes of the directed
graph have special significance and are called leaves,
in analogy with the way leaves are extremities on a
tree. By convention, only leaves in the structure can
specify displayable material. Other blocks are present
only to provide structural information. Figure 10 shows
the typical form of a graphical data structure.
Each node represents a particular sub-part of the picture. Each branch represents a particular occurrence, or
instance, of the node to which it points. The branch
may be thought of as a graphical call to a sub-part of
a picture. It will cause the sub-part to appear at a position specified by information in the branch. Nodes serve
to group together those sub-parts that the user may
want to be associated with each other to form a larger
sub-part. This nesting can continue to arbitrary depth.
703
..-- in-branches
....- out-branches
NODE BLOCK CONTENTS
•
•
•
•
•
•
Block type identifier
Poi nter to name data-block
Pointer to first "in-branch"
Pointer to last "in-branch"
Poi.nter to first "out-branch"
Pointer to last "out-branch"
Figure ll-Typical node-block and its contents
o
Nodes
Branches
o
Leaves
Figure lO-Typical graphic data structure
Nodes
Figure 11 a shows the configuration of a typical node.
Note that an arbitrary number of branches may enter a
node, and an arbitrary number of branches may leave.
It would not be possible to allocate a fixed size block
for the node if pointers to all these branches were required in. the node. To avoid this problem, the "inbranches" (branches entering the node) and "outbranches" (branches leaving the node) are organized
in separate "rings."17 The node contains a pointer to
the first branch in each of these rings, and each of these
branches contains a pointer to the next branch, etc.
Finally, the last branch contains a pointer back to the
original node. A thread established by' "back-pointers"
also links all the elements in a ring in order to make
tracing through rings faster for computer programs.
Figure 11 b shows the contents of a node block. In
addition to pointers defining the "in" and "out" branch
rings, each node contains a block type identifier
(identifying it as a node) and a pointer to a data block
that contains the symbolic name of the node. Thus
every node (and therefore every picture subpart) may
be referred to symbolically if desired. If the node has
not been assigned a name, this pointer will contain
a null value.
Branches
Figure 12a shows a typical branch connecting two
nodes. Each branch has two rings passing through it:
the "out-branch" ring associated with the node the
branch starts on, and the "in-branch" ring associated
with the node the branch terminates on. Figure 12b
704
typical
branch
Fall Joint Computer' Conference, 1967
..
"out-branch "rino
~
.. in-branch" rinO
----~
BRANCH BLOCK CONTENTS
* Block type indentifier
* Name-dato-block pointer
* "In-branch"ring pointers
* "0 Ut- branc hitrlno
. pOinters
.
* System non-display-data pointer
* User non-display-dota pointer
* Branch x- displacement
* Branch y- displacement
* Branch display control parameters
point that control is to be passed to if the instance represented by the branch is pointed at by a light-pen.
The purpose of the user non-display pointer is to
allow the user (programmer) to attach non-display
information to the graphic data structure. This nondisplay information is placed in "data-blocks," which
are one of the four types of blocks found in the
graphical data structure. These data-blocks are for the
exclusive use of the programmer. They are defined and
allocated under program control and may be of arbitrary
format and size. They are intended to allow the user
to specify information about instances that does not
appear in the display.
Finally, the branch contains three fields necessary
for the generation of the display itself. The X and Y
displacements specify the distance between the display
origins of the nodes ( or' node and leaf) which the
branch joins. Since all display information in the structure is in terms of relative coordinate information (only
the starting point of a display is an absolute coordinate),
instances of sub-pictures can be moved about the display surface simply by changing the X and Y displacements in the proper branch. The last field contains display parameter information. Such things as
intensity, scale and whether or not the light-pen is to be
enabled during the display of the instance can be
specified.
Leaves
Figure 12-Typical branch-block and its contents
lists the contents of a branch block. It contains a block
type identifier (identifying it as a branch) and a pointer to a data block that contains its symbolic name.
Thus every branch (and therefore every instance in a
picture) may be referred to symbolically. If the branch
has not been assigned a name, this pointer contains a
null value. Next, the branch contains two ring elements.
Each ring element contains three pointers: (1) a pointer in a forward chain linking all branches in the ring;
(2) a pointer in a backward chain linking all branches
in the ring; (3) a pointer to the node that is the "head"
of this ring. These pointers facilitate rapid examination
of the structure under program control.
Two pointers. are included to data-blocks. These are
the "system non-display data" pointer and the "user
non-display data" pointer. If either of these pointers
is not being used, a null pointer value is used for it: The
system pointer and any data blocks linked to it are
for the exclusive use of the' graphical programming
system. User programs may not access this information.
The principal use of the system pointer is to point to a
data block that identifies the branch as a light button.
That data block contains the name of a program entry
Leaves specify how portions of a picture are actually
to be drawn. They contain the "ink" that is visible in
a portion of a picture. Data is placed in leaves by calls
to data generating subroutines in GRAFCOM. Both
text and line drawing information may be specified.
When information is placed in leaves, the programmer
is specifying information on a very large display surface. It is only when the information is finally displayed on one of the several available devices that a
"window" is specified that establishes what portion of
the display is to be visible on the output device. Data
"grown" into leaves in real time by drawing on the
GRAPHIC-2 scope must be rescaled before it is stored
in the central data structure. Since a leaf may contain
an arbitrary amount of data, its size cannot be specified
in advance. For this reason, the leaf is broken into
blocks of two types; the leaf-header block and leafdata blocks. The leaf-header block contains a single
ring-element, the "in-branch" ring, since by convention
no branches point away from a leaf. It also contains a
pointer to the first leaf-data block and to the last
leaf-data block that make up the body of the leaf.
These leaf-data blocks are linked by chain of pointers.
A new leaf-data block is allocated and added to the
chain whenever new data for a leaf are generated.
Multi-Function Graphics for Large Computer System
Modifications for GRAPHIC-2
Example
The following example illustrates many of the features of the graphic data structure. Figure 13a shows
a type of pattern familiar to anyone who has studied
electronics. It is a diagram of a simple resistor-capacitor
circuit. Because of generally accepted conventions, the
meaning of this picture is immediately apparent to many
people. Computers, however, have taken no electrical
engineering courses. The pattern of lines might just as
well be abstract art so far as the computer is concerned.
The fact that a certain group of straight line segments
symbolizes a resistor is not inherent in the picture, but
is an organization imposed on the image by the viewer.
STRUCTURE I
705
STRUCTURE 2
Figure 13-Simple circuit and two possible structures for it
A leaf is generated that contains the picture corresponding to each of the three types of elements in the
circuit: resistors, capacitors and short-circuits. These
elements may be positioned anywhere on the display
surface by appropriate connecting branches. In the
representation of Structure 1, shown in Figure 13b, there
is no additional structure in the picture aside from the
fact that each element type is a single leaf. In the
representation of Structure 2 in Figure 13c, a sub-picture consisting of a resistor, capacitor and short circuit
has been formed. In the whole picture there are three
instances of this sub-picture ( one for each of the
branches pointing to the subpicture node), and one instance of each of the three basic elements.
Additional non-display data blocks would undoubtedly be linked to these branches in most real applications. They would contain such information as the
electrical type of the elements being displayed and their
values for use by analysis programs.
The data structure in GRAPHIC-2 retains all the
structural information present in the data structure in
the central computer. GRAPHIC-2 is the only one of
the display systems that uses information in structured
form. All the others simply receive a set of display
commands from the appropriate device Translator module. GRAPHIC-2 needs the structure because of the
real time response it must give users at its console. It
must be able to identify objects that are pointed at
without requiring the intervenion of the central computer. It must be able to edit the structure, too. Thus, the
GRAPHIC-2 data structure contains nodes, branches,
leaves and data blocks that are in one-to-one correspondence with equivalent blocks in the central data
base. Formats internal to these blocks are different,
however. First of all, leaves in GRAPHIC-2 contain
display commands in the format required to run the
display scope, while picture information in the central
computer is represented in a device independent way.
Because a different dynamic storage allocation technique
is used in GRAPHIC-2, a leaf is a single contiguous
block of memory rather than a sequence of leaf-data
blocks linked to a leaf-header. These leaves can be
grown in real time under program control and may be
of arbitrary length. Because space is a scarce resource
in the small GRAPHIC-2 computer, an abbreviated
pointer system is used to link blocks in the data structure. In particular, back pointers and pointers to the
heads of rings are not used. Tracing one's way through
the structure therefore may require more time, but time
is a resource that is more readily available than space
in GRAPHIC-2.
V.
GRIN-2 language
The GRIN-2 (GRaphical INteraction) language is
a high-level graphical programming language that permits the generation and manipulation of the graphical
data structure, and provides statements for controlling
real-time man-machine interaction. The interaction portion of the language is used with the GRAPHIC-2
graphical terminal. The rest of the language pertains to
the common data structure used by all graphical devices
and terminals.
The following is not a specification of the GRIN-2
language, but a brief description of a few statements
in several categories, the purpose of which is to give
the reader the· flavor of the language and allow an understanding of the programming example given in the
Appendix. The categories described are:
(1) Real-Time Man-Machine Interaction
(2) Structure Generation
(3) Display Data Generation
706
Fall Joint Computer Conference, 1967
(4) Structure Editing
(5) Display Control
Real time man-machine interaction
The basic man-machine interaction philosophy of the
GRIN-2 language is one of the question and answer.
The language provides statements which ask questions
of the operator at a GRAPHIC-2 terminal. GRAPHIC2 then waits (with control held by the language statement) until the operator answers the question by some
light-pen or keyboard action. Control is then passed on,
along with his answer, to other GRIN-2 statements
which use the answer to direct further processing.
One of the real-time questions provided in GRIN-2
is asked by the WHICH statement. WHICH asks the
operator the question "which of the objects displayed
on the scope?" The operator then answers by pointing
the light-pen at one of the objects. The meaning of this
question depends on when it is asked. For instance, if
a program to delete objects from the scope is in control it might use the WHICH statement to ask "WHICH
of the objects displayed on the scope should be deleted?" When the operator pointed to one of the objects
with the light-pen, control would pass on from the
WHICH statement to the next statement. The next
statements would then use the answer to delete the
object picked.
The WHICH statement can also be used to direct
the flow of control in the program through the use of
light buttons. A light button is a displayable object
which is associated with a program or subroutine. Given
a number of light buttons displayed on the scope, the
program in control could use the WHICH statement
to ask "WHICH program should receive control next?"
or "WHICH function should be performed next?" The
operator could then pick the desired light button with
the .light-pen, and the WHICH subroutine would pass
control to the picked light button's associated program.
Another basic real-time question in the GRIN-2
language is asked by the WHERE statement. WHERE
asks the question "where on the scope?" by displaying a tracking cross which can be moved around
the scope face with the light-pen. The operator answers
this question by positioning the tracking cross with the
light-pen. When the tracking cross is positioned where
he wants it, the operator informs GRAPHIC-2 by pushing a button or taking some other action that can be
specified as an argument in the WHERE statement.
This action could even be picking a light button with
the light-pen. Objects displayed on the scope can be
made to move with the light-pen by "attaching" them
to the tracking cross. Other GRIN-2 statements use
WHICH and WHERE to form higher level statements
such as DRAW. DRAW uses repeated calls to WHERE
to allow the operator to draw a broken line segment
on the scope.
Structure generation
Building a graphical data structure is done with
three statements: LEAF, BRANCH, and NODE.
LEAF BLKPTR
generates an empty leaf-block and places a pointer to
it in BLKPTR.
BRANCH (BLKPTR,FROM,DXY,PARM,TO,LB,
DATA)
generates a branch-block and places a pointer to it
in BLKPTR. FROM is a pointer to the node from
which this branch is to descend. TO is a pointer to the
leaf or node to which this branch is to point. DXY is
a pointer to a DX, DY word pair which specifies the
relative dsplacement on the scope between the display
origins of the FROM and TO nodes. P ARM is a
pointer to a location which contains the parameters
to be specified in the branch. If LB is given, it specifies
that the branch is a light button and its associated subroutine is LB. DATA points to a user's data block that
is to be attached to his branch. All of the arguments in
the BRANCH statement are optional.
NODE BLKPTR ( (B,DXY,P,T,LB,D) ( ... ) ... )
generates a node-block and places a pointer to it in
BLKPTR. The next string of arguments specify a
branch or set of branches which are generated and
descend from the generated node. These arguments are
similar to those in the BRANCH statement.
Display data generation
Display data in leaves are the scope commands which
drive the scope and produce the picture. The following
statements produce display data which is directed into
the leaf specified by the last occurrence of either an
INLEAF or LEAF statement (last generated leaf).
TEXT (CHI,CH2,CH3 ... )
stores a series of characters in the last specified leaf.
When the leaf is displayed, characters CHl,CH2,
CH3 will appear on the scope.
VECTOR (DXY1,DXY2,DXY3 . . . )
generates a series of vectors. The arguments may be
pairs of signed decimal integers or the location of a
DX,DY word pair.
Structure editing
Statements in this category allow changes to be made
to an already existing structure.
TCMOVE (BRANCHl,BRANCH2, . . . )
This is a dynamic statement which specifies that DX
and DY (relative displacement) in the branches
BRANCH 1,BRANCH2 etc., are to be changed as the
position of the tracking cross is changed in the next
Multi-Function Graphics for Large Computer System
WHERE statement. This allows objects to move with
the tracking cross.
DETACH (BRANCH1,BRANCH2, ... )
Specifies that the branches BRANCH 1, BRANCH2,
etc., should be detached from the structure.
ATTACH BRANCH,NODE
Attaches the branch specified by the pointer
BRANCH to the node specified by the pointer NODE.
Display control
The structure or structures to be displayed are specified by attaching them to a special node called the
DISPLAY NODE (DSPNOD). This may be done with
the standard· structure editing statements or by the
special display control statements described below.
NEWDSP (BRANCH1,BRANCH2, ... )
Any existing branches which are attached to the display node are detached and BRANCHl,BRANCH2,
etc., are attached to the display node.
ADDDSP (BRANCHl,BRANCH2, ... )
The branches BRANCHl,BRANCH2, etc., are attached to the display node without disturbing any
branches which were already attached to it, adding them
to the picture.
SUBDSP (BRANCHl,BRANCH2, ... )
The branches BRANCH 1,BRANCH2, etc., are removed from the display node without disturbing other
attached branches (subtracting them from the picture).
Other categories of GRIN-2 statements include
STRUCTURE TRACING, NON-DISPLAY STRUCTURE GENERATION, and SYSTEM CONTROL.
and the GE-645. The data communication program
controls the dataphone, buffers input and output data
streams, detects errors and provides an error recovery
strategy.
management
~emory
The memory management programs give the PDP-9
a very large virtual memory, using the GE-645 and its
file system for secondary storage. To make this possible
the user's program, data and graphical data are broken
up into blocks of variable size. Each block is given a
unique 17-bit identification number (lD) before it is
transmitted to the GRAPHIC-2, and all references
between blocks are in terms of these ID's and an offset
within the block. The ID is also used to request a block
from the GE-645. To make interblock referencing
practical, every block in the GRAPHIC-2 memory has
assigned to it while and only while it is in core an
entry in the BLOCK TABLE, which is located in the
GRAPHIC-2 (see Figure 14). This entry establishes
the correspondence between a block's ID and its location in the GRAPHIC-2, which makes possible easy
relocation of blocks in core; only the core address in a
block's entry in the block table need be updated when
a block is moved.
BLOCK TABLE
VI. Graphic-2 executive
The GRAPHIC-2 Executive is a set of programs that
execute in the GRAPHlC-2's PDP-9 processor. It performs the functions of memory management, interrupt
handling, data communication and display management. These functions are described below.
Interrupt handling
The interrupt handler is the heart of the executive
program. All of the operator inputs to the GRAPHIC-2
(light-pen, pushbuttons, keyboard) are detected via
interrupts as are conditions such as dataphone input
and output, oscilloscope edge violation, and the occurrence of scope commands with an interrupt bit set.
When an interrupt occurs, the trap handler gives control
to the subroutine associated with that interrupt. This
association is changeable from outside the trap handler,
allowing programs to specify and change the reaction
to any of the interrupts.
Data transmission
A 20lB Dataphone (2,000 bits/sec) is used to
transmit data back and forth between the GRAPHlC-2
707
}
800 WORDS
AVAILABLE
SPACE
4892 WORDS
8,192
WORDS
BLOCKS
GRAPHIC-2
EXECUTIVE
o
2500 WORDS
,
Figure 14-GRAPHIC-2 memory layout
708
Fall Joint Computer Conference, 1967
The first time an inter-block reference is executed a
search of the block table is made and the ID in the
reference is replaced by its correspo~ding block table
entry address (BTEA). Succeeding executions of that
reference made before either of the blocks is removed
from PDP-9 core, may be accomplished without having
to search the block table. If the referenced ID is not in
the block table then the block is not in core and a request for it is issued to the GE-645.
When a block is removed from core, its entry in the
block table is also removed. At this time a search of
every block in core is made to find any BTEA references to the removed block. These BTBA references
are then charged to ID's. The hole created by removing
a block is added to the available space (see Figure 14)
by relocating all the blocks above it. The blocks are always contiguous in core.
In summary, when a block is not in core, all references to it are indicated by use of its ID When a
reference is made to a block not in core, the block is
fetched from the GE-645. An entry is made for the
block in the block table and reference by ID is changed
to a reference by BTEA. Other references to this block
from any other blocks are linked (lD changed to
BTEA) only when the reference is made. If the block
is removed from core, all linked references are unlinked. The block table allows conversion from ID to
BTEA (as references are linked) and vice-versa (when
a block is removed). It also provides the starting core
address of the referenced block so that an offset may be
added to complete the reference.
Display management
To display the graphic data structure described in
this paper, a semi-interpretive display program is used.
A single leaf can be displayed by the scope without intervention by the PDP-9, but threading through the
nodes and branches requires push down operations and
help from the memory management programs. The display manager supplies this structure tracing function. It
seeks out every path to every leaf in the specified structure and displays leaves as it encounters them. It uses
the memory management program to link all references
in the structure (if any are not yet linked) on the first
pass through the structure. After the structure is linked,
the interpretive and noninterpretive display functions
are overlapped, i.e., while the GRAPHIC-2 scope-processor is displaying a leaf the display manager in the
PDP-9 finds the next leaf and prepares to display it. Displaying interpretively has several advantages over a
linked self-running display list. The relative positioning
vectors in each of the branches, for example, are added
up along the path to a leaf and the result put out as a
single scope positioning command. This technique is
much faster than executing all individual positioning
vectors. Also, the pushdown list kept by the display
interpreter contains a real time record of the display
path. This record is very valuable when a light-pen strike
occurs. Interpretive operation also allows the relative
positioning vectors in the branches to be stored as
full IS-bit Ax and IS-bit Ay values because scope command op-code bits are not necessary. This allows the
GRAPHIC-2 data structure to contain an IS-bit by
IS-bit picture, of which any IO-bit by IO-bit section can
be displayed on the scope face.
VI/.
GE-645 graphic software system
Routines in the graphic programming system can be
divided into two distinct categories: those which are
accessible to a user by call or GRIN-2 language statement and those that are invisible to the user but provide
necessary services. In the first category are sub-routines
for building and editing the user's Graphic Data Structure and for creating and linking nondisplay information to it. In the second category are programs that
handle communication between the GE-645 and all
graphical devices, and the Translator programs that
convert from internal GE-645 picture representation
to formats required by specific devices. A dynamic
storage allocator is used to allocate and free blocks
that are used in the graphic data structure.
The most complicated device to handle from the
point of view of the software system is the GRAPHlC2. A library, of GRAPHlC-2 subroutine blocks is maintained on GE-645 disk storage. These are kept in
relocatable, linkable format since the GRAPHlC-2
executive system includes a linking loader that runs
on the PDP-9. The equivalent routines in the GE-645
version are also kept on a library file. A critical element
in the system is the "unique ID maintainer." In Section VI on the GRAPIDC-2 executive system it was
pointed out that all program and data blocks in the
GRAPHIC-2 have a I7-bit ID number associated with
them. A complete dictionary of all blocks with assigned
.ID's is kept in the GE-645. This dictionary establishes
a unique correspondence between blocks in or referred
to in the GRAPHlC-2 and the equivalent block in the
GE-645. Whenever GRAPHIC-2 needs a block of any
kind it asks for it by ID number. The ID table must
be used to locate the desired block in the GE-645.
The block is then converted to GRAPHlC-2 format
(if it is part of the Graphic Data Structure) or retrieved from the GRAPHlC-2 program file (if it is a
program block) and sent over the communication link
to the remote terminal. The unique ID assigned to a
block is a dynamic operation that occurs during program execution and is completely invisible to the programmer.
Multi-Function Graphics for Large Computer System
The "real-time-input" simulator in the GE-645 is
invoked wherever one of the real-time GRIN-2 statements is encountered in the GE-645 program. It simply
supplies the next argument (or arguments) found on
the input queue sent over from GRAPHIC-2. 'This
allows the GE-645 version to undate its version of the
Graphic Data Structure to corresRond with events taking place at the remote terminal.
SUMMARY
A flexible graphics system that provides users with
several different types of service h~s been described.
Several devices of each available type are provided to
inSure good access to the system for many people. The
system is intended for use in an environment where
users do most of their own programming. Therefore,
software support is provided that makes programming
graphical I/O fairly simple.
A wide range of applications is expected. These in1 START
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
HOME
DRAWPG
DRAWl
MOVEPO
DLTPG
LEAF
TEXT
LEAF
TEXT
LEAF
TEXT
NODE
BRANCH
NODE
BRANCH
NEWDSP
WHICH
GOTO
WHERE
LEAF
BRANCH
DRAW
GOTO
WHICH
TCMOVE
WHERE
WHICH
DETACH
OOTO
Statement 1 generates a leaf in the data structure and a
pointer to that leaf is placed in DRAWLB. The displayable text "DRAW" is then placed in the leaf
(STATEMENT 2); statements 3,4,5 and 6 generate
two more leaves with the text "MOVE" and "DELETE"
in them. Statement 7 generates a node LTBTNS and
three branches Bl, B2, B3 (one connecting each
of the three leaves to the node LTBTNS). These
709
clude data plotting, circuit mask design and analysis,
generating of motion pictures, text editing, and many
more.
ACKNOWLEDGMENTS
The authors gratefully acknowledge the contributions
of many colleagues in the Information Processing Research and Machine Aids to Development Departments.
In particular, we wish to thank A. D. Hause for valuable
suggestions during the design of the system and L.
RosIer for helping to crystallize many features of the
GRIN-2 language.
APPENDIX
The following is a commented example of a graphically interactive program written in GRIN-2. This program allows an operator at a GRAPHIC-2 terminal to
draw, move or delete broken line segments on the face
of the scope with a light-pen.
DRAWLB
(D,R,A,W)
MOVELB
(M,O,V,E)
DLTLB
(D,E,L,E,T,E)
LTBTNS( (Bl",DRAWLB,DRAWPG)
(B2, (0,-30) ,MOVELB,MOVEPG)
(B3,(0,-60) "DLTLB,DLTPG) )
LBBRAN" (950,950) "LTBTNS
DRAWND
DRAWBR" "DRAWND
(LBBRAN,DRAWBR)
,TRA
HOME
WHICHX,DRAWI
DRLEAF
DRBRAN,DRAWND,WHEREX"DRLEAF
WHEREX
HOME
,SAME
WHICHB
WHICHX,HOME
,SAME
WHICHB
HOME
branches are also declared light buttons with the associated programs DRAWPG,MOVEPG and DLTPG.
Different delta xy values are given in the three branches
so that the three leaves (light-buttons) will be displayed at different locations on the scope. Statements
8, 9 and 10 then generate two more branches and a
node. The total structure generated by statements 1
through 8 is then shown in Figure 15a. The node
710
Fall Joint Computer Conference, 1967
DRAWND is a place to attach more structure when
the DRAWPG light-button program gets control. Statement 11 specifies that the branches LBBRAN and
DRAWBR and all the structure below them are to be
displayed (Figure lSb). Control then is held in statement 12 asking the question "WHICH function should
be performed next?" The TRA argument on the
WHICH statement specifies that when a light-button is
picked control should be given to its associated program. If a non-light-button were picked (impossible
now since there are none), then control would pass
to statement 13 which passes it back to 12 (WHICH).
This in effect ignores any non-light-buttons and forces
the operator to pick a light-button. Pointing to "DRAW"
on the scope gives control to DRAWPG, "MOVE"
to MOVEPG and "DELETE" to DLTPG. Assuming
the operator picked "DRAW" with the light-pen, the
DRAWBR
LBBRAN
6x=0
6y=0
6x=950
6y=950
first question asked by the drawing program DRAWPG
is "WHERE should the broken line start?" The argument WHICHX in statement 14 is a pair of system
locations which contain the scope coordinate of the
light-pen strike that answered the last WHICH question. In this case this is the x,y location of where the
"DRAW" light-button was touched. This intilizes the
tracking cross to appear under the light-pen. The operator then moves the tracking cross to the place he wants
to start drawing. Pushing a button on the keyboard
causes control to pass to DRAWl as specified by the
second argument in statement 14. At this point the
scope coordinates of the tracking cross are contained
in a pair of system locations WHEREX. DRAWl then
generates a leaf DRLEAF and connects it to the node
DRAWND with a branch DRBRAN. The initial position
is also inserted in the branch with the WHEREX argument. The DRAW statement (17) then gets control
along with the starting location WHEREX ( answer
from the WHERE question, statement 14). The operaLBBRAN
6x=950
6y=950
DRAWBR
6x=O
6y=O
DRBRAN
SPECIFIED
6X= } WITH
6y =
r -..........~
TRACKING
CROSS
1023,1023
0,1023
DRAW
MOVE
DELETE
DRAW
MOVE
DELETE
B
B
0,0
NOOE
0
1023,0
~
BRANCH
NODE
0
~
BRANCH
LEAF-O
LEAF-O
LEGEND
LEGEND
Figure 15-Structure and display for the GRIN-2 example
(Appendix)
Figure 16-Structure and display for the GRIN-2 example
(Appendix)
Multi-Function Graphics for Large Computer System
tor uses two buttons on the keyboard, one to indicate
corners and one to indicate the end of the broken line
segment. By repeated calls to WHERE and VECTOR,
the DRAW statement allows the operator to draw on
the scope. When he pushes the end-of-line button on
the keyboard, control is passed to the next statement
(18) which passes control back to the portion of the
program which asks "WHICH function should be performed next?" Figure 16 shows the structure and picture at this point.
If the "MOVE" light button is picked with the light
pen, MOVEPG will get control. This program then
asks "WHICH branch should be moved?" (statement
19). The "SAME" argument specifies that light-buttons should be treated the same as non-light-buttons.
In this case it means the light-buttons, as well as the
non-light-buttons, can be moved around the scope.
When the operator picks a branch to be moved, control passes to statement 20 which "attaches the object
picked (answer left in WHICHB) to the tracking cross.
The program then asks "WHERE should the branch
be moved?" (statement 21). The picked object then
moves with the tracking cross as it moves to follow the
light-pen. The argument HOME specifies that control
should pass to HOME when a button on the keyboard
is pushed, indicating that the moved object is positioned
to the satisfaction of the operator. The "DELETE"
light button program should now be obvious.
5
6
7
8
9
to
11
12
13
REFERENCES
I E SUTHERLAND
Sketchpad: A man-machine graphical communication system
Proc. AFIPS Spring Joint Computer Conference, vol.
23, pp. 329-346 1963
2 E L JACKS
A laboratory for the study of graphical man-machine
communication
Proc. AFIPS Fall Joint Computer Conference, vol. 26,
pp. 343-350 1964
3 G J CULLER B FRIED
The TRW two-station on-line scientific computer
Computer Augmentation of Human Behavior
4 K C KNOWLTON
Computer produced movies
System Analysis by Digital Computer, edited by F. F.
Kuo and J. F. Kaiser, John Wiley and Sons, New York,
Chapter 11, pp. 375-394 1966
14
15
16
17
711
F H HARLOW J P SHANNON J E WELCH
Liquid waves by computer
Science, vol. 149, no. 3688 p. 1092 September 3, 1965
H C SO
Analysis and iterative. design of networks using on-line
simulation
System Analysis by Digital Computer, edited by F. F.
Kuo and J. F. Kaiser, John Wiley and Sons, New York,
chapter 2, pp. 34-58 1966
W R SUTHERLAND
The on-line graphical specification of computer procedures
Lincoln Laboratory Technical Report no. 405, Lexington.
Massachusetts 1966
WHNINKE
GRAPHIC-I: A remote graphical display console system
Proc. AFIPS Fall Joint Computer Conference vol. 27,
pp. 834-846 1965
F J CORBATO V A VYSSOTSKY
Introduction and overview of the multics system
Proc. AFIPS Fall Joint Computer Conference, vol 27,
pp. 185-196 1965
E L GLASER
System design of a computer for time-sharing applications
Proc. AFIPS Fall Joint Computer Conference, vol. 27,
pp. 197-202 1965
V A VYSSOTSKY F J CORBATO R M GRAHAM
Structure of the multics supervisor
Proc. AFIPS Fall Joint Computer Conference, vol. 27,
pp. 203-212 1965
R C DALEY P G NEUMANN
A general-purpose file system for secondary storage
Proc. AFIPS Fall Joint Computer Conference, vol. 27,
pp. 203-212 1965
J F OS SANNA L MIKUS S D DUNTEN
Communications and input-output switching in a multiplex
computing system
Proc. AFIPS Fall Joint Computer Conference, vol. 27,
pp. 213-230 1965
H S McDONALD W H NINKE D R WELLER
A direct-view CRT console for remote computing
Digest of Technical Papers, 1967 International Solid-State
Circuits Conference, vol. to, pp. 68-69.
W H NINKE
A satellite display console system for a time-shared
computer
In Preparation
D T ROSS J E RODRIGUEZ
Theoretical foundations for the computer-aided design
system
Proc. AFIPS Spring Joint Computer Conference, vol.
23, pp. 305-322 1963
L G ROBERTS
Graphical communication and control languages
Proc. Information Systems Sciences Second Congress~
pp. 211-217 1964
Reactive displays: improving man-machine graphical
communication
by JOHN D. JOYCE and MARILYN J. CIANCIOLO
Research Laboratories
General Motors Corporation
Warren, Michigan
INTRODUCTION
The on-line graphic representation and solution of
problems is opening the door to new and exciting
computer applications. Continuous man-machine
interaction via graphic consoles makes feasible the
solution of entirely new classes of problems. This
expanding use of computer graphics is requiring improved techniques of man-machine communication
and graphic data management. At the General Motors
Research Laboratories, we have had the opportunity
since 1962 for considerable experimentation in a manmachine environment. From these experiments new
ideas have evolved about how to improve the two-way
information flow between the console user and the
computer model of his problem. A fundamental concept is the reactive display, which supplies immediate
graphical response to the actions of a man at a console. We have found that reactive displays provide a
good basis for interaction between the man and the
individual phases of his problem.
A problem to be solved is that of providing a good
foundation in graphic displays. The characteristics
of this foundation must be such that console users can
easily do productive work at a console for several
hours per day. These console users in general will
have no computer training and will have no inclination or desire to become encumbered by the intricacies of conventional computer work. These users
may be designers, draftsmen, electrical engineers,
or project planners who merely want to communicate
with a console in order to get a job done. Our experiences have demonstrated that using alphanumeric
language statements to produce graphic displays is
not the best environment for the types of console
users mentioned above. An alphanumeric language is
an abstraction of a problem which is harder to understand than a pictorial abstraction of a problem. For
example, a project planner could describe all the
activities of a project, their durations and the precedence relationships which exist among the activities, solely with an alphanumeric language. However,
this same information is much better described with a
PERT diagram.
Let us consider some of the steps involved in using
a computer to help solve a problem. For a segment
of a problem, a sequence of one or more procedures is requested, several data items are entered as
inputs to the procedures and results are produced.
Certain sets of procedures have specific relationships.
Only certain sets of data items satisfy requirements for
particular procedures. All other data items can
be considered to be background or contextual information when a particular procedure is in control. A foundation for graphic displays must provide the facilities
for representing and allowing the selection of individual procedures, actions, and data items pictorially.
It is also essential that the graphic system dynamically
represent changing relationships among" various sets
of procedures and data items. Many errors can be
eliminated by only allowing selection of syntactically
correct inputs and by providing dynamic feedback to
ease the correction of other human errors.
Let us assume that a project planner wants activity
A to have a longer duration, a different description,
and different precedence relationships; also, that a
PERT diagram is displayed on the console and that a
"Change Activity" procedure is in control. All precedence lines are made non-selectable by a light-pen.
However, all precedence lines remain displayed so
that the activities are viewed in context with the precedence lines. The user places the light-pen on the
screen. Activity B becomes brighter. Although this
selection is syntactically correct, the user has made a
human error and adjusts the light-pen position until
Activity A becomes brighter. Satisfied with the immediate feedback the user removes the pen from the
713
714
Fall Joint Computer Conference, 1967
screen and now a different set of items can be changed,
i.e., (a) the description of A, (b) the duration of A,
and (c) the lines of precedence of A. And so the process .continues with different sets of display entities
changing to reflect the ever-changing status of the
problem.
Objectives
Three aspects of a graphic system will be presented.
(See Figure 1.) First, we shall discuss some of the
human factors of computer graphics, i.e., what is the
best problem-solving environment for the man at a
console. Second, we shall describe in detail the graphic
programming system. They key elements of this system, its internal structure, and the advantages and
disadvantages of certain implementation techniques
will be presented. By graphic programming systems
we mean the software support which is the linkage
between the display hardware and the applications
programmer. Third, we shall consider the facilities
as seen by the applications programmer. It is his job
to build upon the graphic programming system a
graphic language which will best communicate with
the console user.
COMPUTER
MODEL OF
PROBLEM
~
-----.
APPLICATIO NS
PROGRAMS
t
~
I
I
I
"
DISPLAY
ENTITY
DESCRIPTORS
~
GRAPHIC
SYSTEM
PROGRAMS
~
.
I
I
I
I
,.
..
DISPLAY
DATA
:4
•
.---~
•
REGENERATION
- - - - -.
BUFFER
PROGRAM
DATA FLOW
PROGRAM CONTROL
Figure I - Graphic system programs as an interface
In this paper we shall limit -ourselves to a discussion of the tools we have designed and implemented
to interface between the applications programmer
and the graphic console user. We shall make no
attempt to discuss the design or implementation of a
graphical language. Many kinds of man-machine
communications media could be built atop the graphical system we discuss in the following pages.
Definition of terms
A few terms will be defined here for clarity. These
definitions are not suggested as general definitions
but only for their use in the remainder of the paper.
A user or console user will refer to a person who
manipulates console controls such as a light-pen
function buttons, typewriter, etc., to do productive
functions such as mechanical or electrical design or
parts layout. This person usually has no knowledge
of computer hardware or software and is only interested in the console as a tool to get his own job
done.
An applications programmer shall mean the person
who provides the software to do specific productive
jobs. This software is built upon the graphic system
software and the time-sharing system software.
A graphical language is considered to be one in
which communication at the CRT is carried out by
continuous interaction with pictorial representations
of a problem. In such a language very little use is
made of alphanumerics, except for labels and a few
key control words. A language which generates pictures from executing groups of alphanumeric statements is- not considered to be a graphical language.
The human factors of graphics refers to all aspects
of communication with a man at a console. The object here is to provide the maximum comfort and convenience of operation for a console user and to increase efficiency by keeping good response time and
eliminating obvious sources of errors of syntax. These
points will be discussed in more detail under the section on Man-Machine Communication Techniques.
Man-machine communication techniques
No graphical communication system will be an effective problem-solving tool unless it is natural and
convenient to use. Consequently, at the G M Research
Laboratories we have given a great deal of attention
to optimizing user satisfaction. The fundamental
goal has been to bring the man ever closer to direct
communication with a computer. This communication should be in a conve'rsational graphical language
which the man understands.
Reactive Displays
715
Discrete problem elements and procedures
The beginnings were primitive: a display was
thought of as one large picture, a kind of visual feedback. Language statements were fed into a card reader
by the user and executed. The results were displayed
on the console screen. Gradually, console use expanded to communication more directly in graphics.
I t was not evident in the beginning that working
toward a solution of a graphical problem involved
the manipulation of individual data elements. For
example, a mechanical parts designer will work with
an individual line when he is changing the design. An
electronic circuit designer will change a circuit by
working with an individual component and its relationship to other components.
Focusing the user's attention
Another aspect of external communication was not
apparent during initial attempts at a graphic system.
This is the need to gain the attention of the console
user by directing him to a certain portion or portions
of the display. There are many ways of achieving
this: possible methods are intensification, blinking,
modulation of size, or changing the color of portions
of the display.
After investigating several possibilities, we concentrated on the use of intensification for highlighting parts of a display. For example, the four boundary
lines of a surface may be brightened while the interior lines are dimmed. This technique of varying
intensification has proven to be an important piece
of feedback to the console user. We call the preceding example "static" intensification because an item
remains intensified throughout the current display.
Static intensification can be used meaningfully
in other ways, besides highlighting. For example,
user attention can be focused on suggested choices of
control words by brightening them, while dimming the
rest of the display. Shading to give a three-dimensional effect is also useful in optimizing the user's
understanding of a display. This technique, however,
requires enough intensity levels so that the transition between them is continuous and imperceptible.
Dynamic intensification is a more important form
of brightening. An item, a line and its label for example, is displayed at a very high level of brightness
during the time that the pen is pointing at it. (See
Figure 2). Whenever the pen moves to a void area,
nothing is intensified. If the pen is pointed at another
part of the display, that part will be intensified. Intensification of the selected item is feedback that tells
the console operator exactly what he is pointing at.
When the operator is satisfied with his selection,
he removes his pen from the screen.
Figure 2 - Dynamic intensification of a display entity
Restricting selectability of display items
Another important· mechanism in the restricting
of selectability to only certain items or" classes of
items in the display. It is obvious that some background information such as borders or grid lines may
be displayed, but is never selectable. Perhaps not so
obvious is that, frequently in reactive displays,
classes of items should be made non-selectable. The
console user might, for example, wish to execute a
line smoothing procedure. He will probably be required to indicate the line in which he is interested.
At this point in time, then, only lines should be candidates for selection. All other kinds of items should
be "disabled" for detection. Further, only lines should
be giving a feedback response in the form of dynamic
intensification.
This "selective disabling" aids the operator in recognizing his displays as a composition of various sets
of items. In addition, he will be less confused when
trying to make a selection. Only a small subset of
items can be selected, even though other information
is still displayed. Thus, the selectable items are kept
is context with the rest of the display. The combination of selective disabling and dynamic intensification provides the means of conveying the syntax
of a graphical language to the console user.
Other techniques
There are other human factors involved in console
use, which are not a direct concern of the graphical
systems designer. They merit attention because these
external criteria must be met with a minimum of effort
by the graphical language implementer.
716
Fall Joint Computer Conference, 1967
In production design work, for example, console
users are sometimes at work for several hours or more.
This prolonged use clearly indicates the need to minimize the number of manipulations required to solve
a problem, e.g., the number of "pokes" at the screen.
It is the job of a good graphical system to interface
with the graphical language in meeting this important
requirement.
The graphical language can further enhance user
understanding by providing the ability to
(a) change the scale or size of the data,
(b) change the direction of view,
(c) rotate or otherwise transform data,
(d) label items on the screen.
When the user sees these actions carried out in continuous motion, under his control, his visualization
of the problem is improved. A good graphical system
lays the groundwork for implementing these capabilities. It does this by providing the means of effortless communication between the applications programmer and the graphic device.
All the graphical techniques just described help to
improve the all important information flow, the conversation, between the computer and the man. Each
small part of the display now becomes a variable
under the control of the man. He can follow the progress of his problem and analyze intermediate results.
He can, in fact, change the flow of activity to an entirely new direction. He is continuously reacting to
the everchanging display, and equaJly important, the
display is reacting to him.
A characteristic of the above graphical communication techniques is the high burst rate of information
flow. A console user can receive information with his
eyes at rates as high as 4.3 X 106 bits/second.! He can
transmit decisions back to the computer at rates as
high as 102 bits/second. These high tates, although
they cannot be sustained, do require an internal data
structure which provides efficient display handling
and good response time.
Graphic programming system
Elements of a reactive display
The preceding paragraphs have described some of
the external requirements met by the graphic programming system at the GM Research Laboratories.
It is now appropriate to consider the basic internal
structures that can help meet these needs most
efficiently. (See Figure 3.)
As mentioned earlier, a display can be thought of
as one large picture. This means display changes require working with the entire display. Another
approach is to change a display by manipulating only
o
~w
:::>u
zoo(
:::>8;
~
00(
z
:
w
VI
II
'"
0-
w
VI
11
l!
...
~
i3
8
o
C>
Figure 3 - Elements of reactive displays
a small part of it. This involves a decomposition of the
large display into smaller displays called "entities."
An entity may be defined as a distinct collection of
displayable data to which the user may wish to make a
unique reference. It represents some meaningful part
of the model of the problem. The display data comprising an entity may be any combination of vectors,
characters, or points. I t may be scattered anywhere on
the screen.
Each entity has display attributes assigned to it,
which determine its external characteristics. It is
described by a level of beam intensity and the attribute of selectability or non-selectability. Further, to
Reactive Displays
speed internal manipulation, each entity may be
classified by its membership in a set(s). The membership of each entity in zero or more sets determines
its relationship to the other entities in the display.
In addition, the relations between display entities reflect the relations of the data items to which they
correspond. To further aid in rapid data management,
a two-way direct link has also been established between every displayed data item or control word and
its display buffer counterpart.
The use of these basic structural ideas has helped
to create a graphic system which can quickly and
effectively handle the flow and manipulation of
graphical data. The system affords a natural means
of communication with the console user and, at the
same time, ease and flexibility to the applications
programmer.
Structure for entity descriptors
The need for flexible graphic control has impressed upon us the importance of certain internal
requirements. No matter what type of display system
is being implemented, it is useful to have blocks of
entity descriptors, each of which describes an entity
and its properties. Blocks in current use are linked
together in a ring structure. (See Figure 3.) In the
same way, unused blocks are linked together in a
"free space" ring. They can be obtained quickly
when another entity is to be added. Each active block
contains a pointer to the previous entity and to the
next entity, information about the entity attributes,
and the size and display buffer location of the entity
data. (See Figure 3.) It is assumed that the display
data itself resides in the display buffer memory. The
order of the entity descriptor ring matches the order of
regeneration in the display buffer. This implicit information is used when adding or deleting entities.
It might be argued that a separate ring structure to
describe display entities is unnecessary. Display
characteristics could be included in a ring structure
which described the data elements themselves. However, our experiments have indicated that a great deal
of CPU processing time, as well as time to access
peripheral storage devices,* was required to search the
data ring structures. A less time-consuming method
must be used to manipUlate display entities since online response time is a major consideration in graphical
work.
*To minimize the amount of CPU memory used most of the large
data structure was maintained on high-speed drums. Searching a
ring structure which threaded through the data often involved
bringing many "pages" of data into CPU memory. Access time to a
given data item was a function of the depth at which it was buried
in the ring structure.
717
Data elements which correspond to display entities
are generally a small subset of those which describe
the entire problem. Thus a small amount of memory
can contain a ring structure that describes the display
characteristics of displayed data elements and the
displayed control words, which have no data element
counterpart.
The compactness of entity descriptor information
offers advantages in both a paging and non-paging environment. 2 ,3 With paging and ring structures the
descriptor blocks can be contained within one or two
data pages. If it is assumed that pages will remain in
memory based on frequency of use, then the blocks
will nearly always be accessible without retrieval from
a peripheral device. If the blocks are "paged out"
while the console user is thinking, their compactness
will permit rapid retrieval. The blocks will remain in
memory so long as frequency of graphic attentions is
high.
In the non-paging environment the small size of the
entity descriptor ring makes it possible to keep it in
the CPU. Many additions and deletions of blocks can
therefore be carried out quickly and thus, maintain
good response time for the console operator.
Control of execution sequences
It is important to give to the applications programmer the ability to enable or to inhibit the use of hardware features. These might include a light-pen, an
alphanumeric keyboard, or programmed function
keys. A single interrupt handling code in the graphics
system dispatches control to the appropriate place
when these features are activated. Transfer of control is carried out by having the user supply an
"owner" (in the form of a program name or statement
label) for each hardware feature and each display
entity. The owner is recorded in an appropriate control block. When an enabled feature or entity is
selected, control is transferred to the corresponding
"owner." This eliminates the need for applications
programs to decode attention information.
Linking display entities and problem elements
Problems of search and table look-up are eliminated
by a direct two-way link between a display entity and
the data element to which it corresponds. The applications program assigns to each entity a name or
pointer which either has a distinct meaning in the computer model of the problem, or is a direct pointer to
its associated data element. A graphics system program provides another pointer which is guaranteed
to be unique. This pointer is directly linked to an
entity for subsequent changes to or deletion of that
718
Fall Joint Computer Conference, 1967
entity. When an entity is selected, both pointers are
returned to the owner program. Experiments have
shown that a direct two-way link between a display
entity and a data element maximizes efficiency in
manipulating the display.
BEGIN ENTITY
SET ENABLE-DISABLE STATUS
SET INTENSITY
Display hardware capabilities
In order to make the two-way pointer system work
most effectively, the display controller hardware
should have certain logical capabilities. Without
CPU intervention the controller should be able to
"name" every new entity as the pen passes over that
entity. It can do this by physically moving the name or
label of the detected entity to a fixed buffer location.
When the final selection is indicated by the man removing his pen from the screen, the graphics system
program needs only to read the contents of that fixed
buffer location. The pointer to the corresponding
data element or control word is thus available without
. any further processing. To make the concepts of
reactive displays most effective in a time-sharing
environment, it is desirable to reduce the number of
CPU interrupts to a minimum.
We found this could be best accomplished by
making additional demands of the graphic hardware.
Specifically, we needed the ability to perform dynamic
intensification of display entities without CPU intervention. We also needed to handle display attributes
from within the controller. This required hardware
control of display intensity and the enable-disable
status of entities.
These capabilities imply that the display controller
can:
(a) detect light and remember this information,
(b) do a conditional transfer on the remembered
detection,
(c) move the name of the detected entity to a specified location,
(d) control beam intensity with a single buffer
order,
(e) enable or disable graphical data with a single
buffer order.
(See Figure 4.)
Associative relationships among entities
A graphical display is simply a visual representation which helps the console user to understand a
computer model of his problem. Within this model
relationships exist between one data item and other
data items. In a job scheduling model, for example,
a given job is related to all the jobs which must be
completed before that given job -is begun. In the model
ofa design problem two points are related by a dis-
AGAIN
DISPLAY ENTITY DATA
(CHARACTERS, POI NTS,
OR VECTORS)
TRANSFER ON NO LIGHT PEN
DETECT TO NEXT ENTITY
DISABLE FOR DETECTS
SET INTENSITY HIGH
MOVE LABEL TO FIXED BUFFER
LOCATION
TRANSFER TO AGAI N
Figure 4 - Entity structure in display buffer
tance. Another .kind of relationship exists in which
one data element is related to others because they are
members of the same set. For example, all lines in a
drawing belong to one set, while all lines which belong
to Surface A comprise a sub-set of the original set.
The need to manipulate data items based on associative relationships is illustrated by the fact that
whole new languages have been written expressly for
that purpose. 4 ,5 We have found that in manipUlating
graphical display entities, it is at least necessary to
work with sets of entities or logical combinations of
sets of entities. Suppose, for example, that at some
point in time only a "line entity" which lies on
"Surface A" is an acceptable screen selection. The
entities in this set need to be rapidly enabled for
operator selection, while all others should be disabled. At some other point in time all "point entities"
on a "Centerline" should be brightened, or only the
control words "LINE SMOOTHING" or "SURFACE EVALUATION" may be applicable. The
display system must be able to react rapidly to· such
requested changes in display characteristics.
From the above examples we see that the relationships among display entities are simply a reflection of
the relationships which exist among their corresponding data items. We have found it sufficient to record
Reactive Displays
the set membership of entities in the entity descriptor
blocks. Tests on an experimental system indicated
that the assignment of each entity to membership in
one or more sets was convenient and adequate to
handle display manipulations based on associative
properties.
.
Handling the associative relationships among dIsplayed items on an entity basis means that the graphical system does not need to work with the entire data
structure. Since the data set for the entity descriptors
is almost always smaller than the total data set for the
model of a problem, there is a real advantage to the
above method. In addition, display characteristics are
tied directly to the associative relationships. Display
changes are thus speeded up because the same program which searches for the requested set of entities
can change the appropriate display characteristics
at the same time. In a data environment where the
associative relationships among data items are not
considered at all, handling sets of display entities
at the graphical system level provides a capability not
otherwise possible.
The applications programs supply the names of the
sets (if any) of which each entity is to be a member.
The graphic system saves these names and the information about the set membership of each entity. As
additional entities bec~me members of existing sets,
they are marked as such. A new set is created whenever an entity has membership in one or more sets
which are currently unknown to the graphic system.
Sets may become empty when entities are deleted,
or whenever set membership of one or more entities
has changed. Empty sets are autom'atically purged
from the system when the additional space is required
for new sets.
An incident matrix was selected to record the membership of entities .in various sets. The expected
maximum number of entities (150-200), the maximum
number of sets (25-30), and the distribution of entities among sets indicated that an incident matrix
would conserve storage and computer time. One row
of the matrix is stored with each entity descriptor.
The disadvantage of this method is that it is difficultto accommodate more than an arbitrary number of
sets at a given time. A ring structure could be used to
describe associative relationships, but would require
more computer time and storage.
Logical combinations of sets of entities may be
deleted or have their properties changed by one request from the applications program. Any combination of sets which can be expressed by "AND,"
"OR," and "NOT" operations can be handled.
Some of the more frequently used combinations are of
the following types:
719
. h are members of Set A "OR"
(a) entities whlc
Set B,
(b) entities which are members of Set A "AND"
Set B,
(c) entities which are members of Set A "OR"
Set Band "N OT" of Set C.
These unlimited combinations of sets have provided
facilities for making display changes conveniently
and efficiently. The ability to make such changes
provides a syntactical basis for graphical displays.
Display butTer management
No system restrictions have been placed on either
the size or number of display entities which can exist
at one time. The physical size of the regeneration
buffer provides an upper limit. When an entity is
deleted from the display buffer, the space it occupied
is given back to the graphic system. The regeneration
cycle is altered only to the extent that pertinent
transfer addresses are changed. The entity previous to
the deleted entity now transfers to the entity which
followed the deleted entity. This method of deletion
has several advantages:
First, there is no need for the system to maintain
a copy of the regeneration data in CPU memory.
Second, no processing time is required to recreate the
regeneration cycle and store it as a contiguous block
in buffer memory. Third, the amount of dat~ transferred to the display buffer is minimal.
To summarize, entity deletion as described above
saves CPU memory space, CPU processing time, and
I/O time. One disadvantage of this method is that
variable length blocks of unused space remain in the
buffer. Since these holes mayor may not be large
enough to accommodate a new entity, efficiency of
space usage becomes an item of concern.
A graphic system using variable length entities
and this form of deletion was written and sampled to
test fragmentation of the buffer memory. The results
indicated that only a moderate percentage of space
was wasted on holes interspersed among entities. Extensive testing showed that the number of holes did
not usually exceed 10% of the maximum number of
entities. Even with complex applications, the number
of entities does not normally exceed 150-200 within
the framework of current CRT sizes and regeneration
buffers. This means that small CPU memory table
can accommodate all the information needed to
manage buffer space allocation.
a
Facilities for applications programmers
The capabilities of the graphic system described
in this paper are available to the applications pro-
720
Fall Joint Computer Conference, 1967
grammer for a high-level language (PL/I). The following can be easily accomplished:
(a) Creation of new display entities
(b) Deletion of entities
(c) Modification of entity properties
(d) Modification of entity data
(e) Modification of properties of logical combinations of sets of entities
(t) Deletion of logical .combinations of sets of
entities
(g) Enabling of hardware functions (typewriter
keyboard, function buttons, light-pen for
positional input)
.
(h) Temporary inhibition of all interrupts and
re-enabling for interrupts again
Each one of the functions listed above is available by
an individual subroutine call in PL/1. The programmer
provides only X, Y data and attribute information
when he creates an entity. He need not be concerned
about the management of space in the display buffer.
All display control orders and logic are generated
automatically by a graphic systems routine. I/O generation and transmission are also done automatically.
When the graphic system has information to present to the problem program, CPU control is transferred to the appropriate "owner" location. This
location was previously indicated to the system for
each display entity and hardware function. The system also makes available information about the interrupt type and, if applicable, the X, Y position of
the pen.
The applications programmer is thus freed from the
task of interfacing his computer model of a problem
with the display hardware. The two-way information
flow is carried out quickly and efficiently at a systems level. The result is good response time and economical CPU operation.
SUMMARY
The principles of reactive displays can be used in
many different computer console arrangements. At
General Motor-s Research Laboratories three graphic
systems have been written, all of which utilize the
concepts described in this paper. (See Appendix.)
In spite of internal dissimilarities and hardware differences, these three systems provided nearly identical capabilities to the applications programmer.
The reactions of both the applications programmers
and console users have been enthusiastic. The applications programmer appreciates the flexibility and
efficiency of the system. He can easily communicate
with the graphic hardware and has access to specific
information about user respones. Console users in-
dicate that they especially like the dynamic intensification of entities and fast response time. They
also appreciate the selective enabling of only meaningful entities. From the standpoint of internal efficiency, our current thinking is that graphic systems
based on concepts of reactive displays offer maximum speed and ease of data manipulation.
Appendix
Three graphical systems using the principles discussed in this paper have been implemented at the
General Motors Research Laboratories. The main
features in these systems are listed in Table I.
SYSTEM A
SYSTEM B
SYSTEM C
CPU
IBM 7094
IBM 360/50
IBM 36CV67
LANGUAGE
NOMAD
PI/I
PI/I
TIME-SHARING
TIME-SHARING
SOFTWARE
ENVIRONMENT
DISPLAY
CONSOLE
MULTIPROGRAMMING
DAC-I CONSOLE
IBM 2250-1
IBM 2250-111
REGENERATION
BUFFER
WITHIN CPU
ONE PER
CONSOLF
SHARED
BUFFER
(IBM 2840-11)
DISPLAY
CONTROLLER
LOGIC
ALMOST
NONE
LIMITED
AMOUNT
MODEtATE
AMOUNT
POINTING
DEVICE
VOLTAGE
PENCIL
LIGHT
PEN
LIGHT
PEN
Table I - System configurations
The first system was built upon the software and
hardware of the DAC-I System. 6 •7•S The IBM 2250-1
consoles used in the second system were used for
program checkout until the IBM 2250-111 consoles
and 2840-11 controller were installed. This latter combination of hardware included, in addition to the
Graphic Design Feature, orders for a conditional
transfer on light-pen tip switch open and orders to
control display intensity.
ACKNOWLEDGMENT
The authors wish to express their appreciation to
Edwin L. Jacks and Fred N. Krull for their help in
the development of the ideas presented in this paper.
REFERENCES
H.JACOBSON
The informational capacity of the human eye
Science, vol. 113, b, pp. 292-293 1951
2 J G DENNIS
Segmentation and the design of multiprogrammed computer
systems
· D·lSP1ays 721
Reactive
3
4
5
6
7
8
J. of Association for Computing Machinery vol 12 no 4
pp 589-602 October 1965
B WARDEN B A GALLER T C O'BRIEN F H
WESTERVELT
Program and addressing structure in a time sharing environment
J. of Association for Computing Machinery vol 13 no I
pp 1-16January 1966
GGDODD
APL-a languagefor associative data handling in PL/I
1966 Proc FJCC vol 28 pp 677-684
L G ROBERTS
Graphical communication and control languages
Second Congre~s on the Information System Science Spartan Books Washington D C 1964
E LJACKS
A laboratory for the study of graphical man-machine communication
1964 Proc FJCC vol 26 pp 343-350
B HARGREAVES J 0 JOYCE G L COLE et al
Image processing hardware fO'ra man-machine graphical
communication system
1964 Proc FJCC vol 26 pp 363-386
M P COLE P H DORN C R LEWIS
Operational software in a disc-oriented system
1964 Proc FJCC vol 26 pp 351-362
BIBLIOGRAPHY
I SHCHASEN
The introduction of man-computer graphics into the aerosuace industry
1965 Proc FJCC vol 27 pp 883-89 I
2 TEJOHNSON
Sketchpad Ill: A computer program for drawing in three
dimensions
1963 Proc SJCC vol 23 pp 347-353
3 WHNINKE
Graphic J-A remote graphical display console system
1965 Proc FJCC vol 27 pp 839-846
4 MDPRINCE
Man-computer graphics for computer-aided design
Proc. of IEEE vol 54 no 12 pp 1698-1708
December 1966
5 D E RIPPY 0 E HUMPHRIES
MAGIC-A machine for automatic graphics interface to a
computer
1964 FJCC vol 27 pp 819-830
6 RSTOTZ
Man-machine console facilities for computer aided design
1963 Proc SJCC vol 23 pp 323-328
7 I ESUTHERLAND
Sketchpad: A man-machine graphic communication system
1963 Proc SJCC vol 23 pp 329-346
Graphic language translation with a language
independent processor
by RONALD A. MORRISON
General Electric Company'
Cincinnati, Ohio
INTRODUCTION
Since January 1963 when "Sketch Pad, A ManMachine Graphical Communication System"· by
Ivan E. Sutherland was published as a Ph.D. Thesis
at M.LT., graphic displays on computers have been
used for a variety of experimental2 •3 and production4 purposes. The motivation behind the system
described here, is to provide an interactive graphic
input/output facility to a number of existing software
systems. Our business, like many others, has developed over the past 10 years a number of sophisticated and complex "Computer Aided Design"
systems. These systems include principally numerical
control part programming systems ('and engineering
design analysis systems. Although these systems have
proven themselves to be a necessary part of the
design, and manufacturing process, nevertheless
preparing input and assimilating output is still a time
consuming process for the users. The interactive display speeds up these processes. Its output is more
meaningful, too, since pictures as well as numbers and
text are used as communication media between the
man and the machine.
The term "graphic language" has been used ambiguously, in the literature, to describe at least three
different types of language used in graphic processing.
1. The input stream is in the form of actions taken
by a console operator.
a. draw with light pen
b. type names and numbers
c. push buttons
d. light pen references of objects on the screen
A language translator translates these actions
into invocations of appropriate procedures.
These procedures perform requested actions
and provide displayed feed back to the user.
2. Input is in the form of pictures existing on film
or other media. In this case the language trans-
lator is a pattern recognizer which recognizes
and extracts meaning from these pictures. 5
3. A set of programming tools (functions and subroutines) are embedded in a "host" language
(e.g. FORTRAN). Using these tools Ijghtens
the load of the programmer of the, graphic
system.
The primary concern of this paper is the language
and corresponding processor discussed above as type
one. A set of service functions and subroutines (type
three above) are also embodied in the system but are
of secondary importance.
The system described here borrows freely from the
best of earlier graphics work. It is set in an environment similar to GRAPHICS J2 (i.e., a remote display
with local compute power communicating with a
central multiprogrammed computer). It uses a list
structured data base, as expounded by Ling,6 for
storing both information about and relationships be.,
tween graphic entities. This is similar to the "'plex"
structure used by D. Ross in the AED3 system. This
paper purports to contribute to the state-of-the-art by
defining in Backus normal form 7 the class of language
into which graphic statements may be imbedded, and
then defining a language processing scheme that will
translate any statement of this class. A useful feature
of this scheme is that new graphic statements can be
composed at the graphic display causing driving tables
for the language processor to be pro'duced automatically. Thus the language is automatically extendible
within the class described below.
Graphic language
The class of language under scrutiny is a simple
phrase structured grammar. s Statements of the language are of the following form:
Major Word < >,
Minor Word < > Minor Word etc.
723
724 Fall Joint Computer Conference, 1967
The following are examples of some statements in
the language:
Line
Joint ,
Radial Deflection
The language is defined in general terms as follows:
:: =
/
:: =
/
:: = / /
The elements of the terminal vocabulary (denoted by
depends for
definition upon the application and the, specific graphic
hardware. It co,!sists of such things as , or .
Appendix A contains the Backus normal form
language description of the graphic language designed
for a large engineering design analysis system called
"Multishell." Note that in this application members
and joints are graphically just lines and points respectively. They may be defined as simply as:
1. Push "Position" button while pointing light pen
at desired position on the screen
2. Push "Send" button
in which case the line is drawn from the last defined
point to the new light pen position, or as laboriously
as:
1. Point light pen at "Draw Member" menu item
2. Type x, y coordinates of start point
3. Type x, y coordinates of end point
4. Push send button
Note also that statement types (e.g. "Draw Member") are modal (i.e., do not have to be respecified
before each subsequent statement).
Accepting the premise that 'any graphic statement
will be an element of the class described above, we
now attend to defining a language processing scheme
that will translate these statements and compile useful
code (display file) as a result.
Language processor
While it is, in principle, possible to let the input
stream directly invoke the necessary procedures, it
is convenient to interpose a lexical analyzer9 between
the graphic input devices and the procedures themselves. The duties of this lexical analyzer include
isolating identifiers, literals, and the operators and
delimiters of the graphic language. More important,
however, it handles the switching of displayed menus
as the' user makes his selections with the light pen, and
certain graphic manipulations (e.g., light pen tracking,
picture moving, scaling, etc.). It also does some
primitive syntax checking.
Since menu, switching is one of the more significant
duties performed by the lexical analyzer, it is embellished here. In appendix A, the "Case Identification Statement" contains the terminal symbol
"Multishell" followed by a number of "parts." This
statement is implemented as follows:
1. The following menu is displayed on the screen:
SELECT A PROGRAM
ADAM
APT
CYCLE
DYNSAR
MULTISHELL
2. The console user selects MULTISHELL by
pointing the light pen at it.
3. This action by the user causes the lexical
analyzer to delete that menu.
4. The terminal symbol M ultishell is deposited in
the attention file.
5. The following new menu is displayed:
C~E IDENTIFICATION
GO TO TYPEWRITER FOR
FURTHER INSTRUCTIONS
6. The typewriter types
IDENTIFICATION OF THIS CASE *
7. User types the identification code.
8. System user interaction continues until all
"parts" of the case identification statement are
supplied.
The language processor is modularized into two
major subsystems. The first subsystem, the lexical
analyzer, deals with the input language from the
graphic console to a very shallow level. It is concerned only with the words or vocabulary of the
language with little concern for the structure (syntax)
and meaning (semantics) of the language. It recognizes
mputs from the function keys, typewriter, and light
pen, .sorts them out and, where necessary, concatenates them into identifiers, real and integer
literals, and the terminal symbols of the' language.
The second subsystem, the statement subroutines,
is concenled with the syntax and semantics of the
graphic language. A statement subroutine exists for
each statement in the language. It performs the actions
indicated by the semantics of the statement. Many of
the statement subroutines 'perform similar actions
(Le., manipulate or add to the data base, and add items
Graphic Language Translation with a Language Independent Processor
to the display file). Thus the library of subroutines
may conveniently be divided into two classes (i.e.,
the statement subroutines themselves and the service
routines and functions used in common by many of the
subroutines). The statement subroutine may be
thought of as the executive routine for that specific
statement. In terms of language translation it performs
syntactic analysis, code generation (display file), and
the maintenance of a list structured data base. The
service routines are a set of tools used by the statement subroutine in performing its functions. They
'provide a discipline towards generalization. As functions are found to be of common usage they are added
to the service package. A block diagram of the system
is illustrated by Figure 1.
FigJre 1 - System block diagram
The system is a simple feedback system where the
man's input perturbs the system to a change in state
which is reflected by a change in the display. The
state of the machine is kept in the data base and the
display file. The data base is list structured so that
relationships that exist between displayed entities
may be conveniently recorded.
The specific formats of all the data structures (i.e.,
the input queue attention file, data base, and display
file) are machine dependent. However, their contents
and logical structure are outlined here.
Input queue
The input queue receives its input directly from the
graphic console. This is the input stream of characters
to the entire system. There are several types of
characters; function keys, alphanumeric keys, pen
positions, and references to objects "seen" by the
pen. The input stream is typically formatted one
character per computer word with an identification
field in each word to indicate which type of character
it represents. In the interest of clarity and consistency an example will be introduced at this point and
carried on through the description of all the data
structures. The user "draws" a line on the console
by the following actions, assuming the system has
already been placed in the draw line mode:
725
1. typing 1.5, typing comma, typing 2.75,
2. positioning the pen at the line end point, and
pushing the "position" button,
3. pushing the s~atement terminating "send"
button.
This results in the input queue shown in Table I.
TABLE I - Input queue
Identification
Alphanumeric
Alphanumeric
Alphanumeric
Alphanumeric
Alphanumeric
Alphanumeric
Alphanumeric
Alphanumeric
Function Key
Pen Position
Function Key
Data
5
2
7
5
Position
X
y
Send
Attention file
The attention file is the output of the lexical analyzer. It is in a form that is convenient for the statement subroutines. The alphanumeric characters are
concatenated into real numbers, integers, or symbols.
The attention file, that results from lexical analysis
of the input queue example above is illustrated by
Table II.
TABLE II - Attention file
Type
Terminal symbol
Terminal symbol
Real number
Real number
Terminal symbol
Position
Terminal symbol
Data
Line
X Y Coordinate pair
1.5
2.75
Position
XY
Statement Terminator
Data base
The data base is a list structured representation of
the state of the graphic machine at any moment. The
structure is hierarchical in that an item has either
higher, lower, or the same level as any other item. Any
number of relationships between items may exist.
726 Fall Joint Computer Conference, 1967
The data base for the example statement is shown in
Figure 2. The rectangular boxes represent items and
tfte circular ones represent relationships and are
called conjunctions. 6 The rings represent the list
links.
CURRENT
POINT
POINT
3. Recognizes statement termination and as a result causes the appropriate statement subroutine
to be called.
4. Maintains a temporary display file for editing
purposes (points, characters, operator language
guides).
5. Produces as output the attention file (A F) to be
passed along to the statement subroutines.
6. Displays new menus as selections are made.
7. Does some primitive syntax checking.
The fact that the lexical analyzer is required to
know very little about the meaning of the language
it processes, allows it to be written very generally.
It can, in fact, be practically language independent.
This means that adding new language requires no
<. hange in the lexical analyzer itself. Instead appropriate additions are made to its driving tables. Figure
3 shows the lexical analyzer, its associated tables,
and how it fits in with the rest of the system.
Figure 2 - Data base
Display file
ATTENTION
FILE
The display file is the program which drives the
graphic display. It contains such commands as draw
line, draw point, or print character. The display file
that results from our example is shown in Table III.
tABLE III - Display file
Identifier
Position Beam to
Draw Point
Draw Line to
Draw Point
Data
Figure 3 - Lexical analyzer
x
y
x
y
This is the final display file entry that results from our
example. The lexical analyzer, while processing our
input, forms some temporary display file entries e.g.,
the alphanumeric characters, points, etc., but these are
subsequently removed when the statement subroutine
completes its job.
Lexical analyzer
The lexical analyzer has seven major duties.
1. Concatenates literals (real, integer) and symbols.
2. Recognizes terminal symbols. Identifies them as
such so that the proper statement subroutine may
subsequently be called.
The lexical analyzers operation is described as
follows. The lexical analyzer operates between two
ring buffers. It gets its input stream of characters
from the Input Queue. It is driven by the Entry Table
which contains the entries that the lexical analyzer
must make in its output files as a result of each possible input. The specific entry in the Entry Table is
pointed to by either the Character Property Table for
function keys or alphanumeric keys or by the Menu
Table for menu references. The output files that are
driven by the lexical analyzer are the Attention File
and the Display File. The Attention File is the other
ring buffer mentioned above and passes the lexically
analyzed information on to the Statement Subroutines.
Some statements also cause output to be put into the
Display File (i.e., changes in display of menus or
immediate reactions to user actions).
The contents a~d logical structure of the Entry
Table are illustrated below by Table IV.
Graphic Language Translation with a Language Independent Processor
727
The general purpose service subroutines fall into
two classes:
TABLE IV - Entry table
I. The list processing routines are used for creating,
No. of Phrases in this statement
Increment added if this is a phras(;
No. of parts in this phrase
Header
No. of words for Attention File
No. of words for Display File
manipulating (e.g., searching, relating, etc.) and
destroying lists.
2. The display file processing routines are used to
display items and remove items from the display.
Environment
Enable teletype flag
Enable light pen flag
Attention File
Entries
Header
Display File
Entries
The Entry Table is the lexical analyzers key
driving table. The first three words allow the lexical
analyzer to do its primitive syntax che'ck. This consists of checking to see that the statement has the
correct number of phrases and that each phrase has
the correct number of parts. The entries are moved
by the lexical analyzer to the appropriate output
file.
The logic of the Lexical Analyzer is illustrated by
Figure 4.
The proposed environment of the system is described as follows. A small digital computer is placed
at the end of the remote phone line with the graphic
console. It, as well as other remote terminals (e.g.,
teletypes and high speed printer, card reader combinations) communicate with the GE 635 central computer
through voice grade lines at 2.0 kb rate. The GE 635,
operating under the G E Comprehensive Operating
Supervisor and the GE Remote Terminal Supervisor,
provides a multiprogrammed remote terminal environment for the system. The interface between the main
frame and the remote processor is now at the attention file and the display file. That is the input queue,
lexical analyzer, attention file and display file are
located in the remote processor. The statement
subroutines, data base, and attention file are located
in the main frame. With this division of responsibility,
the remote processor does the tasks that require only
a shallow understanding of the problem i.e., the lexical
analysis. The main frame contains the data base and
statement subroutines and does the more detailed
processing. This system is pictured in Figure 6.
Applicationflexibility
Figure 4 - Lexical analyzer logic
Statement subroutines
The statement subroutines consist of the application routines and a package of general purpose
subroutines. A detailed description of all statements
in a specific application is outside the scope of this
paper. However, a flow diagram of the skeleton of a
statement subroutine is illustrated by Figure 5.
One important practical consideration that has not
yet been mentioned is the question of application
flexibility. The lexical analyzer embodies a flexible
table driven translation methodology. However,
coding these tables by hand for every menu of every
application would be a tremendously tedious task.
Therefore, a convenient means of building these
tables needs to be provided.
Ideally, the application programmer would like to
sit at the graphic display and compose his menus. But,
provision must also be made for labeling items in a
menu, cross referencing them to other menus, and
indicating the function code by which the statement
subroutine will recognize the item in the attention
file. A sub language is proposed which uses the lexical
analyzer itself to generate new menus. Of course, the
tables for this sub language must be coded by hand.
But, once the system is thus bootstrapped, new applications can be added easily.
728
Fall Joint Computer Conference, 1967
STATEMENT
SUBROUTI NE
,.
PROCESS
1ST PHRASE
I
PROCESS
NTH PHRASE
PROCESS
STATEMENT
,r
01 SPLAY
RESULTS
RETURN
Figure 5 - Statement subroutines
Graphic Language Translation with a Language Independent Processor
REMOTE COMPUTER
729
routines in the main computer for the application programmer to use to implement his graphic interaction.
action.
ACKNOWLEDGMENTS
The author gratefully acknowledges the many people
whose ideas have contributed to this paper. Chief
among these contributors were A. Dean, M. Ling, and
G. Link.
Figure 6-System Environment
REFERENCES
SUMMARY
The major premise on which this paper is based is
that all graphic statements fall into the class described
earlier. If the potential user of the system will accept
this restriction, his application can be implemented
with a minimum of effort. He must write the statement subroutines, which he would have to do in any
case. Then he must compose the language by which
he will communicate with these subroutines. He
does this graphically at the graphic console. The
software system does not change from application to
application except. for the statement subroutines
and the contents of the lexical analyzer's driving
tables.
Both D. Ross with AED3 and L. Roberts with
extensions to VITAL 10 have taken approaches
similar to that described in this paper. In both cases,
however, graphic language translation ability was
added to existing syntax directed compilers. This
paper presents a translating scheme that is specifically
addressed to translating a broad class of user oriented
languages in a mUlti-computer graphic network. It is
dedicated to the proposition that many specific application oriented languages are superior to one generalized language. I t is based on the premise that the
only things common among these many application
oriented language systems are the lexical analyzer and
a set of service routines. So it proposes a lexical
analyzer in a remote processor and a set of service
2
3
4
5
6
7
8
9
10
I E SUTHERLAND
Sketchpad, a man-machine graphics communication system
SJCC vol 23 Spartan Books Inc Washington D C 1963
W H NINKE
Graphics I -a remote graphical display console system
Proceedings of the FJCC Las Vegas Nevada December
1965
D T ROSS
AED user kit
Massachusetts Institute of Technology, Electronic Systems
Laboratory, various memoranda
E L JACKS
A laboratory for the study of graphical man-machine communication
Proceedings of the FJCC San Francisco California October
27-291964
R NARASIMHAN
Syntax-directed interpretation of classes ofpictures
Comm. ACM, vol 9 no 3, March 1966
T SLING
General Electric reactive display system
Proceedings IEEE Region III Convention, Atlanta, Georgia,
1966
J W BACKUS
The syntax and semantics of the proposed international
language of the Zurich ACM-GAMM conference lCIP
Paris, France. June 1959
CHOMSKY
On certain formal properties of grammars
Information & Control no 2 vol 2, 1959
T E CHEATHAM,JR.
Notes on compiling techniques
University of Michigan, Summer Conference Course on
Automatic Programming, June 1966
L G ROBERTS
A graphical service system with variable syntax
Comm. ACM, vol 9 no 3, March 1966
730
Fall Joint Computer Conference, 1967
Appendix A
Multishell statement definitions
General
:: = Send
:: ~
:: = I
:: = Send I Send
:: = Send I Send
Case identification
:: = Multishell
:: =
:: =
:: =
:: =
:: =
:: =
:: =
Structure drawing
:: = Draw Member I
No more than two point parts
:: = I
:: = I